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jairov4/accel-oil | solution_spartan6/syn/vhdl/nfa_accept_samples_generic_hw_add_14ns_14ns_14_4.vhd | 3 | 9,512 | -- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2013.4
-- Copyright (C) 2013 Xilinx Inc. All rights reserved.
--
-- ==============================================================
library IEEE;
use IEEE.std_logic_1164.all;
use ieee.std_logic_arith.all;
entity nfa_accept_samples_generic_hw_add_14ns_14ns_14_4_AddSubnS_4 is
port (
clk: in std_logic;
reset: in std_logic;
ce: in std_logic;
a: in std_logic_vector(13 downto 0);
b: in std_logic_vector(13 downto 0);
s: out std_logic_vector(13 downto 0));
end entity;
architecture behav of nfa_accept_samples_generic_hw_add_14ns_14ns_14_4_AddSubnS_4 is
component nfa_accept_samples_generic_hw_add_14ns_14ns_14_4_AddSubnS_4_fadder is
port (
faa : IN STD_LOGIC_VECTOR (4-1 downto 0);
fab : IN STD_LOGIC_VECTOR (4-1 downto 0);
facin : IN STD_LOGIC_VECTOR (0 downto 0);
fas : OUT STD_LOGIC_VECTOR (4-1 downto 0);
facout : OUT STD_LOGIC_VECTOR (0 downto 0));
end component;
component nfa_accept_samples_generic_hw_add_14ns_14ns_14_4_AddSubnS_4_fadder_f is
port (
faa : IN STD_LOGIC_VECTOR (2-1 downto 0);
fab : IN STD_LOGIC_VECTOR (2-1 downto 0);
facin : IN STD_LOGIC_VECTOR (0 downto 0);
fas : OUT STD_LOGIC_VECTOR (2-1 downto 0);
facout : OUT STD_LOGIC_VECTOR (0 downto 0));
end component;
-- ---- register and wire type variables list here ----
-- wire for the primary inputs
signal a_reg : std_logic_vector(13 downto 0);
signal b_reg : std_logic_vector(13 downto 0);
-- wires for each small adder
signal a0_cb : std_logic_vector(3 downto 0);
signal b0_cb : std_logic_vector(3 downto 0);
signal a1_cb : std_logic_vector(7 downto 4);
signal b1_cb : std_logic_vector(7 downto 4);
signal a2_cb : std_logic_vector(11 downto 8);
signal b2_cb : std_logic_vector(11 downto 8);
signal a3_cb : std_logic_vector(13 downto 12);
signal b3_cb : std_logic_vector(13 downto 12);
-- registers for input register array
type ramtypei0 is array (0 downto 0) of std_logic_vector(3 downto 0);
signal a1_cb_regi1 : ramtypei0;
signal b1_cb_regi1 : ramtypei0;
type ramtypei1 is array (1 downto 0) of std_logic_vector(3 downto 0);
signal a2_cb_regi2 : ramtypei1;
signal b2_cb_regi2 : ramtypei1;
type ramtypei2 is array (2 downto 0) of std_logic_vector(1 downto 0);
signal a3_cb_regi3 : ramtypei2;
signal b3_cb_regi3 : ramtypei2;
-- wires for each full adder sum
signal fas : std_logic_vector(13 downto 0);
-- wires and register for carry out bit
signal faccout_ini : std_logic_vector (0 downto 0);
signal faccout0_co0 : std_logic_vector (0 downto 0);
signal faccout1_co1 : std_logic_vector (0 downto 0);
signal faccout2_co2 : std_logic_vector (0 downto 0);
signal faccout3_co3 : std_logic_vector (0 downto 0);
signal faccout0_co0_reg : std_logic_vector (0 downto 0);
signal faccout1_co1_reg : std_logic_vector (0 downto 0);
signal faccout2_co2_reg : std_logic_vector (0 downto 0);
-- registers for output register array
type ramtypeo2 is array (2 downto 0) of std_logic_vector(3 downto 0);
signal s0_ca_rego0 : ramtypeo2;
type ramtypeo1 is array (1 downto 0) of std_logic_vector(3 downto 0);
signal s1_ca_rego1 : ramtypeo1;
type ramtypeo0 is array (0 downto 0) of std_logic_vector(3 downto 0);
signal s2_ca_rego2 : ramtypeo0;
-- wire for the temporary output
signal s_tmp : std_logic_vector(13 downto 0);
-- ---- RTL code for assignment statements/always blocks/module instantiations here ----
begin
a_reg <= a;
b_reg <= b;
-- small adder input assigments
a0_cb <= a_reg(3 downto 0);
b0_cb <= b_reg(3 downto 0);
a1_cb <= a_reg(7 downto 4);
b1_cb <= b_reg(7 downto 4);
a2_cb <= a_reg(11 downto 8);
b2_cb <= b_reg(11 downto 8);
a3_cb <= a_reg(13 downto 12);
b3_cb <= b_reg(13 downto 12);
-- input register array
process (clk)
begin
if (clk'event and clk='1') then
if (ce='1') then
a1_cb_regi1 (0) <= a1_cb;
b1_cb_regi1 (0) <= b1_cb;
a2_cb_regi2 (0) <= a2_cb;
b2_cb_regi2 (0) <= b2_cb;
a3_cb_regi3 (0) <= a3_cb;
b3_cb_regi3 (0) <= b3_cb;
a2_cb_regi2 (1) <= a2_cb_regi2 (0);
b2_cb_regi2 (1) <= b2_cb_regi2 (0);
a3_cb_regi3 (1) <= a3_cb_regi3 (0);
b3_cb_regi3 (1) <= b3_cb_regi3 (0);
a3_cb_regi3 (2) <= a3_cb_regi3 (1);
b3_cb_regi3 (2) <= b3_cb_regi3 (1);
end if;
end if;
end process;
-- carry out bit processing
process (clk)
begin
if (clk'event and clk='1') then
if (ce='1') then
faccout0_co0_reg <= faccout0_co0;
faccout1_co1_reg <= faccout1_co1;
faccout2_co2_reg <= faccout2_co2;
end if;
end if;
end process;
-- small adder generation
u0 : nfa_accept_samples_generic_hw_add_14ns_14ns_14_4_AddSubnS_4_fadder
port map
(faa => a0_cb,
fab => b0_cb,
facin => faccout_ini,
fas => fas(3 downto 0),
facout => faccout0_co0);
u1 : nfa_accept_samples_generic_hw_add_14ns_14ns_14_4_AddSubnS_4_fadder
port map
(faa => a1_cb_regi1(0),
fab => b1_cb_regi1(0),
facin => faccout0_co0_reg,
fas => fas(7 downto 4),
facout => faccout1_co1);
u2 : nfa_accept_samples_generic_hw_add_14ns_14ns_14_4_AddSubnS_4_fadder
port map
(faa => a2_cb_regi2(1),
fab => b2_cb_regi2(1),
facin => faccout1_co1_reg,
fas => fas(11 downto 8),
facout => faccout2_co2);
u3 : nfa_accept_samples_generic_hw_add_14ns_14ns_14_4_AddSubnS_4_fadder_f
port map
(faa => a3_cb_regi3(2),
fab => b3_cb_regi3(2),
facin => faccout2_co2_reg,
fas => fas(13 downto 12),
facout => faccout3_co3);
faccout_ini <= "0";
-- output register array
process (clk)
begin
if (clk'event and clk='1') then
if (ce='1') then
s0_ca_rego0 (0) <= fas(3 downto 0);
s1_ca_rego1 (0) <= fas(7 downto 4);
s2_ca_rego2 (0) <= fas(11 downto 8);
s0_ca_rego0 (1) <= s0_ca_rego0 (0);
s0_ca_rego0 (2) <= s0_ca_rego0 (1);
s1_ca_rego1 (1) <= s1_ca_rego1 (0);
end if;
end if;
end process;
-- get the s_tmp, assign it to the primary output
s_tmp(3 downto 0) <= s0_ca_rego0(2);
s_tmp(7 downto 4) <= s1_ca_rego1(1);
s_tmp(11 downto 8) <= s2_ca_rego2(0);
s_tmp(13 downto 12) <= fas(13 downto 12);
s <= s_tmp;
end architecture;
-- short adder
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity nfa_accept_samples_generic_hw_add_14ns_14ns_14_4_AddSubnS_4_fadder is
generic(N : natural :=4);
port (
faa : IN STD_LOGIC_VECTOR (N-1 downto 0);
fab : IN STD_LOGIC_VECTOR (N-1 downto 0);
facin : IN STD_LOGIC_VECTOR (0 downto 0);
fas : OUT STD_LOGIC_VECTOR (N-1 downto 0);
facout : OUT STD_LOGIC_VECTOR (0 downto 0));
end;
architecture behav of nfa_accept_samples_generic_hw_add_14ns_14ns_14_4_AddSubnS_4_fadder is
signal tmp : STD_LOGIC_VECTOR (N downto 0);
begin
tmp <= std_logic_vector(unsigned(std_logic_vector(unsigned(std_logic_vector(resize(unsigned(faa),N+1))) + unsigned(fab))) + unsigned(facin));
fas <= tmp(N-1 downto 0 );
facout <= tmp(N downto N);
end behav;
-- the final stage short adder
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity nfa_accept_samples_generic_hw_add_14ns_14ns_14_4_AddSubnS_4_fadder_f is
generic(N : natural :=2);
port (
faa : IN STD_LOGIC_VECTOR (N-1 downto 0);
fab : IN STD_LOGIC_VECTOR (N-1 downto 0);
facin : IN STD_LOGIC_VECTOR (0 downto 0);
fas : OUT STD_LOGIC_VECTOR (N-1 downto 0);
facout : OUT STD_LOGIC_VECTOR (0 downto 0));
end;
architecture behav of nfa_accept_samples_generic_hw_add_14ns_14ns_14_4_AddSubnS_4_fadder_f is
signal tmp : STD_LOGIC_VECTOR (N downto 0);
begin
tmp <= std_logic_vector(unsigned(std_logic_vector(unsigned(std_logic_vector(resize(unsigned(faa),N+1))) + unsigned(fab))) + unsigned(facin));
fas <= tmp(N-1 downto 0 );
facout <= tmp(N downto N);
end behav;
Library IEEE;
use IEEE.std_logic_1164.all;
entity nfa_accept_samples_generic_hw_add_14ns_14ns_14_4 is
generic (
ID : INTEGER;
NUM_STAGE : INTEGER;
din0_WIDTH : INTEGER;
din1_WIDTH : INTEGER;
dout_WIDTH : INTEGER);
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
ce : IN STD_LOGIC;
din0 : IN STD_LOGIC_VECTOR(din0_WIDTH - 1 DOWNTO 0);
din1 : IN STD_LOGIC_VECTOR(din1_WIDTH - 1 DOWNTO 0);
dout : OUT STD_LOGIC_VECTOR(dout_WIDTH - 1 DOWNTO 0));
end entity;
architecture arch of nfa_accept_samples_generic_hw_add_14ns_14ns_14_4 is
component nfa_accept_samples_generic_hw_add_14ns_14ns_14_4_AddSubnS_4 is
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
ce : IN STD_LOGIC;
a : IN STD_LOGIC_VECTOR;
b : IN STD_LOGIC_VECTOR;
s : OUT STD_LOGIC_VECTOR);
end component;
begin
nfa_accept_samples_generic_hw_add_14ns_14ns_14_4_AddSubnS_4_U : component nfa_accept_samples_generic_hw_add_14ns_14ns_14_4_AddSubnS_4
port map (
clk => clk,
reset => reset,
ce => ce,
a => din0,
b => din1,
s => dout);
end architecture;
| lgpl-3.0 | ff1db8af914856a76f0a01cbf1f2078e | 0.608705 | 2.867651 | false | false | false | false |
jairov4/accel-oil | impl/impl_test_pcie/hdl/system_ac0_mb_bridge_wrapper.vhd | 1 | 11,046 | -------------------------------------------------------------------------------
-- system_ac0_mb_bridge_wrapper.vhd
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
library plbv46_plbv46_bridge_v1_04_a;
use plbv46_plbv46_bridge_v1_04_a.all;
entity system_ac0_mb_bridge_wrapper is
port (
SPLB_Clk : in std_logic;
SPLB_Rst : in std_logic;
IP2INTC_Irpt : out std_logic;
PLB_ABus : in std_logic_vector(0 to 31);
PLB_UABus : in std_logic_vector(0 to 31);
PLB_PAValid : in std_logic;
PLB_SAValid : in std_logic;
PLB_rdPrim : in std_logic;
PLB_wrPrim : in std_logic;
PLB_masterID : in std_logic_vector(0 to 3);
PLB_abort : in std_logic;
PLB_busLock : in std_logic;
PLB_RNW : in std_logic;
PLB_BE : in std_logic_vector(0 to 7);
PLB_MSize : in std_logic_vector(0 to 1);
PLB_size : in std_logic_vector(0 to 3);
PLB_type : in std_logic_vector(0 to 2);
PLB_lockErr : in std_logic;
PLB_wrDBus : in std_logic_vector(0 to 63);
PLB_wrBurst : in std_logic;
PLB_rdBurst : in std_logic;
PLB_wrPendReq : in std_logic;
PLB_rdPendReq : in std_logic;
PLB_wrPendPri : in std_logic_vector(0 to 1);
PLB_rdPendPri : in std_logic_vector(0 to 1);
PLB_reqPri : in std_logic_vector(0 to 1);
PLB_TAttribute : in std_logic_vector(0 to 15);
Sl_addrAck : out std_logic;
Sl_SSize : out std_logic_vector(0 to 1);
Sl_wait : out std_logic;
Sl_rearbitrate : out std_logic;
Sl_wrDAck : out std_logic;
Sl_wrComp : out std_logic;
Sl_wrBTerm : out std_logic;
Sl_rdDBus : out std_logic_vector(0 to 63);
Sl_rdWdAddr : out std_logic_vector(0 to 3);
Sl_rdDAck : out std_logic;
Sl_rdComp : out std_logic;
Sl_rdBTerm : out std_logic;
Sl_MBusy : out std_logic_vector(0 to 14);
Sl_MWrErr : out std_logic_vector(0 to 14);
Sl_MRdErr : out std_logic_vector(0 to 14);
Sl_MIRQ : out std_logic_vector(0 to 14);
MPLB_Clk : in std_logic;
MPLB_Rst : in std_logic;
M_request : out std_logic;
M_priority : out std_logic_vector(0 to 1);
M_busLock : out std_logic;
M_RNW : out std_logic;
M_BE : out std_logic_vector(0 to 7);
M_MSize : out std_logic_vector(0 to 1);
M_size : out std_logic_vector(0 to 3);
M_type : out std_logic_vector(0 to 2);
M_ABus : out std_logic_vector(0 to 31);
M_wrBurst : out std_logic;
M_rdBurst : out std_logic;
M_wrDBus : out std_logic_vector(0 to 63);
PLB_MAddrAck : in std_logic;
PLB_MSSize : in std_logic_vector(0 to 1);
PLB_MRearbitrate : in std_logic;
PLB_MTimeout : in std_logic;
PLB_MRdErr : in std_logic;
PLB_MWrErr : in std_logic;
PLB_MRdDBus : in std_logic_vector(0 to 63);
PLB_MRdDAck : in std_logic;
PLB_MRdBTerm : in std_logic;
PLB_MWrDAck : in std_logic;
PLB_MWrBTerm : in std_logic;
M_TAttribute : out std_logic_vector(0 to 15);
M_lockErr : out std_logic;
M_abort : out std_logic;
M_UABus : out std_logic_vector(0 to 31);
PLB_MBusy : in std_logic;
PLB_MIRQ : in std_logic;
PLB_MRdWdAddr : in std_logic_vector(0 to 3)
);
attribute x_core_info : STRING;
attribute x_core_info of system_ac0_mb_bridge_wrapper : entity is "plbv46_plbv46_bridge_v1_04_a";
end system_ac0_mb_bridge_wrapper;
architecture STRUCTURE of system_ac0_mb_bridge_wrapper is
component plbv46_plbv46_bridge is
generic (
C_NUM_ADDR_RNG : INTEGER;
C_BRIDGE_BASEADDR : std_logic_vector;
C_BRIDGE_HIGHADDR : std_logic_vector;
C_RNG0_BASEADDR : std_logic_vector;
C_RNG0_HIGHADDR : std_logic_vector;
C_RNG1_BASEADDR : std_logic_vector;
C_RNG1_HIGHADDR : std_logic_vector;
C_RNG2_BASEADDR : std_logic_vector;
C_RNG2_HIGHADDR : std_logic_vector;
C_RNG3_BASEADDR : std_logic_vector;
C_RNG3_HIGHADDR : std_logic_vector;
C_SPLB_P2P : INTEGER;
C_SPLB_MID_WIDTH : INTEGER;
C_SPLB_NUM_MASTERS : INTEGER;
C_SPLB_SMALLEST_MASTER : INTEGER;
C_SPLB_BIGGEST_MASTER : INTEGER;
C_SPLB_AWIDTH : INTEGER;
C_SPLB_DWIDTH : INTEGER;
C_MPLB_AWIDTH : INTEGER;
C_MPLB_DWIDTH : INTEGER;
C_SPLB_NATIVE_DWIDTH : INTEGER;
C_MPLB_NATIVE_DWIDTH : INTEGER;
C_MPLB_SMALLEST_SLAVE : INTEGER;
C_BUS_CLOCK_RATIO : INTEGER;
C_PREFETCH_TIMEOUT : INTEGER;
C_FAMILY : STRING
);
port (
SPLB_Clk : in std_logic;
SPLB_Rst : in std_logic;
IP2INTC_Irpt : out std_logic;
PLB_ABus : in std_logic_vector(0 to C_SPLB_AWIDTH-1);
PLB_UABus : in std_logic_vector(0 to C_SPLB_AWIDTH-1);
PLB_PAValid : in std_logic;
PLB_SAValid : in std_logic;
PLB_rdPrim : in std_logic;
PLB_wrPrim : in std_logic;
PLB_masterID : in std_logic_vector(0 to (C_SPLB_MID_WIDTH-1));
PLB_abort : in std_logic;
PLB_busLock : in std_logic;
PLB_RNW : in std_logic;
PLB_BE : in std_logic_vector(0 to ((C_SPLB_DWIDTH/8)-1));
PLB_MSize : in std_logic_vector(0 to 1);
PLB_size : in std_logic_vector(0 to 3);
PLB_type : in std_logic_vector(0 to 2);
PLB_lockErr : in std_logic;
PLB_wrDBus : in std_logic_vector(0 to (C_SPLB_DWIDTH-1));
PLB_wrBurst : in std_logic;
PLB_rdBurst : in std_logic;
PLB_wrPendReq : in std_logic;
PLB_rdPendReq : in std_logic;
PLB_wrPendPri : in std_logic_vector(0 to 1);
PLB_rdPendPri : in std_logic_vector(0 to 1);
PLB_reqPri : in std_logic_vector(0 to 1);
PLB_TAttribute : in std_logic_vector(0 to 15);
Sl_addrAck : out std_logic;
Sl_SSize : out std_logic_vector(0 to 1);
Sl_wait : out std_logic;
Sl_rearbitrate : out std_logic;
Sl_wrDAck : out std_logic;
Sl_wrComp : out std_logic;
Sl_wrBTerm : out std_logic;
Sl_rdDBus : out std_logic_vector(0 to (C_SPLB_DWIDTH-1));
Sl_rdWdAddr : out std_logic_vector(0 to 3);
Sl_rdDAck : out std_logic;
Sl_rdComp : out std_logic;
Sl_rdBTerm : out std_logic;
Sl_MBusy : out std_logic_vector(0 to (C_SPLB_NUM_MASTERS-1));
Sl_MWrErr : out std_logic_vector(0 to (C_SPLB_NUM_MASTERS-1));
Sl_MRdErr : out std_logic_vector(0 to (C_SPLB_NUM_MASTERS-1));
Sl_MIRQ : out std_logic_vector(0 to (C_SPLB_NUM_MASTERS-1));
MPLB_Clk : in std_logic;
MPLB_Rst : in std_logic;
M_request : out std_logic;
M_priority : out std_logic_vector(0 to 1);
M_busLock : out std_logic;
M_RNW : out std_logic;
M_BE : out std_logic_vector(0 to ((C_MPLB_DWIDTH/8)-1));
M_MSize : out std_logic_vector(0 to 1);
M_size : out std_logic_vector(0 to 3);
M_type : out std_logic_vector(0 to 2);
M_ABus : out std_logic_vector(0 to C_MPLB_AWIDTH-1);
M_wrBurst : out std_logic;
M_rdBurst : out std_logic;
M_wrDBus : out std_logic_vector(0 to (C_MPLB_DWIDTH-1));
PLB_MAddrAck : in std_logic;
PLB_MSSize : in std_logic_vector(0 to 1);
PLB_MRearbitrate : in std_logic;
PLB_MTimeout : in std_logic;
PLB_MRdErr : in std_logic;
PLB_MWrErr : in std_logic;
PLB_MRdDBus : in std_logic_vector(0 to (C_MPLB_DWIDTH-1));
PLB_MRdDAck : in std_logic;
PLB_MRdBTerm : in std_logic;
PLB_MWrDAck : in std_logic;
PLB_MWrBTerm : in std_logic;
M_TAttribute : out std_logic_vector(0 to 15);
M_lockErr : out std_logic;
M_abort : out std_logic;
M_UABus : out std_logic_vector(0 to C_MPLB_AWIDTH-1);
PLB_MBusy : in std_logic;
PLB_MIRQ : in std_logic;
PLB_MRdWdAddr : in std_logic_vector(0 to 3)
);
end component;
begin
ac0_mb_bridge : plbv46_plbv46_bridge
generic map (
C_NUM_ADDR_RNG => 1,
C_BRIDGE_BASEADDR => X"00000000",
C_BRIDGE_HIGHADDR => X"FFFFFFFF",
C_RNG0_BASEADDR => X"00000000",
C_RNG0_HIGHADDR => X"FFFFFFFF",
C_RNG1_BASEADDR => X"ffffffff",
C_RNG1_HIGHADDR => X"00000000",
C_RNG2_BASEADDR => X"ffffffff",
C_RNG2_HIGHADDR => X"00000000",
C_RNG3_BASEADDR => X"ffffffff",
C_RNG3_HIGHADDR => X"00000000",
C_SPLB_P2P => 0,
C_SPLB_MID_WIDTH => 4,
C_SPLB_NUM_MASTERS => 15,
C_SPLB_SMALLEST_MASTER => 64,
C_SPLB_BIGGEST_MASTER => 32,
C_SPLB_AWIDTH => 32,
C_SPLB_DWIDTH => 64,
C_MPLB_AWIDTH => 32,
C_MPLB_DWIDTH => 64,
C_SPLB_NATIVE_DWIDTH => 32,
C_MPLB_NATIVE_DWIDTH => 32,
C_MPLB_SMALLEST_SLAVE => 32,
C_BUS_CLOCK_RATIO => 1,
C_PREFETCH_TIMEOUT => 10,
C_FAMILY => "virtex5"
)
port map (
SPLB_Clk => SPLB_Clk,
SPLB_Rst => SPLB_Rst,
IP2INTC_Irpt => IP2INTC_Irpt,
PLB_ABus => PLB_ABus,
PLB_UABus => PLB_UABus,
PLB_PAValid => PLB_PAValid,
PLB_SAValid => PLB_SAValid,
PLB_rdPrim => PLB_rdPrim,
PLB_wrPrim => PLB_wrPrim,
PLB_masterID => PLB_masterID,
PLB_abort => PLB_abort,
PLB_busLock => PLB_busLock,
PLB_RNW => PLB_RNW,
PLB_BE => PLB_BE,
PLB_MSize => PLB_MSize,
PLB_size => PLB_size,
PLB_type => PLB_type,
PLB_lockErr => PLB_lockErr,
PLB_wrDBus => PLB_wrDBus,
PLB_wrBurst => PLB_wrBurst,
PLB_rdBurst => PLB_rdBurst,
PLB_wrPendReq => PLB_wrPendReq,
PLB_rdPendReq => PLB_rdPendReq,
PLB_wrPendPri => PLB_wrPendPri,
PLB_rdPendPri => PLB_rdPendPri,
PLB_reqPri => PLB_reqPri,
PLB_TAttribute => PLB_TAttribute,
Sl_addrAck => Sl_addrAck,
Sl_SSize => Sl_SSize,
Sl_wait => Sl_wait,
Sl_rearbitrate => Sl_rearbitrate,
Sl_wrDAck => Sl_wrDAck,
Sl_wrComp => Sl_wrComp,
Sl_wrBTerm => Sl_wrBTerm,
Sl_rdDBus => Sl_rdDBus,
Sl_rdWdAddr => Sl_rdWdAddr,
Sl_rdDAck => Sl_rdDAck,
Sl_rdComp => Sl_rdComp,
Sl_rdBTerm => Sl_rdBTerm,
Sl_MBusy => Sl_MBusy,
Sl_MWrErr => Sl_MWrErr,
Sl_MRdErr => Sl_MRdErr,
Sl_MIRQ => Sl_MIRQ,
MPLB_Clk => MPLB_Clk,
MPLB_Rst => MPLB_Rst,
M_request => M_request,
M_priority => M_priority,
M_busLock => M_busLock,
M_RNW => M_RNW,
M_BE => M_BE,
M_MSize => M_MSize,
M_size => M_size,
M_type => M_type,
M_ABus => M_ABus,
M_wrBurst => M_wrBurst,
M_rdBurst => M_rdBurst,
M_wrDBus => M_wrDBus,
PLB_MAddrAck => PLB_MAddrAck,
PLB_MSSize => PLB_MSSize,
PLB_MRearbitrate => PLB_MRearbitrate,
PLB_MTimeout => PLB_MTimeout,
PLB_MRdErr => PLB_MRdErr,
PLB_MWrErr => PLB_MWrErr,
PLB_MRdDBus => PLB_MRdDBus,
PLB_MRdDAck => PLB_MRdDAck,
PLB_MRdBTerm => PLB_MRdBTerm,
PLB_MWrDAck => PLB_MWrDAck,
PLB_MWrBTerm => PLB_MWrBTerm,
M_TAttribute => M_TAttribute,
M_lockErr => M_lockErr,
M_abort => M_abort,
M_UABus => M_UABus,
PLB_MBusy => PLB_MBusy,
PLB_MIRQ => PLB_MIRQ,
PLB_MRdWdAddr => PLB_MRdWdAddr
);
end architecture STRUCTURE;
| lgpl-3.0 | 4e1602ec6f50372c3643700ab6f39cb3 | 0.591707 | 3.16142 | false | false | false | false |
grwlf/vsim | vhdl_ct/ct00561.vhd | 1 | 18,794 | -- NEED RESULT: ARCH00561: Aliasing - scalar static subtypes passed
-------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
-------------------------------------------------------------------------------
--
-- TEST NAME:
--
-- CT00561
--
-- AUTHOR:
--
-- A. Wilmot
--
-- TEST OBJECTIVES:
--
-- 4.3.4 (1)
-- 4.3.4 (2)
-- 4.3.4 (9)
-- 4.3.4 (10)
--
-- DESIGN UNIT ORDERING:
--
-- E00000(ARCH00561)
-- ENT00561_Test_Bench(ARCH00561_Test_Bench)
--
-- REVISION HISTORY:
--
-- 19-AUG-1987 - initial revision
--
-- NOTES:
--
-- self-checking
-- automatically generated
--
use WORK.STANDARD_TYPES.all ;
architecture ARCH00561 of E00000 is
constant co_boolean_1 : boolean
:= c_boolean_1 ;
constant co_bit_1 : bit
:= c_bit_1 ;
constant co_severity_level_1 : severity_level
:= c_severity_level_1 ;
constant co_character_1 : character
:= c_character_1 ;
constant co_t_enum1_1 : t_enum1
:= c_t_enum1_1 ;
constant co_st_enum1_1 : st_enum1
:= c_st_enum1_1 ;
constant co_integer_1 : integer
:= c_integer_1 ;
constant co_t_int1_1 : t_int1
:= c_t_int1_1 ;
constant co_st_int1_1 : st_int1
:= c_st_int1_1 ;
constant co_time_1 : time
:= c_time_1 ;
constant co_t_phys1_1 : t_phys1
:= c_t_phys1_1 ;
constant co_st_phys1_1 : st_phys1
:= c_st_phys1_1 ;
constant co_real_1 : real
:= c_real_1 ;
constant co_t_real1_1 : t_real1
:= c_t_real1_1 ;
constant co_st_real1_1 : st_real1
:= c_st_real1_1 ;
signal si_boolean_1 : boolean
:= c_boolean_1 ;
signal si_bit_1 : bit
:= c_bit_1 ;
signal si_severity_level_1 : severity_level
:= c_severity_level_1 ;
signal si_character_1 : character
:= c_character_1 ;
signal si_t_enum1_1 : t_enum1
:= c_t_enum1_1 ;
signal si_st_enum1_1 : st_enum1
:= c_st_enum1_1 ;
signal si_integer_1 : integer
:= c_integer_1 ;
signal si_t_int1_1 : t_int1
:= c_t_int1_1 ;
signal si_st_int1_1 : st_int1
:= c_st_int1_1 ;
signal si_time_1 : time
:= c_time_1 ;
signal si_t_phys1_1 : t_phys1
:= c_t_phys1_1 ;
signal si_st_phys1_1 : st_phys1
:= c_st_phys1_1 ;
signal si_real_1 : real
:= c_real_1 ;
signal si_t_real1_1 : t_real1
:= c_t_real1_1 ;
signal si_st_real1_1 : st_real1
:= c_st_real1_1 ;
alias as_boolean_1 : boolean
is si_boolean_1 ;
alias as_bit_1 : bit
is si_bit_1 ;
alias as_severity_level_1 : severity_level
is si_severity_level_1 ;
alias as_character_1 : character
is si_character_1 ;
alias as_t_enum1_1 : t_enum1
is si_t_enum1_1 ;
alias as_st_enum1_1 : st_enum1
is si_st_enum1_1 ;
alias as_integer_1 : integer
is si_integer_1 ;
alias as_t_int1_1 : t_int1
is si_t_int1_1 ;
alias as_st_int1_1 : st_int1
is si_st_int1_1 ;
alias as_time_1 : time
is si_time_1 ;
alias as_t_phys1_1 : t_phys1
is si_t_phys1_1 ;
alias as_st_phys1_1 : st_phys1
is si_st_phys1_1 ;
alias as_real_1 : real
is si_real_1 ;
alias as_t_real1_1 : t_real1
is si_t_real1_1 ;
alias as_st_real1_1 : st_real1
is si_st_real1_1 ;
type test is (initial, intermediate, final) ;
signal synch : test := initial ;
signal s_correct1 : boolean ;
signal s_correct2 : boolean ;
begin
process
variable correct : boolean := true ;
begin
if synch = initial then
correct := correct and as_boolean_1 = c_boolean_1 ;
correct := correct and as_bit_1 = c_bit_1 ;
correct := correct and as_severity_level_1 = c_severity_level_1 ;
correct := correct and as_character_1 = c_character_1 ;
correct := correct and as_t_enum1_1 = c_t_enum1_1 ;
correct := correct and as_st_enum1_1 = c_st_enum1_1 ;
correct := correct and as_integer_1 = c_integer_1 ;
correct := correct and as_t_int1_1 = c_t_int1_1 ;
correct := correct and as_st_int1_1 = c_st_int1_1 ;
correct := correct and as_time_1 = c_time_1 ;
correct := correct and as_t_phys1_1 = c_t_phys1_1 ;
correct := correct and as_st_phys1_1 = c_st_phys1_1 ;
correct := correct and as_real_1 = c_real_1 ;
correct := correct and as_t_real1_1 = c_t_real1_1 ;
correct := correct and as_st_real1_1 = c_st_real1_1 ;
si_boolean_1 <= c_boolean_2 ;
si_bit_1 <= c_bit_2 ;
si_severity_level_1 <= c_severity_level_2 ;
si_character_1 <= c_character_2 ;
si_t_enum1_1 <= c_t_enum1_2 ;
si_st_enum1_1 <= c_st_enum1_2 ;
si_integer_1 <= c_integer_2 ;
si_t_int1_1 <= c_t_int1_2 ;
si_st_int1_1 <= c_st_int1_2 ;
si_time_1 <= c_time_2 ;
si_t_phys1_1 <= c_t_phys1_2 ;
si_st_phys1_1 <= c_st_phys1_2 ;
si_real_1 <= c_real_2 ;
si_t_real1_1 <= c_t_real1_2 ;
si_st_real1_1 <= c_st_real1_2 ;
synch <= intermediate ;
as_boolean_1 <= transport c_boolean_1 after 1 ns ;
as_bit_1 <= transport c_bit_1 after 1 ns ;
as_severity_level_1 <= transport c_severity_level_1 after 1 ns ;
as_character_1 <= transport c_character_1 after 1 ns ;
as_t_enum1_1 <= transport c_t_enum1_1 after 1 ns ;
as_st_enum1_1 <= transport c_st_enum1_1 after 1 ns ;
as_integer_1 <= transport c_integer_1 after 1 ns ;
as_t_int1_1 <= transport c_t_int1_1 after 1 ns ;
as_st_int1_1 <= transport c_st_int1_1 after 1 ns ;
as_time_1 <= transport c_time_1 after 1 ns ;
as_t_phys1_1 <= transport c_t_phys1_1 after 1 ns ;
as_st_phys1_1 <= transport c_st_phys1_1 after 1 ns ;
as_real_1 <= transport c_real_1 after 1 ns ;
as_t_real1_1 <= transport c_t_real1_1 after 1 ns ;
as_st_real1_1 <= transport c_st_real1_1 after 1 ns ;
synch <= transport final after 1 ns ;
s_correct1 <= correct ;
end if ;
wait ;
end process ;
process (synch)
procedure p1 is
variable correct : boolean ;
variable va_boolean_1 : boolean
:= c_boolean_1 ;
variable va_bit_1 : bit
:= c_bit_1 ;
variable va_severity_level_1 : severity_level
:= c_severity_level_1 ;
variable va_character_1 : character
:= c_character_1 ;
variable va_t_enum1_1 : t_enum1
:= c_t_enum1_1 ;
variable va_st_enum1_1 : st_enum1
:= c_st_enum1_1 ;
variable va_integer_1 : integer
:= c_integer_1 ;
variable va_t_int1_1 : t_int1
:= c_t_int1_1 ;
variable va_st_int1_1 : st_int1
:= c_st_int1_1 ;
variable va_time_1 : time
:= c_time_1 ;
variable va_t_phys1_1 : t_phys1
:= c_t_phys1_1 ;
variable va_st_phys1_1 : st_phys1
:= c_st_phys1_1 ;
variable va_real_1 : real
:= c_real_1 ;
variable va_t_real1_1 : t_real1
:= c_t_real1_1 ;
variable va_st_real1_1 : st_real1
:= c_st_real1_1 ;
alias ac_boolean_1 : boolean
is co_boolean_1 ;
alias ac_bit_1 : bit
is co_bit_1 ;
alias ac_severity_level_1 : severity_level
is co_severity_level_1 ;
alias ac_character_1 : character
is co_character_1 ;
alias ac_t_enum1_1 : t_enum1
is co_t_enum1_1 ;
alias ac_st_enum1_1 : st_enum1
is co_st_enum1_1 ;
alias ac_integer_1 : integer
is co_integer_1 ;
alias ac_t_int1_1 : t_int1
is co_t_int1_1 ;
alias ac_st_int1_1 : st_int1
is co_st_int1_1 ;
alias ac_time_1 : time
is co_time_1 ;
alias ac_t_phys1_1 : t_phys1
is co_t_phys1_1 ;
alias ac_st_phys1_1 : st_phys1
is co_st_phys1_1 ;
alias ac_real_1 : real
is co_real_1 ;
alias ac_t_real1_1 : t_real1
is co_t_real1_1 ;
alias ac_st_real1_1 : st_real1
is co_st_real1_1 ;
alias av_boolean_1 : boolean
is va_boolean_1 ;
alias av_bit_1 : bit
is va_bit_1 ;
alias av_severity_level_1 : severity_level
is va_severity_level_1 ;
alias av_character_1 : character
is va_character_1 ;
alias av_t_enum1_1 : t_enum1
is va_t_enum1_1 ;
alias av_st_enum1_1 : st_enum1
is va_st_enum1_1 ;
alias av_integer_1 : integer
is va_integer_1 ;
alias av_t_int1_1 : t_int1
is va_t_int1_1 ;
alias av_st_int1_1 : st_int1
is va_st_int1_1 ;
alias av_time_1 : time
is va_time_1 ;
alias av_t_phys1_1 : t_phys1
is va_t_phys1_1 ;
alias av_st_phys1_1 : st_phys1
is va_st_phys1_1 ;
alias av_real_1 : real
is va_real_1 ;
alias av_t_real1_1 : t_real1
is va_t_real1_1 ;
alias av_st_real1_1 : st_real1
is va_st_real1_1 ;
begin
correct := s_correct1 ;
if synch = intermediate then
-- test that variables denote same object
correct := correct and av_boolean_1 = c_boolean_1 ;
correct := correct and av_bit_1 = c_bit_1 ;
correct := correct and av_severity_level_1 = c_severity_level_1 ;
correct := correct and av_character_1 = c_character_1 ;
correct := correct and av_t_enum1_1 = c_t_enum1_1 ;
correct := correct and av_st_enum1_1 = c_st_enum1_1 ;
correct := correct and av_integer_1 = c_integer_1 ;
correct := correct and av_t_int1_1 = c_t_int1_1 ;
correct := correct and av_st_int1_1 = c_st_int1_1 ;
correct := correct and av_time_1 = c_time_1 ;
correct := correct and av_t_phys1_1 = c_t_phys1_1 ;
correct := correct and av_st_phys1_1 = c_st_phys1_1 ;
correct := correct and av_real_1 = c_real_1 ;
correct := correct and av_t_real1_1 = c_t_real1_1 ;
correct := correct and av_st_real1_1 = c_st_real1_1 ;
va_boolean_1 := c_boolean_2 ;
va_bit_1 := c_bit_2 ;
va_severity_level_1 := c_severity_level_2 ;
va_character_1 := c_character_2 ;
va_t_enum1_1 := c_t_enum1_2 ;
va_st_enum1_1 := c_st_enum1_2 ;
va_integer_1 := c_integer_2 ;
va_t_int1_1 := c_t_int1_2 ;
va_st_int1_1 := c_st_int1_2 ;
va_time_1 := c_time_2 ;
va_t_phys1_1 := c_t_phys1_2 ;
va_st_phys1_1 := c_st_phys1_2 ;
va_real_1 := c_real_2 ;
va_t_real1_1 := c_t_real1_2 ;
va_st_real1_1 := c_st_real1_2 ;
correct := correct and av_boolean_1 = c_boolean_2 ;
correct := correct and av_bit_1 = c_bit_2 ;
correct := correct and av_severity_level_1 = c_severity_level_2 ;
correct := correct and av_character_1 = c_character_2 ;
correct := correct and av_t_enum1_1 = c_t_enum1_2 ;
correct := correct and av_st_enum1_1 = c_st_enum1_2 ;
correct := correct and av_integer_1 = c_integer_2 ;
correct := correct and av_t_int1_1 = c_t_int1_2 ;
correct := correct and av_st_int1_1 = c_st_int1_2 ;
correct := correct and av_time_1 = c_time_2 ;
correct := correct and av_t_phys1_1 = c_t_phys1_2 ;
correct := correct and av_st_phys1_1 = c_st_phys1_2 ;
correct := correct and av_real_1 = c_real_2 ;
correct := correct and av_t_real1_1 = c_t_real1_2 ;
correct := correct and av_st_real1_1 = c_st_real1_2 ;
av_boolean_1 := c_boolean_1 ;
av_bit_1 := c_bit_1 ;
av_severity_level_1 := c_severity_level_1 ;
av_character_1 := c_character_1 ;
av_t_enum1_1 := c_t_enum1_1 ;
av_st_enum1_1 := c_st_enum1_1 ;
av_integer_1 := c_integer_1 ;
av_t_int1_1 := c_t_int1_1 ;
av_st_int1_1 := c_st_int1_1 ;
av_time_1 := c_time_1 ;
av_t_phys1_1 := c_t_phys1_1 ;
av_st_phys1_1 := c_st_phys1_1 ;
av_real_1 := c_real_1 ;
av_t_real1_1 := c_t_real1_1 ;
av_st_real1_1 := c_st_real1_1 ;
correct := correct and va_boolean_1 = c_boolean_1 ;
correct := correct and va_bit_1 = c_bit_1 ;
correct := correct and va_severity_level_1 = c_severity_level_1 ;
correct := correct and va_character_1 = c_character_1 ;
correct := correct and va_t_enum1_1 = c_t_enum1_1 ;
correct := correct and va_st_enum1_1 = c_st_enum1_1 ;
correct := correct and va_integer_1 = c_integer_1 ;
correct := correct and va_t_int1_1 = c_t_int1_1 ;
correct := correct and va_st_int1_1 = c_st_int1_1 ;
correct := correct and va_time_1 = c_time_1 ;
correct := correct and va_t_phys1_1 = c_t_phys1_1 ;
correct := correct and va_st_phys1_1 = c_st_phys1_1 ;
correct := correct and va_real_1 = c_real_1 ;
correct := correct and va_t_real1_1 = c_t_real1_1 ;
correct := correct and va_st_real1_1 = c_st_real1_1 ;
-- test that signals denote same object
correct := correct and as_boolean_1 = c_boolean_2 ;
correct := correct and as_bit_1 = c_bit_2 ;
correct := correct and as_severity_level_1 = c_severity_level_2 ;
correct := correct and as_character_1 = c_character_2 ;
correct := correct and as_t_enum1_1 = c_t_enum1_2 ;
correct := correct and as_st_enum1_1 = c_st_enum1_2 ;
correct := correct and as_integer_1 = c_integer_2 ;
correct := correct and as_t_int1_1 = c_t_int1_2 ;
correct := correct and as_st_int1_1 = c_st_int1_2 ;
correct := correct and as_time_1 = c_time_2 ;
correct := correct and as_t_phys1_1 = c_t_phys1_2 ;
correct := correct and as_st_phys1_1 = c_st_phys1_2 ;
correct := correct and as_real_1 = c_real_2 ;
correct := correct and as_t_real1_1 = c_t_real1_2 ;
correct := correct and as_st_real1_1 = c_st_real1_2 ;
correct := correct and si_boolean_1 = c_boolean_2 ;
correct := correct and si_bit_1 = c_bit_2 ;
correct := correct and si_severity_level_1 = c_severity_level_2 ;
correct := correct and si_character_1 = c_character_2 ;
correct := correct and si_t_enum1_1 = c_t_enum1_2 ;
correct := correct and si_st_enum1_1 = c_st_enum1_2 ;
correct := correct and si_integer_1 = c_integer_2 ;
correct := correct and si_t_int1_1 = c_t_int1_2 ;
correct := correct and si_st_int1_1 = c_st_int1_2 ;
correct := correct and si_time_1 = c_time_2 ;
correct := correct and si_t_phys1_1 = c_t_phys1_2 ;
correct := correct and si_st_phys1_1 = c_st_phys1_2 ;
correct := correct and si_real_1 = c_real_2 ;
correct := correct and si_t_real1_1 = c_t_real1_2 ;
correct := correct and si_st_real1_1 = c_st_real1_2 ;
-- test that constants denote same object
correct := correct and ac_boolean_1 = c_boolean_1 ;
correct := correct and ac_bit_1 = c_bit_1 ;
correct := correct and ac_severity_level_1 = c_severity_level_1 ;
correct := correct and ac_character_1 = c_character_1 ;
correct := correct and ac_t_enum1_1 = c_t_enum1_1 ;
correct := correct and ac_st_enum1_1 = c_st_enum1_1 ;
correct := correct and ac_integer_1 = c_integer_1 ;
correct := correct and ac_t_int1_1 = c_t_int1_1 ;
correct := correct and ac_st_int1_1 = c_st_int1_1 ;
correct := correct and ac_time_1 = c_time_1 ;
correct := correct and ac_t_phys1_1 = c_t_phys1_1 ;
correct := correct and ac_st_phys1_1 = c_st_phys1_1 ;
correct := correct and ac_real_1 = c_real_1 ;
correct := correct and ac_t_real1_1 = c_t_real1_1 ;
correct := correct and ac_st_real1_1 = c_st_real1_1 ;
s_correct2 <= correct ;
end if ;
end p1 ;
begin
p1 ;
end process ;
--
process (synch)
variable correct : boolean ;
begin
if synch = final then
correct := s_correct2 ;
correct := correct and si_boolean_1 = c_boolean_1 ;
correct := correct and si_bit_1 = c_bit_1 ;
correct := correct and si_severity_level_1 = c_severity_level_1 ;
correct := correct and si_character_1 = c_character_1 ;
correct := correct and si_t_enum1_1 = c_t_enum1_1 ;
correct := correct and si_st_enum1_1 = c_st_enum1_1 ;
correct := correct and si_integer_1 = c_integer_1 ;
correct := correct and si_t_int1_1 = c_t_int1_1 ;
correct := correct and si_st_int1_1 = c_st_int1_1 ;
correct := correct and si_time_1 = c_time_1 ;
correct := correct and si_t_phys1_1 = c_t_phys1_1 ;
correct := correct and si_st_phys1_1 = c_st_phys1_1 ;
correct := correct and si_real_1 = c_real_1 ;
correct := correct and si_t_real1_1 = c_t_real1_1 ;
correct := correct and si_st_real1_1 = c_st_real1_1 ;
test_report ( "ARCH00561" ,
"Aliasing - scalar static subtypes" ,
correct) ;
end if ;
end process ;
end ARCH00561 ;
--
entity ENT00561_Test_Bench is
end ENT00561_Test_Bench ;
--
architecture ARCH00561_Test_Bench of ENT00561_Test_Bench is
begin
L1:
block
component UUT
end component ;
for CIS1 : UUT use entity WORK.E00000 ( ARCH00561 ) ;
begin
CIS1 : UUT ;
end block L1 ;
end ARCH00561_Test_Bench ;
| gpl-3.0 | 8a0121ae68cfd0a4507a32c83e3b1cde | 0.511067 | 3.047511 | false | false | false | false |
jairov4/accel-oil | solution_virtex5_plb/impl/pcores/nfa_accept_samples_generic_hw_top_v1_01_a/synhdl/vhdl/nfa_forward_buckets_if.vhd | 2 | 27,928 | -- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2014.1
-- Copyright (C) 2014 Xilinx Inc. All rights reserved.
--
-- ==============================================================
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity nfa_forward_buckets_if is
generic
(
C_PLB_AWIDTH : integer := 32;
C_PLB_DWIDTH : integer := 64;
PLB_ADDR_SHIFT : integer := 3;
USER_DATA_WIDTH : integer := 32;
USER_DATA_WIDTH_2N : integer := 32;
USER_ADDR_SHIFT : integer := 2; -- log2(byte_count_of_data_width)
REMOTE_DESTINATION_ADDRESS : std_logic_vector(0 to 31):= X"00000000"
);
port
(
-- Bus protocol ports, do not add to or delete
MPLB_Clk : in std_logic;
MPLB_Rst : in std_logic;
M_request : out std_logic;
M_priority : out std_logic_vector(0 to 1);
M_busLock : out std_logic;
M_RNW : out std_logic;
M_BE : out std_logic_vector(0 to C_PLB_DWIDTH/8-1);
M_MSize : out std_logic_vector(0 to 1);
M_size : out std_logic_vector(0 to 3);
M_type : out std_logic_vector(0 to 2);
M_TAttribute : out std_logic_vector(0 to 15);
M_lockErr : out std_logic;
M_abort : out std_logic;
M_ABus : out std_logic_vector(0 to C_PLB_AWIDTH-1);
M_UABus : out std_logic_vector(0 to 31);
M_wrDBus : out std_logic_vector(0 to C_PLB_DWIDTH-1);
M_wrBurst : out std_logic;
M_rdBurst : out std_logic;
PLB_MAddrAck : in std_logic;
PLB_MSSize : in std_logic_vector(0 to 1);
PLB_MRearbitrate : in std_logic;
PLB_MTimeout : in std_logic;
PLB_MBusy : in std_logic;
PLB_MRdErr : in std_logic;
PLB_MWrErr : in std_logic;
PLB_MIRQ : in std_logic;
PLB_MRdDBus : in std_logic_vector(0 to (C_PLB_DWIDTH-1));
PLB_MRdWdAddr : in std_logic_vector(0 to 3);
PLB_MRdDAck : in std_logic;
PLB_MRdBTerm : in std_logic;
PLB_MWrDAck : in std_logic;
PLB_MWrBTerm : in std_logic;
-- signals from user logic
USER_RdData : out std_logic_vector(USER_DATA_WIDTH - 1 downto 0); -- Bus read return data to user_logic
USER_WrData : in std_logic_vector(USER_DATA_WIDTH - 1 downto 0); -- Bus write data
USER_address : in std_logic_vector(31 downto 0); -- word offset from BASE_ADDRESS
USER_size : in std_logic_vector(31 downto 0); -- burst size of word
USER_req_nRW : in std_logic; -- req type 0: Read, 1: write
USER_req_full_n : out std_logic; -- req Fifo full
USER_req_push : in std_logic; -- req Fifo push (new request in)
USER_rsp_empty_n : out std_logic; -- return data FIFO empty
USER_rsp_pop : in std_logic -- return data FIFO pop
);
attribute SIGIS : string;
attribute SIGIS of MPLB_Clk : signal is "Clk";
attribute SIGIS of MPLB_Rst : signal is "Rst";
end entity;
------------------------------------------------------------------------------
-- Architecture section
------------------------------------------------------------------------------
architecture IMP of nfa_forward_buckets_if is
component nfa_forward_buckets_if_ap_fifo is
generic (
DATA_WIDTH : integer := 32;
ADDR_WIDTH : integer := 4;
DEPTH : integer := 16);
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
if_empty_n : OUT STD_LOGIC;
if_read : IN STD_LOGIC;
if_dout : OUT STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0);
if_full_n : OUT STD_LOGIC;
if_write : IN STD_LOGIC;
if_din : IN STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0) );
end component;
component nfa_forward_buckets_if_plb_master_if is
generic (
C_PLB_AWIDTH : integer := 32;
C_PLB_DWIDTH : integer := 64;
PLB_ADDR_SHIFT : integer := 3);
port (
-- Bus protocol ports, do not add to or delete
PLB_Clk : in std_logic;
PLB_Rst : in std_logic;
M_abort : out std_logic;
M_ABus : out std_logic_vector(0 to C_PLB_AWIDTH-1);
M_BE : out std_logic_vector(0 to C_PLB_DWIDTH/8-1);
M_busLock : out std_logic;
M_lockErr : out std_logic;
M_MSize : out std_logic_vector(0 to 1);
M_priority : out std_logic_vector(0 to 1);
M_rdBurst : out std_logic;
M_request : out std_logic;
M_RNW : out std_logic;
M_size : out std_logic_vector(0 to 3);
M_type : out std_logic_vector(0 to 2);
M_wrBurst : out std_logic;
M_wrDBus : out std_logic_vector(0 to C_PLB_DWIDTH-1);
PLB_MBusy : in std_logic;
PLB_MWrBTerm : in std_logic;
PLB_MWrDAck : in std_logic;
PLB_MAddrAck : in std_logic;
PLB_MRdBTerm : in std_logic;
PLB_MRdDAck : in std_logic;
PLB_MRdDBus : in std_logic_vector(0 to (C_PLB_DWIDTH-1));
PLB_MRdWdAddr : in std_logic_vector(0 to 3);
PLB_MRearbitrate : in std_logic;
PLB_MSSize : in std_logic_vector(0 to 1);
-- signals from user logic
BUS_RdData : out std_logic_vector(C_PLB_DWIDTH-1 downto 0); -- Bus read return data to user_logic
BUS_WrData : in std_logic_vector(C_PLB_DWIDTH-1 downto 0); -- Bus write data
BUS_address : in std_logic_vector(31 downto 0); -- word offset from BASE_ADDRESS
BUS_size : in std_logic_vector(31 downto 0); -- burst size of word
BUS_req_nRW : in std_logic; -- req type 0: Read, 1: write
BUS_req_BE : in std_logic_vector(C_PLB_DWIDTH/8 -1 downto 0); -- Bus write data byte enable
BUS_req_full_n : out std_logic; -- req Fifo full
BUS_req_push : in std_logic; -- req Fifo push (new request in)
BUS_rsp_nRW : out std_logic; -- return data FIFO rsp type
BUS_rsp_empty_n : out std_logic; -- return data FIFO empty
BUS_rsp_pop : in std_logic -- return data FIFO pop
);
end component;
-- type state_type is (IDLE, );
-- signal cs, ns : st_type;
constant PLB_BW : integer := C_PLB_DWIDTH;
constant PLB_BYTE_COUNT : integer := C_PLB_DWIDTH/8;
constant USER_DATA_BYTE_COUNT : integer := USER_DATA_WIDTH_2N/8;
constant REQ_FIFO_DATA_WIDTH : integer := 1 + 32 + 32 + USER_DATA_WIDTH_2N; -- nRW + addr + size + wr_data
constant REQ_FIFO_ADDR_WIDTH : integer := 5;
constant REQ_FIFO_DEPTH : integer := 32;
constant ALIGN_DATA_WIDTH : integer := USER_DATA_WIDTH_2N + PLB_BW;
constant ALIGN_DATA_BE_WIDTH : integer := (USER_DATA_WIDTH_2N + PLB_BW)/8;
signal user_phy_address : STD_LOGIC_VECTOR(31 downto 0);
-- request FIFO
signal req_fifo_empty_n : STD_LOGIC;
signal req_fifo_pop : STD_LOGIC;
signal req_fifo_dout : STD_LOGIC_VECTOR(REQ_FIFO_DATA_WIDTH - 1 downto 0);
signal req_fifo_full_n : STD_LOGIC;
signal req_fifo_push : STD_LOGIC;
signal req_fifo_din : STD_LOGIC_VECTOR(REQ_FIFO_DATA_WIDTH - 1 downto 0);
signal user_WrData_2N : STD_LOGIC_VECTOR(USER_DATA_WIDTH_2N-1 downto 0);
signal req_fifo_dout_req_nRW : STD_LOGIC;
signal req_fifo_dout_req_address : STD_LOGIC_VECTOR(31 downto 0);
signal req_fifo_dout_req_size, req_fifo_dout_req_size_normalize : STD_LOGIC_VECTOR(31 downto 0);
-- internal request information
signal req_nRW : STD_LOGIC;
signal req_address : STD_LOGIC_VECTOR(31 downto 0);
signal req_size, burst_size : STD_LOGIC_VECTOR(31 downto 0);
signal req_size_user : STD_LOGIC_VECTOR(31 downto 0);
signal req_BE : STD_LOGIC_VECTOR(PLB_BYTE_COUNT-1 downto 0);
signal req_WrData : STD_LOGIC_VECTOR(ALIGN_DATA_WIDTH -1 downto 0);
signal req_WrData_BE : STD_LOGIC_VECTOR(ALIGN_DATA_BE_WIDTH -1 downto 0);
signal req_WrData_byte_p : STD_LOGIC_VECTOR(PLB_ADDR_SHIFT-1 downto 0);
signal req_valid, req_SOP, req_EOP_user, req_EOP : STD_LOGIC;
signal req_burst_write_counter : STD_LOGIC_VECTOR(31 downto 0);
signal req_burst_mode, req_last_burst: STD_LOGIC;
-- interface to PLB_master_if module
signal PLB_master_if_req_full_n : STD_LOGIC;
signal PLB_master_if_req_push : STD_LOGIC;
signal PLB_master_if_dataout : STD_LOGIC_VECTOR(PLB_BW-1 downto 0);
signal PLB_master_if_rsp_nRW : STD_LOGIC;
signal PLB_master_if_rsp_empty_n : STD_LOGIC;
signal PLB_master_if_rsp_pop : STD_LOGIC;
signal USER_size_local: STD_LOGIC_VECTOR(31 downto 0);
-- rsp FIFO
constant RSP_FIFO_DATA_WIDTH : integer := PLB_ADDR_SHIFT + 32; -- addr + size
constant RSP_FIFO_ADDR_WIDTH : integer := 6;
constant RSP_FIFO_DEPTH : integer := 64;
signal rsp_fifo_empty_n : STD_LOGIC;
signal rsp_fifo_pop : STD_LOGIC;
signal rsp_fifo_dout : STD_LOGIC_VECTOR(RSP_FIFO_DATA_WIDTH -1 downto 0);
signal rsp_fifo_full_n : STD_LOGIC;
signal rsp_fifo_push : STD_LOGIC;
signal rsp_fifo_din : STD_LOGIC_VECTOR(RSP_FIFO_DATA_WIDTH -1 downto 0);
signal rsp_valid, rsp_SOP : STD_LOGIC;
signal rsp_addr : STD_LOGIC_VECTOR(PLB_ADDR_SHIFT-1 downto 0);
signal rsp_size : STD_LOGIC_VECTOR(31 downto 0);
signal rsp_rd_data : STD_LOGIC_VECTOR(ALIGN_DATA_WIDTH -1 downto 0);
signal rsp_rd_data_byte_count : STD_LOGIC_VECTOR(4 downto 0);
-- rd data user FIFO
signal rd_data_user_fifo_empty_n : STD_LOGIC;
signal rd_data_user_fifo_pop : STD_LOGIC;
signal rd_data_user_fifo_dout : STD_LOGIC_VECTOR(USER_DATA_WIDTH -1 downto 0);
signal rd_data_user_fifo_full_n : STD_LOGIC;
signal rd_data_user_fifo_push : STD_LOGIC;
signal rd_data_user_fifo_din : STD_LOGIC_VECTOR(USER_DATA_WIDTH -1 downto 0);
signal rd_data_user_fifo_din_2N : STD_LOGIC_VECTOR(USER_DATA_WIDTH_2N -1 downto 0);
signal BE_ALL_ONE : STD_LOGIC_VECTOR(PLB_BYTE_COUNT -1 downto 0);
begin
BE_ALL_ONE <= (others => '1');
M_UABus <= (others => '0');
M_TAttribute <= (others => '0');
-- interface to user logic
user_phy_address(31 downto USER_ADDR_SHIFT) <= REMOTE_DESTINATION_ADDRESS(0 to C_PLB_AWIDTH - USER_ADDR_SHIFT -1) + USER_address(31 -USER_ADDR_SHIFT downto 0);
user_phy_address(USER_ADDR_SHIFT-1 downto 0) <= REMOTE_DESTINATION_ADDRESS(C_PLB_AWIDTH - USER_ADDR_SHIFT to C_PLB_AWIDTH -1);
USER_size_local <= X"00000001" when conv_integer(USER_size(31 downto 1)) = 0 else USER_size;
USER_req_full_n <= req_fifo_full_n;
process(USER_WrData)
variable i: integer;
begin
user_WrData_2N <= (others=> '0');
for i in 0 to USER_WrData'length -1 loop
user_WrData_2N (USER_DATA_WIDTH_2N-1 -i) <= USER_WrData(i);
end loop;
end process;
req_fifo_din(REQ_FIFO_DATA_WIDTH-1) <= USER_req_nRW;
req_fifo_din(REQ_FIFO_DATA_WIDTH-1-1 downto REQ_FIFO_DATA_WIDTH -1-32) <= user_phy_address;
req_fifo_din(REQ_FIFO_DATA_WIDTH-1-32-1 downto REQ_FIFO_DATA_WIDTH -1-32-32) <= USER_size_local;
req_fifo_din(USER_DATA_WIDTH_2N -1 downto 0) <= user_WrData_2N(USER_DATA_WIDTH_2N-1 downto 0);
req_fifo_push <= USER_req_push;
U_nfa_forward_buckets_if_req_fifo: component nfa_forward_buckets_if_ap_fifo
generic map(
DATA_WIDTH => REQ_FIFO_DATA_WIDTH,
ADDR_WIDTH => REQ_FIFO_ADDR_WIDTH,
DEPTH => REQ_FIFO_DEPTH)
port map(
clk => MPLB_Clk,
reset => MPLB_Rst,
if_empty_n => req_fifo_empty_n,
if_read => req_fifo_pop,
if_dout => req_fifo_dout,
if_full_n => req_fifo_full_n,
if_write => req_fifo_push,
if_din => req_fifo_din
);
req_fifo_dout_req_nRW <= req_fifo_dout(REQ_FIFO_DATA_WIDTH -1);
req_fifo_dout_req_size <= req_fifo_dout(REQ_FIFO_DATA_WIDTH-1-32-1 downto REQ_FIFO_DATA_WIDTH -1-32-32);
req_fifo_dout_req_address <= req_fifo_dout(REQ_FIFO_DATA_WIDTH-1-1 downto REQ_FIFO_DATA_WIDTH -1-32);
req_fifo_dout_req_size_normalize(31 downto USER_ADDR_SHIFT) <= req_fifo_dout_req_size(31-USER_ADDR_SHIFT downto 0);
req_fifo_dout_req_size_normalize(USER_ADDR_SHIFT-1 downto 0) <= (others => '0');
process(req_fifo_empty_n, req_valid)
begin
req_fifo_pop <= '0';
if (req_fifo_empty_n = '1' and req_valid = '0') then -- lunch next request
req_fifo_pop <= '1';
end if;
end process;
process (MPLB_Clk, MPLB_Rst)
variable offset: integer;
begin
if (MPLB_Rst = '1') then
req_nRW <= '0';
burst_size <= (others => '0');
req_size_user <= (others => '0');
req_address <= (others => '0');
req_WrData <= (others => '0'); -- set possible MSB to ZERO
req_WrData_BE <= (others => '0'); -- set possible MSB to ZERO
req_WrData_byte_p <= (others => '0'); -- set possible MSB to ZERO
req_valid <= '0';
req_EOP <= '0';
req_burst_write_counter <= (others => '0');
req_burst_mode <= '0';
elsif (MPLB_Clk'event and MPLB_Clk = '1') then
if (req_fifo_pop = '1') then -- lunch next request
req_valid <= '1';
if (req_burst_mode = '0') then
if (req_fifo_dout_req_nRW = '0') then
if (req_fifo_dout_req_size_normalize(PLB_ADDR_SHIFT-1 downto 0) = CONV_STD_LOGIC_VECTOR(0,PLB_ADDR_SHIFT) and
req_fifo_dout_req_address(PLB_ADDR_SHIFT-1 downto 0) = CONV_STD_LOGIC_VECTOR(0,PLB_ADDR_SHIFT)) then
burst_size(31-PLB_ADDR_SHIFT downto 0) <= req_fifo_dout_req_size_normalize(31 downto PLB_ADDR_SHIFT);
elsif (('0'&req_fifo_dout_req_size_normalize(PLB_ADDR_SHIFT-1 downto 0)) +
('0'&req_fifo_dout_req_address(PLB_ADDR_SHIFT-1 downto 0)) <= PLB_BYTE_COUNT) then
burst_size(31-PLB_ADDR_SHIFT downto 0) <= req_fifo_dout_req_size_normalize(31 downto PLB_ADDR_SHIFT) + 1;
else
burst_size(31-PLB_ADDR_SHIFT downto 0) <= req_fifo_dout_req_size_normalize(31 downto PLB_ADDR_SHIFT) + 2;
end if;
else
burst_size <= X"00000001"; -- single by default
if (req_fifo_dout_req_size_normalize(31 downto PLB_ADDR_SHIFT+1) /= CONV_STD_LOGIC_VECTOR(0,31-PLB_ADDR_SHIFT)) then -- may burst
burst_size(31 downto 32-PLB_ADDR_SHIFT) <= (others=>'0'); -- burst_size for write operation
if (req_fifo_dout_req_address(PLB_ADDR_SHIFT-1 downto 0) = CONV_STD_LOGIC_VECTOR(0, PLB_ADDR_SHIFT)) or
(conv_integer(req_fifo_dout_req_address(PLB_ADDR_SHIFT-1 downto 0)) + conv_integer(req_fifo_dout_req_size_normalize(PLB_ADDR_SHIFT-1 downto 0)) >= PLB_BYTE_COUNT) then
burst_size(31-PLB_ADDR_SHIFT downto 0) <= req_fifo_dout_req_size_normalize(31 downto PLB_ADDR_SHIFT);
else
burst_size(31-PLB_ADDR_SHIFT downto 0) <= req_fifo_dout_req_size_normalize(31 downto PLB_ADDR_SHIFT)-1;
end if;
end if;
end if;
offset := conv_integer(req_fifo_dout_req_address(PLB_ADDR_SHIFT-1 downto 0));
if (req_fifo_dout_req_nRW = '1') then
req_WrData(USER_DATA_WIDTH_2N +offset*8 -1 downto offset*8) <= req_fifo_dout(USER_DATA_WIDTH_2N -1 downto 0);
req_WrData_BE(USER_DATA_BYTE_COUNT+offset-1 downto offset) <= (others => '1');
end if;
req_size_user <= req_fifo_dout_req_size; -- for read operation
req_nRW <= req_fifo_dout_req_nRW;
req_EOP <= '1';
req_address <= req_fifo_dout_req_address;
req_burst_write_counter <= req_fifo_dout_req_size;
req_WrData_byte_p <= req_fifo_dout_req_address(PLB_ADDR_SHIFT-1 downto 0) + USER_DATA_BYTE_COUNT;
if (req_fifo_dout_req_nRW = '1' and req_fifo_dout_req_size(31 downto 1) /= "0000000000000000000000000000000") then
req_burst_mode <= '1';
req_EOP <= '0';
end if;
else -- in a burst write process
req_burst_write_counter <= req_burst_write_counter -1;
offset := conv_integer(req_WrData_byte_p);
req_WrData(USER_DATA_WIDTH_2N +offset*8 -1 downto offset*8) <= req_fifo_dout(USER_DATA_WIDTH_2N -1 downto 0);
req_WrData_BE(USER_DATA_BYTE_COUNT+offset-1 downto offset) <= (others => '1');
req_WrData_byte_p <= req_WrData_byte_p + USER_DATA_BYTE_COUNT;
if (req_last_burst = '1') then
req_burst_mode <= '0';
req_EOP <= '1';
end if;
end if;
elsif (req_valid = '1') then
if (req_nRW = '0' and PLB_master_if_req_push = '1') then
req_valid <= '0';
elsif (req_nRW = '1') then
if (req_EOP = '1' and PLB_master_if_req_push = '1') then -- last burst request
if (req_WrData_BE(ALIGN_DATA_BE_WIDTH-1 downto PLB_BYTE_COUNT) = CONV_STD_LOGIC_VECTOR(0, ALIGN_DATA_BE_WIDTH-PLB_BYTE_COUNT)) then
req_valid <= '0';
req_EOP <= '0';
req_WrData <= (others=>'0');
req_WrData_BE <= (others => '0');
else
req_WrData(USER_DATA_WIDTH_2N + PLB_BW -1 downto USER_DATA_WIDTH_2N) <= (others => '0');
req_WrData(USER_DATA_WIDTH_2N -1 downto 0) <= req_WrData(USER_DATA_WIDTH_2N +PLB_BW -1 downto PLB_BW);
req_WrData_BE(ALIGN_DATA_BE_WIDTH -1 downto ALIGN_DATA_BE_WIDTH-PLB_BYTE_COUNT) <= (others => '0');
req_WrData_BE(ALIGN_DATA_BE_WIDTH -PLB_BYTE_COUNT-1 downto 0) <= req_WrData_BE(ALIGN_DATA_BE_WIDTH -1 downto PLB_BYTE_COUNT);
req_address(31 downto PLB_ADDR_SHIFT) <= req_address(31 downto PLB_ADDR_SHIFT) +1;
req_address(PLB_ADDR_SHIFT-1 downto 0) <= (others=>'0');
end if;
elsif (req_EOP = '0') then
if (req_WrData_BE(PLB_BYTE_COUNT-1) = '0') then
req_valid <= '0';
elsif (req_WrData_BE(PLB_BYTE_COUNT-1) = '1' and PLB_master_if_req_push = '1') then
req_WrData(USER_DATA_WIDTH_2N + PLB_BW -1 downto USER_DATA_WIDTH_2N) <= (others => '0');
req_WrData(USER_DATA_WIDTH_2N -1 downto 0) <= req_WrData(USER_DATA_WIDTH_2N +PLB_BW -1 downto PLB_BW);
req_WrData_BE(ALIGN_DATA_BE_WIDTH -1 downto ALIGN_DATA_BE_WIDTH-PLB_BYTE_COUNT) <= (others => '0');
req_WrData_BE(ALIGN_DATA_BE_WIDTH-PLB_BYTE_COUNT-1 downto 0) <= req_WrData_BE(ALIGN_DATA_BE_WIDTH -1 downto PLB_BYTE_COUNT);
req_address(31 downto PLB_ADDR_SHIFT) <= req_address(31 downto PLB_ADDR_SHIFT) +1;
req_address(PLB_ADDR_SHIFT-1 downto 0) <= (others=>'0');
end if;
end if;
end if;
end if;
end if;
end process;
req_last_burst <= '1' when (req_burst_mode = '1' and req_burst_write_counter(31 downto 0) = X"00000002") else '0';
process(req_nRW, req_WrData_BE, burst_size)
begin
req_size <= (others => '0');
if (req_nRW = '0') then
req_size <= burst_size;
elsif (req_WrData_BE(PLB_BYTE_COUNT-1 downto 0) = BE_ALL_ONE) then
req_size <= burst_size;
else
req_size <= X"00000001";
end if;
end process;
process(req_valid, PLB_master_if_req_full_n, req_nRW, req_WrData_BE)
begin
PLB_master_if_req_push <= '0';
if (req_valid = '1' and PLB_master_if_req_full_n = '1') then
if (req_nRW = '0') then
PLB_master_if_req_push <= '1'; -- only push when the last byte been push
elsif (req_WrData_BE(PLB_BYTE_COUNT-1) = '1' or (req_EOP = '1' and req_WrData_BE(PLB_BYTE_COUNT-1 downto 0) /= CONV_STD_LOGIC_VECTOR(0, PLB_BYTE_COUNT))) then
PLB_master_if_req_push <= '1'; -- only push when the last byte been push
end if;
end if;
end process;
req_BE <= req_WrData_BE(PLB_BYTE_COUNT-1 downto 0) when req_nRW = '1' else (others => '1');
U_nfa_forward_buckets_if_plb_master_if: component nfa_forward_buckets_if_plb_master_if
generic map(
C_PLB_AWIDTH => C_PLB_AWIDTH,
C_PLB_DWIDTH => C_PLB_DWIDTH,
PLB_ADDR_SHIFT => PLB_ADDR_SHIFT)
port map (
-- Bus protocol ports, do not add to or delete
PLB_Clk => MPLB_Clk,
PLB_Rst => MPLB_Rst,
M_abort => M_abort,
M_ABus => M_ABus,
M_BE => M_BE,
M_busLock => M_busLock,
M_lockErr => M_lockErr,
M_MSize => M_MSize,
M_priority => M_priority,
M_rdBurst => M_rdBurst,
M_request => M_request,
M_RNW => M_RNW,
M_size => M_size,
M_type => M_type,
M_wrBurst => M_wrBurst,
M_wrDBus => M_wrDBus,
PLB_MBusy => PLB_MBusy,
PLB_MWrBTerm => PLB_MWrBTerm,
PLB_MWrDAck => PLB_MWrDAck,
PLB_MAddrAck => PLB_MAddrAck,
PLB_MRdBTerm => PLB_MRdBTerm,
PLB_MRdDAck => PLB_MRdDAck,
PLB_MRdDBus => PLB_MRdDBus,
PLB_MRdWdAddr => PLB_MRdWdAddr,
PLB_MRearbitrate => PLB_MRearbitrate,
PLB_MSSize => PLB_MSSize,
-- signals from user logic
BUS_RdData => PLB_master_if_dataout,
BUS_WrData => req_WrData(PLB_BW-1 downto 0),
BUS_address => req_address,
BUS_size => req_size,
BUS_req_nRW => req_nRW,
BUS_req_BE => req_BE,
BUS_req_full_n => PLB_master_if_req_full_n,
BUS_req_push => PLB_master_if_req_push,
BUS_rsp_nRW => PLB_master_if_rsp_nRW,
BUS_rsp_empty_n => PLB_master_if_rsp_empty_n,
BUS_rsp_pop => PLB_master_if_rsp_pop
);
-- below is the response (bus read data) part
U_nfa_forward_buckets_if_rsp_fifo: component nfa_forward_buckets_if_ap_fifo
generic map(
DATA_WIDTH => RSP_FIFO_DATA_WIDTH,
ADDR_WIDTH => RSP_FIFO_ADDR_WIDTH,
DEPTH => RSP_FIFO_DEPTH)
port map(
clk => MPLB_Clk,
reset => MPLB_Rst,
if_empty_n => rsp_fifo_empty_n,
if_read => rsp_fifo_pop,
if_dout => rsp_fifo_dout,
if_full_n => rsp_fifo_full_n,
if_write => rsp_fifo_push,
if_din => rsp_fifo_din
);
rsp_fifo_din(32+PLB_ADDR_SHIFT-1 downto 32) <= req_address(PLB_ADDR_SHIFT-1 downto 0);
rsp_fifo_din(31 downto 0) <= req_size_user;
rsp_fifo_push <= PLB_master_if_req_push and (not req_nRW);
process (rsp_valid, PLB_master_if_rsp_empty_n, rsp_rd_data_byte_count)
begin
PLB_master_if_rsp_pop <= '0';
-- fetch data to rsp_rd_data until enough bytes
if (rsp_valid = '1' and PLB_master_if_rsp_empty_n = '1' and CONV_INTEGER(rsp_rd_data_byte_count) < USER_DATA_BYTE_COUNT) then
PLB_master_if_rsp_pop <= '1';
end if;
end process;
process (MPLB_Clk, MPLB_Rst)
begin
if (MPLB_Rst = '1') then
rsp_valid <= '0';
rsp_addr <= (others=> '0');
rsp_size <= (others=> '0');
rsp_SOP <= '1';
rsp_rd_data_byte_count <= (others => '0');
rsp_rd_data <= (others=>'0');
rsp_fifo_pop <= '0';
elsif (MPLB_Clk'event and MPLB_Clk = '1') then
rsp_fifo_pop <= '0';
if (rsp_valid = '0' and rsp_fifo_empty_n = '1') then
rsp_valid <= '1';
rsp_addr <= rsp_fifo_dout(32+PLB_ADDR_SHIFT-1 downto 32);
rsp_size <= rsp_fifo_dout(31 downto 0);
rsp_fifo_pop <= '1';
rsp_rd_data_byte_count <= (others=>'0');
rsp_SOP <= '1';
end if;
-- fetch data to rsp_rd_data until enough bytes
if (PLB_master_if_rsp_pop = '1') then
rsp_rd_data(USER_DATA_WIDTH_2N-1 downto 0) <= rsp_rd_data(USER_DATA_WIDTH_2N + PLB_BW -1 downto PLB_BW);
rsp_rd_data(USER_DATA_WIDTH_2N +PLB_BW -1 downto USER_DATA_WIDTH_2N) <= PLB_master_if_dataout;
if (rsp_SOP = '1') then
rsp_rd_data_byte_count <= rsp_rd_data_byte_count + PLB_BYTE_COUNT - rsp_addr;
rsp_SOP <= '0';
else
rsp_rd_data_byte_count <= rsp_rd_data_byte_count + PLB_BYTE_COUNT;
end if;
end if;
-- write one unit of data to USER LOGIC
if (rd_data_user_fifo_push = '1') then
rsp_size <= rsp_size -1;
rsp_rd_data_byte_count <= rsp_rd_data_byte_count - USER_DATA_BYTE_COUNT;
rsp_addr <= rsp_addr + USER_DATA_BYTE_COUNT;
if (rsp_size = X"00000001") then
rsp_valid <= '0';
end if;
end if;
end if;
end process;
process(rsp_addr, rsp_rd_data,rsp_valid, rd_data_user_fifo_full_n, rsp_rd_data_byte_count, rd_data_user_fifo_din_2N)
variable i: integer;
begin
case CONV_INTEGER(rsp_addr) is
when 0 => rd_data_user_fifo_din_2N <= rsp_rd_data(USER_DATA_WIDTH_2N +32 -1 downto 32);
when 1 => rd_data_user_fifo_din_2N <= rsp_rd_data(USER_DATA_WIDTH_2N +40 -1 downto 40);
when 2 => rd_data_user_fifo_din_2N <= rsp_rd_data(USER_DATA_WIDTH_2N +48 -1 downto 48);
when 3 => rd_data_user_fifo_din_2N <= rsp_rd_data(USER_DATA_WIDTH_2N +56 -1 downto 56);
when 4 => rd_data_user_fifo_din_2N <= rsp_rd_data(USER_DATA_WIDTH_2N +64 -1 downto 64);
when 5 => rd_data_user_fifo_din_2N <= rsp_rd_data(USER_DATA_WIDTH_2N +8 -1 downto 8);
when 6 => rd_data_user_fifo_din_2N <= rsp_rd_data(USER_DATA_WIDTH_2N +16 -1 downto 16);
when 7 => rd_data_user_fifo_din_2N <= rsp_rd_data(USER_DATA_WIDTH_2N +24 -1 downto 24);
when others => null;
end case;
for i in 0 to USER_DATA_WIDTH -1 loop
rd_data_user_fifo_din(i) <= rd_data_user_fifo_din_2N(USER_DATA_WIDTH_2N-1-i);
end loop;
rd_data_user_fifo_push <= '0';
if (rsp_valid = '1' and rd_data_user_fifo_full_n = '1' and
CONV_INTEGER(rsp_rd_data_byte_count)>= USER_DATA_BYTE_COUNT) then
rd_data_user_fifo_push <= '1';
end if;
end process;
U_nfa_forward_buckets_if_rd_data_user_fifo: component nfa_forward_buckets_if_ap_fifo
generic map(
DATA_WIDTH => USER_DATA_WIDTH,
ADDR_WIDTH => 5,
DEPTH => 32)
port map(
clk => MPLB_Clk,
reset => MPLB_Rst,
if_empty_n => rd_data_user_fifo_empty_n,
if_read => USER_rsp_pop,
if_dout => rd_data_user_fifo_dout,
if_full_n => rd_data_user_fifo_full_n,
if_write => rd_data_user_fifo_push,
if_din => rd_data_user_fifo_din
);
USER_RdData <= rd_data_user_fifo_dout;
USER_rsp_empty_n <= rd_data_user_fifo_empty_n;
end IMP;
| lgpl-3.0 | cf0c5d1982be61d2e284c28f427a407d | 0.55217 | 3.262236 | false | false | false | false |
grwlf/vsim | vhdl_ct/ct00622.vhd | 1 | 6,793 | -- NEED RESULT: ARCH00622: Concurrent proc call 1 passed
-- NEED RESULT: ARCH00622.P1: Multi transport transactions occurred on concurrent signal asg passed
-- NEED RESULT: ARCH00622: Concurrent proc call 2 passed
-- NEED RESULT: ARCH00622: One transport transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00622: Old transactions were removed on a concurrent signal asg passed
-- NEED RESULT: P1: Transport transactions completed entirely passed
-------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
-------------------------------------------------------------------------------
--
-- TEST NAME:
--
-- CT00622
--
-- AUTHOR:
--
-- G. Tominovich
--
-- TEST OBJECTIVES:
--
-- 9.3 (3)
--
-- DESIGN UNIT ORDERING:
--
-- ENT00622(ARCH00622)
-- ENT00622_Test_Bench(ARCH00622_Test_Bench)
--
-- REVISION HISTORY:
--
-- 24-AUG-1987 - initial revision
--
-- NOTES:
--
-- self-checking
-- automatically generated
--
use WORK.STANDARD_TYPES.all ;
entity ENT00622 is
port (
s_st_arr1_vector : inout st_arr1_vector
) ;
subtype chk_sig_type is integer range -1 to 100 ;
signal chk_st_arr1_vector : chk_sig_type := -1 ;
--
end ENT00622 ;
--
--
architecture ARCH00622 of ENT00622 is
subtype chk_time_type is Time ;
signal s_st_arr1_vector_savt : chk_time_type := 0 ns ;
--
subtype chk_cnt_type is Integer ;
signal s_st_arr1_vector_cnt : chk_cnt_type := 0 ;
--
type select_type is range 1 to 3 ;
signal st_arr1_vector_select : select_type := 1 ;
--
procedure P1
(signal s_st_arr1_vector : in st_arr1_vector ;
signal select_sig : out Select_Type ;
signal savtime : out Chk_Time_Type ;
signal chk_sig : out Chk_Sig_Type ;
signal count : out Integer)
is
variable correct : boolean ;
begin
case s_st_arr1_vector_cnt is
when 0
=> null ;
-- s_st_arr1_vector(highb)(lowb to highb-1) <= transport
-- c_st_arr1_vector_2(highb)(lowb to highb-1) after 10 ns,
-- c_st_arr1_vector_1(highb)(lowb to highb-1) after 20 ns ;
--
when 1
=> correct :=
s_st_arr1_vector(highb)(lowb to highb-1) =
c_st_arr1_vector_2(highb)(lowb to highb-1) and
(s_st_arr1_vector_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00622" ,
"Concurrent proc call 1",
correct ) ;
--
when 2
=> correct :=
s_st_arr1_vector(highb)(lowb to highb-1) =
c_st_arr1_vector_1(highb)(lowb to highb-1) and
(s_st_arr1_vector_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00622.P1" ,
"Multi transport transactions occurred on " &
"concurrent signal asg",
correct ) ;
--
select_sig <= transport 2 ;
-- s_st_arr1_vector(highb)(lowb to highb-1) <= transport
-- c_st_arr1_vector_2(highb)(lowb to highb-1) after 10 ns ,
-- c_st_arr1_vector_1(highb)(lowb to highb-1) after 20 ns ,
-- c_st_arr1_vector_2(highb)(lowb to highb-1) after 30 ns ,
-- c_st_arr1_vector_1(highb)(lowb to highb-1) after 40 ns ;
--
when 3
=> correct :=
s_st_arr1_vector(highb)(lowb to highb-1) =
c_st_arr1_vector_2(highb)(lowb to highb-1) and
(s_st_arr1_vector_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00622" ,
"Concurrent proc call 2",
correct ) ;
select_sig <= transport 3 ;
-- s_st_arr1_vector(highb)(lowb to highb-1) <= transport
-- c_st_arr1_vector_1(highb)(lowb to highb-1) after 5 ns ;
--
when 4
=> correct :=
s_st_arr1_vector(highb)(lowb to highb-1) =
c_st_arr1_vector_1(highb)(lowb to highb-1) and
(s_st_arr1_vector_savt + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00622" ,
"One transport transaction occurred on a " &
"concurrent signal asg",
correct ) ;
test_report ( "ARCH00622" ,
"Old transactions were removed on a " &
"concurrent signal asg",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00622" ,
"Old transactions were removed on a " &
"concurrent signal asg",
false ) ;
--
end case ;
--
savtime <= transport Std.Standard.Now ;
chk_sig <= transport s_st_arr1_vector_cnt
after (1 us - Std.Standard.Now) ;
count <= transport s_st_arr1_vector_cnt + 1 ;
--
end ;
--
begin
CHG1 :
P1(
s_st_arr1_vector ,
st_arr1_vector_select ,
s_st_arr1_vector_savt ,
chk_st_arr1_vector ,
s_st_arr1_vector_cnt ) ;
--
PGEN_CHKP_1 :
process ( chk_st_arr1_vector )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P1" ,
"Transport transactions completed entirely",
chk_st_arr1_vector = 4 ) ;
end if ;
end process PGEN_CHKP_1 ;
--
--
with st_arr1_vector_select select
s_st_arr1_vector(highb)(lowb to highb-1) <= transport
c_st_arr1_vector_2(highb)(lowb to highb-1) after 10 ns,
c_st_arr1_vector_1(highb)(lowb to highb-1) after 20 ns
when 1,
--
c_st_arr1_vector_2(highb)(lowb to highb-1) after 10 ns ,
c_st_arr1_vector_1(highb)(lowb to highb-1) after 20 ns ,
c_st_arr1_vector_2(highb)(lowb to highb-1) after 30 ns ,
c_st_arr1_vector_1(highb)(lowb to highb-1) after 40 ns
when 2,
--
c_st_arr1_vector_1(highb)(lowb to highb-1) after 5 ns when 3 ;
--
end ARCH00622 ;
--
--
use WORK.STANDARD_TYPES.all ;
entity ENT00622_Test_Bench is
signal s_st_arr1_vector : st_arr1_vector
:= c_st_arr1_vector_1 ;
--
end ENT00622_Test_Bench ;
--
--
architecture ARCH00622_Test_Bench of ENT00622_Test_Bench is
begin
L1:
block
component UUT
port (
s_st_arr1_vector : inout st_arr1_vector
) ;
end component ;
--
for CIS1 : UUT use entity WORK.ENT00622 ( ARCH00622 ) ;
begin
CIS1 : UUT
port map (
s_st_arr1_vector
)
;
end block L1 ;
end ARCH00622_Test_Bench ;
| gpl-3.0 | 70135526f8cf16ffacfcd42867df39cb | 0.528044 | 3.295973 | false | true | false | false |
MilosSubotic/huffman_coding | RTL/src/rtl/text2sym_conv_and_stage_cnt.vhd | 1 | 3,219 | ------------------------------------------------------------------------------
-- @license MIT
-- @brief
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use work.global.all;
use work.reg;
entity text2sym_conv_and_stage_freq is
port(
i_clk : in std_logic;
in_rst : in std_logic;
-- Input port.
s_axis_tdata : in std_logic_vector(7 downto 0);
s_axis_tvalid : in std_logic;
s_axis_tready : out std_logic;
s_axis_tlast : in std_logic;
-- Output stuff.
o_stage : out t_stage;
o_pipe_en : out std_logic;
o_pipe_flush : out std_logic;
o_sym : out t_sym
);
end entity text2sym_conv_and_stage_freq;
architecture arch_text2sym_conv_and_stage_freq of
text2sym_conv_and_stage_freq is
type t_states is (
NEW_CHAR,
UPPER_NIBBLE,
LAST_STAGE,
UPPER_NIBBLE_LAST,
FLUSH
);
signal state : t_states;
signal sym : t_sym;
signal en : std_logic;
signal up_nib : t_sym;
signal next_up_nib : t_sym;
signal up_nib_en : std_logic;
signal stage : t_stage;
signal next_stage : t_stage;
signal wrap_stage : t_stage;
signal stage_en : std_logic;
begin
-- Regiser and transition function.
process(i_clk, in_rst)
begin
if in_rst = '0' then
state <= NEW_CHAR;
elsif rising_edge(i_clk) then
case state is
when NEW_CHAR =>
if s_axis_tvalid = '1' then
if s_axis_tlast = '1' then
state <= UPPER_NIBBLE_LAST;
else
state <= UPPER_NIBBLE;
end if;
end if;
when UPPER_NIBBLE =>
if stage = 15 then
state <= LAST_STAGE;
else
state <= NEW_CHAR;
end if;
when LAST_STAGE =>
state <= NEW_CHAR;
when UPPER_NIBBLE_LAST =>
state <= FLUSH;
when FLUSH =>
-- TODO Implement.
state <= NEW_CHAR;
end case;
end if;
end process;
with state select en <=
s_axis_tvalid when NEW_CHAR,
'1' when others;
o_pipe_en <= en;
with state select s_axis_tready <=
'1' when NEW_CHAR,
'0' when others;
with state select o_pipe_flush <=
'1' when FLUSH,
'0' when others;
with state select sym <=
s_axis_tdata(3 downto 0) when NEW_CHAR,
up_nib when others;
o_sym <= sym;
-- Upper nibble.
with state select up_nib_en <=
s_axis_tvalid when NEW_CHAR,
'0' when others;
next_up_nib <= s_axis_tdata(7 downto 4) when up_nib_en = '1' else up_nib;
up_nib_reg: entity reg
generic map(
WIDTH => 4
)
port map(
i_clk => i_clk,
in_rst => in_rst,
i_d => next_up_nib,
o_q => up_nib
);
-- Stage counter.
stage_en <= en;
wrap_stage <= "00000" when stage = 16 else stage + 1;
next_stage <= wrap_stage when stage_en = '1' else stage;
stage_reg: entity reg
generic map(
WIDTH => 5
)
port map(
i_clk => i_clk,
in_rst => in_rst,
i_d => next_stage,
o_q => stage
);
o_stage <= stage;
end architecture arch_text2sym_conv_and_stage_freq;
| mit | 6bc2277d5097fc77beb88fb3a5934773 | 0.53091 | 2.937044 | false | false | false | false |
Given-Jiang/Binarization | tb_Binarization/db/Binarization.vhd | 1 | 2,974 | -- This file is not intended for synthesis, is is present so that simulators
-- see a complete view of the system.
-- You may use the entity declaration from this file as the basis for a
-- component declaration in a VHDL file instantiating this entity.
--altera translate_off
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.NUMERIC_STD.all;
entity Binarization is
port (
Avalon_MM_Slave_address : in std_logic_vector(2-1 downto 0) := (others=>'0');
Avalon_MM_Slave_write : in std_logic := '0';
Avalon_MM_Slave_writedata : in std_logic_vector(32-1 downto 0) := (others=>'0');
Avalon_ST_Sink_data : in std_logic_vector(24-1 downto 0) := (others=>'0');
Avalon_ST_Sink_endofpacket : in std_logic := '0';
Avalon_ST_Sink_ready : out std_logic;
Avalon_ST_Sink_startofpacket : in std_logic := '0';
Avalon_ST_Sink_valid : in std_logic := '0';
Avalon_ST_Source_data : out std_logic_vector(24-1 downto 0);
Avalon_ST_Source_endofpacket : out std_logic;
Avalon_ST_Source_ready : in std_logic := '0';
Avalon_ST_Source_startofpacket : out std_logic;
Avalon_ST_Source_valid : out std_logic;
Clock : in std_logic := '0';
aclr : in std_logic := '0'
);
end entity Binarization;
architecture rtl of Binarization is
component Binarization_GN is
port (
Avalon_MM_Slave_address : in std_logic_vector(2-1 downto 0) := (others=>'0');
Avalon_MM_Slave_write : in std_logic := '0';
Avalon_MM_Slave_writedata : in std_logic_vector(32-1 downto 0) := (others=>'0');
Avalon_ST_Sink_data : in std_logic_vector(24-1 downto 0) := (others=>'0');
Avalon_ST_Sink_endofpacket : in std_logic := '0';
Avalon_ST_Sink_ready : out std_logic;
Avalon_ST_Sink_startofpacket : in std_logic := '0';
Avalon_ST_Sink_valid : in std_logic := '0';
Avalon_ST_Source_data : out std_logic_vector(24-1 downto 0);
Avalon_ST_Source_endofpacket : out std_logic;
Avalon_ST_Source_ready : in std_logic := '0';
Avalon_ST_Source_startofpacket : out std_logic;
Avalon_ST_Source_valid : out std_logic;
Clock : in std_logic := '0';
aclr : in std_logic := '0'
);
end component Binarization_GN;
begin
Binarization_GN_0: if true generate
inst_Binarization_GN_0: Binarization_GN
port map(Avalon_MM_Slave_address => Avalon_MM_Slave_address, Avalon_MM_Slave_write => Avalon_MM_Slave_write, Avalon_MM_Slave_writedata => Avalon_MM_Slave_writedata, Avalon_ST_Sink_data => Avalon_ST_Sink_data, Avalon_ST_Sink_endofpacket => Avalon_ST_Sink_endofpacket, Avalon_ST_Sink_ready => Avalon_ST_Sink_ready, Avalon_ST_Sink_startofpacket => Avalon_ST_Sink_startofpacket, Avalon_ST_Sink_valid => Avalon_ST_Sink_valid, Avalon_ST_Source_data => Avalon_ST_Source_data, Avalon_ST_Source_endofpacket => Avalon_ST_Source_endofpacket, Avalon_ST_Source_ready => Avalon_ST_Source_ready, Avalon_ST_Source_startofpacket => Avalon_ST_Source_startofpacket, Avalon_ST_Source_valid => Avalon_ST_Source_valid, Clock => Clock, aclr => aclr);
end generate;
end architecture rtl;
--altera translate_on
| mit | 597e67bf3ce34f4ca2c1f166274975dc | 0.709482 | 3.059671 | false | false | false | false |
takeshineshiro/fpga_fibre_scan | HUCB2P0_150701/pulse.vhd | 1 | 2,713 | --*****************************************************************************
-- @Copyright 2010 by guyoubao, All rights reserved.
-- Module name : Pulse control
-- Call by :
-- Description :
-- IC : EP3C16F484C6
-- Version : A
-- Note: :
-- Author : Weibao Qiu
-- Date : 2010.08.28
-- Update :
--
--
--
--*****************************************************************************
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity pulse is
port
(
I_clk : in std_logic;
I_reset : in std_logic;
I_pulse_trig : in std_logic;
O_pulse : out std_logic_vector(3 downto 0)
);
end pulse;
architecture ARC_pulse of pulse is
signal S_cnt : std_logic_vector(7 downto 0);
signal s_case : std_logic_vector(1 downto 0);
signal s_pulse_buf : std_logic;
signal s_pulse : std_logic_vector(3 downto 0);
begin
O_pulse <= s_pulse;
process(I_reset,I_clk)
begin
if I_reset = '0' then
s_case <= (others=>'0');
S_cnt <= (others=>'0');
s_pulse(0) <= '0';
s_pulse(1) <= '1';
s_pulse_buf <= '0';
elsif rising_edge(I_clk) then
s_pulse_buf <= I_pulse_trig;
case s_case is
when "00" =>
if(s_pulse_buf = '0' and I_pulse_trig = '1')then
s_case <= "01";
S_cnt <= S_cnt + '1';
else
s_case <= (others=>'0');
S_cnt <= (others=>'0');
s_pulse(0) <= '0';
s_pulse(1) <= '1';
end if;
when "01" =>
S_cnt <= S_cnt + '1';
if(S_cnt >= 4 and S_cnt <= 5)then
s_pulse(1) <= '0';
else
s_pulse(1) <= '1';
end if;
if(S_cnt >= 2 and S_cnt <= 3)then
s_pulse(0) <= '1';
else
s_pulse(0) <= '0';
end if;
if(S_cnt = 0)then
s_case <= (others=>'0');
end if;
when others =>
s_case <= (others=>'0');
S_cnt <= (others=>'0');
s_pulse(0) <= '0';
s_pulse(1) <= '1';
end case;
end if;
end process;
end ARC_pulse; | apache-2.0 | b9611cdb0f9170c42224390bd35e9c0e | 0.347954 | 3.691156 | false | false | false | false |
grwlf/vsim | vhdl_ct/ct00140.vhd | 1 | 20,307 | -- NEED RESULT: ARCH00140.P1: Multi inertial transactions occurred on signal asg with indexed name on LHS passed
-- NEED RESULT: ARCH00140.P2: Multi inertial transactions occurred on signal asg with indexed name on LHS passed
-- NEED RESULT: ARCH00140.P3: Multi inertial transactions occurred on signal asg with indexed name on LHS passed
-- NEED RESULT: ARCH00140: One inertial transaction occurred on signal asg with indexed name on LHS passed
-- NEED RESULT: ARCH00140: One inertial transaction occurred on signal asg with indexed name on LHS passed
-- NEED RESULT: ARCH00140: One inertial transaction occurred on signal asg with indexed name on LHS passed
-- NEED RESULT: ARCH00140: Old transactions were removed on signal asg with indexed name on LHS passed
-- NEED RESULT: ARCH00140: Old transactions were removed on signal asg with indexed name on LHS passed
-- NEED RESULT: ARCH00140: Old transactions were removed on signal asg with indexed name on LHS passed
-- NEED RESULT: ARCH00140: One inertial transaction occurred on signal asg with indexed name on LHS passed
-- NEED RESULT: ARCH00140: One inertial transaction occurred on signal asg with indexed name on LHS passed
-- NEED RESULT: ARCH00140: One inertial transaction occurred on signal asg with indexed name on LHS passed
-- NEED RESULT: ARCH00140: Inertial semantics check on a signal asg with indexed name on LHS passed
-- NEED RESULT: ARCH00140: Inertial semantics check on a signal asg with indexed name on LHS passed
-- NEED RESULT: ARCH00140: Inertial semantics check on a signal asg with indexed name on LHS passed
-- NEED RESULT: P3: Inertial transactions entirely completed passed
-- NEED RESULT: P2: Inertial transactions entirely completed passed
-- NEED RESULT: P1: Inertial transactions entirely completed passed
-------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
-------------------------------------------------------------------------------
--
-- TEST NAME:
--
-- CT00140
--
-- AUTHOR:
--
-- G. Tominovich
--
-- TEST OBJECTIVES:
--
-- 8.3 (1)
-- 8.3 (2)
-- 8.3 (4)
-- 8.3 (5)
-- 8.3.1 (4)
--
-- DESIGN UNIT ORDERING:
--
-- ENT00140(ARCH00140)
-- ENT00140_Test_Bench(ARCH00140_Test_Bench)
--
-- REVISION HISTORY:
--
-- 08-JUL-1987 - initial revision
--
-- NOTES:
--
-- self-checking
-- automatically generated
--
use WORK.STANDARD_TYPES.all ;
entity ENT00140 is
port (
s_st_arr1 : inout st_arr1
; s_st_arr2 : inout st_arr2
; s_st_arr3 : inout st_arr3
) ;
subtype chk_sig_type is integer range -1 to 100 ;
signal chk_st_arr1 : chk_sig_type := -1 ;
signal chk_st_arr2 : chk_sig_type := -1 ;
signal chk_st_arr3 : chk_sig_type := -1 ;
--
end ENT00140 ;
--
architecture ARCH00140 of ENT00140 is
begin
P1 :
process
variable correct : boolean ;
variable counter : integer := 0 ;
variable savtime : time ;
begin
case counter is
when 0 =>
s_st_arr1 (st_arr1'Left) <=
c_st_arr1_2 (st_arr1'Right) after 10 ns,
c_st_arr1_1 (st_arr1'Right) after 20 ns ;
--
when 1 =>
correct :=
s_st_arr1 (st_arr1'Left) =
c_st_arr1_2 (st_arr1'Right) and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2 =>
correct :=
correct and
s_st_arr1 (st_arr1'Left) =
c_st_arr1_1 (st_arr1'Right) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00140.P1" ,
"Multi inertial transactions occurred on signal " &
"asg with indexed name on LHS",
correct ) ;
s_st_arr1 (st_arr1'Left) <=
c_st_arr1_2 (st_arr1'Right) after 10 ns,
c_st_arr1_1 (st_arr1'Right) after 20 ns,
c_st_arr1_2 (st_arr1'Right) after 30 ns,
c_st_arr1_1 (st_arr1'Right) after 40 ns ;
--
when 3 =>
correct :=
s_st_arr1 (st_arr1'Left) =
c_st_arr1_2 (st_arr1'Right) and
(savtime + 10 ns) = Std.Standard.Now ;
s_st_arr1 (st_arr1'Left) <=
c_st_arr1_1 (st_arr1'Right) after 5 ns;
--
when 4 =>
correct :=
correct and
s_st_arr1 (st_arr1'Left) =
c_st_arr1_1 (st_arr1'Right) and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00140" ,
"One inertial transaction occurred on signal " &
"asg with indexed name on LHS",
correct ) ;
s_st_arr1 (st_arr1'Left) <= transport
c_st_arr1_1 (st_arr1'Right) after 100 ns;
--
when 5 =>
correct :=
s_st_arr1 (st_arr1'Left) =
c_st_arr1_1 (st_arr1'Right) and
(savtime + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00140" ,
"Old transactions were removed on signal " &
"asg with indexed name on LHS",
correct ) ;
s_st_arr1 (st_arr1'Left) <=
c_st_arr1_2 (st_arr1'Right) after 10 ns,
c_st_arr1_1 (st_arr1'Right) after 20 ns,
c_st_arr1_2 (st_arr1'Right) after 30 ns,
c_st_arr1_1 (st_arr1'Right) after 40 ns ;
--
when 6 =>
correct :=
s_st_arr1 (st_arr1'Left) =
c_st_arr1_2 (st_arr1'Right) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00140" ,
"One inertial transaction occurred on signal " &
"asg with indexed name on LHS",
correct ) ;
-- The following will mark last transaction above
s_st_arr1 (st_arr1'Left) <=
c_st_arr1_1 (st_arr1'Right) after 40 ns;
--
when 7 =>
correct :=
s_st_arr1 (st_arr1'Left) =
c_st_arr1_1 (st_arr1'Right) and
(savtime + 30 ns) = Std.Standard.Now ;
--
when 8 =>
correct :=
correct and
s_st_arr1 (st_arr1'Left) =
c_st_arr1_1 (st_arr1'Right) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00140" ,
"Inertial semantics check on a signal " &
"asg with indexed name on LHS",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00140" ,
"Inertial semantics check on a signal " &
"asg with indexed name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_st_arr1 <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
wait until (not s_st_arr1'Quiet) and
(savtime /= Std.Standard.Now) ;
--
end process P1 ;
--
PGEN_CHKP_1 :
process ( chk_st_arr1 )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P1" ,
"Inertial transactions entirely completed",
chk_st_arr1 = 8 ) ;
end if ;
end process PGEN_CHKP_1 ;
--
P2 :
process
variable correct : boolean ;
variable counter : integer := 0 ;
variable savtime : time ;
begin
case counter is
when 0 =>
s_st_arr2 (
st_arr2'Left(1),st_arr2'Left(2)) <=
c_st_arr2_2 (
st_arr2'Right(1),st_arr2'Right(2)) after 10 ns,
c_st_arr2_1 (
st_arr2'Right(1),st_arr2'Right(2)) after 20 ns ;
--
when 1 =>
correct :=
s_st_arr2 (
st_arr2'Left(1),st_arr2'Left(2)) =
c_st_arr2_2 (
st_arr2'Right(1),st_arr2'Right(2)) and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2 =>
correct :=
correct and
s_st_arr2 (
st_arr2'Left(1),st_arr2'Left(2)) =
c_st_arr2_1 (
st_arr2'Right(1),st_arr2'Right(2)) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00140.P2" ,
"Multi inertial transactions occurred on signal " &
"asg with indexed name on LHS",
correct ) ;
s_st_arr2 (
st_arr2'Left(1),st_arr2'Left(2)) <=
c_st_arr2_2 (
st_arr2'Right(1),st_arr2'Right(2)) after 10 ns,
c_st_arr2_1 (
st_arr2'Right(1),st_arr2'Right(2)) after 20 ns,
c_st_arr2_2 (
st_arr2'Right(1),st_arr2'Right(2)) after 30 ns,
c_st_arr2_1 (
st_arr2'Right(1),st_arr2'Right(2)) after 40 ns ;
--
when 3 =>
correct :=
s_st_arr2 (
st_arr2'Left(1),st_arr2'Left(2)) =
c_st_arr2_2 (
st_arr2'Right(1),st_arr2'Right(2)) and
(savtime + 10 ns) = Std.Standard.Now ;
s_st_arr2 (
st_arr2'Left(1),st_arr2'Left(2)) <=
c_st_arr2_1 (
st_arr2'Right(1),st_arr2'Right(2)) after 5 ns;
--
when 4 =>
correct :=
correct and
s_st_arr2 (
st_arr2'Left(1),st_arr2'Left(2)) =
c_st_arr2_1 (
st_arr2'Right(1),st_arr2'Right(2)) and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00140" ,
"One inertial transaction occurred on signal " &
"asg with indexed name on LHS",
correct ) ;
s_st_arr2 (
st_arr2'Left(1),st_arr2'Left(2)) <= transport
c_st_arr2_1 (
st_arr2'Right(1),st_arr2'Right(2)) after 100 ns;
--
when 5 =>
correct :=
s_st_arr2 (
st_arr2'Left(1),st_arr2'Left(2)) =
c_st_arr2_1 (
st_arr2'Right(1),st_arr2'Right(2)) and
(savtime + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00140" ,
"Old transactions were removed on signal " &
"asg with indexed name on LHS",
correct ) ;
s_st_arr2 (
st_arr2'Left(1),st_arr2'Left(2)) <=
c_st_arr2_2 (
st_arr2'Right(1),st_arr2'Right(2)) after 10 ns,
c_st_arr2_1 (
st_arr2'Right(1),st_arr2'Right(2)) after 20 ns,
c_st_arr2_2 (
st_arr2'Right(1),st_arr2'Right(2)) after 30 ns,
c_st_arr2_1 (
st_arr2'Right(1),st_arr2'Right(2)) after 40 ns ;
--
when 6 =>
correct :=
s_st_arr2 (
st_arr2'Left(1),st_arr2'Left(2)) =
c_st_arr2_2 (
st_arr2'Right(1),st_arr2'Right(2)) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00140" ,
"One inertial transaction occurred on signal " &
"asg with indexed name on LHS",
correct ) ;
-- The following will mark last transaction above
s_st_arr2 (
st_arr2'Left(1),st_arr2'Left(2)) <=
c_st_arr2_1 (
st_arr2'Right(1),st_arr2'Right(2)) after 40 ns;
--
when 7 =>
correct :=
s_st_arr2 (
st_arr2'Left(1),st_arr2'Left(2)) =
c_st_arr2_1 (
st_arr2'Right(1),st_arr2'Right(2)) and
(savtime + 30 ns) = Std.Standard.Now ;
--
when 8 =>
correct :=
correct and
s_st_arr2 (
st_arr2'Left(1),st_arr2'Left(2)) =
c_st_arr2_1 (
st_arr2'Right(1),st_arr2'Right(2)) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00140" ,
"Inertial semantics check on a signal " &
"asg with indexed name on LHS",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00140" ,
"Inertial semantics check on a signal " &
"asg with indexed name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_st_arr2 <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
wait until (not s_st_arr2'Quiet) and
(savtime /= Std.Standard.Now) ;
--
end process P2 ;
--
PGEN_CHKP_2 :
process ( chk_st_arr2 )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P2" ,
"Inertial transactions entirely completed",
chk_st_arr2 = 8 ) ;
end if ;
end process PGEN_CHKP_2 ;
--
P3 :
process
variable correct : boolean ;
variable counter : integer := 0 ;
variable savtime : time ;
begin
case counter is
when 0 =>
s_st_arr3 (
st_arr3'Left(1),st_arr3'Left(2)) <=
c_st_arr3_2 (
st_arr3'Right(1),st_arr3'Right(2)) after 10 ns,
c_st_arr3_1 (
st_arr3'Right(1),st_arr3'Right(2)) after 20 ns ;
--
when 1 =>
correct :=
s_st_arr3 (
st_arr3'Left(1),st_arr3'Left(2)) =
c_st_arr3_2 (
st_arr3'Right(1),st_arr3'Right(2)) and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2 =>
correct :=
correct and
s_st_arr3 (
st_arr3'Left(1),st_arr3'Left(2)) =
c_st_arr3_1 (
st_arr3'Right(1),st_arr3'Right(2)) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00140.P3" ,
"Multi inertial transactions occurred on signal " &
"asg with indexed name on LHS",
correct ) ;
s_st_arr3 (
st_arr3'Left(1),st_arr3'Left(2)) <=
c_st_arr3_2 (
st_arr3'Right(1),st_arr3'Right(2)) after 10 ns,
c_st_arr3_1 (
st_arr3'Right(1),st_arr3'Right(2)) after 20 ns,
c_st_arr3_2 (
st_arr3'Right(1),st_arr3'Right(2)) after 30 ns,
c_st_arr3_1 (
st_arr3'Right(1),st_arr3'Right(2)) after 40 ns ;
--
when 3 =>
correct :=
s_st_arr3 (
st_arr3'Left(1),st_arr3'Left(2)) =
c_st_arr3_2 (
st_arr3'Right(1),st_arr3'Right(2)) and
(savtime + 10 ns) = Std.Standard.Now ;
s_st_arr3 (
st_arr3'Left(1),st_arr3'Left(2)) <=
c_st_arr3_1 (
st_arr3'Right(1),st_arr3'Right(2)) after 5 ns;
--
when 4 =>
correct :=
correct and
s_st_arr3 (
st_arr3'Left(1),st_arr3'Left(2)) =
c_st_arr3_1 (
st_arr3'Right(1),st_arr3'Right(2)) and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00140" ,
"One inertial transaction occurred on signal " &
"asg with indexed name on LHS",
correct ) ;
s_st_arr3 (
st_arr3'Left(1),st_arr3'Left(2)) <= transport
c_st_arr3_1 (
st_arr3'Right(1),st_arr3'Right(2)) after 100 ns;
--
when 5 =>
correct :=
s_st_arr3 (
st_arr3'Left(1),st_arr3'Left(2)) =
c_st_arr3_1 (
st_arr3'Right(1),st_arr3'Right(2)) and
(savtime + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00140" ,
"Old transactions were removed on signal " &
"asg with indexed name on LHS",
correct ) ;
s_st_arr3 (
st_arr3'Left(1),st_arr3'Left(2)) <=
c_st_arr3_2 (
st_arr3'Right(1),st_arr3'Right(2)) after 10 ns,
c_st_arr3_1 (
st_arr3'Right(1),st_arr3'Right(2)) after 20 ns,
c_st_arr3_2 (
st_arr3'Right(1),st_arr3'Right(2)) after 30 ns,
c_st_arr3_1 (
st_arr3'Right(1),st_arr3'Right(2)) after 40 ns ;
--
when 6 =>
correct :=
s_st_arr3 (
st_arr3'Left(1),st_arr3'Left(2)) =
c_st_arr3_2 (
st_arr3'Right(1),st_arr3'Right(2)) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00140" ,
"One inertial transaction occurred on signal " &
"asg with indexed name on LHS",
correct ) ;
-- The following will mark last transaction above
s_st_arr3 (
st_arr3'Left(1),st_arr3'Left(2)) <=
c_st_arr3_1 (
st_arr3'Right(1),st_arr3'Right(2)) after 40 ns;
--
when 7 =>
correct :=
s_st_arr3 (
st_arr3'Left(1),st_arr3'Left(2)) =
c_st_arr3_1 (
st_arr3'Right(1),st_arr3'Right(2)) and
(savtime + 30 ns) = Std.Standard.Now ;
--
when 8 =>
correct :=
correct and
s_st_arr3 (
st_arr3'Left(1),st_arr3'Left(2)) =
c_st_arr3_1 (
st_arr3'Right(1),st_arr3'Right(2)) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00140" ,
"Inertial semantics check on a signal " &
"asg with indexed name on LHS",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00140" ,
"Inertial semantics check on a signal " &
"asg with indexed name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_st_arr3 <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
wait until (not s_st_arr3'Quiet) and
(savtime /= Std.Standard.Now) ;
--
end process P3 ;
--
PGEN_CHKP_3 :
process ( chk_st_arr3 )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P3" ,
"Inertial transactions entirely completed",
chk_st_arr3 = 8 ) ;
end if ;
end process PGEN_CHKP_3 ;
--
--
end ARCH00140 ;
--
use WORK.STANDARD_TYPES.all ;
entity ENT00140_Test_Bench is
signal s_st_arr1 : st_arr1
:= c_st_arr1_1 ;
signal s_st_arr2 : st_arr2
:= c_st_arr2_1 ;
signal s_st_arr3 : st_arr3
:= c_st_arr3_1 ;
--
end ENT00140_Test_Bench ;
--
architecture ARCH00140_Test_Bench of ENT00140_Test_Bench is
begin
L1:
block
component UUT
port (
s_st_arr1 : inout st_arr1
; s_st_arr2 : inout st_arr2
; s_st_arr3 : inout st_arr3
) ;
end component ;
--
for CIS1 : UUT use entity WORK.ENT00140 ( ARCH00140 ) ;
begin
CIS1 : UUT
port map (
s_st_arr1
, s_st_arr2
, s_st_arr3
) ;
end block L1 ;
end ARCH00140_Test_Bench ;
| gpl-3.0 | 5fffb193e3b6d39a86f325ddb6f3ffb2 | 0.46772 | 3.532881 | false | true | false | false |
grwlf/vsim | vhdl_ct/ct00064.vhd | 1 | 4,606 | -- NEED RESULT: ARCH00064.P1_1: Next with no label or condition only effects innermost (labeled) loop passed
-- NEED RESULT: ARCH00064.P1_1: Next with no label or condition only effects innermost (unlabeled) loop passed
-- NEED RESULT: ARCH00064.P1_1: Next with no label or condition only effects innermost (labeled) loop passed
-- NEED RESULT: ARCH00064.P1_1: Next with no label or condition only effects innermost (unlabeled) loop passed
-- NEED RESULT: ARCH00064.P1_1: Next statement does not effect outer loop passed
-- NEED RESULT: ARCH00064.P1_2: Next with no label only effects innermost (unlabeled) loop passed
-- NEED RESULT: ARCH00064.P1_2: Next with no label only effects innermost (labeled) loop passed
-- NEED RESULT: ARCH00064.P1_2: Next statement does not effect outer loop passed
-------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
-------------------------------------------------------------------------------
--
-- TEST NAME:
--
-- CT00064
--
-- AUTHOR:
--
-- G. Tominovich
--
-- TEST OBJECTIVES:
--
-- 8.9 (1)
-- 8.9 (3)
-- 8.9 (4)
--
-- DESIGN UNIT ORDERING:
--
-- E00000(ARCH00064)
-- ENT00064_Test_Bench(ARCH00064_Test_Bench)
--
-- REVISION HISTORY:
--
-- 06-JUL-1987 - initial revision
--
-- NOTES:
--
-- self-checking
-- automatically generated
--
use WORK.STANDARD_TYPES.all ;
architecture ARCH00064 of E00000 is
signal Dummy : Boolean := false ;
begin
P1_1 :
process ( Dummy )
variable correct : boolean ;
variable counter : integer := 0 ;
variable done : boolean := false ;
begin
L1 :
for i in boolean loop
--
correct := true ;
L2 :
for j in 1 to 3 loop
next ;
correct := false ;
end loop L2 ;
--
test_report ( "ARCH00064.P1_1" ,
"Next with no label or condition only effects " &
"innermost (labeled) loop",
correct ) ;
--
correct := true ;
while not done loop
done := true ;
next ;
correct := false ;
end loop ;
--
test_report ( "ARCH00064.P1_1" ,
"Next with no label or condition only effects " &
"innermost (unlabeled) loop",
correct ) ;
--
counter := counter + 1 ;
--
end loop L1 ;
correct := counter =
(boolean'Pos (boolean'High) -
boolean'Pos (boolean'Low) + 1) ;
test_report ( "ARCH00064.P1_1" ,
"Next statement does not effect outer " &
"loop",
correct ) ;
--
end process P1_1 ;
--
P1_2 :
process ( Dummy )
variable correct : boolean := true ;
variable counter : integer := 0 ;
variable done : boolean := false ;
variable v_boolean : boolean :=
c_boolean_1 ;
--
begin
L1 :
while v_boolean /= boolean'High loop
--
correct := true ;
for j in 1 to 3 loop
next when j = j ;
correct := false ;
end loop ;
--
test_report ( "ARCH00064.P1_2" ,
"Next with no label only effects " &
"innermost (unlabeled) loop",
correct ) ;
--
correct := true ;
L2 :
while not done loop
done := true ;
next when done = done ;
correct := false ;
end loop L2 ;
--
test_report ( "ARCH00064.P1_2" ,
"Next with no label only effects " &
"innermost (labeled) loop",
correct ) ;
--
v_boolean :=
boolean'Succ (v_boolean) ;
counter := counter + 1 ;
--
end loop L1 ;
correct := counter =
(boolean'Pos (boolean'High) -
boolean'Pos (c_boolean_1) ) ;
test_report ( "ARCH00064.P1_2" ,
"Next statement does not effect outer " &
"loop",
correct ) ;
--
end process P1_2 ;
--
--
end ARCH00064 ;
--
entity ENT00064_Test_Bench is
end ENT00064_Test_Bench ;
--
architecture ARCH00064_Test_Bench of ENT00064_Test_Bench is
begin
L1:
block
component UUT
end component ;
for CIS1 : UUT use entity WORK.E00000 ( ARCH00064 ) ;
begin
CIS1 : UUT ;
end block L1 ;
end ARCH00064_Test_Bench ;
| gpl-3.0 | 9fa21ba015dcb6b41e41f7e96842c9c9 | 0.508467 | 3.877104 | false | true | false | false |
jairov4/accel-oil | solution_virtex5_plb/syn/vhdl/sample_iterator_next.vhd | 1 | 7,901 | -- ==============================================================
-- RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2014.1
-- Copyright (C) 2014 Xilinx Inc. All rights reserved.
--
-- ===========================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity sample_iterator_next is
port (
ap_clk : IN STD_LOGIC;
ap_rst : IN STD_LOGIC;
ap_start : IN STD_LOGIC;
ap_done : OUT STD_LOGIC;
ap_idle : OUT STD_LOGIC;
ap_ready : OUT STD_LOGIC;
indices_req_din : OUT STD_LOGIC;
indices_req_full_n : IN STD_LOGIC;
indices_req_write : OUT STD_LOGIC;
indices_rsp_empty_n : IN STD_LOGIC;
indices_rsp_read : OUT STD_LOGIC;
indices_address : OUT STD_LOGIC_VECTOR (31 downto 0);
indices_datain : IN STD_LOGIC_VECTOR (55 downto 0);
indices_dataout : OUT STD_LOGIC_VECTOR (55 downto 0);
indices_size : OUT STD_LOGIC_VECTOR (31 downto 0);
i_index : IN STD_LOGIC_VECTOR (15 downto 0);
i_sample : IN STD_LOGIC_VECTOR (15 downto 0);
ap_return_0 : OUT STD_LOGIC_VECTOR (15 downto 0);
ap_return_1 : OUT STD_LOGIC_VECTOR (15 downto 0) );
end;
architecture behav of sample_iterator_next is
constant ap_const_logic_1 : STD_LOGIC := '1';
constant ap_const_logic_0 : STD_LOGIC := '0';
constant ap_ST_st1_fsm_0 : STD_LOGIC_VECTOR (1 downto 0) := "00";
constant ap_ST_st2_fsm_1 : STD_LOGIC_VECTOR (1 downto 0) := "01";
constant ap_ST_st3_fsm_2 : STD_LOGIC_VECTOR (1 downto 0) := "10";
constant ap_ST_st4_fsm_3 : STD_LOGIC_VECTOR (1 downto 0) := "11";
constant ap_const_lv32_1 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000001";
constant ap_const_lv32_20 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000100000";
constant ap_const_lv32_2F : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000101111";
constant ap_const_lv17_1FFFF : STD_LOGIC_VECTOR (16 downto 0) := "11111111111111111";
constant ap_const_lv16_1 : STD_LOGIC_VECTOR (15 downto 0) := "0000000000000001";
constant ap_const_lv16_0 : STD_LOGIC_VECTOR (15 downto 0) := "0000000000000000";
constant ap_const_lv56_0 : STD_LOGIC_VECTOR (55 downto 0) := "00000000000000000000000000000000000000000000000000000000";
signal ap_CS_fsm : STD_LOGIC_VECTOR (1 downto 0) := "00";
signal indices_samples_load_new5_reg_161 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_s_fu_67_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_9_cast_fu_92_p1 : STD_LOGIC_VECTOR (16 downto 0);
signal tmp_4_fu_95_p2 : STD_LOGIC_VECTOR (16 downto 0);
signal tmp_cast_fu_88_p1 : STD_LOGIC_VECTOR (17 downto 0);
signal tmp_5_fu_105_p1 : STD_LOGIC_VECTOR (17 downto 0);
signal tmp_4_fu_95_p2_temp: signed (17-1 downto 0);
signal tmp_5_fu_105_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_7_fu_116_p2 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_6_fu_111_p2 : STD_LOGIC_VECTOR (15 downto 0);
signal agg_result_index_write_assign_fu_130_p3 : STD_LOGIC_VECTOR (15 downto 0);
signal agg_result_sample_write_assign_fu_122_p3 : STD_LOGIC_VECTOR (15 downto 0);
signal ap_NS_fsm : STD_LOGIC_VECTOR (1 downto 0);
begin
-- the current state (ap_CS_fsm) of the state machine. --
ap_CS_fsm_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_CS_fsm <= ap_ST_st1_fsm_0;
else
ap_CS_fsm <= ap_NS_fsm;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ST_st3_fsm_2 = ap_CS_fsm) and not((indices_rsp_empty_n = ap_const_logic_0)))) then
indices_samples_load_new5_reg_161 <= indices_datain(47 downto 32);
end if;
end if;
end process;
-- the next state (ap_NS_fsm) of the state machine. --
ap_NS_fsm_assign_proc : process (ap_start , ap_CS_fsm , indices_rsp_empty_n)
begin
case ap_CS_fsm is
when ap_ST_st1_fsm_0 =>
if (not((ap_start = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st2_fsm_1;
else
ap_NS_fsm <= ap_ST_st1_fsm_0;
end if;
when ap_ST_st2_fsm_1 =>
ap_NS_fsm <= ap_ST_st3_fsm_2;
when ap_ST_st3_fsm_2 =>
if (not((indices_rsp_empty_n = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st4_fsm_3;
else
ap_NS_fsm <= ap_ST_st3_fsm_2;
end if;
when ap_ST_st4_fsm_3 =>
ap_NS_fsm <= ap_ST_st1_fsm_0;
when others =>
ap_NS_fsm <= "XX";
end case;
end process;
agg_result_index_write_assign_fu_130_p3 <=
i_index when (tmp_5_fu_105_p2(0) = '1') else
tmp_6_fu_111_p2;
agg_result_sample_write_assign_fu_122_p3 <=
tmp_7_fu_116_p2 when (tmp_5_fu_105_p2(0) = '1') else
ap_const_lv16_0;
-- ap_done assign process. --
ap_done_assign_proc : process(ap_start, ap_CS_fsm)
begin
if (((not((ap_const_logic_1 = ap_start)) and (ap_ST_st1_fsm_0 = ap_CS_fsm)) or (ap_ST_st4_fsm_3 = ap_CS_fsm))) then
ap_done <= ap_const_logic_1;
else
ap_done <= ap_const_logic_0;
end if;
end process;
-- ap_idle assign process. --
ap_idle_assign_proc : process(ap_start, ap_CS_fsm)
begin
if ((not((ap_const_logic_1 = ap_start)) and (ap_ST_st1_fsm_0 = ap_CS_fsm))) then
ap_idle <= ap_const_logic_1;
else
ap_idle <= ap_const_logic_0;
end if;
end process;
-- ap_ready assign process. --
ap_ready_assign_proc : process(ap_CS_fsm)
begin
if ((ap_ST_st4_fsm_3 = ap_CS_fsm)) then
ap_ready <= ap_const_logic_1;
else
ap_ready <= ap_const_logic_0;
end if;
end process;
ap_return_0 <= agg_result_index_write_assign_fu_130_p3;
ap_return_1 <= agg_result_sample_write_assign_fu_122_p3;
indices_address <= tmp_s_fu_67_p1(32 - 1 downto 0);
indices_dataout <= ap_const_lv56_0;
indices_req_din <= ap_const_logic_0;
-- indices_req_write assign process. --
indices_req_write_assign_proc : process(ap_start, ap_CS_fsm)
begin
if (((ap_ST_st1_fsm_0 = ap_CS_fsm) and not((ap_start = ap_const_logic_0)))) then
indices_req_write <= ap_const_logic_1;
else
indices_req_write <= ap_const_logic_0;
end if;
end process;
-- indices_rsp_read assign process. --
indices_rsp_read_assign_proc : process(ap_CS_fsm, indices_rsp_empty_n)
begin
if (((ap_ST_st3_fsm_2 = ap_CS_fsm) and not((indices_rsp_empty_n = ap_const_logic_0)))) then
indices_rsp_read <= ap_const_logic_1;
else
indices_rsp_read <= ap_const_logic_0;
end if;
end process;
indices_size <= ap_const_lv32_1;
tmp_4_fu_95_p2 <= std_logic_vector(unsigned(tmp_9_cast_fu_92_p1) + unsigned(ap_const_lv17_1FFFF));
tmp_4_fu_95_p2_temp <= signed(tmp_4_fu_95_p2);
tmp_5_fu_105_p1 <= std_logic_vector(resize(tmp_4_fu_95_p2_temp,18));
tmp_5_fu_105_p2 <= "1" when (signed(tmp_cast_fu_88_p1) < signed(tmp_5_fu_105_p1)) else "0";
tmp_6_fu_111_p2 <= std_logic_vector(unsigned(i_index) + unsigned(ap_const_lv16_1));
tmp_7_fu_116_p2 <= std_logic_vector(unsigned(i_sample) + unsigned(ap_const_lv16_1));
tmp_9_cast_fu_92_p1 <= std_logic_vector(resize(unsigned(indices_samples_load_new5_reg_161),17));
tmp_cast_fu_88_p1 <= std_logic_vector(resize(unsigned(i_sample),18));
tmp_s_fu_67_p1 <= std_logic_vector(resize(unsigned(i_index),64));
end behav;
| lgpl-3.0 | 071c5fc98d5a4edea41d89a2b1dcd962 | 0.583091 | 3.006469 | false | false | false | false |
grwlf/vsim | vhdl_ct/ct00058.vhd | 1 | 11,405 | -- NEED RESULT: ARCH00058.P1: While condition in loop is evaluated prior to execution of loop body passed
-- NEED RESULT: ARCH00058.P2: While condition in loop is evaluated prior to execution of loop body passed
-- NEED RESULT: ARCH00058.P3: While condition in loop is evaluated prior to execution of loop body passed
-- NEED RESULT: ARCH00058.P4: While condition in loop is evaluated prior to execution of loop body passed
-- NEED RESULT: ARCH00058.P5: While condition in loop is evaluated prior to execution of loop body passed
-- NEED RESULT: ARCH00058.P6: While condition in loop is evaluated prior to execution of loop body passed
-- NEED RESULT: ARCH00058.P7: While condition in loop is evaluated prior to execution of loop body passed
-- NEED RESULT: ARCH00058.P8: While condition in loop is evaluated prior to execution of loop body passed
-- NEED RESULT: ARCH00058.P9: While condition in loop is evaluated prior to execution of loop body passed
-- NEED RESULT: ARCH00058.P10: While condition in loop is evaluated prior to execution of loop body passed
-- NEED RESULT: ARCH00058.P11: While condition in loop is evaluated prior to execution of loop body passed
-- NEED RESULT: ARCH00058.P12: While condition in loop is evaluated prior to execution of loop body passed
-- NEED RESULT: ARCH00058.P13: While condition in loop is evaluated prior to execution of loop body passed
-- NEED RESULT: ARCH00058.P14: While condition in loop is evaluated prior to execution of loop body passed
-- NEED RESULT: ARCH00058.P15: While condition in loop is evaluated prior to execution of loop body passed
-- NEED RESULT: ARCH00058.P16: While condition in loop is evaluated prior to execution of loop body passed
-- NEED RESULT: ARCH00058.P17: While condition in loop is evaluated prior to execution of loop body passed
-------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
-------------------------------------------------------------------------------
--
-- TEST NAME:
--
-- CT00058
--
-- AUTHOR:
--
-- G. Tominovich
--
-- TEST OBJECTIVES:
--
-- 8.8 (3)
--
-- DESIGN UNIT ORDERING:
--
-- E00000(ARCH00058)
-- ENT00058_Test_Bench(ARCH00058_Test_Bench)
--
-- REVISION HISTORY:
--
-- 02-JUL-1987 - initial revision
--
-- NOTES:
--
-- self-checking
-- automatically generated
--
use WORK.STANDARD_TYPES.all ;
architecture ARCH00058 of E00000 is
signal Dummy : Boolean := false ;
begin
P1 :
process ( Dummy )
variable correct : boolean := true ;
variable v_boolean : boolean :=
c_boolean_1 ;
--
begin
L1 :
while v_boolean /= c_boolean_1 loop
correct := false ;
v_boolean := c_boolean_2 ;
end loop L1 ;
test_report ( "ARCH00058.P1" ,
"While condition in loop is evaluated prior to " &
"execution of loop body",
correct ) ;
--
end process P1 ;
--
P2 :
process ( Dummy )
variable correct : boolean := true ;
variable v_bit : bit :=
c_bit_1 ;
--
begin
L1 :
while v_bit /= c_bit_1 loop
correct := false ;
v_bit := c_bit_2 ;
end loop L1 ;
test_report ( "ARCH00058.P2" ,
"While condition in loop is evaluated prior to " &
"execution of loop body",
correct ) ;
--
end process P2 ;
--
P3 :
process ( Dummy )
variable correct : boolean := true ;
variable v_severity_level : severity_level :=
c_severity_level_1 ;
--
begin
L1 :
while v_severity_level /= c_severity_level_1 loop
correct := false ;
v_severity_level := c_severity_level_2 ;
end loop L1 ;
test_report ( "ARCH00058.P3" ,
"While condition in loop is evaluated prior to " &
"execution of loop body",
correct ) ;
--
end process P3 ;
--
P4 :
process ( Dummy )
variable correct : boolean := true ;
variable v_character : character :=
c_character_1 ;
--
begin
L1 :
while v_character /= c_character_1 loop
correct := false ;
v_character := c_character_2 ;
end loop L1 ;
test_report ( "ARCH00058.P4" ,
"While condition in loop is evaluated prior to " &
"execution of loop body",
correct ) ;
--
end process P4 ;
--
P5 :
process ( Dummy )
variable correct : boolean := true ;
variable v_st_enum1 : st_enum1 :=
c_st_enum1_1 ;
--
begin
L1 :
while v_st_enum1 /= c_st_enum1_1 loop
correct := false ;
v_st_enum1 := c_st_enum1_2 ;
end loop L1 ;
test_report ( "ARCH00058.P5" ,
"While condition in loop is evaluated prior to " &
"execution of loop body",
correct ) ;
--
end process P5 ;
--
P6 :
process ( Dummy )
variable correct : boolean := true ;
variable v_integer : integer :=
c_integer_1 ;
--
begin
L1 :
while v_integer /= c_integer_1 loop
correct := false ;
v_integer := c_integer_2 ;
end loop L1 ;
test_report ( "ARCH00058.P6" ,
"While condition in loop is evaluated prior to " &
"execution of loop body",
correct ) ;
--
end process P6 ;
--
P7 :
process ( Dummy )
variable correct : boolean := true ;
variable v_st_int1 : st_int1 :=
c_st_int1_1 ;
--
begin
L1 :
while v_st_int1 /= c_st_int1_1 loop
correct := false ;
v_st_int1 := c_st_int1_2 ;
end loop L1 ;
test_report ( "ARCH00058.P7" ,
"While condition in loop is evaluated prior to " &
"execution of loop body",
correct ) ;
--
end process P7 ;
--
P8 :
process ( Dummy )
variable correct : boolean := true ;
variable v_time : time :=
c_time_1 ;
--
begin
L1 :
while v_time /= c_time_1 loop
correct := false ;
v_time := c_time_2 ;
end loop L1 ;
test_report ( "ARCH00058.P8" ,
"While condition in loop is evaluated prior to " &
"execution of loop body",
correct ) ;
--
end process P8 ;
--
P9 :
process ( Dummy )
variable correct : boolean := true ;
variable v_st_phys1 : st_phys1 :=
c_st_phys1_1 ;
--
begin
L1 :
while v_st_phys1 /= c_st_phys1_1 loop
correct := false ;
v_st_phys1 := c_st_phys1_2 ;
end loop L1 ;
test_report ( "ARCH00058.P9" ,
"While condition in loop is evaluated prior to " &
"execution of loop body",
correct ) ;
--
end process P9 ;
--
P10 :
process ( Dummy )
variable correct : boolean := true ;
variable v_real : real :=
c_real_1 ;
--
begin
L1 :
while v_real /= c_real_1 loop
correct := false ;
v_real := c_real_2 ;
end loop L1 ;
test_report ( "ARCH00058.P10" ,
"While condition in loop is evaluated prior to " &
"execution of loop body",
correct ) ;
--
end process P10 ;
--
P11 :
process ( Dummy )
variable correct : boolean := true ;
variable v_st_real1 : st_real1 :=
c_st_real1_1 ;
--
begin
L1 :
while v_st_real1 /= c_st_real1_1 loop
correct := false ;
v_st_real1 := c_st_real1_2 ;
end loop L1 ;
test_report ( "ARCH00058.P11" ,
"While condition in loop is evaluated prior to " &
"execution of loop body",
correct ) ;
--
end process P11 ;
--
P12 :
process ( Dummy )
variable correct : boolean := true ;
variable v_st_rec1 : st_rec1 :=
c_st_rec1_1 ;
--
begin
L1 :
while v_st_rec1 /= c_st_rec1_1 loop
correct := false ;
v_st_rec1 := c_st_rec1_2 ;
end loop L1 ;
test_report ( "ARCH00058.P12" ,
"While condition in loop is evaluated prior to " &
"execution of loop body",
correct ) ;
--
end process P12 ;
--
P13 :
process ( Dummy )
variable correct : boolean := true ;
variable v_st_rec2 : st_rec2 :=
c_st_rec2_1 ;
--
begin
L1 :
while v_st_rec2 /= c_st_rec2_1 loop
correct := false ;
v_st_rec2 := c_st_rec2_2 ;
end loop L1 ;
test_report ( "ARCH00058.P13" ,
"While condition in loop is evaluated prior to " &
"execution of loop body",
correct ) ;
--
end process P13 ;
--
P14 :
process ( Dummy )
variable correct : boolean := true ;
variable v_st_rec3 : st_rec3 :=
c_st_rec3_1 ;
--
begin
L1 :
while v_st_rec3 /= c_st_rec3_1 loop
correct := false ;
v_st_rec3 := c_st_rec3_2 ;
end loop L1 ;
test_report ( "ARCH00058.P14" ,
"While condition in loop is evaluated prior to " &
"execution of loop body",
correct ) ;
--
end process P14 ;
--
P15 :
process ( Dummy )
variable correct : boolean := true ;
variable v_st_arr1 : st_arr1 :=
c_st_arr1_1 ;
--
begin
L1 :
while v_st_arr1 /= c_st_arr1_1 loop
correct := false ;
v_st_arr1 := c_st_arr1_2 ;
end loop L1 ;
test_report ( "ARCH00058.P15" ,
"While condition in loop is evaluated prior to " &
"execution of loop body",
correct ) ;
--
end process P15 ;
--
P16 :
process ( Dummy )
variable correct : boolean := true ;
variable v_st_arr2 : st_arr2 :=
c_st_arr2_1 ;
--
begin
L1 :
while v_st_arr2 /= c_st_arr2_1 loop
correct := false ;
v_st_arr2 := c_st_arr2_2 ;
end loop L1 ;
test_report ( "ARCH00058.P16" ,
"While condition in loop is evaluated prior to " &
"execution of loop body",
correct ) ;
--
end process P16 ;
--
P17 :
process ( Dummy )
variable correct : boolean := true ;
variable v_st_arr3 : st_arr3 :=
c_st_arr3_1 ;
--
begin
L1 :
while v_st_arr3 /= c_st_arr3_1 loop
correct := false ;
v_st_arr3 := c_st_arr3_2 ;
end loop L1 ;
test_report ( "ARCH00058.P17" ,
"While condition in loop is evaluated prior to " &
"execution of loop body",
correct ) ;
--
end process P17 ;
--
--
end ARCH00058 ;
--
entity ENT00058_Test_Bench is
end ENT00058_Test_Bench ;
--
architecture ARCH00058_Test_Bench of ENT00058_Test_Bench is
begin
L1:
block
component UUT
end component ;
for CIS1 : UUT use entity WORK.E00000 ( ARCH00058 ) ;
begin
CIS1 : UUT ;
end block L1 ;
end ARCH00058_Test_Bench ;
| gpl-3.0 | 44d03b4eb2ca0d66eb8a86ee8e045623 | 0.528452 | 3.713774 | false | true | false | false |
jairov4/accel-oil | impl/impl_test_pcie/simulation/behavioral/system_xps_central_dma_1_wrapper.vhd | 1 | 10,201 | -------------------------------------------------------------------------------
-- system_xps_central_dma_1_wrapper.vhd
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
library xps_central_dma_v2_03_a;
use xps_central_dma_v2_03_a.all;
entity system_xps_central_dma_1_wrapper is
port (
SPLB_Clk : in std_logic;
SPLB_Rst : in std_logic;
MPLB_Clk : in std_logic;
MPLB_Rst : in std_logic;
SPLB_ABus : in std_logic_vector(0 to 31);
SPLB_BE : in std_logic_vector(0 to 7);
SPLB_UABus : in std_logic_vector(0 to 31);
SPLB_PAValid : in std_logic;
SPLB_SAValid : in std_logic;
SPLB_rdPrim : in std_logic;
SPLB_wrPrim : in std_logic;
SPLB_masterID : in std_logic_vector(0 to 2);
SPLB_abort : in std_logic;
SPLB_busLock : in std_logic;
SPLB_RNW : in std_logic;
SPLB_MSize : in std_logic_vector(0 to 1);
SPLB_size : in std_logic_vector(0 to 3);
SPLB_type : in std_logic_vector(0 to 2);
SPLB_lockErr : in std_logic;
SPLB_wrDBus : in std_logic_vector(0 to 63);
SPLB_wrBurst : in std_logic;
SPLB_rdBurst : in std_logic;
SPLB_wrPendReq : in std_logic;
SPLB_rdPendReq : in std_logic;
SPLB_wrPendPri : in std_logic_vector(0 to 1);
SPLB_rdPendPri : in std_logic_vector(0 to 1);
SPLB_reqPri : in std_logic_vector(0 to 1);
SPLB_TAttribute : in std_logic_vector(0 to 15);
Sl_addrAck : out std_logic;
Sl_SSize : out std_logic_vector(0 to 1);
Sl_wait : out std_logic;
Sl_rearbitrate : out std_logic;
Sl_wrDAck : out std_logic;
Sl_wrComp : out std_logic;
Sl_wrBTerm : out std_logic;
Sl_rdDBus : out std_logic_vector(0 to 63);
Sl_rdWdAddr : out std_logic_vector(0 to 3);
Sl_rdDAck : out std_logic;
Sl_rdComp : out std_logic;
Sl_rdBTerm : out std_logic;
Sl_MBusy : out std_logic_vector(0 to 5);
Sl_MWrErr : out std_logic_vector(0 to 5);
Sl_MRdErr : out std_logic_vector(0 to 5);
Sl_MIRQ : out std_logic_vector(0 to 5);
IP2INTC_Irpt : out std_logic;
MPLB_MAddrAck : in std_logic;
MPLB_MSSize : in std_logic_vector(0 to 1);
MPLB_MRearbitrate : in std_logic;
MPLB_MTimeout : in std_logic;
MPLB_MBusy : in std_logic;
MPLB_MRdErr : in std_logic;
MPLB_MWrErr : in std_logic;
MPLB_MIRQ : in std_logic;
MPLB_MRdDBus : in std_logic_vector(0 to 63);
MPLB_MRdWdAddr : in std_logic_vector(0 to 3);
MPLB_MRdDAck : in std_logic;
MPLB_MRdBTerm : in std_logic;
MPLB_MWrDAck : in std_logic;
MPLB_MWrBTerm : in std_logic;
M_request : out std_logic;
M_priority : out std_logic_vector(0 to 1);
M_busLock : out std_logic;
M_RNW : out std_logic;
M_BE : out std_logic_vector(0 to 7);
M_MSize : out std_logic_vector(0 to 1);
M_size : out std_logic_vector(0 to 3);
M_type : out std_logic_vector(0 to 2);
M_TAttribute : out std_logic_vector(0 to 15);
M_lockErr : out std_logic;
M_abort : out std_logic;
M_UABus : out std_logic_vector(0 to 31);
M_ABus : out std_logic_vector(0 to 31);
M_wrDBus : out std_logic_vector(0 to 63);
M_wrBurst : out std_logic;
M_rdBurst : out std_logic
);
end system_xps_central_dma_1_wrapper;
architecture STRUCTURE of system_xps_central_dma_1_wrapper is
component xps_central_dma is
generic (
C_FIFO_DEPTH : INTEGER;
C_RD_BURST_SIZE : INTEGER;
C_WR_BURST_SIZE : INTEGER;
C_BASEADDR : std_logic_vector;
C_HIGHADDR : std_logic_vector;
C_SPLB_DWIDTH : INTEGER;
C_SPLB_AWIDTH : INTEGER;
C_SPLB_NUM_MASTERS : INTEGER;
C_SPLB_MID_WIDTH : INTEGER;
C_SPLB_P2P : INTEGER;
C_SPLB_NATIVE_DWIDTH : INTEGER;
C_MPLB_NATIVE_DWIDTH : INTEGER;
C_SPLB_SUPPORT_BURSTS : INTEGER;
C_MPLB_AWIDTH : INTEGER;
C_MPLB_DWIDTH : INTEGER;
C_FAMILY : STRING
);
port (
SPLB_Clk : in std_logic;
SPLB_Rst : in std_logic;
MPLB_Clk : in std_logic;
MPLB_Rst : in std_logic;
SPLB_ABus : in std_logic_vector(0 to (C_SPLB_AWIDTH-1));
SPLB_BE : in std_logic_vector(0 to ((C_SPLB_DWIDTH/8)-1));
SPLB_UABus : in std_logic_vector(0 to 31);
SPLB_PAValid : in std_logic;
SPLB_SAValid : in std_logic;
SPLB_rdPrim : in std_logic;
SPLB_wrPrim : in std_logic;
SPLB_masterID : in std_logic_vector(0 to (C_SPLB_MID_WIDTH-1));
SPLB_abort : in std_logic;
SPLB_busLock : in std_logic;
SPLB_RNW : in std_logic;
SPLB_MSize : in std_logic_vector(0 to 1);
SPLB_size : in std_logic_vector(0 to 3);
SPLB_type : in std_logic_vector(0 to 2);
SPLB_lockErr : in std_logic;
SPLB_wrDBus : in std_logic_vector(0 to (C_SPLB_DWIDTH-1));
SPLB_wrBurst : in std_logic;
SPLB_rdBurst : in std_logic;
SPLB_wrPendReq : in std_logic;
SPLB_rdPendReq : in std_logic;
SPLB_wrPendPri : in std_logic_vector(0 to 1);
SPLB_rdPendPri : in std_logic_vector(0 to 1);
SPLB_reqPri : in std_logic_vector(0 to 1);
SPLB_TAttribute : in std_logic_vector(0 to 15);
Sl_addrAck : out std_logic;
Sl_SSize : out std_logic_vector(0 to 1);
Sl_wait : out std_logic;
Sl_rearbitrate : out std_logic;
Sl_wrDAck : out std_logic;
Sl_wrComp : out std_logic;
Sl_wrBTerm : out std_logic;
Sl_rdDBus : out std_logic_vector(0 to (C_SPLB_DWIDTH-1));
Sl_rdWdAddr : out std_logic_vector(0 to 3);
Sl_rdDAck : out std_logic;
Sl_rdComp : out std_logic;
Sl_rdBTerm : out std_logic;
Sl_MBusy : out std_logic_vector(0 to (C_SPLB_NUM_MASTERS-1));
Sl_MWrErr : out std_logic_vector(0 to (C_SPLB_NUM_MASTERS-1));
Sl_MRdErr : out std_logic_vector(0 to (C_SPLB_NUM_MASTERS-1));
Sl_MIRQ : out std_logic_vector(0 to (C_SPLB_NUM_MASTERS-1));
IP2INTC_Irpt : out std_logic;
MPLB_MAddrAck : in std_logic;
MPLB_MSSize : in std_logic_vector(0 to 1);
MPLB_MRearbitrate : in std_logic;
MPLB_MTimeout : in std_logic;
MPLB_MBusy : in std_logic;
MPLB_MRdErr : in std_logic;
MPLB_MWrErr : in std_logic;
MPLB_MIRQ : in std_logic;
MPLB_MRdDBus : in std_logic_vector(0 to (C_MPLB_DWIDTH-1));
MPLB_MRdWdAddr : in std_logic_vector(0 to 3);
MPLB_MRdDAck : in std_logic;
MPLB_MRdBTerm : in std_logic;
MPLB_MWrDAck : in std_logic;
MPLB_MWrBTerm : in std_logic;
M_request : out std_logic;
M_priority : out std_logic_vector(0 to 1);
M_busLock : out std_logic;
M_RNW : out std_logic;
M_BE : out std_logic_vector(0 to ((C_MPLB_DWIDTH/8)-1));
M_MSize : out std_logic_vector(0 to 1);
M_size : out std_logic_vector(0 to 3);
M_type : out std_logic_vector(0 to 2);
M_TAttribute : out std_logic_vector(0 to 15);
M_lockErr : out std_logic;
M_abort : out std_logic;
M_UABus : out std_logic_vector(0 to 31);
M_ABus : out std_logic_vector(0 to (C_MPLB_AWIDTH-1));
M_wrDBus : out std_logic_vector(0 to (C_MPLB_DWIDTH-1));
M_wrBurst : out std_logic;
M_rdBurst : out std_logic
);
end component;
begin
xps_central_dma_1 : xps_central_dma
generic map (
C_FIFO_DEPTH => 8,
C_RD_BURST_SIZE => 8,
C_WR_BURST_SIZE => 8,
C_BASEADDR => X"80200000",
C_HIGHADDR => X"8020ffff",
C_SPLB_DWIDTH => 64,
C_SPLB_AWIDTH => 32,
C_SPLB_NUM_MASTERS => 6,
C_SPLB_MID_WIDTH => 3,
C_SPLB_P2P => 0,
C_SPLB_NATIVE_DWIDTH => 32,
C_MPLB_NATIVE_DWIDTH => 32,
C_SPLB_SUPPORT_BURSTS => 0,
C_MPLB_AWIDTH => 32,
C_MPLB_DWIDTH => 64,
C_FAMILY => "virtex5"
)
port map (
SPLB_Clk => SPLB_Clk,
SPLB_Rst => SPLB_Rst,
MPLB_Clk => MPLB_Clk,
MPLB_Rst => MPLB_Rst,
SPLB_ABus => SPLB_ABus,
SPLB_BE => SPLB_BE,
SPLB_UABus => SPLB_UABus,
SPLB_PAValid => SPLB_PAValid,
SPLB_SAValid => SPLB_SAValid,
SPLB_rdPrim => SPLB_rdPrim,
SPLB_wrPrim => SPLB_wrPrim,
SPLB_masterID => SPLB_masterID,
SPLB_abort => SPLB_abort,
SPLB_busLock => SPLB_busLock,
SPLB_RNW => SPLB_RNW,
SPLB_MSize => SPLB_MSize,
SPLB_size => SPLB_size,
SPLB_type => SPLB_type,
SPLB_lockErr => SPLB_lockErr,
SPLB_wrDBus => SPLB_wrDBus,
SPLB_wrBurst => SPLB_wrBurst,
SPLB_rdBurst => SPLB_rdBurst,
SPLB_wrPendReq => SPLB_wrPendReq,
SPLB_rdPendReq => SPLB_rdPendReq,
SPLB_wrPendPri => SPLB_wrPendPri,
SPLB_rdPendPri => SPLB_rdPendPri,
SPLB_reqPri => SPLB_reqPri,
SPLB_TAttribute => SPLB_TAttribute,
Sl_addrAck => Sl_addrAck,
Sl_SSize => Sl_SSize,
Sl_wait => Sl_wait,
Sl_rearbitrate => Sl_rearbitrate,
Sl_wrDAck => Sl_wrDAck,
Sl_wrComp => Sl_wrComp,
Sl_wrBTerm => Sl_wrBTerm,
Sl_rdDBus => Sl_rdDBus,
Sl_rdWdAddr => Sl_rdWdAddr,
Sl_rdDAck => Sl_rdDAck,
Sl_rdComp => Sl_rdComp,
Sl_rdBTerm => Sl_rdBTerm,
Sl_MBusy => Sl_MBusy,
Sl_MWrErr => Sl_MWrErr,
Sl_MRdErr => Sl_MRdErr,
Sl_MIRQ => Sl_MIRQ,
IP2INTC_Irpt => IP2INTC_Irpt,
MPLB_MAddrAck => MPLB_MAddrAck,
MPLB_MSSize => MPLB_MSSize,
MPLB_MRearbitrate => MPLB_MRearbitrate,
MPLB_MTimeout => MPLB_MTimeout,
MPLB_MBusy => MPLB_MBusy,
MPLB_MRdErr => MPLB_MRdErr,
MPLB_MWrErr => MPLB_MWrErr,
MPLB_MIRQ => MPLB_MIRQ,
MPLB_MRdDBus => MPLB_MRdDBus,
MPLB_MRdWdAddr => MPLB_MRdWdAddr,
MPLB_MRdDAck => MPLB_MRdDAck,
MPLB_MRdBTerm => MPLB_MRdBTerm,
MPLB_MWrDAck => MPLB_MWrDAck,
MPLB_MWrBTerm => MPLB_MWrBTerm,
M_request => M_request,
M_priority => M_priority,
M_busLock => M_busLock,
M_RNW => M_RNW,
M_BE => M_BE,
M_MSize => M_MSize,
M_size => M_size,
M_type => M_type,
M_TAttribute => M_TAttribute,
M_lockErr => M_lockErr,
M_abort => M_abort,
M_UABus => M_UABus,
M_ABus => M_ABus,
M_wrDBus => M_wrDBus,
M_wrBurst => M_wrBurst,
M_rdBurst => M_rdBurst
);
end architecture STRUCTURE;
| lgpl-3.0 | 47c5f57ed56930059e511c8336ca75a0 | 0.591609 | 3.218997 | false | false | false | false |
grwlf/vsim | vhdl_ct/ct00024.vhd | 1 | 7,758 | -- NEED RESULT: ENT00024: Associated scalar ports with static subtypes passed
-------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
-------------------------------------------------------------------------------
--
-- TEST NAME:
--
-- CT00024
--
-- AUTHOR:
--
-- A. Wilmot
--
-- TEST OBJECTIVES:
--
-- 1.1.1.2 (4)
-- 1.1.1.2 (5)
--
-- DESIGN UNIT ORDERING:
--
-- ENT00024(ARCH00024)
-- ENT00024_Test_Bench(ARCH00024_Test_Bench)
--
-- REVISION HISTORY:
--
-- 25-JUN-1987 - initial revision
--
-- NOTES:
--
-- self-checking
-- automatically generated
--
use WORK.STANDARD_TYPES.all ;
entity ENT00024 is
port (
i_boolean_1, i_boolean_2 : in boolean
:= c_boolean_1
;
i_bit_1, i_bit_2 : in bit
:= c_bit_1
;
i_severity_level_1, i_severity_level_2 : in severity_level
:= c_severity_level_1
;
i_character_1, i_character_2 : in character
:= c_character_1
;
i_t_enum1_1, i_t_enum1_2 : in t_enum1
:= c_t_enum1_1
;
i_st_enum1_1, i_st_enum1_2 : in st_enum1
:= c_st_enum1_1
;
i_integer_1, i_integer_2 : in integer
:= c_integer_1
;
i_t_int1_1, i_t_int1_2 : in t_int1
:= c_t_int1_1
;
i_st_int1_1, i_st_int1_2 : in st_int1
:= c_st_int1_1
;
i_time_1, i_time_2 : in time
:= c_time_1
;
i_t_phys1_1, i_t_phys1_2 : in t_phys1
:= c_t_phys1_1
;
i_st_phys1_1, i_st_phys1_2 : in st_phys1
:= c_st_phys1_1
;
i_real_1, i_real_2 : in real
:= c_real_1
;
i_t_real1_1, i_t_real1_2 : in t_real1
:= c_t_real1_1
;
i_st_real1_1, i_st_real1_2 : in st_real1
:= c_st_real1_1
) ;
begin
end ENT00024 ;
--
architecture ARCH00024 of ENT00024 is
begin
process
variable correct : boolean := true ;
begin
correct := correct and i_boolean_1 = c_boolean_1
and i_boolean_2 = c_boolean_1 ;
correct := correct and i_bit_1 = c_bit_1
and i_bit_2 = c_bit_1 ;
correct := correct and i_severity_level_1 = c_severity_level_1
and i_severity_level_2 = c_severity_level_1 ;
correct := correct and i_character_1 = c_character_1
and i_character_2 = c_character_1 ;
correct := correct and i_t_enum1_1 = c_t_enum1_1
and i_t_enum1_2 = c_t_enum1_1 ;
correct := correct and i_st_enum1_1 = c_st_enum1_1
and i_st_enum1_2 = c_st_enum1_1 ;
correct := correct and i_integer_1 = c_integer_1
and i_integer_2 = c_integer_1 ;
correct := correct and i_t_int1_1 = c_t_int1_1
and i_t_int1_2 = c_t_int1_1 ;
correct := correct and i_st_int1_1 = c_st_int1_1
and i_st_int1_2 = c_st_int1_1 ;
correct := correct and i_time_1 = c_time_1
and i_time_2 = c_time_1 ;
correct := correct and i_t_phys1_1 = c_t_phys1_1
and i_t_phys1_2 = c_t_phys1_1 ;
correct := correct and i_st_phys1_1 = c_st_phys1_1
and i_st_phys1_2 = c_st_phys1_1 ;
correct := correct and i_real_1 = c_real_1
and i_real_2 = c_real_1 ;
correct := correct and i_t_real1_1 = c_t_real1_1
and i_t_real1_2 = c_t_real1_1 ;
correct := correct and i_st_real1_1 = c_st_real1_1
and i_st_real1_2 = c_st_real1_1 ;
test_report ( "ENT00024" ,
"Associated scalar ports with static subtypes" ,
correct) ;
wait ;
end process ;
end ARCH00024 ;
--
use WORK.STANDARD_TYPES.all ;
entity ENT00024_Test_Bench is
end ENT00024_Test_Bench ;
--
architecture ARCH00024_Test_Bench of ENT00024_Test_Bench is
begin
L1:
block
signal i_boolean_1, i_boolean_2 : boolean
:= c_boolean_1 ;
signal i_bit_1, i_bit_2 : bit
:= c_bit_1 ;
signal i_severity_level_1, i_severity_level_2 : severity_level
:= c_severity_level_1 ;
signal i_character_1, i_character_2 : character
:= c_character_1 ;
signal i_t_enum1_1, i_t_enum1_2 : t_enum1
:= c_t_enum1_1 ;
signal i_st_enum1_1, i_st_enum1_2 : st_enum1
:= c_st_enum1_1 ;
signal i_integer_1, i_integer_2 : integer
:= c_integer_1 ;
signal i_t_int1_1, i_t_int1_2 : t_int1
:= c_t_int1_1 ;
signal i_st_int1_1, i_st_int1_2 : st_int1
:= c_st_int1_1 ;
signal i_time_1, i_time_2 : time
:= c_time_1 ;
signal i_t_phys1_1, i_t_phys1_2 : t_phys1
:= c_t_phys1_1 ;
signal i_st_phys1_1, i_st_phys1_2 : st_phys1
:= c_st_phys1_1 ;
signal i_real_1, i_real_2 : real
:= c_real_1 ;
signal i_t_real1_1, i_t_real1_2 : t_real1
:= c_t_real1_1 ;
signal i_st_real1_1, i_st_real1_2 : st_real1
:= c_st_real1_1 ;
component UUT
port (
i_boolean_1, i_boolean_2 : in boolean
:= c_boolean_1
;
i_bit_1, i_bit_2 : in bit
:= c_bit_1
;
i_severity_level_1, i_severity_level_2 : in severity_level
:= c_severity_level_1
;
i_character_1, i_character_2 : in character
:= c_character_1
;
i_t_enum1_1, i_t_enum1_2 : in t_enum1
:= c_t_enum1_1
;
i_st_enum1_1, i_st_enum1_2 : in st_enum1
:= c_st_enum1_1
;
i_integer_1, i_integer_2 : in integer
:= c_integer_1
;
i_t_int1_1, i_t_int1_2 : in t_int1
:= c_t_int1_1
;
i_st_int1_1, i_st_int1_2 : in st_int1
:= c_st_int1_1
;
i_time_1, i_time_2 : in time
:= c_time_1
;
i_t_phys1_1, i_t_phys1_2 : in t_phys1
:= c_t_phys1_1
;
i_st_phys1_1, i_st_phys1_2 : in st_phys1
:= c_st_phys1_1
;
i_real_1, i_real_2 : in real
:= c_real_1
;
i_t_real1_1, i_t_real1_2 : in t_real1
:= c_t_real1_1
;
i_st_real1_1, i_st_real1_2 : in st_real1
:= c_st_real1_1
) ;
end component ;
for CIS1 : UUT use entity WORK.ENT00024 (ARCH00024) ;
begin
CIS1 : UUT
port map (
i_boolean_1, i_boolean_2,
i_bit_1, i_bit_2,
i_severity_level_1, i_severity_level_2,
i_character_1, i_character_2,
i_t_enum1_1, i_t_enum1_2,
i_st_enum1_1, i_st_enum1_2,
i_integer_1, i_integer_2,
i_t_int1_1, i_t_int1_2,
i_st_int1_1, i_st_int1_2,
i_time_1, i_time_2,
i_t_phys1_1, i_t_phys1_2,
i_st_phys1_1, i_st_phys1_2,
i_real_1, i_real_2,
i_t_real1_1, i_t_real1_2,
i_st_real1_1, i_st_real1_2
) ;
end block L1 ;
end ARCH00024_Test_Bench ;
| gpl-3.0 | 646e5a4088cc17475838689876ea6d3d | 0.442253 | 2.964463 | false | false | false | false |
grwlf/vsim | vhdl_ct/ct00652.vhd | 1 | 2,624 | -- NEED RESULT: ARCH00652: Subp variable parameters of mode 'out' may be updated passed
-- NEED RESULT: ARCH00652: Ports on blocks and entities along with signal parameters of mode 'out' may be updated passed
-------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
-------------------------------------------------------------------------------
--
-- TEST NAME:
--
-- CT00652
--
-- AUTHOR:
--
-- G. Tominovich
--
-- TEST OBJECTIVES:
--
-- 4.3.3 (14)
--
-- DESIGN UNIT ORDERING:
--
-- ENT00652(ARCH00652)
-- ENT00652_Test_Bench(ARCH00652_Test_Bench)
--
-- REVISION HISTORY:
--
-- 26-AUG-1987 - initial revision
--
-- NOTES:
--
-- self-checking
--
--
use WORK.STANDARD_TYPES.all ;
entity ENT00652 is
port ( Pt1 : out Integer ) ;
end ENT00652 ;
--
architecture ARCH00652 of ENT00652 is
function To_Integer ( P : Real ) return Integer is
begin
if P = -1.0 then
return -1 ;
else
return -2 ;
end if ;
end To_Integer ;
procedure Proc1 ( variable V : out Integer ) is
begin
V := -1 ;
end Proc1 ;
procedure Proc2 ( signal S : out Real ) is
begin
S <= transport -1.0 after 10 ns ;
end Proc2 ;
begin
L1 :
block
port ( Pt1 : out Real ) ;
port map ( To_Integer(Pt1) => Pt1 ) ; -- Check block 'out' port
begin
BP1 :
process
variable Var : Integer := -2 ;
begin
Proc1 (Var) ;
test_report ( "ARCH00652" ,
"Subp variable parameters of mode 'out' may be updated" ,
Var = -1 ) ;
Proc2 (Pt1) ; -- Check signal 'out' parameter
wait ;
end process BP1 ;
end block L1 ;
end ARCH00652 ;
--
use WORK.STANDARD_TYPES.all;
entity ENT00652_Test_Bench is
end ENT00652_Test_Bench ;
architecture ARCH00652_Test_Bench of ENT00652_Test_Bench is
begin
L1:
block
component UUT
end component ;
signal S1 : Integer := -2 ;
for CIS1 : UUT use entity WORK.ENT00652 ( ARCH00652 )
port map ( S1 ) ; -- Check entity 'out' port
begin
CIS1 : UUT ;
process
begin
wait for 11 ns ;
test_report ( "ARCH00652" ,
"Ports on blocks and entities along with signal "&
"parameters of mode 'out' may be updated" ,
S1 = -1 ) ;
wait ;
end process ;
end block L1 ;
end ARCH00652_Test_Bench ;
--
| gpl-3.0 | fc2257140c3d4cd199d88113ca502b4f | 0.512957 | 3.526882 | false | true | false | false |
grwlf/vsim | vhdl_ct/ct00131.vhd | 1 | 77,519 | -- NEED RESULT: ARCH00131.P1: Multi inertial transactions occurred on signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00131.P2: Multi inertial transactions occurred on signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00131.P3: Multi inertial transactions occurred on signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00131.P4: Multi inertial transactions occurred on signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00131.P5: Multi inertial transactions occurred on signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00131.P6: Multi inertial transactions occurred on signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00131.P7: Multi inertial transactions occurred on signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00131.P8: Multi inertial transactions occurred on signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00131.P9: Multi inertial transactions occurred on signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00131.P10: Multi inertial transactions occurred on signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00131.P11: Multi inertial transactions occurred on signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00131.P12: Multi inertial transactions occurred on signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00131.P13: Multi inertial transactions occurred on signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00131.P14: Multi inertial transactions occurred on signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00131.P15: Multi inertial transactions occurred on signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00131.P16: Multi inertial transactions occurred on signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00131.P17: Multi inertial transactions occurred on signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00131: One inertial transaction occurred on signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00131: One inertial transaction occurred on signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00131: One inertial transaction occurred on signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00131: One inertial transaction occurred on signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00131: One inertial transaction occurred on signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00131: One inertial transaction occurred on signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00131: One inertial transaction occurred on signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00131: One inertial transaction occurred on signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00131: One inertial transaction occurred on signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00131: One inertial transaction occurred on signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00131: One inertial transaction occurred on signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00131: One inertial transaction occurred on signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00131: One inertial transaction occurred on signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00131: One inertial transaction occurred on signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00131: One inertial transaction occurred on signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00131: One inertial transaction occurred on signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00131: One inertial transaction occurred on signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00131: Old transactions were removed on signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00131: Old transactions were removed on signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00131: Old transactions were removed on signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00131: Old transactions were removed on signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00131: Old transactions were removed on signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00131: Old transactions were removed on signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00131: Old transactions were removed on signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00131: Old transactions were removed on signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00131: Old transactions were removed on signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00131: Old transactions were removed on signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00131: Old transactions were removed on signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00131: Old transactions were removed on signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00131: Old transactions were removed on signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00131: Old transactions were removed on signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00131: Old transactions were removed on signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00131: Old transactions were removed on signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00131: Old transactions were removed on signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00131: One inertial transaction occurred on signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00131: One inertial transaction occurred on signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00131: One inertial transaction occurred on signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00131: One inertial transaction occurred on signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00131: One inertial transaction occurred on signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00131: One inertial transaction occurred on signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00131: One inertial transaction occurred on signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00131: One inertial transaction occurred on signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00131: One inertial transaction occurred on signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00131: One inertial transaction occurred on signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00131: One inertial transaction occurred on signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00131: One inertial transaction occurred on signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00131: One inertial transaction occurred on signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00131: One inertial transaction occurred on signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00131: One inertial transaction occurred on signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00131: One inertial transaction occurred on signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00131: One inertial transaction occurred on signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00131: Inertial semantics check on a signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00131: Inertial semantics check on a signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00131: Inertial semantics check on a signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00131: Inertial semantics check on a signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00131: Inertial semantics check on a signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00131: Inertial semantics check on a signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00131: Inertial semantics check on a signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00131: Inertial semantics check on a signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00131: Inertial semantics check on a signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00131: Inertial semantics check on a signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00131: Inertial semantics check on a signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00131: Inertial semantics check on a signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00131: Inertial semantics check on a signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00131: Inertial semantics check on a signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00131: Inertial semantics check on a signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00131: Inertial semantics check on a signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00131: Inertial semantics check on a signal asg with simple name on LHS passed
-- NEED RESULT: P17: Inertial transactions entirely completed passed
-- NEED RESULT: P16: Inertial transactions entirely completed passed
-- NEED RESULT: P15: Inertial transactions entirely completed passed
-- NEED RESULT: P14: Inertial transactions entirely completed passed
-- NEED RESULT: P13: Inertial transactions entirely completed passed
-- NEED RESULT: P12: Inertial transactions entirely completed passed
-- NEED RESULT: P11: Inertial transactions entirely completed passed
-- NEED RESULT: P10: Inertial transactions entirely completed passed
-- NEED RESULT: P9: Inertial transactions entirely completed passed
-- NEED RESULT: P8: Inertial transactions entirely completed passed
-- NEED RESULT: P7: Inertial transactions entirely completed passed
-- NEED RESULT: P6: Inertial transactions entirely completed passed
-- NEED RESULT: P5: Inertial transactions entirely completed passed
-- NEED RESULT: P4: Inertial transactions entirely completed passed
-- NEED RESULT: P3: Inertial transactions entirely completed passed
-- NEED RESULT: P2: Inertial transactions entirely completed passed
-- NEED RESULT: P1: Inertial transactions entirely completed passed
-------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
-------------------------------------------------------------------------------
--
-- TEST NAME:
--
-- CT00131
--
-- AUTHOR:
--
-- G. Tominovich
--
-- TEST OBJECTIVES:
--
-- 8.3 (1)
-- 8.3 (2)
-- 8.3 (4)
-- 8.3 (5)
-- 8.3.1 (4)
--
-- DESIGN UNIT ORDERING:
--
-- E00000(ARCH00131)
-- ENT00131_Test_Bench(ARCH00131_Test_Bench)
--
-- REVISION HISTORY:
--
-- 08-JUL-1987 - initial revision
--
-- NOTES:
--
-- self-checking
-- automatically generated
--
use WORK.STANDARD_TYPES.all ;
architecture ARCH00131 of E00000 is
subtype chk_sig_type is integer range -1 to 100 ;
signal chk_boolean : chk_sig_type := -1 ;
signal chk_bit : chk_sig_type := -1 ;
signal chk_severity_level : chk_sig_type := -1 ;
signal chk_character : chk_sig_type := -1 ;
signal chk_st_enum1 : chk_sig_type := -1 ;
signal chk_integer : chk_sig_type := -1 ;
signal chk_st_int1 : chk_sig_type := -1 ;
signal chk_time : chk_sig_type := -1 ;
signal chk_st_phys1 : chk_sig_type := -1 ;
signal chk_real : chk_sig_type := -1 ;
signal chk_st_real1 : chk_sig_type := -1 ;
signal chk_st_rec1 : chk_sig_type := -1 ;
signal chk_st_rec2 : chk_sig_type := -1 ;
signal chk_st_rec3 : chk_sig_type := -1 ;
signal chk_st_arr1 : chk_sig_type := -1 ;
signal chk_st_arr2 : chk_sig_type := -1 ;
signal chk_st_arr3 : chk_sig_type := -1 ;
--
signal s_boolean : boolean
:= c_boolean_1 ;
signal s_bit : bit
:= c_bit_1 ;
signal s_severity_level : severity_level
:= c_severity_level_1 ;
signal s_character : character
:= c_character_1 ;
signal s_st_enum1 : st_enum1
:= c_st_enum1_1 ;
signal s_integer : integer
:= c_integer_1 ;
signal s_st_int1 : st_int1
:= c_st_int1_1 ;
signal s_time : time
:= c_time_1 ;
signal s_st_phys1 : st_phys1
:= c_st_phys1_1 ;
signal s_real : real
:= c_real_1 ;
signal s_st_real1 : st_real1
:= c_st_real1_1 ;
signal s_st_rec1 : st_rec1
:= c_st_rec1_1 ;
signal s_st_rec2 : st_rec2
:= c_st_rec2_1 ;
signal s_st_rec3 : st_rec3
:= c_st_rec3_1 ;
signal s_st_arr1 : st_arr1
:= c_st_arr1_1 ;
signal s_st_arr2 : st_arr2
:= c_st_arr2_1 ;
signal s_st_arr3 : st_arr3
:= c_st_arr3_1 ;
--
begin
P1 :
process
variable correct : boolean ;
variable counter : integer := 0 ;
variable savtime : time ;
begin
case counter is
when 0
=> s_boolean <=
c_boolean_2 after 10 ns,
c_boolean_1 after 20 ns ;
--
when 1
=> correct :=
s_boolean = c_boolean_2 and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_boolean = c_boolean_1 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00131.P1" ,
"Multi inertial transactions occurred on signal " &
"asg with simple name on LHS",
correct ) ;
s_boolean <=
c_boolean_2 after 10 ns ,
c_boolean_1 after 20 ns ,
c_boolean_2 after 30 ns ,
c_boolean_1 after 40 ns ;
--
when 3
=> correct :=
s_boolean = c_boolean_2 and
(savtime + 10 ns) = Std.Standard.Now ;
s_boolean <= c_boolean_1 after 5 ns ;
--
when 4
=> correct :=
correct and
s_boolean = c_boolean_1 and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00131" ,
"One inertial transaction occurred on signal " &
"asg with simple name on LHS",
correct ) ;
s_boolean <= transport
c_boolean_1 after 100 ns ;
--
when 5
=> correct :=
s_boolean = c_boolean_1 and
(savtime + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00131" ,
"Old transactions were removed on signal " &
"asg with simple name on LHS",
correct ) ;
s_boolean <=
c_boolean_2 after 10 ns ,
c_boolean_1 after 20 ns ,
c_boolean_2 after 30 ns ,
c_boolean_1 after 40 ns ;
--
when 6
=> correct :=
s_boolean = c_boolean_2 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00131" ,
"One inertial transaction occurred on signal " &
"asg with simple name on LHS",
correct ) ;
s_boolean <= -- Last transaction above is marked
c_boolean_1 after 40 ns ;
--
when 7
=> correct :=
s_boolean = c_boolean_1 and
(savtime + 30 ns) = Std.Standard.Now ;
--
--
when 8
=> correct := correct and
s_boolean = c_boolean_1 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00131" ,
"Inertial semantics check on a signal " &
"asg with simple name on LHS",
correct ) ;
--
when others
=>
test_report ( "ARCH00131" ,
"Inertial semantics check on a signal " &
"asg with simple name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_boolean <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
wait until (not s_boolean'Quiet) and
(savtime /= Std.Standard.Now) ;
--
end process P1 ;
--
PGEN_CHKP_1 :
process ( chk_boolean )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P1" ,
"Inertial transactions entirely completed",
chk_boolean = 8 ) ;
end if ;
end process PGEN_CHKP_1 ;
--
P2 :
process
variable correct : boolean ;
variable counter : integer := 0 ;
variable savtime : time ;
begin
case counter is
when 0
=> s_bit <=
c_bit_2 after 10 ns,
c_bit_1 after 20 ns ;
--
when 1
=> correct :=
s_bit = c_bit_2 and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_bit = c_bit_1 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00131.P2" ,
"Multi inertial transactions occurred on signal " &
"asg with simple name on LHS",
correct ) ;
s_bit <=
c_bit_2 after 10 ns ,
c_bit_1 after 20 ns ,
c_bit_2 after 30 ns ,
c_bit_1 after 40 ns ;
--
when 3
=> correct :=
s_bit = c_bit_2 and
(savtime + 10 ns) = Std.Standard.Now ;
s_bit <= c_bit_1 after 5 ns ;
--
when 4
=> correct :=
correct and
s_bit = c_bit_1 and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00131" ,
"One inertial transaction occurred on signal " &
"asg with simple name on LHS",
correct ) ;
s_bit <= transport
c_bit_1 after 100 ns ;
--
when 5
=> correct :=
s_bit = c_bit_1 and
(savtime + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00131" ,
"Old transactions were removed on signal " &
"asg with simple name on LHS",
correct ) ;
s_bit <=
c_bit_2 after 10 ns ,
c_bit_1 after 20 ns ,
c_bit_2 after 30 ns ,
c_bit_1 after 40 ns ;
--
when 6
=> correct :=
s_bit = c_bit_2 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00131" ,
"One inertial transaction occurred on signal " &
"asg with simple name on LHS",
correct ) ;
s_bit <= -- Last transaction above is marked
c_bit_1 after 40 ns ;
--
when 7
=> correct :=
s_bit = c_bit_1 and
(savtime + 30 ns) = Std.Standard.Now ;
--
--
when 8
=> correct := correct and
s_bit = c_bit_1 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00131" ,
"Inertial semantics check on a signal " &
"asg with simple name on LHS",
correct ) ;
--
when others
=>
test_report ( "ARCH00131" ,
"Inertial semantics check on a signal " &
"asg with simple name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_bit <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
wait until (not s_bit'Quiet) and
(savtime /= Std.Standard.Now) ;
--
end process P2 ;
--
PGEN_CHKP_2 :
process ( chk_bit )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P2" ,
"Inertial transactions entirely completed",
chk_bit = 8 ) ;
end if ;
end process PGEN_CHKP_2 ;
--
P3 :
process
variable correct : boolean ;
variable counter : integer := 0 ;
variable savtime : time ;
begin
case counter is
when 0
=> s_severity_level <=
c_severity_level_2 after 10 ns,
c_severity_level_1 after 20 ns ;
--
when 1
=> correct :=
s_severity_level = c_severity_level_2 and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_severity_level = c_severity_level_1 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00131.P3" ,
"Multi inertial transactions occurred on signal " &
"asg with simple name on LHS",
correct ) ;
s_severity_level <=
c_severity_level_2 after 10 ns ,
c_severity_level_1 after 20 ns ,
c_severity_level_2 after 30 ns ,
c_severity_level_1 after 40 ns ;
--
when 3
=> correct :=
s_severity_level = c_severity_level_2 and
(savtime + 10 ns) = Std.Standard.Now ;
s_severity_level <= c_severity_level_1 after 5 ns ;
--
when 4
=> correct :=
correct and
s_severity_level = c_severity_level_1 and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00131" ,
"One inertial transaction occurred on signal " &
"asg with simple name on LHS",
correct ) ;
s_severity_level <= transport
c_severity_level_1 after 100 ns ;
--
when 5
=> correct :=
s_severity_level = c_severity_level_1 and
(savtime + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00131" ,
"Old transactions were removed on signal " &
"asg with simple name on LHS",
correct ) ;
s_severity_level <=
c_severity_level_2 after 10 ns ,
c_severity_level_1 after 20 ns ,
c_severity_level_2 after 30 ns ,
c_severity_level_1 after 40 ns ;
--
when 6
=> correct :=
s_severity_level = c_severity_level_2 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00131" ,
"One inertial transaction occurred on signal " &
"asg with simple name on LHS",
correct ) ;
s_severity_level <= -- Last transaction above is marked
c_severity_level_1 after 40 ns ;
--
when 7
=> correct :=
s_severity_level = c_severity_level_1 and
(savtime + 30 ns) = Std.Standard.Now ;
--
--
when 8
=> correct := correct and
s_severity_level = c_severity_level_1 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00131" ,
"Inertial semantics check on a signal " &
"asg with simple name on LHS",
correct ) ;
--
when others
=>
test_report ( "ARCH00131" ,
"Inertial semantics check on a signal " &
"asg with simple name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_severity_level <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
wait until (not s_severity_level'Quiet) and
(savtime /= Std.Standard.Now) ;
--
end process P3 ;
--
PGEN_CHKP_3 :
process ( chk_severity_level )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P3" ,
"Inertial transactions entirely completed",
chk_severity_level = 8 ) ;
end if ;
end process PGEN_CHKP_3 ;
--
P4 :
process
variable correct : boolean ;
variable counter : integer := 0 ;
variable savtime : time ;
begin
case counter is
when 0
=> s_character <=
c_character_2 after 10 ns,
c_character_1 after 20 ns ;
--
when 1
=> correct :=
s_character = c_character_2 and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_character = c_character_1 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00131.P4" ,
"Multi inertial transactions occurred on signal " &
"asg with simple name on LHS",
correct ) ;
s_character <=
c_character_2 after 10 ns ,
c_character_1 after 20 ns ,
c_character_2 after 30 ns ,
c_character_1 after 40 ns ;
--
when 3
=> correct :=
s_character = c_character_2 and
(savtime + 10 ns) = Std.Standard.Now ;
s_character <= c_character_1 after 5 ns ;
--
when 4
=> correct :=
correct and
s_character = c_character_1 and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00131" ,
"One inertial transaction occurred on signal " &
"asg with simple name on LHS",
correct ) ;
s_character <= transport
c_character_1 after 100 ns ;
--
when 5
=> correct :=
s_character = c_character_1 and
(savtime + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00131" ,
"Old transactions were removed on signal " &
"asg with simple name on LHS",
correct ) ;
s_character <=
c_character_2 after 10 ns ,
c_character_1 after 20 ns ,
c_character_2 after 30 ns ,
c_character_1 after 40 ns ;
--
when 6
=> correct :=
s_character = c_character_2 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00131" ,
"One inertial transaction occurred on signal " &
"asg with simple name on LHS",
correct ) ;
s_character <= -- Last transaction above is marked
c_character_1 after 40 ns ;
--
when 7
=> correct :=
s_character = c_character_1 and
(savtime + 30 ns) = Std.Standard.Now ;
--
--
when 8
=> correct := correct and
s_character = c_character_1 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00131" ,
"Inertial semantics check on a signal " &
"asg with simple name on LHS",
correct ) ;
--
when others
=>
test_report ( "ARCH00131" ,
"Inertial semantics check on a signal " &
"asg with simple name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_character <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
wait until (not s_character'Quiet) and
(savtime /= Std.Standard.Now) ;
--
end process P4 ;
--
PGEN_CHKP_4 :
process ( chk_character )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P4" ,
"Inertial transactions entirely completed",
chk_character = 8 ) ;
end if ;
end process PGEN_CHKP_4 ;
--
P5 :
process
variable correct : boolean ;
variable counter : integer := 0 ;
variable savtime : time ;
begin
case counter is
when 0
=> s_st_enum1 <=
c_st_enum1_2 after 10 ns,
c_st_enum1_1 after 20 ns ;
--
when 1
=> correct :=
s_st_enum1 = c_st_enum1_2 and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_enum1 = c_st_enum1_1 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00131.P5" ,
"Multi inertial transactions occurred on signal " &
"asg with simple name on LHS",
correct ) ;
s_st_enum1 <=
c_st_enum1_2 after 10 ns ,
c_st_enum1_1 after 20 ns ,
c_st_enum1_2 after 30 ns ,
c_st_enum1_1 after 40 ns ;
--
when 3
=> correct :=
s_st_enum1 = c_st_enum1_2 and
(savtime + 10 ns) = Std.Standard.Now ;
s_st_enum1 <= c_st_enum1_1 after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_enum1 = c_st_enum1_1 and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00131" ,
"One inertial transaction occurred on signal " &
"asg with simple name on LHS",
correct ) ;
s_st_enum1 <= transport
c_st_enum1_1 after 100 ns ;
--
when 5
=> correct :=
s_st_enum1 = c_st_enum1_1 and
(savtime + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00131" ,
"Old transactions were removed on signal " &
"asg with simple name on LHS",
correct ) ;
s_st_enum1 <=
c_st_enum1_2 after 10 ns ,
c_st_enum1_1 after 20 ns ,
c_st_enum1_2 after 30 ns ,
c_st_enum1_1 after 40 ns ;
--
when 6
=> correct :=
s_st_enum1 = c_st_enum1_2 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00131" ,
"One inertial transaction occurred on signal " &
"asg with simple name on LHS",
correct ) ;
s_st_enum1 <= -- Last transaction above is marked
c_st_enum1_1 after 40 ns ;
--
when 7
=> correct :=
s_st_enum1 = c_st_enum1_1 and
(savtime + 30 ns) = Std.Standard.Now ;
--
--
when 8
=> correct := correct and
s_st_enum1 = c_st_enum1_1 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00131" ,
"Inertial semantics check on a signal " &
"asg with simple name on LHS",
correct ) ;
--
when others
=>
test_report ( "ARCH00131" ,
"Inertial semantics check on a signal " &
"asg with simple name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_st_enum1 <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
wait until (not s_st_enum1'Quiet) and
(savtime /= Std.Standard.Now) ;
--
end process P5 ;
--
PGEN_CHKP_5 :
process ( chk_st_enum1 )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P5" ,
"Inertial transactions entirely completed",
chk_st_enum1 = 8 ) ;
end if ;
end process PGEN_CHKP_5 ;
--
P6 :
process
variable correct : boolean ;
variable counter : integer := 0 ;
variable savtime : time ;
begin
case counter is
when 0
=> s_integer <=
c_integer_2 after 10 ns,
c_integer_1 after 20 ns ;
--
when 1
=> correct :=
s_integer = c_integer_2 and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_integer = c_integer_1 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00131.P6" ,
"Multi inertial transactions occurred on signal " &
"asg with simple name on LHS",
correct ) ;
s_integer <=
c_integer_2 after 10 ns ,
c_integer_1 after 20 ns ,
c_integer_2 after 30 ns ,
c_integer_1 after 40 ns ;
--
when 3
=> correct :=
s_integer = c_integer_2 and
(savtime + 10 ns) = Std.Standard.Now ;
s_integer <= c_integer_1 after 5 ns ;
--
when 4
=> correct :=
correct and
s_integer = c_integer_1 and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00131" ,
"One inertial transaction occurred on signal " &
"asg with simple name on LHS",
correct ) ;
s_integer <= transport
c_integer_1 after 100 ns ;
--
when 5
=> correct :=
s_integer = c_integer_1 and
(savtime + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00131" ,
"Old transactions were removed on signal " &
"asg with simple name on LHS",
correct ) ;
s_integer <=
c_integer_2 after 10 ns ,
c_integer_1 after 20 ns ,
c_integer_2 after 30 ns ,
c_integer_1 after 40 ns ;
--
when 6
=> correct :=
s_integer = c_integer_2 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00131" ,
"One inertial transaction occurred on signal " &
"asg with simple name on LHS",
correct ) ;
s_integer <= -- Last transaction above is marked
c_integer_1 after 40 ns ;
--
when 7
=> correct :=
s_integer = c_integer_1 and
(savtime + 30 ns) = Std.Standard.Now ;
--
--
when 8
=> correct := correct and
s_integer = c_integer_1 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00131" ,
"Inertial semantics check on a signal " &
"asg with simple name on LHS",
correct ) ;
--
when others
=>
test_report ( "ARCH00131" ,
"Inertial semantics check on a signal " &
"asg with simple name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_integer <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
wait until (not s_integer'Quiet) and
(savtime /= Std.Standard.Now) ;
--
end process P6 ;
--
PGEN_CHKP_6 :
process ( chk_integer )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P6" ,
"Inertial transactions entirely completed",
chk_integer = 8 ) ;
end if ;
end process PGEN_CHKP_6 ;
--
P7 :
process
variable correct : boolean ;
variable counter : integer := 0 ;
variable savtime : time ;
begin
case counter is
when 0
=> s_st_int1 <=
c_st_int1_2 after 10 ns,
c_st_int1_1 after 20 ns ;
--
when 1
=> correct :=
s_st_int1 = c_st_int1_2 and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_int1 = c_st_int1_1 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00131.P7" ,
"Multi inertial transactions occurred on signal " &
"asg with simple name on LHS",
correct ) ;
s_st_int1 <=
c_st_int1_2 after 10 ns ,
c_st_int1_1 after 20 ns ,
c_st_int1_2 after 30 ns ,
c_st_int1_1 after 40 ns ;
--
when 3
=> correct :=
s_st_int1 = c_st_int1_2 and
(savtime + 10 ns) = Std.Standard.Now ;
s_st_int1 <= c_st_int1_1 after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_int1 = c_st_int1_1 and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00131" ,
"One inertial transaction occurred on signal " &
"asg with simple name on LHS",
correct ) ;
s_st_int1 <= transport
c_st_int1_1 after 100 ns ;
--
when 5
=> correct :=
s_st_int1 = c_st_int1_1 and
(savtime + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00131" ,
"Old transactions were removed on signal " &
"asg with simple name on LHS",
correct ) ;
s_st_int1 <=
c_st_int1_2 after 10 ns ,
c_st_int1_1 after 20 ns ,
c_st_int1_2 after 30 ns ,
c_st_int1_1 after 40 ns ;
--
when 6
=> correct :=
s_st_int1 = c_st_int1_2 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00131" ,
"One inertial transaction occurred on signal " &
"asg with simple name on LHS",
correct ) ;
s_st_int1 <= -- Last transaction above is marked
c_st_int1_1 after 40 ns ;
--
when 7
=> correct :=
s_st_int1 = c_st_int1_1 and
(savtime + 30 ns) = Std.Standard.Now ;
--
--
when 8
=> correct := correct and
s_st_int1 = c_st_int1_1 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00131" ,
"Inertial semantics check on a signal " &
"asg with simple name on LHS",
correct ) ;
--
when others
=>
test_report ( "ARCH00131" ,
"Inertial semantics check on a signal " &
"asg with simple name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_st_int1 <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
wait until (not s_st_int1'Quiet) and
(savtime /= Std.Standard.Now) ;
--
end process P7 ;
--
PGEN_CHKP_7 :
process ( chk_st_int1 )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P7" ,
"Inertial transactions entirely completed",
chk_st_int1 = 8 ) ;
end if ;
end process PGEN_CHKP_7 ;
--
P8 :
process
variable correct : boolean ;
variable counter : integer := 0 ;
variable savtime : time ;
begin
case counter is
when 0
=> s_time <=
c_time_2 after 10 ns,
c_time_1 after 20 ns ;
--
when 1
=> correct :=
s_time = c_time_2 and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_time = c_time_1 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00131.P8" ,
"Multi inertial transactions occurred on signal " &
"asg with simple name on LHS",
correct ) ;
s_time <=
c_time_2 after 10 ns ,
c_time_1 after 20 ns ,
c_time_2 after 30 ns ,
c_time_1 after 40 ns ;
--
when 3
=> correct :=
s_time = c_time_2 and
(savtime + 10 ns) = Std.Standard.Now ;
s_time <= c_time_1 after 5 ns ;
--
when 4
=> correct :=
correct and
s_time = c_time_1 and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00131" ,
"One inertial transaction occurred on signal " &
"asg with simple name on LHS",
correct ) ;
s_time <= transport
c_time_1 after 100 ns ;
--
when 5
=> correct :=
s_time = c_time_1 and
(savtime + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00131" ,
"Old transactions were removed on signal " &
"asg with simple name on LHS",
correct ) ;
s_time <=
c_time_2 after 10 ns ,
c_time_1 after 20 ns ,
c_time_2 after 30 ns ,
c_time_1 after 40 ns ;
--
when 6
=> correct :=
s_time = c_time_2 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00131" ,
"One inertial transaction occurred on signal " &
"asg with simple name on LHS",
correct ) ;
s_time <= -- Last transaction above is marked
c_time_1 after 40 ns ;
--
when 7
=> correct :=
s_time = c_time_1 and
(savtime + 30 ns) = Std.Standard.Now ;
--
--
when 8
=> correct := correct and
s_time = c_time_1 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00131" ,
"Inertial semantics check on a signal " &
"asg with simple name on LHS",
correct ) ;
--
when others
=>
test_report ( "ARCH00131" ,
"Inertial semantics check on a signal " &
"asg with simple name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_time <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
wait until (not s_time'Quiet) and
(savtime /= Std.Standard.Now) ;
--
end process P8 ;
--
PGEN_CHKP_8 :
process ( chk_time )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P8" ,
"Inertial transactions entirely completed",
chk_time = 8 ) ;
end if ;
end process PGEN_CHKP_8 ;
--
P9 :
process
variable correct : boolean ;
variable counter : integer := 0 ;
variable savtime : time ;
begin
case counter is
when 0
=> s_st_phys1 <=
c_st_phys1_2 after 10 ns,
c_st_phys1_1 after 20 ns ;
--
when 1
=> correct :=
s_st_phys1 = c_st_phys1_2 and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_phys1 = c_st_phys1_1 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00131.P9" ,
"Multi inertial transactions occurred on signal " &
"asg with simple name on LHS",
correct ) ;
s_st_phys1 <=
c_st_phys1_2 after 10 ns ,
c_st_phys1_1 after 20 ns ,
c_st_phys1_2 after 30 ns ,
c_st_phys1_1 after 40 ns ;
--
when 3
=> correct :=
s_st_phys1 = c_st_phys1_2 and
(savtime + 10 ns) = Std.Standard.Now ;
s_st_phys1 <= c_st_phys1_1 after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_phys1 = c_st_phys1_1 and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00131" ,
"One inertial transaction occurred on signal " &
"asg with simple name on LHS",
correct ) ;
s_st_phys1 <= transport
c_st_phys1_1 after 100 ns ;
--
when 5
=> correct :=
s_st_phys1 = c_st_phys1_1 and
(savtime + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00131" ,
"Old transactions were removed on signal " &
"asg with simple name on LHS",
correct ) ;
s_st_phys1 <=
c_st_phys1_2 after 10 ns ,
c_st_phys1_1 after 20 ns ,
c_st_phys1_2 after 30 ns ,
c_st_phys1_1 after 40 ns ;
--
when 6
=> correct :=
s_st_phys1 = c_st_phys1_2 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00131" ,
"One inertial transaction occurred on signal " &
"asg with simple name on LHS",
correct ) ;
s_st_phys1 <= -- Last transaction above is marked
c_st_phys1_1 after 40 ns ;
--
when 7
=> correct :=
s_st_phys1 = c_st_phys1_1 and
(savtime + 30 ns) = Std.Standard.Now ;
--
--
when 8
=> correct := correct and
s_st_phys1 = c_st_phys1_1 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00131" ,
"Inertial semantics check on a signal " &
"asg with simple name on LHS",
correct ) ;
--
when others
=>
test_report ( "ARCH00131" ,
"Inertial semantics check on a signal " &
"asg with simple name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_st_phys1 <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
wait until (not s_st_phys1'Quiet) and
(savtime /= Std.Standard.Now) ;
--
end process P9 ;
--
PGEN_CHKP_9 :
process ( chk_st_phys1 )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P9" ,
"Inertial transactions entirely completed",
chk_st_phys1 = 8 ) ;
end if ;
end process PGEN_CHKP_9 ;
--
P10 :
process
variable correct : boolean ;
variable counter : integer := 0 ;
variable savtime : time ;
begin
case counter is
when 0
=> s_real <=
c_real_2 after 10 ns,
c_real_1 after 20 ns ;
--
when 1
=> correct :=
s_real = c_real_2 and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_real = c_real_1 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00131.P10" ,
"Multi inertial transactions occurred on signal " &
"asg with simple name on LHS",
correct ) ;
s_real <=
c_real_2 after 10 ns ,
c_real_1 after 20 ns ,
c_real_2 after 30 ns ,
c_real_1 after 40 ns ;
--
when 3
=> correct :=
s_real = c_real_2 and
(savtime + 10 ns) = Std.Standard.Now ;
s_real <= c_real_1 after 5 ns ;
--
when 4
=> correct :=
correct and
s_real = c_real_1 and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00131" ,
"One inertial transaction occurred on signal " &
"asg with simple name on LHS",
correct ) ;
s_real <= transport
c_real_1 after 100 ns ;
--
when 5
=> correct :=
s_real = c_real_1 and
(savtime + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00131" ,
"Old transactions were removed on signal " &
"asg with simple name on LHS",
correct ) ;
s_real <=
c_real_2 after 10 ns ,
c_real_1 after 20 ns ,
c_real_2 after 30 ns ,
c_real_1 after 40 ns ;
--
when 6
=> correct :=
s_real = c_real_2 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00131" ,
"One inertial transaction occurred on signal " &
"asg with simple name on LHS",
correct ) ;
s_real <= -- Last transaction above is marked
c_real_1 after 40 ns ;
--
when 7
=> correct :=
s_real = c_real_1 and
(savtime + 30 ns) = Std.Standard.Now ;
--
--
when 8
=> correct := correct and
s_real = c_real_1 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00131" ,
"Inertial semantics check on a signal " &
"asg with simple name on LHS",
correct ) ;
--
when others
=>
test_report ( "ARCH00131" ,
"Inertial semantics check on a signal " &
"asg with simple name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_real <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
wait until (not s_real'Quiet) and
(savtime /= Std.Standard.Now) ;
--
end process P10 ;
--
PGEN_CHKP_10 :
process ( chk_real )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P10" ,
"Inertial transactions entirely completed",
chk_real = 8 ) ;
end if ;
end process PGEN_CHKP_10 ;
--
P11 :
process
variable correct : boolean ;
variable counter : integer := 0 ;
variable savtime : time ;
begin
case counter is
when 0
=> s_st_real1 <=
c_st_real1_2 after 10 ns,
c_st_real1_1 after 20 ns ;
--
when 1
=> correct :=
s_st_real1 = c_st_real1_2 and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_real1 = c_st_real1_1 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00131.P11" ,
"Multi inertial transactions occurred on signal " &
"asg with simple name on LHS",
correct ) ;
s_st_real1 <=
c_st_real1_2 after 10 ns ,
c_st_real1_1 after 20 ns ,
c_st_real1_2 after 30 ns ,
c_st_real1_1 after 40 ns ;
--
when 3
=> correct :=
s_st_real1 = c_st_real1_2 and
(savtime + 10 ns) = Std.Standard.Now ;
s_st_real1 <= c_st_real1_1 after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_real1 = c_st_real1_1 and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00131" ,
"One inertial transaction occurred on signal " &
"asg with simple name on LHS",
correct ) ;
s_st_real1 <= transport
c_st_real1_1 after 100 ns ;
--
when 5
=> correct :=
s_st_real1 = c_st_real1_1 and
(savtime + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00131" ,
"Old transactions were removed on signal " &
"asg with simple name on LHS",
correct ) ;
s_st_real1 <=
c_st_real1_2 after 10 ns ,
c_st_real1_1 after 20 ns ,
c_st_real1_2 after 30 ns ,
c_st_real1_1 after 40 ns ;
--
when 6
=> correct :=
s_st_real1 = c_st_real1_2 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00131" ,
"One inertial transaction occurred on signal " &
"asg with simple name on LHS",
correct ) ;
s_st_real1 <= -- Last transaction above is marked
c_st_real1_1 after 40 ns ;
--
when 7
=> correct :=
s_st_real1 = c_st_real1_1 and
(savtime + 30 ns) = Std.Standard.Now ;
--
--
when 8
=> correct := correct and
s_st_real1 = c_st_real1_1 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00131" ,
"Inertial semantics check on a signal " &
"asg with simple name on LHS",
correct ) ;
--
when others
=>
test_report ( "ARCH00131" ,
"Inertial semantics check on a signal " &
"asg with simple name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_st_real1 <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
wait until (not s_st_real1'Quiet) and
(savtime /= Std.Standard.Now) ;
--
end process P11 ;
--
PGEN_CHKP_11 :
process ( chk_st_real1 )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P11" ,
"Inertial transactions entirely completed",
chk_st_real1 = 8 ) ;
end if ;
end process PGEN_CHKP_11 ;
--
P12 :
process
variable correct : boolean ;
variable counter : integer := 0 ;
variable savtime : time ;
begin
case counter is
when 0
=> s_st_rec1 <=
c_st_rec1_2 after 10 ns,
c_st_rec1_1 after 20 ns ;
--
when 1
=> correct :=
s_st_rec1 = c_st_rec1_2 and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_rec1 = c_st_rec1_1 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00131.P12" ,
"Multi inertial transactions occurred on signal " &
"asg with simple name on LHS",
correct ) ;
s_st_rec1 <=
c_st_rec1_2 after 10 ns ,
c_st_rec1_1 after 20 ns ,
c_st_rec1_2 after 30 ns ,
c_st_rec1_1 after 40 ns ;
--
when 3
=> correct :=
s_st_rec1 = c_st_rec1_2 and
(savtime + 10 ns) = Std.Standard.Now ;
s_st_rec1 <= c_st_rec1_1 after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_rec1 = c_st_rec1_1 and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00131" ,
"One inertial transaction occurred on signal " &
"asg with simple name on LHS",
correct ) ;
s_st_rec1 <= transport
c_st_rec1_1 after 100 ns ;
--
when 5
=> correct :=
s_st_rec1 = c_st_rec1_1 and
(savtime + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00131" ,
"Old transactions were removed on signal " &
"asg with simple name on LHS",
correct ) ;
s_st_rec1 <=
c_st_rec1_2 after 10 ns ,
c_st_rec1_1 after 20 ns ,
c_st_rec1_2 after 30 ns ,
c_st_rec1_1 after 40 ns ;
--
when 6
=> correct :=
s_st_rec1 = c_st_rec1_2 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00131" ,
"One inertial transaction occurred on signal " &
"asg with simple name on LHS",
correct ) ;
s_st_rec1 <= -- Last transaction above is marked
c_st_rec1_1 after 40 ns ;
--
when 7
=> correct :=
s_st_rec1 = c_st_rec1_1 and
(savtime + 30 ns) = Std.Standard.Now ;
--
--
when 8
=> correct := correct and
s_st_rec1 = c_st_rec1_1 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00131" ,
"Inertial semantics check on a signal " &
"asg with simple name on LHS",
correct ) ;
--
when others
=>
test_report ( "ARCH00131" ,
"Inertial semantics check on a signal " &
"asg with simple name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_st_rec1 <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
wait until (not s_st_rec1'Quiet) and
(savtime /= Std.Standard.Now) ;
--
end process P12 ;
--
PGEN_CHKP_12 :
process ( chk_st_rec1 )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P12" ,
"Inertial transactions entirely completed",
chk_st_rec1 = 8 ) ;
end if ;
end process PGEN_CHKP_12 ;
--
P13 :
process
variable correct : boolean ;
variable counter : integer := 0 ;
variable savtime : time ;
begin
case counter is
when 0
=> s_st_rec2 <=
c_st_rec2_2 after 10 ns,
c_st_rec2_1 after 20 ns ;
--
when 1
=> correct :=
s_st_rec2 = c_st_rec2_2 and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_rec2 = c_st_rec2_1 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00131.P13" ,
"Multi inertial transactions occurred on signal " &
"asg with simple name on LHS",
correct ) ;
s_st_rec2 <=
c_st_rec2_2 after 10 ns ,
c_st_rec2_1 after 20 ns ,
c_st_rec2_2 after 30 ns ,
c_st_rec2_1 after 40 ns ;
--
when 3
=> correct :=
s_st_rec2 = c_st_rec2_2 and
(savtime + 10 ns) = Std.Standard.Now ;
s_st_rec2 <= c_st_rec2_1 after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_rec2 = c_st_rec2_1 and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00131" ,
"One inertial transaction occurred on signal " &
"asg with simple name on LHS",
correct ) ;
s_st_rec2 <= transport
c_st_rec2_1 after 100 ns ;
--
when 5
=> correct :=
s_st_rec2 = c_st_rec2_1 and
(savtime + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00131" ,
"Old transactions were removed on signal " &
"asg with simple name on LHS",
correct ) ;
s_st_rec2 <=
c_st_rec2_2 after 10 ns ,
c_st_rec2_1 after 20 ns ,
c_st_rec2_2 after 30 ns ,
c_st_rec2_1 after 40 ns ;
--
when 6
=> correct :=
s_st_rec2 = c_st_rec2_2 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00131" ,
"One inertial transaction occurred on signal " &
"asg with simple name on LHS",
correct ) ;
s_st_rec2 <= -- Last transaction above is marked
c_st_rec2_1 after 40 ns ;
--
when 7
=> correct :=
s_st_rec2 = c_st_rec2_1 and
(savtime + 30 ns) = Std.Standard.Now ;
--
--
when 8
=> correct := correct and
s_st_rec2 = c_st_rec2_1 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00131" ,
"Inertial semantics check on a signal " &
"asg with simple name on LHS",
correct ) ;
--
when others
=>
test_report ( "ARCH00131" ,
"Inertial semantics check on a signal " &
"asg with simple name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_st_rec2 <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
wait until (not s_st_rec2'Quiet) and
(savtime /= Std.Standard.Now) ;
--
end process P13 ;
--
PGEN_CHKP_13 :
process ( chk_st_rec2 )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P13" ,
"Inertial transactions entirely completed",
chk_st_rec2 = 8 ) ;
end if ;
end process PGEN_CHKP_13 ;
--
P14 :
process
variable correct : boolean ;
variable counter : integer := 0 ;
variable savtime : time ;
begin
case counter is
when 0
=> s_st_rec3 <=
c_st_rec3_2 after 10 ns,
c_st_rec3_1 after 20 ns ;
--
when 1
=> correct :=
s_st_rec3 = c_st_rec3_2 and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_rec3 = c_st_rec3_1 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00131.P14" ,
"Multi inertial transactions occurred on signal " &
"asg with simple name on LHS",
correct ) ;
s_st_rec3 <=
c_st_rec3_2 after 10 ns ,
c_st_rec3_1 after 20 ns ,
c_st_rec3_2 after 30 ns ,
c_st_rec3_1 after 40 ns ;
--
when 3
=> correct :=
s_st_rec3 = c_st_rec3_2 and
(savtime + 10 ns) = Std.Standard.Now ;
s_st_rec3 <= c_st_rec3_1 after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_rec3 = c_st_rec3_1 and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00131" ,
"One inertial transaction occurred on signal " &
"asg with simple name on LHS",
correct ) ;
s_st_rec3 <= transport
c_st_rec3_1 after 100 ns ;
--
when 5
=> correct :=
s_st_rec3 = c_st_rec3_1 and
(savtime + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00131" ,
"Old transactions were removed on signal " &
"asg with simple name on LHS",
correct ) ;
s_st_rec3 <=
c_st_rec3_2 after 10 ns ,
c_st_rec3_1 after 20 ns ,
c_st_rec3_2 after 30 ns ,
c_st_rec3_1 after 40 ns ;
--
when 6
=> correct :=
s_st_rec3 = c_st_rec3_2 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00131" ,
"One inertial transaction occurred on signal " &
"asg with simple name on LHS",
correct ) ;
s_st_rec3 <= -- Last transaction above is marked
c_st_rec3_1 after 40 ns ;
--
when 7
=> correct :=
s_st_rec3 = c_st_rec3_1 and
(savtime + 30 ns) = Std.Standard.Now ;
--
--
when 8
=> correct := correct and
s_st_rec3 = c_st_rec3_1 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00131" ,
"Inertial semantics check on a signal " &
"asg with simple name on LHS",
correct ) ;
--
when others
=>
test_report ( "ARCH00131" ,
"Inertial semantics check on a signal " &
"asg with simple name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_st_rec3 <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
wait until (not s_st_rec3'Quiet) and
(savtime /= Std.Standard.Now) ;
--
end process P14 ;
--
PGEN_CHKP_14 :
process ( chk_st_rec3 )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P14" ,
"Inertial transactions entirely completed",
chk_st_rec3 = 8 ) ;
end if ;
end process PGEN_CHKP_14 ;
--
P15 :
process
variable correct : boolean ;
variable counter : integer := 0 ;
variable savtime : time ;
begin
case counter is
when 0
=> s_st_arr1 <=
c_st_arr1_2 after 10 ns,
c_st_arr1_1 after 20 ns ;
--
when 1
=> correct :=
s_st_arr1 = c_st_arr1_2 and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_arr1 = c_st_arr1_1 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00131.P15" ,
"Multi inertial transactions occurred on signal " &
"asg with simple name on LHS",
correct ) ;
s_st_arr1 <=
c_st_arr1_2 after 10 ns ,
c_st_arr1_1 after 20 ns ,
c_st_arr1_2 after 30 ns ,
c_st_arr1_1 after 40 ns ;
--
when 3
=> correct :=
s_st_arr1 = c_st_arr1_2 and
(savtime + 10 ns) = Std.Standard.Now ;
s_st_arr1 <= c_st_arr1_1 after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_arr1 = c_st_arr1_1 and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00131" ,
"One inertial transaction occurred on signal " &
"asg with simple name on LHS",
correct ) ;
s_st_arr1 <= transport
c_st_arr1_1 after 100 ns ;
--
when 5
=> correct :=
s_st_arr1 = c_st_arr1_1 and
(savtime + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00131" ,
"Old transactions were removed on signal " &
"asg with simple name on LHS",
correct ) ;
s_st_arr1 <=
c_st_arr1_2 after 10 ns ,
c_st_arr1_1 after 20 ns ,
c_st_arr1_2 after 30 ns ,
c_st_arr1_1 after 40 ns ;
--
when 6
=> correct :=
s_st_arr1 = c_st_arr1_2 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00131" ,
"One inertial transaction occurred on signal " &
"asg with simple name on LHS",
correct ) ;
s_st_arr1 <= -- Last transaction above is marked
c_st_arr1_1 after 40 ns ;
--
when 7
=> correct :=
s_st_arr1 = c_st_arr1_1 and
(savtime + 30 ns) = Std.Standard.Now ;
--
--
when 8
=> correct := correct and
s_st_arr1 = c_st_arr1_1 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00131" ,
"Inertial semantics check on a signal " &
"asg with simple name on LHS",
correct ) ;
--
when others
=>
test_report ( "ARCH00131" ,
"Inertial semantics check on a signal " &
"asg with simple name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_st_arr1 <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
wait until (not s_st_arr1'Quiet) and
(savtime /= Std.Standard.Now) ;
--
end process P15 ;
--
PGEN_CHKP_15 :
process ( chk_st_arr1 )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P15" ,
"Inertial transactions entirely completed",
chk_st_arr1 = 8 ) ;
end if ;
end process PGEN_CHKP_15 ;
--
P16 :
process
variable correct : boolean ;
variable counter : integer := 0 ;
variable savtime : time ;
begin
case counter is
when 0
=> s_st_arr2 <=
c_st_arr2_2 after 10 ns,
c_st_arr2_1 after 20 ns ;
--
when 1
=> correct :=
s_st_arr2 = c_st_arr2_2 and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_arr2 = c_st_arr2_1 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00131.P16" ,
"Multi inertial transactions occurred on signal " &
"asg with simple name on LHS",
correct ) ;
s_st_arr2 <=
c_st_arr2_2 after 10 ns ,
c_st_arr2_1 after 20 ns ,
c_st_arr2_2 after 30 ns ,
c_st_arr2_1 after 40 ns ;
--
when 3
=> correct :=
s_st_arr2 = c_st_arr2_2 and
(savtime + 10 ns) = Std.Standard.Now ;
s_st_arr2 <= c_st_arr2_1 after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_arr2 = c_st_arr2_1 and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00131" ,
"One inertial transaction occurred on signal " &
"asg with simple name on LHS",
correct ) ;
s_st_arr2 <= transport
c_st_arr2_1 after 100 ns ;
--
when 5
=> correct :=
s_st_arr2 = c_st_arr2_1 and
(savtime + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00131" ,
"Old transactions were removed on signal " &
"asg with simple name on LHS",
correct ) ;
s_st_arr2 <=
c_st_arr2_2 after 10 ns ,
c_st_arr2_1 after 20 ns ,
c_st_arr2_2 after 30 ns ,
c_st_arr2_1 after 40 ns ;
--
when 6
=> correct :=
s_st_arr2 = c_st_arr2_2 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00131" ,
"One inertial transaction occurred on signal " &
"asg with simple name on LHS",
correct ) ;
s_st_arr2 <= -- Last transaction above is marked
c_st_arr2_1 after 40 ns ;
--
when 7
=> correct :=
s_st_arr2 = c_st_arr2_1 and
(savtime + 30 ns) = Std.Standard.Now ;
--
--
when 8
=> correct := correct and
s_st_arr2 = c_st_arr2_1 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00131" ,
"Inertial semantics check on a signal " &
"asg with simple name on LHS",
correct ) ;
--
when others
=>
test_report ( "ARCH00131" ,
"Inertial semantics check on a signal " &
"asg with simple name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_st_arr2 <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
wait until (not s_st_arr2'Quiet) and
(savtime /= Std.Standard.Now) ;
--
end process P16 ;
--
PGEN_CHKP_16 :
process ( chk_st_arr2 )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P16" ,
"Inertial transactions entirely completed",
chk_st_arr2 = 8 ) ;
end if ;
end process PGEN_CHKP_16 ;
--
P17 :
process
variable correct : boolean ;
variable counter : integer := 0 ;
variable savtime : time ;
begin
case counter is
when 0
=> s_st_arr3 <=
c_st_arr3_2 after 10 ns,
c_st_arr3_1 after 20 ns ;
--
when 1
=> correct :=
s_st_arr3 = c_st_arr3_2 and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_arr3 = c_st_arr3_1 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00131.P17" ,
"Multi inertial transactions occurred on signal " &
"asg with simple name on LHS",
correct ) ;
s_st_arr3 <=
c_st_arr3_2 after 10 ns ,
c_st_arr3_1 after 20 ns ,
c_st_arr3_2 after 30 ns ,
c_st_arr3_1 after 40 ns ;
--
when 3
=> correct :=
s_st_arr3 = c_st_arr3_2 and
(savtime + 10 ns) = Std.Standard.Now ;
s_st_arr3 <= c_st_arr3_1 after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_arr3 = c_st_arr3_1 and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00131" ,
"One inertial transaction occurred on signal " &
"asg with simple name on LHS",
correct ) ;
s_st_arr3 <= transport
c_st_arr3_1 after 100 ns ;
--
when 5
=> correct :=
s_st_arr3 = c_st_arr3_1 and
(savtime + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00131" ,
"Old transactions were removed on signal " &
"asg with simple name on LHS",
correct ) ;
s_st_arr3 <=
c_st_arr3_2 after 10 ns ,
c_st_arr3_1 after 20 ns ,
c_st_arr3_2 after 30 ns ,
c_st_arr3_1 after 40 ns ;
--
when 6
=> correct :=
s_st_arr3 = c_st_arr3_2 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00131" ,
"One inertial transaction occurred on signal " &
"asg with simple name on LHS",
correct ) ;
s_st_arr3 <= -- Last transaction above is marked
c_st_arr3_1 after 40 ns ;
--
when 7
=> correct :=
s_st_arr3 = c_st_arr3_1 and
(savtime + 30 ns) = Std.Standard.Now ;
--
--
when 8
=> correct := correct and
s_st_arr3 = c_st_arr3_1 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00131" ,
"Inertial semantics check on a signal " &
"asg with simple name on LHS",
correct ) ;
--
when others
=>
test_report ( "ARCH00131" ,
"Inertial semantics check on a signal " &
"asg with simple name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_st_arr3 <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
wait until (not s_st_arr3'Quiet) and
(savtime /= Std.Standard.Now) ;
--
end process P17 ;
--
PGEN_CHKP_17 :
process ( chk_st_arr3 )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P17" ,
"Inertial transactions entirely completed",
chk_st_arr3 = 8 ) ;
end if ;
end process PGEN_CHKP_17 ;
--
--
end ARCH00131 ;
--
entity ENT00131_Test_Bench is
end ENT00131_Test_Bench ;
--
architecture ARCH00131_Test_Bench of ENT00131_Test_Bench is
begin
L1:
block
component UUT
end component ;
for CIS1 : UUT use entity WORK.E00000 ( ARCH00131 ) ;
begin
CIS1 : UUT ;
end block L1 ;
end ARCH00131_Test_Bench ;
| gpl-3.0 | 87d69558f49c66166a682be91ed3929e | 0.491441 | 4.012578 | false | true | false | false |
jairov4/accel-oil | solution_spartan3/impl/vhdl/sample_iterator_next.vhd | 2 | 31,609 | -- ==============================================================
-- RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2013.4
-- Copyright (C) 2013 Xilinx Inc. All rights reserved.
--
-- ===========================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity sample_iterator_next is
port (
ap_clk : IN STD_LOGIC;
ap_rst : IN STD_LOGIC;
ap_start : IN STD_LOGIC;
ap_done : OUT STD_LOGIC;
ap_idle : OUT STD_LOGIC;
ap_ready : OUT STD_LOGIC;
indices_samples_req_din : OUT STD_LOGIC;
indices_samples_req_full_n : IN STD_LOGIC;
indices_samples_req_write : OUT STD_LOGIC;
indices_samples_rsp_empty_n : IN STD_LOGIC;
indices_samples_rsp_read : OUT STD_LOGIC;
indices_samples_address : OUT STD_LOGIC_VECTOR (31 downto 0);
indices_samples_datain : IN STD_LOGIC_VECTOR (15 downto 0);
indices_samples_dataout : OUT STD_LOGIC_VECTOR (15 downto 0);
indices_samples_size : OUT STD_LOGIC_VECTOR (31 downto 0);
ap_ce : IN STD_LOGIC;
indices_begin_req_din : OUT STD_LOGIC;
indices_begin_req_full_n : IN STD_LOGIC;
indices_begin_req_write : OUT STD_LOGIC;
indices_begin_rsp_empty_n : IN STD_LOGIC;
indices_begin_rsp_read : OUT STD_LOGIC;
indices_begin_address : OUT STD_LOGIC_VECTOR (31 downto 0);
indices_begin_datain : IN STD_LOGIC_VECTOR (31 downto 0);
indices_begin_dataout : OUT STD_LOGIC_VECTOR (31 downto 0);
indices_begin_size : OUT STD_LOGIC_VECTOR (31 downto 0);
indices_stride_req_din : OUT STD_LOGIC;
indices_stride_req_full_n : IN STD_LOGIC;
indices_stride_req_write : OUT STD_LOGIC;
indices_stride_rsp_empty_n : IN STD_LOGIC;
indices_stride_rsp_read : OUT STD_LOGIC;
indices_stride_address : OUT STD_LOGIC_VECTOR (31 downto 0);
indices_stride_datain : IN STD_LOGIC_VECTOR (7 downto 0);
indices_stride_dataout : OUT STD_LOGIC_VECTOR (7 downto 0);
indices_stride_size : OUT STD_LOGIC_VECTOR (31 downto 0);
i_index : IN STD_LOGIC_VECTOR (15 downto 0);
i_sample : IN STD_LOGIC_VECTOR (15 downto 0);
ap_return_0 : OUT STD_LOGIC_VECTOR (15 downto 0);
ap_return_1 : OUT STD_LOGIC_VECTOR (15 downto 0) );
end;
architecture behav of sample_iterator_next is
constant ap_const_logic_1 : STD_LOGIC := '1';
constant ap_const_logic_0 : STD_LOGIC := '0';
constant ap_ST_pp0_stg0_fsm_0 : STD_LOGIC_VECTOR (0 downto 0) := "0";
constant ap_const_lv32_0 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000000";
constant ap_const_lv32_1 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000001";
constant ap_const_lv17_1FFFF : STD_LOGIC_VECTOR (16 downto 0) := "11111111111111111";
constant ap_const_lv16_1 : STD_LOGIC_VECTOR (15 downto 0) := "0000000000000001";
constant ap_const_lv16_0 : STD_LOGIC_VECTOR (15 downto 0) := "0000000000000000";
constant ap_const_lv8_0 : STD_LOGIC_VECTOR (7 downto 0) := "00000000";
signal ap_CS_fsm : STD_LOGIC_VECTOR (0 downto 0) := "0";
signal ap_reg_ppiten_pp0_it0 : STD_LOGIC;
signal ap_reg_ppiten_pp0_it1 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it2 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it3 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it4 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it5 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it6 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it7 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it8 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it9 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it10 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it11 : STD_LOGIC := '0';
signal i_sample_read_reg_128 : STD_LOGIC_VECTOR (15 downto 0);
signal ap_reg_ppstg_i_sample_read_reg_128_pp0_it1 : STD_LOGIC_VECTOR (15 downto 0);
signal ap_reg_ppstg_i_sample_read_reg_128_pp0_it2 : STD_LOGIC_VECTOR (15 downto 0);
signal ap_reg_ppstg_i_sample_read_reg_128_pp0_it3 : STD_LOGIC_VECTOR (15 downto 0);
signal ap_reg_ppstg_i_sample_read_reg_128_pp0_it4 : STD_LOGIC_VECTOR (15 downto 0);
signal ap_reg_ppstg_i_sample_read_reg_128_pp0_it5 : STD_LOGIC_VECTOR (15 downto 0);
signal ap_reg_ppstg_i_sample_read_reg_128_pp0_it6 : STD_LOGIC_VECTOR (15 downto 0);
signal ap_reg_ppstg_i_sample_read_reg_128_pp0_it7 : STD_LOGIC_VECTOR (15 downto 0);
signal ap_reg_ppstg_i_sample_read_reg_128_pp0_it8 : STD_LOGIC_VECTOR (15 downto 0);
signal ap_reg_ppstg_i_sample_read_reg_128_pp0_it9 : STD_LOGIC_VECTOR (15 downto 0);
signal i_index_read_reg_134 : STD_LOGIC_VECTOR (15 downto 0);
signal ap_reg_ppstg_i_index_read_reg_134_pp0_it1 : STD_LOGIC_VECTOR (15 downto 0);
signal ap_reg_ppstg_i_index_read_reg_134_pp0_it2 : STD_LOGIC_VECTOR (15 downto 0);
signal ap_reg_ppstg_i_index_read_reg_134_pp0_it3 : STD_LOGIC_VECTOR (15 downto 0);
signal ap_reg_ppstg_i_index_read_reg_134_pp0_it4 : STD_LOGIC_VECTOR (15 downto 0);
signal ap_reg_ppstg_i_index_read_reg_134_pp0_it5 : STD_LOGIC_VECTOR (15 downto 0);
signal ap_reg_ppstg_i_index_read_reg_134_pp0_it6 : STD_LOGIC_VECTOR (15 downto 0);
signal ap_reg_ppstg_i_index_read_reg_134_pp0_it7 : STD_LOGIC_VECTOR (15 downto 0);
signal ap_reg_ppstg_i_index_read_reg_134_pp0_it8 : STD_LOGIC_VECTOR (15 downto 0);
signal ap_reg_ppstg_i_index_read_reg_134_pp0_it9 : STD_LOGIC_VECTOR (15 downto 0);
signal ap_reg_ppstg_i_index_read_reg_134_pp0_it10 : STD_LOGIC_VECTOR (15 downto 0);
signal indices_samples_addr_read_reg_146 : STD_LOGIC_VECTOR (15 downto 0);
signal grp_fu_77_p2 : STD_LOGIC_VECTOR (16 downto 0);
signal tmp_1_reg_156 : STD_LOGIC_VECTOR (16 downto 0);
signal tmp_2_fu_99_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_2_reg_161 : STD_LOGIC_VECTOR (0 downto 0);
signal grp_fu_83_p2 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_4_reg_167 : STD_LOGIC_VECTOR (15 downto 0);
signal grp_fu_88_p2 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_3_reg_172 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_9_fu_63_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal grp_fu_77_p0 : STD_LOGIC_VECTOR (16 downto 0);
signal grp_fu_77_p1 : STD_LOGIC_VECTOR (16 downto 0);
signal grp_fu_83_p0 : STD_LOGIC_VECTOR (15 downto 0);
signal grp_fu_83_p1 : STD_LOGIC_VECTOR (15 downto 0);
signal grp_fu_88_p0 : STD_LOGIC_VECTOR (15 downto 0);
signal grp_fu_88_p1 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_cast_fu_93_p1 : STD_LOGIC_VECTOR (17 downto 0);
signal tmp_2_fu_99_p1 : STD_LOGIC_VECTOR (17 downto 0);
signal tmp_1_reg_156_temp: signed (17-1 downto 0);
signal agg_result_index_write_assign_fu_111_p3 : STD_LOGIC_VECTOR (15 downto 0);
signal agg_result_sample_write_assign_fu_105_p3 : STD_LOGIC_VECTOR (15 downto 0);
signal grp_fu_77_ce : STD_LOGIC;
signal grp_fu_83_ce : STD_LOGIC;
signal grp_fu_88_ce : STD_LOGIC;
signal ap_NS_fsm : STD_LOGIC_VECTOR (0 downto 0);
signal ap_sig_pprstidle_pp0 : STD_LOGIC;
component nfa_accept_samples_generic_hw_add_17ns_17s_17_4 IS
generic (
ID : INTEGER;
NUM_STAGE : INTEGER;
din0_WIDTH : INTEGER;
din1_WIDTH : INTEGER;
dout_WIDTH : INTEGER );
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
din0 : IN STD_LOGIC_VECTOR (16 downto 0);
din1 : IN STD_LOGIC_VECTOR (16 downto 0);
ce : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR (16 downto 0) );
end component;
component nfa_accept_samples_generic_hw_add_16ns_16ns_16_4 IS
generic (
ID : INTEGER;
NUM_STAGE : INTEGER;
din0_WIDTH : INTEGER;
din1_WIDTH : INTEGER;
dout_WIDTH : INTEGER );
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
din0 : IN STD_LOGIC_VECTOR (15 downto 0);
din1 : IN STD_LOGIC_VECTOR (15 downto 0);
ce : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR (15 downto 0) );
end component;
begin
nfa_accept_samples_generic_hw_add_17ns_17s_17_4_U30 : component nfa_accept_samples_generic_hw_add_17ns_17s_17_4
generic map (
ID => 30,
NUM_STAGE => 4,
din0_WIDTH => 17,
din1_WIDTH => 17,
dout_WIDTH => 17)
port map (
clk => ap_clk,
reset => ap_rst,
din0 => grp_fu_77_p0,
din1 => grp_fu_77_p1,
ce => grp_fu_77_ce,
dout => grp_fu_77_p2);
nfa_accept_samples_generic_hw_add_16ns_16ns_16_4_U31 : component nfa_accept_samples_generic_hw_add_16ns_16ns_16_4
generic map (
ID => 31,
NUM_STAGE => 4,
din0_WIDTH => 16,
din1_WIDTH => 16,
dout_WIDTH => 16)
port map (
clk => ap_clk,
reset => ap_rst,
din0 => grp_fu_83_p0,
din1 => grp_fu_83_p1,
ce => grp_fu_83_ce,
dout => grp_fu_83_p2);
nfa_accept_samples_generic_hw_add_16ns_16ns_16_4_U32 : component nfa_accept_samples_generic_hw_add_16ns_16ns_16_4
generic map (
ID => 32,
NUM_STAGE => 4,
din0_WIDTH => 16,
din1_WIDTH => 16,
dout_WIDTH => 16)
port map (
clk => ap_clk,
reset => ap_rst,
din0 => grp_fu_88_p0,
din1 => grp_fu_88_p1,
ce => grp_fu_88_ce,
dout => grp_fu_88_p2);
-- the current state (ap_CS_fsm) of the state machine. --
ap_CS_fsm_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_CS_fsm <= ap_ST_pp0_stg0_fsm_0;
else
ap_CS_fsm <= ap_NS_fsm;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it1 assign process. --
ap_reg_ppiten_pp0_it1_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_reg_ppiten_pp0_it1 <= ap_const_logic_0;
else
if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it5) and (indices_samples_rsp_empty_n = ap_const_logic_0)) or not((ap_const_logic_1 = ap_ce)))))) then
ap_reg_ppiten_pp0_it1 <= ap_reg_ppiten_pp0_it0;
end if;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it10 assign process. --
ap_reg_ppiten_pp0_it10_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_reg_ppiten_pp0_it10 <= ap_const_logic_0;
else
if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it5) and (indices_samples_rsp_empty_n = ap_const_logic_0)) or not((ap_const_logic_1 = ap_ce)))))) then
ap_reg_ppiten_pp0_it10 <= ap_reg_ppiten_pp0_it9;
end if;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it11 assign process. --
ap_reg_ppiten_pp0_it11_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_reg_ppiten_pp0_it11 <= ap_const_logic_0;
else
if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it5) and (indices_samples_rsp_empty_n = ap_const_logic_0)) or not((ap_const_logic_1 = ap_ce)))))) then
ap_reg_ppiten_pp0_it11 <= ap_reg_ppiten_pp0_it10;
end if;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it2 assign process. --
ap_reg_ppiten_pp0_it2_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_reg_ppiten_pp0_it2 <= ap_const_logic_0;
else
if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it5) and (indices_samples_rsp_empty_n = ap_const_logic_0)) or not((ap_const_logic_1 = ap_ce)))))) then
ap_reg_ppiten_pp0_it2 <= ap_reg_ppiten_pp0_it1;
end if;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it3 assign process. --
ap_reg_ppiten_pp0_it3_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_reg_ppiten_pp0_it3 <= ap_const_logic_0;
else
if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it5) and (indices_samples_rsp_empty_n = ap_const_logic_0)) or not((ap_const_logic_1 = ap_ce)))))) then
ap_reg_ppiten_pp0_it3 <= ap_reg_ppiten_pp0_it2;
end if;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it4 assign process. --
ap_reg_ppiten_pp0_it4_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_reg_ppiten_pp0_it4 <= ap_const_logic_0;
else
if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it5) and (indices_samples_rsp_empty_n = ap_const_logic_0)) or not((ap_const_logic_1 = ap_ce)))))) then
ap_reg_ppiten_pp0_it4 <= ap_reg_ppiten_pp0_it3;
end if;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it5 assign process. --
ap_reg_ppiten_pp0_it5_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_reg_ppiten_pp0_it5 <= ap_const_logic_0;
else
if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it5) and (indices_samples_rsp_empty_n = ap_const_logic_0)) or not((ap_const_logic_1 = ap_ce)))))) then
ap_reg_ppiten_pp0_it5 <= ap_reg_ppiten_pp0_it4;
end if;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it6 assign process. --
ap_reg_ppiten_pp0_it6_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_reg_ppiten_pp0_it6 <= ap_const_logic_0;
else
if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it5) and (indices_samples_rsp_empty_n = ap_const_logic_0)) or not((ap_const_logic_1 = ap_ce)))))) then
ap_reg_ppiten_pp0_it6 <= ap_reg_ppiten_pp0_it5;
end if;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it7 assign process. --
ap_reg_ppiten_pp0_it7_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_reg_ppiten_pp0_it7 <= ap_const_logic_0;
else
if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it5) and (indices_samples_rsp_empty_n = ap_const_logic_0)) or not((ap_const_logic_1 = ap_ce)))))) then
ap_reg_ppiten_pp0_it7 <= ap_reg_ppiten_pp0_it6;
end if;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it8 assign process. --
ap_reg_ppiten_pp0_it8_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_reg_ppiten_pp0_it8 <= ap_const_logic_0;
else
if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it5) and (indices_samples_rsp_empty_n = ap_const_logic_0)) or not((ap_const_logic_1 = ap_ce)))))) then
ap_reg_ppiten_pp0_it8 <= ap_reg_ppiten_pp0_it7;
end if;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it9 assign process. --
ap_reg_ppiten_pp0_it9_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_reg_ppiten_pp0_it9 <= ap_const_logic_0;
else
if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it5) and (indices_samples_rsp_empty_n = ap_const_logic_0)) or not((ap_const_logic_1 = ap_ce)))))) then
ap_reg_ppiten_pp0_it9 <= ap_reg_ppiten_pp0_it8;
end if;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it5) and (indices_samples_rsp_empty_n = ap_const_logic_0)))) and (ap_const_logic_1 = ap_ce))) then
ap_reg_ppstg_i_index_read_reg_134_pp0_it1 <= i_index_read_reg_134;
ap_reg_ppstg_i_index_read_reg_134_pp0_it10 <= ap_reg_ppstg_i_index_read_reg_134_pp0_it9;
ap_reg_ppstg_i_index_read_reg_134_pp0_it2 <= ap_reg_ppstg_i_index_read_reg_134_pp0_it1;
ap_reg_ppstg_i_index_read_reg_134_pp0_it3 <= ap_reg_ppstg_i_index_read_reg_134_pp0_it2;
ap_reg_ppstg_i_index_read_reg_134_pp0_it4 <= ap_reg_ppstg_i_index_read_reg_134_pp0_it3;
ap_reg_ppstg_i_index_read_reg_134_pp0_it5 <= ap_reg_ppstg_i_index_read_reg_134_pp0_it4;
ap_reg_ppstg_i_index_read_reg_134_pp0_it6 <= ap_reg_ppstg_i_index_read_reg_134_pp0_it5;
ap_reg_ppstg_i_index_read_reg_134_pp0_it7 <= ap_reg_ppstg_i_index_read_reg_134_pp0_it6;
ap_reg_ppstg_i_index_read_reg_134_pp0_it8 <= ap_reg_ppstg_i_index_read_reg_134_pp0_it7;
ap_reg_ppstg_i_index_read_reg_134_pp0_it9 <= ap_reg_ppstg_i_index_read_reg_134_pp0_it8;
ap_reg_ppstg_i_sample_read_reg_128_pp0_it1 <= i_sample_read_reg_128;
ap_reg_ppstg_i_sample_read_reg_128_pp0_it2 <= ap_reg_ppstg_i_sample_read_reg_128_pp0_it1;
ap_reg_ppstg_i_sample_read_reg_128_pp0_it3 <= ap_reg_ppstg_i_sample_read_reg_128_pp0_it2;
ap_reg_ppstg_i_sample_read_reg_128_pp0_it4 <= ap_reg_ppstg_i_sample_read_reg_128_pp0_it3;
ap_reg_ppstg_i_sample_read_reg_128_pp0_it5 <= ap_reg_ppstg_i_sample_read_reg_128_pp0_it4;
ap_reg_ppstg_i_sample_read_reg_128_pp0_it6 <= ap_reg_ppstg_i_sample_read_reg_128_pp0_it5;
ap_reg_ppstg_i_sample_read_reg_128_pp0_it7 <= ap_reg_ppstg_i_sample_read_reg_128_pp0_it6;
ap_reg_ppstg_i_sample_read_reg_128_pp0_it8 <= ap_reg_ppstg_i_sample_read_reg_128_pp0_it7;
ap_reg_ppstg_i_sample_read_reg_128_pp0_it9 <= ap_reg_ppstg_i_sample_read_reg_128_pp0_it8;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it5) and (indices_samples_rsp_empty_n = ap_const_logic_0)))) and (ap_const_logic_1 = ap_ce))) then
i_index_read_reg_134 <= i_index;
i_sample_read_reg_128 <= i_sample;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it5) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it5) and (indices_samples_rsp_empty_n = ap_const_logic_0)))) and (ap_const_logic_1 = ap_ce))) then
indices_samples_addr_read_reg_146 <= indices_samples_datain;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it9) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it5) and (indices_samples_rsp_empty_n = ap_const_logic_0)))) and (ap_const_logic_1 = ap_ce))) then
tmp_1_reg_156 <= grp_fu_77_p2;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it10) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it5) and (indices_samples_rsp_empty_n = ap_const_logic_0)))) and (ap_const_logic_1 = ap_ce))) then
tmp_2_reg_161 <= tmp_2_fu_99_p2;
tmp_3_reg_172 <= grp_fu_88_p2;
tmp_4_reg_167 <= grp_fu_83_p2;
end if;
end if;
end process;
-- the next state (ap_NS_fsm) of the state machine. --
ap_NS_fsm_assign_proc : process (ap_start , ap_CS_fsm , ap_reg_ppiten_pp0_it0 , ap_reg_ppiten_pp0_it5 , indices_samples_rsp_empty_n , ap_ce , ap_sig_pprstidle_pp0)
begin
case ap_CS_fsm is
when ap_ST_pp0_stg0_fsm_0 =>
ap_NS_fsm <= ap_ST_pp0_stg0_fsm_0;
when others =>
ap_NS_fsm <= "X";
end case;
end process;
agg_result_index_write_assign_fu_111_p3 <=
ap_reg_ppstg_i_index_read_reg_134_pp0_it10 when (tmp_2_reg_161(0) = '1') else
tmp_4_reg_167;
agg_result_sample_write_assign_fu_105_p3 <=
tmp_3_reg_172 when (tmp_2_reg_161(0) = '1') else
ap_const_lv16_0;
-- ap_done assign process. --
ap_done_assign_proc : process(ap_start, ap_CS_fsm, ap_reg_ppiten_pp0_it0, ap_reg_ppiten_pp0_it5, ap_reg_ppiten_pp0_it11, indices_samples_rsp_empty_n, ap_ce)
begin
if (((not((ap_const_logic_1 = ap_start)) and (ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it0)) or ((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it11) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it5) and (indices_samples_rsp_empty_n = ap_const_logic_0)))) and (ap_const_logic_1 = ap_ce)))) then
ap_done <= ap_const_logic_1;
else
ap_done <= ap_const_logic_0;
end if;
end process;
-- ap_idle assign process. --
ap_idle_assign_proc : process(ap_start, ap_CS_fsm, ap_reg_ppiten_pp0_it0, ap_reg_ppiten_pp0_it1, ap_reg_ppiten_pp0_it2, ap_reg_ppiten_pp0_it3, ap_reg_ppiten_pp0_it4, ap_reg_ppiten_pp0_it5, ap_reg_ppiten_pp0_it6, ap_reg_ppiten_pp0_it7, ap_reg_ppiten_pp0_it8, ap_reg_ppiten_pp0_it9, ap_reg_ppiten_pp0_it10, ap_reg_ppiten_pp0_it11)
begin
if ((not((ap_const_logic_1 = ap_start)) and (ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it0) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it1) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it2) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it3) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it4) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it5) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it6) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it7) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it8) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it9) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it10) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it11))) then
ap_idle <= ap_const_logic_1;
else
ap_idle <= ap_const_logic_0;
end if;
end process;
-- ap_ready assign process. --
ap_ready_assign_proc : process(ap_start, ap_CS_fsm, ap_reg_ppiten_pp0_it0, ap_reg_ppiten_pp0_it5, indices_samples_rsp_empty_n, ap_ce)
begin
if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it5) and (indices_samples_rsp_empty_n = ap_const_logic_0)))) and (ap_const_logic_1 = ap_ce))) then
ap_ready <= ap_const_logic_1;
else
ap_ready <= ap_const_logic_0;
end if;
end process;
ap_reg_ppiten_pp0_it0 <= ap_start;
ap_return_0 <= agg_result_index_write_assign_fu_111_p3;
ap_return_1 <= agg_result_sample_write_assign_fu_105_p3;
-- ap_sig_pprstidle_pp0 assign process. --
ap_sig_pprstidle_pp0_assign_proc : process(ap_start, ap_reg_ppiten_pp0_it0, ap_reg_ppiten_pp0_it1, ap_reg_ppiten_pp0_it2, ap_reg_ppiten_pp0_it3, ap_reg_ppiten_pp0_it4, ap_reg_ppiten_pp0_it5, ap_reg_ppiten_pp0_it6, ap_reg_ppiten_pp0_it7, ap_reg_ppiten_pp0_it8, ap_reg_ppiten_pp0_it9, ap_reg_ppiten_pp0_it10)
begin
if (((ap_const_logic_0 = ap_reg_ppiten_pp0_it0) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it1) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it2) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it3) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it4) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it5) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it6) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it7) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it8) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it9) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it10) and (ap_const_logic_0 = ap_start))) then
ap_sig_pprstidle_pp0 <= ap_const_logic_1;
else
ap_sig_pprstidle_pp0 <= ap_const_logic_0;
end if;
end process;
-- grp_fu_77_ce assign process. --
grp_fu_77_ce_assign_proc : process(ap_start, ap_CS_fsm, ap_reg_ppiten_pp0_it0, ap_reg_ppiten_pp0_it5, indices_samples_rsp_empty_n, ap_ce)
begin
if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it5) and (indices_samples_rsp_empty_n = ap_const_logic_0)))) and (ap_const_logic_1 = ap_ce))) then
grp_fu_77_ce <= ap_const_logic_1;
else
grp_fu_77_ce <= ap_const_logic_0;
end if;
end process;
grp_fu_77_p0 <= std_logic_vector(resize(unsigned(indices_samples_addr_read_reg_146),17));
grp_fu_77_p1 <= ap_const_lv17_1FFFF;
-- grp_fu_83_ce assign process. --
grp_fu_83_ce_assign_proc : process(ap_start, ap_CS_fsm, ap_reg_ppiten_pp0_it0, ap_reg_ppiten_pp0_it5, indices_samples_rsp_empty_n, ap_ce)
begin
if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it5) and (indices_samples_rsp_empty_n = ap_const_logic_0)))) and (ap_const_logic_1 = ap_ce))) then
grp_fu_83_ce <= ap_const_logic_1;
else
grp_fu_83_ce <= ap_const_logic_0;
end if;
end process;
grp_fu_83_p0 <= ap_reg_ppstg_i_index_read_reg_134_pp0_it6;
grp_fu_83_p1 <= ap_const_lv16_1;
-- grp_fu_88_ce assign process. --
grp_fu_88_ce_assign_proc : process(ap_start, ap_CS_fsm, ap_reg_ppiten_pp0_it0, ap_reg_ppiten_pp0_it5, indices_samples_rsp_empty_n, ap_ce)
begin
if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it5) and (indices_samples_rsp_empty_n = ap_const_logic_0)))) and (ap_const_logic_1 = ap_ce))) then
grp_fu_88_ce <= ap_const_logic_1;
else
grp_fu_88_ce <= ap_const_logic_0;
end if;
end process;
grp_fu_88_p0 <= ap_reg_ppstg_i_sample_read_reg_128_pp0_it6;
grp_fu_88_p1 <= ap_const_lv16_1;
indices_begin_address <= ap_const_lv32_0;
indices_begin_dataout <= ap_const_lv32_0;
indices_begin_req_din <= ap_const_logic_0;
indices_begin_req_write <= ap_const_logic_0;
indices_begin_rsp_read <= ap_const_logic_0;
indices_begin_size <= ap_const_lv32_0;
indices_samples_address <= tmp_9_fu_63_p1(32 - 1 downto 0);
indices_samples_dataout <= ap_const_lv16_0;
indices_samples_req_din <= ap_const_logic_0;
-- indices_samples_req_write assign process. --
indices_samples_req_write_assign_proc : process(ap_start, ap_CS_fsm, ap_reg_ppiten_pp0_it0, ap_reg_ppiten_pp0_it5, indices_samples_rsp_empty_n, ap_ce)
begin
if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it5) and (indices_samples_rsp_empty_n = ap_const_logic_0)))) and (ap_const_logic_1 = ap_ce))) then
indices_samples_req_write <= ap_const_logic_1;
else
indices_samples_req_write <= ap_const_logic_0;
end if;
end process;
-- indices_samples_rsp_read assign process. --
indices_samples_rsp_read_assign_proc : process(ap_start, ap_CS_fsm, ap_reg_ppiten_pp0_it0, ap_reg_ppiten_pp0_it5, indices_samples_rsp_empty_n, ap_ce)
begin
if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it5) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it5) and (indices_samples_rsp_empty_n = ap_const_logic_0)))) and (ap_const_logic_1 = ap_ce))) then
indices_samples_rsp_read <= ap_const_logic_1;
else
indices_samples_rsp_read <= ap_const_logic_0;
end if;
end process;
indices_samples_size <= ap_const_lv32_1;
indices_stride_address <= ap_const_lv32_0;
indices_stride_dataout <= ap_const_lv8_0;
indices_stride_req_din <= ap_const_logic_0;
indices_stride_req_write <= ap_const_logic_0;
indices_stride_rsp_read <= ap_const_logic_0;
indices_stride_size <= ap_const_lv32_0;
tmp_1_reg_156_temp <= signed(tmp_1_reg_156);
tmp_2_fu_99_p1 <= std_logic_vector(resize(tmp_1_reg_156_temp,18));
tmp_2_fu_99_p2 <= "1" when (signed(tmp_cast_fu_93_p1) < signed(tmp_2_fu_99_p1)) else "0";
tmp_9_fu_63_p1 <= std_logic_vector(resize(unsigned(i_index),64));
tmp_cast_fu_93_p1 <= std_logic_vector(resize(unsigned(ap_reg_ppstg_i_sample_read_reg_128_pp0_it9),18));
end behav;
| lgpl-3.0 | ff54300abcba48c759302d332794e894 | 0.600019 | 2.715783 | false | false | false | false |
progranism/Open-Source-FPGA-Bitcoin-Miner | projects/VC707_experimental/VC707_experimental.srcs/sources_1/ip/golden_ticket_fifo/fifo_generator_v10_0/ramfifo/rd_status_flags_as.vhd | 9 | 15,251 | `protect begin_protected
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| gpl-3.0 | 8dcf4170409949e184cb10d73ee84db0 | 0.937906 | 1.871059 | false | false | false | false |
jairov4/accel-oil | impl/impl_test_single/simulation/behavioral/system_lmb_bram_wrapper.vhd | 1 | 2,663 | -------------------------------------------------------------------------------
-- system_lmb_bram_wrapper.vhd
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
library lmb_bram_elaborate_v1_00_a;
use lmb_bram_elaborate_v1_00_a.all;
entity system_lmb_bram_wrapper is
port (
BRAM_Rst_A : in std_logic;
BRAM_Clk_A : in std_logic;
BRAM_EN_A : in std_logic;
BRAM_WEN_A : in std_logic_vector(0 to 3);
BRAM_Addr_A : in std_logic_vector(0 to 31);
BRAM_Din_A : out std_logic_vector(0 to 31);
BRAM_Dout_A : in std_logic_vector(0 to 31);
BRAM_Rst_B : in std_logic;
BRAM_Clk_B : in std_logic;
BRAM_EN_B : in std_logic;
BRAM_WEN_B : in std_logic_vector(0 to 3);
BRAM_Addr_B : in std_logic_vector(0 to 31);
BRAM_Din_B : out std_logic_vector(0 to 31);
BRAM_Dout_B : in std_logic_vector(0 to 31)
);
end system_lmb_bram_wrapper;
architecture STRUCTURE of system_lmb_bram_wrapper is
component lmb_bram_elaborate is
generic (
C_MEMSIZE : integer;
C_PORT_DWIDTH : integer;
C_PORT_AWIDTH : integer;
C_NUM_WE : integer;
C_FAMILY : string
);
port (
BRAM_Rst_A : in std_logic;
BRAM_Clk_A : in std_logic;
BRAM_EN_A : in std_logic;
BRAM_WEN_A : in std_logic_vector(0 to C_NUM_WE-1);
BRAM_Addr_A : in std_logic_vector(0 to C_PORT_AWIDTH-1);
BRAM_Din_A : out std_logic_vector(0 to C_PORT_DWIDTH-1);
BRAM_Dout_A : in std_logic_vector(0 to C_PORT_DWIDTH-1);
BRAM_Rst_B : in std_logic;
BRAM_Clk_B : in std_logic;
BRAM_EN_B : in std_logic;
BRAM_WEN_B : in std_logic_vector(0 to C_NUM_WE-1);
BRAM_Addr_B : in std_logic_vector(0 to C_PORT_AWIDTH-1);
BRAM_Din_B : out std_logic_vector(0 to C_PORT_DWIDTH-1);
BRAM_Dout_B : in std_logic_vector(0 to C_PORT_DWIDTH-1)
);
end component;
begin
lmb_bram : lmb_bram_elaborate
generic map (
C_MEMSIZE => 16#4000#,
C_PORT_DWIDTH => 32,
C_PORT_AWIDTH => 32,
C_NUM_WE => 4,
C_FAMILY => "virtex5"
)
port map (
BRAM_Rst_A => BRAM_Rst_A,
BRAM_Clk_A => BRAM_Clk_A,
BRAM_EN_A => BRAM_EN_A,
BRAM_WEN_A => BRAM_WEN_A,
BRAM_Addr_A => BRAM_Addr_A,
BRAM_Din_A => BRAM_Din_A,
BRAM_Dout_A => BRAM_Dout_A,
BRAM_Rst_B => BRAM_Rst_B,
BRAM_Clk_B => BRAM_Clk_B,
BRAM_EN_B => BRAM_EN_B,
BRAM_WEN_B => BRAM_WEN_B,
BRAM_Addr_B => BRAM_Addr_B,
BRAM_Din_B => BRAM_Din_B,
BRAM_Dout_B => BRAM_Dout_B
);
end architecture STRUCTURE;
| lgpl-3.0 | 3f4e565776ae270caa7fe8c5ccd6ed3c | 0.558768 | 2.910383 | false | false | false | false |
wsoltys/AtomFpga | src/T6502/T65.vhd | 1 | 21,011 | -- ****
-- T65(b) core. In an effort to merge and maintain bug fixes ....
--
--
-- Ver 301 more merging
-- Ver 300 Bugfixes by ehenciak added, started tidyup *bust*
-- MikeJ March 2005
-- Latest version from www.fpgaarcade.com (original www.opencores.org)
--
-- ****
--
-- 65xx compatible microprocessor core
--
-- Version : 0246
--
-- Copyright (c) 2002 Daniel Wallner ([email protected])
--
-- All rights reserved
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--
-- Redistributions in synthesized form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- Neither the name of the author nor the names of other contributors may
-- be used to endorse or promote products derived from this software without
-- specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- Please report bugs to the author, but before you do so, please
-- make sure that this is not a derivative work and that
-- you have the latest version of this file.
--
-- The latest version of this file can be found at:
-- http://www.opencores.org/cvsweb.shtml/t65/
--
-- Limitations :
--
-- 65C02 and 65C816 modes are incomplete
-- Undocumented instructions are not supported
-- Some interface signals behaves incorrect
--
-- File history :
--
-- 0246 : First release
--
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.T65_Pack.all;
-- ehenciak 2-23-2005 : Added the enable signal so that one doesn't have to use
-- the ready signal to limit the CPU.
entity T65 is
port(
Mode : in std_logic_vector(1 downto 0); -- "00" => 6502, "01" => 65C02, "10" => 65C816
Res_n : in std_logic;
Enable : in std_logic;
Clk : in std_logic;
Rdy : in std_logic;
Abort_n : in std_logic;
IRQ_n : in std_logic;
NMI_n : in std_logic;
SO_n : in std_logic;
R_W_n : out std_logic;
Sync : out std_logic;
EF : out std_logic;
MF : out std_logic;
XF : out std_logic;
ML_n : out std_logic;
VP_n : out std_logic;
VDA : out std_logic;
VPA : out std_logic;
A : out std_logic_vector(23 downto 0);
DI : in std_logic_vector(7 downto 0);
DO : out std_logic_vector(7 downto 0)
);
end T65;
architecture rtl of T65 is
-- Registers
signal ABC, X, Y, D : std_logic_vector(15 downto 0);
signal P, AD, DL : std_logic_vector(7 downto 0) := x"00";
signal BAH : std_logic_vector(7 downto 0);
signal BAL : std_logic_vector(8 downto 0);
signal PBR : std_logic_vector(7 downto 0);
signal DBR : std_logic_vector(7 downto 0);
signal PC : unsigned(15 downto 0);
signal S : unsigned(15 downto 0);
signal EF_i : std_logic;
signal MF_i : std_logic;
signal XF_i : std_logic;
signal IR : std_logic_vector(7 downto 0);
signal MCycle : std_logic_vector(2 downto 0);
signal Mode_r : std_logic_vector(1 downto 0);
signal ALU_Op_r : std_logic_vector(3 downto 0);
signal Write_Data_r : std_logic_vector(2 downto 0);
signal Set_Addr_To_r : std_logic_vector(1 downto 0);
signal PCAdder : unsigned(8 downto 0);
signal RstCycle : std_logic;
signal IRQCycle : std_logic;
signal NMICycle : std_logic;
signal B_o : std_logic;
signal SO_n_o : std_logic;
signal IRQ_n_o : std_logic;
signal NMI_n_o : std_logic;
signal NMIAct : std_logic;
signal Break : std_logic;
-- ALU signals
signal BusA : std_logic_vector(7 downto 0);
signal BusA_r : std_logic_vector(7 downto 0);
signal BusB : std_logic_vector(7 downto 0);
signal ALU_Q : std_logic_vector(7 downto 0);
signal P_Out : std_logic_vector(7 downto 0);
-- Micro code outputs
signal LCycle : std_logic_vector(2 downto 0);
signal ALU_Op : std_logic_vector(3 downto 0);
signal Set_BusA_To : std_logic_vector(2 downto 0);
signal Set_Addr_To : std_logic_vector(1 downto 0);
signal Write_Data : std_logic_vector(2 downto 0);
signal Jump : std_logic_vector(1 downto 0);
signal BAAdd : std_logic_vector(1 downto 0);
signal BreakAtNA : std_logic;
signal ADAdd : std_logic;
signal AddY : std_logic;
signal PCAdd : std_logic;
signal Inc_S : std_logic;
signal Dec_S : std_logic;
signal LDA : std_logic;
signal LDP : std_logic;
signal LDX : std_logic;
signal LDY : std_logic;
signal LDS : std_logic;
signal LDDI : std_logic;
signal LDALU : std_logic;
signal LDAD : std_logic;
signal LDBAL : std_logic;
signal LDBAH : std_logic;
signal SaveP : std_logic;
signal Write : std_logic;
signal really_rdy : std_logic;
signal R_W_n_i : std_logic;
begin
-- ehenciak : gate Rdy with read/write to make an "OK, it's
-- really OK to stop the processor now if Rdy is
-- deasserted" signal
really_rdy <= Rdy or not(R_W_n_i);
-- ehenciak : Drive R_W_n_i off chip.
R_W_n <= R_W_n_i;
Sync <= '1' when MCycle = "000" else '0';
EF <= EF_i;
MF <= MF_i;
XF <= XF_i;
ML_n <= '0' when IR(7 downto 6) /= "10" and IR(2 downto 1) = "11" and MCycle(2 downto 1) /= "00" else '1';
VP_n <= '0' when IRQCycle = '1' and (MCycle = "101" or MCycle = "110") else '1';
VDA <= '1' when Set_Addr_To_r /= "00" else '0'; -- Incorrect !!!!!!!!!!!!
VPA <= '1' when Jump(1) = '0' else '0'; -- Incorrect !!!!!!!!!!!!
mcode : T65_MCode
port map(
Mode => Mode_r,
IR => IR,
MCycle => MCycle,
P => P,
LCycle => LCycle,
ALU_Op => ALU_Op,
Set_BusA_To => Set_BusA_To,
Set_Addr_To => Set_Addr_To,
Write_Data => Write_Data,
Jump => Jump,
BAAdd => BAAdd,
BreakAtNA => BreakAtNA,
ADAdd => ADAdd,
AddY => AddY,
PCAdd => PCAdd,
Inc_S => Inc_S,
Dec_S => Dec_S,
LDA => LDA,
LDP => LDP,
LDX => LDX,
LDY => LDY,
LDS => LDS,
LDDI => LDDI,
LDALU => LDALU,
LDAD => LDAD,
LDBAL => LDBAL,
LDBAH => LDBAH,
SaveP => SaveP,
Write => Write
);
alu : T65_ALU
port map(
Mode => Mode_r,
Op => ALU_Op_r,
BusA => BusA_r,
BusB => BusB,
P_In => P,
P_Out => P_Out,
Q => ALU_Q
);
process (Res_n, Clk)
begin
if Res_n = '0' then
PC <= (others => '0'); -- Program Counter
IR <= "00000000";
S <= (others => '0'); -- Dummy !!!!!!!!!!!!!!!!!!!!!
D <= (others => '0');
PBR <= (others => '0');
DBR <= (others => '0');
Mode_r <= (others => '0');
ALU_Op_r <= "1100";
Write_Data_r <= "000";
Set_Addr_To_r <= "00";
R_W_n_i <= '1';
EF_i <= '1';
MF_i <= '1';
XF_i <= '1';
elsif Clk'event and Clk = '1' then
if (Enable = '1') then
if (really_rdy = '1') then
R_W_n_i <= not Write or RstCycle;
D <= (others => '1'); -- Dummy
PBR <= (others => '1'); -- Dummy
DBR <= (others => '1'); -- Dummy
EF_i <= '0'; -- Dummy
MF_i <= '0'; -- Dummy
XF_i <= '0'; -- Dummy
if MCycle = "000" then
Mode_r <= Mode;
if IRQCycle = '0' and NMICycle = '0' then
PC <= PC + 1;
end if;
if IRQCycle = '1' or NMICycle = '1' then
IR <= "00000000";
else
IR <= DI;
end if;
end if;
ALU_Op_r <= ALU_Op;
Write_Data_r <= Write_Data;
if Break = '1' then
Set_Addr_To_r <= "00";
else
Set_Addr_To_r <= Set_Addr_To;
end if;
if Inc_S = '1' then
S <= S + 1;
end if;
if Dec_S = '1' and RstCycle = '0' then
S <= S - 1;
end if;
if LDS = '1' then
S(7 downto 0) <= unsigned(ALU_Q);
end if;
if IR = "00000000" and MCycle = "001" and IRQCycle = '0' and NMICycle = '0' then
PC <= PC + 1;
end if;
--
-- jump control logic
--
case Jump is
when "01" =>
PC <= PC + 1;
when "10" =>
PC <= unsigned(DI & DL);
when "11" =>
if PCAdder(8) = '1' then
if DL(7) = '0' then
PC(15 downto 8) <= PC(15 downto 8) + 1;
else
PC(15 downto 8) <= PC(15 downto 8) - 1;
end if;
end if;
PC(7 downto 0) <= PCAdder(7 downto 0);
when others => null;
end case;
end if;
end if;
end if;
end process;
PCAdder <= resize(PC(7 downto 0), 9) + resize(unsigned(DL(7) & DL), 9) when PCAdd = '1'
else "0" & PC(7 downto 0);
process (Clk)
begin
if Clk'event and Clk = '1' then
if (Enable = '1') then
if (really_rdy = '1') then
if MCycle = "000" then
if LDA = '1' then
ABC(7 downto 0) <= ALU_Q;
end if;
if LDX = '1' then
X(7 downto 0) <= ALU_Q;
end if;
if LDY = '1' then
Y(7 downto 0) <= ALU_Q;
end if;
if (LDA or LDX or LDY) = '1' then
P <= P_Out;
end if;
end if;
if SaveP = '1' then
P <= P_Out;
end if;
if LDP = '1' then
P <= ALU_Q;
end if;
if IR(4 downto 0) = "11000" then
case IR(7 downto 5) is
when "000" =>
P(Flag_C) <= '0';
when "001" =>
P(Flag_C) <= '1';
when "010" =>
P(Flag_I) <= '0';
when "011" =>
P(Flag_I) <= '1';
when "101" =>
P(Flag_V) <= '0';
when "110" =>
P(Flag_D) <= '0';
when "111" =>
P(Flag_D) <= '1';
when others =>
end case;
end if;
--if IR = "00000000" and MCycle = "011" and RstCycle = '0' and NMICycle = '0' and IRQCycle = '0' then
-- P(Flag_B) <= '1';
--end if;
--if IR = "00000000" and MCycle = "100" and RstCycle = '0' and (NMICycle = '1' or IRQCycle = '1') then
-- P(Flag_I) <= '1';
-- P(Flag_B) <= B_o;
--end if;
-- B=1 always on the 6502
P(Flag_B) <= '1';
if IR = "00000000" and RstCycle = '0' and (NMICycle = '1' or IRQCycle = '1') then
if MCycle = "011" then
-- B=0 in *copy* of P pushed onto the stack
P(Flag_B) <= '0';
elsif MCycle = "100" then
P(Flag_I) <= '1';
end if;
end if;
if SO_n_o = '1' and SO_n = '0' then
P(Flag_V) <= '1';
end if;
if RstCycle = '1' and Mode_r /= "00" then
P(Flag_1) <= '1';
P(Flag_D) <= '0';
P(Flag_I) <= '1';
end if;
P(Flag_1) <= '1';
B_o <= P(Flag_B);
SO_n_o <= SO_n;
IRQ_n_o <= IRQ_n;
NMI_n_o <= NMI_n;
end if;
end if;
end if;
end process;
---------------------------------------------------------------------------
--
-- Buses
--
---------------------------------------------------------------------------
process (Res_n, Clk)
begin
if Res_n = '0' then
BusA_r <= (others => '0');
BusB <= (others => '0');
AD <= (others => '0');
BAL <= (others => '0');
BAH <= (others => '0');
DL <= (others => '0');
elsif Clk'event and Clk = '1' then
if (Enable = '1') then
if (Rdy = '1') then
BusA_r <= BusA;
BusB <= DI;
case BAAdd is
when "01" =>
-- BA Inc
AD <= std_logic_vector(unsigned(AD) + 1);
BAL <= std_logic_vector(unsigned(BAL) + 1);
when "10" =>
-- BA Add
BAL <= std_logic_vector(resize(unsigned(BAL(7 downto 0)), 9) + resize(unsigned(BusA), 9));
when "11" =>
-- BA Adj
if BAL(8) = '1' then
BAH <= std_logic_vector(unsigned(BAH) + 1);
end if;
when others =>
end case;
-- ehenciak : modified to use Y register as well (bugfix)
if ADAdd = '1' then
if (AddY = '1') then
AD <= std_logic_vector(unsigned(AD) + unsigned(Y(7 downto 0)));
else
AD <= std_logic_vector(unsigned(AD) + unsigned(X(7 downto 0)));
end if;
end if;
if IR = "00000000" then
BAL <= (others => '1');
BAH <= (others => '1');
if RstCycle = '1' then
BAL(2 downto 0) <= "100";
elsif NMICycle = '1' then
BAL(2 downto 0) <= "010";
else
BAL(2 downto 0) <= "110";
end if;
if Set_addr_To_r = "11" then
BAL(0) <= '1';
end if;
end if;
if LDDI = '1' then
DL <= DI;
end if;
if LDALU = '1' then
DL <= ALU_Q;
end if;
if LDAD = '1' then
AD <= DI;
end if;
if LDBAL = '1' then
BAL(7 downto 0) <= DI;
end if;
if LDBAH = '1' then
BAH <= DI;
end if;
end if;
end if;
end if;
end process;
Break <= (BreakAtNA and not BAL(8)) or (PCAdd and not PCAdder(8));
with Set_BusA_To select
BusA <= DI when "000",
ABC(7 downto 0) when "001",
X(7 downto 0) when "010",
Y(7 downto 0) when "011",
std_logic_vector(S(7 downto 0)) when "100",
P when "101",
(others => '-') when others;
with Set_Addr_To_r select
A <= "0000000000000001" & std_logic_vector(S(7 downto 0)) when "01",
DBR & "00000000" & AD when "10",
"00000000" & BAH & BAL(7 downto 0) when "11",
PBR & std_logic_vector(PC(15 downto 8)) & std_logic_vector(PCAdder(7 downto 0)) when others;
with Write_Data_r select
DO <= DL when "000",
ABC(7 downto 0) when "001",
X(7 downto 0) when "010",
Y(7 downto 0) when "011",
std_logic_vector(S(7 downto 0)) when "100",
P when "101",
std_logic_vector(PC(7 downto 0)) when "110",
std_logic_vector(PC(15 downto 8)) when others;
-------------------------------------------------------------------------
--
-- Main state machine
--
-------------------------------------------------------------------------
process (Res_n, Clk)
begin
if Res_n = '0' then
MCycle <= "001";
RstCycle <= '1';
IRQCycle <= '0';
NMICycle <= '0';
NMIAct <= '0';
elsif Clk'event and Clk = '1' then
if (Enable = '1') then
if (really_rdy = '1') then
if MCycle = LCycle or Break = '1' then
MCycle <= "000";
RstCycle <= '0';
IRQCycle <= '0';
NMICycle <= '0';
if NMIAct = '1' then
NMICycle <= '1';
elsif IRQ_n_o = '0' and P(Flag_I) = '0' then
IRQCycle <= '1';
end if;
else
MCycle <= std_logic_vector(unsigned(MCycle) + 1);
end if;
if NMICycle = '1' then
NMIAct <= '0';
end if;
if NMI_n_o = '1' and NMI_n = '0' then
NMIAct <= '1';
end if;
end if;
end if;
end if;
end process;
end;
| apache-2.0 | d5611ab34d1e97f97ea58530e03ca50e | 0.389367 | 4.274873 | false | false | false | false |
jairov4/accel-oil | solution_virtex5_plb/syn/vhdl/nfa_accept_samples_generic_hw_start_indices.vhd | 1 | 3,257 | -- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2014.1
-- Copyright (C) 2014 Xilinx Inc. All rights reserved.
--
-- ==============================================================
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity nfa_accept_samples_generic_hw_start_indices_ram is
generic(
mem_type : string := "distributed";
dwidth : integer := 32;
awidth : integer := 4;
mem_size : integer := 16
);
port (
addr0 : in std_logic_vector(awidth-1 downto 0);
ce0 : in std_logic;
d0 : in std_logic_vector(dwidth-1 downto 0);
we0 : in std_logic;
q0 : out std_logic_vector(dwidth-1 downto 0);
clk : in std_logic
);
end entity;
architecture rtl of nfa_accept_samples_generic_hw_start_indices_ram is
signal addr0_tmp : std_logic_vector(awidth-1 downto 0);
type mem_array is array (0 to mem_size-1) of std_logic_vector (dwidth-1 downto 0);
shared variable ram : mem_array;
attribute syn_ramstyle : string;
attribute syn_ramstyle of ram : variable is "select_ram";
attribute ram_style : string;
attribute ram_style of ram : variable is mem_type;
attribute EQUIVALENT_REGISTER_REMOVAL : string;
begin
memory_access_guard_0: process (addr0)
begin
addr0_tmp <= addr0;
--synthesis translate_off
if (CONV_INTEGER(addr0) > mem_size-1) then
addr0_tmp <= (others => '0');
else
addr0_tmp <= addr0;
end if;
--synthesis translate_on
end process;
p_memory_access_0: process (clk)
begin
if (clk'event and clk = '1') then
if (ce0 = '1') then
if (we0 = '1') then
ram(CONV_INTEGER(addr0_tmp)) := d0;
end if;
q0 <= ram(CONV_INTEGER(addr0_tmp));
end if;
end if;
end process;
end rtl;
Library IEEE;
use IEEE.std_logic_1164.all;
entity nfa_accept_samples_generic_hw_start_indices is
generic (
DataWidth : INTEGER := 32;
AddressRange : INTEGER := 16;
AddressWidth : INTEGER := 4);
port (
reset : IN STD_LOGIC;
clk : IN STD_LOGIC;
address0 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0);
ce0 : IN STD_LOGIC;
we0 : IN STD_LOGIC;
d0 : IN STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0);
q0 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0));
end entity;
architecture arch of nfa_accept_samples_generic_hw_start_indices is
component nfa_accept_samples_generic_hw_start_indices_ram is
port (
clk : IN STD_LOGIC;
addr0 : IN STD_LOGIC_VECTOR;
ce0 : IN STD_LOGIC;
d0 : IN STD_LOGIC_VECTOR;
we0 : IN STD_LOGIC;
q0 : OUT STD_LOGIC_VECTOR);
end component;
begin
nfa_accept_samples_generic_hw_start_indices_ram_U : component nfa_accept_samples_generic_hw_start_indices_ram
port map (
clk => clk,
addr0 => address0,
ce0 => ce0,
d0 => d0,
we0 => we0,
q0 => q0);
end architecture;
| lgpl-3.0 | 4585fff4a0c6f872b00d345fd3fad37a | 0.561253 | 3.555677 | false | false | false | false |
grwlf/vsim | vhdl_ct/ct00593.vhd | 1 | 2,950 | -- NEED RESULT: ARCH00593: Resolution functions may appear in subtype indications used in signal and non-signal declaration passed
-------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
-------------------------------------------------------------------------------
--
-- TEST NAME:
--
-- CT00593
--
-- AUTHOR:
--
-- A. Wilmot
--
-- TEST OBJECTIVES:
--
-- 4.2 (1)
--
-- DESIGN UNIT ORDERING:
--
-- E00000(ARCH00593)
-- ENT00593_Test_Bench(ARCH00593_Test_Bench)
--
-- REVISION HISTORY:
--
-- 26-AUG-1987 - initial revision
--
-- NOTES:
--
-- self-checking
--
use WORK.STANDARD_TYPES.all ;
architecture ARCH00593 of E00000 is
subtype rst_integer is bf_integer integer ;
signal s_integer : bf_integer integer := c_integer_1;
subtype rst_arr1 is bf_arr1 t_arr1 (lowb to highb) ;
signal s_arr1 : rst_arr1 := c_st_arr1_1;
subtype rst_rec2 is bf_rec2 st_rec2 ;
signal s_rec2 : rst_rec2 := c_t_rec2_1;
signal toggle : boolean := false ;
begin
process
variable v_integer : bf_integer integer := 1 ;
variable v_arr1 : rst_arr1 ;
variable v_rec2 : rst_rec2 ;
begin
v_integer := v_integer + 1 ;
s_integer <= v_integer ;
for i in lowb to highb loop
v_arr1(i) := st_int1 ( i + 10) ;
end loop ;
s_arr1 <= v_arr1(lowb to highb) ;
v_rec2 := (true, (1, 10 ns, false, 1.0), 2 fs) ;
s_rec2 <= v_rec2 ;
toggle <= true ;
wait ;
end process ;
process
variable v_integer : rst_integer := 2 ;
variable v_arr1 : bf_arr1 t_arr1 (highb downto lowb) ;
variable v_rec2 : rst_rec2 ;
begin
v_integer := v_integer + 1 ;
s_integer <= v_integer ;
for i in lowb to highb loop
v_arr1(i) := st_int1 ( i + 10) ;
end loop ;
s_arr1 <= v_arr1(highb downto lowb) ;
v_rec2 := (false, (2, 15 ns, true, 2.0), 3 fs) ;
s_rec2 <= v_rec2 ;
wait ;
end process ;
process ( s_integer, s_arr1, s_rec2 )
begin
if toggle then
test_report ( "ARCH00593" ,
"Resolution functions may appear in subtype indications "
& " used in signal and non-signal declaration" ,
s_integer = 5 and
s_arr1 = st_arr1'(others => st_int1 ( highb+lowb+20)) and
s_rec2 = (true, (3, 25 ns, true, 3.0), 5 fs) ) ;
end if ;
end process ;
end ARCH00593 ;
--
entity ENT00593_Test_Bench is
end ENT00593_Test_Bench ;
architecture ARCH00593_Test_Bench of ENT00593_Test_Bench is
begin
L1:
block
component UUT
end component ;
for CIS1 : UUT use entity WORK.E00000 ( ARCH00593 ) ;
begin
CIS1 : UUT ;
end block L1 ;
end ARCH00593_Test_Bench ;
--
| gpl-3.0 | 3511ae2448b9cd385aefdcf400524bf9 | 0.522712 | 3.241758 | false | true | false | false |
jairov4/accel-oil | impl/impl_test_single/simulation/behavioral/system_tb.vhd | 1 | 1,995 | -------------------------------------------------------------------------------
-- system_tb.vhd
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
-- START USER CODE (Do not remove this line)
-- User: Put your libraries here. Code in this
-- section will not be overwritten.
-- END USER CODE (Do not remove this line)
entity system_tb is
end system_tb;
architecture STRUCTURE of system_tb is
constant fpga_0_clk_1_sys_clk_pin_PERIOD : time := 10000.000000 ps;
constant fpga_0_rst_1_sys_rst_pin_LENGTH : time := 160000 ps;
component system is
port (
fpga_0_clk_1_sys_clk_pin : in std_logic;
fpga_0_rst_1_sys_rst_pin : in std_logic
);
end component;
-- Internal signals
signal fpga_0_clk_1_sys_clk_pin : std_logic;
signal fpga_0_rst_1_sys_rst_pin : std_logic;
-- START USER CODE (Do not remove this line)
-- User: Put your signals here. Code in this
-- section will not be overwritten.
-- END USER CODE (Do not remove this line)
begin
dut : system
port map (
fpga_0_clk_1_sys_clk_pin => fpga_0_clk_1_sys_clk_pin,
fpga_0_rst_1_sys_rst_pin => fpga_0_rst_1_sys_rst_pin
);
-- Clock generator for fpga_0_clk_1_sys_clk_pin
process
begin
fpga_0_clk_1_sys_clk_pin <= '0';
loop
wait for (fpga_0_clk_1_sys_clk_pin_PERIOD/2);
fpga_0_clk_1_sys_clk_pin <= not fpga_0_clk_1_sys_clk_pin;
end loop;
end process;
-- Reset Generator for fpga_0_rst_1_sys_rst_pin
process
begin
fpga_0_rst_1_sys_rst_pin <= '0';
wait for (fpga_0_rst_1_sys_rst_pin_LENGTH);
fpga_0_rst_1_sys_rst_pin <= not fpga_0_rst_1_sys_rst_pin;
wait;
end process;
-- START USER CODE (Do not remove this line)
-- User: Put your stimulus here. Code in this
-- section will not be overwritten.
-- END USER CODE (Do not remove this line)
end architecture STRUCTURE;
| lgpl-3.0 | 228a68dd8a2038c1a8cf9b93392ee674 | 0.597494 | 3.22294 | false | false | false | false |
grwlf/vsim | vhdl/timage1.vhd | 1 | 514 | entity ENT00001_Test_Bench is
end entity ENT00001_Test_Bench;
architecture arch of ENT00001_Test_Bench is
constant CYCLES : integer := 1000;
signal clk : integer := 0;
begin
main: process(clk)
begin
report integer'image(clk);
report "clk = " & integer'image(clk);
end process;
terminator : process(clk)
begin
if clk >= CYCLES then
assert false report "end of simulation" severity failure;
-- else
-- report "tick";
end if;
end process;
clk <= (clk+1) after 1 us;
end;
| gpl-3.0 | 3f4ea42646fadc0f3636238d94d82e00 | 0.667315 | 3.253165 | false | true | false | false |
wsoltys/AtomFpga | src/AVR8/FrqDiv/FrqDiv.vhd | 1 | 1,384 | --**********************************************************************************************
-- Frequency divider for AVR uC (40 MHz -> 4 MHz or 40 MHz -> 20 MHz)
-- Version 1.52(Dust Inc version)
-- Modified 16.01.2006
-- Designed by Ruslan Lepetenok
--**********************************************************************************************
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
use WORK.AVRuCPackage.all;
entity FrqDiv is port(
clk_in : in std_logic;
clk_out : out std_logic
);
end FrqDiv;
architecture RTL of FrqDiv is
signal DivCnt : std_logic_vector(3 downto 0);
signal clk_out_int : std_logic;
constant Div2 : boolean := TRUE;
begin
-- Must be sequentially encoded
DivideBy10:if not Div2 generate
Gen:process(clk_in)
begin
if(clk_in='1' and clk_in'event) then -- Clock
if(DivCnt=x"4") then DivCnt <= x"0";
else DivCnt <= DivCnt + 1;
end if;
if(DivCnt=x"4") then clk_out_int <= not clk_out_int;
end if;
end if;
end process;
end generate;
DivideBy10:if Div2 generate
Gen:process(clk_in)
begin
if(clk_in='1' and clk_in'event) then -- Clock
clk_out_int <= not clk_out_int;
end if;
end process;
end generate;
clk_out <= clk_out_int;
end RTL;
| apache-2.0 | 0272a784a5b5a33fd54ff46a035d13f2 | 0.515896 | 3.400491 | false | false | false | false |
MrDoomBringer/DSD-Labs | Lab 9/BCD_to_sevenseg.vhd | 3 | 7,271 | -- BCD display for hex displays
-- (c) Cliff Chapman 2013
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
USE ieee.std_logic_signed.ALL;
-- Seven segment display output
--
ENTITY sevenseg_bcd_display IS
port (
-- Input value to display
R : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
-- Hex/Dec display select
S : IN STD_LOGIC;
-- sevenseg outputs
HEX0 : OUT STD_LOGIC_VECTOR (6 DOWNTO 0) := "1111111";
HEX1 : OUT STD_LOGIC_VECTOR (6 DOWNTO 0) := "1111111";
HEX2 : OUT STD_LOGIC_VECTOR (6 DOWNTO 0) := "1111111"
);
END sevenseg_bcd_display;
ARCHITECTURE display OF sevenseg_bcd_display IS
-- Hex output displays, customized for Altera DE2 board. May require
-- redefinition for different board setups.
CONSTANT hex_blk : STD_LOGIC_VECTOR (6 DOWNTO 0) := "1111111";
CONSTANT hex_neg : STD_LOGIC_VECTOR (6 DOWNTO 0) := "0111111";
CONSTANT hex_zer : STD_LOGIC_VECTOR (6 DOWNTO 0) := "1000000";
CONSTANT hex_one : STD_LOGIC_VECTOR (6 DOWNTO 0) := "1111001";
CONSTANT hex_two : STD_LOGIC_VECTOR (6 DOWNTO 0) := "0100100";
CONSTANT hex_thr : STD_LOGIC_VECTOR (6 DOWNTO 0) := "0110000";
CONSTANT hex_fou : STD_LOGIC_VECTOR (6 DOWNTO 0) := "0011001";
CONSTANT hex_fiv : STD_LOGIC_VECTOR (6 DOWNTO 0) := "0010010";
CONSTANT hex_six : STD_LOGIC_VECTOR (6 DOWNTO 0) := "0000010";
CONSTANT hex_sev : STD_LOGIC_VECTOR (6 DOWNTO 0) := "1111000";
CONSTANT hex_eig : STD_LOGIC_VECTOR (6 DOWNTO 0) := "0000000";
CONSTANT hex_nin : STD_LOGIC_VECTOR (6 DOWNTO 0) := "0011000";
CONSTANT hex_0xa : STD_LOGIC_VECTOR (6 DOWNTO 0) := "0001000";
CONSTANT hex_0xb : STD_LOGIC_VECTOR (6 DOWNTO 0) := "0000011";
CONSTANT hex_0xc : STD_LOGIC_VECTOR (6 DOWNTO 0) := "1000110";
CONSTANT hex_0xd : STD_LOGIC_VECTOR (6 DOWNTO 0) := "0100001";
CONSTANT hex_0xe : STD_LOGIC_VECTOR (6 DOWNTO 0) := "0000110";
CONSTANT hex_0xf : STD_LOGIC_VECTOR (6 DOWNTO 0) := "0001110";
-- Internal buffer signals for display select
SIGNAL HEX0_buff_hex : STD_LOGIC_VECTOR (6 DOWNTO 0);
SIGNAL HEX1_buff_hex : STD_LOGIC_VECTOR (6 DOWNTO 0);
SIGNAL HEX2_buff_hex : STD_LOGIC_VECTOR (6 DOWNTO 0);
SIGNAL HEX0_buff_dec : STD_LOGIC_VECTOR (6 DOWNTO 0);
SIGNAL HEX1_buff_dec : STD_LOGIC_VECTOR (6 DOWNTO 0);
SIGNAL HEX2_buff_dec : STD_LOGIC_VECTOR (6 DOWNTO 0);
BEGIN
-- Generate a hex display
display_hex : PROCESS (R)
ALIAS high_bit : STD_LOGIC_VECTOR (3 DOWNTO 0) IS R (7 DOWNTO 4);
ALIAS low_bit : STD_LOGIC_VECTOR (3 DOWNTO 0) IS R (3 DOWNTO 0);
BEGIN
CASE high_bit IS
WHEN "0000" => HEX1_buff_hex <= hex_zer;
WHEN "0001" => HEX1_buff_hex <= hex_one;
WHEN "0010" => HEX1_buff_hex <= hex_two;
WHEN "0011" => HEX1_buff_hex <= hex_thr;
WHEN "0100" => HEX1_buff_hex <= hex_fou;
WHEN "0101" => HEX1_buff_hex <= hex_fiv;
WHEN "0110" => HEX1_buff_hex <= hex_six;
WHEN "0111" => HEX1_buff_hex <= hex_sev;
WHEN "1000" => HEX1_buff_hex <= hex_eig;
WHEN "1001" => HEX1_buff_hex <= hex_nin;
WHEN "1010" => HEX1_buff_hex <= hex_0xa;
WHEN "1011" => HEX1_buff_hex <= hex_0xb;
WHEN "1100" => HEX1_buff_hex <= hex_0xc;
WHEN "1101" => HEX1_buff_hex <= hex_0xd;
WHEN "1110" => HEX1_buff_hex <= hex_0xe;
WHEN "1111" => HEX1_buff_hex <= hex_0xf;
WHEN OTHERS => HEX1_buff_hex <= hex_blk;
END CASE;
CASE low_bit IS
WHEN "0000" => HEX2_buff_hex <= hex_zer;
WHEN "0001" => HEX2_buff_hex <= hex_one;
WHEN "0010" => HEX2_buff_hex <= hex_two;
WHEN "0011" => HEX2_buff_hex <= hex_thr;
WHEN "0100" => HEX2_buff_hex <= hex_fou;
WHEN "0101" => HEX2_buff_hex <= hex_fiv;
WHEN "0110" => HEX2_buff_hex <= hex_six;
WHEN "0111" => HEX2_buff_hex <= hex_sev;
WHEN "1000" => HEX2_buff_hex <= hex_eig;
WHEN "1001" => HEX2_buff_hex <= hex_nin;
WHEN "1010" => HEX2_buff_hex <= hex_0xa;
WHEN "1011" => HEX2_buff_hex <= hex_0xb;
WHEN "1100" => HEX2_buff_hex <= hex_0xc;
WHEN "1101" => HEX2_buff_hex <= hex_0xd;
WHEN "1110" => HEX2_buff_hex <= hex_0xe;
WHEN "1111" => HEX2_buff_hex <= hex_0xf;
WHEN OTHERS => HEX2_buff_hex <= hex_blk;
END CASE;
END PROCESS display_hex;
-- Generate a decimal display
display_dec: PROCESS (R)
ALIAS sign_bit : STD_LOGIC IS R (7);
VARIABLE r_lower: STD_LOGIC_VECTOR (7 DOWNTO 0);
VARIABLE r_buff : STD_LOGIC_VECTOR (7 DOWNTO 0);
BEGIN
-- Select value to work off of
IF (sign_bit='1') THEN
HEX0_buff_dec <= hex_neg;
r_buff := (NOT(R) + "00000001");
ELSIF (sign_bit='0') THEN
HEX0_buff_dec <= hex_blk;
r_buff := R;
ELSE
HEX0_buff_dec <= hex_blk;
r_buff := "00000000";
END IF;
-- Display higher digit
IF (r_buff >= "00000000" AND r_buff < "00001010") THEN -- Within 0-9
HEX1_buff_dec <= hex_zer;
r_lower := r_buff;
ELSIF (r_buff >= "00001010" AND r_buff < "00010100") THEN -- Within 10-19
HEX1_buff_dec <= hex_one;
r_lower := r_buff - "00001010";
ELSIF (r_buff >= "00010100" AND r_buff < "00011110") THEN -- Within 20-29
HEX1_buff_dec <= hex_two;
r_lower := r_buff - "00010100";
ELSIF (r_buff >= "00011110" AND r_buff < "00101000") THEN -- Within 30-39
HEX1_buff_dec <= hex_thr;
r_lower := r_buff - "00011110";
ELSIF (r_buff >= "00101000" AND r_buff < "00110010") THEN -- Within 40-49
HEX1_buff_dec <= hex_fou;
r_lower := r_buff - "00101000";
ELSIF (r_buff >= "00110010" AND r_buff < "00111100") THEN -- Within 50-59
HEX1_buff_dec <= hex_fiv;
r_lower := r_buff - "00110010";
ELSIF (r_buff >= "00111100" AND r_buff < "01000110") THEN -- Within 60-69
HEX1_buff_dec <= hex_six;
r_lower := r_buff - "00111100";
ELSIF (r_buff >= "01000110" AND r_buff < "01010000") THEN -- Within 70-79
HEX1_buff_dec <= hex_sev;
r_lower := r_buff - "01000110";
ELSIF (r_buff >= "01010000" AND r_buff < "01011010") THEN -- Within 80-89
HEX1_buff_dec <= hex_eig;
r_lower := r_buff - "01010000";
ELSIF (r_buff >= "01011010" AND r_buff < "01100100") THEN -- Within 90-99
HEX1_buff_dec <= hex_nin;
r_lower := r_buff - "01011010";
ELSE -- 99 is the highest value we can reliably display. Higher is out of range
HEX1_buff_dec <= hex_neg;
r_lower := "11111111";
END IF;
-- Display lower digit
CASE r_lower IS
WHEN "00000000" => HEX2_buff_dec <= hex_zer;
WHEN "00000001" => HEX2_buff_dec <= hex_one;
WHEN "00000010" => HEX2_buff_dec <= hex_two;
WHEN "00000011" => HEX2_buff_dec <= hex_thr;
WHEN "00000100" => HEX2_buff_dec <= hex_fou;
WHEN "00000101" => HEX2_buff_dec <= hex_fiv;
WHEN "00000110" => HEX2_buff_dec <= hex_six;
WHEN "00000111" => HEX2_buff_dec <= hex_sev;
WHEN "00001000" => HEX2_buff_dec <= hex_eig;
WHEN "00001001" => HEX2_buff_dec <= hex_nin;
WHEN "11111111" => HEX2_buff_dec <= hex_neg; -- Out of range
WHEN OTHERS => HEX2_buff_dec <= hex_zer;
END CASE;
END PROCESS display_dec;
-- Select display type for output
select_display : PROCESS (S, HEX0_buff_hex, HEX1_buff_hex, HEX2_buff_hex, HEX0_buff_dec, HEX1_buff_dec, HEX2_buff_dec)
BEGIN
IF (s = '0') THEN
HEX2 <= hex_blk;
HEX1 <= HEX1_buff_hex;
HEX0 <= HEX2_buff_hex;
ELSIF (s = '1') THEN
HEX2 <= HEX0_buff_dec;
HEX1 <= HEX1_buff_dec;
HEX0 <= HEX2_buff_dec;
ELSE
HEX2 <= hex_blk;
HEX1 <= hex_blk;
HEX0 <= hex_blk;
END IF;
END PROCESS select_display;
END display; | mit | 59aa025f78f012d3852659c6180974f9 | 0.626186 | 2.705992 | false | false | false | false |
grwlf/vsim | vhdl/entity3.vhd | 1 | 1,076 | -- Simple entity test, array and indexed mappings
library ieee;
use ieee.std_logic_1164.all ;
entity main is
end entity main;
library ieee;
use ieee.std_logic_1164.all ;
entity unit1 is
port (
inum : in std_ulogic_vector (0 to 1);
oled : out std_ulogic);
begin
end;
architecture unit1 of unit1 is
begin
oled <= inum(0) and inum(1);
end architecture unit1;
architecture main of main is
constant CYCLES : integer := 100;
signal clk : integer := 0;
signal o1 : std_ulogic;
signal o2 : std_ulogic;
signal o : std_ulogic;
signal const_1 : std_ulogic := '1';
signal i : std_ulogic_vector (0 to 1);
begin
terminator : process(clk)
begin
if clk >= CYCLES then
assert false report "end of simulation" severity failure;
end if;
end process;
u1:entity unit1(unit1) port map(inum=>(0=>'0', 1=>const_1), oled=>o1);
u2:entity unit1(unit1) port map(inum=>i, oled=>o2);
i <= (others => '0');
o <= o1 and o2;
clk <= clk + 1 after 1 us;
end architecture main;
| gpl-3.0 | 5fd1758c7dc47b34b85f535f3b5384ef | 0.6171 | 3.118841 | false | false | false | false |
wsoltys/AtomFpga | src/AtomGodilVideo/src/mouse/mouse_controller.vhd | 1 | 42,573 | ------------------------------------------------------------------------
-- mouse_controller.vhd
------------------------------------------------------------------------
-- Author : Ulrich Zolt�n
-- Copyright 2006 Digilent, Inc.
------------------------------------------------------------------------
-- Software version : Xilinx ISE 7.1.04i
-- WebPack
-- Device : 3s200ft256-4
------------------------------------------------------------------------
-- This file contains a controller for a ps/2 compatible mouse device.
-- This controller is a client for the ps2interface module.
------------------------------------------------------------------------
-- Behavioral description
------------------------------------------------------------------------
-- Please read the following article on the web for understanding how
-- to interface a ps/2 mouse:
-- http://www.computer-engineering.org/ps2mouse/
-- This controller is implemented as described in the above article.
-- The mouse controller receives bytes from the ps2interface which, in
-- turn, receives them from the mouse device. Data is received on the
-- rx_data input port, and is validated by the read signal. read is
-- active for one clock period when new byte available on rx_data. Data
-- is sent to the ps2interface on the tx_data output port and validated
-- by the write output signal. 'write' should be active for one clock
-- period when tx_data contains the command or data to be sent to the
-- mouse. ps2interface wraps the byte in a 11 bits packet that is sent
-- through the ps/2 port using the ps/2 protocol. Similarly, when the
-- mouse sends data, the ps2interface receives 11 bits for every byte,
-- extracts the byte from the ps/2 frame, puts it on rx_data and
-- activates read for one clock period. If an error occurs when sending
-- or receiving a frame from the mouse, the err input goes high for one
-- clock period. When this occurs, the controller enters reset state.
-- When in reset state, the controller resets the mouse and begins an
-- initialization procedure that consists of tring to put mouse in
-- scroll mode (enables wheel if the mouse has one), setting the
-- resolution of the mouse, the sample rate and finally enables
-- reporting. Implicitly the mouse, after a reset or imediately after a
-- reset, does not send data packets on its own. When reset(or power-up)
-- the mouse enters reset state, where it performs a test, called the
-- bat test (basic assurance test), when this test is done, it sends
-- the result: AAh for test ok, FCh for error. After this it sends its
-- ID which is 00h. When this is done, the mouse enters stream mode,
-- but with reporting disabled (movement data packets are not sent).
-- To enable reporting the enable data reporting command (F4h) must be
-- sent to the mouse. After this command is sent, the mouse will send
-- movement data packets when the mouse is moved or the status of the
-- button changes.
-- After sending a command or a byte following a command, the mouse
-- must respond with ack (FAh). For managing the intialization
-- procedure and receiving the movement data packets, a FSM is used.
-- When the fpga is powered up or the logic is reset using the global
-- reset, the FSM enters reset state. From this state, the FSM will
-- transition to a series of states used to initialize the mouse. When
-- initialization is complete, the FSM remains in state read_byte_1,
-- waiting for a movement data packet to be sent. This is the idle
-- state if the FSM. When a byte is received in this state, this is
-- the first byte of the 3 bytes sent in a movement data packet (4 bytes
-- if mouse in scrolling mode). After reading the last byte from the
-- packet, the FSM enters mark_new_event state and sets new_event high.
-- After that FSM enterss read_byte_1 state, resets new_event and waits
-- for a new packet.
-- After a packet is received, new_event is set high for one clock
-- period to "inform" the clients of this controller a new packet was
-- received and processed.
-- During the initialization procedure, the controller tries to put the
-- mouse in scroll mode (activates wheel, if mouse has one). This is
-- done by successively setting the sample rate to 200, then to 100, and
-- lastly to 80. After this is done, the mouse ID is requested by
-- sending get device ID command (F2h). If the received ID is 00h than
-- the mouse does not have a wheel. If the received ID is 03h than the
-- mouse is in scroll mode, and when sending movement data packets
-- (after enabling data reporting) it will include z movement data.
-- If the mouse is in normal, non-scroll mode, the movement data packet
-- consists of 3 successive bytes. This is their format:
--
--
--
-- bits 7 6 5 4 3 2 1 0
-- -------------------------------------------------
-- byte 1 | YOVF| XOVF|YSIGN|XSIGN| 1 | MBTN| RBTN| LBTN|
-- -------------------------------------------------
-- -------------------------------------------------
-- byte 2 | X MOVEMENT |
-- -------------------------------------------------
-- -------------------------------------------------
-- byte 3 | Y MOVEMENT |
-- -------------------------------------------------
-- OVF = overflow
-- BTN = button
-- M = middle
-- R = right
-- L = left
--
-- When scroll mode is enabled, the mouse send 4 byte movement packets.
-- bits 7 6 5 4 3 2 1 0
-- -------------------------------------------------
-- byte 1 | YOVF| XOVF|YSIGN|XSIGN| 1 | MBTN| RBTN| LBTN|
-- -------------------------------------------------
-- -------------------------------------------------
-- byte 2 | X MOVEMENT |
-- -------------------------------------------------
-- -------------------------------------------------
-- byte 3 | Y MOVEMENT |
-- -------------------------------------------------
-- -------------------------------------------------
-- byte 4 | Z MOVEMENT |
-- -------------------------------------------------
-- x and y movement counters are represented on 8 bits, 2's complement
-- encoding. The first bit (sign bit) of the counters are the xsign and
-- ysign bit from the first packet, the rest of the bits are the second
-- byte for the x movement and the third byte for y movement. For the
-- z movement the range is -8 -> +7 and only the 4 least significant
-- bits from z movement are valid, the rest are sign extensions.
-- The x and y movements are in range: -256 -> +255
-- The mouse uses as axes origin the lower-left corner. For the purpose
-- of displaying a mouse cursor on the screen, the controller inverts
-- the y axis to move the axes origin in the upper-left corner. This
-- is done by negating the y movement value (following the 2s complement
-- encoding). The movement data received from the mouse are delta
-- movements, the data represents the movement of the mouse relative
-- to the last position. The controller keeps track of the position of
-- the mouse relative to the upper-left corner. This is done by keeping
-- the mouse position in two registers x_pos and y_pos and adding the
-- delta movements to their value. The addition uses saturation. That
-- means the value of the mouse position will not exceed certain bounds
-- and will not rollover the a margin. For example, if the mouse is at
-- the left margin and is moved left, the x position remains at the left
-- margin(0). The lower bound is always 0 for both x and y movement.
-- The upper margin can be set using input pins: value, setmax_x,
-- setmax_y. To set the upper bound of the x movement counter, the new
-- value is placed on the value input pins and setmax_x is activated
-- for at least one clock period. Similarly for y movement counter, but
-- setmax_y is activated instead. Notice that value has 10 bits, and so
-- the maximum value for a bound is 1023.
-- The position of the mouse (x_pos and y_pos) can be set at any time,
-- by placing the x or y position on the value input pins and activating
-- the setx, or sety respectively, for at least one clock period. This
-- is useful for setting an original position of the mouse different
-- from (0,0).
------------------------------------------------------------------------
-- Port definitions
------------------------------------------------------------------------
-- clk - global clock signal (100MHz)
-- rst - global reset signal
-- read - input pin, from ps2interface
-- - active one clock period when new data received
-- - and available on rx_data
-- err - input pin, from ps2interface
-- - active one clock period when error occurred when
-- - receiving or sending data.
-- rx_data - input pin, 8 bits, from ps2interface
-- - the byte received from the mouse.
-- xpos - output pin, 10 bits
-- - the x position of the mouse relative to the upper
-- - left corner
-- ypos - output pin, 10 bits
-- - the y position of the mouse relative to the upper
-- - left corner
-- zpos - output pin, 4 bits
-- - last delta movement on z axis
-- left - output pin, high if the left mouse button is pressed
-- middle - output pin, high if the middle mouse button is
-- - pressed
-- right - output pin, high if the right mouse button is
-- - pressed
-- new_event - output pin, active one clock period after receiving
-- - and processing one movement data packet.
-- tx_data - output pin, 8 bits, to ps2interface
-- - byte to be sent to the mouse
-- write - output pin, to ps2interface
-- - active one clock period when sending a byte to the
-- - ps2interface.
------------------------------------------------------------------------
-- Revision History:
-- 09/18/2006(UlrichZ): created
------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- simulation library
library UNISIM;
--use UNISIM.VComponents.all;
-- the mouse_controller entity declaration
-- read above for behavioral description and port definitions.
entity mouse_controller is
port(
clk : in std_logic;
rst : in std_logic;
read : in std_logic;
err : in std_logic;
rx_data : in std_logic_vector(7 downto 0);
xpos : out std_logic_vector(9 downto 0);
ypos : out std_logic_vector(9 downto 0);
zpos : out std_logic_vector(3 downto 0);
left : out std_logic;
middle : out std_logic;
right : out std_logic;
new_event : out std_logic;
tx_data : out std_logic_vector(7 downto 0);
write : out std_logic;
value : in std_logic_vector(9 downto 0);
setx : in std_logic;
sety : in std_logic;
setmax_x : in std_logic;
setmax_y : in std_logic
);
end mouse_controller;
architecture Behavioral of mouse_controller is
------------------------------------------------------------------------
-- CONSTANTS
------------------------------------------------------------------------
-- constants defining commands to send or received from the mouse
constant FA: std_logic_vector(7 downto 0) := "11111010"; -- 0xFA(ACK)
constant FF: std_logic_vector(7 downto 0) := "11111111"; -- 0xFF(RESET)
constant AA: std_logic_vector(7 downto 0) := "10101010"; -- 0xAA(BAT_OK)
constant OO: std_logic_vector(7 downto 0) := "00000000"; -- 0x00(ID)
-- (atention: name is 2 letters O not zero)
-- command to read id
constant READ_ID : std_logic_vector(7 downto 0) := x"F2";
-- command to enable mouse reporting
-- after this command is sent, the mouse begins sending data packets
constant ENABLE_REPORTING : std_logic_vector(7 downto 0) := x"F4";
-- command to set the mouse resolution
constant SET_RESOLUTION : std_logic_vector(7 downto 0) := x"E8";
-- the value of the resolution to send after sending SET_RESOLUTION
constant RESOLUTION : std_logic_vector(7 downto 0) := x"03";
-- (8 counts/mm)
-- command to set the mouse sample rate
constant SET_SAMPLE_RATE : std_logic_vector(7 downto 0) := x"F3";
-- the value of the sample rate to send after sending SET_SAMPLE_RATE
constant SAMPLE_RATE : std_logic_vector(7 downto 0) := x"28";
-- (40 samples/s)
-- default maximum value for the horizontal mouse position
constant DEFAULT_MAX_X : std_logic_vector(9 downto 0) := "1001111111";
-- 639
-- default maximum value for the vertical mouse position
constant DEFAULT_MAX_Y : std_logic_vector(9 downto 0) := "0111011111";
-- 479
------------------------------------------------------------------------
-- SIGNALS
------------------------------------------------------------------------
-- after doing the enable scroll mouse procedure, if the ID returned by
-- the mouse is 03 (scroll mouse enabled) then this register will be set
-- If '1' then the mouse is in scroll mode, else mouse is in simple
-- mouse mode.
signal haswheel: std_logic := '0';
-- horizontal and veritcal mouse position
-- origin of axes is upper-left corner
-- the origin of axes the mouse uses is the lower-left corner
-- The y-axis is inverted, by making negative the y movement received
-- from the mouse (if it was positive it becomes negative
-- and vice versa)
signal x_pos,y_pos: std_logic_vector(10 downto 0) := (others => '0');
-- active when an overflow occurred on the x and y axis
-- bits 6 and 7 from the first byte received from the mouse
signal x_overflow,y_overflow: std_logic := '0';
-- active when the x,y movement is negative
-- bits 4 and 5 from the first byte received from the mouse
signal x_sign,y_sign: std_logic := '0';
-- 2's complement value for incrementing the x_pos,y_pos
-- y_inc is the negated value from the mouse in the third byte
signal x_inc,y_inc: std_logic_vector(7 downto 0) := (others => '0');
-- active for one clock period, indicates new delta movement received
-- on x,y axis
signal x_new,y_new: std_logic := '0';
-- maximum value for x and y position registers(x_pos,y_pos)
signal x_max,y_max: std_logic_vector(9 downto 0) := (others => '0');
-- active when left,middle,right mouse button is down
signal left_down,middle_down,right_down: std_logic := '0';
-- the FSM states
-- states that begin with "reset" are part of the reset procedure.
-- states that end in "_wait_ack" are states in which ack is waited
-- as response to sending a byte to the mouse.
-- read behavioral description above for details.
type fsm_state is
(
reset,reset_wait_ack,reset_wait_bat_completion,reset_wait_id,
reset_set_sample_rate_200,reset_set_sample_rate_200_wait_ack,
reset_send_sample_rate_200,reset_send_sample_rate_200_wait_ack,
reset_set_sample_rate_100,reset_set_sample_rate_100_wait_ack,
reset_send_sample_rate_100,reset_send_sample_rate_100_wait_ack,
reset_set_sample_rate_80,reset_set_sample_rate_80_wait_ack,
reset_send_sample_rate_80,reset_send_sample_rate_80_wait_ack,
reset_read_id,reset_read_id_wait_ack,reset_read_id_wait_id,
reset_set_resolution,reset_set_resolution_wait_ack,
reset_send_resolution,reset_send_resolution_wait_ack,
reset_set_sample_rate_40,reset_set_sample_rate_40_wait_ack,
reset_send_sample_rate_40,reset_send_sample_rate_40_wait_ack,
reset_enable_reporting,reset_enable_reporting_wait_ack,
read_byte_1,read_byte_2,read_byte_3,read_byte_4,mark_new_event
);
-- holds current state of the FSM
signal state: fsm_state := reset;
begin
-- left output the state of the left_down register
left <= left_down when rising_edge(clk);
-- middle output the state of the middle_down register
middle <= middle_down when rising_edge(clk);
-- right output the state of the right_down register
right <= right_down when rising_edge(clk);
-- xpos output is the horizontal position of the mouse
-- it has the range: 0-x_max
xpos <= x_pos(9 downto 0) when rising_edge(clk);
-- ypos output is the vertical position of the mouse
-- it has the range: 0-y_max
ypos <= y_pos(9 downto 0) when rising_edge(clk);
-- sets the value of x_pos from another module when setx is active
-- else, computes the new x_pos from the old position when new x
-- movement detected by adding the delta movement in x_inc, or by
-- adding 256 or -256 when overflow occurs.
set_x: process(clk)
variable x_inter: std_logic_vector(10 downto 0);
variable inc: std_logic_vector(10 downto 0);
begin
if(rising_edge(clk)) then
-- if setx active, set new x_pos value
if(setx = '1') then
x_pos <= '0' & value;
-- if delta movement received from mouse
elsif(x_new = '1') then
-- if negative movement on x axis
if(x_sign = '1') then
-- if overflow occurred
if(x_overflow = '1') then
-- inc is -256
inc := "11100000000";
else
-- inc is sign extended x_inc
inc := "111" & x_inc;
end if;
-- intermediary horizontal position
x_inter := x_pos + inc;
-- if first bit of x_inter is 1
-- then negative overflow occurred and
-- new x position is 0.
-- Note: x_pos and x_inter have 11 bits,
-- and because xpos has only 10, when
-- first bit becomes 1, this is considered
-- a negative number when moving left
if(x_inter(10) = '1') then
x_pos <= (others => '0');
else
x_pos <= x_inter;
end if;
-- if positive movement on x axis
else
-- if overflow occurred
if(x_overflow = '1') then
-- inc is 256
inc := "00100000000";
else
-- inc is sign extended x_inc
inc := "000" & x_inc;
end if;
-- intermediary horizontal position
x_inter := x_pos + inc;
-- if x_inter is greater than x_max
-- then positive overflow occurred and
-- new x position is x_max.
if(x_inter > ('0' & x_max)) then
x_pos <= '0' & x_max;
else
x_pos <= x_inter;
end if;
end if;
end if;
end if;
end process set_x;
-- sets the value of y_pos from another module when sety is active
-- else, computes the new y_pos from the old position when new y
-- movement detected by adding the delta movement in y_inc, or by
-- adding 256 or -256 when overflow occurs.
set_y: process(clk)
variable y_inter: std_logic_vector(10 downto 0);
variable inc: std_logic_vector(10 downto 0);
begin
if(rising_edge(clk)) then
-- if sety active, set new y_pos value
if(sety = '1') then
y_pos <= '0' & value;
-- if delta movement received from mouse
elsif(y_new = '1') then
-- if negative movement on y axis
-- Note: axes origin is upper-left corner
if(y_sign = '1') then
-- if overflow occurred
if(y_overflow = '1') then
-- inc is -256
inc := "11100000000";
else
-- inc is sign extended y_inc
inc := "111" & y_inc;
end if;
-- intermediary vertical position
y_inter := y_pos + inc;
-- if first bit of y_inter is 1
-- then negative overflow occurred and
-- new y position is 0.
-- Note: y_pos and y_inter have 11 bits,
-- and because ypos has only 10, when
-- first bit becomes 1, this is considered
-- a negative number when moving upward
if(y_inter(10) = '1') then
y_pos <= (others => '0');
else
y_pos <= y_inter;
end if;
-- if positive movement on y axis
else
-- if overflow occurred
if(y_overflow = '1') then
-- inc is 256
inc := "00100000000";
else
-- inc is sign extended y_inc
inc := "000" & y_inc;
end if;
-- intermediary vertical position
y_inter := y_pos + inc;
-- if y_inter is greater than y_max
-- then positive overflow occurred and
-- new y position is y_max.
if(y_inter > ('0' & y_max)) then
y_pos <= '0' & y_max;
else
y_pos <= y_inter;
end if;
end if;
end if;
end if;
end process set_y;
-- sets the maximum value of the x movement register, stored in x_max
-- when setmax_x is active, max value should be on value input pin
set_max_x: process(clk,rst)
begin
if(rising_edge(clk)) then
if(rst = '1') then
x_max <= DEFAULT_MAX_X;
elsif(setmax_x = '1') then
x_max <= value;
end if;
end if;
end process set_max_x;
-- sets the maximum value of the y movement register, stored in y_max
-- when setmax_y is active, max value should be on value input pin
set_max_y: process(clk,rst)
begin
if(rising_edge(clk)) then
if(rst = '1') then
y_max <= DEFAULT_MAX_Y;
elsif(setmax_y = '1') then
y_max <= value;
end if;
end if;
end process set_max_y;
-- Synchronous one process fsm to handle the communication
-- with the mouse.
-- When reset and at start-up it enters reset state
-- where it begins the procedure of initializing the mouse.
-- After initialization is complete, it waits packets from
-- the mouse.
-- Read at Behavioral decription for details.
manage_fsm: process(clk,rst)
begin
-- when reset occurs, give signals default values.
if(rst = '1') then
state <= reset;
haswheel <= '0';
x_overflow <= '0';
y_overflow <= '0';
x_sign <= '0';
y_sign <= '0';
x_inc <= (others => '0');
y_inc <= (others => '0');
x_new <= '0';
y_new <= '0';
new_event <= '0';
left_down <= '0';
middle_down <= '0';
right_down <= '0';
elsif(rising_edge(clk)) then
-- at every rising edge of the clock, this signals
-- are reset, thus assuring that they are active
-- for one clock period only if a state sets then
-- because the fsm will transition from the state
-- that set them on the next rising edge of clock.
write <= '0';
x_new <= '0';
y_new <= '0';
case state is
-- if just powered-up, reset occurred or some error in
-- transmision encountered, then fsm will transition to
-- this state. Here the RESET command (FF) is sent to the
-- mouse, and various signals receive their default values
-- From here the FSM transitions to a series of states that
-- perform the mouse initialization procedure. All this
-- state are prefixed by "reset_". After sending a byte
-- to the mouse, it respondes by sending ack (FA). All
-- states that wait ack from the mouse are postfixed by
-- "_wait_ack".
-- Read at Behavioral decription for details.
when reset =>
haswheel <= '0';
x_overflow <= '0';
y_overflow <= '0';
x_sign <= '0';
y_sign <= '0';
x_inc <= (others => '0');
y_inc <= (others => '0');
x_new <= '0';
y_new <= '0';
left_down <= '0';
middle_down <= '0';
right_down <= '0';
tx_data <= FF;
write <= '1';
state <= reset_wait_ack;
-- wait ack for the reset command.
-- when received transition to reset_wait_bat_completion.
-- if error occurs go to reset state.
when reset_wait_ack =>
if(read = '1') then
-- if received ack
if(rx_data = FA) then
state <= reset_wait_bat_completion;
else
state <= reset;
end if;
elsif(err = '1') then
state <= reset;
else
state <= reset_wait_ack;
end if;
-- wait for bat completion test
-- mouse should send AA if test is successful
when reset_wait_bat_completion =>
if(read = '1') then
if(rx_data = AA) then
state <= reset_wait_id;
else
state <= reset;
end if;
elsif(err = '1') then
state <= reset;
else
state <= reset_wait_bat_completion;
end if;
-- the mouse sends its id after performing bat test
-- the mouse id should be 00
when reset_wait_id =>
if(read = '1') then
if(rx_data = OO) then
state <= reset_set_sample_rate_200;
else
state <= reset;
end if;
elsif(err = '1') then
state <= reset;
else
state <= reset_wait_id;
end if;
-- with this state begins the enable wheel mouse
-- procedure. The procedure consists of setting
-- the sample rate of the mouse first 200, then 100
-- then 80. After this is done, the mouse id is
-- requested and if the mouse id is 03, then
-- mouse is in wheel mode and will send 4 byte packets
-- when reporting is enabled.
-- If the id is 00, the mouse does not have a wheel
-- and will send 3 byte packets when reporting is enabled.
-- This state issues the set_sample_rate command to the
-- mouse.
when reset_set_sample_rate_200 =>
tx_data <= SET_SAMPLE_RATE;
write <= '1';
state <= reset_set_sample_rate_200_wait_ack;
-- wait ack for set sample rate command
when reset_set_sample_rate_200_wait_ack =>
if(read = '1') then
if(rx_data = FA) then
state <= reset_send_sample_rate_200;
else
state <= reset;
end if;
elsif(err = '1') then
state <= reset;
else
state <= reset_set_sample_rate_200_wait_ack;
end if;
-- send the desired sample rate (200 = 0xC8)
when reset_send_sample_rate_200 =>
tx_data <= "11001000"; -- 0xC8
write <= '1';
state <= reset_send_sample_rate_200_wait_ack;
-- wait ack for sending the sample rate
when reset_send_sample_rate_200_wait_ack =>
if(read = '1') then
if(rx_data = FA) then
state <= reset_set_sample_rate_100;
else
state <= reset;
end if;
elsif(err = '1') then
state <= reset;
else
state <= reset_send_sample_rate_200_wait_ack;
end if;
-- send the sample rate command
when reset_set_sample_rate_100 =>
tx_data <= SET_SAMPLE_RATE;
write <= '1';
state <= reset_set_sample_rate_100_wait_ack;
-- wait ack for sending the sample rate command
when reset_set_sample_rate_100_wait_ack =>
if(read = '1') then
if(rx_data = FA) then
state <= reset_send_sample_rate_100;
else
state <= reset;
end if;
elsif(err = '1') then
state <= reset;
else
state <= reset_set_sample_rate_100_wait_ack;
end if;
-- send the desired sample rate (100 = 0x64)
when reset_send_sample_rate_100 =>
tx_data <= "01100100"; -- 0x64
write <= '1';
state <= reset_send_sample_rate_100_wait_ack;
-- wait ack for sending the sample rate
when reset_send_sample_rate_100_wait_ack =>
if(read = '1') then
if(rx_data = FA) then
state <= reset_set_sample_rate_80;
else
state <= reset;
end if;
elsif(err = '1') then
state <= reset;
else
state <= reset_send_sample_rate_100_wait_ack;
end if;
-- send set sample rate command
when reset_set_sample_rate_80 =>
tx_data <= SET_SAMPLE_RATE;
write <= '1';
state <= reset_set_sample_rate_80_wait_ack;
-- wait ack for sending the sample rate command
when reset_set_sample_rate_80_wait_ack =>
if(read = '1') then
if(rx_data = FA) then
state <= reset_send_sample_rate_80;
else
state <= reset;
end if;
elsif(err = '1') then
state <= reset;
else
state <= reset_set_sample_rate_80_wait_ack;
end if;
-- send desired sample rate (80 = 0x50)
when reset_send_sample_rate_80 =>
tx_data <= "01010000"; -- 0x50
write <= '1';
state <= reset_send_sample_rate_80_wait_ack;
-- wait ack for sending the sample rate
when reset_send_sample_rate_80_wait_ack =>
if(read = '1') then
if(rx_data = FA) then
state <= reset_read_id;
else
state <= reset;
end if;
elsif(err = '1') then
state <= reset;
else
state <= reset_send_sample_rate_80_wait_ack;
end if;
-- now the procedure for enabling wheel mode is done
-- the mouse id is read to determine is mouse is in
-- wheel mode.
-- Read ID command is sent to the mouse.
when reset_read_id =>
tx_data <= READ_ID;
write <= '1';
state <= reset_read_id_wait_ack;
-- wait ack for sending the read id command
when reset_read_id_wait_ack =>
if(read = '1') then
if(rx_data = FA) then
state <= reset_read_id_wait_id;
else
state <= reset;
end if;
elsif(err = '1') then
state <= reset;
else
state <= reset_read_id_wait_ack;
end if;
-- received the mouse id
-- if the id is 00, then the mouse does not have
-- a wheel and haswheel is reset
-- if the id is 03, then the mouse is in scroll mode
-- and haswheel is set.
-- if anything else is received or an error occurred
-- then the FSM transitions to reset state.
when reset_read_id_wait_id =>
if(read = '1') then
if(rx_data = "000000000") then
-- the mouse does not have a wheel
haswheel <= '0';
state <= reset_set_resolution;
elsif(rx_data = "00000011") then -- 0x03
-- the mouse is in scroll mode
haswheel <= '1';
state <= reset_set_resolution;
else
state <= reset;
end if;
elsif(err = '1') then
state <= reset;
else
state <= reset_read_id_wait_id;
end if;
-- send the set resolution command to the mouse
when reset_set_resolution =>
tx_data <= SET_RESOLUTION;
write <= '1';
state <= reset_set_resolution_wait_ack;
-- wait ack for sending the set resolution command
when reset_set_resolution_wait_ack =>
if(read = '1') then
if(rx_data = FA) then
state <= reset_send_resolution;
else
state <= reset;
end if;
elsif(err = '1') then
state <= reset;
else
state <= reset_set_resolution_wait_ack;
end if;
-- send the desired resolution (0x03 = 8 counts/mm)
when reset_send_resolution =>
tx_data <= RESOLUTION;
write <= '1';
state <= reset_send_resolution_wait_ack;
-- wait ack for sending the resolution
when reset_send_resolution_wait_ack =>
if(read = '1') then
if(rx_data = FA) then
state <= reset_set_sample_rate_40;
else
state <= reset;
end if;
elsif(err = '1') then
state <= reset;
else
state <= reset_send_resolution_wait_ack;
end if;
-- send the set sample rate command
when reset_set_sample_rate_40 =>
tx_data <= SET_SAMPLE_RATE;
write <= '1';
state <= reset_set_sample_rate_40_wait_ack;
-- wait ack for sending the set sample rate command
when reset_set_sample_rate_40_wait_ack =>
if(read = '1') then
if(rx_data = FA) then
state <= reset_send_sample_rate_40;
else
state <= reset;
end if;
elsif(err = '1') then
state <= reset;
else
state <= reset_set_sample_rate_40_wait_ack;
end if;
-- send the desired sampele rate.
-- 40 samples per second is sent.
when reset_send_sample_rate_40 =>
tx_data <= SAMPLE_RATE;
write <= '1';
state <= reset_send_sample_rate_40_wait_ack;
-- wait ack for sending the sample rate
when reset_send_sample_rate_40_wait_ack =>
if(read = '1') then
if(rx_data = FA) then
state <= reset_enable_reporting;
else
state <= reset;
end if;
elsif(err = '1') then
state <= reset;
else
state <= reset_send_sample_rate_40_wait_ack;
end if;
-- in this state enable reporting command is sent
-- to the mouse. Before this point, the mouse
-- does not send packets. Only after issuing this
-- command, the mouse begins sending data packets,
-- 3 byte packets if it doesn't have a wheel and
-- 4 byte packets if it is in scroll mode.
when reset_enable_reporting =>
tx_data <= ENABLE_REPORTING;
write <= '1';
state <= reset_enable_reporting_wait_ack;
-- wait ack for sending the enable reporting command
when reset_enable_reporting_wait_ack =>
if(read = '1') then
if(rx_data = FA) then
state <= read_byte_1;
else
state <= reset;
end if;
elsif(err = '1') then
state <= reset;
else
state <= reset_enable_reporting_wait_ack;
end if;
-- this is idle state of the FSM after the
-- initialization is complete.
-- Here the first byte of a packet is waited.
-- The first byte contains the state of the
-- buttons, the sign of the x and y movement
-- and overflow information about these movements
-- First byte looks like this:
-- 7 6 5 4 3 2 1 0
------------------------------------------------------
-- | Y OVF | X OVF | Y SIGN | X SIGN | 1 | M | R | L |
------------------------------------------------------
when read_byte_1 =>
-- reset new_event when back in idle state.
new_event <= '0';
-- reset last z delta movement
zpos <= (others => '0');
if(read = '1') then
-- mouse button states
left_down <= rx_data(0);
middle_down <= rx_data(2);
right_down <= rx_data(1);
-- sign of the movement data
x_sign <= rx_data(4);
-- y sign is changed to invert the y axis
-- because the mouse uses the lower-left corner
-- as axes origin and it is placed in the upper-left
-- corner by this inversion (suitable for displaying
-- a mouse cursor on the screen).
-- y movement data from the third packet must be
-- also negated.
y_sign <= not rx_data(5);
-- overflow status of the x and y movement
x_overflow <= rx_data(6);
y_overflow <= rx_data(7);
-- transition to state read_byte_2
state <= read_byte_2;
else
-- no byte received yet.
state <= read_byte_1;
end if;
-- wait the second byte of the packet
-- this byte contains the x movement counter.
when read_byte_2 =>
if(read = '1') then
-- put the delta movement in x_inc
x_inc <= rx_data;
-- signal the arrival of new x movement data.
x_new <= '1';
-- go to state read_byte_3.
state <= read_byte_3;
elsif(err = '1') then
state <= reset;
else
-- byte not received yet.
state <= read_byte_2;
end if;
-- wait the third byte of the data, that
-- contains the y data movement counter.
-- negate its value, for the axis to be
-- inverted.
-- If mouse is in scroll mode, transition
-- to read_byte_4, else go to mark_new_event
when read_byte_3 =>
if(read = '1') then
-- when y movement is 0, then ignore
if(rx_data /= "00000000") then
-- 2's complement positive numbers
-- become negative and vice versa
y_inc <= (not rx_data) + "00000001";
y_new <= '1';
end if;
-- if the mouse has a wheel then transition
-- to read_byte_4, else go to mark_new_event
if(haswheel = '1') then
state <= read_byte_4;
else
state <= mark_new_event;
end if;
elsif(err = '1') then
state <= reset;
else
state <= read_byte_3;
end if;
-- only reached when mouse is in scroll mode
-- wait for the fourth byte to arrive
-- fourth byte contains the z movement counter
-- only least significant 4 bits are relevant
-- the rest are sign extension.
when read_byte_4 =>
if(read = '1') then
-- zpos is the delta movement on z
zpos <= rx_data(3 downto 0);
-- packet completly received,
-- go to mark_new_event
state <= mark_new_event;
elsif(err = '1') then
state <= reset;
else
state <= read_byte_4;
end if;
-- set new_event high
-- it will be reset in next state
-- informs client new packet received and processed
when mark_new_event =>
new_event <= '1';
state <= read_byte_1;
-- if invalid transition occurred, reset
when others =>
state <= reset;
end case;
end if;
end process manage_fsm;
end Behavioral; | apache-2.0 | 85352a0356548859fb10e6fb6c52cdf5 | 0.505673 | 4.538002 | false | false | false | false |
jairov4/accel-oil | impl/impl_test_pcie/simulation/behavioral/system_ilmb_cntlr_wrapper.vhd | 1 | 18,331 | -------------------------------------------------------------------------------
-- system_ilmb_cntlr_wrapper.vhd
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
library lmb_bram_if_cntlr_v3_10_c;
use lmb_bram_if_cntlr_v3_10_c.all;
entity system_ilmb_cntlr_wrapper is
port (
LMB_Clk : in std_logic;
LMB_Rst : in std_logic;
LMB_ABus : in std_logic_vector(0 to 31);
LMB_WriteDBus : in std_logic_vector(0 to 31);
LMB_AddrStrobe : in std_logic;
LMB_ReadStrobe : in std_logic;
LMB_WriteStrobe : in std_logic;
LMB_BE : in std_logic_vector(0 to 3);
Sl_DBus : out std_logic_vector(0 to 31);
Sl_Ready : out std_logic;
Sl_Wait : out std_logic;
Sl_UE : out std_logic;
Sl_CE : out std_logic;
LMB1_ABus : in std_logic_vector(0 to 31);
LMB1_WriteDBus : in std_logic_vector(0 to 31);
LMB1_AddrStrobe : in std_logic;
LMB1_ReadStrobe : in std_logic;
LMB1_WriteStrobe : in std_logic;
LMB1_BE : in std_logic_vector(0 to 3);
Sl1_DBus : out std_logic_vector(0 to 31);
Sl1_Ready : out std_logic;
Sl1_Wait : out std_logic;
Sl1_UE : out std_logic;
Sl1_CE : out std_logic;
LMB2_ABus : in std_logic_vector(0 to 31);
LMB2_WriteDBus : in std_logic_vector(0 to 31);
LMB2_AddrStrobe : in std_logic;
LMB2_ReadStrobe : in std_logic;
LMB2_WriteStrobe : in std_logic;
LMB2_BE : in std_logic_vector(0 to 3);
Sl2_DBus : out std_logic_vector(0 to 31);
Sl2_Ready : out std_logic;
Sl2_Wait : out std_logic;
Sl2_UE : out std_logic;
Sl2_CE : out std_logic;
LMB3_ABus : in std_logic_vector(0 to 31);
LMB3_WriteDBus : in std_logic_vector(0 to 31);
LMB3_AddrStrobe : in std_logic;
LMB3_ReadStrobe : in std_logic;
LMB3_WriteStrobe : in std_logic;
LMB3_BE : in std_logic_vector(0 to 3);
Sl3_DBus : out std_logic_vector(0 to 31);
Sl3_Ready : out std_logic;
Sl3_Wait : out std_logic;
Sl3_UE : out std_logic;
Sl3_CE : out std_logic;
BRAM_Rst_A : out std_logic;
BRAM_Clk_A : out std_logic;
BRAM_EN_A : out std_logic;
BRAM_WEN_A : out std_logic_vector(0 to 3);
BRAM_Addr_A : out std_logic_vector(0 to 31);
BRAM_Din_A : in std_logic_vector(0 to 31);
BRAM_Dout_A : out std_logic_vector(0 to 31);
Interrupt : out std_logic;
UE : out std_logic;
CE : out std_logic;
SPLB_CTRL_PLB_ABus : in std_logic_vector(0 to 31);
SPLB_CTRL_PLB_PAValid : in std_logic;
SPLB_CTRL_PLB_masterID : in std_logic_vector(0 to 0);
SPLB_CTRL_PLB_RNW : in std_logic;
SPLB_CTRL_PLB_BE : in std_logic_vector(0 to 3);
SPLB_CTRL_PLB_size : in std_logic_vector(0 to 3);
SPLB_CTRL_PLB_type : in std_logic_vector(0 to 2);
SPLB_CTRL_PLB_wrDBus : in std_logic_vector(0 to 31);
SPLB_CTRL_Sl_addrAck : out std_logic;
SPLB_CTRL_Sl_SSize : out std_logic_vector(0 to 1);
SPLB_CTRL_Sl_wait : out std_logic;
SPLB_CTRL_Sl_rearbitrate : out std_logic;
SPLB_CTRL_Sl_wrDAck : out std_logic;
SPLB_CTRL_Sl_wrComp : out std_logic;
SPLB_CTRL_Sl_rdDBus : out std_logic_vector(0 to 31);
SPLB_CTRL_Sl_rdDAck : out std_logic;
SPLB_CTRL_Sl_rdComp : out std_logic;
SPLB_CTRL_Sl_MBusy : out std_logic_vector(0 to 0);
SPLB_CTRL_Sl_MWrErr : out std_logic_vector(0 to 0);
SPLB_CTRL_Sl_MRdErr : out std_logic_vector(0 to 0);
SPLB_CTRL_PLB_UABus : in std_logic_vector(0 to 31);
SPLB_CTRL_PLB_SAValid : in std_logic;
SPLB_CTRL_PLB_rdPrim : in std_logic;
SPLB_CTRL_PLB_wrPrim : in std_logic;
SPLB_CTRL_PLB_abort : in std_logic;
SPLB_CTRL_PLB_busLock : in std_logic;
SPLB_CTRL_PLB_MSize : in std_logic_vector(0 to 1);
SPLB_CTRL_PLB_lockErr : in std_logic;
SPLB_CTRL_PLB_wrBurst : in std_logic;
SPLB_CTRL_PLB_rdBurst : in std_logic;
SPLB_CTRL_PLB_wrPendReq : in std_logic;
SPLB_CTRL_PLB_rdPendReq : in std_logic;
SPLB_CTRL_PLB_wrPendPri : in std_logic_vector(0 to 1);
SPLB_CTRL_PLB_rdPendPri : in std_logic_vector(0 to 1);
SPLB_CTRL_PLB_reqPri : in std_logic_vector(0 to 1);
SPLB_CTRL_PLB_TAttribute : in std_logic_vector(0 to 15);
SPLB_CTRL_Sl_wrBTerm : out std_logic;
SPLB_CTRL_Sl_rdWdAddr : out std_logic_vector(0 to 3);
SPLB_CTRL_Sl_rdBTerm : out std_logic;
SPLB_CTRL_Sl_MIRQ : out std_logic_vector(0 to 0);
S_AXI_CTRL_ACLK : in std_logic;
S_AXI_CTRL_ARESETN : in std_logic;
S_AXI_CTRL_AWADDR : in std_logic_vector(31 downto 0);
S_AXI_CTRL_AWVALID : in std_logic;
S_AXI_CTRL_AWREADY : out std_logic;
S_AXI_CTRL_WDATA : in std_logic_vector(31 downto 0);
S_AXI_CTRL_WSTRB : in std_logic_vector(3 downto 0);
S_AXI_CTRL_WVALID : in std_logic;
S_AXI_CTRL_WREADY : out std_logic;
S_AXI_CTRL_BRESP : out std_logic_vector(1 downto 0);
S_AXI_CTRL_BVALID : out std_logic;
S_AXI_CTRL_BREADY : in std_logic;
S_AXI_CTRL_ARADDR : in std_logic_vector(31 downto 0);
S_AXI_CTRL_ARVALID : in std_logic;
S_AXI_CTRL_ARREADY : out std_logic;
S_AXI_CTRL_RDATA : out std_logic_vector(31 downto 0);
S_AXI_CTRL_RRESP : out std_logic_vector(1 downto 0);
S_AXI_CTRL_RVALID : out std_logic;
S_AXI_CTRL_RREADY : in std_logic
);
end system_ilmb_cntlr_wrapper;
architecture STRUCTURE of system_ilmb_cntlr_wrapper is
component lmb_bram_if_cntlr is
generic (
C_BASEADDR : std_logic_vector(0 to 31);
C_HIGHADDR : std_logic_vector(0 to 31);
C_FAMILY : string;
C_MASK : std_logic_vector(0 to 31);
C_MASK1 : std_logic_vector(0 to 31);
C_MASK2 : std_logic_vector(0 to 31);
C_MASK3 : std_logic_vector(0 to 31);
C_LMB_AWIDTH : integer;
C_LMB_DWIDTH : integer;
C_ECC : integer;
C_INTERCONNECT : integer;
C_FAULT_INJECT : integer;
C_CE_FAILING_REGISTERS : integer;
C_UE_FAILING_REGISTERS : integer;
C_ECC_STATUS_REGISTERS : integer;
C_ECC_ONOFF_REGISTER : integer;
C_ECC_ONOFF_RESET_VALUE : integer;
C_CE_COUNTER_WIDTH : integer;
C_WRITE_ACCESS : integer;
C_NUM_LMB : integer;
C_SPLB_CTRL_BASEADDR : std_logic_vector;
C_SPLB_CTRL_HIGHADDR : std_logic_vector;
C_SPLB_CTRL_AWIDTH : INTEGER;
C_SPLB_CTRL_DWIDTH : INTEGER;
C_SPLB_CTRL_P2P : INTEGER;
C_SPLB_CTRL_MID_WIDTH : INTEGER;
C_SPLB_CTRL_NUM_MASTERS : INTEGER;
C_SPLB_CTRL_SUPPORT_BURSTS : INTEGER;
C_SPLB_CTRL_NATIVE_DWIDTH : INTEGER;
C_S_AXI_CTRL_BASEADDR : std_logic_vector(31 downto 0);
C_S_AXI_CTRL_HIGHADDR : std_logic_vector(31 downto 0);
C_S_AXI_CTRL_ADDR_WIDTH : INTEGER;
C_S_AXI_CTRL_DATA_WIDTH : INTEGER
);
port (
LMB_Clk : in std_logic;
LMB_Rst : in std_logic;
LMB_ABus : in std_logic_vector(0 to C_LMB_AWIDTH-1);
LMB_WriteDBus : in std_logic_vector(0 to C_LMB_DWIDTH-1);
LMB_AddrStrobe : in std_logic;
LMB_ReadStrobe : in std_logic;
LMB_WriteStrobe : in std_logic;
LMB_BE : in std_logic_vector(0 to C_LMB_DWIDTH/8-1);
Sl_DBus : out std_logic_vector(0 to C_LMB_DWIDTH-1);
Sl_Ready : out std_logic;
Sl_Wait : out std_logic;
Sl_UE : out std_logic;
Sl_CE : out std_logic;
LMB1_ABus : in std_logic_vector(0 to C_LMB_AWIDTH-1);
LMB1_WriteDBus : in std_logic_vector(0 to C_LMB_DWIDTH-1);
LMB1_AddrStrobe : in std_logic;
LMB1_ReadStrobe : in std_logic;
LMB1_WriteStrobe : in std_logic;
LMB1_BE : in std_logic_vector(0 to C_LMB_DWIDTH/8-1);
Sl1_DBus : out std_logic_vector(0 to C_LMB_DWIDTH-1);
Sl1_Ready : out std_logic;
Sl1_Wait : out std_logic;
Sl1_UE : out std_logic;
Sl1_CE : out std_logic;
LMB2_ABus : in std_logic_vector(0 to C_LMB_AWIDTH-1);
LMB2_WriteDBus : in std_logic_vector(0 to C_LMB_DWIDTH-1);
LMB2_AddrStrobe : in std_logic;
LMB2_ReadStrobe : in std_logic;
LMB2_WriteStrobe : in std_logic;
LMB2_BE : in std_logic_vector(0 to C_LMB_DWIDTH/8-1);
Sl2_DBus : out std_logic_vector(0 to C_LMB_DWIDTH-1);
Sl2_Ready : out std_logic;
Sl2_Wait : out std_logic;
Sl2_UE : out std_logic;
Sl2_CE : out std_logic;
LMB3_ABus : in std_logic_vector(0 to C_LMB_AWIDTH-1);
LMB3_WriteDBus : in std_logic_vector(0 to C_LMB_DWIDTH-1);
LMB3_AddrStrobe : in std_logic;
LMB3_ReadStrobe : in std_logic;
LMB3_WriteStrobe : in std_logic;
LMB3_BE : in std_logic_vector(0 to C_LMB_DWIDTH/8-1);
Sl3_DBus : out std_logic_vector(0 to C_LMB_DWIDTH-1);
Sl3_Ready : out std_logic;
Sl3_Wait : out std_logic;
Sl3_UE : out std_logic;
Sl3_CE : out std_logic;
BRAM_Rst_A : out std_logic;
BRAM_Clk_A : out std_logic;
BRAM_EN_A : out std_logic;
BRAM_WEN_A : out std_logic_vector(0 to ((C_LMB_DWIDTH+8*C_ECC)/8)-1);
BRAM_Addr_A : out std_logic_vector(0 to C_LMB_AWIDTH-1);
BRAM_Din_A : in std_logic_vector(0 to C_LMB_DWIDTH-1+8*C_ECC);
BRAM_Dout_A : out std_logic_vector(0 to C_LMB_DWIDTH-1+8*C_ECC);
Interrupt : out std_logic;
UE : out std_logic;
CE : out std_logic;
SPLB_CTRL_PLB_ABus : in std_logic_vector(0 to 31);
SPLB_CTRL_PLB_PAValid : in std_logic;
SPLB_CTRL_PLB_masterID : in std_logic_vector(0 to (C_SPLB_CTRL_MID_WIDTH-1));
SPLB_CTRL_PLB_RNW : in std_logic;
SPLB_CTRL_PLB_BE : in std_logic_vector(0 to ((C_SPLB_CTRL_DWIDTH/8)-1));
SPLB_CTRL_PLB_size : in std_logic_vector(0 to 3);
SPLB_CTRL_PLB_type : in std_logic_vector(0 to 2);
SPLB_CTRL_PLB_wrDBus : in std_logic_vector(0 to (C_SPLB_CTRL_DWIDTH-1));
SPLB_CTRL_Sl_addrAck : out std_logic;
SPLB_CTRL_Sl_SSize : out std_logic_vector(0 to 1);
SPLB_CTRL_Sl_wait : out std_logic;
SPLB_CTRL_Sl_rearbitrate : out std_logic;
SPLB_CTRL_Sl_wrDAck : out std_logic;
SPLB_CTRL_Sl_wrComp : out std_logic;
SPLB_CTRL_Sl_rdDBus : out std_logic_vector(0 to (C_SPLB_CTRL_DWIDTH-1));
SPLB_CTRL_Sl_rdDAck : out std_logic;
SPLB_CTRL_Sl_rdComp : out std_logic;
SPLB_CTRL_Sl_MBusy : out std_logic_vector(0 to (C_SPLB_CTRL_NUM_MASTERS-1));
SPLB_CTRL_Sl_MWrErr : out std_logic_vector(0 to (C_SPLB_CTRL_NUM_MASTERS-1));
SPLB_CTRL_Sl_MRdErr : out std_logic_vector(0 to (C_SPLB_CTRL_NUM_MASTERS-1));
SPLB_CTRL_PLB_UABus : in std_logic_vector(0 to 31);
SPLB_CTRL_PLB_SAValid : in std_logic;
SPLB_CTRL_PLB_rdPrim : in std_logic;
SPLB_CTRL_PLB_wrPrim : in std_logic;
SPLB_CTRL_PLB_abort : in std_logic;
SPLB_CTRL_PLB_busLock : in std_logic;
SPLB_CTRL_PLB_MSize : in std_logic_vector(0 to 1);
SPLB_CTRL_PLB_lockErr : in std_logic;
SPLB_CTRL_PLB_wrBurst : in std_logic;
SPLB_CTRL_PLB_rdBurst : in std_logic;
SPLB_CTRL_PLB_wrPendReq : in std_logic;
SPLB_CTRL_PLB_rdPendReq : in std_logic;
SPLB_CTRL_PLB_wrPendPri : in std_logic_vector(0 to 1);
SPLB_CTRL_PLB_rdPendPri : in std_logic_vector(0 to 1);
SPLB_CTRL_PLB_reqPri : in std_logic_vector(0 to 1);
SPLB_CTRL_PLB_TAttribute : in std_logic_vector(0 to 15);
SPLB_CTRL_Sl_wrBTerm : out std_logic;
SPLB_CTRL_Sl_rdWdAddr : out std_logic_vector(0 to 3);
SPLB_CTRL_Sl_rdBTerm : out std_logic;
SPLB_CTRL_Sl_MIRQ : out std_logic_vector(0 to (C_SPLB_CTRL_NUM_MASTERS-1));
S_AXI_CTRL_ACLK : in std_logic;
S_AXI_CTRL_ARESETN : in std_logic;
S_AXI_CTRL_AWADDR : in std_logic_vector((C_S_AXI_CTRL_ADDR_WIDTH-1) downto 0);
S_AXI_CTRL_AWVALID : in std_logic;
S_AXI_CTRL_AWREADY : out std_logic;
S_AXI_CTRL_WDATA : in std_logic_vector((C_S_AXI_CTRL_DATA_WIDTH-1) downto 0);
S_AXI_CTRL_WSTRB : in std_logic_vector(((C_S_AXI_CTRL_DATA_WIDTH/8)-1) downto 0);
S_AXI_CTRL_WVALID : in std_logic;
S_AXI_CTRL_WREADY : out std_logic;
S_AXI_CTRL_BRESP : out std_logic_vector(1 downto 0);
S_AXI_CTRL_BVALID : out std_logic;
S_AXI_CTRL_BREADY : in std_logic;
S_AXI_CTRL_ARADDR : in std_logic_vector((C_S_AXI_CTRL_ADDR_WIDTH-1) downto 0);
S_AXI_CTRL_ARVALID : in std_logic;
S_AXI_CTRL_ARREADY : out std_logic;
S_AXI_CTRL_RDATA : out std_logic_vector((C_S_AXI_CTRL_DATA_WIDTH-1) downto 0);
S_AXI_CTRL_RRESP : out std_logic_vector(1 downto 0);
S_AXI_CTRL_RVALID : out std_logic;
S_AXI_CTRL_RREADY : in std_logic
);
end component;
begin
ilmb_cntlr : lmb_bram_if_cntlr
generic map (
C_BASEADDR => X"00000000",
C_HIGHADDR => X"00000fff",
C_FAMILY => "virtex5",
C_MASK => X"80000000",
C_MASK1 => X"00800000",
C_MASK2 => X"00800000",
C_MASK3 => X"00800000",
C_LMB_AWIDTH => 32,
C_LMB_DWIDTH => 32,
C_ECC => 0,
C_INTERCONNECT => 0,
C_FAULT_INJECT => 0,
C_CE_FAILING_REGISTERS => 0,
C_UE_FAILING_REGISTERS => 0,
C_ECC_STATUS_REGISTERS => 0,
C_ECC_ONOFF_REGISTER => 0,
C_ECC_ONOFF_RESET_VALUE => 1,
C_CE_COUNTER_WIDTH => 0,
C_WRITE_ACCESS => 2,
C_NUM_LMB => 1,
C_SPLB_CTRL_BASEADDR => X"FFFFFFFF",
C_SPLB_CTRL_HIGHADDR => X"00000000",
C_SPLB_CTRL_AWIDTH => 32,
C_SPLB_CTRL_DWIDTH => 32,
C_SPLB_CTRL_P2P => 0,
C_SPLB_CTRL_MID_WIDTH => 1,
C_SPLB_CTRL_NUM_MASTERS => 1,
C_SPLB_CTRL_SUPPORT_BURSTS => 0,
C_SPLB_CTRL_NATIVE_DWIDTH => 32,
C_S_AXI_CTRL_BASEADDR => X"FFFFFFFF",
C_S_AXI_CTRL_HIGHADDR => X"00000000",
C_S_AXI_CTRL_ADDR_WIDTH => 32,
C_S_AXI_CTRL_DATA_WIDTH => 32
)
port map (
LMB_Clk => LMB_Clk,
LMB_Rst => LMB_Rst,
LMB_ABus => LMB_ABus,
LMB_WriteDBus => LMB_WriteDBus,
LMB_AddrStrobe => LMB_AddrStrobe,
LMB_ReadStrobe => LMB_ReadStrobe,
LMB_WriteStrobe => LMB_WriteStrobe,
LMB_BE => LMB_BE,
Sl_DBus => Sl_DBus,
Sl_Ready => Sl_Ready,
Sl_Wait => Sl_Wait,
Sl_UE => Sl_UE,
Sl_CE => Sl_CE,
LMB1_ABus => LMB1_ABus,
LMB1_WriteDBus => LMB1_WriteDBus,
LMB1_AddrStrobe => LMB1_AddrStrobe,
LMB1_ReadStrobe => LMB1_ReadStrobe,
LMB1_WriteStrobe => LMB1_WriteStrobe,
LMB1_BE => LMB1_BE,
Sl1_DBus => Sl1_DBus,
Sl1_Ready => Sl1_Ready,
Sl1_Wait => Sl1_Wait,
Sl1_UE => Sl1_UE,
Sl1_CE => Sl1_CE,
LMB2_ABus => LMB2_ABus,
LMB2_WriteDBus => LMB2_WriteDBus,
LMB2_AddrStrobe => LMB2_AddrStrobe,
LMB2_ReadStrobe => LMB2_ReadStrobe,
LMB2_WriteStrobe => LMB2_WriteStrobe,
LMB2_BE => LMB2_BE,
Sl2_DBus => Sl2_DBus,
Sl2_Ready => Sl2_Ready,
Sl2_Wait => Sl2_Wait,
Sl2_UE => Sl2_UE,
Sl2_CE => Sl2_CE,
LMB3_ABus => LMB3_ABus,
LMB3_WriteDBus => LMB3_WriteDBus,
LMB3_AddrStrobe => LMB3_AddrStrobe,
LMB3_ReadStrobe => LMB3_ReadStrobe,
LMB3_WriteStrobe => LMB3_WriteStrobe,
LMB3_BE => LMB3_BE,
Sl3_DBus => Sl3_DBus,
Sl3_Ready => Sl3_Ready,
Sl3_Wait => Sl3_Wait,
Sl3_UE => Sl3_UE,
Sl3_CE => Sl3_CE,
BRAM_Rst_A => BRAM_Rst_A,
BRAM_Clk_A => BRAM_Clk_A,
BRAM_EN_A => BRAM_EN_A,
BRAM_WEN_A => BRAM_WEN_A,
BRAM_Addr_A => BRAM_Addr_A,
BRAM_Din_A => BRAM_Din_A,
BRAM_Dout_A => BRAM_Dout_A,
Interrupt => Interrupt,
UE => UE,
CE => CE,
SPLB_CTRL_PLB_ABus => SPLB_CTRL_PLB_ABus,
SPLB_CTRL_PLB_PAValid => SPLB_CTRL_PLB_PAValid,
SPLB_CTRL_PLB_masterID => SPLB_CTRL_PLB_masterID,
SPLB_CTRL_PLB_RNW => SPLB_CTRL_PLB_RNW,
SPLB_CTRL_PLB_BE => SPLB_CTRL_PLB_BE,
SPLB_CTRL_PLB_size => SPLB_CTRL_PLB_size,
SPLB_CTRL_PLB_type => SPLB_CTRL_PLB_type,
SPLB_CTRL_PLB_wrDBus => SPLB_CTRL_PLB_wrDBus,
SPLB_CTRL_Sl_addrAck => SPLB_CTRL_Sl_addrAck,
SPLB_CTRL_Sl_SSize => SPLB_CTRL_Sl_SSize,
SPLB_CTRL_Sl_wait => SPLB_CTRL_Sl_wait,
SPLB_CTRL_Sl_rearbitrate => SPLB_CTRL_Sl_rearbitrate,
SPLB_CTRL_Sl_wrDAck => SPLB_CTRL_Sl_wrDAck,
SPLB_CTRL_Sl_wrComp => SPLB_CTRL_Sl_wrComp,
SPLB_CTRL_Sl_rdDBus => SPLB_CTRL_Sl_rdDBus,
SPLB_CTRL_Sl_rdDAck => SPLB_CTRL_Sl_rdDAck,
SPLB_CTRL_Sl_rdComp => SPLB_CTRL_Sl_rdComp,
SPLB_CTRL_Sl_MBusy => SPLB_CTRL_Sl_MBusy,
SPLB_CTRL_Sl_MWrErr => SPLB_CTRL_Sl_MWrErr,
SPLB_CTRL_Sl_MRdErr => SPLB_CTRL_Sl_MRdErr,
SPLB_CTRL_PLB_UABus => SPLB_CTRL_PLB_UABus,
SPLB_CTRL_PLB_SAValid => SPLB_CTRL_PLB_SAValid,
SPLB_CTRL_PLB_rdPrim => SPLB_CTRL_PLB_rdPrim,
SPLB_CTRL_PLB_wrPrim => SPLB_CTRL_PLB_wrPrim,
SPLB_CTRL_PLB_abort => SPLB_CTRL_PLB_abort,
SPLB_CTRL_PLB_busLock => SPLB_CTRL_PLB_busLock,
SPLB_CTRL_PLB_MSize => SPLB_CTRL_PLB_MSize,
SPLB_CTRL_PLB_lockErr => SPLB_CTRL_PLB_lockErr,
SPLB_CTRL_PLB_wrBurst => SPLB_CTRL_PLB_wrBurst,
SPLB_CTRL_PLB_rdBurst => SPLB_CTRL_PLB_rdBurst,
SPLB_CTRL_PLB_wrPendReq => SPLB_CTRL_PLB_wrPendReq,
SPLB_CTRL_PLB_rdPendReq => SPLB_CTRL_PLB_rdPendReq,
SPLB_CTRL_PLB_wrPendPri => SPLB_CTRL_PLB_wrPendPri,
SPLB_CTRL_PLB_rdPendPri => SPLB_CTRL_PLB_rdPendPri,
SPLB_CTRL_PLB_reqPri => SPLB_CTRL_PLB_reqPri,
SPLB_CTRL_PLB_TAttribute => SPLB_CTRL_PLB_TAttribute,
SPLB_CTRL_Sl_wrBTerm => SPLB_CTRL_Sl_wrBTerm,
SPLB_CTRL_Sl_rdWdAddr => SPLB_CTRL_Sl_rdWdAddr,
SPLB_CTRL_Sl_rdBTerm => SPLB_CTRL_Sl_rdBTerm,
SPLB_CTRL_Sl_MIRQ => SPLB_CTRL_Sl_MIRQ,
S_AXI_CTRL_ACLK => S_AXI_CTRL_ACLK,
S_AXI_CTRL_ARESETN => S_AXI_CTRL_ARESETN,
S_AXI_CTRL_AWADDR => S_AXI_CTRL_AWADDR,
S_AXI_CTRL_AWVALID => S_AXI_CTRL_AWVALID,
S_AXI_CTRL_AWREADY => S_AXI_CTRL_AWREADY,
S_AXI_CTRL_WDATA => S_AXI_CTRL_WDATA,
S_AXI_CTRL_WSTRB => S_AXI_CTRL_WSTRB,
S_AXI_CTRL_WVALID => S_AXI_CTRL_WVALID,
S_AXI_CTRL_WREADY => S_AXI_CTRL_WREADY,
S_AXI_CTRL_BRESP => S_AXI_CTRL_BRESP,
S_AXI_CTRL_BVALID => S_AXI_CTRL_BVALID,
S_AXI_CTRL_BREADY => S_AXI_CTRL_BREADY,
S_AXI_CTRL_ARADDR => S_AXI_CTRL_ARADDR,
S_AXI_CTRL_ARVALID => S_AXI_CTRL_ARVALID,
S_AXI_CTRL_ARREADY => S_AXI_CTRL_ARREADY,
S_AXI_CTRL_RDATA => S_AXI_CTRL_RDATA,
S_AXI_CTRL_RRESP => S_AXI_CTRL_RRESP,
S_AXI_CTRL_RVALID => S_AXI_CTRL_RVALID,
S_AXI_CTRL_RREADY => S_AXI_CTRL_RREADY
);
end architecture STRUCTURE;
| lgpl-3.0 | c962a6ea0d5acdcb60399d067f3f7164 | 0.615078 | 2.93296 | false | false | false | false |
grwlf/vsim | vhdl_ct/ct00586.vhd | 1 | 27,065 | -- NEED RESULT: ARCH00586: Attribute declarations - composite dynamic subtypes with dynamic initial values passed
-------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
-------------------------------------------------------------------------------
--
-- TEST NAME:
--
-- CT00586
--
-- AUTHOR:
--
-- A. Wilmot
--
-- TEST OBJECTIVES:
--
-- 4.4 (1)
-- 4.4 (8)
--
-- DESIGN UNIT ORDERING:
--
-- E00000(ARCH00586)
-- ENT00586_Test_Bench(ARCH00586_Test_Bench)
--
-- REVISION HISTORY:
--
-- 19-AUG-1987 - initial revision
--
-- NOTES:
--
-- self-checking
-- automatically generated
--
use WORK.STANDARD_TYPES.test_report ;
--
architecture ARCH00586 of E00000 is
procedure p2 (
constant lowb : integer := 1 ;
constant highb : integer := 10 ;
constant lowb_i2 : integer := 0 ;
constant highb_i2 : integer := 1000 ;
constant lowb_p : integer := -100 ;
constant highb_p : integer := 1000 ;
constant lowb_r : real := 0.0 ;
constant highb_r : real := 1000.0 ;
constant lowb_r2 : real := 8.0 ;
constant highb_r2 : real := 80.0
--
) is
--
-- assertion: c_xxxxx_2 >= c_xxxxx_1
-- enumeration types
-- predefined
-- boolean
constant c_boolean_1 : boolean := false ;
constant c_boolean_2 : boolean := true ;
--
type boolean_vector is array (integer range <>) of boolean ;
subtype boolean_vector_range1 is integer range lowb to highb ;
subtype st_boolean_vector is boolean_vector (boolean_vector_range1) ;
constant c_st_boolean_vector_1 : st_boolean_vector :=
(others => c_boolean_1) ;
constant c_st_boolean_vector_2 : st_boolean_vector :=
(others => c_boolean_2) ;
--
-- bit
constant c_bit_1 : bit := '0' ;
constant c_bit_2 : bit := '1' ;
--
constant c_bit_vector_1 : bit_vector := B"0000" ;
constant c_bit_vector_2 : bit_vector := B"1111" ;
subtype bit_vector_range1 is integer range lowb to highb ;
subtype st_bit_vector is bit_vector (bit_vector_range1) ;
constant c_st_bit_vector_1 : st_bit_vector :=
(others => c_bit_1) ;
constant c_st_bit_vector_2 : st_bit_vector :=
(others => c_bit_2) ;
-- severity_level
constant c_severity_level_1 : severity_level := NOTE ;
constant c_severity_level_2 : severity_level := WARNING ;
--
type severity_level_vector is array (integer range <>) of severity_level ;
subtype severity_level_vector_range1 is integer range lowb to highb ;
subtype st_severity_level_vector is
severity_level_vector (severity_level_vector_range1) ;
constant c_st_severity_level_vector_1 : st_severity_level_vector :=
(others => c_severity_level_1) ;
constant c_st_severity_level_vector_2 : st_severity_level_vector :=
(others => c_severity_level_2) ;
--
-- character
constant c_character_1 : character := 'A' ;
constant c_character_2 : character := 'a' ;
--
constant c_string_1 : string := "ABC0000" ;
constant c_string_2 : string := "ABC1111" ;
subtype string_range1 is integer range lowb to highb ;
subtype st_string is string (string_range1) ;
constant c_st_string_1 : st_string :=
(others => c_character_1) ;
constant c_st_string_2 : st_string :=
(others => c_character_2) ;
-- user defined enumeration
type t_enum1 is (en1, en2, en3, en4) ;
constant c_t_enum1_1 : t_enum1 := en1 ;
constant c_t_enum1_2 : t_enum1 := en2 ;
subtype st_enum1 is t_enum1 range en4 downto en1 ;
constant c_st_enum1_1 : st_enum1 := en1 ;
constant c_st_enum1_2 : st_enum1 := en2 ;
--
type enum1_vector is array (integer range <>) of st_enum1 ;
subtype enum1_vector_range1 is integer range lowb to highb ;
subtype st_enum1_vector is enum1_vector (enum1_vector_range1) ;
constant c_st_enum1_vector_1 : st_enum1_vector :=
(others => c_st_enum1_1) ;
constant c_st_enum1_vector_2 : st_enum1_vector :=
(others => c_st_enum1_2) ;
-- integer types
-- predefined
constant c_integer_1 : integer := lowb ;
constant c_integer_2 : integer := highb ;
--
type integer_vector is array (integer range <>) of integer ;
subtype integer_vector_range1 is integer range lowb to highb ;
subtype st_integer_vector is integer_vector (integer_vector_range1) ;
constant c_st_integer_vector_1 : st_integer_vector :=
(others => c_integer_1) ;
constant c_st_integer_vector_2 : st_integer_vector :=
(others => c_integer_2) ;
--
-- user defined integer type
type t_int1 is range 0 to 100 ;
constant c_t_int1_1 : t_int1 := 0 ;
constant c_t_int1_2 : t_int1 := 10 ;
subtype st_int1 is t_int1 range 8 to 60 ;
constant c_st_int1_1 : st_int1 := 8 ;
constant c_st_int1_2 : st_int1 := 9 ;
--
type int1_vector is array (integer range <>) of st_int1 ;
subtype int1_vector_range1 is integer range lowb to highb ;
subtype st_int1_vector is int1_vector (int1_vector_range1) ;
constant c_st_int1_vector_1 : st_int1_vector :=
(others => c_st_int1_1) ;
constant c_st_int1_vector_2 : st_int1_vector :=
(others => c_st_int1_2) ;
--
-- physical types
-- predefined
constant c_time_1 : time := 1 ns ;
constant c_time_2 : time := 2 ns ;
--
type time_vector is array (integer range <>) of time ;
subtype time_vector_range1 is integer range lowb to highb ;
subtype st_time_vector is time_vector (time_vector_range1) ;
constant c_st_time_vector_1 : st_time_vector :=
(others => c_time_1) ;
constant c_st_time_vector_2 : st_time_vector :=
(others => c_time_2) ;
--
-- user defined physical type
type t_phys1 is range -100 to 1000
units
phys1_1 ;
phys1_2 = 10 phys1_1 ;
phys1_3 = 10 phys1_2 ;
phys1_4 = 10 phys1_3 ;
phys1_5 = 10 phys1_4 ;
end units ;
--
constant c_t_phys1_1 : t_phys1 := phys1_1 ;
constant c_t_phys1_2 : t_phys1 := phys1_2 ;
subtype st_phys1 is t_phys1 range phys1_2 to phys1_4 ;
constant c_st_phys1_1 : st_phys1 := phys1_2 ;
constant c_st_phys1_2 : st_phys1 := phys1_3 ;
--
type phys1_vector is array (integer range <>) of st_phys1 ;
subtype phys1_vector_range1 is integer range lowb to highb ;
subtype st_phys1_vector is phys1_vector (phys1_vector_range1) ;
constant c_st_phys1_vector_1 : st_phys1_vector :=
(others => c_st_phys1_1) ;
constant c_st_phys1_vector_2 : st_phys1_vector :=
(others => c_st_phys1_2) ;
--
--
-- floating point types
-- predefined
constant c_real_1 : real := 0.0 ;
constant c_real_2 : real := 1.0 ;
--
type real_vector is array (integer range <>) of real ;
subtype real_vector_range1 is integer range lowb to highb ;
subtype st_real_vector is real_vector (real_vector_range1) ;
constant c_st_real_vector_1 : st_real_vector :=
(others => c_real_1) ;
constant c_st_real_vector_2 : st_real_vector :=
(others => c_real_2) ;
--
-- user defined floating type
type t_real1 is range 0.0 to 1000.0 ;
constant c_t_real1_1 : t_real1 := 0.0 ;
constant c_t_real1_2 : t_real1 := 1.0 ;
subtype st_real1 is t_real1 range 8.0 to 80.0 ;
constant c_st_real1_1 : st_real1 := 8.0 ;
constant c_st_real1_2 : st_real1 := 9.0 ;
--
type real1_vector is array (integer range <>) of st_real1 ;
subtype real1_vector_range1 is integer range lowb to highb ;
subtype st_real1_vector is real1_vector (real1_vector_range1) ;
constant c_st_real1_vector_1 : st_real1_vector :=
(others => c_st_real1_1) ;
constant c_st_real1_vector_2 : st_real1_vector :=
(others => c_st_real1_2) ;
-- composite types
--
-- simple record
type t_rec1 is record
f1 : integer range lowb_i2 to highb_i2 ;
f2 : time ;
f3 : boolean ;
f4 : real ;
end record ;
constant c_t_rec1_1 : t_rec1 :=
(c_integer_1, c_time_1, c_boolean_1, c_real_1) ;
constant c_t_rec1_2 : t_rec1 :=
(c_integer_2, c_time_2, c_boolean_2, c_real_2) ;
subtype st_rec1 is t_rec1 ;
constant c_st_rec1_1 : st_rec1 := c_t_rec1_1 ;
constant c_st_rec1_2 : st_rec1 := c_t_rec1_2 ;
--
type rec1_vector is array (integer range <>) of st_rec1 ;
subtype rec1_vector_range1 is integer range lowb to highb ;
subtype st_rec1_vector is rec1_vector (rec1_vector_range1) ;
constant c_st_rec1_vector_1 : st_rec1_vector :=
(others => c_st_rec1_1) ;
constant c_st_rec1_vector_2 : st_rec1_vector :=
(others => c_st_rec1_2) ;
--
--
-- more complex record
type t_rec2 is record
f1 : boolean ;
f2 : st_rec1 ;
f3 : time ;
end record ;
constant c_t_rec2_1 : t_rec2 :=
(c_boolean_1, c_st_rec1_1, c_time_1) ;
constant c_t_rec2_2 : t_rec2 :=
(c_boolean_2, c_st_rec1_2, c_time_2) ;
subtype st_rec2 is t_rec2 ;
constant c_st_rec2_1 : st_rec2 := c_t_rec2_1 ;
constant c_st_rec2_2 : st_rec2 := c_t_rec2_2 ;
--
type rec2_vector is array (integer range <>) of st_rec2 ;
subtype rec2_vector_range1 is integer range lowb to highb ;
subtype st_rec2_vector is rec2_vector (rec2_vector_range1) ;
constant c_st_rec2_vector_1 : st_rec2_vector :=
(others => c_st_rec2_1) ;
constant c_st_rec2_vector_2 : st_rec2_vector :=
(others => c_st_rec2_2) ;
--
-- simple array
type t_arr1 is array (integer range <>) of st_int1 ;
subtype t_arr1_range1 is integer range lowb to highb ;
subtype st_arr1 is t_arr1 (t_arr1_range1) ;
constant c_st_arr1_1 : st_arr1 := (others => c_st_int1_1) ;
constant c_st_arr1_2 : st_arr1 := (others => c_st_int1_2) ;
constant c_t_arr1_1 : st_arr1 := c_st_arr1_1 ;
constant c_t_arr1_2 : st_arr1 := c_st_arr1_2 ;
--
type arr1_vector is array (integer range <>) of st_arr1 ;
subtype arr1_vector_range1 is integer range lowb to highb ;
subtype st_arr1_vector is arr1_vector (arr1_vector_range1) ;
constant c_st_arr1_vector_1 : st_arr1_vector :=
(others => c_st_arr1_1) ;
constant c_st_arr1_vector_2 : st_arr1_vector :=
(others => c_st_arr1_2) ;
-- more complex array
type t_arr2 is array (integer range <>, boolean range <>) of st_arr1 ;
subtype t_arr2_range1 is integer range lowb to highb ;
subtype t_arr2_range2 is boolean range false to true ;
subtype st_arr2 is t_arr2 (t_arr2_range1, t_arr2_range2);
constant c_st_arr2_1 : st_arr2 := (others => (others => c_st_arr1_1)) ;
constant c_st_arr2_2 : st_arr2 := (others => (others => c_st_arr1_2)) ;
constant c_t_arr2_1 : st_arr2 := c_st_arr2_1 ;
constant c_t_arr2_2 : st_arr2 := c_st_arr2_2 ;
--
type arr2_vector is array (integer range <>) of st_arr2 ;
subtype arr2_vector_range1 is integer range lowb to highb ;
subtype st_arr2_vector is arr2_vector (arr2_vector_range1) ;
constant c_st_arr2_vector_1 : st_arr2_vector :=
(others => c_st_arr2_1) ;
constant c_st_arr2_vector_2 : st_arr2_vector :=
(others => c_st_arr2_2) ;
--
--
-- most complex record
type t_rec3 is record
f1 : boolean ;
f2 : st_rec2 ;
f3 : st_arr2 ;
end record ;
constant c_t_rec3_1 : t_rec3 :=
(c_boolean_1, c_st_rec2_1, c_st_arr2_1) ;
constant c_t_rec3_2 : t_rec3 :=
(c_boolean_2, c_st_rec2_2, c_st_arr2_2) ;
subtype st_rec3 is t_rec3 ;
constant c_st_rec3_1 : st_rec3 := c_t_rec3_1 ;
constant c_st_rec3_2 : st_rec3 := c_t_rec3_2 ;
--
type rec3_vector is array (integer range <>) of st_rec3 ;
subtype rec3_vector_range1 is integer range lowb to highb ;
subtype st_rec3_vector is rec3_vector (rec3_vector_range1) ;
constant c_st_rec3_vector_1 : st_rec3_vector :=
(others => c_st_rec3_1) ;
constant c_st_rec3_vector_2 : st_rec3_vector :=
(others => c_st_rec3_2) ;
--
-- most complex array
type t_arr3 is array (integer range <>, boolean range <>) of st_rec3 ;
subtype t_arr3_range1 is integer range lowb to highb ;
subtype t_arr3_range2 is boolean range true downto false ;
subtype st_arr3 is t_arr3 (t_arr3_range1, t_arr3_range2) ;
constant c_st_arr3_1 : st_arr3 := (others => (others => c_st_rec3_1)) ;
constant c_st_arr3_2 : st_arr3 := (others => (others => c_st_rec3_2)) ;
constant c_t_arr3_1 : st_arr3 := c_st_arr3_1 ;
constant c_t_arr3_2 : st_arr3 := c_st_arr3_2 ;
--
type arr3_vector is array (integer range <>) of st_arr3 ;
subtype arr3_vector_range1 is integer range lowb to highb ;
subtype st_arr3_vector is arr3_vector (arr3_vector_range1) ;
constant c_st_arr3_vector_1 : st_arr3_vector :=
(others => c_st_arr3_1) ;
constant c_st_arr3_vector_2 : st_arr3_vector :=
(others => c_st_arr3_2) ;
--
-- enumeration types
-- predefined
-- boolean
function bf_boolean(to_resolve : boolean_vector) return boolean is
variable sum : integer := 0 ;
begin
if to_resolve'length = 0 then
return boolean'left ;
else
for i in to_resolve'range loop
sum := sum + boolean'pos(to_resolve(i)) ;
end loop ;
return boolean'val(integer'pos(sum) mod
(boolean'pos(boolean'high) + 1)) ;
end if ;
end bf_boolean ;
--
--
-- bit
function bf_bit(to_resolve : bit_vector) return bit is
variable sum : integer := 0 ;
begin
if to_resolve'length = 0 then
return bit'left ;
else
for i in to_resolve'range loop
sum := sum + bit'pos(to_resolve(i)) ;
end loop ;
return bit'val(integer'pos(sum) mod
(bit'pos(bit'high) + 1)) ;
end if ;
end bf_bit ;
--
-- severity_level
function bf_severity_level(to_resolve : severity_level_vector)
return severity_level is
variable sum : integer := 0 ;
begin
if to_resolve'length = 0 then
return severity_level'left ;
else
for i in to_resolve'range loop
sum := sum + severity_level'pos(to_resolve(i)) ;
end loop ;
return severity_level'val(integer'pos(sum) mod
(severity_level'pos(severity_level'high) + 1)) ;
end if ;
end bf_severity_level ;
--
-- character
function bf_character(to_resolve : string) return character is
variable sum : integer := 0 ;
begin
if to_resolve'length = 0 then
return character'left ;
else
for i in to_resolve'range loop
sum := sum + character'pos(to_resolve(i)) ;
end loop ;
return character'val(integer'pos(sum) mod
(character'pos(character'high) + 1)) ;
end if ;
end bf_character ;
--
--
-- user defined enumeration
function bf_enum1(to_resolve : enum1_vector) return st_enum1 is
variable sum : integer := 0 ;
begin
if to_resolve'length = 0 then
return st_enum1'left ;
else
for i in to_resolve'range loop
sum := sum + t_enum1'pos(to_resolve(i)) ;
end loop ;
return t_enum1'val(integer'pos(sum) mod
(t_enum1'pos(t_enum1'high) + 1)) ;
end if ;
end bf_enum1 ;
--
--
-- integer types
-- predefined
function bf_integer(to_resolve : integer_vector) return integer is
variable sum : integer := 0 ;
begin
if to_resolve'length = 0 then
return integer'left ;
else
for i in to_resolve'range loop
sum := sum + integer'pos(to_resolve(i)) ;
end loop ;
return sum ;
end if ;
end bf_integer ;
--
--
-- user defined integer type
function bf_int1(to_resolve : int1_vector) return st_int1 is
variable sum : integer := 0 ;
begin
if to_resolve'length = 0 then
return st_int1'left ;
else
for i in to_resolve'range loop
sum := sum + t_int1'pos(to_resolve(i)) ;
end loop ;
return t_int1'val(integer'pos(sum) mod
(t_int1'pos(t_int1'high) + 1)) ;
end if ;
end bf_int1 ;
--
--
-- physical types
-- predefined
function bf_time(to_resolve : time_vector) return time is
variable sum : time := 0 fs;
begin
if to_resolve'length = 0 then
return time'left ;
else
for i in to_resolve'range loop
sum := sum + to_resolve(i) ;
end loop ;
return sum ;
end if ;
end bf_time ;
--
--
-- user defined physical type
function bf_phys1(to_resolve : phys1_vector) return st_phys1 is
variable sum : integer := 0 ;
begin
if to_resolve'length = 0 then
return c_st_phys1_1 ;
else
for i in to_resolve'range loop
sum := sum + t_phys1'pos(to_resolve(i)) ;
end loop ;
return t_phys1'val(integer'pos(sum) mod
(t_phys1'pos(t_phys1'high) + 1)) ;
end if ;
end bf_phys1 ;
--
--
-- floating point types
-- predefined
function bf_real(to_resolve : real_vector) return real is
variable sum : real := 0.0 ;
begin
if to_resolve'length = 0 then
return real'left ;
else
for i in to_resolve'range loop
sum := sum + to_resolve(i) ;
end loop ;
return sum ;
end if ;
end bf_real ;
--
--
-- user defined floating type
function bf_real1(to_resolve : real1_vector) return st_real1 is
variable sum : t_real1 := 0.0 ;
begin
if to_resolve'length = 0 then
return c_st_real1_1 ;
else
for i in to_resolve'range loop
sum := sum + to_resolve(i) ;
end loop ;
return sum ;
end if ;
end bf_real1 ;
--
--
-- composite types
--
-- simple record
function bf_rec1(to_resolve : rec1_vector) return st_rec1 is
variable f1array : integer_vector (to_resolve'range) ;
variable f2array : time_vector (to_resolve'range) ;
variable f3array : boolean_vector (to_resolve'range) ;
variable f4array : real_vector (to_resolve'range) ;
variable result : st_rec1 ;
begin
if to_resolve'length = 0 then
return c_st_rec1_1 ;
else
for i in to_resolve'range loop
f1array(i) := to_resolve(i).f1 ;
f2array(i) := to_resolve(i).f2 ;
f3array(i) := to_resolve(i).f3 ;
f4array(i) := to_resolve(i).f4 ;
end loop ;
result.f1 := bf_integer(f1array) ;
result.f2 := bf_time(f2array) ;
result.f3 := bf_boolean(f3array) ;
result.f4 := bf_real(f4array) ;
return result ;
end if ;
end bf_rec1 ;
--
--
-- more complex record
function bf_rec2(to_resolve : rec2_vector) return st_rec2 is
variable f1array : boolean_vector (to_resolve'range) ;
variable f2array : rec1_vector (to_resolve'range) ;
variable f3array : time_vector (to_resolve'range) ;
variable result : st_rec2 ;
begin
if to_resolve'length = 0 then
return c_st_rec2_1 ;
else
for i in to_resolve'range loop
f1array(i) := to_resolve(i).f1 ;
f2array(i) := to_resolve(i).f2 ;
f3array(i) := to_resolve(i).f3 ;
end loop ;
result.f1 := bf_boolean(f1array) ;
result.f2 := bf_rec1(f2array) ;
result.f3 := bf_time(f3array) ;
return result ;
end if ;
end bf_rec2 ;
--
--
-- simple array
function bf_arr1(to_resolve : arr1_vector) return st_arr1 is
variable temp : int1_vector (to_resolve'range) ;
variable result : st_arr1 ;
begin
if to_resolve'length = 0 then
return c_st_arr1_1 ;
else
for i in st_arr1'range loop
for j in to_resolve'range(1) loop
temp(j) := to_resolve(j)(i) ;
end loop;
result(i) := bf_int1(temp) ;
end loop ;
return result ;
end if ;
end bf_arr1 ;
--
--
-- more complex array
function bf_arr2(to_resolve : arr2_vector) return st_arr2 is
variable temp : arr1_vector (to_resolve'range) ;
variable result : st_arr2 ;
begin
if to_resolve'length = 0 then
return c_st_arr2_1 ;
else
for i in st_arr2'range(1) loop
for j in st_arr2'range(2) loop
for k in to_resolve'range loop
temp(k) := to_resolve(k)(i,j) ;
end loop ;
result(i, j) := bf_arr1(temp) ;
end loop ;
end loop ;
return result ;
end if ;
end bf_arr2 ;
--
--
-- most complex record
function bf_rec3(to_resolve : rec3_vector) return st_rec3 is
variable f1array : boolean_vector (to_resolve'range) ;
variable f2array : rec2_vector (to_resolve'range) ;
variable f3array : arr2_vector (to_resolve'range) ;
variable result : st_rec3 ;
begin
if to_resolve'length = 0 then
return c_st_rec3_1 ;
else
for i in to_resolve'range loop
f1array(i) := to_resolve(i).f1 ;
f2array(i) := to_resolve(i).f2 ;
f3array(i) := to_resolve(i).f3 ;
end loop ;
result.f1 := bf_boolean(f1array) ;
result.f2 := bf_rec2(f2array) ;
result.f3 := bf_arr2(f3array) ;
return result ;
end if ;
end bf_rec3 ;
--
--
-- most complex array
function bf_arr3(to_resolve : arr3_vector) return st_arr3 is
variable temp : rec3_vector (to_resolve'range) ;
variable result : st_arr3 ;
begin
if to_resolve'length = 0 then
return c_st_arr3_1 ;
else
for i in st_arr3'range(1) loop
for j in st_arr3'range(2) loop
for k in to_resolve'range loop
temp(k) := to_resolve(k)(i,j) ;
end loop ;
result(i, j) := bf_rec3(temp) ;
end loop ;
end loop ;
return result ;
end if ;
end bf_arr3 ;
--
attribute at_bit_vector_1 : bit_vector ;
attribute at_string_1 : string ;
attribute at_t_rec1_1 : t_rec1 ;
attribute at_st_rec1_1 : st_rec1 ;
attribute at_t_rec2_1 : t_rec2 ;
attribute at_st_rec2_1 : st_rec2 ;
attribute at_t_rec3_1 : t_rec3 ;
attribute at_st_rec3_1 : st_rec3 ;
attribute at_t_arr1_1 : t_arr1 ;
attribute at_st_arr1_1 : st_arr1 ;
attribute at_t_arr2_1 : t_arr2 ;
attribute at_st_arr2_1 : st_arr2 ;
attribute at_t_arr3_1 : t_arr3 ;
attribute at_st_arr3_1 : st_arr3 ;
procedure p1 ;
attribute at_bit_vector_1 of p1 : procedure is
c_st_bit_vector_1 ;
attribute at_string_1 of p1 : procedure is
c_st_string_1 ;
attribute at_t_rec1_1 of p1 : procedure is
c_st_rec1_1 ;
attribute at_st_rec1_1 of p1 : procedure is
c_st_rec1_1 ;
attribute at_t_rec2_1 of p1 : procedure is
c_st_rec2_1 ;
attribute at_st_rec2_1 of p1 : procedure is
c_st_rec2_1 ;
attribute at_t_rec3_1 of p1 : procedure is
c_st_rec3_1 ;
attribute at_st_rec3_1 of p1 : procedure is
c_st_rec3_1 ;
attribute at_t_arr1_1 of p1 : procedure is
c_st_arr1_1 ;
attribute at_st_arr1_1 of p1 : procedure is
c_st_arr1_1 ;
attribute at_t_arr2_1 of p1 : procedure is
c_st_arr2_1 ;
attribute at_st_arr2_1 of p1 : procedure is
c_st_arr2_1 ;
attribute at_t_arr3_1 of p1 : procedure is
c_st_arr3_1 ;
attribute at_st_arr3_1 of p1 : procedure is
c_st_arr3_1 ;
procedure p1 is
variable correct : boolean := true ;
begin
correct := correct and p1'at_bit_vector_1
= c_st_bit_vector_1 ;
correct := correct and p1'at_string_1
= c_st_string_1 ;
correct := correct and p1'at_t_rec1_1
= c_st_rec1_1 ;
correct := correct and p1'at_st_rec1_1
= c_st_rec1_1 ;
correct := correct and p1'at_t_rec2_1
= c_st_rec2_1 ;
correct := correct and p1'at_st_rec2_1
= c_st_rec2_1 ;
correct := correct and p1'at_t_rec3_1
= c_st_rec3_1 ;
correct := correct and p1'at_st_rec3_1
= c_st_rec3_1 ;
correct := correct and p1'at_t_arr1_1
= c_st_arr1_1 ;
correct := correct and p1'at_st_arr1_1
= c_st_arr1_1 ;
correct := correct and p1'at_t_arr2_1
= c_st_arr2_1 ;
correct := correct and p1'at_st_arr2_1
= c_st_arr2_1 ;
correct := correct and p1'at_t_arr3_1
= c_st_arr3_1 ;
correct := correct and p1'at_st_arr3_1
= c_st_arr3_1 ;
test_report ( "ARCH00586" ,
"Attribute declarations - composite dynamic subtypes"
& " with dynamic initial values" ,
correct) ;
end p1 ;
begin
p1 ;
end p2 ;
begin
process
begin
p2 ;
wait ;
end process ;
end ARCH00586 ;
--
entity ENT00586_Test_Bench is
end ENT00586_Test_Bench ;
--
architecture ARCH00586_Test_Bench of ENT00586_Test_Bench is
begin
L1:
block
component UUT
end component ;
for CIS1 : UUT use entity WORK.E00000 ( ARCH00586 ) ;
begin
CIS1 : UUT ;
end block L1 ;
end ARCH00586_Test_Bench ;
| gpl-3.0 | c00f403cf2bfe515cebeb9ed6c1b389e | 0.539701 | 3.235118 | false | false | false | false |
MilosSubotic/huffman_coding | RTL/src/rtl/huffman_encoder.vhd | 1 | 2,279 | ------------------------------------------------------------------------------
-- @license MIT
-- @brief Huffman encoder 8-bit symbols, max 16 symbols in group.
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.global.all;
use work.text2sym_conv_and_stage_freq;
use work.histogram;
use work.sort_syms_by_freq;
entity huffman_encoder is
port(
-- Clock.
aclk : in std_logic;
-- Reset.
axi_resetn : in std_logic;
-- Input port.
s_axis_tdata : in std_logic_vector(7 downto 0);
s_axis_tvalid : in std_logic;
s_axis_tready : out std_logic;
s_axis_tlast : in std_logic;
-- Output port.
m_axis_tdata : out std_logic_vector(7 downto 0);
m_axis_tvalid : out std_logic;
m_axis_tready : in std_logic;
m_axis_tlast : out std_logic
);
end entity huffman_encoder;
architecture arch_huffman_encoder of huffman_encoder is
signal clk : std_logic;
signal n_rst : std_logic;
signal stage : t_stage;
signal pipe_en : std_logic;
signal pipe_flush : std_logic;
signal sym : t_sym;
signal hist : t_freq_array(0 to 15);
signal sorted_by_freq : t_sym_and_freq_array(0 to 15);
begin
clk <= aclk;
n_rst <= axi_resetn;
text2sym_conv_and_stage_freq_i: entity text2sym_conv_and_stage_freq
port map(
i_clk => clk,
in_rst => n_rst,
s_axis_tdata => s_axis_tdata,
s_axis_tvalid => s_axis_tvalid,
s_axis_tready => s_axis_tready,
s_axis_tlast => s_axis_tlast,
o_stage => stage,
o_pipe_en => pipe_en,
o_pipe_flush => pipe_flush,
o_sym => sym
);
histogram_i: entity histogram
port map(
i_clk => clk,
in_rst => n_rst,
i_stage => stage,
i_pipe_en => pipe_en,
i_sym => sym,
o_hist => hist
);
sort_syms_by_freq_i : entity sort_syms_by_freq
port map (
i_clk => clk,
in_rst => n_rst,
i_stage => stage,
i_pipe_en => pipe_en,
i_hist => hist,
o_sorted_by_freq => sorted_by_freq
);
end architecture arch_huffman_encoder;
| mit | 82e660862d32e1e25800e4230b41c4fe | 0.516455 | 2.998684 | false | false | false | false |
jairov4/accel-oil | solution_virtex5_plb/impl/vhdl/nfa_accept_samples_generic_hw.vhd | 1 | 79,362 | -- ==============================================================
-- RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2014.1
-- Copyright (C) 2014 Xilinx Inc. All rights reserved.
--
-- ===========================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity nfa_accept_samples_generic_hw is
port (
ap_clk : IN STD_LOGIC;
ap_rst : IN STD_LOGIC;
ap_start : IN STD_LOGIC;
ap_done : OUT STD_LOGIC;
ap_idle : OUT STD_LOGIC;
ap_ready : OUT STD_LOGIC;
nfa_initials_buckets_req_din : OUT STD_LOGIC;
nfa_initials_buckets_req_full_n : IN STD_LOGIC;
nfa_initials_buckets_req_write : OUT STD_LOGIC;
nfa_initials_buckets_rsp_empty_n : IN STD_LOGIC;
nfa_initials_buckets_rsp_read : OUT STD_LOGIC;
nfa_initials_buckets_address : OUT STD_LOGIC_VECTOR (31 downto 0);
nfa_initials_buckets_datain : IN STD_LOGIC_VECTOR (31 downto 0);
nfa_initials_buckets_dataout : OUT STD_LOGIC_VECTOR (31 downto 0);
nfa_initials_buckets_size : OUT STD_LOGIC_VECTOR (31 downto 0);
nfa_finals_buckets_req_din : OUT STD_LOGIC;
nfa_finals_buckets_req_full_n : IN STD_LOGIC;
nfa_finals_buckets_req_write : OUT STD_LOGIC;
nfa_finals_buckets_rsp_empty_n : IN STD_LOGIC;
nfa_finals_buckets_rsp_read : OUT STD_LOGIC;
nfa_finals_buckets_address : OUT STD_LOGIC_VECTOR (31 downto 0);
nfa_finals_buckets_datain : IN STD_LOGIC_VECTOR (31 downto 0);
nfa_finals_buckets_dataout : OUT STD_LOGIC_VECTOR (31 downto 0);
nfa_finals_buckets_size : OUT STD_LOGIC_VECTOR (31 downto 0);
nfa_forward_buckets_req_din : OUT STD_LOGIC;
nfa_forward_buckets_req_full_n : IN STD_LOGIC;
nfa_forward_buckets_req_write : OUT STD_LOGIC;
nfa_forward_buckets_rsp_empty_n : IN STD_LOGIC;
nfa_forward_buckets_rsp_read : OUT STD_LOGIC;
nfa_forward_buckets_address : OUT STD_LOGIC_VECTOR (31 downto 0);
nfa_forward_buckets_datain : IN STD_LOGIC_VECTOR (31 downto 0);
nfa_forward_buckets_dataout : OUT STD_LOGIC_VECTOR (31 downto 0);
nfa_forward_buckets_size : OUT STD_LOGIC_VECTOR (31 downto 0);
nfa_symbols : IN STD_LOGIC_VECTOR (7 downto 0);
sample_buffer_req_din : OUT STD_LOGIC;
sample_buffer_req_full_n : IN STD_LOGIC;
sample_buffer_req_write : OUT STD_LOGIC;
sample_buffer_rsp_empty_n : IN STD_LOGIC;
sample_buffer_rsp_read : OUT STD_LOGIC;
sample_buffer_address : OUT STD_LOGIC_VECTOR (31 downto 0);
sample_buffer_datain : IN STD_LOGIC_VECTOR (7 downto 0);
sample_buffer_dataout : OUT STD_LOGIC_VECTOR (7 downto 0);
sample_buffer_size : OUT STD_LOGIC_VECTOR (31 downto 0);
sample_buffer_length : IN STD_LOGIC_VECTOR (31 downto 0);
sample_length : IN STD_LOGIC_VECTOR (15 downto 0);
indices_req_din : OUT STD_LOGIC;
indices_req_full_n : IN STD_LOGIC;
indices_req_write : OUT STD_LOGIC;
indices_rsp_empty_n : IN STD_LOGIC;
indices_rsp_read : OUT STD_LOGIC;
indices_address : OUT STD_LOGIC_VECTOR (31 downto 0);
indices_datain : IN STD_LOGIC_VECTOR (55 downto 0);
indices_dataout : OUT STD_LOGIC_VECTOR (55 downto 0);
indices_size : OUT STD_LOGIC_VECTOR (31 downto 0);
i_size : IN STD_LOGIC_VECTOR (15 downto 0);
begin_index : IN STD_LOGIC_VECTOR (15 downto 0);
begin_sample : IN STD_LOGIC_VECTOR (15 downto 0);
end_index : IN STD_LOGIC_VECTOR (15 downto 0);
end_sample : IN STD_LOGIC_VECTOR (15 downto 0);
stop_on_first : IN STD_LOGIC_VECTOR (0 downto 0);
accept : IN STD_LOGIC_VECTOR (0 downto 0);
ap_return : OUT STD_LOGIC_VECTOR (31 downto 0) );
end;
architecture behav of nfa_accept_samples_generic_hw is
attribute CORE_GENERATION_INFO : STRING;
attribute CORE_GENERATION_INFO of behav : architecture is
"nfa_accept_samples_generic_hw,hls_ip_2014_1,{HLS_INPUT_TYPE=c,HLS_INPUT_FLOAT=0,HLS_INPUT_FIXED=0,HLS_INPUT_PART=xc5vlx50tff1136-3,HLS_INPUT_CLOCK=7.000000,HLS_INPUT_ARCH=others,HLS_SYN_CLOCK=5.200000,HLS_SYN_LAT=53290010,HLS_SYN_TPT=none,HLS_SYN_MEM=0,HLS_SYN_DSP=0,HLS_SYN_FF=0,HLS_SYN_LUT=0}";
constant ap_const_logic_1 : STD_LOGIC := '1';
constant ap_const_logic_0 : STD_LOGIC := '0';
constant ap_ST_st1_fsm_0 : STD_LOGIC_VECTOR (5 downto 0) := "000000";
constant ap_ST_st2_fsm_1 : STD_LOGIC_VECTOR (5 downto 0) := "000001";
constant ap_ST_st3_fsm_2 : STD_LOGIC_VECTOR (5 downto 0) := "000010";
constant ap_ST_st4_fsm_3 : STD_LOGIC_VECTOR (5 downto 0) := "000011";
constant ap_ST_st5_fsm_4 : STD_LOGIC_VECTOR (5 downto 0) := "000100";
constant ap_ST_st6_fsm_5 : STD_LOGIC_VECTOR (5 downto 0) := "000101";
constant ap_ST_st7_fsm_6 : STD_LOGIC_VECTOR (5 downto 0) := "000110";
constant ap_ST_st8_fsm_7 : STD_LOGIC_VECTOR (5 downto 0) := "000111";
constant ap_ST_st9_fsm_8 : STD_LOGIC_VECTOR (5 downto 0) := "001000";
constant ap_ST_st10_fsm_9 : STD_LOGIC_VECTOR (5 downto 0) := "001001";
constant ap_ST_st11_fsm_10 : STD_LOGIC_VECTOR (5 downto 0) := "001010";
constant ap_ST_st12_fsm_11 : STD_LOGIC_VECTOR (5 downto 0) := "001011";
constant ap_ST_st13_fsm_12 : STD_LOGIC_VECTOR (5 downto 0) := "001100";
constant ap_ST_st14_fsm_13 : STD_LOGIC_VECTOR (5 downto 0) := "001101";
constant ap_ST_st15_fsm_14 : STD_LOGIC_VECTOR (5 downto 0) := "001110";
constant ap_ST_st16_fsm_15 : STD_LOGIC_VECTOR (5 downto 0) := "001111";
constant ap_ST_st17_fsm_16 : STD_LOGIC_VECTOR (5 downto 0) := "010000";
constant ap_ST_st18_fsm_17 : STD_LOGIC_VECTOR (5 downto 0) := "010001";
constant ap_ST_st19_fsm_18 : STD_LOGIC_VECTOR (5 downto 0) := "010010";
constant ap_ST_st20_fsm_19 : STD_LOGIC_VECTOR (5 downto 0) := "010011";
constant ap_ST_st21_fsm_20 : STD_LOGIC_VECTOR (5 downto 0) := "010100";
constant ap_ST_st22_fsm_21 : STD_LOGIC_VECTOR (5 downto 0) := "010101";
constant ap_ST_st23_fsm_22 : STD_LOGIC_VECTOR (5 downto 0) := "010110";
constant ap_ST_st24_fsm_23 : STD_LOGIC_VECTOR (5 downto 0) := "010111";
constant ap_ST_st25_fsm_24 : STD_LOGIC_VECTOR (5 downto 0) := "011000";
constant ap_ST_st26_fsm_25 : STD_LOGIC_VECTOR (5 downto 0) := "011001";
constant ap_ST_st27_fsm_26 : STD_LOGIC_VECTOR (5 downto 0) := "011010";
constant ap_ST_st28_fsm_27 : STD_LOGIC_VECTOR (5 downto 0) := "011011";
constant ap_ST_st29_fsm_28 : STD_LOGIC_VECTOR (5 downto 0) := "011100";
constant ap_ST_st30_fsm_29 : STD_LOGIC_VECTOR (5 downto 0) := "011101";
constant ap_ST_st31_fsm_30 : STD_LOGIC_VECTOR (5 downto 0) := "011110";
constant ap_ST_st32_fsm_31 : STD_LOGIC_VECTOR (5 downto 0) := "011111";
constant ap_ST_st33_fsm_32 : STD_LOGIC_VECTOR (5 downto 0) := "100000";
constant ap_ST_st34_fsm_33 : STD_LOGIC_VECTOR (5 downto 0) := "100001";
constant ap_ST_st35_fsm_34 : STD_LOGIC_VECTOR (5 downto 0) := "100010";
constant ap_ST_st36_fsm_35 : STD_LOGIC_VECTOR (5 downto 0) := "100011";
constant ap_ST_st37_fsm_36 : STD_LOGIC_VECTOR (5 downto 0) := "100100";
constant ap_const_lv1_0 : STD_LOGIC_VECTOR (0 downto 0) := "0";
constant ap_const_lv16_0 : STD_LOGIC_VECTOR (15 downto 0) := "0000000000000000";
constant ap_const_lv64_0 : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000";
constant ap_const_lv1_1 : STD_LOGIC_VECTOR (0 downto 0) := "1";
constant ap_const_lv32_0 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000000";
constant ap_const_lv2_2 : STD_LOGIC_VECTOR (1 downto 0) := "10";
constant ap_const_lv32_1 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000001";
constant ap_const_lv64_1 : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000000000000000000000000000000000000000000000001";
constant ap_const_lv16_1 : STD_LOGIC_VECTOR (15 downto 0) := "0000000000000001";
constant ap_const_lv5_0 : STD_LOGIC_VECTOR (4 downto 0) := "00000";
constant ap_const_lv8_0 : STD_LOGIC_VECTOR (7 downto 0) := "00000000";
signal ap_CS_fsm : STD_LOGIC_VECTOR (5 downto 0) := "000000";
signal reg_512 : STD_LOGIC_VECTOR (31 downto 0);
signal stop_on_first_read_read_fu_150_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal c_load_reg_813 : STD_LOGIC_VECTOR (31 downto 0);
signal current_buckets_0_reg_822 : STD_LOGIC_VECTOR (31 downto 0);
signal current_buckets_1_reg_827 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_2_fu_548_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_2_reg_832 : STD_LOGIC_VECTOR (63 downto 0);
signal sample_buffer_addr_reg_837 : STD_LOGIC_VECTOR (31 downto 0);
signal i_fu_568_p2 : STD_LOGIC_VECTOR (15 downto 0);
signal i_reg_846 : STD_LOGIC_VECTOR (15 downto 0);
signal p_rec_i_fu_574_p2 : STD_LOGIC_VECTOR (63 downto 0);
signal p_rec_i_reg_851 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_3_fu_563_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal sym_reg_856 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_2_i_fu_580_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_2_i_reg_861 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_2_1_i_fu_586_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_2_1_i_reg_865 : STD_LOGIC_VECTOR (0 downto 0);
signal r_bit_p_bsf32_hw_fu_506_ap_return : STD_LOGIC_VECTOR (4 downto 0);
signal r_bit_reg_869 : STD_LOGIC_VECTOR (4 downto 0);
signal j_bucket_index1_ph_cast_fu_597_p1 : STD_LOGIC_VECTOR (7 downto 0);
signal j_bit1_ph_cast_fu_601_p1 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_10_i_cast_fu_605_p1 : STD_LOGIC_VECTOR (13 downto 0);
signal tmp_10_i_cast_reg_884 : STD_LOGIC_VECTOR (13 downto 0);
signal j_end_phi_fu_417_p4 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_11_i_fu_644_p2 : STD_LOGIC_VECTOR (13 downto 0);
signal tmp_11_i_reg_899 : STD_LOGIC_VECTOR (13 downto 0);
signal j_bit_reg_911 : STD_LOGIC_VECTOR (7 downto 0);
signal j_bucket_index_reg_916 : STD_LOGIC_VECTOR (7 downto 0);
signal j_bucket_reg_921 : STD_LOGIC_VECTOR (31 downto 0);
signal p_s_reg_926 : STD_LOGIC_VECTOR (0 downto 0);
signal next_buckets_0_1_fu_701_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal next_buckets_0_1_reg_937 : STD_LOGIC_VECTOR (31 downto 0);
signal next_buckets_1_1_fu_707_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_buckets_0_reg_947 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_buckets_1_reg_952 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_5_fu_737_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal grp_bitset_next_fu_460_ap_start : STD_LOGIC;
signal grp_bitset_next_fu_460_ap_done : STD_LOGIC;
signal grp_bitset_next_fu_460_ap_idle : STD_LOGIC;
signal grp_bitset_next_fu_460_ap_ready : STD_LOGIC;
signal grp_bitset_next_fu_460_ap_ce : STD_LOGIC;
signal grp_bitset_next_fu_460_p_read : STD_LOGIC_VECTOR (31 downto 0);
signal grp_bitset_next_fu_460_r_bit : STD_LOGIC_VECTOR (7 downto 0);
signal grp_bitset_next_fu_460_r_bucket_index : STD_LOGIC_VECTOR (7 downto 0);
signal grp_bitset_next_fu_460_r_bucket : STD_LOGIC_VECTOR (31 downto 0);
signal grp_bitset_next_fu_460_ap_return_0 : STD_LOGIC_VECTOR (7 downto 0);
signal grp_bitset_next_fu_460_ap_return_1 : STD_LOGIC_VECTOR (7 downto 0);
signal grp_bitset_next_fu_460_ap_return_2 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_bitset_next_fu_460_ap_return_3 : STD_LOGIC_VECTOR (0 downto 0);
signal grp_sample_iterator_next_fu_472_ap_start : STD_LOGIC;
signal grp_sample_iterator_next_fu_472_ap_done : STD_LOGIC;
signal grp_sample_iterator_next_fu_472_ap_idle : STD_LOGIC;
signal grp_sample_iterator_next_fu_472_ap_ready : STD_LOGIC;
signal grp_sample_iterator_next_fu_472_indices_req_din : STD_LOGIC;
signal grp_sample_iterator_next_fu_472_indices_req_full_n : STD_LOGIC;
signal grp_sample_iterator_next_fu_472_indices_req_write : STD_LOGIC;
signal grp_sample_iterator_next_fu_472_indices_rsp_empty_n : STD_LOGIC;
signal grp_sample_iterator_next_fu_472_indices_rsp_read : STD_LOGIC;
signal grp_sample_iterator_next_fu_472_indices_address : STD_LOGIC_VECTOR (31 downto 0);
signal grp_sample_iterator_next_fu_472_indices_datain : STD_LOGIC_VECTOR (55 downto 0);
signal grp_sample_iterator_next_fu_472_indices_dataout : STD_LOGIC_VECTOR (55 downto 0);
signal grp_sample_iterator_next_fu_472_indices_size : STD_LOGIC_VECTOR (31 downto 0);
signal grp_sample_iterator_next_fu_472_ap_ce : STD_LOGIC;
signal grp_sample_iterator_next_fu_472_i_index : STD_LOGIC_VECTOR (15 downto 0);
signal grp_sample_iterator_next_fu_472_i_sample : STD_LOGIC_VECTOR (15 downto 0);
signal grp_sample_iterator_next_fu_472_ap_return_0 : STD_LOGIC_VECTOR (15 downto 0);
signal grp_sample_iterator_next_fu_472_ap_return_1 : STD_LOGIC_VECTOR (15 downto 0);
signal grp_sample_iterator_get_offset_fu_482_ap_start : STD_LOGIC;
signal grp_sample_iterator_get_offset_fu_482_ap_done : STD_LOGIC;
signal grp_sample_iterator_get_offset_fu_482_ap_idle : STD_LOGIC;
signal grp_sample_iterator_get_offset_fu_482_ap_ready : STD_LOGIC;
signal grp_sample_iterator_get_offset_fu_482_indices_req_din : STD_LOGIC;
signal grp_sample_iterator_get_offset_fu_482_indices_req_full_n : STD_LOGIC;
signal grp_sample_iterator_get_offset_fu_482_indices_req_write : STD_LOGIC;
signal grp_sample_iterator_get_offset_fu_482_indices_rsp_empty_n : STD_LOGIC;
signal grp_sample_iterator_get_offset_fu_482_indices_rsp_read : STD_LOGIC;
signal grp_sample_iterator_get_offset_fu_482_indices_address : STD_LOGIC_VECTOR (31 downto 0);
signal grp_sample_iterator_get_offset_fu_482_indices_datain : STD_LOGIC_VECTOR (55 downto 0);
signal grp_sample_iterator_get_offset_fu_482_indices_dataout : STD_LOGIC_VECTOR (55 downto 0);
signal grp_sample_iterator_get_offset_fu_482_indices_size : STD_LOGIC_VECTOR (31 downto 0);
signal grp_sample_iterator_get_offset_fu_482_ap_ce : STD_LOGIC;
signal grp_sample_iterator_get_offset_fu_482_i_index : STD_LOGIC_VECTOR (15 downto 0);
signal grp_sample_iterator_get_offset_fu_482_i_sample : STD_LOGIC_VECTOR (15 downto 0);
signal grp_sample_iterator_get_offset_fu_482_sample_buffer_size : STD_LOGIC_VECTOR (31 downto 0);
signal grp_sample_iterator_get_offset_fu_482_sample_length : STD_LOGIC_VECTOR (15 downto 0);
signal grp_sample_iterator_get_offset_fu_482_ap_return : STD_LOGIC_VECTOR (31 downto 0);
signal grp_nfa_get_initials_fu_494_ap_start : STD_LOGIC;
signal grp_nfa_get_initials_fu_494_ap_done : STD_LOGIC;
signal grp_nfa_get_initials_fu_494_ap_idle : STD_LOGIC;
signal grp_nfa_get_initials_fu_494_ap_ready : STD_LOGIC;
signal grp_nfa_get_initials_fu_494_ap_ce : STD_LOGIC;
signal grp_nfa_get_initials_fu_494_nfa_initials_buckets_req_din : STD_LOGIC;
signal grp_nfa_get_initials_fu_494_nfa_initials_buckets_req_full_n : STD_LOGIC;
signal grp_nfa_get_initials_fu_494_nfa_initials_buckets_req_write : STD_LOGIC;
signal grp_nfa_get_initials_fu_494_nfa_initials_buckets_rsp_empty_n : STD_LOGIC;
signal grp_nfa_get_initials_fu_494_nfa_initials_buckets_rsp_read : STD_LOGIC;
signal grp_nfa_get_initials_fu_494_nfa_initials_buckets_address : STD_LOGIC_VECTOR (31 downto 0);
signal grp_nfa_get_initials_fu_494_nfa_initials_buckets_datain : STD_LOGIC_VECTOR (31 downto 0);
signal grp_nfa_get_initials_fu_494_nfa_initials_buckets_dataout : STD_LOGIC_VECTOR (31 downto 0);
signal grp_nfa_get_initials_fu_494_nfa_initials_buckets_size : STD_LOGIC_VECTOR (31 downto 0);
signal grp_nfa_get_initials_fu_494_ap_return_0 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_nfa_get_initials_fu_494_ap_return_1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_nfa_get_finals_fu_500_ap_start : STD_LOGIC;
signal grp_nfa_get_finals_fu_500_ap_done : STD_LOGIC;
signal grp_nfa_get_finals_fu_500_ap_idle : STD_LOGIC;
signal grp_nfa_get_finals_fu_500_ap_ready : STD_LOGIC;
signal grp_nfa_get_finals_fu_500_ap_ce : STD_LOGIC;
signal grp_nfa_get_finals_fu_500_nfa_finals_buckets_req_din : STD_LOGIC;
signal grp_nfa_get_finals_fu_500_nfa_finals_buckets_req_full_n : STD_LOGIC;
signal grp_nfa_get_finals_fu_500_nfa_finals_buckets_req_write : STD_LOGIC;
signal grp_nfa_get_finals_fu_500_nfa_finals_buckets_rsp_empty_n : STD_LOGIC;
signal grp_nfa_get_finals_fu_500_nfa_finals_buckets_rsp_read : STD_LOGIC;
signal grp_nfa_get_finals_fu_500_nfa_finals_buckets_address : STD_LOGIC_VECTOR (31 downto 0);
signal grp_nfa_get_finals_fu_500_nfa_finals_buckets_datain : STD_LOGIC_VECTOR (31 downto 0);
signal grp_nfa_get_finals_fu_500_nfa_finals_buckets_dataout : STD_LOGIC_VECTOR (31 downto 0);
signal grp_nfa_get_finals_fu_500_nfa_finals_buckets_size : STD_LOGIC_VECTOR (31 downto 0);
signal grp_nfa_get_finals_fu_500_ap_return_0 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_nfa_get_finals_fu_500_ap_return_1 : STD_LOGIC_VECTOR (31 downto 0);
signal r_bit_p_bsf32_hw_fu_506_bus_r : STD_LOGIC_VECTOR (31 downto 0);
signal i_index_reg_222 : STD_LOGIC_VECTOR (15 downto 0);
signal i_sample_reg_232 : STD_LOGIC_VECTOR (15 downto 0);
signal next_buckets_1_reg_242 : STD_LOGIC_VECTOR (31 downto 0);
signal any_0_i_phi_fu_429_p4 : STD_LOGIC_VECTOR (0 downto 0);
signal next_buckets_0_reg_252 : STD_LOGIC_VECTOR (31 downto 0);
signal i_0_i_reg_262 : STD_LOGIC_VECTOR (15 downto 0);
signal p_01_rec_i_reg_273 : STD_LOGIC_VECTOR (63 downto 0);
signal bus_assign_reg_284 : STD_LOGIC_VECTOR (31 downto 0);
signal agg_result_bucket_index_0_lcssa4_i_reg_296 : STD_LOGIC_VECTOR (0 downto 0);
signal j_bucket1_ph_phi_fu_313_p4 : STD_LOGIC_VECTOR (31 downto 0);
signal j_bucket1_ph_reg_309 : STD_LOGIC_VECTOR (31 downto 0);
signal j_bucket_index1_ph_phi_fu_326_p4 : STD_LOGIC_VECTOR (1 downto 0);
signal j_bucket_index1_ph_reg_322 : STD_LOGIC_VECTOR (1 downto 0);
signal agg_result_bucket_index_0_lcssa4_i_cast_cast_fu_592_p1 : STD_LOGIC_VECTOR (1 downto 0);
signal j_bit1_ph_phi_fu_337_p4 : STD_LOGIC_VECTOR (4 downto 0);
signal j_bit1_ph_reg_333 : STD_LOGIC_VECTOR (4 downto 0);
signal j_end_ph_phi_fu_348_p4 : STD_LOGIC_VECTOR (0 downto 0);
signal j_end_ph_reg_344 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_buckets_1_3_reg_357 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_buckets_0_3_reg_370 : STD_LOGIC_VECTOR (31 downto 0);
signal j_bucket1_reg_383 : STD_LOGIC_VECTOR (31 downto 0);
signal j_bucket_index1_reg_394 : STD_LOGIC_VECTOR (7 downto 0);
signal j_bit1_reg_404 : STD_LOGIC_VECTOR (7 downto 0);
signal j_end_reg_414 : STD_LOGIC_VECTOR (0 downto 0);
signal any_0_i_reg_424 : STD_LOGIC_VECTOR (0 downto 0);
signal r_reg_437 : STD_LOGIC_VECTOR (0 downto 0);
signal p_0_reg_448 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_i_13_fu_534_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal or_cond_fu_743_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal grp_bitset_next_fu_460_ap_start_ap_start_reg : STD_LOGIC := '0';
signal ap_NS_fsm : STD_LOGIC_VECTOR (5 downto 0);
signal grp_sample_iterator_next_fu_472_ap_start_ap_start_reg : STD_LOGIC := '0';
signal grp_sample_iterator_get_offset_fu_482_ap_start_ap_start_reg : STD_LOGIC := '0';
signal grp_nfa_get_initials_fu_494_ap_start_ap_start_reg : STD_LOGIC := '0';
signal grp_nfa_get_finals_fu_500_ap_start_ap_start_reg : STD_LOGIC := '0';
signal sum_fu_552_p2 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_12_i_cast_fu_656_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_13_i_cast_fu_690_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal c_fu_140 : STD_LOGIC_VECTOR (31 downto 0);
signal c_1_fu_748_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_i_fu_524_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_i_12_fu_529_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_6_fu_608_p1 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_i1_fu_612_p3 : STD_LOGIC_VECTOR (5 downto 0);
signal tmp_8_fu_620_p1 : STD_LOGIC_VECTOR (5 downto 0);
signal state_fu_624_p2 : STD_LOGIC_VECTOR (5 downto 0);
signal grp_fu_638_p0 : STD_LOGIC_VECTOR (7 downto 0);
signal grp_fu_638_p1 : STD_LOGIC_VECTOR (5 downto 0);
signal grp_fu_638_p2 : STD_LOGIC_VECTOR (13 downto 0);
signal tmp_12_i_fu_649_p3 : STD_LOGIC_VECTOR (14 downto 0);
signal tmp_13_i_fu_683_p3 : STD_LOGIC_VECTOR (14 downto 0);
signal current_buckets_1_1_fu_726_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal current_buckets_0_1_fu_721_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_1_fu_731_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_638_ce : STD_LOGIC;
signal grp_fu_638_p00 : STD_LOGIC_VECTOR (13 downto 0);
signal grp_fu_638_p10 : STD_LOGIC_VECTOR (13 downto 0);
signal ap_sig_bdd_370 : BOOLEAN;
signal ap_sig_bdd_187 : BOOLEAN;
component bitset_next IS
port (
ap_clk : IN STD_LOGIC;
ap_rst : IN STD_LOGIC;
ap_start : IN STD_LOGIC;
ap_done : OUT STD_LOGIC;
ap_idle : OUT STD_LOGIC;
ap_ready : OUT STD_LOGIC;
ap_ce : IN STD_LOGIC;
p_read : IN STD_LOGIC_VECTOR (31 downto 0);
r_bit : IN STD_LOGIC_VECTOR (7 downto 0);
r_bucket_index : IN STD_LOGIC_VECTOR (7 downto 0);
r_bucket : IN STD_LOGIC_VECTOR (31 downto 0);
ap_return_0 : OUT STD_LOGIC_VECTOR (7 downto 0);
ap_return_1 : OUT STD_LOGIC_VECTOR (7 downto 0);
ap_return_2 : OUT STD_LOGIC_VECTOR (31 downto 0);
ap_return_3 : OUT STD_LOGIC_VECTOR (0 downto 0) );
end component;
component sample_iterator_next IS
port (
ap_clk : IN STD_LOGIC;
ap_rst : IN STD_LOGIC;
ap_start : IN STD_LOGIC;
ap_done : OUT STD_LOGIC;
ap_idle : OUT STD_LOGIC;
ap_ready : OUT STD_LOGIC;
indices_req_din : OUT STD_LOGIC;
indices_req_full_n : IN STD_LOGIC;
indices_req_write : OUT STD_LOGIC;
indices_rsp_empty_n : IN STD_LOGIC;
indices_rsp_read : OUT STD_LOGIC;
indices_address : OUT STD_LOGIC_VECTOR (31 downto 0);
indices_datain : IN STD_LOGIC_VECTOR (55 downto 0);
indices_dataout : OUT STD_LOGIC_VECTOR (55 downto 0);
indices_size : OUT STD_LOGIC_VECTOR (31 downto 0);
ap_ce : IN STD_LOGIC;
i_index : IN STD_LOGIC_VECTOR (15 downto 0);
i_sample : IN STD_LOGIC_VECTOR (15 downto 0);
ap_return_0 : OUT STD_LOGIC_VECTOR (15 downto 0);
ap_return_1 : OUT STD_LOGIC_VECTOR (15 downto 0) );
end component;
component sample_iterator_get_offset IS
port (
ap_clk : IN STD_LOGIC;
ap_rst : IN STD_LOGIC;
ap_start : IN STD_LOGIC;
ap_done : OUT STD_LOGIC;
ap_idle : OUT STD_LOGIC;
ap_ready : OUT STD_LOGIC;
indices_req_din : OUT STD_LOGIC;
indices_req_full_n : IN STD_LOGIC;
indices_req_write : OUT STD_LOGIC;
indices_rsp_empty_n : IN STD_LOGIC;
indices_rsp_read : OUT STD_LOGIC;
indices_address : OUT STD_LOGIC_VECTOR (31 downto 0);
indices_datain : IN STD_LOGIC_VECTOR (55 downto 0);
indices_dataout : OUT STD_LOGIC_VECTOR (55 downto 0);
indices_size : OUT STD_LOGIC_VECTOR (31 downto 0);
ap_ce : IN STD_LOGIC;
i_index : IN STD_LOGIC_VECTOR (15 downto 0);
i_sample : IN STD_LOGIC_VECTOR (15 downto 0);
sample_buffer_size : IN STD_LOGIC_VECTOR (31 downto 0);
sample_length : IN STD_LOGIC_VECTOR (15 downto 0);
ap_return : OUT STD_LOGIC_VECTOR (31 downto 0) );
end component;
component nfa_get_initials IS
port (
ap_clk : IN STD_LOGIC;
ap_rst : IN STD_LOGIC;
ap_start : IN STD_LOGIC;
ap_done : OUT STD_LOGIC;
ap_idle : OUT STD_LOGIC;
ap_ready : OUT STD_LOGIC;
ap_ce : IN STD_LOGIC;
nfa_initials_buckets_req_din : OUT STD_LOGIC;
nfa_initials_buckets_req_full_n : IN STD_LOGIC;
nfa_initials_buckets_req_write : OUT STD_LOGIC;
nfa_initials_buckets_rsp_empty_n : IN STD_LOGIC;
nfa_initials_buckets_rsp_read : OUT STD_LOGIC;
nfa_initials_buckets_address : OUT STD_LOGIC_VECTOR (31 downto 0);
nfa_initials_buckets_datain : IN STD_LOGIC_VECTOR (31 downto 0);
nfa_initials_buckets_dataout : OUT STD_LOGIC_VECTOR (31 downto 0);
nfa_initials_buckets_size : OUT STD_LOGIC_VECTOR (31 downto 0);
ap_return_0 : OUT STD_LOGIC_VECTOR (31 downto 0);
ap_return_1 : OUT STD_LOGIC_VECTOR (31 downto 0) );
end component;
component nfa_get_finals IS
port (
ap_clk : IN STD_LOGIC;
ap_rst : IN STD_LOGIC;
ap_start : IN STD_LOGIC;
ap_done : OUT STD_LOGIC;
ap_idle : OUT STD_LOGIC;
ap_ready : OUT STD_LOGIC;
ap_ce : IN STD_LOGIC;
nfa_finals_buckets_req_din : OUT STD_LOGIC;
nfa_finals_buckets_req_full_n : IN STD_LOGIC;
nfa_finals_buckets_req_write : OUT STD_LOGIC;
nfa_finals_buckets_rsp_empty_n : IN STD_LOGIC;
nfa_finals_buckets_rsp_read : OUT STD_LOGIC;
nfa_finals_buckets_address : OUT STD_LOGIC_VECTOR (31 downto 0);
nfa_finals_buckets_datain : IN STD_LOGIC_VECTOR (31 downto 0);
nfa_finals_buckets_dataout : OUT STD_LOGIC_VECTOR (31 downto 0);
nfa_finals_buckets_size : OUT STD_LOGIC_VECTOR (31 downto 0);
ap_return_0 : OUT STD_LOGIC_VECTOR (31 downto 0);
ap_return_1 : OUT STD_LOGIC_VECTOR (31 downto 0) );
end component;
component p_bsf32_hw IS
port (
bus_r : IN STD_LOGIC_VECTOR (31 downto 0);
ap_return : OUT STD_LOGIC_VECTOR (4 downto 0) );
end component;
component nfa_accept_samples_generic_hw_mul_8ns_6ns_14_2 IS
generic (
ID : INTEGER;
NUM_STAGE : INTEGER;
din0_WIDTH : INTEGER;
din1_WIDTH : INTEGER;
dout_WIDTH : INTEGER );
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
din0 : IN STD_LOGIC_VECTOR (7 downto 0);
din1 : IN STD_LOGIC_VECTOR (5 downto 0);
ce : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR (13 downto 0) );
end component;
begin
grp_bitset_next_fu_460 : component bitset_next
port map (
ap_clk => ap_clk,
ap_rst => ap_rst,
ap_start => grp_bitset_next_fu_460_ap_start,
ap_done => grp_bitset_next_fu_460_ap_done,
ap_idle => grp_bitset_next_fu_460_ap_idle,
ap_ready => grp_bitset_next_fu_460_ap_ready,
ap_ce => grp_bitset_next_fu_460_ap_ce,
p_read => grp_bitset_next_fu_460_p_read,
r_bit => grp_bitset_next_fu_460_r_bit,
r_bucket_index => grp_bitset_next_fu_460_r_bucket_index,
r_bucket => grp_bitset_next_fu_460_r_bucket,
ap_return_0 => grp_bitset_next_fu_460_ap_return_0,
ap_return_1 => grp_bitset_next_fu_460_ap_return_1,
ap_return_2 => grp_bitset_next_fu_460_ap_return_2,
ap_return_3 => grp_bitset_next_fu_460_ap_return_3);
grp_sample_iterator_next_fu_472 : component sample_iterator_next
port map (
ap_clk => ap_clk,
ap_rst => ap_rst,
ap_start => grp_sample_iterator_next_fu_472_ap_start,
ap_done => grp_sample_iterator_next_fu_472_ap_done,
ap_idle => grp_sample_iterator_next_fu_472_ap_idle,
ap_ready => grp_sample_iterator_next_fu_472_ap_ready,
indices_req_din => grp_sample_iterator_next_fu_472_indices_req_din,
indices_req_full_n => grp_sample_iterator_next_fu_472_indices_req_full_n,
indices_req_write => grp_sample_iterator_next_fu_472_indices_req_write,
indices_rsp_empty_n => grp_sample_iterator_next_fu_472_indices_rsp_empty_n,
indices_rsp_read => grp_sample_iterator_next_fu_472_indices_rsp_read,
indices_address => grp_sample_iterator_next_fu_472_indices_address,
indices_datain => grp_sample_iterator_next_fu_472_indices_datain,
indices_dataout => grp_sample_iterator_next_fu_472_indices_dataout,
indices_size => grp_sample_iterator_next_fu_472_indices_size,
ap_ce => grp_sample_iterator_next_fu_472_ap_ce,
i_index => grp_sample_iterator_next_fu_472_i_index,
i_sample => grp_sample_iterator_next_fu_472_i_sample,
ap_return_0 => grp_sample_iterator_next_fu_472_ap_return_0,
ap_return_1 => grp_sample_iterator_next_fu_472_ap_return_1);
grp_sample_iterator_get_offset_fu_482 : component sample_iterator_get_offset
port map (
ap_clk => ap_clk,
ap_rst => ap_rst,
ap_start => grp_sample_iterator_get_offset_fu_482_ap_start,
ap_done => grp_sample_iterator_get_offset_fu_482_ap_done,
ap_idle => grp_sample_iterator_get_offset_fu_482_ap_idle,
ap_ready => grp_sample_iterator_get_offset_fu_482_ap_ready,
indices_req_din => grp_sample_iterator_get_offset_fu_482_indices_req_din,
indices_req_full_n => grp_sample_iterator_get_offset_fu_482_indices_req_full_n,
indices_req_write => grp_sample_iterator_get_offset_fu_482_indices_req_write,
indices_rsp_empty_n => grp_sample_iterator_get_offset_fu_482_indices_rsp_empty_n,
indices_rsp_read => grp_sample_iterator_get_offset_fu_482_indices_rsp_read,
indices_address => grp_sample_iterator_get_offset_fu_482_indices_address,
indices_datain => grp_sample_iterator_get_offset_fu_482_indices_datain,
indices_dataout => grp_sample_iterator_get_offset_fu_482_indices_dataout,
indices_size => grp_sample_iterator_get_offset_fu_482_indices_size,
ap_ce => grp_sample_iterator_get_offset_fu_482_ap_ce,
i_index => grp_sample_iterator_get_offset_fu_482_i_index,
i_sample => grp_sample_iterator_get_offset_fu_482_i_sample,
sample_buffer_size => grp_sample_iterator_get_offset_fu_482_sample_buffer_size,
sample_length => grp_sample_iterator_get_offset_fu_482_sample_length,
ap_return => grp_sample_iterator_get_offset_fu_482_ap_return);
grp_nfa_get_initials_fu_494 : component nfa_get_initials
port map (
ap_clk => ap_clk,
ap_rst => ap_rst,
ap_start => grp_nfa_get_initials_fu_494_ap_start,
ap_done => grp_nfa_get_initials_fu_494_ap_done,
ap_idle => grp_nfa_get_initials_fu_494_ap_idle,
ap_ready => grp_nfa_get_initials_fu_494_ap_ready,
ap_ce => grp_nfa_get_initials_fu_494_ap_ce,
nfa_initials_buckets_req_din => grp_nfa_get_initials_fu_494_nfa_initials_buckets_req_din,
nfa_initials_buckets_req_full_n => grp_nfa_get_initials_fu_494_nfa_initials_buckets_req_full_n,
nfa_initials_buckets_req_write => grp_nfa_get_initials_fu_494_nfa_initials_buckets_req_write,
nfa_initials_buckets_rsp_empty_n => grp_nfa_get_initials_fu_494_nfa_initials_buckets_rsp_empty_n,
nfa_initials_buckets_rsp_read => grp_nfa_get_initials_fu_494_nfa_initials_buckets_rsp_read,
nfa_initials_buckets_address => grp_nfa_get_initials_fu_494_nfa_initials_buckets_address,
nfa_initials_buckets_datain => grp_nfa_get_initials_fu_494_nfa_initials_buckets_datain,
nfa_initials_buckets_dataout => grp_nfa_get_initials_fu_494_nfa_initials_buckets_dataout,
nfa_initials_buckets_size => grp_nfa_get_initials_fu_494_nfa_initials_buckets_size,
ap_return_0 => grp_nfa_get_initials_fu_494_ap_return_0,
ap_return_1 => grp_nfa_get_initials_fu_494_ap_return_1);
grp_nfa_get_finals_fu_500 : component nfa_get_finals
port map (
ap_clk => ap_clk,
ap_rst => ap_rst,
ap_start => grp_nfa_get_finals_fu_500_ap_start,
ap_done => grp_nfa_get_finals_fu_500_ap_done,
ap_idle => grp_nfa_get_finals_fu_500_ap_idle,
ap_ready => grp_nfa_get_finals_fu_500_ap_ready,
ap_ce => grp_nfa_get_finals_fu_500_ap_ce,
nfa_finals_buckets_req_din => grp_nfa_get_finals_fu_500_nfa_finals_buckets_req_din,
nfa_finals_buckets_req_full_n => grp_nfa_get_finals_fu_500_nfa_finals_buckets_req_full_n,
nfa_finals_buckets_req_write => grp_nfa_get_finals_fu_500_nfa_finals_buckets_req_write,
nfa_finals_buckets_rsp_empty_n => grp_nfa_get_finals_fu_500_nfa_finals_buckets_rsp_empty_n,
nfa_finals_buckets_rsp_read => grp_nfa_get_finals_fu_500_nfa_finals_buckets_rsp_read,
nfa_finals_buckets_address => grp_nfa_get_finals_fu_500_nfa_finals_buckets_address,
nfa_finals_buckets_datain => grp_nfa_get_finals_fu_500_nfa_finals_buckets_datain,
nfa_finals_buckets_dataout => grp_nfa_get_finals_fu_500_nfa_finals_buckets_dataout,
nfa_finals_buckets_size => grp_nfa_get_finals_fu_500_nfa_finals_buckets_size,
ap_return_0 => grp_nfa_get_finals_fu_500_ap_return_0,
ap_return_1 => grp_nfa_get_finals_fu_500_ap_return_1);
r_bit_p_bsf32_hw_fu_506 : component p_bsf32_hw
port map (
bus_r => r_bit_p_bsf32_hw_fu_506_bus_r,
ap_return => r_bit_p_bsf32_hw_fu_506_ap_return);
nfa_accept_samples_generic_hw_mul_8ns_6ns_14_2_U16 : component nfa_accept_samples_generic_hw_mul_8ns_6ns_14_2
generic map (
ID => 16,
NUM_STAGE => 2,
din0_WIDTH => 8,
din1_WIDTH => 6,
dout_WIDTH => 14)
port map (
clk => ap_clk,
reset => ap_rst,
din0 => grp_fu_638_p0,
din1 => grp_fu_638_p1,
ce => grp_fu_638_ce,
dout => grp_fu_638_p2);
-- the current state (ap_CS_fsm) of the state machine. --
ap_CS_fsm_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_CS_fsm <= ap_ST_st1_fsm_0;
else
ap_CS_fsm <= ap_NS_fsm;
end if;
end if;
end process;
-- grp_bitset_next_fu_460_ap_start_ap_start_reg assign process. --
grp_bitset_next_fu_460_ap_start_ap_start_reg_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
grp_bitset_next_fu_460_ap_start_ap_start_reg <= ap_const_logic_0;
else
if (((ap_ST_st16_fsm_15 = ap_CS_fsm) and (ap_ST_st17_fsm_16 = ap_NS_fsm))) then
grp_bitset_next_fu_460_ap_start_ap_start_reg <= ap_const_logic_1;
elsif ((ap_const_logic_1 = grp_bitset_next_fu_460_ap_ready)) then
grp_bitset_next_fu_460_ap_start_ap_start_reg <= ap_const_logic_0;
end if;
end if;
end if;
end process;
-- grp_nfa_get_finals_fu_500_ap_start_ap_start_reg assign process. --
grp_nfa_get_finals_fu_500_ap_start_ap_start_reg_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
grp_nfa_get_finals_fu_500_ap_start_ap_start_reg <= ap_const_logic_0;
else
if (((ap_ST_st10_fsm_9 = ap_CS_fsm) and (ap_ST_st25_fsm_24 = ap_NS_fsm))) then
grp_nfa_get_finals_fu_500_ap_start_ap_start_reg <= ap_const_logic_1;
elsif ((ap_const_logic_1 = grp_nfa_get_finals_fu_500_ap_ready)) then
grp_nfa_get_finals_fu_500_ap_start_ap_start_reg <= ap_const_logic_0;
end if;
end if;
end if;
end process;
-- grp_nfa_get_initials_fu_494_ap_start_ap_start_reg assign process. --
grp_nfa_get_initials_fu_494_ap_start_ap_start_reg_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
grp_nfa_get_initials_fu_494_ap_start_ap_start_reg <= ap_const_logic_0;
else
if (((ap_ST_st2_fsm_1 = ap_CS_fsm) and (ap_ST_st3_fsm_2 = ap_NS_fsm))) then
grp_nfa_get_initials_fu_494_ap_start_ap_start_reg <= ap_const_logic_1;
elsif ((ap_const_logic_1 = grp_nfa_get_initials_fu_494_ap_ready)) then
grp_nfa_get_initials_fu_494_ap_start_ap_start_reg <= ap_const_logic_0;
end if;
end if;
end if;
end process;
-- grp_sample_iterator_get_offset_fu_482_ap_start_ap_start_reg assign process. --
grp_sample_iterator_get_offset_fu_482_ap_start_ap_start_reg_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
grp_sample_iterator_get_offset_fu_482_ap_start_ap_start_reg <= ap_const_logic_0;
else
if (((ap_ST_st5_fsm_4 = ap_NS_fsm) and (ap_ST_st4_fsm_3 = ap_CS_fsm))) then
grp_sample_iterator_get_offset_fu_482_ap_start_ap_start_reg <= ap_const_logic_1;
elsif ((ap_const_logic_1 = grp_sample_iterator_get_offset_fu_482_ap_ready)) then
grp_sample_iterator_get_offset_fu_482_ap_start_ap_start_reg <= ap_const_logic_0;
end if;
end if;
end if;
end process;
-- grp_sample_iterator_next_fu_472_ap_start_ap_start_reg assign process. --
grp_sample_iterator_next_fu_472_ap_start_ap_start_reg_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
grp_sample_iterator_next_fu_472_ap_start_ap_start_reg <= ap_const_logic_0;
else
if (((ap_ST_st32_fsm_31 = ap_CS_fsm) and (ap_ST_st33_fsm_32 = ap_NS_fsm))) then
grp_sample_iterator_next_fu_472_ap_start_ap_start_reg <= ap_const_logic_1;
elsif ((ap_const_logic_1 = grp_sample_iterator_next_fu_472_ap_ready)) then
grp_sample_iterator_next_fu_472_ap_start_ap_start_reg <= ap_const_logic_0;
end if;
end if;
end if;
end process;
-- agg_result_bucket_index_0_lcssa4_i_reg_296 assign process. --
agg_result_bucket_index_0_lcssa4_i_reg_296_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_sig_bdd_187) then
if (ap_sig_bdd_370) then
agg_result_bucket_index_0_lcssa4_i_reg_296 <= ap_const_lv1_1;
elsif ((ap_const_lv1_0 = tmp_2_i_fu_580_p2)) then
agg_result_bucket_index_0_lcssa4_i_reg_296 <= ap_const_lv1_0;
end if;
end if;
end if;
end process;
-- any_0_i_reg_424 assign process. --
any_0_i_reg_424_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_ST_st15_fsm_14 = ap_CS_fsm)) then
any_0_i_reg_424 <= ap_const_lv1_0;
elsif ((ap_ST_st24_fsm_23 = ap_CS_fsm)) then
any_0_i_reg_424 <= ap_const_lv1_1;
end if;
end if;
end process;
-- bus_assign_reg_284 assign process. --
bus_assign_reg_284_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_sig_bdd_187) then
if (ap_sig_bdd_370) then
bus_assign_reg_284 <= next_buckets_1_reg_242;
elsif ((ap_const_lv1_0 = tmp_2_i_fu_580_p2)) then
bus_assign_reg_284 <= next_buckets_0_reg_252;
end if;
end if;
end if;
end process;
-- c_fu_140 assign process. --
c_fu_140_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ST_st32_fsm_31 = ap_CS_fsm) and (stop_on_first_read_read_fu_150_p2 = ap_const_lv1_0) and (ap_const_lv1_0 = or_cond_fu_743_p2))) then
c_fu_140 <= c_1_fu_748_p2;
elsif (((ap_ST_st1_fsm_0 = ap_CS_fsm) and not((ap_start = ap_const_logic_0)))) then
c_fu_140 <= ap_const_lv32_0;
end if;
end if;
end process;
-- i_0_i_reg_262 assign process. --
i_0_i_reg_262_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ST_st16_fsm_15 = ap_CS_fsm) and not((ap_const_lv1_0 = j_end_phi_fu_417_p4)) and not((ap_const_lv1_0 = any_0_i_phi_fu_429_p4)))) then
i_0_i_reg_262 <= i_reg_846;
elsif ((ap_ST_st9_fsm_8 = ap_CS_fsm)) then
i_0_i_reg_262 <= ap_const_lv16_0;
end if;
end if;
end process;
-- i_index_reg_222 assign process. --
i_index_reg_222_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_ST_st36_fsm_35 = ap_CS_fsm)) then
i_index_reg_222 <= grp_sample_iterator_next_fu_472_ap_return_0;
elsif (((ap_ST_st1_fsm_0 = ap_CS_fsm) and not((ap_start = ap_const_logic_0)))) then
i_index_reg_222 <= begin_index;
end if;
end if;
end process;
-- i_sample_reg_232 assign process. --
i_sample_reg_232_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_ST_st36_fsm_35 = ap_CS_fsm)) then
i_sample_reg_232 <= grp_sample_iterator_next_fu_472_ap_return_1;
elsif (((ap_ST_st1_fsm_0 = ap_CS_fsm) and not((ap_start = ap_const_logic_0)))) then
i_sample_reg_232 <= begin_sample;
end if;
end if;
end process;
-- j_bit1_reg_404 assign process. --
j_bit1_reg_404_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_ST_st15_fsm_14 = ap_CS_fsm)) then
j_bit1_reg_404 <= j_bit1_ph_cast_fu_601_p1;
elsif ((ap_ST_st24_fsm_23 = ap_CS_fsm)) then
j_bit1_reg_404 <= j_bit_reg_911;
end if;
end if;
end process;
-- j_bucket1_ph_reg_309 assign process. --
j_bucket1_ph_reg_309_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ST_st15_fsm_14 = ap_CS_fsm) and ((ap_const_lv1_0 = tmp_2_i_reg_861) or (ap_const_lv1_0 = tmp_2_1_i_reg_865)))) then
j_bucket1_ph_reg_309 <= bus_assign_reg_284;
elsif (((ap_ST_st13_fsm_12 = ap_CS_fsm) and not((sample_buffer_rsp_empty_n = ap_const_logic_0)) and not((ap_const_lv1_0 = tmp_2_i_fu_580_p2)) and not((ap_const_lv1_0 = tmp_2_1_i_fu_586_p2)))) then
j_bucket1_ph_reg_309 <= ap_const_lv32_0;
end if;
end if;
end process;
-- j_bucket1_reg_383 assign process. --
j_bucket1_reg_383_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_ST_st15_fsm_14 = ap_CS_fsm)) then
j_bucket1_reg_383 <= j_bucket1_ph_phi_fu_313_p4;
elsif ((ap_ST_st24_fsm_23 = ap_CS_fsm)) then
j_bucket1_reg_383 <= j_bucket_reg_921;
end if;
end if;
end process;
-- j_bucket_index1_ph_reg_322 assign process. --
j_bucket_index1_ph_reg_322_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ST_st15_fsm_14 = ap_CS_fsm) and ((ap_const_lv1_0 = tmp_2_i_reg_861) or (ap_const_lv1_0 = tmp_2_1_i_reg_865)))) then
j_bucket_index1_ph_reg_322 <= agg_result_bucket_index_0_lcssa4_i_cast_cast_fu_592_p1;
elsif (((ap_ST_st13_fsm_12 = ap_CS_fsm) and not((sample_buffer_rsp_empty_n = ap_const_logic_0)) and not((ap_const_lv1_0 = tmp_2_i_fu_580_p2)) and not((ap_const_lv1_0 = tmp_2_1_i_fu_586_p2)))) then
j_bucket_index1_ph_reg_322 <= ap_const_lv2_2;
end if;
end if;
end process;
-- j_bucket_index1_reg_394 assign process. --
j_bucket_index1_reg_394_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_ST_st15_fsm_14 = ap_CS_fsm)) then
j_bucket_index1_reg_394 <= j_bucket_index1_ph_cast_fu_597_p1;
elsif ((ap_ST_st24_fsm_23 = ap_CS_fsm)) then
j_bucket_index1_reg_394 <= j_bucket_index_reg_916;
end if;
end if;
end process;
-- j_end_ph_reg_344 assign process. --
j_end_ph_reg_344_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ST_st15_fsm_14 = ap_CS_fsm) and ((ap_const_lv1_0 = tmp_2_i_reg_861) or (ap_const_lv1_0 = tmp_2_1_i_reg_865)))) then
j_end_ph_reg_344 <= ap_const_lv1_0;
elsif (((ap_ST_st13_fsm_12 = ap_CS_fsm) and not((sample_buffer_rsp_empty_n = ap_const_logic_0)) and not((ap_const_lv1_0 = tmp_2_i_fu_580_p2)) and not((ap_const_lv1_0 = tmp_2_1_i_fu_586_p2)))) then
j_end_ph_reg_344 <= ap_const_lv1_1;
end if;
end if;
end process;
-- j_end_reg_414 assign process. --
j_end_reg_414_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_ST_st15_fsm_14 = ap_CS_fsm)) then
j_end_reg_414 <= j_end_ph_phi_fu_348_p4;
elsif ((ap_ST_st24_fsm_23 = ap_CS_fsm)) then
j_end_reg_414 <= p_s_reg_926;
end if;
end if;
end process;
-- next_buckets_0_reg_252 assign process. --
next_buckets_0_reg_252_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ST_st16_fsm_15 = ap_CS_fsm) and not((ap_const_lv1_0 = j_end_phi_fu_417_p4)) and not((ap_const_lv1_0 = any_0_i_phi_fu_429_p4)))) then
next_buckets_0_reg_252 <= tmp_buckets_0_3_reg_370;
elsif ((ap_ST_st9_fsm_8 = ap_CS_fsm)) then
next_buckets_0_reg_252 <= current_buckets_0_reg_822;
end if;
end if;
end process;
-- next_buckets_1_reg_242 assign process. --
next_buckets_1_reg_242_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ST_st16_fsm_15 = ap_CS_fsm) and not((ap_const_lv1_0 = j_end_phi_fu_417_p4)) and not((ap_const_lv1_0 = any_0_i_phi_fu_429_p4)))) then
next_buckets_1_reg_242 <= tmp_buckets_1_3_reg_357;
elsif ((ap_ST_st9_fsm_8 = ap_CS_fsm)) then
next_buckets_1_reg_242 <= current_buckets_1_reg_827;
end if;
end if;
end process;
-- p_01_rec_i_reg_273 assign process. --
p_01_rec_i_reg_273_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ST_st16_fsm_15 = ap_CS_fsm) and not((ap_const_lv1_0 = j_end_phi_fu_417_p4)) and not((ap_const_lv1_0 = any_0_i_phi_fu_429_p4)))) then
p_01_rec_i_reg_273 <= p_rec_i_reg_851;
elsif ((ap_ST_st9_fsm_8 = ap_CS_fsm)) then
p_01_rec_i_reg_273 <= ap_const_lv64_0;
end if;
end if;
end process;
-- p_0_reg_448 assign process. --
p_0_reg_448_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ST_st32_fsm_31 = ap_CS_fsm) and not((stop_on_first_read_read_fu_150_p2 = ap_const_lv1_0)) and (ap_const_lv1_0 = or_cond_fu_743_p2))) then
p_0_reg_448 <= ap_const_lv32_1;
elsif (((ap_ST_st2_fsm_1 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_i_13_fu_534_p2)))) then
p_0_reg_448 <= c_fu_140;
end if;
end if;
end process;
-- r_reg_437 assign process. --
r_reg_437_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ST_st16_fsm_15 = ap_CS_fsm) and not((ap_const_lv1_0 = j_end_phi_fu_417_p4)) and (ap_const_lv1_0 = any_0_i_phi_fu_429_p4))) then
r_reg_437 <= ap_const_lv1_0;
elsif ((ap_ST_st31_fsm_30 = ap_CS_fsm)) then
r_reg_437 <= tmp_5_fu_737_p2;
end if;
end if;
end process;
-- tmp_buckets_0_3_reg_370 assign process. --
tmp_buckets_0_3_reg_370_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_ST_st15_fsm_14 = ap_CS_fsm)) then
tmp_buckets_0_3_reg_370 <= ap_const_lv32_0;
elsif ((ap_ST_st24_fsm_23 = ap_CS_fsm)) then
tmp_buckets_0_3_reg_370 <= next_buckets_0_1_reg_937;
end if;
end if;
end process;
-- tmp_buckets_1_3_reg_357 assign process. --
tmp_buckets_1_3_reg_357_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_ST_st15_fsm_14 = ap_CS_fsm)) then
tmp_buckets_1_3_reg_357 <= ap_const_lv32_0;
elsif ((ap_ST_st24_fsm_23 = ap_CS_fsm)) then
tmp_buckets_1_3_reg_357 <= next_buckets_1_1_fu_707_p2;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_ST_st2_fsm_1 = ap_CS_fsm)) then
c_load_reg_813 <= c_fu_140;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_ST_st8_fsm_7 = ap_CS_fsm)) then
current_buckets_0_reg_822 <= grp_nfa_get_initials_fu_494_ap_return_0;
current_buckets_1_reg_827 <= grp_nfa_get_initials_fu_494_ap_return_1;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_ST_st10_fsm_9 = ap_CS_fsm)) then
i_reg_846 <= i_fu_568_p2;
sample_buffer_addr_reg_837 <= sum_fu_552_p2(32 - 1 downto 0);
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ST_st15_fsm_14 = ap_CS_fsm) and ((ap_const_lv1_0 = tmp_2_i_reg_861) or (ap_const_lv1_0 = tmp_2_1_i_reg_865)))) then
j_bit1_ph_reg_333 <= r_bit_reg_869;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_ST_st19_fsm_18 = ap_CS_fsm)) then
j_bit_reg_911 <= grp_bitset_next_fu_460_ap_return_0;
j_bucket_index_reg_916 <= grp_bitset_next_fu_460_ap_return_1;
j_bucket_reg_921 <= grp_bitset_next_fu_460_ap_return_2;
p_s_reg_926 <= grp_bitset_next_fu_460_ap_return_3;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_ST_st21_fsm_20 = ap_CS_fsm)) then
next_buckets_0_1_reg_937 <= next_buckets_0_1_fu_701_p2;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ST_st10_fsm_9 = ap_CS_fsm) and not((tmp_3_fu_563_p2 = ap_const_lv1_0)))) then
p_rec_i_reg_851 <= p_rec_i_fu_574_p2;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_ST_st14_fsm_13 = ap_CS_fsm)) then
r_bit_reg_869 <= r_bit_p_bsf32_hw_fu_506_ap_return;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((((ap_ST_st20_fsm_19 = ap_CS_fsm) and not((nfa_forward_buckets_rsp_empty_n = ap_const_logic_0))) or (not((nfa_forward_buckets_rsp_empty_n = ap_const_logic_0)) and (ap_ST_st23_fsm_22 = ap_CS_fsm)))) then
reg_512 <= nfa_forward_buckets_datain;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ST_st13_fsm_12 = ap_CS_fsm) and not((sample_buffer_rsp_empty_n = ap_const_logic_0)))) then
sym_reg_856 <= sample_buffer_datain;
tmp_2_i_reg_861 <= tmp_2_i_fu_580_p2;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_ST_st15_fsm_14 = ap_CS_fsm)) then
tmp_10_i_cast_reg_884(0) <= tmp_10_i_cast_fu_605_p1(0);
tmp_10_i_cast_reg_884(1) <= tmp_10_i_cast_fu_605_p1(1);
tmp_10_i_cast_reg_884(2) <= tmp_10_i_cast_fu_605_p1(2);
tmp_10_i_cast_reg_884(3) <= tmp_10_i_cast_fu_605_p1(3);
tmp_10_i_cast_reg_884(4) <= tmp_10_i_cast_fu_605_p1(4);
tmp_10_i_cast_reg_884(5) <= tmp_10_i_cast_fu_605_p1(5);
tmp_10_i_cast_reg_884(6) <= tmp_10_i_cast_fu_605_p1(6);
tmp_10_i_cast_reg_884(7) <= tmp_10_i_cast_fu_605_p1(7);
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_ST_st17_fsm_16 = ap_CS_fsm)) then
tmp_11_i_reg_899 <= tmp_11_i_fu_644_p2;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ST_st13_fsm_12 = ap_CS_fsm) and not((sample_buffer_rsp_empty_n = ap_const_logic_0)) and not((ap_const_lv1_0 = tmp_2_i_fu_580_p2)))) then
tmp_2_1_i_reg_865 <= tmp_2_1_i_fu_586_p2;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_ST_st9_fsm_8 = ap_CS_fsm)) then
tmp_2_reg_832(0) <= tmp_2_fu_548_p1(0);
tmp_2_reg_832(1) <= tmp_2_fu_548_p1(1);
tmp_2_reg_832(2) <= tmp_2_fu_548_p1(2);
tmp_2_reg_832(3) <= tmp_2_fu_548_p1(3);
tmp_2_reg_832(4) <= tmp_2_fu_548_p1(4);
tmp_2_reg_832(5) <= tmp_2_fu_548_p1(5);
tmp_2_reg_832(6) <= tmp_2_fu_548_p1(6);
tmp_2_reg_832(7) <= tmp_2_fu_548_p1(7);
tmp_2_reg_832(8) <= tmp_2_fu_548_p1(8);
tmp_2_reg_832(9) <= tmp_2_fu_548_p1(9);
tmp_2_reg_832(10) <= tmp_2_fu_548_p1(10);
tmp_2_reg_832(11) <= tmp_2_fu_548_p1(11);
tmp_2_reg_832(12) <= tmp_2_fu_548_p1(12);
tmp_2_reg_832(13) <= tmp_2_fu_548_p1(13);
tmp_2_reg_832(14) <= tmp_2_fu_548_p1(14);
tmp_2_reg_832(15) <= tmp_2_fu_548_p1(15);
tmp_2_reg_832(16) <= tmp_2_fu_548_p1(16);
tmp_2_reg_832(17) <= tmp_2_fu_548_p1(17);
tmp_2_reg_832(18) <= tmp_2_fu_548_p1(18);
tmp_2_reg_832(19) <= tmp_2_fu_548_p1(19);
tmp_2_reg_832(20) <= tmp_2_fu_548_p1(20);
tmp_2_reg_832(21) <= tmp_2_fu_548_p1(21);
tmp_2_reg_832(22) <= tmp_2_fu_548_p1(22);
tmp_2_reg_832(23) <= tmp_2_fu_548_p1(23);
tmp_2_reg_832(24) <= tmp_2_fu_548_p1(24);
tmp_2_reg_832(25) <= tmp_2_fu_548_p1(25);
tmp_2_reg_832(26) <= tmp_2_fu_548_p1(26);
tmp_2_reg_832(27) <= tmp_2_fu_548_p1(27);
tmp_2_reg_832(28) <= tmp_2_fu_548_p1(28);
tmp_2_reg_832(29) <= tmp_2_fu_548_p1(29);
tmp_2_reg_832(30) <= tmp_2_fu_548_p1(30);
tmp_2_reg_832(31) <= tmp_2_fu_548_p1(31);
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_ST_st30_fsm_29 = ap_CS_fsm)) then
tmp_buckets_0_reg_947 <= grp_nfa_get_finals_fu_500_ap_return_0;
tmp_buckets_1_reg_952 <= grp_nfa_get_finals_fu_500_ap_return_1;
end if;
end if;
end process;
tmp_2_reg_832(63 downto 32) <= "00000000000000000000000000000000";
tmp_10_i_cast_reg_884(13 downto 8) <= "000000";
-- the next state (ap_NS_fsm) of the state machine. --
ap_NS_fsm_assign_proc : process (ap_start , ap_CS_fsm , nfa_forward_buckets_rsp_empty_n , sample_buffer_rsp_empty_n , stop_on_first_read_read_fu_150_p2 , tmp_3_fu_563_p2 , tmp_2_i_fu_580_p2 , tmp_2_1_i_fu_586_p2 , j_end_phi_fu_417_p4 , any_0_i_phi_fu_429_p4 , tmp_i_13_fu_534_p2 , or_cond_fu_743_p2)
begin
case ap_CS_fsm is
when ap_ST_st1_fsm_0 =>
if (not((ap_start = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st2_fsm_1;
else
ap_NS_fsm <= ap_ST_st1_fsm_0;
end if;
when ap_ST_st2_fsm_1 =>
if (not((ap_const_lv1_0 = tmp_i_13_fu_534_p2))) then
ap_NS_fsm <= ap_ST_st37_fsm_36;
else
ap_NS_fsm <= ap_ST_st3_fsm_2;
end if;
when ap_ST_st3_fsm_2 =>
ap_NS_fsm <= ap_ST_st4_fsm_3;
when ap_ST_st4_fsm_3 =>
ap_NS_fsm <= ap_ST_st5_fsm_4;
when ap_ST_st5_fsm_4 =>
ap_NS_fsm <= ap_ST_st6_fsm_5;
when ap_ST_st6_fsm_5 =>
ap_NS_fsm <= ap_ST_st7_fsm_6;
when ap_ST_st7_fsm_6 =>
ap_NS_fsm <= ap_ST_st8_fsm_7;
when ap_ST_st8_fsm_7 =>
ap_NS_fsm <= ap_ST_st9_fsm_8;
when ap_ST_st9_fsm_8 =>
ap_NS_fsm <= ap_ST_st10_fsm_9;
when ap_ST_st10_fsm_9 =>
if ((tmp_3_fu_563_p2 = ap_const_lv1_0)) then
ap_NS_fsm <= ap_ST_st25_fsm_24;
else
ap_NS_fsm <= ap_ST_st11_fsm_10;
end if;
when ap_ST_st11_fsm_10 =>
ap_NS_fsm <= ap_ST_st12_fsm_11;
when ap_ST_st12_fsm_11 =>
ap_NS_fsm <= ap_ST_st13_fsm_12;
when ap_ST_st13_fsm_12 =>
if ((not((sample_buffer_rsp_empty_n = ap_const_logic_0)) and not((ap_const_lv1_0 = tmp_2_i_fu_580_p2)) and not((ap_const_lv1_0 = tmp_2_1_i_fu_586_p2)))) then
ap_NS_fsm <= ap_ST_st15_fsm_14;
elsif ((not((sample_buffer_rsp_empty_n = ap_const_logic_0)) and ((ap_const_lv1_0 = tmp_2_i_fu_580_p2) or (ap_const_lv1_0 = tmp_2_1_i_fu_586_p2)))) then
ap_NS_fsm <= ap_ST_st14_fsm_13;
else
ap_NS_fsm <= ap_ST_st13_fsm_12;
end if;
when ap_ST_st14_fsm_13 =>
ap_NS_fsm <= ap_ST_st15_fsm_14;
when ap_ST_st15_fsm_14 =>
ap_NS_fsm <= ap_ST_st16_fsm_15;
when ap_ST_st16_fsm_15 =>
if ((not((ap_const_lv1_0 = j_end_phi_fu_417_p4)) and not((ap_const_lv1_0 = any_0_i_phi_fu_429_p4)))) then
ap_NS_fsm <= ap_ST_st10_fsm_9;
elsif ((not((ap_const_lv1_0 = j_end_phi_fu_417_p4)) and (ap_const_lv1_0 = any_0_i_phi_fu_429_p4))) then
ap_NS_fsm <= ap_ST_st32_fsm_31;
else
ap_NS_fsm <= ap_ST_st17_fsm_16;
end if;
when ap_ST_st17_fsm_16 =>
ap_NS_fsm <= ap_ST_st18_fsm_17;
when ap_ST_st18_fsm_17 =>
ap_NS_fsm <= ap_ST_st19_fsm_18;
when ap_ST_st19_fsm_18 =>
ap_NS_fsm <= ap_ST_st20_fsm_19;
when ap_ST_st20_fsm_19 =>
if (not((nfa_forward_buckets_rsp_empty_n = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st21_fsm_20;
else
ap_NS_fsm <= ap_ST_st20_fsm_19;
end if;
when ap_ST_st21_fsm_20 =>
ap_NS_fsm <= ap_ST_st22_fsm_21;
when ap_ST_st22_fsm_21 =>
ap_NS_fsm <= ap_ST_st23_fsm_22;
when ap_ST_st23_fsm_22 =>
if (not((nfa_forward_buckets_rsp_empty_n = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st24_fsm_23;
else
ap_NS_fsm <= ap_ST_st23_fsm_22;
end if;
when ap_ST_st24_fsm_23 =>
ap_NS_fsm <= ap_ST_st16_fsm_15;
when ap_ST_st25_fsm_24 =>
ap_NS_fsm <= ap_ST_st26_fsm_25;
when ap_ST_st26_fsm_25 =>
ap_NS_fsm <= ap_ST_st27_fsm_26;
when ap_ST_st27_fsm_26 =>
ap_NS_fsm <= ap_ST_st28_fsm_27;
when ap_ST_st28_fsm_27 =>
ap_NS_fsm <= ap_ST_st29_fsm_28;
when ap_ST_st29_fsm_28 =>
ap_NS_fsm <= ap_ST_st30_fsm_29;
when ap_ST_st30_fsm_29 =>
ap_NS_fsm <= ap_ST_st31_fsm_30;
when ap_ST_st31_fsm_30 =>
ap_NS_fsm <= ap_ST_st32_fsm_31;
when ap_ST_st32_fsm_31 =>
if ((not((stop_on_first_read_read_fu_150_p2 = ap_const_lv1_0)) and (ap_const_lv1_0 = or_cond_fu_743_p2))) then
ap_NS_fsm <= ap_ST_st37_fsm_36;
else
ap_NS_fsm <= ap_ST_st33_fsm_32;
end if;
when ap_ST_st33_fsm_32 =>
ap_NS_fsm <= ap_ST_st34_fsm_33;
when ap_ST_st34_fsm_33 =>
ap_NS_fsm <= ap_ST_st35_fsm_34;
when ap_ST_st35_fsm_34 =>
ap_NS_fsm <= ap_ST_st36_fsm_35;
when ap_ST_st36_fsm_35 =>
ap_NS_fsm <= ap_ST_st2_fsm_1;
when ap_ST_st37_fsm_36 =>
ap_NS_fsm <= ap_ST_st1_fsm_0;
when others =>
ap_NS_fsm <= "XXXXXX";
end case;
end process;
agg_result_bucket_index_0_lcssa4_i_cast_cast_fu_592_p1 <= std_logic_vector(resize(unsigned(agg_result_bucket_index_0_lcssa4_i_reg_296),2));
any_0_i_phi_fu_429_p4 <= any_0_i_reg_424;
-- ap_done assign process. --
ap_done_assign_proc : process(ap_CS_fsm)
begin
if ((ap_ST_st37_fsm_36 = ap_CS_fsm)) then
ap_done <= ap_const_logic_1;
else
ap_done <= ap_const_logic_0;
end if;
end process;
-- ap_idle assign process. --
ap_idle_assign_proc : process(ap_start, ap_CS_fsm)
begin
if ((not((ap_const_logic_1 = ap_start)) and (ap_ST_st1_fsm_0 = ap_CS_fsm))) then
ap_idle <= ap_const_logic_1;
else
ap_idle <= ap_const_logic_0;
end if;
end process;
-- ap_ready assign process. --
ap_ready_assign_proc : process(ap_CS_fsm)
begin
if ((ap_ST_st37_fsm_36 = ap_CS_fsm)) then
ap_ready <= ap_const_logic_1;
else
ap_ready <= ap_const_logic_0;
end if;
end process;
ap_return <= p_0_reg_448;
-- ap_sig_bdd_187 assign process. --
ap_sig_bdd_187_assign_proc : process(ap_CS_fsm, sample_buffer_rsp_empty_n)
begin
ap_sig_bdd_187 <= ((ap_ST_st13_fsm_12 = ap_CS_fsm) and not((sample_buffer_rsp_empty_n = ap_const_logic_0)));
end process;
-- ap_sig_bdd_370 assign process. --
ap_sig_bdd_370_assign_proc : process(tmp_2_i_fu_580_p2, tmp_2_1_i_fu_586_p2)
begin
ap_sig_bdd_370 <= (not((ap_const_lv1_0 = tmp_2_i_fu_580_p2)) and (ap_const_lv1_0 = tmp_2_1_i_fu_586_p2));
end process;
c_1_fu_748_p2 <= std_logic_vector(unsigned(c_load_reg_813) + unsigned(ap_const_lv32_1));
current_buckets_0_1_fu_721_p2 <= (next_buckets_0_reg_252 and tmp_buckets_0_reg_947);
current_buckets_1_1_fu_726_p2 <= (next_buckets_1_reg_242 and tmp_buckets_1_reg_952);
grp_bitset_next_fu_460_ap_ce <= ap_const_logic_1;
grp_bitset_next_fu_460_ap_start <= grp_bitset_next_fu_460_ap_start_ap_start_reg;
grp_bitset_next_fu_460_p_read <= next_buckets_1_reg_242;
grp_bitset_next_fu_460_r_bit <= j_bit1_reg_404;
grp_bitset_next_fu_460_r_bucket <= j_bucket1_reg_383;
grp_bitset_next_fu_460_r_bucket_index <= j_bucket_index1_reg_394;
grp_fu_638_ce <= ap_const_logic_1;
grp_fu_638_p0 <= grp_fu_638_p00(8 - 1 downto 0);
grp_fu_638_p00 <= std_logic_vector(resize(unsigned(nfa_symbols),14));
grp_fu_638_p1 <= grp_fu_638_p10(6 - 1 downto 0);
grp_fu_638_p10 <= std_logic_vector(resize(unsigned(state_fu_624_p2),14));
grp_nfa_get_finals_fu_500_ap_ce <= ap_const_logic_1;
grp_nfa_get_finals_fu_500_ap_start <= grp_nfa_get_finals_fu_500_ap_start_ap_start_reg;
grp_nfa_get_finals_fu_500_nfa_finals_buckets_datain <= nfa_finals_buckets_datain;
grp_nfa_get_finals_fu_500_nfa_finals_buckets_req_full_n <= nfa_finals_buckets_req_full_n;
grp_nfa_get_finals_fu_500_nfa_finals_buckets_rsp_empty_n <= nfa_finals_buckets_rsp_empty_n;
grp_nfa_get_initials_fu_494_ap_ce <= ap_const_logic_1;
grp_nfa_get_initials_fu_494_ap_start <= grp_nfa_get_initials_fu_494_ap_start_ap_start_reg;
grp_nfa_get_initials_fu_494_nfa_initials_buckets_datain <= nfa_initials_buckets_datain;
grp_nfa_get_initials_fu_494_nfa_initials_buckets_req_full_n <= nfa_initials_buckets_req_full_n;
grp_nfa_get_initials_fu_494_nfa_initials_buckets_rsp_empty_n <= nfa_initials_buckets_rsp_empty_n;
grp_sample_iterator_get_offset_fu_482_ap_ce <= ap_const_logic_1;
grp_sample_iterator_get_offset_fu_482_ap_start <= grp_sample_iterator_get_offset_fu_482_ap_start_ap_start_reg;
grp_sample_iterator_get_offset_fu_482_i_index <= i_index_reg_222;
grp_sample_iterator_get_offset_fu_482_i_sample <= i_sample_reg_232;
grp_sample_iterator_get_offset_fu_482_indices_datain <= indices_datain;
grp_sample_iterator_get_offset_fu_482_indices_req_full_n <= indices_req_full_n;
grp_sample_iterator_get_offset_fu_482_indices_rsp_empty_n <= indices_rsp_empty_n;
grp_sample_iterator_get_offset_fu_482_sample_buffer_size <= sample_buffer_length;
grp_sample_iterator_get_offset_fu_482_sample_length <= sample_length;
grp_sample_iterator_next_fu_472_ap_ce <= ap_const_logic_1;
grp_sample_iterator_next_fu_472_ap_start <= grp_sample_iterator_next_fu_472_ap_start_ap_start_reg;
grp_sample_iterator_next_fu_472_i_index <= i_index_reg_222;
grp_sample_iterator_next_fu_472_i_sample <= i_sample_reg_232;
grp_sample_iterator_next_fu_472_indices_datain <= indices_datain;
grp_sample_iterator_next_fu_472_indices_req_full_n <= indices_req_full_n;
grp_sample_iterator_next_fu_472_indices_rsp_empty_n <= indices_rsp_empty_n;
i_fu_568_p2 <= std_logic_vector(unsigned(i_0_i_reg_262) + unsigned(ap_const_lv16_1));
-- indices_address assign process. --
indices_address_assign_proc : process(ap_CS_fsm, grp_sample_iterator_next_fu_472_indices_address, grp_sample_iterator_get_offset_fu_482_indices_address)
begin
if (((ap_ST_st8_fsm_7 = ap_CS_fsm) or (ap_ST_st9_fsm_8 = ap_CS_fsm) or (ap_ST_st5_fsm_4 = ap_CS_fsm) or (ap_ST_st6_fsm_5 = ap_CS_fsm) or (ap_ST_st7_fsm_6 = ap_CS_fsm))) then
indices_address <= grp_sample_iterator_get_offset_fu_482_indices_address;
elsif (((ap_ST_st36_fsm_35 = ap_CS_fsm) or (ap_ST_st33_fsm_32 = ap_CS_fsm) or (ap_ST_st34_fsm_33 = ap_CS_fsm) or (ap_ST_st35_fsm_34 = ap_CS_fsm))) then
indices_address <= grp_sample_iterator_next_fu_472_indices_address;
else
indices_address <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
-- indices_dataout assign process. --
indices_dataout_assign_proc : process(ap_CS_fsm, grp_sample_iterator_next_fu_472_indices_dataout, grp_sample_iterator_get_offset_fu_482_indices_dataout)
begin
if (((ap_ST_st8_fsm_7 = ap_CS_fsm) or (ap_ST_st9_fsm_8 = ap_CS_fsm) or (ap_ST_st5_fsm_4 = ap_CS_fsm) or (ap_ST_st6_fsm_5 = ap_CS_fsm) or (ap_ST_st7_fsm_6 = ap_CS_fsm))) then
indices_dataout <= grp_sample_iterator_get_offset_fu_482_indices_dataout;
elsif (((ap_ST_st36_fsm_35 = ap_CS_fsm) or (ap_ST_st33_fsm_32 = ap_CS_fsm) or (ap_ST_st34_fsm_33 = ap_CS_fsm) or (ap_ST_st35_fsm_34 = ap_CS_fsm))) then
indices_dataout <= grp_sample_iterator_next_fu_472_indices_dataout;
else
indices_dataout <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
-- indices_req_din assign process. --
indices_req_din_assign_proc : process(ap_CS_fsm, grp_sample_iterator_next_fu_472_indices_req_din, grp_sample_iterator_get_offset_fu_482_indices_req_din)
begin
if (((ap_ST_st8_fsm_7 = ap_CS_fsm) or (ap_ST_st9_fsm_8 = ap_CS_fsm) or (ap_ST_st5_fsm_4 = ap_CS_fsm) or (ap_ST_st6_fsm_5 = ap_CS_fsm) or (ap_ST_st7_fsm_6 = ap_CS_fsm))) then
indices_req_din <= grp_sample_iterator_get_offset_fu_482_indices_req_din;
elsif (((ap_ST_st36_fsm_35 = ap_CS_fsm) or (ap_ST_st33_fsm_32 = ap_CS_fsm) or (ap_ST_st34_fsm_33 = ap_CS_fsm) or (ap_ST_st35_fsm_34 = ap_CS_fsm))) then
indices_req_din <= grp_sample_iterator_next_fu_472_indices_req_din;
else
indices_req_din <= 'X';
end if;
end process;
-- indices_req_write assign process. --
indices_req_write_assign_proc : process(ap_CS_fsm, grp_sample_iterator_next_fu_472_indices_req_write, grp_sample_iterator_get_offset_fu_482_indices_req_write)
begin
if (((ap_ST_st8_fsm_7 = ap_CS_fsm) or (ap_ST_st9_fsm_8 = ap_CS_fsm) or (ap_ST_st5_fsm_4 = ap_CS_fsm) or (ap_ST_st6_fsm_5 = ap_CS_fsm) or (ap_ST_st7_fsm_6 = ap_CS_fsm))) then
indices_req_write <= grp_sample_iterator_get_offset_fu_482_indices_req_write;
elsif (((ap_ST_st36_fsm_35 = ap_CS_fsm) or (ap_ST_st33_fsm_32 = ap_CS_fsm) or (ap_ST_st34_fsm_33 = ap_CS_fsm) or (ap_ST_st35_fsm_34 = ap_CS_fsm))) then
indices_req_write <= grp_sample_iterator_next_fu_472_indices_req_write;
else
indices_req_write <= 'X';
end if;
end process;
-- indices_rsp_read assign process. --
indices_rsp_read_assign_proc : process(ap_CS_fsm, grp_sample_iterator_next_fu_472_indices_rsp_read, grp_sample_iterator_get_offset_fu_482_indices_rsp_read)
begin
if (((ap_ST_st8_fsm_7 = ap_CS_fsm) or (ap_ST_st9_fsm_8 = ap_CS_fsm) or (ap_ST_st5_fsm_4 = ap_CS_fsm) or (ap_ST_st6_fsm_5 = ap_CS_fsm) or (ap_ST_st7_fsm_6 = ap_CS_fsm))) then
indices_rsp_read <= grp_sample_iterator_get_offset_fu_482_indices_rsp_read;
elsif (((ap_ST_st36_fsm_35 = ap_CS_fsm) or (ap_ST_st33_fsm_32 = ap_CS_fsm) or (ap_ST_st34_fsm_33 = ap_CS_fsm) or (ap_ST_st35_fsm_34 = ap_CS_fsm))) then
indices_rsp_read <= grp_sample_iterator_next_fu_472_indices_rsp_read;
else
indices_rsp_read <= 'X';
end if;
end process;
-- indices_size assign process. --
indices_size_assign_proc : process(ap_CS_fsm, grp_sample_iterator_next_fu_472_indices_size, grp_sample_iterator_get_offset_fu_482_indices_size)
begin
if (((ap_ST_st8_fsm_7 = ap_CS_fsm) or (ap_ST_st9_fsm_8 = ap_CS_fsm) or (ap_ST_st5_fsm_4 = ap_CS_fsm) or (ap_ST_st6_fsm_5 = ap_CS_fsm) or (ap_ST_st7_fsm_6 = ap_CS_fsm))) then
indices_size <= grp_sample_iterator_get_offset_fu_482_indices_size;
elsif (((ap_ST_st36_fsm_35 = ap_CS_fsm) or (ap_ST_st33_fsm_32 = ap_CS_fsm) or (ap_ST_st34_fsm_33 = ap_CS_fsm) or (ap_ST_st35_fsm_34 = ap_CS_fsm))) then
indices_size <= grp_sample_iterator_next_fu_472_indices_size;
else
indices_size <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
j_bit1_ph_cast_fu_601_p1 <= std_logic_vector(resize(unsigned(j_bit1_ph_phi_fu_337_p4),8));
-- j_bit1_ph_phi_fu_337_p4 assign process. --
j_bit1_ph_phi_fu_337_p4_assign_proc : process(ap_CS_fsm, tmp_2_i_reg_861, tmp_2_1_i_reg_865, r_bit_reg_869, j_bit1_ph_reg_333)
begin
if (((ap_ST_st15_fsm_14 = ap_CS_fsm) and ((ap_const_lv1_0 = tmp_2_i_reg_861) or (ap_const_lv1_0 = tmp_2_1_i_reg_865)))) then
j_bit1_ph_phi_fu_337_p4 <= r_bit_reg_869;
else
j_bit1_ph_phi_fu_337_p4 <= j_bit1_ph_reg_333;
end if;
end process;
-- j_bucket1_ph_phi_fu_313_p4 assign process. --
j_bucket1_ph_phi_fu_313_p4_assign_proc : process(ap_CS_fsm, tmp_2_i_reg_861, tmp_2_1_i_reg_865, bus_assign_reg_284, j_bucket1_ph_reg_309)
begin
if (((ap_ST_st15_fsm_14 = ap_CS_fsm) and ((ap_const_lv1_0 = tmp_2_i_reg_861) or (ap_const_lv1_0 = tmp_2_1_i_reg_865)))) then
j_bucket1_ph_phi_fu_313_p4 <= bus_assign_reg_284;
else
j_bucket1_ph_phi_fu_313_p4 <= j_bucket1_ph_reg_309;
end if;
end process;
j_bucket_index1_ph_cast_fu_597_p1 <= std_logic_vector(resize(unsigned(j_bucket_index1_ph_phi_fu_326_p4),8));
-- j_bucket_index1_ph_phi_fu_326_p4 assign process. --
j_bucket_index1_ph_phi_fu_326_p4_assign_proc : process(ap_CS_fsm, tmp_2_i_reg_861, tmp_2_1_i_reg_865, j_bucket_index1_ph_reg_322, agg_result_bucket_index_0_lcssa4_i_cast_cast_fu_592_p1)
begin
if (((ap_ST_st15_fsm_14 = ap_CS_fsm) and ((ap_const_lv1_0 = tmp_2_i_reg_861) or (ap_const_lv1_0 = tmp_2_1_i_reg_865)))) then
j_bucket_index1_ph_phi_fu_326_p4 <= agg_result_bucket_index_0_lcssa4_i_cast_cast_fu_592_p1;
else
j_bucket_index1_ph_phi_fu_326_p4 <= j_bucket_index1_ph_reg_322;
end if;
end process;
-- j_end_ph_phi_fu_348_p4 assign process. --
j_end_ph_phi_fu_348_p4_assign_proc : process(ap_CS_fsm, tmp_2_i_reg_861, tmp_2_1_i_reg_865, j_end_ph_reg_344)
begin
if (((ap_ST_st15_fsm_14 = ap_CS_fsm) and ((ap_const_lv1_0 = tmp_2_i_reg_861) or (ap_const_lv1_0 = tmp_2_1_i_reg_865)))) then
j_end_ph_phi_fu_348_p4 <= ap_const_lv1_0;
else
j_end_ph_phi_fu_348_p4 <= j_end_ph_reg_344;
end if;
end process;
j_end_phi_fu_417_p4 <= j_end_reg_414;
next_buckets_0_1_fu_701_p2 <= (reg_512 or tmp_buckets_0_3_reg_370);
next_buckets_1_1_fu_707_p2 <= (reg_512 or tmp_buckets_1_3_reg_357);
nfa_finals_buckets_address <= grp_nfa_get_finals_fu_500_nfa_finals_buckets_address;
nfa_finals_buckets_dataout <= grp_nfa_get_finals_fu_500_nfa_finals_buckets_dataout;
nfa_finals_buckets_req_din <= grp_nfa_get_finals_fu_500_nfa_finals_buckets_req_din;
nfa_finals_buckets_req_write <= grp_nfa_get_finals_fu_500_nfa_finals_buckets_req_write;
nfa_finals_buckets_rsp_read <= grp_nfa_get_finals_fu_500_nfa_finals_buckets_rsp_read;
nfa_finals_buckets_size <= grp_nfa_get_finals_fu_500_nfa_finals_buckets_size;
-- nfa_forward_buckets_address assign process. --
nfa_forward_buckets_address_assign_proc : process(ap_CS_fsm, tmp_12_i_cast_fu_656_p1, tmp_13_i_cast_fu_690_p1)
begin
if ((ap_ST_st21_fsm_20 = ap_CS_fsm)) then
nfa_forward_buckets_address <= tmp_13_i_cast_fu_690_p1(32 - 1 downto 0);
elsif ((ap_ST_st18_fsm_17 = ap_CS_fsm)) then
nfa_forward_buckets_address <= tmp_12_i_cast_fu_656_p1(32 - 1 downto 0);
else
nfa_forward_buckets_address <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
nfa_forward_buckets_dataout <= ap_const_lv32_0;
nfa_forward_buckets_req_din <= ap_const_logic_0;
-- nfa_forward_buckets_req_write assign process. --
nfa_forward_buckets_req_write_assign_proc : process(ap_CS_fsm)
begin
if (((ap_ST_st18_fsm_17 = ap_CS_fsm) or (ap_ST_st21_fsm_20 = ap_CS_fsm))) then
nfa_forward_buckets_req_write <= ap_const_logic_1;
else
nfa_forward_buckets_req_write <= ap_const_logic_0;
end if;
end process;
-- nfa_forward_buckets_rsp_read assign process. --
nfa_forward_buckets_rsp_read_assign_proc : process(ap_CS_fsm, nfa_forward_buckets_rsp_empty_n)
begin
if ((((ap_ST_st20_fsm_19 = ap_CS_fsm) and not((nfa_forward_buckets_rsp_empty_n = ap_const_logic_0))) or (not((nfa_forward_buckets_rsp_empty_n = ap_const_logic_0)) and (ap_ST_st23_fsm_22 = ap_CS_fsm)))) then
nfa_forward_buckets_rsp_read <= ap_const_logic_1;
else
nfa_forward_buckets_rsp_read <= ap_const_logic_0;
end if;
end process;
nfa_forward_buckets_size <= ap_const_lv32_1;
nfa_initials_buckets_address <= grp_nfa_get_initials_fu_494_nfa_initials_buckets_address;
nfa_initials_buckets_dataout <= grp_nfa_get_initials_fu_494_nfa_initials_buckets_dataout;
nfa_initials_buckets_req_din <= grp_nfa_get_initials_fu_494_nfa_initials_buckets_req_din;
nfa_initials_buckets_req_write <= grp_nfa_get_initials_fu_494_nfa_initials_buckets_req_write;
nfa_initials_buckets_rsp_read <= grp_nfa_get_initials_fu_494_nfa_initials_buckets_rsp_read;
nfa_initials_buckets_size <= grp_nfa_get_initials_fu_494_nfa_initials_buckets_size;
or_cond_fu_743_p2 <= (r_reg_437 xor accept);
p_rec_i_fu_574_p2 <= std_logic_vector(unsigned(p_01_rec_i_reg_273) + unsigned(ap_const_lv64_1));
r_bit_p_bsf32_hw_fu_506_bus_r <= bus_assign_reg_284;
sample_buffer_address <= sample_buffer_addr_reg_837;
sample_buffer_dataout <= ap_const_lv8_0;
sample_buffer_req_din <= ap_const_logic_0;
-- sample_buffer_req_write assign process. --
sample_buffer_req_write_assign_proc : process(ap_CS_fsm)
begin
if ((ap_ST_st11_fsm_10 = ap_CS_fsm)) then
sample_buffer_req_write <= ap_const_logic_1;
else
sample_buffer_req_write <= ap_const_logic_0;
end if;
end process;
-- sample_buffer_rsp_read assign process. --
sample_buffer_rsp_read_assign_proc : process(ap_CS_fsm, sample_buffer_rsp_empty_n)
begin
if (((ap_ST_st13_fsm_12 = ap_CS_fsm) and not((sample_buffer_rsp_empty_n = ap_const_logic_0)))) then
sample_buffer_rsp_read <= ap_const_logic_1;
else
sample_buffer_rsp_read <= ap_const_logic_0;
end if;
end process;
sample_buffer_size <= ap_const_lv32_1;
state_fu_624_p2 <= std_logic_vector(unsigned(tmp_i1_fu_612_p3) + unsigned(tmp_8_fu_620_p1));
stop_on_first_read_read_fu_150_p2 <= stop_on_first;
sum_fu_552_p2 <= std_logic_vector(unsigned(p_01_rec_i_reg_273) + unsigned(tmp_2_reg_832));
tmp_10_i_cast_fu_605_p1 <= std_logic_vector(resize(unsigned(sym_reg_856),14));
tmp_11_i_fu_644_p2 <= std_logic_vector(unsigned(grp_fu_638_p2) + unsigned(tmp_10_i_cast_reg_884));
tmp_12_i_cast_fu_656_p1 <= std_logic_vector(resize(unsigned(tmp_12_i_fu_649_p3),64));
tmp_12_i_fu_649_p3 <= (tmp_11_i_reg_899 & ap_const_lv1_0);
tmp_13_i_cast_fu_690_p1 <= std_logic_vector(resize(unsigned(tmp_13_i_fu_683_p3),64));
tmp_13_i_fu_683_p3 <= (tmp_11_i_reg_899 & ap_const_lv1_1);
tmp_1_fu_731_p2 <= (current_buckets_1_1_fu_726_p2 or current_buckets_0_1_fu_721_p2);
tmp_2_1_i_fu_586_p2 <= "1" when (next_buckets_1_reg_242 = ap_const_lv32_0) else "0";
tmp_2_fu_548_p1 <= std_logic_vector(resize(unsigned(grp_sample_iterator_get_offset_fu_482_ap_return),64));
tmp_2_i_fu_580_p2 <= "1" when (next_buckets_0_reg_252 = ap_const_lv32_0) else "0";
tmp_3_fu_563_p2 <= "1" when (unsigned(i_0_i_reg_262) < unsigned(sample_length)) else "0";
tmp_5_fu_737_p2 <= "0" when (tmp_1_fu_731_p2 = ap_const_lv32_0) else "1";
tmp_6_fu_608_p1 <= j_bucket_index1_reg_394(1 - 1 downto 0);
tmp_8_fu_620_p1 <= j_bit1_reg_404(6 - 1 downto 0);
tmp_i1_fu_612_p3 <= (tmp_6_fu_608_p1 & ap_const_lv5_0);
tmp_i_12_fu_529_p2 <= "1" when (i_index_reg_222 = end_index) else "0";
tmp_i_13_fu_534_p2 <= (tmp_i_fu_524_p2 and tmp_i_12_fu_529_p2);
tmp_i_fu_524_p2 <= "1" when (i_sample_reg_232 = end_sample) else "0";
end behav;
| lgpl-3.0 | ab0046b70b1caa0efa075f7192b66246 | 0.60151 | 2.721605 | false | false | false | false |
TWW12/lzw | final_project_sim/lzw/lzw.cache/ip/04a7882d00f7897d/bram_1024_3_sim_netlist.vhdl | 1 | 52,972 | -- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1756540 Mon Jan 23 19:11:23 MST 2017
-- Date : Tue Apr 18 23:18:54 2017
-- Host : DESKTOP-I9J3TQJ running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
-- decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ bram_1024_3_sim_netlist.vhdl
-- Design : bram_1024_3
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7z020clg484-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper_init is
port (
douta : out STD_LOGIC_VECTOR ( 19 downto 0 );
clka : in STD_LOGIC;
ena : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 9 downto 0 );
dina : in STD_LOGIC_VECTOR ( 19 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 )
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper_init;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper_init is
signal \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_21\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_22\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_23\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_29\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_30\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_31\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_37\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_38\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_39\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_45\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_46\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_47\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_85\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_86\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_87\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_88\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute CLOCK_DOMAINS : string;
attribute CLOCK_DOMAINS of \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\ : label is "COMMON";
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 1,
DOB_REG => 0,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_00 => X"000001000000001C0000001800000014000000100000000C0000000800000004",
INIT_01 => X"000002000000011C0000011800000114000001100000010C0000010800000104",
INIT_02 => X"000003000000021C0000021800000214000002100000020C0000020800000204",
INIT_03 => X"000004000000031C0000031800000314000003100000030C0000030800000304",
INIT_04 => X"000005000000041C0000041800000414000004100000040C0000040800000404",
INIT_05 => X"000006000000051C0000051800000514000005100000050C0000050800000504",
INIT_06 => X"000007000000061C0000061800000614000006100000060C0000060800000604",
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INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_45 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_46 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_47 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_48 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_49 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_50 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_51 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_52 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_53 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_54 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_55 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_56 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_57 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_58 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_59 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_60 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_61 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_62 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_63 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_64 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_65 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_66 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_67 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_68 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_69 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_70 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_71 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_72 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_73 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_74 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "PERFORMANCE",
READ_WIDTH_A => 36,
READ_WIDTH_B => 36,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 36,
WRITE_WIDTH_B => 36
)
port map (
ADDRARDADDR(15) => '1',
ADDRARDADDR(14 downto 5) => addra(9 downto 0),
ADDRARDADDR(4 downto 0) => B"11111",
ADDRBWRADDR(15 downto 0) => B"0000000000000000",
CASCADEINA => '0',
CASCADEINB => '0',
CASCADEOUTA => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => clka,
CLKBWRCLK => clka,
DBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\,
DIADI(31 downto 29) => B"000",
DIADI(28 downto 24) => dina(19 downto 15),
DIADI(23 downto 21) => B"000",
DIADI(20 downto 16) => dina(14 downto 10),
DIADI(15 downto 13) => B"000",
DIADI(12 downto 8) => dina(9 downto 5),
DIADI(7 downto 5) => B"000",
DIADI(4 downto 0) => dina(4 downto 0),
DIBDI(31 downto 0) => B"00000000000000000000000000000000",
DIPADIP(3 downto 0) => B"0000",
DIPBDIP(3 downto 0) => B"0000",
DOADO(31) => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_21\,
DOADO(30) => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_22\,
DOADO(29) => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_23\,
DOADO(28 downto 24) => douta(19 downto 15),
DOADO(23) => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_29\,
DOADO(22) => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_30\,
DOADO(21) => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_31\,
DOADO(20 downto 16) => douta(14 downto 10),
DOADO(15) => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_37\,
DOADO(14) => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_38\,
DOADO(13) => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_39\,
DOADO(12 downto 8) => douta(9 downto 5),
DOADO(7) => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_45\,
DOADO(6) => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_46\,
DOADO(5) => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_47\,
DOADO(4 downto 0) => douta(4 downto 0),
DOBDO(31 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\(31 downto 0),
DOPADOP(3) => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_85\,
DOPADOP(2) => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_86\,
DOPADOP(1) => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_87\,
DOPADOP(0) => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_88\,
DOPBDOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\(3 downto 0),
ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => ena,
ENBWREN => '0',
INJECTDBITERR => '0',
INJECTSBITERR => '0',
RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => ena,
REGCEB => '0',
RSTRAMARSTRAM => '0',
RSTRAMB => '0',
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\,
WEA(3) => wea(0),
WEA(2) => wea(0),
WEA(1) => wea(0),
WEA(0) => wea(0),
WEBWE(7 downto 0) => B"00000000"
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width is
port (
douta : out STD_LOGIC_VECTOR ( 19 downto 0 );
clka : in STD_LOGIC;
ena : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 9 downto 0 );
dina : in STD_LOGIC_VECTOR ( 19 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 )
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width is
begin
\prim_init.ram\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper_init
port map (
addra(9 downto 0) => addra(9 downto 0),
clka => clka,
dina(19 downto 0) => dina(19 downto 0),
douta(19 downto 0) => douta(19 downto 0),
ena => ena,
wea(0) => wea(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_generic_cstr is
port (
douta : out STD_LOGIC_VECTOR ( 19 downto 0 );
clka : in STD_LOGIC;
ena : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 9 downto 0 );
dina : in STD_LOGIC_VECTOR ( 19 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 )
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_generic_cstr;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_generic_cstr is
begin
\ramloop[0].ram.r\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width
port map (
addra(9 downto 0) => addra(9 downto 0),
clka => clka,
dina(19 downto 0) => dina(19 downto 0),
douta(19 downto 0) => douta(19 downto 0),
ena => ena,
wea(0) => wea(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_top is
port (
douta : out STD_LOGIC_VECTOR ( 19 downto 0 );
clka : in STD_LOGIC;
ena : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 9 downto 0 );
dina : in STD_LOGIC_VECTOR ( 19 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 )
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_top;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_top is
begin
\valid.cstr\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_generic_cstr
port map (
addra(9 downto 0) => addra(9 downto 0),
clka => clka,
dina(19 downto 0) => dina(19 downto 0),
douta(19 downto 0) => douta(19 downto 0),
ena => ena,
wea(0) => wea(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5_synth is
port (
douta : out STD_LOGIC_VECTOR ( 19 downto 0 );
clka : in STD_LOGIC;
ena : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 9 downto 0 );
dina : in STD_LOGIC_VECTOR ( 19 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 )
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5_synth;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5_synth is
begin
\gnbram.gnativebmg.native_blk_mem_gen\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_top
port map (
addra(9 downto 0) => addra(9 downto 0),
clka => clka,
dina(19 downto 0) => dina(19 downto 0),
douta(19 downto 0) => douta(19 downto 0),
ena => ena,
wea(0) => wea(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 is
port (
clka : in STD_LOGIC;
rsta : in STD_LOGIC;
ena : in STD_LOGIC;
regcea : in STD_LOGIC;
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
addra : in STD_LOGIC_VECTOR ( 9 downto 0 );
dina : in STD_LOGIC_VECTOR ( 19 downto 0 );
douta : out STD_LOGIC_VECTOR ( 19 downto 0 );
clkb : in STD_LOGIC;
rstb : in STD_LOGIC;
enb : in STD_LOGIC;
regceb : in STD_LOGIC;
web : in STD_LOGIC_VECTOR ( 0 to 0 );
addrb : in STD_LOGIC_VECTOR ( 9 downto 0 );
dinb : in STD_LOGIC_VECTOR ( 19 downto 0 );
doutb : out STD_LOGIC_VECTOR ( 19 downto 0 );
injectsbiterr : in STD_LOGIC;
injectdbiterr : in STD_LOGIC;
eccpipece : in STD_LOGIC;
sbiterr : out STD_LOGIC;
dbiterr : out STD_LOGIC;
rdaddrecc : out STD_LOGIC_VECTOR ( 9 downto 0 );
sleep : in STD_LOGIC;
deepsleep : in STD_LOGIC;
shutdown : in STD_LOGIC;
rsta_busy : out STD_LOGIC;
rstb_busy : out STD_LOGIC;
s_aclk : in STD_LOGIC;
s_aresetn : in STD_LOGIC;
s_axi_awid : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_awready : out STD_LOGIC;
s_axi_wdata : in STD_LOGIC_VECTOR ( 19 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_wlast : in STD_LOGIC;
s_axi_wvalid : in STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_bid : out STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_bvalid : out STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_arid : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arvalid : in STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_rid : out STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_rdata : out STD_LOGIC_VECTOR ( 19 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rlast : out STD_LOGIC;
s_axi_rvalid : out STD_LOGIC;
s_axi_rready : in STD_LOGIC;
s_axi_injectsbiterr : in STD_LOGIC;
s_axi_injectdbiterr : in STD_LOGIC;
s_axi_sbiterr : out STD_LOGIC;
s_axi_dbiterr : out STD_LOGIC;
s_axi_rdaddrecc : out STD_LOGIC_VECTOR ( 9 downto 0 )
);
attribute C_ADDRA_WIDTH : integer;
attribute C_ADDRA_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is 10;
attribute C_ADDRB_WIDTH : integer;
attribute C_ADDRB_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is 10;
attribute C_ALGORITHM : integer;
attribute C_ALGORITHM of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is 1;
attribute C_AXI_ID_WIDTH : integer;
attribute C_AXI_ID_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is 4;
attribute C_AXI_SLAVE_TYPE : integer;
attribute C_AXI_SLAVE_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_AXI_TYPE : integer;
attribute C_AXI_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is 1;
attribute C_BYTE_SIZE : integer;
attribute C_BYTE_SIZE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is 9;
attribute C_COMMON_CLK : integer;
attribute C_COMMON_CLK of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_COUNT_18K_BRAM : string;
attribute C_COUNT_18K_BRAM of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is "0";
attribute C_COUNT_36K_BRAM : string;
attribute C_COUNT_36K_BRAM of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is "1";
attribute C_CTRL_ECC_ALGO : string;
attribute C_CTRL_ECC_ALGO of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is "NONE";
attribute C_DEFAULT_DATA : string;
attribute C_DEFAULT_DATA of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is "0";
attribute C_DISABLE_WARN_BHV_COLL : integer;
attribute C_DISABLE_WARN_BHV_COLL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_DISABLE_WARN_BHV_RANGE : integer;
attribute C_DISABLE_WARN_BHV_RANGE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_ELABORATION_DIR : string;
attribute C_ELABORATION_DIR of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is "./";
attribute C_ENABLE_32BIT_ADDRESS : integer;
attribute C_ENABLE_32BIT_ADDRESS of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_EN_DEEPSLEEP_PIN : integer;
attribute C_EN_DEEPSLEEP_PIN of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_EN_ECC_PIPE : integer;
attribute C_EN_ECC_PIPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_EN_RDADDRA_CHG : integer;
attribute C_EN_RDADDRA_CHG of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_EN_RDADDRB_CHG : integer;
attribute C_EN_RDADDRB_CHG of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_EN_SAFETY_CKT : integer;
attribute C_EN_SAFETY_CKT of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_EN_SHUTDOWN_PIN : integer;
attribute C_EN_SHUTDOWN_PIN of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_EN_SLEEP_PIN : integer;
attribute C_EN_SLEEP_PIN of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_EST_POWER_SUMMARY : string;
attribute C_EST_POWER_SUMMARY of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is "Estimated Power for IP : 2.74095 mW";
attribute C_FAMILY : string;
attribute C_FAMILY of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is "zynq";
attribute C_HAS_AXI_ID : integer;
attribute C_HAS_AXI_ID of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_HAS_ENA : integer;
attribute C_HAS_ENA of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is 1;
attribute C_HAS_ENB : integer;
attribute C_HAS_ENB of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_HAS_INJECTERR : integer;
attribute C_HAS_INJECTERR of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_HAS_MEM_OUTPUT_REGS_A : integer;
attribute C_HAS_MEM_OUTPUT_REGS_A of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is 1;
attribute C_HAS_MEM_OUTPUT_REGS_B : integer;
attribute C_HAS_MEM_OUTPUT_REGS_B of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_HAS_MUX_OUTPUT_REGS_A : integer;
attribute C_HAS_MUX_OUTPUT_REGS_A of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_HAS_MUX_OUTPUT_REGS_B : integer;
attribute C_HAS_MUX_OUTPUT_REGS_B of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_HAS_REGCEA : integer;
attribute C_HAS_REGCEA of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_HAS_REGCEB : integer;
attribute C_HAS_REGCEB of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_HAS_RSTA : integer;
attribute C_HAS_RSTA of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_HAS_RSTB : integer;
attribute C_HAS_RSTB of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_HAS_SOFTECC_INPUT_REGS_A : integer;
attribute C_HAS_SOFTECC_INPUT_REGS_A of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_HAS_SOFTECC_OUTPUT_REGS_B : integer;
attribute C_HAS_SOFTECC_OUTPUT_REGS_B of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_INITA_VAL : string;
attribute C_INITA_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is "0";
attribute C_INITB_VAL : string;
attribute C_INITB_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is "0";
attribute C_INIT_FILE : string;
attribute C_INIT_FILE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is "bram_1024_3.mem";
attribute C_INIT_FILE_NAME : string;
attribute C_INIT_FILE_NAME of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is "bram_1024_3.mif";
attribute C_INTERFACE_TYPE : integer;
attribute C_INTERFACE_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_LOAD_INIT_FILE : integer;
attribute C_LOAD_INIT_FILE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is 1;
attribute C_MEM_TYPE : integer;
attribute C_MEM_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_MUX_PIPELINE_STAGES : integer;
attribute C_MUX_PIPELINE_STAGES of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_PRIM_TYPE : integer;
attribute C_PRIM_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is 1;
attribute C_READ_DEPTH_A : integer;
attribute C_READ_DEPTH_A of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is 1024;
attribute C_READ_DEPTH_B : integer;
attribute C_READ_DEPTH_B of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is 1024;
attribute C_READ_WIDTH_A : integer;
attribute C_READ_WIDTH_A of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is 20;
attribute C_READ_WIDTH_B : integer;
attribute C_READ_WIDTH_B of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is 20;
attribute C_RSTRAM_A : integer;
attribute C_RSTRAM_A of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_RSTRAM_B : integer;
attribute C_RSTRAM_B of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_RST_PRIORITY_A : string;
attribute C_RST_PRIORITY_A of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is "CE";
attribute C_RST_PRIORITY_B : string;
attribute C_RST_PRIORITY_B of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is "CE";
attribute C_SIM_COLLISION_CHECK : string;
attribute C_SIM_COLLISION_CHECK of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is "ALL";
attribute C_USE_BRAM_BLOCK : integer;
attribute C_USE_BRAM_BLOCK of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_USE_BYTE_WEA : integer;
attribute C_USE_BYTE_WEA of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_USE_BYTE_WEB : integer;
attribute C_USE_BYTE_WEB of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_USE_DEFAULT_DATA : integer;
attribute C_USE_DEFAULT_DATA of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_USE_ECC : integer;
attribute C_USE_ECC of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_USE_SOFTECC : integer;
attribute C_USE_SOFTECC of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_USE_URAM : integer;
attribute C_USE_URAM of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_WEA_WIDTH : integer;
attribute C_WEA_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is 1;
attribute C_WEB_WIDTH : integer;
attribute C_WEB_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is 1;
attribute C_WRITE_DEPTH_A : integer;
attribute C_WRITE_DEPTH_A of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is 1024;
attribute C_WRITE_DEPTH_B : integer;
attribute C_WRITE_DEPTH_B of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is 1024;
attribute C_WRITE_MODE_A : string;
attribute C_WRITE_MODE_A of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is "WRITE_FIRST";
attribute C_WRITE_MODE_B : string;
attribute C_WRITE_MODE_B of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is "WRITE_FIRST";
attribute C_WRITE_WIDTH_A : integer;
attribute C_WRITE_WIDTH_A of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is 20;
attribute C_WRITE_WIDTH_B : integer;
attribute C_WRITE_WIDTH_B of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is 20;
attribute C_XDEVICEFAMILY : string;
attribute C_XDEVICEFAMILY of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is "zynq";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is "yes";
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 is
signal \<const0>\ : STD_LOGIC;
begin
dbiterr <= \<const0>\;
doutb(19) <= \<const0>\;
doutb(18) <= \<const0>\;
doutb(17) <= \<const0>\;
doutb(16) <= \<const0>\;
doutb(15) <= \<const0>\;
doutb(14) <= \<const0>\;
doutb(13) <= \<const0>\;
doutb(12) <= \<const0>\;
doutb(11) <= \<const0>\;
doutb(10) <= \<const0>\;
doutb(9) <= \<const0>\;
doutb(8) <= \<const0>\;
doutb(7) <= \<const0>\;
doutb(6) <= \<const0>\;
doutb(5) <= \<const0>\;
doutb(4) <= \<const0>\;
doutb(3) <= \<const0>\;
doutb(2) <= \<const0>\;
doutb(1) <= \<const0>\;
doutb(0) <= \<const0>\;
rdaddrecc(9) <= \<const0>\;
rdaddrecc(8) <= \<const0>\;
rdaddrecc(7) <= \<const0>\;
rdaddrecc(6) <= \<const0>\;
rdaddrecc(5) <= \<const0>\;
rdaddrecc(4) <= \<const0>\;
rdaddrecc(3) <= \<const0>\;
rdaddrecc(2) <= \<const0>\;
rdaddrecc(1) <= \<const0>\;
rdaddrecc(0) <= \<const0>\;
rsta_busy <= \<const0>\;
rstb_busy <= \<const0>\;
s_axi_arready <= \<const0>\;
s_axi_awready <= \<const0>\;
s_axi_bid(3) <= \<const0>\;
s_axi_bid(2) <= \<const0>\;
s_axi_bid(1) <= \<const0>\;
s_axi_bid(0) <= \<const0>\;
s_axi_bresp(1) <= \<const0>\;
s_axi_bresp(0) <= \<const0>\;
s_axi_bvalid <= \<const0>\;
s_axi_dbiterr <= \<const0>\;
s_axi_rdaddrecc(9) <= \<const0>\;
s_axi_rdaddrecc(8) <= \<const0>\;
s_axi_rdaddrecc(7) <= \<const0>\;
s_axi_rdaddrecc(6) <= \<const0>\;
s_axi_rdaddrecc(5) <= \<const0>\;
s_axi_rdaddrecc(4) <= \<const0>\;
s_axi_rdaddrecc(3) <= \<const0>\;
s_axi_rdaddrecc(2) <= \<const0>\;
s_axi_rdaddrecc(1) <= \<const0>\;
s_axi_rdaddrecc(0) <= \<const0>\;
s_axi_rdata(19) <= \<const0>\;
s_axi_rdata(18) <= \<const0>\;
s_axi_rdata(17) <= \<const0>\;
s_axi_rdata(16) <= \<const0>\;
s_axi_rdata(15) <= \<const0>\;
s_axi_rdata(14) <= \<const0>\;
s_axi_rdata(13) <= \<const0>\;
s_axi_rdata(12) <= \<const0>\;
s_axi_rdata(11) <= \<const0>\;
s_axi_rdata(10) <= \<const0>\;
s_axi_rdata(9) <= \<const0>\;
s_axi_rdata(8) <= \<const0>\;
s_axi_rdata(7) <= \<const0>\;
s_axi_rdata(6) <= \<const0>\;
s_axi_rdata(5) <= \<const0>\;
s_axi_rdata(4) <= \<const0>\;
s_axi_rdata(3) <= \<const0>\;
s_axi_rdata(2) <= \<const0>\;
s_axi_rdata(1) <= \<const0>\;
s_axi_rdata(0) <= \<const0>\;
s_axi_rid(3) <= \<const0>\;
s_axi_rid(2) <= \<const0>\;
s_axi_rid(1) <= \<const0>\;
s_axi_rid(0) <= \<const0>\;
s_axi_rlast <= \<const0>\;
s_axi_rresp(1) <= \<const0>\;
s_axi_rresp(0) <= \<const0>\;
s_axi_rvalid <= \<const0>\;
s_axi_sbiterr <= \<const0>\;
s_axi_wready <= \<const0>\;
sbiterr <= \<const0>\;
GND: unisim.vcomponents.GND
port map (
G => \<const0>\
);
inst_blk_mem_gen: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5_synth
port map (
addra(9 downto 0) => addra(9 downto 0),
clka => clka,
dina(19 downto 0) => dina(19 downto 0),
douta(19 downto 0) => douta(19 downto 0),
ena => ena,
wea(0) => wea(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
port (
clka : in STD_LOGIC;
ena : in STD_LOGIC;
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
addra : in STD_LOGIC_VECTOR ( 9 downto 0 );
dina : in STD_LOGIC_VECTOR ( 19 downto 0 );
douta : out STD_LOGIC_VECTOR ( 19 downto 0 )
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is true;
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "bram_1024_3,blk_mem_gen_v8_3_5,{}";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "yes";
attribute x_core_info : string;
attribute x_core_info of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "blk_mem_gen_v8_3_5,Vivado 2016.4";
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
signal NLW_U0_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_rsta_busy_UNCONNECTED : STD_LOGIC;
signal NLW_U0_rstb_busy_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_arready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_awready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_bvalid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_rlast_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_rvalid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_wready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_doutb_UNCONNECTED : STD_LOGIC_VECTOR ( 19 downto 0 );
signal NLW_U0_rdaddrecc_UNCONNECTED : STD_LOGIC_VECTOR ( 9 downto 0 );
signal NLW_U0_s_axi_bid_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_s_axi_bresp_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_U0_s_axi_rdaddrecc_UNCONNECTED : STD_LOGIC_VECTOR ( 9 downto 0 );
signal NLW_U0_s_axi_rdata_UNCONNECTED : STD_LOGIC_VECTOR ( 19 downto 0 );
signal NLW_U0_s_axi_rid_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_s_axi_rresp_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute C_ADDRA_WIDTH : integer;
attribute C_ADDRA_WIDTH of U0 : label is 10;
attribute C_ADDRB_WIDTH : integer;
attribute C_ADDRB_WIDTH of U0 : label is 10;
attribute C_ALGORITHM : integer;
attribute C_ALGORITHM of U0 : label is 1;
attribute C_AXI_ID_WIDTH : integer;
attribute C_AXI_ID_WIDTH of U0 : label is 4;
attribute C_AXI_SLAVE_TYPE : integer;
attribute C_AXI_SLAVE_TYPE of U0 : label is 0;
attribute C_AXI_TYPE : integer;
attribute C_AXI_TYPE of U0 : label is 1;
attribute C_BYTE_SIZE : integer;
attribute C_BYTE_SIZE of U0 : label is 9;
attribute C_COMMON_CLK : integer;
attribute C_COMMON_CLK of U0 : label is 0;
attribute C_COUNT_18K_BRAM : string;
attribute C_COUNT_18K_BRAM of U0 : label is "0";
attribute C_COUNT_36K_BRAM : string;
attribute C_COUNT_36K_BRAM of U0 : label is "1";
attribute C_CTRL_ECC_ALGO : string;
attribute C_CTRL_ECC_ALGO of U0 : label is "NONE";
attribute C_DEFAULT_DATA : string;
attribute C_DEFAULT_DATA of U0 : label is "0";
attribute C_DISABLE_WARN_BHV_COLL : integer;
attribute C_DISABLE_WARN_BHV_COLL of U0 : label is 0;
attribute C_DISABLE_WARN_BHV_RANGE : integer;
attribute C_DISABLE_WARN_BHV_RANGE of U0 : label is 0;
attribute C_ELABORATION_DIR : string;
attribute C_ELABORATION_DIR of U0 : label is "./";
attribute C_ENABLE_32BIT_ADDRESS : integer;
attribute C_ENABLE_32BIT_ADDRESS of U0 : label is 0;
attribute C_EN_DEEPSLEEP_PIN : integer;
attribute C_EN_DEEPSLEEP_PIN of U0 : label is 0;
attribute C_EN_ECC_PIPE : integer;
attribute C_EN_ECC_PIPE of U0 : label is 0;
attribute C_EN_RDADDRA_CHG : integer;
attribute C_EN_RDADDRA_CHG of U0 : label is 0;
attribute C_EN_RDADDRB_CHG : integer;
attribute C_EN_RDADDRB_CHG of U0 : label is 0;
attribute C_EN_SAFETY_CKT : integer;
attribute C_EN_SAFETY_CKT of U0 : label is 0;
attribute C_EN_SHUTDOWN_PIN : integer;
attribute C_EN_SHUTDOWN_PIN of U0 : label is 0;
attribute C_EN_SLEEP_PIN : integer;
attribute C_EN_SLEEP_PIN of U0 : label is 0;
attribute C_EST_POWER_SUMMARY : string;
attribute C_EST_POWER_SUMMARY of U0 : label is "Estimated Power for IP : 2.74095 mW";
attribute C_FAMILY : string;
attribute C_FAMILY of U0 : label is "zynq";
attribute C_HAS_AXI_ID : integer;
attribute C_HAS_AXI_ID of U0 : label is 0;
attribute C_HAS_ENA : integer;
attribute C_HAS_ENA of U0 : label is 1;
attribute C_HAS_ENB : integer;
attribute C_HAS_ENB of U0 : label is 0;
attribute C_HAS_INJECTERR : integer;
attribute C_HAS_INJECTERR of U0 : label is 0;
attribute C_HAS_MEM_OUTPUT_REGS_A : integer;
attribute C_HAS_MEM_OUTPUT_REGS_A of U0 : label is 1;
attribute C_HAS_MEM_OUTPUT_REGS_B : integer;
attribute C_HAS_MEM_OUTPUT_REGS_B of U0 : label is 0;
attribute C_HAS_MUX_OUTPUT_REGS_A : integer;
attribute C_HAS_MUX_OUTPUT_REGS_A of U0 : label is 0;
attribute C_HAS_MUX_OUTPUT_REGS_B : integer;
attribute C_HAS_MUX_OUTPUT_REGS_B of U0 : label is 0;
attribute C_HAS_REGCEA : integer;
attribute C_HAS_REGCEA of U0 : label is 0;
attribute C_HAS_REGCEB : integer;
attribute C_HAS_REGCEB of U0 : label is 0;
attribute C_HAS_RSTA : integer;
attribute C_HAS_RSTA of U0 : label is 0;
attribute C_HAS_RSTB : integer;
attribute C_HAS_RSTB of U0 : label is 0;
attribute C_HAS_SOFTECC_INPUT_REGS_A : integer;
attribute C_HAS_SOFTECC_INPUT_REGS_A of U0 : label is 0;
attribute C_HAS_SOFTECC_OUTPUT_REGS_B : integer;
attribute C_HAS_SOFTECC_OUTPUT_REGS_B of U0 : label is 0;
attribute C_INITA_VAL : string;
attribute C_INITA_VAL of U0 : label is "0";
attribute C_INITB_VAL : string;
attribute C_INITB_VAL of U0 : label is "0";
attribute C_INIT_FILE : string;
attribute C_INIT_FILE of U0 : label is "bram_1024_3.mem";
attribute C_INIT_FILE_NAME : string;
attribute C_INIT_FILE_NAME of U0 : label is "bram_1024_3.mif";
attribute C_INTERFACE_TYPE : integer;
attribute C_INTERFACE_TYPE of U0 : label is 0;
attribute C_LOAD_INIT_FILE : integer;
attribute C_LOAD_INIT_FILE of U0 : label is 1;
attribute C_MEM_TYPE : integer;
attribute C_MEM_TYPE of U0 : label is 0;
attribute C_MUX_PIPELINE_STAGES : integer;
attribute C_MUX_PIPELINE_STAGES of U0 : label is 0;
attribute C_PRIM_TYPE : integer;
attribute C_PRIM_TYPE of U0 : label is 1;
attribute C_READ_DEPTH_A : integer;
attribute C_READ_DEPTH_A of U0 : label is 1024;
attribute C_READ_DEPTH_B : integer;
attribute C_READ_DEPTH_B of U0 : label is 1024;
attribute C_READ_WIDTH_A : integer;
attribute C_READ_WIDTH_A of U0 : label is 20;
attribute C_READ_WIDTH_B : integer;
attribute C_READ_WIDTH_B of U0 : label is 20;
attribute C_RSTRAM_A : integer;
attribute C_RSTRAM_A of U0 : label is 0;
attribute C_RSTRAM_B : integer;
attribute C_RSTRAM_B of U0 : label is 0;
attribute C_RST_PRIORITY_A : string;
attribute C_RST_PRIORITY_A of U0 : label is "CE";
attribute C_RST_PRIORITY_B : string;
attribute C_RST_PRIORITY_B of U0 : label is "CE";
attribute C_SIM_COLLISION_CHECK : string;
attribute C_SIM_COLLISION_CHECK of U0 : label is "ALL";
attribute C_USE_BRAM_BLOCK : integer;
attribute C_USE_BRAM_BLOCK of U0 : label is 0;
attribute C_USE_BYTE_WEA : integer;
attribute C_USE_BYTE_WEA of U0 : label is 0;
attribute C_USE_BYTE_WEB : integer;
attribute C_USE_BYTE_WEB of U0 : label is 0;
attribute C_USE_DEFAULT_DATA : integer;
attribute C_USE_DEFAULT_DATA of U0 : label is 0;
attribute C_USE_ECC : integer;
attribute C_USE_ECC of U0 : label is 0;
attribute C_USE_SOFTECC : integer;
attribute C_USE_SOFTECC of U0 : label is 0;
attribute C_USE_URAM : integer;
attribute C_USE_URAM of U0 : label is 0;
attribute C_WEA_WIDTH : integer;
attribute C_WEA_WIDTH of U0 : label is 1;
attribute C_WEB_WIDTH : integer;
attribute C_WEB_WIDTH of U0 : label is 1;
attribute C_WRITE_DEPTH_A : integer;
attribute C_WRITE_DEPTH_A of U0 : label is 1024;
attribute C_WRITE_DEPTH_B : integer;
attribute C_WRITE_DEPTH_B of U0 : label is 1024;
attribute C_WRITE_MODE_A : string;
attribute C_WRITE_MODE_A of U0 : label is "WRITE_FIRST";
attribute C_WRITE_MODE_B : string;
attribute C_WRITE_MODE_B of U0 : label is "WRITE_FIRST";
attribute C_WRITE_WIDTH_A : integer;
attribute C_WRITE_WIDTH_A of U0 : label is 20;
attribute C_WRITE_WIDTH_B : integer;
attribute C_WRITE_WIDTH_B of U0 : label is 20;
attribute C_XDEVICEFAMILY : string;
attribute C_XDEVICEFAMILY of U0 : label is "zynq";
attribute downgradeipidentifiedwarnings of U0 : label is "yes";
begin
U0: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5
port map (
addra(9 downto 0) => addra(9 downto 0),
addrb(9 downto 0) => B"0000000000",
clka => clka,
clkb => '0',
dbiterr => NLW_U0_dbiterr_UNCONNECTED,
deepsleep => '0',
dina(19 downto 0) => dina(19 downto 0),
dinb(19 downto 0) => B"00000000000000000000",
douta(19 downto 0) => douta(19 downto 0),
doutb(19 downto 0) => NLW_U0_doutb_UNCONNECTED(19 downto 0),
eccpipece => '0',
ena => ena,
enb => '0',
injectdbiterr => '0',
injectsbiterr => '0',
rdaddrecc(9 downto 0) => NLW_U0_rdaddrecc_UNCONNECTED(9 downto 0),
regcea => '0',
regceb => '0',
rsta => '0',
rsta_busy => NLW_U0_rsta_busy_UNCONNECTED,
rstb => '0',
rstb_busy => NLW_U0_rstb_busy_UNCONNECTED,
s_aclk => '0',
s_aresetn => '0',
s_axi_araddr(31 downto 0) => B"00000000000000000000000000000000",
s_axi_arburst(1 downto 0) => B"00",
s_axi_arid(3 downto 0) => B"0000",
s_axi_arlen(7 downto 0) => B"00000000",
s_axi_arready => NLW_U0_s_axi_arready_UNCONNECTED,
s_axi_arsize(2 downto 0) => B"000",
s_axi_arvalid => '0',
s_axi_awaddr(31 downto 0) => B"00000000000000000000000000000000",
s_axi_awburst(1 downto 0) => B"00",
s_axi_awid(3 downto 0) => B"0000",
s_axi_awlen(7 downto 0) => B"00000000",
s_axi_awready => NLW_U0_s_axi_awready_UNCONNECTED,
s_axi_awsize(2 downto 0) => B"000",
s_axi_awvalid => '0',
s_axi_bid(3 downto 0) => NLW_U0_s_axi_bid_UNCONNECTED(3 downto 0),
s_axi_bready => '0',
s_axi_bresp(1 downto 0) => NLW_U0_s_axi_bresp_UNCONNECTED(1 downto 0),
s_axi_bvalid => NLW_U0_s_axi_bvalid_UNCONNECTED,
s_axi_dbiterr => NLW_U0_s_axi_dbiterr_UNCONNECTED,
s_axi_injectdbiterr => '0',
s_axi_injectsbiterr => '0',
s_axi_rdaddrecc(9 downto 0) => NLW_U0_s_axi_rdaddrecc_UNCONNECTED(9 downto 0),
s_axi_rdata(19 downto 0) => NLW_U0_s_axi_rdata_UNCONNECTED(19 downto 0),
s_axi_rid(3 downto 0) => NLW_U0_s_axi_rid_UNCONNECTED(3 downto 0),
s_axi_rlast => NLW_U0_s_axi_rlast_UNCONNECTED,
s_axi_rready => '0',
s_axi_rresp(1 downto 0) => NLW_U0_s_axi_rresp_UNCONNECTED(1 downto 0),
s_axi_rvalid => NLW_U0_s_axi_rvalid_UNCONNECTED,
s_axi_sbiterr => NLW_U0_s_axi_sbiterr_UNCONNECTED,
s_axi_wdata(19 downto 0) => B"00000000000000000000",
s_axi_wlast => '0',
s_axi_wready => NLW_U0_s_axi_wready_UNCONNECTED,
s_axi_wstrb(0) => '0',
s_axi_wvalid => '0',
sbiterr => NLW_U0_sbiterr_UNCONNECTED,
shutdown => '0',
sleep => '0',
wea(0) => wea(0),
web(0) => '0'
);
end STRUCTURE;
| unlicense | 9657dcbd67728ab1c6bd33bbabd57d60 | 0.70643 | 3.4478 | false | false | false | false |
grwlf/vsim | vhdl_ct/ct00566.vhd | 1 | 8,287 | -- NEED RESULT: ARCH00566: Attribute declarations - scalar static subtypes with static initial values passed
-- NEED RESULT: ARCH00566: Attribute declarations - scalar static subtypes with generic initial values passed
-------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
-------------------------------------------------------------------------------
--
-- TEST NAME:
--
-- CT00566
--
-- AUTHOR:
--
-- A. Wilmot
--
-- TEST OBJECTIVES:
--
-- 4.4 (3)
-- 4.4 (4)
--
-- DESIGN UNIT ORDERING:
--
-- ENT00566(ARCH00566)
-- ENT00566_Test_Bench(ARCH00566_Test_Bench)
--
-- REVISION HISTORY:
--
-- 19-AUG-1987 - initial revision
--
-- NOTES:
--
-- self-checking
-- automatically generated
--
use WORK.STANDARD_TYPES.all ;
--
entity ENT00566 is
generic (
i_boolean_1, i_boolean_2 : boolean
:= c_boolean_1 ;
i_bit_1, i_bit_2 : bit
:= c_bit_1 ;
i_severity_level_1, i_severity_level_2 : severity_level
:= c_severity_level_1 ;
i_character_1, i_character_2 : character
:= c_character_1 ;
i_t_enum1_1, i_t_enum1_2 : t_enum1
:= c_t_enum1_1 ;
i_st_enum1_1, i_st_enum1_2 : st_enum1
:= c_st_enum1_1 ;
i_integer_1, i_integer_2 : integer
:= c_integer_1 ;
i_t_int1_1, i_t_int1_2 : t_int1
:= c_t_int1_1 ;
i_st_int1_1, i_st_int1_2 : st_int1
:= c_st_int1_1 ;
i_time_1, i_time_2 : time
:= c_time_1 ;
i_t_phys1_1, i_t_phys1_2 : t_phys1
:= c_t_phys1_1 ;
i_st_phys1_1, i_st_phys1_2 : st_phys1
:= c_st_phys1_1 ;
i_real_1, i_real_2 : real
:= c_real_1 ;
i_t_real1_1, i_t_real1_2 : t_real1
:= c_t_real1_1 ;
i_st_real1_1, i_st_real1_2 : st_real1
:= c_st_real1_1
) ;
attribute at_boolean_1 : boolean ;
attribute at_bit_1 : bit ;
attribute at_severity_level_1 : severity_level ;
attribute at_character_1 : character ;
attribute at_t_enum1_1 : t_enum1 ;
attribute at_st_enum1_1 : st_enum1 ;
attribute at_integer_1 : integer ;
attribute at_t_int1_1 : t_int1 ;
attribute at_st_int1_1 : st_int1 ;
attribute at_time_1 : time ;
attribute at_t_phys1_1 : t_phys1 ;
attribute at_st_phys1_1 : st_phys1 ;
attribute at_real_1 : real ;
attribute at_t_real1_1 : t_real1 ;
attribute at_st_real1_1 : st_real1 ;
end ENT00566 ;
architecture ARCH00566 of ENT00566 is
begin
process
variable correct : boolean := true ;
procedure p1 ;
attribute at_boolean_1 of p1 : procedure is
c_boolean_1 ;
attribute at_bit_1 of p1 : procedure is
c_bit_1 ;
attribute at_severity_level_1 of p1 : procedure is
c_severity_level_1 ;
attribute at_character_1 of p1 : procedure is
c_character_1 ;
attribute at_t_enum1_1 of p1 : procedure is
c_t_enum1_1 ;
attribute at_st_enum1_1 of p1 : procedure is
c_st_enum1_1 ;
attribute at_integer_1 of p1 : procedure is
c_integer_1 ;
attribute at_t_int1_1 of p1 : procedure is
c_t_int1_1 ;
attribute at_st_int1_1 of p1 : procedure is
c_st_int1_1 ;
attribute at_time_1 of p1 : procedure is
c_time_1 ;
attribute at_t_phys1_1 of p1 : procedure is
c_t_phys1_1 ;
attribute at_st_phys1_1 of p1 : procedure is
c_st_phys1_1 ;
attribute at_real_1 of p1 : procedure is
c_real_1 ;
attribute at_t_real1_1 of p1 : procedure is
c_t_real1_1 ;
attribute at_st_real1_1 of p1 : procedure is
c_st_real1_1 ;
procedure p1 is
begin
correct := correct and p1'at_boolean_1
= c_boolean_1 ;
correct := correct and p1'at_bit_1
= c_bit_1 ;
correct := correct and p1'at_severity_level_1
= c_severity_level_1 ;
correct := correct and p1'at_character_1
= c_character_1 ;
correct := correct and p1'at_t_enum1_1
= c_t_enum1_1 ;
correct := correct and p1'at_st_enum1_1
= c_st_enum1_1 ;
correct := correct and p1'at_integer_1
= c_integer_1 ;
correct := correct and p1'at_t_int1_1
= c_t_int1_1 ;
correct := correct and p1'at_st_int1_1
= c_st_int1_1 ;
correct := correct and p1'at_time_1
= c_time_1 ;
correct := correct and p1'at_t_phys1_1
= c_t_phys1_1 ;
correct := correct and p1'at_st_phys1_1
= c_st_phys1_1 ;
correct := correct and p1'at_real_1
= c_real_1 ;
correct := correct and p1'at_t_real1_1
= c_t_real1_1 ;
correct := correct and p1'at_st_real1_1
= c_st_real1_1 ;
test_report ( "ARCH00566" ,
"Attribute declarations - scalar static subtypes"
& " with static initial values" ,
correct) ;
end p1 ;
begin
p1 ;
wait ;
end process ;
process
variable correct : boolean := true ;
procedure p1 ;
attribute at_boolean_1 of p1 : procedure is
i_boolean_1 ;
attribute at_bit_1 of p1 : procedure is
i_bit_1 ;
attribute at_severity_level_1 of p1 : procedure is
i_severity_level_1 ;
attribute at_character_1 of p1 : procedure is
i_character_1 ;
attribute at_t_enum1_1 of p1 : procedure is
i_t_enum1_1 ;
attribute at_st_enum1_1 of p1 : procedure is
i_st_enum1_1 ;
attribute at_integer_1 of p1 : procedure is
i_integer_1 ;
attribute at_t_int1_1 of p1 : procedure is
i_t_int1_1 ;
attribute at_st_int1_1 of p1 : procedure is
i_st_int1_1 ;
attribute at_time_1 of p1 : procedure is
i_time_1 ;
attribute at_t_phys1_1 of p1 : procedure is
i_t_phys1_1 ;
attribute at_st_phys1_1 of p1 : procedure is
i_st_phys1_1 ;
attribute at_real_1 of p1 : procedure is
i_real_1 ;
attribute at_t_real1_1 of p1 : procedure is
i_t_real1_1 ;
attribute at_st_real1_1 of p1 : procedure is
i_st_real1_1 ;
procedure p1 is
begin
correct := correct and p1'at_boolean_1
= c_boolean_1 ;
correct := correct and p1'at_bit_1
= c_bit_1 ;
correct := correct and p1'at_severity_level_1
= c_severity_level_1 ;
correct := correct and p1'at_character_1
= c_character_1 ;
correct := correct and p1'at_t_enum1_1
= c_t_enum1_1 ;
correct := correct and p1'at_st_enum1_1
= c_st_enum1_1 ;
correct := correct and p1'at_integer_1
= c_integer_1 ;
correct := correct and p1'at_t_int1_1
= c_t_int1_1 ;
correct := correct and p1'at_st_int1_1
= c_st_int1_1 ;
correct := correct and p1'at_time_1
= c_time_1 ;
correct := correct and p1'at_t_phys1_1
= c_t_phys1_1 ;
correct := correct and p1'at_st_phys1_1
= c_st_phys1_1 ;
correct := correct and p1'at_real_1
= c_real_1 ;
correct := correct and p1'at_t_real1_1
= c_t_real1_1 ;
correct := correct and p1'at_st_real1_1
= c_st_real1_1 ;
test_report ( "ARCH00566" ,
"Attribute declarations - scalar static subtypes"
& " with generic initial values" ,
correct) ;
end p1 ;
begin
p1 ;
wait ;
end process ;
end ARCH00566 ;
--
entity ENT00566_Test_Bench is
end ENT00566_Test_Bench ;
--
architecture ARCH00566_Test_Bench of ENT00566_Test_Bench is
begin
L1:
block
component UUT
end component ;
for CIS1 : UUT use entity WORK.ENT00566 ( ARCH00566 ) ;
begin
CIS1 : UUT ;
end block L1 ;
end ARCH00566_Test_Bench ;
| gpl-3.0 | 7a4a3a8a7a2f427d984751f95851c272 | 0.521298 | 3.158155 | false | false | false | false |
grwlf/vsim | vhdl/IEEE/old/standard.vhd | 1 | 6,164 | -- The sven STANDARD package.
-- This design unit contains some special tokens, which are only
-- recognized by the analyzer when it is in special "bootstrap" mode.
package STANDARD is
-- predefined enumeration types:
type BOOLEAN is (FALSE, TRUE);
function "-" ( a, b: integer ) return integer;
function "+" ( a, b: integer ) return integer;
function "*" ( a, b: integer ) return integer;
function "/" ( a, b: integer ) return integer;
function "mod" ( a, b: integer ) return integer;
function "**" ( a, b: integer ) return integer;
function "and" (anonymous1, anonymous2: BOOLEAN) return BOOLEAN;
function "or" (anonymous1, anonymous2: BOOLEAN) return BOOLEAN;
function "nand" (anonymous1, anonymous2: BOOLEAN) return BOOLEAN;
function "nor" (anonymous1, anonymous2: BOOLEAN) return BOOLEAN;
function "xor" (anonymous1, anonymous2: BOOLEAN) return BOOLEAN;
function "xnor" (anonymous1, anonymous2: BOOLEAN) return BOOLEAN;
function "not" (anonymous1: BOOLEAN) return BOOLEAN;
function "=" (anonymous1, anonymous2: BOOLEAN) return BOOLEAN;
function "/=" (anonymous1, anonymous2: BOOLEAN) return BOOLEAN;
function "<" (anonymous1, anonymous2: BOOLEAN) return BOOLEAN;
function "<=" (anonymous1, anonymous2: BOOLEAN) return BOOLEAN;
function ">" (anonymous1, anonymous2: BOOLEAN) return BOOLEAN;
function ">=" (anonymous1, anonymous2: BOOLEAN) return BOOLEAN;
type BIT is ('0', '1');
-- The predefined operators for this type are as follows:
-- function "and" (anonymous, anonymous: BIT) return BIT;
-- function "or" (anonymous, anonymous: BIT) return BIT;
-- function "nand" (anonymous, anonymous: BIT) return BIT;
-- function "nor" (anonymous, anonymous: BIT) return BIT;
-- function "xor" (anonymous, anonymous: BIT) return BIT;
-- function "xnor" (anonymous, anonymous: BIT) return BIT;
-- function "not" (anonymous: BIT) return BIT;
-- function "=" (anonymous, anonymous: BIT) return BOOLEAN;
-- function "/=" (anonymous, anonymous: BIT) return BOOLEAN;
-- function "<" (anonymous, anonymous: BIT) return BOOLEAN;
-- function "<=" (anonymous, anonymous: BIT) return BOOLEAN;
-- function ">" (anonymous, anonymous: BIT) return BOOLEAN;
-- function ">=" (anonymous, anonymous: BIT) return BOOLEAN;
type CHARACTER is (
NUL, SOH, STX, ETX, EOT, ENQ, ACK, BEL,
BS, HT, LF, VT, FF, CR, SO, SI,
DLE, DC1, DC2, DC3, DC4, NAK, SYN, ETB,
CAN, EM, SUB, ESC, FSP, GSP, RSP, USP,
' ', '!', '"', '#', '$', '%', '&', ''',
'(', ')', '*', '+', ',', '-', '.', '/',
'0', '1', '2', '3', '4', '5', '6', '7',
'8', '9', ':', ';', '<', '=', '>', '?',
'@', 'A', 'B', 'C', 'D', 'E', 'F', 'G',
'H', 'I', 'J', 'K', 'L', 'M', 'N', 'O',
'P', 'Q', 'R', 'S', 'T', 'U', 'V', 'W',
'X', 'Y', 'Z', '[', '\', ']', '^', '_',
'`', 'a', 'b', 'c', 'd', 'e', 'f', 'g',
'h', 'i', 'j', 'k', 'l', 'm', 'n', 'o',
'p', 'q', 'r', 's', 't', 'u', 'v', 'w',
'x', 'y', 'z', '{', '|', '}', '~', DEL,
C128, C129, C130, C131, C132, C133, C134, C135,
C136, C137, C138, C139, C140, C141, C142, C143,
C144, C145, C146, C147, C148, C149, C150, C151,
C152, C153, C154, C155, C156, C157, C158, C159
--,
-- ' ', '¡', '¢', '£', '¤', '¥', '¦', '§',
-- '¨', '©', 'ª', '«', '¬', '', '®', '¯',
-- '°', '±', '²', '³', '´', 'µ', '¶', '·',
-- '¸', '¹', 'º', '»', '¼', '½', '¾', '¿',
-- 'À', 'Á', 'Â', 'Ã', 'Ä', 'Å', 'Æ', 'Ç',
-- 'È', 'É', 'Ê', 'Ë', 'Ì', 'Í', 'Î', 'Ï',
-- 'Ð', 'Ñ', 'Ò', 'Ó', 'Ô', 'Õ', 'Ö', '×',
-- 'Ø', 'Ù', 'Ú', 'Û', 'Ü', 'Ý', 'Þ', 'ß',
-- 'à', 'á', 'â', 'ã', 'ä', 'å', 'æ', 'ç',
-- 'è', 'é', 'ê', 'ë', 'ì', 'í', 'î', 'ï',
-- 'ð', 'ñ', 'ò', 'ó', 'ô', 'õ', 'ö', '÷',
-- 'ø', 'ù', 'ú', 'û', 'ü', 'ý', 'þ', 'ÿ'
);
type SEVERITY_LEVEL is (NOTE, WARNING, ERROR, FAILURE);
-- predefined numeric types:
-- Do INTEGER first to aid implicit declarations of "**".
-- type INTEGER is range -2147483647 to 2147483647;
-- type $UNIVERSAL_INTEGER is range $- to $+;
-- type $UNIVERSAL_REAL is range $-. to $+.;
function "*" (LEFT: real; RIGHT: INTEGER)
return real;
function "*" (LEFT: INTEGER; RIGHT: REAL)
return REAL;
function "/" (LEFT: REAL; RIGHT: INTEGER)
return REAL;
-- type REAL is range $-. to $+.;
-- predefined type TIME:
type TIME is range -1000000 to +100000000
units
fs; -- femtosecond
ps = 1000 fs; -- picosecond
ns = 1000 ps; -- nanosecond
us = 1000 ns; -- microsecond
ms = 1000 us; -- millisecond
sec = 1000 ms; -- second
min = 60 sec; -- minute
hr = 60 min; -- hour;
end units;
-- subtype used internally for checking time expressions for non-negativness:
-- subtype $NATURAL_TIME is TIME range 0 sec to TIME'HIGH;
-- subtype DELAY_LENGTH is TIME range 0 fs to TIME'HIGH;
-- function that returns the current simulation time:
-- impure function NOW return TIME;
-- predefined numeric subtypes:
subtype NATURAL is INTEGER range 0 to INTEGER'HIGH;
subtype POSITIVE is INTEGER range 1 to INTEGER'HIGH;
-- predefined array types:
type STRING is array (POSITIVE range <>) of CHARACTER;
function "&" ( a, b: STRING ) return STRING;
type BIT_VECTOR is array (NATURAL range <>) of BIT;
--type FILE_OPEN_KIND is (READ_OPEN, WRITE_OPEN, APPEND_OPEN);
type FILE_OPEN_KIND is (READ_MODE, WRITE_MODE, APPEND_MODE);
type FILE_OPEN_STATUS is (OPEN_OK, STATUS_ERROR, NAME_ERROR, MODE_ERROR);
attribute FOREIGN: STRING;
--
-- The rest of this package is SVEN specific stuff required to make
-- this implementation go.
-- Note that all things are declared use leading $ characters, so we don't
-- trample the user's name space.
--
-- attribute $BUILTIN: BOOLEAN;
-- procedure $RTINDEX (I: NATURAL; FIRSTARG: INTEGER; PASSAP,SAVEFREGS: BOOLEAN);
-- procedure $RTSYMBOL (S: STRING; FIRSTARG: INTEGER; PASSAP,SAVEFREGS: BOOLEAN);
-- attribute $BUILTIN of all: function is TRUE;
-- attribute $BUILTIN of all: procedure is TRUE;
end STANDARD;
| gpl-3.0 | 0cd80b9abd6bc2495594696eec87d381 | 0.565704 | 2.805644 | false | false | false | false |
grwlf/vsim | vhdl_ct/ct00272.vhd | 1 | 4,098 | -- NEED RESULT: ARCH00272: Configuration item in block configuration may be block or component configuration passed
-- NEED RESULT: ARCH00272: Block specification may be architecture name or block label passed
-- NEED RESULT: ARCH00272: Several configuration item may appear in a block configuration and block configurations may be nested to an arbitrary depth passed
-------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
-------------------------------------------------------------------------------
--
-- TEST NAME:
--
-- CT00272
--
-- AUTHOR:
--
-- A. Wilmot
--
-- TEST OBJECTIVES:
--
-- 1.3.1 (3)
-- 1.3.1 (4)
-- 1.3.1 (5)
--
-- DESIGN UNIT ORDERING:
--
-- ENT00272(ARCH00272)
-- ENT00272_1(ARCH00272_1)
-- CONF00272
-- ENT00272_Test_Bench(ARCH00272_Test_Bench)
--
-- REVISION HISTORY:
--
-- 17-JUL-1987 - initial revision
--
-- NOTES:
--
-- self-checking
--
entity ENT00272 is
generic ( g10, g11, g12 : integer ) ;
port ( s10, s11, s12 : out integer ) ;
end ENT00272 ;
architecture ARCH00272 of ENT00272 is
component COMP1
end component ;
begin
C1 : COMP1;
B1_1 :
block
begin
B2_2 :
block
component COMP1
end component ;
begin
CIS1 : COMP1;
end block B2_2 ;
B2_3 :
block
begin
B3_4 :
block
component COMP1
end component ;
begin
CIS1 : COMP1;
end block B3_4 ;
end block B2_3 ;
end block B1_1 ;
end ARCH00272 ;
entity ENT00272_1 is
generic ( g1 : integer ) ;
port ( s1 : out integer ) ;
begin
end ENT00272_1 ;
architecture ARCH00272_1 of ENT00272_1 is
begin
s1 <= g1 ;
end ARCH00272_1 ;
configuration CONF00272 of WORK.ENT00272 is
for ARCH00272
for C1 : COMP1
use entity WORK.ENT00272_1 ( ARCH00272_1 )
generic map ( g10 )
port map ( s10 ) ;
end for ;
for B1_1
for B2_2
for CIS1 : COMP1
use entity WORK.ENT00272_1 ( ARCH00272_1 )
generic map ( g11 )
port map ( s11 ) ;
end for ;
end for ; -- B2_2 component
for B2_3
for B3_4
for CIS1 : COMP1 -- 3 deep
use entity WORK.ENT00272_1 ( ARCH00272_1 )
generic map ( g12 )
port map ( s12 ) ;
end for ;
end for ; -- B3_4
end for ; -- B2_3
end for ; -- B1_1
end for ;
end CONF00272 ;
use WORK.STANDARD_TYPES.all ;
entity ENT00272_Test_Bench is
end ENT00272_Test_Bench ;
architecture ARCH00272_Test_Bench of ENT00272_Test_Bench is
begin
L1:
block
constant c1 : integer := 1 ;
constant c2 : integer := 2 ;
constant c3 : integer := 3 ;
signal s1, s2, s3 : integer ;
component UUT
end component ;
for CIS1 : UUT use configuration WORK.CONF00272
generic map ( c1, c2, c3 )
port map ( s1, s2, s3 ) ;
begin
CIS1 : UUT ;
P00272 :
process ( s1, s2, s3 )
begin
if s1 = c1 and s2 = c2 and s3 = c3 then
test_report ( "ARCH00272" ,
"Configuration item in block configuration may"
& " be block or component configuration" ,
true ) ;
test_report ( "ARCH00272" ,
"Block specification may be architecture name"
& " or block label" ,
true ) ;
test_report ( "ARCH00272" ,
"Several configuration item may appear in a block"
& " configuration and block configurations may be"
& " nested to an arbitrary depth" ,
true ) ;
end if ;
end process P00272 ;
end block L1 ;
end ARCH00272_Test_Bench ;
| gpl-3.0 | 0440e06a1fd46bf3c86d5db96afcd6ba | 0.504148 | 3.607394 | false | true | false | false |
Given-Jiang/Binarization | tb_Binarization/hdl/Binarization_GN.vhd | 2 | 10,406 | -- Binarization_GN.vhd
-- Generated using ACDS version 13.1 162 at 2015.02.12.09:18:23
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity Binarization_GN is
port (
Avalon_ST_Source_startofpacket : out std_logic; -- Avalon_ST_Source_startofpacket.wire
Avalon_ST_Source_data : out std_logic_vector(23 downto 0); -- Avalon_ST_Source_data.wire
Avalon_ST_Source_endofpacket : out std_logic; -- Avalon_ST_Source_endofpacket.wire
Avalon_MM_Slave_write : in std_logic := '0'; -- Avalon_MM_Slave_write.wire
Avalon_ST_Sink_endofpacket : in std_logic := '0'; -- Avalon_ST_Sink_endofpacket.wire
Avalon_MM_Slave_writedata : in std_logic_vector(31 downto 0) := (others => '0'); -- Avalon_MM_Slave_writedata.wire
Avalon_ST_Source_valid : out std_logic; -- Avalon_ST_Source_valid.wire
Avalon_ST_Source_ready : in std_logic := '0'; -- Avalon_ST_Source_ready.wire
Clock : in std_logic := '0'; -- Clock.clk
aclr : in std_logic := '0'; -- .reset_n
Avalon_MM_Slave_address : in std_logic_vector(1 downto 0) := (others => '0'); -- Avalon_MM_Slave_address.wire
Avalon_ST_Sink_valid : in std_logic := '0'; -- Avalon_ST_Sink_valid.wire
Avalon_ST_Sink_ready : out std_logic; -- Avalon_ST_Sink_ready.wire
Avalon_ST_Sink_startofpacket : in std_logic := '0'; -- Avalon_ST_Sink_startofpacket.wire
Avalon_ST_Sink_data : in std_logic_vector(23 downto 0) := (others => '0') -- Avalon_ST_Sink_data.wire
);
end entity Binarization_GN;
architecture rtl of Binarization_GN is
component alt_dspbuilder_clock_GNF343OQUJ is
port (
aclr : in std_logic := 'X'; -- reset
aclr_n : in std_logic := 'X'; -- reset_n
aclr_out : out std_logic; -- reset
clock : in std_logic := 'X'; -- clk
clock_out : out std_logic -- clk
);
end component alt_dspbuilder_clock_GNF343OQUJ;
component alt_dspbuilder_port_GNOC3SGKQJ is
port (
input : in std_logic_vector(23 downto 0) := (others => 'X'); -- wire
output : out std_logic_vector(23 downto 0) -- wire
);
end component alt_dspbuilder_port_GNOC3SGKQJ;
component alt_dspbuilder_port_GN37ALZBS4 is
port (
input : in std_logic := 'X'; -- wire
output : out std_logic -- wire
);
end component alt_dspbuilder_port_GN37ALZBS4;
component Binarization_GN_Binarization_Binarization_Module is
port (
sop : in std_logic := 'X'; -- wire
writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- wire
eop : in std_logic := 'X'; -- wire
addr : in std_logic_vector(1 downto 0) := (others => 'X'); -- wire
write : in std_logic := 'X'; -- wire
Clock : in std_logic := 'X'; -- clk
aclr : in std_logic := 'X'; -- reset
data_out : out std_logic_vector(23 downto 0); -- wire
data_in : in std_logic_vector(23 downto 0) := (others => 'X') -- wire
);
end component Binarization_GN_Binarization_Binarization_Module;
component alt_dspbuilder_port_GN6TDLHAW6 is
port (
input : in std_logic_vector(1 downto 0) := (others => 'X'); -- wire
output : out std_logic_vector(1 downto 0) -- wire
);
end component alt_dspbuilder_port_GN6TDLHAW6;
component alt_dspbuilder_port_GNEPKLLZKY is
port (
input : in std_logic_vector(31 downto 0) := (others => 'X'); -- wire
output : out std_logic_vector(31 downto 0) -- wire
);
end component alt_dspbuilder_port_GNEPKLLZKY;
signal avalon_st_sink_valid_0_output_wire : std_logic; -- Avalon_ST_Sink_valid_0:output -> Avalon_ST_Source_valid_0:input
signal avalon_st_sink_startofpacket_0_output_wire : std_logic; -- Avalon_ST_Sink_startofpacket_0:output -> [Avalon_ST_Source_startofpacket_0:input, Binarization_Binarization_Module_0:sop]
signal avalon_st_sink_endofpacket_0_output_wire : std_logic; -- Avalon_ST_Sink_endofpacket_0:output -> [Avalon_ST_Source_endofpacket_0:input, Binarization_Binarization_Module_0:eop]
signal avalon_st_source_ready_0_output_wire : std_logic; -- Avalon_ST_Source_ready_0:output -> Avalon_ST_Sink_ready_0:input
signal avalon_mm_slave_address_0_output_wire : std_logic_vector(1 downto 0); -- Avalon_MM_Slave_address_0:output -> Binarization_Binarization_Module_0:addr
signal avalon_mm_slave_write_0_output_wire : std_logic; -- Avalon_MM_Slave_write_0:output -> Binarization_Binarization_Module_0:write
signal avalon_mm_slave_writedata_0_output_wire : std_logic_vector(31 downto 0); -- Avalon_MM_Slave_writedata_0:output -> Binarization_Binarization_Module_0:writedata
signal avalon_st_sink_data_0_output_wire : std_logic_vector(23 downto 0); -- Avalon_ST_Sink_data_0:output -> Binarization_Binarization_Module_0:data_in
signal binarization_binarization_module_0_data_out_wire : std_logic_vector(23 downto 0); -- Binarization_Binarization_Module_0:data_out -> Avalon_ST_Source_data_0:input
signal clock_0_clock_output_reset : std_logic; -- Clock_0:aclr_out -> Binarization_Binarization_Module_0:aclr
signal clock_0_clock_output_clk : std_logic; -- Clock_0:clock_out -> Binarization_Binarization_Module_0:Clock
begin
clock_0 : component alt_dspbuilder_clock_GNF343OQUJ
port map (
clock_out => clock_0_clock_output_clk, -- clock_output.clk
aclr_out => clock_0_clock_output_reset, -- .reset
clock => Clock, -- clock.clk
aclr_n => aclr -- .reset_n
);
avalon_st_sink_data_0 : component alt_dspbuilder_port_GNOC3SGKQJ
port map (
input => Avalon_ST_Sink_data, -- input.wire
output => avalon_st_sink_data_0_output_wire -- output.wire
);
avalon_st_sink_endofpacket_0 : component alt_dspbuilder_port_GN37ALZBS4
port map (
input => Avalon_ST_Sink_endofpacket, -- input.wire
output => avalon_st_sink_endofpacket_0_output_wire -- output.wire
);
binarization_binarization_module_0 : component Binarization_GN_Binarization_Binarization_Module
port map (
sop => avalon_st_sink_startofpacket_0_output_wire, -- sop.wire
writedata => avalon_mm_slave_writedata_0_output_wire, -- writedata.wire
eop => avalon_st_sink_endofpacket_0_output_wire, -- eop.wire
addr => avalon_mm_slave_address_0_output_wire, -- addr.wire
write => avalon_mm_slave_write_0_output_wire, -- write.wire
Clock => clock_0_clock_output_clk, -- Clock.clk
aclr => clock_0_clock_output_reset, -- .reset
data_out => binarization_binarization_module_0_data_out_wire, -- data_out.wire
data_in => avalon_st_sink_data_0_output_wire -- data_in.wire
);
avalon_mm_slave_address_0 : component alt_dspbuilder_port_GN6TDLHAW6
port map (
input => Avalon_MM_Slave_address, -- input.wire
output => avalon_mm_slave_address_0_output_wire -- output.wire
);
avalon_mm_slave_writedata_0 : component alt_dspbuilder_port_GNEPKLLZKY
port map (
input => Avalon_MM_Slave_writedata, -- input.wire
output => avalon_mm_slave_writedata_0_output_wire -- output.wire
);
avalon_st_source_valid_0 : component alt_dspbuilder_port_GN37ALZBS4
port map (
input => avalon_st_sink_valid_0_output_wire, -- input.wire
output => Avalon_ST_Source_valid -- output.wire
);
avalon_st_sink_valid_0 : component alt_dspbuilder_port_GN37ALZBS4
port map (
input => Avalon_ST_Sink_valid, -- input.wire
output => avalon_st_sink_valid_0_output_wire -- output.wire
);
avalon_st_source_endofpacket_0 : component alt_dspbuilder_port_GN37ALZBS4
port map (
input => avalon_st_sink_endofpacket_0_output_wire, -- input.wire
output => Avalon_ST_Source_endofpacket -- output.wire
);
avalon_st_source_startofpacket_0 : component alt_dspbuilder_port_GN37ALZBS4
port map (
input => avalon_st_sink_startofpacket_0_output_wire, -- input.wire
output => Avalon_ST_Source_startofpacket -- output.wire
);
avalon_st_source_ready_0 : component alt_dspbuilder_port_GN37ALZBS4
port map (
input => Avalon_ST_Source_ready, -- input.wire
output => avalon_st_source_ready_0_output_wire -- output.wire
);
avalon_mm_slave_write_0 : component alt_dspbuilder_port_GN37ALZBS4
port map (
input => Avalon_MM_Slave_write, -- input.wire
output => avalon_mm_slave_write_0_output_wire -- output.wire
);
avalon_st_sink_ready_0 : component alt_dspbuilder_port_GN37ALZBS4
port map (
input => avalon_st_source_ready_0_output_wire, -- input.wire
output => Avalon_ST_Sink_ready -- output.wire
);
avalon_st_sink_startofpacket_0 : component alt_dspbuilder_port_GN37ALZBS4
port map (
input => Avalon_ST_Sink_startofpacket, -- input.wire
output => avalon_st_sink_startofpacket_0_output_wire -- output.wire
);
avalon_st_source_data_0 : component alt_dspbuilder_port_GNOC3SGKQJ
port map (
input => binarization_binarization_module_0_data_out_wire, -- input.wire
output => Avalon_ST_Source_data -- output.wire
);
end architecture rtl; -- of Binarization_GN
| mit | 10b77fb4c813df9399112366fbdc3316 | 0.581588 | 3.42528 | false | false | false | false |
jairov4/accel-oil | solution_spartan3/impl/vhdl/sample_iterator_get_offset.vhd | 1 | 57,847 | -- ==============================================================
-- RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2013.4
-- Copyright (C) 2013 Xilinx Inc. All rights reserved.
--
-- ===========================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity sample_iterator_get_offset is
port (
ap_clk : IN STD_LOGIC;
ap_rst : IN STD_LOGIC;
ap_start : IN STD_LOGIC;
ap_done : OUT STD_LOGIC;
ap_idle : OUT STD_LOGIC;
ap_ready : OUT STD_LOGIC;
indices_stride_req_din : OUT STD_LOGIC;
indices_stride_req_full_n : IN STD_LOGIC;
indices_stride_req_write : OUT STD_LOGIC;
indices_stride_rsp_empty_n : IN STD_LOGIC;
indices_stride_rsp_read : OUT STD_LOGIC;
indices_stride_address : OUT STD_LOGIC_VECTOR (31 downto 0);
indices_stride_datain : IN STD_LOGIC_VECTOR (7 downto 0);
indices_stride_dataout : OUT STD_LOGIC_VECTOR (7 downto 0);
indices_stride_size : OUT STD_LOGIC_VECTOR (31 downto 0);
indices_begin_req_din : OUT STD_LOGIC;
indices_begin_req_full_n : IN STD_LOGIC;
indices_begin_req_write : OUT STD_LOGIC;
indices_begin_rsp_empty_n : IN STD_LOGIC;
indices_begin_rsp_read : OUT STD_LOGIC;
indices_begin_address : OUT STD_LOGIC_VECTOR (31 downto 0);
indices_begin_datain : IN STD_LOGIC_VECTOR (31 downto 0);
indices_begin_dataout : OUT STD_LOGIC_VECTOR (31 downto 0);
indices_begin_size : OUT STD_LOGIC_VECTOR (31 downto 0);
ap_ce : IN STD_LOGIC;
i_index : IN STD_LOGIC_VECTOR (15 downto 0);
i_sample : IN STD_LOGIC_VECTOR (15 downto 0);
indices_samples_req_din : OUT STD_LOGIC;
indices_samples_req_full_n : IN STD_LOGIC;
indices_samples_req_write : OUT STD_LOGIC;
indices_samples_rsp_empty_n : IN STD_LOGIC;
indices_samples_rsp_read : OUT STD_LOGIC;
indices_samples_address : OUT STD_LOGIC_VECTOR (31 downto 0);
indices_samples_datain : IN STD_LOGIC_VECTOR (15 downto 0);
indices_samples_dataout : OUT STD_LOGIC_VECTOR (15 downto 0);
indices_samples_size : OUT STD_LOGIC_VECTOR (31 downto 0);
sample_buffer_size : IN STD_LOGIC_VECTOR (31 downto 0);
sample_length : IN STD_LOGIC_VECTOR (15 downto 0);
ap_return : OUT STD_LOGIC_VECTOR (31 downto 0) );
end;
architecture behav of sample_iterator_get_offset is
constant ap_const_logic_1 : STD_LOGIC := '1';
constant ap_const_logic_0 : STD_LOGIC := '0';
constant ap_ST_pp0_stg0_fsm_0 : STD_LOGIC_VECTOR (0 downto 0) := "0";
constant ap_const_lv32_0 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000000";
constant ap_const_lv32_1 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000001";
constant ap_const_lv8_0 : STD_LOGIC_VECTOR (7 downto 0) := "00000000";
constant ap_const_lv16_0 : STD_LOGIC_VECTOR (15 downto 0) := "0000000000000000";
signal ap_CS_fsm : STD_LOGIC_VECTOR (0 downto 0) := "0";
signal ap_reg_ppiten_pp0_it0 : STD_LOGIC;
signal ap_reg_ppiten_pp0_it1 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it2 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it3 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it4 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it5 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it6 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it7 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it8 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it9 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it10 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it11 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it12 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it13 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it14 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it15 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it16 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it17 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it18 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it19 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it20 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it21 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it22 : STD_LOGIC := '0';
signal i_sample_read_reg_130 : STD_LOGIC_VECTOR (15 downto 0);
signal ap_reg_ppstg_i_sample_read_reg_130_pp0_it1 : STD_LOGIC_VECTOR (15 downto 0);
signal ap_reg_ppstg_i_sample_read_reg_130_pp0_it2 : STD_LOGIC_VECTOR (15 downto 0);
signal ap_reg_ppstg_i_sample_read_reg_130_pp0_it3 : STD_LOGIC_VECTOR (15 downto 0);
signal ap_reg_ppstg_i_sample_read_reg_130_pp0_it4 : STD_LOGIC_VECTOR (15 downto 0);
signal ap_reg_ppstg_i_sample_read_reg_130_pp0_it5 : STD_LOGIC_VECTOR (15 downto 0);
signal indices_begin_addr_reg_135 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it1 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it2 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it3 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it4 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it5 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it6 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it7 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it8 : STD_LOGIC_VECTOR (31 downto 0);
signal indices_stride_addr_read_reg_147 : STD_LOGIC_VECTOR (7 downto 0);
signal indices_begin_addr_read_reg_162 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_116_p2 : STD_LOGIC_VECTOR (23 downto 0);
signal tmp_8_reg_167 : STD_LOGIC_VECTOR (23 downto 0);
signal tmp_fu_93_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal grp_fu_116_p0 : STD_LOGIC_VECTOR (15 downto 0);
signal grp_fu_116_p1 : STD_LOGIC_VECTOR (7 downto 0);
signal grp_fu_125_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_125_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_116_ce : STD_LOGIC;
signal grp_fu_125_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_125_ce : STD_LOGIC;
signal ap_NS_fsm : STD_LOGIC_VECTOR (0 downto 0);
signal ap_sig_pprstidle_pp0 : STD_LOGIC;
signal grp_fu_116_p00 : STD_LOGIC_VECTOR (23 downto 0);
signal grp_fu_116_p10 : STD_LOGIC_VECTOR (23 downto 0);
component nfa_accept_samples_generic_hw_mul_16ns_8ns_24_9 IS
generic (
ID : INTEGER;
NUM_STAGE : INTEGER;
din0_WIDTH : INTEGER;
din1_WIDTH : INTEGER;
dout_WIDTH : INTEGER );
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
din0 : IN STD_LOGIC_VECTOR (15 downto 0);
din1 : IN STD_LOGIC_VECTOR (7 downto 0);
ce : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR (23 downto 0) );
end component;
component nfa_accept_samples_generic_hw_add_32ns_32ns_32_8 IS
generic (
ID : INTEGER;
NUM_STAGE : INTEGER;
din0_WIDTH : INTEGER;
din1_WIDTH : INTEGER;
dout_WIDTH : INTEGER );
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
din0 : IN STD_LOGIC_VECTOR (31 downto 0);
din1 : IN STD_LOGIC_VECTOR (31 downto 0);
ce : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR (31 downto 0) );
end component;
begin
nfa_accept_samples_generic_hw_mul_16ns_8ns_24_9_U0 : component nfa_accept_samples_generic_hw_mul_16ns_8ns_24_9
generic map (
ID => 0,
NUM_STAGE => 9,
din0_WIDTH => 16,
din1_WIDTH => 8,
dout_WIDTH => 24)
port map (
clk => ap_clk,
reset => ap_rst,
din0 => grp_fu_116_p0,
din1 => grp_fu_116_p1,
ce => grp_fu_116_ce,
dout => grp_fu_116_p2);
nfa_accept_samples_generic_hw_add_32ns_32ns_32_8_U1 : component nfa_accept_samples_generic_hw_add_32ns_32ns_32_8
generic map (
ID => 1,
NUM_STAGE => 8,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst,
din0 => grp_fu_125_p0,
din1 => grp_fu_125_p1,
ce => grp_fu_125_ce,
dout => grp_fu_125_p2);
-- the current state (ap_CS_fsm) of the state machine. --
ap_CS_fsm_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_CS_fsm <= ap_ST_pp0_stg0_fsm_0;
else
ap_CS_fsm <= ap_NS_fsm;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it1 assign process. --
ap_reg_ppiten_pp0_it1_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_reg_ppiten_pp0_it1 <= ap_const_logic_0;
else
if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it5) and (indices_stride_rsp_empty_n = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it14) and (indices_begin_rsp_empty_n = ap_const_logic_0)) or not((ap_const_logic_1 = ap_ce)))))) then
ap_reg_ppiten_pp0_it1 <= ap_reg_ppiten_pp0_it0;
end if;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it10 assign process. --
ap_reg_ppiten_pp0_it10_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_reg_ppiten_pp0_it10 <= ap_const_logic_0;
else
if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it5) and (indices_stride_rsp_empty_n = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it14) and (indices_begin_rsp_empty_n = ap_const_logic_0)) or not((ap_const_logic_1 = ap_ce)))))) then
ap_reg_ppiten_pp0_it10 <= ap_reg_ppiten_pp0_it9;
end if;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it11 assign process. --
ap_reg_ppiten_pp0_it11_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_reg_ppiten_pp0_it11 <= ap_const_logic_0;
else
if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it5) and (indices_stride_rsp_empty_n = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it14) and (indices_begin_rsp_empty_n = ap_const_logic_0)) or not((ap_const_logic_1 = ap_ce)))))) then
ap_reg_ppiten_pp0_it11 <= ap_reg_ppiten_pp0_it10;
end if;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it12 assign process. --
ap_reg_ppiten_pp0_it12_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_reg_ppiten_pp0_it12 <= ap_const_logic_0;
else
if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it5) and (indices_stride_rsp_empty_n = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it14) and (indices_begin_rsp_empty_n = ap_const_logic_0)) or not((ap_const_logic_1 = ap_ce)))))) then
ap_reg_ppiten_pp0_it12 <= ap_reg_ppiten_pp0_it11;
end if;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it13 assign process. --
ap_reg_ppiten_pp0_it13_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_reg_ppiten_pp0_it13 <= ap_const_logic_0;
else
if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it5) and (indices_stride_rsp_empty_n = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it14) and (indices_begin_rsp_empty_n = ap_const_logic_0)) or not((ap_const_logic_1 = ap_ce)))))) then
ap_reg_ppiten_pp0_it13 <= ap_reg_ppiten_pp0_it12;
end if;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it14 assign process. --
ap_reg_ppiten_pp0_it14_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_reg_ppiten_pp0_it14 <= ap_const_logic_0;
else
if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it5) and (indices_stride_rsp_empty_n = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it14) and (indices_begin_rsp_empty_n = ap_const_logic_0)) or not((ap_const_logic_1 = ap_ce)))))) then
ap_reg_ppiten_pp0_it14 <= ap_reg_ppiten_pp0_it13;
end if;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it15 assign process. --
ap_reg_ppiten_pp0_it15_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_reg_ppiten_pp0_it15 <= ap_const_logic_0;
else
if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it5) and (indices_stride_rsp_empty_n = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it14) and (indices_begin_rsp_empty_n = ap_const_logic_0)) or not((ap_const_logic_1 = ap_ce)))))) then
ap_reg_ppiten_pp0_it15 <= ap_reg_ppiten_pp0_it14;
end if;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it16 assign process. --
ap_reg_ppiten_pp0_it16_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_reg_ppiten_pp0_it16 <= ap_const_logic_0;
else
if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it5) and (indices_stride_rsp_empty_n = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it14) and (indices_begin_rsp_empty_n = ap_const_logic_0)) or not((ap_const_logic_1 = ap_ce)))))) then
ap_reg_ppiten_pp0_it16 <= ap_reg_ppiten_pp0_it15;
end if;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it17 assign process. --
ap_reg_ppiten_pp0_it17_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_reg_ppiten_pp0_it17 <= ap_const_logic_0;
else
if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it5) and (indices_stride_rsp_empty_n = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it14) and (indices_begin_rsp_empty_n = ap_const_logic_0)) or not((ap_const_logic_1 = ap_ce)))))) then
ap_reg_ppiten_pp0_it17 <= ap_reg_ppiten_pp0_it16;
end if;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it18 assign process. --
ap_reg_ppiten_pp0_it18_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_reg_ppiten_pp0_it18 <= ap_const_logic_0;
else
if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it5) and (indices_stride_rsp_empty_n = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it14) and (indices_begin_rsp_empty_n = ap_const_logic_0)) or not((ap_const_logic_1 = ap_ce)))))) then
ap_reg_ppiten_pp0_it18 <= ap_reg_ppiten_pp0_it17;
end if;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it19 assign process. --
ap_reg_ppiten_pp0_it19_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_reg_ppiten_pp0_it19 <= ap_const_logic_0;
else
if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it5) and (indices_stride_rsp_empty_n = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it14) and (indices_begin_rsp_empty_n = ap_const_logic_0)) or not((ap_const_logic_1 = ap_ce)))))) then
ap_reg_ppiten_pp0_it19 <= ap_reg_ppiten_pp0_it18;
end if;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it2 assign process. --
ap_reg_ppiten_pp0_it2_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_reg_ppiten_pp0_it2 <= ap_const_logic_0;
else
if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it5) and (indices_stride_rsp_empty_n = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it14) and (indices_begin_rsp_empty_n = ap_const_logic_0)) or not((ap_const_logic_1 = ap_ce)))))) then
ap_reg_ppiten_pp0_it2 <= ap_reg_ppiten_pp0_it1;
end if;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it20 assign process. --
ap_reg_ppiten_pp0_it20_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_reg_ppiten_pp0_it20 <= ap_const_logic_0;
else
if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it5) and (indices_stride_rsp_empty_n = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it14) and (indices_begin_rsp_empty_n = ap_const_logic_0)) or not((ap_const_logic_1 = ap_ce)))))) then
ap_reg_ppiten_pp0_it20 <= ap_reg_ppiten_pp0_it19;
end if;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it21 assign process. --
ap_reg_ppiten_pp0_it21_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_reg_ppiten_pp0_it21 <= ap_const_logic_0;
else
if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it5) and (indices_stride_rsp_empty_n = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it14) and (indices_begin_rsp_empty_n = ap_const_logic_0)) or not((ap_const_logic_1 = ap_ce)))))) then
ap_reg_ppiten_pp0_it21 <= ap_reg_ppiten_pp0_it20;
end if;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it22 assign process. --
ap_reg_ppiten_pp0_it22_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_reg_ppiten_pp0_it22 <= ap_const_logic_0;
else
if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it5) and (indices_stride_rsp_empty_n = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it14) and (indices_begin_rsp_empty_n = ap_const_logic_0)) or not((ap_const_logic_1 = ap_ce)))))) then
ap_reg_ppiten_pp0_it22 <= ap_reg_ppiten_pp0_it21;
end if;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it3 assign process. --
ap_reg_ppiten_pp0_it3_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_reg_ppiten_pp0_it3 <= ap_const_logic_0;
else
if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it5) and (indices_stride_rsp_empty_n = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it14) and (indices_begin_rsp_empty_n = ap_const_logic_0)) or not((ap_const_logic_1 = ap_ce)))))) then
ap_reg_ppiten_pp0_it3 <= ap_reg_ppiten_pp0_it2;
end if;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it4 assign process. --
ap_reg_ppiten_pp0_it4_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_reg_ppiten_pp0_it4 <= ap_const_logic_0;
else
if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it5) and (indices_stride_rsp_empty_n = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it14) and (indices_begin_rsp_empty_n = ap_const_logic_0)) or not((ap_const_logic_1 = ap_ce)))))) then
ap_reg_ppiten_pp0_it4 <= ap_reg_ppiten_pp0_it3;
end if;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it5 assign process. --
ap_reg_ppiten_pp0_it5_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_reg_ppiten_pp0_it5 <= ap_const_logic_0;
else
if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it5) and (indices_stride_rsp_empty_n = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it14) and (indices_begin_rsp_empty_n = ap_const_logic_0)) or not((ap_const_logic_1 = ap_ce)))))) then
ap_reg_ppiten_pp0_it5 <= ap_reg_ppiten_pp0_it4;
end if;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it6 assign process. --
ap_reg_ppiten_pp0_it6_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_reg_ppiten_pp0_it6 <= ap_const_logic_0;
else
if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it5) and (indices_stride_rsp_empty_n = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it14) and (indices_begin_rsp_empty_n = ap_const_logic_0)) or not((ap_const_logic_1 = ap_ce)))))) then
ap_reg_ppiten_pp0_it6 <= ap_reg_ppiten_pp0_it5;
end if;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it7 assign process. --
ap_reg_ppiten_pp0_it7_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_reg_ppiten_pp0_it7 <= ap_const_logic_0;
else
if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it5) and (indices_stride_rsp_empty_n = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it14) and (indices_begin_rsp_empty_n = ap_const_logic_0)) or not((ap_const_logic_1 = ap_ce)))))) then
ap_reg_ppiten_pp0_it7 <= ap_reg_ppiten_pp0_it6;
end if;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it8 assign process. --
ap_reg_ppiten_pp0_it8_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_reg_ppiten_pp0_it8 <= ap_const_logic_0;
else
if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it5) and (indices_stride_rsp_empty_n = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it14) and (indices_begin_rsp_empty_n = ap_const_logic_0)) or not((ap_const_logic_1 = ap_ce)))))) then
ap_reg_ppiten_pp0_it8 <= ap_reg_ppiten_pp0_it7;
end if;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it9 assign process. --
ap_reg_ppiten_pp0_it9_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_reg_ppiten_pp0_it9 <= ap_const_logic_0;
else
if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it5) and (indices_stride_rsp_empty_n = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it14) and (indices_begin_rsp_empty_n = ap_const_logic_0)) or not((ap_const_logic_1 = ap_ce)))))) then
ap_reg_ppiten_pp0_it9 <= ap_reg_ppiten_pp0_it8;
end if;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it5) and (indices_stride_rsp_empty_n = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it14) and (indices_begin_rsp_empty_n = ap_const_logic_0)))) and (ap_const_logic_1 = ap_ce))) then
ap_reg_ppstg_i_sample_read_reg_130_pp0_it1 <= i_sample_read_reg_130;
ap_reg_ppstg_i_sample_read_reg_130_pp0_it2 <= ap_reg_ppstg_i_sample_read_reg_130_pp0_it1;
ap_reg_ppstg_i_sample_read_reg_130_pp0_it3 <= ap_reg_ppstg_i_sample_read_reg_130_pp0_it2;
ap_reg_ppstg_i_sample_read_reg_130_pp0_it4 <= ap_reg_ppstg_i_sample_read_reg_130_pp0_it3;
ap_reg_ppstg_i_sample_read_reg_130_pp0_it5 <= ap_reg_ppstg_i_sample_read_reg_130_pp0_it4;
ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it1(0) <= indices_begin_addr_reg_135(0);
ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it1(1) <= indices_begin_addr_reg_135(1);
ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it1(2) <= indices_begin_addr_reg_135(2);
ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it1(3) <= indices_begin_addr_reg_135(3);
ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it1(4) <= indices_begin_addr_reg_135(4);
ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it1(5) <= indices_begin_addr_reg_135(5);
ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it1(6) <= indices_begin_addr_reg_135(6);
ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it1(7) <= indices_begin_addr_reg_135(7);
ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it1(8) <= indices_begin_addr_reg_135(8);
ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it1(9) <= indices_begin_addr_reg_135(9);
ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it1(10) <= indices_begin_addr_reg_135(10);
ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it1(11) <= indices_begin_addr_reg_135(11);
ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it1(12) <= indices_begin_addr_reg_135(12);
ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it1(13) <= indices_begin_addr_reg_135(13);
ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it1(14) <= indices_begin_addr_reg_135(14);
ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it1(15) <= indices_begin_addr_reg_135(15);
ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it2(0) <= ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it1(0);
ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it2(1) <= ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it1(1);
ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it2(2) <= ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it1(2);
ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it2(3) <= ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it1(3);
ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it2(4) <= ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it1(4);
ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it2(5) <= ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it1(5);
ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it2(6) <= ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it1(6);
ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it2(7) <= ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it1(7);
ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it2(8) <= ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it1(8);
ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it2(9) <= ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it1(9);
ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it2(10) <= ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it1(10);
ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it2(11) <= ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it1(11);
ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it2(12) <= ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it1(12);
ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it2(13) <= ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it1(13);
ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it2(14) <= ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it1(14);
ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it2(15) <= ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it1(15);
ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it3(0) <= ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it2(0);
ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it3(1) <= ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it2(1);
ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it3(2) <= ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it2(2);
ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it3(3) <= ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it2(3);
ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it3(4) <= ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it2(4);
ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it3(5) <= ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it2(5);
ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it3(6) <= ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it2(6);
ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it3(7) <= ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it2(7);
ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it3(8) <= ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it2(8);
ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it3(9) <= ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it2(9);
ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it3(10) <= ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it2(10);
ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it3(11) <= ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it2(11);
ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it3(12) <= ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it2(12);
ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it3(13) <= ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it2(13);
ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it3(14) <= ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it2(14);
ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it3(15) <= ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it2(15);
ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it4(0) <= ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it3(0);
ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it4(1) <= ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it3(1);
ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it4(2) <= ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it3(2);
ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it4(3) <= ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it3(3);
ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it4(4) <= ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it3(4);
ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it4(5) <= ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it3(5);
ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it4(6) <= ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it3(6);
ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it4(7) <= ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it3(7);
ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it4(8) <= ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it3(8);
ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it4(9) <= ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it3(9);
ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it4(10) <= ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it3(10);
ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it4(11) <= ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it3(11);
ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it4(12) <= ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it3(12);
ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it4(13) <= ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it3(13);
ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it4(14) <= ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it3(14);
ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it4(15) <= ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it3(15);
ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it5(0) <= ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it4(0);
ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it5(1) <= ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it4(1);
ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it5(2) <= ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it4(2);
ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it5(3) <= ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it4(3);
ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it5(4) <= ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it4(4);
ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it5(5) <= ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it4(5);
ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it5(6) <= ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it4(6);
ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it5(7) <= ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it4(7);
ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it5(8) <= ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it4(8);
ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it5(9) <= ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it4(9);
ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it5(10) <= ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it4(10);
ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it5(11) <= ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it4(11);
ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it5(12) <= ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it4(12);
ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it5(13) <= ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it4(13);
ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it5(14) <= ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it4(14);
ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it5(15) <= ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it4(15);
ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it6(0) <= ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it5(0);
ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it6(1) <= ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it5(1);
ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it6(2) <= ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it5(2);
ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it6(3) <= ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it5(3);
ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it6(4) <= ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it5(4);
ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it6(5) <= ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it5(5);
ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it6(6) <= ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it5(6);
ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it6(7) <= ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it5(7);
ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it6(8) <= ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it5(8);
ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it6(9) <= ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it5(9);
ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it6(10) <= ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it5(10);
ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it6(11) <= ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it5(11);
ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it6(12) <= ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it5(12);
ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it6(13) <= ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it5(13);
ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it6(14) <= ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it5(14);
ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it6(15) <= ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it5(15);
ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it7(0) <= ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it6(0);
ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it7(1) <= ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it6(1);
ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it7(2) <= ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it6(2);
ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it7(3) <= ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it6(3);
ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it7(4) <= ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it6(4);
ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it7(5) <= ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it6(5);
ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it7(6) <= ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it6(6);
ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it7(7) <= ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it6(7);
ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it7(8) <= ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it6(8);
ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it7(9) <= ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it6(9);
ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it7(10) <= ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it6(10);
ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it7(11) <= ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it6(11);
ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it7(12) <= ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it6(12);
ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it7(13) <= ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it6(13);
ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it7(14) <= ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it6(14);
ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it7(15) <= ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it6(15);
ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it8(0) <= ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it7(0);
ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it8(1) <= ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it7(1);
ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it8(2) <= ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it7(2);
ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it8(3) <= ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it7(3);
ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it8(4) <= ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it7(4);
ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it8(5) <= ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it7(5);
ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it8(6) <= ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it7(6);
ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it8(7) <= ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it7(7);
ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it8(8) <= ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it7(8);
ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it8(9) <= ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it7(9);
ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it8(10) <= ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it7(10);
ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it8(11) <= ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it7(11);
ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it8(12) <= ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it7(12);
ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it8(13) <= ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it7(13);
ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it8(14) <= ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it7(14);
ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it8(15) <= ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it7(15);
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it5) and (indices_stride_rsp_empty_n = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it14) and (indices_begin_rsp_empty_n = ap_const_logic_0)))) and (ap_const_logic_1 = ap_ce))) then
i_sample_read_reg_130 <= i_sample;
indices_begin_addr_reg_135(0) <= tmp_fu_93_p1(32 - 1 downto 0)(0);
indices_begin_addr_reg_135(1) <= tmp_fu_93_p1(32 - 1 downto 0)(1);
indices_begin_addr_reg_135(2) <= tmp_fu_93_p1(32 - 1 downto 0)(2);
indices_begin_addr_reg_135(3) <= tmp_fu_93_p1(32 - 1 downto 0)(3);
indices_begin_addr_reg_135(4) <= tmp_fu_93_p1(32 - 1 downto 0)(4);
indices_begin_addr_reg_135(5) <= tmp_fu_93_p1(32 - 1 downto 0)(5);
indices_begin_addr_reg_135(6) <= tmp_fu_93_p1(32 - 1 downto 0)(6);
indices_begin_addr_reg_135(7) <= tmp_fu_93_p1(32 - 1 downto 0)(7);
indices_begin_addr_reg_135(8) <= tmp_fu_93_p1(32 - 1 downto 0)(8);
indices_begin_addr_reg_135(9) <= tmp_fu_93_p1(32 - 1 downto 0)(9);
indices_begin_addr_reg_135(10) <= tmp_fu_93_p1(32 - 1 downto 0)(10);
indices_begin_addr_reg_135(11) <= tmp_fu_93_p1(32 - 1 downto 0)(11);
indices_begin_addr_reg_135(12) <= tmp_fu_93_p1(32 - 1 downto 0)(12);
indices_begin_addr_reg_135(13) <= tmp_fu_93_p1(32 - 1 downto 0)(13);
indices_begin_addr_reg_135(14) <= tmp_fu_93_p1(32 - 1 downto 0)(14);
indices_begin_addr_reg_135(15) <= tmp_fu_93_p1(32 - 1 downto 0)(15);
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it14) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it5) and (indices_stride_rsp_empty_n = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it14) and (indices_begin_rsp_empty_n = ap_const_logic_0)))) and (ap_const_logic_1 = ap_ce))) then
indices_begin_addr_read_reg_162 <= indices_begin_datain;
tmp_8_reg_167 <= grp_fu_116_p2;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it5) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it5) and (indices_stride_rsp_empty_n = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it14) and (indices_begin_rsp_empty_n = ap_const_logic_0)))) and (ap_const_logic_1 = ap_ce))) then
indices_stride_addr_read_reg_147 <= indices_stride_datain;
end if;
end if;
end process;
indices_begin_addr_reg_135(31 downto 16) <= "0000000000000000";
ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it1(31 downto 16) <= "0000000000000000";
ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it2(31 downto 16) <= "0000000000000000";
ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it3(31 downto 16) <= "0000000000000000";
ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it4(31 downto 16) <= "0000000000000000";
ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it5(31 downto 16) <= "0000000000000000";
ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it6(31 downto 16) <= "0000000000000000";
ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it7(31 downto 16) <= "0000000000000000";
ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it8(31 downto 16) <= "0000000000000000";
-- the next state (ap_NS_fsm) of the state machine. --
ap_NS_fsm_assign_proc : process (ap_start , ap_CS_fsm , ap_reg_ppiten_pp0_it0 , ap_reg_ppiten_pp0_it5 , ap_reg_ppiten_pp0_it14 , indices_stride_rsp_empty_n , indices_begin_rsp_empty_n , ap_ce , ap_sig_pprstidle_pp0)
begin
case ap_CS_fsm is
when ap_ST_pp0_stg0_fsm_0 =>
ap_NS_fsm <= ap_ST_pp0_stg0_fsm_0;
when others =>
ap_NS_fsm <= "X";
end case;
end process;
-- ap_done assign process. --
ap_done_assign_proc : process(ap_start, ap_CS_fsm, ap_reg_ppiten_pp0_it0, ap_reg_ppiten_pp0_it5, ap_reg_ppiten_pp0_it14, ap_reg_ppiten_pp0_it22, indices_stride_rsp_empty_n, indices_begin_rsp_empty_n, ap_ce)
begin
if (((not((ap_const_logic_1 = ap_start)) and (ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it0)) or ((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it22) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it5) and (indices_stride_rsp_empty_n = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it14) and (indices_begin_rsp_empty_n = ap_const_logic_0)))) and (ap_const_logic_1 = ap_ce)))) then
ap_done <= ap_const_logic_1;
else
ap_done <= ap_const_logic_0;
end if;
end process;
-- ap_idle assign process. --
ap_idle_assign_proc : process(ap_start, ap_CS_fsm, ap_reg_ppiten_pp0_it0, ap_reg_ppiten_pp0_it1, ap_reg_ppiten_pp0_it2, ap_reg_ppiten_pp0_it3, ap_reg_ppiten_pp0_it4, ap_reg_ppiten_pp0_it5, ap_reg_ppiten_pp0_it6, ap_reg_ppiten_pp0_it7, ap_reg_ppiten_pp0_it8, ap_reg_ppiten_pp0_it9, ap_reg_ppiten_pp0_it10, ap_reg_ppiten_pp0_it11, ap_reg_ppiten_pp0_it12, ap_reg_ppiten_pp0_it13, ap_reg_ppiten_pp0_it14, ap_reg_ppiten_pp0_it15, ap_reg_ppiten_pp0_it16, ap_reg_ppiten_pp0_it17, ap_reg_ppiten_pp0_it18, ap_reg_ppiten_pp0_it19, ap_reg_ppiten_pp0_it20, ap_reg_ppiten_pp0_it21, ap_reg_ppiten_pp0_it22)
begin
if ((not((ap_const_logic_1 = ap_start)) and (ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it0) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it1) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it2) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it3) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it4) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it5) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it6) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it7) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it8) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it9) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it10) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it11) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it12) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it13) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it14) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it15) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it16) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it17) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it18) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it19) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it20) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it21) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it22))) then
ap_idle <= ap_const_logic_1;
else
ap_idle <= ap_const_logic_0;
end if;
end process;
-- ap_ready assign process. --
ap_ready_assign_proc : process(ap_start, ap_CS_fsm, ap_reg_ppiten_pp0_it0, ap_reg_ppiten_pp0_it5, ap_reg_ppiten_pp0_it14, indices_stride_rsp_empty_n, indices_begin_rsp_empty_n, ap_ce)
begin
if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it5) and (indices_stride_rsp_empty_n = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it14) and (indices_begin_rsp_empty_n = ap_const_logic_0)))) and (ap_const_logic_1 = ap_ce))) then
ap_ready <= ap_const_logic_1;
else
ap_ready <= ap_const_logic_0;
end if;
end process;
ap_reg_ppiten_pp0_it0 <= ap_start;
ap_return <= grp_fu_125_p2;
-- ap_sig_pprstidle_pp0 assign process. --
ap_sig_pprstidle_pp0_assign_proc : process(ap_start, ap_reg_ppiten_pp0_it0, ap_reg_ppiten_pp0_it1, ap_reg_ppiten_pp0_it2, ap_reg_ppiten_pp0_it3, ap_reg_ppiten_pp0_it4, ap_reg_ppiten_pp0_it5, ap_reg_ppiten_pp0_it6, ap_reg_ppiten_pp0_it7, ap_reg_ppiten_pp0_it8, ap_reg_ppiten_pp0_it9, ap_reg_ppiten_pp0_it10, ap_reg_ppiten_pp0_it11, ap_reg_ppiten_pp0_it12, ap_reg_ppiten_pp0_it13, ap_reg_ppiten_pp0_it14, ap_reg_ppiten_pp0_it15, ap_reg_ppiten_pp0_it16, ap_reg_ppiten_pp0_it17, ap_reg_ppiten_pp0_it18, ap_reg_ppiten_pp0_it19, ap_reg_ppiten_pp0_it20, ap_reg_ppiten_pp0_it21)
begin
if (((ap_const_logic_0 = ap_reg_ppiten_pp0_it0) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it1) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it2) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it3) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it4) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it5) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it6) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it7) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it8) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it9) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it10) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it11) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it12) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it13) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it14) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it15) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it16) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it17) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it18) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it19) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it20) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it21) and (ap_const_logic_0 = ap_start))) then
ap_sig_pprstidle_pp0 <= ap_const_logic_1;
else
ap_sig_pprstidle_pp0 <= ap_const_logic_0;
end if;
end process;
-- grp_fu_116_ce assign process. --
grp_fu_116_ce_assign_proc : process(ap_start, ap_CS_fsm, ap_reg_ppiten_pp0_it0, ap_reg_ppiten_pp0_it5, ap_reg_ppiten_pp0_it14, indices_stride_rsp_empty_n, indices_begin_rsp_empty_n, ap_ce)
begin
if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it5) and (indices_stride_rsp_empty_n = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it14) and (indices_begin_rsp_empty_n = ap_const_logic_0)))) and (ap_const_logic_1 = ap_ce))) then
grp_fu_116_ce <= ap_const_logic_1;
else
grp_fu_116_ce <= ap_const_logic_0;
end if;
end process;
grp_fu_116_p0 <= grp_fu_116_p00(16 - 1 downto 0);
grp_fu_116_p00 <= std_logic_vector(resize(unsigned(ap_reg_ppstg_i_sample_read_reg_130_pp0_it5),24));
grp_fu_116_p1 <= grp_fu_116_p10(8 - 1 downto 0);
grp_fu_116_p10 <= std_logic_vector(resize(unsigned(indices_stride_addr_read_reg_147),24));
-- grp_fu_125_ce assign process. --
grp_fu_125_ce_assign_proc : process(ap_start, ap_CS_fsm, ap_reg_ppiten_pp0_it0, ap_reg_ppiten_pp0_it5, ap_reg_ppiten_pp0_it14, indices_stride_rsp_empty_n, indices_begin_rsp_empty_n, ap_ce)
begin
if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it5) and (indices_stride_rsp_empty_n = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it14) and (indices_begin_rsp_empty_n = ap_const_logic_0)))) and (ap_const_logic_1 = ap_ce))) then
grp_fu_125_ce <= ap_const_logic_1;
else
grp_fu_125_ce <= ap_const_logic_0;
end if;
end process;
grp_fu_125_p0 <= std_logic_vector(resize(unsigned(tmp_8_reg_167),32));
grp_fu_125_p1 <= indices_begin_addr_read_reg_162;
indices_begin_address <= ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it8;
indices_begin_dataout <= ap_const_lv32_0;
indices_begin_req_din <= ap_const_logic_0;
-- indices_begin_req_write assign process. --
indices_begin_req_write_assign_proc : process(ap_start, ap_CS_fsm, ap_reg_ppiten_pp0_it0, ap_reg_ppiten_pp0_it5, ap_reg_ppiten_pp0_it9, ap_reg_ppiten_pp0_it14, indices_stride_rsp_empty_n, indices_begin_rsp_empty_n, ap_ce)
begin
if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it9) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it5) and (indices_stride_rsp_empty_n = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it14) and (indices_begin_rsp_empty_n = ap_const_logic_0)))) and (ap_const_logic_1 = ap_ce))) then
indices_begin_req_write <= ap_const_logic_1;
else
indices_begin_req_write <= ap_const_logic_0;
end if;
end process;
-- indices_begin_rsp_read assign process. --
indices_begin_rsp_read_assign_proc : process(ap_start, ap_CS_fsm, ap_reg_ppiten_pp0_it0, ap_reg_ppiten_pp0_it5, ap_reg_ppiten_pp0_it14, indices_stride_rsp_empty_n, indices_begin_rsp_empty_n, ap_ce)
begin
if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it14) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it5) and (indices_stride_rsp_empty_n = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it14) and (indices_begin_rsp_empty_n = ap_const_logic_0)))) and (ap_const_logic_1 = ap_ce))) then
indices_begin_rsp_read <= ap_const_logic_1;
else
indices_begin_rsp_read <= ap_const_logic_0;
end if;
end process;
indices_begin_size <= ap_const_lv32_1;
indices_samples_address <= ap_const_lv32_0;
indices_samples_dataout <= ap_const_lv16_0;
indices_samples_req_din <= ap_const_logic_0;
indices_samples_req_write <= ap_const_logic_0;
indices_samples_rsp_read <= ap_const_logic_0;
indices_samples_size <= ap_const_lv32_0;
indices_stride_address <= tmp_fu_93_p1(32 - 1 downto 0);
indices_stride_dataout <= ap_const_lv8_0;
indices_stride_req_din <= ap_const_logic_0;
-- indices_stride_req_write assign process. --
indices_stride_req_write_assign_proc : process(ap_start, ap_CS_fsm, ap_reg_ppiten_pp0_it0, ap_reg_ppiten_pp0_it5, ap_reg_ppiten_pp0_it14, indices_stride_rsp_empty_n, indices_begin_rsp_empty_n, ap_ce)
begin
if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it5) and (indices_stride_rsp_empty_n = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it14) and (indices_begin_rsp_empty_n = ap_const_logic_0)))) and (ap_const_logic_1 = ap_ce))) then
indices_stride_req_write <= ap_const_logic_1;
else
indices_stride_req_write <= ap_const_logic_0;
end if;
end process;
-- indices_stride_rsp_read assign process. --
indices_stride_rsp_read_assign_proc : process(ap_start, ap_CS_fsm, ap_reg_ppiten_pp0_it0, ap_reg_ppiten_pp0_it5, ap_reg_ppiten_pp0_it14, indices_stride_rsp_empty_n, indices_begin_rsp_empty_n, ap_ce)
begin
if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it5) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it5) and (indices_stride_rsp_empty_n = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it14) and (indices_begin_rsp_empty_n = ap_const_logic_0)))) and (ap_const_logic_1 = ap_ce))) then
indices_stride_rsp_read <= ap_const_logic_1;
else
indices_stride_rsp_read <= ap_const_logic_0;
end if;
end process;
indices_stride_size <= ap_const_lv32_1;
tmp_fu_93_p1 <= std_logic_vector(resize(unsigned(i_index),64));
end behav;
| lgpl-3.0 | a47f2f8ee5f4499345d0c6e0629f51e0 | 0.629955 | 2.56801 | false | false | false | false |
jairov4/accel-oil | solution_virtex5_plb/impl/vhdl/sample_iterator_next.vhd | 1 | 14,025 | -- ==============================================================
-- RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2014.1
-- Copyright (C) 2014 Xilinx Inc. All rights reserved.
--
-- ===========================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity sample_iterator_next is
port (
ap_clk : IN STD_LOGIC;
ap_rst : IN STD_LOGIC;
ap_start : IN STD_LOGIC;
ap_done : OUT STD_LOGIC;
ap_idle : OUT STD_LOGIC;
ap_ready : OUT STD_LOGIC;
indices_req_din : OUT STD_LOGIC;
indices_req_full_n : IN STD_LOGIC;
indices_req_write : OUT STD_LOGIC;
indices_rsp_empty_n : IN STD_LOGIC;
indices_rsp_read : OUT STD_LOGIC;
indices_address : OUT STD_LOGIC_VECTOR (31 downto 0);
indices_datain : IN STD_LOGIC_VECTOR (55 downto 0);
indices_dataout : OUT STD_LOGIC_VECTOR (55 downto 0);
indices_size : OUT STD_LOGIC_VECTOR (31 downto 0);
ap_ce : IN STD_LOGIC;
i_index : IN STD_LOGIC_VECTOR (15 downto 0);
i_sample : IN STD_LOGIC_VECTOR (15 downto 0);
ap_return_0 : OUT STD_LOGIC_VECTOR (15 downto 0);
ap_return_1 : OUT STD_LOGIC_VECTOR (15 downto 0) );
end;
architecture behav of sample_iterator_next is
constant ap_const_logic_1 : STD_LOGIC := '1';
constant ap_const_logic_0 : STD_LOGIC := '0';
constant ap_ST_pp0_stg0_fsm_0 : STD_LOGIC_VECTOR (0 downto 0) := "0";
constant ap_const_lv32_1 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000001";
constant ap_const_lv32_20 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000100000";
constant ap_const_lv32_2F : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000101111";
constant ap_const_lv17_1FFFF : STD_LOGIC_VECTOR (16 downto 0) := "11111111111111111";
constant ap_const_lv16_1 : STD_LOGIC_VECTOR (15 downto 0) := "0000000000000001";
constant ap_const_lv16_0 : STD_LOGIC_VECTOR (15 downto 0) := "0000000000000000";
constant ap_const_lv56_0 : STD_LOGIC_VECTOR (55 downto 0) := "00000000000000000000000000000000000000000000000000000000";
signal ap_CS_fsm : STD_LOGIC_VECTOR (0 downto 0) := "0";
signal ap_reg_ppiten_pp0_it0 : STD_LOGIC;
signal ap_reg_ppiten_pp0_it1 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it2 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it3 : STD_LOGIC := '0';
signal i_sample_read_reg_147 : STD_LOGIC_VECTOR (15 downto 0);
signal ap_reg_ppstg_i_sample_read_reg_147_pp0_it1 : STD_LOGIC_VECTOR (15 downto 0);
signal ap_reg_ppstg_i_sample_read_reg_147_pp0_it2 : STD_LOGIC_VECTOR (15 downto 0);
signal i_index_read_reg_153 : STD_LOGIC_VECTOR (15 downto 0);
signal ap_reg_ppstg_i_index_read_reg_153_pp0_it1 : STD_LOGIC_VECTOR (15 downto 0);
signal ap_reg_ppstg_i_index_read_reg_153_pp0_it2 : STD_LOGIC_VECTOR (15 downto 0);
signal indices_samples_load_new5_reg_165 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_s_fu_67_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_6_cast_fu_91_p1 : STD_LOGIC_VECTOR (16 downto 0);
signal tmp_7_fu_94_p2 : STD_LOGIC_VECTOR (16 downto 0);
signal tmp_cast_fu_88_p1 : STD_LOGIC_VECTOR (17 downto 0);
signal tmp_8_fu_104_p1 : STD_LOGIC_VECTOR (17 downto 0);
signal tmp_7_fu_94_p2_temp: signed (17-1 downto 0);
signal tmp_8_fu_104_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_1_fu_115_p2 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_9_fu_110_p2 : STD_LOGIC_VECTOR (15 downto 0);
signal agg_result_index_write_assign_fu_128_p3 : STD_LOGIC_VECTOR (15 downto 0);
signal agg_result_sample_write_assign_fu_120_p3 : STD_LOGIC_VECTOR (15 downto 0);
signal ap_NS_fsm : STD_LOGIC_VECTOR (0 downto 0);
signal ap_sig_pprstidle_pp0 : STD_LOGIC;
begin
-- the current state (ap_CS_fsm) of the state machine. --
ap_CS_fsm_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_CS_fsm <= ap_ST_pp0_stg0_fsm_0;
else
ap_CS_fsm <= ap_NS_fsm;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it1 assign process. --
ap_reg_ppiten_pp0_it1_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_reg_ppiten_pp0_it1 <= ap_const_logic_0;
else
if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it2) and (indices_rsp_empty_n = ap_const_logic_0)) or not((ap_const_logic_1 = ap_ce)))))) then
ap_reg_ppiten_pp0_it1 <= ap_reg_ppiten_pp0_it0;
end if;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it2 assign process. --
ap_reg_ppiten_pp0_it2_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_reg_ppiten_pp0_it2 <= ap_const_logic_0;
else
if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it2) and (indices_rsp_empty_n = ap_const_logic_0)) or not((ap_const_logic_1 = ap_ce)))))) then
ap_reg_ppiten_pp0_it2 <= ap_reg_ppiten_pp0_it1;
end if;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it3 assign process. --
ap_reg_ppiten_pp0_it3_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_reg_ppiten_pp0_it3 <= ap_const_logic_0;
else
if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it2) and (indices_rsp_empty_n = ap_const_logic_0)) or not((ap_const_logic_1 = ap_ce)))))) then
ap_reg_ppiten_pp0_it3 <= ap_reg_ppiten_pp0_it2;
end if;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it2) and (indices_rsp_empty_n = ap_const_logic_0)))) and (ap_const_logic_1 = ap_ce))) then
ap_reg_ppstg_i_index_read_reg_153_pp0_it1 <= i_index_read_reg_153;
ap_reg_ppstg_i_index_read_reg_153_pp0_it2 <= ap_reg_ppstg_i_index_read_reg_153_pp0_it1;
ap_reg_ppstg_i_sample_read_reg_147_pp0_it1 <= i_sample_read_reg_147;
ap_reg_ppstg_i_sample_read_reg_147_pp0_it2 <= ap_reg_ppstg_i_sample_read_reg_147_pp0_it1;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it2) and (indices_rsp_empty_n = ap_const_logic_0)))) and (ap_const_logic_1 = ap_ce))) then
i_index_read_reg_153 <= i_index;
i_sample_read_reg_147 <= i_sample;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it2) and (indices_rsp_empty_n = ap_const_logic_0)))) and (ap_const_logic_1 = ap_ce))) then
indices_samples_load_new5_reg_165 <= indices_datain(47 downto 32);
end if;
end if;
end process;
-- the next state (ap_NS_fsm) of the state machine. --
ap_NS_fsm_assign_proc : process (ap_start , ap_CS_fsm , ap_reg_ppiten_pp0_it0 , ap_reg_ppiten_pp0_it2 , indices_rsp_empty_n , ap_ce , ap_sig_pprstidle_pp0)
begin
case ap_CS_fsm is
when ap_ST_pp0_stg0_fsm_0 =>
ap_NS_fsm <= ap_ST_pp0_stg0_fsm_0;
when others =>
ap_NS_fsm <= "X";
end case;
end process;
agg_result_index_write_assign_fu_128_p3 <=
ap_reg_ppstg_i_index_read_reg_153_pp0_it2 when (tmp_8_fu_104_p2(0) = '1') else
tmp_9_fu_110_p2;
agg_result_sample_write_assign_fu_120_p3 <=
tmp_1_fu_115_p2 when (tmp_8_fu_104_p2(0) = '1') else
ap_const_lv16_0;
-- ap_done assign process. --
ap_done_assign_proc : process(ap_start, ap_CS_fsm, ap_reg_ppiten_pp0_it0, ap_reg_ppiten_pp0_it2, ap_reg_ppiten_pp0_it3, indices_rsp_empty_n, ap_ce)
begin
if (((not((ap_const_logic_1 = ap_start)) and (ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it0)) or ((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it3) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it2) and (indices_rsp_empty_n = ap_const_logic_0)))) and (ap_const_logic_1 = ap_ce)))) then
ap_done <= ap_const_logic_1;
else
ap_done <= ap_const_logic_0;
end if;
end process;
-- ap_idle assign process. --
ap_idle_assign_proc : process(ap_start, ap_CS_fsm, ap_reg_ppiten_pp0_it0, ap_reg_ppiten_pp0_it1, ap_reg_ppiten_pp0_it2, ap_reg_ppiten_pp0_it3)
begin
if ((not((ap_const_logic_1 = ap_start)) and (ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it0) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it1) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it2) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it3))) then
ap_idle <= ap_const_logic_1;
else
ap_idle <= ap_const_logic_0;
end if;
end process;
-- ap_ready assign process. --
ap_ready_assign_proc : process(ap_start, ap_CS_fsm, ap_reg_ppiten_pp0_it0, ap_reg_ppiten_pp0_it2, indices_rsp_empty_n, ap_ce)
begin
if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it2) and (indices_rsp_empty_n = ap_const_logic_0)))) and (ap_const_logic_1 = ap_ce))) then
ap_ready <= ap_const_logic_1;
else
ap_ready <= ap_const_logic_0;
end if;
end process;
ap_reg_ppiten_pp0_it0 <= ap_start;
ap_return_0 <= agg_result_index_write_assign_fu_128_p3;
ap_return_1 <= agg_result_sample_write_assign_fu_120_p3;
-- ap_sig_pprstidle_pp0 assign process. --
ap_sig_pprstidle_pp0_assign_proc : process(ap_start, ap_reg_ppiten_pp0_it0, ap_reg_ppiten_pp0_it1, ap_reg_ppiten_pp0_it2)
begin
if (((ap_const_logic_0 = ap_reg_ppiten_pp0_it0) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it1) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it2) and (ap_const_logic_0 = ap_start))) then
ap_sig_pprstidle_pp0 <= ap_const_logic_1;
else
ap_sig_pprstidle_pp0 <= ap_const_logic_0;
end if;
end process;
indices_address <= tmp_s_fu_67_p1(32 - 1 downto 0);
indices_dataout <= ap_const_lv56_0;
indices_req_din <= ap_const_logic_0;
-- indices_req_write assign process. --
indices_req_write_assign_proc : process(ap_start, ap_CS_fsm, ap_reg_ppiten_pp0_it0, ap_reg_ppiten_pp0_it2, indices_rsp_empty_n, ap_ce)
begin
if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it2) and (indices_rsp_empty_n = ap_const_logic_0)))) and (ap_const_logic_1 = ap_ce))) then
indices_req_write <= ap_const_logic_1;
else
indices_req_write <= ap_const_logic_0;
end if;
end process;
-- indices_rsp_read assign process. --
indices_rsp_read_assign_proc : process(ap_start, ap_CS_fsm, ap_reg_ppiten_pp0_it0, ap_reg_ppiten_pp0_it2, indices_rsp_empty_n, ap_ce)
begin
if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it2) and (indices_rsp_empty_n = ap_const_logic_0)))) and (ap_const_logic_1 = ap_ce))) then
indices_rsp_read <= ap_const_logic_1;
else
indices_rsp_read <= ap_const_logic_0;
end if;
end process;
indices_size <= ap_const_lv32_1;
tmp_1_fu_115_p2 <= std_logic_vector(unsigned(ap_reg_ppstg_i_sample_read_reg_147_pp0_it2) + unsigned(ap_const_lv16_1));
tmp_6_cast_fu_91_p1 <= std_logic_vector(resize(unsigned(indices_samples_load_new5_reg_165),17));
tmp_7_fu_94_p2 <= std_logic_vector(unsigned(tmp_6_cast_fu_91_p1) + unsigned(ap_const_lv17_1FFFF));
tmp_7_fu_94_p2_temp <= signed(tmp_7_fu_94_p2);
tmp_8_fu_104_p1 <= std_logic_vector(resize(tmp_7_fu_94_p2_temp,18));
tmp_8_fu_104_p2 <= "1" when (signed(tmp_cast_fu_88_p1) < signed(tmp_8_fu_104_p1)) else "0";
tmp_9_fu_110_p2 <= std_logic_vector(unsigned(ap_reg_ppstg_i_index_read_reg_153_pp0_it2) + unsigned(ap_const_lv16_1));
tmp_cast_fu_88_p1 <= std_logic_vector(resize(unsigned(ap_reg_ppstg_i_sample_read_reg_147_pp0_it2),18));
tmp_s_fu_67_p1 <= std_logic_vector(resize(unsigned(i_index),64));
end behav;
| lgpl-3.0 | 80f61ac85600ba225b914f59b65467b6 | 0.606061 | 2.734984 | false | false | false | false |
astoria-d/super-duper-nes | duper_cartridge/i2c.vhd | 1 | 12,955 | library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.conv_integer;
use ieee.std_logic_arith.conv_std_logic_vector;
use ieee.std_logic_unsigned.all;
---po_i2c_status(3): '1' = bus transfering, '0' = stopped.
---po_i2c_status(2): '1' = read, '0' = write.
---po_i2c_status(1): '1' = data acknowleged, '0' = not acknowleged.
---po_i2c_status(0): '1' = addr acknowleged, '0' = not acknowleged.
entity i2c_slave is
port (
pi_rst_n : in std_logic;
pi_base_clk : in std_logic;
---i2c bus lines...
pi_slave_addr : in std_logic_vector (6 downto 0);
pi_i2c_scl : in std_logic;
pi_i2c_sda : in std_logic;
po_i2c_sda : out std_logic;
---i2c bus contoler internal lines...
pi_i2c_read_data : in std_logic_vector (7 downto 0);
po_i2c_write_data : out std_logic_vector (7 downto 0);
po_i2c_status : out std_logic_vector (3 downto 0)
);
end i2c_slave;
architecture rtl of i2c_slave is
type i2c_sp_stat is (
stop, start, restart
);
type i2c_bus_stat is (
idle,
a6, a5, a4, a3, a2, a1, a0, rw, a_ack,
d7, d6, d5, d4, d3, d2, d1, d0, d_ack
);
component edge_detecter port (
pi_rst_n : in std_logic;
pi_base_clk : in std_logic;
pi_input : in std_logic;
po_rise : out std_logic;
po_fall : out std_logic
);
end component;
signal reg_cur_sp : i2c_sp_stat;
signal reg_scl_rise : std_logic;
signal reg_scl_fall : std_logic;
signal reg_sda_rise : std_logic;
signal reg_sda_fall : std_logic;
signal reg_cur_state : i2c_bus_stat;
signal reg_next_state : i2c_bus_stat;
signal reg_i2c_cmd_addr : std_logic_vector(6 downto 0);
signal reg_i2c_cmd_r_nw : std_logic;
signal reg_i2c_cmd_in_data : std_logic_vector(6 downto 0);
begin
--edge detecter...
scl_detect_p : edge_detecter port map (pi_rst_n, pi_base_clk, pi_i2c_scl, reg_scl_rise, reg_scl_fall);
sda_detect_p : edge_detecter port map (pi_rst_n, pi_base_clk, pi_i2c_sda, reg_sda_rise, reg_sda_fall);
--start/stop w/ edge detect.
start_stop_p : process (pi_rst_n, pi_base_clk)
begin
if (pi_rst_n = '0') then
reg_cur_sp <= stop;
elsif (rising_edge(pi_base_clk)) then
if (pi_i2c_scl = '1' and reg_scl_rise = '0' and reg_scl_fall = '0' and reg_sda_fall = '1'
and reg_cur_sp = stop) then
reg_cur_sp <= start;
elsif (pi_i2c_scl = '1' and reg_scl_rise = '0' and reg_scl_fall = '0' and reg_sda_fall = '1'
and reg_cur_sp = start) then
reg_cur_sp <= restart;
elsif (pi_i2c_scl = '1' and reg_scl_rise = '0' and reg_scl_fall = '0' and reg_sda_rise = '1'
and reg_cur_sp = start) then
reg_cur_sp <= stop;
elsif (reg_cur_sp = restart) then
reg_cur_sp <= start;
end if;
end if;--if (pi_rst_n = '0') then
end process;
--i2c bus state machine (state transition)...
set_stat_p : process (pi_rst_n, reg_cur_sp, pi_base_clk)
begin
if (pi_rst_n = '0') then
reg_cur_state <= idle;
elsif (reg_cur_sp = stop or reg_cur_sp = restart) then
reg_cur_state <= idle;
elsif (rising_edge(pi_base_clk)) then
if (reg_scl_rise = '1') then
reg_cur_state <= reg_next_state;
end if;
end if;--if (pi_rst_n = '0') then
end process;
--state change to next.
next_stat_p : process (reg_cur_state, reg_i2c_cmd_r_nw, pi_i2c_sda)
procedure set_next_stat
(
pi_stat : in i2c_bus_stat
) is
begin
reg_next_state <= pi_stat;
end;
begin
case reg_cur_state is
when idle =>
set_next_stat(a6);
when a6 =>
set_next_stat(a5);
when a5 =>
set_next_stat(a4);
when a4 =>
set_next_stat(a3);
when a3 =>
set_next_stat(a2);
when a2 =>
set_next_stat(a1);
when a1 =>
set_next_stat(a0);
when a0 =>
set_next_stat(rw);
when rw =>
set_next_stat(a_ack);
when a_ack =>
set_next_stat(d7);
when d7 =>
set_next_stat(d6);
when d6 =>
set_next_stat(d5);
when d5 =>
set_next_stat(d4);
when d4 =>
set_next_stat(d3);
when d3 =>
set_next_stat(d2);
when d2 =>
set_next_stat(d1);
when d1 =>
set_next_stat(d0);
when d0 =>
if (reg_i2c_cmd_r_nw = '0') then
set_next_stat(d_ack);
else
--wait for ack.
if (pi_i2c_sda = '0') then
set_next_stat(d_ack);
else
set_next_stat(d0);
end if;
end if;
when d_ack =>
set_next_stat(d7);
end case;
end process;
--i2c addr/data set.
set_addr : process (pi_rst_n, pi_base_clk)
begin
if (pi_rst_n = '0') then
reg_i2c_cmd_addr <= (others => '0');
reg_i2c_cmd_r_nw <= '1';
reg_i2c_cmd_in_data <= (others => '0');
po_i2c_write_data <= (others => '0');
elsif (rising_edge(pi_base_clk)) then
if (reg_scl_rise = '1') then
--address sequence.
if (reg_cur_sp = start and reg_cur_state = idle) then
reg_i2c_cmd_addr (6) <= pi_i2c_sda;
elsif (reg_cur_state = a6) then
reg_i2c_cmd_addr (5) <= pi_i2c_sda;
elsif (reg_cur_state = a5) then
reg_i2c_cmd_addr (4) <= pi_i2c_sda;
elsif (reg_cur_state = a4) then
reg_i2c_cmd_addr (3) <= pi_i2c_sda;
elsif (reg_cur_state = a3) then
reg_i2c_cmd_addr (2) <= pi_i2c_sda;
elsif (reg_cur_state = a2) then
reg_i2c_cmd_addr (1) <= pi_i2c_sda;
elsif (reg_cur_state = a1) then
reg_i2c_cmd_addr (0) <= pi_i2c_sda;
elsif (reg_cur_state = a0) then
reg_i2c_cmd_r_nw <= pi_i2c_sda;
--data write sequence (input).
elsif (reg_cur_state = a_ack and reg_i2c_cmd_r_nw = '0') then
reg_i2c_cmd_in_data (6) <= pi_i2c_sda;
elsif (reg_cur_state = d7 and reg_i2c_cmd_r_nw = '0') then
reg_i2c_cmd_in_data (5) <= pi_i2c_sda;
elsif (reg_cur_state = d6 and reg_i2c_cmd_r_nw = '0') then
reg_i2c_cmd_in_data (4) <= pi_i2c_sda;
elsif (reg_cur_state = d5 and reg_i2c_cmd_r_nw = '0') then
reg_i2c_cmd_in_data (3) <= pi_i2c_sda;
elsif (reg_cur_state = d4 and reg_i2c_cmd_r_nw = '0') then
reg_i2c_cmd_in_data (2) <= pi_i2c_sda;
elsif (reg_cur_state = d3 and reg_i2c_cmd_r_nw = '0') then
reg_i2c_cmd_in_data (1) <= pi_i2c_sda;
elsif (reg_cur_state = d2 and reg_i2c_cmd_r_nw = '0') then
reg_i2c_cmd_in_data (0) <= pi_i2c_sda;
elsif (reg_cur_state = d1 and reg_i2c_cmd_r_nw = '0') then
po_i2c_write_data <= reg_i2c_cmd_in_data & pi_i2c_sda;
end if;
end if;--if (reg_scl_rise = '1') then
end if;--if (pi_rst_n = '0') then
end process;
--output status.
out_stat : process (pi_rst_n, pi_base_clk)
begin
if (pi_rst_n = '0') then
po_i2c_status <= (others => '0');
elsif (rising_edge(pi_base_clk)) then
if (reg_scl_rise = '1') then
if (reg_i2c_cmd_addr = pi_slave_addr) then
if (reg_cur_state = d7 or
reg_cur_state = d6 or
reg_cur_state = d5 or
reg_cur_state = d4 or
reg_cur_state = d3 or
reg_cur_state = d2 or
reg_cur_state = d1 or
reg_cur_state = d0) then
po_i2c_status(3) <= '1';
else
po_i2c_status(3) <= '0';
end if;
po_i2c_status(2) <= reg_i2c_cmd_r_nw;
if (reg_cur_state = d_ack and reg_i2c_cmd_r_nw = '0') then
--write
po_i2c_status(1) <= '1';
elsif (reg_cur_state = d0 and reg_i2c_cmd_r_nw = '1') then
--read
po_i2c_status(1) <= not pi_i2c_sda;
else
po_i2c_status(1) <= '0';
end if;
if (reg_cur_state = a_ack) then
po_i2c_status(0) <= '1';
else
po_i2c_status(0) <= '0';
end if;
else
po_i2c_status <= (others => '0');
end if;--if (reg_i2c_cmd_addr = pi_slave_addr) then
end if;--if (reg_scl_rise = '1') then
end if;--if (pi_rst_n = '0') then
end process;
--output (ack and read response: output) i2c bus.
out_data : process (pi_rst_n, pi_base_clk)
begin
if (pi_rst_n = '0') then
po_i2c_sda <= 'Z';
elsif (rising_edge(pi_base_clk)) then
if (reg_scl_fall = '1') then
if (reg_i2c_cmd_addr = pi_slave_addr) then
if (reg_cur_state = idle) then
--stand by.
po_i2c_sda <= 'Z';
elsif (reg_cur_state = rw) then
--addr ack reply.
po_i2c_sda <= '0';
elsif (reg_cur_state = a_ack) then
--data input.
if (reg_i2c_cmd_r_nw = '0') then
po_i2c_sda <= 'Z';
--data output.
else
po_i2c_sda <= pi_i2c_read_data(7);
end if;
--data output.
elsif (reg_cur_state = d7 and reg_i2c_cmd_r_nw = '1') then
po_i2c_sda <= pi_i2c_read_data(6);
elsif (reg_cur_state = d6 and reg_i2c_cmd_r_nw = '1') then
po_i2c_sda <= pi_i2c_read_data(5);
elsif (reg_cur_state = d5 and reg_i2c_cmd_r_nw = '1') then
po_i2c_sda <= pi_i2c_read_data(4);
elsif (reg_cur_state = d4 and reg_i2c_cmd_r_nw = '1') then
po_i2c_sda <= pi_i2c_read_data(3);
elsif (reg_cur_state = d3 and reg_i2c_cmd_r_nw = '1') then
po_i2c_sda <= pi_i2c_read_data(2);
elsif (reg_cur_state = d2 and reg_i2c_cmd_r_nw = '1') then
po_i2c_sda <= pi_i2c_read_data(1);
elsif (reg_cur_state = d1 and reg_i2c_cmd_r_nw = '1') then
po_i2c_sda <= pi_i2c_read_data(0);
elsif (reg_cur_state = d0) then
--data ack reply.
if (reg_i2c_cmd_r_nw = '0') then
po_i2c_sda <= '0';
else
--yield bus for incoming data.
po_i2c_sda <= 'Z';
end if;
elsif (reg_cur_state = d_ack) then
--data receive.
if (reg_i2c_cmd_r_nw = '0') then
po_i2c_sda <= 'Z';
else
--data out.
po_i2c_sda <= pi_i2c_read_data(7);
end if;
end if;
else
po_i2c_sda <= 'Z';
end if;--reg_i2c_cmd_addr = pi_slave_addr
end if;--if (reg_scl_fall = '1') then
end if;--if (pi_rst_n = '0') then
end process;
end rtl;
| apache-2.0 | a0f1ee7544ff13fd4b3733cd68bfa9a6 | 0.422617 | 3.235514 | false | false | false | false |
MartinCura/SistDig-TP4 | src/ext_ram/extRam_loader.vhd | 1 | 1,293 | library ieee;
use ieee.std_logic_1164.all;
entity extRam_loader is
port(
clock : in std_logic;
reset : in std_logic;
data_in : in std_logic_vector(7 downto 0);
RxRdy_in : in std_logic;
data_out : out std_logic_vector(15 downto 0);
RxRdy_out : out std_logic
);
end;
architecture extRam_loader_arq of extRam_loader is
type t_estado is (LSB, MSB);
signal estado : t_estado := LSB;
begin
process(clock, reset)
begin
-- reset
if reset = '1' then
data_out <= (others => '0');
estado <= LSB;
RxRdy_out <= '0';
elsif rising_edge(clock) then
RxRdy_out <= '0';
case estado is
when LSB =>
if RxRdy_in = '1' then -- Modo lectura del LSB
data_out(7 downto 0) <= data_in;
RxRdy_out <= '0';
estado <= MSB;
end if;
when MSB =>
if RxRdy_in = '1' then
data_out(15 downto 8) <= data_in;
RxRdy_out <= '1';
estado <= LSB;
end if;
end case;
end if;
end process;
end;
| gpl-3.0 | 0f75eac092dbe5a2f88c1ad365bab60f | 0.438515 | 3.978462 | false | false | false | false |
natsutan/NPU | fpga_implement/npu8/npu8.srcs/sources_1/ip/mul8_8/synth/mul8_8.vhd | 1 | 5,640 | -- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:mult_gen:12.0
-- IP Revision: 12
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY mult_gen_v12_0_12;
USE mult_gen_v12_0_12.mult_gen_v12_0_12;
ENTITY mul8_8 IS
PORT (
CLK : IN STD_LOGIC;
A : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
B : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
P : OUT STD_LOGIC_VECTOR(15 DOWNTO 0)
);
END mul8_8;
ARCHITECTURE mul8_8_arch OF mul8_8 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF mul8_8_arch: ARCHITECTURE IS "yes";
COMPONENT mult_gen_v12_0_12 IS
GENERIC (
C_VERBOSITY : INTEGER;
C_MODEL_TYPE : INTEGER;
C_OPTIMIZE_GOAL : INTEGER;
C_XDEVICEFAMILY : STRING;
C_HAS_CE : INTEGER;
C_HAS_SCLR : INTEGER;
C_LATENCY : INTEGER;
C_A_WIDTH : INTEGER;
C_A_TYPE : INTEGER;
C_B_WIDTH : INTEGER;
C_B_TYPE : INTEGER;
C_OUT_HIGH : INTEGER;
C_OUT_LOW : INTEGER;
C_MULT_TYPE : INTEGER;
C_CE_OVERRIDES_SCLR : INTEGER;
C_CCM_IMP : INTEGER;
C_B_VALUE : STRING;
C_HAS_ZERO_DETECT : INTEGER;
C_ROUND_OUTPUT : INTEGER;
C_ROUND_PT : INTEGER
);
PORT (
CLK : IN STD_LOGIC;
A : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
B : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
CE : IN STD_LOGIC;
SCLR : IN STD_LOGIC;
P : OUT STD_LOGIC_VECTOR(15 DOWNTO 0)
);
END COMPONENT mult_gen_v12_0_12;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF mul8_8_arch: ARCHITECTURE IS "mult_gen_v12_0_12,Vivado 2016.4";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF mul8_8_arch : ARCHITECTURE IS "mul8_8,mult_gen_v12_0_12,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF mul8_8_arch: ARCHITECTURE IS "mul8_8,mult_gen_v12_0_12,{x_ipProduct=Vivado 2016.4,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=mult_gen,x_ipVersion=12.0,x_ipCoreRevision=12,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_VERBOSITY=0,C_MODEL_TYPE=0,C_OPTIMIZE_GOAL=1,C_XDEVICEFAMILY=kintexu,C_HAS_CE=0,C_HAS_SCLR=0,C_LATENCY=3,C_A_WIDTH=8,C_A_TYPE=1,C_B_WIDTH=8,C_B_TYPE=1,C_OUT_HIGH=15,C_OUT_LOW=0,C_MULT_TYPE=0,C_CE_OVERRIDES_SCLR=0,C_CCM_IMP=0,C_B_VALUE=10000001,C_HAS_ZERO_DETECT=0,C_ROUND_OUTPUT=0,C_ROUND_PT=0}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF CLK: SIGNAL IS "xilinx.com:signal:clock:1.0 clk_intf CLK";
ATTRIBUTE X_INTERFACE_INFO OF A: SIGNAL IS "xilinx.com:signal:data:1.0 a_intf DATA";
ATTRIBUTE X_INTERFACE_INFO OF B: SIGNAL IS "xilinx.com:signal:data:1.0 b_intf DATA";
ATTRIBUTE X_INTERFACE_INFO OF P: SIGNAL IS "xilinx.com:signal:data:1.0 p_intf DATA";
BEGIN
U0 : mult_gen_v12_0_12
GENERIC MAP (
C_VERBOSITY => 0,
C_MODEL_TYPE => 0,
C_OPTIMIZE_GOAL => 1,
C_XDEVICEFAMILY => "kintexu",
C_HAS_CE => 0,
C_HAS_SCLR => 0,
C_LATENCY => 3,
C_A_WIDTH => 8,
C_A_TYPE => 1,
C_B_WIDTH => 8,
C_B_TYPE => 1,
C_OUT_HIGH => 15,
C_OUT_LOW => 0,
C_MULT_TYPE => 0,
C_CE_OVERRIDES_SCLR => 0,
C_CCM_IMP => 0,
C_B_VALUE => "10000001",
C_HAS_ZERO_DETECT => 0,
C_ROUND_OUTPUT => 0,
C_ROUND_PT => 0
)
PORT MAP (
CLK => CLK,
A => A,
B => B,
CE => '1',
SCLR => '0',
P => P
);
END mul8_8_arch;
| bsd-3-clause | 5c97478f98c3a9d1201f3de000c4bd19 | 0.677482 | 3.339254 | false | false | false | false |
natsutan/NPU | fpga_implement/npu8/npu8.srcs/sources_1/ip/mul8_16/sim/mul8_16.vhd | 1 | 4,793 | -- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:mult_gen:12.0
-- IP Revision: 12
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY mult_gen_v12_0_12;
USE mult_gen_v12_0_12.mult_gen_v12_0_12;
ENTITY mul8_16 IS
PORT (
CLK : IN STD_LOGIC;
A : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
B : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
P : OUT STD_LOGIC_VECTOR(15 DOWNTO 0)
);
END mul8_16;
ARCHITECTURE mul8_16_arch OF mul8_16 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF mul8_16_arch: ARCHITECTURE IS "yes";
COMPONENT mult_gen_v12_0_12 IS
GENERIC (
C_VERBOSITY : INTEGER;
C_MODEL_TYPE : INTEGER;
C_OPTIMIZE_GOAL : INTEGER;
C_XDEVICEFAMILY : STRING;
C_HAS_CE : INTEGER;
C_HAS_SCLR : INTEGER;
C_LATENCY : INTEGER;
C_A_WIDTH : INTEGER;
C_A_TYPE : INTEGER;
C_B_WIDTH : INTEGER;
C_B_TYPE : INTEGER;
C_OUT_HIGH : INTEGER;
C_OUT_LOW : INTEGER;
C_MULT_TYPE : INTEGER;
C_CE_OVERRIDES_SCLR : INTEGER;
C_CCM_IMP : INTEGER;
C_B_VALUE : STRING;
C_HAS_ZERO_DETECT : INTEGER;
C_ROUND_OUTPUT : INTEGER;
C_ROUND_PT : INTEGER
);
PORT (
CLK : IN STD_LOGIC;
A : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
B : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
CE : IN STD_LOGIC;
SCLR : IN STD_LOGIC;
P : OUT STD_LOGIC_VECTOR(15 DOWNTO 0)
);
END COMPONENT mult_gen_v12_0_12;
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF CLK: SIGNAL IS "xilinx.com:signal:clock:1.0 clk_intf CLK";
ATTRIBUTE X_INTERFACE_INFO OF A: SIGNAL IS "xilinx.com:signal:data:1.0 a_intf DATA";
ATTRIBUTE X_INTERFACE_INFO OF B: SIGNAL IS "xilinx.com:signal:data:1.0 b_intf DATA";
ATTRIBUTE X_INTERFACE_INFO OF P: SIGNAL IS "xilinx.com:signal:data:1.0 p_intf DATA";
BEGIN
U0 : mult_gen_v12_0_12
GENERIC MAP (
C_VERBOSITY => 0,
C_MODEL_TYPE => 0,
C_OPTIMIZE_GOAL => 1,
C_XDEVICEFAMILY => "kintexu",
C_HAS_CE => 0,
C_HAS_SCLR => 0,
C_LATENCY => 3,
C_A_WIDTH => 8,
C_A_TYPE => 1,
C_B_WIDTH => 16,
C_B_TYPE => 1,
C_OUT_HIGH => 23,
C_OUT_LOW => 8,
C_MULT_TYPE => 0,
C_CE_OVERRIDES_SCLR => 0,
C_CCM_IMP => 0,
C_B_VALUE => "10000001",
C_HAS_ZERO_DETECT => 0,
C_ROUND_OUTPUT => 0,
C_ROUND_PT => 0
)
PORT MAP (
CLK => CLK,
A => A,
B => B,
CE => '1',
SCLR => '0',
P => P
);
END mul8_16_arch;
| bsd-3-clause | 91468b17435ed508a6260d716adbd026 | 0.665137 | 3.571535 | false | false | false | false |
MartinCura/SistDig-TP4 | src/comps/registroNb.vhd | 1 | 577 | library IEEE;
use IEEE.std_logic_1164.all;
-- Registro de N bits (default = 4)
entity registroNb is
-- Cantidad de bits
generic (N: NATURAL := 4);
port (
clk: in std_logic;
rst: in std_logic;
ena: in std_logic;
d: in std_logic_vector(N-1 downto 0);
q: out std_logic_vector(N-1 downto 0)
);
end;
architecture registroNb_arq of registroNb is
begin
FFD_i: for i in 0 to N-1 generate
FFD_inst: entity work.ffd
port map(
clk => clk,
rst => rst,
ena => ena,
d => d(i),
q => q(i)
);
end generate;
end;
| gpl-3.0 | 072b4c183697afa37a6391f5258fe46c | 0.580589 | 2.658986 | false | false | false | false |
Feuerwerk/fpgaNES | apu.vhd | 1 | 60,173 | /*
This file is part of fpgaNES.
fpgaNES is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.
fpgaNES is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with fpgaNES. If not, see <http://www.gnu.org/licenses/>.
*/
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
entity envelope is
port
(
i_clk : in std_logic;
i_clk_enable : in std_logic := '1';
i_reset_n : in std_logic := '1';
i_reload : in boolean := false;
i_loop : in std_logic := '0';
i_disable : in std_logic := '1';
i_volume : in std_logic_vector(3 downto 0) := "0000";
o_q : out std_logic_vector(3 downto 0)
);
end envelope;
architecture behavioral of envelope is
signal s_counter : std_logic_vector(3 downto 0) := (others => '1');
signal s_divider : std_logic_vector(3 downto 0) := (others => '0');
begin
process (i_clk)
begin
if rising_edge(i_clk) then
if i_reset_n = '0' then
s_divider <= (others => '0');
s_counter <= (others => '1');
elsif i_clk_enable = '1' then
if i_reload then
s_divider <= i_volume;
s_counter <= (others => '1');
elsif s_divider /= "0000" then
s_divider <= s_divider - "0001";
else
s_divider <= i_volume;
if s_counter /= "0000" then
s_counter <= s_counter - "0001";
elsif i_loop = '1' then
s_counter <= (others => '1');
end if;
end if;
end if;
end if;
end process;
o_q <= i_volume when i_disable = '1' else s_counter;
end behavioral;
/********************************************************/
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
entity length_counter is
port
(
i_clk : in std_logic;
i_clk_enable : in std_logic := '1';
i_reset_n : in std_logic := '1';
i_lcounter_clk : in std_logic := '1';
i_channel_enable : in std_logic := '1';
i_channel_reload : in std_logic := '0';
i_enable : in std_logic := '1';
i_addr : in std_logic_vector(1 downto 0);
i_data : in std_logic_vector(7 downto 0);
i_write_enable : in std_logic := '0';
i_cs_n : in std_logic := '1';
o_active : out std_logic
);
end length_counter;
architecture behavioral of length_counter is
type length_counter_t is array (0 to 31) of std_logic_vector(7 downto 0);
constant LENGTH_COUNTER_TABLE : length_counter_t := ( x"0A", x"FE", x"14", x"02", x"28", x"04", x"50", x"06", x"A0", x"08", x"3C", x"0A", x"0E", x"0C", x"1A", x"0E",
x"0C", x"10", x"18", x"12", x"30", x"14", x"60", x"16", x"C0", x"18", x"48", x"1A", x"10", x"1C", x"20", x"1E" );
signal s_length_active : boolean;
signal s_length_counter : std_logic_vector(7 downto 0) := x"00";
begin
process (i_clk)
variable length_index : integer range 0 to 31;
begin
if rising_edge(i_clk) then
if i_reset_n = '0' then
s_length_counter <= x"00";
elsif i_clk_enable = '1' then
if (i_cs_n = '0') and (i_write_enable = '1') and (i_addr = "11") and (i_channel_enable = '1') and ((i_lcounter_clk = '0') or (s_length_counter = x"00")) then
length_index := to_integer(unsigned(i_data(7 downto 3)));
s_length_counter <= LENGTH_COUNTER_TABLE(length_index);
elsif (i_channel_reload = '1') and (i_channel_enable = '0') then
s_length_counter <= x"00";
elsif (i_lcounter_clk = '1') and s_length_active and (i_enable = '1') then
s_length_counter <= s_length_counter - x"01";
end if;
end if;
end if;
end process;
s_length_active <= s_length_counter /= x"00";
o_active <= '1' when s_length_active else '0';
end behavioral;
/********************************************************/
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
entity square_channel is
generic
(
INCREMENT : std_logic := '0'
);
port
(
i_clk : in std_logic;
i_clk_enable : in std_logic;
i_reset_n : in std_logic := '1';
i_apu_clk : in std_logic;
i_envelope_clk : in std_logic := '1';
i_lcounter_clk : in std_logic := '1';
i_addr : in std_logic_vector(1 downto 0);
i_data : in std_logic_vector(7 downto 0);
i_write_enable : in std_logic := '0';
i_cs_n : in std_logic := '1';
i_enable : in std_logic := '0';
i_reload : in std_logic := '0';
o_active : out std_logic;
o_q : out std_logic_vector(3 downto 0)
);
end square_channel;
architecture behavioral of square_channel is
component envelope is
port
(
i_clk : in std_logic;
i_clk_enable : in std_logic := '1';
i_reset_n : in std_logic := '1';
i_reload : in boolean := false;
i_loop : in std_logic := '0';
i_disable : in std_logic := '1';
i_volume : in std_logic_vector(3 downto 0) := "0000";
o_q : out std_logic_vector(3 downto 0)
);
end component;
component length_counter is
port
(
i_clk : in std_logic;
i_clk_enable : in std_logic := '1';
i_reset_n : in std_logic := '1';
i_lcounter_clk : in std_logic := '1';
i_channel_enable : in std_logic := '1';
i_channel_reload : in std_logic := '0';
i_enable : in std_logic := '1';
i_addr : in std_logic_vector(1 downto 0);
i_data : in std_logic_vector(7 downto 0);
i_write_enable : in std_logic := '0';
i_cs_n : in std_logic := '1';
o_active : out std_logic
);
end component;
type duty_table_t is array (0 to 31) of std_logic;
constant DUTY_TABLE : duty_table_t := ( '0', '0', '0', '0', '0', '0', '0', '1',
'0', '0', '0', '0', '0', '0', '1', '1',
'0', '0', '0', '0', '1', '1', '1', '1',
'1', '1', '1', '1', '1', '1', '0', '0' );
signal s_duty : std_logic_vector(1 downto 0) := "00";
signal s_envelope_reload : boolean := false;
signal s_envelope_loop : std_logic := '0';
signal s_envelope_disable : std_logic := '1';
signal s_envelope_volume : std_logic_vector(3 downto 0) := "0000";
signal s_envelope_q : std_logic_vector(3 downto 0);
signal s_sweep_enable : std_logic := '0';
signal s_sweep_period : std_logic_vector(2 downto 0) := "000";
signal s_sweep_negate : std_logic := '0';
signal s_sweep_shift : std_logic_vector(2 downto 0) := "000";
signal s_sweep_update : std_logic := '0';
signal s_length_active : std_logic;
signal s_sweep_counter : std_logic_vector(2 downto 0) := "000";
signal s_duty_counter : std_logic_vector(2 downto 0) := "000";
signal s_current_period : std_logic_vector(10 downto 0) := 11x"0000";
signal s_freq_counter : std_logic_vector(10 downto 0) := 11x"0000";
signal s_shift_res : std_logic_vector(10 downto 0);
signal s_target_period : std_logic_vector(11 downto 0);
signal s_target_in_range : boolean;
signal s_write_ch : boolean;
signal s_write_r0 : boolean;
signal s_write_r1 : boolean;
signal s_write_r2 : boolean;
signal s_write_r3 : boolean;
signal s_duty_index : integer range 0 to 31;
signal s_sweep_reload : boolean := false;
signal s_timer_reload : boolean := false;
signal s_timer_done : boolean;
begin
ev : envelope port map
(
i_clk => i_clk,
i_clk_enable => i_envelope_clk,
i_reset_n => i_reset_n,
i_reload => s_envelope_reload,
i_loop => s_envelope_loop,
i_disable => s_envelope_disable,
i_volume => s_envelope_volume,
o_q => s_envelope_q
);
lc : length_counter port map
(
i_clk => i_clk,
i_clk_enable => i_clk_enable,
i_reset_n => i_reset_n,
i_lcounter_clk => i_lcounter_clk,
i_channel_enable => i_enable,
i_channel_reload => i_reload,
i_enable => not s_envelope_loop,
i_addr => i_addr,
i_data => i_data,
i_write_enable => i_write_enable,
i_cs_n => i_cs_n,
o_active => s_length_active
);
-- Register
process (i_clk)
begin
if rising_edge(i_clk) then
if i_reset_n = '0' then
s_duty <= "00";
s_envelope_loop <= '0';
s_envelope_disable <= '1';
s_envelope_volume <= "0000";
elsif i_clk_enable = '1' then
if s_write_r0 then
s_duty <= i_data(7 downto 6);
s_envelope_loop <= i_data(5);
s_envelope_disable <= i_data(4);
s_envelope_volume <= i_data(3 downto 0);
end if;
end if;
end if;
end process;
process (i_clk)
begin
if rising_edge(i_clk) then
if i_reset_n = '0' then
s_sweep_enable <= '0';
s_sweep_period <= "000";
s_sweep_negate <= '0';
s_sweep_shift <= "000";
elsif i_clk_enable = '1' then
if s_write_r1 then
s_sweep_enable <= i_data(7) and (i_data(2) or i_data(1) or i_data(0));
s_sweep_period <= i_data(6 downto 4);
s_sweep_negate <= i_data(3);
s_sweep_shift <= i_data(2 downto 0);
end if;
end if;
end if;
end process;
process (i_clk)
begin
if rising_edge(i_clk) then
if i_reset_n = '0' then
s_sweep_reload <= false;
elsif i_clk_enable = '1' then
if s_write_r1 then
s_sweep_reload <= true;
elsif i_lcounter_clk = '1' then
s_sweep_reload <= false;
end if;
end if;
end if;
end process;
process (i_clk)
begin
if rising_edge(i_clk) then
if i_reset_n = '0' then
s_timer_reload <= false;
elsif i_clk_enable = '1' then
if s_write_r3 then
s_timer_reload <= true;
elsif i_apu_clk = '1' then
s_timer_reload <= false;
end if;
end if;
end if;
end process;
process (i_clk)
begin
if rising_edge(i_clk) then
if i_reset_n = '0' then
s_envelope_reload <= false;
elsif i_clk_enable = '1' then
if s_write_r3 then
s_envelope_reload <= true;
elsif i_envelope_clk = '1' then
s_envelope_reload <= false;
end if;
end if;
end if;
end process;
-- Duty
process (i_clk)
begin
if rising_edge(i_clk) then
if i_reset_n = '0' then
s_duty_counter <= "000";
elsif i_apu_clk = '1' then
if s_timer_reload then
s_duty_counter <= "000";
elsif s_timer_done then
s_duty_counter <= s_duty_counter - "001";
end if;
end if;
end if;
end process;
-- Timer
process (i_clk)
begin
if rising_edge(i_clk) then
if i_reset_n = '0' then
s_freq_counter <= 11x"0000";
elsif i_apu_clk = '1' then
if s_timer_done or s_timer_reload then
s_freq_counter <= s_current_period;
else
s_freq_counter <= s_freq_counter - 11x"0001";
end if;
end if;
end if;
end process;
-- Sweep
process (i_clk)
begin
if rising_edge(i_clk) then
if i_reset_n = '0' then
s_current_period <= 11x"0000";
elsif i_clk_enable = '1' then
if s_write_r2 then
s_current_period(7 downto 0) <= i_data;
elsif s_write_r3 then
s_current_period(10 downto 8) <= i_data(2 downto 0);
elsif (i_lcounter_clk = '1') and (s_sweep_enable = '1') and (s_sweep_counter = "000") and s_target_in_range then
s_current_period <= s_target_period(10 downto 0);
end if;
end if;
end if;
end process;
process (i_clk)
begin
if rising_edge(i_clk) then
if i_reset_n = '0' then
s_sweep_counter <= "000";
elsif i_lcounter_clk = '1' then
if s_sweep_reload or (s_sweep_counter = "000") then
s_sweep_counter <= s_sweep_period;
else
s_sweep_counter <= s_sweep_counter - "001";
end if;
end if;
end if;
end process;
process (s_current_period, s_sweep_shift)
begin
case s_sweep_shift is
when "001" =>
s_shift_res <= '0' & s_current_period(10 downto 1);
when "010" =>
s_shift_res <= "00" & s_current_period(10 downto 2);
when "011" =>
s_shift_res <= "000" & s_current_period(10 downto 3);
when "100" =>
s_shift_res <= "0000" & s_current_period(10 downto 4);
when "101" =>
s_shift_res <= "00000" & s_current_period(10 downto 5);
when "110" =>
s_shift_res <= "000000" & s_current_period(10 downto 6);
when "111" =>
s_shift_res <= "0000000" & s_current_period(10 downto 7);
when others =>
s_shift_res <= s_current_period;
end case;
end process;
s_write_ch <= (i_cs_n = '0') and (i_write_enable = '1');
s_write_r0 <= s_write_ch and (i_addr = "00");
s_write_r1 <= s_write_ch and (i_addr = "01");
s_write_r2 <= s_write_ch and (i_addr = "10");
s_write_r3 <= s_write_ch and (i_addr = "11");
s_timer_done <= s_freq_counter = 11x"0000";
s_target_period <= ('0' & s_current_period) + ('0' & s_shift_res) when s_sweep_negate = '0'
else ('0' & s_current_period) + ('1' & not(s_shift_res)) + (10x"0000" & INCREMENT);
s_target_in_range <= (s_current_period(10 downto 3) /= "00000000") and ((s_target_period(11) = '0') or (s_sweep_negate = '1'));
s_duty_index <= to_integer(unsigned(s_duty & s_duty_counter));
o_q <= s_envelope_q when (DUTY_TABLE(s_duty_index) = '1') and s_target_in_range and (s_length_active = '1') and (i_enable = '1') else "0000";
o_active <= s_length_active;
end behavioral;
/********************************************************/
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
entity triangle_channel is
port
(
i_clk : in std_logic;
i_clk_enable : in std_logic;
i_reset_n : in std_logic := '1';
i_envelope_clk : in std_logic := '1';
i_lcounter_clk : in std_logic := '1';
i_addr : in std_logic_vector(1 downto 0);
i_data : in std_logic_vector(7 downto 0);
i_write_enable : in std_logic := '0';
i_cs_n : in std_logic := '1';
i_enable : in std_logic := '0';
i_reload : in std_logic := '0';
o_active : out std_logic;
o_q : out std_logic_vector(3 downto 0)
);
end triangle_channel;
architecture behavioral of triangle_channel is
component length_counter is
port
(
i_clk : in std_logic;
i_clk_enable : in std_logic := '1';
i_reset_n : in std_logic := '1';
i_lcounter_clk : in std_logic := '1';
i_channel_enable : in std_logic := '1';
i_channel_reload : in std_logic := '0';
i_enable : in std_logic := '1';
i_addr : in std_logic_vector(1 downto 0);
i_data : in std_logic_vector(7 downto 0);
i_write_enable : in std_logic := '0';
i_cs_n : in std_logic := '1';
o_active : out std_logic
);
end component;
signal s_linear_control : std_logic := '1';
signal s_linear_load : std_logic_vector(6 downto 0) := 7x"00";
signal s_linear_counter : std_logic_vector(6 downto 0) := 7x"00";
signal s_linear_reload : boolean := false;
signal s_linear_active : boolean;
signal s_length_active : std_logic;
signal s_timer_value : std_logic_vector(10 downto 0) := 11x"0000";
signal s_timer_counter : std_logic_vector(10 downto 0) := 11x"0000";
signal s_length_counter : std_logic_vector(7 downto 0) := x"00";
signal s_sequencer : std_logic_vector(4 downto 0) := "00000";
signal s_sequencer_res : std_logic_vector(4 downto 0);
signal s_timer_enable : boolean;
signal s_timer_done : boolean;
signal s_write_ch : boolean;
signal s_write_r0 : boolean;
signal s_write_r2 : boolean;
signal s_write_r3 : boolean;
begin
lc : length_counter port map
(
i_clk => i_clk,
i_clk_enable => i_clk_enable,
i_reset_n => i_reset_n,
i_lcounter_clk => i_lcounter_clk,
i_channel_enable => i_enable,
i_channel_reload => i_reload,
i_enable => not s_linear_control,
i_addr => i_addr,
i_data => i_data,
i_write_enable => i_write_enable,
i_cs_n => i_cs_n,
o_active => s_length_active
);
-- Register
process (i_clk)
begin
if rising_edge(i_clk) then
if i_reset_n = '0' then
s_linear_control <= '1';
s_linear_load <= 7x"00";
elsif i_clk_enable = '1' then
if s_write_r0 then
s_linear_control <= i_data(7);
s_linear_load <= i_data(6 downto 0);
end if;
end if;
end if;
end process;
process (i_clk)
begin
if rising_edge(i_clk) then
if i_reset_n = '0' then
s_timer_value <= 11x"0000";
elsif i_clk_enable = '1' then
if s_write_r2 then
s_timer_value(7 downto 0) <= i_data;
elsif s_write_r3 then
s_timer_value(10 downto 8) <= i_data(2 downto 0);
end if;
end if;
end if;
end process;
process (i_clk)
begin
if rising_edge(i_clk) then
if i_reset_n = '0' then
s_linear_reload <= false;
elsif i_clk_enable = '1' then
if s_write_r3 then
s_linear_reload <= true;
elsif (i_envelope_clk = '1') and (s_linear_control = '0') then
s_linear_reload <= false;
end if;
end if;
end if;
end process;
-- Linear Counter
process (i_clk)
begin
if rising_edge(i_clk) then
if i_reset_n = '0' then
s_linear_counter <= 7x"00";
elsif i_envelope_clk = '1' then
if s_linear_reload then
s_linear_counter <= s_linear_load;
elsif s_linear_active then
s_linear_counter <= s_linear_counter - 7x"01";
end if;
end if;
end if;
end process;
-- Timer
process (i_clk)
begin
if rising_edge(i_clk) then
if i_reset_n = '0' then
s_timer_counter <= 11x"0000";
elsif i_clk_enable = '1' then
if s_timer_enable then
if s_timer_done then
s_timer_counter <= s_timer_value;
else
s_timer_counter <= s_timer_counter - 11x"0001";
end if;
end if;
end if;
end if;
end process;
process (i_clk)
begin
if rising_edge(i_clk) then
if i_reset_n = '0' then
s_sequencer <= "00000";
elsif i_clk_enable = '1' then
if s_timer_done and s_timer_enable then
s_sequencer <= s_sequencer + "00001";
end if;
end if;
end if;
end process;
s_linear_active <= (s_linear_counter /= 7x"00");
s_timer_enable <= (s_length_active = '1') and s_linear_active;
s_timer_done <= s_timer_counter = 11x"0000";
s_sequencer_res <= s_sequencer xor 5x"1F";
s_write_ch <= (i_cs_n = '0') and (i_write_enable = '1');
s_write_r0 <= s_write_ch and (i_addr = "00");
s_write_r2 <= s_write_ch and (i_addr = "10");
s_write_r3 <= s_write_ch and (i_addr = "11");
o_active <= s_length_active;
o_q <= s_sequencer(3 downto 0) when s_sequencer(4) = '1' else s_sequencer_res(3 downto 0);
end behavioral;
/********************************************************/
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
use work.common.all;
entity noise_channel is
port
(
i_clk : in std_logic;
i_clk_enable : in std_logic;
i_reset_n : in std_logic := '1';
i_apu_clk : in std_logic := '1';
i_envelope_clk : in std_logic := '1';
i_lcounter_clk : in std_logic := '1';
i_addr : in std_logic_vector(1 downto 0);
i_data : in std_logic_vector(7 downto 0);
i_write_enable : in std_logic := '0';
i_cs_n : in std_logic := '1';
i_enable : in std_logic := '0';
i_reload : in std_logic := '0';
i_video_mode : in video_mode_t := ntsc;
o_active : out std_logic;
o_q : out std_logic_vector(3 downto 0)
);
end noise_channel;
architecture behavioral of noise_channel is
component envelope is
port
(
i_clk : in std_logic;
i_clk_enable : in std_logic := '1';
i_reset_n : in std_logic := '1';
i_reload : in boolean := false;
i_loop : in std_logic := '0';
i_disable : in std_logic := '1';
i_volume : in std_logic_vector(3 downto 0) := "0000";
o_q : out std_logic_vector(3 downto 0)
);
end component;
component length_counter is
port
(
i_clk : in std_logic;
i_clk_enable : in std_logic := '1';
i_reset_n : in std_logic := '1';
i_lcounter_clk : in std_logic := '1';
i_channel_enable : in std_logic := '1';
i_channel_reload : in std_logic := '0';
i_enable : in std_logic := '1';
i_addr : in std_logic_vector(1 downto 0);
i_data : in std_logic_vector(7 downto 0);
i_write_enable : in std_logic := '0';
i_cs_n : in std_logic := '1';
o_active : out std_logic
);
end component;
/*
NTSC 4, 8, 16, 32, 64, 96, 128, 160, 202, 254, 380, 508, 762, 1016, 2034, 4068
PAL 4, 8, 14, 30, 60, 88, 118, 148, 188, 236, 354, 472, 708, 944, 1890, 3778
*/
type period_table_t is array (0 to 15) of std_logic_vector(11 downto 0);
constant PERIOD_TABLE_NTSC : period_table_t := ( 12x"0004", 12x"0008", 12x"0010", 12x"0020", 12x"0040", 12x"0060", 12x"0080", 12x"00A0",
12x"00CA", 12x"00FE", 12x"017C", 12x"01FC", 12x"02FA", 12x"03F8", 12x"07F2", 12x"0FE4" );
constant PERIOD_TABLE_PAL : period_table_t := ( 12x"0004", 12x"0008", 12x"000E", 12x"001E", 12x"003C", 12x"0058", 12x"0076", 12x"0094",
12x"00BC", 12x"00EC", 12x"0162", 12x"01D8", 12x"02C4", 12x"03B0", 12x"0762", 12x"0EC2" );
signal s_envelope_reload : boolean := false;
signal s_envelope_loop : std_logic := '0';
signal s_envelope_disable : std_logic := '1';
signal s_envelope_volume : std_logic_vector(3 downto 0) := "0000";
signal s_envelope_q : std_logic_vector(3 downto 0);
signal s_length_active : std_logic;
signal s_shift_mode : std_logic := '0';
signal s_shift_bit : std_logic;
signal s_shift_new : std_logic;
signal s_noise_shift : std_logic_vector(14 downto 0) := 15x"01";
signal s_timer_value : std_logic_vector(11 downto 0) := 12x"0000";
signal s_timer_counter : std_logic_vector(11 downto 0) := 12x"0000";
signal s_timer_done : boolean;
signal s_write_ch : boolean;
signal s_write_r0 : boolean;
signal s_write_r2 : boolean;
signal s_write_r3 : boolean;
signal s_period_table : period_table_t;
begin
ev : envelope port map
(
i_clk => i_clk,
i_clk_enable => i_envelope_clk,
i_reset_n => i_reset_n,
i_reload => s_envelope_reload,
i_loop => s_envelope_loop,
i_disable => s_envelope_disable,
i_volume => s_envelope_volume,
o_q => s_envelope_q
);
lc : length_counter port map
(
i_clk => i_clk,
i_clk_enable => i_clk_enable,
i_reset_n => i_reset_n,
i_lcounter_clk => i_lcounter_clk,
i_channel_enable => i_enable,
i_channel_reload => i_reload,
i_enable => not s_envelope_loop,
i_addr => i_addr,
i_data => i_data,
i_write_enable => i_write_enable,
i_cs_n => i_cs_n,
o_active => s_length_active
);
-- Register
process (i_clk)
begin
if rising_edge(i_clk) then
if i_reset_n = '0' then
s_envelope_volume <= "0000";
s_envelope_disable <= '1';
s_envelope_loop <= '0';
elsif i_clk_enable = '1' then
if s_write_r0 then
s_envelope_volume <= i_data(3 downto 0);
s_envelope_disable <= i_data(4);
s_envelope_loop <= i_data(5);
end if;
end if;
end if;
end process;
process (i_clk)
variable period_index : integer range 0 to 15;
begin
if rising_edge(i_clk) then
if i_reset_n = '0' then
s_shift_mode <= '0';
s_timer_value <= 12x"00";
elsif i_clk_enable = '1' then
if s_write_r2 then
s_shift_mode <= i_data(7);
period_index := to_integer(unsigned(i_data(3 downto 0)));
s_timer_value <= s_period_table(period_index);
end if;
end if;
end if;
end process;
process (i_clk)
begin
if rising_edge(i_clk) then
if i_reset_n = '0' then
s_envelope_reload <= false;
elsif i_clk_enable = '1' then
if s_write_r3 then
s_envelope_reload <= true;
elsif i_envelope_clk = '1' then
s_envelope_reload <= false;
end if;
end if;
end if;
end process;
-- Timer
process (i_clk)
begin
if rising_edge(i_clk) then
if i_reset_n = '0' then
s_timer_counter <= 12x"0000";
elsif i_apu_clk = '1' then
if s_timer_done then
s_timer_counter <= s_timer_value;
else
s_timer_counter <= s_timer_counter - 12x"0001";
end if;
end if;
end if;
end process;
-- Shift
process (i_clk)
begin
if rising_edge(i_clk) then
if i_reset_n = '0' then
s_noise_shift <= 15x"01";
elsif (i_apu_clk = '1') and s_timer_done then
s_noise_shift <= s_shift_new & s_noise_shift(14 downto 1);
end if;
end if;
end process;
s_shift_bit <= s_noise_shift(6) when s_shift_mode = '1' else s_noise_shift(1);
s_shift_new <= s_shift_bit xor s_noise_shift(0);
s_timer_done <= s_timer_counter = 12x"0000";
s_write_ch <= (i_cs_n = '0') and (i_write_enable = '1');
s_write_r0 <= s_write_ch and (i_addr = "00");
s_write_r2 <= s_write_ch and (i_addr = "10");
s_write_r3 <= s_write_ch and (i_addr = "11");
s_period_table <= PERIOD_TABLE_PAL when i_video_mode = pal else PERIOD_TABLE_NTSC;
o_active <= s_length_active;
o_q <= s_envelope_q when (s_noise_shift(0) = '0') and (s_length_active = '1') else "0000";
end behavioral;
/********************************************************/
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
use work.common.all;
entity dmc_channel is
port
(
i_clk : in std_logic;
i_clk_enable : in std_logic;
i_reset_n : in std_logic := '1';
i_addr : in std_logic_vector(1 downto 0);
i_data : in std_logic_vector(7 downto 0);
i_dma_busy : in std_logic := '0';
i_dma_data : in std_logic_vector(7 downto 0) := x"00";
i_write_enable : in std_logic := '0';
i_cs_n : in std_logic := '1';
i_enable : in std_logic := '0';
i_reload : in std_logic := '0';
i_video_mode : in video_mode_t := ntsc;
o_dma_request : out std_logic;
o_dma_addr : out std_logic_vector(15 downto 0);
o_active : out std_logic;
o_int_pending : out std_logic;
o_q : out std_logic_vector(6 downto 0)
);
end dmc_channel;
architecture behavioral of dmc_channel is
type period_t is array (0 to 15) of std_logic_vector(8 downto 0);
constant PERIOD_TABLE_NTSC : period_t := ( 9x"1AB", 9x"17B", 9x"153", 9x"13F", 9x"11D", 9x"0FD", 9x"0E1", 9x"0D5",
9x"0BD", 9x"09F", 9x"08D", 9x"07F", 9x"069", 9x"053", 9x"047", 9x"035" );
constant PERIOD_TABLE_PAL : period_t := ( 9x"18E", 9x"162", 9x"13C", 9x"12A", 9x"114", 9x"0EC", 9x"0D2", 9x"0C6",
9x"0B0", 9x"094", 9x"084", 9x"076", 9x"062", 9x"04E", 9x"042", 9x"032" );
signal s_int_enable : std_logic := '0';
signal s_loop : std_logic := '0';
signal s_timer_counter : std_logic_vector(8 downto 0) := 9x"000";
signal s_timer_value : std_logic_vector(8 downto 0) := 9x"000";
signal s_length_load : unsigned(11 downto 0) := 12x"000";
signal s_addr_load : std_logic_vector(15 downto 0) := x"0000";
signal s_output : std_logic_vector(6 downto 0) := 7x"00";
signal s_next_output : std_logic_vector(7 downto 0);
signal s_write_ch : boolean;
signal s_write_r0 : boolean;
signal s_write_r1 : boolean;
signal s_write_r2 : boolean;
signal s_write_r3 : boolean;
signal s_timer_done : boolean;
signal s_silent : boolean := true;
signal s_bits_remaining : unsigned(2 downto 0) := "000";
signal s_shift_buffer : std_logic_vector(7 downto 0) := x"00";
signal s_sample_buffer_empty : boolean := true;
signal s_bits_empty : boolean;
signal s_dma_request : std_logic := '0';
signal s_dma_addr : std_logic_vector(15 downto 0) := x"0000";
signal s_next_addr : std_logic_vector(15 downto 0) := x"0000";
signal s_length : unsigned(11 downto 0) := 12x"000";
signal s_dma_busy_d : std_logic := '0';
signal s_int_pending : std_logic := '0';
signal s_int_trigger : boolean := false;
signal s_dma_free : boolean;
signal s_dma_done : boolean;
signal s_period_table : period_t;
begin
-- DMC
process (i_clk)
begin
if rising_edge(i_clk) then
if i_reset_n = '0' then
s_loop <= '0';
elsif i_clk_enable = '1' then
if s_write_r0 then
s_loop <= i_data(6);
end if;
end if;
end if;
end process;
process (i_clk)
variable period_index : integer range 0 to 15;
begin
if rising_edge(i_clk) then
if i_reset_n = '0' then
s_timer_value <= 9x"000";
elsif i_clk_enable = '1' then
if s_write_r0 then
period_index := to_integer(unsigned(i_data(3 downto 0)));
s_timer_value <= s_period_table(period_index);
end if;
end if;
end if;
end process;
-- Output
process (i_clk)
begin
if rising_edge(i_clk) then
if i_reset_n = '0' then
s_output <= 7x"00";
elsif i_clk_enable = '1' then
if s_write_r1 then
s_output <= i_data(6 downto 0);
elsif s_timer_done and not s_silent then
if s_next_output(7) = '0' then
s_output <= s_next_output(6 downto 0);
end if;
end if;
end if;
end if;
end process;
-- Addr
process (i_clk)
begin
if rising_edge(i_clk) then
if i_reset_n = '0' then
s_addr_load <= x"0000";
elsif i_clk_enable = '1' then
if s_write_r2 then
s_addr_load <= x"C000" or ("00" & i_data & "000000");
end if;
end if;
end if;
end process;
-- Length Counter
process (i_clk)
begin
if rising_edge(i_clk) then
if i_reset_n = '0' then
s_length_load <= 12x"000";
elsif i_clk_enable = '1' then
if s_write_r3 then
s_length_load <= unsigned(i_data) & "0001";
end if;
end if;
end if;
end process;
-- Timer
process (i_clk)
begin
if rising_edge(i_clk) then
if i_reset_n = '0' then
s_timer_counter <= 9x"000";
elsif i_clk_enable = '1' then
if s_timer_done then
s_timer_counter <= s_timer_value;
else
s_timer_counter <= s_timer_counter - 9x"001";
end if;
end if;
end if;
end process;
s_timer_done <= s_timer_counter = "000";
process (i_clk)
begin
if rising_edge(i_clk) then
if i_reset_n = '0' then
s_bits_remaining <= "000";
s_shift_buffer <= x"00";
s_silent <= true;
elsif (i_clk_enable = '1') and s_timer_done then
s_bits_remaining <= s_bits_remaining - "001";
s_shift_buffer <= '0' & s_shift_buffer(7 downto 1);
if s_bits_empty then
s_shift_buffer <= i_dma_data;
s_silent <= s_sample_buffer_empty;
end if;
end if;
end if;
end process;
s_bits_empty <= s_bits_remaining = "000";
-- DMA Response & Sample Buffer
process (i_clk)
begin
if rising_edge(i_clk) then
if i_reset_n = '0' then
s_sample_buffer_empty <= true;
s_dma_busy_d <= '0';
elsif i_clk_enable = '1' then
s_dma_busy_d <= i_dma_busy;
if s_dma_done then
s_sample_buffer_empty <= false;
elsif s_timer_done and s_bits_empty then
s_sample_buffer_empty <= true;
end if;
end if;
end if;
end process;
-- DMA Request
process (i_clk)
variable remaining_length : unsigned(11 downto 0);
variable sample_addr : std_logic_vector(15 downto 0);
begin
if rising_edge(i_clk) then
if i_reset_n = '0' then
s_dma_request <= '0';
s_int_trigger <= false;
elsif i_clk_enable = '1' then
s_dma_request <= '0';
remaining_length := s_length;
sample_addr := s_next_addr;
s_int_trigger <= false;
if i_reload = '1' then
if i_enable = '0' then
remaining_length := 12x"000";
elsif s_length = 12x"000" then
remaining_length := s_length_load;
sample_addr := s_addr_load;
end if;
end if;
if s_sample_buffer_empty and s_dma_free and not s_dma_done and (remaining_length /= 12x"000") then
s_dma_request <= '1';
s_dma_addr <= sample_addr;
if remaining_length = 12x"001" then
-- if last byte is requested
if s_loop = '1' then
-- restart playback
remaining_length := s_length_load;
sample_addr := s_addr_load;
else
-- stop playback
remaining_length := 12x"000";
s_int_trigger <= true;
end if;
else
-- determine address of next byte
sample_addr := (sample_addr + x"0001") or x"8000";
remaining_length := remaining_length - 12x"001";
end if;
end if;
s_next_addr <= sample_addr;
s_length <= remaining_length;
end if;
end if;
end process;
o_dma_request <= s_dma_request;
o_dma_addr <= s_dma_addr;
-- Interrupt
process (i_clk)
begin
if rising_edge(i_clk) then
if i_reset_n = '0' then
s_int_enable <= '0';
elsif (i_clk_enable = '1') and s_write_r0 then
s_int_enable <= i_data(7);
end if;
end if;
end process;
process (i_clk)
begin
if rising_edge(i_clk) then
if i_reset_n = '0' then
s_int_pending <= '0';
elsif i_clk_enable = '1' then
if s_write_r0 and (i_data(7) = '0') then
s_int_pending <= '0';
elsif s_int_trigger and (s_int_enable = '1') then
s_int_pending <= '1';
elsif i_reload = '1' then
s_int_pending <= '0';
end if;
end if;
end if;
end process;
o_int_pending <= s_int_pending;
-- Misc
s_write_ch <= (i_cs_n = '0') and (i_write_enable = '1');
s_write_r0 <= s_write_ch and (i_addr = "00");
s_write_r1 <= s_write_ch and (i_addr = "01");
s_write_r2 <= s_write_ch and (i_addr = "10");
s_write_r3 <= s_write_ch and (i_addr = "11");
s_next_output <= ('0' & s_output) + x"02" when s_shift_buffer(0) = '1' else ('0' & s_output - x"02");
s_dma_free <= (s_dma_request = '0') and (i_dma_busy = '0');
s_dma_done <= (s_dma_busy_d = '1') and (i_dma_busy = '0');
s_period_table <= PERIOD_TABLE_PAL when i_video_mode = pal else PERIOD_TABLE_NTSC;
o_active <= '0' when s_length = 12x"000" else '1';
o_q <= s_output;
end behavioral;
/********************************************************/
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
entity dma is
generic
(
TARGET_ADDR : std_logic_vector(15 downto 0) := x"2004"
);
port
(
i_clk : in std_logic;
i_reset_n : in std_logic := '1';
i_clk_enable : in std_logic := '1';
i_write_enable : in std_logic := '0';
i_seq_enable : in std_logic := '0';
i_seq_addr : in std_logic_vector(7 downto 0) := x"02";
i_single_enable : in std_logic := '0';
i_single_addr : in std_logic_vector(15 downto 0) := x"c045";
i_data : in std_logic_vector(7 downto 0) := x"00";
o_single_busy : out std_logic;
o_single_q : out std_logic_vector(7 downto 0);
o_addr : out std_logic_vector(15 downto 0);
o_data : out std_logic_vector(7 downto 0);
o_write_enable : out std_logic;
o_ready : out std_logic;
o_active : out std_logic
);
end dma;
architecture behavioral of dma is
type seq_mode_t is (idle, wait_read, align, transfer);
type sin_mode_t is (idle, wait_read, wait_byte, align, read_byte);
signal s_seq_mode : seq_mode_t := idle;
signal s_sin_mode : sin_mode_t := idle;
signal s_addr : std_logic_vector(7 downto 0) := x"00";
signal s_data : std_logic_vector(7 downto 0) := x"00";
signal s_write_enable : std_logic := '0';
signal s_single_q : std_logic_vector(7 downto 0) := x"00";
signal s_single_non_busy : boolean;
signal s_fetch_single : boolean := false;
begin
process (i_clk)
begin
if rising_edge(i_clk) then
if i_reset_n = '0' then
s_write_enable <= '0';
elsif i_clk_enable = '1' then
s_write_enable <= not s_write_enable;
end if;
end if;
end process;
-- Single DMA (DMC)
process (i_clk)
begin
if rising_edge(i_clk) then
if i_reset_n = '0' then
s_single_q <= x"00";
elsif (i_clk_enable = '1') and s_fetch_single then
s_single_q <= i_data;
end if;
end if;
end process;
process (i_clk)
begin
if rising_edge(i_clk) then
if i_reset_n = '0' then
s_sin_mode <= idle;
s_fetch_single <= false;
elsif i_clk_enable = '1' then
s_fetch_single <= false;
case s_sin_mode is
when idle =>
if i_single_enable = '1' then
s_sin_mode <= wait_read;
end if;
when wait_read =>
if i_write_enable = '0' then
s_sin_mode <= wait_byte;
end if;
when wait_byte =>
if s_write_enable = '0' then
s_sin_mode <= align;
else
s_sin_mode <= read_byte;
end if;
when align =>
s_sin_mode <= read_byte;
when read_byte =>
s_sin_mode <= idle;
s_fetch_single <= true;
end case;
end if;
end if;
end process;
-- Sequencial DMA (OAM)
process (i_clk)
begin
if rising_edge(i_clk) then
if i_reset_n = '0' then
s_seq_mode <= idle;
elsif i_clk_enable = '1' then
case s_seq_mode is
when idle =>
if i_seq_enable = '1' then
s_addr <= x"00";
s_seq_mode <= wait_read;
end if;
when wait_read =>
if i_write_enable = '0' then
if s_write_enable = '0' then
s_seq_mode <= align;
else
s_seq_mode <= transfer;
end if;
end if;
when align =>
s_seq_mode <= transfer;
when transfer =>
if s_write_enable = '1' then
if s_addr = x"ff" then
s_seq_mode <= idle;
elsif not s_fetch_single then
s_addr <= s_addr + x"01";
end if;
end if;
end case;
end if;
end if;
end process;
o_addr <= i_single_addr when s_sin_mode = read_byte
else i_seq_addr & s_addr when s_write_enable = '0'
else TARGET_ADDR;
o_ready <= '1' when (s_seq_mode = idle) and (s_sin_mode = idle) else i_write_enable;
o_active <= '0' when s_fetch_single
else '1' when (s_seq_mode = transfer) or (s_sin_mode = read_byte)
else '0';
o_data <= i_data;
o_write_enable <= s_write_enable;
o_single_busy <= '1' when s_fetch_single or (s_sin_mode /= idle) else '0';
o_single_q <= s_single_q;
end behavioral;
/********************************************************/
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
use work.common.all;
entity apu is
port
(
i_clk : in std_logic;
i_clk_enable : in std_logic;
i_reset_n : in std_logic := '1';
i_addr : in std_logic_vector(4 downto 0) := 5x"00";
i_data : in std_logic_vector(7 downto 0) := x"00";
i_write_enable : in std_logic := '0';
i_cs_n : in std_logic := '1';
i_dma_write_enable : in std_logic := '0';
i_dma_q : in std_logic_vector(7 downto 0) := x"00";
i_ctrl_a_data : in std_logic := '1';
i_ctrl_b_data : in std_logic := '1';
i_video_mode : in video_mode_t := ntsc;
o_ctrl_strobe : out std_logic;
o_ctrl_a_clk : out std_logic;
o_ctrl_b_clk : out std_logic;
o_int_n : out std_logic;
o_audio : out std_logic_vector(15 downto 0);
o_q : out std_logic_vector(7 downto 0);
o_dma_addr : out std_logic_vector(15 downto 0);
o_dma_data : out std_logic_vector(7 downto 0);
o_dma_write_enable : out std_logic;
o_dma_ready : out std_logic;
o_dma_active : out std_logic
);
end apu;
architecture behavioral of apu is
component square_channel is
generic
(
INCREMENT : std_logic := '0'
);
port
(
i_clk : in std_logic;
i_clk_enable : in std_logic;
i_reset_n : in std_logic := '1';
i_apu_clk : in std_logic;
i_envelope_clk : in std_logic := '1';
i_lcounter_clk : in std_logic := '1';
i_addr : in std_logic_vector(1 downto 0);
i_data : in std_logic_vector(7 downto 0);
i_write_enable : in std_logic := '0';
i_cs_n : in std_logic := '1';
i_enable : in std_logic := '0';
i_reload : in std_logic := '0';
o_active : out std_logic;
o_q : out std_logic_vector(3 downto 0)
);
end component;
component triangle_channel is
port
(
i_clk : in std_logic;
i_clk_enable : in std_logic;
i_reset_n : in std_logic := '1';
i_envelope_clk : in std_logic := '1';
i_lcounter_clk : in std_logic := '1';
i_addr : in std_logic_vector(1 downto 0);
i_data : in std_logic_vector(7 downto 0);
i_write_enable : in std_logic := '0';
i_cs_n : in std_logic := '1';
i_enable : in std_logic := '0';
i_reload : in std_logic := '0';
o_active : out std_logic;
o_q : out std_logic_vector(3 downto 0)
);
end component;
component noise_channel is
port
(
i_clk : in std_logic;
i_clk_enable : in std_logic;
i_reset_n : in std_logic := '1';
i_apu_clk : in std_logic := '1';
i_envelope_clk : in std_logic := '1';
i_lcounter_clk : in std_logic := '1';
i_addr : in std_logic_vector(1 downto 0);
i_data : in std_logic_vector(7 downto 0);
i_write_enable : in std_logic := '0';
i_cs_n : in std_logic := '1';
i_enable : in std_logic := '0';
i_reload : in std_logic := '0';
i_video_mode : in video_mode_t := ntsc;
o_active : out std_logic;
o_q : out std_logic_vector(3 downto 0)
);
end component;
component dmc_channel is
port
(
i_clk : in std_logic;
i_clk_enable : in std_logic;
i_reset_n : in std_logic := '1';
i_addr : in std_logic_vector(1 downto 0);
i_data : in std_logic_vector(7 downto 0);
i_dma_busy : in std_logic := '0';
i_dma_data : in std_logic_vector(7 downto 0) := x"00";
i_write_enable : in std_logic := '0';
i_cs_n : in std_logic := '1';
i_enable : in std_logic := '0';
i_reload : in std_logic := '0';
i_video_mode : in video_mode_t := ntsc;
o_dma_request : out std_logic;
o_dma_addr : out std_logic_vector(15 downto 0);
o_active : out std_logic;
o_int_pending : out std_logic;
o_q : out std_logic_vector(6 downto 0)
);
end component;
component dma is
generic
(
TARGET_ADDR : std_logic_vector(15 downto 0) := x"2004"
);
port
(
i_clk : in std_logic;
i_reset_n : in std_logic := '1';
i_clk_enable : in std_logic := '1';
i_write_enable : in std_logic := '0';
i_seq_enable : in std_logic := '0';
i_seq_addr : in std_logic_vector(7 downto 0) := x"02";
i_single_enable : in std_logic := '0';
i_single_addr : in std_logic_vector(15 downto 0) := x"c045";
i_data : in std_logic_vector(7 downto 0) := x"00";
o_single_busy : out std_logic;
o_single_q : out std_logic_vector(7 downto 0);
o_addr : out std_logic_vector(15 downto 0);
o_data : out std_logic_vector(7 downto 0);
o_write_enable : out std_logic;
o_ready : out std_logic;
o_active : out std_logic
);
end component;
type square_table_t is array (0 to 30) of std_logic_vector(15 downto 0);
type tnd_table_t is array (0 to 202) of std_logic_vector(15 downto 0);
-- this values were calculated by the equations in http://wiki.nesdev.com/w/index.php/APU_Mixer
/*
Base 0xFFFF
constant SQUARE_LOOKUP : square_table_t := ( x"0000", x"02f9", x"05df", x"08b4", x"0b78", x"0e2c", x"10cf", x"1364", x"15e9",
x"1860", x"1aca", x"1d26", x"1f75", x"21b8", x"23ee", x"2619", x"2838", x"2a4c",
x"2c56", x"2e55", x"304a", x"3235", x"3416", x"35ef", x"37be", x"3985", x"3b43",
x"3cf9", x"3ea7", x"404d", x"41ec" );
constant TND_LOOKUP : tnd_table_t := ( x"0000", x"01b7", x"036b", x"051b", x"06c7", x"0870", x"0a16", x"0bb8", x"0d57", x"0ef2",
x"108b", x"1220", x"13b2", x"1541", x"16cc", x"1855", x"19db", x"1b5d", x"1cdd", x"1e5a",
x"1fd4", x"214b", x"22bf", x"2430", x"259f", x"270b", x"2874", x"29db", x"2b3e", x"2ca0",
x"2dfe", x"2f5b", x"30b4", x"320b", x"3360", x"34b2", x"3602", x"374f", x"389a", x"39e3",
x"3b29", x"3c6d", x"3daf", x"3eee", x"402c", x"4167", x"42a0", x"43d6", x"450b", x"463d",
x"476e", x"489c", x"49c8", x"4af3", x"4c1b", x"4d41", x"4e66", x"4f88", x"50a8", x"51c7",
x"52e4", x"53fe", x"5517", x"562e", x"5744", x"5857", x"5969", x"5a79", x"5b87", x"5c93",
x"5d9e", x"5ea7", x"5fae", x"60b4", x"61b8", x"62ba", x"63bb", x"64ba", x"65b8", x"66b4",
x"67ae", x"68a7", x"699f", x"6a95", x"6b89", x"6c7c", x"6d6d", x"6e5d", x"6f4c", x"7039",
x"7124", x"720e", x"72f7", x"73df", x"74c5", x"75aa", x"768d", x"776f", x"7850", x"792f",
x"7a0d", x"7aea", x"7bc5", x"7ca0", x"7d79", x"7e50", x"7f27", x"7ffc", x"80d0", x"81a3",
x"8275", x"8345", x"8415", x"84e3", x"85b0", x"867c", x"8746", x"8810", x"88d8", x"89a0",
x"8a66", x"8b2b", x"8bef", x"8cb2", x"8d74", x"8e35", x"8ef5", x"8fb4", x"9072", x"912e",
x"91ea", x"92a5", x"935f", x"9418", x"94cf", x"9586", x"963c", x"96f1", x"97a5", x"9858",
x"990a", x"99bb", x"9a6b", x"9b1b", x"9bc9", x"9c77", x"9d23", x"9dcf", x"9e7a", x"9f24",
x"9fcd", x"a075", x"a11d", x"a1c3", x"a269", x"a30e", x"a3b2", x"a455", x"a4f8", x"a59a",
x"a63a", x"a6da", x"a77a", x"a818", x"a8b6", x"a953", x"a9ef", x"aa8a", x"ab25", x"abbf",
x"ac58", x"acf0", x"ad88", x"ae1f", x"aeb5", x"af4b", x"afe0", x"b074", x"b107", x"b19a",
x"b22c", x"b2bd", x"b34e", x"b3de", x"b46d", x"b4fb", x"b589", x"b617", x"b6a3", x"b72f",
x"b7bb", x"b845", x"b8cf", x"b959", x"b9e1", x"ba6a", x"baf1", x"bb78", x"bbfe", x"bc84",
x"bd09", x"bd8e", x"be12" );
*/
constant SQUARE_LOOKUP : square_table_t := ( x"0000", x"011d", x"0234", x"0344", x"044d", x"0550", x"064e", x"0745", x"0837",
x"0924", x"0a0c", x"0aee", x"0bcc", x"0ca5", x"0d79", x"0e49", x"0f15", x"0fdd",
x"10a0", x"1160", x"121c", x"12d4", x"1388", x"143a", x"14e7", x"1592", x"1639",
x"16de", x"177f", x"181d", x"18b9" );
constant TND_LOOKUP : tnd_table_t := ( x"0000", x"00a5", x"0148", x"01ea", x"028b", x"032a", x"03c8", x"0465", x"0501", x"059b",
x"0634", x"06cc", x"0763", x"07f8", x"088d", x"0920", x"09b2", x"0a43", x"0ad3", x"0b62",
x"0bef", x"0c7c", x"0d08", x"0d92", x"0e1c", x"0ea4", x"0f2c", x"0fb2", x"1037", x"10bc",
x"113f", x"11c2", x"1244", x"12c4", x"1344", x"13c3", x"1441", x"14be", x"153a", x"15b5",
x"162f", x"16a9", x"1722", x"1799", x"1810", x"1887", x"18fc", x"1970", x"19e4", x"1a57",
x"1ac9", x"1b3b", x"1bab", x"1c1b", x"1c8a", x"1cf9", x"1d66", x"1dd3", x"1e3f", x"1eab",
x"1f15", x"1f7f", x"1fe9", x"2051", x"20b9", x"2121", x"2187", x"21ed", x"2253", x"22b7",
x"231b", x"237f", x"23e1", x"2444", x"24a5", x"2506", x"2566", x"25c6", x"2625", x"2684",
x"26e2", x"273f", x"279c", x"27f8", x"2853", x"28af", x"2909", x"2963", x"29bd", x"2a15",
x"2a6e", x"2ac6", x"2b1d", x"2b74", x"2bca", x"2c20", x"2c75", x"2cca", x"2d1e", x"2d72",
x"2dc5", x"2e18", x"2e6a", x"2ebc", x"2f0d", x"2f5e", x"2faf", x"2fff", x"304e", x"309d",
x"30ec", x"313a", x"3188", x"31d5", x"3222", x"326f", x"32bb", x"3306", x"3351", x"339c",
x"33e6", x"3430", x"347a", x"34c3", x"350c", x"3554", x"359c", x"35e4", x"362b", x"3672",
x"36b8", x"36fe", x"3744", x"3789", x"37ce", x"3813", x"3857", x"389b", x"38de", x"3921",
x"3964", x"39a6", x"39e9", x"3a2a", x"3a6c", x"3aad", x"3aee", x"3b2e", x"3b6e", x"3bae",
x"3bed", x"3c2c", x"3c6b", x"3caa", x"3ce8", x"3d26", x"3d63", x"3da0", x"3ddd", x"3e1a",
x"3e56", x"3e92", x"3ece", x"3f09", x"3f44", x"3f7f", x"3fba", x"3ff4", x"402e", x"4068",
x"40a1", x"40da", x"4113", x"414c", x"4184", x"41bc", x"41f4", x"422c", x"4263", x"429a",
x"42d1", x"4307", x"433d", x"4373", x"43a9", x"43df", x"4414", x"4449", x"447e", x"44b2",
x"44e6", x"451a", x"454e", x"4582", x"45b5", x"45e8", x"461b", x"464d", x"4680", x"46b2",
x"46e4", x"4715", x"4747" );
constant REG_4014 : std_logic_vector(4 downto 0) := "10100";
constant REG_4015 : std_logic_vector(4 downto 0) := "10101";
constant REG_4016 : std_logic_vector(4 downto 0) := "10110";
constant REG_4017 : std_logic_vector(4 downto 0) := "10111";
constant REBOOT_CLK : natural := 12; -- @todo correct reset behavior, not working, value should be between 12 and 13 for (blargg 09.reset_timing)
signal s_clk_divider : natural range 0 to 37281 := REBOOT_CLK;
signal s_apu_clk : std_logic;
signal s_envelope_clk : std_logic;
signal s_lcounter_clk : std_logic;
signal s_envelope_signal : std_logic;
signal s_lcounter_signal : std_logic;
signal s_apu_signal : std_logic := '1';
signal s_mode : std_logic := '0';
signal s_int_disable : std_logic := '0';
signal s_read_apu : boolean;
signal s_read_r15 : boolean;
signal s_read_r16 : boolean;
signal s_read_r17 : boolean;
signal s_write_r14 : std_logic;
signal s_write_r15 : boolean;
signal s_write_r16 : boolean;
signal s_write_r17 : boolean;
signal s_write_apu : boolean;
signal s_square1_q : std_logic_vector(3 downto 0) := "0000";
signal s_square2_q : std_logic_vector(3 downto 0) := "0000";
signal s_square_sum : std_logic_vector(4 downto 0);
signal s_square_index : integer range 0 to 30;
signal s_tnd_sum : std_logic_vector(7 downto 0);
signal s_tnd_index : integer range 0 to 202;
signal s_frame_int_pending : std_logic := '0';
signal s_square1_enable : std_logic := '0';
signal s_square2_enable : std_logic := '0';
signal s_triangle_enable : std_logic := '0';
signal s_noise_enable : std_logic := '0';
signal s_dmc_enable : std_logic := '0';
signal s_square1_active : std_logic := '0';
signal s_square2_active : std_logic := '0';
signal s_triangle_active : std_logic := '0';
signal s_noise_active : std_logic := '0';
signal s_dmc_active : std_logic := '0';
signal s_triangle_q : std_logic_vector(3 downto 0) := "0000";
signal s_noise_q : std_logic_vector(3 downto 0) := "0000";
signal s_dmc_q : std_logic_vector(6 downto 0) := 7x"00";
signal s_reload : std_logic := '0';
signal s_ctrl_strobe : std_logic := '0';
signal s_ctrl_a_clk : std_logic := '1';
signal s_ctrl_b_clk : std_logic := '1';
signal s_q : std_logic_vector(7 downto 0) := x"00";
signal s_oma_addr : std_logic_vector(7 downto 0) := x"00";
signal s_dmc_busy : std_logic;
signal s_dmc_data : std_logic_vector(7 downto 0);
signal s_dmc_request : std_logic;
signal s_dmc_addr : std_logic_vector(15 downto 0);
signal s_dmc_int_pending : std_logic;
signal s_clock_trigger : std_logic := '0';
signal s_frame_int_trigger : std_logic;
signal s_frame_int_active : std_logic;
signal s_frame_int_buffer : std_logic_vector(2 downto 0) := (others => '0');
signal s_frame_int_visible : std_logic;
signal s_last_cycle : std_logic;
signal s_data : std_logic_vector(7 downto 0) := x"00";
signal s_data_sync : std_logic_vector(7 downto 0);
signal s_r17_written : boolean := false;
signal s_write_r17_sync : boolean;
begin
sq1 : square_channel generic map ( INCREMENT => '0' ) port map
(
i_clk => i_clk,
i_clk_enable => i_clk_enable,
i_reset_n => i_reset_n,
i_apu_clk => s_apu_clk,
i_envelope_clk => s_envelope_clk,
i_lcounter_clk => s_lcounter_clk,
i_addr => i_addr(1 downto 0),
i_data => i_data,
i_write_enable => i_write_enable,
i_cs_n => i_cs_n or i_addr(4) or i_addr(3) or i_addr(2),
i_enable => s_square1_enable,
i_reload => s_reload,
o_active => s_square1_active,
o_q => s_square1_q
);
sq2 : square_channel generic map ( INCREMENT => '1' ) port map
(
i_clk => i_clk,
i_clk_enable => i_clk_enable,
i_reset_n => i_reset_n,
i_apu_clk => s_apu_clk,
i_envelope_clk => s_envelope_clk,
i_lcounter_clk => s_lcounter_clk,
i_addr => i_addr(1 downto 0),
i_data => i_data,
i_write_enable => i_write_enable,
i_cs_n => i_cs_n or i_addr(4) or i_addr(3) or not i_addr(2),
i_enable => s_square2_enable,
i_reload => s_reload,
o_active => s_square2_active,
o_q => s_square2_q
);
tr : triangle_channel port map
(
i_clk => i_clk,
i_clk_enable => i_clk_enable,
i_reset_n => i_reset_n,
i_envelope_clk => s_envelope_clk,
i_lcounter_clk => s_lcounter_clk,
i_addr => i_addr(1 downto 0),
i_data => i_data,
i_write_enable => i_write_enable,
i_cs_n => i_cs_n or i_addr(4) or not i_addr(3) or i_addr(2),
i_enable => s_triangle_enable,
i_reload => s_reload,
o_active => s_triangle_active,
o_q => s_triangle_q
);
ns : noise_channel port map
(
i_clk => i_clk,
i_clk_enable => i_clk_enable,
i_reset_n => i_reset_n,
i_apu_clk => s_apu_clk,
i_envelope_clk => s_envelope_clk,
i_lcounter_clk => s_lcounter_clk,
i_addr => i_addr(1 downto 0),
i_data => i_data,
i_write_enable => i_write_enable,
i_cs_n => i_cs_n or i_addr(4) or not i_addr(3) or not i_addr(2),
i_enable => s_noise_enable,
i_reload => s_reload,
i_video_mode => i_video_mode,
o_active => s_noise_active,
o_q => s_noise_q
);
dmc : dmc_channel port map
(
i_clk => i_clk,
i_clk_enable => i_clk_enable,
i_reset_n => i_reset_n,
i_addr => i_addr(1 downto 0),
i_data => i_data,
i_write_enable => i_write_enable,
i_dma_busy => s_dmc_busy,
i_dma_data => s_dmc_data,
i_cs_n => i_cs_n or not i_addr(4) or i_addr(3) or i_addr(2),
i_enable => s_dmc_enable,
i_reload => s_reload,
i_video_mode => i_video_mode,
o_dma_request => s_dmc_request,
o_dma_addr => s_dmc_addr,
o_active => s_dmc_active,
o_int_pending => s_dmc_int_pending,
o_q => s_dmc_q
);
dma_cmp : dma port map
(
i_clk => i_clk,
i_clk_enable => i_clk_enable,
i_reset_n => i_reset_n,
i_write_enable => i_dma_write_enable,
i_seq_enable => s_write_r14,
i_seq_addr => s_oma_addr,
i_single_enable => s_dmc_request,
i_single_addr => s_dmc_addr,
i_data => i_dma_q,
o_single_busy => s_dmc_busy,
o_single_q => s_dmc_data,
o_addr => o_dma_addr,
o_data => o_dma_data,
o_write_enable => o_dma_write_enable,
o_ready => o_dma_ready,
o_active => o_dma_active
);
-- Mixer
s_square_sum <= ('0' & s_square1_q) + ('0' & s_square2_q);
s_square_index <= to_integer(unsigned(s_square_sum));
s_tnd_sum <= s_triangle_q * x"3" + ("000" & s_noise_q & '0') + ('0' & s_dmc_q);
s_tnd_index <= to_integer(unsigned(s_tnd_sum));
o_audio <= SQUARE_LOOKUP(s_square_index) + TND_LOOKUP(s_tnd_index);
-- Interrupt Disable
process (i_clk)
begin
if rising_edge(i_clk) then
if i_reset_n = '0' then
s_int_disable <= '0';
elsif i_clk_enable = '1' then
if s_write_r17_sync then
s_int_disable <= s_data_sync(6);
end if;
end if;
end if;
end process;
-- IRQ
process (i_clk)
begin
if rising_edge(i_clk) then
if i_reset_n = '0' then
s_frame_int_pending <= '0';
elsif i_clk_enable = '1' then
if s_write_r17_sync and (s_data_sync(6) = '1') then
s_frame_int_pending <= '0';
elsif s_read_r15 then
s_frame_int_pending <= '0';
elsif s_frame_int_trigger then
s_frame_int_pending <= '1';
end if;
end if;
end if;
end process;
process (i_clk)
begin
if rising_edge(i_clk) then
if i_reset_n = '0' then
s_frame_int_buffer <= (others => '0');
elsif i_clk_enable = '1' then
s_frame_int_buffer <= s_frame_int_buffer(1 downto 0) & s_frame_int_active;
end if;
end if;
end process;
process (i_clk)
begin
if rising_edge(i_clk) then
if i_reset_n = '0' then
s_frame_int_visible <= '0';
elsif i_clk_enable = '1' then
s_frame_int_visible <= s_frame_int_trigger or s_frame_int_pending;
end if;
end if;
end process;
o_int_n <= s_frame_int_pending nor s_dmc_int_pending;
s_frame_int_active <= s_last_cycle and not s_int_disable and not s_mode;
s_frame_int_trigger <= s_frame_int_active or s_frame_int_buffer(2);
s_last_cycle <= '1' when (s_clk_divider = 29829) else '0';
-- Frame Sequencer
process (i_clk)
begin
if rising_edge(i_clk) then
if i_reset_n = '0' then
s_mode <= '0';
s_clock_trigger <= '0';
elsif i_clk_enable = '1' then
s_clock_trigger <= '0';
if s_write_r17_sync then
s_mode <= s_data_sync(7);
s_clock_trigger <= s_data_sync(7);
end if;
end if;
end if;
end process;
process (i_clk)
begin
if rising_edge(i_clk) then
if i_reset_n = '0' then
s_clk_divider <= REBOOT_CLK;
elsif i_clk_enable = '1' then
if s_write_r17_sync or ((s_mode = '0') and (s_clk_divider = 29829)) or ((s_mode = '1') and (s_clk_divider = 37281)) then
s_clk_divider <= 0;
else
s_clk_divider <= s_clk_divider + 1;
end if;
end if;
end if;
end process;
process (i_clk)
begin
if rising_edge(i_clk) then
if i_reset_n = '0' then
s_envelope_signal <= '0';
s_lcounter_signal <= '0';
s_apu_signal <= '1';
elsif i_clk_enable = '1' then
s_apu_signal <= not s_apu_signal;
if s_clock_trigger = '1' then
s_envelope_signal <= '1';
s_lcounter_signal <= '1';
else
case s_clk_divider is
when 7457 =>
s_envelope_signal <= '1';
s_lcounter_signal <= '0';
when 14913 =>
s_envelope_signal <= '1';
s_lcounter_signal <= '1';
when 22371 =>
s_envelope_signal <= '1';
s_lcounter_signal <= '0';
when 29829 =>
s_envelope_signal <= not s_mode;
s_lcounter_signal <= not s_mode;
when 37281 =>
s_envelope_signal <= '1';
s_lcounter_signal <= '1';
when others =>
s_envelope_signal <= '0';
s_lcounter_signal <= '0';
end case;
end if;
end if;
end if;
end process;
s_apu_clk <= s_apu_signal and i_clk_enable;
s_envelope_clk <= s_envelope_signal and i_clk_enable;
s_lcounter_clk <= s_lcounter_signal and i_clk_enable;
-- APU Controlling
process (i_clk)
begin
if rising_edge(i_clk) then
if i_reset_n = '0' then
s_square1_enable <= '0';
s_square2_enable <= '0';
s_triangle_enable <= '0';
s_noise_enable <= '0';
s_dmc_enable <= '0';
elsif i_clk_enable = '1' then
if s_write_r15 then
s_square1_enable <= i_data(0);
s_square2_enable <= i_data(1);
s_triangle_enable <= i_data(2);
s_noise_enable <= i_data(3);
s_dmc_enable <= i_data(4);
end if;
end if;
end if;
end process;
process (i_clk)
begin
if rising_edge(i_clk) then
if i_reset_n = '0' then
s_reload <= '0';
elsif i_clk_enable = '1' then
if s_write_r15 then
s_reload <= '1';
else
s_reload <= '0';
end if;
end if;
end if;
end process;
-- OMA-DMA
process (i_clk)
begin
if rising_edge(i_clk) then
if i_reset_n = '0' then
s_oma_addr <= x"00";
elsif (i_clk_enable = '1') and (s_write_r14 = '1') then
s_oma_addr <= i_data;
end if;
end if;
end process;
-- Read Port
process (i_clk)
begin
if rising_edge(i_clk) then
if i_reset_n = '0' then
s_q <= x"00";
elsif (i_clk_enable = '1') and s_read_apu then
case i_addr is
when REG_4015 =>
s_q <= s_dmc_int_pending & s_frame_int_visible & '0' & s_dmc_active & s_noise_active & s_triangle_active & s_square2_active & s_square1_active;
when REG_4016 =>
s_q <= "0000000" & not i_ctrl_a_data;
when REG_4017 =>
s_q <= "0000000" & not i_ctrl_b_data;
when others =>
s_q <= x"00";
end case;
end if;
end if;
end process;
o_q <= s_q;
-- Write Port
process (i_clk)
begin
if rising_edge(i_clk) then
if i_reset_n = '0' then
s_data <= x"00";
s_r17_written <= false;
elsif i_clk_enable = '1' then
s_r17_written <= s_write_r17;
if s_write_apu then
s_data <= i_data;
end if;
end if;
end if;
end process;
s_write_apu <= (i_cs_n = '0') and (i_write_enable = '1');
s_write_r14 <= '1' when s_write_apu and (i_addr = REG_4014) else '0';
s_write_r15 <= s_write_apu and (i_addr = REG_4015);
s_write_r16 <= s_write_apu and (i_addr = REG_4016);
s_write_r17 <= s_write_apu and (i_addr = REG_4017);
s_write_r17_sync <= false when s_apu_signal = '0' else s_r17_written or s_write_r17;
s_data_sync <= i_data when s_write_apu else s_data;
-- Read Controller A
process (i_clk)
begin
if rising_edge(i_clk) then
if i_reset_n = '0' then
s_ctrl_a_clk <= '1';
elsif i_clk_enable = '1' then
s_ctrl_a_clk <= '1';
if s_read_r16 then
s_ctrl_a_clk <= '0';
end if;
end if;
end if;
end process;
o_ctrl_a_clk <= s_ctrl_a_clk;
-- Read Controller B
process (i_clk)
begin
if rising_edge(i_clk) then
if i_reset_n = '0' then
s_ctrl_b_clk <= '1';
elsif i_clk_enable = '1' then
s_ctrl_b_clk <= '1';
if s_read_r17 then
s_ctrl_b_clk <= '0';
end if;
end if;
end if;
end process;
o_ctrl_b_clk <= s_ctrl_b_clk;
-- Write Controller Strobe
process (i_clk)
begin
if rising_edge(i_clk) then
if i_reset_n = '0' then
s_ctrl_strobe <= '0';
elsif (i_clk_enable = '1') and s_write_r16 then
s_ctrl_strobe <= i_data(0);
end if;
end if;
end process;
o_ctrl_strobe <= s_ctrl_strobe;
-- Misc
s_read_apu <= (i_cs_n = '0') and (i_write_enable = '0');
s_read_r15 <= s_read_apu and (i_addr = REG_4015);
s_read_r16 <= s_read_apu and (i_addr = REG_4016);
s_read_r17 <= s_read_apu and (i_addr = REG_4017);
end behavioral; | gpl-3.0 | c427c8a1ad5121fde12d7b147d6a2ab7 | 0.584033 | 2.477173 | false | false | false | false |
varunnagpaal/Digital-Hardware-Modelling | vhdl/filter/moving-avg/fir_moving_avg_time_mux_multiple.vhdl | 1 | 10,843 | -- Author: Varun Nagpal
-- May 4th, 2019
library IEEE;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
-- This design implements an FIR Moving Average filter
-- which averages L points
--
-- y[n] = ( x[n] + x[n-1] + .. + x[n-L-1] ) / L
-- = summation( x[n-k], k = 0 to L-1 ) / L
--
-- L= Number of points to be averaged or length of filter
-- N = L-1 = order of the filter
--
-- To design above FIR filer using R adders (resources),
-- we modify the difference equation in two ways below:
--
-- 1. y[n] = summation( summation( x[ n - r x M - s], s = 0 to M-1 ), r = 0 to R-1 ) / L
--
-- where,
-- M = L/R = Samples to be processed per resource (adder)
-- r = resource id = 0 to R-1
-- s = sample id = 0 to M-1
--
-- This allocates resource id
-- 0 with sub-sequence : x[n] x[n-1] ... x[n-M+1]
-- 1 with sub-sequence : x[n-M] x[n-M-1] ... x[n-2M+1]
-- 2 with sub-sequence : x[n-2M] x[n-2M-1] ... x[n-3M+1]
-- ...
-- R-1 with sub-sequence : x[n-(R-1)M] x[n-(R-1)M-1] ... x[n-RM+1] = x[n-L+1]
--
-- 2. y[n] = summation( summation( x[ n - R x s - r], s = 0 to M-1 ), r = 0 to R-1 ) / L
--
-- where,
-- M = L/R = Samples to be processed per resource (adder)
-- r = resource id = 0 to R-1
-- s = sample id = 0 to M-1
--
-- This allocates rth resource id with subsequence
-- m = 0 m = 1 m = M-1
-- r = 0 : x[n-1] x[n-1-R] ... x[n-1-RM+R]
-- r = 1 : x[n-2] x[n-2-R] ... x[n-2-RM+R]
-- r = 2 : x[n-3] x[n-3-R] ... x[n-3-RM+R]
-- ..
-- r = R-1 : x[n-R] x[n-R-R] ... x[n-R-RM+R] = x[n-RM]= x[n-L]
--
-- While we can implement any of above two equations,
-- in our design we implement the second of the above
-- two equations
entity fir is
generic( L : natural := 16; -- L = Filter length or number of points to be averaged
L_BW : natural := 4; -- L_BW = Ceil(Log2(L))
R : natural := 4; -- R = Number of resources (adders and multiplexers)
R_BW : natural := 2; -- R_BW = Ceil(Log2(R))
M : natural := 4; -- M = L/R = Samples to be processed per resource (adder)
M_BW : natural := 2; -- M_BW = Ceil(Log2(M)) = number of select bits for M samples
W : natural := 16 ); -- W = Bit width of input and output sample data (signed)
port (clk : in std_logic; -- clock
reset_n : in std_logic; -- active low asynchronous reset
fir_en : in std_logic; -- handshake signal
fir_in : in std_logic_vector( W-1 downto 0 ); -- sample inout x[n]
fir_out : out std_logic_vector( W-1 downto 0 ); -- sample output y[n]
fir_rdy : out std_logic -- handshake signal
);
end fir;
architecture rtl of fir is
type t_reg_x is array ( 0 to L-1 ) of signed( W-1 downto 0 );
signal reg_x : t_reg_x := ( others => ( others => '0' ) );
-- R outputs of R muxes (one mux output per resource)
type t_array_mux_out_x is array ( 0 to R-1 ) of signed( W-1 downto 0 );
signal sig_array_mux_out_x : t_array_mux_out_x := ( others => ( others => '0') );
-- Each of the R muxes has M data inputs requiring total of L=MR data inputs
--type t_array_mux_in_x is array ( 0 to L-1 ) of signed( W-1 downto 0 );
--signal sig_array_mux_in_x : t_array_mux_in_x := ( others => ( others => '0') );
type t_mux_in is array ( 0 to R-1, 0 to M-1 ) of signed( W-1 downto 0 );
signal sig_array_mux_in_x : t_mux_in := ( others => ( others => ( others => '0') ) );
-- M_BW-bit select signal for each mux where M_BW = Ceil(Log2(M)), M = L/R
signal sig_mux_sel_cnt : unsigned( M_BW-1 downto 0 ) := ( others => '0' );
signal sig_mux_sel_cnt_next : unsigned( M_BW-1 downto 0 ) := ( others => '0' );
-- R-1 signed adders to add R mux outputs.
-- i.e. 0, 1..., (R-2)th signed adders
-- Note that we set bit size of each adder output equal to the
-- maximum bit-size required to accumulate addition of R signed
-- numbers which is W+R_BW bits where R_BW = Ceil(Log2(R))
type t_array_signed_adders is array ( 0 to R-2 ) of signed( W+R_BW-1 downto 0 );
signal sig_array_signed_adders: t_array_signed_adders := ( others => ( others => '0' ) );
-- (R-1)th signed adder is used to accumulate result of
-- R-1 signed adders i.e output of the (R-2)th signed adder
signal sig_y_sum : signed( W+L_BW-1 downto 0 ) := ( others => '0' ); -- add/sub of L = MR signed numbers each of W bit-width
-- requires total W+L_BW bits where L_BW = Ceil(log2(L))
signal reg_y_sum : signed( W+L_BW-1 downto 0 ) := ( others => '0' );
signal sig_y_out : signed( W+L_BW-1 downto 0 ) := ( others => '0' );
signal reg_fir_rdy : std_logic := '0';
begin
-- Generate ready signal 1 cc after enable input changes
process( clk, reset_n )
begin
if( reset_n = '0' ) then
reg_fir_rdy <= '0';
fir_rdy <= '0';
elsif ( rising_edge(clk) ) then
if( fir_en = '1' ) then
reg_fir_rdy <= '1';
else
reg_fir_rdy <= '0';
end if;
fir_rdy <= reg_fir_rdy;
end if;
end process;
-- Generate x[n-1],x[n-2]...x[n-L+1], x[n-L]
-- Shift x[n] after every M clock cycles
process ( clk, reset_n )
begin
if ( reset_n = '0' ) then
for i in 0 to (L-1) loop
reg_x(i) <= ( others => '0');
end loop;
elsif ( rising_edge(clk) ) then
-- Shift new data only when filter is enabled
if( fir_en = '1' ) then
if ( sig_mux_sel_cnt = (M-1) ) then
reg_x(0) <= signed(fir_in);
for i in 1 to (L-1) loop
reg_x(i) <= reg_x(i-1);
end loop;
end if;
end if;
end if;
end process;
-- Allocate following data lines as inputs to the rth multiplexer:
-- j = 0 j = 1 j = M-1
-- i = 0 : x[n-1] x[n-1-R] ... x[n-1-RM+R]
-- i = 1 : x[n-2] x[n-2-R] ... x[n-2-RM+R]
-- i = 2 : x[n-3] x[n-3-R] ... x[n-3-RM+R]
-- ..
-- i = R-1 : x[n-R] x[n-R-R] ... x[n-R-RM+R] = x[n-RM]= x[n-L]
process( reg_x )
begin
for i in 0 to R-1 loop
for j in 0 to M-1 loop
sig_array_mux_in_x( i, j ) <= reg_x( i + j*R );
end loop;
end loop;
end process;
-- Generate select signal for the muxes using a counter (mod M)
process ( clk, reset_n )
begin
if ( reset_n = '0' ) then
sig_mux_sel_cnt <= to_unsigned( 0, sig_mux_sel_cnt'LENGTH );
elsif ( rising_edge( clk ) ) then
if ( reg_fir_rdy = '1' ) then
sig_mux_sel_cnt <= sig_mux_sel_cnt_next;
end if;
end if;
end process;
sig_mux_sel_cnt_next <= ( others => '0' ) when sig_mux_sel_cnt = ( M-1 ) else
( sig_mux_sel_cnt + 1 );
-- Generate the R muxes
process ( sig_array_mux_in_x, sig_mux_sel_cnt )
begin
for i in 0 to R-1 loop
sig_array_mux_out_x( i ) <= sig_array_mux_in_x( i, to_integer( sig_mux_sel_cnt ) );
end loop;
end process;
-- Generate R-1 signed adders for R muxes.
-- i.e. 0, 1..., (R-2)th signed adders
-- A[0] = M[0]+M[1]
-- A[1] = A[0]+M[2]
-- A[2] = A[1]+M[3]
-- ....
-- A[R-2] = A[R-3]+M[R-1]
--
-- Note: The last signed adder to be used for
-- accumulation is generated separately
comb_adders : process ( sig_array_mux_out_x, sig_array_signed_adders )
begin
sig_array_signed_adders(0) <= resize( sig_array_mux_out_x(0), sig_array_signed_adders(0)'LENGTH ) +
resize( sig_array_mux_out_x(1), sig_array_signed_adders(0)'LENGTH );
for i in 1 to R-2 loop
sig_array_signed_adders(i)<= resize( sig_array_signed_adders(i-1), sig_array_signed_adders(i)'LENGTH ) +
resize( sig_array_mux_out_x(i+1), sig_array_signed_adders(i)'LENGTH );
end loop;
end process comb_adders;
-- Generate Y[n] i.e. Rth signed adder which accumulates
-- result of R-1 signed adders i.e the output of
-- (R-1)th signed adder
-- A[R-1] = A[R-1] + A[R-2]
-- Y[n] = Y[n-1] + A[R-2];
sig_y_sum <= reg_y_sum + resize( sig_array_signed_adders( R-2 ), sig_y_sum'LENGTH ) ;
-- Generate Y[n-1]
process( clk, reset_n )
begin
if ( reset_n = '0' ) then
reg_y_sum <= ( others => '0');
elsif ( rising_edge(clk) ) then
if( fir_en = '1' ) then
if ( sig_mux_sel_cnt = (M-1) ) then
-- reset the accumulated sum after every M clock cycles
reg_y_sum <= ( others => '0');
else
reg_y_sum <= sig_y_sum;
end if;
end if;
end if;
end process;
-- y[n] = Y[n]/L = Y[n] >> L_BW, where L_BW=Ceil(log2(L))
sig_y_out <= sig_y_sum srl L_BW;
process ( clk, reset_n )
variable temp : signed( W-1 downto 0 ) := ( others => '0' );
begin
if ( reset_n = '0' ) then
fir_out <= ( others => '0' );
elsif ( rising_edge( clk ) ) then
temp := ( others => '0' );
if( fir_en = '1' ) then
-- Produce filter output after every M clock cycles
if ( sig_mux_sel_cnt = (M-1) ) then
-- Round towards 0.
-- This means when doing binary division of a negative signed number
-- with a positive number through right shifting operation,
-- the rounding of quotient happens towards +infinity.
-- So there is a DC offset in negative quotients which needs to be eliminated
-- by rounding negative quotients towards zero instead of +infinity
temp := sig_y_out( W-1 downto 0 );
if ( temp(W-1) = '1' ) then
temp := temp+1;
end if;
fir_out <= std_logic_vector( temp );
end if;
end if;
end if;
end process;
end rtl; | mit | 3c34d355f81b16de5c3f5fffdc4fafe0 | 0.480494 | 3.120288 | false | false | false | false |
natsutan/NPU | fpga_implement/npu8/npu8.srcs/sources_1/ip/mult16_16/mult16_16_sim_netlist.vhdl | 1 | 595,269 | -- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (lin64) Build 1733598 Wed Dec 14 22:35:42 MST 2016
-- Date : Sat Jan 21 14:32:47 2017
-- Host : natu-OMEN-by-HP-Laptop running 64-bit Ubuntu 16.04.1 LTS
-- Command : write_vhdl -force -mode funcsim
-- /media/natu/data/proj/myproj/NPU/fpga_implement/npu8/npu8.srcs/sources_1/ip/mult16_16/mult16_16_sim_netlist.vhdl
-- Design : mult16_16
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xcku035-fbva676-3-e
-- --------------------------------------------------------------------------------
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`protect end_protected
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity mult16_16_mult_gen_v12_0_12 is
port (
CLK : in STD_LOGIC;
A : in STD_LOGIC_VECTOR ( 15 downto 0 );
B : in STD_LOGIC_VECTOR ( 15 downto 0 );
CE : in STD_LOGIC;
SCLR : in STD_LOGIC;
ZERO_DETECT : out STD_LOGIC_VECTOR ( 1 downto 0 );
P : out STD_LOGIC_VECTOR ( 7 downto 0 );
PCASC : out STD_LOGIC_VECTOR ( 47 downto 0 )
);
attribute C_A_TYPE : integer;
attribute C_A_TYPE of mult16_16_mult_gen_v12_0_12 : entity is 1;
attribute C_A_WIDTH : integer;
attribute C_A_WIDTH of mult16_16_mult_gen_v12_0_12 : entity is 16;
attribute C_B_TYPE : integer;
attribute C_B_TYPE of mult16_16_mult_gen_v12_0_12 : entity is 1;
attribute C_B_VALUE : string;
attribute C_B_VALUE of mult16_16_mult_gen_v12_0_12 : entity is "10000001";
attribute C_B_WIDTH : integer;
attribute C_B_WIDTH of mult16_16_mult_gen_v12_0_12 : entity is 16;
attribute C_CCM_IMP : integer;
attribute C_CCM_IMP of mult16_16_mult_gen_v12_0_12 : entity is 0;
attribute C_CE_OVERRIDES_SCLR : integer;
attribute C_CE_OVERRIDES_SCLR of mult16_16_mult_gen_v12_0_12 : entity is 0;
attribute C_HAS_CE : integer;
attribute C_HAS_CE of mult16_16_mult_gen_v12_0_12 : entity is 0;
attribute C_HAS_SCLR : integer;
attribute C_HAS_SCLR of mult16_16_mult_gen_v12_0_12 : entity is 0;
attribute C_HAS_ZERO_DETECT : integer;
attribute C_HAS_ZERO_DETECT of mult16_16_mult_gen_v12_0_12 : entity is 0;
attribute C_LATENCY : integer;
attribute C_LATENCY of mult16_16_mult_gen_v12_0_12 : entity is 4;
attribute C_MODEL_TYPE : integer;
attribute C_MODEL_TYPE of mult16_16_mult_gen_v12_0_12 : entity is 0;
attribute C_MULT_TYPE : integer;
attribute C_MULT_TYPE of mult16_16_mult_gen_v12_0_12 : entity is 0;
attribute C_OPTIMIZE_GOAL : integer;
attribute C_OPTIMIZE_GOAL of mult16_16_mult_gen_v12_0_12 : entity is 1;
attribute C_OUT_HIGH : integer;
attribute C_OUT_HIGH of mult16_16_mult_gen_v12_0_12 : entity is 31;
attribute C_OUT_LOW : integer;
attribute C_OUT_LOW of mult16_16_mult_gen_v12_0_12 : entity is 24;
attribute C_ROUND_OUTPUT : integer;
attribute C_ROUND_OUTPUT of mult16_16_mult_gen_v12_0_12 : entity is 0;
attribute C_ROUND_PT : integer;
attribute C_ROUND_PT of mult16_16_mult_gen_v12_0_12 : entity is 0;
attribute C_VERBOSITY : integer;
attribute C_VERBOSITY of mult16_16_mult_gen_v12_0_12 : entity is 0;
attribute C_XDEVICEFAMILY : string;
attribute C_XDEVICEFAMILY of mult16_16_mult_gen_v12_0_12 : entity is "kintexu";
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of mult16_16_mult_gen_v12_0_12 : entity is "mult_gen_v12_0_12";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of mult16_16_mult_gen_v12_0_12 : entity is "yes";
end mult16_16_mult_gen_v12_0_12;
architecture STRUCTURE of mult16_16_mult_gen_v12_0_12 is
signal \<const0>\ : STD_LOGIC;
signal NLW_i_mult_PCASC_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 0 );
signal NLW_i_mult_ZERO_DETECT_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute C_A_TYPE of i_mult : label is 1;
attribute C_A_WIDTH of i_mult : label is 16;
attribute C_B_TYPE of i_mult : label is 1;
attribute C_B_VALUE of i_mult : label is "10000001";
attribute C_B_WIDTH of i_mult : label is 16;
attribute C_CCM_IMP of i_mult : label is 0;
attribute C_CE_OVERRIDES_SCLR of i_mult : label is 0;
attribute C_HAS_CE of i_mult : label is 0;
attribute C_HAS_SCLR of i_mult : label is 0;
attribute C_HAS_ZERO_DETECT of i_mult : label is 0;
attribute C_LATENCY of i_mult : label is 4;
attribute C_MODEL_TYPE of i_mult : label is 0;
attribute C_MULT_TYPE of i_mult : label is 0;
attribute C_OUT_HIGH of i_mult : label is 31;
attribute C_OUT_LOW of i_mult : label is 24;
attribute C_ROUND_OUTPUT of i_mult : label is 0;
attribute C_ROUND_PT of i_mult : label is 0;
attribute C_VERBOSITY of i_mult : label is 0;
attribute C_XDEVICEFAMILY of i_mult : label is "kintexu";
attribute c_optimize_goal of i_mult : label is 1;
attribute downgradeipidentifiedwarnings of i_mult : label is "yes";
begin
PCASC(47) <= \<const0>\;
PCASC(46) <= \<const0>\;
PCASC(45) <= \<const0>\;
PCASC(44) <= \<const0>\;
PCASC(43) <= \<const0>\;
PCASC(42) <= \<const0>\;
PCASC(41) <= \<const0>\;
PCASC(40) <= \<const0>\;
PCASC(39) <= \<const0>\;
PCASC(38) <= \<const0>\;
PCASC(37) <= \<const0>\;
PCASC(36) <= \<const0>\;
PCASC(35) <= \<const0>\;
PCASC(34) <= \<const0>\;
PCASC(33) <= \<const0>\;
PCASC(32) <= \<const0>\;
PCASC(31) <= \<const0>\;
PCASC(30) <= \<const0>\;
PCASC(29) <= \<const0>\;
PCASC(28) <= \<const0>\;
PCASC(27) <= \<const0>\;
PCASC(26) <= \<const0>\;
PCASC(25) <= \<const0>\;
PCASC(24) <= \<const0>\;
PCASC(23) <= \<const0>\;
PCASC(22) <= \<const0>\;
PCASC(21) <= \<const0>\;
PCASC(20) <= \<const0>\;
PCASC(19) <= \<const0>\;
PCASC(18) <= \<const0>\;
PCASC(17) <= \<const0>\;
PCASC(16) <= \<const0>\;
PCASC(15) <= \<const0>\;
PCASC(14) <= \<const0>\;
PCASC(13) <= \<const0>\;
PCASC(12) <= \<const0>\;
PCASC(11) <= \<const0>\;
PCASC(10) <= \<const0>\;
PCASC(9) <= \<const0>\;
PCASC(8) <= \<const0>\;
PCASC(7) <= \<const0>\;
PCASC(6) <= \<const0>\;
PCASC(5) <= \<const0>\;
PCASC(4) <= \<const0>\;
PCASC(3) <= \<const0>\;
PCASC(2) <= \<const0>\;
PCASC(1) <= \<const0>\;
PCASC(0) <= \<const0>\;
ZERO_DETECT(1) <= \<const0>\;
ZERO_DETECT(0) <= \<const0>\;
GND: unisim.vcomponents.GND
port map (
G => \<const0>\
);
i_mult: entity work.mult16_16_mult_gen_v12_0_12_viv
port map (
A(15 downto 0) => A(15 downto 0),
B(15 downto 0) => B(15 downto 0),
CE => '0',
CLK => CLK,
P(7 downto 0) => P(7 downto 0),
PCASC(47 downto 0) => NLW_i_mult_PCASC_UNCONNECTED(47 downto 0),
SCLR => '0',
ZERO_DETECT(1 downto 0) => NLW_i_mult_ZERO_DETECT_UNCONNECTED(1 downto 0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity mult16_16 is
port (
CLK : in STD_LOGIC;
A : in STD_LOGIC_VECTOR ( 15 downto 0 );
B : in STD_LOGIC_VECTOR ( 15 downto 0 );
P : out STD_LOGIC_VECTOR ( 7 downto 0 )
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of mult16_16 : entity is true;
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of mult16_16 : entity is "mult16_16,mult_gen_v12_0_12,{}";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of mult16_16 : entity is "yes";
attribute x_core_info : string;
attribute x_core_info of mult16_16 : entity is "mult_gen_v12_0_12,Vivado 2016.4";
end mult16_16;
architecture STRUCTURE of mult16_16 is
signal NLW_U0_PCASC_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 0 );
signal NLW_U0_ZERO_DETECT_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute C_A_TYPE : integer;
attribute C_A_TYPE of U0 : label is 1;
attribute C_A_WIDTH : integer;
attribute C_A_WIDTH of U0 : label is 16;
attribute C_B_TYPE : integer;
attribute C_B_TYPE of U0 : label is 1;
attribute C_B_VALUE : string;
attribute C_B_VALUE of U0 : label is "10000001";
attribute C_B_WIDTH : integer;
attribute C_B_WIDTH of U0 : label is 16;
attribute C_CCM_IMP : integer;
attribute C_CCM_IMP of U0 : label is 0;
attribute C_CE_OVERRIDES_SCLR : integer;
attribute C_CE_OVERRIDES_SCLR of U0 : label is 0;
attribute C_HAS_CE : integer;
attribute C_HAS_CE of U0 : label is 0;
attribute C_HAS_SCLR : integer;
attribute C_HAS_SCLR of U0 : label is 0;
attribute C_HAS_ZERO_DETECT : integer;
attribute C_HAS_ZERO_DETECT of U0 : label is 0;
attribute C_LATENCY : integer;
attribute C_LATENCY of U0 : label is 4;
attribute C_MODEL_TYPE : integer;
attribute C_MODEL_TYPE of U0 : label is 0;
attribute C_MULT_TYPE : integer;
attribute C_MULT_TYPE of U0 : label is 0;
attribute C_OUT_HIGH : integer;
attribute C_OUT_HIGH of U0 : label is 31;
attribute C_OUT_LOW : integer;
attribute C_OUT_LOW of U0 : label is 24;
attribute C_ROUND_OUTPUT : integer;
attribute C_ROUND_OUTPUT of U0 : label is 0;
attribute C_ROUND_PT : integer;
attribute C_ROUND_PT of U0 : label is 0;
attribute C_VERBOSITY : integer;
attribute C_VERBOSITY of U0 : label is 0;
attribute C_XDEVICEFAMILY : string;
attribute C_XDEVICEFAMILY of U0 : label is "kintexu";
attribute c_optimize_goal : integer;
attribute c_optimize_goal of U0 : label is 1;
attribute downgradeipidentifiedwarnings of U0 : label is "yes";
begin
U0: entity work.mult16_16_mult_gen_v12_0_12
port map (
A(15 downto 0) => A(15 downto 0),
B(15 downto 0) => B(15 downto 0),
CE => '1',
CLK => CLK,
P(7 downto 0) => P(7 downto 0),
PCASC(47 downto 0) => NLW_U0_PCASC_UNCONNECTED(47 downto 0),
SCLR => '0',
ZERO_DETECT(1 downto 0) => NLW_U0_ZERO_DETECT_UNCONNECTED(1 downto 0)
);
end STRUCTURE;
| bsd-3-clause | aee3305c15a141f6c80b271c138d73e5 | 0.95028 | 1.820556 | false | false | false | false |
besm6/micro-besm | tests/2910/vhdl/funct_block_alg_beh/components/reg/reg.vhdl | 1 | 1,691 | --------------------------------------------------------------------------------
--
-- AMD 2910 Benchmark (Functional blocks) (Algorithmic Behaviour of Funct blocks)
--
-- Source: AMD data book
--
-- VHDL Benchmark author Indraneel Ghosh
-- University Of California, Irvine, CA 92717
--
-- Developed on Feb 19, 1992
--
-- Verification Information:
--
-- Verified By whom? Date Simulator
-- -------- ------------ -------- ------------
-- Syntax yes Champaka Ramachandran Sept17, 92 ZYCAD
-- Functionality yes Champaka Ramachandran Sept17, 92 ZYCAD
--------------------------------------------------------------------------------
--library ZYCAD;
use work.types.all;
use work.MVL7_functions.all;
use work.synthesis_types.all;
entity reg is
port (
RLD_BAR : in MVL7;
load : in MVL7;
decr : in MVL7;
clk : in clock;
D : in MVL7_VECTOR(11 downto 0);
RE : inout MVL7_VECTOR(11 downto 0);
Rzero_bar : out MVL7
);
end reg;
architecture reg of reg is
begin
-------------------------------------------------------------------------------
reg_ctr : block ( (clk = '1') and (not clk'stable) )
begin
RE <= guarded D WHEN (( load = '1') or (RLD_BAR = '0')) ELSE -- load
RE - "000000000001" WHEN (decr = '1') and (RLD_BAR = '1') ELSE -- decr
RE ; -- hold
Rzero_bar <= RE(0) or RE(1) or RE(2) or RE(4) or RE(5) or RE(6) or RE(7) or RE(8) or RE(9) or RE(10) or RE (11);
end block reg_ctr;
-------------------------------------------------------------------------------
end reg;
| mit | 35a02ec3dfd2025851fd084f5f689ba6 | 0.43702 | 3.843182 | false | false | false | false |
besm6/micro-besm | tests/2910/vhdl/alg_beh/alg_beh2910.vhdl | 1 | 11,142 | --------------------------------------------------------------------------------
--
-- AMD 2910 Benchmark
--
-- Source: AMD data book
--
-- VHDL Benchmark author Indraneel Ghosh
-- University Of California, Irvine, CA 92717
--
-- Developed on Feb 19, 1992
--
-- Verification Information:
--
-- Verified By whom? Date Simulator
-- -------- ------------ -------- ------------
-- Syntax yes Champaka Ramachandran Sept17, 92 ZYCAD
-- Functionality yes Champaka Ramachandran Sept17, 92 ZYCAD
--------------------------------------------------------------------------------
use work.types.all;
use work.MVL7_functions.all;
use work.synthesis_types.all;
entity AM2910 is
port (
I : in MVL7_VECTOR(3 downto 0); -- 2910 instruction
CCEN_BAR : in MVL7; -- condition code enable input bit
CC_BAR : in MVL7; -- condition code input bit
RLD_BAR : in MVL7; -- R register load
CI : in MVL7; -- carry in
OEbar : in MVL7; -- tri-state driver
clk : in clock; -- clock
D : in MVL7_VECTOR(11 downto 0); -- direct inputs
Y : out MVL7_VECTOR(11 downto 0); -- output instruction word
PL_BAR : out MVL7; --
VECT_BAR : out MVL7; --
MAP_BAR : out MVL7; --
FULL_BAR : out MVL7 -- stack full flag
);
end AM2910;
architecture AM2910 of AM2910 is
begin
process
variable FAIL : MVL7; -- CC fail flag
variable SP : INTEGER range 0 to 5; -- stack pointer
variable STACK : MEMORY_12_bit(5 downto 0); -- stack register file
variable RE : MVL7_vector(11 downto 0);
variable uPC : MVL7_vector(11 downto 0);
variable Y_temp : MVL7_vector(11 downto 0);
begin
wait until ( (clk = '0') and (not clk'stable) );
fail := CC_bar and ( not CCEN_bar);
if (SP = 5) then -- NECCESSARY FOR CORRECT SIMULATION
FULL_BAR <= '0'; -- SINCE THIS PROCESS IS NOT TRIGERRED BY
else -- A RISING CLOCK EDGE
FULL_BAR <= '1';
end if;
---------------------------------------------------------------------------
case I is
when "0000" => -- JZ instruction
Y_temp := "000000000000";
if (RLD_BAR = '0') then
RE := D;
end if;
SP := 0;
uPC := "000000000000";
MAP_BAR <= '1';
VECT_BAR <= '1';
PL_BAR <= '0';
----------------------------------------------------------------------------
when "0001" => -- CJS instruction
if (FAIL = '0') then
Y_temp := D;
if (SP /= 5) then -- PUSH
SP := SP + 1;
end if;
STACK(SP) := uPC;
else
Y_temp := uPC;
end if;
if (RLD_BAR = '0') then
RE := D;
end if;
uPC := Y_temp + ("00000000000" & CI);
MAP_BAR <= '1';
VECT_BAR <= '1';
PL_BAR <= '0';
-------------------------------------------------------------------------------
when "0010" => -- JMAP instruction
Y_temp := D;
if (RLD_BAR = '0') then
RE := D;
end if;
uPC := Y_temp + ("00000000000" & CI);
MAP_BAR <= '0';
VECT_BAR <= '1';
PL_BAR <= '1';
-------------------------------------------------------------------------------
when "0011" => -- CJP instruction
if (FAIL = '1') then
Y_temp := uPC;
else
Y_temp := D;
end if;
if (RLD_BAR = '0') then
RE := D;
end if;
uPC := Y_temp + ("00000000000" & CI);
MAP_BAR <= '1';
VECT_BAR <= '1';
PL_BAR <= '0';
--------------------------------------------------------------------------------
when "0100" => -- PUSH instruction
Y_temp := uPC;
if ( FAIL = '0') or (RLD_BAR = '0') then
RE := D;
end if;
if (SP /= 5) then -- PUSH
SP := SP + 1;
end if;
STACK(SP) := uPC;
uPC := Y_temp + ("00000000000" & CI);
MAP_BAR <= '1';
VECT_BAR <= '1';
PL_BAR <= '0';
---------------------------------------------------------------------------------
when "0101" => -- JSRP instruction
if (FAIL = '1') then
Y_temp := RE;
else
Y_temp := D;
end if;
if (RLD_BAR = '0') then
RE := D;
end if;
if (SP /= 5) then -- PUSH
SP := SP + 1;
end if;
STACK(SP) := uPC;
uPC := Y_temp + ("00000000000" & CI);
MAP_BAR <= '1';
VECT_BAR <= '1';
PL_BAR <= '0';
---------------------------------------------------------------------------------
when "0110" => -- CJV instruction
if (FAIL = '1') then
Y_temp := uPC;
else
Y_temp := D;
end if;
if (RLD_BAR = '0') then
RE := D;
end if;
uPC := Y_temp + ("00000000000" & CI);
MAP_BAR <= '1';
VECT_BAR <= '0';
PL_BAR <= '1';
---------------------------------------------------------------------------------
when "0111" => -- JRP instruction
if (FAIL = '1') then
Y_temp := RE;
else
Y_temp := D;
end if;
if (RLD_BAR = '0') then
RE := D;
end if;
uPC := Y_temp + ("00000000000" & CI);
MAP_BAR <= '1';
VECT_BAR <= '1';
PL_BAR <= '0';
---------------------------------------------------------------------------------
when "1000" => -- RFCT instruction
if (RE = "000000000000") then
Y_temp := uPC;
if (SP /= 0) then -- POP
SP := SP - 1;
end if;
else
Y_temp := STACK(SP);
if (RLD_BAR = '1') then
RE := RE - "000000000001";
end if;
end if;
if ( RLD_BAR = '0') then
RE := D;
end if;
uPC := Y_temp + ("00000000000" & CI);
MAP_BAR <= '1';
VECT_BAR <= '1';
PL_BAR <= '0';
----------------------------------------------------------------------------------
when "1001" => -- RPCT instruction
if (RE /= "000000000000") then
Y_temp := D;
if (RLD_BAR = '1') then
RE := RE - "000000000001";
end if;
else
Y_temp := uPC;
end if;
if ( RLD_BAR = '0') then
RE := D;
end if;
uPC := Y_temp + ("00000000000" & CI);
MAP_BAR <= '1';
VECT_BAR <= '1';
PL_BAR <= '0';
-----------------------------------------------------------------------------------
when "1010" => -- CRTN instruction
if (FAIL = '0') then
Y_temp := STACK(SP);
if (SP /= 0) then
SP := SP - 1; -- pop
end if;
else
Y_temp := uPC;
end if;
if ( RLD_BAR = '0') then
RE := D;
end if;
uPC := Y_temp + ("00000000000" & CI);
MAP_BAR <= '1';
VECT_BAR <= '1';
PL_BAR <= '0';
------------------------------------------------------------------------------------
when "1011" => -- CJPP instruction
if (FAIL = '0') then
Y_temp := D;
if (SP /= 0) then -- pop
SP := SP - 1;
end if;
else
Y_temp := uPC;
end if;
if ( RLD_BAR = '0') then
RE := D;
end if;
uPC := Y_temp + ("00000000000" & CI);
MAP_BAR <= '1';
VECT_BAR <= '1';
PL_BAR <= '0';
----------------------------------------------------------------------------------
when "1100" => -- LDCT instruction
Y_temp := uPC;
RE := D;
uPC := Y_temp + ("00000000000" & CI);
MAP_BAR <= '1';
VECT_BAR <= '1';
PL_BAR <= '0';
----------------------------------------------------------------------------------
when "1101" => -- LOOP instruction
if (FAIL = '0') then
Y_temp := uPC;
if (SP /= 0) then -- pop
SP := SP - 1;
end if;
else
Y_temp := STACK(SP);
end if;
if ( RLD_BAR = '0') then
RE := D;
end if;
uPC := Y_temp + ("00000000000" & CI);
MAP_BAR <= '1';
VECT_BAR <= '1';
PL_BAR <= '0';
------------------------------------------------------------------------------
when "1110" => -- CONT instruction
Y_temp := uPC;
if ( RLD_BAR = '0') then
RE := D;
end if;
uPC := Y_temp + ("00000000000" & CI);
MAP_BAR <= '1';
VECT_BAR <= '1';
PL_BAR <= '0';
----------------------------------------------------------------------------
when "1111" => -- TWB instruction
if RE = "000000000000" then
if fail = '1' then
Y_temp := D;
else
Y_temp := uPC;
end if;
if (SP /= 0) then -- pop
SP := SP - 1;
end if;
else
if (FAIL = '0') then
Y_temp := uPC;
if (SP /= 0) then -- pop
SP := SP - 1;
end if;
else
Y_temp := stack(sp);
end if;
if(RLD_BAR = '1') then
RE := RE - "000000000001";
end if;
end if;
if ( RLD_BAR = '0') then
RE := D;
end if;
uPC := Y_temp + ("00000000000" & CI);
MAP_BAR <= '1';
VECT_BAR <= '1';
PL_BAR <= '0';
-------------------------------------------------------------------------------
when others =>
end case;
-- TRI-STATE DRIVER CONTROL
if OEbar = '0' then
Y <= Y_temp;
else
Y <= "ZZZZZZZZZZZZ";
end if;
end process;
end AM2910;
| mit | ea4e161970c361529333cae58e4d180b | 0.306049 | 4.534799 | false | false | false | false |
mrozo/programmable-digital-circuits | rs232monitor/freqDividerTb.vhd | 1 | 1,884 | LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY freqDividerTb IS
END freqDividerTb;
ARCHITECTURE behavior OF freqDividerTb IS
COMPONENT freqDivider
Generic (
divisor : integer
);
PORT(
clk : IN std_logic;
rst : IN std_logic;
enable : IN std_logic;
output : OUT std_logic
);
END COMPONENT;
--Inputs
signal clk : std_logic := '0';
signal rst : std_logic := '0';
signal enable : std_logic := '1';
--Outputs
signal clkDividedBy2 : std_logic;
signal clkDividedBy3 : std_logic;
signal clkDividedBy4 : std_logic;
signal clkDividedBy5 : std_logic;
signal clkDividedBy6 : std_logic;
signal clkDividedBy7 : std_logic;
-- Clock period definitions
constant clk_period : time := 10 ns;
BEGIN
clk <= not clk after clk_period;
divBy2: freqDivider
GENERIC MAP (divisor => 2)
PORT MAP (clk => clk, rst => rst, enable => enable, output => clkDividedBy2);
divBy3: freqDivider
GENERIC MAP (divisor => 3)
PORT MAP (clk => clk, rst => rst, enable => enable, output => clkDividedBy3);
divBy4: freqDivider
GENERIC MAP (divisor => 4)
PORT MAP (clk => clk, rst => rst, enable => enable, output => clkDividedBy4);
divBy5: freqDivider
GENERIC MAP (divisor => 5)
PORT MAP (clk => clk, rst => rst, enable => enable, output => clkDividedBy5);
divBy6: freqDivider
GENERIC MAP (divisor => 6)
PORT MAP (clk => clk, rst => rst, enable => enable, output => clkDividedBy6);
divBy7: freqDivider
GENERIC MAP (divisor => 7)
PORT MAP (clk => clk, rst => rst, enable => enable, output => clkDividedBy7);
END;
| bsd-3-clause | 0a19c018761c57ceb622ea99d20e24cd | 0.553609 | 3.966316 | false | false | false | false |
ShirmanXia/EE469SPRING16 | lab3/nios_system/nios_system_inst.vhd | 1 | 5,883 | component nios_system is
port (
alu_a_export : out std_logic_vector(31 downto 0); -- export
alu_b_export : out std_logic_vector(31 downto 0); -- export
alu_carry_out_export : in std_logic := 'X'; -- export
alu_control_export : out std_logic_vector(2 downto 0); -- export
alu_negative_export : in std_logic := 'X'; -- export
alu_out_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
alu_overflow_export : in std_logic := 'X'; -- export
alu_zero_export : in std_logic := 'X'; -- export
clk_clk : in std_logic := 'X'; -- clk
hex_0_export : out std_logic_vector(3 downto 0); -- export
hex_1_export : out std_logic_vector(3 downto 0); -- export
hex_2_export : out std_logic_vector(3 downto 0); -- export
hex_3_export : out std_logic_vector(3 downto 0); -- export
hex_4_export : out std_logic_vector(3 downto 0); -- export
hex_5_export : out std_logic_vector(3 downto 0); -- export
leds_export : out std_logic_vector(9 downto 0); -- export
regfile_data_export : out std_logic_vector(31 downto 0); -- export
regfile_r1sel_export : out std_logic_vector(5 downto 0); -- export
regfile_r2sel_export : out std_logic_vector(5 downto 0); -- export
regfile_reg1_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
regfile_reg2_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
regfile_we_export : out std_logic; -- export
regfile_wsel_export : out std_logic_vector(5 downto 0); -- export
reset_reset_n : in std_logic := 'X'; -- reset_n
sram_addr_export : out std_logic_vector(10 downto 0); -- export
sram_cs_export : out std_logic; -- export
sram_data_in_export : inout std_logic_vector(15 downto 0) := (others => 'X'); -- export
sram_oe_export : out std_logic; -- export
sram_read_write_export : out std_logic; -- export
switches_export : in std_logic_vector(9 downto 0) := (others => 'X'); -- export
keys_export : in std_logic_vector(3 downto 0) := (others => 'X') -- export
);
end component nios_system;
u0 : component nios_system
port map (
alu_a_export => CONNECTED_TO_alu_a_export, -- alu_a.export
alu_b_export => CONNECTED_TO_alu_b_export, -- alu_b.export
alu_carry_out_export => CONNECTED_TO_alu_carry_out_export, -- alu_carry_out.export
alu_control_export => CONNECTED_TO_alu_control_export, -- alu_control.export
alu_negative_export => CONNECTED_TO_alu_negative_export, -- alu_negative.export
alu_out_export => CONNECTED_TO_alu_out_export, -- alu_out.export
alu_overflow_export => CONNECTED_TO_alu_overflow_export, -- alu_overflow.export
alu_zero_export => CONNECTED_TO_alu_zero_export, -- alu_zero.export
clk_clk => CONNECTED_TO_clk_clk, -- clk.clk
hex_0_export => CONNECTED_TO_hex_0_export, -- hex_0.export
hex_1_export => CONNECTED_TO_hex_1_export, -- hex_1.export
hex_2_export => CONNECTED_TO_hex_2_export, -- hex_2.export
hex_3_export => CONNECTED_TO_hex_3_export, -- hex_3.export
hex_4_export => CONNECTED_TO_hex_4_export, -- hex_4.export
hex_5_export => CONNECTED_TO_hex_5_export, -- hex_5.export
leds_export => CONNECTED_TO_leds_export, -- leds.export
regfile_data_export => CONNECTED_TO_regfile_data_export, -- regfile_data.export
regfile_r1sel_export => CONNECTED_TO_regfile_r1sel_export, -- regfile_r1sel.export
regfile_r2sel_export => CONNECTED_TO_regfile_r2sel_export, -- regfile_r2sel.export
regfile_reg1_export => CONNECTED_TO_regfile_reg1_export, -- regfile_reg1.export
regfile_reg2_export => CONNECTED_TO_regfile_reg2_export, -- regfile_reg2.export
regfile_we_export => CONNECTED_TO_regfile_we_export, -- regfile_we.export
regfile_wsel_export => CONNECTED_TO_regfile_wsel_export, -- regfile_wsel.export
reset_reset_n => CONNECTED_TO_reset_reset_n, -- reset.reset_n
sram_addr_export => CONNECTED_TO_sram_addr_export, -- sram_addr.export
sram_cs_export => CONNECTED_TO_sram_cs_export, -- sram_cs.export
sram_data_in_export => CONNECTED_TO_sram_data_in_export, -- sram_data_in.export
sram_oe_export => CONNECTED_TO_sram_oe_export, -- sram_oe.export
sram_read_write_export => CONNECTED_TO_sram_read_write_export, -- sram_read_write.export
switches_export => CONNECTED_TO_switches_export, -- switches.export
keys_export => CONNECTED_TO_keys_export -- keys.export
);
| gpl-3.0 | 9c739ee21aabf43dffa5fb4294f14b08 | 0.499915 | 3.598165 | false | false | false | false |
jakubcabal/uart-for-fpga | rtl/comp/uart_parity.vhd | 2 | 2,007 | --------------------------------------------------------------------------------
-- PROJECT: SIMPLE UART FOR FPGA
--------------------------------------------------------------------------------
-- AUTHORS: Jakub Cabal <[email protected]>
-- LICENSE: The MIT License, please read LICENSE file
-- WEBSITE: https://github.com/jakubcabal/uart-for-fpga
--------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity UART_PARITY is
Generic (
DATA_WIDTH : integer := 8;
PARITY_TYPE : string := "none" -- legal values: "none", "even", "odd", "mark", "space"
);
Port (
DATA_IN : in std_logic_vector(DATA_WIDTH-1 downto 0);
PARITY_OUT : out std_logic
);
end entity;
architecture RTL of UART_PARITY is
begin
-- -------------------------------------------------------------------------
-- PARITY BIT GENERATOR
-- -------------------------------------------------------------------------
even_parity_g : if (PARITY_TYPE = "even") generate
process (DATA_IN)
variable parity_temp : std_logic;
begin
parity_temp := '0';
for i in DATA_IN'range loop
parity_temp := parity_temp XOR DATA_IN(i);
end loop;
PARITY_OUT <= parity_temp;
end process;
end generate;
odd_parity_g : if (PARITY_TYPE = "odd") generate
process (DATA_IN)
variable parity_temp : std_logic;
begin
parity_temp := '1';
for i in DATA_IN'range loop
parity_temp := parity_temp XOR DATA_IN(i);
end loop;
PARITY_OUT <= parity_temp;
end process;
end generate;
mark_parity_g : if (PARITY_TYPE = "mark") generate
PARITY_OUT <= '1';
end generate;
space_parity_g : if (PARITY_TYPE = "space") generate
PARITY_OUT <= '0';
end generate;
end architecture;
| mit | e55fc48f4fb2907b2c78615904a505e4 | 0.455904 | 4.52027 | false | false | false | false |
elionne/easy_bitcoin_wallet | testbench_pw_string.vhdl | 1 | 5,734 |
library IEEE;
use IEEE.std_logic_1164.all;
entity testbench_pw_string is
end testbench_pw_string;
architecture testbench_arch_pw_string of testbench_pw_string is
signal clk : std_logic;
signal enable : std_logic;
signal push_pop : std_logic;
signal char : character;
signal pwd : string (1 to 5);
component pw_string
port (
char : in character;
pwd : out string;
enable: in std_logic;
push_pop : in std_logic;
clk : in std_logic
);
end component;
begin
final_string : pw_string port map (
char => char,
pwd => pwd,
enable => enable,
push_pop => push_pop,
clk => clk
);
process
begin
-- --------------------
clk <= transport '0';
push_pop <= transport '1';
enable <= transport '1';
char <= transport 'a';
-- --------------------
WAIT FOR 110 ns;
clk <= transport '1';
-- --------------------
WAIT FOR 10 ns;
clk <= transport '0';
-- --------------------
WAIT FOR 10 ns;
assert pwd(1) = 'a';
clk <= transport '1';
-- --------------------
WAIT FOR 10 ns;
clk <= transport '0';
-- --------------------
WAIT FOR 10 ns;
clk <= transport '1';
assert pwd(2) = 'a';
-- --------------------
WAIT FOR 10 ns;
clk <= transport '0';
char <= transport 'b';
-- --------------------
WAIT FOR 10 ns;
clk <= transport '1';
assert pwd(3) = 'b';
enable <= transport '0';
-- --------------------
WAIT FOR 10 ns;
clk <= transport '0';
-- --------------------
WAIT FOR 10 ns;
clk <= transport '1';
-- --------------------
WAIT FOR 10 ns;
clk <= transport '0';
char <= transport 'c';
-- --------------------
WAIT FOR 10 ns;
clk <= transport '1';
assert pwd(3) = 'b';
assert pwd(4) = nul;
-- --------------------
WAIT FOR 10 ns;
clk <= transport '0';
char <= transport 'd';
-- --------------------
WAIT FOR 10 ns;
clk <= transport '1';
-- --------------------
WAIT FOR 10 ns;
clk <= transport '0';
-- --------------------
WAIT FOR 10 ns;
clk <= transport '1';
enable <= transport '1';
-- --------------------
WAIT FOR 10 ns;
clk <= transport '0';
-- --------------------
WAIT FOR 10 ns;
clk <= transport '1';
assert pwd(4) = 'd' ;
-- --------------------
WAIT FOR 10 ns;
clk <= transport '0';
char <= transport 'e';
-- --------------------
WAIT FOR 10 ns;
clk <= transport '1';
assert pwd(5) = 'e' ;
push_pop <= transport '0';
-- --------------------
WAIT FOR 10 ns;
clk <= transport '0';
char <= transport 'f';
-- --------------------
WAIT FOR 10 ns;
clk <= transport '1';
assert pwd(5) = nul ;
-- --------------------
WAIT FOR 10 ns;
clk <= transport '0';
char <= transport 'g';
-- --------------------
WAIT FOR 10 ns;
clk <= transport '1';
-- --------------------
WAIT FOR 10 ns;
clk <= transport '0';
-- --------------------
WAIT FOR 10 ns;
clk <= transport '1';
-- --------------------
WAIT FOR 10 ns;
clk <= transport '0';
-- --------------------
WAIT FOR 10 ns;
clk <= transport '1';
char <= transport 'h';
-- --------------------
WAIT FOR 10 ns;
clk <= transport '0';
-- --------------------
WAIT FOR 10 ns;
clk <= transport '1';
-- --------------------
WAIT FOR 10 ns;
clk <= transport '0';
char <= transport 'i';
-- --------------------
WAIT FOR 10 ns;
clk <= transport '1';
assert pwd(1) = nul ;
-- --------------------
WAIT FOR 10 ns;
clk <= transport '0';
-- --------------------
WAIT FOR 10 ns;
clk <= transport '1';
push_pop <= transport '1';
char <= transport 'j';
-- --------------------
WAIT FOR 10 ns;
clk <= transport '0';
-- --------------------
WAIT FOR 10 ns;
clk <= transport '1';
assert pwd(1) = 'j' ;
char <= transport 'k';
-- --------------------
WAIT FOR 10 ns;
clk <= transport '0';
-- --------------------
WAIT FOR 10 ns;
clk <= transport '1';
char <= transport 'l';
-- --------------------
WAIT FOR 10 ns;
clk <= transport '0';
-- --------------------
WAIT FOR 10 ns;
clk <= transport '1';
char <= transport 'm';
-- --------------------
WAIT FOR 10 ns;
clk <= transport '0';
-- --------------------
WAIT FOR 10 ns;
clk <= transport '1';
-- --------------------
WAIT FOR 10 ns;
clk <= transport '0';
-- --------------------
WAIT FOR 10 ns;
clk <= transport '1';
-- --------------------
WAIT FOR 10 ns;
clk <= transport '0';
-- --------------------
WAIT FOR 10 ns;
clk <= transport '1';
-- --------------------
WAIT FOR 10 ns;
clk <= transport '0';
-- --------------------
WAIT;
end process;
end testbench_arch_pw_string;
| mit | 984d4c4fbed715a9d0668a671ea86906 | 0.344611 | 4.758506 | false | false | false | false |
besm6/micro-besm | tests/2901/vhdl/funct_blocks_alg_beh/components/alu/alu.vhdl | 1 | 3,228 | --------------------------------------------------------------------------------
--
-- AM2901 Benchmark
--
-- Source: AMD data book
--
-- VHDL Benchmark author Indraneel Ghosh
-- University Of California, Irvine, CA 92717
--
-- Developed on Jan 1, 1992
--
-- Verification Information:
--
-- Verified By whom? Date Simulator
-- -------- ------------ -------- ------------
-- Syntax yes Champaka Ramachandran Sept 17, 92 ZYCAD
-- Functionality yes Champaka Ramachandran Sept 17, 92 ZYCAD
--------------------------------------------------------------------------------
--library ZYCAD;
use work.TYPES.all;
use work.MVL7_functions.all;
entity alu is
port (
RE, S : in MVL7_vector(3 downto 0);
I : in MVL7_vector(8 downto 0);
C0 : in MVL7;
C4, OVR, F30, F3, Pbar, Gbar : out MVL7;
F : out MVL7_vector(3 downto 0)
);
end alu;
architecture alu of alu is
signal R_ext,S_ext,result,temp_p,temp_g : MVL7_vector(4 downto 0);
begin
-- TO FACILITATE COMPUTATION OF CARRY-OUT "C4", WE EXTEND THE CHOSEN
-- ALU OPERANDS "RE" AND "S" (4 BIT OPERANDS) BY 1 BIT IN THE MSB POSITION.
-- THUS THE EXTENDED OPERANDS "R_EXT" AND "S_EXT" (5 BIT OPERANDS) ARE
-- FORMED AND ARE USED IN THE ALU OPERATION. THE EXTRA BIT IS SET TO '0'
-- INITIALLY. THE ALU'S EXTENDED OUTPUT ( 5 BITS LONG) IS "result".
R_ext <= '0' & not(RE) when I(5 downto 3) = "001" else
'0' & RE;
S_ext <= '0' & not(S) when I(5 downto 3) = "010" else
'0' & S;
-- SELECT THE FUNCTION FOR ALU.
-- IN THE ADD/SUBTRACT OPERATIONS, THE CARRY-INPUT "C0" (1 BIT) IS EXTENDED
-- BY 4 BITS ( ALL '0') IN THE MORE SIGNIFICANT BITS TO MATCH ITS LENGTH TO
-- THAT OF "R_ext" AND "S_ext". THEN, THESE THREE OPERANDS ARE ADDED.
-- ADD/SUBTRACT OPERATIONS ARE DONE ON 2'S COMPLEMENT OPERANDS.
with I(5 downto 3) select
result <= R_ext + S_ext + ("0000" & C0) when "000" | "001" | "010",
R_ext or S_ext when "011",
R_ext and S_ext when "100",
not(R_ext) and S_ext when "101",
R_ext xor S_ext when "110",
not( R_ext xor S_ext) when others;
-- EVALUATE OTHER ALU OUTPUTS.
-- FROM EXTENDED OUTPUT "result" ( 5 BITS), WE OBTAIN THE NORMAL ALU OUTPUT,
-- "F" (4 BITS) BY LEAVING OUT THE MSB ( WHICH CORRESPONDS TO CARRY-OUT
-- "C4").
-- TO FACILITATE COMPUTATION OF CARRY LOOKAHEAD TERMS "Pbar" AND "Gbar", WE
-- COMPUTE INTERMEDIATE TERMS "temp_p" AND "temp_g".
F <= result(3 downto 0);
OVR <= not (R_ext(3) xor S_ext(3)) and
( R_ext(3) xor result(3) );
C4 <= result(4);
temp_p <= R_ext or S_ext; -- R or S may get
temp_g <= R_ext and S_ext; -- inverted (sub)
Pbar <= not(temp_p(0) and temp_p(1) and temp_p(2) and temp_p(3));
Gbar <= not( temp_g(3) or
(temp_p(3) and temp_g(2)) or
(temp_p(3) and temp_p(2) and temp_g(1)) or
(temp_p(3) and temp_p(2) and temp_p(1) and temp_g(0))
);
F3 <= result(3);
F30 <= not(result(3) or result(2) or result(1) or result(0));
end alu;
------------------------------
| mit | 3c38123e850c8e97a4a5d9218c4f58d6 | 0.533147 | 3.094919 | false | false | false | false |
kuba-moo/VHDL-lib | uart_rx.vhd | 2 | 4,036 | -- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>
--
-- Copyright (C) 2014 Jakub Kicinski <[email protected]>
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_ARITH.all;
use IEEE.STD_LOGIC_UNSIGNED.all;
use work.globals.all;
-- UART receive
entity uart_rx is
generic (FREQUENCY : integer);
port (Clk : in std_logic;
Rst : in std_logic;
RsRx : in std_logic;
Byte : out byte_t;
Valid : out std_logic);
end uart_rx;
-- Operation:
-- When @RsRx goes down start counting bit time, sample on half of bit time.
-- To rule out spurious starts wait for @RsRx to go low for a few cycles.
architecture Behavioral of uart_rx is
constant CLK_MAX : integer := FPGA_CLK_FREQ/FREQUENCY;
constant CLK_SAMPLE : integer := CLK_MAX/2;
type a2_byte is array(1 downto 0) of byte_t;
type state_t is (IDLE, START, RX, STOP);
signal bit_no, NEXT_bit_no : integer range 0 to 8;
signal value, NEXT_value : byte_t;
signal cnt, NEXT_cnt : integer range 0 to CLK_MAX;
signal state, NEXT_state : state_t;
signal rx_d : std_logic_vector(1 downto 0);
begin
Byte <= value;
rx_d(0) <= RsRx when rising_edge(Clk);
rx_d(1) <= rx_d(0) when rising_edge(Clk);
NEXT_fsm : process (state, cnt, value, bit_no, rx_d(1))
begin
NEXT_state <= state;
NEXT_cnt <= cnt + 1;
NEXT_value <= value;
NEXT_bit_no <= bit_no;
Valid <= '0';
case state is
when IDLE =>
if rx_d(1) = '0' then -- waiting for a stable low input will
-- offset the sampling time by 8, but it
-- should be ok for UART rates
NEXT_bit_no <= bit_no + 1;
if CONV_std_logic_vector(bit_no, 4)(3) = '1' then
NEXT_state <= START;
NEXT_cnt <= 0;
end if;
else
NEXT_bit_no <= 0;
end if;
when START =>
if cnt = CLK_MAX then
NEXT_state <= RX;
NEXT_cnt <= 0;
NEXT_bit_no <= 0;
end if;
when RX =>
if CONV_std_logic_vector(bit_no, 4)(3) = '1' then
NEXT_state <= STOP;
Valid <= '1';
end if;
if cnt = CLK_SAMPLE then
NEXT_value(bit_no) <= rx_d(1);
end if;
if cnt = CLK_MAX then
NEXT_state <= RX;
NEXT_cnt <= 0;
NEXT_bit_no <= bit_no + 1;
end if;
when STOP =>
if cnt = CLK_SAMPLE then -- go to IDLE early, if we wait full
-- bit time, delays from IDLE might
-- accumulate
NEXT_state <= IDLE;
end if;
end case;
end process;
fsm : process (Clk)
begin
if rising_edge(Clk) then
state <= NEXT_state;
cnt <= NEXT_cnt;
value <= NEXT_value;
bit_no <= NEXT_bit_no;
if Rst = '1' then
state <= IDLE;
end if;
end if;
end process;
end Behavioral;
| gpl-3.0 | 1cc63f683cc479c28db3dfacc7e66113 | 0.50446 | 4 | false | false | false | false |
natsutan/NPU | fpga_implement/npu8/npu8.srcs/sources_1/ip/mul8_16/synth/mul8_16.vhd | 1 | 5,655 | -- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:mult_gen:12.0
-- IP Revision: 12
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY mult_gen_v12_0_12;
USE mult_gen_v12_0_12.mult_gen_v12_0_12;
ENTITY mul8_16 IS
PORT (
CLK : IN STD_LOGIC;
A : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
B : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
P : OUT STD_LOGIC_VECTOR(15 DOWNTO 0)
);
END mul8_16;
ARCHITECTURE mul8_16_arch OF mul8_16 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF mul8_16_arch: ARCHITECTURE IS "yes";
COMPONENT mult_gen_v12_0_12 IS
GENERIC (
C_VERBOSITY : INTEGER;
C_MODEL_TYPE : INTEGER;
C_OPTIMIZE_GOAL : INTEGER;
C_XDEVICEFAMILY : STRING;
C_HAS_CE : INTEGER;
C_HAS_SCLR : INTEGER;
C_LATENCY : INTEGER;
C_A_WIDTH : INTEGER;
C_A_TYPE : INTEGER;
C_B_WIDTH : INTEGER;
C_B_TYPE : INTEGER;
C_OUT_HIGH : INTEGER;
C_OUT_LOW : INTEGER;
C_MULT_TYPE : INTEGER;
C_CE_OVERRIDES_SCLR : INTEGER;
C_CCM_IMP : INTEGER;
C_B_VALUE : STRING;
C_HAS_ZERO_DETECT : INTEGER;
C_ROUND_OUTPUT : INTEGER;
C_ROUND_PT : INTEGER
);
PORT (
CLK : IN STD_LOGIC;
A : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
B : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
CE : IN STD_LOGIC;
SCLR : IN STD_LOGIC;
P : OUT STD_LOGIC_VECTOR(15 DOWNTO 0)
);
END COMPONENT mult_gen_v12_0_12;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF mul8_16_arch: ARCHITECTURE IS "mult_gen_v12_0_12,Vivado 2016.4";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF mul8_16_arch : ARCHITECTURE IS "mul8_16,mult_gen_v12_0_12,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF mul8_16_arch: ARCHITECTURE IS "mul8_16,mult_gen_v12_0_12,{x_ipProduct=Vivado 2016.4,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=mult_gen,x_ipVersion=12.0,x_ipCoreRevision=12,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_VERBOSITY=0,C_MODEL_TYPE=0,C_OPTIMIZE_GOAL=1,C_XDEVICEFAMILY=kintexu,C_HAS_CE=0,C_HAS_SCLR=0,C_LATENCY=3,C_A_WIDTH=8,C_A_TYPE=1,C_B_WIDTH=16,C_B_TYPE=1,C_OUT_HIGH=23,C_OUT_LOW=8,C_MULT_TYPE=0,C_CE_OVERRIDES_SCLR=0,C_CCM_IMP=0,C_B_VALUE=10000001,C_HAS_ZERO_DETECT=0,C_ROUND_OUTPUT=0,C_ROUND_PT=0}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF CLK: SIGNAL IS "xilinx.com:signal:clock:1.0 clk_intf CLK";
ATTRIBUTE X_INTERFACE_INFO OF A: SIGNAL IS "xilinx.com:signal:data:1.0 a_intf DATA";
ATTRIBUTE X_INTERFACE_INFO OF B: SIGNAL IS "xilinx.com:signal:data:1.0 b_intf DATA";
ATTRIBUTE X_INTERFACE_INFO OF P: SIGNAL IS "xilinx.com:signal:data:1.0 p_intf DATA";
BEGIN
U0 : mult_gen_v12_0_12
GENERIC MAP (
C_VERBOSITY => 0,
C_MODEL_TYPE => 0,
C_OPTIMIZE_GOAL => 1,
C_XDEVICEFAMILY => "kintexu",
C_HAS_CE => 0,
C_HAS_SCLR => 0,
C_LATENCY => 3,
C_A_WIDTH => 8,
C_A_TYPE => 1,
C_B_WIDTH => 16,
C_B_TYPE => 1,
C_OUT_HIGH => 23,
C_OUT_LOW => 8,
C_MULT_TYPE => 0,
C_CE_OVERRIDES_SCLR => 0,
C_CCM_IMP => 0,
C_B_VALUE => "10000001",
C_HAS_ZERO_DETECT => 0,
C_ROUND_OUTPUT => 0,
C_ROUND_PT => 0
)
PORT MAP (
CLK => CLK,
A => A,
B => B,
CE => '1',
SCLR => '0',
P => P
);
END mul8_16_arch;
| bsd-3-clause | e10146437879e6943fe878b637f899ef | 0.678338 | 3.348135 | false | false | false | false |
varunnagpaal/Digital-Hardware-Modelling | vhdl/filter/iir/bq/filter_datapath.vhdl | 1 | 7,740 | library IEEE;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.all;
use work.filter_shared_package.all;
entity filter_datapath is
generic
(
FPMULT_PIPE_LENGTH : P_T := PM;
FPADD_PIPE_LENGTH : P_T := PA;
PRECISION : natural := PREC;
ENVELOPE_EN : natural := ENV;
SETZERO_EN : natural := SETZ
);
port
(
-- Input ports
clk : in std_logic;
rstn : in std_logic;
aclr : in std_logic;
x_rdaddr : in X_ADD_T;
x_rden : in std_logic;
x_wraddr : in X_ADD_T;
x_wren : in std_logic;
sink_data : in std_logic_vector(SINGLE_EXT-1 downto 0);
coeff_rdaddr : in COEFF_ADD_T;
coeff_rden : in std_logic;
coeff_wraddr : in COEFF_ADD_T;
coeff_wren : in std_logic;
coeff_data : in DATA_IO_PORT_T;
acc_rdaddr : in ACC_ADD_T;
acc_rden : in std_logic;
acc_wraddr : in ACC_ADD_T;
acc_wren : in std_logic;
zero_acc : in std_logic;
y_rdaddr : in Y_ADD_T;
y_rden : in std_logic;
y_wraddr : in Y_ADD_T;
y_wren : in std_logic;
zero_y : in std_logic;
is_abs : in std_logic;
mac_x_y_sel : in std_logic;
mac_coeff_y_sel : in std_logic;
-- Output ports
source_data : out std_logic_vector(SINGLE_EXT-1 downto 0)
);
end filter_datapath;
architecture filter_datapath_arch of filter_datapath is
signal mac_x_in_s : DATA_IO_PORT_T;
signal mac_y_in_s : DATA_IO_PORT_T;
signal mac_r_out_s : DATA_IO_PORT_T;
signal x_data_out_s : DATA_IO_PORT_T;
signal y_data_in_s, y_data_out_s : DATA_IO_PORT_T;
signal acc_data_in_s, acc_data_out_s : DATA_IO_PORT_T;
signal coeff_data_out_s : DATA_IO_PORT_T;
signal mac_r_reg_s : DATA_IO_PORT_T;
signal mac_r_float_data_out_s : std_logic_vector(SINGLE_EXT-1 downto 0);
signal datapath_out_reg_s : std_logic_vector(SINGLE_EXT-1 downto 0);
signal sign_s : std_logic_vector(0 downto 0);
begin
-- Filter Datapath Components
filter_in_data_memory_inst : entity work.filter_in_data_memory
generic map
(
PRECISION => PRECISION
)
port map
(
clk => clk,
aclr => aclr,
x_data_in => sink_data,
x_rdaddr => x_rdaddr,
x_rden => x_rden,
x_wraddr => x_wraddr,
x_wren => x_wren,
x_data_out => x_data_out_s
);
filter_out_data_memory_inst : entity work.device_ram_blocks
generic map
(
INTENDED_DEVICE_FAMILY => "SmartFusion",
WIDTH_AD => y_rdaddr'length, -- WIDTH_RDAD = WIDTH_WRAD
WIDTH_DATA => y_data_in_s'length, -- WIDTH_DATAIN = WIDTH_DATAOUT
OUP_REG => "UNREGISTERED" -- "UNREGISTERED" or "CLOCK0"
)
port map
(
clock => clk,
aclr => aclr,
rden => y_rden,
rdaddress => y_rdaddr,
data_in => y_data_in_s,
wren => y_wren,
wraddress => y_wraddr,
data_out => y_data_out_s
);
filter_mac_mem_inst : entity work.device_ram_blocks
generic map
(
INTENDED_DEVICE_FAMILY => "SmartFusion",
WIDTH_AD => acc_rdaddr'length, -- WIDTH_RDAD = WIDTH_WRAD
WIDTH_DATA => acc_data_in_s'length, -- WIDTH_DATAIN = WIDTH_DATAOUT
OUP_REG => "CLOCK0" -- "UNREGISTERED" or "CLOCK0"
)
port map
(
clock => clk,
aclr => aclr,
rdaddress => acc_rdaddr,
rden => acc_rden,
data_in => acc_data_in_s,
wren => acc_wren,
wraddress => acc_wraddr,
data_out => acc_data_out_s
);
filter_coeff_mem_inst : entity work.device_ram_blocks
generic map
(
INTENDED_DEVICE_FAMILY => "SmartFusion",
WIDTH_AD => coeff_rdaddr'length, -- WIDTH_RDAD = WIDTH_WRAD
WIDTH_DATA => coeff_data'length, -- WIDTH_DATAIN = WIDTH_DATAOUT
OUP_REG => "UNREGISTERED" -- "UNREGISTERED" or "CLOCK0"
)
port map
(
clock => clk,
aclr => aclr,
rden => coeff_rden,
rdaddress => coeff_rdaddr,
data_in => coeff_data,
wren => coeff_wren,
wraddress => coeff_wraddr,
data_out => coeff_data_out_s
);
filter_mac_datapath_inst : entity work.filter_mac_datapath
generic map
(
FPMULT_PIPE_LENGTH => FPMULT_PIPE_LENGTH,
FPADD_PIPE_LENGTH => FPADD_PIPE_LENGTH
)
port map
(
clk => clk,
rst => rstn,
X => mac_x_in_s,
Y => mac_y_in_s,
A => acc_data_out_s,
R => mac_r_out_s
);
-- register the mac output
filter_mac_datapath_reg : process(clk, rstn)
begin
if(rstn = '0') then
mac_r_reg_s <= (others => '0');
elsif(rising_edge(clk)) then
mac_r_reg_s <= mac_r_out_s;
end if;
end process filter_mac_datapath_reg;
-- convert mac output to float type if required
mac_sgl : if PRECISION = SINGLE_EXT generate
mac_r_float_data_out_s <= mac_r_reg_s;
end generate;
mac_dbl: if PRECISION = DOUBLE_EXT generate
D2F : entity work.filter_converter_dp2sp
port map(double => mac_r_reg_s, float => mac_r_float_data_out_s);
end generate;
-- register this mac output
datapath_reg : process(clk, rstn)
begin
if(rstn = '0') then
datapath_out_reg_s <= (others => '0');
elsif(rising_edge(clk)) then
datapath_out_reg_s <= mac_r_float_data_out_s;
end if;
end process datapath_reg;
-- connect mac output to datapath output port
source_data <= datapath_out_reg_s;
-- Select Y input of MAC from x or y memory
env_en: if ENVELOPE_EN /= 0 generate
sign_s(0) <= y_data_out_s(PRECISION-3) and not is_abs;
with mac_x_y_sel select
mac_y_in_s <= x_data_out_s when '1',
y_data_out_s(PRECISION-1 downto PRECISION-2) & sign_s & y_data_out_s(PRECISION-4 downto 0) when others;
end generate;
env_dis: if ENVELOPE_EN = 0 generate
with mac_x_y_sel select
mac_y_in_s <= x_data_out_s when '1',
y_data_out_s when others;
end generate;
-- Select X input of MAC from coeff or y memory
with mac_coeff_y_sel select
mac_x_in_s <=
coeff_data_out_s when '1',
y_data_out_s when others;
-- Sending zeros to Y-memory
setz_en: if SETZERO_EN /= 0 generate
with zero_y select
y_data_in_s <=
mac_r_out_s when '0',
(others => '0') when others;
end generate;
setz_dis: if SETZERO_EN = 0 generate
y_data_in_s <= mac_r_out_s;
end generate;
-- Sending zeros to Acc-memory
with zero_acc select
acc_data_in_s <=
mac_r_out_s when '0',
(others => '0') when others;
end filter_datapath_arch;
| mit | 1519c7eba82bb65af83723419e4f187e | 0.493798 | 3.513391 | false | false | false | false |
jakubcabal/uart-for-fpga | rtl/comp/uart_tx.vhd | 2 | 8,375 | --------------------------------------------------------------------------------
-- PROJECT: SIMPLE UART FOR FPGA
--------------------------------------------------------------------------------
-- AUTHORS: Jakub Cabal <[email protected]>
-- LICENSE: The MIT License, please read LICENSE file
-- WEBSITE: https://github.com/jakubcabal/uart-for-fpga
--------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity UART_TX is
Generic (
CLK_DIV_VAL : integer := 16;
PARITY_BIT : string := "none" -- type of parity: "none", "even", "odd", "mark", "space"
);
Port (
CLK : in std_logic; -- system clock
RST : in std_logic; -- high active synchronous reset
-- UART INTERFACE
UART_CLK_EN : in std_logic; -- oversampling (16x) UART clock enable
UART_TXD : out std_logic; -- serial transmit data
-- USER DATA INPUT INTERFACE
DIN : in std_logic_vector(7 downto 0); -- input data to be transmitted over UART
DIN_VLD : in std_logic; -- when DIN_VLD = 1, input data (DIN) are valid
DIN_RDY : out std_logic -- when DIN_RDY = 1, transmitter is ready and valid input data will be accepted for transmiting
);
end entity;
architecture RTL of UART_TX is
signal tx_clk_en : std_logic;
signal tx_clk_div_clr : std_logic;
signal tx_data : std_logic_vector(7 downto 0);
signal tx_bit_count : unsigned(2 downto 0);
signal tx_bit_count_en : std_logic;
signal tx_ready : std_logic;
signal tx_parity_bit : std_logic;
signal tx_data_out_sel : std_logic_vector(1 downto 0);
type state is (idle, txsync, startbit, databits, paritybit, stopbit);
signal tx_pstate : state;
signal tx_nstate : state;
begin
DIN_RDY <= tx_ready;
-- -------------------------------------------------------------------------
-- UART TRANSMITTER CLOCK DIVIDER AND CLOCK ENABLE FLAG
-- -------------------------------------------------------------------------
tx_clk_divider_i : entity work.UART_CLK_DIV
generic map(
DIV_MAX_VAL => CLK_DIV_VAL,
DIV_MARK_POS => 1
)
port map (
CLK => CLK,
RST => RST,
CLEAR => tx_clk_div_clr,
ENABLE => UART_CLK_EN,
DIV_MARK => tx_clk_en
);
-- -------------------------------------------------------------------------
-- UART TRANSMITTER INPUT DATA REGISTER
-- -------------------------------------------------------------------------
uart_tx_input_data_reg_p : process (CLK)
begin
if (rising_edge(CLK)) then
if (DIN_VLD = '1' AND tx_ready = '1') then
tx_data <= DIN;
end if;
end if;
end process;
-- -------------------------------------------------------------------------
-- UART TRANSMITTER BIT COUNTER
-- -------------------------------------------------------------------------
uart_tx_bit_counter_p : process (CLK)
begin
if (rising_edge(CLK)) then
if (RST = '1') then
tx_bit_count <= (others => '0');
elsif (tx_bit_count_en = '1' AND tx_clk_en = '1') then
if (tx_bit_count = "111") then
tx_bit_count <= (others => '0');
else
tx_bit_count <= tx_bit_count + 1;
end if;
end if;
end if;
end process;
-- -------------------------------------------------------------------------
-- UART TRANSMITTER PARITY GENERATOR
-- -------------------------------------------------------------------------
uart_tx_parity_g : if (PARITY_BIT /= "none") generate
uart_tx_parity_gen_i: entity work.UART_PARITY
generic map (
DATA_WIDTH => 8,
PARITY_TYPE => PARITY_BIT
)
port map (
DATA_IN => tx_data,
PARITY_OUT => tx_parity_bit
);
end generate;
uart_tx_noparity_g : if (PARITY_BIT = "none") generate
tx_parity_bit <= '0';
end generate;
-- -------------------------------------------------------------------------
-- UART TRANSMITTER OUTPUT DATA REGISTER
-- -------------------------------------------------------------------------
uart_tx_output_data_reg_p : process (CLK)
begin
if (rising_edge(CLK)) then
if (RST = '1') then
UART_TXD <= '1';
else
case tx_data_out_sel is
when "01" => -- START BIT
UART_TXD <= '0';
when "10" => -- DATA BITS
UART_TXD <= tx_data(to_integer(tx_bit_count));
when "11" => -- PARITY BIT
UART_TXD <= tx_parity_bit;
when others => -- STOP BIT OR IDLE
UART_TXD <= '1';
end case;
end if;
end if;
end process;
-- -------------------------------------------------------------------------
-- UART TRANSMITTER FSM
-- -------------------------------------------------------------------------
-- PRESENT STATE REGISTER
process (CLK)
begin
if (rising_edge(CLK)) then
if (RST = '1') then
tx_pstate <= idle;
else
tx_pstate <= tx_nstate;
end if;
end if;
end process;
-- NEXT STATE AND OUTPUTS LOGIC
process (tx_pstate, DIN_VLD, tx_clk_en, tx_bit_count)
begin
case tx_pstate is
when idle =>
tx_ready <= '1';
tx_data_out_sel <= "00";
tx_bit_count_en <= '0';
tx_clk_div_clr <= '1';
if (DIN_VLD = '1') then
tx_nstate <= txsync;
else
tx_nstate <= idle;
end if;
when txsync =>
tx_ready <= '0';
tx_data_out_sel <= "00";
tx_bit_count_en <= '0';
tx_clk_div_clr <= '0';
if (tx_clk_en = '1') then
tx_nstate <= startbit;
else
tx_nstate <= txsync;
end if;
when startbit =>
tx_ready <= '0';
tx_data_out_sel <= "01";
tx_bit_count_en <= '0';
tx_clk_div_clr <= '0';
if (tx_clk_en = '1') then
tx_nstate <= databits;
else
tx_nstate <= startbit;
end if;
when databits =>
tx_ready <= '0';
tx_data_out_sel <= "10";
tx_bit_count_en <= '1';
tx_clk_div_clr <= '0';
if ((tx_clk_en = '1') AND (tx_bit_count = "111")) then
if (PARITY_BIT = "none") then
tx_nstate <= stopbit;
else
tx_nstate <= paritybit;
end if ;
else
tx_nstate <= databits;
end if;
when paritybit =>
tx_ready <= '0';
tx_data_out_sel <= "11";
tx_bit_count_en <= '0';
tx_clk_div_clr <= '0';
if (tx_clk_en = '1') then
tx_nstate <= stopbit;
else
tx_nstate <= paritybit;
end if;
when stopbit =>
tx_ready <= '1';
tx_data_out_sel <= "00";
tx_bit_count_en <= '0';
tx_clk_div_clr <= '0';
if (DIN_VLD = '1') then
tx_nstate <= txsync;
elsif (tx_clk_en = '1') then
tx_nstate <= idle;
else
tx_nstate <= stopbit;
end if;
when others =>
tx_ready <= '0';
tx_data_out_sel <= "00";
tx_bit_count_en <= '0';
tx_clk_div_clr <= '0';
tx_nstate <= idle;
end case;
end process;
end architecture;
| mit | fef968742c64d83a942059a9a8bb5267 | 0.380299 | 4.574003 | false | false | false | false |
jakubcabal/uart-for-fpga | examples/uart2wb/uart2wbm.vhd | 2 | 9,087 | --------------------------------------------------------------------------------
-- PROJECT: SIMPLE UART FOR FPGA
--------------------------------------------------------------------------------
-- AUTHORS: Jakub Cabal <[email protected]>
-- LICENSE: The MIT License, please read LICENSE file
-- WEBSITE: https://github.com/jakubcabal/uart-for-fpga
--------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity UART2WBM is
Generic (
CLK_FREQ : integer := 50e6; -- system clock frequency in Hz
BAUD_RATE : integer := 115200 -- baud rate value
);
Port (
-- CLOCK AND RESET
CLK : in std_logic;
RST : in std_logic;
-- UART INTERFACE
UART_TXD : out std_logic;
UART_RXD : in std_logic;
-- WISHBONE MASTER INTERFACE
WB_CYC : out std_logic;
WB_STB : out std_logic;
WB_WE : out std_logic;
WB_ADDR : out std_logic_vector(15 downto 0);
WB_DOUT : out std_logic_vector(31 downto 0);
WB_STALL : in std_logic;
WB_ACK : in std_logic;
WB_DIN : in std_logic_vector(31 downto 0)
);
end entity;
architecture RTL of UART2WBM is
type state is (cmd, addr_low, addr_high, dout0, dout1, dout2, dout3,
request, wait4ack, response, din0, din1, din2, din3);
signal fsm_pstate : state;
signal fsm_nstate : state;
signal cmd_reg : std_logic_vector(7 downto 0);
signal cmd_next : std_logic_vector(7 downto 0);
signal addr_reg : std_logic_vector(15 downto 0);
signal addr_next : std_logic_vector(15 downto 0);
signal dout_reg : std_logic_vector(31 downto 0);
signal dout_next : std_logic_vector(31 downto 0);
signal din_reg : std_logic_vector(31 downto 0);
signal uart_dout : std_logic_vector(7 downto 0);
signal uart_dout_vld : std_logic;
signal uart_din : std_logic_vector(7 downto 0);
signal uart_din_vld : std_logic;
signal uart_din_rdy : std_logic;
begin
process (CLK)
begin
if (rising_edge(CLK)) then
cmd_reg <= cmd_next;
addr_reg <= addr_next;
dout_reg <= dout_next;
end if;
end process;
WB_WE <= cmd_reg(0);
WB_ADDR <= addr_reg;
WB_DOUT <= dout_reg;
process (CLK)
begin
if (rising_edge(CLK)) then
if (WB_ACK = '1') then
din_reg <= WB_DIN;
end if;
end if;
end process;
-- -------------------------------------------------------------------------
-- FSM
-- -------------------------------------------------------------------------
process (CLK)
begin
if (rising_edge(CLK)) then
if (RST = '1') then
fsm_pstate <= cmd;
else
fsm_pstate <= fsm_nstate;
end if;
end if;
end process;
process (fsm_pstate, uart_dout, uart_dout_vld, cmd_reg, addr_reg, dout_reg,
WB_STALL, WB_ACK, uart_din_rdy, din_reg)
begin
fsm_nstate <= cmd;
cmd_next <= cmd_reg;
addr_next <= addr_reg;
dout_next <= dout_reg;
WB_STB <= '0';
WB_CYC <= '0';
uart_din <= cmd_reg;
uart_din_vld <= '0';
case fsm_pstate is
when cmd => -- idle and read request cmd from UART
cmd_next <= uart_dout;
if (uart_dout_vld = '1') then
fsm_nstate <= addr_low;
else
fsm_nstate <= cmd;
end if;
when addr_low => -- read low bits of address from UART
addr_next(7 downto 0) <= uart_dout;
if (uart_dout_vld = '1') then
fsm_nstate <= addr_high;
else
fsm_nstate <= addr_low;
end if;
when addr_high => -- read high bits of address from UART
addr_next(15 downto 8) <= uart_dout;
if (uart_dout_vld = '1') then
if (cmd_reg(0) = '1') then
fsm_nstate <= dout0; -- write cmd
else
fsm_nstate <= request; -- read cmd
end if;
else
fsm_nstate <= addr_high;
end if;
when dout0 => -- read data byte 0 from UART (write cmd only)
dout_next(7 downto 0) <= uart_dout;
if (uart_dout_vld = '1') then
fsm_nstate <= dout1;
else
fsm_nstate <= dout0;
end if;
when dout1 => -- read data byte 1 from UART (write cmd only)
dout_next(15 downto 8) <= uart_dout;
if (uart_dout_vld = '1') then
fsm_nstate <= dout2;
else
fsm_nstate <= dout1;
end if;
when dout2 => -- read data byte 2 from UART (write cmd only)
dout_next(23 downto 16) <= uart_dout;
if (uart_dout_vld = '1') then
fsm_nstate <= dout3;
else
fsm_nstate <= dout2;
end if;
when dout3 => -- read data byte 3 from UART (write cmd only)
dout_next(31 downto 24) <= uart_dout;
if (uart_dout_vld = '1') then
fsm_nstate <= request; -- write request
else
fsm_nstate <= dout3;
end if;
when request => -- send WR or RD request to Wishbone bus
WB_STB <= '1'; -- request is valid
WB_CYC <= '1';
if (WB_STALL = '0') then
fsm_nstate <= wait4ack;
else
fsm_nstate <= request;
end if;
when wait4ack => -- wait for ACK on Wishbone bus
WB_CYC <= '1';
if (WB_ACK = '1') then
fsm_nstate <= response;
else
fsm_nstate <= wait4ack;
end if;
when response => -- send response cmd to UART
uart_din <= cmd_reg;
uart_din_vld <= '1';
if (uart_din_rdy = '1') then
if (cmd_reg(0) = '1') then
fsm_nstate <= cmd; -- idle or new read request cmd (write cmd only)
else
fsm_nstate <= din0; -- send read data to UART (read cmd only)
end if;
else
fsm_nstate <= response;
end if;
when din0 => -- send read data byte 0 to UART (read cmd only)
uart_din <= din_reg(7 downto 0);
uart_din_vld <= '1';
if (uart_din_rdy = '1') then
fsm_nstate <= din1;
else
fsm_nstate <= din0;
end if;
when din1 => -- send read data byte 1 to UART (read cmd only)
uart_din <= din_reg(15 downto 8);
uart_din_vld <= '1';
if (uart_din_rdy = '1') then
fsm_nstate <= din2;
else
fsm_nstate <= din1;
end if;
when din2 => -- send read data byte 2 to UART (read cmd only)
uart_din <= din_reg(23 downto 16);
uart_din_vld <= '1';
if (uart_din_rdy = '1') then
fsm_nstate <= din3;
else
fsm_nstate <= din2;
end if;
when din3 => -- send read data byte 3 to UART (read cmd only)
uart_din <= din_reg(31 downto 24);
uart_din_vld <= '1';
if (uart_din_rdy = '1') then
fsm_nstate <= cmd;
else
fsm_nstate <= din3;
end if;
end case;
end process;
-- -------------------------------------------------------------------------
-- UART module
-- -------------------------------------------------------------------------
uart_i : entity work.UART
generic map (
CLK_FREQ => CLK_FREQ,
BAUD_RATE => BAUD_RATE,
PARITY_BIT => "none",
USE_DEBOUNCER => True
)
port map (
CLK => CLK,
RST => RST,
-- UART INTERFACE
UART_TXD => UART_TXD,
UART_RXD => UART_RXD,
-- USER DATA INPUT INTERFACE
DIN => uart_din,
DIN_VLD => uart_din_vld,
DIN_RDY => uart_din_rdy,
-- USER DATA OUTPUT INTERFACE
DOUT => uart_dout,
DOUT_VLD => uart_dout_vld,
FRAME_ERROR => open,
PARITY_ERROR => open
);
end architecture;
| mit | 394c8cd088c1183a7c983b1e640384f3 | 0.421481 | 4.300521 | false | false | false | false |
varunnagpaal/Digital-Hardware-Modelling | vhdl/aluseq/top - Copy.vhdl | 1 | 5,702 | library IEEE;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity top is
generic( W : natural := 4, -- Width of data
N : natural := 5, -- Width of control signals
L : natural := 4 ); -- Depth of instruction pipeline
port (clk : in std_logic;
rst : in std_logic; -- active high sync to clock
in_data_a : in std_logic_vector(W-1 downto 0); -- input data A
in_data_b : in std_logic_vector(W-1 downto 0); -- input data B
in_data_carry : in std_logic; -- carry in or borrow in
in_ctrl : in std_logic_vector(N-1 downto 0); -- control signals
out_data_c : out std_logic_vector(W-1 downto 0); -- output data C
out_data_carry : out std_logic; -- carry out or borrow out
out_data_comp : out std_logic_vector(1 downto 0); -- output comparison
out_valid : out std_logic -- valid output
);
end top;
architecture behavioral of top is
signal reg_instr: std_logic_vector(in_ctrl'RANGE) := (others => '1');
signal sig_valid_instr: std_logic;
signal sig_valid_cnt: std_logic;
begin
process(clk)
begin
if rising_edge(clk) then
if( rst == '1') then
out_data_c <= (others => '0');
out_data_carry <= '0';
out_data_comp <= (others => '0');
out_valid <= '0';
reg_instr <= (others => '1');
else
out_data_c <= (others => '0');
out_data_carry <= '0';
out_data_comp <= (others => '0');
-- TBU: out_valid set to sig_valid after 2 additional clock cycles
out_valid <= '0';
reg_instr <= in_ctrl;
end if;
end if;
end process;
-- For every new instruction received on clock cycle,
-- generate internal valid signal
sig_valid_instr <= '1' when reg_instr = "0001" OR
reg_instr = "0010" OR
reg_instr = "0011" OR
reg_instr = "0100" OR
reg_instr = "0101" OR
reg_instr = "0110" OR
reg_instr = "0111" else '0';
comb_memless_process: process ( in_data_a, in_data_b, in_data_carry, in_ctrl )
variable temp_carry: std_logic_vector(W downto 0) := ( others => '0' );
begin
out_data_c <= (others => '0');
out_data_carry <= '0';
out_data_comp <= (others => '0');
case in_ctrl is
--when "000" => out_data_c <= in_data_a;
-- out_data_carry <= in_data_carry;
when "0001" => -- ripple carry adder: {sum, cout} = a+b+cin
temp_carry(0) := in_data_carry;
for i in 0 to W-1 loop
-- sum(k) = a(k) xor b(k) xor c(k)
out_data_c(i) <= in_data_a(i) xor in_data_b(i) xor temp_carry(i);
-- cout(k+1) = a(k).b(k) + b(k).c(k) + c(k).a(k)
temp_carry(i+1) := ( in_data_a(i) and in_data_b(i) ) or
( in_data_b(i) and temp_carry(i) ) or
( temp_carry(i) and in_data_a(i) );
end loop;
out_data_carry <= temp_carry(W);
when "0010" => -- full subtraction: {diff, bout} = a-b-bin
temp_carry(0) := in_data_carry;
for i in 0 to W-1 loop
-- diff(k) = a(k) xor b(k) xor c(k)
out_data_c(i) <= in_data_a(i) xor in_data_b(i) xor temp_carry(i);
-- bout(k+1) = !a(k).b(k) + b(k).c(k) + c(k).!a(k)
temp_carry(i+1) := ( ( NOT in_data_a(i) ) AND in_data_b(i) ) OR
( in_data_b(i) AND temp_carry(i) ) OR
( temp_carry(i) AND ( NOT in_data_a(i) ) );
end loop;
out_data_carry <= temp_carry(W);
when "0011" => -- comparator: comp_out = 1 if A > B
if( in_data_a > in_data_b ) then
out_data_comp <= "01";
else
out_data_comp <= "00";
end if;
when "0100" => -- comparator: comp_out = 1 if A < B
if( in_data_a < in_data_b ) then
out_data_comp <= "01";
else
out_data_comp <= ( others => '0' );
end if;
when "0101" => -- comparator: comp_out = 1 if A = B
if( in_data_a = in_data_b ) then
out_data_comp <= "01";
else
out_data_comp <= ( others => '0' );
end if;
when "0110" => -- logical right shift A by B[1:0]
out_data_c <= std_logic_vector( unsigned(in_data_a) srl to_integer( unsigned( in_data_b(1 downto 0) ) ) );
when "111" => -- logical left shift A by B
out_data_c <= std_logic_vector( unsigned(in_data_a) sll to_integer( unsigned( in_data_b(1 downto 0) ) ) );
when others => -- NOP
--
end case;
end process comb_memless_process;
end behavioral; | mit | 228ee932dfe69151178c3a97d4b41ccd | 0.416696 | 3.731675 | false | false | false | false |
MartinCura/SistDig-TP4 | old/det_angulos.vhd | 1 | 1,924 | library IEEE;
use IEEE.std_logic_1164.all;
library work;
use work.cordic_lib.all;
---use work.float_pkg.all;
--library ieee_proposed;
--use ieee_proposed.float_pkg.all;
library floatfixlib;
use floatfixlib.float_pkg.all;
-- Almacena y actualiza ángulos de rotación en cada ciclo
--- Funciona perfecto (salvo por un retraso de 1 clock para resetear, nada importante)
entity det_angulos is
generic (
C : integer := 1---50 * (10**6) -- Ciclo en clocks. Clock es 50 MHz. --- Si es rotación manual, chequear siempre
);
port (
clk: in std_logic;
ena: in std_logic;
rst: in std_logic;
inc_a, inc_b, inc_g: in std_logic;
neg_a, neg_b, neg_g: in std_logic;
a, b, g: out float32 := CERO
);
end;
architecture det_angulos_arq of det_angulos is
constant PASO_ANG : t_float := "00111111001101000000000000000000"; -- Paso angular ∆φ: 0.703125 grados
constant PASO_ANG_R : t_float := PI_PF * PASO_ANG / 180; -- Paso angular en radianes
signal a_aux, b_aux, g_aux : t_float := CERO;
begin
process(clk)---, rst, inc_a, inc_b, inc_g)
variable i : NATURAL := 0;
begin
if rising_edge(clk) then
if rst = '1' then
a_aux <= CERO;
b_aux <= CERO;
g_aux <= CERO;
elsif ena = '1' then
i := i + 1;
if i >= C then -- Actualizar ángulos de rotación cada C clocks
i := 0;
if inc_a = '1' then
if neg_a = '1' then
a_aux <= a_aux - PASO_ANG_R;
else
a_aux <= a_aux + PASO_ANG_R;
end if;
end if;
if inc_b = '1' then
if neg_b = '1' then
b_aux <= b_aux - PASO_ANG_R;
else
b_aux <= b_aux + PASO_ANG_R;
end if;
end if;
if inc_g = '1' then
if neg_g = '1' then
g_aux <= g_aux - PASO_ANG_R;
else
g_aux <= g_aux + PASO_ANG_R;
end if;
end if;
end if;
end if;
end if;
end process;
a <= a_aux;
b <= b_aux;
g <= g_aux;
end;
| gpl-3.0 | 8811d4c2dac8b180c26b5b5c3beadc38 | 0.5762 | 2.544489 | false | false | false | false |
varunnagpaal/Digital-Hardware-Modelling | xilinx-vivado/proj_pointer_basic_hls_ip_integ/proj_pointer_basic_hls_ip_integ.cache/ip/2018.2/62bdfa38c62a5876/design_1_pointer_basic_0_0_sim_netlist.vhdl | 1 | 103,345 | -- Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2018.2 (win64) Build 2258646 Thu Jun 14 20:03:12 MDT 2018
-- Date : Mon Sep 16 04:56:42 2019
-- Host : varun-laptop running 64-bit Service Pack 1 (build 7601)
-- Command : write_vhdl -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
-- decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ design_1_pointer_basic_0_0_sim_netlist.vhdl
-- Design : design_1_pointer_basic_0_0
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7z010clg400-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_pointer_basic_pointer_basic_io_s_axi is
port (
\out\ : out STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_pointer_basic_io_RVALID : out STD_LOGIC_VECTOR ( 1 downto 0 );
SR : out STD_LOGIC_VECTOR ( 0 to 0 );
Q : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_pointer_basic_io_RDATA : out STD_LOGIC_VECTOR ( 31 downto 0 );
ap_clk : in STD_LOGIC;
s_axi_pointer_basic_io_ARVALID : in STD_LOGIC;
s_axi_pointer_basic_io_RREADY : in STD_LOGIC;
s_axi_pointer_basic_io_ARADDR : in STD_LOGIC_VECTOR ( 4 downto 0 );
s_axi_pointer_basic_io_WDATA : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_pointer_basic_io_WSTRB : in STD_LOGIC_VECTOR ( 3 downto 0 );
ap_rst_n : in STD_LOGIC;
\ap_CS_fsm_reg[2]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_pointer_basic_io_AWADDR : in STD_LOGIC_VECTOR ( 4 downto 0 );
D : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_pointer_basic_io_AWVALID : in STD_LOGIC;
s_axi_pointer_basic_io_BREADY : in STD_LOGIC;
s_axi_pointer_basic_io_WVALID : in STD_LOGIC
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_pointer_basic_pointer_basic_io_s_axi;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_pointer_basic_pointer_basic_io_s_axi is
signal \FSM_onehot_rstate[1]_i_1_n_0\ : STD_LOGIC;
signal \FSM_onehot_rstate[2]_i_1_n_0\ : STD_LOGIC;
signal \FSM_onehot_rstate_reg_n_0_[0]\ : STD_LOGIC;
attribute RTL_KEEP : string;
attribute RTL_KEEP of \FSM_onehot_rstate_reg_n_0_[0]\ : signal is "yes";
signal \FSM_onehot_wstate[1]_i_1_n_0\ : STD_LOGIC;
signal \FSM_onehot_wstate[2]_i_1_n_0\ : STD_LOGIC;
signal \FSM_onehot_wstate[3]_i_1_n_0\ : STD_LOGIC;
signal \FSM_onehot_wstate_reg_n_0_[0]\ : STD_LOGIC;
attribute RTL_KEEP of \FSM_onehot_wstate_reg_n_0_[0]\ : signal is "yes";
signal \^q\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \^sr\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal ar_hs : STD_LOGIC;
signal \int_d_i[0]_i_1_n_0\ : STD_LOGIC;
signal \int_d_i[10]_i_1_n_0\ : STD_LOGIC;
signal \int_d_i[11]_i_1_n_0\ : STD_LOGIC;
signal \int_d_i[12]_i_1_n_0\ : STD_LOGIC;
signal \int_d_i[13]_i_1_n_0\ : STD_LOGIC;
signal \int_d_i[14]_i_1_n_0\ : STD_LOGIC;
signal \int_d_i[15]_i_1_n_0\ : STD_LOGIC;
signal \int_d_i[16]_i_1_n_0\ : STD_LOGIC;
signal \int_d_i[17]_i_1_n_0\ : STD_LOGIC;
signal \int_d_i[18]_i_1_n_0\ : STD_LOGIC;
signal \int_d_i[19]_i_1_n_0\ : STD_LOGIC;
signal \int_d_i[1]_i_1_n_0\ : STD_LOGIC;
signal \int_d_i[20]_i_1_n_0\ : STD_LOGIC;
signal \int_d_i[21]_i_1_n_0\ : STD_LOGIC;
signal \int_d_i[22]_i_1_n_0\ : STD_LOGIC;
signal \int_d_i[23]_i_1_n_0\ : STD_LOGIC;
signal \int_d_i[24]_i_1_n_0\ : STD_LOGIC;
signal \int_d_i[25]_i_1_n_0\ : STD_LOGIC;
signal \int_d_i[26]_i_1_n_0\ : STD_LOGIC;
signal \int_d_i[27]_i_1_n_0\ : STD_LOGIC;
signal \int_d_i[28]_i_1_n_0\ : STD_LOGIC;
signal \int_d_i[29]_i_1_n_0\ : STD_LOGIC;
signal \int_d_i[2]_i_1_n_0\ : STD_LOGIC;
signal \int_d_i[30]_i_1_n_0\ : STD_LOGIC;
signal \int_d_i[31]_i_2_n_0\ : STD_LOGIC;
signal \int_d_i[31]_i_3_n_0\ : STD_LOGIC;
signal \int_d_i[3]_i_1_n_0\ : STD_LOGIC;
signal \int_d_i[4]_i_1_n_0\ : STD_LOGIC;
signal \int_d_i[5]_i_1_n_0\ : STD_LOGIC;
signal \int_d_i[6]_i_1_n_0\ : STD_LOGIC;
signal \int_d_i[7]_i_1_n_0\ : STD_LOGIC;
signal \int_d_i[8]_i_1_n_0\ : STD_LOGIC;
signal \int_d_i[9]_i_1_n_0\ : STD_LOGIC;
signal int_d_o : STD_LOGIC_VECTOR ( 31 downto 0 );
signal int_d_o_ap_vld : STD_LOGIC;
signal int_d_o_ap_vld_i_1_n_0 : STD_LOGIC;
signal int_d_o_ap_vld_i_2_n_0 : STD_LOGIC;
signal \^out\ : STD_LOGIC_VECTOR ( 2 downto 0 );
attribute RTL_KEEP of \^out\ : signal is "yes";
signal p_0_in : STD_LOGIC;
signal \rdata[0]_i_1_n_0\ : STD_LOGIC;
signal \rdata[0]_i_2_n_0\ : STD_LOGIC;
signal \rdata[10]_i_1_n_0\ : STD_LOGIC;
signal \rdata[11]_i_1_n_0\ : STD_LOGIC;
signal \rdata[12]_i_1_n_0\ : STD_LOGIC;
signal \rdata[13]_i_1_n_0\ : STD_LOGIC;
signal \rdata[14]_i_1_n_0\ : STD_LOGIC;
signal \rdata[15]_i_1_n_0\ : STD_LOGIC;
signal \rdata[16]_i_1_n_0\ : STD_LOGIC;
signal \rdata[17]_i_1_n_0\ : STD_LOGIC;
signal \rdata[18]_i_1_n_0\ : STD_LOGIC;
signal \rdata[19]_i_1_n_0\ : STD_LOGIC;
signal \rdata[1]_i_1_n_0\ : STD_LOGIC;
signal \rdata[20]_i_1_n_0\ : STD_LOGIC;
signal \rdata[21]_i_1_n_0\ : STD_LOGIC;
signal \rdata[22]_i_1_n_0\ : STD_LOGIC;
signal \rdata[23]_i_1_n_0\ : STD_LOGIC;
signal \rdata[24]_i_1_n_0\ : STD_LOGIC;
signal \rdata[25]_i_1_n_0\ : STD_LOGIC;
signal \rdata[26]_i_1_n_0\ : STD_LOGIC;
signal \rdata[27]_i_1_n_0\ : STD_LOGIC;
signal \rdata[28]_i_1_n_0\ : STD_LOGIC;
signal \rdata[29]_i_1_n_0\ : STD_LOGIC;
signal \rdata[2]_i_1_n_0\ : STD_LOGIC;
signal \rdata[30]_i_1_n_0\ : STD_LOGIC;
signal \rdata[31]_i_1_n_0\ : STD_LOGIC;
signal \rdata[31]_i_3_n_0\ : STD_LOGIC;
signal \rdata[3]_i_1_n_0\ : STD_LOGIC;
signal \rdata[4]_i_1_n_0\ : STD_LOGIC;
signal \rdata[5]_i_1_n_0\ : STD_LOGIC;
signal \rdata[6]_i_1_n_0\ : STD_LOGIC;
signal \rdata[7]_i_1_n_0\ : STD_LOGIC;
signal \rdata[8]_i_1_n_0\ : STD_LOGIC;
signal \rdata[9]_i_1_n_0\ : STD_LOGIC;
signal \^s_axi_pointer_basic_io_rdata\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \^s_axi_pointer_basic_io_rvalid\ : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute RTL_KEEP of \^s_axi_pointer_basic_io_rvalid\ : signal is "yes";
signal waddr : STD_LOGIC;
signal \waddr_reg_n_0_[0]\ : STD_LOGIC;
signal \waddr_reg_n_0_[1]\ : STD_LOGIC;
signal \waddr_reg_n_0_[2]\ : STD_LOGIC;
signal \waddr_reg_n_0_[3]\ : STD_LOGIC;
signal \waddr_reg_n_0_[4]\ : STD_LOGIC;
attribute FSM_ENCODED_STATES : string;
attribute FSM_ENCODED_STATES of \FSM_onehot_rstate_reg[0]\ : label is "RDIDLE:010,RDDATA:100,iSTATE:001";
attribute KEEP : string;
attribute KEEP of \FSM_onehot_rstate_reg[0]\ : label is "yes";
attribute FSM_ENCODED_STATES of \FSM_onehot_rstate_reg[1]\ : label is "RDIDLE:010,RDDATA:100,iSTATE:001";
attribute KEEP of \FSM_onehot_rstate_reg[1]\ : label is "yes";
attribute FSM_ENCODED_STATES of \FSM_onehot_rstate_reg[2]\ : label is "RDIDLE:010,RDDATA:100,iSTATE:001";
attribute KEEP of \FSM_onehot_rstate_reg[2]\ : label is "yes";
attribute FSM_ENCODED_STATES of \FSM_onehot_wstate_reg[0]\ : label is "WRDATA:0100,WRRESP:1000,WRIDLE:0010,iSTATE:0001";
attribute KEEP of \FSM_onehot_wstate_reg[0]\ : label is "yes";
attribute FSM_ENCODED_STATES of \FSM_onehot_wstate_reg[1]\ : label is "WRDATA:0100,WRRESP:1000,WRIDLE:0010,iSTATE:0001";
attribute KEEP of \FSM_onehot_wstate_reg[1]\ : label is "yes";
attribute FSM_ENCODED_STATES of \FSM_onehot_wstate_reg[2]\ : label is "WRDATA:0100,WRRESP:1000,WRIDLE:0010,iSTATE:0001";
attribute KEEP of \FSM_onehot_wstate_reg[2]\ : label is "yes";
attribute FSM_ENCODED_STATES of \FSM_onehot_wstate_reg[3]\ : label is "WRDATA:0100,WRRESP:1000,WRIDLE:0010,iSTATE:0001";
attribute KEEP of \FSM_onehot_wstate_reg[3]\ : label is "yes";
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \int_d_i[0]_i_1\ : label is "soft_lutpair15";
attribute SOFT_HLUTNM of \int_d_i[10]_i_1\ : label is "soft_lutpair10";
attribute SOFT_HLUTNM of \int_d_i[11]_i_1\ : label is "soft_lutpair10";
attribute SOFT_HLUTNM of \int_d_i[12]_i_1\ : label is "soft_lutpair9";
attribute SOFT_HLUTNM of \int_d_i[13]_i_1\ : label is "soft_lutpair9";
attribute SOFT_HLUTNM of \int_d_i[14]_i_1\ : label is "soft_lutpair8";
attribute SOFT_HLUTNM of \int_d_i[15]_i_1\ : label is "soft_lutpair8";
attribute SOFT_HLUTNM of \int_d_i[16]_i_1\ : label is "soft_lutpair7";
attribute SOFT_HLUTNM of \int_d_i[17]_i_1\ : label is "soft_lutpair7";
attribute SOFT_HLUTNM of \int_d_i[18]_i_1\ : label is "soft_lutpair6";
attribute SOFT_HLUTNM of \int_d_i[19]_i_1\ : label is "soft_lutpair6";
attribute SOFT_HLUTNM of \int_d_i[1]_i_1\ : label is "soft_lutpair15";
attribute SOFT_HLUTNM of \int_d_i[20]_i_1\ : label is "soft_lutpair5";
attribute SOFT_HLUTNM of \int_d_i[21]_i_1\ : label is "soft_lutpair5";
attribute SOFT_HLUTNM of \int_d_i[22]_i_1\ : label is "soft_lutpair4";
attribute SOFT_HLUTNM of \int_d_i[23]_i_1\ : label is "soft_lutpair4";
attribute SOFT_HLUTNM of \int_d_i[24]_i_1\ : label is "soft_lutpair3";
attribute SOFT_HLUTNM of \int_d_i[25]_i_1\ : label is "soft_lutpair3";
attribute SOFT_HLUTNM of \int_d_i[26]_i_1\ : label is "soft_lutpair2";
attribute SOFT_HLUTNM of \int_d_i[27]_i_1\ : label is "soft_lutpair2";
attribute SOFT_HLUTNM of \int_d_i[28]_i_1\ : label is "soft_lutpair1";
attribute SOFT_HLUTNM of \int_d_i[29]_i_1\ : label is "soft_lutpair1";
attribute SOFT_HLUTNM of \int_d_i[2]_i_1\ : label is "soft_lutpair14";
attribute SOFT_HLUTNM of \int_d_i[30]_i_1\ : label is "soft_lutpair0";
attribute SOFT_HLUTNM of \int_d_i[31]_i_2\ : label is "soft_lutpair0";
attribute SOFT_HLUTNM of \int_d_i[3]_i_1\ : label is "soft_lutpair14";
attribute SOFT_HLUTNM of \int_d_i[4]_i_1\ : label is "soft_lutpair13";
attribute SOFT_HLUTNM of \int_d_i[5]_i_1\ : label is "soft_lutpair13";
attribute SOFT_HLUTNM of \int_d_i[6]_i_1\ : label is "soft_lutpair12";
attribute SOFT_HLUTNM of \int_d_i[7]_i_1\ : label is "soft_lutpair12";
attribute SOFT_HLUTNM of \int_d_i[8]_i_1\ : label is "soft_lutpair11";
attribute SOFT_HLUTNM of \int_d_i[9]_i_1\ : label is "soft_lutpair11";
attribute SOFT_HLUTNM of \rdata[10]_i_1\ : label is "soft_lutpair26";
attribute SOFT_HLUTNM of \rdata[11]_i_1\ : label is "soft_lutpair26";
attribute SOFT_HLUTNM of \rdata[12]_i_1\ : label is "soft_lutpair25";
attribute SOFT_HLUTNM of \rdata[13]_i_1\ : label is "soft_lutpair25";
attribute SOFT_HLUTNM of \rdata[14]_i_1\ : label is "soft_lutpair24";
attribute SOFT_HLUTNM of \rdata[15]_i_1\ : label is "soft_lutpair24";
attribute SOFT_HLUTNM of \rdata[16]_i_1\ : label is "soft_lutpair23";
attribute SOFT_HLUTNM of \rdata[17]_i_1\ : label is "soft_lutpair23";
attribute SOFT_HLUTNM of \rdata[18]_i_1\ : label is "soft_lutpair22";
attribute SOFT_HLUTNM of \rdata[19]_i_1\ : label is "soft_lutpair22";
attribute SOFT_HLUTNM of \rdata[20]_i_1\ : label is "soft_lutpair21";
attribute SOFT_HLUTNM of \rdata[21]_i_1\ : label is "soft_lutpair21";
attribute SOFT_HLUTNM of \rdata[22]_i_1\ : label is "soft_lutpair20";
attribute SOFT_HLUTNM of \rdata[23]_i_1\ : label is "soft_lutpair20";
attribute SOFT_HLUTNM of \rdata[24]_i_1\ : label is "soft_lutpair19";
attribute SOFT_HLUTNM of \rdata[25]_i_1\ : label is "soft_lutpair19";
attribute SOFT_HLUTNM of \rdata[26]_i_1\ : label is "soft_lutpair18";
attribute SOFT_HLUTNM of \rdata[27]_i_1\ : label is "soft_lutpair18";
attribute SOFT_HLUTNM of \rdata[28]_i_1\ : label is "soft_lutpair17";
attribute SOFT_HLUTNM of \rdata[29]_i_1\ : label is "soft_lutpair17";
attribute SOFT_HLUTNM of \rdata[2]_i_1\ : label is "soft_lutpair30";
attribute SOFT_HLUTNM of \rdata[30]_i_1\ : label is "soft_lutpair16";
attribute SOFT_HLUTNM of \rdata[31]_i_3\ : label is "soft_lutpair16";
attribute SOFT_HLUTNM of \rdata[3]_i_1\ : label is "soft_lutpair30";
attribute SOFT_HLUTNM of \rdata[4]_i_1\ : label is "soft_lutpair29";
attribute SOFT_HLUTNM of \rdata[5]_i_1\ : label is "soft_lutpair29";
attribute SOFT_HLUTNM of \rdata[6]_i_1\ : label is "soft_lutpair28";
attribute SOFT_HLUTNM of \rdata[7]_i_1\ : label is "soft_lutpair28";
attribute SOFT_HLUTNM of \rdata[8]_i_1\ : label is "soft_lutpair27";
attribute SOFT_HLUTNM of \rdata[9]_i_1\ : label is "soft_lutpair27";
begin
Q(31 downto 0) <= \^q\(31 downto 0);
SR(0) <= \^sr\(0);
\out\(2 downto 0) <= \^out\(2 downto 0);
s_axi_pointer_basic_io_RDATA(31 downto 0) <= \^s_axi_pointer_basic_io_rdata\(31 downto 0);
s_axi_pointer_basic_io_RVALID(1 downto 0) <= \^s_axi_pointer_basic_io_rvalid\(1 downto 0);
\FSM_onehot_rstate[1]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"8BFB"
)
port map (
I0 => s_axi_pointer_basic_io_RREADY,
I1 => \^s_axi_pointer_basic_io_rvalid\(1),
I2 => \^s_axi_pointer_basic_io_rvalid\(0),
I3 => s_axi_pointer_basic_io_ARVALID,
O => \FSM_onehot_rstate[1]_i_1_n_0\
);
\FSM_onehot_rstate[2]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"8F88"
)
port map (
I0 => s_axi_pointer_basic_io_ARVALID,
I1 => \^s_axi_pointer_basic_io_rvalid\(0),
I2 => s_axi_pointer_basic_io_RREADY,
I3 => \^s_axi_pointer_basic_io_rvalid\(1),
O => \FSM_onehot_rstate[2]_i_1_n_0\
);
\FSM_onehot_rstate_reg[0]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => ap_clk,
CE => '1',
D => '0',
Q => \FSM_onehot_rstate_reg_n_0_[0]\,
S => \^sr\(0)
);
\FSM_onehot_rstate_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ap_clk,
CE => '1',
D => \FSM_onehot_rstate[1]_i_1_n_0\,
Q => \^s_axi_pointer_basic_io_rvalid\(0),
R => \^sr\(0)
);
\FSM_onehot_rstate_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ap_clk,
CE => '1',
D => \FSM_onehot_rstate[2]_i_1_n_0\,
Q => \^s_axi_pointer_basic_io_rvalid\(1),
R => \^sr\(0)
);
\FSM_onehot_wstate[1]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"888BFF8B"
)
port map (
I0 => s_axi_pointer_basic_io_BREADY,
I1 => \^out\(2),
I2 => \^out\(1),
I3 => \^out\(0),
I4 => s_axi_pointer_basic_io_AWVALID,
O => \FSM_onehot_wstate[1]_i_1_n_0\
);
\FSM_onehot_wstate[2]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"8F88"
)
port map (
I0 => s_axi_pointer_basic_io_AWVALID,
I1 => \^out\(0),
I2 => s_axi_pointer_basic_io_WVALID,
I3 => \^out\(1),
O => \FSM_onehot_wstate[2]_i_1_n_0\
);
\FSM_onehot_wstate[3]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"8F88"
)
port map (
I0 => s_axi_pointer_basic_io_WVALID,
I1 => \^out\(1),
I2 => s_axi_pointer_basic_io_BREADY,
I3 => \^out\(2),
O => \FSM_onehot_wstate[3]_i_1_n_0\
);
\FSM_onehot_wstate_reg[0]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => ap_clk,
CE => '1',
D => '0',
Q => \FSM_onehot_wstate_reg_n_0_[0]\,
S => \^sr\(0)
);
\FSM_onehot_wstate_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ap_clk,
CE => '1',
D => \FSM_onehot_wstate[1]_i_1_n_0\,
Q => \^out\(0),
R => \^sr\(0)
);
\FSM_onehot_wstate_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ap_clk,
CE => '1',
D => \FSM_onehot_wstate[2]_i_1_n_0\,
Q => \^out\(1),
R => \^sr\(0)
);
\FSM_onehot_wstate_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ap_clk,
CE => '1',
D => \FSM_onehot_wstate[3]_i_1_n_0\,
Q => \^out\(2),
R => \^sr\(0)
);
\ap_CS_fsm[2]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => ap_rst_n,
O => \^sr\(0)
);
\int_d_i[0]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_pointer_basic_io_WDATA(0),
I1 => s_axi_pointer_basic_io_WSTRB(0),
I2 => \^q\(0),
O => \int_d_i[0]_i_1_n_0\
);
\int_d_i[10]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_pointer_basic_io_WDATA(10),
I1 => s_axi_pointer_basic_io_WSTRB(1),
I2 => \^q\(10),
O => \int_d_i[10]_i_1_n_0\
);
\int_d_i[11]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_pointer_basic_io_WDATA(11),
I1 => s_axi_pointer_basic_io_WSTRB(1),
I2 => \^q\(11),
O => \int_d_i[11]_i_1_n_0\
);
\int_d_i[12]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_pointer_basic_io_WDATA(12),
I1 => s_axi_pointer_basic_io_WSTRB(1),
I2 => \^q\(12),
O => \int_d_i[12]_i_1_n_0\
);
\int_d_i[13]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_pointer_basic_io_WDATA(13),
I1 => s_axi_pointer_basic_io_WSTRB(1),
I2 => \^q\(13),
O => \int_d_i[13]_i_1_n_0\
);
\int_d_i[14]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_pointer_basic_io_WDATA(14),
I1 => s_axi_pointer_basic_io_WSTRB(1),
I2 => \^q\(14),
O => \int_d_i[14]_i_1_n_0\
);
\int_d_i[15]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_pointer_basic_io_WDATA(15),
I1 => s_axi_pointer_basic_io_WSTRB(1),
I2 => \^q\(15),
O => \int_d_i[15]_i_1_n_0\
);
\int_d_i[16]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_pointer_basic_io_WDATA(16),
I1 => s_axi_pointer_basic_io_WSTRB(2),
I2 => \^q\(16),
O => \int_d_i[16]_i_1_n_0\
);
\int_d_i[17]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_pointer_basic_io_WDATA(17),
I1 => s_axi_pointer_basic_io_WSTRB(2),
I2 => \^q\(17),
O => \int_d_i[17]_i_1_n_0\
);
\int_d_i[18]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_pointer_basic_io_WDATA(18),
I1 => s_axi_pointer_basic_io_WSTRB(2),
I2 => \^q\(18),
O => \int_d_i[18]_i_1_n_0\
);
\int_d_i[19]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_pointer_basic_io_WDATA(19),
I1 => s_axi_pointer_basic_io_WSTRB(2),
I2 => \^q\(19),
O => \int_d_i[19]_i_1_n_0\
);
\int_d_i[1]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_pointer_basic_io_WDATA(1),
I1 => s_axi_pointer_basic_io_WSTRB(0),
I2 => \^q\(1),
O => \int_d_i[1]_i_1_n_0\
);
\int_d_i[20]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_pointer_basic_io_WDATA(20),
I1 => s_axi_pointer_basic_io_WSTRB(2),
I2 => \^q\(20),
O => \int_d_i[20]_i_1_n_0\
);
\int_d_i[21]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_pointer_basic_io_WDATA(21),
I1 => s_axi_pointer_basic_io_WSTRB(2),
I2 => \^q\(21),
O => \int_d_i[21]_i_1_n_0\
);
\int_d_i[22]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_pointer_basic_io_WDATA(22),
I1 => s_axi_pointer_basic_io_WSTRB(2),
I2 => \^q\(22),
O => \int_d_i[22]_i_1_n_0\
);
\int_d_i[23]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_pointer_basic_io_WDATA(23),
I1 => s_axi_pointer_basic_io_WSTRB(2),
I2 => \^q\(23),
O => \int_d_i[23]_i_1_n_0\
);
\int_d_i[24]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_pointer_basic_io_WDATA(24),
I1 => s_axi_pointer_basic_io_WSTRB(3),
I2 => \^q\(24),
O => \int_d_i[24]_i_1_n_0\
);
\int_d_i[25]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_pointer_basic_io_WDATA(25),
I1 => s_axi_pointer_basic_io_WSTRB(3),
I2 => \^q\(25),
O => \int_d_i[25]_i_1_n_0\
);
\int_d_i[26]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_pointer_basic_io_WDATA(26),
I1 => s_axi_pointer_basic_io_WSTRB(3),
I2 => \^q\(26),
O => \int_d_i[26]_i_1_n_0\
);
\int_d_i[27]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_pointer_basic_io_WDATA(27),
I1 => s_axi_pointer_basic_io_WSTRB(3),
I2 => \^q\(27),
O => \int_d_i[27]_i_1_n_0\
);
\int_d_i[28]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_pointer_basic_io_WDATA(28),
I1 => s_axi_pointer_basic_io_WSTRB(3),
I2 => \^q\(28),
O => \int_d_i[28]_i_1_n_0\
);
\int_d_i[29]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_pointer_basic_io_WDATA(29),
I1 => s_axi_pointer_basic_io_WSTRB(3),
I2 => \^q\(29),
O => \int_d_i[29]_i_1_n_0\
);
\int_d_i[2]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_pointer_basic_io_WDATA(2),
I1 => s_axi_pointer_basic_io_WSTRB(0),
I2 => \^q\(2),
O => \int_d_i[2]_i_1_n_0\
);
\int_d_i[30]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_pointer_basic_io_WDATA(30),
I1 => s_axi_pointer_basic_io_WSTRB(3),
I2 => \^q\(30),
O => \int_d_i[30]_i_1_n_0\
);
\int_d_i[31]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => s_axi_pointer_basic_io_WVALID,
I1 => \int_d_i[31]_i_3_n_0\,
O => p_0_in
);
\int_d_i[31]_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_pointer_basic_io_WDATA(31),
I1 => s_axi_pointer_basic_io_WSTRB(3),
I2 => \^q\(31),
O => \int_d_i[31]_i_2_n_0\
);
\int_d_i[31]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"0001000000000000"
)
port map (
I0 => \waddr_reg_n_0_[0]\,
I1 => \waddr_reg_n_0_[3]\,
I2 => \waddr_reg_n_0_[1]\,
I3 => \waddr_reg_n_0_[2]\,
I4 => \waddr_reg_n_0_[4]\,
I5 => \^out\(1),
O => \int_d_i[31]_i_3_n_0\
);
\int_d_i[3]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_pointer_basic_io_WDATA(3),
I1 => s_axi_pointer_basic_io_WSTRB(0),
I2 => \^q\(3),
O => \int_d_i[3]_i_1_n_0\
);
\int_d_i[4]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_pointer_basic_io_WDATA(4),
I1 => s_axi_pointer_basic_io_WSTRB(0),
I2 => \^q\(4),
O => \int_d_i[4]_i_1_n_0\
);
\int_d_i[5]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_pointer_basic_io_WDATA(5),
I1 => s_axi_pointer_basic_io_WSTRB(0),
I2 => \^q\(5),
O => \int_d_i[5]_i_1_n_0\
);
\int_d_i[6]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_pointer_basic_io_WDATA(6),
I1 => s_axi_pointer_basic_io_WSTRB(0),
I2 => \^q\(6),
O => \int_d_i[6]_i_1_n_0\
);
\int_d_i[7]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_pointer_basic_io_WDATA(7),
I1 => s_axi_pointer_basic_io_WSTRB(0),
I2 => \^q\(7),
O => \int_d_i[7]_i_1_n_0\
);
\int_d_i[8]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_pointer_basic_io_WDATA(8),
I1 => s_axi_pointer_basic_io_WSTRB(1),
I2 => \^q\(8),
O => \int_d_i[8]_i_1_n_0\
);
\int_d_i[9]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_pointer_basic_io_WDATA(9),
I1 => s_axi_pointer_basic_io_WSTRB(1),
I2 => \^q\(9),
O => \int_d_i[9]_i_1_n_0\
);
\int_d_i_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ap_clk,
CE => p_0_in,
D => \int_d_i[0]_i_1_n_0\,
Q => \^q\(0),
R => \^sr\(0)
);
\int_d_i_reg[10]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ap_clk,
CE => p_0_in,
D => \int_d_i[10]_i_1_n_0\,
Q => \^q\(10),
R => \^sr\(0)
);
\int_d_i_reg[11]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ap_clk,
CE => p_0_in,
D => \int_d_i[11]_i_1_n_0\,
Q => \^q\(11),
R => \^sr\(0)
);
\int_d_i_reg[12]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ap_clk,
CE => p_0_in,
D => \int_d_i[12]_i_1_n_0\,
Q => \^q\(12),
R => \^sr\(0)
);
\int_d_i_reg[13]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ap_clk,
CE => p_0_in,
D => \int_d_i[13]_i_1_n_0\,
Q => \^q\(13),
R => \^sr\(0)
);
\int_d_i_reg[14]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ap_clk,
CE => p_0_in,
D => \int_d_i[14]_i_1_n_0\,
Q => \^q\(14),
R => \^sr\(0)
);
\int_d_i_reg[15]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ap_clk,
CE => p_0_in,
D => \int_d_i[15]_i_1_n_0\,
Q => \^q\(15),
R => \^sr\(0)
);
\int_d_i_reg[16]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ap_clk,
CE => p_0_in,
D => \int_d_i[16]_i_1_n_0\,
Q => \^q\(16),
R => \^sr\(0)
);
\int_d_i_reg[17]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ap_clk,
CE => p_0_in,
D => \int_d_i[17]_i_1_n_0\,
Q => \^q\(17),
R => \^sr\(0)
);
\int_d_i_reg[18]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ap_clk,
CE => p_0_in,
D => \int_d_i[18]_i_1_n_0\,
Q => \^q\(18),
R => \^sr\(0)
);
\int_d_i_reg[19]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ap_clk,
CE => p_0_in,
D => \int_d_i[19]_i_1_n_0\,
Q => \^q\(19),
R => \^sr\(0)
);
\int_d_i_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ap_clk,
CE => p_0_in,
D => \int_d_i[1]_i_1_n_0\,
Q => \^q\(1),
R => \^sr\(0)
);
\int_d_i_reg[20]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ap_clk,
CE => p_0_in,
D => \int_d_i[20]_i_1_n_0\,
Q => \^q\(20),
R => \^sr\(0)
);
\int_d_i_reg[21]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ap_clk,
CE => p_0_in,
D => \int_d_i[21]_i_1_n_0\,
Q => \^q\(21),
R => \^sr\(0)
);
\int_d_i_reg[22]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ap_clk,
CE => p_0_in,
D => \int_d_i[22]_i_1_n_0\,
Q => \^q\(22),
R => \^sr\(0)
);
\int_d_i_reg[23]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ap_clk,
CE => p_0_in,
D => \int_d_i[23]_i_1_n_0\,
Q => \^q\(23),
R => \^sr\(0)
);
\int_d_i_reg[24]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ap_clk,
CE => p_0_in,
D => \int_d_i[24]_i_1_n_0\,
Q => \^q\(24),
R => \^sr\(0)
);
\int_d_i_reg[25]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ap_clk,
CE => p_0_in,
D => \int_d_i[25]_i_1_n_0\,
Q => \^q\(25),
R => \^sr\(0)
);
\int_d_i_reg[26]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ap_clk,
CE => p_0_in,
D => \int_d_i[26]_i_1_n_0\,
Q => \^q\(26),
R => \^sr\(0)
);
\int_d_i_reg[27]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ap_clk,
CE => p_0_in,
D => \int_d_i[27]_i_1_n_0\,
Q => \^q\(27),
R => \^sr\(0)
);
\int_d_i_reg[28]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ap_clk,
CE => p_0_in,
D => \int_d_i[28]_i_1_n_0\,
Q => \^q\(28),
R => \^sr\(0)
);
\int_d_i_reg[29]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ap_clk,
CE => p_0_in,
D => \int_d_i[29]_i_1_n_0\,
Q => \^q\(29),
R => \^sr\(0)
);
\int_d_i_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ap_clk,
CE => p_0_in,
D => \int_d_i[2]_i_1_n_0\,
Q => \^q\(2),
R => \^sr\(0)
);
\int_d_i_reg[30]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ap_clk,
CE => p_0_in,
D => \int_d_i[30]_i_1_n_0\,
Q => \^q\(30),
R => \^sr\(0)
);
\int_d_i_reg[31]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ap_clk,
CE => p_0_in,
D => \int_d_i[31]_i_2_n_0\,
Q => \^q\(31),
R => \^sr\(0)
);
\int_d_i_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ap_clk,
CE => p_0_in,
D => \int_d_i[3]_i_1_n_0\,
Q => \^q\(3),
R => \^sr\(0)
);
\int_d_i_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ap_clk,
CE => p_0_in,
D => \int_d_i[4]_i_1_n_0\,
Q => \^q\(4),
R => \^sr\(0)
);
\int_d_i_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ap_clk,
CE => p_0_in,
D => \int_d_i[5]_i_1_n_0\,
Q => \^q\(5),
R => \^sr\(0)
);
\int_d_i_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ap_clk,
CE => p_0_in,
D => \int_d_i[6]_i_1_n_0\,
Q => \^q\(6),
R => \^sr\(0)
);
\int_d_i_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ap_clk,
CE => p_0_in,
D => \int_d_i[7]_i_1_n_0\,
Q => \^q\(7),
R => \^sr\(0)
);
\int_d_i_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ap_clk,
CE => p_0_in,
D => \int_d_i[8]_i_1_n_0\,
Q => \^q\(8),
R => \^sr\(0)
);
\int_d_i_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ap_clk,
CE => p_0_in,
D => \int_d_i[9]_i_1_n_0\,
Q => \^q\(9),
R => \^sr\(0)
);
int_d_o_ap_vld_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFBFFFAAAAAAAA"
)
port map (
I0 => \ap_CS_fsm_reg[2]\(0),
I1 => ar_hs,
I2 => s_axi_pointer_basic_io_ARADDR(3),
I3 => s_axi_pointer_basic_io_ARADDR(2),
I4 => int_d_o_ap_vld_i_2_n_0,
I5 => int_d_o_ap_vld,
O => int_d_o_ap_vld_i_1_n_0
);
int_d_o_ap_vld_i_2: unisim.vcomponents.LUT3
generic map(
INIT => X"FB"
)
port map (
I0 => s_axi_pointer_basic_io_ARADDR(1),
I1 => s_axi_pointer_basic_io_ARADDR(4),
I2 => s_axi_pointer_basic_io_ARADDR(0),
O => int_d_o_ap_vld_i_2_n_0
);
int_d_o_ap_vld_reg: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => '1',
D => int_d_o_ap_vld_i_1_n_0,
Q => int_d_o_ap_vld,
R => \^sr\(0)
);
\int_d_o_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ap_clk,
CE => \ap_CS_fsm_reg[2]\(0),
D => D(0),
Q => int_d_o(0),
R => \^sr\(0)
);
\int_d_o_reg[10]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ap_clk,
CE => \ap_CS_fsm_reg[2]\(0),
D => D(10),
Q => int_d_o(10),
R => \^sr\(0)
);
\int_d_o_reg[11]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ap_clk,
CE => \ap_CS_fsm_reg[2]\(0),
D => D(11),
Q => int_d_o(11),
R => \^sr\(0)
);
\int_d_o_reg[12]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ap_clk,
CE => \ap_CS_fsm_reg[2]\(0),
D => D(12),
Q => int_d_o(12),
R => \^sr\(0)
);
\int_d_o_reg[13]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ap_clk,
CE => \ap_CS_fsm_reg[2]\(0),
D => D(13),
Q => int_d_o(13),
R => \^sr\(0)
);
\int_d_o_reg[14]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ap_clk,
CE => \ap_CS_fsm_reg[2]\(0),
D => D(14),
Q => int_d_o(14),
R => \^sr\(0)
);
\int_d_o_reg[15]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ap_clk,
CE => \ap_CS_fsm_reg[2]\(0),
D => D(15),
Q => int_d_o(15),
R => \^sr\(0)
);
\int_d_o_reg[16]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ap_clk,
CE => \ap_CS_fsm_reg[2]\(0),
D => D(16),
Q => int_d_o(16),
R => \^sr\(0)
);
\int_d_o_reg[17]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ap_clk,
CE => \ap_CS_fsm_reg[2]\(0),
D => D(17),
Q => int_d_o(17),
R => \^sr\(0)
);
\int_d_o_reg[18]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ap_clk,
CE => \ap_CS_fsm_reg[2]\(0),
D => D(18),
Q => int_d_o(18),
R => \^sr\(0)
);
\int_d_o_reg[19]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ap_clk,
CE => \ap_CS_fsm_reg[2]\(0),
D => D(19),
Q => int_d_o(19),
R => \^sr\(0)
);
\int_d_o_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ap_clk,
CE => \ap_CS_fsm_reg[2]\(0),
D => D(1),
Q => int_d_o(1),
R => \^sr\(0)
);
\int_d_o_reg[20]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ap_clk,
CE => \ap_CS_fsm_reg[2]\(0),
D => D(20),
Q => int_d_o(20),
R => \^sr\(0)
);
\int_d_o_reg[21]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ap_clk,
CE => \ap_CS_fsm_reg[2]\(0),
D => D(21),
Q => int_d_o(21),
R => \^sr\(0)
);
\int_d_o_reg[22]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ap_clk,
CE => \ap_CS_fsm_reg[2]\(0),
D => D(22),
Q => int_d_o(22),
R => \^sr\(0)
);
\int_d_o_reg[23]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ap_clk,
CE => \ap_CS_fsm_reg[2]\(0),
D => D(23),
Q => int_d_o(23),
R => \^sr\(0)
);
\int_d_o_reg[24]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ap_clk,
CE => \ap_CS_fsm_reg[2]\(0),
D => D(24),
Q => int_d_o(24),
R => \^sr\(0)
);
\int_d_o_reg[25]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ap_clk,
CE => \ap_CS_fsm_reg[2]\(0),
D => D(25),
Q => int_d_o(25),
R => \^sr\(0)
);
\int_d_o_reg[26]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ap_clk,
CE => \ap_CS_fsm_reg[2]\(0),
D => D(26),
Q => int_d_o(26),
R => \^sr\(0)
);
\int_d_o_reg[27]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ap_clk,
CE => \ap_CS_fsm_reg[2]\(0),
D => D(27),
Q => int_d_o(27),
R => \^sr\(0)
);
\int_d_o_reg[28]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ap_clk,
CE => \ap_CS_fsm_reg[2]\(0),
D => D(28),
Q => int_d_o(28),
R => \^sr\(0)
);
\int_d_o_reg[29]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ap_clk,
CE => \ap_CS_fsm_reg[2]\(0),
D => D(29),
Q => int_d_o(29),
R => \^sr\(0)
);
\int_d_o_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ap_clk,
CE => \ap_CS_fsm_reg[2]\(0),
D => D(2),
Q => int_d_o(2),
R => \^sr\(0)
);
\int_d_o_reg[30]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ap_clk,
CE => \ap_CS_fsm_reg[2]\(0),
D => D(30),
Q => int_d_o(30),
R => \^sr\(0)
);
\int_d_o_reg[31]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ap_clk,
CE => \ap_CS_fsm_reg[2]\(0),
D => D(31),
Q => int_d_o(31),
R => \^sr\(0)
);
\int_d_o_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ap_clk,
CE => \ap_CS_fsm_reg[2]\(0),
D => D(3),
Q => int_d_o(3),
R => \^sr\(0)
);
\int_d_o_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ap_clk,
CE => \ap_CS_fsm_reg[2]\(0),
D => D(4),
Q => int_d_o(4),
R => \^sr\(0)
);
\int_d_o_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ap_clk,
CE => \ap_CS_fsm_reg[2]\(0),
D => D(5),
Q => int_d_o(5),
R => \^sr\(0)
);
\int_d_o_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ap_clk,
CE => \ap_CS_fsm_reg[2]\(0),
D => D(6),
Q => int_d_o(6),
R => \^sr\(0)
);
\int_d_o_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ap_clk,
CE => \ap_CS_fsm_reg[2]\(0),
D => D(7),
Q => int_d_o(7),
R => \^sr\(0)
);
\int_d_o_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ap_clk,
CE => \ap_CS_fsm_reg[2]\(0),
D => D(8),
Q => int_d_o(8),
R => \^sr\(0)
);
\int_d_o_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ap_clk,
CE => \ap_CS_fsm_reg[2]\(0),
D => D(9),
Q => int_d_o(9),
R => \^sr\(0)
);
\rdata[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0020FFFF00200000"
)
port map (
I0 => \rdata[0]_i_2_n_0\,
I1 => s_axi_pointer_basic_io_ARADDR(0),
I2 => s_axi_pointer_basic_io_ARADDR(4),
I3 => s_axi_pointer_basic_io_ARADDR(1),
I4 => ar_hs,
I5 => \^s_axi_pointer_basic_io_rdata\(0),
O => \rdata[0]_i_1_n_0\
);
\rdata[0]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"A0A0CFC0"
)
port map (
I0 => int_d_o_ap_vld,
I1 => int_d_o(0),
I2 => s_axi_pointer_basic_io_ARADDR(3),
I3 => \^q\(0),
I4 => s_axi_pointer_basic_io_ARADDR(2),
O => \rdata[0]_i_2_n_0\
);
\rdata[10]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => int_d_o(10),
I1 => s_axi_pointer_basic_io_ARADDR(3),
I2 => \^q\(10),
O => \rdata[10]_i_1_n_0\
);
\rdata[11]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => int_d_o(11),
I1 => s_axi_pointer_basic_io_ARADDR(3),
I2 => \^q\(11),
O => \rdata[11]_i_1_n_0\
);
\rdata[12]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => int_d_o(12),
I1 => s_axi_pointer_basic_io_ARADDR(3),
I2 => \^q\(12),
O => \rdata[12]_i_1_n_0\
);
\rdata[13]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => int_d_o(13),
I1 => s_axi_pointer_basic_io_ARADDR(3),
I2 => \^q\(13),
O => \rdata[13]_i_1_n_0\
);
\rdata[14]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => int_d_o(14),
I1 => s_axi_pointer_basic_io_ARADDR(3),
I2 => \^q\(14),
O => \rdata[14]_i_1_n_0\
);
\rdata[15]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => int_d_o(15),
I1 => s_axi_pointer_basic_io_ARADDR(3),
I2 => \^q\(15),
O => \rdata[15]_i_1_n_0\
);
\rdata[16]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => int_d_o(16),
I1 => s_axi_pointer_basic_io_ARADDR(3),
I2 => \^q\(16),
O => \rdata[16]_i_1_n_0\
);
\rdata[17]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => int_d_o(17),
I1 => s_axi_pointer_basic_io_ARADDR(3),
I2 => \^q\(17),
O => \rdata[17]_i_1_n_0\
);
\rdata[18]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => int_d_o(18),
I1 => s_axi_pointer_basic_io_ARADDR(3),
I2 => \^q\(18),
O => \rdata[18]_i_1_n_0\
);
\rdata[19]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => int_d_o(19),
I1 => s_axi_pointer_basic_io_ARADDR(3),
I2 => \^q\(19),
O => \rdata[19]_i_1_n_0\
);
\rdata[1]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => int_d_o(1),
I1 => s_axi_pointer_basic_io_ARADDR(3),
I2 => \^q\(1),
O => \rdata[1]_i_1_n_0\
);
\rdata[20]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => int_d_o(20),
I1 => s_axi_pointer_basic_io_ARADDR(3),
I2 => \^q\(20),
O => \rdata[20]_i_1_n_0\
);
\rdata[21]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => int_d_o(21),
I1 => s_axi_pointer_basic_io_ARADDR(3),
I2 => \^q\(21),
O => \rdata[21]_i_1_n_0\
);
\rdata[22]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => int_d_o(22),
I1 => s_axi_pointer_basic_io_ARADDR(3),
I2 => \^q\(22),
O => \rdata[22]_i_1_n_0\
);
\rdata[23]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => int_d_o(23),
I1 => s_axi_pointer_basic_io_ARADDR(3),
I2 => \^q\(23),
O => \rdata[23]_i_1_n_0\
);
\rdata[24]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => int_d_o(24),
I1 => s_axi_pointer_basic_io_ARADDR(3),
I2 => \^q\(24),
O => \rdata[24]_i_1_n_0\
);
\rdata[25]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => int_d_o(25),
I1 => s_axi_pointer_basic_io_ARADDR(3),
I2 => \^q\(25),
O => \rdata[25]_i_1_n_0\
);
\rdata[26]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => int_d_o(26),
I1 => s_axi_pointer_basic_io_ARADDR(3),
I2 => \^q\(26),
O => \rdata[26]_i_1_n_0\
);
\rdata[27]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => int_d_o(27),
I1 => s_axi_pointer_basic_io_ARADDR(3),
I2 => \^q\(27),
O => \rdata[27]_i_1_n_0\
);
\rdata[28]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => int_d_o(28),
I1 => s_axi_pointer_basic_io_ARADDR(3),
I2 => \^q\(28),
O => \rdata[28]_i_1_n_0\
);
\rdata[29]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => int_d_o(29),
I1 => s_axi_pointer_basic_io_ARADDR(3),
I2 => \^q\(29),
O => \rdata[29]_i_1_n_0\
);
\rdata[2]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => int_d_o(2),
I1 => s_axi_pointer_basic_io_ARADDR(3),
I2 => \^q\(2),
O => \rdata[2]_i_1_n_0\
);
\rdata[30]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => int_d_o(30),
I1 => s_axi_pointer_basic_io_ARADDR(3),
I2 => \^q\(30),
O => \rdata[30]_i_1_n_0\
);
\rdata[31]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFB000000000000"
)
port map (
I0 => s_axi_pointer_basic_io_ARADDR(1),
I1 => s_axi_pointer_basic_io_ARADDR(4),
I2 => s_axi_pointer_basic_io_ARADDR(0),
I3 => s_axi_pointer_basic_io_ARADDR(2),
I4 => s_axi_pointer_basic_io_ARVALID,
I5 => \^s_axi_pointer_basic_io_rvalid\(0),
O => \rdata[31]_i_1_n_0\
);
\rdata[31]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \^s_axi_pointer_basic_io_rvalid\(0),
I1 => s_axi_pointer_basic_io_ARVALID,
O => ar_hs
);
\rdata[31]_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => int_d_o(31),
I1 => s_axi_pointer_basic_io_ARADDR(3),
I2 => \^q\(31),
O => \rdata[31]_i_3_n_0\
);
\rdata[3]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => int_d_o(3),
I1 => s_axi_pointer_basic_io_ARADDR(3),
I2 => \^q\(3),
O => \rdata[3]_i_1_n_0\
);
\rdata[4]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => int_d_o(4),
I1 => s_axi_pointer_basic_io_ARADDR(3),
I2 => \^q\(4),
O => \rdata[4]_i_1_n_0\
);
\rdata[5]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => int_d_o(5),
I1 => s_axi_pointer_basic_io_ARADDR(3),
I2 => \^q\(5),
O => \rdata[5]_i_1_n_0\
);
\rdata[6]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => int_d_o(6),
I1 => s_axi_pointer_basic_io_ARADDR(3),
I2 => \^q\(6),
O => \rdata[6]_i_1_n_0\
);
\rdata[7]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => int_d_o(7),
I1 => s_axi_pointer_basic_io_ARADDR(3),
I2 => \^q\(7),
O => \rdata[7]_i_1_n_0\
);
\rdata[8]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => int_d_o(8),
I1 => s_axi_pointer_basic_io_ARADDR(3),
I2 => \^q\(8),
O => \rdata[8]_i_1_n_0\
);
\rdata[9]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => int_d_o(9),
I1 => s_axi_pointer_basic_io_ARADDR(3),
I2 => \^q\(9),
O => \rdata[9]_i_1_n_0\
);
\rdata_reg[0]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => '1',
D => \rdata[0]_i_1_n_0\,
Q => \^s_axi_pointer_basic_io_rdata\(0),
R => '0'
);
\rdata_reg[10]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => ar_hs,
D => \rdata[10]_i_1_n_0\,
Q => \^s_axi_pointer_basic_io_rdata\(10),
R => \rdata[31]_i_1_n_0\
);
\rdata_reg[11]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => ar_hs,
D => \rdata[11]_i_1_n_0\,
Q => \^s_axi_pointer_basic_io_rdata\(11),
R => \rdata[31]_i_1_n_0\
);
\rdata_reg[12]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => ar_hs,
D => \rdata[12]_i_1_n_0\,
Q => \^s_axi_pointer_basic_io_rdata\(12),
R => \rdata[31]_i_1_n_0\
);
\rdata_reg[13]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => ar_hs,
D => \rdata[13]_i_1_n_0\,
Q => \^s_axi_pointer_basic_io_rdata\(13),
R => \rdata[31]_i_1_n_0\
);
\rdata_reg[14]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => ar_hs,
D => \rdata[14]_i_1_n_0\,
Q => \^s_axi_pointer_basic_io_rdata\(14),
R => \rdata[31]_i_1_n_0\
);
\rdata_reg[15]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => ar_hs,
D => \rdata[15]_i_1_n_0\,
Q => \^s_axi_pointer_basic_io_rdata\(15),
R => \rdata[31]_i_1_n_0\
);
\rdata_reg[16]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => ar_hs,
D => \rdata[16]_i_1_n_0\,
Q => \^s_axi_pointer_basic_io_rdata\(16),
R => \rdata[31]_i_1_n_0\
);
\rdata_reg[17]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => ar_hs,
D => \rdata[17]_i_1_n_0\,
Q => \^s_axi_pointer_basic_io_rdata\(17),
R => \rdata[31]_i_1_n_0\
);
\rdata_reg[18]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => ar_hs,
D => \rdata[18]_i_1_n_0\,
Q => \^s_axi_pointer_basic_io_rdata\(18),
R => \rdata[31]_i_1_n_0\
);
\rdata_reg[19]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => ar_hs,
D => \rdata[19]_i_1_n_0\,
Q => \^s_axi_pointer_basic_io_rdata\(19),
R => \rdata[31]_i_1_n_0\
);
\rdata_reg[1]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => ar_hs,
D => \rdata[1]_i_1_n_0\,
Q => \^s_axi_pointer_basic_io_rdata\(1),
R => \rdata[31]_i_1_n_0\
);
\rdata_reg[20]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => ar_hs,
D => \rdata[20]_i_1_n_0\,
Q => \^s_axi_pointer_basic_io_rdata\(20),
R => \rdata[31]_i_1_n_0\
);
\rdata_reg[21]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => ar_hs,
D => \rdata[21]_i_1_n_0\,
Q => \^s_axi_pointer_basic_io_rdata\(21),
R => \rdata[31]_i_1_n_0\
);
\rdata_reg[22]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => ar_hs,
D => \rdata[22]_i_1_n_0\,
Q => \^s_axi_pointer_basic_io_rdata\(22),
R => \rdata[31]_i_1_n_0\
);
\rdata_reg[23]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => ar_hs,
D => \rdata[23]_i_1_n_0\,
Q => \^s_axi_pointer_basic_io_rdata\(23),
R => \rdata[31]_i_1_n_0\
);
\rdata_reg[24]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => ar_hs,
D => \rdata[24]_i_1_n_0\,
Q => \^s_axi_pointer_basic_io_rdata\(24),
R => \rdata[31]_i_1_n_0\
);
\rdata_reg[25]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => ar_hs,
D => \rdata[25]_i_1_n_0\,
Q => \^s_axi_pointer_basic_io_rdata\(25),
R => \rdata[31]_i_1_n_0\
);
\rdata_reg[26]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => ar_hs,
D => \rdata[26]_i_1_n_0\,
Q => \^s_axi_pointer_basic_io_rdata\(26),
R => \rdata[31]_i_1_n_0\
);
\rdata_reg[27]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => ar_hs,
D => \rdata[27]_i_1_n_0\,
Q => \^s_axi_pointer_basic_io_rdata\(27),
R => \rdata[31]_i_1_n_0\
);
\rdata_reg[28]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => ar_hs,
D => \rdata[28]_i_1_n_0\,
Q => \^s_axi_pointer_basic_io_rdata\(28),
R => \rdata[31]_i_1_n_0\
);
\rdata_reg[29]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => ar_hs,
D => \rdata[29]_i_1_n_0\,
Q => \^s_axi_pointer_basic_io_rdata\(29),
R => \rdata[31]_i_1_n_0\
);
\rdata_reg[2]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => ar_hs,
D => \rdata[2]_i_1_n_0\,
Q => \^s_axi_pointer_basic_io_rdata\(2),
R => \rdata[31]_i_1_n_0\
);
\rdata_reg[30]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => ar_hs,
D => \rdata[30]_i_1_n_0\,
Q => \^s_axi_pointer_basic_io_rdata\(30),
R => \rdata[31]_i_1_n_0\
);
\rdata_reg[31]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => ar_hs,
D => \rdata[31]_i_3_n_0\,
Q => \^s_axi_pointer_basic_io_rdata\(31),
R => \rdata[31]_i_1_n_0\
);
\rdata_reg[3]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => ar_hs,
D => \rdata[3]_i_1_n_0\,
Q => \^s_axi_pointer_basic_io_rdata\(3),
R => \rdata[31]_i_1_n_0\
);
\rdata_reg[4]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => ar_hs,
D => \rdata[4]_i_1_n_0\,
Q => \^s_axi_pointer_basic_io_rdata\(4),
R => \rdata[31]_i_1_n_0\
);
\rdata_reg[5]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => ar_hs,
D => \rdata[5]_i_1_n_0\,
Q => \^s_axi_pointer_basic_io_rdata\(5),
R => \rdata[31]_i_1_n_0\
);
\rdata_reg[6]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => ar_hs,
D => \rdata[6]_i_1_n_0\,
Q => \^s_axi_pointer_basic_io_rdata\(6),
R => \rdata[31]_i_1_n_0\
);
\rdata_reg[7]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => ar_hs,
D => \rdata[7]_i_1_n_0\,
Q => \^s_axi_pointer_basic_io_rdata\(7),
R => \rdata[31]_i_1_n_0\
);
\rdata_reg[8]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => ar_hs,
D => \rdata[8]_i_1_n_0\,
Q => \^s_axi_pointer_basic_io_rdata\(8),
R => \rdata[31]_i_1_n_0\
);
\rdata_reg[9]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => ar_hs,
D => \rdata[9]_i_1_n_0\,
Q => \^s_axi_pointer_basic_io_rdata\(9),
R => \rdata[31]_i_1_n_0\
);
\waddr[4]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => s_axi_pointer_basic_io_AWVALID,
I1 => \^out\(0),
O => waddr
);
\waddr_reg[0]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => waddr,
D => s_axi_pointer_basic_io_AWADDR(0),
Q => \waddr_reg_n_0_[0]\,
R => '0'
);
\waddr_reg[1]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => waddr,
D => s_axi_pointer_basic_io_AWADDR(1),
Q => \waddr_reg_n_0_[1]\,
R => '0'
);
\waddr_reg[2]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => waddr,
D => s_axi_pointer_basic_io_AWADDR(2),
Q => \waddr_reg_n_0_[2]\,
R => '0'
);
\waddr_reg[3]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => waddr,
D => s_axi_pointer_basic_io_AWADDR(3),
Q => \waddr_reg_n_0_[3]\,
R => '0'
);
\waddr_reg[4]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => waddr,
D => s_axi_pointer_basic_io_AWADDR(4),
Q => \waddr_reg_n_0_[4]\,
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_pointer_basic is
port (
ap_clk : in STD_LOGIC;
ap_rst_n : in STD_LOGIC;
ap_start : in STD_LOGIC;
ap_done : out STD_LOGIC;
ap_idle : out STD_LOGIC;
ap_ready : out STD_LOGIC;
s_axi_pointer_basic_io_AWVALID : in STD_LOGIC;
s_axi_pointer_basic_io_AWREADY : out STD_LOGIC;
s_axi_pointer_basic_io_AWADDR : in STD_LOGIC_VECTOR ( 4 downto 0 );
s_axi_pointer_basic_io_WVALID : in STD_LOGIC;
s_axi_pointer_basic_io_WREADY : out STD_LOGIC;
s_axi_pointer_basic_io_WDATA : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_pointer_basic_io_WSTRB : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_pointer_basic_io_ARVALID : in STD_LOGIC;
s_axi_pointer_basic_io_ARREADY : out STD_LOGIC;
s_axi_pointer_basic_io_ARADDR : in STD_LOGIC_VECTOR ( 4 downto 0 );
s_axi_pointer_basic_io_RVALID : out STD_LOGIC;
s_axi_pointer_basic_io_RREADY : in STD_LOGIC;
s_axi_pointer_basic_io_RDATA : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_pointer_basic_io_RRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_pointer_basic_io_BVALID : out STD_LOGIC;
s_axi_pointer_basic_io_BREADY : in STD_LOGIC;
s_axi_pointer_basic_io_BRESP : out STD_LOGIC_VECTOR ( 1 downto 0 )
);
attribute C_S_AXI_DATA_WIDTH : integer;
attribute C_S_AXI_DATA_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_pointer_basic : entity is 32;
attribute C_S_AXI_POINTER_BASIC_IO_ADDR_WIDTH : integer;
attribute C_S_AXI_POINTER_BASIC_IO_ADDR_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_pointer_basic : entity is 5;
attribute C_S_AXI_POINTER_BASIC_IO_DATA_WIDTH : integer;
attribute C_S_AXI_POINTER_BASIC_IO_DATA_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_pointer_basic : entity is 32;
attribute C_S_AXI_POINTER_BASIC_IO_WSTRB_WIDTH : integer;
attribute C_S_AXI_POINTER_BASIC_IO_WSTRB_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_pointer_basic : entity is 4;
attribute C_S_AXI_WSTRB_WIDTH : integer;
attribute C_S_AXI_WSTRB_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_pointer_basic : entity is 4;
attribute ap_ST_fsm_state1 : string;
attribute ap_ST_fsm_state1 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_pointer_basic : entity is "3'b001";
attribute ap_ST_fsm_state2 : string;
attribute ap_ST_fsm_state2 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_pointer_basic : entity is "3'b010";
attribute ap_ST_fsm_state3 : string;
attribute ap_ST_fsm_state3 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_pointer_basic : entity is "3'b100";
attribute hls_module : string;
attribute hls_module of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_pointer_basic : entity is "yes";
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_pointer_basic;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_pointer_basic is
signal \<const0>\ : STD_LOGIC;
signal \acc[0]_i_2_n_0\ : STD_LOGIC;
signal \acc[0]_i_3_n_0\ : STD_LOGIC;
signal \acc[0]_i_4_n_0\ : STD_LOGIC;
signal \acc[0]_i_5_n_0\ : STD_LOGIC;
signal \acc[12]_i_2_n_0\ : STD_LOGIC;
signal \acc[12]_i_3_n_0\ : STD_LOGIC;
signal \acc[12]_i_4_n_0\ : STD_LOGIC;
signal \acc[12]_i_5_n_0\ : STD_LOGIC;
signal \acc[16]_i_2_n_0\ : STD_LOGIC;
signal \acc[16]_i_3_n_0\ : STD_LOGIC;
signal \acc[16]_i_4_n_0\ : STD_LOGIC;
signal \acc[16]_i_5_n_0\ : STD_LOGIC;
signal \acc[20]_i_2_n_0\ : STD_LOGIC;
signal \acc[20]_i_3_n_0\ : STD_LOGIC;
signal \acc[20]_i_4_n_0\ : STD_LOGIC;
signal \acc[20]_i_5_n_0\ : STD_LOGIC;
signal \acc[24]_i_2_n_0\ : STD_LOGIC;
signal \acc[24]_i_3_n_0\ : STD_LOGIC;
signal \acc[24]_i_4_n_0\ : STD_LOGIC;
signal \acc[24]_i_5_n_0\ : STD_LOGIC;
signal \acc[28]_i_2_n_0\ : STD_LOGIC;
signal \acc[28]_i_3_n_0\ : STD_LOGIC;
signal \acc[28]_i_4_n_0\ : STD_LOGIC;
signal \acc[28]_i_5_n_0\ : STD_LOGIC;
signal \acc[4]_i_2_n_0\ : STD_LOGIC;
signal \acc[4]_i_3_n_0\ : STD_LOGIC;
signal \acc[4]_i_4_n_0\ : STD_LOGIC;
signal \acc[4]_i_5_n_0\ : STD_LOGIC;
signal \acc[8]_i_2_n_0\ : STD_LOGIC;
signal \acc[8]_i_3_n_0\ : STD_LOGIC;
signal \acc[8]_i_4_n_0\ : STD_LOGIC;
signal \acc[8]_i_5_n_0\ : STD_LOGIC;
signal acc_reg : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \acc_reg[0]_i_1_n_0\ : STD_LOGIC;
signal \acc_reg[0]_i_1_n_1\ : STD_LOGIC;
signal \acc_reg[0]_i_1_n_2\ : STD_LOGIC;
signal \acc_reg[0]_i_1_n_3\ : STD_LOGIC;
signal \acc_reg[0]_i_1_n_4\ : STD_LOGIC;
signal \acc_reg[0]_i_1_n_5\ : STD_LOGIC;
signal \acc_reg[0]_i_1_n_6\ : STD_LOGIC;
signal \acc_reg[0]_i_1_n_7\ : STD_LOGIC;
signal \acc_reg[12]_i_1_n_0\ : STD_LOGIC;
signal \acc_reg[12]_i_1_n_1\ : STD_LOGIC;
signal \acc_reg[12]_i_1_n_2\ : STD_LOGIC;
signal \acc_reg[12]_i_1_n_3\ : STD_LOGIC;
signal \acc_reg[12]_i_1_n_4\ : STD_LOGIC;
signal \acc_reg[12]_i_1_n_5\ : STD_LOGIC;
signal \acc_reg[12]_i_1_n_6\ : STD_LOGIC;
signal \acc_reg[12]_i_1_n_7\ : STD_LOGIC;
signal \acc_reg[16]_i_1_n_0\ : STD_LOGIC;
signal \acc_reg[16]_i_1_n_1\ : STD_LOGIC;
signal \acc_reg[16]_i_1_n_2\ : STD_LOGIC;
signal \acc_reg[16]_i_1_n_3\ : STD_LOGIC;
signal \acc_reg[16]_i_1_n_4\ : STD_LOGIC;
signal \acc_reg[16]_i_1_n_5\ : STD_LOGIC;
signal \acc_reg[16]_i_1_n_6\ : STD_LOGIC;
signal \acc_reg[16]_i_1_n_7\ : STD_LOGIC;
signal \acc_reg[20]_i_1_n_0\ : STD_LOGIC;
signal \acc_reg[20]_i_1_n_1\ : STD_LOGIC;
signal \acc_reg[20]_i_1_n_2\ : STD_LOGIC;
signal \acc_reg[20]_i_1_n_3\ : STD_LOGIC;
signal \acc_reg[20]_i_1_n_4\ : STD_LOGIC;
signal \acc_reg[20]_i_1_n_5\ : STD_LOGIC;
signal \acc_reg[20]_i_1_n_6\ : STD_LOGIC;
signal \acc_reg[20]_i_1_n_7\ : STD_LOGIC;
signal \acc_reg[24]_i_1_n_0\ : STD_LOGIC;
signal \acc_reg[24]_i_1_n_1\ : STD_LOGIC;
signal \acc_reg[24]_i_1_n_2\ : STD_LOGIC;
signal \acc_reg[24]_i_1_n_3\ : STD_LOGIC;
signal \acc_reg[24]_i_1_n_4\ : STD_LOGIC;
signal \acc_reg[24]_i_1_n_5\ : STD_LOGIC;
signal \acc_reg[24]_i_1_n_6\ : STD_LOGIC;
signal \acc_reg[24]_i_1_n_7\ : STD_LOGIC;
signal \acc_reg[28]_i_1_n_1\ : STD_LOGIC;
signal \acc_reg[28]_i_1_n_2\ : STD_LOGIC;
signal \acc_reg[28]_i_1_n_3\ : STD_LOGIC;
signal \acc_reg[28]_i_1_n_4\ : STD_LOGIC;
signal \acc_reg[28]_i_1_n_5\ : STD_LOGIC;
signal \acc_reg[28]_i_1_n_6\ : STD_LOGIC;
signal \acc_reg[28]_i_1_n_7\ : STD_LOGIC;
signal \acc_reg[4]_i_1_n_0\ : STD_LOGIC;
signal \acc_reg[4]_i_1_n_1\ : STD_LOGIC;
signal \acc_reg[4]_i_1_n_2\ : STD_LOGIC;
signal \acc_reg[4]_i_1_n_3\ : STD_LOGIC;
signal \acc_reg[4]_i_1_n_4\ : STD_LOGIC;
signal \acc_reg[4]_i_1_n_5\ : STD_LOGIC;
signal \acc_reg[4]_i_1_n_6\ : STD_LOGIC;
signal \acc_reg[4]_i_1_n_7\ : STD_LOGIC;
signal \acc_reg[8]_i_1_n_0\ : STD_LOGIC;
signal \acc_reg[8]_i_1_n_1\ : STD_LOGIC;
signal \acc_reg[8]_i_1_n_2\ : STD_LOGIC;
signal \acc_reg[8]_i_1_n_3\ : STD_LOGIC;
signal \acc_reg[8]_i_1_n_4\ : STD_LOGIC;
signal \acc_reg[8]_i_1_n_5\ : STD_LOGIC;
signal \acc_reg[8]_i_1_n_6\ : STD_LOGIC;
signal \acc_reg[8]_i_1_n_7\ : STD_LOGIC;
signal \ap_CS_fsm_reg_n_0_[0]\ : STD_LOGIC;
signal ap_CS_fsm_state2 : STD_LOGIC;
signal ap_NS_fsm : STD_LOGIC_VECTOR ( 1 downto 0 );
signal ap_NS_fsm1 : STD_LOGIC;
signal \^ap_done\ : STD_LOGIC;
signal ap_rst_n_inv : STD_LOGIC;
signal d_i : STD_LOGIC_VECTOR ( 31 downto 0 );
signal d_read_reg_52 : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \NLW_acc_reg[28]_i_1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \ap_CS_fsm[0]_i_1\ : label is "soft_lutpair31";
attribute FSM_ENCODING : string;
attribute FSM_ENCODING of \ap_CS_fsm_reg[0]\ : label is "none";
attribute FSM_ENCODING of \ap_CS_fsm_reg[1]\ : label is "none";
attribute FSM_ENCODING of \ap_CS_fsm_reg[2]\ : label is "none";
attribute SOFT_HLUTNM of ap_idle_INST_0 : label is "soft_lutpair31";
begin
ap_done <= \^ap_done\;
ap_ready <= \^ap_done\;
s_axi_pointer_basic_io_BRESP(1) <= \<const0>\;
s_axi_pointer_basic_io_BRESP(0) <= \<const0>\;
s_axi_pointer_basic_io_RRESP(1) <= \<const0>\;
s_axi_pointer_basic_io_RRESP(0) <= \<const0>\;
GND: unisim.vcomponents.GND
port map (
G => \<const0>\
);
\acc[0]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => d_read_reg_52(3),
I1 => acc_reg(3),
O => \acc[0]_i_2_n_0\
);
\acc[0]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => d_read_reg_52(2),
I1 => acc_reg(2),
O => \acc[0]_i_3_n_0\
);
\acc[0]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => d_read_reg_52(1),
I1 => acc_reg(1),
O => \acc[0]_i_4_n_0\
);
\acc[0]_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => d_read_reg_52(0),
I1 => acc_reg(0),
O => \acc[0]_i_5_n_0\
);
\acc[12]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => d_read_reg_52(15),
I1 => acc_reg(15),
O => \acc[12]_i_2_n_0\
);
\acc[12]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => d_read_reg_52(14),
I1 => acc_reg(14),
O => \acc[12]_i_3_n_0\
);
\acc[12]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => d_read_reg_52(13),
I1 => acc_reg(13),
O => \acc[12]_i_4_n_0\
);
\acc[12]_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => d_read_reg_52(12),
I1 => acc_reg(12),
O => \acc[12]_i_5_n_0\
);
\acc[16]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => d_read_reg_52(19),
I1 => acc_reg(19),
O => \acc[16]_i_2_n_0\
);
\acc[16]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => d_read_reg_52(18),
I1 => acc_reg(18),
O => \acc[16]_i_3_n_0\
);
\acc[16]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => d_read_reg_52(17),
I1 => acc_reg(17),
O => \acc[16]_i_4_n_0\
);
\acc[16]_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => d_read_reg_52(16),
I1 => acc_reg(16),
O => \acc[16]_i_5_n_0\
);
\acc[20]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => d_read_reg_52(23),
I1 => acc_reg(23),
O => \acc[20]_i_2_n_0\
);
\acc[20]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => d_read_reg_52(22),
I1 => acc_reg(22),
O => \acc[20]_i_3_n_0\
);
\acc[20]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => d_read_reg_52(21),
I1 => acc_reg(21),
O => \acc[20]_i_4_n_0\
);
\acc[20]_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => d_read_reg_52(20),
I1 => acc_reg(20),
O => \acc[20]_i_5_n_0\
);
\acc[24]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => d_read_reg_52(27),
I1 => acc_reg(27),
O => \acc[24]_i_2_n_0\
);
\acc[24]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => d_read_reg_52(26),
I1 => acc_reg(26),
O => \acc[24]_i_3_n_0\
);
\acc[24]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => d_read_reg_52(25),
I1 => acc_reg(25),
O => \acc[24]_i_4_n_0\
);
\acc[24]_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => d_read_reg_52(24),
I1 => acc_reg(24),
O => \acc[24]_i_5_n_0\
);
\acc[28]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => acc_reg(31),
I1 => d_read_reg_52(31),
O => \acc[28]_i_2_n_0\
);
\acc[28]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => d_read_reg_52(30),
I1 => acc_reg(30),
O => \acc[28]_i_3_n_0\
);
\acc[28]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => d_read_reg_52(29),
I1 => acc_reg(29),
O => \acc[28]_i_4_n_0\
);
\acc[28]_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => d_read_reg_52(28),
I1 => acc_reg(28),
O => \acc[28]_i_5_n_0\
);
\acc[4]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => d_read_reg_52(7),
I1 => acc_reg(7),
O => \acc[4]_i_2_n_0\
);
\acc[4]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => d_read_reg_52(6),
I1 => acc_reg(6),
O => \acc[4]_i_3_n_0\
);
\acc[4]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => d_read_reg_52(5),
I1 => acc_reg(5),
O => \acc[4]_i_4_n_0\
);
\acc[4]_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => d_read_reg_52(4),
I1 => acc_reg(4),
O => \acc[4]_i_5_n_0\
);
\acc[8]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => d_read_reg_52(11),
I1 => acc_reg(11),
O => \acc[8]_i_2_n_0\
);
\acc[8]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => d_read_reg_52(10),
I1 => acc_reg(10),
O => \acc[8]_i_3_n_0\
);
\acc[8]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => d_read_reg_52(9),
I1 => acc_reg(9),
O => \acc[8]_i_4_n_0\
);
\acc[8]_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => d_read_reg_52(8),
I1 => acc_reg(8),
O => \acc[8]_i_5_n_0\
);
\acc_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ap_clk,
CE => ap_CS_fsm_state2,
D => \acc_reg[0]_i_1_n_7\,
Q => acc_reg(0),
R => '0'
);
\acc_reg[0]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \acc_reg[0]_i_1_n_0\,
CO(2) => \acc_reg[0]_i_1_n_1\,
CO(1) => \acc_reg[0]_i_1_n_2\,
CO(0) => \acc_reg[0]_i_1_n_3\,
CYINIT => '0',
DI(3 downto 0) => d_read_reg_52(3 downto 0),
O(3) => \acc_reg[0]_i_1_n_4\,
O(2) => \acc_reg[0]_i_1_n_5\,
O(1) => \acc_reg[0]_i_1_n_6\,
O(0) => \acc_reg[0]_i_1_n_7\,
S(3) => \acc[0]_i_2_n_0\,
S(2) => \acc[0]_i_3_n_0\,
S(1) => \acc[0]_i_4_n_0\,
S(0) => \acc[0]_i_5_n_0\
);
\acc_reg[10]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ap_clk,
CE => ap_CS_fsm_state2,
D => \acc_reg[8]_i_1_n_5\,
Q => acc_reg(10),
R => '0'
);
\acc_reg[11]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ap_clk,
CE => ap_CS_fsm_state2,
D => \acc_reg[8]_i_1_n_4\,
Q => acc_reg(11),
R => '0'
);
\acc_reg[12]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ap_clk,
CE => ap_CS_fsm_state2,
D => \acc_reg[12]_i_1_n_7\,
Q => acc_reg(12),
R => '0'
);
\acc_reg[12]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \acc_reg[8]_i_1_n_0\,
CO(3) => \acc_reg[12]_i_1_n_0\,
CO(2) => \acc_reg[12]_i_1_n_1\,
CO(1) => \acc_reg[12]_i_1_n_2\,
CO(0) => \acc_reg[12]_i_1_n_3\,
CYINIT => '0',
DI(3 downto 0) => d_read_reg_52(15 downto 12),
O(3) => \acc_reg[12]_i_1_n_4\,
O(2) => \acc_reg[12]_i_1_n_5\,
O(1) => \acc_reg[12]_i_1_n_6\,
O(0) => \acc_reg[12]_i_1_n_7\,
S(3) => \acc[12]_i_2_n_0\,
S(2) => \acc[12]_i_3_n_0\,
S(1) => \acc[12]_i_4_n_0\,
S(0) => \acc[12]_i_5_n_0\
);
\acc_reg[13]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ap_clk,
CE => ap_CS_fsm_state2,
D => \acc_reg[12]_i_1_n_6\,
Q => acc_reg(13),
R => '0'
);
\acc_reg[14]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ap_clk,
CE => ap_CS_fsm_state2,
D => \acc_reg[12]_i_1_n_5\,
Q => acc_reg(14),
R => '0'
);
\acc_reg[15]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ap_clk,
CE => ap_CS_fsm_state2,
D => \acc_reg[12]_i_1_n_4\,
Q => acc_reg(15),
R => '0'
);
\acc_reg[16]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ap_clk,
CE => ap_CS_fsm_state2,
D => \acc_reg[16]_i_1_n_7\,
Q => acc_reg(16),
R => '0'
);
\acc_reg[16]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \acc_reg[12]_i_1_n_0\,
CO(3) => \acc_reg[16]_i_1_n_0\,
CO(2) => \acc_reg[16]_i_1_n_1\,
CO(1) => \acc_reg[16]_i_1_n_2\,
CO(0) => \acc_reg[16]_i_1_n_3\,
CYINIT => '0',
DI(3 downto 0) => d_read_reg_52(19 downto 16),
O(3) => \acc_reg[16]_i_1_n_4\,
O(2) => \acc_reg[16]_i_1_n_5\,
O(1) => \acc_reg[16]_i_1_n_6\,
O(0) => \acc_reg[16]_i_1_n_7\,
S(3) => \acc[16]_i_2_n_0\,
S(2) => \acc[16]_i_3_n_0\,
S(1) => \acc[16]_i_4_n_0\,
S(0) => \acc[16]_i_5_n_0\
);
\acc_reg[17]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ap_clk,
CE => ap_CS_fsm_state2,
D => \acc_reg[16]_i_1_n_6\,
Q => acc_reg(17),
R => '0'
);
\acc_reg[18]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ap_clk,
CE => ap_CS_fsm_state2,
D => \acc_reg[16]_i_1_n_5\,
Q => acc_reg(18),
R => '0'
);
\acc_reg[19]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ap_clk,
CE => ap_CS_fsm_state2,
D => \acc_reg[16]_i_1_n_4\,
Q => acc_reg(19),
R => '0'
);
\acc_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ap_clk,
CE => ap_CS_fsm_state2,
D => \acc_reg[0]_i_1_n_6\,
Q => acc_reg(1),
R => '0'
);
\acc_reg[20]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ap_clk,
CE => ap_CS_fsm_state2,
D => \acc_reg[20]_i_1_n_7\,
Q => acc_reg(20),
R => '0'
);
\acc_reg[20]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \acc_reg[16]_i_1_n_0\,
CO(3) => \acc_reg[20]_i_1_n_0\,
CO(2) => \acc_reg[20]_i_1_n_1\,
CO(1) => \acc_reg[20]_i_1_n_2\,
CO(0) => \acc_reg[20]_i_1_n_3\,
CYINIT => '0',
DI(3 downto 0) => d_read_reg_52(23 downto 20),
O(3) => \acc_reg[20]_i_1_n_4\,
O(2) => \acc_reg[20]_i_1_n_5\,
O(1) => \acc_reg[20]_i_1_n_6\,
O(0) => \acc_reg[20]_i_1_n_7\,
S(3) => \acc[20]_i_2_n_0\,
S(2) => \acc[20]_i_3_n_0\,
S(1) => \acc[20]_i_4_n_0\,
S(0) => \acc[20]_i_5_n_0\
);
\acc_reg[21]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ap_clk,
CE => ap_CS_fsm_state2,
D => \acc_reg[20]_i_1_n_6\,
Q => acc_reg(21),
R => '0'
);
\acc_reg[22]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ap_clk,
CE => ap_CS_fsm_state2,
D => \acc_reg[20]_i_1_n_5\,
Q => acc_reg(22),
R => '0'
);
\acc_reg[23]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ap_clk,
CE => ap_CS_fsm_state2,
D => \acc_reg[20]_i_1_n_4\,
Q => acc_reg(23),
R => '0'
);
\acc_reg[24]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ap_clk,
CE => ap_CS_fsm_state2,
D => \acc_reg[24]_i_1_n_7\,
Q => acc_reg(24),
R => '0'
);
\acc_reg[24]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \acc_reg[20]_i_1_n_0\,
CO(3) => \acc_reg[24]_i_1_n_0\,
CO(2) => \acc_reg[24]_i_1_n_1\,
CO(1) => \acc_reg[24]_i_1_n_2\,
CO(0) => \acc_reg[24]_i_1_n_3\,
CYINIT => '0',
DI(3 downto 0) => d_read_reg_52(27 downto 24),
O(3) => \acc_reg[24]_i_1_n_4\,
O(2) => \acc_reg[24]_i_1_n_5\,
O(1) => \acc_reg[24]_i_1_n_6\,
O(0) => \acc_reg[24]_i_1_n_7\,
S(3) => \acc[24]_i_2_n_0\,
S(2) => \acc[24]_i_3_n_0\,
S(1) => \acc[24]_i_4_n_0\,
S(0) => \acc[24]_i_5_n_0\
);
\acc_reg[25]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ap_clk,
CE => ap_CS_fsm_state2,
D => \acc_reg[24]_i_1_n_6\,
Q => acc_reg(25),
R => '0'
);
\acc_reg[26]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ap_clk,
CE => ap_CS_fsm_state2,
D => \acc_reg[24]_i_1_n_5\,
Q => acc_reg(26),
R => '0'
);
\acc_reg[27]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ap_clk,
CE => ap_CS_fsm_state2,
D => \acc_reg[24]_i_1_n_4\,
Q => acc_reg(27),
R => '0'
);
\acc_reg[28]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ap_clk,
CE => ap_CS_fsm_state2,
D => \acc_reg[28]_i_1_n_7\,
Q => acc_reg(28),
R => '0'
);
\acc_reg[28]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \acc_reg[24]_i_1_n_0\,
CO(3) => \NLW_acc_reg[28]_i_1_CO_UNCONNECTED\(3),
CO(2) => \acc_reg[28]_i_1_n_1\,
CO(1) => \acc_reg[28]_i_1_n_2\,
CO(0) => \acc_reg[28]_i_1_n_3\,
CYINIT => '0',
DI(3) => '0',
DI(2 downto 0) => d_read_reg_52(30 downto 28),
O(3) => \acc_reg[28]_i_1_n_4\,
O(2) => \acc_reg[28]_i_1_n_5\,
O(1) => \acc_reg[28]_i_1_n_6\,
O(0) => \acc_reg[28]_i_1_n_7\,
S(3) => \acc[28]_i_2_n_0\,
S(2) => \acc[28]_i_3_n_0\,
S(1) => \acc[28]_i_4_n_0\,
S(0) => \acc[28]_i_5_n_0\
);
\acc_reg[29]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ap_clk,
CE => ap_CS_fsm_state2,
D => \acc_reg[28]_i_1_n_6\,
Q => acc_reg(29),
R => '0'
);
\acc_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ap_clk,
CE => ap_CS_fsm_state2,
D => \acc_reg[0]_i_1_n_5\,
Q => acc_reg(2),
R => '0'
);
\acc_reg[30]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ap_clk,
CE => ap_CS_fsm_state2,
D => \acc_reg[28]_i_1_n_5\,
Q => acc_reg(30),
R => '0'
);
\acc_reg[31]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ap_clk,
CE => ap_CS_fsm_state2,
D => \acc_reg[28]_i_1_n_4\,
Q => acc_reg(31),
R => '0'
);
\acc_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ap_clk,
CE => ap_CS_fsm_state2,
D => \acc_reg[0]_i_1_n_4\,
Q => acc_reg(3),
R => '0'
);
\acc_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ap_clk,
CE => ap_CS_fsm_state2,
D => \acc_reg[4]_i_1_n_7\,
Q => acc_reg(4),
R => '0'
);
\acc_reg[4]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \acc_reg[0]_i_1_n_0\,
CO(3) => \acc_reg[4]_i_1_n_0\,
CO(2) => \acc_reg[4]_i_1_n_1\,
CO(1) => \acc_reg[4]_i_1_n_2\,
CO(0) => \acc_reg[4]_i_1_n_3\,
CYINIT => '0',
DI(3 downto 0) => d_read_reg_52(7 downto 4),
O(3) => \acc_reg[4]_i_1_n_4\,
O(2) => \acc_reg[4]_i_1_n_5\,
O(1) => \acc_reg[4]_i_1_n_6\,
O(0) => \acc_reg[4]_i_1_n_7\,
S(3) => \acc[4]_i_2_n_0\,
S(2) => \acc[4]_i_3_n_0\,
S(1) => \acc[4]_i_4_n_0\,
S(0) => \acc[4]_i_5_n_0\
);
\acc_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ap_clk,
CE => ap_CS_fsm_state2,
D => \acc_reg[4]_i_1_n_6\,
Q => acc_reg(5),
R => '0'
);
\acc_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ap_clk,
CE => ap_CS_fsm_state2,
D => \acc_reg[4]_i_1_n_5\,
Q => acc_reg(6),
R => '0'
);
\acc_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ap_clk,
CE => ap_CS_fsm_state2,
D => \acc_reg[4]_i_1_n_4\,
Q => acc_reg(7),
R => '0'
);
\acc_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ap_clk,
CE => ap_CS_fsm_state2,
D => \acc_reg[8]_i_1_n_7\,
Q => acc_reg(8),
R => '0'
);
\acc_reg[8]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \acc_reg[4]_i_1_n_0\,
CO(3) => \acc_reg[8]_i_1_n_0\,
CO(2) => \acc_reg[8]_i_1_n_1\,
CO(1) => \acc_reg[8]_i_1_n_2\,
CO(0) => \acc_reg[8]_i_1_n_3\,
CYINIT => '0',
DI(3 downto 0) => d_read_reg_52(11 downto 8),
O(3) => \acc_reg[8]_i_1_n_4\,
O(2) => \acc_reg[8]_i_1_n_5\,
O(1) => \acc_reg[8]_i_1_n_6\,
O(0) => \acc_reg[8]_i_1_n_7\,
S(3) => \acc[8]_i_2_n_0\,
S(2) => \acc[8]_i_3_n_0\,
S(1) => \acc[8]_i_4_n_0\,
S(0) => \acc[8]_i_5_n_0\
);
\acc_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ap_clk,
CE => ap_CS_fsm_state2,
D => \acc_reg[8]_i_1_n_6\,
Q => acc_reg(9),
R => '0'
);
\ap_CS_fsm[0]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"4555"
)
port map (
I0 => ap_CS_fsm_state2,
I1 => \^ap_done\,
I2 => ap_start,
I3 => \ap_CS_fsm_reg_n_0_[0]\,
O => ap_NS_fsm(0)
);
\ap_CS_fsm[1]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"0040"
)
port map (
I0 => \^ap_done\,
I1 => ap_start,
I2 => \ap_CS_fsm_reg_n_0_[0]\,
I3 => ap_CS_fsm_state2,
O => ap_NS_fsm(1)
);
\ap_CS_fsm_reg[0]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => ap_clk,
CE => '1',
D => ap_NS_fsm(0),
Q => \ap_CS_fsm_reg_n_0_[0]\,
S => ap_rst_n_inv
);
\ap_CS_fsm_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ap_clk,
CE => '1',
D => ap_NS_fsm(1),
Q => ap_CS_fsm_state2,
R => ap_rst_n_inv
);
\ap_CS_fsm_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ap_clk,
CE => '1',
D => ap_CS_fsm_state2,
Q => \^ap_done\,
R => ap_rst_n_inv
);
ap_idle_INST_0: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \ap_CS_fsm_reg_n_0_[0]\,
I1 => ap_start,
O => ap_idle
);
\d_read_reg_52[31]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => ap_start,
I1 => \ap_CS_fsm_reg_n_0_[0]\,
O => ap_NS_fsm1
);
\d_read_reg_52_reg[0]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => ap_NS_fsm1,
D => d_i(0),
Q => d_read_reg_52(0),
R => '0'
);
\d_read_reg_52_reg[10]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => ap_NS_fsm1,
D => d_i(10),
Q => d_read_reg_52(10),
R => '0'
);
\d_read_reg_52_reg[11]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => ap_NS_fsm1,
D => d_i(11),
Q => d_read_reg_52(11),
R => '0'
);
\d_read_reg_52_reg[12]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => ap_NS_fsm1,
D => d_i(12),
Q => d_read_reg_52(12),
R => '0'
);
\d_read_reg_52_reg[13]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => ap_NS_fsm1,
D => d_i(13),
Q => d_read_reg_52(13),
R => '0'
);
\d_read_reg_52_reg[14]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => ap_NS_fsm1,
D => d_i(14),
Q => d_read_reg_52(14),
R => '0'
);
\d_read_reg_52_reg[15]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => ap_NS_fsm1,
D => d_i(15),
Q => d_read_reg_52(15),
R => '0'
);
\d_read_reg_52_reg[16]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => ap_NS_fsm1,
D => d_i(16),
Q => d_read_reg_52(16),
R => '0'
);
\d_read_reg_52_reg[17]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => ap_NS_fsm1,
D => d_i(17),
Q => d_read_reg_52(17),
R => '0'
);
\d_read_reg_52_reg[18]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => ap_NS_fsm1,
D => d_i(18),
Q => d_read_reg_52(18),
R => '0'
);
\d_read_reg_52_reg[19]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => ap_NS_fsm1,
D => d_i(19),
Q => d_read_reg_52(19),
R => '0'
);
\d_read_reg_52_reg[1]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => ap_NS_fsm1,
D => d_i(1),
Q => d_read_reg_52(1),
R => '0'
);
\d_read_reg_52_reg[20]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => ap_NS_fsm1,
D => d_i(20),
Q => d_read_reg_52(20),
R => '0'
);
\d_read_reg_52_reg[21]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => ap_NS_fsm1,
D => d_i(21),
Q => d_read_reg_52(21),
R => '0'
);
\d_read_reg_52_reg[22]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => ap_NS_fsm1,
D => d_i(22),
Q => d_read_reg_52(22),
R => '0'
);
\d_read_reg_52_reg[23]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => ap_NS_fsm1,
D => d_i(23),
Q => d_read_reg_52(23),
R => '0'
);
\d_read_reg_52_reg[24]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => ap_NS_fsm1,
D => d_i(24),
Q => d_read_reg_52(24),
R => '0'
);
\d_read_reg_52_reg[25]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => ap_NS_fsm1,
D => d_i(25),
Q => d_read_reg_52(25),
R => '0'
);
\d_read_reg_52_reg[26]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => ap_NS_fsm1,
D => d_i(26),
Q => d_read_reg_52(26),
R => '0'
);
\d_read_reg_52_reg[27]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => ap_NS_fsm1,
D => d_i(27),
Q => d_read_reg_52(27),
R => '0'
);
\d_read_reg_52_reg[28]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => ap_NS_fsm1,
D => d_i(28),
Q => d_read_reg_52(28),
R => '0'
);
\d_read_reg_52_reg[29]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => ap_NS_fsm1,
D => d_i(29),
Q => d_read_reg_52(29),
R => '0'
);
\d_read_reg_52_reg[2]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => ap_NS_fsm1,
D => d_i(2),
Q => d_read_reg_52(2),
R => '0'
);
\d_read_reg_52_reg[30]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => ap_NS_fsm1,
D => d_i(30),
Q => d_read_reg_52(30),
R => '0'
);
\d_read_reg_52_reg[31]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => ap_NS_fsm1,
D => d_i(31),
Q => d_read_reg_52(31),
R => '0'
);
\d_read_reg_52_reg[3]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => ap_NS_fsm1,
D => d_i(3),
Q => d_read_reg_52(3),
R => '0'
);
\d_read_reg_52_reg[4]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => ap_NS_fsm1,
D => d_i(4),
Q => d_read_reg_52(4),
R => '0'
);
\d_read_reg_52_reg[5]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => ap_NS_fsm1,
D => d_i(5),
Q => d_read_reg_52(5),
R => '0'
);
\d_read_reg_52_reg[6]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => ap_NS_fsm1,
D => d_i(6),
Q => d_read_reg_52(6),
R => '0'
);
\d_read_reg_52_reg[7]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => ap_NS_fsm1,
D => d_i(7),
Q => d_read_reg_52(7),
R => '0'
);
\d_read_reg_52_reg[8]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => ap_NS_fsm1,
D => d_i(8),
Q => d_read_reg_52(8),
R => '0'
);
\d_read_reg_52_reg[9]\: unisim.vcomponents.FDRE
port map (
C => ap_clk,
CE => ap_NS_fsm1,
D => d_i(9),
Q => d_read_reg_52(9),
R => '0'
);
pointer_basic_pointer_basic_io_s_axi_U: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_pointer_basic_pointer_basic_io_s_axi
port map (
D(31 downto 0) => acc_reg(31 downto 0),
Q(31 downto 0) => d_i(31 downto 0),
SR(0) => ap_rst_n_inv,
\ap_CS_fsm_reg[2]\(0) => \^ap_done\,
ap_clk => ap_clk,
ap_rst_n => ap_rst_n,
\out\(2) => s_axi_pointer_basic_io_BVALID,
\out\(1) => s_axi_pointer_basic_io_WREADY,
\out\(0) => s_axi_pointer_basic_io_AWREADY,
s_axi_pointer_basic_io_ARADDR(4 downto 0) => s_axi_pointer_basic_io_ARADDR(4 downto 0),
s_axi_pointer_basic_io_ARVALID => s_axi_pointer_basic_io_ARVALID,
s_axi_pointer_basic_io_AWADDR(4 downto 0) => s_axi_pointer_basic_io_AWADDR(4 downto 0),
s_axi_pointer_basic_io_AWVALID => s_axi_pointer_basic_io_AWVALID,
s_axi_pointer_basic_io_BREADY => s_axi_pointer_basic_io_BREADY,
s_axi_pointer_basic_io_RDATA(31 downto 0) => s_axi_pointer_basic_io_RDATA(31 downto 0),
s_axi_pointer_basic_io_RREADY => s_axi_pointer_basic_io_RREADY,
s_axi_pointer_basic_io_RVALID(1) => s_axi_pointer_basic_io_RVALID,
s_axi_pointer_basic_io_RVALID(0) => s_axi_pointer_basic_io_ARREADY,
s_axi_pointer_basic_io_WDATA(31 downto 0) => s_axi_pointer_basic_io_WDATA(31 downto 0),
s_axi_pointer_basic_io_WSTRB(3 downto 0) => s_axi_pointer_basic_io_WSTRB(3 downto 0),
s_axi_pointer_basic_io_WVALID => s_axi_pointer_basic_io_WVALID
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
port (
s_axi_pointer_basic_io_AWADDR : in STD_LOGIC_VECTOR ( 4 downto 0 );
s_axi_pointer_basic_io_AWVALID : in STD_LOGIC;
s_axi_pointer_basic_io_AWREADY : out STD_LOGIC;
s_axi_pointer_basic_io_WDATA : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_pointer_basic_io_WSTRB : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_pointer_basic_io_WVALID : in STD_LOGIC;
s_axi_pointer_basic_io_WREADY : out STD_LOGIC;
s_axi_pointer_basic_io_BRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_pointer_basic_io_BVALID : out STD_LOGIC;
s_axi_pointer_basic_io_BREADY : in STD_LOGIC;
s_axi_pointer_basic_io_ARADDR : in STD_LOGIC_VECTOR ( 4 downto 0 );
s_axi_pointer_basic_io_ARVALID : in STD_LOGIC;
s_axi_pointer_basic_io_ARREADY : out STD_LOGIC;
s_axi_pointer_basic_io_RDATA : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_pointer_basic_io_RRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_pointer_basic_io_RVALID : out STD_LOGIC;
s_axi_pointer_basic_io_RREADY : in STD_LOGIC;
ap_clk : in STD_LOGIC;
ap_rst_n : in STD_LOGIC;
ap_start : in STD_LOGIC;
ap_done : out STD_LOGIC;
ap_idle : out STD_LOGIC;
ap_ready : out STD_LOGIC
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is true;
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "design_1_pointer_basic_0_0,pointer_basic,{}";
attribute DowngradeIPIdentifiedWarnings : string;
attribute DowngradeIPIdentifiedWarnings of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "yes";
attribute IP_DEFINITION_SOURCE : string;
attribute IP_DEFINITION_SOURCE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "HLS";
attribute X_CORE_INFO : string;
attribute X_CORE_INFO of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "pointer_basic,Vivado 2018.2";
attribute hls_module : string;
attribute hls_module of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "yes";
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
attribute C_S_AXI_DATA_WIDTH : integer;
attribute C_S_AXI_DATA_WIDTH of inst : label is 32;
attribute C_S_AXI_POINTER_BASIC_IO_ADDR_WIDTH : integer;
attribute C_S_AXI_POINTER_BASIC_IO_ADDR_WIDTH of inst : label is 5;
attribute C_S_AXI_POINTER_BASIC_IO_DATA_WIDTH : integer;
attribute C_S_AXI_POINTER_BASIC_IO_DATA_WIDTH of inst : label is 32;
attribute C_S_AXI_POINTER_BASIC_IO_WSTRB_WIDTH : integer;
attribute C_S_AXI_POINTER_BASIC_IO_WSTRB_WIDTH of inst : label is 4;
attribute C_S_AXI_WSTRB_WIDTH : integer;
attribute C_S_AXI_WSTRB_WIDTH of inst : label is 4;
attribute ap_ST_fsm_state1 : string;
attribute ap_ST_fsm_state1 of inst : label is "3'b001";
attribute ap_ST_fsm_state2 : string;
attribute ap_ST_fsm_state2 of inst : label is "3'b010";
attribute ap_ST_fsm_state3 : string;
attribute ap_ST_fsm_state3 of inst : label is "3'b100";
attribute X_INTERFACE_INFO : string;
attribute X_INTERFACE_INFO of ap_clk : signal is "xilinx.com:signal:clock:1.0 ap_clk CLK";
attribute X_INTERFACE_PARAMETER : string;
attribute X_INTERFACE_PARAMETER of ap_clk : signal is "XIL_INTERFACENAME ap_clk, ASSOCIATED_BUSIF s_axi_pointer_basic_io, ASSOCIATED_RESET ap_rst_n, LAYERED_METADATA xilinx.com:interface:datatypes:1.0 {CLK {datatype {name {attribs {resolve_type immediate dependency {} format string minimum {} maximum {}} value {}} bitwidth {attribs {resolve_type immediate dependency {} format long minimum {} maximum {}} value 1} bitoffset {attribs {resolve_type immediate dependency {} format long minimum {} maximum {}} value 0}}}}, FREQ_HZ 50000000, PHASE 0.000, CLK_DOMAIN design_1_processing_system7_0_0_FCLK_CLK0";
attribute X_INTERFACE_INFO of ap_done : signal is "xilinx.com:interface:acc_handshake:1.0 ap_ctrl done";
attribute X_INTERFACE_INFO of ap_idle : signal is "xilinx.com:interface:acc_handshake:1.0 ap_ctrl idle";
attribute X_INTERFACE_INFO of ap_ready : signal is "xilinx.com:interface:acc_handshake:1.0 ap_ctrl ready";
attribute X_INTERFACE_PARAMETER of ap_ready : signal is "XIL_INTERFACENAME ap_ctrl, LAYERED_METADATA xilinx.com:interface:datatypes:1.0 {start {datatype {name {attribs {resolve_type immediate dependency {} format string minimum {} maximum {}} value {}} bitwidth {attribs {resolve_type immediate dependency {} format long minimum {} maximum {}} value 1} bitoffset {attribs {resolve_type immediate dependency {} format long minimum {} maximum {}} value 0}}} done {datatype {name {attribs {resolve_type immediate dependency {} format string minimum {} maximum {}} value {}} bitwidth {attribs {resolve_type immediate dependency {} format long minimum {} maximum {}} value 1} bitoffset {attribs {resolve_type immediate dependency {} format long minimum {} maximum {}} value 0}}} idle {datatype {name {attribs {resolve_type immediate dependency {} format string minimum {} maximum {}} value {}} bitwidth {attribs {resolve_type immediate dependency {} format long minimum {} maximum {}} value 1} bitoffset {attribs {resolve_type immediate dependency {} format long minimum {} maximum {}} value 0}}} ready {datatype {name {attribs {resolve_type immediate dependency {} format string minimum {} maximum {}} value {}} bitwidth {attribs {resolve_type immediate dependency {} format long minimum {} maximum {}} value 1} bitoffset {attribs {resolve_type immediate dependency {} format long minimum {} maximum {}} value 0}}}}";
attribute X_INTERFACE_INFO of ap_rst_n : signal is "xilinx.com:signal:reset:1.0 ap_rst_n RST";
attribute X_INTERFACE_PARAMETER of ap_rst_n : signal is "XIL_INTERFACENAME ap_rst_n, POLARITY ACTIVE_LOW, LAYERED_METADATA xilinx.com:interface:datatypes:1.0 {RST {datatype {name {attribs {resolve_type immediate dependency {} format string minimum {} maximum {}} value {}} bitwidth {attribs {resolve_type immediate dependency {} format long minimum {} maximum {}} value 1} bitoffset {attribs {resolve_type immediate dependency {} format long minimum {} maximum {}} value 0}}}}";
attribute X_INTERFACE_INFO of ap_start : signal is "xilinx.com:interface:acc_handshake:1.0 ap_ctrl start";
attribute X_INTERFACE_INFO of s_axi_pointer_basic_io_ARREADY : signal is "xilinx.com:interface:aximm:1.0 s_axi_pointer_basic_io ARREADY";
attribute X_INTERFACE_INFO of s_axi_pointer_basic_io_ARVALID : signal is "xilinx.com:interface:aximm:1.0 s_axi_pointer_basic_io ARVALID";
attribute X_INTERFACE_INFO of s_axi_pointer_basic_io_AWREADY : signal is "xilinx.com:interface:aximm:1.0 s_axi_pointer_basic_io AWREADY";
attribute X_INTERFACE_INFO of s_axi_pointer_basic_io_AWVALID : signal is "xilinx.com:interface:aximm:1.0 s_axi_pointer_basic_io AWVALID";
attribute X_INTERFACE_INFO of s_axi_pointer_basic_io_BREADY : signal is "xilinx.com:interface:aximm:1.0 s_axi_pointer_basic_io BREADY";
attribute X_INTERFACE_INFO of s_axi_pointer_basic_io_BVALID : signal is "xilinx.com:interface:aximm:1.0 s_axi_pointer_basic_io BVALID";
attribute X_INTERFACE_INFO of s_axi_pointer_basic_io_RREADY : signal is "xilinx.com:interface:aximm:1.0 s_axi_pointer_basic_io RREADY";
attribute X_INTERFACE_PARAMETER of s_axi_pointer_basic_io_RREADY : signal is "XIL_INTERFACENAME s_axi_pointer_basic_io, ADDR_WIDTH 5, DATA_WIDTH 32, PROTOCOL AXI4LITE, READ_WRITE_MODE READ_WRITE, LAYERED_METADATA xilinx.com:interface:datatypes:1.0 {CLK {datatype {name {attribs {resolve_type immediate dependency {} format string minimum {} maximum {}} value {}} bitwidth {attribs {resolve_type immediate dependency {} format long minimum {} maximum {}} value 1} bitoffset {attribs {resolve_type immediate dependency {} format long minimum {} maximum {}} value 0}}}}, FREQ_HZ 50000000, ID_WIDTH 0, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 0, HAS_CACHE 0, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 1, NUM_WRITE_OUTSTANDING 1, MAX_BURST_LENGTH 1, PHASE 0.000, CLK_DOMAIN design_1_processing_system7_0_0_FCLK_CLK0, NUM_READ_THREADS 4, NUM_WRITE_THREADS 4, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0";
attribute X_INTERFACE_INFO of s_axi_pointer_basic_io_RVALID : signal is "xilinx.com:interface:aximm:1.0 s_axi_pointer_basic_io RVALID";
attribute X_INTERFACE_INFO of s_axi_pointer_basic_io_WREADY : signal is "xilinx.com:interface:aximm:1.0 s_axi_pointer_basic_io WREADY";
attribute X_INTERFACE_INFO of s_axi_pointer_basic_io_WVALID : signal is "xilinx.com:interface:aximm:1.0 s_axi_pointer_basic_io WVALID";
attribute X_INTERFACE_INFO of s_axi_pointer_basic_io_ARADDR : signal is "xilinx.com:interface:aximm:1.0 s_axi_pointer_basic_io ARADDR";
attribute X_INTERFACE_INFO of s_axi_pointer_basic_io_AWADDR : signal is "xilinx.com:interface:aximm:1.0 s_axi_pointer_basic_io AWADDR";
attribute X_INTERFACE_INFO of s_axi_pointer_basic_io_BRESP : signal is "xilinx.com:interface:aximm:1.0 s_axi_pointer_basic_io BRESP";
attribute X_INTERFACE_INFO of s_axi_pointer_basic_io_RDATA : signal is "xilinx.com:interface:aximm:1.0 s_axi_pointer_basic_io RDATA";
attribute X_INTERFACE_INFO of s_axi_pointer_basic_io_RRESP : signal is "xilinx.com:interface:aximm:1.0 s_axi_pointer_basic_io RRESP";
attribute X_INTERFACE_INFO of s_axi_pointer_basic_io_WDATA : signal is "xilinx.com:interface:aximm:1.0 s_axi_pointer_basic_io WDATA";
attribute X_INTERFACE_INFO of s_axi_pointer_basic_io_WSTRB : signal is "xilinx.com:interface:aximm:1.0 s_axi_pointer_basic_io WSTRB";
begin
inst: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_pointer_basic
port map (
ap_clk => ap_clk,
ap_done => ap_done,
ap_idle => ap_idle,
ap_ready => ap_ready,
ap_rst_n => ap_rst_n,
ap_start => ap_start,
s_axi_pointer_basic_io_ARADDR(4 downto 0) => s_axi_pointer_basic_io_ARADDR(4 downto 0),
s_axi_pointer_basic_io_ARREADY => s_axi_pointer_basic_io_ARREADY,
s_axi_pointer_basic_io_ARVALID => s_axi_pointer_basic_io_ARVALID,
s_axi_pointer_basic_io_AWADDR(4 downto 0) => s_axi_pointer_basic_io_AWADDR(4 downto 0),
s_axi_pointer_basic_io_AWREADY => s_axi_pointer_basic_io_AWREADY,
s_axi_pointer_basic_io_AWVALID => s_axi_pointer_basic_io_AWVALID,
s_axi_pointer_basic_io_BREADY => s_axi_pointer_basic_io_BREADY,
s_axi_pointer_basic_io_BRESP(1 downto 0) => s_axi_pointer_basic_io_BRESP(1 downto 0),
s_axi_pointer_basic_io_BVALID => s_axi_pointer_basic_io_BVALID,
s_axi_pointer_basic_io_RDATA(31 downto 0) => s_axi_pointer_basic_io_RDATA(31 downto 0),
s_axi_pointer_basic_io_RREADY => s_axi_pointer_basic_io_RREADY,
s_axi_pointer_basic_io_RRESP(1 downto 0) => s_axi_pointer_basic_io_RRESP(1 downto 0),
s_axi_pointer_basic_io_RVALID => s_axi_pointer_basic_io_RVALID,
s_axi_pointer_basic_io_WDATA(31 downto 0) => s_axi_pointer_basic_io_WDATA(31 downto 0),
s_axi_pointer_basic_io_WREADY => s_axi_pointer_basic_io_WREADY,
s_axi_pointer_basic_io_WSTRB(3 downto 0) => s_axi_pointer_basic_io_WSTRB(3 downto 0),
s_axi_pointer_basic_io_WVALID => s_axi_pointer_basic_io_WVALID
);
end STRUCTURE;
| mit | 9e1af0e94e97760c18136047fe4be37d | 0.51479 | 2.591919 | false | false | false | false |
elionne/easy_bitcoin_wallet | testbench_vowels.vhdl | 1 | 5,679 |
library IEEE;
use IEEE.std_logic_1164.all;
entity testbench_vowels is
end testbench_vowels;
architecture testbench_arch_vowels of testbench_vowels is
signal clk : std_logic;
signal enable : std_logic;
signal length_in, length_out : natural;
signal reset : std_logic;
signal load_index : natural;
signal char : character;
signal finished : std_logic;
component vowels
port (
length_in : in natural;
length_out : out natural;
enable : in std_logic;
reset : in std_logic;
load_index : in natural;
current_index: out natural;
clk : in std_logic;
char : out character := 'a';
finished : out std_logic := '1'
);
end component;
begin
list_vowels : vowels port map (
length_in => length_in,
length_out => length_out,
enable => enable,
reset => reset,
load_index => load_index,
clk => clk,
char => char,
finished => finished
);
length_in <= length_out;
process
begin
-- --------------------
clk <= transport '0';
enable <= transport '1';
reset <= transport '0';
-- --------------------
WAIT FOR 110 ns;
clk <= transport '1';
-- --------------------
WAIT FOR 10 ns;
clk <= transport '0';
-- --------------------
WAIT FOR 10 ns;
clk <= transport '1';
-- --------------------
WAIT FOR 10 ns;
clk <= transport '0';
-- --------------------
WAIT FOR 10 ns;
clk <= transport '1';
-- --------------------
WAIT FOR 10 ns;
clk <= transport '0';
-- --------------------
WAIT FOR 10 ns;
clk <= transport '1';
enable <= transport '0';
-- --------------------
WAIT FOR 10 ns;
clk <= transport '0';
-- --------------------
WAIT FOR 10 ns;
clk <= transport '1';
-- --------------------
WAIT FOR 10 ns;
clk <= transport '0';
-- --------------------
WAIT FOR 10 ns;
clk <= transport '1';
-- --------------------
WAIT FOR 10 ns;
clk <= transport '0';
-- --------------------
WAIT FOR 10 ns;
clk <= transport '1';
-- --------------------
WAIT FOR 10 ns;
clk <= transport '0';
-- --------------------
WAIT FOR 10 ns;
clk <= transport '1';
enable <= transport '1';
-- --------------------
WAIT FOR 10 ns;
clk <= transport '0';
-- --------------------
WAIT FOR 10 ns;
clk <= transport '1';
-- --------------------
WAIT FOR 10 ns;
clk <= transport '0';
assert char = 'u';
-- --------------------
WAIT FOR 10 ns;
clk <= transport '1';
-- --------------------
WAIT FOR 10 ns;
clk <= transport '0';
assert char = 'u';
assert finished = '1';
-- --------------------
WAIT FOR 10 ns;
clk <= transport '1';
-- --------------------
WAIT FOR 10 ns;
clk <= transport '0';
-- --------------------
WAIT FOR 10 ns;
clk <= transport '1';
-- --------------------
WAIT FOR 10 ns;
clk <= transport '0';
reset <= transport '1';
-- --------------------
WAIT FOR 10 ns;
clk <= transport '1';
-- --------------------
WAIT FOR 10 ns;
clk <= transport '0';
reset <= transport '0';
assert finished = '0';
assert char = 'a';
-- --------------------
WAIT FOR 10 ns;
clk <= transport '1';
-- --------------------
WAIT FOR 10 ns;
clk <= transport '0';
-- --------------------
WAIT FOR 10 ns;
clk <= transport '1';
-- --------------------
WAIT FOR 10 ns;
clk <= transport '0';
-- --------------------
WAIT FOR 10 ns;
clk <= transport '1';
-- --------------------
WAIT FOR 10 ns;
clk <= transport '0';
reset <= transport '1';
load_index <= 4;
-- --------------------
WAIT FOR 10 ns;
clk <= transport '1';
-- --------------------
WAIT FOR 10 ns;
clk <= transport '0';
reset <= transport '0';
assert finished = '0';
assert char = 'u';
-- --------------------
WAIT FOR 10 ns;
clk <= transport '1';
-- --------------------
WAIT FOR 10 ns;
clk <= transport '0';
-- --------------------
WAIT FOR 10 ns;
clk <= transport '1';
-- --------------------
WAIT FOR 10 ns;
clk <= transport '0';
-- --------------------
WAIT FOR 10 ns;
clk <= transport '1';
-- --------------------
WAIT FOR 10 ns;
clk <= transport '0';
-- --------------------
WAIT FOR 10 ns;
clk <= transport '1';
-- --------------------
WAIT FOR 10 ns;
clk <= transport '0';
-- --------------------
WAIT FOR 10 ns;
clk <= transport '1';
-- --------------------
WAIT FOR 10 ns;
clk <= transport '0';
-- --------------------
WAIT FOR 10 ns;
clk <= transport '1';
-- --------------------
WAIT FOR 10 ns;
clk <= transport '0';
-- --------------------
WAIT;
END PROCESS;
end testbench_arch_vowels;
| mit | daa12929fe846968b41ca851018e7d9f | 0.351823 | 4.866324 | false | false | false | false |
natsutan/NPU | fpga_implement/npu8/npu8.srcs/sources_1/ip/mul16_16/mul16_16_sim_netlist.vhdl | 1 | 599,991 | -- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (lin64) Build 1733598 Wed Dec 14 22:35:42 MST 2016
-- Date : Sat Jan 21 17:58:34 2017
-- Host : natu-OMEN-by-HP-Laptop running 64-bit Ubuntu 16.04.1 LTS
-- Command : write_vhdl -force -mode funcsim
-- /media/natu/data/proj/myproj/NPU/fpga_implement/npu8/npu8.srcs/sources_1/ip/mul16_16/mul16_16_sim_netlist.vhdl
-- Design : mul16_16
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xcku035-fbva676-3-e
-- --------------------------------------------------------------------------------
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`protect encoding = (enctype="BASE64", line_length=76, bytes=256)
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`protect encoding = (enctype="BASE64", line_length=76, bytes=256)
`protect key_block
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`protect encoding = (enctype="BASE64", line_length=76, bytes=256)
`protect key_block
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`protect encoding = (enctype="base64", line_length=76, bytes=256)
`protect key_block
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`protect encoding = (enctype="base64", line_length=76, bytes=256)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 433968)
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`protect end_protected
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity mul16_16_mult_gen_v12_0_12 is
port (
CLK : in STD_LOGIC;
A : in STD_LOGIC_VECTOR ( 15 downto 0 );
B : in STD_LOGIC_VECTOR ( 15 downto 0 );
CE : in STD_LOGIC;
SCLR : in STD_LOGIC;
ZERO_DETECT : out STD_LOGIC_VECTOR ( 1 downto 0 );
P : out STD_LOGIC_VECTOR ( 15 downto 0 );
PCASC : out STD_LOGIC_VECTOR ( 47 downto 0 )
);
attribute C_A_TYPE : integer;
attribute C_A_TYPE of mul16_16_mult_gen_v12_0_12 : entity is 1;
attribute C_A_WIDTH : integer;
attribute C_A_WIDTH of mul16_16_mult_gen_v12_0_12 : entity is 16;
attribute C_B_TYPE : integer;
attribute C_B_TYPE of mul16_16_mult_gen_v12_0_12 : entity is 1;
attribute C_B_VALUE : string;
attribute C_B_VALUE of mul16_16_mult_gen_v12_0_12 : entity is "10000001";
attribute C_B_WIDTH : integer;
attribute C_B_WIDTH of mul16_16_mult_gen_v12_0_12 : entity is 16;
attribute C_CCM_IMP : integer;
attribute C_CCM_IMP of mul16_16_mult_gen_v12_0_12 : entity is 0;
attribute C_CE_OVERRIDES_SCLR : integer;
attribute C_CE_OVERRIDES_SCLR of mul16_16_mult_gen_v12_0_12 : entity is 0;
attribute C_HAS_CE : integer;
attribute C_HAS_CE of mul16_16_mult_gen_v12_0_12 : entity is 0;
attribute C_HAS_SCLR : integer;
attribute C_HAS_SCLR of mul16_16_mult_gen_v12_0_12 : entity is 0;
attribute C_HAS_ZERO_DETECT : integer;
attribute C_HAS_ZERO_DETECT of mul16_16_mult_gen_v12_0_12 : entity is 0;
attribute C_LATENCY : integer;
attribute C_LATENCY of mul16_16_mult_gen_v12_0_12 : entity is 4;
attribute C_MODEL_TYPE : integer;
attribute C_MODEL_TYPE of mul16_16_mult_gen_v12_0_12 : entity is 0;
attribute C_MULT_TYPE : integer;
attribute C_MULT_TYPE of mul16_16_mult_gen_v12_0_12 : entity is 0;
attribute C_OPTIMIZE_GOAL : integer;
attribute C_OPTIMIZE_GOAL of mul16_16_mult_gen_v12_0_12 : entity is 1;
attribute C_OUT_HIGH : integer;
attribute C_OUT_HIGH of mul16_16_mult_gen_v12_0_12 : entity is 31;
attribute C_OUT_LOW : integer;
attribute C_OUT_LOW of mul16_16_mult_gen_v12_0_12 : entity is 16;
attribute C_ROUND_OUTPUT : integer;
attribute C_ROUND_OUTPUT of mul16_16_mult_gen_v12_0_12 : entity is 0;
attribute C_ROUND_PT : integer;
attribute C_ROUND_PT of mul16_16_mult_gen_v12_0_12 : entity is 0;
attribute C_VERBOSITY : integer;
attribute C_VERBOSITY of mul16_16_mult_gen_v12_0_12 : entity is 0;
attribute C_XDEVICEFAMILY : string;
attribute C_XDEVICEFAMILY of mul16_16_mult_gen_v12_0_12 : entity is "kintexu";
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of mul16_16_mult_gen_v12_0_12 : entity is "mult_gen_v12_0_12";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of mul16_16_mult_gen_v12_0_12 : entity is "yes";
end mul16_16_mult_gen_v12_0_12;
architecture STRUCTURE of mul16_16_mult_gen_v12_0_12 is
signal \<const0>\ : STD_LOGIC;
signal NLW_i_mult_PCASC_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 0 );
signal NLW_i_mult_ZERO_DETECT_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute C_A_TYPE of i_mult : label is 1;
attribute C_A_WIDTH of i_mult : label is 16;
attribute C_B_TYPE of i_mult : label is 1;
attribute C_B_VALUE of i_mult : label is "10000001";
attribute C_B_WIDTH of i_mult : label is 16;
attribute C_CCM_IMP of i_mult : label is 0;
attribute C_CE_OVERRIDES_SCLR of i_mult : label is 0;
attribute C_HAS_CE of i_mult : label is 0;
attribute C_HAS_SCLR of i_mult : label is 0;
attribute C_HAS_ZERO_DETECT of i_mult : label is 0;
attribute C_LATENCY of i_mult : label is 4;
attribute C_MODEL_TYPE of i_mult : label is 0;
attribute C_MULT_TYPE of i_mult : label is 0;
attribute C_OUT_HIGH of i_mult : label is 31;
attribute C_OUT_LOW of i_mult : label is 16;
attribute C_ROUND_OUTPUT of i_mult : label is 0;
attribute C_ROUND_PT of i_mult : label is 0;
attribute C_VERBOSITY of i_mult : label is 0;
attribute C_XDEVICEFAMILY of i_mult : label is "kintexu";
attribute c_optimize_goal of i_mult : label is 1;
attribute downgradeipidentifiedwarnings of i_mult : label is "yes";
begin
PCASC(47) <= \<const0>\;
PCASC(46) <= \<const0>\;
PCASC(45) <= \<const0>\;
PCASC(44) <= \<const0>\;
PCASC(43) <= \<const0>\;
PCASC(42) <= \<const0>\;
PCASC(41) <= \<const0>\;
PCASC(40) <= \<const0>\;
PCASC(39) <= \<const0>\;
PCASC(38) <= \<const0>\;
PCASC(37) <= \<const0>\;
PCASC(36) <= \<const0>\;
PCASC(35) <= \<const0>\;
PCASC(34) <= \<const0>\;
PCASC(33) <= \<const0>\;
PCASC(32) <= \<const0>\;
PCASC(31) <= \<const0>\;
PCASC(30) <= \<const0>\;
PCASC(29) <= \<const0>\;
PCASC(28) <= \<const0>\;
PCASC(27) <= \<const0>\;
PCASC(26) <= \<const0>\;
PCASC(25) <= \<const0>\;
PCASC(24) <= \<const0>\;
PCASC(23) <= \<const0>\;
PCASC(22) <= \<const0>\;
PCASC(21) <= \<const0>\;
PCASC(20) <= \<const0>\;
PCASC(19) <= \<const0>\;
PCASC(18) <= \<const0>\;
PCASC(17) <= \<const0>\;
PCASC(16) <= \<const0>\;
PCASC(15) <= \<const0>\;
PCASC(14) <= \<const0>\;
PCASC(13) <= \<const0>\;
PCASC(12) <= \<const0>\;
PCASC(11) <= \<const0>\;
PCASC(10) <= \<const0>\;
PCASC(9) <= \<const0>\;
PCASC(8) <= \<const0>\;
PCASC(7) <= \<const0>\;
PCASC(6) <= \<const0>\;
PCASC(5) <= \<const0>\;
PCASC(4) <= \<const0>\;
PCASC(3) <= \<const0>\;
PCASC(2) <= \<const0>\;
PCASC(1) <= \<const0>\;
PCASC(0) <= \<const0>\;
ZERO_DETECT(1) <= \<const0>\;
ZERO_DETECT(0) <= \<const0>\;
GND: unisim.vcomponents.GND
port map (
G => \<const0>\
);
i_mult: entity work.mul16_16_mult_gen_v12_0_12_viv
port map (
A(15 downto 0) => A(15 downto 0),
B(15 downto 0) => B(15 downto 0),
CE => '0',
CLK => CLK,
P(15 downto 0) => P(15 downto 0),
PCASC(47 downto 0) => NLW_i_mult_PCASC_UNCONNECTED(47 downto 0),
SCLR => '0',
ZERO_DETECT(1 downto 0) => NLW_i_mult_ZERO_DETECT_UNCONNECTED(1 downto 0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity mul16_16 is
port (
CLK : in STD_LOGIC;
A : in STD_LOGIC_VECTOR ( 15 downto 0 );
B : in STD_LOGIC_VECTOR ( 15 downto 0 );
P : out STD_LOGIC_VECTOR ( 15 downto 0 )
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of mul16_16 : entity is true;
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of mul16_16 : entity is "mul16_16,mult_gen_v12_0_12,{}";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of mul16_16 : entity is "yes";
attribute x_core_info : string;
attribute x_core_info of mul16_16 : entity is "mult_gen_v12_0_12,Vivado 2016.4";
end mul16_16;
architecture STRUCTURE of mul16_16 is
signal NLW_U0_PCASC_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 0 );
signal NLW_U0_ZERO_DETECT_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute C_A_TYPE : integer;
attribute C_A_TYPE of U0 : label is 1;
attribute C_A_WIDTH : integer;
attribute C_A_WIDTH of U0 : label is 16;
attribute C_B_TYPE : integer;
attribute C_B_TYPE of U0 : label is 1;
attribute C_B_VALUE : string;
attribute C_B_VALUE of U0 : label is "10000001";
attribute C_B_WIDTH : integer;
attribute C_B_WIDTH of U0 : label is 16;
attribute C_CCM_IMP : integer;
attribute C_CCM_IMP of U0 : label is 0;
attribute C_CE_OVERRIDES_SCLR : integer;
attribute C_CE_OVERRIDES_SCLR of U0 : label is 0;
attribute C_HAS_CE : integer;
attribute C_HAS_CE of U0 : label is 0;
attribute C_HAS_SCLR : integer;
attribute C_HAS_SCLR of U0 : label is 0;
attribute C_HAS_ZERO_DETECT : integer;
attribute C_HAS_ZERO_DETECT of U0 : label is 0;
attribute C_LATENCY : integer;
attribute C_LATENCY of U0 : label is 4;
attribute C_MODEL_TYPE : integer;
attribute C_MODEL_TYPE of U0 : label is 0;
attribute C_MULT_TYPE : integer;
attribute C_MULT_TYPE of U0 : label is 0;
attribute C_OUT_HIGH : integer;
attribute C_OUT_HIGH of U0 : label is 31;
attribute C_OUT_LOW : integer;
attribute C_OUT_LOW of U0 : label is 16;
attribute C_ROUND_OUTPUT : integer;
attribute C_ROUND_OUTPUT of U0 : label is 0;
attribute C_ROUND_PT : integer;
attribute C_ROUND_PT of U0 : label is 0;
attribute C_VERBOSITY : integer;
attribute C_VERBOSITY of U0 : label is 0;
attribute C_XDEVICEFAMILY : string;
attribute C_XDEVICEFAMILY of U0 : label is "kintexu";
attribute c_optimize_goal : integer;
attribute c_optimize_goal of U0 : label is 1;
attribute downgradeipidentifiedwarnings of U0 : label is "yes";
begin
U0: entity work.mul16_16_mult_gen_v12_0_12
port map (
A(15 downto 0) => A(15 downto 0),
B(15 downto 0) => B(15 downto 0),
CE => '1',
CLK => CLK,
P(15 downto 0) => P(15 downto 0),
PCASC(47 downto 0) => NLW_U0_PCASC_UNCONNECTED(47 downto 0),
SCLR => '0',
ZERO_DETECT(1 downto 0) => NLW_U0_ZERO_DETECT_UNCONNECTED(1 downto 0)
);
end STRUCTURE;
| bsd-3-clause | 2c075e7a2267a038e9e0cfafd71b0008 | 0.950259 | 1.819329 | false | false | false | false |
besm6/micro-besm | tests/2901/vhdl/funct_blocks_alg_beh/components/Q_reg/test_vectors.vhdl | 1 | 5,076 | --------------------------------------------------------------------------------
--
-- AM2901 Benchmark
--
-- Source: AMD data book
--
-- VHDL Benchmark author Indraneel Ghosh
-- University Of California, Irvine, CA 92717
--
-- Developed on Jan 1, 1992
--
-- Verification Information:
--
-- Verified By whom? Date Simulator
-- -------- ------------ -------- ------------
-- Syntax yes Champaka Ramachandran Sept 17, 92 ZYCAD
-- Functionality yes Champaka Ramachandran Sept 17, 92 ZYCAD
--------------------------------------------------------------------------------
--library ZYCAD;
use work.TYPES.all;
use work.MVL7_functions.all;
use work.synthesis_types.all;
entity E is
end;
architecture A of E is
component Q_reg_inst
port (
F : in MVL7_vector(3 downto 0);
clk : in clock;
I : in MVL7_vector(8 downto 0);
Q0, Q3 : in MVL7;
Q : inout MVL7_vector(3 downto 0)
);
end component;
signal F : MVL7_vector(3 downto 0);
signal clk : clock;
signal I : MVL7_vector(8 downto 0);
signal Q0, Q3 : MVL7;
signal Q : MVL7_vector(3 downto 0);
for all : Q_reg_inst use entity work.Q_reg(Q_reg);
begin
Q_reg_inst1 : Q_reg_inst port map(
F,
clk,
I,
Q0, Q3,
Q
);
process
begin
---------------------------------------------------------------------
I <= "000000000"; --#1
F <= "0111";
Q0 <= 'Z';
Q3 <= 'Z'; -- load F into Q
wait for 1 ns;
clk <= '1';
wait for 1 ns;
clk <= '0';
wait for 1 ns;
assert (Q = "0111")
report
"Assert 1 : < Q /= '0111'> "
severity warning;
wait for 1 ns;
---------------------------------------------------------------------
I <= "001000000"; --#2
F <= "0000";
Q0 <= 'Z'; -- do nothing
Q3 <= 'Z';
wait for 1 ns;
clk <= '1';
wait for 1 ns;
clk <= '0';
wait for 1 ns;
assert (Q = "0111")
report
"Assert 2 : < Q /= '0111'> "
severity warning;
wait for 1 ns;
---------------------------------------------------------------------
I <= "010000000"; --#3
F <= "0000";
Q0 <= 'Z'; -- do nothing
Q3 <= 'Z';
wait for 1 ns;
clk <= '1';
wait for 1 ns;
clk <= '0';
wait for 1 ns;
assert (Q = "0111")
report
"Assert 3 : < Q /= '0111'> "
severity warning;
wait for 1 ns;
---------------------------------------------------------------------
I <= "011000000"; --#4
F <= "0000";
Q0 <= 'Z'; -- do nothing
Q3 <= 'Z';
wait for 1 ns;
clk <= '1';
wait for 1 ns;
clk <= '0';
wait for 1 ns;
assert (Q = "0111")
report
"Assert 4 : < Q /= '0111'> "
severity warning;
wait for 1 ns;
---------------------------------------------------------------------
I <= "100000000"; --#5
F <= "0000";
Q0 <= 'Z';
Q3 <= '1'; -- down shift Q with input 1
wait for 1 ns;
clk <= '1';
wait for 1 ns;
clk <= '0';
wait for 1 ns;
assert (Q = "1011")
report
"Assert 5 : < Q /= '1011'> "
severity warning;
wait for 1 ns;
---------------------------------------------------------------------
I <= "100000000"; --#6
F <= "0000";
Q0 <= 'Z';
Q3 <= '0'; -- down shift Q with input 0
wait for 1 ns;
clk <= '1';
wait for 1 ns;
clk <= '0';
wait for 1 ns;
assert (Q = "0101")
report
"Assert 6 : < Q /= '0101'> "
severity warning;
wait for 1 ns;
--------------------------------------------------------------------
I <= "101000000"; --#7
F <= "0000";
Q0 <= 'Z';
Q3 <= 'Z'; -- do nothing
wait for 1 ns;
clk <= '1';
wait for 1 ns;
clk <= '0';
wait for 1 ns;
assert (Q = "0101")
report
"Assert 7 : < Q /= '0101'> "
severity warning;
wait for 1 ns;
---------------------------------------------------------------------
I <= "110000000"; --#8
F <= "0000";
Q0 <= '1'; -- Up shift Q with input 1
Q3 <= 'Z';
wait for 1 ns;
clk <= '1';
wait for 1 ns;
clk <= '0';
wait for 1 ns;
assert (Q = "1011")
report
"Assert 8 : < Q /= '1011'> "
severity warning;
wait for 1 ns;
---------------------------------------------------------------------
I <= "110000000"; --#9
F <= "0000";
Q0 <= '0'; -- Up shift Q with input 0
Q3 <= 'Z';
wait for 1 ns;
clk <= '1';
wait for 1 ns;
clk <= '0';
wait for 1 ns;
assert (Q = "0110")
report
"Assert 9 : < Q /= '0110'> "
severity warning;
wait for 1 ns;
---------------------------------------------------------------------
I <= "111000000"; --#10
F <= "0000";
Q0 <= 'Z';
Q3 <= 'Z'; -- do nothing
wait for 1 ns;
clk <= '1';
wait for 1 ns;
clk <= '0';
wait for 1 ns;
assert (Q = "0110")
report
"Assert 10 : < Q /= '0110'> "
severity warning;
wait for 1 ns;
---------------------------------------------------------------------
end process;
end A;
| mit | 9c81eef2d1c160ecb08232149218b2d5 | 0.385934 | 3.377246 | false | false | false | false |
varunnagpaal/Digital-Hardware-Modelling | vhdl/filter/fir/fir_generic_transposed_filter_syn.vhdl | 1 | 1,042,149 |
library IEEE;
use IEEE.std_logic_1164.all;
package CONV_PACK_fir_generic_transposed_filter is
-- define attributes
attribute ENUM_ENCODING : STRING;
-- define any necessary types
--type SIGNED is array (INTEGER range <>) of std_logic;
end CONV_PACK_fir_generic_transposed_filter;
library IEEE;
use IEEE.std_logic_1164.all;
use ieee.numeric_std.all;
use work.CONV_PACK_fir_generic_transposed_filter.all;
entity fir_generic_transposed_filter is
port( clk, rst, valid_x_in : in std_logic; ready_x_out : out std_logic;
valid_h_in : in std_logic; ready_h_out, valid_out : out std_logic;
ready_in : in std_logic; x_data_in, h_data_in : in SIGNED (15 downto
0); y_data_out : out SIGNED (32 downto 0));
end fir_generic_transposed_filter;
architecture SYN_fir_rtl_arch of fir_generic_transposed_filter is
component inv
port( inb : in std_logic; outb : out std_logic);
end component;
component xor2
port( a, b : in std_logic; outb : out std_logic);
end component;
component nand2
port( a, b : in std_logic; outb : out std_logic);
end component;
component oai22
port( a, b, c, d : in std_logic; outb : out std_logic);
end component;
component aoi22
port( a, b, c, d : in std_logic; outb : out std_logic);
end component;
component nor2
port( a, b : in std_logic; outb : out std_logic);
end component;
component oai12
port( b, c, a : in std_logic; outb : out std_logic);
end component;
component aoi12
port( b, c, a : in std_logic; outb : out std_logic);
end component;
component dff
port( d, gclk, rnot : in std_logic; q : out std_logic);
end component;
component dff_asyncprehh
port( d, gclk, asyncprehh : in std_logic; q : out std_logic);
end component;
component dff_asyncrsthl
port( d, gclk, asyncrsthl : in std_logic; q : out std_logic);
end component;
signal ready_x_out_port, ready_h_out_port, valid_out_port,
coefficient_mem_array_0_15_port, coefficient_mem_array_0_14_port,
coefficient_mem_array_0_13_port, coefficient_mem_array_0_12_port,
coefficient_mem_array_0_11_port, coefficient_mem_array_0_10_port,
coefficient_mem_array_0_9_port, coefficient_mem_array_0_8_port,
coefficient_mem_array_0_7_port, coefficient_mem_array_0_6_port,
coefficient_mem_array_0_5_port, coefficient_mem_array_0_4_port,
coefficient_mem_array_0_3_port, coefficient_mem_array_0_2_port,
coefficient_mem_array_0_1_port, coefficient_mem_array_0_0_port,
coefficient_mem_array_1_15_port, coefficient_mem_array_1_14_port,
coefficient_mem_array_1_13_port, coefficient_mem_array_1_12_port,
coefficient_mem_array_1_11_port, coefficient_mem_array_1_10_port,
coefficient_mem_array_1_9_port, coefficient_mem_array_1_8_port,
coefficient_mem_array_1_7_port, coefficient_mem_array_1_6_port,
coefficient_mem_array_1_5_port, coefficient_mem_array_1_4_port,
coefficient_mem_array_1_3_port, coefficient_mem_array_1_2_port,
coefficient_mem_array_1_1_port, coefficient_mem_array_1_0_port,
coefficient_mem_array_2_15_port, coefficient_mem_array_2_14_port,
coefficient_mem_array_2_13_port, coefficient_mem_array_2_12_port,
coefficient_mem_array_2_11_port, coefficient_mem_array_2_10_port,
coefficient_mem_array_2_9_port, coefficient_mem_array_2_8_port,
coefficient_mem_array_2_7_port, coefficient_mem_array_2_6_port,
coefficient_mem_array_2_5_port, coefficient_mem_array_2_4_port,
coefficient_mem_array_2_3_port, coefficient_mem_array_2_2_port,
coefficient_mem_array_2_1_port, coefficient_mem_array_2_0_port,
coefficient_mem_array_3_15_port, coefficient_mem_array_3_14_port,
coefficient_mem_array_3_13_port, coefficient_mem_array_3_12_port,
coefficient_mem_array_3_11_port, coefficient_mem_array_3_10_port,
coefficient_mem_array_3_9_port, coefficient_mem_array_3_8_port,
coefficient_mem_array_3_7_port, coefficient_mem_array_3_6_port,
coefficient_mem_array_3_5_port, coefficient_mem_array_3_4_port,
coefficient_mem_array_3_3_port, coefficient_mem_array_3_2_port,
coefficient_mem_array_3_1_port, coefficient_mem_array_3_0_port,
input_sample_mem_15_port, input_sample_mem_14_port,
input_sample_mem_13_port, input_sample_mem_12_port,
input_sample_mem_11_port, input_sample_mem_10_port,
input_sample_mem_9_port, input_sample_mem_8_port, input_sample_mem_7_port
, input_sample_mem_6_port, input_sample_mem_5_port,
input_sample_mem_4_port, input_sample_mem_3_port, input_sample_mem_2_port
, input_sample_mem_1_port, input_sample_mem_0_port,
adder_mem_array_0_32_port, adder_mem_array_0_31_port,
adder_mem_array_0_30_port, adder_mem_array_0_29_port,
adder_mem_array_0_28_port, adder_mem_array_0_27_port,
adder_mem_array_0_26_port, adder_mem_array_0_25_port,
adder_mem_array_0_24_port, adder_mem_array_0_23_port,
adder_mem_array_0_22_port, adder_mem_array_0_21_port,
adder_mem_array_0_20_port, adder_mem_array_0_19_port,
adder_mem_array_0_18_port, adder_mem_array_0_17_port,
adder_mem_array_0_16_port, adder_mem_array_0_15_port,
adder_mem_array_0_14_port, adder_mem_array_0_13_port,
adder_mem_array_0_12_port, adder_mem_array_0_11_port,
adder_mem_array_0_10_port, adder_mem_array_0_9_port,
adder_mem_array_0_8_port, adder_mem_array_0_7_port,
adder_mem_array_0_6_port, adder_mem_array_0_5_port,
adder_mem_array_0_4_port, adder_mem_array_0_3_port,
adder_mem_array_0_2_port, adder_mem_array_0_1_port,
adder_mem_array_0_0_port, adder_mem_array_1_32_port,
adder_mem_array_1_31_port, adder_mem_array_1_30_port,
adder_mem_array_1_29_port, adder_mem_array_1_28_port,
adder_mem_array_1_27_port, adder_mem_array_1_26_port,
adder_mem_array_1_25_port, adder_mem_array_1_24_port,
adder_mem_array_1_23_port, adder_mem_array_1_22_port,
adder_mem_array_1_21_port, adder_mem_array_1_20_port,
adder_mem_array_1_19_port, adder_mem_array_1_18_port,
adder_mem_array_1_17_port, adder_mem_array_1_16_port,
adder_mem_array_1_15_port, adder_mem_array_1_14_port,
adder_mem_array_1_13_port, adder_mem_array_1_12_port,
adder_mem_array_1_11_port, adder_mem_array_1_10_port,
adder_mem_array_1_9_port, adder_mem_array_1_8_port,
adder_mem_array_1_7_port, adder_mem_array_1_6_port,
adder_mem_array_1_5_port, adder_mem_array_1_4_port,
adder_mem_array_1_3_port, adder_mem_array_1_2_port,
adder_mem_array_1_1_port, adder_mem_array_1_0_port,
adder_mem_array_2_32_port, adder_mem_array_2_31_port,
adder_mem_array_2_30_port, adder_mem_array_2_29_port,
adder_mem_array_2_28_port, adder_mem_array_2_27_port,
adder_mem_array_2_26_port, adder_mem_array_2_25_port,
adder_mem_array_2_24_port, adder_mem_array_2_23_port,
adder_mem_array_2_22_port, adder_mem_array_2_21_port,
adder_mem_array_2_20_port, adder_mem_array_2_19_port,
adder_mem_array_2_18_port, adder_mem_array_2_17_port,
adder_mem_array_2_16_port, adder_mem_array_2_15_port,
adder_mem_array_2_14_port, adder_mem_array_2_13_port,
adder_mem_array_2_12_port, adder_mem_array_2_11_port,
adder_mem_array_2_10_port, adder_mem_array_2_9_port,
adder_mem_array_2_8_port, adder_mem_array_2_7_port,
adder_mem_array_2_6_port, adder_mem_array_2_5_port,
adder_mem_array_2_4_port, adder_mem_array_2_3_port,
adder_mem_array_2_2_port, adder_mem_array_2_1_port,
adder_mem_array_2_0_port, adder_mem_array_3_32_port,
adder_mem_array_3_31_port, adder_mem_array_3_30_port,
adder_mem_array_3_29_port, adder_mem_array_3_28_port,
adder_mem_array_3_27_port, adder_mem_array_3_26_port,
adder_mem_array_3_25_port, adder_mem_array_3_24_port,
adder_mem_array_3_23_port, adder_mem_array_3_22_port,
adder_mem_array_3_21_port, adder_mem_array_3_20_port,
adder_mem_array_3_19_port, adder_mem_array_3_18_port,
adder_mem_array_3_17_port, adder_mem_array_3_16_port,
adder_mem_array_3_15_port, adder_mem_array_3_14_port,
adder_mem_array_3_13_port, adder_mem_array_3_12_port,
adder_mem_array_3_11_port, adder_mem_array_3_10_port,
adder_mem_array_3_9_port, adder_mem_array_3_8_port,
adder_mem_array_3_7_port, adder_mem_array_3_6_port,
adder_mem_array_3_5_port, adder_mem_array_3_4_port,
adder_mem_array_3_3_port, adder_mem_array_3_2_port,
adder_mem_array_3_1_port, adder_mem_array_3_0_port,
multiplier_sigs_0_31_port, multiplier_sigs_0_30_port,
multiplier_sigs_0_29_port, multiplier_sigs_0_28_port,
multiplier_sigs_0_27_port, multiplier_sigs_0_26_port,
multiplier_sigs_0_25_port, multiplier_sigs_0_24_port,
multiplier_sigs_0_23_port, multiplier_sigs_0_22_port,
multiplier_sigs_0_21_port, multiplier_sigs_0_20_port,
multiplier_sigs_0_19_port, multiplier_sigs_0_18_port,
multiplier_sigs_0_17_port, multiplier_sigs_0_16_port,
multiplier_sigs_0_15_port, multiplier_sigs_0_14_port,
multiplier_sigs_0_13_port, multiplier_sigs_0_12_port,
multiplier_sigs_0_11_port, multiplier_sigs_0_10_port,
multiplier_sigs_0_9_port, multiplier_sigs_0_8_port,
multiplier_sigs_0_7_port, multiplier_sigs_0_6_port,
multiplier_sigs_0_5_port, multiplier_sigs_0_4_port,
multiplier_sigs_0_3_port, multiplier_sigs_0_2_port,
multiplier_sigs_0_0_port, multiplier_sigs_1_31_port,
multiplier_sigs_1_30_port, multiplier_sigs_1_29_port,
multiplier_sigs_1_28_port, multiplier_sigs_1_27_port,
multiplier_sigs_1_26_port, multiplier_sigs_1_25_port,
multiplier_sigs_1_24_port, multiplier_sigs_1_23_port,
multiplier_sigs_1_22_port, multiplier_sigs_1_21_port,
multiplier_sigs_1_20_port, multiplier_sigs_1_19_port,
multiplier_sigs_1_18_port, multiplier_sigs_1_17_port,
multiplier_sigs_1_16_port, multiplier_sigs_1_15_port,
multiplier_sigs_1_14_port, multiplier_sigs_1_13_port,
multiplier_sigs_1_12_port, multiplier_sigs_1_11_port,
multiplier_sigs_1_10_port, multiplier_sigs_1_9_port,
multiplier_sigs_1_8_port, multiplier_sigs_1_7_port,
multiplier_sigs_1_6_port, multiplier_sigs_1_5_port,
multiplier_sigs_1_4_port, multiplier_sigs_1_3_port,
multiplier_sigs_1_2_port, multiplier_sigs_1_0_port,
multiplier_sigs_2_31_port, multiplier_sigs_2_30_port,
multiplier_sigs_2_29_port, multiplier_sigs_2_28_port,
multiplier_sigs_2_27_port, multiplier_sigs_2_26_port,
multiplier_sigs_2_25_port, multiplier_sigs_2_24_port,
multiplier_sigs_2_23_port, multiplier_sigs_2_22_port,
multiplier_sigs_2_21_port, multiplier_sigs_2_20_port,
multiplier_sigs_2_19_port, multiplier_sigs_2_18_port,
multiplier_sigs_2_17_port, multiplier_sigs_2_16_port,
multiplier_sigs_2_15_port, multiplier_sigs_2_14_port,
multiplier_sigs_2_13_port, multiplier_sigs_2_12_port,
multiplier_sigs_2_11_port, multiplier_sigs_2_10_port,
multiplier_sigs_2_9_port, multiplier_sigs_2_8_port,
multiplier_sigs_2_7_port, multiplier_sigs_2_6_port,
multiplier_sigs_2_5_port, multiplier_sigs_2_4_port,
multiplier_sigs_2_3_port, multiplier_sigs_2_2_port,
multiplier_sigs_2_0_port, multiplier_sigs_3_31_port,
multiplier_sigs_3_30_port, multiplier_sigs_3_29_port,
multiplier_sigs_3_28_port, multiplier_sigs_3_27_port,
multiplier_sigs_3_26_port, multiplier_sigs_3_25_port,
multiplier_sigs_3_24_port, multiplier_sigs_3_23_port,
multiplier_sigs_3_22_port, multiplier_sigs_3_21_port,
multiplier_sigs_3_20_port, multiplier_sigs_3_19_port,
multiplier_sigs_3_18_port, multiplier_sigs_3_17_port,
multiplier_sigs_3_16_port, multiplier_sigs_3_15_port,
multiplier_sigs_3_14_port, multiplier_sigs_3_13_port,
multiplier_sigs_3_12_port, multiplier_sigs_3_11_port,
multiplier_sigs_3_10_port, multiplier_sigs_3_9_port,
multiplier_sigs_3_8_port, multiplier_sigs_3_7_port,
multiplier_sigs_3_6_port, multiplier_sigs_3_5_port,
multiplier_sigs_3_4_port, multiplier_sigs_3_3_port,
multiplier_sigs_3_2_port, multiplier_sigs_3_1_port,
multiplier_sigs_3_0_port, N6, N7, N8, N9, N10, N11, N12, N13, N14, N15,
N16, N17, N18, N19, N20, N21, N22, N23, N24, N25, N26, N27, N28, N29, N30
, N31, N32, N33, N34, N35, N36, N37, N38, N39, N40, N41, N42, N43, N44,
N45, N46, N47, N48, N49, N50, N51, N52, N53, N54, N55, N56, N57, N58, N59
, N60, N61, N62, N63, N64, N65, N66, N67, N68, N69, N70, N71, N72, N73,
N74, N75, N76, N77, N78, N79, N80, N81, N82, N83, N84, N85, N86, N87, N88
, N89, N90, N91, N92, N93, N94, N95, N96, N97, N98, N99, N100, N101, N102
, N103, N104, coeff_cnt_1_port, coeff_cnt_0_port, n16_port, n17_port,
n18_port, n19_port, n20_port, n21_port, n22_port, n23_port, n24_port,
n25_port, n26_port, n27_port, n28_port, n29_port, n30_port, n31_port,
n32_port, n33_port, n34_port, n35_port, n36_port, n37_port, n38_port,
n39_port, n40_port, n41_port, n42_port, n43_port, n44_port, n45_port,
n46_port, n47_port, n48_port, n49_port, n50_port, n51_port, n52_port,
n53_port, n54_port, n55_port, n56_port, n57_port, n58_port, n59_port,
n60_port, n61_port, n62_port, n63_port, n64_port, n65_port, n66_port,
n67_port, n68_port, n69_port, n70_port, n71_port, n72_port, n73_port,
n74_port, n75_port, n76_port, n77_port, n78_port, n79_port, n80_port,
n81_port, n82_port, n83_port, n84_port, n85_port, n86_port, n87_port,
n88_port, n89_port, n90_port, n91_port, n92_port, n93_port, n94_port,
n95_port, n96_port, n97_port, n98_port, n99_port, n100_port, n101_port,
n102_port, n103_port, n104_port, n105, n106, n107, n108, n109, n110, n111
, n112, n113, n114, n115, n116, n117, n118, n119, n120, n121, n122, n123,
n124, n125, n126, n127, n128, n129, n130, n131, n132, n133, n134, n135,
n136, n137, n138, n139, n140, n141, n142, n143, n144, n145, n146, n147,
n148, n149, n150, n151, n152, n153, n154, n155, n156, n157, n158, n159,
n160, n161, n162, n163, n164, n165, n166, n167, n168, n169, n170, n171,
n172, n173, n174, n175, n176, n177, n178, n179, n180, n181, n182, n183,
n184, n185, n186, n187, n188, n189, n190, n191, n192, n193, n194, n195,
n196, n197, n198, n199, n200, n201, n202, n203, n204, n205, n206, n207,
n208, n209, n210, n211, n212, n213, n214, n215, n216, n217, n218, n219,
n220, n221, n222, n223, n224, n225, n226, n227, n228, n229, n230, n231,
n232, n233, n234, n235, n236, n237, n238, n239,
mult_125_G3_FS_1_C_1_3_3_port, mult_125_G3_FS_1_C_1_4_0_port,
mult_125_G3_FS_1_C_1_4_1_port, mult_125_G3_FS_1_C_1_4_2_port,
mult_125_G3_FS_1_C_1_4_3_port, mult_125_G3_FS_1_C_1_5_0_port,
mult_125_G3_FS_1_C_1_5_1_port, mult_125_G3_FS_1_C_1_5_2_port,
mult_125_G3_FS_1_C_1_5_3_port, mult_125_G3_FS_1_C_1_6_0_port,
mult_125_G3_FS_1_C_1_6_1_port, mult_125_G3_FS_1_C_1_6_2_port,
mult_125_G3_FS_1_C_1_6_3_port, mult_125_G3_FS_1_C_1_7_0_port,
mult_125_G3_FS_1_C_1_7_1_port, mult_125_G3_FS_1_P_0_0_1_port,
mult_125_G3_FS_1_P_0_0_2_port, mult_125_G3_FS_1_P_0_0_3_port,
mult_125_G3_FS_1_P_0_1_1_port, mult_125_G3_FS_1_P_0_1_2_port,
mult_125_G3_FS_1_P_0_1_3_port, mult_125_G3_FS_1_P_0_2_1_port,
mult_125_G3_FS_1_P_0_2_2_port, mult_125_G3_FS_1_P_0_2_3_port,
mult_125_G3_FS_1_P_0_3_1_port, mult_125_G3_FS_1_P_0_3_2_port,
mult_125_G3_FS_1_P_0_3_3_port, mult_125_G3_FS_1_P_0_4_1_port,
mult_125_G3_FS_1_P_0_4_2_port, mult_125_G3_FS_1_P_0_4_3_port,
mult_125_G3_FS_1_P_0_5_1_port, mult_125_G3_FS_1_P_0_5_2_port,
mult_125_G3_FS_1_P_0_5_3_port, mult_125_G3_FS_1_P_0_6_1_port,
mult_125_G3_FS_1_P_0_6_2_port, mult_125_G3_FS_1_P_0_6_3_port,
mult_125_G3_FS_1_P_0_7_1_port, mult_125_G3_FS_1_TEMP_P_0_0_0_port,
mult_125_G3_FS_1_TEMP_P_0_1_0_port, mult_125_G3_FS_1_TEMP_P_0_2_0_port,
mult_125_G3_FS_1_TEMP_P_0_3_0_port, mult_125_G3_FS_1_TEMP_P_0_4_0_port,
mult_125_G3_FS_1_TEMP_P_0_4_1_port, mult_125_G3_FS_1_TEMP_P_0_4_2_port,
mult_125_G3_FS_1_TEMP_P_0_5_0_port, mult_125_G3_FS_1_TEMP_P_0_5_1_port,
mult_125_G3_FS_1_TEMP_P_0_5_2_port, mult_125_G3_FS_1_TEMP_P_0_6_0_port,
mult_125_G3_FS_1_TEMP_P_0_6_1_port, mult_125_G3_FS_1_TEMP_P_0_6_2_port,
mult_125_G3_FS_1_TEMP_P_0_7_0_port, mult_125_G3_FS_1_G_1_0_3_port,
mult_125_G3_FS_1_G_1_1_0_port, mult_125_G3_FS_1_G_1_1_1_port,
mult_125_G3_FS_1_G_1_1_2_port, mult_125_G3_FS_1_G_2_0_0_port,
mult_125_G3_FS_1_TEMP_G_0_3_2_port, mult_125_G3_FS_1_TEMP_G_0_4_1_port,
mult_125_G3_FS_1_TEMP_G_0_4_2_port, mult_125_G3_FS_1_TEMP_G_0_5_1_port,
mult_125_G3_FS_1_TEMP_G_0_5_2_port, mult_125_G3_FS_1_TEMP_G_0_6_1_port,
mult_125_G3_FS_1_TEMP_G_0_6_2_port, mult_125_G3_FS_1_G_n_int_0_3_2_port,
mult_125_G3_FS_1_G_n_int_0_3_3_port, mult_125_G3_FS_1_G_n_int_0_4_0_port,
mult_125_G3_FS_1_G_n_int_0_4_1_port, mult_125_G3_FS_1_G_n_int_0_4_2_port,
mult_125_G3_FS_1_G_n_int_0_4_3_port, mult_125_G3_FS_1_G_n_int_0_5_0_port,
mult_125_G3_FS_1_G_n_int_0_5_1_port, mult_125_G3_FS_1_G_n_int_0_5_2_port,
mult_125_G3_FS_1_G_n_int_0_5_3_port, mult_125_G3_FS_1_G_n_int_0_6_0_port,
mult_125_G3_FS_1_G_n_int_0_6_1_port, mult_125_G3_FS_1_G_n_int_0_6_2_port,
mult_125_G3_FS_1_G_n_int_0_6_3_port, mult_125_G3_FS_1_G_n_int_0_7_0_port,
mult_125_G3_FS_1_G_n_int_0_7_1_port, mult_125_G3_FS_1_PG_int_0_3_3_port,
mult_125_G3_FS_1_PG_int_0_4_0_port, mult_125_G3_FS_1_PG_int_0_4_1_port,
mult_125_G3_FS_1_PG_int_0_4_2_port, mult_125_G3_FS_1_PG_int_0_4_3_port,
mult_125_G3_FS_1_PG_int_0_5_0_port, mult_125_G3_FS_1_PG_int_0_5_1_port,
mult_125_G3_FS_1_PG_int_0_5_2_port, mult_125_G3_FS_1_PG_int_0_5_3_port,
mult_125_G3_FS_1_PG_int_0_6_0_port, mult_125_G3_FS_1_PG_int_0_6_1_port,
mult_125_G3_FS_1_PG_int_0_6_2_port, mult_125_G3_FS_1_PG_int_0_6_3_port,
mult_125_G3_FS_1_PG_int_0_7_0_port, mult_125_G3_FS_1_PG_int_0_7_1_port,
mult_125_G3_A2_14_port, mult_125_G3_A2_15_port, mult_125_G3_A2_16_port,
mult_125_G3_A2_17_port, mult_125_G3_A2_18_port, mult_125_G3_A2_19_port,
mult_125_G3_A2_20_port, mult_125_G3_A2_21_port, mult_125_G3_A2_22_port,
mult_125_G3_A2_23_port, mult_125_G3_A2_24_port, mult_125_G3_A2_25_port,
mult_125_G3_A2_26_port, mult_125_G3_A2_27_port, mult_125_G3_A2_28_port,
mult_125_G3_A2_29_port, mult_125_G3_A1_0_port, mult_125_G3_A1_1_port,
mult_125_G3_A1_2_port, mult_125_G3_A1_3_port, mult_125_G3_A1_4_port,
mult_125_G3_A1_5_port, mult_125_G3_A1_6_port, mult_125_G3_A1_7_port,
mult_125_G3_A1_8_port, mult_125_G3_A1_9_port, mult_125_G3_A1_10_port,
mult_125_G3_A1_11_port, mult_125_G3_A1_12_port, mult_125_G3_A1_13_port,
mult_125_G3_A1_14_port, mult_125_G3_A1_15_port, mult_125_G3_A1_16_port,
mult_125_G3_A1_17_port, mult_125_G3_A1_18_port, mult_125_G3_A1_19_port,
mult_125_G3_A1_20_port, mult_125_G3_A1_21_port, mult_125_G3_A1_22_port,
mult_125_G3_A1_23_port, mult_125_G3_A1_24_port, mult_125_G3_A1_25_port,
mult_125_G3_A1_26_port, mult_125_G3_A1_27_port, mult_125_G3_A1_28_port,
mult_125_G3_A1_29_port, mult_125_G3_ZB, mult_125_G3_ZA, mult_125_G3_QB,
mult_125_G3_QA, mult_125_G3_A_notx_0_port, mult_125_G3_A_notx_1_port,
mult_125_G3_A_notx_2_port, mult_125_G3_A_notx_3_port,
mult_125_G3_A_notx_4_port, mult_125_G3_A_notx_5_port,
mult_125_G3_A_notx_6_port, mult_125_G3_A_notx_7_port,
mult_125_G3_A_notx_8_port, mult_125_G3_A_notx_9_port,
mult_125_G3_A_notx_10_port, mult_125_G3_A_notx_11_port,
mult_125_G3_A_notx_12_port, mult_125_G3_A_notx_13_port,
mult_125_G3_A_notx_14_port, mult_125_G3_B_notx_0_port,
mult_125_G3_B_notx_1_port, mult_125_G3_B_notx_2_port,
mult_125_G3_B_notx_3_port, mult_125_G3_B_notx_4_port,
mult_125_G3_B_notx_5_port, mult_125_G3_B_notx_6_port,
mult_125_G3_B_notx_7_port, mult_125_G3_B_notx_8_port,
mult_125_G3_B_notx_9_port, mult_125_G3_B_notx_10_port,
mult_125_G3_B_notx_11_port, mult_125_G3_B_notx_12_port,
mult_125_G3_B_notx_13_port, mult_125_G3_B_notx_14_port,
mult_125_G3_ab_0_1_port, mult_125_G3_ab_0_2_port, mult_125_G3_ab_0_3_port
, mult_125_G3_ab_0_4_port, mult_125_G3_ab_0_5_port,
mult_125_G3_ab_0_6_port, mult_125_G3_ab_0_7_port, mult_125_G3_ab_0_8_port
, mult_125_G3_ab_0_9_port, mult_125_G3_ab_0_10_port,
mult_125_G3_ab_0_11_port, mult_125_G3_ab_0_12_port,
mult_125_G3_ab_0_13_port, mult_125_G3_ab_0_14_port,
mult_125_G3_ab_0_15_port, mult_125_G3_ab_1_0_port,
mult_125_G3_ab_1_1_port, mult_125_G3_ab_1_2_port, mult_125_G3_ab_1_3_port
, mult_125_G3_ab_1_4_port, mult_125_G3_ab_1_5_port,
mult_125_G3_ab_1_6_port, mult_125_G3_ab_1_7_port, mult_125_G3_ab_1_8_port
, mult_125_G3_ab_1_9_port, mult_125_G3_ab_1_10_port,
mult_125_G3_ab_1_11_port, mult_125_G3_ab_1_12_port,
mult_125_G3_ab_1_13_port, mult_125_G3_ab_1_14_port,
mult_125_G3_ab_1_15_port, mult_125_G3_ab_2_0_port,
mult_125_G3_ab_2_1_port, mult_125_G3_ab_2_2_port, mult_125_G3_ab_2_3_port
, mult_125_G3_ab_2_4_port, mult_125_G3_ab_2_5_port,
mult_125_G3_ab_2_6_port, mult_125_G3_ab_2_7_port, mult_125_G3_ab_2_8_port
, mult_125_G3_ab_2_9_port, mult_125_G3_ab_2_10_port,
mult_125_G3_ab_2_11_port, mult_125_G3_ab_2_12_port,
mult_125_G3_ab_2_13_port, mult_125_G3_ab_2_14_port,
mult_125_G3_ab_2_15_port, mult_125_G3_ab_3_0_port,
mult_125_G3_ab_3_1_port, mult_125_G3_ab_3_2_port, mult_125_G3_ab_3_3_port
, mult_125_G3_ab_3_4_port, mult_125_G3_ab_3_5_port,
mult_125_G3_ab_3_6_port, mult_125_G3_ab_3_7_port, mult_125_G3_ab_3_8_port
, mult_125_G3_ab_3_9_port, mult_125_G3_ab_3_10_port,
mult_125_G3_ab_3_11_port, mult_125_G3_ab_3_12_port,
mult_125_G3_ab_3_13_port, mult_125_G3_ab_3_14_port,
mult_125_G3_ab_3_15_port, mult_125_G3_ab_4_0_port,
mult_125_G3_ab_4_1_port, mult_125_G3_ab_4_2_port, mult_125_G3_ab_4_3_port
, mult_125_G3_ab_4_4_port, mult_125_G3_ab_4_5_port,
mult_125_G3_ab_4_6_port, mult_125_G3_ab_4_7_port, mult_125_G3_ab_4_8_port
, mult_125_G3_ab_4_9_port, mult_125_G3_ab_4_10_port,
mult_125_G3_ab_4_11_port, mult_125_G3_ab_4_12_port,
mult_125_G3_ab_4_13_port, mult_125_G3_ab_4_14_port,
mult_125_G3_ab_4_15_port, mult_125_G3_ab_5_0_port,
mult_125_G3_ab_5_1_port, mult_125_G3_ab_5_2_port, mult_125_G3_ab_5_3_port
, mult_125_G3_ab_5_4_port, mult_125_G3_ab_5_5_port,
mult_125_G3_ab_5_6_port, mult_125_G3_ab_5_7_port, mult_125_G3_ab_5_8_port
, mult_125_G3_ab_5_9_port, mult_125_G3_ab_5_10_port,
mult_125_G3_ab_5_11_port, mult_125_G3_ab_5_12_port,
mult_125_G3_ab_5_13_port, mult_125_G3_ab_5_14_port,
mult_125_G3_ab_5_15_port, mult_125_G3_ab_6_0_port,
mult_125_G3_ab_6_1_port, mult_125_G3_ab_6_2_port, mult_125_G3_ab_6_3_port
, mult_125_G3_ab_6_4_port, mult_125_G3_ab_6_5_port,
mult_125_G3_ab_6_6_port, mult_125_G3_ab_6_7_port, mult_125_G3_ab_6_8_port
, mult_125_G3_ab_6_9_port, mult_125_G3_ab_6_10_port,
mult_125_G3_ab_6_11_port, mult_125_G3_ab_6_12_port,
mult_125_G3_ab_6_13_port, mult_125_G3_ab_6_14_port,
mult_125_G3_ab_6_15_port, mult_125_G3_ab_7_0_port,
mult_125_G3_ab_7_1_port, mult_125_G3_ab_7_2_port, mult_125_G3_ab_7_3_port
, mult_125_G3_ab_7_4_port, mult_125_G3_ab_7_5_port,
mult_125_G3_ab_7_6_port, mult_125_G3_ab_7_7_port, mult_125_G3_ab_7_8_port
, mult_125_G3_ab_7_9_port, mult_125_G3_ab_7_10_port,
mult_125_G3_ab_7_11_port, mult_125_G3_ab_7_12_port,
mult_125_G3_ab_7_13_port, mult_125_G3_ab_7_14_port,
mult_125_G3_ab_7_15_port, mult_125_G3_ab_8_0_port,
mult_125_G3_ab_8_1_port, mult_125_G3_ab_8_2_port, mult_125_G3_ab_8_3_port
, mult_125_G3_ab_8_4_port, mult_125_G3_ab_8_5_port,
mult_125_G3_ab_8_6_port, mult_125_G3_ab_8_7_port, mult_125_G3_ab_8_8_port
, mult_125_G3_ab_8_9_port, mult_125_G3_ab_8_10_port,
mult_125_G3_ab_8_11_port, mult_125_G3_ab_8_12_port,
mult_125_G3_ab_8_13_port, mult_125_G3_ab_8_14_port,
mult_125_G3_ab_8_15_port, mult_125_G3_ab_9_0_port,
mult_125_G3_ab_9_1_port, mult_125_G3_ab_9_2_port, mult_125_G3_ab_9_3_port
, mult_125_G3_ab_9_4_port, mult_125_G3_ab_9_5_port,
mult_125_G3_ab_9_6_port, mult_125_G3_ab_9_7_port, mult_125_G3_ab_9_8_port
, mult_125_G3_ab_9_9_port, mult_125_G3_ab_9_10_port,
mult_125_G3_ab_9_11_port, mult_125_G3_ab_9_12_port,
mult_125_G3_ab_9_13_port, mult_125_G3_ab_9_14_port,
mult_125_G3_ab_9_15_port, mult_125_G3_ab_10_0_port,
mult_125_G3_ab_10_1_port, mult_125_G3_ab_10_2_port,
mult_125_G3_ab_10_3_port, mult_125_G3_ab_10_4_port,
mult_125_G3_ab_10_5_port, mult_125_G3_ab_10_6_port,
mult_125_G3_ab_10_7_port, mult_125_G3_ab_10_8_port,
mult_125_G3_ab_10_9_port, mult_125_G3_ab_10_10_port,
mult_125_G3_ab_10_11_port, mult_125_G3_ab_10_12_port,
mult_125_G3_ab_10_13_port, mult_125_G3_ab_10_14_port,
mult_125_G3_ab_10_15_port, mult_125_G3_ab_11_0_port,
mult_125_G3_ab_11_1_port, mult_125_G3_ab_11_2_port,
mult_125_G3_ab_11_3_port, mult_125_G3_ab_11_4_port,
mult_125_G3_ab_11_5_port, mult_125_G3_ab_11_6_port,
mult_125_G3_ab_11_7_port, mult_125_G3_ab_11_8_port,
mult_125_G3_ab_11_9_port, mult_125_G3_ab_11_10_port,
mult_125_G3_ab_11_11_port, mult_125_G3_ab_11_12_port,
mult_125_G3_ab_11_13_port, mult_125_G3_ab_11_14_port,
mult_125_G3_ab_11_15_port, mult_125_G3_ab_12_0_port,
mult_125_G3_ab_12_1_port, mult_125_G3_ab_12_2_port,
mult_125_G3_ab_12_3_port, mult_125_G3_ab_12_4_port,
mult_125_G3_ab_12_5_port, mult_125_G3_ab_12_6_port,
mult_125_G3_ab_12_7_port, mult_125_G3_ab_12_8_port,
mult_125_G3_ab_12_9_port, mult_125_G3_ab_12_10_port,
mult_125_G3_ab_12_11_port, mult_125_G3_ab_12_12_port,
mult_125_G3_ab_12_13_port, mult_125_G3_ab_12_14_port,
mult_125_G3_ab_12_15_port, mult_125_G3_ab_13_0_port,
mult_125_G3_ab_13_1_port, mult_125_G3_ab_13_2_port,
mult_125_G3_ab_13_3_port, mult_125_G3_ab_13_4_port,
mult_125_G3_ab_13_5_port, mult_125_G3_ab_13_6_port,
mult_125_G3_ab_13_7_port, mult_125_G3_ab_13_8_port,
mult_125_G3_ab_13_9_port, mult_125_G3_ab_13_10_port,
mult_125_G3_ab_13_11_port, mult_125_G3_ab_13_12_port,
mult_125_G3_ab_13_13_port, mult_125_G3_ab_13_14_port,
mult_125_G3_ab_13_15_port, mult_125_G3_ab_14_0_port,
mult_125_G3_ab_14_1_port, mult_125_G3_ab_14_2_port,
mult_125_G3_ab_14_3_port, mult_125_G3_ab_14_4_port,
mult_125_G3_ab_14_5_port, mult_125_G3_ab_14_6_port,
mult_125_G3_ab_14_7_port, mult_125_G3_ab_14_8_port,
mult_125_G3_ab_14_9_port, mult_125_G3_ab_14_10_port,
mult_125_G3_ab_14_11_port, mult_125_G3_ab_14_12_port,
mult_125_G3_ab_14_13_port, mult_125_G3_ab_14_14_port,
mult_125_G3_ab_14_15_port, mult_125_G3_ab_15_0_port,
mult_125_G3_ab_15_1_port, mult_125_G3_ab_15_2_port,
mult_125_G3_ab_15_3_port, mult_125_G3_ab_15_4_port,
mult_125_G3_ab_15_5_port, mult_125_G3_ab_15_6_port,
mult_125_G3_ab_15_7_port, mult_125_G3_ab_15_8_port,
mult_125_G3_ab_15_9_port, mult_125_G3_ab_15_10_port,
mult_125_G3_ab_15_11_port, mult_125_G3_ab_15_12_port,
mult_125_G3_ab_15_13_port, mult_125_G3_ab_15_14_port,
mult_125_G3_ab_15_15_port, mult_125_G3_B_not_0_port,
mult_125_G3_B_not_1_port, mult_125_G3_B_not_2_port,
mult_125_G3_B_not_3_port, mult_125_G3_B_not_4_port,
mult_125_G3_B_not_5_port, mult_125_G3_B_not_6_port,
mult_125_G3_B_not_7_port, mult_125_G3_B_not_8_port,
mult_125_G3_B_not_9_port, mult_125_G3_B_not_10_port,
mult_125_G3_B_not_11_port, mult_125_G3_B_not_12_port,
mult_125_G3_B_not_13_port, mult_125_G3_B_not_14_port,
mult_125_G3_B_not_15_port, mult_125_G3_A_not_0_port,
mult_125_G3_A_not_1_port, mult_125_G3_A_not_2_port,
mult_125_G3_A_not_3_port, mult_125_G3_A_not_4_port,
mult_125_G3_A_not_5_port, mult_125_G3_A_not_6_port,
mult_125_G3_A_not_7_port, mult_125_G3_A_not_8_port,
mult_125_G3_A_not_9_port, mult_125_G3_A_not_10_port,
mult_125_G3_A_not_11_port, mult_125_G3_A_not_12_port,
mult_125_G3_A_not_13_port, mult_125_G3_A_not_14_port,
mult_125_G3_A_not_15_port, mult_125_G2_FS_1_C_1_3_3_port,
mult_125_G2_FS_1_C_1_4_0_port, mult_125_G2_FS_1_C_1_4_1_port,
mult_125_G2_FS_1_C_1_4_2_port, mult_125_G2_FS_1_C_1_4_3_port,
mult_125_G2_FS_1_C_1_5_0_port, mult_125_G2_FS_1_C_1_5_1_port,
mult_125_G2_FS_1_C_1_5_2_port, mult_125_G2_FS_1_C_1_5_3_port,
mult_125_G2_FS_1_C_1_6_0_port, mult_125_G2_FS_1_C_1_6_1_port,
mult_125_G2_FS_1_C_1_6_2_port, mult_125_G2_FS_1_C_1_6_3_port,
mult_125_G2_FS_1_C_1_7_0_port, mult_125_G2_FS_1_C_1_7_1_port,
mult_125_G2_FS_1_P_0_0_1_port, mult_125_G2_FS_1_P_0_0_2_port,
mult_125_G2_FS_1_P_0_0_3_port, mult_125_G2_FS_1_P_0_1_1_port,
mult_125_G2_FS_1_P_0_1_2_port, mult_125_G2_FS_1_P_0_1_3_port,
mult_125_G2_FS_1_P_0_2_1_port, mult_125_G2_FS_1_P_0_2_2_port,
mult_125_G2_FS_1_P_0_2_3_port, mult_125_G2_FS_1_P_0_3_1_port,
mult_125_G2_FS_1_P_0_3_2_port, mult_125_G2_FS_1_P_0_3_3_port,
mult_125_G2_FS_1_P_0_4_1_port, mult_125_G2_FS_1_P_0_4_2_port,
mult_125_G2_FS_1_P_0_4_3_port, mult_125_G2_FS_1_P_0_5_1_port,
mult_125_G2_FS_1_P_0_5_2_port, mult_125_G2_FS_1_P_0_5_3_port,
mult_125_G2_FS_1_P_0_6_1_port, mult_125_G2_FS_1_P_0_6_2_port,
mult_125_G2_FS_1_P_0_6_3_port, mult_125_G2_FS_1_P_0_7_1_port,
mult_125_G2_FS_1_TEMP_P_0_0_0_port, mult_125_G2_FS_1_TEMP_P_0_1_0_port,
mult_125_G2_FS_1_TEMP_P_0_2_0_port, mult_125_G2_FS_1_TEMP_P_0_3_0_port,
mult_125_G2_FS_1_TEMP_P_0_4_0_port, mult_125_G2_FS_1_TEMP_P_0_4_1_port,
mult_125_G2_FS_1_TEMP_P_0_4_2_port, mult_125_G2_FS_1_TEMP_P_0_5_0_port,
mult_125_G2_FS_1_TEMP_P_0_5_1_port, mult_125_G2_FS_1_TEMP_P_0_5_2_port,
mult_125_G2_FS_1_TEMP_P_0_6_0_port, mult_125_G2_FS_1_TEMP_P_0_6_1_port,
mult_125_G2_FS_1_TEMP_P_0_6_2_port, mult_125_G2_FS_1_TEMP_P_0_7_0_port,
mult_125_G2_FS_1_G_1_0_3_port, mult_125_G2_FS_1_G_1_1_0_port,
mult_125_G2_FS_1_G_1_1_1_port, mult_125_G2_FS_1_G_1_1_2_port,
mult_125_G2_FS_1_G_2_0_0_port, mult_125_G2_FS_1_TEMP_G_0_3_2_port,
mult_125_G2_FS_1_TEMP_G_0_4_1_port, mult_125_G2_FS_1_TEMP_G_0_4_2_port,
mult_125_G2_FS_1_TEMP_G_0_5_1_port, mult_125_G2_FS_1_TEMP_G_0_5_2_port,
mult_125_G2_FS_1_TEMP_G_0_6_1_port, mult_125_G2_FS_1_TEMP_G_0_6_2_port,
mult_125_G2_FS_1_G_n_int_0_3_2_port, mult_125_G2_FS_1_G_n_int_0_3_3_port,
mult_125_G2_FS_1_G_n_int_0_4_0_port, mult_125_G2_FS_1_G_n_int_0_4_1_port,
mult_125_G2_FS_1_G_n_int_0_4_2_port, mult_125_G2_FS_1_G_n_int_0_4_3_port,
mult_125_G2_FS_1_G_n_int_0_5_0_port, mult_125_G2_FS_1_G_n_int_0_5_1_port,
mult_125_G2_FS_1_G_n_int_0_5_2_port, mult_125_G2_FS_1_G_n_int_0_5_3_port,
mult_125_G2_FS_1_G_n_int_0_6_0_port, mult_125_G2_FS_1_G_n_int_0_6_1_port,
mult_125_G2_FS_1_G_n_int_0_6_2_port, mult_125_G2_FS_1_G_n_int_0_6_3_port,
mult_125_G2_FS_1_G_n_int_0_7_0_port, mult_125_G2_FS_1_G_n_int_0_7_1_port,
mult_125_G2_FS_1_PG_int_0_3_3_port, mult_125_G2_FS_1_PG_int_0_4_0_port,
mult_125_G2_FS_1_PG_int_0_4_1_port, mult_125_G2_FS_1_PG_int_0_4_2_port,
mult_125_G2_FS_1_PG_int_0_4_3_port, mult_125_G2_FS_1_PG_int_0_5_0_port,
mult_125_G2_FS_1_PG_int_0_5_1_port, mult_125_G2_FS_1_PG_int_0_5_2_port,
mult_125_G2_FS_1_PG_int_0_5_3_port, mult_125_G2_FS_1_PG_int_0_6_0_port,
mult_125_G2_FS_1_PG_int_0_6_1_port, mult_125_G2_FS_1_PG_int_0_6_2_port,
mult_125_G2_FS_1_PG_int_0_6_3_port, mult_125_G2_FS_1_PG_int_0_7_0_port,
mult_125_G2_FS_1_PG_int_0_7_1_port, mult_125_G2_A2_14_port,
mult_125_G2_A2_15_port, mult_125_G2_A2_16_port, mult_125_G2_A2_17_port,
mult_125_G2_A2_18_port, mult_125_G2_A2_19_port, mult_125_G2_A2_20_port,
mult_125_G2_A2_21_port, mult_125_G2_A2_22_port, mult_125_G2_A2_23_port,
mult_125_G2_A2_24_port, mult_125_G2_A2_25_port, mult_125_G2_A2_26_port,
mult_125_G2_A2_27_port, mult_125_G2_A2_28_port, mult_125_G2_A2_29_port,
mult_125_G2_A1_0_port, mult_125_G2_A1_1_port, mult_125_G2_A1_2_port,
mult_125_G2_A1_3_port, mult_125_G2_A1_4_port, mult_125_G2_A1_5_port,
mult_125_G2_A1_6_port, mult_125_G2_A1_7_port, mult_125_G2_A1_8_port,
mult_125_G2_A1_9_port, mult_125_G2_A1_10_port, mult_125_G2_A1_11_port,
mult_125_G2_A1_12_port, mult_125_G2_A1_13_port, mult_125_G2_A1_14_port,
mult_125_G2_A1_15_port, mult_125_G2_A1_16_port, mult_125_G2_A1_17_port,
mult_125_G2_A1_18_port, mult_125_G2_A1_19_port, mult_125_G2_A1_20_port,
mult_125_G2_A1_21_port, mult_125_G2_A1_22_port, mult_125_G2_A1_23_port,
mult_125_G2_A1_24_port, mult_125_G2_A1_25_port, mult_125_G2_A1_26_port,
mult_125_G2_A1_27_port, mult_125_G2_A1_28_port, mult_125_G2_A1_29_port,
mult_125_G2_ZB, mult_125_G2_ZA, mult_125_G2_QB, mult_125_G2_QA,
mult_125_G2_A_notx_0_port, mult_125_G2_A_notx_1_port,
mult_125_G2_A_notx_2_port, mult_125_G2_A_notx_3_port,
mult_125_G2_A_notx_4_port, mult_125_G2_A_notx_5_port,
mult_125_G2_A_notx_6_port, mult_125_G2_A_notx_7_port,
mult_125_G2_A_notx_8_port, mult_125_G2_A_notx_9_port,
mult_125_G2_A_notx_10_port, mult_125_G2_A_notx_11_port,
mult_125_G2_A_notx_12_port, mult_125_G2_A_notx_13_port,
mult_125_G2_A_notx_14_port, mult_125_G2_B_notx_0_port,
mult_125_G2_B_notx_1_port, mult_125_G2_B_notx_2_port,
mult_125_G2_B_notx_3_port, mult_125_G2_B_notx_4_port,
mult_125_G2_B_notx_5_port, mult_125_G2_B_notx_6_port,
mult_125_G2_B_notx_7_port, mult_125_G2_B_notx_8_port,
mult_125_G2_B_notx_9_port, mult_125_G2_B_notx_10_port,
mult_125_G2_B_notx_11_port, mult_125_G2_B_notx_12_port,
mult_125_G2_B_notx_13_port, mult_125_G2_B_notx_14_port,
mult_125_G2_ab_0_1_port, mult_125_G2_ab_0_2_port, mult_125_G2_ab_0_3_port
, mult_125_G2_ab_0_4_port, mult_125_G2_ab_0_5_port,
mult_125_G2_ab_0_6_port, mult_125_G2_ab_0_7_port, mult_125_G2_ab_0_8_port
, mult_125_G2_ab_0_9_port, mult_125_G2_ab_0_10_port,
mult_125_G2_ab_0_11_port, mult_125_G2_ab_0_12_port,
mult_125_G2_ab_0_13_port, mult_125_G2_ab_0_14_port,
mult_125_G2_ab_0_15_port, mult_125_G2_ab_1_0_port,
mult_125_G2_ab_1_1_port, mult_125_G2_ab_1_2_port, mult_125_G2_ab_1_3_port
, mult_125_G2_ab_1_4_port, mult_125_G2_ab_1_5_port,
mult_125_G2_ab_1_6_port, mult_125_G2_ab_1_7_port, mult_125_G2_ab_1_8_port
, mult_125_G2_ab_1_9_port, mult_125_G2_ab_1_10_port,
mult_125_G2_ab_1_11_port, mult_125_G2_ab_1_12_port,
mult_125_G2_ab_1_13_port, mult_125_G2_ab_1_14_port,
mult_125_G2_ab_1_15_port, mult_125_G2_ab_2_0_port,
mult_125_G2_ab_2_1_port, mult_125_G2_ab_2_2_port, mult_125_G2_ab_2_3_port
, mult_125_G2_ab_2_4_port, mult_125_G2_ab_2_5_port,
mult_125_G2_ab_2_6_port, mult_125_G2_ab_2_7_port, mult_125_G2_ab_2_8_port
, mult_125_G2_ab_2_9_port, mult_125_G2_ab_2_10_port,
mult_125_G2_ab_2_11_port, mult_125_G2_ab_2_12_port,
mult_125_G2_ab_2_13_port, mult_125_G2_ab_2_14_port,
mult_125_G2_ab_2_15_port, mult_125_G2_ab_3_0_port,
mult_125_G2_ab_3_1_port, mult_125_G2_ab_3_2_port, mult_125_G2_ab_3_3_port
, mult_125_G2_ab_3_4_port, mult_125_G2_ab_3_5_port,
mult_125_G2_ab_3_6_port, mult_125_G2_ab_3_7_port, mult_125_G2_ab_3_8_port
, mult_125_G2_ab_3_9_port, mult_125_G2_ab_3_10_port,
mult_125_G2_ab_3_11_port, mult_125_G2_ab_3_12_port,
mult_125_G2_ab_3_13_port, mult_125_G2_ab_3_14_port,
mult_125_G2_ab_3_15_port, mult_125_G2_ab_4_0_port,
mult_125_G2_ab_4_1_port, mult_125_G2_ab_4_2_port, mult_125_G2_ab_4_3_port
, mult_125_G2_ab_4_4_port, mult_125_G2_ab_4_5_port,
mult_125_G2_ab_4_6_port, mult_125_G2_ab_4_7_port, mult_125_G2_ab_4_8_port
, mult_125_G2_ab_4_9_port, mult_125_G2_ab_4_10_port,
mult_125_G2_ab_4_11_port, mult_125_G2_ab_4_12_port,
mult_125_G2_ab_4_13_port, mult_125_G2_ab_4_14_port,
mult_125_G2_ab_4_15_port, mult_125_G2_ab_5_0_port,
mult_125_G2_ab_5_1_port, mult_125_G2_ab_5_2_port, mult_125_G2_ab_5_3_port
, mult_125_G2_ab_5_4_port, mult_125_G2_ab_5_5_port,
mult_125_G2_ab_5_6_port, mult_125_G2_ab_5_7_port, mult_125_G2_ab_5_8_port
, mult_125_G2_ab_5_9_port, mult_125_G2_ab_5_10_port,
mult_125_G2_ab_5_11_port, mult_125_G2_ab_5_12_port,
mult_125_G2_ab_5_13_port, mult_125_G2_ab_5_14_port,
mult_125_G2_ab_5_15_port, mult_125_G2_ab_6_0_port,
mult_125_G2_ab_6_1_port, mult_125_G2_ab_6_2_port, mult_125_G2_ab_6_3_port
, mult_125_G2_ab_6_4_port, mult_125_G2_ab_6_5_port,
mult_125_G2_ab_6_6_port, mult_125_G2_ab_6_7_port, mult_125_G2_ab_6_8_port
, mult_125_G2_ab_6_9_port, mult_125_G2_ab_6_10_port,
mult_125_G2_ab_6_11_port, mult_125_G2_ab_6_12_port,
mult_125_G2_ab_6_13_port, mult_125_G2_ab_6_14_port,
mult_125_G2_ab_6_15_port, mult_125_G2_ab_7_0_port,
mult_125_G2_ab_7_1_port, mult_125_G2_ab_7_2_port, mult_125_G2_ab_7_3_port
, mult_125_G2_ab_7_4_port, mult_125_G2_ab_7_5_port,
mult_125_G2_ab_7_6_port, mult_125_G2_ab_7_7_port, mult_125_G2_ab_7_8_port
, mult_125_G2_ab_7_9_port, mult_125_G2_ab_7_10_port,
mult_125_G2_ab_7_11_port, mult_125_G2_ab_7_12_port,
mult_125_G2_ab_7_13_port, mult_125_G2_ab_7_14_port,
mult_125_G2_ab_7_15_port, mult_125_G2_ab_8_0_port,
mult_125_G2_ab_8_1_port, mult_125_G2_ab_8_2_port, mult_125_G2_ab_8_3_port
, mult_125_G2_ab_8_4_port, mult_125_G2_ab_8_5_port,
mult_125_G2_ab_8_6_port, mult_125_G2_ab_8_7_port, mult_125_G2_ab_8_8_port
, mult_125_G2_ab_8_9_port, mult_125_G2_ab_8_10_port,
mult_125_G2_ab_8_11_port, mult_125_G2_ab_8_12_port,
mult_125_G2_ab_8_13_port, mult_125_G2_ab_8_14_port,
mult_125_G2_ab_8_15_port, mult_125_G2_ab_9_0_port,
mult_125_G2_ab_9_1_port, mult_125_G2_ab_9_2_port, mult_125_G2_ab_9_3_port
, mult_125_G2_ab_9_4_port, mult_125_G2_ab_9_5_port,
mult_125_G2_ab_9_6_port, mult_125_G2_ab_9_7_port, mult_125_G2_ab_9_8_port
, mult_125_G2_ab_9_9_port, mult_125_G2_ab_9_10_port,
mult_125_G2_ab_9_11_port, mult_125_G2_ab_9_12_port,
mult_125_G2_ab_9_13_port, mult_125_G2_ab_9_14_port,
mult_125_G2_ab_9_15_port, mult_125_G2_ab_10_0_port,
mult_125_G2_ab_10_1_port, mult_125_G2_ab_10_2_port,
mult_125_G2_ab_10_3_port, mult_125_G2_ab_10_4_port,
mult_125_G2_ab_10_5_port, mult_125_G2_ab_10_6_port,
mult_125_G2_ab_10_7_port, mult_125_G2_ab_10_8_port,
mult_125_G2_ab_10_9_port, mult_125_G2_ab_10_10_port,
mult_125_G2_ab_10_11_port, mult_125_G2_ab_10_12_port,
mult_125_G2_ab_10_13_port, mult_125_G2_ab_10_14_port,
mult_125_G2_ab_10_15_port, mult_125_G2_ab_11_0_port,
mult_125_G2_ab_11_1_port, mult_125_G2_ab_11_2_port,
mult_125_G2_ab_11_3_port, mult_125_G2_ab_11_4_port,
mult_125_G2_ab_11_5_port, mult_125_G2_ab_11_6_port,
mult_125_G2_ab_11_7_port, mult_125_G2_ab_11_8_port,
mult_125_G2_ab_11_9_port, mult_125_G2_ab_11_10_port,
mult_125_G2_ab_11_11_port, mult_125_G2_ab_11_12_port,
mult_125_G2_ab_11_13_port, mult_125_G2_ab_11_14_port,
mult_125_G2_ab_11_15_port, mult_125_G2_ab_12_0_port,
mult_125_G2_ab_12_1_port, mult_125_G2_ab_12_2_port,
mult_125_G2_ab_12_3_port, mult_125_G2_ab_12_4_port,
mult_125_G2_ab_12_5_port, mult_125_G2_ab_12_6_port,
mult_125_G2_ab_12_7_port, mult_125_G2_ab_12_8_port,
mult_125_G2_ab_12_9_port, mult_125_G2_ab_12_10_port,
mult_125_G2_ab_12_11_port, mult_125_G2_ab_12_12_port,
mult_125_G2_ab_12_13_port, mult_125_G2_ab_12_14_port,
mult_125_G2_ab_12_15_port, mult_125_G2_ab_13_0_port,
mult_125_G2_ab_13_1_port, mult_125_G2_ab_13_2_port,
mult_125_G2_ab_13_3_port, mult_125_G2_ab_13_4_port,
mult_125_G2_ab_13_5_port, mult_125_G2_ab_13_6_port,
mult_125_G2_ab_13_7_port, mult_125_G2_ab_13_8_port,
mult_125_G2_ab_13_9_port, mult_125_G2_ab_13_10_port,
mult_125_G2_ab_13_11_port, mult_125_G2_ab_13_12_port,
mult_125_G2_ab_13_13_port, mult_125_G2_ab_13_14_port,
mult_125_G2_ab_13_15_port, mult_125_G2_ab_14_0_port,
mult_125_G2_ab_14_1_port, mult_125_G2_ab_14_2_port,
mult_125_G2_ab_14_3_port, mult_125_G2_ab_14_4_port,
mult_125_G2_ab_14_5_port, mult_125_G2_ab_14_6_port,
mult_125_G2_ab_14_7_port, mult_125_G2_ab_14_8_port,
mult_125_G2_ab_14_9_port, mult_125_G2_ab_14_10_port,
mult_125_G2_ab_14_11_port, mult_125_G2_ab_14_12_port,
mult_125_G2_ab_14_13_port, mult_125_G2_ab_14_14_port,
mult_125_G2_ab_14_15_port, mult_125_G2_ab_15_0_port,
mult_125_G2_ab_15_1_port, mult_125_G2_ab_15_2_port,
mult_125_G2_ab_15_3_port, mult_125_G2_ab_15_4_port,
mult_125_G2_ab_15_5_port, mult_125_G2_ab_15_6_port,
mult_125_G2_ab_15_7_port, mult_125_G2_ab_15_8_port,
mult_125_G2_ab_15_9_port, mult_125_G2_ab_15_10_port,
mult_125_G2_ab_15_11_port, mult_125_G2_ab_15_12_port,
mult_125_G2_ab_15_13_port, mult_125_G2_ab_15_14_port,
mult_125_G2_ab_15_15_port, mult_125_G2_B_not_0_port,
mult_125_G2_B_not_1_port, mult_125_G2_B_not_2_port,
mult_125_G2_B_not_3_port, mult_125_G2_B_not_4_port,
mult_125_G2_B_not_5_port, mult_125_G2_B_not_6_port,
mult_125_G2_B_not_7_port, mult_125_G2_B_not_8_port,
mult_125_G2_B_not_9_port, mult_125_G2_B_not_10_port,
mult_125_G2_B_not_11_port, mult_125_G2_B_not_12_port,
mult_125_G2_B_not_13_port, mult_125_G2_B_not_14_port,
mult_125_G2_B_not_15_port, mult_125_G2_A_not_0_port,
mult_125_G2_A_not_1_port, mult_125_G2_A_not_2_port,
mult_125_G2_A_not_3_port, mult_125_G2_A_not_4_port,
mult_125_G2_A_not_5_port, mult_125_G2_A_not_6_port,
mult_125_G2_A_not_7_port, mult_125_G2_A_not_8_port,
mult_125_G2_A_not_9_port, mult_125_G2_A_not_10_port,
mult_125_G2_A_not_11_port, mult_125_G2_A_not_12_port,
mult_125_G2_A_not_13_port, mult_125_G2_A_not_14_port,
mult_125_G2_A_not_15_port, mult_125_FS_1_C_1_3_3_port,
mult_125_FS_1_C_1_4_0_port, mult_125_FS_1_C_1_4_1_port,
mult_125_FS_1_C_1_4_2_port, mult_125_FS_1_C_1_4_3_port,
mult_125_FS_1_C_1_5_0_port, mult_125_FS_1_C_1_5_1_port,
mult_125_FS_1_C_1_5_2_port, mult_125_FS_1_C_1_5_3_port,
mult_125_FS_1_C_1_6_0_port, mult_125_FS_1_C_1_6_1_port,
mult_125_FS_1_C_1_6_2_port, mult_125_FS_1_C_1_6_3_port,
mult_125_FS_1_C_1_7_0_port, mult_125_FS_1_C_1_7_1_port,
mult_125_FS_1_P_0_0_1_port, mult_125_FS_1_P_0_0_2_port,
mult_125_FS_1_P_0_0_3_port, mult_125_FS_1_P_0_1_1_port,
mult_125_FS_1_P_0_1_2_port, mult_125_FS_1_P_0_1_3_port,
mult_125_FS_1_P_0_2_1_port, mult_125_FS_1_P_0_2_2_port,
mult_125_FS_1_P_0_2_3_port, mult_125_FS_1_P_0_3_1_port,
mult_125_FS_1_P_0_3_2_port, mult_125_FS_1_P_0_3_3_port,
mult_125_FS_1_P_0_4_1_port, mult_125_FS_1_P_0_4_2_port,
mult_125_FS_1_P_0_4_3_port, mult_125_FS_1_P_0_5_1_port,
mult_125_FS_1_P_0_5_2_port, mult_125_FS_1_P_0_5_3_port,
mult_125_FS_1_P_0_6_1_port, mult_125_FS_1_P_0_6_2_port,
mult_125_FS_1_P_0_6_3_port, mult_125_FS_1_P_0_7_1_port,
mult_125_FS_1_TEMP_P_0_0_0_port, mult_125_FS_1_TEMP_P_0_1_0_port,
mult_125_FS_1_TEMP_P_0_2_0_port, mult_125_FS_1_TEMP_P_0_3_0_port,
mult_125_FS_1_TEMP_P_0_4_0_port, mult_125_FS_1_TEMP_P_0_4_1_port,
mult_125_FS_1_TEMP_P_0_4_2_port, mult_125_FS_1_TEMP_P_0_5_0_port,
mult_125_FS_1_TEMP_P_0_5_1_port, mult_125_FS_1_TEMP_P_0_5_2_port,
mult_125_FS_1_TEMP_P_0_6_0_port, mult_125_FS_1_TEMP_P_0_6_1_port,
mult_125_FS_1_TEMP_P_0_6_2_port, mult_125_FS_1_TEMP_P_0_7_0_port,
mult_125_FS_1_G_1_0_3_port, mult_125_FS_1_G_1_1_0_port,
mult_125_FS_1_G_1_1_1_port, mult_125_FS_1_G_1_1_2_port,
mult_125_FS_1_G_2_0_0_port, mult_125_FS_1_TEMP_G_0_3_2_port,
mult_125_FS_1_TEMP_G_0_4_1_port, mult_125_FS_1_TEMP_G_0_4_2_port,
mult_125_FS_1_TEMP_G_0_5_1_port, mult_125_FS_1_TEMP_G_0_5_2_port,
mult_125_FS_1_TEMP_G_0_6_1_port, mult_125_FS_1_TEMP_G_0_6_2_port,
mult_125_FS_1_G_n_int_0_3_2_port, mult_125_FS_1_G_n_int_0_3_3_port,
mult_125_FS_1_G_n_int_0_4_0_port, mult_125_FS_1_G_n_int_0_4_1_port,
mult_125_FS_1_G_n_int_0_4_2_port, mult_125_FS_1_G_n_int_0_4_3_port,
mult_125_FS_1_G_n_int_0_5_0_port, mult_125_FS_1_G_n_int_0_5_1_port,
mult_125_FS_1_G_n_int_0_5_2_port, mult_125_FS_1_G_n_int_0_5_3_port,
mult_125_FS_1_G_n_int_0_6_0_port, mult_125_FS_1_G_n_int_0_6_1_port,
mult_125_FS_1_G_n_int_0_6_2_port, mult_125_FS_1_G_n_int_0_6_3_port,
mult_125_FS_1_G_n_int_0_7_0_port, mult_125_FS_1_G_n_int_0_7_1_port,
mult_125_FS_1_PG_int_0_3_3_port, mult_125_FS_1_PG_int_0_4_0_port,
mult_125_FS_1_PG_int_0_4_1_port, mult_125_FS_1_PG_int_0_4_2_port,
mult_125_FS_1_PG_int_0_4_3_port, mult_125_FS_1_PG_int_0_5_0_port,
mult_125_FS_1_PG_int_0_5_1_port, mult_125_FS_1_PG_int_0_5_2_port,
mult_125_FS_1_PG_int_0_5_3_port, mult_125_FS_1_PG_int_0_6_0_port,
mult_125_FS_1_PG_int_0_6_1_port, mult_125_FS_1_PG_int_0_6_2_port,
mult_125_FS_1_PG_int_0_6_3_port, mult_125_FS_1_PG_int_0_7_0_port,
mult_125_FS_1_PG_int_0_7_1_port, mult_125_A2_14_port, mult_125_A2_15_port
, mult_125_A2_16_port, mult_125_A2_17_port, mult_125_A2_18_port,
mult_125_A2_19_port, mult_125_A2_20_port, mult_125_A2_21_port,
mult_125_A2_22_port, mult_125_A2_23_port, mult_125_A2_24_port,
mult_125_A2_25_port, mult_125_A2_26_port, mult_125_A2_27_port,
mult_125_A2_28_port, mult_125_A2_29_port, mult_125_A1_0_port,
mult_125_A1_1_port, mult_125_A1_2_port, mult_125_A1_3_port,
mult_125_A1_4_port, mult_125_A1_5_port, mult_125_A1_6_port,
mult_125_A1_7_port, mult_125_A1_8_port, mult_125_A1_9_port,
mult_125_A1_10_port, mult_125_A1_11_port, mult_125_A1_12_port,
mult_125_A1_13_port, mult_125_A1_14_port, mult_125_A1_15_port,
mult_125_A1_16_port, mult_125_A1_17_port, mult_125_A1_18_port,
mult_125_A1_19_port, mult_125_A1_20_port, mult_125_A1_21_port,
mult_125_A1_22_port, mult_125_A1_23_port, mult_125_A1_24_port,
mult_125_A1_25_port, mult_125_A1_26_port, mult_125_A1_27_port,
mult_125_A1_28_port, mult_125_A1_29_port, mult_125_ZB, mult_125_ZA,
mult_125_QB, mult_125_QA, mult_125_A_notx_0_port, mult_125_A_notx_1_port,
mult_125_A_notx_2_port, mult_125_A_notx_3_port, mult_125_A_notx_4_port,
mult_125_A_notx_5_port, mult_125_A_notx_6_port, mult_125_A_notx_7_port,
mult_125_A_notx_8_port, mult_125_A_notx_9_port, mult_125_A_notx_10_port,
mult_125_A_notx_11_port, mult_125_A_notx_12_port, mult_125_A_notx_13_port
, mult_125_A_notx_14_port, mult_125_B_notx_0_port, mult_125_B_notx_1_port
, mult_125_B_notx_2_port, mult_125_B_notx_3_port, mult_125_B_notx_4_port,
mult_125_B_notx_5_port, mult_125_B_notx_6_port, mult_125_B_notx_7_port,
mult_125_B_notx_8_port, mult_125_B_notx_9_port, mult_125_B_notx_10_port,
mult_125_B_notx_11_port, mult_125_B_notx_12_port, mult_125_B_notx_13_port
, mult_125_B_notx_14_port, mult_125_ab_0_1_port, mult_125_ab_0_2_port,
mult_125_ab_0_3_port, mult_125_ab_0_4_port, mult_125_ab_0_5_port,
mult_125_ab_0_6_port, mult_125_ab_0_7_port, mult_125_ab_0_8_port,
mult_125_ab_0_9_port, mult_125_ab_0_10_port, mult_125_ab_0_11_port,
mult_125_ab_0_12_port, mult_125_ab_0_13_port, mult_125_ab_0_14_port,
mult_125_ab_0_15_port, mult_125_ab_1_0_port, mult_125_ab_1_1_port,
mult_125_ab_1_2_port, mult_125_ab_1_3_port, mult_125_ab_1_4_port,
mult_125_ab_1_5_port, mult_125_ab_1_6_port, mult_125_ab_1_7_port,
mult_125_ab_1_8_port, mult_125_ab_1_9_port, mult_125_ab_1_10_port,
mult_125_ab_1_11_port, mult_125_ab_1_12_port, mult_125_ab_1_13_port,
mult_125_ab_1_14_port, mult_125_ab_1_15_port, mult_125_ab_2_0_port,
mult_125_ab_2_1_port, mult_125_ab_2_2_port, mult_125_ab_2_3_port,
mult_125_ab_2_4_port, mult_125_ab_2_5_port, mult_125_ab_2_6_port,
mult_125_ab_2_7_port, mult_125_ab_2_8_port, mult_125_ab_2_9_port,
mult_125_ab_2_10_port, mult_125_ab_2_11_port, mult_125_ab_2_12_port,
mult_125_ab_2_13_port, mult_125_ab_2_14_port, mult_125_ab_2_15_port,
mult_125_ab_3_0_port, mult_125_ab_3_1_port, mult_125_ab_3_2_port,
mult_125_ab_3_3_port, mult_125_ab_3_4_port, mult_125_ab_3_5_port,
mult_125_ab_3_6_port, mult_125_ab_3_7_port, mult_125_ab_3_8_port,
mult_125_ab_3_9_port, mult_125_ab_3_10_port, mult_125_ab_3_11_port,
mult_125_ab_3_12_port, mult_125_ab_3_13_port, mult_125_ab_3_14_port,
mult_125_ab_3_15_port, mult_125_ab_4_0_port, mult_125_ab_4_1_port,
mult_125_ab_4_2_port, mult_125_ab_4_3_port, mult_125_ab_4_4_port,
mult_125_ab_4_5_port, mult_125_ab_4_6_port, mult_125_ab_4_7_port,
mult_125_ab_4_8_port, mult_125_ab_4_9_port, mult_125_ab_4_10_port,
mult_125_ab_4_11_port, mult_125_ab_4_12_port, mult_125_ab_4_13_port,
mult_125_ab_4_14_port, mult_125_ab_4_15_port, mult_125_ab_5_0_port,
mult_125_ab_5_1_port, mult_125_ab_5_2_port, mult_125_ab_5_3_port,
mult_125_ab_5_4_port, mult_125_ab_5_5_port, mult_125_ab_5_6_port,
mult_125_ab_5_7_port, mult_125_ab_5_8_port, mult_125_ab_5_9_port,
mult_125_ab_5_10_port, mult_125_ab_5_11_port, mult_125_ab_5_12_port,
mult_125_ab_5_13_port, mult_125_ab_5_14_port, mult_125_ab_5_15_port,
mult_125_ab_6_0_port, mult_125_ab_6_1_port, mult_125_ab_6_2_port,
mult_125_ab_6_3_port, mult_125_ab_6_4_port, mult_125_ab_6_5_port,
mult_125_ab_6_6_port, mult_125_ab_6_7_port, mult_125_ab_6_8_port,
mult_125_ab_6_9_port, mult_125_ab_6_10_port, mult_125_ab_6_11_port,
mult_125_ab_6_12_port, mult_125_ab_6_13_port, mult_125_ab_6_14_port,
mult_125_ab_6_15_port, mult_125_ab_7_0_port, mult_125_ab_7_1_port,
mult_125_ab_7_2_port, mult_125_ab_7_3_port, mult_125_ab_7_4_port,
mult_125_ab_7_5_port, mult_125_ab_7_6_port, mult_125_ab_7_7_port,
mult_125_ab_7_8_port, mult_125_ab_7_9_port, mult_125_ab_7_10_port,
mult_125_ab_7_11_port, mult_125_ab_7_12_port, mult_125_ab_7_13_port,
mult_125_ab_7_14_port, mult_125_ab_7_15_port, mult_125_ab_8_0_port,
mult_125_ab_8_1_port, mult_125_ab_8_2_port, mult_125_ab_8_3_port,
mult_125_ab_8_4_port, mult_125_ab_8_5_port, mult_125_ab_8_6_port,
mult_125_ab_8_7_port, mult_125_ab_8_8_port, mult_125_ab_8_9_port,
mult_125_ab_8_10_port, mult_125_ab_8_11_port, mult_125_ab_8_12_port,
mult_125_ab_8_13_port, mult_125_ab_8_14_port, mult_125_ab_8_15_port,
mult_125_ab_9_0_port, mult_125_ab_9_1_port, mult_125_ab_9_2_port,
mult_125_ab_9_3_port, mult_125_ab_9_4_port, mult_125_ab_9_5_port,
mult_125_ab_9_6_port, mult_125_ab_9_7_port, mult_125_ab_9_8_port,
mult_125_ab_9_9_port, mult_125_ab_9_10_port, mult_125_ab_9_11_port,
mult_125_ab_9_12_port, mult_125_ab_9_13_port, mult_125_ab_9_14_port,
mult_125_ab_9_15_port, mult_125_ab_10_0_port, mult_125_ab_10_1_port,
mult_125_ab_10_2_port, mult_125_ab_10_3_port, mult_125_ab_10_4_port,
mult_125_ab_10_5_port, mult_125_ab_10_6_port, mult_125_ab_10_7_port,
mult_125_ab_10_8_port, mult_125_ab_10_9_port, mult_125_ab_10_10_port,
mult_125_ab_10_11_port, mult_125_ab_10_12_port, mult_125_ab_10_13_port,
mult_125_ab_10_14_port, mult_125_ab_10_15_port, mult_125_ab_11_0_port,
mult_125_ab_11_1_port, mult_125_ab_11_2_port, mult_125_ab_11_3_port,
mult_125_ab_11_4_port, mult_125_ab_11_5_port, mult_125_ab_11_6_port,
mult_125_ab_11_7_port, mult_125_ab_11_8_port, mult_125_ab_11_9_port,
mult_125_ab_11_10_port, mult_125_ab_11_11_port, mult_125_ab_11_12_port,
mult_125_ab_11_13_port, mult_125_ab_11_14_port, mult_125_ab_11_15_port,
mult_125_ab_12_0_port, mult_125_ab_12_1_port, mult_125_ab_12_2_port,
mult_125_ab_12_3_port, mult_125_ab_12_4_port, mult_125_ab_12_5_port,
mult_125_ab_12_6_port, mult_125_ab_12_7_port, mult_125_ab_12_8_port,
mult_125_ab_12_9_port, mult_125_ab_12_10_port, mult_125_ab_12_11_port,
mult_125_ab_12_12_port, mult_125_ab_12_13_port, mult_125_ab_12_14_port,
mult_125_ab_12_15_port, mult_125_ab_13_0_port, mult_125_ab_13_1_port,
mult_125_ab_13_2_port, mult_125_ab_13_3_port, mult_125_ab_13_4_port,
mult_125_ab_13_5_port, mult_125_ab_13_6_port, mult_125_ab_13_7_port,
mult_125_ab_13_8_port, mult_125_ab_13_9_port, mult_125_ab_13_10_port,
mult_125_ab_13_11_port, mult_125_ab_13_12_port, mult_125_ab_13_13_port,
mult_125_ab_13_14_port, mult_125_ab_13_15_port, mult_125_ab_14_0_port,
mult_125_ab_14_1_port, mult_125_ab_14_2_port, mult_125_ab_14_3_port,
mult_125_ab_14_4_port, mult_125_ab_14_5_port, mult_125_ab_14_6_port,
mult_125_ab_14_7_port, mult_125_ab_14_8_port, mult_125_ab_14_9_port,
mult_125_ab_14_10_port, mult_125_ab_14_11_port, mult_125_ab_14_12_port,
mult_125_ab_14_13_port, mult_125_ab_14_14_port, mult_125_ab_14_15_port,
mult_125_ab_15_0_port, mult_125_ab_15_1_port, mult_125_ab_15_2_port,
mult_125_ab_15_3_port, mult_125_ab_15_4_port, mult_125_ab_15_5_port,
mult_125_ab_15_6_port, mult_125_ab_15_7_port, mult_125_ab_15_8_port,
mult_125_ab_15_9_port, mult_125_ab_15_10_port, mult_125_ab_15_11_port,
mult_125_ab_15_12_port, mult_125_ab_15_13_port, mult_125_ab_15_14_port,
mult_125_ab_15_15_port, mult_125_B_not_0_port, mult_125_B_not_1_port,
mult_125_B_not_2_port, mult_125_B_not_3_port, mult_125_B_not_4_port,
mult_125_B_not_5_port, mult_125_B_not_6_port, mult_125_B_not_7_port,
mult_125_B_not_8_port, mult_125_B_not_9_port, mult_125_B_not_10_port,
mult_125_B_not_11_port, mult_125_B_not_12_port, mult_125_B_not_13_port,
mult_125_B_not_14_port, mult_125_B_not_15_port, mult_125_A_not_0_port,
mult_125_A_not_1_port, mult_125_A_not_2_port, mult_125_A_not_3_port,
mult_125_A_not_4_port, mult_125_A_not_5_port, mult_125_A_not_6_port,
mult_125_A_not_7_port, mult_125_A_not_8_port, mult_125_A_not_9_port,
mult_125_A_not_10_port, mult_125_A_not_11_port, mult_125_A_not_12_port,
mult_125_A_not_13_port, mult_125_A_not_14_port, mult_125_A_not_15_port,
mult_125_G4_FS_1_C_1_3_3_port, mult_125_G4_FS_1_C_1_4_0_port,
mult_125_G4_FS_1_C_1_4_1_port, mult_125_G4_FS_1_C_1_4_2_port,
mult_125_G4_FS_1_C_1_4_3_port, mult_125_G4_FS_1_C_1_5_0_port,
mult_125_G4_FS_1_C_1_5_1_port, mult_125_G4_FS_1_C_1_5_2_port,
mult_125_G4_FS_1_C_1_5_3_port, mult_125_G4_FS_1_C_1_6_0_port,
mult_125_G4_FS_1_C_1_6_1_port, mult_125_G4_FS_1_C_1_6_2_port,
mult_125_G4_FS_1_C_1_6_3_port, mult_125_G4_FS_1_C_1_7_0_port,
mult_125_G4_FS_1_C_1_7_1_port, mult_125_G4_FS_1_P_0_0_1_port,
mult_125_G4_FS_1_P_0_0_2_port, mult_125_G4_FS_1_P_0_0_3_port,
mult_125_G4_FS_1_P_0_1_1_port, mult_125_G4_FS_1_P_0_1_2_port,
mult_125_G4_FS_1_P_0_1_3_port, mult_125_G4_FS_1_P_0_2_1_port,
mult_125_G4_FS_1_P_0_2_2_port, mult_125_G4_FS_1_P_0_2_3_port,
mult_125_G4_FS_1_P_0_3_1_port, mult_125_G4_FS_1_P_0_3_2_port,
mult_125_G4_FS_1_P_0_3_3_port, mult_125_G4_FS_1_P_0_4_1_port,
mult_125_G4_FS_1_P_0_4_2_port, mult_125_G4_FS_1_P_0_4_3_port,
mult_125_G4_FS_1_P_0_5_1_port, mult_125_G4_FS_1_P_0_5_2_port,
mult_125_G4_FS_1_P_0_5_3_port, mult_125_G4_FS_1_P_0_6_1_port,
mult_125_G4_FS_1_P_0_6_2_port, mult_125_G4_FS_1_P_0_6_3_port,
mult_125_G4_FS_1_P_0_7_1_port, mult_125_G4_FS_1_TEMP_P_0_0_0_port,
mult_125_G4_FS_1_TEMP_P_0_1_0_port, mult_125_G4_FS_1_TEMP_P_0_2_0_port,
mult_125_G4_FS_1_TEMP_P_0_3_0_port, mult_125_G4_FS_1_TEMP_P_0_4_0_port,
mult_125_G4_FS_1_TEMP_P_0_4_1_port, mult_125_G4_FS_1_TEMP_P_0_4_2_port,
mult_125_G4_FS_1_TEMP_P_0_5_0_port, mult_125_G4_FS_1_TEMP_P_0_5_1_port,
mult_125_G4_FS_1_TEMP_P_0_5_2_port, mult_125_G4_FS_1_TEMP_P_0_6_0_port,
mult_125_G4_FS_1_TEMP_P_0_6_1_port, mult_125_G4_FS_1_TEMP_P_0_6_2_port,
mult_125_G4_FS_1_TEMP_P_0_7_0_port, mult_125_G4_FS_1_G_1_0_3_port,
mult_125_G4_FS_1_G_1_1_0_port, mult_125_G4_FS_1_G_1_1_1_port,
mult_125_G4_FS_1_G_1_1_2_port, mult_125_G4_FS_1_G_2_0_0_port,
mult_125_G4_FS_1_TEMP_G_0_3_2_port, mult_125_G4_FS_1_TEMP_G_0_4_1_port,
mult_125_G4_FS_1_TEMP_G_0_4_2_port, mult_125_G4_FS_1_TEMP_G_0_5_1_port,
mult_125_G4_FS_1_TEMP_G_0_5_2_port, mult_125_G4_FS_1_TEMP_G_0_6_1_port,
mult_125_G4_FS_1_TEMP_G_0_6_2_port, mult_125_G4_FS_1_G_n_int_0_3_2_port,
mult_125_G4_FS_1_G_n_int_0_3_3_port, mult_125_G4_FS_1_G_n_int_0_4_0_port,
mult_125_G4_FS_1_G_n_int_0_4_1_port, mult_125_G4_FS_1_G_n_int_0_4_2_port,
mult_125_G4_FS_1_G_n_int_0_4_3_port, mult_125_G4_FS_1_G_n_int_0_5_0_port,
mult_125_G4_FS_1_G_n_int_0_5_1_port, mult_125_G4_FS_1_G_n_int_0_5_2_port,
mult_125_G4_FS_1_G_n_int_0_5_3_port, mult_125_G4_FS_1_G_n_int_0_6_0_port,
mult_125_G4_FS_1_G_n_int_0_6_1_port, mult_125_G4_FS_1_G_n_int_0_6_2_port,
mult_125_G4_FS_1_G_n_int_0_6_3_port, mult_125_G4_FS_1_G_n_int_0_7_0_port,
mult_125_G4_FS_1_G_n_int_0_7_1_port, mult_125_G4_FS_1_PG_int_0_3_3_port,
mult_125_G4_FS_1_PG_int_0_4_0_port, mult_125_G4_FS_1_PG_int_0_4_1_port,
mult_125_G4_FS_1_PG_int_0_4_2_port, mult_125_G4_FS_1_PG_int_0_4_3_port,
mult_125_G4_FS_1_PG_int_0_5_0_port, mult_125_G4_FS_1_PG_int_0_5_1_port,
mult_125_G4_FS_1_PG_int_0_5_2_port, mult_125_G4_FS_1_PG_int_0_5_3_port,
mult_125_G4_FS_1_PG_int_0_6_0_port, mult_125_G4_FS_1_PG_int_0_6_1_port,
mult_125_G4_FS_1_PG_int_0_6_2_port, mult_125_G4_FS_1_PG_int_0_6_3_port,
mult_125_G4_FS_1_PG_int_0_7_0_port, mult_125_G4_FS_1_PG_int_0_7_1_port,
mult_125_G4_A2_14_port, mult_125_G4_A2_15_port, mult_125_G4_A2_16_port,
mult_125_G4_A2_17_port, mult_125_G4_A2_18_port, mult_125_G4_A2_19_port,
mult_125_G4_A2_20_port, mult_125_G4_A2_21_port, mult_125_G4_A2_22_port,
mult_125_G4_A2_23_port, mult_125_G4_A2_24_port, mult_125_G4_A2_25_port,
mult_125_G4_A2_26_port, mult_125_G4_A2_27_port, mult_125_G4_A2_28_port,
mult_125_G4_A2_29_port, mult_125_G4_A1_0_port, mult_125_G4_A1_1_port,
mult_125_G4_A1_2_port, mult_125_G4_A1_3_port, mult_125_G4_A1_4_port,
mult_125_G4_A1_5_port, mult_125_G4_A1_6_port, mult_125_G4_A1_7_port,
mult_125_G4_A1_8_port, mult_125_G4_A1_9_port, mult_125_G4_A1_10_port,
mult_125_G4_A1_11_port, mult_125_G4_A1_12_port, mult_125_G4_A1_13_port,
mult_125_G4_A1_14_port, mult_125_G4_A1_15_port, mult_125_G4_A1_16_port,
mult_125_G4_A1_17_port, mult_125_G4_A1_18_port, mult_125_G4_A1_19_port,
mult_125_G4_A1_20_port, mult_125_G4_A1_21_port, mult_125_G4_A1_22_port,
mult_125_G4_A1_23_port, mult_125_G4_A1_24_port, mult_125_G4_A1_25_port,
mult_125_G4_A1_26_port, mult_125_G4_A1_27_port, mult_125_G4_A1_28_port,
mult_125_G4_A1_29_port, mult_125_G4_ZB, mult_125_G4_ZA, mult_125_G4_QB,
mult_125_G4_QA, mult_125_G4_A_notx_0_port, mult_125_G4_A_notx_1_port,
mult_125_G4_A_notx_2_port, mult_125_G4_A_notx_3_port,
mult_125_G4_A_notx_4_port, mult_125_G4_A_notx_5_port,
mult_125_G4_A_notx_6_port, mult_125_G4_A_notx_7_port,
mult_125_G4_A_notx_8_port, mult_125_G4_A_notx_9_port,
mult_125_G4_A_notx_10_port, mult_125_G4_A_notx_11_port,
mult_125_G4_A_notx_12_port, mult_125_G4_A_notx_13_port,
mult_125_G4_A_notx_14_port, mult_125_G4_B_notx_0_port,
mult_125_G4_B_notx_1_port, mult_125_G4_B_notx_2_port,
mult_125_G4_B_notx_3_port, mult_125_G4_B_notx_4_port,
mult_125_G4_B_notx_5_port, mult_125_G4_B_notx_6_port,
mult_125_G4_B_notx_7_port, mult_125_G4_B_notx_8_port,
mult_125_G4_B_notx_9_port, mult_125_G4_B_notx_10_port,
mult_125_G4_B_notx_11_port, mult_125_G4_B_notx_12_port,
mult_125_G4_B_notx_13_port, mult_125_G4_B_notx_14_port,
mult_125_G4_ab_0_1_port, mult_125_G4_ab_0_2_port, mult_125_G4_ab_0_3_port
, mult_125_G4_ab_0_4_port, mult_125_G4_ab_0_5_port,
mult_125_G4_ab_0_6_port, mult_125_G4_ab_0_7_port, mult_125_G4_ab_0_8_port
, mult_125_G4_ab_0_9_port, mult_125_G4_ab_0_10_port,
mult_125_G4_ab_0_11_port, mult_125_G4_ab_0_12_port,
mult_125_G4_ab_0_13_port, mult_125_G4_ab_0_14_port,
mult_125_G4_ab_0_15_port, mult_125_G4_ab_1_0_port,
mult_125_G4_ab_1_1_port, mult_125_G4_ab_1_2_port, mult_125_G4_ab_1_3_port
, mult_125_G4_ab_1_4_port, mult_125_G4_ab_1_5_port,
mult_125_G4_ab_1_6_port, mult_125_G4_ab_1_7_port, mult_125_G4_ab_1_8_port
, mult_125_G4_ab_1_9_port, mult_125_G4_ab_1_10_port,
mult_125_G4_ab_1_11_port, mult_125_G4_ab_1_12_port,
mult_125_G4_ab_1_13_port, mult_125_G4_ab_1_14_port,
mult_125_G4_ab_1_15_port, mult_125_G4_ab_2_0_port,
mult_125_G4_ab_2_1_port, mult_125_G4_ab_2_2_port, mult_125_G4_ab_2_3_port
, mult_125_G4_ab_2_4_port, mult_125_G4_ab_2_5_port,
mult_125_G4_ab_2_6_port, mult_125_G4_ab_2_7_port, mult_125_G4_ab_2_8_port
, mult_125_G4_ab_2_9_port, mult_125_G4_ab_2_10_port,
mult_125_G4_ab_2_11_port, mult_125_G4_ab_2_12_port,
mult_125_G4_ab_2_13_port, mult_125_G4_ab_2_14_port,
mult_125_G4_ab_2_15_port, mult_125_G4_ab_3_0_port,
mult_125_G4_ab_3_1_port, mult_125_G4_ab_3_2_port, mult_125_G4_ab_3_3_port
, mult_125_G4_ab_3_4_port, mult_125_G4_ab_3_5_port,
mult_125_G4_ab_3_6_port, mult_125_G4_ab_3_7_port, mult_125_G4_ab_3_8_port
, mult_125_G4_ab_3_9_port, mult_125_G4_ab_3_10_port,
mult_125_G4_ab_3_11_port, mult_125_G4_ab_3_12_port,
mult_125_G4_ab_3_13_port, mult_125_G4_ab_3_14_port,
mult_125_G4_ab_3_15_port, mult_125_G4_ab_4_0_port,
mult_125_G4_ab_4_1_port, mult_125_G4_ab_4_2_port, mult_125_G4_ab_4_3_port
, mult_125_G4_ab_4_4_port, mult_125_G4_ab_4_5_port,
mult_125_G4_ab_4_6_port, mult_125_G4_ab_4_7_port, mult_125_G4_ab_4_8_port
, mult_125_G4_ab_4_9_port, mult_125_G4_ab_4_10_port,
mult_125_G4_ab_4_11_port, mult_125_G4_ab_4_12_port,
mult_125_G4_ab_4_13_port, mult_125_G4_ab_4_14_port,
mult_125_G4_ab_4_15_port, mult_125_G4_ab_5_0_port,
mult_125_G4_ab_5_1_port, mult_125_G4_ab_5_2_port, mult_125_G4_ab_5_3_port
, mult_125_G4_ab_5_4_port, mult_125_G4_ab_5_5_port,
mult_125_G4_ab_5_6_port, mult_125_G4_ab_5_7_port, mult_125_G4_ab_5_8_port
, mult_125_G4_ab_5_9_port, mult_125_G4_ab_5_10_port,
mult_125_G4_ab_5_11_port, mult_125_G4_ab_5_12_port,
mult_125_G4_ab_5_13_port, mult_125_G4_ab_5_14_port,
mult_125_G4_ab_5_15_port, mult_125_G4_ab_6_0_port,
mult_125_G4_ab_6_1_port, mult_125_G4_ab_6_2_port, mult_125_G4_ab_6_3_port
, mult_125_G4_ab_6_4_port, mult_125_G4_ab_6_5_port,
mult_125_G4_ab_6_6_port, mult_125_G4_ab_6_7_port, mult_125_G4_ab_6_8_port
, mult_125_G4_ab_6_9_port, mult_125_G4_ab_6_10_port,
mult_125_G4_ab_6_11_port, mult_125_G4_ab_6_12_port,
mult_125_G4_ab_6_13_port, mult_125_G4_ab_6_14_port,
mult_125_G4_ab_6_15_port, mult_125_G4_ab_7_0_port,
mult_125_G4_ab_7_1_port, mult_125_G4_ab_7_2_port, mult_125_G4_ab_7_3_port
, mult_125_G4_ab_7_4_port, mult_125_G4_ab_7_5_port,
mult_125_G4_ab_7_6_port, mult_125_G4_ab_7_7_port, mult_125_G4_ab_7_8_port
, mult_125_G4_ab_7_9_port, mult_125_G4_ab_7_10_port,
mult_125_G4_ab_7_11_port, mult_125_G4_ab_7_12_port,
mult_125_G4_ab_7_13_port, mult_125_G4_ab_7_14_port,
mult_125_G4_ab_7_15_port, mult_125_G4_ab_8_0_port,
mult_125_G4_ab_8_1_port, mult_125_G4_ab_8_2_port, mult_125_G4_ab_8_3_port
, mult_125_G4_ab_8_4_port, mult_125_G4_ab_8_5_port,
mult_125_G4_ab_8_6_port, mult_125_G4_ab_8_7_port, mult_125_G4_ab_8_8_port
, mult_125_G4_ab_8_9_port, mult_125_G4_ab_8_10_port,
mult_125_G4_ab_8_11_port, mult_125_G4_ab_8_12_port,
mult_125_G4_ab_8_13_port, mult_125_G4_ab_8_14_port,
mult_125_G4_ab_8_15_port, mult_125_G4_ab_9_0_port,
mult_125_G4_ab_9_1_port, mult_125_G4_ab_9_2_port, mult_125_G4_ab_9_3_port
, mult_125_G4_ab_9_4_port, mult_125_G4_ab_9_5_port,
mult_125_G4_ab_9_6_port, mult_125_G4_ab_9_7_port, mult_125_G4_ab_9_8_port
, mult_125_G4_ab_9_9_port, mult_125_G4_ab_9_10_port,
mult_125_G4_ab_9_11_port, mult_125_G4_ab_9_12_port,
mult_125_G4_ab_9_13_port, mult_125_G4_ab_9_14_port,
mult_125_G4_ab_9_15_port, mult_125_G4_ab_10_0_port,
mult_125_G4_ab_10_1_port, mult_125_G4_ab_10_2_port,
mult_125_G4_ab_10_3_port, mult_125_G4_ab_10_4_port,
mult_125_G4_ab_10_5_port, mult_125_G4_ab_10_6_port,
mult_125_G4_ab_10_7_port, mult_125_G4_ab_10_8_port,
mult_125_G4_ab_10_9_port, mult_125_G4_ab_10_10_port,
mult_125_G4_ab_10_11_port, mult_125_G4_ab_10_12_port,
mult_125_G4_ab_10_13_port, mult_125_G4_ab_10_14_port,
mult_125_G4_ab_10_15_port, mult_125_G4_ab_11_0_port,
mult_125_G4_ab_11_1_port, mult_125_G4_ab_11_2_port,
mult_125_G4_ab_11_3_port, mult_125_G4_ab_11_4_port,
mult_125_G4_ab_11_5_port, mult_125_G4_ab_11_6_port,
mult_125_G4_ab_11_7_port, mult_125_G4_ab_11_8_port,
mult_125_G4_ab_11_9_port, mult_125_G4_ab_11_10_port,
mult_125_G4_ab_11_11_port, mult_125_G4_ab_11_12_port,
mult_125_G4_ab_11_13_port, mult_125_G4_ab_11_14_port,
mult_125_G4_ab_11_15_port, mult_125_G4_ab_12_0_port,
mult_125_G4_ab_12_1_port, mult_125_G4_ab_12_2_port,
mult_125_G4_ab_12_3_port, mult_125_G4_ab_12_4_port,
mult_125_G4_ab_12_5_port, mult_125_G4_ab_12_6_port,
mult_125_G4_ab_12_7_port, mult_125_G4_ab_12_8_port,
mult_125_G4_ab_12_9_port, mult_125_G4_ab_12_10_port,
mult_125_G4_ab_12_11_port, mult_125_G4_ab_12_12_port,
mult_125_G4_ab_12_13_port, mult_125_G4_ab_12_14_port,
mult_125_G4_ab_12_15_port, mult_125_G4_ab_13_0_port,
mult_125_G4_ab_13_1_port, mult_125_G4_ab_13_2_port,
mult_125_G4_ab_13_3_port, mult_125_G4_ab_13_4_port,
mult_125_G4_ab_13_5_port, mult_125_G4_ab_13_6_port,
mult_125_G4_ab_13_7_port, mult_125_G4_ab_13_8_port,
mult_125_G4_ab_13_9_port, mult_125_G4_ab_13_10_port,
mult_125_G4_ab_13_11_port, mult_125_G4_ab_13_12_port,
mult_125_G4_ab_13_13_port, mult_125_G4_ab_13_14_port,
mult_125_G4_ab_13_15_port, mult_125_G4_ab_14_0_port,
mult_125_G4_ab_14_1_port, mult_125_G4_ab_14_2_port,
mult_125_G4_ab_14_3_port, mult_125_G4_ab_14_4_port,
mult_125_G4_ab_14_5_port, mult_125_G4_ab_14_6_port,
mult_125_G4_ab_14_7_port, mult_125_G4_ab_14_8_port,
mult_125_G4_ab_14_9_port, mult_125_G4_ab_14_10_port,
mult_125_G4_ab_14_11_port, mult_125_G4_ab_14_12_port,
mult_125_G4_ab_14_13_port, mult_125_G4_ab_14_14_port,
mult_125_G4_ab_14_15_port, mult_125_G4_ab_15_0_port,
mult_125_G4_ab_15_1_port, mult_125_G4_ab_15_2_port,
mult_125_G4_ab_15_3_port, mult_125_G4_ab_15_4_port,
mult_125_G4_ab_15_5_port, mult_125_G4_ab_15_6_port,
mult_125_G4_ab_15_7_port, mult_125_G4_ab_15_8_port,
mult_125_G4_ab_15_9_port, mult_125_G4_ab_15_10_port,
mult_125_G4_ab_15_11_port, mult_125_G4_ab_15_12_port,
mult_125_G4_ab_15_13_port, mult_125_G4_ab_15_14_port,
mult_125_G4_ab_15_15_port, mult_125_G4_B_not_0_port,
mult_125_G4_B_not_1_port, mult_125_G4_B_not_2_port,
mult_125_G4_B_not_3_port, mult_125_G4_B_not_4_port,
mult_125_G4_B_not_5_port, mult_125_G4_B_not_6_port,
mult_125_G4_B_not_7_port, mult_125_G4_B_not_8_port,
mult_125_G4_B_not_9_port, mult_125_G4_B_not_10_port,
mult_125_G4_B_not_11_port, mult_125_G4_B_not_12_port,
mult_125_G4_B_not_13_port, mult_125_G4_B_not_14_port,
mult_125_G4_B_not_15_port, mult_125_G4_A_not_0_port,
mult_125_G4_A_not_1_port, mult_125_G4_A_not_2_port,
mult_125_G4_A_not_3_port, mult_125_G4_A_not_4_port,
mult_125_G4_A_not_5_port, mult_125_G4_A_not_6_port,
mult_125_G4_A_not_7_port, mult_125_G4_A_not_8_port,
mult_125_G4_A_not_9_port, mult_125_G4_A_not_10_port,
mult_125_G4_A_not_11_port, mult_125_G4_A_not_12_port,
mult_125_G4_A_not_13_port, mult_125_G4_A_not_14_port,
mult_125_G4_A_not_15_port, n240, n241, n242, n243, n244, n245, n246, n247
, n248, n249, n250, n251, n252, n253, n254, n255, n256, n257, n258, n259,
n260, n261, n262, n263, n264, n265, n266, n267, n268, n269, n270, n271,
n272, n273, n274, n275, n276, n277, n278, n279, n280, n281, n282, n283,
n284, n285, n286, n287, n288, n289, n290, n291, n292, n293, n294, n295,
n296, n297, n298, n299, n300, n301, n302, n303, n304, n305, n306, n307,
n308, n309, n310, n311, n312, n313, n314, n315, n316, n317, n318, n319,
n320, n321, n322, n323, n324, n325, n326, n327, n328, n329, n330, n331,
n332, n333, n334, n335, n336, n337, n338, n339, n340, n341, n342, n343,
n344, n345, n346, n347, n348, n349, n350, n351, n352, n353, n354, n355,
n356, n357, n358, n359, n360, n361, n362, n363, n364, n365, n366, n367,
n368, n369, n370, n371, n372, n373, n374, n375, n376, n377, n378, n379,
n380, n381, n382, n383, n384, n385, n386, n387, n388, n389, n390, n391,
n392, n393, n394, n395, n396, n397, n398, n399, n400, n401, n402, n403,
n404, n405, n406, n407, n408, n409, n410, n411, n412, n413, n414, n415,
n416, n417, n418, n419, n420, n421, n422, n423, n424, n425, n426, n427,
n428, n429, n430, n431, n432, n433, n434, n435, n436, n437, n438, n439,
n440, n441, n442, n443, n444, n445, n446, n447, n448, n449, n450, n451,
n452, n453, n454, n455, n456, n457, n458, n459, n460, n461, n462, n463,
n464, n465, n466, n467, n468, n469, n470, n471, n472, n473, n474, n475,
n476, n477, n478, n479, n480, n481, n482, n483, n484, n485, n486, n487,
n488, n489, n490, n491, n492, n493, n494, n495, n496, n497, n498, n499,
n500, n501, n502, n503, n504, n505, n506, n507, n508, n509, n510, n511,
n512, n513, n514, n515, n516, n517, n518, n519, n520, n521, n522, n523,
n524, n525, n526, n527, n528, n529, n530, n531, n532, n533, n534, n535,
n536, n537, n538, n539, n540, n541, n542, n543, n544, n545, n546, n547,
n548, n549, n550, n551, n552, n553, n554, n555, n556, n557, n558, n559,
n560, n561, n562, n563, n564, n565, n566, n567, n568, n569, n570, n571,
n572, n573, n574, n575, n576, n577, n578, n579, n580, n581, n582, n583,
n584, n585, n586, n587, n588, n589, n590, n591, n592, n593, n594, n595,
n596, n597, n598, n599, n600, n601, n602, n603, n604, n605, n606, n607,
n608, n609, n610, n611, n612, n613, n614, n615, n616, n617, n618, n619,
n620, n621, n622, n623, n624, n625, n626, n627, n628, n629, n630, n631,
n632, n633, n634, n635, n636, n637, n638, n639, n640, n641, n642, n643,
n644, n645, n646, n647, n648, n649, n650, n651, n652, n653, n654, n655,
n656, n657, n658, n659, n660, n661, n662, n663, n664, n665, n666, n667,
n668, n669, n670, n671, n672, n673, n674, n675, n676, n677, n678, n679,
n680, n681, n682, n683, n684, n685, n686, n687, n688, n689, n690, n691,
n692, n693, n694, n695, n696, n697, n698, n699, n700, n701, n702, n703,
n704, n705, n706, n707, n708, n709, n710, n711, n712, n713, n714, n715,
n716, n717, n718, n719, n720, n721, n722, n723, n724, n725, n726, n727,
n728, n729, n730, n731, n732, n733, n734, n735, n736, n737, n738, n739,
n740, n741, n742, n743, n744, n745, n746, n747, n748, n749, n750, n751,
n752, n753, n754, n755, n756, n757, n758, n759, n760, n761, n762, n763,
n764, n765, n766, n767, n768, n769, n770, n771, n772, n773, n774, n775,
n776, n777, n778, n779, n780, n781, n782, n783, n784, n785, n786, n787,
n788, n789, n790, n791, n792, n793, n794, n795, n796, n797, n798, n799,
n800, n801, n802, n803, n804, n805, n806, n807, n808, n809, n810, n811,
n812, n813, n814, n815, n816, n817, n818, n819, n820, n821, n822, n823,
n824, n825, n826, n827, n828, n829, n830, n831, n832, n833, n834, n835,
n836, n837, n838, n839, n840, n841, n842, n843, n844, n845, n846, n847,
n848, n849, n850, n851, n852, n853, n854, n855, n856, n857, n858, n859,
n860, n861, n862, n863, n864, n865, n866, n867, n868, n869, n870, n871,
n872, n873, n874, n875, n876, n877, n878, n879, n880, n881, n882, n883,
n884, n885, n886, n887, n888, n889, n890, n891, n892, n893, n894, n895,
n896, n897, n898, n899, n900, n901, n902, n903, n904, n905, n906, n907,
n908, n909, n910, n911, n912, n913, n914, n915, n916, n917, n918, n919,
n920, n921, n922, n923, n924, n925, n926, n927, n928, n929, n930, n931,
n932, n933, n934, n935, n936, n937, n938, n939, n940, n941, n942, n943,
n944, n945, n946, n947, n948, n949, n950, n951, n952, n953, n954, n955,
n956, n957, n958, n959, n960, n961, n962, n963, n964, n965, n966, n967,
n968, n969, n970, n971, n972, n973, n974, n975, n976, n977, n978, n979,
n980, n981, n982, n983, n984, n985, n986, n987, n988, n989, n990, n991,
n992, n993, n994, n995, n996, n997, n998, n999, n1000, n1001, n1002,
n1003, n1004, n1005, n1006, n1007, n1008, n1009, n1010, n1011, n1012,
n1013, n1014, n1015, n1016, n1017, n1018, n1019, n1020, n1021, n1022,
n1023, n1024, n1025, n1026, n1027, n1028, n1029, n1030, n1031, n1032,
n1033, n1034, n1035, n1036, n1037, n1038, n1039, n1040, n1041, n1042,
n1043, n1044, n1045, n1046, n1047, n1048, n1049, n1050, n1051, n1052,
n1053, n1054, n1055, n1056, n1057, n1058, n1059, n1060, n1061, n1062,
n1063, n1064, n1065, n1066, n1067, n1068, n1069, n1070, n1071, n1072,
n1073, n1074, n1075, n1076, n1077, n1078, n1079, n1080, n1081, n1082,
n1083, n1084, n1085, n1086, n1087, n1088, n1089, n1090, n1091, n1092,
n1093, n1094, n1095, n1096, n1097, n1098, n1099, n1100, n1101, n1102,
n1103, n1104, n1105, n1106, n1107, n1108, n1109, n1110, n1111, n1112,
n1113, n1114, n1115, n1116, n1117, n1118, n1119, n1120, n1121, n1122,
n1123, n1124, n1125, n1126, n1127, n1128, n1129, n1130, n1131, n1132,
n1133, n1134, n1135, n1136, n1137, n1138, n1139, n1140, n1141, n1142,
n1143, n1144, n1145, n1146, n1147, n1148, n1149, n1150, n1151, n1152,
n1153, n1154, n1155, n1156, n1157, n1158, n1159, n1160, n1161, n1162,
n1163, n1164, n1165, n1166, n1167, n1168, n1169, n1170, n1171, n1172,
n1173, n1174, n1175, n1176, n1177, n1178, n1179, n1180, n1181, n1182,
n1183, n1184, n1185, n1186, n1187, n1188, n1189, n1190, n1191, n1192,
n1193, n1194, n1195, n1196, n1197, n1198, n1199, n1200, n1201, n1202,
n1203, n1204, n1205, n1206, n1207, n1208, n1209, n1210, n1211, n1212,
n1213, n1214, n1215, n1216, n1217, n1218, n1219, n1220, n1221, n1222,
n1223, n1224, n1225, n1226, n1227, n1228, n1229, n1230, n1231, n1232,
n1233, n1234, n1235, n1236, n1237, n1238, n1239, n1240, n1241, n1242,
n1243, n1244, n1245, n1246, n1247, n1248, n1249, n1250, n1251, n1252,
n1253, n1254, n1255, n1256, n1257, n1258, n1259, n1260, n1261, n1262,
n1263, n1264, n1265, n1266, n1267, n1268, n1269, n1270, n1271, n1272,
n1273, n1274, n1275, n1276, n1277, n1278, n1279, n1280, n1281, n1282,
n1283, n1284, n1285, n1286, n1287, n1288, n1289, n1290, n1291, n1292,
n1293, n1294, n1295, n1296, n1297, n1298, n1299, n1300, n1301, n1302,
n1303, n1304, n1305, n1306, n1307, n1308, n1309, n1310, n1311, n1312,
n1313, n1314, n1315, n1316, n1317, n1318, n1319, n1320, n1321, n1322,
n1323, n1324, n1325, n1326, n1327, n1328, n1329, n1330, n1331, n1332,
n1333, n1334, n1335, n1336, n1337, n1338, n1339, n1340, n1341, n1342,
n1343, n1344, n1345, n1346, n1347, n1348, n1349, n1350, n1351, n1352,
n1353, n1354, n1355, n1356, n1357, n1358, n1359, n1360, n1361, n1362,
n1363, n1364, n1365, n1366, n1367, n1368, n1369, n1370, n1371, n1372,
n1373, n1374, n1375, n1376, n1377, n1378, n1379, n1380, n1381, n1382,
n1383, n1384, n1385, n1386, n1387, n1388, n1389, n1390, n1391, n1392,
n1393, n1394, n1395, n1396, n1397, n1398, n1399, n1400, n1401, n1402,
n1403, n1404, n1405, n1406, n1407, n1408, n1409, n1410, n1411, n1412,
n1413, n1414, n1415, n1416, n1417, n1418, n1419, n1420, n1421, n1422,
n1423, n1424, n1425, n1426, n1427, n1428, n1429, n1430, n1431, n1432,
n1433, n1434, n1435, n1436, n1437, n1438, n1439, n1440, n1441, n1442,
n1443, n1444, n1445, n1446, n1447, n1448, n1449, n1450, n1451, n1452,
n1453, n1454, n1455, n1456, n1457, n1458, n1459, n1460, n1461, n1462,
n1463, n1464, n1465, n1466, n1467, n1468, n1469, n1470, n1471, n1472,
n1473, n1474, n1475, n1476, n1477, n1478, n1479, n1480, n1481, n1482,
n1483, n1484, n1485, n1486, n1487, n1488, n1489, n1490, n1491, n1492,
n1493, n1494, n1495, n1496, n1497, n1498, n1499, n1500, n1501, n1502,
n1503, n1504, n1505, n1506, n1507, n1508, n1509, n1510, n1511, n1512,
n1513, n1514, n1515, n1516, n1517, n1518, n1519, n1520, n1521, n1522,
n1523, n1524, n1525, n1526, n1527, n1528, n1529, n1530, n1531, n1532,
n1533, n1534, n1535, n1536, n1537, n1538, n1539, n1540, n1541, n1542,
n1543, n1544, n1545, n1546, n1547, n1548, n1549, n1550, n1551, n1552,
n1553, n1554, n1555, n1556, n1557, n1558, n1559, n1560, n1561, n1562,
n1563, n1564, n1565, n1566, n1567, n1568, n1569, n1570, n1571, n1572,
n1573, n1574, n1575, n1576, n1577, n1578, n1579, n1580, n1581, n1582,
n1583, n1584, n1585, n1586, n1587, n1588, n1589, n1590, n1591, n1592,
n1593, n1594, n1595, n1596, n1597, n1598, n1599, n1600, n1601, n1602,
n1603, n1604, n1605, n1606, n1607, n1608, n1609, n1610, n1611, n1612,
n1613, n1614, n1615, n1616, n1617, n1618, n1619, n1620, n1621, n1622,
n1623, n1624, n1625, n1626, n1627, n1628, n1629, n1630, n1631, n1632,
n1633, n1634, n1635, n1636, n1637, n1638, n1639, n1640, n1641, n1642,
n1643, n1644, n1645, n1646, n1647, n1648, n1649, n1650, n1651, n1652,
n1653, n1654, n1655, n1656, n1657, n1658, n1659, n1660, n1661, n1662,
n1663, n1664, n1665, n1666, n1667, n1668, n1669, n1670, n1671, n1672,
n1673, n1674, n1675, n1676, n1677, n1678, n1679, n1680, n1681, n1682,
n1683, n1684, n1685, n1686, n1687, n1688, n1689, n1690, n1691, n1692,
n1693, n1694, n1695, n1696, n1697, n1698, n1699, n1700, n1701, n1702,
n1703, n1704, n1705, n1706, n1707, n1708, n1709, n1710, n1711, n1712,
n1713, n1714, n1715, n1716, n1717, n1718, n1719, n1720, n1721, n1722,
n1723, n1724, n1725, n1726, n1727, n1728, n1729, n1730, n1731, n1732,
n1733, n1734, n1735, n1736, n1737, n1738, n1739, n1740, n1741, n1742,
n1743, n1744, n1745, n1746, n1747, n1748, n1749, n1750, n1751, n1752,
n1753, n1754, n1755, n1756, n1757, n1758, n1759, n1760, n1761, n1762,
n1763, n1764, n1765, n1766, n1767, n1768, n1769, n1770, n1771, n1772,
n1773, n1774, n1775, n1776, n1777, n1778, n1779, n1780, n1781, n1782,
n1783, n1784, n1785, n1786, n1787, n1788, n1789, n1790, n1791, n1792,
n1793, n1794, n1795, n1796, n1797, n1798, n1799, n1800, n1801, n1802,
n1803, n1804, n1805, n1806, n1807, n1808, n1809, n1810, n1811, n1812,
n1813, n1814, n1815, n1816, n1817, n1818, n1819, n1820, n1821, n1822,
n1823, n1824, n1825, n1826, n1827, n1828, n1829, n1830, n1831, n1832,
n1833, n1834, n1835, n1836, n1837, n1838, n1839, n1840, n1841, n1842,
n1843, n1844, n1845, n1846, n1847, n1848, n1849, n1850, n1851, n1852,
n1853, n1854, n1855, n1856, n1857, n1858, n1859, n1860, n1861, n1862,
n1863, n1864, n1865, n1866, n1867, n1868, n1869, n1870, n1871, n1872,
n1873, n1874, n1875, n1876, n1877, n1878, n1879, n1880, n1881, n1882,
n1883, n1884, n1885, n1886, n1887, n1888, n1889, n1890, n1891, n1892,
n1893, n1894, n1895, n1896, n1897, n1898, n1899, n1900, n1901, n1902,
n1903, n1904, n1905, n1906, n1907, n1908, n1909, n1910, n1911, n1912,
n1913, n1914, n1915, n1916, n1917, n1918, n1919, n1920, n1921, n1922,
n1923, n1924, n1925, n1926, n1927, n1928, n1929, n1930, n1931, n1932,
n1933, n1934, n1935, n1936, n1937, n1938, n1939, n1940, n1941, n1942,
n1943, n1944, n1945, n1946, n1947, n1948, n1949, n1950, n1951, n1952,
n1953, n1954, n1955, n1956, n1957, n1958, n1959, n1960, n1961, n1962,
n1963, n1964, n1965, n1966, n1967, n1968, n1969, n1970, n1971, n1972,
n1973, n1974, n1975, n1976, n1977, n1978, n1979, n1980, n1981, n1982,
n1983, n1984, n1985, n1986, n1987, n1988, n1989, n1990, n1991, n1992,
n1993, n1994, n1995, n1996, n1997, n1998, n1999, n2000, n2001, n2002,
n2003, n2004, n2005, n2006, n2007, n2008, n2009, n2010, n2011, n2012,
n2013, n2014, n2015, n2016, n2017, n2018, n2019, n2020, n2021, n2022,
n2023, n2024, n2025, n2026, n2027, n2028, n2029, n2030, n2031, n2032,
n2033, n2034, n2035, n2036, n2037, n2038, n2039, n2040, n2041, n2042,
n2043, n2044, n2045, n2046, n2047, n2048, n2049, n2050, n2051, n2052,
n2053, n2054, n2055, n2056, n2057, n2058, n2059, n2060, n2061, n2062,
n2063, n2064, n2065, n2066, n2067, n2068, n2069, n2070, n2071, n2072,
n2073, n2074, n2075, n2076, n2077, n2078, n2079, n2080, n2081, n2082,
n2083, n2084, n2085, n2086, n2087, n2088, n2089, n2090, n2091, n2092,
n2093, n2094, n2095, n2096, n2097, n2098, n2099, n2100, n2101, n2102,
n2103, n2104, n2105, n2106, n2107, n2108, n2109, n2110, n2111, n2112,
n2113, n2114, n2115, n2116, n2117, n2118, n2119, n2120, n2121, n2122,
n2123, n2124, n2125, n2126, n2127, n2128, n2129, n2130, n2131, n2132,
n2133, n2134, n2135, n2136, n2137, n2138, n2139, n2140, n2141, n2142,
n2143, n2144, n2145, n2146, n2147, n2148, n2149, n2150, n2151, n2152,
n2153, n2154, n2155, n2156, n2157, n2158, n2159, n2160, n2161, n2162,
n2163, n2164, n2165, n2166, n2167, n2168, n2169, n2170, n2171, n2172,
n2173, n2174, n2175, n2176, n2177, n2178, n2179, n2180, n2181, n2182,
n2183, n2184, n2185, n2186, n2187, n2188, n2189, n2190, n2191, n2192,
n2193, n2194, n2195, n2196, n2197, n2198, n2199, n2200, n2201, n2202,
n2203, n2204, n2205, n2206, n2207, n2208, n2209, n2210, n2211, n2212,
n2213, n2214, n2215, n2216, n2217, n2218, n2219, n2220, n2221, n2222,
n2223, n2224, n2225, n2226, n2227, n2228, n2229, n2230, n2231, n2232,
n2233, n2234, n2235, n2236, n2237, n2238, n2239, n2240, n2241, n2242,
n2243, n2244, n2245, n2246, n2247, n2248, n2249, n2250, n2251, n2252,
n2253, n2254, n2255, n2256, n2257, n2258, n2259, n2260, n2261, n2262,
n2263, n2264, n2265, n2266, n2267, n2268, n2269, n2270, n2271, n2272,
n2273, n2274, n2275, n2276, n2277, n2278, n2279, n2280, n2281, n2282,
n2283, n2284, n2285, n2286, n2287, n2288, n2289, n2290, n2291, n2292,
n2293, n2294, n2295, n2296, n2297, n2298, n2299, n2300, n2301, n2302,
n2303, n2304, n2305, n2306, n2307, n2308, n2309, n2310, n2311, n2312,
n2313, n2314, n2315, n2316, n2317, n2318, n2319, n2320, n2321, n2322,
n2323, n2324, n2325, n2326, n2327, n2328, n2329, n2330, n2331, n2332,
n2333, n2334, n2335, n2336, n2337, n2338, n2339, n2340, n2341, n2342,
n2343, n2344, n2345, n2346, n2347, n2348, n2349, n2350, n2351, n2352,
n2353, n2354, n2355, n2356, n2357, n2358, n2359, n2360, n2361, n2362,
n2363, n2364, n2365, n2366, n2367, n2368, n2369, n2370, n2371, n2372,
n2373, n2374, n2375, n2376, n2377, n2378, n2379, n2380, n2381, n2382,
n2383, n2384, n2385, n2386, n2387, n2388, n2389, n2390, n2391, n2392,
n2393, n2394, n2395, n2396, n2397, n2398, n2399, n2400, n2401, n2402,
n2403, n2404, n2405, n2406, n2407, n2408, n2409, n2410, n2411, n2412,
n2413, n2414, n2415, n2416, n2417, n2418, n2419, n2420, n2421, n2422,
n2423, n2424, n2425, n2426, n2427, n2428, n2429, n2430, n2431, n2432,
n2433, n2434, n2435, n2436, n2437, n2438, n2439, n2440, n2441, n2442,
n2443, n2444, n2445, n2446, n2447, n2448, n2449, n2450, n2451, n2452,
n2453, n2454, n2455, n2456, n2457, n2458, n2459, n2460, n2461, n2462,
n2463, n2464, n2465, n2466, n2467, n2468, n2469, n2470, n2471, n2472,
n2473, n2474, n2475, n2476, n2477, n2478, n2479, n2480, n2481, n2482,
n2483, n2484, n2485, n2486, n2487, n2488, n2489, n2490, n2491, n2492,
n2493, n2494, n2495, n2496, n2497, n2498, n2499, n2500, n2501, n2502,
n2503, n2504, n2505, n2506, n2507, n2508, n2509, n2510, n2511, n2512,
n2513, n2514, n2515, n2516, n2517, n2518, n2519, n2520, n2521, n2522,
n2523, n2524, n2525, n2526, n2527, n2528, n2529, n2530, n2531, n2532,
n2533, n2534, n2535, n2536, n2537, n2538, n2539, n2540, n2541, n2542,
n2543, n2544, n2545, n2546, n2547, n2548, n2549, n2550, n2551, n2552,
n2553, n2554, n2555, n2556, n2557, n2558, n2559, n2560, n2561, n2562,
n2563, n2564, n2565, n2566, n2567, n2568, n2569, n2570, n2571, n2572,
n2573, n2574, n2575, n2576, n2577, n2578, n2579, n2580, n2581, n2582,
n2583, n2584, n2585, n2586, n2587, n2588, n2589, n2590, n2591, n2592,
n2593, n2594, n2595, n2596, n2597, n2598, n2599, n2600, n2601, n2602,
n2603, n2604, n2605, n2606, n2607, n2608, n2609, n2610, n2611, n2612,
n2613, n2614, n2615, n2616, n2617, n2618, n2619, n2620, n2621, n2622,
n2623, n2624, n2625, n2626, n2627, n2628, n2629, n2630, n2631, n2632,
n2633, n2634, n2635, n2636, n2637, n2638, n2639, n2640, n2641, n2642,
n2643, n2644, n2645, n2646, n2647, n2648, n2649, n2650, n2651, n2652,
n2653, n2654, n2655, n2656, n2657, n2658, n2659, n2660, n2661, n2662,
n2663, n2664, n2665, n2666, n2667, n2668, n2669, n2670, n2671, n2672,
n2673, n2674, n2675, n2676, n2677, n2678, n2679, n2680, n2681, n2682,
n2683, n2684, n2685, n2686, n2687, n2688, n2689, n2690, n2691, n2692,
n2693, n2694, n2695, n2696, n2697, n2698, n2699, n2700, n2701, n2702,
n2703, n2704, n2705, n2706, n2707, n2708, n2709, n2710, n2711, n2712,
n2713, n2714, n2715, n2716, n2717, n2718, n2719, n2720, n2721, n2722,
n2723, n2724, n2725, n2726, n2727, n2728, n2729, n2730, n2731, n2732,
n2733, n2734, n2735, n2736, n2737, n2738, n2739, n2740, n2741, n2742,
n2743, n2744, n2745, n2746, n2747, n2748, n2749, n2750, n2751, n2752,
n2753, n2754, n2755, n2756, n2757, n2758, n2759, n2760, n2761, n2762,
n2763, n2764, n2765, n2766, n2767, n2768, n2769, n2770, n2771, n2772,
n2773, n2774, n2775, n2776, n2777, n2778, n2779, n2780, n2781, n2782,
n2783, n2784, n2785, n2786, n2787, n2788, n2789, n2790, n2791, n2792,
n2793, n2794, n2795, n2796, n2797, n2798, n2799, n2800, n2801, n2802,
n2803, n2804, n2805, n2806, n2807, n2808, n2809, n2810, n2811, n2812,
n2813, n2814, n2815, n2816, n2817, n2818, n2819, n2820, n2821, n2822,
n2823, n2824, n2825, n2826, n2827, n2828, n2829, n2830, n2831, n2832,
n2833, n2834, n2835, n2836, n2837, n2838, n2839, n2840, n2841, n2842,
n2843, n2844, n2845, n2846, n2847, n2848, n2849, n2850, n2851, n2852,
n2853, n2854, n2855, n2856, n2857, n2858, n2859, n2860, n2861, n2862,
n2863, n2864, n2865, n2866, n2867, n2868, n2869, n2870, n2871, n2872,
n2873, n2874, n2875, n2876, n2877, n2878, n2879, n2880, n2881, n2882,
n2883, n2884, n2885, n2886, n2887, n2888, n2889, n2890, n2891, n2892,
n2893, n2894, n2895, n2896, n2897, n2898, n2899, n2900, n2901, n2902,
n2903, n2904, n2905, n2906, n2907, n2908, n2909, n2910, n2911, n2912,
n2913, n2914, n2915, n2916, n2917, n2918, n2919, n2920, n2921, n2922,
n2923, n2924, n2925, n2926, n2927, n2928, n2929, n2930, n2931, n2932,
n2933, n2934, n2935, n2936, n2937, n2938, n2939, n2940, n2941, n2942,
n2943, n2944, n2945, n2946, n2947, n2948, n2949, n2950, n2951, n2952,
n2953, n2954, n2955, n2956, n2957, n2958, n2959, n2960, n2961, n2962,
n2963, n2964, n2965, n2966, n2967, n2968, n2969, n2970, n2971, n2972,
n2973, n2974, n2975, n2976, n2977, n2978, n2979, n2980, n2981, n2982,
n2983, n2984, n2985, n2986, n2987, n2988, n2989, n2990, n2991, n2992,
n2993, n2994, n2995, n2996, n2997, n2998, n2999, n3000, n3001, n3002,
n3003, n3004, n3005, n3006, n3007, n3008, n3009, n3010, n3011, n3012,
n3013, n3014, n3015, n3016, n3017, n3018, n3019, n3020, n3021, n3022,
n3023, n3024, n3025, n3026, n3027, n3028, n3029, n3030, n3031, n3032,
n3033, n3034, n3035, n3036, n3037, n3038, n3039, n3040, n3041, n3042,
n3043, n3044, n3045, n3046, n3047, n3048, n3049, n3050, n3051, n3052,
n3053, n3054, n3055, n3056, n3057, n3058, n3059, n3060, n3061, n3062,
n3063, n3064, n3065, n3066, n3067, n3068, n3069, n3070, n3071, n3072,
n3073, n3074, n3075, n3076, n3077, n3078, n3079, n3080, n3081, n3082,
n3083, n3084, n3085, n3086, n3087, n3088, n3089, n3090, n3091, n3092,
n3093, n3094, n3095, n3096, n3097, n3098, n3099, n3100, n3101, n3102,
n3103, n3104, n3105, n3106, n3107, n3108, n3109, n3110, n3111, n3112,
n3113, n3114, n3115, n3116, n3117, n3118, n3119, n3120, n3121, n3122,
n3123, n3124, n3125, n3126, n3127, n3128, n3129, n3130, n3131, n3132,
n3133, n3134, n3135, n3136, n3137, n3138, n3139, n3140, n3141, n3142,
n3143, n3144, n3145, n3146, n3147, n3148, n3149, n3150, n3151, n3152,
n3153, n3154, n3155, n3156, n3157, n3158, n3159, n3160, n3161, n3162,
n3163, n3164, n3165, n3166, n3167, n3168, n3169, n3170, n3171, n3172,
n3173, n3174, n3175, n3176, n3177, n3178, n3179, n3180, n3181, n3182,
n3183, n3184, n3185, n3186, n3187, n3188, n3189, n3190, n3191, n3192,
n3193, n3194, n3195, n3196, n3197, n3198, n3199, n3200, n3201, n3202,
n3203, n3204, n3205, n3206, n3207, n3208, n3209, n3210, n3211, n3212,
n3213, n3214, n3215, n3216, n3217, n3218, n3219, n3220, n3221, n3222,
n3223, n3224, n3225, n3226, n3227, n3228, n3229, n3230, n3231, n3232,
n3233, n3234, n3235, n3236, n3237, n3238, n3239, n3240, n3241, n3242,
n3243, n3244, n3245, n3246, n3247, n3248, n3249, n3250, n3251, n3252,
n3253, n3254, n3255, n3256, n3257, n3258, n3259, n3260, n3261, n3262,
n3263, n3264, n3265, n3266, n3267, n3268, n3269, n3270, n3271, n3272,
n3273, n3274, n3275, n3276, n3277, n3278, n3279, n3280, n3281, n3282,
n3283, n3284, n3285, n3286, n3287, n3288, n3289, n3290, n3291, n3292,
n3293, n3294, n3295, n3296, n3297, n3298, n3299, n3300, n3301, n3302,
n3303, n3304, n3305, n3306, n3307, n3308, n3309, n3310, n3311, n3312,
n3313, n3314, n3315, n3316, n3317, n3318, n3319, n3320, n3321, n3322,
n3323, n3324, n3325, n3326, n3327, n3328, n3329, n3330, n3331, n3332,
n3333, n3334, n3335, n3336, n3337, n3338, n3339, n3340, n3341, n3342,
n3343, n3344, n3345, n3346, n3347, n3348, n3349, n3350, n3351, n3352,
n3353, n3354, n3355, n3356, n3357, n3358, n3359, n3360, n3361, n3362,
n3363, n3364, n3365, n3366, n3367, n3368, n3369, n3370, n3371, n3372,
n3373, n3374, n3375, n3376, n3377, n3378, n3379, n3380, n3381, n3382,
n3383, n3384, n3385, n3386, n3387, n3388, n3389, n3390, n3391, n3392,
n3393, n3394, n3395, n3396, n3397, n3398, n3399, n3400, n3401, n3402,
n3403, n3404, n3405, n3406, n3407, n3408, n3409, n3410, n3411, n3412,
n3413, n3414, n3415, n3416, n3417, n3418, n3419, n3420, n3421, n3422,
n3423, n3424, n3425, n3426, n3427, n3428, n3429, n3430, n3431, n3432,
n3433, n3434, n3435, n3436, n3437, n3438, n3439, n3440, n3441, n3442,
n3443, n3444, n3445, n3446, n3447, n3448, n3449, n3450, n3451, n3452,
n3453, n3454, n3455, n3456, n3457, n3458, n3459, n3460, n3461, n3462,
n3463, n3464, n3465, n3466, n3467, n3468, n3469, n3470, n3471, n3472,
n3473, n3474, n3475, n3476, n3477, n3478, n3479, n3480, n3481, n3482,
n3483, n3484, n3485, n3486, n3487, n3488, n3489, n3490, n3491, n3492,
n3493, n3494, n3495, n3496, n3497, n3498, n3499, n3500, n3501, n3502,
n3503, n3504, n3505, n3506, n3507, n3508, n3509, n3510, n3511, n3512,
n3513, n3514, n3515, n3516, n3517, n3518, n3519, n3520, n3521, n3522,
n3523, n3524, n3525, n3526, n3527, n3528, n3529, n3530, n3531, n3532,
n3533, n3534, n3535, n3536, n3537, n3538, n3539, n3540, n3541, n3542,
n3543, n3544, n3545, n3546, n3547, n3548, n3549, n3550, n3551, n3552,
n3553, n3554, n3555, n3556, n3557, n3558, n3559, n3560, n3561, n3562,
n3563, n3564, n3565, n3566, n3567, n3568, n3569, n3570, n3571, n3572,
n3573, n3574, n3575, n3576, n3577, n3578, n3579, n3580, n3581, n3582,
n3583, n3584, n3585, n3586, n3587, n3588, n3589, n3590, n3591, n3592,
n3593, n3594, n3595, n3596, n3597, n3598, n3599, n3600, n3601, n3602,
n3603, n3604, n3605, n3606, n3607, n3608, n3609, n3610, n3611, n3612,
n3613, n3614, n3615, n3616, n3617, n3618, n3619, n3620, n3621, n3622,
n3623, n3624, n3625, n3626, n3627, n3628, n3629, n3630, n3631, n3632,
n3633, n3634, n3635, n3636, n3637, n3638, n3639, n3640, n3641, n3642,
n3643, n3644, n3645, n3646, n3647, n3648, n3649, n3650, n3651, n3652,
n3653, n3654, n3655, n3656, n3657, n3658, n3659, n3660, n3661, n3662,
n3663, n3664, n3665, n3666, n3667, n3668, n3669, n3670, n3671, n3672,
n3673, n3674, n3675, n3676, n3677, n3678, n3679, n3680, n3681, n3682,
n3683, n3684, n3685, n3686, n3687, n3688, n3689, n3690, n3691, n3692,
n3693, n3694, n3695, n3696, n3697, n3698, n3699, n3700, n3701, n3702,
n3703, n3704, n3705, n3706, n3707, n3708, n3709, n3710, n3711, n3712,
n3713, n3714, n3715, n3716, n3717, n3718, n3719, n3720, n3721, n3722,
n3723, n3724, n3725, n3726, n3727, n3728, n3729, n3730, n3731, n3732,
n3733, n3734, n3735, n3736, n3737, n3738, n3739, n3740, n3741, n3742,
n3743, n3744, n3745, n3746, n3747, n3748, n3749, n3750, n3751, n3752,
n3753, n3754, n3755, n3756, n3757, n3758, n3759, n3760, n3761, n3762,
n3763, n3764, n3765, n3766, n3767, n3768, n3769, n3770, n3771, n3772,
n3773, n3774, n3775, n3776, n3777, n3778, n3779, n3780, n3781, n3782,
n3783, n3784, n3785, n3786, n3787, n3788, n3789, n3790, n3791, n3792,
n3793, n3794, n3795, n3796, n3797, n3798, n3799, n3800, n3801, n3802,
n3803, n3804, n3805, n3806, n3807, n3808, n3809, n3810, n3811, n3812,
n3813, n3814, n3815, n3816, n3817, n3818, n3819, n3820, n3821, n3822,
n3823, n3824, n3825, n3826, n3827, n3828, n3829, n3830, n3831, n3832,
n3833, n3834, n3835, n3836, n3837, n3838, n3839, n3840, n3841, n3842,
n3843, n3844, n3845, n3846, n3847, n3848, n3849, n3850, n3851, n3852,
n3853, n3854, n3855, n3856, n3857, n3858, n3859, n3860, n3861, n3862,
n3863, n3864, n3865, n3866, n3867, n3868, n3869, n3870, n3871, n3872,
n3873, n3874, n3875, n3876, n3877, n3878, n3879, n3880, n3881, n3882,
n3883, n3884, n3885, n3886, n3887, n3888, n3889, n3890, n3891, n3892,
n3893, n3894, n3895, n3896, n3897, n3898, n3899, n3900, n3901, n3902,
n3903, n3904, n3905, n3906, n3907, n3908, n3909, n3910, n3911, n3912,
n3913, n3914, n3915, n3916, n3917, n3918, n3919, n3920, n3921, n3922,
n3923, n3924, n3925, n3926, n3927, n3928, n3929, n3930, n3931, n3932,
n3933, n3934, n3935, n3936, n3937, n3938, n3939, n3940, n3941, n3942,
n3943, n3944, n3945, n3946, n3947, n3948, n3949, n3950, n3951, n3952,
n3953, n3954, n3955, n3956, n3957, n3958, n3959, n3960, n3961, n3962,
n3963, n3964, n3965, n3966, n3967, n3968, n3969, n3970, n3971, n3972,
n3973, n3974, n3975, n3976, n3977, n3978, n3979, n3980, n3981, n3982,
n3983, n3984, n3985, n3986, n3987, n3988, n3989, n3990, n3991, n3992,
n3993, n3994, n3995, n3996, n3997, n3998, n3999, n4000, n4001, n4002,
n4003, n4004, n4005, n4006, n4007, n4008, n4009, n4010, n4011, n4012,
n4013, n4014, n4015, n4016, n4017, n4018, n4019, n4020, n4021, n4022,
n4023, n4024, n4025, n4026, n4027, n4028, n4029, n4030, n4031, n4032,
n4033, n4034, n4035, n4036, n4037, n4038, n4039, n4040, n4041, n4042,
n4043, n4044, n4045, n4046, n4047, n4048, n4049, n4050, n4051, n4052,
n4053, n4054, n4055, n4056, n4057, n4058, n4059, n4060, n4061, n4062,
n4063, n4064, n4065, n4066, n4067, n4068, n4069, n4070, n4071, n4072,
n4073, n4074, n4075, n4076, n4077, n4078, n4079, n4080, n4081, n4082,
n4083, n4084, n4085, n4086, n4087, n4088, n4089, n4090, n4091, n4092,
n4093, n4094, n4095, n4096, n4097, n4098, n4099, n4100, n4101, n4102,
n4103, n4104, n4105, n4106, n4107, n4108, n4109, n4110, n4111, n4112,
n4113, n4114, n4115, n4116, n4117, n4118, n4119, n4120, n4121, n4122,
n4123, n4124, n4125, n4126, n4127, n4128, n4129, n4130, n4131, n4132,
n4133, n4134, n4135, n4136, n4137, n4138, n4139, n4140, n4141, n4142,
n4143, n4144, n4145, n4146, n4147, n4148, n4149, n4150, n4151, n4152,
n4153, n4154, n4155, n4156, n4157, n4158, n4159, n4160, n4161, n4162,
n4163, n4164, n4165, n4166, n4167, n4168, n4169, n4170, n4171, n4172,
n4173, n4174, n4175, n4176, n4177, n4178, n4179, n4180, n4181, n4182,
n4183, n4184, n4185, n4186, n4187, n4188, n4189, n4190, n4191, n4192,
n4193, n4194, n4195, n4196, n4197, n4198, n4199, n4200, n4201, n4202,
n4203, n4204, n4205, n4206, n4207, n4208, n4209, n4210, n4211, n4212,
n4213, n4214, n4215, n4216, n4217, n4218, n4219, n4220, n4221, n4222,
n4223, n4224, n4225, n4226, n4227, n4228, n4229, n4230, n4231, n4232,
n4233, n4234, n4235, n4236, n4237, n4238, n4239, n4240, n4241, n4242,
n4243, n4244, n4245, n4246, n4247, n4248, n4249, n4250, n4251, n4252,
n4253, n4254, n4255, n4256, n4257, n4258, n4259, n4260, n4261, n4262,
n4263, n4264, n4265, n4266, n4267, n4268, n4269, n4270, n4271, n4272,
n4273, n4274, n4275, n4276, n4277, n4278, n4279, n4280, n4281, n4282,
n4283, n4284, n4285, n4286, n4287, n4288, n4289, n4290, n4291, n4292,
n4293, n4294, n4295, n4296, n4297, n4298, n4299, n4300, n4301, n4302,
n4303, n4304, n4305, n4306, n4307, n4308, n4309, n4310, n4311, n4312,
n4313, n4314, n4315, n4316, n4317, n4318, n4319, n4320, n4321, n4322,
n4323, n4324, n4325, n4326, n4327, n4328, n4329, n4330, n4331, n4332,
n4333, n4334, n4335, n4336, n4337, n4338, n4339, n4340, n4341, n4342,
n4343, n4344, n4345, n4346, n4347, n4348, n4349, n4350, n4351, n4352,
n4353, n4354, n4355, n4356, n4357, n4358, n4359, n4360, n4361, n4362,
n4363, n4364, n4365, n4366, n4367, n4368, n4369, n4370, n4371, n4372,
n4373, n4374, n4375, n4376, n4377, n4378, n4379, n4380, n4381, n4382,
n4383, n4384, n4385, n4386, n4387, n4388, n4389, n4390, n4391, n4392,
n4393, n4394, n4395, n4396, n4397, n4398, n4399, n4400, n4401, n4402,
n4403, n4404, n4405, n4406, n4407, n4408, n4409, n4410, n4411, n4412,
n4413, n4414, n4415, n4416, n4417, n4418, n4419, n4420, n4421, n4422,
n4423, n4424, n4425, n4426, n4427, n4428, n4429, n4430, n4431, n4432,
n4433, n4434, n4435, n4436, n4437, n4438, n4439, n4440, n4441, n4442,
n4443, n4444, n4445, n4446, n4447, n4448, n4449, n4450, n4451, n4452,
n4453, n4454, n4455, n4456, n4457, n4458, n4459, n4460, n4461, n4462,
n4463, n4464, n4465, n4466, n4467, n4468, n4469, n4470, n4471, n4472,
n4473, n4474, n4475, n4476, n4477, n4478, n4479, n4480, n4481, n4482,
n4483, n4484, n4485, n4486, n4487, n4488, n4489, n4490, n4491, n4492,
n4493, n4494, n4495, n4496, n4497, n4498, n4499, n4500, n4501, n4502,
n4503, n4504, n4505, n4506, n4507, n4508, n4509, n4510, n4511, n4512,
n4513, n4514, n4515, n4516, n4517, n4518, n4519, n4520, n4521, n4522,
n4523, n4524, n4525, n4526, n4527, n4528, n4529, n4530, n4531, n4532,
n4533, n4534, n4535, n4536, n4537, n4538, n4539, n4540, n4541, n4542,
n4543, n4544, n4545, n4546, n4547, n4548, n4549, n4550, n4551, n4552,
n4553, n4554, n4555, n4556, n4557, n4558, n4559, n4560, n4561, n4562,
n4563, n4564, n4565, n4566, n4567, n4568, n4569, n4570, n4571, n4572,
n4573, n4574, n4575, n4576, n4577, n4578, n4579, n4580, n4581, n4582,
n4583, n4584, n4585, n4586, n4587, n4588, n4589, n4590, n4591, n4592,
n4593, n4594, n4595, n4596, n4597, n4598, n4599, n4600, n4601, n4602,
n4603, n4604, n4605, n4606, n4607, n4608, n4609, n4610, n4611, n4612,
n4613, n4614, n4615, n4616, n4617, n4618, n4619, n4620, n4621, n4622,
n4623, n4624, n4625, n4626, n4627, n4628, n4629, n4630, n4631, n4632,
n4633, n4634, n4635, n4636, n4637, n4638, n4639, n4640, n4641, n4642,
n4643, n4644, n4645, n4646, n4647, n4648, n4649, n4650, n4651, n4652,
n4653, n4654, n4655, n4656, n4657, n4658, n4659, n4660, n4661, n4662,
n4663, n4664, n4665, n4666, n4667, n4668, n4669, n4670, n4671, n4672,
n4673, n4674, n4675, n4676, n4677, n4678, n4679, n4680, n4681, n4682,
n4683, n4684, n4685, n4686, n4687, n4688, n4689, n4690, n4691, n4692,
n4693, n4694, n4695, n4696, n4697, n4698, n4699, n4700, n4701, n4702,
n4703, n4704, n4705, n4706, n4707, n4708, n4709, n4710, n4711, n4712,
n4713, n4714, n4715, n4716, n4717, n4718, n4719, n4720, n4721, n4722,
n4723, n4724, n4725, n4726, n4727, n4728, n4729, n4730, n4731, n4732,
n4733, n4734, n4735, n4736, n4737, n4738, n4739, n4740, n4741, n4742,
n4743, n4744, n4745, n4746, n4747, n4748, n4749, n4750, n4751, n4752,
n4753, n4754, n4755, n4756, n4757, n4758, n4759, n4760, n4761, n4762,
n4763, n4764, n4765, n4766, n4767, n4768, n4769, n4770, n4771, n4772,
n4773, n4774, n4775, n4776, n4777, n4778, n4779, n4780, n4781, n4782,
n4783, n4784, n4785, n4786, n4787, n4788, n4789, n4790, n4791, n4792,
n4793, n4794, n4795, n4796, n4797, n4798, n4799, n4800, n4801, n4802,
n4803, n4804, n4805, n4806, n4807, n4808, n4809, n4810, n4811, n4812,
n4813, n4814, n4815, n4816, n4817, n4818, n4819, n4820, n4821, n4822,
n4823, n4824, n4825, n4826, n4827, n4828, n4829, n4830, n4831, n4832,
n4833, n4834, n4835, n4836, n4837, n4838, n4839, n4840, n4841, n4842,
n4843, n4844, n4845, n4846, n4847, n4848, n4849, n4850, n4851, n4852,
n4853, n4854, n4855, n4856, n4857, n4858, n4859, n4860, n4861, n4862,
n4863, n4864, n4865, n4866, n4867, n4868, n4869, n4870, n4871, n4872,
n4873, n4874, n4875, n4876, n4877, n4878, n4879, n4880, n4881, n4882,
n4883, n4884, n4885, n4886, n4887, n4888, n4889, n4890, n4891, n4892,
n4893, n4894, n4895, n4896, n4897, n4898, n4899, n4900, n4901, n4902,
n4903, n4904, n4905, n4906, n4907, n4908, n4909, n4910, n4911, n4912,
n4913, n4914, n4915, n4916, n4917, n4918, n4919, n4920, n4921, n4922,
n4923, n4924, n4925, n4926, n4927, n4928, n4929, n4930, n4931, n4932,
n4933, n4934, n4935, n4936, n4937, n4938, n4939, n4940, n4941, n4942,
n4943, n4944, n4945, n4946, n4947, n4948, n4949, n4950, n4951, n4952,
n4953, n4954, n4955, n4956, n4957, n4958, n4959, n4960, n4961, n4962,
n4963, n4964, n4965, n4966, n4967, n4968, n4969, n4970, n4971, n4972,
n4973, n4974, n4975, n4976, n4977, n4978, n4979, n4980, n4981, n4982,
n4983, n4984, n4985, n4986, n4987, n4988, n4989, n4990, n4991, n4992,
n4993, n4994, n4995, n4996, n4997, n4998, n4999, n5000, n5001, n5002,
n5003, n5004, n5005, n5006, n5007, n5008, n5009, n5010, n5011, n5012,
n5013, n5014, n5015, n5016, n5017, n5018, n5019, n5020, n5021, n5022,
n5023, n5024, n5025, n5026, n5027, n5028, n5029, n5030, n5031, n5032,
n5033, n5034, n5035, n5036, n5037, n5038, n5039, n5040, n5041, n5042,
n5043, n5044, n5045, n5046, n5047, n5048, n5049, n5050, n5051, n5052,
n5053, n5054, n5055, n5056, n5057, n5058, n5059, n5060, n5061, n5062,
n5063, n5064, n5065, n5066, n5067, n5068, n5069, n5070, n5071, n5072,
n5073, n5074, n5075, n5076, n5077, n5078, n5079, n5080, n5081, n5082,
n5083, n5084, n5085, n5086, n5087, n5088, n5089, n5090, n5091, n5092,
n5093, n5094, n5095, n5096, n5097, n5098, n5099, n5100, n5101, n5102,
n5103, n5104, n5105, n5106, n5107, n5108, n5109, n5110, n5111, n5112,
n5113, n5114, n5115, n5116, n5117, n5118, n5119, n5120, n5121, n5122,
n5123, n5124, n5125, n5126, n5127, n5128, n5129, n5130, n5131, n5132,
n5133, n5134, n5135, n5136, n5137, n5138, n5139, n5140, n5141, n5142,
n5143, n5144, n5145, n5146, n5147, n5148, n5149, n5150, n5151, n5152,
n5153, n5154, n5155, n5156, n5157, n5158, n5159, n5160, n5161, n5162,
n5163, n5164, n5165, n5166, n5167, n5168, n5169, n5170, n5171, n5172,
n5173, n5174, n5175, n5176, n5177, n5178, n5179, n5180, n5181, n5182,
n5183, n5184, n5185, n5186, n5187, n5188, n5189, n5190, n5191, n5192,
n5193, n5194, n5195, n5196, n5197, n5198, n5199, n5200, n5201, n5202,
n5203, n5204, n5205, n5206, n5207, n5208, n5209, n5210, n5211, n5212,
n5213, n5214, n5215, n5216, n5217, n5218, n5219, n5220, n5221, n5222,
n5223, n5224, n5225, n5226, n5227, n5228, n5229, n5230, n5231, n5232,
n5233, n5234, n5235, n5236, n5237, n5238, n5239, n5240, n5241, n5242,
n5243, n5244, n5245, n5246, n5247, n5248, n5249, n5250, n5251, n5252,
n5253, n5254, n5255, n5256, n5257, n5258, n5259, n5260, n5261, n5262,
n5263, n5264, n5265, n5266, n5267, n5268, n5269, n5270, n5271, n5272,
n5273, n5274, n5275, n5276, n5277, n5278, n5279, n5280, n5281, n5282,
n5283, n5284, n5285, n5286, n5287, n5288, n5289, n5290, n5291, n5292,
n5293, n5294, n5295, n5296, n5297, n5298, n5299, n5300, n5301, n5302,
n5303, n5304, n5305, n5306, n5307, n5308, n5309, n5310, n5311, n5312,
n5313, n5314, n5315, n5316, n5317, n5318, n5319, n5320, n5321, n5322,
n5323, n5324, n5325, n5326, n5327, n5328, n5329, n5330, n5331, n5332,
n5333, n5334, n5335, n5336, n5337, n5338, n5339, n5340, n5341, n5342,
n5343, n5344, n5345, n5346, n5347, n5348, n5349, n5350, n5351, n5352,
n5353, n5354, n5355, n5356, n5357, n5358, n5359, n5360, n5361, n5362,
n5363, n5364, n5365, n5366, n5367, n5368, n5369, n5370, n5371, n5372,
n5373, n5374, n5375, n5376, n5377, n5378, n5379, n5380, n5381, n5382,
n5383, n5384, n5385, n5386, n5387, n5388, n5389, n5390, n5391, n5392,
n5393, n5394, n5395, n5396, n5397, n5398, n5399, n5400, n5401, n5402,
n5403, n5404, n5405, n5406, n5407, n5408, n5409, n5410, n5411, n5412,
n5413, n5414, n5415, n5416, n5417, n5418, n5419, n5420, n5421, n5422,
n5423, n5424, n5425, n5426, n5427, n5428, n5429, n5430, n5431, n5432,
n5433, n5434, n5435, n5436, n5437, n5438, n5439, n5440, n5441, n5442,
n5443, n5444, n5445, n5446, n5447, n5448, n5449, n5450, n5451, n5452,
n5453, n5454, n5455, n5456, n5457, n5458, n5459, n5460, n5461, n5462,
n5463, n5464, n5465, n5466, n5467, n5468, n5469, n5470, n5471, n5472,
n5473, n5474, n5475, n5476, n5477, n5478, n5479, n5480, n5481, n5482,
n5483, n5484, n5485, n5486, n5487, n5488, n5489, n5490, n5491, n5492,
n5493, n5494, n5495, n5496, n5497, n5498, n5499, n5500, n5501, n5502,
n5503, n5504, n5505, n5506, n5507, n5508, n5509, n5510, n5511, n5512,
n5513, n5514, n5515, n5516, n5517, n5518, n5519, n5520, n5521, n5522,
n5523, n5524, n5525, n5526, n5527, n5528, n5529, n5530, n5531, n5532,
n5533, n5534, n5535, n5536, n5537, n5538, n5539, n5540, n5541, n5542,
n5543, n5544, n5545, n5546, n5547, n5548, n5549, n5550, n5551, n5552,
n5553, n5554, n5555, n5556, n5557, n5558, n5559, n5560, n5561, n5562,
n5563, n5564, n5565, n5566, n5567, n5568, n5569, n5570, n5571, n5572,
n5573, n5574, n5575, n5576, n5577, n5578, n5579, n5580, n5581, n5582,
n5583, n5584, n5585, n5586, n5587, n5588, n5589, n5590, n5591, n5592,
n5593, n5594, n5595, n5596, n5597, n5598, n5599, n5600, n5601, n5602,
n5603, n5604, n5605, n5606, n5607, n5608, n5609, n5610, n5611, n5612,
n5613, n5614, n5615, n5616, n5617, n5618, n5619, n5620, n5621, n5622,
n5623, n5624, n5625, n5626, n5627, n5628, n5629, n5630, n5631, n5632,
n5633, n5634, n5635, n5636, n5637, n5638, n5639, n5640, n5641, n5642,
n5643, n5644, n5645, n5646, n5647, n5648, n5649, n5650, n5651, n5652,
n5653, n5654, n5655, n5656, n5657, n5658, n5659, n5660, n5661, n5662,
n5663, n5664, n5665, n5666, n5667, n5668, n5669, n5670, n5671, n5672,
n5673, n5674, n5675, n5676, n5677, n5678, n5679, n5680, n5681, n5682,
n5683, n5684, n5685, n5686, n5687, n5688, n5689, n5690, n5691, n5692,
n5693, n5694, n5695, n5696, n5697, n5698, n5699, n5700, n5701, n5702,
n5703, n5704, n5705, n5706, n5707, n5708, n5709, n5710, n5711, n5712,
n5713, n5714, n5715, n5716, n5717, n5718, n5719, n5720, n5721, n5722,
n5723, n5724, n5725, n5726, n5727, n5728, n5729, n5730, n5731, n5732,
n5733, n5734, n5735, n5736, n5737, n5738, n5739, n5740, n5741, n5742,
n5743, n5744, n5745, n5746, n5747, n5748, n5749, n5750, n5751, n5752,
n5753, n5754, n5755, n5756, n5757, n5758, n5759, n5760, n5761, n5762,
n5763, n5764, n5765, n5766, n5767, n5768, n5769, n5770, n5771, n5772,
n5773, n5774, n5775, n5776, n5777, n5778, n5779, n5780, n5781, n5782,
n5783, n5784, n5785, n5786, n5787, n5788, n5789, n5790, n5791, n5792,
n5793, n5794, n5795, n5796, n5797, n5798, n5799, n5800, n5801, n5802,
n5803, n5804, n5805, n5806, n5807, n5808, n5809, n5810, n5811, n5812,
n5813, n5814, n5815, n5816, n5817, n5818, n5819, n5820, n5821, n5822,
n5823, n5824, n5825, n5826, n5827, n5828, n5829, n5830, n5831, n5832,
n5833, n5834, n5835, n5836, n5837, n5838, n5839, n5840, n5841, n5842,
n5843, n5844, n5845, n5846, n5847, n5848, n5849, n5850, n5851, n5852,
n5853, n5854, n5855, n5856, n5857, n5858, n5859, n5860, n5861, n5862,
n5863, n5864, n5865, n5866, n5867, n5868, n5869, n5870, n5871, n5872,
n5873, n5874, n5875, n5876, n5877, n5878, n5879, n5880, n5881, n5882,
n5883, n5884, n5885, n5886, n5887, n5888, n5889, n5890, n5891, n5892,
n5893, n5894, n5895, n5896, n5897, n5898, n5899, n5900, n5901, n5902,
n5903, n5904, n5905, n5906, n5907, n5908, n5909, n5910, n5911, n5912,
n5913, n5914, n5915, n5916, n5917, n5918, n5919, n5920, n5921, n5922,
n5923, n5924, n5925, n5926, n5927, n5928, n5929, n5930, n5931, n5932,
n5933, n5934, n5935, n5936, n5937, n5938, n5939, n5940, n5941, n5942,
n5943, n5944, n5945, n5946, n5947, n5948, n5949, n5950, n5951, n5952,
n5953, n5954, n5955, n5956, n5957, n5958, n5959, n5960, n5961, n5962,
n5963, n5964, n5965, n5966, n5967, n5968, n5969, n5970, n5971, n5972,
n5973, n5974, n5975, n5976, n5977, n5978, n5979, n5980, n5981, n5982,
n5983, n5984, n5985, n5986, n5987, n5988, n5989, n5990, n5991, n5992,
n5993, n5994, n5995, n5996, n5997, n5998, n5999, n6000, n6001, n6002,
n6003, n6004, n6005, n6006, n6007, n6008, n6009, n6010, n6011, n6012,
n6013, n6014, n6015, n6016, n6017, n6018, n6019, n6020, n6021, n6022,
n6023, n6024, n6025, n6026, n6027, n6028, n6029, n6030, n6031, n6032,
n6033, n6034, n6035 : std_logic;
begin
ready_x_out <= ready_x_out_port;
ready_h_out <= ready_h_out_port;
valid_out <= valid_out_port;
adder_mem_array_reg_3_0_inst : dff_asyncrsthl port map( d =>
multiplier_sigs_3_0_port, gclk => clk, asyncrsthl =>
rst, q => adder_mem_array_3_0_port);
adder_mem_array_reg_3_1_inst : dff_asyncrsthl port map( d =>
multiplier_sigs_3_1_port, gclk => clk, asyncrsthl =>
rst, q => adder_mem_array_3_1_port);
adder_mem_array_reg_3_2_inst : dff_asyncrsthl port map( d =>
multiplier_sigs_3_2_port, gclk => clk, asyncrsthl =>
rst, q => adder_mem_array_3_2_port);
adder_mem_array_reg_3_3_inst : dff_asyncrsthl port map( d =>
multiplier_sigs_3_3_port, gclk => clk, asyncrsthl =>
rst, q => adder_mem_array_3_3_port);
adder_mem_array_reg_3_4_inst : dff_asyncrsthl port map( d =>
multiplier_sigs_3_4_port, gclk => clk, asyncrsthl =>
rst, q => adder_mem_array_3_4_port);
adder_mem_array_reg_3_5_inst : dff_asyncrsthl port map( d =>
multiplier_sigs_3_5_port, gclk => clk, asyncrsthl =>
rst, q => adder_mem_array_3_5_port);
adder_mem_array_reg_3_6_inst : dff_asyncrsthl port map( d =>
multiplier_sigs_3_6_port, gclk => clk, asyncrsthl =>
rst, q => adder_mem_array_3_6_port);
adder_mem_array_reg_3_7_inst : dff_asyncrsthl port map( d =>
multiplier_sigs_3_7_port, gclk => clk, asyncrsthl =>
rst, q => adder_mem_array_3_7_port);
adder_mem_array_reg_3_8_inst : dff_asyncrsthl port map( d =>
multiplier_sigs_3_8_port, gclk => clk, asyncrsthl =>
rst, q => adder_mem_array_3_8_port);
adder_mem_array_reg_3_9_inst : dff_asyncrsthl port map( d =>
multiplier_sigs_3_9_port, gclk => clk, asyncrsthl =>
rst, q => adder_mem_array_3_9_port);
adder_mem_array_reg_3_10_inst : dff_asyncrsthl port map( d =>
multiplier_sigs_3_10_port, gclk => clk, asyncrsthl
=> rst, q => adder_mem_array_3_10_port);
adder_mem_array_reg_3_11_inst : dff_asyncrsthl port map( d =>
multiplier_sigs_3_11_port, gclk => clk, asyncrsthl
=> rst, q => adder_mem_array_3_11_port);
adder_mem_array_reg_3_12_inst : dff_asyncrsthl port map( d =>
multiplier_sigs_3_12_port, gclk => clk, asyncrsthl
=> rst, q => adder_mem_array_3_12_port);
adder_mem_array_reg_3_13_inst : dff_asyncrsthl port map( d =>
multiplier_sigs_3_13_port, gclk => clk, asyncrsthl
=> rst, q => adder_mem_array_3_13_port);
adder_mem_array_reg_3_14_inst : dff_asyncrsthl port map( d =>
multiplier_sigs_3_14_port, gclk => clk, asyncrsthl
=> rst, q => adder_mem_array_3_14_port);
adder_mem_array_reg_3_15_inst : dff_asyncrsthl port map( d =>
multiplier_sigs_3_15_port, gclk => clk, asyncrsthl
=> rst, q => adder_mem_array_3_15_port);
adder_mem_array_reg_3_16_inst : dff_asyncrsthl port map( d =>
multiplier_sigs_3_16_port, gclk => clk, asyncrsthl
=> rst, q => adder_mem_array_3_16_port);
adder_mem_array_reg_3_17_inst : dff_asyncrsthl port map( d =>
multiplier_sigs_3_17_port, gclk => clk, asyncrsthl
=> rst, q => adder_mem_array_3_17_port);
adder_mem_array_reg_3_18_inst : dff_asyncrsthl port map( d =>
multiplier_sigs_3_18_port, gclk => clk, asyncrsthl
=> rst, q => adder_mem_array_3_18_port);
adder_mem_array_reg_3_19_inst : dff_asyncrsthl port map( d =>
multiplier_sigs_3_19_port, gclk => clk, asyncrsthl
=> rst, q => adder_mem_array_3_19_port);
adder_mem_array_reg_3_20_inst : dff_asyncrsthl port map( d =>
multiplier_sigs_3_20_port, gclk => clk, asyncrsthl
=> rst, q => adder_mem_array_3_20_port);
adder_mem_array_reg_3_21_inst : dff_asyncrsthl port map( d =>
multiplier_sigs_3_21_port, gclk => clk, asyncrsthl
=> rst, q => adder_mem_array_3_21_port);
adder_mem_array_reg_3_22_inst : dff_asyncrsthl port map( d =>
multiplier_sigs_3_22_port, gclk => clk, asyncrsthl
=> rst, q => adder_mem_array_3_22_port);
adder_mem_array_reg_3_23_inst : dff_asyncrsthl port map( d =>
multiplier_sigs_3_23_port, gclk => clk, asyncrsthl
=> rst, q => adder_mem_array_3_23_port);
adder_mem_array_reg_3_24_inst : dff_asyncrsthl port map( d =>
multiplier_sigs_3_24_port, gclk => clk, asyncrsthl
=> rst, q => adder_mem_array_3_24_port);
adder_mem_array_reg_3_25_inst : dff_asyncrsthl port map( d =>
multiplier_sigs_3_25_port, gclk => clk, asyncrsthl
=> rst, q => adder_mem_array_3_25_port);
adder_mem_array_reg_3_26_inst : dff_asyncrsthl port map( d =>
multiplier_sigs_3_26_port, gclk => clk, asyncrsthl
=> rst, q => adder_mem_array_3_26_port);
adder_mem_array_reg_3_27_inst : dff_asyncrsthl port map( d =>
multiplier_sigs_3_27_port, gclk => clk, asyncrsthl
=> rst, q => adder_mem_array_3_27_port);
adder_mem_array_reg_3_28_inst : dff_asyncrsthl port map( d =>
multiplier_sigs_3_28_port, gclk => clk, asyncrsthl
=> rst, q => adder_mem_array_3_28_port);
adder_mem_array_reg_3_29_inst : dff_asyncrsthl port map( d =>
multiplier_sigs_3_29_port, gclk => clk, asyncrsthl
=> rst, q => adder_mem_array_3_29_port);
adder_mem_array_reg_3_30_inst : dff_asyncrsthl port map( d =>
multiplier_sigs_3_30_port, gclk => clk, asyncrsthl
=> rst, q => adder_mem_array_3_30_port);
adder_mem_array_reg_3_32_inst : dff_asyncrsthl port map( d =>
multiplier_sigs_3_31_port, gclk => clk, asyncrsthl
=> rst, q => adder_mem_array_3_32_port);
adder_mem_array_reg_3_31_inst : dff_asyncrsthl port map( d =>
multiplier_sigs_3_31_port, gclk => clk, asyncrsthl
=> rst, q => adder_mem_array_3_31_port);
adder_mem_array_reg_2_0_inst : dff_asyncrsthl port map( d => N72, gclk =>
clk, asyncrsthl => rst, q =>
adder_mem_array_2_0_port);
adder_mem_array_reg_2_1_inst : dff_asyncrsthl port map( d => N73, gclk =>
clk, asyncrsthl => rst, q =>
adder_mem_array_2_1_port);
adder_mem_array_reg_2_2_inst : dff_asyncrsthl port map( d => N74, gclk =>
clk, asyncrsthl => rst, q =>
adder_mem_array_2_2_port);
adder_mem_array_reg_2_3_inst : dff_asyncrsthl port map( d => N75, gclk =>
clk, asyncrsthl => rst, q =>
adder_mem_array_2_3_port);
adder_mem_array_reg_2_4_inst : dff_asyncrsthl port map( d => N76, gclk =>
clk, asyncrsthl => rst, q =>
adder_mem_array_2_4_port);
adder_mem_array_reg_2_5_inst : dff_asyncrsthl port map( d => N77, gclk =>
clk, asyncrsthl => rst, q =>
adder_mem_array_2_5_port);
adder_mem_array_reg_2_6_inst : dff_asyncrsthl port map( d => N78, gclk =>
clk, asyncrsthl => rst, q =>
adder_mem_array_2_6_port);
adder_mem_array_reg_2_7_inst : dff_asyncrsthl port map( d => N79, gclk =>
clk, asyncrsthl => rst, q =>
adder_mem_array_2_7_port);
adder_mem_array_reg_2_8_inst : dff_asyncrsthl port map( d => N80, gclk =>
clk, asyncrsthl => rst, q =>
adder_mem_array_2_8_port);
adder_mem_array_reg_2_9_inst : dff_asyncrsthl port map( d => N81, gclk =>
clk, asyncrsthl => rst, q =>
adder_mem_array_2_9_port);
adder_mem_array_reg_2_10_inst : dff_asyncrsthl port map( d => N82, gclk =>
clk, asyncrsthl => rst, q =>
adder_mem_array_2_10_port);
adder_mem_array_reg_2_11_inst : dff_asyncrsthl port map( d => N83, gclk =>
clk, asyncrsthl => rst, q =>
adder_mem_array_2_11_port);
adder_mem_array_reg_2_12_inst : dff_asyncrsthl port map( d => N84, gclk =>
clk, asyncrsthl => rst, q =>
adder_mem_array_2_12_port);
adder_mem_array_reg_2_13_inst : dff_asyncrsthl port map( d => N85, gclk =>
clk, asyncrsthl => rst, q =>
adder_mem_array_2_13_port);
adder_mem_array_reg_2_14_inst : dff_asyncrsthl port map( d => N86, gclk =>
clk, asyncrsthl => rst, q =>
adder_mem_array_2_14_port);
adder_mem_array_reg_2_15_inst : dff_asyncrsthl port map( d => N87, gclk =>
clk, asyncrsthl => rst, q =>
adder_mem_array_2_15_port);
adder_mem_array_reg_2_16_inst : dff_asyncrsthl port map( d => N88, gclk =>
clk, asyncrsthl => rst, q =>
adder_mem_array_2_16_port);
adder_mem_array_reg_2_17_inst : dff_asyncrsthl port map( d => N89, gclk =>
clk, asyncrsthl => rst, q =>
adder_mem_array_2_17_port);
adder_mem_array_reg_2_18_inst : dff_asyncrsthl port map( d => N90, gclk =>
clk, asyncrsthl => rst, q =>
adder_mem_array_2_18_port);
adder_mem_array_reg_2_19_inst : dff_asyncrsthl port map( d => N91, gclk =>
clk, asyncrsthl => rst, q =>
adder_mem_array_2_19_port);
adder_mem_array_reg_2_20_inst : dff_asyncrsthl port map( d => N92, gclk =>
clk, asyncrsthl => rst, q =>
adder_mem_array_2_20_port);
adder_mem_array_reg_2_21_inst : dff_asyncrsthl port map( d => N93, gclk =>
clk, asyncrsthl => rst, q =>
adder_mem_array_2_21_port);
adder_mem_array_reg_2_22_inst : dff_asyncrsthl port map( d => N94, gclk =>
clk, asyncrsthl => rst, q =>
adder_mem_array_2_22_port);
adder_mem_array_reg_2_23_inst : dff_asyncrsthl port map( d => N95, gclk =>
clk, asyncrsthl => rst, q =>
adder_mem_array_2_23_port);
adder_mem_array_reg_2_24_inst : dff_asyncrsthl port map( d => N96, gclk =>
clk, asyncrsthl => rst, q =>
adder_mem_array_2_24_port);
adder_mem_array_reg_2_25_inst : dff_asyncrsthl port map( d => N97, gclk =>
clk, asyncrsthl => rst, q =>
adder_mem_array_2_25_port);
adder_mem_array_reg_2_26_inst : dff_asyncrsthl port map( d => N98, gclk =>
clk, asyncrsthl => rst, q =>
adder_mem_array_2_26_port);
adder_mem_array_reg_2_27_inst : dff_asyncrsthl port map( d => N99, gclk =>
clk, asyncrsthl => rst, q =>
adder_mem_array_2_27_port);
adder_mem_array_reg_2_28_inst : dff_asyncrsthl port map( d => N100, gclk =>
clk, asyncrsthl => rst, q =>
adder_mem_array_2_28_port);
adder_mem_array_reg_2_29_inst : dff_asyncrsthl port map( d => N101, gclk =>
clk, asyncrsthl => rst, q =>
adder_mem_array_2_29_port);
adder_mem_array_reg_2_30_inst : dff_asyncrsthl port map( d => N102, gclk =>
clk, asyncrsthl => rst, q =>
adder_mem_array_2_30_port);
adder_mem_array_reg_2_31_inst : dff_asyncrsthl port map( d => N103, gclk =>
clk, asyncrsthl => rst, q =>
adder_mem_array_2_31_port);
adder_mem_array_reg_2_32_inst : dff_asyncrsthl port map( d => N104, gclk =>
clk, asyncrsthl => rst, q =>
adder_mem_array_2_32_port);
adder_mem_array_reg_1_0_inst : dff_asyncrsthl port map( d => N39, gclk =>
clk, asyncrsthl => rst, q =>
adder_mem_array_1_0_port);
adder_mem_array_reg_1_1_inst : dff_asyncrsthl port map( d => N40, gclk =>
clk, asyncrsthl => rst, q =>
adder_mem_array_1_1_port);
adder_mem_array_reg_1_2_inst : dff_asyncrsthl port map( d => N41, gclk =>
clk, asyncrsthl => rst, q =>
adder_mem_array_1_2_port);
adder_mem_array_reg_1_3_inst : dff_asyncrsthl port map( d => N42, gclk =>
clk, asyncrsthl => rst, q =>
adder_mem_array_1_3_port);
adder_mem_array_reg_1_4_inst : dff_asyncrsthl port map( d => N43, gclk =>
clk, asyncrsthl => rst, q =>
adder_mem_array_1_4_port);
adder_mem_array_reg_1_5_inst : dff_asyncrsthl port map( d => N44, gclk =>
clk, asyncrsthl => rst, q =>
adder_mem_array_1_5_port);
adder_mem_array_reg_1_6_inst : dff_asyncrsthl port map( d => N45, gclk =>
clk, asyncrsthl => rst, q =>
adder_mem_array_1_6_port);
adder_mem_array_reg_1_7_inst : dff_asyncrsthl port map( d => N46, gclk =>
clk, asyncrsthl => rst, q =>
adder_mem_array_1_7_port);
adder_mem_array_reg_1_8_inst : dff_asyncrsthl port map( d => N47, gclk =>
clk, asyncrsthl => rst, q =>
adder_mem_array_1_8_port);
adder_mem_array_reg_1_9_inst : dff_asyncrsthl port map( d => N48, gclk =>
clk, asyncrsthl => rst, q =>
adder_mem_array_1_9_port);
adder_mem_array_reg_1_10_inst : dff_asyncrsthl port map( d => N49, gclk =>
clk, asyncrsthl => rst, q =>
adder_mem_array_1_10_port);
adder_mem_array_reg_1_11_inst : dff_asyncrsthl port map( d => N50, gclk =>
clk, asyncrsthl => rst, q =>
adder_mem_array_1_11_port);
adder_mem_array_reg_1_12_inst : dff_asyncrsthl port map( d => N51, gclk =>
clk, asyncrsthl => rst, q =>
adder_mem_array_1_12_port);
adder_mem_array_reg_1_13_inst : dff_asyncrsthl port map( d => N52, gclk =>
clk, asyncrsthl => rst, q =>
adder_mem_array_1_13_port);
adder_mem_array_reg_1_14_inst : dff_asyncrsthl port map( d => N53, gclk =>
clk, asyncrsthl => rst, q =>
adder_mem_array_1_14_port);
adder_mem_array_reg_1_15_inst : dff_asyncrsthl port map( d => N54, gclk =>
clk, asyncrsthl => rst, q =>
adder_mem_array_1_15_port);
adder_mem_array_reg_1_16_inst : dff_asyncrsthl port map( d => N55, gclk =>
clk, asyncrsthl => rst, q =>
adder_mem_array_1_16_port);
adder_mem_array_reg_1_17_inst : dff_asyncrsthl port map( d => N56, gclk =>
clk, asyncrsthl => rst, q =>
adder_mem_array_1_17_port);
adder_mem_array_reg_1_18_inst : dff_asyncrsthl port map( d => N57, gclk =>
clk, asyncrsthl => rst, q =>
adder_mem_array_1_18_port);
adder_mem_array_reg_1_19_inst : dff_asyncrsthl port map( d => N58, gclk =>
clk, asyncrsthl => rst, q =>
adder_mem_array_1_19_port);
adder_mem_array_reg_1_20_inst : dff_asyncrsthl port map( d => N59, gclk =>
clk, asyncrsthl => rst, q =>
adder_mem_array_1_20_port);
adder_mem_array_reg_1_21_inst : dff_asyncrsthl port map( d => N60, gclk =>
clk, asyncrsthl => rst, q =>
adder_mem_array_1_21_port);
adder_mem_array_reg_1_22_inst : dff_asyncrsthl port map( d => N61, gclk =>
clk, asyncrsthl => rst, q =>
adder_mem_array_1_22_port);
adder_mem_array_reg_1_23_inst : dff_asyncrsthl port map( d => N62, gclk =>
clk, asyncrsthl => rst, q =>
adder_mem_array_1_23_port);
adder_mem_array_reg_1_24_inst : dff_asyncrsthl port map( d => N63, gclk =>
clk, asyncrsthl => rst, q =>
adder_mem_array_1_24_port);
adder_mem_array_reg_1_25_inst : dff_asyncrsthl port map( d => N64, gclk =>
clk, asyncrsthl => rst, q =>
adder_mem_array_1_25_port);
adder_mem_array_reg_1_26_inst : dff_asyncrsthl port map( d => N65, gclk =>
clk, asyncrsthl => rst, q =>
adder_mem_array_1_26_port);
adder_mem_array_reg_1_27_inst : dff_asyncrsthl port map( d => N66, gclk =>
clk, asyncrsthl => rst, q =>
adder_mem_array_1_27_port);
adder_mem_array_reg_1_28_inst : dff_asyncrsthl port map( d => N67, gclk =>
clk, asyncrsthl => rst, q =>
adder_mem_array_1_28_port);
adder_mem_array_reg_1_29_inst : dff_asyncrsthl port map( d => N68, gclk =>
clk, asyncrsthl => rst, q =>
adder_mem_array_1_29_port);
adder_mem_array_reg_1_30_inst : dff_asyncrsthl port map( d => N69, gclk =>
clk, asyncrsthl => rst, q =>
adder_mem_array_1_30_port);
adder_mem_array_reg_1_31_inst : dff_asyncrsthl port map( d => N70, gclk =>
clk, asyncrsthl => rst, q =>
adder_mem_array_1_31_port);
adder_mem_array_reg_1_32_inst : dff_asyncrsthl port map( d => N71, gclk =>
clk, asyncrsthl => rst, q =>
adder_mem_array_1_32_port);
adder_mem_array_reg_0_0_inst : dff_asyncrsthl port map( d => N6, gclk => clk
, asyncrsthl => rst, q => adder_mem_array_0_0_port);
adder_mem_array_reg_0_1_inst : dff_asyncrsthl port map( d => N7, gclk => clk
, asyncrsthl => rst, q => adder_mem_array_0_1_port);
adder_mem_array_reg_0_2_inst : dff_asyncrsthl port map( d => N8, gclk => clk
, asyncrsthl => rst, q => adder_mem_array_0_2_port);
adder_mem_array_reg_0_3_inst : dff_asyncrsthl port map( d => N9, gclk => clk
, asyncrsthl => rst, q => adder_mem_array_0_3_port);
adder_mem_array_reg_0_4_inst : dff_asyncrsthl port map( d => N10, gclk =>
clk, asyncrsthl => rst, q =>
adder_mem_array_0_4_port);
adder_mem_array_reg_0_5_inst : dff_asyncrsthl port map( d => N11, gclk =>
clk, asyncrsthl => rst, q =>
adder_mem_array_0_5_port);
adder_mem_array_reg_0_6_inst : dff_asyncrsthl port map( d => N12, gclk =>
clk, asyncrsthl => rst, q =>
adder_mem_array_0_6_port);
adder_mem_array_reg_0_7_inst : dff_asyncrsthl port map( d => N13, gclk =>
clk, asyncrsthl => rst, q =>
adder_mem_array_0_7_port);
adder_mem_array_reg_0_8_inst : dff_asyncrsthl port map( d => N14, gclk =>
clk, asyncrsthl => rst, q =>
adder_mem_array_0_8_port);
adder_mem_array_reg_0_9_inst : dff_asyncrsthl port map( d => N15, gclk =>
clk, asyncrsthl => rst, q =>
adder_mem_array_0_9_port);
adder_mem_array_reg_0_10_inst : dff_asyncrsthl port map( d => N16, gclk =>
clk, asyncrsthl => rst, q =>
adder_mem_array_0_10_port);
adder_mem_array_reg_0_11_inst : dff_asyncrsthl port map( d => N17, gclk =>
clk, asyncrsthl => rst, q =>
adder_mem_array_0_11_port);
adder_mem_array_reg_0_12_inst : dff_asyncrsthl port map( d => N18, gclk =>
clk, asyncrsthl => rst, q =>
adder_mem_array_0_12_port);
adder_mem_array_reg_0_13_inst : dff_asyncrsthl port map( d => N19, gclk =>
clk, asyncrsthl => rst, q =>
adder_mem_array_0_13_port);
adder_mem_array_reg_0_14_inst : dff_asyncrsthl port map( d => N20, gclk =>
clk, asyncrsthl => rst, q =>
adder_mem_array_0_14_port);
adder_mem_array_reg_0_15_inst : dff_asyncrsthl port map( d => N21, gclk =>
clk, asyncrsthl => rst, q =>
adder_mem_array_0_15_port);
adder_mem_array_reg_0_16_inst : dff_asyncrsthl port map( d => N22, gclk =>
clk, asyncrsthl => rst, q =>
adder_mem_array_0_16_port);
adder_mem_array_reg_0_17_inst : dff_asyncrsthl port map( d => N23, gclk =>
clk, asyncrsthl => rst, q =>
adder_mem_array_0_17_port);
adder_mem_array_reg_0_18_inst : dff_asyncrsthl port map( d => N24, gclk =>
clk, asyncrsthl => rst, q =>
adder_mem_array_0_18_port);
adder_mem_array_reg_0_19_inst : dff_asyncrsthl port map( d => N25, gclk =>
clk, asyncrsthl => rst, q =>
adder_mem_array_0_19_port);
adder_mem_array_reg_0_20_inst : dff_asyncrsthl port map( d => N26, gclk =>
clk, asyncrsthl => rst, q =>
adder_mem_array_0_20_port);
adder_mem_array_reg_0_21_inst : dff_asyncrsthl port map( d => N27, gclk =>
clk, asyncrsthl => rst, q =>
adder_mem_array_0_21_port);
adder_mem_array_reg_0_22_inst : dff_asyncrsthl port map( d => N28, gclk =>
clk, asyncrsthl => rst, q =>
adder_mem_array_0_22_port);
adder_mem_array_reg_0_23_inst : dff_asyncrsthl port map( d => N29, gclk =>
clk, asyncrsthl => rst, q =>
adder_mem_array_0_23_port);
adder_mem_array_reg_0_24_inst : dff_asyncrsthl port map( d => N30, gclk =>
clk, asyncrsthl => rst, q =>
adder_mem_array_0_24_port);
adder_mem_array_reg_0_25_inst : dff_asyncrsthl port map( d => N31, gclk =>
clk, asyncrsthl => rst, q =>
adder_mem_array_0_25_port);
adder_mem_array_reg_0_26_inst : dff_asyncrsthl port map( d => N32, gclk =>
clk, asyncrsthl => rst, q =>
adder_mem_array_0_26_port);
adder_mem_array_reg_0_27_inst : dff_asyncrsthl port map( d => N33, gclk =>
clk, asyncrsthl => rst, q =>
adder_mem_array_0_27_port);
adder_mem_array_reg_0_28_inst : dff_asyncrsthl port map( d => N34, gclk =>
clk, asyncrsthl => rst, q =>
adder_mem_array_0_28_port);
adder_mem_array_reg_0_29_inst : dff_asyncrsthl port map( d => N35, gclk =>
clk, asyncrsthl => rst, q =>
adder_mem_array_0_29_port);
adder_mem_array_reg_0_30_inst : dff_asyncrsthl port map( d => N36, gclk =>
clk, asyncrsthl => rst, q =>
adder_mem_array_0_30_port);
adder_mem_array_reg_0_31_inst : dff_asyncrsthl port map( d => N37, gclk =>
clk, asyncrsthl => rst, q =>
adder_mem_array_0_31_port);
adder_mem_array_reg_0_32_inst : dff_asyncrsthl port map( d => N38, gclk =>
clk, asyncrsthl => rst, q =>
adder_mem_array_0_32_port);
coeff_cnt_reg_0_inst : dff port map( d => n206, gclk => clk, rnot => n121, q
=> coeff_cnt_0_port);
ready_h_out_reg_reg : dff_asyncprehh port map( d => n205, gclk => clk,
asyncprehh => rst, q => ready_h_out_port);
coeff_cnt_reg_1_inst : dff port map( d => n204, gclk => clk, rnot => n121, q
=> coeff_cnt_1_port);
coefficient_mem_array_reg_3_0_inst : dff port map( d => n203, gclk => clk,
rnot => n121, q => coefficient_mem_array_3_0_port);
coefficient_mem_array_reg_2_0_inst : dff port map( d => n202, gclk => clk,
rnot => n121, q => coefficient_mem_array_2_0_port);
coefficient_mem_array_reg_1_0_inst : dff port map( d => n201, gclk => clk,
rnot => n121, q => coefficient_mem_array_1_0_port);
coefficient_mem_array_reg_0_0_inst : dff port map( d => n200, gclk => clk,
rnot => n121, q => coefficient_mem_array_0_0_port);
coefficient_mem_array_reg_3_15_inst : dff port map( d => n199, gclk => clk,
rnot => n121, q => coefficient_mem_array_3_15_port);
coefficient_mem_array_reg_2_15_inst : dff port map( d => n198, gclk => clk,
rnot => n121, q => coefficient_mem_array_2_15_port);
coefficient_mem_array_reg_1_15_inst : dff port map( d => n197, gclk => clk,
rnot => n121, q => coefficient_mem_array_1_15_port);
coefficient_mem_array_reg_0_15_inst : dff port map( d => n196, gclk => clk,
rnot => n121, q => coefficient_mem_array_0_15_port);
coefficient_mem_array_reg_3_14_inst : dff port map( d => n195, gclk => clk,
rnot => n121, q => coefficient_mem_array_3_14_port);
coefficient_mem_array_reg_2_14_inst : dff port map( d => n194, gclk => clk,
rnot => n121, q => coefficient_mem_array_2_14_port);
coefficient_mem_array_reg_1_14_inst : dff port map( d => n193, gclk => clk,
rnot => n121, q => coefficient_mem_array_1_14_port);
coefficient_mem_array_reg_0_14_inst : dff port map( d => n192, gclk => clk,
rnot => n121, q => coefficient_mem_array_0_14_port);
coefficient_mem_array_reg_3_13_inst : dff port map( d => n191, gclk => clk,
rnot => n121, q => coefficient_mem_array_3_13_port);
coefficient_mem_array_reg_2_13_inst : dff port map( d => n190, gclk => clk,
rnot => n121, q => coefficient_mem_array_2_13_port);
coefficient_mem_array_reg_1_13_inst : dff port map( d => n189, gclk => clk,
rnot => n121, q => coefficient_mem_array_1_13_port);
coefficient_mem_array_reg_0_13_inst : dff port map( d => n188, gclk => clk,
rnot => n121, q => coefficient_mem_array_0_13_port);
coefficient_mem_array_reg_3_12_inst : dff port map( d => n187, gclk => clk,
rnot => n121, q => coefficient_mem_array_3_12_port);
coefficient_mem_array_reg_2_12_inst : dff port map( d => n186, gclk => clk,
rnot => n121, q => coefficient_mem_array_2_12_port);
coefficient_mem_array_reg_1_12_inst : dff port map( d => n185, gclk => clk,
rnot => n121, q => coefficient_mem_array_1_12_port);
coefficient_mem_array_reg_0_12_inst : dff port map( d => n184, gclk => clk,
rnot => n121, q => coefficient_mem_array_0_12_port);
coefficient_mem_array_reg_3_11_inst : dff port map( d => n183, gclk => clk,
rnot => n121, q => coefficient_mem_array_3_11_port);
coefficient_mem_array_reg_2_11_inst : dff port map( d => n182, gclk => clk,
rnot => n121, q => coefficient_mem_array_2_11_port);
coefficient_mem_array_reg_1_11_inst : dff port map( d => n181, gclk => clk,
rnot => n121, q => coefficient_mem_array_1_11_port);
coefficient_mem_array_reg_0_11_inst : dff port map( d => n180, gclk => clk,
rnot => n121, q => coefficient_mem_array_0_11_port);
coefficient_mem_array_reg_3_10_inst : dff port map( d => n179, gclk => clk,
rnot => n121, q => coefficient_mem_array_3_10_port);
coefficient_mem_array_reg_2_10_inst : dff port map( d => n178, gclk => clk,
rnot => n121, q => coefficient_mem_array_2_10_port);
coefficient_mem_array_reg_1_10_inst : dff port map( d => n177, gclk => clk,
rnot => n121, q => coefficient_mem_array_1_10_port);
coefficient_mem_array_reg_0_10_inst : dff port map( d => n176, gclk => clk,
rnot => n121, q => coefficient_mem_array_0_10_port);
coefficient_mem_array_reg_3_9_inst : dff port map( d => n175, gclk => clk,
rnot => n121, q => coefficient_mem_array_3_9_port);
coefficient_mem_array_reg_2_9_inst : dff port map( d => n174, gclk => clk,
rnot => n121, q => coefficient_mem_array_2_9_port);
coefficient_mem_array_reg_1_9_inst : dff port map( d => n173, gclk => clk,
rnot => n121, q => coefficient_mem_array_1_9_port);
coefficient_mem_array_reg_0_9_inst : dff port map( d => n172, gclk => clk,
rnot => n121, q => coefficient_mem_array_0_9_port);
coefficient_mem_array_reg_3_8_inst : dff port map( d => n171, gclk => clk,
rnot => n121, q => coefficient_mem_array_3_8_port);
coefficient_mem_array_reg_2_8_inst : dff port map( d => n170, gclk => clk,
rnot => n121, q => coefficient_mem_array_2_8_port);
coefficient_mem_array_reg_1_8_inst : dff port map( d => n169, gclk => clk,
rnot => n121, q => coefficient_mem_array_1_8_port);
coefficient_mem_array_reg_0_8_inst : dff port map( d => n168, gclk => clk,
rnot => n121, q => coefficient_mem_array_0_8_port);
coefficient_mem_array_reg_3_7_inst : dff port map( d => n167, gclk => clk,
rnot => n121, q => coefficient_mem_array_3_7_port);
coefficient_mem_array_reg_2_7_inst : dff port map( d => n166, gclk => clk,
rnot => n121, q => coefficient_mem_array_2_7_port);
coefficient_mem_array_reg_1_7_inst : dff port map( d => n165, gclk => clk,
rnot => n121, q => coefficient_mem_array_1_7_port);
coefficient_mem_array_reg_0_7_inst : dff port map( d => n164, gclk => clk,
rnot => n121, q => coefficient_mem_array_0_7_port);
coefficient_mem_array_reg_3_6_inst : dff port map( d => n163, gclk => clk,
rnot => n121, q => coefficient_mem_array_3_6_port);
coefficient_mem_array_reg_2_6_inst : dff port map( d => n162, gclk => clk,
rnot => n121, q => coefficient_mem_array_2_6_port);
coefficient_mem_array_reg_1_6_inst : dff port map( d => n161, gclk => clk,
rnot => n121, q => coefficient_mem_array_1_6_port);
coefficient_mem_array_reg_0_6_inst : dff port map( d => n160, gclk => clk,
rnot => n121, q => coefficient_mem_array_0_6_port);
coefficient_mem_array_reg_3_5_inst : dff port map( d => n159, gclk => clk,
rnot => n121, q => coefficient_mem_array_3_5_port);
coefficient_mem_array_reg_2_5_inst : dff port map( d => n158, gclk => clk,
rnot => n121, q => coefficient_mem_array_2_5_port);
coefficient_mem_array_reg_1_5_inst : dff port map( d => n157, gclk => clk,
rnot => n121, q => coefficient_mem_array_1_5_port);
coefficient_mem_array_reg_0_5_inst : dff port map( d => n156, gclk => clk,
rnot => n121, q => coefficient_mem_array_0_5_port);
coefficient_mem_array_reg_3_4_inst : dff port map( d => n155, gclk => clk,
rnot => n121, q => coefficient_mem_array_3_4_port);
coefficient_mem_array_reg_2_4_inst : dff port map( d => n154, gclk => clk,
rnot => n121, q => coefficient_mem_array_2_4_port);
coefficient_mem_array_reg_1_4_inst : dff port map( d => n153, gclk => clk,
rnot => n121, q => coefficient_mem_array_1_4_port);
coefficient_mem_array_reg_0_4_inst : dff port map( d => n152, gclk => clk,
rnot => n121, q => coefficient_mem_array_0_4_port);
coefficient_mem_array_reg_3_3_inst : dff port map( d => n151, gclk => clk,
rnot => n121, q => coefficient_mem_array_3_3_port);
coefficient_mem_array_reg_2_3_inst : dff port map( d => n150, gclk => clk,
rnot => n121, q => coefficient_mem_array_2_3_port);
coefficient_mem_array_reg_1_3_inst : dff port map( d => n149, gclk => clk,
rnot => n121, q => coefficient_mem_array_1_3_port);
coefficient_mem_array_reg_0_3_inst : dff port map( d => n148, gclk => clk,
rnot => n121, q => coefficient_mem_array_0_3_port);
coefficient_mem_array_reg_3_2_inst : dff port map( d => n147, gclk => clk,
rnot => n121, q => coefficient_mem_array_3_2_port);
coefficient_mem_array_reg_2_2_inst : dff port map( d => n146, gclk => clk,
rnot => n121, q => coefficient_mem_array_2_2_port);
coefficient_mem_array_reg_1_2_inst : dff port map( d => n145, gclk => clk,
rnot => n121, q => coefficient_mem_array_1_2_port);
coefficient_mem_array_reg_0_2_inst : dff port map( d => n144, gclk => clk,
rnot => n121, q => coefficient_mem_array_0_2_port);
coefficient_mem_array_reg_3_1_inst : dff port map( d => n143, gclk => clk,
rnot => n121, q => coefficient_mem_array_3_1_port);
coefficient_mem_array_reg_2_1_inst : dff port map( d => n142, gclk => clk,
rnot => n121, q => coefficient_mem_array_2_1_port);
coefficient_mem_array_reg_1_1_inst : dff port map( d => n141, gclk => clk,
rnot => n121, q => coefficient_mem_array_1_1_port);
coefficient_mem_array_reg_0_1_inst : dff port map( d => n140, gclk => clk,
rnot => n121, q => coefficient_mem_array_0_1_port);
valid_out_reg_reg : dff port map( d => n139, gclk => clk, rnot => n121, q =>
valid_out_port);
ready_x_out_reg_reg : dff port map( d => n138, gclk => clk, rnot => n121, q
=> ready_x_out_port);
input_sample_mem_reg_0_inst : dff port map( d => n137, gclk => clk, rnot =>
n121, q => input_sample_mem_0_port);
input_sample_mem_reg_15_inst : dff port map( d => n136, gclk => clk, rnot =>
n121, q => input_sample_mem_15_port);
input_sample_mem_reg_14_inst : dff port map( d => n135, gclk => clk, rnot =>
n121, q => input_sample_mem_14_port);
input_sample_mem_reg_13_inst : dff port map( d => n134, gclk => clk, rnot =>
n121, q => input_sample_mem_13_port);
input_sample_mem_reg_12_inst : dff port map( d => n133, gclk => clk, rnot =>
n121, q => input_sample_mem_12_port);
input_sample_mem_reg_11_inst : dff port map( d => n132, gclk => clk, rnot =>
n121, q => input_sample_mem_11_port);
input_sample_mem_reg_10_inst : dff port map( d => n131, gclk => clk, rnot =>
n121, q => input_sample_mem_10_port);
input_sample_mem_reg_9_inst : dff port map( d => n130, gclk => clk, rnot =>
n121, q => input_sample_mem_9_port);
input_sample_mem_reg_8_inst : dff port map( d => n129, gclk => clk, rnot =>
n121, q => input_sample_mem_8_port);
input_sample_mem_reg_7_inst : dff port map( d => n128, gclk => clk, rnot =>
n121, q => input_sample_mem_7_port);
input_sample_mem_reg_6_inst : dff port map( d => n127, gclk => clk, rnot =>
n121, q => input_sample_mem_6_port);
input_sample_mem_reg_5_inst : dff port map( d => n126, gclk => clk, rnot =>
n121, q => input_sample_mem_5_port);
input_sample_mem_reg_4_inst : dff port map( d => n125, gclk => clk, rnot =>
n121, q => input_sample_mem_4_port);
input_sample_mem_reg_3_inst : dff port map( d => n124, gclk => clk, rnot =>
n121, q => input_sample_mem_3_port);
input_sample_mem_reg_2_inst : dff port map( d => n123, gclk => clk, rnot =>
n121, q => input_sample_mem_2_port);
input_sample_mem_reg_1_inst : dff port map( d => n122, gclk => clk, rnot =>
n121, q => input_sample_mem_1_port);
U3 : inv port map( inb => n16_port, outb => n139);
U4 : aoi12 port map( b => coeff_cnt_0_port, c => coeff_cnt_1_port, a =>
valid_out_port, outb => n16_port);
U12 : inv port map( inb => n17_port, outb => n138);
U13 : aoi12 port map( b => coeff_cnt_0_port, c => coeff_cnt_1_port, a =>
ready_x_out_port, outb => n17_port);
U14 : aoi12 port map( b => coeff_cnt_1_port, c => coeff_cnt_0_port, a =>
n18_port, outb => n205);
U15 : inv port map( inb => ready_h_out_port, outb => n18_port);
U16 : inv port map( inb => n19_port, outb => n130);
U17 : aoi22 port map( a => x_data_in(9), b => n20_port, c =>
input_sample_mem_9_port, d => n21_port, outb =>
n19_port);
U18 : inv port map( inb => n22_port, outb => n129);
U19 : aoi22 port map( a => x_data_in(8), b => n20_port, c =>
input_sample_mem_8_port, d => n21_port, outb =>
n22_port);
U20 : inv port map( inb => n23_port, outb => n128);
U21 : aoi22 port map( a => x_data_in(7), b => n20_port, c =>
input_sample_mem_7_port, d => n21_port, outb =>
n23_port);
U22 : inv port map( inb => n24_port, outb => n127);
U23 : aoi22 port map( a => x_data_in(6), b => n20_port, c =>
input_sample_mem_6_port, d => n21_port, outb =>
n24_port);
U24 : inv port map( inb => n25_port, outb => n126);
U25 : aoi22 port map( a => x_data_in(5), b => n20_port, c =>
input_sample_mem_5_port, d => n21_port, outb =>
n25_port);
U26 : inv port map( inb => n26_port, outb => n125);
U27 : aoi22 port map( a => x_data_in(4), b => n20_port, c =>
input_sample_mem_4_port, d => n21_port, outb =>
n26_port);
U28 : inv port map( inb => n27_port, outb => n124);
U29 : aoi22 port map( a => x_data_in(3), b => n20_port, c =>
input_sample_mem_3_port, d => n21_port, outb =>
n27_port);
U30 : inv port map( inb => n28_port, outb => n123);
U31 : aoi22 port map( a => x_data_in(2), b => n20_port, c =>
input_sample_mem_2_port, d => n21_port, outb =>
n28_port);
U32 : inv port map( inb => n29_port, outb => n122);
U33 : aoi22 port map( a => x_data_in(1), b => n20_port, c =>
input_sample_mem_1_port, d => n21_port, outb =>
n29_port);
U34 : inv port map( inb => n30_port, outb => n136);
U35 : aoi22 port map( a => x_data_in(15), b => n20_port, c =>
input_sample_mem_15_port, d => n21_port, outb =>
n30_port);
U36 : inv port map( inb => n31_port, outb => n135);
U37 : aoi22 port map( a => x_data_in(14), b => n20_port, c =>
input_sample_mem_14_port, d => n21_port, outb =>
n31_port);
U38 : inv port map( inb => n32_port, outb => n134);
U39 : aoi22 port map( a => x_data_in(13), b => n20_port, c =>
input_sample_mem_13_port, d => n21_port, outb =>
n32_port);
U40 : inv port map( inb => n33_port, outb => n133);
U41 : aoi22 port map( a => x_data_in(12), b => n20_port, c =>
input_sample_mem_12_port, d => n21_port, outb =>
n33_port);
U42 : inv port map( inb => n34_port, outb => n132);
U43 : aoi22 port map( a => x_data_in(11), b => n20_port, c =>
input_sample_mem_11_port, d => n21_port, outb =>
n34_port);
U44 : inv port map( inb => n35_port, outb => n131);
U45 : aoi22 port map( a => x_data_in(10), b => n20_port, c =>
input_sample_mem_10_port, d => n21_port, outb =>
n35_port);
U46 : inv port map( inb => n36_port, outb => n137);
U47 : aoi22 port map( a => x_data_in(0), b => n20_port, c =>
input_sample_mem_0_port, d => n21_port, outb =>
n36_port);
U48 : inv port map( inb => n21_port, outb => n20_port);
U49 : nand2 port map( a => valid_x_in, b => ready_x_out_port, outb =>
n21_port);
U50 : inv port map( inb => n37_port, outb => n175);
U51 : aoi22 port map( a => n38_port, b => h_data_in(9), c => n39_port, d =>
coefficient_mem_array_3_9_port, outb => n37_port);
U52 : inv port map( inb => n40_port, outb => n171);
U53 : aoi22 port map( a => n38_port, b => h_data_in(8), c => n39_port, d =>
coefficient_mem_array_3_8_port, outb => n40_port);
U54 : inv port map( inb => n41_port, outb => n167);
U55 : aoi22 port map( a => n38_port, b => h_data_in(7), c => n39_port, d =>
coefficient_mem_array_3_7_port, outb => n41_port);
U56 : inv port map( inb => n42_port, outb => n163);
U57 : aoi22 port map( a => n38_port, b => h_data_in(6), c => n39_port, d =>
coefficient_mem_array_3_6_port, outb => n42_port);
U58 : inv port map( inb => n43_port, outb => n159);
U59 : aoi22 port map( a => n38_port, b => h_data_in(5), c => n39_port, d =>
coefficient_mem_array_3_5_port, outb => n43_port);
U60 : inv port map( inb => n44_port, outb => n155);
U61 : aoi22 port map( a => n38_port, b => h_data_in(4), c => n39_port, d =>
coefficient_mem_array_3_4_port, outb => n44_port);
U62 : inv port map( inb => n45_port, outb => n151);
U63 : aoi22 port map( a => n38_port, b => h_data_in(3), c => n39_port, d =>
coefficient_mem_array_3_3_port, outb => n45_port);
U64 : inv port map( inb => n46_port, outb => n147);
U65 : aoi22 port map( a => n38_port, b => h_data_in(2), c => n39_port, d =>
coefficient_mem_array_3_2_port, outb => n46_port);
U66 : inv port map( inb => n47_port, outb => n143);
U67 : aoi22 port map( a => n38_port, b => h_data_in(1), c => n39_port, d =>
coefficient_mem_array_3_1_port, outb => n47_port);
U68 : inv port map( inb => n48_port, outb => n199);
U69 : aoi22 port map( a => n38_port, b => h_data_in(15), c => n39_port, d =>
coefficient_mem_array_3_15_port, outb => n48_port);
U70 : inv port map( inb => n49_port, outb => n195);
U71 : aoi22 port map( a => n38_port, b => h_data_in(14), c => n39_port, d =>
coefficient_mem_array_3_14_port, outb => n49_port);
U72 : inv port map( inb => n50_port, outb => n191);
U73 : aoi22 port map( a => n38_port, b => h_data_in(13), c => n39_port, d =>
coefficient_mem_array_3_13_port, outb => n50_port);
U74 : inv port map( inb => n51_port, outb => n187);
U75 : aoi22 port map( a => n38_port, b => h_data_in(12), c => n39_port, d =>
coefficient_mem_array_3_12_port, outb => n51_port);
U76 : inv port map( inb => n52_port, outb => n183);
U77 : aoi22 port map( a => n38_port, b => h_data_in(11), c => n39_port, d =>
coefficient_mem_array_3_11_port, outb => n52_port);
U78 : inv port map( inb => n53_port, outb => n179);
U79 : aoi22 port map( a => n38_port, b => h_data_in(10), c => n39_port, d =>
coefficient_mem_array_3_10_port, outb => n53_port);
U80 : inv port map( inb => n54_port, outb => n203);
U81 : aoi22 port map( a => n38_port, b => h_data_in(0), c => n39_port, d =>
coefficient_mem_array_3_0_port, outb => n54_port);
U82 : oai22 port map( a => n55_port, b => n39_port, c => n38_port, d =>
n56_port, outb => n174);
U83 : inv port map( inb => coefficient_mem_array_3_9_port, outb => n55_port)
;
U84 : oai22 port map( a => n39_port, b => n57_port, c => n38_port, d =>
n58_port, outb => n170);
U85 : inv port map( inb => coefficient_mem_array_3_8_port, outb => n57_port)
;
U86 : oai22 port map( a => n39_port, b => n59_port, c => n38_port, d =>
n60_port, outb => n166);
U87 : inv port map( inb => coefficient_mem_array_3_7_port, outb => n59_port)
;
U88 : oai22 port map( a => n39_port, b => n61_port, c => n38_port, d =>
n62_port, outb => n162);
U89 : inv port map( inb => coefficient_mem_array_3_6_port, outb => n61_port)
;
U90 : oai22 port map( a => n39_port, b => n63_port, c => n38_port, d =>
n64_port, outb => n158);
U91 : inv port map( inb => coefficient_mem_array_3_5_port, outb => n63_port)
;
U92 : oai22 port map( a => n39_port, b => n65_port, c => n38_port, d =>
n66_port, outb => n154);
U93 : inv port map( inb => coefficient_mem_array_3_4_port, outb => n65_port)
;
U94 : oai22 port map( a => n39_port, b => n67_port, c => n38_port, d =>
n68_port, outb => n150);
U95 : inv port map( inb => coefficient_mem_array_3_3_port, outb => n67_port)
;
U96 : oai22 port map( a => n39_port, b => n69_port, c => n38_port, d =>
n70_port, outb => n146);
U97 : inv port map( inb => coefficient_mem_array_3_2_port, outb => n69_port)
;
U98 : oai22 port map( a => n39_port, b => n71_port, c => n38_port, d =>
n72_port, outb => n142);
U99 : inv port map( inb => coefficient_mem_array_3_1_port, outb => n71_port)
;
U100 : oai22 port map( a => n39_port, b => n73_port, c => n38_port, d =>
n74_port, outb => n198);
U101 : inv port map( inb => coefficient_mem_array_3_15_port, outb =>
n73_port);
U102 : oai22 port map( a => n39_port, b => n75_port, c => n38_port, d =>
n76_port, outb => n194);
U103 : inv port map( inb => coefficient_mem_array_3_14_port, outb =>
n75_port);
U104 : oai22 port map( a => n39_port, b => n77_port, c => n38_port, d =>
n78_port, outb => n190);
U105 : inv port map( inb => coefficient_mem_array_3_13_port, outb =>
n77_port);
U106 : oai22 port map( a => n39_port, b => n79_port, c => n38_port, d =>
n80_port, outb => n186);
U107 : inv port map( inb => coefficient_mem_array_3_12_port, outb =>
n79_port);
U108 : oai22 port map( a => n39_port, b => n81_port, c => n38_port, d =>
n82_port, outb => n182);
U109 : inv port map( inb => coefficient_mem_array_3_11_port, outb =>
n81_port);
U110 : oai22 port map( a => n39_port, b => n83_port, c => n38_port, d =>
n84_port, outb => n178);
U111 : inv port map( inb => coefficient_mem_array_3_10_port, outb =>
n83_port);
U112 : oai22 port map( a => n39_port, b => n85_port, c => n38_port, d =>
n86_port, outb => n202);
U113 : inv port map( inb => coefficient_mem_array_3_0_port, outb => n85_port
);
U114 : oai22 port map( a => n39_port, b => n56_port, c => n38_port, d =>
n87_port, outb => n173);
U115 : inv port map( inb => coefficient_mem_array_2_9_port, outb => n56_port
);
U116 : oai22 port map( a => n39_port, b => n58_port, c => n38_port, d =>
n88_port, outb => n169);
U117 : inv port map( inb => coefficient_mem_array_2_8_port, outb => n58_port
);
U118 : oai22 port map( a => n39_port, b => n60_port, c => n38_port, d =>
n89_port, outb => n165);
U119 : inv port map( inb => coefficient_mem_array_2_7_port, outb => n60_port
);
U120 : oai22 port map( a => n39_port, b => n62_port, c => n38_port, d =>
n90_port, outb => n161);
U121 : inv port map( inb => coefficient_mem_array_2_6_port, outb => n62_port
);
U122 : oai22 port map( a => n39_port, b => n64_port, c => n38_port, d =>
n91_port, outb => n157);
U123 : inv port map( inb => coefficient_mem_array_2_5_port, outb => n64_port
);
U124 : oai22 port map( a => n39_port, b => n66_port, c => n38_port, d =>
n92_port, outb => n153);
U125 : inv port map( inb => coefficient_mem_array_2_4_port, outb => n66_port
);
U126 : oai22 port map( a => n39_port, b => n68_port, c => n38_port, d =>
n93_port, outb => n149);
U127 : inv port map( inb => coefficient_mem_array_2_3_port, outb => n68_port
);
U128 : oai22 port map( a => n39_port, b => n70_port, c => n38_port, d =>
n94_port, outb => n145);
U129 : inv port map( inb => coefficient_mem_array_2_2_port, outb => n70_port
);
U130 : oai22 port map( a => n39_port, b => n72_port, c => n38_port, d =>
n95_port, outb => n141);
U131 : inv port map( inb => coefficient_mem_array_2_1_port, outb => n72_port
);
U132 : oai22 port map( a => n39_port, b => n74_port, c => n38_port, d =>
n96_port, outb => n197);
U133 : inv port map( inb => coefficient_mem_array_2_15_port, outb =>
n74_port);
U134 : oai22 port map( a => n39_port, b => n76_port, c => n38_port, d =>
n97_port, outb => n193);
U135 : inv port map( inb => coefficient_mem_array_2_14_port, outb =>
n76_port);
U136 : oai22 port map( a => n39_port, b => n78_port, c => n38_port, d =>
n98_port, outb => n189);
U137 : inv port map( inb => coefficient_mem_array_2_13_port, outb =>
n78_port);
U138 : oai22 port map( a => n39_port, b => n80_port, c => n38_port, d =>
n99_port, outb => n185);
U139 : inv port map( inb => coefficient_mem_array_2_12_port, outb =>
n80_port);
U140 : oai22 port map( a => n39_port, b => n82_port, c => n38_port, d =>
n100_port, outb => n181);
U141 : inv port map( inb => coefficient_mem_array_2_11_port, outb =>
n82_port);
U142 : oai22 port map( a => n39_port, b => n84_port, c => n38_port, d =>
n101_port, outb => n177);
U143 : inv port map( inb => coefficient_mem_array_2_10_port, outb =>
n84_port);
U144 : oai22 port map( a => n39_port, b => n86_port, c => n38_port, d =>
n102_port, outb => n201);
U145 : inv port map( inb => coefficient_mem_array_2_0_port, outb => n86_port
);
U146 : oai12 port map( b => n39_port, c => n87_port, a => n103_port, outb =>
n172);
U147 : nand2 port map( a => coefficient_mem_array_0_9_port, b => n39_port,
outb => n103_port);
U148 : inv port map( inb => coefficient_mem_array_1_9_port, outb => n87_port
);
U149 : oai12 port map( b => n39_port, c => n88_port, a => n104_port, outb =>
n168);
U150 : nand2 port map( a => coefficient_mem_array_0_8_port, b => n39_port,
outb => n104_port);
U151 : inv port map( inb => coefficient_mem_array_1_8_port, outb => n88_port
);
U152 : oai12 port map( b => n39_port, c => n89_port, a => n105, outb => n164
);
U153 : nand2 port map( a => coefficient_mem_array_0_7_port, b => n39_port,
outb => n105);
U154 : inv port map( inb => coefficient_mem_array_1_7_port, outb => n89_port
);
U155 : oai12 port map( b => n39_port, c => n90_port, a => n106, outb => n160
);
U156 : nand2 port map( a => coefficient_mem_array_0_6_port, b => n39_port,
outb => n106);
U157 : inv port map( inb => coefficient_mem_array_1_6_port, outb => n90_port
);
U158 : oai12 port map( b => n39_port, c => n91_port, a => n107, outb => n156
);
U159 : nand2 port map( a => coefficient_mem_array_0_5_port, b => n39_port,
outb => n107);
U160 : inv port map( inb => coefficient_mem_array_1_5_port, outb => n91_port
);
U161 : oai12 port map( b => n39_port, c => n92_port, a => n108, outb => n152
);
U162 : nand2 port map( a => coefficient_mem_array_0_4_port, b => n39_port,
outb => n108);
U163 : inv port map( inb => coefficient_mem_array_1_4_port, outb => n92_port
);
U164 : oai12 port map( b => n39_port, c => n93_port, a => n109, outb => n148
);
U165 : nand2 port map( a => coefficient_mem_array_0_3_port, b => n39_port,
outb => n109);
U166 : inv port map( inb => coefficient_mem_array_1_3_port, outb => n93_port
);
U167 : oai12 port map( b => n39_port, c => n94_port, a => n110, outb => n144
);
U168 : nand2 port map( a => coefficient_mem_array_0_2_port, b => n39_port,
outb => n110);
U169 : inv port map( inb => coefficient_mem_array_1_2_port, outb => n94_port
);
U170 : oai12 port map( b => n39_port, c => n95_port, a => n111, outb => n140
);
U171 : nand2 port map( a => coefficient_mem_array_0_1_port, b => n39_port,
outb => n111);
U172 : inv port map( inb => coefficient_mem_array_1_1_port, outb => n95_port
);
U173 : oai12 port map( b => n39_port, c => n96_port, a => n112, outb => n196
);
U174 : nand2 port map( a => coefficient_mem_array_0_15_port, b => n39_port,
outb => n112);
U175 : inv port map( inb => coefficient_mem_array_1_15_port, outb =>
n96_port);
U176 : oai12 port map( b => n39_port, c => n97_port, a => n113, outb => n192
);
U177 : nand2 port map( a => coefficient_mem_array_0_14_port, b => n39_port,
outb => n113);
U178 : inv port map( inb => coefficient_mem_array_1_14_port, outb =>
n97_port);
U179 : oai12 port map( b => n39_port, c => n98_port, a => n114, outb => n188
);
U180 : nand2 port map( a => coefficient_mem_array_0_13_port, b => n39_port,
outb => n114);
U181 : inv port map( inb => coefficient_mem_array_1_13_port, outb =>
n98_port);
U182 : oai12 port map( b => n39_port, c => n99_port, a => n115, outb => n184
);
U183 : nand2 port map( a => coefficient_mem_array_0_12_port, b => n39_port,
outb => n115);
U184 : inv port map( inb => coefficient_mem_array_1_12_port, outb =>
n99_port);
U185 : oai12 port map( b => n39_port, c => n100_port, a => n116, outb =>
n180);
U186 : nand2 port map( a => coefficient_mem_array_0_11_port, b => n39_port,
outb => n116);
U187 : inv port map( inb => coefficient_mem_array_1_11_port, outb =>
n100_port);
U188 : oai12 port map( b => n39_port, c => n101_port, a => n117, outb =>
n176);
U189 : nand2 port map( a => coefficient_mem_array_0_10_port, b => n39_port,
outb => n117);
U190 : inv port map( inb => coefficient_mem_array_1_10_port, outb =>
n101_port);
U191 : oai12 port map( b => n39_port, c => n102_port, a => n118, outb =>
n200);
U192 : nand2 port map( a => coefficient_mem_array_0_0_port, b => n39_port,
outb => n118);
U193 : inv port map( inb => coefficient_mem_array_1_0_port, outb =>
n102_port);
U194 : xor2 port map( a => n119, b => n120, outb => n204);
U195 : nand2 port map( a => coeff_cnt_0_port, b => n38_port, outb => n120);
U196 : inv port map( inb => coeff_cnt_1_port, outb => n119);
U197 : inv port map( inb => rst, outb => n121);
U198 : xor2 port map( a => coeff_cnt_0_port, b => n38_port, outb => n206);
U199 : inv port map( inb => n39_port, outb => n38_port);
U200 : nand2 port map( a => valid_h_in, b => ready_h_out_port, outb =>
n39_port);
U201 : inv port map( inb => n207, outb => y_data_out(9));
U202 : nand2 port map( a => valid_out_port, b => adder_mem_array_0_9_port,
outb => n207);
U203 : inv port map( inb => n208, outb => y_data_out(8));
U204 : nand2 port map( a => adder_mem_array_0_8_port, b => valid_out_port,
outb => n208);
U205 : inv port map( inb => n209, outb => y_data_out(7));
U206 : nand2 port map( a => adder_mem_array_0_7_port, b => valid_out_port,
outb => n209);
U207 : inv port map( inb => n210, outb => y_data_out(6));
U208 : nand2 port map( a => adder_mem_array_0_6_port, b => valid_out_port,
outb => n210);
U209 : inv port map( inb => n211, outb => y_data_out(5));
U210 : nand2 port map( a => adder_mem_array_0_5_port, b => valid_out_port,
outb => n211);
U211 : inv port map( inb => n212, outb => y_data_out(4));
U212 : nand2 port map( a => adder_mem_array_0_4_port, b => valid_out_port,
outb => n212);
U213 : inv port map( inb => n213, outb => y_data_out(3));
U214 : nand2 port map( a => adder_mem_array_0_3_port, b => valid_out_port,
outb => n213);
U215 : inv port map( inb => n214, outb => y_data_out(32));
U216 : nand2 port map( a => adder_mem_array_0_32_port, b => valid_out_port,
outb => n214);
U217 : inv port map( inb => n215, outb => y_data_out(31));
U218 : nand2 port map( a => adder_mem_array_0_31_port, b => valid_out_port,
outb => n215);
U219 : inv port map( inb => n216, outb => y_data_out(30));
U220 : nand2 port map( a => adder_mem_array_0_30_port, b => valid_out_port,
outb => n216);
U221 : inv port map( inb => n217, outb => y_data_out(2));
U222 : nand2 port map( a => adder_mem_array_0_2_port, b => valid_out_port,
outb => n217);
U223 : inv port map( inb => n218, outb => y_data_out(29));
U224 : nand2 port map( a => adder_mem_array_0_29_port, b => valid_out_port,
outb => n218);
U225 : inv port map( inb => n219, outb => y_data_out(28));
U226 : nand2 port map( a => adder_mem_array_0_28_port, b => valid_out_port,
outb => n219);
U227 : inv port map( inb => n220, outb => y_data_out(27));
U228 : nand2 port map( a => adder_mem_array_0_27_port, b => valid_out_port,
outb => n220);
U229 : inv port map( inb => n221, outb => y_data_out(26));
U230 : nand2 port map( a => adder_mem_array_0_26_port, b => valid_out_port,
outb => n221);
U231 : inv port map( inb => n222, outb => y_data_out(25));
U232 : nand2 port map( a => adder_mem_array_0_25_port, b => valid_out_port,
outb => n222);
U233 : inv port map( inb => n223, outb => y_data_out(24));
U234 : nand2 port map( a => adder_mem_array_0_24_port, b => valid_out_port,
outb => n223);
U235 : inv port map( inb => n224, outb => y_data_out(23));
U236 : nand2 port map( a => adder_mem_array_0_23_port, b => valid_out_port,
outb => n224);
U237 : inv port map( inb => n225, outb => y_data_out(22));
U238 : nand2 port map( a => adder_mem_array_0_22_port, b => valid_out_port,
outb => n225);
U239 : inv port map( inb => n226, outb => y_data_out(21));
U240 : nand2 port map( a => adder_mem_array_0_21_port, b => valid_out_port,
outb => n226);
U241 : inv port map( inb => n227, outb => y_data_out(20));
U242 : nand2 port map( a => adder_mem_array_0_20_port, b => valid_out_port,
outb => n227);
U243 : inv port map( inb => n228, outb => y_data_out(1));
U244 : nand2 port map( a => adder_mem_array_0_1_port, b => valid_out_port,
outb => n228);
U245 : inv port map( inb => n229, outb => y_data_out(19));
U246 : nand2 port map( a => adder_mem_array_0_19_port, b => valid_out_port,
outb => n229);
U247 : inv port map( inb => n230, outb => y_data_out(18));
U248 : nand2 port map( a => adder_mem_array_0_18_port, b => valid_out_port,
outb => n230);
U249 : inv port map( inb => n231, outb => y_data_out(17));
U250 : nand2 port map( a => adder_mem_array_0_17_port, b => valid_out_port,
outb => n231);
U251 : inv port map( inb => n232, outb => y_data_out(16));
U252 : nand2 port map( a => adder_mem_array_0_16_port, b => valid_out_port,
outb => n232);
U253 : inv port map( inb => n233, outb => y_data_out(15));
U254 : nand2 port map( a => adder_mem_array_0_15_port, b => valid_out_port,
outb => n233);
U255 : inv port map( inb => n234, outb => y_data_out(14));
U256 : nand2 port map( a => adder_mem_array_0_14_port, b => valid_out_port,
outb => n234);
U257 : inv port map( inb => n235, outb => y_data_out(13));
U258 : nand2 port map( a => adder_mem_array_0_13_port, b => valid_out_port,
outb => n235);
U259 : inv port map( inb => n236, outb => y_data_out(12));
U260 : nand2 port map( a => adder_mem_array_0_12_port, b => valid_out_port,
outb => n236);
U261 : inv port map( inb => n237, outb => y_data_out(11));
U262 : nand2 port map( a => adder_mem_array_0_11_port, b => valid_out_port,
outb => n237);
U263 : inv port map( inb => n238, outb => y_data_out(10));
U264 : nand2 port map( a => adder_mem_array_0_10_port, b => valid_out_port,
outb => n238);
U265 : inv port map( inb => n239, outb => y_data_out(0));
U266 : nand2 port map( a => adder_mem_array_0_0_port, b => valid_out_port,
outb => n239);
mult_125_G3_FS_1_U6_1_1_3 : oai12 port map( b => n6032, c => n6033, a =>
n6034, outb => mult_125_G3_FS_1_C_1_7_0_port);
mult_125_G3_FS_1_U6_1_1_2 : oai12 port map( b => n6029, c => n6030, a =>
n6031, outb => mult_125_G3_FS_1_C_1_6_0_port);
mult_125_G3_FS_1_U6_1_1_1 : oai12 port map( b => n6026, c => n6027, a =>
n6028, outb => mult_125_G3_FS_1_C_1_5_0_port);
mult_125_G3_FS_1_U6_0_7_1 : oai12 port map( b => n6023, c => n6024, a =>
mult_125_G3_FS_1_G_n_int_0_7_0_port, outb =>
mult_125_G3_FS_1_C_1_7_1_port);
mult_125_G3_FS_1_U3_C_0_7_1 : xor2 port map( a =>
mult_125_G3_FS_1_PG_int_0_7_1_port, b =>
mult_125_G3_FS_1_C_1_7_1_port, outb =>
multiplier_sigs_2_31_port);
mult_125_G3_FS_1_U3_B_0_7_1 : nand2 port map( a =>
mult_125_G3_FS_1_G_n_int_0_7_1_port, b =>
mult_125_G3_FS_1_P_0_7_1_port, outb => n6022);
mult_125_G3_FS_1_U2_0_7_1 : nand2 port map( a => mult_125_G3_A1_29_port, b
=> mult_125_G3_A2_29_port, outb =>
mult_125_G3_FS_1_G_n_int_0_7_1_port);
mult_125_G3_FS_1_U1_0_7_1 : nand2 port map( a => n6020, b => n6021, outb =>
mult_125_G3_FS_1_P_0_7_1_port);
mult_125_G3_FS_1_U3_C_0_7_0 : xor2 port map( a =>
mult_125_G3_FS_1_PG_int_0_7_0_port, b =>
mult_125_G3_FS_1_C_1_7_0_port, outb =>
multiplier_sigs_2_30_port);
mult_125_G3_FS_1_U3_B_0_7_0 : nand2 port map( a =>
mult_125_G3_FS_1_G_n_int_0_7_0_port, b =>
mult_125_G3_FS_1_TEMP_P_0_7_0_port, outb => n6019);
mult_125_G3_FS_1_U2_0_7_0 : nand2 port map( a => mult_125_G3_A1_28_port, b
=> mult_125_G3_A2_28_port, outb =>
mult_125_G3_FS_1_G_n_int_0_7_0_port);
mult_125_G3_FS_1_U1_0_7_0 : nand2 port map( a => n6017, b => n6018, outb =>
mult_125_G3_FS_1_TEMP_P_0_7_0_port);
mult_125_G3_FS_1_U6_0_6_3 : oai12 port map( b => n6015, c => n6016, a =>
mult_125_G3_FS_1_G_n_int_0_6_2_port, outb =>
mult_125_G3_FS_1_C_1_6_3_port);
mult_125_G3_FS_1_U5_0_6_3 : oai12 port map( b => n6013, c => n6014, a =>
mult_125_G3_FS_1_G_n_int_0_6_3_port, outb =>
mult_125_G3_FS_1_G_1_1_2_port);
mult_125_G3_FS_1_U4_0_6_3 : nand2 port map( a =>
mult_125_G3_FS_1_TEMP_P_0_6_2_port, b =>
mult_125_G3_FS_1_P_0_6_3_port, outb => n6033);
mult_125_G3_FS_1_U3_C_0_6_3 : xor2 port map( a =>
mult_125_G3_FS_1_PG_int_0_6_3_port, b =>
mult_125_G3_FS_1_C_1_6_3_port, outb =>
multiplier_sigs_2_29_port);
mult_125_G3_FS_1_U3_B_0_6_3 : nand2 port map( a =>
mult_125_G3_FS_1_G_n_int_0_6_3_port, b =>
mult_125_G3_FS_1_P_0_6_3_port, outb => n6012);
mult_125_G3_FS_1_U2_0_6_3 : nand2 port map( a => mult_125_G3_A1_27_port, b
=> mult_125_G3_A2_27_port, outb =>
mult_125_G3_FS_1_G_n_int_0_6_3_port);
mult_125_G3_FS_1_U1_0_6_3 : nand2 port map( a => n6010, b => n6011, outb =>
mult_125_G3_FS_1_P_0_6_3_port);
mult_125_G3_FS_1_U6_0_6_2 : oai12 port map( b => n6008, c => n6009, a =>
mult_125_G3_FS_1_G_n_int_0_6_1_port, outb =>
mult_125_G3_FS_1_C_1_6_2_port);
mult_125_G3_FS_1_U5_0_6_2 : oai12 port map( b => n6007, c => n6016, a =>
mult_125_G3_FS_1_G_n_int_0_6_2_port, outb =>
mult_125_G3_FS_1_TEMP_G_0_6_2_port);
mult_125_G3_FS_1_U4_0_6_2 : nand2 port map( a =>
mult_125_G3_FS_1_TEMP_P_0_6_1_port, b =>
mult_125_G3_FS_1_P_0_6_2_port, outb => n6006);
mult_125_G3_FS_1_U3_C_0_6_2 : xor2 port map( a =>
mult_125_G3_FS_1_PG_int_0_6_2_port, b =>
mult_125_G3_FS_1_C_1_6_2_port, outb =>
multiplier_sigs_2_28_port);
mult_125_G3_FS_1_U3_B_0_6_2 : nand2 port map( a =>
mult_125_G3_FS_1_G_n_int_0_6_2_port, b =>
mult_125_G3_FS_1_P_0_6_2_port, outb => n6005);
mult_125_G3_FS_1_U2_0_6_2 : nand2 port map( a => mult_125_G3_A1_26_port, b
=> mult_125_G3_A2_26_port, outb =>
mult_125_G3_FS_1_G_n_int_0_6_2_port);
mult_125_G3_FS_1_U1_0_6_2 : nand2 port map( a => n6003, b => n6004, outb =>
mult_125_G3_FS_1_P_0_6_2_port);
mult_125_G3_FS_1_U6_0_6_1 : oai12 port map( b => n6032, c => n6002, a =>
mult_125_G3_FS_1_G_n_int_0_6_0_port, outb =>
mult_125_G3_FS_1_C_1_6_1_port);
mult_125_G3_FS_1_U5_0_6_1 : oai12 port map( b =>
mult_125_G3_FS_1_G_n_int_0_6_0_port, c => n6009, a
=> mult_125_G3_FS_1_G_n_int_0_6_1_port, outb =>
mult_125_G3_FS_1_TEMP_G_0_6_1_port);
mult_125_G3_FS_1_U4_0_6_1 : nand2 port map( a =>
mult_125_G3_FS_1_TEMP_P_0_6_0_port, b =>
mult_125_G3_FS_1_P_0_6_1_port, outb => n6001);
mult_125_G3_FS_1_U3_C_0_6_1 : xor2 port map( a =>
mult_125_G3_FS_1_PG_int_0_6_1_port, b =>
mult_125_G3_FS_1_C_1_6_1_port, outb =>
multiplier_sigs_2_27_port);
mult_125_G3_FS_1_U3_B_0_6_1 : nand2 port map( a =>
mult_125_G3_FS_1_G_n_int_0_6_1_port, b =>
mult_125_G3_FS_1_P_0_6_1_port, outb => n6000);
mult_125_G3_FS_1_U2_0_6_1 : nand2 port map( a => mult_125_G3_A1_25_port, b
=> mult_125_G3_A2_25_port, outb =>
mult_125_G3_FS_1_G_n_int_0_6_1_port);
mult_125_G3_FS_1_U1_0_6_1 : nand2 port map( a => n5998, b => n5999, outb =>
mult_125_G3_FS_1_P_0_6_1_port);
mult_125_G3_FS_1_U3_C_0_6_0 : xor2 port map( a =>
mult_125_G3_FS_1_PG_int_0_6_0_port, b =>
mult_125_G3_FS_1_C_1_6_0_port, outb =>
multiplier_sigs_2_26_port);
mult_125_G3_FS_1_U3_B_0_6_0 : nand2 port map( a =>
mult_125_G3_FS_1_G_n_int_0_6_0_port, b =>
mult_125_G3_FS_1_TEMP_P_0_6_0_port, outb => n5997);
mult_125_G3_FS_1_U2_0_6_0 : nand2 port map( a => mult_125_G3_A1_24_port, b
=> mult_125_G3_A2_24_port, outb =>
mult_125_G3_FS_1_G_n_int_0_6_0_port);
mult_125_G3_FS_1_U1_0_6_0 : nand2 port map( a => n5995, b => n5996, outb =>
mult_125_G3_FS_1_TEMP_P_0_6_0_port);
mult_125_G3_FS_1_U6_0_5_3 : oai12 port map( b => n5993, c => n5994, a =>
mult_125_G3_FS_1_G_n_int_0_5_2_port, outb =>
mult_125_G3_FS_1_C_1_5_3_port);
mult_125_G3_FS_1_U5_0_5_3 : oai12 port map( b => n5991, c => n5992, a =>
mult_125_G3_FS_1_G_n_int_0_5_3_port, outb =>
mult_125_G3_FS_1_G_1_1_1_port);
mult_125_G3_FS_1_U4_0_5_3 : nand2 port map( a =>
mult_125_G3_FS_1_TEMP_P_0_5_2_port, b =>
mult_125_G3_FS_1_P_0_5_3_port, outb => n6030);
mult_125_G3_FS_1_U3_C_0_5_3 : xor2 port map( a =>
mult_125_G3_FS_1_PG_int_0_5_3_port, b =>
mult_125_G3_FS_1_C_1_5_3_port, outb =>
multiplier_sigs_2_25_port);
mult_125_G3_FS_1_U3_B_0_5_3 : nand2 port map( a =>
mult_125_G3_FS_1_G_n_int_0_5_3_port, b =>
mult_125_G3_FS_1_P_0_5_3_port, outb => n5990);
mult_125_G3_FS_1_U2_0_5_3 : nand2 port map( a => mult_125_G3_A1_23_port, b
=> mult_125_G3_A2_23_port, outb =>
mult_125_G3_FS_1_G_n_int_0_5_3_port);
mult_125_G3_FS_1_U1_0_5_3 : nand2 port map( a => n5988, b => n5989, outb =>
mult_125_G3_FS_1_P_0_5_3_port);
mult_125_G3_FS_1_U6_0_5_2 : oai12 port map( b => n5986, c => n5987, a =>
mult_125_G3_FS_1_G_n_int_0_5_1_port, outb =>
mult_125_G3_FS_1_C_1_5_2_port);
mult_125_G3_FS_1_U5_0_5_2 : oai12 port map( b => n5985, c => n5994, a =>
mult_125_G3_FS_1_G_n_int_0_5_2_port, outb =>
mult_125_G3_FS_1_TEMP_G_0_5_2_port);
mult_125_G3_FS_1_U4_0_5_2 : nand2 port map( a =>
mult_125_G3_FS_1_TEMP_P_0_5_1_port, b =>
mult_125_G3_FS_1_P_0_5_2_port, outb => n5984);
mult_125_G3_FS_1_U3_C_0_5_2 : xor2 port map( a =>
mult_125_G3_FS_1_PG_int_0_5_2_port, b =>
mult_125_G3_FS_1_C_1_5_2_port, outb =>
multiplier_sigs_2_24_port);
mult_125_G3_FS_1_U3_B_0_5_2 : nand2 port map( a =>
mult_125_G3_FS_1_G_n_int_0_5_2_port, b =>
mult_125_G3_FS_1_P_0_5_2_port, outb => n5983);
mult_125_G3_FS_1_U2_0_5_2 : nand2 port map( a => mult_125_G3_A1_22_port, b
=> mult_125_G3_A2_22_port, outb =>
mult_125_G3_FS_1_G_n_int_0_5_2_port);
mult_125_G3_FS_1_U1_0_5_2 : nand2 port map( a => n5981, b => n5982, outb =>
mult_125_G3_FS_1_P_0_5_2_port);
mult_125_G3_FS_1_U6_0_5_1 : oai12 port map( b => n6029, c => n5980, a =>
mult_125_G3_FS_1_G_n_int_0_5_0_port, outb =>
mult_125_G3_FS_1_C_1_5_1_port);
mult_125_G3_FS_1_U5_0_5_1 : oai12 port map( b =>
mult_125_G3_FS_1_G_n_int_0_5_0_port, c => n5987, a
=> mult_125_G3_FS_1_G_n_int_0_5_1_port, outb =>
mult_125_G3_FS_1_TEMP_G_0_5_1_port);
mult_125_G3_FS_1_U4_0_5_1 : nand2 port map( a =>
mult_125_G3_FS_1_TEMP_P_0_5_0_port, b =>
mult_125_G3_FS_1_P_0_5_1_port, outb => n5979);
mult_125_G3_FS_1_U3_C_0_5_1 : xor2 port map( a =>
mult_125_G3_FS_1_PG_int_0_5_1_port, b =>
mult_125_G3_FS_1_C_1_5_1_port, outb =>
multiplier_sigs_2_23_port);
mult_125_G3_FS_1_U3_B_0_5_1 : nand2 port map( a =>
mult_125_G3_FS_1_G_n_int_0_5_1_port, b =>
mult_125_G3_FS_1_P_0_5_1_port, outb => n5978);
mult_125_G3_FS_1_U2_0_5_1 : nand2 port map( a => mult_125_G3_A1_21_port, b
=> mult_125_G3_A2_21_port, outb =>
mult_125_G3_FS_1_G_n_int_0_5_1_port);
mult_125_G3_FS_1_U1_0_5_1 : nand2 port map( a => n5976, b => n5977, outb =>
mult_125_G3_FS_1_P_0_5_1_port);
mult_125_G3_FS_1_U3_C_0_5_0 : xor2 port map( a =>
mult_125_G3_FS_1_PG_int_0_5_0_port, b =>
mult_125_G3_FS_1_C_1_5_0_port, outb =>
multiplier_sigs_2_22_port);
mult_125_G3_FS_1_U3_B_0_5_0 : nand2 port map( a =>
mult_125_G3_FS_1_G_n_int_0_5_0_port, b =>
mult_125_G3_FS_1_TEMP_P_0_5_0_port, outb => n5975);
mult_125_G3_FS_1_U2_0_5_0 : nand2 port map( a => mult_125_G3_A1_20_port, b
=> mult_125_G3_A2_20_port, outb =>
mult_125_G3_FS_1_G_n_int_0_5_0_port);
mult_125_G3_FS_1_U1_0_5_0 : nand2 port map( a => n5973, b => n5974, outb =>
mult_125_G3_FS_1_TEMP_P_0_5_0_port);
mult_125_G3_FS_1_U6_0_4_3 : oai12 port map( b => n5971, c => n5972, a =>
mult_125_G3_FS_1_G_n_int_0_4_2_port, outb =>
mult_125_G3_FS_1_C_1_4_3_port);
mult_125_G3_FS_1_U5_0_4_3 : oai12 port map( b => n5969, c => n5970, a =>
mult_125_G3_FS_1_G_n_int_0_4_3_port, outb =>
mult_125_G3_FS_1_G_1_1_0_port);
mult_125_G3_FS_1_U4_0_4_3 : nand2 port map( a =>
mult_125_G3_FS_1_TEMP_P_0_4_2_port, b =>
mult_125_G3_FS_1_P_0_4_3_port, outb => n6027);
mult_125_G3_FS_1_U3_C_0_4_3 : xor2 port map( a =>
mult_125_G3_FS_1_PG_int_0_4_3_port, b =>
mult_125_G3_FS_1_C_1_4_3_port, outb =>
multiplier_sigs_2_21_port);
mult_125_G3_FS_1_U3_B_0_4_3 : nand2 port map( a =>
mult_125_G3_FS_1_G_n_int_0_4_3_port, b =>
mult_125_G3_FS_1_P_0_4_3_port, outb => n5968);
mult_125_G3_FS_1_U2_0_4_3 : nand2 port map( a => mult_125_G3_A1_19_port, b
=> mult_125_G3_A2_19_port, outb =>
mult_125_G3_FS_1_G_n_int_0_4_3_port);
mult_125_G3_FS_1_U1_0_4_3 : nand2 port map( a => n5966, b => n5967, outb =>
mult_125_G3_FS_1_P_0_4_3_port);
mult_125_G3_FS_1_U6_0_4_2 : oai12 port map( b => n5964, c => n5965, a =>
mult_125_G3_FS_1_G_n_int_0_4_1_port, outb =>
mult_125_G3_FS_1_C_1_4_2_port);
mult_125_G3_FS_1_U5_0_4_2 : oai12 port map( b => n5963, c => n5972, a =>
mult_125_G3_FS_1_G_n_int_0_4_2_port, outb =>
mult_125_G3_FS_1_TEMP_G_0_4_2_port);
mult_125_G3_FS_1_U4_0_4_2 : nand2 port map( a =>
mult_125_G3_FS_1_TEMP_P_0_4_1_port, b =>
mult_125_G3_FS_1_P_0_4_2_port, outb => n5962);
mult_125_G3_FS_1_U3_C_0_4_2 : xor2 port map( a =>
mult_125_G3_FS_1_PG_int_0_4_2_port, b =>
mult_125_G3_FS_1_C_1_4_2_port, outb =>
multiplier_sigs_2_20_port);
mult_125_G3_FS_1_U3_B_0_4_2 : nand2 port map( a =>
mult_125_G3_FS_1_G_n_int_0_4_2_port, b =>
mult_125_G3_FS_1_P_0_4_2_port, outb => n5961);
mult_125_G3_FS_1_U2_0_4_2 : nand2 port map( a => mult_125_G3_A1_18_port, b
=> mult_125_G3_A2_18_port, outb =>
mult_125_G3_FS_1_G_n_int_0_4_2_port);
mult_125_G3_FS_1_U1_0_4_2 : nand2 port map( a => n5959, b => n5960, outb =>
mult_125_G3_FS_1_P_0_4_2_port);
mult_125_G3_FS_1_U6_0_4_1 : oai12 port map( b => n6026, c => n5958, a =>
mult_125_G3_FS_1_G_n_int_0_4_0_port, outb =>
mult_125_G3_FS_1_C_1_4_1_port);
mult_125_G3_FS_1_U5_0_4_1 : oai12 port map( b =>
mult_125_G3_FS_1_G_n_int_0_4_0_port, c => n5965, a
=> mult_125_G3_FS_1_G_n_int_0_4_1_port, outb =>
mult_125_G3_FS_1_TEMP_G_0_4_1_port);
mult_125_G3_FS_1_U4_0_4_1 : nand2 port map( a =>
mult_125_G3_FS_1_TEMP_P_0_4_0_port, b =>
mult_125_G3_FS_1_P_0_4_1_port, outb => n5957);
mult_125_G3_FS_1_U3_C_0_4_1 : xor2 port map( a =>
mult_125_G3_FS_1_PG_int_0_4_1_port, b =>
mult_125_G3_FS_1_C_1_4_1_port, outb =>
multiplier_sigs_2_19_port);
mult_125_G3_FS_1_U3_B_0_4_1 : nand2 port map( a =>
mult_125_G3_FS_1_G_n_int_0_4_1_port, b =>
mult_125_G3_FS_1_P_0_4_1_port, outb => n5956);
mult_125_G3_FS_1_U2_0_4_1 : nand2 port map( a => mult_125_G3_A1_17_port, b
=> mult_125_G3_A2_17_port, outb =>
mult_125_G3_FS_1_G_n_int_0_4_1_port);
mult_125_G3_FS_1_U1_0_4_1 : nand2 port map( a => n5954, b => n5955, outb =>
mult_125_G3_FS_1_P_0_4_1_port);
mult_125_G3_FS_1_U3_C_0_4_0 : xor2 port map( a =>
mult_125_G3_FS_1_PG_int_0_4_0_port, b =>
mult_125_G3_FS_1_C_1_4_0_port, outb =>
multiplier_sigs_2_18_port);
mult_125_G3_FS_1_U3_B_0_4_0 : nand2 port map( a =>
mult_125_G3_FS_1_G_n_int_0_4_0_port, b =>
mult_125_G3_FS_1_TEMP_P_0_4_0_port, outb => n5953);
mult_125_G3_FS_1_U2_0_4_0 : nand2 port map( a => mult_125_G3_A1_16_port, b
=> mult_125_G3_A2_16_port, outb =>
mult_125_G3_FS_1_G_n_int_0_4_0_port);
mult_125_G3_FS_1_U1_0_4_0 : nand2 port map( a => n5951, b => n5952, outb =>
mult_125_G3_FS_1_TEMP_P_0_4_0_port);
mult_125_G3_FS_1_U5_0_3_3 : oai12 port map( b => n5949, c => n5950, a =>
mult_125_G3_FS_1_G_n_int_0_3_3_port, outb =>
mult_125_G3_FS_1_G_1_0_3_port);
mult_125_G3_FS_1_U3_C_0_3_3 : xor2 port map( a =>
mult_125_G3_FS_1_PG_int_0_3_3_port, b =>
mult_125_G3_FS_1_C_1_3_3_port, outb =>
multiplier_sigs_2_17_port);
mult_125_G3_FS_1_U3_B_0_3_3 : nand2 port map( a =>
mult_125_G3_FS_1_G_n_int_0_3_3_port, b =>
mult_125_G3_FS_1_P_0_3_3_port, outb => n5948);
mult_125_G3_FS_1_U2_0_3_3 : nand2 port map( a => mult_125_G3_A1_15_port, b
=> mult_125_G3_A2_15_port, outb =>
mult_125_G3_FS_1_G_n_int_0_3_3_port);
mult_125_G3_FS_1_U1_0_3_3 : nand2 port map( a => n5946, b => n5947, outb =>
mult_125_G3_FS_1_P_0_3_3_port);
mult_125_G3_FS_1_U3_B_0_3_2 : nand2 port map( a =>
mult_125_G3_FS_1_G_n_int_0_3_2_port, b =>
mult_125_G3_FS_1_P_0_3_2_port, outb => n5945);
mult_125_G3_FS_1_U2_0_3_2 : nand2 port map( a => mult_125_G3_A1_14_port, b
=> mult_125_G3_A2_14_port, outb =>
mult_125_G3_FS_1_G_n_int_0_3_2_port);
mult_125_G3_FS_1_U1_0_3_2 : nand2 port map( a => n5943, b => n5944, outb =>
mult_125_G3_FS_1_P_0_3_2_port);
mult_125_G3_AN1_15 : inv port map( inb => coefficient_mem_array_2_15_port,
outb => mult_125_G3_A_not_15_port);
mult_125_G3_AN1_14 : inv port map( inb => coefficient_mem_array_2_14_port,
outb => mult_125_G3_A_not_14_port);
mult_125_G3_AN1_13 : inv port map( inb => coefficient_mem_array_2_13_port,
outb => mult_125_G3_A_not_13_port);
mult_125_G3_AN1_12 : inv port map( inb => coefficient_mem_array_2_12_port,
outb => mult_125_G3_A_not_12_port);
mult_125_G3_AN1_11 : inv port map( inb => coefficient_mem_array_2_11_port,
outb => mult_125_G3_A_not_11_port);
mult_125_G3_AN1_10 : inv port map( inb => coefficient_mem_array_2_10_port,
outb => mult_125_G3_A_not_10_port);
mult_125_G3_AN1_9 : inv port map( inb => coefficient_mem_array_2_9_port,
outb => mult_125_G3_A_not_9_port);
mult_125_G3_AN1_8 : inv port map( inb => coefficient_mem_array_2_8_port,
outb => mult_125_G3_A_not_8_port);
mult_125_G3_AN1_7 : inv port map( inb => coefficient_mem_array_2_7_port,
outb => mult_125_G3_A_not_7_port);
mult_125_G3_AN1_6 : inv port map( inb => coefficient_mem_array_2_6_port,
outb => mult_125_G3_A_not_6_port);
mult_125_G3_AN1_5 : inv port map( inb => coefficient_mem_array_2_5_port,
outb => mult_125_G3_A_not_5_port);
mult_125_G3_AN1_4 : inv port map( inb => coefficient_mem_array_2_4_port,
outb => mult_125_G3_A_not_4_port);
mult_125_G3_AN1_3 : inv port map( inb => coefficient_mem_array_2_3_port,
outb => mult_125_G3_A_not_3_port);
mult_125_G3_AN1_2 : inv port map( inb => coefficient_mem_array_2_2_port,
outb => mult_125_G3_A_not_2_port);
mult_125_G3_AN1_1 : inv port map( inb => coefficient_mem_array_2_1_port,
outb => mult_125_G3_A_not_1_port);
mult_125_G3_AN1_0 : inv port map( inb => coefficient_mem_array_2_0_port,
outb => mult_125_G3_A_not_0_port);
mult_125_G3_AN1_15_0 : inv port map( inb => input_sample_mem_15_port, outb
=> mult_125_G3_B_not_15_port);
mult_125_G3_AN1_14_0 : inv port map( inb => input_sample_mem_14_port, outb
=> mult_125_G3_B_not_14_port);
mult_125_G3_AN1_13_0 : inv port map( inb => input_sample_mem_13_port, outb
=> mult_125_G3_B_not_13_port);
mult_125_G3_AN1_12_0 : inv port map( inb => input_sample_mem_12_port, outb
=> mult_125_G3_B_not_12_port);
mult_125_G3_AN1_11_0 : inv port map( inb => input_sample_mem_11_port, outb
=> mult_125_G3_B_not_11_port);
mult_125_G3_AN1_10_0 : inv port map( inb => input_sample_mem_10_port, outb
=> mult_125_G3_B_not_10_port);
mult_125_G3_AN1_9_0 : inv port map( inb => input_sample_mem_9_port, outb =>
mult_125_G3_B_not_9_port);
mult_125_G3_AN1_8_0 : inv port map( inb => input_sample_mem_8_port, outb =>
mult_125_G3_B_not_8_port);
mult_125_G3_AN1_7_0 : inv port map( inb => input_sample_mem_7_port, outb =>
mult_125_G3_B_not_7_port);
mult_125_G3_AN1_6_0 : inv port map( inb => input_sample_mem_6_port, outb =>
mult_125_G3_B_not_6_port);
mult_125_G3_AN1_5_0 : inv port map( inb => input_sample_mem_5_port, outb =>
mult_125_G3_B_not_5_port);
mult_125_G3_AN1_4_0 : inv port map( inb => input_sample_mem_4_port, outb =>
mult_125_G3_B_not_4_port);
mult_125_G3_AN1_3_0 : inv port map( inb => input_sample_mem_3_port, outb =>
mult_125_G3_B_not_3_port);
mult_125_G3_AN1_2_0 : inv port map( inb => input_sample_mem_2_port, outb =>
mult_125_G3_B_not_2_port);
mult_125_G3_AN1_1_0 : inv port map( inb => input_sample_mem_1_port, outb =>
mult_125_G3_B_not_1_port);
mult_125_G3_AN1_0_0 : inv port map( inb => input_sample_mem_0_port, outb =>
mult_125_G3_B_not_0_port);
mult_125_G3_AN1_15_15 : nor2 port map( a => mult_125_G3_A_not_15_port, b =>
mult_125_G3_B_not_15_port, outb =>
mult_125_G3_ab_15_15_port);
mult_125_G3_AN3_15_14 : nor2 port map( a => mult_125_G3_A_not_15_port, b =>
mult_125_G3_B_notx_14_port, outb =>
mult_125_G3_ab_15_14_port);
mult_125_G3_AN3_15_13 : nor2 port map( a => mult_125_G3_A_not_15_port, b =>
mult_125_G3_B_notx_13_port, outb =>
mult_125_G3_ab_15_13_port);
mult_125_G3_AN3_15_12 : nor2 port map( a => mult_125_G3_A_not_15_port, b =>
mult_125_G3_B_notx_12_port, outb =>
mult_125_G3_ab_15_12_port);
mult_125_G3_AN3_15_11 : nor2 port map( a => mult_125_G3_A_not_15_port, b =>
mult_125_G3_B_notx_11_port, outb =>
mult_125_G3_ab_15_11_port);
mult_125_G3_AN3_15_10 : nor2 port map( a => mult_125_G3_A_not_15_port, b =>
mult_125_G3_B_notx_10_port, outb =>
mult_125_G3_ab_15_10_port);
mult_125_G3_AN3_15_9 : nor2 port map( a => mult_125_G3_A_not_15_port, b =>
mult_125_G3_B_notx_9_port, outb =>
mult_125_G3_ab_15_9_port);
mult_125_G3_AN3_15_8 : nor2 port map( a => mult_125_G3_A_not_15_port, b =>
mult_125_G3_B_notx_8_port, outb =>
mult_125_G3_ab_15_8_port);
mult_125_G3_AN3_15_7 : nor2 port map( a => mult_125_G3_A_not_15_port, b =>
mult_125_G3_B_notx_7_port, outb =>
mult_125_G3_ab_15_7_port);
mult_125_G3_AN3_15_6 : nor2 port map( a => mult_125_G3_A_not_15_port, b =>
mult_125_G3_B_notx_6_port, outb =>
mult_125_G3_ab_15_6_port);
mult_125_G3_AN3_15_5 : nor2 port map( a => mult_125_G3_A_not_15_port, b =>
mult_125_G3_B_notx_5_port, outb =>
mult_125_G3_ab_15_5_port);
mult_125_G3_AN3_15_4 : nor2 port map( a => mult_125_G3_A_not_15_port, b =>
mult_125_G3_B_notx_4_port, outb =>
mult_125_G3_ab_15_4_port);
mult_125_G3_AN3_15_3 : nor2 port map( a => mult_125_G3_A_not_15_port, b =>
mult_125_G3_B_notx_3_port, outb =>
mult_125_G3_ab_15_3_port);
mult_125_G3_AN3_15_2 : nor2 port map( a => mult_125_G3_A_not_15_port, b =>
mult_125_G3_B_notx_2_port, outb =>
mult_125_G3_ab_15_2_port);
mult_125_G3_AN3_15_1 : nor2 port map( a => mult_125_G3_A_not_15_port, b =>
mult_125_G3_B_notx_1_port, outb =>
mult_125_G3_ab_15_1_port);
mult_125_G3_AN3_15_0 : nor2 port map( a => mult_125_G3_A_not_15_port, b =>
mult_125_G3_B_notx_0_port, outb =>
mult_125_G3_ab_15_0_port);
mult_125_G3_AN2_14_15 : nor2 port map( a => mult_125_G3_A_notx_14_port, b =>
mult_125_G3_B_not_15_port, outb =>
mult_125_G3_ab_14_15_port);
mult_125_G3_AN1_14_14 : nor2 port map( a => mult_125_G3_A_not_14_port, b =>
mult_125_G3_B_not_14_port, outb =>
mult_125_G3_ab_14_14_port);
mult_125_G3_AN1_14_13 : nor2 port map( a => mult_125_G3_A_not_14_port, b =>
mult_125_G3_B_not_13_port, outb =>
mult_125_G3_ab_14_13_port);
mult_125_G3_AN1_14_12 : nor2 port map( a => mult_125_G3_A_not_14_port, b =>
mult_125_G3_B_not_12_port, outb =>
mult_125_G3_ab_14_12_port);
mult_125_G3_AN1_14_11 : nor2 port map( a => mult_125_G3_A_not_14_port, b =>
mult_125_G3_B_not_11_port, outb =>
mult_125_G3_ab_14_11_port);
mult_125_G3_AN1_14_10 : nor2 port map( a => mult_125_G3_A_not_14_port, b =>
mult_125_G3_B_not_10_port, outb =>
mult_125_G3_ab_14_10_port);
mult_125_G3_AN1_14_9 : nor2 port map( a => mult_125_G3_A_not_14_port, b =>
mult_125_G3_B_not_9_port, outb =>
mult_125_G3_ab_14_9_port);
mult_125_G3_AN1_14_8 : nor2 port map( a => mult_125_G3_A_not_14_port, b =>
mult_125_G3_B_not_8_port, outb =>
mult_125_G3_ab_14_8_port);
mult_125_G3_AN1_14_7 : nor2 port map( a => mult_125_G3_A_not_14_port, b =>
mult_125_G3_B_not_7_port, outb =>
mult_125_G3_ab_14_7_port);
mult_125_G3_AN1_14_6 : nor2 port map( a => mult_125_G3_A_not_14_port, b =>
mult_125_G3_B_not_6_port, outb =>
mult_125_G3_ab_14_6_port);
mult_125_G3_AN1_14_5 : nor2 port map( a => mult_125_G3_A_not_14_port, b =>
mult_125_G3_B_not_5_port, outb =>
mult_125_G3_ab_14_5_port);
mult_125_G3_AN1_14_4 : nor2 port map( a => mult_125_G3_A_not_14_port, b =>
mult_125_G3_B_not_4_port, outb =>
mult_125_G3_ab_14_4_port);
mult_125_G3_AN1_14_3 : nor2 port map( a => mult_125_G3_A_not_14_port, b =>
mult_125_G3_B_not_3_port, outb =>
mult_125_G3_ab_14_3_port);
mult_125_G3_AN1_14_2 : nor2 port map( a => mult_125_G3_A_not_14_port, b =>
mult_125_G3_B_not_2_port, outb =>
mult_125_G3_ab_14_2_port);
mult_125_G3_AN1_14_1 : nor2 port map( a => mult_125_G3_A_not_14_port, b =>
mult_125_G3_B_not_1_port, outb =>
mult_125_G3_ab_14_1_port);
mult_125_G3_AN1_14_0_0 : nor2 port map( a => mult_125_G3_A_not_14_port, b =>
mult_125_G3_B_not_0_port, outb =>
mult_125_G3_ab_14_0_port);
mult_125_G3_AN2_13_15 : nor2 port map( a => mult_125_G3_A_notx_13_port, b =>
mult_125_G3_B_not_15_port, outb =>
mult_125_G3_ab_13_15_port);
mult_125_G3_AN1_13_14 : nor2 port map( a => mult_125_G3_A_not_13_port, b =>
mult_125_G3_B_not_14_port, outb =>
mult_125_G3_ab_13_14_port);
mult_125_G3_AN1_13_13 : nor2 port map( a => mult_125_G3_A_not_13_port, b =>
mult_125_G3_B_not_13_port, outb =>
mult_125_G3_ab_13_13_port);
mult_125_G3_AN1_13_12 : nor2 port map( a => mult_125_G3_A_not_13_port, b =>
mult_125_G3_B_not_12_port, outb =>
mult_125_G3_ab_13_12_port);
mult_125_G3_AN1_13_11 : nor2 port map( a => mult_125_G3_A_not_13_port, b =>
mult_125_G3_B_not_11_port, outb =>
mult_125_G3_ab_13_11_port);
mult_125_G3_AN1_13_10 : nor2 port map( a => mult_125_G3_A_not_13_port, b =>
mult_125_G3_B_not_10_port, outb =>
mult_125_G3_ab_13_10_port);
mult_125_G3_AN1_13_9 : nor2 port map( a => mult_125_G3_A_not_13_port, b =>
mult_125_G3_B_not_9_port, outb =>
mult_125_G3_ab_13_9_port);
mult_125_G3_AN1_13_8 : nor2 port map( a => mult_125_G3_A_not_13_port, b =>
mult_125_G3_B_not_8_port, outb =>
mult_125_G3_ab_13_8_port);
mult_125_G3_AN1_13_7 : nor2 port map( a => mult_125_G3_A_not_13_port, b =>
mult_125_G3_B_not_7_port, outb =>
mult_125_G3_ab_13_7_port);
mult_125_G3_AN1_13_6 : nor2 port map( a => mult_125_G3_A_not_13_port, b =>
mult_125_G3_B_not_6_port, outb =>
mult_125_G3_ab_13_6_port);
mult_125_G3_AN1_13_5 : nor2 port map( a => mult_125_G3_A_not_13_port, b =>
mult_125_G3_B_not_5_port, outb =>
mult_125_G3_ab_13_5_port);
mult_125_G3_AN1_13_4 : nor2 port map( a => mult_125_G3_A_not_13_port, b =>
mult_125_G3_B_not_4_port, outb =>
mult_125_G3_ab_13_4_port);
mult_125_G3_AN1_13_3 : nor2 port map( a => mult_125_G3_A_not_13_port, b =>
mult_125_G3_B_not_3_port, outb =>
mult_125_G3_ab_13_3_port);
mult_125_G3_AN1_13_2 : nor2 port map( a => mult_125_G3_A_not_13_port, b =>
mult_125_G3_B_not_2_port, outb =>
mult_125_G3_ab_13_2_port);
mult_125_G3_AN1_13_1 : nor2 port map( a => mult_125_G3_A_not_13_port, b =>
mult_125_G3_B_not_1_port, outb =>
mult_125_G3_ab_13_1_port);
mult_125_G3_AN1_13_0_0 : nor2 port map( a => mult_125_G3_A_not_13_port, b =>
mult_125_G3_B_not_0_port, outb =>
mult_125_G3_ab_13_0_port);
mult_125_G3_AN2_12_15 : nor2 port map( a => mult_125_G3_A_notx_12_port, b =>
mult_125_G3_B_not_15_port, outb =>
mult_125_G3_ab_12_15_port);
mult_125_G3_AN1_12_14 : nor2 port map( a => mult_125_G3_A_not_12_port, b =>
mult_125_G3_B_not_14_port, outb =>
mult_125_G3_ab_12_14_port);
mult_125_G3_AN1_12_13 : nor2 port map( a => mult_125_G3_A_not_12_port, b =>
mult_125_G3_B_not_13_port, outb =>
mult_125_G3_ab_12_13_port);
mult_125_G3_AN1_12_12 : nor2 port map( a => mult_125_G3_A_not_12_port, b =>
mult_125_G3_B_not_12_port, outb =>
mult_125_G3_ab_12_12_port);
mult_125_G3_AN1_12_11 : nor2 port map( a => mult_125_G3_A_not_12_port, b =>
mult_125_G3_B_not_11_port, outb =>
mult_125_G3_ab_12_11_port);
mult_125_G3_AN1_12_10 : nor2 port map( a => mult_125_G3_A_not_12_port, b =>
mult_125_G3_B_not_10_port, outb =>
mult_125_G3_ab_12_10_port);
mult_125_G3_AN1_12_9 : nor2 port map( a => mult_125_G3_A_not_12_port, b =>
mult_125_G3_B_not_9_port, outb =>
mult_125_G3_ab_12_9_port);
mult_125_G3_AN1_12_8 : nor2 port map( a => mult_125_G3_A_not_12_port, b =>
mult_125_G3_B_not_8_port, outb =>
mult_125_G3_ab_12_8_port);
mult_125_G3_AN1_12_7 : nor2 port map( a => mult_125_G3_A_not_12_port, b =>
mult_125_G3_B_not_7_port, outb =>
mult_125_G3_ab_12_7_port);
mult_125_G3_AN1_12_6 : nor2 port map( a => mult_125_G3_A_not_12_port, b =>
mult_125_G3_B_not_6_port, outb =>
mult_125_G3_ab_12_6_port);
mult_125_G3_AN1_12_5 : nor2 port map( a => mult_125_G3_A_not_12_port, b =>
mult_125_G3_B_not_5_port, outb =>
mult_125_G3_ab_12_5_port);
mult_125_G3_AN1_12_4 : nor2 port map( a => mult_125_G3_A_not_12_port, b =>
mult_125_G3_B_not_4_port, outb =>
mult_125_G3_ab_12_4_port);
mult_125_G3_AN1_12_3 : nor2 port map( a => mult_125_G3_A_not_12_port, b =>
mult_125_G3_B_not_3_port, outb =>
mult_125_G3_ab_12_3_port);
mult_125_G3_AN1_12_2 : nor2 port map( a => mult_125_G3_A_not_12_port, b =>
mult_125_G3_B_not_2_port, outb =>
mult_125_G3_ab_12_2_port);
mult_125_G3_AN1_12_1 : nor2 port map( a => mult_125_G3_A_not_12_port, b =>
mult_125_G3_B_not_1_port, outb =>
mult_125_G3_ab_12_1_port);
mult_125_G3_AN1_12_0_0 : nor2 port map( a => mult_125_G3_A_not_12_port, b =>
mult_125_G3_B_not_0_port, outb =>
mult_125_G3_ab_12_0_port);
mult_125_G3_AN2_11_15 : nor2 port map( a => mult_125_G3_A_notx_11_port, b =>
mult_125_G3_B_not_15_port, outb =>
mult_125_G3_ab_11_15_port);
mult_125_G3_AN1_11_14 : nor2 port map( a => mult_125_G3_A_not_11_port, b =>
mult_125_G3_B_not_14_port, outb =>
mult_125_G3_ab_11_14_port);
mult_125_G3_AN1_11_13 : nor2 port map( a => mult_125_G3_A_not_11_port, b =>
mult_125_G3_B_not_13_port, outb =>
mult_125_G3_ab_11_13_port);
mult_125_G3_AN1_11_12 : nor2 port map( a => mult_125_G3_A_not_11_port, b =>
mult_125_G3_B_not_12_port, outb =>
mult_125_G3_ab_11_12_port);
mult_125_G3_AN1_11_11 : nor2 port map( a => mult_125_G3_A_not_11_port, b =>
mult_125_G3_B_not_11_port, outb =>
mult_125_G3_ab_11_11_port);
mult_125_G3_AN1_11_10 : nor2 port map( a => mult_125_G3_A_not_11_port, b =>
mult_125_G3_B_not_10_port, outb =>
mult_125_G3_ab_11_10_port);
mult_125_G3_AN1_11_9 : nor2 port map( a => mult_125_G3_A_not_11_port, b =>
mult_125_G3_B_not_9_port, outb =>
mult_125_G3_ab_11_9_port);
mult_125_G3_AN1_11_8 : nor2 port map( a => mult_125_G3_A_not_11_port, b =>
mult_125_G3_B_not_8_port, outb =>
mult_125_G3_ab_11_8_port);
mult_125_G3_AN1_11_7 : nor2 port map( a => mult_125_G3_A_not_11_port, b =>
mult_125_G3_B_not_7_port, outb =>
mult_125_G3_ab_11_7_port);
mult_125_G3_AN1_11_6 : nor2 port map( a => mult_125_G3_A_not_11_port, b =>
mult_125_G3_B_not_6_port, outb =>
mult_125_G3_ab_11_6_port);
mult_125_G3_AN1_11_5 : nor2 port map( a => mult_125_G3_A_not_11_port, b =>
mult_125_G3_B_not_5_port, outb =>
mult_125_G3_ab_11_5_port);
mult_125_G3_AN1_11_4 : nor2 port map( a => mult_125_G3_A_not_11_port, b =>
mult_125_G3_B_not_4_port, outb =>
mult_125_G3_ab_11_4_port);
mult_125_G3_AN1_11_3 : nor2 port map( a => mult_125_G3_A_not_11_port, b =>
mult_125_G3_B_not_3_port, outb =>
mult_125_G3_ab_11_3_port);
mult_125_G3_AN1_11_2 : nor2 port map( a => mult_125_G3_A_not_11_port, b =>
mult_125_G3_B_not_2_port, outb =>
mult_125_G3_ab_11_2_port);
mult_125_G3_AN1_11_1 : nor2 port map( a => mult_125_G3_A_not_11_port, b =>
mult_125_G3_B_not_1_port, outb =>
mult_125_G3_ab_11_1_port);
mult_125_G3_AN1_11_0_0 : nor2 port map( a => mult_125_G3_A_not_11_port, b =>
mult_125_G3_B_not_0_port, outb =>
mult_125_G3_ab_11_0_port);
mult_125_G3_AN2_10_15 : nor2 port map( a => mult_125_G3_A_notx_10_port, b =>
mult_125_G3_B_not_15_port, outb =>
mult_125_G3_ab_10_15_port);
mult_125_G3_AN1_10_14 : nor2 port map( a => mult_125_G3_A_not_10_port, b =>
mult_125_G3_B_not_14_port, outb =>
mult_125_G3_ab_10_14_port);
mult_125_G3_AN1_10_13 : nor2 port map( a => mult_125_G3_A_not_10_port, b =>
mult_125_G3_B_not_13_port, outb =>
mult_125_G3_ab_10_13_port);
mult_125_G3_AN1_10_12 : nor2 port map( a => mult_125_G3_A_not_10_port, b =>
mult_125_G3_B_not_12_port, outb =>
mult_125_G3_ab_10_12_port);
mult_125_G3_AN1_10_11 : nor2 port map( a => mult_125_G3_A_not_10_port, b =>
mult_125_G3_B_not_11_port, outb =>
mult_125_G3_ab_10_11_port);
mult_125_G3_AN1_10_10 : nor2 port map( a => mult_125_G3_A_not_10_port, b =>
mult_125_G3_B_not_10_port, outb =>
mult_125_G3_ab_10_10_port);
mult_125_G3_AN1_10_9 : nor2 port map( a => mult_125_G3_A_not_10_port, b =>
mult_125_G3_B_not_9_port, outb =>
mult_125_G3_ab_10_9_port);
mult_125_G3_AN1_10_8 : nor2 port map( a => mult_125_G3_A_not_10_port, b =>
mult_125_G3_B_not_8_port, outb =>
mult_125_G3_ab_10_8_port);
mult_125_G3_AN1_10_7 : nor2 port map( a => mult_125_G3_A_not_10_port, b =>
mult_125_G3_B_not_7_port, outb =>
mult_125_G3_ab_10_7_port);
mult_125_G3_AN1_10_6 : nor2 port map( a => mult_125_G3_A_not_10_port, b =>
mult_125_G3_B_not_6_port, outb =>
mult_125_G3_ab_10_6_port);
mult_125_G3_AN1_10_5 : nor2 port map( a => mult_125_G3_A_not_10_port, b =>
mult_125_G3_B_not_5_port, outb =>
mult_125_G3_ab_10_5_port);
mult_125_G3_AN1_10_4 : nor2 port map( a => mult_125_G3_A_not_10_port, b =>
mult_125_G3_B_not_4_port, outb =>
mult_125_G3_ab_10_4_port);
mult_125_G3_AN1_10_3 : nor2 port map( a => mult_125_G3_A_not_10_port, b =>
mult_125_G3_B_not_3_port, outb =>
mult_125_G3_ab_10_3_port);
mult_125_G3_AN1_10_2 : nor2 port map( a => mult_125_G3_A_not_10_port, b =>
mult_125_G3_B_not_2_port, outb =>
mult_125_G3_ab_10_2_port);
mult_125_G3_AN1_10_1 : nor2 port map( a => mult_125_G3_A_not_10_port, b =>
mult_125_G3_B_not_1_port, outb =>
mult_125_G3_ab_10_1_port);
mult_125_G3_AN1_10_0_0 : nor2 port map( a => mult_125_G3_A_not_10_port, b =>
mult_125_G3_B_not_0_port, outb =>
mult_125_G3_ab_10_0_port);
mult_125_G3_AN2_9_15 : nor2 port map( a => mult_125_G3_A_notx_9_port, b =>
mult_125_G3_B_not_15_port, outb =>
mult_125_G3_ab_9_15_port);
mult_125_G3_AN1_9_14 : nor2 port map( a => mult_125_G3_A_not_9_port, b =>
mult_125_G3_B_not_14_port, outb =>
mult_125_G3_ab_9_14_port);
mult_125_G3_AN1_9_13 : nor2 port map( a => mult_125_G3_A_not_9_port, b =>
mult_125_G3_B_not_13_port, outb =>
mult_125_G3_ab_9_13_port);
mult_125_G3_AN1_9_12 : nor2 port map( a => mult_125_G3_A_not_9_port, b =>
mult_125_G3_B_not_12_port, outb =>
mult_125_G3_ab_9_12_port);
mult_125_G3_AN1_9_11 : nor2 port map( a => mult_125_G3_A_not_9_port, b =>
mult_125_G3_B_not_11_port, outb =>
mult_125_G3_ab_9_11_port);
mult_125_G3_AN1_9_10 : nor2 port map( a => mult_125_G3_A_not_9_port, b =>
mult_125_G3_B_not_10_port, outb =>
mult_125_G3_ab_9_10_port);
mult_125_G3_AN1_9_9 : nor2 port map( a => mult_125_G3_A_not_9_port, b =>
mult_125_G3_B_not_9_port, outb =>
mult_125_G3_ab_9_9_port);
mult_125_G3_AN1_9_8 : nor2 port map( a => mult_125_G3_A_not_9_port, b =>
mult_125_G3_B_not_8_port, outb =>
mult_125_G3_ab_9_8_port);
mult_125_G3_AN1_9_7 : nor2 port map( a => mult_125_G3_A_not_9_port, b =>
mult_125_G3_B_not_7_port, outb =>
mult_125_G3_ab_9_7_port);
mult_125_G3_AN1_9_6 : nor2 port map( a => mult_125_G3_A_not_9_port, b =>
mult_125_G3_B_not_6_port, outb =>
mult_125_G3_ab_9_6_port);
mult_125_G3_AN1_9_5 : nor2 port map( a => mult_125_G3_A_not_9_port, b =>
mult_125_G3_B_not_5_port, outb =>
mult_125_G3_ab_9_5_port);
mult_125_G3_AN1_9_4 : nor2 port map( a => mult_125_G3_A_not_9_port, b =>
mult_125_G3_B_not_4_port, outb =>
mult_125_G3_ab_9_4_port);
mult_125_G3_AN1_9_3 : nor2 port map( a => mult_125_G3_A_not_9_port, b =>
mult_125_G3_B_not_3_port, outb =>
mult_125_G3_ab_9_3_port);
mult_125_G3_AN1_9_2 : nor2 port map( a => mult_125_G3_A_not_9_port, b =>
mult_125_G3_B_not_2_port, outb =>
mult_125_G3_ab_9_2_port);
mult_125_G3_AN1_9_1 : nor2 port map( a => mult_125_G3_A_not_9_port, b =>
mult_125_G3_B_not_1_port, outb =>
mult_125_G3_ab_9_1_port);
mult_125_G3_AN1_9_0_0 : nor2 port map( a => mult_125_G3_A_not_9_port, b =>
mult_125_G3_B_not_0_port, outb =>
mult_125_G3_ab_9_0_port);
mult_125_G3_AN2_8_15 : nor2 port map( a => mult_125_G3_A_notx_8_port, b =>
mult_125_G3_B_not_15_port, outb =>
mult_125_G3_ab_8_15_port);
mult_125_G3_AN1_8_14 : nor2 port map( a => mult_125_G3_A_not_8_port, b =>
mult_125_G3_B_not_14_port, outb =>
mult_125_G3_ab_8_14_port);
mult_125_G3_AN1_8_13 : nor2 port map( a => mult_125_G3_A_not_8_port, b =>
mult_125_G3_B_not_13_port, outb =>
mult_125_G3_ab_8_13_port);
mult_125_G3_AN1_8_12 : nor2 port map( a => mult_125_G3_A_not_8_port, b =>
mult_125_G3_B_not_12_port, outb =>
mult_125_G3_ab_8_12_port);
mult_125_G3_AN1_8_11 : nor2 port map( a => mult_125_G3_A_not_8_port, b =>
mult_125_G3_B_not_11_port, outb =>
mult_125_G3_ab_8_11_port);
mult_125_G3_AN1_8_10 : nor2 port map( a => mult_125_G3_A_not_8_port, b =>
mult_125_G3_B_not_10_port, outb =>
mult_125_G3_ab_8_10_port);
mult_125_G3_AN1_8_9 : nor2 port map( a => mult_125_G3_A_not_8_port, b =>
mult_125_G3_B_not_9_port, outb =>
mult_125_G3_ab_8_9_port);
mult_125_G3_AN1_8_8 : nor2 port map( a => mult_125_G3_A_not_8_port, b =>
mult_125_G3_B_not_8_port, outb =>
mult_125_G3_ab_8_8_port);
mult_125_G3_AN1_8_7 : nor2 port map( a => mult_125_G3_A_not_8_port, b =>
mult_125_G3_B_not_7_port, outb =>
mult_125_G3_ab_8_7_port);
mult_125_G3_AN1_8_6 : nor2 port map( a => mult_125_G3_A_not_8_port, b =>
mult_125_G3_B_not_6_port, outb =>
mult_125_G3_ab_8_6_port);
mult_125_G3_AN1_8_5 : nor2 port map( a => mult_125_G3_A_not_8_port, b =>
mult_125_G3_B_not_5_port, outb =>
mult_125_G3_ab_8_5_port);
mult_125_G3_AN1_8_4 : nor2 port map( a => mult_125_G3_A_not_8_port, b =>
mult_125_G3_B_not_4_port, outb =>
mult_125_G3_ab_8_4_port);
mult_125_G3_AN1_8_3 : nor2 port map( a => mult_125_G3_A_not_8_port, b =>
mult_125_G3_B_not_3_port, outb =>
mult_125_G3_ab_8_3_port);
mult_125_G3_AN1_8_2 : nor2 port map( a => mult_125_G3_A_not_8_port, b =>
mult_125_G3_B_not_2_port, outb =>
mult_125_G3_ab_8_2_port);
mult_125_G3_AN1_8_1 : nor2 port map( a => mult_125_G3_A_not_8_port, b =>
mult_125_G3_B_not_1_port, outb =>
mult_125_G3_ab_8_1_port);
mult_125_G3_AN1_8_0_0 : nor2 port map( a => mult_125_G3_A_not_8_port, b =>
mult_125_G3_B_not_0_port, outb =>
mult_125_G3_ab_8_0_port);
mult_125_G3_AN2_7_15 : nor2 port map( a => mult_125_G3_A_notx_7_port, b =>
mult_125_G3_B_not_15_port, outb =>
mult_125_G3_ab_7_15_port);
mult_125_G3_AN1_7_14 : nor2 port map( a => mult_125_G3_A_not_7_port, b =>
mult_125_G3_B_not_14_port, outb =>
mult_125_G3_ab_7_14_port);
mult_125_G3_AN1_7_13 : nor2 port map( a => mult_125_G3_A_not_7_port, b =>
mult_125_G3_B_not_13_port, outb =>
mult_125_G3_ab_7_13_port);
mult_125_G3_AN1_7_12 : nor2 port map( a => mult_125_G3_A_not_7_port, b =>
mult_125_G3_B_not_12_port, outb =>
mult_125_G3_ab_7_12_port);
mult_125_G3_AN1_7_11 : nor2 port map( a => mult_125_G3_A_not_7_port, b =>
mult_125_G3_B_not_11_port, outb =>
mult_125_G3_ab_7_11_port);
mult_125_G3_AN1_7_10 : nor2 port map( a => mult_125_G3_A_not_7_port, b =>
mult_125_G3_B_not_10_port, outb =>
mult_125_G3_ab_7_10_port);
mult_125_G3_AN1_7_9 : nor2 port map( a => mult_125_G3_A_not_7_port, b =>
mult_125_G3_B_not_9_port, outb =>
mult_125_G3_ab_7_9_port);
mult_125_G3_AN1_7_8 : nor2 port map( a => mult_125_G3_A_not_7_port, b =>
mult_125_G3_B_not_8_port, outb =>
mult_125_G3_ab_7_8_port);
mult_125_G3_AN1_7_7 : nor2 port map( a => mult_125_G3_A_not_7_port, b =>
mult_125_G3_B_not_7_port, outb =>
mult_125_G3_ab_7_7_port);
mult_125_G3_AN1_7_6 : nor2 port map( a => mult_125_G3_A_not_7_port, b =>
mult_125_G3_B_not_6_port, outb =>
mult_125_G3_ab_7_6_port);
mult_125_G3_AN1_7_5 : nor2 port map( a => mult_125_G3_A_not_7_port, b =>
mult_125_G3_B_not_5_port, outb =>
mult_125_G3_ab_7_5_port);
mult_125_G3_AN1_7_4 : nor2 port map( a => mult_125_G3_A_not_7_port, b =>
mult_125_G3_B_not_4_port, outb =>
mult_125_G3_ab_7_4_port);
mult_125_G3_AN1_7_3 : nor2 port map( a => mult_125_G3_A_not_7_port, b =>
mult_125_G3_B_not_3_port, outb =>
mult_125_G3_ab_7_3_port);
mult_125_G3_AN1_7_2 : nor2 port map( a => mult_125_G3_A_not_7_port, b =>
mult_125_G3_B_not_2_port, outb =>
mult_125_G3_ab_7_2_port);
mult_125_G3_AN1_7_1 : nor2 port map( a => mult_125_G3_A_not_7_port, b =>
mult_125_G3_B_not_1_port, outb =>
mult_125_G3_ab_7_1_port);
mult_125_G3_AN1_7_0_0 : nor2 port map( a => mult_125_G3_A_not_7_port, b =>
mult_125_G3_B_not_0_port, outb =>
mult_125_G3_ab_7_0_port);
mult_125_G3_AN2_6_15 : nor2 port map( a => mult_125_G3_A_notx_6_port, b =>
mult_125_G3_B_not_15_port, outb =>
mult_125_G3_ab_6_15_port);
mult_125_G3_AN1_6_14 : nor2 port map( a => mult_125_G3_A_not_6_port, b =>
mult_125_G3_B_not_14_port, outb =>
mult_125_G3_ab_6_14_port);
mult_125_G3_AN1_6_13 : nor2 port map( a => mult_125_G3_A_not_6_port, b =>
mult_125_G3_B_not_13_port, outb =>
mult_125_G3_ab_6_13_port);
mult_125_G3_AN1_6_12 : nor2 port map( a => mult_125_G3_A_not_6_port, b =>
mult_125_G3_B_not_12_port, outb =>
mult_125_G3_ab_6_12_port);
mult_125_G3_AN1_6_11 : nor2 port map( a => mult_125_G3_A_not_6_port, b =>
mult_125_G3_B_not_11_port, outb =>
mult_125_G3_ab_6_11_port);
mult_125_G3_AN1_6_10 : nor2 port map( a => mult_125_G3_A_not_6_port, b =>
mult_125_G3_B_not_10_port, outb =>
mult_125_G3_ab_6_10_port);
mult_125_G3_AN1_6_9 : nor2 port map( a => mult_125_G3_A_not_6_port, b =>
mult_125_G3_B_not_9_port, outb =>
mult_125_G3_ab_6_9_port);
mult_125_G3_AN1_6_8 : nor2 port map( a => mult_125_G3_A_not_6_port, b =>
mult_125_G3_B_not_8_port, outb =>
mult_125_G3_ab_6_8_port);
mult_125_G3_AN1_6_7 : nor2 port map( a => mult_125_G3_A_not_6_port, b =>
mult_125_G3_B_not_7_port, outb =>
mult_125_G3_ab_6_7_port);
mult_125_G3_AN1_6_6 : nor2 port map( a => mult_125_G3_A_not_6_port, b =>
mult_125_G3_B_not_6_port, outb =>
mult_125_G3_ab_6_6_port);
mult_125_G3_AN1_6_5 : nor2 port map( a => mult_125_G3_A_not_6_port, b =>
mult_125_G3_B_not_5_port, outb =>
mult_125_G3_ab_6_5_port);
mult_125_G3_AN1_6_4 : nor2 port map( a => mult_125_G3_A_not_6_port, b =>
mult_125_G3_B_not_4_port, outb =>
mult_125_G3_ab_6_4_port);
mult_125_G3_AN1_6_3 : nor2 port map( a => mult_125_G3_A_not_6_port, b =>
mult_125_G3_B_not_3_port, outb =>
mult_125_G3_ab_6_3_port);
mult_125_G3_AN1_6_2 : nor2 port map( a => mult_125_G3_A_not_6_port, b =>
mult_125_G3_B_not_2_port, outb =>
mult_125_G3_ab_6_2_port);
mult_125_G3_AN1_6_1 : nor2 port map( a => mult_125_G3_A_not_6_port, b =>
mult_125_G3_B_not_1_port, outb =>
mult_125_G3_ab_6_1_port);
mult_125_G3_AN1_6_0_0 : nor2 port map( a => mult_125_G3_A_not_6_port, b =>
mult_125_G3_B_not_0_port, outb =>
mult_125_G3_ab_6_0_port);
mult_125_G3_AN2_5_15 : nor2 port map( a => mult_125_G3_A_notx_5_port, b =>
mult_125_G3_B_not_15_port, outb =>
mult_125_G3_ab_5_15_port);
mult_125_G3_AN1_5_14 : nor2 port map( a => mult_125_G3_A_not_5_port, b =>
mult_125_G3_B_not_14_port, outb =>
mult_125_G3_ab_5_14_port);
mult_125_G3_AN1_5_13 : nor2 port map( a => mult_125_G3_A_not_5_port, b =>
mult_125_G3_B_not_13_port, outb =>
mult_125_G3_ab_5_13_port);
mult_125_G3_AN1_5_12 : nor2 port map( a => mult_125_G3_A_not_5_port, b =>
mult_125_G3_B_not_12_port, outb =>
mult_125_G3_ab_5_12_port);
mult_125_G3_AN1_5_11 : nor2 port map( a => mult_125_G3_A_not_5_port, b =>
mult_125_G3_B_not_11_port, outb =>
mult_125_G3_ab_5_11_port);
mult_125_G3_AN1_5_10 : nor2 port map( a => mult_125_G3_A_not_5_port, b =>
mult_125_G3_B_not_10_port, outb =>
mult_125_G3_ab_5_10_port);
mult_125_G3_AN1_5_9 : nor2 port map( a => mult_125_G3_A_not_5_port, b =>
mult_125_G3_B_not_9_port, outb =>
mult_125_G3_ab_5_9_port);
mult_125_G3_AN1_5_8 : nor2 port map( a => mult_125_G3_A_not_5_port, b =>
mult_125_G3_B_not_8_port, outb =>
mult_125_G3_ab_5_8_port);
mult_125_G3_AN1_5_7 : nor2 port map( a => mult_125_G3_A_not_5_port, b =>
mult_125_G3_B_not_7_port, outb =>
mult_125_G3_ab_5_7_port);
mult_125_G3_AN1_5_6 : nor2 port map( a => mult_125_G3_A_not_5_port, b =>
mult_125_G3_B_not_6_port, outb =>
mult_125_G3_ab_5_6_port);
mult_125_G3_AN1_5_5 : nor2 port map( a => mult_125_G3_A_not_5_port, b =>
mult_125_G3_B_not_5_port, outb =>
mult_125_G3_ab_5_5_port);
mult_125_G3_AN1_5_4 : nor2 port map( a => mult_125_G3_A_not_5_port, b =>
mult_125_G3_B_not_4_port, outb =>
mult_125_G3_ab_5_4_port);
mult_125_G3_AN1_5_3 : nor2 port map( a => mult_125_G3_A_not_5_port, b =>
mult_125_G3_B_not_3_port, outb =>
mult_125_G3_ab_5_3_port);
mult_125_G3_AN1_5_2 : nor2 port map( a => mult_125_G3_A_not_5_port, b =>
mult_125_G3_B_not_2_port, outb =>
mult_125_G3_ab_5_2_port);
mult_125_G3_AN1_5_1 : nor2 port map( a => mult_125_G3_A_not_5_port, b =>
mult_125_G3_B_not_1_port, outb =>
mult_125_G3_ab_5_1_port);
mult_125_G3_AN1_5_0_0 : nor2 port map( a => mult_125_G3_A_not_5_port, b =>
mult_125_G3_B_not_0_port, outb =>
mult_125_G3_ab_5_0_port);
mult_125_G3_AN2_4_15 : nor2 port map( a => mult_125_G3_A_notx_4_port, b =>
mult_125_G3_B_not_15_port, outb =>
mult_125_G3_ab_4_15_port);
mult_125_G3_AN1_4_14 : nor2 port map( a => mult_125_G3_A_not_4_port, b =>
mult_125_G3_B_not_14_port, outb =>
mult_125_G3_ab_4_14_port);
mult_125_G3_AN1_4_13 : nor2 port map( a => mult_125_G3_A_not_4_port, b =>
mult_125_G3_B_not_13_port, outb =>
mult_125_G3_ab_4_13_port);
mult_125_G3_AN1_4_12 : nor2 port map( a => mult_125_G3_A_not_4_port, b =>
mult_125_G3_B_not_12_port, outb =>
mult_125_G3_ab_4_12_port);
mult_125_G3_AN1_4_11 : nor2 port map( a => mult_125_G3_A_not_4_port, b =>
mult_125_G3_B_not_11_port, outb =>
mult_125_G3_ab_4_11_port);
mult_125_G3_AN1_4_10 : nor2 port map( a => mult_125_G3_A_not_4_port, b =>
mult_125_G3_B_not_10_port, outb =>
mult_125_G3_ab_4_10_port);
mult_125_G3_AN1_4_9 : nor2 port map( a => mult_125_G3_A_not_4_port, b =>
mult_125_G3_B_not_9_port, outb =>
mult_125_G3_ab_4_9_port);
mult_125_G3_AN1_4_8 : nor2 port map( a => mult_125_G3_A_not_4_port, b =>
mult_125_G3_B_not_8_port, outb =>
mult_125_G3_ab_4_8_port);
mult_125_G3_AN1_4_7 : nor2 port map( a => mult_125_G3_A_not_4_port, b =>
mult_125_G3_B_not_7_port, outb =>
mult_125_G3_ab_4_7_port);
mult_125_G3_AN1_4_6 : nor2 port map( a => mult_125_G3_A_not_4_port, b =>
mult_125_G3_B_not_6_port, outb =>
mult_125_G3_ab_4_6_port);
mult_125_G3_AN1_4_5 : nor2 port map( a => mult_125_G3_A_not_4_port, b =>
mult_125_G3_B_not_5_port, outb =>
mult_125_G3_ab_4_5_port);
mult_125_G3_AN1_4_4 : nor2 port map( a => mult_125_G3_A_not_4_port, b =>
mult_125_G3_B_not_4_port, outb =>
mult_125_G3_ab_4_4_port);
mult_125_G3_AN1_4_3 : nor2 port map( a => mult_125_G3_A_not_4_port, b =>
mult_125_G3_B_not_3_port, outb =>
mult_125_G3_ab_4_3_port);
mult_125_G3_AN1_4_2 : nor2 port map( a => mult_125_G3_A_not_4_port, b =>
mult_125_G3_B_not_2_port, outb =>
mult_125_G3_ab_4_2_port);
mult_125_G3_AN1_4_1 : nor2 port map( a => mult_125_G3_A_not_4_port, b =>
mult_125_G3_B_not_1_port, outb =>
mult_125_G3_ab_4_1_port);
mult_125_G3_AN1_4_0_0 : nor2 port map( a => mult_125_G3_A_not_4_port, b =>
mult_125_G3_B_not_0_port, outb =>
mult_125_G3_ab_4_0_port);
mult_125_G3_AN2_3_15 : nor2 port map( a => mult_125_G3_A_notx_3_port, b =>
mult_125_G3_B_not_15_port, outb =>
mult_125_G3_ab_3_15_port);
mult_125_G3_AN1_3_14 : nor2 port map( a => mult_125_G3_A_not_3_port, b =>
mult_125_G3_B_not_14_port, outb =>
mult_125_G3_ab_3_14_port);
mult_125_G3_AN1_3_13 : nor2 port map( a => mult_125_G3_A_not_3_port, b =>
mult_125_G3_B_not_13_port, outb =>
mult_125_G3_ab_3_13_port);
mult_125_G3_AN1_3_12 : nor2 port map( a => mult_125_G3_A_not_3_port, b =>
mult_125_G3_B_not_12_port, outb =>
mult_125_G3_ab_3_12_port);
mult_125_G3_AN1_3_11 : nor2 port map( a => mult_125_G3_A_not_3_port, b =>
mult_125_G3_B_not_11_port, outb =>
mult_125_G3_ab_3_11_port);
mult_125_G3_AN1_3_10 : nor2 port map( a => mult_125_G3_A_not_3_port, b =>
mult_125_G3_B_not_10_port, outb =>
mult_125_G3_ab_3_10_port);
mult_125_G3_AN1_3_9 : nor2 port map( a => mult_125_G3_A_not_3_port, b =>
mult_125_G3_B_not_9_port, outb =>
mult_125_G3_ab_3_9_port);
mult_125_G3_AN1_3_8 : nor2 port map( a => mult_125_G3_A_not_3_port, b =>
mult_125_G3_B_not_8_port, outb =>
mult_125_G3_ab_3_8_port);
mult_125_G3_AN1_3_7 : nor2 port map( a => mult_125_G3_A_not_3_port, b =>
mult_125_G3_B_not_7_port, outb =>
mult_125_G3_ab_3_7_port);
mult_125_G3_AN1_3_6 : nor2 port map( a => mult_125_G3_A_not_3_port, b =>
mult_125_G3_B_not_6_port, outb =>
mult_125_G3_ab_3_6_port);
mult_125_G3_AN1_3_5 : nor2 port map( a => mult_125_G3_A_not_3_port, b =>
mult_125_G3_B_not_5_port, outb =>
mult_125_G3_ab_3_5_port);
mult_125_G3_AN1_3_4 : nor2 port map( a => mult_125_G3_A_not_3_port, b =>
mult_125_G3_B_not_4_port, outb =>
mult_125_G3_ab_3_4_port);
mult_125_G3_AN1_3_3 : nor2 port map( a => mult_125_G3_A_not_3_port, b =>
mult_125_G3_B_not_3_port, outb =>
mult_125_G3_ab_3_3_port);
mult_125_G3_AN1_3_2 : nor2 port map( a => mult_125_G3_A_not_3_port, b =>
mult_125_G3_B_not_2_port, outb =>
mult_125_G3_ab_3_2_port);
mult_125_G3_AN1_3_1 : nor2 port map( a => mult_125_G3_A_not_3_port, b =>
mult_125_G3_B_not_1_port, outb =>
mult_125_G3_ab_3_1_port);
mult_125_G3_AN1_3_0_0 : nor2 port map( a => mult_125_G3_A_not_3_port, b =>
mult_125_G3_B_not_0_port, outb =>
mult_125_G3_ab_3_0_port);
mult_125_G3_AN2_2_15 : nor2 port map( a => mult_125_G3_A_notx_2_port, b =>
mult_125_G3_B_not_15_port, outb =>
mult_125_G3_ab_2_15_port);
mult_125_G3_AN1_2_14 : nor2 port map( a => mult_125_G3_A_not_2_port, b =>
mult_125_G3_B_not_14_port, outb =>
mult_125_G3_ab_2_14_port);
mult_125_G3_AN1_2_13 : nor2 port map( a => mult_125_G3_A_not_2_port, b =>
mult_125_G3_B_not_13_port, outb =>
mult_125_G3_ab_2_13_port);
mult_125_G3_AN1_2_12 : nor2 port map( a => mult_125_G3_A_not_2_port, b =>
mult_125_G3_B_not_12_port, outb =>
mult_125_G3_ab_2_12_port);
mult_125_G3_AN1_2_11 : nor2 port map( a => mult_125_G3_A_not_2_port, b =>
mult_125_G3_B_not_11_port, outb =>
mult_125_G3_ab_2_11_port);
mult_125_G3_AN1_2_10 : nor2 port map( a => mult_125_G3_A_not_2_port, b =>
mult_125_G3_B_not_10_port, outb =>
mult_125_G3_ab_2_10_port);
mult_125_G3_AN1_2_9 : nor2 port map( a => mult_125_G3_A_not_2_port, b =>
mult_125_G3_B_not_9_port, outb =>
mult_125_G3_ab_2_9_port);
mult_125_G3_AN1_2_8 : nor2 port map( a => mult_125_G3_A_not_2_port, b =>
mult_125_G3_B_not_8_port, outb =>
mult_125_G3_ab_2_8_port);
mult_125_G3_AN1_2_7 : nor2 port map( a => mult_125_G3_A_not_2_port, b =>
mult_125_G3_B_not_7_port, outb =>
mult_125_G3_ab_2_7_port);
mult_125_G3_AN1_2_6 : nor2 port map( a => mult_125_G3_A_not_2_port, b =>
mult_125_G3_B_not_6_port, outb =>
mult_125_G3_ab_2_6_port);
mult_125_G3_AN1_2_5 : nor2 port map( a => mult_125_G3_A_not_2_port, b =>
mult_125_G3_B_not_5_port, outb =>
mult_125_G3_ab_2_5_port);
mult_125_G3_AN1_2_4 : nor2 port map( a => mult_125_G3_A_not_2_port, b =>
mult_125_G3_B_not_4_port, outb =>
mult_125_G3_ab_2_4_port);
mult_125_G3_AN1_2_3 : nor2 port map( a => mult_125_G3_A_not_2_port, b =>
mult_125_G3_B_not_3_port, outb =>
mult_125_G3_ab_2_3_port);
mult_125_G3_AN1_2_2 : nor2 port map( a => mult_125_G3_A_not_2_port, b =>
mult_125_G3_B_not_2_port, outb =>
mult_125_G3_ab_2_2_port);
mult_125_G3_AN1_2_1 : nor2 port map( a => mult_125_G3_A_not_2_port, b =>
mult_125_G3_B_not_1_port, outb =>
mult_125_G3_ab_2_1_port);
mult_125_G3_AN1_2_0_0 : nor2 port map( a => mult_125_G3_A_not_2_port, b =>
mult_125_G3_B_not_0_port, outb =>
mult_125_G3_ab_2_0_port);
mult_125_G3_AN2_1_15 : nor2 port map( a => mult_125_G3_A_notx_1_port, b =>
mult_125_G3_B_not_15_port, outb =>
mult_125_G3_ab_1_15_port);
mult_125_G3_AN1_1_14 : nor2 port map( a => mult_125_G3_A_not_1_port, b =>
mult_125_G3_B_not_14_port, outb =>
mult_125_G3_ab_1_14_port);
mult_125_G3_AN1_1_13 : nor2 port map( a => mult_125_G3_A_not_1_port, b =>
mult_125_G3_B_not_13_port, outb =>
mult_125_G3_ab_1_13_port);
mult_125_G3_AN1_1_12 : nor2 port map( a => mult_125_G3_A_not_1_port, b =>
mult_125_G3_B_not_12_port, outb =>
mult_125_G3_ab_1_12_port);
mult_125_G3_AN1_1_11 : nor2 port map( a => mult_125_G3_A_not_1_port, b =>
mult_125_G3_B_not_11_port, outb =>
mult_125_G3_ab_1_11_port);
mult_125_G3_AN1_1_10 : nor2 port map( a => mult_125_G3_A_not_1_port, b =>
mult_125_G3_B_not_10_port, outb =>
mult_125_G3_ab_1_10_port);
mult_125_G3_AN1_1_9 : nor2 port map( a => mult_125_G3_A_not_1_port, b =>
mult_125_G3_B_not_9_port, outb =>
mult_125_G3_ab_1_9_port);
mult_125_G3_AN1_1_8 : nor2 port map( a => mult_125_G3_A_not_1_port, b =>
mult_125_G3_B_not_8_port, outb =>
mult_125_G3_ab_1_8_port);
mult_125_G3_AN1_1_7 : nor2 port map( a => mult_125_G3_A_not_1_port, b =>
mult_125_G3_B_not_7_port, outb =>
mult_125_G3_ab_1_7_port);
mult_125_G3_AN1_1_6 : nor2 port map( a => mult_125_G3_A_not_1_port, b =>
mult_125_G3_B_not_6_port, outb =>
mult_125_G3_ab_1_6_port);
mult_125_G3_AN1_1_5 : nor2 port map( a => mult_125_G3_A_not_1_port, b =>
mult_125_G3_B_not_5_port, outb =>
mult_125_G3_ab_1_5_port);
mult_125_G3_AN1_1_4 : nor2 port map( a => mult_125_G3_A_not_1_port, b =>
mult_125_G3_B_not_4_port, outb =>
mult_125_G3_ab_1_4_port);
mult_125_G3_AN1_1_3 : nor2 port map( a => mult_125_G3_A_not_1_port, b =>
mult_125_G3_B_not_3_port, outb =>
mult_125_G3_ab_1_3_port);
mult_125_G3_AN1_1_2 : nor2 port map( a => mult_125_G3_A_not_1_port, b =>
mult_125_G3_B_not_2_port, outb =>
mult_125_G3_ab_1_2_port);
mult_125_G3_AN1_1_1 : nor2 port map( a => mult_125_G3_A_not_1_port, b =>
mult_125_G3_B_not_1_port, outb =>
mult_125_G3_ab_1_1_port);
mult_125_G3_AN1_1_0_0 : nor2 port map( a => mult_125_G3_A_not_1_port, b =>
mult_125_G3_B_not_0_port, outb =>
mult_125_G3_ab_1_0_port);
mult_125_G3_AN2_0_15 : nor2 port map( a => mult_125_G3_A_notx_0_port, b =>
mult_125_G3_B_not_15_port, outb =>
mult_125_G3_ab_0_15_port);
mult_125_G3_AN1_0_14 : nor2 port map( a => mult_125_G3_A_not_0_port, b =>
mult_125_G3_B_not_14_port, outb =>
mult_125_G3_ab_0_14_port);
mult_125_G3_AN1_0_13 : nor2 port map( a => mult_125_G3_A_not_0_port, b =>
mult_125_G3_B_not_13_port, outb =>
mult_125_G3_ab_0_13_port);
mult_125_G3_AN1_0_12 : nor2 port map( a => mult_125_G3_A_not_0_port, b =>
mult_125_G3_B_not_12_port, outb =>
mult_125_G3_ab_0_12_port);
mult_125_G3_AN1_0_11 : nor2 port map( a => mult_125_G3_A_not_0_port, b =>
mult_125_G3_B_not_11_port, outb =>
mult_125_G3_ab_0_11_port);
mult_125_G3_AN1_0_10 : nor2 port map( a => mult_125_G3_A_not_0_port, b =>
mult_125_G3_B_not_10_port, outb =>
mult_125_G3_ab_0_10_port);
mult_125_G3_AN1_0_9 : nor2 port map( a => mult_125_G3_A_not_0_port, b =>
mult_125_G3_B_not_9_port, outb =>
mult_125_G3_ab_0_9_port);
mult_125_G3_AN1_0_8 : nor2 port map( a => mult_125_G3_A_not_0_port, b =>
mult_125_G3_B_not_8_port, outb =>
mult_125_G3_ab_0_8_port);
mult_125_G3_AN1_0_7 : nor2 port map( a => mult_125_G3_A_not_0_port, b =>
mult_125_G3_B_not_7_port, outb =>
mult_125_G3_ab_0_7_port);
mult_125_G3_AN1_0_6 : nor2 port map( a => mult_125_G3_A_not_0_port, b =>
mult_125_G3_B_not_6_port, outb =>
mult_125_G3_ab_0_6_port);
mult_125_G3_AN1_0_5 : nor2 port map( a => mult_125_G3_A_not_0_port, b =>
mult_125_G3_B_not_5_port, outb =>
mult_125_G3_ab_0_5_port);
mult_125_G3_AN1_0_4 : nor2 port map( a => mult_125_G3_A_not_0_port, b =>
mult_125_G3_B_not_4_port, outb =>
mult_125_G3_ab_0_4_port);
mult_125_G3_AN1_0_3 : nor2 port map( a => mult_125_G3_A_not_0_port, b =>
mult_125_G3_B_not_3_port, outb =>
mult_125_G3_ab_0_3_port);
mult_125_G3_AN1_0_2 : nor2 port map( a => mult_125_G3_A_not_0_port, b =>
mult_125_G3_B_not_2_port, outb =>
mult_125_G3_ab_0_2_port);
mult_125_G3_AN1_0_1 : nor2 port map( a => mult_125_G3_A_not_0_port, b =>
mult_125_G3_B_not_1_port, outb =>
mult_125_G3_ab_0_1_port);
mult_125_G3_AN1_0_0_0 : nor2 port map( a => mult_125_G3_A_not_0_port, b =>
mult_125_G3_B_not_0_port, outb =>
multiplier_sigs_2_0_port);
mult_125_G2_FS_1_U6_1_1_3 : oai12 port map( b => n5907, c => n5908, a =>
n5909, outb => mult_125_G2_FS_1_C_1_7_0_port);
mult_125_G2_FS_1_U6_1_1_2 : oai12 port map( b => n5904, c => n5905, a =>
n5906, outb => mult_125_G2_FS_1_C_1_6_0_port);
mult_125_G2_FS_1_U6_1_1_1 : oai12 port map( b => n5901, c => n5902, a =>
n5903, outb => mult_125_G2_FS_1_C_1_5_0_port);
mult_125_G2_FS_1_U6_0_7_1 : oai12 port map( b => n5898, c => n5899, a =>
mult_125_G2_FS_1_G_n_int_0_7_0_port, outb =>
mult_125_G2_FS_1_C_1_7_1_port);
mult_125_G2_FS_1_U3_C_0_7_1 : xor2 port map( a =>
mult_125_G2_FS_1_PG_int_0_7_1_port, b =>
mult_125_G2_FS_1_C_1_7_1_port, outb =>
multiplier_sigs_1_31_port);
mult_125_G2_FS_1_U3_B_0_7_1 : nand2 port map( a =>
mult_125_G2_FS_1_G_n_int_0_7_1_port, b =>
mult_125_G2_FS_1_P_0_7_1_port, outb => n5897);
mult_125_G2_FS_1_U2_0_7_1 : nand2 port map( a => mult_125_G2_A1_29_port, b
=> mult_125_G2_A2_29_port, outb =>
mult_125_G2_FS_1_G_n_int_0_7_1_port);
mult_125_G2_FS_1_U1_0_7_1 : nand2 port map( a => n5895, b => n5896, outb =>
mult_125_G2_FS_1_P_0_7_1_port);
mult_125_G2_FS_1_U3_C_0_7_0 : xor2 port map( a =>
mult_125_G2_FS_1_PG_int_0_7_0_port, b =>
mult_125_G2_FS_1_C_1_7_0_port, outb =>
multiplier_sigs_1_30_port);
mult_125_G2_FS_1_U3_B_0_7_0 : nand2 port map( a =>
mult_125_G2_FS_1_G_n_int_0_7_0_port, b =>
mult_125_G2_FS_1_TEMP_P_0_7_0_port, outb => n5894);
mult_125_G2_FS_1_U2_0_7_0 : nand2 port map( a => mult_125_G2_A1_28_port, b
=> mult_125_G2_A2_28_port, outb =>
mult_125_G2_FS_1_G_n_int_0_7_0_port);
mult_125_G2_FS_1_U1_0_7_0 : nand2 port map( a => n5892, b => n5893, outb =>
mult_125_G2_FS_1_TEMP_P_0_7_0_port);
mult_125_G2_FS_1_U6_0_6_3 : oai12 port map( b => n5890, c => n5891, a =>
mult_125_G2_FS_1_G_n_int_0_6_2_port, outb =>
mult_125_G2_FS_1_C_1_6_3_port);
mult_125_G2_FS_1_U5_0_6_3 : oai12 port map( b => n5888, c => n5889, a =>
mult_125_G2_FS_1_G_n_int_0_6_3_port, outb =>
mult_125_G2_FS_1_G_1_1_2_port);
mult_125_G2_FS_1_U4_0_6_3 : nand2 port map( a =>
mult_125_G2_FS_1_TEMP_P_0_6_2_port, b =>
mult_125_G2_FS_1_P_0_6_3_port, outb => n5908);
mult_125_G2_FS_1_U3_C_0_6_3 : xor2 port map( a =>
mult_125_G2_FS_1_PG_int_0_6_3_port, b =>
mult_125_G2_FS_1_C_1_6_3_port, outb =>
multiplier_sigs_1_29_port);
mult_125_G2_FS_1_U3_B_0_6_3 : nand2 port map( a =>
mult_125_G2_FS_1_G_n_int_0_6_3_port, b =>
mult_125_G2_FS_1_P_0_6_3_port, outb => n5887);
mult_125_G2_FS_1_U2_0_6_3 : nand2 port map( a => mult_125_G2_A1_27_port, b
=> mult_125_G2_A2_27_port, outb =>
mult_125_G2_FS_1_G_n_int_0_6_3_port);
mult_125_G2_FS_1_U1_0_6_3 : nand2 port map( a => n5885, b => n5886, outb =>
mult_125_G2_FS_1_P_0_6_3_port);
mult_125_G2_FS_1_U6_0_6_2 : oai12 port map( b => n5883, c => n5884, a =>
mult_125_G2_FS_1_G_n_int_0_6_1_port, outb =>
mult_125_G2_FS_1_C_1_6_2_port);
mult_125_G2_FS_1_U5_0_6_2 : oai12 port map( b => n5882, c => n5891, a =>
mult_125_G2_FS_1_G_n_int_0_6_2_port, outb =>
mult_125_G2_FS_1_TEMP_G_0_6_2_port);
mult_125_G2_FS_1_U4_0_6_2 : nand2 port map( a =>
mult_125_G2_FS_1_TEMP_P_0_6_1_port, b =>
mult_125_G2_FS_1_P_0_6_2_port, outb => n5881);
mult_125_G2_FS_1_U3_C_0_6_2 : xor2 port map( a =>
mult_125_G2_FS_1_PG_int_0_6_2_port, b =>
mult_125_G2_FS_1_C_1_6_2_port, outb =>
multiplier_sigs_1_28_port);
mult_125_G2_FS_1_U3_B_0_6_2 : nand2 port map( a =>
mult_125_G2_FS_1_G_n_int_0_6_2_port, b =>
mult_125_G2_FS_1_P_0_6_2_port, outb => n5880);
mult_125_G2_FS_1_U2_0_6_2 : nand2 port map( a => mult_125_G2_A1_26_port, b
=> mult_125_G2_A2_26_port, outb =>
mult_125_G2_FS_1_G_n_int_0_6_2_port);
mult_125_G2_FS_1_U1_0_6_2 : nand2 port map( a => n5878, b => n5879, outb =>
mult_125_G2_FS_1_P_0_6_2_port);
mult_125_G2_FS_1_U6_0_6_1 : oai12 port map( b => n5907, c => n5877, a =>
mult_125_G2_FS_1_G_n_int_0_6_0_port, outb =>
mult_125_G2_FS_1_C_1_6_1_port);
mult_125_G2_FS_1_U5_0_6_1 : oai12 port map( b =>
mult_125_G2_FS_1_G_n_int_0_6_0_port, c => n5884, a
=> mult_125_G2_FS_1_G_n_int_0_6_1_port, outb =>
mult_125_G2_FS_1_TEMP_G_0_6_1_port);
mult_125_G2_FS_1_U4_0_6_1 : nand2 port map( a =>
mult_125_G2_FS_1_TEMP_P_0_6_0_port, b =>
mult_125_G2_FS_1_P_0_6_1_port, outb => n5876);
mult_125_G2_FS_1_U3_C_0_6_1 : xor2 port map( a =>
mult_125_G2_FS_1_PG_int_0_6_1_port, b =>
mult_125_G2_FS_1_C_1_6_1_port, outb =>
multiplier_sigs_1_27_port);
mult_125_G2_FS_1_U3_B_0_6_1 : nand2 port map( a =>
mult_125_G2_FS_1_G_n_int_0_6_1_port, b =>
mult_125_G2_FS_1_P_0_6_1_port, outb => n5875);
mult_125_G2_FS_1_U2_0_6_1 : nand2 port map( a => mult_125_G2_A1_25_port, b
=> mult_125_G2_A2_25_port, outb =>
mult_125_G2_FS_1_G_n_int_0_6_1_port);
mult_125_G2_FS_1_U1_0_6_1 : nand2 port map( a => n5873, b => n5874, outb =>
mult_125_G2_FS_1_P_0_6_1_port);
mult_125_G2_FS_1_U3_C_0_6_0 : xor2 port map( a =>
mult_125_G2_FS_1_PG_int_0_6_0_port, b =>
mult_125_G2_FS_1_C_1_6_0_port, outb =>
multiplier_sigs_1_26_port);
mult_125_G2_FS_1_U3_B_0_6_0 : nand2 port map( a =>
mult_125_G2_FS_1_G_n_int_0_6_0_port, b =>
mult_125_G2_FS_1_TEMP_P_0_6_0_port, outb => n5872);
mult_125_G2_FS_1_U2_0_6_0 : nand2 port map( a => mult_125_G2_A1_24_port, b
=> mult_125_G2_A2_24_port, outb =>
mult_125_G2_FS_1_G_n_int_0_6_0_port);
mult_125_G2_FS_1_U1_0_6_0 : nand2 port map( a => n5870, b => n5871, outb =>
mult_125_G2_FS_1_TEMP_P_0_6_0_port);
mult_125_G2_FS_1_U6_0_5_3 : oai12 port map( b => n5868, c => n5869, a =>
mult_125_G2_FS_1_G_n_int_0_5_2_port, outb =>
mult_125_G2_FS_1_C_1_5_3_port);
mult_125_G2_FS_1_U5_0_5_3 : oai12 port map( b => n5866, c => n5867, a =>
mult_125_G2_FS_1_G_n_int_0_5_3_port, outb =>
mult_125_G2_FS_1_G_1_1_1_port);
mult_125_G2_FS_1_U4_0_5_3 : nand2 port map( a =>
mult_125_G2_FS_1_TEMP_P_0_5_2_port, b =>
mult_125_G2_FS_1_P_0_5_3_port, outb => n5905);
mult_125_G2_FS_1_U3_C_0_5_3 : xor2 port map( a =>
mult_125_G2_FS_1_PG_int_0_5_3_port, b =>
mult_125_G2_FS_1_C_1_5_3_port, outb =>
multiplier_sigs_1_25_port);
mult_125_G2_FS_1_U3_B_0_5_3 : nand2 port map( a =>
mult_125_G2_FS_1_G_n_int_0_5_3_port, b =>
mult_125_G2_FS_1_P_0_5_3_port, outb => n5865);
mult_125_G2_FS_1_U2_0_5_3 : nand2 port map( a => mult_125_G2_A1_23_port, b
=> mult_125_G2_A2_23_port, outb =>
mult_125_G2_FS_1_G_n_int_0_5_3_port);
mult_125_G2_FS_1_U1_0_5_3 : nand2 port map( a => n5863, b => n5864, outb =>
mult_125_G2_FS_1_P_0_5_3_port);
mult_125_G2_FS_1_U6_0_5_2 : oai12 port map( b => n5861, c => n5862, a =>
mult_125_G2_FS_1_G_n_int_0_5_1_port, outb =>
mult_125_G2_FS_1_C_1_5_2_port);
mult_125_G2_FS_1_U5_0_5_2 : oai12 port map( b => n5860, c => n5869, a =>
mult_125_G2_FS_1_G_n_int_0_5_2_port, outb =>
mult_125_G2_FS_1_TEMP_G_0_5_2_port);
mult_125_G2_FS_1_U4_0_5_2 : nand2 port map( a =>
mult_125_G2_FS_1_TEMP_P_0_5_1_port, b =>
mult_125_G2_FS_1_P_0_5_2_port, outb => n5859);
mult_125_G2_FS_1_U3_C_0_5_2 : xor2 port map( a =>
mult_125_G2_FS_1_PG_int_0_5_2_port, b =>
mult_125_G2_FS_1_C_1_5_2_port, outb =>
multiplier_sigs_1_24_port);
mult_125_G2_FS_1_U3_B_0_5_2 : nand2 port map( a =>
mult_125_G2_FS_1_G_n_int_0_5_2_port, b =>
mult_125_G2_FS_1_P_0_5_2_port, outb => n5858);
mult_125_G2_FS_1_U2_0_5_2 : nand2 port map( a => mult_125_G2_A1_22_port, b
=> mult_125_G2_A2_22_port, outb =>
mult_125_G2_FS_1_G_n_int_0_5_2_port);
mult_125_G2_FS_1_U1_0_5_2 : nand2 port map( a => n5856, b => n5857, outb =>
mult_125_G2_FS_1_P_0_5_2_port);
mult_125_G2_FS_1_U6_0_5_1 : oai12 port map( b => n5904, c => n5855, a =>
mult_125_G2_FS_1_G_n_int_0_5_0_port, outb =>
mult_125_G2_FS_1_C_1_5_1_port);
mult_125_G2_FS_1_U5_0_5_1 : oai12 port map( b =>
mult_125_G2_FS_1_G_n_int_0_5_0_port, c => n5862, a
=> mult_125_G2_FS_1_G_n_int_0_5_1_port, outb =>
mult_125_G2_FS_1_TEMP_G_0_5_1_port);
mult_125_G2_FS_1_U4_0_5_1 : nand2 port map( a =>
mult_125_G2_FS_1_TEMP_P_0_5_0_port, b =>
mult_125_G2_FS_1_P_0_5_1_port, outb => n5854);
mult_125_G2_FS_1_U3_C_0_5_1 : xor2 port map( a =>
mult_125_G2_FS_1_PG_int_0_5_1_port, b =>
mult_125_G2_FS_1_C_1_5_1_port, outb =>
multiplier_sigs_1_23_port);
mult_125_G2_FS_1_U3_B_0_5_1 : nand2 port map( a =>
mult_125_G2_FS_1_G_n_int_0_5_1_port, b =>
mult_125_G2_FS_1_P_0_5_1_port, outb => n5853);
mult_125_G2_FS_1_U2_0_5_1 : nand2 port map( a => mult_125_G2_A1_21_port, b
=> mult_125_G2_A2_21_port, outb =>
mult_125_G2_FS_1_G_n_int_0_5_1_port);
mult_125_G2_FS_1_U1_0_5_1 : nand2 port map( a => n5851, b => n5852, outb =>
mult_125_G2_FS_1_P_0_5_1_port);
mult_125_G2_FS_1_U3_C_0_5_0 : xor2 port map( a =>
mult_125_G2_FS_1_PG_int_0_5_0_port, b =>
mult_125_G2_FS_1_C_1_5_0_port, outb =>
multiplier_sigs_1_22_port);
mult_125_G2_FS_1_U3_B_0_5_0 : nand2 port map( a =>
mult_125_G2_FS_1_G_n_int_0_5_0_port, b =>
mult_125_G2_FS_1_TEMP_P_0_5_0_port, outb => n5850);
mult_125_G2_FS_1_U2_0_5_0 : nand2 port map( a => mult_125_G2_A1_20_port, b
=> mult_125_G2_A2_20_port, outb =>
mult_125_G2_FS_1_G_n_int_0_5_0_port);
mult_125_G2_FS_1_U1_0_5_0 : nand2 port map( a => n5848, b => n5849, outb =>
mult_125_G2_FS_1_TEMP_P_0_5_0_port);
mult_125_G2_FS_1_U6_0_4_3 : oai12 port map( b => n5846, c => n5847, a =>
mult_125_G2_FS_1_G_n_int_0_4_2_port, outb =>
mult_125_G2_FS_1_C_1_4_3_port);
mult_125_G2_FS_1_U5_0_4_3 : oai12 port map( b => n5844, c => n5845, a =>
mult_125_G2_FS_1_G_n_int_0_4_3_port, outb =>
mult_125_G2_FS_1_G_1_1_0_port);
mult_125_G2_FS_1_U4_0_4_3 : nand2 port map( a =>
mult_125_G2_FS_1_TEMP_P_0_4_2_port, b =>
mult_125_G2_FS_1_P_0_4_3_port, outb => n5902);
mult_125_G2_FS_1_U3_C_0_4_3 : xor2 port map( a =>
mult_125_G2_FS_1_PG_int_0_4_3_port, b =>
mult_125_G2_FS_1_C_1_4_3_port, outb =>
multiplier_sigs_1_21_port);
mult_125_G2_FS_1_U3_B_0_4_3 : nand2 port map( a =>
mult_125_G2_FS_1_G_n_int_0_4_3_port, b =>
mult_125_G2_FS_1_P_0_4_3_port, outb => n5843);
mult_125_G2_FS_1_U2_0_4_3 : nand2 port map( a => mult_125_G2_A1_19_port, b
=> mult_125_G2_A2_19_port, outb =>
mult_125_G2_FS_1_G_n_int_0_4_3_port);
mult_125_G2_FS_1_U1_0_4_3 : nand2 port map( a => n5841, b => n5842, outb =>
mult_125_G2_FS_1_P_0_4_3_port);
mult_125_G2_FS_1_U6_0_4_2 : oai12 port map( b => n5839, c => n5840, a =>
mult_125_G2_FS_1_G_n_int_0_4_1_port, outb =>
mult_125_G2_FS_1_C_1_4_2_port);
mult_125_G2_FS_1_U5_0_4_2 : oai12 port map( b => n5838, c => n5847, a =>
mult_125_G2_FS_1_G_n_int_0_4_2_port, outb =>
mult_125_G2_FS_1_TEMP_G_0_4_2_port);
mult_125_G2_FS_1_U4_0_4_2 : nand2 port map( a =>
mult_125_G2_FS_1_TEMP_P_0_4_1_port, b =>
mult_125_G2_FS_1_P_0_4_2_port, outb => n5837);
mult_125_G2_FS_1_U3_C_0_4_2 : xor2 port map( a =>
mult_125_G2_FS_1_PG_int_0_4_2_port, b =>
mult_125_G2_FS_1_C_1_4_2_port, outb =>
multiplier_sigs_1_20_port);
mult_125_G2_FS_1_U3_B_0_4_2 : nand2 port map( a =>
mult_125_G2_FS_1_G_n_int_0_4_2_port, b =>
mult_125_G2_FS_1_P_0_4_2_port, outb => n5836);
mult_125_G2_FS_1_U2_0_4_2 : nand2 port map( a => mult_125_G2_A1_18_port, b
=> mult_125_G2_A2_18_port, outb =>
mult_125_G2_FS_1_G_n_int_0_4_2_port);
mult_125_G2_FS_1_U1_0_4_2 : nand2 port map( a => n5834, b => n5835, outb =>
mult_125_G2_FS_1_P_0_4_2_port);
mult_125_G2_FS_1_U6_0_4_1 : oai12 port map( b => n5901, c => n5833, a =>
mult_125_G2_FS_1_G_n_int_0_4_0_port, outb =>
mult_125_G2_FS_1_C_1_4_1_port);
mult_125_G2_FS_1_U5_0_4_1 : oai12 port map( b =>
mult_125_G2_FS_1_G_n_int_0_4_0_port, c => n5840, a
=> mult_125_G2_FS_1_G_n_int_0_4_1_port, outb =>
mult_125_G2_FS_1_TEMP_G_0_4_1_port);
mult_125_G2_FS_1_U4_0_4_1 : nand2 port map( a =>
mult_125_G2_FS_1_TEMP_P_0_4_0_port, b =>
mult_125_G2_FS_1_P_0_4_1_port, outb => n5832);
mult_125_G2_FS_1_U3_C_0_4_1 : xor2 port map( a =>
mult_125_G2_FS_1_PG_int_0_4_1_port, b =>
mult_125_G2_FS_1_C_1_4_1_port, outb =>
multiplier_sigs_1_19_port);
mult_125_G2_FS_1_U3_B_0_4_1 : nand2 port map( a =>
mult_125_G2_FS_1_G_n_int_0_4_1_port, b =>
mult_125_G2_FS_1_P_0_4_1_port, outb => n5831);
mult_125_G2_FS_1_U2_0_4_1 : nand2 port map( a => mult_125_G2_A1_17_port, b
=> mult_125_G2_A2_17_port, outb =>
mult_125_G2_FS_1_G_n_int_0_4_1_port);
mult_125_G2_FS_1_U1_0_4_1 : nand2 port map( a => n5829, b => n5830, outb =>
mult_125_G2_FS_1_P_0_4_1_port);
mult_125_G2_FS_1_U3_C_0_4_0 : xor2 port map( a =>
mult_125_G2_FS_1_PG_int_0_4_0_port, b =>
mult_125_G2_FS_1_C_1_4_0_port, outb =>
multiplier_sigs_1_18_port);
mult_125_G2_FS_1_U3_B_0_4_0 : nand2 port map( a =>
mult_125_G2_FS_1_G_n_int_0_4_0_port, b =>
mult_125_G2_FS_1_TEMP_P_0_4_0_port, outb => n5828);
mult_125_G2_FS_1_U2_0_4_0 : nand2 port map( a => mult_125_G2_A1_16_port, b
=> mult_125_G2_A2_16_port, outb =>
mult_125_G2_FS_1_G_n_int_0_4_0_port);
mult_125_G2_FS_1_U1_0_4_0 : nand2 port map( a => n5826, b => n5827, outb =>
mult_125_G2_FS_1_TEMP_P_0_4_0_port);
mult_125_G2_FS_1_U5_0_3_3 : oai12 port map( b => n5824, c => n5825, a =>
mult_125_G2_FS_1_G_n_int_0_3_3_port, outb =>
mult_125_G2_FS_1_G_1_0_3_port);
mult_125_G2_FS_1_U3_C_0_3_3 : xor2 port map( a =>
mult_125_G2_FS_1_PG_int_0_3_3_port, b =>
mult_125_G2_FS_1_C_1_3_3_port, outb =>
multiplier_sigs_1_17_port);
mult_125_G2_FS_1_U3_B_0_3_3 : nand2 port map( a =>
mult_125_G2_FS_1_G_n_int_0_3_3_port, b =>
mult_125_G2_FS_1_P_0_3_3_port, outb => n5823);
mult_125_G2_FS_1_U2_0_3_3 : nand2 port map( a => mult_125_G2_A1_15_port, b
=> mult_125_G2_A2_15_port, outb =>
mult_125_G2_FS_1_G_n_int_0_3_3_port);
mult_125_G2_FS_1_U1_0_3_3 : nand2 port map( a => n5821, b => n5822, outb =>
mult_125_G2_FS_1_P_0_3_3_port);
mult_125_G2_FS_1_U3_B_0_3_2 : nand2 port map( a =>
mult_125_G2_FS_1_G_n_int_0_3_2_port, b =>
mult_125_G2_FS_1_P_0_3_2_port, outb => n5820);
mult_125_G2_FS_1_U2_0_3_2 : nand2 port map( a => mult_125_G2_A1_14_port, b
=> mult_125_G2_A2_14_port, outb =>
mult_125_G2_FS_1_G_n_int_0_3_2_port);
mult_125_G2_FS_1_U1_0_3_2 : nand2 port map( a => n5818, b => n5819, outb =>
mult_125_G2_FS_1_P_0_3_2_port);
mult_125_G2_AN1_15 : inv port map( inb => coefficient_mem_array_1_15_port,
outb => mult_125_G2_A_not_15_port);
mult_125_G2_AN1_14 : inv port map( inb => coefficient_mem_array_1_14_port,
outb => mult_125_G2_A_not_14_port);
mult_125_G2_AN1_13 : inv port map( inb => coefficient_mem_array_1_13_port,
outb => mult_125_G2_A_not_13_port);
mult_125_G2_AN1_12 : inv port map( inb => coefficient_mem_array_1_12_port,
outb => mult_125_G2_A_not_12_port);
mult_125_G2_AN1_11 : inv port map( inb => coefficient_mem_array_1_11_port,
outb => mult_125_G2_A_not_11_port);
mult_125_G2_AN1_10 : inv port map( inb => coefficient_mem_array_1_10_port,
outb => mult_125_G2_A_not_10_port);
mult_125_G2_AN1_9 : inv port map( inb => coefficient_mem_array_1_9_port,
outb => mult_125_G2_A_not_9_port);
mult_125_G2_AN1_8 : inv port map( inb => coefficient_mem_array_1_8_port,
outb => mult_125_G2_A_not_8_port);
mult_125_G2_AN1_7 : inv port map( inb => coefficient_mem_array_1_7_port,
outb => mult_125_G2_A_not_7_port);
mult_125_G2_AN1_6 : inv port map( inb => coefficient_mem_array_1_6_port,
outb => mult_125_G2_A_not_6_port);
mult_125_G2_AN1_5 : inv port map( inb => coefficient_mem_array_1_5_port,
outb => mult_125_G2_A_not_5_port);
mult_125_G2_AN1_4 : inv port map( inb => coefficient_mem_array_1_4_port,
outb => mult_125_G2_A_not_4_port);
mult_125_G2_AN1_3 : inv port map( inb => coefficient_mem_array_1_3_port,
outb => mult_125_G2_A_not_3_port);
mult_125_G2_AN1_2 : inv port map( inb => coefficient_mem_array_1_2_port,
outb => mult_125_G2_A_not_2_port);
mult_125_G2_AN1_1 : inv port map( inb => coefficient_mem_array_1_1_port,
outb => mult_125_G2_A_not_1_port);
mult_125_G2_AN1_0 : inv port map( inb => coefficient_mem_array_1_0_port,
outb => mult_125_G2_A_not_0_port);
mult_125_G2_AN1_15_0 : inv port map( inb => input_sample_mem_15_port, outb
=> mult_125_G2_B_not_15_port);
mult_125_G2_AN1_14_0 : inv port map( inb => input_sample_mem_14_port, outb
=> mult_125_G2_B_not_14_port);
mult_125_G2_AN1_13_0 : inv port map( inb => input_sample_mem_13_port, outb
=> mult_125_G2_B_not_13_port);
mult_125_G2_AN1_12_0 : inv port map( inb => input_sample_mem_12_port, outb
=> mult_125_G2_B_not_12_port);
mult_125_G2_AN1_11_0 : inv port map( inb => input_sample_mem_11_port, outb
=> mult_125_G2_B_not_11_port);
mult_125_G2_AN1_10_0 : inv port map( inb => input_sample_mem_10_port, outb
=> mult_125_G2_B_not_10_port);
mult_125_G2_AN1_9_0 : inv port map( inb => input_sample_mem_9_port, outb =>
mult_125_G2_B_not_9_port);
mult_125_G2_AN1_8_0 : inv port map( inb => input_sample_mem_8_port, outb =>
mult_125_G2_B_not_8_port);
mult_125_G2_AN1_7_0 : inv port map( inb => input_sample_mem_7_port, outb =>
mult_125_G2_B_not_7_port);
mult_125_G2_AN1_6_0 : inv port map( inb => input_sample_mem_6_port, outb =>
mult_125_G2_B_not_6_port);
mult_125_G2_AN1_5_0 : inv port map( inb => input_sample_mem_5_port, outb =>
mult_125_G2_B_not_5_port);
mult_125_G2_AN1_4_0 : inv port map( inb => input_sample_mem_4_port, outb =>
mult_125_G2_B_not_4_port);
mult_125_G2_AN1_3_0 : inv port map( inb => input_sample_mem_3_port, outb =>
mult_125_G2_B_not_3_port);
mult_125_G2_AN1_2_0 : inv port map( inb => input_sample_mem_2_port, outb =>
mult_125_G2_B_not_2_port);
mult_125_G2_AN1_1_0 : inv port map( inb => input_sample_mem_1_port, outb =>
mult_125_G2_B_not_1_port);
mult_125_G2_AN1_0_0 : inv port map( inb => input_sample_mem_0_port, outb =>
mult_125_G2_B_not_0_port);
mult_125_G2_AN1_15_15 : nor2 port map( a => mult_125_G2_A_not_15_port, b =>
mult_125_G2_B_not_15_port, outb =>
mult_125_G2_ab_15_15_port);
mult_125_G2_AN3_15_14 : nor2 port map( a => mult_125_G2_A_not_15_port, b =>
mult_125_G2_B_notx_14_port, outb =>
mult_125_G2_ab_15_14_port);
mult_125_G2_AN3_15_13 : nor2 port map( a => mult_125_G2_A_not_15_port, b =>
mult_125_G2_B_notx_13_port, outb =>
mult_125_G2_ab_15_13_port);
mult_125_G2_AN3_15_12 : nor2 port map( a => mult_125_G2_A_not_15_port, b =>
mult_125_G2_B_notx_12_port, outb =>
mult_125_G2_ab_15_12_port);
mult_125_G2_AN3_15_11 : nor2 port map( a => mult_125_G2_A_not_15_port, b =>
mult_125_G2_B_notx_11_port, outb =>
mult_125_G2_ab_15_11_port);
mult_125_G2_AN3_15_10 : nor2 port map( a => mult_125_G2_A_not_15_port, b =>
mult_125_G2_B_notx_10_port, outb =>
mult_125_G2_ab_15_10_port);
mult_125_G2_AN3_15_9 : nor2 port map( a => mult_125_G2_A_not_15_port, b =>
mult_125_G2_B_notx_9_port, outb =>
mult_125_G2_ab_15_9_port);
mult_125_G2_AN3_15_8 : nor2 port map( a => mult_125_G2_A_not_15_port, b =>
mult_125_G2_B_notx_8_port, outb =>
mult_125_G2_ab_15_8_port);
mult_125_G2_AN3_15_7 : nor2 port map( a => mult_125_G2_A_not_15_port, b =>
mult_125_G2_B_notx_7_port, outb =>
mult_125_G2_ab_15_7_port);
mult_125_G2_AN3_15_6 : nor2 port map( a => mult_125_G2_A_not_15_port, b =>
mult_125_G2_B_notx_6_port, outb =>
mult_125_G2_ab_15_6_port);
mult_125_G2_AN3_15_5 : nor2 port map( a => mult_125_G2_A_not_15_port, b =>
mult_125_G2_B_notx_5_port, outb =>
mult_125_G2_ab_15_5_port);
mult_125_G2_AN3_15_4 : nor2 port map( a => mult_125_G2_A_not_15_port, b =>
mult_125_G2_B_notx_4_port, outb =>
mult_125_G2_ab_15_4_port);
mult_125_G2_AN3_15_3 : nor2 port map( a => mult_125_G2_A_not_15_port, b =>
mult_125_G2_B_notx_3_port, outb =>
mult_125_G2_ab_15_3_port);
mult_125_G2_AN3_15_2 : nor2 port map( a => mult_125_G2_A_not_15_port, b =>
mult_125_G2_B_notx_2_port, outb =>
mult_125_G2_ab_15_2_port);
mult_125_G2_AN3_15_1 : nor2 port map( a => mult_125_G2_A_not_15_port, b =>
mult_125_G2_B_notx_1_port, outb =>
mult_125_G2_ab_15_1_port);
mult_125_G2_AN3_15_0 : nor2 port map( a => mult_125_G2_A_not_15_port, b =>
mult_125_G2_B_notx_0_port, outb =>
mult_125_G2_ab_15_0_port);
mult_125_G2_AN2_14_15 : nor2 port map( a => mult_125_G2_A_notx_14_port, b =>
mult_125_G2_B_not_15_port, outb =>
mult_125_G2_ab_14_15_port);
mult_125_G2_AN1_14_14 : nor2 port map( a => mult_125_G2_A_not_14_port, b =>
mult_125_G2_B_not_14_port, outb =>
mult_125_G2_ab_14_14_port);
mult_125_G2_AN1_14_13 : nor2 port map( a => mult_125_G2_A_not_14_port, b =>
mult_125_G2_B_not_13_port, outb =>
mult_125_G2_ab_14_13_port);
mult_125_G2_AN1_14_12 : nor2 port map( a => mult_125_G2_A_not_14_port, b =>
mult_125_G2_B_not_12_port, outb =>
mult_125_G2_ab_14_12_port);
mult_125_G2_AN1_14_11 : nor2 port map( a => mult_125_G2_A_not_14_port, b =>
mult_125_G2_B_not_11_port, outb =>
mult_125_G2_ab_14_11_port);
mult_125_G2_AN1_14_10 : nor2 port map( a => mult_125_G2_A_not_14_port, b =>
mult_125_G2_B_not_10_port, outb =>
mult_125_G2_ab_14_10_port);
mult_125_G2_AN1_14_9 : nor2 port map( a => mult_125_G2_A_not_14_port, b =>
mult_125_G2_B_not_9_port, outb =>
mult_125_G2_ab_14_9_port);
mult_125_G2_AN1_14_8 : nor2 port map( a => mult_125_G2_A_not_14_port, b =>
mult_125_G2_B_not_8_port, outb =>
mult_125_G2_ab_14_8_port);
mult_125_G2_AN1_14_7 : nor2 port map( a => mult_125_G2_A_not_14_port, b =>
mult_125_G2_B_not_7_port, outb =>
mult_125_G2_ab_14_7_port);
mult_125_G2_AN1_14_6 : nor2 port map( a => mult_125_G2_A_not_14_port, b =>
mult_125_G2_B_not_6_port, outb =>
mult_125_G2_ab_14_6_port);
mult_125_G2_AN1_14_5 : nor2 port map( a => mult_125_G2_A_not_14_port, b =>
mult_125_G2_B_not_5_port, outb =>
mult_125_G2_ab_14_5_port);
mult_125_G2_AN1_14_4 : nor2 port map( a => mult_125_G2_A_not_14_port, b =>
mult_125_G2_B_not_4_port, outb =>
mult_125_G2_ab_14_4_port);
mult_125_G2_AN1_14_3 : nor2 port map( a => mult_125_G2_A_not_14_port, b =>
mult_125_G2_B_not_3_port, outb =>
mult_125_G2_ab_14_3_port);
mult_125_G2_AN1_14_2 : nor2 port map( a => mult_125_G2_A_not_14_port, b =>
mult_125_G2_B_not_2_port, outb =>
mult_125_G2_ab_14_2_port);
mult_125_G2_AN1_14_1 : nor2 port map( a => mult_125_G2_A_not_14_port, b =>
mult_125_G2_B_not_1_port, outb =>
mult_125_G2_ab_14_1_port);
mult_125_G2_AN1_14_0_0 : nor2 port map( a => mult_125_G2_A_not_14_port, b =>
mult_125_G2_B_not_0_port, outb =>
mult_125_G2_ab_14_0_port);
mult_125_G2_AN2_13_15 : nor2 port map( a => mult_125_G2_A_notx_13_port, b =>
mult_125_G2_B_not_15_port, outb =>
mult_125_G2_ab_13_15_port);
mult_125_G2_AN1_13_14 : nor2 port map( a => mult_125_G2_A_not_13_port, b =>
mult_125_G2_B_not_14_port, outb =>
mult_125_G2_ab_13_14_port);
mult_125_G2_AN1_13_13 : nor2 port map( a => mult_125_G2_A_not_13_port, b =>
mult_125_G2_B_not_13_port, outb =>
mult_125_G2_ab_13_13_port);
mult_125_G2_AN1_13_12 : nor2 port map( a => mult_125_G2_A_not_13_port, b =>
mult_125_G2_B_not_12_port, outb =>
mult_125_G2_ab_13_12_port);
mult_125_G2_AN1_13_11 : nor2 port map( a => mult_125_G2_A_not_13_port, b =>
mult_125_G2_B_not_11_port, outb =>
mult_125_G2_ab_13_11_port);
mult_125_G2_AN1_13_10 : nor2 port map( a => mult_125_G2_A_not_13_port, b =>
mult_125_G2_B_not_10_port, outb =>
mult_125_G2_ab_13_10_port);
mult_125_G2_AN1_13_9 : nor2 port map( a => mult_125_G2_A_not_13_port, b =>
mult_125_G2_B_not_9_port, outb =>
mult_125_G2_ab_13_9_port);
mult_125_G2_AN1_13_8 : nor2 port map( a => mult_125_G2_A_not_13_port, b =>
mult_125_G2_B_not_8_port, outb =>
mult_125_G2_ab_13_8_port);
mult_125_G2_AN1_13_7 : nor2 port map( a => mult_125_G2_A_not_13_port, b =>
mult_125_G2_B_not_7_port, outb =>
mult_125_G2_ab_13_7_port);
mult_125_G2_AN1_13_6 : nor2 port map( a => mult_125_G2_A_not_13_port, b =>
mult_125_G2_B_not_6_port, outb =>
mult_125_G2_ab_13_6_port);
mult_125_G2_AN1_13_5 : nor2 port map( a => mult_125_G2_A_not_13_port, b =>
mult_125_G2_B_not_5_port, outb =>
mult_125_G2_ab_13_5_port);
mult_125_G2_AN1_13_4 : nor2 port map( a => mult_125_G2_A_not_13_port, b =>
mult_125_G2_B_not_4_port, outb =>
mult_125_G2_ab_13_4_port);
mult_125_G2_AN1_13_3 : nor2 port map( a => mult_125_G2_A_not_13_port, b =>
mult_125_G2_B_not_3_port, outb =>
mult_125_G2_ab_13_3_port);
mult_125_G2_AN1_13_2 : nor2 port map( a => mult_125_G2_A_not_13_port, b =>
mult_125_G2_B_not_2_port, outb =>
mult_125_G2_ab_13_2_port);
mult_125_G2_AN1_13_1 : nor2 port map( a => mult_125_G2_A_not_13_port, b =>
mult_125_G2_B_not_1_port, outb =>
mult_125_G2_ab_13_1_port);
mult_125_G2_AN1_13_0_0 : nor2 port map( a => mult_125_G2_A_not_13_port, b =>
mult_125_G2_B_not_0_port, outb =>
mult_125_G2_ab_13_0_port);
mult_125_G2_AN2_12_15 : nor2 port map( a => mult_125_G2_A_notx_12_port, b =>
mult_125_G2_B_not_15_port, outb =>
mult_125_G2_ab_12_15_port);
mult_125_G2_AN1_12_14 : nor2 port map( a => mult_125_G2_A_not_12_port, b =>
mult_125_G2_B_not_14_port, outb =>
mult_125_G2_ab_12_14_port);
mult_125_G2_AN1_12_13 : nor2 port map( a => mult_125_G2_A_not_12_port, b =>
mult_125_G2_B_not_13_port, outb =>
mult_125_G2_ab_12_13_port);
mult_125_G2_AN1_12_12 : nor2 port map( a => mult_125_G2_A_not_12_port, b =>
mult_125_G2_B_not_12_port, outb =>
mult_125_G2_ab_12_12_port);
mult_125_G2_AN1_12_11 : nor2 port map( a => mult_125_G2_A_not_12_port, b =>
mult_125_G2_B_not_11_port, outb =>
mult_125_G2_ab_12_11_port);
mult_125_G2_AN1_12_10 : nor2 port map( a => mult_125_G2_A_not_12_port, b =>
mult_125_G2_B_not_10_port, outb =>
mult_125_G2_ab_12_10_port);
mult_125_G2_AN1_12_9 : nor2 port map( a => mult_125_G2_A_not_12_port, b =>
mult_125_G2_B_not_9_port, outb =>
mult_125_G2_ab_12_9_port);
mult_125_G2_AN1_12_8 : nor2 port map( a => mult_125_G2_A_not_12_port, b =>
mult_125_G2_B_not_8_port, outb =>
mult_125_G2_ab_12_8_port);
mult_125_G2_AN1_12_7 : nor2 port map( a => mult_125_G2_A_not_12_port, b =>
mult_125_G2_B_not_7_port, outb =>
mult_125_G2_ab_12_7_port);
mult_125_G2_AN1_12_6 : nor2 port map( a => mult_125_G2_A_not_12_port, b =>
mult_125_G2_B_not_6_port, outb =>
mult_125_G2_ab_12_6_port);
mult_125_G2_AN1_12_5 : nor2 port map( a => mult_125_G2_A_not_12_port, b =>
mult_125_G2_B_not_5_port, outb =>
mult_125_G2_ab_12_5_port);
mult_125_G2_AN1_12_4 : nor2 port map( a => mult_125_G2_A_not_12_port, b =>
mult_125_G2_B_not_4_port, outb =>
mult_125_G2_ab_12_4_port);
mult_125_G2_AN1_12_3 : nor2 port map( a => mult_125_G2_A_not_12_port, b =>
mult_125_G2_B_not_3_port, outb =>
mult_125_G2_ab_12_3_port);
mult_125_G2_AN1_12_2 : nor2 port map( a => mult_125_G2_A_not_12_port, b =>
mult_125_G2_B_not_2_port, outb =>
mult_125_G2_ab_12_2_port);
mult_125_G2_AN1_12_1 : nor2 port map( a => mult_125_G2_A_not_12_port, b =>
mult_125_G2_B_not_1_port, outb =>
mult_125_G2_ab_12_1_port);
mult_125_G2_AN1_12_0_0 : nor2 port map( a => mult_125_G2_A_not_12_port, b =>
mult_125_G2_B_not_0_port, outb =>
mult_125_G2_ab_12_0_port);
mult_125_G2_AN2_11_15 : nor2 port map( a => mult_125_G2_A_notx_11_port, b =>
mult_125_G2_B_not_15_port, outb =>
mult_125_G2_ab_11_15_port);
mult_125_G2_AN1_11_14 : nor2 port map( a => mult_125_G2_A_not_11_port, b =>
mult_125_G2_B_not_14_port, outb =>
mult_125_G2_ab_11_14_port);
mult_125_G2_AN1_11_13 : nor2 port map( a => mult_125_G2_A_not_11_port, b =>
mult_125_G2_B_not_13_port, outb =>
mult_125_G2_ab_11_13_port);
mult_125_G2_AN1_11_12 : nor2 port map( a => mult_125_G2_A_not_11_port, b =>
mult_125_G2_B_not_12_port, outb =>
mult_125_G2_ab_11_12_port);
mult_125_G2_AN1_11_11 : nor2 port map( a => mult_125_G2_A_not_11_port, b =>
mult_125_G2_B_not_11_port, outb =>
mult_125_G2_ab_11_11_port);
mult_125_G2_AN1_11_10 : nor2 port map( a => mult_125_G2_A_not_11_port, b =>
mult_125_G2_B_not_10_port, outb =>
mult_125_G2_ab_11_10_port);
mult_125_G2_AN1_11_9 : nor2 port map( a => mult_125_G2_A_not_11_port, b =>
mult_125_G2_B_not_9_port, outb =>
mult_125_G2_ab_11_9_port);
mult_125_G2_AN1_11_8 : nor2 port map( a => mult_125_G2_A_not_11_port, b =>
mult_125_G2_B_not_8_port, outb =>
mult_125_G2_ab_11_8_port);
mult_125_G2_AN1_11_7 : nor2 port map( a => mult_125_G2_A_not_11_port, b =>
mult_125_G2_B_not_7_port, outb =>
mult_125_G2_ab_11_7_port);
mult_125_G2_AN1_11_6 : nor2 port map( a => mult_125_G2_A_not_11_port, b =>
mult_125_G2_B_not_6_port, outb =>
mult_125_G2_ab_11_6_port);
mult_125_G2_AN1_11_5 : nor2 port map( a => mult_125_G2_A_not_11_port, b =>
mult_125_G2_B_not_5_port, outb =>
mult_125_G2_ab_11_5_port);
mult_125_G2_AN1_11_4 : nor2 port map( a => mult_125_G2_A_not_11_port, b =>
mult_125_G2_B_not_4_port, outb =>
mult_125_G2_ab_11_4_port);
mult_125_G2_AN1_11_3 : nor2 port map( a => mult_125_G2_A_not_11_port, b =>
mult_125_G2_B_not_3_port, outb =>
mult_125_G2_ab_11_3_port);
mult_125_G2_AN1_11_2 : nor2 port map( a => mult_125_G2_A_not_11_port, b =>
mult_125_G2_B_not_2_port, outb =>
mult_125_G2_ab_11_2_port);
mult_125_G2_AN1_11_1 : nor2 port map( a => mult_125_G2_A_not_11_port, b =>
mult_125_G2_B_not_1_port, outb =>
mult_125_G2_ab_11_1_port);
mult_125_G2_AN1_11_0_0 : nor2 port map( a => mult_125_G2_A_not_11_port, b =>
mult_125_G2_B_not_0_port, outb =>
mult_125_G2_ab_11_0_port);
mult_125_G2_AN2_10_15 : nor2 port map( a => mult_125_G2_A_notx_10_port, b =>
mult_125_G2_B_not_15_port, outb =>
mult_125_G2_ab_10_15_port);
mult_125_G2_AN1_10_14 : nor2 port map( a => mult_125_G2_A_not_10_port, b =>
mult_125_G2_B_not_14_port, outb =>
mult_125_G2_ab_10_14_port);
mult_125_G2_AN1_10_13 : nor2 port map( a => mult_125_G2_A_not_10_port, b =>
mult_125_G2_B_not_13_port, outb =>
mult_125_G2_ab_10_13_port);
mult_125_G2_AN1_10_12 : nor2 port map( a => mult_125_G2_A_not_10_port, b =>
mult_125_G2_B_not_12_port, outb =>
mult_125_G2_ab_10_12_port);
mult_125_G2_AN1_10_11 : nor2 port map( a => mult_125_G2_A_not_10_port, b =>
mult_125_G2_B_not_11_port, outb =>
mult_125_G2_ab_10_11_port);
mult_125_G2_AN1_10_10 : nor2 port map( a => mult_125_G2_A_not_10_port, b =>
mult_125_G2_B_not_10_port, outb =>
mult_125_G2_ab_10_10_port);
mult_125_G2_AN1_10_9 : nor2 port map( a => mult_125_G2_A_not_10_port, b =>
mult_125_G2_B_not_9_port, outb =>
mult_125_G2_ab_10_9_port);
mult_125_G2_AN1_10_8 : nor2 port map( a => mult_125_G2_A_not_10_port, b =>
mult_125_G2_B_not_8_port, outb =>
mult_125_G2_ab_10_8_port);
mult_125_G2_AN1_10_7 : nor2 port map( a => mult_125_G2_A_not_10_port, b =>
mult_125_G2_B_not_7_port, outb =>
mult_125_G2_ab_10_7_port);
mult_125_G2_AN1_10_6 : nor2 port map( a => mult_125_G2_A_not_10_port, b =>
mult_125_G2_B_not_6_port, outb =>
mult_125_G2_ab_10_6_port);
mult_125_G2_AN1_10_5 : nor2 port map( a => mult_125_G2_A_not_10_port, b =>
mult_125_G2_B_not_5_port, outb =>
mult_125_G2_ab_10_5_port);
mult_125_G2_AN1_10_4 : nor2 port map( a => mult_125_G2_A_not_10_port, b =>
mult_125_G2_B_not_4_port, outb =>
mult_125_G2_ab_10_4_port);
mult_125_G2_AN1_10_3 : nor2 port map( a => mult_125_G2_A_not_10_port, b =>
mult_125_G2_B_not_3_port, outb =>
mult_125_G2_ab_10_3_port);
mult_125_G2_AN1_10_2 : nor2 port map( a => mult_125_G2_A_not_10_port, b =>
mult_125_G2_B_not_2_port, outb =>
mult_125_G2_ab_10_2_port);
mult_125_G2_AN1_10_1 : nor2 port map( a => mult_125_G2_A_not_10_port, b =>
mult_125_G2_B_not_1_port, outb =>
mult_125_G2_ab_10_1_port);
mult_125_G2_AN1_10_0_0 : nor2 port map( a => mult_125_G2_A_not_10_port, b =>
mult_125_G2_B_not_0_port, outb =>
mult_125_G2_ab_10_0_port);
mult_125_G2_AN2_9_15 : nor2 port map( a => mult_125_G2_A_notx_9_port, b =>
mult_125_G2_B_not_15_port, outb =>
mult_125_G2_ab_9_15_port);
mult_125_G2_AN1_9_14 : nor2 port map( a => mult_125_G2_A_not_9_port, b =>
mult_125_G2_B_not_14_port, outb =>
mult_125_G2_ab_9_14_port);
mult_125_G2_AN1_9_13 : nor2 port map( a => mult_125_G2_A_not_9_port, b =>
mult_125_G2_B_not_13_port, outb =>
mult_125_G2_ab_9_13_port);
mult_125_G2_AN1_9_12 : nor2 port map( a => mult_125_G2_A_not_9_port, b =>
mult_125_G2_B_not_12_port, outb =>
mult_125_G2_ab_9_12_port);
mult_125_G2_AN1_9_11 : nor2 port map( a => mult_125_G2_A_not_9_port, b =>
mult_125_G2_B_not_11_port, outb =>
mult_125_G2_ab_9_11_port);
mult_125_G2_AN1_9_10 : nor2 port map( a => mult_125_G2_A_not_9_port, b =>
mult_125_G2_B_not_10_port, outb =>
mult_125_G2_ab_9_10_port);
mult_125_G2_AN1_9_9 : nor2 port map( a => mult_125_G2_A_not_9_port, b =>
mult_125_G2_B_not_9_port, outb =>
mult_125_G2_ab_9_9_port);
mult_125_G2_AN1_9_8 : nor2 port map( a => mult_125_G2_A_not_9_port, b =>
mult_125_G2_B_not_8_port, outb =>
mult_125_G2_ab_9_8_port);
mult_125_G2_AN1_9_7 : nor2 port map( a => mult_125_G2_A_not_9_port, b =>
mult_125_G2_B_not_7_port, outb =>
mult_125_G2_ab_9_7_port);
mult_125_G2_AN1_9_6 : nor2 port map( a => mult_125_G2_A_not_9_port, b =>
mult_125_G2_B_not_6_port, outb =>
mult_125_G2_ab_9_6_port);
mult_125_G2_AN1_9_5 : nor2 port map( a => mult_125_G2_A_not_9_port, b =>
mult_125_G2_B_not_5_port, outb =>
mult_125_G2_ab_9_5_port);
mult_125_G2_AN1_9_4 : nor2 port map( a => mult_125_G2_A_not_9_port, b =>
mult_125_G2_B_not_4_port, outb =>
mult_125_G2_ab_9_4_port);
mult_125_G2_AN1_9_3 : nor2 port map( a => mult_125_G2_A_not_9_port, b =>
mult_125_G2_B_not_3_port, outb =>
mult_125_G2_ab_9_3_port);
mult_125_G2_AN1_9_2 : nor2 port map( a => mult_125_G2_A_not_9_port, b =>
mult_125_G2_B_not_2_port, outb =>
mult_125_G2_ab_9_2_port);
mult_125_G2_AN1_9_1 : nor2 port map( a => mult_125_G2_A_not_9_port, b =>
mult_125_G2_B_not_1_port, outb =>
mult_125_G2_ab_9_1_port);
mult_125_G2_AN1_9_0_0 : nor2 port map( a => mult_125_G2_A_not_9_port, b =>
mult_125_G2_B_not_0_port, outb =>
mult_125_G2_ab_9_0_port);
mult_125_G2_AN2_8_15 : nor2 port map( a => mult_125_G2_A_notx_8_port, b =>
mult_125_G2_B_not_15_port, outb =>
mult_125_G2_ab_8_15_port);
mult_125_G2_AN1_8_14 : nor2 port map( a => mult_125_G2_A_not_8_port, b =>
mult_125_G2_B_not_14_port, outb =>
mult_125_G2_ab_8_14_port);
mult_125_G2_AN1_8_13 : nor2 port map( a => mult_125_G2_A_not_8_port, b =>
mult_125_G2_B_not_13_port, outb =>
mult_125_G2_ab_8_13_port);
mult_125_G2_AN1_8_12 : nor2 port map( a => mult_125_G2_A_not_8_port, b =>
mult_125_G2_B_not_12_port, outb =>
mult_125_G2_ab_8_12_port);
mult_125_G2_AN1_8_11 : nor2 port map( a => mult_125_G2_A_not_8_port, b =>
mult_125_G2_B_not_11_port, outb =>
mult_125_G2_ab_8_11_port);
mult_125_G2_AN1_8_10 : nor2 port map( a => mult_125_G2_A_not_8_port, b =>
mult_125_G2_B_not_10_port, outb =>
mult_125_G2_ab_8_10_port);
mult_125_G2_AN1_8_9 : nor2 port map( a => mult_125_G2_A_not_8_port, b =>
mult_125_G2_B_not_9_port, outb =>
mult_125_G2_ab_8_9_port);
mult_125_G2_AN1_8_8 : nor2 port map( a => mult_125_G2_A_not_8_port, b =>
mult_125_G2_B_not_8_port, outb =>
mult_125_G2_ab_8_8_port);
mult_125_G2_AN1_8_7 : nor2 port map( a => mult_125_G2_A_not_8_port, b =>
mult_125_G2_B_not_7_port, outb =>
mult_125_G2_ab_8_7_port);
mult_125_G2_AN1_8_6 : nor2 port map( a => mult_125_G2_A_not_8_port, b =>
mult_125_G2_B_not_6_port, outb =>
mult_125_G2_ab_8_6_port);
mult_125_G2_AN1_8_5 : nor2 port map( a => mult_125_G2_A_not_8_port, b =>
mult_125_G2_B_not_5_port, outb =>
mult_125_G2_ab_8_5_port);
mult_125_G2_AN1_8_4 : nor2 port map( a => mult_125_G2_A_not_8_port, b =>
mult_125_G2_B_not_4_port, outb =>
mult_125_G2_ab_8_4_port);
mult_125_G2_AN1_8_3 : nor2 port map( a => mult_125_G2_A_not_8_port, b =>
mult_125_G2_B_not_3_port, outb =>
mult_125_G2_ab_8_3_port);
mult_125_G2_AN1_8_2 : nor2 port map( a => mult_125_G2_A_not_8_port, b =>
mult_125_G2_B_not_2_port, outb =>
mult_125_G2_ab_8_2_port);
mult_125_G2_AN1_8_1 : nor2 port map( a => mult_125_G2_A_not_8_port, b =>
mult_125_G2_B_not_1_port, outb =>
mult_125_G2_ab_8_1_port);
mult_125_G2_AN1_8_0_0 : nor2 port map( a => mult_125_G2_A_not_8_port, b =>
mult_125_G2_B_not_0_port, outb =>
mult_125_G2_ab_8_0_port);
mult_125_G2_AN2_7_15 : nor2 port map( a => mult_125_G2_A_notx_7_port, b =>
mult_125_G2_B_not_15_port, outb =>
mult_125_G2_ab_7_15_port);
mult_125_G2_AN1_7_14 : nor2 port map( a => mult_125_G2_A_not_7_port, b =>
mult_125_G2_B_not_14_port, outb =>
mult_125_G2_ab_7_14_port);
mult_125_G2_AN1_7_13 : nor2 port map( a => mult_125_G2_A_not_7_port, b =>
mult_125_G2_B_not_13_port, outb =>
mult_125_G2_ab_7_13_port);
mult_125_G2_AN1_7_12 : nor2 port map( a => mult_125_G2_A_not_7_port, b =>
mult_125_G2_B_not_12_port, outb =>
mult_125_G2_ab_7_12_port);
mult_125_G2_AN1_7_11 : nor2 port map( a => mult_125_G2_A_not_7_port, b =>
mult_125_G2_B_not_11_port, outb =>
mult_125_G2_ab_7_11_port);
mult_125_G2_AN1_7_10 : nor2 port map( a => mult_125_G2_A_not_7_port, b =>
mult_125_G2_B_not_10_port, outb =>
mult_125_G2_ab_7_10_port);
mult_125_G2_AN1_7_9 : nor2 port map( a => mult_125_G2_A_not_7_port, b =>
mult_125_G2_B_not_9_port, outb =>
mult_125_G2_ab_7_9_port);
mult_125_G2_AN1_7_8 : nor2 port map( a => mult_125_G2_A_not_7_port, b =>
mult_125_G2_B_not_8_port, outb =>
mult_125_G2_ab_7_8_port);
mult_125_G2_AN1_7_7 : nor2 port map( a => mult_125_G2_A_not_7_port, b =>
mult_125_G2_B_not_7_port, outb =>
mult_125_G2_ab_7_7_port);
mult_125_G2_AN1_7_6 : nor2 port map( a => mult_125_G2_A_not_7_port, b =>
mult_125_G2_B_not_6_port, outb =>
mult_125_G2_ab_7_6_port);
mult_125_G2_AN1_7_5 : nor2 port map( a => mult_125_G2_A_not_7_port, b =>
mult_125_G2_B_not_5_port, outb =>
mult_125_G2_ab_7_5_port);
mult_125_G2_AN1_7_4 : nor2 port map( a => mult_125_G2_A_not_7_port, b =>
mult_125_G2_B_not_4_port, outb =>
mult_125_G2_ab_7_4_port);
mult_125_G2_AN1_7_3 : nor2 port map( a => mult_125_G2_A_not_7_port, b =>
mult_125_G2_B_not_3_port, outb =>
mult_125_G2_ab_7_3_port);
mult_125_G2_AN1_7_2 : nor2 port map( a => mult_125_G2_A_not_7_port, b =>
mult_125_G2_B_not_2_port, outb =>
mult_125_G2_ab_7_2_port);
mult_125_G2_AN1_7_1 : nor2 port map( a => mult_125_G2_A_not_7_port, b =>
mult_125_G2_B_not_1_port, outb =>
mult_125_G2_ab_7_1_port);
mult_125_G2_AN1_7_0_0 : nor2 port map( a => mult_125_G2_A_not_7_port, b =>
mult_125_G2_B_not_0_port, outb =>
mult_125_G2_ab_7_0_port);
mult_125_G2_AN2_6_15 : nor2 port map( a => mult_125_G2_A_notx_6_port, b =>
mult_125_G2_B_not_15_port, outb =>
mult_125_G2_ab_6_15_port);
mult_125_G2_AN1_6_14 : nor2 port map( a => mult_125_G2_A_not_6_port, b =>
mult_125_G2_B_not_14_port, outb =>
mult_125_G2_ab_6_14_port);
mult_125_G2_AN1_6_13 : nor2 port map( a => mult_125_G2_A_not_6_port, b =>
mult_125_G2_B_not_13_port, outb =>
mult_125_G2_ab_6_13_port);
mult_125_G2_AN1_6_12 : nor2 port map( a => mult_125_G2_A_not_6_port, b =>
mult_125_G2_B_not_12_port, outb =>
mult_125_G2_ab_6_12_port);
mult_125_G2_AN1_6_11 : nor2 port map( a => mult_125_G2_A_not_6_port, b =>
mult_125_G2_B_not_11_port, outb =>
mult_125_G2_ab_6_11_port);
mult_125_G2_AN1_6_10 : nor2 port map( a => mult_125_G2_A_not_6_port, b =>
mult_125_G2_B_not_10_port, outb =>
mult_125_G2_ab_6_10_port);
mult_125_G2_AN1_6_9 : nor2 port map( a => mult_125_G2_A_not_6_port, b =>
mult_125_G2_B_not_9_port, outb =>
mult_125_G2_ab_6_9_port);
mult_125_G2_AN1_6_8 : nor2 port map( a => mult_125_G2_A_not_6_port, b =>
mult_125_G2_B_not_8_port, outb =>
mult_125_G2_ab_6_8_port);
mult_125_G2_AN1_6_7 : nor2 port map( a => mult_125_G2_A_not_6_port, b =>
mult_125_G2_B_not_7_port, outb =>
mult_125_G2_ab_6_7_port);
mult_125_G2_AN1_6_6 : nor2 port map( a => mult_125_G2_A_not_6_port, b =>
mult_125_G2_B_not_6_port, outb =>
mult_125_G2_ab_6_6_port);
mult_125_G2_AN1_6_5 : nor2 port map( a => mult_125_G2_A_not_6_port, b =>
mult_125_G2_B_not_5_port, outb =>
mult_125_G2_ab_6_5_port);
mult_125_G2_AN1_6_4 : nor2 port map( a => mult_125_G2_A_not_6_port, b =>
mult_125_G2_B_not_4_port, outb =>
mult_125_G2_ab_6_4_port);
mult_125_G2_AN1_6_3 : nor2 port map( a => mult_125_G2_A_not_6_port, b =>
mult_125_G2_B_not_3_port, outb =>
mult_125_G2_ab_6_3_port);
mult_125_G2_AN1_6_2 : nor2 port map( a => mult_125_G2_A_not_6_port, b =>
mult_125_G2_B_not_2_port, outb =>
mult_125_G2_ab_6_2_port);
mult_125_G2_AN1_6_1 : nor2 port map( a => mult_125_G2_A_not_6_port, b =>
mult_125_G2_B_not_1_port, outb =>
mult_125_G2_ab_6_1_port);
mult_125_G2_AN1_6_0_0 : nor2 port map( a => mult_125_G2_A_not_6_port, b =>
mult_125_G2_B_not_0_port, outb =>
mult_125_G2_ab_6_0_port);
mult_125_G2_AN2_5_15 : nor2 port map( a => mult_125_G2_A_notx_5_port, b =>
mult_125_G2_B_not_15_port, outb =>
mult_125_G2_ab_5_15_port);
mult_125_G2_AN1_5_14 : nor2 port map( a => mult_125_G2_A_not_5_port, b =>
mult_125_G2_B_not_14_port, outb =>
mult_125_G2_ab_5_14_port);
mult_125_G2_AN1_5_13 : nor2 port map( a => mult_125_G2_A_not_5_port, b =>
mult_125_G2_B_not_13_port, outb =>
mult_125_G2_ab_5_13_port);
mult_125_G2_AN1_5_12 : nor2 port map( a => mult_125_G2_A_not_5_port, b =>
mult_125_G2_B_not_12_port, outb =>
mult_125_G2_ab_5_12_port);
mult_125_G2_AN1_5_11 : nor2 port map( a => mult_125_G2_A_not_5_port, b =>
mult_125_G2_B_not_11_port, outb =>
mult_125_G2_ab_5_11_port);
mult_125_G2_AN1_5_10 : nor2 port map( a => mult_125_G2_A_not_5_port, b =>
mult_125_G2_B_not_10_port, outb =>
mult_125_G2_ab_5_10_port);
mult_125_G2_AN1_5_9 : nor2 port map( a => mult_125_G2_A_not_5_port, b =>
mult_125_G2_B_not_9_port, outb =>
mult_125_G2_ab_5_9_port);
mult_125_G2_AN1_5_8 : nor2 port map( a => mult_125_G2_A_not_5_port, b =>
mult_125_G2_B_not_8_port, outb =>
mult_125_G2_ab_5_8_port);
mult_125_G2_AN1_5_7 : nor2 port map( a => mult_125_G2_A_not_5_port, b =>
mult_125_G2_B_not_7_port, outb =>
mult_125_G2_ab_5_7_port);
mult_125_G2_AN1_5_6 : nor2 port map( a => mult_125_G2_A_not_5_port, b =>
mult_125_G2_B_not_6_port, outb =>
mult_125_G2_ab_5_6_port);
mult_125_G2_AN1_5_5 : nor2 port map( a => mult_125_G2_A_not_5_port, b =>
mult_125_G2_B_not_5_port, outb =>
mult_125_G2_ab_5_5_port);
mult_125_G2_AN1_5_4 : nor2 port map( a => mult_125_G2_A_not_5_port, b =>
mult_125_G2_B_not_4_port, outb =>
mult_125_G2_ab_5_4_port);
mult_125_G2_AN1_5_3 : nor2 port map( a => mult_125_G2_A_not_5_port, b =>
mult_125_G2_B_not_3_port, outb =>
mult_125_G2_ab_5_3_port);
mult_125_G2_AN1_5_2 : nor2 port map( a => mult_125_G2_A_not_5_port, b =>
mult_125_G2_B_not_2_port, outb =>
mult_125_G2_ab_5_2_port);
mult_125_G2_AN1_5_1 : nor2 port map( a => mult_125_G2_A_not_5_port, b =>
mult_125_G2_B_not_1_port, outb =>
mult_125_G2_ab_5_1_port);
mult_125_G2_AN1_5_0_0 : nor2 port map( a => mult_125_G2_A_not_5_port, b =>
mult_125_G2_B_not_0_port, outb =>
mult_125_G2_ab_5_0_port);
mult_125_G2_AN2_4_15 : nor2 port map( a => mult_125_G2_A_notx_4_port, b =>
mult_125_G2_B_not_15_port, outb =>
mult_125_G2_ab_4_15_port);
mult_125_G2_AN1_4_14 : nor2 port map( a => mult_125_G2_A_not_4_port, b =>
mult_125_G2_B_not_14_port, outb =>
mult_125_G2_ab_4_14_port);
mult_125_G2_AN1_4_13 : nor2 port map( a => mult_125_G2_A_not_4_port, b =>
mult_125_G2_B_not_13_port, outb =>
mult_125_G2_ab_4_13_port);
mult_125_G2_AN1_4_12 : nor2 port map( a => mult_125_G2_A_not_4_port, b =>
mult_125_G2_B_not_12_port, outb =>
mult_125_G2_ab_4_12_port);
mult_125_G2_AN1_4_11 : nor2 port map( a => mult_125_G2_A_not_4_port, b =>
mult_125_G2_B_not_11_port, outb =>
mult_125_G2_ab_4_11_port);
mult_125_G2_AN1_4_10 : nor2 port map( a => mult_125_G2_A_not_4_port, b =>
mult_125_G2_B_not_10_port, outb =>
mult_125_G2_ab_4_10_port);
mult_125_G2_AN1_4_9 : nor2 port map( a => mult_125_G2_A_not_4_port, b =>
mult_125_G2_B_not_9_port, outb =>
mult_125_G2_ab_4_9_port);
mult_125_G2_AN1_4_8 : nor2 port map( a => mult_125_G2_A_not_4_port, b =>
mult_125_G2_B_not_8_port, outb =>
mult_125_G2_ab_4_8_port);
mult_125_G2_AN1_4_7 : nor2 port map( a => mult_125_G2_A_not_4_port, b =>
mult_125_G2_B_not_7_port, outb =>
mult_125_G2_ab_4_7_port);
mult_125_G2_AN1_4_6 : nor2 port map( a => mult_125_G2_A_not_4_port, b =>
mult_125_G2_B_not_6_port, outb =>
mult_125_G2_ab_4_6_port);
mult_125_G2_AN1_4_5 : nor2 port map( a => mult_125_G2_A_not_4_port, b =>
mult_125_G2_B_not_5_port, outb =>
mult_125_G2_ab_4_5_port);
mult_125_G2_AN1_4_4 : nor2 port map( a => mult_125_G2_A_not_4_port, b =>
mult_125_G2_B_not_4_port, outb =>
mult_125_G2_ab_4_4_port);
mult_125_G2_AN1_4_3 : nor2 port map( a => mult_125_G2_A_not_4_port, b =>
mult_125_G2_B_not_3_port, outb =>
mult_125_G2_ab_4_3_port);
mult_125_G2_AN1_4_2 : nor2 port map( a => mult_125_G2_A_not_4_port, b =>
mult_125_G2_B_not_2_port, outb =>
mult_125_G2_ab_4_2_port);
mult_125_G2_AN1_4_1 : nor2 port map( a => mult_125_G2_A_not_4_port, b =>
mult_125_G2_B_not_1_port, outb =>
mult_125_G2_ab_4_1_port);
mult_125_G2_AN1_4_0_0 : nor2 port map( a => mult_125_G2_A_not_4_port, b =>
mult_125_G2_B_not_0_port, outb =>
mult_125_G2_ab_4_0_port);
mult_125_G2_AN2_3_15 : nor2 port map( a => mult_125_G2_A_notx_3_port, b =>
mult_125_G2_B_not_15_port, outb =>
mult_125_G2_ab_3_15_port);
mult_125_G2_AN1_3_14 : nor2 port map( a => mult_125_G2_A_not_3_port, b =>
mult_125_G2_B_not_14_port, outb =>
mult_125_G2_ab_3_14_port);
mult_125_G2_AN1_3_13 : nor2 port map( a => mult_125_G2_A_not_3_port, b =>
mult_125_G2_B_not_13_port, outb =>
mult_125_G2_ab_3_13_port);
mult_125_G2_AN1_3_12 : nor2 port map( a => mult_125_G2_A_not_3_port, b =>
mult_125_G2_B_not_12_port, outb =>
mult_125_G2_ab_3_12_port);
mult_125_G2_AN1_3_11 : nor2 port map( a => mult_125_G2_A_not_3_port, b =>
mult_125_G2_B_not_11_port, outb =>
mult_125_G2_ab_3_11_port);
mult_125_G2_AN1_3_10 : nor2 port map( a => mult_125_G2_A_not_3_port, b =>
mult_125_G2_B_not_10_port, outb =>
mult_125_G2_ab_3_10_port);
mult_125_G2_AN1_3_9 : nor2 port map( a => mult_125_G2_A_not_3_port, b =>
mult_125_G2_B_not_9_port, outb =>
mult_125_G2_ab_3_9_port);
mult_125_G2_AN1_3_8 : nor2 port map( a => mult_125_G2_A_not_3_port, b =>
mult_125_G2_B_not_8_port, outb =>
mult_125_G2_ab_3_8_port);
mult_125_G2_AN1_3_7 : nor2 port map( a => mult_125_G2_A_not_3_port, b =>
mult_125_G2_B_not_7_port, outb =>
mult_125_G2_ab_3_7_port);
mult_125_G2_AN1_3_6 : nor2 port map( a => mult_125_G2_A_not_3_port, b =>
mult_125_G2_B_not_6_port, outb =>
mult_125_G2_ab_3_6_port);
mult_125_G2_AN1_3_5 : nor2 port map( a => mult_125_G2_A_not_3_port, b =>
mult_125_G2_B_not_5_port, outb =>
mult_125_G2_ab_3_5_port);
mult_125_G2_AN1_3_4 : nor2 port map( a => mult_125_G2_A_not_3_port, b =>
mult_125_G2_B_not_4_port, outb =>
mult_125_G2_ab_3_4_port);
mult_125_G2_AN1_3_3 : nor2 port map( a => mult_125_G2_A_not_3_port, b =>
mult_125_G2_B_not_3_port, outb =>
mult_125_G2_ab_3_3_port);
mult_125_G2_AN1_3_2 : nor2 port map( a => mult_125_G2_A_not_3_port, b =>
mult_125_G2_B_not_2_port, outb =>
mult_125_G2_ab_3_2_port);
mult_125_G2_AN1_3_1 : nor2 port map( a => mult_125_G2_A_not_3_port, b =>
mult_125_G2_B_not_1_port, outb =>
mult_125_G2_ab_3_1_port);
mult_125_G2_AN1_3_0_0 : nor2 port map( a => mult_125_G2_A_not_3_port, b =>
mult_125_G2_B_not_0_port, outb =>
mult_125_G2_ab_3_0_port);
mult_125_G2_AN2_2_15 : nor2 port map( a => mult_125_G2_A_notx_2_port, b =>
mult_125_G2_B_not_15_port, outb =>
mult_125_G2_ab_2_15_port);
mult_125_G2_AN1_2_14 : nor2 port map( a => mult_125_G2_A_not_2_port, b =>
mult_125_G2_B_not_14_port, outb =>
mult_125_G2_ab_2_14_port);
mult_125_G2_AN1_2_13 : nor2 port map( a => mult_125_G2_A_not_2_port, b =>
mult_125_G2_B_not_13_port, outb =>
mult_125_G2_ab_2_13_port);
mult_125_G2_AN1_2_12 : nor2 port map( a => mult_125_G2_A_not_2_port, b =>
mult_125_G2_B_not_12_port, outb =>
mult_125_G2_ab_2_12_port);
mult_125_G2_AN1_2_11 : nor2 port map( a => mult_125_G2_A_not_2_port, b =>
mult_125_G2_B_not_11_port, outb =>
mult_125_G2_ab_2_11_port);
mult_125_G2_AN1_2_10 : nor2 port map( a => mult_125_G2_A_not_2_port, b =>
mult_125_G2_B_not_10_port, outb =>
mult_125_G2_ab_2_10_port);
mult_125_G2_AN1_2_9 : nor2 port map( a => mult_125_G2_A_not_2_port, b =>
mult_125_G2_B_not_9_port, outb =>
mult_125_G2_ab_2_9_port);
mult_125_G2_AN1_2_8 : nor2 port map( a => mult_125_G2_A_not_2_port, b =>
mult_125_G2_B_not_8_port, outb =>
mult_125_G2_ab_2_8_port);
mult_125_G2_AN1_2_7 : nor2 port map( a => mult_125_G2_A_not_2_port, b =>
mult_125_G2_B_not_7_port, outb =>
mult_125_G2_ab_2_7_port);
mult_125_G2_AN1_2_6 : nor2 port map( a => mult_125_G2_A_not_2_port, b =>
mult_125_G2_B_not_6_port, outb =>
mult_125_G2_ab_2_6_port);
mult_125_G2_AN1_2_5 : nor2 port map( a => mult_125_G2_A_not_2_port, b =>
mult_125_G2_B_not_5_port, outb =>
mult_125_G2_ab_2_5_port);
mult_125_G2_AN1_2_4 : nor2 port map( a => mult_125_G2_A_not_2_port, b =>
mult_125_G2_B_not_4_port, outb =>
mult_125_G2_ab_2_4_port);
mult_125_G2_AN1_2_3 : nor2 port map( a => mult_125_G2_A_not_2_port, b =>
mult_125_G2_B_not_3_port, outb =>
mult_125_G2_ab_2_3_port);
mult_125_G2_AN1_2_2 : nor2 port map( a => mult_125_G2_A_not_2_port, b =>
mult_125_G2_B_not_2_port, outb =>
mult_125_G2_ab_2_2_port);
mult_125_G2_AN1_2_1 : nor2 port map( a => mult_125_G2_A_not_2_port, b =>
mult_125_G2_B_not_1_port, outb =>
mult_125_G2_ab_2_1_port);
mult_125_G2_AN1_2_0_0 : nor2 port map( a => mult_125_G2_A_not_2_port, b =>
mult_125_G2_B_not_0_port, outb =>
mult_125_G2_ab_2_0_port);
mult_125_G2_AN2_1_15 : nor2 port map( a => mult_125_G2_A_notx_1_port, b =>
mult_125_G2_B_not_15_port, outb =>
mult_125_G2_ab_1_15_port);
mult_125_G2_AN1_1_14 : nor2 port map( a => mult_125_G2_A_not_1_port, b =>
mult_125_G2_B_not_14_port, outb =>
mult_125_G2_ab_1_14_port);
mult_125_G2_AN1_1_13 : nor2 port map( a => mult_125_G2_A_not_1_port, b =>
mult_125_G2_B_not_13_port, outb =>
mult_125_G2_ab_1_13_port);
mult_125_G2_AN1_1_12 : nor2 port map( a => mult_125_G2_A_not_1_port, b =>
mult_125_G2_B_not_12_port, outb =>
mult_125_G2_ab_1_12_port);
mult_125_G2_AN1_1_11 : nor2 port map( a => mult_125_G2_A_not_1_port, b =>
mult_125_G2_B_not_11_port, outb =>
mult_125_G2_ab_1_11_port);
mult_125_G2_AN1_1_10 : nor2 port map( a => mult_125_G2_A_not_1_port, b =>
mult_125_G2_B_not_10_port, outb =>
mult_125_G2_ab_1_10_port);
mult_125_G2_AN1_1_9 : nor2 port map( a => mult_125_G2_A_not_1_port, b =>
mult_125_G2_B_not_9_port, outb =>
mult_125_G2_ab_1_9_port);
mult_125_G2_AN1_1_8 : nor2 port map( a => mult_125_G2_A_not_1_port, b =>
mult_125_G2_B_not_8_port, outb =>
mult_125_G2_ab_1_8_port);
mult_125_G2_AN1_1_7 : nor2 port map( a => mult_125_G2_A_not_1_port, b =>
mult_125_G2_B_not_7_port, outb =>
mult_125_G2_ab_1_7_port);
mult_125_G2_AN1_1_6 : nor2 port map( a => mult_125_G2_A_not_1_port, b =>
mult_125_G2_B_not_6_port, outb =>
mult_125_G2_ab_1_6_port);
mult_125_G2_AN1_1_5 : nor2 port map( a => mult_125_G2_A_not_1_port, b =>
mult_125_G2_B_not_5_port, outb =>
mult_125_G2_ab_1_5_port);
mult_125_G2_AN1_1_4 : nor2 port map( a => mult_125_G2_A_not_1_port, b =>
mult_125_G2_B_not_4_port, outb =>
mult_125_G2_ab_1_4_port);
mult_125_G2_AN1_1_3 : nor2 port map( a => mult_125_G2_A_not_1_port, b =>
mult_125_G2_B_not_3_port, outb =>
mult_125_G2_ab_1_3_port);
mult_125_G2_AN1_1_2 : nor2 port map( a => mult_125_G2_A_not_1_port, b =>
mult_125_G2_B_not_2_port, outb =>
mult_125_G2_ab_1_2_port);
mult_125_G2_AN1_1_1 : nor2 port map( a => mult_125_G2_A_not_1_port, b =>
mult_125_G2_B_not_1_port, outb =>
mult_125_G2_ab_1_1_port);
mult_125_G2_AN1_1_0_0 : nor2 port map( a => mult_125_G2_A_not_1_port, b =>
mult_125_G2_B_not_0_port, outb =>
mult_125_G2_ab_1_0_port);
mult_125_G2_AN2_0_15 : nor2 port map( a => mult_125_G2_A_notx_0_port, b =>
mult_125_G2_B_not_15_port, outb =>
mult_125_G2_ab_0_15_port);
mult_125_G2_AN1_0_14 : nor2 port map( a => mult_125_G2_A_not_0_port, b =>
mult_125_G2_B_not_14_port, outb =>
mult_125_G2_ab_0_14_port);
mult_125_G2_AN1_0_13 : nor2 port map( a => mult_125_G2_A_not_0_port, b =>
mult_125_G2_B_not_13_port, outb =>
mult_125_G2_ab_0_13_port);
mult_125_G2_AN1_0_12 : nor2 port map( a => mult_125_G2_A_not_0_port, b =>
mult_125_G2_B_not_12_port, outb =>
mult_125_G2_ab_0_12_port);
mult_125_G2_AN1_0_11 : nor2 port map( a => mult_125_G2_A_not_0_port, b =>
mult_125_G2_B_not_11_port, outb =>
mult_125_G2_ab_0_11_port);
mult_125_G2_AN1_0_10 : nor2 port map( a => mult_125_G2_A_not_0_port, b =>
mult_125_G2_B_not_10_port, outb =>
mult_125_G2_ab_0_10_port);
mult_125_G2_AN1_0_9 : nor2 port map( a => mult_125_G2_A_not_0_port, b =>
mult_125_G2_B_not_9_port, outb =>
mult_125_G2_ab_0_9_port);
mult_125_G2_AN1_0_8 : nor2 port map( a => mult_125_G2_A_not_0_port, b =>
mult_125_G2_B_not_8_port, outb =>
mult_125_G2_ab_0_8_port);
mult_125_G2_AN1_0_7 : nor2 port map( a => mult_125_G2_A_not_0_port, b =>
mult_125_G2_B_not_7_port, outb =>
mult_125_G2_ab_0_7_port);
mult_125_G2_AN1_0_6 : nor2 port map( a => mult_125_G2_A_not_0_port, b =>
mult_125_G2_B_not_6_port, outb =>
mult_125_G2_ab_0_6_port);
mult_125_G2_AN1_0_5 : nor2 port map( a => mult_125_G2_A_not_0_port, b =>
mult_125_G2_B_not_5_port, outb =>
mult_125_G2_ab_0_5_port);
mult_125_G2_AN1_0_4 : nor2 port map( a => mult_125_G2_A_not_0_port, b =>
mult_125_G2_B_not_4_port, outb =>
mult_125_G2_ab_0_4_port);
mult_125_G2_AN1_0_3 : nor2 port map( a => mult_125_G2_A_not_0_port, b =>
mult_125_G2_B_not_3_port, outb =>
mult_125_G2_ab_0_3_port);
mult_125_G2_AN1_0_2 : nor2 port map( a => mult_125_G2_A_not_0_port, b =>
mult_125_G2_B_not_2_port, outb =>
mult_125_G2_ab_0_2_port);
mult_125_G2_AN1_0_1 : nor2 port map( a => mult_125_G2_A_not_0_port, b =>
mult_125_G2_B_not_1_port, outb =>
mult_125_G2_ab_0_1_port);
mult_125_G2_AN1_0_0_0 : nor2 port map( a => mult_125_G2_A_not_0_port, b =>
mult_125_G2_B_not_0_port, outb =>
multiplier_sigs_1_0_port);
mult_125_FS_1_U6_1_1_3 : oai12 port map( b => n5782, c => n5783, a => n5784,
outb => mult_125_FS_1_C_1_7_0_port);
mult_125_FS_1_U6_1_1_2 : oai12 port map( b => n5779, c => n5780, a => n5781,
outb => mult_125_FS_1_C_1_6_0_port);
mult_125_FS_1_U6_1_1_1 : oai12 port map( b => n5776, c => n5777, a => n5778,
outb => mult_125_FS_1_C_1_5_0_port);
mult_125_FS_1_U6_0_7_1 : oai12 port map( b => n5773, c => n5774, a =>
mult_125_FS_1_G_n_int_0_7_0_port, outb =>
mult_125_FS_1_C_1_7_1_port);
mult_125_FS_1_U3_C_0_7_1 : xor2 port map( a =>
mult_125_FS_1_PG_int_0_7_1_port, b =>
mult_125_FS_1_C_1_7_1_port, outb =>
multiplier_sigs_0_31_port);
mult_125_FS_1_U3_B_0_7_1 : nand2 port map( a =>
mult_125_FS_1_G_n_int_0_7_1_port, b =>
mult_125_FS_1_P_0_7_1_port, outb => n5772);
mult_125_FS_1_U2_0_7_1 : nand2 port map( a => mult_125_A1_29_port, b =>
mult_125_A2_29_port, outb =>
mult_125_FS_1_G_n_int_0_7_1_port);
mult_125_FS_1_U1_0_7_1 : nand2 port map( a => n5770, b => n5771, outb =>
mult_125_FS_1_P_0_7_1_port);
mult_125_FS_1_U3_C_0_7_0 : xor2 port map( a =>
mult_125_FS_1_PG_int_0_7_0_port, b =>
mult_125_FS_1_C_1_7_0_port, outb =>
multiplier_sigs_0_30_port);
mult_125_FS_1_U3_B_0_7_0 : nand2 port map( a =>
mult_125_FS_1_G_n_int_0_7_0_port, b =>
mult_125_FS_1_TEMP_P_0_7_0_port, outb => n5769);
mult_125_FS_1_U2_0_7_0 : nand2 port map( a => mult_125_A1_28_port, b =>
mult_125_A2_28_port, outb =>
mult_125_FS_1_G_n_int_0_7_0_port);
mult_125_FS_1_U1_0_7_0 : nand2 port map( a => n5767, b => n5768, outb =>
mult_125_FS_1_TEMP_P_0_7_0_port);
mult_125_FS_1_U6_0_6_3 : oai12 port map( b => n5765, c => n5766, a =>
mult_125_FS_1_G_n_int_0_6_2_port, outb =>
mult_125_FS_1_C_1_6_3_port);
mult_125_FS_1_U5_0_6_3 : oai12 port map( b => n5763, c => n5764, a =>
mult_125_FS_1_G_n_int_0_6_3_port, outb =>
mult_125_FS_1_G_1_1_2_port);
mult_125_FS_1_U4_0_6_3 : nand2 port map( a =>
mult_125_FS_1_TEMP_P_0_6_2_port, b =>
mult_125_FS_1_P_0_6_3_port, outb => n5783);
mult_125_FS_1_U3_C_0_6_3 : xor2 port map( a =>
mult_125_FS_1_PG_int_0_6_3_port, b =>
mult_125_FS_1_C_1_6_3_port, outb =>
multiplier_sigs_0_29_port);
mult_125_FS_1_U3_B_0_6_3 : nand2 port map( a =>
mult_125_FS_1_G_n_int_0_6_3_port, b =>
mult_125_FS_1_P_0_6_3_port, outb => n5762);
mult_125_FS_1_U2_0_6_3 : nand2 port map( a => mult_125_A1_27_port, b =>
mult_125_A2_27_port, outb =>
mult_125_FS_1_G_n_int_0_6_3_port);
mult_125_FS_1_U1_0_6_3 : nand2 port map( a => n5760, b => n5761, outb =>
mult_125_FS_1_P_0_6_3_port);
mult_125_FS_1_U6_0_6_2 : oai12 port map( b => n5758, c => n5759, a =>
mult_125_FS_1_G_n_int_0_6_1_port, outb =>
mult_125_FS_1_C_1_6_2_port);
mult_125_FS_1_U5_0_6_2 : oai12 port map( b => n5757, c => n5766, a =>
mult_125_FS_1_G_n_int_0_6_2_port, outb =>
mult_125_FS_1_TEMP_G_0_6_2_port);
mult_125_FS_1_U4_0_6_2 : nand2 port map( a =>
mult_125_FS_1_TEMP_P_0_6_1_port, b =>
mult_125_FS_1_P_0_6_2_port, outb => n5756);
mult_125_FS_1_U3_C_0_6_2 : xor2 port map( a =>
mult_125_FS_1_PG_int_0_6_2_port, b =>
mult_125_FS_1_C_1_6_2_port, outb =>
multiplier_sigs_0_28_port);
mult_125_FS_1_U3_B_0_6_2 : nand2 port map( a =>
mult_125_FS_1_G_n_int_0_6_2_port, b =>
mult_125_FS_1_P_0_6_2_port, outb => n5755);
mult_125_FS_1_U2_0_6_2 : nand2 port map( a => mult_125_A1_26_port, b =>
mult_125_A2_26_port, outb =>
mult_125_FS_1_G_n_int_0_6_2_port);
mult_125_FS_1_U1_0_6_2 : nand2 port map( a => n5753, b => n5754, outb =>
mult_125_FS_1_P_0_6_2_port);
mult_125_FS_1_U6_0_6_1 : oai12 port map( b => n5782, c => n5752, a =>
mult_125_FS_1_G_n_int_0_6_0_port, outb =>
mult_125_FS_1_C_1_6_1_port);
mult_125_FS_1_U5_0_6_1 : oai12 port map( b =>
mult_125_FS_1_G_n_int_0_6_0_port, c => n5759, a =>
mult_125_FS_1_G_n_int_0_6_1_port, outb =>
mult_125_FS_1_TEMP_G_0_6_1_port);
mult_125_FS_1_U4_0_6_1 : nand2 port map( a =>
mult_125_FS_1_TEMP_P_0_6_0_port, b =>
mult_125_FS_1_P_0_6_1_port, outb => n5751);
mult_125_FS_1_U3_C_0_6_1 : xor2 port map( a =>
mult_125_FS_1_PG_int_0_6_1_port, b =>
mult_125_FS_1_C_1_6_1_port, outb =>
multiplier_sigs_0_27_port);
mult_125_FS_1_U3_B_0_6_1 : nand2 port map( a =>
mult_125_FS_1_G_n_int_0_6_1_port, b =>
mult_125_FS_1_P_0_6_1_port, outb => n5750);
mult_125_FS_1_U2_0_6_1 : nand2 port map( a => mult_125_A1_25_port, b =>
mult_125_A2_25_port, outb =>
mult_125_FS_1_G_n_int_0_6_1_port);
mult_125_FS_1_U1_0_6_1 : nand2 port map( a => n5748, b => n5749, outb =>
mult_125_FS_1_P_0_6_1_port);
mult_125_FS_1_U3_C_0_6_0 : xor2 port map( a =>
mult_125_FS_1_PG_int_0_6_0_port, b =>
mult_125_FS_1_C_1_6_0_port, outb =>
multiplier_sigs_0_26_port);
mult_125_FS_1_U3_B_0_6_0 : nand2 port map( a =>
mult_125_FS_1_G_n_int_0_6_0_port, b =>
mult_125_FS_1_TEMP_P_0_6_0_port, outb => n5747);
mult_125_FS_1_U2_0_6_0 : nand2 port map( a => mult_125_A1_24_port, b =>
mult_125_A2_24_port, outb =>
mult_125_FS_1_G_n_int_0_6_0_port);
mult_125_FS_1_U1_0_6_0 : nand2 port map( a => n5745, b => n5746, outb =>
mult_125_FS_1_TEMP_P_0_6_0_port);
mult_125_FS_1_U6_0_5_3 : oai12 port map( b => n5743, c => n5744, a =>
mult_125_FS_1_G_n_int_0_5_2_port, outb =>
mult_125_FS_1_C_1_5_3_port);
mult_125_FS_1_U5_0_5_3 : oai12 port map( b => n5741, c => n5742, a =>
mult_125_FS_1_G_n_int_0_5_3_port, outb =>
mult_125_FS_1_G_1_1_1_port);
mult_125_FS_1_U4_0_5_3 : nand2 port map( a =>
mult_125_FS_1_TEMP_P_0_5_2_port, b =>
mult_125_FS_1_P_0_5_3_port, outb => n5780);
mult_125_FS_1_U3_C_0_5_3 : xor2 port map( a =>
mult_125_FS_1_PG_int_0_5_3_port, b =>
mult_125_FS_1_C_1_5_3_port, outb =>
multiplier_sigs_0_25_port);
mult_125_FS_1_U3_B_0_5_3 : nand2 port map( a =>
mult_125_FS_1_G_n_int_0_5_3_port, b =>
mult_125_FS_1_P_0_5_3_port, outb => n5740);
mult_125_FS_1_U2_0_5_3 : nand2 port map( a => mult_125_A1_23_port, b =>
mult_125_A2_23_port, outb =>
mult_125_FS_1_G_n_int_0_5_3_port);
mult_125_FS_1_U1_0_5_3 : nand2 port map( a => n5738, b => n5739, outb =>
mult_125_FS_1_P_0_5_3_port);
mult_125_FS_1_U6_0_5_2 : oai12 port map( b => n5736, c => n5737, a =>
mult_125_FS_1_G_n_int_0_5_1_port, outb =>
mult_125_FS_1_C_1_5_2_port);
mult_125_FS_1_U5_0_5_2 : oai12 port map( b => n5735, c => n5744, a =>
mult_125_FS_1_G_n_int_0_5_2_port, outb =>
mult_125_FS_1_TEMP_G_0_5_2_port);
mult_125_FS_1_U4_0_5_2 : nand2 port map( a =>
mult_125_FS_1_TEMP_P_0_5_1_port, b =>
mult_125_FS_1_P_0_5_2_port, outb => n5734);
mult_125_FS_1_U3_C_0_5_2 : xor2 port map( a =>
mult_125_FS_1_PG_int_0_5_2_port, b =>
mult_125_FS_1_C_1_5_2_port, outb =>
multiplier_sigs_0_24_port);
mult_125_FS_1_U3_B_0_5_2 : nand2 port map( a =>
mult_125_FS_1_G_n_int_0_5_2_port, b =>
mult_125_FS_1_P_0_5_2_port, outb => n5733);
mult_125_FS_1_U2_0_5_2 : nand2 port map( a => mult_125_A1_22_port, b =>
mult_125_A2_22_port, outb =>
mult_125_FS_1_G_n_int_0_5_2_port);
mult_125_FS_1_U1_0_5_2 : nand2 port map( a => n5731, b => n5732, outb =>
mult_125_FS_1_P_0_5_2_port);
mult_125_FS_1_U6_0_5_1 : oai12 port map( b => n5779, c => n5730, a =>
mult_125_FS_1_G_n_int_0_5_0_port, outb =>
mult_125_FS_1_C_1_5_1_port);
mult_125_FS_1_U5_0_5_1 : oai12 port map( b =>
mult_125_FS_1_G_n_int_0_5_0_port, c => n5737, a =>
mult_125_FS_1_G_n_int_0_5_1_port, outb =>
mult_125_FS_1_TEMP_G_0_5_1_port);
mult_125_FS_1_U4_0_5_1 : nand2 port map( a =>
mult_125_FS_1_TEMP_P_0_5_0_port, b =>
mult_125_FS_1_P_0_5_1_port, outb => n5729);
mult_125_FS_1_U3_C_0_5_1 : xor2 port map( a =>
mult_125_FS_1_PG_int_0_5_1_port, b =>
mult_125_FS_1_C_1_5_1_port, outb =>
multiplier_sigs_0_23_port);
mult_125_FS_1_U3_B_0_5_1 : nand2 port map( a =>
mult_125_FS_1_G_n_int_0_5_1_port, b =>
mult_125_FS_1_P_0_5_1_port, outb => n5728);
mult_125_FS_1_U2_0_5_1 : nand2 port map( a => mult_125_A1_21_port, b =>
mult_125_A2_21_port, outb =>
mult_125_FS_1_G_n_int_0_5_1_port);
mult_125_FS_1_U1_0_5_1 : nand2 port map( a => n5726, b => n5727, outb =>
mult_125_FS_1_P_0_5_1_port);
mult_125_FS_1_U3_C_0_5_0 : xor2 port map( a =>
mult_125_FS_1_PG_int_0_5_0_port, b =>
mult_125_FS_1_C_1_5_0_port, outb =>
multiplier_sigs_0_22_port);
mult_125_FS_1_U3_B_0_5_0 : nand2 port map( a =>
mult_125_FS_1_G_n_int_0_5_0_port, b =>
mult_125_FS_1_TEMP_P_0_5_0_port, outb => n5725);
mult_125_FS_1_U2_0_5_0 : nand2 port map( a => mult_125_A1_20_port, b =>
mult_125_A2_20_port, outb =>
mult_125_FS_1_G_n_int_0_5_0_port);
mult_125_FS_1_U1_0_5_0 : nand2 port map( a => n5723, b => n5724, outb =>
mult_125_FS_1_TEMP_P_0_5_0_port);
mult_125_FS_1_U6_0_4_3 : oai12 port map( b => n5721, c => n5722, a =>
mult_125_FS_1_G_n_int_0_4_2_port, outb =>
mult_125_FS_1_C_1_4_3_port);
mult_125_FS_1_U5_0_4_3 : oai12 port map( b => n5719, c => n5720, a =>
mult_125_FS_1_G_n_int_0_4_3_port, outb =>
mult_125_FS_1_G_1_1_0_port);
mult_125_FS_1_U4_0_4_3 : nand2 port map( a =>
mult_125_FS_1_TEMP_P_0_4_2_port, b =>
mult_125_FS_1_P_0_4_3_port, outb => n5777);
mult_125_FS_1_U3_C_0_4_3 : xor2 port map( a =>
mult_125_FS_1_PG_int_0_4_3_port, b =>
mult_125_FS_1_C_1_4_3_port, outb =>
multiplier_sigs_0_21_port);
mult_125_FS_1_U3_B_0_4_3 : nand2 port map( a =>
mult_125_FS_1_G_n_int_0_4_3_port, b =>
mult_125_FS_1_P_0_4_3_port, outb => n5718);
mult_125_FS_1_U2_0_4_3 : nand2 port map( a => mult_125_A1_19_port, b =>
mult_125_A2_19_port, outb =>
mult_125_FS_1_G_n_int_0_4_3_port);
mult_125_FS_1_U1_0_4_3 : nand2 port map( a => n5716, b => n5717, outb =>
mult_125_FS_1_P_0_4_3_port);
mult_125_FS_1_U6_0_4_2 : oai12 port map( b => n5714, c => n5715, a =>
mult_125_FS_1_G_n_int_0_4_1_port, outb =>
mult_125_FS_1_C_1_4_2_port);
mult_125_FS_1_U5_0_4_2 : oai12 port map( b => n5713, c => n5722, a =>
mult_125_FS_1_G_n_int_0_4_2_port, outb =>
mult_125_FS_1_TEMP_G_0_4_2_port);
mult_125_FS_1_U4_0_4_2 : nand2 port map( a =>
mult_125_FS_1_TEMP_P_0_4_1_port, b =>
mult_125_FS_1_P_0_4_2_port, outb => n5712);
mult_125_FS_1_U3_C_0_4_2 : xor2 port map( a =>
mult_125_FS_1_PG_int_0_4_2_port, b =>
mult_125_FS_1_C_1_4_2_port, outb =>
multiplier_sigs_0_20_port);
mult_125_FS_1_U3_B_0_4_2 : nand2 port map( a =>
mult_125_FS_1_G_n_int_0_4_2_port, b =>
mult_125_FS_1_P_0_4_2_port, outb => n5711);
mult_125_FS_1_U2_0_4_2 : nand2 port map( a => mult_125_A1_18_port, b =>
mult_125_A2_18_port, outb =>
mult_125_FS_1_G_n_int_0_4_2_port);
mult_125_FS_1_U1_0_4_2 : nand2 port map( a => n5709, b => n5710, outb =>
mult_125_FS_1_P_0_4_2_port);
mult_125_FS_1_U6_0_4_1 : oai12 port map( b => n5776, c => n5708, a =>
mult_125_FS_1_G_n_int_0_4_0_port, outb =>
mult_125_FS_1_C_1_4_1_port);
mult_125_FS_1_U5_0_4_1 : oai12 port map( b =>
mult_125_FS_1_G_n_int_0_4_0_port, c => n5715, a =>
mult_125_FS_1_G_n_int_0_4_1_port, outb =>
mult_125_FS_1_TEMP_G_0_4_1_port);
mult_125_FS_1_U4_0_4_1 : nand2 port map( a =>
mult_125_FS_1_TEMP_P_0_4_0_port, b =>
mult_125_FS_1_P_0_4_1_port, outb => n5707);
mult_125_FS_1_U3_C_0_4_1 : xor2 port map( a =>
mult_125_FS_1_PG_int_0_4_1_port, b =>
mult_125_FS_1_C_1_4_1_port, outb =>
multiplier_sigs_0_19_port);
mult_125_FS_1_U3_B_0_4_1 : nand2 port map( a =>
mult_125_FS_1_G_n_int_0_4_1_port, b =>
mult_125_FS_1_P_0_4_1_port, outb => n5706);
mult_125_FS_1_U2_0_4_1 : nand2 port map( a => mult_125_A1_17_port, b =>
mult_125_A2_17_port, outb =>
mult_125_FS_1_G_n_int_0_4_1_port);
mult_125_FS_1_U1_0_4_1 : nand2 port map( a => n5704, b => n5705, outb =>
mult_125_FS_1_P_0_4_1_port);
mult_125_FS_1_U3_C_0_4_0 : xor2 port map( a =>
mult_125_FS_1_PG_int_0_4_0_port, b =>
mult_125_FS_1_C_1_4_0_port, outb =>
multiplier_sigs_0_18_port);
mult_125_FS_1_U3_B_0_4_0 : nand2 port map( a =>
mult_125_FS_1_G_n_int_0_4_0_port, b =>
mult_125_FS_1_TEMP_P_0_4_0_port, outb => n5703);
mult_125_FS_1_U2_0_4_0 : nand2 port map( a => mult_125_A1_16_port, b =>
mult_125_A2_16_port, outb =>
mult_125_FS_1_G_n_int_0_4_0_port);
mult_125_FS_1_U1_0_4_0 : nand2 port map( a => n5701, b => n5702, outb =>
mult_125_FS_1_TEMP_P_0_4_0_port);
mult_125_FS_1_U5_0_3_3 : oai12 port map( b => n5699, c => n5700, a =>
mult_125_FS_1_G_n_int_0_3_3_port, outb =>
mult_125_FS_1_G_1_0_3_port);
mult_125_FS_1_U3_C_0_3_3 : xor2 port map( a =>
mult_125_FS_1_PG_int_0_3_3_port, b =>
mult_125_FS_1_C_1_3_3_port, outb =>
multiplier_sigs_0_17_port);
mult_125_FS_1_U3_B_0_3_3 : nand2 port map( a =>
mult_125_FS_1_G_n_int_0_3_3_port, b =>
mult_125_FS_1_P_0_3_3_port, outb => n5698);
mult_125_FS_1_U2_0_3_3 : nand2 port map( a => mult_125_A1_15_port, b =>
mult_125_A2_15_port, outb =>
mult_125_FS_1_G_n_int_0_3_3_port);
mult_125_FS_1_U1_0_3_3 : nand2 port map( a => n5696, b => n5697, outb =>
mult_125_FS_1_P_0_3_3_port);
mult_125_FS_1_U3_B_0_3_2 : nand2 port map( a =>
mult_125_FS_1_G_n_int_0_3_2_port, b =>
mult_125_FS_1_P_0_3_2_port, outb => n5695);
mult_125_FS_1_U2_0_3_2 : nand2 port map( a => mult_125_A1_14_port, b =>
mult_125_A2_14_port, outb =>
mult_125_FS_1_G_n_int_0_3_2_port);
mult_125_FS_1_U1_0_3_2 : nand2 port map( a => n5693, b => n5694, outb =>
mult_125_FS_1_P_0_3_2_port);
mult_125_AN1_15 : inv port map( inb => coefficient_mem_array_0_15_port, outb
=> mult_125_A_not_15_port);
mult_125_AN1_14 : inv port map( inb => coefficient_mem_array_0_14_port, outb
=> mult_125_A_not_14_port);
mult_125_AN1_13 : inv port map( inb => coefficient_mem_array_0_13_port, outb
=> mult_125_A_not_13_port);
mult_125_AN1_12 : inv port map( inb => coefficient_mem_array_0_12_port, outb
=> mult_125_A_not_12_port);
mult_125_AN1_11 : inv port map( inb => coefficient_mem_array_0_11_port, outb
=> mult_125_A_not_11_port);
mult_125_AN1_10 : inv port map( inb => coefficient_mem_array_0_10_port, outb
=> mult_125_A_not_10_port);
mult_125_AN1_9 : inv port map( inb => coefficient_mem_array_0_9_port, outb
=> mult_125_A_not_9_port);
mult_125_AN1_8 : inv port map( inb => coefficient_mem_array_0_8_port, outb
=> mult_125_A_not_8_port);
mult_125_AN1_7 : inv port map( inb => coefficient_mem_array_0_7_port, outb
=> mult_125_A_not_7_port);
mult_125_AN1_6 : inv port map( inb => coefficient_mem_array_0_6_port, outb
=> mult_125_A_not_6_port);
mult_125_AN1_5 : inv port map( inb => coefficient_mem_array_0_5_port, outb
=> mult_125_A_not_5_port);
mult_125_AN1_4 : inv port map( inb => coefficient_mem_array_0_4_port, outb
=> mult_125_A_not_4_port);
mult_125_AN1_3 : inv port map( inb => coefficient_mem_array_0_3_port, outb
=> mult_125_A_not_3_port);
mult_125_AN1_2 : inv port map( inb => coefficient_mem_array_0_2_port, outb
=> mult_125_A_not_2_port);
mult_125_AN1_1 : inv port map( inb => coefficient_mem_array_0_1_port, outb
=> mult_125_A_not_1_port);
mult_125_AN1_0 : inv port map( inb => coefficient_mem_array_0_0_port, outb
=> mult_125_A_not_0_port);
mult_125_AN1_15_0 : inv port map( inb => input_sample_mem_15_port, outb =>
mult_125_B_not_15_port);
mult_125_AN1_14_0 : inv port map( inb => input_sample_mem_14_port, outb =>
mult_125_B_not_14_port);
mult_125_AN1_13_0 : inv port map( inb => input_sample_mem_13_port, outb =>
mult_125_B_not_13_port);
mult_125_AN1_12_0 : inv port map( inb => input_sample_mem_12_port, outb =>
mult_125_B_not_12_port);
mult_125_AN1_11_0 : inv port map( inb => input_sample_mem_11_port, outb =>
mult_125_B_not_11_port);
mult_125_AN1_10_0 : inv port map( inb => input_sample_mem_10_port, outb =>
mult_125_B_not_10_port);
mult_125_AN1_9_0 : inv port map( inb => input_sample_mem_9_port, outb =>
mult_125_B_not_9_port);
mult_125_AN1_8_0 : inv port map( inb => input_sample_mem_8_port, outb =>
mult_125_B_not_8_port);
mult_125_AN1_7_0 : inv port map( inb => input_sample_mem_7_port, outb =>
mult_125_B_not_7_port);
mult_125_AN1_6_0 : inv port map( inb => input_sample_mem_6_port, outb =>
mult_125_B_not_6_port);
mult_125_AN1_5_0 : inv port map( inb => input_sample_mem_5_port, outb =>
mult_125_B_not_5_port);
mult_125_AN1_4_0 : inv port map( inb => input_sample_mem_4_port, outb =>
mult_125_B_not_4_port);
mult_125_AN1_3_0 : inv port map( inb => input_sample_mem_3_port, outb =>
mult_125_B_not_3_port);
mult_125_AN1_2_0 : inv port map( inb => input_sample_mem_2_port, outb =>
mult_125_B_not_2_port);
mult_125_AN1_1_0 : inv port map( inb => input_sample_mem_1_port, outb =>
mult_125_B_not_1_port);
mult_125_AN1_0_0 : inv port map( inb => input_sample_mem_0_port, outb =>
mult_125_B_not_0_port);
mult_125_AN1_15_15 : nor2 port map( a => mult_125_A_not_15_port, b =>
mult_125_B_not_15_port, outb =>
mult_125_ab_15_15_port);
mult_125_AN3_15_14 : nor2 port map( a => mult_125_A_not_15_port, b =>
mult_125_B_notx_14_port, outb =>
mult_125_ab_15_14_port);
mult_125_AN3_15_13 : nor2 port map( a => mult_125_A_not_15_port, b =>
mult_125_B_notx_13_port, outb =>
mult_125_ab_15_13_port);
mult_125_AN3_15_12 : nor2 port map( a => mult_125_A_not_15_port, b =>
mult_125_B_notx_12_port, outb =>
mult_125_ab_15_12_port);
mult_125_AN3_15_11 : nor2 port map( a => mult_125_A_not_15_port, b =>
mult_125_B_notx_11_port, outb =>
mult_125_ab_15_11_port);
mult_125_AN3_15_10 : nor2 port map( a => mult_125_A_not_15_port, b =>
mult_125_B_notx_10_port, outb =>
mult_125_ab_15_10_port);
mult_125_AN3_15_9 : nor2 port map( a => mult_125_A_not_15_port, b =>
mult_125_B_notx_9_port, outb =>
mult_125_ab_15_9_port);
mult_125_AN3_15_8 : nor2 port map( a => mult_125_A_not_15_port, b =>
mult_125_B_notx_8_port, outb =>
mult_125_ab_15_8_port);
mult_125_AN3_15_7 : nor2 port map( a => mult_125_A_not_15_port, b =>
mult_125_B_notx_7_port, outb =>
mult_125_ab_15_7_port);
mult_125_AN3_15_6 : nor2 port map( a => mult_125_A_not_15_port, b =>
mult_125_B_notx_6_port, outb =>
mult_125_ab_15_6_port);
mult_125_AN3_15_5 : nor2 port map( a => mult_125_A_not_15_port, b =>
mult_125_B_notx_5_port, outb =>
mult_125_ab_15_5_port);
mult_125_AN3_15_4 : nor2 port map( a => mult_125_A_not_15_port, b =>
mult_125_B_notx_4_port, outb =>
mult_125_ab_15_4_port);
mult_125_AN3_15_3 : nor2 port map( a => mult_125_A_not_15_port, b =>
mult_125_B_notx_3_port, outb =>
mult_125_ab_15_3_port);
mult_125_AN3_15_2 : nor2 port map( a => mult_125_A_not_15_port, b =>
mult_125_B_notx_2_port, outb =>
mult_125_ab_15_2_port);
mult_125_AN3_15_1 : nor2 port map( a => mult_125_A_not_15_port, b =>
mult_125_B_notx_1_port, outb =>
mult_125_ab_15_1_port);
mult_125_AN3_15_0 : nor2 port map( a => mult_125_A_not_15_port, b =>
mult_125_B_notx_0_port, outb =>
mult_125_ab_15_0_port);
mult_125_AN2_14_15 : nor2 port map( a => mult_125_A_notx_14_port, b =>
mult_125_B_not_15_port, outb =>
mult_125_ab_14_15_port);
mult_125_AN1_14_14 : nor2 port map( a => mult_125_A_not_14_port, b =>
mult_125_B_not_14_port, outb =>
mult_125_ab_14_14_port);
mult_125_AN1_14_13 : nor2 port map( a => mult_125_A_not_14_port, b =>
mult_125_B_not_13_port, outb =>
mult_125_ab_14_13_port);
mult_125_AN1_14_12 : nor2 port map( a => mult_125_A_not_14_port, b =>
mult_125_B_not_12_port, outb =>
mult_125_ab_14_12_port);
mult_125_AN1_14_11 : nor2 port map( a => mult_125_A_not_14_port, b =>
mult_125_B_not_11_port, outb =>
mult_125_ab_14_11_port);
mult_125_AN1_14_10 : nor2 port map( a => mult_125_A_not_14_port, b =>
mult_125_B_not_10_port, outb =>
mult_125_ab_14_10_port);
mult_125_AN1_14_9 : nor2 port map( a => mult_125_A_not_14_port, b =>
mult_125_B_not_9_port, outb => mult_125_ab_14_9_port
);
mult_125_AN1_14_8 : nor2 port map( a => mult_125_A_not_14_port, b =>
mult_125_B_not_8_port, outb => mult_125_ab_14_8_port
);
mult_125_AN1_14_7 : nor2 port map( a => mult_125_A_not_14_port, b =>
mult_125_B_not_7_port, outb => mult_125_ab_14_7_port
);
mult_125_AN1_14_6 : nor2 port map( a => mult_125_A_not_14_port, b =>
mult_125_B_not_6_port, outb => mult_125_ab_14_6_port
);
mult_125_AN1_14_5 : nor2 port map( a => mult_125_A_not_14_port, b =>
mult_125_B_not_5_port, outb => mult_125_ab_14_5_port
);
mult_125_AN1_14_4 : nor2 port map( a => mult_125_A_not_14_port, b =>
mult_125_B_not_4_port, outb => mult_125_ab_14_4_port
);
mult_125_AN1_14_3 : nor2 port map( a => mult_125_A_not_14_port, b =>
mult_125_B_not_3_port, outb => mult_125_ab_14_3_port
);
mult_125_AN1_14_2 : nor2 port map( a => mult_125_A_not_14_port, b =>
mult_125_B_not_2_port, outb => mult_125_ab_14_2_port
);
mult_125_AN1_14_1 : nor2 port map( a => mult_125_A_not_14_port, b =>
mult_125_B_not_1_port, outb => mult_125_ab_14_1_port
);
mult_125_AN1_14_0_0 : nor2 port map( a => mult_125_A_not_14_port, b =>
mult_125_B_not_0_port, outb => mult_125_ab_14_0_port
);
mult_125_AN2_13_15 : nor2 port map( a => mult_125_A_notx_13_port, b =>
mult_125_B_not_15_port, outb =>
mult_125_ab_13_15_port);
mult_125_AN1_13_14 : nor2 port map( a => mult_125_A_not_13_port, b =>
mult_125_B_not_14_port, outb =>
mult_125_ab_13_14_port);
mult_125_AN1_13_13 : nor2 port map( a => mult_125_A_not_13_port, b =>
mult_125_B_not_13_port, outb =>
mult_125_ab_13_13_port);
mult_125_AN1_13_12 : nor2 port map( a => mult_125_A_not_13_port, b =>
mult_125_B_not_12_port, outb =>
mult_125_ab_13_12_port);
mult_125_AN1_13_11 : nor2 port map( a => mult_125_A_not_13_port, b =>
mult_125_B_not_11_port, outb =>
mult_125_ab_13_11_port);
mult_125_AN1_13_10 : nor2 port map( a => mult_125_A_not_13_port, b =>
mult_125_B_not_10_port, outb =>
mult_125_ab_13_10_port);
mult_125_AN1_13_9 : nor2 port map( a => mult_125_A_not_13_port, b =>
mult_125_B_not_9_port, outb => mult_125_ab_13_9_port
);
mult_125_AN1_13_8 : nor2 port map( a => mult_125_A_not_13_port, b =>
mult_125_B_not_8_port, outb => mult_125_ab_13_8_port
);
mult_125_AN1_13_7 : nor2 port map( a => mult_125_A_not_13_port, b =>
mult_125_B_not_7_port, outb => mult_125_ab_13_7_port
);
mult_125_AN1_13_6 : nor2 port map( a => mult_125_A_not_13_port, b =>
mult_125_B_not_6_port, outb => mult_125_ab_13_6_port
);
mult_125_AN1_13_5 : nor2 port map( a => mult_125_A_not_13_port, b =>
mult_125_B_not_5_port, outb => mult_125_ab_13_5_port
);
mult_125_AN1_13_4 : nor2 port map( a => mult_125_A_not_13_port, b =>
mult_125_B_not_4_port, outb => mult_125_ab_13_4_port
);
mult_125_AN1_13_3 : nor2 port map( a => mult_125_A_not_13_port, b =>
mult_125_B_not_3_port, outb => mult_125_ab_13_3_port
);
mult_125_AN1_13_2 : nor2 port map( a => mult_125_A_not_13_port, b =>
mult_125_B_not_2_port, outb => mult_125_ab_13_2_port
);
mult_125_AN1_13_1 : nor2 port map( a => mult_125_A_not_13_port, b =>
mult_125_B_not_1_port, outb => mult_125_ab_13_1_port
);
mult_125_AN1_13_0_0 : nor2 port map( a => mult_125_A_not_13_port, b =>
mult_125_B_not_0_port, outb => mult_125_ab_13_0_port
);
mult_125_AN2_12_15 : nor2 port map( a => mult_125_A_notx_12_port, b =>
mult_125_B_not_15_port, outb =>
mult_125_ab_12_15_port);
mult_125_AN1_12_14 : nor2 port map( a => mult_125_A_not_12_port, b =>
mult_125_B_not_14_port, outb =>
mult_125_ab_12_14_port);
mult_125_AN1_12_13 : nor2 port map( a => mult_125_A_not_12_port, b =>
mult_125_B_not_13_port, outb =>
mult_125_ab_12_13_port);
mult_125_AN1_12_12 : nor2 port map( a => mult_125_A_not_12_port, b =>
mult_125_B_not_12_port, outb =>
mult_125_ab_12_12_port);
mult_125_AN1_12_11 : nor2 port map( a => mult_125_A_not_12_port, b =>
mult_125_B_not_11_port, outb =>
mult_125_ab_12_11_port);
mult_125_AN1_12_10 : nor2 port map( a => mult_125_A_not_12_port, b =>
mult_125_B_not_10_port, outb =>
mult_125_ab_12_10_port);
mult_125_AN1_12_9 : nor2 port map( a => mult_125_A_not_12_port, b =>
mult_125_B_not_9_port, outb => mult_125_ab_12_9_port
);
mult_125_AN1_12_8 : nor2 port map( a => mult_125_A_not_12_port, b =>
mult_125_B_not_8_port, outb => mult_125_ab_12_8_port
);
mult_125_AN1_12_7 : nor2 port map( a => mult_125_A_not_12_port, b =>
mult_125_B_not_7_port, outb => mult_125_ab_12_7_port
);
mult_125_AN1_12_6 : nor2 port map( a => mult_125_A_not_12_port, b =>
mult_125_B_not_6_port, outb => mult_125_ab_12_6_port
);
mult_125_AN1_12_5 : nor2 port map( a => mult_125_A_not_12_port, b =>
mult_125_B_not_5_port, outb => mult_125_ab_12_5_port
);
mult_125_AN1_12_4 : nor2 port map( a => mult_125_A_not_12_port, b =>
mult_125_B_not_4_port, outb => mult_125_ab_12_4_port
);
mult_125_AN1_12_3 : nor2 port map( a => mult_125_A_not_12_port, b =>
mult_125_B_not_3_port, outb => mult_125_ab_12_3_port
);
mult_125_AN1_12_2 : nor2 port map( a => mult_125_A_not_12_port, b =>
mult_125_B_not_2_port, outb => mult_125_ab_12_2_port
);
mult_125_AN1_12_1 : nor2 port map( a => mult_125_A_not_12_port, b =>
mult_125_B_not_1_port, outb => mult_125_ab_12_1_port
);
mult_125_AN1_12_0_0 : nor2 port map( a => mult_125_A_not_12_port, b =>
mult_125_B_not_0_port, outb => mult_125_ab_12_0_port
);
mult_125_AN2_11_15 : nor2 port map( a => mult_125_A_notx_11_port, b =>
mult_125_B_not_15_port, outb =>
mult_125_ab_11_15_port);
mult_125_AN1_11_14 : nor2 port map( a => mult_125_A_not_11_port, b =>
mult_125_B_not_14_port, outb =>
mult_125_ab_11_14_port);
mult_125_AN1_11_13 : nor2 port map( a => mult_125_A_not_11_port, b =>
mult_125_B_not_13_port, outb =>
mult_125_ab_11_13_port);
mult_125_AN1_11_12 : nor2 port map( a => mult_125_A_not_11_port, b =>
mult_125_B_not_12_port, outb =>
mult_125_ab_11_12_port);
mult_125_AN1_11_11 : nor2 port map( a => mult_125_A_not_11_port, b =>
mult_125_B_not_11_port, outb =>
mult_125_ab_11_11_port);
mult_125_AN1_11_10 : nor2 port map( a => mult_125_A_not_11_port, b =>
mult_125_B_not_10_port, outb =>
mult_125_ab_11_10_port);
mult_125_AN1_11_9 : nor2 port map( a => mult_125_A_not_11_port, b =>
mult_125_B_not_9_port, outb => mult_125_ab_11_9_port
);
mult_125_AN1_11_8 : nor2 port map( a => mult_125_A_not_11_port, b =>
mult_125_B_not_8_port, outb => mult_125_ab_11_8_port
);
mult_125_AN1_11_7 : nor2 port map( a => mult_125_A_not_11_port, b =>
mult_125_B_not_7_port, outb => mult_125_ab_11_7_port
);
mult_125_AN1_11_6 : nor2 port map( a => mult_125_A_not_11_port, b =>
mult_125_B_not_6_port, outb => mult_125_ab_11_6_port
);
mult_125_AN1_11_5 : nor2 port map( a => mult_125_A_not_11_port, b =>
mult_125_B_not_5_port, outb => mult_125_ab_11_5_port
);
mult_125_AN1_11_4 : nor2 port map( a => mult_125_A_not_11_port, b =>
mult_125_B_not_4_port, outb => mult_125_ab_11_4_port
);
mult_125_AN1_11_3 : nor2 port map( a => mult_125_A_not_11_port, b =>
mult_125_B_not_3_port, outb => mult_125_ab_11_3_port
);
mult_125_AN1_11_2 : nor2 port map( a => mult_125_A_not_11_port, b =>
mult_125_B_not_2_port, outb => mult_125_ab_11_2_port
);
mult_125_AN1_11_1 : nor2 port map( a => mult_125_A_not_11_port, b =>
mult_125_B_not_1_port, outb => mult_125_ab_11_1_port
);
mult_125_AN1_11_0_0 : nor2 port map( a => mult_125_A_not_11_port, b =>
mult_125_B_not_0_port, outb => mult_125_ab_11_0_port
);
mult_125_AN2_10_15 : nor2 port map( a => mult_125_A_notx_10_port, b =>
mult_125_B_not_15_port, outb =>
mult_125_ab_10_15_port);
mult_125_AN1_10_14 : nor2 port map( a => mult_125_A_not_10_port, b =>
mult_125_B_not_14_port, outb =>
mult_125_ab_10_14_port);
mult_125_AN1_10_13 : nor2 port map( a => mult_125_A_not_10_port, b =>
mult_125_B_not_13_port, outb =>
mult_125_ab_10_13_port);
mult_125_AN1_10_12 : nor2 port map( a => mult_125_A_not_10_port, b =>
mult_125_B_not_12_port, outb =>
mult_125_ab_10_12_port);
mult_125_AN1_10_11 : nor2 port map( a => mult_125_A_not_10_port, b =>
mult_125_B_not_11_port, outb =>
mult_125_ab_10_11_port);
mult_125_AN1_10_10 : nor2 port map( a => mult_125_A_not_10_port, b =>
mult_125_B_not_10_port, outb =>
mult_125_ab_10_10_port);
mult_125_AN1_10_9 : nor2 port map( a => mult_125_A_not_10_port, b =>
mult_125_B_not_9_port, outb => mult_125_ab_10_9_port
);
mult_125_AN1_10_8 : nor2 port map( a => mult_125_A_not_10_port, b =>
mult_125_B_not_8_port, outb => mult_125_ab_10_8_port
);
mult_125_AN1_10_7 : nor2 port map( a => mult_125_A_not_10_port, b =>
mult_125_B_not_7_port, outb => mult_125_ab_10_7_port
);
mult_125_AN1_10_6 : nor2 port map( a => mult_125_A_not_10_port, b =>
mult_125_B_not_6_port, outb => mult_125_ab_10_6_port
);
mult_125_AN1_10_5 : nor2 port map( a => mult_125_A_not_10_port, b =>
mult_125_B_not_5_port, outb => mult_125_ab_10_5_port
);
mult_125_AN1_10_4 : nor2 port map( a => mult_125_A_not_10_port, b =>
mult_125_B_not_4_port, outb => mult_125_ab_10_4_port
);
mult_125_AN1_10_3 : nor2 port map( a => mult_125_A_not_10_port, b =>
mult_125_B_not_3_port, outb => mult_125_ab_10_3_port
);
mult_125_AN1_10_2 : nor2 port map( a => mult_125_A_not_10_port, b =>
mult_125_B_not_2_port, outb => mult_125_ab_10_2_port
);
mult_125_AN1_10_1 : nor2 port map( a => mult_125_A_not_10_port, b =>
mult_125_B_not_1_port, outb => mult_125_ab_10_1_port
);
mult_125_AN1_10_0_0 : nor2 port map( a => mult_125_A_not_10_port, b =>
mult_125_B_not_0_port, outb => mult_125_ab_10_0_port
);
mult_125_AN2_9_15 : nor2 port map( a => mult_125_A_notx_9_port, b =>
mult_125_B_not_15_port, outb =>
mult_125_ab_9_15_port);
mult_125_AN1_9_14 : nor2 port map( a => mult_125_A_not_9_port, b =>
mult_125_B_not_14_port, outb =>
mult_125_ab_9_14_port);
mult_125_AN1_9_13 : nor2 port map( a => mult_125_A_not_9_port, b =>
mult_125_B_not_13_port, outb =>
mult_125_ab_9_13_port);
mult_125_AN1_9_12 : nor2 port map( a => mult_125_A_not_9_port, b =>
mult_125_B_not_12_port, outb =>
mult_125_ab_9_12_port);
mult_125_AN1_9_11 : nor2 port map( a => mult_125_A_not_9_port, b =>
mult_125_B_not_11_port, outb =>
mult_125_ab_9_11_port);
mult_125_AN1_9_10 : nor2 port map( a => mult_125_A_not_9_port, b =>
mult_125_B_not_10_port, outb =>
mult_125_ab_9_10_port);
mult_125_AN1_9_9 : nor2 port map( a => mult_125_A_not_9_port, b =>
mult_125_B_not_9_port, outb => mult_125_ab_9_9_port)
;
mult_125_AN1_9_8 : nor2 port map( a => mult_125_A_not_9_port, b =>
mult_125_B_not_8_port, outb => mult_125_ab_9_8_port)
;
mult_125_AN1_9_7 : nor2 port map( a => mult_125_A_not_9_port, b =>
mult_125_B_not_7_port, outb => mult_125_ab_9_7_port)
;
mult_125_AN1_9_6 : nor2 port map( a => mult_125_A_not_9_port, b =>
mult_125_B_not_6_port, outb => mult_125_ab_9_6_port)
;
mult_125_AN1_9_5 : nor2 port map( a => mult_125_A_not_9_port, b =>
mult_125_B_not_5_port, outb => mult_125_ab_9_5_port)
;
mult_125_AN1_9_4 : nor2 port map( a => mult_125_A_not_9_port, b =>
mult_125_B_not_4_port, outb => mult_125_ab_9_4_port)
;
mult_125_AN1_9_3 : nor2 port map( a => mult_125_A_not_9_port, b =>
mult_125_B_not_3_port, outb => mult_125_ab_9_3_port)
;
mult_125_AN1_9_2 : nor2 port map( a => mult_125_A_not_9_port, b =>
mult_125_B_not_2_port, outb => mult_125_ab_9_2_port)
;
mult_125_AN1_9_1 : nor2 port map( a => mult_125_A_not_9_port, b =>
mult_125_B_not_1_port, outb => mult_125_ab_9_1_port)
;
mult_125_AN1_9_0_0 : nor2 port map( a => mult_125_A_not_9_port, b =>
mult_125_B_not_0_port, outb => mult_125_ab_9_0_port)
;
mult_125_AN2_8_15 : nor2 port map( a => mult_125_A_notx_8_port, b =>
mult_125_B_not_15_port, outb =>
mult_125_ab_8_15_port);
mult_125_AN1_8_14 : nor2 port map( a => mult_125_A_not_8_port, b =>
mult_125_B_not_14_port, outb =>
mult_125_ab_8_14_port);
mult_125_AN1_8_13 : nor2 port map( a => mult_125_A_not_8_port, b =>
mult_125_B_not_13_port, outb =>
mult_125_ab_8_13_port);
mult_125_AN1_8_12 : nor2 port map( a => mult_125_A_not_8_port, b =>
mult_125_B_not_12_port, outb =>
mult_125_ab_8_12_port);
mult_125_AN1_8_11 : nor2 port map( a => mult_125_A_not_8_port, b =>
mult_125_B_not_11_port, outb =>
mult_125_ab_8_11_port);
mult_125_AN1_8_10 : nor2 port map( a => mult_125_A_not_8_port, b =>
mult_125_B_not_10_port, outb =>
mult_125_ab_8_10_port);
mult_125_AN1_8_9 : nor2 port map( a => mult_125_A_not_8_port, b =>
mult_125_B_not_9_port, outb => mult_125_ab_8_9_port)
;
mult_125_AN1_8_8 : nor2 port map( a => mult_125_A_not_8_port, b =>
mult_125_B_not_8_port, outb => mult_125_ab_8_8_port)
;
mult_125_AN1_8_7 : nor2 port map( a => mult_125_A_not_8_port, b =>
mult_125_B_not_7_port, outb => mult_125_ab_8_7_port)
;
mult_125_AN1_8_6 : nor2 port map( a => mult_125_A_not_8_port, b =>
mult_125_B_not_6_port, outb => mult_125_ab_8_6_port)
;
mult_125_AN1_8_5 : nor2 port map( a => mult_125_A_not_8_port, b =>
mult_125_B_not_5_port, outb => mult_125_ab_8_5_port)
;
mult_125_AN1_8_4 : nor2 port map( a => mult_125_A_not_8_port, b =>
mult_125_B_not_4_port, outb => mult_125_ab_8_4_port)
;
mult_125_AN1_8_3 : nor2 port map( a => mult_125_A_not_8_port, b =>
mult_125_B_not_3_port, outb => mult_125_ab_8_3_port)
;
mult_125_AN1_8_2 : nor2 port map( a => mult_125_A_not_8_port, b =>
mult_125_B_not_2_port, outb => mult_125_ab_8_2_port)
;
mult_125_AN1_8_1 : nor2 port map( a => mult_125_A_not_8_port, b =>
mult_125_B_not_1_port, outb => mult_125_ab_8_1_port)
;
mult_125_AN1_8_0_0 : nor2 port map( a => mult_125_A_not_8_port, b =>
mult_125_B_not_0_port, outb => mult_125_ab_8_0_port)
;
mult_125_AN2_7_15 : nor2 port map( a => mult_125_A_notx_7_port, b =>
mult_125_B_not_15_port, outb =>
mult_125_ab_7_15_port);
mult_125_AN1_7_14 : nor2 port map( a => mult_125_A_not_7_port, b =>
mult_125_B_not_14_port, outb =>
mult_125_ab_7_14_port);
mult_125_AN1_7_13 : nor2 port map( a => mult_125_A_not_7_port, b =>
mult_125_B_not_13_port, outb =>
mult_125_ab_7_13_port);
mult_125_AN1_7_12 : nor2 port map( a => mult_125_A_not_7_port, b =>
mult_125_B_not_12_port, outb =>
mult_125_ab_7_12_port);
mult_125_AN1_7_11 : nor2 port map( a => mult_125_A_not_7_port, b =>
mult_125_B_not_11_port, outb =>
mult_125_ab_7_11_port);
mult_125_AN1_7_10 : nor2 port map( a => mult_125_A_not_7_port, b =>
mult_125_B_not_10_port, outb =>
mult_125_ab_7_10_port);
mult_125_AN1_7_9 : nor2 port map( a => mult_125_A_not_7_port, b =>
mult_125_B_not_9_port, outb => mult_125_ab_7_9_port)
;
mult_125_AN1_7_8 : nor2 port map( a => mult_125_A_not_7_port, b =>
mult_125_B_not_8_port, outb => mult_125_ab_7_8_port)
;
mult_125_AN1_7_7 : nor2 port map( a => mult_125_A_not_7_port, b =>
mult_125_B_not_7_port, outb => mult_125_ab_7_7_port)
;
mult_125_AN1_7_6 : nor2 port map( a => mult_125_A_not_7_port, b =>
mult_125_B_not_6_port, outb => mult_125_ab_7_6_port)
;
mult_125_AN1_7_5 : nor2 port map( a => mult_125_A_not_7_port, b =>
mult_125_B_not_5_port, outb => mult_125_ab_7_5_port)
;
mult_125_AN1_7_4 : nor2 port map( a => mult_125_A_not_7_port, b =>
mult_125_B_not_4_port, outb => mult_125_ab_7_4_port)
;
mult_125_AN1_7_3 : nor2 port map( a => mult_125_A_not_7_port, b =>
mult_125_B_not_3_port, outb => mult_125_ab_7_3_port)
;
mult_125_AN1_7_2 : nor2 port map( a => mult_125_A_not_7_port, b =>
mult_125_B_not_2_port, outb => mult_125_ab_7_2_port)
;
mult_125_AN1_7_1 : nor2 port map( a => mult_125_A_not_7_port, b =>
mult_125_B_not_1_port, outb => mult_125_ab_7_1_port)
;
mult_125_AN1_7_0_0 : nor2 port map( a => mult_125_A_not_7_port, b =>
mult_125_B_not_0_port, outb => mult_125_ab_7_0_port)
;
mult_125_AN2_6_15 : nor2 port map( a => mult_125_A_notx_6_port, b =>
mult_125_B_not_15_port, outb =>
mult_125_ab_6_15_port);
mult_125_AN1_6_14 : nor2 port map( a => mult_125_A_not_6_port, b =>
mult_125_B_not_14_port, outb =>
mult_125_ab_6_14_port);
mult_125_AN1_6_13 : nor2 port map( a => mult_125_A_not_6_port, b =>
mult_125_B_not_13_port, outb =>
mult_125_ab_6_13_port);
mult_125_AN1_6_12 : nor2 port map( a => mult_125_A_not_6_port, b =>
mult_125_B_not_12_port, outb =>
mult_125_ab_6_12_port);
mult_125_AN1_6_11 : nor2 port map( a => mult_125_A_not_6_port, b =>
mult_125_B_not_11_port, outb =>
mult_125_ab_6_11_port);
mult_125_AN1_6_10 : nor2 port map( a => mult_125_A_not_6_port, b =>
mult_125_B_not_10_port, outb =>
mult_125_ab_6_10_port);
mult_125_AN1_6_9 : nor2 port map( a => mult_125_A_not_6_port, b =>
mult_125_B_not_9_port, outb => mult_125_ab_6_9_port)
;
mult_125_AN1_6_8 : nor2 port map( a => mult_125_A_not_6_port, b =>
mult_125_B_not_8_port, outb => mult_125_ab_6_8_port)
;
mult_125_AN1_6_7 : nor2 port map( a => mult_125_A_not_6_port, b =>
mult_125_B_not_7_port, outb => mult_125_ab_6_7_port)
;
mult_125_AN1_6_6 : nor2 port map( a => mult_125_A_not_6_port, b =>
mult_125_B_not_6_port, outb => mult_125_ab_6_6_port)
;
mult_125_AN1_6_5 : nor2 port map( a => mult_125_A_not_6_port, b =>
mult_125_B_not_5_port, outb => mult_125_ab_6_5_port)
;
mult_125_AN1_6_4 : nor2 port map( a => mult_125_A_not_6_port, b =>
mult_125_B_not_4_port, outb => mult_125_ab_6_4_port)
;
mult_125_AN1_6_3 : nor2 port map( a => mult_125_A_not_6_port, b =>
mult_125_B_not_3_port, outb => mult_125_ab_6_3_port)
;
mult_125_AN1_6_2 : nor2 port map( a => mult_125_A_not_6_port, b =>
mult_125_B_not_2_port, outb => mult_125_ab_6_2_port)
;
mult_125_AN1_6_1 : nor2 port map( a => mult_125_A_not_6_port, b =>
mult_125_B_not_1_port, outb => mult_125_ab_6_1_port)
;
mult_125_AN1_6_0_0 : nor2 port map( a => mult_125_A_not_6_port, b =>
mult_125_B_not_0_port, outb => mult_125_ab_6_0_port)
;
mult_125_AN2_5_15 : nor2 port map( a => mult_125_A_notx_5_port, b =>
mult_125_B_not_15_port, outb =>
mult_125_ab_5_15_port);
mult_125_AN1_5_14 : nor2 port map( a => mult_125_A_not_5_port, b =>
mult_125_B_not_14_port, outb =>
mult_125_ab_5_14_port);
mult_125_AN1_5_13 : nor2 port map( a => mult_125_A_not_5_port, b =>
mult_125_B_not_13_port, outb =>
mult_125_ab_5_13_port);
mult_125_AN1_5_12 : nor2 port map( a => mult_125_A_not_5_port, b =>
mult_125_B_not_12_port, outb =>
mult_125_ab_5_12_port);
mult_125_AN1_5_11 : nor2 port map( a => mult_125_A_not_5_port, b =>
mult_125_B_not_11_port, outb =>
mult_125_ab_5_11_port);
mult_125_AN1_5_10 : nor2 port map( a => mult_125_A_not_5_port, b =>
mult_125_B_not_10_port, outb =>
mult_125_ab_5_10_port);
mult_125_AN1_5_9 : nor2 port map( a => mult_125_A_not_5_port, b =>
mult_125_B_not_9_port, outb => mult_125_ab_5_9_port)
;
mult_125_AN1_5_8 : nor2 port map( a => mult_125_A_not_5_port, b =>
mult_125_B_not_8_port, outb => mult_125_ab_5_8_port)
;
mult_125_AN1_5_7 : nor2 port map( a => mult_125_A_not_5_port, b =>
mult_125_B_not_7_port, outb => mult_125_ab_5_7_port)
;
mult_125_AN1_5_6 : nor2 port map( a => mult_125_A_not_5_port, b =>
mult_125_B_not_6_port, outb => mult_125_ab_5_6_port)
;
mult_125_AN1_5_5 : nor2 port map( a => mult_125_A_not_5_port, b =>
mult_125_B_not_5_port, outb => mult_125_ab_5_5_port)
;
mult_125_AN1_5_4 : nor2 port map( a => mult_125_A_not_5_port, b =>
mult_125_B_not_4_port, outb => mult_125_ab_5_4_port)
;
mult_125_AN1_5_3 : nor2 port map( a => mult_125_A_not_5_port, b =>
mult_125_B_not_3_port, outb => mult_125_ab_5_3_port)
;
mult_125_AN1_5_2 : nor2 port map( a => mult_125_A_not_5_port, b =>
mult_125_B_not_2_port, outb => mult_125_ab_5_2_port)
;
mult_125_AN1_5_1 : nor2 port map( a => mult_125_A_not_5_port, b =>
mult_125_B_not_1_port, outb => mult_125_ab_5_1_port)
;
mult_125_AN1_5_0_0 : nor2 port map( a => mult_125_A_not_5_port, b =>
mult_125_B_not_0_port, outb => mult_125_ab_5_0_port)
;
mult_125_AN2_4_15 : nor2 port map( a => mult_125_A_notx_4_port, b =>
mult_125_B_not_15_port, outb =>
mult_125_ab_4_15_port);
mult_125_AN1_4_14 : nor2 port map( a => mult_125_A_not_4_port, b =>
mult_125_B_not_14_port, outb =>
mult_125_ab_4_14_port);
mult_125_AN1_4_13 : nor2 port map( a => mult_125_A_not_4_port, b =>
mult_125_B_not_13_port, outb =>
mult_125_ab_4_13_port);
mult_125_AN1_4_12 : nor2 port map( a => mult_125_A_not_4_port, b =>
mult_125_B_not_12_port, outb =>
mult_125_ab_4_12_port);
mult_125_AN1_4_11 : nor2 port map( a => mult_125_A_not_4_port, b =>
mult_125_B_not_11_port, outb =>
mult_125_ab_4_11_port);
mult_125_AN1_4_10 : nor2 port map( a => mult_125_A_not_4_port, b =>
mult_125_B_not_10_port, outb =>
mult_125_ab_4_10_port);
mult_125_AN1_4_9 : nor2 port map( a => mult_125_A_not_4_port, b =>
mult_125_B_not_9_port, outb => mult_125_ab_4_9_port)
;
mult_125_AN1_4_8 : nor2 port map( a => mult_125_A_not_4_port, b =>
mult_125_B_not_8_port, outb => mult_125_ab_4_8_port)
;
mult_125_AN1_4_7 : nor2 port map( a => mult_125_A_not_4_port, b =>
mult_125_B_not_7_port, outb => mult_125_ab_4_7_port)
;
mult_125_AN1_4_6 : nor2 port map( a => mult_125_A_not_4_port, b =>
mult_125_B_not_6_port, outb => mult_125_ab_4_6_port)
;
mult_125_AN1_4_5 : nor2 port map( a => mult_125_A_not_4_port, b =>
mult_125_B_not_5_port, outb => mult_125_ab_4_5_port)
;
mult_125_AN1_4_4 : nor2 port map( a => mult_125_A_not_4_port, b =>
mult_125_B_not_4_port, outb => mult_125_ab_4_4_port)
;
mult_125_AN1_4_3 : nor2 port map( a => mult_125_A_not_4_port, b =>
mult_125_B_not_3_port, outb => mult_125_ab_4_3_port)
;
mult_125_AN1_4_2 : nor2 port map( a => mult_125_A_not_4_port, b =>
mult_125_B_not_2_port, outb => mult_125_ab_4_2_port)
;
mult_125_AN1_4_1 : nor2 port map( a => mult_125_A_not_4_port, b =>
mult_125_B_not_1_port, outb => mult_125_ab_4_1_port)
;
mult_125_AN1_4_0_0 : nor2 port map( a => mult_125_A_not_4_port, b =>
mult_125_B_not_0_port, outb => mult_125_ab_4_0_port)
;
mult_125_AN2_3_15 : nor2 port map( a => mult_125_A_notx_3_port, b =>
mult_125_B_not_15_port, outb =>
mult_125_ab_3_15_port);
mult_125_AN1_3_14 : nor2 port map( a => mult_125_A_not_3_port, b =>
mult_125_B_not_14_port, outb =>
mult_125_ab_3_14_port);
mult_125_AN1_3_13 : nor2 port map( a => mult_125_A_not_3_port, b =>
mult_125_B_not_13_port, outb =>
mult_125_ab_3_13_port);
mult_125_AN1_3_12 : nor2 port map( a => mult_125_A_not_3_port, b =>
mult_125_B_not_12_port, outb =>
mult_125_ab_3_12_port);
mult_125_AN1_3_11 : nor2 port map( a => mult_125_A_not_3_port, b =>
mult_125_B_not_11_port, outb =>
mult_125_ab_3_11_port);
mult_125_AN1_3_10 : nor2 port map( a => mult_125_A_not_3_port, b =>
mult_125_B_not_10_port, outb =>
mult_125_ab_3_10_port);
mult_125_AN1_3_9 : nor2 port map( a => mult_125_A_not_3_port, b =>
mult_125_B_not_9_port, outb => mult_125_ab_3_9_port)
;
mult_125_AN1_3_8 : nor2 port map( a => mult_125_A_not_3_port, b =>
mult_125_B_not_8_port, outb => mult_125_ab_3_8_port)
;
mult_125_AN1_3_7 : nor2 port map( a => mult_125_A_not_3_port, b =>
mult_125_B_not_7_port, outb => mult_125_ab_3_7_port)
;
mult_125_AN1_3_6 : nor2 port map( a => mult_125_A_not_3_port, b =>
mult_125_B_not_6_port, outb => mult_125_ab_3_6_port)
;
mult_125_AN1_3_5 : nor2 port map( a => mult_125_A_not_3_port, b =>
mult_125_B_not_5_port, outb => mult_125_ab_3_5_port)
;
mult_125_AN1_3_4 : nor2 port map( a => mult_125_A_not_3_port, b =>
mult_125_B_not_4_port, outb => mult_125_ab_3_4_port)
;
mult_125_AN1_3_3 : nor2 port map( a => mult_125_A_not_3_port, b =>
mult_125_B_not_3_port, outb => mult_125_ab_3_3_port)
;
mult_125_AN1_3_2 : nor2 port map( a => mult_125_A_not_3_port, b =>
mult_125_B_not_2_port, outb => mult_125_ab_3_2_port)
;
mult_125_AN1_3_1 : nor2 port map( a => mult_125_A_not_3_port, b =>
mult_125_B_not_1_port, outb => mult_125_ab_3_1_port)
;
mult_125_AN1_3_0_0 : nor2 port map( a => mult_125_A_not_3_port, b =>
mult_125_B_not_0_port, outb => mult_125_ab_3_0_port)
;
mult_125_AN2_2_15 : nor2 port map( a => mult_125_A_notx_2_port, b =>
mult_125_B_not_15_port, outb =>
mult_125_ab_2_15_port);
mult_125_AN1_2_14 : nor2 port map( a => mult_125_A_not_2_port, b =>
mult_125_B_not_14_port, outb =>
mult_125_ab_2_14_port);
mult_125_AN1_2_13 : nor2 port map( a => mult_125_A_not_2_port, b =>
mult_125_B_not_13_port, outb =>
mult_125_ab_2_13_port);
mult_125_AN1_2_12 : nor2 port map( a => mult_125_A_not_2_port, b =>
mult_125_B_not_12_port, outb =>
mult_125_ab_2_12_port);
mult_125_AN1_2_11 : nor2 port map( a => mult_125_A_not_2_port, b =>
mult_125_B_not_11_port, outb =>
mult_125_ab_2_11_port);
mult_125_AN1_2_10 : nor2 port map( a => mult_125_A_not_2_port, b =>
mult_125_B_not_10_port, outb =>
mult_125_ab_2_10_port);
mult_125_AN1_2_9 : nor2 port map( a => mult_125_A_not_2_port, b =>
mult_125_B_not_9_port, outb => mult_125_ab_2_9_port)
;
mult_125_AN1_2_8 : nor2 port map( a => mult_125_A_not_2_port, b =>
mult_125_B_not_8_port, outb => mult_125_ab_2_8_port)
;
mult_125_AN1_2_7 : nor2 port map( a => mult_125_A_not_2_port, b =>
mult_125_B_not_7_port, outb => mult_125_ab_2_7_port)
;
mult_125_AN1_2_6 : nor2 port map( a => mult_125_A_not_2_port, b =>
mult_125_B_not_6_port, outb => mult_125_ab_2_6_port)
;
mult_125_AN1_2_5 : nor2 port map( a => mult_125_A_not_2_port, b =>
mult_125_B_not_5_port, outb => mult_125_ab_2_5_port)
;
mult_125_AN1_2_4 : nor2 port map( a => mult_125_A_not_2_port, b =>
mult_125_B_not_4_port, outb => mult_125_ab_2_4_port)
;
mult_125_AN1_2_3 : nor2 port map( a => mult_125_A_not_2_port, b =>
mult_125_B_not_3_port, outb => mult_125_ab_2_3_port)
;
mult_125_AN1_2_2 : nor2 port map( a => mult_125_A_not_2_port, b =>
mult_125_B_not_2_port, outb => mult_125_ab_2_2_port)
;
mult_125_AN1_2_1 : nor2 port map( a => mult_125_A_not_2_port, b =>
mult_125_B_not_1_port, outb => mult_125_ab_2_1_port)
;
mult_125_AN1_2_0_0 : nor2 port map( a => mult_125_A_not_2_port, b =>
mult_125_B_not_0_port, outb => mult_125_ab_2_0_port)
;
mult_125_AN2_1_15 : nor2 port map( a => mult_125_A_notx_1_port, b =>
mult_125_B_not_15_port, outb =>
mult_125_ab_1_15_port);
mult_125_AN1_1_14 : nor2 port map( a => mult_125_A_not_1_port, b =>
mult_125_B_not_14_port, outb =>
mult_125_ab_1_14_port);
mult_125_AN1_1_13 : nor2 port map( a => mult_125_A_not_1_port, b =>
mult_125_B_not_13_port, outb =>
mult_125_ab_1_13_port);
mult_125_AN1_1_12 : nor2 port map( a => mult_125_A_not_1_port, b =>
mult_125_B_not_12_port, outb =>
mult_125_ab_1_12_port);
mult_125_AN1_1_11 : nor2 port map( a => mult_125_A_not_1_port, b =>
mult_125_B_not_11_port, outb =>
mult_125_ab_1_11_port);
mult_125_AN1_1_10 : nor2 port map( a => mult_125_A_not_1_port, b =>
mult_125_B_not_10_port, outb =>
mult_125_ab_1_10_port);
mult_125_AN1_1_9 : nor2 port map( a => mult_125_A_not_1_port, b =>
mult_125_B_not_9_port, outb => mult_125_ab_1_9_port)
;
mult_125_AN1_1_8 : nor2 port map( a => mult_125_A_not_1_port, b =>
mult_125_B_not_8_port, outb => mult_125_ab_1_8_port)
;
mult_125_AN1_1_7 : nor2 port map( a => mult_125_A_not_1_port, b =>
mult_125_B_not_7_port, outb => mult_125_ab_1_7_port)
;
mult_125_AN1_1_6 : nor2 port map( a => mult_125_A_not_1_port, b =>
mult_125_B_not_6_port, outb => mult_125_ab_1_6_port)
;
mult_125_AN1_1_5 : nor2 port map( a => mult_125_A_not_1_port, b =>
mult_125_B_not_5_port, outb => mult_125_ab_1_5_port)
;
mult_125_AN1_1_4 : nor2 port map( a => mult_125_A_not_1_port, b =>
mult_125_B_not_4_port, outb => mult_125_ab_1_4_port)
;
mult_125_AN1_1_3 : nor2 port map( a => mult_125_A_not_1_port, b =>
mult_125_B_not_3_port, outb => mult_125_ab_1_3_port)
;
mult_125_AN1_1_2 : nor2 port map( a => mult_125_A_not_1_port, b =>
mult_125_B_not_2_port, outb => mult_125_ab_1_2_port)
;
mult_125_AN1_1_1 : nor2 port map( a => mult_125_A_not_1_port, b =>
mult_125_B_not_1_port, outb => mult_125_ab_1_1_port)
;
mult_125_AN1_1_0_0 : nor2 port map( a => mult_125_A_not_1_port, b =>
mult_125_B_not_0_port, outb => mult_125_ab_1_0_port)
;
mult_125_AN2_0_15 : nor2 port map( a => mult_125_A_notx_0_port, b =>
mult_125_B_not_15_port, outb =>
mult_125_ab_0_15_port);
mult_125_AN1_0_14 : nor2 port map( a => mult_125_A_not_0_port, b =>
mult_125_B_not_14_port, outb =>
mult_125_ab_0_14_port);
mult_125_AN1_0_13 : nor2 port map( a => mult_125_A_not_0_port, b =>
mult_125_B_not_13_port, outb =>
mult_125_ab_0_13_port);
mult_125_AN1_0_12 : nor2 port map( a => mult_125_A_not_0_port, b =>
mult_125_B_not_12_port, outb =>
mult_125_ab_0_12_port);
mult_125_AN1_0_11 : nor2 port map( a => mult_125_A_not_0_port, b =>
mult_125_B_not_11_port, outb =>
mult_125_ab_0_11_port);
mult_125_AN1_0_10 : nor2 port map( a => mult_125_A_not_0_port, b =>
mult_125_B_not_10_port, outb =>
mult_125_ab_0_10_port);
mult_125_AN1_0_9 : nor2 port map( a => mult_125_A_not_0_port, b =>
mult_125_B_not_9_port, outb => mult_125_ab_0_9_port)
;
mult_125_AN1_0_8 : nor2 port map( a => mult_125_A_not_0_port, b =>
mult_125_B_not_8_port, outb => mult_125_ab_0_8_port)
;
mult_125_AN1_0_7 : nor2 port map( a => mult_125_A_not_0_port, b =>
mult_125_B_not_7_port, outb => mult_125_ab_0_7_port)
;
mult_125_AN1_0_6 : nor2 port map( a => mult_125_A_not_0_port, b =>
mult_125_B_not_6_port, outb => mult_125_ab_0_6_port)
;
mult_125_AN1_0_5 : nor2 port map( a => mult_125_A_not_0_port, b =>
mult_125_B_not_5_port, outb => mult_125_ab_0_5_port)
;
mult_125_AN1_0_4 : nor2 port map( a => mult_125_A_not_0_port, b =>
mult_125_B_not_4_port, outb => mult_125_ab_0_4_port)
;
mult_125_AN1_0_3 : nor2 port map( a => mult_125_A_not_0_port, b =>
mult_125_B_not_3_port, outb => mult_125_ab_0_3_port)
;
mult_125_AN1_0_2 : nor2 port map( a => mult_125_A_not_0_port, b =>
mult_125_B_not_2_port, outb => mult_125_ab_0_2_port)
;
mult_125_AN1_0_1 : nor2 port map( a => mult_125_A_not_0_port, b =>
mult_125_B_not_1_port, outb => mult_125_ab_0_1_port)
;
mult_125_AN1_0_0_0 : nor2 port map( a => mult_125_A_not_0_port, b =>
mult_125_B_not_0_port, outb =>
multiplier_sigs_0_0_port);
mult_125_G4_FS_1_U6_1_1_3 : oai12 port map( b => n5657, c => n5658, a =>
n5659, outb => mult_125_G4_FS_1_C_1_7_0_port);
mult_125_G4_FS_1_U6_1_1_2 : oai12 port map( b => n5654, c => n5655, a =>
n5656, outb => mult_125_G4_FS_1_C_1_6_0_port);
mult_125_G4_FS_1_U6_1_1_1 : oai12 port map( b => n5651, c => n5652, a =>
n5653, outb => mult_125_G4_FS_1_C_1_5_0_port);
mult_125_G4_FS_1_U6_0_7_1 : oai12 port map( b => n5648, c => n5649, a =>
mult_125_G4_FS_1_G_n_int_0_7_0_port, outb =>
mult_125_G4_FS_1_C_1_7_1_port);
mult_125_G4_FS_1_U3_C_0_7_1 : xor2 port map( a =>
mult_125_G4_FS_1_PG_int_0_7_1_port, b =>
mult_125_G4_FS_1_C_1_7_1_port, outb =>
multiplier_sigs_3_31_port);
mult_125_G4_FS_1_U3_B_0_7_1 : nand2 port map( a =>
mult_125_G4_FS_1_G_n_int_0_7_1_port, b =>
mult_125_G4_FS_1_P_0_7_1_port, outb => n5647);
mult_125_G4_FS_1_U2_0_7_1 : nand2 port map( a => mult_125_G4_A1_29_port, b
=> mult_125_G4_A2_29_port, outb =>
mult_125_G4_FS_1_G_n_int_0_7_1_port);
mult_125_G4_FS_1_U1_0_7_1 : nand2 port map( a => n5645, b => n5646, outb =>
mult_125_G4_FS_1_P_0_7_1_port);
mult_125_G4_FS_1_U3_C_0_7_0 : xor2 port map( a =>
mult_125_G4_FS_1_PG_int_0_7_0_port, b =>
mult_125_G4_FS_1_C_1_7_0_port, outb =>
multiplier_sigs_3_30_port);
mult_125_G4_FS_1_U3_B_0_7_0 : nand2 port map( a =>
mult_125_G4_FS_1_G_n_int_0_7_0_port, b =>
mult_125_G4_FS_1_TEMP_P_0_7_0_port, outb => n5644);
mult_125_G4_FS_1_U2_0_7_0 : nand2 port map( a => mult_125_G4_A1_28_port, b
=> mult_125_G4_A2_28_port, outb =>
mult_125_G4_FS_1_G_n_int_0_7_0_port);
mult_125_G4_FS_1_U1_0_7_0 : nand2 port map( a => n5642, b => n5643, outb =>
mult_125_G4_FS_1_TEMP_P_0_7_0_port);
mult_125_G4_FS_1_U6_0_6_3 : oai12 port map( b => n5640, c => n5641, a =>
mult_125_G4_FS_1_G_n_int_0_6_2_port, outb =>
mult_125_G4_FS_1_C_1_6_3_port);
mult_125_G4_FS_1_U5_0_6_3 : oai12 port map( b => n5638, c => n5639, a =>
mult_125_G4_FS_1_G_n_int_0_6_3_port, outb =>
mult_125_G4_FS_1_G_1_1_2_port);
mult_125_G4_FS_1_U4_0_6_3 : nand2 port map( a =>
mult_125_G4_FS_1_TEMP_P_0_6_2_port, b =>
mult_125_G4_FS_1_P_0_6_3_port, outb => n5658);
mult_125_G4_FS_1_U3_C_0_6_3 : xor2 port map( a =>
mult_125_G4_FS_1_PG_int_0_6_3_port, b =>
mult_125_G4_FS_1_C_1_6_3_port, outb =>
multiplier_sigs_3_29_port);
mult_125_G4_FS_1_U3_B_0_6_3 : nand2 port map( a =>
mult_125_G4_FS_1_G_n_int_0_6_3_port, b =>
mult_125_G4_FS_1_P_0_6_3_port, outb => n5637);
mult_125_G4_FS_1_U2_0_6_3 : nand2 port map( a => mult_125_G4_A1_27_port, b
=> mult_125_G4_A2_27_port, outb =>
mult_125_G4_FS_1_G_n_int_0_6_3_port);
mult_125_G4_FS_1_U1_0_6_3 : nand2 port map( a => n5635, b => n5636, outb =>
mult_125_G4_FS_1_P_0_6_3_port);
mult_125_G4_FS_1_U6_0_6_2 : oai12 port map( b => n5633, c => n5634, a =>
mult_125_G4_FS_1_G_n_int_0_6_1_port, outb =>
mult_125_G4_FS_1_C_1_6_2_port);
mult_125_G4_FS_1_U5_0_6_2 : oai12 port map( b => n5632, c => n5641, a =>
mult_125_G4_FS_1_G_n_int_0_6_2_port, outb =>
mult_125_G4_FS_1_TEMP_G_0_6_2_port);
mult_125_G4_FS_1_U4_0_6_2 : nand2 port map( a =>
mult_125_G4_FS_1_TEMP_P_0_6_1_port, b =>
mult_125_G4_FS_1_P_0_6_2_port, outb => n5631);
mult_125_G4_FS_1_U3_C_0_6_2 : xor2 port map( a =>
mult_125_G4_FS_1_PG_int_0_6_2_port, b =>
mult_125_G4_FS_1_C_1_6_2_port, outb =>
multiplier_sigs_3_28_port);
mult_125_G4_FS_1_U3_B_0_6_2 : nand2 port map( a =>
mult_125_G4_FS_1_G_n_int_0_6_2_port, b =>
mult_125_G4_FS_1_P_0_6_2_port, outb => n5630);
mult_125_G4_FS_1_U2_0_6_2 : nand2 port map( a => mult_125_G4_A1_26_port, b
=> mult_125_G4_A2_26_port, outb =>
mult_125_G4_FS_1_G_n_int_0_6_2_port);
mult_125_G4_FS_1_U1_0_6_2 : nand2 port map( a => n5628, b => n5629, outb =>
mult_125_G4_FS_1_P_0_6_2_port);
mult_125_G4_FS_1_U6_0_6_1 : oai12 port map( b => n5657, c => n5627, a =>
mult_125_G4_FS_1_G_n_int_0_6_0_port, outb =>
mult_125_G4_FS_1_C_1_6_1_port);
mult_125_G4_FS_1_U5_0_6_1 : oai12 port map( b =>
mult_125_G4_FS_1_G_n_int_0_6_0_port, c => n5634, a
=> mult_125_G4_FS_1_G_n_int_0_6_1_port, outb =>
mult_125_G4_FS_1_TEMP_G_0_6_1_port);
mult_125_G4_FS_1_U4_0_6_1 : nand2 port map( a =>
mult_125_G4_FS_1_TEMP_P_0_6_0_port, b =>
mult_125_G4_FS_1_P_0_6_1_port, outb => n5626);
mult_125_G4_FS_1_U3_C_0_6_1 : xor2 port map( a =>
mult_125_G4_FS_1_PG_int_0_6_1_port, b =>
mult_125_G4_FS_1_C_1_6_1_port, outb =>
multiplier_sigs_3_27_port);
mult_125_G4_FS_1_U3_B_0_6_1 : nand2 port map( a =>
mult_125_G4_FS_1_G_n_int_0_6_1_port, b =>
mult_125_G4_FS_1_P_0_6_1_port, outb => n5625);
mult_125_G4_FS_1_U2_0_6_1 : nand2 port map( a => mult_125_G4_A1_25_port, b
=> mult_125_G4_A2_25_port, outb =>
mult_125_G4_FS_1_G_n_int_0_6_1_port);
mult_125_G4_FS_1_U1_0_6_1 : nand2 port map( a => n5623, b => n5624, outb =>
mult_125_G4_FS_1_P_0_6_1_port);
mult_125_G4_FS_1_U3_C_0_6_0 : xor2 port map( a =>
mult_125_G4_FS_1_PG_int_0_6_0_port, b =>
mult_125_G4_FS_1_C_1_6_0_port, outb =>
multiplier_sigs_3_26_port);
mult_125_G4_FS_1_U3_B_0_6_0 : nand2 port map( a =>
mult_125_G4_FS_1_G_n_int_0_6_0_port, b =>
mult_125_G4_FS_1_TEMP_P_0_6_0_port, outb => n5622);
mult_125_G4_FS_1_U2_0_6_0 : nand2 port map( a => mult_125_G4_A1_24_port, b
=> mult_125_G4_A2_24_port, outb =>
mult_125_G4_FS_1_G_n_int_0_6_0_port);
mult_125_G4_FS_1_U1_0_6_0 : nand2 port map( a => n5620, b => n5621, outb =>
mult_125_G4_FS_1_TEMP_P_0_6_0_port);
mult_125_G4_FS_1_U6_0_5_3 : oai12 port map( b => n5618, c => n5619, a =>
mult_125_G4_FS_1_G_n_int_0_5_2_port, outb =>
mult_125_G4_FS_1_C_1_5_3_port);
mult_125_G4_FS_1_U5_0_5_3 : oai12 port map( b => n5616, c => n5617, a =>
mult_125_G4_FS_1_G_n_int_0_5_3_port, outb =>
mult_125_G4_FS_1_G_1_1_1_port);
mult_125_G4_FS_1_U4_0_5_3 : nand2 port map( a =>
mult_125_G4_FS_1_TEMP_P_0_5_2_port, b =>
mult_125_G4_FS_1_P_0_5_3_port, outb => n5655);
mult_125_G4_FS_1_U3_C_0_5_3 : xor2 port map( a =>
mult_125_G4_FS_1_PG_int_0_5_3_port, b =>
mult_125_G4_FS_1_C_1_5_3_port, outb =>
multiplier_sigs_3_25_port);
mult_125_G4_FS_1_U3_B_0_5_3 : nand2 port map( a =>
mult_125_G4_FS_1_G_n_int_0_5_3_port, b =>
mult_125_G4_FS_1_P_0_5_3_port, outb => n5615);
mult_125_G4_FS_1_U2_0_5_3 : nand2 port map( a => mult_125_G4_A1_23_port, b
=> mult_125_G4_A2_23_port, outb =>
mult_125_G4_FS_1_G_n_int_0_5_3_port);
mult_125_G4_FS_1_U1_0_5_3 : nand2 port map( a => n5613, b => n5614, outb =>
mult_125_G4_FS_1_P_0_5_3_port);
mult_125_G4_FS_1_U6_0_5_2 : oai12 port map( b => n5611, c => n5612, a =>
mult_125_G4_FS_1_G_n_int_0_5_1_port, outb =>
mult_125_G4_FS_1_C_1_5_2_port);
mult_125_G4_FS_1_U5_0_5_2 : oai12 port map( b => n5610, c => n5619, a =>
mult_125_G4_FS_1_G_n_int_0_5_2_port, outb =>
mult_125_G4_FS_1_TEMP_G_0_5_2_port);
mult_125_G4_FS_1_U4_0_5_2 : nand2 port map( a =>
mult_125_G4_FS_1_TEMP_P_0_5_1_port, b =>
mult_125_G4_FS_1_P_0_5_2_port, outb => n5609);
mult_125_G4_FS_1_U3_C_0_5_2 : xor2 port map( a =>
mult_125_G4_FS_1_PG_int_0_5_2_port, b =>
mult_125_G4_FS_1_C_1_5_2_port, outb =>
multiplier_sigs_3_24_port);
mult_125_G4_FS_1_U3_B_0_5_2 : nand2 port map( a =>
mult_125_G4_FS_1_G_n_int_0_5_2_port, b =>
mult_125_G4_FS_1_P_0_5_2_port, outb => n5608);
mult_125_G4_FS_1_U2_0_5_2 : nand2 port map( a => mult_125_G4_A1_22_port, b
=> mult_125_G4_A2_22_port, outb =>
mult_125_G4_FS_1_G_n_int_0_5_2_port);
mult_125_G4_FS_1_U1_0_5_2 : nand2 port map( a => n5606, b => n5607, outb =>
mult_125_G4_FS_1_P_0_5_2_port);
mult_125_G4_FS_1_U6_0_5_1 : oai12 port map( b => n5654, c => n5605, a =>
mult_125_G4_FS_1_G_n_int_0_5_0_port, outb =>
mult_125_G4_FS_1_C_1_5_1_port);
mult_125_G4_FS_1_U5_0_5_1 : oai12 port map( b =>
mult_125_G4_FS_1_G_n_int_0_5_0_port, c => n5612, a
=> mult_125_G4_FS_1_G_n_int_0_5_1_port, outb =>
mult_125_G4_FS_1_TEMP_G_0_5_1_port);
mult_125_G4_FS_1_U4_0_5_1 : nand2 port map( a =>
mult_125_G4_FS_1_TEMP_P_0_5_0_port, b =>
mult_125_G4_FS_1_P_0_5_1_port, outb => n5604);
mult_125_G4_FS_1_U3_C_0_5_1 : xor2 port map( a =>
mult_125_G4_FS_1_PG_int_0_5_1_port, b =>
mult_125_G4_FS_1_C_1_5_1_port, outb =>
multiplier_sigs_3_23_port);
mult_125_G4_FS_1_U3_B_0_5_1 : nand2 port map( a =>
mult_125_G4_FS_1_G_n_int_0_5_1_port, b =>
mult_125_G4_FS_1_P_0_5_1_port, outb => n5603);
mult_125_G4_FS_1_U2_0_5_1 : nand2 port map( a => mult_125_G4_A1_21_port, b
=> mult_125_G4_A2_21_port, outb =>
mult_125_G4_FS_1_G_n_int_0_5_1_port);
mult_125_G4_FS_1_U1_0_5_1 : nand2 port map( a => n5601, b => n5602, outb =>
mult_125_G4_FS_1_P_0_5_1_port);
mult_125_G4_FS_1_U3_C_0_5_0 : xor2 port map( a =>
mult_125_G4_FS_1_PG_int_0_5_0_port, b =>
mult_125_G4_FS_1_C_1_5_0_port, outb =>
multiplier_sigs_3_22_port);
mult_125_G4_FS_1_U3_B_0_5_0 : nand2 port map( a =>
mult_125_G4_FS_1_G_n_int_0_5_0_port, b =>
mult_125_G4_FS_1_TEMP_P_0_5_0_port, outb => n5600);
mult_125_G4_FS_1_U2_0_5_0 : nand2 port map( a => mult_125_G4_A1_20_port, b
=> mult_125_G4_A2_20_port, outb =>
mult_125_G4_FS_1_G_n_int_0_5_0_port);
mult_125_G4_FS_1_U1_0_5_0 : nand2 port map( a => n5598, b => n5599, outb =>
mult_125_G4_FS_1_TEMP_P_0_5_0_port);
mult_125_G4_FS_1_U6_0_4_3 : oai12 port map( b => n5596, c => n5597, a =>
mult_125_G4_FS_1_G_n_int_0_4_2_port, outb =>
mult_125_G4_FS_1_C_1_4_3_port);
mult_125_G4_FS_1_U5_0_4_3 : oai12 port map( b => n5594, c => n5595, a =>
mult_125_G4_FS_1_G_n_int_0_4_3_port, outb =>
mult_125_G4_FS_1_G_1_1_0_port);
mult_125_G4_FS_1_U4_0_4_3 : nand2 port map( a =>
mult_125_G4_FS_1_TEMP_P_0_4_2_port, b =>
mult_125_G4_FS_1_P_0_4_3_port, outb => n5652);
mult_125_G4_FS_1_U3_C_0_4_3 : xor2 port map( a =>
mult_125_G4_FS_1_PG_int_0_4_3_port, b =>
mult_125_G4_FS_1_C_1_4_3_port, outb =>
multiplier_sigs_3_21_port);
mult_125_G4_FS_1_U3_B_0_4_3 : nand2 port map( a =>
mult_125_G4_FS_1_G_n_int_0_4_3_port, b =>
mult_125_G4_FS_1_P_0_4_3_port, outb => n5593);
mult_125_G4_FS_1_U2_0_4_3 : nand2 port map( a => mult_125_G4_A1_19_port, b
=> mult_125_G4_A2_19_port, outb =>
mult_125_G4_FS_1_G_n_int_0_4_3_port);
mult_125_G4_FS_1_U1_0_4_3 : nand2 port map( a => n5591, b => n5592, outb =>
mult_125_G4_FS_1_P_0_4_3_port);
mult_125_G4_FS_1_U6_0_4_2 : oai12 port map( b => n5589, c => n5590, a =>
mult_125_G4_FS_1_G_n_int_0_4_1_port, outb =>
mult_125_G4_FS_1_C_1_4_2_port);
mult_125_G4_FS_1_U5_0_4_2 : oai12 port map( b => n5588, c => n5597, a =>
mult_125_G4_FS_1_G_n_int_0_4_2_port, outb =>
mult_125_G4_FS_1_TEMP_G_0_4_2_port);
mult_125_G4_FS_1_U4_0_4_2 : nand2 port map( a =>
mult_125_G4_FS_1_TEMP_P_0_4_1_port, b =>
mult_125_G4_FS_1_P_0_4_2_port, outb => n5587);
mult_125_G4_FS_1_U3_C_0_4_2 : xor2 port map( a =>
mult_125_G4_FS_1_PG_int_0_4_2_port, b =>
mult_125_G4_FS_1_C_1_4_2_port, outb =>
multiplier_sigs_3_20_port);
mult_125_G4_FS_1_U3_B_0_4_2 : nand2 port map( a =>
mult_125_G4_FS_1_G_n_int_0_4_2_port, b =>
mult_125_G4_FS_1_P_0_4_2_port, outb => n5586);
mult_125_G4_FS_1_U2_0_4_2 : nand2 port map( a => mult_125_G4_A1_18_port, b
=> mult_125_G4_A2_18_port, outb =>
mult_125_G4_FS_1_G_n_int_0_4_2_port);
mult_125_G4_FS_1_U1_0_4_2 : nand2 port map( a => n5584, b => n5585, outb =>
mult_125_G4_FS_1_P_0_4_2_port);
mult_125_G4_FS_1_U6_0_4_1 : oai12 port map( b => n5651, c => n5583, a =>
mult_125_G4_FS_1_G_n_int_0_4_0_port, outb =>
mult_125_G4_FS_1_C_1_4_1_port);
mult_125_G4_FS_1_U5_0_4_1 : oai12 port map( b =>
mult_125_G4_FS_1_G_n_int_0_4_0_port, c => n5590, a
=> mult_125_G4_FS_1_G_n_int_0_4_1_port, outb =>
mult_125_G4_FS_1_TEMP_G_0_4_1_port);
mult_125_G4_FS_1_U4_0_4_1 : nand2 port map( a =>
mult_125_G4_FS_1_TEMP_P_0_4_0_port, b =>
mult_125_G4_FS_1_P_0_4_1_port, outb => n5582);
mult_125_G4_FS_1_U3_C_0_4_1 : xor2 port map( a =>
mult_125_G4_FS_1_PG_int_0_4_1_port, b =>
mult_125_G4_FS_1_C_1_4_1_port, outb =>
multiplier_sigs_3_19_port);
mult_125_G4_FS_1_U3_B_0_4_1 : nand2 port map( a =>
mult_125_G4_FS_1_G_n_int_0_4_1_port, b =>
mult_125_G4_FS_1_P_0_4_1_port, outb => n5581);
mult_125_G4_FS_1_U2_0_4_1 : nand2 port map( a => mult_125_G4_A1_17_port, b
=> mult_125_G4_A2_17_port, outb =>
mult_125_G4_FS_1_G_n_int_0_4_1_port);
mult_125_G4_FS_1_U1_0_4_1 : nand2 port map( a => n5579, b => n5580, outb =>
mult_125_G4_FS_1_P_0_4_1_port);
mult_125_G4_FS_1_U3_C_0_4_0 : xor2 port map( a =>
mult_125_G4_FS_1_PG_int_0_4_0_port, b =>
mult_125_G4_FS_1_C_1_4_0_port, outb =>
multiplier_sigs_3_18_port);
mult_125_G4_FS_1_U3_B_0_4_0 : nand2 port map( a =>
mult_125_G4_FS_1_G_n_int_0_4_0_port, b =>
mult_125_G4_FS_1_TEMP_P_0_4_0_port, outb => n5578);
mult_125_G4_FS_1_U2_0_4_0 : nand2 port map( a => mult_125_G4_A1_16_port, b
=> mult_125_G4_A2_16_port, outb =>
mult_125_G4_FS_1_G_n_int_0_4_0_port);
mult_125_G4_FS_1_U1_0_4_0 : nand2 port map( a => n5576, b => n5577, outb =>
mult_125_G4_FS_1_TEMP_P_0_4_0_port);
mult_125_G4_FS_1_U5_0_3_3 : oai12 port map( b => n5574, c => n5575, a =>
mult_125_G4_FS_1_G_n_int_0_3_3_port, outb =>
mult_125_G4_FS_1_G_1_0_3_port);
mult_125_G4_FS_1_U3_C_0_3_3 : xor2 port map( a =>
mult_125_G4_FS_1_PG_int_0_3_3_port, b =>
mult_125_G4_FS_1_C_1_3_3_port, outb =>
multiplier_sigs_3_17_port);
mult_125_G4_FS_1_U3_B_0_3_3 : nand2 port map( a =>
mult_125_G4_FS_1_G_n_int_0_3_3_port, b =>
mult_125_G4_FS_1_P_0_3_3_port, outb => n5573);
mult_125_G4_FS_1_U2_0_3_3 : nand2 port map( a => mult_125_G4_A1_15_port, b
=> mult_125_G4_A2_15_port, outb =>
mult_125_G4_FS_1_G_n_int_0_3_3_port);
mult_125_G4_FS_1_U1_0_3_3 : nand2 port map( a => n5571, b => n5572, outb =>
mult_125_G4_FS_1_P_0_3_3_port);
mult_125_G4_FS_1_U3_B_0_3_2 : nand2 port map( a =>
mult_125_G4_FS_1_G_n_int_0_3_2_port, b =>
mult_125_G4_FS_1_P_0_3_2_port, outb => n5570);
mult_125_G4_FS_1_U2_0_3_2 : nand2 port map( a => mult_125_G4_A1_14_port, b
=> mult_125_G4_A2_14_port, outb =>
mult_125_G4_FS_1_G_n_int_0_3_2_port);
mult_125_G4_FS_1_U1_0_3_2 : nand2 port map( a => n5568, b => n5569, outb =>
mult_125_G4_FS_1_P_0_3_2_port);
mult_125_G4_AN1_15 : inv port map( inb => coefficient_mem_array_3_15_port,
outb => mult_125_G4_A_not_15_port);
mult_125_G4_AN1_14 : inv port map( inb => coefficient_mem_array_3_14_port,
outb => mult_125_G4_A_not_14_port);
mult_125_G4_AN1_13 : inv port map( inb => coefficient_mem_array_3_13_port,
outb => mult_125_G4_A_not_13_port);
mult_125_G4_AN1_12 : inv port map( inb => coefficient_mem_array_3_12_port,
outb => mult_125_G4_A_not_12_port);
mult_125_G4_AN1_11 : inv port map( inb => coefficient_mem_array_3_11_port,
outb => mult_125_G4_A_not_11_port);
mult_125_G4_AN1_10 : inv port map( inb => coefficient_mem_array_3_10_port,
outb => mult_125_G4_A_not_10_port);
mult_125_G4_AN1_9 : inv port map( inb => coefficient_mem_array_3_9_port,
outb => mult_125_G4_A_not_9_port);
mult_125_G4_AN1_8 : inv port map( inb => coefficient_mem_array_3_8_port,
outb => mult_125_G4_A_not_8_port);
mult_125_G4_AN1_7 : inv port map( inb => coefficient_mem_array_3_7_port,
outb => mult_125_G4_A_not_7_port);
mult_125_G4_AN1_6 : inv port map( inb => coefficient_mem_array_3_6_port,
outb => mult_125_G4_A_not_6_port);
mult_125_G4_AN1_5 : inv port map( inb => coefficient_mem_array_3_5_port,
outb => mult_125_G4_A_not_5_port);
mult_125_G4_AN1_4 : inv port map( inb => coefficient_mem_array_3_4_port,
outb => mult_125_G4_A_not_4_port);
mult_125_G4_AN1_3 : inv port map( inb => coefficient_mem_array_3_3_port,
outb => mult_125_G4_A_not_3_port);
mult_125_G4_AN1_2 : inv port map( inb => coefficient_mem_array_3_2_port,
outb => mult_125_G4_A_not_2_port);
mult_125_G4_AN1_1 : inv port map( inb => coefficient_mem_array_3_1_port,
outb => mult_125_G4_A_not_1_port);
mult_125_G4_AN1_0 : inv port map( inb => coefficient_mem_array_3_0_port,
outb => mult_125_G4_A_not_0_port);
mult_125_G4_AN1_15_0 : inv port map( inb => input_sample_mem_15_port, outb
=> mult_125_G4_B_not_15_port);
mult_125_G4_AN1_14_0 : inv port map( inb => input_sample_mem_14_port, outb
=> mult_125_G4_B_not_14_port);
mult_125_G4_AN1_13_0 : inv port map( inb => input_sample_mem_13_port, outb
=> mult_125_G4_B_not_13_port);
mult_125_G4_AN1_12_0 : inv port map( inb => input_sample_mem_12_port, outb
=> mult_125_G4_B_not_12_port);
mult_125_G4_AN1_11_0 : inv port map( inb => input_sample_mem_11_port, outb
=> mult_125_G4_B_not_11_port);
mult_125_G4_AN1_10_0 : inv port map( inb => input_sample_mem_10_port, outb
=> mult_125_G4_B_not_10_port);
mult_125_G4_AN1_9_0 : inv port map( inb => input_sample_mem_9_port, outb =>
mult_125_G4_B_not_9_port);
mult_125_G4_AN1_8_0 : inv port map( inb => input_sample_mem_8_port, outb =>
mult_125_G4_B_not_8_port);
mult_125_G4_AN1_7_0 : inv port map( inb => input_sample_mem_7_port, outb =>
mult_125_G4_B_not_7_port);
mult_125_G4_AN1_6_0 : inv port map( inb => input_sample_mem_6_port, outb =>
mult_125_G4_B_not_6_port);
mult_125_G4_AN1_5_0 : inv port map( inb => input_sample_mem_5_port, outb =>
mult_125_G4_B_not_5_port);
mult_125_G4_AN1_4_0 : inv port map( inb => input_sample_mem_4_port, outb =>
mult_125_G4_B_not_4_port);
mult_125_G4_AN1_3_0 : inv port map( inb => input_sample_mem_3_port, outb =>
mult_125_G4_B_not_3_port);
mult_125_G4_AN1_2_0 : inv port map( inb => input_sample_mem_2_port, outb =>
mult_125_G4_B_not_2_port);
mult_125_G4_AN1_1_0 : inv port map( inb => input_sample_mem_1_port, outb =>
mult_125_G4_B_not_1_port);
mult_125_G4_AN1_0_0 : inv port map( inb => input_sample_mem_0_port, outb =>
mult_125_G4_B_not_0_port);
mult_125_G4_AN1_15_15 : nor2 port map( a => mult_125_G4_A_not_15_port, b =>
mult_125_G4_B_not_15_port, outb =>
mult_125_G4_ab_15_15_port);
mult_125_G4_AN3_15_14 : nor2 port map( a => mult_125_G4_A_not_15_port, b =>
mult_125_G4_B_notx_14_port, outb =>
mult_125_G4_ab_15_14_port);
mult_125_G4_AN3_15_13 : nor2 port map( a => mult_125_G4_A_not_15_port, b =>
mult_125_G4_B_notx_13_port, outb =>
mult_125_G4_ab_15_13_port);
mult_125_G4_AN3_15_12 : nor2 port map( a => mult_125_G4_A_not_15_port, b =>
mult_125_G4_B_notx_12_port, outb =>
mult_125_G4_ab_15_12_port);
mult_125_G4_AN3_15_11 : nor2 port map( a => mult_125_G4_A_not_15_port, b =>
mult_125_G4_B_notx_11_port, outb =>
mult_125_G4_ab_15_11_port);
mult_125_G4_AN3_15_10 : nor2 port map( a => mult_125_G4_A_not_15_port, b =>
mult_125_G4_B_notx_10_port, outb =>
mult_125_G4_ab_15_10_port);
mult_125_G4_AN3_15_9 : nor2 port map( a => mult_125_G4_A_not_15_port, b =>
mult_125_G4_B_notx_9_port, outb =>
mult_125_G4_ab_15_9_port);
mult_125_G4_AN3_15_8 : nor2 port map( a => mult_125_G4_A_not_15_port, b =>
mult_125_G4_B_notx_8_port, outb =>
mult_125_G4_ab_15_8_port);
mult_125_G4_AN3_15_7 : nor2 port map( a => mult_125_G4_A_not_15_port, b =>
mult_125_G4_B_notx_7_port, outb =>
mult_125_G4_ab_15_7_port);
mult_125_G4_AN3_15_6 : nor2 port map( a => mult_125_G4_A_not_15_port, b =>
mult_125_G4_B_notx_6_port, outb =>
mult_125_G4_ab_15_6_port);
mult_125_G4_AN3_15_5 : nor2 port map( a => mult_125_G4_A_not_15_port, b =>
mult_125_G4_B_notx_5_port, outb =>
mult_125_G4_ab_15_5_port);
mult_125_G4_AN3_15_4 : nor2 port map( a => mult_125_G4_A_not_15_port, b =>
mult_125_G4_B_notx_4_port, outb =>
mult_125_G4_ab_15_4_port);
mult_125_G4_AN3_15_3 : nor2 port map( a => mult_125_G4_A_not_15_port, b =>
mult_125_G4_B_notx_3_port, outb =>
mult_125_G4_ab_15_3_port);
mult_125_G4_AN3_15_2 : nor2 port map( a => mult_125_G4_A_not_15_port, b =>
mult_125_G4_B_notx_2_port, outb =>
mult_125_G4_ab_15_2_port);
mult_125_G4_AN3_15_1 : nor2 port map( a => mult_125_G4_A_not_15_port, b =>
mult_125_G4_B_notx_1_port, outb =>
mult_125_G4_ab_15_1_port);
mult_125_G4_AN3_15_0 : nor2 port map( a => mult_125_G4_A_not_15_port, b =>
mult_125_G4_B_notx_0_port, outb =>
mult_125_G4_ab_15_0_port);
mult_125_G4_AN2_14_15 : nor2 port map( a => mult_125_G4_A_notx_14_port, b =>
mult_125_G4_B_not_15_port, outb =>
mult_125_G4_ab_14_15_port);
mult_125_G4_AN1_14_14 : nor2 port map( a => mult_125_G4_A_not_14_port, b =>
mult_125_G4_B_not_14_port, outb =>
mult_125_G4_ab_14_14_port);
mult_125_G4_AN1_14_13 : nor2 port map( a => mult_125_G4_A_not_14_port, b =>
mult_125_G4_B_not_13_port, outb =>
mult_125_G4_ab_14_13_port);
mult_125_G4_AN1_14_12 : nor2 port map( a => mult_125_G4_A_not_14_port, b =>
mult_125_G4_B_not_12_port, outb =>
mult_125_G4_ab_14_12_port);
mult_125_G4_AN1_14_11 : nor2 port map( a => mult_125_G4_A_not_14_port, b =>
mult_125_G4_B_not_11_port, outb =>
mult_125_G4_ab_14_11_port);
mult_125_G4_AN1_14_10 : nor2 port map( a => mult_125_G4_A_not_14_port, b =>
mult_125_G4_B_not_10_port, outb =>
mult_125_G4_ab_14_10_port);
mult_125_G4_AN1_14_9 : nor2 port map( a => mult_125_G4_A_not_14_port, b =>
mult_125_G4_B_not_9_port, outb =>
mult_125_G4_ab_14_9_port);
mult_125_G4_AN1_14_8 : nor2 port map( a => mult_125_G4_A_not_14_port, b =>
mult_125_G4_B_not_8_port, outb =>
mult_125_G4_ab_14_8_port);
mult_125_G4_AN1_14_7 : nor2 port map( a => mult_125_G4_A_not_14_port, b =>
mult_125_G4_B_not_7_port, outb =>
mult_125_G4_ab_14_7_port);
mult_125_G4_AN1_14_6 : nor2 port map( a => mult_125_G4_A_not_14_port, b =>
mult_125_G4_B_not_6_port, outb =>
mult_125_G4_ab_14_6_port);
mult_125_G4_AN1_14_5 : nor2 port map( a => mult_125_G4_A_not_14_port, b =>
mult_125_G4_B_not_5_port, outb =>
mult_125_G4_ab_14_5_port);
mult_125_G4_AN1_14_4 : nor2 port map( a => mult_125_G4_A_not_14_port, b =>
mult_125_G4_B_not_4_port, outb =>
mult_125_G4_ab_14_4_port);
mult_125_G4_AN1_14_3 : nor2 port map( a => mult_125_G4_A_not_14_port, b =>
mult_125_G4_B_not_3_port, outb =>
mult_125_G4_ab_14_3_port);
mult_125_G4_AN1_14_2 : nor2 port map( a => mult_125_G4_A_not_14_port, b =>
mult_125_G4_B_not_2_port, outb =>
mult_125_G4_ab_14_2_port);
mult_125_G4_AN1_14_1 : nor2 port map( a => mult_125_G4_A_not_14_port, b =>
mult_125_G4_B_not_1_port, outb =>
mult_125_G4_ab_14_1_port);
mult_125_G4_AN1_14_0_0 : nor2 port map( a => mult_125_G4_A_not_14_port, b =>
mult_125_G4_B_not_0_port, outb =>
mult_125_G4_ab_14_0_port);
mult_125_G4_AN2_13_15 : nor2 port map( a => mult_125_G4_A_notx_13_port, b =>
mult_125_G4_B_not_15_port, outb =>
mult_125_G4_ab_13_15_port);
mult_125_G4_AN1_13_14 : nor2 port map( a => mult_125_G4_A_not_13_port, b =>
mult_125_G4_B_not_14_port, outb =>
mult_125_G4_ab_13_14_port);
mult_125_G4_AN1_13_13 : nor2 port map( a => mult_125_G4_A_not_13_port, b =>
mult_125_G4_B_not_13_port, outb =>
mult_125_G4_ab_13_13_port);
mult_125_G4_AN1_13_12 : nor2 port map( a => mult_125_G4_A_not_13_port, b =>
mult_125_G4_B_not_12_port, outb =>
mult_125_G4_ab_13_12_port);
mult_125_G4_AN1_13_11 : nor2 port map( a => mult_125_G4_A_not_13_port, b =>
mult_125_G4_B_not_11_port, outb =>
mult_125_G4_ab_13_11_port);
mult_125_G4_AN1_13_10 : nor2 port map( a => mult_125_G4_A_not_13_port, b =>
mult_125_G4_B_not_10_port, outb =>
mult_125_G4_ab_13_10_port);
mult_125_G4_AN1_13_9 : nor2 port map( a => mult_125_G4_A_not_13_port, b =>
mult_125_G4_B_not_9_port, outb =>
mult_125_G4_ab_13_9_port);
mult_125_G4_AN1_13_8 : nor2 port map( a => mult_125_G4_A_not_13_port, b =>
mult_125_G4_B_not_8_port, outb =>
mult_125_G4_ab_13_8_port);
mult_125_G4_AN1_13_7 : nor2 port map( a => mult_125_G4_A_not_13_port, b =>
mult_125_G4_B_not_7_port, outb =>
mult_125_G4_ab_13_7_port);
mult_125_G4_AN1_13_6 : nor2 port map( a => mult_125_G4_A_not_13_port, b =>
mult_125_G4_B_not_6_port, outb =>
mult_125_G4_ab_13_6_port);
mult_125_G4_AN1_13_5 : nor2 port map( a => mult_125_G4_A_not_13_port, b =>
mult_125_G4_B_not_5_port, outb =>
mult_125_G4_ab_13_5_port);
mult_125_G4_AN1_13_4 : nor2 port map( a => mult_125_G4_A_not_13_port, b =>
mult_125_G4_B_not_4_port, outb =>
mult_125_G4_ab_13_4_port);
mult_125_G4_AN1_13_3 : nor2 port map( a => mult_125_G4_A_not_13_port, b =>
mult_125_G4_B_not_3_port, outb =>
mult_125_G4_ab_13_3_port);
mult_125_G4_AN1_13_2 : nor2 port map( a => mult_125_G4_A_not_13_port, b =>
mult_125_G4_B_not_2_port, outb =>
mult_125_G4_ab_13_2_port);
mult_125_G4_AN1_13_1 : nor2 port map( a => mult_125_G4_A_not_13_port, b =>
mult_125_G4_B_not_1_port, outb =>
mult_125_G4_ab_13_1_port);
mult_125_G4_AN1_13_0_0 : nor2 port map( a => mult_125_G4_A_not_13_port, b =>
mult_125_G4_B_not_0_port, outb =>
mult_125_G4_ab_13_0_port);
mult_125_G4_AN2_12_15 : nor2 port map( a => mult_125_G4_A_notx_12_port, b =>
mult_125_G4_B_not_15_port, outb =>
mult_125_G4_ab_12_15_port);
mult_125_G4_AN1_12_14 : nor2 port map( a => mult_125_G4_A_not_12_port, b =>
mult_125_G4_B_not_14_port, outb =>
mult_125_G4_ab_12_14_port);
mult_125_G4_AN1_12_13 : nor2 port map( a => mult_125_G4_A_not_12_port, b =>
mult_125_G4_B_not_13_port, outb =>
mult_125_G4_ab_12_13_port);
mult_125_G4_AN1_12_12 : nor2 port map( a => mult_125_G4_A_not_12_port, b =>
mult_125_G4_B_not_12_port, outb =>
mult_125_G4_ab_12_12_port);
mult_125_G4_AN1_12_11 : nor2 port map( a => mult_125_G4_A_not_12_port, b =>
mult_125_G4_B_not_11_port, outb =>
mult_125_G4_ab_12_11_port);
mult_125_G4_AN1_12_10 : nor2 port map( a => mult_125_G4_A_not_12_port, b =>
mult_125_G4_B_not_10_port, outb =>
mult_125_G4_ab_12_10_port);
mult_125_G4_AN1_12_9 : nor2 port map( a => mult_125_G4_A_not_12_port, b =>
mult_125_G4_B_not_9_port, outb =>
mult_125_G4_ab_12_9_port);
mult_125_G4_AN1_12_8 : nor2 port map( a => mult_125_G4_A_not_12_port, b =>
mult_125_G4_B_not_8_port, outb =>
mult_125_G4_ab_12_8_port);
mult_125_G4_AN1_12_7 : nor2 port map( a => mult_125_G4_A_not_12_port, b =>
mult_125_G4_B_not_7_port, outb =>
mult_125_G4_ab_12_7_port);
mult_125_G4_AN1_12_6 : nor2 port map( a => mult_125_G4_A_not_12_port, b =>
mult_125_G4_B_not_6_port, outb =>
mult_125_G4_ab_12_6_port);
mult_125_G4_AN1_12_5 : nor2 port map( a => mult_125_G4_A_not_12_port, b =>
mult_125_G4_B_not_5_port, outb =>
mult_125_G4_ab_12_5_port);
mult_125_G4_AN1_12_4 : nor2 port map( a => mult_125_G4_A_not_12_port, b =>
mult_125_G4_B_not_4_port, outb =>
mult_125_G4_ab_12_4_port);
mult_125_G4_AN1_12_3 : nor2 port map( a => mult_125_G4_A_not_12_port, b =>
mult_125_G4_B_not_3_port, outb =>
mult_125_G4_ab_12_3_port);
mult_125_G4_AN1_12_2 : nor2 port map( a => mult_125_G4_A_not_12_port, b =>
mult_125_G4_B_not_2_port, outb =>
mult_125_G4_ab_12_2_port);
mult_125_G4_AN1_12_1 : nor2 port map( a => mult_125_G4_A_not_12_port, b =>
mult_125_G4_B_not_1_port, outb =>
mult_125_G4_ab_12_1_port);
mult_125_G4_AN1_12_0_0 : nor2 port map( a => mult_125_G4_A_not_12_port, b =>
mult_125_G4_B_not_0_port, outb =>
mult_125_G4_ab_12_0_port);
mult_125_G4_AN2_11_15 : nor2 port map( a => mult_125_G4_A_notx_11_port, b =>
mult_125_G4_B_not_15_port, outb =>
mult_125_G4_ab_11_15_port);
mult_125_G4_AN1_11_14 : nor2 port map( a => mult_125_G4_A_not_11_port, b =>
mult_125_G4_B_not_14_port, outb =>
mult_125_G4_ab_11_14_port);
mult_125_G4_AN1_11_13 : nor2 port map( a => mult_125_G4_A_not_11_port, b =>
mult_125_G4_B_not_13_port, outb =>
mult_125_G4_ab_11_13_port);
mult_125_G4_AN1_11_12 : nor2 port map( a => mult_125_G4_A_not_11_port, b =>
mult_125_G4_B_not_12_port, outb =>
mult_125_G4_ab_11_12_port);
mult_125_G4_AN1_11_11 : nor2 port map( a => mult_125_G4_A_not_11_port, b =>
mult_125_G4_B_not_11_port, outb =>
mult_125_G4_ab_11_11_port);
mult_125_G4_AN1_11_10 : nor2 port map( a => mult_125_G4_A_not_11_port, b =>
mult_125_G4_B_not_10_port, outb =>
mult_125_G4_ab_11_10_port);
mult_125_G4_AN1_11_9 : nor2 port map( a => mult_125_G4_A_not_11_port, b =>
mult_125_G4_B_not_9_port, outb =>
mult_125_G4_ab_11_9_port);
mult_125_G4_AN1_11_8 : nor2 port map( a => mult_125_G4_A_not_11_port, b =>
mult_125_G4_B_not_8_port, outb =>
mult_125_G4_ab_11_8_port);
mult_125_G4_AN1_11_7 : nor2 port map( a => mult_125_G4_A_not_11_port, b =>
mult_125_G4_B_not_7_port, outb =>
mult_125_G4_ab_11_7_port);
mult_125_G4_AN1_11_6 : nor2 port map( a => mult_125_G4_A_not_11_port, b =>
mult_125_G4_B_not_6_port, outb =>
mult_125_G4_ab_11_6_port);
mult_125_G4_AN1_11_5 : nor2 port map( a => mult_125_G4_A_not_11_port, b =>
mult_125_G4_B_not_5_port, outb =>
mult_125_G4_ab_11_5_port);
mult_125_G4_AN1_11_4 : nor2 port map( a => mult_125_G4_A_not_11_port, b =>
mult_125_G4_B_not_4_port, outb =>
mult_125_G4_ab_11_4_port);
mult_125_G4_AN1_11_3 : nor2 port map( a => mult_125_G4_A_not_11_port, b =>
mult_125_G4_B_not_3_port, outb =>
mult_125_G4_ab_11_3_port);
mult_125_G4_AN1_11_2 : nor2 port map( a => mult_125_G4_A_not_11_port, b =>
mult_125_G4_B_not_2_port, outb =>
mult_125_G4_ab_11_2_port);
mult_125_G4_AN1_11_1 : nor2 port map( a => mult_125_G4_A_not_11_port, b =>
mult_125_G4_B_not_1_port, outb =>
mult_125_G4_ab_11_1_port);
mult_125_G4_AN1_11_0_0 : nor2 port map( a => mult_125_G4_A_not_11_port, b =>
mult_125_G4_B_not_0_port, outb =>
mult_125_G4_ab_11_0_port);
mult_125_G4_AN2_10_15 : nor2 port map( a => mult_125_G4_A_notx_10_port, b =>
mult_125_G4_B_not_15_port, outb =>
mult_125_G4_ab_10_15_port);
mult_125_G4_AN1_10_14 : nor2 port map( a => mult_125_G4_A_not_10_port, b =>
mult_125_G4_B_not_14_port, outb =>
mult_125_G4_ab_10_14_port);
mult_125_G4_AN1_10_13 : nor2 port map( a => mult_125_G4_A_not_10_port, b =>
mult_125_G4_B_not_13_port, outb =>
mult_125_G4_ab_10_13_port);
mult_125_G4_AN1_10_12 : nor2 port map( a => mult_125_G4_A_not_10_port, b =>
mult_125_G4_B_not_12_port, outb =>
mult_125_G4_ab_10_12_port);
mult_125_G4_AN1_10_11 : nor2 port map( a => mult_125_G4_A_not_10_port, b =>
mult_125_G4_B_not_11_port, outb =>
mult_125_G4_ab_10_11_port);
mult_125_G4_AN1_10_10 : nor2 port map( a => mult_125_G4_A_not_10_port, b =>
mult_125_G4_B_not_10_port, outb =>
mult_125_G4_ab_10_10_port);
mult_125_G4_AN1_10_9 : nor2 port map( a => mult_125_G4_A_not_10_port, b =>
mult_125_G4_B_not_9_port, outb =>
mult_125_G4_ab_10_9_port);
mult_125_G4_AN1_10_8 : nor2 port map( a => mult_125_G4_A_not_10_port, b =>
mult_125_G4_B_not_8_port, outb =>
mult_125_G4_ab_10_8_port);
mult_125_G4_AN1_10_7 : nor2 port map( a => mult_125_G4_A_not_10_port, b =>
mult_125_G4_B_not_7_port, outb =>
mult_125_G4_ab_10_7_port);
mult_125_G4_AN1_10_6 : nor2 port map( a => mult_125_G4_A_not_10_port, b =>
mult_125_G4_B_not_6_port, outb =>
mult_125_G4_ab_10_6_port);
mult_125_G4_AN1_10_5 : nor2 port map( a => mult_125_G4_A_not_10_port, b =>
mult_125_G4_B_not_5_port, outb =>
mult_125_G4_ab_10_5_port);
mult_125_G4_AN1_10_4 : nor2 port map( a => mult_125_G4_A_not_10_port, b =>
mult_125_G4_B_not_4_port, outb =>
mult_125_G4_ab_10_4_port);
mult_125_G4_AN1_10_3 : nor2 port map( a => mult_125_G4_A_not_10_port, b =>
mult_125_G4_B_not_3_port, outb =>
mult_125_G4_ab_10_3_port);
mult_125_G4_AN1_10_2 : nor2 port map( a => mult_125_G4_A_not_10_port, b =>
mult_125_G4_B_not_2_port, outb =>
mult_125_G4_ab_10_2_port);
mult_125_G4_AN1_10_1 : nor2 port map( a => mult_125_G4_A_not_10_port, b =>
mult_125_G4_B_not_1_port, outb =>
mult_125_G4_ab_10_1_port);
mult_125_G4_AN1_10_0_0 : nor2 port map( a => mult_125_G4_A_not_10_port, b =>
mult_125_G4_B_not_0_port, outb =>
mult_125_G4_ab_10_0_port);
mult_125_G4_AN2_9_15 : nor2 port map( a => mult_125_G4_A_notx_9_port, b =>
mult_125_G4_B_not_15_port, outb =>
mult_125_G4_ab_9_15_port);
mult_125_G4_AN1_9_14 : nor2 port map( a => mult_125_G4_A_not_9_port, b =>
mult_125_G4_B_not_14_port, outb =>
mult_125_G4_ab_9_14_port);
mult_125_G4_AN1_9_13 : nor2 port map( a => mult_125_G4_A_not_9_port, b =>
mult_125_G4_B_not_13_port, outb =>
mult_125_G4_ab_9_13_port);
mult_125_G4_AN1_9_12 : nor2 port map( a => mult_125_G4_A_not_9_port, b =>
mult_125_G4_B_not_12_port, outb =>
mult_125_G4_ab_9_12_port);
mult_125_G4_AN1_9_11 : nor2 port map( a => mult_125_G4_A_not_9_port, b =>
mult_125_G4_B_not_11_port, outb =>
mult_125_G4_ab_9_11_port);
mult_125_G4_AN1_9_10 : nor2 port map( a => mult_125_G4_A_not_9_port, b =>
mult_125_G4_B_not_10_port, outb =>
mult_125_G4_ab_9_10_port);
mult_125_G4_AN1_9_9 : nor2 port map( a => mult_125_G4_A_not_9_port, b =>
mult_125_G4_B_not_9_port, outb =>
mult_125_G4_ab_9_9_port);
mult_125_G4_AN1_9_8 : nor2 port map( a => mult_125_G4_A_not_9_port, b =>
mult_125_G4_B_not_8_port, outb =>
mult_125_G4_ab_9_8_port);
mult_125_G4_AN1_9_7 : nor2 port map( a => mult_125_G4_A_not_9_port, b =>
mult_125_G4_B_not_7_port, outb =>
mult_125_G4_ab_9_7_port);
mult_125_G4_AN1_9_6 : nor2 port map( a => mult_125_G4_A_not_9_port, b =>
mult_125_G4_B_not_6_port, outb =>
mult_125_G4_ab_9_6_port);
mult_125_G4_AN1_9_5 : nor2 port map( a => mult_125_G4_A_not_9_port, b =>
mult_125_G4_B_not_5_port, outb =>
mult_125_G4_ab_9_5_port);
mult_125_G4_AN1_9_4 : nor2 port map( a => mult_125_G4_A_not_9_port, b =>
mult_125_G4_B_not_4_port, outb =>
mult_125_G4_ab_9_4_port);
mult_125_G4_AN1_9_3 : nor2 port map( a => mult_125_G4_A_not_9_port, b =>
mult_125_G4_B_not_3_port, outb =>
mult_125_G4_ab_9_3_port);
mult_125_G4_AN1_9_2 : nor2 port map( a => mult_125_G4_A_not_9_port, b =>
mult_125_G4_B_not_2_port, outb =>
mult_125_G4_ab_9_2_port);
mult_125_G4_AN1_9_1 : nor2 port map( a => mult_125_G4_A_not_9_port, b =>
mult_125_G4_B_not_1_port, outb =>
mult_125_G4_ab_9_1_port);
mult_125_G4_AN1_9_0_0 : nor2 port map( a => mult_125_G4_A_not_9_port, b =>
mult_125_G4_B_not_0_port, outb =>
mult_125_G4_ab_9_0_port);
mult_125_G4_AN2_8_15 : nor2 port map( a => mult_125_G4_A_notx_8_port, b =>
mult_125_G4_B_not_15_port, outb =>
mult_125_G4_ab_8_15_port);
mult_125_G4_AN1_8_14 : nor2 port map( a => mult_125_G4_A_not_8_port, b =>
mult_125_G4_B_not_14_port, outb =>
mult_125_G4_ab_8_14_port);
mult_125_G4_AN1_8_13 : nor2 port map( a => mult_125_G4_A_not_8_port, b =>
mult_125_G4_B_not_13_port, outb =>
mult_125_G4_ab_8_13_port);
mult_125_G4_AN1_8_12 : nor2 port map( a => mult_125_G4_A_not_8_port, b =>
mult_125_G4_B_not_12_port, outb =>
mult_125_G4_ab_8_12_port);
mult_125_G4_AN1_8_11 : nor2 port map( a => mult_125_G4_A_not_8_port, b =>
mult_125_G4_B_not_11_port, outb =>
mult_125_G4_ab_8_11_port);
mult_125_G4_AN1_8_10 : nor2 port map( a => mult_125_G4_A_not_8_port, b =>
mult_125_G4_B_not_10_port, outb =>
mult_125_G4_ab_8_10_port);
mult_125_G4_AN1_8_9 : nor2 port map( a => mult_125_G4_A_not_8_port, b =>
mult_125_G4_B_not_9_port, outb =>
mult_125_G4_ab_8_9_port);
mult_125_G4_AN1_8_8 : nor2 port map( a => mult_125_G4_A_not_8_port, b =>
mult_125_G4_B_not_8_port, outb =>
mult_125_G4_ab_8_8_port);
mult_125_G4_AN1_8_7 : nor2 port map( a => mult_125_G4_A_not_8_port, b =>
mult_125_G4_B_not_7_port, outb =>
mult_125_G4_ab_8_7_port);
mult_125_G4_AN1_8_6 : nor2 port map( a => mult_125_G4_A_not_8_port, b =>
mult_125_G4_B_not_6_port, outb =>
mult_125_G4_ab_8_6_port);
mult_125_G4_AN1_8_5 : nor2 port map( a => mult_125_G4_A_not_8_port, b =>
mult_125_G4_B_not_5_port, outb =>
mult_125_G4_ab_8_5_port);
mult_125_G4_AN1_8_4 : nor2 port map( a => mult_125_G4_A_not_8_port, b =>
mult_125_G4_B_not_4_port, outb =>
mult_125_G4_ab_8_4_port);
mult_125_G4_AN1_8_3 : nor2 port map( a => mult_125_G4_A_not_8_port, b =>
mult_125_G4_B_not_3_port, outb =>
mult_125_G4_ab_8_3_port);
mult_125_G4_AN1_8_2 : nor2 port map( a => mult_125_G4_A_not_8_port, b =>
mult_125_G4_B_not_2_port, outb =>
mult_125_G4_ab_8_2_port);
mult_125_G4_AN1_8_1 : nor2 port map( a => mult_125_G4_A_not_8_port, b =>
mult_125_G4_B_not_1_port, outb =>
mult_125_G4_ab_8_1_port);
mult_125_G4_AN1_8_0_0 : nor2 port map( a => mult_125_G4_A_not_8_port, b =>
mult_125_G4_B_not_0_port, outb =>
mult_125_G4_ab_8_0_port);
mult_125_G4_AN2_7_15 : nor2 port map( a => mult_125_G4_A_notx_7_port, b =>
mult_125_G4_B_not_15_port, outb =>
mult_125_G4_ab_7_15_port);
mult_125_G4_AN1_7_14 : nor2 port map( a => mult_125_G4_A_not_7_port, b =>
mult_125_G4_B_not_14_port, outb =>
mult_125_G4_ab_7_14_port);
mult_125_G4_AN1_7_13 : nor2 port map( a => mult_125_G4_A_not_7_port, b =>
mult_125_G4_B_not_13_port, outb =>
mult_125_G4_ab_7_13_port);
mult_125_G4_AN1_7_12 : nor2 port map( a => mult_125_G4_A_not_7_port, b =>
mult_125_G4_B_not_12_port, outb =>
mult_125_G4_ab_7_12_port);
mult_125_G4_AN1_7_11 : nor2 port map( a => mult_125_G4_A_not_7_port, b =>
mult_125_G4_B_not_11_port, outb =>
mult_125_G4_ab_7_11_port);
mult_125_G4_AN1_7_10 : nor2 port map( a => mult_125_G4_A_not_7_port, b =>
mult_125_G4_B_not_10_port, outb =>
mult_125_G4_ab_7_10_port);
mult_125_G4_AN1_7_9 : nor2 port map( a => mult_125_G4_A_not_7_port, b =>
mult_125_G4_B_not_9_port, outb =>
mult_125_G4_ab_7_9_port);
mult_125_G4_AN1_7_8 : nor2 port map( a => mult_125_G4_A_not_7_port, b =>
mult_125_G4_B_not_8_port, outb =>
mult_125_G4_ab_7_8_port);
mult_125_G4_AN1_7_7 : nor2 port map( a => mult_125_G4_A_not_7_port, b =>
mult_125_G4_B_not_7_port, outb =>
mult_125_G4_ab_7_7_port);
mult_125_G4_AN1_7_6 : nor2 port map( a => mult_125_G4_A_not_7_port, b =>
mult_125_G4_B_not_6_port, outb =>
mult_125_G4_ab_7_6_port);
mult_125_G4_AN1_7_5 : nor2 port map( a => mult_125_G4_A_not_7_port, b =>
mult_125_G4_B_not_5_port, outb =>
mult_125_G4_ab_7_5_port);
mult_125_G4_AN1_7_4 : nor2 port map( a => mult_125_G4_A_not_7_port, b =>
mult_125_G4_B_not_4_port, outb =>
mult_125_G4_ab_7_4_port);
mult_125_G4_AN1_7_3 : nor2 port map( a => mult_125_G4_A_not_7_port, b =>
mult_125_G4_B_not_3_port, outb =>
mult_125_G4_ab_7_3_port);
mult_125_G4_AN1_7_2 : nor2 port map( a => mult_125_G4_A_not_7_port, b =>
mult_125_G4_B_not_2_port, outb =>
mult_125_G4_ab_7_2_port);
mult_125_G4_AN1_7_1 : nor2 port map( a => mult_125_G4_A_not_7_port, b =>
mult_125_G4_B_not_1_port, outb =>
mult_125_G4_ab_7_1_port);
mult_125_G4_AN1_7_0_0 : nor2 port map( a => mult_125_G4_A_not_7_port, b =>
mult_125_G4_B_not_0_port, outb =>
mult_125_G4_ab_7_0_port);
mult_125_G4_AN2_6_15 : nor2 port map( a => mult_125_G4_A_notx_6_port, b =>
mult_125_G4_B_not_15_port, outb =>
mult_125_G4_ab_6_15_port);
mult_125_G4_AN1_6_14 : nor2 port map( a => mult_125_G4_A_not_6_port, b =>
mult_125_G4_B_not_14_port, outb =>
mult_125_G4_ab_6_14_port);
mult_125_G4_AN1_6_13 : nor2 port map( a => mult_125_G4_A_not_6_port, b =>
mult_125_G4_B_not_13_port, outb =>
mult_125_G4_ab_6_13_port);
mult_125_G4_AN1_6_12 : nor2 port map( a => mult_125_G4_A_not_6_port, b =>
mult_125_G4_B_not_12_port, outb =>
mult_125_G4_ab_6_12_port);
mult_125_G4_AN1_6_11 : nor2 port map( a => mult_125_G4_A_not_6_port, b =>
mult_125_G4_B_not_11_port, outb =>
mult_125_G4_ab_6_11_port);
mult_125_G4_AN1_6_10 : nor2 port map( a => mult_125_G4_A_not_6_port, b =>
mult_125_G4_B_not_10_port, outb =>
mult_125_G4_ab_6_10_port);
mult_125_G4_AN1_6_9 : nor2 port map( a => mult_125_G4_A_not_6_port, b =>
mult_125_G4_B_not_9_port, outb =>
mult_125_G4_ab_6_9_port);
mult_125_G4_AN1_6_8 : nor2 port map( a => mult_125_G4_A_not_6_port, b =>
mult_125_G4_B_not_8_port, outb =>
mult_125_G4_ab_6_8_port);
mult_125_G4_AN1_6_7 : nor2 port map( a => mult_125_G4_A_not_6_port, b =>
mult_125_G4_B_not_7_port, outb =>
mult_125_G4_ab_6_7_port);
mult_125_G4_AN1_6_6 : nor2 port map( a => mult_125_G4_A_not_6_port, b =>
mult_125_G4_B_not_6_port, outb =>
mult_125_G4_ab_6_6_port);
mult_125_G4_AN1_6_5 : nor2 port map( a => mult_125_G4_A_not_6_port, b =>
mult_125_G4_B_not_5_port, outb =>
mult_125_G4_ab_6_5_port);
mult_125_G4_AN1_6_4 : nor2 port map( a => mult_125_G4_A_not_6_port, b =>
mult_125_G4_B_not_4_port, outb =>
mult_125_G4_ab_6_4_port);
mult_125_G4_AN1_6_3 : nor2 port map( a => mult_125_G4_A_not_6_port, b =>
mult_125_G4_B_not_3_port, outb =>
mult_125_G4_ab_6_3_port);
mult_125_G4_AN1_6_2 : nor2 port map( a => mult_125_G4_A_not_6_port, b =>
mult_125_G4_B_not_2_port, outb =>
mult_125_G4_ab_6_2_port);
mult_125_G4_AN1_6_1 : nor2 port map( a => mult_125_G4_A_not_6_port, b =>
mult_125_G4_B_not_1_port, outb =>
mult_125_G4_ab_6_1_port);
mult_125_G4_AN1_6_0_0 : nor2 port map( a => mult_125_G4_A_not_6_port, b =>
mult_125_G4_B_not_0_port, outb =>
mult_125_G4_ab_6_0_port);
mult_125_G4_AN2_5_15 : nor2 port map( a => mult_125_G4_A_notx_5_port, b =>
mult_125_G4_B_not_15_port, outb =>
mult_125_G4_ab_5_15_port);
mult_125_G4_AN1_5_14 : nor2 port map( a => mult_125_G4_A_not_5_port, b =>
mult_125_G4_B_not_14_port, outb =>
mult_125_G4_ab_5_14_port);
mult_125_G4_AN1_5_13 : nor2 port map( a => mult_125_G4_A_not_5_port, b =>
mult_125_G4_B_not_13_port, outb =>
mult_125_G4_ab_5_13_port);
mult_125_G4_AN1_5_12 : nor2 port map( a => mult_125_G4_A_not_5_port, b =>
mult_125_G4_B_not_12_port, outb =>
mult_125_G4_ab_5_12_port);
mult_125_G4_AN1_5_11 : nor2 port map( a => mult_125_G4_A_not_5_port, b =>
mult_125_G4_B_not_11_port, outb =>
mult_125_G4_ab_5_11_port);
mult_125_G4_AN1_5_10 : nor2 port map( a => mult_125_G4_A_not_5_port, b =>
mult_125_G4_B_not_10_port, outb =>
mult_125_G4_ab_5_10_port);
mult_125_G4_AN1_5_9 : nor2 port map( a => mult_125_G4_A_not_5_port, b =>
mult_125_G4_B_not_9_port, outb =>
mult_125_G4_ab_5_9_port);
mult_125_G4_AN1_5_8 : nor2 port map( a => mult_125_G4_A_not_5_port, b =>
mult_125_G4_B_not_8_port, outb =>
mult_125_G4_ab_5_8_port);
mult_125_G4_AN1_5_7 : nor2 port map( a => mult_125_G4_A_not_5_port, b =>
mult_125_G4_B_not_7_port, outb =>
mult_125_G4_ab_5_7_port);
mult_125_G4_AN1_5_6 : nor2 port map( a => mult_125_G4_A_not_5_port, b =>
mult_125_G4_B_not_6_port, outb =>
mult_125_G4_ab_5_6_port);
mult_125_G4_AN1_5_5 : nor2 port map( a => mult_125_G4_A_not_5_port, b =>
mult_125_G4_B_not_5_port, outb =>
mult_125_G4_ab_5_5_port);
mult_125_G4_AN1_5_4 : nor2 port map( a => mult_125_G4_A_not_5_port, b =>
mult_125_G4_B_not_4_port, outb =>
mult_125_G4_ab_5_4_port);
mult_125_G4_AN1_5_3 : nor2 port map( a => mult_125_G4_A_not_5_port, b =>
mult_125_G4_B_not_3_port, outb =>
mult_125_G4_ab_5_3_port);
mult_125_G4_AN1_5_2 : nor2 port map( a => mult_125_G4_A_not_5_port, b =>
mult_125_G4_B_not_2_port, outb =>
mult_125_G4_ab_5_2_port);
mult_125_G4_AN1_5_1 : nor2 port map( a => mult_125_G4_A_not_5_port, b =>
mult_125_G4_B_not_1_port, outb =>
mult_125_G4_ab_5_1_port);
mult_125_G4_AN1_5_0_0 : nor2 port map( a => mult_125_G4_A_not_5_port, b =>
mult_125_G4_B_not_0_port, outb =>
mult_125_G4_ab_5_0_port);
mult_125_G4_AN2_4_15 : nor2 port map( a => mult_125_G4_A_notx_4_port, b =>
mult_125_G4_B_not_15_port, outb =>
mult_125_G4_ab_4_15_port);
mult_125_G4_AN1_4_14 : nor2 port map( a => mult_125_G4_A_not_4_port, b =>
mult_125_G4_B_not_14_port, outb =>
mult_125_G4_ab_4_14_port);
mult_125_G4_AN1_4_13 : nor2 port map( a => mult_125_G4_A_not_4_port, b =>
mult_125_G4_B_not_13_port, outb =>
mult_125_G4_ab_4_13_port);
mult_125_G4_AN1_4_12 : nor2 port map( a => mult_125_G4_A_not_4_port, b =>
mult_125_G4_B_not_12_port, outb =>
mult_125_G4_ab_4_12_port);
mult_125_G4_AN1_4_11 : nor2 port map( a => mult_125_G4_A_not_4_port, b =>
mult_125_G4_B_not_11_port, outb =>
mult_125_G4_ab_4_11_port);
mult_125_G4_AN1_4_10 : nor2 port map( a => mult_125_G4_A_not_4_port, b =>
mult_125_G4_B_not_10_port, outb =>
mult_125_G4_ab_4_10_port);
mult_125_G4_AN1_4_9 : nor2 port map( a => mult_125_G4_A_not_4_port, b =>
mult_125_G4_B_not_9_port, outb =>
mult_125_G4_ab_4_9_port);
mult_125_G4_AN1_4_8 : nor2 port map( a => mult_125_G4_A_not_4_port, b =>
mult_125_G4_B_not_8_port, outb =>
mult_125_G4_ab_4_8_port);
mult_125_G4_AN1_4_7 : nor2 port map( a => mult_125_G4_A_not_4_port, b =>
mult_125_G4_B_not_7_port, outb =>
mult_125_G4_ab_4_7_port);
mult_125_G4_AN1_4_6 : nor2 port map( a => mult_125_G4_A_not_4_port, b =>
mult_125_G4_B_not_6_port, outb =>
mult_125_G4_ab_4_6_port);
mult_125_G4_AN1_4_5 : nor2 port map( a => mult_125_G4_A_not_4_port, b =>
mult_125_G4_B_not_5_port, outb =>
mult_125_G4_ab_4_5_port);
mult_125_G4_AN1_4_4 : nor2 port map( a => mult_125_G4_A_not_4_port, b =>
mult_125_G4_B_not_4_port, outb =>
mult_125_G4_ab_4_4_port);
mult_125_G4_AN1_4_3 : nor2 port map( a => mult_125_G4_A_not_4_port, b =>
mult_125_G4_B_not_3_port, outb =>
mult_125_G4_ab_4_3_port);
mult_125_G4_AN1_4_2 : nor2 port map( a => mult_125_G4_A_not_4_port, b =>
mult_125_G4_B_not_2_port, outb =>
mult_125_G4_ab_4_2_port);
mult_125_G4_AN1_4_1 : nor2 port map( a => mult_125_G4_A_not_4_port, b =>
mult_125_G4_B_not_1_port, outb =>
mult_125_G4_ab_4_1_port);
mult_125_G4_AN1_4_0_0 : nor2 port map( a => mult_125_G4_A_not_4_port, b =>
mult_125_G4_B_not_0_port, outb =>
mult_125_G4_ab_4_0_port);
mult_125_G4_AN2_3_15 : nor2 port map( a => mult_125_G4_A_notx_3_port, b =>
mult_125_G4_B_not_15_port, outb =>
mult_125_G4_ab_3_15_port);
mult_125_G4_AN1_3_14 : nor2 port map( a => mult_125_G4_A_not_3_port, b =>
mult_125_G4_B_not_14_port, outb =>
mult_125_G4_ab_3_14_port);
mult_125_G4_AN1_3_13 : nor2 port map( a => mult_125_G4_A_not_3_port, b =>
mult_125_G4_B_not_13_port, outb =>
mult_125_G4_ab_3_13_port);
mult_125_G4_AN1_3_12 : nor2 port map( a => mult_125_G4_A_not_3_port, b =>
mult_125_G4_B_not_12_port, outb =>
mult_125_G4_ab_3_12_port);
mult_125_G4_AN1_3_11 : nor2 port map( a => mult_125_G4_A_not_3_port, b =>
mult_125_G4_B_not_11_port, outb =>
mult_125_G4_ab_3_11_port);
mult_125_G4_AN1_3_10 : nor2 port map( a => mult_125_G4_A_not_3_port, b =>
mult_125_G4_B_not_10_port, outb =>
mult_125_G4_ab_3_10_port);
mult_125_G4_AN1_3_9 : nor2 port map( a => mult_125_G4_A_not_3_port, b =>
mult_125_G4_B_not_9_port, outb =>
mult_125_G4_ab_3_9_port);
mult_125_G4_AN1_3_8 : nor2 port map( a => mult_125_G4_A_not_3_port, b =>
mult_125_G4_B_not_8_port, outb =>
mult_125_G4_ab_3_8_port);
mult_125_G4_AN1_3_7 : nor2 port map( a => mult_125_G4_A_not_3_port, b =>
mult_125_G4_B_not_7_port, outb =>
mult_125_G4_ab_3_7_port);
mult_125_G4_AN1_3_6 : nor2 port map( a => mult_125_G4_A_not_3_port, b =>
mult_125_G4_B_not_6_port, outb =>
mult_125_G4_ab_3_6_port);
mult_125_G4_AN1_3_5 : nor2 port map( a => mult_125_G4_A_not_3_port, b =>
mult_125_G4_B_not_5_port, outb =>
mult_125_G4_ab_3_5_port);
mult_125_G4_AN1_3_4 : nor2 port map( a => mult_125_G4_A_not_3_port, b =>
mult_125_G4_B_not_4_port, outb =>
mult_125_G4_ab_3_4_port);
mult_125_G4_AN1_3_3 : nor2 port map( a => mult_125_G4_A_not_3_port, b =>
mult_125_G4_B_not_3_port, outb =>
mult_125_G4_ab_3_3_port);
mult_125_G4_AN1_3_2 : nor2 port map( a => mult_125_G4_A_not_3_port, b =>
mult_125_G4_B_not_2_port, outb =>
mult_125_G4_ab_3_2_port);
mult_125_G4_AN1_3_1 : nor2 port map( a => mult_125_G4_A_not_3_port, b =>
mult_125_G4_B_not_1_port, outb =>
mult_125_G4_ab_3_1_port);
mult_125_G4_AN1_3_0_0 : nor2 port map( a => mult_125_G4_A_not_3_port, b =>
mult_125_G4_B_not_0_port, outb =>
mult_125_G4_ab_3_0_port);
mult_125_G4_AN2_2_15 : nor2 port map( a => mult_125_G4_A_notx_2_port, b =>
mult_125_G4_B_not_15_port, outb =>
mult_125_G4_ab_2_15_port);
mult_125_G4_AN1_2_14 : nor2 port map( a => mult_125_G4_A_not_2_port, b =>
mult_125_G4_B_not_14_port, outb =>
mult_125_G4_ab_2_14_port);
mult_125_G4_AN1_2_13 : nor2 port map( a => mult_125_G4_A_not_2_port, b =>
mult_125_G4_B_not_13_port, outb =>
mult_125_G4_ab_2_13_port);
mult_125_G4_AN1_2_12 : nor2 port map( a => mult_125_G4_A_not_2_port, b =>
mult_125_G4_B_not_12_port, outb =>
mult_125_G4_ab_2_12_port);
mult_125_G4_AN1_2_11 : nor2 port map( a => mult_125_G4_A_not_2_port, b =>
mult_125_G4_B_not_11_port, outb =>
mult_125_G4_ab_2_11_port);
mult_125_G4_AN1_2_10 : nor2 port map( a => mult_125_G4_A_not_2_port, b =>
mult_125_G4_B_not_10_port, outb =>
mult_125_G4_ab_2_10_port);
mult_125_G4_AN1_2_9 : nor2 port map( a => mult_125_G4_A_not_2_port, b =>
mult_125_G4_B_not_9_port, outb =>
mult_125_G4_ab_2_9_port);
mult_125_G4_AN1_2_8 : nor2 port map( a => mult_125_G4_A_not_2_port, b =>
mult_125_G4_B_not_8_port, outb =>
mult_125_G4_ab_2_8_port);
mult_125_G4_AN1_2_7 : nor2 port map( a => mult_125_G4_A_not_2_port, b =>
mult_125_G4_B_not_7_port, outb =>
mult_125_G4_ab_2_7_port);
mult_125_G4_AN1_2_6 : nor2 port map( a => mult_125_G4_A_not_2_port, b =>
mult_125_G4_B_not_6_port, outb =>
mult_125_G4_ab_2_6_port);
mult_125_G4_AN1_2_5 : nor2 port map( a => mult_125_G4_A_not_2_port, b =>
mult_125_G4_B_not_5_port, outb =>
mult_125_G4_ab_2_5_port);
mult_125_G4_AN1_2_4 : nor2 port map( a => mult_125_G4_A_not_2_port, b =>
mult_125_G4_B_not_4_port, outb =>
mult_125_G4_ab_2_4_port);
mult_125_G4_AN1_2_3 : nor2 port map( a => mult_125_G4_A_not_2_port, b =>
mult_125_G4_B_not_3_port, outb =>
mult_125_G4_ab_2_3_port);
mult_125_G4_AN1_2_2 : nor2 port map( a => mult_125_G4_A_not_2_port, b =>
mult_125_G4_B_not_2_port, outb =>
mult_125_G4_ab_2_2_port);
mult_125_G4_AN1_2_1 : nor2 port map( a => mult_125_G4_A_not_2_port, b =>
mult_125_G4_B_not_1_port, outb =>
mult_125_G4_ab_2_1_port);
mult_125_G4_AN1_2_0_0 : nor2 port map( a => mult_125_G4_A_not_2_port, b =>
mult_125_G4_B_not_0_port, outb =>
mult_125_G4_ab_2_0_port);
mult_125_G4_AN2_1_15 : nor2 port map( a => mult_125_G4_A_notx_1_port, b =>
mult_125_G4_B_not_15_port, outb =>
mult_125_G4_ab_1_15_port);
mult_125_G4_AN1_1_14 : nor2 port map( a => mult_125_G4_A_not_1_port, b =>
mult_125_G4_B_not_14_port, outb =>
mult_125_G4_ab_1_14_port);
mult_125_G4_AN1_1_13 : nor2 port map( a => mult_125_G4_A_not_1_port, b =>
mult_125_G4_B_not_13_port, outb =>
mult_125_G4_ab_1_13_port);
mult_125_G4_AN1_1_12 : nor2 port map( a => mult_125_G4_A_not_1_port, b =>
mult_125_G4_B_not_12_port, outb =>
mult_125_G4_ab_1_12_port);
mult_125_G4_AN1_1_11 : nor2 port map( a => mult_125_G4_A_not_1_port, b =>
mult_125_G4_B_not_11_port, outb =>
mult_125_G4_ab_1_11_port);
mult_125_G4_AN1_1_10 : nor2 port map( a => mult_125_G4_A_not_1_port, b =>
mult_125_G4_B_not_10_port, outb =>
mult_125_G4_ab_1_10_port);
mult_125_G4_AN1_1_9 : nor2 port map( a => mult_125_G4_A_not_1_port, b =>
mult_125_G4_B_not_9_port, outb =>
mult_125_G4_ab_1_9_port);
mult_125_G4_AN1_1_8 : nor2 port map( a => mult_125_G4_A_not_1_port, b =>
mult_125_G4_B_not_8_port, outb =>
mult_125_G4_ab_1_8_port);
mult_125_G4_AN1_1_7 : nor2 port map( a => mult_125_G4_A_not_1_port, b =>
mult_125_G4_B_not_7_port, outb =>
mult_125_G4_ab_1_7_port);
mult_125_G4_AN1_1_6 : nor2 port map( a => mult_125_G4_A_not_1_port, b =>
mult_125_G4_B_not_6_port, outb =>
mult_125_G4_ab_1_6_port);
mult_125_G4_AN1_1_5 : nor2 port map( a => mult_125_G4_A_not_1_port, b =>
mult_125_G4_B_not_5_port, outb =>
mult_125_G4_ab_1_5_port);
mult_125_G4_AN1_1_4 : nor2 port map( a => mult_125_G4_A_not_1_port, b =>
mult_125_G4_B_not_4_port, outb =>
mult_125_G4_ab_1_4_port);
mult_125_G4_AN1_1_3 : nor2 port map( a => mult_125_G4_A_not_1_port, b =>
mult_125_G4_B_not_3_port, outb =>
mult_125_G4_ab_1_3_port);
mult_125_G4_AN1_1_2 : nor2 port map( a => mult_125_G4_A_not_1_port, b =>
mult_125_G4_B_not_2_port, outb =>
mult_125_G4_ab_1_2_port);
mult_125_G4_AN1_1_1 : nor2 port map( a => mult_125_G4_A_not_1_port, b =>
mult_125_G4_B_not_1_port, outb =>
mult_125_G4_ab_1_1_port);
mult_125_G4_AN1_1_0_0 : nor2 port map( a => mult_125_G4_A_not_1_port, b =>
mult_125_G4_B_not_0_port, outb =>
mult_125_G4_ab_1_0_port);
mult_125_G4_AN2_0_15 : nor2 port map( a => mult_125_G4_A_notx_0_port, b =>
mult_125_G4_B_not_15_port, outb =>
mult_125_G4_ab_0_15_port);
mult_125_G4_AN1_0_14 : nor2 port map( a => mult_125_G4_A_not_0_port, b =>
mult_125_G4_B_not_14_port, outb =>
mult_125_G4_ab_0_14_port);
mult_125_G4_AN1_0_13 : nor2 port map( a => mult_125_G4_A_not_0_port, b =>
mult_125_G4_B_not_13_port, outb =>
mult_125_G4_ab_0_13_port);
mult_125_G4_AN1_0_12 : nor2 port map( a => mult_125_G4_A_not_0_port, b =>
mult_125_G4_B_not_12_port, outb =>
mult_125_G4_ab_0_12_port);
mult_125_G4_AN1_0_11 : nor2 port map( a => mult_125_G4_A_not_0_port, b =>
mult_125_G4_B_not_11_port, outb =>
mult_125_G4_ab_0_11_port);
mult_125_G4_AN1_0_10 : nor2 port map( a => mult_125_G4_A_not_0_port, b =>
mult_125_G4_B_not_10_port, outb =>
mult_125_G4_ab_0_10_port);
mult_125_G4_AN1_0_9 : nor2 port map( a => mult_125_G4_A_not_0_port, b =>
mult_125_G4_B_not_9_port, outb =>
mult_125_G4_ab_0_9_port);
mult_125_G4_AN1_0_8 : nor2 port map( a => mult_125_G4_A_not_0_port, b =>
mult_125_G4_B_not_8_port, outb =>
mult_125_G4_ab_0_8_port);
mult_125_G4_AN1_0_7 : nor2 port map( a => mult_125_G4_A_not_0_port, b =>
mult_125_G4_B_not_7_port, outb =>
mult_125_G4_ab_0_7_port);
mult_125_G4_AN1_0_6 : nor2 port map( a => mult_125_G4_A_not_0_port, b =>
mult_125_G4_B_not_6_port, outb =>
mult_125_G4_ab_0_6_port);
mult_125_G4_AN1_0_5 : nor2 port map( a => mult_125_G4_A_not_0_port, b =>
mult_125_G4_B_not_5_port, outb =>
mult_125_G4_ab_0_5_port);
mult_125_G4_AN1_0_4 : nor2 port map( a => mult_125_G4_A_not_0_port, b =>
mult_125_G4_B_not_4_port, outb =>
mult_125_G4_ab_0_4_port);
mult_125_G4_AN1_0_3 : nor2 port map( a => mult_125_G4_A_not_0_port, b =>
mult_125_G4_B_not_3_port, outb =>
mult_125_G4_ab_0_3_port);
mult_125_G4_AN1_0_2 : nor2 port map( a => mult_125_G4_A_not_0_port, b =>
mult_125_G4_B_not_2_port, outb =>
mult_125_G4_ab_0_2_port);
mult_125_G4_AN1_0_1 : nor2 port map( a => mult_125_G4_A_not_0_port, b =>
mult_125_G4_B_not_1_port, outb =>
mult_125_G4_ab_0_1_port);
mult_125_G4_AN1_0_0_0 : nor2 port map( a => mult_125_G4_A_not_0_port, b =>
mult_125_G4_B_not_0_port, outb =>
multiplier_sigs_3_0_port);
U267 : inv port map( inb => input_sample_mem_15_port, outb => n5911);
U268 : inv port map( inb => coefficient_mem_array_2_15_port, outb => n5912);
U269 : inv port map( inb => mult_125_G3_B_not_15_port, outb => n5913);
U270 : inv port map( inb => mult_125_G3_A_not_15_port, outb => n5914);
U271 : inv port map( inb => mult_125_G3_A_not_0_port, outb =>
mult_125_G3_A_notx_0_port);
U272 : inv port map( inb => mult_125_G3_A_not_1_port, outb =>
mult_125_G3_A_notx_1_port);
U273 : inv port map( inb => mult_125_G3_A_not_2_port, outb =>
mult_125_G3_A_notx_2_port);
U274 : inv port map( inb => mult_125_G3_A_not_3_port, outb =>
mult_125_G3_A_notx_3_port);
U275 : inv port map( inb => mult_125_G3_A_not_4_port, outb =>
mult_125_G3_A_notx_4_port);
U276 : inv port map( inb => mult_125_G3_A_not_5_port, outb =>
mult_125_G3_A_notx_5_port);
U277 : inv port map( inb => mult_125_G3_A_not_6_port, outb =>
mult_125_G3_A_notx_6_port);
U278 : inv port map( inb => mult_125_G3_A_not_7_port, outb =>
mult_125_G3_A_notx_7_port);
U279 : inv port map( inb => mult_125_G3_A_not_8_port, outb =>
mult_125_G3_A_notx_8_port);
U280 : inv port map( inb => mult_125_G3_A_not_9_port, outb =>
mult_125_G3_A_notx_9_port);
U281 : inv port map( inb => mult_125_G3_A_not_10_port, outb =>
mult_125_G3_A_notx_10_port);
U282 : inv port map( inb => mult_125_G3_A_not_11_port, outb =>
mult_125_G3_A_notx_11_port);
U283 : inv port map( inb => mult_125_G3_A_not_12_port, outb =>
mult_125_G3_A_notx_12_port);
U284 : inv port map( inb => mult_125_G3_A_not_13_port, outb =>
mult_125_G3_A_notx_13_port);
U285 : inv port map( inb => mult_125_G3_A_not_14_port, outb =>
mult_125_G3_A_notx_14_port);
U286 : inv port map( inb => mult_125_G3_B_not_0_port, outb =>
mult_125_G3_B_notx_0_port);
U287 : inv port map( inb => mult_125_G3_B_not_1_port, outb =>
mult_125_G3_B_notx_1_port);
U288 : inv port map( inb => mult_125_G3_B_not_2_port, outb =>
mult_125_G3_B_notx_2_port);
U289 : inv port map( inb => mult_125_G3_B_not_3_port, outb =>
mult_125_G3_B_notx_3_port);
U290 : inv port map( inb => mult_125_G3_B_not_4_port, outb =>
mult_125_G3_B_notx_4_port);
U291 : inv port map( inb => mult_125_G3_B_not_5_port, outb =>
mult_125_G3_B_notx_5_port);
U292 : inv port map( inb => mult_125_G3_B_not_6_port, outb =>
mult_125_G3_B_notx_6_port);
U293 : inv port map( inb => mult_125_G3_B_not_7_port, outb =>
mult_125_G3_B_notx_7_port);
U294 : inv port map( inb => mult_125_G3_B_not_8_port, outb =>
mult_125_G3_B_notx_8_port);
U295 : inv port map( inb => mult_125_G3_B_not_9_port, outb =>
mult_125_G3_B_notx_9_port);
U296 : inv port map( inb => mult_125_G3_B_not_10_port, outb =>
mult_125_G3_B_notx_10_port);
U297 : inv port map( inb => mult_125_G3_B_not_11_port, outb =>
mult_125_G3_B_notx_11_port);
U298 : inv port map( inb => mult_125_G3_B_not_12_port, outb =>
mult_125_G3_B_notx_12_port);
U299 : inv port map( inb => mult_125_G3_B_not_13_port, outb =>
mult_125_G3_B_notx_13_port);
U300 : inv port map( inb => mult_125_G3_B_not_14_port, outb =>
mult_125_G3_B_notx_14_port);
U301 : inv port map( inb => input_sample_mem_15_port, outb => n5786);
U302 : inv port map( inb => coefficient_mem_array_1_15_port, outb => n5787);
U303 : inv port map( inb => mult_125_G2_B_not_15_port, outb => n5788);
U304 : inv port map( inb => mult_125_G2_A_not_15_port, outb => n5789);
U305 : inv port map( inb => mult_125_G2_A_not_0_port, outb =>
mult_125_G2_A_notx_0_port);
U306 : inv port map( inb => mult_125_G2_A_not_1_port, outb =>
mult_125_G2_A_notx_1_port);
U307 : inv port map( inb => mult_125_G2_A_not_2_port, outb =>
mult_125_G2_A_notx_2_port);
U308 : inv port map( inb => mult_125_G2_A_not_3_port, outb =>
mult_125_G2_A_notx_3_port);
U309 : inv port map( inb => mult_125_G2_A_not_4_port, outb =>
mult_125_G2_A_notx_4_port);
U310 : inv port map( inb => mult_125_G2_A_not_5_port, outb =>
mult_125_G2_A_notx_5_port);
U311 : inv port map( inb => mult_125_G2_A_not_6_port, outb =>
mult_125_G2_A_notx_6_port);
U312 : inv port map( inb => mult_125_G2_A_not_7_port, outb =>
mult_125_G2_A_notx_7_port);
U313 : inv port map( inb => mult_125_G2_A_not_8_port, outb =>
mult_125_G2_A_notx_8_port);
U314 : inv port map( inb => mult_125_G2_A_not_9_port, outb =>
mult_125_G2_A_notx_9_port);
U315 : inv port map( inb => mult_125_G2_A_not_10_port, outb =>
mult_125_G2_A_notx_10_port);
U316 : inv port map( inb => mult_125_G2_A_not_11_port, outb =>
mult_125_G2_A_notx_11_port);
U317 : inv port map( inb => mult_125_G2_A_not_12_port, outb =>
mult_125_G2_A_notx_12_port);
U318 : inv port map( inb => mult_125_G2_A_not_13_port, outb =>
mult_125_G2_A_notx_13_port);
U319 : inv port map( inb => mult_125_G2_A_not_14_port, outb =>
mult_125_G2_A_notx_14_port);
U320 : inv port map( inb => mult_125_G2_B_not_0_port, outb =>
mult_125_G2_B_notx_0_port);
U321 : inv port map( inb => mult_125_G2_B_not_1_port, outb =>
mult_125_G2_B_notx_1_port);
U322 : inv port map( inb => mult_125_G2_B_not_2_port, outb =>
mult_125_G2_B_notx_2_port);
U323 : inv port map( inb => mult_125_G2_B_not_3_port, outb =>
mult_125_G2_B_notx_3_port);
U324 : inv port map( inb => mult_125_G2_B_not_4_port, outb =>
mult_125_G2_B_notx_4_port);
U325 : inv port map( inb => mult_125_G2_B_not_5_port, outb =>
mult_125_G2_B_notx_5_port);
U326 : inv port map( inb => mult_125_G2_B_not_6_port, outb =>
mult_125_G2_B_notx_6_port);
U327 : inv port map( inb => mult_125_G2_B_not_7_port, outb =>
mult_125_G2_B_notx_7_port);
U328 : inv port map( inb => mult_125_G2_B_not_8_port, outb =>
mult_125_G2_B_notx_8_port);
U329 : inv port map( inb => mult_125_G2_B_not_9_port, outb =>
mult_125_G2_B_notx_9_port);
U330 : inv port map( inb => mult_125_G2_B_not_10_port, outb =>
mult_125_G2_B_notx_10_port);
U331 : inv port map( inb => mult_125_G2_B_not_11_port, outb =>
mult_125_G2_B_notx_11_port);
U332 : inv port map( inb => mult_125_G2_B_not_12_port, outb =>
mult_125_G2_B_notx_12_port);
U333 : inv port map( inb => mult_125_G2_B_not_13_port, outb =>
mult_125_G2_B_notx_13_port);
U334 : inv port map( inb => mult_125_G2_B_not_14_port, outb =>
mult_125_G2_B_notx_14_port);
U335 : inv port map( inb => input_sample_mem_15_port, outb => n5661);
U336 : inv port map( inb => coefficient_mem_array_0_15_port, outb => n5662);
U337 : inv port map( inb => mult_125_B_not_15_port, outb => n5663);
U338 : inv port map( inb => mult_125_A_not_15_port, outb => n5664);
U339 : inv port map( inb => mult_125_A_not_0_port, outb =>
mult_125_A_notx_0_port);
U340 : inv port map( inb => mult_125_A_not_1_port, outb =>
mult_125_A_notx_1_port);
U341 : inv port map( inb => mult_125_A_not_2_port, outb =>
mult_125_A_notx_2_port);
U342 : inv port map( inb => mult_125_A_not_3_port, outb =>
mult_125_A_notx_3_port);
U343 : inv port map( inb => mult_125_A_not_4_port, outb =>
mult_125_A_notx_4_port);
U344 : inv port map( inb => mult_125_A_not_5_port, outb =>
mult_125_A_notx_5_port);
U345 : inv port map( inb => mult_125_A_not_6_port, outb =>
mult_125_A_notx_6_port);
U346 : inv port map( inb => mult_125_A_not_7_port, outb =>
mult_125_A_notx_7_port);
U347 : inv port map( inb => mult_125_A_not_8_port, outb =>
mult_125_A_notx_8_port);
U348 : inv port map( inb => mult_125_A_not_9_port, outb =>
mult_125_A_notx_9_port);
U349 : inv port map( inb => mult_125_A_not_10_port, outb =>
mult_125_A_notx_10_port);
U350 : inv port map( inb => mult_125_A_not_11_port, outb =>
mult_125_A_notx_11_port);
U351 : inv port map( inb => mult_125_A_not_12_port, outb =>
mult_125_A_notx_12_port);
U352 : inv port map( inb => mult_125_A_not_13_port, outb =>
mult_125_A_notx_13_port);
U353 : inv port map( inb => mult_125_A_not_14_port, outb =>
mult_125_A_notx_14_port);
U354 : inv port map( inb => mult_125_B_not_0_port, outb =>
mult_125_B_notx_0_port);
U355 : inv port map( inb => mult_125_B_not_1_port, outb =>
mult_125_B_notx_1_port);
U356 : inv port map( inb => mult_125_B_not_2_port, outb =>
mult_125_B_notx_2_port);
U357 : inv port map( inb => mult_125_B_not_3_port, outb =>
mult_125_B_notx_3_port);
U358 : inv port map( inb => mult_125_B_not_4_port, outb =>
mult_125_B_notx_4_port);
U359 : inv port map( inb => mult_125_B_not_5_port, outb =>
mult_125_B_notx_5_port);
U360 : inv port map( inb => mult_125_B_not_6_port, outb =>
mult_125_B_notx_6_port);
U361 : inv port map( inb => mult_125_B_not_7_port, outb =>
mult_125_B_notx_7_port);
U362 : inv port map( inb => mult_125_B_not_8_port, outb =>
mult_125_B_notx_8_port);
U363 : inv port map( inb => mult_125_B_not_9_port, outb =>
mult_125_B_notx_9_port);
U364 : inv port map( inb => mult_125_B_not_10_port, outb =>
mult_125_B_notx_10_port);
U365 : inv port map( inb => mult_125_B_not_11_port, outb =>
mult_125_B_notx_11_port);
U366 : inv port map( inb => mult_125_B_not_12_port, outb =>
mult_125_B_notx_12_port);
U367 : inv port map( inb => mult_125_B_not_13_port, outb =>
mult_125_B_notx_13_port);
U368 : inv port map( inb => mult_125_B_not_14_port, outb =>
mult_125_B_notx_14_port);
U369 : inv port map( inb => input_sample_mem_15_port, outb => n5536);
U370 : inv port map( inb => coefficient_mem_array_3_15_port, outb => n5537);
U371 : inv port map( inb => mult_125_G4_B_not_15_port, outb => n5538);
U372 : inv port map( inb => mult_125_G4_A_not_15_port, outb => n5539);
U373 : inv port map( inb => mult_125_G4_A_not_0_port, outb =>
mult_125_G4_A_notx_0_port);
U374 : inv port map( inb => mult_125_G4_A_not_1_port, outb =>
mult_125_G4_A_notx_1_port);
U375 : inv port map( inb => mult_125_G4_A_not_2_port, outb =>
mult_125_G4_A_notx_2_port);
U376 : inv port map( inb => mult_125_G4_A_not_3_port, outb =>
mult_125_G4_A_notx_3_port);
U377 : inv port map( inb => mult_125_G4_A_not_4_port, outb =>
mult_125_G4_A_notx_4_port);
U378 : inv port map( inb => mult_125_G4_A_not_5_port, outb =>
mult_125_G4_A_notx_5_port);
U379 : inv port map( inb => mult_125_G4_A_not_6_port, outb =>
mult_125_G4_A_notx_6_port);
U380 : inv port map( inb => mult_125_G4_A_not_7_port, outb =>
mult_125_G4_A_notx_7_port);
U381 : inv port map( inb => mult_125_G4_A_not_8_port, outb =>
mult_125_G4_A_notx_8_port);
U382 : inv port map( inb => mult_125_G4_A_not_9_port, outb =>
mult_125_G4_A_notx_9_port);
U383 : inv port map( inb => mult_125_G4_A_not_10_port, outb =>
mult_125_G4_A_notx_10_port);
U384 : inv port map( inb => mult_125_G4_A_not_11_port, outb =>
mult_125_G4_A_notx_11_port);
U385 : inv port map( inb => mult_125_G4_A_not_12_port, outb =>
mult_125_G4_A_notx_12_port);
U386 : inv port map( inb => mult_125_G4_A_not_13_port, outb =>
mult_125_G4_A_notx_13_port);
U387 : inv port map( inb => mult_125_G4_A_not_14_port, outb =>
mult_125_G4_A_notx_14_port);
U388 : inv port map( inb => mult_125_G4_B_not_0_port, outb =>
mult_125_G4_B_notx_0_port);
U389 : inv port map( inb => mult_125_G4_B_not_1_port, outb =>
mult_125_G4_B_notx_1_port);
U390 : inv port map( inb => mult_125_G4_B_not_2_port, outb =>
mult_125_G4_B_notx_2_port);
U391 : inv port map( inb => mult_125_G4_B_not_3_port, outb =>
mult_125_G4_B_notx_3_port);
U392 : inv port map( inb => mult_125_G4_B_not_4_port, outb =>
mult_125_G4_B_notx_4_port);
U393 : inv port map( inb => mult_125_G4_B_not_5_port, outb =>
mult_125_G4_B_notx_5_port);
U394 : inv port map( inb => mult_125_G4_B_not_6_port, outb =>
mult_125_G4_B_notx_6_port);
U395 : inv port map( inb => mult_125_G4_B_not_7_port, outb =>
mult_125_G4_B_notx_7_port);
U396 : inv port map( inb => mult_125_G4_B_not_8_port, outb =>
mult_125_G4_B_notx_8_port);
U397 : inv port map( inb => mult_125_G4_B_not_9_port, outb =>
mult_125_G4_B_notx_9_port);
U398 : inv port map( inb => mult_125_G4_B_not_10_port, outb =>
mult_125_G4_B_notx_10_port);
U399 : inv port map( inb => mult_125_G4_B_not_11_port, outb =>
mult_125_G4_B_notx_11_port);
U400 : inv port map( inb => mult_125_G4_B_not_12_port, outb =>
mult_125_G4_B_notx_12_port);
U401 : inv port map( inb => mult_125_G4_B_not_13_port, outb =>
mult_125_G4_B_notx_13_port);
U402 : inv port map( inb => mult_125_G4_B_not_14_port, outb =>
mult_125_G4_B_notx_14_port);
U403 : inv port map( inb => n5540, outb =>
mult_125_G4_FS_1_TEMP_P_0_0_0_port);
U404 : inv port map( inb => n5660, outb => mult_125_G4_FS_1_C_1_4_0_port);
U405 : inv port map( inb => n5665, outb => mult_125_FS_1_TEMP_P_0_0_0_port);
U406 : inv port map( inb => n5785, outb => mult_125_FS_1_C_1_4_0_port);
U407 : inv port map( inb => n5790, outb =>
mult_125_G2_FS_1_TEMP_P_0_0_0_port);
U408 : inv port map( inb => n5910, outb => mult_125_G2_FS_1_C_1_4_0_port);
U409 : inv port map( inb => n5915, outb =>
mult_125_G3_FS_1_TEMP_P_0_0_0_port);
U410 : inv port map( inb => n6035, outb => mult_125_G3_FS_1_C_1_4_0_port);
U411 : inv port map( inb => mult_125_FS_1_TEMP_P_0_0_0_port, outb => n5666);
U412 : inv port map( inb => n5667, outb => mult_125_FS_1_P_0_0_1_port);
U413 : inv port map( inb => mult_125_FS_1_P_0_0_1_port, outb => n5668);
U414 : inv port map( inb => n5669, outb => mult_125_FS_1_P_0_0_2_port);
U415 : inv port map( inb => mult_125_FS_1_P_0_0_2_port, outb => n5670);
U416 : inv port map( inb => n5671, outb => mult_125_FS_1_P_0_0_3_port);
U417 : inv port map( inb => mult_125_FS_1_P_0_0_3_port, outb => n5672);
U418 : inv port map( inb => n5673, outb => mult_125_FS_1_TEMP_P_0_1_0_port);
U419 : inv port map( inb => mult_125_FS_1_TEMP_P_0_1_0_port, outb => n5674);
U420 : inv port map( inb => n5675, outb => mult_125_FS_1_P_0_1_1_port);
U421 : inv port map( inb => mult_125_FS_1_P_0_1_1_port, outb => n5676);
U422 : inv port map( inb => n5677, outb => mult_125_FS_1_P_0_1_2_port);
U423 : inv port map( inb => mult_125_FS_1_P_0_1_2_port, outb => n5678);
U424 : inv port map( inb => n5679, outb => mult_125_FS_1_P_0_1_3_port);
U425 : inv port map( inb => mult_125_FS_1_P_0_1_3_port, outb => n5680);
U426 : inv port map( inb => n5681, outb => mult_125_FS_1_TEMP_P_0_2_0_port);
U427 : inv port map( inb => mult_125_FS_1_TEMP_P_0_2_0_port, outb => n5682);
U428 : inv port map( inb => n5683, outb => mult_125_FS_1_P_0_2_1_port);
U429 : inv port map( inb => mult_125_FS_1_P_0_2_1_port, outb => n5684);
U430 : inv port map( inb => n5685, outb => mult_125_FS_1_P_0_2_2_port);
U431 : inv port map( inb => mult_125_FS_1_P_0_2_2_port, outb => n5686);
U432 : inv port map( inb => n5687, outb => mult_125_FS_1_P_0_2_3_port);
U433 : inv port map( inb => mult_125_FS_1_P_0_2_3_port, outb => n5688);
U434 : inv port map( inb => n5775, outb => mult_125_FS_1_G_2_0_0_port);
U435 : inv port map( inb => n5689, outb => mult_125_FS_1_TEMP_P_0_3_0_port);
U436 : inv port map( inb => mult_125_FS_1_TEMP_P_0_3_0_port, outb => n5690);
U437 : inv port map( inb => n5691, outb => mult_125_FS_1_P_0_3_1_port);
U438 : inv port map( inb => mult_125_FS_1_P_0_3_1_port, outb => n5692);
U439 : inv port map( inb => mult_125_FS_1_G_n_int_0_3_2_port, outb =>
mult_125_FS_1_C_1_3_3_port);
U440 : inv port map( inb => mult_125_FS_1_G_n_int_0_3_2_port, outb =>
mult_125_FS_1_TEMP_G_0_3_2_port);
U441 : inv port map( inb => mult_125_G2_FS_1_TEMP_P_0_0_0_port, outb =>
n5791);
U442 : inv port map( inb => n5792, outb => mult_125_G2_FS_1_P_0_0_1_port);
U443 : inv port map( inb => mult_125_G2_FS_1_P_0_0_1_port, outb => n5793);
U444 : inv port map( inb => n5794, outb => mult_125_G2_FS_1_P_0_0_2_port);
U445 : inv port map( inb => mult_125_G2_FS_1_P_0_0_2_port, outb => n5795);
U446 : inv port map( inb => n5796, outb => mult_125_G2_FS_1_P_0_0_3_port);
U447 : inv port map( inb => mult_125_G2_FS_1_P_0_0_3_port, outb => n5797);
U448 : inv port map( inb => n5798, outb =>
mult_125_G2_FS_1_TEMP_P_0_1_0_port);
U449 : inv port map( inb => mult_125_G2_FS_1_TEMP_P_0_1_0_port, outb =>
n5799);
U450 : inv port map( inb => n5800, outb => mult_125_G2_FS_1_P_0_1_1_port);
U451 : inv port map( inb => mult_125_G2_FS_1_P_0_1_1_port, outb => n5801);
U452 : inv port map( inb => n5802, outb => mult_125_G2_FS_1_P_0_1_2_port);
U453 : inv port map( inb => mult_125_G2_FS_1_P_0_1_2_port, outb => n5803);
U454 : inv port map( inb => n5804, outb => mult_125_G2_FS_1_P_0_1_3_port);
U455 : inv port map( inb => mult_125_G2_FS_1_P_0_1_3_port, outb => n5805);
U456 : inv port map( inb => n5806, outb =>
mult_125_G2_FS_1_TEMP_P_0_2_0_port);
U457 : inv port map( inb => mult_125_G2_FS_1_TEMP_P_0_2_0_port, outb =>
n5807);
U458 : inv port map( inb => n5808, outb => mult_125_G2_FS_1_P_0_2_1_port);
U459 : inv port map( inb => mult_125_G2_FS_1_P_0_2_1_port, outb => n5809);
U460 : inv port map( inb => n5810, outb => mult_125_G2_FS_1_P_0_2_2_port);
U461 : inv port map( inb => mult_125_G2_FS_1_P_0_2_2_port, outb => n5811);
U462 : inv port map( inb => n5812, outb => mult_125_G2_FS_1_P_0_2_3_port);
U463 : inv port map( inb => mult_125_G2_FS_1_P_0_2_3_port, outb => n5813);
U464 : inv port map( inb => n5900, outb => mult_125_G2_FS_1_G_2_0_0_port);
U465 : inv port map( inb => n5814, outb =>
mult_125_G2_FS_1_TEMP_P_0_3_0_port);
U466 : inv port map( inb => mult_125_G2_FS_1_TEMP_P_0_3_0_port, outb =>
n5815);
U467 : inv port map( inb => n5816, outb => mult_125_G2_FS_1_P_0_3_1_port);
U468 : inv port map( inb => mult_125_G2_FS_1_P_0_3_1_port, outb => n5817);
U469 : inv port map( inb => mult_125_G2_FS_1_G_n_int_0_3_2_port, outb =>
mult_125_G2_FS_1_C_1_3_3_port);
U470 : inv port map( inb => mult_125_G2_FS_1_G_n_int_0_3_2_port, outb =>
mult_125_G2_FS_1_TEMP_G_0_3_2_port);
U471 : inv port map( inb => mult_125_G3_FS_1_TEMP_P_0_0_0_port, outb =>
n5916);
U472 : inv port map( inb => n5917, outb => mult_125_G3_FS_1_P_0_0_1_port);
U473 : inv port map( inb => mult_125_G3_FS_1_P_0_0_1_port, outb => n5918);
U474 : inv port map( inb => n5919, outb => mult_125_G3_FS_1_P_0_0_2_port);
U475 : inv port map( inb => mult_125_G3_FS_1_P_0_0_2_port, outb => n5920);
U476 : inv port map( inb => n5921, outb => mult_125_G3_FS_1_P_0_0_3_port);
U477 : inv port map( inb => mult_125_G3_FS_1_P_0_0_3_port, outb => n5922);
U478 : inv port map( inb => n5923, outb =>
mult_125_G3_FS_1_TEMP_P_0_1_0_port);
U479 : inv port map( inb => mult_125_G3_FS_1_TEMP_P_0_1_0_port, outb =>
n5924);
U480 : inv port map( inb => n5925, outb => mult_125_G3_FS_1_P_0_1_1_port);
U481 : inv port map( inb => mult_125_G3_FS_1_P_0_1_1_port, outb => n5926);
U482 : inv port map( inb => n5927, outb => mult_125_G3_FS_1_P_0_1_2_port);
U483 : inv port map( inb => mult_125_G3_FS_1_P_0_1_2_port, outb => n5928);
U484 : inv port map( inb => n5929, outb => mult_125_G3_FS_1_P_0_1_3_port);
U485 : inv port map( inb => mult_125_G3_FS_1_P_0_1_3_port, outb => n5930);
U486 : inv port map( inb => n5931, outb =>
mult_125_G3_FS_1_TEMP_P_0_2_0_port);
U487 : inv port map( inb => mult_125_G3_FS_1_TEMP_P_0_2_0_port, outb =>
n5932);
U488 : inv port map( inb => n5933, outb => mult_125_G3_FS_1_P_0_2_1_port);
U489 : inv port map( inb => mult_125_G3_FS_1_P_0_2_1_port, outb => n5934);
U490 : inv port map( inb => n5935, outb => mult_125_G3_FS_1_P_0_2_2_port);
U491 : inv port map( inb => mult_125_G3_FS_1_P_0_2_2_port, outb => n5936);
U492 : inv port map( inb => n5937, outb => mult_125_G3_FS_1_P_0_2_3_port);
U493 : inv port map( inb => mult_125_G3_FS_1_P_0_2_3_port, outb => n5938);
U494 : inv port map( inb => n6025, outb => mult_125_G3_FS_1_G_2_0_0_port);
U495 : inv port map( inb => n5939, outb =>
mult_125_G3_FS_1_TEMP_P_0_3_0_port);
U496 : inv port map( inb => mult_125_G3_FS_1_TEMP_P_0_3_0_port, outb =>
n5940);
U497 : inv port map( inb => n5941, outb => mult_125_G3_FS_1_P_0_3_1_port);
U498 : inv port map( inb => mult_125_G3_FS_1_P_0_3_1_port, outb => n5942);
U499 : inv port map( inb => mult_125_G3_FS_1_G_n_int_0_3_2_port, outb =>
mult_125_G3_FS_1_C_1_3_3_port);
U500 : inv port map( inb => mult_125_G3_FS_1_G_n_int_0_3_2_port, outb =>
mult_125_G3_FS_1_TEMP_G_0_3_2_port);
U501 : inv port map( inb => mult_125_G4_FS_1_TEMP_P_0_0_0_port, outb =>
n5541);
U502 : inv port map( inb => n5542, outb => mult_125_G4_FS_1_P_0_0_1_port);
U503 : inv port map( inb => mult_125_G4_FS_1_P_0_0_1_port, outb => n5543);
U504 : inv port map( inb => n5544, outb => mult_125_G4_FS_1_P_0_0_2_port);
U505 : inv port map( inb => mult_125_G4_FS_1_P_0_0_2_port, outb => n5545);
U506 : inv port map( inb => n5546, outb => mult_125_G4_FS_1_P_0_0_3_port);
U507 : inv port map( inb => mult_125_G4_FS_1_P_0_0_3_port, outb => n5547);
U508 : inv port map( inb => n5548, outb =>
mult_125_G4_FS_1_TEMP_P_0_1_0_port);
U509 : inv port map( inb => mult_125_G4_FS_1_TEMP_P_0_1_0_port, outb =>
n5549);
U510 : inv port map( inb => n5550, outb => mult_125_G4_FS_1_P_0_1_1_port);
U511 : inv port map( inb => mult_125_G4_FS_1_P_0_1_1_port, outb => n5551);
U512 : inv port map( inb => n5552, outb => mult_125_G4_FS_1_P_0_1_2_port);
U513 : inv port map( inb => mult_125_G4_FS_1_P_0_1_2_port, outb => n5553);
U514 : inv port map( inb => n5554, outb => mult_125_G4_FS_1_P_0_1_3_port);
U515 : inv port map( inb => mult_125_G4_FS_1_P_0_1_3_port, outb => n5555);
U516 : inv port map( inb => n5556, outb =>
mult_125_G4_FS_1_TEMP_P_0_2_0_port);
U517 : inv port map( inb => mult_125_G4_FS_1_TEMP_P_0_2_0_port, outb =>
n5557);
U518 : inv port map( inb => n5558, outb => mult_125_G4_FS_1_P_0_2_1_port);
U519 : inv port map( inb => mult_125_G4_FS_1_P_0_2_1_port, outb => n5559);
U520 : inv port map( inb => n5560, outb => mult_125_G4_FS_1_P_0_2_2_port);
U521 : inv port map( inb => mult_125_G4_FS_1_P_0_2_2_port, outb => n5561);
U522 : inv port map( inb => n5562, outb => mult_125_G4_FS_1_P_0_2_3_port);
U523 : inv port map( inb => mult_125_G4_FS_1_P_0_2_3_port, outb => n5563);
U524 : inv port map( inb => n5650, outb => mult_125_G4_FS_1_G_2_0_0_port);
U525 : inv port map( inb => n5564, outb =>
mult_125_G4_FS_1_TEMP_P_0_3_0_port);
U526 : inv port map( inb => mult_125_G4_FS_1_TEMP_P_0_3_0_port, outb =>
n5565);
U527 : inv port map( inb => n5566, outb => mult_125_G4_FS_1_P_0_3_1_port);
U528 : inv port map( inb => mult_125_G4_FS_1_P_0_3_1_port, outb => n5567);
U529 : inv port map( inb => mult_125_G4_FS_1_G_n_int_0_3_2_port, outb =>
mult_125_G4_FS_1_C_1_3_3_port);
U530 : inv port map( inb => mult_125_G4_FS_1_G_n_int_0_3_2_port, outb =>
mult_125_G4_FS_1_TEMP_G_0_3_2_port);
U531 : oai22 port map( a => mult_125_G4_QB, b => mult_125_G4_ab_15_15_port,
c => mult_125_G4_QA, d => n240, outb =>
mult_125_G4_A1_29_port);
U532 : nor2 port map( a => n241, b => n242, outb => mult_125_G4_A2_29_port);
U533 : nor2 port map( a => n243, b => n244, outb => mult_125_G4_A2_28_port);
U534 : nor2 port map( a => n245, b => n246, outb => mult_125_G4_A2_27_port);
U535 : nor2 port map( a => n247, b => n248, outb => mult_125_G4_A2_26_port);
U536 : nor2 port map( a => n249, b => n250, outb => mult_125_G4_A2_25_port);
U537 : nor2 port map( a => n251, b => n252, outb => mult_125_G4_A2_24_port);
U538 : nor2 port map( a => n253, b => n254, outb => mult_125_G4_A2_23_port);
U539 : nor2 port map( a => n255, b => n256, outb => mult_125_G4_A2_22_port);
U540 : nor2 port map( a => n257, b => n258, outb => mult_125_G4_A2_21_port);
U541 : nor2 port map( a => n259, b => n260, outb => mult_125_G4_A2_20_port);
U542 : nor2 port map( a => n261, b => n262, outb => mult_125_G4_A2_19_port);
U543 : nor2 port map( a => n263, b => n264, outb => mult_125_G4_A2_18_port);
U544 : nand2 port map( a => n266, b => n267, outb => n265);
U545 : nor2 port map( a => n268, b => n269, outb => mult_125_G4_A2_16_port);
U546 : nor2 port map( a => n270, b => n271, outb => mult_125_G4_A2_15_port);
U547 : oai22 port map( a => n272, b => n273, c => n274, d => n275, outb =>
mult_125_G4_A2_14_port);
U548 : oai22 port map( a => mult_125_QB, b => mult_125_ab_15_15_port, c =>
mult_125_QA, d => n276, outb => mult_125_A1_29_port)
;
U549 : nor2 port map( a => n277, b => n278, outb => mult_125_A2_29_port);
U550 : nor2 port map( a => n279, b => n280, outb => mult_125_A2_28_port);
U551 : nor2 port map( a => n281, b => n282, outb => mult_125_A2_27_port);
U552 : nor2 port map( a => n283, b => n284, outb => mult_125_A2_26_port);
U553 : nor2 port map( a => n285, b => n286, outb => mult_125_A2_25_port);
U554 : nor2 port map( a => n287, b => n288, outb => mult_125_A2_24_port);
U555 : nor2 port map( a => n289, b => n290, outb => mult_125_A2_23_port);
U556 : nor2 port map( a => n291, b => n292, outb => mult_125_A2_22_port);
U557 : nor2 port map( a => n293, b => n294, outb => mult_125_A2_21_port);
U558 : nor2 port map( a => n295, b => n296, outb => mult_125_A2_20_port);
U559 : nor2 port map( a => n297, b => n298, outb => mult_125_A2_19_port);
U560 : nor2 port map( a => n299, b => n300, outb => mult_125_A2_18_port);
U561 : nand2 port map( a => n302, b => n303, outb => n301);
U562 : nor2 port map( a => n304, b => n305, outb => mult_125_A2_16_port);
U563 : nor2 port map( a => n306, b => n307, outb => mult_125_A2_15_port);
U564 : oai22 port map( a => n308, b => n309, c => n310, d => n311, outb =>
mult_125_A2_14_port);
U565 : oai22 port map( a => mult_125_G2_QB, b => mult_125_G2_ab_15_15_port,
c => mult_125_G2_QA, d => n312, outb =>
mult_125_G2_A1_29_port);
U566 : nor2 port map( a => n313, b => n314, outb => mult_125_G2_A2_29_port);
U567 : nor2 port map( a => n315, b => n316, outb => mult_125_G2_A2_28_port);
U568 : nor2 port map( a => n317, b => n318, outb => mult_125_G2_A2_27_port);
U569 : nor2 port map( a => n319, b => n320, outb => mult_125_G2_A2_26_port);
U570 : nor2 port map( a => n321, b => n322, outb => mult_125_G2_A2_25_port);
U571 : nor2 port map( a => n323, b => n324, outb => mult_125_G2_A2_24_port);
U572 : nor2 port map( a => n325, b => n326, outb => mult_125_G2_A2_23_port);
U573 : nor2 port map( a => n327, b => n328, outb => mult_125_G2_A2_22_port);
U574 : nor2 port map( a => n329, b => n330, outb => mult_125_G2_A2_21_port);
U575 : nor2 port map( a => n331, b => n332, outb => mult_125_G2_A2_20_port);
U576 : nor2 port map( a => n333, b => n334, outb => mult_125_G2_A2_19_port);
U577 : nor2 port map( a => n335, b => n336, outb => mult_125_G2_A2_18_port);
U578 : nand2 port map( a => n338, b => n339, outb => n337);
U579 : nor2 port map( a => n340, b => n341, outb => mult_125_G2_A2_16_port);
U580 : nor2 port map( a => n342, b => n343, outb => mult_125_G2_A2_15_port);
U581 : oai22 port map( a => n344, b => n345, c => n346, d => n347, outb =>
mult_125_G2_A2_14_port);
U582 : oai22 port map( a => mult_125_G3_QB, b => mult_125_G3_ab_15_15_port,
c => mult_125_G3_QA, d => n348, outb =>
mult_125_G3_A1_29_port);
U583 : nor2 port map( a => n349, b => n350, outb => mult_125_G3_A2_29_port);
U584 : nor2 port map( a => n351, b => n352, outb => mult_125_G3_A2_28_port);
U585 : nor2 port map( a => n353, b => n354, outb => mult_125_G3_A2_27_port);
U586 : nor2 port map( a => n355, b => n356, outb => mult_125_G3_A2_26_port);
U587 : nor2 port map( a => n357, b => n358, outb => mult_125_G3_A2_25_port);
U588 : nor2 port map( a => n359, b => n360, outb => mult_125_G3_A2_24_port);
U589 : nor2 port map( a => n361, b => n362, outb => mult_125_G3_A2_23_port);
U590 : nor2 port map( a => n363, b => n364, outb => mult_125_G3_A2_22_port);
U591 : nor2 port map( a => n365, b => n366, outb => mult_125_G3_A2_21_port);
U592 : nor2 port map( a => n367, b => n368, outb => mult_125_G3_A2_20_port);
U593 : nor2 port map( a => n369, b => n370, outb => mult_125_G3_A2_19_port);
U594 : nor2 port map( a => n371, b => n372, outb => mult_125_G3_A2_18_port);
U595 : nand2 port map( a => n374, b => n375, outb => n373);
U596 : nor2 port map( a => n376, b => n377, outb => mult_125_G3_A2_16_port);
U597 : nor2 port map( a => n378, b => n379, outb => mult_125_G3_A2_15_port);
U598 : oai22 port map( a => n380, b => n381, c => n382, d => n383, outb =>
mult_125_G3_A2_14_port);
U599 : nor2 port map( a => mult_125_G4_ab_1_15_port, b =>
mult_125_G4_ab_2_14_port, outb => n384);
U600 : nor2 port map( a => mult_125_G4_ab_2_15_port, b =>
mult_125_G4_ab_3_14_port, outb => n385);
U601 : nor2 port map( a => mult_125_G4_ab_3_15_port, b =>
mult_125_G4_ab_4_14_port, outb => n386);
U602 : nor2 port map( a => mult_125_G4_ab_4_15_port, b =>
mult_125_G4_ab_5_14_port, outb => n387);
U603 : nor2 port map( a => mult_125_G4_ab_5_15_port, b =>
mult_125_G4_ab_6_14_port, outb => n388);
U604 : nor2 port map( a => mult_125_G4_ab_6_15_port, b =>
mult_125_G4_ab_7_14_port, outb => n389);
U605 : nor2 port map( a => mult_125_G4_ab_7_15_port, b =>
mult_125_G4_ab_8_14_port, outb => n390);
U606 : nor2 port map( a => mult_125_G4_ab_8_15_port, b =>
mult_125_G4_ab_9_14_port, outb => n391);
U607 : nor2 port map( a => mult_125_G4_ab_9_15_port, b =>
mult_125_G4_ab_10_14_port, outb => n392);
U608 : nor2 port map( a => mult_125_G4_ab_10_15_port, b =>
mult_125_G4_ab_11_14_port, outb => n393);
U609 : nor2 port map( a => mult_125_G4_ab_11_15_port, b =>
mult_125_G4_ab_12_14_port, outb => n394);
U610 : nor2 port map( a => mult_125_G4_ab_12_15_port, b =>
mult_125_G4_ab_13_14_port, outb => n395);
U611 : nor2 port map( a => mult_125_G4_ab_13_15_port, b =>
mult_125_G4_ab_14_14_port, outb => n396);
U612 : nor2 port map( a => mult_125_G4_ab_14_15_port, b =>
mult_125_G4_ab_15_14_port, outb => n397);
U613 : nand2 port map( a => n399, b => n400, outb => n398);
U614 : nand2 port map( a => n402, b => n403, outb => n401);
U615 : nor2 port map( a => mult_125_G4_ab_4_13_port, b => n405, outb => n404
);
U616 : nor2 port map( a => mult_125_G4_ab_5_13_port, b => n407, outb => n406
);
U617 : nor2 port map( a => mult_125_G4_ab_6_13_port, b => n409, outb => n408
);
U618 : nor2 port map( a => mult_125_G4_ab_7_13_port, b => n411, outb => n410
);
U619 : nor2 port map( a => mult_125_G4_ab_8_13_port, b => n413, outb => n412
);
U620 : nor2 port map( a => mult_125_G4_ab_9_13_port, b => n415, outb => n414
);
U621 : nor2 port map( a => mult_125_G4_ab_10_13_port, b => n417, outb =>
n416);
U622 : nor2 port map( a => mult_125_G4_ab_11_13_port, b => n419, outb =>
n418);
U623 : nor2 port map( a => mult_125_G4_ab_12_13_port, b => n421, outb =>
n420);
U624 : nor2 port map( a => mult_125_G4_ab_13_13_port, b => n423, outb =>
n422);
U625 : nor2 port map( a => mult_125_G4_ab_14_13_port, b => n425, outb =>
n424);
U626 : nor2 port map( a => mult_125_G4_ab_15_13_port, b => n427, outb =>
n426);
U627 : nand2 port map( a => n429, b => n430, outb => n428);
U628 : nor2 port map( a => mult_125_G4_ab_3_12_port, b => n432, outb => n431
);
U629 : nor2 port map( a => mult_125_G4_ab_4_12_port, b => n434, outb => n433
);
U630 : nor2 port map( a => mult_125_G4_ab_5_12_port, b => n436, outb => n435
);
U631 : nor2 port map( a => mult_125_G4_ab_6_12_port, b => n438, outb => n437
);
U632 : nor2 port map( a => mult_125_G4_ab_7_12_port, b => n440, outb => n439
);
U633 : nor2 port map( a => mult_125_G4_ab_8_12_port, b => n442, outb => n441
);
U634 : nor2 port map( a => mult_125_G4_ab_9_12_port, b => n444, outb => n443
);
U635 : nor2 port map( a => mult_125_G4_ab_10_12_port, b => n446, outb =>
n445);
U636 : nor2 port map( a => mult_125_G4_ab_11_12_port, b => n448, outb =>
n447);
U637 : nor2 port map( a => mult_125_G4_ab_12_12_port, b => n450, outb =>
n449);
U638 : nor2 port map( a => mult_125_G4_ab_13_12_port, b => n452, outb =>
n451);
U639 : nor2 port map( a => mult_125_G4_ab_14_12_port, b => n454, outb =>
n453);
U640 : nor2 port map( a => mult_125_G4_ab_15_12_port, b => n456, outb =>
n455);
U641 : nand2 port map( a => n458, b => n459, outb => n457);
U642 : nand2 port map( a => n461, b => n462, outb => n460);
U643 : nor2 port map( a => mult_125_G4_ab_4_11_port, b => n464, outb => n463
);
U644 : nor2 port map( a => mult_125_G4_ab_5_11_port, b => n466, outb => n465
);
U645 : nor2 port map( a => mult_125_G4_ab_6_11_port, b => n468, outb => n467
);
U646 : nor2 port map( a => mult_125_G4_ab_7_11_port, b => n470, outb => n469
);
U647 : nor2 port map( a => mult_125_G4_ab_8_11_port, b => n472, outb => n471
);
U648 : nor2 port map( a => mult_125_G4_ab_9_11_port, b => n474, outb => n473
);
U649 : nor2 port map( a => mult_125_G4_ab_10_11_port, b => n476, outb =>
n475);
U650 : nor2 port map( a => mult_125_G4_ab_11_11_port, b => n478, outb =>
n477);
U651 : nor2 port map( a => mult_125_G4_ab_12_11_port, b => n480, outb =>
n479);
U652 : nor2 port map( a => mult_125_G4_ab_13_11_port, b => n482, outb =>
n481);
U653 : nor2 port map( a => mult_125_G4_ab_14_11_port, b => n484, outb =>
n483);
U654 : nand2 port map( a => n486, b => n487, outb => n485);
U655 : nand2 port map( a => n489, b => n490, outb => n488);
U656 : nor2 port map( a => mult_125_G4_ab_3_10_port, b => n492, outb => n491
);
U657 : nor2 port map( a => mult_125_G4_ab_4_10_port, b => n494, outb => n493
);
U658 : nand2 port map( a => n496, b => n497, outb => n495);
U659 : nor2 port map( a => mult_125_G4_ab_6_10_port, b => n499, outb => n498
);
U660 : nor2 port map( a => mult_125_G4_ab_7_10_port, b => n501, outb => n500
);
U661 : nor2 port map( a => mult_125_G4_ab_8_10_port, b => n503, outb => n502
);
U662 : nor2 port map( a => mult_125_G4_ab_9_10_port, b => n505, outb => n504
);
U663 : nor2 port map( a => mult_125_G4_ab_10_10_port, b => n507, outb =>
n506);
U664 : nor2 port map( a => mult_125_G4_ab_11_10_port, b => n509, outb =>
n508);
U665 : nor2 port map( a => mult_125_G4_ab_12_10_port, b => n511, outb =>
n510);
U666 : nor2 port map( a => mult_125_G4_ab_13_10_port, b => n513, outb =>
n512);
U667 : nor2 port map( a => mult_125_G4_ab_14_10_port, b => n515, outb =>
n514);
U668 : nor2 port map( a => mult_125_G4_ab_15_10_port, b => n517, outb =>
n516);
U669 : nand2 port map( a => n519, b => n520, outb => n518);
U670 : nor2 port map( a => mult_125_G4_ab_3_9_port, b => n522, outb => n521)
;
U671 : nor2 port map( a => mult_125_G4_ab_4_9_port, b => n524, outb => n523)
;
U672 : nor2 port map( a => mult_125_G4_ab_5_9_port, b => n526, outb => n525)
;
U673 : nor2 port map( a => mult_125_G4_ab_6_9_port, b => n528, outb => n527)
;
U674 : nor2 port map( a => mult_125_G4_ab_7_9_port, b => n530, outb => n529)
;
U675 : nor2 port map( a => mult_125_G4_ab_8_9_port, b => n532, outb => n531)
;
U676 : nor2 port map( a => mult_125_G4_ab_9_9_port, b => n534, outb => n533)
;
U677 : nor2 port map( a => mult_125_G4_ab_10_9_port, b => n536, outb => n535
);
U678 : nor2 port map( a => mult_125_G4_ab_11_9_port, b => n538, outb => n537
);
U679 : nor2 port map( a => mult_125_G4_ab_12_9_port, b => n540, outb => n539
);
U680 : nor2 port map( a => mult_125_G4_ab_13_9_port, b => n542, outb => n541
);
U681 : nor2 port map( a => mult_125_G4_ab_14_9_port, b => n544, outb => n543
);
U682 : nand2 port map( a => n546, b => n547, outb => n545);
U683 : nand2 port map( a => n549, b => n550, outb => n548);
U684 : nor2 port map( a => mult_125_G4_ab_3_8_port, b => n552, outb => n551)
;
U685 : nor2 port map( a => mult_125_G4_ab_4_8_port, b => n554, outb => n553)
;
U686 : nor2 port map( a => mult_125_G4_ab_5_8_port, b => n556, outb => n555)
;
U687 : nor2 port map( a => mult_125_G4_ab_6_8_port, b => n558, outb => n557)
;
U688 : nor2 port map( a => mult_125_G4_ab_7_8_port, b => n560, outb => n559)
;
U689 : nor2 port map( a => mult_125_G4_ab_8_8_port, b => n562, outb => n561)
;
U690 : nor2 port map( a => mult_125_G4_ab_9_8_port, b => n564, outb => n563)
;
U691 : nor2 port map( a => mult_125_G4_ab_10_8_port, b => n566, outb => n565
);
U692 : nor2 port map( a => mult_125_G4_ab_11_8_port, b => n568, outb => n567
);
U693 : nor2 port map( a => mult_125_G4_ab_12_8_port, b => n570, outb => n569
);
U694 : nor2 port map( a => mult_125_G4_ab_13_8_port, b => n572, outb => n571
);
U695 : nor2 port map( a => mult_125_G4_ab_14_8_port, b => n574, outb => n573
);
U696 : nor2 port map( a => mult_125_G4_ab_15_8_port, b => n576, outb => n575
);
U697 : nand2 port map( a => n578, b => n579, outb => n577);
U698 : nand2 port map( a => n581, b => n582, outb => n580);
U699 : nor2 port map( a => mult_125_G4_ab_4_7_port, b => n584, outb => n583)
;
U700 : nor2 port map( a => mult_125_G4_ab_5_7_port, b => n586, outb => n585)
;
U701 : nor2 port map( a => mult_125_G4_ab_6_7_port, b => n588, outb => n587)
;
U702 : nor2 port map( a => mult_125_G4_ab_7_7_port, b => n590, outb => n589)
;
U703 : nor2 port map( a => mult_125_G4_ab_8_7_port, b => n592, outb => n591)
;
U704 : nor2 port map( a => mult_125_G4_ab_9_7_port, b => n594, outb => n593)
;
U705 : nor2 port map( a => mult_125_G4_ab_10_7_port, b => n596, outb => n595
);
U706 : nor2 port map( a => mult_125_G4_ab_11_7_port, b => n598, outb => n597
);
U707 : nor2 port map( a => mult_125_G4_ab_12_7_port, b => n600, outb => n599
);
U708 : nor2 port map( a => mult_125_G4_ab_13_7_port, b => n602, outb => n601
);
U709 : nor2 port map( a => mult_125_G4_ab_14_7_port, b => n604, outb => n603
);
U710 : nand2 port map( a => n606, b => n607, outb => n605);
U711 : nand2 port map( a => n609, b => n610, outb => n608);
U712 : nor2 port map( a => mult_125_G4_ab_3_6_port, b => n612, outb => n611)
;
U713 : nor2 port map( a => mult_125_G4_ab_4_6_port, b => n614, outb => n613)
;
U714 : nand2 port map( a => n616, b => n617, outb => n615);
U715 : nor2 port map( a => mult_125_G4_ab_6_6_port, b => n619, outb => n618)
;
U716 : nor2 port map( a => mult_125_G4_ab_7_6_port, b => n621, outb => n620)
;
U717 : nor2 port map( a => mult_125_G4_ab_8_6_port, b => n623, outb => n622)
;
U718 : nand2 port map( a => n625, b => n626, outb => n624);
U719 : nor2 port map( a => mult_125_G4_ab_10_6_port, b => n628, outb => n627
);
U720 : nor2 port map( a => mult_125_G4_ab_11_6_port, b => n630, outb => n629
);
U721 : nor2 port map( a => mult_125_G4_ab_12_6_port, b => n632, outb => n631
);
U722 : nor2 port map( a => mult_125_G4_ab_13_6_port, b => n634, outb => n633
);
U723 : nor2 port map( a => mult_125_G4_ab_14_6_port, b => n636, outb => n635
);
U724 : nor2 port map( a => mult_125_G4_ab_15_6_port, b => n638, outb => n637
);
U725 : nand2 port map( a => n640, b => n641, outb => n639);
U726 : nand2 port map( a => n643, b => n644, outb => n642);
U727 : nor2 port map( a => mult_125_G4_ab_4_5_port, b => n646, outb => n645)
;
U728 : nor2 port map( a => mult_125_G4_ab_5_5_port, b => n648, outb => n647)
;
U729 : nand2 port map( a => n650, b => n651, outb => n649);
U730 : nor2 port map( a => mult_125_G4_ab_7_5_port, b => n653, outb => n652)
;
U731 : nor2 port map( a => mult_125_G4_ab_8_5_port, b => n655, outb => n654)
;
U732 : nor2 port map( a => mult_125_G4_ab_9_5_port, b => n657, outb => n656)
;
U733 : nor2 port map( a => mult_125_G4_ab_10_5_port, b => n659, outb => n658
);
U734 : nor2 port map( a => mult_125_G4_ab_11_5_port, b => n661, outb => n660
);
U735 : nor2 port map( a => mult_125_G4_ab_12_5_port, b => n663, outb => n662
);
U736 : nor2 port map( a => mult_125_G4_ab_13_5_port, b => n665, outb => n664
);
U737 : nor2 port map( a => mult_125_G4_ab_14_5_port, b => n667, outb => n666
);
U738 : nand2 port map( a => n669, b => n670, outb => n668);
U739 : nand2 port map( a => n672, b => n673, outb => n671);
U740 : nor2 port map( a => mult_125_G4_ab_3_4_port, b => n675, outb => n674)
;
U741 : nor2 port map( a => mult_125_G4_ab_4_4_port, b => n677, outb => n676)
;
U742 : nand2 port map( a => n679, b => n680, outb => n678);
U743 : nor2 port map( a => mult_125_G4_ab_6_4_port, b => n682, outb => n681)
;
U744 : nand2 port map( a => n684, b => n685, outb => n683);
U745 : nor2 port map( a => mult_125_G4_ab_8_4_port, b => n687, outb => n686)
;
U746 : nor2 port map( a => mult_125_G4_ab_9_4_port, b => n689, outb => n688)
;
U747 : nor2 port map( a => mult_125_G4_ab_10_4_port, b => n691, outb => n690
);
U748 : nand2 port map( a => n693, b => n694, outb => n692);
U749 : nor2 port map( a => mult_125_G4_ab_12_4_port, b => n696, outb => n695
);
U750 : nor2 port map( a => mult_125_G4_ab_13_4_port, b => n698, outb => n697
);
U751 : nor2 port map( a => mult_125_G4_ab_14_4_port, b => n700, outb => n699
);
U752 : nand2 port map( a => n702, b => n703, outb => n701);
U753 : nand2 port map( a => n705, b => n706, outb => n704);
U754 : nand2 port map( a => n708, b => n709, outb => n707);
U755 : nor2 port map( a => mult_125_G4_ab_4_3_port, b => n711, outb => n710)
;
U756 : nor2 port map( a => mult_125_G4_ab_5_3_port, b => n713, outb => n712)
;
U757 : nor2 port map( a => mult_125_G4_ab_6_3_port, b => n715, outb => n714)
;
U758 : nor2 port map( a => mult_125_G4_ab_7_3_port, b => n717, outb => n716)
;
U759 : nor2 port map( a => mult_125_G4_ab_8_3_port, b => n719, outb => n718)
;
U760 : nor2 port map( a => mult_125_G4_ab_9_3_port, b => n721, outb => n720)
;
U761 : nor2 port map( a => mult_125_G4_ab_10_3_port, b => n723, outb => n722
);
U762 : nor2 port map( a => mult_125_G4_ab_11_3_port, b => n725, outb => n724
);
U763 : nor2 port map( a => mult_125_G4_ab_12_3_port, b => n727, outb => n726
);
U764 : nor2 port map( a => mult_125_G4_ab_13_3_port, b => n729, outb => n728
);
U765 : nor2 port map( a => mult_125_G4_ab_14_3_port, b => n731, outb => n730
);
U766 : nor2 port map( a => mult_125_G4_ab_15_3_port, b => n733, outb => n732
);
U767 : nand2 port map( a => n735, b => n736, outb => n734);
U768 : nor2 port map( a => mult_125_G4_ab_3_2_port, b => n738, outb => n737)
;
U769 : nor2 port map( a => mult_125_G4_ab_4_2_port, b => n740, outb => n739)
;
U770 : nor2 port map( a => mult_125_G4_ab_5_2_port, b => n742, outb => n741)
;
U771 : nor2 port map( a => mult_125_G4_ab_6_2_port, b => n744, outb => n743)
;
U772 : nand2 port map( a => n746, b => n747, outb => n745);
U773 : nor2 port map( a => mult_125_G4_ab_8_2_port, b => n749, outb => n748)
;
U774 : nor2 port map( a => mult_125_G4_ab_9_2_port, b => n751, outb => n750)
;
U775 : nor2 port map( a => mult_125_G4_ab_10_2_port, b => n753, outb => n752
);
U776 : nor2 port map( a => mult_125_G4_ab_11_2_port, b => n755, outb => n754
);
U777 : nor2 port map( a => mult_125_G4_ab_12_2_port, b => n757, outb => n756
);
U778 : nor2 port map( a => mult_125_G4_ab_13_2_port, b => n759, outb => n758
);
U779 : nor2 port map( a => mult_125_G4_ab_14_2_port, b => n761, outb => n760
);
U780 : nor2 port map( a => mult_125_G4_ab_15_2_port, b => n763, outb => n762
);
U781 : nand2 port map( a => n765, b => n766, outb => n764);
U782 : nor2 port map( a => mult_125_G4_ab_3_1_port, b => n768, outb => n767)
;
U783 : nor2 port map( a => mult_125_G4_ab_4_1_port, b => n770, outb => n769)
;
U784 : nor2 port map( a => mult_125_G4_ab_5_1_port, b => n772, outb => n771)
;
U785 : nor2 port map( a => mult_125_G4_ab_6_1_port, b => n774, outb => n773)
;
U786 : nor2 port map( a => mult_125_G4_ab_7_1_port, b => n776, outb => n775)
;
U787 : nor2 port map( a => mult_125_G4_ab_8_1_port, b => n778, outb => n777)
;
U788 : nor2 port map( a => mult_125_G4_ab_9_1_port, b => n780, outb => n779)
;
U789 : nor2 port map( a => mult_125_G4_ab_10_1_port, b => n782, outb => n781
);
U790 : nor2 port map( a => mult_125_G4_ab_11_1_port, b => n784, outb => n783
);
U791 : nor2 port map( a => mult_125_G4_ab_12_1_port, b => n786, outb => n785
);
U792 : nor2 port map( a => mult_125_G4_ab_13_1_port, b => n788, outb => n787
);
U793 : nor2 port map( a => mult_125_G4_ab_14_1_port, b => n790, outb => n789
);
U794 : nor2 port map( a => mult_125_G4_ab_15_1_port, b => n792, outb => n791
);
U795 : nor2 port map( a => mult_125_G4_ab_2_0_port, b => n794, outb => n793)
;
U796 : nor2 port map( a => mult_125_G4_ab_3_0_port, b => n796, outb => n795)
;
U797 : nor2 port map( a => mult_125_G4_ab_4_0_port, b => n798, outb => n797)
;
U798 : nor2 port map( a => mult_125_G4_ab_5_0_port, b => n800, outb => n799)
;
U799 : nor2 port map( a => mult_125_G4_ab_6_0_port, b => n802, outb => n801)
;
U800 : nor2 port map( a => mult_125_G4_ab_7_0_port, b => n804, outb => n803)
;
U801 : nor2 port map( a => mult_125_G4_ab_8_0_port, b => n806, outb => n805)
;
U802 : nor2 port map( a => mult_125_G4_ab_9_0_port, b => n808, outb => n807)
;
U803 : nor2 port map( a => mult_125_G4_ab_10_0_port, b => n810, outb => n809
);
U804 : nor2 port map( a => mult_125_G4_ab_11_0_port, b => n812, outb => n811
);
U805 : nor2 port map( a => mult_125_G4_ab_12_0_port, b => n814, outb => n813
);
U806 : nor2 port map( a => mult_125_G4_ab_13_0_port, b => n816, outb => n815
);
U807 : nor2 port map( a => mult_125_G4_ab_14_0_port, b => n818, outb => n817
);
U808 : nor2 port map( a => mult_125_G4_ab_15_0_port, b => n820, outb => n819
);
U809 : nor2 port map( a => mult_125_G4_ZB, b => mult_125_G4_ZA, outb => n274
);
U810 : nand2 port map( a => mult_125_G4_QB, b => mult_125_G4_ab_15_15_port,
outb => n821);
U811 : nor2 port map( a => mult_125_G3_ab_1_15_port, b =>
mult_125_G3_ab_2_14_port, outb => n822);
U812 : nor2 port map( a => mult_125_G3_ab_2_15_port, b =>
mult_125_G3_ab_3_14_port, outb => n823);
U813 : nor2 port map( a => mult_125_G3_ab_3_15_port, b =>
mult_125_G3_ab_4_14_port, outb => n824);
U814 : nor2 port map( a => mult_125_G3_ab_4_15_port, b =>
mult_125_G3_ab_5_14_port, outb => n825);
U815 : nor2 port map( a => mult_125_G3_ab_5_15_port, b =>
mult_125_G3_ab_6_14_port, outb => n826);
U816 : nor2 port map( a => mult_125_G3_ab_6_15_port, b =>
mult_125_G3_ab_7_14_port, outb => n827);
U817 : nor2 port map( a => mult_125_G3_ab_7_15_port, b =>
mult_125_G3_ab_8_14_port, outb => n828);
U818 : nor2 port map( a => mult_125_G3_ab_8_15_port, b =>
mult_125_G3_ab_9_14_port, outb => n829);
U819 : nor2 port map( a => mult_125_G3_ab_9_15_port, b =>
mult_125_G3_ab_10_14_port, outb => n830);
U820 : nor2 port map( a => mult_125_G3_ab_10_15_port, b =>
mult_125_G3_ab_11_14_port, outb => n831);
U821 : nor2 port map( a => mult_125_G3_ab_11_15_port, b =>
mult_125_G3_ab_12_14_port, outb => n832);
U822 : nor2 port map( a => mult_125_G3_ab_12_15_port, b =>
mult_125_G3_ab_13_14_port, outb => n833);
U823 : nor2 port map( a => mult_125_G3_ab_13_15_port, b =>
mult_125_G3_ab_14_14_port, outb => n834);
U824 : nor2 port map( a => mult_125_G3_ab_14_15_port, b =>
mult_125_G3_ab_15_14_port, outb => n835);
U825 : nand2 port map( a => n837, b => n838, outb => n836);
U826 : nand2 port map( a => n840, b => n841, outb => n839);
U827 : nor2 port map( a => mult_125_G3_ab_4_13_port, b => n843, outb => n842
);
U828 : nor2 port map( a => mult_125_G3_ab_5_13_port, b => n845, outb => n844
);
U829 : nor2 port map( a => mult_125_G3_ab_6_13_port, b => n847, outb => n846
);
U830 : nor2 port map( a => mult_125_G3_ab_7_13_port, b => n849, outb => n848
);
U831 : nor2 port map( a => mult_125_G3_ab_8_13_port, b => n851, outb => n850
);
U832 : nor2 port map( a => mult_125_G3_ab_9_13_port, b => n853, outb => n852
);
U833 : nor2 port map( a => mult_125_G3_ab_10_13_port, b => n855, outb =>
n854);
U834 : nor2 port map( a => mult_125_G3_ab_11_13_port, b => n857, outb =>
n856);
U835 : nor2 port map( a => mult_125_G3_ab_12_13_port, b => n859, outb =>
n858);
U836 : nor2 port map( a => mult_125_G3_ab_13_13_port, b => n861, outb =>
n860);
U837 : nor2 port map( a => mult_125_G3_ab_14_13_port, b => n863, outb =>
n862);
U838 : nor2 port map( a => mult_125_G3_ab_15_13_port, b => n865, outb =>
n864);
U839 : nand2 port map( a => n867, b => n868, outb => n866);
U840 : nor2 port map( a => mult_125_G3_ab_3_12_port, b => n870, outb => n869
);
U841 : nor2 port map( a => mult_125_G3_ab_4_12_port, b => n872, outb => n871
);
U842 : nor2 port map( a => mult_125_G3_ab_5_12_port, b => n874, outb => n873
);
U843 : nor2 port map( a => mult_125_G3_ab_6_12_port, b => n876, outb => n875
);
U844 : nor2 port map( a => mult_125_G3_ab_7_12_port, b => n878, outb => n877
);
U845 : nor2 port map( a => mult_125_G3_ab_8_12_port, b => n880, outb => n879
);
U846 : nor2 port map( a => mult_125_G3_ab_9_12_port, b => n882, outb => n881
);
U847 : nor2 port map( a => mult_125_G3_ab_10_12_port, b => n884, outb =>
n883);
U848 : nor2 port map( a => mult_125_G3_ab_11_12_port, b => n886, outb =>
n885);
U849 : nor2 port map( a => mult_125_G3_ab_12_12_port, b => n888, outb =>
n887);
U850 : nor2 port map( a => mult_125_G3_ab_13_12_port, b => n890, outb =>
n889);
U851 : nor2 port map( a => mult_125_G3_ab_14_12_port, b => n892, outb =>
n891);
U852 : nor2 port map( a => mult_125_G3_ab_15_12_port, b => n894, outb =>
n893);
U853 : nand2 port map( a => n896, b => n897, outb => n895);
U854 : nand2 port map( a => n899, b => n900, outb => n898);
U855 : nor2 port map( a => mult_125_G3_ab_4_11_port, b => n902, outb => n901
);
U856 : nor2 port map( a => mult_125_G3_ab_5_11_port, b => n904, outb => n903
);
U857 : nor2 port map( a => mult_125_G3_ab_6_11_port, b => n906, outb => n905
);
U858 : nor2 port map( a => mult_125_G3_ab_7_11_port, b => n908, outb => n907
);
U859 : nor2 port map( a => mult_125_G3_ab_8_11_port, b => n910, outb => n909
);
U860 : nor2 port map( a => mult_125_G3_ab_9_11_port, b => n912, outb => n911
);
U861 : nor2 port map( a => mult_125_G3_ab_10_11_port, b => n914, outb =>
n913);
U862 : nor2 port map( a => mult_125_G3_ab_11_11_port, b => n916, outb =>
n915);
U863 : nor2 port map( a => mult_125_G3_ab_12_11_port, b => n918, outb =>
n917);
U864 : nor2 port map( a => mult_125_G3_ab_13_11_port, b => n920, outb =>
n919);
U865 : nor2 port map( a => mult_125_G3_ab_14_11_port, b => n922, outb =>
n921);
U866 : nand2 port map( a => n924, b => n925, outb => n923);
U867 : nand2 port map( a => n927, b => n928, outb => n926);
U868 : nor2 port map( a => mult_125_G3_ab_3_10_port, b => n930, outb => n929
);
U869 : nor2 port map( a => mult_125_G3_ab_4_10_port, b => n932, outb => n931
);
U870 : nand2 port map( a => n934, b => n935, outb => n933);
U871 : nor2 port map( a => mult_125_G3_ab_6_10_port, b => n937, outb => n936
);
U872 : nor2 port map( a => mult_125_G3_ab_7_10_port, b => n939, outb => n938
);
U873 : nor2 port map( a => mult_125_G3_ab_8_10_port, b => n941, outb => n940
);
U874 : nor2 port map( a => mult_125_G3_ab_9_10_port, b => n943, outb => n942
);
U875 : nor2 port map( a => mult_125_G3_ab_10_10_port, b => n945, outb =>
n944);
U876 : nor2 port map( a => mult_125_G3_ab_11_10_port, b => n947, outb =>
n946);
U877 : nor2 port map( a => mult_125_G3_ab_12_10_port, b => n949, outb =>
n948);
U878 : nor2 port map( a => mult_125_G3_ab_13_10_port, b => n951, outb =>
n950);
U879 : nor2 port map( a => mult_125_G3_ab_14_10_port, b => n953, outb =>
n952);
U880 : nor2 port map( a => mult_125_G3_ab_15_10_port, b => n955, outb =>
n954);
U881 : nand2 port map( a => n957, b => n958, outb => n956);
U882 : nor2 port map( a => mult_125_G3_ab_3_9_port, b => n960, outb => n959)
;
U883 : nor2 port map( a => mult_125_G3_ab_4_9_port, b => n962, outb => n961)
;
U884 : nor2 port map( a => mult_125_G3_ab_5_9_port, b => n964, outb => n963)
;
U885 : nor2 port map( a => mult_125_G3_ab_6_9_port, b => n966, outb => n965)
;
U886 : nor2 port map( a => mult_125_G3_ab_7_9_port, b => n968, outb => n967)
;
U887 : nor2 port map( a => mult_125_G3_ab_8_9_port, b => n970, outb => n969)
;
U888 : nor2 port map( a => mult_125_G3_ab_9_9_port, b => n972, outb => n971)
;
U889 : nor2 port map( a => mult_125_G3_ab_10_9_port, b => n974, outb => n973
);
U890 : nor2 port map( a => mult_125_G3_ab_11_9_port, b => n976, outb => n975
);
U891 : nor2 port map( a => mult_125_G3_ab_12_9_port, b => n978, outb => n977
);
U892 : nor2 port map( a => mult_125_G3_ab_13_9_port, b => n980, outb => n979
);
U893 : nor2 port map( a => mult_125_G3_ab_14_9_port, b => n982, outb => n981
);
U894 : nand2 port map( a => n984, b => n985, outb => n983);
U895 : nand2 port map( a => n987, b => n988, outb => n986);
U896 : nor2 port map( a => mult_125_G3_ab_3_8_port, b => n990, outb => n989)
;
U897 : nor2 port map( a => mult_125_G3_ab_4_8_port, b => n992, outb => n991)
;
U898 : nor2 port map( a => mult_125_G3_ab_5_8_port, b => n994, outb => n993)
;
U899 : nor2 port map( a => mult_125_G3_ab_6_8_port, b => n996, outb => n995)
;
U900 : nor2 port map( a => mult_125_G3_ab_7_8_port, b => n998, outb => n997)
;
U901 : nor2 port map( a => mult_125_G3_ab_8_8_port, b => n1000, outb => n999
);
U902 : nor2 port map( a => mult_125_G3_ab_9_8_port, b => n1002, outb =>
n1001);
U903 : nor2 port map( a => mult_125_G3_ab_10_8_port, b => n1004, outb =>
n1003);
U904 : nor2 port map( a => mult_125_G3_ab_11_8_port, b => n1006, outb =>
n1005);
U905 : nor2 port map( a => mult_125_G3_ab_12_8_port, b => n1008, outb =>
n1007);
U906 : nor2 port map( a => mult_125_G3_ab_13_8_port, b => n1010, outb =>
n1009);
U907 : nor2 port map( a => mult_125_G3_ab_14_8_port, b => n1012, outb =>
n1011);
U908 : nor2 port map( a => mult_125_G3_ab_15_8_port, b => n1014, outb =>
n1013);
U909 : nand2 port map( a => n1016, b => n1017, outb => n1015);
U910 : nand2 port map( a => n1019, b => n1020, outb => n1018);
U911 : nor2 port map( a => mult_125_G3_ab_4_7_port, b => n1022, outb =>
n1021);
U912 : nor2 port map( a => mult_125_G3_ab_5_7_port, b => n1024, outb =>
n1023);
U913 : nor2 port map( a => mult_125_G3_ab_6_7_port, b => n1026, outb =>
n1025);
U914 : nor2 port map( a => mult_125_G3_ab_7_7_port, b => n1028, outb =>
n1027);
U915 : nor2 port map( a => mult_125_G3_ab_8_7_port, b => n1030, outb =>
n1029);
U916 : nor2 port map( a => mult_125_G3_ab_9_7_port, b => n1032, outb =>
n1031);
U917 : nor2 port map( a => mult_125_G3_ab_10_7_port, b => n1034, outb =>
n1033);
U918 : nor2 port map( a => mult_125_G3_ab_11_7_port, b => n1036, outb =>
n1035);
U919 : nor2 port map( a => mult_125_G3_ab_12_7_port, b => n1038, outb =>
n1037);
U920 : nor2 port map( a => mult_125_G3_ab_13_7_port, b => n1040, outb =>
n1039);
U921 : nor2 port map( a => mult_125_G3_ab_14_7_port, b => n1042, outb =>
n1041);
U922 : nand2 port map( a => n1044, b => n1045, outb => n1043);
U923 : nand2 port map( a => n1047, b => n1048, outb => n1046);
U924 : nor2 port map( a => mult_125_G3_ab_3_6_port, b => n1050, outb =>
n1049);
U925 : nor2 port map( a => mult_125_G3_ab_4_6_port, b => n1052, outb =>
n1051);
U926 : nand2 port map( a => n1054, b => n1055, outb => n1053);
U927 : nor2 port map( a => mult_125_G3_ab_6_6_port, b => n1057, outb =>
n1056);
U928 : nor2 port map( a => mult_125_G3_ab_7_6_port, b => n1059, outb =>
n1058);
U929 : nor2 port map( a => mult_125_G3_ab_8_6_port, b => n1061, outb =>
n1060);
U930 : nand2 port map( a => n1063, b => n1064, outb => n1062);
U931 : nor2 port map( a => mult_125_G3_ab_10_6_port, b => n1066, outb =>
n1065);
U932 : nor2 port map( a => mult_125_G3_ab_11_6_port, b => n1068, outb =>
n1067);
U933 : nor2 port map( a => mult_125_G3_ab_12_6_port, b => n1070, outb =>
n1069);
U934 : nor2 port map( a => mult_125_G3_ab_13_6_port, b => n1072, outb =>
n1071);
U935 : nor2 port map( a => mult_125_G3_ab_14_6_port, b => n1074, outb =>
n1073);
U936 : nor2 port map( a => mult_125_G3_ab_15_6_port, b => n1076, outb =>
n1075);
U937 : nand2 port map( a => n1078, b => n1079, outb => n1077);
U938 : nand2 port map( a => n1081, b => n1082, outb => n1080);
U939 : nor2 port map( a => mult_125_G3_ab_4_5_port, b => n1084, outb =>
n1083);
U940 : nor2 port map( a => mult_125_G3_ab_5_5_port, b => n1086, outb =>
n1085);
U941 : nand2 port map( a => n1088, b => n1089, outb => n1087);
U942 : nor2 port map( a => mult_125_G3_ab_7_5_port, b => n1091, outb =>
n1090);
U943 : nor2 port map( a => mult_125_G3_ab_8_5_port, b => n1093, outb =>
n1092);
U944 : nor2 port map( a => mult_125_G3_ab_9_5_port, b => n1095, outb =>
n1094);
U945 : nor2 port map( a => mult_125_G3_ab_10_5_port, b => n1097, outb =>
n1096);
U946 : nor2 port map( a => mult_125_G3_ab_11_5_port, b => n1099, outb =>
n1098);
U947 : nor2 port map( a => mult_125_G3_ab_12_5_port, b => n1101, outb =>
n1100);
U948 : nor2 port map( a => mult_125_G3_ab_13_5_port, b => n1103, outb =>
n1102);
U949 : nor2 port map( a => mult_125_G3_ab_14_5_port, b => n1105, outb =>
n1104);
U950 : nand2 port map( a => n1107, b => n1108, outb => n1106);
U951 : nand2 port map( a => n1110, b => n1111, outb => n1109);
U952 : nor2 port map( a => mult_125_G3_ab_3_4_port, b => n1113, outb =>
n1112);
U953 : nor2 port map( a => mult_125_G3_ab_4_4_port, b => n1115, outb =>
n1114);
U954 : nand2 port map( a => n1117, b => n1118, outb => n1116);
U955 : nor2 port map( a => mult_125_G3_ab_6_4_port, b => n1120, outb =>
n1119);
U956 : nand2 port map( a => n1122, b => n1123, outb => n1121);
U957 : nor2 port map( a => mult_125_G3_ab_8_4_port, b => n1125, outb =>
n1124);
U958 : nor2 port map( a => mult_125_G3_ab_9_4_port, b => n1127, outb =>
n1126);
U959 : nor2 port map( a => mult_125_G3_ab_10_4_port, b => n1129, outb =>
n1128);
U960 : nand2 port map( a => n1131, b => n1132, outb => n1130);
U961 : nor2 port map( a => mult_125_G3_ab_12_4_port, b => n1134, outb =>
n1133);
U962 : nor2 port map( a => mult_125_G3_ab_13_4_port, b => n1136, outb =>
n1135);
U963 : nor2 port map( a => mult_125_G3_ab_14_4_port, b => n1138, outb =>
n1137);
U964 : nand2 port map( a => n1140, b => n1141, outb => n1139);
U965 : nand2 port map( a => n1143, b => n1144, outb => n1142);
U966 : nand2 port map( a => n1146, b => n1147, outb => n1145);
U967 : nor2 port map( a => mult_125_G3_ab_4_3_port, b => n1149, outb =>
n1148);
U968 : nor2 port map( a => mult_125_G3_ab_5_3_port, b => n1151, outb =>
n1150);
U969 : nor2 port map( a => mult_125_G3_ab_6_3_port, b => n1153, outb =>
n1152);
U970 : nor2 port map( a => mult_125_G3_ab_7_3_port, b => n1155, outb =>
n1154);
U971 : nor2 port map( a => mult_125_G3_ab_8_3_port, b => n1157, outb =>
n1156);
U972 : nor2 port map( a => mult_125_G3_ab_9_3_port, b => n1159, outb =>
n1158);
U973 : nor2 port map( a => mult_125_G3_ab_10_3_port, b => n1161, outb =>
n1160);
U974 : nor2 port map( a => mult_125_G3_ab_11_3_port, b => n1163, outb =>
n1162);
U975 : nor2 port map( a => mult_125_G3_ab_12_3_port, b => n1165, outb =>
n1164);
U976 : nor2 port map( a => mult_125_G3_ab_13_3_port, b => n1167, outb =>
n1166);
U977 : nor2 port map( a => mult_125_G3_ab_14_3_port, b => n1169, outb =>
n1168);
U978 : nor2 port map( a => mult_125_G3_ab_15_3_port, b => n1171, outb =>
n1170);
U979 : nand2 port map( a => n1173, b => n1174, outb => n1172);
U980 : nor2 port map( a => mult_125_G3_ab_3_2_port, b => n1176, outb =>
n1175);
U981 : nor2 port map( a => mult_125_G3_ab_4_2_port, b => n1178, outb =>
n1177);
U982 : nor2 port map( a => mult_125_G3_ab_5_2_port, b => n1180, outb =>
n1179);
U983 : nor2 port map( a => mult_125_G3_ab_6_2_port, b => n1182, outb =>
n1181);
U984 : nand2 port map( a => n1184, b => n1185, outb => n1183);
U985 : nor2 port map( a => mult_125_G3_ab_8_2_port, b => n1187, outb =>
n1186);
U986 : nor2 port map( a => mult_125_G3_ab_9_2_port, b => n1189, outb =>
n1188);
U987 : nor2 port map( a => mult_125_G3_ab_10_2_port, b => n1191, outb =>
n1190);
U988 : nor2 port map( a => mult_125_G3_ab_11_2_port, b => n1193, outb =>
n1192);
U989 : nor2 port map( a => mult_125_G3_ab_12_2_port, b => n1195, outb =>
n1194);
U990 : nor2 port map( a => mult_125_G3_ab_13_2_port, b => n1197, outb =>
n1196);
U991 : nor2 port map( a => mult_125_G3_ab_14_2_port, b => n1199, outb =>
n1198);
U992 : nor2 port map( a => mult_125_G3_ab_15_2_port, b => n1201, outb =>
n1200);
U993 : nand2 port map( a => n1203, b => n1204, outb => n1202);
U994 : nor2 port map( a => mult_125_G3_ab_3_1_port, b => n1206, outb =>
n1205);
U995 : nor2 port map( a => mult_125_G3_ab_4_1_port, b => n1208, outb =>
n1207);
U996 : nor2 port map( a => mult_125_G3_ab_5_1_port, b => n1210, outb =>
n1209);
U997 : nor2 port map( a => mult_125_G3_ab_6_1_port, b => n1212, outb =>
n1211);
U998 : nor2 port map( a => mult_125_G3_ab_7_1_port, b => n1214, outb =>
n1213);
U999 : nor2 port map( a => mult_125_G3_ab_8_1_port, b => n1216, outb =>
n1215);
U1000 : nor2 port map( a => mult_125_G3_ab_9_1_port, b => n1218, outb =>
n1217);
U1001 : nor2 port map( a => mult_125_G3_ab_10_1_port, b => n1220, outb =>
n1219);
U1002 : nor2 port map( a => mult_125_G3_ab_11_1_port, b => n1222, outb =>
n1221);
U1003 : nor2 port map( a => mult_125_G3_ab_12_1_port, b => n1224, outb =>
n1223);
U1004 : nor2 port map( a => mult_125_G3_ab_13_1_port, b => n1226, outb =>
n1225);
U1005 : nor2 port map( a => mult_125_G3_ab_14_1_port, b => n1228, outb =>
n1227);
U1006 : nor2 port map( a => mult_125_G3_ab_15_1_port, b => n1230, outb =>
n1229);
U1007 : nor2 port map( a => mult_125_G3_ab_2_0_port, b => n1232, outb =>
n1231);
U1008 : nor2 port map( a => mult_125_G3_ab_3_0_port, b => n1234, outb =>
n1233);
U1009 : nor2 port map( a => mult_125_G3_ab_4_0_port, b => n1236, outb =>
n1235);
U1010 : nor2 port map( a => mult_125_G3_ab_5_0_port, b => n1238, outb =>
n1237);
U1011 : nor2 port map( a => mult_125_G3_ab_6_0_port, b => n1240, outb =>
n1239);
U1012 : nor2 port map( a => mult_125_G3_ab_7_0_port, b => n1242, outb =>
n1241);
U1013 : nor2 port map( a => mult_125_G3_ab_8_0_port, b => n1244, outb =>
n1243);
U1014 : nor2 port map( a => mult_125_G3_ab_9_0_port, b => n1246, outb =>
n1245);
U1015 : nor2 port map( a => mult_125_G3_ab_10_0_port, b => n1248, outb =>
n1247);
U1016 : nor2 port map( a => mult_125_G3_ab_11_0_port, b => n1250, outb =>
n1249);
U1017 : nor2 port map( a => mult_125_G3_ab_12_0_port, b => n1252, outb =>
n1251);
U1018 : nor2 port map( a => mult_125_G3_ab_13_0_port, b => n1254, outb =>
n1253);
U1019 : nor2 port map( a => mult_125_G3_ab_14_0_port, b => n1256, outb =>
n1255);
U1020 : nor2 port map( a => mult_125_G3_ab_15_0_port, b => n1258, outb =>
n1257);
U1021 : nor2 port map( a => mult_125_G3_ZB, b => mult_125_G3_ZA, outb =>
n382);
U1022 : nand2 port map( a => mult_125_G3_QB, b => mult_125_G3_ab_15_15_port,
outb => n1259);
U1023 : nor2 port map( a => mult_125_G2_ab_1_15_port, b =>
mult_125_G2_ab_2_14_port, outb => n1260);
U1024 : nor2 port map( a => mult_125_G2_ab_2_15_port, b =>
mult_125_G2_ab_3_14_port, outb => n1261);
U1025 : nor2 port map( a => mult_125_G2_ab_3_15_port, b =>
mult_125_G2_ab_4_14_port, outb => n1262);
U1026 : nor2 port map( a => mult_125_G2_ab_4_15_port, b =>
mult_125_G2_ab_5_14_port, outb => n1263);
U1027 : nor2 port map( a => mult_125_G2_ab_5_15_port, b =>
mult_125_G2_ab_6_14_port, outb => n1264);
U1028 : nor2 port map( a => mult_125_G2_ab_6_15_port, b =>
mult_125_G2_ab_7_14_port, outb => n1265);
U1029 : nor2 port map( a => mult_125_G2_ab_7_15_port, b =>
mult_125_G2_ab_8_14_port, outb => n1266);
U1030 : nor2 port map( a => mult_125_G2_ab_8_15_port, b =>
mult_125_G2_ab_9_14_port, outb => n1267);
U1031 : nor2 port map( a => mult_125_G2_ab_9_15_port, b =>
mult_125_G2_ab_10_14_port, outb => n1268);
U1032 : nor2 port map( a => mult_125_G2_ab_10_15_port, b =>
mult_125_G2_ab_11_14_port, outb => n1269);
U1033 : nor2 port map( a => mult_125_G2_ab_11_15_port, b =>
mult_125_G2_ab_12_14_port, outb => n1270);
U1034 : nor2 port map( a => mult_125_G2_ab_12_15_port, b =>
mult_125_G2_ab_13_14_port, outb => n1271);
U1035 : nor2 port map( a => mult_125_G2_ab_13_15_port, b =>
mult_125_G2_ab_14_14_port, outb => n1272);
U1036 : nor2 port map( a => mult_125_G2_ab_14_15_port, b =>
mult_125_G2_ab_15_14_port, outb => n1273);
U1037 : nand2 port map( a => n1275, b => n1276, outb => n1274);
U1038 : nand2 port map( a => n1278, b => n1279, outb => n1277);
U1039 : nor2 port map( a => mult_125_G2_ab_4_13_port, b => n1281, outb =>
n1280);
U1040 : nor2 port map( a => mult_125_G2_ab_5_13_port, b => n1283, outb =>
n1282);
U1041 : nor2 port map( a => mult_125_G2_ab_6_13_port, b => n1285, outb =>
n1284);
U1042 : nor2 port map( a => mult_125_G2_ab_7_13_port, b => n1287, outb =>
n1286);
U1043 : nor2 port map( a => mult_125_G2_ab_8_13_port, b => n1289, outb =>
n1288);
U1044 : nor2 port map( a => mult_125_G2_ab_9_13_port, b => n1291, outb =>
n1290);
U1045 : nor2 port map( a => mult_125_G2_ab_10_13_port, b => n1293, outb =>
n1292);
U1046 : nor2 port map( a => mult_125_G2_ab_11_13_port, b => n1295, outb =>
n1294);
U1047 : nor2 port map( a => mult_125_G2_ab_12_13_port, b => n1297, outb =>
n1296);
U1048 : nor2 port map( a => mult_125_G2_ab_13_13_port, b => n1299, outb =>
n1298);
U1049 : nor2 port map( a => mult_125_G2_ab_14_13_port, b => n1301, outb =>
n1300);
U1050 : nor2 port map( a => mult_125_G2_ab_15_13_port, b => n1303, outb =>
n1302);
U1051 : nand2 port map( a => n1305, b => n1306, outb => n1304);
U1052 : nor2 port map( a => mult_125_G2_ab_3_12_port, b => n1308, outb =>
n1307);
U1053 : nor2 port map( a => mult_125_G2_ab_4_12_port, b => n1310, outb =>
n1309);
U1054 : nor2 port map( a => mult_125_G2_ab_5_12_port, b => n1312, outb =>
n1311);
U1055 : nor2 port map( a => mult_125_G2_ab_6_12_port, b => n1314, outb =>
n1313);
U1056 : nor2 port map( a => mult_125_G2_ab_7_12_port, b => n1316, outb =>
n1315);
U1057 : nor2 port map( a => mult_125_G2_ab_8_12_port, b => n1318, outb =>
n1317);
U1058 : nor2 port map( a => mult_125_G2_ab_9_12_port, b => n1320, outb =>
n1319);
U1059 : nor2 port map( a => mult_125_G2_ab_10_12_port, b => n1322, outb =>
n1321);
U1060 : nor2 port map( a => mult_125_G2_ab_11_12_port, b => n1324, outb =>
n1323);
U1061 : nor2 port map( a => mult_125_G2_ab_12_12_port, b => n1326, outb =>
n1325);
U1062 : nor2 port map( a => mult_125_G2_ab_13_12_port, b => n1328, outb =>
n1327);
U1063 : nor2 port map( a => mult_125_G2_ab_14_12_port, b => n1330, outb =>
n1329);
U1064 : nor2 port map( a => mult_125_G2_ab_15_12_port, b => n1332, outb =>
n1331);
U1065 : nand2 port map( a => n1334, b => n1335, outb => n1333);
U1066 : nand2 port map( a => n1337, b => n1338, outb => n1336);
U1067 : nor2 port map( a => mult_125_G2_ab_4_11_port, b => n1340, outb =>
n1339);
U1068 : nor2 port map( a => mult_125_G2_ab_5_11_port, b => n1342, outb =>
n1341);
U1069 : nor2 port map( a => mult_125_G2_ab_6_11_port, b => n1344, outb =>
n1343);
U1070 : nor2 port map( a => mult_125_G2_ab_7_11_port, b => n1346, outb =>
n1345);
U1071 : nor2 port map( a => mult_125_G2_ab_8_11_port, b => n1348, outb =>
n1347);
U1072 : nor2 port map( a => mult_125_G2_ab_9_11_port, b => n1350, outb =>
n1349);
U1073 : nor2 port map( a => mult_125_G2_ab_10_11_port, b => n1352, outb =>
n1351);
U1074 : nor2 port map( a => mult_125_G2_ab_11_11_port, b => n1354, outb =>
n1353);
U1075 : nor2 port map( a => mult_125_G2_ab_12_11_port, b => n1356, outb =>
n1355);
U1076 : nor2 port map( a => mult_125_G2_ab_13_11_port, b => n1358, outb =>
n1357);
U1077 : nor2 port map( a => mult_125_G2_ab_14_11_port, b => n1360, outb =>
n1359);
U1078 : nand2 port map( a => n1362, b => n1363, outb => n1361);
U1079 : nand2 port map( a => n1365, b => n1366, outb => n1364);
U1080 : nor2 port map( a => mult_125_G2_ab_3_10_port, b => n1368, outb =>
n1367);
U1081 : nor2 port map( a => mult_125_G2_ab_4_10_port, b => n1370, outb =>
n1369);
U1082 : nand2 port map( a => n1372, b => n1373, outb => n1371);
U1083 : nor2 port map( a => mult_125_G2_ab_6_10_port, b => n1375, outb =>
n1374);
U1084 : nor2 port map( a => mult_125_G2_ab_7_10_port, b => n1377, outb =>
n1376);
U1085 : nor2 port map( a => mult_125_G2_ab_8_10_port, b => n1379, outb =>
n1378);
U1086 : nor2 port map( a => mult_125_G2_ab_9_10_port, b => n1381, outb =>
n1380);
U1087 : nor2 port map( a => mult_125_G2_ab_10_10_port, b => n1383, outb =>
n1382);
U1088 : nor2 port map( a => mult_125_G2_ab_11_10_port, b => n1385, outb =>
n1384);
U1089 : nor2 port map( a => mult_125_G2_ab_12_10_port, b => n1387, outb =>
n1386);
U1090 : nor2 port map( a => mult_125_G2_ab_13_10_port, b => n1389, outb =>
n1388);
U1091 : nor2 port map( a => mult_125_G2_ab_14_10_port, b => n1391, outb =>
n1390);
U1092 : nor2 port map( a => mult_125_G2_ab_15_10_port, b => n1393, outb =>
n1392);
U1093 : nand2 port map( a => n1395, b => n1396, outb => n1394);
U1094 : nor2 port map( a => mult_125_G2_ab_3_9_port, b => n1398, outb =>
n1397);
U1095 : nor2 port map( a => mult_125_G2_ab_4_9_port, b => n1400, outb =>
n1399);
U1096 : nor2 port map( a => mult_125_G2_ab_5_9_port, b => n1402, outb =>
n1401);
U1097 : nor2 port map( a => mult_125_G2_ab_6_9_port, b => n1404, outb =>
n1403);
U1098 : nor2 port map( a => mult_125_G2_ab_7_9_port, b => n1406, outb =>
n1405);
U1099 : nor2 port map( a => mult_125_G2_ab_8_9_port, b => n1408, outb =>
n1407);
U1100 : nor2 port map( a => mult_125_G2_ab_9_9_port, b => n1410, outb =>
n1409);
U1101 : nor2 port map( a => mult_125_G2_ab_10_9_port, b => n1412, outb =>
n1411);
U1102 : nor2 port map( a => mult_125_G2_ab_11_9_port, b => n1414, outb =>
n1413);
U1103 : nor2 port map( a => mult_125_G2_ab_12_9_port, b => n1416, outb =>
n1415);
U1104 : nor2 port map( a => mult_125_G2_ab_13_9_port, b => n1418, outb =>
n1417);
U1105 : nor2 port map( a => mult_125_G2_ab_14_9_port, b => n1420, outb =>
n1419);
U1106 : nand2 port map( a => n1422, b => n1423, outb => n1421);
U1107 : nand2 port map( a => n1425, b => n1426, outb => n1424);
U1108 : nor2 port map( a => mult_125_G2_ab_3_8_port, b => n1428, outb =>
n1427);
U1109 : nor2 port map( a => mult_125_G2_ab_4_8_port, b => n1430, outb =>
n1429);
U1110 : nor2 port map( a => mult_125_G2_ab_5_8_port, b => n1432, outb =>
n1431);
U1111 : nor2 port map( a => mult_125_G2_ab_6_8_port, b => n1434, outb =>
n1433);
U1112 : nor2 port map( a => mult_125_G2_ab_7_8_port, b => n1436, outb =>
n1435);
U1113 : nor2 port map( a => mult_125_G2_ab_8_8_port, b => n1438, outb =>
n1437);
U1114 : nor2 port map( a => mult_125_G2_ab_9_8_port, b => n1440, outb =>
n1439);
U1115 : nor2 port map( a => mult_125_G2_ab_10_8_port, b => n1442, outb =>
n1441);
U1116 : nor2 port map( a => mult_125_G2_ab_11_8_port, b => n1444, outb =>
n1443);
U1117 : nor2 port map( a => mult_125_G2_ab_12_8_port, b => n1446, outb =>
n1445);
U1118 : nor2 port map( a => mult_125_G2_ab_13_8_port, b => n1448, outb =>
n1447);
U1119 : nor2 port map( a => mult_125_G2_ab_14_8_port, b => n1450, outb =>
n1449);
U1120 : nor2 port map( a => mult_125_G2_ab_15_8_port, b => n1452, outb =>
n1451);
U1121 : nand2 port map( a => n1454, b => n1455, outb => n1453);
U1122 : nand2 port map( a => n1457, b => n1458, outb => n1456);
U1123 : nor2 port map( a => mult_125_G2_ab_4_7_port, b => n1460, outb =>
n1459);
U1124 : nor2 port map( a => mult_125_G2_ab_5_7_port, b => n1462, outb =>
n1461);
U1125 : nor2 port map( a => mult_125_G2_ab_6_7_port, b => n1464, outb =>
n1463);
U1126 : nor2 port map( a => mult_125_G2_ab_7_7_port, b => n1466, outb =>
n1465);
U1127 : nor2 port map( a => mult_125_G2_ab_8_7_port, b => n1468, outb =>
n1467);
U1128 : nor2 port map( a => mult_125_G2_ab_9_7_port, b => n1470, outb =>
n1469);
U1129 : nor2 port map( a => mult_125_G2_ab_10_7_port, b => n1472, outb =>
n1471);
U1130 : nor2 port map( a => mult_125_G2_ab_11_7_port, b => n1474, outb =>
n1473);
U1131 : nor2 port map( a => mult_125_G2_ab_12_7_port, b => n1476, outb =>
n1475);
U1132 : nor2 port map( a => mult_125_G2_ab_13_7_port, b => n1478, outb =>
n1477);
U1133 : nor2 port map( a => mult_125_G2_ab_14_7_port, b => n1480, outb =>
n1479);
U1134 : nand2 port map( a => n1482, b => n1483, outb => n1481);
U1135 : nand2 port map( a => n1485, b => n1486, outb => n1484);
U1136 : nor2 port map( a => mult_125_G2_ab_3_6_port, b => n1488, outb =>
n1487);
U1137 : nor2 port map( a => mult_125_G2_ab_4_6_port, b => n1490, outb =>
n1489);
U1138 : nand2 port map( a => n1492, b => n1493, outb => n1491);
U1139 : nor2 port map( a => mult_125_G2_ab_6_6_port, b => n1495, outb =>
n1494);
U1140 : nor2 port map( a => mult_125_G2_ab_7_6_port, b => n1497, outb =>
n1496);
U1141 : nor2 port map( a => mult_125_G2_ab_8_6_port, b => n1499, outb =>
n1498);
U1142 : nand2 port map( a => n1501, b => n1502, outb => n1500);
U1143 : nor2 port map( a => mult_125_G2_ab_10_6_port, b => n1504, outb =>
n1503);
U1144 : nor2 port map( a => mult_125_G2_ab_11_6_port, b => n1506, outb =>
n1505);
U1145 : nor2 port map( a => mult_125_G2_ab_12_6_port, b => n1508, outb =>
n1507);
U1146 : nor2 port map( a => mult_125_G2_ab_13_6_port, b => n1510, outb =>
n1509);
U1147 : nor2 port map( a => mult_125_G2_ab_14_6_port, b => n1512, outb =>
n1511);
U1148 : nor2 port map( a => mult_125_G2_ab_15_6_port, b => n1514, outb =>
n1513);
U1149 : nand2 port map( a => n1516, b => n1517, outb => n1515);
U1150 : nand2 port map( a => n1519, b => n1520, outb => n1518);
U1151 : nor2 port map( a => mult_125_G2_ab_4_5_port, b => n1522, outb =>
n1521);
U1152 : nor2 port map( a => mult_125_G2_ab_5_5_port, b => n1524, outb =>
n1523);
U1153 : nand2 port map( a => n1526, b => n1527, outb => n1525);
U1154 : nor2 port map( a => mult_125_G2_ab_7_5_port, b => n1529, outb =>
n1528);
U1155 : nor2 port map( a => mult_125_G2_ab_8_5_port, b => n1531, outb =>
n1530);
U1156 : nor2 port map( a => mult_125_G2_ab_9_5_port, b => n1533, outb =>
n1532);
U1157 : nor2 port map( a => mult_125_G2_ab_10_5_port, b => n1535, outb =>
n1534);
U1158 : nor2 port map( a => mult_125_G2_ab_11_5_port, b => n1537, outb =>
n1536);
U1159 : nor2 port map( a => mult_125_G2_ab_12_5_port, b => n1539, outb =>
n1538);
U1160 : nor2 port map( a => mult_125_G2_ab_13_5_port, b => n1541, outb =>
n1540);
U1161 : nor2 port map( a => mult_125_G2_ab_14_5_port, b => n1543, outb =>
n1542);
U1162 : nand2 port map( a => n1545, b => n1546, outb => n1544);
U1163 : nand2 port map( a => n1548, b => n1549, outb => n1547);
U1164 : nor2 port map( a => mult_125_G2_ab_3_4_port, b => n1551, outb =>
n1550);
U1165 : nor2 port map( a => mult_125_G2_ab_4_4_port, b => n1553, outb =>
n1552);
U1166 : nand2 port map( a => n1555, b => n1556, outb => n1554);
U1167 : nor2 port map( a => mult_125_G2_ab_6_4_port, b => n1558, outb =>
n1557);
U1168 : nand2 port map( a => n1560, b => n1561, outb => n1559);
U1169 : nor2 port map( a => mult_125_G2_ab_8_4_port, b => n1563, outb =>
n1562);
U1170 : nor2 port map( a => mult_125_G2_ab_9_4_port, b => n1565, outb =>
n1564);
U1171 : nor2 port map( a => mult_125_G2_ab_10_4_port, b => n1567, outb =>
n1566);
U1172 : nand2 port map( a => n1569, b => n1570, outb => n1568);
U1173 : nor2 port map( a => mult_125_G2_ab_12_4_port, b => n1572, outb =>
n1571);
U1174 : nor2 port map( a => mult_125_G2_ab_13_4_port, b => n1574, outb =>
n1573);
U1175 : nor2 port map( a => mult_125_G2_ab_14_4_port, b => n1576, outb =>
n1575);
U1176 : nand2 port map( a => n1578, b => n1579, outb => n1577);
U1177 : nand2 port map( a => n1581, b => n1582, outb => n1580);
U1178 : nand2 port map( a => n1584, b => n1585, outb => n1583);
U1179 : nor2 port map( a => mult_125_G2_ab_4_3_port, b => n1587, outb =>
n1586);
U1180 : nor2 port map( a => mult_125_G2_ab_5_3_port, b => n1589, outb =>
n1588);
U1181 : nor2 port map( a => mult_125_G2_ab_6_3_port, b => n1591, outb =>
n1590);
U1182 : nor2 port map( a => mult_125_G2_ab_7_3_port, b => n1593, outb =>
n1592);
U1183 : nor2 port map( a => mult_125_G2_ab_8_3_port, b => n1595, outb =>
n1594);
U1184 : nor2 port map( a => mult_125_G2_ab_9_3_port, b => n1597, outb =>
n1596);
U1185 : nor2 port map( a => mult_125_G2_ab_10_3_port, b => n1599, outb =>
n1598);
U1186 : nor2 port map( a => mult_125_G2_ab_11_3_port, b => n1601, outb =>
n1600);
U1187 : nor2 port map( a => mult_125_G2_ab_12_3_port, b => n1603, outb =>
n1602);
U1188 : nor2 port map( a => mult_125_G2_ab_13_3_port, b => n1605, outb =>
n1604);
U1189 : nor2 port map( a => mult_125_G2_ab_14_3_port, b => n1607, outb =>
n1606);
U1190 : nor2 port map( a => mult_125_G2_ab_15_3_port, b => n1609, outb =>
n1608);
U1191 : nand2 port map( a => n1611, b => n1612, outb => n1610);
U1192 : nor2 port map( a => mult_125_G2_ab_3_2_port, b => n1614, outb =>
n1613);
U1193 : nor2 port map( a => mult_125_G2_ab_4_2_port, b => n1616, outb =>
n1615);
U1194 : nor2 port map( a => mult_125_G2_ab_5_2_port, b => n1618, outb =>
n1617);
U1195 : nor2 port map( a => mult_125_G2_ab_6_2_port, b => n1620, outb =>
n1619);
U1196 : nand2 port map( a => n1622, b => n1623, outb => n1621);
U1197 : nor2 port map( a => mult_125_G2_ab_8_2_port, b => n1625, outb =>
n1624);
U1198 : nor2 port map( a => mult_125_G2_ab_9_2_port, b => n1627, outb =>
n1626);
U1199 : nor2 port map( a => mult_125_G2_ab_10_2_port, b => n1629, outb =>
n1628);
U1200 : nor2 port map( a => mult_125_G2_ab_11_2_port, b => n1631, outb =>
n1630);
U1201 : nor2 port map( a => mult_125_G2_ab_12_2_port, b => n1633, outb =>
n1632);
U1202 : nor2 port map( a => mult_125_G2_ab_13_2_port, b => n1635, outb =>
n1634);
U1203 : nor2 port map( a => mult_125_G2_ab_14_2_port, b => n1637, outb =>
n1636);
U1204 : nor2 port map( a => mult_125_G2_ab_15_2_port, b => n1639, outb =>
n1638);
U1205 : nand2 port map( a => n1641, b => n1642, outb => n1640);
U1206 : nor2 port map( a => mult_125_G2_ab_3_1_port, b => n1644, outb =>
n1643);
U1207 : nor2 port map( a => mult_125_G2_ab_4_1_port, b => n1646, outb =>
n1645);
U1208 : nor2 port map( a => mult_125_G2_ab_5_1_port, b => n1648, outb =>
n1647);
U1209 : nor2 port map( a => mult_125_G2_ab_6_1_port, b => n1650, outb =>
n1649);
U1210 : nor2 port map( a => mult_125_G2_ab_7_1_port, b => n1652, outb =>
n1651);
U1211 : nor2 port map( a => mult_125_G2_ab_8_1_port, b => n1654, outb =>
n1653);
U1212 : nor2 port map( a => mult_125_G2_ab_9_1_port, b => n1656, outb =>
n1655);
U1213 : nor2 port map( a => mult_125_G2_ab_10_1_port, b => n1658, outb =>
n1657);
U1214 : nor2 port map( a => mult_125_G2_ab_11_1_port, b => n1660, outb =>
n1659);
U1215 : nor2 port map( a => mult_125_G2_ab_12_1_port, b => n1662, outb =>
n1661);
U1216 : nor2 port map( a => mult_125_G2_ab_13_1_port, b => n1664, outb =>
n1663);
U1217 : nor2 port map( a => mult_125_G2_ab_14_1_port, b => n1666, outb =>
n1665);
U1218 : nor2 port map( a => mult_125_G2_ab_15_1_port, b => n1668, outb =>
n1667);
U1219 : nor2 port map( a => mult_125_G2_ab_2_0_port, b => n1670, outb =>
n1669);
U1220 : nor2 port map( a => mult_125_G2_ab_3_0_port, b => n1672, outb =>
n1671);
U1221 : nor2 port map( a => mult_125_G2_ab_4_0_port, b => n1674, outb =>
n1673);
U1222 : nor2 port map( a => mult_125_G2_ab_5_0_port, b => n1676, outb =>
n1675);
U1223 : nor2 port map( a => mult_125_G2_ab_6_0_port, b => n1678, outb =>
n1677);
U1224 : nor2 port map( a => mult_125_G2_ab_7_0_port, b => n1680, outb =>
n1679);
U1225 : nor2 port map( a => mult_125_G2_ab_8_0_port, b => n1682, outb =>
n1681);
U1226 : nor2 port map( a => mult_125_G2_ab_9_0_port, b => n1684, outb =>
n1683);
U1227 : nor2 port map( a => mult_125_G2_ab_10_0_port, b => n1686, outb =>
n1685);
U1228 : nor2 port map( a => mult_125_G2_ab_11_0_port, b => n1688, outb =>
n1687);
U1229 : nor2 port map( a => mult_125_G2_ab_12_0_port, b => n1690, outb =>
n1689);
U1230 : nor2 port map( a => mult_125_G2_ab_13_0_port, b => n1692, outb =>
n1691);
U1231 : nor2 port map( a => mult_125_G2_ab_14_0_port, b => n1694, outb =>
n1693);
U1232 : nor2 port map( a => mult_125_G2_ab_15_0_port, b => n1696, outb =>
n1695);
U1233 : nor2 port map( a => mult_125_G2_ZB, b => mult_125_G2_ZA, outb =>
n346);
U1234 : nand2 port map( a => mult_125_G2_QB, b => mult_125_G2_ab_15_15_port,
outb => n1697);
U1235 : nor2 port map( a => mult_125_ab_1_15_port, b =>
mult_125_ab_2_14_port, outb => n1698);
U1236 : nor2 port map( a => mult_125_ab_2_15_port, b =>
mult_125_ab_3_14_port, outb => n1699);
U1237 : nor2 port map( a => mult_125_ab_3_15_port, b =>
mult_125_ab_4_14_port, outb => n1700);
U1238 : nor2 port map( a => mult_125_ab_4_15_port, b =>
mult_125_ab_5_14_port, outb => n1701);
U1239 : nor2 port map( a => mult_125_ab_5_15_port, b =>
mult_125_ab_6_14_port, outb => n1702);
U1240 : nor2 port map( a => mult_125_ab_6_15_port, b =>
mult_125_ab_7_14_port, outb => n1703);
U1241 : nor2 port map( a => mult_125_ab_7_15_port, b =>
mult_125_ab_8_14_port, outb => n1704);
U1242 : nor2 port map( a => mult_125_ab_8_15_port, b =>
mult_125_ab_9_14_port, outb => n1705);
U1243 : nor2 port map( a => mult_125_ab_9_15_port, b =>
mult_125_ab_10_14_port, outb => n1706);
U1244 : nor2 port map( a => mult_125_ab_10_15_port, b =>
mult_125_ab_11_14_port, outb => n1707);
U1245 : nor2 port map( a => mult_125_ab_11_15_port, b =>
mult_125_ab_12_14_port, outb => n1708);
U1246 : nor2 port map( a => mult_125_ab_12_15_port, b =>
mult_125_ab_13_14_port, outb => n1709);
U1247 : nor2 port map( a => mult_125_ab_13_15_port, b =>
mult_125_ab_14_14_port, outb => n1710);
U1248 : nor2 port map( a => mult_125_ab_14_15_port, b =>
mult_125_ab_15_14_port, outb => n1711);
U1249 : nand2 port map( a => n1713, b => n1714, outb => n1712);
U1250 : nand2 port map( a => n1716, b => n1717, outb => n1715);
U1251 : nor2 port map( a => mult_125_ab_4_13_port, b => n1719, outb => n1718
);
U1252 : nor2 port map( a => mult_125_ab_5_13_port, b => n1721, outb => n1720
);
U1253 : nor2 port map( a => mult_125_ab_6_13_port, b => n1723, outb => n1722
);
U1254 : nor2 port map( a => mult_125_ab_7_13_port, b => n1725, outb => n1724
);
U1255 : nor2 port map( a => mult_125_ab_8_13_port, b => n1727, outb => n1726
);
U1256 : nor2 port map( a => mult_125_ab_9_13_port, b => n1729, outb => n1728
);
U1257 : nor2 port map( a => mult_125_ab_10_13_port, b => n1731, outb =>
n1730);
U1258 : nor2 port map( a => mult_125_ab_11_13_port, b => n1733, outb =>
n1732);
U1259 : nor2 port map( a => mult_125_ab_12_13_port, b => n1735, outb =>
n1734);
U1260 : nor2 port map( a => mult_125_ab_13_13_port, b => n1737, outb =>
n1736);
U1261 : nor2 port map( a => mult_125_ab_14_13_port, b => n1739, outb =>
n1738);
U1262 : nor2 port map( a => mult_125_ab_15_13_port, b => n1741, outb =>
n1740);
U1263 : nand2 port map( a => n1743, b => n1744, outb => n1742);
U1264 : nor2 port map( a => mult_125_ab_3_12_port, b => n1746, outb => n1745
);
U1265 : nor2 port map( a => mult_125_ab_4_12_port, b => n1748, outb => n1747
);
U1266 : nor2 port map( a => mult_125_ab_5_12_port, b => n1750, outb => n1749
);
U1267 : nor2 port map( a => mult_125_ab_6_12_port, b => n1752, outb => n1751
);
U1268 : nor2 port map( a => mult_125_ab_7_12_port, b => n1754, outb => n1753
);
U1269 : nor2 port map( a => mult_125_ab_8_12_port, b => n1756, outb => n1755
);
U1270 : nor2 port map( a => mult_125_ab_9_12_port, b => n1758, outb => n1757
);
U1271 : nor2 port map( a => mult_125_ab_10_12_port, b => n1760, outb =>
n1759);
U1272 : nor2 port map( a => mult_125_ab_11_12_port, b => n1762, outb =>
n1761);
U1273 : nor2 port map( a => mult_125_ab_12_12_port, b => n1764, outb =>
n1763);
U1274 : nor2 port map( a => mult_125_ab_13_12_port, b => n1766, outb =>
n1765);
U1275 : nor2 port map( a => mult_125_ab_14_12_port, b => n1768, outb =>
n1767);
U1276 : nor2 port map( a => mult_125_ab_15_12_port, b => n1770, outb =>
n1769);
U1277 : nand2 port map( a => n1772, b => n1773, outb => n1771);
U1278 : nand2 port map( a => n1775, b => n1776, outb => n1774);
U1279 : nor2 port map( a => mult_125_ab_4_11_port, b => n1778, outb => n1777
);
U1280 : nor2 port map( a => mult_125_ab_5_11_port, b => n1780, outb => n1779
);
U1281 : nor2 port map( a => mult_125_ab_6_11_port, b => n1782, outb => n1781
);
U1282 : nor2 port map( a => mult_125_ab_7_11_port, b => n1784, outb => n1783
);
U1283 : nor2 port map( a => mult_125_ab_8_11_port, b => n1786, outb => n1785
);
U1284 : nor2 port map( a => mult_125_ab_9_11_port, b => n1788, outb => n1787
);
U1285 : nor2 port map( a => mult_125_ab_10_11_port, b => n1790, outb =>
n1789);
U1286 : nor2 port map( a => mult_125_ab_11_11_port, b => n1792, outb =>
n1791);
U1287 : nor2 port map( a => mult_125_ab_12_11_port, b => n1794, outb =>
n1793);
U1288 : nor2 port map( a => mult_125_ab_13_11_port, b => n1796, outb =>
n1795);
U1289 : nor2 port map( a => mult_125_ab_14_11_port, b => n1798, outb =>
n1797);
U1290 : nand2 port map( a => n1800, b => n1801, outb => n1799);
U1291 : nand2 port map( a => n1803, b => n1804, outb => n1802);
U1292 : nor2 port map( a => mult_125_ab_3_10_port, b => n1806, outb => n1805
);
U1293 : nor2 port map( a => mult_125_ab_4_10_port, b => n1808, outb => n1807
);
U1294 : nand2 port map( a => n1810, b => n1811, outb => n1809);
U1295 : nor2 port map( a => mult_125_ab_6_10_port, b => n1813, outb => n1812
);
U1296 : nor2 port map( a => mult_125_ab_7_10_port, b => n1815, outb => n1814
);
U1297 : nor2 port map( a => mult_125_ab_8_10_port, b => n1817, outb => n1816
);
U1298 : nor2 port map( a => mult_125_ab_9_10_port, b => n1819, outb => n1818
);
U1299 : nor2 port map( a => mult_125_ab_10_10_port, b => n1821, outb =>
n1820);
U1300 : nor2 port map( a => mult_125_ab_11_10_port, b => n1823, outb =>
n1822);
U1301 : nor2 port map( a => mult_125_ab_12_10_port, b => n1825, outb =>
n1824);
U1302 : nor2 port map( a => mult_125_ab_13_10_port, b => n1827, outb =>
n1826);
U1303 : nor2 port map( a => mult_125_ab_14_10_port, b => n1829, outb =>
n1828);
U1304 : nor2 port map( a => mult_125_ab_15_10_port, b => n1831, outb =>
n1830);
U1305 : nand2 port map( a => n1833, b => n1834, outb => n1832);
U1306 : nor2 port map( a => mult_125_ab_3_9_port, b => n1836, outb => n1835)
;
U1307 : nor2 port map( a => mult_125_ab_4_9_port, b => n1838, outb => n1837)
;
U1308 : nor2 port map( a => mult_125_ab_5_9_port, b => n1840, outb => n1839)
;
U1309 : nor2 port map( a => mult_125_ab_6_9_port, b => n1842, outb => n1841)
;
U1310 : nor2 port map( a => mult_125_ab_7_9_port, b => n1844, outb => n1843)
;
U1311 : nor2 port map( a => mult_125_ab_8_9_port, b => n1846, outb => n1845)
;
U1312 : nor2 port map( a => mult_125_ab_9_9_port, b => n1848, outb => n1847)
;
U1313 : nor2 port map( a => mult_125_ab_10_9_port, b => n1850, outb => n1849
);
U1314 : nor2 port map( a => mult_125_ab_11_9_port, b => n1852, outb => n1851
);
U1315 : nor2 port map( a => mult_125_ab_12_9_port, b => n1854, outb => n1853
);
U1316 : nor2 port map( a => mult_125_ab_13_9_port, b => n1856, outb => n1855
);
U1317 : nor2 port map( a => mult_125_ab_14_9_port, b => n1858, outb => n1857
);
U1318 : nand2 port map( a => n1860, b => n1861, outb => n1859);
U1319 : nand2 port map( a => n1863, b => n1864, outb => n1862);
U1320 : nor2 port map( a => mult_125_ab_3_8_port, b => n1866, outb => n1865)
;
U1321 : nor2 port map( a => mult_125_ab_4_8_port, b => n1868, outb => n1867)
;
U1322 : nor2 port map( a => mult_125_ab_5_8_port, b => n1870, outb => n1869)
;
U1323 : nor2 port map( a => mult_125_ab_6_8_port, b => n1872, outb => n1871)
;
U1324 : nor2 port map( a => mult_125_ab_7_8_port, b => n1874, outb => n1873)
;
U1325 : nor2 port map( a => mult_125_ab_8_8_port, b => n1876, outb => n1875)
;
U1326 : nor2 port map( a => mult_125_ab_9_8_port, b => n1878, outb => n1877)
;
U1327 : nor2 port map( a => mult_125_ab_10_8_port, b => n1880, outb => n1879
);
U1328 : nor2 port map( a => mult_125_ab_11_8_port, b => n1882, outb => n1881
);
U1329 : nor2 port map( a => mult_125_ab_12_8_port, b => n1884, outb => n1883
);
U1330 : nor2 port map( a => mult_125_ab_13_8_port, b => n1886, outb => n1885
);
U1331 : nor2 port map( a => mult_125_ab_14_8_port, b => n1888, outb => n1887
);
U1332 : nor2 port map( a => mult_125_ab_15_8_port, b => n1890, outb => n1889
);
U1333 : nand2 port map( a => n1892, b => n1893, outb => n1891);
U1334 : nand2 port map( a => n1895, b => n1896, outb => n1894);
U1335 : nor2 port map( a => mult_125_ab_4_7_port, b => n1898, outb => n1897)
;
U1336 : nor2 port map( a => mult_125_ab_5_7_port, b => n1900, outb => n1899)
;
U1337 : nor2 port map( a => mult_125_ab_6_7_port, b => n1902, outb => n1901)
;
U1338 : nor2 port map( a => mult_125_ab_7_7_port, b => n1904, outb => n1903)
;
U1339 : nor2 port map( a => mult_125_ab_8_7_port, b => n1906, outb => n1905)
;
U1340 : nor2 port map( a => mult_125_ab_9_7_port, b => n1908, outb => n1907)
;
U1341 : nor2 port map( a => mult_125_ab_10_7_port, b => n1910, outb => n1909
);
U1342 : nor2 port map( a => mult_125_ab_11_7_port, b => n1912, outb => n1911
);
U1343 : nor2 port map( a => mult_125_ab_12_7_port, b => n1914, outb => n1913
);
U1344 : nor2 port map( a => mult_125_ab_13_7_port, b => n1916, outb => n1915
);
U1345 : nor2 port map( a => mult_125_ab_14_7_port, b => n1918, outb => n1917
);
U1346 : nand2 port map( a => n1920, b => n1921, outb => n1919);
U1347 : nand2 port map( a => n1923, b => n1924, outb => n1922);
U1348 : nor2 port map( a => mult_125_ab_3_6_port, b => n1926, outb => n1925)
;
U1349 : nor2 port map( a => mult_125_ab_4_6_port, b => n1928, outb => n1927)
;
U1350 : nand2 port map( a => n1930, b => n1931, outb => n1929);
U1351 : nor2 port map( a => mult_125_ab_6_6_port, b => n1933, outb => n1932)
;
U1352 : nor2 port map( a => mult_125_ab_7_6_port, b => n1935, outb => n1934)
;
U1353 : nor2 port map( a => mult_125_ab_8_6_port, b => n1937, outb => n1936)
;
U1354 : nand2 port map( a => n1939, b => n1940, outb => n1938);
U1355 : nor2 port map( a => mult_125_ab_10_6_port, b => n1942, outb => n1941
);
U1356 : nor2 port map( a => mult_125_ab_11_6_port, b => n1944, outb => n1943
);
U1357 : nor2 port map( a => mult_125_ab_12_6_port, b => n1946, outb => n1945
);
U1358 : nor2 port map( a => mult_125_ab_13_6_port, b => n1948, outb => n1947
);
U1359 : nor2 port map( a => mult_125_ab_14_6_port, b => n1950, outb => n1949
);
U1360 : nor2 port map( a => mult_125_ab_15_6_port, b => n1952, outb => n1951
);
U1361 : nand2 port map( a => n1954, b => n1955, outb => n1953);
U1362 : nand2 port map( a => n1957, b => n1958, outb => n1956);
U1363 : nor2 port map( a => mult_125_ab_4_5_port, b => n1960, outb => n1959)
;
U1364 : nor2 port map( a => mult_125_ab_5_5_port, b => n1962, outb => n1961)
;
U1365 : nand2 port map( a => n1964, b => n1965, outb => n1963);
U1366 : nor2 port map( a => mult_125_ab_7_5_port, b => n1967, outb => n1966)
;
U1367 : nor2 port map( a => mult_125_ab_8_5_port, b => n1969, outb => n1968)
;
U1368 : nor2 port map( a => mult_125_ab_9_5_port, b => n1971, outb => n1970)
;
U1369 : nor2 port map( a => mult_125_ab_10_5_port, b => n1973, outb => n1972
);
U1370 : nor2 port map( a => mult_125_ab_11_5_port, b => n1975, outb => n1974
);
U1371 : nor2 port map( a => mult_125_ab_12_5_port, b => n1977, outb => n1976
);
U1372 : nor2 port map( a => mult_125_ab_13_5_port, b => n1979, outb => n1978
);
U1373 : nor2 port map( a => mult_125_ab_14_5_port, b => n1981, outb => n1980
);
U1374 : nand2 port map( a => n1983, b => n1984, outb => n1982);
U1375 : nand2 port map( a => n1986, b => n1987, outb => n1985);
U1376 : nor2 port map( a => mult_125_ab_3_4_port, b => n1989, outb => n1988)
;
U1377 : nor2 port map( a => mult_125_ab_4_4_port, b => n1991, outb => n1990)
;
U1378 : nand2 port map( a => n1993, b => n1994, outb => n1992);
U1379 : nor2 port map( a => mult_125_ab_6_4_port, b => n1996, outb => n1995)
;
U1380 : nand2 port map( a => n1998, b => n1999, outb => n1997);
U1381 : nor2 port map( a => mult_125_ab_8_4_port, b => n2001, outb => n2000)
;
U1382 : nor2 port map( a => mult_125_ab_9_4_port, b => n2003, outb => n2002)
;
U1383 : nor2 port map( a => mult_125_ab_10_4_port, b => n2005, outb => n2004
);
U1384 : nand2 port map( a => n2007, b => n2008, outb => n2006);
U1385 : nor2 port map( a => mult_125_ab_12_4_port, b => n2010, outb => n2009
);
U1386 : nor2 port map( a => mult_125_ab_13_4_port, b => n2012, outb => n2011
);
U1387 : nor2 port map( a => mult_125_ab_14_4_port, b => n2014, outb => n2013
);
U1388 : nand2 port map( a => n2016, b => n2017, outb => n2015);
U1389 : nand2 port map( a => n2019, b => n2020, outb => n2018);
U1390 : nand2 port map( a => n2022, b => n2023, outb => n2021);
U1391 : nor2 port map( a => mult_125_ab_4_3_port, b => n2025, outb => n2024)
;
U1392 : nor2 port map( a => mult_125_ab_5_3_port, b => n2027, outb => n2026)
;
U1393 : nor2 port map( a => mult_125_ab_6_3_port, b => n2029, outb => n2028)
;
U1394 : nor2 port map( a => mult_125_ab_7_3_port, b => n2031, outb => n2030)
;
U1395 : nor2 port map( a => mult_125_ab_8_3_port, b => n2033, outb => n2032)
;
U1396 : nor2 port map( a => mult_125_ab_9_3_port, b => n2035, outb => n2034)
;
U1397 : nor2 port map( a => mult_125_ab_10_3_port, b => n2037, outb => n2036
);
U1398 : nor2 port map( a => mult_125_ab_11_3_port, b => n2039, outb => n2038
);
U1399 : nor2 port map( a => mult_125_ab_12_3_port, b => n2041, outb => n2040
);
U1400 : nor2 port map( a => mult_125_ab_13_3_port, b => n2043, outb => n2042
);
U1401 : nor2 port map( a => mult_125_ab_14_3_port, b => n2045, outb => n2044
);
U1402 : nor2 port map( a => mult_125_ab_15_3_port, b => n2047, outb => n2046
);
U1403 : nand2 port map( a => n2049, b => n2050, outb => n2048);
U1404 : nor2 port map( a => mult_125_ab_3_2_port, b => n2052, outb => n2051)
;
U1405 : nor2 port map( a => mult_125_ab_4_2_port, b => n2054, outb => n2053)
;
U1406 : nor2 port map( a => mult_125_ab_5_2_port, b => n2056, outb => n2055)
;
U1407 : nor2 port map( a => mult_125_ab_6_2_port, b => n2058, outb => n2057)
;
U1408 : nand2 port map( a => n2060, b => n2061, outb => n2059);
U1409 : nor2 port map( a => mult_125_ab_8_2_port, b => n2063, outb => n2062)
;
U1410 : nor2 port map( a => mult_125_ab_9_2_port, b => n2065, outb => n2064)
;
U1411 : nor2 port map( a => mult_125_ab_10_2_port, b => n2067, outb => n2066
);
U1412 : nor2 port map( a => mult_125_ab_11_2_port, b => n2069, outb => n2068
);
U1413 : nor2 port map( a => mult_125_ab_12_2_port, b => n2071, outb => n2070
);
U1414 : nor2 port map( a => mult_125_ab_13_2_port, b => n2073, outb => n2072
);
U1415 : nor2 port map( a => mult_125_ab_14_2_port, b => n2075, outb => n2074
);
U1416 : nor2 port map( a => mult_125_ab_15_2_port, b => n2077, outb => n2076
);
U1417 : nand2 port map( a => n2079, b => n2080, outb => n2078);
U1418 : nor2 port map( a => mult_125_ab_3_1_port, b => n2082, outb => n2081)
;
U1419 : nor2 port map( a => mult_125_ab_4_1_port, b => n2084, outb => n2083)
;
U1420 : nor2 port map( a => mult_125_ab_5_1_port, b => n2086, outb => n2085)
;
U1421 : nor2 port map( a => mult_125_ab_6_1_port, b => n2088, outb => n2087)
;
U1422 : nor2 port map( a => mult_125_ab_7_1_port, b => n2090, outb => n2089)
;
U1423 : nor2 port map( a => mult_125_ab_8_1_port, b => n2092, outb => n2091)
;
U1424 : nor2 port map( a => mult_125_ab_9_1_port, b => n2094, outb => n2093)
;
U1425 : nor2 port map( a => mult_125_ab_10_1_port, b => n2096, outb => n2095
);
U1426 : nor2 port map( a => mult_125_ab_11_1_port, b => n2098, outb => n2097
);
U1427 : nor2 port map( a => mult_125_ab_12_1_port, b => n2100, outb => n2099
);
U1428 : nor2 port map( a => mult_125_ab_13_1_port, b => n2102, outb => n2101
);
U1429 : nor2 port map( a => mult_125_ab_14_1_port, b => n2104, outb => n2103
);
U1430 : nor2 port map( a => mult_125_ab_15_1_port, b => n2106, outb => n2105
);
U1431 : nor2 port map( a => mult_125_ab_2_0_port, b => n2108, outb => n2107)
;
U1432 : nor2 port map( a => mult_125_ab_3_0_port, b => n2110, outb => n2109)
;
U1433 : nor2 port map( a => mult_125_ab_4_0_port, b => n2112, outb => n2111)
;
U1434 : nor2 port map( a => mult_125_ab_5_0_port, b => n2114, outb => n2113)
;
U1435 : nor2 port map( a => mult_125_ab_6_0_port, b => n2116, outb => n2115)
;
U1436 : nor2 port map( a => mult_125_ab_7_0_port, b => n2118, outb => n2117)
;
U1437 : nor2 port map( a => mult_125_ab_8_0_port, b => n2120, outb => n2119)
;
U1438 : nor2 port map( a => mult_125_ab_9_0_port, b => n2122, outb => n2121)
;
U1439 : nor2 port map( a => mult_125_ab_10_0_port, b => n2124, outb => n2123
);
U1440 : nor2 port map( a => mult_125_ab_11_0_port, b => n2126, outb => n2125
);
U1441 : nor2 port map( a => mult_125_ab_12_0_port, b => n2128, outb => n2127
);
U1442 : nor2 port map( a => mult_125_ab_13_0_port, b => n2130, outb => n2129
);
U1443 : nor2 port map( a => mult_125_ab_14_0_port, b => n2132, outb => n2131
);
U1444 : nor2 port map( a => mult_125_ab_15_0_port, b => n2134, outb => n2133
);
U1445 : nor2 port map( a => mult_125_ZB, b => mult_125_ZA, outb => n310);
U1446 : nand2 port map( a => mult_125_QB, b => mult_125_ab_15_15_port, outb
=> n2135);
U1447 : nor2 port map( a => adder_mem_array_3_1_port, b => n2137, outb =>
n2136);
U1448 : nor2 port map( a => multiplier_sigs_2_2_port, b =>
adder_mem_array_3_2_port, outb => n2138);
U1449 : nor2 port map( a => multiplier_sigs_2_3_port, b =>
adder_mem_array_3_3_port, outb => n2139);
U1450 : nor2 port map( a => multiplier_sigs_2_4_port, b =>
adder_mem_array_3_4_port, outb => n2140);
U1451 : nor2 port map( a => multiplier_sigs_2_5_port, b =>
adder_mem_array_3_5_port, outb => n2141);
U1452 : nor2 port map( a => multiplier_sigs_2_6_port, b =>
adder_mem_array_3_6_port, outb => n2142);
U1453 : nor2 port map( a => multiplier_sigs_2_7_port, b =>
adder_mem_array_3_7_port, outb => n2143);
U1454 : nor2 port map( a => multiplier_sigs_2_8_port, b =>
adder_mem_array_3_8_port, outb => n2144);
U1455 : nor2 port map( a => multiplier_sigs_2_9_port, b =>
adder_mem_array_3_9_port, outb => n2145);
U1456 : nor2 port map( a => multiplier_sigs_2_10_port, b =>
adder_mem_array_3_10_port, outb => n2146);
U1457 : nor2 port map( a => multiplier_sigs_2_11_port, b =>
adder_mem_array_3_11_port, outb => n2147);
U1458 : nor2 port map( a => multiplier_sigs_2_12_port, b =>
adder_mem_array_3_12_port, outb => n2148);
U1459 : nor2 port map( a => multiplier_sigs_2_13_port, b =>
adder_mem_array_3_13_port, outb => n2149);
U1460 : nor2 port map( a => multiplier_sigs_2_14_port, b =>
adder_mem_array_3_14_port, outb => n2150);
U1461 : nor2 port map( a => multiplier_sigs_2_15_port, b =>
adder_mem_array_3_15_port, outb => n2151);
U1462 : nor2 port map( a => multiplier_sigs_2_16_port, b =>
adder_mem_array_3_16_port, outb => n2152);
U1463 : nor2 port map( a => multiplier_sigs_2_17_port, b =>
adder_mem_array_3_17_port, outb => n2153);
U1464 : nor2 port map( a => multiplier_sigs_2_18_port, b =>
adder_mem_array_3_18_port, outb => n2154);
U1465 : nor2 port map( a => multiplier_sigs_2_19_port, b =>
adder_mem_array_3_19_port, outb => n2155);
U1466 : nor2 port map( a => multiplier_sigs_2_20_port, b =>
adder_mem_array_3_20_port, outb => n2156);
U1467 : nor2 port map( a => multiplier_sigs_2_21_port, b =>
adder_mem_array_3_21_port, outb => n2157);
U1468 : nor2 port map( a => multiplier_sigs_2_22_port, b =>
adder_mem_array_3_22_port, outb => n2158);
U1469 : nor2 port map( a => multiplier_sigs_2_23_port, b =>
adder_mem_array_3_23_port, outb => n2159);
U1470 : nor2 port map( a => multiplier_sigs_2_24_port, b =>
adder_mem_array_3_24_port, outb => n2160);
U1471 : nor2 port map( a => multiplier_sigs_2_25_port, b =>
adder_mem_array_3_25_port, outb => n2161);
U1472 : nor2 port map( a => multiplier_sigs_2_26_port, b =>
adder_mem_array_3_26_port, outb => n2162);
U1473 : nor2 port map( a => adder_mem_array_1_1_port, b => n2164, outb =>
n2163);
U1474 : nor2 port map( a => multiplier_sigs_0_2_port, b =>
adder_mem_array_1_2_port, outb => n2165);
U1475 : nor2 port map( a => adder_mem_array_2_1_port, b => n2167, outb =>
n2166);
U1476 : nor2 port map( a => multiplier_sigs_1_2_port, b =>
adder_mem_array_2_2_port, outb => n2168);
U1477 : nor2 port map( a => multiplier_sigs_1_3_port, b =>
adder_mem_array_2_3_port, outb => n2169);
U1478 : nor2 port map( a => multiplier_sigs_1_4_port, b =>
adder_mem_array_2_4_port, outb => n2170);
U1479 : nor2 port map( a => multiplier_sigs_1_5_port, b =>
adder_mem_array_2_5_port, outb => n2171);
U1480 : nor2 port map( a => multiplier_sigs_1_6_port, b =>
adder_mem_array_2_6_port, outb => n2172);
U1481 : nor2 port map( a => multiplier_sigs_1_7_port, b =>
adder_mem_array_2_7_port, outb => n2173);
U1482 : nor2 port map( a => multiplier_sigs_1_8_port, b =>
adder_mem_array_2_8_port, outb => n2174);
U1483 : nor2 port map( a => multiplier_sigs_1_9_port, b =>
adder_mem_array_2_9_port, outb => n2175);
U1484 : nor2 port map( a => multiplier_sigs_1_10_port, b =>
adder_mem_array_2_10_port, outb => n2176);
U1485 : nor2 port map( a => multiplier_sigs_1_11_port, b =>
adder_mem_array_2_11_port, outb => n2177);
U1486 : nor2 port map( a => multiplier_sigs_1_12_port, b =>
adder_mem_array_2_12_port, outb => n2178);
U1487 : nor2 port map( a => multiplier_sigs_1_13_port, b =>
adder_mem_array_2_13_port, outb => n2179);
U1488 : nor2 port map( a => multiplier_sigs_1_14_port, b =>
adder_mem_array_2_14_port, outb => n2180);
U1489 : nor2 port map( a => multiplier_sigs_1_15_port, b =>
adder_mem_array_2_15_port, outb => n2181);
U1490 : nor2 port map( a => multiplier_sigs_1_16_port, b =>
adder_mem_array_2_16_port, outb => n2182);
U1491 : nor2 port map( a => multiplier_sigs_1_17_port, b =>
adder_mem_array_2_17_port, outb => n2183);
U1492 : nor2 port map( a => multiplier_sigs_1_18_port, b =>
adder_mem_array_2_18_port, outb => n2184);
U1493 : nor2 port map( a => multiplier_sigs_1_19_port, b =>
adder_mem_array_2_19_port, outb => n2185);
U1494 : nor2 port map( a => multiplier_sigs_1_20_port, b =>
adder_mem_array_2_20_port, outb => n2186);
U1495 : nor2 port map( a => multiplier_sigs_1_21_port, b =>
adder_mem_array_2_21_port, outb => n2187);
U1496 : nor2 port map( a => multiplier_sigs_1_22_port, b =>
adder_mem_array_2_22_port, outb => n2188);
U1497 : nor2 port map( a => multiplier_sigs_1_23_port, b =>
adder_mem_array_2_23_port, outb => n2189);
U1498 : nor2 port map( a => multiplier_sigs_1_24_port, b =>
adder_mem_array_2_24_port, outb => n2190);
U1499 : nor2 port map( a => multiplier_sigs_1_25_port, b =>
adder_mem_array_2_25_port, outb => n2191);
U1500 : nor2 port map( a => multiplier_sigs_1_26_port, b =>
adder_mem_array_2_26_port, outb => n2192);
U1501 : nor2 port map( a => multiplier_sigs_1_27_port, b =>
adder_mem_array_2_27_port, outb => n2193);
U1502 : nor2 port map( a => multiplier_sigs_1_28_port, b =>
adder_mem_array_2_28_port, outb => n2194);
U1503 : nor2 port map( a => multiplier_sigs_1_29_port, b =>
adder_mem_array_2_29_port, outb => n2195);
U1504 : nor2 port map( a => multiplier_sigs_1_30_port, b =>
adder_mem_array_2_30_port, outb => n2196);
U1505 : aoi22 port map( a => n2198, b => n2199, c =>
adder_mem_array_2_31_port, d =>
multiplier_sigs_1_31_port, outb => n2197);
U1506 : nor2 port map( a => multiplier_sigs_0_3_port, b =>
adder_mem_array_1_3_port, outb => n2200);
U1507 : nor2 port map( a => multiplier_sigs_0_4_port, b =>
adder_mem_array_1_4_port, outb => n2201);
U1508 : nor2 port map( a => multiplier_sigs_0_5_port, b =>
adder_mem_array_1_5_port, outb => n2202);
U1509 : nor2 port map( a => multiplier_sigs_0_6_port, b =>
adder_mem_array_1_6_port, outb => n2203);
U1510 : nor2 port map( a => multiplier_sigs_0_7_port, b =>
adder_mem_array_1_7_port, outb => n2204);
U1511 : nor2 port map( a => multiplier_sigs_0_8_port, b =>
adder_mem_array_1_8_port, outb => n2205);
U1512 : nor2 port map( a => multiplier_sigs_0_9_port, b =>
adder_mem_array_1_9_port, outb => n2206);
U1513 : nor2 port map( a => multiplier_sigs_0_10_port, b =>
adder_mem_array_1_10_port, outb => n2207);
U1514 : nor2 port map( a => multiplier_sigs_0_11_port, b =>
adder_mem_array_1_11_port, outb => n2208);
U1515 : nor2 port map( a => multiplier_sigs_0_12_port, b =>
adder_mem_array_1_12_port, outb => n2209);
U1516 : nor2 port map( a => multiplier_sigs_0_13_port, b =>
adder_mem_array_1_13_port, outb => n2210);
U1517 : nor2 port map( a => multiplier_sigs_0_14_port, b =>
adder_mem_array_1_14_port, outb => n2211);
U1518 : nor2 port map( a => multiplier_sigs_0_15_port, b =>
adder_mem_array_1_15_port, outb => n2212);
U1519 : nor2 port map( a => multiplier_sigs_0_16_port, b =>
adder_mem_array_1_16_port, outb => n2213);
U1520 : nor2 port map( a => multiplier_sigs_0_17_port, b =>
adder_mem_array_1_17_port, outb => n2214);
U1521 : nor2 port map( a => multiplier_sigs_0_18_port, b =>
adder_mem_array_1_18_port, outb => n2215);
U1522 : nor2 port map( a => multiplier_sigs_0_19_port, b =>
adder_mem_array_1_19_port, outb => n2216);
U1523 : nor2 port map( a => multiplier_sigs_0_20_port, b =>
adder_mem_array_1_20_port, outb => n2217);
U1524 : nor2 port map( a => multiplier_sigs_0_21_port, b =>
adder_mem_array_1_21_port, outb => n2218);
U1525 : nor2 port map( a => multiplier_sigs_0_22_port, b =>
adder_mem_array_1_22_port, outb => n2219);
U1526 : nor2 port map( a => multiplier_sigs_0_23_port, b =>
adder_mem_array_1_23_port, outb => n2220);
U1527 : nor2 port map( a => multiplier_sigs_0_24_port, b =>
adder_mem_array_1_24_port, outb => n2221);
U1528 : nor2 port map( a => multiplier_sigs_0_25_port, b =>
adder_mem_array_1_25_port, outb => n2222);
U1529 : nor2 port map( a => multiplier_sigs_0_26_port, b =>
adder_mem_array_1_26_port, outb => n2223);
U1530 : nor2 port map( a => multiplier_sigs_0_27_port, b =>
adder_mem_array_1_27_port, outb => n2224);
U1531 : nor2 port map( a => multiplier_sigs_0_28_port, b =>
adder_mem_array_1_28_port, outb => n2225);
U1532 : nor2 port map( a => multiplier_sigs_0_29_port, b =>
adder_mem_array_1_29_port, outb => n2226);
U1533 : nor2 port map( a => multiplier_sigs_0_30_port, b =>
adder_mem_array_1_30_port, outb => n2227);
U1534 : aoi22 port map( a => n2229, b => n2230, c =>
adder_mem_array_1_31_port, d =>
multiplier_sigs_0_31_port, outb => n2228);
U1535 : nor2 port map( a => multiplier_sigs_2_27_port, b =>
adder_mem_array_3_27_port, outb => n2231);
U1536 : nor2 port map( a => multiplier_sigs_2_28_port, b =>
adder_mem_array_3_28_port, outb => n2232);
U1537 : nor2 port map( a => multiplier_sigs_2_29_port, b =>
adder_mem_array_3_29_port, outb => n2233);
U1538 : nor2 port map( a => multiplier_sigs_2_30_port, b =>
adder_mem_array_3_30_port, outb => n2234);
U1539 : aoi22 port map( a => n2236, b => n2237, c =>
adder_mem_array_3_31_port, d =>
multiplier_sigs_2_31_port, outb => n2235);
U1540 : xor2 port map( a => mult_125_G4_ab_15_15_port, b => n2239, outb =>
n2238);
U1541 : xor2 port map( a => mult_125_G4_ab_1_14_port, b =>
mult_125_G4_ab_0_15_port, outb => n2240);
U1542 : xor2 port map( a => n2242, b => mult_125_G4_ab_1_15_port, outb =>
n2241);
U1543 : xor2 port map( a => mult_125_G4_ab_1_13_port, b =>
mult_125_G4_ab_0_14_port, outb => n2243);
U1544 : xor2 port map( a => n2245, b => n2240, outb => n2244);
U1545 : xor2 port map( a => n2247, b => n2248, outb => n2246);
U1546 : xor2 port map( a => n2250, b => n2251, outb => n2249);
U1547 : xor2 port map( a => n2253, b => n2254, outb => n2252);
U1548 : xor2 port map( a => n2256, b => n2257, outb => n2255);
U1549 : xor2 port map( a => n2259, b => n2260, outb => n2258);
U1550 : xor2 port map( a => n2262, b => n2263, outb => n2261);
U1551 : xor2 port map( a => n2265, b => n2266, outb => n2264);
U1552 : xor2 port map( a => n2268, b => n2269, outb => n2267);
U1553 : xor2 port map( a => n2271, b => n2272, outb => n2270);
U1554 : xor2 port map( a => n2274, b => n2275, outb => n2273);
U1555 : xor2 port map( a => n2277, b => n2278, outb => n2276);
U1556 : xor2 port map( a => n2279, b => n2280, outb => n246);
U1557 : xor2 port map( a => mult_125_G4_ab_1_12_port, b =>
mult_125_G4_ab_0_13_port, outb => n2281);
U1558 : xor2 port map( a => n2283, b => n2243, outb => n2282);
U1559 : xor2 port map( a => n2285, b => n2286, outb => n2284);
U1560 : xor2 port map( a => mult_125_G4_ab_1_11_port, b =>
mult_125_G4_ab_0_12_port, outb => n2287);
U1561 : xor2 port map( a => n2289, b => n2281, outb => n2288);
U1562 : xor2 port map( a => n2291, b => n2292, outb => n2290);
U1563 : xor2 port map( a => n2294, b => n2295, outb => n2293);
U1564 : xor2 port map( a => n2297, b => n2298, outb => n2296);
U1565 : xor2 port map( a => n2300, b => n2301, outb => n2299);
U1566 : xor2 port map( a => n2303, b => n2304, outb => n2302);
U1567 : xor2 port map( a => n2306, b => n2307, outb => n2305);
U1568 : xor2 port map( a => n2309, b => n2310, outb => n2308);
U1569 : xor2 port map( a => n2312, b => n2313, outb => n2311);
U1570 : xor2 port map( a => n2315, b => n2316, outb => n2314);
U1571 : xor2 port map( a => n2318, b => n2319, outb => n2317);
U1572 : xor2 port map( a => n2320, b => n2321, outb => n250);
U1573 : xor2 port map( a => mult_125_G4_ab_1_10_port, b =>
mult_125_G4_ab_0_11_port, outb => n2322);
U1574 : xor2 port map( a => n2324, b => n2287, outb => n2323);
U1575 : xor2 port map( a => n2326, b => n2327, outb => n2325);
U1576 : xor2 port map( a => n2329, b => n2330, outb => n2328);
U1577 : xor2 port map( a => mult_125_G4_ab_1_9_port, b =>
mult_125_G4_ab_0_10_port, outb => n2331);
U1578 : xor2 port map( a => n2333, b => n2322, outb => n2332);
U1579 : xor2 port map( a => n2335, b => n2336, outb => n2334);
U1580 : xor2 port map( a => n2338, b => n2339, outb => n2337);
U1581 : xor2 port map( a => n2341, b => n2342, outb => n2340);
U1582 : xor2 port map( a => n2344, b => n2345, outb => n2343);
U1583 : xor2 port map( a => n2347, b => n2348, outb => n2346);
U1584 : xor2 port map( a => n2350, b => n2351, outb => n2349);
U1585 : xor2 port map( a => n2353, b => n2354, outb => n2352);
U1586 : xor2 port map( a => n2356, b => n2357, outb => n2355);
U1587 : xor2 port map( a => n2359, b => n2360, outb => n2358);
U1588 : xor2 port map( a => n2361, b => n2362, outb => n254);
U1589 : xor2 port map( a => mult_125_G4_ab_1_8_port, b =>
mult_125_G4_ab_0_9_port, outb => n2363);
U1590 : xor2 port map( a => n2365, b => n2331, outb => n2364);
U1591 : xor2 port map( a => n2367, b => n2368, outb => n2366);
U1592 : xor2 port map( a => n2370, b => n2371, outb => n2369);
U1593 : xor2 port map( a => n2373, b => n2374, outb => n2372);
U1594 : xor2 port map( a => mult_125_G4_ab_1_7_port, b =>
mult_125_G4_ab_0_8_port, outb => n2375);
U1595 : xor2 port map( a => n2377, b => n2363, outb => n2376);
U1596 : xor2 port map( a => n2379, b => n2380, outb => n2378);
U1597 : xor2 port map( a => n2382, b => n2383, outb => n2381);
U1598 : xor2 port map( a => n2385, b => n2386, outb => n2384);
U1599 : xor2 port map( a => n2388, b => n2389, outb => n2387);
U1600 : xor2 port map( a => n2391, b => n2392, outb => n2390);
U1601 : xor2 port map( a => n2394, b => n2395, outb => n2393);
U1602 : xor2 port map( a => n2397, b => n2398, outb => n2396);
U1603 : xor2 port map( a => n2400, b => n2401, outb => n2399);
U1604 : xor2 port map( a => n2402, b => n2403, outb => n258);
U1605 : xor2 port map( a => mult_125_G4_ab_1_6_port, b =>
mult_125_G4_ab_0_7_port, outb => n2404);
U1606 : xor2 port map( a => n2406, b => n2375, outb => n2405);
U1607 : xor2 port map( a => n2408, b => n2409, outb => n2407);
U1608 : xor2 port map( a => n2411, b => n2412, outb => n2410);
U1609 : xor2 port map( a => n2414, b => n2415, outb => n2413);
U1610 : xor2 port map( a => n2417, b => n2418, outb => n2416);
U1611 : xor2 port map( a => mult_125_G4_ab_1_5_port, b =>
mult_125_G4_ab_0_6_port, outb => n2419);
U1612 : xor2 port map( a => n2421, b => n2404, outb => n2420);
U1613 : xor2 port map( a => n2423, b => n2424, outb => n2422);
U1614 : xor2 port map( a => n2426, b => n2427, outb => n2425);
U1615 : xor2 port map( a => n2429, b => n2430, outb => n2428);
U1616 : xor2 port map( a => n2432, b => n2433, outb => n2431);
U1617 : xor2 port map( a => n2435, b => n2436, outb => n2434);
U1618 : xor2 port map( a => n2438, b => n2439, outb => n2437);
U1619 : xor2 port map( a => n2441, b => n2442, outb => n2440);
U1620 : xor2 port map( a => n2443, b => n2444, outb => n262);
U1621 : xor2 port map( a => mult_125_G4_ab_1_4_port, b =>
mult_125_G4_ab_0_5_port, outb => n2445);
U1622 : xor2 port map( a => n2447, b => n2419, outb => n2446);
U1623 : xor2 port map( a => n2449, b => n2450, outb => n2448);
U1624 : xor2 port map( a => n2452, b => n2453, outb => n2451);
U1625 : xor2 port map( a => n2455, b => n2456, outb => n2454);
U1626 : xor2 port map( a => n2458, b => n2459, outb => n2457);
U1627 : xor2 port map( a => n2461, b => n2462, outb => n2460);
U1628 : xor2 port map( a => mult_125_G4_ab_1_3_port, b =>
mult_125_G4_ab_0_4_port, outb => n2463);
U1629 : xor2 port map( a => n2465, b => n2445, outb => n2464);
U1630 : xor2 port map( a => n2467, b => n2468, outb => n2466);
U1631 : xor2 port map( a => n2470, b => n2471, outb => n2469);
U1632 : xor2 port map( a => n2473, b => n2474, outb => n2472);
U1633 : xor2 port map( a => n2476, b => n2477, outb => n2475);
U1634 : xor2 port map( a => n2479, b => n2480, outb => n2478);
U1635 : xor2 port map( a => n2482, b => n2483, outb => n2481);
U1636 : xor2 port map( a => n2484, b => n2485, outb => n267);
U1637 : xor2 port map( a => mult_125_G4_ab_1_2_port, b =>
mult_125_G4_ab_0_3_port, outb => n2486);
U1638 : xor2 port map( a => n2488, b => n2463, outb => n2487);
U1639 : xor2 port map( a => n2490, b => n2491, outb => n2489);
U1640 : xor2 port map( a => n2493, b => n2494, outb => n2492);
U1641 : xor2 port map( a => n2496, b => n2497, outb => n2495);
U1642 : xor2 port map( a => n2499, b => n2500, outb => n2498);
U1643 : xor2 port map( a => n2502, b => n2503, outb => n2501);
U1644 : xor2 port map( a => n2505, b => n2506, outb => n2504);
U1645 : xor2 port map( a => mult_125_G4_ab_1_1_port, b =>
mult_125_G4_ab_0_2_port, outb => n2507);
U1646 : xor2 port map( a => n2509, b => n2486, outb => n2508);
U1647 : xor2 port map( a => n2511, b => n2512, outb => n2510);
U1648 : xor2 port map( a => n2514, b => n2515, outb => n2513);
U1649 : xor2 port map( a => n2517, b => n2518, outb => n2516);
U1650 : xor2 port map( a => n2520, b => n2521, outb => n2519);
U1651 : xor2 port map( a => n2523, b => n2524, outb => n2522);
U1652 : xor2 port map( a => n2526, b => n2527, outb => n2525);
U1653 : xor2 port map( a => n2528, b => n2519, outb => mult_125_G4_A1_9_port
);
U1654 : xor2 port map( a => n2529, b => n2516, outb => mult_125_G4_A1_7_port
);
U1655 : xor2 port map( a => n2530, b => n2513, outb => mult_125_G4_A1_5_port
);
U1656 : xor2 port map( a => n2531, b => n2510, outb => mult_125_G4_A1_3_port
);
U1657 : xor2 port map( a => n242, b => n241, outb => mult_125_G4_A1_28_port)
;
U1658 : xor2 port map( a => n246, b => n245, outb => mult_125_G4_A1_26_port)
;
U1659 : xor2 port map( a => n250, b => n249, outb => mult_125_G4_A1_24_port)
;
U1660 : xor2 port map( a => n254, b => n253, outb => mult_125_G4_A1_22_port)
;
U1661 : xor2 port map( a => n258, b => n257, outb => mult_125_G4_A1_20_port)
;
U1662 : xor2 port map( a => n2532, b => n2508, outb => mult_125_G4_A1_1_port
);
U1663 : xor2 port map( a => n262, b => n261, outb => mult_125_G4_A1_18_port)
;
U1664 : xor2 port map( a => n267, b => n266, outb => mult_125_G4_A1_16_port)
;
U1665 : xor2 port map( a => n2533, b => n275, outb => mult_125_G4_A1_13_port
);
U1666 : xor2 port map( a => n2534, b => n2522, outb =>
mult_125_G4_A1_11_port);
U1667 : xor2 port map( a => mult_125_G3_ab_15_15_port, b => n2536, outb =>
n2535);
U1668 : xor2 port map( a => mult_125_G3_ab_1_14_port, b =>
mult_125_G3_ab_0_15_port, outb => n2537);
U1669 : xor2 port map( a => n2539, b => mult_125_G3_ab_1_15_port, outb =>
n2538);
U1670 : xor2 port map( a => mult_125_G3_ab_1_13_port, b =>
mult_125_G3_ab_0_14_port, outb => n2540);
U1671 : xor2 port map( a => n2542, b => n2537, outb => n2541);
U1672 : xor2 port map( a => n2544, b => n2545, outb => n2543);
U1673 : xor2 port map( a => n2547, b => n2548, outb => n2546);
U1674 : xor2 port map( a => n2550, b => n2551, outb => n2549);
U1675 : xor2 port map( a => n2553, b => n2554, outb => n2552);
U1676 : xor2 port map( a => n2556, b => n2557, outb => n2555);
U1677 : xor2 port map( a => n2559, b => n2560, outb => n2558);
U1678 : xor2 port map( a => n2562, b => n2563, outb => n2561);
U1679 : xor2 port map( a => n2565, b => n2566, outb => n2564);
U1680 : xor2 port map( a => n2568, b => n2569, outb => n2567);
U1681 : xor2 port map( a => n2571, b => n2572, outb => n2570);
U1682 : xor2 port map( a => n2574, b => n2575, outb => n2573);
U1683 : xor2 port map( a => n2576, b => n2577, outb => n354);
U1684 : xor2 port map( a => mult_125_G3_ab_1_12_port, b =>
mult_125_G3_ab_0_13_port, outb => n2578);
U1685 : xor2 port map( a => n2580, b => n2540, outb => n2579);
U1686 : xor2 port map( a => n2582, b => n2583, outb => n2581);
U1687 : xor2 port map( a => mult_125_G3_ab_1_11_port, b =>
mult_125_G3_ab_0_12_port, outb => n2584);
U1688 : xor2 port map( a => n2586, b => n2578, outb => n2585);
U1689 : xor2 port map( a => n2588, b => n2589, outb => n2587);
U1690 : xor2 port map( a => n2591, b => n2592, outb => n2590);
U1691 : xor2 port map( a => n2594, b => n2595, outb => n2593);
U1692 : xor2 port map( a => n2597, b => n2598, outb => n2596);
U1693 : xor2 port map( a => n2600, b => n2601, outb => n2599);
U1694 : xor2 port map( a => n2603, b => n2604, outb => n2602);
U1695 : xor2 port map( a => n2606, b => n2607, outb => n2605);
U1696 : xor2 port map( a => n2609, b => n2610, outb => n2608);
U1697 : xor2 port map( a => n2612, b => n2613, outb => n2611);
U1698 : xor2 port map( a => n2615, b => n2616, outb => n2614);
U1699 : xor2 port map( a => n2617, b => n2618, outb => n358);
U1700 : xor2 port map( a => mult_125_G3_ab_1_10_port, b =>
mult_125_G3_ab_0_11_port, outb => n2619);
U1701 : xor2 port map( a => n2621, b => n2584, outb => n2620);
U1702 : xor2 port map( a => n2623, b => n2624, outb => n2622);
U1703 : xor2 port map( a => n2626, b => n2627, outb => n2625);
U1704 : xor2 port map( a => mult_125_G3_ab_1_9_port, b =>
mult_125_G3_ab_0_10_port, outb => n2628);
U1705 : xor2 port map( a => n2630, b => n2619, outb => n2629);
U1706 : xor2 port map( a => n2632, b => n2633, outb => n2631);
U1707 : xor2 port map( a => n2635, b => n2636, outb => n2634);
U1708 : xor2 port map( a => n2638, b => n2639, outb => n2637);
U1709 : xor2 port map( a => n2641, b => n2642, outb => n2640);
U1710 : xor2 port map( a => n2644, b => n2645, outb => n2643);
U1711 : xor2 port map( a => n2647, b => n2648, outb => n2646);
U1712 : xor2 port map( a => n2650, b => n2651, outb => n2649);
U1713 : xor2 port map( a => n2653, b => n2654, outb => n2652);
U1714 : xor2 port map( a => n2656, b => n2657, outb => n2655);
U1715 : xor2 port map( a => n2658, b => n2659, outb => n362);
U1716 : xor2 port map( a => mult_125_G3_ab_1_8_port, b =>
mult_125_G3_ab_0_9_port, outb => n2660);
U1717 : xor2 port map( a => n2662, b => n2628, outb => n2661);
U1718 : xor2 port map( a => n2664, b => n2665, outb => n2663);
U1719 : xor2 port map( a => n2667, b => n2668, outb => n2666);
U1720 : xor2 port map( a => n2670, b => n2671, outb => n2669);
U1721 : xor2 port map( a => mult_125_G3_ab_1_7_port, b =>
mult_125_G3_ab_0_8_port, outb => n2672);
U1722 : xor2 port map( a => n2674, b => n2660, outb => n2673);
U1723 : xor2 port map( a => n2676, b => n2677, outb => n2675);
U1724 : xor2 port map( a => n2679, b => n2680, outb => n2678);
U1725 : xor2 port map( a => n2682, b => n2683, outb => n2681);
U1726 : xor2 port map( a => n2685, b => n2686, outb => n2684);
U1727 : xor2 port map( a => n2688, b => n2689, outb => n2687);
U1728 : xor2 port map( a => n2691, b => n2692, outb => n2690);
U1729 : xor2 port map( a => n2694, b => n2695, outb => n2693);
U1730 : xor2 port map( a => n2697, b => n2698, outb => n2696);
U1731 : xor2 port map( a => n2699, b => n2700, outb => n366);
U1732 : xor2 port map( a => mult_125_G3_ab_1_6_port, b =>
mult_125_G3_ab_0_7_port, outb => n2701);
U1733 : xor2 port map( a => n2703, b => n2672, outb => n2702);
U1734 : xor2 port map( a => n2705, b => n2706, outb => n2704);
U1735 : xor2 port map( a => n2708, b => n2709, outb => n2707);
U1736 : xor2 port map( a => n2711, b => n2712, outb => n2710);
U1737 : xor2 port map( a => n2714, b => n2715, outb => n2713);
U1738 : xor2 port map( a => mult_125_G3_ab_1_5_port, b =>
mult_125_G3_ab_0_6_port, outb => n2716);
U1739 : xor2 port map( a => n2718, b => n2701, outb => n2717);
U1740 : xor2 port map( a => n2720, b => n2721, outb => n2719);
U1741 : xor2 port map( a => n2723, b => n2724, outb => n2722);
U1742 : xor2 port map( a => n2726, b => n2727, outb => n2725);
U1743 : xor2 port map( a => n2729, b => n2730, outb => n2728);
U1744 : xor2 port map( a => n2732, b => n2733, outb => n2731);
U1745 : xor2 port map( a => n2735, b => n2736, outb => n2734);
U1746 : xor2 port map( a => n2738, b => n2739, outb => n2737);
U1747 : xor2 port map( a => n2740, b => n2741, outb => n370);
U1748 : xor2 port map( a => mult_125_G3_ab_1_4_port, b =>
mult_125_G3_ab_0_5_port, outb => n2742);
U1749 : xor2 port map( a => n2744, b => n2716, outb => n2743);
U1750 : xor2 port map( a => n2746, b => n2747, outb => n2745);
U1751 : xor2 port map( a => n2749, b => n2750, outb => n2748);
U1752 : xor2 port map( a => n2752, b => n2753, outb => n2751);
U1753 : xor2 port map( a => n2755, b => n2756, outb => n2754);
U1754 : xor2 port map( a => n2758, b => n2759, outb => n2757);
U1755 : xor2 port map( a => mult_125_G3_ab_1_3_port, b =>
mult_125_G3_ab_0_4_port, outb => n2760);
U1756 : xor2 port map( a => n2762, b => n2742, outb => n2761);
U1757 : xor2 port map( a => n2764, b => n2765, outb => n2763);
U1758 : xor2 port map( a => n2767, b => n2768, outb => n2766);
U1759 : xor2 port map( a => n2770, b => n2771, outb => n2769);
U1760 : xor2 port map( a => n2773, b => n2774, outb => n2772);
U1761 : xor2 port map( a => n2776, b => n2777, outb => n2775);
U1762 : xor2 port map( a => n2779, b => n2780, outb => n2778);
U1763 : xor2 port map( a => n2781, b => n2782, outb => n375);
U1764 : xor2 port map( a => mult_125_G3_ab_1_2_port, b =>
mult_125_G3_ab_0_3_port, outb => n2783);
U1765 : xor2 port map( a => n2785, b => n2760, outb => n2784);
U1766 : xor2 port map( a => n2787, b => n2788, outb => n2786);
U1767 : xor2 port map( a => n2790, b => n2791, outb => n2789);
U1768 : xor2 port map( a => n2793, b => n2794, outb => n2792);
U1769 : xor2 port map( a => n2796, b => n2797, outb => n2795);
U1770 : xor2 port map( a => n2799, b => n2800, outb => n2798);
U1771 : xor2 port map( a => n2802, b => n2803, outb => n2801);
U1772 : xor2 port map( a => mult_125_G3_ab_1_1_port, b =>
mult_125_G3_ab_0_2_port, outb => n2804);
U1773 : xor2 port map( a => n2806, b => n2783, outb => n2805);
U1774 : xor2 port map( a => n2808, b => n2809, outb => n2807);
U1775 : xor2 port map( a => n2811, b => n2812, outb => n2810);
U1776 : xor2 port map( a => n2814, b => n2815, outb => n2813);
U1777 : xor2 port map( a => n2817, b => n2818, outb => n2816);
U1778 : xor2 port map( a => n2820, b => n2821, outb => n2819);
U1779 : xor2 port map( a => n2823, b => n2824, outb => n2822);
U1780 : xor2 port map( a => n2825, b => n2816, outb => mult_125_G3_A1_9_port
);
U1781 : xor2 port map( a => n2826, b => n2813, outb => mult_125_G3_A1_7_port
);
U1782 : xor2 port map( a => n2827, b => n2810, outb => mult_125_G3_A1_5_port
);
U1783 : xor2 port map( a => n2828, b => n2807, outb => mult_125_G3_A1_3_port
);
U1784 : xor2 port map( a => n350, b => n349, outb => mult_125_G3_A1_28_port)
;
U1785 : xor2 port map( a => n354, b => n353, outb => mult_125_G3_A1_26_port)
;
U1786 : xor2 port map( a => n358, b => n357, outb => mult_125_G3_A1_24_port)
;
U1787 : xor2 port map( a => n362, b => n361, outb => mult_125_G3_A1_22_port)
;
U1788 : xor2 port map( a => n366, b => n365, outb => mult_125_G3_A1_20_port)
;
U1789 : xor2 port map( a => n2829, b => n2805, outb => mult_125_G3_A1_1_port
);
U1790 : xor2 port map( a => n370, b => n369, outb => mult_125_G3_A1_18_port)
;
U1791 : xor2 port map( a => n375, b => n374, outb => mult_125_G3_A1_16_port)
;
U1792 : xor2 port map( a => n2830, b => n383, outb => mult_125_G3_A1_13_port
);
U1793 : xor2 port map( a => n2831, b => n2819, outb =>
mult_125_G3_A1_11_port);
U1794 : xor2 port map( a => mult_125_G2_ab_15_15_port, b => n2833, outb =>
n2832);
U1795 : xor2 port map( a => mult_125_G2_ab_1_14_port, b =>
mult_125_G2_ab_0_15_port, outb => n2834);
U1796 : xor2 port map( a => n2836, b => mult_125_G2_ab_1_15_port, outb =>
n2835);
U1797 : xor2 port map( a => mult_125_G2_ab_1_13_port, b =>
mult_125_G2_ab_0_14_port, outb => n2837);
U1798 : xor2 port map( a => n2839, b => n2834, outb => n2838);
U1799 : xor2 port map( a => n2841, b => n2842, outb => n2840);
U1800 : xor2 port map( a => n2844, b => n2845, outb => n2843);
U1801 : xor2 port map( a => n2847, b => n2848, outb => n2846);
U1802 : xor2 port map( a => n2850, b => n2851, outb => n2849);
U1803 : xor2 port map( a => n2853, b => n2854, outb => n2852);
U1804 : xor2 port map( a => n2856, b => n2857, outb => n2855);
U1805 : xor2 port map( a => n2859, b => n2860, outb => n2858);
U1806 : xor2 port map( a => n2862, b => n2863, outb => n2861);
U1807 : xor2 port map( a => n2865, b => n2866, outb => n2864);
U1808 : xor2 port map( a => n2868, b => n2869, outb => n2867);
U1809 : xor2 port map( a => n2871, b => n2872, outb => n2870);
U1810 : xor2 port map( a => n2873, b => n2874, outb => n318);
U1811 : xor2 port map( a => mult_125_G2_ab_1_12_port, b =>
mult_125_G2_ab_0_13_port, outb => n2875);
U1812 : xor2 port map( a => n2877, b => n2837, outb => n2876);
U1813 : xor2 port map( a => n2879, b => n2880, outb => n2878);
U1814 : xor2 port map( a => mult_125_G2_ab_1_11_port, b =>
mult_125_G2_ab_0_12_port, outb => n2881);
U1815 : xor2 port map( a => n2883, b => n2875, outb => n2882);
U1816 : xor2 port map( a => n2885, b => n2886, outb => n2884);
U1817 : xor2 port map( a => n2888, b => n2889, outb => n2887);
U1818 : xor2 port map( a => n2891, b => n2892, outb => n2890);
U1819 : xor2 port map( a => n2894, b => n2895, outb => n2893);
U1820 : xor2 port map( a => n2897, b => n2898, outb => n2896);
U1821 : xor2 port map( a => n2900, b => n2901, outb => n2899);
U1822 : xor2 port map( a => n2903, b => n2904, outb => n2902);
U1823 : xor2 port map( a => n2906, b => n2907, outb => n2905);
U1824 : xor2 port map( a => n2909, b => n2910, outb => n2908);
U1825 : xor2 port map( a => n2912, b => n2913, outb => n2911);
U1826 : xor2 port map( a => n2914, b => n2915, outb => n322);
U1827 : xor2 port map( a => mult_125_G2_ab_1_10_port, b =>
mult_125_G2_ab_0_11_port, outb => n2916);
U1828 : xor2 port map( a => n2918, b => n2881, outb => n2917);
U1829 : xor2 port map( a => n2920, b => n2921, outb => n2919);
U1830 : xor2 port map( a => n2923, b => n2924, outb => n2922);
U1831 : xor2 port map( a => mult_125_G2_ab_1_9_port, b =>
mult_125_G2_ab_0_10_port, outb => n2925);
U1832 : xor2 port map( a => n2927, b => n2916, outb => n2926);
U1833 : xor2 port map( a => n2929, b => n2930, outb => n2928);
U1834 : xor2 port map( a => n2932, b => n2933, outb => n2931);
U1835 : xor2 port map( a => n2935, b => n2936, outb => n2934);
U1836 : xor2 port map( a => n2938, b => n2939, outb => n2937);
U1837 : xor2 port map( a => n2941, b => n2942, outb => n2940);
U1838 : xor2 port map( a => n2944, b => n2945, outb => n2943);
U1839 : xor2 port map( a => n2947, b => n2948, outb => n2946);
U1840 : xor2 port map( a => n2950, b => n2951, outb => n2949);
U1841 : xor2 port map( a => n2953, b => n2954, outb => n2952);
U1842 : xor2 port map( a => n2955, b => n2956, outb => n326);
U1843 : xor2 port map( a => mult_125_G2_ab_1_8_port, b =>
mult_125_G2_ab_0_9_port, outb => n2957);
U1844 : xor2 port map( a => n2959, b => n2925, outb => n2958);
U1845 : xor2 port map( a => n2961, b => n2962, outb => n2960);
U1846 : xor2 port map( a => n2964, b => n2965, outb => n2963);
U1847 : xor2 port map( a => n2967, b => n2968, outb => n2966);
U1848 : xor2 port map( a => mult_125_G2_ab_1_7_port, b =>
mult_125_G2_ab_0_8_port, outb => n2969);
U1849 : xor2 port map( a => n2971, b => n2957, outb => n2970);
U1850 : xor2 port map( a => n2973, b => n2974, outb => n2972);
U1851 : xor2 port map( a => n2976, b => n2977, outb => n2975);
U1852 : xor2 port map( a => n2979, b => n2980, outb => n2978);
U1853 : xor2 port map( a => n2982, b => n2983, outb => n2981);
U1854 : xor2 port map( a => n2985, b => n2986, outb => n2984);
U1855 : xor2 port map( a => n2988, b => n2989, outb => n2987);
U1856 : xor2 port map( a => n2991, b => n2992, outb => n2990);
U1857 : xor2 port map( a => n2994, b => n2995, outb => n2993);
U1858 : xor2 port map( a => n2996, b => n2997, outb => n330);
U1859 : xor2 port map( a => mult_125_G2_ab_1_6_port, b =>
mult_125_G2_ab_0_7_port, outb => n2998);
U1860 : xor2 port map( a => n3000, b => n2969, outb => n2999);
U1861 : xor2 port map( a => n3002, b => n3003, outb => n3001);
U1862 : xor2 port map( a => n3005, b => n3006, outb => n3004);
U1863 : xor2 port map( a => n3008, b => n3009, outb => n3007);
U1864 : xor2 port map( a => n3011, b => n3012, outb => n3010);
U1865 : xor2 port map( a => mult_125_G2_ab_1_5_port, b =>
mult_125_G2_ab_0_6_port, outb => n3013);
U1866 : xor2 port map( a => n3015, b => n2998, outb => n3014);
U1867 : xor2 port map( a => n3017, b => n3018, outb => n3016);
U1868 : xor2 port map( a => n3020, b => n3021, outb => n3019);
U1869 : xor2 port map( a => n3023, b => n3024, outb => n3022);
U1870 : xor2 port map( a => n3026, b => n3027, outb => n3025);
U1871 : xor2 port map( a => n3029, b => n3030, outb => n3028);
U1872 : xor2 port map( a => n3032, b => n3033, outb => n3031);
U1873 : xor2 port map( a => n3035, b => n3036, outb => n3034);
U1874 : xor2 port map( a => n3037, b => n3038, outb => n334);
U1875 : xor2 port map( a => mult_125_G2_ab_1_4_port, b =>
mult_125_G2_ab_0_5_port, outb => n3039);
U1876 : xor2 port map( a => n3041, b => n3013, outb => n3040);
U1877 : xor2 port map( a => n3043, b => n3044, outb => n3042);
U1878 : xor2 port map( a => n3046, b => n3047, outb => n3045);
U1879 : xor2 port map( a => n3049, b => n3050, outb => n3048);
U1880 : xor2 port map( a => n3052, b => n3053, outb => n3051);
U1881 : xor2 port map( a => n3055, b => n3056, outb => n3054);
U1882 : xor2 port map( a => mult_125_G2_ab_1_3_port, b =>
mult_125_G2_ab_0_4_port, outb => n3057);
U1883 : xor2 port map( a => n3059, b => n3039, outb => n3058);
U1884 : xor2 port map( a => n3061, b => n3062, outb => n3060);
U1885 : xor2 port map( a => n3064, b => n3065, outb => n3063);
U1886 : xor2 port map( a => n3067, b => n3068, outb => n3066);
U1887 : xor2 port map( a => n3070, b => n3071, outb => n3069);
U1888 : xor2 port map( a => n3073, b => n3074, outb => n3072);
U1889 : xor2 port map( a => n3076, b => n3077, outb => n3075);
U1890 : xor2 port map( a => n3078, b => n3079, outb => n339);
U1891 : xor2 port map( a => mult_125_G2_ab_1_2_port, b =>
mult_125_G2_ab_0_3_port, outb => n3080);
U1892 : xor2 port map( a => n3082, b => n3057, outb => n3081);
U1893 : xor2 port map( a => n3084, b => n3085, outb => n3083);
U1894 : xor2 port map( a => n3087, b => n3088, outb => n3086);
U1895 : xor2 port map( a => n3090, b => n3091, outb => n3089);
U1896 : xor2 port map( a => n3093, b => n3094, outb => n3092);
U1897 : xor2 port map( a => n3096, b => n3097, outb => n3095);
U1898 : xor2 port map( a => n3099, b => n3100, outb => n3098);
U1899 : xor2 port map( a => mult_125_G2_ab_1_1_port, b =>
mult_125_G2_ab_0_2_port, outb => n3101);
U1900 : xor2 port map( a => n3103, b => n3080, outb => n3102);
U1901 : xor2 port map( a => n3105, b => n3106, outb => n3104);
U1902 : xor2 port map( a => n3108, b => n3109, outb => n3107);
U1903 : xor2 port map( a => n3111, b => n3112, outb => n3110);
U1904 : xor2 port map( a => n3114, b => n3115, outb => n3113);
U1905 : xor2 port map( a => n3117, b => n3118, outb => n3116);
U1906 : xor2 port map( a => n3120, b => n3121, outb => n3119);
U1907 : xor2 port map( a => n3122, b => n3113, outb => mult_125_G2_A1_9_port
);
U1908 : xor2 port map( a => n3123, b => n3110, outb => mult_125_G2_A1_7_port
);
U1909 : xor2 port map( a => n3124, b => n3107, outb => mult_125_G2_A1_5_port
);
U1910 : xor2 port map( a => n3125, b => n3104, outb => mult_125_G2_A1_3_port
);
U1911 : xor2 port map( a => n314, b => n313, outb => mult_125_G2_A1_28_port)
;
U1912 : xor2 port map( a => n318, b => n317, outb => mult_125_G2_A1_26_port)
;
U1913 : xor2 port map( a => n322, b => n321, outb => mult_125_G2_A1_24_port)
;
U1914 : xor2 port map( a => n326, b => n325, outb => mult_125_G2_A1_22_port)
;
U1915 : xor2 port map( a => n330, b => n329, outb => mult_125_G2_A1_20_port)
;
U1916 : xor2 port map( a => n3126, b => n3102, outb => mult_125_G2_A1_1_port
);
U1917 : xor2 port map( a => n334, b => n333, outb => mult_125_G2_A1_18_port)
;
U1918 : xor2 port map( a => n339, b => n338, outb => mult_125_G2_A1_16_port)
;
U1919 : xor2 port map( a => n3127, b => n347, outb => mult_125_G2_A1_13_port
);
U1920 : xor2 port map( a => n3128, b => n3116, outb =>
mult_125_G2_A1_11_port);
U1921 : xor2 port map( a => mult_125_ab_15_15_port, b => n3130, outb =>
n3129);
U1922 : xor2 port map( a => mult_125_ab_1_14_port, b =>
mult_125_ab_0_15_port, outb => n3131);
U1923 : xor2 port map( a => n3133, b => mult_125_ab_1_15_port, outb => n3132
);
U1924 : xor2 port map( a => mult_125_ab_1_13_port, b =>
mult_125_ab_0_14_port, outb => n3134);
U1925 : xor2 port map( a => n3136, b => n3131, outb => n3135);
U1926 : xor2 port map( a => n3138, b => n3139, outb => n3137);
U1927 : xor2 port map( a => n3141, b => n3142, outb => n3140);
U1928 : xor2 port map( a => n3144, b => n3145, outb => n3143);
U1929 : xor2 port map( a => n3147, b => n3148, outb => n3146);
U1930 : xor2 port map( a => n3150, b => n3151, outb => n3149);
U1931 : xor2 port map( a => n3153, b => n3154, outb => n3152);
U1932 : xor2 port map( a => n3156, b => n3157, outb => n3155);
U1933 : xor2 port map( a => n3159, b => n3160, outb => n3158);
U1934 : xor2 port map( a => n3162, b => n3163, outb => n3161);
U1935 : xor2 port map( a => n3165, b => n3166, outb => n3164);
U1936 : xor2 port map( a => n3168, b => n3169, outb => n3167);
U1937 : xor2 port map( a => n3170, b => n3171, outb => n282);
U1938 : xor2 port map( a => mult_125_ab_1_12_port, b =>
mult_125_ab_0_13_port, outb => n3172);
U1939 : xor2 port map( a => n3174, b => n3134, outb => n3173);
U1940 : xor2 port map( a => n3176, b => n3177, outb => n3175);
U1941 : xor2 port map( a => mult_125_ab_1_11_port, b =>
mult_125_ab_0_12_port, outb => n3178);
U1942 : xor2 port map( a => n3180, b => n3172, outb => n3179);
U1943 : xor2 port map( a => n3182, b => n3183, outb => n3181);
U1944 : xor2 port map( a => n3185, b => n3186, outb => n3184);
U1945 : xor2 port map( a => n3188, b => n3189, outb => n3187);
U1946 : xor2 port map( a => n3191, b => n3192, outb => n3190);
U1947 : xor2 port map( a => n3194, b => n3195, outb => n3193);
U1948 : xor2 port map( a => n3197, b => n3198, outb => n3196);
U1949 : xor2 port map( a => n3200, b => n3201, outb => n3199);
U1950 : xor2 port map( a => n3203, b => n3204, outb => n3202);
U1951 : xor2 port map( a => n3206, b => n3207, outb => n3205);
U1952 : xor2 port map( a => n3209, b => n3210, outb => n3208);
U1953 : xor2 port map( a => n3211, b => n3212, outb => n286);
U1954 : xor2 port map( a => mult_125_ab_1_10_port, b =>
mult_125_ab_0_11_port, outb => n3213);
U1955 : xor2 port map( a => n3215, b => n3178, outb => n3214);
U1956 : xor2 port map( a => n3217, b => n3218, outb => n3216);
U1957 : xor2 port map( a => n3220, b => n3221, outb => n3219);
U1958 : xor2 port map( a => mult_125_ab_1_9_port, b => mult_125_ab_0_10_port
, outb => n3222);
U1959 : xor2 port map( a => n3224, b => n3213, outb => n3223);
U1960 : xor2 port map( a => n3226, b => n3227, outb => n3225);
U1961 : xor2 port map( a => n3229, b => n3230, outb => n3228);
U1962 : xor2 port map( a => n3232, b => n3233, outb => n3231);
U1963 : xor2 port map( a => n3235, b => n3236, outb => n3234);
U1964 : xor2 port map( a => n3238, b => n3239, outb => n3237);
U1965 : xor2 port map( a => n3241, b => n3242, outb => n3240);
U1966 : xor2 port map( a => n3244, b => n3245, outb => n3243);
U1967 : xor2 port map( a => n3247, b => n3248, outb => n3246);
U1968 : xor2 port map( a => n3250, b => n3251, outb => n3249);
U1969 : xor2 port map( a => n3252, b => n3253, outb => n290);
U1970 : xor2 port map( a => mult_125_ab_1_8_port, b => mult_125_ab_0_9_port,
outb => n3254);
U1971 : xor2 port map( a => n3256, b => n3222, outb => n3255);
U1972 : xor2 port map( a => n3258, b => n3259, outb => n3257);
U1973 : xor2 port map( a => n3261, b => n3262, outb => n3260);
U1974 : xor2 port map( a => n3264, b => n3265, outb => n3263);
U1975 : xor2 port map( a => mult_125_ab_1_7_port, b => mult_125_ab_0_8_port,
outb => n3266);
U1976 : xor2 port map( a => n3268, b => n3254, outb => n3267);
U1977 : xor2 port map( a => n3270, b => n3271, outb => n3269);
U1978 : xor2 port map( a => n3273, b => n3274, outb => n3272);
U1979 : xor2 port map( a => n3276, b => n3277, outb => n3275);
U1980 : xor2 port map( a => n3279, b => n3280, outb => n3278);
U1981 : xor2 port map( a => n3282, b => n3283, outb => n3281);
U1982 : xor2 port map( a => n3285, b => n3286, outb => n3284);
U1983 : xor2 port map( a => n3288, b => n3289, outb => n3287);
U1984 : xor2 port map( a => n3291, b => n3292, outb => n3290);
U1985 : xor2 port map( a => n3293, b => n3294, outb => n294);
U1986 : xor2 port map( a => mult_125_ab_1_6_port, b => mult_125_ab_0_7_port,
outb => n3295);
U1987 : xor2 port map( a => n3297, b => n3266, outb => n3296);
U1988 : xor2 port map( a => n3299, b => n3300, outb => n3298);
U1989 : xor2 port map( a => n3302, b => n3303, outb => n3301);
U1990 : xor2 port map( a => n3305, b => n3306, outb => n3304);
U1991 : xor2 port map( a => n3308, b => n3309, outb => n3307);
U1992 : xor2 port map( a => mult_125_ab_1_5_port, b => mult_125_ab_0_6_port,
outb => n3310);
U1993 : xor2 port map( a => n3312, b => n3295, outb => n3311);
U1994 : xor2 port map( a => n3314, b => n3315, outb => n3313);
U1995 : xor2 port map( a => n3317, b => n3318, outb => n3316);
U1996 : xor2 port map( a => n3320, b => n3321, outb => n3319);
U1997 : xor2 port map( a => n3323, b => n3324, outb => n3322);
U1998 : xor2 port map( a => n3326, b => n3327, outb => n3325);
U1999 : xor2 port map( a => n3329, b => n3330, outb => n3328);
U2000 : xor2 port map( a => n3332, b => n3333, outb => n3331);
U2001 : xor2 port map( a => n3334, b => n3335, outb => n298);
U2002 : xor2 port map( a => mult_125_ab_1_4_port, b => mult_125_ab_0_5_port,
outb => n3336);
U2003 : xor2 port map( a => n3338, b => n3310, outb => n3337);
U2004 : xor2 port map( a => n3340, b => n3341, outb => n3339);
U2005 : xor2 port map( a => n3343, b => n3344, outb => n3342);
U2006 : xor2 port map( a => n3346, b => n3347, outb => n3345);
U2007 : xor2 port map( a => n3349, b => n3350, outb => n3348);
U2008 : xor2 port map( a => n3352, b => n3353, outb => n3351);
U2009 : xor2 port map( a => mult_125_ab_1_3_port, b => mult_125_ab_0_4_port,
outb => n3354);
U2010 : xor2 port map( a => n3356, b => n3336, outb => n3355);
U2011 : xor2 port map( a => n3358, b => n3359, outb => n3357);
U2012 : xor2 port map( a => n3361, b => n3362, outb => n3360);
U2013 : xor2 port map( a => n3364, b => n3365, outb => n3363);
U2014 : xor2 port map( a => n3367, b => n3368, outb => n3366);
U2015 : xor2 port map( a => n3370, b => n3371, outb => n3369);
U2016 : xor2 port map( a => n3373, b => n3374, outb => n3372);
U2017 : xor2 port map( a => n3375, b => n3376, outb => n303);
U2018 : xor2 port map( a => mult_125_ab_1_2_port, b => mult_125_ab_0_3_port,
outb => n3377);
U2019 : xor2 port map( a => n3379, b => n3354, outb => n3378);
U2020 : xor2 port map( a => n3381, b => n3382, outb => n3380);
U2021 : xor2 port map( a => n3384, b => n3385, outb => n3383);
U2022 : xor2 port map( a => n3387, b => n3388, outb => n3386);
U2023 : xor2 port map( a => n3390, b => n3391, outb => n3389);
U2024 : xor2 port map( a => n3393, b => n3394, outb => n3392);
U2025 : xor2 port map( a => n3396, b => n3397, outb => n3395);
U2026 : xor2 port map( a => mult_125_ab_1_1_port, b => mult_125_ab_0_2_port,
outb => n3398);
U2027 : xor2 port map( a => n3400, b => n3377, outb => n3399);
U2028 : xor2 port map( a => n3402, b => n3403, outb => n3401);
U2029 : xor2 port map( a => n3405, b => n3406, outb => n3404);
U2030 : xor2 port map( a => n3408, b => n3409, outb => n3407);
U2031 : xor2 port map( a => n3411, b => n3412, outb => n3410);
U2032 : xor2 port map( a => n3414, b => n3415, outb => n3413);
U2033 : xor2 port map( a => n3417, b => n3418, outb => n3416);
U2034 : xor2 port map( a => n3419, b => n3410, outb => mult_125_A1_9_port);
U2035 : xor2 port map( a => n3420, b => n3407, outb => mult_125_A1_7_port);
U2036 : xor2 port map( a => n3421, b => n3404, outb => mult_125_A1_5_port);
U2037 : xor2 port map( a => n3422, b => n3401, outb => mult_125_A1_3_port);
U2038 : xor2 port map( a => n278, b => n277, outb => mult_125_A1_28_port);
U2039 : xor2 port map( a => n282, b => n281, outb => mult_125_A1_26_port);
U2040 : xor2 port map( a => n286, b => n285, outb => mult_125_A1_24_port);
U2041 : xor2 port map( a => n290, b => n289, outb => mult_125_A1_22_port);
U2042 : xor2 port map( a => n294, b => n293, outb => mult_125_A1_20_port);
U2043 : xor2 port map( a => n3423, b => n3399, outb => mult_125_A1_1_port);
U2044 : xor2 port map( a => n298, b => n297, outb => mult_125_A1_18_port);
U2045 : xor2 port map( a => n303, b => n302, outb => mult_125_A1_16_port);
U2046 : xor2 port map( a => n3424, b => n311, outb => mult_125_A1_13_port);
U2047 : xor2 port map( a => n3425, b => n3413, outb => mult_125_A1_11_port);
U2048 : xor2 port map( a => mult_125_G3_ab_1_0_port, b =>
mult_125_G3_ab_0_1_port, outb => n3426);
U2049 : xor2 port map( a => n3427, b => n3428, outb => N99);
U2050 : xor2 port map( a => n3429, b => n3430, outb => N98);
U2051 : xor2 port map( a => n3431, b => n3432, outb => N97);
U2052 : xor2 port map( a => n3433, b => n3434, outb => N96);
U2053 : xor2 port map( a => n3435, b => n3436, outb => N95);
U2054 : xor2 port map( a => n3437, b => n3438, outb => N94);
U2055 : xor2 port map( a => n3439, b => n3440, outb => N93);
U2056 : xor2 port map( a => n3441, b => n3442, outb => N92);
U2057 : xor2 port map( a => n3443, b => n3444, outb => N91);
U2058 : xor2 port map( a => n3445, b => n3446, outb => N90);
U2059 : xor2 port map( a => mult_125_ab_1_0_port, b => mult_125_ab_0_1_port,
outb => n3447);
U2060 : xor2 port map( a => n3448, b => n3449, outb => N9);
U2061 : xor2 port map( a => n3450, b => n3451, outb => N89);
U2062 : xor2 port map( a => n3452, b => n3453, outb => N88);
U2063 : xor2 port map( a => n3454, b => n3455, outb => N87);
U2064 : xor2 port map( a => n3456, b => n3457, outb => N86);
U2065 : xor2 port map( a => n3458, b => n3459, outb => N85);
U2066 : xor2 port map( a => n3460, b => n3461, outb => N84);
U2067 : xor2 port map( a => n3462, b => n3463, outb => N83);
U2068 : xor2 port map( a => n3464, b => n3465, outb => N82);
U2069 : xor2 port map( a => n3466, b => n3467, outb => N81);
U2070 : xor2 port map( a => n3468, b => n3469, outb => N80);
U2071 : xor2 port map( a => n3470, b => n3471, outb => N8);
U2072 : xor2 port map( a => n3472, b => n3473, outb => N79);
U2073 : xor2 port map( a => n3474, b => n3475, outb => N78);
U2074 : xor2 port map( a => n3476, b => n3477, outb => N77);
U2075 : xor2 port map( a => n3478, b => n3479, outb => N76);
U2076 : xor2 port map( a => n3480, b => n3481, outb => N75);
U2077 : xor2 port map( a => n3482, b => n3483, outb => N74);
U2078 : xor2 port map( a => mult_125_G2_ab_1_0_port, b =>
mult_125_G2_ab_0_1_port, outb => n3484);
U2079 : xor2 port map( a => n3485, b => n2197, outb => N71);
U2080 : xor2 port map( a => n2199, b => n3486, outb => N70);
U2081 : xor2 port map( a => n3487, b => n3488, outb => N69);
U2082 : xor2 port map( a => n3489, b => n3490, outb => N68);
U2083 : xor2 port map( a => n3491, b => n3492, outb => N67);
U2084 : xor2 port map( a => n3493, b => n3494, outb => N66);
U2085 : xor2 port map( a => n3495, b => n3496, outb => N65);
U2086 : xor2 port map( a => n3497, b => n3498, outb => N64);
U2087 : xor2 port map( a => n3499, b => n3500, outb => N63);
U2088 : xor2 port map( a => n3501, b => n3502, outb => N62);
U2089 : xor2 port map( a => n3503, b => n3504, outb => N61);
U2090 : xor2 port map( a => n3505, b => n3506, outb => N60);
U2091 : xor2 port map( a => n3507, b => n3508, outb => N59);
U2092 : xor2 port map( a => n3509, b => n3510, outb => N58);
U2093 : xor2 port map( a => n3511, b => n3512, outb => N57);
U2094 : xor2 port map( a => n3513, b => n3514, outb => N56);
U2095 : xor2 port map( a => n3515, b => n3516, outb => N55);
U2096 : xor2 port map( a => n3517, b => n3518, outb => N54);
U2097 : xor2 port map( a => n3519, b => n3520, outb => N53);
U2098 : xor2 port map( a => n3521, b => n3522, outb => N52);
U2099 : xor2 port map( a => n3523, b => n3524, outb => N51);
U2100 : xor2 port map( a => n3525, b => n3526, outb => N50);
U2101 : xor2 port map( a => n3527, b => n3528, outb => N49);
U2102 : xor2 port map( a => n3529, b => n3530, outb => N48);
U2103 : xor2 port map( a => n3531, b => n3532, outb => N47);
U2104 : xor2 port map( a => n3533, b => n3534, outb => N46);
U2105 : xor2 port map( a => n3535, b => n3536, outb => N45);
U2106 : xor2 port map( a => n3537, b => n3538, outb => N44);
U2107 : xor2 port map( a => n3539, b => n3540, outb => N43);
U2108 : xor2 port map( a => n3541, b => n3542, outb => N42);
U2109 : xor2 port map( a => n3543, b => n3544, outb => N41);
U2110 : xor2 port map( a => n3545, b => n2228, outb => N38);
U2111 : xor2 port map( a => n2230, b => n3546, outb => N37);
U2112 : xor2 port map( a => n3547, b => n3548, outb => N36);
U2113 : xor2 port map( a => n3549, b => n3550, outb => N35);
U2114 : xor2 port map( a => n3551, b => n3552, outb => N34);
U2115 : xor2 port map( a => n3553, b => n3554, outb => N33);
U2116 : xor2 port map( a => n3555, b => n3556, outb => N32);
U2117 : xor2 port map( a => n3557, b => n3558, outb => N31);
U2118 : xor2 port map( a => n3559, b => n3560, outb => N30);
U2119 : xor2 port map( a => n3561, b => n3562, outb => N29);
U2120 : xor2 port map( a => n3563, b => n3564, outb => N28);
U2121 : xor2 port map( a => n3565, b => n3566, outb => N27);
U2122 : xor2 port map( a => n3567, b => n3568, outb => N26);
U2123 : xor2 port map( a => n3569, b => n3570, outb => N25);
U2124 : xor2 port map( a => n3571, b => n3572, outb => N24);
U2125 : xor2 port map( a => n3573, b => n3574, outb => N23);
U2126 : xor2 port map( a => n3575, b => n3576, outb => N22);
U2127 : xor2 port map( a => n3577, b => n3578, outb => N21);
U2128 : xor2 port map( a => n3579, b => n3580, outb => N20);
U2129 : xor2 port map( a => n3581, b => n3582, outb => N19);
U2130 : xor2 port map( a => n3583, b => n3584, outb => N18);
U2131 : xor2 port map( a => n3585, b => n3586, outb => N17);
U2132 : xor2 port map( a => n3587, b => n3588, outb => N16);
U2133 : xor2 port map( a => n3589, b => n3590, outb => N15);
U2134 : xor2 port map( a => n3591, b => n3592, outb => N14);
U2135 : xor2 port map( a => n3593, b => n3594, outb => N13);
U2136 : xor2 port map( a => n3595, b => n3596, outb => N12);
U2137 : xor2 port map( a => n3597, b => n3598, outb => N11);
U2138 : xor2 port map( a => n3599, b => n2235, outb => N104);
U2139 : xor2 port map( a => n2237, b => n3600, outb => N103);
U2140 : xor2 port map( a => n3601, b => n3602, outb => N102);
U2141 : xor2 port map( a => n3603, b => n3604, outb => N101);
U2142 : xor2 port map( a => n3605, b => n3606, outb => N100);
U2143 : xor2 port map( a => n3607, b => n3608, outb => N10);
U2144 : nand2 port map( a => mult_125_G4_ab_0_15_port, b =>
mult_125_G4_ab_1_14_port, outb => n3609);
U2145 : inv port map( inb => mult_125_G4_ab_3_15_port, outb => n3610);
U2146 : inv port map( inb => mult_125_G4_ab_4_14_port, outb => n3611);
U2147 : inv port map( inb => mult_125_G4_ab_5_15_port, outb => n3612);
U2148 : inv port map( inb => mult_125_G4_ab_6_14_port, outb => n3613);
U2149 : inv port map( inb => mult_125_G4_ab_7_15_port, outb => n3614);
U2150 : inv port map( inb => mult_125_G4_ab_8_14_port, outb => n3615);
U2151 : inv port map( inb => mult_125_G4_ab_9_15_port, outb => n3616);
U2152 : inv port map( inb => mult_125_G4_ab_10_14_port, outb => n3617);
U2153 : inv port map( inb => mult_125_G4_ab_11_15_port, outb => n3618);
U2154 : inv port map( inb => mult_125_G4_ab_12_14_port, outb => n3619);
U2155 : nand2 port map( a => mult_125_G4_ab_0_14_port, b =>
mult_125_G4_ab_1_13_port, outb => n400);
U2156 : aoi22 port map( a => mult_125_G4_ab_2_13_port, b => n3620, c => n398
, d => n2240, outb => n403);
U2157 : oai22 port map( a => n403, b => n402, c => n3621, d => n2241, outb
=> n405);
U2158 : aoi22 port map( a => n405, b => mult_125_G4_ab_4_13_port, c => n3623
, d => n2248, outb => n3622);
U2159 : oai22 port map( a => n3622, b => n3624, c => n406, d => n2251, outb
=> n409);
U2160 : aoi22 port map( a => n409, b => mult_125_G4_ab_6_13_port, c => n3626
, d => n2254, outb => n3625);
U2161 : inv port map( inb => mult_125_G4_ab_7_13_port, outb => n3627);
U2162 : oai22 port map( a => n3625, b => n3627, c => n410, d => n2257, outb
=> n413);
U2163 : aoi22 port map( a => n413, b => mult_125_G4_ab_8_13_port, c => n3629
, d => n2260, outb => n3628);
U2164 : inv port map( inb => mult_125_G4_ab_9_13_port, outb => n3630);
U2165 : oai22 port map( a => n3628, b => n3630, c => n414, d => n2263, outb
=> n417);
U2166 : aoi22 port map( a => n417, b => mult_125_G4_ab_10_13_port, c =>
n3632, d => n2266, outb => n3631);
U2167 : inv port map( inb => mult_125_G4_ab_11_13_port, outb => n3633);
U2168 : oai22 port map( a => n3631, b => n3633, c => n418, d => n2269, outb
=> n421);
U2169 : aoi22 port map( a => n421, b => mult_125_G4_ab_12_13_port, c =>
n3635, d => n2272, outb => n3634);
U2170 : inv port map( inb => mult_125_G4_ab_13_13_port, outb => n3636);
U2171 : oai22 port map( a => n3634, b => n3636, c => n422, d => n2275, outb
=> n425);
U2172 : aoi22 port map( a => n425, b => mult_125_G4_ab_14_13_port, c =>
n3638, d => n2278, outb => n3637);
U2173 : nand2 port map( a => mult_125_G4_ab_0_13_port, b =>
mult_125_G4_ab_1_12_port, outb => n430);
U2174 : aoi22 port map( a => mult_125_G4_ab_2_12_port, b => n3640, c => n428
, d => n2243, outb => n3639);
U2175 : oai22 port map( a => n3639, b => n3641, c => n431, d => n2244, outb
=> n434);
U2176 : aoi22 port map( a => n434, b => mult_125_G4_ab_4_12_port, c => n3643
, d => n2286, outb => n3642);
U2177 : aoi22 port map( a => n436, b => mult_125_G4_ab_5_12_port, c => n3645
, d => n2246, outb => n3644);
U2178 : inv port map( inb => mult_125_G4_ab_6_12_port, outb => n3646);
U2179 : oai22 port map( a => n3644, b => n3646, c => n437, d => n2249, outb
=> n440);
U2180 : aoi22 port map( a => n440, b => mult_125_G4_ab_7_12_port, c => n3648
, d => n2252, outb => n3647);
U2181 : inv port map( inb => mult_125_G4_ab_8_12_port, outb => n3649);
U2182 : oai22 port map( a => n3647, b => n3649, c => n441, d => n2255, outb
=> n444);
U2183 : aoi22 port map( a => n444, b => mult_125_G4_ab_9_12_port, c => n3651
, d => n2258, outb => n3650);
U2184 : inv port map( inb => mult_125_G4_ab_10_12_port, outb => n3652);
U2185 : oai22 port map( a => n3650, b => n3652, c => n445, d => n2261, outb
=> n448);
U2186 : aoi22 port map( a => n448, b => mult_125_G4_ab_11_12_port, c =>
n3654, d => n2264, outb => n3653);
U2187 : inv port map( inb => mult_125_G4_ab_12_12_port, outb => n3655);
U2188 : oai22 port map( a => n3653, b => n3655, c => n449, d => n2267, outb
=> n452);
U2189 : aoi22 port map( a => n452, b => mult_125_G4_ab_13_12_port, c =>
n3657, d => n2270, outb => n3656);
U2190 : inv port map( inb => mult_125_G4_ab_14_12_port, outb => n3658);
U2191 : oai22 port map( a => n3656, b => n3658, c => n453, d => n2273, outb
=> n456);
U2192 : nand2 port map( a => mult_125_G4_ab_0_12_port, b =>
mult_125_G4_ab_1_11_port, outb => n459);
U2193 : aoi22 port map( a => mult_125_G4_ab_2_11_port, b => n3659, c => n457
, d => n2281, outb => n462);
U2194 : oai22 port map( a => n462, b => n461, c => n3660, d => n2282, outb
=> n464);
U2195 : oai22 port map( a => n3661, b => n3662, c => n463, d => n2292, outb
=> n466);
U2196 : aoi22 port map( a => n466, b => mult_125_G4_ab_5_11_port, c => n3664
, d => n2284, outb => n3663);
U2197 : oai22 port map( a => n3663, b => n3665, c => n467, d => n2295, outb
=> n470);
U2198 : oai22 port map( a => n3666, b => n3667, c => n469, d => n2298, outb
=> n472);
U2199 : aoi22 port map( a => n472, b => mult_125_G4_ab_8_11_port, c => n3669
, d => n2301, outb => n3668);
U2200 : inv port map( inb => mult_125_G4_ab_9_11_port, outb => n3670);
U2201 : oai22 port map( a => n3668, b => n3670, c => n473, d => n2304, outb
=> n476);
U2202 : aoi22 port map( a => n476, b => mult_125_G4_ab_10_11_port, c =>
n3672, d => n2307, outb => n3671);
U2203 : inv port map( inb => mult_125_G4_ab_11_11_port, outb => n3673);
U2204 : oai22 port map( a => n3671, b => n3673, c => n477, d => n2310, outb
=> n480);
U2205 : aoi22 port map( a => n480, b => mult_125_G4_ab_12_11_port, c =>
n3675, d => n2313, outb => n3674);
U2206 : inv port map( inb => mult_125_G4_ab_13_11_port, outb => n3676);
U2207 : oai22 port map( a => n3674, b => n3676, c => n481, d => n2316, outb
=> n484);
U2208 : aoi22 port map( a => n484, b => mult_125_G4_ab_14_11_port, c =>
n3677, d => n2319, outb => n487);
U2209 : nand2 port map( a => mult_125_G4_ab_0_11_port, b =>
mult_125_G4_ab_1_10_port, outb => n490);
U2210 : aoi22 port map( a => mult_125_G4_ab_2_10_port, b => n3679, c => n488
, d => n2287, outb => n3678);
U2211 : oai22 port map( a => n3678, b => n3680, c => n491, d => n2288, outb
=> n494);
U2212 : aoi22 port map( a => n494, b => mult_125_G4_ab_4_10_port, c => n3681
, d => n2327, outb => n497);
U2213 : oai22 port map( a => n497, b => n496, c => n3682, d => n2290, outb
=> n499);
U2214 : aoi22 port map( a => n499, b => mult_125_G4_ab_6_10_port, c => n3684
, d => n2330, outb => n3683);
U2215 : oai22 port map( a => n3683, b => n3685, c => n500, d => n2293, outb
=> n503);
U2216 : inv port map( inb => mult_125_G4_ab_8_10_port, outb => n3686);
U2217 : oai22 port map( a => n3687, b => n3686, c => n502, d => n2296, outb
=> n505);
U2218 : aoi22 port map( a => n505, b => mult_125_G4_ab_9_10_port, c => n3689
, d => n2299, outb => n3688);
U2219 : inv port map( inb => mult_125_G4_ab_10_10_port, outb => n3690);
U2220 : oai22 port map( a => n3688, b => n3690, c => n506, d => n2302, outb
=> n509);
U2221 : aoi22 port map( a => n509, b => mult_125_G4_ab_11_10_port, c =>
n3692, d => n2305, outb => n3691);
U2222 : inv port map( inb => mult_125_G4_ab_12_10_port, outb => n3693);
U2223 : oai22 port map( a => n3691, b => n3693, c => n510, d => n2308, outb
=> n513);
U2224 : aoi22 port map( a => n513, b => mult_125_G4_ab_13_10_port, c =>
n3695, d => n2311, outb => n3694);
U2225 : inv port map( inb => mult_125_G4_ab_14_10_port, outb => n3696);
U2226 : oai22 port map( a => n3694, b => n3696, c => n514, d => n2314, outb
=> n517);
U2227 : nand2 port map( a => mult_125_G4_ab_0_10_port, b =>
mult_125_G4_ab_1_9_port, outb => n520);
U2228 : aoi22 port map( a => mult_125_G4_ab_2_9_port, b => n3698, c => n518,
d => n2322, outb => n3697);
U2229 : oai22 port map( a => n3697, b => n3699, c => n521, d => n2323, outb
=> n524);
U2230 : oai22 port map( a => n3700, b => n3701, c => n523, d => n2336, outb
=> n526);
U2231 : aoi22 port map( a => n526, b => mult_125_G4_ab_5_9_port, c => n3703,
d => n2325, outb => n3702);
U2232 : oai22 port map( a => n3702, b => n3704, c => n527, d => n2339, outb
=> n530);
U2233 : aoi22 port map( a => n530, b => mult_125_G4_ab_7_9_port, c => n3706,
d => n2328, outb => n3705);
U2234 : oai22 port map( a => n3705, b => n3707, c => n531, d => n2342, outb
=> n534);
U2235 : oai22 port map( a => n3708, b => n3709, c => n533, d => n2345, outb
=> n536);
U2236 : aoi22 port map( a => n536, b => mult_125_G4_ab_10_9_port, c => n3711
, d => n2348, outb => n3710);
U2237 : inv port map( inb => mult_125_G4_ab_11_9_port, outb => n3712);
U2238 : oai22 port map( a => n3710, b => n3712, c => n537, d => n2351, outb
=> n540);
U2239 : aoi22 port map( a => n540, b => mult_125_G4_ab_12_9_port, c => n3714
, d => n2354, outb => n3713);
U2240 : inv port map( inb => mult_125_G4_ab_13_9_port, outb => n3715);
U2241 : oai22 port map( a => n3713, b => n3715, c => n541, d => n2357, outb
=> n544);
U2242 : aoi22 port map( a => n544, b => mult_125_G4_ab_14_9_port, c => n3716
, d => n2360, outb => n547);
U2243 : nand2 port map( a => mult_125_G4_ab_0_9_port, b =>
mult_125_G4_ab_1_8_port, outb => n550);
U2244 : aoi22 port map( a => mult_125_G4_ab_2_8_port, b => n3718, c => n548,
d => n2331, outb => n3717);
U2245 : oai22 port map( a => n3717, b => n3719, c => n551, d => n2332, outb
=> n554);
U2246 : oai22 port map( a => n3720, b => n3721, c => n553, d => n2368, outb
=> n556);
U2247 : oai22 port map( a => n3722, b => n3723, c => n555, d => n2334, outb
=> n558);
U2248 : aoi22 port map( a => n558, b => mult_125_G4_ab_6_8_port, c => n3725,
d => n2371, outb => n3724);
U2249 : oai22 port map( a => n3724, b => n3726, c => n559, d => n2337, outb
=> n562);
U2250 : aoi22 port map( a => n562, b => mult_125_G4_ab_8_8_port, c => n3728,
d => n2374, outb => n3727);
U2251 : oai22 port map( a => n3727, b => n3729, c => n563, d => n2340, outb
=> n566);
U2252 : inv port map( inb => mult_125_G4_ab_10_8_port, outb => n3730);
U2253 : oai22 port map( a => n3731, b => n3730, c => n565, d => n2343, outb
=> n568);
U2254 : aoi22 port map( a => n568, b => mult_125_G4_ab_11_8_port, c => n3733
, d => n2346, outb => n3732);
U2255 : inv port map( inb => mult_125_G4_ab_12_8_port, outb => n3734);
U2256 : oai22 port map( a => n3732, b => n3734, c => n569, d => n2349, outb
=> n572);
U2257 : aoi22 port map( a => n572, b => mult_125_G4_ab_13_8_port, c => n3736
, d => n2352, outb => n3735);
U2258 : inv port map( inb => mult_125_G4_ab_14_8_port, outb => n3737);
U2259 : oai22 port map( a => n3735, b => n3737, c => n573, d => n2355, outb
=> n576);
U2260 : nand2 port map( a => mult_125_G4_ab_0_8_port, b =>
mult_125_G4_ab_1_7_port, outb => n579);
U2261 : aoi22 port map( a => mult_125_G4_ab_2_7_port, b => n3738, c => n577,
d => n2363, outb => n582);
U2262 : oai22 port map( a => n582, b => n581, c => n3739, d => n2364, outb
=> n584);
U2263 : oai22 port map( a => n3740, b => n3741, c => n583, d => n2380, outb
=> n586);
U2264 : aoi22 port map( a => n586, b => mult_125_G4_ab_5_7_port, c => n3743,
d => n2366, outb => n3742);
U2265 : oai22 port map( a => n3742, b => n3744, c => n587, d => n2383, outb
=> n590);
U2266 : aoi22 port map( a => n590, b => mult_125_G4_ab_7_7_port, c => n3746,
d => n2369, outb => n3745);
U2267 : oai22 port map( a => n3745, b => n3747, c => n591, d => n2386, outb
=> n594);
U2268 : aoi22 port map( a => n594, b => mult_125_G4_ab_9_7_port, c => n3749,
d => n2372, outb => n3748);
U2269 : oai22 port map( a => n3748, b => n3750, c => n595, d => n2389, outb
=> n598);
U2270 : oai22 port map( a => n3751, b => n3752, c => n597, d => n2392, outb
=> n600);
U2271 : aoi22 port map( a => n600, b => mult_125_G4_ab_12_7_port, c => n3754
, d => n2395, outb => n3753);
U2272 : inv port map( inb => mult_125_G4_ab_13_7_port, outb => n3755);
U2273 : oai22 port map( a => n3753, b => n3755, c => n601, d => n2398, outb
=> n604);
U2274 : aoi22 port map( a => n604, b => mult_125_G4_ab_14_7_port, c => n3756
, d => n2401, outb => n607);
U2275 : nand2 port map( a => mult_125_G4_ab_0_7_port, b =>
mult_125_G4_ab_1_6_port, outb => n610);
U2276 : aoi22 port map( a => mult_125_G4_ab_2_6_port, b => n3758, c => n608,
d => n2375, outb => n3757);
U2277 : oai22 port map( a => n3757, b => n3759, c => n611, d => n2376, outb
=> n614);
U2278 : aoi22 port map( a => n614, b => mult_125_G4_ab_4_6_port, c => n3760,
d => n2409, outb => n617);
U2279 : oai22 port map( a => n617, b => n616, c => n3761, d => n2378, outb
=> n619);
U2280 : aoi22 port map( a => n619, b => mult_125_G4_ab_6_6_port, c => n3763,
d => n2412, outb => n3762);
U2281 : oai22 port map( a => n3762, b => n3764, c => n620, d => n2381, outb
=> n623);
U2282 : aoi22 port map( a => n623, b => mult_125_G4_ab_8_6_port, c => n3765,
d => n2415, outb => n626);
U2283 : oai22 port map( a => n626, b => n625, c => n3766, d => n2384, outb
=> n628);
U2284 : aoi22 port map( a => n628, b => mult_125_G4_ab_10_6_port, c => n3768
, d => n2418, outb => n3767);
U2285 : oai22 port map( a => n3767, b => n3769, c => n629, d => n2387, outb
=> n632);
U2286 : inv port map( inb => mult_125_G4_ab_12_6_port, outb => n3770);
U2287 : oai22 port map( a => n3771, b => n3770, c => n631, d => n2390, outb
=> n634);
U2288 : aoi22 port map( a => n634, b => mult_125_G4_ab_13_6_port, c => n3773
, d => n2393, outb => n3772);
U2289 : inv port map( inb => mult_125_G4_ab_14_6_port, outb => n3774);
U2290 : oai22 port map( a => n3772, b => n3774, c => n635, d => n2396, outb
=> n638);
U2291 : nand2 port map( a => mult_125_G4_ab_0_6_port, b =>
mult_125_G4_ab_1_5_port, outb => n641);
U2292 : aoi22 port map( a => mult_125_G4_ab_2_5_port, b => n3775, c => n639,
d => n2404, outb => n644);
U2293 : oai22 port map( a => n644, b => n643, c => n3776, d => n2405, outb
=> n646);
U2294 : oai22 port map( a => n3777, b => n3778, c => n645, d => n2424, outb
=> n648);
U2295 : aoi22 port map( a => n648, b => mult_125_G4_ab_5_5_port, c => n3779,
d => n2407, outb => n651);
U2296 : oai22 port map( a => n651, b => n650, c => n3780, d => n2427, outb
=> n653);
U2297 : aoi22 port map( a => n653, b => mult_125_G4_ab_7_5_port, c => n3782,
d => n2410, outb => n3781);
U2298 : oai22 port map( a => n3781, b => n3783, c => n654, d => n2430, outb
=> n657);
U2299 : aoi22 port map( a => n657, b => mult_125_G4_ab_9_5_port, c => n3785,
d => n2413, outb => n3784);
U2300 : oai22 port map( a => n3784, b => n3786, c => n658, d => n2433, outb
=> n661);
U2301 : aoi22 port map( a => n661, b => mult_125_G4_ab_11_5_port, c => n3788
, d => n2416, outb => n3787);
U2302 : oai22 port map( a => n3787, b => n3789, c => n662, d => n2436, outb
=> n665);
U2303 : oai22 port map( a => n3790, b => n3791, c => n664, d => n2439, outb
=> n667);
U2304 : aoi22 port map( a => n667, b => mult_125_G4_ab_14_5_port, c => n3792
, d => n2442, outb => n670);
U2305 : nand2 port map( a => mult_125_G4_ab_0_5_port, b =>
mult_125_G4_ab_1_4_port, outb => n673);
U2306 : aoi22 port map( a => mult_125_G4_ab_2_4_port, b => n3794, c => n671,
d => n2419, outb => n3793);
U2307 : oai22 port map( a => n3793, b => n3795, c => n674, d => n2420, outb
=> n677);
U2308 : aoi22 port map( a => n677, b => mult_125_G4_ab_4_4_port, c => n3796,
d => n2450, outb => n680);
U2309 : oai22 port map( a => n680, b => n679, c => n3797, d => n2422, outb
=> n682);
U2310 : aoi22 port map( a => n682, b => mult_125_G4_ab_6_4_port, c => n3798,
d => n2453, outb => n685);
U2311 : oai22 port map( a => n685, b => n684, c => n3799, d => n2425, outb
=> n687);
U2312 : aoi22 port map( a => n687, b => mult_125_G4_ab_8_4_port, c => n3801,
d => n2456, outb => n3800);
U2313 : oai22 port map( a => n3800, b => n3802, c => n688, d => n2428, outb
=> n691);
U2314 : aoi22 port map( a => n691, b => mult_125_G4_ab_10_4_port, c => n3803
, d => n2459, outb => n694);
U2315 : oai22 port map( a => n694, b => n693, c => n3804, d => n2431, outb
=> n696);
U2316 : aoi22 port map( a => n696, b => mult_125_G4_ab_12_4_port, c => n3806
, d => n2462, outb => n3805);
U2317 : oai22 port map( a => n3805, b => n3807, c => n697, d => n2434, outb
=> n700);
U2318 : aoi22 port map( a => n700, b => mult_125_G4_ab_14_4_port, c => n3808
, d => n2437, outb => n703);
U2319 : nand2 port map( a => mult_125_G4_ab_0_4_port, b =>
mult_125_G4_ab_1_3_port, outb => n706);
U2320 : aoi22 port map( a => mult_125_G4_ab_2_3_port, b => n3809, c => n704,
d => n2445, outb => n709);
U2321 : oai22 port map( a => n709, b => n708, c => n3810, d => n2446, outb
=> n711);
U2322 : oai22 port map( a => n3811, b => n3812, c => n710, d => n2468, outb
=> n713);
U2323 : aoi22 port map( a => n713, b => mult_125_G4_ab_5_3_port, c => n3814,
d => n2448, outb => n3813);
U2324 : oai22 port map( a => n3813, b => n3815, c => n714, d => n2471, outb
=> n717);
U2325 : aoi22 port map( a => n717, b => mult_125_G4_ab_7_3_port, c => n3817,
d => n2451, outb => n3816);
U2326 : oai22 port map( a => n3816, b => n3818, c => n718, d => n2474, outb
=> n721);
U2327 : aoi22 port map( a => n721, b => mult_125_G4_ab_9_3_port, c => n3820,
d => n2454, outb => n3819);
U2328 : oai22 port map( a => n3819, b => n3821, c => n722, d => n2477, outb
=> n725);
U2329 : aoi22 port map( a => n725, b => mult_125_G4_ab_11_3_port, c => n3823
, d => n2457, outb => n3822);
U2330 : oai22 port map( a => n3822, b => n3824, c => n726, d => n2480, outb
=> n729);
U2331 : aoi22 port map( a => n729, b => mult_125_G4_ab_13_3_port, c => n3826
, d => n2460, outb => n3825);
U2332 : inv port map( inb => mult_125_G4_ab_14_3_port, outb => n3827);
U2333 : oai22 port map( a => n3825, b => n3827, c => n730, d => n2483, outb
=> n733);
U2334 : nand2 port map( a => mult_125_G4_ab_0_3_port, b =>
mult_125_G4_ab_1_2_port, outb => n736);
U2335 : aoi22 port map( a => mult_125_G4_ab_2_2_port, b => n3829, c => n734,
d => n2463, outb => n3828);
U2336 : oai22 port map( a => n3828, b => n3830, c => n737, d => n2464, outb
=> n740);
U2337 : aoi22 port map( a => n740, b => mult_125_G4_ab_4_2_port, c => n3832,
d => n2491, outb => n3831);
U2338 : oai22 port map( a => n3831, b => n3833, c => n741, d => n2466, outb
=> n744);
U2339 : aoi22 port map( a => n744, b => mult_125_G4_ab_6_2_port, c => n3834,
d => n2494, outb => n747);
U2340 : oai22 port map( a => n747, b => n746, c => n3835, d => n2469, outb
=> n749);
U2341 : aoi22 port map( a => n749, b => mult_125_G4_ab_8_2_port, c => n3837,
d => n2497, outb => n3836);
U2342 : oai22 port map( a => n3836, b => n3838, c => n750, d => n2472, outb
=> n753);
U2343 : aoi22 port map( a => n753, b => mult_125_G4_ab_10_2_port, c => n3840
, d => n2500, outb => n3839);
U2344 : oai22 port map( a => n3839, b => n3841, c => n754, d => n2475, outb
=> n757);
U2345 : aoi22 port map( a => n757, b => mult_125_G4_ab_12_2_port, c => n3843
, d => n2503, outb => n3842);
U2346 : oai22 port map( a => n3842, b => n3844, c => n758, d => n2478, outb
=> n761);
U2347 : aoi22 port map( a => n761, b => mult_125_G4_ab_14_2_port, c => n3846
, d => n2506, outb => n3845);
U2348 : nand2 port map( a => mult_125_G4_ab_0_2_port, b =>
mult_125_G4_ab_1_1_port, outb => n766);
U2349 : aoi22 port map( a => mult_125_G4_ab_2_1_port, b => n3848, c => n764,
d => n2486, outb => n3847);
U2350 : oai22 port map( a => n3847, b => n3849, c => n767, d => n2487, outb
=> n770);
U2351 : inv port map( inb => mult_125_G4_ab_4_1_port, outb => n3850);
U2352 : oai22 port map( a => n3851, b => n3850, c => n769, d => n2512, outb
=> n772);
U2353 : aoi22 port map( a => n772, b => mult_125_G4_ab_5_1_port, c => n3853,
d => n2489, outb => n3852);
U2354 : oai22 port map( a => n3852, b => n3854, c => n773, d => n2515, outb
=> n776);
U2355 : aoi22 port map( a => n776, b => mult_125_G4_ab_7_1_port, c => n3856,
d => n2492, outb => n3855);
U2356 : oai22 port map( a => n3855, b => n3857, c => n777, d => n2518, outb
=> n780);
U2357 : aoi22 port map( a => n780, b => mult_125_G4_ab_9_1_port, c => n3859,
d => n2495, outb => n3858);
U2358 : oai22 port map( a => n3858, b => n3860, c => n781, d => n2521, outb
=> n784);
U2359 : aoi22 port map( a => n784, b => mult_125_G4_ab_11_1_port, c => n3862
, d => n2498, outb => n3861);
U2360 : oai22 port map( a => n3861, b => n3863, c => n785, d => n2524, outb
=> n788);
U2361 : aoi22 port map( a => n788, b => mult_125_G4_ab_13_1_port, c => n3865
, d => n2501, outb => n3864);
U2362 : inv port map( inb => mult_125_G4_ab_14_1_port, outb => n3866);
U2363 : oai22 port map( a => n3864, b => n3866, c => n789, d => n2527, outb
=> n792);
U2364 : nand2 port map( a => mult_125_G4_ab_1_0_port, b =>
mult_125_G4_ab_0_1_port, outb => n3867);
U2365 : aoi22 port map( a => mult_125_G4_ab_2_0_port, b => n794, c => n3869,
d => n2507, outb => n3868);
U2366 : aoi22 port map( a => n796, b => mult_125_G4_ab_3_0_port, c => n3871,
d => n2508, outb => n3870);
U2367 : inv port map( inb => mult_125_G4_ab_4_0_port, outb => n3872);
U2368 : oai22 port map( a => n3870, b => n3872, c => n797, d => n3873, outb
=> n800);
U2369 : aoi22 port map( a => n800, b => mult_125_G4_ab_5_0_port, c => n3875,
d => n2510, outb => n3874);
U2370 : inv port map( inb => mult_125_G4_ab_6_0_port, outb => n3876);
U2371 : oai22 port map( a => n3874, b => n3876, c => n801, d => n3877, outb
=> n804);
U2372 : aoi22 port map( a => n804, b => mult_125_G4_ab_7_0_port, c => n3879,
d => n2513, outb => n3878);
U2373 : inv port map( inb => mult_125_G4_ab_8_0_port, outb => n3880);
U2374 : oai22 port map( a => n3878, b => n3880, c => n805, d => n3881, outb
=> n808);
U2375 : aoi22 port map( a => n808, b => mult_125_G4_ab_9_0_port, c => n3883,
d => n2516, outb => n3882);
U2376 : inv port map( inb => mult_125_G4_ab_10_0_port, outb => n3884);
U2377 : oai22 port map( a => n3882, b => n3884, c => n809, d => n3885, outb
=> n812);
U2378 : aoi22 port map( a => n812, b => mult_125_G4_ab_11_0_port, c => n3887
, d => n2519, outb => n3886);
U2379 : inv port map( inb => mult_125_G4_ab_12_0_port, outb => n3888);
U2380 : oai22 port map( a => n3886, b => n3888, c => n813, d => n3889, outb
=> n816);
U2381 : aoi22 port map( a => n816, b => mult_125_G4_ab_13_0_port, c => n3891
, d => n2522, outb => n3890);
U2382 : inv port map( inb => mult_125_G4_ab_14_0_port, outb => n3892);
U2383 : oai22 port map( a => n3890, b => n3892, c => n817, d => n3893, outb
=> n820);
U2384 : inv port map( inb => mult_125_G4_ZB, outb => n272);
U2385 : inv port map( inb => mult_125_G4_ZA, outb => n273);
U2386 : nand2 port map( a => mult_125_G3_ab_0_15_port, b =>
mult_125_G3_ab_1_14_port, outb => n3894);
U2387 : inv port map( inb => mult_125_G3_ab_3_15_port, outb => n3895);
U2388 : inv port map( inb => mult_125_G3_ab_4_14_port, outb => n3896);
U2389 : inv port map( inb => mult_125_G3_ab_5_15_port, outb => n3897);
U2390 : inv port map( inb => mult_125_G3_ab_6_14_port, outb => n3898);
U2391 : inv port map( inb => mult_125_G3_ab_7_15_port, outb => n3899);
U2392 : inv port map( inb => mult_125_G3_ab_8_14_port, outb => n3900);
U2393 : inv port map( inb => mult_125_G3_ab_9_15_port, outb => n3901);
U2394 : inv port map( inb => mult_125_G3_ab_10_14_port, outb => n3902);
U2395 : inv port map( inb => mult_125_G3_ab_11_15_port, outb => n3903);
U2396 : inv port map( inb => mult_125_G3_ab_12_14_port, outb => n3904);
U2397 : nand2 port map( a => mult_125_G3_ab_0_14_port, b =>
mult_125_G3_ab_1_13_port, outb => n838);
U2398 : aoi22 port map( a => mult_125_G3_ab_2_13_port, b => n3905, c => n836
, d => n2537, outb => n841);
U2399 : oai22 port map( a => n841, b => n840, c => n3906, d => n2538, outb
=> n843);
U2400 : aoi22 port map( a => n843, b => mult_125_G3_ab_4_13_port, c => n3908
, d => n2545, outb => n3907);
U2401 : oai22 port map( a => n3907, b => n3909, c => n844, d => n2548, outb
=> n847);
U2402 : aoi22 port map( a => n847, b => mult_125_G3_ab_6_13_port, c => n3911
, d => n2551, outb => n3910);
U2403 : inv port map( inb => mult_125_G3_ab_7_13_port, outb => n3912);
U2404 : oai22 port map( a => n3910, b => n3912, c => n848, d => n2554, outb
=> n851);
U2405 : aoi22 port map( a => n851, b => mult_125_G3_ab_8_13_port, c => n3914
, d => n2557, outb => n3913);
U2406 : inv port map( inb => mult_125_G3_ab_9_13_port, outb => n3915);
U2407 : oai22 port map( a => n3913, b => n3915, c => n852, d => n2560, outb
=> n855);
U2408 : aoi22 port map( a => n855, b => mult_125_G3_ab_10_13_port, c =>
n3917, d => n2563, outb => n3916);
U2409 : inv port map( inb => mult_125_G3_ab_11_13_port, outb => n3918);
U2410 : oai22 port map( a => n3916, b => n3918, c => n856, d => n2566, outb
=> n859);
U2411 : aoi22 port map( a => n859, b => mult_125_G3_ab_12_13_port, c =>
n3920, d => n2569, outb => n3919);
U2412 : inv port map( inb => mult_125_G3_ab_13_13_port, outb => n3921);
U2413 : oai22 port map( a => n3919, b => n3921, c => n860, d => n2572, outb
=> n863);
U2414 : aoi22 port map( a => n863, b => mult_125_G3_ab_14_13_port, c =>
n3923, d => n2575, outb => n3922);
U2415 : nand2 port map( a => mult_125_G3_ab_0_13_port, b =>
mult_125_G3_ab_1_12_port, outb => n868);
U2416 : aoi22 port map( a => mult_125_G3_ab_2_12_port, b => n3925, c => n866
, d => n2540, outb => n3924);
U2417 : oai22 port map( a => n3924, b => n3926, c => n869, d => n2541, outb
=> n872);
U2418 : aoi22 port map( a => n872, b => mult_125_G3_ab_4_12_port, c => n3928
, d => n2583, outb => n3927);
U2419 : aoi22 port map( a => n874, b => mult_125_G3_ab_5_12_port, c => n3930
, d => n2543, outb => n3929);
U2420 : inv port map( inb => mult_125_G3_ab_6_12_port, outb => n3931);
U2421 : oai22 port map( a => n3929, b => n3931, c => n875, d => n2546, outb
=> n878);
U2422 : aoi22 port map( a => n878, b => mult_125_G3_ab_7_12_port, c => n3933
, d => n2549, outb => n3932);
U2423 : inv port map( inb => mult_125_G3_ab_8_12_port, outb => n3934);
U2424 : oai22 port map( a => n3932, b => n3934, c => n879, d => n2552, outb
=> n882);
U2425 : aoi22 port map( a => n882, b => mult_125_G3_ab_9_12_port, c => n3936
, d => n2555, outb => n3935);
U2426 : inv port map( inb => mult_125_G3_ab_10_12_port, outb => n3937);
U2427 : oai22 port map( a => n3935, b => n3937, c => n883, d => n2558, outb
=> n886);
U2428 : aoi22 port map( a => n886, b => mult_125_G3_ab_11_12_port, c =>
n3939, d => n2561, outb => n3938);
U2429 : inv port map( inb => mult_125_G3_ab_12_12_port, outb => n3940);
U2430 : oai22 port map( a => n3938, b => n3940, c => n887, d => n2564, outb
=> n890);
U2431 : aoi22 port map( a => n890, b => mult_125_G3_ab_13_12_port, c =>
n3942, d => n2567, outb => n3941);
U2432 : inv port map( inb => mult_125_G3_ab_14_12_port, outb => n3943);
U2433 : oai22 port map( a => n3941, b => n3943, c => n891, d => n2570, outb
=> n894);
U2434 : nand2 port map( a => mult_125_G3_ab_0_12_port, b =>
mult_125_G3_ab_1_11_port, outb => n897);
U2435 : aoi22 port map( a => mult_125_G3_ab_2_11_port, b => n3944, c => n895
, d => n2578, outb => n900);
U2436 : oai22 port map( a => n900, b => n899, c => n3945, d => n2579, outb
=> n902);
U2437 : oai22 port map( a => n3946, b => n3947, c => n901, d => n2589, outb
=> n904);
U2438 : aoi22 port map( a => n904, b => mult_125_G3_ab_5_11_port, c => n3949
, d => n2581, outb => n3948);
U2439 : oai22 port map( a => n3948, b => n3950, c => n905, d => n2592, outb
=> n908);
U2440 : oai22 port map( a => n3951, b => n3952, c => n907, d => n2595, outb
=> n910);
U2441 : aoi22 port map( a => n910, b => mult_125_G3_ab_8_11_port, c => n3954
, d => n2598, outb => n3953);
U2442 : inv port map( inb => mult_125_G3_ab_9_11_port, outb => n3955);
U2443 : oai22 port map( a => n3953, b => n3955, c => n911, d => n2601, outb
=> n914);
U2444 : aoi22 port map( a => n914, b => mult_125_G3_ab_10_11_port, c =>
n3957, d => n2604, outb => n3956);
U2445 : inv port map( inb => mult_125_G3_ab_11_11_port, outb => n3958);
U2446 : oai22 port map( a => n3956, b => n3958, c => n915, d => n2607, outb
=> n918);
U2447 : aoi22 port map( a => n918, b => mult_125_G3_ab_12_11_port, c =>
n3960, d => n2610, outb => n3959);
U2448 : inv port map( inb => mult_125_G3_ab_13_11_port, outb => n3961);
U2449 : oai22 port map( a => n3959, b => n3961, c => n919, d => n2613, outb
=> n922);
U2450 : aoi22 port map( a => n922, b => mult_125_G3_ab_14_11_port, c =>
n3962, d => n2616, outb => n925);
U2451 : nand2 port map( a => mult_125_G3_ab_0_11_port, b =>
mult_125_G3_ab_1_10_port, outb => n928);
U2452 : aoi22 port map( a => mult_125_G3_ab_2_10_port, b => n3964, c => n926
, d => n2584, outb => n3963);
U2453 : oai22 port map( a => n3963, b => n3965, c => n929, d => n2585, outb
=> n932);
U2454 : aoi22 port map( a => n932, b => mult_125_G3_ab_4_10_port, c => n3966
, d => n2624, outb => n935);
U2455 : oai22 port map( a => n935, b => n934, c => n3967, d => n2587, outb
=> n937);
U2456 : aoi22 port map( a => n937, b => mult_125_G3_ab_6_10_port, c => n3969
, d => n2627, outb => n3968);
U2457 : oai22 port map( a => n3968, b => n3970, c => n938, d => n2590, outb
=> n941);
U2458 : inv port map( inb => mult_125_G3_ab_8_10_port, outb => n3971);
U2459 : oai22 port map( a => n3972, b => n3971, c => n940, d => n2593, outb
=> n943);
U2460 : aoi22 port map( a => n943, b => mult_125_G3_ab_9_10_port, c => n3974
, d => n2596, outb => n3973);
U2461 : inv port map( inb => mult_125_G3_ab_10_10_port, outb => n3975);
U2462 : oai22 port map( a => n3973, b => n3975, c => n944, d => n2599, outb
=> n947);
U2463 : aoi22 port map( a => n947, b => mult_125_G3_ab_11_10_port, c =>
n3977, d => n2602, outb => n3976);
U2464 : inv port map( inb => mult_125_G3_ab_12_10_port, outb => n3978);
U2465 : oai22 port map( a => n3976, b => n3978, c => n948, d => n2605, outb
=> n951);
U2466 : aoi22 port map( a => n951, b => mult_125_G3_ab_13_10_port, c =>
n3980, d => n2608, outb => n3979);
U2467 : inv port map( inb => mult_125_G3_ab_14_10_port, outb => n3981);
U2468 : oai22 port map( a => n3979, b => n3981, c => n952, d => n2611, outb
=> n955);
U2469 : nand2 port map( a => mult_125_G3_ab_0_10_port, b =>
mult_125_G3_ab_1_9_port, outb => n958);
U2470 : aoi22 port map( a => mult_125_G3_ab_2_9_port, b => n3983, c => n956,
d => n2619, outb => n3982);
U2471 : oai22 port map( a => n3982, b => n3984, c => n959, d => n2620, outb
=> n962);
U2472 : oai22 port map( a => n3985, b => n3986, c => n961, d => n2633, outb
=> n964);
U2473 : aoi22 port map( a => n964, b => mult_125_G3_ab_5_9_port, c => n3988,
d => n2622, outb => n3987);
U2474 : oai22 port map( a => n3987, b => n3989, c => n965, d => n2636, outb
=> n968);
U2475 : aoi22 port map( a => n968, b => mult_125_G3_ab_7_9_port, c => n3991,
d => n2625, outb => n3990);
U2476 : oai22 port map( a => n3990, b => n3992, c => n969, d => n2639, outb
=> n972);
U2477 : oai22 port map( a => n3993, b => n3994, c => n971, d => n2642, outb
=> n974);
U2478 : aoi22 port map( a => n974, b => mult_125_G3_ab_10_9_port, c => n3996
, d => n2645, outb => n3995);
U2479 : inv port map( inb => mult_125_G3_ab_11_9_port, outb => n3997);
U2480 : oai22 port map( a => n3995, b => n3997, c => n975, d => n2648, outb
=> n978);
U2481 : aoi22 port map( a => n978, b => mult_125_G3_ab_12_9_port, c => n3999
, d => n2651, outb => n3998);
U2482 : inv port map( inb => mult_125_G3_ab_13_9_port, outb => n4000);
U2483 : oai22 port map( a => n3998, b => n4000, c => n979, d => n2654, outb
=> n982);
U2484 : aoi22 port map( a => n982, b => mult_125_G3_ab_14_9_port, c => n4001
, d => n2657, outb => n985);
U2485 : nand2 port map( a => mult_125_G3_ab_0_9_port, b =>
mult_125_G3_ab_1_8_port, outb => n988);
U2486 : aoi22 port map( a => mult_125_G3_ab_2_8_port, b => n4003, c => n986,
d => n2628, outb => n4002);
U2487 : oai22 port map( a => n4002, b => n4004, c => n989, d => n2629, outb
=> n992);
U2488 : oai22 port map( a => n4005, b => n4006, c => n991, d => n2665, outb
=> n994);
U2489 : oai22 port map( a => n4007, b => n4008, c => n993, d => n2631, outb
=> n996);
U2490 : aoi22 port map( a => n996, b => mult_125_G3_ab_6_8_port, c => n4010,
d => n2668, outb => n4009);
U2491 : oai22 port map( a => n4009, b => n4011, c => n997, d => n2634, outb
=> n1000);
U2492 : aoi22 port map( a => n1000, b => mult_125_G3_ab_8_8_port, c => n4013
, d => n2671, outb => n4012);
U2493 : oai22 port map( a => n4012, b => n4014, c => n1001, d => n2637, outb
=> n1004);
U2494 : inv port map( inb => mult_125_G3_ab_10_8_port, outb => n4015);
U2495 : oai22 port map( a => n4016, b => n4015, c => n1003, d => n2640, outb
=> n1006);
U2496 : aoi22 port map( a => n1006, b => mult_125_G3_ab_11_8_port, c =>
n4018, d => n2643, outb => n4017);
U2497 : inv port map( inb => mult_125_G3_ab_12_8_port, outb => n4019);
U2498 : oai22 port map( a => n4017, b => n4019, c => n1007, d => n2646, outb
=> n1010);
U2499 : aoi22 port map( a => n1010, b => mult_125_G3_ab_13_8_port, c =>
n4021, d => n2649, outb => n4020);
U2500 : inv port map( inb => mult_125_G3_ab_14_8_port, outb => n4022);
U2501 : oai22 port map( a => n4020, b => n4022, c => n1011, d => n2652, outb
=> n1014);
U2502 : nand2 port map( a => mult_125_G3_ab_0_8_port, b =>
mult_125_G3_ab_1_7_port, outb => n1017);
U2503 : aoi22 port map( a => mult_125_G3_ab_2_7_port, b => n4023, c => n1015
, d => n2660, outb => n1020);
U2504 : oai22 port map( a => n1020, b => n1019, c => n4024, d => n2661, outb
=> n1022);
U2505 : oai22 port map( a => n4025, b => n4026, c => n1021, d => n2677, outb
=> n1024);
U2506 : aoi22 port map( a => n1024, b => mult_125_G3_ab_5_7_port, c => n4028
, d => n2663, outb => n4027);
U2507 : oai22 port map( a => n4027, b => n4029, c => n1025, d => n2680, outb
=> n1028);
U2508 : aoi22 port map( a => n1028, b => mult_125_G3_ab_7_7_port, c => n4031
, d => n2666, outb => n4030);
U2509 : oai22 port map( a => n4030, b => n4032, c => n1029, d => n2683, outb
=> n1032);
U2510 : aoi22 port map( a => n1032, b => mult_125_G3_ab_9_7_port, c => n4034
, d => n2669, outb => n4033);
U2511 : oai22 port map( a => n4033, b => n4035, c => n1033, d => n2686, outb
=> n1036);
U2512 : oai22 port map( a => n4036, b => n4037, c => n1035, d => n2689, outb
=> n1038);
U2513 : aoi22 port map( a => n1038, b => mult_125_G3_ab_12_7_port, c =>
n4039, d => n2692, outb => n4038);
U2514 : inv port map( inb => mult_125_G3_ab_13_7_port, outb => n4040);
U2515 : oai22 port map( a => n4038, b => n4040, c => n1039, d => n2695, outb
=> n1042);
U2516 : aoi22 port map( a => n1042, b => mult_125_G3_ab_14_7_port, c =>
n4041, d => n2698, outb => n1045);
U2517 : nand2 port map( a => mult_125_G3_ab_0_7_port, b =>
mult_125_G3_ab_1_6_port, outb => n1048);
U2518 : aoi22 port map( a => mult_125_G3_ab_2_6_port, b => n4043, c => n1046
, d => n2672, outb => n4042);
U2519 : oai22 port map( a => n4042, b => n4044, c => n1049, d => n2673, outb
=> n1052);
U2520 : aoi22 port map( a => n1052, b => mult_125_G3_ab_4_6_port, c => n4045
, d => n2706, outb => n1055);
U2521 : oai22 port map( a => n1055, b => n1054, c => n4046, d => n2675, outb
=> n1057);
U2522 : aoi22 port map( a => n1057, b => mult_125_G3_ab_6_6_port, c => n4048
, d => n2709, outb => n4047);
U2523 : oai22 port map( a => n4047, b => n4049, c => n1058, d => n2678, outb
=> n1061);
U2524 : aoi22 port map( a => n1061, b => mult_125_G3_ab_8_6_port, c => n4050
, d => n2712, outb => n1064);
U2525 : oai22 port map( a => n1064, b => n1063, c => n4051, d => n2681, outb
=> n1066);
U2526 : aoi22 port map( a => n1066, b => mult_125_G3_ab_10_6_port, c =>
n4053, d => n2715, outb => n4052);
U2527 : oai22 port map( a => n4052, b => n4054, c => n1067, d => n2684, outb
=> n1070);
U2528 : inv port map( inb => mult_125_G3_ab_12_6_port, outb => n4055);
U2529 : oai22 port map( a => n4056, b => n4055, c => n1069, d => n2687, outb
=> n1072);
U2530 : aoi22 port map( a => n1072, b => mult_125_G3_ab_13_6_port, c =>
n4058, d => n2690, outb => n4057);
U2531 : inv port map( inb => mult_125_G3_ab_14_6_port, outb => n4059);
U2532 : oai22 port map( a => n4057, b => n4059, c => n1073, d => n2693, outb
=> n1076);
U2533 : nand2 port map( a => mult_125_G3_ab_0_6_port, b =>
mult_125_G3_ab_1_5_port, outb => n1079);
U2534 : aoi22 port map( a => mult_125_G3_ab_2_5_port, b => n4060, c => n1077
, d => n2701, outb => n1082);
U2535 : oai22 port map( a => n1082, b => n1081, c => n4061, d => n2702, outb
=> n1084);
U2536 : oai22 port map( a => n4062, b => n4063, c => n1083, d => n2721, outb
=> n1086);
U2537 : aoi22 port map( a => n1086, b => mult_125_G3_ab_5_5_port, c => n4064
, d => n2704, outb => n1089);
U2538 : oai22 port map( a => n1089, b => n1088, c => n4065, d => n2724, outb
=> n1091);
U2539 : aoi22 port map( a => n1091, b => mult_125_G3_ab_7_5_port, c => n4067
, d => n2707, outb => n4066);
U2540 : oai22 port map( a => n4066, b => n4068, c => n1092, d => n2727, outb
=> n1095);
U2541 : aoi22 port map( a => n1095, b => mult_125_G3_ab_9_5_port, c => n4070
, d => n2710, outb => n4069);
U2542 : oai22 port map( a => n4069, b => n4071, c => n1096, d => n2730, outb
=> n1099);
U2543 : aoi22 port map( a => n1099, b => mult_125_G3_ab_11_5_port, c =>
n4073, d => n2713, outb => n4072);
U2544 : oai22 port map( a => n4072, b => n4074, c => n1100, d => n2733, outb
=> n1103);
U2545 : oai22 port map( a => n4075, b => n4076, c => n1102, d => n2736, outb
=> n1105);
U2546 : aoi22 port map( a => n1105, b => mult_125_G3_ab_14_5_port, c =>
n4077, d => n2739, outb => n1108);
U2547 : nand2 port map( a => mult_125_G3_ab_0_5_port, b =>
mult_125_G3_ab_1_4_port, outb => n1111);
U2548 : aoi22 port map( a => mult_125_G3_ab_2_4_port, b => n4079, c => n1109
, d => n2716, outb => n4078);
U2549 : oai22 port map( a => n4078, b => n4080, c => n1112, d => n2717, outb
=> n1115);
U2550 : aoi22 port map( a => n1115, b => mult_125_G3_ab_4_4_port, c => n4081
, d => n2747, outb => n1118);
U2551 : oai22 port map( a => n1118, b => n1117, c => n4082, d => n2719, outb
=> n1120);
U2552 : aoi22 port map( a => n1120, b => mult_125_G3_ab_6_4_port, c => n4083
, d => n2750, outb => n1123);
U2553 : oai22 port map( a => n1123, b => n1122, c => n4084, d => n2722, outb
=> n1125);
U2554 : aoi22 port map( a => n1125, b => mult_125_G3_ab_8_4_port, c => n4086
, d => n2753, outb => n4085);
U2555 : oai22 port map( a => n4085, b => n4087, c => n1126, d => n2725, outb
=> n1129);
U2556 : aoi22 port map( a => n1129, b => mult_125_G3_ab_10_4_port, c =>
n4088, d => n2756, outb => n1132);
U2557 : oai22 port map( a => n1132, b => n1131, c => n4089, d => n2728, outb
=> n1134);
U2558 : aoi22 port map( a => n1134, b => mult_125_G3_ab_12_4_port, c =>
n4091, d => n2759, outb => n4090);
U2559 : oai22 port map( a => n4090, b => n4092, c => n1135, d => n2731, outb
=> n1138);
U2560 : aoi22 port map( a => n1138, b => mult_125_G3_ab_14_4_port, c =>
n4093, d => n2734, outb => n1141);
U2561 : nand2 port map( a => mult_125_G3_ab_0_4_port, b =>
mult_125_G3_ab_1_3_port, outb => n1144);
U2562 : aoi22 port map( a => mult_125_G3_ab_2_3_port, b => n4094, c => n1142
, d => n2742, outb => n1147);
U2563 : oai22 port map( a => n1147, b => n1146, c => n4095, d => n2743, outb
=> n1149);
U2564 : oai22 port map( a => n4096, b => n4097, c => n1148, d => n2765, outb
=> n1151);
U2565 : aoi22 port map( a => n1151, b => mult_125_G3_ab_5_3_port, c => n4099
, d => n2745, outb => n4098);
U2566 : oai22 port map( a => n4098, b => n4100, c => n1152, d => n2768, outb
=> n1155);
U2567 : aoi22 port map( a => n1155, b => mult_125_G3_ab_7_3_port, c => n4102
, d => n2748, outb => n4101);
U2568 : oai22 port map( a => n4101, b => n4103, c => n1156, d => n2771, outb
=> n1159);
U2569 : aoi22 port map( a => n1159, b => mult_125_G3_ab_9_3_port, c => n4105
, d => n2751, outb => n4104);
U2570 : oai22 port map( a => n4104, b => n4106, c => n1160, d => n2774, outb
=> n1163);
U2571 : aoi22 port map( a => n1163, b => mult_125_G3_ab_11_3_port, c =>
n4108, d => n2754, outb => n4107);
U2572 : oai22 port map( a => n4107, b => n4109, c => n1164, d => n2777, outb
=> n1167);
U2573 : aoi22 port map( a => n1167, b => mult_125_G3_ab_13_3_port, c =>
n4111, d => n2757, outb => n4110);
U2574 : inv port map( inb => mult_125_G3_ab_14_3_port, outb => n4112);
U2575 : oai22 port map( a => n4110, b => n4112, c => n1168, d => n2780, outb
=> n1171);
U2576 : nand2 port map( a => mult_125_G3_ab_0_3_port, b =>
mult_125_G3_ab_1_2_port, outb => n1174);
U2577 : aoi22 port map( a => mult_125_G3_ab_2_2_port, b => n4114, c => n1172
, d => n2760, outb => n4113);
U2578 : oai22 port map( a => n4113, b => n4115, c => n1175, d => n2761, outb
=> n1178);
U2579 : aoi22 port map( a => n1178, b => mult_125_G3_ab_4_2_port, c => n4117
, d => n2788, outb => n4116);
U2580 : oai22 port map( a => n4116, b => n4118, c => n1179, d => n2763, outb
=> n1182);
U2581 : aoi22 port map( a => n1182, b => mult_125_G3_ab_6_2_port, c => n4119
, d => n2791, outb => n1185);
U2582 : oai22 port map( a => n1185, b => n1184, c => n4120, d => n2766, outb
=> n1187);
U2583 : aoi22 port map( a => n1187, b => mult_125_G3_ab_8_2_port, c => n4122
, d => n2794, outb => n4121);
U2584 : oai22 port map( a => n4121, b => n4123, c => n1188, d => n2769, outb
=> n1191);
U2585 : aoi22 port map( a => n1191, b => mult_125_G3_ab_10_2_port, c =>
n4125, d => n2797, outb => n4124);
U2586 : oai22 port map( a => n4124, b => n4126, c => n1192, d => n2772, outb
=> n1195);
U2587 : aoi22 port map( a => n1195, b => mult_125_G3_ab_12_2_port, c =>
n4128, d => n2800, outb => n4127);
U2588 : oai22 port map( a => n4127, b => n4129, c => n1196, d => n2775, outb
=> n1199);
U2589 : aoi22 port map( a => n1199, b => mult_125_G3_ab_14_2_port, c =>
n4131, d => n2803, outb => n4130);
U2590 : nand2 port map( a => mult_125_G3_ab_0_2_port, b =>
mult_125_G3_ab_1_1_port, outb => n1204);
U2591 : aoi22 port map( a => mult_125_G3_ab_2_1_port, b => n4133, c => n1202
, d => n2783, outb => n4132);
U2592 : oai22 port map( a => n4132, b => n4134, c => n1205, d => n2784, outb
=> n1208);
U2593 : inv port map( inb => mult_125_G3_ab_4_1_port, outb => n4135);
U2594 : oai22 port map( a => n4136, b => n4135, c => n1207, d => n2809, outb
=> n1210);
U2595 : aoi22 port map( a => n1210, b => mult_125_G3_ab_5_1_port, c => n4138
, d => n2786, outb => n4137);
U2596 : oai22 port map( a => n4137, b => n4139, c => n1211, d => n2812, outb
=> n1214);
U2597 : aoi22 port map( a => n1214, b => mult_125_G3_ab_7_1_port, c => n4141
, d => n2789, outb => n4140);
U2598 : oai22 port map( a => n4140, b => n4142, c => n1215, d => n2815, outb
=> n1218);
U2599 : aoi22 port map( a => n1218, b => mult_125_G3_ab_9_1_port, c => n4144
, d => n2792, outb => n4143);
U2600 : oai22 port map( a => n4143, b => n4145, c => n1219, d => n2818, outb
=> n1222);
U2601 : aoi22 port map( a => n1222, b => mult_125_G3_ab_11_1_port, c =>
n4147, d => n2795, outb => n4146);
U2602 : oai22 port map( a => n4146, b => n4148, c => n1223, d => n2821, outb
=> n1226);
U2603 : aoi22 port map( a => n1226, b => mult_125_G3_ab_13_1_port, c =>
n4150, d => n2798, outb => n4149);
U2604 : inv port map( inb => mult_125_G3_ab_14_1_port, outb => n4151);
U2605 : oai22 port map( a => n4149, b => n4151, c => n1227, d => n2824, outb
=> n1230);
U2606 : nand2 port map( a => mult_125_G3_ab_0_1_port, b =>
mult_125_G3_ab_1_0_port, outb => n4152);
U2607 : aoi22 port map( a => mult_125_G3_ab_2_0_port, b => n1232, c => n4154
, d => n2804, outb => n4153);
U2608 : aoi22 port map( a => n1234, b => mult_125_G3_ab_3_0_port, c => n4156
, d => n2805, outb => n4155);
U2609 : inv port map( inb => mult_125_G3_ab_4_0_port, outb => n4157);
U2610 : oai22 port map( a => n4155, b => n4157, c => n1235, d => n4158, outb
=> n1238);
U2611 : aoi22 port map( a => n1238, b => mult_125_G3_ab_5_0_port, c => n4160
, d => n2807, outb => n4159);
U2612 : inv port map( inb => mult_125_G3_ab_6_0_port, outb => n4161);
U2613 : oai22 port map( a => n4159, b => n4161, c => n1239, d => n4162, outb
=> n1242);
U2614 : aoi22 port map( a => n1242, b => mult_125_G3_ab_7_0_port, c => n4164
, d => n2810, outb => n4163);
U2615 : inv port map( inb => mult_125_G3_ab_8_0_port, outb => n4165);
U2616 : oai22 port map( a => n4163, b => n4165, c => n1243, d => n4166, outb
=> n1246);
U2617 : aoi22 port map( a => n1246, b => mult_125_G3_ab_9_0_port, c => n4168
, d => n2813, outb => n4167);
U2618 : inv port map( inb => mult_125_G3_ab_10_0_port, outb => n4169);
U2619 : oai22 port map( a => n4167, b => n4169, c => n1247, d => n4170, outb
=> n1250);
U2620 : aoi22 port map( a => n1250, b => mult_125_G3_ab_11_0_port, c =>
n4172, d => n2816, outb => n4171);
U2621 : inv port map( inb => mult_125_G3_ab_12_0_port, outb => n4173);
U2622 : oai22 port map( a => n4171, b => n4173, c => n1251, d => n4174, outb
=> n1254);
U2623 : aoi22 port map( a => n1254, b => mult_125_G3_ab_13_0_port, c =>
n4176, d => n2819, outb => n4175);
U2624 : inv port map( inb => mult_125_G3_ab_14_0_port, outb => n4177);
U2625 : oai22 port map( a => n4175, b => n4177, c => n1255, d => n4178, outb
=> n1258);
U2626 : inv port map( inb => mult_125_G3_ZB, outb => n380);
U2627 : inv port map( inb => mult_125_G3_ZA, outb => n381);
U2628 : nand2 port map( a => mult_125_G2_ab_0_15_port, b =>
mult_125_G2_ab_1_14_port, outb => n4179);
U2629 : inv port map( inb => mult_125_G2_ab_3_15_port, outb => n4180);
U2630 : inv port map( inb => mult_125_G2_ab_4_14_port, outb => n4181);
U2631 : inv port map( inb => mult_125_G2_ab_5_15_port, outb => n4182);
U2632 : inv port map( inb => mult_125_G2_ab_6_14_port, outb => n4183);
U2633 : inv port map( inb => mult_125_G2_ab_7_15_port, outb => n4184);
U2634 : inv port map( inb => mult_125_G2_ab_8_14_port, outb => n4185);
U2635 : inv port map( inb => mult_125_G2_ab_9_15_port, outb => n4186);
U2636 : inv port map( inb => mult_125_G2_ab_10_14_port, outb => n4187);
U2637 : inv port map( inb => mult_125_G2_ab_11_15_port, outb => n4188);
U2638 : inv port map( inb => mult_125_G2_ab_12_14_port, outb => n4189);
U2639 : nand2 port map( a => mult_125_G2_ab_0_14_port, b =>
mult_125_G2_ab_1_13_port, outb => n1276);
U2640 : aoi22 port map( a => mult_125_G2_ab_2_13_port, b => n4190, c =>
n1274, d => n2834, outb => n1279);
U2641 : oai22 port map( a => n1279, b => n1278, c => n4191, d => n2835, outb
=> n1281);
U2642 : aoi22 port map( a => n1281, b => mult_125_G2_ab_4_13_port, c =>
n4193, d => n2842, outb => n4192);
U2643 : oai22 port map( a => n4192, b => n4194, c => n1282, d => n2845, outb
=> n1285);
U2644 : aoi22 port map( a => n1285, b => mult_125_G2_ab_6_13_port, c =>
n4196, d => n2848, outb => n4195);
U2645 : inv port map( inb => mult_125_G2_ab_7_13_port, outb => n4197);
U2646 : oai22 port map( a => n4195, b => n4197, c => n1286, d => n2851, outb
=> n1289);
U2647 : aoi22 port map( a => n1289, b => mult_125_G2_ab_8_13_port, c =>
n4199, d => n2854, outb => n4198);
U2648 : inv port map( inb => mult_125_G2_ab_9_13_port, outb => n4200);
U2649 : oai22 port map( a => n4198, b => n4200, c => n1290, d => n2857, outb
=> n1293);
U2650 : aoi22 port map( a => n1293, b => mult_125_G2_ab_10_13_port, c =>
n4202, d => n2860, outb => n4201);
U2651 : inv port map( inb => mult_125_G2_ab_11_13_port, outb => n4203);
U2652 : oai22 port map( a => n4201, b => n4203, c => n1294, d => n2863, outb
=> n1297);
U2653 : aoi22 port map( a => n1297, b => mult_125_G2_ab_12_13_port, c =>
n4205, d => n2866, outb => n4204);
U2654 : inv port map( inb => mult_125_G2_ab_13_13_port, outb => n4206);
U2655 : oai22 port map( a => n4204, b => n4206, c => n1298, d => n2869, outb
=> n1301);
U2656 : aoi22 port map( a => n1301, b => mult_125_G2_ab_14_13_port, c =>
n4208, d => n2872, outb => n4207);
U2657 : nand2 port map( a => mult_125_G2_ab_0_13_port, b =>
mult_125_G2_ab_1_12_port, outb => n1306);
U2658 : aoi22 port map( a => mult_125_G2_ab_2_12_port, b => n4210, c =>
n1304, d => n2837, outb => n4209);
U2659 : oai22 port map( a => n4209, b => n4211, c => n1307, d => n2838, outb
=> n1310);
U2660 : aoi22 port map( a => n1310, b => mult_125_G2_ab_4_12_port, c =>
n4213, d => n2880, outb => n4212);
U2661 : aoi22 port map( a => n1312, b => mult_125_G2_ab_5_12_port, c =>
n4215, d => n2840, outb => n4214);
U2662 : inv port map( inb => mult_125_G2_ab_6_12_port, outb => n4216);
U2663 : oai22 port map( a => n4214, b => n4216, c => n1313, d => n2843, outb
=> n1316);
U2664 : aoi22 port map( a => n1316, b => mult_125_G2_ab_7_12_port, c =>
n4218, d => n2846, outb => n4217);
U2665 : inv port map( inb => mult_125_G2_ab_8_12_port, outb => n4219);
U2666 : oai22 port map( a => n4217, b => n4219, c => n1317, d => n2849, outb
=> n1320);
U2667 : aoi22 port map( a => n1320, b => mult_125_G2_ab_9_12_port, c =>
n4221, d => n2852, outb => n4220);
U2668 : inv port map( inb => mult_125_G2_ab_10_12_port, outb => n4222);
U2669 : oai22 port map( a => n4220, b => n4222, c => n1321, d => n2855, outb
=> n1324);
U2670 : aoi22 port map( a => n1324, b => mult_125_G2_ab_11_12_port, c =>
n4224, d => n2858, outb => n4223);
U2671 : inv port map( inb => mult_125_G2_ab_12_12_port, outb => n4225);
U2672 : oai22 port map( a => n4223, b => n4225, c => n1325, d => n2861, outb
=> n1328);
U2673 : aoi22 port map( a => n1328, b => mult_125_G2_ab_13_12_port, c =>
n4227, d => n2864, outb => n4226);
U2674 : inv port map( inb => mult_125_G2_ab_14_12_port, outb => n4228);
U2675 : oai22 port map( a => n4226, b => n4228, c => n1329, d => n2867, outb
=> n1332);
U2676 : nand2 port map( a => mult_125_G2_ab_0_12_port, b =>
mult_125_G2_ab_1_11_port, outb => n1335);
U2677 : aoi22 port map( a => mult_125_G2_ab_2_11_port, b => n4229, c =>
n1333, d => n2875, outb => n1338);
U2678 : oai22 port map( a => n1338, b => n1337, c => n4230, d => n2876, outb
=> n1340);
U2679 : oai22 port map( a => n4231, b => n4232, c => n1339, d => n2886, outb
=> n1342);
U2680 : aoi22 port map( a => n1342, b => mult_125_G2_ab_5_11_port, c =>
n4234, d => n2878, outb => n4233);
U2681 : oai22 port map( a => n4233, b => n4235, c => n1343, d => n2889, outb
=> n1346);
U2682 : oai22 port map( a => n4236, b => n4237, c => n1345, d => n2892, outb
=> n1348);
U2683 : aoi22 port map( a => n1348, b => mult_125_G2_ab_8_11_port, c =>
n4239, d => n2895, outb => n4238);
U2684 : inv port map( inb => mult_125_G2_ab_9_11_port, outb => n4240);
U2685 : oai22 port map( a => n4238, b => n4240, c => n1349, d => n2898, outb
=> n1352);
U2686 : aoi22 port map( a => n1352, b => mult_125_G2_ab_10_11_port, c =>
n4242, d => n2901, outb => n4241);
U2687 : inv port map( inb => mult_125_G2_ab_11_11_port, outb => n4243);
U2688 : oai22 port map( a => n4241, b => n4243, c => n1353, d => n2904, outb
=> n1356);
U2689 : aoi22 port map( a => n1356, b => mult_125_G2_ab_12_11_port, c =>
n4245, d => n2907, outb => n4244);
U2690 : inv port map( inb => mult_125_G2_ab_13_11_port, outb => n4246);
U2691 : oai22 port map( a => n4244, b => n4246, c => n1357, d => n2910, outb
=> n1360);
U2692 : aoi22 port map( a => n1360, b => mult_125_G2_ab_14_11_port, c =>
n4247, d => n2913, outb => n1363);
U2693 : nand2 port map( a => mult_125_G2_ab_0_11_port, b =>
mult_125_G2_ab_1_10_port, outb => n1366);
U2694 : aoi22 port map( a => mult_125_G2_ab_2_10_port, b => n4249, c =>
n1364, d => n2881, outb => n4248);
U2695 : oai22 port map( a => n4248, b => n4250, c => n1367, d => n2882, outb
=> n1370);
U2696 : aoi22 port map( a => n1370, b => mult_125_G2_ab_4_10_port, c =>
n4251, d => n2921, outb => n1373);
U2697 : oai22 port map( a => n1373, b => n1372, c => n4252, d => n2884, outb
=> n1375);
U2698 : aoi22 port map( a => n1375, b => mult_125_G2_ab_6_10_port, c =>
n4254, d => n2924, outb => n4253);
U2699 : oai22 port map( a => n4253, b => n4255, c => n1376, d => n2887, outb
=> n1379);
U2700 : inv port map( inb => mult_125_G2_ab_8_10_port, outb => n4256);
U2701 : oai22 port map( a => n4257, b => n4256, c => n1378, d => n2890, outb
=> n1381);
U2702 : aoi22 port map( a => n1381, b => mult_125_G2_ab_9_10_port, c =>
n4259, d => n2893, outb => n4258);
U2703 : inv port map( inb => mult_125_G2_ab_10_10_port, outb => n4260);
U2704 : oai22 port map( a => n4258, b => n4260, c => n1382, d => n2896, outb
=> n1385);
U2705 : aoi22 port map( a => n1385, b => mult_125_G2_ab_11_10_port, c =>
n4262, d => n2899, outb => n4261);
U2706 : inv port map( inb => mult_125_G2_ab_12_10_port, outb => n4263);
U2707 : oai22 port map( a => n4261, b => n4263, c => n1386, d => n2902, outb
=> n1389);
U2708 : aoi22 port map( a => n1389, b => mult_125_G2_ab_13_10_port, c =>
n4265, d => n2905, outb => n4264);
U2709 : inv port map( inb => mult_125_G2_ab_14_10_port, outb => n4266);
U2710 : oai22 port map( a => n4264, b => n4266, c => n1390, d => n2908, outb
=> n1393);
U2711 : nand2 port map( a => mult_125_G2_ab_0_10_port, b =>
mult_125_G2_ab_1_9_port, outb => n1396);
U2712 : aoi22 port map( a => mult_125_G2_ab_2_9_port, b => n4268, c => n1394
, d => n2916, outb => n4267);
U2713 : oai22 port map( a => n4267, b => n4269, c => n1397, d => n2917, outb
=> n1400);
U2714 : oai22 port map( a => n4270, b => n4271, c => n1399, d => n2930, outb
=> n1402);
U2715 : aoi22 port map( a => n1402, b => mult_125_G2_ab_5_9_port, c => n4273
, d => n2919, outb => n4272);
U2716 : oai22 port map( a => n4272, b => n4274, c => n1403, d => n2933, outb
=> n1406);
U2717 : aoi22 port map( a => n1406, b => mult_125_G2_ab_7_9_port, c => n4276
, d => n2922, outb => n4275);
U2718 : oai22 port map( a => n4275, b => n4277, c => n1407, d => n2936, outb
=> n1410);
U2719 : oai22 port map( a => n4278, b => n4279, c => n1409, d => n2939, outb
=> n1412);
U2720 : aoi22 port map( a => n1412, b => mult_125_G2_ab_10_9_port, c =>
n4281, d => n2942, outb => n4280);
U2721 : inv port map( inb => mult_125_G2_ab_11_9_port, outb => n4282);
U2722 : oai22 port map( a => n4280, b => n4282, c => n1413, d => n2945, outb
=> n1416);
U2723 : aoi22 port map( a => n1416, b => mult_125_G2_ab_12_9_port, c =>
n4284, d => n2948, outb => n4283);
U2724 : inv port map( inb => mult_125_G2_ab_13_9_port, outb => n4285);
U2725 : oai22 port map( a => n4283, b => n4285, c => n1417, d => n2951, outb
=> n1420);
U2726 : aoi22 port map( a => n1420, b => mult_125_G2_ab_14_9_port, c =>
n4286, d => n2954, outb => n1423);
U2727 : nand2 port map( a => mult_125_G2_ab_0_9_port, b =>
mult_125_G2_ab_1_8_port, outb => n1426);
U2728 : aoi22 port map( a => mult_125_G2_ab_2_8_port, b => n4288, c => n1424
, d => n2925, outb => n4287);
U2729 : oai22 port map( a => n4287, b => n4289, c => n1427, d => n2926, outb
=> n1430);
U2730 : oai22 port map( a => n4290, b => n4291, c => n1429, d => n2962, outb
=> n1432);
U2731 : oai22 port map( a => n4292, b => n4293, c => n1431, d => n2928, outb
=> n1434);
U2732 : aoi22 port map( a => n1434, b => mult_125_G2_ab_6_8_port, c => n4295
, d => n2965, outb => n4294);
U2733 : oai22 port map( a => n4294, b => n4296, c => n1435, d => n2931, outb
=> n1438);
U2734 : aoi22 port map( a => n1438, b => mult_125_G2_ab_8_8_port, c => n4298
, d => n2968, outb => n4297);
U2735 : oai22 port map( a => n4297, b => n4299, c => n1439, d => n2934, outb
=> n1442);
U2736 : inv port map( inb => mult_125_G2_ab_10_8_port, outb => n4300);
U2737 : oai22 port map( a => n4301, b => n4300, c => n1441, d => n2937, outb
=> n1444);
U2738 : aoi22 port map( a => n1444, b => mult_125_G2_ab_11_8_port, c =>
n4303, d => n2940, outb => n4302);
U2739 : inv port map( inb => mult_125_G2_ab_12_8_port, outb => n4304);
U2740 : oai22 port map( a => n4302, b => n4304, c => n1445, d => n2943, outb
=> n1448);
U2741 : aoi22 port map( a => n1448, b => mult_125_G2_ab_13_8_port, c =>
n4306, d => n2946, outb => n4305);
U2742 : inv port map( inb => mult_125_G2_ab_14_8_port, outb => n4307);
U2743 : oai22 port map( a => n4305, b => n4307, c => n1449, d => n2949, outb
=> n1452);
U2744 : nand2 port map( a => mult_125_G2_ab_0_8_port, b =>
mult_125_G2_ab_1_7_port, outb => n1455);
U2745 : aoi22 port map( a => mult_125_G2_ab_2_7_port, b => n4308, c => n1453
, d => n2957, outb => n1458);
U2746 : oai22 port map( a => n1458, b => n1457, c => n4309, d => n2958, outb
=> n1460);
U2747 : oai22 port map( a => n4310, b => n4311, c => n1459, d => n2974, outb
=> n1462);
U2748 : aoi22 port map( a => n1462, b => mult_125_G2_ab_5_7_port, c => n4313
, d => n2960, outb => n4312);
U2749 : oai22 port map( a => n4312, b => n4314, c => n1463, d => n2977, outb
=> n1466);
U2750 : aoi22 port map( a => n1466, b => mult_125_G2_ab_7_7_port, c => n4316
, d => n2963, outb => n4315);
U2751 : oai22 port map( a => n4315, b => n4317, c => n1467, d => n2980, outb
=> n1470);
U2752 : aoi22 port map( a => n1470, b => mult_125_G2_ab_9_7_port, c => n4319
, d => n2966, outb => n4318);
U2753 : oai22 port map( a => n4318, b => n4320, c => n1471, d => n2983, outb
=> n1474);
U2754 : oai22 port map( a => n4321, b => n4322, c => n1473, d => n2986, outb
=> n1476);
U2755 : aoi22 port map( a => n1476, b => mult_125_G2_ab_12_7_port, c =>
n4324, d => n2989, outb => n4323);
U2756 : inv port map( inb => mult_125_G2_ab_13_7_port, outb => n4325);
U2757 : oai22 port map( a => n4323, b => n4325, c => n1477, d => n2992, outb
=> n1480);
U2758 : aoi22 port map( a => n1480, b => mult_125_G2_ab_14_7_port, c =>
n4326, d => n2995, outb => n1483);
U2759 : nand2 port map( a => mult_125_G2_ab_0_7_port, b =>
mult_125_G2_ab_1_6_port, outb => n1486);
U2760 : aoi22 port map( a => mult_125_G2_ab_2_6_port, b => n4328, c => n1484
, d => n2969, outb => n4327);
U2761 : oai22 port map( a => n4327, b => n4329, c => n1487, d => n2970, outb
=> n1490);
U2762 : aoi22 port map( a => n1490, b => mult_125_G2_ab_4_6_port, c => n4330
, d => n3003, outb => n1493);
U2763 : oai22 port map( a => n1493, b => n1492, c => n4331, d => n2972, outb
=> n1495);
U2764 : aoi22 port map( a => n1495, b => mult_125_G2_ab_6_6_port, c => n4333
, d => n3006, outb => n4332);
U2765 : oai22 port map( a => n4332, b => n4334, c => n1496, d => n2975, outb
=> n1499);
U2766 : aoi22 port map( a => n1499, b => mult_125_G2_ab_8_6_port, c => n4335
, d => n3009, outb => n1502);
U2767 : oai22 port map( a => n1502, b => n1501, c => n4336, d => n2978, outb
=> n1504);
U2768 : aoi22 port map( a => n1504, b => mult_125_G2_ab_10_6_port, c =>
n4338, d => n3012, outb => n4337);
U2769 : oai22 port map( a => n4337, b => n4339, c => n1505, d => n2981, outb
=> n1508);
U2770 : inv port map( inb => mult_125_G2_ab_12_6_port, outb => n4340);
U2771 : oai22 port map( a => n4341, b => n4340, c => n1507, d => n2984, outb
=> n1510);
U2772 : aoi22 port map( a => n1510, b => mult_125_G2_ab_13_6_port, c =>
n4343, d => n2987, outb => n4342);
U2773 : inv port map( inb => mult_125_G2_ab_14_6_port, outb => n4344);
U2774 : oai22 port map( a => n4342, b => n4344, c => n1511, d => n2990, outb
=> n1514);
U2775 : nand2 port map( a => mult_125_G2_ab_0_6_port, b =>
mult_125_G2_ab_1_5_port, outb => n1517);
U2776 : aoi22 port map( a => mult_125_G2_ab_2_5_port, b => n4345, c => n1515
, d => n2998, outb => n1520);
U2777 : oai22 port map( a => n1520, b => n1519, c => n4346, d => n2999, outb
=> n1522);
U2778 : oai22 port map( a => n4347, b => n4348, c => n1521, d => n3018, outb
=> n1524);
U2779 : aoi22 port map( a => n1524, b => mult_125_G2_ab_5_5_port, c => n4349
, d => n3001, outb => n1527);
U2780 : oai22 port map( a => n1527, b => n1526, c => n4350, d => n3021, outb
=> n1529);
U2781 : aoi22 port map( a => n1529, b => mult_125_G2_ab_7_5_port, c => n4352
, d => n3004, outb => n4351);
U2782 : oai22 port map( a => n4351, b => n4353, c => n1530, d => n3024, outb
=> n1533);
U2783 : aoi22 port map( a => n1533, b => mult_125_G2_ab_9_5_port, c => n4355
, d => n3007, outb => n4354);
U2784 : oai22 port map( a => n4354, b => n4356, c => n1534, d => n3027, outb
=> n1537);
U2785 : aoi22 port map( a => n1537, b => mult_125_G2_ab_11_5_port, c =>
n4358, d => n3010, outb => n4357);
U2786 : oai22 port map( a => n4357, b => n4359, c => n1538, d => n3030, outb
=> n1541);
U2787 : oai22 port map( a => n4360, b => n4361, c => n1540, d => n3033, outb
=> n1543);
U2788 : aoi22 port map( a => n1543, b => mult_125_G2_ab_14_5_port, c =>
n4362, d => n3036, outb => n1546);
U2789 : nand2 port map( a => mult_125_G2_ab_0_5_port, b =>
mult_125_G2_ab_1_4_port, outb => n1549);
U2790 : aoi22 port map( a => mult_125_G2_ab_2_4_port, b => n4364, c => n1547
, d => n3013, outb => n4363);
U2791 : oai22 port map( a => n4363, b => n4365, c => n1550, d => n3014, outb
=> n1553);
U2792 : aoi22 port map( a => n1553, b => mult_125_G2_ab_4_4_port, c => n4366
, d => n3044, outb => n1556);
U2793 : oai22 port map( a => n1556, b => n1555, c => n4367, d => n3016, outb
=> n1558);
U2794 : aoi22 port map( a => n1558, b => mult_125_G2_ab_6_4_port, c => n4368
, d => n3047, outb => n1561);
U2795 : oai22 port map( a => n1561, b => n1560, c => n4369, d => n3019, outb
=> n1563);
U2796 : aoi22 port map( a => n1563, b => mult_125_G2_ab_8_4_port, c => n4371
, d => n3050, outb => n4370);
U2797 : oai22 port map( a => n4370, b => n4372, c => n1564, d => n3022, outb
=> n1567);
U2798 : aoi22 port map( a => n1567, b => mult_125_G2_ab_10_4_port, c =>
n4373, d => n3053, outb => n1570);
U2799 : oai22 port map( a => n1570, b => n1569, c => n4374, d => n3025, outb
=> n1572);
U2800 : aoi22 port map( a => n1572, b => mult_125_G2_ab_12_4_port, c =>
n4376, d => n3056, outb => n4375);
U2801 : oai22 port map( a => n4375, b => n4377, c => n1573, d => n3028, outb
=> n1576);
U2802 : aoi22 port map( a => n1576, b => mult_125_G2_ab_14_4_port, c =>
n4378, d => n3031, outb => n1579);
U2803 : nand2 port map( a => mult_125_G2_ab_0_4_port, b =>
mult_125_G2_ab_1_3_port, outb => n1582);
U2804 : aoi22 port map( a => mult_125_G2_ab_2_3_port, b => n4379, c => n1580
, d => n3039, outb => n1585);
U2805 : oai22 port map( a => n1585, b => n1584, c => n4380, d => n3040, outb
=> n1587);
U2806 : oai22 port map( a => n4381, b => n4382, c => n1586, d => n3062, outb
=> n1589);
U2807 : aoi22 port map( a => n1589, b => mult_125_G2_ab_5_3_port, c => n4384
, d => n3042, outb => n4383);
U2808 : oai22 port map( a => n4383, b => n4385, c => n1590, d => n3065, outb
=> n1593);
U2809 : aoi22 port map( a => n1593, b => mult_125_G2_ab_7_3_port, c => n4387
, d => n3045, outb => n4386);
U2810 : oai22 port map( a => n4386, b => n4388, c => n1594, d => n3068, outb
=> n1597);
U2811 : aoi22 port map( a => n1597, b => mult_125_G2_ab_9_3_port, c => n4390
, d => n3048, outb => n4389);
U2812 : oai22 port map( a => n4389, b => n4391, c => n1598, d => n3071, outb
=> n1601);
U2813 : aoi22 port map( a => n1601, b => mult_125_G2_ab_11_3_port, c =>
n4393, d => n3051, outb => n4392);
U2814 : oai22 port map( a => n4392, b => n4394, c => n1602, d => n3074, outb
=> n1605);
U2815 : aoi22 port map( a => n1605, b => mult_125_G2_ab_13_3_port, c =>
n4396, d => n3054, outb => n4395);
U2816 : inv port map( inb => mult_125_G2_ab_14_3_port, outb => n4397);
U2817 : oai22 port map( a => n4395, b => n4397, c => n1606, d => n3077, outb
=> n1609);
U2818 : nand2 port map( a => mult_125_G2_ab_0_3_port, b =>
mult_125_G2_ab_1_2_port, outb => n1612);
U2819 : aoi22 port map( a => mult_125_G2_ab_2_2_port, b => n4399, c => n1610
, d => n3057, outb => n4398);
U2820 : oai22 port map( a => n4398, b => n4400, c => n1613, d => n3058, outb
=> n1616);
U2821 : aoi22 port map( a => n1616, b => mult_125_G2_ab_4_2_port, c => n4402
, d => n3085, outb => n4401);
U2822 : oai22 port map( a => n4401, b => n4403, c => n1617, d => n3060, outb
=> n1620);
U2823 : aoi22 port map( a => n1620, b => mult_125_G2_ab_6_2_port, c => n4404
, d => n3088, outb => n1623);
U2824 : oai22 port map( a => n1623, b => n1622, c => n4405, d => n3063, outb
=> n1625);
U2825 : aoi22 port map( a => n1625, b => mult_125_G2_ab_8_2_port, c => n4407
, d => n3091, outb => n4406);
U2826 : oai22 port map( a => n4406, b => n4408, c => n1626, d => n3066, outb
=> n1629);
U2827 : aoi22 port map( a => n1629, b => mult_125_G2_ab_10_2_port, c =>
n4410, d => n3094, outb => n4409);
U2828 : oai22 port map( a => n4409, b => n4411, c => n1630, d => n3069, outb
=> n1633);
U2829 : aoi22 port map( a => n1633, b => mult_125_G2_ab_12_2_port, c =>
n4413, d => n3097, outb => n4412);
U2830 : oai22 port map( a => n4412, b => n4414, c => n1634, d => n3072, outb
=> n1637);
U2831 : aoi22 port map( a => n1637, b => mult_125_G2_ab_14_2_port, c =>
n4416, d => n3100, outb => n4415);
U2832 : nand2 port map( a => mult_125_G2_ab_0_2_port, b =>
mult_125_G2_ab_1_1_port, outb => n1642);
U2833 : aoi22 port map( a => mult_125_G2_ab_2_1_port, b => n4418, c => n1640
, d => n3080, outb => n4417);
U2834 : oai22 port map( a => n4417, b => n4419, c => n1643, d => n3081, outb
=> n1646);
U2835 : inv port map( inb => mult_125_G2_ab_4_1_port, outb => n4420);
U2836 : oai22 port map( a => n4421, b => n4420, c => n1645, d => n3106, outb
=> n1648);
U2837 : aoi22 port map( a => n1648, b => mult_125_G2_ab_5_1_port, c => n4423
, d => n3083, outb => n4422);
U2838 : oai22 port map( a => n4422, b => n4424, c => n1649, d => n3109, outb
=> n1652);
U2839 : aoi22 port map( a => n1652, b => mult_125_G2_ab_7_1_port, c => n4426
, d => n3086, outb => n4425);
U2840 : oai22 port map( a => n4425, b => n4427, c => n1653, d => n3112, outb
=> n1656);
U2841 : aoi22 port map( a => n1656, b => mult_125_G2_ab_9_1_port, c => n4429
, d => n3089, outb => n4428);
U2842 : oai22 port map( a => n4428, b => n4430, c => n1657, d => n3115, outb
=> n1660);
U2843 : aoi22 port map( a => n1660, b => mult_125_G2_ab_11_1_port, c =>
n4432, d => n3092, outb => n4431);
U2844 : oai22 port map( a => n4431, b => n4433, c => n1661, d => n3118, outb
=> n1664);
U2845 : aoi22 port map( a => n1664, b => mult_125_G2_ab_13_1_port, c =>
n4435, d => n3095, outb => n4434);
U2846 : inv port map( inb => mult_125_G2_ab_14_1_port, outb => n4436);
U2847 : oai22 port map( a => n4434, b => n4436, c => n1665, d => n3121, outb
=> n1668);
U2848 : nand2 port map( a => mult_125_G2_ab_0_1_port, b =>
mult_125_G2_ab_1_0_port, outb => n4437);
U2849 : aoi22 port map( a => mult_125_G2_ab_2_0_port, b => n1670, c => n4439
, d => n3101, outb => n4438);
U2850 : aoi22 port map( a => n1672, b => mult_125_G2_ab_3_0_port, c => n4441
, d => n3102, outb => n4440);
U2851 : inv port map( inb => mult_125_G2_ab_4_0_port, outb => n4442);
U2852 : oai22 port map( a => n4440, b => n4442, c => n1673, d => n4443, outb
=> n1676);
U2853 : aoi22 port map( a => n1676, b => mult_125_G2_ab_5_0_port, c => n4445
, d => n3104, outb => n4444);
U2854 : inv port map( inb => mult_125_G2_ab_6_0_port, outb => n4446);
U2855 : oai22 port map( a => n4444, b => n4446, c => n1677, d => n4447, outb
=> n1680);
U2856 : aoi22 port map( a => n1680, b => mult_125_G2_ab_7_0_port, c => n4449
, d => n3107, outb => n4448);
U2857 : inv port map( inb => mult_125_G2_ab_8_0_port, outb => n4450);
U2858 : oai22 port map( a => n4448, b => n4450, c => n1681, d => n4451, outb
=> n1684);
U2859 : aoi22 port map( a => n1684, b => mult_125_G2_ab_9_0_port, c => n4453
, d => n3110, outb => n4452);
U2860 : inv port map( inb => mult_125_G2_ab_10_0_port, outb => n4454);
U2861 : oai22 port map( a => n4452, b => n4454, c => n1685, d => n4455, outb
=> n1688);
U2862 : aoi22 port map( a => n1688, b => mult_125_G2_ab_11_0_port, c =>
n4457, d => n3113, outb => n4456);
U2863 : inv port map( inb => mult_125_G2_ab_12_0_port, outb => n4458);
U2864 : oai22 port map( a => n4456, b => n4458, c => n1689, d => n4459, outb
=> n1692);
U2865 : aoi22 port map( a => n1692, b => mult_125_G2_ab_13_0_port, c =>
n4461, d => n3116, outb => n4460);
U2866 : inv port map( inb => mult_125_G2_ab_14_0_port, outb => n4462);
U2867 : oai22 port map( a => n4460, b => n4462, c => n1693, d => n4463, outb
=> n1696);
U2868 : inv port map( inb => mult_125_G2_ZB, outb => n344);
U2869 : inv port map( inb => mult_125_G2_ZA, outb => n345);
U2870 : nand2 port map( a => mult_125_ab_0_15_port, b =>
mult_125_ab_1_14_port, outb => n4464);
U2871 : inv port map( inb => mult_125_ab_3_15_port, outb => n4465);
U2872 : inv port map( inb => mult_125_ab_4_14_port, outb => n4466);
U2873 : inv port map( inb => mult_125_ab_5_15_port, outb => n4467);
U2874 : inv port map( inb => mult_125_ab_6_14_port, outb => n4468);
U2875 : inv port map( inb => mult_125_ab_7_15_port, outb => n4469);
U2876 : inv port map( inb => mult_125_ab_8_14_port, outb => n4470);
U2877 : inv port map( inb => mult_125_ab_9_15_port, outb => n4471);
U2878 : inv port map( inb => mult_125_ab_10_14_port, outb => n4472);
U2879 : inv port map( inb => mult_125_ab_11_15_port, outb => n4473);
U2880 : inv port map( inb => mult_125_ab_12_14_port, outb => n4474);
U2881 : nand2 port map( a => mult_125_ab_0_14_port, b =>
mult_125_ab_1_13_port, outb => n1714);
U2882 : aoi22 port map( a => mult_125_ab_2_13_port, b => n4475, c => n1712,
d => n3131, outb => n1717);
U2883 : oai22 port map( a => n1717, b => n1716, c => n4476, d => n3132, outb
=> n1719);
U2884 : aoi22 port map( a => n1719, b => mult_125_ab_4_13_port, c => n4478,
d => n3139, outb => n4477);
U2885 : oai22 port map( a => n4477, b => n4479, c => n1720, d => n3142, outb
=> n1723);
U2886 : aoi22 port map( a => n1723, b => mult_125_ab_6_13_port, c => n4481,
d => n3145, outb => n4480);
U2887 : inv port map( inb => mult_125_ab_7_13_port, outb => n4482);
U2888 : oai22 port map( a => n4480, b => n4482, c => n1724, d => n3148, outb
=> n1727);
U2889 : aoi22 port map( a => n1727, b => mult_125_ab_8_13_port, c => n4484,
d => n3151, outb => n4483);
U2890 : inv port map( inb => mult_125_ab_9_13_port, outb => n4485);
U2891 : oai22 port map( a => n4483, b => n4485, c => n1728, d => n3154, outb
=> n1731);
U2892 : aoi22 port map( a => n1731, b => mult_125_ab_10_13_port, c => n4487,
d => n3157, outb => n4486);
U2893 : inv port map( inb => mult_125_ab_11_13_port, outb => n4488);
U2894 : oai22 port map( a => n4486, b => n4488, c => n1732, d => n3160, outb
=> n1735);
U2895 : aoi22 port map( a => n1735, b => mult_125_ab_12_13_port, c => n4490,
d => n3163, outb => n4489);
U2896 : inv port map( inb => mult_125_ab_13_13_port, outb => n4491);
U2897 : oai22 port map( a => n4489, b => n4491, c => n1736, d => n3166, outb
=> n1739);
U2898 : aoi22 port map( a => n1739, b => mult_125_ab_14_13_port, c => n4493,
d => n3169, outb => n4492);
U2899 : nand2 port map( a => mult_125_ab_0_13_port, b =>
mult_125_ab_1_12_port, outb => n1744);
U2900 : aoi22 port map( a => mult_125_ab_2_12_port, b => n4495, c => n1742,
d => n3134, outb => n4494);
U2901 : oai22 port map( a => n4494, b => n4496, c => n1745, d => n3135, outb
=> n1748);
U2902 : aoi22 port map( a => n1748, b => mult_125_ab_4_12_port, c => n4498,
d => n3177, outb => n4497);
U2903 : aoi22 port map( a => n1750, b => mult_125_ab_5_12_port, c => n4500,
d => n3137, outb => n4499);
U2904 : inv port map( inb => mult_125_ab_6_12_port, outb => n4501);
U2905 : oai22 port map( a => n4499, b => n4501, c => n1751, d => n3140, outb
=> n1754);
U2906 : aoi22 port map( a => n1754, b => mult_125_ab_7_12_port, c => n4503,
d => n3143, outb => n4502);
U2907 : inv port map( inb => mult_125_ab_8_12_port, outb => n4504);
U2908 : oai22 port map( a => n4502, b => n4504, c => n1755, d => n3146, outb
=> n1758);
U2909 : aoi22 port map( a => n1758, b => mult_125_ab_9_12_port, c => n4506,
d => n3149, outb => n4505);
U2910 : inv port map( inb => mult_125_ab_10_12_port, outb => n4507);
U2911 : oai22 port map( a => n4505, b => n4507, c => n1759, d => n3152, outb
=> n1762);
U2912 : aoi22 port map( a => n1762, b => mult_125_ab_11_12_port, c => n4509,
d => n3155, outb => n4508);
U2913 : inv port map( inb => mult_125_ab_12_12_port, outb => n4510);
U2914 : oai22 port map( a => n4508, b => n4510, c => n1763, d => n3158, outb
=> n1766);
U2915 : aoi22 port map( a => n1766, b => mult_125_ab_13_12_port, c => n4512,
d => n3161, outb => n4511);
U2916 : inv port map( inb => mult_125_ab_14_12_port, outb => n4513);
U2917 : oai22 port map( a => n4511, b => n4513, c => n1767, d => n3164, outb
=> n1770);
U2918 : nand2 port map( a => mult_125_ab_0_12_port, b =>
mult_125_ab_1_11_port, outb => n1773);
U2919 : aoi22 port map( a => mult_125_ab_2_11_port, b => n4514, c => n1771,
d => n3172, outb => n1776);
U2920 : oai22 port map( a => n1776, b => n1775, c => n4515, d => n3173, outb
=> n1778);
U2921 : oai22 port map( a => n4516, b => n4517, c => n1777, d => n3183, outb
=> n1780);
U2922 : aoi22 port map( a => n1780, b => mult_125_ab_5_11_port, c => n4519,
d => n3175, outb => n4518);
U2923 : oai22 port map( a => n4518, b => n4520, c => n1781, d => n3186, outb
=> n1784);
U2924 : oai22 port map( a => n4521, b => n4522, c => n1783, d => n3189, outb
=> n1786);
U2925 : aoi22 port map( a => n1786, b => mult_125_ab_8_11_port, c => n4524,
d => n3192, outb => n4523);
U2926 : inv port map( inb => mult_125_ab_9_11_port, outb => n4525);
U2927 : oai22 port map( a => n4523, b => n4525, c => n1787, d => n3195, outb
=> n1790);
U2928 : aoi22 port map( a => n1790, b => mult_125_ab_10_11_port, c => n4527,
d => n3198, outb => n4526);
U2929 : inv port map( inb => mult_125_ab_11_11_port, outb => n4528);
U2930 : oai22 port map( a => n4526, b => n4528, c => n1791, d => n3201, outb
=> n1794);
U2931 : aoi22 port map( a => n1794, b => mult_125_ab_12_11_port, c => n4530,
d => n3204, outb => n4529);
U2932 : inv port map( inb => mult_125_ab_13_11_port, outb => n4531);
U2933 : oai22 port map( a => n4529, b => n4531, c => n1795, d => n3207, outb
=> n1798);
U2934 : aoi22 port map( a => n1798, b => mult_125_ab_14_11_port, c => n4532,
d => n3210, outb => n1801);
U2935 : nand2 port map( a => mult_125_ab_0_11_port, b =>
mult_125_ab_1_10_port, outb => n1804);
U2936 : aoi22 port map( a => mult_125_ab_2_10_port, b => n4534, c => n1802,
d => n3178, outb => n4533);
U2937 : oai22 port map( a => n4533, b => n4535, c => n1805, d => n3179, outb
=> n1808);
U2938 : aoi22 port map( a => n1808, b => mult_125_ab_4_10_port, c => n4536,
d => n3218, outb => n1811);
U2939 : oai22 port map( a => n1811, b => n1810, c => n4537, d => n3181, outb
=> n1813);
U2940 : aoi22 port map( a => n1813, b => mult_125_ab_6_10_port, c => n4539,
d => n3221, outb => n4538);
U2941 : oai22 port map( a => n4538, b => n4540, c => n1814, d => n3184, outb
=> n1817);
U2942 : inv port map( inb => mult_125_ab_8_10_port, outb => n4541);
U2943 : oai22 port map( a => n4542, b => n4541, c => n1816, d => n3187, outb
=> n1819);
U2944 : aoi22 port map( a => n1819, b => mult_125_ab_9_10_port, c => n4544,
d => n3190, outb => n4543);
U2945 : inv port map( inb => mult_125_ab_10_10_port, outb => n4545);
U2946 : oai22 port map( a => n4543, b => n4545, c => n1820, d => n3193, outb
=> n1823);
U2947 : aoi22 port map( a => n1823, b => mult_125_ab_11_10_port, c => n4547,
d => n3196, outb => n4546);
U2948 : inv port map( inb => mult_125_ab_12_10_port, outb => n4548);
U2949 : oai22 port map( a => n4546, b => n4548, c => n1824, d => n3199, outb
=> n1827);
U2950 : aoi22 port map( a => n1827, b => mult_125_ab_13_10_port, c => n4550,
d => n3202, outb => n4549);
U2951 : inv port map( inb => mult_125_ab_14_10_port, outb => n4551);
U2952 : oai22 port map( a => n4549, b => n4551, c => n1828, d => n3205, outb
=> n1831);
U2953 : nand2 port map( a => mult_125_ab_0_10_port, b =>
mult_125_ab_1_9_port, outb => n1834);
U2954 : aoi22 port map( a => mult_125_ab_2_9_port, b => n4553, c => n1832, d
=> n3213, outb => n4552);
U2955 : oai22 port map( a => n4552, b => n4554, c => n1835, d => n3214, outb
=> n1838);
U2956 : oai22 port map( a => n4555, b => n4556, c => n1837, d => n3227, outb
=> n1840);
U2957 : aoi22 port map( a => n1840, b => mult_125_ab_5_9_port, c => n4558, d
=> n3216, outb => n4557);
U2958 : oai22 port map( a => n4557, b => n4559, c => n1841, d => n3230, outb
=> n1844);
U2959 : aoi22 port map( a => n1844, b => mult_125_ab_7_9_port, c => n4561, d
=> n3219, outb => n4560);
U2960 : oai22 port map( a => n4560, b => n4562, c => n1845, d => n3233, outb
=> n1848);
U2961 : oai22 port map( a => n4563, b => n4564, c => n1847, d => n3236, outb
=> n1850);
U2962 : aoi22 port map( a => n1850, b => mult_125_ab_10_9_port, c => n4566,
d => n3239, outb => n4565);
U2963 : inv port map( inb => mult_125_ab_11_9_port, outb => n4567);
U2964 : oai22 port map( a => n4565, b => n4567, c => n1851, d => n3242, outb
=> n1854);
U2965 : aoi22 port map( a => n1854, b => mult_125_ab_12_9_port, c => n4569,
d => n3245, outb => n4568);
U2966 : inv port map( inb => mult_125_ab_13_9_port, outb => n4570);
U2967 : oai22 port map( a => n4568, b => n4570, c => n1855, d => n3248, outb
=> n1858);
U2968 : aoi22 port map( a => n1858, b => mult_125_ab_14_9_port, c => n4571,
d => n3251, outb => n1861);
U2969 : nand2 port map( a => mult_125_ab_0_9_port, b => mult_125_ab_1_8_port
, outb => n1864);
U2970 : aoi22 port map( a => mult_125_ab_2_8_port, b => n4573, c => n1862, d
=> n3222, outb => n4572);
U2971 : oai22 port map( a => n4572, b => n4574, c => n1865, d => n3223, outb
=> n1868);
U2972 : oai22 port map( a => n4575, b => n4576, c => n1867, d => n3259, outb
=> n1870);
U2973 : oai22 port map( a => n4577, b => n4578, c => n1869, d => n3225, outb
=> n1872);
U2974 : aoi22 port map( a => n1872, b => mult_125_ab_6_8_port, c => n4580, d
=> n3262, outb => n4579);
U2975 : oai22 port map( a => n4579, b => n4581, c => n1873, d => n3228, outb
=> n1876);
U2976 : aoi22 port map( a => n1876, b => mult_125_ab_8_8_port, c => n4583, d
=> n3265, outb => n4582);
U2977 : oai22 port map( a => n4582, b => n4584, c => n1877, d => n3231, outb
=> n1880);
U2978 : inv port map( inb => mult_125_ab_10_8_port, outb => n4585);
U2979 : oai22 port map( a => n4586, b => n4585, c => n1879, d => n3234, outb
=> n1882);
U2980 : aoi22 port map( a => n1882, b => mult_125_ab_11_8_port, c => n4588,
d => n3237, outb => n4587);
U2981 : inv port map( inb => mult_125_ab_12_8_port, outb => n4589);
U2982 : oai22 port map( a => n4587, b => n4589, c => n1883, d => n3240, outb
=> n1886);
U2983 : aoi22 port map( a => n1886, b => mult_125_ab_13_8_port, c => n4591,
d => n3243, outb => n4590);
U2984 : inv port map( inb => mult_125_ab_14_8_port, outb => n4592);
U2985 : oai22 port map( a => n4590, b => n4592, c => n1887, d => n3246, outb
=> n1890);
U2986 : nand2 port map( a => mult_125_ab_0_8_port, b => mult_125_ab_1_7_port
, outb => n1893);
U2987 : aoi22 port map( a => mult_125_ab_2_7_port, b => n4593, c => n1891, d
=> n3254, outb => n1896);
U2988 : oai22 port map( a => n1896, b => n1895, c => n4594, d => n3255, outb
=> n1898);
U2989 : oai22 port map( a => n4595, b => n4596, c => n1897, d => n3271, outb
=> n1900);
U2990 : aoi22 port map( a => n1900, b => mult_125_ab_5_7_port, c => n4598, d
=> n3257, outb => n4597);
U2991 : oai22 port map( a => n4597, b => n4599, c => n1901, d => n3274, outb
=> n1904);
U2992 : aoi22 port map( a => n1904, b => mult_125_ab_7_7_port, c => n4601, d
=> n3260, outb => n4600);
U2993 : oai22 port map( a => n4600, b => n4602, c => n1905, d => n3277, outb
=> n1908);
U2994 : aoi22 port map( a => n1908, b => mult_125_ab_9_7_port, c => n4604, d
=> n3263, outb => n4603);
U2995 : oai22 port map( a => n4603, b => n4605, c => n1909, d => n3280, outb
=> n1912);
U2996 : oai22 port map( a => n4606, b => n4607, c => n1911, d => n3283, outb
=> n1914);
U2997 : aoi22 port map( a => n1914, b => mult_125_ab_12_7_port, c => n4609,
d => n3286, outb => n4608);
U2998 : inv port map( inb => mult_125_ab_13_7_port, outb => n4610);
U2999 : oai22 port map( a => n4608, b => n4610, c => n1915, d => n3289, outb
=> n1918);
U3000 : aoi22 port map( a => n1918, b => mult_125_ab_14_7_port, c => n4611,
d => n3292, outb => n1921);
U3001 : nand2 port map( a => mult_125_ab_0_7_port, b => mult_125_ab_1_6_port
, outb => n1924);
U3002 : aoi22 port map( a => mult_125_ab_2_6_port, b => n4613, c => n1922, d
=> n3266, outb => n4612);
U3003 : oai22 port map( a => n4612, b => n4614, c => n1925, d => n3267, outb
=> n1928);
U3004 : aoi22 port map( a => n1928, b => mult_125_ab_4_6_port, c => n4615, d
=> n3300, outb => n1931);
U3005 : oai22 port map( a => n1931, b => n1930, c => n4616, d => n3269, outb
=> n1933);
U3006 : aoi22 port map( a => n1933, b => mult_125_ab_6_6_port, c => n4618, d
=> n3303, outb => n4617);
U3007 : oai22 port map( a => n4617, b => n4619, c => n1934, d => n3272, outb
=> n1937);
U3008 : aoi22 port map( a => n1937, b => mult_125_ab_8_6_port, c => n4620, d
=> n3306, outb => n1940);
U3009 : oai22 port map( a => n1940, b => n1939, c => n4621, d => n3275, outb
=> n1942);
U3010 : aoi22 port map( a => n1942, b => mult_125_ab_10_6_port, c => n4623,
d => n3309, outb => n4622);
U3011 : oai22 port map( a => n4622, b => n4624, c => n1943, d => n3278, outb
=> n1946);
U3012 : inv port map( inb => mult_125_ab_12_6_port, outb => n4625);
U3013 : oai22 port map( a => n4626, b => n4625, c => n1945, d => n3281, outb
=> n1948);
U3014 : aoi22 port map( a => n1948, b => mult_125_ab_13_6_port, c => n4628,
d => n3284, outb => n4627);
U3015 : inv port map( inb => mult_125_ab_14_6_port, outb => n4629);
U3016 : oai22 port map( a => n4627, b => n4629, c => n1949, d => n3287, outb
=> n1952);
U3017 : nand2 port map( a => mult_125_ab_0_6_port, b => mult_125_ab_1_5_port
, outb => n1955);
U3018 : aoi22 port map( a => mult_125_ab_2_5_port, b => n4630, c => n1953, d
=> n3295, outb => n1958);
U3019 : oai22 port map( a => n1958, b => n1957, c => n4631, d => n3296, outb
=> n1960);
U3020 : oai22 port map( a => n4632, b => n4633, c => n1959, d => n3315, outb
=> n1962);
U3021 : aoi22 port map( a => n1962, b => mult_125_ab_5_5_port, c => n4634, d
=> n3298, outb => n1965);
U3022 : oai22 port map( a => n1965, b => n1964, c => n4635, d => n3318, outb
=> n1967);
U3023 : aoi22 port map( a => n1967, b => mult_125_ab_7_5_port, c => n4637, d
=> n3301, outb => n4636);
U3024 : oai22 port map( a => n4636, b => n4638, c => n1968, d => n3321, outb
=> n1971);
U3025 : aoi22 port map( a => n1971, b => mult_125_ab_9_5_port, c => n4640, d
=> n3304, outb => n4639);
U3026 : oai22 port map( a => n4639, b => n4641, c => n1972, d => n3324, outb
=> n1975);
U3027 : aoi22 port map( a => n1975, b => mult_125_ab_11_5_port, c => n4643,
d => n3307, outb => n4642);
U3028 : oai22 port map( a => n4642, b => n4644, c => n1976, d => n3327, outb
=> n1979);
U3029 : oai22 port map( a => n4645, b => n4646, c => n1978, d => n3330, outb
=> n1981);
U3030 : aoi22 port map( a => n1981, b => mult_125_ab_14_5_port, c => n4647,
d => n3333, outb => n1984);
U3031 : nand2 port map( a => mult_125_ab_0_5_port, b => mult_125_ab_1_4_port
, outb => n1987);
U3032 : aoi22 port map( a => mult_125_ab_2_4_port, b => n4649, c => n1985, d
=> n3310, outb => n4648);
U3033 : oai22 port map( a => n4648, b => n4650, c => n1988, d => n3311, outb
=> n1991);
U3034 : aoi22 port map( a => n1991, b => mult_125_ab_4_4_port, c => n4651, d
=> n3341, outb => n1994);
U3035 : oai22 port map( a => n1994, b => n1993, c => n4652, d => n3313, outb
=> n1996);
U3036 : aoi22 port map( a => n1996, b => mult_125_ab_6_4_port, c => n4653, d
=> n3344, outb => n1999);
U3037 : oai22 port map( a => n1999, b => n1998, c => n4654, d => n3316, outb
=> n2001);
U3038 : aoi22 port map( a => n2001, b => mult_125_ab_8_4_port, c => n4656, d
=> n3347, outb => n4655);
U3039 : oai22 port map( a => n4655, b => n4657, c => n2002, d => n3319, outb
=> n2005);
U3040 : aoi22 port map( a => n2005, b => mult_125_ab_10_4_port, c => n4658,
d => n3350, outb => n2008);
U3041 : oai22 port map( a => n2008, b => n2007, c => n4659, d => n3322, outb
=> n2010);
U3042 : aoi22 port map( a => n2010, b => mult_125_ab_12_4_port, c => n4661,
d => n3353, outb => n4660);
U3043 : oai22 port map( a => n4660, b => n4662, c => n2011, d => n3325, outb
=> n2014);
U3044 : aoi22 port map( a => n2014, b => mult_125_ab_14_4_port, c => n4663,
d => n3328, outb => n2017);
U3045 : nand2 port map( a => mult_125_ab_0_4_port, b => mult_125_ab_1_3_port
, outb => n2020);
U3046 : aoi22 port map( a => mult_125_ab_2_3_port, b => n4664, c => n2018, d
=> n3336, outb => n2023);
U3047 : oai22 port map( a => n2023, b => n2022, c => n4665, d => n3337, outb
=> n2025);
U3048 : oai22 port map( a => n4666, b => n4667, c => n2024, d => n3359, outb
=> n2027);
U3049 : aoi22 port map( a => n2027, b => mult_125_ab_5_3_port, c => n4669, d
=> n3339, outb => n4668);
U3050 : oai22 port map( a => n4668, b => n4670, c => n2028, d => n3362, outb
=> n2031);
U3051 : aoi22 port map( a => n2031, b => mult_125_ab_7_3_port, c => n4672, d
=> n3342, outb => n4671);
U3052 : oai22 port map( a => n4671, b => n4673, c => n2032, d => n3365, outb
=> n2035);
U3053 : aoi22 port map( a => n2035, b => mult_125_ab_9_3_port, c => n4675, d
=> n3345, outb => n4674);
U3054 : oai22 port map( a => n4674, b => n4676, c => n2036, d => n3368, outb
=> n2039);
U3055 : aoi22 port map( a => n2039, b => mult_125_ab_11_3_port, c => n4678,
d => n3348, outb => n4677);
U3056 : oai22 port map( a => n4677, b => n4679, c => n2040, d => n3371, outb
=> n2043);
U3057 : aoi22 port map( a => n2043, b => mult_125_ab_13_3_port, c => n4681,
d => n3351, outb => n4680);
U3058 : inv port map( inb => mult_125_ab_14_3_port, outb => n4682);
U3059 : oai22 port map( a => n4680, b => n4682, c => n2044, d => n3374, outb
=> n2047);
U3060 : nand2 port map( a => mult_125_ab_0_3_port, b => mult_125_ab_1_2_port
, outb => n2050);
U3061 : aoi22 port map( a => mult_125_ab_2_2_port, b => n4684, c => n2048, d
=> n3354, outb => n4683);
U3062 : oai22 port map( a => n4683, b => n4685, c => n2051, d => n3355, outb
=> n2054);
U3063 : aoi22 port map( a => n2054, b => mult_125_ab_4_2_port, c => n4687, d
=> n3382, outb => n4686);
U3064 : oai22 port map( a => n4686, b => n4688, c => n2055, d => n3357, outb
=> n2058);
U3065 : aoi22 port map( a => n2058, b => mult_125_ab_6_2_port, c => n4689, d
=> n3385, outb => n2061);
U3066 : oai22 port map( a => n2061, b => n2060, c => n4690, d => n3360, outb
=> n2063);
U3067 : aoi22 port map( a => n2063, b => mult_125_ab_8_2_port, c => n4692, d
=> n3388, outb => n4691);
U3068 : oai22 port map( a => n4691, b => n4693, c => n2064, d => n3363, outb
=> n2067);
U3069 : aoi22 port map( a => n2067, b => mult_125_ab_10_2_port, c => n4695,
d => n3391, outb => n4694);
U3070 : oai22 port map( a => n4694, b => n4696, c => n2068, d => n3366, outb
=> n2071);
U3071 : aoi22 port map( a => n2071, b => mult_125_ab_12_2_port, c => n4698,
d => n3394, outb => n4697);
U3072 : oai22 port map( a => n4697, b => n4699, c => n2072, d => n3369, outb
=> n2075);
U3073 : aoi22 port map( a => n2075, b => mult_125_ab_14_2_port, c => n4701,
d => n3397, outb => n4700);
U3074 : nand2 port map( a => mult_125_ab_0_2_port, b => mult_125_ab_1_1_port
, outb => n2080);
U3075 : aoi22 port map( a => mult_125_ab_2_1_port, b => n4703, c => n2078, d
=> n3377, outb => n4702);
U3076 : oai22 port map( a => n4702, b => n4704, c => n2081, d => n3378, outb
=> n2084);
U3077 : inv port map( inb => mult_125_ab_4_1_port, outb => n4705);
U3078 : oai22 port map( a => n4706, b => n4705, c => n2083, d => n3403, outb
=> n2086);
U3079 : aoi22 port map( a => n2086, b => mult_125_ab_5_1_port, c => n4708, d
=> n3380, outb => n4707);
U3080 : oai22 port map( a => n4707, b => n4709, c => n2087, d => n3406, outb
=> n2090);
U3081 : aoi22 port map( a => n2090, b => mult_125_ab_7_1_port, c => n4711, d
=> n3383, outb => n4710);
U3082 : oai22 port map( a => n4710, b => n4712, c => n2091, d => n3409, outb
=> n2094);
U3083 : aoi22 port map( a => n2094, b => mult_125_ab_9_1_port, c => n4714, d
=> n3386, outb => n4713);
U3084 : oai22 port map( a => n4713, b => n4715, c => n2095, d => n3412, outb
=> n2098);
U3085 : aoi22 port map( a => n2098, b => mult_125_ab_11_1_port, c => n4717,
d => n3389, outb => n4716);
U3086 : oai22 port map( a => n4716, b => n4718, c => n2099, d => n3415, outb
=> n2102);
U3087 : aoi22 port map( a => n2102, b => mult_125_ab_13_1_port, c => n4720,
d => n3392, outb => n4719);
U3088 : inv port map( inb => mult_125_ab_14_1_port, outb => n4721);
U3089 : oai22 port map( a => n4719, b => n4721, c => n2103, d => n3418, outb
=> n2106);
U3090 : nand2 port map( a => mult_125_ab_0_1_port, b => mult_125_ab_1_0_port
, outb => n4722);
U3091 : aoi22 port map( a => mult_125_ab_2_0_port, b => n2108, c => n4724, d
=> n3398, outb => n4723);
U3092 : aoi22 port map( a => n2110, b => mult_125_ab_3_0_port, c => n4726, d
=> n3399, outb => n4725);
U3093 : inv port map( inb => mult_125_ab_4_0_port, outb => n4727);
U3094 : oai22 port map( a => n4725, b => n4727, c => n2111, d => n4728, outb
=> n2114);
U3095 : aoi22 port map( a => n2114, b => mult_125_ab_5_0_port, c => n4730, d
=> n3401, outb => n4729);
U3096 : inv port map( inb => mult_125_ab_6_0_port, outb => n4731);
U3097 : oai22 port map( a => n4729, b => n4731, c => n2115, d => n4732, outb
=> n2118);
U3098 : aoi22 port map( a => n2118, b => mult_125_ab_7_0_port, c => n4734, d
=> n3404, outb => n4733);
U3099 : inv port map( inb => mult_125_ab_8_0_port, outb => n4735);
U3100 : oai22 port map( a => n4733, b => n4735, c => n2119, d => n4736, outb
=> n2122);
U3101 : aoi22 port map( a => n2122, b => mult_125_ab_9_0_port, c => n4738, d
=> n3407, outb => n4737);
U3102 : inv port map( inb => mult_125_ab_10_0_port, outb => n4739);
U3103 : oai22 port map( a => n4737, b => n4739, c => n2123, d => n4740, outb
=> n2126);
U3104 : aoi22 port map( a => n2126, b => mult_125_ab_11_0_port, c => n4742,
d => n3410, outb => n4741);
U3105 : inv port map( inb => mult_125_ab_12_0_port, outb => n4743);
U3106 : oai22 port map( a => n4741, b => n4743, c => n2127, d => n4744, outb
=> n2130);
U3107 : aoi22 port map( a => n2130, b => mult_125_ab_13_0_port, c => n4746,
d => n3413, outb => n4745);
U3108 : inv port map( inb => mult_125_ab_14_0_port, outb => n4747);
U3109 : oai22 port map( a => n4745, b => n4747, c => n2131, d => n4748, outb
=> n2134);
U3110 : inv port map( inb => mult_125_ZB, outb => n308);
U3111 : inv port map( inb => mult_125_ZA, outb => n309);
U3112 : nand2 port map( a => adder_mem_array_3_0_port, b =>
multiplier_sigs_2_0_port, outb => n4749);
U3113 : inv port map( inb => multiplier_sigs_2_2_port, outb => n4750);
U3114 : inv port map( inb => adder_mem_array_3_2_port, outb => n4751);
U3115 : inv port map( inb => multiplier_sigs_2_4_port, outb => n4752);
U3116 : inv port map( inb => adder_mem_array_3_4_port, outb => n4753);
U3117 : inv port map( inb => multiplier_sigs_2_6_port, outb => n4754);
U3118 : inv port map( inb => adder_mem_array_3_6_port, outb => n4755);
U3119 : inv port map( inb => multiplier_sigs_2_8_port, outb => n4756);
U3120 : inv port map( inb => adder_mem_array_3_8_port, outb => n4757);
U3121 : inv port map( inb => multiplier_sigs_2_10_port, outb => n4758);
U3122 : inv port map( inb => adder_mem_array_3_10_port, outb => n4759);
U3123 : inv port map( inb => multiplier_sigs_2_12_port, outb => n4760);
U3124 : inv port map( inb => adder_mem_array_3_12_port, outb => n4761);
U3125 : inv port map( inb => multiplier_sigs_2_14_port, outb => n4762);
U3126 : inv port map( inb => adder_mem_array_3_14_port, outb => n4763);
U3127 : inv port map( inb => multiplier_sigs_2_16_port, outb => n4764);
U3128 : inv port map( inb => adder_mem_array_3_16_port, outb => n4765);
U3129 : inv port map( inb => multiplier_sigs_2_18_port, outb => n4766);
U3130 : inv port map( inb => adder_mem_array_3_18_port, outb => n4767);
U3131 : inv port map( inb => multiplier_sigs_2_20_port, outb => n4768);
U3132 : inv port map( inb => adder_mem_array_3_20_port, outb => n4769);
U3133 : inv port map( inb => multiplier_sigs_2_22_port, outb => n4770);
U3134 : inv port map( inb => adder_mem_array_3_22_port, outb => n4771);
U3135 : inv port map( inb => multiplier_sigs_2_24_port, outb => n4772);
U3136 : inv port map( inb => adder_mem_array_3_24_port, outb => n4773);
U3137 : inv port map( inb => multiplier_sigs_2_26_port, outb => n4774);
U3138 : inv port map( inb => adder_mem_array_3_26_port, outb => n4775);
U3139 : nand2 port map( a => adder_mem_array_1_0_port, b =>
multiplier_sigs_0_0_port, outb => n4776);
U3140 : inv port map( inb => multiplier_sigs_0_2_port, outb => n4777);
U3141 : inv port map( inb => adder_mem_array_1_2_port, outb => n4778);
U3142 : nand2 port map( a => adder_mem_array_2_0_port, b =>
multiplier_sigs_1_0_port, outb => n4779);
U3143 : inv port map( inb => multiplier_sigs_1_2_port, outb => n4780);
U3144 : inv port map( inb => adder_mem_array_2_2_port, outb => n4781);
U3145 : inv port map( inb => multiplier_sigs_1_4_port, outb => n4782);
U3146 : inv port map( inb => adder_mem_array_2_4_port, outb => n4783);
U3147 : inv port map( inb => multiplier_sigs_1_6_port, outb => n4784);
U3148 : inv port map( inb => adder_mem_array_2_6_port, outb => n4785);
U3149 : inv port map( inb => multiplier_sigs_1_8_port, outb => n4786);
U3150 : inv port map( inb => adder_mem_array_2_8_port, outb => n4787);
U3151 : inv port map( inb => multiplier_sigs_1_10_port, outb => n4788);
U3152 : inv port map( inb => adder_mem_array_2_10_port, outb => n4789);
U3153 : inv port map( inb => multiplier_sigs_1_12_port, outb => n4790);
U3154 : inv port map( inb => adder_mem_array_2_12_port, outb => n4791);
U3155 : inv port map( inb => multiplier_sigs_1_14_port, outb => n4792);
U3156 : inv port map( inb => adder_mem_array_2_14_port, outb => n4793);
U3157 : inv port map( inb => multiplier_sigs_1_16_port, outb => n4794);
U3158 : inv port map( inb => adder_mem_array_2_16_port, outb => n4795);
U3159 : inv port map( inb => multiplier_sigs_1_18_port, outb => n4796);
U3160 : inv port map( inb => adder_mem_array_2_18_port, outb => n4797);
U3161 : inv port map( inb => multiplier_sigs_1_20_port, outb => n4798);
U3162 : inv port map( inb => adder_mem_array_2_20_port, outb => n4799);
U3163 : inv port map( inb => multiplier_sigs_1_22_port, outb => n4800);
U3164 : inv port map( inb => adder_mem_array_2_22_port, outb => n4801);
U3165 : inv port map( inb => multiplier_sigs_1_24_port, outb => n4802);
U3166 : inv port map( inb => adder_mem_array_2_24_port, outb => n4803);
U3167 : inv port map( inb => multiplier_sigs_1_26_port, outb => n4804);
U3168 : inv port map( inb => adder_mem_array_2_26_port, outb => n4805);
U3169 : inv port map( inb => multiplier_sigs_1_28_port, outb => n4806);
U3170 : inv port map( inb => adder_mem_array_2_28_port, outb => n4807);
U3171 : inv port map( inb => multiplier_sigs_1_30_port, outb => n4808);
U3172 : inv port map( inb => adder_mem_array_2_30_port, outb => n4809);
U3173 : inv port map( inb => multiplier_sigs_0_4_port, outb => n4810);
U3174 : inv port map( inb => adder_mem_array_1_4_port, outb => n4811);
U3175 : inv port map( inb => multiplier_sigs_0_6_port, outb => n4812);
U3176 : inv port map( inb => adder_mem_array_1_6_port, outb => n4813);
U3177 : inv port map( inb => multiplier_sigs_0_8_port, outb => n4814);
U3178 : inv port map( inb => adder_mem_array_1_8_port, outb => n4815);
U3179 : inv port map( inb => multiplier_sigs_0_10_port, outb => n4816);
U3180 : inv port map( inb => adder_mem_array_1_10_port, outb => n4817);
U3181 : inv port map( inb => multiplier_sigs_0_12_port, outb => n4818);
U3182 : inv port map( inb => adder_mem_array_1_12_port, outb => n4819);
U3183 : inv port map( inb => multiplier_sigs_0_14_port, outb => n4820);
U3184 : inv port map( inb => adder_mem_array_1_14_port, outb => n4821);
U3185 : inv port map( inb => multiplier_sigs_0_16_port, outb => n4822);
U3186 : inv port map( inb => adder_mem_array_1_16_port, outb => n4823);
U3187 : inv port map( inb => multiplier_sigs_0_18_port, outb => n4824);
U3188 : inv port map( inb => adder_mem_array_1_18_port, outb => n4825);
U3189 : inv port map( inb => multiplier_sigs_0_20_port, outb => n4826);
U3190 : inv port map( inb => adder_mem_array_1_20_port, outb => n4827);
U3191 : inv port map( inb => multiplier_sigs_0_22_port, outb => n4828);
U3192 : inv port map( inb => adder_mem_array_1_22_port, outb => n4829);
U3193 : inv port map( inb => multiplier_sigs_0_24_port, outb => n4830);
U3194 : inv port map( inb => adder_mem_array_1_24_port, outb => n4831);
U3195 : inv port map( inb => multiplier_sigs_0_26_port, outb => n4832);
U3196 : inv port map( inb => adder_mem_array_1_26_port, outb => n4833);
U3197 : inv port map( inb => multiplier_sigs_0_28_port, outb => n4834);
U3198 : inv port map( inb => adder_mem_array_1_28_port, outb => n4835);
U3199 : inv port map( inb => multiplier_sigs_0_30_port, outb => n4836);
U3200 : inv port map( inb => adder_mem_array_1_30_port, outb => n4837);
U3201 : inv port map( inb => multiplier_sigs_2_28_port, outb => n4838);
U3202 : inv port map( inb => adder_mem_array_3_28_port, outb => n4839);
U3203 : inv port map( inb => multiplier_sigs_2_30_port, outb => n4840);
U3204 : inv port map( inb => adder_mem_array_3_30_port, outb => n4841);
U3205 : xor2 port map( a => mult_125_G4_ab_0_1_port, b =>
mult_125_G4_ab_1_0_port, outb =>
multiplier_sigs_3_1_port);
U3206 : xor2 port map( a => n3885, b => n4842, outb => mult_125_G4_A1_8_port
);
U3207 : xor2 port map( a => n3881, b => n4843, outb => mult_125_G4_A1_6_port
);
U3208 : xor2 port map( a => n3877, b => n4844, outb => mult_125_G4_A1_4_port
);
U3209 : xor2 port map( a => n3873, b => n4845, outb => mult_125_G4_A1_2_port
);
U3210 : xor2 port map( a => n243, b => n244, outb => mult_125_G4_A1_27_port)
;
U3211 : xor2 port map( a => n247, b => n248, outb => mult_125_G4_A1_25_port)
;
U3212 : xor2 port map( a => n251, b => n252, outb => mult_125_G4_A1_23_port)
;
U3213 : xor2 port map( a => n255, b => n256, outb => mult_125_G4_A1_21_port)
;
U3214 : xor2 port map( a => n259, b => n260, outb => mult_125_G4_A1_19_port)
;
U3215 : xor2 port map( a => n263, b => n264, outb => mult_125_G4_A1_17_port)
;
U3216 : xor2 port map( a => n268, b => n269, outb => mult_125_G4_A1_15_port)
;
U3217 : xor2 port map( a => n270, b => n271, outb => mult_125_G4_A1_14_port)
;
U3218 : xor2 port map( a => n3893, b => n4846, outb =>
mult_125_G4_A1_12_port);
U3219 : xor2 port map( a => n3889, b => n4847, outb =>
mult_125_G4_A1_10_port);
U3220 : xor2 port map( a => n2507, b => n4848, outb => mult_125_G4_A1_0_port
);
U3221 : xor2 port map( a => n4170, b => n4849, outb => mult_125_G3_A1_8_port
);
U3222 : xor2 port map( a => n4166, b => n4850, outb => mult_125_G3_A1_6_port
);
U3223 : xor2 port map( a => n4162, b => n4851, outb => mult_125_G3_A1_4_port
);
U3224 : xor2 port map( a => n4158, b => n4852, outb => mult_125_G3_A1_2_port
);
U3225 : xor2 port map( a => n351, b => n352, outb => mult_125_G3_A1_27_port)
;
U3226 : xor2 port map( a => n355, b => n356, outb => mult_125_G3_A1_25_port)
;
U3227 : xor2 port map( a => n359, b => n360, outb => mult_125_G3_A1_23_port)
;
U3228 : xor2 port map( a => n363, b => n364, outb => mult_125_G3_A1_21_port)
;
U3229 : xor2 port map( a => n367, b => n368, outb => mult_125_G3_A1_19_port)
;
U3230 : xor2 port map( a => n371, b => n372, outb => mult_125_G3_A1_17_port)
;
U3231 : xor2 port map( a => n376, b => n377, outb => mult_125_G3_A1_15_port)
;
U3232 : xor2 port map( a => n378, b => n379, outb => mult_125_G3_A1_14_port)
;
U3233 : xor2 port map( a => n4178, b => n4853, outb =>
mult_125_G3_A1_12_port);
U3234 : xor2 port map( a => n4174, b => n4854, outb =>
mult_125_G3_A1_10_port);
U3235 : xor2 port map( a => n2804, b => n4855, outb => mult_125_G3_A1_0_port
);
U3236 : xor2 port map( a => n4455, b => n4856, outb => mult_125_G2_A1_8_port
);
U3237 : xor2 port map( a => n4451, b => n4857, outb => mult_125_G2_A1_6_port
);
U3238 : xor2 port map( a => n4447, b => n4858, outb => mult_125_G2_A1_4_port
);
U3239 : xor2 port map( a => n4443, b => n4859, outb => mult_125_G2_A1_2_port
);
U3240 : xor2 port map( a => n315, b => n316, outb => mult_125_G2_A1_27_port)
;
U3241 : xor2 port map( a => n319, b => n320, outb => mult_125_G2_A1_25_port)
;
U3242 : xor2 port map( a => n323, b => n324, outb => mult_125_G2_A1_23_port)
;
U3243 : xor2 port map( a => n327, b => n328, outb => mult_125_G2_A1_21_port)
;
U3244 : xor2 port map( a => n331, b => n332, outb => mult_125_G2_A1_19_port)
;
U3245 : xor2 port map( a => n335, b => n336, outb => mult_125_G2_A1_17_port)
;
U3246 : xor2 port map( a => n340, b => n341, outb => mult_125_G2_A1_15_port)
;
U3247 : xor2 port map( a => n342, b => n343, outb => mult_125_G2_A1_14_port)
;
U3248 : xor2 port map( a => n4463, b => n4860, outb =>
mult_125_G2_A1_12_port);
U3249 : xor2 port map( a => n4459, b => n4861, outb =>
mult_125_G2_A1_10_port);
U3250 : xor2 port map( a => n3101, b => n4862, outb => mult_125_G2_A1_0_port
);
U3251 : xor2 port map( a => n4740, b => n4863, outb => mult_125_A1_8_port);
U3252 : xor2 port map( a => n4736, b => n4864, outb => mult_125_A1_6_port);
U3253 : xor2 port map( a => n4732, b => n4865, outb => mult_125_A1_4_port);
U3254 : xor2 port map( a => n4728, b => n4866, outb => mult_125_A1_2_port);
U3255 : xor2 port map( a => n279, b => n280, outb => mult_125_A1_27_port);
U3256 : xor2 port map( a => n283, b => n284, outb => mult_125_A1_25_port);
U3257 : xor2 port map( a => n287, b => n288, outb => mult_125_A1_23_port);
U3258 : xor2 port map( a => n291, b => n292, outb => mult_125_A1_21_port);
U3259 : xor2 port map( a => n295, b => n296, outb => mult_125_A1_19_port);
U3260 : xor2 port map( a => n299, b => n300, outb => mult_125_A1_17_port);
U3261 : xor2 port map( a => n304, b => n305, outb => mult_125_A1_15_port);
U3262 : xor2 port map( a => n306, b => n307, outb => mult_125_A1_14_port);
U3263 : xor2 port map( a => n4748, b => n4867, outb => mult_125_A1_12_port);
U3264 : xor2 port map( a => n4744, b => n4868, outb => mult_125_A1_10_port);
U3265 : xor2 port map( a => n3398, b => n4869, outb => mult_125_A1_0_port);
U3266 : xor2 port map( a => n3426, b => n4870, outb => N73);
U3267 : xor2 port map( a => adder_mem_array_3_0_port, b =>
multiplier_sigs_2_0_port, outb => N72);
U3268 : xor2 port map( a => n3447, b => n4871, outb => N7);
U3269 : xor2 port map( a => adder_mem_array_1_0_port, b =>
multiplier_sigs_0_0_port, outb => N6);
U3270 : xor2 port map( a => n3484, b => n4872, outb => N40);
U3271 : xor2 port map( a => adder_mem_array_2_0_port, b =>
multiplier_sigs_1_0_port, outb => N39);
U3272 : xor2 port map( a => mult_125_G4_QA, b => mult_125_G4_QB, outb =>
n2239);
U3273 : xor2 port map( a => mult_125_G4_ab_3_14_port, b =>
mult_125_G4_ab_2_15_port, outb => n4873);
U3274 : xor2 port map( a => mult_125_G4_ab_5_14_port, b =>
mult_125_G4_ab_4_15_port, outb => n4874);
U3275 : xor2 port map( a => mult_125_G4_ab_7_14_port, b =>
mult_125_G4_ab_6_15_port, outb => n4875);
U3276 : xor2 port map( a => mult_125_G4_ab_9_14_port, b =>
mult_125_G4_ab_8_15_port, outb => n4876);
U3277 : xor2 port map( a => mult_125_G4_ab_11_14_port, b =>
mult_125_G4_ab_10_15_port, outb => n4877);
U3278 : xor2 port map( a => mult_125_G4_ab_13_14_port, b =>
mult_125_G4_ab_12_15_port, outb => n4878);
U3279 : xor2 port map( a => mult_125_G4_ab_15_14_port, b =>
mult_125_G4_ab_14_15_port, outb => n4879);
U3280 : xor2 port map( a => mult_125_G4_ab_10_0_port, b => n3882, outb =>
n4842);
U3281 : xor2 port map( a => mult_125_G4_ab_8_0_port, b => n3878, outb =>
n4843);
U3282 : xor2 port map( a => mult_125_G4_ab_6_0_port, b => n3874, outb =>
n4844);
U3283 : xor2 port map( a => n3872, b => n798, outb => n4845);
U3284 : xor2 port map( a => mult_125_G4_ab_14_0_port, b => n3890, outb =>
n4846);
U3285 : xor2 port map( a => mult_125_G4_ab_12_0_port, b => n3886, outb =>
n4847);
U3286 : xor2 port map( a => n794, b => mult_125_G4_ab_2_0_port, outb =>
n4848);
U3287 : xor2 port map( a => mult_125_G3_QA, b => mult_125_G3_QB, outb =>
n2536);
U3288 : xor2 port map( a => mult_125_G3_ab_3_14_port, b =>
mult_125_G3_ab_2_15_port, outb => n4880);
U3289 : xor2 port map( a => mult_125_G3_ab_5_14_port, b =>
mult_125_G3_ab_4_15_port, outb => n4881);
U3290 : xor2 port map( a => mult_125_G3_ab_7_14_port, b =>
mult_125_G3_ab_6_15_port, outb => n4882);
U3291 : xor2 port map( a => mult_125_G3_ab_9_14_port, b =>
mult_125_G3_ab_8_15_port, outb => n4883);
U3292 : xor2 port map( a => mult_125_G3_ab_11_14_port, b =>
mult_125_G3_ab_10_15_port, outb => n4884);
U3293 : xor2 port map( a => mult_125_G3_ab_13_14_port, b =>
mult_125_G3_ab_12_15_port, outb => n4885);
U3294 : xor2 port map( a => mult_125_G3_ab_15_14_port, b =>
mult_125_G3_ab_14_15_port, outb => n4886);
U3295 : xor2 port map( a => mult_125_G3_ab_10_0_port, b => n4167, outb =>
n4849);
U3296 : xor2 port map( a => mult_125_G3_ab_8_0_port, b => n4163, outb =>
n4850);
U3297 : xor2 port map( a => mult_125_G3_ab_6_0_port, b => n4159, outb =>
n4851);
U3298 : xor2 port map( a => n4157, b => n1236, outb => n4852);
U3299 : xor2 port map( a => mult_125_G3_ab_14_0_port, b => n4175, outb =>
n4853);
U3300 : xor2 port map( a => mult_125_G3_ab_12_0_port, b => n4171, outb =>
n4854);
U3301 : xor2 port map( a => n1232, b => mult_125_G3_ab_2_0_port, outb =>
n4855);
U3302 : xor2 port map( a => mult_125_G2_QA, b => mult_125_G2_QB, outb =>
n2833);
U3303 : xor2 port map( a => mult_125_G2_ab_3_14_port, b =>
mult_125_G2_ab_2_15_port, outb => n4887);
U3304 : xor2 port map( a => mult_125_G2_ab_5_14_port, b =>
mult_125_G2_ab_4_15_port, outb => n4888);
U3305 : xor2 port map( a => mult_125_G2_ab_7_14_port, b =>
mult_125_G2_ab_6_15_port, outb => n4889);
U3306 : xor2 port map( a => mult_125_G2_ab_9_14_port, b =>
mult_125_G2_ab_8_15_port, outb => n4890);
U3307 : xor2 port map( a => mult_125_G2_ab_11_14_port, b =>
mult_125_G2_ab_10_15_port, outb => n4891);
U3308 : xor2 port map( a => mult_125_G2_ab_13_14_port, b =>
mult_125_G2_ab_12_15_port, outb => n4892);
U3309 : xor2 port map( a => mult_125_G2_ab_15_14_port, b =>
mult_125_G2_ab_14_15_port, outb => n4893);
U3310 : xor2 port map( a => mult_125_G2_ab_10_0_port, b => n4452, outb =>
n4856);
U3311 : xor2 port map( a => mult_125_G2_ab_8_0_port, b => n4448, outb =>
n4857);
U3312 : xor2 port map( a => mult_125_G2_ab_6_0_port, b => n4444, outb =>
n4858);
U3313 : xor2 port map( a => n4442, b => n1674, outb => n4859);
U3314 : xor2 port map( a => mult_125_G2_ab_14_0_port, b => n4460, outb =>
n4860);
U3315 : xor2 port map( a => mult_125_G2_ab_12_0_port, b => n4456, outb =>
n4861);
U3316 : xor2 port map( a => n1670, b => mult_125_G2_ab_2_0_port, outb =>
n4862);
U3317 : xor2 port map( a => mult_125_QA, b => mult_125_QB, outb => n3130);
U3318 : xor2 port map( a => mult_125_ab_3_14_port, b =>
mult_125_ab_2_15_port, outb => n4894);
U3319 : xor2 port map( a => mult_125_ab_5_14_port, b =>
mult_125_ab_4_15_port, outb => n4895);
U3320 : xor2 port map( a => mult_125_ab_7_14_port, b =>
mult_125_ab_6_15_port, outb => n4896);
U3321 : xor2 port map( a => mult_125_ab_9_14_port, b =>
mult_125_ab_8_15_port, outb => n4897);
U3322 : xor2 port map( a => mult_125_ab_11_14_port, b =>
mult_125_ab_10_15_port, outb => n4898);
U3323 : xor2 port map( a => mult_125_ab_13_14_port, b =>
mult_125_ab_12_15_port, outb => n4899);
U3324 : xor2 port map( a => mult_125_ab_15_14_port, b =>
mult_125_ab_14_15_port, outb => n4900);
U3325 : xor2 port map( a => mult_125_ab_10_0_port, b => n4737, outb => n4863
);
U3326 : xor2 port map( a => mult_125_ab_8_0_port, b => n4733, outb => n4864)
;
U3327 : xor2 port map( a => mult_125_ab_6_0_port, b => n4729, outb => n4865)
;
U3328 : xor2 port map( a => n4727, b => n2112, outb => n4866);
U3329 : xor2 port map( a => mult_125_ab_14_0_port, b => n4745, outb => n4867
);
U3330 : xor2 port map( a => mult_125_ab_12_0_port, b => n4741, outb => n4868
);
U3331 : xor2 port map( a => n2108, b => mult_125_ab_2_0_port, outb => n4869)
;
U3332 : xor2 port map( a => adder_mem_array_3_27_port, b =>
multiplier_sigs_2_27_port, outb => n3428);
U3333 : xor2 port map( a => adder_mem_array_3_25_port, b =>
multiplier_sigs_2_25_port, outb => n3432);
U3334 : xor2 port map( a => adder_mem_array_3_23_port, b =>
multiplier_sigs_2_23_port, outb => n3436);
U3335 : xor2 port map( a => adder_mem_array_3_21_port, b =>
multiplier_sigs_2_21_port, outb => n3440);
U3336 : xor2 port map( a => adder_mem_array_3_19_port, b =>
multiplier_sigs_2_19_port, outb => n3444);
U3337 : xor2 port map( a => adder_mem_array_1_3_port, b =>
multiplier_sigs_0_3_port, outb => n3449);
U3338 : xor2 port map( a => adder_mem_array_3_17_port, b =>
multiplier_sigs_2_17_port, outb => n3451);
U3339 : xor2 port map( a => adder_mem_array_3_15_port, b =>
multiplier_sigs_2_15_port, outb => n3455);
U3340 : xor2 port map( a => adder_mem_array_3_13_port, b =>
multiplier_sigs_2_13_port, outb => n3459);
U3341 : xor2 port map( a => adder_mem_array_3_11_port, b =>
multiplier_sigs_2_11_port, outb => n3463);
U3342 : xor2 port map( a => adder_mem_array_3_9_port, b =>
multiplier_sigs_2_9_port, outb => n3467);
U3343 : xor2 port map( a => adder_mem_array_3_7_port, b =>
multiplier_sigs_2_7_port, outb => n3473);
U3344 : xor2 port map( a => adder_mem_array_3_5_port, b =>
multiplier_sigs_2_5_port, outb => n3477);
U3345 : xor2 port map( a => adder_mem_array_3_3_port, b =>
multiplier_sigs_2_3_port, outb => n3481);
U3346 : xor2 port map( a => n2137, b => adder_mem_array_3_1_port, outb =>
n4870);
U3347 : xor2 port map( a => adder_mem_array_2_31_port, b =>
multiplier_sigs_1_31_port, outb => n3486);
U3348 : xor2 port map( a => n2164, b => adder_mem_array_1_1_port, outb =>
n4871);
U3349 : xor2 port map( a => adder_mem_array_2_29_port, b =>
multiplier_sigs_1_29_port, outb => n3490);
U3350 : xor2 port map( a => adder_mem_array_2_27_port, b =>
multiplier_sigs_1_27_port, outb => n3494);
U3351 : xor2 port map( a => adder_mem_array_2_25_port, b =>
multiplier_sigs_1_25_port, outb => n3498);
U3352 : xor2 port map( a => adder_mem_array_2_23_port, b =>
multiplier_sigs_1_23_port, outb => n3502);
U3353 : xor2 port map( a => adder_mem_array_2_21_port, b =>
multiplier_sigs_1_21_port, outb => n3506);
U3354 : xor2 port map( a => adder_mem_array_2_19_port, b =>
multiplier_sigs_1_19_port, outb => n3510);
U3355 : xor2 port map( a => adder_mem_array_2_17_port, b =>
multiplier_sigs_1_17_port, outb => n3514);
U3356 : xor2 port map( a => adder_mem_array_2_15_port, b =>
multiplier_sigs_1_15_port, outb => n3518);
U3357 : xor2 port map( a => adder_mem_array_2_13_port, b =>
multiplier_sigs_1_13_port, outb => n3522);
U3358 : xor2 port map( a => adder_mem_array_2_11_port, b =>
multiplier_sigs_1_11_port, outb => n3526);
U3359 : xor2 port map( a => adder_mem_array_2_9_port, b =>
multiplier_sigs_1_9_port, outb => n3530);
U3360 : xor2 port map( a => adder_mem_array_2_7_port, b =>
multiplier_sigs_1_7_port, outb => n3534);
U3361 : xor2 port map( a => adder_mem_array_2_5_port, b =>
multiplier_sigs_1_5_port, outb => n3538);
U3362 : xor2 port map( a => adder_mem_array_2_3_port, b =>
multiplier_sigs_1_3_port, outb => n3542);
U3363 : xor2 port map( a => n2167, b => adder_mem_array_2_1_port, outb =>
n4872);
U3364 : xor2 port map( a => adder_mem_array_1_31_port, b =>
multiplier_sigs_0_31_port, outb => n3546);
U3365 : xor2 port map( a => adder_mem_array_1_29_port, b =>
multiplier_sigs_0_29_port, outb => n3550);
U3366 : xor2 port map( a => adder_mem_array_1_27_port, b =>
multiplier_sigs_0_27_port, outb => n3554);
U3367 : xor2 port map( a => adder_mem_array_1_25_port, b =>
multiplier_sigs_0_25_port, outb => n3558);
U3368 : xor2 port map( a => adder_mem_array_1_23_port, b =>
multiplier_sigs_0_23_port, outb => n3562);
U3369 : xor2 port map( a => adder_mem_array_1_21_port, b =>
multiplier_sigs_0_21_port, outb => n3566);
U3370 : xor2 port map( a => adder_mem_array_1_19_port, b =>
multiplier_sigs_0_19_port, outb => n3570);
U3371 : xor2 port map( a => adder_mem_array_1_17_port, b =>
multiplier_sigs_0_17_port, outb => n3574);
U3372 : xor2 port map( a => adder_mem_array_1_15_port, b =>
multiplier_sigs_0_15_port, outb => n3578);
U3373 : xor2 port map( a => adder_mem_array_1_13_port, b =>
multiplier_sigs_0_13_port, outb => n3582);
U3374 : xor2 port map( a => adder_mem_array_1_11_port, b =>
multiplier_sigs_0_11_port, outb => n3586);
U3375 : xor2 port map( a => adder_mem_array_1_9_port, b =>
multiplier_sigs_0_9_port, outb => n3590);
U3376 : xor2 port map( a => adder_mem_array_1_7_port, b =>
multiplier_sigs_0_7_port, outb => n3594);
U3377 : xor2 port map( a => adder_mem_array_1_5_port, b =>
multiplier_sigs_0_5_port, outb => n3598);
U3378 : xor2 port map( a => adder_mem_array_3_31_port, b =>
multiplier_sigs_2_31_port, outb => n3600);
U3379 : xor2 port map( a => adder_mem_array_3_29_port, b =>
multiplier_sigs_2_29_port, outb => n3604);
U3380 : oai22 port map( a => n4902, b => n4903, c => n384, d => n3609, outb
=> n4901);
U3381 : aoi22 port map( a => mult_125_G4_ab_2_15_port, b =>
mult_125_G4_ab_3_14_port, c => n4901, d => n4905,
outb => n4904);
U3382 : oai22 port map( a => n3610, b => n3611, c => n4904, d => n386, outb
=> n4906);
U3383 : aoi22 port map( a => mult_125_G4_ab_4_15_port, b =>
mult_125_G4_ab_5_14_port, c => n4906, d => n4908,
outb => n4907);
U3384 : oai22 port map( a => n3612, b => n3613, c => n4907, d => n388, outb
=> n4909);
U3385 : aoi22 port map( a => mult_125_G4_ab_6_15_port, b =>
mult_125_G4_ab_7_14_port, c => n4909, d => n4911,
outb => n4910);
U3386 : oai22 port map( a => n3614, b => n3615, c => n4910, d => n390, outb
=> n4912);
U3387 : aoi22 port map( a => mult_125_G4_ab_8_15_port, b =>
mult_125_G4_ab_9_14_port, c => n4912, d => n4914,
outb => n4913);
U3388 : oai22 port map( a => n3616, b => n3617, c => n4913, d => n392, outb
=> n4915);
U3389 : aoi22 port map( a => mult_125_G4_ab_10_15_port, b =>
mult_125_G4_ab_11_14_port, c => n4915, d => n4917,
outb => n4916);
U3390 : oai22 port map( a => n3618, b => n3619, c => n4916, d => n394, outb
=> n4918);
U3391 : aoi22 port map( a => mult_125_G4_ab_12_15_port, b =>
mult_125_G4_ab_13_14_port, c => n4918, d => n4920,
outb => n4919);
U3392 : aoi22 port map( a => mult_125_G4_ab_13_15_port, b =>
mult_125_G4_ab_14_14_port, c => n4922, d => n4923,
outb => n4921);
U3393 : aoi22 port map( a => mult_125_G4_ab_14_15_port, b =>
mult_125_G4_ab_15_14_port, c => n4924, d => n4925,
outb => n241);
U3394 : inv port map( inb => n3637, outb => n427);
U3395 : aoi22 port map( a => n427, b => mult_125_G4_ab_15_13_port, c =>
n4926, d => n2280, outb => n243);
U3396 : aoi22 port map( a => n456, b => mult_125_G4_ab_15_12_port, c =>
n4927, d => n2276, outb => n245);
U3397 : oai22 port map( a => n487, b => n486, c => n4929, d => n2321, outb
=> n4928);
U3398 : inv port map( inb => n503, outb => n3687);
U3399 : aoi22 port map( a => n517, b => mult_125_G4_ab_15_10_port, c =>
n4930, d => n2317, outb => n249);
U3400 : oai22 port map( a => n547, b => n546, c => n4932, d => n2362, outb
=> n4931);
U3401 : inv port map( inb => n566, outb => n3731);
U3402 : aoi22 port map( a => n576, b => mult_125_G4_ab_15_8_port, c => n4933
, d => n2358, outb => n253);
U3403 : oai22 port map( a => n607, b => n606, c => n4935, d => n2403, outb
=> n4934);
U3404 : inv port map( inb => n632, outb => n3771);
U3405 : aoi22 port map( a => n638, b => mult_125_G4_ab_15_6_port, c => n4936
, d => n2399, outb => n257);
U3406 : oai22 port map( a => n670, b => n669, c => n4938, d => n2444, outb
=> n4937);
U3407 : aoi22 port map( a => n4939, b => mult_125_G4_ab_15_4_port, c => n701
, d => n2440, outb => n261);
U3408 : aoi22 port map( a => n733, b => mult_125_G4_ab_15_3_port, c => n4940
, d => n2485, outb => n263);
U3409 : oai22 port map( a => n3845, b => n4941, c => n762, d => n2481, outb
=> n266);
U3410 : aoi22 port map( a => n792, b => mult_125_G4_ab_15_1_port, c => n4942
, d => n2504, outb => n268);
U3411 : aoi22 port map( a => n820, b => mult_125_G4_ab_15_0_port, c => n4943
, d => n4944, outb => n270);
U3412 : xor2 port map( a => n4901, b => n4873, outb => n2248);
U3413 : xor2 port map( a => n4945, b => n4904, outb => n2251);
U3414 : xor2 port map( a => n4906, b => n4874, outb => n2254);
U3415 : xor2 port map( a => n4946, b => n4907, outb => n2257);
U3416 : xor2 port map( a => n4909, b => n4875, outb => n2260);
U3417 : xor2 port map( a => n4947, b => n4910, outb => n2263);
U3418 : xor2 port map( a => n4912, b => n4876, outb => n2266);
U3419 : xor2 port map( a => n4948, b => n4913, outb => n2269);
U3420 : xor2 port map( a => n4915, b => n4877, outb => n2272);
U3421 : xor2 port map( a => n4949, b => n4916, outb => n2275);
U3422 : xor2 port map( a => n4918, b => n4878, outb => n2278);
U3423 : xor2 port map( a => n4950, b => n4922, outb => n2280);
U3424 : xor2 port map( a => n4921, b => n4879, outb => n244);
U3425 : xor2 port map( a => n4951, b => n2241, outb => n2286);
U3426 : xor2 port map( a => n4952, b => n2244, outb => n2292);
U3427 : xor2 port map( a => n4953, b => n2246, outb => n2295);
U3428 : xor2 port map( a => n4954, b => n2249, outb => n2298);
U3429 : xor2 port map( a => n4955, b => n2252, outb => n2301);
U3430 : xor2 port map( a => n4956, b => n2255, outb => n2304);
U3431 : xor2 port map( a => n4957, b => n2258, outb => n2307);
U3432 : xor2 port map( a => n4958, b => n2261, outb => n2310);
U3433 : xor2 port map( a => n4959, b => n2264, outb => n2313);
U3434 : xor2 port map( a => n4960, b => n2267, outb => n2316);
U3435 : xor2 port map( a => n4961, b => n2270, outb => n2319);
U3436 : xor2 port map( a => n4962, b => n2273, outb => n2321);
U3437 : xor2 port map( a => n4963, b => n2276, outb => n248);
U3438 : xor2 port map( a => n4964, b => n2282, outb => n2327);
U3439 : xor2 port map( a => n4965, b => n2284, outb => n2330);
U3440 : xor2 port map( a => n4966, b => n2288, outb => n2336);
U3441 : xor2 port map( a => n4967, b => n2290, outb => n2339);
U3442 : xor2 port map( a => n4968, b => n2293, outb => n2342);
U3443 : xor2 port map( a => n4969, b => n2296, outb => n2345);
U3444 : xor2 port map( a => n4970, b => n2299, outb => n2348);
U3445 : xor2 port map( a => n4971, b => n2302, outb => n2351);
U3446 : xor2 port map( a => n4972, b => n2305, outb => n2354);
U3447 : xor2 port map( a => n4973, b => n2308, outb => n2357);
U3448 : xor2 port map( a => n4974, b => n2311, outb => n2360);
U3449 : xor2 port map( a => n4975, b => n2314, outb => n2362);
U3450 : xor2 port map( a => n4976, b => n2317, outb => n252);
U3451 : xor2 port map( a => n4977, b => n2323, outb => n2368);
U3452 : xor2 port map( a => n4978, b => n2325, outb => n2371);
U3453 : xor2 port map( a => n4979, b => n2328, outb => n2374);
U3454 : xor2 port map( a => n4980, b => n2332, outb => n2380);
U3455 : xor2 port map( a => n4981, b => n2334, outb => n2383);
U3456 : xor2 port map( a => n4982, b => n2337, outb => n2386);
U3457 : xor2 port map( a => n4983, b => n2340, outb => n2389);
U3458 : xor2 port map( a => n4984, b => n2343, outb => n2392);
U3459 : xor2 port map( a => n4985, b => n2346, outb => n2395);
U3460 : xor2 port map( a => n4986, b => n2349, outb => n2398);
U3461 : xor2 port map( a => n4987, b => n2352, outb => n2401);
U3462 : xor2 port map( a => n4988, b => n2355, outb => n2403);
U3463 : xor2 port map( a => n4989, b => n2358, outb => n256);
U3464 : xor2 port map( a => n4990, b => n2364, outb => n2409);
U3465 : xor2 port map( a => n4991, b => n2366, outb => n2412);
U3466 : xor2 port map( a => n4992, b => n2369, outb => n2415);
U3467 : xor2 port map( a => n4993, b => n2372, outb => n2418);
U3468 : xor2 port map( a => n4994, b => n2376, outb => n2424);
U3469 : xor2 port map( a => n4995, b => n2378, outb => n2427);
U3470 : xor2 port map( a => n4996, b => n2381, outb => n2430);
U3471 : xor2 port map( a => n4997, b => n2384, outb => n2433);
U3472 : xor2 port map( a => n4998, b => n2387, outb => n2436);
U3473 : xor2 port map( a => n4999, b => n2390, outb => n2439);
U3474 : xor2 port map( a => n5000, b => n2393, outb => n2442);
U3475 : xor2 port map( a => n5001, b => n2396, outb => n2444);
U3476 : xor2 port map( a => n5002, b => n2399, outb => n260);
U3477 : xor2 port map( a => n5003, b => n2405, outb => n2450);
U3478 : xor2 port map( a => n5004, b => n2407, outb => n2453);
U3479 : xor2 port map( a => n5005, b => n2410, outb => n2456);
U3480 : xor2 port map( a => n5006, b => n2413, outb => n2459);
U3481 : xor2 port map( a => n5007, b => n2416, outb => n2462);
U3482 : xor2 port map( a => n5008, b => n2420, outb => n2468);
U3483 : xor2 port map( a => n5009, b => n2422, outb => n2471);
U3484 : xor2 port map( a => n5010, b => n2425, outb => n2474);
U3485 : xor2 port map( a => n5011, b => n2428, outb => n2477);
U3486 : xor2 port map( a => n5012, b => n2431, outb => n2480);
U3487 : xor2 port map( a => n5013, b => n2434, outb => n2483);
U3488 : xor2 port map( a => n5014, b => n2437, outb => n2485);
U3489 : xor2 port map( a => n5015, b => n2440, outb => n264);
U3490 : xor2 port map( a => n5016, b => n2446, outb => n2491);
U3491 : xor2 port map( a => n5017, b => n2448, outb => n2494);
U3492 : xor2 port map( a => n5018, b => n2451, outb => n2497);
U3493 : xor2 port map( a => n5019, b => n2454, outb => n2500);
U3494 : xor2 port map( a => n5020, b => n2457, outb => n2503);
U3495 : xor2 port map( a => n5021, b => n2460, outb => n2506);
U3496 : xor2 port map( a => n5022, b => n2464, outb => n2512);
U3497 : xor2 port map( a => n5023, b => n2466, outb => n2515);
U3498 : xor2 port map( a => n5024, b => n2469, outb => n2518);
U3499 : xor2 port map( a => n5025, b => n2472, outb => n2521);
U3500 : xor2 port map( a => n5026, b => n2475, outb => n2524);
U3501 : xor2 port map( a => n5027, b => n2478, outb => n2527);
U3502 : xor2 port map( a => n5028, b => n2481, outb => n269);
U3503 : xor2 port map( a => n5029, b => n2487, outb => n3873);
U3504 : xor2 port map( a => n5030, b => n2489, outb => n3877);
U3505 : xor2 port map( a => n5031, b => n2492, outb => n3881);
U3506 : xor2 port map( a => n5032, b => n2495, outb => n3885);
U3507 : xor2 port map( a => n5033, b => n2498, outb => n3889);
U3508 : xor2 port map( a => n5034, b => n2501, outb => n3893);
U3509 : inv port map( inb => n2525, outb => n4944);
U3510 : xor2 port map( a => n5035, b => n2504, outb => n271);
U3511 : xor2 port map( a => n5036, b => n2525, outb => n275);
U3512 : xor2 port map( a => n3609, b => mult_125_G4_ab_2_14_port, outb =>
n2242);
U3513 : xor2 port map( a => n3610, b => n3611, outb => n4945);
U3514 : xor2 port map( a => n3612, b => n3613, outb => n4946);
U3515 : xor2 port map( a => n3614, b => n3615, outb => n4947);
U3516 : xor2 port map( a => n3616, b => n3617, outb => n4948);
U3517 : xor2 port map( a => n3618, b => n3619, outb => n4949);
U3518 : xor2 port map( a => mult_125_G4_ab_13_15_port, b =>
mult_125_G4_ab_14_14_port, outb => n4950);
U3519 : xor2 port map( a => n3620, b => n399, outb => n2245);
U3520 : xor2 port map( a => mult_125_G4_ab_3_13_port, b => n403, outb =>
n4951);
U3521 : xor2 port map( a => mult_125_G4_ab_4_13_port, b => n405, outb =>
n2247);
U3522 : xor2 port map( a => mult_125_G4_ab_5_13_port, b => n407, outb =>
n2250);
U3523 : xor2 port map( a => mult_125_G4_ab_6_13_port, b => n409, outb =>
n2253);
U3524 : xor2 port map( a => n3627, b => n3625, outb => n2256);
U3525 : xor2 port map( a => mult_125_G4_ab_8_13_port, b => n413, outb =>
n2259);
U3526 : xor2 port map( a => n3630, b => n3628, outb => n2262);
U3527 : xor2 port map( a => mult_125_G4_ab_10_13_port, b => n417, outb =>
n2265);
U3528 : xor2 port map( a => n3633, b => n3631, outb => n2268);
U3529 : xor2 port map( a => mult_125_G4_ab_12_13_port, b => n421, outb =>
n2271);
U3530 : xor2 port map( a => n3636, b => n3634, outb => n2274);
U3531 : xor2 port map( a => mult_125_G4_ab_14_13_port, b => n425, outb =>
n2277);
U3532 : xor2 port map( a => mult_125_G4_ab_15_13_port, b => n3637, outb =>
n2279);
U3533 : xor2 port map( a => n430, b => mult_125_G4_ab_2_12_port, outb =>
n2283);
U3534 : xor2 port map( a => n3641, b => n3639, outb => n4952);
U3535 : xor2 port map( a => mult_125_G4_ab_4_12_port, b => n434, outb =>
n2285);
U3536 : xor2 port map( a => mult_125_G4_ab_5_12_port, b => n3642, outb =>
n4953);
U3537 : xor2 port map( a => n3646, b => n3644, outb => n4954);
U3538 : xor2 port map( a => mult_125_G4_ab_7_12_port, b => n440, outb =>
n4955);
U3539 : xor2 port map( a => n3649, b => n3647, outb => n4956);
U3540 : xor2 port map( a => mult_125_G4_ab_9_12_port, b => n444, outb =>
n4957);
U3541 : xor2 port map( a => n3652, b => n3650, outb => n4958);
U3542 : xor2 port map( a => mult_125_G4_ab_11_12_port, b => n448, outb =>
n4959);
U3543 : xor2 port map( a => n3655, b => n3653, outb => n4960);
U3544 : xor2 port map( a => mult_125_G4_ab_13_12_port, b => n452, outb =>
n4961);
U3545 : xor2 port map( a => n3658, b => n3656, outb => n4962);
U3546 : xor2 port map( a => n5037, b => n456, outb => n4963);
U3547 : xor2 port map( a => n459, b => mult_125_G4_ab_2_11_port, outb =>
n2289);
U3548 : xor2 port map( a => mult_125_G4_ab_3_11_port, b => n462, outb =>
n4964);
U3549 : xor2 port map( a => n3662, b => n3661, outb => n2291);
U3550 : xor2 port map( a => mult_125_G4_ab_5_11_port, b => n466, outb =>
n4965);
U3551 : xor2 port map( a => mult_125_G4_ab_6_11_port, b => n468, outb =>
n2294);
U3552 : xor2 port map( a => n3667, b => n3666, outb => n2297);
U3553 : xor2 port map( a => mult_125_G4_ab_8_11_port, b => n472, outb =>
n2300);
U3554 : xor2 port map( a => n3670, b => n3668, outb => n2303);
U3555 : xor2 port map( a => mult_125_G4_ab_10_11_port, b => n476, outb =>
n2306);
U3556 : xor2 port map( a => n3673, b => n3671, outb => n2309);
U3557 : xor2 port map( a => mult_125_G4_ab_12_11_port, b => n480, outb =>
n2312);
U3558 : xor2 port map( a => n3676, b => n3674, outb => n2315);
U3559 : xor2 port map( a => mult_125_G4_ab_14_11_port, b => n484, outb =>
n2318);
U3560 : xor2 port map( a => n486, b => n487, outb => n2320);
U3561 : xor2 port map( a => n490, b => mult_125_G4_ab_2_10_port, outb =>
n2324);
U3562 : xor2 port map( a => n3680, b => n3678, outb => n4966);
U3563 : xor2 port map( a => mult_125_G4_ab_4_10_port, b => n494, outb =>
n2326);
U3564 : xor2 port map( a => n496, b => n497, outb => n4967);
U3565 : xor2 port map( a => mult_125_G4_ab_6_10_port, b => n499, outb =>
n2329);
U3566 : xor2 port map( a => mult_125_G4_ab_7_10_port, b => n501, outb =>
n4968);
U3567 : xor2 port map( a => n3686, b => n3687, outb => n4969);
U3568 : xor2 port map( a => mult_125_G4_ab_9_10_port, b => n505, outb =>
n4970);
U3569 : xor2 port map( a => n3690, b => n3688, outb => n4971);
U3570 : xor2 port map( a => mult_125_G4_ab_11_10_port, b => n509, outb =>
n4972);
U3571 : xor2 port map( a => n3693, b => n3691, outb => n4973);
U3572 : xor2 port map( a => mult_125_G4_ab_13_10_port, b => n513, outb =>
n4974);
U3573 : xor2 port map( a => n3696, b => n3694, outb => n4975);
U3574 : xor2 port map( a => n5038, b => n517, outb => n4976);
U3575 : xor2 port map( a => n520, b => mult_125_G4_ab_2_9_port, outb =>
n2333);
U3576 : xor2 port map( a => n3699, b => n3697, outb => n4977);
U3577 : xor2 port map( a => mult_125_G4_ab_4_9_port, b => n524, outb =>
n2335);
U3578 : xor2 port map( a => mult_125_G4_ab_5_9_port, b => n526, outb =>
n4978);
U3579 : xor2 port map( a => mult_125_G4_ab_6_9_port, b => n528, outb =>
n2338);
U3580 : xor2 port map( a => mult_125_G4_ab_7_9_port, b => n530, outb =>
n4979);
U3581 : xor2 port map( a => n3707, b => n3705, outb => n2341);
U3582 : xor2 port map( a => n3709, b => n3708, outb => n2344);
U3583 : xor2 port map( a => mult_125_G4_ab_10_9_port, b => n536, outb =>
n2347);
U3584 : xor2 port map( a => n3712, b => n3710, outb => n2350);
U3585 : xor2 port map( a => mult_125_G4_ab_12_9_port, b => n540, outb =>
n2353);
U3586 : xor2 port map( a => n3715, b => n3713, outb => n2356);
U3587 : xor2 port map( a => mult_125_G4_ab_14_9_port, b => n544, outb =>
n2359);
U3588 : xor2 port map( a => n546, b => n547, outb => n2361);
U3589 : xor2 port map( a => n550, b => mult_125_G4_ab_2_8_port, outb =>
n2365);
U3590 : xor2 port map( a => n3719, b => n3717, outb => n4980);
U3591 : xor2 port map( a => n3721, b => n554, outb => n2367);
U3592 : xor2 port map( a => n3723, b => n3722, outb => n4981);
U3593 : xor2 port map( a => mult_125_G4_ab_6_8_port, b => n558, outb =>
n2370);
U3594 : xor2 port map( a => n3726, b => n3724, outb => n4982);
U3595 : xor2 port map( a => mult_125_G4_ab_8_8_port, b => n562, outb =>
n2373);
U3596 : xor2 port map( a => mult_125_G4_ab_9_8_port, b => n564, outb =>
n4983);
U3597 : xor2 port map( a => n3730, b => n3731, outb => n4984);
U3598 : xor2 port map( a => mult_125_G4_ab_11_8_port, b => n568, outb =>
n4985);
U3599 : xor2 port map( a => n3734, b => n3732, outb => n4986);
U3600 : xor2 port map( a => mult_125_G4_ab_13_8_port, b => n572, outb =>
n4987);
U3601 : xor2 port map( a => n3737, b => n3735, outb => n4988);
U3602 : xor2 port map( a => n5039, b => n576, outb => n4989);
U3603 : xor2 port map( a => n579, b => mult_125_G4_ab_2_7_port, outb =>
n2377);
U3604 : xor2 port map( a => mult_125_G4_ab_3_7_port, b => n582, outb =>
n4990);
U3605 : xor2 port map( a => n3741, b => n3740, outb => n2379);
U3606 : xor2 port map( a => mult_125_G4_ab_5_7_port, b => n586, outb =>
n4991);
U3607 : xor2 port map( a => n3744, b => n3742, outb => n2382);
U3608 : xor2 port map( a => mult_125_G4_ab_7_7_port, b => n590, outb =>
n4992);
U3609 : xor2 port map( a => n3747, b => n3745, outb => n2385);
U3610 : xor2 port map( a => mult_125_G4_ab_9_7_port, b => n594, outb =>
n4993);
U3611 : xor2 port map( a => n3750, b => n3748, outb => n2388);
U3612 : xor2 port map( a => n3752, b => n3751, outb => n2391);
U3613 : xor2 port map( a => mult_125_G4_ab_12_7_port, b => n600, outb =>
n2394);
U3614 : xor2 port map( a => n3755, b => n3753, outb => n2397);
U3615 : xor2 port map( a => mult_125_G4_ab_14_7_port, b => n604, outb =>
n2400);
U3616 : xor2 port map( a => n606, b => n607, outb => n2402);
U3617 : xor2 port map( a => n610, b => mult_125_G4_ab_2_6_port, outb =>
n2406);
U3618 : xor2 port map( a => n3759, b => n3757, outb => n4994);
U3619 : xor2 port map( a => mult_125_G4_ab_4_6_port, b => n614, outb =>
n2408);
U3620 : xor2 port map( a => n616, b => n617, outb => n4995);
U3621 : xor2 port map( a => mult_125_G4_ab_6_6_port, b => n619, outb =>
n2411);
U3622 : xor2 port map( a => n3764, b => n3762, outb => n4996);
U3623 : xor2 port map( a => mult_125_G4_ab_8_6_port, b => n623, outb =>
n2414);
U3624 : xor2 port map( a => n625, b => n626, outb => n4997);
U3625 : xor2 port map( a => mult_125_G4_ab_10_6_port, b => n628, outb =>
n2417);
U3626 : xor2 port map( a => mult_125_G4_ab_11_6_port, b => n630, outb =>
n4998);
U3627 : xor2 port map( a => n3770, b => n3771, outb => n4999);
U3628 : xor2 port map( a => mult_125_G4_ab_13_6_port, b => n634, outb =>
n5000);
U3629 : xor2 port map( a => n3774, b => n3772, outb => n5001);
U3630 : xor2 port map( a => n5040, b => n638, outb => n5002);
U3631 : xor2 port map( a => n641, b => mult_125_G4_ab_2_5_port, outb =>
n2421);
U3632 : xor2 port map( a => mult_125_G4_ab_3_5_port, b => n644, outb =>
n5003);
U3633 : xor2 port map( a => mult_125_G4_ab_4_5_port, b => n646, outb =>
n2423);
U3634 : xor2 port map( a => mult_125_G4_ab_5_5_port, b => n648, outb =>
n5004);
U3635 : xor2 port map( a => n650, b => n651, outb => n2426);
U3636 : xor2 port map( a => mult_125_G4_ab_7_5_port, b => n653, outb =>
n5005);
U3637 : xor2 port map( a => mult_125_G4_ab_8_5_port, b => n655, outb =>
n2429);
U3638 : xor2 port map( a => mult_125_G4_ab_9_5_port, b => n657, outb =>
n5006);
U3639 : xor2 port map( a => n3786, b => n3784, outb => n2432);
U3640 : xor2 port map( a => mult_125_G4_ab_11_5_port, b => n661, outb =>
n5007);
U3641 : xor2 port map( a => n3789, b => n3787, outb => n2435);
U3642 : xor2 port map( a => n3791, b => n665, outb => n2438);
U3643 : xor2 port map( a => mult_125_G4_ab_14_5_port, b => n667, outb =>
n2441);
U3644 : xor2 port map( a => n669, b => n670, outb => n2443);
U3645 : xor2 port map( a => n673, b => mult_125_G4_ab_2_4_port, outb =>
n2447);
U3646 : xor2 port map( a => n3795, b => n3793, outb => n5008);
U3647 : xor2 port map( a => mult_125_G4_ab_4_4_port, b => n677, outb =>
n2449);
U3648 : xor2 port map( a => n679, b => n680, outb => n5009);
U3649 : xor2 port map( a => mult_125_G4_ab_6_4_port, b => n682, outb =>
n2452);
U3650 : xor2 port map( a => n684, b => n685, outb => n5010);
U3651 : xor2 port map( a => mult_125_G4_ab_8_4_port, b => n687, outb =>
n2455);
U3652 : xor2 port map( a => mult_125_G4_ab_9_4_port, b => n689, outb =>
n5011);
U3653 : xor2 port map( a => mult_125_G4_ab_10_4_port, b => n691, outb =>
n2458);
U3654 : xor2 port map( a => n693, b => n694, outb => n5012);
U3655 : xor2 port map( a => mult_125_G4_ab_12_4_port, b => n696, outb =>
n2461);
U3656 : xor2 port map( a => mult_125_G4_ab_13_4_port, b => n698, outb =>
n5013);
U3657 : xor2 port map( a => mult_125_G4_ab_14_4_port, b => n700, outb =>
n5014);
U3658 : xor2 port map( a => mult_125_G4_ab_15_4_port, b => n703, outb =>
n5015);
U3659 : xor2 port map( a => n706, b => mult_125_G4_ab_2_3_port, outb =>
n2465);
U3660 : xor2 port map( a => mult_125_G4_ab_3_3_port, b => n709, outb =>
n5016);
U3661 : xor2 port map( a => mult_125_G4_ab_4_3_port, b => n711, outb =>
n2467);
U3662 : xor2 port map( a => mult_125_G4_ab_5_3_port, b => n713, outb =>
n5017);
U3663 : xor2 port map( a => mult_125_G4_ab_6_3_port, b => n715, outb =>
n2470);
U3664 : xor2 port map( a => mult_125_G4_ab_7_3_port, b => n717, outb =>
n5018);
U3665 : xor2 port map( a => mult_125_G4_ab_8_3_port, b => n719, outb =>
n2473);
U3666 : xor2 port map( a => mult_125_G4_ab_9_3_port, b => n721, outb =>
n5019);
U3667 : xor2 port map( a => mult_125_G4_ab_10_3_port, b => n723, outb =>
n2476);
U3668 : xor2 port map( a => mult_125_G4_ab_11_3_port, b => n725, outb =>
n5020);
U3669 : xor2 port map( a => n3824, b => n3822, outb => n2479);
U3670 : xor2 port map( a => mult_125_G4_ab_13_3_port, b => n729, outb =>
n5021);
U3671 : xor2 port map( a => mult_125_G4_ab_14_3_port, b => n731, outb =>
n2482);
U3672 : xor2 port map( a => mult_125_G4_ab_15_3_port, b => n733, outb =>
n2484);
U3673 : xor2 port map( a => n736, b => mult_125_G4_ab_2_2_port, outb =>
n2488);
U3674 : xor2 port map( a => n3830, b => n3828, outb => n5022);
U3675 : xor2 port map( a => mult_125_G4_ab_4_2_port, b => n740, outb =>
n2490);
U3676 : xor2 port map( a => mult_125_G4_ab_5_2_port, b => n742, outb =>
n5023);
U3677 : xor2 port map( a => mult_125_G4_ab_6_2_port, b => n744, outb =>
n2493);
U3678 : xor2 port map( a => n746, b => n747, outb => n5024);
U3679 : xor2 port map( a => mult_125_G4_ab_8_2_port, b => n749, outb =>
n2496);
U3680 : xor2 port map( a => mult_125_G4_ab_9_2_port, b => n751, outb =>
n5025);
U3681 : xor2 port map( a => mult_125_G4_ab_10_2_port, b => n753, outb =>
n2499);
U3682 : xor2 port map( a => mult_125_G4_ab_11_2_port, b => n755, outb =>
n5026);
U3683 : xor2 port map( a => mult_125_G4_ab_12_2_port, b => n757, outb =>
n2502);
U3684 : xor2 port map( a => mult_125_G4_ab_13_2_port, b => n759, outb =>
n5027);
U3685 : xor2 port map( a => mult_125_G4_ab_14_2_port, b => n761, outb =>
n2505);
U3686 : xor2 port map( a => n4941, b => n3845, outb => n5028);
U3687 : xor2 port map( a => n3848, b => mult_125_G4_ab_2_1_port, outb =>
n2509);
U3688 : xor2 port map( a => n3849, b => n3847, outb => n5029);
U3689 : xor2 port map( a => mult_125_G4_ab_4_1_port, b => n3851, outb =>
n2511);
U3690 : xor2 port map( a => mult_125_G4_ab_5_1_port, b => n772, outb =>
n5041);
U3691 : xor2 port map( a => n3854, b => n774, outb => n2514);
U3692 : xor2 port map( a => n5042, b => n776, outb => n5031);
U3693 : xor2 port map( a => mult_125_G4_ab_8_1_port, b => n3855, outb =>
n2517);
U3694 : xor2 port map( a => n5043, b => n780, outb => n5032);
U3695 : xor2 port map( a => n3860, b => n782, outb => n2520);
U3696 : xor2 port map( a => n5044, b => n784, outb => n5033);
U3697 : xor2 port map( a => n3863, b => n786, outb => n2523);
U3698 : xor2 port map( a => n5045, b => n788, outb => n5034);
U3699 : xor2 port map( a => n3866, b => n3864, outb => n2526);
U3700 : xor2 port map( a => n5046, b => n792, outb => n5035);
U3701 : xor2 port map( a => mult_125_G4_ab_15_0_port, b => n820, outb =>
n5036);
U3702 : xor2 port map( a => mult_125_G4_ab_11_0_port, b => n812, outb =>
n2528);
U3703 : xor2 port map( a => mult_125_G4_ab_9_0_port, b => n808, outb =>
n2529);
U3704 : xor2 port map( a => mult_125_G4_ab_7_0_port, b => n804, outb =>
n2530);
U3705 : xor2 port map( a => mult_125_G4_ab_5_0_port, b => n800, outb =>
n2531);
U3706 : xor2 port map( a => mult_125_G4_ab_3_0_port, b => n796, outb =>
n2532);
U3707 : xor2 port map( a => n272, b => mult_125_G4_ZA, outb => n2533);
U3708 : xor2 port map( a => mult_125_G4_ab_13_0_port, b => n816, outb =>
n2534);
U3709 : oai22 port map( a => n5048, b => n5049, c => n822, d => n3894, outb
=> n5047);
U3710 : aoi22 port map( a => mult_125_G3_ab_2_15_port, b =>
mult_125_G3_ab_3_14_port, c => n5047, d => n5051,
outb => n5050);
U3711 : oai22 port map( a => n3895, b => n3896, c => n5050, d => n824, outb
=> n5052);
U3712 : aoi22 port map( a => mult_125_G3_ab_4_15_port, b =>
mult_125_G3_ab_5_14_port, c => n5052, d => n5054,
outb => n5053);
U3713 : oai22 port map( a => n3897, b => n3898, c => n5053, d => n826, outb
=> n5055);
U3714 : aoi22 port map( a => mult_125_G3_ab_6_15_port, b =>
mult_125_G3_ab_7_14_port, c => n5055, d => n5057,
outb => n5056);
U3715 : oai22 port map( a => n3899, b => n3900, c => n5056, d => n828, outb
=> n5058);
U3716 : aoi22 port map( a => mult_125_G3_ab_8_15_port, b =>
mult_125_G3_ab_9_14_port, c => n5058, d => n5060,
outb => n5059);
U3717 : oai22 port map( a => n3901, b => n3902, c => n5059, d => n830, outb
=> n5061);
U3718 : aoi22 port map( a => mult_125_G3_ab_10_15_port, b =>
mult_125_G3_ab_11_14_port, c => n5061, d => n5063,
outb => n5062);
U3719 : oai22 port map( a => n3903, b => n3904, c => n5062, d => n832, outb
=> n5064);
U3720 : aoi22 port map( a => mult_125_G3_ab_12_15_port, b =>
mult_125_G3_ab_13_14_port, c => n5064, d => n5066,
outb => n5065);
U3721 : aoi22 port map( a => mult_125_G3_ab_13_15_port, b =>
mult_125_G3_ab_14_14_port, c => n5068, d => n5069,
outb => n5067);
U3722 : aoi22 port map( a => mult_125_G3_ab_14_15_port, b =>
mult_125_G3_ab_15_14_port, c => n5070, d => n5071,
outb => n349);
U3723 : inv port map( inb => n3922, outb => n865);
U3724 : aoi22 port map( a => n865, b => mult_125_G3_ab_15_13_port, c =>
n5072, d => n2577, outb => n351);
U3725 : aoi22 port map( a => n894, b => mult_125_G3_ab_15_12_port, c =>
n5073, d => n2573, outb => n353);
U3726 : oai22 port map( a => n925, b => n924, c => n5075, d => n2618, outb
=> n5074);
U3727 : inv port map( inb => n941, outb => n3972);
U3728 : aoi22 port map( a => n955, b => mult_125_G3_ab_15_10_port, c =>
n5076, d => n2614, outb => n357);
U3729 : oai22 port map( a => n985, b => n984, c => n5078, d => n2659, outb
=> n5077);
U3730 : inv port map( inb => n1004, outb => n4016);
U3731 : aoi22 port map( a => n1014, b => mult_125_G3_ab_15_8_port, c =>
n5079, d => n2655, outb => n361);
U3732 : oai22 port map( a => n1045, b => n1044, c => n5081, d => n2700, outb
=> n5080);
U3733 : inv port map( inb => n1070, outb => n4056);
U3734 : aoi22 port map( a => n1076, b => mult_125_G3_ab_15_6_port, c =>
n5082, d => n2696, outb => n365);
U3735 : oai22 port map( a => n1108, b => n1107, c => n5084, d => n2741, outb
=> n5083);
U3736 : aoi22 port map( a => n5085, b => mult_125_G3_ab_15_4_port, c =>
n1139, d => n2737, outb => n369);
U3737 : aoi22 port map( a => n1171, b => mult_125_G3_ab_15_3_port, c =>
n5086, d => n2782, outb => n371);
U3738 : oai22 port map( a => n4130, b => n5087, c => n1200, d => n2778, outb
=> n374);
U3739 : aoi22 port map( a => n1230, b => mult_125_G3_ab_15_1_port, c =>
n5088, d => n2801, outb => n376);
U3740 : aoi22 port map( a => n1258, b => mult_125_G3_ab_15_0_port, c =>
n5089, d => n5090, outb => n378);
U3741 : aoi22 port map( a => adder_mem_array_3_1_port, b => n2137, c =>
n5091, d => n3426, outb => n3483);
U3742 : oai22 port map( a => n4750, b => n4751, c => n3483, d => n2138, outb
=> n3480);
U3743 : aoi22 port map( a => multiplier_sigs_2_3_port, b =>
adder_mem_array_3_3_port, c => n3480, d => n5092,
outb => n3479);
U3744 : oai22 port map( a => n4752, b => n4753, c => n3479, d => n2140, outb
=> n3476);
U3745 : aoi22 port map( a => multiplier_sigs_2_5_port, b =>
adder_mem_array_3_5_port, c => n3476, d => n5093,
outb => n3475);
U3746 : oai22 port map( a => n4754, b => n4755, c => n3475, d => n2142, outb
=> n3472);
U3747 : aoi22 port map( a => multiplier_sigs_2_7_port, b =>
adder_mem_array_3_7_port, c => n3472, d => n5094,
outb => n3469);
U3748 : oai22 port map( a => n4756, b => n4757, c => n3469, d => n2144, outb
=> n3466);
U3749 : aoi22 port map( a => multiplier_sigs_2_9_port, b =>
adder_mem_array_3_9_port, c => n3466, d => n5095,
outb => n3465);
U3750 : oai22 port map( a => n4758, b => n4759, c => n3465, d => n2146, outb
=> n3462);
U3751 : aoi22 port map( a => multiplier_sigs_2_11_port, b =>
adder_mem_array_3_11_port, c => n3462, d => n5096,
outb => n3461);
U3752 : oai22 port map( a => n4760, b => n4761, c => n3461, d => n2148, outb
=> n3458);
U3753 : aoi22 port map( a => multiplier_sigs_2_13_port, b =>
adder_mem_array_3_13_port, c => n3458, d => n5097,
outb => n3457);
U3754 : oai22 port map( a => n4762, b => n4763, c => n3457, d => n2150, outb
=> n3454);
U3755 : aoi22 port map( a => multiplier_sigs_2_15_port, b =>
adder_mem_array_3_15_port, c => n3454, d => n5098,
outb => n3453);
U3756 : oai22 port map( a => n4764, b => n4765, c => n3453, d => n2152, outb
=> n3450);
U3757 : aoi22 port map( a => multiplier_sigs_2_17_port, b =>
adder_mem_array_3_17_port, c => n3450, d => n5099,
outb => n3446);
U3758 : oai22 port map( a => n4766, b => n4767, c => n3446, d => n2154, outb
=> n3443);
U3759 : aoi22 port map( a => multiplier_sigs_2_19_port, b =>
adder_mem_array_3_19_port, c => n3443, d => n5100,
outb => n3442);
U3760 : oai22 port map( a => n4768, b => n4769, c => n3442, d => n2156, outb
=> n3439);
U3761 : aoi22 port map( a => multiplier_sigs_2_21_port, b =>
adder_mem_array_3_21_port, c => n3439, d => n5101,
outb => n3438);
U3762 : oai22 port map( a => n4770, b => n4771, c => n3438, d => n2158, outb
=> n3435);
U3763 : aoi22 port map( a => multiplier_sigs_2_23_port, b =>
adder_mem_array_3_23_port, c => n3435, d => n5102,
outb => n3434);
U3764 : oai22 port map( a => n4772, b => n4773, c => n3434, d => n2160, outb
=> n3431);
U3765 : aoi22 port map( a => multiplier_sigs_2_25_port, b =>
adder_mem_array_3_25_port, c => n3431, d => n5103,
outb => n3430);
U3766 : oai22 port map( a => n4774, b => n4775, c => n3430, d => n2162, outb
=> n3427);
U3767 : aoi22 port map( a => adder_mem_array_3_27_port, b =>
multiplier_sigs_2_27_port, c => n3427, d => n5104,
outb => n3606);
U3768 : oai22 port map( a => n4838, b => n4839, c => n3606, d => n2232, outb
=> n3603);
U3769 : aoi22 port map( a => multiplier_sigs_2_29_port, b =>
adder_mem_array_3_29_port, c => n3603, d => n5105,
outb => n3602);
U3770 : oai22 port map( a => n4840, b => n4841, c => n3602, d => n2234, outb
=> n2237);
U3771 : nand2 port map( a => n5106, b => n5107, outb => n2236);
U3772 : xor2 port map( a => n5047, b => n4880, outb => n2545);
U3773 : xor2 port map( a => n5108, b => n5050, outb => n2548);
U3774 : xor2 port map( a => n5052, b => n4881, outb => n2551);
U3775 : xor2 port map( a => n5109, b => n5053, outb => n2554);
U3776 : xor2 port map( a => n5055, b => n4882, outb => n2557);
U3777 : xor2 port map( a => n5110, b => n5056, outb => n2560);
U3778 : xor2 port map( a => n5058, b => n4883, outb => n2563);
U3779 : xor2 port map( a => n5111, b => n5059, outb => n2566);
U3780 : xor2 port map( a => n5061, b => n4884, outb => n2569);
U3781 : xor2 port map( a => n5112, b => n5062, outb => n2572);
U3782 : xor2 port map( a => n5064, b => n4885, outb => n2575);
U3783 : xor2 port map( a => n5113, b => n5068, outb => n2577);
U3784 : xor2 port map( a => n5067, b => n4886, outb => n352);
U3785 : xor2 port map( a => n5114, b => n2538, outb => n2583);
U3786 : xor2 port map( a => n5115, b => n2541, outb => n2589);
U3787 : xor2 port map( a => n5116, b => n2543, outb => n2592);
U3788 : xor2 port map( a => n5117, b => n2546, outb => n2595);
U3789 : xor2 port map( a => n5118, b => n2549, outb => n2598);
U3790 : xor2 port map( a => n5119, b => n2552, outb => n2601);
U3791 : xor2 port map( a => n5120, b => n2555, outb => n2604);
U3792 : xor2 port map( a => n5121, b => n2558, outb => n2607);
U3793 : xor2 port map( a => n5122, b => n2561, outb => n2610);
U3794 : xor2 port map( a => n5123, b => n2564, outb => n2613);
U3795 : xor2 port map( a => n5124, b => n2567, outb => n2616);
U3796 : xor2 port map( a => n5125, b => n2570, outb => n2618);
U3797 : xor2 port map( a => n5126, b => n2573, outb => n356);
U3798 : xor2 port map( a => n5127, b => n2579, outb => n2624);
U3799 : xor2 port map( a => n5128, b => n2581, outb => n2627);
U3800 : xor2 port map( a => n5129, b => n2585, outb => n2633);
U3801 : xor2 port map( a => n5130, b => n2587, outb => n2636);
U3802 : xor2 port map( a => n5131, b => n2590, outb => n2639);
U3803 : xor2 port map( a => n5132, b => n2593, outb => n2642);
U3804 : xor2 port map( a => n5133, b => n2596, outb => n2645);
U3805 : xor2 port map( a => n5134, b => n2599, outb => n2648);
U3806 : xor2 port map( a => n5135, b => n2602, outb => n2651);
U3807 : xor2 port map( a => n5136, b => n2605, outb => n2654);
U3808 : xor2 port map( a => n5137, b => n2608, outb => n2657);
U3809 : xor2 port map( a => n5138, b => n2611, outb => n2659);
U3810 : xor2 port map( a => n5139, b => n2614, outb => n360);
U3811 : xor2 port map( a => n5140, b => n2620, outb => n2665);
U3812 : xor2 port map( a => n5141, b => n2622, outb => n2668);
U3813 : xor2 port map( a => n5142, b => n2625, outb => n2671);
U3814 : xor2 port map( a => n5143, b => n2629, outb => n2677);
U3815 : xor2 port map( a => n5144, b => n2631, outb => n2680);
U3816 : xor2 port map( a => n5145, b => n2634, outb => n2683);
U3817 : xor2 port map( a => n5146, b => n2637, outb => n2686);
U3818 : xor2 port map( a => n5147, b => n2640, outb => n2689);
U3819 : xor2 port map( a => n5148, b => n2643, outb => n2692);
U3820 : xor2 port map( a => n5149, b => n2646, outb => n2695);
U3821 : xor2 port map( a => n5150, b => n2649, outb => n2698);
U3822 : xor2 port map( a => n5151, b => n2652, outb => n2700);
U3823 : xor2 port map( a => n5152, b => n2655, outb => n364);
U3824 : xor2 port map( a => n5153, b => n2661, outb => n2706);
U3825 : xor2 port map( a => n5154, b => n2663, outb => n2709);
U3826 : xor2 port map( a => n5155, b => n2666, outb => n2712);
U3827 : xor2 port map( a => n5156, b => n2669, outb => n2715);
U3828 : xor2 port map( a => n5157, b => n2673, outb => n2721);
U3829 : xor2 port map( a => n5158, b => n2675, outb => n2724);
U3830 : xor2 port map( a => n5159, b => n2678, outb => n2727);
U3831 : xor2 port map( a => n5160, b => n2681, outb => n2730);
U3832 : xor2 port map( a => n5161, b => n2684, outb => n2733);
U3833 : xor2 port map( a => n5162, b => n2687, outb => n2736);
U3834 : xor2 port map( a => n5163, b => n2690, outb => n2739);
U3835 : xor2 port map( a => n5164, b => n2693, outb => n2741);
U3836 : xor2 port map( a => n5165, b => n2696, outb => n368);
U3837 : xor2 port map( a => n5166, b => n2702, outb => n2747);
U3838 : xor2 port map( a => n5167, b => n2704, outb => n2750);
U3839 : xor2 port map( a => n5168, b => n2707, outb => n2753);
U3840 : xor2 port map( a => n5169, b => n2710, outb => n2756);
U3841 : xor2 port map( a => n5170, b => n2713, outb => n2759);
U3842 : xor2 port map( a => n5171, b => n2717, outb => n2765);
U3843 : xor2 port map( a => n5172, b => n2719, outb => n2768);
U3844 : xor2 port map( a => n5173, b => n2722, outb => n2771);
U3845 : xor2 port map( a => n5174, b => n2725, outb => n2774);
U3846 : xor2 port map( a => n5175, b => n2728, outb => n2777);
U3847 : xor2 port map( a => n5176, b => n2731, outb => n2780);
U3848 : xor2 port map( a => n5177, b => n2734, outb => n2782);
U3849 : xor2 port map( a => n5178, b => n2737, outb => n372);
U3850 : xor2 port map( a => n5179, b => n2743, outb => n2788);
U3851 : xor2 port map( a => n5180, b => n2745, outb => n2791);
U3852 : xor2 port map( a => n5181, b => n2748, outb => n2794);
U3853 : xor2 port map( a => n5182, b => n2751, outb => n2797);
U3854 : xor2 port map( a => n5183, b => n2754, outb => n2800);
U3855 : xor2 port map( a => n5184, b => n2757, outb => n2803);
U3856 : xor2 port map( a => n5185, b => n2761, outb => n2809);
U3857 : xor2 port map( a => n5186, b => n2763, outb => n2812);
U3858 : xor2 port map( a => n5187, b => n2766, outb => n2815);
U3859 : xor2 port map( a => n5188, b => n2769, outb => n2818);
U3860 : xor2 port map( a => n5189, b => n2772, outb => n2821);
U3861 : xor2 port map( a => n5190, b => n2775, outb => n2824);
U3862 : xor2 port map( a => n5191, b => n2778, outb => n377);
U3863 : xor2 port map( a => n5192, b => n2784, outb => n4158);
U3864 : xor2 port map( a => n5193, b => n2786, outb => n4162);
U3865 : xor2 port map( a => n5194, b => n2789, outb => n4166);
U3866 : xor2 port map( a => n5195, b => n2792, outb => n4170);
U3867 : xor2 port map( a => n5196, b => n2795, outb => n4174);
U3868 : xor2 port map( a => n5197, b => n2798, outb => n4178);
U3869 : inv port map( inb => n2822, outb => n5090);
U3870 : xor2 port map( a => n5198, b => n2801, outb => n379);
U3871 : xor2 port map( a => n5199, b => n2822, outb => n383);
U3872 : xor2 port map( a => n3894, b => mult_125_G3_ab_2_14_port, outb =>
n2539);
U3873 : xor2 port map( a => n3895, b => n3896, outb => n5108);
U3874 : xor2 port map( a => n3897, b => n3898, outb => n5109);
U3875 : xor2 port map( a => n3899, b => n3900, outb => n5110);
U3876 : xor2 port map( a => n3901, b => n3902, outb => n5111);
U3877 : xor2 port map( a => n3903, b => n3904, outb => n5112);
U3878 : xor2 port map( a => mult_125_G3_ab_13_15_port, b =>
mult_125_G3_ab_14_14_port, outb => n5113);
U3879 : xor2 port map( a => n3905, b => n837, outb => n2542);
U3880 : xor2 port map( a => mult_125_G3_ab_3_13_port, b => n841, outb =>
n5114);
U3881 : xor2 port map( a => mult_125_G3_ab_4_13_port, b => n843, outb =>
n2544);
U3882 : xor2 port map( a => mult_125_G3_ab_5_13_port, b => n845, outb =>
n2547);
U3883 : xor2 port map( a => mult_125_G3_ab_6_13_port, b => n847, outb =>
n2550);
U3884 : xor2 port map( a => n3912, b => n3910, outb => n2553);
U3885 : xor2 port map( a => mult_125_G3_ab_8_13_port, b => n851, outb =>
n2556);
U3886 : xor2 port map( a => n3915, b => n3913, outb => n2559);
U3887 : xor2 port map( a => mult_125_G3_ab_10_13_port, b => n855, outb =>
n2562);
U3888 : xor2 port map( a => n3918, b => n3916, outb => n2565);
U3889 : xor2 port map( a => mult_125_G3_ab_12_13_port, b => n859, outb =>
n2568);
U3890 : xor2 port map( a => n3921, b => n3919, outb => n2571);
U3891 : xor2 port map( a => mult_125_G3_ab_14_13_port, b => n863, outb =>
n2574);
U3892 : xor2 port map( a => mult_125_G3_ab_15_13_port, b => n3922, outb =>
n2576);
U3893 : xor2 port map( a => n868, b => mult_125_G3_ab_2_12_port, outb =>
n2580);
U3894 : xor2 port map( a => n3926, b => n3924, outb => n5115);
U3895 : xor2 port map( a => mult_125_G3_ab_4_12_port, b => n872, outb =>
n2582);
U3896 : xor2 port map( a => mult_125_G3_ab_5_12_port, b => n3927, outb =>
n5116);
U3897 : xor2 port map( a => n3931, b => n3929, outb => n5117);
U3898 : xor2 port map( a => mult_125_G3_ab_7_12_port, b => n878, outb =>
n5118);
U3899 : xor2 port map( a => n3934, b => n3932, outb => n5119);
U3900 : xor2 port map( a => mult_125_G3_ab_9_12_port, b => n882, outb =>
n5120);
U3901 : xor2 port map( a => n3937, b => n3935, outb => n5121);
U3902 : xor2 port map( a => mult_125_G3_ab_11_12_port, b => n886, outb =>
n5122);
U3903 : xor2 port map( a => n3940, b => n3938, outb => n5123);
U3904 : xor2 port map( a => mult_125_G3_ab_13_12_port, b => n890, outb =>
n5124);
U3905 : xor2 port map( a => n3943, b => n3941, outb => n5125);
U3906 : xor2 port map( a => n5200, b => n894, outb => n5126);
U3907 : xor2 port map( a => n897, b => mult_125_G3_ab_2_11_port, outb =>
n2586);
U3908 : xor2 port map( a => mult_125_G3_ab_3_11_port, b => n900, outb =>
n5127);
U3909 : xor2 port map( a => n3947, b => n3946, outb => n2588);
U3910 : xor2 port map( a => mult_125_G3_ab_5_11_port, b => n904, outb =>
n5128);
U3911 : xor2 port map( a => mult_125_G3_ab_6_11_port, b => n906, outb =>
n2591);
U3912 : xor2 port map( a => n3952, b => n3951, outb => n2594);
U3913 : xor2 port map( a => mult_125_G3_ab_8_11_port, b => n910, outb =>
n2597);
U3914 : xor2 port map( a => n3955, b => n3953, outb => n2600);
U3915 : xor2 port map( a => mult_125_G3_ab_10_11_port, b => n914, outb =>
n2603);
U3916 : xor2 port map( a => n3958, b => n3956, outb => n2606);
U3917 : xor2 port map( a => mult_125_G3_ab_12_11_port, b => n918, outb =>
n2609);
U3918 : xor2 port map( a => n3961, b => n3959, outb => n2612);
U3919 : xor2 port map( a => mult_125_G3_ab_14_11_port, b => n922, outb =>
n2615);
U3920 : xor2 port map( a => n924, b => n925, outb => n2617);
U3921 : xor2 port map( a => n928, b => mult_125_G3_ab_2_10_port, outb =>
n2621);
U3922 : xor2 port map( a => n3965, b => n3963, outb => n5129);
U3923 : xor2 port map( a => mult_125_G3_ab_4_10_port, b => n932, outb =>
n2623);
U3924 : xor2 port map( a => n934, b => n935, outb => n5130);
U3925 : xor2 port map( a => mult_125_G3_ab_6_10_port, b => n937, outb =>
n2626);
U3926 : xor2 port map( a => mult_125_G3_ab_7_10_port, b => n939, outb =>
n5131);
U3927 : xor2 port map( a => n3971, b => n3972, outb => n5132);
U3928 : xor2 port map( a => mult_125_G3_ab_9_10_port, b => n943, outb =>
n5133);
U3929 : xor2 port map( a => n3975, b => n3973, outb => n5134);
U3930 : xor2 port map( a => mult_125_G3_ab_11_10_port, b => n947, outb =>
n5135);
U3931 : xor2 port map( a => n3978, b => n3976, outb => n5136);
U3932 : xor2 port map( a => mult_125_G3_ab_13_10_port, b => n951, outb =>
n5137);
U3933 : xor2 port map( a => n3981, b => n3979, outb => n5138);
U3934 : xor2 port map( a => n5201, b => n955, outb => n5139);
U3935 : xor2 port map( a => n958, b => mult_125_G3_ab_2_9_port, outb =>
n2630);
U3936 : xor2 port map( a => n3984, b => n3982, outb => n5140);
U3937 : xor2 port map( a => mult_125_G3_ab_4_9_port, b => n962, outb =>
n2632);
U3938 : xor2 port map( a => mult_125_G3_ab_5_9_port, b => n964, outb =>
n5141);
U3939 : xor2 port map( a => mult_125_G3_ab_6_9_port, b => n966, outb =>
n2635);
U3940 : xor2 port map( a => mult_125_G3_ab_7_9_port, b => n968, outb =>
n5142);
U3941 : xor2 port map( a => n3992, b => n3990, outb => n2638);
U3942 : xor2 port map( a => n3994, b => n3993, outb => n2641);
U3943 : xor2 port map( a => mult_125_G3_ab_10_9_port, b => n974, outb =>
n2644);
U3944 : xor2 port map( a => n3997, b => n3995, outb => n2647);
U3945 : xor2 port map( a => mult_125_G3_ab_12_9_port, b => n978, outb =>
n2650);
U3946 : xor2 port map( a => n4000, b => n3998, outb => n2653);
U3947 : xor2 port map( a => mult_125_G3_ab_14_9_port, b => n982, outb =>
n2656);
U3948 : xor2 port map( a => n984, b => n985, outb => n2658);
U3949 : xor2 port map( a => n988, b => mult_125_G3_ab_2_8_port, outb =>
n2662);
U3950 : xor2 port map( a => n4004, b => n4002, outb => n5143);
U3951 : xor2 port map( a => n4006, b => n992, outb => n2664);
U3952 : xor2 port map( a => n4008, b => n4007, outb => n5144);
U3953 : xor2 port map( a => mult_125_G3_ab_6_8_port, b => n996, outb =>
n2667);
U3954 : xor2 port map( a => n4011, b => n4009, outb => n5145);
U3955 : xor2 port map( a => mult_125_G3_ab_8_8_port, b => n1000, outb =>
n2670);
U3956 : xor2 port map( a => mult_125_G3_ab_9_8_port, b => n1002, outb =>
n5146);
U3957 : xor2 port map( a => n4015, b => n4016, outb => n5147);
U3958 : xor2 port map( a => mult_125_G3_ab_11_8_port, b => n1006, outb =>
n5148);
U3959 : xor2 port map( a => n4019, b => n4017, outb => n5149);
U3960 : xor2 port map( a => mult_125_G3_ab_13_8_port, b => n1010, outb =>
n5150);
U3961 : xor2 port map( a => n4022, b => n4020, outb => n5151);
U3962 : xor2 port map( a => n5202, b => n1014, outb => n5152);
U3963 : xor2 port map( a => n1017, b => mult_125_G3_ab_2_7_port, outb =>
n2674);
U3964 : xor2 port map( a => mult_125_G3_ab_3_7_port, b => n1020, outb =>
n5153);
U3965 : xor2 port map( a => n4026, b => n4025, outb => n2676);
U3966 : xor2 port map( a => mult_125_G3_ab_5_7_port, b => n1024, outb =>
n5154);
U3967 : xor2 port map( a => n4029, b => n4027, outb => n2679);
U3968 : xor2 port map( a => mult_125_G3_ab_7_7_port, b => n1028, outb =>
n5155);
U3969 : xor2 port map( a => n4032, b => n4030, outb => n2682);
U3970 : xor2 port map( a => mult_125_G3_ab_9_7_port, b => n1032, outb =>
n5156);
U3971 : xor2 port map( a => n4035, b => n4033, outb => n2685);
U3972 : xor2 port map( a => n4037, b => n4036, outb => n2688);
U3973 : xor2 port map( a => mult_125_G3_ab_12_7_port, b => n1038, outb =>
n2691);
U3974 : xor2 port map( a => n4040, b => n4038, outb => n2694);
U3975 : xor2 port map( a => mult_125_G3_ab_14_7_port, b => n1042, outb =>
n2697);
U3976 : xor2 port map( a => n1044, b => n1045, outb => n2699);
U3977 : xor2 port map( a => n1048, b => mult_125_G3_ab_2_6_port, outb =>
n2703);
U3978 : xor2 port map( a => n4044, b => n4042, outb => n5157);
U3979 : xor2 port map( a => mult_125_G3_ab_4_6_port, b => n1052, outb =>
n2705);
U3980 : xor2 port map( a => n1054, b => n1055, outb => n5158);
U3981 : xor2 port map( a => mult_125_G3_ab_6_6_port, b => n1057, outb =>
n2708);
U3982 : xor2 port map( a => n4049, b => n4047, outb => n5159);
U3983 : xor2 port map( a => mult_125_G3_ab_8_6_port, b => n1061, outb =>
n2711);
U3984 : xor2 port map( a => n1063, b => n1064, outb => n5160);
U3985 : xor2 port map( a => mult_125_G3_ab_10_6_port, b => n1066, outb =>
n2714);
U3986 : xor2 port map( a => mult_125_G3_ab_11_6_port, b => n1068, outb =>
n5161);
U3987 : xor2 port map( a => n4055, b => n4056, outb => n5162);
U3988 : xor2 port map( a => mult_125_G3_ab_13_6_port, b => n1072, outb =>
n5163);
U3989 : xor2 port map( a => n4059, b => n4057, outb => n5164);
U3990 : xor2 port map( a => n5203, b => n1076, outb => n5165);
U3991 : xor2 port map( a => n1079, b => mult_125_G3_ab_2_5_port, outb =>
n2718);
U3992 : xor2 port map( a => mult_125_G3_ab_3_5_port, b => n1082, outb =>
n5166);
U3993 : xor2 port map( a => mult_125_G3_ab_4_5_port, b => n1084, outb =>
n2720);
U3994 : xor2 port map( a => mult_125_G3_ab_5_5_port, b => n1086, outb =>
n5167);
U3995 : xor2 port map( a => n1088, b => n1089, outb => n2723);
U3996 : xor2 port map( a => mult_125_G3_ab_7_5_port, b => n1091, outb =>
n5168);
U3997 : xor2 port map( a => mult_125_G3_ab_8_5_port, b => n1093, outb =>
n2726);
U3998 : xor2 port map( a => mult_125_G3_ab_9_5_port, b => n1095, outb =>
n5169);
U3999 : xor2 port map( a => n4071, b => n4069, outb => n2729);
U4000 : xor2 port map( a => mult_125_G3_ab_11_5_port, b => n1099, outb =>
n5170);
U4001 : xor2 port map( a => n4074, b => n4072, outb => n2732);
U4002 : xor2 port map( a => n4076, b => n1103, outb => n2735);
U4003 : xor2 port map( a => mult_125_G3_ab_14_5_port, b => n1105, outb =>
n2738);
U4004 : xor2 port map( a => n1107, b => n1108, outb => n2740);
U4005 : xor2 port map( a => n1111, b => mult_125_G3_ab_2_4_port, outb =>
n2744);
U4006 : xor2 port map( a => n4080, b => n4078, outb => n5171);
U4007 : xor2 port map( a => mult_125_G3_ab_4_4_port, b => n1115, outb =>
n2746);
U4008 : xor2 port map( a => n1117, b => n1118, outb => n5172);
U4009 : xor2 port map( a => mult_125_G3_ab_6_4_port, b => n1120, outb =>
n2749);
U4010 : xor2 port map( a => n1122, b => n1123, outb => n5173);
U4011 : xor2 port map( a => mult_125_G3_ab_8_4_port, b => n1125, outb =>
n2752);
U4012 : xor2 port map( a => mult_125_G3_ab_9_4_port, b => n1127, outb =>
n5174);
U4013 : xor2 port map( a => mult_125_G3_ab_10_4_port, b => n1129, outb =>
n2755);
U4014 : xor2 port map( a => n1131, b => n1132, outb => n5175);
U4015 : xor2 port map( a => mult_125_G3_ab_12_4_port, b => n1134, outb =>
n2758);
U4016 : xor2 port map( a => mult_125_G3_ab_13_4_port, b => n1136, outb =>
n5176);
U4017 : xor2 port map( a => mult_125_G3_ab_14_4_port, b => n1138, outb =>
n5177);
U4018 : xor2 port map( a => mult_125_G3_ab_15_4_port, b => n1141, outb =>
n5178);
U4019 : xor2 port map( a => n1144, b => mult_125_G3_ab_2_3_port, outb =>
n2762);
U4020 : xor2 port map( a => mult_125_G3_ab_3_3_port, b => n1147, outb =>
n5179);
U4021 : xor2 port map( a => mult_125_G3_ab_4_3_port, b => n1149, outb =>
n2764);
U4022 : xor2 port map( a => mult_125_G3_ab_5_3_port, b => n1151, outb =>
n5180);
U4023 : xor2 port map( a => mult_125_G3_ab_6_3_port, b => n1153, outb =>
n2767);
U4024 : xor2 port map( a => mult_125_G3_ab_7_3_port, b => n1155, outb =>
n5181);
U4025 : xor2 port map( a => mult_125_G3_ab_8_3_port, b => n1157, outb =>
n2770);
U4026 : xor2 port map( a => mult_125_G3_ab_9_3_port, b => n1159, outb =>
n5182);
U4027 : xor2 port map( a => mult_125_G3_ab_10_3_port, b => n1161, outb =>
n2773);
U4028 : xor2 port map( a => mult_125_G3_ab_11_3_port, b => n1163, outb =>
n5183);
U4029 : xor2 port map( a => n4109, b => n4107, outb => n2776);
U4030 : xor2 port map( a => mult_125_G3_ab_13_3_port, b => n1167, outb =>
n5184);
U4031 : xor2 port map( a => mult_125_G3_ab_14_3_port, b => n1169, outb =>
n2779);
U4032 : xor2 port map( a => mult_125_G3_ab_15_3_port, b => n1171, outb =>
n2781);
U4033 : xor2 port map( a => n1174, b => mult_125_G3_ab_2_2_port, outb =>
n2785);
U4034 : xor2 port map( a => n4115, b => n4113, outb => n5185);
U4035 : xor2 port map( a => mult_125_G3_ab_4_2_port, b => n1178, outb =>
n2787);
U4036 : xor2 port map( a => mult_125_G3_ab_5_2_port, b => n1180, outb =>
n5186);
U4037 : xor2 port map( a => mult_125_G3_ab_6_2_port, b => n1182, outb =>
n2790);
U4038 : xor2 port map( a => n1184, b => n1185, outb => n5187);
U4039 : xor2 port map( a => mult_125_G3_ab_8_2_port, b => n1187, outb =>
n2793);
U4040 : xor2 port map( a => mult_125_G3_ab_9_2_port, b => n1189, outb =>
n5188);
U4041 : xor2 port map( a => mult_125_G3_ab_10_2_port, b => n1191, outb =>
n2796);
U4042 : xor2 port map( a => mult_125_G3_ab_11_2_port, b => n1193, outb =>
n5189);
U4043 : xor2 port map( a => mult_125_G3_ab_12_2_port, b => n1195, outb =>
n2799);
U4044 : xor2 port map( a => mult_125_G3_ab_13_2_port, b => n1197, outb =>
n5190);
U4045 : xor2 port map( a => mult_125_G3_ab_14_2_port, b => n1199, outb =>
n2802);
U4046 : xor2 port map( a => n5087, b => n4130, outb => n5191);
U4047 : xor2 port map( a => n4133, b => mult_125_G3_ab_2_1_port, outb =>
n2806);
U4048 : xor2 port map( a => n4134, b => n4132, outb => n5192);
U4049 : xor2 port map( a => mult_125_G3_ab_4_1_port, b => n4136, outb =>
n2808);
U4050 : xor2 port map( a => mult_125_G3_ab_5_1_port, b => n1210, outb =>
n5204);
U4051 : xor2 port map( a => n4139, b => n1212, outb => n2811);
U4052 : xor2 port map( a => n5205, b => n1214, outb => n5194);
U4053 : xor2 port map( a => mult_125_G3_ab_8_1_port, b => n4140, outb =>
n2814);
U4054 : xor2 port map( a => n5206, b => n1218, outb => n5195);
U4055 : xor2 port map( a => n4145, b => n1220, outb => n2817);
U4056 : xor2 port map( a => n5207, b => n1222, outb => n5196);
U4057 : xor2 port map( a => n4148, b => n1224, outb => n2820);
U4058 : xor2 port map( a => n5208, b => n1226, outb => n5197);
U4059 : xor2 port map( a => n4151, b => n4149, outb => n2823);
U4060 : xor2 port map( a => n5209, b => n1230, outb => n5198);
U4061 : xor2 port map( a => mult_125_G3_ab_15_0_port, b => n1258, outb =>
n5199);
U4062 : xor2 port map( a => mult_125_G3_ab_11_0_port, b => n1250, outb =>
n2825);
U4063 : xor2 port map( a => mult_125_G3_ab_9_0_port, b => n1246, outb =>
n2826);
U4064 : xor2 port map( a => mult_125_G3_ab_7_0_port, b => n1242, outb =>
n2827);
U4065 : xor2 port map( a => mult_125_G3_ab_5_0_port, b => n1238, outb =>
n2828);
U4066 : xor2 port map( a => mult_125_G3_ab_3_0_port, b => n1234, outb =>
n2829);
U4067 : xor2 port map( a => n380, b => mult_125_G3_ZA, outb => n2830);
U4068 : xor2 port map( a => mult_125_G3_ab_13_0_port, b => n1254, outb =>
n2831);
U4069 : xor2 port map( a => n4774, b => adder_mem_array_3_26_port, outb =>
n3429);
U4070 : xor2 port map( a => n4772, b => adder_mem_array_3_24_port, outb =>
n3433);
U4071 : xor2 port map( a => n4770, b => adder_mem_array_3_22_port, outb =>
n3437);
U4072 : xor2 port map( a => n4768, b => adder_mem_array_3_20_port, outb =>
n3441);
U4073 : xor2 port map( a => n4766, b => adder_mem_array_3_18_port, outb =>
n3445);
U4074 : xor2 port map( a => n4764, b => adder_mem_array_3_16_port, outb =>
n3452);
U4075 : xor2 port map( a => n4762, b => adder_mem_array_3_14_port, outb =>
n3456);
U4076 : xor2 port map( a => n4760, b => adder_mem_array_3_12_port, outb =>
n3460);
U4077 : xor2 port map( a => n4758, b => adder_mem_array_3_10_port, outb =>
n3464);
U4078 : xor2 port map( a => n4756, b => adder_mem_array_3_8_port, outb =>
n3468);
U4079 : xor2 port map( a => n4754, b => adder_mem_array_3_6_port, outb =>
n3474);
U4080 : xor2 port map( a => n4752, b => adder_mem_array_3_4_port, outb =>
n3478);
U4081 : xor2 port map( a => n4750, b => adder_mem_array_3_2_port, outb =>
n3482);
U4082 : xor2 port map( a => n5107, b => adder_mem_array_3_32_port, outb =>
n3599);
U4083 : xor2 port map( a => n4840, b => adder_mem_array_3_30_port, outb =>
n3601);
U4084 : xor2 port map( a => n4838, b => adder_mem_array_3_28_port, outb =>
n3605);
U4085 : oai22 port map( a => n5211, b => n5212, c => n1260, d => n4179, outb
=> n5210);
U4086 : aoi22 port map( a => mult_125_G2_ab_2_15_port, b =>
mult_125_G2_ab_3_14_port, c => n5210, d => n5214,
outb => n5213);
U4087 : oai22 port map( a => n4180, b => n4181, c => n5213, d => n1262, outb
=> n5215);
U4088 : aoi22 port map( a => mult_125_G2_ab_4_15_port, b =>
mult_125_G2_ab_5_14_port, c => n5215, d => n5217,
outb => n5216);
U4089 : oai22 port map( a => n4182, b => n4183, c => n5216, d => n1264, outb
=> n5218);
U4090 : aoi22 port map( a => mult_125_G2_ab_6_15_port, b =>
mult_125_G2_ab_7_14_port, c => n5218, d => n5220,
outb => n5219);
U4091 : oai22 port map( a => n4184, b => n4185, c => n5219, d => n1266, outb
=> n5221);
U4092 : aoi22 port map( a => mult_125_G2_ab_8_15_port, b =>
mult_125_G2_ab_9_14_port, c => n5221, d => n5223,
outb => n5222);
U4093 : oai22 port map( a => n4186, b => n4187, c => n5222, d => n1268, outb
=> n5224);
U4094 : aoi22 port map( a => mult_125_G2_ab_10_15_port, b =>
mult_125_G2_ab_11_14_port, c => n5224, d => n5226,
outb => n5225);
U4095 : oai22 port map( a => n4188, b => n4189, c => n5225, d => n1270, outb
=> n5227);
U4096 : aoi22 port map( a => mult_125_G2_ab_12_15_port, b =>
mult_125_G2_ab_13_14_port, c => n5227, d => n5229,
outb => n5228);
U4097 : aoi22 port map( a => mult_125_G2_ab_13_15_port, b =>
mult_125_G2_ab_14_14_port, c => n5231, d => n5232,
outb => n5230);
U4098 : aoi22 port map( a => mult_125_G2_ab_14_15_port, b =>
mult_125_G2_ab_15_14_port, c => n5233, d => n5234,
outb => n313);
U4099 : inv port map( inb => n4207, outb => n1303);
U4100 : aoi22 port map( a => n1303, b => mult_125_G2_ab_15_13_port, c =>
n5235, d => n2874, outb => n315);
U4101 : aoi22 port map( a => n1332, b => mult_125_G2_ab_15_12_port, c =>
n5236, d => n2870, outb => n317);
U4102 : oai22 port map( a => n1363, b => n1362, c => n5238, d => n2915, outb
=> n5237);
U4103 : inv port map( inb => n1379, outb => n4257);
U4104 : aoi22 port map( a => n1393, b => mult_125_G2_ab_15_10_port, c =>
n5239, d => n2911, outb => n321);
U4105 : oai22 port map( a => n1423, b => n1422, c => n5241, d => n2956, outb
=> n5240);
U4106 : inv port map( inb => n1442, outb => n4301);
U4107 : aoi22 port map( a => n1452, b => mult_125_G2_ab_15_8_port, c =>
n5242, d => n2952, outb => n325);
U4108 : oai22 port map( a => n1483, b => n1482, c => n5244, d => n2997, outb
=> n5243);
U4109 : inv port map( inb => n1508, outb => n4341);
U4110 : aoi22 port map( a => n1514, b => mult_125_G2_ab_15_6_port, c =>
n5245, d => n2993, outb => n329);
U4111 : oai22 port map( a => n1546, b => n1545, c => n5247, d => n3038, outb
=> n5246);
U4112 : aoi22 port map( a => n5248, b => mult_125_G2_ab_15_4_port, c =>
n1577, d => n3034, outb => n333);
U4113 : aoi22 port map( a => n1609, b => mult_125_G2_ab_15_3_port, c =>
n5249, d => n3079, outb => n335);
U4114 : oai22 port map( a => n4415, b => n5250, c => n1638, d => n3075, outb
=> n338);
U4115 : aoi22 port map( a => n1668, b => mult_125_G2_ab_15_1_port, c =>
n5251, d => n3098, outb => n340);
U4116 : aoi22 port map( a => n1696, b => mult_125_G2_ab_15_0_port, c =>
n5252, d => n5253, outb => n342);
U4117 : aoi22 port map( a => adder_mem_array_2_1_port, b => n2167, c =>
n5254, d => n3484, outb => n3544);
U4118 : oai22 port map( a => n4780, b => n4781, c => n3544, d => n2168, outb
=> n3541);
U4119 : aoi22 port map( a => multiplier_sigs_1_3_port, b =>
adder_mem_array_2_3_port, c => n3541, d => n5255,
outb => n3540);
U4120 : oai22 port map( a => n4782, b => n4783, c => n3540, d => n2170, outb
=> n3537);
U4121 : aoi22 port map( a => multiplier_sigs_1_5_port, b =>
adder_mem_array_2_5_port, c => n3537, d => n5256,
outb => n3536);
U4122 : oai22 port map( a => n4784, b => n4785, c => n3536, d => n2172, outb
=> n3533);
U4123 : aoi22 port map( a => multiplier_sigs_1_7_port, b =>
adder_mem_array_2_7_port, c => n3533, d => n5257,
outb => n3532);
U4124 : oai22 port map( a => n4786, b => n4787, c => n3532, d => n2174, outb
=> n3529);
U4125 : aoi22 port map( a => multiplier_sigs_1_9_port, b =>
adder_mem_array_2_9_port, c => n3529, d => n5258,
outb => n3528);
U4126 : oai22 port map( a => n4788, b => n4789, c => n3528, d => n2176, outb
=> n3525);
U4127 : aoi22 port map( a => multiplier_sigs_1_11_port, b =>
adder_mem_array_2_11_port, c => n3525, d => n5259,
outb => n3524);
U4128 : oai22 port map( a => n4790, b => n4791, c => n3524, d => n2178, outb
=> n3521);
U4129 : aoi22 port map( a => multiplier_sigs_1_13_port, b =>
adder_mem_array_2_13_port, c => n3521, d => n5260,
outb => n3520);
U4130 : oai22 port map( a => n4792, b => n4793, c => n3520, d => n2180, outb
=> n3517);
U4131 : aoi22 port map( a => multiplier_sigs_1_15_port, b =>
adder_mem_array_2_15_port, c => n3517, d => n5261,
outb => n3516);
U4132 : oai22 port map( a => n4794, b => n4795, c => n3516, d => n2182, outb
=> n3513);
U4133 : aoi22 port map( a => multiplier_sigs_1_17_port, b =>
adder_mem_array_2_17_port, c => n3513, d => n5262,
outb => n3512);
U4134 : oai22 port map( a => n4796, b => n4797, c => n3512, d => n2184, outb
=> n3509);
U4135 : aoi22 port map( a => multiplier_sigs_1_19_port, b =>
adder_mem_array_2_19_port, c => n3509, d => n5263,
outb => n3508);
U4136 : oai22 port map( a => n4798, b => n4799, c => n3508, d => n2186, outb
=> n3505);
U4137 : aoi22 port map( a => multiplier_sigs_1_21_port, b =>
adder_mem_array_2_21_port, c => n3505, d => n5264,
outb => n3504);
U4138 : oai22 port map( a => n4800, b => n4801, c => n3504, d => n2188, outb
=> n3501);
U4139 : aoi22 port map( a => multiplier_sigs_1_23_port, b =>
adder_mem_array_2_23_port, c => n3501, d => n5265,
outb => n3500);
U4140 : oai22 port map( a => n4802, b => n4803, c => n3500, d => n2190, outb
=> n3497);
U4141 : aoi22 port map( a => multiplier_sigs_1_25_port, b =>
adder_mem_array_2_25_port, c => n3497, d => n5266,
outb => n3496);
U4142 : oai22 port map( a => n4804, b => n4805, c => n3496, d => n2192, outb
=> n3493);
U4143 : aoi22 port map( a => multiplier_sigs_1_27_port, b =>
adder_mem_array_2_27_port, c => n3493, d => n5267,
outb => n3492);
U4144 : oai22 port map( a => n4806, b => n4807, c => n3492, d => n2194, outb
=> n3489);
U4145 : aoi22 port map( a => multiplier_sigs_1_29_port, b =>
adder_mem_array_2_29_port, c => n3489, d => n5268,
outb => n3488);
U4146 : oai22 port map( a => n4808, b => n4809, c => n3488, d => n2196, outb
=> n2199);
U4147 : nand2 port map( a => n5269, b => n5270, outb => n2198);
U4148 : xor2 port map( a => n5210, b => n4887, outb => n2842);
U4149 : xor2 port map( a => n5271, b => n5213, outb => n2845);
U4150 : xor2 port map( a => n5215, b => n4888, outb => n2848);
U4151 : xor2 port map( a => n5272, b => n5216, outb => n2851);
U4152 : xor2 port map( a => n5218, b => n4889, outb => n2854);
U4153 : xor2 port map( a => n5273, b => n5219, outb => n2857);
U4154 : xor2 port map( a => n5221, b => n4890, outb => n2860);
U4155 : xor2 port map( a => n5274, b => n5222, outb => n2863);
U4156 : xor2 port map( a => n5224, b => n4891, outb => n2866);
U4157 : xor2 port map( a => n5275, b => n5225, outb => n2869);
U4158 : xor2 port map( a => n5227, b => n4892, outb => n2872);
U4159 : xor2 port map( a => n5276, b => n5231, outb => n2874);
U4160 : xor2 port map( a => n5230, b => n4893, outb => n316);
U4161 : xor2 port map( a => n5277, b => n2835, outb => n2880);
U4162 : xor2 port map( a => n5278, b => n2838, outb => n2886);
U4163 : xor2 port map( a => n5279, b => n2840, outb => n2889);
U4164 : xor2 port map( a => n5280, b => n2843, outb => n2892);
U4165 : xor2 port map( a => n5281, b => n2846, outb => n2895);
U4166 : xor2 port map( a => n5282, b => n2849, outb => n2898);
U4167 : xor2 port map( a => n5283, b => n2852, outb => n2901);
U4168 : xor2 port map( a => n5284, b => n2855, outb => n2904);
U4169 : xor2 port map( a => n5285, b => n2858, outb => n2907);
U4170 : xor2 port map( a => n5286, b => n2861, outb => n2910);
U4171 : xor2 port map( a => n5287, b => n2864, outb => n2913);
U4172 : xor2 port map( a => n5288, b => n2867, outb => n2915);
U4173 : xor2 port map( a => n5289, b => n2870, outb => n320);
U4174 : xor2 port map( a => n5290, b => n2876, outb => n2921);
U4175 : xor2 port map( a => n5291, b => n2878, outb => n2924);
U4176 : xor2 port map( a => n5292, b => n2882, outb => n2930);
U4177 : xor2 port map( a => n5293, b => n2884, outb => n2933);
U4178 : xor2 port map( a => n5294, b => n2887, outb => n2936);
U4179 : xor2 port map( a => n5295, b => n2890, outb => n2939);
U4180 : xor2 port map( a => n5296, b => n2893, outb => n2942);
U4181 : xor2 port map( a => n5297, b => n2896, outb => n2945);
U4182 : xor2 port map( a => n5298, b => n2899, outb => n2948);
U4183 : xor2 port map( a => n5299, b => n2902, outb => n2951);
U4184 : xor2 port map( a => n5300, b => n2905, outb => n2954);
U4185 : xor2 port map( a => n5301, b => n2908, outb => n2956);
U4186 : xor2 port map( a => n5302, b => n2911, outb => n324);
U4187 : xor2 port map( a => n5303, b => n2917, outb => n2962);
U4188 : xor2 port map( a => n5304, b => n2919, outb => n2965);
U4189 : xor2 port map( a => n5305, b => n2922, outb => n2968);
U4190 : xor2 port map( a => n5306, b => n2926, outb => n2974);
U4191 : xor2 port map( a => n5307, b => n2928, outb => n2977);
U4192 : xor2 port map( a => n5308, b => n2931, outb => n2980);
U4193 : xor2 port map( a => n5309, b => n2934, outb => n2983);
U4194 : xor2 port map( a => n5310, b => n2937, outb => n2986);
U4195 : xor2 port map( a => n5311, b => n2940, outb => n2989);
U4196 : xor2 port map( a => n5312, b => n2943, outb => n2992);
U4197 : xor2 port map( a => n5313, b => n2946, outb => n2995);
U4198 : xor2 port map( a => n5314, b => n2949, outb => n2997);
U4199 : xor2 port map( a => n5315, b => n2952, outb => n328);
U4200 : xor2 port map( a => n5316, b => n2958, outb => n3003);
U4201 : xor2 port map( a => n5317, b => n2960, outb => n3006);
U4202 : xor2 port map( a => n5318, b => n2963, outb => n3009);
U4203 : xor2 port map( a => n5319, b => n2966, outb => n3012);
U4204 : xor2 port map( a => n5320, b => n2970, outb => n3018);
U4205 : xor2 port map( a => n5321, b => n2972, outb => n3021);
U4206 : xor2 port map( a => n5322, b => n2975, outb => n3024);
U4207 : xor2 port map( a => n5323, b => n2978, outb => n3027);
U4208 : xor2 port map( a => n5324, b => n2981, outb => n3030);
U4209 : xor2 port map( a => n5325, b => n2984, outb => n3033);
U4210 : xor2 port map( a => n5326, b => n2987, outb => n3036);
U4211 : xor2 port map( a => n5327, b => n2990, outb => n3038);
U4212 : xor2 port map( a => n5328, b => n2993, outb => n332);
U4213 : xor2 port map( a => n5329, b => n2999, outb => n3044);
U4214 : xor2 port map( a => n5330, b => n3001, outb => n3047);
U4215 : xor2 port map( a => n5331, b => n3004, outb => n3050);
U4216 : xor2 port map( a => n5332, b => n3007, outb => n3053);
U4217 : xor2 port map( a => n5333, b => n3010, outb => n3056);
U4218 : xor2 port map( a => n5334, b => n3014, outb => n3062);
U4219 : xor2 port map( a => n5335, b => n3016, outb => n3065);
U4220 : xor2 port map( a => n5336, b => n3019, outb => n3068);
U4221 : xor2 port map( a => n5337, b => n3022, outb => n3071);
U4222 : xor2 port map( a => n5338, b => n3025, outb => n3074);
U4223 : xor2 port map( a => n5339, b => n3028, outb => n3077);
U4224 : xor2 port map( a => n5340, b => n3031, outb => n3079);
U4225 : xor2 port map( a => n5341, b => n3034, outb => n336);
U4226 : xor2 port map( a => n5342, b => n3040, outb => n3085);
U4227 : xor2 port map( a => n5343, b => n3042, outb => n3088);
U4228 : xor2 port map( a => n5344, b => n3045, outb => n3091);
U4229 : xor2 port map( a => n5345, b => n3048, outb => n3094);
U4230 : xor2 port map( a => n5346, b => n3051, outb => n3097);
U4231 : xor2 port map( a => n5347, b => n3054, outb => n3100);
U4232 : xor2 port map( a => n5348, b => n3058, outb => n3106);
U4233 : xor2 port map( a => n5349, b => n3060, outb => n3109);
U4234 : xor2 port map( a => n5350, b => n3063, outb => n3112);
U4235 : xor2 port map( a => n5351, b => n3066, outb => n3115);
U4236 : xor2 port map( a => n5352, b => n3069, outb => n3118);
U4237 : xor2 port map( a => n5353, b => n3072, outb => n3121);
U4238 : xor2 port map( a => n5354, b => n3075, outb => n341);
U4239 : xor2 port map( a => n5355, b => n3081, outb => n4443);
U4240 : xor2 port map( a => n5356, b => n3083, outb => n4447);
U4241 : xor2 port map( a => n5357, b => n3086, outb => n4451);
U4242 : xor2 port map( a => n5358, b => n3089, outb => n4455);
U4243 : xor2 port map( a => n5359, b => n3092, outb => n4459);
U4244 : xor2 port map( a => n5360, b => n3095, outb => n4463);
U4245 : inv port map( inb => n3119, outb => n5253);
U4246 : xor2 port map( a => n5361, b => n3098, outb => n343);
U4247 : xor2 port map( a => n5362, b => n3119, outb => n347);
U4248 : xor2 port map( a => n4179, b => mult_125_G2_ab_2_14_port, outb =>
n2836);
U4249 : xor2 port map( a => n4180, b => n4181, outb => n5271);
U4250 : xor2 port map( a => n4182, b => n4183, outb => n5272);
U4251 : xor2 port map( a => n4184, b => n4185, outb => n5273);
U4252 : xor2 port map( a => n4186, b => n4187, outb => n5274);
U4253 : xor2 port map( a => n4188, b => n4189, outb => n5275);
U4254 : xor2 port map( a => mult_125_G2_ab_13_15_port, b =>
mult_125_G2_ab_14_14_port, outb => n5276);
U4255 : xor2 port map( a => n4190, b => n1275, outb => n2839);
U4256 : xor2 port map( a => mult_125_G2_ab_3_13_port, b => n1279, outb =>
n5277);
U4257 : xor2 port map( a => mult_125_G2_ab_4_13_port, b => n1281, outb =>
n2841);
U4258 : xor2 port map( a => mult_125_G2_ab_5_13_port, b => n1283, outb =>
n2844);
U4259 : xor2 port map( a => mult_125_G2_ab_6_13_port, b => n1285, outb =>
n2847);
U4260 : xor2 port map( a => n4197, b => n4195, outb => n2850);
U4261 : xor2 port map( a => mult_125_G2_ab_8_13_port, b => n1289, outb =>
n2853);
U4262 : xor2 port map( a => n4200, b => n4198, outb => n2856);
U4263 : xor2 port map( a => mult_125_G2_ab_10_13_port, b => n1293, outb =>
n2859);
U4264 : xor2 port map( a => n4203, b => n4201, outb => n2862);
U4265 : xor2 port map( a => mult_125_G2_ab_12_13_port, b => n1297, outb =>
n2865);
U4266 : xor2 port map( a => n4206, b => n4204, outb => n2868);
U4267 : xor2 port map( a => mult_125_G2_ab_14_13_port, b => n1301, outb =>
n2871);
U4268 : xor2 port map( a => mult_125_G2_ab_15_13_port, b => n4207, outb =>
n2873);
U4269 : xor2 port map( a => n1306, b => mult_125_G2_ab_2_12_port, outb =>
n2877);
U4270 : xor2 port map( a => n4211, b => n4209, outb => n5278);
U4271 : xor2 port map( a => mult_125_G2_ab_4_12_port, b => n1310, outb =>
n2879);
U4272 : xor2 port map( a => mult_125_G2_ab_5_12_port, b => n4212, outb =>
n5279);
U4273 : xor2 port map( a => n4216, b => n4214, outb => n5280);
U4274 : xor2 port map( a => mult_125_G2_ab_7_12_port, b => n1316, outb =>
n5281);
U4275 : xor2 port map( a => n4219, b => n4217, outb => n5282);
U4276 : xor2 port map( a => mult_125_G2_ab_9_12_port, b => n1320, outb =>
n5283);
U4277 : xor2 port map( a => n4222, b => n4220, outb => n5284);
U4278 : xor2 port map( a => mult_125_G2_ab_11_12_port, b => n1324, outb =>
n5285);
U4279 : xor2 port map( a => n4225, b => n4223, outb => n5286);
U4280 : xor2 port map( a => mult_125_G2_ab_13_12_port, b => n1328, outb =>
n5287);
U4281 : xor2 port map( a => n4228, b => n4226, outb => n5288);
U4282 : xor2 port map( a => n5363, b => n1332, outb => n5289);
U4283 : xor2 port map( a => n1335, b => mult_125_G2_ab_2_11_port, outb =>
n2883);
U4284 : xor2 port map( a => mult_125_G2_ab_3_11_port, b => n1338, outb =>
n5290);
U4285 : xor2 port map( a => n4232, b => n4231, outb => n2885);
U4286 : xor2 port map( a => mult_125_G2_ab_5_11_port, b => n1342, outb =>
n5291);
U4287 : xor2 port map( a => mult_125_G2_ab_6_11_port, b => n1344, outb =>
n2888);
U4288 : xor2 port map( a => n4237, b => n4236, outb => n2891);
U4289 : xor2 port map( a => mult_125_G2_ab_8_11_port, b => n1348, outb =>
n2894);
U4290 : xor2 port map( a => n4240, b => n4238, outb => n2897);
U4291 : xor2 port map( a => mult_125_G2_ab_10_11_port, b => n1352, outb =>
n2900);
U4292 : xor2 port map( a => n4243, b => n4241, outb => n2903);
U4293 : xor2 port map( a => mult_125_G2_ab_12_11_port, b => n1356, outb =>
n2906);
U4294 : xor2 port map( a => n4246, b => n4244, outb => n2909);
U4295 : xor2 port map( a => mult_125_G2_ab_14_11_port, b => n1360, outb =>
n2912);
U4296 : xor2 port map( a => n1362, b => n1363, outb => n2914);
U4297 : xor2 port map( a => n1366, b => mult_125_G2_ab_2_10_port, outb =>
n2918);
U4298 : xor2 port map( a => n4250, b => n4248, outb => n5292);
U4299 : xor2 port map( a => mult_125_G2_ab_4_10_port, b => n1370, outb =>
n2920);
U4300 : xor2 port map( a => n1372, b => n1373, outb => n5293);
U4301 : xor2 port map( a => mult_125_G2_ab_6_10_port, b => n1375, outb =>
n2923);
U4302 : xor2 port map( a => mult_125_G2_ab_7_10_port, b => n1377, outb =>
n5294);
U4303 : xor2 port map( a => n4256, b => n4257, outb => n5295);
U4304 : xor2 port map( a => mult_125_G2_ab_9_10_port, b => n1381, outb =>
n5296);
U4305 : xor2 port map( a => n4260, b => n4258, outb => n5297);
U4306 : xor2 port map( a => mult_125_G2_ab_11_10_port, b => n1385, outb =>
n5298);
U4307 : xor2 port map( a => n4263, b => n4261, outb => n5299);
U4308 : xor2 port map( a => mult_125_G2_ab_13_10_port, b => n1389, outb =>
n5300);
U4309 : xor2 port map( a => n4266, b => n4264, outb => n5301);
U4310 : xor2 port map( a => n5364, b => n1393, outb => n5302);
U4311 : xor2 port map( a => n1396, b => mult_125_G2_ab_2_9_port, outb =>
n2927);
U4312 : xor2 port map( a => n4269, b => n4267, outb => n5303);
U4313 : xor2 port map( a => mult_125_G2_ab_4_9_port, b => n1400, outb =>
n2929);
U4314 : xor2 port map( a => mult_125_G2_ab_5_9_port, b => n1402, outb =>
n5304);
U4315 : xor2 port map( a => mult_125_G2_ab_6_9_port, b => n1404, outb =>
n2932);
U4316 : xor2 port map( a => mult_125_G2_ab_7_9_port, b => n1406, outb =>
n5305);
U4317 : xor2 port map( a => n4277, b => n4275, outb => n2935);
U4318 : xor2 port map( a => n4279, b => n4278, outb => n2938);
U4319 : xor2 port map( a => mult_125_G2_ab_10_9_port, b => n1412, outb =>
n2941);
U4320 : xor2 port map( a => n4282, b => n4280, outb => n2944);
U4321 : xor2 port map( a => mult_125_G2_ab_12_9_port, b => n1416, outb =>
n2947);
U4322 : xor2 port map( a => n4285, b => n4283, outb => n2950);
U4323 : xor2 port map( a => mult_125_G2_ab_14_9_port, b => n1420, outb =>
n2953);
U4324 : xor2 port map( a => n1422, b => n1423, outb => n2955);
U4325 : xor2 port map( a => n1426, b => mult_125_G2_ab_2_8_port, outb =>
n2959);
U4326 : xor2 port map( a => n4289, b => n4287, outb => n5306);
U4327 : xor2 port map( a => n4291, b => n1430, outb => n2961);
U4328 : xor2 port map( a => n4293, b => n4292, outb => n5307);
U4329 : xor2 port map( a => mult_125_G2_ab_6_8_port, b => n1434, outb =>
n2964);
U4330 : xor2 port map( a => n4296, b => n4294, outb => n5308);
U4331 : xor2 port map( a => mult_125_G2_ab_8_8_port, b => n1438, outb =>
n2967);
U4332 : xor2 port map( a => mult_125_G2_ab_9_8_port, b => n1440, outb =>
n5309);
U4333 : xor2 port map( a => n4300, b => n4301, outb => n5310);
U4334 : xor2 port map( a => mult_125_G2_ab_11_8_port, b => n1444, outb =>
n5311);
U4335 : xor2 port map( a => n4304, b => n4302, outb => n5312);
U4336 : xor2 port map( a => mult_125_G2_ab_13_8_port, b => n1448, outb =>
n5313);
U4337 : xor2 port map( a => n4307, b => n4305, outb => n5314);
U4338 : xor2 port map( a => n5365, b => n1452, outb => n5315);
U4339 : xor2 port map( a => n1455, b => mult_125_G2_ab_2_7_port, outb =>
n2971);
U4340 : xor2 port map( a => mult_125_G2_ab_3_7_port, b => n1458, outb =>
n5316);
U4341 : xor2 port map( a => n4311, b => n4310, outb => n2973);
U4342 : xor2 port map( a => mult_125_G2_ab_5_7_port, b => n1462, outb =>
n5317);
U4343 : xor2 port map( a => n4314, b => n4312, outb => n2976);
U4344 : xor2 port map( a => mult_125_G2_ab_7_7_port, b => n1466, outb =>
n5318);
U4345 : xor2 port map( a => n4317, b => n4315, outb => n2979);
U4346 : xor2 port map( a => mult_125_G2_ab_9_7_port, b => n1470, outb =>
n5319);
U4347 : xor2 port map( a => n4320, b => n4318, outb => n2982);
U4348 : xor2 port map( a => n4322, b => n4321, outb => n2985);
U4349 : xor2 port map( a => mult_125_G2_ab_12_7_port, b => n1476, outb =>
n2988);
U4350 : xor2 port map( a => n4325, b => n4323, outb => n2991);
U4351 : xor2 port map( a => mult_125_G2_ab_14_7_port, b => n1480, outb =>
n2994);
U4352 : xor2 port map( a => n1482, b => n1483, outb => n2996);
U4353 : xor2 port map( a => n1486, b => mult_125_G2_ab_2_6_port, outb =>
n3000);
U4354 : xor2 port map( a => n4329, b => n4327, outb => n5320);
U4355 : xor2 port map( a => mult_125_G2_ab_4_6_port, b => n1490, outb =>
n3002);
U4356 : xor2 port map( a => n1492, b => n1493, outb => n5321);
U4357 : xor2 port map( a => mult_125_G2_ab_6_6_port, b => n1495, outb =>
n3005);
U4358 : xor2 port map( a => n4334, b => n4332, outb => n5322);
U4359 : xor2 port map( a => mult_125_G2_ab_8_6_port, b => n1499, outb =>
n3008);
U4360 : xor2 port map( a => n1501, b => n1502, outb => n5323);
U4361 : xor2 port map( a => mult_125_G2_ab_10_6_port, b => n1504, outb =>
n3011);
U4362 : xor2 port map( a => mult_125_G2_ab_11_6_port, b => n1506, outb =>
n5324);
U4363 : xor2 port map( a => n4340, b => n4341, outb => n5325);
U4364 : xor2 port map( a => mult_125_G2_ab_13_6_port, b => n1510, outb =>
n5326);
U4365 : xor2 port map( a => n4344, b => n4342, outb => n5327);
U4366 : xor2 port map( a => n5366, b => n1514, outb => n5328);
U4367 : xor2 port map( a => n1517, b => mult_125_G2_ab_2_5_port, outb =>
n3015);
U4368 : xor2 port map( a => mult_125_G2_ab_3_5_port, b => n1520, outb =>
n5329);
U4369 : xor2 port map( a => mult_125_G2_ab_4_5_port, b => n1522, outb =>
n3017);
U4370 : xor2 port map( a => mult_125_G2_ab_5_5_port, b => n1524, outb =>
n5330);
U4371 : xor2 port map( a => n1526, b => n1527, outb => n3020);
U4372 : xor2 port map( a => mult_125_G2_ab_7_5_port, b => n1529, outb =>
n5331);
U4373 : xor2 port map( a => mult_125_G2_ab_8_5_port, b => n1531, outb =>
n3023);
U4374 : xor2 port map( a => mult_125_G2_ab_9_5_port, b => n1533, outb =>
n5332);
U4375 : xor2 port map( a => n4356, b => n4354, outb => n3026);
U4376 : xor2 port map( a => mult_125_G2_ab_11_5_port, b => n1537, outb =>
n5333);
U4377 : xor2 port map( a => n4359, b => n4357, outb => n3029);
U4378 : xor2 port map( a => n4361, b => n1541, outb => n3032);
U4379 : xor2 port map( a => mult_125_G2_ab_14_5_port, b => n1543, outb =>
n3035);
U4380 : xor2 port map( a => n1545, b => n1546, outb => n3037);
U4381 : xor2 port map( a => n1549, b => mult_125_G2_ab_2_4_port, outb =>
n3041);
U4382 : xor2 port map( a => n4365, b => n4363, outb => n5334);
U4383 : xor2 port map( a => mult_125_G2_ab_4_4_port, b => n1553, outb =>
n3043);
U4384 : xor2 port map( a => n1555, b => n1556, outb => n5335);
U4385 : xor2 port map( a => mult_125_G2_ab_6_4_port, b => n1558, outb =>
n3046);
U4386 : xor2 port map( a => n1560, b => n1561, outb => n5336);
U4387 : xor2 port map( a => mult_125_G2_ab_8_4_port, b => n1563, outb =>
n3049);
U4388 : xor2 port map( a => mult_125_G2_ab_9_4_port, b => n1565, outb =>
n5337);
U4389 : xor2 port map( a => mult_125_G2_ab_10_4_port, b => n1567, outb =>
n3052);
U4390 : xor2 port map( a => n1569, b => n1570, outb => n5338);
U4391 : xor2 port map( a => mult_125_G2_ab_12_4_port, b => n1572, outb =>
n3055);
U4392 : xor2 port map( a => mult_125_G2_ab_13_4_port, b => n1574, outb =>
n5339);
U4393 : xor2 port map( a => mult_125_G2_ab_14_4_port, b => n1576, outb =>
n5340);
U4394 : xor2 port map( a => mult_125_G2_ab_15_4_port, b => n1579, outb =>
n5341);
U4395 : xor2 port map( a => n1582, b => mult_125_G2_ab_2_3_port, outb =>
n3059);
U4396 : xor2 port map( a => mult_125_G2_ab_3_3_port, b => n1585, outb =>
n5342);
U4397 : xor2 port map( a => mult_125_G2_ab_4_3_port, b => n1587, outb =>
n3061);
U4398 : xor2 port map( a => mult_125_G2_ab_5_3_port, b => n1589, outb =>
n5343);
U4399 : xor2 port map( a => mult_125_G2_ab_6_3_port, b => n1591, outb =>
n3064);
U4400 : xor2 port map( a => mult_125_G2_ab_7_3_port, b => n1593, outb =>
n5344);
U4401 : xor2 port map( a => mult_125_G2_ab_8_3_port, b => n1595, outb =>
n3067);
U4402 : xor2 port map( a => mult_125_G2_ab_9_3_port, b => n1597, outb =>
n5345);
U4403 : xor2 port map( a => mult_125_G2_ab_10_3_port, b => n1599, outb =>
n3070);
U4404 : xor2 port map( a => mult_125_G2_ab_11_3_port, b => n1601, outb =>
n5346);
U4405 : xor2 port map( a => n4394, b => n4392, outb => n3073);
U4406 : xor2 port map( a => mult_125_G2_ab_13_3_port, b => n1605, outb =>
n5347);
U4407 : xor2 port map( a => mult_125_G2_ab_14_3_port, b => n1607, outb =>
n3076);
U4408 : xor2 port map( a => mult_125_G2_ab_15_3_port, b => n1609, outb =>
n3078);
U4409 : xor2 port map( a => n1612, b => mult_125_G2_ab_2_2_port, outb =>
n3082);
U4410 : xor2 port map( a => n4400, b => n4398, outb => n5348);
U4411 : xor2 port map( a => mult_125_G2_ab_4_2_port, b => n1616, outb =>
n3084);
U4412 : xor2 port map( a => mult_125_G2_ab_5_2_port, b => n1618, outb =>
n5349);
U4413 : xor2 port map( a => mult_125_G2_ab_6_2_port, b => n1620, outb =>
n3087);
U4414 : xor2 port map( a => n1622, b => n1623, outb => n5350);
U4415 : xor2 port map( a => mult_125_G2_ab_8_2_port, b => n1625, outb =>
n3090);
U4416 : xor2 port map( a => mult_125_G2_ab_9_2_port, b => n1627, outb =>
n5351);
U4417 : xor2 port map( a => mult_125_G2_ab_10_2_port, b => n1629, outb =>
n3093);
U4418 : xor2 port map( a => mult_125_G2_ab_11_2_port, b => n1631, outb =>
n5352);
U4419 : xor2 port map( a => mult_125_G2_ab_12_2_port, b => n1633, outb =>
n3096);
U4420 : xor2 port map( a => mult_125_G2_ab_13_2_port, b => n1635, outb =>
n5353);
U4421 : xor2 port map( a => mult_125_G2_ab_14_2_port, b => n1637, outb =>
n3099);
U4422 : xor2 port map( a => n5250, b => n4415, outb => n5354);
U4423 : xor2 port map( a => n4418, b => mult_125_G2_ab_2_1_port, outb =>
n3103);
U4424 : xor2 port map( a => n4419, b => n4417, outb => n5355);
U4425 : xor2 port map( a => mult_125_G2_ab_4_1_port, b => n4421, outb =>
n3105);
U4426 : xor2 port map( a => mult_125_G2_ab_5_1_port, b => n1648, outb =>
n5367);
U4427 : xor2 port map( a => n4424, b => n1650, outb => n3108);
U4428 : xor2 port map( a => n5368, b => n1652, outb => n5357);
U4429 : xor2 port map( a => mult_125_G2_ab_8_1_port, b => n4425, outb =>
n3111);
U4430 : xor2 port map( a => n5369, b => n1656, outb => n5358);
U4431 : xor2 port map( a => n4430, b => n1658, outb => n3114);
U4432 : xor2 port map( a => n5370, b => n1660, outb => n5359);
U4433 : xor2 port map( a => n4433, b => n1662, outb => n3117);
U4434 : xor2 port map( a => n5371, b => n1664, outb => n5360);
U4435 : xor2 port map( a => n4436, b => n4434, outb => n3120);
U4436 : xor2 port map( a => n5372, b => n1668, outb => n5361);
U4437 : xor2 port map( a => mult_125_G2_ab_15_0_port, b => n1696, outb =>
n5362);
U4438 : xor2 port map( a => mult_125_G2_ab_11_0_port, b => n1688, outb =>
n3122);
U4439 : xor2 port map( a => mult_125_G2_ab_9_0_port, b => n1684, outb =>
n3123);
U4440 : xor2 port map( a => mult_125_G2_ab_7_0_port, b => n1680, outb =>
n3124);
U4441 : xor2 port map( a => mult_125_G2_ab_5_0_port, b => n1676, outb =>
n3125);
U4442 : xor2 port map( a => mult_125_G2_ab_3_0_port, b => n1672, outb =>
n3126);
U4443 : xor2 port map( a => n344, b => mult_125_G2_ZA, outb => n3127);
U4444 : xor2 port map( a => mult_125_G2_ab_13_0_port, b => n1692, outb =>
n3128);
U4445 : xor2 port map( a => n5270, b => adder_mem_array_2_32_port, outb =>
n3485);
U4446 : xor2 port map( a => n4808, b => adder_mem_array_2_30_port, outb =>
n3487);
U4447 : xor2 port map( a => n4806, b => adder_mem_array_2_28_port, outb =>
n3491);
U4448 : xor2 port map( a => n4804, b => adder_mem_array_2_26_port, outb =>
n3495);
U4449 : xor2 port map( a => n4802, b => adder_mem_array_2_24_port, outb =>
n3499);
U4450 : xor2 port map( a => n4800, b => adder_mem_array_2_22_port, outb =>
n3503);
U4451 : xor2 port map( a => n4798, b => adder_mem_array_2_20_port, outb =>
n3507);
U4452 : xor2 port map( a => n4796, b => adder_mem_array_2_18_port, outb =>
n3511);
U4453 : xor2 port map( a => n4794, b => adder_mem_array_2_16_port, outb =>
n3515);
U4454 : xor2 port map( a => n4792, b => adder_mem_array_2_14_port, outb =>
n3519);
U4455 : xor2 port map( a => n4790, b => adder_mem_array_2_12_port, outb =>
n3523);
U4456 : xor2 port map( a => n4788, b => adder_mem_array_2_10_port, outb =>
n3527);
U4457 : xor2 port map( a => n4786, b => adder_mem_array_2_8_port, outb =>
n3531);
U4458 : xor2 port map( a => n4784, b => adder_mem_array_2_6_port, outb =>
n3535);
U4459 : xor2 port map( a => n4782, b => adder_mem_array_2_4_port, outb =>
n3539);
U4460 : xor2 port map( a => n4780, b => adder_mem_array_2_2_port, outb =>
n3543);
U4461 : oai22 port map( a => n5374, b => n5375, c => n1698, d => n4464, outb
=> n5373);
U4462 : aoi22 port map( a => mult_125_ab_2_15_port, b =>
mult_125_ab_3_14_port, c => n5373, d => n5377, outb
=> n5376);
U4463 : oai22 port map( a => n4465, b => n4466, c => n5376, d => n1700, outb
=> n5378);
U4464 : aoi22 port map( a => mult_125_ab_4_15_port, b =>
mult_125_ab_5_14_port, c => n5378, d => n5380, outb
=> n5379);
U4465 : oai22 port map( a => n4467, b => n4468, c => n5379, d => n1702, outb
=> n5381);
U4466 : aoi22 port map( a => mult_125_ab_6_15_port, b =>
mult_125_ab_7_14_port, c => n5381, d => n5383, outb
=> n5382);
U4467 : oai22 port map( a => n4469, b => n4470, c => n5382, d => n1704, outb
=> n5384);
U4468 : aoi22 port map( a => mult_125_ab_8_15_port, b =>
mult_125_ab_9_14_port, c => n5384, d => n5386, outb
=> n5385);
U4469 : oai22 port map( a => n4471, b => n4472, c => n5385, d => n1706, outb
=> n5387);
U4470 : aoi22 port map( a => mult_125_ab_10_15_port, b =>
mult_125_ab_11_14_port, c => n5387, d => n5389, outb
=> n5388);
U4471 : oai22 port map( a => n4473, b => n4474, c => n5388, d => n1708, outb
=> n5390);
U4472 : aoi22 port map( a => mult_125_ab_12_15_port, b =>
mult_125_ab_13_14_port, c => n5390, d => n5392, outb
=> n5391);
U4473 : aoi22 port map( a => mult_125_ab_13_15_port, b =>
mult_125_ab_14_14_port, c => n5394, d => n5395, outb
=> n5393);
U4474 : aoi22 port map( a => mult_125_ab_14_15_port, b =>
mult_125_ab_15_14_port, c => n5396, d => n5397, outb
=> n277);
U4475 : inv port map( inb => n4492, outb => n1741);
U4476 : aoi22 port map( a => n1741, b => mult_125_ab_15_13_port, c => n5398,
d => n3171, outb => n279);
U4477 : aoi22 port map( a => n1770, b => mult_125_ab_15_12_port, c => n5399,
d => n3167, outb => n281);
U4478 : oai22 port map( a => n1801, b => n1800, c => n5401, d => n3212, outb
=> n5400);
U4479 : inv port map( inb => n1817, outb => n4542);
U4480 : aoi22 port map( a => n1831, b => mult_125_ab_15_10_port, c => n5402,
d => n3208, outb => n285);
U4481 : oai22 port map( a => n1861, b => n1860, c => n5404, d => n3253, outb
=> n5403);
U4482 : inv port map( inb => n1880, outb => n4586);
U4483 : aoi22 port map( a => n1890, b => mult_125_ab_15_8_port, c => n5405,
d => n3249, outb => n289);
U4484 : oai22 port map( a => n1921, b => n1920, c => n5407, d => n3294, outb
=> n5406);
U4485 : inv port map( inb => n1946, outb => n4626);
U4486 : aoi22 port map( a => n1952, b => mult_125_ab_15_6_port, c => n5408,
d => n3290, outb => n293);
U4487 : oai22 port map( a => n1984, b => n1983, c => n5410, d => n3335, outb
=> n5409);
U4488 : aoi22 port map( a => n5411, b => mult_125_ab_15_4_port, c => n2015,
d => n3331, outb => n297);
U4489 : aoi22 port map( a => n2047, b => mult_125_ab_15_3_port, c => n5412,
d => n3376, outb => n299);
U4490 : oai22 port map( a => n4700, b => n5413, c => n2076, d => n3372, outb
=> n302);
U4491 : aoi22 port map( a => n2106, b => mult_125_ab_15_1_port, c => n5414,
d => n3395, outb => n304);
U4492 : aoi22 port map( a => n2134, b => mult_125_ab_15_0_port, c => n5415,
d => n5416, outb => n306);
U4493 : aoi22 port map( a => adder_mem_array_1_1_port, b => n2164, c =>
n5417, d => n3447, outb => n3471);
U4494 : oai22 port map( a => n4777, b => n4778, c => n3471, d => n2165, outb
=> n3448);
U4495 : aoi22 port map( a => adder_mem_array_1_3_port, b =>
multiplier_sigs_0_3_port, c => n3448, d => n5418,
outb => n3608);
U4496 : oai22 port map( a => n4810, b => n4811, c => n3608, d => n2201, outb
=> n3597);
U4497 : aoi22 port map( a => multiplier_sigs_0_5_port, b =>
adder_mem_array_1_5_port, c => n3597, d => n5419,
outb => n3596);
U4498 : oai22 port map( a => n4812, b => n4813, c => n3596, d => n2203, outb
=> n3593);
U4499 : aoi22 port map( a => multiplier_sigs_0_7_port, b =>
adder_mem_array_1_7_port, c => n3593, d => n5420,
outb => n3592);
U4500 : oai22 port map( a => n4814, b => n4815, c => n3592, d => n2205, outb
=> n3589);
U4501 : aoi22 port map( a => multiplier_sigs_0_9_port, b =>
adder_mem_array_1_9_port, c => n3589, d => n5421,
outb => n3588);
U4502 : oai22 port map( a => n4816, b => n4817, c => n3588, d => n2207, outb
=> n3585);
U4503 : aoi22 port map( a => multiplier_sigs_0_11_port, b =>
adder_mem_array_1_11_port, c => n3585, d => n5422,
outb => n3584);
U4504 : oai22 port map( a => n4818, b => n4819, c => n3584, d => n2209, outb
=> n3581);
U4505 : aoi22 port map( a => multiplier_sigs_0_13_port, b =>
adder_mem_array_1_13_port, c => n3581, d => n5423,
outb => n3580);
U4506 : oai22 port map( a => n4820, b => n4821, c => n3580, d => n2211, outb
=> n3577);
U4507 : aoi22 port map( a => multiplier_sigs_0_15_port, b =>
adder_mem_array_1_15_port, c => n3577, d => n5424,
outb => n3576);
U4508 : oai22 port map( a => n4822, b => n4823, c => n3576, d => n2213, outb
=> n3573);
U4509 : aoi22 port map( a => multiplier_sigs_0_17_port, b =>
adder_mem_array_1_17_port, c => n3573, d => n5425,
outb => n3572);
U4510 : oai22 port map( a => n4824, b => n4825, c => n3572, d => n2215, outb
=> n3569);
U4511 : aoi22 port map( a => multiplier_sigs_0_19_port, b =>
adder_mem_array_1_19_port, c => n3569, d => n5426,
outb => n3568);
U4512 : oai22 port map( a => n4826, b => n4827, c => n3568, d => n2217, outb
=> n3565);
U4513 : aoi22 port map( a => multiplier_sigs_0_21_port, b =>
adder_mem_array_1_21_port, c => n3565, d => n5427,
outb => n3564);
U4514 : oai22 port map( a => n4828, b => n4829, c => n3564, d => n2219, outb
=> n3561);
U4515 : aoi22 port map( a => multiplier_sigs_0_23_port, b =>
adder_mem_array_1_23_port, c => n3561, d => n5428,
outb => n3560);
U4516 : oai22 port map( a => n4830, b => n4831, c => n3560, d => n2221, outb
=> n3557);
U4517 : aoi22 port map( a => multiplier_sigs_0_25_port, b =>
adder_mem_array_1_25_port, c => n3557, d => n5429,
outb => n3556);
U4518 : oai22 port map( a => n4832, b => n4833, c => n3556, d => n2223, outb
=> n3553);
U4519 : aoi22 port map( a => multiplier_sigs_0_27_port, b =>
adder_mem_array_1_27_port, c => n3553, d => n5430,
outb => n3552);
U4520 : oai22 port map( a => n4834, b => n4835, c => n3552, d => n2225, outb
=> n3549);
U4521 : aoi22 port map( a => multiplier_sigs_0_29_port, b =>
adder_mem_array_1_29_port, c => n3549, d => n5431,
outb => n3548);
U4522 : oai22 port map( a => n4836, b => n4837, c => n3548, d => n2227, outb
=> n2230);
U4523 : nand2 port map( a => n5432, b => n5433, outb => n2229);
U4524 : xor2 port map( a => n5373, b => n4894, outb => n3139);
U4525 : xor2 port map( a => n5434, b => n5376, outb => n3142);
U4526 : xor2 port map( a => n5378, b => n4895, outb => n3145);
U4527 : xor2 port map( a => n5435, b => n5379, outb => n3148);
U4528 : xor2 port map( a => n5381, b => n4896, outb => n3151);
U4529 : xor2 port map( a => n5436, b => n5382, outb => n3154);
U4530 : xor2 port map( a => n5384, b => n4897, outb => n3157);
U4531 : xor2 port map( a => n5437, b => n5385, outb => n3160);
U4532 : xor2 port map( a => n5387, b => n4898, outb => n3163);
U4533 : xor2 port map( a => n5438, b => n5388, outb => n3166);
U4534 : xor2 port map( a => n5390, b => n4899, outb => n3169);
U4535 : xor2 port map( a => n5439, b => n5394, outb => n3171);
U4536 : xor2 port map( a => n5393, b => n4900, outb => n280);
U4537 : xor2 port map( a => n5440, b => n3132, outb => n3177);
U4538 : xor2 port map( a => n5441, b => n3135, outb => n3183);
U4539 : xor2 port map( a => n5442, b => n3137, outb => n3186);
U4540 : xor2 port map( a => n5443, b => n3140, outb => n3189);
U4541 : xor2 port map( a => n5444, b => n3143, outb => n3192);
U4542 : xor2 port map( a => n5445, b => n3146, outb => n3195);
U4543 : xor2 port map( a => n5446, b => n3149, outb => n3198);
U4544 : xor2 port map( a => n5447, b => n3152, outb => n3201);
U4545 : xor2 port map( a => n5448, b => n3155, outb => n3204);
U4546 : xor2 port map( a => n5449, b => n3158, outb => n3207);
U4547 : xor2 port map( a => n5450, b => n3161, outb => n3210);
U4548 : xor2 port map( a => n5451, b => n3164, outb => n3212);
U4549 : xor2 port map( a => n5452, b => n3167, outb => n284);
U4550 : xor2 port map( a => n5453, b => n3173, outb => n3218);
U4551 : xor2 port map( a => n5454, b => n3175, outb => n3221);
U4552 : xor2 port map( a => n5455, b => n3179, outb => n3227);
U4553 : xor2 port map( a => n5456, b => n3181, outb => n3230);
U4554 : xor2 port map( a => n5457, b => n3184, outb => n3233);
U4555 : xor2 port map( a => n5458, b => n3187, outb => n3236);
U4556 : xor2 port map( a => n5459, b => n3190, outb => n3239);
U4557 : xor2 port map( a => n5460, b => n3193, outb => n3242);
U4558 : xor2 port map( a => n5461, b => n3196, outb => n3245);
U4559 : xor2 port map( a => n5462, b => n3199, outb => n3248);
U4560 : xor2 port map( a => n5463, b => n3202, outb => n3251);
U4561 : xor2 port map( a => n5464, b => n3205, outb => n3253);
U4562 : xor2 port map( a => n5465, b => n3208, outb => n288);
U4563 : xor2 port map( a => n5466, b => n3214, outb => n3259);
U4564 : xor2 port map( a => n5467, b => n3216, outb => n3262);
U4565 : xor2 port map( a => n5468, b => n3219, outb => n3265);
U4566 : xor2 port map( a => n5469, b => n3223, outb => n3271);
U4567 : xor2 port map( a => n5470, b => n3225, outb => n3274);
U4568 : xor2 port map( a => n5471, b => n3228, outb => n3277);
U4569 : xor2 port map( a => n5472, b => n3231, outb => n3280);
U4570 : xor2 port map( a => n5473, b => n3234, outb => n3283);
U4571 : xor2 port map( a => n5474, b => n3237, outb => n3286);
U4572 : xor2 port map( a => n5475, b => n3240, outb => n3289);
U4573 : xor2 port map( a => n5476, b => n3243, outb => n3292);
U4574 : xor2 port map( a => n5477, b => n3246, outb => n3294);
U4575 : xor2 port map( a => n5478, b => n3249, outb => n292);
U4576 : xor2 port map( a => n5479, b => n3255, outb => n3300);
U4577 : xor2 port map( a => n5480, b => n3257, outb => n3303);
U4578 : xor2 port map( a => n5481, b => n3260, outb => n3306);
U4579 : xor2 port map( a => n5482, b => n3263, outb => n3309);
U4580 : xor2 port map( a => n5483, b => n3267, outb => n3315);
U4581 : xor2 port map( a => n5484, b => n3269, outb => n3318);
U4582 : xor2 port map( a => n5485, b => n3272, outb => n3321);
U4583 : xor2 port map( a => n5486, b => n3275, outb => n3324);
U4584 : xor2 port map( a => n5487, b => n3278, outb => n3327);
U4585 : xor2 port map( a => n5488, b => n3281, outb => n3330);
U4586 : xor2 port map( a => n5489, b => n3284, outb => n3333);
U4587 : xor2 port map( a => n5490, b => n3287, outb => n3335);
U4588 : xor2 port map( a => n5491, b => n3290, outb => n296);
U4589 : xor2 port map( a => n5492, b => n3296, outb => n3341);
U4590 : xor2 port map( a => n5493, b => n3298, outb => n3344);
U4591 : xor2 port map( a => n5494, b => n3301, outb => n3347);
U4592 : xor2 port map( a => n5495, b => n3304, outb => n3350);
U4593 : xor2 port map( a => n5496, b => n3307, outb => n3353);
U4594 : xor2 port map( a => n5497, b => n3311, outb => n3359);
U4595 : xor2 port map( a => n5498, b => n3313, outb => n3362);
U4596 : xor2 port map( a => n5499, b => n3316, outb => n3365);
U4597 : xor2 port map( a => n5500, b => n3319, outb => n3368);
U4598 : xor2 port map( a => n5501, b => n3322, outb => n3371);
U4599 : xor2 port map( a => n5502, b => n3325, outb => n3374);
U4600 : xor2 port map( a => n5503, b => n3328, outb => n3376);
U4601 : xor2 port map( a => n5504, b => n3331, outb => n300);
U4602 : xor2 port map( a => n5505, b => n3337, outb => n3382);
U4603 : xor2 port map( a => n5506, b => n3339, outb => n3385);
U4604 : xor2 port map( a => n5507, b => n3342, outb => n3388);
U4605 : xor2 port map( a => n5508, b => n3345, outb => n3391);
U4606 : xor2 port map( a => n5509, b => n3348, outb => n3394);
U4607 : xor2 port map( a => n5510, b => n3351, outb => n3397);
U4608 : xor2 port map( a => n5511, b => n3355, outb => n3403);
U4609 : xor2 port map( a => n5512, b => n3357, outb => n3406);
U4610 : xor2 port map( a => n5513, b => n3360, outb => n3409);
U4611 : xor2 port map( a => n5514, b => n3363, outb => n3412);
U4612 : xor2 port map( a => n5515, b => n3366, outb => n3415);
U4613 : xor2 port map( a => n5516, b => n3369, outb => n3418);
U4614 : xor2 port map( a => n5517, b => n3372, outb => n305);
U4615 : xor2 port map( a => n5518, b => n3378, outb => n4728);
U4616 : xor2 port map( a => n5519, b => n3380, outb => n4732);
U4617 : xor2 port map( a => n5520, b => n3383, outb => n4736);
U4618 : xor2 port map( a => n5521, b => n3386, outb => n4740);
U4619 : xor2 port map( a => n5522, b => n3389, outb => n4744);
U4620 : xor2 port map( a => n5523, b => n3392, outb => n4748);
U4621 : inv port map( inb => n3416, outb => n5416);
U4622 : xor2 port map( a => n5524, b => n3395, outb => n307);
U4623 : xor2 port map( a => n5525, b => n3416, outb => n311);
U4624 : xor2 port map( a => n4464, b => mult_125_ab_2_14_port, outb => n3133
);
U4625 : xor2 port map( a => n4465, b => n4466, outb => n5434);
U4626 : xor2 port map( a => n4467, b => n4468, outb => n5435);
U4627 : xor2 port map( a => n4469, b => n4470, outb => n5436);
U4628 : xor2 port map( a => n4471, b => n4472, outb => n5437);
U4629 : xor2 port map( a => n4473, b => n4474, outb => n5438);
U4630 : xor2 port map( a => mult_125_ab_13_15_port, b =>
mult_125_ab_14_14_port, outb => n5439);
U4631 : xor2 port map( a => n4475, b => n1713, outb => n3136);
U4632 : xor2 port map( a => mult_125_ab_3_13_port, b => n1717, outb => n5440
);
U4633 : xor2 port map( a => mult_125_ab_4_13_port, b => n1719, outb => n3138
);
U4634 : xor2 port map( a => mult_125_ab_5_13_port, b => n1721, outb => n3141
);
U4635 : xor2 port map( a => mult_125_ab_6_13_port, b => n1723, outb => n3144
);
U4636 : xor2 port map( a => n4482, b => n4480, outb => n3147);
U4637 : xor2 port map( a => mult_125_ab_8_13_port, b => n1727, outb => n3150
);
U4638 : xor2 port map( a => n4485, b => n4483, outb => n3153);
U4639 : xor2 port map( a => mult_125_ab_10_13_port, b => n1731, outb =>
n3156);
U4640 : xor2 port map( a => n4488, b => n4486, outb => n3159);
U4641 : xor2 port map( a => mult_125_ab_12_13_port, b => n1735, outb =>
n3162);
U4642 : xor2 port map( a => n4491, b => n4489, outb => n3165);
U4643 : xor2 port map( a => mult_125_ab_14_13_port, b => n1739, outb =>
n3168);
U4644 : xor2 port map( a => mult_125_ab_15_13_port, b => n4492, outb =>
n3170);
U4645 : xor2 port map( a => n1744, b => mult_125_ab_2_12_port, outb => n3174
);
U4646 : xor2 port map( a => n4496, b => n4494, outb => n5441);
U4647 : xor2 port map( a => mult_125_ab_4_12_port, b => n1748, outb => n3176
);
U4648 : xor2 port map( a => mult_125_ab_5_12_port, b => n4497, outb => n5442
);
U4649 : xor2 port map( a => n4501, b => n4499, outb => n5443);
U4650 : xor2 port map( a => mult_125_ab_7_12_port, b => n1754, outb => n5444
);
U4651 : xor2 port map( a => n4504, b => n4502, outb => n5445);
U4652 : xor2 port map( a => mult_125_ab_9_12_port, b => n1758, outb => n5446
);
U4653 : xor2 port map( a => n4507, b => n4505, outb => n5447);
U4654 : xor2 port map( a => mult_125_ab_11_12_port, b => n1762, outb =>
n5448);
U4655 : xor2 port map( a => n4510, b => n4508, outb => n5449);
U4656 : xor2 port map( a => mult_125_ab_13_12_port, b => n1766, outb =>
n5450);
U4657 : xor2 port map( a => n4513, b => n4511, outb => n5451);
U4658 : xor2 port map( a => n5526, b => n1770, outb => n5452);
U4659 : xor2 port map( a => n1773, b => mult_125_ab_2_11_port, outb => n3180
);
U4660 : xor2 port map( a => mult_125_ab_3_11_port, b => n1776, outb => n5453
);
U4661 : xor2 port map( a => n4517, b => n4516, outb => n3182);
U4662 : xor2 port map( a => mult_125_ab_5_11_port, b => n1780, outb => n5454
);
U4663 : xor2 port map( a => mult_125_ab_6_11_port, b => n1782, outb => n3185
);
U4664 : xor2 port map( a => n4522, b => n4521, outb => n3188);
U4665 : xor2 port map( a => mult_125_ab_8_11_port, b => n1786, outb => n3191
);
U4666 : xor2 port map( a => n4525, b => n4523, outb => n3194);
U4667 : xor2 port map( a => mult_125_ab_10_11_port, b => n1790, outb =>
n3197);
U4668 : xor2 port map( a => n4528, b => n4526, outb => n3200);
U4669 : xor2 port map( a => mult_125_ab_12_11_port, b => n1794, outb =>
n3203);
U4670 : xor2 port map( a => n4531, b => n4529, outb => n3206);
U4671 : xor2 port map( a => mult_125_ab_14_11_port, b => n1798, outb =>
n3209);
U4672 : xor2 port map( a => n1800, b => n1801, outb => n3211);
U4673 : xor2 port map( a => n1804, b => mult_125_ab_2_10_port, outb => n3215
);
U4674 : xor2 port map( a => n4535, b => n4533, outb => n5455);
U4675 : xor2 port map( a => mult_125_ab_4_10_port, b => n1808, outb => n3217
);
U4676 : xor2 port map( a => n1810, b => n1811, outb => n5456);
U4677 : xor2 port map( a => mult_125_ab_6_10_port, b => n1813, outb => n3220
);
U4678 : xor2 port map( a => mult_125_ab_7_10_port, b => n1815, outb => n5457
);
U4679 : xor2 port map( a => n4541, b => n4542, outb => n5458);
U4680 : xor2 port map( a => mult_125_ab_9_10_port, b => n1819, outb => n5459
);
U4681 : xor2 port map( a => n4545, b => n4543, outb => n5460);
U4682 : xor2 port map( a => mult_125_ab_11_10_port, b => n1823, outb =>
n5461);
U4683 : xor2 port map( a => n4548, b => n4546, outb => n5462);
U4684 : xor2 port map( a => mult_125_ab_13_10_port, b => n1827, outb =>
n5463);
U4685 : xor2 port map( a => n4551, b => n4549, outb => n5464);
U4686 : xor2 port map( a => n5527, b => n1831, outb => n5465);
U4687 : xor2 port map( a => n1834, b => mult_125_ab_2_9_port, outb => n3224)
;
U4688 : xor2 port map( a => n4554, b => n4552, outb => n5466);
U4689 : xor2 port map( a => mult_125_ab_4_9_port, b => n1838, outb => n3226)
;
U4690 : xor2 port map( a => mult_125_ab_5_9_port, b => n1840, outb => n5467)
;
U4691 : xor2 port map( a => mult_125_ab_6_9_port, b => n1842, outb => n3229)
;
U4692 : xor2 port map( a => mult_125_ab_7_9_port, b => n1844, outb => n5468)
;
U4693 : xor2 port map( a => n4562, b => n4560, outb => n3232);
U4694 : xor2 port map( a => n4564, b => n4563, outb => n3235);
U4695 : xor2 port map( a => mult_125_ab_10_9_port, b => n1850, outb => n3238
);
U4696 : xor2 port map( a => n4567, b => n4565, outb => n3241);
U4697 : xor2 port map( a => mult_125_ab_12_9_port, b => n1854, outb => n3244
);
U4698 : xor2 port map( a => n4570, b => n4568, outb => n3247);
U4699 : xor2 port map( a => mult_125_ab_14_9_port, b => n1858, outb => n3250
);
U4700 : xor2 port map( a => n1860, b => n1861, outb => n3252);
U4701 : xor2 port map( a => n1864, b => mult_125_ab_2_8_port, outb => n3256)
;
U4702 : xor2 port map( a => n4574, b => n4572, outb => n5469);
U4703 : xor2 port map( a => n4576, b => n1868, outb => n3258);
U4704 : xor2 port map( a => n4578, b => n4577, outb => n5470);
U4705 : xor2 port map( a => mult_125_ab_6_8_port, b => n1872, outb => n3261)
;
U4706 : xor2 port map( a => n4581, b => n4579, outb => n5471);
U4707 : xor2 port map( a => mult_125_ab_8_8_port, b => n1876, outb => n3264)
;
U4708 : xor2 port map( a => mult_125_ab_9_8_port, b => n1878, outb => n5472)
;
U4709 : xor2 port map( a => n4585, b => n4586, outb => n5473);
U4710 : xor2 port map( a => mult_125_ab_11_8_port, b => n1882, outb => n5474
);
U4711 : xor2 port map( a => n4589, b => n4587, outb => n5475);
U4712 : xor2 port map( a => mult_125_ab_13_8_port, b => n1886, outb => n5476
);
U4713 : xor2 port map( a => n4592, b => n4590, outb => n5477);
U4714 : xor2 port map( a => n5528, b => n1890, outb => n5478);
U4715 : xor2 port map( a => n1893, b => mult_125_ab_2_7_port, outb => n3268)
;
U4716 : xor2 port map( a => mult_125_ab_3_7_port, b => n1896, outb => n5479)
;
U4717 : xor2 port map( a => n4596, b => n4595, outb => n3270);
U4718 : xor2 port map( a => mult_125_ab_5_7_port, b => n1900, outb => n5480)
;
U4719 : xor2 port map( a => n4599, b => n4597, outb => n3273);
U4720 : xor2 port map( a => mult_125_ab_7_7_port, b => n1904, outb => n5481)
;
U4721 : xor2 port map( a => n4602, b => n4600, outb => n3276);
U4722 : xor2 port map( a => mult_125_ab_9_7_port, b => n1908, outb => n5482)
;
U4723 : xor2 port map( a => n4605, b => n4603, outb => n3279);
U4724 : xor2 port map( a => n4607, b => n4606, outb => n3282);
U4725 : xor2 port map( a => mult_125_ab_12_7_port, b => n1914, outb => n3285
);
U4726 : xor2 port map( a => n4610, b => n4608, outb => n3288);
U4727 : xor2 port map( a => mult_125_ab_14_7_port, b => n1918, outb => n3291
);
U4728 : xor2 port map( a => n1920, b => n1921, outb => n3293);
U4729 : xor2 port map( a => n1924, b => mult_125_ab_2_6_port, outb => n3297)
;
U4730 : xor2 port map( a => n4614, b => n4612, outb => n5483);
U4731 : xor2 port map( a => mult_125_ab_4_6_port, b => n1928, outb => n3299)
;
U4732 : xor2 port map( a => n1930, b => n1931, outb => n5484);
U4733 : xor2 port map( a => mult_125_ab_6_6_port, b => n1933, outb => n3302)
;
U4734 : xor2 port map( a => n4619, b => n4617, outb => n5485);
U4735 : xor2 port map( a => mult_125_ab_8_6_port, b => n1937, outb => n3305)
;
U4736 : xor2 port map( a => n1939, b => n1940, outb => n5486);
U4737 : xor2 port map( a => mult_125_ab_10_6_port, b => n1942, outb => n3308
);
U4738 : xor2 port map( a => mult_125_ab_11_6_port, b => n1944, outb => n5487
);
U4739 : xor2 port map( a => n4625, b => n4626, outb => n5488);
U4740 : xor2 port map( a => mult_125_ab_13_6_port, b => n1948, outb => n5489
);
U4741 : xor2 port map( a => n4629, b => n4627, outb => n5490);
U4742 : xor2 port map( a => n5529, b => n1952, outb => n5491);
U4743 : xor2 port map( a => n1955, b => mult_125_ab_2_5_port, outb => n3312)
;
U4744 : xor2 port map( a => mult_125_ab_3_5_port, b => n1958, outb => n5492)
;
U4745 : xor2 port map( a => mult_125_ab_4_5_port, b => n1960, outb => n3314)
;
U4746 : xor2 port map( a => mult_125_ab_5_5_port, b => n1962, outb => n5493)
;
U4747 : xor2 port map( a => n1964, b => n1965, outb => n3317);
U4748 : xor2 port map( a => mult_125_ab_7_5_port, b => n1967, outb => n5494)
;
U4749 : xor2 port map( a => mult_125_ab_8_5_port, b => n1969, outb => n3320)
;
U4750 : xor2 port map( a => mult_125_ab_9_5_port, b => n1971, outb => n5495)
;
U4751 : xor2 port map( a => n4641, b => n4639, outb => n3323);
U4752 : xor2 port map( a => mult_125_ab_11_5_port, b => n1975, outb => n5496
);
U4753 : xor2 port map( a => n4644, b => n4642, outb => n3326);
U4754 : xor2 port map( a => n4646, b => n1979, outb => n3329);
U4755 : xor2 port map( a => mult_125_ab_14_5_port, b => n1981, outb => n3332
);
U4756 : xor2 port map( a => n1983, b => n1984, outb => n3334);
U4757 : xor2 port map( a => n1987, b => mult_125_ab_2_4_port, outb => n3338)
;
U4758 : xor2 port map( a => n4650, b => n4648, outb => n5497);
U4759 : xor2 port map( a => mult_125_ab_4_4_port, b => n1991, outb => n3340)
;
U4760 : xor2 port map( a => n1993, b => n1994, outb => n5498);
U4761 : xor2 port map( a => mult_125_ab_6_4_port, b => n1996, outb => n3343)
;
U4762 : xor2 port map( a => n1998, b => n1999, outb => n5499);
U4763 : xor2 port map( a => mult_125_ab_8_4_port, b => n2001, outb => n3346)
;
U4764 : xor2 port map( a => mult_125_ab_9_4_port, b => n2003, outb => n5500)
;
U4765 : xor2 port map( a => mult_125_ab_10_4_port, b => n2005, outb => n3349
);
U4766 : xor2 port map( a => n2007, b => n2008, outb => n5501);
U4767 : xor2 port map( a => mult_125_ab_12_4_port, b => n2010, outb => n3352
);
U4768 : xor2 port map( a => mult_125_ab_13_4_port, b => n2012, outb => n5502
);
U4769 : xor2 port map( a => mult_125_ab_14_4_port, b => n2014, outb => n5503
);
U4770 : xor2 port map( a => mult_125_ab_15_4_port, b => n2017, outb => n5504
);
U4771 : xor2 port map( a => n2020, b => mult_125_ab_2_3_port, outb => n3356)
;
U4772 : xor2 port map( a => mult_125_ab_3_3_port, b => n2023, outb => n5505)
;
U4773 : xor2 port map( a => mult_125_ab_4_3_port, b => n2025, outb => n3358)
;
U4774 : xor2 port map( a => mult_125_ab_5_3_port, b => n2027, outb => n5506)
;
U4775 : xor2 port map( a => mult_125_ab_6_3_port, b => n2029, outb => n3361)
;
U4776 : xor2 port map( a => mult_125_ab_7_3_port, b => n2031, outb => n5507)
;
U4777 : xor2 port map( a => mult_125_ab_8_3_port, b => n2033, outb => n3364)
;
U4778 : xor2 port map( a => mult_125_ab_9_3_port, b => n2035, outb => n5508)
;
U4779 : xor2 port map( a => mult_125_ab_10_3_port, b => n2037, outb => n3367
);
U4780 : xor2 port map( a => mult_125_ab_11_3_port, b => n2039, outb => n5509
);
U4781 : xor2 port map( a => n4679, b => n4677, outb => n3370);
U4782 : xor2 port map( a => mult_125_ab_13_3_port, b => n2043, outb => n5510
);
U4783 : xor2 port map( a => mult_125_ab_14_3_port, b => n2045, outb => n3373
);
U4784 : xor2 port map( a => mult_125_ab_15_3_port, b => n2047, outb => n3375
);
U4785 : xor2 port map( a => n2050, b => mult_125_ab_2_2_port, outb => n3379)
;
U4786 : xor2 port map( a => n4685, b => n4683, outb => n5511);
U4787 : xor2 port map( a => mult_125_ab_4_2_port, b => n2054, outb => n3381)
;
U4788 : xor2 port map( a => mult_125_ab_5_2_port, b => n2056, outb => n5512)
;
U4789 : xor2 port map( a => mult_125_ab_6_2_port, b => n2058, outb => n3384)
;
U4790 : xor2 port map( a => n2060, b => n2061, outb => n5513);
U4791 : xor2 port map( a => mult_125_ab_8_2_port, b => n2063, outb => n3387)
;
U4792 : xor2 port map( a => mult_125_ab_9_2_port, b => n2065, outb => n5514)
;
U4793 : xor2 port map( a => mult_125_ab_10_2_port, b => n2067, outb => n3390
);
U4794 : xor2 port map( a => mult_125_ab_11_2_port, b => n2069, outb => n5515
);
U4795 : xor2 port map( a => mult_125_ab_12_2_port, b => n2071, outb => n3393
);
U4796 : xor2 port map( a => mult_125_ab_13_2_port, b => n2073, outb => n5516
);
U4797 : xor2 port map( a => mult_125_ab_14_2_port, b => n2075, outb => n3396
);
U4798 : xor2 port map( a => n5413, b => n4700, outb => n5517);
U4799 : xor2 port map( a => n4703, b => mult_125_ab_2_1_port, outb => n3400)
;
U4800 : xor2 port map( a => n4704, b => n4702, outb => n5518);
U4801 : xor2 port map( a => mult_125_ab_4_1_port, b => n4706, outb => n3402)
;
U4802 : xor2 port map( a => mult_125_ab_5_1_port, b => n2086, outb => n5530)
;
U4803 : xor2 port map( a => n4709, b => n2088, outb => n3405);
U4804 : xor2 port map( a => n5531, b => n2090, outb => n5520);
U4805 : xor2 port map( a => mult_125_ab_8_1_port, b => n4710, outb => n3408)
;
U4806 : xor2 port map( a => n5532, b => n2094, outb => n5521);
U4807 : xor2 port map( a => n4715, b => n2096, outb => n3411);
U4808 : xor2 port map( a => n5533, b => n2098, outb => n5522);
U4809 : xor2 port map( a => n4718, b => n2100, outb => n3414);
U4810 : xor2 port map( a => n5534, b => n2102, outb => n5523);
U4811 : xor2 port map( a => n4721, b => n4719, outb => n3417);
U4812 : xor2 port map( a => n5535, b => n2106, outb => n5524);
U4813 : xor2 port map( a => mult_125_ab_15_0_port, b => n2134, outb => n5525
);
U4814 : xor2 port map( a => mult_125_ab_11_0_port, b => n2126, outb => n3419
);
U4815 : xor2 port map( a => mult_125_ab_9_0_port, b => n2122, outb => n3420)
;
U4816 : xor2 port map( a => mult_125_ab_7_0_port, b => n2118, outb => n3421)
;
U4817 : xor2 port map( a => mult_125_ab_5_0_port, b => n2114, outb => n3422)
;
U4818 : xor2 port map( a => mult_125_ab_3_0_port, b => n2110, outb => n3423)
;
U4819 : xor2 port map( a => n308, b => mult_125_ZA, outb => n3424);
U4820 : xor2 port map( a => mult_125_ab_13_0_port, b => n2130, outb => n3425
);
U4821 : xor2 port map( a => n4777, b => adder_mem_array_1_2_port, outb =>
n3470);
U4822 : xor2 port map( a => n5433, b => adder_mem_array_1_32_port, outb =>
n3545);
U4823 : xor2 port map( a => n4836, b => adder_mem_array_1_30_port, outb =>
n3547);
U4824 : xor2 port map( a => n4834, b => adder_mem_array_1_28_port, outb =>
n3551);
U4825 : xor2 port map( a => n4832, b => adder_mem_array_1_26_port, outb =>
n3555);
U4826 : xor2 port map( a => n4830, b => adder_mem_array_1_24_port, outb =>
n3559);
U4827 : xor2 port map( a => n4828, b => adder_mem_array_1_22_port, outb =>
n3563);
U4828 : xor2 port map( a => n4826, b => adder_mem_array_1_20_port, outb =>
n3567);
U4829 : xor2 port map( a => n4824, b => adder_mem_array_1_18_port, outb =>
n3571);
U4830 : xor2 port map( a => n4822, b => adder_mem_array_1_16_port, outb =>
n3575);
U4831 : xor2 port map( a => n4820, b => adder_mem_array_1_14_port, outb =>
n3579);
U4832 : xor2 port map( a => n4818, b => adder_mem_array_1_12_port, outb =>
n3583);
U4833 : xor2 port map( a => n4816, b => adder_mem_array_1_10_port, outb =>
n3587);
U4834 : xor2 port map( a => n4814, b => adder_mem_array_1_8_port, outb =>
n3591);
U4835 : xor2 port map( a => n4812, b => adder_mem_array_1_6_port, outb =>
n3595);
U4836 : xor2 port map( a => n4810, b => adder_mem_array_1_4_port, outb =>
n3607);
U4837 : inv port map( inb => n385, outb => n4905);
U4838 : inv port map( inb => n387, outb => n4908);
U4839 : inv port map( inb => n389, outb => n4911);
U4840 : inv port map( inb => n391, outb => n4914);
U4841 : inv port map( inb => n393, outb => n4917);
U4842 : inv port map( inb => n395, outb => n4920);
U4843 : inv port map( inb => n397, outb => n4925);
U4844 : inv port map( inb => n430, outb => n3640);
U4845 : inv port map( inb => n459, outb => n3659);
U4846 : inv port map( inb => n490, outb => n3679);
U4847 : inv port map( inb => n520, outb => n3698);
U4848 : inv port map( inb => n550, outb => n3718);
U4849 : inv port map( inb => n579, outb => n3738);
U4850 : inv port map( inb => n610, outb => n3758);
U4851 : inv port map( inb => n641, outb => n3775);
U4852 : inv port map( inb => n673, outb => n3794);
U4853 : inv port map( inb => n706, outb => n3809);
U4854 : inv port map( inb => n736, outb => n3829);
U4855 : inv port map( inb => n766, outb => n3848);
U4856 : inv port map( inb => n3867, outb => n794);
U4857 : inv port map( inb => n3868, outb => n796);
U4858 : inv port map( inb => n819, outb => n4943);
U4859 : inv port map( inb => n823, outb => n5051);
U4860 : inv port map( inb => n825, outb => n5054);
U4861 : inv port map( inb => n827, outb => n5057);
U4862 : inv port map( inb => n829, outb => n5060);
U4863 : inv port map( inb => n831, outb => n5063);
U4864 : inv port map( inb => n833, outb => n5066);
U4865 : inv port map( inb => n835, outb => n5071);
U4866 : inv port map( inb => n868, outb => n3925);
U4867 : inv port map( inb => n897, outb => n3944);
U4868 : inv port map( inb => n928, outb => n3964);
U4869 : inv port map( inb => n958, outb => n3983);
U4870 : inv port map( inb => n988, outb => n4003);
U4871 : inv port map( inb => n1017, outb => n4023);
U4872 : inv port map( inb => n1048, outb => n4043);
U4873 : inv port map( inb => n1079, outb => n4060);
U4874 : inv port map( inb => n1111, outb => n4079);
U4875 : inv port map( inb => n1144, outb => n4094);
U4876 : inv port map( inb => n1174, outb => n4114);
U4877 : inv port map( inb => n1204, outb => n4133);
U4878 : inv port map( inb => n4152, outb => n1232);
U4879 : inv port map( inb => n4153, outb => n1234);
U4880 : inv port map( inb => n1257, outb => n5089);
U4881 : inv port map( inb => n1261, outb => n5214);
U4882 : inv port map( inb => n1263, outb => n5217);
U4883 : inv port map( inb => n1265, outb => n5220);
U4884 : inv port map( inb => n1267, outb => n5223);
U4885 : inv port map( inb => n1269, outb => n5226);
U4886 : inv port map( inb => n1271, outb => n5229);
U4887 : inv port map( inb => n1273, outb => n5234);
U4888 : inv port map( inb => n1306, outb => n4210);
U4889 : inv port map( inb => n1335, outb => n4229);
U4890 : inv port map( inb => n1366, outb => n4249);
U4891 : inv port map( inb => n1396, outb => n4268);
U4892 : inv port map( inb => n1426, outb => n4288);
U4893 : inv port map( inb => n1455, outb => n4308);
U4894 : inv port map( inb => n1486, outb => n4328);
U4895 : inv port map( inb => n1517, outb => n4345);
U4896 : inv port map( inb => n1549, outb => n4364);
U4897 : inv port map( inb => n1582, outb => n4379);
U4898 : inv port map( inb => n1612, outb => n4399);
U4899 : inv port map( inb => n1642, outb => n4418);
U4900 : inv port map( inb => n4437, outb => n1670);
U4901 : inv port map( inb => n4438, outb => n1672);
U4902 : inv port map( inb => n1695, outb => n5252);
U4903 : inv port map( inb => n1699, outb => n5377);
U4904 : inv port map( inb => n1701, outb => n5380);
U4905 : inv port map( inb => n1703, outb => n5383);
U4906 : inv port map( inb => n1705, outb => n5386);
U4907 : inv port map( inb => n1707, outb => n5389);
U4908 : inv port map( inb => n1709, outb => n5392);
U4909 : inv port map( inb => n1711, outb => n5397);
U4910 : inv port map( inb => n1744, outb => n4495);
U4911 : inv port map( inb => n1773, outb => n4514);
U4912 : inv port map( inb => n1804, outb => n4534);
U4913 : inv port map( inb => n1834, outb => n4553);
U4914 : inv port map( inb => n1864, outb => n4573);
U4915 : inv port map( inb => n1893, outb => n4593);
U4916 : inv port map( inb => n1924, outb => n4613);
U4917 : inv port map( inb => n1955, outb => n4630);
U4918 : inv port map( inb => n1987, outb => n4649);
U4919 : inv port map( inb => n2020, outb => n4664);
U4920 : inv port map( inb => n2050, outb => n4684);
U4921 : inv port map( inb => n2080, outb => n4703);
U4922 : inv port map( inb => n4722, outb => n2108);
U4923 : inv port map( inb => n4723, outb => n2110);
U4924 : inv port map( inb => n2133, outb => n5415);
U4925 : inv port map( inb => n4749, outb => n2137);
U4926 : inv port map( inb => n2139, outb => n5092);
U4927 : inv port map( inb => n2141, outb => n5093);
U4928 : inv port map( inb => n2143, outb => n5094);
U4929 : inv port map( inb => n2145, outb => n5095);
U4930 : inv port map( inb => n2147, outb => n5096);
U4931 : inv port map( inb => n2149, outb => n5097);
U4932 : inv port map( inb => n2151, outb => n5098);
U4933 : inv port map( inb => n2153, outb => n5099);
U4934 : inv port map( inb => n2155, outb => n5100);
U4935 : inv port map( inb => n2157, outb => n5101);
U4936 : inv port map( inb => n2159, outb => n5102);
U4937 : inv port map( inb => n2161, outb => n5103);
U4938 : inv port map( inb => n4776, outb => n2164);
U4939 : inv port map( inb => n4779, outb => n2167);
U4940 : inv port map( inb => n2169, outb => n5255);
U4941 : inv port map( inb => n2171, outb => n5256);
U4942 : inv port map( inb => n2173, outb => n5257);
U4943 : inv port map( inb => n2175, outb => n5258);
U4944 : inv port map( inb => n2177, outb => n5259);
U4945 : inv port map( inb => n2179, outb => n5260);
U4946 : inv port map( inb => n2181, outb => n5261);
U4947 : inv port map( inb => n2183, outb => n5262);
U4948 : inv port map( inb => n2185, outb => n5263);
U4949 : inv port map( inb => n2187, outb => n5264);
U4950 : inv port map( inb => n2189, outb => n5265);
U4951 : inv port map( inb => n2191, outb => n5266);
U4952 : inv port map( inb => n2193, outb => n5267);
U4953 : inv port map( inb => n2195, outb => n5268);
U4954 : inv port map( inb => n2200, outb => n5418);
U4955 : inv port map( inb => n2202, outb => n5419);
U4956 : inv port map( inb => n2204, outb => n5420);
U4957 : inv port map( inb => n2206, outb => n5421);
U4958 : inv port map( inb => n2208, outb => n5422);
U4959 : inv port map( inb => n2210, outb => n5423);
U4960 : inv port map( inb => n2212, outb => n5424);
U4961 : inv port map( inb => n2214, outb => n5425);
U4962 : inv port map( inb => n2216, outb => n5426);
U4963 : inv port map( inb => n2218, outb => n5427);
U4964 : inv port map( inb => n2220, outb => n5428);
U4965 : inv port map( inb => n2222, outb => n5429);
U4966 : inv port map( inb => n2224, outb => n5430);
U4967 : inv port map( inb => n2226, outb => n5431);
U4968 : inv port map( inb => n2231, outb => n5104);
U4969 : inv port map( inb => n2233, outb => n5105);
U4970 : inv port map( inb => mult_125_G4_ab_1_15_port, outb => n4902);
U4971 : inv port map( inb => mult_125_G4_ab_2_14_port, outb => n4903);
U4972 : inv port map( inb => n408, outb => n3626);
U4973 : inv port map( inb => n412, outb => n3629);
U4974 : inv port map( inb => n416, outb => n3632);
U4975 : inv port map( inb => n420, outb => n3635);
U4976 : inv port map( inb => n424, outb => n3638);
U4977 : inv port map( inb => mult_125_G4_ab_3_12_port, outb => n3641);
U4978 : inv port map( inb => n439, outb => n3648);
U4979 : inv port map( inb => n443, outb => n3651);
U4980 : inv port map( inb => n447, outb => n3654);
U4981 : inv port map( inb => n451, outb => n3657);
U4982 : inv port map( inb => mult_125_G4_ab_3_11_port, outb => n461);
U4983 : inv port map( inb => n471, outb => n3669);
U4984 : inv port map( inb => n475, outb => n3672);
U4985 : inv port map( inb => n479, outb => n3675);
U4986 : inv port map( inb => n483, outb => n3677);
U4987 : inv port map( inb => mult_125_G4_ab_3_10_port, outb => n3680);
U4988 : inv port map( inb => n504, outb => n3689);
U4989 : inv port map( inb => n508, outb => n3692);
U4990 : inv port map( inb => n512, outb => n3695);
U4991 : inv port map( inb => mult_125_G4_ab_3_9_port, outb => n3699);
U4992 : inv port map( inb => n535, outb => n3711);
U4993 : inv port map( inb => n539, outb => n3714);
U4994 : inv port map( inb => n543, outb => n3716);
U4995 : inv port map( inb => mult_125_G4_ab_3_8_port, outb => n3719);
U4996 : inv port map( inb => n567, outb => n3733);
U4997 : inv port map( inb => n571, outb => n3736);
U4998 : inv port map( inb => mult_125_G4_ab_3_7_port, outb => n581);
U4999 : inv port map( inb => n599, outb => n3754);
U5000 : inv port map( inb => n603, outb => n3756);
U5001 : inv port map( inb => mult_125_G4_ab_3_6_port, outb => n3759);
U5002 : inv port map( inb => n633, outb => n3773);
U5003 : inv port map( inb => mult_125_G4_ab_3_5_port, outb => n643);
U5004 : inv port map( inb => n666, outb => n3792);
U5005 : inv port map( inb => mult_125_G4_ab_3_4_port, outb => n3795);
U5006 : inv port map( inb => mult_125_G4_ab_3_3_port, outb => n708);
U5007 : inv port map( inb => mult_125_G4_ab_3_2_port, outb => n3830);
U5008 : inv port map( inb => mult_125_G4_ab_3_1_port, outb => n3849);
U5009 : inv port map( inb => n770, outb => n3851);
U5010 : inv port map( inb => n799, outb => n3875);
U5011 : inv port map( inb => n803, outb => n3879);
U5012 : inv port map( inb => n807, outb => n3883);
U5013 : inv port map( inb => n811, outb => n3887);
U5014 : inv port map( inb => n815, outb => n3891);
U5015 : inv port map( inb => mult_125_G3_ab_1_15_port, outb => n5048);
U5016 : inv port map( inb => mult_125_G3_ab_2_14_port, outb => n5049);
U5017 : inv port map( inb => n846, outb => n3911);
U5018 : inv port map( inb => n850, outb => n3914);
U5019 : inv port map( inb => n854, outb => n3917);
U5020 : inv port map( inb => n858, outb => n3920);
U5021 : inv port map( inb => n862, outb => n3923);
U5022 : inv port map( inb => mult_125_G3_ab_3_12_port, outb => n3926);
U5023 : inv port map( inb => n877, outb => n3933);
U5024 : inv port map( inb => n881, outb => n3936);
U5025 : inv port map( inb => n885, outb => n3939);
U5026 : inv port map( inb => n889, outb => n3942);
U5027 : inv port map( inb => mult_125_G3_ab_3_11_port, outb => n899);
U5028 : inv port map( inb => n909, outb => n3954);
U5029 : inv port map( inb => n913, outb => n3957);
U5030 : inv port map( inb => n917, outb => n3960);
U5031 : inv port map( inb => n921, outb => n3962);
U5032 : inv port map( inb => mult_125_G3_ab_3_10_port, outb => n3965);
U5033 : inv port map( inb => n942, outb => n3974);
U5034 : inv port map( inb => n946, outb => n3977);
U5035 : inv port map( inb => n950, outb => n3980);
U5036 : inv port map( inb => mult_125_G3_ab_3_9_port, outb => n3984);
U5037 : inv port map( inb => n973, outb => n3996);
U5038 : inv port map( inb => n977, outb => n3999);
U5039 : inv port map( inb => n981, outb => n4001);
U5040 : inv port map( inb => mult_125_G3_ab_3_8_port, outb => n4004);
U5041 : inv port map( inb => n1005, outb => n4018);
U5042 : inv port map( inb => n1009, outb => n4021);
U5043 : inv port map( inb => mult_125_G3_ab_3_7_port, outb => n1019);
U5044 : inv port map( inb => n1037, outb => n4039);
U5045 : inv port map( inb => n1041, outb => n4041);
U5046 : inv port map( inb => mult_125_G3_ab_3_6_port, outb => n4044);
U5047 : inv port map( inb => n1071, outb => n4058);
U5048 : inv port map( inb => mult_125_G3_ab_3_5_port, outb => n1081);
U5049 : inv port map( inb => n1104, outb => n4077);
U5050 : inv port map( inb => mult_125_G3_ab_3_4_port, outb => n4080);
U5051 : inv port map( inb => mult_125_G3_ab_3_3_port, outb => n1146);
U5052 : inv port map( inb => mult_125_G3_ab_3_2_port, outb => n4115);
U5053 : inv port map( inb => mult_125_G3_ab_3_1_port, outb => n4134);
U5054 : inv port map( inb => n1208, outb => n4136);
U5055 : inv port map( inb => n1237, outb => n4160);
U5056 : inv port map( inb => n1241, outb => n4164);
U5057 : inv port map( inb => n1245, outb => n4168);
U5058 : inv port map( inb => n1249, outb => n4172);
U5059 : inv port map( inb => n1253, outb => n4176);
U5060 : inv port map( inb => mult_125_G2_ab_1_15_port, outb => n5211);
U5061 : inv port map( inb => mult_125_G2_ab_2_14_port, outb => n5212);
U5062 : inv port map( inb => n1284, outb => n4196);
U5063 : inv port map( inb => n1288, outb => n4199);
U5064 : inv port map( inb => n1292, outb => n4202);
U5065 : inv port map( inb => n1296, outb => n4205);
U5066 : inv port map( inb => n1300, outb => n4208);
U5067 : inv port map( inb => mult_125_G2_ab_3_12_port, outb => n4211);
U5068 : inv port map( inb => n1315, outb => n4218);
U5069 : inv port map( inb => n1319, outb => n4221);
U5070 : inv port map( inb => n1323, outb => n4224);
U5071 : inv port map( inb => n1327, outb => n4227);
U5072 : inv port map( inb => mult_125_G2_ab_3_11_port, outb => n1337);
U5073 : inv port map( inb => n1347, outb => n4239);
U5074 : inv port map( inb => n1351, outb => n4242);
U5075 : inv port map( inb => n1355, outb => n4245);
U5076 : inv port map( inb => n1359, outb => n4247);
U5077 : inv port map( inb => mult_125_G2_ab_3_10_port, outb => n4250);
U5078 : inv port map( inb => n1380, outb => n4259);
U5079 : inv port map( inb => n1384, outb => n4262);
U5080 : inv port map( inb => n1388, outb => n4265);
U5081 : inv port map( inb => mult_125_G2_ab_3_9_port, outb => n4269);
U5082 : inv port map( inb => n1411, outb => n4281);
U5083 : inv port map( inb => n1415, outb => n4284);
U5084 : inv port map( inb => n1419, outb => n4286);
U5085 : inv port map( inb => mult_125_G2_ab_3_8_port, outb => n4289);
U5086 : inv port map( inb => n1443, outb => n4303);
U5087 : inv port map( inb => n1447, outb => n4306);
U5088 : inv port map( inb => mult_125_G2_ab_3_7_port, outb => n1457);
U5089 : inv port map( inb => n1475, outb => n4324);
U5090 : inv port map( inb => n1479, outb => n4326);
U5091 : inv port map( inb => mult_125_G2_ab_3_6_port, outb => n4329);
U5092 : inv port map( inb => n1509, outb => n4343);
U5093 : inv port map( inb => mult_125_G2_ab_3_5_port, outb => n1519);
U5094 : inv port map( inb => n1542, outb => n4362);
U5095 : inv port map( inb => mult_125_G2_ab_3_4_port, outb => n4365);
U5096 : inv port map( inb => mult_125_G2_ab_3_3_port, outb => n1584);
U5097 : inv port map( inb => mult_125_G2_ab_3_2_port, outb => n4400);
U5098 : inv port map( inb => mult_125_G2_ab_3_1_port, outb => n4419);
U5099 : inv port map( inb => n1646, outb => n4421);
U5100 : inv port map( inb => n1675, outb => n4445);
U5101 : inv port map( inb => n1679, outb => n4449);
U5102 : inv port map( inb => n1683, outb => n4453);
U5103 : inv port map( inb => n1687, outb => n4457);
U5104 : inv port map( inb => n1691, outb => n4461);
U5105 : inv port map( inb => mult_125_ab_1_15_port, outb => n5374);
U5106 : inv port map( inb => mult_125_ab_2_14_port, outb => n5375);
U5107 : inv port map( inb => n1722, outb => n4481);
U5108 : inv port map( inb => n1726, outb => n4484);
U5109 : inv port map( inb => n1730, outb => n4487);
U5110 : inv port map( inb => n1734, outb => n4490);
U5111 : inv port map( inb => n1738, outb => n4493);
U5112 : inv port map( inb => mult_125_ab_3_12_port, outb => n4496);
U5113 : inv port map( inb => n1753, outb => n4503);
U5114 : inv port map( inb => n1757, outb => n4506);
U5115 : inv port map( inb => n1761, outb => n4509);
U5116 : inv port map( inb => n1765, outb => n4512);
U5117 : inv port map( inb => mult_125_ab_3_11_port, outb => n1775);
U5118 : inv port map( inb => n1785, outb => n4524);
U5119 : inv port map( inb => n1789, outb => n4527);
U5120 : inv port map( inb => n1793, outb => n4530);
U5121 : inv port map( inb => n1797, outb => n4532);
U5122 : inv port map( inb => mult_125_ab_3_10_port, outb => n4535);
U5123 : inv port map( inb => n1818, outb => n4544);
U5124 : inv port map( inb => n1822, outb => n4547);
U5125 : inv port map( inb => n1826, outb => n4550);
U5126 : inv port map( inb => mult_125_ab_3_9_port, outb => n4554);
U5127 : inv port map( inb => n1849, outb => n4566);
U5128 : inv port map( inb => n1853, outb => n4569);
U5129 : inv port map( inb => n1857, outb => n4571);
U5130 : inv port map( inb => mult_125_ab_3_8_port, outb => n4574);
U5131 : inv port map( inb => n1881, outb => n4588);
U5132 : inv port map( inb => n1885, outb => n4591);
U5133 : inv port map( inb => mult_125_ab_3_7_port, outb => n1895);
U5134 : inv port map( inb => n1913, outb => n4609);
U5135 : inv port map( inb => n1917, outb => n4611);
U5136 : inv port map( inb => mult_125_ab_3_6_port, outb => n4614);
U5137 : inv port map( inb => n1947, outb => n4628);
U5138 : inv port map( inb => mult_125_ab_3_5_port, outb => n1957);
U5139 : inv port map( inb => n1980, outb => n4647);
U5140 : inv port map( inb => mult_125_ab_3_4_port, outb => n4650);
U5141 : inv port map( inb => mult_125_ab_3_3_port, outb => n2022);
U5142 : inv port map( inb => mult_125_ab_3_2_port, outb => n4685);
U5143 : inv port map( inb => mult_125_ab_3_1_port, outb => n4704);
U5144 : inv port map( inb => n2084, outb => n4706);
U5145 : inv port map( inb => n2113, outb => n4730);
U5146 : inv port map( inb => n2117, outb => n4734);
U5147 : inv port map( inb => n2121, outb => n4738);
U5148 : inv port map( inb => n2125, outb => n4742);
U5149 : inv port map( inb => n2129, outb => n4746);
U5150 : inv port map( inb => mult_125_G4_ab_5_13_port, outb => n3624);
U5151 : inv port map( inb => n4921, outb => n4924);
U5152 : inv port map( inb => mult_125_G4_ab_7_11_port, outb => n3667);
U5153 : inv port map( inb => mult_125_G4_ab_5_10_port, outb => n496);
U5154 : inv port map( inb => mult_125_G4_ab_7_10_port, outb => n3685);
U5155 : inv port map( inb => mult_125_G4_ab_9_9_port, outb => n3709);
U5156 : inv port map( inb => mult_125_G4_ab_7_8_port, outb => n3726);
U5157 : inv port map( inb => mult_125_G4_ab_9_8_port, outb => n3729);
U5158 : inv port map( inb => mult_125_G4_ab_11_7_port, outb => n3752);
U5159 : inv port map( inb => mult_125_G4_ab_9_6_port, outb => n625);
U5160 : inv port map( inb => mult_125_G4_ab_11_6_port, outb => n3769);
U5161 : inv port map( inb => mult_125_G4_ab_13_5_port, outb => n3791);
U5162 : inv port map( inb => mult_125_G4_ab_11_4_port, outb => n693);
U5163 : inv port map( inb => mult_125_G4_ab_13_4_port, outb => n3807);
U5164 : inv port map( inb => mult_125_G3_ab_5_13_port, outb => n3909);
U5165 : inv port map( inb => n5067, outb => n5070);
U5166 : inv port map( inb => mult_125_G3_ab_7_11_port, outb => n3952);
U5167 : inv port map( inb => mult_125_G3_ab_5_10_port, outb => n934);
U5168 : inv port map( inb => mult_125_G3_ab_7_10_port, outb => n3970);
U5169 : inv port map( inb => mult_125_G3_ab_9_9_port, outb => n3994);
U5170 : inv port map( inb => mult_125_G3_ab_7_8_port, outb => n4011);
U5171 : inv port map( inb => mult_125_G3_ab_9_8_port, outb => n4014);
U5172 : inv port map( inb => mult_125_G3_ab_11_7_port, outb => n4037);
U5173 : inv port map( inb => mult_125_G3_ab_9_6_port, outb => n1063);
U5174 : inv port map( inb => mult_125_G3_ab_11_6_port, outb => n4054);
U5175 : inv port map( inb => mult_125_G3_ab_13_5_port, outb => n4076);
U5176 : inv port map( inb => mult_125_G3_ab_11_4_port, outb => n1131);
U5177 : inv port map( inb => mult_125_G3_ab_13_4_port, outb => n4092);
U5178 : inv port map( inb => mult_125_G2_ab_5_13_port, outb => n4194);
U5179 : inv port map( inb => n5230, outb => n5233);
U5180 : inv port map( inb => mult_125_G2_ab_7_11_port, outb => n4237);
U5181 : inv port map( inb => mult_125_G2_ab_5_10_port, outb => n1372);
U5182 : inv port map( inb => mult_125_G2_ab_7_10_port, outb => n4255);
U5183 : inv port map( inb => mult_125_G2_ab_9_9_port, outb => n4279);
U5184 : inv port map( inb => mult_125_G2_ab_7_8_port, outb => n4296);
U5185 : inv port map( inb => mult_125_G2_ab_9_8_port, outb => n4299);
U5186 : inv port map( inb => mult_125_G2_ab_11_7_port, outb => n4322);
U5187 : inv port map( inb => mult_125_G2_ab_9_6_port, outb => n1501);
U5188 : inv port map( inb => mult_125_G2_ab_11_6_port, outb => n4339);
U5189 : inv port map( inb => mult_125_G2_ab_13_5_port, outb => n4361);
U5190 : inv port map( inb => mult_125_G2_ab_11_4_port, outb => n1569);
U5191 : inv port map( inb => mult_125_G2_ab_13_4_port, outb => n4377);
U5192 : inv port map( inb => mult_125_ab_5_13_port, outb => n4479);
U5193 : inv port map( inb => n5393, outb => n5396);
U5194 : inv port map( inb => mult_125_ab_7_11_port, outb => n4522);
U5195 : inv port map( inb => mult_125_ab_5_10_port, outb => n1810);
U5196 : inv port map( inb => mult_125_ab_7_10_port, outb => n4540);
U5197 : inv port map( inb => mult_125_ab_9_9_port, outb => n4564);
U5198 : inv port map( inb => mult_125_ab_7_8_port, outb => n4581);
U5199 : inv port map( inb => mult_125_ab_9_8_port, outb => n4584);
U5200 : inv port map( inb => mult_125_ab_11_7_port, outb => n4607);
U5201 : inv port map( inb => mult_125_ab_9_6_port, outb => n1939);
U5202 : inv port map( inb => mult_125_ab_11_6_port, outb => n4624);
U5203 : inv port map( inb => mult_125_ab_13_5_port, outb => n4646);
U5204 : inv port map( inb => mult_125_ab_11_4_port, outb => n2007);
U5205 : inv port map( inb => mult_125_ab_13_4_port, outb => n4662);
U5206 : inv port map( inb => n4919, outb => n4922);
U5207 : inv port map( inb => n396, outb => n4923);
U5208 : inv port map( inb => n498, outb => n3684);
U5209 : inv port map( inb => n561, outb => n3728);
U5210 : inv port map( inb => n627, outb => n3768);
U5211 : inv port map( inb => n695, outb => n3806);
U5212 : inv port map( inb => n5065, outb => n5068);
U5213 : inv port map( inb => n834, outb => n5069);
U5214 : inv port map( inb => n936, outb => n3969);
U5215 : inv port map( inb => n999, outb => n4013);
U5216 : inv port map( inb => n1065, outb => n4053);
U5217 : inv port map( inb => n1133, outb => n4091);
U5218 : inv port map( inb => n5228, outb => n5231);
U5219 : inv port map( inb => n1272, outb => n5232);
U5220 : inv port map( inb => n1374, outb => n4254);
U5221 : inv port map( inb => n1437, outb => n4298);
U5222 : inv port map( inb => n1503, outb => n4338);
U5223 : inv port map( inb => n1571, outb => n4376);
U5224 : inv port map( inb => n5391, outb => n5394);
U5225 : inv port map( inb => n1710, outb => n5395);
U5226 : inv port map( inb => n1812, outb => n4539);
U5227 : inv port map( inb => n1875, outb => n4583);
U5228 : inv port map( inb => n1941, outb => n4623);
U5229 : inv port map( inb => n2009, outb => n4661);
U5230 : inv port map( inb => n400, outb => n3620);
U5231 : inv port map( inb => n433, outb => n3643);
U5232 : inv port map( inb => n470, outb => n3666);
U5233 : inv port map( inb => n534, outb => n3708);
U5234 : inv port map( inb => n598, outb => n3751);
U5235 : inv port map( inb => n665, outb => n3790);
U5236 : inv port map( inb => n703, outb => n4939);
U5237 : inv port map( inb => n838, outb => n3905);
U5238 : inv port map( inb => n871, outb => n3928);
U5239 : inv port map( inb => n908, outb => n3951);
U5240 : inv port map( inb => n972, outb => n3993);
U5241 : inv port map( inb => n1036, outb => n4036);
U5242 : inv port map( inb => n1103, outb => n4075);
U5243 : inv port map( inb => n1141, outb => n5085);
U5244 : inv port map( inb => n1276, outb => n4190);
U5245 : inv port map( inb => n1309, outb => n4213);
U5246 : inv port map( inb => n1346, outb => n4236);
U5247 : inv port map( inb => n1410, outb => n4278);
U5248 : inv port map( inb => n1474, outb => n4321);
U5249 : inv port map( inb => n1541, outb => n4360);
U5250 : inv port map( inb => n1579, outb => n5248);
U5251 : inv port map( inb => n1714, outb => n4475);
U5252 : inv port map( inb => n1747, outb => n4498);
U5253 : inv port map( inb => n1784, outb => n4521);
U5254 : inv port map( inb => n1848, outb => n4563);
U5255 : inv port map( inb => n1912, outb => n4606);
U5256 : inv port map( inb => n1979, outb => n4645);
U5257 : inv port map( inb => n2017, outb => n5411);
U5258 : inv port map( inb => mult_125_G4_ab_3_13_port, outb => n402);
U5259 : inv port map( inb => n464, outb => n3661);
U5260 : inv port map( inb => mult_125_G4_ab_4_11_port, outb => n3662);
U5261 : inv port map( inb => mult_125_G4_ab_6_11_port, outb => n3665);
U5262 : inv port map( inb => mult_125_G4_ab_6_9_port, outb => n3704);
U5263 : inv port map( inb => n529, outb => n3706);
U5264 : inv port map( inb => mult_125_G4_ab_8_9_port, outb => n3707);
U5265 : inv port map( inb => mult_125_G4_ab_6_7_port, outb => n3744);
U5266 : inv port map( inb => mult_125_G4_ab_8_7_port, outb => n3747);
U5267 : inv port map( inb => n593, outb => n3749);
U5268 : inv port map( inb => mult_125_G4_ab_10_7_port, outb => n3750);
U5269 : inv port map( inb => mult_125_G4_ab_8_5_port, outb => n3783);
U5270 : inv port map( inb => mult_125_G4_ab_10_5_port, outb => n3786);
U5271 : inv port map( inb => n660, outb => n3788);
U5272 : inv port map( inb => mult_125_G4_ab_12_5_port, outb => n3789);
U5273 : inv port map( inb => n699, outb => n3808);
U5274 : inv port map( inb => mult_125_G4_ab_10_3_port, outb => n3821);
U5275 : inv port map( inb => mult_125_G4_ab_12_3_port, outb => n3824);
U5276 : inv port map( inb => n728, outb => n3826);
U5277 : inv port map( inb => mult_125_G4_ab_6_1_port, outb => n3854);
U5278 : inv port map( inb => mult_125_G4_ab_8_1_port, outb => n3857);
U5279 : inv port map( inb => mult_125_G4_ab_10_1_port, outb => n3860);
U5280 : inv port map( inb => mult_125_G4_ab_12_1_port, outb => n3863);
U5281 : inv port map( inb => mult_125_G3_ab_3_13_port, outb => n840);
U5282 : inv port map( inb => n902, outb => n3946);
U5283 : inv port map( inb => mult_125_G3_ab_4_11_port, outb => n3947);
U5284 : inv port map( inb => mult_125_G3_ab_6_11_port, outb => n3950);
U5285 : inv port map( inb => mult_125_G3_ab_6_9_port, outb => n3989);
U5286 : inv port map( inb => n967, outb => n3991);
U5287 : inv port map( inb => mult_125_G3_ab_8_9_port, outb => n3992);
U5288 : inv port map( inb => mult_125_G3_ab_6_7_port, outb => n4029);
U5289 : inv port map( inb => mult_125_G3_ab_8_7_port, outb => n4032);
U5290 : inv port map( inb => n1031, outb => n4034);
U5291 : inv port map( inb => mult_125_G3_ab_10_7_port, outb => n4035);
U5292 : inv port map( inb => mult_125_G3_ab_8_5_port, outb => n4068);
U5293 : inv port map( inb => mult_125_G3_ab_10_5_port, outb => n4071);
U5294 : inv port map( inb => n1098, outb => n4073);
U5295 : inv port map( inb => mult_125_G3_ab_12_5_port, outb => n4074);
U5296 : inv port map( inb => n1137, outb => n4093);
U5297 : inv port map( inb => mult_125_G3_ab_10_3_port, outb => n4106);
U5298 : inv port map( inb => mult_125_G3_ab_12_3_port, outb => n4109);
U5299 : inv port map( inb => n1166, outb => n4111);
U5300 : inv port map( inb => mult_125_G3_ab_6_1_port, outb => n4139);
U5301 : inv port map( inb => mult_125_G3_ab_8_1_port, outb => n4142);
U5302 : inv port map( inb => mult_125_G3_ab_10_1_port, outb => n4145);
U5303 : inv port map( inb => mult_125_G3_ab_12_1_port, outb => n4148);
U5304 : inv port map( inb => mult_125_G2_ab_3_13_port, outb => n1278);
U5305 : inv port map( inb => n1340, outb => n4231);
U5306 : inv port map( inb => mult_125_G2_ab_4_11_port, outb => n4232);
U5307 : inv port map( inb => mult_125_G2_ab_6_11_port, outb => n4235);
U5308 : inv port map( inb => mult_125_G2_ab_6_9_port, outb => n4274);
U5309 : inv port map( inb => n1405, outb => n4276);
U5310 : inv port map( inb => mult_125_G2_ab_8_9_port, outb => n4277);
U5311 : inv port map( inb => mult_125_G2_ab_6_7_port, outb => n4314);
U5312 : inv port map( inb => mult_125_G2_ab_8_7_port, outb => n4317);
U5313 : inv port map( inb => n1469, outb => n4319);
U5314 : inv port map( inb => mult_125_G2_ab_10_7_port, outb => n4320);
U5315 : inv port map( inb => mult_125_G2_ab_8_5_port, outb => n4353);
U5316 : inv port map( inb => mult_125_G2_ab_10_5_port, outb => n4356);
U5317 : inv port map( inb => n1536, outb => n4358);
U5318 : inv port map( inb => mult_125_G2_ab_12_5_port, outb => n4359);
U5319 : inv port map( inb => n1575, outb => n4378);
U5320 : inv port map( inb => mult_125_G2_ab_10_3_port, outb => n4391);
U5321 : inv port map( inb => mult_125_G2_ab_12_3_port, outb => n4394);
U5322 : inv port map( inb => n1604, outb => n4396);
U5323 : inv port map( inb => mult_125_G2_ab_6_1_port, outb => n4424);
U5324 : inv port map( inb => mult_125_G2_ab_8_1_port, outb => n4427);
U5325 : inv port map( inb => mult_125_G2_ab_10_1_port, outb => n4430);
U5326 : inv port map( inb => mult_125_G2_ab_12_1_port, outb => n4433);
U5327 : inv port map( inb => mult_125_ab_3_13_port, outb => n1716);
U5328 : inv port map( inb => n1778, outb => n4516);
U5329 : inv port map( inb => mult_125_ab_4_11_port, outb => n4517);
U5330 : inv port map( inb => mult_125_ab_6_11_port, outb => n4520);
U5331 : inv port map( inb => mult_125_ab_6_9_port, outb => n4559);
U5332 : inv port map( inb => n1843, outb => n4561);
U5333 : inv port map( inb => mult_125_ab_8_9_port, outb => n4562);
U5334 : inv port map( inb => mult_125_ab_6_7_port, outb => n4599);
U5335 : inv port map( inb => mult_125_ab_8_7_port, outb => n4602);
U5336 : inv port map( inb => n1907, outb => n4604);
U5337 : inv port map( inb => mult_125_ab_10_7_port, outb => n4605);
U5338 : inv port map( inb => mult_125_ab_8_5_port, outb => n4638);
U5339 : inv port map( inb => mult_125_ab_10_5_port, outb => n4641);
U5340 : inv port map( inb => n1974, outb => n4643);
U5341 : inv port map( inb => mult_125_ab_12_5_port, outb => n4644);
U5342 : inv port map( inb => n2013, outb => n4663);
U5343 : inv port map( inb => mult_125_ab_10_3_port, outb => n4676);
U5344 : inv port map( inb => mult_125_ab_12_3_port, outb => n4679);
U5345 : inv port map( inb => n2042, outb => n4681);
U5346 : inv port map( inb => mult_125_ab_6_1_port, outb => n4709);
U5347 : inv port map( inb => mult_125_ab_8_1_port, outb => n4712);
U5348 : inv port map( inb => mult_125_ab_10_1_port, outb => n4715);
U5349 : inv port map( inb => mult_125_ab_12_1_port, outb => n4718);
U5350 : inv port map( inb => n3642, outb => n436);
U5351 : inv port map( inb => n465, outb => n3664);
U5352 : inv port map( inb => mult_125_G4_ab_13_2_port, outb => n3844);
U5353 : inv port map( inb => n3927, outb => n874);
U5354 : inv port map( inb => n903, outb => n3949);
U5355 : inv port map( inb => mult_125_G3_ab_13_2_port, outb => n4129);
U5356 : inv port map( inb => n4212, outb => n1312);
U5357 : inv port map( inb => n1341, outb => n4234);
U5358 : inv port map( inb => mult_125_G2_ab_13_2_port, outb => n4414);
U5359 : inv port map( inb => n4497, outb => n1750);
U5360 : inv port map( inb => n1779, outb => n4519);
U5361 : inv port map( inb => mult_125_ab_13_2_port, outb => n4699);
U5362 : inv port map( inb => n404, outb => n3623);
U5363 : inv port map( inb => n493, outb => n3681);
U5364 : inv port map( inb => n589, outb => n3746);
U5365 : inv port map( inb => n656, outb => n3785);
U5366 : inv port map( inb => n760, outb => n3846);
U5367 : inv port map( inb => mult_125_G4_ab_15_2_port, outb => n4941);
U5368 : inv port map( inb => n842, outb => n3908);
U5369 : inv port map( inb => n931, outb => n3966);
U5370 : inv port map( inb => n1027, outb => n4031);
U5371 : inv port map( inb => n1094, outb => n4070);
U5372 : inv port map( inb => n1198, outb => n4131);
U5373 : inv port map( inb => mult_125_G3_ab_15_2_port, outb => n5087);
U5374 : inv port map( inb => n1280, outb => n4193);
U5375 : inv port map( inb => n1369, outb => n4251);
U5376 : inv port map( inb => n1465, outb => n4316);
U5377 : inv port map( inb => n1532, outb => n4355);
U5378 : inv port map( inb => n1636, outb => n4416);
U5379 : inv port map( inb => mult_125_G2_ab_15_2_port, outb => n5250);
U5380 : inv port map( inb => n1718, outb => n4478);
U5381 : inv port map( inb => n1807, outb => n4536);
U5382 : inv port map( inb => n1903, outb => n4601);
U5383 : inv port map( inb => n1970, outb => n4640);
U5384 : inv port map( inb => n2074, outb => n4701);
U5385 : inv port map( inb => mult_125_ab_15_2_port, outb => n5413);
U5386 : inv port map( inb => mult_125_G4_ab_5_8_port, outb => n3723);
U5387 : inv port map( inb => n557, outb => n3725);
U5388 : inv port map( inb => mult_125_G4_ab_5_6_port, outb => n616);
U5389 : inv port map( inb => mult_125_G4_ab_7_6_port, outb => n3764);
U5390 : inv port map( inb => mult_125_G4_ab_5_4_port, outb => n679);
U5391 : inv port map( inb => mult_125_G4_ab_7_4_port, outb => n684);
U5392 : inv port map( inb => mult_125_G4_ab_9_4_port, outb => n3802);
U5393 : inv port map( inb => mult_125_G4_ab_5_2_port, outb => n3833);
U5394 : inv port map( inb => mult_125_G4_ab_7_2_port, outb => n746);
U5395 : inv port map( inb => mult_125_G4_ab_9_2_port, outb => n3838);
U5396 : inv port map( inb => mult_125_G4_ab_11_2_port, outb => n3841);
U5397 : inv port map( inb => mult_125_G3_ab_5_8_port, outb => n4008);
U5398 : inv port map( inb => n995, outb => n4010);
U5399 : inv port map( inb => mult_125_G3_ab_5_6_port, outb => n1054);
U5400 : inv port map( inb => mult_125_G3_ab_7_6_port, outb => n4049);
U5401 : inv port map( inb => mult_125_G3_ab_5_4_port, outb => n1117);
U5402 : inv port map( inb => mult_125_G3_ab_7_4_port, outb => n1122);
U5403 : inv port map( inb => mult_125_G3_ab_9_4_port, outb => n4087);
U5404 : inv port map( inb => mult_125_G3_ab_5_2_port, outb => n4118);
U5405 : inv port map( inb => mult_125_G3_ab_7_2_port, outb => n1184);
U5406 : inv port map( inb => mult_125_G3_ab_9_2_port, outb => n4123);
U5407 : inv port map( inb => mult_125_G3_ab_11_2_port, outb => n4126);
U5408 : inv port map( inb => mult_125_G2_ab_5_8_port, outb => n4293);
U5409 : inv port map( inb => n1433, outb => n4295);
U5410 : inv port map( inb => mult_125_G2_ab_5_6_port, outb => n1492);
U5411 : inv port map( inb => mult_125_G2_ab_7_6_port, outb => n4334);
U5412 : inv port map( inb => mult_125_G2_ab_5_4_port, outb => n1555);
U5413 : inv port map( inb => mult_125_G2_ab_7_4_port, outb => n1560);
U5414 : inv port map( inb => mult_125_G2_ab_9_4_port, outb => n4372);
U5415 : inv port map( inb => mult_125_G2_ab_5_2_port, outb => n4403);
U5416 : inv port map( inb => mult_125_G2_ab_7_2_port, outb => n1622);
U5417 : inv port map( inb => mult_125_G2_ab_9_2_port, outb => n4408);
U5418 : inv port map( inb => mult_125_G2_ab_11_2_port, outb => n4411);
U5419 : inv port map( inb => mult_125_ab_5_8_port, outb => n4578);
U5420 : inv port map( inb => n1871, outb => n4580);
U5421 : inv port map( inb => mult_125_ab_5_6_port, outb => n1930);
U5422 : inv port map( inb => mult_125_ab_7_6_port, outb => n4619);
U5423 : inv port map( inb => mult_125_ab_5_4_port, outb => n1993);
U5424 : inv port map( inb => mult_125_ab_7_4_port, outb => n1998);
U5425 : inv port map( inb => mult_125_ab_9_4_port, outb => n4657);
U5426 : inv port map( inb => mult_125_ab_5_2_port, outb => n4688);
U5427 : inv port map( inb => mult_125_ab_7_2_port, outb => n2060);
U5428 : inv port map( inb => mult_125_ab_9_2_port, outb => n4693);
U5429 : inv port map( inb => mult_125_ab_11_2_port, outb => n4696);
U5430 : inv port map( inb => n622, outb => n3765);
U5431 : inv port map( inb => n686, outb => n3801);
U5432 : inv port map( inb => n690, outb => n3803);
U5433 : inv port map( inb => n732, outb => n4940);
U5434 : inv port map( inb => n739, outb => n3832);
U5435 : inv port map( inb => n748, outb => n3837);
U5436 : inv port map( inb => n752, outb => n3840);
U5437 : inv port map( inb => n756, outb => n3843);
U5438 : inv port map( inb => n1060, outb => n4050);
U5439 : inv port map( inb => n1124, outb => n4086);
U5440 : inv port map( inb => n1128, outb => n4088);
U5441 : inv port map( inb => n1170, outb => n5086);
U5442 : inv port map( inb => n1177, outb => n4117);
U5443 : inv port map( inb => n1186, outb => n4122);
U5444 : inv port map( inb => n1190, outb => n4125);
U5445 : inv port map( inb => n1194, outb => n4128);
U5446 : inv port map( inb => n1498, outb => n4335);
U5447 : inv port map( inb => n1562, outb => n4371);
U5448 : inv port map( inb => n1566, outb => n4373);
U5449 : inv port map( inb => n1608, outb => n5249);
U5450 : inv port map( inb => n1615, outb => n4402);
U5451 : inv port map( inb => n1624, outb => n4407);
U5452 : inv port map( inb => n1628, outb => n4410);
U5453 : inv port map( inb => n1632, outb => n4413);
U5454 : inv port map( inb => n1936, outb => n4620);
U5455 : inv port map( inb => n2000, outb => n4656);
U5456 : inv port map( inb => n2004, outb => n4658);
U5457 : inv port map( inb => n2046, outb => n5412);
U5458 : inv port map( inb => n2053, outb => n4687);
U5459 : inv port map( inb => n2062, outb => n4692);
U5460 : inv port map( inb => n2066, outb => n4695);
U5461 : inv port map( inb => n2070, outb => n4698);
U5462 : inv port map( inb => n556, outb => n3722);
U5463 : inv port map( inb => n618, outb => n3763);
U5464 : inv port map( inb => n265, outb => mult_125_G4_A2_17_port);
U5465 : inv port map( inb => n994, outb => n4007);
U5466 : inv port map( inb => n1056, outb => n4048);
U5467 : inv port map( inb => n373, outb => mult_125_G3_A2_17_port);
U5468 : inv port map( inb => n1432, outb => n4292);
U5469 : inv port map( inb => n1494, outb => n4333);
U5470 : inv port map( inb => n337, outb => mult_125_G2_A2_17_port);
U5471 : inv port map( inb => n1870, outb => n4577);
U5472 : inv port map( inb => n1932, outb => n4618);
U5473 : inv port map( inb => n301, outb => mult_125_A2_17_port);
U5474 : inv port map( inb => n525, outb => n3703);
U5475 : inv port map( inb => n584, outb => n3740);
U5476 : inv port map( inb => mult_125_G4_ab_4_7_port, outb => n3741);
U5477 : inv port map( inb => n585, outb => n3743);
U5478 : inv port map( inb => mult_125_G4_ab_6_5_port, outb => n650);
U5479 : inv port map( inb => n963, outb => n3988);
U5480 : inv port map( inb => n1022, outb => n4025);
U5481 : inv port map( inb => mult_125_G3_ab_4_7_port, outb => n4026);
U5482 : inv port map( inb => n1023, outb => n4028);
U5483 : inv port map( inb => mult_125_G3_ab_6_5_port, outb => n1088);
U5484 : inv port map( inb => n1401, outb => n4273);
U5485 : inv port map( inb => n1460, outb => n4310);
U5486 : inv port map( inb => mult_125_G2_ab_4_7_port, outb => n4311);
U5487 : inv port map( inb => n1461, outb => n4313);
U5488 : inv port map( inb => mult_125_G2_ab_6_5_port, outb => n1526);
U5489 : inv port map( inb => n1839, outb => n4558);
U5490 : inv port map( inb => n1898, outb => n4595);
U5491 : inv port map( inb => mult_125_ab_4_7_port, outb => n4596);
U5492 : inv port map( inb => n1899, outb => n4598);
U5493 : inv port map( inb => mult_125_ab_6_5_port, outb => n1964);
U5494 : inv port map( inb => n524, outb => n3700);
U5495 : inv port map( inb => mult_125_G4_ab_4_9_port, outb => n3701);
U5496 : inv port map( inb => n652, outb => n3782);
U5497 : inv port map( inb => n724, outb => n3823);
U5498 : inv port map( inb => n962, outb => n3985);
U5499 : inv port map( inb => mult_125_G3_ab_4_9_port, outb => n3986);
U5500 : inv port map( inb => n1090, outb => n4067);
U5501 : inv port map( inb => n1162, outb => n4108);
U5502 : inv port map( inb => n1400, outb => n4270);
U5503 : inv port map( inb => mult_125_G2_ab_4_9_port, outb => n4271);
U5504 : inv port map( inb => n1528, outb => n4352);
U5505 : inv port map( inb => n1600, outb => n4393);
U5506 : inv port map( inb => n1838, outb => n4555);
U5507 : inv port map( inb => mult_125_ab_4_9_port, outb => n4556);
U5508 : inv port map( inb => n1966, outb => n4637);
U5509 : inv port map( inb => n2038, outb => n4678);
U5510 : inv port map( inb => mult_125_G4_ab_4_8_port, outb => n3721);
U5511 : inv port map( inb => n681, outb => n3798);
U5512 : inv port map( inb => n720, outb => n3820);
U5513 : inv port map( inb => n743, outb => n3834);
U5514 : inv port map( inb => mult_125_G3_ab_4_8_port, outb => n4006);
U5515 : inv port map( inb => n1119, outb => n4083);
U5516 : inv port map( inb => n1158, outb => n4105);
U5517 : inv port map( inb => n1181, outb => n4119);
U5518 : inv port map( inb => mult_125_G2_ab_4_8_port, outb => n4291);
U5519 : inv port map( inb => n1557, outb => n4368);
U5520 : inv port map( inb => n1596, outb => n4390);
U5521 : inv port map( inb => n1619, outb => n4404);
U5522 : inv port map( inb => mult_125_ab_4_8_port, outb => n4576);
U5523 : inv port map( inb => n1995, outb => n4653);
U5524 : inv port map( inb => n2034, outb => n4675);
U5525 : inv port map( inb => n2057, outb => n4689);
U5526 : inv port map( inb => n554, outb => n3720);
U5527 : inv port map( inb => n646, outb => n3777);
U5528 : inv port map( inb => mult_125_G4_ab_4_5_port, outb => n3778);
U5529 : inv port map( inb => n711, outb => n3811);
U5530 : inv port map( inb => mult_125_G4_ab_4_3_port, outb => n3812);
U5531 : inv port map( inb => mult_125_G4_ab_6_3_port, outb => n3815);
U5532 : inv port map( inb => mult_125_G4_ab_8_3_port, outb => n3818);
U5533 : inv port map( inb => n992, outb => n4005);
U5534 : inv port map( inb => n1084, outb => n4062);
U5535 : inv port map( inb => mult_125_G3_ab_4_5_port, outb => n4063);
U5536 : inv port map( inb => n1149, outb => n4096);
U5537 : inv port map( inb => mult_125_G3_ab_4_3_port, outb => n4097);
U5538 : inv port map( inb => mult_125_G3_ab_6_3_port, outb => n4100);
U5539 : inv port map( inb => mult_125_G3_ab_8_3_port, outb => n4103);
U5540 : inv port map( inb => n1430, outb => n4290);
U5541 : inv port map( inb => n1522, outb => n4347);
U5542 : inv port map( inb => mult_125_G2_ab_4_5_port, outb => n4348);
U5543 : inv port map( inb => n1587, outb => n4381);
U5544 : inv port map( inb => mult_125_G2_ab_4_3_port, outb => n4382);
U5545 : inv port map( inb => mult_125_G2_ab_6_3_port, outb => n4385);
U5546 : inv port map( inb => mult_125_G2_ab_8_3_port, outb => n4388);
U5547 : inv port map( inb => n1868, outb => n4575);
U5548 : inv port map( inb => n1960, outb => n4632);
U5549 : inv port map( inb => mult_125_ab_4_5_port, outb => n4633);
U5550 : inv port map( inb => n2025, outb => n4666);
U5551 : inv port map( inb => mult_125_ab_4_3_port, outb => n4667);
U5552 : inv port map( inb => mult_125_ab_6_3_port, outb => n4670);
U5553 : inv port map( inb => mult_125_ab_8_3_port, outb => n4673);
U5554 : inv port map( inb => n647, outb => n3779);
U5555 : inv port map( inb => n716, outb => n3817);
U5556 : inv port map( inb => n1085, outb => n4064);
U5557 : inv port map( inb => n1154, outb => n4102);
U5558 : inv port map( inb => n1523, outb => n4349);
U5559 : inv port map( inb => n1592, outb => n4387);
U5560 : inv port map( inb => n1961, outb => n4634);
U5561 : inv port map( inb => n2030, outb => n4672);
U5562 : inv port map( inb => n613, outb => n3760);
U5563 : inv port map( inb => n676, outb => n3796);
U5564 : inv port map( inb => n1051, outb => n4045);
U5565 : inv port map( inb => n1114, outb => n4081);
U5566 : inv port map( inb => n1489, outb => n4330);
U5567 : inv port map( inb => n1552, outb => n4366);
U5568 : inv port map( inb => n1927, outb => n4615);
U5569 : inv port map( inb => n1990, outb => n4651);
U5570 : inv port map( inb => n455, outb => n4927);
U5571 : inv port map( inb => n516, outb => n4930);
U5572 : inv port map( inb => n575, outb => n4933);
U5573 : inv port map( inb => n637, outb => n4936);
U5574 : inv port map( inb => n712, outb => n3814);
U5575 : inv port map( inb => n775, outb => n3856);
U5576 : inv port map( inb => n779, outb => n3859);
U5577 : inv port map( inb => n783, outb => n3862);
U5578 : inv port map( inb => n787, outb => n3865);
U5579 : inv port map( inb => n791, outb => n4942);
U5580 : inv port map( inb => n893, outb => n5073);
U5581 : inv port map( inb => n954, outb => n5076);
U5582 : inv port map( inb => n1013, outb => n5079);
U5583 : inv port map( inb => n1075, outb => n5082);
U5584 : inv port map( inb => n1150, outb => n4099);
U5585 : inv port map( inb => n1213, outb => n4141);
U5586 : inv port map( inb => n1217, outb => n4144);
U5587 : inv port map( inb => n1221, outb => n4147);
U5588 : inv port map( inb => n1225, outb => n4150);
U5589 : inv port map( inb => n1229, outb => n5088);
U5590 : inv port map( inb => n1331, outb => n5236);
U5591 : inv port map( inb => n1392, outb => n5239);
U5592 : inv port map( inb => n1451, outb => n5242);
U5593 : inv port map( inb => n1513, outb => n5245);
U5594 : inv port map( inb => n1588, outb => n4384);
U5595 : inv port map( inb => n1651, outb => n4426);
U5596 : inv port map( inb => n1655, outb => n4429);
U5597 : inv port map( inb => n1659, outb => n4432);
U5598 : inv port map( inb => n1663, outb => n4435);
U5599 : inv port map( inb => n1667, outb => n5251);
U5600 : inv port map( inb => n1769, outb => n5399);
U5601 : inv port map( inb => n1830, outb => n5402);
U5602 : inv port map( inb => n1889, outb => n5405);
U5603 : inv port map( inb => n1951, outb => n5408);
U5604 : inv port map( inb => n2026, outb => n4669);
U5605 : inv port map( inb => n2089, outb => n4711);
U5606 : inv port map( inb => n2093, outb => n4714);
U5607 : inv port map( inb => n2097, outb => n4717);
U5608 : inv port map( inb => n2101, outb => n4720);
U5609 : inv port map( inb => n2105, outb => n5414);
U5610 : inv port map( inb => n3625, outb => n411);
U5611 : inv port map( inb => n3628, outb => n415);
U5612 : inv port map( inb => n3631, outb => n419);
U5613 : inv port map( inb => n3634, outb => n423);
U5614 : inv port map( inb => mult_125_G4_ab_2_12_port, outb => n429);
U5615 : inv port map( inb => n3639, outb => n432);
U5616 : inv port map( inb => n3644, outb => n438);
U5617 : inv port map( inb => n3647, outb => n442);
U5618 : inv port map( inb => n3650, outb => n446);
U5619 : inv port map( inb => n3653, outb => n450);
U5620 : inv port map( inb => n3656, outb => n454);
U5621 : inv port map( inb => mult_125_G4_ab_2_11_port, outb => n458);
U5622 : inv port map( inb => n3668, outb => n474);
U5623 : inv port map( inb => n3671, outb => n478);
U5624 : inv port map( inb => n3674, outb => n482);
U5625 : inv port map( inb => mult_125_G4_ab_15_11_port, outb => n486);
U5626 : inv port map( inb => mult_125_G4_ab_2_10_port, outb => n489);
U5627 : inv port map( inb => n3678, outb => n492);
U5628 : inv port map( inb => n3688, outb => n507);
U5629 : inv port map( inb => n3691, outb => n511);
U5630 : inv port map( inb => n3694, outb => n515);
U5631 : inv port map( inb => mult_125_G4_ab_2_9_port, outb => n519);
U5632 : inv port map( inb => n3697, outb => n522);
U5633 : inv port map( inb => n3705, outb => n532);
U5634 : inv port map( inb => n3710, outb => n538);
U5635 : inv port map( inb => n3713, outb => n542);
U5636 : inv port map( inb => mult_125_G4_ab_15_9_port, outb => n546);
U5637 : inv port map( inb => mult_125_G4_ab_2_8_port, outb => n549);
U5638 : inv port map( inb => n3717, outb => n552);
U5639 : inv port map( inb => n3724, outb => n560);
U5640 : inv port map( inb => n3732, outb => n570);
U5641 : inv port map( inb => n3735, outb => n574);
U5642 : inv port map( inb => mult_125_G4_ab_2_7_port, outb => n578);
U5643 : inv port map( inb => n3742, outb => n588);
U5644 : inv port map( inb => n3745, outb => n592);
U5645 : inv port map( inb => n3748, outb => n596);
U5646 : inv port map( inb => n3753, outb => n602);
U5647 : inv port map( inb => mult_125_G4_ab_15_7_port, outb => n606);
U5648 : inv port map( inb => mult_125_G4_ab_2_6_port, outb => n609);
U5649 : inv port map( inb => n3757, outb => n612);
U5650 : inv port map( inb => n3762, outb => n621);
U5651 : inv port map( inb => n3772, outb => n636);
U5652 : inv port map( inb => mult_125_G4_ab_2_5_port, outb => n640);
U5653 : inv port map( inb => n3784, outb => n659);
U5654 : inv port map( inb => n3787, outb => n663);
U5655 : inv port map( inb => mult_125_G4_ab_15_5_port, outb => n669);
U5656 : inv port map( inb => mult_125_G4_ab_2_4_port, outb => n672);
U5657 : inv port map( inb => n3793, outb => n675);
U5658 : inv port map( inb => mult_125_G4_ab_15_4_port, outb => n702);
U5659 : inv port map( inb => mult_125_G4_ab_2_3_port, outb => n705);
U5660 : inv port map( inb => n3822, outb => n727);
U5661 : inv port map( inb => mult_125_G4_ab_2_2_port, outb => n735);
U5662 : inv port map( inb => n3828, outb => n738);
U5663 : inv port map( inb => n3845, outb => n763);
U5664 : inv port map( inb => mult_125_G4_ab_2_1_port, outb => n765);
U5665 : inv port map( inb => n3847, outb => n768);
U5666 : inv port map( inb => n771, outb => n3853);
U5667 : inv port map( inb => n3855, outb => n778);
U5668 : inv port map( inb => n3864, outb => n790);
U5669 : inv port map( inb => n3874, outb => n802);
U5670 : inv port map( inb => n3878, outb => n806);
U5671 : inv port map( inb => n3882, outb => n810);
U5672 : inv port map( inb => n3886, outb => n814);
U5673 : inv port map( inb => n3890, outb => n818);
U5674 : inv port map( inb => n821, outb => n240);
U5675 : inv port map( inb => n3910, outb => n849);
U5676 : inv port map( inb => n3913, outb => n853);
U5677 : inv port map( inb => n3916, outb => n857);
U5678 : inv port map( inb => n3919, outb => n861);
U5679 : inv port map( inb => mult_125_G3_ab_2_12_port, outb => n867);
U5680 : inv port map( inb => n3924, outb => n870);
U5681 : inv port map( inb => n3929, outb => n876);
U5682 : inv port map( inb => n3932, outb => n880);
U5683 : inv port map( inb => n3935, outb => n884);
U5684 : inv port map( inb => n3938, outb => n888);
U5685 : inv port map( inb => n3941, outb => n892);
U5686 : inv port map( inb => mult_125_G3_ab_2_11_port, outb => n896);
U5687 : inv port map( inb => n3953, outb => n912);
U5688 : inv port map( inb => n3956, outb => n916);
U5689 : inv port map( inb => n3959, outb => n920);
U5690 : inv port map( inb => mult_125_G3_ab_15_11_port, outb => n924);
U5691 : inv port map( inb => mult_125_G3_ab_2_10_port, outb => n927);
U5692 : inv port map( inb => n3963, outb => n930);
U5693 : inv port map( inb => n3973, outb => n945);
U5694 : inv port map( inb => n3976, outb => n949);
U5695 : inv port map( inb => n3979, outb => n953);
U5696 : inv port map( inb => mult_125_G3_ab_2_9_port, outb => n957);
U5697 : inv port map( inb => n3982, outb => n960);
U5698 : inv port map( inb => n3990, outb => n970);
U5699 : inv port map( inb => n3995, outb => n976);
U5700 : inv port map( inb => n3998, outb => n980);
U5701 : inv port map( inb => mult_125_G3_ab_15_9_port, outb => n984);
U5702 : inv port map( inb => mult_125_G3_ab_2_8_port, outb => n987);
U5703 : inv port map( inb => n4002, outb => n990);
U5704 : inv port map( inb => n4009, outb => n998);
U5705 : inv port map( inb => n4017, outb => n1008);
U5706 : inv port map( inb => n4020, outb => n1012);
U5707 : inv port map( inb => mult_125_G3_ab_2_7_port, outb => n1016);
U5708 : inv port map( inb => n4027, outb => n1026);
U5709 : inv port map( inb => n4030, outb => n1030);
U5710 : inv port map( inb => n4033, outb => n1034);
U5711 : inv port map( inb => n4038, outb => n1040);
U5712 : inv port map( inb => mult_125_G3_ab_15_7_port, outb => n1044);
U5713 : inv port map( inb => mult_125_G3_ab_2_6_port, outb => n1047);
U5714 : inv port map( inb => n4042, outb => n1050);
U5715 : inv port map( inb => n4047, outb => n1059);
U5716 : inv port map( inb => n4057, outb => n1074);
U5717 : inv port map( inb => mult_125_G3_ab_2_5_port, outb => n1078);
U5718 : inv port map( inb => n4069, outb => n1097);
U5719 : inv port map( inb => n4072, outb => n1101);
U5720 : inv port map( inb => mult_125_G3_ab_15_5_port, outb => n1107);
U5721 : inv port map( inb => mult_125_G3_ab_2_4_port, outb => n1110);
U5722 : inv port map( inb => n4078, outb => n1113);
U5723 : inv port map( inb => mult_125_G3_ab_15_4_port, outb => n1140);
U5724 : inv port map( inb => mult_125_G3_ab_2_3_port, outb => n1143);
U5725 : inv port map( inb => n4107, outb => n1165);
U5726 : inv port map( inb => mult_125_G3_ab_2_2_port, outb => n1173);
U5727 : inv port map( inb => n4113, outb => n1176);
U5728 : inv port map( inb => n4130, outb => n1201);
U5729 : inv port map( inb => mult_125_G3_ab_2_1_port, outb => n1203);
U5730 : inv port map( inb => n4132, outb => n1206);
U5731 : inv port map( inb => n1209, outb => n4138);
U5732 : inv port map( inb => n4140, outb => n1216);
U5733 : inv port map( inb => n4149, outb => n1228);
U5734 : inv port map( inb => n4159, outb => n1240);
U5735 : inv port map( inb => n4163, outb => n1244);
U5736 : inv port map( inb => n4167, outb => n1248);
U5737 : inv port map( inb => n4171, outb => n1252);
U5738 : inv port map( inb => n4175, outb => n1256);
U5739 : inv port map( inb => n1259, outb => n348);
U5740 : inv port map( inb => n4195, outb => n1287);
U5741 : inv port map( inb => n4198, outb => n1291);
U5742 : inv port map( inb => n4201, outb => n1295);
U5743 : inv port map( inb => n4204, outb => n1299);
U5744 : inv port map( inb => mult_125_G2_ab_2_12_port, outb => n1305);
U5745 : inv port map( inb => n4209, outb => n1308);
U5746 : inv port map( inb => n4214, outb => n1314);
U5747 : inv port map( inb => n4217, outb => n1318);
U5748 : inv port map( inb => n4220, outb => n1322);
U5749 : inv port map( inb => n4223, outb => n1326);
U5750 : inv port map( inb => n4226, outb => n1330);
U5751 : inv port map( inb => mult_125_G2_ab_2_11_port, outb => n1334);
U5752 : inv port map( inb => n4238, outb => n1350);
U5753 : inv port map( inb => n4241, outb => n1354);
U5754 : inv port map( inb => n4244, outb => n1358);
U5755 : inv port map( inb => mult_125_G2_ab_15_11_port, outb => n1362);
U5756 : inv port map( inb => mult_125_G2_ab_2_10_port, outb => n1365);
U5757 : inv port map( inb => n4248, outb => n1368);
U5758 : inv port map( inb => n4258, outb => n1383);
U5759 : inv port map( inb => n4261, outb => n1387);
U5760 : inv port map( inb => n4264, outb => n1391);
U5761 : inv port map( inb => mult_125_G2_ab_2_9_port, outb => n1395);
U5762 : inv port map( inb => n4267, outb => n1398);
U5763 : inv port map( inb => n4275, outb => n1408);
U5764 : inv port map( inb => n4280, outb => n1414);
U5765 : inv port map( inb => n4283, outb => n1418);
U5766 : inv port map( inb => mult_125_G2_ab_15_9_port, outb => n1422);
U5767 : inv port map( inb => mult_125_G2_ab_2_8_port, outb => n1425);
U5768 : inv port map( inb => n4287, outb => n1428);
U5769 : inv port map( inb => n4294, outb => n1436);
U5770 : inv port map( inb => n4302, outb => n1446);
U5771 : inv port map( inb => n4305, outb => n1450);
U5772 : inv port map( inb => mult_125_G2_ab_2_7_port, outb => n1454);
U5773 : inv port map( inb => n4312, outb => n1464);
U5774 : inv port map( inb => n4315, outb => n1468);
U5775 : inv port map( inb => n4318, outb => n1472);
U5776 : inv port map( inb => n4323, outb => n1478);
U5777 : inv port map( inb => mult_125_G2_ab_15_7_port, outb => n1482);
U5778 : inv port map( inb => mult_125_G2_ab_2_6_port, outb => n1485);
U5779 : inv port map( inb => n4327, outb => n1488);
U5780 : inv port map( inb => n4332, outb => n1497);
U5781 : inv port map( inb => n4342, outb => n1512);
U5782 : inv port map( inb => mult_125_G2_ab_2_5_port, outb => n1516);
U5783 : inv port map( inb => n4354, outb => n1535);
U5784 : inv port map( inb => n4357, outb => n1539);
U5785 : inv port map( inb => mult_125_G2_ab_15_5_port, outb => n1545);
U5786 : inv port map( inb => mult_125_G2_ab_2_4_port, outb => n1548);
U5787 : inv port map( inb => n4363, outb => n1551);
U5788 : inv port map( inb => mult_125_G2_ab_15_4_port, outb => n1578);
U5789 : inv port map( inb => mult_125_G2_ab_2_3_port, outb => n1581);
U5790 : inv port map( inb => n4392, outb => n1603);
U5791 : inv port map( inb => mult_125_G2_ab_2_2_port, outb => n1611);
U5792 : inv port map( inb => n4398, outb => n1614);
U5793 : inv port map( inb => n4415, outb => n1639);
U5794 : inv port map( inb => mult_125_G2_ab_2_1_port, outb => n1641);
U5795 : inv port map( inb => n4417, outb => n1644);
U5796 : inv port map( inb => n1647, outb => n4423);
U5797 : inv port map( inb => n4425, outb => n1654);
U5798 : inv port map( inb => n4434, outb => n1666);
U5799 : inv port map( inb => n4444, outb => n1678);
U5800 : inv port map( inb => n4448, outb => n1682);
U5801 : inv port map( inb => n4452, outb => n1686);
U5802 : inv port map( inb => n4456, outb => n1690);
U5803 : inv port map( inb => n4460, outb => n1694);
U5804 : inv port map( inb => n1697, outb => n312);
U5805 : inv port map( inb => n4480, outb => n1725);
U5806 : inv port map( inb => n4483, outb => n1729);
U5807 : inv port map( inb => n4486, outb => n1733);
U5808 : inv port map( inb => n4489, outb => n1737);
U5809 : inv port map( inb => mult_125_ab_2_12_port, outb => n1743);
U5810 : inv port map( inb => n4494, outb => n1746);
U5811 : inv port map( inb => n4499, outb => n1752);
U5812 : inv port map( inb => n4502, outb => n1756);
U5813 : inv port map( inb => n4505, outb => n1760);
U5814 : inv port map( inb => n4508, outb => n1764);
U5815 : inv port map( inb => n4511, outb => n1768);
U5816 : inv port map( inb => mult_125_ab_2_11_port, outb => n1772);
U5817 : inv port map( inb => n4523, outb => n1788);
U5818 : inv port map( inb => n4526, outb => n1792);
U5819 : inv port map( inb => n4529, outb => n1796);
U5820 : inv port map( inb => mult_125_ab_15_11_port, outb => n1800);
U5821 : inv port map( inb => mult_125_ab_2_10_port, outb => n1803);
U5822 : inv port map( inb => n4533, outb => n1806);
U5823 : inv port map( inb => n4543, outb => n1821);
U5824 : inv port map( inb => n4546, outb => n1825);
U5825 : inv port map( inb => n4549, outb => n1829);
U5826 : inv port map( inb => mult_125_ab_2_9_port, outb => n1833);
U5827 : inv port map( inb => n4552, outb => n1836);
U5828 : inv port map( inb => n4560, outb => n1846);
U5829 : inv port map( inb => n4565, outb => n1852);
U5830 : inv port map( inb => n4568, outb => n1856);
U5831 : inv port map( inb => mult_125_ab_15_9_port, outb => n1860);
U5832 : inv port map( inb => mult_125_ab_2_8_port, outb => n1863);
U5833 : inv port map( inb => n4572, outb => n1866);
U5834 : inv port map( inb => n4579, outb => n1874);
U5835 : inv port map( inb => n4587, outb => n1884);
U5836 : inv port map( inb => n4590, outb => n1888);
U5837 : inv port map( inb => mult_125_ab_2_7_port, outb => n1892);
U5838 : inv port map( inb => n4597, outb => n1902);
U5839 : inv port map( inb => n4600, outb => n1906);
U5840 : inv port map( inb => n4603, outb => n1910);
U5841 : inv port map( inb => n4608, outb => n1916);
U5842 : inv port map( inb => mult_125_ab_15_7_port, outb => n1920);
U5843 : inv port map( inb => mult_125_ab_2_6_port, outb => n1923);
U5844 : inv port map( inb => n4612, outb => n1926);
U5845 : inv port map( inb => n4617, outb => n1935);
U5846 : inv port map( inb => n4627, outb => n1950);
U5847 : inv port map( inb => mult_125_ab_2_5_port, outb => n1954);
U5848 : inv port map( inb => n4639, outb => n1973);
U5849 : inv port map( inb => n4642, outb => n1977);
U5850 : inv port map( inb => mult_125_ab_15_5_port, outb => n1983);
U5851 : inv port map( inb => mult_125_ab_2_4_port, outb => n1986);
U5852 : inv port map( inb => n4648, outb => n1989);
U5853 : inv port map( inb => mult_125_ab_15_4_port, outb => n2016);
U5854 : inv port map( inb => mult_125_ab_2_3_port, outb => n2019);
U5855 : inv port map( inb => n4677, outb => n2041);
U5856 : inv port map( inb => mult_125_ab_2_2_port, outb => n2049);
U5857 : inv port map( inb => n4683, outb => n2052);
U5858 : inv port map( inb => n4700, outb => n2077);
U5859 : inv port map( inb => mult_125_ab_2_1_port, outb => n2079);
U5860 : inv port map( inb => n4702, outb => n2082);
U5861 : inv port map( inb => n2085, outb => n4708);
U5862 : inv port map( inb => n4710, outb => n2092);
U5863 : inv port map( inb => n4719, outb => n2104);
U5864 : inv port map( inb => n4729, outb => n2116);
U5865 : inv port map( inb => n4733, outb => n2120);
U5866 : inv port map( inb => n4737, outb => n2124);
U5867 : inv port map( inb => n4741, outb => n2128);
U5868 : inv port map( inb => n4745, outb => n2132);
U5869 : inv port map( inb => n2135, outb => n276);
U5870 : inv port map( inb => multiplier_sigs_1_31_port, outb => n5270);
U5871 : inv port map( inb => adder_mem_array_2_31_port, outb => n5269);
U5872 : inv port map( inb => multiplier_sigs_0_31_port, outb => n5433);
U5873 : inv port map( inb => adder_mem_array_1_31_port, outb => n5432);
U5874 : inv port map( inb => multiplier_sigs_2_31_port, outb => n5107);
U5875 : inv port map( inb => adder_mem_array_3_31_port, outb => n5106);
U5876 : inv port map( inb => n2238, outb => n242);
U5877 : inv port map( inb => mult_125_G4_ab_2_13_port, outb => n399);
U5878 : inv port map( inb => n401, outb => n3621);
U5879 : inv port map( inb => n3622, outb => n407);
U5880 : inv port map( inb => n426, outb => n4926);
U5881 : inv port map( inb => n435, outb => n3645);
U5882 : inv port map( inb => n460, outb => n3660);
U5883 : inv port map( inb => n3663, outb => n468);
U5884 : inv port map( inb => n485, outb => n4929);
U5885 : inv port map( inb => n4928, outb => n247);
U5886 : inv port map( inb => mult_125_G4_ab_15_12_port, outb => n5037);
U5887 : inv port map( inb => n495, outb => n3682);
U5888 : inv port map( inb => n3683, outb => n501);
U5889 : inv port map( inb => n3702, outb => n528);
U5890 : inv port map( inb => n545, outb => n4932);
U5891 : inv port map( inb => n4931, outb => n251);
U5892 : inv port map( inb => mult_125_G4_ab_15_10_port, outb => n5038);
U5893 : inv port map( inb => n3727, outb => n564);
U5894 : inv port map( inb => n580, outb => n3739);
U5895 : inv port map( inb => n605, outb => n4935);
U5896 : inv port map( inb => n4934, outb => n255);
U5897 : inv port map( inb => mult_125_G4_ab_15_8_port, outb => n5039);
U5898 : inv port map( inb => n615, outb => n3761);
U5899 : inv port map( inb => n624, outb => n3766);
U5900 : inv port map( inb => n3767, outb => n630);
U5901 : inv port map( inb => n642, outb => n3776);
U5902 : inv port map( inb => n649, outb => n3780);
U5903 : inv port map( inb => n3781, outb => n655);
U5904 : inv port map( inb => n668, outb => n4938);
U5905 : inv port map( inb => n4937, outb => n259);
U5906 : inv port map( inb => mult_125_G4_ab_15_6_port, outb => n5040);
U5907 : inv port map( inb => n678, outb => n3797);
U5908 : inv port map( inb => n683, outb => n3799);
U5909 : inv port map( inb => n3800, outb => n689);
U5910 : inv port map( inb => n692, outb => n3804);
U5911 : inv port map( inb => n3805, outb => n698);
U5912 : inv port map( inb => n707, outb => n3810);
U5913 : inv port map( inb => n3813, outb => n715);
U5914 : inv port map( inb => n3816, outb => n719);
U5915 : inv port map( inb => n3819, outb => n723);
U5916 : inv port map( inb => n3825, outb => n731);
U5917 : inv port map( inb => n3831, outb => n742);
U5918 : inv port map( inb => n745, outb => n3835);
U5919 : inv port map( inb => n3836, outb => n751);
U5920 : inv port map( inb => n3839, outb => n755);
U5921 : inv port map( inb => n3842, outb => n759);
U5922 : inv port map( inb => n3852, outb => n774);
U5923 : inv port map( inb => n3858, outb => n782);
U5924 : inv port map( inb => n3861, outb => n786);
U5925 : inv port map( inb => n793, outb => n3869);
U5926 : inv port map( inb => n795, outb => n3871);
U5927 : inv port map( inb => n3870, outb => n798);
U5928 : inv port map( inb => n5041, outb => n5030);
U5929 : inv port map( inb => mult_125_G4_ab_7_1_port, outb => n5042);
U5930 : inv port map( inb => mult_125_G4_ab_9_1_port, outb => n5043);
U5931 : inv port map( inb => mult_125_G4_ab_11_1_port, outb => n5044);
U5932 : inv port map( inb => mult_125_G4_ab_13_1_port, outb => n5045);
U5933 : inv port map( inb => mult_125_G4_ab_15_1_port, outb => n5046);
U5934 : inv port map( inb => n2535, outb => n350);
U5935 : inv port map( inb => mult_125_G3_ab_2_13_port, outb => n837);
U5936 : inv port map( inb => n839, outb => n3906);
U5937 : inv port map( inb => n3907, outb => n845);
U5938 : inv port map( inb => n864, outb => n5072);
U5939 : inv port map( inb => n873, outb => n3930);
U5940 : inv port map( inb => n898, outb => n3945);
U5941 : inv port map( inb => n3948, outb => n906);
U5942 : inv port map( inb => n923, outb => n5075);
U5943 : inv port map( inb => n5074, outb => n355);
U5944 : inv port map( inb => mult_125_G3_ab_15_12_port, outb => n5200);
U5945 : inv port map( inb => n933, outb => n3967);
U5946 : inv port map( inb => n3968, outb => n939);
U5947 : inv port map( inb => n3987, outb => n966);
U5948 : inv port map( inb => n983, outb => n5078);
U5949 : inv port map( inb => n5077, outb => n359);
U5950 : inv port map( inb => mult_125_G3_ab_15_10_port, outb => n5201);
U5951 : inv port map( inb => n4012, outb => n1002);
U5952 : inv port map( inb => n1018, outb => n4024);
U5953 : inv port map( inb => n1043, outb => n5081);
U5954 : inv port map( inb => n5080, outb => n363);
U5955 : inv port map( inb => mult_125_G3_ab_15_8_port, outb => n5202);
U5956 : inv port map( inb => n1053, outb => n4046);
U5957 : inv port map( inb => n1062, outb => n4051);
U5958 : inv port map( inb => n4052, outb => n1068);
U5959 : inv port map( inb => n1080, outb => n4061);
U5960 : inv port map( inb => n1087, outb => n4065);
U5961 : inv port map( inb => n4066, outb => n1093);
U5962 : inv port map( inb => n1106, outb => n5084);
U5963 : inv port map( inb => n5083, outb => n367);
U5964 : inv port map( inb => mult_125_G3_ab_15_6_port, outb => n5203);
U5965 : inv port map( inb => n1116, outb => n4082);
U5966 : inv port map( inb => n1121, outb => n4084);
U5967 : inv port map( inb => n4085, outb => n1127);
U5968 : inv port map( inb => n1130, outb => n4089);
U5969 : inv port map( inb => n4090, outb => n1136);
U5970 : inv port map( inb => n1145, outb => n4095);
U5971 : inv port map( inb => n4098, outb => n1153);
U5972 : inv port map( inb => n4101, outb => n1157);
U5973 : inv port map( inb => n4104, outb => n1161);
U5974 : inv port map( inb => n4110, outb => n1169);
U5975 : inv port map( inb => n4116, outb => n1180);
U5976 : inv port map( inb => n1183, outb => n4120);
U5977 : inv port map( inb => n4121, outb => n1189);
U5978 : inv port map( inb => n4124, outb => n1193);
U5979 : inv port map( inb => n4127, outb => n1197);
U5980 : inv port map( inb => n4137, outb => n1212);
U5981 : inv port map( inb => n4143, outb => n1220);
U5982 : inv port map( inb => n4146, outb => n1224);
U5983 : inv port map( inb => n1231, outb => n4154);
U5984 : inv port map( inb => n1233, outb => n4156);
U5985 : inv port map( inb => n4155, outb => n1236);
U5986 : inv port map( inb => n5204, outb => n5193);
U5987 : inv port map( inb => mult_125_G3_ab_7_1_port, outb => n5205);
U5988 : inv port map( inb => mult_125_G3_ab_9_1_port, outb => n5206);
U5989 : inv port map( inb => mult_125_G3_ab_11_1_port, outb => n5207);
U5990 : inv port map( inb => mult_125_G3_ab_13_1_port, outb => n5208);
U5991 : inv port map( inb => mult_125_G3_ab_15_1_port, outb => n5209);
U5992 : inv port map( inb => n2832, outb => n314);
U5993 : inv port map( inb => mult_125_G2_ab_2_13_port, outb => n1275);
U5994 : inv port map( inb => n1277, outb => n4191);
U5995 : inv port map( inb => n4192, outb => n1283);
U5996 : inv port map( inb => n1302, outb => n5235);
U5997 : inv port map( inb => n1311, outb => n4215);
U5998 : inv port map( inb => n1336, outb => n4230);
U5999 : inv port map( inb => n4233, outb => n1344);
U6000 : inv port map( inb => n1361, outb => n5238);
U6001 : inv port map( inb => n5237, outb => n319);
U6002 : inv port map( inb => mult_125_G2_ab_15_12_port, outb => n5363);
U6003 : inv port map( inb => n1371, outb => n4252);
U6004 : inv port map( inb => n4253, outb => n1377);
U6005 : inv port map( inb => n4272, outb => n1404);
U6006 : inv port map( inb => n1421, outb => n5241);
U6007 : inv port map( inb => n5240, outb => n323);
U6008 : inv port map( inb => mult_125_G2_ab_15_10_port, outb => n5364);
U6009 : inv port map( inb => n4297, outb => n1440);
U6010 : inv port map( inb => n1456, outb => n4309);
U6011 : inv port map( inb => n1481, outb => n5244);
U6012 : inv port map( inb => n5243, outb => n327);
U6013 : inv port map( inb => mult_125_G2_ab_15_8_port, outb => n5365);
U6014 : inv port map( inb => n1491, outb => n4331);
U6015 : inv port map( inb => n1500, outb => n4336);
U6016 : inv port map( inb => n4337, outb => n1506);
U6017 : inv port map( inb => n1518, outb => n4346);
U6018 : inv port map( inb => n1525, outb => n4350);
U6019 : inv port map( inb => n4351, outb => n1531);
U6020 : inv port map( inb => n1544, outb => n5247);
U6021 : inv port map( inb => n5246, outb => n331);
U6022 : inv port map( inb => mult_125_G2_ab_15_6_port, outb => n5366);
U6023 : inv port map( inb => n1554, outb => n4367);
U6024 : inv port map( inb => n1559, outb => n4369);
U6025 : inv port map( inb => n4370, outb => n1565);
U6026 : inv port map( inb => n1568, outb => n4374);
U6027 : inv port map( inb => n4375, outb => n1574);
U6028 : inv port map( inb => n1583, outb => n4380);
U6029 : inv port map( inb => n4383, outb => n1591);
U6030 : inv port map( inb => n4386, outb => n1595);
U6031 : inv port map( inb => n4389, outb => n1599);
U6032 : inv port map( inb => n4395, outb => n1607);
U6033 : inv port map( inb => n4401, outb => n1618);
U6034 : inv port map( inb => n1621, outb => n4405);
U6035 : inv port map( inb => n4406, outb => n1627);
U6036 : inv port map( inb => n4409, outb => n1631);
U6037 : inv port map( inb => n4412, outb => n1635);
U6038 : inv port map( inb => n4422, outb => n1650);
U6039 : inv port map( inb => n4428, outb => n1658);
U6040 : inv port map( inb => n4431, outb => n1662);
U6041 : inv port map( inb => n1669, outb => n4439);
U6042 : inv port map( inb => n1671, outb => n4441);
U6043 : inv port map( inb => n4440, outb => n1674);
U6044 : inv port map( inb => n5367, outb => n5356);
U6045 : inv port map( inb => mult_125_G2_ab_7_1_port, outb => n5368);
U6046 : inv port map( inb => mult_125_G2_ab_9_1_port, outb => n5369);
U6047 : inv port map( inb => mult_125_G2_ab_11_1_port, outb => n5370);
U6048 : inv port map( inb => mult_125_G2_ab_13_1_port, outb => n5371);
U6049 : inv port map( inb => mult_125_G2_ab_15_1_port, outb => n5372);
U6050 : inv port map( inb => n3129, outb => n278);
U6051 : inv port map( inb => mult_125_ab_2_13_port, outb => n1713);
U6052 : inv port map( inb => n1715, outb => n4476);
U6053 : inv port map( inb => n4477, outb => n1721);
U6054 : inv port map( inb => n1740, outb => n5398);
U6055 : inv port map( inb => n1749, outb => n4500);
U6056 : inv port map( inb => n1774, outb => n4515);
U6057 : inv port map( inb => n4518, outb => n1782);
U6058 : inv port map( inb => n1799, outb => n5401);
U6059 : inv port map( inb => n5400, outb => n283);
U6060 : inv port map( inb => mult_125_ab_15_12_port, outb => n5526);
U6061 : inv port map( inb => n1809, outb => n4537);
U6062 : inv port map( inb => n4538, outb => n1815);
U6063 : inv port map( inb => n4557, outb => n1842);
U6064 : inv port map( inb => n1859, outb => n5404);
U6065 : inv port map( inb => n5403, outb => n287);
U6066 : inv port map( inb => mult_125_ab_15_10_port, outb => n5527);
U6067 : inv port map( inb => n4582, outb => n1878);
U6068 : inv port map( inb => n1894, outb => n4594);
U6069 : inv port map( inb => n1919, outb => n5407);
U6070 : inv port map( inb => n5406, outb => n291);
U6071 : inv port map( inb => mult_125_ab_15_8_port, outb => n5528);
U6072 : inv port map( inb => n1929, outb => n4616);
U6073 : inv port map( inb => n1938, outb => n4621);
U6074 : inv port map( inb => n4622, outb => n1944);
U6075 : inv port map( inb => n1956, outb => n4631);
U6076 : inv port map( inb => n1963, outb => n4635);
U6077 : inv port map( inb => n4636, outb => n1969);
U6078 : inv port map( inb => n1982, outb => n5410);
U6079 : inv port map( inb => n5409, outb => n295);
U6080 : inv port map( inb => mult_125_ab_15_6_port, outb => n5529);
U6081 : inv port map( inb => n1992, outb => n4652);
U6082 : inv port map( inb => n1997, outb => n4654);
U6083 : inv port map( inb => n4655, outb => n2003);
U6084 : inv port map( inb => n2006, outb => n4659);
U6085 : inv port map( inb => n4660, outb => n2012);
U6086 : inv port map( inb => n2021, outb => n4665);
U6087 : inv port map( inb => n4668, outb => n2029);
U6088 : inv port map( inb => n4671, outb => n2033);
U6089 : inv port map( inb => n4674, outb => n2037);
U6090 : inv port map( inb => n4680, outb => n2045);
U6091 : inv port map( inb => n4686, outb => n2056);
U6092 : inv port map( inb => n2059, outb => n4690);
U6093 : inv port map( inb => n4691, outb => n2065);
U6094 : inv port map( inb => n4694, outb => n2069);
U6095 : inv port map( inb => n4697, outb => n2073);
U6096 : inv port map( inb => n4707, outb => n2088);
U6097 : inv port map( inb => n4713, outb => n2096);
U6098 : inv port map( inb => n4716, outb => n2100);
U6099 : inv port map( inb => n2107, outb => n4724);
U6100 : inv port map( inb => n2109, outb => n4726);
U6101 : inv port map( inb => n4725, outb => n2112);
U6102 : inv port map( inb => n5530, outb => n5519);
U6103 : inv port map( inb => mult_125_ab_7_1_port, outb => n5531);
U6104 : inv port map( inb => mult_125_ab_9_1_port, outb => n5532);
U6105 : inv port map( inb => mult_125_ab_11_1_port, outb => n5533);
U6106 : inv port map( inb => mult_125_ab_13_1_port, outb => n5534);
U6107 : inv port map( inb => mult_125_ab_15_1_port, outb => n5535);
U6108 : inv port map( inb => n2136, outb => n5091);
U6109 : inv port map( inb => n2163, outb => n5417);
U6110 : inv port map( inb => n2166, outb => n5254);
U6111 : inv port map( inb => n5536, outb => mult_125_G4_ZB);
U6112 : inv port map( inb => n5537, outb => mult_125_G4_ZA);
U6113 : inv port map( inb => n5538, outb => mult_125_G4_QB);
U6114 : inv port map( inb => n5539, outb => mult_125_G4_QA);
U6115 : inv port map( inb => mult_125_G4_A1_0_port, outb => n5540);
U6116 : inv port map( inb => n5541, outb => multiplier_sigs_3_2_port);
U6117 : inv port map( inb => mult_125_G4_A1_1_port, outb => n5542);
U6118 : inv port map( inb => n5543, outb => multiplier_sigs_3_3_port);
U6119 : inv port map( inb => mult_125_G4_A1_2_port, outb => n5544);
U6120 : inv port map( inb => n5545, outb => multiplier_sigs_3_4_port);
U6121 : inv port map( inb => mult_125_G4_A1_3_port, outb => n5546);
U6122 : inv port map( inb => n5547, outb => multiplier_sigs_3_5_port);
U6123 : inv port map( inb => mult_125_G4_A1_4_port, outb => n5548);
U6124 : inv port map( inb => n5549, outb => multiplier_sigs_3_6_port);
U6125 : inv port map( inb => mult_125_G4_A1_5_port, outb => n5550);
U6126 : inv port map( inb => n5551, outb => multiplier_sigs_3_7_port);
U6127 : inv port map( inb => mult_125_G4_A1_6_port, outb => n5552);
U6128 : inv port map( inb => n5553, outb => multiplier_sigs_3_8_port);
U6129 : inv port map( inb => mult_125_G4_A1_7_port, outb => n5554);
U6130 : inv port map( inb => n5555, outb => multiplier_sigs_3_9_port);
U6131 : inv port map( inb => mult_125_G4_A1_8_port, outb => n5556);
U6132 : inv port map( inb => n5557, outb => multiplier_sigs_3_10_port);
U6133 : inv port map( inb => mult_125_G4_A1_9_port, outb => n5558);
U6134 : inv port map( inb => n5559, outb => multiplier_sigs_3_11_port);
U6135 : inv port map( inb => mult_125_G4_A1_10_port, outb => n5560);
U6136 : inv port map( inb => n5561, outb => multiplier_sigs_3_12_port);
U6137 : inv port map( inb => mult_125_G4_A1_11_port, outb => n5562);
U6138 : inv port map( inb => n5563, outb => multiplier_sigs_3_13_port);
U6139 : inv port map( inb => mult_125_G4_A1_12_port, outb => n5564);
U6140 : inv port map( inb => n5565, outb => multiplier_sigs_3_14_port);
U6141 : inv port map( inb => mult_125_G4_A1_13_port, outb => n5566);
U6142 : inv port map( inb => n5567, outb => multiplier_sigs_3_15_port);
U6143 : inv port map( inb => mult_125_G4_A1_14_port, outb => n5568);
U6144 : inv port map( inb => mult_125_G4_A2_14_port, outb => n5569);
U6145 : inv port map( inb => n5570, outb => multiplier_sigs_3_16_port);
U6146 : inv port map( inb => mult_125_G4_A1_15_port, outb => n5571);
U6147 : inv port map( inb => mult_125_G4_A2_15_port, outb => n5572);
U6148 : inv port map( inb => n5573, outb =>
mult_125_G4_FS_1_PG_int_0_3_3_port);
U6149 : inv port map( inb => mult_125_G4_FS_1_TEMP_G_0_3_2_port, outb =>
n5574);
U6150 : inv port map( inb => mult_125_G4_FS_1_P_0_3_3_port, outb => n5575);
U6151 : inv port map( inb => mult_125_G4_A1_16_port, outb => n5576);
U6152 : inv port map( inb => mult_125_G4_A2_16_port, outb => n5577);
U6153 : inv port map( inb => n5578, outb =>
mult_125_G4_FS_1_PG_int_0_4_0_port);
U6154 : inv port map( inb => mult_125_G4_A1_17_port, outb => n5579);
U6155 : inv port map( inb => mult_125_G4_A2_17_port, outb => n5580);
U6156 : inv port map( inb => n5581, outb =>
mult_125_G4_FS_1_PG_int_0_4_1_port);
U6157 : inv port map( inb => n5582, outb =>
mult_125_G4_FS_1_TEMP_P_0_4_1_port);
U6158 : inv port map( inb => mult_125_G4_FS_1_TEMP_P_0_4_0_port, outb =>
n5583);
U6159 : inv port map( inb => mult_125_G4_A1_18_port, outb => n5584);
U6160 : inv port map( inb => mult_125_G4_A2_18_port, outb => n5585);
U6161 : inv port map( inb => n5586, outb =>
mult_125_G4_FS_1_PG_int_0_4_2_port);
U6162 : inv port map( inb => n5587, outb =>
mult_125_G4_FS_1_TEMP_P_0_4_2_port);
U6163 : inv port map( inb => mult_125_G4_FS_1_TEMP_G_0_4_1_port, outb =>
n5588);
U6164 : inv port map( inb => mult_125_G4_FS_1_C_1_4_1_port, outb => n5589);
U6165 : inv port map( inb => mult_125_G4_FS_1_P_0_4_1_port, outb => n5590);
U6166 : inv port map( inb => mult_125_G4_A1_19_port, outb => n5591);
U6167 : inv port map( inb => mult_125_G4_A2_19_port, outb => n5592);
U6168 : inv port map( inb => n5593, outb =>
mult_125_G4_FS_1_PG_int_0_4_3_port);
U6169 : inv port map( inb => mult_125_G4_FS_1_TEMP_G_0_4_2_port, outb =>
n5594);
U6170 : inv port map( inb => mult_125_G4_FS_1_P_0_4_3_port, outb => n5595);
U6171 : inv port map( inb => mult_125_G4_FS_1_C_1_4_2_port, outb => n5596);
U6172 : inv port map( inb => mult_125_G4_FS_1_P_0_4_2_port, outb => n5597);
U6173 : inv port map( inb => mult_125_G4_A1_20_port, outb => n5598);
U6174 : inv port map( inb => mult_125_G4_A2_20_port, outb => n5599);
U6175 : inv port map( inb => n5600, outb =>
mult_125_G4_FS_1_PG_int_0_5_0_port);
U6176 : inv port map( inb => mult_125_G4_A1_21_port, outb => n5601);
U6177 : inv port map( inb => mult_125_G4_A2_21_port, outb => n5602);
U6178 : inv port map( inb => n5603, outb =>
mult_125_G4_FS_1_PG_int_0_5_1_port);
U6179 : inv port map( inb => n5604, outb =>
mult_125_G4_FS_1_TEMP_P_0_5_1_port);
U6180 : inv port map( inb => mult_125_G4_FS_1_TEMP_P_0_5_0_port, outb =>
n5605);
U6181 : inv port map( inb => mult_125_G4_A1_22_port, outb => n5606);
U6182 : inv port map( inb => mult_125_G4_A2_22_port, outb => n5607);
U6183 : inv port map( inb => n5608, outb =>
mult_125_G4_FS_1_PG_int_0_5_2_port);
U6184 : inv port map( inb => n5609, outb =>
mult_125_G4_FS_1_TEMP_P_0_5_2_port);
U6185 : inv port map( inb => mult_125_G4_FS_1_TEMP_G_0_5_1_port, outb =>
n5610);
U6186 : inv port map( inb => mult_125_G4_FS_1_C_1_5_1_port, outb => n5611);
U6187 : inv port map( inb => mult_125_G4_FS_1_P_0_5_1_port, outb => n5612);
U6188 : inv port map( inb => mult_125_G4_A1_23_port, outb => n5613);
U6189 : inv port map( inb => mult_125_G4_A2_23_port, outb => n5614);
U6190 : inv port map( inb => n5615, outb =>
mult_125_G4_FS_1_PG_int_0_5_3_port);
U6191 : inv port map( inb => mult_125_G4_FS_1_TEMP_G_0_5_2_port, outb =>
n5616);
U6192 : inv port map( inb => mult_125_G4_FS_1_P_0_5_3_port, outb => n5617);
U6193 : inv port map( inb => mult_125_G4_FS_1_C_1_5_2_port, outb => n5618);
U6194 : inv port map( inb => mult_125_G4_FS_1_P_0_5_2_port, outb => n5619);
U6195 : inv port map( inb => mult_125_G4_A1_24_port, outb => n5620);
U6196 : inv port map( inb => mult_125_G4_A2_24_port, outb => n5621);
U6197 : inv port map( inb => n5622, outb =>
mult_125_G4_FS_1_PG_int_0_6_0_port);
U6198 : inv port map( inb => mult_125_G4_A1_25_port, outb => n5623);
U6199 : inv port map( inb => mult_125_G4_A2_25_port, outb => n5624);
U6200 : inv port map( inb => n5625, outb =>
mult_125_G4_FS_1_PG_int_0_6_1_port);
U6201 : inv port map( inb => n5626, outb =>
mult_125_G4_FS_1_TEMP_P_0_6_1_port);
U6202 : inv port map( inb => mult_125_G4_FS_1_TEMP_P_0_6_0_port, outb =>
n5627);
U6203 : inv port map( inb => mult_125_G4_A1_26_port, outb => n5628);
U6204 : inv port map( inb => mult_125_G4_A2_26_port, outb => n5629);
U6205 : inv port map( inb => n5630, outb =>
mult_125_G4_FS_1_PG_int_0_6_2_port);
U6206 : inv port map( inb => n5631, outb =>
mult_125_G4_FS_1_TEMP_P_0_6_2_port);
U6207 : inv port map( inb => mult_125_G4_FS_1_TEMP_G_0_6_1_port, outb =>
n5632);
U6208 : inv port map( inb => mult_125_G4_FS_1_C_1_6_1_port, outb => n5633);
U6209 : inv port map( inb => mult_125_G4_FS_1_P_0_6_1_port, outb => n5634);
U6210 : inv port map( inb => mult_125_G4_A1_27_port, outb => n5635);
U6211 : inv port map( inb => mult_125_G4_A2_27_port, outb => n5636);
U6212 : inv port map( inb => n5637, outb =>
mult_125_G4_FS_1_PG_int_0_6_3_port);
U6213 : inv port map( inb => mult_125_G4_FS_1_TEMP_G_0_6_2_port, outb =>
n5638);
U6214 : inv port map( inb => mult_125_G4_FS_1_P_0_6_3_port, outb => n5639);
U6215 : inv port map( inb => mult_125_G4_FS_1_C_1_6_2_port, outb => n5640);
U6216 : inv port map( inb => mult_125_G4_FS_1_P_0_6_2_port, outb => n5641);
U6217 : inv port map( inb => mult_125_G4_A1_28_port, outb => n5642);
U6218 : inv port map( inb => mult_125_G4_A2_28_port, outb => n5643);
U6219 : inv port map( inb => n5644, outb =>
mult_125_G4_FS_1_PG_int_0_7_0_port);
U6220 : inv port map( inb => mult_125_G4_A1_29_port, outb => n5645);
U6221 : inv port map( inb => mult_125_G4_A2_29_port, outb => n5646);
U6222 : inv port map( inb => n5647, outb =>
mult_125_G4_FS_1_PG_int_0_7_1_port);
U6223 : inv port map( inb => mult_125_G4_FS_1_C_1_7_0_port, outb => n5648);
U6224 : inv port map( inb => mult_125_G4_FS_1_TEMP_P_0_7_0_port, outb =>
n5649);
U6225 : inv port map( inb => mult_125_G4_FS_1_G_1_0_3_port, outb => n5650);
U6226 : inv port map( inb => mult_125_G4_FS_1_C_1_4_0_port, outb => n5651);
U6227 : inv port map( inb => mult_125_G4_FS_1_G_1_1_0_port, outb => n5653);
U6228 : inv port map( inb => mult_125_G4_FS_1_C_1_5_0_port, outb => n5654);
U6229 : inv port map( inb => mult_125_G4_FS_1_G_1_1_1_port, outb => n5656);
U6230 : inv port map( inb => mult_125_G4_FS_1_C_1_6_0_port, outb => n5657);
U6231 : inv port map( inb => mult_125_G4_FS_1_G_1_1_2_port, outb => n5659);
U6232 : inv port map( inb => mult_125_G4_FS_1_G_2_0_0_port, outb => n5660);
U6233 : inv port map( inb => n5661, outb => mult_125_ZB);
U6234 : inv port map( inb => n5662, outb => mult_125_ZA);
U6235 : inv port map( inb => n5663, outb => mult_125_QB);
U6236 : inv port map( inb => n5664, outb => mult_125_QA);
U6237 : inv port map( inb => mult_125_A1_0_port, outb => n5665);
U6238 : inv port map( inb => n5666, outb => multiplier_sigs_0_2_port);
U6239 : inv port map( inb => mult_125_A1_1_port, outb => n5667);
U6240 : inv port map( inb => n5668, outb => multiplier_sigs_0_3_port);
U6241 : inv port map( inb => mult_125_A1_2_port, outb => n5669);
U6242 : inv port map( inb => n5670, outb => multiplier_sigs_0_4_port);
U6243 : inv port map( inb => mult_125_A1_3_port, outb => n5671);
U6244 : inv port map( inb => n5672, outb => multiplier_sigs_0_5_port);
U6245 : inv port map( inb => mult_125_A1_4_port, outb => n5673);
U6246 : inv port map( inb => n5674, outb => multiplier_sigs_0_6_port);
U6247 : inv port map( inb => mult_125_A1_5_port, outb => n5675);
U6248 : inv port map( inb => n5676, outb => multiplier_sigs_0_7_port);
U6249 : inv port map( inb => mult_125_A1_6_port, outb => n5677);
U6250 : inv port map( inb => n5678, outb => multiplier_sigs_0_8_port);
U6251 : inv port map( inb => mult_125_A1_7_port, outb => n5679);
U6252 : inv port map( inb => n5680, outb => multiplier_sigs_0_9_port);
U6253 : inv port map( inb => mult_125_A1_8_port, outb => n5681);
U6254 : inv port map( inb => n5682, outb => multiplier_sigs_0_10_port);
U6255 : inv port map( inb => mult_125_A1_9_port, outb => n5683);
U6256 : inv port map( inb => n5684, outb => multiplier_sigs_0_11_port);
U6257 : inv port map( inb => mult_125_A1_10_port, outb => n5685);
U6258 : inv port map( inb => n5686, outb => multiplier_sigs_0_12_port);
U6259 : inv port map( inb => mult_125_A1_11_port, outb => n5687);
U6260 : inv port map( inb => n5688, outb => multiplier_sigs_0_13_port);
U6261 : inv port map( inb => mult_125_A1_12_port, outb => n5689);
U6262 : inv port map( inb => n5690, outb => multiplier_sigs_0_14_port);
U6263 : inv port map( inb => mult_125_A1_13_port, outb => n5691);
U6264 : inv port map( inb => n5692, outb => multiplier_sigs_0_15_port);
U6265 : inv port map( inb => mult_125_A1_14_port, outb => n5693);
U6266 : inv port map( inb => mult_125_A2_14_port, outb => n5694);
U6267 : inv port map( inb => n5695, outb => multiplier_sigs_0_16_port);
U6268 : inv port map( inb => mult_125_A1_15_port, outb => n5696);
U6269 : inv port map( inb => mult_125_A2_15_port, outb => n5697);
U6270 : inv port map( inb => n5698, outb => mult_125_FS_1_PG_int_0_3_3_port)
;
U6271 : inv port map( inb => mult_125_FS_1_TEMP_G_0_3_2_port, outb => n5699)
;
U6272 : inv port map( inb => mult_125_FS_1_P_0_3_3_port, outb => n5700);
U6273 : inv port map( inb => mult_125_A1_16_port, outb => n5701);
U6274 : inv port map( inb => mult_125_A2_16_port, outb => n5702);
U6275 : inv port map( inb => n5703, outb => mult_125_FS_1_PG_int_0_4_0_port)
;
U6276 : inv port map( inb => mult_125_A1_17_port, outb => n5704);
U6277 : inv port map( inb => mult_125_A2_17_port, outb => n5705);
U6278 : inv port map( inb => n5706, outb => mult_125_FS_1_PG_int_0_4_1_port)
;
U6279 : inv port map( inb => n5707, outb => mult_125_FS_1_TEMP_P_0_4_1_port)
;
U6280 : inv port map( inb => mult_125_FS_1_TEMP_P_0_4_0_port, outb => n5708)
;
U6281 : inv port map( inb => mult_125_A1_18_port, outb => n5709);
U6282 : inv port map( inb => mult_125_A2_18_port, outb => n5710);
U6283 : inv port map( inb => n5711, outb => mult_125_FS_1_PG_int_0_4_2_port)
;
U6284 : inv port map( inb => n5712, outb => mult_125_FS_1_TEMP_P_0_4_2_port)
;
U6285 : inv port map( inb => mult_125_FS_1_TEMP_G_0_4_1_port, outb => n5713)
;
U6286 : inv port map( inb => mult_125_FS_1_C_1_4_1_port, outb => n5714);
U6287 : inv port map( inb => mult_125_FS_1_P_0_4_1_port, outb => n5715);
U6288 : inv port map( inb => mult_125_A1_19_port, outb => n5716);
U6289 : inv port map( inb => mult_125_A2_19_port, outb => n5717);
U6290 : inv port map( inb => n5718, outb => mult_125_FS_1_PG_int_0_4_3_port)
;
U6291 : inv port map( inb => mult_125_FS_1_TEMP_G_0_4_2_port, outb => n5719)
;
U6292 : inv port map( inb => mult_125_FS_1_P_0_4_3_port, outb => n5720);
U6293 : inv port map( inb => mult_125_FS_1_C_1_4_2_port, outb => n5721);
U6294 : inv port map( inb => mult_125_FS_1_P_0_4_2_port, outb => n5722);
U6295 : inv port map( inb => mult_125_A1_20_port, outb => n5723);
U6296 : inv port map( inb => mult_125_A2_20_port, outb => n5724);
U6297 : inv port map( inb => n5725, outb => mult_125_FS_1_PG_int_0_5_0_port)
;
U6298 : inv port map( inb => mult_125_A1_21_port, outb => n5726);
U6299 : inv port map( inb => mult_125_A2_21_port, outb => n5727);
U6300 : inv port map( inb => n5728, outb => mult_125_FS_1_PG_int_0_5_1_port)
;
U6301 : inv port map( inb => n5729, outb => mult_125_FS_1_TEMP_P_0_5_1_port)
;
U6302 : inv port map( inb => mult_125_FS_1_TEMP_P_0_5_0_port, outb => n5730)
;
U6303 : inv port map( inb => mult_125_A1_22_port, outb => n5731);
U6304 : inv port map( inb => mult_125_A2_22_port, outb => n5732);
U6305 : inv port map( inb => n5733, outb => mult_125_FS_1_PG_int_0_5_2_port)
;
U6306 : inv port map( inb => n5734, outb => mult_125_FS_1_TEMP_P_0_5_2_port)
;
U6307 : inv port map( inb => mult_125_FS_1_TEMP_G_0_5_1_port, outb => n5735)
;
U6308 : inv port map( inb => mult_125_FS_1_C_1_5_1_port, outb => n5736);
U6309 : inv port map( inb => mult_125_FS_1_P_0_5_1_port, outb => n5737);
U6310 : inv port map( inb => mult_125_A1_23_port, outb => n5738);
U6311 : inv port map( inb => mult_125_A2_23_port, outb => n5739);
U6312 : inv port map( inb => n5740, outb => mult_125_FS_1_PG_int_0_5_3_port)
;
U6313 : inv port map( inb => mult_125_FS_1_TEMP_G_0_5_2_port, outb => n5741)
;
U6314 : inv port map( inb => mult_125_FS_1_P_0_5_3_port, outb => n5742);
U6315 : inv port map( inb => mult_125_FS_1_C_1_5_2_port, outb => n5743);
U6316 : inv port map( inb => mult_125_FS_1_P_0_5_2_port, outb => n5744);
U6317 : inv port map( inb => mult_125_A1_24_port, outb => n5745);
U6318 : inv port map( inb => mult_125_A2_24_port, outb => n5746);
U6319 : inv port map( inb => n5747, outb => mult_125_FS_1_PG_int_0_6_0_port)
;
U6320 : inv port map( inb => mult_125_A1_25_port, outb => n5748);
U6321 : inv port map( inb => mult_125_A2_25_port, outb => n5749);
U6322 : inv port map( inb => n5750, outb => mult_125_FS_1_PG_int_0_6_1_port)
;
U6323 : inv port map( inb => n5751, outb => mult_125_FS_1_TEMP_P_0_6_1_port)
;
U6324 : inv port map( inb => mult_125_FS_1_TEMP_P_0_6_0_port, outb => n5752)
;
U6325 : inv port map( inb => mult_125_A1_26_port, outb => n5753);
U6326 : inv port map( inb => mult_125_A2_26_port, outb => n5754);
U6327 : inv port map( inb => n5755, outb => mult_125_FS_1_PG_int_0_6_2_port)
;
U6328 : inv port map( inb => n5756, outb => mult_125_FS_1_TEMP_P_0_6_2_port)
;
U6329 : inv port map( inb => mult_125_FS_1_TEMP_G_0_6_1_port, outb => n5757)
;
U6330 : inv port map( inb => mult_125_FS_1_C_1_6_1_port, outb => n5758);
U6331 : inv port map( inb => mult_125_FS_1_P_0_6_1_port, outb => n5759);
U6332 : inv port map( inb => mult_125_A1_27_port, outb => n5760);
U6333 : inv port map( inb => mult_125_A2_27_port, outb => n5761);
U6334 : inv port map( inb => n5762, outb => mult_125_FS_1_PG_int_0_6_3_port)
;
U6335 : inv port map( inb => mult_125_FS_1_TEMP_G_0_6_2_port, outb => n5763)
;
U6336 : inv port map( inb => mult_125_FS_1_P_0_6_3_port, outb => n5764);
U6337 : inv port map( inb => mult_125_FS_1_C_1_6_2_port, outb => n5765);
U6338 : inv port map( inb => mult_125_FS_1_P_0_6_2_port, outb => n5766);
U6339 : inv port map( inb => mult_125_A1_28_port, outb => n5767);
U6340 : inv port map( inb => mult_125_A2_28_port, outb => n5768);
U6341 : inv port map( inb => n5769, outb => mult_125_FS_1_PG_int_0_7_0_port)
;
U6342 : inv port map( inb => mult_125_A1_29_port, outb => n5770);
U6343 : inv port map( inb => mult_125_A2_29_port, outb => n5771);
U6344 : inv port map( inb => n5772, outb => mult_125_FS_1_PG_int_0_7_1_port)
;
U6345 : inv port map( inb => mult_125_FS_1_C_1_7_0_port, outb => n5773);
U6346 : inv port map( inb => mult_125_FS_1_TEMP_P_0_7_0_port, outb => n5774)
;
U6347 : inv port map( inb => mult_125_FS_1_G_1_0_3_port, outb => n5775);
U6348 : inv port map( inb => mult_125_FS_1_C_1_4_0_port, outb => n5776);
U6349 : inv port map( inb => mult_125_FS_1_G_1_1_0_port, outb => n5778);
U6350 : inv port map( inb => mult_125_FS_1_C_1_5_0_port, outb => n5779);
U6351 : inv port map( inb => mult_125_FS_1_G_1_1_1_port, outb => n5781);
U6352 : inv port map( inb => mult_125_FS_1_C_1_6_0_port, outb => n5782);
U6353 : inv port map( inb => mult_125_FS_1_G_1_1_2_port, outb => n5784);
U6354 : inv port map( inb => mult_125_FS_1_G_2_0_0_port, outb => n5785);
U6355 : inv port map( inb => n5786, outb => mult_125_G2_ZB);
U6356 : inv port map( inb => n5787, outb => mult_125_G2_ZA);
U6357 : inv port map( inb => n5788, outb => mult_125_G2_QB);
U6358 : inv port map( inb => n5789, outb => mult_125_G2_QA);
U6359 : inv port map( inb => mult_125_G2_A1_0_port, outb => n5790);
U6360 : inv port map( inb => n5791, outb => multiplier_sigs_1_2_port);
U6361 : inv port map( inb => mult_125_G2_A1_1_port, outb => n5792);
U6362 : inv port map( inb => n5793, outb => multiplier_sigs_1_3_port);
U6363 : inv port map( inb => mult_125_G2_A1_2_port, outb => n5794);
U6364 : inv port map( inb => n5795, outb => multiplier_sigs_1_4_port);
U6365 : inv port map( inb => mult_125_G2_A1_3_port, outb => n5796);
U6366 : inv port map( inb => n5797, outb => multiplier_sigs_1_5_port);
U6367 : inv port map( inb => mult_125_G2_A1_4_port, outb => n5798);
U6368 : inv port map( inb => n5799, outb => multiplier_sigs_1_6_port);
U6369 : inv port map( inb => mult_125_G2_A1_5_port, outb => n5800);
U6370 : inv port map( inb => n5801, outb => multiplier_sigs_1_7_port);
U6371 : inv port map( inb => mult_125_G2_A1_6_port, outb => n5802);
U6372 : inv port map( inb => n5803, outb => multiplier_sigs_1_8_port);
U6373 : inv port map( inb => mult_125_G2_A1_7_port, outb => n5804);
U6374 : inv port map( inb => n5805, outb => multiplier_sigs_1_9_port);
U6375 : inv port map( inb => mult_125_G2_A1_8_port, outb => n5806);
U6376 : inv port map( inb => n5807, outb => multiplier_sigs_1_10_port);
U6377 : inv port map( inb => mult_125_G2_A1_9_port, outb => n5808);
U6378 : inv port map( inb => n5809, outb => multiplier_sigs_1_11_port);
U6379 : inv port map( inb => mult_125_G2_A1_10_port, outb => n5810);
U6380 : inv port map( inb => n5811, outb => multiplier_sigs_1_12_port);
U6381 : inv port map( inb => mult_125_G2_A1_11_port, outb => n5812);
U6382 : inv port map( inb => n5813, outb => multiplier_sigs_1_13_port);
U6383 : inv port map( inb => mult_125_G2_A1_12_port, outb => n5814);
U6384 : inv port map( inb => n5815, outb => multiplier_sigs_1_14_port);
U6385 : inv port map( inb => mult_125_G2_A1_13_port, outb => n5816);
U6386 : inv port map( inb => n5817, outb => multiplier_sigs_1_15_port);
U6387 : inv port map( inb => mult_125_G2_A1_14_port, outb => n5818);
U6388 : inv port map( inb => mult_125_G2_A2_14_port, outb => n5819);
U6389 : inv port map( inb => n5820, outb => multiplier_sigs_1_16_port);
U6390 : inv port map( inb => mult_125_G2_A1_15_port, outb => n5821);
U6391 : inv port map( inb => mult_125_G2_A2_15_port, outb => n5822);
U6392 : inv port map( inb => n5823, outb =>
mult_125_G2_FS_1_PG_int_0_3_3_port);
U6393 : inv port map( inb => mult_125_G2_FS_1_TEMP_G_0_3_2_port, outb =>
n5824);
U6394 : inv port map( inb => mult_125_G2_FS_1_P_0_3_3_port, outb => n5825);
U6395 : inv port map( inb => mult_125_G2_A1_16_port, outb => n5826);
U6396 : inv port map( inb => mult_125_G2_A2_16_port, outb => n5827);
U6397 : inv port map( inb => n5828, outb =>
mult_125_G2_FS_1_PG_int_0_4_0_port);
U6398 : inv port map( inb => mult_125_G2_A1_17_port, outb => n5829);
U6399 : inv port map( inb => mult_125_G2_A2_17_port, outb => n5830);
U6400 : inv port map( inb => n5831, outb =>
mult_125_G2_FS_1_PG_int_0_4_1_port);
U6401 : inv port map( inb => n5832, outb =>
mult_125_G2_FS_1_TEMP_P_0_4_1_port);
U6402 : inv port map( inb => mult_125_G2_FS_1_TEMP_P_0_4_0_port, outb =>
n5833);
U6403 : inv port map( inb => mult_125_G2_A1_18_port, outb => n5834);
U6404 : inv port map( inb => mult_125_G2_A2_18_port, outb => n5835);
U6405 : inv port map( inb => n5836, outb =>
mult_125_G2_FS_1_PG_int_0_4_2_port);
U6406 : inv port map( inb => n5837, outb =>
mult_125_G2_FS_1_TEMP_P_0_4_2_port);
U6407 : inv port map( inb => mult_125_G2_FS_1_TEMP_G_0_4_1_port, outb =>
n5838);
U6408 : inv port map( inb => mult_125_G2_FS_1_C_1_4_1_port, outb => n5839);
U6409 : inv port map( inb => mult_125_G2_FS_1_P_0_4_1_port, outb => n5840);
U6410 : inv port map( inb => mult_125_G2_A1_19_port, outb => n5841);
U6411 : inv port map( inb => mult_125_G2_A2_19_port, outb => n5842);
U6412 : inv port map( inb => n5843, outb =>
mult_125_G2_FS_1_PG_int_0_4_3_port);
U6413 : inv port map( inb => mult_125_G2_FS_1_TEMP_G_0_4_2_port, outb =>
n5844);
U6414 : inv port map( inb => mult_125_G2_FS_1_P_0_4_3_port, outb => n5845);
U6415 : inv port map( inb => mult_125_G2_FS_1_C_1_4_2_port, outb => n5846);
U6416 : inv port map( inb => mult_125_G2_FS_1_P_0_4_2_port, outb => n5847);
U6417 : inv port map( inb => mult_125_G2_A1_20_port, outb => n5848);
U6418 : inv port map( inb => mult_125_G2_A2_20_port, outb => n5849);
U6419 : inv port map( inb => n5850, outb =>
mult_125_G2_FS_1_PG_int_0_5_0_port);
U6420 : inv port map( inb => mult_125_G2_A1_21_port, outb => n5851);
U6421 : inv port map( inb => mult_125_G2_A2_21_port, outb => n5852);
U6422 : inv port map( inb => n5853, outb =>
mult_125_G2_FS_1_PG_int_0_5_1_port);
U6423 : inv port map( inb => n5854, outb =>
mult_125_G2_FS_1_TEMP_P_0_5_1_port);
U6424 : inv port map( inb => mult_125_G2_FS_1_TEMP_P_0_5_0_port, outb =>
n5855);
U6425 : inv port map( inb => mult_125_G2_A1_22_port, outb => n5856);
U6426 : inv port map( inb => mult_125_G2_A2_22_port, outb => n5857);
U6427 : inv port map( inb => n5858, outb =>
mult_125_G2_FS_1_PG_int_0_5_2_port);
U6428 : inv port map( inb => n5859, outb =>
mult_125_G2_FS_1_TEMP_P_0_5_2_port);
U6429 : inv port map( inb => mult_125_G2_FS_1_TEMP_G_0_5_1_port, outb =>
n5860);
U6430 : inv port map( inb => mult_125_G2_FS_1_C_1_5_1_port, outb => n5861);
U6431 : inv port map( inb => mult_125_G2_FS_1_P_0_5_1_port, outb => n5862);
U6432 : inv port map( inb => mult_125_G2_A1_23_port, outb => n5863);
U6433 : inv port map( inb => mult_125_G2_A2_23_port, outb => n5864);
U6434 : inv port map( inb => n5865, outb =>
mult_125_G2_FS_1_PG_int_0_5_3_port);
U6435 : inv port map( inb => mult_125_G2_FS_1_TEMP_G_0_5_2_port, outb =>
n5866);
U6436 : inv port map( inb => mult_125_G2_FS_1_P_0_5_3_port, outb => n5867);
U6437 : inv port map( inb => mult_125_G2_FS_1_C_1_5_2_port, outb => n5868);
U6438 : inv port map( inb => mult_125_G2_FS_1_P_0_5_2_port, outb => n5869);
U6439 : inv port map( inb => mult_125_G2_A1_24_port, outb => n5870);
U6440 : inv port map( inb => mult_125_G2_A2_24_port, outb => n5871);
U6441 : inv port map( inb => n5872, outb =>
mult_125_G2_FS_1_PG_int_0_6_0_port);
U6442 : inv port map( inb => mult_125_G2_A1_25_port, outb => n5873);
U6443 : inv port map( inb => mult_125_G2_A2_25_port, outb => n5874);
U6444 : inv port map( inb => n5875, outb =>
mult_125_G2_FS_1_PG_int_0_6_1_port);
U6445 : inv port map( inb => n5876, outb =>
mult_125_G2_FS_1_TEMP_P_0_6_1_port);
U6446 : inv port map( inb => mult_125_G2_FS_1_TEMP_P_0_6_0_port, outb =>
n5877);
U6447 : inv port map( inb => mult_125_G2_A1_26_port, outb => n5878);
U6448 : inv port map( inb => mult_125_G2_A2_26_port, outb => n5879);
U6449 : inv port map( inb => n5880, outb =>
mult_125_G2_FS_1_PG_int_0_6_2_port);
U6450 : inv port map( inb => n5881, outb =>
mult_125_G2_FS_1_TEMP_P_0_6_2_port);
U6451 : inv port map( inb => mult_125_G2_FS_1_TEMP_G_0_6_1_port, outb =>
n5882);
U6452 : inv port map( inb => mult_125_G2_FS_1_C_1_6_1_port, outb => n5883);
U6453 : inv port map( inb => mult_125_G2_FS_1_P_0_6_1_port, outb => n5884);
U6454 : inv port map( inb => mult_125_G2_A1_27_port, outb => n5885);
U6455 : inv port map( inb => mult_125_G2_A2_27_port, outb => n5886);
U6456 : inv port map( inb => n5887, outb =>
mult_125_G2_FS_1_PG_int_0_6_3_port);
U6457 : inv port map( inb => mult_125_G2_FS_1_TEMP_G_0_6_2_port, outb =>
n5888);
U6458 : inv port map( inb => mult_125_G2_FS_1_P_0_6_3_port, outb => n5889);
U6459 : inv port map( inb => mult_125_G2_FS_1_C_1_6_2_port, outb => n5890);
U6460 : inv port map( inb => mult_125_G2_FS_1_P_0_6_2_port, outb => n5891);
U6461 : inv port map( inb => mult_125_G2_A1_28_port, outb => n5892);
U6462 : inv port map( inb => mult_125_G2_A2_28_port, outb => n5893);
U6463 : inv port map( inb => n5894, outb =>
mult_125_G2_FS_1_PG_int_0_7_0_port);
U6464 : inv port map( inb => mult_125_G2_A1_29_port, outb => n5895);
U6465 : inv port map( inb => mult_125_G2_A2_29_port, outb => n5896);
U6466 : inv port map( inb => n5897, outb =>
mult_125_G2_FS_1_PG_int_0_7_1_port);
U6467 : inv port map( inb => mult_125_G2_FS_1_C_1_7_0_port, outb => n5898);
U6468 : inv port map( inb => mult_125_G2_FS_1_TEMP_P_0_7_0_port, outb =>
n5899);
U6469 : inv port map( inb => mult_125_G2_FS_1_G_1_0_3_port, outb => n5900);
U6470 : inv port map( inb => mult_125_G2_FS_1_C_1_4_0_port, outb => n5901);
U6471 : inv port map( inb => mult_125_G2_FS_1_G_1_1_0_port, outb => n5903);
U6472 : inv port map( inb => mult_125_G2_FS_1_C_1_5_0_port, outb => n5904);
U6473 : inv port map( inb => mult_125_G2_FS_1_G_1_1_1_port, outb => n5906);
U6474 : inv port map( inb => mult_125_G2_FS_1_C_1_6_0_port, outb => n5907);
U6475 : inv port map( inb => mult_125_G2_FS_1_G_1_1_2_port, outb => n5909);
U6476 : inv port map( inb => mult_125_G2_FS_1_G_2_0_0_port, outb => n5910);
U6477 : inv port map( inb => n5911, outb => mult_125_G3_ZB);
U6478 : inv port map( inb => n5912, outb => mult_125_G3_ZA);
U6479 : inv port map( inb => n5913, outb => mult_125_G3_QB);
U6480 : inv port map( inb => n5914, outb => mult_125_G3_QA);
U6481 : inv port map( inb => mult_125_G3_A1_0_port, outb => n5915);
U6482 : inv port map( inb => n5916, outb => multiplier_sigs_2_2_port);
U6483 : inv port map( inb => mult_125_G3_A1_1_port, outb => n5917);
U6484 : inv port map( inb => n5918, outb => multiplier_sigs_2_3_port);
U6485 : inv port map( inb => mult_125_G3_A1_2_port, outb => n5919);
U6486 : inv port map( inb => n5920, outb => multiplier_sigs_2_4_port);
U6487 : inv port map( inb => mult_125_G3_A1_3_port, outb => n5921);
U6488 : inv port map( inb => n5922, outb => multiplier_sigs_2_5_port);
U6489 : inv port map( inb => mult_125_G3_A1_4_port, outb => n5923);
U6490 : inv port map( inb => n5924, outb => multiplier_sigs_2_6_port);
U6491 : inv port map( inb => mult_125_G3_A1_5_port, outb => n5925);
U6492 : inv port map( inb => n5926, outb => multiplier_sigs_2_7_port);
U6493 : inv port map( inb => mult_125_G3_A1_6_port, outb => n5927);
U6494 : inv port map( inb => n5928, outb => multiplier_sigs_2_8_port);
U6495 : inv port map( inb => mult_125_G3_A1_7_port, outb => n5929);
U6496 : inv port map( inb => n5930, outb => multiplier_sigs_2_9_port);
U6497 : inv port map( inb => mult_125_G3_A1_8_port, outb => n5931);
U6498 : inv port map( inb => n5932, outb => multiplier_sigs_2_10_port);
U6499 : inv port map( inb => mult_125_G3_A1_9_port, outb => n5933);
U6500 : inv port map( inb => n5934, outb => multiplier_sigs_2_11_port);
U6501 : inv port map( inb => mult_125_G3_A1_10_port, outb => n5935);
U6502 : inv port map( inb => n5936, outb => multiplier_sigs_2_12_port);
U6503 : inv port map( inb => mult_125_G3_A1_11_port, outb => n5937);
U6504 : inv port map( inb => n5938, outb => multiplier_sigs_2_13_port);
U6505 : inv port map( inb => mult_125_G3_A1_12_port, outb => n5939);
U6506 : inv port map( inb => n5940, outb => multiplier_sigs_2_14_port);
U6507 : inv port map( inb => mult_125_G3_A1_13_port, outb => n5941);
U6508 : inv port map( inb => n5942, outb => multiplier_sigs_2_15_port);
U6509 : inv port map( inb => mult_125_G3_A1_14_port, outb => n5943);
U6510 : inv port map( inb => mult_125_G3_A2_14_port, outb => n5944);
U6511 : inv port map( inb => n5945, outb => multiplier_sigs_2_16_port);
U6512 : inv port map( inb => mult_125_G3_A1_15_port, outb => n5946);
U6513 : inv port map( inb => mult_125_G3_A2_15_port, outb => n5947);
U6514 : inv port map( inb => n5948, outb =>
mult_125_G3_FS_1_PG_int_0_3_3_port);
U6515 : inv port map( inb => mult_125_G3_FS_1_TEMP_G_0_3_2_port, outb =>
n5949);
U6516 : inv port map( inb => mult_125_G3_FS_1_P_0_3_3_port, outb => n5950);
U6517 : inv port map( inb => mult_125_G3_A1_16_port, outb => n5951);
U6518 : inv port map( inb => mult_125_G3_A2_16_port, outb => n5952);
U6519 : inv port map( inb => n5953, outb =>
mult_125_G3_FS_1_PG_int_0_4_0_port);
U6520 : inv port map( inb => mult_125_G3_A1_17_port, outb => n5954);
U6521 : inv port map( inb => mult_125_G3_A2_17_port, outb => n5955);
U6522 : inv port map( inb => n5956, outb =>
mult_125_G3_FS_1_PG_int_0_4_1_port);
U6523 : inv port map( inb => n5957, outb =>
mult_125_G3_FS_1_TEMP_P_0_4_1_port);
U6524 : inv port map( inb => mult_125_G3_FS_1_TEMP_P_0_4_0_port, outb =>
n5958);
U6525 : inv port map( inb => mult_125_G3_A1_18_port, outb => n5959);
U6526 : inv port map( inb => mult_125_G3_A2_18_port, outb => n5960);
U6527 : inv port map( inb => n5961, outb =>
mult_125_G3_FS_1_PG_int_0_4_2_port);
U6528 : inv port map( inb => n5962, outb =>
mult_125_G3_FS_1_TEMP_P_0_4_2_port);
U6529 : inv port map( inb => mult_125_G3_FS_1_TEMP_G_0_4_1_port, outb =>
n5963);
U6530 : inv port map( inb => mult_125_G3_FS_1_C_1_4_1_port, outb => n5964);
U6531 : inv port map( inb => mult_125_G3_FS_1_P_0_4_1_port, outb => n5965);
U6532 : inv port map( inb => mult_125_G3_A1_19_port, outb => n5966);
U6533 : inv port map( inb => mult_125_G3_A2_19_port, outb => n5967);
U6534 : inv port map( inb => n5968, outb =>
mult_125_G3_FS_1_PG_int_0_4_3_port);
U6535 : inv port map( inb => mult_125_G3_FS_1_TEMP_G_0_4_2_port, outb =>
n5969);
U6536 : inv port map( inb => mult_125_G3_FS_1_P_0_4_3_port, outb => n5970);
U6537 : inv port map( inb => mult_125_G3_FS_1_C_1_4_2_port, outb => n5971);
U6538 : inv port map( inb => mult_125_G3_FS_1_P_0_4_2_port, outb => n5972);
U6539 : inv port map( inb => mult_125_G3_A1_20_port, outb => n5973);
U6540 : inv port map( inb => mult_125_G3_A2_20_port, outb => n5974);
U6541 : inv port map( inb => n5975, outb =>
mult_125_G3_FS_1_PG_int_0_5_0_port);
U6542 : inv port map( inb => mult_125_G3_A1_21_port, outb => n5976);
U6543 : inv port map( inb => mult_125_G3_A2_21_port, outb => n5977);
U6544 : inv port map( inb => n5978, outb =>
mult_125_G3_FS_1_PG_int_0_5_1_port);
U6545 : inv port map( inb => n5979, outb =>
mult_125_G3_FS_1_TEMP_P_0_5_1_port);
U6546 : inv port map( inb => mult_125_G3_FS_1_TEMP_P_0_5_0_port, outb =>
n5980);
U6547 : inv port map( inb => mult_125_G3_A1_22_port, outb => n5981);
U6548 : inv port map( inb => mult_125_G3_A2_22_port, outb => n5982);
U6549 : inv port map( inb => n5983, outb =>
mult_125_G3_FS_1_PG_int_0_5_2_port);
U6550 : inv port map( inb => n5984, outb =>
mult_125_G3_FS_1_TEMP_P_0_5_2_port);
U6551 : inv port map( inb => mult_125_G3_FS_1_TEMP_G_0_5_1_port, outb =>
n5985);
U6552 : inv port map( inb => mult_125_G3_FS_1_C_1_5_1_port, outb => n5986);
U6553 : inv port map( inb => mult_125_G3_FS_1_P_0_5_1_port, outb => n5987);
U6554 : inv port map( inb => mult_125_G3_A1_23_port, outb => n5988);
U6555 : inv port map( inb => mult_125_G3_A2_23_port, outb => n5989);
U6556 : inv port map( inb => n5990, outb =>
mult_125_G3_FS_1_PG_int_0_5_3_port);
U6557 : inv port map( inb => mult_125_G3_FS_1_TEMP_G_0_5_2_port, outb =>
n5991);
U6558 : inv port map( inb => mult_125_G3_FS_1_P_0_5_3_port, outb => n5992);
U6559 : inv port map( inb => mult_125_G3_FS_1_C_1_5_2_port, outb => n5993);
U6560 : inv port map( inb => mult_125_G3_FS_1_P_0_5_2_port, outb => n5994);
U6561 : inv port map( inb => mult_125_G3_A1_24_port, outb => n5995);
U6562 : inv port map( inb => mult_125_G3_A2_24_port, outb => n5996);
U6563 : inv port map( inb => n5997, outb =>
mult_125_G3_FS_1_PG_int_0_6_0_port);
U6564 : inv port map( inb => mult_125_G3_A1_25_port, outb => n5998);
U6565 : inv port map( inb => mult_125_G3_A2_25_port, outb => n5999);
U6566 : inv port map( inb => n6000, outb =>
mult_125_G3_FS_1_PG_int_0_6_1_port);
U6567 : inv port map( inb => n6001, outb =>
mult_125_G3_FS_1_TEMP_P_0_6_1_port);
U6568 : inv port map( inb => mult_125_G3_FS_1_TEMP_P_0_6_0_port, outb =>
n6002);
U6569 : inv port map( inb => mult_125_G3_A1_26_port, outb => n6003);
U6570 : inv port map( inb => mult_125_G3_A2_26_port, outb => n6004);
U6571 : inv port map( inb => n6005, outb =>
mult_125_G3_FS_1_PG_int_0_6_2_port);
U6572 : inv port map( inb => n6006, outb =>
mult_125_G3_FS_1_TEMP_P_0_6_2_port);
U6573 : inv port map( inb => mult_125_G3_FS_1_TEMP_G_0_6_1_port, outb =>
n6007);
U6574 : inv port map( inb => mult_125_G3_FS_1_C_1_6_1_port, outb => n6008);
U6575 : inv port map( inb => mult_125_G3_FS_1_P_0_6_1_port, outb => n6009);
U6576 : inv port map( inb => mult_125_G3_A1_27_port, outb => n6010);
U6577 : inv port map( inb => mult_125_G3_A2_27_port, outb => n6011);
U6578 : inv port map( inb => n6012, outb =>
mult_125_G3_FS_1_PG_int_0_6_3_port);
U6579 : inv port map( inb => mult_125_G3_FS_1_TEMP_G_0_6_2_port, outb =>
n6013);
U6580 : inv port map( inb => mult_125_G3_FS_1_P_0_6_3_port, outb => n6014);
U6581 : inv port map( inb => mult_125_G3_FS_1_C_1_6_2_port, outb => n6015);
U6582 : inv port map( inb => mult_125_G3_FS_1_P_0_6_2_port, outb => n6016);
U6583 : inv port map( inb => mult_125_G3_A1_28_port, outb => n6017);
U6584 : inv port map( inb => mult_125_G3_A2_28_port, outb => n6018);
U6585 : inv port map( inb => n6019, outb =>
mult_125_G3_FS_1_PG_int_0_7_0_port);
U6586 : inv port map( inb => mult_125_G3_A1_29_port, outb => n6020);
U6587 : inv port map( inb => mult_125_G3_A2_29_port, outb => n6021);
U6588 : inv port map( inb => n6022, outb =>
mult_125_G3_FS_1_PG_int_0_7_1_port);
U6589 : inv port map( inb => mult_125_G3_FS_1_C_1_7_0_port, outb => n6023);
U6590 : inv port map( inb => mult_125_G3_FS_1_TEMP_P_0_7_0_port, outb =>
n6024);
U6591 : inv port map( inb => mult_125_G3_FS_1_G_1_0_3_port, outb => n6025);
U6592 : inv port map( inb => mult_125_G3_FS_1_C_1_4_0_port, outb => n6026);
U6593 : inv port map( inb => mult_125_G3_FS_1_G_1_1_0_port, outb => n6028);
U6594 : inv port map( inb => mult_125_G3_FS_1_C_1_5_0_port, outb => n6029);
U6595 : inv port map( inb => mult_125_G3_FS_1_G_1_1_1_port, outb => n6031);
U6596 : inv port map( inb => mult_125_G3_FS_1_C_1_6_0_port, outb => n6032);
U6597 : inv port map( inb => mult_125_G3_FS_1_G_1_1_2_port, outb => n6034);
U6598 : inv port map( inb => mult_125_G3_FS_1_G_2_0_0_port, outb => n6035);
end SYN_fir_rtl_arch;
| mit | e30da3c5c351862c2024a68b101cf098 | 0.497127 | 2.653507 | false | false | false | false |
Feuerwerk/fpgaNES | i2c.vhd | 1 | 9,105 | /*
This file is part of fpgaNES.
fpgaNES is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.
fpgaNES is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with fpgaNES. If not, see <http://www.gnu.org/licenses/>.
*/
-- inspired by http://opencores.org/project,i2c
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity i2c is
generic
(
input_clk : integer := 50_000_000; -- input clock speed from user logic in Hz
bus_clk : integer := 400_000 -- speed the i2c bus (scl) will run at in Hz
);
port
(
i_clk : in std_logic;
i_reset_n : in std_logic;
i_enable : in std_logic;
i_flag : in std_logic;
i_start_condition : in std_logic;
i_stop_condition : in std_logic;
i_enable_ack : in std_logic;
i_data : in std_logic_vector(7 downto 0);
io_sda : inout std_logic;
io_scl : inout std_logic;
o_q : out std_logic_vector(7 downto 0);
o_status : out std_logic_vector(4 downto 0);
o_busy : out std_logic;
o_ack_error : out std_logic
);
end i2c;
architecture behavioral of i2c is
constant divider: integer := (input_clk / bus_clk) / 4; --number of clocks in 1/4 cycle of scl
type state_t is (starting1, starting2, started, restarting1, restarting2, write_addr_for_read, write_addr_for_write, await_ack1, await_ack2, await_ack3, await_ack4, await_ack5, await_ack6, write_ack1, write_ack2, addr_written_for_write, addr_written_for_read, read_data, prepare_read, write_data, stopping1, stopping2, stopped);
signal s_state : state_t := stopped;
signal s_data_clk : std_logic;
signal s_data_clk_prev : std_logic;
signal s_scl_clk : std_logic;
signal s_sda : std_logic := '1';
signal s_scl : std_logic := '1';
signal s_scl_enable : std_logic := '0';
signal s_scl_int : std_logic;
signal s_busy : std_logic;
signal s_ack : std_logic := '0';
signal s_buffer : std_logic_vector(7 downto 0);
signal s_q : std_logic_vector(7 downto 0) := x"00";
signal s_index : integer range 0 to 7 := 7;
signal s_stretch : std_logic := '0';
signal s_status : std_logic_vector(4 downto 0) := "00000";
signal s_ack_error :std_logic := '0';
begin
-- generate the timing for the bus clock (s_scl_clk) and the data clock (data_clk)
process (i_clk)
variable count: integer range 0 to divider * 4; -- timing for clock generation
begin
if rising_edge(i_clk) then
if i_reset_n = '0' then -- reset asserted
s_stretch <= '0';
count := 0;
else
s_data_clk_prev <= s_data_clk;
if count = divider * 4 - 1 then -- end of timing cycle
count := 0; -- reset timer
elsif s_stretch = '0' then -- clock stretching from slave not detected
count := count + 1; -- continue clock generation timing
end if;
case count is
when 0 to divider - 1 => -- first 1/4 cycle of clocking
s_scl_clk <= '0';
s_data_clk <= '0';
when divider to divider * 2 - 1 => -- second 1/4 cycle of clocking
s_scl_clk <= '0';
s_data_clk <= '1';
when divider * 2 to divider * 3 - 1 => -- third 1/4 cycle of clocking
s_scl_clk <= '1'; -- release scl
/*
if io_scl = '0' then -- detect if slave is stretching clock
s_stretch <= '1';
else
s_stretch <= '0';
end if;
*/
s_stretch <= '0';
s_data_clk <= '1';
when others => -- last 1/4 cycle of clocking
s_scl_clk <= '1';
s_data_clk <= '0';
end case;
end if;
end if;
end process;
process (i_clk)
begin
if rising_edge(i_clk) then
if i_reset_n = '0' then
s_sda <= '1';
s_scl <= '1';
s_state <= stopped;
s_scl_enable <= '0';
s_ack_error <= '0';
else
if i_flag = '1' then
if s_busy = '0' then
if i_start_condition = '1' then
case s_state is
when stopped =>
s_state <= starting1;
when others =>
s_state <= restarting1;
end case;
elsif i_stop_condition = '1' then
s_state <= stopping1;
else
case s_state is
when started =>
if i_data(0) = '1' then
s_state <= write_addr_for_read;
else
s_state <= write_addr_for_write;
end if;
s_buffer <= i_data;
s_index <= 7;
when addr_written_for_write =>
s_state <= write_data;
s_buffer <= i_data;
s_index <= 7;
when addr_written_for_read =>
s_state <= prepare_read;
s_ack <= i_enable_ack;
when others =>
null;
end case;
end if;
end if;
end if;
if (s_data_clk = '1') and (s_data_clk_prev = '0') then
case s_state is
when starting2 =>
s_scl <= '0';
s_scl_enable <= '0';
s_state <= started;
s_status <= "00001";
when restarting1 =>
s_sda <= '1';
s_scl_enable <= '1';
s_state <= restarting2;
when restarting2 =>
s_scl <= '0';
s_scl_enable <= '0';
s_state <= started;
s_status <= "00010";
when stopping1 =>
s_sda <= '0';
s_scl_enable <= '1';
s_state <= stopping2;
when write_addr_for_read =>
s_scl_enable <= '1';
s_sda <= s_buffer(s_index);
if s_index = 0 then
s_state <= await_ack5;
else
s_index <= s_index - 1;
end if;
when write_addr_for_write =>
s_scl_enable <= '1';
s_sda <= s_buffer(s_index);
if s_index = 0 then
s_state <= await_ack1;
else
s_index <= s_index - 1;
end if;
when write_data =>
s_scl_enable <= '1';
s_sda <= s_buffer(s_index);
if s_index = 0 then
s_state <= await_ack3;
else
s_index <= s_index - 1;
end if;
when await_ack1 =>
s_sda <= '1';
s_state <= await_ack2;
when await_ack2 =>
s_sda <= '0';
s_scl <= '0';
s_scl_enable <= '0';
s_state <= addr_written_for_write;
when await_ack3 =>
s_sda <= '1';
s_state <= await_ack4;
when await_ack4 =>
s_sda <= '0';
s_scl <= '0';
s_scl_enable <= '0';
s_state <= addr_written_for_write;
when await_ack5 =>
s_sda <= '1';
s_state <= await_ack6;
when await_ack6 =>
s_sda <= '0';
s_scl <= '0';
s_scl_enable <= '0';
s_state <= addr_written_for_read;
when prepare_read =>
s_index <= 7;
s_sda <= '1';
s_scl_enable <= '1';
s_state <= read_data;
when write_ack1 =>
s_sda <= not s_ack;
s_state <= write_ack2;
when write_ack2 =>
s_sda <= '0';
s_scl <= '0';
s_scl_enable <= '0';
s_state <= addr_written_for_read;
s_status <= "0101" & not s_ack;
when others =>
null;
end case;
elsif (s_data_clk = '0') and (s_data_clk_prev = '1') then
case s_state is
when starting1 =>
s_sda <= '0';
s_scl_enable <= '1';
s_state <= starting2;
when restarting2 =>
s_sda <= '0';
when stopping2 =>
s_sda <= '1';
s_scl <= '1';
s_scl_enable <= '0';
s_state <= stopped;
s_status <= "00000";
when await_ack2 =>
s_status <= "00" & io_sda & not io_sda & not io_sda;
if io_sda = '1' then
s_ack_error <= '1';
end if;
when await_ack4 =>
s_status <= "001" & io_sda & not io_sda;
if io_sda = '1' then
s_ack_error <= '1';
end if;
when await_ack6 =>
s_status <= "0100" & io_sda;
if io_sda = '1' then
s_ack_error <= '1';
end if;
when read_data =>
if s_index = 0 then
s_state <= write_ack1;
else
s_index <= s_index - 1;
end if;
s_q <= s_q(6 downto 0) & io_sda;
when others =>
null;
end case;
end if;
end if;
if s_scl_enable = '1' then
s_scl_int <= s_scl_clk;
else
s_scl_int <= s_scl;
end if;
end if;
end process;
with s_state select s_busy <=
'0' when started,
'0' when stopped,
'0' when addr_written_for_read,
'0' when addr_written_for_write,
'1' when others;
o_q <= s_q;
o_status <= s_status;
o_ack_error <= s_ack_error;
o_busy <= s_busy;
io_scl <= '0' when (s_scl_int = '0') and (i_enable = '1') else 'Z';
io_sda <= '0' when (s_sda = '0') and (i_enable = '1') else 'Z';
end behavioral;
| gpl-3.0 | 7681a69f75d6c5ce1f84f56c50e05061 | 0.523229 | 2.93048 | false | false | false | false |
varunnagpaal/Digital-Hardware-Modelling | xilinx-vivado/hls_tutorial_lab1/hls_tutorial_lab1.cache/ip/2018.2/ddc26209722952ee/zybo_zynq_design_processing_system7_0_0_sim_netlist.vhdl | 1 | 204,716 | -- Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2018.2 (win64) Build 2258646 Thu Jun 14 20:03:12 MDT 2018
-- Date : Sun Sep 22 02:34:37 2019
-- Host : varun-laptop running 64-bit Service Pack 1 (build 7601)
-- Command : write_vhdl -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
-- decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ zybo_zynq_design_processing_system7_0_0_sim_netlist.vhdl
-- Design : zybo_zynq_design_processing_system7_0_0
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7z010clg400-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 is
port (
CAN0_PHY_TX : out STD_LOGIC;
CAN0_PHY_RX : in STD_LOGIC;
CAN1_PHY_TX : out STD_LOGIC;
CAN1_PHY_RX : in STD_LOGIC;
ENET0_GMII_TX_EN : out STD_LOGIC;
ENET0_GMII_TX_ER : out STD_LOGIC;
ENET0_MDIO_MDC : out STD_LOGIC;
ENET0_MDIO_O : out STD_LOGIC;
ENET0_MDIO_T : out STD_LOGIC;
ENET0_PTP_DELAY_REQ_RX : out STD_LOGIC;
ENET0_PTP_DELAY_REQ_TX : out STD_LOGIC;
ENET0_PTP_PDELAY_REQ_RX : out STD_LOGIC;
ENET0_PTP_PDELAY_REQ_TX : out STD_LOGIC;
ENET0_PTP_PDELAY_RESP_RX : out STD_LOGIC;
ENET0_PTP_PDELAY_RESP_TX : out STD_LOGIC;
ENET0_PTP_SYNC_FRAME_RX : out STD_LOGIC;
ENET0_PTP_SYNC_FRAME_TX : out STD_LOGIC;
ENET0_SOF_RX : out STD_LOGIC;
ENET0_SOF_TX : out STD_LOGIC;
ENET0_GMII_TXD : out STD_LOGIC_VECTOR ( 7 downto 0 );
ENET0_GMII_COL : in STD_LOGIC;
ENET0_GMII_CRS : in STD_LOGIC;
ENET0_GMII_RX_CLK : in STD_LOGIC;
ENET0_GMII_RX_DV : in STD_LOGIC;
ENET0_GMII_RX_ER : in STD_LOGIC;
ENET0_GMII_TX_CLK : in STD_LOGIC;
ENET0_MDIO_I : in STD_LOGIC;
ENET0_EXT_INTIN : in STD_LOGIC;
ENET0_GMII_RXD : in STD_LOGIC_VECTOR ( 7 downto 0 );
ENET1_GMII_TX_EN : out STD_LOGIC;
ENET1_GMII_TX_ER : out STD_LOGIC;
ENET1_MDIO_MDC : out STD_LOGIC;
ENET1_MDIO_O : out STD_LOGIC;
ENET1_MDIO_T : out STD_LOGIC;
ENET1_PTP_DELAY_REQ_RX : out STD_LOGIC;
ENET1_PTP_DELAY_REQ_TX : out STD_LOGIC;
ENET1_PTP_PDELAY_REQ_RX : out STD_LOGIC;
ENET1_PTP_PDELAY_REQ_TX : out STD_LOGIC;
ENET1_PTP_PDELAY_RESP_RX : out STD_LOGIC;
ENET1_PTP_PDELAY_RESP_TX : out STD_LOGIC;
ENET1_PTP_SYNC_FRAME_RX : out STD_LOGIC;
ENET1_PTP_SYNC_FRAME_TX : out STD_LOGIC;
ENET1_SOF_RX : out STD_LOGIC;
ENET1_SOF_TX : out STD_LOGIC;
ENET1_GMII_TXD : out STD_LOGIC_VECTOR ( 7 downto 0 );
ENET1_GMII_COL : in STD_LOGIC;
ENET1_GMII_CRS : in STD_LOGIC;
ENET1_GMII_RX_CLK : in STD_LOGIC;
ENET1_GMII_RX_DV : in STD_LOGIC;
ENET1_GMII_RX_ER : in STD_LOGIC;
ENET1_GMII_TX_CLK : in STD_LOGIC;
ENET1_MDIO_I : in STD_LOGIC;
ENET1_EXT_INTIN : in STD_LOGIC;
ENET1_GMII_RXD : in STD_LOGIC_VECTOR ( 7 downto 0 );
GPIO_I : in STD_LOGIC_VECTOR ( 63 downto 0 );
GPIO_O : out STD_LOGIC_VECTOR ( 63 downto 0 );
GPIO_T : out STD_LOGIC_VECTOR ( 63 downto 0 );
I2C0_SDA_I : in STD_LOGIC;
I2C0_SDA_O : out STD_LOGIC;
I2C0_SDA_T : out STD_LOGIC;
I2C0_SCL_I : in STD_LOGIC;
I2C0_SCL_O : out STD_LOGIC;
I2C0_SCL_T : out STD_LOGIC;
I2C1_SDA_I : in STD_LOGIC;
I2C1_SDA_O : out STD_LOGIC;
I2C1_SDA_T : out STD_LOGIC;
I2C1_SCL_I : in STD_LOGIC;
I2C1_SCL_O : out STD_LOGIC;
I2C1_SCL_T : out STD_LOGIC;
PJTAG_TCK : in STD_LOGIC;
PJTAG_TMS : in STD_LOGIC;
PJTAG_TDI : in STD_LOGIC;
PJTAG_TDO : out STD_LOGIC;
SDIO0_CLK : out STD_LOGIC;
SDIO0_CLK_FB : in STD_LOGIC;
SDIO0_CMD_O : out STD_LOGIC;
SDIO0_CMD_I : in STD_LOGIC;
SDIO0_CMD_T : out STD_LOGIC;
SDIO0_DATA_I : in STD_LOGIC_VECTOR ( 3 downto 0 );
SDIO0_DATA_O : out STD_LOGIC_VECTOR ( 3 downto 0 );
SDIO0_DATA_T : out STD_LOGIC_VECTOR ( 3 downto 0 );
SDIO0_LED : out STD_LOGIC;
SDIO0_CDN : in STD_LOGIC;
SDIO0_WP : in STD_LOGIC;
SDIO0_BUSPOW : out STD_LOGIC;
SDIO0_BUSVOLT : out STD_LOGIC_VECTOR ( 2 downto 0 );
SDIO1_CLK : out STD_LOGIC;
SDIO1_CLK_FB : in STD_LOGIC;
SDIO1_CMD_O : out STD_LOGIC;
SDIO1_CMD_I : in STD_LOGIC;
SDIO1_CMD_T : out STD_LOGIC;
SDIO1_DATA_I : in STD_LOGIC_VECTOR ( 3 downto 0 );
SDIO1_DATA_O : out STD_LOGIC_VECTOR ( 3 downto 0 );
SDIO1_DATA_T : out STD_LOGIC_VECTOR ( 3 downto 0 );
SDIO1_LED : out STD_LOGIC;
SDIO1_CDN : in STD_LOGIC;
SDIO1_WP : in STD_LOGIC;
SDIO1_BUSPOW : out STD_LOGIC;
SDIO1_BUSVOLT : out STD_LOGIC_VECTOR ( 2 downto 0 );
SPI0_SCLK_I : in STD_LOGIC;
SPI0_SCLK_O : out STD_LOGIC;
SPI0_SCLK_T : out STD_LOGIC;
SPI0_MOSI_I : in STD_LOGIC;
SPI0_MOSI_O : out STD_LOGIC;
SPI0_MOSI_T : out STD_LOGIC;
SPI0_MISO_I : in STD_LOGIC;
SPI0_MISO_O : out STD_LOGIC;
SPI0_MISO_T : out STD_LOGIC;
SPI0_SS_I : in STD_LOGIC;
SPI0_SS_O : out STD_LOGIC;
SPI0_SS1_O : out STD_LOGIC;
SPI0_SS2_O : out STD_LOGIC;
SPI0_SS_T : out STD_LOGIC;
SPI1_SCLK_I : in STD_LOGIC;
SPI1_SCLK_O : out STD_LOGIC;
SPI1_SCLK_T : out STD_LOGIC;
SPI1_MOSI_I : in STD_LOGIC;
SPI1_MOSI_O : out STD_LOGIC;
SPI1_MOSI_T : out STD_LOGIC;
SPI1_MISO_I : in STD_LOGIC;
SPI1_MISO_O : out STD_LOGIC;
SPI1_MISO_T : out STD_LOGIC;
SPI1_SS_I : in STD_LOGIC;
SPI1_SS_O : out STD_LOGIC;
SPI1_SS1_O : out STD_LOGIC;
SPI1_SS2_O : out STD_LOGIC;
SPI1_SS_T : out STD_LOGIC;
UART0_DTRN : out STD_LOGIC;
UART0_RTSN : out STD_LOGIC;
UART0_TX : out STD_LOGIC;
UART0_CTSN : in STD_LOGIC;
UART0_DCDN : in STD_LOGIC;
UART0_DSRN : in STD_LOGIC;
UART0_RIN : in STD_LOGIC;
UART0_RX : in STD_LOGIC;
UART1_DTRN : out STD_LOGIC;
UART1_RTSN : out STD_LOGIC;
UART1_TX : out STD_LOGIC;
UART1_CTSN : in STD_LOGIC;
UART1_DCDN : in STD_LOGIC;
UART1_DSRN : in STD_LOGIC;
UART1_RIN : in STD_LOGIC;
UART1_RX : in STD_LOGIC;
TTC0_WAVE0_OUT : out STD_LOGIC;
TTC0_WAVE1_OUT : out STD_LOGIC;
TTC0_WAVE2_OUT : out STD_LOGIC;
TTC0_CLK0_IN : in STD_LOGIC;
TTC0_CLK1_IN : in STD_LOGIC;
TTC0_CLK2_IN : in STD_LOGIC;
TTC1_WAVE0_OUT : out STD_LOGIC;
TTC1_WAVE1_OUT : out STD_LOGIC;
TTC1_WAVE2_OUT : out STD_LOGIC;
TTC1_CLK0_IN : in STD_LOGIC;
TTC1_CLK1_IN : in STD_LOGIC;
TTC1_CLK2_IN : in STD_LOGIC;
WDT_CLK_IN : in STD_LOGIC;
WDT_RST_OUT : out STD_LOGIC;
TRACE_CLK : in STD_LOGIC;
TRACE_CTL : out STD_LOGIC;
TRACE_DATA : out STD_LOGIC_VECTOR ( 1 downto 0 );
TRACE_CLK_OUT : out STD_LOGIC;
USB0_PORT_INDCTL : out STD_LOGIC_VECTOR ( 1 downto 0 );
USB0_VBUS_PWRSELECT : out STD_LOGIC;
USB0_VBUS_PWRFAULT : in STD_LOGIC;
USB1_PORT_INDCTL : out STD_LOGIC_VECTOR ( 1 downto 0 );
USB1_VBUS_PWRSELECT : out STD_LOGIC;
USB1_VBUS_PWRFAULT : in STD_LOGIC;
SRAM_INTIN : in STD_LOGIC;
M_AXI_GP0_ARESETN : out STD_LOGIC;
M_AXI_GP0_ARVALID : out STD_LOGIC;
M_AXI_GP0_AWVALID : out STD_LOGIC;
M_AXI_GP0_BREADY : out STD_LOGIC;
M_AXI_GP0_RREADY : out STD_LOGIC;
M_AXI_GP0_WLAST : out STD_LOGIC;
M_AXI_GP0_WVALID : out STD_LOGIC;
M_AXI_GP0_ARID : out STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_AWID : out STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_WID : out STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_ARBURST : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_ARLOCK : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_ARSIZE : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP0_AWBURST : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_AWLOCK : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_AWSIZE : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP0_ARPROT : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP0_AWPROT : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP0_ARADDR : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_GP0_AWADDR : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_GP0_WDATA : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_GP0_ARCACHE : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_ARLEN : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_ARQOS : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_AWCACHE : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_AWLEN : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_AWQOS : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_WSTRB : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_ACLK : in STD_LOGIC;
M_AXI_GP0_ARREADY : in STD_LOGIC;
M_AXI_GP0_AWREADY : in STD_LOGIC;
M_AXI_GP0_BVALID : in STD_LOGIC;
M_AXI_GP0_RLAST : in STD_LOGIC;
M_AXI_GP0_RVALID : in STD_LOGIC;
M_AXI_GP0_WREADY : in STD_LOGIC;
M_AXI_GP0_BID : in STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_RID : in STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_BRESP : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_RRESP : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_RDATA : in STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_GP1_ARESETN : out STD_LOGIC;
M_AXI_GP1_ARVALID : out STD_LOGIC;
M_AXI_GP1_AWVALID : out STD_LOGIC;
M_AXI_GP1_BREADY : out STD_LOGIC;
M_AXI_GP1_RREADY : out STD_LOGIC;
M_AXI_GP1_WLAST : out STD_LOGIC;
M_AXI_GP1_WVALID : out STD_LOGIC;
M_AXI_GP1_ARID : out STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP1_AWID : out STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP1_WID : out STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP1_ARBURST : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP1_ARLOCK : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP1_ARSIZE : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP1_AWBURST : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP1_AWLOCK : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP1_AWSIZE : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP1_ARPROT : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP1_AWPROT : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP1_ARADDR : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_GP1_AWADDR : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_GP1_WDATA : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_GP1_ARCACHE : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP1_ARLEN : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP1_ARQOS : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP1_AWCACHE : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP1_AWLEN : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP1_AWQOS : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP1_WSTRB : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP1_ACLK : in STD_LOGIC;
M_AXI_GP1_ARREADY : in STD_LOGIC;
M_AXI_GP1_AWREADY : in STD_LOGIC;
M_AXI_GP1_BVALID : in STD_LOGIC;
M_AXI_GP1_RLAST : in STD_LOGIC;
M_AXI_GP1_RVALID : in STD_LOGIC;
M_AXI_GP1_WREADY : in STD_LOGIC;
M_AXI_GP1_BID : in STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP1_RID : in STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP1_BRESP : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP1_RRESP : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP1_RDATA : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_GP0_ARESETN : out STD_LOGIC;
S_AXI_GP0_ARREADY : out STD_LOGIC;
S_AXI_GP0_AWREADY : out STD_LOGIC;
S_AXI_GP0_BVALID : out STD_LOGIC;
S_AXI_GP0_RLAST : out STD_LOGIC;
S_AXI_GP0_RVALID : out STD_LOGIC;
S_AXI_GP0_WREADY : out STD_LOGIC;
S_AXI_GP0_BRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_GP0_RRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_GP0_RDATA : out STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_GP0_BID : out STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_GP0_RID : out STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_GP0_ACLK : in STD_LOGIC;
S_AXI_GP0_ARVALID : in STD_LOGIC;
S_AXI_GP0_AWVALID : in STD_LOGIC;
S_AXI_GP0_BREADY : in STD_LOGIC;
S_AXI_GP0_RREADY : in STD_LOGIC;
S_AXI_GP0_WLAST : in STD_LOGIC;
S_AXI_GP0_WVALID : in STD_LOGIC;
S_AXI_GP0_ARBURST : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_GP0_ARLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_GP0_ARSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_GP0_AWBURST : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_GP0_AWLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_GP0_AWSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_GP0_ARPROT : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_GP0_AWPROT : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_GP0_ARADDR : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_GP0_AWADDR : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_GP0_WDATA : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_GP0_ARCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_GP0_ARLEN : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_GP0_ARQOS : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_GP0_AWCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_GP0_AWLEN : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_GP0_AWQOS : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_GP0_WSTRB : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_GP0_ARID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_GP0_AWID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_GP0_WID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_GP1_ARESETN : out STD_LOGIC;
S_AXI_GP1_ARREADY : out STD_LOGIC;
S_AXI_GP1_AWREADY : out STD_LOGIC;
S_AXI_GP1_BVALID : out STD_LOGIC;
S_AXI_GP1_RLAST : out STD_LOGIC;
S_AXI_GP1_RVALID : out STD_LOGIC;
S_AXI_GP1_WREADY : out STD_LOGIC;
S_AXI_GP1_BRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_GP1_RRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_GP1_RDATA : out STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_GP1_BID : out STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_GP1_RID : out STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_GP1_ACLK : in STD_LOGIC;
S_AXI_GP1_ARVALID : in STD_LOGIC;
S_AXI_GP1_AWVALID : in STD_LOGIC;
S_AXI_GP1_BREADY : in STD_LOGIC;
S_AXI_GP1_RREADY : in STD_LOGIC;
S_AXI_GP1_WLAST : in STD_LOGIC;
S_AXI_GP1_WVALID : in STD_LOGIC;
S_AXI_GP1_ARBURST : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_GP1_ARLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_GP1_ARSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_GP1_AWBURST : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_GP1_AWLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_GP1_AWSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_GP1_ARPROT : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_GP1_AWPROT : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_GP1_ARADDR : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_GP1_AWADDR : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_GP1_WDATA : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_GP1_ARCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_GP1_ARLEN : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_GP1_ARQOS : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_GP1_AWCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_GP1_AWLEN : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_GP1_AWQOS : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_GP1_WSTRB : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_GP1_ARID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_GP1_AWID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_GP1_WID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_ACP_ARESETN : out STD_LOGIC;
S_AXI_ACP_ARREADY : out STD_LOGIC;
S_AXI_ACP_AWREADY : out STD_LOGIC;
S_AXI_ACP_BVALID : out STD_LOGIC;
S_AXI_ACP_RLAST : out STD_LOGIC;
S_AXI_ACP_RVALID : out STD_LOGIC;
S_AXI_ACP_WREADY : out STD_LOGIC;
S_AXI_ACP_BRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_ACP_RRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_ACP_BID : out STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_ACP_RID : out STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_ACP_RDATA : out STD_LOGIC_VECTOR ( 63 downto 0 );
S_AXI_ACP_ACLK : in STD_LOGIC;
S_AXI_ACP_ARVALID : in STD_LOGIC;
S_AXI_ACP_AWVALID : in STD_LOGIC;
S_AXI_ACP_BREADY : in STD_LOGIC;
S_AXI_ACP_RREADY : in STD_LOGIC;
S_AXI_ACP_WLAST : in STD_LOGIC;
S_AXI_ACP_WVALID : in STD_LOGIC;
S_AXI_ACP_ARID : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_ACP_ARPROT : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_ACP_AWID : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_ACP_AWPROT : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_ACP_WID : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_ACP_ARADDR : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_ACP_AWADDR : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_ACP_ARCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_ACP_ARLEN : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_ACP_ARQOS : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_ACP_AWCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_ACP_AWLEN : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_ACP_AWQOS : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_ACP_ARBURST : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_ACP_ARLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_ACP_ARSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_ACP_AWBURST : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_ACP_AWLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_ACP_AWSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_ACP_ARUSER : in STD_LOGIC_VECTOR ( 4 downto 0 );
S_AXI_ACP_AWUSER : in STD_LOGIC_VECTOR ( 4 downto 0 );
S_AXI_ACP_WDATA : in STD_LOGIC_VECTOR ( 63 downto 0 );
S_AXI_ACP_WSTRB : in STD_LOGIC_VECTOR ( 7 downto 0 );
S_AXI_HP0_ARESETN : out STD_LOGIC;
S_AXI_HP0_ARREADY : out STD_LOGIC;
S_AXI_HP0_AWREADY : out STD_LOGIC;
S_AXI_HP0_BVALID : out STD_LOGIC;
S_AXI_HP0_RLAST : out STD_LOGIC;
S_AXI_HP0_RVALID : out STD_LOGIC;
S_AXI_HP0_WREADY : out STD_LOGIC;
S_AXI_HP0_BRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP0_RRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP0_BID : out STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP0_RID : out STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP0_RDATA : out STD_LOGIC_VECTOR ( 63 downto 0 );
S_AXI_HP0_RCOUNT : out STD_LOGIC_VECTOR ( 7 downto 0 );
S_AXI_HP0_WCOUNT : out STD_LOGIC_VECTOR ( 7 downto 0 );
S_AXI_HP0_RACOUNT : out STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP0_WACOUNT : out STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP0_ACLK : in STD_LOGIC;
S_AXI_HP0_ARVALID : in STD_LOGIC;
S_AXI_HP0_AWVALID : in STD_LOGIC;
S_AXI_HP0_BREADY : in STD_LOGIC;
S_AXI_HP0_RDISSUECAP1_EN : in STD_LOGIC;
S_AXI_HP0_RREADY : in STD_LOGIC;
S_AXI_HP0_WLAST : in STD_LOGIC;
S_AXI_HP0_WRISSUECAP1_EN : in STD_LOGIC;
S_AXI_HP0_WVALID : in STD_LOGIC;
S_AXI_HP0_ARBURST : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP0_ARLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP0_ARSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP0_AWBURST : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP0_AWLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP0_AWSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP0_ARPROT : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP0_AWPROT : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP0_ARADDR : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_HP0_AWADDR : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_HP0_ARCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP0_ARLEN : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP0_ARQOS : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP0_AWCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP0_AWLEN : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP0_AWQOS : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP0_ARID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP0_AWID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP0_WID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP0_WDATA : in STD_LOGIC_VECTOR ( 63 downto 0 );
S_AXI_HP0_WSTRB : in STD_LOGIC_VECTOR ( 7 downto 0 );
S_AXI_HP1_ARESETN : out STD_LOGIC;
S_AXI_HP1_ARREADY : out STD_LOGIC;
S_AXI_HP1_AWREADY : out STD_LOGIC;
S_AXI_HP1_BVALID : out STD_LOGIC;
S_AXI_HP1_RLAST : out STD_LOGIC;
S_AXI_HP1_RVALID : out STD_LOGIC;
S_AXI_HP1_WREADY : out STD_LOGIC;
S_AXI_HP1_BRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP1_RRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP1_BID : out STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP1_RID : out STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP1_RDATA : out STD_LOGIC_VECTOR ( 63 downto 0 );
S_AXI_HP1_RCOUNT : out STD_LOGIC_VECTOR ( 7 downto 0 );
S_AXI_HP1_WCOUNT : out STD_LOGIC_VECTOR ( 7 downto 0 );
S_AXI_HP1_RACOUNT : out STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP1_WACOUNT : out STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP1_ACLK : in STD_LOGIC;
S_AXI_HP1_ARVALID : in STD_LOGIC;
S_AXI_HP1_AWVALID : in STD_LOGIC;
S_AXI_HP1_BREADY : in STD_LOGIC;
S_AXI_HP1_RDISSUECAP1_EN : in STD_LOGIC;
S_AXI_HP1_RREADY : in STD_LOGIC;
S_AXI_HP1_WLAST : in STD_LOGIC;
S_AXI_HP1_WRISSUECAP1_EN : in STD_LOGIC;
S_AXI_HP1_WVALID : in STD_LOGIC;
S_AXI_HP1_ARBURST : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP1_ARLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP1_ARSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP1_AWBURST : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP1_AWLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP1_AWSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP1_ARPROT : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP1_AWPROT : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP1_ARADDR : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_HP1_AWADDR : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_HP1_ARCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP1_ARLEN : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP1_ARQOS : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP1_AWCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP1_AWLEN : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP1_AWQOS : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP1_ARID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP1_AWID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP1_WID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP1_WDATA : in STD_LOGIC_VECTOR ( 63 downto 0 );
S_AXI_HP1_WSTRB : in STD_LOGIC_VECTOR ( 7 downto 0 );
S_AXI_HP2_ARESETN : out STD_LOGIC;
S_AXI_HP2_ARREADY : out STD_LOGIC;
S_AXI_HP2_AWREADY : out STD_LOGIC;
S_AXI_HP2_BVALID : out STD_LOGIC;
S_AXI_HP2_RLAST : out STD_LOGIC;
S_AXI_HP2_RVALID : out STD_LOGIC;
S_AXI_HP2_WREADY : out STD_LOGIC;
S_AXI_HP2_BRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP2_RRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP2_BID : out STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP2_RID : out STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP2_RDATA : out STD_LOGIC_VECTOR ( 63 downto 0 );
S_AXI_HP2_RCOUNT : out STD_LOGIC_VECTOR ( 7 downto 0 );
S_AXI_HP2_WCOUNT : out STD_LOGIC_VECTOR ( 7 downto 0 );
S_AXI_HP2_RACOUNT : out STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP2_WACOUNT : out STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP2_ACLK : in STD_LOGIC;
S_AXI_HP2_ARVALID : in STD_LOGIC;
S_AXI_HP2_AWVALID : in STD_LOGIC;
S_AXI_HP2_BREADY : in STD_LOGIC;
S_AXI_HP2_RDISSUECAP1_EN : in STD_LOGIC;
S_AXI_HP2_RREADY : in STD_LOGIC;
S_AXI_HP2_WLAST : in STD_LOGIC;
S_AXI_HP2_WRISSUECAP1_EN : in STD_LOGIC;
S_AXI_HP2_WVALID : in STD_LOGIC;
S_AXI_HP2_ARBURST : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP2_ARLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP2_ARSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP2_AWBURST : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP2_AWLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP2_AWSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP2_ARPROT : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP2_AWPROT : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP2_ARADDR : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_HP2_AWADDR : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_HP2_ARCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP2_ARLEN : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP2_ARQOS : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP2_AWCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP2_AWLEN : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP2_AWQOS : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP2_ARID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP2_AWID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP2_WID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP2_WDATA : in STD_LOGIC_VECTOR ( 63 downto 0 );
S_AXI_HP2_WSTRB : in STD_LOGIC_VECTOR ( 7 downto 0 );
S_AXI_HP3_ARESETN : out STD_LOGIC;
S_AXI_HP3_ARREADY : out STD_LOGIC;
S_AXI_HP3_AWREADY : out STD_LOGIC;
S_AXI_HP3_BVALID : out STD_LOGIC;
S_AXI_HP3_RLAST : out STD_LOGIC;
S_AXI_HP3_RVALID : out STD_LOGIC;
S_AXI_HP3_WREADY : out STD_LOGIC;
S_AXI_HP3_BRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP3_RRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP3_BID : out STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP3_RID : out STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP3_RDATA : out STD_LOGIC_VECTOR ( 63 downto 0 );
S_AXI_HP3_RCOUNT : out STD_LOGIC_VECTOR ( 7 downto 0 );
S_AXI_HP3_WCOUNT : out STD_LOGIC_VECTOR ( 7 downto 0 );
S_AXI_HP3_RACOUNT : out STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP3_WACOUNT : out STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP3_ACLK : in STD_LOGIC;
S_AXI_HP3_ARVALID : in STD_LOGIC;
S_AXI_HP3_AWVALID : in STD_LOGIC;
S_AXI_HP3_BREADY : in STD_LOGIC;
S_AXI_HP3_RDISSUECAP1_EN : in STD_LOGIC;
S_AXI_HP3_RREADY : in STD_LOGIC;
S_AXI_HP3_WLAST : in STD_LOGIC;
S_AXI_HP3_WRISSUECAP1_EN : in STD_LOGIC;
S_AXI_HP3_WVALID : in STD_LOGIC;
S_AXI_HP3_ARBURST : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP3_ARLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP3_ARSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP3_AWBURST : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP3_AWLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP3_AWSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP3_ARPROT : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP3_AWPROT : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP3_ARADDR : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_HP3_AWADDR : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_HP3_ARCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP3_ARLEN : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP3_ARQOS : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP3_AWCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP3_AWLEN : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP3_AWQOS : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP3_ARID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP3_AWID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP3_WID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP3_WDATA : in STD_LOGIC_VECTOR ( 63 downto 0 );
S_AXI_HP3_WSTRB : in STD_LOGIC_VECTOR ( 7 downto 0 );
IRQ_P2F_DMAC_ABORT : out STD_LOGIC;
IRQ_P2F_DMAC0 : out STD_LOGIC;
IRQ_P2F_DMAC1 : out STD_LOGIC;
IRQ_P2F_DMAC2 : out STD_LOGIC;
IRQ_P2F_DMAC3 : out STD_LOGIC;
IRQ_P2F_DMAC4 : out STD_LOGIC;
IRQ_P2F_DMAC5 : out STD_LOGIC;
IRQ_P2F_DMAC6 : out STD_LOGIC;
IRQ_P2F_DMAC7 : out STD_LOGIC;
IRQ_P2F_SMC : out STD_LOGIC;
IRQ_P2F_QSPI : out STD_LOGIC;
IRQ_P2F_CTI : out STD_LOGIC;
IRQ_P2F_GPIO : out STD_LOGIC;
IRQ_P2F_USB0 : out STD_LOGIC;
IRQ_P2F_ENET0 : out STD_LOGIC;
IRQ_P2F_ENET_WAKE0 : out STD_LOGIC;
IRQ_P2F_SDIO0 : out STD_LOGIC;
IRQ_P2F_I2C0 : out STD_LOGIC;
IRQ_P2F_SPI0 : out STD_LOGIC;
IRQ_P2F_UART0 : out STD_LOGIC;
IRQ_P2F_CAN0 : out STD_LOGIC;
IRQ_P2F_USB1 : out STD_LOGIC;
IRQ_P2F_ENET1 : out STD_LOGIC;
IRQ_P2F_ENET_WAKE1 : out STD_LOGIC;
IRQ_P2F_SDIO1 : out STD_LOGIC;
IRQ_P2F_I2C1 : out STD_LOGIC;
IRQ_P2F_SPI1 : out STD_LOGIC;
IRQ_P2F_UART1 : out STD_LOGIC;
IRQ_P2F_CAN1 : out STD_LOGIC;
IRQ_F2P : in STD_LOGIC_VECTOR ( 0 to 0 );
Core0_nFIQ : in STD_LOGIC;
Core0_nIRQ : in STD_LOGIC;
Core1_nFIQ : in STD_LOGIC;
Core1_nIRQ : in STD_LOGIC;
DMA0_DATYPE : out STD_LOGIC_VECTOR ( 1 downto 0 );
DMA0_DAVALID : out STD_LOGIC;
DMA0_DRREADY : out STD_LOGIC;
DMA0_RSTN : out STD_LOGIC;
DMA1_DATYPE : out STD_LOGIC_VECTOR ( 1 downto 0 );
DMA1_DAVALID : out STD_LOGIC;
DMA1_DRREADY : out STD_LOGIC;
DMA1_RSTN : out STD_LOGIC;
DMA2_DATYPE : out STD_LOGIC_VECTOR ( 1 downto 0 );
DMA2_DAVALID : out STD_LOGIC;
DMA2_DRREADY : out STD_LOGIC;
DMA2_RSTN : out STD_LOGIC;
DMA3_DATYPE : out STD_LOGIC_VECTOR ( 1 downto 0 );
DMA3_DAVALID : out STD_LOGIC;
DMA3_DRREADY : out STD_LOGIC;
DMA3_RSTN : out STD_LOGIC;
DMA0_ACLK : in STD_LOGIC;
DMA0_DAREADY : in STD_LOGIC;
DMA0_DRLAST : in STD_LOGIC;
DMA0_DRVALID : in STD_LOGIC;
DMA1_ACLK : in STD_LOGIC;
DMA1_DAREADY : in STD_LOGIC;
DMA1_DRLAST : in STD_LOGIC;
DMA1_DRVALID : in STD_LOGIC;
DMA2_ACLK : in STD_LOGIC;
DMA2_DAREADY : in STD_LOGIC;
DMA2_DRLAST : in STD_LOGIC;
DMA2_DRVALID : in STD_LOGIC;
DMA3_ACLK : in STD_LOGIC;
DMA3_DAREADY : in STD_LOGIC;
DMA3_DRLAST : in STD_LOGIC;
DMA3_DRVALID : in STD_LOGIC;
DMA0_DRTYPE : in STD_LOGIC_VECTOR ( 1 downto 0 );
DMA1_DRTYPE : in STD_LOGIC_VECTOR ( 1 downto 0 );
DMA2_DRTYPE : in STD_LOGIC_VECTOR ( 1 downto 0 );
DMA3_DRTYPE : in STD_LOGIC_VECTOR ( 1 downto 0 );
FCLK_CLK3 : out STD_LOGIC;
FCLK_CLK2 : out STD_LOGIC;
FCLK_CLK1 : out STD_LOGIC;
FCLK_CLK0 : out STD_LOGIC;
FCLK_CLKTRIG3_N : in STD_LOGIC;
FCLK_CLKTRIG2_N : in STD_LOGIC;
FCLK_CLKTRIG1_N : in STD_LOGIC;
FCLK_CLKTRIG0_N : in STD_LOGIC;
FCLK_RESET3_N : out STD_LOGIC;
FCLK_RESET2_N : out STD_LOGIC;
FCLK_RESET1_N : out STD_LOGIC;
FCLK_RESET0_N : out STD_LOGIC;
FTMD_TRACEIN_DATA : in STD_LOGIC_VECTOR ( 31 downto 0 );
FTMD_TRACEIN_VALID : in STD_LOGIC;
FTMD_TRACEIN_CLK : in STD_LOGIC;
FTMD_TRACEIN_ATID : in STD_LOGIC_VECTOR ( 3 downto 0 );
FTMT_F2P_TRIG_0 : in STD_LOGIC;
FTMT_F2P_TRIGACK_0 : out STD_LOGIC;
FTMT_F2P_TRIG_1 : in STD_LOGIC;
FTMT_F2P_TRIGACK_1 : out STD_LOGIC;
FTMT_F2P_TRIG_2 : in STD_LOGIC;
FTMT_F2P_TRIGACK_2 : out STD_LOGIC;
FTMT_F2P_TRIG_3 : in STD_LOGIC;
FTMT_F2P_TRIGACK_3 : out STD_LOGIC;
FTMT_F2P_DEBUG : in STD_LOGIC_VECTOR ( 31 downto 0 );
FTMT_P2F_TRIGACK_0 : in STD_LOGIC;
FTMT_P2F_TRIG_0 : out STD_LOGIC;
FTMT_P2F_TRIGACK_1 : in STD_LOGIC;
FTMT_P2F_TRIG_1 : out STD_LOGIC;
FTMT_P2F_TRIGACK_2 : in STD_LOGIC;
FTMT_P2F_TRIG_2 : out STD_LOGIC;
FTMT_P2F_TRIGACK_3 : in STD_LOGIC;
FTMT_P2F_TRIG_3 : out STD_LOGIC;
FTMT_P2F_DEBUG : out STD_LOGIC_VECTOR ( 31 downto 0 );
FPGA_IDLE_N : in STD_LOGIC;
EVENT_EVENTO : out STD_LOGIC;
EVENT_STANDBYWFE : out STD_LOGIC_VECTOR ( 1 downto 0 );
EVENT_STANDBYWFI : out STD_LOGIC_VECTOR ( 1 downto 0 );
EVENT_EVENTI : in STD_LOGIC;
DDR_ARB : in STD_LOGIC_VECTOR ( 3 downto 0 );
MIO : inout STD_LOGIC_VECTOR ( 53 downto 0 );
DDR_CAS_n : inout STD_LOGIC;
DDR_CKE : inout STD_LOGIC;
DDR_Clk_n : inout STD_LOGIC;
DDR_Clk : inout STD_LOGIC;
DDR_CS_n : inout STD_LOGIC;
DDR_DRSTB : inout STD_LOGIC;
DDR_ODT : inout STD_LOGIC;
DDR_RAS_n : inout STD_LOGIC;
DDR_WEB : inout STD_LOGIC;
DDR_BankAddr : inout STD_LOGIC_VECTOR ( 2 downto 0 );
DDR_Addr : inout STD_LOGIC_VECTOR ( 14 downto 0 );
DDR_VRN : inout STD_LOGIC;
DDR_VRP : inout STD_LOGIC;
DDR_DM : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_DQ : inout STD_LOGIC_VECTOR ( 31 downto 0 );
DDR_DQS_n : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_DQS : inout STD_LOGIC_VECTOR ( 3 downto 0 );
PS_SRSTB : inout STD_LOGIC;
PS_CLK : inout STD_LOGIC;
PS_PORB : inout STD_LOGIC
);
attribute C_DM_WIDTH : integer;
attribute C_DM_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 4;
attribute C_DQS_WIDTH : integer;
attribute C_DQS_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 4;
attribute C_DQ_WIDTH : integer;
attribute C_DQ_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 32;
attribute C_EMIO_GPIO_WIDTH : integer;
attribute C_EMIO_GPIO_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 64;
attribute C_EN_EMIO_ENET0 : integer;
attribute C_EN_EMIO_ENET0 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 0;
attribute C_EN_EMIO_ENET1 : integer;
attribute C_EN_EMIO_ENET1 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 0;
attribute C_EN_EMIO_PJTAG : integer;
attribute C_EN_EMIO_PJTAG of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 0;
attribute C_EN_EMIO_TRACE : integer;
attribute C_EN_EMIO_TRACE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 0;
attribute C_FCLK_CLK0_BUF : string;
attribute C_FCLK_CLK0_BUF of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is "TRUE";
attribute C_FCLK_CLK1_BUF : string;
attribute C_FCLK_CLK1_BUF of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is "FALSE";
attribute C_FCLK_CLK2_BUF : string;
attribute C_FCLK_CLK2_BUF of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is "FALSE";
attribute C_FCLK_CLK3_BUF : string;
attribute C_FCLK_CLK3_BUF of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is "FALSE";
attribute C_GP0_EN_MODIFIABLE_TXN : integer;
attribute C_GP0_EN_MODIFIABLE_TXN of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 0;
attribute C_GP1_EN_MODIFIABLE_TXN : integer;
attribute C_GP1_EN_MODIFIABLE_TXN of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 0;
attribute C_INCLUDE_ACP_TRANS_CHECK : integer;
attribute C_INCLUDE_ACP_TRANS_CHECK of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 0;
attribute C_INCLUDE_TRACE_BUFFER : integer;
attribute C_INCLUDE_TRACE_BUFFER of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 0;
attribute C_IRQ_F2P_MODE : string;
attribute C_IRQ_F2P_MODE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is "DIRECT";
attribute C_MIO_PRIMITIVE : integer;
attribute C_MIO_PRIMITIVE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 54;
attribute C_M_AXI_GP0_ENABLE_STATIC_REMAP : integer;
attribute C_M_AXI_GP0_ENABLE_STATIC_REMAP of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 0;
attribute C_M_AXI_GP0_ID_WIDTH : integer;
attribute C_M_AXI_GP0_ID_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 12;
attribute C_M_AXI_GP0_THREAD_ID_WIDTH : integer;
attribute C_M_AXI_GP0_THREAD_ID_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 12;
attribute C_M_AXI_GP1_ENABLE_STATIC_REMAP : integer;
attribute C_M_AXI_GP1_ENABLE_STATIC_REMAP of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 0;
attribute C_M_AXI_GP1_ID_WIDTH : integer;
attribute C_M_AXI_GP1_ID_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 12;
attribute C_M_AXI_GP1_THREAD_ID_WIDTH : integer;
attribute C_M_AXI_GP1_THREAD_ID_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 12;
attribute C_NUM_F2P_INTR_INPUTS : integer;
attribute C_NUM_F2P_INTR_INPUTS of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 1;
attribute C_PACKAGE_NAME : string;
attribute C_PACKAGE_NAME of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is "clg400";
attribute C_PS7_SI_REV : string;
attribute C_PS7_SI_REV of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is "PRODUCTION";
attribute C_S_AXI_ACP_ARUSER_VAL : integer;
attribute C_S_AXI_ACP_ARUSER_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 31;
attribute C_S_AXI_ACP_AWUSER_VAL : integer;
attribute C_S_AXI_ACP_AWUSER_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 31;
attribute C_S_AXI_ACP_ID_WIDTH : integer;
attribute C_S_AXI_ACP_ID_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 3;
attribute C_S_AXI_GP0_ID_WIDTH : integer;
attribute C_S_AXI_GP0_ID_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 6;
attribute C_S_AXI_GP1_ID_WIDTH : integer;
attribute C_S_AXI_GP1_ID_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 6;
attribute C_S_AXI_HP0_DATA_WIDTH : integer;
attribute C_S_AXI_HP0_DATA_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 64;
attribute C_S_AXI_HP0_ID_WIDTH : integer;
attribute C_S_AXI_HP0_ID_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 6;
attribute C_S_AXI_HP1_DATA_WIDTH : integer;
attribute C_S_AXI_HP1_DATA_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 64;
attribute C_S_AXI_HP1_ID_WIDTH : integer;
attribute C_S_AXI_HP1_ID_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 6;
attribute C_S_AXI_HP2_DATA_WIDTH : integer;
attribute C_S_AXI_HP2_DATA_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 64;
attribute C_S_AXI_HP2_ID_WIDTH : integer;
attribute C_S_AXI_HP2_ID_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 6;
attribute C_S_AXI_HP3_DATA_WIDTH : integer;
attribute C_S_AXI_HP3_DATA_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 64;
attribute C_S_AXI_HP3_ID_WIDTH : integer;
attribute C_S_AXI_HP3_ID_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 6;
attribute C_TRACE_BUFFER_CLOCK_DELAY : integer;
attribute C_TRACE_BUFFER_CLOCK_DELAY of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 12;
attribute C_TRACE_BUFFER_FIFO_SIZE : integer;
attribute C_TRACE_BUFFER_FIFO_SIZE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 128;
attribute C_TRACE_INTERNAL_WIDTH : integer;
attribute C_TRACE_INTERNAL_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 2;
attribute C_TRACE_PIPELINE_WIDTH : integer;
attribute C_TRACE_PIPELINE_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 8;
attribute C_USE_AXI_NONSECURE : integer;
attribute C_USE_AXI_NONSECURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 0;
attribute C_USE_DEFAULT_ACP_USER_VAL : integer;
attribute C_USE_DEFAULT_ACP_USER_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 0;
attribute C_USE_M_AXI_GP0 : integer;
attribute C_USE_M_AXI_GP0 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 1;
attribute C_USE_M_AXI_GP1 : integer;
attribute C_USE_M_AXI_GP1 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 0;
attribute C_USE_S_AXI_ACP : integer;
attribute C_USE_S_AXI_ACP of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 0;
attribute C_USE_S_AXI_GP0 : integer;
attribute C_USE_S_AXI_GP0 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 0;
attribute C_USE_S_AXI_GP1 : integer;
attribute C_USE_S_AXI_GP1 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 0;
attribute C_USE_S_AXI_HP0 : integer;
attribute C_USE_S_AXI_HP0 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 0;
attribute C_USE_S_AXI_HP1 : integer;
attribute C_USE_S_AXI_HP1 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 0;
attribute C_USE_S_AXI_HP2 : integer;
attribute C_USE_S_AXI_HP2 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 0;
attribute C_USE_S_AXI_HP3 : integer;
attribute C_USE_S_AXI_HP3 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 0;
attribute HW_HANDOFF : string;
attribute HW_HANDOFF of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is "zybo_zynq_design_processing_system7_0_0.hwdef";
attribute POWER : string;
attribute POWER of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is "<PROCESSOR name={system} numA9Cores={2} clockFreq={650} load={0.5} /><MEMORY name={code} memType={DDR3} dataWidth={32} clockFreq={525} readRate={0.5} writeRate={0.5} /><IO interface={GPIO_Bank_1} ioStandard={LVCMOS18} bidis={2} ioBank={Vcco_p1} clockFreq={1} usageRate={0.5} /><IO interface={GPIO_Bank_0} ioStandard={LVCMOS33} bidis={9} ioBank={Vcco_p0} clockFreq={1} usageRate={0.5} /><IO interface={Timer} ioStandard={} bidis={0} ioBank={} clockFreq={108.333336} usageRate={0.5} /><IO interface={UART} ioStandard={LVCMOS18} bidis={2} ioBank={Vcco_p1} clockFreq={100.000000} usageRate={0.5} /><IO interface={SD} ioStandard={LVCMOS18} bidis={7} ioBank={Vcco_p1} clockFreq={50.000000} usageRate={0.5} /><IO interface={USB} ioStandard={LVCMOS18} bidis={12} ioBank={Vcco_p1} clockFreq={60} usageRate={0.5} /><IO interface={GigE} ioStandard={HSTL_I_18} bidis={14} ioBank={Vcco_p1} clockFreq={125.000000} usageRate={0.5} /><IO interface={QSPI} ioStandard={LVCMOS33} bidis={7} ioBank={Vcco_p0} clockFreq={200} usageRate={0.5} /><PLL domain={Processor} vco={1300.000} /><PLL domain={Memory} vco={1050.000} /><PLL domain={IO} vco={1000.000} /><AXI interface={M_AXI_GP0} dataWidth={32} clockFreq={100} usageRate={0.5} />/>";
attribute USE_TRACE_DATA_EDGE_DETECTOR : integer;
attribute USE_TRACE_DATA_EDGE_DETECTOR of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 0;
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 is
signal \<const0>\ : STD_LOGIC;
signal ENET0_MDIO_T_n : STD_LOGIC;
signal ENET1_MDIO_T_n : STD_LOGIC;
signal FCLK_CLK_unbuffered : STD_LOGIC_VECTOR ( 0 to 0 );
signal I2C0_SCL_T_n : STD_LOGIC;
signal I2C0_SDA_T_n : STD_LOGIC;
signal I2C1_SCL_T_n : STD_LOGIC;
signal I2C1_SDA_T_n : STD_LOGIC;
signal \^m_axi_gp0_arsize\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \^m_axi_gp0_awsize\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \^m_axi_gp1_arsize\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \^m_axi_gp1_awsize\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal SDIO0_CMD_T_n : STD_LOGIC;
signal SDIO0_DATA_T_n : STD_LOGIC_VECTOR ( 3 downto 0 );
signal SDIO1_CMD_T_n : STD_LOGIC;
signal SDIO1_DATA_T_n : STD_LOGIC_VECTOR ( 3 downto 0 );
signal SPI0_MISO_T_n : STD_LOGIC;
signal SPI0_MOSI_T_n : STD_LOGIC;
signal SPI0_SCLK_T_n : STD_LOGIC;
signal SPI0_SS_T_n : STD_LOGIC;
signal SPI1_MISO_T_n : STD_LOGIC;
signal SPI1_MOSI_T_n : STD_LOGIC;
signal SPI1_SCLK_T_n : STD_LOGIC;
signal SPI1_SS_T_n : STD_LOGIC;
signal \TRACE_CTL_PIPE[0]\ : STD_LOGIC;
attribute RTL_KEEP : string;
attribute RTL_KEEP of \TRACE_CTL_PIPE[0]\ : signal is "true";
signal \TRACE_CTL_PIPE[1]\ : STD_LOGIC;
attribute RTL_KEEP of \TRACE_CTL_PIPE[1]\ : signal is "true";
signal \TRACE_CTL_PIPE[2]\ : STD_LOGIC;
attribute RTL_KEEP of \TRACE_CTL_PIPE[2]\ : signal is "true";
signal \TRACE_CTL_PIPE[3]\ : STD_LOGIC;
attribute RTL_KEEP of \TRACE_CTL_PIPE[3]\ : signal is "true";
signal \TRACE_CTL_PIPE[4]\ : STD_LOGIC;
attribute RTL_KEEP of \TRACE_CTL_PIPE[4]\ : signal is "true";
signal \TRACE_CTL_PIPE[5]\ : STD_LOGIC;
attribute RTL_KEEP of \TRACE_CTL_PIPE[5]\ : signal is "true";
signal \TRACE_CTL_PIPE[6]\ : STD_LOGIC;
attribute RTL_KEEP of \TRACE_CTL_PIPE[6]\ : signal is "true";
signal \TRACE_CTL_PIPE[7]\ : STD_LOGIC;
attribute RTL_KEEP of \TRACE_CTL_PIPE[7]\ : signal is "true";
signal \TRACE_DATA_PIPE[0]\ : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute RTL_KEEP of \TRACE_DATA_PIPE[0]\ : signal is "true";
signal \TRACE_DATA_PIPE[1]\ : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute RTL_KEEP of \TRACE_DATA_PIPE[1]\ : signal is "true";
signal \TRACE_DATA_PIPE[2]\ : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute RTL_KEEP of \TRACE_DATA_PIPE[2]\ : signal is "true";
signal \TRACE_DATA_PIPE[3]\ : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute RTL_KEEP of \TRACE_DATA_PIPE[3]\ : signal is "true";
signal \TRACE_DATA_PIPE[4]\ : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute RTL_KEEP of \TRACE_DATA_PIPE[4]\ : signal is "true";
signal \TRACE_DATA_PIPE[5]\ : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute RTL_KEEP of \TRACE_DATA_PIPE[5]\ : signal is "true";
signal \TRACE_DATA_PIPE[6]\ : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute RTL_KEEP of \TRACE_DATA_PIPE[6]\ : signal is "true";
signal \TRACE_DATA_PIPE[7]\ : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute RTL_KEEP of \TRACE_DATA_PIPE[7]\ : signal is "true";
signal buffered_DDR_Addr : STD_LOGIC_VECTOR ( 14 downto 0 );
signal buffered_DDR_BankAddr : STD_LOGIC_VECTOR ( 2 downto 0 );
signal buffered_DDR_CAS_n : STD_LOGIC;
signal buffered_DDR_CKE : STD_LOGIC;
signal buffered_DDR_CS_n : STD_LOGIC;
signal buffered_DDR_Clk : STD_LOGIC;
signal buffered_DDR_Clk_n : STD_LOGIC;
signal buffered_DDR_DM : STD_LOGIC_VECTOR ( 3 downto 0 );
signal buffered_DDR_DQ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal buffered_DDR_DQS : STD_LOGIC_VECTOR ( 3 downto 0 );
signal buffered_DDR_DQS_n : STD_LOGIC_VECTOR ( 3 downto 0 );
signal buffered_DDR_DRSTB : STD_LOGIC;
signal buffered_DDR_ODT : STD_LOGIC;
signal buffered_DDR_RAS_n : STD_LOGIC;
signal buffered_DDR_VRN : STD_LOGIC;
signal buffered_DDR_VRP : STD_LOGIC;
signal buffered_DDR_WEB : STD_LOGIC;
signal buffered_MIO : STD_LOGIC_VECTOR ( 53 downto 0 );
signal buffered_PS_CLK : STD_LOGIC;
signal buffered_PS_PORB : STD_LOGIC;
signal buffered_PS_SRSTB : STD_LOGIC;
signal gpio_out_t_n : STD_LOGIC_VECTOR ( 63 downto 0 );
signal NLW_PS7_i_EMIOENET0GMIITXEN_UNCONNECTED : STD_LOGIC;
signal NLW_PS7_i_EMIOENET0GMIITXER_UNCONNECTED : STD_LOGIC;
signal NLW_PS7_i_EMIOENET1GMIITXEN_UNCONNECTED : STD_LOGIC;
signal NLW_PS7_i_EMIOENET1GMIITXER_UNCONNECTED : STD_LOGIC;
signal NLW_PS7_i_EMIOPJTAGTDO_UNCONNECTED : STD_LOGIC;
signal NLW_PS7_i_EMIOPJTAGTDTN_UNCONNECTED : STD_LOGIC;
signal NLW_PS7_i_EMIOTRACECTL_UNCONNECTED : STD_LOGIC;
signal NLW_PS7_i_EMIOENET0GMIITXD_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_PS7_i_EMIOENET1GMIITXD_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_PS7_i_EMIOTRACEDATA_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
attribute BOX_TYPE : string;
attribute BOX_TYPE of DDR_CAS_n_BIBUF : label is "PRIMITIVE";
attribute BOX_TYPE of DDR_CKE_BIBUF : label is "PRIMITIVE";
attribute BOX_TYPE of DDR_CS_n_BIBUF : label is "PRIMITIVE";
attribute BOX_TYPE of DDR_Clk_BIBUF : label is "PRIMITIVE";
attribute BOX_TYPE of DDR_Clk_n_BIBUF : label is "PRIMITIVE";
attribute BOX_TYPE of DDR_DRSTB_BIBUF : label is "PRIMITIVE";
attribute BOX_TYPE of DDR_ODT_BIBUF : label is "PRIMITIVE";
attribute BOX_TYPE of DDR_RAS_n_BIBUF : label is "PRIMITIVE";
attribute BOX_TYPE of DDR_VRN_BIBUF : label is "PRIMITIVE";
attribute BOX_TYPE of DDR_VRP_BIBUF : label is "PRIMITIVE";
attribute BOX_TYPE of DDR_WEB_BIBUF : label is "PRIMITIVE";
attribute BOX_TYPE of PS7_i : label is "PRIMITIVE";
attribute BOX_TYPE of PS_CLK_BIBUF : label is "PRIMITIVE";
attribute BOX_TYPE of PS_PORB_BIBUF : label is "PRIMITIVE";
attribute BOX_TYPE of PS_SRSTB_BIBUF : label is "PRIMITIVE";
attribute BOX_TYPE of \buffer_fclk_clk_0.FCLK_CLK_0_BUFG\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[0].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[10].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[11].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[12].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[13].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[14].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[15].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[16].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[17].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[18].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[19].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[1].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[20].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[21].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[22].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[23].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[24].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[25].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[26].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[27].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[28].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[29].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[2].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[30].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[31].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[32].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[33].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[34].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[35].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[36].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[37].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[38].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[39].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[3].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[40].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[41].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[42].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[43].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[44].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[45].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[46].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[47].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[48].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[49].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[4].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[50].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[51].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[52].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[53].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[5].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[6].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[7].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[8].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[9].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk14[0].DDR_BankAddr_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk14[1].DDR_BankAddr_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk14[2].DDR_BankAddr_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk15[0].DDR_Addr_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk15[10].DDR_Addr_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk15[11].DDR_Addr_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk15[12].DDR_Addr_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk15[13].DDR_Addr_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk15[14].DDR_Addr_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk15[1].DDR_Addr_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk15[2].DDR_Addr_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk15[3].DDR_Addr_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk15[4].DDR_Addr_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk15[5].DDR_Addr_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk15[6].DDR_Addr_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk15[7].DDR_Addr_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk15[8].DDR_Addr_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk15[9].DDR_Addr_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk16[0].DDR_DM_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk16[1].DDR_DM_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk16[2].DDR_DM_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk16[3].DDR_DM_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[0].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[10].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[11].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[12].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[13].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[14].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[15].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[16].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[17].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[18].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[19].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[1].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[20].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[21].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[22].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[23].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[24].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[25].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[26].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[27].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[28].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[29].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[2].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[30].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[31].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[3].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[4].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[5].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[6].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[7].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[8].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[9].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk18[0].DDR_DQS_n_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk18[1].DDR_DQS_n_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk18[2].DDR_DQS_n_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk18[3].DDR_DQS_n_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk19[0].DDR_DQS_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk19[1].DDR_DQS_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk19[2].DDR_DQS_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk19[3].DDR_DQS_BIBUF\ : label is "PRIMITIVE";
begin
ENET0_GMII_TXD(7) <= \<const0>\;
ENET0_GMII_TXD(6) <= \<const0>\;
ENET0_GMII_TXD(5) <= \<const0>\;
ENET0_GMII_TXD(4) <= \<const0>\;
ENET0_GMII_TXD(3) <= \<const0>\;
ENET0_GMII_TXD(2) <= \<const0>\;
ENET0_GMII_TXD(1) <= \<const0>\;
ENET0_GMII_TXD(0) <= \<const0>\;
ENET0_GMII_TX_EN <= \<const0>\;
ENET0_GMII_TX_ER <= \<const0>\;
ENET1_GMII_TXD(7) <= \<const0>\;
ENET1_GMII_TXD(6) <= \<const0>\;
ENET1_GMII_TXD(5) <= \<const0>\;
ENET1_GMII_TXD(4) <= \<const0>\;
ENET1_GMII_TXD(3) <= \<const0>\;
ENET1_GMII_TXD(2) <= \<const0>\;
ENET1_GMII_TXD(1) <= \<const0>\;
ENET1_GMII_TXD(0) <= \<const0>\;
ENET1_GMII_TX_EN <= \<const0>\;
ENET1_GMII_TX_ER <= \<const0>\;
M_AXI_GP0_ARSIZE(2) <= \<const0>\;
M_AXI_GP0_ARSIZE(1 downto 0) <= \^m_axi_gp0_arsize\(1 downto 0);
M_AXI_GP0_AWSIZE(2) <= \<const0>\;
M_AXI_GP0_AWSIZE(1 downto 0) <= \^m_axi_gp0_awsize\(1 downto 0);
M_AXI_GP1_ARSIZE(2) <= \<const0>\;
M_AXI_GP1_ARSIZE(1 downto 0) <= \^m_axi_gp1_arsize\(1 downto 0);
M_AXI_GP1_AWSIZE(2) <= \<const0>\;
M_AXI_GP1_AWSIZE(1 downto 0) <= \^m_axi_gp1_awsize\(1 downto 0);
PJTAG_TDO <= \<const0>\;
TRACE_CLK_OUT <= \<const0>\;
TRACE_CTL <= \TRACE_CTL_PIPE[0]\;
TRACE_DATA(1 downto 0) <= \TRACE_DATA_PIPE[0]\(1 downto 0);
DDR_CAS_n_BIBUF: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_CAS_n,
PAD => DDR_CAS_n
);
DDR_CKE_BIBUF: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_CKE,
PAD => DDR_CKE
);
DDR_CS_n_BIBUF: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_CS_n,
PAD => DDR_CS_n
);
DDR_Clk_BIBUF: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_Clk,
PAD => DDR_Clk
);
DDR_Clk_n_BIBUF: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_Clk_n,
PAD => DDR_Clk_n
);
DDR_DRSTB_BIBUF: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DRSTB,
PAD => DDR_DRSTB
);
DDR_ODT_BIBUF: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_ODT,
PAD => DDR_ODT
);
DDR_RAS_n_BIBUF: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_RAS_n,
PAD => DDR_RAS_n
);
DDR_VRN_BIBUF: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_VRN,
PAD => DDR_VRN
);
DDR_VRP_BIBUF: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_VRP,
PAD => DDR_VRP
);
DDR_WEB_BIBUF: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_WEB,
PAD => DDR_WEB
);
ENET0_MDIO_T_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => ENET0_MDIO_T_n,
O => ENET0_MDIO_T
);
ENET1_MDIO_T_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => ENET1_MDIO_T_n,
O => ENET1_MDIO_T
);
GND: unisim.vcomponents.GND
port map (
G => \<const0>\
);
\GPIO_T[0]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(0),
O => GPIO_T(0)
);
\GPIO_T[10]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(10),
O => GPIO_T(10)
);
\GPIO_T[11]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(11),
O => GPIO_T(11)
);
\GPIO_T[12]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(12),
O => GPIO_T(12)
);
\GPIO_T[13]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(13),
O => GPIO_T(13)
);
\GPIO_T[14]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(14),
O => GPIO_T(14)
);
\GPIO_T[15]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(15),
O => GPIO_T(15)
);
\GPIO_T[16]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(16),
O => GPIO_T(16)
);
\GPIO_T[17]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(17),
O => GPIO_T(17)
);
\GPIO_T[18]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(18),
O => GPIO_T(18)
);
\GPIO_T[19]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(19),
O => GPIO_T(19)
);
\GPIO_T[1]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(1),
O => GPIO_T(1)
);
\GPIO_T[20]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(20),
O => GPIO_T(20)
);
\GPIO_T[21]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(21),
O => GPIO_T(21)
);
\GPIO_T[22]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(22),
O => GPIO_T(22)
);
\GPIO_T[23]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(23),
O => GPIO_T(23)
);
\GPIO_T[24]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(24),
O => GPIO_T(24)
);
\GPIO_T[25]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(25),
O => GPIO_T(25)
);
\GPIO_T[26]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(26),
O => GPIO_T(26)
);
\GPIO_T[27]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(27),
O => GPIO_T(27)
);
\GPIO_T[28]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(28),
O => GPIO_T(28)
);
\GPIO_T[29]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(29),
O => GPIO_T(29)
);
\GPIO_T[2]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(2),
O => GPIO_T(2)
);
\GPIO_T[30]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(30),
O => GPIO_T(30)
);
\GPIO_T[31]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(31),
O => GPIO_T(31)
);
\GPIO_T[32]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(32),
O => GPIO_T(32)
);
\GPIO_T[33]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(33),
O => GPIO_T(33)
);
\GPIO_T[34]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(34),
O => GPIO_T(34)
);
\GPIO_T[35]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(35),
O => GPIO_T(35)
);
\GPIO_T[36]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(36),
O => GPIO_T(36)
);
\GPIO_T[37]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(37),
O => GPIO_T(37)
);
\GPIO_T[38]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(38),
O => GPIO_T(38)
);
\GPIO_T[39]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(39),
O => GPIO_T(39)
);
\GPIO_T[3]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(3),
O => GPIO_T(3)
);
\GPIO_T[40]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(40),
O => GPIO_T(40)
);
\GPIO_T[41]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(41),
O => GPIO_T(41)
);
\GPIO_T[42]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(42),
O => GPIO_T(42)
);
\GPIO_T[43]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(43),
O => GPIO_T(43)
);
\GPIO_T[44]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(44),
O => GPIO_T(44)
);
\GPIO_T[45]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(45),
O => GPIO_T(45)
);
\GPIO_T[46]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(46),
O => GPIO_T(46)
);
\GPIO_T[47]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(47),
O => GPIO_T(47)
);
\GPIO_T[48]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(48),
O => GPIO_T(48)
);
\GPIO_T[49]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(49),
O => GPIO_T(49)
);
\GPIO_T[4]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(4),
O => GPIO_T(4)
);
\GPIO_T[50]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(50),
O => GPIO_T(50)
);
\GPIO_T[51]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(51),
O => GPIO_T(51)
);
\GPIO_T[52]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(52),
O => GPIO_T(52)
);
\GPIO_T[53]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(53),
O => GPIO_T(53)
);
\GPIO_T[54]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(54),
O => GPIO_T(54)
);
\GPIO_T[55]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(55),
O => GPIO_T(55)
);
\GPIO_T[56]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(56),
O => GPIO_T(56)
);
\GPIO_T[57]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(57),
O => GPIO_T(57)
);
\GPIO_T[58]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(58),
O => GPIO_T(58)
);
\GPIO_T[59]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(59),
O => GPIO_T(59)
);
\GPIO_T[5]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(5),
O => GPIO_T(5)
);
\GPIO_T[60]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(60),
O => GPIO_T(60)
);
\GPIO_T[61]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(61),
O => GPIO_T(61)
);
\GPIO_T[62]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(62),
O => GPIO_T(62)
);
\GPIO_T[63]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(63),
O => GPIO_T(63)
);
\GPIO_T[6]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(6),
O => GPIO_T(6)
);
\GPIO_T[7]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(7),
O => GPIO_T(7)
);
\GPIO_T[8]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(8),
O => GPIO_T(8)
);
\GPIO_T[9]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(9),
O => GPIO_T(9)
);
I2C0_SCL_T_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => I2C0_SCL_T_n,
O => I2C0_SCL_T
);
I2C0_SDA_T_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => I2C0_SDA_T_n,
O => I2C0_SDA_T
);
I2C1_SCL_T_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => I2C1_SCL_T_n,
O => I2C1_SCL_T
);
I2C1_SDA_T_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => I2C1_SDA_T_n,
O => I2C1_SDA_T
);
PS7_i: unisim.vcomponents.PS7
port map (
DDRA(14 downto 0) => buffered_DDR_Addr(14 downto 0),
DDRARB(3 downto 0) => DDR_ARB(3 downto 0),
DDRBA(2 downto 0) => buffered_DDR_BankAddr(2 downto 0),
DDRCASB => buffered_DDR_CAS_n,
DDRCKE => buffered_DDR_CKE,
DDRCKN => buffered_DDR_Clk_n,
DDRCKP => buffered_DDR_Clk,
DDRCSB => buffered_DDR_CS_n,
DDRDM(3 downto 0) => buffered_DDR_DM(3 downto 0),
DDRDQ(31 downto 0) => buffered_DDR_DQ(31 downto 0),
DDRDQSN(3 downto 0) => buffered_DDR_DQS_n(3 downto 0),
DDRDQSP(3 downto 0) => buffered_DDR_DQS(3 downto 0),
DDRDRSTB => buffered_DDR_DRSTB,
DDRODT => buffered_DDR_ODT,
DDRRASB => buffered_DDR_RAS_n,
DDRVRN => buffered_DDR_VRN,
DDRVRP => buffered_DDR_VRP,
DDRWEB => buffered_DDR_WEB,
DMA0ACLK => DMA0_ACLK,
DMA0DAREADY => DMA0_DAREADY,
DMA0DATYPE(1 downto 0) => DMA0_DATYPE(1 downto 0),
DMA0DAVALID => DMA0_DAVALID,
DMA0DRLAST => DMA0_DRLAST,
DMA0DRREADY => DMA0_DRREADY,
DMA0DRTYPE(1 downto 0) => DMA0_DRTYPE(1 downto 0),
DMA0DRVALID => DMA0_DRVALID,
DMA0RSTN => DMA0_RSTN,
DMA1ACLK => DMA1_ACLK,
DMA1DAREADY => DMA1_DAREADY,
DMA1DATYPE(1 downto 0) => DMA1_DATYPE(1 downto 0),
DMA1DAVALID => DMA1_DAVALID,
DMA1DRLAST => DMA1_DRLAST,
DMA1DRREADY => DMA1_DRREADY,
DMA1DRTYPE(1 downto 0) => DMA1_DRTYPE(1 downto 0),
DMA1DRVALID => DMA1_DRVALID,
DMA1RSTN => DMA1_RSTN,
DMA2ACLK => DMA2_ACLK,
DMA2DAREADY => DMA2_DAREADY,
DMA2DATYPE(1 downto 0) => DMA2_DATYPE(1 downto 0),
DMA2DAVALID => DMA2_DAVALID,
DMA2DRLAST => DMA2_DRLAST,
DMA2DRREADY => DMA2_DRREADY,
DMA2DRTYPE(1 downto 0) => DMA2_DRTYPE(1 downto 0),
DMA2DRVALID => DMA2_DRVALID,
DMA2RSTN => DMA2_RSTN,
DMA3ACLK => DMA3_ACLK,
DMA3DAREADY => DMA3_DAREADY,
DMA3DATYPE(1 downto 0) => DMA3_DATYPE(1 downto 0),
DMA3DAVALID => DMA3_DAVALID,
DMA3DRLAST => DMA3_DRLAST,
DMA3DRREADY => DMA3_DRREADY,
DMA3DRTYPE(1 downto 0) => DMA3_DRTYPE(1 downto 0),
DMA3DRVALID => DMA3_DRVALID,
DMA3RSTN => DMA3_RSTN,
EMIOCAN0PHYRX => CAN0_PHY_RX,
EMIOCAN0PHYTX => CAN0_PHY_TX,
EMIOCAN1PHYRX => CAN1_PHY_RX,
EMIOCAN1PHYTX => CAN1_PHY_TX,
EMIOENET0EXTINTIN => ENET0_EXT_INTIN,
EMIOENET0GMIICOL => '0',
EMIOENET0GMIICRS => '0',
EMIOENET0GMIIRXCLK => ENET0_GMII_RX_CLK,
EMIOENET0GMIIRXD(7 downto 0) => B"00000000",
EMIOENET0GMIIRXDV => '0',
EMIOENET0GMIIRXER => '0',
EMIOENET0GMIITXCLK => ENET0_GMII_TX_CLK,
EMIOENET0GMIITXD(7 downto 0) => NLW_PS7_i_EMIOENET0GMIITXD_UNCONNECTED(7 downto 0),
EMIOENET0GMIITXEN => NLW_PS7_i_EMIOENET0GMIITXEN_UNCONNECTED,
EMIOENET0GMIITXER => NLW_PS7_i_EMIOENET0GMIITXER_UNCONNECTED,
EMIOENET0MDIOI => ENET0_MDIO_I,
EMIOENET0MDIOMDC => ENET0_MDIO_MDC,
EMIOENET0MDIOO => ENET0_MDIO_O,
EMIOENET0MDIOTN => ENET0_MDIO_T_n,
EMIOENET0PTPDELAYREQRX => ENET0_PTP_DELAY_REQ_RX,
EMIOENET0PTPDELAYREQTX => ENET0_PTP_DELAY_REQ_TX,
EMIOENET0PTPPDELAYREQRX => ENET0_PTP_PDELAY_REQ_RX,
EMIOENET0PTPPDELAYREQTX => ENET0_PTP_PDELAY_REQ_TX,
EMIOENET0PTPPDELAYRESPRX => ENET0_PTP_PDELAY_RESP_RX,
EMIOENET0PTPPDELAYRESPTX => ENET0_PTP_PDELAY_RESP_TX,
EMIOENET0PTPSYNCFRAMERX => ENET0_PTP_SYNC_FRAME_RX,
EMIOENET0PTPSYNCFRAMETX => ENET0_PTP_SYNC_FRAME_TX,
EMIOENET0SOFRX => ENET0_SOF_RX,
EMIOENET0SOFTX => ENET0_SOF_TX,
EMIOENET1EXTINTIN => ENET1_EXT_INTIN,
EMIOENET1GMIICOL => '0',
EMIOENET1GMIICRS => '0',
EMIOENET1GMIIRXCLK => ENET1_GMII_RX_CLK,
EMIOENET1GMIIRXD(7 downto 0) => B"00000000",
EMIOENET1GMIIRXDV => '0',
EMIOENET1GMIIRXER => '0',
EMIOENET1GMIITXCLK => ENET1_GMII_TX_CLK,
EMIOENET1GMIITXD(7 downto 0) => NLW_PS7_i_EMIOENET1GMIITXD_UNCONNECTED(7 downto 0),
EMIOENET1GMIITXEN => NLW_PS7_i_EMIOENET1GMIITXEN_UNCONNECTED,
EMIOENET1GMIITXER => NLW_PS7_i_EMIOENET1GMIITXER_UNCONNECTED,
EMIOENET1MDIOI => ENET1_MDIO_I,
EMIOENET1MDIOMDC => ENET1_MDIO_MDC,
EMIOENET1MDIOO => ENET1_MDIO_O,
EMIOENET1MDIOTN => ENET1_MDIO_T_n,
EMIOENET1PTPDELAYREQRX => ENET1_PTP_DELAY_REQ_RX,
EMIOENET1PTPDELAYREQTX => ENET1_PTP_DELAY_REQ_TX,
EMIOENET1PTPPDELAYREQRX => ENET1_PTP_PDELAY_REQ_RX,
EMIOENET1PTPPDELAYREQTX => ENET1_PTP_PDELAY_REQ_TX,
EMIOENET1PTPPDELAYRESPRX => ENET1_PTP_PDELAY_RESP_RX,
EMIOENET1PTPPDELAYRESPTX => ENET1_PTP_PDELAY_RESP_TX,
EMIOENET1PTPSYNCFRAMERX => ENET1_PTP_SYNC_FRAME_RX,
EMIOENET1PTPSYNCFRAMETX => ENET1_PTP_SYNC_FRAME_TX,
EMIOENET1SOFRX => ENET1_SOF_RX,
EMIOENET1SOFTX => ENET1_SOF_TX,
EMIOGPIOI(63 downto 0) => GPIO_I(63 downto 0),
EMIOGPIOO(63 downto 0) => GPIO_O(63 downto 0),
EMIOGPIOTN(63 downto 0) => gpio_out_t_n(63 downto 0),
EMIOI2C0SCLI => I2C0_SCL_I,
EMIOI2C0SCLO => I2C0_SCL_O,
EMIOI2C0SCLTN => I2C0_SCL_T_n,
EMIOI2C0SDAI => I2C0_SDA_I,
EMIOI2C0SDAO => I2C0_SDA_O,
EMIOI2C0SDATN => I2C0_SDA_T_n,
EMIOI2C1SCLI => I2C1_SCL_I,
EMIOI2C1SCLO => I2C1_SCL_O,
EMIOI2C1SCLTN => I2C1_SCL_T_n,
EMIOI2C1SDAI => I2C1_SDA_I,
EMIOI2C1SDAO => I2C1_SDA_O,
EMIOI2C1SDATN => I2C1_SDA_T_n,
EMIOPJTAGTCK => PJTAG_TCK,
EMIOPJTAGTDI => PJTAG_TDI,
EMIOPJTAGTDO => NLW_PS7_i_EMIOPJTAGTDO_UNCONNECTED,
EMIOPJTAGTDTN => NLW_PS7_i_EMIOPJTAGTDTN_UNCONNECTED,
EMIOPJTAGTMS => PJTAG_TMS,
EMIOSDIO0BUSPOW => SDIO0_BUSPOW,
EMIOSDIO0BUSVOLT(2 downto 0) => SDIO0_BUSVOLT(2 downto 0),
EMIOSDIO0CDN => SDIO0_CDN,
EMIOSDIO0CLK => SDIO0_CLK,
EMIOSDIO0CLKFB => SDIO0_CLK_FB,
EMIOSDIO0CMDI => SDIO0_CMD_I,
EMIOSDIO0CMDO => SDIO0_CMD_O,
EMIOSDIO0CMDTN => SDIO0_CMD_T_n,
EMIOSDIO0DATAI(3 downto 0) => SDIO0_DATA_I(3 downto 0),
EMIOSDIO0DATAO(3 downto 0) => SDIO0_DATA_O(3 downto 0),
EMIOSDIO0DATATN(3 downto 0) => SDIO0_DATA_T_n(3 downto 0),
EMIOSDIO0LED => SDIO0_LED,
EMIOSDIO0WP => SDIO0_WP,
EMIOSDIO1BUSPOW => SDIO1_BUSPOW,
EMIOSDIO1BUSVOLT(2 downto 0) => SDIO1_BUSVOLT(2 downto 0),
EMIOSDIO1CDN => SDIO1_CDN,
EMIOSDIO1CLK => SDIO1_CLK,
EMIOSDIO1CLKFB => SDIO1_CLK_FB,
EMIOSDIO1CMDI => SDIO1_CMD_I,
EMIOSDIO1CMDO => SDIO1_CMD_O,
EMIOSDIO1CMDTN => SDIO1_CMD_T_n,
EMIOSDIO1DATAI(3 downto 0) => SDIO1_DATA_I(3 downto 0),
EMIOSDIO1DATAO(3 downto 0) => SDIO1_DATA_O(3 downto 0),
EMIOSDIO1DATATN(3 downto 0) => SDIO1_DATA_T_n(3 downto 0),
EMIOSDIO1LED => SDIO1_LED,
EMIOSDIO1WP => SDIO1_WP,
EMIOSPI0MI => SPI0_MISO_I,
EMIOSPI0MO => SPI0_MOSI_O,
EMIOSPI0MOTN => SPI0_MOSI_T_n,
EMIOSPI0SCLKI => SPI0_SCLK_I,
EMIOSPI0SCLKO => SPI0_SCLK_O,
EMIOSPI0SCLKTN => SPI0_SCLK_T_n,
EMIOSPI0SI => SPI0_MOSI_I,
EMIOSPI0SO => SPI0_MISO_O,
EMIOSPI0SSIN => SPI0_SS_I,
EMIOSPI0SSNTN => SPI0_SS_T_n,
EMIOSPI0SSON(2) => SPI0_SS2_O,
EMIOSPI0SSON(1) => SPI0_SS1_O,
EMIOSPI0SSON(0) => SPI0_SS_O,
EMIOSPI0STN => SPI0_MISO_T_n,
EMIOSPI1MI => SPI1_MISO_I,
EMIOSPI1MO => SPI1_MOSI_O,
EMIOSPI1MOTN => SPI1_MOSI_T_n,
EMIOSPI1SCLKI => SPI1_SCLK_I,
EMIOSPI1SCLKO => SPI1_SCLK_O,
EMIOSPI1SCLKTN => SPI1_SCLK_T_n,
EMIOSPI1SI => SPI1_MOSI_I,
EMIOSPI1SO => SPI1_MISO_O,
EMIOSPI1SSIN => SPI1_SS_I,
EMIOSPI1SSNTN => SPI1_SS_T_n,
EMIOSPI1SSON(2) => SPI1_SS2_O,
EMIOSPI1SSON(1) => SPI1_SS1_O,
EMIOSPI1SSON(0) => SPI1_SS_O,
EMIOSPI1STN => SPI1_MISO_T_n,
EMIOSRAMINTIN => SRAM_INTIN,
EMIOTRACECLK => TRACE_CLK,
EMIOTRACECTL => NLW_PS7_i_EMIOTRACECTL_UNCONNECTED,
EMIOTRACEDATA(31 downto 0) => NLW_PS7_i_EMIOTRACEDATA_UNCONNECTED(31 downto 0),
EMIOTTC0CLKI(2) => TTC0_CLK2_IN,
EMIOTTC0CLKI(1) => TTC0_CLK1_IN,
EMIOTTC0CLKI(0) => TTC0_CLK0_IN,
EMIOTTC0WAVEO(2) => TTC0_WAVE2_OUT,
EMIOTTC0WAVEO(1) => TTC0_WAVE1_OUT,
EMIOTTC0WAVEO(0) => TTC0_WAVE0_OUT,
EMIOTTC1CLKI(2) => TTC1_CLK2_IN,
EMIOTTC1CLKI(1) => TTC1_CLK1_IN,
EMIOTTC1CLKI(0) => TTC1_CLK0_IN,
EMIOTTC1WAVEO(2) => TTC1_WAVE2_OUT,
EMIOTTC1WAVEO(1) => TTC1_WAVE1_OUT,
EMIOTTC1WAVEO(0) => TTC1_WAVE0_OUT,
EMIOUART0CTSN => UART0_CTSN,
EMIOUART0DCDN => UART0_DCDN,
EMIOUART0DSRN => UART0_DSRN,
EMIOUART0DTRN => UART0_DTRN,
EMIOUART0RIN => UART0_RIN,
EMIOUART0RTSN => UART0_RTSN,
EMIOUART0RX => UART0_RX,
EMIOUART0TX => UART0_TX,
EMIOUART1CTSN => UART1_CTSN,
EMIOUART1DCDN => UART1_DCDN,
EMIOUART1DSRN => UART1_DSRN,
EMIOUART1DTRN => UART1_DTRN,
EMIOUART1RIN => UART1_RIN,
EMIOUART1RTSN => UART1_RTSN,
EMIOUART1RX => UART1_RX,
EMIOUART1TX => UART1_TX,
EMIOUSB0PORTINDCTL(1 downto 0) => USB0_PORT_INDCTL(1 downto 0),
EMIOUSB0VBUSPWRFAULT => USB0_VBUS_PWRFAULT,
EMIOUSB0VBUSPWRSELECT => USB0_VBUS_PWRSELECT,
EMIOUSB1PORTINDCTL(1 downto 0) => USB1_PORT_INDCTL(1 downto 0),
EMIOUSB1VBUSPWRFAULT => USB1_VBUS_PWRFAULT,
EMIOUSB1VBUSPWRSELECT => USB1_VBUS_PWRSELECT,
EMIOWDTCLKI => WDT_CLK_IN,
EMIOWDTRSTO => WDT_RST_OUT,
EVENTEVENTI => EVENT_EVENTI,
EVENTEVENTO => EVENT_EVENTO,
EVENTSTANDBYWFE(1 downto 0) => EVENT_STANDBYWFE(1 downto 0),
EVENTSTANDBYWFI(1 downto 0) => EVENT_STANDBYWFI(1 downto 0),
FCLKCLK(3) => FCLK_CLK3,
FCLKCLK(2) => FCLK_CLK2,
FCLKCLK(1) => FCLK_CLK1,
FCLKCLK(0) => FCLK_CLK_unbuffered(0),
FCLKCLKTRIGN(3 downto 0) => B"0000",
FCLKRESETN(3) => FCLK_RESET3_N,
FCLKRESETN(2) => FCLK_RESET2_N,
FCLKRESETN(1) => FCLK_RESET1_N,
FCLKRESETN(0) => FCLK_RESET0_N,
FPGAIDLEN => FPGA_IDLE_N,
FTMDTRACEINATID(3 downto 0) => B"0000",
FTMDTRACEINCLOCK => FTMD_TRACEIN_CLK,
FTMDTRACEINDATA(31 downto 0) => B"00000000000000000000000000000000",
FTMDTRACEINVALID => '0',
FTMTF2PDEBUG(31 downto 0) => FTMT_F2P_DEBUG(31 downto 0),
FTMTF2PTRIG(3) => FTMT_F2P_TRIG_3,
FTMTF2PTRIG(2) => FTMT_F2P_TRIG_2,
FTMTF2PTRIG(1) => FTMT_F2P_TRIG_1,
FTMTF2PTRIG(0) => FTMT_F2P_TRIG_0,
FTMTF2PTRIGACK(3) => FTMT_F2P_TRIGACK_3,
FTMTF2PTRIGACK(2) => FTMT_F2P_TRIGACK_2,
FTMTF2PTRIGACK(1) => FTMT_F2P_TRIGACK_1,
FTMTF2PTRIGACK(0) => FTMT_F2P_TRIGACK_0,
FTMTP2FDEBUG(31 downto 0) => FTMT_P2F_DEBUG(31 downto 0),
FTMTP2FTRIG(3) => FTMT_P2F_TRIG_3,
FTMTP2FTRIG(2) => FTMT_P2F_TRIG_2,
FTMTP2FTRIG(1) => FTMT_P2F_TRIG_1,
FTMTP2FTRIG(0) => FTMT_P2F_TRIG_0,
FTMTP2FTRIGACK(3) => FTMT_P2F_TRIGACK_3,
FTMTP2FTRIGACK(2) => FTMT_P2F_TRIGACK_2,
FTMTP2FTRIGACK(1) => FTMT_P2F_TRIGACK_1,
FTMTP2FTRIGACK(0) => FTMT_P2F_TRIGACK_0,
IRQF2P(19) => Core1_nFIQ,
IRQF2P(18) => Core0_nFIQ,
IRQF2P(17) => Core1_nIRQ,
IRQF2P(16) => Core0_nIRQ,
IRQF2P(15 downto 1) => B"000000000000000",
IRQF2P(0) => IRQ_F2P(0),
IRQP2F(28) => IRQ_P2F_DMAC_ABORT,
IRQP2F(27) => IRQ_P2F_DMAC7,
IRQP2F(26) => IRQ_P2F_DMAC6,
IRQP2F(25) => IRQ_P2F_DMAC5,
IRQP2F(24) => IRQ_P2F_DMAC4,
IRQP2F(23) => IRQ_P2F_DMAC3,
IRQP2F(22) => IRQ_P2F_DMAC2,
IRQP2F(21) => IRQ_P2F_DMAC1,
IRQP2F(20) => IRQ_P2F_DMAC0,
IRQP2F(19) => IRQ_P2F_SMC,
IRQP2F(18) => IRQ_P2F_QSPI,
IRQP2F(17) => IRQ_P2F_CTI,
IRQP2F(16) => IRQ_P2F_GPIO,
IRQP2F(15) => IRQ_P2F_USB0,
IRQP2F(14) => IRQ_P2F_ENET0,
IRQP2F(13) => IRQ_P2F_ENET_WAKE0,
IRQP2F(12) => IRQ_P2F_SDIO0,
IRQP2F(11) => IRQ_P2F_I2C0,
IRQP2F(10) => IRQ_P2F_SPI0,
IRQP2F(9) => IRQ_P2F_UART0,
IRQP2F(8) => IRQ_P2F_CAN0,
IRQP2F(7) => IRQ_P2F_USB1,
IRQP2F(6) => IRQ_P2F_ENET1,
IRQP2F(5) => IRQ_P2F_ENET_WAKE1,
IRQP2F(4) => IRQ_P2F_SDIO1,
IRQP2F(3) => IRQ_P2F_I2C1,
IRQP2F(2) => IRQ_P2F_SPI1,
IRQP2F(1) => IRQ_P2F_UART1,
IRQP2F(0) => IRQ_P2F_CAN1,
MAXIGP0ACLK => M_AXI_GP0_ACLK,
MAXIGP0ARADDR(31 downto 0) => M_AXI_GP0_ARADDR(31 downto 0),
MAXIGP0ARBURST(1 downto 0) => M_AXI_GP0_ARBURST(1 downto 0),
MAXIGP0ARCACHE(3 downto 0) => M_AXI_GP0_ARCACHE(3 downto 0),
MAXIGP0ARESETN => M_AXI_GP0_ARESETN,
MAXIGP0ARID(11 downto 0) => M_AXI_GP0_ARID(11 downto 0),
MAXIGP0ARLEN(3 downto 0) => M_AXI_GP0_ARLEN(3 downto 0),
MAXIGP0ARLOCK(1 downto 0) => M_AXI_GP0_ARLOCK(1 downto 0),
MAXIGP0ARPROT(2 downto 0) => M_AXI_GP0_ARPROT(2 downto 0),
MAXIGP0ARQOS(3 downto 0) => M_AXI_GP0_ARQOS(3 downto 0),
MAXIGP0ARREADY => M_AXI_GP0_ARREADY,
MAXIGP0ARSIZE(1 downto 0) => \^m_axi_gp0_arsize\(1 downto 0),
MAXIGP0ARVALID => M_AXI_GP0_ARVALID,
MAXIGP0AWADDR(31 downto 0) => M_AXI_GP0_AWADDR(31 downto 0),
MAXIGP0AWBURST(1 downto 0) => M_AXI_GP0_AWBURST(1 downto 0),
MAXIGP0AWCACHE(3 downto 0) => M_AXI_GP0_AWCACHE(3 downto 0),
MAXIGP0AWID(11 downto 0) => M_AXI_GP0_AWID(11 downto 0),
MAXIGP0AWLEN(3 downto 0) => M_AXI_GP0_AWLEN(3 downto 0),
MAXIGP0AWLOCK(1 downto 0) => M_AXI_GP0_AWLOCK(1 downto 0),
MAXIGP0AWPROT(2 downto 0) => M_AXI_GP0_AWPROT(2 downto 0),
MAXIGP0AWQOS(3 downto 0) => M_AXI_GP0_AWQOS(3 downto 0),
MAXIGP0AWREADY => M_AXI_GP0_AWREADY,
MAXIGP0AWSIZE(1 downto 0) => \^m_axi_gp0_awsize\(1 downto 0),
MAXIGP0AWVALID => M_AXI_GP0_AWVALID,
MAXIGP0BID(11 downto 0) => M_AXI_GP0_BID(11 downto 0),
MAXIGP0BREADY => M_AXI_GP0_BREADY,
MAXIGP0BRESP(1 downto 0) => M_AXI_GP0_BRESP(1 downto 0),
MAXIGP0BVALID => M_AXI_GP0_BVALID,
MAXIGP0RDATA(31 downto 0) => M_AXI_GP0_RDATA(31 downto 0),
MAXIGP0RID(11 downto 0) => M_AXI_GP0_RID(11 downto 0),
MAXIGP0RLAST => M_AXI_GP0_RLAST,
MAXIGP0RREADY => M_AXI_GP0_RREADY,
MAXIGP0RRESP(1 downto 0) => M_AXI_GP0_RRESP(1 downto 0),
MAXIGP0RVALID => M_AXI_GP0_RVALID,
MAXIGP0WDATA(31 downto 0) => M_AXI_GP0_WDATA(31 downto 0),
MAXIGP0WID(11 downto 0) => M_AXI_GP0_WID(11 downto 0),
MAXIGP0WLAST => M_AXI_GP0_WLAST,
MAXIGP0WREADY => M_AXI_GP0_WREADY,
MAXIGP0WSTRB(3 downto 0) => M_AXI_GP0_WSTRB(3 downto 0),
MAXIGP0WVALID => M_AXI_GP0_WVALID,
MAXIGP1ACLK => M_AXI_GP1_ACLK,
MAXIGP1ARADDR(31 downto 0) => M_AXI_GP1_ARADDR(31 downto 0),
MAXIGP1ARBURST(1 downto 0) => M_AXI_GP1_ARBURST(1 downto 0),
MAXIGP1ARCACHE(3 downto 0) => M_AXI_GP1_ARCACHE(3 downto 0),
MAXIGP1ARESETN => M_AXI_GP1_ARESETN,
MAXIGP1ARID(11 downto 0) => M_AXI_GP1_ARID(11 downto 0),
MAXIGP1ARLEN(3 downto 0) => M_AXI_GP1_ARLEN(3 downto 0),
MAXIGP1ARLOCK(1 downto 0) => M_AXI_GP1_ARLOCK(1 downto 0),
MAXIGP1ARPROT(2 downto 0) => M_AXI_GP1_ARPROT(2 downto 0),
MAXIGP1ARQOS(3 downto 0) => M_AXI_GP1_ARQOS(3 downto 0),
MAXIGP1ARREADY => M_AXI_GP1_ARREADY,
MAXIGP1ARSIZE(1 downto 0) => \^m_axi_gp1_arsize\(1 downto 0),
MAXIGP1ARVALID => M_AXI_GP1_ARVALID,
MAXIGP1AWADDR(31 downto 0) => M_AXI_GP1_AWADDR(31 downto 0),
MAXIGP1AWBURST(1 downto 0) => M_AXI_GP1_AWBURST(1 downto 0),
MAXIGP1AWCACHE(3 downto 0) => M_AXI_GP1_AWCACHE(3 downto 0),
MAXIGP1AWID(11 downto 0) => M_AXI_GP1_AWID(11 downto 0),
MAXIGP1AWLEN(3 downto 0) => M_AXI_GP1_AWLEN(3 downto 0),
MAXIGP1AWLOCK(1 downto 0) => M_AXI_GP1_AWLOCK(1 downto 0),
MAXIGP1AWPROT(2 downto 0) => M_AXI_GP1_AWPROT(2 downto 0),
MAXIGP1AWQOS(3 downto 0) => M_AXI_GP1_AWQOS(3 downto 0),
MAXIGP1AWREADY => M_AXI_GP1_AWREADY,
MAXIGP1AWSIZE(1 downto 0) => \^m_axi_gp1_awsize\(1 downto 0),
MAXIGP1AWVALID => M_AXI_GP1_AWVALID,
MAXIGP1BID(11 downto 0) => M_AXI_GP1_BID(11 downto 0),
MAXIGP1BREADY => M_AXI_GP1_BREADY,
MAXIGP1BRESP(1 downto 0) => M_AXI_GP1_BRESP(1 downto 0),
MAXIGP1BVALID => M_AXI_GP1_BVALID,
MAXIGP1RDATA(31 downto 0) => M_AXI_GP1_RDATA(31 downto 0),
MAXIGP1RID(11 downto 0) => M_AXI_GP1_RID(11 downto 0),
MAXIGP1RLAST => M_AXI_GP1_RLAST,
MAXIGP1RREADY => M_AXI_GP1_RREADY,
MAXIGP1RRESP(1 downto 0) => M_AXI_GP1_RRESP(1 downto 0),
MAXIGP1RVALID => M_AXI_GP1_RVALID,
MAXIGP1WDATA(31 downto 0) => M_AXI_GP1_WDATA(31 downto 0),
MAXIGP1WID(11 downto 0) => M_AXI_GP1_WID(11 downto 0),
MAXIGP1WLAST => M_AXI_GP1_WLAST,
MAXIGP1WREADY => M_AXI_GP1_WREADY,
MAXIGP1WSTRB(3 downto 0) => M_AXI_GP1_WSTRB(3 downto 0),
MAXIGP1WVALID => M_AXI_GP1_WVALID,
MIO(53 downto 0) => buffered_MIO(53 downto 0),
PSCLK => buffered_PS_CLK,
PSPORB => buffered_PS_PORB,
PSSRSTB => buffered_PS_SRSTB,
SAXIACPACLK => S_AXI_ACP_ACLK,
SAXIACPARADDR(31 downto 0) => S_AXI_ACP_ARADDR(31 downto 0),
SAXIACPARBURST(1 downto 0) => S_AXI_ACP_ARBURST(1 downto 0),
SAXIACPARCACHE(3 downto 0) => S_AXI_ACP_ARCACHE(3 downto 0),
SAXIACPARESETN => S_AXI_ACP_ARESETN,
SAXIACPARID(2 downto 0) => S_AXI_ACP_ARID(2 downto 0),
SAXIACPARLEN(3 downto 0) => S_AXI_ACP_ARLEN(3 downto 0),
SAXIACPARLOCK(1 downto 0) => S_AXI_ACP_ARLOCK(1 downto 0),
SAXIACPARPROT(2 downto 0) => S_AXI_ACP_ARPROT(2 downto 0),
SAXIACPARQOS(3 downto 0) => S_AXI_ACP_ARQOS(3 downto 0),
SAXIACPARREADY => S_AXI_ACP_ARREADY,
SAXIACPARSIZE(1 downto 0) => S_AXI_ACP_ARSIZE(1 downto 0),
SAXIACPARUSER(4 downto 0) => S_AXI_ACP_ARUSER(4 downto 0),
SAXIACPARVALID => S_AXI_ACP_ARVALID,
SAXIACPAWADDR(31 downto 0) => S_AXI_ACP_AWADDR(31 downto 0),
SAXIACPAWBURST(1 downto 0) => S_AXI_ACP_AWBURST(1 downto 0),
SAXIACPAWCACHE(3 downto 0) => S_AXI_ACP_AWCACHE(3 downto 0),
SAXIACPAWID(2 downto 0) => S_AXI_ACP_AWID(2 downto 0),
SAXIACPAWLEN(3 downto 0) => S_AXI_ACP_AWLEN(3 downto 0),
SAXIACPAWLOCK(1 downto 0) => S_AXI_ACP_AWLOCK(1 downto 0),
SAXIACPAWPROT(2 downto 0) => S_AXI_ACP_AWPROT(2 downto 0),
SAXIACPAWQOS(3 downto 0) => S_AXI_ACP_AWQOS(3 downto 0),
SAXIACPAWREADY => S_AXI_ACP_AWREADY,
SAXIACPAWSIZE(1 downto 0) => S_AXI_ACP_AWSIZE(1 downto 0),
SAXIACPAWUSER(4 downto 0) => S_AXI_ACP_AWUSER(4 downto 0),
SAXIACPAWVALID => S_AXI_ACP_AWVALID,
SAXIACPBID(2 downto 0) => S_AXI_ACP_BID(2 downto 0),
SAXIACPBREADY => S_AXI_ACP_BREADY,
SAXIACPBRESP(1 downto 0) => S_AXI_ACP_BRESP(1 downto 0),
SAXIACPBVALID => S_AXI_ACP_BVALID,
SAXIACPRDATA(63 downto 0) => S_AXI_ACP_RDATA(63 downto 0),
SAXIACPRID(2 downto 0) => S_AXI_ACP_RID(2 downto 0),
SAXIACPRLAST => S_AXI_ACP_RLAST,
SAXIACPRREADY => S_AXI_ACP_RREADY,
SAXIACPRRESP(1 downto 0) => S_AXI_ACP_RRESP(1 downto 0),
SAXIACPRVALID => S_AXI_ACP_RVALID,
SAXIACPWDATA(63 downto 0) => S_AXI_ACP_WDATA(63 downto 0),
SAXIACPWID(2 downto 0) => S_AXI_ACP_WID(2 downto 0),
SAXIACPWLAST => S_AXI_ACP_WLAST,
SAXIACPWREADY => S_AXI_ACP_WREADY,
SAXIACPWSTRB(7 downto 0) => S_AXI_ACP_WSTRB(7 downto 0),
SAXIACPWVALID => S_AXI_ACP_WVALID,
SAXIGP0ACLK => S_AXI_GP0_ACLK,
SAXIGP0ARADDR(31 downto 0) => S_AXI_GP0_ARADDR(31 downto 0),
SAXIGP0ARBURST(1 downto 0) => S_AXI_GP0_ARBURST(1 downto 0),
SAXIGP0ARCACHE(3 downto 0) => S_AXI_GP0_ARCACHE(3 downto 0),
SAXIGP0ARESETN => S_AXI_GP0_ARESETN,
SAXIGP0ARID(5 downto 0) => S_AXI_GP0_ARID(5 downto 0),
SAXIGP0ARLEN(3 downto 0) => S_AXI_GP0_ARLEN(3 downto 0),
SAXIGP0ARLOCK(1 downto 0) => S_AXI_GP0_ARLOCK(1 downto 0),
SAXIGP0ARPROT(2 downto 0) => S_AXI_GP0_ARPROT(2 downto 0),
SAXIGP0ARQOS(3 downto 0) => S_AXI_GP0_ARQOS(3 downto 0),
SAXIGP0ARREADY => S_AXI_GP0_ARREADY,
SAXIGP0ARSIZE(1 downto 0) => S_AXI_GP0_ARSIZE(1 downto 0),
SAXIGP0ARVALID => S_AXI_GP0_ARVALID,
SAXIGP0AWADDR(31 downto 0) => S_AXI_GP0_AWADDR(31 downto 0),
SAXIGP0AWBURST(1 downto 0) => S_AXI_GP0_AWBURST(1 downto 0),
SAXIGP0AWCACHE(3 downto 0) => S_AXI_GP0_AWCACHE(3 downto 0),
SAXIGP0AWID(5 downto 0) => S_AXI_GP0_AWID(5 downto 0),
SAXIGP0AWLEN(3 downto 0) => S_AXI_GP0_AWLEN(3 downto 0),
SAXIGP0AWLOCK(1 downto 0) => S_AXI_GP0_AWLOCK(1 downto 0),
SAXIGP0AWPROT(2 downto 0) => S_AXI_GP0_AWPROT(2 downto 0),
SAXIGP0AWQOS(3 downto 0) => S_AXI_GP0_AWQOS(3 downto 0),
SAXIGP0AWREADY => S_AXI_GP0_AWREADY,
SAXIGP0AWSIZE(1 downto 0) => S_AXI_GP0_AWSIZE(1 downto 0),
SAXIGP0AWVALID => S_AXI_GP0_AWVALID,
SAXIGP0BID(5 downto 0) => S_AXI_GP0_BID(5 downto 0),
SAXIGP0BREADY => S_AXI_GP0_BREADY,
SAXIGP0BRESP(1 downto 0) => S_AXI_GP0_BRESP(1 downto 0),
SAXIGP0BVALID => S_AXI_GP0_BVALID,
SAXIGP0RDATA(31 downto 0) => S_AXI_GP0_RDATA(31 downto 0),
SAXIGP0RID(5 downto 0) => S_AXI_GP0_RID(5 downto 0),
SAXIGP0RLAST => S_AXI_GP0_RLAST,
SAXIGP0RREADY => S_AXI_GP0_RREADY,
SAXIGP0RRESP(1 downto 0) => S_AXI_GP0_RRESP(1 downto 0),
SAXIGP0RVALID => S_AXI_GP0_RVALID,
SAXIGP0WDATA(31 downto 0) => S_AXI_GP0_WDATA(31 downto 0),
SAXIGP0WID(5 downto 0) => S_AXI_GP0_WID(5 downto 0),
SAXIGP0WLAST => S_AXI_GP0_WLAST,
SAXIGP0WREADY => S_AXI_GP0_WREADY,
SAXIGP0WSTRB(3 downto 0) => S_AXI_GP0_WSTRB(3 downto 0),
SAXIGP0WVALID => S_AXI_GP0_WVALID,
SAXIGP1ACLK => S_AXI_GP1_ACLK,
SAXIGP1ARADDR(31 downto 0) => S_AXI_GP1_ARADDR(31 downto 0),
SAXIGP1ARBURST(1 downto 0) => S_AXI_GP1_ARBURST(1 downto 0),
SAXIGP1ARCACHE(3 downto 0) => S_AXI_GP1_ARCACHE(3 downto 0),
SAXIGP1ARESETN => S_AXI_GP1_ARESETN,
SAXIGP1ARID(5 downto 0) => S_AXI_GP1_ARID(5 downto 0),
SAXIGP1ARLEN(3 downto 0) => S_AXI_GP1_ARLEN(3 downto 0),
SAXIGP1ARLOCK(1 downto 0) => S_AXI_GP1_ARLOCK(1 downto 0),
SAXIGP1ARPROT(2 downto 0) => S_AXI_GP1_ARPROT(2 downto 0),
SAXIGP1ARQOS(3 downto 0) => S_AXI_GP1_ARQOS(3 downto 0),
SAXIGP1ARREADY => S_AXI_GP1_ARREADY,
SAXIGP1ARSIZE(1 downto 0) => S_AXI_GP1_ARSIZE(1 downto 0),
SAXIGP1ARVALID => S_AXI_GP1_ARVALID,
SAXIGP1AWADDR(31 downto 0) => S_AXI_GP1_AWADDR(31 downto 0),
SAXIGP1AWBURST(1 downto 0) => S_AXI_GP1_AWBURST(1 downto 0),
SAXIGP1AWCACHE(3 downto 0) => S_AXI_GP1_AWCACHE(3 downto 0),
SAXIGP1AWID(5 downto 0) => S_AXI_GP1_AWID(5 downto 0),
SAXIGP1AWLEN(3 downto 0) => S_AXI_GP1_AWLEN(3 downto 0),
SAXIGP1AWLOCK(1 downto 0) => S_AXI_GP1_AWLOCK(1 downto 0),
SAXIGP1AWPROT(2 downto 0) => S_AXI_GP1_AWPROT(2 downto 0),
SAXIGP1AWQOS(3 downto 0) => S_AXI_GP1_AWQOS(3 downto 0),
SAXIGP1AWREADY => S_AXI_GP1_AWREADY,
SAXIGP1AWSIZE(1 downto 0) => S_AXI_GP1_AWSIZE(1 downto 0),
SAXIGP1AWVALID => S_AXI_GP1_AWVALID,
SAXIGP1BID(5 downto 0) => S_AXI_GP1_BID(5 downto 0),
SAXIGP1BREADY => S_AXI_GP1_BREADY,
SAXIGP1BRESP(1 downto 0) => S_AXI_GP1_BRESP(1 downto 0),
SAXIGP1BVALID => S_AXI_GP1_BVALID,
SAXIGP1RDATA(31 downto 0) => S_AXI_GP1_RDATA(31 downto 0),
SAXIGP1RID(5 downto 0) => S_AXI_GP1_RID(5 downto 0),
SAXIGP1RLAST => S_AXI_GP1_RLAST,
SAXIGP1RREADY => S_AXI_GP1_RREADY,
SAXIGP1RRESP(1 downto 0) => S_AXI_GP1_RRESP(1 downto 0),
SAXIGP1RVALID => S_AXI_GP1_RVALID,
SAXIGP1WDATA(31 downto 0) => S_AXI_GP1_WDATA(31 downto 0),
SAXIGP1WID(5 downto 0) => S_AXI_GP1_WID(5 downto 0),
SAXIGP1WLAST => S_AXI_GP1_WLAST,
SAXIGP1WREADY => S_AXI_GP1_WREADY,
SAXIGP1WSTRB(3 downto 0) => S_AXI_GP1_WSTRB(3 downto 0),
SAXIGP1WVALID => S_AXI_GP1_WVALID,
SAXIHP0ACLK => S_AXI_HP0_ACLK,
SAXIHP0ARADDR(31 downto 0) => S_AXI_HP0_ARADDR(31 downto 0),
SAXIHP0ARBURST(1 downto 0) => S_AXI_HP0_ARBURST(1 downto 0),
SAXIHP0ARCACHE(3 downto 0) => S_AXI_HP0_ARCACHE(3 downto 0),
SAXIHP0ARESETN => S_AXI_HP0_ARESETN,
SAXIHP0ARID(5 downto 0) => S_AXI_HP0_ARID(5 downto 0),
SAXIHP0ARLEN(3 downto 0) => S_AXI_HP0_ARLEN(3 downto 0),
SAXIHP0ARLOCK(1 downto 0) => S_AXI_HP0_ARLOCK(1 downto 0),
SAXIHP0ARPROT(2 downto 0) => S_AXI_HP0_ARPROT(2 downto 0),
SAXIHP0ARQOS(3 downto 0) => S_AXI_HP0_ARQOS(3 downto 0),
SAXIHP0ARREADY => S_AXI_HP0_ARREADY,
SAXIHP0ARSIZE(1 downto 0) => S_AXI_HP0_ARSIZE(1 downto 0),
SAXIHP0ARVALID => S_AXI_HP0_ARVALID,
SAXIHP0AWADDR(31 downto 0) => S_AXI_HP0_AWADDR(31 downto 0),
SAXIHP0AWBURST(1 downto 0) => S_AXI_HP0_AWBURST(1 downto 0),
SAXIHP0AWCACHE(3 downto 0) => S_AXI_HP0_AWCACHE(3 downto 0),
SAXIHP0AWID(5 downto 0) => S_AXI_HP0_AWID(5 downto 0),
SAXIHP0AWLEN(3 downto 0) => S_AXI_HP0_AWLEN(3 downto 0),
SAXIHP0AWLOCK(1 downto 0) => S_AXI_HP0_AWLOCK(1 downto 0),
SAXIHP0AWPROT(2 downto 0) => S_AXI_HP0_AWPROT(2 downto 0),
SAXIHP0AWQOS(3 downto 0) => S_AXI_HP0_AWQOS(3 downto 0),
SAXIHP0AWREADY => S_AXI_HP0_AWREADY,
SAXIHP0AWSIZE(1 downto 0) => S_AXI_HP0_AWSIZE(1 downto 0),
SAXIHP0AWVALID => S_AXI_HP0_AWVALID,
SAXIHP0BID(5 downto 0) => S_AXI_HP0_BID(5 downto 0),
SAXIHP0BREADY => S_AXI_HP0_BREADY,
SAXIHP0BRESP(1 downto 0) => S_AXI_HP0_BRESP(1 downto 0),
SAXIHP0BVALID => S_AXI_HP0_BVALID,
SAXIHP0RACOUNT(2 downto 0) => S_AXI_HP0_RACOUNT(2 downto 0),
SAXIHP0RCOUNT(7 downto 0) => S_AXI_HP0_RCOUNT(7 downto 0),
SAXIHP0RDATA(63 downto 0) => S_AXI_HP0_RDATA(63 downto 0),
SAXIHP0RDISSUECAP1EN => S_AXI_HP0_RDISSUECAP1_EN,
SAXIHP0RID(5 downto 0) => S_AXI_HP0_RID(5 downto 0),
SAXIHP0RLAST => S_AXI_HP0_RLAST,
SAXIHP0RREADY => S_AXI_HP0_RREADY,
SAXIHP0RRESP(1 downto 0) => S_AXI_HP0_RRESP(1 downto 0),
SAXIHP0RVALID => S_AXI_HP0_RVALID,
SAXIHP0WACOUNT(5 downto 0) => S_AXI_HP0_WACOUNT(5 downto 0),
SAXIHP0WCOUNT(7 downto 0) => S_AXI_HP0_WCOUNT(7 downto 0),
SAXIHP0WDATA(63 downto 0) => S_AXI_HP0_WDATA(63 downto 0),
SAXIHP0WID(5 downto 0) => S_AXI_HP0_WID(5 downto 0),
SAXIHP0WLAST => S_AXI_HP0_WLAST,
SAXIHP0WREADY => S_AXI_HP0_WREADY,
SAXIHP0WRISSUECAP1EN => S_AXI_HP0_WRISSUECAP1_EN,
SAXIHP0WSTRB(7 downto 0) => S_AXI_HP0_WSTRB(7 downto 0),
SAXIHP0WVALID => S_AXI_HP0_WVALID,
SAXIHP1ACLK => S_AXI_HP1_ACLK,
SAXIHP1ARADDR(31 downto 0) => S_AXI_HP1_ARADDR(31 downto 0),
SAXIHP1ARBURST(1 downto 0) => S_AXI_HP1_ARBURST(1 downto 0),
SAXIHP1ARCACHE(3 downto 0) => S_AXI_HP1_ARCACHE(3 downto 0),
SAXIHP1ARESETN => S_AXI_HP1_ARESETN,
SAXIHP1ARID(5 downto 0) => S_AXI_HP1_ARID(5 downto 0),
SAXIHP1ARLEN(3 downto 0) => S_AXI_HP1_ARLEN(3 downto 0),
SAXIHP1ARLOCK(1 downto 0) => S_AXI_HP1_ARLOCK(1 downto 0),
SAXIHP1ARPROT(2 downto 0) => S_AXI_HP1_ARPROT(2 downto 0),
SAXIHP1ARQOS(3 downto 0) => S_AXI_HP1_ARQOS(3 downto 0),
SAXIHP1ARREADY => S_AXI_HP1_ARREADY,
SAXIHP1ARSIZE(1 downto 0) => S_AXI_HP1_ARSIZE(1 downto 0),
SAXIHP1ARVALID => S_AXI_HP1_ARVALID,
SAXIHP1AWADDR(31 downto 0) => S_AXI_HP1_AWADDR(31 downto 0),
SAXIHP1AWBURST(1 downto 0) => S_AXI_HP1_AWBURST(1 downto 0),
SAXIHP1AWCACHE(3 downto 0) => S_AXI_HP1_AWCACHE(3 downto 0),
SAXIHP1AWID(5 downto 0) => S_AXI_HP1_AWID(5 downto 0),
SAXIHP1AWLEN(3 downto 0) => S_AXI_HP1_AWLEN(3 downto 0),
SAXIHP1AWLOCK(1 downto 0) => S_AXI_HP1_AWLOCK(1 downto 0),
SAXIHP1AWPROT(2 downto 0) => S_AXI_HP1_AWPROT(2 downto 0),
SAXIHP1AWQOS(3 downto 0) => S_AXI_HP1_AWQOS(3 downto 0),
SAXIHP1AWREADY => S_AXI_HP1_AWREADY,
SAXIHP1AWSIZE(1 downto 0) => S_AXI_HP1_AWSIZE(1 downto 0),
SAXIHP1AWVALID => S_AXI_HP1_AWVALID,
SAXIHP1BID(5 downto 0) => S_AXI_HP1_BID(5 downto 0),
SAXIHP1BREADY => S_AXI_HP1_BREADY,
SAXIHP1BRESP(1 downto 0) => S_AXI_HP1_BRESP(1 downto 0),
SAXIHP1BVALID => S_AXI_HP1_BVALID,
SAXIHP1RACOUNT(2 downto 0) => S_AXI_HP1_RACOUNT(2 downto 0),
SAXIHP1RCOUNT(7 downto 0) => S_AXI_HP1_RCOUNT(7 downto 0),
SAXIHP1RDATA(63 downto 0) => S_AXI_HP1_RDATA(63 downto 0),
SAXIHP1RDISSUECAP1EN => S_AXI_HP1_RDISSUECAP1_EN,
SAXIHP1RID(5 downto 0) => S_AXI_HP1_RID(5 downto 0),
SAXIHP1RLAST => S_AXI_HP1_RLAST,
SAXIHP1RREADY => S_AXI_HP1_RREADY,
SAXIHP1RRESP(1 downto 0) => S_AXI_HP1_RRESP(1 downto 0),
SAXIHP1RVALID => S_AXI_HP1_RVALID,
SAXIHP1WACOUNT(5 downto 0) => S_AXI_HP1_WACOUNT(5 downto 0),
SAXIHP1WCOUNT(7 downto 0) => S_AXI_HP1_WCOUNT(7 downto 0),
SAXIHP1WDATA(63 downto 0) => S_AXI_HP1_WDATA(63 downto 0),
SAXIHP1WID(5 downto 0) => S_AXI_HP1_WID(5 downto 0),
SAXIHP1WLAST => S_AXI_HP1_WLAST,
SAXIHP1WREADY => S_AXI_HP1_WREADY,
SAXIHP1WRISSUECAP1EN => S_AXI_HP1_WRISSUECAP1_EN,
SAXIHP1WSTRB(7 downto 0) => S_AXI_HP1_WSTRB(7 downto 0),
SAXIHP1WVALID => S_AXI_HP1_WVALID,
SAXIHP2ACLK => S_AXI_HP2_ACLK,
SAXIHP2ARADDR(31 downto 0) => S_AXI_HP2_ARADDR(31 downto 0),
SAXIHP2ARBURST(1 downto 0) => S_AXI_HP2_ARBURST(1 downto 0),
SAXIHP2ARCACHE(3 downto 0) => S_AXI_HP2_ARCACHE(3 downto 0),
SAXIHP2ARESETN => S_AXI_HP2_ARESETN,
SAXIHP2ARID(5 downto 0) => S_AXI_HP2_ARID(5 downto 0),
SAXIHP2ARLEN(3 downto 0) => S_AXI_HP2_ARLEN(3 downto 0),
SAXIHP2ARLOCK(1 downto 0) => S_AXI_HP2_ARLOCK(1 downto 0),
SAXIHP2ARPROT(2 downto 0) => S_AXI_HP2_ARPROT(2 downto 0),
SAXIHP2ARQOS(3 downto 0) => S_AXI_HP2_ARQOS(3 downto 0),
SAXIHP2ARREADY => S_AXI_HP2_ARREADY,
SAXIHP2ARSIZE(1 downto 0) => S_AXI_HP2_ARSIZE(1 downto 0),
SAXIHP2ARVALID => S_AXI_HP2_ARVALID,
SAXIHP2AWADDR(31 downto 0) => S_AXI_HP2_AWADDR(31 downto 0),
SAXIHP2AWBURST(1 downto 0) => S_AXI_HP2_AWBURST(1 downto 0),
SAXIHP2AWCACHE(3 downto 0) => S_AXI_HP2_AWCACHE(3 downto 0),
SAXIHP2AWID(5 downto 0) => S_AXI_HP2_AWID(5 downto 0),
SAXIHP2AWLEN(3 downto 0) => S_AXI_HP2_AWLEN(3 downto 0),
SAXIHP2AWLOCK(1 downto 0) => S_AXI_HP2_AWLOCK(1 downto 0),
SAXIHP2AWPROT(2 downto 0) => S_AXI_HP2_AWPROT(2 downto 0),
SAXIHP2AWQOS(3 downto 0) => S_AXI_HP2_AWQOS(3 downto 0),
SAXIHP2AWREADY => S_AXI_HP2_AWREADY,
SAXIHP2AWSIZE(1 downto 0) => S_AXI_HP2_AWSIZE(1 downto 0),
SAXIHP2AWVALID => S_AXI_HP2_AWVALID,
SAXIHP2BID(5 downto 0) => S_AXI_HP2_BID(5 downto 0),
SAXIHP2BREADY => S_AXI_HP2_BREADY,
SAXIHP2BRESP(1 downto 0) => S_AXI_HP2_BRESP(1 downto 0),
SAXIHP2BVALID => S_AXI_HP2_BVALID,
SAXIHP2RACOUNT(2 downto 0) => S_AXI_HP2_RACOUNT(2 downto 0),
SAXIHP2RCOUNT(7 downto 0) => S_AXI_HP2_RCOUNT(7 downto 0),
SAXIHP2RDATA(63 downto 0) => S_AXI_HP2_RDATA(63 downto 0),
SAXIHP2RDISSUECAP1EN => S_AXI_HP2_RDISSUECAP1_EN,
SAXIHP2RID(5 downto 0) => S_AXI_HP2_RID(5 downto 0),
SAXIHP2RLAST => S_AXI_HP2_RLAST,
SAXIHP2RREADY => S_AXI_HP2_RREADY,
SAXIHP2RRESP(1 downto 0) => S_AXI_HP2_RRESP(1 downto 0),
SAXIHP2RVALID => S_AXI_HP2_RVALID,
SAXIHP2WACOUNT(5 downto 0) => S_AXI_HP2_WACOUNT(5 downto 0),
SAXIHP2WCOUNT(7 downto 0) => S_AXI_HP2_WCOUNT(7 downto 0),
SAXIHP2WDATA(63 downto 0) => S_AXI_HP2_WDATA(63 downto 0),
SAXIHP2WID(5 downto 0) => S_AXI_HP2_WID(5 downto 0),
SAXIHP2WLAST => S_AXI_HP2_WLAST,
SAXIHP2WREADY => S_AXI_HP2_WREADY,
SAXIHP2WRISSUECAP1EN => S_AXI_HP2_WRISSUECAP1_EN,
SAXIHP2WSTRB(7 downto 0) => S_AXI_HP2_WSTRB(7 downto 0),
SAXIHP2WVALID => S_AXI_HP2_WVALID,
SAXIHP3ACLK => S_AXI_HP3_ACLK,
SAXIHP3ARADDR(31 downto 0) => S_AXI_HP3_ARADDR(31 downto 0),
SAXIHP3ARBURST(1 downto 0) => S_AXI_HP3_ARBURST(1 downto 0),
SAXIHP3ARCACHE(3 downto 0) => S_AXI_HP3_ARCACHE(3 downto 0),
SAXIHP3ARESETN => S_AXI_HP3_ARESETN,
SAXIHP3ARID(5 downto 0) => S_AXI_HP3_ARID(5 downto 0),
SAXIHP3ARLEN(3 downto 0) => S_AXI_HP3_ARLEN(3 downto 0),
SAXIHP3ARLOCK(1 downto 0) => S_AXI_HP3_ARLOCK(1 downto 0),
SAXIHP3ARPROT(2 downto 0) => S_AXI_HP3_ARPROT(2 downto 0),
SAXIHP3ARQOS(3 downto 0) => S_AXI_HP3_ARQOS(3 downto 0),
SAXIHP3ARREADY => S_AXI_HP3_ARREADY,
SAXIHP3ARSIZE(1 downto 0) => S_AXI_HP3_ARSIZE(1 downto 0),
SAXIHP3ARVALID => S_AXI_HP3_ARVALID,
SAXIHP3AWADDR(31 downto 0) => S_AXI_HP3_AWADDR(31 downto 0),
SAXIHP3AWBURST(1 downto 0) => S_AXI_HP3_AWBURST(1 downto 0),
SAXIHP3AWCACHE(3 downto 0) => S_AXI_HP3_AWCACHE(3 downto 0),
SAXIHP3AWID(5 downto 0) => S_AXI_HP3_AWID(5 downto 0),
SAXIHP3AWLEN(3 downto 0) => S_AXI_HP3_AWLEN(3 downto 0),
SAXIHP3AWLOCK(1 downto 0) => S_AXI_HP3_AWLOCK(1 downto 0),
SAXIHP3AWPROT(2 downto 0) => S_AXI_HP3_AWPROT(2 downto 0),
SAXIHP3AWQOS(3 downto 0) => S_AXI_HP3_AWQOS(3 downto 0),
SAXIHP3AWREADY => S_AXI_HP3_AWREADY,
SAXIHP3AWSIZE(1 downto 0) => S_AXI_HP3_AWSIZE(1 downto 0),
SAXIHP3AWVALID => S_AXI_HP3_AWVALID,
SAXIHP3BID(5 downto 0) => S_AXI_HP3_BID(5 downto 0),
SAXIHP3BREADY => S_AXI_HP3_BREADY,
SAXIHP3BRESP(1 downto 0) => S_AXI_HP3_BRESP(1 downto 0),
SAXIHP3BVALID => S_AXI_HP3_BVALID,
SAXIHP3RACOUNT(2 downto 0) => S_AXI_HP3_RACOUNT(2 downto 0),
SAXIHP3RCOUNT(7 downto 0) => S_AXI_HP3_RCOUNT(7 downto 0),
SAXIHP3RDATA(63 downto 0) => S_AXI_HP3_RDATA(63 downto 0),
SAXIHP3RDISSUECAP1EN => S_AXI_HP3_RDISSUECAP1_EN,
SAXIHP3RID(5 downto 0) => S_AXI_HP3_RID(5 downto 0),
SAXIHP3RLAST => S_AXI_HP3_RLAST,
SAXIHP3RREADY => S_AXI_HP3_RREADY,
SAXIHP3RRESP(1 downto 0) => S_AXI_HP3_RRESP(1 downto 0),
SAXIHP3RVALID => S_AXI_HP3_RVALID,
SAXIHP3WACOUNT(5 downto 0) => S_AXI_HP3_WACOUNT(5 downto 0),
SAXIHP3WCOUNT(7 downto 0) => S_AXI_HP3_WCOUNT(7 downto 0),
SAXIHP3WDATA(63 downto 0) => S_AXI_HP3_WDATA(63 downto 0),
SAXIHP3WID(5 downto 0) => S_AXI_HP3_WID(5 downto 0),
SAXIHP3WLAST => S_AXI_HP3_WLAST,
SAXIHP3WREADY => S_AXI_HP3_WREADY,
SAXIHP3WRISSUECAP1EN => S_AXI_HP3_WRISSUECAP1_EN,
SAXIHP3WSTRB(7 downto 0) => S_AXI_HP3_WSTRB(7 downto 0),
SAXIHP3WVALID => S_AXI_HP3_WVALID
);
PS_CLK_BIBUF: unisim.vcomponents.BIBUF
port map (
IO => buffered_PS_CLK,
PAD => PS_CLK
);
PS_PORB_BIBUF: unisim.vcomponents.BIBUF
port map (
IO => buffered_PS_PORB,
PAD => PS_PORB
);
PS_SRSTB_BIBUF: unisim.vcomponents.BIBUF
port map (
IO => buffered_PS_SRSTB,
PAD => PS_SRSTB
);
SDIO0_CMD_T_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => SDIO0_CMD_T_n,
O => SDIO0_CMD_T
);
\SDIO0_DATA_T[0]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => SDIO0_DATA_T_n(0),
O => SDIO0_DATA_T(0)
);
\SDIO0_DATA_T[1]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => SDIO0_DATA_T_n(1),
O => SDIO0_DATA_T(1)
);
\SDIO0_DATA_T[2]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => SDIO0_DATA_T_n(2),
O => SDIO0_DATA_T(2)
);
\SDIO0_DATA_T[3]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => SDIO0_DATA_T_n(3),
O => SDIO0_DATA_T(3)
);
SDIO1_CMD_T_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => SDIO1_CMD_T_n,
O => SDIO1_CMD_T
);
\SDIO1_DATA_T[0]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => SDIO1_DATA_T_n(0),
O => SDIO1_DATA_T(0)
);
\SDIO1_DATA_T[1]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => SDIO1_DATA_T_n(1),
O => SDIO1_DATA_T(1)
);
\SDIO1_DATA_T[2]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => SDIO1_DATA_T_n(2),
O => SDIO1_DATA_T(2)
);
\SDIO1_DATA_T[3]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => SDIO1_DATA_T_n(3),
O => SDIO1_DATA_T(3)
);
SPI0_MISO_T_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => SPI0_MISO_T_n,
O => SPI0_MISO_T
);
SPI0_MOSI_T_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => SPI0_MOSI_T_n,
O => SPI0_MOSI_T
);
SPI0_SCLK_T_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => SPI0_SCLK_T_n,
O => SPI0_SCLK_T
);
SPI0_SS_T_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => SPI0_SS_T_n,
O => SPI0_SS_T
);
SPI1_MISO_T_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => SPI1_MISO_T_n,
O => SPI1_MISO_T
);
SPI1_MOSI_T_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => SPI1_MOSI_T_n,
O => SPI1_MOSI_T
);
SPI1_SCLK_T_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => SPI1_SCLK_T_n,
O => SPI1_SCLK_T
);
SPI1_SS_T_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => SPI1_SS_T_n,
O => SPI1_SS_T
);
\buffer_fclk_clk_0.FCLK_CLK_0_BUFG\: unisim.vcomponents.BUFG
port map (
I => FCLK_CLK_unbuffered(0),
O => FCLK_CLK0
);
\genblk13[0].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(0),
PAD => MIO(0)
);
\genblk13[10].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(10),
PAD => MIO(10)
);
\genblk13[11].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(11),
PAD => MIO(11)
);
\genblk13[12].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(12),
PAD => MIO(12)
);
\genblk13[13].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(13),
PAD => MIO(13)
);
\genblk13[14].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(14),
PAD => MIO(14)
);
\genblk13[15].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(15),
PAD => MIO(15)
);
\genblk13[16].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(16),
PAD => MIO(16)
);
\genblk13[17].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(17),
PAD => MIO(17)
);
\genblk13[18].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(18),
PAD => MIO(18)
);
\genblk13[19].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(19),
PAD => MIO(19)
);
\genblk13[1].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(1),
PAD => MIO(1)
);
\genblk13[20].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(20),
PAD => MIO(20)
);
\genblk13[21].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(21),
PAD => MIO(21)
);
\genblk13[22].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(22),
PAD => MIO(22)
);
\genblk13[23].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(23),
PAD => MIO(23)
);
\genblk13[24].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(24),
PAD => MIO(24)
);
\genblk13[25].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(25),
PAD => MIO(25)
);
\genblk13[26].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(26),
PAD => MIO(26)
);
\genblk13[27].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(27),
PAD => MIO(27)
);
\genblk13[28].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(28),
PAD => MIO(28)
);
\genblk13[29].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(29),
PAD => MIO(29)
);
\genblk13[2].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(2),
PAD => MIO(2)
);
\genblk13[30].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(30),
PAD => MIO(30)
);
\genblk13[31].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(31),
PAD => MIO(31)
);
\genblk13[32].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(32),
PAD => MIO(32)
);
\genblk13[33].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(33),
PAD => MIO(33)
);
\genblk13[34].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(34),
PAD => MIO(34)
);
\genblk13[35].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(35),
PAD => MIO(35)
);
\genblk13[36].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(36),
PAD => MIO(36)
);
\genblk13[37].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(37),
PAD => MIO(37)
);
\genblk13[38].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(38),
PAD => MIO(38)
);
\genblk13[39].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(39),
PAD => MIO(39)
);
\genblk13[3].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(3),
PAD => MIO(3)
);
\genblk13[40].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(40),
PAD => MIO(40)
);
\genblk13[41].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(41),
PAD => MIO(41)
);
\genblk13[42].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(42),
PAD => MIO(42)
);
\genblk13[43].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(43),
PAD => MIO(43)
);
\genblk13[44].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(44),
PAD => MIO(44)
);
\genblk13[45].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(45),
PAD => MIO(45)
);
\genblk13[46].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(46),
PAD => MIO(46)
);
\genblk13[47].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(47),
PAD => MIO(47)
);
\genblk13[48].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(48),
PAD => MIO(48)
);
\genblk13[49].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(49),
PAD => MIO(49)
);
\genblk13[4].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(4),
PAD => MIO(4)
);
\genblk13[50].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(50),
PAD => MIO(50)
);
\genblk13[51].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(51),
PAD => MIO(51)
);
\genblk13[52].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(52),
PAD => MIO(52)
);
\genblk13[53].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(53),
PAD => MIO(53)
);
\genblk13[5].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(5),
PAD => MIO(5)
);
\genblk13[6].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(6),
PAD => MIO(6)
);
\genblk13[7].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(7),
PAD => MIO(7)
);
\genblk13[8].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(8),
PAD => MIO(8)
);
\genblk13[9].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(9),
PAD => MIO(9)
);
\genblk14[0].DDR_BankAddr_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_BankAddr(0),
PAD => DDR_BankAddr(0)
);
\genblk14[1].DDR_BankAddr_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_BankAddr(1),
PAD => DDR_BankAddr(1)
);
\genblk14[2].DDR_BankAddr_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_BankAddr(2),
PAD => DDR_BankAddr(2)
);
\genblk15[0].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_Addr(0),
PAD => DDR_Addr(0)
);
\genblk15[10].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_Addr(10),
PAD => DDR_Addr(10)
);
\genblk15[11].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_Addr(11),
PAD => DDR_Addr(11)
);
\genblk15[12].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_Addr(12),
PAD => DDR_Addr(12)
);
\genblk15[13].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_Addr(13),
PAD => DDR_Addr(13)
);
\genblk15[14].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_Addr(14),
PAD => DDR_Addr(14)
);
\genblk15[1].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_Addr(1),
PAD => DDR_Addr(1)
);
\genblk15[2].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_Addr(2),
PAD => DDR_Addr(2)
);
\genblk15[3].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_Addr(3),
PAD => DDR_Addr(3)
);
\genblk15[4].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_Addr(4),
PAD => DDR_Addr(4)
);
\genblk15[5].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_Addr(5),
PAD => DDR_Addr(5)
);
\genblk15[6].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_Addr(6),
PAD => DDR_Addr(6)
);
\genblk15[7].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_Addr(7),
PAD => DDR_Addr(7)
);
\genblk15[8].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_Addr(8),
PAD => DDR_Addr(8)
);
\genblk15[9].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_Addr(9),
PAD => DDR_Addr(9)
);
\genblk16[0].DDR_DM_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DM(0),
PAD => DDR_DM(0)
);
\genblk16[1].DDR_DM_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DM(1),
PAD => DDR_DM(1)
);
\genblk16[2].DDR_DM_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DM(2),
PAD => DDR_DM(2)
);
\genblk16[3].DDR_DM_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DM(3),
PAD => DDR_DM(3)
);
\genblk17[0].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(0),
PAD => DDR_DQ(0)
);
\genblk17[10].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(10),
PAD => DDR_DQ(10)
);
\genblk17[11].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(11),
PAD => DDR_DQ(11)
);
\genblk17[12].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(12),
PAD => DDR_DQ(12)
);
\genblk17[13].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(13),
PAD => DDR_DQ(13)
);
\genblk17[14].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(14),
PAD => DDR_DQ(14)
);
\genblk17[15].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(15),
PAD => DDR_DQ(15)
);
\genblk17[16].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(16),
PAD => DDR_DQ(16)
);
\genblk17[17].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(17),
PAD => DDR_DQ(17)
);
\genblk17[18].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(18),
PAD => DDR_DQ(18)
);
\genblk17[19].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(19),
PAD => DDR_DQ(19)
);
\genblk17[1].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(1),
PAD => DDR_DQ(1)
);
\genblk17[20].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(20),
PAD => DDR_DQ(20)
);
\genblk17[21].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(21),
PAD => DDR_DQ(21)
);
\genblk17[22].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(22),
PAD => DDR_DQ(22)
);
\genblk17[23].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(23),
PAD => DDR_DQ(23)
);
\genblk17[24].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(24),
PAD => DDR_DQ(24)
);
\genblk17[25].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(25),
PAD => DDR_DQ(25)
);
\genblk17[26].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(26),
PAD => DDR_DQ(26)
);
\genblk17[27].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(27),
PAD => DDR_DQ(27)
);
\genblk17[28].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(28),
PAD => DDR_DQ(28)
);
\genblk17[29].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(29),
PAD => DDR_DQ(29)
);
\genblk17[2].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(2),
PAD => DDR_DQ(2)
);
\genblk17[30].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(30),
PAD => DDR_DQ(30)
);
\genblk17[31].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(31),
PAD => DDR_DQ(31)
);
\genblk17[3].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(3),
PAD => DDR_DQ(3)
);
\genblk17[4].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(4),
PAD => DDR_DQ(4)
);
\genblk17[5].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(5),
PAD => DDR_DQ(5)
);
\genblk17[6].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(6),
PAD => DDR_DQ(6)
);
\genblk17[7].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(7),
PAD => DDR_DQ(7)
);
\genblk17[8].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(8),
PAD => DDR_DQ(8)
);
\genblk17[9].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(9),
PAD => DDR_DQ(9)
);
\genblk18[0].DDR_DQS_n_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQS_n(0),
PAD => DDR_DQS_n(0)
);
\genblk18[1].DDR_DQS_n_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQS_n(1),
PAD => DDR_DQS_n(1)
);
\genblk18[2].DDR_DQS_n_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQS_n(2),
PAD => DDR_DQS_n(2)
);
\genblk18[3].DDR_DQS_n_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQS_n(3),
PAD => DDR_DQS_n(3)
);
\genblk19[0].DDR_DQS_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQS(0),
PAD => DDR_DQS(0)
);
\genblk19[1].DDR_DQS_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQS(1),
PAD => DDR_DQS(1)
);
\genblk19[2].DDR_DQS_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQS(2),
PAD => DDR_DQS(2)
);
\genblk19[3].DDR_DQS_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQS(3),
PAD => DDR_DQS(3)
);
i_0: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_CTL_PIPE[0]\
);
i_1: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_DATA_PIPE[0]\(1)
);
i_10: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_DATA_PIPE[7]\(1)
);
i_11: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_DATA_PIPE[7]\(0)
);
i_12: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_DATA_PIPE[6]\(1)
);
i_13: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_DATA_PIPE[6]\(0)
);
i_14: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_DATA_PIPE[5]\(1)
);
i_15: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_DATA_PIPE[5]\(0)
);
i_16: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_DATA_PIPE[4]\(1)
);
i_17: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_DATA_PIPE[4]\(0)
);
i_18: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_DATA_PIPE[3]\(1)
);
i_19: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_DATA_PIPE[3]\(0)
);
i_2: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_DATA_PIPE[0]\(0)
);
i_20: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_DATA_PIPE[2]\(1)
);
i_21: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_DATA_PIPE[2]\(0)
);
i_22: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_DATA_PIPE[1]\(1)
);
i_23: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_DATA_PIPE[1]\(0)
);
i_3: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_CTL_PIPE[7]\
);
i_4: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_CTL_PIPE[6]\
);
i_5: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_CTL_PIPE[5]\
);
i_6: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_CTL_PIPE[4]\
);
i_7: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_CTL_PIPE[3]\
);
i_8: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_CTL_PIPE[2]\
);
i_9: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_CTL_PIPE[1]\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
port (
SDIO0_WP : in STD_LOGIC;
TTC0_WAVE0_OUT : out STD_LOGIC;
TTC0_WAVE1_OUT : out STD_LOGIC;
TTC0_WAVE2_OUT : out STD_LOGIC;
USB0_PORT_INDCTL : out STD_LOGIC_VECTOR ( 1 downto 0 );
USB0_VBUS_PWRSELECT : out STD_LOGIC;
USB0_VBUS_PWRFAULT : in STD_LOGIC;
M_AXI_GP0_ARVALID : out STD_LOGIC;
M_AXI_GP0_AWVALID : out STD_LOGIC;
M_AXI_GP0_BREADY : out STD_LOGIC;
M_AXI_GP0_RREADY : out STD_LOGIC;
M_AXI_GP0_WLAST : out STD_LOGIC;
M_AXI_GP0_WVALID : out STD_LOGIC;
M_AXI_GP0_ARID : out STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_AWID : out STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_WID : out STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_ARBURST : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_ARLOCK : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_ARSIZE : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP0_AWBURST : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_AWLOCK : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_AWSIZE : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP0_ARPROT : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP0_AWPROT : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP0_ARADDR : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_GP0_AWADDR : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_GP0_WDATA : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_GP0_ARCACHE : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_ARLEN : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_ARQOS : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_AWCACHE : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_AWLEN : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_AWQOS : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_WSTRB : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_ACLK : in STD_LOGIC;
M_AXI_GP0_ARREADY : in STD_LOGIC;
M_AXI_GP0_AWREADY : in STD_LOGIC;
M_AXI_GP0_BVALID : in STD_LOGIC;
M_AXI_GP0_RLAST : in STD_LOGIC;
M_AXI_GP0_RVALID : in STD_LOGIC;
M_AXI_GP0_WREADY : in STD_LOGIC;
M_AXI_GP0_BID : in STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_RID : in STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_BRESP : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_RRESP : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_RDATA : in STD_LOGIC_VECTOR ( 31 downto 0 );
IRQ_F2P : in STD_LOGIC_VECTOR ( 0 to 0 );
FCLK_CLK0 : out STD_LOGIC;
FCLK_RESET0_N : out STD_LOGIC;
MIO : inout STD_LOGIC_VECTOR ( 53 downto 0 );
DDR_CAS_n : inout STD_LOGIC;
DDR_CKE : inout STD_LOGIC;
DDR_Clk_n : inout STD_LOGIC;
DDR_Clk : inout STD_LOGIC;
DDR_CS_n : inout STD_LOGIC;
DDR_DRSTB : inout STD_LOGIC;
DDR_ODT : inout STD_LOGIC;
DDR_RAS_n : inout STD_LOGIC;
DDR_WEB : inout STD_LOGIC;
DDR_BankAddr : inout STD_LOGIC_VECTOR ( 2 downto 0 );
DDR_Addr : inout STD_LOGIC_VECTOR ( 14 downto 0 );
DDR_VRN : inout STD_LOGIC;
DDR_VRP : inout STD_LOGIC;
DDR_DM : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_DQ : inout STD_LOGIC_VECTOR ( 31 downto 0 );
DDR_DQS_n : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_DQS : inout STD_LOGIC_VECTOR ( 3 downto 0 );
PS_SRSTB : inout STD_LOGIC;
PS_CLK : inout STD_LOGIC;
PS_PORB : inout STD_LOGIC
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is true;
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "zybo_zynq_design_processing_system7_0_0,processing_system7_v5_5_processing_system7,{}";
attribute DowngradeIPIdentifiedWarnings : string;
attribute DowngradeIPIdentifiedWarnings of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "yes";
attribute X_CORE_INFO : string;
attribute X_CORE_INFO of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "processing_system7_v5_5_processing_system7,Vivado 2018.2";
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
signal NLW_inst_CAN0_PHY_TX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_CAN1_PHY_TX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_DMA0_DAVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_DMA0_DRREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_DMA0_RSTN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_DMA1_DAVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_DMA1_DRREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_DMA1_RSTN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_DMA2_DAVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_DMA2_DRREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_DMA2_RSTN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_DMA3_DAVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_DMA3_DRREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_DMA3_RSTN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET0_GMII_TX_EN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET0_GMII_TX_ER_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET0_MDIO_MDC_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET0_MDIO_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET0_MDIO_T_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET0_PTP_DELAY_REQ_RX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET0_PTP_DELAY_REQ_TX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET0_PTP_PDELAY_REQ_RX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET0_PTP_PDELAY_REQ_TX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET0_PTP_PDELAY_RESP_RX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET0_PTP_PDELAY_RESP_TX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET0_PTP_SYNC_FRAME_RX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET0_PTP_SYNC_FRAME_TX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET0_SOF_RX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET0_SOF_TX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET1_GMII_TX_EN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET1_GMII_TX_ER_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET1_MDIO_MDC_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET1_MDIO_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET1_MDIO_T_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET1_PTP_DELAY_REQ_RX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET1_PTP_DELAY_REQ_TX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET1_PTP_PDELAY_REQ_RX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET1_PTP_PDELAY_REQ_TX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET1_PTP_PDELAY_RESP_RX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET1_PTP_PDELAY_RESP_TX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET1_PTP_SYNC_FRAME_RX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET1_PTP_SYNC_FRAME_TX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET1_SOF_RX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET1_SOF_TX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_EVENT_EVENTO_UNCONNECTED : STD_LOGIC;
signal NLW_inst_FCLK_CLK1_UNCONNECTED : STD_LOGIC;
signal NLW_inst_FCLK_CLK2_UNCONNECTED : STD_LOGIC;
signal NLW_inst_FCLK_CLK3_UNCONNECTED : STD_LOGIC;
signal NLW_inst_FCLK_RESET1_N_UNCONNECTED : STD_LOGIC;
signal NLW_inst_FCLK_RESET2_N_UNCONNECTED : STD_LOGIC;
signal NLW_inst_FCLK_RESET3_N_UNCONNECTED : STD_LOGIC;
signal NLW_inst_FTMT_F2P_TRIGACK_0_UNCONNECTED : STD_LOGIC;
signal NLW_inst_FTMT_F2P_TRIGACK_1_UNCONNECTED : STD_LOGIC;
signal NLW_inst_FTMT_F2P_TRIGACK_2_UNCONNECTED : STD_LOGIC;
signal NLW_inst_FTMT_F2P_TRIGACK_3_UNCONNECTED : STD_LOGIC;
signal NLW_inst_FTMT_P2F_TRIG_0_UNCONNECTED : STD_LOGIC;
signal NLW_inst_FTMT_P2F_TRIG_1_UNCONNECTED : STD_LOGIC;
signal NLW_inst_FTMT_P2F_TRIG_2_UNCONNECTED : STD_LOGIC;
signal NLW_inst_FTMT_P2F_TRIG_3_UNCONNECTED : STD_LOGIC;
signal NLW_inst_I2C0_SCL_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_I2C0_SCL_T_UNCONNECTED : STD_LOGIC;
signal NLW_inst_I2C0_SDA_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_I2C0_SDA_T_UNCONNECTED : STD_LOGIC;
signal NLW_inst_I2C1_SCL_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_I2C1_SCL_T_UNCONNECTED : STD_LOGIC;
signal NLW_inst_I2C1_SDA_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_I2C1_SDA_T_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_CAN0_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_CAN1_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_CTI_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_DMAC0_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_DMAC1_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_DMAC2_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_DMAC3_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_DMAC4_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_DMAC5_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_DMAC6_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_DMAC7_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_DMAC_ABORT_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_ENET0_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_ENET1_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_ENET_WAKE0_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_ENET_WAKE1_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_GPIO_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_I2C0_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_I2C1_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_QSPI_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_SDIO0_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_SDIO1_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_SMC_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_SPI0_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_SPI1_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_UART0_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_UART1_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_USB0_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_USB1_UNCONNECTED : STD_LOGIC;
signal NLW_inst_M_AXI_GP0_ARESETN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_M_AXI_GP1_ARESETN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_M_AXI_GP1_ARVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_M_AXI_GP1_AWVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_M_AXI_GP1_BREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_M_AXI_GP1_RREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_M_AXI_GP1_WLAST_UNCONNECTED : STD_LOGIC;
signal NLW_inst_M_AXI_GP1_WVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_PJTAG_TDO_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SDIO0_BUSPOW_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SDIO0_CLK_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SDIO0_CMD_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SDIO0_CMD_T_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SDIO0_LED_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SDIO1_BUSPOW_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SDIO1_CLK_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SDIO1_CMD_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SDIO1_CMD_T_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SDIO1_LED_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI0_MISO_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI0_MISO_T_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI0_MOSI_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI0_MOSI_T_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI0_SCLK_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI0_SCLK_T_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI0_SS1_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI0_SS2_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI0_SS_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI0_SS_T_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI1_MISO_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI1_MISO_T_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI1_MOSI_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI1_MOSI_T_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI1_SCLK_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI1_SCLK_T_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI1_SS1_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI1_SS2_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI1_SS_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI1_SS_T_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_ACP_ARESETN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_ACP_ARREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_ACP_AWREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_ACP_BVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_ACP_RLAST_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_ACP_RVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_ACP_WREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_GP0_ARESETN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_GP0_ARREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_GP0_AWREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_GP0_BVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_GP0_RLAST_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_GP0_RVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_GP0_WREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_GP1_ARESETN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_GP1_ARREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_GP1_AWREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_GP1_BVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_GP1_RLAST_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_GP1_RVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_GP1_WREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP0_ARESETN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP0_ARREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP0_AWREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP0_BVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP0_RLAST_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP0_RVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP0_WREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP1_ARESETN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP1_ARREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP1_AWREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP1_BVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP1_RLAST_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP1_RVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP1_WREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP2_ARESETN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP2_ARREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP2_AWREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP2_BVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP2_RLAST_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP2_RVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP2_WREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP3_ARESETN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP3_ARREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP3_AWREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP3_BVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP3_RLAST_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP3_RVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP3_WREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_TRACE_CLK_OUT_UNCONNECTED : STD_LOGIC;
signal NLW_inst_TRACE_CTL_UNCONNECTED : STD_LOGIC;
signal NLW_inst_TTC1_WAVE0_OUT_UNCONNECTED : STD_LOGIC;
signal NLW_inst_TTC1_WAVE1_OUT_UNCONNECTED : STD_LOGIC;
signal NLW_inst_TTC1_WAVE2_OUT_UNCONNECTED : STD_LOGIC;
signal NLW_inst_UART0_DTRN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_UART0_RTSN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_UART0_TX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_UART1_DTRN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_UART1_RTSN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_UART1_TX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_USB1_VBUS_PWRSELECT_UNCONNECTED : STD_LOGIC;
signal NLW_inst_WDT_RST_OUT_UNCONNECTED : STD_LOGIC;
signal NLW_inst_DMA0_DATYPE_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_DMA1_DATYPE_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_DMA2_DATYPE_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_DMA3_DATYPE_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_ENET0_GMII_TXD_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_inst_ENET1_GMII_TXD_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_inst_EVENT_STANDBYWFE_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_EVENT_STANDBYWFI_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_FTMT_P2F_DEBUG_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_inst_GPIO_O_UNCONNECTED : STD_LOGIC_VECTOR ( 63 downto 0 );
signal NLW_inst_GPIO_T_UNCONNECTED : STD_LOGIC_VECTOR ( 63 downto 0 );
signal NLW_inst_M_AXI_GP1_ARADDR_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_inst_M_AXI_GP1_ARBURST_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_M_AXI_GP1_ARCACHE_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_inst_M_AXI_GP1_ARID_UNCONNECTED : STD_LOGIC_VECTOR ( 11 downto 0 );
signal NLW_inst_M_AXI_GP1_ARLEN_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_inst_M_AXI_GP1_ARLOCK_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_M_AXI_GP1_ARPROT_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_inst_M_AXI_GP1_ARQOS_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_inst_M_AXI_GP1_ARSIZE_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_inst_M_AXI_GP1_AWADDR_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_inst_M_AXI_GP1_AWBURST_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_M_AXI_GP1_AWCACHE_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_inst_M_AXI_GP1_AWID_UNCONNECTED : STD_LOGIC_VECTOR ( 11 downto 0 );
signal NLW_inst_M_AXI_GP1_AWLEN_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_inst_M_AXI_GP1_AWLOCK_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_M_AXI_GP1_AWPROT_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_inst_M_AXI_GP1_AWQOS_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_inst_M_AXI_GP1_AWSIZE_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_inst_M_AXI_GP1_WDATA_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_inst_M_AXI_GP1_WID_UNCONNECTED : STD_LOGIC_VECTOR ( 11 downto 0 );
signal NLW_inst_M_AXI_GP1_WSTRB_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_inst_SDIO0_BUSVOLT_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_inst_SDIO0_DATA_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_inst_SDIO0_DATA_T_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_inst_SDIO1_BUSVOLT_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_inst_SDIO1_DATA_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_inst_SDIO1_DATA_T_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_inst_S_AXI_ACP_BID_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_inst_S_AXI_ACP_BRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_S_AXI_ACP_RDATA_UNCONNECTED : STD_LOGIC_VECTOR ( 63 downto 0 );
signal NLW_inst_S_AXI_ACP_RID_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_inst_S_AXI_ACP_RRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_S_AXI_GP0_BID_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_inst_S_AXI_GP0_BRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_S_AXI_GP0_RDATA_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_inst_S_AXI_GP0_RID_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_inst_S_AXI_GP0_RRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_S_AXI_GP1_BID_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_inst_S_AXI_GP1_BRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_S_AXI_GP1_RDATA_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_inst_S_AXI_GP1_RID_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_inst_S_AXI_GP1_RRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_S_AXI_HP0_BID_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_inst_S_AXI_HP0_BRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_S_AXI_HP0_RACOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_inst_S_AXI_HP0_RCOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_inst_S_AXI_HP0_RDATA_UNCONNECTED : STD_LOGIC_VECTOR ( 63 downto 0 );
signal NLW_inst_S_AXI_HP0_RID_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_inst_S_AXI_HP0_RRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_S_AXI_HP0_WACOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_inst_S_AXI_HP0_WCOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_inst_S_AXI_HP1_BID_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_inst_S_AXI_HP1_BRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_S_AXI_HP1_RACOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_inst_S_AXI_HP1_RCOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_inst_S_AXI_HP1_RDATA_UNCONNECTED : STD_LOGIC_VECTOR ( 63 downto 0 );
signal NLW_inst_S_AXI_HP1_RID_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_inst_S_AXI_HP1_RRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_S_AXI_HP1_WACOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_inst_S_AXI_HP1_WCOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_inst_S_AXI_HP2_BID_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_inst_S_AXI_HP2_BRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_S_AXI_HP2_RACOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_inst_S_AXI_HP2_RCOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_inst_S_AXI_HP2_RDATA_UNCONNECTED : STD_LOGIC_VECTOR ( 63 downto 0 );
signal NLW_inst_S_AXI_HP2_RID_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_inst_S_AXI_HP2_RRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_S_AXI_HP2_WACOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_inst_S_AXI_HP2_WCOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_inst_S_AXI_HP3_BID_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_inst_S_AXI_HP3_BRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_S_AXI_HP3_RACOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_inst_S_AXI_HP3_RCOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_inst_S_AXI_HP3_RDATA_UNCONNECTED : STD_LOGIC_VECTOR ( 63 downto 0 );
signal NLW_inst_S_AXI_HP3_RID_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_inst_S_AXI_HP3_RRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_S_AXI_HP3_WACOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_inst_S_AXI_HP3_WCOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_inst_TRACE_DATA_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_USB1_PORT_INDCTL_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute C_DM_WIDTH : integer;
attribute C_DM_WIDTH of inst : label is 4;
attribute C_DQS_WIDTH : integer;
attribute C_DQS_WIDTH of inst : label is 4;
attribute C_DQ_WIDTH : integer;
attribute C_DQ_WIDTH of inst : label is 32;
attribute C_EMIO_GPIO_WIDTH : integer;
attribute C_EMIO_GPIO_WIDTH of inst : label is 64;
attribute C_EN_EMIO_ENET0 : integer;
attribute C_EN_EMIO_ENET0 of inst : label is 0;
attribute C_EN_EMIO_ENET1 : integer;
attribute C_EN_EMIO_ENET1 of inst : label is 0;
attribute C_EN_EMIO_PJTAG : integer;
attribute C_EN_EMIO_PJTAG of inst : label is 0;
attribute C_EN_EMIO_TRACE : integer;
attribute C_EN_EMIO_TRACE of inst : label is 0;
attribute C_FCLK_CLK0_BUF : string;
attribute C_FCLK_CLK0_BUF of inst : label is "TRUE";
attribute C_FCLK_CLK1_BUF : string;
attribute C_FCLK_CLK1_BUF of inst : label is "FALSE";
attribute C_FCLK_CLK2_BUF : string;
attribute C_FCLK_CLK2_BUF of inst : label is "FALSE";
attribute C_FCLK_CLK3_BUF : string;
attribute C_FCLK_CLK3_BUF of inst : label is "FALSE";
attribute C_GP0_EN_MODIFIABLE_TXN : integer;
attribute C_GP0_EN_MODIFIABLE_TXN of inst : label is 0;
attribute C_GP1_EN_MODIFIABLE_TXN : integer;
attribute C_GP1_EN_MODIFIABLE_TXN of inst : label is 0;
attribute C_INCLUDE_ACP_TRANS_CHECK : integer;
attribute C_INCLUDE_ACP_TRANS_CHECK of inst : label is 0;
attribute C_INCLUDE_TRACE_BUFFER : integer;
attribute C_INCLUDE_TRACE_BUFFER of inst : label is 0;
attribute C_IRQ_F2P_MODE : string;
attribute C_IRQ_F2P_MODE of inst : label is "DIRECT";
attribute C_MIO_PRIMITIVE : integer;
attribute C_MIO_PRIMITIVE of inst : label is 54;
attribute C_M_AXI_GP0_ENABLE_STATIC_REMAP : integer;
attribute C_M_AXI_GP0_ENABLE_STATIC_REMAP of inst : label is 0;
attribute C_M_AXI_GP0_ID_WIDTH : integer;
attribute C_M_AXI_GP0_ID_WIDTH of inst : label is 12;
attribute C_M_AXI_GP0_THREAD_ID_WIDTH : integer;
attribute C_M_AXI_GP0_THREAD_ID_WIDTH of inst : label is 12;
attribute C_M_AXI_GP1_ENABLE_STATIC_REMAP : integer;
attribute C_M_AXI_GP1_ENABLE_STATIC_REMAP of inst : label is 0;
attribute C_M_AXI_GP1_ID_WIDTH : integer;
attribute C_M_AXI_GP1_ID_WIDTH of inst : label is 12;
attribute C_M_AXI_GP1_THREAD_ID_WIDTH : integer;
attribute C_M_AXI_GP1_THREAD_ID_WIDTH of inst : label is 12;
attribute C_NUM_F2P_INTR_INPUTS : integer;
attribute C_NUM_F2P_INTR_INPUTS of inst : label is 1;
attribute C_PACKAGE_NAME : string;
attribute C_PACKAGE_NAME of inst : label is "clg400";
attribute C_PS7_SI_REV : string;
attribute C_PS7_SI_REV of inst : label is "PRODUCTION";
attribute C_S_AXI_ACP_ARUSER_VAL : integer;
attribute C_S_AXI_ACP_ARUSER_VAL of inst : label is 31;
attribute C_S_AXI_ACP_AWUSER_VAL : integer;
attribute C_S_AXI_ACP_AWUSER_VAL of inst : label is 31;
attribute C_S_AXI_ACP_ID_WIDTH : integer;
attribute C_S_AXI_ACP_ID_WIDTH of inst : label is 3;
attribute C_S_AXI_GP0_ID_WIDTH : integer;
attribute C_S_AXI_GP0_ID_WIDTH of inst : label is 6;
attribute C_S_AXI_GP1_ID_WIDTH : integer;
attribute C_S_AXI_GP1_ID_WIDTH of inst : label is 6;
attribute C_S_AXI_HP0_DATA_WIDTH : integer;
attribute C_S_AXI_HP0_DATA_WIDTH of inst : label is 64;
attribute C_S_AXI_HP0_ID_WIDTH : integer;
attribute C_S_AXI_HP0_ID_WIDTH of inst : label is 6;
attribute C_S_AXI_HP1_DATA_WIDTH : integer;
attribute C_S_AXI_HP1_DATA_WIDTH of inst : label is 64;
attribute C_S_AXI_HP1_ID_WIDTH : integer;
attribute C_S_AXI_HP1_ID_WIDTH of inst : label is 6;
attribute C_S_AXI_HP2_DATA_WIDTH : integer;
attribute C_S_AXI_HP2_DATA_WIDTH of inst : label is 64;
attribute C_S_AXI_HP2_ID_WIDTH : integer;
attribute C_S_AXI_HP2_ID_WIDTH of inst : label is 6;
attribute C_S_AXI_HP3_DATA_WIDTH : integer;
attribute C_S_AXI_HP3_DATA_WIDTH of inst : label is 64;
attribute C_S_AXI_HP3_ID_WIDTH : integer;
attribute C_S_AXI_HP3_ID_WIDTH of inst : label is 6;
attribute C_TRACE_BUFFER_CLOCK_DELAY : integer;
attribute C_TRACE_BUFFER_CLOCK_DELAY of inst : label is 12;
attribute C_TRACE_BUFFER_FIFO_SIZE : integer;
attribute C_TRACE_BUFFER_FIFO_SIZE of inst : label is 128;
attribute C_TRACE_INTERNAL_WIDTH : integer;
attribute C_TRACE_INTERNAL_WIDTH of inst : label is 2;
attribute C_TRACE_PIPELINE_WIDTH : integer;
attribute C_TRACE_PIPELINE_WIDTH of inst : label is 8;
attribute C_USE_AXI_NONSECURE : integer;
attribute C_USE_AXI_NONSECURE of inst : label is 0;
attribute C_USE_DEFAULT_ACP_USER_VAL : integer;
attribute C_USE_DEFAULT_ACP_USER_VAL of inst : label is 0;
attribute C_USE_M_AXI_GP0 : integer;
attribute C_USE_M_AXI_GP0 of inst : label is 1;
attribute C_USE_M_AXI_GP1 : integer;
attribute C_USE_M_AXI_GP1 of inst : label is 0;
attribute C_USE_S_AXI_ACP : integer;
attribute C_USE_S_AXI_ACP of inst : label is 0;
attribute C_USE_S_AXI_GP0 : integer;
attribute C_USE_S_AXI_GP0 of inst : label is 0;
attribute C_USE_S_AXI_GP1 : integer;
attribute C_USE_S_AXI_GP1 of inst : label is 0;
attribute C_USE_S_AXI_HP0 : integer;
attribute C_USE_S_AXI_HP0 of inst : label is 0;
attribute C_USE_S_AXI_HP1 : integer;
attribute C_USE_S_AXI_HP1 of inst : label is 0;
attribute C_USE_S_AXI_HP2 : integer;
attribute C_USE_S_AXI_HP2 of inst : label is 0;
attribute C_USE_S_AXI_HP3 : integer;
attribute C_USE_S_AXI_HP3 of inst : label is 0;
attribute HW_HANDOFF : string;
attribute HW_HANDOFF of inst : label is "zybo_zynq_design_processing_system7_0_0.hwdef";
attribute POWER : string;
attribute POWER of inst : label is "<PROCESSOR name={system} numA9Cores={2} clockFreq={650} load={0.5} /><MEMORY name={code} memType={DDR3} dataWidth={32} clockFreq={525} readRate={0.5} writeRate={0.5} /><IO interface={GPIO_Bank_1} ioStandard={LVCMOS18} bidis={2} ioBank={Vcco_p1} clockFreq={1} usageRate={0.5} /><IO interface={GPIO_Bank_0} ioStandard={LVCMOS33} bidis={9} ioBank={Vcco_p0} clockFreq={1} usageRate={0.5} /><IO interface={Timer} ioStandard={} bidis={0} ioBank={} clockFreq={108.333336} usageRate={0.5} /><IO interface={UART} ioStandard={LVCMOS18} bidis={2} ioBank={Vcco_p1} clockFreq={100.000000} usageRate={0.5} /><IO interface={SD} ioStandard={LVCMOS18} bidis={7} ioBank={Vcco_p1} clockFreq={50.000000} usageRate={0.5} /><IO interface={USB} ioStandard={LVCMOS18} bidis={12} ioBank={Vcco_p1} clockFreq={60} usageRate={0.5} /><IO interface={GigE} ioStandard={HSTL_I_18} bidis={14} ioBank={Vcco_p1} clockFreq={125.000000} usageRate={0.5} /><IO interface={QSPI} ioStandard={LVCMOS33} bidis={7} ioBank={Vcco_p0} clockFreq={200} usageRate={0.5} /><PLL domain={Processor} vco={1300.000} /><PLL domain={Memory} vco={1050.000} /><PLL domain={IO} vco={1000.000} /><AXI interface={M_AXI_GP0} dataWidth={32} clockFreq={100} usageRate={0.5} />/>";
attribute USE_TRACE_DATA_EDGE_DETECTOR : integer;
attribute USE_TRACE_DATA_EDGE_DETECTOR of inst : label is 0;
attribute X_INTERFACE_INFO : string;
attribute X_INTERFACE_INFO of DDR_CAS_n : signal is "xilinx.com:interface:ddrx:1.0 DDR CAS_N";
attribute X_INTERFACE_INFO of DDR_CKE : signal is "xilinx.com:interface:ddrx:1.0 DDR CKE";
attribute X_INTERFACE_INFO of DDR_CS_n : signal is "xilinx.com:interface:ddrx:1.0 DDR CS_N";
attribute X_INTERFACE_INFO of DDR_Clk : signal is "xilinx.com:interface:ddrx:1.0 DDR CK_P";
attribute X_INTERFACE_INFO of DDR_Clk_n : signal is "xilinx.com:interface:ddrx:1.0 DDR CK_N";
attribute X_INTERFACE_INFO of DDR_DRSTB : signal is "xilinx.com:interface:ddrx:1.0 DDR RESET_N";
attribute X_INTERFACE_INFO of DDR_ODT : signal is "xilinx.com:interface:ddrx:1.0 DDR ODT";
attribute X_INTERFACE_INFO of DDR_RAS_n : signal is "xilinx.com:interface:ddrx:1.0 DDR RAS_N";
attribute X_INTERFACE_INFO of DDR_VRN : signal is "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO DDR_VRN";
attribute X_INTERFACE_INFO of DDR_VRP : signal is "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO DDR_VRP";
attribute X_INTERFACE_INFO of DDR_WEB : signal is "xilinx.com:interface:ddrx:1.0 DDR WE_N";
attribute X_INTERFACE_INFO of FCLK_CLK0 : signal is "xilinx.com:signal:clock:1.0 FCLK_CLK0 CLK";
attribute X_INTERFACE_PARAMETER : string;
attribute X_INTERFACE_PARAMETER of FCLK_CLK0 : signal is "XIL_INTERFACENAME FCLK_CLK0, FREQ_HZ 100000000, PHASE 0.000, CLK_DOMAIN zybo_zynq_design_processing_system7_0_0_FCLK_CLK0";
attribute X_INTERFACE_INFO of FCLK_RESET0_N : signal is "xilinx.com:signal:reset:1.0 FCLK_RESET0_N RST";
attribute X_INTERFACE_PARAMETER of FCLK_RESET0_N : signal is "XIL_INTERFACENAME FCLK_RESET0_N, POLARITY ACTIVE_LOW";
attribute X_INTERFACE_INFO of M_AXI_GP0_ACLK : signal is "xilinx.com:signal:clock:1.0 M_AXI_GP0_ACLK CLK";
attribute X_INTERFACE_PARAMETER of M_AXI_GP0_ACLK : signal is "XIL_INTERFACENAME M_AXI_GP0_ACLK, ASSOCIATED_BUSIF M_AXI_GP0, FREQ_HZ 100000000, PHASE 0.000, CLK_DOMAIN zybo_zynq_design_processing_system7_0_0_FCLK_CLK0";
attribute X_INTERFACE_INFO of M_AXI_GP0_ARREADY : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARREADY";
attribute X_INTERFACE_INFO of M_AXI_GP0_ARVALID : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARVALID";
attribute X_INTERFACE_INFO of M_AXI_GP0_AWREADY : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWREADY";
attribute X_INTERFACE_INFO of M_AXI_GP0_AWVALID : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWVALID";
attribute X_INTERFACE_INFO of M_AXI_GP0_BREADY : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 BREADY";
attribute X_INTERFACE_INFO of M_AXI_GP0_BVALID : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 BVALID";
attribute X_INTERFACE_INFO of M_AXI_GP0_RLAST : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 RLAST";
attribute X_INTERFACE_INFO of M_AXI_GP0_RREADY : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 RREADY";
attribute X_INTERFACE_INFO of M_AXI_GP0_RVALID : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 RVALID";
attribute X_INTERFACE_INFO of M_AXI_GP0_WLAST : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 WLAST";
attribute X_INTERFACE_INFO of M_AXI_GP0_WREADY : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 WREADY";
attribute X_INTERFACE_INFO of M_AXI_GP0_WVALID : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 WVALID";
attribute X_INTERFACE_INFO of PS_CLK : signal is "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO PS_CLK";
attribute X_INTERFACE_INFO of PS_PORB : signal is "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO PS_PORB";
attribute X_INTERFACE_PARAMETER of PS_PORB : signal is "XIL_INTERFACENAME FIXED_IO, CAN_DEBUG false";
attribute X_INTERFACE_INFO of PS_SRSTB : signal is "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO PS_SRSTB";
attribute X_INTERFACE_INFO of SDIO0_WP : signal is "xilinx.com:interface:sdio:1.0 SDIO_0 WP";
attribute X_INTERFACE_INFO of USB0_VBUS_PWRFAULT : signal is "xilinx.com:display_processing_system7:usbctrl:1.0 USBIND_0 VBUS_PWRFAULT";
attribute X_INTERFACE_INFO of USB0_VBUS_PWRSELECT : signal is "xilinx.com:display_processing_system7:usbctrl:1.0 USBIND_0 VBUS_PWRSELECT";
attribute X_INTERFACE_INFO of DDR_Addr : signal is "xilinx.com:interface:ddrx:1.0 DDR ADDR";
attribute X_INTERFACE_INFO of DDR_BankAddr : signal is "xilinx.com:interface:ddrx:1.0 DDR BA";
attribute X_INTERFACE_INFO of DDR_DM : signal is "xilinx.com:interface:ddrx:1.0 DDR DM";
attribute X_INTERFACE_INFO of DDR_DQ : signal is "xilinx.com:interface:ddrx:1.0 DDR DQ";
attribute X_INTERFACE_INFO of DDR_DQS : signal is "xilinx.com:interface:ddrx:1.0 DDR DQS_P";
attribute X_INTERFACE_PARAMETER of DDR_DQS : signal is "XIL_INTERFACENAME DDR, CAN_DEBUG false, TIMEPERIOD_PS 1250, MEMORY_TYPE COMPONENTS, DATA_WIDTH 8, CS_ENABLED true, DATA_MASK_ENABLED true, SLOT Single, MEM_ADDR_MAP ROW_COLUMN_BANK, BURST_LENGTH 8, AXI_ARBITRATION_SCHEME TDM, CAS_LATENCY 11, CAS_WRITE_LATENCY 11";
attribute X_INTERFACE_INFO of DDR_DQS_n : signal is "xilinx.com:interface:ddrx:1.0 DDR DQS_N";
attribute X_INTERFACE_INFO of IRQ_F2P : signal is "xilinx.com:signal:interrupt:1.0 IRQ_F2P INTERRUPT";
attribute X_INTERFACE_PARAMETER of IRQ_F2P : signal is "XIL_INTERFACENAME IRQ_F2P, SENSITIVITY LEVEL_HIGH, PortWidth 1";
attribute X_INTERFACE_INFO of MIO : signal is "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO MIO";
attribute X_INTERFACE_INFO of M_AXI_GP0_ARADDR : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARADDR";
attribute X_INTERFACE_INFO of M_AXI_GP0_ARBURST : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARBURST";
attribute X_INTERFACE_INFO of M_AXI_GP0_ARCACHE : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARCACHE";
attribute X_INTERFACE_INFO of M_AXI_GP0_ARID : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARID";
attribute X_INTERFACE_INFO of M_AXI_GP0_ARLEN : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARLEN";
attribute X_INTERFACE_INFO of M_AXI_GP0_ARLOCK : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARLOCK";
attribute X_INTERFACE_INFO of M_AXI_GP0_ARPROT : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARPROT";
attribute X_INTERFACE_INFO of M_AXI_GP0_ARQOS : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARQOS";
attribute X_INTERFACE_INFO of M_AXI_GP0_ARSIZE : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARSIZE";
attribute X_INTERFACE_INFO of M_AXI_GP0_AWADDR : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWADDR";
attribute X_INTERFACE_INFO of M_AXI_GP0_AWBURST : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWBURST";
attribute X_INTERFACE_INFO of M_AXI_GP0_AWCACHE : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWCACHE";
attribute X_INTERFACE_INFO of M_AXI_GP0_AWID : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWID";
attribute X_INTERFACE_INFO of M_AXI_GP0_AWLEN : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWLEN";
attribute X_INTERFACE_INFO of M_AXI_GP0_AWLOCK : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWLOCK";
attribute X_INTERFACE_INFO of M_AXI_GP0_AWPROT : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWPROT";
attribute X_INTERFACE_INFO of M_AXI_GP0_AWQOS : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWQOS";
attribute X_INTERFACE_INFO of M_AXI_GP0_AWSIZE : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWSIZE";
attribute X_INTERFACE_INFO of M_AXI_GP0_BID : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 BID";
attribute X_INTERFACE_INFO of M_AXI_GP0_BRESP : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 BRESP";
attribute X_INTERFACE_INFO of M_AXI_GP0_RDATA : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 RDATA";
attribute X_INTERFACE_PARAMETER of M_AXI_GP0_RDATA : signal is "XIL_INTERFACENAME M_AXI_GP0, SUPPORTS_NARROW_BURST 0, NUM_WRITE_OUTSTANDING 8, NUM_READ_OUTSTANDING 8, DATA_WIDTH 32, PROTOCOL AXI3, FREQ_HZ 100000000, ID_WIDTH 12, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 1, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 1, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, MAX_BURST_LENGTH 16, PHASE 0.000, CLK_DOMAIN zybo_zynq_design_processing_system7_0_0_FCLK_CLK0, NUM_READ_THREADS 4, NUM_WRITE_THREADS 4, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0";
attribute X_INTERFACE_INFO of M_AXI_GP0_RID : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 RID";
attribute X_INTERFACE_INFO of M_AXI_GP0_RRESP : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 RRESP";
attribute X_INTERFACE_INFO of M_AXI_GP0_WDATA : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 WDATA";
attribute X_INTERFACE_INFO of M_AXI_GP0_WID : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 WID";
attribute X_INTERFACE_INFO of M_AXI_GP0_WSTRB : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 WSTRB";
attribute X_INTERFACE_INFO of USB0_PORT_INDCTL : signal is "xilinx.com:display_processing_system7:usbctrl:1.0 USBIND_0 PORT_INDCTL";
begin
inst: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7
port map (
CAN0_PHY_RX => '0',
CAN0_PHY_TX => NLW_inst_CAN0_PHY_TX_UNCONNECTED,
CAN1_PHY_RX => '0',
CAN1_PHY_TX => NLW_inst_CAN1_PHY_TX_UNCONNECTED,
Core0_nFIQ => '0',
Core0_nIRQ => '0',
Core1_nFIQ => '0',
Core1_nIRQ => '0',
DDR_ARB(3 downto 0) => B"0000",
DDR_Addr(14 downto 0) => DDR_Addr(14 downto 0),
DDR_BankAddr(2 downto 0) => DDR_BankAddr(2 downto 0),
DDR_CAS_n => DDR_CAS_n,
DDR_CKE => DDR_CKE,
DDR_CS_n => DDR_CS_n,
DDR_Clk => DDR_Clk,
DDR_Clk_n => DDR_Clk_n,
DDR_DM(3 downto 0) => DDR_DM(3 downto 0),
DDR_DQ(31 downto 0) => DDR_DQ(31 downto 0),
DDR_DQS(3 downto 0) => DDR_DQS(3 downto 0),
DDR_DQS_n(3 downto 0) => DDR_DQS_n(3 downto 0),
DDR_DRSTB => DDR_DRSTB,
DDR_ODT => DDR_ODT,
DDR_RAS_n => DDR_RAS_n,
DDR_VRN => DDR_VRN,
DDR_VRP => DDR_VRP,
DDR_WEB => DDR_WEB,
DMA0_ACLK => '0',
DMA0_DAREADY => '0',
DMA0_DATYPE(1 downto 0) => NLW_inst_DMA0_DATYPE_UNCONNECTED(1 downto 0),
DMA0_DAVALID => NLW_inst_DMA0_DAVALID_UNCONNECTED,
DMA0_DRLAST => '0',
DMA0_DRREADY => NLW_inst_DMA0_DRREADY_UNCONNECTED,
DMA0_DRTYPE(1 downto 0) => B"00",
DMA0_DRVALID => '0',
DMA0_RSTN => NLW_inst_DMA0_RSTN_UNCONNECTED,
DMA1_ACLK => '0',
DMA1_DAREADY => '0',
DMA1_DATYPE(1 downto 0) => NLW_inst_DMA1_DATYPE_UNCONNECTED(1 downto 0),
DMA1_DAVALID => NLW_inst_DMA1_DAVALID_UNCONNECTED,
DMA1_DRLAST => '0',
DMA1_DRREADY => NLW_inst_DMA1_DRREADY_UNCONNECTED,
DMA1_DRTYPE(1 downto 0) => B"00",
DMA1_DRVALID => '0',
DMA1_RSTN => NLW_inst_DMA1_RSTN_UNCONNECTED,
DMA2_ACLK => '0',
DMA2_DAREADY => '0',
DMA2_DATYPE(1 downto 0) => NLW_inst_DMA2_DATYPE_UNCONNECTED(1 downto 0),
DMA2_DAVALID => NLW_inst_DMA2_DAVALID_UNCONNECTED,
DMA2_DRLAST => '0',
DMA2_DRREADY => NLW_inst_DMA2_DRREADY_UNCONNECTED,
DMA2_DRTYPE(1 downto 0) => B"00",
DMA2_DRVALID => '0',
DMA2_RSTN => NLW_inst_DMA2_RSTN_UNCONNECTED,
DMA3_ACLK => '0',
DMA3_DAREADY => '0',
DMA3_DATYPE(1 downto 0) => NLW_inst_DMA3_DATYPE_UNCONNECTED(1 downto 0),
DMA3_DAVALID => NLW_inst_DMA3_DAVALID_UNCONNECTED,
DMA3_DRLAST => '0',
DMA3_DRREADY => NLW_inst_DMA3_DRREADY_UNCONNECTED,
DMA3_DRTYPE(1 downto 0) => B"00",
DMA3_DRVALID => '0',
DMA3_RSTN => NLW_inst_DMA3_RSTN_UNCONNECTED,
ENET0_EXT_INTIN => '0',
ENET0_GMII_COL => '0',
ENET0_GMII_CRS => '0',
ENET0_GMII_RXD(7 downto 0) => B"00000000",
ENET0_GMII_RX_CLK => '0',
ENET0_GMII_RX_DV => '0',
ENET0_GMII_RX_ER => '0',
ENET0_GMII_TXD(7 downto 0) => NLW_inst_ENET0_GMII_TXD_UNCONNECTED(7 downto 0),
ENET0_GMII_TX_CLK => '0',
ENET0_GMII_TX_EN => NLW_inst_ENET0_GMII_TX_EN_UNCONNECTED,
ENET0_GMII_TX_ER => NLW_inst_ENET0_GMII_TX_ER_UNCONNECTED,
ENET0_MDIO_I => '0',
ENET0_MDIO_MDC => NLW_inst_ENET0_MDIO_MDC_UNCONNECTED,
ENET0_MDIO_O => NLW_inst_ENET0_MDIO_O_UNCONNECTED,
ENET0_MDIO_T => NLW_inst_ENET0_MDIO_T_UNCONNECTED,
ENET0_PTP_DELAY_REQ_RX => NLW_inst_ENET0_PTP_DELAY_REQ_RX_UNCONNECTED,
ENET0_PTP_DELAY_REQ_TX => NLW_inst_ENET0_PTP_DELAY_REQ_TX_UNCONNECTED,
ENET0_PTP_PDELAY_REQ_RX => NLW_inst_ENET0_PTP_PDELAY_REQ_RX_UNCONNECTED,
ENET0_PTP_PDELAY_REQ_TX => NLW_inst_ENET0_PTP_PDELAY_REQ_TX_UNCONNECTED,
ENET0_PTP_PDELAY_RESP_RX => NLW_inst_ENET0_PTP_PDELAY_RESP_RX_UNCONNECTED,
ENET0_PTP_PDELAY_RESP_TX => NLW_inst_ENET0_PTP_PDELAY_RESP_TX_UNCONNECTED,
ENET0_PTP_SYNC_FRAME_RX => NLW_inst_ENET0_PTP_SYNC_FRAME_RX_UNCONNECTED,
ENET0_PTP_SYNC_FRAME_TX => NLW_inst_ENET0_PTP_SYNC_FRAME_TX_UNCONNECTED,
ENET0_SOF_RX => NLW_inst_ENET0_SOF_RX_UNCONNECTED,
ENET0_SOF_TX => NLW_inst_ENET0_SOF_TX_UNCONNECTED,
ENET1_EXT_INTIN => '0',
ENET1_GMII_COL => '0',
ENET1_GMII_CRS => '0',
ENET1_GMII_RXD(7 downto 0) => B"00000000",
ENET1_GMII_RX_CLK => '0',
ENET1_GMII_RX_DV => '0',
ENET1_GMII_RX_ER => '0',
ENET1_GMII_TXD(7 downto 0) => NLW_inst_ENET1_GMII_TXD_UNCONNECTED(7 downto 0),
ENET1_GMII_TX_CLK => '0',
ENET1_GMII_TX_EN => NLW_inst_ENET1_GMII_TX_EN_UNCONNECTED,
ENET1_GMII_TX_ER => NLW_inst_ENET1_GMII_TX_ER_UNCONNECTED,
ENET1_MDIO_I => '0',
ENET1_MDIO_MDC => NLW_inst_ENET1_MDIO_MDC_UNCONNECTED,
ENET1_MDIO_O => NLW_inst_ENET1_MDIO_O_UNCONNECTED,
ENET1_MDIO_T => NLW_inst_ENET1_MDIO_T_UNCONNECTED,
ENET1_PTP_DELAY_REQ_RX => NLW_inst_ENET1_PTP_DELAY_REQ_RX_UNCONNECTED,
ENET1_PTP_DELAY_REQ_TX => NLW_inst_ENET1_PTP_DELAY_REQ_TX_UNCONNECTED,
ENET1_PTP_PDELAY_REQ_RX => NLW_inst_ENET1_PTP_PDELAY_REQ_RX_UNCONNECTED,
ENET1_PTP_PDELAY_REQ_TX => NLW_inst_ENET1_PTP_PDELAY_REQ_TX_UNCONNECTED,
ENET1_PTP_PDELAY_RESP_RX => NLW_inst_ENET1_PTP_PDELAY_RESP_RX_UNCONNECTED,
ENET1_PTP_PDELAY_RESP_TX => NLW_inst_ENET1_PTP_PDELAY_RESP_TX_UNCONNECTED,
ENET1_PTP_SYNC_FRAME_RX => NLW_inst_ENET1_PTP_SYNC_FRAME_RX_UNCONNECTED,
ENET1_PTP_SYNC_FRAME_TX => NLW_inst_ENET1_PTP_SYNC_FRAME_TX_UNCONNECTED,
ENET1_SOF_RX => NLW_inst_ENET1_SOF_RX_UNCONNECTED,
ENET1_SOF_TX => NLW_inst_ENET1_SOF_TX_UNCONNECTED,
EVENT_EVENTI => '0',
EVENT_EVENTO => NLW_inst_EVENT_EVENTO_UNCONNECTED,
EVENT_STANDBYWFE(1 downto 0) => NLW_inst_EVENT_STANDBYWFE_UNCONNECTED(1 downto 0),
EVENT_STANDBYWFI(1 downto 0) => NLW_inst_EVENT_STANDBYWFI_UNCONNECTED(1 downto 0),
FCLK_CLK0 => FCLK_CLK0,
FCLK_CLK1 => NLW_inst_FCLK_CLK1_UNCONNECTED,
FCLK_CLK2 => NLW_inst_FCLK_CLK2_UNCONNECTED,
FCLK_CLK3 => NLW_inst_FCLK_CLK3_UNCONNECTED,
FCLK_CLKTRIG0_N => '0',
FCLK_CLKTRIG1_N => '0',
FCLK_CLKTRIG2_N => '0',
FCLK_CLKTRIG3_N => '0',
FCLK_RESET0_N => FCLK_RESET0_N,
FCLK_RESET1_N => NLW_inst_FCLK_RESET1_N_UNCONNECTED,
FCLK_RESET2_N => NLW_inst_FCLK_RESET2_N_UNCONNECTED,
FCLK_RESET3_N => NLW_inst_FCLK_RESET3_N_UNCONNECTED,
FPGA_IDLE_N => '0',
FTMD_TRACEIN_ATID(3 downto 0) => B"0000",
FTMD_TRACEIN_CLK => '0',
FTMD_TRACEIN_DATA(31 downto 0) => B"00000000000000000000000000000000",
FTMD_TRACEIN_VALID => '0',
FTMT_F2P_DEBUG(31 downto 0) => B"00000000000000000000000000000000",
FTMT_F2P_TRIGACK_0 => NLW_inst_FTMT_F2P_TRIGACK_0_UNCONNECTED,
FTMT_F2P_TRIGACK_1 => NLW_inst_FTMT_F2P_TRIGACK_1_UNCONNECTED,
FTMT_F2P_TRIGACK_2 => NLW_inst_FTMT_F2P_TRIGACK_2_UNCONNECTED,
FTMT_F2P_TRIGACK_3 => NLW_inst_FTMT_F2P_TRIGACK_3_UNCONNECTED,
FTMT_F2P_TRIG_0 => '0',
FTMT_F2P_TRIG_1 => '0',
FTMT_F2P_TRIG_2 => '0',
FTMT_F2P_TRIG_3 => '0',
FTMT_P2F_DEBUG(31 downto 0) => NLW_inst_FTMT_P2F_DEBUG_UNCONNECTED(31 downto 0),
FTMT_P2F_TRIGACK_0 => '0',
FTMT_P2F_TRIGACK_1 => '0',
FTMT_P2F_TRIGACK_2 => '0',
FTMT_P2F_TRIGACK_3 => '0',
FTMT_P2F_TRIG_0 => NLW_inst_FTMT_P2F_TRIG_0_UNCONNECTED,
FTMT_P2F_TRIG_1 => NLW_inst_FTMT_P2F_TRIG_1_UNCONNECTED,
FTMT_P2F_TRIG_2 => NLW_inst_FTMT_P2F_TRIG_2_UNCONNECTED,
FTMT_P2F_TRIG_3 => NLW_inst_FTMT_P2F_TRIG_3_UNCONNECTED,
GPIO_I(63 downto 0) => B"0000000000000000000000000000000000000000000000000000000000000000",
GPIO_O(63 downto 0) => NLW_inst_GPIO_O_UNCONNECTED(63 downto 0),
GPIO_T(63 downto 0) => NLW_inst_GPIO_T_UNCONNECTED(63 downto 0),
I2C0_SCL_I => '0',
I2C0_SCL_O => NLW_inst_I2C0_SCL_O_UNCONNECTED,
I2C0_SCL_T => NLW_inst_I2C0_SCL_T_UNCONNECTED,
I2C0_SDA_I => '0',
I2C0_SDA_O => NLW_inst_I2C0_SDA_O_UNCONNECTED,
I2C0_SDA_T => NLW_inst_I2C0_SDA_T_UNCONNECTED,
I2C1_SCL_I => '0',
I2C1_SCL_O => NLW_inst_I2C1_SCL_O_UNCONNECTED,
I2C1_SCL_T => NLW_inst_I2C1_SCL_T_UNCONNECTED,
I2C1_SDA_I => '0',
I2C1_SDA_O => NLW_inst_I2C1_SDA_O_UNCONNECTED,
I2C1_SDA_T => NLW_inst_I2C1_SDA_T_UNCONNECTED,
IRQ_F2P(0) => IRQ_F2P(0),
IRQ_P2F_CAN0 => NLW_inst_IRQ_P2F_CAN0_UNCONNECTED,
IRQ_P2F_CAN1 => NLW_inst_IRQ_P2F_CAN1_UNCONNECTED,
IRQ_P2F_CTI => NLW_inst_IRQ_P2F_CTI_UNCONNECTED,
IRQ_P2F_DMAC0 => NLW_inst_IRQ_P2F_DMAC0_UNCONNECTED,
IRQ_P2F_DMAC1 => NLW_inst_IRQ_P2F_DMAC1_UNCONNECTED,
IRQ_P2F_DMAC2 => NLW_inst_IRQ_P2F_DMAC2_UNCONNECTED,
IRQ_P2F_DMAC3 => NLW_inst_IRQ_P2F_DMAC3_UNCONNECTED,
IRQ_P2F_DMAC4 => NLW_inst_IRQ_P2F_DMAC4_UNCONNECTED,
IRQ_P2F_DMAC5 => NLW_inst_IRQ_P2F_DMAC5_UNCONNECTED,
IRQ_P2F_DMAC6 => NLW_inst_IRQ_P2F_DMAC6_UNCONNECTED,
IRQ_P2F_DMAC7 => NLW_inst_IRQ_P2F_DMAC7_UNCONNECTED,
IRQ_P2F_DMAC_ABORT => NLW_inst_IRQ_P2F_DMAC_ABORT_UNCONNECTED,
IRQ_P2F_ENET0 => NLW_inst_IRQ_P2F_ENET0_UNCONNECTED,
IRQ_P2F_ENET1 => NLW_inst_IRQ_P2F_ENET1_UNCONNECTED,
IRQ_P2F_ENET_WAKE0 => NLW_inst_IRQ_P2F_ENET_WAKE0_UNCONNECTED,
IRQ_P2F_ENET_WAKE1 => NLW_inst_IRQ_P2F_ENET_WAKE1_UNCONNECTED,
IRQ_P2F_GPIO => NLW_inst_IRQ_P2F_GPIO_UNCONNECTED,
IRQ_P2F_I2C0 => NLW_inst_IRQ_P2F_I2C0_UNCONNECTED,
IRQ_P2F_I2C1 => NLW_inst_IRQ_P2F_I2C1_UNCONNECTED,
IRQ_P2F_QSPI => NLW_inst_IRQ_P2F_QSPI_UNCONNECTED,
IRQ_P2F_SDIO0 => NLW_inst_IRQ_P2F_SDIO0_UNCONNECTED,
IRQ_P2F_SDIO1 => NLW_inst_IRQ_P2F_SDIO1_UNCONNECTED,
IRQ_P2F_SMC => NLW_inst_IRQ_P2F_SMC_UNCONNECTED,
IRQ_P2F_SPI0 => NLW_inst_IRQ_P2F_SPI0_UNCONNECTED,
IRQ_P2F_SPI1 => NLW_inst_IRQ_P2F_SPI1_UNCONNECTED,
IRQ_P2F_UART0 => NLW_inst_IRQ_P2F_UART0_UNCONNECTED,
IRQ_P2F_UART1 => NLW_inst_IRQ_P2F_UART1_UNCONNECTED,
IRQ_P2F_USB0 => NLW_inst_IRQ_P2F_USB0_UNCONNECTED,
IRQ_P2F_USB1 => NLW_inst_IRQ_P2F_USB1_UNCONNECTED,
MIO(53 downto 0) => MIO(53 downto 0),
M_AXI_GP0_ACLK => M_AXI_GP0_ACLK,
M_AXI_GP0_ARADDR(31 downto 0) => M_AXI_GP0_ARADDR(31 downto 0),
M_AXI_GP0_ARBURST(1 downto 0) => M_AXI_GP0_ARBURST(1 downto 0),
M_AXI_GP0_ARCACHE(3 downto 0) => M_AXI_GP0_ARCACHE(3 downto 0),
M_AXI_GP0_ARESETN => NLW_inst_M_AXI_GP0_ARESETN_UNCONNECTED,
M_AXI_GP0_ARID(11 downto 0) => M_AXI_GP0_ARID(11 downto 0),
M_AXI_GP0_ARLEN(3 downto 0) => M_AXI_GP0_ARLEN(3 downto 0),
M_AXI_GP0_ARLOCK(1 downto 0) => M_AXI_GP0_ARLOCK(1 downto 0),
M_AXI_GP0_ARPROT(2 downto 0) => M_AXI_GP0_ARPROT(2 downto 0),
M_AXI_GP0_ARQOS(3 downto 0) => M_AXI_GP0_ARQOS(3 downto 0),
M_AXI_GP0_ARREADY => M_AXI_GP0_ARREADY,
M_AXI_GP0_ARSIZE(2 downto 0) => M_AXI_GP0_ARSIZE(2 downto 0),
M_AXI_GP0_ARVALID => M_AXI_GP0_ARVALID,
M_AXI_GP0_AWADDR(31 downto 0) => M_AXI_GP0_AWADDR(31 downto 0),
M_AXI_GP0_AWBURST(1 downto 0) => M_AXI_GP0_AWBURST(1 downto 0),
M_AXI_GP0_AWCACHE(3 downto 0) => M_AXI_GP0_AWCACHE(3 downto 0),
M_AXI_GP0_AWID(11 downto 0) => M_AXI_GP0_AWID(11 downto 0),
M_AXI_GP0_AWLEN(3 downto 0) => M_AXI_GP0_AWLEN(3 downto 0),
M_AXI_GP0_AWLOCK(1 downto 0) => M_AXI_GP0_AWLOCK(1 downto 0),
M_AXI_GP0_AWPROT(2 downto 0) => M_AXI_GP0_AWPROT(2 downto 0),
M_AXI_GP0_AWQOS(3 downto 0) => M_AXI_GP0_AWQOS(3 downto 0),
M_AXI_GP0_AWREADY => M_AXI_GP0_AWREADY,
M_AXI_GP0_AWSIZE(2 downto 0) => M_AXI_GP0_AWSIZE(2 downto 0),
M_AXI_GP0_AWVALID => M_AXI_GP0_AWVALID,
M_AXI_GP0_BID(11 downto 0) => M_AXI_GP0_BID(11 downto 0),
M_AXI_GP0_BREADY => M_AXI_GP0_BREADY,
M_AXI_GP0_BRESP(1 downto 0) => M_AXI_GP0_BRESP(1 downto 0),
M_AXI_GP0_BVALID => M_AXI_GP0_BVALID,
M_AXI_GP0_RDATA(31 downto 0) => M_AXI_GP0_RDATA(31 downto 0),
M_AXI_GP0_RID(11 downto 0) => M_AXI_GP0_RID(11 downto 0),
M_AXI_GP0_RLAST => M_AXI_GP0_RLAST,
M_AXI_GP0_RREADY => M_AXI_GP0_RREADY,
M_AXI_GP0_RRESP(1 downto 0) => M_AXI_GP0_RRESP(1 downto 0),
M_AXI_GP0_RVALID => M_AXI_GP0_RVALID,
M_AXI_GP0_WDATA(31 downto 0) => M_AXI_GP0_WDATA(31 downto 0),
M_AXI_GP0_WID(11 downto 0) => M_AXI_GP0_WID(11 downto 0),
M_AXI_GP0_WLAST => M_AXI_GP0_WLAST,
M_AXI_GP0_WREADY => M_AXI_GP0_WREADY,
M_AXI_GP0_WSTRB(3 downto 0) => M_AXI_GP0_WSTRB(3 downto 0),
M_AXI_GP0_WVALID => M_AXI_GP0_WVALID,
M_AXI_GP1_ACLK => '0',
M_AXI_GP1_ARADDR(31 downto 0) => NLW_inst_M_AXI_GP1_ARADDR_UNCONNECTED(31 downto 0),
M_AXI_GP1_ARBURST(1 downto 0) => NLW_inst_M_AXI_GP1_ARBURST_UNCONNECTED(1 downto 0),
M_AXI_GP1_ARCACHE(3 downto 0) => NLW_inst_M_AXI_GP1_ARCACHE_UNCONNECTED(3 downto 0),
M_AXI_GP1_ARESETN => NLW_inst_M_AXI_GP1_ARESETN_UNCONNECTED,
M_AXI_GP1_ARID(11 downto 0) => NLW_inst_M_AXI_GP1_ARID_UNCONNECTED(11 downto 0),
M_AXI_GP1_ARLEN(3 downto 0) => NLW_inst_M_AXI_GP1_ARLEN_UNCONNECTED(3 downto 0),
M_AXI_GP1_ARLOCK(1 downto 0) => NLW_inst_M_AXI_GP1_ARLOCK_UNCONNECTED(1 downto 0),
M_AXI_GP1_ARPROT(2 downto 0) => NLW_inst_M_AXI_GP1_ARPROT_UNCONNECTED(2 downto 0),
M_AXI_GP1_ARQOS(3 downto 0) => NLW_inst_M_AXI_GP1_ARQOS_UNCONNECTED(3 downto 0),
M_AXI_GP1_ARREADY => '0',
M_AXI_GP1_ARSIZE(2 downto 0) => NLW_inst_M_AXI_GP1_ARSIZE_UNCONNECTED(2 downto 0),
M_AXI_GP1_ARVALID => NLW_inst_M_AXI_GP1_ARVALID_UNCONNECTED,
M_AXI_GP1_AWADDR(31 downto 0) => NLW_inst_M_AXI_GP1_AWADDR_UNCONNECTED(31 downto 0),
M_AXI_GP1_AWBURST(1 downto 0) => NLW_inst_M_AXI_GP1_AWBURST_UNCONNECTED(1 downto 0),
M_AXI_GP1_AWCACHE(3 downto 0) => NLW_inst_M_AXI_GP1_AWCACHE_UNCONNECTED(3 downto 0),
M_AXI_GP1_AWID(11 downto 0) => NLW_inst_M_AXI_GP1_AWID_UNCONNECTED(11 downto 0),
M_AXI_GP1_AWLEN(3 downto 0) => NLW_inst_M_AXI_GP1_AWLEN_UNCONNECTED(3 downto 0),
M_AXI_GP1_AWLOCK(1 downto 0) => NLW_inst_M_AXI_GP1_AWLOCK_UNCONNECTED(1 downto 0),
M_AXI_GP1_AWPROT(2 downto 0) => NLW_inst_M_AXI_GP1_AWPROT_UNCONNECTED(2 downto 0),
M_AXI_GP1_AWQOS(3 downto 0) => NLW_inst_M_AXI_GP1_AWQOS_UNCONNECTED(3 downto 0),
M_AXI_GP1_AWREADY => '0',
M_AXI_GP1_AWSIZE(2 downto 0) => NLW_inst_M_AXI_GP1_AWSIZE_UNCONNECTED(2 downto 0),
M_AXI_GP1_AWVALID => NLW_inst_M_AXI_GP1_AWVALID_UNCONNECTED,
M_AXI_GP1_BID(11 downto 0) => B"000000000000",
M_AXI_GP1_BREADY => NLW_inst_M_AXI_GP1_BREADY_UNCONNECTED,
M_AXI_GP1_BRESP(1 downto 0) => B"00",
M_AXI_GP1_BVALID => '0',
M_AXI_GP1_RDATA(31 downto 0) => B"00000000000000000000000000000000",
M_AXI_GP1_RID(11 downto 0) => B"000000000000",
M_AXI_GP1_RLAST => '0',
M_AXI_GP1_RREADY => NLW_inst_M_AXI_GP1_RREADY_UNCONNECTED,
M_AXI_GP1_RRESP(1 downto 0) => B"00",
M_AXI_GP1_RVALID => '0',
M_AXI_GP1_WDATA(31 downto 0) => NLW_inst_M_AXI_GP1_WDATA_UNCONNECTED(31 downto 0),
M_AXI_GP1_WID(11 downto 0) => NLW_inst_M_AXI_GP1_WID_UNCONNECTED(11 downto 0),
M_AXI_GP1_WLAST => NLW_inst_M_AXI_GP1_WLAST_UNCONNECTED,
M_AXI_GP1_WREADY => '0',
M_AXI_GP1_WSTRB(3 downto 0) => NLW_inst_M_AXI_GP1_WSTRB_UNCONNECTED(3 downto 0),
M_AXI_GP1_WVALID => NLW_inst_M_AXI_GP1_WVALID_UNCONNECTED,
PJTAG_TCK => '0',
PJTAG_TDI => '0',
PJTAG_TDO => NLW_inst_PJTAG_TDO_UNCONNECTED,
PJTAG_TMS => '0',
PS_CLK => PS_CLK,
PS_PORB => PS_PORB,
PS_SRSTB => PS_SRSTB,
SDIO0_BUSPOW => NLW_inst_SDIO0_BUSPOW_UNCONNECTED,
SDIO0_BUSVOLT(2 downto 0) => NLW_inst_SDIO0_BUSVOLT_UNCONNECTED(2 downto 0),
SDIO0_CDN => '0',
SDIO0_CLK => NLW_inst_SDIO0_CLK_UNCONNECTED,
SDIO0_CLK_FB => '0',
SDIO0_CMD_I => '0',
SDIO0_CMD_O => NLW_inst_SDIO0_CMD_O_UNCONNECTED,
SDIO0_CMD_T => NLW_inst_SDIO0_CMD_T_UNCONNECTED,
SDIO0_DATA_I(3 downto 0) => B"0000",
SDIO0_DATA_O(3 downto 0) => NLW_inst_SDIO0_DATA_O_UNCONNECTED(3 downto 0),
SDIO0_DATA_T(3 downto 0) => NLW_inst_SDIO0_DATA_T_UNCONNECTED(3 downto 0),
SDIO0_LED => NLW_inst_SDIO0_LED_UNCONNECTED,
SDIO0_WP => SDIO0_WP,
SDIO1_BUSPOW => NLW_inst_SDIO1_BUSPOW_UNCONNECTED,
SDIO1_BUSVOLT(2 downto 0) => NLW_inst_SDIO1_BUSVOLT_UNCONNECTED(2 downto 0),
SDIO1_CDN => '0',
SDIO1_CLK => NLW_inst_SDIO1_CLK_UNCONNECTED,
SDIO1_CLK_FB => '0',
SDIO1_CMD_I => '0',
SDIO1_CMD_O => NLW_inst_SDIO1_CMD_O_UNCONNECTED,
SDIO1_CMD_T => NLW_inst_SDIO1_CMD_T_UNCONNECTED,
SDIO1_DATA_I(3 downto 0) => B"0000",
SDIO1_DATA_O(3 downto 0) => NLW_inst_SDIO1_DATA_O_UNCONNECTED(3 downto 0),
SDIO1_DATA_T(3 downto 0) => NLW_inst_SDIO1_DATA_T_UNCONNECTED(3 downto 0),
SDIO1_LED => NLW_inst_SDIO1_LED_UNCONNECTED,
SDIO1_WP => '0',
SPI0_MISO_I => '0',
SPI0_MISO_O => NLW_inst_SPI0_MISO_O_UNCONNECTED,
SPI0_MISO_T => NLW_inst_SPI0_MISO_T_UNCONNECTED,
SPI0_MOSI_I => '0',
SPI0_MOSI_O => NLW_inst_SPI0_MOSI_O_UNCONNECTED,
SPI0_MOSI_T => NLW_inst_SPI0_MOSI_T_UNCONNECTED,
SPI0_SCLK_I => '0',
SPI0_SCLK_O => NLW_inst_SPI0_SCLK_O_UNCONNECTED,
SPI0_SCLK_T => NLW_inst_SPI0_SCLK_T_UNCONNECTED,
SPI0_SS1_O => NLW_inst_SPI0_SS1_O_UNCONNECTED,
SPI0_SS2_O => NLW_inst_SPI0_SS2_O_UNCONNECTED,
SPI0_SS_I => '0',
SPI0_SS_O => NLW_inst_SPI0_SS_O_UNCONNECTED,
SPI0_SS_T => NLW_inst_SPI0_SS_T_UNCONNECTED,
SPI1_MISO_I => '0',
SPI1_MISO_O => NLW_inst_SPI1_MISO_O_UNCONNECTED,
SPI1_MISO_T => NLW_inst_SPI1_MISO_T_UNCONNECTED,
SPI1_MOSI_I => '0',
SPI1_MOSI_O => NLW_inst_SPI1_MOSI_O_UNCONNECTED,
SPI1_MOSI_T => NLW_inst_SPI1_MOSI_T_UNCONNECTED,
SPI1_SCLK_I => '0',
SPI1_SCLK_O => NLW_inst_SPI1_SCLK_O_UNCONNECTED,
SPI1_SCLK_T => NLW_inst_SPI1_SCLK_T_UNCONNECTED,
SPI1_SS1_O => NLW_inst_SPI1_SS1_O_UNCONNECTED,
SPI1_SS2_O => NLW_inst_SPI1_SS2_O_UNCONNECTED,
SPI1_SS_I => '0',
SPI1_SS_O => NLW_inst_SPI1_SS_O_UNCONNECTED,
SPI1_SS_T => NLW_inst_SPI1_SS_T_UNCONNECTED,
SRAM_INTIN => '0',
S_AXI_ACP_ACLK => '0',
S_AXI_ACP_ARADDR(31 downto 0) => B"00000000000000000000000000000000",
S_AXI_ACP_ARBURST(1 downto 0) => B"00",
S_AXI_ACP_ARCACHE(3 downto 0) => B"0000",
S_AXI_ACP_ARESETN => NLW_inst_S_AXI_ACP_ARESETN_UNCONNECTED,
S_AXI_ACP_ARID(2 downto 0) => B"000",
S_AXI_ACP_ARLEN(3 downto 0) => B"0000",
S_AXI_ACP_ARLOCK(1 downto 0) => B"00",
S_AXI_ACP_ARPROT(2 downto 0) => B"000",
S_AXI_ACP_ARQOS(3 downto 0) => B"0000",
S_AXI_ACP_ARREADY => NLW_inst_S_AXI_ACP_ARREADY_UNCONNECTED,
S_AXI_ACP_ARSIZE(2 downto 0) => B"000",
S_AXI_ACP_ARUSER(4 downto 0) => B"00000",
S_AXI_ACP_ARVALID => '0',
S_AXI_ACP_AWADDR(31 downto 0) => B"00000000000000000000000000000000",
S_AXI_ACP_AWBURST(1 downto 0) => B"00",
S_AXI_ACP_AWCACHE(3 downto 0) => B"0000",
S_AXI_ACP_AWID(2 downto 0) => B"000",
S_AXI_ACP_AWLEN(3 downto 0) => B"0000",
S_AXI_ACP_AWLOCK(1 downto 0) => B"00",
S_AXI_ACP_AWPROT(2 downto 0) => B"000",
S_AXI_ACP_AWQOS(3 downto 0) => B"0000",
S_AXI_ACP_AWREADY => NLW_inst_S_AXI_ACP_AWREADY_UNCONNECTED,
S_AXI_ACP_AWSIZE(2 downto 0) => B"000",
S_AXI_ACP_AWUSER(4 downto 0) => B"00000",
S_AXI_ACP_AWVALID => '0',
S_AXI_ACP_BID(2 downto 0) => NLW_inst_S_AXI_ACP_BID_UNCONNECTED(2 downto 0),
S_AXI_ACP_BREADY => '0',
S_AXI_ACP_BRESP(1 downto 0) => NLW_inst_S_AXI_ACP_BRESP_UNCONNECTED(1 downto 0),
S_AXI_ACP_BVALID => NLW_inst_S_AXI_ACP_BVALID_UNCONNECTED,
S_AXI_ACP_RDATA(63 downto 0) => NLW_inst_S_AXI_ACP_RDATA_UNCONNECTED(63 downto 0),
S_AXI_ACP_RID(2 downto 0) => NLW_inst_S_AXI_ACP_RID_UNCONNECTED(2 downto 0),
S_AXI_ACP_RLAST => NLW_inst_S_AXI_ACP_RLAST_UNCONNECTED,
S_AXI_ACP_RREADY => '0',
S_AXI_ACP_RRESP(1 downto 0) => NLW_inst_S_AXI_ACP_RRESP_UNCONNECTED(1 downto 0),
S_AXI_ACP_RVALID => NLW_inst_S_AXI_ACP_RVALID_UNCONNECTED,
S_AXI_ACP_WDATA(63 downto 0) => B"0000000000000000000000000000000000000000000000000000000000000000",
S_AXI_ACP_WID(2 downto 0) => B"000",
S_AXI_ACP_WLAST => '0',
S_AXI_ACP_WREADY => NLW_inst_S_AXI_ACP_WREADY_UNCONNECTED,
S_AXI_ACP_WSTRB(7 downto 0) => B"00000000",
S_AXI_ACP_WVALID => '0',
S_AXI_GP0_ACLK => '0',
S_AXI_GP0_ARADDR(31 downto 0) => B"00000000000000000000000000000000",
S_AXI_GP0_ARBURST(1 downto 0) => B"00",
S_AXI_GP0_ARCACHE(3 downto 0) => B"0000",
S_AXI_GP0_ARESETN => NLW_inst_S_AXI_GP0_ARESETN_UNCONNECTED,
S_AXI_GP0_ARID(5 downto 0) => B"000000",
S_AXI_GP0_ARLEN(3 downto 0) => B"0000",
S_AXI_GP0_ARLOCK(1 downto 0) => B"00",
S_AXI_GP0_ARPROT(2 downto 0) => B"000",
S_AXI_GP0_ARQOS(3 downto 0) => B"0000",
S_AXI_GP0_ARREADY => NLW_inst_S_AXI_GP0_ARREADY_UNCONNECTED,
S_AXI_GP0_ARSIZE(2 downto 0) => B"000",
S_AXI_GP0_ARVALID => '0',
S_AXI_GP0_AWADDR(31 downto 0) => B"00000000000000000000000000000000",
S_AXI_GP0_AWBURST(1 downto 0) => B"00",
S_AXI_GP0_AWCACHE(3 downto 0) => B"0000",
S_AXI_GP0_AWID(5 downto 0) => B"000000",
S_AXI_GP0_AWLEN(3 downto 0) => B"0000",
S_AXI_GP0_AWLOCK(1 downto 0) => B"00",
S_AXI_GP0_AWPROT(2 downto 0) => B"000",
S_AXI_GP0_AWQOS(3 downto 0) => B"0000",
S_AXI_GP0_AWREADY => NLW_inst_S_AXI_GP0_AWREADY_UNCONNECTED,
S_AXI_GP0_AWSIZE(2 downto 0) => B"000",
S_AXI_GP0_AWVALID => '0',
S_AXI_GP0_BID(5 downto 0) => NLW_inst_S_AXI_GP0_BID_UNCONNECTED(5 downto 0),
S_AXI_GP0_BREADY => '0',
S_AXI_GP0_BRESP(1 downto 0) => NLW_inst_S_AXI_GP0_BRESP_UNCONNECTED(1 downto 0),
S_AXI_GP0_BVALID => NLW_inst_S_AXI_GP0_BVALID_UNCONNECTED,
S_AXI_GP0_RDATA(31 downto 0) => NLW_inst_S_AXI_GP0_RDATA_UNCONNECTED(31 downto 0),
S_AXI_GP0_RID(5 downto 0) => NLW_inst_S_AXI_GP0_RID_UNCONNECTED(5 downto 0),
S_AXI_GP0_RLAST => NLW_inst_S_AXI_GP0_RLAST_UNCONNECTED,
S_AXI_GP0_RREADY => '0',
S_AXI_GP0_RRESP(1 downto 0) => NLW_inst_S_AXI_GP0_RRESP_UNCONNECTED(1 downto 0),
S_AXI_GP0_RVALID => NLW_inst_S_AXI_GP0_RVALID_UNCONNECTED,
S_AXI_GP0_WDATA(31 downto 0) => B"00000000000000000000000000000000",
S_AXI_GP0_WID(5 downto 0) => B"000000",
S_AXI_GP0_WLAST => '0',
S_AXI_GP0_WREADY => NLW_inst_S_AXI_GP0_WREADY_UNCONNECTED,
S_AXI_GP0_WSTRB(3 downto 0) => B"0000",
S_AXI_GP0_WVALID => '0',
S_AXI_GP1_ACLK => '0',
S_AXI_GP1_ARADDR(31 downto 0) => B"00000000000000000000000000000000",
S_AXI_GP1_ARBURST(1 downto 0) => B"00",
S_AXI_GP1_ARCACHE(3 downto 0) => B"0000",
S_AXI_GP1_ARESETN => NLW_inst_S_AXI_GP1_ARESETN_UNCONNECTED,
S_AXI_GP1_ARID(5 downto 0) => B"000000",
S_AXI_GP1_ARLEN(3 downto 0) => B"0000",
S_AXI_GP1_ARLOCK(1 downto 0) => B"00",
S_AXI_GP1_ARPROT(2 downto 0) => B"000",
S_AXI_GP1_ARQOS(3 downto 0) => B"0000",
S_AXI_GP1_ARREADY => NLW_inst_S_AXI_GP1_ARREADY_UNCONNECTED,
S_AXI_GP1_ARSIZE(2 downto 0) => B"000",
S_AXI_GP1_ARVALID => '0',
S_AXI_GP1_AWADDR(31 downto 0) => B"00000000000000000000000000000000",
S_AXI_GP1_AWBURST(1 downto 0) => B"00",
S_AXI_GP1_AWCACHE(3 downto 0) => B"0000",
S_AXI_GP1_AWID(5 downto 0) => B"000000",
S_AXI_GP1_AWLEN(3 downto 0) => B"0000",
S_AXI_GP1_AWLOCK(1 downto 0) => B"00",
S_AXI_GP1_AWPROT(2 downto 0) => B"000",
S_AXI_GP1_AWQOS(3 downto 0) => B"0000",
S_AXI_GP1_AWREADY => NLW_inst_S_AXI_GP1_AWREADY_UNCONNECTED,
S_AXI_GP1_AWSIZE(2 downto 0) => B"000",
S_AXI_GP1_AWVALID => '0',
S_AXI_GP1_BID(5 downto 0) => NLW_inst_S_AXI_GP1_BID_UNCONNECTED(5 downto 0),
S_AXI_GP1_BREADY => '0',
S_AXI_GP1_BRESP(1 downto 0) => NLW_inst_S_AXI_GP1_BRESP_UNCONNECTED(1 downto 0),
S_AXI_GP1_BVALID => NLW_inst_S_AXI_GP1_BVALID_UNCONNECTED,
S_AXI_GP1_RDATA(31 downto 0) => NLW_inst_S_AXI_GP1_RDATA_UNCONNECTED(31 downto 0),
S_AXI_GP1_RID(5 downto 0) => NLW_inst_S_AXI_GP1_RID_UNCONNECTED(5 downto 0),
S_AXI_GP1_RLAST => NLW_inst_S_AXI_GP1_RLAST_UNCONNECTED,
S_AXI_GP1_RREADY => '0',
S_AXI_GP1_RRESP(1 downto 0) => NLW_inst_S_AXI_GP1_RRESP_UNCONNECTED(1 downto 0),
S_AXI_GP1_RVALID => NLW_inst_S_AXI_GP1_RVALID_UNCONNECTED,
S_AXI_GP1_WDATA(31 downto 0) => B"00000000000000000000000000000000",
S_AXI_GP1_WID(5 downto 0) => B"000000",
S_AXI_GP1_WLAST => '0',
S_AXI_GP1_WREADY => NLW_inst_S_AXI_GP1_WREADY_UNCONNECTED,
S_AXI_GP1_WSTRB(3 downto 0) => B"0000",
S_AXI_GP1_WVALID => '0',
S_AXI_HP0_ACLK => '0',
S_AXI_HP0_ARADDR(31 downto 0) => B"00000000000000000000000000000000",
S_AXI_HP0_ARBURST(1 downto 0) => B"00",
S_AXI_HP0_ARCACHE(3 downto 0) => B"0000",
S_AXI_HP0_ARESETN => NLW_inst_S_AXI_HP0_ARESETN_UNCONNECTED,
S_AXI_HP0_ARID(5 downto 0) => B"000000",
S_AXI_HP0_ARLEN(3 downto 0) => B"0000",
S_AXI_HP0_ARLOCK(1 downto 0) => B"00",
S_AXI_HP0_ARPROT(2 downto 0) => B"000",
S_AXI_HP0_ARQOS(3 downto 0) => B"0000",
S_AXI_HP0_ARREADY => NLW_inst_S_AXI_HP0_ARREADY_UNCONNECTED,
S_AXI_HP0_ARSIZE(2 downto 0) => B"000",
S_AXI_HP0_ARVALID => '0',
S_AXI_HP0_AWADDR(31 downto 0) => B"00000000000000000000000000000000",
S_AXI_HP0_AWBURST(1 downto 0) => B"00",
S_AXI_HP0_AWCACHE(3 downto 0) => B"0000",
S_AXI_HP0_AWID(5 downto 0) => B"000000",
S_AXI_HP0_AWLEN(3 downto 0) => B"0000",
S_AXI_HP0_AWLOCK(1 downto 0) => B"00",
S_AXI_HP0_AWPROT(2 downto 0) => B"000",
S_AXI_HP0_AWQOS(3 downto 0) => B"0000",
S_AXI_HP0_AWREADY => NLW_inst_S_AXI_HP0_AWREADY_UNCONNECTED,
S_AXI_HP0_AWSIZE(2 downto 0) => B"000",
S_AXI_HP0_AWVALID => '0',
S_AXI_HP0_BID(5 downto 0) => NLW_inst_S_AXI_HP0_BID_UNCONNECTED(5 downto 0),
S_AXI_HP0_BREADY => '0',
S_AXI_HP0_BRESP(1 downto 0) => NLW_inst_S_AXI_HP0_BRESP_UNCONNECTED(1 downto 0),
S_AXI_HP0_BVALID => NLW_inst_S_AXI_HP0_BVALID_UNCONNECTED,
S_AXI_HP0_RACOUNT(2 downto 0) => NLW_inst_S_AXI_HP0_RACOUNT_UNCONNECTED(2 downto 0),
S_AXI_HP0_RCOUNT(7 downto 0) => NLW_inst_S_AXI_HP0_RCOUNT_UNCONNECTED(7 downto 0),
S_AXI_HP0_RDATA(63 downto 0) => NLW_inst_S_AXI_HP0_RDATA_UNCONNECTED(63 downto 0),
S_AXI_HP0_RDISSUECAP1_EN => '0',
S_AXI_HP0_RID(5 downto 0) => NLW_inst_S_AXI_HP0_RID_UNCONNECTED(5 downto 0),
S_AXI_HP0_RLAST => NLW_inst_S_AXI_HP0_RLAST_UNCONNECTED,
S_AXI_HP0_RREADY => '0',
S_AXI_HP0_RRESP(1 downto 0) => NLW_inst_S_AXI_HP0_RRESP_UNCONNECTED(1 downto 0),
S_AXI_HP0_RVALID => NLW_inst_S_AXI_HP0_RVALID_UNCONNECTED,
S_AXI_HP0_WACOUNT(5 downto 0) => NLW_inst_S_AXI_HP0_WACOUNT_UNCONNECTED(5 downto 0),
S_AXI_HP0_WCOUNT(7 downto 0) => NLW_inst_S_AXI_HP0_WCOUNT_UNCONNECTED(7 downto 0),
S_AXI_HP0_WDATA(63 downto 0) => B"0000000000000000000000000000000000000000000000000000000000000000",
S_AXI_HP0_WID(5 downto 0) => B"000000",
S_AXI_HP0_WLAST => '0',
S_AXI_HP0_WREADY => NLW_inst_S_AXI_HP0_WREADY_UNCONNECTED,
S_AXI_HP0_WRISSUECAP1_EN => '0',
S_AXI_HP0_WSTRB(7 downto 0) => B"00000000",
S_AXI_HP0_WVALID => '0',
S_AXI_HP1_ACLK => '0',
S_AXI_HP1_ARADDR(31 downto 0) => B"00000000000000000000000000000000",
S_AXI_HP1_ARBURST(1 downto 0) => B"00",
S_AXI_HP1_ARCACHE(3 downto 0) => B"0000",
S_AXI_HP1_ARESETN => NLW_inst_S_AXI_HP1_ARESETN_UNCONNECTED,
S_AXI_HP1_ARID(5 downto 0) => B"000000",
S_AXI_HP1_ARLEN(3 downto 0) => B"0000",
S_AXI_HP1_ARLOCK(1 downto 0) => B"00",
S_AXI_HP1_ARPROT(2 downto 0) => B"000",
S_AXI_HP1_ARQOS(3 downto 0) => B"0000",
S_AXI_HP1_ARREADY => NLW_inst_S_AXI_HP1_ARREADY_UNCONNECTED,
S_AXI_HP1_ARSIZE(2 downto 0) => B"000",
S_AXI_HP1_ARVALID => '0',
S_AXI_HP1_AWADDR(31 downto 0) => B"00000000000000000000000000000000",
S_AXI_HP1_AWBURST(1 downto 0) => B"00",
S_AXI_HP1_AWCACHE(3 downto 0) => B"0000",
S_AXI_HP1_AWID(5 downto 0) => B"000000",
S_AXI_HP1_AWLEN(3 downto 0) => B"0000",
S_AXI_HP1_AWLOCK(1 downto 0) => B"00",
S_AXI_HP1_AWPROT(2 downto 0) => B"000",
S_AXI_HP1_AWQOS(3 downto 0) => B"0000",
S_AXI_HP1_AWREADY => NLW_inst_S_AXI_HP1_AWREADY_UNCONNECTED,
S_AXI_HP1_AWSIZE(2 downto 0) => B"000",
S_AXI_HP1_AWVALID => '0',
S_AXI_HP1_BID(5 downto 0) => NLW_inst_S_AXI_HP1_BID_UNCONNECTED(5 downto 0),
S_AXI_HP1_BREADY => '0',
S_AXI_HP1_BRESP(1 downto 0) => NLW_inst_S_AXI_HP1_BRESP_UNCONNECTED(1 downto 0),
S_AXI_HP1_BVALID => NLW_inst_S_AXI_HP1_BVALID_UNCONNECTED,
S_AXI_HP1_RACOUNT(2 downto 0) => NLW_inst_S_AXI_HP1_RACOUNT_UNCONNECTED(2 downto 0),
S_AXI_HP1_RCOUNT(7 downto 0) => NLW_inst_S_AXI_HP1_RCOUNT_UNCONNECTED(7 downto 0),
S_AXI_HP1_RDATA(63 downto 0) => NLW_inst_S_AXI_HP1_RDATA_UNCONNECTED(63 downto 0),
S_AXI_HP1_RDISSUECAP1_EN => '0',
S_AXI_HP1_RID(5 downto 0) => NLW_inst_S_AXI_HP1_RID_UNCONNECTED(5 downto 0),
S_AXI_HP1_RLAST => NLW_inst_S_AXI_HP1_RLAST_UNCONNECTED,
S_AXI_HP1_RREADY => '0',
S_AXI_HP1_RRESP(1 downto 0) => NLW_inst_S_AXI_HP1_RRESP_UNCONNECTED(1 downto 0),
S_AXI_HP1_RVALID => NLW_inst_S_AXI_HP1_RVALID_UNCONNECTED,
S_AXI_HP1_WACOUNT(5 downto 0) => NLW_inst_S_AXI_HP1_WACOUNT_UNCONNECTED(5 downto 0),
S_AXI_HP1_WCOUNT(7 downto 0) => NLW_inst_S_AXI_HP1_WCOUNT_UNCONNECTED(7 downto 0),
S_AXI_HP1_WDATA(63 downto 0) => B"0000000000000000000000000000000000000000000000000000000000000000",
S_AXI_HP1_WID(5 downto 0) => B"000000",
S_AXI_HP1_WLAST => '0',
S_AXI_HP1_WREADY => NLW_inst_S_AXI_HP1_WREADY_UNCONNECTED,
S_AXI_HP1_WRISSUECAP1_EN => '0',
S_AXI_HP1_WSTRB(7 downto 0) => B"00000000",
S_AXI_HP1_WVALID => '0',
S_AXI_HP2_ACLK => '0',
S_AXI_HP2_ARADDR(31 downto 0) => B"00000000000000000000000000000000",
S_AXI_HP2_ARBURST(1 downto 0) => B"00",
S_AXI_HP2_ARCACHE(3 downto 0) => B"0000",
S_AXI_HP2_ARESETN => NLW_inst_S_AXI_HP2_ARESETN_UNCONNECTED,
S_AXI_HP2_ARID(5 downto 0) => B"000000",
S_AXI_HP2_ARLEN(3 downto 0) => B"0000",
S_AXI_HP2_ARLOCK(1 downto 0) => B"00",
S_AXI_HP2_ARPROT(2 downto 0) => B"000",
S_AXI_HP2_ARQOS(3 downto 0) => B"0000",
S_AXI_HP2_ARREADY => NLW_inst_S_AXI_HP2_ARREADY_UNCONNECTED,
S_AXI_HP2_ARSIZE(2 downto 0) => B"000",
S_AXI_HP2_ARVALID => '0',
S_AXI_HP2_AWADDR(31 downto 0) => B"00000000000000000000000000000000",
S_AXI_HP2_AWBURST(1 downto 0) => B"00",
S_AXI_HP2_AWCACHE(3 downto 0) => B"0000",
S_AXI_HP2_AWID(5 downto 0) => B"000000",
S_AXI_HP2_AWLEN(3 downto 0) => B"0000",
S_AXI_HP2_AWLOCK(1 downto 0) => B"00",
S_AXI_HP2_AWPROT(2 downto 0) => B"000",
S_AXI_HP2_AWQOS(3 downto 0) => B"0000",
S_AXI_HP2_AWREADY => NLW_inst_S_AXI_HP2_AWREADY_UNCONNECTED,
S_AXI_HP2_AWSIZE(2 downto 0) => B"000",
S_AXI_HP2_AWVALID => '0',
S_AXI_HP2_BID(5 downto 0) => NLW_inst_S_AXI_HP2_BID_UNCONNECTED(5 downto 0),
S_AXI_HP2_BREADY => '0',
S_AXI_HP2_BRESP(1 downto 0) => NLW_inst_S_AXI_HP2_BRESP_UNCONNECTED(1 downto 0),
S_AXI_HP2_BVALID => NLW_inst_S_AXI_HP2_BVALID_UNCONNECTED,
S_AXI_HP2_RACOUNT(2 downto 0) => NLW_inst_S_AXI_HP2_RACOUNT_UNCONNECTED(2 downto 0),
S_AXI_HP2_RCOUNT(7 downto 0) => NLW_inst_S_AXI_HP2_RCOUNT_UNCONNECTED(7 downto 0),
S_AXI_HP2_RDATA(63 downto 0) => NLW_inst_S_AXI_HP2_RDATA_UNCONNECTED(63 downto 0),
S_AXI_HP2_RDISSUECAP1_EN => '0',
S_AXI_HP2_RID(5 downto 0) => NLW_inst_S_AXI_HP2_RID_UNCONNECTED(5 downto 0),
S_AXI_HP2_RLAST => NLW_inst_S_AXI_HP2_RLAST_UNCONNECTED,
S_AXI_HP2_RREADY => '0',
S_AXI_HP2_RRESP(1 downto 0) => NLW_inst_S_AXI_HP2_RRESP_UNCONNECTED(1 downto 0),
S_AXI_HP2_RVALID => NLW_inst_S_AXI_HP2_RVALID_UNCONNECTED,
S_AXI_HP2_WACOUNT(5 downto 0) => NLW_inst_S_AXI_HP2_WACOUNT_UNCONNECTED(5 downto 0),
S_AXI_HP2_WCOUNT(7 downto 0) => NLW_inst_S_AXI_HP2_WCOUNT_UNCONNECTED(7 downto 0),
S_AXI_HP2_WDATA(63 downto 0) => B"0000000000000000000000000000000000000000000000000000000000000000",
S_AXI_HP2_WID(5 downto 0) => B"000000",
S_AXI_HP2_WLAST => '0',
S_AXI_HP2_WREADY => NLW_inst_S_AXI_HP2_WREADY_UNCONNECTED,
S_AXI_HP2_WRISSUECAP1_EN => '0',
S_AXI_HP2_WSTRB(7 downto 0) => B"00000000",
S_AXI_HP2_WVALID => '0',
S_AXI_HP3_ACLK => '0',
S_AXI_HP3_ARADDR(31 downto 0) => B"00000000000000000000000000000000",
S_AXI_HP3_ARBURST(1 downto 0) => B"00",
S_AXI_HP3_ARCACHE(3 downto 0) => B"0000",
S_AXI_HP3_ARESETN => NLW_inst_S_AXI_HP3_ARESETN_UNCONNECTED,
S_AXI_HP3_ARID(5 downto 0) => B"000000",
S_AXI_HP3_ARLEN(3 downto 0) => B"0000",
S_AXI_HP3_ARLOCK(1 downto 0) => B"00",
S_AXI_HP3_ARPROT(2 downto 0) => B"000",
S_AXI_HP3_ARQOS(3 downto 0) => B"0000",
S_AXI_HP3_ARREADY => NLW_inst_S_AXI_HP3_ARREADY_UNCONNECTED,
S_AXI_HP3_ARSIZE(2 downto 0) => B"000",
S_AXI_HP3_ARVALID => '0',
S_AXI_HP3_AWADDR(31 downto 0) => B"00000000000000000000000000000000",
S_AXI_HP3_AWBURST(1 downto 0) => B"00",
S_AXI_HP3_AWCACHE(3 downto 0) => B"0000",
S_AXI_HP3_AWID(5 downto 0) => B"000000",
S_AXI_HP3_AWLEN(3 downto 0) => B"0000",
S_AXI_HP3_AWLOCK(1 downto 0) => B"00",
S_AXI_HP3_AWPROT(2 downto 0) => B"000",
S_AXI_HP3_AWQOS(3 downto 0) => B"0000",
S_AXI_HP3_AWREADY => NLW_inst_S_AXI_HP3_AWREADY_UNCONNECTED,
S_AXI_HP3_AWSIZE(2 downto 0) => B"000",
S_AXI_HP3_AWVALID => '0',
S_AXI_HP3_BID(5 downto 0) => NLW_inst_S_AXI_HP3_BID_UNCONNECTED(5 downto 0),
S_AXI_HP3_BREADY => '0',
S_AXI_HP3_BRESP(1 downto 0) => NLW_inst_S_AXI_HP3_BRESP_UNCONNECTED(1 downto 0),
S_AXI_HP3_BVALID => NLW_inst_S_AXI_HP3_BVALID_UNCONNECTED,
S_AXI_HP3_RACOUNT(2 downto 0) => NLW_inst_S_AXI_HP3_RACOUNT_UNCONNECTED(2 downto 0),
S_AXI_HP3_RCOUNT(7 downto 0) => NLW_inst_S_AXI_HP3_RCOUNT_UNCONNECTED(7 downto 0),
S_AXI_HP3_RDATA(63 downto 0) => NLW_inst_S_AXI_HP3_RDATA_UNCONNECTED(63 downto 0),
S_AXI_HP3_RDISSUECAP1_EN => '0',
S_AXI_HP3_RID(5 downto 0) => NLW_inst_S_AXI_HP3_RID_UNCONNECTED(5 downto 0),
S_AXI_HP3_RLAST => NLW_inst_S_AXI_HP3_RLAST_UNCONNECTED,
S_AXI_HP3_RREADY => '0',
S_AXI_HP3_RRESP(1 downto 0) => NLW_inst_S_AXI_HP3_RRESP_UNCONNECTED(1 downto 0),
S_AXI_HP3_RVALID => NLW_inst_S_AXI_HP3_RVALID_UNCONNECTED,
S_AXI_HP3_WACOUNT(5 downto 0) => NLW_inst_S_AXI_HP3_WACOUNT_UNCONNECTED(5 downto 0),
S_AXI_HP3_WCOUNT(7 downto 0) => NLW_inst_S_AXI_HP3_WCOUNT_UNCONNECTED(7 downto 0),
S_AXI_HP3_WDATA(63 downto 0) => B"0000000000000000000000000000000000000000000000000000000000000000",
S_AXI_HP3_WID(5 downto 0) => B"000000",
S_AXI_HP3_WLAST => '0',
S_AXI_HP3_WREADY => NLW_inst_S_AXI_HP3_WREADY_UNCONNECTED,
S_AXI_HP3_WRISSUECAP1_EN => '0',
S_AXI_HP3_WSTRB(7 downto 0) => B"00000000",
S_AXI_HP3_WVALID => '0',
TRACE_CLK => '0',
TRACE_CLK_OUT => NLW_inst_TRACE_CLK_OUT_UNCONNECTED,
TRACE_CTL => NLW_inst_TRACE_CTL_UNCONNECTED,
TRACE_DATA(1 downto 0) => NLW_inst_TRACE_DATA_UNCONNECTED(1 downto 0),
TTC0_CLK0_IN => '0',
TTC0_CLK1_IN => '0',
TTC0_CLK2_IN => '0',
TTC0_WAVE0_OUT => TTC0_WAVE0_OUT,
TTC0_WAVE1_OUT => TTC0_WAVE1_OUT,
TTC0_WAVE2_OUT => TTC0_WAVE2_OUT,
TTC1_CLK0_IN => '0',
TTC1_CLK1_IN => '0',
TTC1_CLK2_IN => '0',
TTC1_WAVE0_OUT => NLW_inst_TTC1_WAVE0_OUT_UNCONNECTED,
TTC1_WAVE1_OUT => NLW_inst_TTC1_WAVE1_OUT_UNCONNECTED,
TTC1_WAVE2_OUT => NLW_inst_TTC1_WAVE2_OUT_UNCONNECTED,
UART0_CTSN => '0',
UART0_DCDN => '0',
UART0_DSRN => '0',
UART0_DTRN => NLW_inst_UART0_DTRN_UNCONNECTED,
UART0_RIN => '0',
UART0_RTSN => NLW_inst_UART0_RTSN_UNCONNECTED,
UART0_RX => '1',
UART0_TX => NLW_inst_UART0_TX_UNCONNECTED,
UART1_CTSN => '0',
UART1_DCDN => '0',
UART1_DSRN => '0',
UART1_DTRN => NLW_inst_UART1_DTRN_UNCONNECTED,
UART1_RIN => '0',
UART1_RTSN => NLW_inst_UART1_RTSN_UNCONNECTED,
UART1_RX => '1',
UART1_TX => NLW_inst_UART1_TX_UNCONNECTED,
USB0_PORT_INDCTL(1 downto 0) => USB0_PORT_INDCTL(1 downto 0),
USB0_VBUS_PWRFAULT => USB0_VBUS_PWRFAULT,
USB0_VBUS_PWRSELECT => USB0_VBUS_PWRSELECT,
USB1_PORT_INDCTL(1 downto 0) => NLW_inst_USB1_PORT_INDCTL_UNCONNECTED(1 downto 0),
USB1_VBUS_PWRFAULT => '0',
USB1_VBUS_PWRSELECT => NLW_inst_USB1_VBUS_PWRSELECT_UNCONNECTED,
WDT_CLK_IN => '0',
WDT_RST_OUT => NLW_inst_WDT_RST_OUT_UNCONNECTED
);
end STRUCTURE;
| mit | 5479c3bcdeb7fa18c4a1452795be0081 | 0.639711 | 2.767405 | false | false | false | false |
besm6/micro-besm | tests/2901/vhdl/alg_beh/alg_beh2901.vhdl | 1 | 7,828 | --------------------------------------------------------------------------------
--
-- AM2901 Benchmark
--
-- Source: AMD data book
--
-- VHDL Benchmark author Indraneel Ghosh
-- University Of California, Irvine, CA 92717
--
-- Developed on Jan 1, 1992
--
-- Verification Information:
--
-- Verified By whom? Date Simulator
-- -------- ------------ -------- ------------
-- Syntax yes Champaka Ramachandran Sept19, 92 ZYCAD
-- Functionality yes Champaka Ramachandran Sept19, 92 ZYCAD
--------------------------------------------------------------------------------
use work.TYPES.all;
use work.MVL7_functions.all; -- some MVL7 functions
use work.synthesis_types.all; -- some data types ( hints for synthesis)
entity a2901 is
port (
I : in MVL7_vector(8 downto 0);
Aadd, Badd : in integer range 0 to 15;
D : in MVL7_vector(3 downto 0);
Y : out MVL7_vector(3 downto 0);
RAM0, RAM3, Q0, Q3 : in MVL7;
RAM0out, RAM3out, Q0out, Q3out : out MVL7;
CLK : in clock;
C0 : in MVL7;
OEbar : in MVL7;
C4, Gbar, Pbar, OVR, F3, F30 : out MVL7
);
end a2901;
architecture a2901 of a2901 is
begin
process
variable A, B : MVL7_vector(3 downto 0);
variable RAM : Memory(15 downto 0);
variable Q : MVL7_vector(3 downto 0);
variable RE, S : MVL7_vector(3 downto 0);
variable F : MVL7_vector(3 downto 0);
variable dout : MVL7_vector(3 downto 0);
variable R_ext,S_ext,result : MVL7_vector(4 downto 0);
variable temp_p, temp_g : MVL7_vector(3 downto 0) ;
begin
wait until ( (clk = '0') and (not clk'stable) );
A := RAM(Aadd); -- RAM OUTPUTS ( ADDRESSED BY Aadd AND Badd ) ARE
B := RAM(Badd); -- MADE AVAILABLE TO ALU SOURCE SELECTOR
-- SELECT THE SOURCE OPERANDS FOR ALU. SELECTED OPERANDS ARE "RE" AND "S".
case I(2 downto 0) is
when "000" =>
RE := A;
S := Q;
when "001" =>
RE := A;
S := B;
when "010" =>
RE := "0000";
S := Q;
when "011" =>
RE := "0000";
S := B;
when "100" =>
RE := "0000";
S := A;
when "101" =>
RE := D;
S := A;
when "110" =>
RE := D;
S := Q;
when "111" =>
RE := D;
S := "0000";
when others =>
end case;
-- SELECT THE FUNCTION FOR ALU.
-- TO FACILITATE COMPUTATION OF CARRY-OUT "C4", WE EXTEND THE CHOSEN
-- ALU OPERANDS "RE" AND "S" (4 BIT OPERANDS) BY 1 BIT IN THE MSB POSITION.
-- THUS THE EXTENDED OPERANDS "R_EXT" AND "S_EXT" (5 BIT OPERANDS) ARE
-- FORMED AND ARE USED IN THE ALU OPERATION. THE EXTRA BIT IS SET TO '0'
-- INITIALLY. THE ALU'S EXTENDED OUTPUT ( 5 BITS LONG) IS "result".
-- IN THE ADD/SUBTRACT OPERATIONS, THE CARRY-INPUT "C0" (1 BIT) IS EXTENDED
-- BY 4 BITS ( ALL '0') IN THE MORE SIGNIFICANT BITS TO MATCH ITS LENGTH TO
-- THAT OF "R_ext" AND "S_ext". THEN, THESE THREE OPERANDS ARE ADDED.
-- ADD/SUBTRACT OPERATIONS ARE DONE ON 2'S COMPLEMENT OPERANDS.
case I(5 downto 3) is
when "000" =>
R_ext := '0' & RE;
S_ext := '0' & S;
result := R_ext + S_ext + ("0000" & C0);
when "001" =>
R_ext := '0' & not(RE);
S_ext := '0' & S;
result := R_ext + S_ext + ("0000" & C0);
when "010" =>
R_ext := '0' & RE;
S_ext := '0' & not(S);
result := R_ext + S_ext + ("0000" & C0);
when "011" =>
R_ext := '0' & RE;
S_ext := '0' & S;
result := R_ext or S_ext;
when "100" =>
R_ext := '0' & RE;
S_ext := '0' & S;
result := R_ext and S_ext;
when "101" =>
R_ext := '0' & RE;
S_ext := '0' & S;
result := not(R_ext) and S_ext;
when "110" =>
R_ext := '0' & RE;
S_ext := '0' & S;
result := R_ext xor S_ext;
when "111" =>
R_ext := '0' & RE;
S_ext := '0' & S;
result := not(R_ext xor S_ext);
when others =>
end case;
-- EVALUATE OTHER ALU OUTPUTS.
-- FROM EXTENDED OUTPUT "result" ( 5 BITS), WE OBTAIN THE NORMAL ALU OUTPUT,
-- "F" (4 BITS) BY LEAVING OUT THE MSB ( WHICH CORRESPONDS TO CARRY-OUT
-- "C4").
-- TO FACILITATE COMPUTATION OF CARRY LOOKAHEAD TERMS "Pbar" AND "Gbar", WE
-- COMPUTE INTERMEDIATE TERMS "temp_p" AND "temp_g".
C4 <= result(4) ;
OVR <= not (R_ext(3) xor S_ext(3)) and
(R_ext(3) xor result(3)) ;
F := result(3 downto 0) ;
temp_p := R_ext(3 downto 0) or S_ext(3 downto 0);
temp_g := R_ext(3 downto 0) and S_ext(3 downto 0);
Pbar <= not( temp_p(0) and temp_p(1) and temp_p(2) and temp_p(3) ) ;
Gbar <= not( temp_g(3) or
( temp_p(3) and temp_g(2) ) or
(temp_p(3) and temp_p(2) and temp_g(1) ) or
(temp_p(3) and temp_p(2) and temp_p(1) and temp_g(0) )
);
F3 <= result(3) ;
F30 <= not( result(3) or result(2) or result(1) or result(0) ) ;
-- GENERATE INTERMEDIATE OUTPUT "dout" AND BIDIRECTIONAL SHIFTER SIGNALS.
-- WRITE TO DESTINATION(S) WITH/WITHOUT SHIFTING. RAM DESTINATIONS ARE
-- ADDRESSED BY "Badd".
case I(8 downto 6) is
when "000" =>
dout := F; -- INTERMEDIATE OUTPUT
Q := F; -- WRITE TO DESTINATION
Q0out <= 'Z';
Q3out <= 'Z';
RAM0out <= 'Z';
RAM3out <= 'Z';
when "001" =>
dout := F;
Q0out <= 'Z';
Q3out <= 'Z';
RAM0out <= 'Z';
RAM3out <= 'Z';
when "010" =>
dout := A;
RAM(Badd) := F;
Q0out <= 'Z';
Q3out <= 'Z';
RAM0out <= 'Z';
RAM3out <= 'Z';
when "011" =>
dout := F;
RAM(Badd) := F;
Q0out <= 'Z';
Q3out <= 'Z';
RAM0out <= 'Z';
RAM3out <= 'Z';
when "100" =>
dout := F;
RAM(Badd) := RAM3 & F(3 downto 1);
Q := Q3 & Q(3 downto 1);
Q3out <= 'Z';
RAM3out <= 'Z';
RAM0out <= F(0) ; -- SHIFTER SIGNALS
Q0out <= Q(0) ;
when "101" =>
dout := F;
RAM(Badd) := RAM3 & F(3 downto 1);
Q0out <= 'Z';
Q3out <= 'Z';
RAM3out <= 'Z';
RAM0out <= F(0) ;
when "110" =>
dout := F;
RAM(Badd) := F(2 downto 0) & RAM0;
Q := Q(2 downto 0) & Q0;
Q0out <= 'Z';
RAM0out <= 'Z';
RAM3out <= F(3) ;
Q3out <= Q(3) ;
when "111" =>
dout := F;
RAM(Badd) := F(2 downto 0) & RAM0;
Q0out <= 'Z';
Q3out <= 'Z';
RAM0out <= 'Z';
RAM3out <= F(3) ;
when others =>
end case;
-- GENERATE DATA OUTPUT "Y" FROM INTERMEDIATE OUTPUT "dout".
if (OEbar = '0') then
Y <= dout;
else
Y <= "ZZZZ";
end if;
end process;
end a2901;
| mit | 65a5c02ac479981d63cee501333071c0 | 0.420158 | 3.388745 | false | false | false | false |
Feuerwerk/fpgaNES | debounce.vhd | 1 | 1,823 | /*
This file is part of fpgaNES.
fpgaNES is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.
fpgaNES is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with fpgaNES. If not, see <http://www.gnu.org/licenses/>.
from http://www.lothar-miller.de/s9y/categories/5-Entprellung
*/
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity debounce is
port
(
i_clk : in std_logic;
i_in : in std_logic;
o_q : out std_logic;
o_riseedge : out std_logic;
o_falledge : out std_logic
);
end debounce;
architecture behavioral of debounce is
signal s_prescaler : integer range 0 to 10239;
signal s_shift_register : std_logic_vector(3 downto 0) := (others => '0');
begin
process (i_clk)
begin
if rising_edge(i_clk) then
o_riseedge <= '0';
o_falledge <= '0';
if s_prescaler = 0 then
s_prescaler <= 10239;
-- Pegel zuweisen
if s_shift_register = "0000" then
o_q <= '0';
end if;
if s_shift_register = "1111" then
o_q <= '1';
end if;
-- steigende Flanke
if s_shift_register = "0111" then
o_riseedge <= '1';
end if;
-- fallende Flanke
if s_shift_register = "1000" then
o_falledge <= '1';
end if;
-- von rechts Eintakten
s_shift_register <= s_shift_register(2 downto 0) & i_in;
else
s_prescaler <= s_prescaler - 1;
end if;
end if;
end process;
end behavioral;
| gpl-3.0 | c521fd367e0d987a733f341afb08643b | 0.670324 | 3.079392 | false | false | false | false |
Feuerwerk/fpgaNES | audio_pll.vhd | 1 | 17,849 | -- megafunction wizard: %PLL Intel FPGA IP v18.0%
-- GENERATION: XML
-- audio_pll.vhd
-- Generated using ACDS version 18.0 614
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity audio_pll is
port (
refclk : in std_logic := '0'; -- refclk.clk
rst : in std_logic := '0'; -- reset.reset
outclk_0 : out std_logic; -- outclk0.clk
locked : out std_logic -- locked.export
);
end entity audio_pll;
architecture rtl of audio_pll is
component audio_pll_0002 is
port (
refclk : in std_logic := 'X'; -- clk
rst : in std_logic := 'X'; -- reset
outclk_0 : out std_logic; -- clk
locked : out std_logic -- export
);
end component audio_pll_0002;
begin
audio_pll_inst : component audio_pll_0002
port map (
refclk => refclk, -- refclk.clk
rst => rst, -- reset.reset
outclk_0 => outclk_0, -- outclk0.clk
locked => locked -- locked.export
);
end architecture rtl; -- of audio_pll
-- Retrieval info: <?xml version="1.0"?>
--<!--
-- Generated by Altera MegaWizard Launcher Utility version 1.0
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
-- ************************************************************
-- Copyright (C) 1991-2018 Altera Corporation
-- Any megafunction design, and related net list (encrypted or decrypted),
-- support information, device programming or simulation file, and any other
-- associated documentation or information provided by Altera or a partner
-- under Altera's Megafunction Partnership Program may be used only to
-- program PLD devices (but not masked PLD devices) from Altera. Any other
-- use of such megafunction design, net list, support information, device
-- programming or simulation file, or any other related documentation or
-- information is prohibited for any other purpose, including, but not
-- limited to modification, reverse engineering, de-compiling, or use with
-- any other silicon devices, unless such use is explicitly licensed under
-- a separate agreement with Altera or a megafunction partner. Title to
-- the intellectual property, including patents, copyrights, trademarks,
-- trade secrets, or maskworks, embodied in any such megafunction design,
-- net list, support information, device programming or simulation file, or
-- any other related documentation or information provided by Altera or a
-- megafunction partner, remains with Altera, the megafunction partner, or
-- their respective licensors. No other licenses, including any licenses
-- needed under any third party's intellectual property, are provided herein.
---->
-- Retrieval info: <instance entity-name="altera_pll" version="18.0" >
-- Retrieval info: <generic name="debug_print_output" value="false" />
-- Retrieval info: <generic name="debug_use_rbc_taf_method" value="false" />
-- Retrieval info: <generic name="device_family" value="Cyclone V" />
-- Retrieval info: <generic name="device" value="Unknown" />
-- Retrieval info: <generic name="gui_device_speed_grade" value="2" />
-- Retrieval info: <generic name="gui_pll_mode" value="Integer-N PLL" />
-- Retrieval info: <generic name="gui_reference_clock_frequency" value="50.0" />
-- Retrieval info: <generic name="gui_channel_spacing" value="0.0" />
-- Retrieval info: <generic name="gui_operation_mode" value="direct" />
-- Retrieval info: <generic name="gui_feedback_clock" value="Global Clock" />
-- Retrieval info: <generic name="gui_fractional_cout" value="32" />
-- Retrieval info: <generic name="gui_dsm_out_sel" value="1st_order" />
-- Retrieval info: <generic name="gui_use_locked" value="true" />
-- Retrieval info: <generic name="gui_en_adv_params" value="false" />
-- Retrieval info: <generic name="gui_number_of_clocks" value="1" />
-- Retrieval info: <generic name="gui_multiply_factor" value="1" />
-- Retrieval info: <generic name="gui_frac_multiply_factor" value="1" />
-- Retrieval info: <generic name="gui_divide_factor_n" value="1" />
-- Retrieval info: <generic name="gui_cascade_counter0" value="false" />
-- Retrieval info: <generic name="gui_output_clock_frequency0" value="11.2896" />
-- Retrieval info: <generic name="gui_divide_factor_c0" value="1" />
-- Retrieval info: <generic name="gui_actual_output_clock_frequency0" value="0 MHz" />
-- Retrieval info: <generic name="gui_ps_units0" value="ps" />
-- Retrieval info: <generic name="gui_phase_shift0" value="0" />
-- Retrieval info: <generic name="gui_phase_shift_deg0" value="0.0" />
-- Retrieval info: <generic name="gui_actual_phase_shift0" value="0" />
-- Retrieval info: <generic name="gui_duty_cycle0" value="50" />
-- Retrieval info: <generic name="gui_cascade_counter1" value="false" />
-- Retrieval info: <generic name="gui_output_clock_frequency1" value="100.0" />
-- Retrieval info: <generic name="gui_divide_factor_c1" value="1" />
-- Retrieval info: <generic name="gui_actual_output_clock_frequency1" value="0 MHz" />
-- Retrieval info: <generic name="gui_ps_units1" value="ps" />
-- Retrieval info: <generic name="gui_phase_shift1" value="0" />
-- Retrieval info: <generic name="gui_phase_shift_deg1" value="0.0" />
-- Retrieval info: <generic name="gui_actual_phase_shift1" value="0" />
-- Retrieval info: <generic name="gui_duty_cycle1" value="50" />
-- Retrieval info: <generic name="gui_cascade_counter2" value="false" />
-- Retrieval info: <generic name="gui_output_clock_frequency2" value="100.0" />
-- Retrieval info: <generic name="gui_divide_factor_c2" value="1" />
-- Retrieval info: <generic name="gui_actual_output_clock_frequency2" value="0 MHz" />
-- Retrieval info: <generic name="gui_ps_units2" value="ps" />
-- Retrieval info: <generic name="gui_phase_shift2" value="0" />
-- Retrieval info: <generic name="gui_phase_shift_deg2" value="0.0" />
-- Retrieval info: <generic name="gui_actual_phase_shift2" value="0" />
-- Retrieval info: <generic name="gui_duty_cycle2" value="50" />
-- Retrieval info: <generic name="gui_cascade_counter3" value="false" />
-- Retrieval info: <generic name="gui_output_clock_frequency3" value="100.0" />
-- Retrieval info: <generic name="gui_divide_factor_c3" value="1" />
-- Retrieval info: <generic name="gui_actual_output_clock_frequency3" value="0 MHz" />
-- Retrieval info: <generic name="gui_ps_units3" value="ps" />
-- Retrieval info: <generic name="gui_phase_shift3" value="0" />
-- Retrieval info: <generic name="gui_phase_shift_deg3" value="0.0" />
-- Retrieval info: <generic name="gui_actual_phase_shift3" value="0" />
-- Retrieval info: <generic name="gui_duty_cycle3" value="50" />
-- Retrieval info: <generic name="gui_cascade_counter4" value="false" />
-- Retrieval info: <generic name="gui_output_clock_frequency4" value="100.0" />
-- Retrieval info: <generic name="gui_divide_factor_c4" value="1" />
-- Retrieval info: <generic name="gui_actual_output_clock_frequency4" value="0 MHz" />
-- Retrieval info: <generic name="gui_ps_units4" value="ps" />
-- Retrieval info: <generic name="gui_phase_shift4" value="0" />
-- Retrieval info: <generic name="gui_phase_shift_deg4" value="0.0" />
-- Retrieval info: <generic name="gui_actual_phase_shift4" value="0" />
-- Retrieval info: <generic name="gui_duty_cycle4" value="50" />
-- Retrieval info: <generic name="gui_cascade_counter5" value="false" />
-- Retrieval info: <generic name="gui_output_clock_frequency5" value="100.0" />
-- Retrieval info: <generic name="gui_divide_factor_c5" value="1" />
-- Retrieval info: <generic name="gui_actual_output_clock_frequency5" value="0 MHz" />
-- Retrieval info: <generic name="gui_ps_units5" value="ps" />
-- Retrieval info: <generic name="gui_phase_shift5" value="0" />
-- Retrieval info: <generic name="gui_phase_shift_deg5" value="0.0" />
-- Retrieval info: <generic name="gui_actual_phase_shift5" value="0" />
-- Retrieval info: <generic name="gui_duty_cycle5" value="50" />
-- Retrieval info: <generic name="gui_cascade_counter6" value="false" />
-- Retrieval info: <generic name="gui_output_clock_frequency6" value="100.0" />
-- Retrieval info: <generic name="gui_divide_factor_c6" value="1" />
-- Retrieval info: <generic name="gui_actual_output_clock_frequency6" value="0 MHz" />
-- Retrieval info: <generic name="gui_ps_units6" value="ps" />
-- Retrieval info: <generic name="gui_phase_shift6" value="0" />
-- Retrieval info: <generic name="gui_phase_shift_deg6" value="0.0" />
-- Retrieval info: <generic name="gui_actual_phase_shift6" value="0" />
-- Retrieval info: <generic name="gui_duty_cycle6" value="50" />
-- Retrieval info: <generic name="gui_cascade_counter7" value="false" />
-- Retrieval info: <generic name="gui_output_clock_frequency7" value="100.0" />
-- Retrieval info: <generic name="gui_divide_factor_c7" value="1" />
-- Retrieval info: <generic name="gui_actual_output_clock_frequency7" value="0 MHz" />
-- Retrieval info: <generic name="gui_ps_units7" value="ps" />
-- Retrieval info: <generic name="gui_phase_shift7" value="0" />
-- Retrieval info: <generic name="gui_phase_shift_deg7" value="0.0" />
-- Retrieval info: <generic name="gui_actual_phase_shift7" value="0" />
-- Retrieval info: <generic name="gui_duty_cycle7" value="50" />
-- Retrieval info: <generic name="gui_cascade_counter8" value="false" />
-- Retrieval info: <generic name="gui_output_clock_frequency8" value="100.0" />
-- Retrieval info: <generic name="gui_divide_factor_c8" value="1" />
-- Retrieval info: <generic name="gui_actual_output_clock_frequency8" value="0 MHz" />
-- Retrieval info: <generic name="gui_ps_units8" value="ps" />
-- Retrieval info: <generic name="gui_phase_shift8" value="0" />
-- Retrieval info: <generic name="gui_phase_shift_deg8" value="0.0" />
-- Retrieval info: <generic name="gui_actual_phase_shift8" value="0" />
-- Retrieval info: <generic name="gui_duty_cycle8" value="50" />
-- Retrieval info: <generic name="gui_cascade_counter9" value="false" />
-- Retrieval info: <generic name="gui_output_clock_frequency9" value="100.0" />
-- Retrieval info: <generic name="gui_divide_factor_c9" value="1" />
-- Retrieval info: <generic name="gui_actual_output_clock_frequency9" value="0 MHz" />
-- Retrieval info: <generic name="gui_ps_units9" value="ps" />
-- Retrieval info: <generic name="gui_phase_shift9" value="0" />
-- Retrieval info: <generic name="gui_phase_shift_deg9" value="0.0" />
-- Retrieval info: <generic name="gui_actual_phase_shift9" value="0" />
-- Retrieval info: <generic name="gui_duty_cycle9" value="50" />
-- Retrieval info: <generic name="gui_cascade_counter10" value="false" />
-- Retrieval info: <generic name="gui_output_clock_frequency10" value="100.0" />
-- Retrieval info: <generic name="gui_divide_factor_c10" value="1" />
-- Retrieval info: <generic name="gui_actual_output_clock_frequency10" value="0 MHz" />
-- Retrieval info: <generic name="gui_ps_units10" value="ps" />
-- Retrieval info: <generic name="gui_phase_shift10" value="0" />
-- Retrieval info: <generic name="gui_phase_shift_deg10" value="0.0" />
-- Retrieval info: <generic name="gui_actual_phase_shift10" value="0" />
-- Retrieval info: <generic name="gui_duty_cycle10" value="50" />
-- Retrieval info: <generic name="gui_cascade_counter11" value="false" />
-- Retrieval info: <generic name="gui_output_clock_frequency11" value="100.0" />
-- Retrieval info: <generic name="gui_divide_factor_c11" value="1" />
-- Retrieval info: <generic name="gui_actual_output_clock_frequency11" value="0 MHz" />
-- Retrieval info: <generic name="gui_ps_units11" value="ps" />
-- Retrieval info: <generic name="gui_phase_shift11" value="0" />
-- Retrieval info: <generic name="gui_phase_shift_deg11" value="0.0" />
-- Retrieval info: <generic name="gui_actual_phase_shift11" value="0" />
-- Retrieval info: <generic name="gui_duty_cycle11" value="50" />
-- Retrieval info: <generic name="gui_cascade_counter12" value="false" />
-- Retrieval info: <generic name="gui_output_clock_frequency12" value="100.0" />
-- Retrieval info: <generic name="gui_divide_factor_c12" value="1" />
-- Retrieval info: <generic name="gui_actual_output_clock_frequency12" value="0 MHz" />
-- Retrieval info: <generic name="gui_ps_units12" value="ps" />
-- Retrieval info: <generic name="gui_phase_shift12" value="0" />
-- Retrieval info: <generic name="gui_phase_shift_deg12" value="0.0" />
-- Retrieval info: <generic name="gui_actual_phase_shift12" value="0" />
-- Retrieval info: <generic name="gui_duty_cycle12" value="50" />
-- Retrieval info: <generic name="gui_cascade_counter13" value="false" />
-- Retrieval info: <generic name="gui_output_clock_frequency13" value="100.0" />
-- Retrieval info: <generic name="gui_divide_factor_c13" value="1" />
-- Retrieval info: <generic name="gui_actual_output_clock_frequency13" value="0 MHz" />
-- Retrieval info: <generic name="gui_ps_units13" value="ps" />
-- Retrieval info: <generic name="gui_phase_shift13" value="0" />
-- Retrieval info: <generic name="gui_phase_shift_deg13" value="0.0" />
-- Retrieval info: <generic name="gui_actual_phase_shift13" value="0" />
-- Retrieval info: <generic name="gui_duty_cycle13" value="50" />
-- Retrieval info: <generic name="gui_cascade_counter14" value="false" />
-- Retrieval info: <generic name="gui_output_clock_frequency14" value="100.0" />
-- Retrieval info: <generic name="gui_divide_factor_c14" value="1" />
-- Retrieval info: <generic name="gui_actual_output_clock_frequency14" value="0 MHz" />
-- Retrieval info: <generic name="gui_ps_units14" value="ps" />
-- Retrieval info: <generic name="gui_phase_shift14" value="0" />
-- Retrieval info: <generic name="gui_phase_shift_deg14" value="0.0" />
-- Retrieval info: <generic name="gui_actual_phase_shift14" value="0" />
-- Retrieval info: <generic name="gui_duty_cycle14" value="50" />
-- Retrieval info: <generic name="gui_cascade_counter15" value="false" />
-- Retrieval info: <generic name="gui_output_clock_frequency15" value="100.0" />
-- Retrieval info: <generic name="gui_divide_factor_c15" value="1" />
-- Retrieval info: <generic name="gui_actual_output_clock_frequency15" value="0 MHz" />
-- Retrieval info: <generic name="gui_ps_units15" value="ps" />
-- Retrieval info: <generic name="gui_phase_shift15" value="0" />
-- Retrieval info: <generic name="gui_phase_shift_deg15" value="0.0" />
-- Retrieval info: <generic name="gui_actual_phase_shift15" value="0" />
-- Retrieval info: <generic name="gui_duty_cycle15" value="50" />
-- Retrieval info: <generic name="gui_cascade_counter16" value="false" />
-- Retrieval info: <generic name="gui_output_clock_frequency16" value="100.0" />
-- Retrieval info: <generic name="gui_divide_factor_c16" value="1" />
-- Retrieval info: <generic name="gui_actual_output_clock_frequency16" value="0 MHz" />
-- Retrieval info: <generic name="gui_ps_units16" value="ps" />
-- Retrieval info: <generic name="gui_phase_shift16" value="0" />
-- Retrieval info: <generic name="gui_phase_shift_deg16" value="0.0" />
-- Retrieval info: <generic name="gui_actual_phase_shift16" value="0" />
-- Retrieval info: <generic name="gui_duty_cycle16" value="50" />
-- Retrieval info: <generic name="gui_cascade_counter17" value="false" />
-- Retrieval info: <generic name="gui_output_clock_frequency17" value="100.0" />
-- Retrieval info: <generic name="gui_divide_factor_c17" value="1" />
-- Retrieval info: <generic name="gui_actual_output_clock_frequency17" value="0 MHz" />
-- Retrieval info: <generic name="gui_ps_units17" value="ps" />
-- Retrieval info: <generic name="gui_phase_shift17" value="0" />
-- Retrieval info: <generic name="gui_phase_shift_deg17" value="0.0" />
-- Retrieval info: <generic name="gui_actual_phase_shift17" value="0" />
-- Retrieval info: <generic name="gui_duty_cycle17" value="50" />
-- Retrieval info: <generic name="gui_pll_auto_reset" value="Off" />
-- Retrieval info: <generic name="gui_pll_bandwidth_preset" value="Auto" />
-- Retrieval info: <generic name="gui_en_reconf" value="false" />
-- Retrieval info: <generic name="gui_en_dps_ports" value="false" />
-- Retrieval info: <generic name="gui_en_phout_ports" value="false" />
-- Retrieval info: <generic name="gui_phout_division" value="1" />
-- Retrieval info: <generic name="gui_mif_generate" value="false" />
-- Retrieval info: <generic name="gui_enable_mif_dps" value="false" />
-- Retrieval info: <generic name="gui_dps_cntr" value="C0" />
-- Retrieval info: <generic name="gui_dps_num" value="1" />
-- Retrieval info: <generic name="gui_dps_dir" value="Positive" />
-- Retrieval info: <generic name="gui_refclk_switch" value="false" />
-- Retrieval info: <generic name="gui_refclk1_frequency" value="100.0" />
-- Retrieval info: <generic name="gui_switchover_mode" value="Automatic Switchover" />
-- Retrieval info: <generic name="gui_switchover_delay" value="0" />
-- Retrieval info: <generic name="gui_active_clk" value="false" />
-- Retrieval info: <generic name="gui_clk_bad" value="false" />
-- Retrieval info: <generic name="gui_enable_cascade_out" value="false" />
-- Retrieval info: <generic name="gui_cascade_outclk_index" value="0" />
-- Retrieval info: <generic name="gui_enable_cascade_in" value="false" />
-- Retrieval info: <generic name="gui_pll_cascading_mode" value="Create an adjpllin signal to connect with an upstream PLL" />
-- Retrieval info: </instance>
-- IPFS_FILES : audio_pll.vho
-- RELATED_FILES: audio_pll.vhd, audio_pll_0002.v
| gpl-3.0 | 9e7ea60e59e7d68df52eb7c7d1d27251 | 0.673707 | 3.009949 | false | false | false | false |
varunnagpaal/Digital-Hardware-Modelling | xilinx-vivado/proj_pointer_basic_hls_ip_integ/proj_pointer_basic_hls_ip_integ.cache/ip/2018.2/5aea95b49c8de87e/design_1_rst_ps7_0_50M_0_sim_netlist.vhdl | 1 | 35,448 | -- Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2018.2 (win64) Build 2258646 Thu Jun 14 20:03:12 MDT 2018
-- Date : Mon Sep 16 04:56:41 2019
-- Host : varun-laptop running 64-bit Service Pack 1 (build 7601)
-- Command : write_vhdl -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
-- decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ design_1_rst_ps7_0_50M_0_sim_netlist.vhdl
-- Design : design_1_rst_ps7_0_50M_0
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7z010clg400-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_cdc_sync is
port (
lpf_asr_reg : out STD_LOGIC;
scndry_out : out STD_LOGIC;
lpf_asr : in STD_LOGIC;
p_1_in : in STD_LOGIC;
p_2_in : in STD_LOGIC;
asr_lpf : in STD_LOGIC_VECTOR ( 0 to 0 );
aux_reset_in : in STD_LOGIC;
slowest_sync_clk : in STD_LOGIC
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_cdc_sync;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_cdc_sync is
signal asr_d1 : STD_LOGIC;
signal s_level_out_d1_cdc_to : STD_LOGIC;
signal s_level_out_d2 : STD_LOGIC;
signal s_level_out_d3 : STD_LOGIC;
signal \^scndry_out\ : STD_LOGIC;
attribute ASYNC_REG : boolean;
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM : string;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "FDR";
attribute box_type : string;
attribute box_type of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\ : label is "PRIMITIVE";
begin
scndry_out <= \^scndry_out\;
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => asr_d1,
Q => s_level_out_d1_cdc_to,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to_i_1__0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => aux_reset_in,
O => asr_d1
);
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => s_level_out_d1_cdc_to,
Q => s_level_out_d2,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => s_level_out_d2,
Q => s_level_out_d3,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => s_level_out_d3,
Q => \^scndry_out\,
R => '0'
);
lpf_asr_i_1: unisim.vcomponents.LUT5
generic map(
INIT => X"EAAAAAA8"
)
port map (
I0 => lpf_asr,
I1 => p_1_in,
I2 => p_2_in,
I3 => \^scndry_out\,
I4 => asr_lpf(0),
O => lpf_asr_reg
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_cdc_sync_0 is
port (
lpf_exr_reg : out STD_LOGIC;
scndry_out : out STD_LOGIC;
lpf_exr : in STD_LOGIC;
p_3_out : in STD_LOGIC_VECTOR ( 2 downto 0 );
mb_debug_sys_rst : in STD_LOGIC;
ext_reset_in : in STD_LOGIC;
slowest_sync_clk : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_cdc_sync_0 : entity is "cdc_sync";
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_cdc_sync_0;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_cdc_sync_0 is
signal exr_d1 : STD_LOGIC;
signal s_level_out_d1_cdc_to : STD_LOGIC;
signal s_level_out_d2 : STD_LOGIC;
signal s_level_out_d3 : STD_LOGIC;
signal \^scndry_out\ : STD_LOGIC;
attribute ASYNC_REG : boolean;
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM : string;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "FDR";
attribute box_type : string;
attribute box_type of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\ : label is "PRIMITIVE";
begin
scndry_out <= \^scndry_out\;
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => exr_d1,
Q => s_level_out_d1_cdc_to,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"B"
)
port map (
I0 => mb_debug_sys_rst,
I1 => ext_reset_in,
O => exr_d1
);
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => s_level_out_d1_cdc_to,
Q => s_level_out_d2,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => s_level_out_d2,
Q => s_level_out_d3,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => s_level_out_d3,
Q => \^scndry_out\,
R => '0'
);
lpf_exr_i_1: unisim.vcomponents.LUT5
generic map(
INIT => X"EAAAAAA8"
)
port map (
I0 => lpf_exr,
I1 => p_3_out(1),
I2 => p_3_out(2),
I3 => \^scndry_out\,
I4 => p_3_out(0),
O => lpf_exr_reg
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_upcnt_n is
port (
Q : out STD_LOGIC_VECTOR ( 5 downto 0 );
seq_clr : in STD_LOGIC;
seq_cnt_en : in STD_LOGIC;
slowest_sync_clk : in STD_LOGIC
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_upcnt_n;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_upcnt_n is
signal \^q\ : STD_LOGIC_VECTOR ( 5 downto 0 );
signal clear : STD_LOGIC;
signal q_int0 : STD_LOGIC_VECTOR ( 5 downto 0 );
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \q_int[1]_i_1\ : label is "soft_lutpair1";
attribute SOFT_HLUTNM of \q_int[2]_i_1\ : label is "soft_lutpair1";
attribute SOFT_HLUTNM of \q_int[3]_i_1\ : label is "soft_lutpair0";
attribute SOFT_HLUTNM of \q_int[4]_i_1\ : label is "soft_lutpair0";
begin
Q(5 downto 0) <= \^q\(5 downto 0);
\q_int[0]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^q\(0),
O => q_int0(0)
);
\q_int[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \^q\(0),
I1 => \^q\(1),
O => q_int0(1)
);
\q_int[2]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"78"
)
port map (
I0 => \^q\(0),
I1 => \^q\(1),
I2 => \^q\(2),
O => q_int0(2)
);
\q_int[3]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"7F80"
)
port map (
I0 => \^q\(1),
I1 => \^q\(0),
I2 => \^q\(2),
I3 => \^q\(3),
O => q_int0(3)
);
\q_int[4]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"7FFF8000"
)
port map (
I0 => \^q\(2),
I1 => \^q\(0),
I2 => \^q\(1),
I3 => \^q\(3),
I4 => \^q\(4),
O => q_int0(4)
);
\q_int[5]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => seq_clr,
O => clear
);
\q_int[5]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"7FFFFFFF80000000"
)
port map (
I0 => \^q\(3),
I1 => \^q\(1),
I2 => \^q\(0),
I3 => \^q\(2),
I4 => \^q\(4),
I5 => \^q\(5),
O => q_int0(5)
);
\q_int_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => slowest_sync_clk,
CE => seq_cnt_en,
D => q_int0(0),
Q => \^q\(0),
R => clear
);
\q_int_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => slowest_sync_clk,
CE => seq_cnt_en,
D => q_int0(1),
Q => \^q\(1),
R => clear
);
\q_int_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => slowest_sync_clk,
CE => seq_cnt_en,
D => q_int0(2),
Q => \^q\(2),
R => clear
);
\q_int_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => slowest_sync_clk,
CE => seq_cnt_en,
D => q_int0(3),
Q => \^q\(3),
R => clear
);
\q_int_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => slowest_sync_clk,
CE => seq_cnt_en,
D => q_int0(4),
Q => \^q\(4),
R => clear
);
\q_int_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => slowest_sync_clk,
CE => seq_cnt_en,
D => q_int0(5),
Q => \^q\(5),
R => clear
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_lpf is
port (
lpf_int : out STD_LOGIC;
slowest_sync_clk : in STD_LOGIC;
dcm_locked : in STD_LOGIC;
mb_debug_sys_rst : in STD_LOGIC;
ext_reset_in : in STD_LOGIC;
aux_reset_in : in STD_LOGIC
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_lpf;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_lpf is
signal \ACTIVE_LOW_AUX.ACT_LO_AUX_n_0\ : STD_LOGIC;
signal \ACTIVE_LOW_EXT.ACT_LO_EXT_n_0\ : STD_LOGIC;
signal Q : STD_LOGIC;
signal asr_lpf : STD_LOGIC_VECTOR ( 0 to 0 );
signal lpf_asr : STD_LOGIC;
signal lpf_exr : STD_LOGIC;
signal \lpf_int0__0\ : STD_LOGIC;
signal p_1_in : STD_LOGIC;
signal p_2_in : STD_LOGIC;
signal p_3_in1_in : STD_LOGIC;
signal p_3_out : STD_LOGIC_VECTOR ( 3 downto 0 );
attribute XILINX_LEGACY_PRIM : string;
attribute XILINX_LEGACY_PRIM of POR_SRL_I : label is "SRL16";
attribute box_type : string;
attribute box_type of POR_SRL_I : label is "PRIMITIVE";
attribute srl_name : string;
attribute srl_name of POR_SRL_I : label is "U0/\EXT_LPF/POR_SRL_I ";
begin
\ACTIVE_LOW_AUX.ACT_LO_AUX\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_cdc_sync
port map (
asr_lpf(0) => asr_lpf(0),
aux_reset_in => aux_reset_in,
lpf_asr => lpf_asr,
lpf_asr_reg => \ACTIVE_LOW_AUX.ACT_LO_AUX_n_0\,
p_1_in => p_1_in,
p_2_in => p_2_in,
scndry_out => p_3_in1_in,
slowest_sync_clk => slowest_sync_clk
);
\ACTIVE_LOW_EXT.ACT_LO_EXT\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_cdc_sync_0
port map (
ext_reset_in => ext_reset_in,
lpf_exr => lpf_exr,
lpf_exr_reg => \ACTIVE_LOW_EXT.ACT_LO_EXT_n_0\,
mb_debug_sys_rst => mb_debug_sys_rst,
p_3_out(2 downto 0) => p_3_out(2 downto 0),
scndry_out => p_3_out(3),
slowest_sync_clk => slowest_sync_clk
);
\AUX_LPF[1].asr_lpf_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => p_3_in1_in,
Q => p_2_in,
R => '0'
);
\AUX_LPF[2].asr_lpf_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => p_2_in,
Q => p_1_in,
R => '0'
);
\AUX_LPF[3].asr_lpf_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => p_1_in,
Q => asr_lpf(0),
R => '0'
);
\EXT_LPF[1].exr_lpf_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => p_3_out(3),
Q => p_3_out(2),
R => '0'
);
\EXT_LPF[2].exr_lpf_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => p_3_out(2),
Q => p_3_out(1),
R => '0'
);
\EXT_LPF[3].exr_lpf_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => p_3_out(1),
Q => p_3_out(0),
R => '0'
);
POR_SRL_I: unisim.vcomponents.SRL16E
generic map(
INIT => X"FFFF"
)
port map (
A0 => '1',
A1 => '1',
A2 => '1',
A3 => '1',
CE => '1',
CLK => slowest_sync_clk,
D => '0',
Q => Q
);
lpf_asr_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => \ACTIVE_LOW_AUX.ACT_LO_AUX_n_0\,
Q => lpf_asr,
R => '0'
);
lpf_exr_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => \ACTIVE_LOW_EXT.ACT_LO_EXT_n_0\,
Q => lpf_exr,
R => '0'
);
lpf_int0: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFD"
)
port map (
I0 => dcm_locked,
I1 => lpf_exr,
I2 => lpf_asr,
I3 => Q,
O => \lpf_int0__0\
);
lpf_int_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => \lpf_int0__0\,
Q => lpf_int,
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_sequence_psr is
port (
MB_out : out STD_LOGIC;
Bsr_out : out STD_LOGIC;
Pr_out : out STD_LOGIC;
\ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N\ : out STD_LOGIC;
\ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N\ : out STD_LOGIC;
lpf_int : in STD_LOGIC;
slowest_sync_clk : in STD_LOGIC
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_sequence_psr;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_sequence_psr is
signal \^bsr_out\ : STD_LOGIC;
signal Core_i_1_n_0 : STD_LOGIC;
signal \^mb_out\ : STD_LOGIC;
signal \^pr_out\ : STD_LOGIC;
signal \bsr_dec_reg_n_0_[0]\ : STD_LOGIC;
signal \bsr_dec_reg_n_0_[2]\ : STD_LOGIC;
signal bsr_i_1_n_0 : STD_LOGIC;
signal \core_dec[0]_i_1_n_0\ : STD_LOGIC;
signal \core_dec[2]_i_1_n_0\ : STD_LOGIC;
signal \core_dec_reg_n_0_[0]\ : STD_LOGIC;
signal \core_dec_reg_n_0_[1]\ : STD_LOGIC;
signal from_sys_i_1_n_0 : STD_LOGIC;
signal p_0_in : STD_LOGIC;
signal p_3_out : STD_LOGIC_VECTOR ( 2 downto 0 );
signal p_5_out : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \pr_dec0__0\ : STD_LOGIC;
signal \pr_dec_reg_n_0_[0]\ : STD_LOGIC;
signal \pr_dec_reg_n_0_[2]\ : STD_LOGIC;
signal pr_i_1_n_0 : STD_LOGIC;
signal seq_clr : STD_LOGIC;
signal seq_cnt : STD_LOGIC_VECTOR ( 5 downto 0 );
signal seq_cnt_en : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N_i_1\ : label is "soft_lutpair5";
attribute SOFT_HLUTNM of \ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_i_1\ : label is "soft_lutpair4";
attribute SOFT_HLUTNM of Core_i_1 : label is "soft_lutpair3";
attribute SOFT_HLUTNM of \bsr_dec[2]_i_1\ : label is "soft_lutpair6";
attribute SOFT_HLUTNM of bsr_i_1 : label is "soft_lutpair5";
attribute SOFT_HLUTNM of \core_dec[0]_i_1\ : label is "soft_lutpair2";
attribute SOFT_HLUTNM of \core_dec[2]_i_1\ : label is "soft_lutpair6";
attribute SOFT_HLUTNM of from_sys_i_1 : label is "soft_lutpair3";
attribute SOFT_HLUTNM of \pr_dec[0]_i_1\ : label is "soft_lutpair2";
attribute SOFT_HLUTNM of pr_i_1 : label is "soft_lutpair4";
begin
Bsr_out <= \^bsr_out\;
MB_out <= \^mb_out\;
Pr_out <= \^pr_out\;
\ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^bsr_out\,
O => \ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N\
);
\ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^pr_out\,
O => \ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N\
);
Core_i_1: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \^mb_out\,
I1 => p_0_in,
O => Core_i_1_n_0
);
Core_reg: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => Core_i_1_n_0,
Q => \^mb_out\,
S => lpf_int
);
SEQ_COUNTER: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_upcnt_n
port map (
Q(5 downto 0) => seq_cnt(5 downto 0),
seq_clr => seq_clr,
seq_cnt_en => seq_cnt_en,
slowest_sync_clk => slowest_sync_clk
);
\bsr_dec[0]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"0090"
)
port map (
I0 => seq_cnt_en,
I1 => seq_cnt(4),
I2 => seq_cnt(3),
I3 => seq_cnt(5),
O => p_5_out(0)
);
\bsr_dec[2]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \core_dec_reg_n_0_[1]\,
I1 => \bsr_dec_reg_n_0_[0]\,
O => p_5_out(2)
);
\bsr_dec_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => p_5_out(0),
Q => \bsr_dec_reg_n_0_[0]\,
R => '0'
);
\bsr_dec_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => p_5_out(2),
Q => \bsr_dec_reg_n_0_[2]\,
R => '0'
);
bsr_i_1: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \^bsr_out\,
I1 => \bsr_dec_reg_n_0_[2]\,
O => bsr_i_1_n_0
);
bsr_reg: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => bsr_i_1_n_0,
Q => \^bsr_out\,
S => lpf_int
);
\core_dec[0]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"9000"
)
port map (
I0 => seq_cnt_en,
I1 => seq_cnt(4),
I2 => seq_cnt(3),
I3 => seq_cnt(5),
O => \core_dec[0]_i_1_n_0\
);
\core_dec[2]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \core_dec_reg_n_0_[1]\,
I1 => \core_dec_reg_n_0_[0]\,
O => \core_dec[2]_i_1_n_0\
);
\core_dec_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => \core_dec[0]_i_1_n_0\,
Q => \core_dec_reg_n_0_[0]\,
R => '0'
);
\core_dec_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => \pr_dec0__0\,
Q => \core_dec_reg_n_0_[1]\,
R => '0'
);
\core_dec_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => \core_dec[2]_i_1_n_0\,
Q => p_0_in,
R => '0'
);
from_sys_i_1: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \^mb_out\,
I1 => seq_cnt_en,
O => from_sys_i_1_n_0
);
from_sys_reg: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => from_sys_i_1_n_0,
Q => seq_cnt_en,
S => lpf_int
);
pr_dec0: unisim.vcomponents.LUT4
generic map(
INIT => X"0018"
)
port map (
I0 => seq_cnt_en,
I1 => seq_cnt(0),
I2 => seq_cnt(2),
I3 => seq_cnt(1),
O => \pr_dec0__0\
);
\pr_dec[0]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"0480"
)
port map (
I0 => seq_cnt_en,
I1 => seq_cnt(3),
I2 => seq_cnt(5),
I3 => seq_cnt(4),
O => p_3_out(0)
);
\pr_dec[2]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \core_dec_reg_n_0_[1]\,
I1 => \pr_dec_reg_n_0_[0]\,
O => p_3_out(2)
);
\pr_dec_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => p_3_out(0),
Q => \pr_dec_reg_n_0_[0]\,
R => '0'
);
\pr_dec_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => p_3_out(2),
Q => \pr_dec_reg_n_0_[2]\,
R => '0'
);
pr_i_1: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \^pr_out\,
I1 => \pr_dec_reg_n_0_[2]\,
O => pr_i_1_n_0
);
pr_reg: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => pr_i_1_n_0,
Q => \^pr_out\,
S => lpf_int
);
seq_clr_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => '1',
Q => seq_clr,
R => lpf_int
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_proc_sys_reset is
port (
slowest_sync_clk : in STD_LOGIC;
ext_reset_in : in STD_LOGIC;
aux_reset_in : in STD_LOGIC;
mb_debug_sys_rst : in STD_LOGIC;
dcm_locked : in STD_LOGIC;
mb_reset : out STD_LOGIC;
bus_struct_reset : out STD_LOGIC_VECTOR ( 0 to 0 );
peripheral_reset : out STD_LOGIC_VECTOR ( 0 to 0 );
interconnect_aresetn : out STD_LOGIC_VECTOR ( 0 to 0 );
peripheral_aresetn : out STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute C_AUX_RESET_HIGH : string;
attribute C_AUX_RESET_HIGH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_proc_sys_reset : entity is "1'b0";
attribute C_AUX_RST_WIDTH : integer;
attribute C_AUX_RST_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_proc_sys_reset : entity is 4;
attribute C_EXT_RESET_HIGH : string;
attribute C_EXT_RESET_HIGH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_proc_sys_reset : entity is "1'b0";
attribute C_EXT_RST_WIDTH : integer;
attribute C_EXT_RST_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_proc_sys_reset : entity is 4;
attribute C_FAMILY : string;
attribute C_FAMILY of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_proc_sys_reset : entity is "zynq";
attribute C_NUM_BUS_RST : integer;
attribute C_NUM_BUS_RST of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_proc_sys_reset : entity is 1;
attribute C_NUM_INTERCONNECT_ARESETN : integer;
attribute C_NUM_INTERCONNECT_ARESETN of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_proc_sys_reset : entity is 1;
attribute C_NUM_PERP_ARESETN : integer;
attribute C_NUM_PERP_ARESETN of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_proc_sys_reset : entity is 1;
attribute C_NUM_PERP_RST : integer;
attribute C_NUM_PERP_RST of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_proc_sys_reset : entity is 1;
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_proc_sys_reset;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_proc_sys_reset is
signal Bsr_out : STD_LOGIC;
signal MB_out : STD_LOGIC;
signal Pr_out : STD_LOGIC;
signal SEQ_n_3 : STD_LOGIC;
signal SEQ_n_4 : STD_LOGIC;
signal lpf_int : STD_LOGIC;
attribute box_type : string;
attribute box_type of \ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N\ : label is "PRIMITIVE";
attribute box_type of \ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N\ : label is "PRIMITIVE";
attribute box_type of \BSR_OUT_DFF[0].FDRE_BSR\ : label is "PRIMITIVE";
attribute box_type of FDRE_inst : label is "PRIMITIVE";
attribute box_type of \PR_OUT_DFF[0].FDRE_PER\ : label is "PRIMITIVE";
attribute equivalent_register_removal : string;
attribute equivalent_register_removal of bus_struct_reset : signal is "no";
attribute equivalent_register_removal of interconnect_aresetn : signal is "no";
attribute equivalent_register_removal of peripheral_aresetn : signal is "no";
attribute equivalent_register_removal of peripheral_reset : signal is "no";
begin
\ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => SEQ_n_3,
Q => interconnect_aresetn(0),
R => '0'
);
\ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => SEQ_n_4,
Q => peripheral_aresetn(0),
R => '0'
);
\BSR_OUT_DFF[0].FDRE_BSR\: unisim.vcomponents.FDRE
generic map(
INIT => '1',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => Bsr_out,
Q => bus_struct_reset(0),
R => '0'
);
EXT_LPF: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_lpf
port map (
aux_reset_in => aux_reset_in,
dcm_locked => dcm_locked,
ext_reset_in => ext_reset_in,
lpf_int => lpf_int,
mb_debug_sys_rst => mb_debug_sys_rst,
slowest_sync_clk => slowest_sync_clk
);
FDRE_inst: unisim.vcomponents.FDRE
generic map(
INIT => '1',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => MB_out,
Q => mb_reset,
R => '0'
);
\PR_OUT_DFF[0].FDRE_PER\: unisim.vcomponents.FDRE
generic map(
INIT => '1',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => Pr_out,
Q => peripheral_reset(0),
R => '0'
);
SEQ: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_sequence_psr
port map (
\ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N\ => SEQ_n_3,
\ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N\ => SEQ_n_4,
Bsr_out => Bsr_out,
MB_out => MB_out,
Pr_out => Pr_out,
lpf_int => lpf_int,
slowest_sync_clk => slowest_sync_clk
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
port (
slowest_sync_clk : in STD_LOGIC;
ext_reset_in : in STD_LOGIC;
aux_reset_in : in STD_LOGIC;
mb_debug_sys_rst : in STD_LOGIC;
dcm_locked : in STD_LOGIC;
mb_reset : out STD_LOGIC;
bus_struct_reset : out STD_LOGIC_VECTOR ( 0 to 0 );
peripheral_reset : out STD_LOGIC_VECTOR ( 0 to 0 );
interconnect_aresetn : out STD_LOGIC_VECTOR ( 0 to 0 );
peripheral_aresetn : out STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is true;
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "design_1_rst_ps7_0_50M_0,proc_sys_reset,{}";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "yes";
attribute x_core_info : string;
attribute x_core_info of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "proc_sys_reset,Vivado 2018.2";
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
attribute C_AUX_RESET_HIGH : string;
attribute C_AUX_RESET_HIGH of U0 : label is "1'b0";
attribute C_AUX_RST_WIDTH : integer;
attribute C_AUX_RST_WIDTH of U0 : label is 4;
attribute C_EXT_RESET_HIGH : string;
attribute C_EXT_RESET_HIGH of U0 : label is "1'b0";
attribute C_EXT_RST_WIDTH : integer;
attribute C_EXT_RST_WIDTH of U0 : label is 4;
attribute C_FAMILY : string;
attribute C_FAMILY of U0 : label is "zynq";
attribute C_NUM_BUS_RST : integer;
attribute C_NUM_BUS_RST of U0 : label is 1;
attribute C_NUM_INTERCONNECT_ARESETN : integer;
attribute C_NUM_INTERCONNECT_ARESETN of U0 : label is 1;
attribute C_NUM_PERP_ARESETN : integer;
attribute C_NUM_PERP_ARESETN of U0 : label is 1;
attribute C_NUM_PERP_RST : integer;
attribute C_NUM_PERP_RST of U0 : label is 1;
attribute x_interface_info : string;
attribute x_interface_info of aux_reset_in : signal is "xilinx.com:signal:reset:1.0 aux_reset RST";
attribute x_interface_parameter : string;
attribute x_interface_parameter of aux_reset_in : signal is "XIL_INTERFACENAME aux_reset, POLARITY ACTIVE_LOW";
attribute x_interface_info of ext_reset_in : signal is "xilinx.com:signal:reset:1.0 ext_reset RST";
attribute x_interface_parameter of ext_reset_in : signal is "XIL_INTERFACENAME ext_reset, BOARD.ASSOCIATED_PARAM RESET_BOARD_INTERFACE, POLARITY ACTIVE_LOW";
attribute x_interface_info of mb_debug_sys_rst : signal is "xilinx.com:signal:reset:1.0 dbg_reset RST";
attribute x_interface_parameter of mb_debug_sys_rst : signal is "XIL_INTERFACENAME dbg_reset, POLARITY ACTIVE_HIGH";
attribute x_interface_info of mb_reset : signal is "xilinx.com:signal:reset:1.0 mb_rst RST";
attribute x_interface_parameter of mb_reset : signal is "XIL_INTERFACENAME mb_rst, POLARITY ACTIVE_HIGH, TYPE PROCESSOR";
attribute x_interface_info of slowest_sync_clk : signal is "xilinx.com:signal:clock:1.0 clock CLK";
attribute x_interface_parameter of slowest_sync_clk : signal is "XIL_INTERFACENAME clock, ASSOCIATED_RESET mb_reset:bus_struct_reset:interconnect_aresetn:peripheral_aresetn:peripheral_reset, FREQ_HZ 50000000, PHASE 0.000, CLK_DOMAIN design_1_processing_system7_0_0_FCLK_CLK0";
attribute x_interface_info of bus_struct_reset : signal is "xilinx.com:signal:reset:1.0 bus_struct_reset RST";
attribute x_interface_parameter of bus_struct_reset : signal is "XIL_INTERFACENAME bus_struct_reset, POLARITY ACTIVE_HIGH, TYPE INTERCONNECT";
attribute x_interface_info of interconnect_aresetn : signal is "xilinx.com:signal:reset:1.0 interconnect_low_rst RST";
attribute x_interface_parameter of interconnect_aresetn : signal is "XIL_INTERFACENAME interconnect_low_rst, POLARITY ACTIVE_LOW, TYPE INTERCONNECT";
attribute x_interface_info of peripheral_aresetn : signal is "xilinx.com:signal:reset:1.0 peripheral_low_rst RST";
attribute x_interface_parameter of peripheral_aresetn : signal is "XIL_INTERFACENAME peripheral_low_rst, POLARITY ACTIVE_LOW, TYPE PERIPHERAL";
attribute x_interface_info of peripheral_reset : signal is "xilinx.com:signal:reset:1.0 peripheral_high_rst RST";
attribute x_interface_parameter of peripheral_reset : signal is "XIL_INTERFACENAME peripheral_high_rst, POLARITY ACTIVE_HIGH, TYPE PERIPHERAL";
begin
U0: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_proc_sys_reset
port map (
aux_reset_in => aux_reset_in,
bus_struct_reset(0) => bus_struct_reset(0),
dcm_locked => dcm_locked,
ext_reset_in => ext_reset_in,
interconnect_aresetn(0) => interconnect_aresetn(0),
mb_debug_sys_rst => mb_debug_sys_rst,
mb_reset => mb_reset,
peripheral_aresetn(0) => peripheral_aresetn(0),
peripheral_reset(0) => peripheral_reset(0),
slowest_sync_clk => slowest_sync_clk
);
end STRUCTURE;
| mit | 49c2dd4c7b5d2ff811a9c53171611d6d | 0.588637 | 2.918492 | false | false | false | false |
MartinCura/SistDig-TP4 | old/fix_floating_point_files/fixed_pkg_c.vhdl | 1 | 301,463 | -- --------------------------------------------------------------------
-- "fixed_pkg_c.vhdl" package contains functions for fixed point math.
-- Please see the documentation for the fixed point package.
-- This package should be compiled into "ieee_proposed" and used as follows:
-- use ieee.std_logic_1164.all;
-- use ieee.numeric_std.all;
-- use ieee_proposed.fixed_float_types.all;
-- use ieee_proposed.fixed_pkg.all;
--
-- This verison is designed to work with the VHDL-93 compilers
-- synthesis tools. Please note the "%%%" comments. These are where we
-- diverge from the VHDL-200X LRM.
-- --------------------------------------------------------------------
-- Version : $Revision: 1.22 $
-- Date : $Date: 2010/09/22 18:34:14 $
-- --------------------------------------------------------------------
use STD.TEXTIO.all;
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
--library ieee_proposed;
--use ieee_proposed.fixed_float_types.all;
library floatfixlib;
use floatfixlib.fixed_float_types.all;
---library work;
---use work.fixed_float_types.all;
package fixed_pkg is
-- generic (
-- Rounding routine to use in fixed point, fixed_round or fixed_truncate
constant fixed_round_style : fixed_round_style_type := fixed_round;
-- Overflow routine to use in fixed point, fixed_saturate or fixed_wrap
constant fixed_overflow_style : fixed_overflow_style_type := fixed_saturate;
-- Extra bits used in divide routines
constant fixed_guard_bits : NATURAL := 3;
-- If TRUE, then turn off warnings on "X" propagation
constant no_warning : BOOLEAN := (false
);
-- Author David Bishop ([email protected])
-- base Unsigned fixed point type, downto direction assumed
type UNRESOLVED_ufixed is array (INTEGER range <>) of STD_ULOGIC;
-- base Signed fixed point type, downto direction assumed
type UNRESOLVED_sfixed is array (INTEGER range <>) of STD_ULOGIC;
subtype U_ufixed is UNRESOLVED_ufixed;
subtype U_sfixed is UNRESOLVED_sfixed;
subtype ufixed is UNRESOLVED_ufixed;
subtype sfixed is UNRESOLVED_sfixed;
--===========================================================================
-- Arithmetic Operators:
--===========================================================================
-- Absolute value, 2's complement
-- abs sfixed(a downto b) = sfixed(a+1 downto b)
function "abs" (arg : UNRESOLVED_sfixed) return UNRESOLVED_sfixed;
-- Negation, 2's complement
-- - sfixed(a downto b) = sfixed(a+1 downto b)
function "-" (arg : UNRESOLVED_sfixed)return UNRESOLVED_sfixed;
-- Addition
-- ufixed(a downto b) + ufixed(c downto d)
-- = ufixed(maximum(a,c)+1 downto minimum(b,d))
function "+" (l, r : UNRESOLVED_ufixed) return UNRESOLVED_ufixed;
-- sfixed(a downto b) + sfixed(c downto d)
-- = sfixed(maximum(a,c)+1 downto minimum(b,d))
function "+" (l, r : UNRESOLVED_sfixed) return UNRESOLVED_sfixed;
-- Subtraction
-- ufixed(a downto b) - ufixed(c downto d)
-- = ufixed(maximum(a,c)+1 downto minimum(b,d))
function "-" (l, r : UNRESOLVED_ufixed) return UNRESOLVED_ufixed;
-- sfixed(a downto b) - sfixed(c downto d)
-- = sfixed(maximum(a,c)+1 downto minimum(b,d))
function "-" (l, r : UNRESOLVED_sfixed) return UNRESOLVED_sfixed;
-- Multiplication
-- ufixed(a downto b) * ufixed(c downto d) = ufixed(a+c+1 downto b+d)
function "*" (l, r : UNRESOLVED_ufixed) return UNRESOLVED_ufixed;
-- sfixed(a downto b) * sfixed(c downto d) = sfixed(a+c+1 downto b+d)
function "*" (l, r : UNRESOLVED_sfixed) return UNRESOLVED_sfixed;
-- Division
-- ufixed(a downto b) / ufixed(c downto d) = ufixed(a-d downto b-c-1)
function "/" (l, r : UNRESOLVED_ufixed) return UNRESOLVED_ufixed;
-- sfixed(a downto b) / sfixed(c downto d) = sfixed(a-d+1 downto b-c)
function "/" (l, r : UNRESOLVED_sfixed) return UNRESOLVED_sfixed;
-- Remainder
-- ufixed (a downto b) rem ufixed (c downto d)
-- = ufixed (minimum(a,c) downto minimum(b,d))
function "rem" (l, r : UNRESOLVED_ufixed) return UNRESOLVED_ufixed;
-- sfixed (a downto b) rem sfixed (c downto d)
-- = sfixed (minimum(a,c) downto minimum(b,d))
function "rem" (l, r : UNRESOLVED_sfixed) return UNRESOLVED_sfixed;
-- Modulo
-- ufixed (a downto b) mod ufixed (c downto d)
-- = ufixed (minimum(a,c) downto minimum(b, d))
function "mod" (l, r : UNRESOLVED_ufixed) return UNRESOLVED_ufixed;
-- sfixed (a downto b) mod sfixed (c downto d)
-- = sfixed (c downto minimum(b, d))
function "mod" (l, r : UNRESOLVED_sfixed) return UNRESOLVED_sfixed;
----------------------------------------------------------------------------
-- In these routines the "real" or "natural" (integer)
-- are converted into a fixed point number and then the operation is
-- performed. It is assumed that the array will be large enough.
-- If the input is "real" then the real number is converted into a fixed of
-- the same size as the fixed point input. If the number is an "integer"
-- then it is converted into fixed with the range (l'high downto 0).
----------------------------------------------------------------------------
-- ufixed(a downto b) + ufixed(a downto b) = ufixed(a+1 downto b)
function "+" (l : UNRESOLVED_ufixed; r : REAL) return UNRESOLVED_ufixed;
-- ufixed(c downto d) + ufixed(c downto d) = ufixed(c+1 downto d)
function "+" (l : REAL; r : UNRESOLVED_ufixed) return UNRESOLVED_ufixed;
-- ufixed(a downto b) + ufixed(a downto 0) = ufixed(a+1 downto minimum(0,b))
function "+" (l : UNRESOLVED_ufixed; r : NATURAL) return UNRESOLVED_ufixed;
-- ufixed(a downto 0) + ufixed(c downto d) = ufixed(c+1 downto minimum(0,d))
function "+" (l : NATURAL; r : UNRESOLVED_ufixed) return UNRESOLVED_ufixed;
-- ufixed(a downto b) - ufixed(a downto b) = ufixed(a+1 downto b)
function "-" (l : UNRESOLVED_ufixed; r : REAL) return UNRESOLVED_ufixed;
-- ufixed(c downto d) - ufixed(c downto d) = ufixed(c+1 downto d)
function "-" (l : REAL; r : UNRESOLVED_ufixed) return UNRESOLVED_ufixed;
-- ufixed(a downto b) - ufixed(a downto 0) = ufixed(a+1 downto minimum(0,b))
function "-" (l : UNRESOLVED_ufixed; r : NATURAL) return UNRESOLVED_ufixed;
-- ufixed(a downto 0) + ufixed(c downto d) = ufixed(c+1 downto minimum(0,d))
function "-" (l : NATURAL; r : UNRESOLVED_ufixed) return UNRESOLVED_ufixed;
-- ufixed(a downto b) * ufixed(a downto b) = ufixed(2a+1 downto 2b)
function "*" (l : UNRESOLVED_ufixed; r : REAL) return UNRESOLVED_ufixed;
-- ufixed(c downto d) * ufixed(c downto d) = ufixed(2c+1 downto 2d)
function "*" (l : REAL; r : UNRESOLVED_ufixed) return UNRESOLVED_ufixed;
-- ufixed (a downto b) * ufixed (a downto 0) = ufixed (2a+1 downto b)
function "*" (l : UNRESOLVED_ufixed; r : NATURAL) return UNRESOLVED_ufixed;
-- ufixed (a downto b) * ufixed (a downto 0) = ufixed (2a+1 downto b)
function "*" (l : NATURAL; r : UNRESOLVED_ufixed) return UNRESOLVED_ufixed;
-- ufixed(a downto b) / ufixed(a downto b) = ufixed(a-b downto b-a-1)
function "/" (l : UNRESOLVED_ufixed; r : REAL) return UNRESOLVED_ufixed;
-- ufixed(a downto b) / ufixed(a downto b) = ufixed(a-b downto b-a-1)
function "/" (l : REAL; r : UNRESOLVED_ufixed) return UNRESOLVED_ufixed;
-- ufixed(a downto b) / ufixed(a downto 0) = ufixed(a downto b-a-1)
function "/" (l : UNRESOLVED_ufixed; r : NATURAL) return UNRESOLVED_ufixed;
-- ufixed(c downto 0) / ufixed(c downto d) = ufixed(c-d downto -c-1)
function "/" (l : NATURAL; r : UNRESOLVED_ufixed) return UNRESOLVED_ufixed;
-- ufixed (a downto b) rem ufixed (a downto b) = ufixed (a downto b)
function "rem" (l : UNRESOLVED_ufixed; r : REAL) return UNRESOLVED_ufixed;
-- ufixed (c downto d) rem ufixed (c downto d) = ufixed (c downto d)
function "rem" (l : REAL; r : UNRESOLVED_ufixed) return UNRESOLVED_ufixed;
-- ufixed (a downto b) rem ufixed (a downto 0) = ufixed (a downto minimum(b,0))
function "rem" (l : UNRESOLVED_ufixed; r : NATURAL) return UNRESOLVED_ufixed;
-- ufixed (c downto 0) rem ufixed (c downto d) = ufixed (c downto minimum(d,0))
function "rem" (l : NATURAL; r : UNRESOLVED_ufixed) return UNRESOLVED_ufixed;
-- ufixed (a downto b) mod ufixed (a downto b) = ufixed (a downto b)
function "mod" (l : UNRESOLVED_ufixed; r : REAL) return UNRESOLVED_ufixed;
-- ufixed (c downto d) mod ufixed (c downto d) = ufixed (c downto d)
function "mod" (l : REAL; r : UNRESOLVED_ufixed) return UNRESOLVED_ufixed;
-- ufixed (a downto b) mod ufixed (a downto 0) = ufixed (a downto minimum(b,0))
function "mod" (l : UNRESOLVED_ufixed; r : NATURAL) return UNRESOLVED_ufixed;
-- ufixed (c downto 0) mod ufixed (c downto d) = ufixed (c downto minimum(d,0))
function "mod" (l : NATURAL; r : UNRESOLVED_ufixed) return UNRESOLVED_ufixed;
-- sfixed(a downto b) + sfixed(a downto b) = sfixed(a+1 downto b)
function "+" (l : UNRESOLVED_sfixed; r : REAL) return UNRESOLVED_sfixed;
-- sfixed(c downto d) + sfixed(c downto d) = sfixed(c+1 downto d)
function "+" (l : REAL; r : UNRESOLVED_sfixed) return UNRESOLVED_sfixed;
-- sfixed(a downto b) + sfixed(a downto 0) = sfixed(a+1 downto minimum(0,b))
function "+" (l : UNRESOLVED_sfixed; r : INTEGER) return UNRESOLVED_sfixed;
-- sfixed(c downto 0) + sfixed(c downto d) = sfixed(c+1 downto minimum(0,d))
function "+" (l : INTEGER; r : UNRESOLVED_sfixed) return UNRESOLVED_sfixed;
-- sfixed(a downto b) - sfixed(a downto b) = sfixed(a+1 downto b)
function "-" (l : UNRESOLVED_sfixed; r : REAL) return UNRESOLVED_sfixed;
-- sfixed(c downto d) - sfixed(c downto d) = sfixed(c+1 downto d)
function "-" (l : REAL; r : UNRESOLVED_sfixed) return UNRESOLVED_sfixed;
-- sfixed(a downto b) - sfixed(a downto 0) = sfixed(a+1 downto minimum(0,b))
function "-" (l : UNRESOLVED_sfixed; r : INTEGER) return UNRESOLVED_sfixed;
-- sfixed(c downto 0) - sfixed(c downto d) = sfixed(c+1 downto minimum(0,d))
function "-" (l : INTEGER; r : UNRESOLVED_sfixed) return UNRESOLVED_sfixed;
-- sfixed(a downto b) * sfixed(a downto b) = sfixed(2a+1 downto 2b)
function "*" (l : UNRESOLVED_sfixed; r : REAL) return UNRESOLVED_sfixed;
-- sfixed(c downto d) * sfixed(c downto d) = sfixed(2c+1 downto 2d)
function "*" (l : REAL; r : UNRESOLVED_sfixed) return UNRESOLVED_sfixed;
-- sfixed(a downto b) * sfixed(a downto 0) = sfixed(2a+1 downto b)
function "*" (l : UNRESOLVED_sfixed; r : INTEGER) return UNRESOLVED_sfixed;
-- sfixed(c downto 0) * sfixed(c downto d) = sfixed(2c+1 downto d)
function "*" (l : INTEGER; r : UNRESOLVED_sfixed) return UNRESOLVED_sfixed;
-- sfixed(a downto b) / sfixed(a downto b) = sfixed(a-b+1 downto b-a)
function "/" (l : UNRESOLVED_sfixed; r : REAL) return UNRESOLVED_sfixed;
-- sfixed(c downto d) / sfixed(c downto d) = sfixed(c-d+1 downto d-c)
function "/" (l : REAL; r : UNRESOLVED_sfixed) return UNRESOLVED_sfixed;
-- sfixed(a downto b) / sfixed(a downto 0) = sfixed(a+1 downto b-a)
function "/" (l : UNRESOLVED_sfixed; r : INTEGER) return UNRESOLVED_sfixed;
-- sfixed(c downto 0) / sfixed(c downto d) = sfixed(c-d+1 downto -c)
function "/" (l : INTEGER; r : UNRESOLVED_sfixed) return UNRESOLVED_sfixed;
-- sfixed (a downto b) rem sfixed (a downto b) = sfixed (a downto b)
function "rem" (l : UNRESOLVED_sfixed; r : REAL) return UNRESOLVED_sfixed;
-- sfixed (c downto d) rem sfixed (c downto d) = sfixed (c downto d)
function "rem" (l : REAL; r : UNRESOLVED_sfixed) return UNRESOLVED_sfixed;
-- sfixed (a downto b) rem sfixed (a downto 0) = sfixed (a downto minimum(b,0))
function "rem" (l : UNRESOLVED_sfixed; r : INTEGER) return UNRESOLVED_sfixed;
-- sfixed (c downto 0) rem sfixed (c downto d) = sfixed (c downto minimum(d,0))
function "rem" (l : INTEGER; r : UNRESOLVED_sfixed) return UNRESOLVED_sfixed;
-- sfixed (a downto b) mod sfixed (a downto b) = sfixed (a downto b)
function "mod" (l : UNRESOLVED_sfixed; r : REAL) return UNRESOLVED_sfixed;
-- sfixed (c downto d) mod sfixed (c downto d) = sfixed (c downto d)
function "mod" (l : REAL; r : UNRESOLVED_sfixed) return UNRESOLVED_sfixed;
-- sfixed (a downto b) mod sfixed (a downto 0) = sfixed (a downto minimum(b,0))
function "mod" (l : UNRESOLVED_sfixed; r : INTEGER) return UNRESOLVED_sfixed;
-- sfixed (c downto 0) mod sfixed (c downto d) = sfixed (c downto minimum(d,0))
function "mod" (l : INTEGER; r : UNRESOLVED_sfixed) return UNRESOLVED_sfixed;
-- This version of divide gives the user more control
-- ufixed(a downto b) / ufixed(c downto d) = ufixed(a-d downto b-c-1)
function divide (
l, r : UNRESOLVED_ufixed;
constant round_style : fixed_round_style_type := fixed_round_style;
constant guard_bits : NATURAL := fixed_guard_bits)
return UNRESOLVED_ufixed;
-- This version of divide gives the user more control
-- sfixed(a downto b) / sfixed(c downto d) = sfixed(a-d+1 downto b-c)
function divide (
l, r : UNRESOLVED_sfixed;
constant round_style : fixed_round_style_type := fixed_round_style;
constant guard_bits : NATURAL := fixed_guard_bits)
return UNRESOLVED_sfixed;
-- These functions return 1/X
-- 1 / ufixed(a downto b) = ufixed(-b downto -a-1)
function reciprocal (
arg : UNRESOLVED_ufixed; -- fixed point input
constant round_style : fixed_round_style_type := fixed_round_style;
constant guard_bits : NATURAL := fixed_guard_bits)
return UNRESOLVED_ufixed;
-- 1 / sfixed(a downto b) = sfixed(-b+1 downto -a)
function reciprocal (
arg : UNRESOLVED_sfixed; -- fixed point input
constant round_style : fixed_round_style_type := fixed_round_style;
constant guard_bits : NATURAL := fixed_guard_bits)
return UNRESOLVED_sfixed;
-- REM function
-- ufixed (a downto b) rem ufixed (c downto d)
-- = ufixed (minimum(a,c) downto minimum(b,d))
function remainder (
l, r : UNRESOLVED_ufixed;
constant round_style : fixed_round_style_type := fixed_round_style;
constant guard_bits : NATURAL := fixed_guard_bits)
return UNRESOLVED_ufixed;
-- sfixed (a downto b) rem sfixed (c downto d)
-- = sfixed (minimum(a,c) downto minimum(b,d))
function remainder (
l, r : UNRESOLVED_sfixed;
constant round_style : fixed_round_style_type := fixed_round_style;
constant guard_bits : NATURAL := fixed_guard_bits)
return UNRESOLVED_sfixed;
-- mod function
-- ufixed (a downto b) mod ufixed (c downto d)
-- = ufixed (minimum(a,c) downto minimum(b, d))
function modulo (
l, r : UNRESOLVED_ufixed;
constant round_style : fixed_round_style_type := fixed_round_style;
constant guard_bits : NATURAL := fixed_guard_bits)
return UNRESOLVED_ufixed;
-- sfixed (a downto b) mod sfixed (c downto d)
-- = sfixed (c downto minimum(b, d))
function modulo (
l, r : UNRESOLVED_sfixed;
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;
constant round_style : fixed_round_style_type := fixed_round_style;
constant guard_bits : NATURAL := fixed_guard_bits)
return UNRESOLVED_sfixed;
-- Procedure for those who need an "accumulator" function.
-- add_carry (ufixed(a downto b), ufixed (c downto d))
-- = ufixed (maximum(a,c) downto minimum(b,d))
procedure add_carry (
L, R : in UNRESOLVED_ufixed;
c_in : in STD_ULOGIC;
result : out UNRESOLVED_ufixed;
c_out : out STD_ULOGIC);
-- add_carry (sfixed(a downto b), sfixed (c downto d))
-- = sfixed (maximum(a,c) downto minimum(b,d))
procedure add_carry (
L, R : in UNRESOLVED_sfixed;
c_in : in STD_ULOGIC;
result : out UNRESOLVED_sfixed;
c_out : out STD_ULOGIC);
-- Scales the result by a power of 2. Width of input = width of output with
-- the binary point moved.
function scalb (y : UNRESOLVED_ufixed; N : INTEGER) return UNRESOLVED_ufixed;
function scalb (y : UNRESOLVED_ufixed; N : SIGNED) return UNRESOLVED_ufixed;
function scalb (y : UNRESOLVED_sfixed; N : INTEGER) return UNRESOLVED_sfixed;
function scalb (y : UNRESOLVED_sfixed; N : SIGNED) return UNRESOLVED_sfixed;
function Is_Negative (arg : UNRESOLVED_sfixed) return BOOLEAN;
--===========================================================================
-- Comparison Operators
--===========================================================================
function ">" (l, r : UNRESOLVED_ufixed) return BOOLEAN;
function ">" (l, r : UNRESOLVED_sfixed) return BOOLEAN;
function "<" (l, r : UNRESOLVED_ufixed) return BOOLEAN;
function "<" (l, r : UNRESOLVED_sfixed) return BOOLEAN;
function "<=" (l, r : UNRESOLVED_ufixed) return BOOLEAN;
function "<=" (l, r : UNRESOLVED_sfixed) return BOOLEAN;
function ">=" (l, r : UNRESOLVED_ufixed) return BOOLEAN;
function ">=" (l, r : UNRESOLVED_sfixed) return BOOLEAN;
function "=" (l, r : UNRESOLVED_ufixed) return BOOLEAN;
function "=" (l, r : UNRESOLVED_sfixed) return BOOLEAN;
function "/=" (l, r : UNRESOLVED_ufixed) return BOOLEAN;
function "/=" (l, r : UNRESOLVED_sfixed) return BOOLEAN;
function \?=\ (l, r : UNRESOLVED_ufixed) return STD_ULOGIC;
function \?/=\ (l, r : UNRESOLVED_ufixed) return STD_ULOGIC;
function \?>\ (l, r : UNRESOLVED_ufixed) return STD_ULOGIC;
function \?>=\ (l, r : UNRESOLVED_ufixed) return STD_ULOGIC;
function \?<\ (l, r : UNRESOLVED_ufixed) return STD_ULOGIC;
function \?<=\ (l, r : UNRESOLVED_ufixed) return STD_ULOGIC;
function \?=\ (l, r : UNRESOLVED_sfixed) return STD_ULOGIC;
function \?/=\ (l, r : UNRESOLVED_sfixed) return STD_ULOGIC;
function \?>\ (l, r : UNRESOLVED_sfixed) return STD_ULOGIC;
function \?>=\ (l, r : UNRESOLVED_sfixed) return STD_ULOGIC;
function \?<\ (l, r : UNRESOLVED_sfixed) return STD_ULOGIC;
function \?<=\ (l, r : UNRESOLVED_sfixed) return STD_ULOGIC;
function std_match (l, r : UNRESOLVED_ufixed) return BOOLEAN;
function std_match (l, r : UNRESOLVED_sfixed) return BOOLEAN;
-- Overloads the default "maximum" and "minimum" function
function maximum (l, r : UNRESOLVED_ufixed) return UNRESOLVED_ufixed;
function minimum (l, r : UNRESOLVED_ufixed) return UNRESOLVED_ufixed;
function maximum (l, r : UNRESOLVED_sfixed) return UNRESOLVED_sfixed;
function minimum (l, r : UNRESOLVED_sfixed) return UNRESOLVED_sfixed;
----------------------------------------------------------------------------
-- In these compare functions a natural is converted into a
-- fixed point number of the bounds "maximum(l'high,0) downto 0"
----------------------------------------------------------------------------
function "=" (l : UNRESOLVED_ufixed; r : NATURAL) return BOOLEAN;
function "/=" (l : UNRESOLVED_ufixed; r : NATURAL) return BOOLEAN;
function ">=" (l : UNRESOLVED_ufixed; r : NATURAL) return BOOLEAN;
function "<=" (l : UNRESOLVED_ufixed; r : NATURAL) return BOOLEAN;
function ">" (l : UNRESOLVED_ufixed; r : NATURAL) return BOOLEAN;
function "<" (l : UNRESOLVED_ufixed; r : NATURAL) return BOOLEAN;
function "=" (l : NATURAL; r : UNRESOLVED_ufixed) return BOOLEAN;
function "/=" (l : NATURAL; r : UNRESOLVED_ufixed) return BOOLEAN;
function ">=" (l : NATURAL; r : UNRESOLVED_ufixed) return BOOLEAN;
function "<=" (l : NATURAL; r : UNRESOLVED_ufixed) return BOOLEAN;
function ">" (l : NATURAL; r : UNRESOLVED_ufixed) return BOOLEAN;
function "<" (l : NATURAL; r : UNRESOLVED_ufixed) return BOOLEAN;
function \?=\ (l : UNRESOLVED_ufixed; r : NATURAL) return STD_ULOGIC;
function \?/=\ (l : UNRESOLVED_ufixed; r : NATURAL) return STD_ULOGIC;
function \?>=\ (l : UNRESOLVED_ufixed; r : NATURAL) return STD_ULOGIC;
function \?<=\ (l : UNRESOLVED_ufixed; r : NATURAL) return STD_ULOGIC;
function \?>\ (l : UNRESOLVED_ufixed; r : NATURAL) return STD_ULOGIC;
function \?<\ (l : UNRESOLVED_ufixed; r : NATURAL) return STD_ULOGIC;
function \?=\ (l : NATURAL; r : UNRESOLVED_ufixed) return STD_ULOGIC;
function \?/=\ (l : NATURAL; r : UNRESOLVED_ufixed) return STD_ULOGIC;
function \?>=\ (l : NATURAL; r : UNRESOLVED_ufixed) return STD_ULOGIC;
function \?<=\ (l : NATURAL; r : UNRESOLVED_ufixed) return STD_ULOGIC;
function \?>\ (l : NATURAL; r : UNRESOLVED_ufixed) return STD_ULOGIC;
function \?<\ (l : NATURAL; r : UNRESOLVED_ufixed) return STD_ULOGIC;
function maximum (l : UNRESOLVED_ufixed; r : NATURAL)
return UNRESOLVED_ufixed;
function minimum (l : UNRESOLVED_ufixed; r : NATURAL)
return UNRESOLVED_ufixed;
function maximum (l : NATURAL; r : UNRESOLVED_ufixed)
return UNRESOLVED_ufixed;
function minimum (l : NATURAL; r : UNRESOLVED_ufixed)
return UNRESOLVED_ufixed;
----------------------------------------------------------------------------
-- In these compare functions a real is converted into a
-- fixed point number of the bounds "l'high+1 downto l'low"
----------------------------------------------------------------------------
function "=" (l : UNRESOLVED_ufixed; r : REAL) return BOOLEAN;
function "/=" (l : UNRESOLVED_ufixed; r : REAL) return BOOLEAN;
function ">=" (l : UNRESOLVED_ufixed; r : REAL) return BOOLEAN;
function "<=" (l : UNRESOLVED_ufixed; r : REAL) return BOOLEAN;
function ">" (l : UNRESOLVED_ufixed; r : REAL) return BOOLEAN;
function "<" (l : UNRESOLVED_ufixed; r : REAL) return BOOLEAN;
function "=" (l : REAL; r : UNRESOLVED_ufixed) return BOOLEAN;
function "/=" (l : REAL; r : UNRESOLVED_ufixed) return BOOLEAN;
function ">=" (l : REAL; r : UNRESOLVED_ufixed) return BOOLEAN;
function "<=" (l : REAL; r : UNRESOLVED_ufixed) return BOOLEAN;
function ">" (l : REAL; r : UNRESOLVED_ufixed) return BOOLEAN;
function "<" (l : REAL; r : UNRESOLVED_ufixed) return BOOLEAN;
function \?=\ (l : UNRESOLVED_ufixed; r : REAL) return STD_ULOGIC;
function \?/=\ (l : UNRESOLVED_ufixed; r : REAL) return STD_ULOGIC;
function \?>=\ (l : UNRESOLVED_ufixed; r : REAL) return STD_ULOGIC;
function \?<=\ (l : UNRESOLVED_ufixed; r : REAL) return STD_ULOGIC;
function \?>\ (l : UNRESOLVED_ufixed; r : REAL) return STD_ULOGIC;
function \?<\ (l : UNRESOLVED_ufixed; r : REAL) return STD_ULOGIC;
function \?=\ (l : REAL; r : UNRESOLVED_ufixed) return STD_ULOGIC;
function \?/=\ (l : REAL; r : UNRESOLVED_ufixed) return STD_ULOGIC;
function \?>=\ (l : REAL; r : UNRESOLVED_ufixed) return STD_ULOGIC;
function \?<=\ (l : REAL; r : UNRESOLVED_ufixed) return STD_ULOGIC;
function \?>\ (l : REAL; r : UNRESOLVED_ufixed) return STD_ULOGIC;
function \?<\ (l : REAL; r : UNRESOLVED_ufixed) return STD_ULOGIC;
function maximum (l : UNRESOLVED_ufixed; r : REAL) return UNRESOLVED_ufixed;
function maximum (l : REAL; r : UNRESOLVED_ufixed) return UNRESOLVED_ufixed;
function minimum (l : UNRESOLVED_ufixed; r : REAL) return UNRESOLVED_ufixed;
function minimum (l : REAL; r : UNRESOLVED_ufixed) return UNRESOLVED_ufixed;
----------------------------------------------------------------------------
-- In these compare functions an integer is converted into a
-- fixed point number of the bounds "maximum(l'high,1) downto 0"
----------------------------------------------------------------------------
function "=" (l : UNRESOLVED_sfixed; r : INTEGER) return BOOLEAN;
function "/=" (l : UNRESOLVED_sfixed; r : INTEGER) return BOOLEAN;
function ">=" (l : UNRESOLVED_sfixed; r : INTEGER) return BOOLEAN;
function "<=" (l : UNRESOLVED_sfixed; r : INTEGER) return BOOLEAN;
function ">" (l : UNRESOLVED_sfixed; r : INTEGER) return BOOLEAN;
function "<" (l : UNRESOLVED_sfixed; r : INTEGER) return BOOLEAN;
function "=" (l : INTEGER; r : UNRESOLVED_sfixed) return BOOLEAN;
function "/=" (l : INTEGER; r : UNRESOLVED_sfixed) return BOOLEAN;
function ">=" (l : INTEGER; r : UNRESOLVED_sfixed) return BOOLEAN;
function "<=" (l : INTEGER; r : UNRESOLVED_sfixed) return BOOLEAN;
function ">" (l : INTEGER; r : UNRESOLVED_sfixed) return BOOLEAN;
function "<" (l : INTEGER; r : UNRESOLVED_sfixed) return BOOLEAN;
function \?=\ (l : UNRESOLVED_sfixed; r : INTEGER) return STD_ULOGIC;
function \?/=\ (l : UNRESOLVED_sfixed; r : INTEGER) return STD_ULOGIC;
function \?>=\ (l : UNRESOLVED_sfixed; r : INTEGER) return STD_ULOGIC;
function \?<=\ (l : UNRESOLVED_sfixed; r : INTEGER) return STD_ULOGIC;
function \?>\ (l : UNRESOLVED_sfixed; r : INTEGER) return STD_ULOGIC;
function \?<\ (l : UNRESOLVED_sfixed; r : INTEGER) return STD_ULOGIC;
function \?=\ (l : INTEGER; r : UNRESOLVED_sfixed) return STD_ULOGIC;
function \?/=\ (l : INTEGER; r : UNRESOLVED_sfixed) return STD_ULOGIC;
function \?>=\ (l : INTEGER; r : UNRESOLVED_sfixed) return STD_ULOGIC;
function \?<=\ (l : INTEGER; r : UNRESOLVED_sfixed) return STD_ULOGIC;
function \?>\ (l : INTEGER; r : UNRESOLVED_sfixed) return STD_ULOGIC;
function \?<\ (l : INTEGER; r : UNRESOLVED_sfixed) return STD_ULOGIC;
function maximum (l : UNRESOLVED_sfixed; r : INTEGER)
return UNRESOLVED_sfixed;
function maximum (l : INTEGER; r : UNRESOLVED_sfixed)
return UNRESOLVED_sfixed;
function minimum (l : UNRESOLVED_sfixed; r : INTEGER)
return UNRESOLVED_sfixed;
function minimum (l : INTEGER; r : UNRESOLVED_sfixed)
return UNRESOLVED_sfixed;
----------------------------------------------------------------------------
-- In these compare functions a real is converted into a
-- fixed point number of the bounds "l'high+1 downto l'low"
----------------------------------------------------------------------------
function "=" (l : UNRESOLVED_sfixed; r : REAL) return BOOLEAN;
function "/=" (l : UNRESOLVED_sfixed; r : REAL) return BOOLEAN;
function ">=" (l : UNRESOLVED_sfixed; r : REAL) return BOOLEAN;
function "<=" (l : UNRESOLVED_sfixed; r : REAL) return BOOLEAN;
function ">" (l : UNRESOLVED_sfixed; r : REAL) return BOOLEAN;
function "<" (l : UNRESOLVED_sfixed; r : REAL) return BOOLEAN;
function "=" (l : REAL; r : UNRESOLVED_sfixed) return BOOLEAN;
function "/=" (l : REAL; r : UNRESOLVED_sfixed) return BOOLEAN;
function ">=" (l : REAL; r : UNRESOLVED_sfixed) return BOOLEAN;
function "<=" (l : REAL; r : UNRESOLVED_sfixed) return BOOLEAN;
function ">" (l : REAL; r : UNRESOLVED_sfixed) return BOOLEAN;
function "<" (l : REAL; r : UNRESOLVED_sfixed) return BOOLEAN;
function \?=\ (l : UNRESOLVED_sfixed; r : REAL) return STD_ULOGIC;
function \?/=\ (l : UNRESOLVED_sfixed; r : REAL) return STD_ULOGIC;
function \?>=\ (l : UNRESOLVED_sfixed; r : REAL) return STD_ULOGIC;
function \?<=\ (l : UNRESOLVED_sfixed; r : REAL) return STD_ULOGIC;
function \?>\ (l : UNRESOLVED_sfixed; r : REAL) return STD_ULOGIC;
function \?<\ (l : UNRESOLVED_sfixed; r : REAL) return STD_ULOGIC;
function \?=\ (l : REAL; r : UNRESOLVED_sfixed) return STD_ULOGIC;
function \?/=\ (l : REAL; r : UNRESOLVED_sfixed) return STD_ULOGIC;
function \?>=\ (l : REAL; r : UNRESOLVED_sfixed) return STD_ULOGIC;
function \?<=\ (l : REAL; r : UNRESOLVED_sfixed) return STD_ULOGIC;
function \?>\ (l : REAL; r : UNRESOLVED_sfixed) return STD_ULOGIC;
function \?<\ (l : REAL; r : UNRESOLVED_sfixed) return STD_ULOGIC;
function maximum (l : UNRESOLVED_sfixed; r : REAL) return UNRESOLVED_sfixed;
function maximum (l : REAL; r : UNRESOLVED_sfixed) return UNRESOLVED_sfixed;
function minimum (l : UNRESOLVED_sfixed; r : REAL) return UNRESOLVED_sfixed;
function minimum (l : REAL; r : UNRESOLVED_sfixed) return UNRESOLVED_sfixed;
--===========================================================================
-- Shift and Rotate Functions.
-- Note that sra and sla are not the same as the BIT_VECTOR version
--===========================================================================
function "sll" (ARG : UNRESOLVED_ufixed; COUNT : INTEGER)
return UNRESOLVED_ufixed;
function "srl" (ARG : UNRESOLVED_ufixed; COUNT : INTEGER)
return UNRESOLVED_ufixed;
function "rol" (ARG : UNRESOLVED_ufixed; COUNT : INTEGER)
return UNRESOLVED_ufixed;
function "ror" (ARG : UNRESOLVED_ufixed; COUNT : INTEGER)
return UNRESOLVED_ufixed;
function "sla" (ARG : UNRESOLVED_ufixed; COUNT : INTEGER)
return UNRESOLVED_ufixed;
function "sra" (ARG : UNRESOLVED_ufixed; COUNT : INTEGER)
return UNRESOLVED_ufixed;
function "sll" (ARG : UNRESOLVED_sfixed; COUNT : INTEGER)
return UNRESOLVED_sfixed;
function "srl" (ARG : UNRESOLVED_sfixed; COUNT : INTEGER)
return UNRESOLVED_sfixed;
function "rol" (ARG : UNRESOLVED_sfixed; COUNT : INTEGER)
return UNRESOLVED_sfixed;
function "ror" (ARG : UNRESOLVED_sfixed; COUNT : INTEGER)
return UNRESOLVED_sfixed;
function "sla" (ARG : UNRESOLVED_sfixed; COUNT : INTEGER)
return UNRESOLVED_sfixed;
function "sra" (ARG : UNRESOLVED_sfixed; COUNT : INTEGER)
return UNRESOLVED_sfixed;
function SHIFT_LEFT (ARG : UNRESOLVED_ufixed; COUNT : NATURAL)
return UNRESOLVED_ufixed;
function SHIFT_RIGHT (ARG : UNRESOLVED_ufixed; COUNT : NATURAL)
return UNRESOLVED_ufixed;
function SHIFT_LEFT (ARG : UNRESOLVED_sfixed; COUNT : NATURAL)
return UNRESOLVED_sfixed;
function SHIFT_RIGHT (ARG : UNRESOLVED_sfixed; COUNT : NATURAL)
return UNRESOLVED_sfixed;
----------------------------------------------------------------------------
-- logical functions
----------------------------------------------------------------------------
function "not" (l : UNRESOLVED_ufixed) return UNRESOLVED_ufixed;
function "and" (l, r : UNRESOLVED_ufixed) return UNRESOLVED_ufixed;
function "or" (l, r : UNRESOLVED_ufixed) return UNRESOLVED_ufixed;
function "nand" (l, r : UNRESOLVED_ufixed) return UNRESOLVED_ufixed;
function "nor" (l, r : UNRESOLVED_ufixed) return UNRESOLVED_ufixed;
function "xor" (l, r : UNRESOLVED_ufixed) return UNRESOLVED_ufixed;
function "xnor" (l, r : UNRESOLVED_ufixed) return UNRESOLVED_ufixed;
function "not" (l : UNRESOLVED_sfixed) return UNRESOLVED_sfixed;
function "and" (l, r : UNRESOLVED_sfixed) return UNRESOLVED_sfixed;
function "or" (l, r : UNRESOLVED_sfixed) return UNRESOLVED_sfixed;
function "nand" (l, r : UNRESOLVED_sfixed) return UNRESOLVED_sfixed;
function "nor" (l, r : UNRESOLVED_sfixed) return UNRESOLVED_sfixed;
function "xor" (l, r : UNRESOLVED_sfixed) return UNRESOLVED_sfixed;
function "xnor" (l, r : UNRESOLVED_sfixed) return UNRESOLVED_sfixed;
-- Vector and std_ulogic functions, same as functions in numeric_std
function "and" (l : STD_ULOGIC; r : UNRESOLVED_ufixed)
return UNRESOLVED_ufixed;
function "and" (l : UNRESOLVED_ufixed; r : STD_ULOGIC)
return UNRESOLVED_ufixed;
function "or" (l : STD_ULOGIC; r : UNRESOLVED_ufixed)
return UNRESOLVED_ufixed;
function "or" (l : UNRESOLVED_ufixed; r : STD_ULOGIC)
return UNRESOLVED_ufixed;
function "nand" (l : STD_ULOGIC; r : UNRESOLVED_ufixed)
return UNRESOLVED_ufixed;
function "nand" (l : UNRESOLVED_ufixed; r : STD_ULOGIC)
return UNRESOLVED_ufixed;
function "nor" (l : STD_ULOGIC; r : UNRESOLVED_ufixed)
return UNRESOLVED_ufixed;
function "nor" (l : UNRESOLVED_ufixed; r : STD_ULOGIC)
return UNRESOLVED_ufixed;
function "xor" (l : STD_ULOGIC; r : UNRESOLVED_ufixed)
return UNRESOLVED_ufixed;
function "xor" (l : UNRESOLVED_ufixed; r : STD_ULOGIC)
return UNRESOLVED_ufixed;
function "xnor" (l : STD_ULOGIC; r : UNRESOLVED_ufixed)
return UNRESOLVED_ufixed;
function "xnor" (l : UNRESOLVED_ufixed; r : STD_ULOGIC)
return UNRESOLVED_ufixed;
function "and" (l : STD_ULOGIC; r : UNRESOLVED_sfixed)
return UNRESOLVED_sfixed;
function "and" (l : UNRESOLVED_sfixed; r : STD_ULOGIC)
return UNRESOLVED_sfixed;
function "or" (l : STD_ULOGIC; r : UNRESOLVED_sfixed)
return UNRESOLVED_sfixed;
function "or" (l : UNRESOLVED_sfixed; r : STD_ULOGIC)
return UNRESOLVED_sfixed;
function "nand" (l : STD_ULOGIC; r : UNRESOLVED_sfixed)
return UNRESOLVED_sfixed;
function "nand" (l : UNRESOLVED_sfixed; r : STD_ULOGIC)
return UNRESOLVED_sfixed;
function "nor" (l : STD_ULOGIC; r : UNRESOLVED_sfixed)
return UNRESOLVED_sfixed;
function "nor" (l : UNRESOLVED_sfixed; r : STD_ULOGIC)
return UNRESOLVED_sfixed;
function "xor" (l : STD_ULOGIC; r : UNRESOLVED_sfixed)
return UNRESOLVED_sfixed;
function "xor" (l : UNRESOLVED_sfixed; r : STD_ULOGIC)
return UNRESOLVED_sfixed;
function "xnor" (l : STD_ULOGIC; r : UNRESOLVED_sfixed)
return UNRESOLVED_sfixed;
function "xnor" (l : UNRESOLVED_sfixed; r : STD_ULOGIC)
return UNRESOLVED_sfixed;
-- Reduction operators, same as numeric_std functions
function and_reduce (l : UNRESOLVED_ufixed) return STD_ULOGIC;
function nand_reduce (l : UNRESOLVED_ufixed) return STD_ULOGIC;
function or_reduce (l : UNRESOLVED_ufixed) return STD_ULOGIC;
function nor_reduce (l : UNRESOLVED_ufixed) return STD_ULOGIC;
function xor_reduce (l : UNRESOLVED_ufixed) return STD_ULOGIC;
function xnor_reduce (l : UNRESOLVED_ufixed) return STD_ULOGIC;
function and_reduce (l : UNRESOLVED_sfixed) return STD_ULOGIC;
function nand_reduce (l : UNRESOLVED_sfixed) return STD_ULOGIC;
function or_reduce (l : UNRESOLVED_sfixed) return STD_ULOGIC;
function nor_reduce (l : UNRESOLVED_sfixed) return STD_ULOGIC;
function xor_reduce (l : UNRESOLVED_sfixed) return STD_ULOGIC;
function xnor_reduce (l : UNRESOLVED_sfixed) return STD_ULOGIC;
-- returns arg'low-1 if not found
function find_leftmost (arg : UNRESOLVED_ufixed; y : STD_ULOGIC)
return INTEGER;
function find_leftmost (arg : UNRESOLVED_sfixed; y : STD_ULOGIC)
return INTEGER;
-- returns arg'high+1 if not found
function find_rightmost (arg : UNRESOLVED_ufixed; y : STD_ULOGIC)
return INTEGER;
function find_rightmost (arg : UNRESOLVED_sfixed; y : STD_ULOGIC)
return INTEGER;
--===========================================================================
-- RESIZE Functions
--===========================================================================
-- resizes the number (larger or smaller)
-- The returned result will be ufixed (left_index downto right_index)
-- If "round_style" is fixed_round, then the result will be rounded.
-- If the MSB of the remainder is a "1" AND the LSB of the unrounded result
-- is a '1' or the lower bits of the remainder include a '1' then the result
-- will be increased by the smallest representable number for that type.
-- "overflow_style" can be fixed_saturate or fixed_wrap.
-- In saturate mode, if the number overflows then the largest possible
-- representable number is returned. If wrap mode, then the upper bits
-- of the number are truncated.
function resize (
arg : UNRESOLVED_ufixed; -- input
constant left_index : INTEGER; -- integer portion
constant right_index : INTEGER; -- size of fraction
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;
constant round_style : fixed_round_style_type := fixed_round_style)
return UNRESOLVED_ufixed;
-- "size_res" functions create the size of the output from the indices
-- of the "size_res" input. The actual value of "size_res" is not used.
function resize (
arg : UNRESOLVED_ufixed; -- input
size_res : UNRESOLVED_ufixed; -- for size only
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;
constant round_style : fixed_round_style_type := fixed_round_style)
return UNRESOLVED_ufixed;
-- Note that in "wrap" mode the sign bit is not replicated. Thus the
-- resize of a negative number can have a positive result in wrap mode.
function resize (
arg : UNRESOLVED_sfixed; -- input
constant left_index : INTEGER; -- integer portion
constant right_index : INTEGER; -- size of fraction
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;
constant round_style : fixed_round_style_type := fixed_round_style)
return UNRESOLVED_sfixed;
function resize (
arg : UNRESOLVED_sfixed; -- input
size_res : UNRESOLVED_sfixed; -- for size only
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;
constant round_style : fixed_round_style_type := fixed_round_style)
return UNRESOLVED_sfixed;
--===========================================================================
-- Conversion Functions
--===========================================================================
-- integer (natural) to unsigned fixed point.
-- arguments are the upper and lower bounds of the number, thus
-- ufixed (7 downto -3) <= to_ufixed (int, 7, -3);
function to_ufixed (
arg : NATURAL; -- integer
constant left_index : INTEGER; -- left index (high index)
constant right_index : INTEGER := 0; -- right index
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;
constant round_style : fixed_round_style_type := fixed_round_style)
return UNRESOLVED_ufixed;
function to_ufixed (
arg : NATURAL; -- integer
size_res : UNRESOLVED_ufixed; -- for size only
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;
constant round_style : fixed_round_style_type := fixed_round_style)
return UNRESOLVED_ufixed;
-- real to unsigned fixed point
function to_ufixed (
arg : REAL; -- real
constant left_index : INTEGER; -- left index (high index)
constant right_index : INTEGER; -- right index
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;
constant round_style : fixed_round_style_type := fixed_round_style;
constant guard_bits : NATURAL := fixed_guard_bits)
return UNRESOLVED_ufixed;
function to_ufixed (
arg : REAL; -- real
size_res : UNRESOLVED_ufixed; -- for size only
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;
constant round_style : fixed_round_style_type := fixed_round_style;
constant guard_bits : NATURAL := fixed_guard_bits)
return UNRESOLVED_ufixed;
-- unsigned to unsigned fixed point
function to_ufixed (
arg : UNSIGNED; -- unsigned
constant left_index : INTEGER; -- left index (high index)
constant right_index : INTEGER := 0; -- right index
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;
constant round_style : fixed_round_style_type := fixed_round_style)
return UNRESOLVED_ufixed;
function to_ufixed (
arg : UNSIGNED; -- unsigned
size_res : UNRESOLVED_ufixed; -- for size only
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;
constant round_style : fixed_round_style_type := fixed_round_style)
return UNRESOLVED_ufixed;
-- Performs a conversion. ufixed (arg'range) is returned
function to_ufixed (
arg : UNSIGNED) -- unsigned
return UNRESOLVED_ufixed;
-- unsigned fixed point to unsigned
function to_unsigned (
arg : UNRESOLVED_ufixed; -- fixed point input
constant size : NATURAL; -- length of output
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;
constant round_style : fixed_round_style_type := fixed_round_style)
return UNSIGNED;
-- unsigned fixed point to unsigned
function to_unsigned (
arg : UNRESOLVED_ufixed; -- fixed point input
size_res : UNSIGNED; -- used for length of output
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;
constant round_style : fixed_round_style_type := fixed_round_style)
return UNSIGNED;
-- unsigned fixed point to real
function to_real (
arg : UNRESOLVED_ufixed) -- fixed point input
return REAL;
-- unsigned fixed point to integer
function to_integer (
arg : UNRESOLVED_ufixed; -- fixed point input
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;
constant round_style : fixed_round_style_type := fixed_round_style)
return NATURAL;
-- Integer to UNRESOLVED_sfixed
function to_sfixed (
arg : INTEGER; -- integer
constant left_index : INTEGER; -- left index (high index)
constant right_index : INTEGER := 0; -- right index
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;
constant round_style : fixed_round_style_type := fixed_round_style)
return UNRESOLVED_sfixed;
function to_sfixed (
arg : INTEGER; -- integer
size_res : UNRESOLVED_sfixed; -- for size only
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;
constant round_style : fixed_round_style_type := fixed_round_style)
return UNRESOLVED_sfixed;
-- Real to sfixed
function to_sfixed (
arg : REAL; -- real
constant left_index : INTEGER; -- left index (high index)
constant right_index : INTEGER; -- right index
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;
constant round_style : fixed_round_style_type := fixed_round_style;
constant guard_bits : NATURAL := fixed_guard_bits)
return UNRESOLVED_sfixed;
function to_sfixed (
arg : REAL; -- real
size_res : UNRESOLVED_sfixed; -- for size only
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;
constant round_style : fixed_round_style_type := fixed_round_style;
constant guard_bits : NATURAL := fixed_guard_bits)
return UNRESOLVED_sfixed;
-- signed to sfixed
function to_sfixed (
arg : SIGNED; -- signed
constant left_index : INTEGER; -- left index (high index)
constant right_index : INTEGER := 0; -- right index
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;
constant round_style : fixed_round_style_type := fixed_round_style)
return UNRESOLVED_sfixed;
function to_sfixed (
arg : SIGNED; -- signed
size_res : UNRESOLVED_sfixed; -- for size only
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;
constant round_style : fixed_round_style_type := fixed_round_style)
return UNRESOLVED_sfixed;
-- signed to sfixed (output assumed to be size of signed input)
function to_sfixed (
arg : SIGNED) -- signed
return UNRESOLVED_sfixed;
-- Conversion from ufixed to sfixed
function to_sfixed (
arg : UNRESOLVED_ufixed)
return UNRESOLVED_sfixed;
-- signed fixed point to signed
function to_signed (
arg : UNRESOLVED_sfixed; -- fixed point input
constant size : NATURAL; -- length of output
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;
constant round_style : fixed_round_style_type := fixed_round_style)
return SIGNED;
-- signed fixed point to signed
function to_signed (
arg : UNRESOLVED_sfixed; -- fixed point input
size_res : SIGNED; -- used for length of output
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;
constant round_style : fixed_round_style_type := fixed_round_style)
return SIGNED;
-- signed fixed point to real
function to_real (
arg : UNRESOLVED_sfixed) -- fixed point input
return REAL;
-- signed fixed point to integer
function to_integer (
arg : UNRESOLVED_sfixed; -- fixed point input
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;
constant round_style : fixed_round_style_type := fixed_round_style)
return INTEGER;
-- Because of the fairly complicated sizing rules in the fixed point
-- packages these functions are provided to compute the result ranges
-- Example:
-- signal uf1 : ufixed (3 downto -3);
-- signal uf2 : ufixed (4 downto -2);
-- signal uf1multuf2 : ufixed (ufixed_high (3, -3, '*', 4, -2) downto
-- ufixed_low (3, -3, '*', 4, -2));
-- uf1multuf2 <= uf1 * uf2;
-- Valid characters: '+', '-', '*', '/', 'r' or 'R' (rem), 'm' or 'M' (mod),
-- '1' (reciprocal), 'a' or 'A' (abs), 'n' or 'N' (unary -)
function ufixed_high (left_index, right_index : INTEGER;
operation : CHARACTER := 'X';
left_index2, right_index2 : INTEGER := 0)
return INTEGER;
function ufixed_low (left_index, right_index : INTEGER;
operation : CHARACTER := 'X';
left_index2, right_index2 : INTEGER := 0)
return INTEGER;
function sfixed_high (left_index, right_index : INTEGER;
operation : CHARACTER := 'X';
left_index2, right_index2 : INTEGER := 0)
return INTEGER;
function sfixed_low (left_index, right_index : INTEGER;
operation : CHARACTER := 'X';
left_index2, right_index2 : INTEGER := 0)
return INTEGER;
-- Same as above, but using the "size_res" input only for their ranges:
-- signal uf1multuf2 : ufixed (ufixed_high (uf1, '*', uf2) downto
-- ufixed_low (uf1, '*', uf2));
-- uf1multuf2 <= uf1 * uf2;
--
function ufixed_high (size_res : UNRESOLVED_ufixed;
operation : CHARACTER := 'X';
size_res2 : UNRESOLVED_ufixed)
return INTEGER;
function ufixed_low (size_res : UNRESOLVED_ufixed;
operation : CHARACTER := 'X';
size_res2 : UNRESOLVED_ufixed)
return INTEGER;
function sfixed_high (size_res : UNRESOLVED_sfixed;
operation : CHARACTER := 'X';
size_res2 : UNRESOLVED_sfixed)
return INTEGER;
function sfixed_low (size_res : UNRESOLVED_sfixed;
operation : CHARACTER := 'X';
size_res2 : UNRESOLVED_sfixed)
return INTEGER;
-- purpose: returns a saturated number
function saturate (
constant left_index : INTEGER;
constant right_index : INTEGER)
return UNRESOLVED_ufixed;
-- purpose: returns a saturated number
function saturate (
constant left_index : INTEGER;
constant right_index : INTEGER)
return UNRESOLVED_sfixed;
function saturate (
size_res : UNRESOLVED_ufixed) -- only the size of this is used
return UNRESOLVED_ufixed;
function saturate (
size_res : UNRESOLVED_sfixed) -- only the size of this is used
return UNRESOLVED_sfixed;
--===========================================================================
-- Translation Functions
--===========================================================================
-- maps meta-logical values
function to_01 (
s : UNRESOLVED_ufixed; -- fixed point input
constant XMAP : STD_ULOGIC := '0') -- Map x to
return UNRESOLVED_ufixed;
-- maps meta-logical values
function to_01 (
s : UNRESOLVED_sfixed; -- fixed point input
constant XMAP : STD_ULOGIC := '0') -- Map x to
return UNRESOLVED_sfixed;
function Is_X (arg : UNRESOLVED_ufixed) return BOOLEAN;
function Is_X (arg : UNRESOLVED_sfixed) return BOOLEAN;
function to_X01 (arg : UNRESOLVED_ufixed) return UNRESOLVED_ufixed;
function to_X01 (arg : UNRESOLVED_sfixed) return UNRESOLVED_sfixed;
function to_X01Z (arg : UNRESOLVED_ufixed) return UNRESOLVED_ufixed;
function to_X01Z (arg : UNRESOLVED_sfixed) return UNRESOLVED_sfixed;
function to_UX01 (arg : UNRESOLVED_ufixed) return UNRESOLVED_ufixed;
function to_UX01 (arg : UNRESOLVED_sfixed) return UNRESOLVED_sfixed;
-- straight vector conversion routines, needed for synthesis.
-- These functions are here so that a std_logic_vector can be
-- converted to and from sfixed and ufixed. Note that you can
-- not convert these vectors because of their negative index.
function to_slv (
arg : UNRESOLVED_ufixed) -- fixed point vector
return STD_LOGIC_VECTOR;
alias to_StdLogicVector is to_slv [UNRESOLVED_ufixed
return STD_LOGIC_VECTOR];
alias to_Std_Logic_Vector is to_slv [UNRESOLVED_ufixed
return STD_LOGIC_VECTOR];
function to_slv (
arg : UNRESOLVED_sfixed) -- fixed point vector
return STD_LOGIC_VECTOR;
alias to_StdLogicVector is to_slv [UNRESOLVED_sfixed
return STD_LOGIC_VECTOR];
alias to_Std_Logic_Vector is to_slv [UNRESOLVED_sfixed
return STD_LOGIC_VECTOR];
function to_sulv (
arg : UNRESOLVED_ufixed) -- fixed point vector
return STD_ULOGIC_VECTOR;
alias to_StdULogicVector is to_sulv [UNRESOLVED_ufixed
return STD_ULOGIC_VECTOR];
alias to_Std_ULogic_Vector is to_sulv [UNRESOLVED_ufixed
return STD_ULOGIC_VECTOR];
function to_sulv (
arg : UNRESOLVED_sfixed) -- fixed point vector
return STD_ULOGIC_VECTOR;
alias to_StdULogicVector is to_sulv [UNRESOLVED_sfixed
return STD_ULOGIC_VECTOR];
alias to_Std_ULogic_Vector is to_sulv [UNRESOLVED_sfixed
return STD_ULOGIC_VECTOR];
function to_ufixed (
arg : STD_ULOGIC_VECTOR; -- shifted vector
constant left_index : INTEGER;
constant right_index : INTEGER)
return UNRESOLVED_ufixed;
function to_ufixed (
arg : STD_ULOGIC_VECTOR; -- shifted vector
size_res : UNRESOLVED_ufixed) -- for size only
return UNRESOLVED_ufixed;
function to_sfixed (
arg : STD_ULOGIC_VECTOR; -- shifted vector
constant left_index : INTEGER;
constant right_index : INTEGER)
return UNRESOLVED_sfixed;
function to_sfixed (
arg : STD_ULOGIC_VECTOR; -- shifted vector
size_res : UNRESOLVED_sfixed) -- for size only
return UNRESOLVED_sfixed;
-- As a concession to those who use a graphical DSP environment,
-- these functions take parameters in those tools format and create
-- fixed point numbers. These functions are designed to convert from
-- a std_logic_vector to the VHDL fixed point format using the conventions
-- of these packages. In a pure VHDL environment you should use the
-- "to_ufixed" and "to_sfixed" routines.
-- unsigned fixed point
function to_UFix (
arg : STD_ULOGIC_VECTOR;
width : NATURAL; -- width of vector
fraction : NATURAL) -- width of fraction
return UNRESOLVED_ufixed;
-- signed fixed point
function to_SFix (
arg : STD_ULOGIC_VECTOR;
width : NATURAL; -- width of vector
fraction : NATURAL) -- width of fraction
return UNRESOLVED_sfixed;
-- finding the bounds of a number. These functions can be used like this:
-- signal xxx : ufixed (7 downto -3);
-- -- Which is the same as "ufixed (UFix_high (11,3) downto UFix_low(11,3))"
-- signal yyy : ufixed (UFix_high (11, 3, "+", 11, 3)
-- downto UFix_low(11, 3, "+", 11, 3));
-- Where "11" is the width of xxx (xxx'length),
-- and 3 is the lower bound (abs (xxx'low))
-- In a pure VHDL environment use "ufixed_high" and "ufixed_low"
function UFix_high (width, fraction : NATURAL;
operation : CHARACTER := 'X';
width2, fraction2 : NATURAL := 0)
return INTEGER;
function UFix_low (width, fraction : NATURAL;
operation : CHARACTER := 'X';
width2, fraction2 : NATURAL := 0)
return INTEGER;
-- Same as above but for signed fixed point. Note that the width
-- of a signed fixed point number ignores the sign bit, thus
-- width = sxxx'length-1
function SFix_high (width, fraction : NATURAL;
operation : CHARACTER := 'X';
width2, fraction2 : NATURAL := 0)
return INTEGER;
function SFix_low (width, fraction : NATURAL;
operation : CHARACTER := 'X';
width2, fraction2 : NATURAL := 0)
return INTEGER;
-- rtl_synthesis off
-- pragma synthesis_off
--===========================================================================
-- string and textio Functions
--===========================================================================
-- purpose: writes fixed point into a line
procedure WRITE (
L : inout LINE; -- input line
VALUE : in UNRESOLVED_ufixed; -- fixed point input
JUSTIFIED : in SIDE := right;
FIELD : in WIDTH := 0);
-- purpose: writes fixed point into a line
procedure WRITE (
L : inout LINE; -- input line
VALUE : in UNRESOLVED_sfixed; -- fixed point input
JUSTIFIED : in SIDE := right;
FIELD : in WIDTH := 0);
procedure READ(L : inout LINE;
VALUE : out UNRESOLVED_ufixed);
procedure READ(L : inout LINE;
VALUE : out UNRESOLVED_ufixed;
GOOD : out BOOLEAN);
procedure READ(L : inout LINE;
VALUE : out UNRESOLVED_sfixed);
procedure READ(L : inout LINE;
VALUE : out UNRESOLVED_sfixed;
GOOD : out BOOLEAN);
alias bwrite is WRITE [LINE, UNRESOLVED_ufixed, SIDE, width];
alias bwrite is WRITE [LINE, UNRESOLVED_sfixed, SIDE, width];
alias bread is READ [LINE, UNRESOLVED_ufixed];
alias bread is READ [LINE, UNRESOLVED_ufixed, BOOLEAN];
alias bread is READ [LINE, UNRESOLVED_sfixed];
alias bread is READ [LINE, UNRESOLVED_sfixed, BOOLEAN];
alias BINARY_WRITE is WRITE [LINE, UNRESOLVED_ufixed, SIDE, width];
alias BINARY_WRITE is WRITE [LINE, UNRESOLVED_sfixed, SIDE, width];
alias BINARY_READ is READ [LINE, UNRESOLVED_ufixed, BOOLEAN];
alias BINARY_READ is READ [LINE, UNRESOLVED_ufixed];
alias BINARY_READ is READ [LINE, UNRESOLVED_sfixed, BOOLEAN];
alias BINARY_READ is READ [LINE, UNRESOLVED_sfixed];
-- octal read and write
procedure OWRITE (
L : inout LINE; -- input line
VALUE : in UNRESOLVED_ufixed; -- fixed point input
JUSTIFIED : in SIDE := right;
FIELD : in WIDTH := 0);
procedure OWRITE (
L : inout LINE; -- input line
VALUE : in UNRESOLVED_sfixed; -- fixed point input
JUSTIFIED : in SIDE := right;
FIELD : in WIDTH := 0);
procedure OREAD(L : inout LINE;
VALUE : out UNRESOLVED_ufixed);
procedure OREAD(L : inout LINE;
VALUE : out UNRESOLVED_ufixed;
GOOD : out BOOLEAN);
procedure OREAD(L : inout LINE;
VALUE : out UNRESOLVED_sfixed);
procedure OREAD(L : inout LINE;
VALUE : out UNRESOLVED_sfixed;
GOOD : out BOOLEAN);
alias OCTAL_READ is OREAD [LINE, UNRESOLVED_ufixed, BOOLEAN];
alias OCTAL_READ is OREAD [LINE, UNRESOLVED_ufixed];
alias OCTAL_READ is OREAD [LINE, UNRESOLVED_sfixed, BOOLEAN];
alias OCTAL_READ is OREAD [LINE, UNRESOLVED_sfixed];
alias OCTAL_WRITE is OWRITE [LINE, UNRESOLVED_ufixed, SIDE, WIDTH];
alias OCTAL_WRITE is OWRITE [LINE, UNRESOLVED_sfixed, SIDE, WIDTH];
-- hex read and write
procedure HWRITE (
L : inout LINE; -- input line
VALUE : in UNRESOLVED_ufixed; -- fixed point input
JUSTIFIED : in SIDE := right;
FIELD : in WIDTH := 0);
-- purpose: writes fixed point into a line
procedure HWRITE (
L : inout LINE; -- input line
VALUE : in UNRESOLVED_sfixed; -- fixed point input
JUSTIFIED : in SIDE := right;
FIELD : in WIDTH := 0);
procedure HREAD(L : inout LINE;
VALUE : out UNRESOLVED_ufixed);
procedure HREAD(L : inout LINE;
VALUE : out UNRESOLVED_ufixed;
GOOD : out BOOLEAN);
procedure HREAD(L : inout LINE;
VALUE : out UNRESOLVED_sfixed);
procedure HREAD(L : inout LINE;
VALUE : out UNRESOLVED_sfixed;
GOOD : out BOOLEAN);
alias HEX_READ is HREAD [LINE, UNRESOLVED_ufixed, BOOLEAN];
alias HEX_READ is HREAD [LINE, UNRESOLVED_sfixed, BOOLEAN];
alias HEX_READ is HREAD [LINE, UNRESOLVED_ufixed];
alias HEX_READ is HREAD [LINE, UNRESOLVED_sfixed];
alias HEX_WRITE is HWRITE [LINE, UNRESOLVED_ufixed, SIDE, WIDTH];
alias HEX_WRITE is HWRITE [LINE, UNRESOLVED_sfixed, SIDE, WIDTH];
-- returns a string, useful for:
-- assert (x = y) report "error found " & to_string(x) severity error;
function to_string (value : UNRESOLVED_ufixed) return STRING;
alias to_bstring is to_string [UNRESOLVED_ufixed return STRING];
alias TO_BINARY_STRING is TO_STRING [UNRESOLVED_ufixed return STRING];
function to_ostring (value : UNRESOLVED_ufixed) return STRING;
alias TO_OCTAL_STRING is TO_OSTRING [UNRESOLVED_ufixed return STRING];
function to_hstring (value : UNRESOLVED_ufixed) return STRING;
alias TO_HEX_STRING is TO_HSTRING [UNRESOLVED_ufixed return STRING];
function to_string (value : UNRESOLVED_sfixed) return STRING;
alias to_bstring is to_string [UNRESOLVED_sfixed return STRING];
alias TO_BINARY_STRING is TO_STRING [UNRESOLVED_sfixed return STRING];
function to_ostring (value : UNRESOLVED_sfixed) return STRING;
alias TO_OCTAL_STRING is TO_OSTRING [UNRESOLVED_sfixed return STRING];
function to_hstring (value : UNRESOLVED_sfixed) return STRING;
alias TO_HEX_STRING is TO_HSTRING [UNRESOLVED_sfixed return STRING];
-- From string functions allow you to convert a string into a fixed
-- point number. Example:
-- signal uf1 : ufixed (3 downto -3);
-- uf1 <= from_string ("0110.100", uf1'high, uf1'low); -- 6.5
-- The "." is optional in this syntax, however it exist and is
-- in the wrong location an error is produced. Overflow will
-- result in saturation.
function from_string (
bstring : STRING; -- binary string
constant left_index : INTEGER;
constant right_index : INTEGER)
return UNRESOLVED_ufixed;
alias from_bstring is from_string [STRING, INTEGER, INTEGER
return UNRESOLVED_ufixed];
alias from_binary_string is from_string [STRING, INTEGER, INTEGER
return UNRESOLVED_ufixed];
-- Octal and hex conversions work as follows:
-- uf1 <= from_hstring ("6.8", 3, -3); -- 6.5 (bottom zeros dropped)
-- uf1 <= from_ostring ("06.4", 3, -3); -- 6.5 (top zeros dropped)
function from_ostring (
ostring : STRING; -- Octal string
constant left_index : INTEGER;
constant right_index : INTEGER)
return UNRESOLVED_ufixed;
alias from_octal_string is from_ostring [STRING, INTEGER, INTEGER
return UNRESOLVED_ufixed];
function from_hstring (
hstring : STRING; -- hex string
constant left_index : INTEGER;
constant right_index : INTEGER)
return UNRESOLVED_ufixed;
alias from_hex_string is from_hstring [STRING, INTEGER, INTEGER
return UNRESOLVED_ufixed];
function from_string (
bstring : STRING; -- binary string
constant left_index : INTEGER;
constant right_index : INTEGER)
return UNRESOLVED_sfixed;
alias from_bstring is from_string [STRING, INTEGER, INTEGER
return UNRESOLVED_sfixed];
alias from_binary_string is from_string [STRING, INTEGER, INTEGER
return UNRESOLVED_sfixed];
function from_ostring (
ostring : STRING; -- Octal string
constant left_index : INTEGER;
constant right_index : INTEGER)
return UNRESOLVED_sfixed;
alias from_octal_string is from_ostring [STRING, INTEGER, INTEGER
return UNRESOLVED_sfixed];
function from_hstring (
hstring : STRING; -- hex string
constant left_index : INTEGER;
constant right_index : INTEGER)
return UNRESOLVED_sfixed;
alias from_hex_string is from_hstring [STRING, INTEGER, INTEGER
return UNRESOLVED_sfixed];
-- Same as above, "size_res" is used for it's range only.
function from_string (
bstring : STRING; -- binary string
size_res : UNRESOLVED_ufixed)
return UNRESOLVED_ufixed;
alias from_bstring is from_string [STRING, UNRESOLVED_ufixed
return UNRESOLVED_ufixed];
alias from_binary_string is from_string [STRING, UNRESOLVED_ufixed
return UNRESOLVED_ufixed];
function from_ostring (
ostring : STRING; -- Octal string
size_res : UNRESOLVED_ufixed)
return UNRESOLVED_ufixed;
alias from_octal_string is from_ostring [STRING, UNRESOLVED_ufixed
return UNRESOLVED_ufixed];
function from_hstring (
hstring : STRING; -- hex string
size_res : UNRESOLVED_ufixed)
return UNRESOLVED_ufixed;
alias from_hex_string is from_hstring [STRING, UNRESOLVED_ufixed
return UNRESOLVED_ufixed];
function from_string (
bstring : STRING; -- binary string
size_res : UNRESOLVED_sfixed)
return UNRESOLVED_sfixed;
alias from_bstring is from_string [STRING, UNRESOLVED_sfixed
return UNRESOLVED_sfixed];
alias from_binary_string is from_string [STRING, UNRESOLVED_sfixed
return UNRESOLVED_sfixed];
function from_ostring (
ostring : STRING; -- Octal string
size_res : UNRESOLVED_sfixed)
return UNRESOLVED_sfixed;
alias from_octal_string is from_ostring [STRING, UNRESOLVED_sfixed
return UNRESOLVED_sfixed];
function from_hstring (
hstring : STRING; -- hex string
size_res : UNRESOLVED_sfixed)
return UNRESOLVED_sfixed;
alias from_hex_string is from_hstring [STRING, UNRESOLVED_sfixed
return UNRESOLVED_sfixed];
-- Direct conversion functions. Example:
-- signal uf1 : ufixed (3 downto -3);
-- uf1 <= from_string ("0110.100"); -- 6.5
-- In this case the "." is not optional, and the size of
-- the output must match exactly.
function from_string (
bstring : STRING) -- binary string
return UNRESOLVED_ufixed;
alias from_bstring is from_string [STRING return UNRESOLVED_ufixed];
alias from_binary_string is from_string [STRING return UNRESOLVED_ufixed];
-- Direct octal and hex conversion functions. In this case
-- the string lengths must match. Example:
-- signal sf1 := sfixed (5 downto -3);
-- sf1 <= from_ostring ("71.4") -- -6.5
function from_ostring (
ostring : STRING) -- Octal string
return UNRESOLVED_ufixed;
alias from_octal_string is from_ostring [STRING return UNRESOLVED_ufixed];
function from_hstring (
hstring : STRING) -- hex string
return UNRESOLVED_ufixed;
alias from_hex_string is from_hstring [STRING return UNRESOLVED_ufixed];
function from_string (
bstring : STRING) -- binary string
return UNRESOLVED_sfixed;
alias from_bstring is from_string [STRING return UNRESOLVED_sfixed];
alias from_binary_string is from_string [STRING return UNRESOLVED_sfixed];
function from_ostring (
ostring : STRING) -- Octal string
return UNRESOLVED_sfixed;
alias from_octal_string is from_ostring [STRING return UNRESOLVED_sfixed];
function from_hstring (
hstring : STRING) -- hex string
return UNRESOLVED_sfixed;
alias from_hex_string is from_hstring [STRING return UNRESOLVED_sfixed];
-- rtl_synthesis on
-- pragma synthesis_on
-- IN VHDL-2006 std_logic_vector is a subtype of std_ulogic_vector, so these
-- extra functions are needed for compatability.
function to_ufixed (
arg : STD_LOGIC_VECTOR; -- shifted vector
constant left_index : INTEGER;
constant right_index : INTEGER)
return UNRESOLVED_ufixed;
function to_ufixed (
arg : STD_LOGIC_VECTOR; -- shifted vector
size_res : UNRESOLVED_ufixed) -- for size only
return UNRESOLVED_ufixed;
function to_sfixed (
arg : STD_LOGIC_VECTOR; -- shifted vector
constant left_index : INTEGER;
constant right_index : INTEGER)
return UNRESOLVED_sfixed;
function to_sfixed (
arg : STD_LOGIC_VECTOR; -- shifted vector
size_res : UNRESOLVED_sfixed) -- for size only
return UNRESOLVED_sfixed;
-- unsigned fixed point
function to_UFix (
arg : STD_LOGIC_VECTOR;
width : NATURAL; -- width of vector
fraction : NATURAL) -- width of fraction
return UNRESOLVED_ufixed;
-- signed fixed point
function to_SFix (
arg : STD_LOGIC_VECTOR;
width : NATURAL; -- width of vector
fraction : NATURAL) -- width of fraction
return UNRESOLVED_sfixed;
end package fixed_pkg;
-------------------------------------------------------------------------------
-- Proposed package body for the VHDL-200x-FT fixed_pkg package
-- (Fixed point math package)
-- This package body supplies a recommended implementation of these functions
-- Version : $Revision: 1.22 $
-- Date : $Date: 2010/09/22 18:34:14 $
--
-- Created for VHDL-200X-ft, David Bishop ([email protected])
-------------------------------------------------------------------------------
library IEEE;
use IEEE.MATH_REAL.all;
package body fixed_pkg is
-- Author David Bishop ([email protected])
-- Other contributers: Jim Lewis, Yannick Grugni, Ryan W. Hilton
-- null array constants
constant NAUF : UNRESOLVED_ufixed (0 downto 1) := (others => '0');
constant NASF : UNRESOLVED_sfixed (0 downto 1) := (others => '0');
constant NSLV : STD_ULOGIC_VECTOR (0 downto 1) := (others => '0');
-- This differed constant will tell you if the package body is synthesizable
-- or implemented as real numbers, set to "true" if synthesizable.
constant fixedsynth_or_real : BOOLEAN := true;
-- %%% Replicated functions
function maximum (
l, r : integer) -- inputs
return integer is
begin -- function max
if l > r then return l;
else return r;
end if;
end function maximum;
function minimum (
l, r : integer) -- inputs
return integer is
begin -- function min
if l > r then return r;
else return l;
end if;
end function minimum;
function "sra" (arg : SIGNED; count : INTEGER)
return SIGNED is
begin
if (COUNT >= 0) then
return SHIFT_RIGHT(arg, count);
else
return SHIFT_LEFT(arg, -count);
end if;
end function "sra";
function or_reduce (arg : STD_ULOGIC_VECTOR)
return STD_LOGIC is
variable Upper, Lower : STD_ULOGIC;
variable Half : INTEGER;
variable BUS_int : STD_ULOGIC_VECTOR (arg'length - 1 downto 0);
variable Result : STD_ULOGIC;
begin
if (arg'length < 1) then -- In the case of a NULL range
Result := '0';
else
BUS_int := to_ux01 (arg);
if (BUS_int'length = 1) then
Result := BUS_int (BUS_int'left);
elsif (BUS_int'length = 2) then
Result := BUS_int (BUS_int'right) or BUS_int (BUS_int'left);
else
Half := (BUS_int'length + 1) / 2 + BUS_int'right;
Upper := or_reduce (BUS_int (BUS_int'left downto Half));
Lower := or_reduce (BUS_int (Half - 1 downto BUS_int'right));
Result := Upper or Lower;
end if;
end if;
return Result;
end function or_reduce;
-- purpose: AND all of the bits in a vector together
-- This is a copy of the proposed "and_reduce" from 1076.3
function and_reduce (arg : STD_ULOGIC_VECTOR)
return STD_LOGIC is
variable Upper, Lower : STD_ULOGIC;
variable Half : INTEGER;
variable BUS_int : STD_ULOGIC_VECTOR (arg'length - 1 downto 0);
variable Result : STD_ULOGIC;
begin
if (arg'length < 1) then -- In the case of a NULL range
Result := '1';
else
BUS_int := to_ux01 (arg);
if (BUS_int'length = 1) then
Result := BUS_int (BUS_int'left);
elsif (BUS_int'length = 2) then
Result := BUS_int (BUS_int'right) and BUS_int (BUS_int'left);
else
Half := (BUS_int'length + 1) / 2 + BUS_int'right;
Upper := and_reduce (BUS_int (BUS_int'left downto Half));
Lower := and_reduce (BUS_int (Half - 1 downto BUS_int'right));
Result := Upper and Lower;
end if;
end if;
return Result;
end function and_reduce;
function xor_reduce (arg : STD_ULOGIC_VECTOR) return STD_ULOGIC is
variable Upper, Lower : STD_ULOGIC;
variable Half : INTEGER;
variable BUS_int : STD_ULOGIC_VECTOR (arg'length - 1 downto 0);
variable Result : STD_ULOGIC := '0'; -- In the case of a NULL range
begin
if (arg'length >= 1) then
BUS_int := to_ux01 (arg);
if (BUS_int'length = 1) then
Result := BUS_int (BUS_int'left);
elsif (BUS_int'length = 2) then
Result := BUS_int(BUS_int'right) xor BUS_int(BUS_int'left);
else
Half := (BUS_int'length + 1) / 2 + BUS_int'right;
Upper := xor_reduce (BUS_int (BUS_int'left downto Half));
Lower := xor_reduce (BUS_int (Half - 1 downto BUS_int'right));
Result := Upper xor Lower;
end if;
end if;
return Result;
end function xor_reduce;
function nand_reduce(arg : std_ulogic_vector) return STD_ULOGIC is
begin
return not and_reduce (arg);
end function nand_reduce;
function nor_reduce(arg : std_ulogic_vector) return STD_ULOGIC is
begin
return not or_reduce (arg);
end function nor_reduce;
function xnor_reduce(arg : std_ulogic_vector) return STD_ULOGIC is
begin
return not xor_reduce (arg);
end function xnor_reduce;
-- Match table, copied form new std_logic_1164
type stdlogic_table is array(STD_ULOGIC, STD_ULOGIC) of STD_ULOGIC;
constant match_logic_table : stdlogic_table := (
-----------------------------------------------------
-- U X 0 1 Z W L H - | |
-----------------------------------------------------
('U', 'U', 'U', 'U', 'U', 'U', 'U', 'U', '1'), -- | U |
('U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', '1'), -- | X |
('U', 'X', '1', '0', 'X', 'X', '1', '0', '1'), -- | 0 |
('U', 'X', '0', '1', 'X', 'X', '0', '1', '1'), -- | 1 |
('U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', '1'), -- | Z |
('U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', '1'), -- | W |
('U', 'X', '1', '0', 'X', 'X', '1', '0', '1'), -- | L |
('U', 'X', '0', '1', 'X', 'X', '0', '1', '1'), -- | H |
('1', '1', '1', '1', '1', '1', '1', '1', '1') -- | - |
);
-------------------------------------------------------------------
-- ?= functions, Similar to "std_match", but returns "std_ulogic".
-------------------------------------------------------------------
function \?=\ (l, r : STD_ULOGIC) return STD_ULOGIC is
begin
return match_logic_table (l, r);
end function \?=\;
function \?/=\ (l, r : STD_ULOGIC) return STD_ULOGIC is
begin
return not match_logic_table (l, r);
end function \?/=\;
-- "?=" operator is similar to "std_match", but returns a std_ulogic..
-- Id: M.2B
function \?=\ (L, R: UNSIGNED) return STD_ULOGIC is
constant L_LEFT : INTEGER := L'LENGTH-1;
constant R_LEFT : INTEGER := R'LENGTH-1;
alias XL : UNSIGNED(L_LEFT downto 0) is L;
alias XR : UNSIGNED(R_LEFT downto 0) is R;
constant SIZE : NATURAL := MAXIMUM(L'LENGTH, R'LENGTH);
variable LX : UNSIGNED(SIZE-1 downto 0);
variable RX : UNSIGNED(SIZE-1 downto 0);
variable result, result1 : STD_ULOGIC; -- result
begin
-- Logically identical to an "=" operator.
if ((L'LENGTH < 1) or (R'LENGTH < 1)) then
assert NO_WARNING
report "NUMERIC_STD.""?="": null detected, returning X"
severity warning;
return 'X';
else
LX := RESIZE(XL, SIZE);
RX := RESIZE(XR, SIZE);
result := '1';
for i in LX'low to LX'high loop
result1 := \?=\(LX(i), RX(i));
if result1 = 'U' then
return 'U';
elsif result1 = 'X' or result = 'X' then
result := 'X';
else
result := result and result1;
end if;
end loop;
return result;
end if;
end function \?=\;
-- Id: M.3B
function \?=\ (L, R: SIGNED) return std_ulogic is
constant L_LEFT : INTEGER := L'LENGTH-1;
constant R_LEFT : INTEGER := R'LENGTH-1;
alias XL : SIGNED(L_LEFT downto 0) is L;
alias XR : SIGNED(R_LEFT downto 0) is R;
constant SIZE : NATURAL := MAXIMUM(L'LENGTH, R'LENGTH);
variable LX : SIGNED(SIZE-1 downto 0);
variable RX : SIGNED(SIZE-1 downto 0);
variable result, result1 : STD_ULOGIC; -- result
begin -- ?=
if ((L'LENGTH < 1) or (R'LENGTH < 1)) then
assert NO_WARNING
report "NUMERIC_STD.""?="": null detected, returning X"
severity warning;
return 'X';
else
LX := RESIZE(XL, SIZE);
RX := RESIZE(XR, SIZE);
result := '1';
for i in LX'low to LX'high loop
result1 := \?=\ (LX(i), RX(i));
if result1 = 'U' then
return 'U';
elsif result1 = 'X' or result = 'X' then
result := 'X';
else
result := result and result1;
end if;
end loop;
return result;
end if;
end function \?=\;
function \?/=\ (L, R : UNSIGNED) return std_ulogic is
constant L_LEFT : INTEGER := L'LENGTH-1;
constant R_LEFT : INTEGER := R'LENGTH-1;
alias XL : UNSIGNED(L_LEFT downto 0) is L;
alias XR : UNSIGNED(R_LEFT downto 0) is R;
constant SIZE : NATURAL := MAXIMUM(L'LENGTH, R'LENGTH);
variable LX : UNSIGNED(SIZE-1 downto 0);
variable RX : UNSIGNED(SIZE-1 downto 0);
variable result, result1 : STD_ULOGIC; -- result
begin -- ?=
if ((L'LENGTH < 1) or (R'LENGTH < 1)) then
assert NO_WARNING
report "NUMERIC_STD.""?/="": null detected, returning X"
severity warning;
return 'X';
else
LX := RESIZE(XL, SIZE);
RX := RESIZE(XR, SIZE);
result := '0';
for i in LX'low to LX'high loop
result1 := \?/=\ (LX(i), RX(i));
if result1 = 'U' then
result := 'U';
elsif result1 = 'X' or result = 'X' then
result := 'X';
else
result := result or result1;
end if;
end loop;
return result;
end if;
end function \?/=\;
function \?/=\ (L, R : SIGNED) return std_ulogic is
constant L_LEFT : INTEGER := L'LENGTH-1;
constant R_LEFT : INTEGER := R'LENGTH-1;
alias XL : SIGNED(L_LEFT downto 0) is L;
alias XR : SIGNED(R_LEFT downto 0) is R;
constant SIZE : NATURAL := MAXIMUM(L'LENGTH, R'LENGTH);
variable LX : SIGNED(SIZE-1 downto 0);
variable RX : SIGNED(SIZE-1 downto 0);
variable result, result1 : STD_ULOGIC; -- result
begin -- ?=
if ((L'LENGTH < 1) or (R'LENGTH < 1)) then
assert NO_WARNING
report "NUMERIC_STD.""?/="": null detected, returning X"
severity warning;
return 'X';
else
LX := RESIZE(XL, SIZE);
RX := RESIZE(XR, SIZE);
result := '0';
for i in LX'low to LX'high loop
result1 := \?/=\ (LX(i), RX(i));
if result1 = 'U' then
return 'U';
elsif result1 = 'X' or result = 'X' then
result := 'X';
else
result := result or result1;
end if;
end loop;
return result;
end if;
end function \?/=\;
function Is_X ( s : UNSIGNED ) return BOOLEAN is
begin
return Is_X (STD_LOGIC_VECTOR (s));
end function Is_X;
function Is_X ( s : SIGNED ) return BOOLEAN is
begin
return Is_X (STD_LOGIC_VECTOR (s));
end function Is_X;
function \?>\ (L, R : UNSIGNED) return STD_ULOGIC is
begin
if ((l'length < 1) or (r'length < 1)) then
assert NO_WARNING
report "NUMERIC_STD.""?>"": null detected, returning X"
severity warning;
return 'X';
else
for i in L'range loop
if L(i) = '-' then
report "NUMERIC_STD.""?>"": '-' found in compare string"
severity error;
return 'X';
end if;
end loop;
for i in R'range loop
if R(i) = '-' then
report "NUMERIC_STD.""?>"": '-' found in compare string"
severity error;
return 'X';
end if;
end loop;
if is_x(l) or is_x(r) then
return 'X';
elsif l > r then
return '1';
else
return '0';
end if;
end if;
end function \?>\;
-- %%% function "?>" (L, R : UNSIGNED) return std_ulogic is
-- %%% end function "?>"\;
function \?>\ (L, R : SIGNED) return STD_ULOGIC is
begin
if ((l'length < 1) or (r'length < 1)) then
assert NO_WARNING
report "NUMERIC_STD.""?>"": null detected, returning X"
severity warning;
return 'X';
else
for i in L'range loop
if L(i) = '-' then
report "NUMERIC_STD.""?>"": '-' found in compare string"
severity error;
return 'X';
end if;
end loop;
for i in R'range loop
if R(i) = '-' then
report "NUMERIC_STD.""?>"": '-' found in compare string"
severity error;
return 'X';
end if;
end loop;
if is_x(l) or is_x(r) then
return 'X';
elsif l > r then
return '1';
else
return '0';
end if;
end if;
end function \?>\;
function \?>=\ (L, R : UNSIGNED) return STD_ULOGIC is
begin
if ((l'length < 1) or (r'length < 1)) then
assert NO_WARNING
report "NUMERIC_STD.""?>="": null detected, returning X"
severity warning;
return 'X';
else
for i in L'range loop
if L(i) = '-' then
report "NUMERIC_STD.""?>="": '-' found in compare string"
severity error;
return 'X';
end if;
end loop;
for i in R'range loop
if R(i) = '-' then
report "NUMERIC_STD.""?>="": '-' found in compare string"
severity error;
return 'X';
end if;
end loop;
if is_x(l) or is_x(r) then
return 'X';
elsif l >= r then
return '1';
else
return '0';
end if;
end if;
end function \?>=\;
-- %%% function "?>=" (L, R : UNSIGNED) return std_ulogic is
-- %%% end function "?>=";
function \?>=\ (L, R : SIGNED) return STD_ULOGIC is
begin
if ((l'length < 1) or (r'length < 1)) then
assert NO_WARNING
report "NUMERIC_STD.""?>="": null detected, returning X"
severity warning;
return 'X';
else
for i in L'range loop
if L(i) = '-' then
report "NUMERIC_STD.""?>="": '-' found in compare string"
severity error;
return 'X';
end if;
end loop;
for i in R'range loop
if R(i) = '-' then
report "NUMERIC_STD.""?>="": '-' found in compare string"
severity error;
return 'X';
end if;
end loop;
if is_x(l) or is_x(r) then
return 'X';
elsif l >= r then
return '1';
else
return '0';
end if;
end if;
end function \?>=\;
function \?<\ (L, R : UNSIGNED) return STD_ULOGIC is
begin
if ((l'length < 1) or (r'length < 1)) then
assert NO_WARNING
report "NUMERIC_STD.""?<"": null detected, returning X"
severity warning;
return 'X';
else
for i in L'range loop
if L(i) = '-' then
report "NUMERIC_STD.""?<"": '-' found in compare string"
severity error;
return 'X';
end if;
end loop;
for i in R'range loop
if R(i) = '-' then
report "NUMERIC_STD.""?<"": '-' found in compare string"
severity error;
return 'X';
end if;
end loop;
if is_x(l) or is_x(r) then
return 'X';
elsif l < r then
return '1';
else
return '0';
end if;
end if;
end function \?<\;
-- %%% function "?<" (L, R : UNSIGNED) return std_ulogic is
-- %%% end function "?<";
function \?<\ (L, R : SIGNED) return STD_ULOGIC is
begin
if ((l'length < 1) or (r'length < 1)) then
assert NO_WARNING
report "NUMERIC_STD.""?<"": null detected, returning X"
severity warning;
return 'X';
else
for i in L'range loop
if L(i) = '-' then
report "NUMERIC_STD.""?<"": '-' found in compare string"
severity error;
return 'X';
end if;
end loop;
for i in R'range loop
if R(i) = '-' then
report "NUMERIC_STD.""?<"": '-' found in compare string"
severity error;
return 'X';
end if;
end loop;
if is_x(l) or is_x(r) then
return 'X';
elsif l < r then
return '1';
else
return '0';
end if;
end if;
end function \?<\;
function \?<=\ (L, R : UNSIGNED) return STD_ULOGIC is
begin
if ((l'length < 1) or (r'length < 1)) then
assert NO_WARNING
report "NUMERIC_STD.""?<="": null detected, returning X"
severity warning;
return 'X';
else
for i in L'range loop
if L(i) = '-' then
report "NUMERIC_STD.""?<="": '-' found in compare string"
severity error;
return 'X';
end if;
end loop;
for i in R'range loop
if R(i) = '-' then
report "NUMERIC_STD.""?<="": '-' found in compare string"
severity error;
return 'X';
end if;
end loop;
if is_x(l) or is_x(r) then
return 'X';
elsif l <= r then
return '1';
else
return '0';
end if;
end if;
end function \?<=\;
-- %%% function "?<=" (L, R : UNSIGNED) return std_ulogic is
-- %%% end function "?<=";
function \?<=\ (L, R : SIGNED) return STD_ULOGIC is
begin
if ((l'length < 1) or (r'length < 1)) then
assert NO_WARNING
report "NUMERIC_STD.""?<="": null detected, returning X"
severity warning;
return 'X';
else
for i in L'range loop
if L(i) = '-' then
report "NUMERIC_STD.""?<="": '-' found in compare string"
severity error;
return 'X';
end if;
end loop;
for i in R'range loop
if R(i) = '-' then
report "NUMERIC_STD.""?<="": '-' found in compare string"
severity error;
return 'X';
end if;
end loop;
if is_x(l) or is_x(r) then
return 'X';
elsif l <= r then
return '1';
else
return '0';
end if;
end if;
end function \?<=\;
-- %%% END replicated functions
-- Special version of "minimum" to do some boundary checking without errors
function mins (l, r : INTEGER)
return INTEGER is
begin -- function mins
if (L = INTEGER'low or R = INTEGER'low) then
return 0; -- error condition, silent
end if;
return minimum (L, R);
end function mins;
-- Special version of "minimum" to do some boundary checking with errors
function mine (l, r : INTEGER)
return INTEGER is
begin -- function mine
if (L = INTEGER'low or R = INTEGER'low) then
report "fixed_pkg"
& " Unbounded number passed, was a literal used?"
severity error;
return 0;
end if;
return minimum (L, R);
end function mine;
-- The following functions are used only internally. Every function
-- calls "cleanvec" either directly or indirectly.
-- purpose: Fixes "downto" problem and resolves meta states
function cleanvec (
arg : UNRESOLVED_sfixed) -- input
return UNRESOLVED_sfixed is
constant left_index : INTEGER := maximum(arg'left, arg'right);
constant right_index : INTEGER := mins(arg'left, arg'right);
variable result : UNRESOLVED_sfixed (arg'range);
begin -- function cleanvec
assert not (arg'ascending and (arg'low /= INTEGER'low))
report "fixed_pkg"
& " Vector passed using a ""to"" range, expected is ""downto"""
severity error;
return arg;
end function cleanvec;
-- purpose: Fixes "downto" problem and resolves meta states
function cleanvec (
arg : UNRESOLVED_ufixed) -- input
return UNRESOLVED_ufixed is
constant left_index : INTEGER := maximum(arg'left, arg'right);
constant right_index : INTEGER := mins(arg'left, arg'right);
variable result : UNRESOLVED_ufixed (arg'range);
begin -- function cleanvec
assert not (arg'ascending and (arg'low /= INTEGER'low))
report "fixed_pkg"
& " Vector passed using a ""to"" range, expected is ""downto"""
severity error;
return arg;
end function cleanvec;
-- Type convert a "unsigned" into a "ufixed", used internally
function to_fixed (
arg : UNSIGNED; -- shifted vector
constant left_index : INTEGER;
constant right_index : INTEGER)
return UNRESOLVED_ufixed is
variable result : UNRESOLVED_ufixed (left_index downto right_index);
begin -- function to_fixed
result := UNRESOLVED_ufixed(arg);
return result;
end function to_fixed;
-- Type convert a "signed" into an "sfixed", used internally
function to_fixed (
arg : SIGNED; -- shifted vector
constant left_index : INTEGER;
constant right_index : INTEGER)
return UNRESOLVED_sfixed is
variable result : UNRESOLVED_sfixed (left_index downto right_index);
begin -- function to_fixed
result := UNRESOLVED_sfixed(arg);
return result;
end function to_fixed;
-- Type convert a "ufixed" into an "unsigned", used internally
function to_uns (
arg : UNRESOLVED_ufixed) -- fp vector
return UNSIGNED is
subtype t is UNSIGNED(arg'high - arg'low downto 0);
variable slv : t;
begin -- function to_uns
slv := t(arg);
return slv;
end function to_uns;
-- Type convert an "sfixed" into a "signed", used internally
function to_s (
arg : UNRESOLVED_sfixed) -- fp vector
return SIGNED is
subtype t is SIGNED(arg'high - arg'low downto 0);
variable slv : t;
begin -- function to_s
slv := t(arg);
return slv;
end function to_s;
-- adds 1 to the LSB of the number
procedure round_up (arg : in UNRESOLVED_ufixed;
result : out UNRESOLVED_ufixed;
overflowx : out BOOLEAN) is
variable arguns, resuns : UNSIGNED (arg'high-arg'low+1 downto 0)
:= (others => '0');
begin -- round_up
arguns (arguns'high-1 downto 0) := to_uns (arg);
resuns := arguns + 1;
result := to_fixed(resuns(arg'high-arg'low
downto 0), arg'high, arg'low);
overflowx := (resuns(resuns'high) = '1');
end procedure round_up;
-- adds 1 to the LSB of the number
procedure round_up (arg : in UNRESOLVED_sfixed;
result : out UNRESOLVED_sfixed;
overflowx : out BOOLEAN) is
variable args, ress : SIGNED (arg'high-arg'low+1 downto 0);
begin -- round_up
args (args'high-1 downto 0) := to_s (arg);
args(args'high) := arg(arg'high); -- sign extend
ress := args + 1;
result := to_fixed(ress (ress'high-1
downto 0), arg'high, arg'low);
overflowx := ((arg(arg'high) /= ress(ress'high-1))
and (or_reduce (STD_ULOGIC_VECTOR(ress)) /= '0'));
end procedure round_up;
-- Rounding - Performs a "round_nearest" (IEEE 754) which rounds up
-- when the remainder is > 0.5. If the remainder IS 0.5 then if the
-- bottom bit is a "1" it is rounded, otherwise it remains the same.
function round_fixed (arg : UNRESOLVED_ufixed;
remainder : UNRESOLVED_ufixed;
overflow_style : fixed_overflow_style_type := fixed_overflow_style)
return UNRESOLVED_ufixed is
variable rounds : BOOLEAN;
variable round_overflow : BOOLEAN;
variable result : UNRESOLVED_ufixed (arg'range);
begin
rounds := false;
if (remainder'length > 1) then
if (remainder (remainder'high) = '1') then
rounds := (arg(arg'low) = '1')
or (or_reduce (to_sulv(remainder(remainder'high-1 downto
remainder'low))) = '1');
end if;
else
rounds := (arg(arg'low) = '1') and (remainder (remainder'high) = '1');
end if;
if rounds then
round_up(arg => arg,
result => result,
overflowx => round_overflow);
else
result := arg;
end if;
if (overflow_style = fixed_saturate) and round_overflow then
result := saturate (result'high, result'low);
end if;
return result;
end function round_fixed;
-- Rounding case statement
function round_fixed (arg : UNRESOLVED_sfixed;
remainder : UNRESOLVED_sfixed;
overflow_style : fixed_overflow_style_type := fixed_overflow_style)
return UNRESOLVED_sfixed is
variable rounds : BOOLEAN;
variable round_overflow : BOOLEAN;
variable result : UNRESOLVED_sfixed (arg'range);
begin
rounds := false;
if (remainder'length > 1) then
if (remainder (remainder'high) = '1') then
rounds := (arg(arg'low) = '1')
or (or_reduce (to_sulv(remainder(remainder'high-1 downto
remainder'low))) = '1');
end if;
else
rounds := (arg(arg'low) = '1') and (remainder (remainder'high) = '1');
end if;
if rounds then
round_up(arg => arg,
result => result,
overflowx => round_overflow);
else
result := arg;
end if;
if round_overflow then
if (overflow_style = fixed_saturate) then
if arg(arg'high) = '0' then
result := saturate (result'high, result'low);
else
result := not saturate (result'high, result'low);
end if;
-- Sign bit not fixed when wrapping
end if;
end if;
return result;
end function round_fixed;
-- converts an sfixed into a ufixed. The output is the same length as the
-- input, because abs("1000") = "1000" = 8.
function to_ufixed (
arg : UNRESOLVED_sfixed)
return UNRESOLVED_ufixed
is
constant left_index : INTEGER := arg'high;
constant right_index : INTEGER := mine(arg'low, arg'low);
variable xarg : UNRESOLVED_sfixed(left_index+1 downto right_index);
variable result : UNRESOLVED_ufixed(left_index downto right_index);
begin
if arg'length < 1 then
return NAUF;
end if;
xarg := abs(arg);
result := UNRESOLVED_ufixed (xarg (left_index downto right_index));
return result;
end function to_ufixed;
-----------------------------------------------------------------------------
-- Visible functions
-----------------------------------------------------------------------------
-- Conversion functions. These are needed for synthesis where typically
-- the only input and output type is a std_logic_vector.
function to_sulv (
arg : UNRESOLVED_ufixed) -- fixed point vector
return STD_ULOGIC_VECTOR is
variable result : STD_ULOGIC_VECTOR (arg'length-1 downto 0);
begin
if arg'length < 1 then
return NSLV;
end if;
result := STD_ULOGIC_VECTOR (arg);
return result;
end function to_sulv;
function to_sulv (
arg : UNRESOLVED_sfixed) -- fixed point vector
return STD_ULOGIC_VECTOR is
variable result : STD_ULOGIC_VECTOR (arg'length-1 downto 0);
begin
if arg'length < 1 then
return NSLV;
end if;
result := STD_ULOGIC_VECTOR (arg);
return result;
end function to_sulv;
function to_slv (
arg : UNRESOLVED_ufixed) -- fixed point vector
return STD_LOGIC_VECTOR is
begin
return std_logic_vector(arg);---to_stdlogicvector(to_sulv(arg));
end function to_slv;
function to_slv (
arg : UNRESOLVED_sfixed) -- fixed point vector
return STD_LOGIC_VECTOR is
begin
return std_logic_vector(arg);---to_stdlogicvector(to_sulv(arg));
end function to_slv;
function to_ufixed (
arg : STD_ULOGIC_VECTOR; -- shifted vector
constant left_index : INTEGER;
constant right_index : INTEGER)
return unresolved_ufixed is
variable result : UNRESOLVED_ufixed (left_index downto right_index);
begin
if (arg'length < 1 or right_index > left_index) then
return NAUF;
end if;
if (arg'length /= result'length) then
report "fixed_pkg" & "TO_UFIXED(SLV) "
& "Vector lengths do not match. Input length is "
& INTEGER'image(arg'length) & " and output will be "
& INTEGER'image(result'length) & " wide."
severity error;
return NAUF;
else
result := to_fixed (arg => UNSIGNED(arg),
left_index => left_index,
right_index => right_index);
return result;
end if;
end function to_ufixed;
function to_sfixed (
arg : STD_ULOGIC_VECTOR; -- shifted vector
constant left_index : INTEGER;
constant right_index : INTEGER)
return unresolved_sfixed is
variable result : UNRESOLVED_sfixed (left_index downto right_index);
begin
if (arg'length < 1 or right_index > left_index) then
return NASF;
end if;
if (arg'length /= result'length) then
report "fixed_pkg" & "TO_SFIXED(SLV) "
& "Vector lengths do not match. Input length is "
& INTEGER'image(arg'length) & " and output will be "
& INTEGER'image(result'length) & " wide."
severity error;
return NASF;
else
result := to_fixed (arg => SIGNED(arg),
left_index => left_index,
right_index => right_index);
return result;
end if;
end function to_sfixed;
-- Two's complement number, Grows the vector by 1 bit.
-- because "abs (1000.000) = 01000.000" or abs(-16) = 16.
function "abs" (
arg : UNRESOLVED_sfixed) -- fixed point input
return UNRESOLVED_sfixed is
constant left_index : INTEGER := arg'high;
constant right_index : INTEGER := mine(arg'low, arg'low);
variable ressns : SIGNED (arg'length downto 0);
variable result : UNRESOLVED_sfixed (left_index+1 downto right_index);
begin
if (arg'length < 1 or result'length < 1) then
return NASF;
end if;
ressns (arg'length-1 downto 0) := to_s (cleanvec (arg));
ressns (arg'length) := ressns (arg'length-1); -- expand sign bit
result := to_fixed (abs(ressns), left_index+1, right_index);
return result;
end function "abs";
-- also grows the vector by 1 bit.
function "-" (
arg : UNRESOLVED_sfixed) -- fixed point input
return UNRESOLVED_sfixed is
constant left_index : INTEGER := arg'high+1;
constant right_index : INTEGER := mine(arg'low, arg'low);
variable ressns : SIGNED (arg'length downto 0);
variable result : UNRESOLVED_sfixed (left_index downto right_index);
begin
if (arg'length < 1 or result'length < 1) then
return NASF;
end if;
ressns (arg'length-1 downto 0) := to_s (cleanvec(arg));
ressns (arg'length) := ressns (arg'length-1); -- expand sign bit
result := to_fixed (-ressns, left_index, right_index);
return result;
end function "-";
-- Addition
function "+" (
l, r : UNRESOLVED_ufixed) -- ufixed(a downto b) + ufixed(c downto d) =
return UNRESOLVED_ufixed is -- ufixed(max(a,c)+1 downto min(b,d))
constant left_index : INTEGER := maximum(l'high, r'high)+1;
constant right_index : INTEGER := mine(l'low, r'low);
variable lresize, rresize : UNRESOLVED_ufixed (left_index downto right_index);
variable result : UNRESOLVED_ufixed (left_index downto right_index);
variable lslv, rslv : UNSIGNED (left_index-right_index
downto 0);
variable result_slv : UNSIGNED (left_index-right_index
downto 0);
begin
if (l'length < 1 or r'length < 1 or result'length < 1) then
return NAUF;
end if;
lresize := resize (l, left_index, right_index);
rresize := resize (r, left_index, right_index);
lslv := to_uns (lresize);
rslv := to_uns (rresize);
result_slv := lslv + rslv;
result := to_fixed(result_slv, left_index, right_index);
return result;
end function "+";
function "+" (
l, r : UNRESOLVED_sfixed) -- sfixed(a downto b) + sfixed(c downto d) =
return UNRESOLVED_sfixed is -- sfixed(max(a,c)+1 downto min(b,d))
constant left_index : INTEGER := maximum(l'high, r'high)+1;
constant right_index : INTEGER := mine(l'low, r'low);
variable lresize, rresize : UNRESOLVED_sfixed (left_index downto right_index);
variable result : UNRESOLVED_sfixed (left_index downto right_index);
variable lslv, rslv : SIGNED (left_index-right_index downto 0);
variable result_slv : SIGNED (left_index-right_index downto 0);
begin
if (l'length < 1 or r'length < 1 or result'length < 1) then
return NASF;
end if;
lresize := resize (l, left_index, right_index);
rresize := resize (r, left_index, right_index);
lslv := to_s (lresize);
rslv := to_s (rresize);
result_slv := lslv + rslv;
result := to_fixed(result_slv, left_index, right_index);
return result;
end function "+";
-- Subtraction
function "-" (
l, r : UNRESOLVED_ufixed) -- ufixed(a downto b) - ufixed(c downto d) =
return UNRESOLVED_ufixed is -- ufixed(max(a,c)+1 downto min(b,d))
constant left_index : INTEGER := maximum(l'high, r'high)+1;
constant right_index : INTEGER := mine(l'low, r'low);
variable lresize, rresize : UNRESOLVED_ufixed (left_index downto right_index);
variable result : UNRESOLVED_ufixed (left_index downto right_index);
variable lslv, rslv : UNSIGNED (left_index-right_index
downto 0);
variable result_slv : UNSIGNED (left_index-right_index
downto 0);
begin
if (l'length < 1 or r'length < 1 or result'length < 1) then
return NAUF;
end if;
lresize := resize (l, left_index, right_index);
rresize := resize (r, left_index, right_index);
lslv := to_uns (lresize);
rslv := to_uns (rresize);
result_slv := lslv - rslv;
result := to_fixed(result_slv, left_index, right_index);
return result;
end function "-";
function "-" (
l, r : UNRESOLVED_sfixed) -- sfixed(a downto b) - sfixed(c downto d) =
return UNRESOLVED_sfixed is -- sfixed(max(a,c)+1 downto min(b,d))
constant left_index : INTEGER := maximum(l'high, r'high)+1;
constant right_index : INTEGER := mine(l'low, r'low);
variable lresize, rresize : UNRESOLVED_sfixed (left_index downto right_index);
variable result : UNRESOLVED_sfixed (left_index downto right_index);
variable lslv, rslv : SIGNED (left_index-right_index downto 0);
variable result_slv : SIGNED (left_index-right_index downto 0);
begin
if (l'length < 1 or r'length < 1 or result'length < 1) then
return NASF;
end if;
lresize := resize (l, left_index, right_index);
rresize := resize (r, left_index, right_index);
lslv := to_s (lresize);
rslv := to_s (rresize);
result_slv := lslv - rslv;
result := to_fixed(result_slv, left_index, right_index);
return result;
end function "-";
function "*" (
l, r : UNRESOLVED_ufixed) -- ufixed(a downto b) * ufixed(c downto d) =
return UNRESOLVED_ufixed is -- ufixed(a+c+1 downto b+d)
variable lslv : UNSIGNED (l'length-1 downto 0);
variable rslv : UNSIGNED (r'length-1 downto 0);
variable result_slv : UNSIGNED (r'length+l'length-1 downto 0);
variable result : UNRESOLVED_ufixed (l'high + r'high+1 downto
mine(l'low, l'low) + mine(r'low, r'low));
begin
if (l'length < 1 or r'length < 1 or
result'length /= result_slv'length) then
return NAUF;
end if;
lslv := to_uns (cleanvec(l));
rslv := to_uns (cleanvec(r));
result_slv := lslv * rslv;
result := to_fixed (result_slv, result'high, result'low);
return result;
end function "*";
function "*" (
l, r : UNRESOLVED_sfixed) -- sfixed(a downto b) * sfixed(c downto d) =
return UNRESOLVED_sfixed is -- sfixed(a+c+1 downto b+d)
variable lslv : SIGNED (l'length-1 downto 0);
variable rslv : SIGNED (r'length-1 downto 0);
variable result_slv : SIGNED (r'length+l'length-1 downto 0);
variable result : UNRESOLVED_sfixed (l'high + r'high+1 downto
mine(l'low, l'low) + mine(r'low, r'low));
begin
if (l'length < 1 or r'length < 1 or
result'length /= result_slv'length) then
return NASF;
end if;
lslv := to_s (cleanvec(l));
rslv := to_s (cleanvec(r));
result_slv := lslv * rslv;
result := to_fixed (result_slv, result'high, result'low);
return result;
end function "*";
function "/" (
l, r : UNRESOLVED_ufixed) -- ufixed(a downto b) / ufixed(c downto d) =
return UNRESOLVED_ufixed is -- ufixed(a-d downto b-c-1)
begin
return divide (l, r);
end function "/";
function "/" (
l, r : UNRESOLVED_sfixed) -- sfixed(a downto b) / sfixed(c downto d) =
return UNRESOLVED_sfixed is -- sfixed(a-d+1 downto b-c)
begin
return divide (l, r);
end function "/";
-- This version of divide gives the user more control
-- ufixed(a downto b) / ufixed(c downto d) = ufixed(a-d downto b-c-1)
function divide (
l, r : UNRESOLVED_ufixed;
constant round_style : fixed_round_style_type := fixed_round_style;
constant guard_bits : NATURAL := fixed_guard_bits)
return UNRESOLVED_ufixed is
variable result : UNRESOLVED_ufixed (l'high - mine(r'low, r'low) downto
mine (l'low, l'low) - r'high -1);
variable dresult : UNRESOLVED_ufixed (result'high downto result'low -guard_bits);
variable lresize : UNRESOLVED_ufixed (l'high downto l'high - dresult'length+1);
variable lslv : UNSIGNED (lresize'length-1 downto 0);
variable rslv : UNSIGNED (r'length-1 downto 0);
variable result_slv : UNSIGNED (lresize'length-1 downto 0);
begin
if (l'length < 1 or r'length < 1 or
mins(r'low, r'low) /= r'low or mins(l'low, l'low) /= l'low) then
return NAUF;
end if;
lresize := resize (arg => l,
left_index => lresize'high,
right_index => lresize'low,
overflow_style => fixed_wrap, -- vector only grows
round_style => fixed_truncate);
lslv := to_uns (cleanvec (lresize));
rslv := to_uns (cleanvec (r));
if (rslv = 0) then
report "fixed_pkg"
& "DIVIDE(ufixed) Division by zero" severity error;
result := saturate (result'high, result'low); -- saturate
else
result_slv := lslv / rslv;
dresult := to_fixed (result_slv, dresult'high, dresult'low);
result := resize (arg => dresult,
left_index => result'high,
right_index => result'low,
overflow_style => fixed_wrap, -- overflow impossible
round_style => round_style);
end if;
return result;
end function divide;
-- sfixed(a downto b) / sfixed(c downto d) = sfixed(a-d+1 downto b-c)
function divide (
l, r : UNRESOLVED_sfixed;
constant round_style : fixed_round_style_type := fixed_round_style;
constant guard_bits : NATURAL := fixed_guard_bits)
return UNRESOLVED_sfixed is
variable result : UNRESOLVED_sfixed (l'high - mine(r'low, r'low) + 1 downto
mine (l'low, l'low) - r'high);
variable dresult : UNRESOLVED_sfixed (result'high downto result'low-guard_bits);
variable lresize : UNRESOLVED_sfixed (l'high+1 downto l'high+1 -dresult'length+1);
variable lslv : SIGNED (lresize'length-1 downto 0);
variable rslv : SIGNED (r'length-1 downto 0);
variable result_slv : SIGNED (lresize'length-1 downto 0);
begin
if (l'length < 1 or r'length < 1 or
mins(r'low, r'low) /= r'low or mins(l'low, l'low) /= l'low) then
return NASF;
end if;
lresize := resize (arg => l,
left_index => lresize'high,
right_index => lresize'low,
overflow_style => fixed_wrap, -- vector only grows
round_style => fixed_truncate);
lslv := to_s (cleanvec (lresize));
rslv := to_s (cleanvec (r));
if (rslv = 0) then
report "fixed_pkg"
& "DIVIDE(sfixed) Division by zero" severity error;
result := saturate (result'high, result'low);
else
result_slv := lslv / rslv;
dresult := to_fixed (result_slv, dresult'high, dresult'low);
result := resize (arg => dresult,
left_index => result'high,
right_index => result'low,
overflow_style => fixed_wrap, -- overflow impossible
round_style => round_style);
end if;
return result;
end function divide;
-- 1 / ufixed(a downto b) = ufixed(-b downto -a-1)
function reciprocal (
arg : UNRESOLVED_ufixed; -- fixed point input
constant round_style : fixed_round_style_type := fixed_round_style;
constant guard_bits : NATURAL := fixed_guard_bits)
return UNRESOLVED_ufixed is
constant one : UNRESOLVED_ufixed (0 downto 0) := "1";
begin
return divide (l => one,
r => arg,
round_style => round_style,
guard_bits => guard_bits);
end function reciprocal;
-- 1 / sfixed(a downto b) = sfixed(-b+1 downto -a)
function reciprocal (
arg : UNRESOLVED_sfixed; -- fixed point input
constant round_style : fixed_round_style_type := fixed_round_style;
constant guard_bits : NATURAL := fixed_guard_bits)
return UNRESOLVED_sfixed is
constant one : UNRESOLVED_sfixed (1 downto 0) := "01"; -- extra bit.
variable resultx : UNRESOLVED_sfixed (-mine(arg'low, arg'low)+2 downto -arg'high);
begin
if (arg'length < 1 or resultx'length < 1) then
return NASF;
else
resultx := divide (l => one,
r => arg,
round_style => round_style,
guard_bits => guard_bits);
return resultx (resultx'high-1 downto resultx'low); -- remove extra bit
end if;
end function reciprocal;
-- ufixed (a downto b) rem ufixed (c downto d)
-- = ufixed (min(a,c) downto min(b,d))
function "rem" (
l, r : UNRESOLVED_ufixed) -- fixed point input
return UNRESOLVED_ufixed is
begin
return remainder (l, r);
end function "rem";
-- remainder
-- sfixed (a downto b) rem sfixed (c downto d)
-- = sfixed (min(a,c) downto min(b,d))
function "rem" (
l, r : UNRESOLVED_sfixed) -- fixed point input
return UNRESOLVED_sfixed is
begin
return remainder (l, r);
end function "rem";
-- ufixed (a downto b) rem ufixed (c downto d)
-- = ufixed (min(a,c) downto min(b,d))
function remainder (
l, r : UNRESOLVED_ufixed; -- fixed point input
constant round_style : fixed_round_style_type := fixed_round_style;
constant guard_bits : NATURAL := fixed_guard_bits)
return UNRESOLVED_ufixed is
variable result : UNRESOLVED_ufixed (minimum(l'high, r'high) downto
mine(l'low, r'low));
variable lresize : UNRESOLVED_ufixed (maximum(l'high, r'low) downto
mins(r'low, r'low)-guard_bits);
variable rresize : UNRESOLVED_ufixed (r'high downto r'low-guard_bits);
variable dresult : UNRESOLVED_ufixed (rresize'range);
variable lslv : UNSIGNED (lresize'length-1 downto 0);
variable rslv : UNSIGNED (rresize'length-1 downto 0);
variable result_slv : UNSIGNED (rslv'range);
begin
if (l'length < 1 or r'length < 1 or
mins(r'low, r'low) /= r'low or mins(l'low, l'low) /= l'low) then
return NAUF;
end if;
lresize := resize (arg => l,
left_index => lresize'high,
right_index => lresize'low,
overflow_style => fixed_wrap, -- vector only grows
round_style => fixed_truncate);
lslv := to_uns (lresize);
rresize := resize (arg => r,
left_index => rresize'high,
right_index => rresize'low,
overflow_style => fixed_wrap, -- vector only grows
round_style => fixed_truncate);
rslv := to_uns (rresize);
if (rslv = 0) then
report "fixed_pkg"
& "remainder(ufixed) Division by zero" severity error;
result := saturate (result'high, result'low); -- saturate
else
if (r'low <= l'high) then
result_slv := lslv rem rslv;
dresult := to_fixed (result_slv, dresult'high, dresult'low);
result := resize (arg => dresult,
left_index => result'high,
right_index => result'low,
overflow_style => fixed_wrap, -- can't overflow
round_style => round_style);
end if;
if l'low < r'low then
result(mins(r'low-1, l'high) downto l'low) :=
cleanvec(l(mins(r'low-1, l'high) downto l'low));
end if;
end if;
return result;
end function remainder;
-- remainder
-- sfixed (a downto b) rem sfixed (c downto d)
-- = sfixed (min(a,c) downto min(b,d))
function remainder (
l, r : UNRESOLVED_sfixed; -- fixed point input
constant round_style : fixed_round_style_type := fixed_round_style;
constant guard_bits : NATURAL := fixed_guard_bits)
return UNRESOLVED_sfixed is
variable l_abs : UNRESOLVED_ufixed (l'range);
variable r_abs : UNRESOLVED_ufixed (r'range);
variable result : UNRESOLVED_sfixed (minimum(r'high, l'high) downto
mine(r'low, l'low));
variable neg_result : UNRESOLVED_sfixed (minimum(r'high, l'high)+1 downto
mins(r'low, l'low));
begin
if (l'length < 1 or r'length < 1 or
mins(r'low, r'low) /= r'low or mins(l'low, l'low) /= l'low) then
return NASF;
end if;
l_abs := to_ufixed (l);
r_abs := to_ufixed (r);
result := UNRESOLVED_sfixed (remainder (
l => l_abs,
r => r_abs,
round_style => round_style));
neg_result := -result;
if l(l'high) = '1' then
result := neg_result(result'range);
end if;
return result;
end function remainder;
-- modulo
-- ufixed (a downto b) mod ufixed (c downto d)
-- = ufixed (min(a,c) downto min(b, d))
function "mod" (
l, r : UNRESOLVED_ufixed) -- fixed point input
return UNRESOLVED_ufixed is
begin
return modulo (l, r);
end function "mod";
-- sfixed (a downto b) mod sfixed (c downto d)
-- = sfixed (c downto min(b, d))
function "mod" (
l, r : UNRESOLVED_sfixed) -- fixed point input
return UNRESOLVED_sfixed is
begin
return modulo(l, r);
end function "mod";
-- modulo
-- ufixed (a downto b) mod ufixed (c downto d)
-- = ufixed (min(a,c) downto min(b, d))
function modulo (
l, r : UNRESOLVED_ufixed; -- fixed point input
constant round_style : fixed_round_style_type := fixed_round_style;
constant guard_bits : NATURAL := fixed_guard_bits)
return UNRESOLVED_ufixed is
begin
return remainder(l => l,
r => r,
round_style => round_style,
guard_bits => guard_bits);
end function modulo;
-- sfixed (a downto b) mod sfixed (c downto d)
-- = sfixed (c downto min(b, d))
function modulo (
l, r : UNRESOLVED_sfixed; -- fixed point input
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;
constant round_style : fixed_round_style_type := fixed_round_style;
constant guard_bits : NATURAL := fixed_guard_bits)
return UNRESOLVED_sfixed is
variable l_abs : UNRESOLVED_ufixed (l'range);
variable r_abs : UNRESOLVED_ufixed (r'range);
variable result : UNRESOLVED_sfixed (r'high downto
mine(r'low, l'low));
variable dresult : UNRESOLVED_sfixed (minimum(r'high, l'high)+1 downto
mins(r'low, l'low));
variable dresult_not_zero : BOOLEAN;
begin
if (l'length < 1 or r'length < 1 or
mins(r'low, r'low) /= r'low or mins(l'low, l'low) /= l'low) then
return NASF;
end if;
l_abs := to_ufixed (l);
r_abs := to_ufixed (r);
dresult := "0" & UNRESOLVED_sfixed(remainder (l => l_abs,
r => r_abs,
round_style => round_style));
if (to_s(dresult) = 0) then
dresult_not_zero := false;
else
dresult_not_zero := true;
end if;
if to_x01(l(l'high)) = '1' and to_x01(r(r'high)) = '0'
and dresult_not_zero then
result := resize (arg => r - dresult,
left_index => result'high,
right_index => result'low,
overflow_style => overflow_style,
round_style => round_style);
elsif to_x01(l(l'high)) = '1' and to_x01(r(r'high)) = '1' then
result := resize (arg => -dresult,
left_index => result'high,
right_index => result'low,
overflow_style => overflow_style,
round_style => round_style);
elsif to_x01(l(l'high)) = '0' and to_x01(r(r'high)) = '1'
and dresult_not_zero then
result := resize (arg => dresult + r,
left_index => result'high,
right_index => result'low,
overflow_style => overflow_style,
round_style => round_style);
else
result := resize (arg => dresult,
left_index => result'high,
right_index => result'low,
overflow_style => overflow_style,
round_style => round_style);
end if;
return result;
end function modulo;
-- Procedure for those who need an "accumulator" function
procedure add_carry (
L, R : in UNRESOLVED_ufixed;
c_in : in STD_ULOGIC;
result : out UNRESOLVED_ufixed;
c_out : out STD_ULOGIC) is
constant left_index : INTEGER := maximum(l'high, r'high)+1;
constant right_index : INTEGER := mins(l'low, r'low);
variable lresize, rresize : UNRESOLVED_ufixed (left_index downto right_index);
variable lslv, rslv : UNSIGNED (left_index-right_index
downto 0);
variable result_slv : UNSIGNED (left_index-right_index
downto 0);
variable cx : UNSIGNED (0 downto 0); -- Carry in
begin
if (l'length < 1 or r'length < 1) then
result := NAUF;
c_out := '0';
else
cx (0) := c_in;
lresize := resize (l, left_index, right_index);
rresize := resize (r, left_index, right_index);
lslv := to_uns (lresize);
rslv := to_uns (rresize);
result_slv := lslv + rslv + cx;
c_out := result_slv(left_index);
result := to_fixed(result_slv (left_index-right_index-1 downto 0),
left_index-1, right_index);
end if;
end procedure add_carry;
procedure add_carry (
L, R : in UNRESOLVED_sfixed;
c_in : in STD_ULOGIC;
result : out UNRESOLVED_sfixed;
c_out : out STD_ULOGIC) is
constant left_index : INTEGER := maximum(l'high, r'high)+1;
constant right_index : INTEGER := mins(l'low, r'low);
variable lresize, rresize : UNRESOLVED_sfixed (left_index downto right_index);
variable lslv, rslv : SIGNED (left_index-right_index
downto 0);
variable result_slv : SIGNED (left_index-right_index
downto 0);
variable cx : SIGNED (1 downto 0); -- Carry in
begin
if (l'length < 1 or r'length < 1) then
result := NASF;
c_out := '0';
else
cx (1) := '0';
cx (0) := c_in;
lresize := resize (l, left_index, right_index);
rresize := resize (r, left_index, right_index);
lslv := to_s (lresize);
rslv := to_s (rresize);
result_slv := lslv + rslv + cx;
c_out := result_slv(left_index);
result := to_fixed(result_slv (left_index-right_index-1 downto 0),
left_index-1, right_index);
end if;
end procedure add_carry;
-- Scales the result by a power of 2. Width of input = width of output with
-- the decimal point moved.
function scalb (y : UNRESOLVED_ufixed; N : INTEGER)
return UNRESOLVED_ufixed is
variable result : UNRESOLVED_ufixed (y'high+N downto y'low+N);
begin
if y'length < 1 then
return NAUF;
else
result := y;
return result;
end if;
end function scalb;
function scalb (y : UNRESOLVED_ufixed; N : SIGNED)
return UNRESOLVED_ufixed is
begin
return scalb (y => y,
N => to_integer(N));
end function scalb;
function scalb (y : UNRESOLVED_sfixed; N : INTEGER)
return UNRESOLVED_sfixed is
variable result : UNRESOLVED_sfixed (y'high+N downto y'low+N);
begin
if y'length < 1 then
return NASF;
else
result := y;
return result;
end if;
end function scalb;
function scalb (y : UNRESOLVED_sfixed; N : SIGNED)
return UNRESOLVED_sfixed is
begin
return scalb (y => y,
N => to_integer(N));
end function scalb;
function Is_Negative (arg : UNRESOLVED_sfixed) return BOOLEAN is
begin
if to_X01(arg(arg'high)) = '1' then
return true;
else
return false;
end if;
end function Is_Negative;
function find_rightmost (arg : UNRESOLVED_ufixed; y : STD_ULOGIC)
return INTEGER is
begin
for_loop : for i in arg'reverse_range loop
if \?=\ (arg(i), y) = '1' then
return i;
end if;
end loop;
return arg'high+1; -- return out of bounds 'high
end function find_rightmost;
function find_leftmost (arg : UNRESOLVED_ufixed; y : STD_ULOGIC)
return INTEGER is
begin
for_loop : for i in arg'range loop
if \?=\ (arg(i), y) = '1' then
return i;
end if;
end loop;
return arg'low-1; -- return out of bounds 'low
end function find_leftmost;
function find_rightmost (arg : UNRESOLVED_sfixed; y : STD_ULOGIC)
return INTEGER is
begin
for_loop : for i in arg'reverse_range loop
if \?=\ (arg(i), y) = '1' then
return i;
end if;
end loop;
return arg'high+1; -- return out of bounds 'high
end function find_rightmost;
function find_leftmost (arg : UNRESOLVED_sfixed; y : STD_ULOGIC)
return INTEGER is
begin
for_loop : for i in arg'range loop
if \?=\ (arg(i), y) = '1' then
return i;
end if;
end loop;
return arg'low-1; -- return out of bounds 'low
end function find_leftmost;
function "sll" (ARG : UNRESOLVED_ufixed; COUNT : INTEGER)
return UNRESOLVED_ufixed is
variable argslv : UNSIGNED (arg'length-1 downto 0);
variable result : UNRESOLVED_ufixed (arg'range);
begin
argslv := to_uns (arg);
argslv := argslv sll COUNT;
result := to_fixed (argslv, result'high, result'low);
return result;
end function "sll";
function "srl" (ARG : UNRESOLVED_ufixed; COUNT : INTEGER)
return UNRESOLVED_ufixed is
variable argslv : UNSIGNED (arg'length-1 downto 0);
variable result : UNRESOLVED_ufixed (arg'range);
begin
argslv := to_uns (arg);
argslv := argslv srl COUNT;
result := to_fixed (argslv, result'high, result'low);
return result;
end function "srl";
function "rol" (ARG : UNRESOLVED_ufixed; COUNT : INTEGER)
return UNRESOLVED_ufixed is
variable argslv : UNSIGNED (arg'length-1 downto 0);
variable result : UNRESOLVED_ufixed (arg'range);
begin
argslv := to_uns (arg);
argslv := argslv rol COUNT;
result := to_fixed (argslv, result'high, result'low);
return result;
end function "rol";
function "ror" (ARG : UNRESOLVED_ufixed; COUNT : INTEGER)
return UNRESOLVED_ufixed is
variable argslv : UNSIGNED (arg'length-1 downto 0);
variable result : UNRESOLVED_ufixed (arg'range);
begin
argslv := to_uns (arg);
argslv := argslv ror COUNT;
result := to_fixed (argslv, result'high, result'low);
return result;
end function "ror";
function "sla" (ARG : UNRESOLVED_ufixed; COUNT : INTEGER)
return UNRESOLVED_ufixed is
variable argslv : UNSIGNED (arg'length-1 downto 0);
variable result : UNRESOLVED_ufixed (arg'range);
begin
argslv := to_uns (arg);
-- Arithmetic shift on an unsigned is a logical shift
argslv := argslv sll COUNT;
result := to_fixed (argslv, result'high, result'low);
return result;
end function "sla";
function "sra" (ARG : UNRESOLVED_ufixed; COUNT : INTEGER)
return UNRESOLVED_ufixed is
variable argslv : UNSIGNED (arg'length-1 downto 0);
variable result : UNRESOLVED_ufixed (arg'range);
begin
argslv := to_uns (arg);
-- Arithmetic shift on an unsigned is a logical shift
argslv := argslv srl COUNT;
result := to_fixed (argslv, result'high, result'low);
return result;
end function "sra";
function "sll" (ARG : UNRESOLVED_sfixed; COUNT : INTEGER)
return UNRESOLVED_sfixed is
variable argslv : SIGNED (arg'length-1 downto 0);
variable result : UNRESOLVED_sfixed (arg'range);
begin
argslv := to_s (arg);
argslv := argslv sll COUNT;
result := to_fixed (argslv, result'high, result'low);
return result;
end function "sll";
function "srl" (ARG : UNRESOLVED_sfixed; COUNT : INTEGER)
return UNRESOLVED_sfixed is
variable argslv : SIGNED (arg'length-1 downto 0);
variable result : UNRESOLVED_sfixed (arg'range);
begin
argslv := to_s (arg);
argslv := argslv srl COUNT;
result := to_fixed (argslv, result'high, result'low);
return result;
end function "srl";
function "rol" (ARG : UNRESOLVED_sfixed; COUNT : INTEGER)
return UNRESOLVED_sfixed is
variable argslv : SIGNED (arg'length-1 downto 0);
variable result : UNRESOLVED_sfixed (arg'range);
begin
argslv := to_s (arg);
argslv := argslv rol COUNT;
result := to_fixed (argslv, result'high, result'low);
return result;
end function "rol";
function "ror" (ARG : UNRESOLVED_sfixed; COUNT : INTEGER)
return UNRESOLVED_sfixed is
variable argslv : SIGNED (arg'length-1 downto 0);
variable result : UNRESOLVED_sfixed (arg'range);
begin
argslv := to_s (arg);
argslv := argslv ror COUNT;
result := to_fixed (argslv, result'high, result'low);
return result;
end function "ror";
function "sla" (ARG : UNRESOLVED_sfixed; COUNT : INTEGER)
return UNRESOLVED_sfixed is
variable argslv : SIGNED (arg'length-1 downto 0);
variable result : UNRESOLVED_sfixed (arg'range);
begin
argslv := to_s (arg);
if COUNT > 0 then
-- Arithmetic shift left on a 2's complement number is a logic shift
argslv := argslv sll COUNT;
else
argslv := argslv sra -COUNT;
end if;
result := to_fixed (argslv, result'high, result'low);
return result;
end function "sla";
function "sra" (ARG : UNRESOLVED_sfixed; COUNT : INTEGER)
return UNRESOLVED_sfixed is
variable argslv : SIGNED (arg'length-1 downto 0);
variable result : UNRESOLVED_sfixed (arg'range);
begin
argslv := to_s (arg);
if COUNT > 0 then
argslv := argslv sra COUNT;
else
-- Arithmetic shift left on a 2's complement number is a logic shift
argslv := argslv sll -COUNT;
end if;
result := to_fixed (argslv, result'high, result'low);
return result;
end function "sra";
-- Because some people want the older functions.
function SHIFT_LEFT (ARG : UNRESOLVED_ufixed; COUNT : NATURAL)
return UNRESOLVED_ufixed is
begin
if (ARG'length < 1) then
return NAUF;
end if;
return ARG sla COUNT;
end function SHIFT_LEFT;
function SHIFT_RIGHT (ARG : UNRESOLVED_ufixed; COUNT : NATURAL)
return UNRESOLVED_ufixed is
begin
if (ARG'length < 1) then
return NAUF;
end if;
return ARG sra COUNT;
end function SHIFT_RIGHT;
function SHIFT_LEFT (ARG : UNRESOLVED_sfixed; COUNT : NATURAL)
return UNRESOLVED_sfixed is
begin
if (ARG'length < 1) then
return NASF;
end if;
return ARG sla COUNT;
end function SHIFT_LEFT;
function SHIFT_RIGHT (ARG : UNRESOLVED_sfixed; COUNT : NATURAL)
return UNRESOLVED_sfixed is
begin
if (ARG'length < 1) then
return NASF;
end if;
return ARG sra COUNT;
end function SHIFT_RIGHT;
----------------------------------------------------------------------------
-- logical functions
----------------------------------------------------------------------------
function "not" (L : UNRESOLVED_ufixed) return UNRESOLVED_ufixed is
variable RESULT : STD_ULOGIC_VECTOR(L'length-1 downto 0); -- force downto
begin
RESULT := not to_sulv(L);
return to_ufixed(RESULT, L'high, L'low);
end function "not";
function "and" (L, R : UNRESOLVED_ufixed) return UNRESOLVED_ufixed is
variable RESULT : STD_ULOGIC_VECTOR(L'length-1 downto 0); -- force downto
begin
if (L'high = R'high and L'low = R'low) then
RESULT := to_sulv(L) and to_sulv(R);
else
assert NO_WARNING
report "fixed_pkg"
& """and"": Range error L'RANGE /= R'RANGE"
severity warning;
RESULT := (others => 'X');
end if;
return to_ufixed(RESULT, L'high, L'low);
end function "and";
function "or" (L, R : UNRESOLVED_ufixed) return UNRESOLVED_ufixed is
variable RESULT : STD_ULOGIC_VECTOR(L'length-1 downto 0); -- force downto
begin
if (L'high = R'high and L'low = R'low) then
RESULT := to_sulv(L) or to_sulv(R);
else
assert NO_WARNING
report "fixed_pkg"
& """or"": Range error L'RANGE /= R'RANGE"
severity warning;
RESULT := (others => 'X');
end if;
return to_ufixed(RESULT, L'high, L'low);
end function "or";
function "nand" (L, R : UNRESOLVED_ufixed) return UNRESOLVED_ufixed is
variable RESULT : STD_ULOGIC_VECTOR(L'length-1 downto 0); -- force downto
begin
if (L'high = R'high and L'low = R'low) then
RESULT := to_sulv(L) nand to_sulv(R);
else
assert NO_WARNING
report "fixed_pkg"
& """nand"": Range error L'RANGE /= R'RANGE"
severity warning;
RESULT := (others => 'X');
end if;
return to_ufixed(RESULT, L'high, L'low);
end function "nand";
function "nor" (L, R : UNRESOLVED_ufixed) return UNRESOLVED_ufixed is
variable RESULT : STD_ULOGIC_VECTOR(L'length-1 downto 0); -- force downto
begin
if (L'high = R'high and L'low = R'low) then
RESULT := to_sulv(L) nor to_sulv(R);
else
assert NO_WARNING
report "fixed_pkg"
& """nor"": Range error L'RANGE /= R'RANGE"
severity warning;
RESULT := (others => 'X');
end if;
return to_ufixed(RESULT, L'high, L'low);
end function "nor";
function "xor" (L, R : UNRESOLVED_ufixed) return UNRESOLVED_ufixed is
variable RESULT : STD_ULOGIC_VECTOR(L'length-1 downto 0); -- force downto
begin
if (L'high = R'high and L'low = R'low) then
RESULT := to_sulv(L) xor to_sulv(R);
else
assert NO_WARNING
report "fixed_pkg"
& """xor"": Range error L'RANGE /= R'RANGE"
severity warning;
RESULT := (others => 'X');
end if;
return to_ufixed(RESULT, L'high, L'low);
end function "xor";
function "xnor" (L, R : UNRESOLVED_ufixed) return UNRESOLVED_ufixed is
variable RESULT : STD_ULOGIC_VECTOR(L'length-1 downto 0); -- force downto
begin
if (L'high = R'high and L'low = R'low) then
RESULT := to_sulv(L) xnor to_sulv(R);
else
assert NO_WARNING
report "fixed_pkg"
& """xnor"": Range error L'RANGE /= R'RANGE"
severity warning;
RESULT := (others => 'X');
end if;
return to_ufixed(RESULT, L'high, L'low);
end function "xnor";
function "not" (L : UNRESOLVED_sfixed) return UNRESOLVED_sfixed is
variable RESULT : STD_ULOGIC_VECTOR(L'length-1 downto 0); -- force downto
begin
RESULT := not to_sulv(L);
return to_sfixed(RESULT, L'high, L'low);
end function "not";
function "and" (L, R : UNRESOLVED_sfixed) return UNRESOLVED_sfixed is
variable RESULT : STD_ULOGIC_VECTOR(L'length-1 downto 0); -- force downto
begin
if (L'high = R'high and L'low = R'low) then
RESULT := to_sulv(L) and to_sulv(R);
else
assert NO_WARNING
report "fixed_pkg"
& """and"": Range error L'RANGE /= R'RANGE"
severity warning;
RESULT := (others => 'X');
end if;
return to_sfixed(RESULT, L'high, L'low);
end function "and";
function "or" (L, R : UNRESOLVED_sfixed) return UNRESOLVED_sfixed is
variable RESULT : STD_ULOGIC_VECTOR(L'length-1 downto 0); -- force downto
begin
if (L'high = R'high and L'low = R'low) then
RESULT := to_sulv(L) or to_sulv(R);
else
assert NO_WARNING
report "fixed_pkg"
& """or"": Range error L'RANGE /= R'RANGE"
severity warning;
RESULT := (others => 'X');
end if;
return to_sfixed(RESULT, L'high, L'low);
end function "or";
function "nand" (L, R : UNRESOLVED_sfixed) return UNRESOLVED_sfixed is
variable RESULT : STD_ULOGIC_VECTOR(L'length-1 downto 0); -- force downto
begin
if (L'high = R'high and L'low = R'low) then
RESULT := to_sulv(L) nand to_sulv(R);
else
assert NO_WARNING
report "fixed_pkg"
& """nand"": Range error L'RANGE /= R'RANGE"
severity warning;
RESULT := (others => 'X');
end if;
return to_sfixed(RESULT, L'high, L'low);
end function "nand";
function "nor" (L, R : UNRESOLVED_sfixed) return UNRESOLVED_sfixed is
variable RESULT : STD_ULOGIC_VECTOR(L'length-1 downto 0); -- force downto
begin
if (L'high = R'high and L'low = R'low) then
RESULT := to_sulv(L) nor to_sulv(R);
else
assert NO_WARNING
report "fixed_pkg"
& """nor"": Range error L'RANGE /= R'RANGE"
severity warning;
RESULT := (others => 'X');
end if;
return to_sfixed(RESULT, L'high, L'low);
end function "nor";
function "xor" (L, R : UNRESOLVED_sfixed) return UNRESOLVED_sfixed is
variable RESULT : STD_ULOGIC_VECTOR(L'length-1 downto 0); -- force downto
begin
if (L'high = R'high and L'low = R'low) then
RESULT := to_sulv(L) xor to_sulv(R);
else
assert NO_WARNING
report "fixed_pkg"
& """xor"": Range error L'RANGE /= R'RANGE"
severity warning;
RESULT := (others => 'X');
end if;
return to_sfixed(RESULT, L'high, L'low);
end function "xor";
function "xnor" (L, R : UNRESOLVED_sfixed) return UNRESOLVED_sfixed is
variable RESULT : STD_ULOGIC_VECTOR(L'length-1 downto 0); -- force downto
begin
if (L'high = R'high and L'low = R'low) then
RESULT := to_sulv(L) xnor to_sulv(R);
else
assert NO_WARNING
report "fixed_pkg"
& """xnor"": Range error L'RANGE /= R'RANGE"
severity warning;
RESULT := (others => 'X');
end if;
return to_sfixed(RESULT, L'high, L'low);
end function "xnor";
-- Vector and std_ulogic functions, same as functions in numeric_std
function "and" (L : STD_ULOGIC; R : UNRESOLVED_ufixed)
return UNRESOLVED_ufixed is
variable result : UNRESOLVED_ufixed (R'range);
begin
for i in result'range loop
result(i) := L and R(i);
end loop;
return result;
end function "and";
function "and" (L : UNRESOLVED_ufixed; R : STD_ULOGIC)
return UNRESOLVED_ufixed is
variable result : UNRESOLVED_ufixed (L'range);
begin
for i in result'range loop
result(i) := L(i) and R;
end loop;
return result;
end function "and";
function "or" (L : STD_ULOGIC; R : UNRESOLVED_ufixed)
return UNRESOLVED_ufixed is
variable result : UNRESOLVED_ufixed (R'range);
begin
for i in result'range loop
result(i) := L or R(i);
end loop;
return result;
end function "or";
function "or" (L : UNRESOLVED_ufixed; R : STD_ULOGIC)
return UNRESOLVED_ufixed is
variable result : UNRESOLVED_ufixed (L'range);
begin
for i in result'range loop
result(i) := L(i) or R;
end loop;
return result;
end function "or";
function "nand" (L : STD_ULOGIC; R : UNRESOLVED_ufixed)
return UNRESOLVED_ufixed is
variable result : UNRESOLVED_ufixed (R'range);
begin
for i in result'range loop
result(i) := L nand R(i);
end loop;
return result;
end function "nand";
function "nand" (L : UNRESOLVED_ufixed; R : STD_ULOGIC)
return UNRESOLVED_ufixed is
variable result : UNRESOLVED_ufixed (L'range);
begin
for i in result'range loop
result(i) := L(i) nand R;
end loop;
return result;
end function "nand";
function "nor" (L : STD_ULOGIC; R : UNRESOLVED_ufixed)
return UNRESOLVED_ufixed is
variable result : UNRESOLVED_ufixed (R'range);
begin
for i in result'range loop
result(i) := L nor R(i);
end loop;
return result;
end function "nor";
function "nor" (L : UNRESOLVED_ufixed; R : STD_ULOGIC)
return UNRESOLVED_ufixed is
variable result : UNRESOLVED_ufixed (L'range);
begin
for i in result'range loop
result(i) := L(i) nor R;
end loop;
return result;
end function "nor";
function "xor" (L : STD_ULOGIC; R : UNRESOLVED_ufixed)
return UNRESOLVED_ufixed is
variable result : UNRESOLVED_ufixed (R'range);
begin
for i in result'range loop
result(i) := L xor R(i);
end loop;
return result;
end function "xor";
function "xor" (L : UNRESOLVED_ufixed; R : STD_ULOGIC)
return UNRESOLVED_ufixed is
variable result : UNRESOLVED_ufixed (L'range);
begin
for i in result'range loop
result(i) := L(i) xor R;
end loop;
return result;
end function "xor";
function "xnor" (L : STD_ULOGIC; R : UNRESOLVED_ufixed)
return UNRESOLVED_ufixed is
variable result : UNRESOLVED_ufixed (R'range);
begin
for i in result'range loop
result(i) := L xnor R(i);
end loop;
return result;
end function "xnor";
function "xnor" (L : UNRESOLVED_ufixed; R : STD_ULOGIC)
return UNRESOLVED_ufixed is
variable result : UNRESOLVED_ufixed (L'range);
begin
for i in result'range loop
result(i) := L(i) xnor R;
end loop;
return result;
end function "xnor";
function "and" (L : STD_ULOGIC; R : UNRESOLVED_sfixed)
return UNRESOLVED_sfixed is
variable result : UNRESOLVED_sfixed (R'range);
begin
for i in result'range loop
result(i) := L and R(i);
end loop;
return result;
end function "and";
function "and" (L : UNRESOLVED_sfixed; R : STD_ULOGIC)
return UNRESOLVED_sfixed is
variable result : UNRESOLVED_sfixed (L'range);
begin
for i in result'range loop
result(i) := L(i) and R;
end loop;
return result;
end function "and";
function "or" (L : STD_ULOGIC; R : UNRESOLVED_sfixed)
return UNRESOLVED_sfixed is
variable result : UNRESOLVED_sfixed (R'range);
begin
for i in result'range loop
result(i) := L or R(i);
end loop;
return result;
end function "or";
function "or" (L : UNRESOLVED_sfixed; R : STD_ULOGIC)
return UNRESOLVED_sfixed is
variable result : UNRESOLVED_sfixed (L'range);
begin
for i in result'range loop
result(i) := L(i) or R;
end loop;
return result;
end function "or";
function "nand" (L : STD_ULOGIC; R : UNRESOLVED_sfixed)
return UNRESOLVED_sfixed is
variable result : UNRESOLVED_sfixed (R'range);
begin
for i in result'range loop
result(i) := L nand R(i);
end loop;
return result;
end function "nand";
function "nand" (L : UNRESOLVED_sfixed; R : STD_ULOGIC)
return UNRESOLVED_sfixed is
variable result : UNRESOLVED_sfixed (L'range);
begin
for i in result'range loop
result(i) := L(i) nand R;
end loop;
return result;
end function "nand";
function "nor" (L : STD_ULOGIC; R : UNRESOLVED_sfixed)
return UNRESOLVED_sfixed is
variable result : UNRESOLVED_sfixed (R'range);
begin
for i in result'range loop
result(i) := L nor R(i);
end loop;
return result;
end function "nor";
function "nor" (L : UNRESOLVED_sfixed; R : STD_ULOGIC)
return UNRESOLVED_sfixed is
variable result : UNRESOLVED_sfixed (L'range);
begin
for i in result'range loop
result(i) := L(i) nor R;
end loop;
return result;
end function "nor";
function "xor" (L : STD_ULOGIC; R : UNRESOLVED_sfixed)
return UNRESOLVED_sfixed is
variable result : UNRESOLVED_sfixed (R'range);
begin
for i in result'range loop
result(i) := L xor R(i);
end loop;
return result;
end function "xor";
function "xor" (L : UNRESOLVED_sfixed; R : STD_ULOGIC)
return UNRESOLVED_sfixed is
variable result : UNRESOLVED_sfixed (L'range);
begin
for i in result'range loop
result(i) := L(i) xor R;
end loop;
return result;
end function "xor";
function "xnor" (L : STD_ULOGIC; R : UNRESOLVED_sfixed)
return UNRESOLVED_sfixed is
variable result : UNRESOLVED_sfixed (R'range);
begin
for i in result'range loop
result(i) := L xnor R(i);
end loop;
return result;
end function "xnor";
function "xnor" (L : UNRESOLVED_sfixed; R : STD_ULOGIC)
return UNRESOLVED_sfixed is
variable result : UNRESOLVED_sfixed (L'range);
begin
for i in result'range loop
result(i) := L(i) xnor R;
end loop;
return result;
end function "xnor";
-- Reduction operator_reduces
function and_reduce (l : UNRESOLVED_ufixed) return STD_ULOGIC is
begin
return and_reduce (to_sulv(l));
end function and_reduce;
function nand_reduce (l : UNRESOLVED_ufixed) return STD_ULOGIC is
begin
return nand_reduce (to_sulv(l));
end function nand_reduce;
function or_reduce (l : UNRESOLVED_ufixed) return STD_ULOGIC is
begin
return or_reduce (to_sulv(l));
end function or_reduce;
function nor_reduce (l : UNRESOLVED_ufixed) return STD_ULOGIC is
begin
return nor_reduce (to_sulv(l));
end function nor_reduce;
function xor_reduce (l : UNRESOLVED_ufixed) return STD_ULOGIC is
begin
return xor_reduce (to_sulv(l));
end function xor_reduce;
function xnor_reduce (l : UNRESOLVED_ufixed) return STD_ULOGIC is
begin
return xnor_reduce (to_sulv(l));
end function xnor_reduce;
function and_reduce (l : UNRESOLVED_sfixed) return STD_ULOGIC is
begin
return and_reduce (to_sulv(l));
end function and_reduce;
function nand_reduce (l : UNRESOLVED_sfixed) return STD_ULOGIC is
begin
return nand_reduce (to_sulv(l));
end function nand_reduce;
function or_reduce (l : UNRESOLVED_sfixed) return STD_ULOGIC is
begin
return or_reduce (to_sulv(l));
end function or_reduce;
function nor_reduce (l : UNRESOLVED_sfixed) return STD_ULOGIC is
begin
return nor_reduce (to_sulv(l));
end function nor_reduce;
function xor_reduce (l : UNRESOLVED_sfixed) return STD_ULOGIC is
begin
return xor_reduce (to_sulv(l));
end function xor_reduce;
function xnor_reduce (l : UNRESOLVED_sfixed) return STD_ULOGIC is
begin
return xnor_reduce (to_sulv(l));
end function xnor_reduce;
-- End reduction operator_reduces
function \?=\ (L, R : UNRESOLVED_ufixed) return STD_ULOGIC is
constant left_index : INTEGER := maximum(l'high, r'high);
constant right_index : INTEGER := mins(l'low, r'low);
variable lresize, rresize : UNRESOLVED_ufixed (left_index downto right_index);
variable lslv, rslv : UNSIGNED (lresize'length-1 downto 0);
begin -- ?=
if ((L'length < 1) or (R'length < 1)) then
assert NO_WARNING
report "fixed_pkg"
& """?="": null detected, returning X"
severity warning;
return 'X';
else
lresize := resize (l, left_index, right_index);
rresize := resize (r, left_index, right_index);
lslv := to_uns (lresize);
rslv := to_uns (rresize);
return \?=\ (lslv, rslv);
end if;
end function \?=\;
function \?/=\ (L, R : UNRESOLVED_ufixed) return STD_ULOGIC is
constant left_index : INTEGER := maximum(l'high, r'high);
constant right_index : INTEGER := mins(l'low, r'low);
variable lresize, rresize : UNRESOLVED_ufixed (left_index downto right_index);
variable lslv, rslv : UNSIGNED (lresize'length-1 downto 0);
begin -- ?/=
if ((L'length < 1) or (R'length < 1)) then
assert NO_WARNING
report "fixed_pkg"
& """?/="": null detected, returning X"
severity warning;
return 'X';
else
lresize := resize (l, left_index, right_index);
rresize := resize (r, left_index, right_index);
lslv := to_uns (lresize);
rslv := to_uns (rresize);
return \?/=\ (lslv, rslv);
end if;
end function \?/=\;
function \?>\ (L, R : UNRESOLVED_ufixed) return STD_ULOGIC is
constant left_index : INTEGER := maximum(l'high, r'high);
constant right_index : INTEGER := mins(l'low, r'low);
variable lresize, rresize : UNRESOLVED_ufixed (left_index downto right_index);
variable lslv, rslv : UNSIGNED (lresize'length-1 downto 0);
begin -- ?>
if ((l'length < 1) or (r'length < 1)) then
assert NO_WARNING
report "fixed_pkg"
& """?>"": null detected, returning X"
severity warning;
return 'X';
else
lresize := resize (l, left_index, right_index);
rresize := resize (r, left_index, right_index);
lslv := to_uns (lresize);
rslv := to_uns (rresize);
return \?>\ (lslv, rslv);
end if;
end function \?>\;
function \?>=\ (L, R : UNRESOLVED_ufixed) return STD_ULOGIC is
constant left_index : INTEGER := maximum(l'high, r'high);
constant right_index : INTEGER := mins(l'low, r'low);
variable lresize, rresize : UNRESOLVED_ufixed (left_index downto right_index);
variable lslv, rslv : UNSIGNED (lresize'length-1 downto 0);
begin -- ?>=
if ((l'length < 1) or (r'length < 1)) then
assert NO_WARNING
report "fixed_pkg"
& """?>="": null detected, returning X"
severity warning;
return 'X';
else
lresize := resize (l, left_index, right_index);
rresize := resize (r, left_index, right_index);
lslv := to_uns (lresize);
rslv := to_uns (rresize);
return \?>=\ (lslv, rslv);
end if;
end function \?>=\;
function \?<\ (L, R : UNRESOLVED_ufixed) return STD_ULOGIC is
constant left_index : INTEGER := maximum(l'high, r'high);
constant right_index : INTEGER := mins(l'low, r'low);
variable lresize, rresize : UNRESOLVED_ufixed (left_index downto right_index);
variable lslv, rslv : UNSIGNED (lresize'length-1 downto 0);
begin -- ?<
if ((l'length < 1) or (r'length < 1)) then
assert NO_WARNING
report "fixed_pkg"
& """?<"": null detected, returning X"
severity warning;
return 'X';
else
lresize := resize (l, left_index, right_index);
rresize := resize (r, left_index, right_index);
lslv := to_uns (lresize);
rslv := to_uns (rresize);
return \?<\ (lslv, rslv);
end if;
end function \?<\;
function \?<=\ (L, R : UNRESOLVED_ufixed) return STD_ULOGIC is
constant left_index : INTEGER := maximum(l'high, r'high);
constant right_index : INTEGER := mins(l'low, r'low);
variable lresize, rresize : UNRESOLVED_ufixed (left_index downto right_index);
variable lslv, rslv : UNSIGNED (lresize'length-1 downto 0);
begin -- ?<=
if ((l'length < 1) or (r'length < 1)) then
assert NO_WARNING
report "fixed_pkg"
& """?<="": null detected, returning X"
severity warning;
return 'X';
else
lresize := resize (l, left_index, right_index);
rresize := resize (r, left_index, right_index);
lslv := to_uns (lresize);
rslv := to_uns (rresize);
return \?<=\ (lslv, rslv);
end if;
end function \?<=\;
function \?=\ (L, R : UNRESOLVED_sfixed) return STD_ULOGIC is
constant left_index : INTEGER := maximum(l'high, r'high);
constant right_index : INTEGER := mins(l'low, r'low);
variable lresize, rresize : UNRESOLVED_sfixed (left_index downto right_index);
variable lslv, rslv : SIGNED (lresize'length-1 downto 0);
begin -- ?=
if ((L'length < 1) or (R'length < 1)) then
assert NO_WARNING
report "fixed_pkg"
& """?="": null detected, returning X"
severity warning;
return 'X';
else
lresize := resize (l, left_index, right_index);
rresize := resize (r, left_index, right_index);
lslv := to_s (lresize);
rslv := to_s (rresize);
return \?=\ (lslv, rslv);
end if;
end function \?=\;
function \?/=\ (L, R : UNRESOLVED_sfixed) return STD_ULOGIC is
constant left_index : INTEGER := maximum(l'high, r'high);
constant right_index : INTEGER := mins(l'low, r'low);
variable lresize, rresize : UNRESOLVED_sfixed (left_index downto right_index);
variable lslv, rslv : SIGNED (lresize'length-1 downto 0);
begin -- ?/=
if ((L'length < 1) or (R'length < 1)) then
assert NO_WARNING
report "fixed_pkg"
& """?/="": null detected, returning X"
severity warning;
return 'X';
else
lresize := resize (l, left_index, right_index);
rresize := resize (r, left_index, right_index);
lslv := to_s (lresize);
rslv := to_s (rresize);
return \?/=\ (lslv, rslv);
end if;
end function \?/=\;
function \?>\ (L, R : UNRESOLVED_sfixed) return STD_ULOGIC is
constant left_index : INTEGER := maximum(l'high, r'high);
constant right_index : INTEGER := mins(l'low, r'low);
variable lresize, rresize : UNRESOLVED_sfixed (left_index downto right_index);
variable lslv, rslv : SIGNED (lresize'length-1 downto 0);
begin -- ?>
if ((l'length < 1) or (r'length < 1)) then
assert NO_WARNING
report "fixed_pkg"
& """?>"": null detected, returning X"
severity warning;
return 'X';
else
lresize := resize (l, left_index, right_index);
rresize := resize (r, left_index, right_index);
lslv := to_s (lresize);
rslv := to_s (rresize);
return \?>\ (lslv, rslv);
end if;
end function \?>\;
function \?>=\ (L, R : UNRESOLVED_sfixed) return STD_ULOGIC is
constant left_index : INTEGER := maximum(l'high, r'high);
constant right_index : INTEGER := mins(l'low, r'low);
variable lresize, rresize : UNRESOLVED_sfixed (left_index downto right_index);
variable lslv, rslv : SIGNED (lresize'length-1 downto 0);
begin -- ?>=
if ((l'length < 1) or (r'length < 1)) then
assert NO_WARNING
report "fixed_pkg"
& """?>="": null detected, returning X"
severity warning;
return 'X';
else
lresize := resize (l, left_index, right_index);
rresize := resize (r, left_index, right_index);
lslv := to_s (lresize);
rslv := to_s (rresize);
return \?>=\ (lslv, rslv);
end if;
end function \?>=\;
function \?<\ (L, R : UNRESOLVED_sfixed) return STD_ULOGIC is
constant left_index : INTEGER := maximum(l'high, r'high);
constant right_index : INTEGER := mins(l'low, r'low);
variable lresize, rresize : UNRESOLVED_sfixed (left_index downto right_index);
variable lslv, rslv : SIGNED (lresize'length-1 downto 0);
begin -- ?<
if ((l'length < 1) or (r'length < 1)) then
assert NO_WARNING
report "fixed_pkg"
& """?<"": null detected, returning X"
severity warning;
return 'X';
else
lresize := resize (l, left_index, right_index);
rresize := resize (r, left_index, right_index);
lslv := to_s (lresize);
rslv := to_s (rresize);
return \?<\ (lslv, rslv);
end if;
end function \?<\;
function \?<=\ (L, R : UNRESOLVED_sfixed) return STD_ULOGIC is
constant left_index : INTEGER := maximum(l'high, r'high);
constant right_index : INTEGER := mins(l'low, r'low);
variable lresize, rresize : UNRESOLVED_sfixed (left_index downto right_index);
variable lslv, rslv : SIGNED (lresize'length-1 downto 0);
begin -- ?<=
if ((l'length < 1) or (r'length < 1)) then
assert NO_WARNING
report "fixed_pkg"
& """?<="": null detected, returning X"
severity warning;
return 'X';
else
lresize := resize (l, left_index, right_index);
rresize := resize (r, left_index, right_index);
lslv := to_s (lresize);
rslv := to_s (rresize);
return \?<=\ (lslv, rslv);
end if;
end function \?<=\;
-- Match function, similar to "std_match" from numeric_std
function std_match (L, R : UNRESOLVED_ufixed) return BOOLEAN is
begin
if (L'high = R'high and L'low = R'low) then
return std_match(to_sulv(L), to_sulv(R));
else
assert NO_WARNING
report "fixed_pkg"
& "STD_MATCH: L'RANGE /= R'RANGE, returning FALSE"
severity warning;
return false;
end if;
end function std_match;
function std_match (L, R : UNRESOLVED_sfixed) return BOOLEAN is
begin
if (L'high = R'high and L'low = R'low) then
return std_match(to_sulv(L), to_sulv(R));
else
assert NO_WARNING
report "fixed_pkg"
& "STD_MATCH: L'RANGE /= R'RANGE, returning FALSE"
severity warning;
return false;
end if;
end function std_match;
-- compare functions
function "=" (
l, r : UNRESOLVED_ufixed) -- fixed point input
return BOOLEAN is
constant left_index : INTEGER := maximum(l'high, r'high);
constant right_index : INTEGER := mins(l'low, r'low);
variable lresize, rresize : UNRESOLVED_ufixed (left_index downto right_index);
variable lslv, rslv : UNSIGNED (lresize'length-1 downto 0);
begin
if (l'length < 1 or r'length < 1) then
assert NO_WARNING
report "fixed_pkg"
& """="": null argument detected, returning FALSE"
severity warning;
return false;
elsif (Is_X(l) or Is_X(r)) then
assert NO_WARNING
report "fixed_pkg"
& """="": metavalue detected, returning FALSE"
severity warning;
return false;
end if;
lresize := resize (l, left_index, right_index);
rresize := resize (r, left_index, right_index);
lslv := to_uns (lresize);
rslv := to_uns (rresize);
return lslv = rslv;
end function "=";
function "=" (
l, r : UNRESOLVED_sfixed) -- fixed point input
return BOOLEAN is
constant left_index : INTEGER := maximum(l'high, r'high);
constant right_index : INTEGER := mins(l'low, r'low);
variable lresize, rresize : UNRESOLVED_sfixed (left_index downto right_index);
variable lslv, rslv : SIGNED (lresize'length-1 downto 0);
begin
if (l'length < 1 or r'length < 1) then
assert NO_WARNING
report "fixed_pkg"
& """="": null argument detected, returning FALSE"
severity warning;
return false;
elsif (Is_X(l) or Is_X(r)) then
assert NO_WARNING
report "fixed_pkg"
& """="": metavalue detected, returning FALSE"
severity warning;
return false;
end if;
lresize := resize (l, left_index, right_index);
rresize := resize (r, left_index, right_index);
lslv := to_s (lresize);
rslv := to_s (rresize);
return lslv = rslv;
end function "=";
function "/=" (
l, r : UNRESOLVED_ufixed) -- fixed point input
return BOOLEAN is
constant left_index : INTEGER := maximum(l'high, r'high);
constant right_index : INTEGER := mins(l'low, r'low);
variable lresize, rresize : UNRESOLVED_ufixed (left_index downto right_index);
variable lslv, rslv : UNSIGNED (lresize'length-1 downto 0);
begin
if (l'length < 1 or r'length < 1) then
assert NO_WARNING
report "fixed_pkg"
& """/="": null argument detected, returning TRUE"
severity warning;
return true;
elsif (Is_X(l) or Is_X(r)) then
assert NO_WARNING
report "fixed_pkg"
& """/="": metavalue detected, returning TRUE"
severity warning;
return true;
end if;
lresize := resize (l, left_index, right_index);
rresize := resize (r, left_index, right_index);
lslv := to_uns (lresize);
rslv := to_uns (rresize);
return lslv /= rslv;
end function "/=";
function "/=" (
l, r : UNRESOLVED_sfixed) -- fixed point input
return BOOLEAN is
constant left_index : INTEGER := maximum(l'high, r'high);
constant right_index : INTEGER := mins(l'low, r'low);
variable lresize, rresize : UNRESOLVED_sfixed (left_index downto right_index);
variable lslv, rslv : SIGNED (lresize'length-1 downto 0);
begin
if (l'length < 1 or r'length < 1) then
assert NO_WARNING
report "fixed_pkg"
& """/="": null argument detected, returning TRUE"
severity warning;
return true;
elsif (Is_X(l) or Is_X(r)) then
assert NO_WARNING
report "fixed_pkg"
& """/="": metavalue detected, returning TRUE"
severity warning;
return true;
end if;
lresize := resize (l, left_index, right_index);
rresize := resize (r, left_index, right_index);
lslv := to_s (lresize);
rslv := to_s (rresize);
return lslv /= rslv;
end function "/=";
function ">" (
l, r : UNRESOLVED_ufixed) -- fixed point input
return BOOLEAN is
constant left_index : INTEGER := maximum(l'high, r'high);
constant right_index : INTEGER := mins(l'low, r'low);
variable lresize, rresize : UNRESOLVED_ufixed (left_index downto right_index);
variable lslv, rslv : UNSIGNED (lresize'length-1 downto 0);
begin
if (l'length < 1 or r'length < 1) then
assert NO_WARNING
report "fixed_pkg"
& """>"": null argument detected, returning FALSE"
severity warning;
return false;
elsif (Is_X(l) or Is_X(r)) then
assert NO_WARNING
report "fixed_pkg"
& """>"": metavalue detected, returning FALSE"
severity warning;
return false;
end if;
lresize := resize (l, left_index, right_index);
rresize := resize (r, left_index, right_index);
lslv := to_uns (lresize);
rslv := to_uns (rresize);
return lslv > rslv;
end function ">";
function ">" (
l, r : UNRESOLVED_sfixed) -- fixed point input
return BOOLEAN is
constant left_index : INTEGER := maximum(l'high, r'high);
constant right_index : INTEGER := mins(l'low, r'low);
variable lresize, rresize : UNRESOLVED_sfixed (left_index downto right_index);
variable lslv, rslv : SIGNED (lresize'length-1 downto 0);
begin
if (l'length < 1 or r'length < 1) then
assert NO_WARNING
report "fixed_pkg"
& """>"": null argument detected, returning FALSE"
severity warning;
return false;
elsif (Is_X(l) or Is_X(r)) then
assert NO_WARNING
report "fixed_pkg"
& """>"": metavalue detected, returning FALSE"
severity warning;
return false;
end if;
lresize := resize (l, left_index, right_index);
rresize := resize (r, left_index, right_index);
lslv := to_s (lresize);
rslv := to_s (rresize);
return lslv > rslv;
end function ">";
function "<" (
l, r : UNRESOLVED_ufixed) -- fixed point input
return BOOLEAN is
constant left_index : INTEGER := maximum(l'high, r'high);
constant right_index : INTEGER := mins(l'low, r'low);
variable lresize, rresize : UNRESOLVED_ufixed (left_index downto right_index);
variable lslv, rslv : UNSIGNED (lresize'length-1 downto 0);
begin
if (l'length < 1 or r'length < 1) then
assert NO_WARNING
report "fixed_pkg"
& """<"": null argument detected, returning FALSE"
severity warning;
return false;
elsif (Is_X(l) or Is_X(r)) then
assert NO_WARNING
report "fixed_pkg"
& """<"": metavalue detected, returning FALSE"
severity warning;
return false;
end if;
lresize := resize (l, left_index, right_index);
rresize := resize (r, left_index, right_index);
lslv := to_uns (lresize);
rslv := to_uns (rresize);
return lslv < rslv;
end function "<";
function "<" (
l, r : UNRESOLVED_sfixed) -- fixed point input
return BOOLEAN is
constant left_index : INTEGER := maximum(l'high, r'high);
constant right_index : INTEGER := mins(l'low, r'low);
variable lresize, rresize : UNRESOLVED_sfixed (left_index downto right_index);
variable lslv, rslv : SIGNED (lresize'length-1 downto 0);
begin
if (l'length < 1 or r'length < 1) then
assert NO_WARNING
report "fixed_pkg"
& """<"": null argument detected, returning FALSE"
severity warning;
return false;
elsif (Is_X(l) or Is_X(r)) then
assert NO_WARNING
report "fixed_pkg"
& """<"": metavalue detected, returning FALSE"
severity warning;
return false;
end if;
lresize := resize (l, left_index, right_index);
rresize := resize (r, left_index, right_index);
lslv := to_s (lresize);
rslv := to_s (rresize);
return lslv < rslv;
end function "<";
function ">=" (
l, r : UNRESOLVED_ufixed) -- fixed point input
return BOOLEAN is
constant left_index : INTEGER := maximum(l'high, r'high);
constant right_index : INTEGER := mins(l'low, r'low);
variable lresize, rresize : UNRESOLVED_ufixed (left_index downto right_index);
variable lslv, rslv : UNSIGNED (lresize'length-1 downto 0);
begin
if (l'length < 1 or r'length < 1) then
assert NO_WARNING
report "fixed_pkg"
& """>="": null argument detected, returning FALSE"
severity warning;
return false;
elsif (Is_X(l) or Is_X(r)) then
assert NO_WARNING
report "fixed_pkg"
& """>="": metavalue detected, returning FALSE"
severity warning;
return false;
end if;
lresize := resize (l, left_index, right_index);
rresize := resize (r, left_index, right_index);
lslv := to_uns (lresize);
rslv := to_uns (rresize);
return lslv >= rslv;
end function ">=";
function ">=" (
l, r : UNRESOLVED_sfixed) -- fixed point input
return BOOLEAN is
constant left_index : INTEGER := maximum(l'high, r'high);
constant right_index : INTEGER := mins(l'low, r'low);
variable lresize, rresize : UNRESOLVED_sfixed (left_index downto right_index);
variable lslv, rslv : SIGNED (lresize'length-1 downto 0);
begin
if (l'length < 1 or r'length < 1) then
assert NO_WARNING
report "fixed_pkg"
& """>="": null argument detected, returning FALSE"
severity warning;
return false;
elsif (Is_X(l) or Is_X(r)) then
assert NO_WARNING
report "fixed_pkg"
& """>="": metavalue detected, returning FALSE"
severity warning;
return false;
end if;
lresize := resize (l, left_index, right_index);
rresize := resize (r, left_index, right_index);
lslv := to_s (lresize);
rslv := to_s (rresize);
return lslv >= rslv;
end function ">=";
function "<=" (
l, r : UNRESOLVED_ufixed) -- fixed point input
return BOOLEAN is
constant left_index : INTEGER := maximum(l'high, r'high);
constant right_index : INTEGER := mins(l'low, r'low);
variable lresize, rresize : UNRESOLVED_ufixed (left_index downto right_index);
variable lslv, rslv : UNSIGNED (lresize'length-1 downto 0);
begin
if (l'length < 1 or r'length < 1) then
assert NO_WARNING
report "fixed_pkg"
& """<="": null argument detected, returning FALSE"
severity warning;
return false;
elsif (Is_X(l) or Is_X(r)) then
assert NO_WARNING
report "fixed_pkg"
& """<="": metavalue detected, returning FALSE"
severity warning;
return false;
end if;
lresize := resize (l, left_index, right_index);
rresize := resize (r, left_index, right_index);
lslv := to_uns (lresize);
rslv := to_uns (rresize);
return lslv <= rslv;
end function "<=";
function "<=" (
l, r : UNRESOLVED_sfixed) -- fixed point input
return BOOLEAN is
constant left_index : INTEGER := maximum(l'high, r'high);
constant right_index : INTEGER := mins(l'low, r'low);
variable lresize, rresize : UNRESOLVED_sfixed (left_index downto right_index);
variable lslv, rslv : SIGNED (lresize'length-1 downto 0);
begin
if (l'length < 1 or r'length < 1) then
assert NO_WARNING
report "fixed_pkg"
& """<="": null argument detected, returning FALSE"
severity warning;
return false;
elsif (Is_X(l) or Is_X(r)) then
assert NO_WARNING
report "fixed_pkg"
& """<="": metavalue detected, returning FALSE"
severity warning;
return false;
end if;
lresize := resize (l, left_index, right_index);
rresize := resize (r, left_index, right_index);
lslv := to_s (lresize);
rslv := to_s (rresize);
return lslv <= rslv;
end function "<=";
-- overloads of the default maximum and minimum functions
function maximum (l, r : UNRESOLVED_ufixed) return UNRESOLVED_ufixed is
constant left_index : INTEGER := maximum(l'high, r'high);
constant right_index : INTEGER := mins(l'low, r'low);
variable lresize, rresize : UNRESOLVED_ufixed (left_index downto right_index);
begin
if (l'length < 1 or r'length < 1) then
return NAUF;
end if;
lresize := resize (l, left_index, right_index);
rresize := resize (r, left_index, right_index);
if lresize > rresize then return lresize;
else return rresize;
end if;
end function maximum;
function maximum (l, r : UNRESOLVED_sfixed) return UNRESOLVED_sfixed is
constant left_index : INTEGER := maximum(l'high, r'high);
constant right_index : INTEGER := mins(l'low, r'low);
variable lresize, rresize : UNRESOLVED_sfixed (left_index downto right_index);
begin
if (l'length < 1 or r'length < 1) then
return NASF;
end if;
lresize := resize (l, left_index, right_index);
rresize := resize (r, left_index, right_index);
if lresize > rresize then return lresize;
else return rresize;
end if;
end function maximum;
function minimum (l, r : UNRESOLVED_ufixed) return UNRESOLVED_ufixed is
constant left_index : INTEGER := maximum(l'high, r'high);
constant right_index : INTEGER := mins(l'low, r'low);
variable lresize, rresize : UNRESOLVED_ufixed (left_index downto right_index);
begin
if (l'length < 1 or r'length < 1) then
return NAUF;
end if;
lresize := resize (l, left_index, right_index);
rresize := resize (r, left_index, right_index);
if lresize > rresize then return rresize;
else return lresize;
end if;
end function minimum;
function minimum (l, r : UNRESOLVED_sfixed) return UNRESOLVED_sfixed is
constant left_index : INTEGER := maximum(l'high, r'high);
constant right_index : INTEGER := mins(l'low, r'low);
variable lresize, rresize : UNRESOLVED_sfixed (left_index downto right_index);
begin
if (l'length < 1 or r'length < 1) then
return NASF;
end if;
lresize := resize (l, left_index, right_index);
rresize := resize (r, left_index, right_index);
if lresize > rresize then return rresize;
else return lresize;
end if;
end function minimum;
function to_ufixed (
arg : NATURAL; -- integer
constant left_index : INTEGER; -- left index (high index)
constant right_index : INTEGER := 0; -- right index
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;
constant round_style : fixed_round_style_type := fixed_round_style)
return UNRESOLVED_ufixed is
constant fw : INTEGER := mins (right_index, right_index); -- catch literals
variable result : UNRESOLVED_ufixed (left_index downto fw);
variable sresult : UNRESOLVED_ufixed (left_index downto 0) :=
(others => '0'); -- integer portion
variable argx : NATURAL; -- internal version of arg
begin
if (result'length < 1) then
return NAUF;
end if;
if arg /= 0 then
argx := arg;
for I in 0 to sresult'left loop
if (argx mod 2) = 0 then
sresult(I) := '0';
else
sresult(I) := '1';
end if;
argx := argx/2;
end loop;
if argx /= 0 then
assert NO_WARNING
report "fixed_pkg"
& "TO_UFIXED(NATURAL): vector truncated"
severity warning;
if overflow_style = fixed_saturate then
return saturate (left_index, right_index);
end if;
end if;
result := resize (arg => sresult,
left_index => left_index,
right_index => right_index,
round_style => round_style,
overflow_style => overflow_style);
else
result := (others => '0');
end if;
return result;
end function to_ufixed;
function to_sfixed (
arg : INTEGER; -- integer
constant left_index : INTEGER; -- left index (high index)
constant right_index : INTEGER := 0; -- right index
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;
constant round_style : fixed_round_style_type := fixed_round_style)
return UNRESOLVED_sfixed is
constant fw : INTEGER := mins (right_index, right_index); -- catch literals
variable result : UNRESOLVED_sfixed (left_index downto fw);
variable sresult : UNRESOLVED_sfixed (left_index downto 0) :=
(others => '0'); -- integer portion
variable argx : INTEGER; -- internal version of arg
variable sign : STD_ULOGIC; -- sign of input
begin
if (result'length < 1) then -- null range
return NASF;
end if;
if arg /= 0 then
if (arg < 0) then
sign := '1';
argx := -(arg + 1);
else
sign := '0';
argx := arg;
end if;
for I in 0 to sresult'left loop
if (argx mod 2) = 0 then
sresult(I) := sign;
else
sresult(I) := not sign;
end if;
argx := argx/2;
end loop;
if argx /= 0 or left_index < 0 or sign /= sresult(sresult'left) then
assert NO_WARNING
report "fixed_pkg"
& "TO_SFIXED(INTEGER): vector truncated"
severity warning;
if overflow_style = fixed_saturate then -- saturate
if arg < 0 then
result := not saturate (result'high, result'low); -- underflow
else
result := saturate (result'high, result'low); -- overflow
end if;
return result;
end if;
end if;
result := resize (arg => sresult,
left_index => left_index,
right_index => right_index,
round_style => round_style,
overflow_style => overflow_style);
else
result := (others => '0');
end if;
return result;
end function to_sfixed;
function to_ufixed (
arg : REAL; -- real
constant left_index : INTEGER; -- left index (high index)
constant right_index : INTEGER; -- right index
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;
constant round_style : fixed_round_style_type := fixed_round_style;
constant guard_bits : NATURAL := fixed_guard_bits) -- # of guard bits
return UNRESOLVED_ufixed is
constant fw : INTEGER := mins (right_index, right_index); -- catch literals
variable result : UNRESOLVED_ufixed (left_index downto fw) :=
(others => '0');
variable Xresult : UNRESOLVED_ufixed (left_index downto
fw-guard_bits) :=
(others => '0');
variable presult : REAL;
-- variable overflow_needed : BOOLEAN;
begin
-- If negative or null range, return.
if (left_index < fw) then
return NAUF;
end if;
if (arg < 0.0) then
report "fixed_pkg"
& "TO_UFIXED: Negative argument passed "
& REAL'image(arg) severity error;
return result;
end if;
presult := arg;
if presult >= (2.0**(left_index+1)) then
assert NO_WARNING report "fixed_pkg"
& "TO_UFIXED(REAL): vector truncated"
severity warning;
if overflow_style = fixed_wrap then
presult := presult mod (2.0**(left_index+1)); -- wrap
else
return saturate (result'high, result'low);
end if;
end if;
for i in Xresult'range loop
if presult >= 2.0**i then
Xresult(i) := '1';
presult := presult - 2.0**i;
else
Xresult(i) := '0';
end if;
end loop;
if guard_bits > 0 and round_style = fixed_round then
result := round_fixed (arg => Xresult (left_index
downto right_index),
remainder => Xresult (right_index-1 downto
right_index-guard_bits),
overflow_style => overflow_style);
else
result := Xresult (result'range);
end if;
return result;
end function to_ufixed;
function to_sfixed (
arg : REAL; -- real
constant left_index : INTEGER; -- left index (high index)
constant right_index : INTEGER; -- right index
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;
constant round_style : fixed_round_style_type := fixed_round_style;
constant guard_bits : NATURAL := fixed_guard_bits) -- # of guard bits
return UNRESOLVED_sfixed is
constant fw : INTEGER := mins (right_index, right_index); -- catch literals
variable result : UNRESOLVED_sfixed (left_index downto fw) :=
(others => '0');
variable Xresult : UNRESOLVED_sfixed (left_index+1 downto fw-guard_bits) :=
(others => '0');
variable presult : REAL;
begin
if (left_index < fw) then -- null range
return NASF;
end if;
if (arg >= (2.0**left_index) or arg < -(2.0**left_index)) then
assert NO_WARNING report "fixed_pkg"
& "TO_SFIXED(REAL): vector truncated"
severity warning;
if overflow_style = fixed_saturate then
if arg < 0.0 then -- saturate
result := not saturate (result'high, result'low); -- underflow
else
result := saturate (result'high, result'low); -- overflow
end if;
return result;
else
presult := abs(arg) mod (2.0**(left_index+1)); -- wrap
end if;
else
presult := abs(arg);
end if;
for i in Xresult'range loop
if presult >= 2.0**i then
Xresult(i) := '1';
presult := presult - 2.0**i;
else
Xresult(i) := '0';
end if;
end loop;
if arg < 0.0 then
Xresult := to_fixed(-to_s(Xresult), Xresult'high, Xresult'low);
end if;
if guard_bits > 0 and round_style = fixed_round then
result := round_fixed (arg => Xresult (left_index
downto right_index),
remainder => Xresult (right_index-1 downto
right_index-guard_bits),
overflow_style => overflow_style);
else
result := Xresult (result'range);
end if;
return result;
end function to_sfixed;
function to_ufixed (
arg : UNSIGNED; -- unsigned
constant left_index : INTEGER; -- left index (high index)
constant right_index : INTEGER := 0; -- right index
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;
constant round_style : fixed_round_style_type := fixed_round_style)
return UNRESOLVED_ufixed is
constant ARG_LEFT : INTEGER := ARG'length-1;
alias XARG : UNSIGNED(ARG_LEFT downto 0) is ARG;
variable result : UNRESOLVED_ufixed (left_index downto right_index);
begin
if arg'length < 1 or (left_index < right_index) then
return NAUF;
end if;
result := resize (arg => UNRESOLVED_ufixed (XARG),
left_index => left_index,
right_index => right_index,
round_style => round_style,
overflow_style => overflow_style);
return result;
end function to_ufixed;
-- converted version
function to_ufixed (
arg : UNSIGNED) -- unsigned
return UNRESOLVED_ufixed is
constant ARG_LEFT : INTEGER := ARG'length-1;
alias XARG : UNSIGNED(ARG_LEFT downto 0) is ARG;
begin
if arg'length < 1 then
return NAUF;
end if;
return UNRESOLVED_ufixed(xarg);
end function to_ufixed;
function to_sfixed (
arg : SIGNED; -- signed
constant left_index : INTEGER; -- left index (high index)
constant right_index : INTEGER := 0; -- right index
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;
constant round_style : fixed_round_style_type := fixed_round_style)
return UNRESOLVED_sfixed is
constant ARG_LEFT : INTEGER := ARG'length-1;
alias XARG : SIGNED(ARG_LEFT downto 0) is ARG;
variable result : UNRESOLVED_sfixed (left_index downto right_index);
begin
if arg'length < 1 or (left_index < right_index) then
return NASF;
end if;
result := resize (arg => UNRESOLVED_sfixed (XARG),
left_index => left_index,
right_index => right_index,
round_style => round_style,
overflow_style => overflow_style);
return result;
end function to_sfixed;
-- converted version
function to_sfixed (
arg : SIGNED) -- signed
return UNRESOLVED_sfixed is
constant ARG_LEFT : INTEGER := ARG'length-1;
alias XARG : SIGNED(ARG_LEFT downto 0) is ARG;
begin
if arg'length < 1 then
return NASF;
end if;
return UNRESOLVED_sfixed(xarg);
end function to_sfixed;
function to_sfixed (arg : UNRESOLVED_ufixed) return UNRESOLVED_sfixed is
variable result : UNRESOLVED_sfixed (arg'high+1 downto arg'low);
begin
if arg'length < 1 then
return NASF;
end if;
result (arg'high downto arg'low) := UNRESOLVED_sfixed(cleanvec(arg));
result (arg'high+1) := '0';
return result;
end function to_sfixed;
-- Because of the fairly complicated sizing rules in the fixed point
-- packages these functions are provided to compute the result ranges
-- Example:
-- signal uf1 : ufixed (3 downto -3);
-- signal uf2 : ufixed (4 downto -2);
-- signal uf1multuf2 : ufixed (ufixed_high (3, -3, '*', 4, -2) downto
-- ufixed_low (3, -3, '*', 4, -2));
-- uf1multuf2 <= uf1 * uf2;
-- Valid characters: '+', '-', '*', '/', 'r' or 'R' (rem), 'm' or 'M' (mod),
-- '1' (reciprocal), 'A', 'a' (abs), 'N', 'n' (-sfixed)
function ufixed_high (left_index, right_index : INTEGER;
operation : CHARACTER := 'X';
left_index2, right_index2 : INTEGER := 0)
return INTEGER is
begin
case operation is
when '+'| '-' => return maximum (left_index, left_index2) + 1;
when '*' => return left_index + left_index2 + 1;
when '/' => return left_index - right_index2;
when '1' => return -right_index; -- reciprocal
when 'R'|'r' => return mins (left_index, left_index2); -- "rem"
when 'M'|'m' => return mins (left_index, left_index2); -- "mod"
when others => return left_index; -- For abs and default
end case;
end function ufixed_high;
function ufixed_low (left_index, right_index : INTEGER;
operation : CHARACTER := 'X';
left_index2, right_index2 : INTEGER := 0)
return INTEGER is
begin
case operation is
when '+'| '-' => return mins (right_index, right_index2);
when '*' => return right_index + right_index2;
when '/' => return right_index - left_index2 - 1;
when '1' => return -left_index - 1; -- reciprocal
when 'R'|'r' => return mins (right_index, right_index2); -- "rem"
when 'M'|'m' => return mins (right_index, right_index2); -- "mod"
when others => return right_index; -- for abs and default
end case;
end function ufixed_low;
function sfixed_high (left_index, right_index : INTEGER;
operation : CHARACTER := 'X';
left_index2, right_index2 : INTEGER := 0)
return INTEGER is
begin
case operation is
when '+'| '-' => return maximum (left_index, left_index2) + 1;
when '*' => return left_index + left_index2 + 1;
when '/' => return left_index - right_index2 + 1;
when '1' => return -right_index + 1; -- reciprocal
when 'R'|'r' => return mins (left_index, left_index2); -- "rem"
when 'M'|'m' => return left_index2; -- "mod"
when 'A'|'a' => return left_index + 1; -- "abs"
when 'N'|'n' => return left_index + 1; -- -sfixed
when others => return left_index;
end case;
end function sfixed_high;
function sfixed_low (left_index, right_index : INTEGER;
operation : CHARACTER := 'X';
left_index2, right_index2 : INTEGER := 0)
return INTEGER is
begin
case operation is
when '+'| '-' => return mins (right_index, right_index2);
when '*' => return right_index + right_index2;
when '/' => return right_index - left_index2;
when '1' => return -left_index; -- reciprocal
when 'R'|'r' => return mins (right_index, right_index2); -- "rem"
when 'M'|'m' => return mins (right_index, right_index2); -- "mod"
when others => return right_index; -- default for abs, neg and default
end case;
end function sfixed_low;
-- Same as above, but using the "size_res" input only for their ranges:
-- signal uf1multuf2 : ufixed (ufixed_high (uf1, '*', uf2) downto
-- ufixed_low (uf1, '*', uf2));
-- uf1multuf2 <= uf1 * uf2;
function ufixed_high (size_res : UNRESOLVED_ufixed;
operation : CHARACTER := 'X';
size_res2 : UNRESOLVED_ufixed)
return INTEGER is
begin
return ufixed_high (left_index => size_res'high,
right_index => size_res'low,
operation => operation,
left_index2 => size_res2'high,
right_index2 => size_res2'low);
end function ufixed_high;
function ufixed_low (size_res : UNRESOLVED_ufixed;
operation : CHARACTER := 'X';
size_res2 : UNRESOLVED_ufixed)
return INTEGER is
begin
return ufixed_low (left_index => size_res'high,
right_index => size_res'low,
operation => operation,
left_index2 => size_res2'high,
right_index2 => size_res2'low);
end function ufixed_low;
function sfixed_high (size_res : UNRESOLVED_sfixed;
operation : CHARACTER := 'X';
size_res2 : UNRESOLVED_sfixed)
return INTEGER is
begin
return sfixed_high (left_index => size_res'high,
right_index => size_res'low,
operation => operation,
left_index2 => size_res2'high,
right_index2 => size_res2'low);
end function sfixed_high;
function sfixed_low (size_res : UNRESOLVED_sfixed;
operation : CHARACTER := 'X';
size_res2 : UNRESOLVED_sfixed)
return INTEGER is
begin
return sfixed_low (left_index => size_res'high,
right_index => size_res'low,
operation => operation,
left_index2 => size_res2'high,
right_index2 => size_res2'low);
end function sfixed_low;
-- purpose: returns a saturated number
function saturate (
constant left_index : INTEGER;
constant right_index : INTEGER)
return UNRESOLVED_ufixed is
constant sat : UNRESOLVED_ufixed (left_index downto right_index) :=
(others => '1');
begin
return sat;
end function saturate;
-- purpose: returns a saturated number
function saturate (
constant left_index : INTEGER;
constant right_index : INTEGER)
return UNRESOLVED_sfixed is
variable sat : UNRESOLVED_sfixed (left_index downto right_index) :=
(others => '1');
begin
-- saturate positive, to saturate negative, just do "not saturate()"
sat (left_index) := '0';
return sat;
end function saturate;
function saturate (
size_res : UNRESOLVED_ufixed) -- only the size of this is used
return UNRESOLVED_ufixed is
begin
return saturate (size_res'high, size_res'low);
end function saturate;
function saturate (
size_res : UNRESOLVED_sfixed) -- only the size of this is used
return UNRESOLVED_sfixed is
begin
return saturate (size_res'high, size_res'low);
end function saturate;
-- As a concession to those who use a graphical DSP environment,
-- these functions take parameters in those tools format and create
-- fixed point numbers. These functions are designed to convert from
-- a std_logic_vector to the VHDL fixed point format using the conventions
-- of these packages. In a pure VHDL environment you should use the
-- "to_ufixed" and "to_sfixed" routines.
-- Unsigned fixed point
function to_UFix (
arg : STD_ULOGIC_VECTOR;
width : NATURAL; -- width of vector
fraction : NATURAL) -- width of fraction
return UNRESOLVED_ufixed is
variable result : UNRESOLVED_ufixed (width-fraction-1 downto -fraction);
begin
if (arg'length /= result'length) then
report "fixed_pkg"
& "TO_UFIX (STD_ULOGIC_VECTOR) "
& "Vector lengths do not match. Input length is "
& INTEGER'image(arg'length) & " and output will be "
& INTEGER'image(result'length) & " wide."
severity error;
return NAUF;
else
result := to_ufixed (arg, result'high, result'low);
return result;
end if;
end function to_UFix;
-- signed fixed point
function to_SFix (
arg : STD_ULOGIC_VECTOR;
width : NATURAL; -- width of vector
fraction : NATURAL) -- width of fraction
return UNRESOLVED_sfixed is
variable result : UNRESOLVED_sfixed (width-fraction-1 downto -fraction);
begin
if (arg'length /= result'length) then
report "fixed_pkg"
& "TO_SFIX (STD_ULOGIC_VECTOR) "
& "Vector lengths do not match. Input length is "
& INTEGER'image(arg'length) & " and output will be "
& INTEGER'image(result'length) & " wide."
severity error;
return NASF;
else
result := to_sfixed (arg, result'high, result'low);
return result;
end if;
end function to_SFix;
-- finding the bounds of a number. These functions can be used like this:
-- signal xxx : ufixed (7 downto -3);
-- -- Which is the same as "ufixed (UFix_high (11,3) downto UFix_low(11,3))"
-- signal yyy : ufixed (UFix_high (11, 3, "+", 11, 3)
-- downto UFix_low(11, 3, "+", 11, 3));
-- Where "11" is the width of xxx (xxx'length),
-- and 3 is the lower bound (abs (xxx'low))
-- In a pure VHDL environment use "ufixed_high" and "ufixed_low"
function ufix_high (
width, fraction : NATURAL;
operation : CHARACTER := 'X';
width2, fraction2 : NATURAL := 0)
return INTEGER is
begin
return ufixed_high (left_index => width - 1 - fraction,
right_index => -fraction,
operation => operation,
left_index2 => width2 - 1 - fraction2,
right_index2 => -fraction2);
end function ufix_high;
function ufix_low (
width, fraction : NATURAL;
operation : CHARACTER := 'X';
width2, fraction2 : NATURAL := 0)
return INTEGER is
begin
return ufixed_low (left_index => width - 1 - fraction,
right_index => -fraction,
operation => operation,
left_index2 => width2 - 1 - fraction2,
right_index2 => -fraction2);
end function ufix_low;
function sfix_high (
width, fraction : NATURAL;
operation : CHARACTER := 'X';
width2, fraction2 : NATURAL := 0)
return INTEGER is
begin
return sfixed_high (left_index => width - fraction,
right_index => -fraction,
operation => operation,
left_index2 => width2 - fraction2,
right_index2 => -fraction2);
end function sfix_high;
function sfix_low (
width, fraction : NATURAL;
operation : CHARACTER := 'X';
width2, fraction2 : NATURAL := 0)
return INTEGER is
begin
return sfixed_low (left_index => width - fraction,
right_index => -fraction,
operation => operation,
left_index2 => width2 - fraction2,
right_index2 => -fraction2);
end function sfix_low;
function to_unsigned (
arg : UNRESOLVED_ufixed; -- ufixed point input
constant size : NATURAL; -- length of output
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;
constant round_style : fixed_round_style_type := fixed_round_style)
return UNSIGNED is
begin
return to_uns(resize (arg => arg,
left_index => size-1,
right_index => 0,
round_style => round_style,
overflow_style => overflow_style));
end function to_unsigned;
function to_unsigned (
arg : UNRESOLVED_ufixed; -- ufixed point input
size_res : UNSIGNED; -- length of output
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;
constant round_style : fixed_round_style_type := fixed_round_style)
return UNSIGNED is
begin
return to_unsigned (arg => arg,
size => size_res'length,
round_style => round_style,
overflow_style => overflow_style);
end function to_unsigned;
function to_signed (
arg : UNRESOLVED_sfixed; -- sfixed point input
constant size : NATURAL; -- length of output
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;
constant round_style : fixed_round_style_type := fixed_round_style)
return SIGNED is
begin
return to_s(resize (arg => arg,
left_index => size-1,
right_index => 0,
round_style => round_style,
overflow_style => overflow_style));
end function to_signed;
function to_signed (
arg : UNRESOLVED_sfixed; -- sfixed point input
size_res : SIGNED; -- used for length of output
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;
constant round_style : fixed_round_style_type := fixed_round_style)
return SIGNED is
begin
return to_signed (arg => arg,
size => size_res'length,
round_style => round_style,
overflow_style => overflow_style);
end function to_signed;
function to_real (
arg : UNRESOLVED_ufixed) -- ufixed point input
return REAL is
constant left_index : INTEGER := arg'high;
constant right_index : INTEGER := arg'low;
variable result : REAL; -- result
variable arg_int : UNRESOLVED_ufixed (left_index downto right_index);
begin
if (arg'length < 1) then
return 0.0;
end if;
arg_int := to_x01(cleanvec(arg));
if (Is_X(arg_int)) then
assert NO_WARNING
report "fixed_pkg"
& "TO_REAL (ufixed): metavalue detected, returning 0.0"
severity warning;
return 0.0;
end if;
result := 0.0;
for i in arg_int'range loop
if (arg_int(i) = '1') then
result := result + (2.0**i);
end if;
end loop;
return result;
end function to_real;
function to_real (
arg : UNRESOLVED_sfixed) -- ufixed point input
return REAL is
constant left_index : INTEGER := arg'high;
constant right_index : INTEGER := arg'low;
variable result : REAL; -- result
variable arg_int : UNRESOLVED_sfixed (left_index downto right_index);
-- unsigned version of argument
variable arg_uns : UNRESOLVED_ufixed (left_index downto right_index);
-- absolute of argument
begin
if (arg'length < 1) then
return 0.0;
end if;
arg_int := to_x01(cleanvec(arg));
if (Is_X(arg_int)) then
assert NO_WARNING
report "fixed_pkg"
& "TO_REAL (sfixed): metavalue detected, returning 0.0"
severity warning;
return 0.0;
end if;
arg_uns := to_ufixed (arg_int);
result := to_real (arg_uns);
if (arg_int(arg_int'high) = '1') then
result := -result;
end if;
return result;
end function to_real;
function to_integer (
arg : UNRESOLVED_ufixed; -- fixed point input
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;
constant round_style : fixed_round_style_type := fixed_round_style)
return NATURAL is
constant left_index : INTEGER := arg'high;
variable arg_uns : UNSIGNED (left_index+1 downto 0)
:= (others => '0');
begin
if (arg'length < 1) then
return 0;
end if;
if (Is_X (arg)) then
assert NO_WARNING
report "fixed_pkg"
& "TO_INTEGER (ufixed): metavalue detected, returning 0"
severity warning;
return 0;
end if;
if (left_index < -1) then
return 0;
end if;
arg_uns := to_uns(resize (arg => arg,
left_index => arg_uns'high,
right_index => 0,
round_style => round_style,
overflow_style => overflow_style));
return to_integer (arg_uns);
end function to_integer;
function to_integer (
arg : UNRESOLVED_sfixed; -- fixed point input
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;
constant round_style : fixed_round_style_type := fixed_round_style)
return INTEGER is
constant left_index : INTEGER := arg'high;
constant right_index : INTEGER := arg'low;
variable arg_s : SIGNED (left_index+1 downto 0);
begin
if (arg'length < 1) then
return 0;
end if;
if (Is_X (arg)) then
assert NO_WARNING
report "fixed_pkg"
& "TO_INTEGER (sfixed): metavalue detected, returning 0"
severity warning;
return 0;
end if;
if (left_index < -1) then
return 0;
end if;
arg_s := to_s(resize (arg => arg,
left_index => arg_s'high,
right_index => 0,
round_style => round_style,
overflow_style => overflow_style));
return to_integer (arg_s);
end function to_integer;
function to_01 (
s : UNRESOLVED_ufixed; -- ufixed point input
constant XMAP : STD_ULOGIC := '0') -- Map x to
return UNRESOLVED_ufixed is
variable result : UNRESOLVED_ufixed (s'range); -- result
begin
if (s'length < 1) then
assert NO_WARNING
report "fixed_pkg"
& "TO_01(ufixed): null detected, returning NULL"
severity warning;
return NAUF;
end if;
return to_fixed (to_01(to_uns(s), XMAP), s'high, s'low);
end function to_01;
function to_01 (
s : UNRESOLVED_sfixed; -- sfixed point input
constant XMAP : STD_ULOGIC := '0') -- Map x to
return UNRESOLVED_sfixed is
variable result : UNRESOLVED_sfixed (s'range);
begin
if (s'length < 1) then
assert NO_WARNING
report "fixed_pkg"
& "TO_01(sfixed): null detected, returning NULL"
severity warning;
return NASF;
end if;
return to_fixed (to_01(to_s(s), XMAP), s'high, s'low);
end function to_01;
function Is_X (
arg : UNRESOLVED_ufixed)
return BOOLEAN is
variable argslv : STD_ULOGIC_VECTOR (arg'length-1 downto 0); -- slv
begin
argslv := to_sulv(arg);
return Is_X (argslv);
end function Is_X;
function Is_X (
arg : UNRESOLVED_sfixed)
return BOOLEAN is
variable argslv : STD_ULOGIC_VECTOR (arg'length-1 downto 0); -- slv
begin
argslv := to_sulv(arg);
return Is_X (argslv);
end function Is_X;
function To_X01 (
arg : UNRESOLVED_ufixed)
return UNRESOLVED_ufixed is
begin
return to_ufixed (To_X01(to_sulv(arg)), arg'high, arg'low);
end function To_X01;
function to_X01 (
arg : UNRESOLVED_sfixed)
return UNRESOLVED_sfixed is
begin
return to_sfixed (To_X01(to_sulv(arg)), arg'high, arg'low);
end function To_X01;
function To_X01Z (
arg : UNRESOLVED_ufixed)
return UNRESOLVED_ufixed is
begin
return to_ufixed (To_X01Z(to_sulv(arg)), arg'high, arg'low);
end function To_X01Z;
function to_X01Z (
arg : UNRESOLVED_sfixed)
return UNRESOLVED_sfixed is
begin
return to_sfixed (To_X01Z(to_sulv(arg)), arg'high, arg'low);
end function To_X01Z;
function To_UX01 (
arg : UNRESOLVED_ufixed)
return UNRESOLVED_ufixed is
begin
return to_ufixed (To_UX01(to_sulv(arg)), arg'high, arg'low);
end function To_UX01;
function to_UX01 (
arg : UNRESOLVED_sfixed)
return UNRESOLVED_sfixed is
begin
return to_sfixed (To_UX01(to_sulv(arg)), arg'high, arg'low);
end function To_UX01;
function resize (
arg : UNRESOLVED_ufixed; -- input
constant left_index : INTEGER; -- integer portion
constant right_index : INTEGER; -- size of fraction
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;
constant round_style : fixed_round_style_type := fixed_round_style)
return UNRESOLVED_ufixed is
constant arghigh : INTEGER := maximum (arg'high, arg'low);
constant arglow : INTEGER := mine (arg'high, arg'low);
variable invec : UNRESOLVED_ufixed (arghigh downto arglow);
variable result : UNRESOLVED_ufixed(left_index downto right_index) :=
(others => '0');
variable needs_rounding : BOOLEAN := false;
begin -- resize
if (arg'length < 1) or (result'length < 1) then
return NAUF;
elsif (invec'length < 1) then
return result; -- string literal value
else
invec := cleanvec(arg);
if (right_index > arghigh) then -- return top zeros
needs_rounding := (round_style = fixed_round) and
(right_index = arghigh+1);
elsif (left_index < arglow) then -- return overflow
if (overflow_style = fixed_saturate) and
(or_reduce(to_sulv(invec)) = '1') then
result := saturate (result'high, result'low); -- saturate
end if;
elsif (arghigh > left_index) then
-- wrap or saturate?
if (overflow_style = fixed_saturate and
or_reduce (to_sulv(invec(arghigh downto left_index+1))) = '1')
then
result := saturate (result'high, result'low); -- saturate
else
if (arglow >= right_index) then
result (left_index downto arglow) :=
invec(left_index downto arglow);
else
result (left_index downto right_index) :=
invec (left_index downto right_index);
needs_rounding := (round_style = fixed_round); -- round
end if;
end if;
else -- arghigh <= integer width
if (arglow >= right_index) then
result (arghigh downto arglow) := invec;
else
result (arghigh downto right_index) :=
invec (arghigh downto right_index);
needs_rounding := (round_style = fixed_round); -- round
end if;
end if;
-- Round result
if needs_rounding then
result := round_fixed (arg => result,
remainder => invec (right_index-1
downto arglow),
overflow_style => overflow_style);
end if;
return result;
end if;
end function resize;
function resize (
arg : UNRESOLVED_sfixed; -- input
constant left_index : INTEGER; -- integer portion
constant right_index : INTEGER; -- size of fraction
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;
constant round_style : fixed_round_style_type := fixed_round_style)
return UNRESOLVED_sfixed is
constant arghigh : INTEGER := maximum (arg'high, arg'low);
constant arglow : INTEGER := mine (arg'high, arg'low);
variable invec : UNRESOLVED_sfixed (arghigh downto arglow);
variable result : UNRESOLVED_sfixed(left_index downto right_index) :=
(others => '0');
variable reduced : STD_ULOGIC;
variable needs_rounding : BOOLEAN := false; -- rounding
begin -- resize
if (arg'length < 1) or (result'length < 1) then
return NASF;
elsif (invec'length < 1) then
return result; -- string literal value
else
invec := cleanvec(arg);
if (right_index > arghigh) then -- return top zeros
if (arg'low /= INTEGER'low) then -- check for a literal
result := (others => arg(arghigh)); -- sign extend
end if;
needs_rounding := (round_style = fixed_round) and
(right_index = arghigh+1);
elsif (left_index < arglow) then -- return overflow
if (overflow_style = fixed_saturate) then
reduced := or_reduce (to_sulv(invec));
if (reduced = '1') then
if (invec(arghigh) = '0') then
-- saturate POSITIVE
result := saturate (result'high, result'low);
else
-- saturate negative
result := not saturate (result'high, result'low);
end if;
-- else return 0 (input was 0)
end if;
-- else return 0 (wrap)
end if;
elsif (arghigh > left_index) then
if (invec(arghigh) = '0') then
reduced := or_reduce (to_sulv(invec(arghigh-1 downto
left_index)));
if overflow_style = fixed_saturate and reduced = '1' then
-- saturate positive
result := saturate (result'high, result'low);
else
if (right_index > arglow) then
result := invec (left_index downto right_index);
needs_rounding := (round_style = fixed_round);
else
result (left_index downto arglow) :=
invec (left_index downto arglow);
end if;
end if;
else
reduced := and_reduce (to_sulv(invec(arghigh-1 downto
left_index)));
if overflow_style = fixed_saturate and reduced = '0' then
result := not saturate (result'high, result'low);
else
if (right_index > arglow) then
result := invec (left_index downto right_index);
needs_rounding := (round_style = fixed_round);
else
result (left_index downto arglow) :=
invec (left_index downto arglow);
end if;
end if;
end if;
else -- arghigh <= integer width
if (arglow >= right_index) then
result (arghigh downto arglow) := invec;
else
result (arghigh downto right_index) :=
invec (arghigh downto right_index);
needs_rounding := (round_style = fixed_round); -- round
end if;
if (left_index > arghigh) then -- sign extend
result(left_index downto arghigh+1) := (others => invec(arghigh));
end if;
end if;
-- Round result
if (needs_rounding) then
result := round_fixed (arg => result,
remainder => invec (right_index-1
downto arglow),
overflow_style => overflow_style);
end if;
return result;
end if;
end function resize;
-- size_res functions
-- These functions compute the size from a passed variable named "size_res"
-- The only part of this variable used it it's size, it is never passed
-- to a lower level routine.
function to_ufixed (
arg : STD_ULOGIC_VECTOR; -- shifted vector
size_res : UNRESOLVED_ufixed) -- for size only
return UNRESOLVED_ufixed is
constant fw : INTEGER := mine (size_res'low, size_res'low); -- catch literals
variable result : UNRESOLVED_ufixed (size_res'left downto fw);
begin
if (result'length < 1 or arg'length < 1) then
return NAUF;
else
result := to_ufixed (arg => arg,
left_index => size_res'high,
right_index => size_res'low);
return result;
end if;
end function to_ufixed;
function to_sfixed (
arg : STD_ULOGIC_VECTOR; -- shifted vector
size_res : UNRESOLVED_sfixed) -- for size only
return UNRESOLVED_sfixed is
constant fw : INTEGER := mine (size_res'low, size_res'low); -- catch literals
variable result : UNRESOLVED_sfixed (size_res'left downto fw);
begin
if (result'length < 1 or arg'length < 1) then
return NASF;
else
result := to_sfixed (arg => arg,
left_index => size_res'high,
right_index => size_res'low);
return result;
end if;
end function to_sfixed;
function to_ufixed (
arg : NATURAL; -- integer
size_res : UNRESOLVED_ufixed; -- for size only
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;
constant round_style : fixed_round_style_type := fixed_round_style)
return UNRESOLVED_ufixed is
constant fw : INTEGER := mine (size_res'low, size_res'low); -- catch literals
variable result : UNRESOLVED_ufixed (size_res'left downto fw);
begin
if (result'length < 1) then
return NAUF;
else
result := to_ufixed (arg => arg,
left_index => size_res'high,
right_index => size_res'low,
round_style => round_style,
overflow_style => overflow_style);
return result;
end if;
end function to_ufixed;
function to_sfixed (
arg : INTEGER; -- integer
size_res : UNRESOLVED_sfixed; -- for size only
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;
constant round_style : fixed_round_style_type := fixed_round_style)
return UNRESOLVED_sfixed is
constant fw : INTEGER := mine (size_res'low, size_res'low); -- catch literals
variable result : UNRESOLVED_sfixed (size_res'left downto fw);
begin
if (result'length < 1) then
return NASF;
else
result := to_sfixed (arg => arg,
left_index => size_res'high,
right_index => size_res'low,
round_style => round_style,
overflow_style => overflow_style);
return result;
end if;
end function to_sfixed;
function to_ufixed (
arg : REAL; -- real
size_res : UNRESOLVED_ufixed; -- for size only
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;
constant round_style : fixed_round_style_type := fixed_round_style;
constant guard_bits : NATURAL := fixed_guard_bits) -- # of guard bits
return UNRESOLVED_ufixed is
constant fw : INTEGER := mine (size_res'low, size_res'low); -- catch literals
variable result : UNRESOLVED_ufixed (size_res'left downto fw);
begin
if (result'length < 1) then
return NAUF;
else
result := to_ufixed (arg => arg,
left_index => size_res'high,
right_index => size_res'low,
guard_bits => guard_bits,
round_style => round_style,
overflow_style => overflow_style);
return result;
end if;
end function to_ufixed;
function to_sfixed (
arg : REAL; -- real
size_res : UNRESOLVED_sfixed; -- for size only
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;
constant round_style : fixed_round_style_type := fixed_round_style;
constant guard_bits : NATURAL := fixed_guard_bits) -- # of guard bits
return UNRESOLVED_sfixed is
constant fw : INTEGER := mine (size_res'low, size_res'low); -- catch literals
variable result : UNRESOLVED_sfixed (size_res'left downto fw);
begin
if (result'length < 1) then
return NASF;
else
result := to_sfixed (arg => arg,
left_index => size_res'high,
right_index => size_res'low,
guard_bits => guard_bits,
round_style => round_style,
overflow_style => overflow_style);
return result;
end if;
end function to_sfixed;
function to_ufixed (
arg : UNSIGNED; -- unsigned
size_res : UNRESOLVED_ufixed; -- for size only
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;
constant round_style : fixed_round_style_type := fixed_round_style)
return UNRESOLVED_ufixed is
constant fw : INTEGER := mine (size_res'low, size_res'low); -- catch literals
variable result : UNRESOLVED_ufixed (size_res'left downto fw);
begin
if (result'length < 1 or arg'length < 1) then
return NAUF;
else
result := to_ufixed (arg => arg,
left_index => size_res'high,
right_index => size_res'low,
round_style => round_style,
overflow_style => overflow_style);
return result;
end if;
end function to_ufixed;
function to_sfixed (
arg : SIGNED; -- signed
size_res : UNRESOLVED_sfixed; -- for size only
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;
constant round_style : fixed_round_style_type := fixed_round_style)
return UNRESOLVED_sfixed is
constant fw : INTEGER := mine (size_res'low, size_res'low); -- catch literals
variable result : UNRESOLVED_sfixed (size_res'left downto fw);
begin
if (result'length < 1 or arg'length < 1) then
return NASF;
else
result := to_sfixed (arg => arg,
left_index => size_res'high,
right_index => size_res'low,
round_style => round_style,
overflow_style => overflow_style);
return result;
end if;
end function to_sfixed;
function resize (
arg : UNRESOLVED_ufixed; -- input
size_res : UNRESOLVED_ufixed; -- for size only
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;
constant round_style : fixed_round_style_type := fixed_round_style)
return UNRESOLVED_ufixed is
constant fw : INTEGER := mine (size_res'low, size_res'low); -- catch literals
variable result : UNRESOLVED_ufixed (size_res'high downto fw);
begin
if (result'length < 1 or arg'length < 1) then
return NAUF;
else
result := resize (arg => arg,
left_index => size_res'high,
right_index => size_res'low,
round_style => round_style,
overflow_style => overflow_style);
return result;
end if;
end function resize;
function resize (
arg : UNRESOLVED_sfixed; -- input
size_res : UNRESOLVED_sfixed; -- for size only
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;
constant round_style : fixed_round_style_type := fixed_round_style)
return UNRESOLVED_sfixed is
constant fw : INTEGER := mine (size_res'low, size_res'low); -- catch literals
variable result : UNRESOLVED_sfixed (size_res'high downto fw);
begin
if (result'length < 1 or arg'length < 1) then
return NASF;
else
result := resize (arg => arg,
left_index => size_res'high,
right_index => size_res'low,
round_style => round_style,
overflow_style => overflow_style);
return result;
end if;
end function resize;
-- Overloaded math functions for real
function "+" (
l : UNRESOLVED_ufixed; -- fixed point input
r : REAL)
return UNRESOLVED_ufixed is
begin
return (l + to_ufixed (r, l'high, l'low));
end function "+";
function "+" (
l : REAL;
r : UNRESOLVED_ufixed) -- fixed point input
return UNRESOLVED_ufixed is
begin
return (to_ufixed (l, r'high, r'low) + r);
end function "+";
function "+" (
l : UNRESOLVED_sfixed; -- fixed point input
r : REAL)
return UNRESOLVED_sfixed is
begin
return (l + to_sfixed (r, l'high, l'low));
end function "+";
function "+" (
l : REAL;
r : UNRESOLVED_sfixed) -- fixed point input
return UNRESOLVED_sfixed is
begin
return (to_sfixed (l, r'high, r'low) + r);
end function "+";
function "-" (
l : UNRESOLVED_ufixed; -- fixed point input
r : REAL)
return UNRESOLVED_ufixed is
begin
return (l - to_ufixed (r, l'high, l'low));
end function "-";
function "-" (
l : REAL;
r : UNRESOLVED_ufixed) -- fixed point input
return UNRESOLVED_ufixed is
begin
return (to_ufixed (l, r'high, r'low) - r);
end function "-";
function "-" (
l : UNRESOLVED_sfixed; -- fixed point input
r : REAL)
return UNRESOLVED_sfixed is
begin
return (l - to_sfixed (r, l'high, l'low));
end function "-";
function "-" (
l : REAL;
r : UNRESOLVED_sfixed) -- fixed point input
return UNRESOLVED_sfixed is
begin
return (to_sfixed (l, r'high, r'low) - r);
end function "-";
function "*" (
l : UNRESOLVED_ufixed; -- fixed point input
r : REAL)
return UNRESOLVED_ufixed is
begin
return (l * to_ufixed (r, l'high, l'low));
end function "*";
function "*" (
l : REAL;
r : UNRESOLVED_ufixed) -- fixed point input
return UNRESOLVED_ufixed is
begin
return (to_ufixed (l, r'high, r'low) * r);
end function "*";
function "*" (
l : UNRESOLVED_sfixed; -- fixed point input
r : REAL)
return UNRESOLVED_sfixed is
begin
return (l * to_sfixed (r, l'high, l'low));
end function "*";
function "*" (
l : REAL;
r : UNRESOLVED_sfixed) -- fixed point input
return UNRESOLVED_sfixed is
begin
return (to_sfixed (l, r'high, r'low) * r);
end function "*";
function "/" (
l : UNRESOLVED_ufixed; -- fixed point input
r : REAL)
return UNRESOLVED_ufixed is
begin
return (l / to_ufixed (r, l'high, l'low));
end function "/";
function "/" (
l : REAL;
r : UNRESOLVED_ufixed) -- fixed point input
return UNRESOLVED_ufixed is
begin
return (to_ufixed (l, r'high, r'low) / r);
end function "/";
function "/" (
l : UNRESOLVED_sfixed; -- fixed point input
r : REAL)
return UNRESOLVED_sfixed is
begin
return (l / to_sfixed (r, l'high, l'low));
end function "/";
function "/" (
l : REAL;
r : UNRESOLVED_sfixed) -- fixed point input
return UNRESOLVED_sfixed is
begin
return (to_sfixed (l, r'high, r'low) / r);
end function "/";
function "rem" (
l : UNRESOLVED_ufixed; -- fixed point input
r : REAL)
return UNRESOLVED_ufixed is
begin
return (l rem to_ufixed (r, l'high, l'low));
end function "rem";
function "rem" (
l : REAL;
r : UNRESOLVED_ufixed) -- fixed point input
return UNRESOLVED_ufixed is
begin
return (to_ufixed (l, r'high, r'low) rem r);
end function "rem";
function "rem" (
l : UNRESOLVED_sfixed; -- fixed point input
r : REAL)
return UNRESOLVED_sfixed is
begin
return (l rem to_sfixed (r, l'high, l'low));
end function "rem";
function "rem" (
l : REAL;
r : UNRESOLVED_sfixed) -- fixed point input
return UNRESOLVED_sfixed is
begin
return (to_sfixed (l, r'high, r'low) rem r);
end function "rem";
function "mod" (
l : UNRESOLVED_ufixed; -- fixed point input
r : REAL)
return UNRESOLVED_ufixed is
begin
return (l mod to_ufixed (r, l'high, l'low));
end function "mod";
function "mod" (
l : REAL;
r : UNRESOLVED_ufixed) -- fixed point input
return UNRESOLVED_ufixed is
begin
return (to_ufixed (l, r'high, r'low) mod r);
end function "mod";
function "mod" (
l : UNRESOLVED_sfixed; -- fixed point input
r : REAL)
return UNRESOLVED_sfixed is
begin
return (l mod to_sfixed (r, l'high, l'low));
end function "mod";
function "mod" (
l : REAL;
r : UNRESOLVED_sfixed) -- fixed point input
return UNRESOLVED_sfixed is
begin
return (to_sfixed (l, r'high, r'low) mod r);
end function "mod";
-- Overloaded math functions for integers
function "+" (
l : UNRESOLVED_ufixed; -- fixed point input
r : NATURAL)
return UNRESOLVED_ufixed is
begin
return (l + to_ufixed (r, l'high, 0));
end function "+";
function "+" (
l : NATURAL;
r : UNRESOLVED_ufixed) -- fixed point input
return UNRESOLVED_ufixed is
begin
return (to_ufixed (l, r'high, 0) + r);
end function "+";
function "+" (
l : UNRESOLVED_sfixed; -- fixed point input
r : INTEGER)
return UNRESOLVED_sfixed is
begin
return (l + to_sfixed (r, l'high, 0));
end function "+";
function "+" (
l : INTEGER;
r : UNRESOLVED_sfixed) -- fixed point input
return UNRESOLVED_sfixed is
begin
return (to_sfixed (l, r'high, 0) + r);
end function "+";
-- Overloaded functions
function "-" (
l : UNRESOLVED_ufixed; -- fixed point input
r : NATURAL)
return UNRESOLVED_ufixed is
begin
return (l - to_ufixed (r, l'high, 0));
end function "-";
function "-" (
l : NATURAL;
r : UNRESOLVED_ufixed) -- fixed point input
return UNRESOLVED_ufixed is
begin
return (to_ufixed (l, r'high, 0) - r);
end function "-";
function "-" (
l : UNRESOLVED_sfixed; -- fixed point input
r : INTEGER)
return UNRESOLVED_sfixed is
begin
return (l - to_sfixed (r, l'high, 0));
end function "-";
function "-" (
l : INTEGER;
r : UNRESOLVED_sfixed) -- fixed point input
return UNRESOLVED_sfixed is
begin
return (to_sfixed (l, r'high, 0) - r);
end function "-";
-- Overloaded functions
function "*" (
l : UNRESOLVED_ufixed; -- fixed point input
r : NATURAL)
return UNRESOLVED_ufixed is
begin
return (l * to_ufixed (r, l'high, 0));
end function "*";
function "*" (
l : NATURAL;
r : UNRESOLVED_ufixed) -- fixed point input
return UNRESOLVED_ufixed is
begin
return (to_ufixed (l, r'high, 0) * r);
end function "*";
function "*" (
l : UNRESOLVED_sfixed; -- fixed point input
r : INTEGER)
return UNRESOLVED_sfixed is
begin
return (l * to_sfixed (r, l'high, 0));
end function "*";
function "*" (
l : INTEGER;
r : UNRESOLVED_sfixed) -- fixed point input
return UNRESOLVED_sfixed is
begin
return (to_sfixed (l, r'high, 0) * r);
end function "*";
-- Overloaded functions
function "/" (
l : UNRESOLVED_ufixed; -- fixed point input
r : NATURAL)
return UNRESOLVED_ufixed is
begin
return (l / to_ufixed (r, l'high, 0));
end function "/";
function "/" (
l : NATURAL;
r : UNRESOLVED_ufixed) -- fixed point input
return UNRESOLVED_ufixed is
begin
return (to_ufixed (l, r'high, 0) / r);
end function "/";
function "/" (
l : UNRESOLVED_sfixed; -- fixed point input
r : INTEGER)
return UNRESOLVED_sfixed is
begin
return (l / to_sfixed (r, l'high, 0));
end function "/";
function "/" (
l : INTEGER;
r : UNRESOLVED_sfixed) -- fixed point input
return UNRESOLVED_sfixed is
begin
return (to_sfixed (l, r'high, 0) / r);
end function "/";
function "rem" (
l : UNRESOLVED_ufixed; -- fixed point input
r : NATURAL)
return UNRESOLVED_ufixed is
begin
return (l rem to_ufixed (r, l'high, 0));
end function "rem";
function "rem" (
l : NATURAL;
r : UNRESOLVED_ufixed) -- fixed point input
return UNRESOLVED_ufixed is
begin
return (to_ufixed (l, r'high, 0) rem r);
end function "rem";
function "rem" (
l : UNRESOLVED_sfixed; -- fixed point input
r : INTEGER)
return UNRESOLVED_sfixed is
begin
return (l rem to_sfixed (r, l'high, 0));
end function "rem";
function "rem" (
l : INTEGER;
r : UNRESOLVED_sfixed) -- fixed point input
return UNRESOLVED_sfixed is
begin
return (to_sfixed (l, r'high, 0) rem r);
end function "rem";
function "mod" (
l : UNRESOLVED_ufixed; -- fixed point input
r : NATURAL)
return UNRESOLVED_ufixed is
begin
return (l mod to_ufixed (r, l'high, 0));
end function "mod";
function "mod" (
l : NATURAL;
r : UNRESOLVED_ufixed) -- fixed point input
return UNRESOLVED_ufixed is
begin
return (to_ufixed (l, r'high, 0) mod r);
end function "mod";
function "mod" (
l : UNRESOLVED_sfixed; -- fixed point input
r : INTEGER)
return UNRESOLVED_sfixed is
begin
return (l mod to_sfixed (r, l'high, 0));
end function "mod";
function "mod" (
l : INTEGER;
r : UNRESOLVED_sfixed) -- fixed point input
return UNRESOLVED_sfixed is
begin
return (to_sfixed (l, r'high, 0) mod r);
end function "mod";
-- overloaded ufixed compare functions with integer
function "=" (
l : UNRESOLVED_ufixed;
r : NATURAL) -- fixed point input
return BOOLEAN is
begin
return (l = to_ufixed (r, l'high, l'low));
end function "=";
function "/=" (
l : UNRESOLVED_ufixed;
r : NATURAL) -- fixed point input
return BOOLEAN is
begin
return (l /= to_ufixed (r, l'high, l'low));
end function "/=";
function ">=" (
l : UNRESOLVED_ufixed;
r : NATURAL) -- fixed point input
return BOOLEAN is
begin
return (l >= to_ufixed (r, l'high, l'low));
end function ">=";
function "<=" (
l : UNRESOLVED_ufixed;
r : NATURAL) -- fixed point input
return BOOLEAN is
begin
return (l <= to_ufixed (r, l'high, l'low));
end function "<=";
function ">" (
l : UNRESOLVED_ufixed;
r : NATURAL) -- fixed point input
return BOOLEAN is
begin
return (l > to_ufixed (r, l'high, l'low));
end function ">";
function "<" (
l : UNRESOLVED_ufixed;
r : NATURAL) -- fixed point input
return BOOLEAN is
begin
return (l < to_ufixed (r, l'high, l'low));
end function "<";
function \?=\ (
l : UNRESOLVED_ufixed;
r : NATURAL) -- fixed point input
return STD_ULOGIC is
begin
return \?=\ (l, to_ufixed (r, l'high, l'low));
end function \?=\;
function \?/=\ (
l : UNRESOLVED_ufixed;
r : NATURAL) -- fixed point input
return STD_ULOGIC is
begin
return \?/=\ (l, to_ufixed (r, l'high, l'low));
end function \?/=\;
function \?>=\ (
l : UNRESOLVED_ufixed;
r : NATURAL) -- fixed point input
return STD_ULOGIC is
begin
return \?>=\ (l, to_ufixed (r, l'high, l'low));
end function \?>=\;
function \?<=\ (
l : UNRESOLVED_ufixed;
r : NATURAL) -- fixed point input
return STD_ULOGIC is
begin
return \?<=\ (l, to_ufixed (r, l'high, l'low));
end function \?<=\;
function \?>\ (
l : UNRESOLVED_ufixed;
r : NATURAL) -- fixed point input
return STD_ULOGIC is
begin
return \?>\ (l, to_ufixed (r, l'high, l'low));
end function \?>\;
function \?<\ (
l : UNRESOLVED_ufixed;
r : NATURAL) -- fixed point input
return STD_ULOGIC is
begin
return \?<\ (l, to_ufixed (r, l'high, l'low));
end function \?<\;
function maximum (
l : UNRESOLVED_ufixed; -- fixed point input
r : NATURAL)
return UNRESOLVED_ufixed is
begin
return maximum (l, to_ufixed (r, l'high, l'low));
end function maximum;
function minimum (
l : UNRESOLVED_ufixed; -- fixed point input
r : NATURAL)
return UNRESOLVED_ufixed is
begin
return minimum (l, to_ufixed (r, l'high, l'low));
end function minimum;
-- NATURAL to ufixed
function "=" (
l : NATURAL;
r : UNRESOLVED_ufixed) -- fixed point input
return BOOLEAN is
begin
return (to_ufixed (l, r'high, r'low) = r);
end function "=";
function "/=" (
l : NATURAL;
r : UNRESOLVED_ufixed) -- fixed point input
return BOOLEAN is
begin
return (to_ufixed (l, r'high, r'low) /= r);
end function "/=";
function ">=" (
l : NATURAL;
r : UNRESOLVED_ufixed) -- fixed point input
return BOOLEAN is
begin
return (to_ufixed (l, r'high, r'low) >= r);
end function ">=";
function "<=" (
l : NATURAL;
r : UNRESOLVED_ufixed) -- fixed point input
return BOOLEAN is
begin
return (to_ufixed (l, r'high, r'low) <= r);
end function "<=";
function ">" (
l : NATURAL;
r : UNRESOLVED_ufixed) -- fixed point input
return BOOLEAN is
begin
return (to_ufixed (l, r'high, r'low) > r);
end function ">";
function "<" (
l : NATURAL;
r : UNRESOLVED_ufixed) -- fixed point input
return BOOLEAN is
begin
return (to_ufixed (l, r'high, r'low) < r);
end function "<";
function \?=\ (
l : NATURAL;
r : UNRESOLVED_ufixed) -- fixed point input
return STD_ULOGIC is
begin
return \?=\ (to_ufixed (l, r'high, r'low), r);
end function \?=\;
function \?/=\ (
l : NATURAL;
r : UNRESOLVED_ufixed) -- fixed point input
return STD_ULOGIC is
begin
return \?/=\ (to_ufixed (l, r'high, r'low), r);
end function \?/=\;
function \?>=\ (
l : NATURAL;
r : UNRESOLVED_ufixed) -- fixed point input
return STD_ULOGIC is
begin
return \?>=\ (to_ufixed (l, r'high, r'low), r);
end function \?>=\;
function \?<=\ (
l : NATURAL;
r : UNRESOLVED_ufixed) -- fixed point input
return STD_ULOGIC is
begin
return \?<=\ (to_ufixed (l, r'high, r'low), r);
end function \?<=\;
function \?>\ (
l : NATURAL;
r : UNRESOLVED_ufixed) -- fixed point input
return STD_ULOGIC is
begin
return \?>\ (to_ufixed (l, r'high, r'low), r);
end function \?>\;
function \?<\ (
l : NATURAL;
r : UNRESOLVED_ufixed) -- fixed point input
return STD_ULOGIC is
begin
return \?<\ (to_ufixed (l, r'high, r'low), r);
end function \?<\;
function maximum (
l : NATURAL;
r : UNRESOLVED_ufixed) -- fixed point input
return UNRESOLVED_ufixed is
begin
return maximum (to_ufixed (l, r'high, r'low), r);
end function maximum;
function minimum (
l : NATURAL;
r : UNRESOLVED_ufixed) -- fixed point input
return UNRESOLVED_ufixed is
begin
return minimum (to_ufixed (l, r'high, r'low), r);
end function minimum;
-- overloaded ufixed compare functions with real
function "=" (
l : UNRESOLVED_ufixed;
r : REAL)
return BOOLEAN is
begin
return (l = to_ufixed (r, l'high, l'low));
end function "=";
function "/=" (
l : UNRESOLVED_ufixed;
r : REAL)
return BOOLEAN is
begin
return (l /= to_ufixed (r, l'high, l'low));
end function "/=";
function ">=" (
l : UNRESOLVED_ufixed;
r : REAL)
return BOOLEAN is
begin
return (l >= to_ufixed (r, l'high, l'low));
end function ">=";
function "<=" (
l : UNRESOLVED_ufixed;
r : REAL)
return BOOLEAN is
begin
return (l <= to_ufixed (r, l'high, l'low));
end function "<=";
function ">" (
l : UNRESOLVED_ufixed;
r : REAL)
return BOOLEAN is
begin
return (l > to_ufixed (r, l'high, l'low));
end function ">";
function "<" (
l : UNRESOLVED_ufixed;
r : REAL)
return BOOLEAN is
begin
return (l < to_ufixed (r, l'high, l'low));
end function "<";
function \?=\ (
l : UNRESOLVED_ufixed;
r : REAL)
return STD_ULOGIC is
begin
return \?=\ (l, to_ufixed (r, l'high, l'low));
end function \?=\;
function \?/=\ (
l : UNRESOLVED_ufixed;
r : REAL)
return STD_ULOGIC is
begin
return \?/=\ (l, to_ufixed (r, l'high, l'low));
end function \?/=\;
function \?>=\ (
l : UNRESOLVED_ufixed;
r : REAL)
return STD_ULOGIC is
begin
return \?>=\ (l, to_ufixed (r, l'high, l'low));
end function \?>=\;
function \?<=\ (
l : UNRESOLVED_ufixed;
r : REAL)
return STD_ULOGIC is
begin
return \?<=\ (l, to_ufixed (r, l'high, l'low));
end function \?<=\;
function \?>\ (
l : UNRESOLVED_ufixed;
r : REAL)
return STD_ULOGIC is
begin
return \?>\ (l, to_ufixed (r, l'high, l'low));
end function \?>\;
function \?<\ (
l : UNRESOLVED_ufixed;
r : REAL)
return STD_ULOGIC is
begin
return \?<\ (l, to_ufixed (r, l'high, l'low));
end function \?<\;
function maximum (
l : UNRESOLVED_ufixed;
r : REAL)
return UNRESOLVED_ufixed is
begin
return maximum (l, to_ufixed (r, l'high, l'low));
end function maximum;
function minimum (
l : UNRESOLVED_ufixed;
r : REAL)
return UNRESOLVED_ufixed is
begin
return minimum (l, to_ufixed (r, l'high, l'low));
end function minimum;
-- real and ufixed
function "=" (
l : REAL;
r : UNRESOLVED_ufixed) -- fixed point input
return BOOLEAN is
begin
return (to_ufixed (l, r'high, r'low) = r);
end function "=";
function "/=" (
l : REAL;
r : UNRESOLVED_ufixed) -- fixed point input
return BOOLEAN is
begin
return (to_ufixed (l, r'high, r'low) /= r);
end function "/=";
function ">=" (
l : REAL;
r : UNRESOLVED_ufixed) -- fixed point input
return BOOLEAN is
begin
return (to_ufixed (l, r'high, r'low) >= r);
end function ">=";
function "<=" (
l : REAL;
r : UNRESOLVED_ufixed) -- fixed point input
return BOOLEAN is
begin
return (to_ufixed (l, r'high, r'low) <= r);
end function "<=";
function ">" (
l : REAL;
r : UNRESOLVED_ufixed) -- fixed point input
return BOOLEAN is
begin
return (to_ufixed (l, r'high, r'low) > r);
end function ">";
function "<" (
l : REAL;
r : UNRESOLVED_ufixed) -- fixed point input
return BOOLEAN is
begin
return (to_ufixed (l, r'high, r'low) < r);
end function "<";
function \?=\ (
l : REAL;
r : UNRESOLVED_ufixed) -- fixed point input
return STD_ULOGIC is
begin
return \?=\ (to_ufixed (l, r'high, r'low), r);
end function \?=\;
function \?/=\ (
l : REAL;
r : UNRESOLVED_ufixed) -- fixed point input
return STD_ULOGIC is
begin
return \?/=\ (to_ufixed (l, r'high, r'low), r);
end function \?/=\;
function \?>=\ (
l : REAL;
r : UNRESOLVED_ufixed) -- fixed point input
return STD_ULOGIC is
begin
return \?>=\ (to_ufixed (l, r'high, r'low), r);
end function \?>=\;
function \?<=\ (
l : REAL;
r : UNRESOLVED_ufixed) -- fixed point input
return STD_ULOGIC is
begin
return \?<=\ (to_ufixed (l, r'high, r'low), r);
end function \?<=\;
function \?>\ (
l : REAL;
r : UNRESOLVED_ufixed) -- fixed point input
return STD_ULOGIC is
begin
return \?>\ (to_ufixed (l, r'high, r'low), r);
end function \?>\;
function \?<\ (
l : REAL;
r : UNRESOLVED_ufixed) -- fixed point input
return STD_ULOGIC is
begin
return \?<\ (to_ufixed (l, r'high, r'low), r);
end function \?<\;
function maximum (
l : REAL;
r : UNRESOLVED_ufixed) -- fixed point input
return UNRESOLVED_ufixed is
begin
return maximum (to_ufixed (l, r'high, r'low), r);
end function maximum;
function minimum (
l : REAL;
r : UNRESOLVED_ufixed) -- fixed point input
return UNRESOLVED_ufixed is
begin
return minimum (to_ufixed (l, r'high, r'low), r);
end function minimum;
-- overloaded sfixed compare functions with integer
function "=" (
l : UNRESOLVED_sfixed;
r : INTEGER)
return BOOLEAN is
begin
return (l = to_sfixed (r, l'high, l'low));
end function "=";
function "/=" (
l : UNRESOLVED_sfixed;
r : INTEGER)
return BOOLEAN is
begin
return (l /= to_sfixed (r, l'high, l'low));
end function "/=";
function ">=" (
l : UNRESOLVED_sfixed;
r : INTEGER)
return BOOLEAN is
begin
return (l >= to_sfixed (r, l'high, l'low));
end function ">=";
function "<=" (
l : UNRESOLVED_sfixed;
r : INTEGER)
return BOOLEAN is
begin
return (l <= to_sfixed (r, l'high, l'low));
end function "<=";
function ">" (
l : UNRESOLVED_sfixed;
r : INTEGER)
return BOOLEAN is
begin
return (l > to_sfixed (r, l'high, l'low));
end function ">";
function "<" (
l : UNRESOLVED_sfixed;
r : INTEGER)
return BOOLEAN is
begin
return (l < to_sfixed (r, l'high, l'low));
end function "<";
function \?=\ (
l : UNRESOLVED_sfixed;
r : INTEGER)
return STD_ULOGIC is
begin
return \?=\ (l, to_sfixed (r, l'high, l'low));
end function \?=\;
function \?/=\ (
l : UNRESOLVED_sfixed;
r : INTEGER)
return STD_ULOGIC is
begin
return \?/=\ (l, to_sfixed (r, l'high, l'low));
end function \?/=\;
function \?>=\ (
l : UNRESOLVED_sfixed;
r : INTEGER)
return STD_ULOGIC is
begin
return \?>=\ (l, to_sfixed (r, l'high, l'low));
end function \?>=\;
function \?<=\ (
l : UNRESOLVED_sfixed;
r : INTEGER)
return STD_ULOGIC is
begin
return \?<=\ (l, to_sfixed (r, l'high, l'low));
end function \?<=\;
function \?>\ (
l : UNRESOLVED_sfixed;
r : INTEGER)
return STD_ULOGIC is
begin
return \?>\ (l, to_sfixed (r, l'high, l'low));
end function \?>\;
function \?<\ (
l : UNRESOLVED_sfixed;
r : INTEGER)
return STD_ULOGIC is
begin
return \?<\ (l, to_sfixed (r, l'high, l'low));
end function \?<\;
function maximum (
l : UNRESOLVED_sfixed;
r : INTEGER)
return UNRESOLVED_sfixed is
begin
return maximum (l, to_sfixed (r, l'high, l'low));
end function maximum;
function minimum (
l : UNRESOLVED_sfixed;
r : INTEGER)
return UNRESOLVED_sfixed is
begin
return minimum (l, to_sfixed (r, l'high, l'low));
end function minimum;
-- integer and sfixed
function "=" (
l : INTEGER;
r : UNRESOLVED_sfixed) -- fixed point input
return BOOLEAN is
begin
return (to_sfixed (l, r'high, r'low) = r);
end function "=";
function "/=" (
l : INTEGER;
r : UNRESOLVED_sfixed) -- fixed point input
return BOOLEAN is
begin
return (to_sfixed (l, r'high, r'low) /= r);
end function "/=";
function ">=" (
l : INTEGER;
r : UNRESOLVED_sfixed) -- fixed point input
return BOOLEAN is
begin
return (to_sfixed (l, r'high, r'low) >= r);
end function ">=";
function "<=" (
l : INTEGER;
r : UNRESOLVED_sfixed) -- fixed point input
return BOOLEAN is
begin
return (to_sfixed (l, r'high, r'low) <= r);
end function "<=";
function ">" (
l : INTEGER;
r : UNRESOLVED_sfixed) -- fixed point input
return BOOLEAN is
begin
return (to_sfixed (l, r'high, r'low) > r);
end function ">";
function "<" (
l : INTEGER;
r : UNRESOLVED_sfixed) -- fixed point input
return BOOLEAN is
begin
return (to_sfixed (l, r'high, r'low) < r);
end function "<";
function \?=\ (
l : INTEGER;
r : UNRESOLVED_sfixed) -- fixed point input
return STD_ULOGIC is
begin
return \?=\ (to_sfixed (l, r'high, r'low), r);
end function \?=\;
function \?/=\ (
l : INTEGER;
r : UNRESOLVED_sfixed) -- fixed point input
return STD_ULOGIC is
begin
return \?/=\ (to_sfixed (l, r'high, r'low), r);
end function \?/=\;
function \?>=\ (
l : INTEGER;
r : UNRESOLVED_sfixed) -- fixed point input
return STD_ULOGIC is
begin
return \?>=\ (to_sfixed (l, r'high, r'low), r);
end function \?>=\;
function \?<=\ (
l : INTEGER;
r : UNRESOLVED_sfixed) -- fixed point input
return STD_ULOGIC is
begin
return \?<=\ (to_sfixed (l, r'high, r'low), r);
end function \?<=\;
function \?>\ (
l : INTEGER;
r : UNRESOLVED_sfixed) -- fixed point input
return STD_ULOGIC is
begin
return \?>\ (to_sfixed (l, r'high, r'low), r);
end function \?>\;
function \?<\ (
l : INTEGER;
r : UNRESOLVED_sfixed) -- fixed point input
return STD_ULOGIC is
begin
return \?<\ (to_sfixed (l, r'high, r'low), r);
end function \?<\;
function maximum (
l : INTEGER;
r : UNRESOLVED_sfixed)
return UNRESOLVED_sfixed is
begin
return maximum (to_sfixed (l, r'high, r'low), r);
end function maximum;
function minimum (
l : INTEGER;
r : UNRESOLVED_sfixed)
return UNRESOLVED_sfixed is
begin
return minimum (to_sfixed (l, r'high, r'low), r);
end function minimum;
-- overloaded sfixed compare functions with real
function "=" (
l : UNRESOLVED_sfixed;
r : REAL)
return BOOLEAN is
begin
return (l = to_sfixed (r, l'high, l'low));
end function "=";
function "/=" (
l : UNRESOLVED_sfixed;
r : REAL)
return BOOLEAN is
begin
return (l /= to_sfixed (r, l'high, l'low));
end function "/=";
function ">=" (
l : UNRESOLVED_sfixed;
r : REAL)
return BOOLEAN is
begin
return (l >= to_sfixed (r, l'high, l'low));
end function ">=";
function "<=" (
l : UNRESOLVED_sfixed;
r : REAL)
return BOOLEAN is
begin
return (l <= to_sfixed (r, l'high, l'low));
end function "<=";
function ">" (
l : UNRESOLVED_sfixed;
r : REAL)
return BOOLEAN is
begin
return (l > to_sfixed (r, l'high, l'low));
end function ">";
function "<" (
l : UNRESOLVED_sfixed;
r : REAL)
return BOOLEAN is
begin
return (l < to_sfixed (r, l'high, l'low));
end function "<";
function \?=\ (
l : UNRESOLVED_sfixed;
r : REAL)
return STD_ULOGIC is
begin
return \?=\ (l, to_sfixed (r, l'high, l'low));
end function \?=\;
function \?/=\ (
l : UNRESOLVED_sfixed;
r : REAL)
return STD_ULOGIC is
begin
return \?/=\ (l, to_sfixed (r, l'high, l'low));
end function \?/=\;
function \?>=\ (
l : UNRESOLVED_sfixed;
r : REAL)
return STD_ULOGIC is
begin
return \?>=\ (l, to_sfixed (r, l'high, l'low));
end function \?>=\;
function \?<=\ (
l : UNRESOLVED_sfixed;
r : REAL)
return STD_ULOGIC is
begin
return \?<=\ (l, to_sfixed (r, l'high, l'low));
end function \?<=\;
function \?>\ (
l : UNRESOLVED_sfixed;
r : REAL)
return STD_ULOGIC is
begin
return \?>\ (l, to_sfixed (r, l'high, l'low));
end function \?>\;
function \?<\ (
l : UNRESOLVED_sfixed;
r : REAL)
return STD_ULOGIC is
begin
return \?<\ (l, to_sfixed (r, l'high, l'low));
end function \?<\;
function maximum (
l : UNRESOLVED_sfixed;
r : REAL)
return UNRESOLVED_sfixed is
begin
return maximum (l, to_sfixed (r, l'high, l'low));
end function maximum;
function minimum (
l : UNRESOLVED_sfixed;
r : REAL)
return UNRESOLVED_sfixed is
begin
return minimum (l, to_sfixed (r, l'high, l'low));
end function minimum;
-- REAL and sfixed
function "=" (
l : REAL;
r : UNRESOLVED_sfixed) -- fixed point input
return BOOLEAN is
begin
return (to_sfixed (l, r'high, r'low) = r);
end function "=";
function "/=" (
l : REAL;
r : UNRESOLVED_sfixed) -- fixed point input
return BOOLEAN is
begin
return (to_sfixed (l, r'high, r'low) /= r);
end function "/=";
function ">=" (
l : REAL;
r : UNRESOLVED_sfixed) -- fixed point input
return BOOLEAN is
begin
return (to_sfixed (l, r'high, r'low) >= r);
end function ">=";
function "<=" (
l : REAL;
r : UNRESOLVED_sfixed) -- fixed point input
return BOOLEAN is
begin
return (to_sfixed (l, r'high, r'low) <= r);
end function "<=";
function ">" (
l : REAL;
r : UNRESOLVED_sfixed) -- fixed point input
return BOOLEAN is
begin
return (to_sfixed (l, r'high, r'low) > r);
end function ">";
function "<" (
l : REAL;
r : UNRESOLVED_sfixed) -- fixed point input
return BOOLEAN is
begin
return (to_sfixed (l, r'high, r'low) < r);
end function "<";
function \?=\ (
l : REAL;
r : UNRESOLVED_sfixed) -- fixed point input
return STD_ULOGIC is
begin
return \?=\ (to_sfixed (l, r'high, r'low), r);
end function \?=\;
function \?/=\ (
l : REAL;
r : UNRESOLVED_sfixed) -- fixed point input
return STD_ULOGIC is
begin
return \?/=\ (to_sfixed (l, r'high, r'low), r);
end function \?/=\;
function \?>=\ (
l : REAL;
r : UNRESOLVED_sfixed) -- fixed point input
return STD_ULOGIC is
begin
return \?>=\ (to_sfixed (l, r'high, r'low), r);
end function \?>=\;
function \?<=\ (
l : REAL;
r : UNRESOLVED_sfixed) -- fixed point input
return STD_ULOGIC is
begin
return \?<=\ (to_sfixed (l, r'high, r'low), r);
end function \?<=\;
function \?>\ (
l : REAL;
r : UNRESOLVED_sfixed) -- fixed point input
return STD_ULOGIC is
begin
return \?>\ (to_sfixed (l, r'high, r'low), r);
end function \?>\;
function \?<\ (
l : REAL;
r : UNRESOLVED_sfixed) -- fixed point input
return STD_ULOGIC is
begin
return \?<\ (to_sfixed (l, r'high, r'low), r);
end function \?<\;
function maximum (
l : REAL;
r : UNRESOLVED_sfixed)
return UNRESOLVED_sfixed is
begin
return maximum (to_sfixed (l, r'high, r'low), r);
end function maximum;
function minimum (
l : REAL;
r : UNRESOLVED_sfixed)
return UNRESOLVED_sfixed is
begin
return minimum (to_sfixed (l, r'high, r'low), r);
end function minimum;
-- rtl_synthesis off
-- pragma synthesis_off
-- copied from std_logic_textio
type MVL9plus is ('U', 'X', '0', '1', 'Z', 'W', 'L', 'H', '-', error);
type char_indexed_by_MVL9 is array (STD_ULOGIC) of CHARACTER;
type MVL9_indexed_by_char is array (CHARACTER) of STD_ULOGIC;
type MVL9plus_indexed_by_char is array (CHARACTER) of MVL9plus;
constant MVL9_to_char : char_indexed_by_MVL9 := "UX01ZWLH-";
constant char_to_MVL9 : MVL9_indexed_by_char :=
('U' => 'U', 'X' => 'X', '0' => '0', '1' => '1', 'Z' => 'Z',
'W' => 'W', 'L' => 'L', 'H' => 'H', '-' => '-', others => 'U');
constant char_to_MVL9plus : MVL9plus_indexed_by_char :=
('U' => 'U', 'X' => 'X', '0' => '0', '1' => '1', 'Z' => 'Z',
'W' => 'W', 'L' => 'L', 'H' => 'H', '-' => '-', others => error);
constant NBSP : CHARACTER := CHARACTER'val(160); -- space character
constant NUS : STRING(2 to 1) := (others => ' ');
-- %%% Replicated Textio functions
procedure Char2TriBits (C : CHARACTER;
RESULT : out STD_ULOGIC_VECTOR(2 downto 0);
GOOD : out BOOLEAN;
ISSUE_ERROR : in BOOLEAN) is
begin
case c is
when '0' => result := o"0"; good := true;
when '1' => result := o"1"; good := true;
when '2' => result := o"2"; good := true;
when '3' => result := o"3"; good := true;
when '4' => result := o"4"; good := true;
when '5' => result := o"5"; good := true;
when '6' => result := o"6"; good := true;
when '7' => result := o"7"; good := true;
when 'Z' => result := "ZZZ"; good := true;
when 'X' => result := "XXX"; good := true;
when others =>
assert not ISSUE_ERROR
report "fixed_pkg"
& "OREAD Error: Read a '" & c &
"', expected an Octal character (0-7)."
severity error;
result := "UUU";
good := false;
end case;
end procedure Char2TriBits;
-- Hex Read and Write procedures for STD_ULOGIC_VECTOR.
-- Modified from the original to be more forgiving.
procedure Char2QuadBits (C : CHARACTER;
RESULT : out STD_ULOGIC_VECTOR(3 downto 0);
GOOD : out BOOLEAN;
ISSUE_ERROR : in BOOLEAN) is
begin
case c is
when '0' => result := x"0"; good := true;
when '1' => result := x"1"; good := true;
when '2' => result := x"2"; good := true;
when '3' => result := x"3"; good := true;
when '4' => result := x"4"; good := true;
when '5' => result := x"5"; good := true;
when '6' => result := x"6"; good := true;
when '7' => result := x"7"; good := true;
when '8' => result := x"8"; good := true;
when '9' => result := x"9"; good := true;
when 'A' | 'a' => result := x"A"; good := true;
when 'B' | 'b' => result := x"B"; good := true;
when 'C' | 'c' => result := x"C"; good := true;
when 'D' | 'd' => result := x"D"; good := true;
when 'E' | 'e' => result := x"E"; good := true;
when 'F' | 'f' => result := x"F"; good := true;
when 'Z' => result := "ZZZZ"; good := true;
when 'X' => result := "XXXX"; good := true;
when others =>
assert not ISSUE_ERROR
report "fixed_pkg"
& "HREAD Error: Read a '" & c &
"', expected a Hex character (0-F)."
severity error;
result := "UUUU";
good := false;
end case;
end procedure Char2QuadBits;
-- purpose: Skips white space
procedure skip_whitespace (
L : inout LINE) is
variable readOk : BOOLEAN;
variable c : CHARACTER;
begin
while L /= null and L.all'length /= 0 loop
if (L.all(1) = ' ' or L.all(1) = NBSP or L.all(1) = HT) then
read (l, c, readOk);
else
exit;
end if;
end loop;
end procedure skip_whitespace;
function to_ostring (value : STD_ULOGIC_VECTOR) return STRING is
constant ne : INTEGER := (value'length+2)/3;
variable pad : STD_ULOGIC_VECTOR(0 to (ne*3 - value'length) - 1);
variable ivalue : STD_ULOGIC_VECTOR(0 to ne*3 - 1);
variable result : STRING(1 to ne);
variable tri : STD_ULOGIC_VECTOR(0 to 2);
begin
if value'length < 1 then
return NUS;
else
if value (value'left) = 'Z' then
pad := (others => 'Z');
else
pad := (others => '0');
end if;
ivalue := pad & value;
for i in 0 to ne-1 loop
tri := To_X01Z(ivalue(3*i to 3*i+2));
case tri is
when o"0" => result(i+1) := '0';
when o"1" => result(i+1) := '1';
when o"2" => result(i+1) := '2';
when o"3" => result(i+1) := '3';
when o"4" => result(i+1) := '4';
when o"5" => result(i+1) := '5';
when o"6" => result(i+1) := '6';
when o"7" => result(i+1) := '7';
when "ZZZ" => result(i+1) := 'Z';
when others => result(i+1) := 'X';
end case;
end loop;
return result;
end if;
end function to_ostring;
-------------------------------------------------------------------
function to_hstring (value : STD_ULOGIC_VECTOR) return STRING is
constant ne : INTEGER := (value'length+3)/4;
variable pad : STD_ULOGIC_VECTOR(0 to (ne*4 - value'length) - 1);
variable ivalue : STD_ULOGIC_VECTOR(0 to ne*4 - 1);
variable result : STRING(1 to ne);
variable quad : STD_ULOGIC_VECTOR(0 to 3);
begin
if value'length < 1 then
return NUS;
else
if value (value'left) = 'Z' then
pad := (others => 'Z');
else
pad := (others => '0');
end if;
ivalue := pad & value;
for i in 0 to ne-1 loop
quad := To_X01Z(ivalue(4*i to 4*i+3));
case quad is
when x"0" => result(i+1) := '0';
when x"1" => result(i+1) := '1';
when x"2" => result(i+1) := '2';
when x"3" => result(i+1) := '3';
when x"4" => result(i+1) := '4';
when x"5" => result(i+1) := '5';
when x"6" => result(i+1) := '6';
when x"7" => result(i+1) := '7';
when x"8" => result(i+1) := '8';
when x"9" => result(i+1) := '9';
when x"A" => result(i+1) := 'A';
when x"B" => result(i+1) := 'B';
when x"C" => result(i+1) := 'C';
when x"D" => result(i+1) := 'D';
when x"E" => result(i+1) := 'E';
when x"F" => result(i+1) := 'F';
when "ZZZZ" => result(i+1) := 'Z';
when others => result(i+1) := 'X';
end case;
end loop;
return result;
end if;
end function to_hstring;
-- %%% END replicated textio functions
-- purpose: writes fixed point into a line
procedure write (
L : inout LINE; -- input line
VALUE : in UNRESOLVED_ufixed; -- fixed point input
JUSTIFIED : in SIDE := right;
FIELD : in WIDTH := 0) is
variable s : STRING(1 to value'length +1) := (others => ' ');
variable sindx : INTEGER;
begin -- function write Example: 0011.1100
sindx := 1;
for i in value'high downto value'low loop
if i = -1 then
s(sindx) := '.';
sindx := sindx + 1;
end if;
s(sindx) := MVL9_to_char(STD_ULOGIC(value(i)));
sindx := sindx + 1;
end loop;
write(l, s, justified, field);
end procedure write;
-- purpose: writes fixed point into a line
procedure write (
L : inout LINE; -- input line
VALUE : in UNRESOLVED_sfixed; -- fixed point input
JUSTIFIED : in SIDE := right;
FIELD : in WIDTH := 0) is
variable s : STRING(1 to value'length +1);
variable sindx : INTEGER;
begin -- function write Example: 0011.1100
sindx := 1;
for i in value'high downto value'low loop
if i = -1 then
s(sindx) := '.';
sindx := sindx + 1;
end if;
s(sindx) := MVL9_to_char(STD_ULOGIC(value(i)));
sindx := sindx + 1;
end loop;
write(l, s, justified, field);
end procedure write;
procedure READ(L : inout LINE;
VALUE : out UNRESOLVED_ufixed) is
-- Possible data: 00000.0000000
-- 000000000000
variable c : CHARACTER;
variable readOk : BOOLEAN;
variable i : INTEGER; -- index variable
variable mv : ufixed (VALUE'range);
variable lastu : BOOLEAN := false; -- last character was an "_"
variable founddot : BOOLEAN := false; -- found a "."
begin -- READ
VALUE := (VALUE'range => 'U');
Skip_whitespace (L);
if VALUE'length > 0 then -- non Null input string
read (l, c, readOk);
i := value'high;
while i >= VALUE'low loop
if readOk = false then -- Bail out if there was a bad read
report "fixed_pkg" & "READ(ufixed) "
& "End of string encountered"
severity error;
return;
elsif c = '_' then
if i = value'high then
report "fixed_pkg" & "READ(ufixed) "
& "String begins with an ""_""" severity error;
return;
elsif lastu then
report "fixed_pkg" & "READ(ufixed) "
& "Two underscores detected in input string ""__"""
severity error;
return;
else
lastu := true;
end if;
elsif c = '.' then -- binary point
if founddot then
report "fixed_pkg" & "READ(ufixed) "
& "Two binary points found in input string" severity error;
return;
elsif i /= -1 then -- Seperator in the wrong spot
report "fixed_pkg" & "READ(ufixed) "
& "Decimal point does not match number format "
severity error;
return;
end if;
founddot := true;
lastu := false;
elsif c = ' ' or c = NBSP or c = HT then -- reading done.
report "fixed_pkg" & "READ(ufixed) "
& "Short read, Space encounted in input string"
severity error;
return;
elsif char_to_MVL9plus(c) = error then
report "fixed_pkg" & "READ(ufixed) "
& "Character '" &
c & "' read, expected STD_ULOGIC literal."
severity error;
return;
else
mv(i) := char_to_MVL9(c);
i := i - 1;
if i < mv'low then
VALUE := mv;
return;
end if;
lastu := false;
end if;
read(L, c, readOk);
end loop;
end if;
end procedure READ;
procedure READ(L : inout LINE;
VALUE : out UNRESOLVED_ufixed;
GOOD : out BOOLEAN) is
-- Possible data: 00000.0000000
-- 000000000000
variable c : CHARACTER;
variable readOk : BOOLEAN;
variable mv : ufixed (VALUE'range);
variable i : INTEGER; -- index variable
variable lastu : BOOLEAN := false; -- last character was an "_"
variable founddot : BOOLEAN := false; -- found a "."
begin -- READ
VALUE := (VALUE'range => 'U');
Skip_whitespace (L);
if VALUE'length > 0 then
read (l, c, readOk);
i := value'high;
GOOD := false;
while i >= VALUE'low loop
if not readOk then -- Bail out if there was a bad read
return;
elsif c = '_' then
if i = value'high then -- Begins with an "_"
return;
elsif lastu then -- "__" detected
return;
else
lastu := true;
end if;
elsif c = '.' then -- binary point
if founddot then
return;
elsif i /= -1 then -- Seperator in the wrong spot
return;
end if;
founddot := true;
lastu := false;
elsif (char_to_MVL9plus(c) = error) then -- Illegal character/short read
return;
else
mv(i) := char_to_MVL9(c);
i := i - 1;
if i < mv'low then -- reading done
GOOD := true;
VALUE := mv;
return;
end if;
lastu := false;
end if;
read(L, c, readOk);
end loop;
else
GOOD := true; -- read into a null array
end if;
end procedure READ;
procedure READ(L : inout LINE;
VALUE : out UNRESOLVED_sfixed) is
variable c : CHARACTER;
variable readOk : BOOLEAN;
variable i : INTEGER; -- index variable
variable mv : sfixed (VALUE'range);
variable lastu : BOOLEAN := false; -- last character was an "_"
variable founddot : BOOLEAN := false; -- found a "."
begin -- READ
VALUE := (VALUE'range => 'U');
Skip_whitespace (L);
if VALUE'length > 0 then -- non Null input string
read (l, c, readOk);
i := value'high;
while i >= VALUE'low loop
if readOk = false then -- Bail out if there was a bad read
report "fixed_pkg" & "READ(sfixed) "
& "End of string encountered"
severity error;
return;
elsif c = '_' then
if i = value'high then
report "fixed_pkg" & "READ(sfixed) "
& "String begins with an ""_""" severity error;
return;
elsif lastu then
report "fixed_pkg" & "READ(sfixed) "
& "Two underscores detected in input string ""__"""
severity error;
return;
else
lastu := true;
end if;
elsif c = '.' then -- binary point
if founddot then
report "fixed_pkg" & "READ(sfixed) "
& "Two binary points found in input string" severity error;
return;
elsif i /= -1 then -- Seperator in the wrong spot
report "fixed_pkg" & "READ(sfixed) "
& "Decimal point does not match number format "
severity error;
return;
end if;
founddot := true;
lastu := false;
elsif c = ' ' or c = NBSP or c = HT then -- reading done.
report "fixed_pkg" & "READ(sfixed) "
& "Short read, Space encounted in input string"
severity error;
return;
elsif char_to_MVL9plus(c) = error then
report "fixed_pkg" & "READ(sfixed) "
& "Character '" &
c & "' read, expected STD_ULOGIC literal."
severity error;
return;
else
mv(i) := char_to_MVL9(c);
i := i - 1;
if i < mv'low then
VALUE := mv;
return;
end if;
lastu := false;
end if;
read(L, c, readOk);
end loop;
end if;
end procedure READ;
procedure READ(L : inout LINE;
VALUE : out UNRESOLVED_sfixed;
GOOD : out BOOLEAN) is
variable value_ufixed : UNRESOLVED_ufixed (VALUE'range);
begin -- READ
READ (L => L, VALUE => value_ufixed, GOOD => GOOD);
VALUE := UNRESOLVED_sfixed (value_ufixed);
end procedure READ;
-- octal read and write
procedure owrite (
L : inout LINE; -- input line
VALUE : in UNRESOLVED_ufixed; -- fixed point input
JUSTIFIED : in SIDE := right;
FIELD : in WIDTH := 0) is
begin -- Example 03.30
write (L => L,
VALUE => to_ostring (VALUE),
JUSTIFIED => JUSTIFIED,
FIELD => FIELD);
end procedure owrite;
procedure owrite (
L : inout LINE; -- input line
VALUE : in UNRESOLVED_sfixed; -- fixed point input
JUSTIFIED : in SIDE := right;
FIELD : in WIDTH := 0) is
begin -- Example 03.30
write (L => L,
VALUE => to_ostring (VALUE),
JUSTIFIED => JUSTIFIED,
FIELD => FIELD);
end procedure owrite;
-- purpose: Routines common to the OREAD routines
procedure OREAD_common (
L : inout LINE;
slv : out STD_ULOGIC_VECTOR;
igood : out BOOLEAN;
idex : out INTEGER;
constant bpoint : in INTEGER; -- binary point
constant message : in BOOLEAN;
constant smath : in BOOLEAN) is
-- purpose: error message routine
procedure errmes (
constant mess : in STRING) is -- error message
begin
if message then
if smath then
report "fixed_pkg"
& "OREAD(sfixed) "
& mess
severity error;
else
report "fixed_pkg"
& "OREAD(ufixed) "
& mess
severity error;
end if;
end if;
end procedure errmes;
variable xgood : BOOLEAN;
variable nybble : STD_ULOGIC_VECTOR (2 downto 0); -- 3 bits
variable c : CHARACTER;
variable i : INTEGER;
variable lastu : BOOLEAN := false; -- last character was an "_"
variable founddot : BOOLEAN := false; -- found a dot.
begin
Skip_whitespace (L);
if slv'length > 0 then
i := slv'high;
read (l, c, xgood);
while i > 0 loop
if xgood = false then
errmes ("Error: end of string encountered");
exit;
elsif c = '_' then
if i = slv'length then
errmes ("Error: String begins with an ""_""");
xgood := false;
exit;
elsif lastu then
errmes ("Error: Two underscores detected in input string ""__""");
xgood := false;
exit;
else
lastu := true;
end if;
elsif (c = '.') then
if (i + 1 /= bpoint) then
errmes ("encountered ""."" at wrong index");
xgood := false;
exit;
elsif i = slv'length then
errmes ("encounted a ""."" at the beginning of the line");
xgood := false;
exit;
elsif founddot then
errmes ("Two ""."" encounted in input string");
xgood := false;
exit;
end if;
founddot := true;
lastu := false;
else
Char2triBits(c, nybble, xgood, message);
if not xgood then
exit;
end if;
slv (i downto i-2) := nybble;
i := i - 3;
lastu := false;
end if;
if i > 0 then
read (L, c, xgood);
end if;
end loop;
idex := i;
igood := xgood;
else
igood := true; -- read into a null array
idex := -1;
end if;
end procedure OREAD_common;
-- Note that for Octal and Hex read, you can not start with a ".",
-- the read is for numbers formatted "A.BC". These routines go to
-- the nearest bounds, so "F.E" will fit into an sfixed (2 downto -3).
procedure OREAD (L : inout LINE;
VALUE : out UNRESOLVED_ufixed) is
constant hbv : INTEGER := (((maximum(3, (VALUE'high+1))+2)/3)*3)-1;
constant lbv : INTEGER := ((mine(0, VALUE'low)-2)/3)*3;
variable slv : STD_ULOGIC_VECTOR (hbv-lbv downto 0); -- high bits
variable valuex : UNRESOLVED_ufixed (hbv downto lbv);
variable igood : BOOLEAN;
variable i : INTEGER;
begin
VALUE := (VALUE'range => 'U');
OREAD_common ( L => L,
slv => slv,
igood => igood,
idex => i,
bpoint => -lbv,
message => true,
smath => false);
if igood then -- We did not get another error
if not ((i = -1) and -- We read everything, and high bits 0
(or_reduce (slv(hbv-lbv downto VALUE'high+1-lbv)) = '0')) then
report "fixed_pkg"
& "OREAD(ufixed): Vector truncated."
severity error;
else
if (or_reduce (slv(VALUE'low-lbv-1 downto 0)) = '1') then
assert NO_WARNING
report "fixed_pkg"
& "OREAD(ufixed): Vector truncated"
severity warning;
end if;
valuex := to_ufixed (slv, hbv, lbv);
VALUE := valuex (VALUE'range);
end if;
end if;
end procedure OREAD;
procedure OREAD(L : inout LINE;
VALUE : out UNRESOLVED_ufixed;
GOOD : out BOOLEAN) is
constant hbv : INTEGER := (((maximum(3, (VALUE'high+1))+2)/3)*3)-1;
constant lbv : INTEGER := ((mine(0, VALUE'low)-2)/3)*3;
variable slv : STD_ULOGIC_VECTOR (hbv-lbv downto 0); -- high bits
variable valuex : UNRESOLVED_ufixed (hbv downto lbv);
variable igood : BOOLEAN;
variable i : INTEGER;
begin
VALUE := (VALUE'range => 'U');
OREAD_common ( L => L,
slv => slv,
igood => igood,
idex => i,
bpoint => -lbv,
message => false,
smath => false);
if (igood and -- We did not get another error
(i = -1) and -- We read everything, and high bits 0
(or_reduce (slv(hbv-lbv downto VALUE'high+1-lbv)) = '0')) then
valuex := to_ufixed (slv, hbv, lbv);
VALUE := valuex (VALUE'range);
good := true;
else
good := false;
end if;
end procedure OREAD;
procedure OREAD(L : inout LINE;
VALUE : out UNRESOLVED_sfixed) is
constant hbv : INTEGER := (((maximum(3, (VALUE'high+1))+2)/3)*3)-1;
constant lbv : INTEGER := ((mine(0, VALUE'low)-2)/3)*3;
variable slv : STD_ULOGIC_VECTOR (hbv-lbv downto 0); -- high bits
variable valuex : UNRESOLVED_sfixed (hbv downto lbv);
variable igood : BOOLEAN;
variable i : INTEGER;
begin
VALUE := (VALUE'range => 'U');
OREAD_common ( L => L,
slv => slv,
igood => igood,
idex => i,
bpoint => -lbv,
message => true,
smath => true);
if igood then -- We did not get another error
if not ((i = -1) and -- We read everything
((slv(VALUE'high-lbv) = '0' and -- sign bits = extra bits
or_reduce (slv(hbv-lbv downto VALUE'high+1-lbv)) = '0') or
(slv(VALUE'high-lbv) = '1' and
and_reduce (slv(hbv-lbv downto VALUE'high+1-lbv)) = '1'))) then
report "fixed_pkg"
& "OREAD(sfixed): Vector truncated."
severity error;
else
if (or_reduce (slv(VALUE'low-lbv-1 downto 0)) = '1') then
assert NO_WARNING
report "fixed_pkg"
& "OREAD(sfixed): Vector truncated"
severity warning;
end if;
valuex := to_sfixed (slv, hbv, lbv);
VALUE := valuex (VALUE'range);
end if;
end if;
end procedure OREAD;
procedure OREAD(L : inout LINE;
VALUE : out UNRESOLVED_sfixed;
GOOD : out BOOLEAN) is
constant hbv : INTEGER := (((maximum(3, (VALUE'high+1))+2)/3)*3)-1;
constant lbv : INTEGER := ((mine(0, VALUE'low)-2)/3)*3;
variable slv : STD_ULOGIC_VECTOR (hbv-lbv downto 0); -- high bits
variable valuex : UNRESOLVED_sfixed (hbv downto lbv);
variable igood : BOOLEAN;
variable i : INTEGER;
begin
VALUE := (VALUE'range => 'U');
OREAD_common ( L => L,
slv => slv,
igood => igood,
idex => i,
bpoint => -lbv,
message => false,
smath => true);
if (igood -- We did not get another error
and (i = -1) -- We read everything
and ((slv(VALUE'high-lbv) = '0' and -- sign bits = extra bits
or_reduce (slv(hbv-lbv downto VALUE'high+1-lbv)) = '0') or
(slv(VALUE'high-lbv) = '1' and
and_reduce (slv(hbv-lbv downto VALUE'high+1-lbv)) = '1'))) then
valuex := to_sfixed (slv, hbv, lbv);
VALUE := valuex (VALUE'range);
good := true;
else
good := false;
end if;
end procedure OREAD;
-- hex read and write
procedure hwrite (
L : inout LINE; -- input line
VALUE : in UNRESOLVED_ufixed; -- fixed point input
JUSTIFIED : in SIDE := right;
FIELD : in WIDTH := 0) is
begin -- Example 03.30
write (L => L,
VALUE => to_hstring (VALUE),
JUSTIFIED => JUSTIFIED,
FIELD => FIELD);
end procedure hwrite;
-- purpose: writes fixed point into a line
procedure hwrite (
L : inout LINE; -- input line
VALUE : in UNRESOLVED_sfixed; -- fixed point input
JUSTIFIED : in SIDE := right;
FIELD : in WIDTH := 0) is
begin -- Example 03.30
write (L => L,
VALUE => to_hstring (VALUE),
JUSTIFIED => JUSTIFIED,
FIELD => FIELD);
end procedure hwrite;
-- purpose: Routines common to the OREAD routines
procedure HREAD_common (
L : inout LINE;
slv : out STD_ULOGIC_VECTOR;
igood : out BOOLEAN;
idex : out INTEGER;
constant bpoint : in INTEGER; -- binary point
constant message : in BOOLEAN;
constant smath : in BOOLEAN) is
-- purpose: error message routine
procedure errmes (
constant mess : in STRING) is -- error message
begin
if message then
if smath then
report "fixed_pkg"
& "HREAD(sfixed) "
& mess
severity error;
else
report "fixed_pkg"
& "HREAD(ufixed) "
& mess
severity error;
end if;
end if;
end procedure errmes;
variable xgood : BOOLEAN;
variable nybble : STD_ULOGIC_VECTOR (3 downto 0); -- 4 bits
variable c : CHARACTER;
variable i : INTEGER;
variable lastu : BOOLEAN := false; -- last character was an "_"
variable founddot : BOOLEAN := false; -- found a dot.
begin
Skip_whitespace (L);
if slv'length > 0 then
i := slv'high;
read (l, c, xgood);
while i > 0 loop
if xgood = false then
errmes ("Error: end of string encountered");
exit;
elsif c = '_' then
if i = slv'length then
errmes ("Error: String begins with an ""_""");
xgood := false;
exit;
elsif lastu then
errmes ("Error: Two underscores detected in input string ""__""");
xgood := false;
exit;
else
lastu := true;
end if;
elsif (c = '.') then
if (i + 1 /= bpoint) then
errmes ("encountered ""."" at wrong index");
xgood := false;
exit;
elsif i = slv'length then
errmes ("encounted a ""."" at the beginning of the line");
xgood := false;
exit;
elsif founddot then
errmes ("Two ""."" encounted in input string");
xgood := false;
exit;
end if;
founddot := true;
lastu := false;
else
Char2QuadBits(c, nybble, xgood, message);
if not xgood then
exit;
end if;
slv (i downto i-3) := nybble;
i := i - 4;
lastu := false;
end if;
if i > 0 then
read (L, c, xgood);
end if;
end loop;
idex := i;
igood := xgood;
else
idex := -1;
igood := true; -- read null string
end if;
end procedure HREAD_common;
procedure HREAD(L : inout LINE;
VALUE : out UNRESOLVED_ufixed) is
constant hbv : INTEGER := (((maximum(4, (VALUE'high+1))+3)/4)*4)-1;
constant lbv : INTEGER := ((mine(0, VALUE'low)-3)/4)*4;
variable slv : STD_ULOGIC_VECTOR (hbv-lbv downto 0); -- high bits
variable valuex : UNRESOLVED_ufixed (hbv downto lbv);
variable igood : BOOLEAN;
variable i : INTEGER;
begin
VALUE := (VALUE'range => 'U');
HREAD_common ( L => L,
slv => slv,
igood => igood,
idex => i,
bpoint => -lbv,
message => false,
smath => false);
if igood then
if not ((i = -1) and -- We read everything, and high bits 0
(or_reduce (slv(hbv-lbv downto VALUE'high+1-lbv)) = '0')) then
report "fixed_pkg"
& "HREAD(ufixed): Vector truncated."
severity error;
else
if (or_reduce (slv(VALUE'low-lbv-1 downto 0)) = '1') then
assert NO_WARNING
report "fixed_pkg"
& "HREAD(ufixed): Vector truncated"
severity warning;
end if;
valuex := to_ufixed (slv, hbv, lbv);
VALUE := valuex (VALUE'range);
end if;
end if;
end procedure HREAD;
procedure HREAD(L : inout LINE;
VALUE : out UNRESOLVED_ufixed;
GOOD : out BOOLEAN) is
constant hbv : INTEGER := (((maximum(4, (VALUE'high+1))+3)/4)*4)-1;
constant lbv : INTEGER := ((mine(0, VALUE'low)-3)/4)*4;
variable slv : STD_ULOGIC_VECTOR (hbv-lbv downto 0); -- high bits
variable valuex : UNRESOLVED_ufixed (hbv downto lbv);
variable igood : BOOLEAN;
variable i : INTEGER;
begin
VALUE := (VALUE'range => 'U');
HREAD_common ( L => L,
slv => slv,
igood => igood,
idex => i,
bpoint => -lbv,
message => false,
smath => false);
if (igood and -- We did not get another error
(i = -1) and -- We read everything, and high bits 0
(or_reduce (slv(hbv-lbv downto VALUE'high+1-lbv)) = '0')) then
valuex := to_ufixed (slv, hbv, lbv);
VALUE := valuex (VALUE'range);
good := true;
else
good := false;
end if;
end procedure HREAD;
procedure HREAD(L : inout LINE;
VALUE : out UNRESOLVED_sfixed) is
constant hbv : INTEGER := (((maximum(4, (VALUE'high+1))+3)/4)*4)-1;
constant lbv : INTEGER := ((mine(0, VALUE'low)-3)/4)*4;
variable slv : STD_ULOGIC_VECTOR (hbv-lbv downto 0); -- high bits
variable valuex : UNRESOLVED_sfixed (hbv downto lbv);
variable igood : BOOLEAN;
variable i : INTEGER;
begin
VALUE := (VALUE'range => 'U');
HREAD_common ( L => L,
slv => slv,
igood => igood,
idex => i,
bpoint => -lbv,
message => true,
smath => true);
if igood then -- We did not get another error
if not ((i = -1) -- We read everything
and ((slv(VALUE'high-lbv) = '0' and -- sign bits = extra bits
or_reduce (slv(hbv-lbv downto VALUE'high+1-lbv)) = '0') or
(slv(VALUE'high-lbv) = '1' and
and_reduce (slv(hbv-lbv downto VALUE'high+1-lbv)) = '1'))) then
report "fixed_pkg"
& "HREAD(sfixed): Vector truncated."
severity error;
else
if (or_reduce (slv(VALUE'low-lbv-1 downto 0)) = '1') then
assert NO_WARNING
report "fixed_pkg"
& "HREAD(sfixed): Vector truncated"
severity warning;
end if;
valuex := to_sfixed (slv, hbv, lbv);
VALUE := valuex (VALUE'range);
end if;
end if;
end procedure HREAD;
procedure HREAD(L : inout LINE;
VALUE : out UNRESOLVED_sfixed;
GOOD : out BOOLEAN) is
constant hbv : INTEGER := (((maximum(4, (VALUE'high+1))+3)/4)*4)-1;
constant lbv : INTEGER := ((mine(0, VALUE'low)-3)/4)*4;
variable slv : STD_ULOGIC_VECTOR (hbv-lbv downto 0); -- high bits
variable valuex : UNRESOLVED_sfixed (hbv downto lbv);
variable igood : BOOLEAN;
variable i : INTEGER;
begin
VALUE := (VALUE'range => 'U');
HREAD_common ( L => L,
slv => slv,
igood => igood,
idex => i,
bpoint => -lbv,
message => false,
smath => true);
if (igood and -- We did not get another error
(i = -1) and -- We read everything
((slv(VALUE'high-lbv) = '0' and -- sign bits = extra bits
or_reduce (slv(hbv-lbv downto VALUE'high+1-lbv)) = '0') or
(slv(VALUE'high-lbv) = '1' and
and_reduce (slv(hbv-lbv downto VALUE'high+1-lbv)) = '1'))) then
valuex := to_sfixed (slv, hbv, lbv);
VALUE := valuex (VALUE'range);
good := true;
else
good := false;
end if;
end procedure HREAD;
function to_string (value : UNRESOLVED_ufixed) return STRING is
variable s : STRING(1 to value'length +1) := (others => ' ');
variable subval : UNRESOLVED_ufixed (value'high downto -1);
variable sindx : INTEGER;
begin
if value'length < 1 then
return NUS;
else
if value'high < 0 then
if value(value'high) = 'Z' then
return to_string (resize (sfixed(value), 0, value'low));
else
return to_string (resize (value, 0, value'low));
end if;
elsif value'low >= 0 then
if Is_X (value(value'low)) then
subval := (others => value(value'low));
subval (value'range) := value;
return to_string(subval);
else
return to_string (resize (value, value'high, -1));
end if;
else
sindx := 1;
for i in value'high downto value'low loop
if i = -1 then
s(sindx) := '.';
sindx := sindx + 1;
end if;
s(sindx) := MVL9_to_char(STD_ULOGIC(value(i)));
sindx := sindx + 1;
end loop;
return s;
end if;
end if;
end function to_string;
function to_string (value : UNRESOLVED_sfixed) return STRING is
variable s : STRING(1 to value'length + 1) := (others => ' ');
variable subval : UNRESOLVED_sfixed (value'high downto -1);
variable sindx : INTEGER;
begin
if value'length < 1 then
return NUS;
else
if value'high < 0 then
return to_string (resize (value, 0, value'low));
elsif value'low >= 0 then
if Is_X (value(value'low)) then
subval := (others => value(value'low));
subval (value'range) := value;
return to_string(subval);
else
return to_string (resize (value, value'high, -1));
end if;
else
sindx := 1;
for i in value'high downto value'low loop
if i = -1 then
s(sindx) := '.';
sindx := sindx + 1;
end if;
s(sindx) := MVL9_to_char(STD_ULOGIC(value(i)));
sindx := sindx + 1;
end loop;
return s;
end if;
end if;
end function to_string;
function to_ostring (value : UNRESOLVED_ufixed) return STRING is
constant lne : INTEGER := (-VALUE'low+2)/3;
variable subval : UNRESOLVED_ufixed (value'high downto -3);
variable lpad : STD_ULOGIC_VECTOR (0 to (lne*3 + VALUE'low) -1);
variable slv : STD_ULOGIC_VECTOR (value'length-1 downto 0);
begin
if value'length < 1 then
return NUS;
else
if value'high < 0 then
if value(value'high) = 'Z' then
return to_ostring (resize (sfixed(value), 2, value'low));
else
return to_ostring (resize (value, 2, value'low));
end if;
elsif value'low >= 0 then
if Is_X (value(value'low)) then
subval := (others => value(value'low));
subval (value'range) := value;
return to_ostring(subval);
else
return to_ostring (resize (value, value'high, -3));
end if;
else
slv := to_sulv (value);
if Is_X (value (value'low)) then
lpad := (others => value (value'low));
else
lpad := (others => '0');
end if;
return to_ostring(slv(slv'high downto slv'high-VALUE'high))
& "."
& to_ostring(slv(slv'high-VALUE'high-1 downto 0) & lpad);
end if;
end if;
end function to_ostring;
function to_hstring (value : UNRESOLVED_ufixed) return STRING is
constant lne : INTEGER := (-VALUE'low+3)/4;
variable subval : UNRESOLVED_ufixed (value'high downto -4);
variable lpad : STD_ULOGIC_VECTOR (0 to (lne*4 + VALUE'low) -1);
variable slv : STD_ULOGIC_VECTOR (value'length-1 downto 0);
begin
if value'length < 1 then
return NUS;
else
if value'high < 0 then
if value(value'high) = 'Z' then
return to_hstring (resize (sfixed(value), 3, value'low));
else
return to_hstring (resize (value, 3, value'low));
end if;
elsif value'low >= 0 then
if Is_X (value(value'low)) then
subval := (others => value(value'low));
subval (value'range) := value;
return to_hstring(subval);
else
return to_hstring (resize (value, value'high, -4));
end if;
else
slv := to_sulv (value);
if Is_X (value (value'low)) then
lpad := (others => value(value'low));
else
lpad := (others => '0');
end if;
return to_hstring(slv(slv'high downto slv'high-VALUE'high))
& "."
& to_hstring(slv(slv'high-VALUE'high-1 downto 0)&lpad);
end if;
end if;
end function to_hstring;
function to_ostring (value : UNRESOLVED_sfixed) return STRING is
constant ne : INTEGER := ((value'high+1)+2)/3;
variable pad : STD_ULOGIC_VECTOR(0 to (ne*3 - (value'high+1)) - 1);
constant lne : INTEGER := (-VALUE'low+2)/3;
variable subval : UNRESOLVED_sfixed (value'high downto -3);
variable lpad : STD_ULOGIC_VECTOR (0 to (lne*3 + VALUE'low) -1);
variable slv : STD_ULOGIC_VECTOR (VALUE'high - VALUE'low downto 0);
begin
if value'length < 1 then
return NUS;
else
if value'high < 0 then
return to_ostring (resize (value, 2, value'low));
elsif value'low >= 0 then
if Is_X (value(value'low)) then
subval := (others => value(value'low));
subval (value'range) := value;
return to_ostring(subval);
else
return to_ostring (resize (value, value'high, -3));
end if;
else
pad := (others => value(value'high));
slv := to_sulv (value);
if Is_X (value (value'low)) then
lpad := (others => value(value'low));
else
lpad := (others => '0');
end if;
return to_ostring(pad & slv(slv'high downto slv'high-VALUE'high))
& "."
& to_ostring(slv(slv'high-VALUE'high-1 downto 0) & lpad);
end if;
end if;
end function to_ostring;
function to_hstring (value : UNRESOLVED_sfixed) return STRING is
constant ne : INTEGER := ((value'high+1)+3)/4;
variable pad : STD_ULOGIC_VECTOR(0 to (ne*4 - (value'high+1)) - 1);
constant lne : INTEGER := (-VALUE'low+3)/4;
variable subval : UNRESOLVED_sfixed (value'high downto -4);
variable lpad : STD_ULOGIC_VECTOR (0 to (lne*4 + VALUE'low) -1);
variable slv : STD_ULOGIC_VECTOR (value'length-1 downto 0);
begin
if value'length < 1 then
return NUS;
else
if value'high < 0 then
return to_hstring (resize (value, 3, value'low));
elsif value'low >= 0 then
if Is_X (value(value'low)) then
subval := (others => value(value'low));
subval (value'range) := value;
return to_hstring(subval);
else
return to_hstring (resize (value, value'high, -4));
end if;
else
slv := to_sulv (value);
pad := (others => value(value'high));
if Is_X (value (value'low)) then
lpad := (others => value(value'low));
else
lpad := (others => '0');
end if;
return to_hstring(pad & slv(slv'high downto slv'high-VALUE'high))
& "."
& to_hstring(slv(slv'high-VALUE'high-1 downto 0) & lpad);
end if;
end if;
end function to_hstring;
-- From string functions allow you to convert a string into a fixed
-- point number. Example:
-- signal uf1 : ufixed (3 downto -3);
-- uf1 <= from_string ("0110.100", uf1'high, uf1'low); -- 6.5
-- The "." is optional in this syntax, however it exist and is
-- in the wrong location an error is produced. Overflow will
-- result in saturation.
function from_string (
bstring : STRING; -- binary string
constant left_index : INTEGER;
constant right_index : INTEGER)
return UNRESOLVED_ufixed is
variable result : UNRESOLVED_ufixed (left_index downto right_index);
variable L : LINE;
variable good : BOOLEAN;
begin
L := new STRING'(bstring);
read (L, result, good);
deallocate (L);
assert (good)
report "fixed_pkg"
& "from_string: Bad string "& bstring severity error;
return result;
end function from_string;
-- Octal and hex conversions work as follows:
-- uf1 <= from_hstring ("6.8", 3, -3); -- 6.5 (bottom zeros dropped)
-- uf1 <= from_ostring ("06.4", 3, -3); -- 6.5 (top zeros dropped)
function from_ostring (
ostring : STRING; -- Octal string
constant left_index : INTEGER;
constant right_index : INTEGER)
return UNRESOLVED_ufixed is
variable result : UNRESOLVED_ufixed (left_index downto right_index);
variable L : LINE;
variable good : BOOLEAN;
begin
L := new STRING'(ostring);
oread (L, result, good);
deallocate (L);
assert (good)
report "fixed_pkg"
& "from_ostring: Bad string "& ostring severity error;
return result;
end function from_ostring;
function from_hstring (
hstring : STRING; -- hex string
constant left_index : INTEGER;
constant right_index : INTEGER)
return UNRESOLVED_ufixed is
variable result : UNRESOLVED_ufixed (left_index downto right_index);
variable L : LINE;
variable good : BOOLEAN;
begin
L := new STRING'(hstring);
hread (L, result, good);
deallocate (L);
assert (good)
report "fixed_pkg"
& "from_hstring: Bad string "& hstring severity error;
return result;
end function from_hstring;
function from_string (
bstring : STRING; -- binary string
constant left_index : INTEGER;
constant right_index : INTEGER)
return UNRESOLVED_sfixed is
variable result : UNRESOLVED_sfixed (left_index downto right_index);
variable L : LINE;
variable good : BOOLEAN;
begin
L := new STRING'(bstring);
read (L, result, good);
deallocate (L);
assert (good)
report "fixed_pkg"
& "from_string: Bad string "& bstring severity error;
return result;
end function from_string;
function from_ostring (
ostring : STRING; -- Octal string
constant left_index : INTEGER;
constant right_index : INTEGER)
return UNRESOLVED_sfixed is
variable result : UNRESOLVED_sfixed (left_index downto right_index);
variable L : LINE;
variable good : BOOLEAN;
begin
L := new STRING'(ostring);
oread (L, result, good);
deallocate (L);
assert (good)
report "fixed_pkg"
& "from_ostring: Bad string "& ostring severity error;
return result;
end function from_ostring;
function from_hstring (
hstring : STRING; -- hex string
constant left_index : INTEGER;
constant right_index : INTEGER)
return UNRESOLVED_sfixed is
variable result : UNRESOLVED_sfixed (left_index downto right_index);
variable L : LINE;
variable good : BOOLEAN;
begin
L := new STRING'(hstring);
hread (L, result, good);
deallocate (L);
assert (good)
report "fixed_pkg"
& "from_hstring: Bad string "& hstring severity error;
return result;
end function from_hstring;
-- Same as above, "size_res" is used for it's range only.
function from_string (
bstring : STRING; -- binary string
size_res : UNRESOLVED_ufixed)
return UNRESOLVED_ufixed is
begin
return from_string (bstring, size_res'high, size_res'low);
end function from_string;
function from_ostring (
ostring : STRING; -- Octal string
size_res : UNRESOLVED_ufixed)
return UNRESOLVED_ufixed is
begin
return from_ostring (ostring, size_res'high, size_res'low);
end function from_ostring;
function from_hstring (
hstring : STRING; -- hex string
size_res : UNRESOLVED_ufixed)
return UNRESOLVED_ufixed is
begin
return from_hstring(hstring, size_res'high, size_res'low);
end function from_hstring;
function from_string (
bstring : STRING; -- binary string
size_res : UNRESOLVED_sfixed)
return UNRESOLVED_sfixed is
begin
return from_string (bstring, size_res'high, size_res'low);
end function from_string;
function from_ostring (
ostring : STRING; -- Octal string
size_res : UNRESOLVED_sfixed)
return UNRESOLVED_sfixed is
begin
return from_ostring (ostring, size_res'high, size_res'low);
end function from_ostring;
function from_hstring (
hstring : STRING; -- hex string
size_res : UNRESOLVED_sfixed)
return UNRESOLVED_sfixed is
begin
return from_hstring (hstring, size_res'high, size_res'low);
end function from_hstring;
-- purpose: Calculate the string boundaries
procedure calculate_string_boundry (
arg : in STRING; -- input string
left_index : out INTEGER; -- left
right_index : out INTEGER) is -- right
-- examples "10001.111" would return +4, -3
-- "07X.44" would return +2, -2 (then the octal routine would multiply)
-- "A_B_._C" would return +1, -1 (then the hex routine would multiply)
alias xarg : STRING (arg'length downto 1) is arg; -- make it downto range
variable l, r : INTEGER; -- internal indexes
variable founddot : BOOLEAN := false;
begin
if arg'length > 0 then
l := xarg'high - 1;
r := 0;
for i in xarg'range loop
if xarg(i) = '_' then
if r = 0 then
l := l - 1;
else
r := r + 1;
end if;
elsif xarg(i) = ' ' or xarg(i) = NBSP or xarg(i) = HT then
report "fixed_pkg"
& "Found a space in the input STRING " & xarg
severity error;
elsif xarg(i) = '.' then
if founddot then
report "fixed_pkg"
& "Found two binary points in input string " & xarg
severity error;
else
l := l - i;
r := -i + 1;
founddot := true;
end if;
end if;
end loop;
left_index := l;
right_index := r;
else
left_index := 0;
right_index := 0;
end if;
end procedure calculate_string_boundry;
-- Direct conversion functions. Example:
-- signal uf1 : ufixed (3 downto -3);
-- uf1 <= from_string ("0110.100"); -- 6.5
-- In this case the "." is not optional, and the size of
-- the output must match exactly.
function from_string (
bstring : STRING) -- binary string
return UNRESOLVED_ufixed is
variable left_index, right_index : INTEGER;
begin
calculate_string_boundry (bstring, left_index, right_index);
return from_string (bstring, left_index, right_index);
end function from_string;
-- Direct octal and hex conversion functions. In this case
-- the string lengths must match. Example:
-- signal sf1 := sfixed (5 downto -3);
-- sf1 <= from_ostring ("71.4") -- -6.5
function from_ostring (
ostring : STRING) -- Octal string
return UNRESOLVED_ufixed is
variable left_index, right_index : INTEGER;
begin
calculate_string_boundry (ostring, left_index, right_index);
return from_ostring (ostring, ((left_index+1)*3)-1, right_index*3);
end function from_ostring;
function from_hstring (
hstring : STRING) -- hex string
return UNRESOLVED_ufixed is
variable left_index, right_index : INTEGER;
begin
calculate_string_boundry (hstring, left_index, right_index);
return from_hstring (hstring, ((left_index+1)*4)-1, right_index*4);
end function from_hstring;
function from_string (
bstring : STRING) -- binary string
return UNRESOLVED_sfixed is
variable left_index, right_index : INTEGER;
begin
calculate_string_boundry (bstring, left_index, right_index);
return from_string (bstring, left_index, right_index);
end function from_string;
function from_ostring (
ostring : STRING) -- Octal string
return UNRESOLVED_sfixed is
variable left_index, right_index : INTEGER;
begin
calculate_string_boundry (ostring, left_index, right_index);
return from_ostring (ostring, ((left_index+1)*3)-1, right_index*3);
end function from_ostring;
function from_hstring (
hstring : STRING) -- hex string
return UNRESOLVED_sfixed is
variable left_index, right_index : INTEGER;
begin
calculate_string_boundry (hstring, left_index, right_index);
return from_hstring (hstring, ((left_index+1)*4)-1, right_index*4);
end function from_hstring;
-- pragma synthesis_on
-- rtl_synthesis on
-- IN VHDL-2006 std_logic_vector is a subtype of std_ulogic_vector, so these
-- extra functions are needed for compatability.
function to_ufixed (
arg : STD_LOGIC_VECTOR; -- shifted vector
constant left_index : INTEGER;
constant right_index : INTEGER)
return UNRESOLVED_ufixed is
begin
return to_ufixed (
arg => std_ulogic_vector(arg),
left_index => left_index,
right_index => right_index);
end function to_ufixed;
function to_ufixed (
arg : STD_LOGIC_VECTOR; -- shifted vector
size_res : UNRESOLVED_ufixed) -- for size only
return UNRESOLVED_ufixed is
begin
return to_ufixed (
arg => std_ulogic_vector(arg),
size_res => size_res);
end function to_ufixed;
function to_sfixed (
arg : STD_LOGIC_VECTOR; -- shifted vector
constant left_index : INTEGER;
constant right_index : INTEGER)
return UNRESOLVED_sfixed is
begin
return to_sfixed (
arg => std_ulogic_vector(arg),
left_index => left_index,
right_index => right_index);
end function to_sfixed;
function to_sfixed (
arg : STD_LOGIC_VECTOR; -- shifted vector
size_res : UNRESOLVED_sfixed) -- for size only
return UNRESOLVED_sfixed is
begin
return to_sfixed (
arg => std_ulogic_vector(arg),
size_res => size_res);
end function to_sfixed;
-- unsigned fixed point
function to_UFix (
arg : STD_LOGIC_VECTOR;
width : NATURAL; -- width of vector
fraction : NATURAL) -- width of fraction
return UNRESOLVED_ufixed is
begin
return to_UFix (
arg => std_ulogic_vector(arg),
width => width,
fraction => fraction);
end function to_UFix;
-- signed fixed point
function to_SFix (
arg : STD_LOGIC_VECTOR;
width : NATURAL; -- width of vector
fraction : NATURAL) -- width of fraction
return UNRESOLVED_sfixed is
begin
return to_SFix (
arg => std_ulogic_vector(arg),
width => width,
fraction => fraction);
end function to_SFix;
end package body fixed_pkg;
| gpl-3.0 | 618550c377a99084555043063f4768a7 | 0.567502 | 3.977819 | false | false | false | false |
Feuerwerk/fpgaNES | datamem.vhd | 1 | 6,762 | -- megafunction wizard: %RAM: 1-PORT%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: altsyncram
-- ============================================================
-- File Name: datamem.vhd
-- Megafunction Name(s):
-- altsyncram
--
-- Simulation Library Files(s):
-- altera_mf
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 18.0.0 Build 614 04/24/2018 SJ Lite Edition
-- ************************************************************
--Copyright (C) 2018 Intel Corporation. All rights reserved.
--Your use of Intel Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Intel Program License
--Subscription Agreement, the Intel Quartus Prime License Agreement,
--the Intel FPGA IP License Agreement, or other applicable license
--agreement, including, without limitation, that your use is for
--the sole purpose of programming logic devices manufactured by
--Intel and sold by Intel or its authorized distributors. Please
--refer to the applicable agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY altera_mf;
USE altera_mf.altera_mf_components.all;
ENTITY datamem IS
PORT
(
address : IN STD_LOGIC_VECTOR (10 DOWNTO 0);
clken : IN STD_LOGIC := '1';
clock : IN STD_LOGIC := '1';
data : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
wren : IN STD_LOGIC ;
q : OUT STD_LOGIC_VECTOR (7 DOWNTO 0)
);
END datamem;
ARCHITECTURE SYN OF datamem IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (7 DOWNTO 0);
BEGIN
q <= sub_wire0(7 DOWNTO 0);
altsyncram_component : altsyncram
GENERIC MAP (
clock_enable_input_a => "NORMAL",
clock_enable_output_a => "BYPASS",
intended_device_family => "Cyclone V",
lpm_hint => "ENABLE_RUNTIME_MOD=YES,INSTANCE_NAME=DATA",
lpm_type => "altsyncram",
numwords_a => 2048,
operation_mode => "SINGLE_PORT",
outdata_aclr_a => "NONE",
outdata_reg_a => "UNREGISTERED",
power_up_uninitialized => "FALSE",
read_during_write_mode_port_a => "NEW_DATA_NO_NBE_READ",
widthad_a => 11,
width_a => 8,
width_byteena_a => 1
)
PORT MAP (
address_a => address,
clock0 => clock,
clocken0 => clken,
data_a => data,
wren_a => wren,
q_a => sub_wire0
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
-- Retrieval info: PRIVATE: AclrAddr NUMERIC "0"
-- Retrieval info: PRIVATE: AclrByte NUMERIC "0"
-- Retrieval info: PRIVATE: AclrData NUMERIC "0"
-- Retrieval info: PRIVATE: AclrOutput NUMERIC "0"
-- Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0"
-- Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
-- Retrieval info: PRIVATE: BlankMemory NUMERIC "1"
-- Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "1"
-- Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
-- Retrieval info: PRIVATE: Clken NUMERIC "1"
-- Retrieval info: PRIVATE: DataBusSeparated NUMERIC "1"
-- Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
-- Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
-- Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone V"
-- Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "1"
-- Retrieval info: PRIVATE: JTAG_ID STRING "DATA"
-- Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
-- Retrieval info: PRIVATE: MIFfilename STRING "datamem.mif"
-- Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "2048"
-- Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
-- Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "3"
-- Retrieval info: PRIVATE: RegAddr NUMERIC "1"
-- Retrieval info: PRIVATE: RegData NUMERIC "1"
-- Retrieval info: PRIVATE: RegOutput NUMERIC "0"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: SingleClock NUMERIC "1"
-- Retrieval info: PRIVATE: UseDQRAM NUMERIC "1"
-- Retrieval info: PRIVATE: WRCONTROL_ACLR_A NUMERIC "0"
-- Retrieval info: PRIVATE: WidthAddr NUMERIC "11"
-- Retrieval info: PRIVATE: WidthData NUMERIC "8"
-- Retrieval info: PRIVATE: rden NUMERIC "0"
-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
-- Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "NORMAL"
-- Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone V"
-- Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=YES,INSTANCE_NAME=DATA"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
-- Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "2048"
-- Retrieval info: CONSTANT: OPERATION_MODE STRING "SINGLE_PORT"
-- Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
-- Retrieval info: CONSTANT: OUTDATA_REG_A STRING "UNREGISTERED"
-- Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE"
-- Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_PORT_A STRING "NEW_DATA_NO_NBE_READ"
-- Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "11"
-- Retrieval info: CONSTANT: WIDTH_A NUMERIC "8"
-- Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
-- Retrieval info: USED_PORT: address 0 0 11 0 INPUT NODEFVAL "address[10..0]"
-- Retrieval info: USED_PORT: clken 0 0 0 0 INPUT VCC "clken"
-- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
-- Retrieval info: USED_PORT: data 0 0 8 0 INPUT NODEFVAL "data[7..0]"
-- Retrieval info: USED_PORT: q 0 0 8 0 OUTPUT NODEFVAL "q[7..0]"
-- Retrieval info: USED_PORT: wren 0 0 0 0 INPUT NODEFVAL "wren"
-- Retrieval info: CONNECT: @address_a 0 0 11 0 address 0 0 11 0
-- Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
-- Retrieval info: CONNECT: @clocken0 0 0 0 0 clken 0 0 0 0
-- Retrieval info: CONNECT: @data_a 0 0 8 0 data 0 0 8 0
-- Retrieval info: CONNECT: @wren_a 0 0 0 0 wren 0 0 0 0
-- Retrieval info: CONNECT: q 0 0 8 0 @q_a 0 0 8 0
-- Retrieval info: GEN_FILE: TYPE_NORMAL datamem.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL datamem.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL datamem.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL datamem.bsf FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL datamem_inst.vhd FALSE
-- Retrieval info: LIB_FILE: altera_mf
| gpl-3.0 | a1a74a98d6f8a2337e5e0c4f7deb29ad | 0.661934 | 3.542169 | false | false | false | false |
natsutan/NPU | fpga_implement/npu8/npu8.srcs/sources_1/ip/mul8_8/mul8_8_sim_netlist.vhdl | 1 | 177,383 | -- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (lin64) Build 1733598 Wed Dec 14 22:35:42 MST 2016
-- Date : Sat Jan 21 17:57:16 2017
-- Host : natu-OMEN-by-HP-Laptop running 64-bit Ubuntu 16.04.1 LTS
-- Command : write_vhdl -force -mode funcsim
-- /media/natu/data/proj/myproj/NPU/fpga_implement/npu8/npu8.srcs/sources_1/ip/mul8_8/mul8_8_sim_netlist.vhdl
-- Design : mul8_8
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xcku035-fbva676-3-e
-- --------------------------------------------------------------------------------
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`protect end_protected
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity mul8_8_mult_gen_v12_0_12 is
port (
CLK : in STD_LOGIC;
A : in STD_LOGIC_VECTOR ( 7 downto 0 );
B : in STD_LOGIC_VECTOR ( 7 downto 0 );
CE : in STD_LOGIC;
SCLR : in STD_LOGIC;
ZERO_DETECT : out STD_LOGIC_VECTOR ( 1 downto 0 );
P : out STD_LOGIC_VECTOR ( 15 downto 0 );
PCASC : out STD_LOGIC_VECTOR ( 47 downto 0 )
);
attribute C_A_TYPE : integer;
attribute C_A_TYPE of mul8_8_mult_gen_v12_0_12 : entity is 1;
attribute C_A_WIDTH : integer;
attribute C_A_WIDTH of mul8_8_mult_gen_v12_0_12 : entity is 8;
attribute C_B_TYPE : integer;
attribute C_B_TYPE of mul8_8_mult_gen_v12_0_12 : entity is 1;
attribute C_B_VALUE : string;
attribute C_B_VALUE of mul8_8_mult_gen_v12_0_12 : entity is "10000001";
attribute C_B_WIDTH : integer;
attribute C_B_WIDTH of mul8_8_mult_gen_v12_0_12 : entity is 8;
attribute C_CCM_IMP : integer;
attribute C_CCM_IMP of mul8_8_mult_gen_v12_0_12 : entity is 0;
attribute C_CE_OVERRIDES_SCLR : integer;
attribute C_CE_OVERRIDES_SCLR of mul8_8_mult_gen_v12_0_12 : entity is 0;
attribute C_HAS_CE : integer;
attribute C_HAS_CE of mul8_8_mult_gen_v12_0_12 : entity is 0;
attribute C_HAS_SCLR : integer;
attribute C_HAS_SCLR of mul8_8_mult_gen_v12_0_12 : entity is 0;
attribute C_HAS_ZERO_DETECT : integer;
attribute C_HAS_ZERO_DETECT of mul8_8_mult_gen_v12_0_12 : entity is 0;
attribute C_LATENCY : integer;
attribute C_LATENCY of mul8_8_mult_gen_v12_0_12 : entity is 3;
attribute C_MODEL_TYPE : integer;
attribute C_MODEL_TYPE of mul8_8_mult_gen_v12_0_12 : entity is 0;
attribute C_MULT_TYPE : integer;
attribute C_MULT_TYPE of mul8_8_mult_gen_v12_0_12 : entity is 0;
attribute C_OPTIMIZE_GOAL : integer;
attribute C_OPTIMIZE_GOAL of mul8_8_mult_gen_v12_0_12 : entity is 1;
attribute C_OUT_HIGH : integer;
attribute C_OUT_HIGH of mul8_8_mult_gen_v12_0_12 : entity is 15;
attribute C_OUT_LOW : integer;
attribute C_OUT_LOW of mul8_8_mult_gen_v12_0_12 : entity is 0;
attribute C_ROUND_OUTPUT : integer;
attribute C_ROUND_OUTPUT of mul8_8_mult_gen_v12_0_12 : entity is 0;
attribute C_ROUND_PT : integer;
attribute C_ROUND_PT of mul8_8_mult_gen_v12_0_12 : entity is 0;
attribute C_VERBOSITY : integer;
attribute C_VERBOSITY of mul8_8_mult_gen_v12_0_12 : entity is 0;
attribute C_XDEVICEFAMILY : string;
attribute C_XDEVICEFAMILY of mul8_8_mult_gen_v12_0_12 : entity is "kintexu";
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of mul8_8_mult_gen_v12_0_12 : entity is "mult_gen_v12_0_12";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of mul8_8_mult_gen_v12_0_12 : entity is "yes";
end mul8_8_mult_gen_v12_0_12;
architecture STRUCTURE of mul8_8_mult_gen_v12_0_12 is
signal \<const0>\ : STD_LOGIC;
signal NLW_i_mult_PCASC_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 0 );
signal NLW_i_mult_ZERO_DETECT_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute C_A_TYPE of i_mult : label is 1;
attribute C_A_WIDTH of i_mult : label is 8;
attribute C_B_TYPE of i_mult : label is 1;
attribute C_B_VALUE of i_mult : label is "10000001";
attribute C_B_WIDTH of i_mult : label is 8;
attribute C_CCM_IMP of i_mult : label is 0;
attribute C_CE_OVERRIDES_SCLR of i_mult : label is 0;
attribute C_HAS_CE of i_mult : label is 0;
attribute C_HAS_SCLR of i_mult : label is 0;
attribute C_HAS_ZERO_DETECT of i_mult : label is 0;
attribute C_LATENCY of i_mult : label is 3;
attribute C_MODEL_TYPE of i_mult : label is 0;
attribute C_MULT_TYPE of i_mult : label is 0;
attribute C_OUT_HIGH of i_mult : label is 15;
attribute C_OUT_LOW of i_mult : label is 0;
attribute C_ROUND_OUTPUT of i_mult : label is 0;
attribute C_ROUND_PT of i_mult : label is 0;
attribute C_VERBOSITY of i_mult : label is 0;
attribute C_XDEVICEFAMILY of i_mult : label is "kintexu";
attribute c_optimize_goal of i_mult : label is 1;
attribute downgradeipidentifiedwarnings of i_mult : label is "yes";
begin
PCASC(47) <= \<const0>\;
PCASC(46) <= \<const0>\;
PCASC(45) <= \<const0>\;
PCASC(44) <= \<const0>\;
PCASC(43) <= \<const0>\;
PCASC(42) <= \<const0>\;
PCASC(41) <= \<const0>\;
PCASC(40) <= \<const0>\;
PCASC(39) <= \<const0>\;
PCASC(38) <= \<const0>\;
PCASC(37) <= \<const0>\;
PCASC(36) <= \<const0>\;
PCASC(35) <= \<const0>\;
PCASC(34) <= \<const0>\;
PCASC(33) <= \<const0>\;
PCASC(32) <= \<const0>\;
PCASC(31) <= \<const0>\;
PCASC(30) <= \<const0>\;
PCASC(29) <= \<const0>\;
PCASC(28) <= \<const0>\;
PCASC(27) <= \<const0>\;
PCASC(26) <= \<const0>\;
PCASC(25) <= \<const0>\;
PCASC(24) <= \<const0>\;
PCASC(23) <= \<const0>\;
PCASC(22) <= \<const0>\;
PCASC(21) <= \<const0>\;
PCASC(20) <= \<const0>\;
PCASC(19) <= \<const0>\;
PCASC(18) <= \<const0>\;
PCASC(17) <= \<const0>\;
PCASC(16) <= \<const0>\;
PCASC(15) <= \<const0>\;
PCASC(14) <= \<const0>\;
PCASC(13) <= \<const0>\;
PCASC(12) <= \<const0>\;
PCASC(11) <= \<const0>\;
PCASC(10) <= \<const0>\;
PCASC(9) <= \<const0>\;
PCASC(8) <= \<const0>\;
PCASC(7) <= \<const0>\;
PCASC(6) <= \<const0>\;
PCASC(5) <= \<const0>\;
PCASC(4) <= \<const0>\;
PCASC(3) <= \<const0>\;
PCASC(2) <= \<const0>\;
PCASC(1) <= \<const0>\;
PCASC(0) <= \<const0>\;
ZERO_DETECT(1) <= \<const0>\;
ZERO_DETECT(0) <= \<const0>\;
GND: unisim.vcomponents.GND
port map (
G => \<const0>\
);
i_mult: entity work.mul8_8_mult_gen_v12_0_12_viv
port map (
A(7 downto 0) => A(7 downto 0),
B(7 downto 0) => B(7 downto 0),
CE => '0',
CLK => CLK,
P(15 downto 0) => P(15 downto 0),
PCASC(47 downto 0) => NLW_i_mult_PCASC_UNCONNECTED(47 downto 0),
SCLR => '0',
ZERO_DETECT(1 downto 0) => NLW_i_mult_ZERO_DETECT_UNCONNECTED(1 downto 0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity mul8_8 is
port (
CLK : in STD_LOGIC;
A : in STD_LOGIC_VECTOR ( 7 downto 0 );
B : in STD_LOGIC_VECTOR ( 7 downto 0 );
P : out STD_LOGIC_VECTOR ( 15 downto 0 )
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of mul8_8 : entity is true;
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of mul8_8 : entity is "mul8_8,mult_gen_v12_0_12,{}";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of mul8_8 : entity is "yes";
attribute x_core_info : string;
attribute x_core_info of mul8_8 : entity is "mult_gen_v12_0_12,Vivado 2016.4";
end mul8_8;
architecture STRUCTURE of mul8_8 is
signal NLW_U0_PCASC_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 0 );
signal NLW_U0_ZERO_DETECT_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute C_A_TYPE : integer;
attribute C_A_TYPE of U0 : label is 1;
attribute C_A_WIDTH : integer;
attribute C_A_WIDTH of U0 : label is 8;
attribute C_B_TYPE : integer;
attribute C_B_TYPE of U0 : label is 1;
attribute C_B_VALUE : string;
attribute C_B_VALUE of U0 : label is "10000001";
attribute C_B_WIDTH : integer;
attribute C_B_WIDTH of U0 : label is 8;
attribute C_CCM_IMP : integer;
attribute C_CCM_IMP of U0 : label is 0;
attribute C_CE_OVERRIDES_SCLR : integer;
attribute C_CE_OVERRIDES_SCLR of U0 : label is 0;
attribute C_HAS_CE : integer;
attribute C_HAS_CE of U0 : label is 0;
attribute C_HAS_SCLR : integer;
attribute C_HAS_SCLR of U0 : label is 0;
attribute C_HAS_ZERO_DETECT : integer;
attribute C_HAS_ZERO_DETECT of U0 : label is 0;
attribute C_LATENCY : integer;
attribute C_LATENCY of U0 : label is 3;
attribute C_MODEL_TYPE : integer;
attribute C_MODEL_TYPE of U0 : label is 0;
attribute C_MULT_TYPE : integer;
attribute C_MULT_TYPE of U0 : label is 0;
attribute C_OUT_HIGH : integer;
attribute C_OUT_HIGH of U0 : label is 15;
attribute C_OUT_LOW : integer;
attribute C_OUT_LOW of U0 : label is 0;
attribute C_ROUND_OUTPUT : integer;
attribute C_ROUND_OUTPUT of U0 : label is 0;
attribute C_ROUND_PT : integer;
attribute C_ROUND_PT of U0 : label is 0;
attribute C_VERBOSITY : integer;
attribute C_VERBOSITY of U0 : label is 0;
attribute C_XDEVICEFAMILY : string;
attribute C_XDEVICEFAMILY of U0 : label is "kintexu";
attribute c_optimize_goal : integer;
attribute c_optimize_goal of U0 : label is 1;
attribute downgradeipidentifiedwarnings of U0 : label is "yes";
begin
U0: entity work.mul8_8_mult_gen_v12_0_12
port map (
A(7 downto 0) => A(7 downto 0),
B(7 downto 0) => B(7 downto 0),
CE => '1',
CLK => CLK,
P(15 downto 0) => P(15 downto 0),
PCASC(47 downto 0) => NLW_U0_PCASC_UNCONNECTED(47 downto 0),
SCLR => '0',
ZERO_DETECT(1 downto 0) => NLW_U0_ZERO_DETECT_UNCONNECTED(1 downto 0)
);
end STRUCTURE;
| bsd-3-clause | 37303bc6c28c2b567ff515e23af163f0 | 0.937542 | 1.857277 | false | false | false | false |
besm6/micro-besm | tests/2910/vhdl/types.vhd | 10 | 31,064 | ----------------------------------------------------------------------------
--
-- Copyright (c) 1990, 1991 by Synopsys, Inc. All rights reserved.
--
-- This source file may be used and distributed without restriction
-- provided that this copyright statement is not removed from the file
-- and that any derivative work contains this copyright notice.
--
-- Package name: TYPES
--
-- Purpose: This package defines the types, logic functions,
-- truth tables, definitions for wired signals, and
-- conversion functions for the Synopsys Standard Logic library.
--
-- Author: JT, PH, GWH
--
-- Modified with attributes for Synopsys synthesis.
--
-- Also synthesis_off and synthesis_on pairs required because
-- synthesis does not fully support or gives warnings about:
-- 1) Multi-dimentional arrays
-- 2) aliases
-- 3) assert
--
--
-- Modified by Champaka Ramachandran on Sept 15th 1992
--
-- Modifications to get rid of the Synopsys specific library and attributes
--
----------------------------------------------------------------------------
--synopsys translate_off
-- library SYNOPSYS;
-- use SYNOPSYS.ATTRIBUTES.all;
--synopsys translate_on
package TYPES is
---------------------------------------------------------------------
--
-- Definitions for Standard Logic types
--
---------------------------------------------------------------------
-- multi-valued logic 7 states:
type MVL7 is ('X', -- strong X (strong unknown)
'0', -- strong 0 (strong low)
'1', -- strong 1 (strong high)
'Z', -- tristate X (high impedance)
'W', -- weak X (weak unknown)
'L', -- weak 0 (weak low)
'H'); -- weak 1 (weak high)
-- attribute ENUM_ENCODING : STRING;
-- attribute ENUM_ENCODING of MVL7 : type is "D 0 1 Z U 0 1";
-- vector of MVL7
type MVL7_VECTOR is array (Natural range <>) of MVL7;
-- output-strength types
type STRENGTH is (X01, X0H, XL1, X0Z, XZ1, WLH, WLZ, WZH, W0H, WL1);
-----------------------------------------------------------------------
--
-- Internal types for table look up
--
----------------------------------------------------------------------
--synopsys synthesis_off
type MVL7_TAB1D is array (MVL7) of MVL7; -- one dimensional
type MVL7_TABLE is array (MVL7, MVL7) of MVL7; -- two dimensional
type STRN_MVL7_TABLE is array (MVL7,STRENGTH) of MVL7;
type MUX_TABLE is array (MVL7 range 'X' to '1',
MVL7 range 'X' to '1',
MVL7 range 'X' to '1') of MVL7;
type TRISTATE_TABLE is array (STRENGTH,
MVL7 range 'X' to '1',
MVL7 range 'X' to '1') of MVL7;
type MINOMAX is array (1 to 3) of TIME;
-----------------------------------------------------------------------
--
-- Truth tables for output strength --> MVL7 lookup
--
-----------------------------------------------------------------------
-- truth table for output strength --> MVL7 lookup
constant tbl_STRN_MVL7: STRN_MVL7_TABLE :=
-- ------------------------------------------------------------------
-- | X01 X0H XL1 X0Z XZ1 WLH WLZ WZH W0H WL1 | strn/ output|
-- ------------------------------------------------------------------
(('X', 'X', 'X', 'X', 'X', 'W', 'W', 'W', 'W', 'W'), -- | X |
('0', '0', 'L', '0', 'Z', 'L', 'L', 'Z', '0', 'L'), -- | 0 |
('1', 'H', '1', 'Z', '1', 'H', 'Z', 'H', 'H', '1'), -- | 1 |
('X', 'X', 'X', 'X', 'X', 'W', 'W', 'W', 'W', 'W'), -- | Z |
('X', 'X', 'X', 'X', 'X', 'W', 'W', 'W', 'W', 'W'), -- | W |
('0', '0', 'L', '0', 'Z', 'L', 'L', 'Z', '0', 'L'), -- | L |
('1', 'H', '1', 'Z', '1', 'H', 'Z', 'H', 'H', '1')); -- | H |
-----------------------------------------------------------------------
--
-- Truth tables for strength --> MVL7 mapping ('Z' pass through)
--
-----------------------------------------------------------------------
-- truth table for output strength --> MVL7 lookup
constant tbl_STRN_MVL7_Z: STRN_MVL7_TABLE :=
-- ------------------------------------------------------------------
-- | X01 X0H XL1 X0Z XZ1 WLH WLZ WZH W0H WL1 | strn/ output|
-- ------------------------------------------------------------------
(('X', 'X', 'X', 'X', 'X', 'W', 'W', 'W', 'W', 'W'), -- | X |
('0', '0', 'L', '0', 'Z', 'L', 'L', 'Z', '0', 'L'), -- | 0 |
('1', 'H', '1', 'Z', '1', 'H', 'Z', 'H', 'H', '1'), -- | 1 |
('Z', 'Z', 'Z', 'Z', 'Z', 'Z', 'Z', 'Z', 'Z', 'Z'), -- | Z |
('X', 'X', 'X', 'X', 'X', 'W', 'W', 'W', 'W', 'W'), -- | W |
('0', '0', 'L', '0', 'Z', 'L', 'L', 'Z', '0', 'L'), -- | L |
('1', 'H', '1', 'Z', '1', 'H', 'Z', 'H', 'H', '1')); -- | H |
-----------------------------------------------------------------------
--
-- Truth tables for logical operations
--
-----------------------------------------------------------------------
-- truth table for "and" function
constant tbl_AND: MVL7_TABLE :=
-- -----------------------------------------------
-- | X 0 1 Z W L H | |
-- -----------------------------------------------
(('X', '0', 'X', 'X', 'X', '0', 'X'), -- | X |
('0', '0', '0', '0', '0', '0', '0'), -- | 0 |
('X', '0', '1', 'X', 'X', '0', '1'), -- | 1 |
('X', '0', 'X', 'X', 'X', '0', 'X'), -- | Z |
('X', '0', 'X', 'X', 'X', '0', 'X'), -- | W |
('0', '0', '0', '0', '0', '0', '0'), -- | L |
('X', '0', '1', 'X', 'X', '0', '1')); -- | H |
-- truth table for "or" function
constant tbl_OR: MVL7_TABLE :=
-- -----------------------------------------------
-- | X 0 1 Z W L H | |
-- -----------------------------------------------
(('X', 'X', '1', 'X', 'X', 'X', '1'), -- | X |
('X', '0', '1', 'X', 'X', '0', '1'), -- | 0 |
('1', '1', '1', '1', '1', '1', '1'), -- | 1 |
('X', 'X', '1', 'X', 'X', 'X', '1'), -- | Z |
('X', 'X', '1', 'X', 'X', 'X', '1'), -- | W |
('X', '0', '1', 'X', 'X', '0', '1'), -- | L |
('1', '1', '1', '1', '1', '1', '1')); -- | H |
-- truth table for "xor" function
constant tbl_XOR: MVL7_TABLE :=
-- -----------------------------------------------
-- | X 0 1 Z W L H | |
-- -----------------------------------------------
(('X', 'X', 'X', 'X', 'X', 'X', 'X'), -- | X |
('X', '0', '1', 'X', 'X', '0', '1'), -- | 0 |
('X', '1', '0', 'X', 'X', '1', '0'), -- | 1 |
('X', 'X', 'X', 'X', 'X', 'X', 'X'), -- | Z |
('X', 'X', 'X', 'X', 'X', 'X', 'X'), -- | W |
('X', '0', '1', 'X', 'X', '0', '1'), -- | L |
('X', '1', '0', 'X', 'X', '1', '0')); -- | H |
-- truth table for "not" function
constant tbl_NOT: MVL7_TAB1D :=
-- -------------------------------------
-- | X 0 1 Z W L H |
-- -------------------------------------
('X', '1', '0', 'X', 'X', '1', '0');
-- truth table for "buf" function
constant tbl_BUF: MVL7_TAB1D :=
-- -------------------------------------
-- | X 0 1 Z W L H |
-- -------------------------------------
('X', '0', '1', 'X', 'X', '0', '1');
-- truth table for tristate "buf" function (Enable active High)
constant tbl_BUF3S: TRISTATE_TABLE :=
-- ----------------------------------------
-- | X 0 1 | Enable Strength |
-- ----------------------------------------
((('X', 'X', 'X'), --| X X01 |
('Z', 'Z', 'Z'), --| 0 X01 |
('X', '0', '1')), --| 1 X01 |
(('X', 'X', 'X'), --| X X0H |
('Z', 'Z', 'Z'), --| 0 X0H |
('X', '0', 'H')), --| 1 X0H |
(('X', 'X', 'X'), --| X XL1 |
('Z', 'Z', 'Z'), --| 0 XL1 |
('X', 'L', '1')), --| 1 XL1 |
(('X', 'X', 'Z'), --| X X0Z |
('Z', 'Z', 'Z'), --| 0 X0Z |
('X', '0', 'Z')), --| 1 X0Z |
(('X', 'X', 'X'), --| X XZ1 |
('Z', 'Z', 'Z'), --| 0 XZ1 |
('X', 'Z', '1')), --| 1 XZ1 |
(('W', 'W', 'W'), --| X WLH |
('Z', 'Z', 'Z'), --| 0 WLH |
('W', 'L', 'H')), --| 1 WLH |
(('W', 'W', 'Z'), --| X WLZ |
('Z', 'Z', 'Z'), --| 0 WLZ |
('W', 'L', 'Z')), --| 1 WLZ |
(('W', 'W', 'W'), --| X WZH |
('Z', 'Z', 'Z'), --| 0 WZH |
('W', 'Z', 'H')), --| 1 WZH |
(('W', 'W', 'W'), --| X W0H |
('Z', 'Z', 'Z'), --| 0 W0H |
('W', '0', 'H')), --| 1 W0H |
(('W', 'W', 'W'), --| X WL1 |
('Z', 'Z', 'Z'), --| 0 WL1 |
('W', 'L', '1')));--| 1 WL1 |
-- truth table for tristate "buf" function (Enable active Low)
constant tbl_BUF3SL: TRISTATE_TABLE :=
-- ----------------------------------------
-- | X 0 1 | Enable Strength |
-- ----------------------------------------
((('X', 'X', 'X'), --| X X01 |
('X', '0', '1'), --| 0 X01 |
('Z', 'Z', 'Z')), --| 1 X01 |
(('X', 'X', 'X'), --| X X0H |
('X', '0', 'H'), --| 0 X0H |
('Z', 'Z', 'Z')), --| 1 X0H |
(('X', 'X', 'X'), --| X XL1 |
('X', 'L', '1'), --| 0 XL1 |
('Z', 'Z', 'Z')), --| 1 XL1 |
(('X', 'X', 'Z'), --| X X0Z |
('X', '0', 'Z'), --| 0 X0Z |
('Z', 'Z', 'Z')), --| 1 X0Z |
(('X', 'X', 'X'), --| X XZ1 |
('X', 'Z', '1'), --| 0 XZ1 |
('Z', 'Z', 'Z')), --| 1 XZ1 |
(('W', 'W', 'W'), --| X WLH |
('W', 'L', 'H'), --| 0 WLH |
('Z', 'Z', 'Z')), --| 1 WLH |
(('W', 'W', 'Z'), --| X WLZ |
('W', 'L', 'Z'), --| 0 WLZ |
('Z', 'Z', 'Z')), --| 1 WLZ |
(('W', 'W', 'W'), --| X WZH |
('W', 'Z', 'H'), --| 0 WZH |
('Z', 'Z', 'Z')), --| 1 WZH |
(('W', 'W', 'W'), --| X W0H |
('W', '0', 'H'), --| 0 W0H |
('Z', 'Z', 'Z')), --| 1 W0H |
(('W', 'W', 'W'), --| X WL1 |
('W', 'L', '1'), --| 0 WL1 |
('Z', 'Z', 'Z')));--| 1 WL1 |
-- truth table for "MUX2x1" function
constant tbl_MUX2x1: MUX_TABLE :=
---------------------------------------
--| In0 'X' '0' '1' | Sel In1 |
---------------------------------------
((('X', 'X', 'X'), --| 'X' 'X' |
('X', '0', '1'), --| '0' 'X' |
('X', 'X', 'X')), --| '1' 'X' |
(('X', '0', 'X'), --| 'X' '0' |
('X', '0', '1'), --| '0' '0' |
('0', '0', '0')), --| '1' '0' |
(('X', 'X', '1'), --| 'X' '1' |
('X', '0', '1'), --| '0' '1' |
('1', '1', '1')));--| '1' '1' |
----------------------------------------------------------------------
--
-- Truth tables for resolution functions
--
----------------------------------------------------------------------
-- truth table for "WiredX" function
constant tbl_WIREDX: MVL7_TABLE :=
-- -----------------------------------------------
-- | X 0 1 Z W L H | |
-- -----------------------------------------------
(('X', 'X', 'X', 'X', 'X', 'X', 'X'), -- | X |
('X', '0', 'X', '0', '0', '0', '0'), -- | 0 |
('X', 'X', '1', '1', '1', '1', '1'), -- | 1 |
('X', '0', '1', 'Z', 'W', 'L', 'H'), -- | Z |
('X', '0', '1', 'W', 'W', 'W', 'W'), -- | W |
('X', '0', '1', 'L', 'W', 'L', 'W'), -- | L |
('X', '0', '1', 'H', 'W', 'W', 'H')); -- | H |
-- truth table for "WiredOr" function
constant tbl_WIREDOR: MVL7_TABLE :=
-- -----------------------------------------------
-- | X 0 1 Z W L H | |
-- -----------------------------------------------
(('X', 'X', '1', 'X', 'X', 'L', 'H'), -- | X |
('X', '0', '1', '0', '0', 'L', 'H'), -- | 0 |
('1', '1', '1', '1', '1', '1', '1'), -- | 1 |
('X', '0', '1', 'Z', 'W', 'L', 'H'), -- | Z |
('X', '0', '1', 'W', 'W', 'W', 'W'), -- | W |
('L', 'L', '1', 'L', 'W', 'L', 'W'), -- | L |
('H', 'H', '1', 'H', 'W', 'W', 'H')); -- | H |
--synopsys synthesis_on
-----------------------------------------------------------------------
--
-- logical functions for scalar type of MVL7
--
-----------------------------------------------------------------------
function "and" (L, R: MVL7) return MVL7;
function "nand" (L, R: MVL7) return MVL7;
function "or" (L, R: MVL7) return MVL7;
function "nor" (L, R: MVL7) return MVL7;
function "xor" (L, R: MVL7) return MVL7;
function nxor (L, R: MVL7) return MVL7;
function "not" (R: MVL7) return MVL7;
function buf (R: MVL7) return MVL7;
-----------------------------------------------------------------------
--
-- logical functions for composite type of MVL7_VECTOR
--
-----------------------------------------------------------------------
function "and" (L, R: MVL7_VECTOR) return MVL7_VECTOR;
function "nand" (L, R: MVL7_VECTOR) return MVL7_VECTOR;
function "or" (L, R: MVL7_VECTOR) return MVL7_VECTOR;
function "nor" (L, R: MVL7_VECTOR) return MVL7_VECTOR;
function "xor" (L, R: MVL7_VECTOR) return MVL7_VECTOR;
function nxor (L, R: MVL7_VECTOR) return MVL7_VECTOR;
function "not" (R: MVL7_VECTOR) return MVL7_VECTOR;
function buf (R: MVL7_VECTOR) return MVL7_VECTOR;
-----------------------------------------------------------------------
--
-- resolution functions for wired signals and its attributes
--
-----------------------------------------------------------------------
function WiredX (V: MVL7_VECTOR) return MVL7;
function WiredOr (V: MVL7_VECTOR) return MVL7;
--synopsys translate_off
-- attribute REFLEXIVE of WiredX: function is TRUE;
-- attribute RESULT_INITIAL_VALUE of WiredX: function is MVL7'POS('Z');
-- attribute TABLE_NAME of WiredX: function is "TYPES.tbl_WIREDX";
--synopsys translate_on
-----------------------------------------------------------------------
--
-- Definitions for wired signals (scalars and vectors)
--
-----------------------------------------------------------------------
subtype DotX is WiredX MVL7;
type BusX is array (Natural range <>) of DotX;
--synopsys synthesis_off
-----------------------------------------------------------------------
--
-- conversion functions for driving various types
--
-----------------------------------------------------------------------
function Drive (V: MVL7_VECTOR) return BusX;
function Drive (V: BusX) return MVL7_VECTOR;
--synopsys synthesis_on
--synopsys translate_off
-- attribute CLOSELY_RELATED_TCF of Drive: function is TRUE;
--synopsys translate_on
--synopsys synthesis_off
-----------------------------------------------------------------------
--
-- conversion functions for sensing various types
-- (the second argument allows the user to specify the value to
-- be returned when the network is undriven)
--
-----------------------------------------------------------------------
function Sense (V: MVL7; vZ: MVL7) return MVL7;
function Sense (V: MVL7_VECTOR; vZ: MVL7) return MVL7_VECTOR;
function Sense (V: BusX; vZ: MVL7) return MVL7_VECTOR;
--synopsys synthesis_on
-----------------------------------------------------------------------
--
-- Function: BVtoMVL7V
--
-- Purpose: Conversion function from BIT_VECTOR to MVL7_VECTOR
--
-- Mapping: 0 --> 0
-- 1 --> 1
--
-----------------------------------------------------------------------
function BVtoMVL7V (V: BIT_VECTOR) return MVL7_VECTOR;
-----------------------------------------------------------------------
--
-- Function: MVL7VtoBV
--
-- Purpose: Conversion function from MVL7_VECTOR to BIT_VECTOR
--
-- Mapping: 0, L --> 0
-- 1, H --> 1
-- X --> vX if Xflag is TRUE
-- X --> 0 if Xflag is FALSE
-- Z --> vZ if Zflag is TRUE
-- Z --> 0 if Zflag is FALSE
--
-----------------------------------------------------------------------
function MVL7VtoBV (V: MVL7_VECTOR
--synopsys synthesis_off
; vX, vZ: BIT := '0'; Xflag, Zflag: BOOLEAN := FALSE
--synopsys synthesis_on
) return BIT_VECTOR;
-----------------------------------------------------------------------
--
-- Function: BITtoMVL7
--
-- Purpose: Conversion function from BIT to MVL7
--
-- Mapping: 0 --> 0
-- 1 --> 1
--
-----------------------------------------------------------------------
function BITtoMVL7 (V: BIT) return MVL7;
-----------------------------------------------------------------------
--
-- Function: MVL7toBIT
--
-- Purpose: Conversion function from MVL7 to BIT
--
-- Mapping: 0, L --> 0
-- 1, H --> 1
-- X --> vX if Xflag is TRUE
-- X --> 0 if Xflag is FALSE
-- Z --> vZ if Zflag is TRUE
-- Z --> 0 if Zflag is FALSE
--
-----------------------------------------------------------------------
function MVL7toBIT (V: MVL7
--synopsys synthesis_off
; vX, vZ: BIT := '0'; Xflag, Zflag: BOOLEAN := FALSE
--synopsys synthesis_on
) return BIT;
--synopsys synthesis_off
-----------------------------------------------------------------------
--
-- Truth tables for unidirectional transistors
--
-----------------------------------------------------------------------
-- truth table for reduce function
constant tbl_REDUCE: MVL7_TAB1D :=
-- ------------------------------------
-- | X 0 1 Z W L H |
-- ------------------------------------
('W', 'L', 'H', 'Z', 'W', 'L', 'H');
constant tbl_NXFER: MVL7_TABLE :=
----------------------------------------------------------
-- | Input 'X' '0' '1' 'Z' 'W' 'L' 'H' | Enable
----------------------------------------------------------
(('X', 'X', 'X', 'X', 'X', 'X', 'X'), -- 'X'
('Z', 'Z', 'Z', 'Z', 'Z', 'Z', 'Z'), -- '0'
('X', '0', '1', 'Z', 'W', 'L', 'H'), -- '1'
('X', 'X', 'X', 'X', 'X', 'X', 'X'), -- 'Z'
('X', 'X', 'X', 'X', 'X', 'X', 'X'), -- 'W'
('Z', 'Z', 'Z', 'Z', 'Z', 'Z', 'Z'), -- 'L'
('X', '0', '1', 'Z', 'W', 'L', 'H')); -- 'H'
constant tbl_PXFER: MVL7_TABLE :=
----------------------------------------------------------
-- | Input 'X' '0' '1' 'Z' 'W' 'L' 'H' | Enable
----------------------------------------------------------
(('X', 'X', 'X', 'X', 'X', 'X', 'X'), -- 'X'
('X', '0', '1', 'Z', 'W', 'L', 'H'), -- '0'
('Z', 'Z', 'Z', 'Z', 'Z', 'Z', 'Z'), -- '1'
('X', 'X', 'X', 'X', 'X', 'X', 'X'), -- 'Z'
('X', 'X', 'X', 'X', 'X', 'X', 'X'), -- 'W'
('X', '0', '1', 'Z', 'W', 'L', 'H'), -- 'L'
('Z', 'Z', 'Z', 'Z', 'Z', 'Z', 'Z')); -- 'H'
--synopsys synthesis_on
end TYPES;
package body TYPES is
-----------------------------------------------------------------------
--
-- logical functions for scalar type of MVL7
--
-----------------------------------------------------------------------
function "and" (L, R: MVL7) return MVL7 is
-- pragma built_in SYN_AND
begin
--synopsys synthesis_off
return tbl_AND(L, R);
--synopsys synthesis_on
end "and";
function "nand" (L, R: MVL7) return MVL7 is
-- pragma built_in SYN_NAND
begin
--synopsys synthesis_off
return tbl_NOT(tbl_AND(L, R));
--synopsys synthesis_on
end "nand";
function "or" (L, R: MVL7) return MVL7 is
-- pragma built_in SYN_OR
begin
--synopsys synthesis_off
return tbl_OR(L, R);
--synopsys synthesis_on
end "or";
function "nor" (L, R: MVL7) return MVL7 is
-- pragma built_in SYN_NOR
begin
--synopsys synthesis_off
return tbl_NOT(tbl_OR(L, R));
--synopsys synthesis_on
end "nor";
function "xor" (L, R: MVL7) return MVL7 is
-- pragma built_in SYN_XOR
begin
--synopsys synthesis_off
return tbl_XOR(L, R);
--synopsys synthesis_on
end "xor";
function nxor (L, R: MVL7) return MVL7 is
-- pragma built_in SYN_XNOR
begin
--synopsys synthesis_off
return tbl_NOT(tbl_XOR(L, R));
--synopsys synthesis_on
end nxor;
function "not" (R: MVL7) return MVL7 is
-- pragma built_in SYN_NOT
begin
--synopsys synthesis_off
return tbl_NOT(R);
--synopsys synthesis_on
end "not";
function buf (R: MVL7) return MVL7 is
-- pragma built_in SYN_BUF
begin
--synopsys synthesis_off
return tbl_BUF(R);
--synopsys synthesis_on
end buf;
-----------------------------------------------------------------------
--
-- logical functions for composite type of MVL7_VECTOR
--
-----------------------------------------------------------------------
function "and" (L, R: MVL7_VECTOR) return MVL7_VECTOR is
-- pragma built_in SYN_AND
--synopsys synthesis_off
alias LV: MVL7_VECTOR (L'length-1 downto 0) is L;
alias RV: MVL7_VECTOR (R'length-1 downto 0) is R;
variable result: MVL7_VECTOR (L'length-1 downto 0);
--synopsys synthesis_on
begin
--synopsys synthesis_off
assert L'length = R'length;
for i in result'range loop
result (i) := tbl_AND(LV (i), RV (i));
end loop;
return result;
--synopsys synthesis_on
end "and";
function "nand" (L, R: MVL7_VECTOR) return MVL7_VECTOR is
-- pragma built_in SYN_NAND
--synopsys synthesis_off
alias LV: MVL7_VECTOR (L'length-1 downto 0) is L;
alias RV: MVL7_VECTOR (R'length-1 downto 0) is R;
variable result: MVL7_VECTOR (L'length-1 downto 0);
--synopsys synthesis_on
begin
--synopsys synthesis_off
assert L'length = R'length;
for i in result'range loop
result (i) := tbl_NOT(tbl_AND(LV (i), RV (i)));
end loop;
return result;
--synopsys synthesis_on
end "nand";
function "or" (L, R: MVL7_VECTOR) return MVL7_VECTOR is
-- pragma built_in SYN_OR
--synopsys synthesis_off
alias LV: MVL7_VECTOR (L'length-1 downto 0) is L;
alias RV: MVL7_VECTOR (R'length-1 downto 0) is R;
variable result: MVL7_VECTOR (L'length-1 downto 0);
--synopsys synthesis_on
begin
--synopsys synthesis_off
assert L'length = R'length;
for i in result'range loop
result (i) := tbl_OR(LV (i), RV (i));
end loop;
return result;
--synopsys synthesis_on
end "or";
function "nor" (L, R: MVL7_VECTOR) return MVL7_VECTOR is
-- pragma built_in SYN_NOR
--synopsys synthesis_off
alias LV: MVL7_VECTOR (L'length-1 downto 0) is L;
alias RV: MVL7_VECTOR (R'length-1 downto 0) is R;
variable result: MVL7_VECTOR (L'length-1 downto 0);
--synopsys synthesis_on
begin
--synopsys synthesis_off
assert L'length = R'length;
for i in result'range loop
result (i) := tbl_NOT(tbl_OR(LV (i), RV (i)));
end loop;
return result;
--synopsys synthesis_on
end "nor";
function "xor" (L, R: MVL7_VECTOR) return MVL7_VECTOR is
-- pragma built_in SYN_XOR
--synopsys synthesis_off
alias LV: MVL7_VECTOR (L'length-1 downto 0) is L;
alias RV: MVL7_VECTOR (R'length-1 downto 0) is R;
variable result: MVL7_VECTOR (L'length-1 downto 0);
--synopsys synthesis_on
begin
--synopsys synthesis_off
assert L'length = R'length;
for i in result'range loop
result (i) := tbl_XOR(LV (i), RV (i));
end loop;
return result;
--synopsys synthesis_on
end "xor";
function nxor (L, R: MVL7_VECTOR) return MVL7_VECTOR is
-- pragma built_in SYN_XNOR
--synopsys synthesis_off
alias LV: MVL7_VECTOR (L'length-1 downto 0) is L;
alias RV: MVL7_VECTOR (R'length-1 downto 0) is R;
variable result: MVL7_VECTOR (L'length-1 downto 0);
--synopsys synthesis_on
begin
--synopsys synthesis_off
assert L'length = R'length;
for i in result'range loop
result(i) := tbl_NOT(tbl_XOR(LV(i), RV(i)));
end loop;
return result;
--synopsys synthesis_on
end nxor;
function "not" (R: MVL7_VECTOR) return MVL7_VECTOR is
-- pragma built_in SYN_NOT
--synopsys synthesis_off
alias RV: MVL7_VECTOR (R'length-1 downto 0) is R;
variable result: MVL7_VECTOR (R'length-1 downto 0);
--synopsys synthesis_on
begin
--synopsys synthesis_off
for i in result'range loop
result (i) := tbl_NOT( RV(i) );
end loop;
return result;
--synopsys synthesis_on
end "not";
function buf (R: MVL7_VECTOR) return MVL7_VECTOR is
-- pragma built_in SYN_BUF
--synopsys synthesis_off
alias RV: MVL7_VECTOR (R'length-1 downto 0) is R;
variable result: MVL7_VECTOR (R'length-1 downto 0);
--synopsys synthesis_on
begin
--synopsys synthesis_off
for i in result'range loop
result(i) := tbl_BUF( RV(i) );
end loop;
return result;
--synopsys synthesis_on
end buf;
-----------------------------------------------------------------------
--
-- resolution functions for wired signals
--
-----------------------------------------------------------------------
function WiredX (V: MVL7_VECTOR) return MVL7 is
-- pragma resolution_method three_state
variable result: MVL7;
begin
--synopsys synthesis_off
result := 'Z';
for i in V'range loop
result := tbl_WIREDX(result, V(i));
exit when result = 'X';
end loop;
return result;
--synopsys synthesis_on
end WiredX;
function WiredOr (V: MVL7_VECTOR) return MVL7 is
variable result: MVL7;
begin
--synopsys synthesis_off
result := 'Z';
for i in V'range loop
result := tbl_WIREDOr(result, V(i));
exit when result = '1';
end loop;
return result;
--synopsys synthesis_on
end WiredOr;
-- synopsys synthesis_off
-----------------------------------------------------------------------
--
-- conversion functions for driving various types
--
-----------------------------------------------------------------------
function Drive (V: BusX) return MVL7_VECTOR is
begin
return MVL7_VECTOR(V);
end Drive;
function Drive (V: MVL7_VECTOR) return BusX is
begin
return BusX(V);
end Drive;
-----------------------------------------------------------------------
--
-- conversion functions for sensing various types
--
-- (the second argument allows the user to specify the value to
-- be returned when the network is undriven)
--
-----------------------------------------------------------------------
function Sense (V: MVL7; vZ: MVL7) return MVL7 is
begin
if V = 'Z' then
return vZ;
else
return V;
end if;
end Sense;
function Sense (V: MVL7_VECTOR; vZ: MVL7) return MVL7_VECTOR is
alias Value: MVL7_VECTOR (V'length-1 downto 0) is V;
variable Result: MVL7_VECTOR (V'length-1 downto 0);
begin
for i in Value'range loop
if ( Value(i) = 'Z' ) then
Result(i) := vZ;
else
Result(i) := Value(i);
end if;
end loop;
return Result;
end Sense;
function Sense (V: BusX; vZ: MVL7) return MVL7_VECTOR is
alias Value: BusX (V'length-1 downto 0) is V;
variable Result: MVL7_VECTOR (V'length-1 downto 0);
begin
for i in Value'range loop
if ( Value(i) = 'Z' ) then
Result(i) := vZ;
else
Result(i) := Value(i);
end if;
end loop;
return Result;
end Sense;
-- synopsys synthesis_on
-----------------------------------------------------------------------
--
-- Function: BVtoMVL7V
--
-- Purpose: Conversion function from BIT_VECTOR to MVL7_VECTOR
--
-- Mapping: 0 --> 0
-- 1 --> 1
--
-----------------------------------------------------------------------
function BVtoMVL7V (V: BIT_VECTOR) return MVL7_VECTOR is
-- pragma built_in SYN_FEED_THRU
--synopsys synthesis_off
alias Value: BIT_VECTOR (V'length-1 downto 0) is V;
variable Result: MVL7_VECTOR (V'length-1 downto 0);
--synopsys synthesis_on
begin
--synopsys synthesis_off
for i in Value'range loop
if ( Value(i) = '0' ) then
Result(i) := '0';
else
Result(i) := '1';
end if;
end loop;
return Result;
--synopsys synthesis_on
end BVtoMVL7V;
-----------------------------------------------------------------------
--
-- Function: MVL7VtoBV
--
-- Purpose: Conversion function from MVL7_VECTOR to BIT_VECTOR
--
-- Mapping: 0, L --> 0
-- 1, H --> 1
-- X --> vX if Xflag is TRUE
-- X --> 0 if Xflag is FALSE
-- Z --> vZ if Zflag is TRUE
-- Z --> 0 if Zflag is FALSE
--
-----------------------------------------------------------------------
function MVL7VtoBV (V: MVL7_VECTOR
--synopsys synthesis_off
; vX, vZ: BIT := '0'; Xflag, Zflag: BOOLEAN := FALSE
--synopsys synthesis_on
) return BIT_VECTOR is
-- pragma built_in SYN_FEED_THRU
--synopsys synthesis_off
alias Value: MVL7_VECTOR (V'length-1 downto 0) is V;
variable Result: BIT_VECTOR (V'length-1 downto 0);
--synopsys synthesis_on
begin
--synopsys synthesis_off
for i in Value'range loop
case Value(i) is
when '0' | 'L' =>
Result(i) := '0';
when '1' | 'H' =>
Result(i) := '1';
when 'X' | 'W' =>
if ( Xflag ) then
Result(i) := vX;
else
Result(i) := '0';
assert FALSE
report "MVL7VtoBV: X --> 0"
severity WARNING;
end if;
when others =>
if ( Zflag ) then
Result(i) := vZ;
else
Result(i) := '0';
assert FALSE
report "MVL7VtoBV: Z --> 0"
severity WARNING;
end if;
end case;
end loop;
return Result;
--synopsys synthesis_on
end MVL7VtoBV;
-----------------------------------------------------------------------
--
-- Function: BITtoMVL7
--
-- Purpose: Conversion function from BIT to MVL7
--
-- Mapping: 0 --> 0
-- 1 --> 1
--
-----------------------------------------------------------------------
function BITtoMVL7 (V: BIT) return MVL7 is
variable Result: MVL7;
-- pragma built_in SYN_FEED_THRU
begin
if ( V = '0' ) then
Result := '0';
else
Result := '1';
end if;
return Result;
end BITtoMVL7;
-----------------------------------------------------------------------
--
-- Function: MVL7toBIT
--
-- Purpose: Conversion function from MVL7 to BIT
--
-- Mapping: 0, L --> 0
-- 1, H --> 1
-- X --> vX if Xflag is TRUE
-- X --> 0 if Xflag is FALSE
-- Z --> vZ if Zflag is TRUE
-- Z --> 0 if Zflag is FALSE
--
-----------------------------------------------------------------------
function MVL7toBIT (V: MVL7
--synopsys synthesis_off
; vX, vZ: BIT := '0'; Xflag, Zflag: BOOLEAN := FALSE
--synopsys synthesis_on
) return BIT is
-- pragma built_in SYN_FEED_THRU
variable Result: BIT;
begin
--synopsys synthesis_off
case V is
when '0' | 'L' =>
Result := '0';
when '1' | 'H' =>
Result := '1';
when 'X' | 'W' =>
if ( Xflag ) then
Result := vX;
else
Result := '0';
assert FALSE
report "MVL7toBIT: X --> 0"
severity WARNING;
end if;
when others =>
if ( Zflag ) then
Result := vZ;
else
Result := '0';
assert FALSE
report "MVL7toBIT: Z --> 0"
severity WARNING;
end if;
end case;
return Result;
--synopsys synthesis_on
end MVL7toBIT;
end TYPES;
| mit | ad0865b3092e48dc012aefd31c026e84 | 0.410379 | 3.14923 | false | false | false | false |
varunnagpaal/Digital-Hardware-Modelling | vhdl/filter/iir/bq/filter_in_data_memory.vhdl | 1 | 2,228 | -- Library Clause(s) (optional)
-- Use Clause(s) (optional)
library IEEE;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.filter_shared_package.all;
entity filter_in_data_memory is
generic
(
PRECISION : natural := PREC
);
port
(
-- Input ports
clk, aclr : in std_logic;
x_data_in : in std_logic_vector(SINGLE_EXT-1 downto 0);
x_rdaddr : in X_ADD_T;
x_rden : in std_logic;
x_wraddr : in X_ADD_T;
x_wren : in std_logic;
-- Output ports
x_data_out : out DATA_IO_PORT_T
);
end filter_in_data_memory;
architecture filter_in_data_memory_arch of filter_in_data_memory is
component filter_converter_sp2dp is
port
(
float : in std_logic_vector(SINGLE_EXT-1 downto 0);
double : out std_logic_vector(DOUBLE_EXT-1 downto 0)
);
end component;
signal float_data_s : std_logic_vector(SINGLE_EXT-1 downto 0);
begin
-- Instance of X-Memory
filter_in_data_memory_inst : entity work.device_ram_blocks
generic map
(
INTENDED_DEVICE_FAMILY => "SmartFusion",
WIDTH_AD => x_rdaddr'length, -- WIDTH_RDAD = WIDTH_WRAD
WIDTH_DATA => x_data_in'length, -- WIDTH_DATAIN = WIDTH_DATAOUT
OUP_REG => "UNREGISTERED" -- "UNREGISTERED" or "CLOCK0"
)
port map
(
clock => clk,
aclr => aclr,
rden => x_rden,
rdaddress => x_rdaddr,
data_in => x_data_in,
wren => x_wren,
wraddress => x_wraddr,
data_out => float_data_s
);
-- Output is either float type or double type
SNGL: if PRECISION = SINGLE_EXT generate
x_data_out <= float_data_s;
end generate;
DBL: if PRECISION = DOUBLE_EXT generate
F2D : component filter_converter_sp2dp
port map(float => float_data_s, double => x_data_out);
end generate;
end filter_in_data_memory_arch; | mit | 6383395d43ce726b35a2638486766dba | 0.516607 | 3.828179 | false | false | false | false |
natsutan/NPU | fpga_implement/npu8/npu8.srcs/sources_1/ip/mult_17x16/mult_17x16_sim_netlist.vhdl | 1 | 635,233 | -- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (lin64) Build 1733598 Wed Dec 14 22:35:42 MST 2016
-- Date : Sat Jan 21 14:43:34 2017
-- Host : natu-OMEN-by-HP-Laptop running 64-bit Ubuntu 16.04.1 LTS
-- Command : write_vhdl -force -mode funcsim
-- /media/natu/data/proj/myproj/NPU/fpga_implement/npu8/npu8.srcs/sources_1/ip/mult_17x16/mult_17x16_sim_netlist.vhdl
-- Design : mult_17x16
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xcku035-fbva676-3-e
-- --------------------------------------------------------------------------------
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`protect key_keyowner="Synplicity", key_keyname="SYNP05_001", key_method="rsa"
`protect encoding = (enctype="base64", line_length=76, bytes=256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 460000)
`protect data_block
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`protect end_protected
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity mult_17x16_mult_gen_v12_0_12 is
port (
CLK : in STD_LOGIC;
A : in STD_LOGIC_VECTOR ( 16 downto 0 );
B : in STD_LOGIC_VECTOR ( 15 downto 0 );
CE : in STD_LOGIC;
SCLR : in STD_LOGIC;
ZERO_DETECT : out STD_LOGIC_VECTOR ( 1 downto 0 );
P : out STD_LOGIC_VECTOR ( 24 downto 0 );
PCASC : out STD_LOGIC_VECTOR ( 47 downto 0 )
);
attribute C_A_TYPE : integer;
attribute C_A_TYPE of mult_17x16_mult_gen_v12_0_12 : entity is 1;
attribute C_A_WIDTH : integer;
attribute C_A_WIDTH of mult_17x16_mult_gen_v12_0_12 : entity is 17;
attribute C_B_TYPE : integer;
attribute C_B_TYPE of mult_17x16_mult_gen_v12_0_12 : entity is 1;
attribute C_B_VALUE : string;
attribute C_B_VALUE of mult_17x16_mult_gen_v12_0_12 : entity is "10000001";
attribute C_B_WIDTH : integer;
attribute C_B_WIDTH of mult_17x16_mult_gen_v12_0_12 : entity is 16;
attribute C_CCM_IMP : integer;
attribute C_CCM_IMP of mult_17x16_mult_gen_v12_0_12 : entity is 0;
attribute C_CE_OVERRIDES_SCLR : integer;
attribute C_CE_OVERRIDES_SCLR of mult_17x16_mult_gen_v12_0_12 : entity is 0;
attribute C_HAS_CE : integer;
attribute C_HAS_CE of mult_17x16_mult_gen_v12_0_12 : entity is 0;
attribute C_HAS_SCLR : integer;
attribute C_HAS_SCLR of mult_17x16_mult_gen_v12_0_12 : entity is 0;
attribute C_HAS_ZERO_DETECT : integer;
attribute C_HAS_ZERO_DETECT of mult_17x16_mult_gen_v12_0_12 : entity is 0;
attribute C_LATENCY : integer;
attribute C_LATENCY of mult_17x16_mult_gen_v12_0_12 : entity is 4;
attribute C_MODEL_TYPE : integer;
attribute C_MODEL_TYPE of mult_17x16_mult_gen_v12_0_12 : entity is 0;
attribute C_MULT_TYPE : integer;
attribute C_MULT_TYPE of mult_17x16_mult_gen_v12_0_12 : entity is 0;
attribute C_OPTIMIZE_GOAL : integer;
attribute C_OPTIMIZE_GOAL of mult_17x16_mult_gen_v12_0_12 : entity is 1;
attribute C_OUT_HIGH : integer;
attribute C_OUT_HIGH of mult_17x16_mult_gen_v12_0_12 : entity is 32;
attribute C_OUT_LOW : integer;
attribute C_OUT_LOW of mult_17x16_mult_gen_v12_0_12 : entity is 8;
attribute C_ROUND_OUTPUT : integer;
attribute C_ROUND_OUTPUT of mult_17x16_mult_gen_v12_0_12 : entity is 0;
attribute C_ROUND_PT : integer;
attribute C_ROUND_PT of mult_17x16_mult_gen_v12_0_12 : entity is 0;
attribute C_VERBOSITY : integer;
attribute C_VERBOSITY of mult_17x16_mult_gen_v12_0_12 : entity is 0;
attribute C_XDEVICEFAMILY : string;
attribute C_XDEVICEFAMILY of mult_17x16_mult_gen_v12_0_12 : entity is "kintexu";
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of mult_17x16_mult_gen_v12_0_12 : entity is "mult_gen_v12_0_12";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of mult_17x16_mult_gen_v12_0_12 : entity is "yes";
end mult_17x16_mult_gen_v12_0_12;
architecture STRUCTURE of mult_17x16_mult_gen_v12_0_12 is
signal \<const0>\ : STD_LOGIC;
signal NLW_i_mult_PCASC_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 0 );
signal NLW_i_mult_ZERO_DETECT_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute C_A_TYPE of i_mult : label is 1;
attribute C_A_WIDTH of i_mult : label is 17;
attribute C_B_TYPE of i_mult : label is 1;
attribute C_B_VALUE of i_mult : label is "10000001";
attribute C_B_WIDTH of i_mult : label is 16;
attribute C_CCM_IMP of i_mult : label is 0;
attribute C_CE_OVERRIDES_SCLR of i_mult : label is 0;
attribute C_HAS_CE of i_mult : label is 0;
attribute C_HAS_SCLR of i_mult : label is 0;
attribute C_HAS_ZERO_DETECT of i_mult : label is 0;
attribute C_LATENCY of i_mult : label is 4;
attribute C_MODEL_TYPE of i_mult : label is 0;
attribute C_MULT_TYPE of i_mult : label is 0;
attribute C_OUT_HIGH of i_mult : label is 32;
attribute C_OUT_LOW of i_mult : label is 8;
attribute C_ROUND_OUTPUT of i_mult : label is 0;
attribute C_ROUND_PT of i_mult : label is 0;
attribute C_VERBOSITY of i_mult : label is 0;
attribute C_XDEVICEFAMILY of i_mult : label is "kintexu";
attribute c_optimize_goal of i_mult : label is 1;
attribute downgradeipidentifiedwarnings of i_mult : label is "yes";
begin
PCASC(47) <= \<const0>\;
PCASC(46) <= \<const0>\;
PCASC(45) <= \<const0>\;
PCASC(44) <= \<const0>\;
PCASC(43) <= \<const0>\;
PCASC(42) <= \<const0>\;
PCASC(41) <= \<const0>\;
PCASC(40) <= \<const0>\;
PCASC(39) <= \<const0>\;
PCASC(38) <= \<const0>\;
PCASC(37) <= \<const0>\;
PCASC(36) <= \<const0>\;
PCASC(35) <= \<const0>\;
PCASC(34) <= \<const0>\;
PCASC(33) <= \<const0>\;
PCASC(32) <= \<const0>\;
PCASC(31) <= \<const0>\;
PCASC(30) <= \<const0>\;
PCASC(29) <= \<const0>\;
PCASC(28) <= \<const0>\;
PCASC(27) <= \<const0>\;
PCASC(26) <= \<const0>\;
PCASC(25) <= \<const0>\;
PCASC(24) <= \<const0>\;
PCASC(23) <= \<const0>\;
PCASC(22) <= \<const0>\;
PCASC(21) <= \<const0>\;
PCASC(20) <= \<const0>\;
PCASC(19) <= \<const0>\;
PCASC(18) <= \<const0>\;
PCASC(17) <= \<const0>\;
PCASC(16) <= \<const0>\;
PCASC(15) <= \<const0>\;
PCASC(14) <= \<const0>\;
PCASC(13) <= \<const0>\;
PCASC(12) <= \<const0>\;
PCASC(11) <= \<const0>\;
PCASC(10) <= \<const0>\;
PCASC(9) <= \<const0>\;
PCASC(8) <= \<const0>\;
PCASC(7) <= \<const0>\;
PCASC(6) <= \<const0>\;
PCASC(5) <= \<const0>\;
PCASC(4) <= \<const0>\;
PCASC(3) <= \<const0>\;
PCASC(2) <= \<const0>\;
PCASC(1) <= \<const0>\;
PCASC(0) <= \<const0>\;
ZERO_DETECT(1) <= \<const0>\;
ZERO_DETECT(0) <= \<const0>\;
GND: unisim.vcomponents.GND
port map (
G => \<const0>\
);
i_mult: entity work.mult_17x16_mult_gen_v12_0_12_viv
port map (
A(16 downto 0) => A(16 downto 0),
B(15 downto 0) => B(15 downto 0),
CE => '0',
CLK => CLK,
P(24 downto 0) => P(24 downto 0),
PCASC(47 downto 0) => NLW_i_mult_PCASC_UNCONNECTED(47 downto 0),
SCLR => '0',
ZERO_DETECT(1 downto 0) => NLW_i_mult_ZERO_DETECT_UNCONNECTED(1 downto 0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity mult_17x16 is
port (
CLK : in STD_LOGIC;
A : in STD_LOGIC_VECTOR ( 16 downto 0 );
B : in STD_LOGIC_VECTOR ( 15 downto 0 );
P : out STD_LOGIC_VECTOR ( 24 downto 0 )
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of mult_17x16 : entity is true;
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of mult_17x16 : entity is "mult_17x16,mult_gen_v12_0_12,{}";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of mult_17x16 : entity is "yes";
attribute x_core_info : string;
attribute x_core_info of mult_17x16 : entity is "mult_gen_v12_0_12,Vivado 2016.4";
end mult_17x16;
architecture STRUCTURE of mult_17x16 is
signal NLW_U0_PCASC_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 0 );
signal NLW_U0_ZERO_DETECT_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute C_A_TYPE : integer;
attribute C_A_TYPE of U0 : label is 1;
attribute C_A_WIDTH : integer;
attribute C_A_WIDTH of U0 : label is 17;
attribute C_B_TYPE : integer;
attribute C_B_TYPE of U0 : label is 1;
attribute C_B_VALUE : string;
attribute C_B_VALUE of U0 : label is "10000001";
attribute C_B_WIDTH : integer;
attribute C_B_WIDTH of U0 : label is 16;
attribute C_CCM_IMP : integer;
attribute C_CCM_IMP of U0 : label is 0;
attribute C_CE_OVERRIDES_SCLR : integer;
attribute C_CE_OVERRIDES_SCLR of U0 : label is 0;
attribute C_HAS_CE : integer;
attribute C_HAS_CE of U0 : label is 0;
attribute C_HAS_SCLR : integer;
attribute C_HAS_SCLR of U0 : label is 0;
attribute C_HAS_ZERO_DETECT : integer;
attribute C_HAS_ZERO_DETECT of U0 : label is 0;
attribute C_LATENCY : integer;
attribute C_LATENCY of U0 : label is 4;
attribute C_MODEL_TYPE : integer;
attribute C_MODEL_TYPE of U0 : label is 0;
attribute C_MULT_TYPE : integer;
attribute C_MULT_TYPE of U0 : label is 0;
attribute C_OUT_HIGH : integer;
attribute C_OUT_HIGH of U0 : label is 32;
attribute C_OUT_LOW : integer;
attribute C_OUT_LOW of U0 : label is 8;
attribute C_ROUND_OUTPUT : integer;
attribute C_ROUND_OUTPUT of U0 : label is 0;
attribute C_ROUND_PT : integer;
attribute C_ROUND_PT of U0 : label is 0;
attribute C_VERBOSITY : integer;
attribute C_VERBOSITY of U0 : label is 0;
attribute C_XDEVICEFAMILY : string;
attribute C_XDEVICEFAMILY of U0 : label is "kintexu";
attribute c_optimize_goal : integer;
attribute c_optimize_goal of U0 : label is 1;
attribute downgradeipidentifiedwarnings of U0 : label is "yes";
begin
U0: entity work.mult_17x16_mult_gen_v12_0_12
port map (
A(16 downto 0) => A(16 downto 0),
B(15 downto 0) => B(15 downto 0),
CE => '1',
CLK => CLK,
P(24 downto 0) => P(24 downto 0),
PCASC(47 downto 0) => NLW_U0_PCASC_UNCONNECTED(47 downto 0),
SCLR => '0',
ZERO_DETECT(1 downto 0) => NLW_U0_ZERO_DETECT_UNCONNECTED(1 downto 0)
);
end STRUCTURE;
| bsd-3-clause | d308688a23532206d479520fc163107d | 0.950739 | 1.819578 | false | false | false | false |
MartinCura/SistDig-TP4 | src/uart/timing.vhd | 1 | 3,237 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_unsigned.all;
entity timing is
generic (
F : natural;
min_baud: natural
);
port (
clk : in std_logic;
rst : in std_logic;
divisor : in std_logic_vector;
ClrDiv : in std_logic;
Top16 : buffer std_logic;
TopTx : out std_logic;
TopRx : out std_logic
);
end timing;
architecture timing_arq of timing is
-- signal baud_value : natural;
constant max_div : natural := ((F*1000)/(16*min_baud));
subtype div16_type is natural range 0 to max_div-1;
signal Div16 : div16_type;
signal ClkDiv : integer;
signal RxDiv : integer;
begin
-- --------------------------
-- Baud rate selection
-- --------------------------
--
-- process (clk) -- baud_value setting.
-- begin
-- if rising_edge(clk) then
-- case Baud is
-- when "000" => baud_value <= 115200;
-- when "001" => baud_value <= 57600;
-- when "010" => baud_value <= 38400;
-- when "011" => baud_value <= 19200;
-- when "100" => baud_value <= 9600;
-- when "101" => baud_value <= 4800;
-- when "110" => baud_value <= 2400;
-- when "111" => baud_value <= 1200;
-- when others => baud_value <= 1200; -- n.u.
-- end case;
-- end if;
-- end process;
-- --------------------------
-- Clk16 Clock Generation
-- --------------------------
process (rst, clk)
begin
if rst = '1' then
Top16 <= '0';
Div16 <= 0;
elsif rising_edge(clk) then
Top16 <= '0';
if Div16 = conv_integer(divisor) then
Div16 <= 0;
Top16 <= '1';
else
Div16 <= Div16 + 1;
end if;
end if;
end process;
-- --------------------------
-- Tx Clock Generation
-- --------------------------
process (rst, clk)
begin
if rst = '1' then
TopTx <= '0';
ClkDiv <= 0; --(others=>'0');
elsif rising_edge(clk) then
TopTx <= '0';
if Top16 = '1' then
ClkDiv <= ClkDiv + 1;
if ClkDiv = 15 then
TopTx <= '1';
ClkDiv <= 0;
end if;
end if;
end if;
end process;
-- ------------------------------
-- Rx Sampling Clock Generation
-- ------------------------------
process (rst, clk)
begin
if rst = '1' then
TopRx <= '0';
RxDiv <= 0;
elsif rising_edge(clk) then
TopRx <= '0';
if ClrDiv = '1' then
RxDiv <= 0;
elsif Top16 = '1' then
if RxDiv = 7 then
RxDiv <= 0;
TopRx <= '1';
else
RxDiv <= RxDiv + 1;
end if;
end if;
end if;
end process;
end;
| gpl-3.0 | 718e19b495bb2139709277e64bfa873c | 0.388631 | 4.374324 | false | false | false | false |
ls1intum/ArTEMiS | src/main/resources/templates/vhdl/solution/verzoegerung.vhd | 1 | 1,284 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity verzoegerung is
port(
CLK, START : in std_logic;
STOP : in std_logic; -- Aufgabe 2
ALARM : out std_logic
);
end entity;
architecture behaviour of verzoegerung is
signal z : unsigned(2 downto 0) := "000";
begin
ALARM <= '1' when z = "100" else '0'; -- Ausgang
process(CLK)
begin
if rising_edge(CLK) then
-- if STOP = '1' then -- synchroner Reset (Aufgabe 2), für Afgabe 2 unkommentieren
-- z <= "000";
else
case z is
when "000" => -- Startzustand
if START = '1' then
z <= "001";
end if;
when "001" | "010" | "011" => -- Wartezustaende
z <= z + 1;
when "100" => -- Alarmzustand
if START = '0' then
z <= "000";
end if;
when others =>
end case;
-- end if; -- für Aufgabe 2 unkommentieren
end if;
end process;
end architecture;
| mit | 8cf56dc299217111c2d7abebdaba4659 | 0.413417 | 4.175896 | false | false | false | false |
astoria-d/super-duper-nes | test/i2c_test/i2c.vhd | 1 | 12,147 | library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.conv_integer;
use ieee.std_logic_arith.conv_std_logic_vector;
use ieee.std_logic_unsigned.all;
---po_i2c_status(0): '1' = bus transfering, '0' = stopped.
---po_i2c_status(1): '1' = acknowleged, '0' = not acknowleged.
---po_i2c_status(2): '1' = read, '0' = write.
entity i2c_slave is
port (
pi_rst_n : in std_logic;
pi_base_clk : in std_logic;
---i2c bus lines...
pi_slave_addr : in std_logic_vector (6 downto 0);
pi_i2c_scl : in std_logic;
pio_i2c_sda : inout std_logic;
---i2c bus contoler internal lines...
po_i2c_status : out std_logic_vector (2 downto 0);
po_slave_in_data : out std_logic_vector (7 downto 0);
pi_slave_out_data : in std_logic_vector (7 downto 0)
);
end i2c_slave;
architecture rtl of i2c_slave is
type i2c_sp_stat is (
stop, start, restart
);
type i2c_bus_stat is (
idle,
a6, a5, a4, a3, a2, a1, a0, rw, a_ack,
d7, d6, d5, d4, d3, d2, d1, d0, d_ack
);
signal reg_cur_sp : i2c_sp_stat;
signal reg_bsyn_sda : std_logic;
signal reg_bsyn_scl : std_logic;
signal reg_cur_state : i2c_bus_stat;
signal reg_next_state : i2c_bus_stat;
signal reg_i2c_cmd_addr : std_logic_vector(6 downto 0);
signal reg_i2c_cmd_r_nw : std_logic;
signal reg_i2c_cmd_in_data : std_logic_vector(6 downto 0);
begin
--for metastability, synchronize with two stages intermediate FF.
bsync_p : process (pi_rst_n, pi_base_clk)
variable reg_temp_sda : std_logic_vector(2 downto 0);
variable reg_temp_scl : std_logic_vector(2 downto 0);
begin
if (pi_rst_n = '0') then
reg_temp_sda := (others => '0');
reg_temp_scl := (others => '0');
elsif (rising_edge(pi_base_clk)) then
--shift two stage register.
reg_temp_sda := pio_i2c_sda & reg_temp_sda(2 downto 1);
reg_temp_scl := pi_i2c_scl & reg_temp_scl(2 downto 1);
reg_bsyn_sda <= reg_temp_sda(0);
reg_bsyn_scl <= reg_temp_scl(0);
end if;--if (pi_rst_n = '0') then
end process;
--start/stop w/ edge detect.
edge_detect_p : process (pi_rst_n, pi_base_clk)
variable reg_temp_sda2 : std_logic;
variable reg_temp_st : i2c_sp_stat;
begin
if (pi_rst_n = '0') then
reg_temp_sda2 := '0';
reg_cur_sp <= stop;
reg_temp_st := stop;
elsif (rising_edge(pi_base_clk)) then
if (reg_bsyn_scl = '1' and reg_bsyn_sda = '0' and reg_temp_sda2 = '1'
and reg_cur_sp = stop) then
reg_cur_sp <= start;
elsif (reg_bsyn_scl = '1' and reg_bsyn_sda = '0' and reg_temp_sda2 = '1'
and reg_cur_sp = start) then
reg_cur_sp <= restart;
elsif (reg_bsyn_scl = '1' and reg_bsyn_sda = '1' and reg_temp_sda2 = '0'
and reg_cur_sp = start) then
reg_cur_sp <= stop;
elsif (reg_temp_st = restart) then
reg_cur_sp <= start;
end if;
reg_temp_sda2 := reg_bsyn_sda;
reg_temp_st := reg_cur_sp;
end if;--if (pi_rst_n = '0') then
end process;
--i2c bus state machine (state transition)...
set_stat_p : process (pi_rst_n, reg_cur_sp, pi_i2c_scl)
begin
if (pi_rst_n = '0') then
reg_cur_state <= idle;
elsif (reg_cur_sp = stop or reg_cur_sp = restart) then
reg_cur_state <= idle;
elsif (rising_edge(pi_i2c_scl)) then
reg_cur_state <= reg_next_state;
end if;--if (pi_rst_n = '0') then
end process;
--state change to next.
next_stat_p : process (reg_cur_state, reg_i2c_cmd_r_nw, pio_i2c_sda)
procedure set_next_stat
(
pi_stat : in i2c_bus_stat
) is
begin
reg_next_state <= pi_stat;
end;
begin
case reg_cur_state is
when idle =>
set_next_stat(a6);
when a6 =>
set_next_stat(a5);
when a5 =>
set_next_stat(a4);
when a4 =>
set_next_stat(a3);
when a3 =>
set_next_stat(a2);
when a2 =>
set_next_stat(a1);
when a1 =>
set_next_stat(a0);
when a0 =>
set_next_stat(rw);
when rw =>
set_next_stat(a_ack);
when a_ack =>
set_next_stat(d7);
when d7 =>
set_next_stat(d6);
when d6 =>
set_next_stat(d5);
when d5 =>
set_next_stat(d4);
when d4 =>
set_next_stat(d3);
when d3 =>
set_next_stat(d2);
when d2 =>
set_next_stat(d1);
when d1 =>
set_next_stat(d0);
when d0 =>
if (reg_i2c_cmd_r_nw = '0') then
set_next_stat(d_ack);
else
--wait for ack.
if (pio_i2c_sda = '0') then
set_next_stat(d_ack);
else
set_next_stat(d0);
end if;
end if;
when d_ack =>
set_next_stat(d7);
end case;
end process;
--i2c addr/data set.
set_addr : process (pi_rst_n, pi_i2c_scl)
begin
if (pi_rst_n = '0') then
reg_i2c_cmd_addr <= (others => '0');
reg_i2c_cmd_r_nw <= '1';
reg_i2c_cmd_in_data <= (others => '0');
po_slave_in_data <= (others => '0');
elsif (rising_edge(pi_i2c_scl)) then
--address sequence.
if (reg_cur_sp = start and reg_cur_state = idle) then
reg_i2c_cmd_addr (6) <= pio_i2c_sda;
elsif (reg_cur_state = a6) then
reg_i2c_cmd_addr (5) <= pio_i2c_sda;
elsif (reg_cur_state = a5) then
reg_i2c_cmd_addr (4) <= pio_i2c_sda;
elsif (reg_cur_state = a4) then
reg_i2c_cmd_addr (3) <= pio_i2c_sda;
elsif (reg_cur_state = a3) then
reg_i2c_cmd_addr (2) <= pio_i2c_sda;
elsif (reg_cur_state = a2) then
reg_i2c_cmd_addr (1) <= pio_i2c_sda;
elsif (reg_cur_state = a1) then
reg_i2c_cmd_addr (0) <= pio_i2c_sda;
elsif (reg_cur_state = a0) then
reg_i2c_cmd_r_nw <= pio_i2c_sda;
--data write sequence (input).
elsif (reg_cur_state = a_ack and reg_i2c_cmd_r_nw = '0') then
reg_i2c_cmd_in_data (6) <= pio_i2c_sda;
elsif (reg_cur_state = d7 and reg_i2c_cmd_r_nw = '0') then
reg_i2c_cmd_in_data (5) <= pio_i2c_sda;
elsif (reg_cur_state = d6 and reg_i2c_cmd_r_nw = '0') then
reg_i2c_cmd_in_data (4) <= pio_i2c_sda;
elsif (reg_cur_state = d5 and reg_i2c_cmd_r_nw = '0') then
reg_i2c_cmd_in_data (3) <= pio_i2c_sda;
elsif (reg_cur_state = d4 and reg_i2c_cmd_r_nw = '0') then
reg_i2c_cmd_in_data (2) <= pio_i2c_sda;
elsif (reg_cur_state = d3 and reg_i2c_cmd_r_nw = '0') then
reg_i2c_cmd_in_data (1) <= pio_i2c_sda;
elsif (reg_cur_state = d2 and reg_i2c_cmd_r_nw = '0') then
reg_i2c_cmd_in_data (0) <= pio_i2c_sda;
elsif (reg_cur_state = d1 and reg_i2c_cmd_r_nw = '0') then
po_slave_in_data <= reg_i2c_cmd_in_data & pio_i2c_sda;
end if;
end if;--if (pi_rst_n = '0') then
end process;
--output status.
out_stat : process (pi_rst_n, pi_i2c_scl)
begin
if (pi_rst_n = '0') then
po_i2c_status <= (others => '0');
elsif (rising_edge(pi_i2c_scl)) then
if (reg_i2c_cmd_addr = pi_slave_addr) then
if (reg_cur_state = d7 or
reg_cur_state = d6 or
reg_cur_state = d5 or
reg_cur_state = d4 or
reg_cur_state = d3 or
reg_cur_state = d2 or
reg_cur_state = d1 or
reg_cur_state = d0 or
reg_cur_state = d_ack) then
po_i2c_status(0) <= '1';
else
po_i2c_status(0) <= '0';
end if;
po_i2c_status(2) <= reg_i2c_cmd_r_nw;
if (reg_cur_state = d_ack and reg_i2c_cmd_r_nw = '0') then
--write
po_i2c_status(1) <= '1';
elsif (reg_cur_state = d0 and reg_i2c_cmd_r_nw = '1') then
--read
po_i2c_status(1) <= not pio_i2c_sda;
else
po_i2c_status(1) <= '0';
end if;
else
po_i2c_status <= (others => '0');
end if;--if (reg_i2c_cmd_addr = pi_slave_addr) then
end if;--if (pi_rst_n = '0') then
end process;
--output (ack and read response: output) i2c bus.
out_data : process (pi_rst_n, pi_i2c_scl)
begin
if (pi_rst_n = '0') then
pio_i2c_sda <= 'Z';
elsif (falling_edge(pi_i2c_scl)) then
if (reg_i2c_cmd_addr = pi_slave_addr) then
if (reg_cur_state = rw) then
--addr ack reply.
pio_i2c_sda <= '0';
elsif (reg_cur_state = a_ack) then
--data input.
if (reg_i2c_cmd_r_nw = '0') then
pio_i2c_sda <= 'Z';
--data output.
else
pio_i2c_sda <= pi_slave_out_data(7);
end if;
--data output.
elsif (reg_cur_state = d7 and reg_i2c_cmd_r_nw = '1') then
pio_i2c_sda <= pi_slave_out_data(6);
elsif (reg_cur_state = d6 and reg_i2c_cmd_r_nw = '1') then
pio_i2c_sda <= pi_slave_out_data(5);
elsif (reg_cur_state = d5 and reg_i2c_cmd_r_nw = '1') then
pio_i2c_sda <= pi_slave_out_data(4);
elsif (reg_cur_state = d4 and reg_i2c_cmd_r_nw = '1') then
pio_i2c_sda <= pi_slave_out_data(3);
elsif (reg_cur_state = d3 and reg_i2c_cmd_r_nw = '1') then
pio_i2c_sda <= pi_slave_out_data(2);
elsif (reg_cur_state = d2 and reg_i2c_cmd_r_nw = '1') then
pio_i2c_sda <= pi_slave_out_data(1);
elsif (reg_cur_state = d1 and reg_i2c_cmd_r_nw = '1') then
pio_i2c_sda <= pi_slave_out_data(0);
elsif (reg_cur_state = d0) then
--data ack reply.
if (reg_i2c_cmd_r_nw = '0') then
pio_i2c_sda <= '0';
else
--yield bus for incoming data.
pio_i2c_sda <= 'Z';
end if;
elsif (reg_cur_state = d_ack) then
--data receive.
if (reg_i2c_cmd_r_nw = '0') then
pio_i2c_sda <= 'Z';
else
--data out.
pio_i2c_sda <= pi_slave_out_data(7);
end if;
end if;
else
pio_i2c_sda <= 'Z';
end if;--reg_i2c_cmd_addr = pi_slave_addr
end if;--if (pi_rst_n = '0') then
end process;
end rtl;
| apache-2.0 | 98355bfab9051d47732a265c23f4d96d | 0.44406 | 3.152608 | false | false | false | false |
varunnagpaal/Digital-Hardware-Modelling | vhdl/filter/fir_picoblaze/ssg_program.vhd | 1 | 232,369 | --
-------------------------------------------------------------------------------------------
-- Copyright © 2010-2013, Xilinx, Inc.
-- This file contains confidential and proprietary information of Xilinx, Inc. and is
-- protected under U.S. and international copyright and other intellectual property laws.
-------------------------------------------------------------------------------------------
--
-- Disclaimer:
-- This disclaimer is not a license and does not grant any rights to the materials
-- distributed herewith. Except as otherwise provided in a valid license issued to
-- you by Xilinx, and to the maximum extent permitted by applicable law: (1) THESE
-- MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND XILINX HEREBY
-- DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY,
-- INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT,
-- OR FITNESS FOR ANY PARTICULAR PURPOSE; and (2) Xilinx shall not be liable
-- (whether in contract or tort, including negligence, or under any other theory
-- of liability) for any loss or damage of any kind or nature related to, arising
-- under or in connection with these materials, including for any direct, or any
-- indirect, special, incidental, or consequential loss or damage (including loss
-- of data, profits, goodwill, or any type of loss or damage suffered as a result
-- of any action brought by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-safe, or for use in any
-- application requiring fail-safe performance, such as life-support or safety
-- devices or systems, Class III medical devices, nuclear facilities, applications
-- related to the deployment of airbags, or any other applications that could lead
-- to death, personal injury, or severe property or environmental damage
-- (individually and collectively, "Critical Applications"). Customer assumes the
-- sole risk and liability of any use of Xilinx products in Critical Applications,
-- subject only to applicable laws and regulations governing limitations on product
-- liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE AT ALL TIMES.
--
-------------------------------------------------------------------------------------------
--
--
-- Definition of a program memory for KCPSM6 including generic parameters for the
-- convenient selection of device family, program memory size and the ability to include
-- the JTAG Loader hardware for rapid software development.
--
-- This file is primarily for use during code development and it is recommended that the
-- appropriate simplified program memory definition be used in a final production design.
--
-- Generic Values Comments
-- Parameter Supported
--
-- C_FAMILY "S6" Spartan-6 device
-- "V6" Virtex-6 device
-- "7S" 7-Series device
-- (Artix-7, Kintex-7, Virtex-7 or Zynq)
--
-- C_RAM_SIZE_KWORDS 1, 2 or 4 Size of program memory in K-instructions
--
-- C_JTAG_LOADER_ENABLE 0 or 1 Set to '1' to include JTAG Loader
--
-- Notes
--
-- If your design contains MULTIPLE KCPSM6 instances then only one should have the
-- JTAG Loader enabled at a time (i.e. make sure that C_JTAG_LOADER_ENABLE is only set to
-- '1' on one instance of the program memory). Advanced users may be interested to know
-- that it is possible to connect JTAG Loader to multiple memories and then to use the
-- JTAG Loader utility to specify which memory contents are to be modified. However,
-- this scheme does require some effort to set up and the additional connectivity of the
-- multiple BRAMs can impact the placement, routing and performance of the complete
-- design. Please contact the author at Xilinx for more detailed information.
--
-- Regardless of the size of program memory specified by C_RAM_SIZE_KWORDS, the complete
-- 12-bit address bus is connected to KCPSM6. This enables the generic to be modified
-- without requiring changes to the fundamental hardware definition. However, when the
-- program memory is 1K then only the lower 10-bits of the address are actually used and
-- the valid address range is 000 to 3FF hex. Likewise, for a 2K program only the lower
-- 11-bits of the address are actually used and the valid address range is 000 to 7FF hex.
--
-- Programs are stored in Block Memory (BRAM) and the number of BRAM used depends on the
-- size of the program and the device family.
--
-- In a Spartan-6 device a BRAM is capable of holding 1K instructions. Hence a 2K program
-- will require 2 BRAMs to be used and a 4K program will require 4 BRAMs to be used. It
-- should be noted that a 4K program is not such a natural fit in a Spartan-6 device and
-- the implementation also requires a small amount of logic resulting in slightly lower
-- performance. A Spartan-6 BRAM can also be split into two 9k-bit memories suggesting
-- that a program containing up to 512 instructions could be implemented. However, there
-- is a silicon errata which makes this unsuitable and therefore it is not supported by
-- this file.
--
-- In a Virtex-6 or any 7-Series device a BRAM is capable of holding 2K instructions so
-- obviously a 2K program requires only a single BRAM. Each BRAM can also be divided into
-- 2 smaller memories supporting programs of 1K in half of a 36k-bit BRAM (generally
-- reported as being an 18k-bit BRAM). For a program of 4K instructions, 2 BRAMs are used.
--
--
-- Program defined by 'D:\github\Embedded\Lab 3\ssg_program.psm'.
--
-- Generated by KCPSM6 Assembler: 09 Dec 2018 - 12:55:25.
--
-- Assembler used ROM_form template: ROM_form_JTAGLoader_14March13.vhd
--
-- Standard IEEE libraries
--
--
package jtag_loader_pkg is
function addr_width_calc (size_in_k: integer) return integer;
end jtag_loader_pkg;
--
package body jtag_loader_pkg is
function addr_width_calc (size_in_k: integer) return integer is
begin
if (size_in_k = 1) then return 10;
elsif (size_in_k = 2) then return 11;
elsif (size_in_k = 4) then return 12;
else report "Invalid BlockRAM size. Please set to 1, 2 or 4 K words." severity FAILURE;
end if;
return 0;
end function addr_width_calc;
end package body;
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use work.jtag_loader_pkg.ALL;
--
-- The Unisim Library is used to define Xilinx primitives. It is also used during
-- simulation. The source can be viewed at %XILINX%\vhdl\src\unisims\unisim_VCOMP.vhd
--
library unisim;
use unisim.vcomponents.all;
--
--
entity ssg_program is
generic( C_FAMILY : string := "S6";
C_RAM_SIZE_KWORDS : integer := 1;
C_JTAG_LOADER_ENABLE : integer := 0);
Port ( address : in std_logic_vector(11 downto 0);
instruction : out std_logic_vector(17 downto 0);
enable : in std_logic;
rdl : out std_logic;
clk : in std_logic);
end ssg_program;
--
architecture low_level_definition of ssg_program is
--
signal address_a : std_logic_vector(15 downto 0);
signal pipe_a11 : std_logic;
signal data_in_a : std_logic_vector(35 downto 0);
signal data_out_a : std_logic_vector(35 downto 0);
signal data_out_a_l : std_logic_vector(35 downto 0);
signal data_out_a_h : std_logic_vector(35 downto 0);
signal data_out_a_ll : std_logic_vector(35 downto 0);
signal data_out_a_lh : std_logic_vector(35 downto 0);
signal data_out_a_hl : std_logic_vector(35 downto 0);
signal data_out_a_hh : std_logic_vector(35 downto 0);
signal address_b : std_logic_vector(15 downto 0);
signal data_in_b : std_logic_vector(35 downto 0);
signal data_in_b_l : std_logic_vector(35 downto 0);
signal data_in_b_ll : std_logic_vector(35 downto 0);
signal data_in_b_hl : std_logic_vector(35 downto 0);
signal data_out_b : std_logic_vector(35 downto 0);
signal data_out_b_l : std_logic_vector(35 downto 0);
signal data_out_b_ll : std_logic_vector(35 downto 0);
signal data_out_b_hl : std_logic_vector(35 downto 0);
signal data_in_b_h : std_logic_vector(35 downto 0);
signal data_in_b_lh : std_logic_vector(35 downto 0);
signal data_in_b_hh : std_logic_vector(35 downto 0);
signal data_out_b_h : std_logic_vector(35 downto 0);
signal data_out_b_lh : std_logic_vector(35 downto 0);
signal data_out_b_hh : std_logic_vector(35 downto 0);
signal enable_b : std_logic;
signal clk_b : std_logic;
signal we_b : std_logic_vector(7 downto 0);
signal we_b_l : std_logic_vector(3 downto 0);
signal we_b_h : std_logic_vector(3 downto 0);
--
signal jtag_addr : std_logic_vector(11 downto 0);
signal jtag_we : std_logic;
signal jtag_we_l : std_logic;
signal jtag_we_h : std_logic;
signal jtag_clk : std_logic;
signal jtag_din : std_logic_vector(17 downto 0);
signal jtag_dout : std_logic_vector(17 downto 0);
signal jtag_dout_1 : std_logic_vector(17 downto 0);
signal jtag_en : std_logic_vector(0 downto 0);
--
signal picoblaze_reset : std_logic_vector(0 downto 0);
signal rdl_bus : std_logic_vector(0 downto 0);
--
constant BRAM_ADDRESS_WIDTH : integer := addr_width_calc(C_RAM_SIZE_KWORDS);
--
--
component jtag_loader_6
generic( C_JTAG_LOADER_ENABLE : integer := 1;
C_FAMILY : string := "V6";
C_NUM_PICOBLAZE : integer := 1;
C_BRAM_MAX_ADDR_WIDTH : integer := 10;
C_PICOBLAZE_INSTRUCTION_DATA_WIDTH : integer := 18;
C_JTAG_CHAIN : integer := 2;
C_ADDR_WIDTH_0 : integer := 10;
C_ADDR_WIDTH_1 : integer := 10;
C_ADDR_WIDTH_2 : integer := 10;
C_ADDR_WIDTH_3 : integer := 10;
C_ADDR_WIDTH_4 : integer := 10;
C_ADDR_WIDTH_5 : integer := 10;
C_ADDR_WIDTH_6 : integer := 10;
C_ADDR_WIDTH_7 : integer := 10);
port( picoblaze_reset : out std_logic_vector(C_NUM_PICOBLAZE-1 downto 0);
jtag_en : out std_logic_vector(C_NUM_PICOBLAZE-1 downto 0);
jtag_din : out STD_LOGIC_VECTOR(C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-1 downto 0);
jtag_addr : out STD_LOGIC_VECTOR(C_BRAM_MAX_ADDR_WIDTH-1 downto 0);
jtag_clk : out std_logic;
jtag_we : out std_logic;
jtag_dout_0 : in STD_LOGIC_VECTOR(C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-1 downto 0);
jtag_dout_1 : in STD_LOGIC_VECTOR(C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-1 downto 0);
jtag_dout_2 : in STD_LOGIC_VECTOR(C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-1 downto 0);
jtag_dout_3 : in STD_LOGIC_VECTOR(C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-1 downto 0);
jtag_dout_4 : in STD_LOGIC_VECTOR(C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-1 downto 0);
jtag_dout_5 : in STD_LOGIC_VECTOR(C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-1 downto 0);
jtag_dout_6 : in STD_LOGIC_VECTOR(C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-1 downto 0);
jtag_dout_7 : in STD_LOGIC_VECTOR(C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-1 downto 0));
end component;
--
begin
--
--
ram_1k_generate : if (C_RAM_SIZE_KWORDS = 1) generate
s6: if (C_FAMILY = "S6") generate
--
address_a(13 downto 0) <= address(9 downto 0) & "0000";
instruction <= data_out_a(33 downto 32) & data_out_a(15 downto 0);
data_in_a <= "0000000000000000000000000000000000" & address(11 downto 10);
jtag_dout <= data_out_b(33 downto 32) & data_out_b(15 downto 0);
--
no_loader : if (C_JTAG_LOADER_ENABLE = 0) generate
data_in_b <= "00" & data_out_b(33 downto 32) & "0000000000000000" & data_out_b(15 downto 0);
address_b(13 downto 0) <= "00000000000000";
we_b(3 downto 0) <= "0000";
enable_b <= '0';
rdl <= '0';
clk_b <= '0';
end generate no_loader;
--
loader : if (C_JTAG_LOADER_ENABLE = 1) generate
data_in_b <= "00" & jtag_din(17 downto 16) & "0000000000000000" & jtag_din(15 downto 0);
address_b(13 downto 0) <= jtag_addr(9 downto 0) & "0000";
we_b(3 downto 0) <= jtag_we & jtag_we & jtag_we & jtag_we;
enable_b <= jtag_en(0);
rdl <= rdl_bus(0);
clk_b <= jtag_clk;
end generate loader;
--
kcpsm6_rom: RAMB16BWER
generic map ( DATA_WIDTH_A => 18,
DOA_REG => 0,
EN_RSTRAM_A => FALSE,
INIT_A => X"000000000",
RST_PRIORITY_A => "CE",
SRVAL_A => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
DATA_WIDTH_B => 18,
DOB_REG => 0,
EN_RSTRAM_B => FALSE,
INIT_B => X"000000000",
RST_PRIORITY_B => "CE",
SRVAL_B => X"000000000",
WRITE_MODE_B => "WRITE_FIRST",
RSTTYPE => "SYNC",
INIT_FILE => "NONE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "SPARTAN6",
INIT_00 => X"00000000000000000000000000002000D0020010D203D101D000920291019000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000029A80",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000")
port map( ADDRA => address_a(13 downto 0),
ENA => enable,
CLKA => clk,
DOA => data_out_a(31 downto 0),
DOPA => data_out_a(35 downto 32),
DIA => data_in_a(31 downto 0),
DIPA => data_in_a(35 downto 32),
WEA => "0000",
REGCEA => '0',
RSTA => '0',
ADDRB => address_b(13 downto 0),
ENB => enable_b,
CLKB => clk_b,
DOB => data_out_b(31 downto 0),
DOPB => data_out_b(35 downto 32),
DIB => data_in_b(31 downto 0),
DIPB => data_in_b(35 downto 32),
WEB => we_b(3 downto 0),
REGCEB => '0',
RSTB => '0');
--
end generate s6;
--
--
v6 : if (C_FAMILY = "V6") generate
--
address_a(13 downto 0) <= address(9 downto 0) & "1111";
instruction <= data_out_a(17 downto 0);
data_in_a(17 downto 0) <= "0000000000000000" & address(11 downto 10);
jtag_dout <= data_out_b(17 downto 0);
--
no_loader : if (C_JTAG_LOADER_ENABLE = 0) generate
data_in_b(17 downto 0) <= data_out_b(17 downto 0);
address_b(13 downto 0) <= "11111111111111";
we_b(3 downto 0) <= "0000";
enable_b <= '0';
rdl <= '0';
clk_b <= '0';
end generate no_loader;
--
loader : if (C_JTAG_LOADER_ENABLE = 1) generate
data_in_b(17 downto 0) <= jtag_din(17 downto 0);
address_b(13 downto 0) <= jtag_addr(9 downto 0) & "1111";
we_b(3 downto 0) <= jtag_we & jtag_we & jtag_we & jtag_we;
enable_b <= jtag_en(0);
rdl <= rdl_bus(0);
clk_b <= jtag_clk;
end generate loader;
--
kcpsm6_rom: RAMB18E1
generic map ( READ_WIDTH_A => 18,
WRITE_WIDTH_A => 18,
DOA_REG => 0,
INIT_A => "000000000000000000",
RSTREG_PRIORITY_A => "REGCE",
SRVAL_A => X"000000000000000000",
WRITE_MODE_A => "WRITE_FIRST",
READ_WIDTH_B => 18,
WRITE_WIDTH_B => 18,
DOB_REG => 0,
INIT_B => X"000000000000000000",
RSTREG_PRIORITY_B => "REGCE",
SRVAL_B => X"000000000000000000",
WRITE_MODE_B => "WRITE_FIRST",
INIT_FILE => "NONE",
SIM_COLLISION_CHECK => "ALL",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE",
SIM_DEVICE => "VIRTEX6",
INIT_00 => X"00000000000000000000000000002000D0020010D203D101D000920291019000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000029A80",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000")
port map( ADDRARDADDR => address_a(13 downto 0),
ENARDEN => enable,
CLKARDCLK => clk,
DOADO => data_out_a(15 downto 0),
DOPADOP => data_out_a(17 downto 16),
DIADI => data_in_a(15 downto 0),
DIPADIP => data_in_a(17 downto 16),
WEA => "00",
REGCEAREGCE => '0',
RSTRAMARSTRAM => '0',
RSTREGARSTREG => '0',
ADDRBWRADDR => address_b(13 downto 0),
ENBWREN => enable_b,
CLKBWRCLK => clk_b,
DOBDO => data_out_b(15 downto 0),
DOPBDOP => data_out_b(17 downto 16),
DIBDI => data_in_b(15 downto 0),
DIPBDIP => data_in_b(17 downto 16),
WEBWE => we_b(3 downto 0),
REGCEB => '0',
RSTRAMB => '0',
RSTREGB => '0');
--
end generate v6;
--
--
akv7 : if (C_FAMILY = "7S") generate
--
address_a(13 downto 0) <= address(9 downto 0) & "1111";
instruction <= data_out_a(17 downto 0);
data_in_a(17 downto 0) <= "0000000000000000" & address(11 downto 10);
jtag_dout <= data_out_b(17 downto 0);
--
no_loader : if (C_JTAG_LOADER_ENABLE = 0) generate
data_in_b(17 downto 0) <= data_out_b(17 downto 0);
address_b(13 downto 0) <= "11111111111111";
we_b(3 downto 0) <= "0000";
enable_b <= '0';
rdl <= '0';
clk_b <= '0';
end generate no_loader;
--
loader : if (C_JTAG_LOADER_ENABLE = 1) generate
data_in_b(17 downto 0) <= jtag_din(17 downto 0);
address_b(13 downto 0) <= jtag_addr(9 downto 0) & "1111";
we_b(3 downto 0) <= jtag_we & jtag_we & jtag_we & jtag_we;
enable_b <= jtag_en(0);
rdl <= rdl_bus(0);
clk_b <= jtag_clk;
end generate loader;
--
kcpsm6_rom: RAMB18E1
generic map ( READ_WIDTH_A => 18,
WRITE_WIDTH_A => 18,
DOA_REG => 0,
INIT_A => "000000000000000000",
RSTREG_PRIORITY_A => "REGCE",
SRVAL_A => X"000000000000000000",
WRITE_MODE_A => "WRITE_FIRST",
READ_WIDTH_B => 18,
WRITE_WIDTH_B => 18,
DOB_REG => 0,
INIT_B => X"000000000000000000",
RSTREG_PRIORITY_B => "REGCE",
SRVAL_B => X"000000000000000000",
WRITE_MODE_B => "WRITE_FIRST",
INIT_FILE => "NONE",
SIM_COLLISION_CHECK => "ALL",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE",
SIM_DEVICE => "7SERIES",
INIT_00 => X"00000000000000000000000000002000D0020010D203D101D000920291019000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000029A80",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000")
port map( ADDRARDADDR => address_a(13 downto 0),
ENARDEN => enable,
CLKARDCLK => clk,
DOADO => data_out_a(15 downto 0),
DOPADOP => data_out_a(17 downto 16),
DIADI => data_in_a(15 downto 0),
DIPADIP => data_in_a(17 downto 16),
WEA => "00",
REGCEAREGCE => '0',
RSTRAMARSTRAM => '0',
RSTREGARSTREG => '0',
ADDRBWRADDR => address_b(13 downto 0),
ENBWREN => enable_b,
CLKBWRCLK => clk_b,
DOBDO => data_out_b(15 downto 0),
DOPBDOP => data_out_b(17 downto 16),
DIBDI => data_in_b(15 downto 0),
DIPBDIP => data_in_b(17 downto 16),
WEBWE => we_b(3 downto 0),
REGCEB => '0',
RSTRAMB => '0',
RSTREGB => '0');
--
end generate akv7;
--
end generate ram_1k_generate;
--
--
--
ram_2k_generate : if (C_RAM_SIZE_KWORDS = 2) generate
--
--
s6: if (C_FAMILY = "S6") generate
--
address_a(13 downto 0) <= address(10 downto 0) & "000";
instruction <= data_out_a_h(32) & data_out_a_h(7 downto 0) & data_out_a_l(32) & data_out_a_l(7 downto 0);
data_in_a <= "00000000000000000000000000000000000" & address(11);
jtag_dout <= data_out_b_h(32) & data_out_b_h(7 downto 0) & data_out_b_l(32) & data_out_b_l(7 downto 0);
--
no_loader : if (C_JTAG_LOADER_ENABLE = 0) generate
data_in_b_l <= "000" & data_out_b_l(32) & "000000000000000000000000" & data_out_b_l(7 downto 0);
data_in_b_h <= "000" & data_out_b_h(32) & "000000000000000000000000" & data_out_b_h(7 downto 0);
address_b(13 downto 0) <= "00000000000000";
we_b(3 downto 0) <= "0000";
enable_b <= '0';
rdl <= '0';
clk_b <= '0';
end generate no_loader;
--
loader : if (C_JTAG_LOADER_ENABLE = 1) generate
data_in_b_h <= "000" & jtag_din(17) & "000000000000000000000000" & jtag_din(16 downto 9);
data_in_b_l <= "000" & jtag_din(8) & "000000000000000000000000" & jtag_din(7 downto 0);
address_b(13 downto 0) <= jtag_addr(10 downto 0) & "000";
we_b(3 downto 0) <= jtag_we & jtag_we & jtag_we & jtag_we;
enable_b <= jtag_en(0);
rdl <= rdl_bus(0);
clk_b <= jtag_clk;
end generate loader;
--
kcpsm6_rom_l: RAMB16BWER
generic map ( DATA_WIDTH_A => 9,
DOA_REG => 0,
EN_RSTRAM_A => FALSE,
INIT_A => X"000000000",
RST_PRIORITY_A => "CE",
SRVAL_A => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
DATA_WIDTH_B => 9,
DOB_REG => 0,
EN_RSTRAM_B => FALSE,
INIT_B => X"000000000",
RST_PRIORITY_B => "CE",
SRVAL_B => X"000000000",
WRITE_MODE_B => "WRITE_FIRST",
RSTTYPE => "SYNC",
INIT_FILE => "NONE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "SPARTAN6",
INIT_00 => X"0000000000000000000000000000000000000000000000000210030100020100",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000012",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000")
port map( ADDRA => address_a(13 downto 0),
ENA => enable,
CLKA => clk,
DOA => data_out_a_l(31 downto 0),
DOPA => data_out_a_l(35 downto 32),
DIA => data_in_a(31 downto 0),
DIPA => data_in_a(35 downto 32),
WEA => "0000",
REGCEA => '0',
RSTA => '0',
ADDRB => address_b(13 downto 0),
ENB => enable_b,
CLKB => clk_b,
DOB => data_out_b_l(31 downto 0),
DOPB => data_out_b_l(35 downto 32),
DIB => data_in_b_l(31 downto 0),
DIPB => data_in_b_l(35 downto 32),
WEB => we_b(3 downto 0),
REGCEB => '0',
RSTB => '0');
--
kcpsm6_rom_h: RAMB16BWER
generic map ( DATA_WIDTH_A => 9,
DOA_REG => 0,
EN_RSTRAM_A => FALSE,
INIT_A => X"000000000",
RST_PRIORITY_A => "CE",
SRVAL_A => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
DATA_WIDTH_B => 9,
DOB_REG => 0,
EN_RSTRAM_B => FALSE,
INIT_B => X"000000000",
RST_PRIORITY_B => "CE",
SRVAL_B => X"000000000",
WRITE_MODE_B => "WRITE_FIRST",
RSTTYPE => "SYNC",
INIT_FILE => "NONE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "SPARTAN6",
INIT_00 => X"0000000000000000000000000000000000000000000000106880696868494848",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_00 => X"00000000000000000000000000000000000000000000000000000000000001B8",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000")
port map( ADDRA => address_a(13 downto 0),
ENA => enable,
CLKA => clk,
DOA => data_out_a_h(31 downto 0),
DOPA => data_out_a_h(35 downto 32),
DIA => data_in_a(31 downto 0),
DIPA => data_in_a(35 downto 32),
WEA => "0000",
REGCEA => '0',
RSTA => '0',
ADDRB => address_b(13 downto 0),
ENB => enable_b,
CLKB => clk_b,
DOB => data_out_b_h(31 downto 0),
DOPB => data_out_b_h(35 downto 32),
DIB => data_in_b_h(31 downto 0),
DIPB => data_in_b_h(35 downto 32),
WEB => we_b(3 downto 0),
REGCEB => '0',
RSTB => '0');
--
end generate s6;
--
--
v6 : if (C_FAMILY = "V6") generate
--
address_a <= '1' & address(10 downto 0) & "1111";
instruction <= data_out_a(33 downto 32) & data_out_a(15 downto 0);
data_in_a <= "00000000000000000000000000000000000" & address(11);
jtag_dout <= data_out_b(33 downto 32) & data_out_b(15 downto 0);
--
no_loader : if (C_JTAG_LOADER_ENABLE = 0) generate
data_in_b <= "00" & data_out_b(33 downto 32) & "0000000000000000" & data_out_b(15 downto 0);
address_b <= "1111111111111111";
we_b <= "00000000";
enable_b <= '0';
rdl <= '0';
clk_b <= '0';
end generate no_loader;
--
loader : if (C_JTAG_LOADER_ENABLE = 1) generate
data_in_b <= "00" & jtag_din(17 downto 16) & "0000000000000000" & jtag_din(15 downto 0);
address_b <= '1' & jtag_addr(10 downto 0) & "1111";
we_b <= jtag_we & jtag_we & jtag_we & jtag_we & jtag_we & jtag_we & jtag_we & jtag_we;
enable_b <= jtag_en(0);
rdl <= rdl_bus(0);
clk_b <= jtag_clk;
end generate loader;
--
kcpsm6_rom: RAMB36E1
generic map ( READ_WIDTH_A => 18,
WRITE_WIDTH_A => 18,
DOA_REG => 0,
INIT_A => X"000000000",
RSTREG_PRIORITY_A => "REGCE",
SRVAL_A => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
READ_WIDTH_B => 18,
WRITE_WIDTH_B => 18,
DOB_REG => 0,
INIT_B => X"000000000",
RSTREG_PRIORITY_B => "REGCE",
SRVAL_B => X"000000000",
WRITE_MODE_B => "WRITE_FIRST",
INIT_FILE => "NONE",
SIM_COLLISION_CHECK => "ALL",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE",
EN_ECC_READ => FALSE,
EN_ECC_WRITE => FALSE,
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
SIM_DEVICE => "VIRTEX6",
INIT_00 => X"00000000000000000000000000002000D0020010D203D101D000920291019000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_40 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_41 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_42 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_43 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_44 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_45 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_46 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_47 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_48 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_49 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_50 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_51 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_52 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_53 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_54 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_55 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_56 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_57 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_58 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_59 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_60 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_61 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_62 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_63 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_64 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_65 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_66 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_67 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_68 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_69 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_70 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_71 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_72 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_73 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_74 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000029A80",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000")
port map( ADDRARDADDR => address_a,
ENARDEN => enable,
CLKARDCLK => clk,
DOADO => data_out_a(31 downto 0),
DOPADOP => data_out_a(35 downto 32),
DIADI => data_in_a(31 downto 0),
DIPADIP => data_in_a(35 downto 32),
WEA => "0000",
REGCEAREGCE => '0',
RSTRAMARSTRAM => '0',
RSTREGARSTREG => '0',
ADDRBWRADDR => address_b,
ENBWREN => enable_b,
CLKBWRCLK => clk_b,
DOBDO => data_out_b(31 downto 0),
DOPBDOP => data_out_b(35 downto 32),
DIBDI => data_in_b(31 downto 0),
DIPBDIP => data_in_b(35 downto 32),
WEBWE => we_b,
REGCEB => '0',
RSTRAMB => '0',
RSTREGB => '0',
CASCADEINA => '0',
CASCADEINB => '0',
INJECTDBITERR => '0',
INJECTSBITERR => '0');
--
end generate v6;
--
--
akv7 : if (C_FAMILY = "7S") generate
--
address_a <= '1' & address(10 downto 0) & "1111";
instruction <= data_out_a(33 downto 32) & data_out_a(15 downto 0);
data_in_a <= "00000000000000000000000000000000000" & address(11);
jtag_dout <= data_out_b(33 downto 32) & data_out_b(15 downto 0);
--
no_loader : if (C_JTAG_LOADER_ENABLE = 0) generate
data_in_b <= "00" & data_out_b(33 downto 32) & "0000000000000000" & data_out_b(15 downto 0);
address_b <= "1111111111111111";
we_b <= "00000000";
enable_b <= '0';
rdl <= '0';
clk_b <= '0';
end generate no_loader;
--
loader : if (C_JTAG_LOADER_ENABLE = 1) generate
data_in_b <= "00" & jtag_din(17 downto 16) & "0000000000000000" & jtag_din(15 downto 0);
address_b <= '1' & jtag_addr(10 downto 0) & "1111";
we_b <= jtag_we & jtag_we & jtag_we & jtag_we & jtag_we & jtag_we & jtag_we & jtag_we;
enable_b <= jtag_en(0);
rdl <= rdl_bus(0);
clk_b <= jtag_clk;
end generate loader;
--
kcpsm6_rom: RAMB36E1
generic map ( READ_WIDTH_A => 18,
WRITE_WIDTH_A => 18,
DOA_REG => 0,
INIT_A => X"000000000",
RSTREG_PRIORITY_A => "REGCE",
SRVAL_A => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
READ_WIDTH_B => 18,
WRITE_WIDTH_B => 18,
DOB_REG => 0,
INIT_B => X"000000000",
RSTREG_PRIORITY_B => "REGCE",
SRVAL_B => X"000000000",
WRITE_MODE_B => "WRITE_FIRST",
INIT_FILE => "NONE",
SIM_COLLISION_CHECK => "ALL",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE",
EN_ECC_READ => FALSE,
EN_ECC_WRITE => FALSE,
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
SIM_DEVICE => "7SERIES",
INIT_00 => X"00000000000000000000000000002000D0020010D203D101D000920291019000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_40 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_41 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_42 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_43 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_44 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_45 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_46 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_47 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_48 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_49 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_50 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_51 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_52 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_53 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_54 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_55 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_56 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_57 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_58 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_59 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_60 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_61 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_62 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_63 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_64 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_65 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_66 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_67 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_68 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_69 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_70 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_71 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_72 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_73 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_74 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000029A80",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000")
port map( ADDRARDADDR => address_a,
ENARDEN => enable,
CLKARDCLK => clk,
DOADO => data_out_a(31 downto 0),
DOPADOP => data_out_a(35 downto 32),
DIADI => data_in_a(31 downto 0),
DIPADIP => data_in_a(35 downto 32),
WEA => "0000",
REGCEAREGCE => '0',
RSTRAMARSTRAM => '0',
RSTREGARSTREG => '0',
ADDRBWRADDR => address_b,
ENBWREN => enable_b,
CLKBWRCLK => clk_b,
DOBDO => data_out_b(31 downto 0),
DOPBDOP => data_out_b(35 downto 32),
DIBDI => data_in_b(31 downto 0),
DIPBDIP => data_in_b(35 downto 32),
WEBWE => we_b,
REGCEB => '0',
RSTRAMB => '0',
RSTREGB => '0',
CASCADEINA => '0',
CASCADEINB => '0',
INJECTDBITERR => '0',
INJECTSBITERR => '0');
--
end generate akv7;
--
end generate ram_2k_generate;
--
--
ram_4k_generate : if (C_RAM_SIZE_KWORDS = 4) generate
s6: if (C_FAMILY = "S6") generate
--
address_a(13 downto 0) <= address(10 downto 0) & "000";
data_in_a <= "000000000000000000000000000000000000";
--
s6_a11_flop: FD
port map ( D => address(11),
Q => pipe_a11,
C => clk);
--
s6_4k_mux0_lut: LUT6_2
generic map (INIT => X"FF00F0F0CCCCAAAA")
port map( I0 => data_out_a_ll(0),
I1 => data_out_a_hl(0),
I2 => data_out_a_ll(1),
I3 => data_out_a_hl(1),
I4 => pipe_a11,
I5 => '1',
O5 => instruction(0),
O6 => instruction(1));
--
s6_4k_mux2_lut: LUT6_2
generic map (INIT => X"FF00F0F0CCCCAAAA")
port map( I0 => data_out_a_ll(2),
I1 => data_out_a_hl(2),
I2 => data_out_a_ll(3),
I3 => data_out_a_hl(3),
I4 => pipe_a11,
I5 => '1',
O5 => instruction(2),
O6 => instruction(3));
--
s6_4k_mux4_lut: LUT6_2
generic map (INIT => X"FF00F0F0CCCCAAAA")
port map( I0 => data_out_a_ll(4),
I1 => data_out_a_hl(4),
I2 => data_out_a_ll(5),
I3 => data_out_a_hl(5),
I4 => pipe_a11,
I5 => '1',
O5 => instruction(4),
O6 => instruction(5));
--
s6_4k_mux6_lut: LUT6_2
generic map (INIT => X"FF00F0F0CCCCAAAA")
port map( I0 => data_out_a_ll(6),
I1 => data_out_a_hl(6),
I2 => data_out_a_ll(7),
I3 => data_out_a_hl(7),
I4 => pipe_a11,
I5 => '1',
O5 => instruction(6),
O6 => instruction(7));
--
s6_4k_mux8_lut: LUT6_2
generic map (INIT => X"FF00F0F0CCCCAAAA")
port map( I0 => data_out_a_ll(32),
I1 => data_out_a_hl(32),
I2 => data_out_a_lh(0),
I3 => data_out_a_hh(0),
I4 => pipe_a11,
I5 => '1',
O5 => instruction(8),
O6 => instruction(9));
--
s6_4k_mux10_lut: LUT6_2
generic map (INIT => X"FF00F0F0CCCCAAAA")
port map( I0 => data_out_a_lh(1),
I1 => data_out_a_hh(1),
I2 => data_out_a_lh(2),
I3 => data_out_a_hh(2),
I4 => pipe_a11,
I5 => '1',
O5 => instruction(10),
O6 => instruction(11));
--
s6_4k_mux12_lut: LUT6_2
generic map (INIT => X"FF00F0F0CCCCAAAA")
port map( I0 => data_out_a_lh(3),
I1 => data_out_a_hh(3),
I2 => data_out_a_lh(4),
I3 => data_out_a_hh(4),
I4 => pipe_a11,
I5 => '1',
O5 => instruction(12),
O6 => instruction(13));
--
s6_4k_mux14_lut: LUT6_2
generic map (INIT => X"FF00F0F0CCCCAAAA")
port map( I0 => data_out_a_lh(5),
I1 => data_out_a_hh(5),
I2 => data_out_a_lh(6),
I3 => data_out_a_hh(6),
I4 => pipe_a11,
I5 => '1',
O5 => instruction(14),
O6 => instruction(15));
--
s6_4k_mux16_lut: LUT6_2
generic map (INIT => X"FF00F0F0CCCCAAAA")
port map( I0 => data_out_a_lh(7),
I1 => data_out_a_hh(7),
I2 => data_out_a_lh(32),
I3 => data_out_a_hh(32),
I4 => pipe_a11,
I5 => '1',
O5 => instruction(16),
O6 => instruction(17));
--
no_loader : if (C_JTAG_LOADER_ENABLE = 0) generate
data_in_b_ll <= "000" & data_out_b_ll(32) & "000000000000000000000000" & data_out_b_ll(7 downto 0);
data_in_b_lh <= "000" & data_out_b_lh(32) & "000000000000000000000000" & data_out_b_lh(7 downto 0);
data_in_b_hl <= "000" & data_out_b_hl(32) & "000000000000000000000000" & data_out_b_hl(7 downto 0);
data_in_b_hh <= "000" & data_out_b_hh(32) & "000000000000000000000000" & data_out_b_hh(7 downto 0);
address_b(13 downto 0) <= "00000000000000";
we_b_l(3 downto 0) <= "0000";
we_b_h(3 downto 0) <= "0000";
enable_b <= '0';
rdl <= '0';
clk_b <= '0';
jtag_dout <= data_out_b_lh(32) & data_out_b_lh(7 downto 0) & data_out_b_ll(32) & data_out_b_ll(7 downto 0);
end generate no_loader;
--
loader : if (C_JTAG_LOADER_ENABLE = 1) generate
data_in_b_lh <= "000" & jtag_din(17) & "000000000000000000000000" & jtag_din(16 downto 9);
data_in_b_ll <= "000" & jtag_din(8) & "000000000000000000000000" & jtag_din(7 downto 0);
data_in_b_hh <= "000" & jtag_din(17) & "000000000000000000000000" & jtag_din(16 downto 9);
data_in_b_hl <= "000" & jtag_din(8) & "000000000000000000000000" & jtag_din(7 downto 0);
address_b(13 downto 0) <= jtag_addr(10 downto 0) & "000";
--
s6_4k_jtag_we_lut: LUT6_2
generic map (INIT => X"8000000020000000")
port map( I0 => jtag_we,
I1 => jtag_addr(11),
I2 => '1',
I3 => '1',
I4 => '1',
I5 => '1',
O5 => jtag_we_l,
O6 => jtag_we_h);
--
we_b_l(3 downto 0) <= jtag_we_l & jtag_we_l & jtag_we_l & jtag_we_l;
we_b_h(3 downto 0) <= jtag_we_h & jtag_we_h & jtag_we_h & jtag_we_h;
--
enable_b <= jtag_en(0);
rdl <= rdl_bus(0);
clk_b <= jtag_clk;
--
s6_4k_jtag_mux0_lut: LUT6_2
generic map (INIT => X"FF00F0F0CCCCAAAA")
port map( I0 => data_out_b_ll(0),
I1 => data_out_b_hl(0),
I2 => data_out_b_ll(1),
I3 => data_out_b_hl(1),
I4 => jtag_addr(11),
I5 => '1',
O5 => jtag_dout(0),
O6 => jtag_dout(1));
--
s6_4k_jtag_mux2_lut: LUT6_2
generic map (INIT => X"FF00F0F0CCCCAAAA")
port map( I0 => data_out_b_ll(2),
I1 => data_out_b_hl(2),
I2 => data_out_b_ll(3),
I3 => data_out_b_hl(3),
I4 => jtag_addr(11),
I5 => '1',
O5 => jtag_dout(2),
O6 => jtag_dout(3));
--
s6_4k_jtag_mux4_lut: LUT6_2
generic map (INIT => X"FF00F0F0CCCCAAAA")
port map( I0 => data_out_b_ll(4),
I1 => data_out_b_hl(4),
I2 => data_out_b_ll(5),
I3 => data_out_b_hl(5),
I4 => jtag_addr(11),
I5 => '1',
O5 => jtag_dout(4),
O6 => jtag_dout(5));
--
s6_4k_jtag_mux6_lut: LUT6_2
generic map (INIT => X"FF00F0F0CCCCAAAA")
port map( I0 => data_out_b_ll(6),
I1 => data_out_b_hl(6),
I2 => data_out_b_ll(7),
I3 => data_out_b_hl(7),
I4 => jtag_addr(11),
I5 => '1',
O5 => jtag_dout(6),
O6 => jtag_dout(7));
--
s6_4k_jtag_mux8_lut: LUT6_2
generic map (INIT => X"FF00F0F0CCCCAAAA")
port map( I0 => data_out_b_ll(32),
I1 => data_out_b_hl(32),
I2 => data_out_b_lh(0),
I3 => data_out_b_hh(0),
I4 => jtag_addr(11),
I5 => '1',
O5 => jtag_dout(8),
O6 => jtag_dout(9));
--
s6_4k_jtag_mux10_lut: LUT6_2
generic map (INIT => X"FF00F0F0CCCCAAAA")
port map( I0 => data_out_b_lh(1),
I1 => data_out_b_hh(1),
I2 => data_out_b_lh(2),
I3 => data_out_b_hh(2),
I4 => jtag_addr(11),
I5 => '1',
O5 => jtag_dout(10),
O6 => jtag_dout(11));
--
s6_4k_jtag_mux12_lut: LUT6_2
generic map (INIT => X"FF00F0F0CCCCAAAA")
port map( I0 => data_out_b_lh(3),
I1 => data_out_b_hh(3),
I2 => data_out_b_lh(4),
I3 => data_out_b_hh(4),
I4 => jtag_addr(11),
I5 => '1',
O5 => jtag_dout(12),
O6 => jtag_dout(13));
--
s6_4k_jtag_mux14_lut: LUT6_2
generic map (INIT => X"FF00F0F0CCCCAAAA")
port map( I0 => data_out_b_lh(5),
I1 => data_out_b_hh(5),
I2 => data_out_b_lh(6),
I3 => data_out_b_hh(6),
I4 => jtag_addr(11),
I5 => '1',
O5 => jtag_dout(14),
O6 => jtag_dout(15));
--
s6_4k_jtag_mux16_lut: LUT6_2
generic map (INIT => X"FF00F0F0CCCCAAAA")
port map( I0 => data_out_b_lh(7),
I1 => data_out_b_hh(7),
I2 => data_out_b_lh(32),
I3 => data_out_b_hh(32),
I4 => jtag_addr(11),
I5 => '1',
O5 => jtag_dout(16),
O6 => jtag_dout(17));
--
end generate loader;
--
kcpsm6_rom_ll: RAMB16BWER
generic map ( DATA_WIDTH_A => 9,
DOA_REG => 0,
EN_RSTRAM_A => FALSE,
INIT_A => X"000000000",
RST_PRIORITY_A => "CE",
SRVAL_A => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
DATA_WIDTH_B => 9,
DOB_REG => 0,
EN_RSTRAM_B => FALSE,
INIT_B => X"000000000",
RST_PRIORITY_B => "CE",
SRVAL_B => X"000000000",
WRITE_MODE_B => "WRITE_FIRST",
RSTTYPE => "SYNC",
INIT_FILE => "NONE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "SPARTAN6",
INIT_00 => X"0000000000000000000000000000000000000000000000000210030100020100",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000012",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000")
port map( ADDRA => address_a(13 downto 0),
ENA => enable,
CLKA => clk,
DOA => data_out_a_ll(31 downto 0),
DOPA => data_out_a_ll(35 downto 32),
DIA => data_in_a(31 downto 0),
DIPA => data_in_a(35 downto 32),
WEA => "0000",
REGCEA => '0',
RSTA => '0',
ADDRB => address_b(13 downto 0),
ENB => enable_b,
CLKB => clk_b,
DOB => data_out_b_ll(31 downto 0),
DOPB => data_out_b_ll(35 downto 32),
DIB => data_in_b_ll(31 downto 0),
DIPB => data_in_b_ll(35 downto 32),
WEB => we_b_l(3 downto 0),
REGCEB => '0',
RSTB => '0');
--
kcpsm6_rom_lh: RAMB16BWER
generic map ( DATA_WIDTH_A => 9,
DOA_REG => 0,
EN_RSTRAM_A => FALSE,
INIT_A => X"000000000",
RST_PRIORITY_A => "CE",
SRVAL_A => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
DATA_WIDTH_B => 9,
DOB_REG => 0,
EN_RSTRAM_B => FALSE,
INIT_B => X"000000000",
RST_PRIORITY_B => "CE",
SRVAL_B => X"000000000",
WRITE_MODE_B => "WRITE_FIRST",
RSTTYPE => "SYNC",
INIT_FILE => "NONE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "SPARTAN6",
INIT_00 => X"0000000000000000000000000000000000000000000000106880696868494848",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_00 => X"00000000000000000000000000000000000000000000000000000000000001B8",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000")
port map( ADDRA => address_a(13 downto 0),
ENA => enable,
CLKA => clk,
DOA => data_out_a_lh(31 downto 0),
DOPA => data_out_a_lh(35 downto 32),
DIA => data_in_a(31 downto 0),
DIPA => data_in_a(35 downto 32),
WEA => "0000",
REGCEA => '0',
RSTA => '0',
ADDRB => address_b(13 downto 0),
ENB => enable_b,
CLKB => clk_b,
DOB => data_out_b_lh(31 downto 0),
DOPB => data_out_b_lh(35 downto 32),
DIB => data_in_b_lh(31 downto 0),
DIPB => data_in_b_lh(35 downto 32),
WEB => we_b_l(3 downto 0),
REGCEB => '0',
RSTB => '0');
--
kcpsm6_rom_hl: RAMB16BWER
generic map ( DATA_WIDTH_A => 9,
DOA_REG => 0,
EN_RSTRAM_A => FALSE,
INIT_A => X"000000000",
RST_PRIORITY_A => "CE",
SRVAL_A => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
DATA_WIDTH_B => 9,
DOB_REG => 0,
EN_RSTRAM_B => FALSE,
INIT_B => X"000000000",
RST_PRIORITY_B => "CE",
SRVAL_B => X"000000000",
WRITE_MODE_B => "WRITE_FIRST",
RSTTYPE => "SYNC",
INIT_FILE => "NONE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "SPARTAN6",
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000")
port map( ADDRA => address_a(13 downto 0),
ENA => enable,
CLKA => clk,
DOA => data_out_a_hl(31 downto 0),
DOPA => data_out_a_hl(35 downto 32),
DIA => data_in_a(31 downto 0),
DIPA => data_in_a(35 downto 32),
WEA => "0000",
REGCEA => '0',
RSTA => '0',
ADDRB => address_b(13 downto 0),
ENB => enable_b,
CLKB => clk_b,
DOB => data_out_b_hl(31 downto 0),
DOPB => data_out_b_hl(35 downto 32),
DIB => data_in_b_hl(31 downto 0),
DIPB => data_in_b_hl(35 downto 32),
WEB => we_b_h(3 downto 0),
REGCEB => '0',
RSTB => '0');
--
kcpsm6_rom_hh: RAMB16BWER
generic map ( DATA_WIDTH_A => 9,
DOA_REG => 0,
EN_RSTRAM_A => FALSE,
INIT_A => X"000000000",
RST_PRIORITY_A => "CE",
SRVAL_A => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
DATA_WIDTH_B => 9,
DOB_REG => 0,
EN_RSTRAM_B => FALSE,
INIT_B => X"000000000",
RST_PRIORITY_B => "CE",
SRVAL_B => X"000000000",
WRITE_MODE_B => "WRITE_FIRST",
RSTTYPE => "SYNC",
INIT_FILE => "NONE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "SPARTAN6",
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000")
port map( ADDRA => address_a(13 downto 0),
ENA => enable,
CLKA => clk,
DOA => data_out_a_hh(31 downto 0),
DOPA => data_out_a_hh(35 downto 32),
DIA => data_in_a(31 downto 0),
DIPA => data_in_a(35 downto 32),
WEA => "0000",
REGCEA => '0',
RSTA => '0',
ADDRB => address_b(13 downto 0),
ENB => enable_b,
CLKB => clk_b,
DOB => data_out_b_hh(31 downto 0),
DOPB => data_out_b_hh(35 downto 32),
DIB => data_in_b_hh(31 downto 0),
DIPB => data_in_b_hh(35 downto 32),
WEB => we_b_h(3 downto 0),
REGCEB => '0',
RSTB => '0');
--
end generate s6;
--
--
v6 : if (C_FAMILY = "V6") generate
--
address_a <= '1' & address(11 downto 0) & "111";
instruction <= data_out_a_h(32) & data_out_a_h(7 downto 0) & data_out_a_l(32) & data_out_a_l(7 downto 0);
data_in_a <= "000000000000000000000000000000000000";
jtag_dout <= data_out_b_h(32) & data_out_b_h(7 downto 0) & data_out_b_l(32) & data_out_b_l(7 downto 0);
--
no_loader : if (C_JTAG_LOADER_ENABLE = 0) generate
data_in_b_l <= "000" & data_out_b_l(32) & "000000000000000000000000" & data_out_b_l(7 downto 0);
data_in_b_h <= "000" & data_out_b_h(32) & "000000000000000000000000" & data_out_b_h(7 downto 0);
address_b <= "1111111111111111";
we_b <= "00000000";
enable_b <= '0';
rdl <= '0';
clk_b <= '0';
end generate no_loader;
--
loader : if (C_JTAG_LOADER_ENABLE = 1) generate
data_in_b_h <= "000" & jtag_din(17) & "000000000000000000000000" & jtag_din(16 downto 9);
data_in_b_l <= "000" & jtag_din(8) & "000000000000000000000000" & jtag_din(7 downto 0);
address_b <= '1' & jtag_addr(11 downto 0) & "111";
we_b <= jtag_we & jtag_we & jtag_we & jtag_we & jtag_we & jtag_we & jtag_we & jtag_we;
enable_b <= jtag_en(0);
rdl <= rdl_bus(0);
clk_b <= jtag_clk;
end generate loader;
--
kcpsm6_rom_l: RAMB36E1
generic map ( READ_WIDTH_A => 9,
WRITE_WIDTH_A => 9,
DOA_REG => 0,
INIT_A => X"000000000",
RSTREG_PRIORITY_A => "REGCE",
SRVAL_A => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
READ_WIDTH_B => 9,
WRITE_WIDTH_B => 9,
DOB_REG => 0,
INIT_B => X"000000000",
RSTREG_PRIORITY_B => "REGCE",
SRVAL_B => X"000000000",
WRITE_MODE_B => "WRITE_FIRST",
INIT_FILE => "NONE",
SIM_COLLISION_CHECK => "ALL",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE",
EN_ECC_READ => FALSE,
EN_ECC_WRITE => FALSE,
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
SIM_DEVICE => "VIRTEX6",
INIT_00 => X"0000000000000000000000000000000000000000000000000210030100020100",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_40 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_41 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_42 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_43 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_44 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_45 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_46 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_47 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_48 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_49 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_50 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_51 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_52 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_53 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_54 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_55 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_56 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_57 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_58 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_59 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_60 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_61 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_62 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_63 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_64 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_65 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_66 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_67 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_68 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_69 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_70 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_71 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_72 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_73 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_74 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000012",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000")
port map( ADDRARDADDR => address_a,
ENARDEN => enable,
CLKARDCLK => clk,
DOADO => data_out_a_l(31 downto 0),
DOPADOP => data_out_a_l(35 downto 32),
DIADI => data_in_a(31 downto 0),
DIPADIP => data_in_a(35 downto 32),
WEA => "0000",
REGCEAREGCE => '0',
RSTRAMARSTRAM => '0',
RSTREGARSTREG => '0',
ADDRBWRADDR => address_b,
ENBWREN => enable_b,
CLKBWRCLK => clk_b,
DOBDO => data_out_b_l(31 downto 0),
DOPBDOP => data_out_b_l(35 downto 32),
DIBDI => data_in_b_l(31 downto 0),
DIPBDIP => data_in_b_l(35 downto 32),
WEBWE => we_b,
REGCEB => '0',
RSTRAMB => '0',
RSTREGB => '0',
CASCADEINA => '0',
CASCADEINB => '0',
INJECTDBITERR => '0',
INJECTSBITERR => '0');
--
kcpsm6_rom_h: RAMB36E1
generic map ( READ_WIDTH_A => 9,
WRITE_WIDTH_A => 9,
DOA_REG => 0,
INIT_A => X"000000000",
RSTREG_PRIORITY_A => "REGCE",
SRVAL_A => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
READ_WIDTH_B => 9,
WRITE_WIDTH_B => 9,
DOB_REG => 0,
INIT_B => X"000000000",
RSTREG_PRIORITY_B => "REGCE",
SRVAL_B => X"000000000",
WRITE_MODE_B => "WRITE_FIRST",
INIT_FILE => "NONE",
SIM_COLLISION_CHECK => "ALL",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE",
EN_ECC_READ => FALSE,
EN_ECC_WRITE => FALSE,
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
SIM_DEVICE => "VIRTEX6",
INIT_00 => X"0000000000000000000000000000000000000000000000106880696868494848",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_40 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_41 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_42 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_43 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_44 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_45 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_46 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_47 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_48 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_49 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_50 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_51 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_52 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_53 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_54 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_55 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_56 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_57 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_58 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_59 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_60 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_61 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_62 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_63 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_64 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_65 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_66 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_67 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_68 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_69 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_70 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_71 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_72 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_73 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_74 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_00 => X"00000000000000000000000000000000000000000000000000000000000001B8",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000")
port map( ADDRARDADDR => address_a,
ENARDEN => enable,
CLKARDCLK => clk,
DOADO => data_out_a_h(31 downto 0),
DOPADOP => data_out_a_h(35 downto 32),
DIADI => data_in_a(31 downto 0),
DIPADIP => data_in_a(35 downto 32),
WEA => "0000",
REGCEAREGCE => '0',
RSTRAMARSTRAM => '0',
RSTREGARSTREG => '0',
ADDRBWRADDR => address_b,
ENBWREN => enable_b,
CLKBWRCLK => clk_b,
DOBDO => data_out_b_h(31 downto 0),
DOPBDOP => data_out_b_h(35 downto 32),
DIBDI => data_in_b_h(31 downto 0),
DIPBDIP => data_in_b_h(35 downto 32),
WEBWE => we_b,
REGCEB => '0',
RSTRAMB => '0',
RSTREGB => '0',
CASCADEINA => '0',
CASCADEINB => '0',
INJECTDBITERR => '0',
INJECTSBITERR => '0');
--
end generate v6;
--
--
akv7 : if (C_FAMILY = "7S") generate
--
address_a <= '1' & address(11 downto 0) & "111";
instruction <= data_out_a_h(32) & data_out_a_h(7 downto 0) & data_out_a_l(32) & data_out_a_l(7 downto 0);
data_in_a <= "000000000000000000000000000000000000";
jtag_dout <= data_out_b_h(32) & data_out_b_h(7 downto 0) & data_out_b_l(32) & data_out_b_l(7 downto 0);
--
no_loader : if (C_JTAG_LOADER_ENABLE = 0) generate
data_in_b_l <= "000" & data_out_b_l(32) & "000000000000000000000000" & data_out_b_l(7 downto 0);
data_in_b_h <= "000" & data_out_b_h(32) & "000000000000000000000000" & data_out_b_h(7 downto 0);
address_b <= "1111111111111111";
we_b <= "00000000";
enable_b <= '0';
rdl <= '0';
clk_b <= '0';
end generate no_loader;
--
loader : if (C_JTAG_LOADER_ENABLE = 1) generate
data_in_b_h <= "000" & jtag_din(17) & "000000000000000000000000" & jtag_din(16 downto 9);
data_in_b_l <= "000" & jtag_din(8) & "000000000000000000000000" & jtag_din(7 downto 0);
address_b <= '1' & jtag_addr(11 downto 0) & "111";
we_b <= jtag_we & jtag_we & jtag_we & jtag_we & jtag_we & jtag_we & jtag_we & jtag_we;
enable_b <= jtag_en(0);
rdl <= rdl_bus(0);
clk_b <= jtag_clk;
end generate loader;
--
kcpsm6_rom_l: RAMB36E1
generic map ( READ_WIDTH_A => 9,
WRITE_WIDTH_A => 9,
DOA_REG => 0,
INIT_A => X"000000000",
RSTREG_PRIORITY_A => "REGCE",
SRVAL_A => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
READ_WIDTH_B => 9,
WRITE_WIDTH_B => 9,
DOB_REG => 0,
INIT_B => X"000000000",
RSTREG_PRIORITY_B => "REGCE",
SRVAL_B => X"000000000",
WRITE_MODE_B => "WRITE_FIRST",
INIT_FILE => "NONE",
SIM_COLLISION_CHECK => "ALL",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE",
EN_ECC_READ => FALSE,
EN_ECC_WRITE => FALSE,
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
SIM_DEVICE => "7SERIES",
INIT_00 => X"0000000000000000000000000000000000000000000000000210030100020100",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_44 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_47 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_48 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_49 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_4B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4F => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_51 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_52 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_54 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_56 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_57 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_58 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_59 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_60 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_61 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_62 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_63 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_64 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_65 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_66 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_67 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_68 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_69 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6F => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_71 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_72 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_73 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_74 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000012",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
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INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
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port map( ADDRARDADDR => address_a,
ENARDEN => enable,
CLKARDCLK => clk,
DOADO => data_out_a_l(31 downto 0),
DOPADOP => data_out_a_l(35 downto 32),
DIADI => data_in_a(31 downto 0),
DIPADIP => data_in_a(35 downto 32),
WEA => "0000",
REGCEAREGCE => '0',
RSTRAMARSTRAM => '0',
RSTREGARSTREG => '0',
ADDRBWRADDR => address_b,
ENBWREN => enable_b,
CLKBWRCLK => clk_b,
DOBDO => data_out_b_l(31 downto 0),
DOPBDOP => data_out_b_l(35 downto 32),
DIBDI => data_in_b_l(31 downto 0),
DIPBDIP => data_in_b_l(35 downto 32),
WEBWE => we_b,
REGCEB => '0',
RSTRAMB => '0',
RSTREGB => '0',
CASCADEINA => '0',
CASCADEINB => '0',
INJECTDBITERR => '0',
INJECTSBITERR => '0');
--
kcpsm6_rom_h: RAMB36E1
generic map ( READ_WIDTH_A => 9,
WRITE_WIDTH_A => 9,
DOA_REG => 0,
INIT_A => X"000000000",
RSTREG_PRIORITY_A => "REGCE",
SRVAL_A => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
READ_WIDTH_B => 9,
WRITE_WIDTH_B => 9,
DOB_REG => 0,
INIT_B => X"000000000",
RSTREG_PRIORITY_B => "REGCE",
SRVAL_B => X"000000000",
WRITE_MODE_B => "WRITE_FIRST",
INIT_FILE => "NONE",
SIM_COLLISION_CHECK => "ALL",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE",
EN_ECC_READ => FALSE,
EN_ECC_WRITE => FALSE,
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
SIM_DEVICE => "7SERIES",
INIT_00 => X"0000000000000000000000000000000000000000000000106880696868494848",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_41 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_42 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_44 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_45 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_46 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_47 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_48 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_49 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_50 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_51 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_52 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_53 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_54 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_55 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_56 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_57 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_58 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_59 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_60 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_61 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_62 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_63 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_64 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_65 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_66 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_67 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_68 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_69 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_70 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_71 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_72 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_73 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_74 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_00 => X"00000000000000000000000000000000000000000000000000000000000001B8",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000")
port map( ADDRARDADDR => address_a,
ENARDEN => enable,
CLKARDCLK => clk,
DOADO => data_out_a_h(31 downto 0),
DOPADOP => data_out_a_h(35 downto 32),
DIADI => data_in_a(31 downto 0),
DIPADIP => data_in_a(35 downto 32),
WEA => "0000",
REGCEAREGCE => '0',
RSTRAMARSTRAM => '0',
RSTREGARSTREG => '0',
ADDRBWRADDR => address_b,
ENBWREN => enable_b,
CLKBWRCLK => clk_b,
DOBDO => data_out_b_h(31 downto 0),
DOPBDOP => data_out_b_h(35 downto 32),
DIBDI => data_in_b_h(31 downto 0),
DIPBDIP => data_in_b_h(35 downto 32),
WEBWE => we_b,
REGCEB => '0',
RSTRAMB => '0',
RSTREGB => '0',
CASCADEINA => '0',
CASCADEINB => '0',
INJECTDBITERR => '0',
INJECTSBITERR => '0');
--
end generate akv7;
--
end generate ram_4k_generate;
--
--
--
--
-- JTAG Loader
--
instantiate_loader : if (C_JTAG_LOADER_ENABLE = 1) generate
--
jtag_loader_6_inst : jtag_loader_6
generic map( C_FAMILY => C_FAMILY,
C_NUM_PICOBLAZE => 1,
C_JTAG_LOADER_ENABLE => C_JTAG_LOADER_ENABLE,
C_BRAM_MAX_ADDR_WIDTH => BRAM_ADDRESS_WIDTH,
C_ADDR_WIDTH_0 => BRAM_ADDRESS_WIDTH)
port map( picoblaze_reset => rdl_bus,
jtag_en => jtag_en,
jtag_din => jtag_din,
jtag_addr => jtag_addr(BRAM_ADDRESS_WIDTH-1 downto 0),
jtag_clk => jtag_clk,
jtag_we => jtag_we,
jtag_dout_0 => jtag_dout,
jtag_dout_1 => jtag_dout, -- ports 1-7 are not used
jtag_dout_2 => jtag_dout, -- in a 1 device debug
jtag_dout_3 => jtag_dout, -- session. However, Synplify
jtag_dout_4 => jtag_dout, -- etc require all ports to
jtag_dout_5 => jtag_dout, -- be connected
jtag_dout_6 => jtag_dout,
jtag_dout_7 => jtag_dout);
--
end generate instantiate_loader;
--
end low_level_definition;
--
--
-------------------------------------------------------------------------------------------
--
-- JTAG Loader
--
-------------------------------------------------------------------------------------------
--
--
-- JTAG Loader 6 - Version 6.00
-- Kris Chaplin 4 February 2010
-- Ken Chapman 15 August 2011 - Revised coding style
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
--
library unisim;
use unisim.vcomponents.all;
--
entity jtag_loader_6 is
generic( C_JTAG_LOADER_ENABLE : integer := 1;
C_FAMILY : string := "V6";
C_NUM_PICOBLAZE : integer := 1;
C_BRAM_MAX_ADDR_WIDTH : integer := 10;
C_PICOBLAZE_INSTRUCTION_DATA_WIDTH : integer := 18;
C_JTAG_CHAIN : integer := 2;
C_ADDR_WIDTH_0 : integer := 10;
C_ADDR_WIDTH_1 : integer := 10;
C_ADDR_WIDTH_2 : integer := 10;
C_ADDR_WIDTH_3 : integer := 10;
C_ADDR_WIDTH_4 : integer := 10;
C_ADDR_WIDTH_5 : integer := 10;
C_ADDR_WIDTH_6 : integer := 10;
C_ADDR_WIDTH_7 : integer := 10);
port( picoblaze_reset : out std_logic_vector(C_NUM_PICOBLAZE-1 downto 0);
jtag_en : out std_logic_vector(C_NUM_PICOBLAZE-1 downto 0) := (others => '0');
jtag_din : out std_logic_vector(C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-1 downto 0) := (others => '0');
jtag_addr : out std_logic_vector(C_BRAM_MAX_ADDR_WIDTH-1 downto 0) := (others => '0');
jtag_clk : out std_logic := '0';
jtag_we : out std_logic := '0';
jtag_dout_0 : in std_logic_vector(C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-1 downto 0);
jtag_dout_1 : in std_logic_vector(C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-1 downto 0);
jtag_dout_2 : in std_logic_vector(C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-1 downto 0);
jtag_dout_3 : in std_logic_vector(C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-1 downto 0);
jtag_dout_4 : in std_logic_vector(C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-1 downto 0);
jtag_dout_5 : in std_logic_vector(C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-1 downto 0);
jtag_dout_6 : in std_logic_vector(C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-1 downto 0);
jtag_dout_7 : in std_logic_vector(C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-1 downto 0));
end jtag_loader_6;
--
architecture Behavioral of jtag_loader_6 is
--
signal num_picoblaze : std_logic_vector(2 downto 0);
signal picoblaze_instruction_data_width : std_logic_vector(4 downto 0);
--
signal drck : std_logic;
signal shift_clk : std_logic;
signal shift_din : std_logic;
signal shift_dout : std_logic;
signal shift : std_logic;
signal capture : std_logic;
--
signal control_reg_ce : std_logic;
signal bram_ce : std_logic_vector(C_NUM_PICOBLAZE-1 downto 0);
signal bus_zero : std_logic_vector(C_NUM_PICOBLAZE-1 downto 0) := (others => '0');
signal jtag_en_int : std_logic_vector(C_NUM_PICOBLAZE-1 downto 0);
signal jtag_en_expanded : std_logic_vector(7 downto 0) := (others => '0');
signal jtag_addr_int : std_logic_vector(C_BRAM_MAX_ADDR_WIDTH-1 downto 0);
signal jtag_din_int : std_logic_vector(C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-1 downto 0);
signal control_din : std_logic_vector(C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-1 downto 0):= (others => '0');
signal control_dout : std_logic_vector(C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-1 downto 0):= (others => '0');
signal control_dout_int : std_logic_vector(7 downto 0):= (others => '0');
signal bram_dout_int : std_logic_vector(C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-1 downto 0) := (others => '0');
signal jtag_we_int : std_logic;
signal jtag_clk_int : std_logic;
signal bram_ce_valid : std_logic;
signal din_load : std_logic;
--
signal jtag_dout_0_masked : std_logic_vector(C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-1 downto 0);
signal jtag_dout_1_masked : std_logic_vector(C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-1 downto 0);
signal jtag_dout_2_masked : std_logic_vector(C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-1 downto 0);
signal jtag_dout_3_masked : std_logic_vector(C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-1 downto 0);
signal jtag_dout_4_masked : std_logic_vector(C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-1 downto 0);
signal jtag_dout_5_masked : std_logic_vector(C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-1 downto 0);
signal jtag_dout_6_masked : std_logic_vector(C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-1 downto 0);
signal jtag_dout_7_masked : std_logic_vector(C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-1 downto 0);
signal picoblaze_reset_int : std_logic_vector(C_NUM_PICOBLAZE-1 downto 0) := (others => '0');
--
begin
bus_zero <= (others => '0');
--
jtag_loader_gen: if (C_JTAG_LOADER_ENABLE = 1) generate
--
-- Insert BSCAN primitive for target device architecture.
--
BSCAN_SPARTAN6_gen: if (C_FAMILY="S6") generate
begin
BSCAN_BLOCK_inst : BSCAN_SPARTAN6
generic map ( JTAG_CHAIN => C_JTAG_CHAIN)
port map( CAPTURE => capture,
DRCK => drck,
RESET => open,
RUNTEST => open,
SEL => bram_ce_valid,
SHIFT => shift,
TCK => open,
TDI => shift_din,
TMS => open,
UPDATE => jtag_clk_int,
TDO => shift_dout);
end generate BSCAN_SPARTAN6_gen;
--
BSCAN_VIRTEX6_gen: if (C_FAMILY="V6") generate
begin
BSCAN_BLOCK_inst: BSCAN_VIRTEX6
generic map( JTAG_CHAIN => C_JTAG_CHAIN,
DISABLE_JTAG => FALSE)
port map( CAPTURE => capture,
DRCK => drck,
RESET => open,
RUNTEST => open,
SEL => bram_ce_valid,
SHIFT => shift,
TCK => open,
TDI => shift_din,
TMS => open,
UPDATE => jtag_clk_int,
TDO => shift_dout);
end generate BSCAN_VIRTEX6_gen;
--
BSCAN_7SERIES_gen: if (C_FAMILY="7S") generate
begin
BSCAN_BLOCK_inst: BSCANE2
generic map( JTAG_CHAIN => C_JTAG_CHAIN,
DISABLE_JTAG => "FALSE")
port map( CAPTURE => capture,
DRCK => drck,
RESET => open,
RUNTEST => open,
SEL => bram_ce_valid,
SHIFT => shift,
TCK => open,
TDI => shift_din,
TMS => open,
UPDATE => jtag_clk_int,
TDO => shift_dout);
end generate BSCAN_7SERIES_gen;
--
--
-- Insert clock buffer to ensure reliable shift operations.
--
upload_clock: BUFG
port map( I => drck,
O => shift_clk);
--
--
-- Shift Register
--
--
control_reg_ce_shift: process (shift_clk)
begin
if shift_clk'event and shift_clk = '1' then
if (shift = '1') then
control_reg_ce <= shift_din;
end if;
end if;
end process control_reg_ce_shift;
--
bram_ce_shift: process (shift_clk)
begin
if shift_clk'event and shift_clk='1' then
if (shift = '1') then
if(C_NUM_PICOBLAZE > 1) then
for i in 0 to C_NUM_PICOBLAZE-2 loop
bram_ce(i+1) <= bram_ce(i);
end loop;
end if;
bram_ce(0) <= control_reg_ce;
end if;
end if;
end process bram_ce_shift;
--
bram_we_shift: process (shift_clk)
begin
if shift_clk'event and shift_clk='1' then
if (shift = '1') then
jtag_we_int <= bram_ce(C_NUM_PICOBLAZE-1);
end if;
end if;
end process bram_we_shift;
--
bram_a_shift: process (shift_clk)
begin
if shift_clk'event and shift_clk='1' then
if (shift = '1') then
for i in 0 to C_BRAM_MAX_ADDR_WIDTH-2 loop
jtag_addr_int(i+1) <= jtag_addr_int(i);
end loop;
jtag_addr_int(0) <= jtag_we_int;
end if;
end if;
end process bram_a_shift;
--
bram_d_shift: process (shift_clk)
begin
if shift_clk'event and shift_clk='1' then
if (din_load = '1') then
jtag_din_int <= bram_dout_int;
elsif (shift = '1') then
for i in 0 to C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-2 loop
jtag_din_int(i+1) <= jtag_din_int(i);
end loop;
jtag_din_int(0) <= jtag_addr_int(C_BRAM_MAX_ADDR_WIDTH-1);
end if;
end if;
end process bram_d_shift;
--
shift_dout <= jtag_din_int(C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-1);
--
--
din_load_select:process (bram_ce, din_load, capture, bus_zero, control_reg_ce)
begin
if ( bram_ce = bus_zero ) then
din_load <= capture and control_reg_ce;
else
din_load <= capture;
end if;
end process din_load_select;
--
--
-- Control Registers
--
num_picoblaze <= conv_std_logic_vector(C_NUM_PICOBLAZE-1,3);
picoblaze_instruction_data_width <= conv_std_logic_vector(C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-1,5);
--
control_registers: process(jtag_clk_int)
begin
if (jtag_clk_int'event and jtag_clk_int = '1') then
if (bram_ce_valid = '1') and (jtag_we_int = '0') and (control_reg_ce = '1') then
case (jtag_addr_int(3 downto 0)) is
when "0000" => -- 0 = version - returns (7 downto 4) illustrating number of PB
-- and (3 downto 0) picoblaze instruction data width
control_dout_int <= num_picoblaze & picoblaze_instruction_data_width;
when "0001" => -- 1 = PicoBlaze 0 reset / status
if (C_NUM_PICOBLAZE >= 1) then
control_dout_int <= picoblaze_reset_int(0) & "00" & (conv_std_logic_vector(C_ADDR_WIDTH_0-1,5) );
else
control_dout_int <= (others => '0');
end if;
when "0010" => -- 2 = PicoBlaze 1 reset / status
if (C_NUM_PICOBLAZE >= 2) then
control_dout_int <= picoblaze_reset_int(1) & "00" & (conv_std_logic_vector(C_ADDR_WIDTH_1-1,5) );
else
control_dout_int <= (others => '0');
end if;
when "0011" => -- 3 = PicoBlaze 2 reset / status
if (C_NUM_PICOBLAZE >= 3) then
control_dout_int <= picoblaze_reset_int(2) & "00" & (conv_std_logic_vector(C_ADDR_WIDTH_2-1,5) );
else
control_dout_int <= (others => '0');
end if;
when "0100" => -- 4 = PicoBlaze 3 reset / status
if (C_NUM_PICOBLAZE >= 4) then
control_dout_int <= picoblaze_reset_int(3) & "00" & (conv_std_logic_vector(C_ADDR_WIDTH_3-1,5) );
else
control_dout_int <= (others => '0');
end if;
when "0101" => -- 5 = PicoBlaze 4 reset / status
if (C_NUM_PICOBLAZE >= 5) then
control_dout_int <= picoblaze_reset_int(4) & "00" & (conv_std_logic_vector(C_ADDR_WIDTH_4-1,5) );
else
control_dout_int <= (others => '0');
end if;
when "0110" => -- 6 = PicoBlaze 5 reset / status
if (C_NUM_PICOBLAZE >= 6) then
control_dout_int <= picoblaze_reset_int(5) & "00" & (conv_std_logic_vector(C_ADDR_WIDTH_5-1,5) );
else
control_dout_int <= (others => '0');
end if;
when "0111" => -- 7 = PicoBlaze 6 reset / status
if (C_NUM_PICOBLAZE >= 7) then
control_dout_int <= picoblaze_reset_int(6) & "00" & (conv_std_logic_vector(C_ADDR_WIDTH_6-1,5) );
else
control_dout_int <= (others => '0');
end if;
when "1000" => -- 8 = PicoBlaze 7 reset / status
if (C_NUM_PICOBLAZE >= 8) then
control_dout_int <= picoblaze_reset_int(7) & "00" & (conv_std_logic_vector(C_ADDR_WIDTH_7-1,5) );
else
control_dout_int <= (others => '0');
end if;
when "1111" => control_dout_int <= conv_std_logic_vector(C_BRAM_MAX_ADDR_WIDTH -1,8);
when others => control_dout_int <= (others => '1');
end case;
else
control_dout_int <= (others => '0');
end if;
end if;
end process control_registers;
--
control_dout(C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-1 downto C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-8) <= control_dout_int;
--
pb_reset: process(jtag_clk_int)
begin
if (jtag_clk_int'event and jtag_clk_int = '1') then
if (bram_ce_valid = '1') and (jtag_we_int = '1') and (control_reg_ce = '1') then
picoblaze_reset_int(C_NUM_PICOBLAZE-1 downto 0) <= control_din(C_NUM_PICOBLAZE-1 downto 0);
end if;
end if;
end process pb_reset;
--
--
-- Assignments
--
control_dout (C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-9 downto 0) <= (others => '0') when (C_PICOBLAZE_INSTRUCTION_DATA_WIDTH > 8);
--
-- Qualify the blockram CS signal with bscan select output
jtag_en_int <= bram_ce when bram_ce_valid = '1' else (others => '0');
--
jtag_en_expanded(C_NUM_PICOBLAZE-1 downto 0) <= jtag_en_int;
jtag_en_expanded(7 downto C_NUM_PICOBLAZE) <= (others => '0') when (C_NUM_PICOBLAZE < 8);
--
bram_dout_int <= control_dout or jtag_dout_0_masked or jtag_dout_1_masked or jtag_dout_2_masked or jtag_dout_3_masked or jtag_dout_4_masked or jtag_dout_5_masked or jtag_dout_6_masked or jtag_dout_7_masked;
--
control_din <= jtag_din_int;
--
jtag_dout_0_masked <= jtag_dout_0 when jtag_en_expanded(0) = '1' else (others => '0');
jtag_dout_1_masked <= jtag_dout_1 when jtag_en_expanded(1) = '1' else (others => '0');
jtag_dout_2_masked <= jtag_dout_2 when jtag_en_expanded(2) = '1' else (others => '0');
jtag_dout_3_masked <= jtag_dout_3 when jtag_en_expanded(3) = '1' else (others => '0');
jtag_dout_4_masked <= jtag_dout_4 when jtag_en_expanded(4) = '1' else (others => '0');
jtag_dout_5_masked <= jtag_dout_5 when jtag_en_expanded(5) = '1' else (others => '0');
jtag_dout_6_masked <= jtag_dout_6 when jtag_en_expanded(6) = '1' else (others => '0');
jtag_dout_7_masked <= jtag_dout_7 when jtag_en_expanded(7) = '1' else (others => '0');
--
jtag_en <= jtag_en_int;
jtag_din <= jtag_din_int;
jtag_addr <= jtag_addr_int;
jtag_clk <= jtag_clk_int;
jtag_we <= jtag_we_int;
picoblaze_reset <= picoblaze_reset_int;
--
end generate jtag_loader_gen;
--
end Behavioral;
--
--
------------------------------------------------------------------------------------
--
-- END OF FILE ssg_program.vhd
--
------------------------------------------------------------------------------------
| mit | 06988b6eaf270dbeb444bb60fd7d5f68 | 0.617475 | 6.688225 | false | false | false | false |
natsutan/NPU | fpga_implement/npu8/npu8.cache/ip/a150bf43a2bfa1c8/mul8_16_sim_netlist.vhdl | 1 | 289,653 | -- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (lin64) Build 1733598 Wed Dec 14 22:35:42 MST 2016
-- Date : Sat Jan 21 14:33:05 2017
-- Host : natu-OMEN-by-HP-Laptop running 64-bit Ubuntu 16.04.1 LTS
-- Command : write_vhdl -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
-- decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ mul8_16_sim_netlist.vhdl
-- Design : mul8_16
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xcku035-fbva676-3-e
-- --------------------------------------------------------------------------------
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`protect end_protected
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_mult_gen_v12_0_12 is
port (
CLK : in STD_LOGIC;
A : in STD_LOGIC_VECTOR ( 7 downto 0 );
B : in STD_LOGIC_VECTOR ( 15 downto 0 );
CE : in STD_LOGIC;
SCLR : in STD_LOGIC;
ZERO_DETECT : out STD_LOGIC_VECTOR ( 1 downto 0 );
P : out STD_LOGIC_VECTOR ( 15 downto 0 );
PCASC : out STD_LOGIC_VECTOR ( 47 downto 0 )
);
attribute C_A_TYPE : integer;
attribute C_A_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_mult_gen_v12_0_12 : entity is 1;
attribute C_A_WIDTH : integer;
attribute C_A_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_mult_gen_v12_0_12 : entity is 8;
attribute C_B_TYPE : integer;
attribute C_B_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_mult_gen_v12_0_12 : entity is 1;
attribute C_B_VALUE : string;
attribute C_B_VALUE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_mult_gen_v12_0_12 : entity is "10000001";
attribute C_B_WIDTH : integer;
attribute C_B_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_mult_gen_v12_0_12 : entity is 16;
attribute C_CCM_IMP : integer;
attribute C_CCM_IMP of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_mult_gen_v12_0_12 : entity is 0;
attribute C_CE_OVERRIDES_SCLR : integer;
attribute C_CE_OVERRIDES_SCLR of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_mult_gen_v12_0_12 : entity is 0;
attribute C_HAS_CE : integer;
attribute C_HAS_CE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_mult_gen_v12_0_12 : entity is 0;
attribute C_HAS_SCLR : integer;
attribute C_HAS_SCLR of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_mult_gen_v12_0_12 : entity is 0;
attribute C_HAS_ZERO_DETECT : integer;
attribute C_HAS_ZERO_DETECT of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_mult_gen_v12_0_12 : entity is 0;
attribute C_LATENCY : integer;
attribute C_LATENCY of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_mult_gen_v12_0_12 : entity is 3;
attribute C_MODEL_TYPE : integer;
attribute C_MODEL_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_mult_gen_v12_0_12 : entity is 0;
attribute C_MULT_TYPE : integer;
attribute C_MULT_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_mult_gen_v12_0_12 : entity is 0;
attribute C_OPTIMIZE_GOAL : integer;
attribute C_OPTIMIZE_GOAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_mult_gen_v12_0_12 : entity is 1;
attribute C_OUT_HIGH : integer;
attribute C_OUT_HIGH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_mult_gen_v12_0_12 : entity is 23;
attribute C_OUT_LOW : integer;
attribute C_OUT_LOW of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_mult_gen_v12_0_12 : entity is 8;
attribute C_ROUND_OUTPUT : integer;
attribute C_ROUND_OUTPUT of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_mult_gen_v12_0_12 : entity is 0;
attribute C_ROUND_PT : integer;
attribute C_ROUND_PT of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_mult_gen_v12_0_12 : entity is 0;
attribute C_VERBOSITY : integer;
attribute C_VERBOSITY of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_mult_gen_v12_0_12 : entity is 0;
attribute C_XDEVICEFAMILY : string;
attribute C_XDEVICEFAMILY of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_mult_gen_v12_0_12 : entity is "kintexu";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_mult_gen_v12_0_12 : entity is "yes";
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_mult_gen_v12_0_12;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_mult_gen_v12_0_12 is
signal \<const0>\ : STD_LOGIC;
signal NLW_i_mult_PCASC_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 0 );
signal NLW_i_mult_ZERO_DETECT_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute C_A_TYPE of i_mult : label is 1;
attribute C_A_WIDTH of i_mult : label is 8;
attribute C_B_TYPE of i_mult : label is 1;
attribute C_B_VALUE of i_mult : label is "10000001";
attribute C_B_WIDTH of i_mult : label is 16;
attribute C_CCM_IMP of i_mult : label is 0;
attribute C_CE_OVERRIDES_SCLR of i_mult : label is 0;
attribute C_HAS_CE of i_mult : label is 0;
attribute C_HAS_SCLR of i_mult : label is 0;
attribute C_HAS_ZERO_DETECT of i_mult : label is 0;
attribute C_LATENCY of i_mult : label is 3;
attribute C_MODEL_TYPE of i_mult : label is 0;
attribute C_MULT_TYPE of i_mult : label is 0;
attribute C_OUT_HIGH of i_mult : label is 23;
attribute C_OUT_LOW of i_mult : label is 8;
attribute C_ROUND_OUTPUT of i_mult : label is 0;
attribute C_ROUND_PT of i_mult : label is 0;
attribute C_VERBOSITY of i_mult : label is 0;
attribute C_XDEVICEFAMILY of i_mult : label is "kintexu";
attribute c_optimize_goal of i_mult : label is 1;
attribute downgradeipidentifiedwarnings of i_mult : label is "yes";
begin
PCASC(47) <= \<const0>\;
PCASC(46) <= \<const0>\;
PCASC(45) <= \<const0>\;
PCASC(44) <= \<const0>\;
PCASC(43) <= \<const0>\;
PCASC(42) <= \<const0>\;
PCASC(41) <= \<const0>\;
PCASC(40) <= \<const0>\;
PCASC(39) <= \<const0>\;
PCASC(38) <= \<const0>\;
PCASC(37) <= \<const0>\;
PCASC(36) <= \<const0>\;
PCASC(35) <= \<const0>\;
PCASC(34) <= \<const0>\;
PCASC(33) <= \<const0>\;
PCASC(32) <= \<const0>\;
PCASC(31) <= \<const0>\;
PCASC(30) <= \<const0>\;
PCASC(29) <= \<const0>\;
PCASC(28) <= \<const0>\;
PCASC(27) <= \<const0>\;
PCASC(26) <= \<const0>\;
PCASC(25) <= \<const0>\;
PCASC(24) <= \<const0>\;
PCASC(23) <= \<const0>\;
PCASC(22) <= \<const0>\;
PCASC(21) <= \<const0>\;
PCASC(20) <= \<const0>\;
PCASC(19) <= \<const0>\;
PCASC(18) <= \<const0>\;
PCASC(17) <= \<const0>\;
PCASC(16) <= \<const0>\;
PCASC(15) <= \<const0>\;
PCASC(14) <= \<const0>\;
PCASC(13) <= \<const0>\;
PCASC(12) <= \<const0>\;
PCASC(11) <= \<const0>\;
PCASC(10) <= \<const0>\;
PCASC(9) <= \<const0>\;
PCASC(8) <= \<const0>\;
PCASC(7) <= \<const0>\;
PCASC(6) <= \<const0>\;
PCASC(5) <= \<const0>\;
PCASC(4) <= \<const0>\;
PCASC(3) <= \<const0>\;
PCASC(2) <= \<const0>\;
PCASC(1) <= \<const0>\;
PCASC(0) <= \<const0>\;
ZERO_DETECT(1) <= \<const0>\;
ZERO_DETECT(0) <= \<const0>\;
GND: unisim.vcomponents.GND
port map (
G => \<const0>\
);
i_mult: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_mult_gen_v12_0_12_viv
port map (
A(7 downto 0) => A(7 downto 0),
B(15 downto 0) => B(15 downto 0),
CE => '0',
CLK => CLK,
P(15 downto 0) => P(15 downto 0),
PCASC(47 downto 0) => NLW_i_mult_PCASC_UNCONNECTED(47 downto 0),
SCLR => '0',
ZERO_DETECT(1 downto 0) => NLW_i_mult_ZERO_DETECT_UNCONNECTED(1 downto 0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
port (
CLK : in STD_LOGIC;
A : in STD_LOGIC_VECTOR ( 7 downto 0 );
B : in STD_LOGIC_VECTOR ( 15 downto 0 );
P : out STD_LOGIC_VECTOR ( 15 downto 0 )
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is true;
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "mul8_16,mult_gen_v12_0_12,{}";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "yes";
attribute x_core_info : string;
attribute x_core_info of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "mult_gen_v12_0_12,Vivado 2016.4";
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
signal NLW_U0_PCASC_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 0 );
signal NLW_U0_ZERO_DETECT_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute C_A_TYPE : integer;
attribute C_A_TYPE of U0 : label is 1;
attribute C_A_WIDTH : integer;
attribute C_A_WIDTH of U0 : label is 8;
attribute C_B_TYPE : integer;
attribute C_B_TYPE of U0 : label is 1;
attribute C_B_VALUE : string;
attribute C_B_VALUE of U0 : label is "10000001";
attribute C_B_WIDTH : integer;
attribute C_B_WIDTH of U0 : label is 16;
attribute C_CCM_IMP : integer;
attribute C_CCM_IMP of U0 : label is 0;
attribute C_CE_OVERRIDES_SCLR : integer;
attribute C_CE_OVERRIDES_SCLR of U0 : label is 0;
attribute C_HAS_CE : integer;
attribute C_HAS_CE of U0 : label is 0;
attribute C_HAS_SCLR : integer;
attribute C_HAS_SCLR of U0 : label is 0;
attribute C_HAS_ZERO_DETECT : integer;
attribute C_HAS_ZERO_DETECT of U0 : label is 0;
attribute C_LATENCY : integer;
attribute C_LATENCY of U0 : label is 3;
attribute C_MODEL_TYPE : integer;
attribute C_MODEL_TYPE of U0 : label is 0;
attribute C_MULT_TYPE : integer;
attribute C_MULT_TYPE of U0 : label is 0;
attribute C_OUT_HIGH : integer;
attribute C_OUT_HIGH of U0 : label is 23;
attribute C_OUT_LOW : integer;
attribute C_OUT_LOW of U0 : label is 8;
attribute C_ROUND_OUTPUT : integer;
attribute C_ROUND_OUTPUT of U0 : label is 0;
attribute C_ROUND_PT : integer;
attribute C_ROUND_PT of U0 : label is 0;
attribute C_VERBOSITY : integer;
attribute C_VERBOSITY of U0 : label is 0;
attribute C_XDEVICEFAMILY : string;
attribute C_XDEVICEFAMILY of U0 : label is "kintexu";
attribute c_optimize_goal : integer;
attribute c_optimize_goal of U0 : label is 1;
attribute downgradeipidentifiedwarnings of U0 : label is "yes";
begin
U0: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_mult_gen_v12_0_12
port map (
A(7 downto 0) => A(7 downto 0),
B(15 downto 0) => B(15 downto 0),
CE => '1',
CLK => CLK,
P(15 downto 0) => P(15 downto 0),
PCASC(47 downto 0) => NLW_U0_PCASC_UNCONNECTED(47 downto 0),
SCLR => '0',
ZERO_DETECT(1 downto 0) => NLW_U0_ZERO_DETECT_UNCONNECTED(1 downto 0)
);
end STRUCTURE;
| bsd-3-clause | 47da97038521746b1cb39eb9c0dbb153 | 0.943691 | 1.838763 | false | false | false | false |
astoria-d/super-duper-nes | test/rom_test01/rom_test01.vhd | 1 | 6,258 | library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.conv_integer;
use ieee.std_logic_arith.conv_std_logic_vector;
use ieee.std_logic_unsigned.all;
--entity rom_test01 is
entity rom_test01_de0_cv is
port (
pi_reset_n : in std_logic;
pi_base_clk : in std_logic;
-- pi_sw : in std_logic_vector(9 downto 0);
-- pi_btn_n : in std_logic_vector(3 downto 0);
-- po_led_r : out std_logic_vector(9 downto 0);
-- po_led_g : out std_logic_vector(7 downto 0);
--nes side
pi_phi2 : in std_logic;
pi_prg_ce_n : in std_logic;
pi_prg_r_nw : in std_logic;
pi_prg_addr : in std_logic_vector(14 downto 0);
po_prg_data : out std_logic_vector(7 downto 0);
pi_chr_ce_n : in std_logic;
pi_chr_oe_n : in std_logic;
pi_chr_we_n : in std_logic;
pi_chr_addr : in std_logic_vector(12 downto 0);
po_chr_data : out std_logic_vector(7 downto 0);
--i2c side
pi_i2c_scl : in std_logic;
pio_i2c_sda : inout std_logic;
po_dbg_cnt : out std_logic_vector (63 downto 0)
);
--end rom_test01;
end rom_test01_de0_cv;
--architecture rtl of rom_test01 is
architecture rtl of rom_test01_de0_cv is
component prg_rom port (
pi_base_clk : in std_logic;
pi_ce_n : in std_logic;
pi_oe_n : in std_logic;
pi_addr : in std_logic_vector (14 downto 0);
po_data : out std_logic_vector (7 downto 0)
);
end component;
component chr_rom port (
pi_base_clk : in std_logic;
pi_ce_n : in std_logic;
pi_oe_n : in std_logic;
pi_addr : in std_logic_vector (12 downto 0);
po_data : out std_logic_vector (7 downto 0)
);
end component;
component i2c_slave
port (
pi_rst_n : in std_logic;
pi_base_clk : in std_logic;
---i2c bus lines...
pi_slave_addr : in std_logic_vector (6 downto 0);
pi_i2c_scl : in std_logic;
pio_i2c_sda : inout std_logic;
---i2c bus contoler internal lines...
po_i2c_status : out std_logic_vector (2 downto 0);
po_slave_in_data : out std_logic_vector (7 downto 0);
pi_slave_out_data : in std_logic_vector (7 downto 0)
);
end component;
component i2c_eeprom
generic (abus_size : integer := 16);
port (
pi_rst_n : in std_logic;
pi_base_clk : in std_logic;
pi_bus_xfer : in std_logic;
pi_r_nw : in std_logic;
pi_bus_ack : in std_logic;
po_bus_ack : out std_logic;
pi_data : in std_logic_vector (7 downto 0);
po_data : out std_logic_vector (7 downto 0)
);
end component;
--signal wk_chr_ce_n : std_logic;
--signal wk_phi2_n : std_logic;
signal reg_reset_n : std_logic;
signal reg_chr_addr : std_logic_vector(11 downto 0);
signal reg_dbg_cnt : std_logic_vector (63 downto 0);
--2, 4, 8, 16, 32 divide counter.
signal reg_divide_cnt : std_logic_vector (4 downto 0);
--i2c registers.
signal reg_slave_in_data : std_logic_vector (7 downto 0);
signal reg_slave_out_data : std_logic_vector (7 downto 0);
signal reg_slave_status : std_logic_vector (2 downto 0);
signal reg_slave_addr_ack : std_logic;
begin
-- wk_phi2_n <= not pi_phi2;
divider_p : process (pi_phi2)
use ieee.std_logic_unsigned.all;
begin
if (rising_edge(pi_phi2)) then
reg_divide_cnt <= reg_divide_cnt + 1;
end if;
end process;
-- chr_addr_p : process (pi_base_clk)
-- begin
-- if (rising_edge(pi_base_clk)) then
-- if (pi_chr_ce_n = '0') then
-- reg_chr_addr <= pi_chr_addr(11 downto 0);
-- end if;
-- end if;
-- end process;
--program rom
prom_inst : prg_rom port map (
pi_base_clk,
pi_prg_ce_n,
pi_prg_ce_n,
pi_prg_addr,
po_prg_data
);
--character rom
crom_inst : chr_rom port map (
pi_base_clk,
pi_chr_ce_n,
pi_chr_oe_n,
pi_chr_addr,
po_chr_data
);
i2c_slave_inst : i2c_slave
port map (
pi_reset_n,
pi_base_clk,
conv_std_logic_vector(16#44#, 7),
pi_i2c_scl,
pio_i2c_sda,
reg_slave_status,
reg_slave_in_data,
reg_slave_out_data
);
i2c_eeprom_inst : i2c_eeprom generic map (8)
port map (
pi_reset_n,
pi_base_clk,
reg_slave_status(0),
reg_slave_status(2),
reg_slave_status(1),
reg_slave_addr_ack,
reg_slave_in_data,
reg_slave_out_data
);
reset_p : process (pi_base_clk)
use ieee.std_logic_unsigned.all;
variable cnt1, cnt2 : integer;
begin
if (rising_edge(pi_base_clk)) then
-- case addr is 0x77fc
if (pi_prg_addr = "111111111111100") then
-- case addr is 0x77fd
cnt1 := cnt1 + 1;
elsif (pi_prg_addr = "111111111111101") then
cnt2 := cnt2 + 1;
else
cnt1 := 0;
cnt2 := 0;
end if;
--condition:
--reset vector is fetched.
--cpu address is fixed at the reset vector addr for more than 50 clocks.
--assume that reset happened.
if (cnt1 + cnt2 > 50) then
reg_reset_n <= '0';
else
reg_reset_n <= '1';
end if;
end if;
end process;
po_dbg_cnt <= reg_dbg_cnt;
deb_cnt_p : process (pi_base_clk, pi_reset_n)
use ieee.std_logic_unsigned.all;
begin
if (reg_reset_n = '0') then
reg_dbg_cnt <= (others => '0');
elsif (rising_edge(pi_base_clk)) then
reg_dbg_cnt <= reg_dbg_cnt + 1;
end if;
end process;
end rtl;
| apache-2.0 | b2566b142d748fefa6f6afb38467a00b | 0.50799 | 3.141566 | false | false | false | false |
Feuerwerk/fpgaNES | frmmem.vhd | 1 | 9,037 | -- megafunction wizard: %RAM: 2-PORT%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: altsyncram
-- ============================================================
-- File Name: frmmem.vhd
-- Megafunction Name(s):
-- altsyncram
--
-- Simulation Library Files(s):
-- altera_mf
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 18.0.0 Build 614 04/24/2018 SJ Lite Edition
-- ************************************************************
--Copyright (C) 2018 Intel Corporation. All rights reserved.
--Your use of Intel Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Intel Program License
--Subscription Agreement, the Intel Quartus Prime License Agreement,
--the Intel FPGA IP License Agreement, or other applicable license
--agreement, including, without limitation, that your use is for
--the sole purpose of programming logic devices manufactured by
--Intel and sold by Intel or its authorized distributors. Please
--refer to the applicable agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY altera_mf;
USE altera_mf.altera_mf_components.all;
ENTITY frmmem IS
PORT
(
data : IN STD_LOGIC_VECTOR (8 DOWNTO 0);
rdaddress : IN STD_LOGIC_VECTOR (15 DOWNTO 0);
rdclock : IN STD_LOGIC ;
rdclocken : IN STD_LOGIC := '1';
wraddress : IN STD_LOGIC_VECTOR (15 DOWNTO 0);
wrclock : IN STD_LOGIC := '1';
wrclocken : IN STD_LOGIC := '1';
wren : IN STD_LOGIC := '0';
q : OUT STD_LOGIC_VECTOR (8 DOWNTO 0)
);
END frmmem;
ARCHITECTURE SYN OF frmmem IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (8 DOWNTO 0);
BEGIN
q <= sub_wire0(8 DOWNTO 0);
altsyncram_component : altsyncram
GENERIC MAP (
address_aclr_b => "NONE",
address_reg_b => "CLOCK1",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "BYPASS",
intended_device_family => "Cyclone V",
lpm_type => "altsyncram",
numwords_a => 61440,
numwords_b => 61440,
operation_mode => "DUAL_PORT",
outdata_aclr_b => "NONE",
outdata_reg_b => "UNREGISTERED",
power_up_uninitialized => "FALSE",
widthad_a => 16,
widthad_b => 16,
width_a => 9,
width_b => 9,
width_byteena_a => 1
)
PORT MAP (
address_a => wraddress,
address_b => rdaddress,
clock0 => wrclock,
clock1 => rdclock,
clocken0 => wrclocken,
clocken1 => rdclocken,
data_a => data,
wren_a => wren,
q_b => sub_wire0
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
-- Retrieval info: PRIVATE: ADDRESSSTALL_B NUMERIC "0"
-- Retrieval info: PRIVATE: BYTEENA_ACLR_A NUMERIC "0"
-- Retrieval info: PRIVATE: BYTEENA_ACLR_B NUMERIC "0"
-- Retrieval info: PRIVATE: BYTE_ENABLE_A NUMERIC "0"
-- Retrieval info: PRIVATE: BYTE_ENABLE_B NUMERIC "0"
-- Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "9"
-- Retrieval info: PRIVATE: BlankMemory NUMERIC "1"
-- Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "1"
-- Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_B NUMERIC "1"
-- Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "1"
-- Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_B NUMERIC "1"
-- Retrieval info: PRIVATE: CLRdata NUMERIC "0"
-- Retrieval info: PRIVATE: CLRq NUMERIC "0"
-- Retrieval info: PRIVATE: CLRrdaddress NUMERIC "0"
-- Retrieval info: PRIVATE: CLRrren NUMERIC "0"
-- Retrieval info: PRIVATE: CLRwraddress NUMERIC "0"
-- Retrieval info: PRIVATE: CLRwren NUMERIC "0"
-- Retrieval info: PRIVATE: Clock NUMERIC "1"
-- Retrieval info: PRIVATE: Clock_A NUMERIC "0"
-- Retrieval info: PRIVATE: Clock_B NUMERIC "0"
-- Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
-- Retrieval info: PRIVATE: INDATA_ACLR_B NUMERIC "0"
-- Retrieval info: PRIVATE: INDATA_REG_B NUMERIC "0"
-- Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_B"
-- Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone V"
-- Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
-- Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
-- Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
-- Retrieval info: PRIVATE: MEMSIZE NUMERIC "552960"
-- Retrieval info: PRIVATE: MEM_IN_BITS NUMERIC "0"
-- Retrieval info: PRIVATE: MIFfilename STRING ""
-- Retrieval info: PRIVATE: OPERATION_MODE NUMERIC "2"
-- Retrieval info: PRIVATE: OUTDATA_ACLR_B NUMERIC "0"
-- Retrieval info: PRIVATE: OUTDATA_REG_B NUMERIC "0"
-- Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
-- Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_MIXED_PORTS NUMERIC "2"
-- Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "3"
-- Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_B NUMERIC "3"
-- Retrieval info: PRIVATE: REGdata NUMERIC "1"
-- Retrieval info: PRIVATE: REGq NUMERIC "1"
-- Retrieval info: PRIVATE: REGrdaddress NUMERIC "1"
-- Retrieval info: PRIVATE: REGrren NUMERIC "1"
-- Retrieval info: PRIVATE: REGwraddress NUMERIC "1"
-- Retrieval info: PRIVATE: REGwren NUMERIC "1"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: USE_DIFF_CLKEN NUMERIC "0"
-- Retrieval info: PRIVATE: UseDPRAM NUMERIC "1"
-- Retrieval info: PRIVATE: VarWidth NUMERIC "0"
-- Retrieval info: PRIVATE: WIDTH_READ_A NUMERIC "9"
-- Retrieval info: PRIVATE: WIDTH_READ_B NUMERIC "9"
-- Retrieval info: PRIVATE: WIDTH_WRITE_A NUMERIC "9"
-- Retrieval info: PRIVATE: WIDTH_WRITE_B NUMERIC "9"
-- Retrieval info: PRIVATE: WRADDR_ACLR_B NUMERIC "0"
-- Retrieval info: PRIVATE: WRADDR_REG_B NUMERIC "0"
-- Retrieval info: PRIVATE: WRCTRL_ACLR_B NUMERIC "0"
-- Retrieval info: PRIVATE: enable NUMERIC "1"
-- Retrieval info: PRIVATE: rden NUMERIC "0"
-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
-- Retrieval info: CONSTANT: ADDRESS_ACLR_B STRING "NONE"
-- Retrieval info: CONSTANT: ADDRESS_REG_B STRING "CLOCK1"
-- Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "NORMAL"
-- Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_B STRING "NORMAL"
-- Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_B STRING "BYPASS"
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone V"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
-- Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "61440"
-- Retrieval info: CONSTANT: NUMWORDS_B NUMERIC "61440"
-- Retrieval info: CONSTANT: OPERATION_MODE STRING "DUAL_PORT"
-- Retrieval info: CONSTANT: OUTDATA_ACLR_B STRING "NONE"
-- Retrieval info: CONSTANT: OUTDATA_REG_B STRING "UNREGISTERED"
-- Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE"
-- Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "16"
-- Retrieval info: CONSTANT: WIDTHAD_B NUMERIC "16"
-- Retrieval info: CONSTANT: WIDTH_A NUMERIC "9"
-- Retrieval info: CONSTANT: WIDTH_B NUMERIC "9"
-- Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
-- Retrieval info: USED_PORT: data 0 0 9 0 INPUT NODEFVAL "data[8..0]"
-- Retrieval info: USED_PORT: q 0 0 9 0 OUTPUT NODEFVAL "q[8..0]"
-- Retrieval info: USED_PORT: rdaddress 0 0 16 0 INPUT NODEFVAL "rdaddress[15..0]"
-- Retrieval info: USED_PORT: rdclock 0 0 0 0 INPUT NODEFVAL "rdclock"
-- Retrieval info: USED_PORT: rdclocken 0 0 0 0 INPUT VCC "rdclocken"
-- Retrieval info: USED_PORT: wraddress 0 0 16 0 INPUT NODEFVAL "wraddress[15..0]"
-- Retrieval info: USED_PORT: wrclock 0 0 0 0 INPUT VCC "wrclock"
-- Retrieval info: USED_PORT: wrclocken 0 0 0 0 INPUT VCC "wrclocken"
-- Retrieval info: USED_PORT: wren 0 0 0 0 INPUT GND "wren"
-- Retrieval info: CONNECT: @address_a 0 0 16 0 wraddress 0 0 16 0
-- Retrieval info: CONNECT: @address_b 0 0 16 0 rdaddress 0 0 16 0
-- Retrieval info: CONNECT: @clock0 0 0 0 0 wrclock 0 0 0 0
-- Retrieval info: CONNECT: @clock1 0 0 0 0 rdclock 0 0 0 0
-- Retrieval info: CONNECT: @clocken0 0 0 0 0 wrclocken 0 0 0 0
-- Retrieval info: CONNECT: @clocken1 0 0 0 0 rdclocken 0 0 0 0
-- Retrieval info: CONNECT: @data_a 0 0 9 0 data 0 0 9 0
-- Retrieval info: CONNECT: @wren_a 0 0 0 0 wren 0 0 0 0
-- Retrieval info: CONNECT: q 0 0 9 0 @q_b 0 0 9 0
-- Retrieval info: GEN_FILE: TYPE_NORMAL frmmem.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL frmmem.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL frmmem.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL frmmem.bsf FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL frmmem_inst.vhd FALSE
-- Retrieval info: LIB_FILE: altera_mf
| gpl-3.0 | 452fd4f74526c858780ac0f84a14895d | 0.66947 | 3.467767 | false | false | false | false |
varunnagpaal/Digital-Hardware-Modelling | xilinx-vivado/proj_pointer_basic_hls_ip_integ/proj_pointer_basic_hls_ip_integ.srcs/sources_1/bd/design_1/ip/design_1_rst_ps7_0_50M_0/sim/design_1_rst_ps7_0_50M_0.vhd | 2 | 7,266 | -- (c) Copyright 1995-2019 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:proc_sys_reset:5.0
-- IP Revision: 12
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY proc_sys_reset_v5_0_12;
USE proc_sys_reset_v5_0_12.proc_sys_reset;
ENTITY design_1_rst_ps7_0_50M_0 IS
PORT (
slowest_sync_clk : IN STD_LOGIC;
ext_reset_in : IN STD_LOGIC;
aux_reset_in : IN STD_LOGIC;
mb_debug_sys_rst : IN STD_LOGIC;
dcm_locked : IN STD_LOGIC;
mb_reset : OUT STD_LOGIC;
bus_struct_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
peripheral_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
interconnect_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
peripheral_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0)
);
END design_1_rst_ps7_0_50M_0;
ARCHITECTURE design_1_rst_ps7_0_50M_0_arch OF design_1_rst_ps7_0_50M_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF design_1_rst_ps7_0_50M_0_arch: ARCHITECTURE IS "yes";
COMPONENT proc_sys_reset IS
GENERIC (
C_FAMILY : STRING;
C_EXT_RST_WIDTH : INTEGER;
C_AUX_RST_WIDTH : INTEGER;
C_EXT_RESET_HIGH : STD_LOGIC;
C_AUX_RESET_HIGH : STD_LOGIC;
C_NUM_BUS_RST : INTEGER;
C_NUM_PERP_RST : INTEGER;
C_NUM_INTERCONNECT_ARESETN : INTEGER;
C_NUM_PERP_ARESETN : INTEGER
);
PORT (
slowest_sync_clk : IN STD_LOGIC;
ext_reset_in : IN STD_LOGIC;
aux_reset_in : IN STD_LOGIC;
mb_debug_sys_rst : IN STD_LOGIC;
dcm_locked : IN STD_LOGIC;
mb_reset : OUT STD_LOGIC;
bus_struct_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
peripheral_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
interconnect_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
peripheral_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0)
);
END COMPONENT proc_sys_reset;
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_PARAMETER : STRING;
ATTRIBUTE X_INTERFACE_PARAMETER OF peripheral_aresetn: SIGNAL IS "XIL_INTERFACENAME peripheral_low_rst, POLARITY ACTIVE_LOW, TYPE PERIPHERAL";
ATTRIBUTE X_INTERFACE_INFO OF peripheral_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 peripheral_low_rst RST";
ATTRIBUTE X_INTERFACE_PARAMETER OF interconnect_aresetn: SIGNAL IS "XIL_INTERFACENAME interconnect_low_rst, POLARITY ACTIVE_LOW, TYPE INTERCONNECT";
ATTRIBUTE X_INTERFACE_INFO OF interconnect_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 interconnect_low_rst RST";
ATTRIBUTE X_INTERFACE_PARAMETER OF peripheral_reset: SIGNAL IS "XIL_INTERFACENAME peripheral_high_rst, POLARITY ACTIVE_HIGH, TYPE PERIPHERAL";
ATTRIBUTE X_INTERFACE_INFO OF peripheral_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 peripheral_high_rst RST";
ATTRIBUTE X_INTERFACE_PARAMETER OF bus_struct_reset: SIGNAL IS "XIL_INTERFACENAME bus_struct_reset, POLARITY ACTIVE_HIGH, TYPE INTERCONNECT";
ATTRIBUTE X_INTERFACE_INFO OF bus_struct_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 bus_struct_reset RST";
ATTRIBUTE X_INTERFACE_PARAMETER OF mb_reset: SIGNAL IS "XIL_INTERFACENAME mb_rst, POLARITY ACTIVE_HIGH, TYPE PROCESSOR";
ATTRIBUTE X_INTERFACE_INFO OF mb_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 mb_rst RST";
ATTRIBUTE X_INTERFACE_PARAMETER OF mb_debug_sys_rst: SIGNAL IS "XIL_INTERFACENAME dbg_reset, POLARITY ACTIVE_HIGH";
ATTRIBUTE X_INTERFACE_INFO OF mb_debug_sys_rst: SIGNAL IS "xilinx.com:signal:reset:1.0 dbg_reset RST";
ATTRIBUTE X_INTERFACE_PARAMETER OF aux_reset_in: SIGNAL IS "XIL_INTERFACENAME aux_reset, POLARITY ACTIVE_LOW";
ATTRIBUTE X_INTERFACE_INFO OF aux_reset_in: SIGNAL IS "xilinx.com:signal:reset:1.0 aux_reset RST";
ATTRIBUTE X_INTERFACE_PARAMETER OF ext_reset_in: SIGNAL IS "XIL_INTERFACENAME ext_reset, BOARD.ASSOCIATED_PARAM RESET_BOARD_INTERFACE, POLARITY ACTIVE_HIGH";
ATTRIBUTE X_INTERFACE_INFO OF ext_reset_in: SIGNAL IS "xilinx.com:signal:reset:1.0 ext_reset RST";
ATTRIBUTE X_INTERFACE_PARAMETER OF slowest_sync_clk: SIGNAL IS "XIL_INTERFACENAME clock, ASSOCIATED_RESET mb_reset:bus_struct_reset:interconnect_aresetn:peripheral_aresetn:peripheral_reset, FREQ_HZ 50000000, PHASE 0.000, CLK_DOMAIN design_1_processing_system7_0_2_FCLK_CLK0";
ATTRIBUTE X_INTERFACE_INFO OF slowest_sync_clk: SIGNAL IS "xilinx.com:signal:clock:1.0 clock CLK";
BEGIN
U0 : proc_sys_reset
GENERIC MAP (
C_FAMILY => "zynq",
C_EXT_RST_WIDTH => 4,
C_AUX_RST_WIDTH => 4,
C_EXT_RESET_HIGH => '1',
C_AUX_RESET_HIGH => '0',
C_NUM_BUS_RST => 1,
C_NUM_PERP_RST => 1,
C_NUM_INTERCONNECT_ARESETN => 1,
C_NUM_PERP_ARESETN => 1
)
PORT MAP (
slowest_sync_clk => slowest_sync_clk,
ext_reset_in => ext_reset_in,
aux_reset_in => aux_reset_in,
mb_debug_sys_rst => mb_debug_sys_rst,
dcm_locked => dcm_locked,
mb_reset => mb_reset,
bus_struct_reset => bus_struct_reset,
peripheral_reset => peripheral_reset,
interconnect_aresetn => interconnect_aresetn,
peripheral_aresetn => peripheral_aresetn
);
END design_1_rst_ps7_0_50M_0_arch;
| mit | b3e26a1740a244ada17200305aedf0e5 | 0.724883 | 3.631184 | false | false | false | false |
varunnagpaal/Digital-Hardware-Modelling | xilinx-vivado/project_1/project_1.srcs/sources_1/bd/base_zynq/hdl/base_zynq_wrapper.vhd | 1 | 3,661 | --Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
----------------------------------------------------------------------------------
--Tool Version: Vivado v.2017.4.1 (win64) Build 2117270 Tue Jan 30 15:32:00 MST 2018
--Date : Wed Apr 4 00:27:52 2018
--Host : varun-laptop running 64-bit Service Pack 1 (build 7601)
--Command : generate_target base_zynq_wrapper.bd
--Design : base_zynq_wrapper
--Purpose : IP block netlist
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity base_zynq_wrapper is
port (
DDR_addr : inout STD_LOGIC_VECTOR ( 14 downto 0 );
DDR_ba : inout STD_LOGIC_VECTOR ( 2 downto 0 );
DDR_cas_n : inout STD_LOGIC;
DDR_ck_n : inout STD_LOGIC;
DDR_ck_p : inout STD_LOGIC;
DDR_cke : inout STD_LOGIC;
DDR_cs_n : inout STD_LOGIC;
DDR_dm : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_dq : inout STD_LOGIC_VECTOR ( 31 downto 0 );
DDR_dqs_n : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_dqs_p : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_odt : inout STD_LOGIC;
DDR_ras_n : inout STD_LOGIC;
DDR_reset_n : inout STD_LOGIC;
DDR_we_n : inout STD_LOGIC;
FIXED_IO_ddr_vrn : inout STD_LOGIC;
FIXED_IO_ddr_vrp : inout STD_LOGIC;
FIXED_IO_mio : inout STD_LOGIC_VECTOR ( 53 downto 0 );
FIXED_IO_ps_clk : inout STD_LOGIC;
FIXED_IO_ps_porb : inout STD_LOGIC;
FIXED_IO_ps_srstb : inout STD_LOGIC;
leds_4bits_tri_o : out STD_LOGIC_VECTOR ( 3 downto 0 )
);
end base_zynq_wrapper;
architecture STRUCTURE of base_zynq_wrapper is
component base_zynq is
port (
DDR_cas_n : inout STD_LOGIC;
DDR_cke : inout STD_LOGIC;
DDR_ck_n : inout STD_LOGIC;
DDR_ck_p : inout STD_LOGIC;
DDR_cs_n : inout STD_LOGIC;
DDR_reset_n : inout STD_LOGIC;
DDR_odt : inout STD_LOGIC;
DDR_ras_n : inout STD_LOGIC;
DDR_we_n : inout STD_LOGIC;
DDR_ba : inout STD_LOGIC_VECTOR ( 2 downto 0 );
DDR_addr : inout STD_LOGIC_VECTOR ( 14 downto 0 );
DDR_dm : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_dq : inout STD_LOGIC_VECTOR ( 31 downto 0 );
DDR_dqs_n : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_dqs_p : inout STD_LOGIC_VECTOR ( 3 downto 0 );
FIXED_IO_mio : inout STD_LOGIC_VECTOR ( 53 downto 0 );
FIXED_IO_ddr_vrn : inout STD_LOGIC;
FIXED_IO_ddr_vrp : inout STD_LOGIC;
FIXED_IO_ps_srstb : inout STD_LOGIC;
FIXED_IO_ps_clk : inout STD_LOGIC;
FIXED_IO_ps_porb : inout STD_LOGIC;
leds_4bits_tri_o : out STD_LOGIC_VECTOR ( 3 downto 0 )
);
end component base_zynq;
begin
base_zynq_i: component base_zynq
port map (
DDR_addr(14 downto 0) => DDR_addr(14 downto 0),
DDR_ba(2 downto 0) => DDR_ba(2 downto 0),
DDR_cas_n => DDR_cas_n,
DDR_ck_n => DDR_ck_n,
DDR_ck_p => DDR_ck_p,
DDR_cke => DDR_cke,
DDR_cs_n => DDR_cs_n,
DDR_dm(3 downto 0) => DDR_dm(3 downto 0),
DDR_dq(31 downto 0) => DDR_dq(31 downto 0),
DDR_dqs_n(3 downto 0) => DDR_dqs_n(3 downto 0),
DDR_dqs_p(3 downto 0) => DDR_dqs_p(3 downto 0),
DDR_odt => DDR_odt,
DDR_ras_n => DDR_ras_n,
DDR_reset_n => DDR_reset_n,
DDR_we_n => DDR_we_n,
FIXED_IO_ddr_vrn => FIXED_IO_ddr_vrn,
FIXED_IO_ddr_vrp => FIXED_IO_ddr_vrp,
FIXED_IO_mio(53 downto 0) => FIXED_IO_mio(53 downto 0),
FIXED_IO_ps_clk => FIXED_IO_ps_clk,
FIXED_IO_ps_porb => FIXED_IO_ps_porb,
FIXED_IO_ps_srstb => FIXED_IO_ps_srstb,
leds_4bits_tri_o(3 downto 0) => leds_4bits_tri_o(3 downto 0)
);
end STRUCTURE;
| mit | 323dc1e50542e51989aa977d3ce74dd5 | 0.591368 | 3.035655 | false | false | false | false |
varunnagpaal/Digital-Hardware-Modelling | xilinx-vivado/proj_pointer_basic_hls_ip_integ/proj_pointer_basic_hls_ip_integ.srcs/sources_1/bd/design_1/ip/design_1_processing_system7_0_2/design_1_processing_system7_0_2_sim_netlist.vhdl | 2 | 205,576 | -- Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2018.2 (win64) Build 2258646 Thu Jun 14 20:03:12 MDT 2018
-- Date : Mon Sep 16 05:33:33 2019
-- Host : varun-laptop running 64-bit Service Pack 1 (build 7601)
-- Command : write_vhdl -force -mode funcsim -rename_top design_1_processing_system7_0_2 -prefix
-- design_1_processing_system7_0_2_ design_1_processing_system7_0_2_sim_netlist.vhdl
-- Design : design_1_processing_system7_0_2
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7z010clg400-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_processing_system7_0_2_processing_system7_v5_5_processing_system7 is
port (
CAN0_PHY_TX : out STD_LOGIC;
CAN0_PHY_RX : in STD_LOGIC;
CAN1_PHY_TX : out STD_LOGIC;
CAN1_PHY_RX : in STD_LOGIC;
ENET0_GMII_TX_EN : out STD_LOGIC;
ENET0_GMII_TX_ER : out STD_LOGIC;
ENET0_MDIO_MDC : out STD_LOGIC;
ENET0_MDIO_O : out STD_LOGIC;
ENET0_MDIO_T : out STD_LOGIC;
ENET0_PTP_DELAY_REQ_RX : out STD_LOGIC;
ENET0_PTP_DELAY_REQ_TX : out STD_LOGIC;
ENET0_PTP_PDELAY_REQ_RX : out STD_LOGIC;
ENET0_PTP_PDELAY_REQ_TX : out STD_LOGIC;
ENET0_PTP_PDELAY_RESP_RX : out STD_LOGIC;
ENET0_PTP_PDELAY_RESP_TX : out STD_LOGIC;
ENET0_PTP_SYNC_FRAME_RX : out STD_LOGIC;
ENET0_PTP_SYNC_FRAME_TX : out STD_LOGIC;
ENET0_SOF_RX : out STD_LOGIC;
ENET0_SOF_TX : out STD_LOGIC;
ENET0_GMII_TXD : out STD_LOGIC_VECTOR ( 7 downto 0 );
ENET0_GMII_COL : in STD_LOGIC;
ENET0_GMII_CRS : in STD_LOGIC;
ENET0_GMII_RX_CLK : in STD_LOGIC;
ENET0_GMII_RX_DV : in STD_LOGIC;
ENET0_GMII_RX_ER : in STD_LOGIC;
ENET0_GMII_TX_CLK : in STD_LOGIC;
ENET0_MDIO_I : in STD_LOGIC;
ENET0_EXT_INTIN : in STD_LOGIC;
ENET0_GMII_RXD : in STD_LOGIC_VECTOR ( 7 downto 0 );
ENET1_GMII_TX_EN : out STD_LOGIC;
ENET1_GMII_TX_ER : out STD_LOGIC;
ENET1_MDIO_MDC : out STD_LOGIC;
ENET1_MDIO_O : out STD_LOGIC;
ENET1_MDIO_T : out STD_LOGIC;
ENET1_PTP_DELAY_REQ_RX : out STD_LOGIC;
ENET1_PTP_DELAY_REQ_TX : out STD_LOGIC;
ENET1_PTP_PDELAY_REQ_RX : out STD_LOGIC;
ENET1_PTP_PDELAY_REQ_TX : out STD_LOGIC;
ENET1_PTP_PDELAY_RESP_RX : out STD_LOGIC;
ENET1_PTP_PDELAY_RESP_TX : out STD_LOGIC;
ENET1_PTP_SYNC_FRAME_RX : out STD_LOGIC;
ENET1_PTP_SYNC_FRAME_TX : out STD_LOGIC;
ENET1_SOF_RX : out STD_LOGIC;
ENET1_SOF_TX : out STD_LOGIC;
ENET1_GMII_TXD : out STD_LOGIC_VECTOR ( 7 downto 0 );
ENET1_GMII_COL : in STD_LOGIC;
ENET1_GMII_CRS : in STD_LOGIC;
ENET1_GMII_RX_CLK : in STD_LOGIC;
ENET1_GMII_RX_DV : in STD_LOGIC;
ENET1_GMII_RX_ER : in STD_LOGIC;
ENET1_GMII_TX_CLK : in STD_LOGIC;
ENET1_MDIO_I : in STD_LOGIC;
ENET1_EXT_INTIN : in STD_LOGIC;
ENET1_GMII_RXD : in STD_LOGIC_VECTOR ( 7 downto 0 );
GPIO_I : in STD_LOGIC_VECTOR ( 63 downto 0 );
GPIO_O : out STD_LOGIC_VECTOR ( 63 downto 0 );
GPIO_T : out STD_LOGIC_VECTOR ( 63 downto 0 );
I2C0_SDA_I : in STD_LOGIC;
I2C0_SDA_O : out STD_LOGIC;
I2C0_SDA_T : out STD_LOGIC;
I2C0_SCL_I : in STD_LOGIC;
I2C0_SCL_O : out STD_LOGIC;
I2C0_SCL_T : out STD_LOGIC;
I2C1_SDA_I : in STD_LOGIC;
I2C1_SDA_O : out STD_LOGIC;
I2C1_SDA_T : out STD_LOGIC;
I2C1_SCL_I : in STD_LOGIC;
I2C1_SCL_O : out STD_LOGIC;
I2C1_SCL_T : out STD_LOGIC;
PJTAG_TCK : in STD_LOGIC;
PJTAG_TMS : in STD_LOGIC;
PJTAG_TDI : in STD_LOGIC;
PJTAG_TDO : out STD_LOGIC;
SDIO0_CLK : out STD_LOGIC;
SDIO0_CLK_FB : in STD_LOGIC;
SDIO0_CMD_O : out STD_LOGIC;
SDIO0_CMD_I : in STD_LOGIC;
SDIO0_CMD_T : out STD_LOGIC;
SDIO0_DATA_I : in STD_LOGIC_VECTOR ( 3 downto 0 );
SDIO0_DATA_O : out STD_LOGIC_VECTOR ( 3 downto 0 );
SDIO0_DATA_T : out STD_LOGIC_VECTOR ( 3 downto 0 );
SDIO0_LED : out STD_LOGIC;
SDIO0_CDN : in STD_LOGIC;
SDIO0_WP : in STD_LOGIC;
SDIO0_BUSPOW : out STD_LOGIC;
SDIO0_BUSVOLT : out STD_LOGIC_VECTOR ( 2 downto 0 );
SDIO1_CLK : out STD_LOGIC;
SDIO1_CLK_FB : in STD_LOGIC;
SDIO1_CMD_O : out STD_LOGIC;
SDIO1_CMD_I : in STD_LOGIC;
SDIO1_CMD_T : out STD_LOGIC;
SDIO1_DATA_I : in STD_LOGIC_VECTOR ( 3 downto 0 );
SDIO1_DATA_O : out STD_LOGIC_VECTOR ( 3 downto 0 );
SDIO1_DATA_T : out STD_LOGIC_VECTOR ( 3 downto 0 );
SDIO1_LED : out STD_LOGIC;
SDIO1_CDN : in STD_LOGIC;
SDIO1_WP : in STD_LOGIC;
SDIO1_BUSPOW : out STD_LOGIC;
SDIO1_BUSVOLT : out STD_LOGIC_VECTOR ( 2 downto 0 );
SPI0_SCLK_I : in STD_LOGIC;
SPI0_SCLK_O : out STD_LOGIC;
SPI0_SCLK_T : out STD_LOGIC;
SPI0_MOSI_I : in STD_LOGIC;
SPI0_MOSI_O : out STD_LOGIC;
SPI0_MOSI_T : out STD_LOGIC;
SPI0_MISO_I : in STD_LOGIC;
SPI0_MISO_O : out STD_LOGIC;
SPI0_MISO_T : out STD_LOGIC;
SPI0_SS_I : in STD_LOGIC;
SPI0_SS_O : out STD_LOGIC;
SPI0_SS1_O : out STD_LOGIC;
SPI0_SS2_O : out STD_LOGIC;
SPI0_SS_T : out STD_LOGIC;
SPI1_SCLK_I : in STD_LOGIC;
SPI1_SCLK_O : out STD_LOGIC;
SPI1_SCLK_T : out STD_LOGIC;
SPI1_MOSI_I : in STD_LOGIC;
SPI1_MOSI_O : out STD_LOGIC;
SPI1_MOSI_T : out STD_LOGIC;
SPI1_MISO_I : in STD_LOGIC;
SPI1_MISO_O : out STD_LOGIC;
SPI1_MISO_T : out STD_LOGIC;
SPI1_SS_I : in STD_LOGIC;
SPI1_SS_O : out STD_LOGIC;
SPI1_SS1_O : out STD_LOGIC;
SPI1_SS2_O : out STD_LOGIC;
SPI1_SS_T : out STD_LOGIC;
UART0_DTRN : out STD_LOGIC;
UART0_RTSN : out STD_LOGIC;
UART0_TX : out STD_LOGIC;
UART0_CTSN : in STD_LOGIC;
UART0_DCDN : in STD_LOGIC;
UART0_DSRN : in STD_LOGIC;
UART0_RIN : in STD_LOGIC;
UART0_RX : in STD_LOGIC;
UART1_DTRN : out STD_LOGIC;
UART1_RTSN : out STD_LOGIC;
UART1_TX : out STD_LOGIC;
UART1_CTSN : in STD_LOGIC;
UART1_DCDN : in STD_LOGIC;
UART1_DSRN : in STD_LOGIC;
UART1_RIN : in STD_LOGIC;
UART1_RX : in STD_LOGIC;
TTC0_WAVE0_OUT : out STD_LOGIC;
TTC0_WAVE1_OUT : out STD_LOGIC;
TTC0_WAVE2_OUT : out STD_LOGIC;
TTC0_CLK0_IN : in STD_LOGIC;
TTC0_CLK1_IN : in STD_LOGIC;
TTC0_CLK2_IN : in STD_LOGIC;
TTC1_WAVE0_OUT : out STD_LOGIC;
TTC1_WAVE1_OUT : out STD_LOGIC;
TTC1_WAVE2_OUT : out STD_LOGIC;
TTC1_CLK0_IN : in STD_LOGIC;
TTC1_CLK1_IN : in STD_LOGIC;
TTC1_CLK2_IN : in STD_LOGIC;
WDT_CLK_IN : in STD_LOGIC;
WDT_RST_OUT : out STD_LOGIC;
TRACE_CLK : in STD_LOGIC;
TRACE_CTL : out STD_LOGIC;
TRACE_DATA : out STD_LOGIC_VECTOR ( 1 downto 0 );
TRACE_CLK_OUT : out STD_LOGIC;
USB0_PORT_INDCTL : out STD_LOGIC_VECTOR ( 1 downto 0 );
USB0_VBUS_PWRSELECT : out STD_LOGIC;
USB0_VBUS_PWRFAULT : in STD_LOGIC;
USB1_PORT_INDCTL : out STD_LOGIC_VECTOR ( 1 downto 0 );
USB1_VBUS_PWRSELECT : out STD_LOGIC;
USB1_VBUS_PWRFAULT : in STD_LOGIC;
SRAM_INTIN : in STD_LOGIC;
M_AXI_GP0_ARESETN : out STD_LOGIC;
M_AXI_GP0_ARVALID : out STD_LOGIC;
M_AXI_GP0_AWVALID : out STD_LOGIC;
M_AXI_GP0_BREADY : out STD_LOGIC;
M_AXI_GP0_RREADY : out STD_LOGIC;
M_AXI_GP0_WLAST : out STD_LOGIC;
M_AXI_GP0_WVALID : out STD_LOGIC;
M_AXI_GP0_ARID : out STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_AWID : out STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_WID : out STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_ARBURST : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_ARLOCK : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_ARSIZE : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP0_AWBURST : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_AWLOCK : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_AWSIZE : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP0_ARPROT : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP0_AWPROT : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP0_ARADDR : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_GP0_AWADDR : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_GP0_WDATA : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_GP0_ARCACHE : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_ARLEN : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_ARQOS : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_AWCACHE : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_AWLEN : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_AWQOS : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_WSTRB : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_ACLK : in STD_LOGIC;
M_AXI_GP0_ARREADY : in STD_LOGIC;
M_AXI_GP0_AWREADY : in STD_LOGIC;
M_AXI_GP0_BVALID : in STD_LOGIC;
M_AXI_GP0_RLAST : in STD_LOGIC;
M_AXI_GP0_RVALID : in STD_LOGIC;
M_AXI_GP0_WREADY : in STD_LOGIC;
M_AXI_GP0_BID : in STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_RID : in STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_BRESP : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_RRESP : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_RDATA : in STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_GP1_ARESETN : out STD_LOGIC;
M_AXI_GP1_ARVALID : out STD_LOGIC;
M_AXI_GP1_AWVALID : out STD_LOGIC;
M_AXI_GP1_BREADY : out STD_LOGIC;
M_AXI_GP1_RREADY : out STD_LOGIC;
M_AXI_GP1_WLAST : out STD_LOGIC;
M_AXI_GP1_WVALID : out STD_LOGIC;
M_AXI_GP1_ARID : out STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP1_AWID : out STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP1_WID : out STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP1_ARBURST : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP1_ARLOCK : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP1_ARSIZE : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP1_AWBURST : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP1_AWLOCK : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP1_AWSIZE : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP1_ARPROT : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP1_AWPROT : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP1_ARADDR : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_GP1_AWADDR : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_GP1_WDATA : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_GP1_ARCACHE : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP1_ARLEN : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP1_ARQOS : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP1_AWCACHE : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP1_AWLEN : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP1_AWQOS : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP1_WSTRB : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP1_ACLK : in STD_LOGIC;
M_AXI_GP1_ARREADY : in STD_LOGIC;
M_AXI_GP1_AWREADY : in STD_LOGIC;
M_AXI_GP1_BVALID : in STD_LOGIC;
M_AXI_GP1_RLAST : in STD_LOGIC;
M_AXI_GP1_RVALID : in STD_LOGIC;
M_AXI_GP1_WREADY : in STD_LOGIC;
M_AXI_GP1_BID : in STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP1_RID : in STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP1_BRESP : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP1_RRESP : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP1_RDATA : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_GP0_ARESETN : out STD_LOGIC;
S_AXI_GP0_ARREADY : out STD_LOGIC;
S_AXI_GP0_AWREADY : out STD_LOGIC;
S_AXI_GP0_BVALID : out STD_LOGIC;
S_AXI_GP0_RLAST : out STD_LOGIC;
S_AXI_GP0_RVALID : out STD_LOGIC;
S_AXI_GP0_WREADY : out STD_LOGIC;
S_AXI_GP0_BRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_GP0_RRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_GP0_RDATA : out STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_GP0_BID : out STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_GP0_RID : out STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_GP0_ACLK : in STD_LOGIC;
S_AXI_GP0_ARVALID : in STD_LOGIC;
S_AXI_GP0_AWVALID : in STD_LOGIC;
S_AXI_GP0_BREADY : in STD_LOGIC;
S_AXI_GP0_RREADY : in STD_LOGIC;
S_AXI_GP0_WLAST : in STD_LOGIC;
S_AXI_GP0_WVALID : in STD_LOGIC;
S_AXI_GP0_ARBURST : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_GP0_ARLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_GP0_ARSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_GP0_AWBURST : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_GP0_AWLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_GP0_AWSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_GP0_ARPROT : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_GP0_AWPROT : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_GP0_ARADDR : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_GP0_AWADDR : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_GP0_WDATA : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_GP0_ARCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_GP0_ARLEN : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_GP0_ARQOS : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_GP0_AWCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_GP0_AWLEN : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_GP0_AWQOS : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_GP0_WSTRB : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_GP0_ARID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_GP0_AWID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_GP0_WID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_GP1_ARESETN : out STD_LOGIC;
S_AXI_GP1_ARREADY : out STD_LOGIC;
S_AXI_GP1_AWREADY : out STD_LOGIC;
S_AXI_GP1_BVALID : out STD_LOGIC;
S_AXI_GP1_RLAST : out STD_LOGIC;
S_AXI_GP1_RVALID : out STD_LOGIC;
S_AXI_GP1_WREADY : out STD_LOGIC;
S_AXI_GP1_BRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_GP1_RRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_GP1_RDATA : out STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_GP1_BID : out STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_GP1_RID : out STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_GP1_ACLK : in STD_LOGIC;
S_AXI_GP1_ARVALID : in STD_LOGIC;
S_AXI_GP1_AWVALID : in STD_LOGIC;
S_AXI_GP1_BREADY : in STD_LOGIC;
S_AXI_GP1_RREADY : in STD_LOGIC;
S_AXI_GP1_WLAST : in STD_LOGIC;
S_AXI_GP1_WVALID : in STD_LOGIC;
S_AXI_GP1_ARBURST : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_GP1_ARLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_GP1_ARSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_GP1_AWBURST : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_GP1_AWLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_GP1_AWSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_GP1_ARPROT : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_GP1_AWPROT : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_GP1_ARADDR : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_GP1_AWADDR : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_GP1_WDATA : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_GP1_ARCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_GP1_ARLEN : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_GP1_ARQOS : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_GP1_AWCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_GP1_AWLEN : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_GP1_AWQOS : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_GP1_WSTRB : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_GP1_ARID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_GP1_AWID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_GP1_WID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_ACP_ARESETN : out STD_LOGIC;
S_AXI_ACP_ARREADY : out STD_LOGIC;
S_AXI_ACP_AWREADY : out STD_LOGIC;
S_AXI_ACP_BVALID : out STD_LOGIC;
S_AXI_ACP_RLAST : out STD_LOGIC;
S_AXI_ACP_RVALID : out STD_LOGIC;
S_AXI_ACP_WREADY : out STD_LOGIC;
S_AXI_ACP_BRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_ACP_RRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_ACP_BID : out STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_ACP_RID : out STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_ACP_RDATA : out STD_LOGIC_VECTOR ( 63 downto 0 );
S_AXI_ACP_ACLK : in STD_LOGIC;
S_AXI_ACP_ARVALID : in STD_LOGIC;
S_AXI_ACP_AWVALID : in STD_LOGIC;
S_AXI_ACP_BREADY : in STD_LOGIC;
S_AXI_ACP_RREADY : in STD_LOGIC;
S_AXI_ACP_WLAST : in STD_LOGIC;
S_AXI_ACP_WVALID : in STD_LOGIC;
S_AXI_ACP_ARID : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_ACP_ARPROT : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_ACP_AWID : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_ACP_AWPROT : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_ACP_WID : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_ACP_ARADDR : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_ACP_AWADDR : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_ACP_ARCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_ACP_ARLEN : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_ACP_ARQOS : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_ACP_AWCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_ACP_AWLEN : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_ACP_AWQOS : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_ACP_ARBURST : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_ACP_ARLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_ACP_ARSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_ACP_AWBURST : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_ACP_AWLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_ACP_AWSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_ACP_ARUSER : in STD_LOGIC_VECTOR ( 4 downto 0 );
S_AXI_ACP_AWUSER : in STD_LOGIC_VECTOR ( 4 downto 0 );
S_AXI_ACP_WDATA : in STD_LOGIC_VECTOR ( 63 downto 0 );
S_AXI_ACP_WSTRB : in STD_LOGIC_VECTOR ( 7 downto 0 );
S_AXI_HP0_ARESETN : out STD_LOGIC;
S_AXI_HP0_ARREADY : out STD_LOGIC;
S_AXI_HP0_AWREADY : out STD_LOGIC;
S_AXI_HP0_BVALID : out STD_LOGIC;
S_AXI_HP0_RLAST : out STD_LOGIC;
S_AXI_HP0_RVALID : out STD_LOGIC;
S_AXI_HP0_WREADY : out STD_LOGIC;
S_AXI_HP0_BRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP0_RRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP0_BID : out STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP0_RID : out STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP0_RDATA : out STD_LOGIC_VECTOR ( 63 downto 0 );
S_AXI_HP0_RCOUNT : out STD_LOGIC_VECTOR ( 7 downto 0 );
S_AXI_HP0_WCOUNT : out STD_LOGIC_VECTOR ( 7 downto 0 );
S_AXI_HP0_RACOUNT : out STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP0_WACOUNT : out STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP0_ACLK : in STD_LOGIC;
S_AXI_HP0_ARVALID : in STD_LOGIC;
S_AXI_HP0_AWVALID : in STD_LOGIC;
S_AXI_HP0_BREADY : in STD_LOGIC;
S_AXI_HP0_RDISSUECAP1_EN : in STD_LOGIC;
S_AXI_HP0_RREADY : in STD_LOGIC;
S_AXI_HP0_WLAST : in STD_LOGIC;
S_AXI_HP0_WRISSUECAP1_EN : in STD_LOGIC;
S_AXI_HP0_WVALID : in STD_LOGIC;
S_AXI_HP0_ARBURST : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP0_ARLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP0_ARSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP0_AWBURST : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP0_AWLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP0_AWSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP0_ARPROT : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP0_AWPROT : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP0_ARADDR : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_HP0_AWADDR : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_HP0_ARCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP0_ARLEN : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP0_ARQOS : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP0_AWCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP0_AWLEN : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP0_AWQOS : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP0_ARID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP0_AWID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP0_WID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP0_WDATA : in STD_LOGIC_VECTOR ( 63 downto 0 );
S_AXI_HP0_WSTRB : in STD_LOGIC_VECTOR ( 7 downto 0 );
S_AXI_HP1_ARESETN : out STD_LOGIC;
S_AXI_HP1_ARREADY : out STD_LOGIC;
S_AXI_HP1_AWREADY : out STD_LOGIC;
S_AXI_HP1_BVALID : out STD_LOGIC;
S_AXI_HP1_RLAST : out STD_LOGIC;
S_AXI_HP1_RVALID : out STD_LOGIC;
S_AXI_HP1_WREADY : out STD_LOGIC;
S_AXI_HP1_BRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP1_RRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP1_BID : out STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP1_RID : out STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP1_RDATA : out STD_LOGIC_VECTOR ( 63 downto 0 );
S_AXI_HP1_RCOUNT : out STD_LOGIC_VECTOR ( 7 downto 0 );
S_AXI_HP1_WCOUNT : out STD_LOGIC_VECTOR ( 7 downto 0 );
S_AXI_HP1_RACOUNT : out STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP1_WACOUNT : out STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP1_ACLK : in STD_LOGIC;
S_AXI_HP1_ARVALID : in STD_LOGIC;
S_AXI_HP1_AWVALID : in STD_LOGIC;
S_AXI_HP1_BREADY : in STD_LOGIC;
S_AXI_HP1_RDISSUECAP1_EN : in STD_LOGIC;
S_AXI_HP1_RREADY : in STD_LOGIC;
S_AXI_HP1_WLAST : in STD_LOGIC;
S_AXI_HP1_WRISSUECAP1_EN : in STD_LOGIC;
S_AXI_HP1_WVALID : in STD_LOGIC;
S_AXI_HP1_ARBURST : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP1_ARLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP1_ARSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP1_AWBURST : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP1_AWLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP1_AWSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP1_ARPROT : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP1_AWPROT : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP1_ARADDR : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_HP1_AWADDR : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_HP1_ARCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP1_ARLEN : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP1_ARQOS : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP1_AWCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP1_AWLEN : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP1_AWQOS : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP1_ARID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP1_AWID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP1_WID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP1_WDATA : in STD_LOGIC_VECTOR ( 63 downto 0 );
S_AXI_HP1_WSTRB : in STD_LOGIC_VECTOR ( 7 downto 0 );
S_AXI_HP2_ARESETN : out STD_LOGIC;
S_AXI_HP2_ARREADY : out STD_LOGIC;
S_AXI_HP2_AWREADY : out STD_LOGIC;
S_AXI_HP2_BVALID : out STD_LOGIC;
S_AXI_HP2_RLAST : out STD_LOGIC;
S_AXI_HP2_RVALID : out STD_LOGIC;
S_AXI_HP2_WREADY : out STD_LOGIC;
S_AXI_HP2_BRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP2_RRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP2_BID : out STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP2_RID : out STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP2_RDATA : out STD_LOGIC_VECTOR ( 63 downto 0 );
S_AXI_HP2_RCOUNT : out STD_LOGIC_VECTOR ( 7 downto 0 );
S_AXI_HP2_WCOUNT : out STD_LOGIC_VECTOR ( 7 downto 0 );
S_AXI_HP2_RACOUNT : out STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP2_WACOUNT : out STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP2_ACLK : in STD_LOGIC;
S_AXI_HP2_ARVALID : in STD_LOGIC;
S_AXI_HP2_AWVALID : in STD_LOGIC;
S_AXI_HP2_BREADY : in STD_LOGIC;
S_AXI_HP2_RDISSUECAP1_EN : in STD_LOGIC;
S_AXI_HP2_RREADY : in STD_LOGIC;
S_AXI_HP2_WLAST : in STD_LOGIC;
S_AXI_HP2_WRISSUECAP1_EN : in STD_LOGIC;
S_AXI_HP2_WVALID : in STD_LOGIC;
S_AXI_HP2_ARBURST : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP2_ARLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP2_ARSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP2_AWBURST : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP2_AWLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP2_AWSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP2_ARPROT : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP2_AWPROT : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP2_ARADDR : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_HP2_AWADDR : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_HP2_ARCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP2_ARLEN : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP2_ARQOS : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP2_AWCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP2_AWLEN : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP2_AWQOS : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP2_ARID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP2_AWID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP2_WID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP2_WDATA : in STD_LOGIC_VECTOR ( 63 downto 0 );
S_AXI_HP2_WSTRB : in STD_LOGIC_VECTOR ( 7 downto 0 );
S_AXI_HP3_ARESETN : out STD_LOGIC;
S_AXI_HP3_ARREADY : out STD_LOGIC;
S_AXI_HP3_AWREADY : out STD_LOGIC;
S_AXI_HP3_BVALID : out STD_LOGIC;
S_AXI_HP3_RLAST : out STD_LOGIC;
S_AXI_HP3_RVALID : out STD_LOGIC;
S_AXI_HP3_WREADY : out STD_LOGIC;
S_AXI_HP3_BRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP3_RRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP3_BID : out STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP3_RID : out STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP3_RDATA : out STD_LOGIC_VECTOR ( 63 downto 0 );
S_AXI_HP3_RCOUNT : out STD_LOGIC_VECTOR ( 7 downto 0 );
S_AXI_HP3_WCOUNT : out STD_LOGIC_VECTOR ( 7 downto 0 );
S_AXI_HP3_RACOUNT : out STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP3_WACOUNT : out STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP3_ACLK : in STD_LOGIC;
S_AXI_HP3_ARVALID : in STD_LOGIC;
S_AXI_HP3_AWVALID : in STD_LOGIC;
S_AXI_HP3_BREADY : in STD_LOGIC;
S_AXI_HP3_RDISSUECAP1_EN : in STD_LOGIC;
S_AXI_HP3_RREADY : in STD_LOGIC;
S_AXI_HP3_WLAST : in STD_LOGIC;
S_AXI_HP3_WRISSUECAP1_EN : in STD_LOGIC;
S_AXI_HP3_WVALID : in STD_LOGIC;
S_AXI_HP3_ARBURST : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP3_ARLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP3_ARSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP3_AWBURST : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP3_AWLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP3_AWSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP3_ARPROT : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP3_AWPROT : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP3_ARADDR : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_HP3_AWADDR : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_HP3_ARCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP3_ARLEN : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP3_ARQOS : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP3_AWCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP3_AWLEN : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP3_AWQOS : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP3_ARID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP3_AWID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP3_WID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP3_WDATA : in STD_LOGIC_VECTOR ( 63 downto 0 );
S_AXI_HP3_WSTRB : in STD_LOGIC_VECTOR ( 7 downto 0 );
IRQ_P2F_DMAC_ABORT : out STD_LOGIC;
IRQ_P2F_DMAC0 : out STD_LOGIC;
IRQ_P2F_DMAC1 : out STD_LOGIC;
IRQ_P2F_DMAC2 : out STD_LOGIC;
IRQ_P2F_DMAC3 : out STD_LOGIC;
IRQ_P2F_DMAC4 : out STD_LOGIC;
IRQ_P2F_DMAC5 : out STD_LOGIC;
IRQ_P2F_DMAC6 : out STD_LOGIC;
IRQ_P2F_DMAC7 : out STD_LOGIC;
IRQ_P2F_SMC : out STD_LOGIC;
IRQ_P2F_QSPI : out STD_LOGIC;
IRQ_P2F_CTI : out STD_LOGIC;
IRQ_P2F_GPIO : out STD_LOGIC;
IRQ_P2F_USB0 : out STD_LOGIC;
IRQ_P2F_ENET0 : out STD_LOGIC;
IRQ_P2F_ENET_WAKE0 : out STD_LOGIC;
IRQ_P2F_SDIO0 : out STD_LOGIC;
IRQ_P2F_I2C0 : out STD_LOGIC;
IRQ_P2F_SPI0 : out STD_LOGIC;
IRQ_P2F_UART0 : out STD_LOGIC;
IRQ_P2F_CAN0 : out STD_LOGIC;
IRQ_P2F_USB1 : out STD_LOGIC;
IRQ_P2F_ENET1 : out STD_LOGIC;
IRQ_P2F_ENET_WAKE1 : out STD_LOGIC;
IRQ_P2F_SDIO1 : out STD_LOGIC;
IRQ_P2F_I2C1 : out STD_LOGIC;
IRQ_P2F_SPI1 : out STD_LOGIC;
IRQ_P2F_UART1 : out STD_LOGIC;
IRQ_P2F_CAN1 : out STD_LOGIC;
IRQ_F2P : in STD_LOGIC_VECTOR ( 0 to 0 );
Core0_nFIQ : in STD_LOGIC;
Core0_nIRQ : in STD_LOGIC;
Core1_nFIQ : in STD_LOGIC;
Core1_nIRQ : in STD_LOGIC;
DMA0_DATYPE : out STD_LOGIC_VECTOR ( 1 downto 0 );
DMA0_DAVALID : out STD_LOGIC;
DMA0_DRREADY : out STD_LOGIC;
DMA0_RSTN : out STD_LOGIC;
DMA1_DATYPE : out STD_LOGIC_VECTOR ( 1 downto 0 );
DMA1_DAVALID : out STD_LOGIC;
DMA1_DRREADY : out STD_LOGIC;
DMA1_RSTN : out STD_LOGIC;
DMA2_DATYPE : out STD_LOGIC_VECTOR ( 1 downto 0 );
DMA2_DAVALID : out STD_LOGIC;
DMA2_DRREADY : out STD_LOGIC;
DMA2_RSTN : out STD_LOGIC;
DMA3_DATYPE : out STD_LOGIC_VECTOR ( 1 downto 0 );
DMA3_DAVALID : out STD_LOGIC;
DMA3_DRREADY : out STD_LOGIC;
DMA3_RSTN : out STD_LOGIC;
DMA0_ACLK : in STD_LOGIC;
DMA0_DAREADY : in STD_LOGIC;
DMA0_DRLAST : in STD_LOGIC;
DMA0_DRVALID : in STD_LOGIC;
DMA1_ACLK : in STD_LOGIC;
DMA1_DAREADY : in STD_LOGIC;
DMA1_DRLAST : in STD_LOGIC;
DMA1_DRVALID : in STD_LOGIC;
DMA2_ACLK : in STD_LOGIC;
DMA2_DAREADY : in STD_LOGIC;
DMA2_DRLAST : in STD_LOGIC;
DMA2_DRVALID : in STD_LOGIC;
DMA3_ACLK : in STD_LOGIC;
DMA3_DAREADY : in STD_LOGIC;
DMA3_DRLAST : in STD_LOGIC;
DMA3_DRVALID : in STD_LOGIC;
DMA0_DRTYPE : in STD_LOGIC_VECTOR ( 1 downto 0 );
DMA1_DRTYPE : in STD_LOGIC_VECTOR ( 1 downto 0 );
DMA2_DRTYPE : in STD_LOGIC_VECTOR ( 1 downto 0 );
DMA3_DRTYPE : in STD_LOGIC_VECTOR ( 1 downto 0 );
FCLK_CLK3 : out STD_LOGIC;
FCLK_CLK2 : out STD_LOGIC;
FCLK_CLK1 : out STD_LOGIC;
FCLK_CLK0 : out STD_LOGIC;
FCLK_CLKTRIG3_N : in STD_LOGIC;
FCLK_CLKTRIG2_N : in STD_LOGIC;
FCLK_CLKTRIG1_N : in STD_LOGIC;
FCLK_CLKTRIG0_N : in STD_LOGIC;
FCLK_RESET3_N : out STD_LOGIC;
FCLK_RESET2_N : out STD_LOGIC;
FCLK_RESET1_N : out STD_LOGIC;
FCLK_RESET0_N : out STD_LOGIC;
FTMD_TRACEIN_DATA : in STD_LOGIC_VECTOR ( 31 downto 0 );
FTMD_TRACEIN_VALID : in STD_LOGIC;
FTMD_TRACEIN_CLK : in STD_LOGIC;
FTMD_TRACEIN_ATID : in STD_LOGIC_VECTOR ( 3 downto 0 );
FTMT_F2P_TRIG_0 : in STD_LOGIC;
FTMT_F2P_TRIGACK_0 : out STD_LOGIC;
FTMT_F2P_TRIG_1 : in STD_LOGIC;
FTMT_F2P_TRIGACK_1 : out STD_LOGIC;
FTMT_F2P_TRIG_2 : in STD_LOGIC;
FTMT_F2P_TRIGACK_2 : out STD_LOGIC;
FTMT_F2P_TRIG_3 : in STD_LOGIC;
FTMT_F2P_TRIGACK_3 : out STD_LOGIC;
FTMT_F2P_DEBUG : in STD_LOGIC_VECTOR ( 31 downto 0 );
FTMT_P2F_TRIGACK_0 : in STD_LOGIC;
FTMT_P2F_TRIG_0 : out STD_LOGIC;
FTMT_P2F_TRIGACK_1 : in STD_LOGIC;
FTMT_P2F_TRIG_1 : out STD_LOGIC;
FTMT_P2F_TRIGACK_2 : in STD_LOGIC;
FTMT_P2F_TRIG_2 : out STD_LOGIC;
FTMT_P2F_TRIGACK_3 : in STD_LOGIC;
FTMT_P2F_TRIG_3 : out STD_LOGIC;
FTMT_P2F_DEBUG : out STD_LOGIC_VECTOR ( 31 downto 0 );
FPGA_IDLE_N : in STD_LOGIC;
EVENT_EVENTO : out STD_LOGIC;
EVENT_STANDBYWFE : out STD_LOGIC_VECTOR ( 1 downto 0 );
EVENT_STANDBYWFI : out STD_LOGIC_VECTOR ( 1 downto 0 );
EVENT_EVENTI : in STD_LOGIC;
DDR_ARB : in STD_LOGIC_VECTOR ( 3 downto 0 );
MIO : inout STD_LOGIC_VECTOR ( 53 downto 0 );
DDR_CAS_n : inout STD_LOGIC;
DDR_CKE : inout STD_LOGIC;
DDR_Clk_n : inout STD_LOGIC;
DDR_Clk : inout STD_LOGIC;
DDR_CS_n : inout STD_LOGIC;
DDR_DRSTB : inout STD_LOGIC;
DDR_ODT : inout STD_LOGIC;
DDR_RAS_n : inout STD_LOGIC;
DDR_WEB : inout STD_LOGIC;
DDR_BankAddr : inout STD_LOGIC_VECTOR ( 2 downto 0 );
DDR_Addr : inout STD_LOGIC_VECTOR ( 14 downto 0 );
DDR_VRN : inout STD_LOGIC;
DDR_VRP : inout STD_LOGIC;
DDR_DM : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_DQ : inout STD_LOGIC_VECTOR ( 31 downto 0 );
DDR_DQS_n : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_DQS : inout STD_LOGIC_VECTOR ( 3 downto 0 );
PS_SRSTB : inout STD_LOGIC;
PS_CLK : inout STD_LOGIC;
PS_PORB : inout STD_LOGIC
);
attribute C_DM_WIDTH : integer;
attribute C_DM_WIDTH of design_1_processing_system7_0_2_processing_system7_v5_5_processing_system7 : entity is 4;
attribute C_DQS_WIDTH : integer;
attribute C_DQS_WIDTH of design_1_processing_system7_0_2_processing_system7_v5_5_processing_system7 : entity is 4;
attribute C_DQ_WIDTH : integer;
attribute C_DQ_WIDTH of design_1_processing_system7_0_2_processing_system7_v5_5_processing_system7 : entity is 32;
attribute C_EMIO_GPIO_WIDTH : integer;
attribute C_EMIO_GPIO_WIDTH of design_1_processing_system7_0_2_processing_system7_v5_5_processing_system7 : entity is 64;
attribute C_EN_EMIO_ENET0 : integer;
attribute C_EN_EMIO_ENET0 of design_1_processing_system7_0_2_processing_system7_v5_5_processing_system7 : entity is 0;
attribute C_EN_EMIO_ENET1 : integer;
attribute C_EN_EMIO_ENET1 of design_1_processing_system7_0_2_processing_system7_v5_5_processing_system7 : entity is 0;
attribute C_EN_EMIO_PJTAG : integer;
attribute C_EN_EMIO_PJTAG of design_1_processing_system7_0_2_processing_system7_v5_5_processing_system7 : entity is 0;
attribute C_EN_EMIO_TRACE : integer;
attribute C_EN_EMIO_TRACE of design_1_processing_system7_0_2_processing_system7_v5_5_processing_system7 : entity is 0;
attribute C_FCLK_CLK0_BUF : string;
attribute C_FCLK_CLK0_BUF of design_1_processing_system7_0_2_processing_system7_v5_5_processing_system7 : entity is "TRUE";
attribute C_FCLK_CLK1_BUF : string;
attribute C_FCLK_CLK1_BUF of design_1_processing_system7_0_2_processing_system7_v5_5_processing_system7 : entity is "FALSE";
attribute C_FCLK_CLK2_BUF : string;
attribute C_FCLK_CLK2_BUF of design_1_processing_system7_0_2_processing_system7_v5_5_processing_system7 : entity is "FALSE";
attribute C_FCLK_CLK3_BUF : string;
attribute C_FCLK_CLK3_BUF of design_1_processing_system7_0_2_processing_system7_v5_5_processing_system7 : entity is "FALSE";
attribute C_GP0_EN_MODIFIABLE_TXN : integer;
attribute C_GP0_EN_MODIFIABLE_TXN of design_1_processing_system7_0_2_processing_system7_v5_5_processing_system7 : entity is 1;
attribute C_GP1_EN_MODIFIABLE_TXN : integer;
attribute C_GP1_EN_MODIFIABLE_TXN of design_1_processing_system7_0_2_processing_system7_v5_5_processing_system7 : entity is 1;
attribute C_INCLUDE_ACP_TRANS_CHECK : integer;
attribute C_INCLUDE_ACP_TRANS_CHECK of design_1_processing_system7_0_2_processing_system7_v5_5_processing_system7 : entity is 0;
attribute C_INCLUDE_TRACE_BUFFER : integer;
attribute C_INCLUDE_TRACE_BUFFER of design_1_processing_system7_0_2_processing_system7_v5_5_processing_system7 : entity is 0;
attribute C_IRQ_F2P_MODE : string;
attribute C_IRQ_F2P_MODE of design_1_processing_system7_0_2_processing_system7_v5_5_processing_system7 : entity is "DIRECT";
attribute C_MIO_PRIMITIVE : integer;
attribute C_MIO_PRIMITIVE of design_1_processing_system7_0_2_processing_system7_v5_5_processing_system7 : entity is 54;
attribute C_M_AXI_GP0_ENABLE_STATIC_REMAP : integer;
attribute C_M_AXI_GP0_ENABLE_STATIC_REMAP of design_1_processing_system7_0_2_processing_system7_v5_5_processing_system7 : entity is 0;
attribute C_M_AXI_GP0_ID_WIDTH : integer;
attribute C_M_AXI_GP0_ID_WIDTH of design_1_processing_system7_0_2_processing_system7_v5_5_processing_system7 : entity is 12;
attribute C_M_AXI_GP0_THREAD_ID_WIDTH : integer;
attribute C_M_AXI_GP0_THREAD_ID_WIDTH of design_1_processing_system7_0_2_processing_system7_v5_5_processing_system7 : entity is 12;
attribute C_M_AXI_GP1_ENABLE_STATIC_REMAP : integer;
attribute C_M_AXI_GP1_ENABLE_STATIC_REMAP of design_1_processing_system7_0_2_processing_system7_v5_5_processing_system7 : entity is 0;
attribute C_M_AXI_GP1_ID_WIDTH : integer;
attribute C_M_AXI_GP1_ID_WIDTH of design_1_processing_system7_0_2_processing_system7_v5_5_processing_system7 : entity is 12;
attribute C_M_AXI_GP1_THREAD_ID_WIDTH : integer;
attribute C_M_AXI_GP1_THREAD_ID_WIDTH of design_1_processing_system7_0_2_processing_system7_v5_5_processing_system7 : entity is 12;
attribute C_NUM_F2P_INTR_INPUTS : integer;
attribute C_NUM_F2P_INTR_INPUTS of design_1_processing_system7_0_2_processing_system7_v5_5_processing_system7 : entity is 1;
attribute C_PACKAGE_NAME : string;
attribute C_PACKAGE_NAME of design_1_processing_system7_0_2_processing_system7_v5_5_processing_system7 : entity is "clg400";
attribute C_PS7_SI_REV : string;
attribute C_PS7_SI_REV of design_1_processing_system7_0_2_processing_system7_v5_5_processing_system7 : entity is "PRODUCTION";
attribute C_S_AXI_ACP_ARUSER_VAL : integer;
attribute C_S_AXI_ACP_ARUSER_VAL of design_1_processing_system7_0_2_processing_system7_v5_5_processing_system7 : entity is 31;
attribute C_S_AXI_ACP_AWUSER_VAL : integer;
attribute C_S_AXI_ACP_AWUSER_VAL of design_1_processing_system7_0_2_processing_system7_v5_5_processing_system7 : entity is 31;
attribute C_S_AXI_ACP_ID_WIDTH : integer;
attribute C_S_AXI_ACP_ID_WIDTH of design_1_processing_system7_0_2_processing_system7_v5_5_processing_system7 : entity is 3;
attribute C_S_AXI_GP0_ID_WIDTH : integer;
attribute C_S_AXI_GP0_ID_WIDTH of design_1_processing_system7_0_2_processing_system7_v5_5_processing_system7 : entity is 6;
attribute C_S_AXI_GP1_ID_WIDTH : integer;
attribute C_S_AXI_GP1_ID_WIDTH of design_1_processing_system7_0_2_processing_system7_v5_5_processing_system7 : entity is 6;
attribute C_S_AXI_HP0_DATA_WIDTH : integer;
attribute C_S_AXI_HP0_DATA_WIDTH of design_1_processing_system7_0_2_processing_system7_v5_5_processing_system7 : entity is 64;
attribute C_S_AXI_HP0_ID_WIDTH : integer;
attribute C_S_AXI_HP0_ID_WIDTH of design_1_processing_system7_0_2_processing_system7_v5_5_processing_system7 : entity is 6;
attribute C_S_AXI_HP1_DATA_WIDTH : integer;
attribute C_S_AXI_HP1_DATA_WIDTH of design_1_processing_system7_0_2_processing_system7_v5_5_processing_system7 : entity is 64;
attribute C_S_AXI_HP1_ID_WIDTH : integer;
attribute C_S_AXI_HP1_ID_WIDTH of design_1_processing_system7_0_2_processing_system7_v5_5_processing_system7 : entity is 6;
attribute C_S_AXI_HP2_DATA_WIDTH : integer;
attribute C_S_AXI_HP2_DATA_WIDTH of design_1_processing_system7_0_2_processing_system7_v5_5_processing_system7 : entity is 64;
attribute C_S_AXI_HP2_ID_WIDTH : integer;
attribute C_S_AXI_HP2_ID_WIDTH of design_1_processing_system7_0_2_processing_system7_v5_5_processing_system7 : entity is 6;
attribute C_S_AXI_HP3_DATA_WIDTH : integer;
attribute C_S_AXI_HP3_DATA_WIDTH of design_1_processing_system7_0_2_processing_system7_v5_5_processing_system7 : entity is 64;
attribute C_S_AXI_HP3_ID_WIDTH : integer;
attribute C_S_AXI_HP3_ID_WIDTH of design_1_processing_system7_0_2_processing_system7_v5_5_processing_system7 : entity is 6;
attribute C_TRACE_BUFFER_CLOCK_DELAY : integer;
attribute C_TRACE_BUFFER_CLOCK_DELAY of design_1_processing_system7_0_2_processing_system7_v5_5_processing_system7 : entity is 12;
attribute C_TRACE_BUFFER_FIFO_SIZE : integer;
attribute C_TRACE_BUFFER_FIFO_SIZE of design_1_processing_system7_0_2_processing_system7_v5_5_processing_system7 : entity is 128;
attribute C_TRACE_INTERNAL_WIDTH : integer;
attribute C_TRACE_INTERNAL_WIDTH of design_1_processing_system7_0_2_processing_system7_v5_5_processing_system7 : entity is 2;
attribute C_TRACE_PIPELINE_WIDTH : integer;
attribute C_TRACE_PIPELINE_WIDTH of design_1_processing_system7_0_2_processing_system7_v5_5_processing_system7 : entity is 8;
attribute C_USE_AXI_NONSECURE : integer;
attribute C_USE_AXI_NONSECURE of design_1_processing_system7_0_2_processing_system7_v5_5_processing_system7 : entity is 0;
attribute C_USE_DEFAULT_ACP_USER_VAL : integer;
attribute C_USE_DEFAULT_ACP_USER_VAL of design_1_processing_system7_0_2_processing_system7_v5_5_processing_system7 : entity is 0;
attribute C_USE_M_AXI_GP0 : integer;
attribute C_USE_M_AXI_GP0 of design_1_processing_system7_0_2_processing_system7_v5_5_processing_system7 : entity is 1;
attribute C_USE_M_AXI_GP1 : integer;
attribute C_USE_M_AXI_GP1 of design_1_processing_system7_0_2_processing_system7_v5_5_processing_system7 : entity is 0;
attribute C_USE_S_AXI_ACP : integer;
attribute C_USE_S_AXI_ACP of design_1_processing_system7_0_2_processing_system7_v5_5_processing_system7 : entity is 0;
attribute C_USE_S_AXI_GP0 : integer;
attribute C_USE_S_AXI_GP0 of design_1_processing_system7_0_2_processing_system7_v5_5_processing_system7 : entity is 0;
attribute C_USE_S_AXI_GP1 : integer;
attribute C_USE_S_AXI_GP1 of design_1_processing_system7_0_2_processing_system7_v5_5_processing_system7 : entity is 0;
attribute C_USE_S_AXI_HP0 : integer;
attribute C_USE_S_AXI_HP0 of design_1_processing_system7_0_2_processing_system7_v5_5_processing_system7 : entity is 0;
attribute C_USE_S_AXI_HP1 : integer;
attribute C_USE_S_AXI_HP1 of design_1_processing_system7_0_2_processing_system7_v5_5_processing_system7 : entity is 0;
attribute C_USE_S_AXI_HP2 : integer;
attribute C_USE_S_AXI_HP2 of design_1_processing_system7_0_2_processing_system7_v5_5_processing_system7 : entity is 0;
attribute C_USE_S_AXI_HP3 : integer;
attribute C_USE_S_AXI_HP3 of design_1_processing_system7_0_2_processing_system7_v5_5_processing_system7 : entity is 0;
attribute HW_HANDOFF : string;
attribute HW_HANDOFF of design_1_processing_system7_0_2_processing_system7_v5_5_processing_system7 : entity is "design_1_processing_system7_0_2.hwdef";
attribute POWER : string;
attribute POWER of design_1_processing_system7_0_2_processing_system7_v5_5_processing_system7 : entity is "<PROCESSOR name={system} numA9Cores={2} clockFreq={667} load={0.5} /><MEMORY name={code} memType={DDR3(LowVoltage)} dataWidth={32} clockFreq={533.333333} readRate={0.5} writeRate={0.5} /><IO interface={GPIO_Bank_1} ioStandard={LVCMOS18} bidis={2} ioBank={Vcco_p1} clockFreq={1} usageRate={0.5} /><IO interface={GPIO_Bank_0} ioStandard={LVCMOS33} bidis={9} ioBank={Vcco_p0} clockFreq={1} usageRate={0.5} /><IO interface={UART} ioStandard={LVCMOS18} bidis={2} ioBank={Vcco_p1} clockFreq={100.000000} usageRate={0.5} /><IO interface={SD} ioStandard={LVCMOS18} bidis={7} ioBank={Vcco_p1} clockFreq={50.000000} usageRate={0.5} /><IO interface={USB} ioStandard={LVCMOS18} bidis={12} ioBank={Vcco_p1} clockFreq={60} usageRate={0.5} /><IO interface={GigE} ioStandard={LVCMOS18} bidis={14} ioBank={Vcco_p1} clockFreq={125.000000} usageRate={0.5} /><IO interface={QSPI} ioStandard={LVCMOS33} bidis={7} ioBank={Vcco_p0} clockFreq={200} usageRate={0.5} /><PLL domain={Processor} vco={1333.333} /><PLL domain={Memory} vco={1066.667} /><PLL domain={IO} vco={1000.000} /><AXI interface={M_AXI_GP0} dataWidth={32} clockFreq={50} usageRate={0.5} />/>";
attribute USE_TRACE_DATA_EDGE_DETECTOR : integer;
attribute USE_TRACE_DATA_EDGE_DETECTOR of design_1_processing_system7_0_2_processing_system7_v5_5_processing_system7 : entity is 0;
end design_1_processing_system7_0_2_processing_system7_v5_5_processing_system7;
architecture STRUCTURE of design_1_processing_system7_0_2_processing_system7_v5_5_processing_system7 is
signal \<const0>\ : STD_LOGIC;
signal \<const1>\ : STD_LOGIC;
signal ENET0_MDIO_T_n : STD_LOGIC;
signal ENET1_MDIO_T_n : STD_LOGIC;
signal FCLK_CLK_unbuffered : STD_LOGIC_VECTOR ( 0 to 0 );
signal I2C0_SCL_T_n : STD_LOGIC;
signal I2C0_SDA_T_n : STD_LOGIC;
signal I2C1_SCL_T_n : STD_LOGIC;
signal I2C1_SDA_T_n : STD_LOGIC;
signal \^m_axi_gp0_arcache\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \^m_axi_gp0_arsize\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \^m_axi_gp0_awcache\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \^m_axi_gp0_awsize\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \^m_axi_gp1_arcache\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \^m_axi_gp1_arsize\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \^m_axi_gp1_awcache\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \^m_axi_gp1_awsize\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal SDIO0_CMD_T_n : STD_LOGIC;
signal SDIO0_DATA_T_n : STD_LOGIC_VECTOR ( 3 downto 0 );
signal SDIO1_CMD_T_n : STD_LOGIC;
signal SDIO1_DATA_T_n : STD_LOGIC_VECTOR ( 3 downto 0 );
signal SPI0_MISO_T_n : STD_LOGIC;
signal SPI0_MOSI_T_n : STD_LOGIC;
signal SPI0_SCLK_T_n : STD_LOGIC;
signal SPI0_SS_T_n : STD_LOGIC;
signal SPI1_MISO_T_n : STD_LOGIC;
signal SPI1_MOSI_T_n : STD_LOGIC;
signal SPI1_SCLK_T_n : STD_LOGIC;
signal SPI1_SS_T_n : STD_LOGIC;
signal \TRACE_CTL_PIPE[0]\ : STD_LOGIC;
attribute RTL_KEEP : string;
attribute RTL_KEEP of \TRACE_CTL_PIPE[0]\ : signal is "true";
signal \TRACE_CTL_PIPE[1]\ : STD_LOGIC;
attribute RTL_KEEP of \TRACE_CTL_PIPE[1]\ : signal is "true";
signal \TRACE_CTL_PIPE[2]\ : STD_LOGIC;
attribute RTL_KEEP of \TRACE_CTL_PIPE[2]\ : signal is "true";
signal \TRACE_CTL_PIPE[3]\ : STD_LOGIC;
attribute RTL_KEEP of \TRACE_CTL_PIPE[3]\ : signal is "true";
signal \TRACE_CTL_PIPE[4]\ : STD_LOGIC;
attribute RTL_KEEP of \TRACE_CTL_PIPE[4]\ : signal is "true";
signal \TRACE_CTL_PIPE[5]\ : STD_LOGIC;
attribute RTL_KEEP of \TRACE_CTL_PIPE[5]\ : signal is "true";
signal \TRACE_CTL_PIPE[6]\ : STD_LOGIC;
attribute RTL_KEEP of \TRACE_CTL_PIPE[6]\ : signal is "true";
signal \TRACE_CTL_PIPE[7]\ : STD_LOGIC;
attribute RTL_KEEP of \TRACE_CTL_PIPE[7]\ : signal is "true";
signal \TRACE_DATA_PIPE[0]\ : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute RTL_KEEP of \TRACE_DATA_PIPE[0]\ : signal is "true";
signal \TRACE_DATA_PIPE[1]\ : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute RTL_KEEP of \TRACE_DATA_PIPE[1]\ : signal is "true";
signal \TRACE_DATA_PIPE[2]\ : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute RTL_KEEP of \TRACE_DATA_PIPE[2]\ : signal is "true";
signal \TRACE_DATA_PIPE[3]\ : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute RTL_KEEP of \TRACE_DATA_PIPE[3]\ : signal is "true";
signal \TRACE_DATA_PIPE[4]\ : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute RTL_KEEP of \TRACE_DATA_PIPE[4]\ : signal is "true";
signal \TRACE_DATA_PIPE[5]\ : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute RTL_KEEP of \TRACE_DATA_PIPE[5]\ : signal is "true";
signal \TRACE_DATA_PIPE[6]\ : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute RTL_KEEP of \TRACE_DATA_PIPE[6]\ : signal is "true";
signal \TRACE_DATA_PIPE[7]\ : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute RTL_KEEP of \TRACE_DATA_PIPE[7]\ : signal is "true";
signal buffered_DDR_Addr : STD_LOGIC_VECTOR ( 14 downto 0 );
signal buffered_DDR_BankAddr : STD_LOGIC_VECTOR ( 2 downto 0 );
signal buffered_DDR_CAS_n : STD_LOGIC;
signal buffered_DDR_CKE : STD_LOGIC;
signal buffered_DDR_CS_n : STD_LOGIC;
signal buffered_DDR_Clk : STD_LOGIC;
signal buffered_DDR_Clk_n : STD_LOGIC;
signal buffered_DDR_DM : STD_LOGIC_VECTOR ( 3 downto 0 );
signal buffered_DDR_DQ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal buffered_DDR_DQS : STD_LOGIC_VECTOR ( 3 downto 0 );
signal buffered_DDR_DQS_n : STD_LOGIC_VECTOR ( 3 downto 0 );
signal buffered_DDR_DRSTB : STD_LOGIC;
signal buffered_DDR_ODT : STD_LOGIC;
signal buffered_DDR_RAS_n : STD_LOGIC;
signal buffered_DDR_VRN : STD_LOGIC;
signal buffered_DDR_VRP : STD_LOGIC;
signal buffered_DDR_WEB : STD_LOGIC;
signal buffered_MIO : STD_LOGIC_VECTOR ( 53 downto 0 );
signal buffered_PS_CLK : STD_LOGIC;
signal buffered_PS_PORB : STD_LOGIC;
signal buffered_PS_SRSTB : STD_LOGIC;
signal gpio_out_t_n : STD_LOGIC_VECTOR ( 63 downto 0 );
signal NLW_PS7_i_EMIOENET0GMIITXEN_UNCONNECTED : STD_LOGIC;
signal NLW_PS7_i_EMIOENET0GMIITXER_UNCONNECTED : STD_LOGIC;
signal NLW_PS7_i_EMIOENET1GMIITXEN_UNCONNECTED : STD_LOGIC;
signal NLW_PS7_i_EMIOENET1GMIITXER_UNCONNECTED : STD_LOGIC;
signal NLW_PS7_i_EMIOPJTAGTDO_UNCONNECTED : STD_LOGIC;
signal NLW_PS7_i_EMIOPJTAGTDTN_UNCONNECTED : STD_LOGIC;
signal NLW_PS7_i_EMIOTRACECTL_UNCONNECTED : STD_LOGIC;
signal NLW_PS7_i_EMIOENET0GMIITXD_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_PS7_i_EMIOENET1GMIITXD_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_PS7_i_EMIOTRACEDATA_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_PS7_i_MAXIGP0ARCACHE_UNCONNECTED : STD_LOGIC_VECTOR ( 1 to 1 );
signal NLW_PS7_i_MAXIGP0AWCACHE_UNCONNECTED : STD_LOGIC_VECTOR ( 1 to 1 );
signal NLW_PS7_i_MAXIGP1ARCACHE_UNCONNECTED : STD_LOGIC_VECTOR ( 1 to 1 );
signal NLW_PS7_i_MAXIGP1AWCACHE_UNCONNECTED : STD_LOGIC_VECTOR ( 1 to 1 );
attribute BOX_TYPE : string;
attribute BOX_TYPE of DDR_CAS_n_BIBUF : label is "PRIMITIVE";
attribute BOX_TYPE of DDR_CKE_BIBUF : label is "PRIMITIVE";
attribute BOX_TYPE of DDR_CS_n_BIBUF : label is "PRIMITIVE";
attribute BOX_TYPE of DDR_Clk_BIBUF : label is "PRIMITIVE";
attribute BOX_TYPE of DDR_Clk_n_BIBUF : label is "PRIMITIVE";
attribute BOX_TYPE of DDR_DRSTB_BIBUF : label is "PRIMITIVE";
attribute BOX_TYPE of DDR_ODT_BIBUF : label is "PRIMITIVE";
attribute BOX_TYPE of DDR_RAS_n_BIBUF : label is "PRIMITIVE";
attribute BOX_TYPE of DDR_VRN_BIBUF : label is "PRIMITIVE";
attribute BOX_TYPE of DDR_VRP_BIBUF : label is "PRIMITIVE";
attribute BOX_TYPE of DDR_WEB_BIBUF : label is "PRIMITIVE";
attribute BOX_TYPE of PS7_i : label is "PRIMITIVE";
attribute BOX_TYPE of PS_CLK_BIBUF : label is "PRIMITIVE";
attribute BOX_TYPE of PS_PORB_BIBUF : label is "PRIMITIVE";
attribute BOX_TYPE of PS_SRSTB_BIBUF : label is "PRIMITIVE";
attribute BOX_TYPE of \buffer_fclk_clk_0.FCLK_CLK_0_BUFG\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[0].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[10].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[11].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[12].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[13].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[14].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[15].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[16].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[17].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[18].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[19].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[1].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[20].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[21].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[22].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[23].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[24].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[25].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[26].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[27].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[28].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[29].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[2].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[30].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[31].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[32].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[33].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[34].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[35].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[36].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[37].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[38].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[39].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[3].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[40].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[41].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[42].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[43].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[44].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[45].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[46].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[47].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[48].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[49].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[4].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[50].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[51].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[52].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[53].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[5].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[6].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[7].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[8].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[9].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk14[0].DDR_BankAddr_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk14[1].DDR_BankAddr_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk14[2].DDR_BankAddr_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk15[0].DDR_Addr_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk15[10].DDR_Addr_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk15[11].DDR_Addr_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk15[12].DDR_Addr_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk15[13].DDR_Addr_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk15[14].DDR_Addr_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk15[1].DDR_Addr_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk15[2].DDR_Addr_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk15[3].DDR_Addr_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk15[4].DDR_Addr_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk15[5].DDR_Addr_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk15[6].DDR_Addr_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk15[7].DDR_Addr_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk15[8].DDR_Addr_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk15[9].DDR_Addr_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk16[0].DDR_DM_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk16[1].DDR_DM_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk16[2].DDR_DM_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk16[3].DDR_DM_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[0].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[10].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[11].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[12].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[13].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[14].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[15].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[16].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[17].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[18].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[19].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[1].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[20].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[21].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[22].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[23].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[24].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[25].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[26].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[27].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[28].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[29].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[2].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[30].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[31].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[3].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[4].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[5].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[6].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[7].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[8].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[9].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk18[0].DDR_DQS_n_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk18[1].DDR_DQS_n_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk18[2].DDR_DQS_n_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk18[3].DDR_DQS_n_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk19[0].DDR_DQS_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk19[1].DDR_DQS_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk19[2].DDR_DQS_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk19[3].DDR_DQS_BIBUF\ : label is "PRIMITIVE";
begin
ENET0_GMII_TXD(7) <= \<const0>\;
ENET0_GMII_TXD(6) <= \<const0>\;
ENET0_GMII_TXD(5) <= \<const0>\;
ENET0_GMII_TXD(4) <= \<const0>\;
ENET0_GMII_TXD(3) <= \<const0>\;
ENET0_GMII_TXD(2) <= \<const0>\;
ENET0_GMII_TXD(1) <= \<const0>\;
ENET0_GMII_TXD(0) <= \<const0>\;
ENET0_GMII_TX_EN <= \<const0>\;
ENET0_GMII_TX_ER <= \<const0>\;
ENET1_GMII_TXD(7) <= \<const0>\;
ENET1_GMII_TXD(6) <= \<const0>\;
ENET1_GMII_TXD(5) <= \<const0>\;
ENET1_GMII_TXD(4) <= \<const0>\;
ENET1_GMII_TXD(3) <= \<const0>\;
ENET1_GMII_TXD(2) <= \<const0>\;
ENET1_GMII_TXD(1) <= \<const0>\;
ENET1_GMII_TXD(0) <= \<const0>\;
ENET1_GMII_TX_EN <= \<const0>\;
ENET1_GMII_TX_ER <= \<const0>\;
M_AXI_GP0_ARCACHE(3 downto 2) <= \^m_axi_gp0_arcache\(3 downto 2);
M_AXI_GP0_ARCACHE(1) <= \<const1>\;
M_AXI_GP0_ARCACHE(0) <= \^m_axi_gp0_arcache\(0);
M_AXI_GP0_ARSIZE(2) <= \<const0>\;
M_AXI_GP0_ARSIZE(1 downto 0) <= \^m_axi_gp0_arsize\(1 downto 0);
M_AXI_GP0_AWCACHE(3 downto 2) <= \^m_axi_gp0_awcache\(3 downto 2);
M_AXI_GP0_AWCACHE(1) <= \<const1>\;
M_AXI_GP0_AWCACHE(0) <= \^m_axi_gp0_awcache\(0);
M_AXI_GP0_AWSIZE(2) <= \<const0>\;
M_AXI_GP0_AWSIZE(1 downto 0) <= \^m_axi_gp0_awsize\(1 downto 0);
M_AXI_GP1_ARCACHE(3 downto 2) <= \^m_axi_gp1_arcache\(3 downto 2);
M_AXI_GP1_ARCACHE(1) <= \<const1>\;
M_AXI_GP1_ARCACHE(0) <= \^m_axi_gp1_arcache\(0);
M_AXI_GP1_ARSIZE(2) <= \<const0>\;
M_AXI_GP1_ARSIZE(1 downto 0) <= \^m_axi_gp1_arsize\(1 downto 0);
M_AXI_GP1_AWCACHE(3 downto 2) <= \^m_axi_gp1_awcache\(3 downto 2);
M_AXI_GP1_AWCACHE(1) <= \<const1>\;
M_AXI_GP1_AWCACHE(0) <= \^m_axi_gp1_awcache\(0);
M_AXI_GP1_AWSIZE(2) <= \<const0>\;
M_AXI_GP1_AWSIZE(1 downto 0) <= \^m_axi_gp1_awsize\(1 downto 0);
PJTAG_TDO <= \<const0>\;
TRACE_CLK_OUT <= \<const0>\;
TRACE_CTL <= \TRACE_CTL_PIPE[0]\;
TRACE_DATA(1 downto 0) <= \TRACE_DATA_PIPE[0]\(1 downto 0);
DDR_CAS_n_BIBUF: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_CAS_n,
PAD => DDR_CAS_n
);
DDR_CKE_BIBUF: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_CKE,
PAD => DDR_CKE
);
DDR_CS_n_BIBUF: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_CS_n,
PAD => DDR_CS_n
);
DDR_Clk_BIBUF: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_Clk,
PAD => DDR_Clk
);
DDR_Clk_n_BIBUF: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_Clk_n,
PAD => DDR_Clk_n
);
DDR_DRSTB_BIBUF: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DRSTB,
PAD => DDR_DRSTB
);
DDR_ODT_BIBUF: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_ODT,
PAD => DDR_ODT
);
DDR_RAS_n_BIBUF: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_RAS_n,
PAD => DDR_RAS_n
);
DDR_VRN_BIBUF: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_VRN,
PAD => DDR_VRN
);
DDR_VRP_BIBUF: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_VRP,
PAD => DDR_VRP
);
DDR_WEB_BIBUF: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_WEB,
PAD => DDR_WEB
);
ENET0_MDIO_T_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => ENET0_MDIO_T_n,
O => ENET0_MDIO_T
);
ENET1_MDIO_T_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => ENET1_MDIO_T_n,
O => ENET1_MDIO_T
);
GND: unisim.vcomponents.GND
port map (
G => \<const0>\
);
\GPIO_T[0]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(0),
O => GPIO_T(0)
);
\GPIO_T[10]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(10),
O => GPIO_T(10)
);
\GPIO_T[11]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(11),
O => GPIO_T(11)
);
\GPIO_T[12]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(12),
O => GPIO_T(12)
);
\GPIO_T[13]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(13),
O => GPIO_T(13)
);
\GPIO_T[14]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(14),
O => GPIO_T(14)
);
\GPIO_T[15]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(15),
O => GPIO_T(15)
);
\GPIO_T[16]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(16),
O => GPIO_T(16)
);
\GPIO_T[17]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(17),
O => GPIO_T(17)
);
\GPIO_T[18]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(18),
O => GPIO_T(18)
);
\GPIO_T[19]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(19),
O => GPIO_T(19)
);
\GPIO_T[1]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(1),
O => GPIO_T(1)
);
\GPIO_T[20]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(20),
O => GPIO_T(20)
);
\GPIO_T[21]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(21),
O => GPIO_T(21)
);
\GPIO_T[22]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(22),
O => GPIO_T(22)
);
\GPIO_T[23]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(23),
O => GPIO_T(23)
);
\GPIO_T[24]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(24),
O => GPIO_T(24)
);
\GPIO_T[25]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(25),
O => GPIO_T(25)
);
\GPIO_T[26]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(26),
O => GPIO_T(26)
);
\GPIO_T[27]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(27),
O => GPIO_T(27)
);
\GPIO_T[28]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(28),
O => GPIO_T(28)
);
\GPIO_T[29]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(29),
O => GPIO_T(29)
);
\GPIO_T[2]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(2),
O => GPIO_T(2)
);
\GPIO_T[30]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(30),
O => GPIO_T(30)
);
\GPIO_T[31]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(31),
O => GPIO_T(31)
);
\GPIO_T[32]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(32),
O => GPIO_T(32)
);
\GPIO_T[33]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(33),
O => GPIO_T(33)
);
\GPIO_T[34]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(34),
O => GPIO_T(34)
);
\GPIO_T[35]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(35),
O => GPIO_T(35)
);
\GPIO_T[36]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(36),
O => GPIO_T(36)
);
\GPIO_T[37]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(37),
O => GPIO_T(37)
);
\GPIO_T[38]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(38),
O => GPIO_T(38)
);
\GPIO_T[39]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(39),
O => GPIO_T(39)
);
\GPIO_T[3]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(3),
O => GPIO_T(3)
);
\GPIO_T[40]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(40),
O => GPIO_T(40)
);
\GPIO_T[41]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(41),
O => GPIO_T(41)
);
\GPIO_T[42]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(42),
O => GPIO_T(42)
);
\GPIO_T[43]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(43),
O => GPIO_T(43)
);
\GPIO_T[44]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(44),
O => GPIO_T(44)
);
\GPIO_T[45]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(45),
O => GPIO_T(45)
);
\GPIO_T[46]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(46),
O => GPIO_T(46)
);
\GPIO_T[47]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(47),
O => GPIO_T(47)
);
\GPIO_T[48]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(48),
O => GPIO_T(48)
);
\GPIO_T[49]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(49),
O => GPIO_T(49)
);
\GPIO_T[4]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(4),
O => GPIO_T(4)
);
\GPIO_T[50]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(50),
O => GPIO_T(50)
);
\GPIO_T[51]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(51),
O => GPIO_T(51)
);
\GPIO_T[52]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(52),
O => GPIO_T(52)
);
\GPIO_T[53]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(53),
O => GPIO_T(53)
);
\GPIO_T[54]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(54),
O => GPIO_T(54)
);
\GPIO_T[55]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(55),
O => GPIO_T(55)
);
\GPIO_T[56]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(56),
O => GPIO_T(56)
);
\GPIO_T[57]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(57),
O => GPIO_T(57)
);
\GPIO_T[58]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(58),
O => GPIO_T(58)
);
\GPIO_T[59]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(59),
O => GPIO_T(59)
);
\GPIO_T[5]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(5),
O => GPIO_T(5)
);
\GPIO_T[60]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(60),
O => GPIO_T(60)
);
\GPIO_T[61]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(61),
O => GPIO_T(61)
);
\GPIO_T[62]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(62),
O => GPIO_T(62)
);
\GPIO_T[63]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(63),
O => GPIO_T(63)
);
\GPIO_T[6]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(6),
O => GPIO_T(6)
);
\GPIO_T[7]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(7),
O => GPIO_T(7)
);
\GPIO_T[8]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(8),
O => GPIO_T(8)
);
\GPIO_T[9]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(9),
O => GPIO_T(9)
);
I2C0_SCL_T_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => I2C0_SCL_T_n,
O => I2C0_SCL_T
);
I2C0_SDA_T_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => I2C0_SDA_T_n,
O => I2C0_SDA_T
);
I2C1_SCL_T_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => I2C1_SCL_T_n,
O => I2C1_SCL_T
);
I2C1_SDA_T_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => I2C1_SDA_T_n,
O => I2C1_SDA_T
);
PS7_i: unisim.vcomponents.PS7
port map (
DDRA(14 downto 0) => buffered_DDR_Addr(14 downto 0),
DDRARB(3 downto 0) => DDR_ARB(3 downto 0),
DDRBA(2 downto 0) => buffered_DDR_BankAddr(2 downto 0),
DDRCASB => buffered_DDR_CAS_n,
DDRCKE => buffered_DDR_CKE,
DDRCKN => buffered_DDR_Clk_n,
DDRCKP => buffered_DDR_Clk,
DDRCSB => buffered_DDR_CS_n,
DDRDM(3 downto 0) => buffered_DDR_DM(3 downto 0),
DDRDQ(31 downto 0) => buffered_DDR_DQ(31 downto 0),
DDRDQSN(3 downto 0) => buffered_DDR_DQS_n(3 downto 0),
DDRDQSP(3 downto 0) => buffered_DDR_DQS(3 downto 0),
DDRDRSTB => buffered_DDR_DRSTB,
DDRODT => buffered_DDR_ODT,
DDRRASB => buffered_DDR_RAS_n,
DDRVRN => buffered_DDR_VRN,
DDRVRP => buffered_DDR_VRP,
DDRWEB => buffered_DDR_WEB,
DMA0ACLK => DMA0_ACLK,
DMA0DAREADY => DMA0_DAREADY,
DMA0DATYPE(1 downto 0) => DMA0_DATYPE(1 downto 0),
DMA0DAVALID => DMA0_DAVALID,
DMA0DRLAST => DMA0_DRLAST,
DMA0DRREADY => DMA0_DRREADY,
DMA0DRTYPE(1 downto 0) => DMA0_DRTYPE(1 downto 0),
DMA0DRVALID => DMA0_DRVALID,
DMA0RSTN => DMA0_RSTN,
DMA1ACLK => DMA1_ACLK,
DMA1DAREADY => DMA1_DAREADY,
DMA1DATYPE(1 downto 0) => DMA1_DATYPE(1 downto 0),
DMA1DAVALID => DMA1_DAVALID,
DMA1DRLAST => DMA1_DRLAST,
DMA1DRREADY => DMA1_DRREADY,
DMA1DRTYPE(1 downto 0) => DMA1_DRTYPE(1 downto 0),
DMA1DRVALID => DMA1_DRVALID,
DMA1RSTN => DMA1_RSTN,
DMA2ACLK => DMA2_ACLK,
DMA2DAREADY => DMA2_DAREADY,
DMA2DATYPE(1 downto 0) => DMA2_DATYPE(1 downto 0),
DMA2DAVALID => DMA2_DAVALID,
DMA2DRLAST => DMA2_DRLAST,
DMA2DRREADY => DMA2_DRREADY,
DMA2DRTYPE(1 downto 0) => DMA2_DRTYPE(1 downto 0),
DMA2DRVALID => DMA2_DRVALID,
DMA2RSTN => DMA2_RSTN,
DMA3ACLK => DMA3_ACLK,
DMA3DAREADY => DMA3_DAREADY,
DMA3DATYPE(1 downto 0) => DMA3_DATYPE(1 downto 0),
DMA3DAVALID => DMA3_DAVALID,
DMA3DRLAST => DMA3_DRLAST,
DMA3DRREADY => DMA3_DRREADY,
DMA3DRTYPE(1 downto 0) => DMA3_DRTYPE(1 downto 0),
DMA3DRVALID => DMA3_DRVALID,
DMA3RSTN => DMA3_RSTN,
EMIOCAN0PHYRX => CAN0_PHY_RX,
EMIOCAN0PHYTX => CAN0_PHY_TX,
EMIOCAN1PHYRX => CAN1_PHY_RX,
EMIOCAN1PHYTX => CAN1_PHY_TX,
EMIOENET0EXTINTIN => ENET0_EXT_INTIN,
EMIOENET0GMIICOL => '0',
EMIOENET0GMIICRS => '0',
EMIOENET0GMIIRXCLK => ENET0_GMII_RX_CLK,
EMIOENET0GMIIRXD(7 downto 0) => B"00000000",
EMIOENET0GMIIRXDV => '0',
EMIOENET0GMIIRXER => '0',
EMIOENET0GMIITXCLK => ENET0_GMII_TX_CLK,
EMIOENET0GMIITXD(7 downto 0) => NLW_PS7_i_EMIOENET0GMIITXD_UNCONNECTED(7 downto 0),
EMIOENET0GMIITXEN => NLW_PS7_i_EMIOENET0GMIITXEN_UNCONNECTED,
EMIOENET0GMIITXER => NLW_PS7_i_EMIOENET0GMIITXER_UNCONNECTED,
EMIOENET0MDIOI => ENET0_MDIO_I,
EMIOENET0MDIOMDC => ENET0_MDIO_MDC,
EMIOENET0MDIOO => ENET0_MDIO_O,
EMIOENET0MDIOTN => ENET0_MDIO_T_n,
EMIOENET0PTPDELAYREQRX => ENET0_PTP_DELAY_REQ_RX,
EMIOENET0PTPDELAYREQTX => ENET0_PTP_DELAY_REQ_TX,
EMIOENET0PTPPDELAYREQRX => ENET0_PTP_PDELAY_REQ_RX,
EMIOENET0PTPPDELAYREQTX => ENET0_PTP_PDELAY_REQ_TX,
EMIOENET0PTPPDELAYRESPRX => ENET0_PTP_PDELAY_RESP_RX,
EMIOENET0PTPPDELAYRESPTX => ENET0_PTP_PDELAY_RESP_TX,
EMIOENET0PTPSYNCFRAMERX => ENET0_PTP_SYNC_FRAME_RX,
EMIOENET0PTPSYNCFRAMETX => ENET0_PTP_SYNC_FRAME_TX,
EMIOENET0SOFRX => ENET0_SOF_RX,
EMIOENET0SOFTX => ENET0_SOF_TX,
EMIOENET1EXTINTIN => ENET1_EXT_INTIN,
EMIOENET1GMIICOL => '0',
EMIOENET1GMIICRS => '0',
EMIOENET1GMIIRXCLK => ENET1_GMII_RX_CLK,
EMIOENET1GMIIRXD(7 downto 0) => B"00000000",
EMIOENET1GMIIRXDV => '0',
EMIOENET1GMIIRXER => '0',
EMIOENET1GMIITXCLK => ENET1_GMII_TX_CLK,
EMIOENET1GMIITXD(7 downto 0) => NLW_PS7_i_EMIOENET1GMIITXD_UNCONNECTED(7 downto 0),
EMIOENET1GMIITXEN => NLW_PS7_i_EMIOENET1GMIITXEN_UNCONNECTED,
EMIOENET1GMIITXER => NLW_PS7_i_EMIOENET1GMIITXER_UNCONNECTED,
EMIOENET1MDIOI => ENET1_MDIO_I,
EMIOENET1MDIOMDC => ENET1_MDIO_MDC,
EMIOENET1MDIOO => ENET1_MDIO_O,
EMIOENET1MDIOTN => ENET1_MDIO_T_n,
EMIOENET1PTPDELAYREQRX => ENET1_PTP_DELAY_REQ_RX,
EMIOENET1PTPDELAYREQTX => ENET1_PTP_DELAY_REQ_TX,
EMIOENET1PTPPDELAYREQRX => ENET1_PTP_PDELAY_REQ_RX,
EMIOENET1PTPPDELAYREQTX => ENET1_PTP_PDELAY_REQ_TX,
EMIOENET1PTPPDELAYRESPRX => ENET1_PTP_PDELAY_RESP_RX,
EMIOENET1PTPPDELAYRESPTX => ENET1_PTP_PDELAY_RESP_TX,
EMIOENET1PTPSYNCFRAMERX => ENET1_PTP_SYNC_FRAME_RX,
EMIOENET1PTPSYNCFRAMETX => ENET1_PTP_SYNC_FRAME_TX,
EMIOENET1SOFRX => ENET1_SOF_RX,
EMIOENET1SOFTX => ENET1_SOF_TX,
EMIOGPIOI(63 downto 0) => GPIO_I(63 downto 0),
EMIOGPIOO(63 downto 0) => GPIO_O(63 downto 0),
EMIOGPIOTN(63 downto 0) => gpio_out_t_n(63 downto 0),
EMIOI2C0SCLI => I2C0_SCL_I,
EMIOI2C0SCLO => I2C0_SCL_O,
EMIOI2C0SCLTN => I2C0_SCL_T_n,
EMIOI2C0SDAI => I2C0_SDA_I,
EMIOI2C0SDAO => I2C0_SDA_O,
EMIOI2C0SDATN => I2C0_SDA_T_n,
EMIOI2C1SCLI => I2C1_SCL_I,
EMIOI2C1SCLO => I2C1_SCL_O,
EMIOI2C1SCLTN => I2C1_SCL_T_n,
EMIOI2C1SDAI => I2C1_SDA_I,
EMIOI2C1SDAO => I2C1_SDA_O,
EMIOI2C1SDATN => I2C1_SDA_T_n,
EMIOPJTAGTCK => PJTAG_TCK,
EMIOPJTAGTDI => PJTAG_TDI,
EMIOPJTAGTDO => NLW_PS7_i_EMIOPJTAGTDO_UNCONNECTED,
EMIOPJTAGTDTN => NLW_PS7_i_EMIOPJTAGTDTN_UNCONNECTED,
EMIOPJTAGTMS => PJTAG_TMS,
EMIOSDIO0BUSPOW => SDIO0_BUSPOW,
EMIOSDIO0BUSVOLT(2 downto 0) => SDIO0_BUSVOLT(2 downto 0),
EMIOSDIO0CDN => SDIO0_CDN,
EMIOSDIO0CLK => SDIO0_CLK,
EMIOSDIO0CLKFB => SDIO0_CLK_FB,
EMIOSDIO0CMDI => SDIO0_CMD_I,
EMIOSDIO0CMDO => SDIO0_CMD_O,
EMIOSDIO0CMDTN => SDIO0_CMD_T_n,
EMIOSDIO0DATAI(3 downto 0) => SDIO0_DATA_I(3 downto 0),
EMIOSDIO0DATAO(3 downto 0) => SDIO0_DATA_O(3 downto 0),
EMIOSDIO0DATATN(3 downto 0) => SDIO0_DATA_T_n(3 downto 0),
EMIOSDIO0LED => SDIO0_LED,
EMIOSDIO0WP => SDIO0_WP,
EMIOSDIO1BUSPOW => SDIO1_BUSPOW,
EMIOSDIO1BUSVOLT(2 downto 0) => SDIO1_BUSVOLT(2 downto 0),
EMIOSDIO1CDN => SDIO1_CDN,
EMIOSDIO1CLK => SDIO1_CLK,
EMIOSDIO1CLKFB => SDIO1_CLK_FB,
EMIOSDIO1CMDI => SDIO1_CMD_I,
EMIOSDIO1CMDO => SDIO1_CMD_O,
EMIOSDIO1CMDTN => SDIO1_CMD_T_n,
EMIOSDIO1DATAI(3 downto 0) => SDIO1_DATA_I(3 downto 0),
EMIOSDIO1DATAO(3 downto 0) => SDIO1_DATA_O(3 downto 0),
EMIOSDIO1DATATN(3 downto 0) => SDIO1_DATA_T_n(3 downto 0),
EMIOSDIO1LED => SDIO1_LED,
EMIOSDIO1WP => SDIO1_WP,
EMIOSPI0MI => SPI0_MISO_I,
EMIOSPI0MO => SPI0_MOSI_O,
EMIOSPI0MOTN => SPI0_MOSI_T_n,
EMIOSPI0SCLKI => SPI0_SCLK_I,
EMIOSPI0SCLKO => SPI0_SCLK_O,
EMIOSPI0SCLKTN => SPI0_SCLK_T_n,
EMIOSPI0SI => SPI0_MOSI_I,
EMIOSPI0SO => SPI0_MISO_O,
EMIOSPI0SSIN => SPI0_SS_I,
EMIOSPI0SSNTN => SPI0_SS_T_n,
EMIOSPI0SSON(2) => SPI0_SS2_O,
EMIOSPI0SSON(1) => SPI0_SS1_O,
EMIOSPI0SSON(0) => SPI0_SS_O,
EMIOSPI0STN => SPI0_MISO_T_n,
EMIOSPI1MI => SPI1_MISO_I,
EMIOSPI1MO => SPI1_MOSI_O,
EMIOSPI1MOTN => SPI1_MOSI_T_n,
EMIOSPI1SCLKI => SPI1_SCLK_I,
EMIOSPI1SCLKO => SPI1_SCLK_O,
EMIOSPI1SCLKTN => SPI1_SCLK_T_n,
EMIOSPI1SI => SPI1_MOSI_I,
EMIOSPI1SO => SPI1_MISO_O,
EMIOSPI1SSIN => SPI1_SS_I,
EMIOSPI1SSNTN => SPI1_SS_T_n,
EMIOSPI1SSON(2) => SPI1_SS2_O,
EMIOSPI1SSON(1) => SPI1_SS1_O,
EMIOSPI1SSON(0) => SPI1_SS_O,
EMIOSPI1STN => SPI1_MISO_T_n,
EMIOSRAMINTIN => SRAM_INTIN,
EMIOTRACECLK => TRACE_CLK,
EMIOTRACECTL => NLW_PS7_i_EMIOTRACECTL_UNCONNECTED,
EMIOTRACEDATA(31 downto 0) => NLW_PS7_i_EMIOTRACEDATA_UNCONNECTED(31 downto 0),
EMIOTTC0CLKI(2) => TTC0_CLK2_IN,
EMIOTTC0CLKI(1) => TTC0_CLK1_IN,
EMIOTTC0CLKI(0) => TTC0_CLK0_IN,
EMIOTTC0WAVEO(2) => TTC0_WAVE2_OUT,
EMIOTTC0WAVEO(1) => TTC0_WAVE1_OUT,
EMIOTTC0WAVEO(0) => TTC0_WAVE0_OUT,
EMIOTTC1CLKI(2) => TTC1_CLK2_IN,
EMIOTTC1CLKI(1) => TTC1_CLK1_IN,
EMIOTTC1CLKI(0) => TTC1_CLK0_IN,
EMIOTTC1WAVEO(2) => TTC1_WAVE2_OUT,
EMIOTTC1WAVEO(1) => TTC1_WAVE1_OUT,
EMIOTTC1WAVEO(0) => TTC1_WAVE0_OUT,
EMIOUART0CTSN => UART0_CTSN,
EMIOUART0DCDN => UART0_DCDN,
EMIOUART0DSRN => UART0_DSRN,
EMIOUART0DTRN => UART0_DTRN,
EMIOUART0RIN => UART0_RIN,
EMIOUART0RTSN => UART0_RTSN,
EMIOUART0RX => UART0_RX,
EMIOUART0TX => UART0_TX,
EMIOUART1CTSN => UART1_CTSN,
EMIOUART1DCDN => UART1_DCDN,
EMIOUART1DSRN => UART1_DSRN,
EMIOUART1DTRN => UART1_DTRN,
EMIOUART1RIN => UART1_RIN,
EMIOUART1RTSN => UART1_RTSN,
EMIOUART1RX => UART1_RX,
EMIOUART1TX => UART1_TX,
EMIOUSB0PORTINDCTL(1 downto 0) => USB0_PORT_INDCTL(1 downto 0),
EMIOUSB0VBUSPWRFAULT => USB0_VBUS_PWRFAULT,
EMIOUSB0VBUSPWRSELECT => USB0_VBUS_PWRSELECT,
EMIOUSB1PORTINDCTL(1 downto 0) => USB1_PORT_INDCTL(1 downto 0),
EMIOUSB1VBUSPWRFAULT => USB1_VBUS_PWRFAULT,
EMIOUSB1VBUSPWRSELECT => USB1_VBUS_PWRSELECT,
EMIOWDTCLKI => WDT_CLK_IN,
EMIOWDTRSTO => WDT_RST_OUT,
EVENTEVENTI => EVENT_EVENTI,
EVENTEVENTO => EVENT_EVENTO,
EVENTSTANDBYWFE(1 downto 0) => EVENT_STANDBYWFE(1 downto 0),
EVENTSTANDBYWFI(1 downto 0) => EVENT_STANDBYWFI(1 downto 0),
FCLKCLK(3) => FCLK_CLK3,
FCLKCLK(2) => FCLK_CLK2,
FCLKCLK(1) => FCLK_CLK1,
FCLKCLK(0) => FCLK_CLK_unbuffered(0),
FCLKCLKTRIGN(3 downto 0) => B"0000",
FCLKRESETN(3) => FCLK_RESET3_N,
FCLKRESETN(2) => FCLK_RESET2_N,
FCLKRESETN(1) => FCLK_RESET1_N,
FCLKRESETN(0) => FCLK_RESET0_N,
FPGAIDLEN => FPGA_IDLE_N,
FTMDTRACEINATID(3 downto 0) => B"0000",
FTMDTRACEINCLOCK => FTMD_TRACEIN_CLK,
FTMDTRACEINDATA(31 downto 0) => B"00000000000000000000000000000000",
FTMDTRACEINVALID => '0',
FTMTF2PDEBUG(31 downto 0) => FTMT_F2P_DEBUG(31 downto 0),
FTMTF2PTRIG(3) => FTMT_F2P_TRIG_3,
FTMTF2PTRIG(2) => FTMT_F2P_TRIG_2,
FTMTF2PTRIG(1) => FTMT_F2P_TRIG_1,
FTMTF2PTRIG(0) => FTMT_F2P_TRIG_0,
FTMTF2PTRIGACK(3) => FTMT_F2P_TRIGACK_3,
FTMTF2PTRIGACK(2) => FTMT_F2P_TRIGACK_2,
FTMTF2PTRIGACK(1) => FTMT_F2P_TRIGACK_1,
FTMTF2PTRIGACK(0) => FTMT_F2P_TRIGACK_0,
FTMTP2FDEBUG(31 downto 0) => FTMT_P2F_DEBUG(31 downto 0),
FTMTP2FTRIG(3) => FTMT_P2F_TRIG_3,
FTMTP2FTRIG(2) => FTMT_P2F_TRIG_2,
FTMTP2FTRIG(1) => FTMT_P2F_TRIG_1,
FTMTP2FTRIG(0) => FTMT_P2F_TRIG_0,
FTMTP2FTRIGACK(3) => FTMT_P2F_TRIGACK_3,
FTMTP2FTRIGACK(2) => FTMT_P2F_TRIGACK_2,
FTMTP2FTRIGACK(1) => FTMT_P2F_TRIGACK_1,
FTMTP2FTRIGACK(0) => FTMT_P2F_TRIGACK_0,
IRQF2P(19) => Core1_nFIQ,
IRQF2P(18) => Core0_nFIQ,
IRQF2P(17) => Core1_nIRQ,
IRQF2P(16) => Core0_nIRQ,
IRQF2P(15 downto 1) => B"000000000000000",
IRQF2P(0) => IRQ_F2P(0),
IRQP2F(28) => IRQ_P2F_DMAC_ABORT,
IRQP2F(27) => IRQ_P2F_DMAC7,
IRQP2F(26) => IRQ_P2F_DMAC6,
IRQP2F(25) => IRQ_P2F_DMAC5,
IRQP2F(24) => IRQ_P2F_DMAC4,
IRQP2F(23) => IRQ_P2F_DMAC3,
IRQP2F(22) => IRQ_P2F_DMAC2,
IRQP2F(21) => IRQ_P2F_DMAC1,
IRQP2F(20) => IRQ_P2F_DMAC0,
IRQP2F(19) => IRQ_P2F_SMC,
IRQP2F(18) => IRQ_P2F_QSPI,
IRQP2F(17) => IRQ_P2F_CTI,
IRQP2F(16) => IRQ_P2F_GPIO,
IRQP2F(15) => IRQ_P2F_USB0,
IRQP2F(14) => IRQ_P2F_ENET0,
IRQP2F(13) => IRQ_P2F_ENET_WAKE0,
IRQP2F(12) => IRQ_P2F_SDIO0,
IRQP2F(11) => IRQ_P2F_I2C0,
IRQP2F(10) => IRQ_P2F_SPI0,
IRQP2F(9) => IRQ_P2F_UART0,
IRQP2F(8) => IRQ_P2F_CAN0,
IRQP2F(7) => IRQ_P2F_USB1,
IRQP2F(6) => IRQ_P2F_ENET1,
IRQP2F(5) => IRQ_P2F_ENET_WAKE1,
IRQP2F(4) => IRQ_P2F_SDIO1,
IRQP2F(3) => IRQ_P2F_I2C1,
IRQP2F(2) => IRQ_P2F_SPI1,
IRQP2F(1) => IRQ_P2F_UART1,
IRQP2F(0) => IRQ_P2F_CAN1,
MAXIGP0ACLK => M_AXI_GP0_ACLK,
MAXIGP0ARADDR(31 downto 0) => M_AXI_GP0_ARADDR(31 downto 0),
MAXIGP0ARBURST(1 downto 0) => M_AXI_GP0_ARBURST(1 downto 0),
MAXIGP0ARCACHE(3 downto 2) => \^m_axi_gp0_arcache\(3 downto 2),
MAXIGP0ARCACHE(1) => NLW_PS7_i_MAXIGP0ARCACHE_UNCONNECTED(1),
MAXIGP0ARCACHE(0) => \^m_axi_gp0_arcache\(0),
MAXIGP0ARESETN => M_AXI_GP0_ARESETN,
MAXIGP0ARID(11 downto 0) => M_AXI_GP0_ARID(11 downto 0),
MAXIGP0ARLEN(3 downto 0) => M_AXI_GP0_ARLEN(3 downto 0),
MAXIGP0ARLOCK(1 downto 0) => M_AXI_GP0_ARLOCK(1 downto 0),
MAXIGP0ARPROT(2 downto 0) => M_AXI_GP0_ARPROT(2 downto 0),
MAXIGP0ARQOS(3 downto 0) => M_AXI_GP0_ARQOS(3 downto 0),
MAXIGP0ARREADY => M_AXI_GP0_ARREADY,
MAXIGP0ARSIZE(1 downto 0) => \^m_axi_gp0_arsize\(1 downto 0),
MAXIGP0ARVALID => M_AXI_GP0_ARVALID,
MAXIGP0AWADDR(31 downto 0) => M_AXI_GP0_AWADDR(31 downto 0),
MAXIGP0AWBURST(1 downto 0) => M_AXI_GP0_AWBURST(1 downto 0),
MAXIGP0AWCACHE(3 downto 2) => \^m_axi_gp0_awcache\(3 downto 2),
MAXIGP0AWCACHE(1) => NLW_PS7_i_MAXIGP0AWCACHE_UNCONNECTED(1),
MAXIGP0AWCACHE(0) => \^m_axi_gp0_awcache\(0),
MAXIGP0AWID(11 downto 0) => M_AXI_GP0_AWID(11 downto 0),
MAXIGP0AWLEN(3 downto 0) => M_AXI_GP0_AWLEN(3 downto 0),
MAXIGP0AWLOCK(1 downto 0) => M_AXI_GP0_AWLOCK(1 downto 0),
MAXIGP0AWPROT(2 downto 0) => M_AXI_GP0_AWPROT(2 downto 0),
MAXIGP0AWQOS(3 downto 0) => M_AXI_GP0_AWQOS(3 downto 0),
MAXIGP0AWREADY => M_AXI_GP0_AWREADY,
MAXIGP0AWSIZE(1 downto 0) => \^m_axi_gp0_awsize\(1 downto 0),
MAXIGP0AWVALID => M_AXI_GP0_AWVALID,
MAXIGP0BID(11 downto 0) => M_AXI_GP0_BID(11 downto 0),
MAXIGP0BREADY => M_AXI_GP0_BREADY,
MAXIGP0BRESP(1 downto 0) => M_AXI_GP0_BRESP(1 downto 0),
MAXIGP0BVALID => M_AXI_GP0_BVALID,
MAXIGP0RDATA(31 downto 0) => M_AXI_GP0_RDATA(31 downto 0),
MAXIGP0RID(11 downto 0) => M_AXI_GP0_RID(11 downto 0),
MAXIGP0RLAST => M_AXI_GP0_RLAST,
MAXIGP0RREADY => M_AXI_GP0_RREADY,
MAXIGP0RRESP(1 downto 0) => M_AXI_GP0_RRESP(1 downto 0),
MAXIGP0RVALID => M_AXI_GP0_RVALID,
MAXIGP0WDATA(31 downto 0) => M_AXI_GP0_WDATA(31 downto 0),
MAXIGP0WID(11 downto 0) => M_AXI_GP0_WID(11 downto 0),
MAXIGP0WLAST => M_AXI_GP0_WLAST,
MAXIGP0WREADY => M_AXI_GP0_WREADY,
MAXIGP0WSTRB(3 downto 0) => M_AXI_GP0_WSTRB(3 downto 0),
MAXIGP0WVALID => M_AXI_GP0_WVALID,
MAXIGP1ACLK => M_AXI_GP1_ACLK,
MAXIGP1ARADDR(31 downto 0) => M_AXI_GP1_ARADDR(31 downto 0),
MAXIGP1ARBURST(1 downto 0) => M_AXI_GP1_ARBURST(1 downto 0),
MAXIGP1ARCACHE(3 downto 2) => \^m_axi_gp1_arcache\(3 downto 2),
MAXIGP1ARCACHE(1) => NLW_PS7_i_MAXIGP1ARCACHE_UNCONNECTED(1),
MAXIGP1ARCACHE(0) => \^m_axi_gp1_arcache\(0),
MAXIGP1ARESETN => M_AXI_GP1_ARESETN,
MAXIGP1ARID(11 downto 0) => M_AXI_GP1_ARID(11 downto 0),
MAXIGP1ARLEN(3 downto 0) => M_AXI_GP1_ARLEN(3 downto 0),
MAXIGP1ARLOCK(1 downto 0) => M_AXI_GP1_ARLOCK(1 downto 0),
MAXIGP1ARPROT(2 downto 0) => M_AXI_GP1_ARPROT(2 downto 0),
MAXIGP1ARQOS(3 downto 0) => M_AXI_GP1_ARQOS(3 downto 0),
MAXIGP1ARREADY => M_AXI_GP1_ARREADY,
MAXIGP1ARSIZE(1 downto 0) => \^m_axi_gp1_arsize\(1 downto 0),
MAXIGP1ARVALID => M_AXI_GP1_ARVALID,
MAXIGP1AWADDR(31 downto 0) => M_AXI_GP1_AWADDR(31 downto 0),
MAXIGP1AWBURST(1 downto 0) => M_AXI_GP1_AWBURST(1 downto 0),
MAXIGP1AWCACHE(3 downto 2) => \^m_axi_gp1_awcache\(3 downto 2),
MAXIGP1AWCACHE(1) => NLW_PS7_i_MAXIGP1AWCACHE_UNCONNECTED(1),
MAXIGP1AWCACHE(0) => \^m_axi_gp1_awcache\(0),
MAXIGP1AWID(11 downto 0) => M_AXI_GP1_AWID(11 downto 0),
MAXIGP1AWLEN(3 downto 0) => M_AXI_GP1_AWLEN(3 downto 0),
MAXIGP1AWLOCK(1 downto 0) => M_AXI_GP1_AWLOCK(1 downto 0),
MAXIGP1AWPROT(2 downto 0) => M_AXI_GP1_AWPROT(2 downto 0),
MAXIGP1AWQOS(3 downto 0) => M_AXI_GP1_AWQOS(3 downto 0),
MAXIGP1AWREADY => M_AXI_GP1_AWREADY,
MAXIGP1AWSIZE(1 downto 0) => \^m_axi_gp1_awsize\(1 downto 0),
MAXIGP1AWVALID => M_AXI_GP1_AWVALID,
MAXIGP1BID(11 downto 0) => M_AXI_GP1_BID(11 downto 0),
MAXIGP1BREADY => M_AXI_GP1_BREADY,
MAXIGP1BRESP(1 downto 0) => M_AXI_GP1_BRESP(1 downto 0),
MAXIGP1BVALID => M_AXI_GP1_BVALID,
MAXIGP1RDATA(31 downto 0) => M_AXI_GP1_RDATA(31 downto 0),
MAXIGP1RID(11 downto 0) => M_AXI_GP1_RID(11 downto 0),
MAXIGP1RLAST => M_AXI_GP1_RLAST,
MAXIGP1RREADY => M_AXI_GP1_RREADY,
MAXIGP1RRESP(1 downto 0) => M_AXI_GP1_RRESP(1 downto 0),
MAXIGP1RVALID => M_AXI_GP1_RVALID,
MAXIGP1WDATA(31 downto 0) => M_AXI_GP1_WDATA(31 downto 0),
MAXIGP1WID(11 downto 0) => M_AXI_GP1_WID(11 downto 0),
MAXIGP1WLAST => M_AXI_GP1_WLAST,
MAXIGP1WREADY => M_AXI_GP1_WREADY,
MAXIGP1WSTRB(3 downto 0) => M_AXI_GP1_WSTRB(3 downto 0),
MAXIGP1WVALID => M_AXI_GP1_WVALID,
MIO(53 downto 0) => buffered_MIO(53 downto 0),
PSCLK => buffered_PS_CLK,
PSPORB => buffered_PS_PORB,
PSSRSTB => buffered_PS_SRSTB,
SAXIACPACLK => S_AXI_ACP_ACLK,
SAXIACPARADDR(31 downto 0) => S_AXI_ACP_ARADDR(31 downto 0),
SAXIACPARBURST(1 downto 0) => S_AXI_ACP_ARBURST(1 downto 0),
SAXIACPARCACHE(3 downto 0) => S_AXI_ACP_ARCACHE(3 downto 0),
SAXIACPARESETN => S_AXI_ACP_ARESETN,
SAXIACPARID(2 downto 0) => S_AXI_ACP_ARID(2 downto 0),
SAXIACPARLEN(3 downto 0) => S_AXI_ACP_ARLEN(3 downto 0),
SAXIACPARLOCK(1 downto 0) => S_AXI_ACP_ARLOCK(1 downto 0),
SAXIACPARPROT(2 downto 0) => S_AXI_ACP_ARPROT(2 downto 0),
SAXIACPARQOS(3 downto 0) => S_AXI_ACP_ARQOS(3 downto 0),
SAXIACPARREADY => S_AXI_ACP_ARREADY,
SAXIACPARSIZE(1 downto 0) => S_AXI_ACP_ARSIZE(1 downto 0),
SAXIACPARUSER(4 downto 0) => S_AXI_ACP_ARUSER(4 downto 0),
SAXIACPARVALID => S_AXI_ACP_ARVALID,
SAXIACPAWADDR(31 downto 0) => S_AXI_ACP_AWADDR(31 downto 0),
SAXIACPAWBURST(1 downto 0) => S_AXI_ACP_AWBURST(1 downto 0),
SAXIACPAWCACHE(3 downto 0) => S_AXI_ACP_AWCACHE(3 downto 0),
SAXIACPAWID(2 downto 0) => S_AXI_ACP_AWID(2 downto 0),
SAXIACPAWLEN(3 downto 0) => S_AXI_ACP_AWLEN(3 downto 0),
SAXIACPAWLOCK(1 downto 0) => S_AXI_ACP_AWLOCK(1 downto 0),
SAXIACPAWPROT(2 downto 0) => S_AXI_ACP_AWPROT(2 downto 0),
SAXIACPAWQOS(3 downto 0) => S_AXI_ACP_AWQOS(3 downto 0),
SAXIACPAWREADY => S_AXI_ACP_AWREADY,
SAXIACPAWSIZE(1 downto 0) => S_AXI_ACP_AWSIZE(1 downto 0),
SAXIACPAWUSER(4 downto 0) => S_AXI_ACP_AWUSER(4 downto 0),
SAXIACPAWVALID => S_AXI_ACP_AWVALID,
SAXIACPBID(2 downto 0) => S_AXI_ACP_BID(2 downto 0),
SAXIACPBREADY => S_AXI_ACP_BREADY,
SAXIACPBRESP(1 downto 0) => S_AXI_ACP_BRESP(1 downto 0),
SAXIACPBVALID => S_AXI_ACP_BVALID,
SAXIACPRDATA(63 downto 0) => S_AXI_ACP_RDATA(63 downto 0),
SAXIACPRID(2 downto 0) => S_AXI_ACP_RID(2 downto 0),
SAXIACPRLAST => S_AXI_ACP_RLAST,
SAXIACPRREADY => S_AXI_ACP_RREADY,
SAXIACPRRESP(1 downto 0) => S_AXI_ACP_RRESP(1 downto 0),
SAXIACPRVALID => S_AXI_ACP_RVALID,
SAXIACPWDATA(63 downto 0) => S_AXI_ACP_WDATA(63 downto 0),
SAXIACPWID(2 downto 0) => S_AXI_ACP_WID(2 downto 0),
SAXIACPWLAST => S_AXI_ACP_WLAST,
SAXIACPWREADY => S_AXI_ACP_WREADY,
SAXIACPWSTRB(7 downto 0) => S_AXI_ACP_WSTRB(7 downto 0),
SAXIACPWVALID => S_AXI_ACP_WVALID,
SAXIGP0ACLK => S_AXI_GP0_ACLK,
SAXIGP0ARADDR(31 downto 0) => S_AXI_GP0_ARADDR(31 downto 0),
SAXIGP0ARBURST(1 downto 0) => S_AXI_GP0_ARBURST(1 downto 0),
SAXIGP0ARCACHE(3 downto 0) => S_AXI_GP0_ARCACHE(3 downto 0),
SAXIGP0ARESETN => S_AXI_GP0_ARESETN,
SAXIGP0ARID(5 downto 0) => S_AXI_GP0_ARID(5 downto 0),
SAXIGP0ARLEN(3 downto 0) => S_AXI_GP0_ARLEN(3 downto 0),
SAXIGP0ARLOCK(1 downto 0) => S_AXI_GP0_ARLOCK(1 downto 0),
SAXIGP0ARPROT(2 downto 0) => S_AXI_GP0_ARPROT(2 downto 0),
SAXIGP0ARQOS(3 downto 0) => S_AXI_GP0_ARQOS(3 downto 0),
SAXIGP0ARREADY => S_AXI_GP0_ARREADY,
SAXIGP0ARSIZE(1 downto 0) => S_AXI_GP0_ARSIZE(1 downto 0),
SAXIGP0ARVALID => S_AXI_GP0_ARVALID,
SAXIGP0AWADDR(31 downto 0) => S_AXI_GP0_AWADDR(31 downto 0),
SAXIGP0AWBURST(1 downto 0) => S_AXI_GP0_AWBURST(1 downto 0),
SAXIGP0AWCACHE(3 downto 0) => S_AXI_GP0_AWCACHE(3 downto 0),
SAXIGP0AWID(5 downto 0) => S_AXI_GP0_AWID(5 downto 0),
SAXIGP0AWLEN(3 downto 0) => S_AXI_GP0_AWLEN(3 downto 0),
SAXIGP0AWLOCK(1 downto 0) => S_AXI_GP0_AWLOCK(1 downto 0),
SAXIGP0AWPROT(2 downto 0) => S_AXI_GP0_AWPROT(2 downto 0),
SAXIGP0AWQOS(3 downto 0) => S_AXI_GP0_AWQOS(3 downto 0),
SAXIGP0AWREADY => S_AXI_GP0_AWREADY,
SAXIGP0AWSIZE(1 downto 0) => S_AXI_GP0_AWSIZE(1 downto 0),
SAXIGP0AWVALID => S_AXI_GP0_AWVALID,
SAXIGP0BID(5 downto 0) => S_AXI_GP0_BID(5 downto 0),
SAXIGP0BREADY => S_AXI_GP0_BREADY,
SAXIGP0BRESP(1 downto 0) => S_AXI_GP0_BRESP(1 downto 0),
SAXIGP0BVALID => S_AXI_GP0_BVALID,
SAXIGP0RDATA(31 downto 0) => S_AXI_GP0_RDATA(31 downto 0),
SAXIGP0RID(5 downto 0) => S_AXI_GP0_RID(5 downto 0),
SAXIGP0RLAST => S_AXI_GP0_RLAST,
SAXIGP0RREADY => S_AXI_GP0_RREADY,
SAXIGP0RRESP(1 downto 0) => S_AXI_GP0_RRESP(1 downto 0),
SAXIGP0RVALID => S_AXI_GP0_RVALID,
SAXIGP0WDATA(31 downto 0) => S_AXI_GP0_WDATA(31 downto 0),
SAXIGP0WID(5 downto 0) => S_AXI_GP0_WID(5 downto 0),
SAXIGP0WLAST => S_AXI_GP0_WLAST,
SAXIGP0WREADY => S_AXI_GP0_WREADY,
SAXIGP0WSTRB(3 downto 0) => S_AXI_GP0_WSTRB(3 downto 0),
SAXIGP0WVALID => S_AXI_GP0_WVALID,
SAXIGP1ACLK => S_AXI_GP1_ACLK,
SAXIGP1ARADDR(31 downto 0) => S_AXI_GP1_ARADDR(31 downto 0),
SAXIGP1ARBURST(1 downto 0) => S_AXI_GP1_ARBURST(1 downto 0),
SAXIGP1ARCACHE(3 downto 0) => S_AXI_GP1_ARCACHE(3 downto 0),
SAXIGP1ARESETN => S_AXI_GP1_ARESETN,
SAXIGP1ARID(5 downto 0) => S_AXI_GP1_ARID(5 downto 0),
SAXIGP1ARLEN(3 downto 0) => S_AXI_GP1_ARLEN(3 downto 0),
SAXIGP1ARLOCK(1 downto 0) => S_AXI_GP1_ARLOCK(1 downto 0),
SAXIGP1ARPROT(2 downto 0) => S_AXI_GP1_ARPROT(2 downto 0),
SAXIGP1ARQOS(3 downto 0) => S_AXI_GP1_ARQOS(3 downto 0),
SAXIGP1ARREADY => S_AXI_GP1_ARREADY,
SAXIGP1ARSIZE(1 downto 0) => S_AXI_GP1_ARSIZE(1 downto 0),
SAXIGP1ARVALID => S_AXI_GP1_ARVALID,
SAXIGP1AWADDR(31 downto 0) => S_AXI_GP1_AWADDR(31 downto 0),
SAXIGP1AWBURST(1 downto 0) => S_AXI_GP1_AWBURST(1 downto 0),
SAXIGP1AWCACHE(3 downto 0) => S_AXI_GP1_AWCACHE(3 downto 0),
SAXIGP1AWID(5 downto 0) => S_AXI_GP1_AWID(5 downto 0),
SAXIGP1AWLEN(3 downto 0) => S_AXI_GP1_AWLEN(3 downto 0),
SAXIGP1AWLOCK(1 downto 0) => S_AXI_GP1_AWLOCK(1 downto 0),
SAXIGP1AWPROT(2 downto 0) => S_AXI_GP1_AWPROT(2 downto 0),
SAXIGP1AWQOS(3 downto 0) => S_AXI_GP1_AWQOS(3 downto 0),
SAXIGP1AWREADY => S_AXI_GP1_AWREADY,
SAXIGP1AWSIZE(1 downto 0) => S_AXI_GP1_AWSIZE(1 downto 0),
SAXIGP1AWVALID => S_AXI_GP1_AWVALID,
SAXIGP1BID(5 downto 0) => S_AXI_GP1_BID(5 downto 0),
SAXIGP1BREADY => S_AXI_GP1_BREADY,
SAXIGP1BRESP(1 downto 0) => S_AXI_GP1_BRESP(1 downto 0),
SAXIGP1BVALID => S_AXI_GP1_BVALID,
SAXIGP1RDATA(31 downto 0) => S_AXI_GP1_RDATA(31 downto 0),
SAXIGP1RID(5 downto 0) => S_AXI_GP1_RID(5 downto 0),
SAXIGP1RLAST => S_AXI_GP1_RLAST,
SAXIGP1RREADY => S_AXI_GP1_RREADY,
SAXIGP1RRESP(1 downto 0) => S_AXI_GP1_RRESP(1 downto 0),
SAXIGP1RVALID => S_AXI_GP1_RVALID,
SAXIGP1WDATA(31 downto 0) => S_AXI_GP1_WDATA(31 downto 0),
SAXIGP1WID(5 downto 0) => S_AXI_GP1_WID(5 downto 0),
SAXIGP1WLAST => S_AXI_GP1_WLAST,
SAXIGP1WREADY => S_AXI_GP1_WREADY,
SAXIGP1WSTRB(3 downto 0) => S_AXI_GP1_WSTRB(3 downto 0),
SAXIGP1WVALID => S_AXI_GP1_WVALID,
SAXIHP0ACLK => S_AXI_HP0_ACLK,
SAXIHP0ARADDR(31 downto 0) => S_AXI_HP0_ARADDR(31 downto 0),
SAXIHP0ARBURST(1 downto 0) => S_AXI_HP0_ARBURST(1 downto 0),
SAXIHP0ARCACHE(3 downto 0) => S_AXI_HP0_ARCACHE(3 downto 0),
SAXIHP0ARESETN => S_AXI_HP0_ARESETN,
SAXIHP0ARID(5 downto 0) => S_AXI_HP0_ARID(5 downto 0),
SAXIHP0ARLEN(3 downto 0) => S_AXI_HP0_ARLEN(3 downto 0),
SAXIHP0ARLOCK(1 downto 0) => S_AXI_HP0_ARLOCK(1 downto 0),
SAXIHP0ARPROT(2 downto 0) => S_AXI_HP0_ARPROT(2 downto 0),
SAXIHP0ARQOS(3 downto 0) => S_AXI_HP0_ARQOS(3 downto 0),
SAXIHP0ARREADY => S_AXI_HP0_ARREADY,
SAXIHP0ARSIZE(1 downto 0) => S_AXI_HP0_ARSIZE(1 downto 0),
SAXIHP0ARVALID => S_AXI_HP0_ARVALID,
SAXIHP0AWADDR(31 downto 0) => S_AXI_HP0_AWADDR(31 downto 0),
SAXIHP0AWBURST(1 downto 0) => S_AXI_HP0_AWBURST(1 downto 0),
SAXIHP0AWCACHE(3 downto 0) => S_AXI_HP0_AWCACHE(3 downto 0),
SAXIHP0AWID(5 downto 0) => S_AXI_HP0_AWID(5 downto 0),
SAXIHP0AWLEN(3 downto 0) => S_AXI_HP0_AWLEN(3 downto 0),
SAXIHP0AWLOCK(1 downto 0) => S_AXI_HP0_AWLOCK(1 downto 0),
SAXIHP0AWPROT(2 downto 0) => S_AXI_HP0_AWPROT(2 downto 0),
SAXIHP0AWQOS(3 downto 0) => S_AXI_HP0_AWQOS(3 downto 0),
SAXIHP0AWREADY => S_AXI_HP0_AWREADY,
SAXIHP0AWSIZE(1 downto 0) => S_AXI_HP0_AWSIZE(1 downto 0),
SAXIHP0AWVALID => S_AXI_HP0_AWVALID,
SAXIHP0BID(5 downto 0) => S_AXI_HP0_BID(5 downto 0),
SAXIHP0BREADY => S_AXI_HP0_BREADY,
SAXIHP0BRESP(1 downto 0) => S_AXI_HP0_BRESP(1 downto 0),
SAXIHP0BVALID => S_AXI_HP0_BVALID,
SAXIHP0RACOUNT(2 downto 0) => S_AXI_HP0_RACOUNT(2 downto 0),
SAXIHP0RCOUNT(7 downto 0) => S_AXI_HP0_RCOUNT(7 downto 0),
SAXIHP0RDATA(63 downto 0) => S_AXI_HP0_RDATA(63 downto 0),
SAXIHP0RDISSUECAP1EN => S_AXI_HP0_RDISSUECAP1_EN,
SAXIHP0RID(5 downto 0) => S_AXI_HP0_RID(5 downto 0),
SAXIHP0RLAST => S_AXI_HP0_RLAST,
SAXIHP0RREADY => S_AXI_HP0_RREADY,
SAXIHP0RRESP(1 downto 0) => S_AXI_HP0_RRESP(1 downto 0),
SAXIHP0RVALID => S_AXI_HP0_RVALID,
SAXIHP0WACOUNT(5 downto 0) => S_AXI_HP0_WACOUNT(5 downto 0),
SAXIHP0WCOUNT(7 downto 0) => S_AXI_HP0_WCOUNT(7 downto 0),
SAXIHP0WDATA(63 downto 0) => S_AXI_HP0_WDATA(63 downto 0),
SAXIHP0WID(5 downto 0) => S_AXI_HP0_WID(5 downto 0),
SAXIHP0WLAST => S_AXI_HP0_WLAST,
SAXIHP0WREADY => S_AXI_HP0_WREADY,
SAXIHP0WRISSUECAP1EN => S_AXI_HP0_WRISSUECAP1_EN,
SAXIHP0WSTRB(7 downto 0) => S_AXI_HP0_WSTRB(7 downto 0),
SAXIHP0WVALID => S_AXI_HP0_WVALID,
SAXIHP1ACLK => S_AXI_HP1_ACLK,
SAXIHP1ARADDR(31 downto 0) => S_AXI_HP1_ARADDR(31 downto 0),
SAXIHP1ARBURST(1 downto 0) => S_AXI_HP1_ARBURST(1 downto 0),
SAXIHP1ARCACHE(3 downto 0) => S_AXI_HP1_ARCACHE(3 downto 0),
SAXIHP1ARESETN => S_AXI_HP1_ARESETN,
SAXIHP1ARID(5 downto 0) => S_AXI_HP1_ARID(5 downto 0),
SAXIHP1ARLEN(3 downto 0) => S_AXI_HP1_ARLEN(3 downto 0),
SAXIHP1ARLOCK(1 downto 0) => S_AXI_HP1_ARLOCK(1 downto 0),
SAXIHP1ARPROT(2 downto 0) => S_AXI_HP1_ARPROT(2 downto 0),
SAXIHP1ARQOS(3 downto 0) => S_AXI_HP1_ARQOS(3 downto 0),
SAXIHP1ARREADY => S_AXI_HP1_ARREADY,
SAXIHP1ARSIZE(1 downto 0) => S_AXI_HP1_ARSIZE(1 downto 0),
SAXIHP1ARVALID => S_AXI_HP1_ARVALID,
SAXIHP1AWADDR(31 downto 0) => S_AXI_HP1_AWADDR(31 downto 0),
SAXIHP1AWBURST(1 downto 0) => S_AXI_HP1_AWBURST(1 downto 0),
SAXIHP1AWCACHE(3 downto 0) => S_AXI_HP1_AWCACHE(3 downto 0),
SAXIHP1AWID(5 downto 0) => S_AXI_HP1_AWID(5 downto 0),
SAXIHP1AWLEN(3 downto 0) => S_AXI_HP1_AWLEN(3 downto 0),
SAXIHP1AWLOCK(1 downto 0) => S_AXI_HP1_AWLOCK(1 downto 0),
SAXIHP1AWPROT(2 downto 0) => S_AXI_HP1_AWPROT(2 downto 0),
SAXIHP1AWQOS(3 downto 0) => S_AXI_HP1_AWQOS(3 downto 0),
SAXIHP1AWREADY => S_AXI_HP1_AWREADY,
SAXIHP1AWSIZE(1 downto 0) => S_AXI_HP1_AWSIZE(1 downto 0),
SAXIHP1AWVALID => S_AXI_HP1_AWVALID,
SAXIHP1BID(5 downto 0) => S_AXI_HP1_BID(5 downto 0),
SAXIHP1BREADY => S_AXI_HP1_BREADY,
SAXIHP1BRESP(1 downto 0) => S_AXI_HP1_BRESP(1 downto 0),
SAXIHP1BVALID => S_AXI_HP1_BVALID,
SAXIHP1RACOUNT(2 downto 0) => S_AXI_HP1_RACOUNT(2 downto 0),
SAXIHP1RCOUNT(7 downto 0) => S_AXI_HP1_RCOUNT(7 downto 0),
SAXIHP1RDATA(63 downto 0) => S_AXI_HP1_RDATA(63 downto 0),
SAXIHP1RDISSUECAP1EN => S_AXI_HP1_RDISSUECAP1_EN,
SAXIHP1RID(5 downto 0) => S_AXI_HP1_RID(5 downto 0),
SAXIHP1RLAST => S_AXI_HP1_RLAST,
SAXIHP1RREADY => S_AXI_HP1_RREADY,
SAXIHP1RRESP(1 downto 0) => S_AXI_HP1_RRESP(1 downto 0),
SAXIHP1RVALID => S_AXI_HP1_RVALID,
SAXIHP1WACOUNT(5 downto 0) => S_AXI_HP1_WACOUNT(5 downto 0),
SAXIHP1WCOUNT(7 downto 0) => S_AXI_HP1_WCOUNT(7 downto 0),
SAXIHP1WDATA(63 downto 0) => S_AXI_HP1_WDATA(63 downto 0),
SAXIHP1WID(5 downto 0) => S_AXI_HP1_WID(5 downto 0),
SAXIHP1WLAST => S_AXI_HP1_WLAST,
SAXIHP1WREADY => S_AXI_HP1_WREADY,
SAXIHP1WRISSUECAP1EN => S_AXI_HP1_WRISSUECAP1_EN,
SAXIHP1WSTRB(7 downto 0) => S_AXI_HP1_WSTRB(7 downto 0),
SAXIHP1WVALID => S_AXI_HP1_WVALID,
SAXIHP2ACLK => S_AXI_HP2_ACLK,
SAXIHP2ARADDR(31 downto 0) => S_AXI_HP2_ARADDR(31 downto 0),
SAXIHP2ARBURST(1 downto 0) => S_AXI_HP2_ARBURST(1 downto 0),
SAXIHP2ARCACHE(3 downto 0) => S_AXI_HP2_ARCACHE(3 downto 0),
SAXIHP2ARESETN => S_AXI_HP2_ARESETN,
SAXIHP2ARID(5 downto 0) => S_AXI_HP2_ARID(5 downto 0),
SAXIHP2ARLEN(3 downto 0) => S_AXI_HP2_ARLEN(3 downto 0),
SAXIHP2ARLOCK(1 downto 0) => S_AXI_HP2_ARLOCK(1 downto 0),
SAXIHP2ARPROT(2 downto 0) => S_AXI_HP2_ARPROT(2 downto 0),
SAXIHP2ARQOS(3 downto 0) => S_AXI_HP2_ARQOS(3 downto 0),
SAXIHP2ARREADY => S_AXI_HP2_ARREADY,
SAXIHP2ARSIZE(1 downto 0) => S_AXI_HP2_ARSIZE(1 downto 0),
SAXIHP2ARVALID => S_AXI_HP2_ARVALID,
SAXIHP2AWADDR(31 downto 0) => S_AXI_HP2_AWADDR(31 downto 0),
SAXIHP2AWBURST(1 downto 0) => S_AXI_HP2_AWBURST(1 downto 0),
SAXIHP2AWCACHE(3 downto 0) => S_AXI_HP2_AWCACHE(3 downto 0),
SAXIHP2AWID(5 downto 0) => S_AXI_HP2_AWID(5 downto 0),
SAXIHP2AWLEN(3 downto 0) => S_AXI_HP2_AWLEN(3 downto 0),
SAXIHP2AWLOCK(1 downto 0) => S_AXI_HP2_AWLOCK(1 downto 0),
SAXIHP2AWPROT(2 downto 0) => S_AXI_HP2_AWPROT(2 downto 0),
SAXIHP2AWQOS(3 downto 0) => S_AXI_HP2_AWQOS(3 downto 0),
SAXIHP2AWREADY => S_AXI_HP2_AWREADY,
SAXIHP2AWSIZE(1 downto 0) => S_AXI_HP2_AWSIZE(1 downto 0),
SAXIHP2AWVALID => S_AXI_HP2_AWVALID,
SAXIHP2BID(5 downto 0) => S_AXI_HP2_BID(5 downto 0),
SAXIHP2BREADY => S_AXI_HP2_BREADY,
SAXIHP2BRESP(1 downto 0) => S_AXI_HP2_BRESP(1 downto 0),
SAXIHP2BVALID => S_AXI_HP2_BVALID,
SAXIHP2RACOUNT(2 downto 0) => S_AXI_HP2_RACOUNT(2 downto 0),
SAXIHP2RCOUNT(7 downto 0) => S_AXI_HP2_RCOUNT(7 downto 0),
SAXIHP2RDATA(63 downto 0) => S_AXI_HP2_RDATA(63 downto 0),
SAXIHP2RDISSUECAP1EN => S_AXI_HP2_RDISSUECAP1_EN,
SAXIHP2RID(5 downto 0) => S_AXI_HP2_RID(5 downto 0),
SAXIHP2RLAST => S_AXI_HP2_RLAST,
SAXIHP2RREADY => S_AXI_HP2_RREADY,
SAXIHP2RRESP(1 downto 0) => S_AXI_HP2_RRESP(1 downto 0),
SAXIHP2RVALID => S_AXI_HP2_RVALID,
SAXIHP2WACOUNT(5 downto 0) => S_AXI_HP2_WACOUNT(5 downto 0),
SAXIHP2WCOUNT(7 downto 0) => S_AXI_HP2_WCOUNT(7 downto 0),
SAXIHP2WDATA(63 downto 0) => S_AXI_HP2_WDATA(63 downto 0),
SAXIHP2WID(5 downto 0) => S_AXI_HP2_WID(5 downto 0),
SAXIHP2WLAST => S_AXI_HP2_WLAST,
SAXIHP2WREADY => S_AXI_HP2_WREADY,
SAXIHP2WRISSUECAP1EN => S_AXI_HP2_WRISSUECAP1_EN,
SAXIHP2WSTRB(7 downto 0) => S_AXI_HP2_WSTRB(7 downto 0),
SAXIHP2WVALID => S_AXI_HP2_WVALID,
SAXIHP3ACLK => S_AXI_HP3_ACLK,
SAXIHP3ARADDR(31 downto 0) => S_AXI_HP3_ARADDR(31 downto 0),
SAXIHP3ARBURST(1 downto 0) => S_AXI_HP3_ARBURST(1 downto 0),
SAXIHP3ARCACHE(3 downto 0) => S_AXI_HP3_ARCACHE(3 downto 0),
SAXIHP3ARESETN => S_AXI_HP3_ARESETN,
SAXIHP3ARID(5 downto 0) => S_AXI_HP3_ARID(5 downto 0),
SAXIHP3ARLEN(3 downto 0) => S_AXI_HP3_ARLEN(3 downto 0),
SAXIHP3ARLOCK(1 downto 0) => S_AXI_HP3_ARLOCK(1 downto 0),
SAXIHP3ARPROT(2 downto 0) => S_AXI_HP3_ARPROT(2 downto 0),
SAXIHP3ARQOS(3 downto 0) => S_AXI_HP3_ARQOS(3 downto 0),
SAXIHP3ARREADY => S_AXI_HP3_ARREADY,
SAXIHP3ARSIZE(1 downto 0) => S_AXI_HP3_ARSIZE(1 downto 0),
SAXIHP3ARVALID => S_AXI_HP3_ARVALID,
SAXIHP3AWADDR(31 downto 0) => S_AXI_HP3_AWADDR(31 downto 0),
SAXIHP3AWBURST(1 downto 0) => S_AXI_HP3_AWBURST(1 downto 0),
SAXIHP3AWCACHE(3 downto 0) => S_AXI_HP3_AWCACHE(3 downto 0),
SAXIHP3AWID(5 downto 0) => S_AXI_HP3_AWID(5 downto 0),
SAXIHP3AWLEN(3 downto 0) => S_AXI_HP3_AWLEN(3 downto 0),
SAXIHP3AWLOCK(1 downto 0) => S_AXI_HP3_AWLOCK(1 downto 0),
SAXIHP3AWPROT(2 downto 0) => S_AXI_HP3_AWPROT(2 downto 0),
SAXIHP3AWQOS(3 downto 0) => S_AXI_HP3_AWQOS(3 downto 0),
SAXIHP3AWREADY => S_AXI_HP3_AWREADY,
SAXIHP3AWSIZE(1 downto 0) => S_AXI_HP3_AWSIZE(1 downto 0),
SAXIHP3AWVALID => S_AXI_HP3_AWVALID,
SAXIHP3BID(5 downto 0) => S_AXI_HP3_BID(5 downto 0),
SAXIHP3BREADY => S_AXI_HP3_BREADY,
SAXIHP3BRESP(1 downto 0) => S_AXI_HP3_BRESP(1 downto 0),
SAXIHP3BVALID => S_AXI_HP3_BVALID,
SAXIHP3RACOUNT(2 downto 0) => S_AXI_HP3_RACOUNT(2 downto 0),
SAXIHP3RCOUNT(7 downto 0) => S_AXI_HP3_RCOUNT(7 downto 0),
SAXIHP3RDATA(63 downto 0) => S_AXI_HP3_RDATA(63 downto 0),
SAXIHP3RDISSUECAP1EN => S_AXI_HP3_RDISSUECAP1_EN,
SAXIHP3RID(5 downto 0) => S_AXI_HP3_RID(5 downto 0),
SAXIHP3RLAST => S_AXI_HP3_RLAST,
SAXIHP3RREADY => S_AXI_HP3_RREADY,
SAXIHP3RRESP(1 downto 0) => S_AXI_HP3_RRESP(1 downto 0),
SAXIHP3RVALID => S_AXI_HP3_RVALID,
SAXIHP3WACOUNT(5 downto 0) => S_AXI_HP3_WACOUNT(5 downto 0),
SAXIHP3WCOUNT(7 downto 0) => S_AXI_HP3_WCOUNT(7 downto 0),
SAXIHP3WDATA(63 downto 0) => S_AXI_HP3_WDATA(63 downto 0),
SAXIHP3WID(5 downto 0) => S_AXI_HP3_WID(5 downto 0),
SAXIHP3WLAST => S_AXI_HP3_WLAST,
SAXIHP3WREADY => S_AXI_HP3_WREADY,
SAXIHP3WRISSUECAP1EN => S_AXI_HP3_WRISSUECAP1_EN,
SAXIHP3WSTRB(7 downto 0) => S_AXI_HP3_WSTRB(7 downto 0),
SAXIHP3WVALID => S_AXI_HP3_WVALID
);
PS_CLK_BIBUF: unisim.vcomponents.BIBUF
port map (
IO => buffered_PS_CLK,
PAD => PS_CLK
);
PS_PORB_BIBUF: unisim.vcomponents.BIBUF
port map (
IO => buffered_PS_PORB,
PAD => PS_PORB
);
PS_SRSTB_BIBUF: unisim.vcomponents.BIBUF
port map (
IO => buffered_PS_SRSTB,
PAD => PS_SRSTB
);
SDIO0_CMD_T_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => SDIO0_CMD_T_n,
O => SDIO0_CMD_T
);
\SDIO0_DATA_T[0]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => SDIO0_DATA_T_n(0),
O => SDIO0_DATA_T(0)
);
\SDIO0_DATA_T[1]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => SDIO0_DATA_T_n(1),
O => SDIO0_DATA_T(1)
);
\SDIO0_DATA_T[2]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => SDIO0_DATA_T_n(2),
O => SDIO0_DATA_T(2)
);
\SDIO0_DATA_T[3]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => SDIO0_DATA_T_n(3),
O => SDIO0_DATA_T(3)
);
SDIO1_CMD_T_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => SDIO1_CMD_T_n,
O => SDIO1_CMD_T
);
\SDIO1_DATA_T[0]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => SDIO1_DATA_T_n(0),
O => SDIO1_DATA_T(0)
);
\SDIO1_DATA_T[1]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => SDIO1_DATA_T_n(1),
O => SDIO1_DATA_T(1)
);
\SDIO1_DATA_T[2]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => SDIO1_DATA_T_n(2),
O => SDIO1_DATA_T(2)
);
\SDIO1_DATA_T[3]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => SDIO1_DATA_T_n(3),
O => SDIO1_DATA_T(3)
);
SPI0_MISO_T_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => SPI0_MISO_T_n,
O => SPI0_MISO_T
);
SPI0_MOSI_T_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => SPI0_MOSI_T_n,
O => SPI0_MOSI_T
);
SPI0_SCLK_T_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => SPI0_SCLK_T_n,
O => SPI0_SCLK_T
);
SPI0_SS_T_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => SPI0_SS_T_n,
O => SPI0_SS_T
);
SPI1_MISO_T_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => SPI1_MISO_T_n,
O => SPI1_MISO_T
);
SPI1_MOSI_T_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => SPI1_MOSI_T_n,
O => SPI1_MOSI_T
);
SPI1_SCLK_T_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => SPI1_SCLK_T_n,
O => SPI1_SCLK_T
);
SPI1_SS_T_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => SPI1_SS_T_n,
O => SPI1_SS_T
);
VCC: unisim.vcomponents.VCC
port map (
P => \<const1>\
);
\buffer_fclk_clk_0.FCLK_CLK_0_BUFG\: unisim.vcomponents.BUFG
port map (
I => FCLK_CLK_unbuffered(0),
O => FCLK_CLK0
);
\genblk13[0].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(0),
PAD => MIO(0)
);
\genblk13[10].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(10),
PAD => MIO(10)
);
\genblk13[11].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(11),
PAD => MIO(11)
);
\genblk13[12].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(12),
PAD => MIO(12)
);
\genblk13[13].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(13),
PAD => MIO(13)
);
\genblk13[14].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(14),
PAD => MIO(14)
);
\genblk13[15].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(15),
PAD => MIO(15)
);
\genblk13[16].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(16),
PAD => MIO(16)
);
\genblk13[17].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(17),
PAD => MIO(17)
);
\genblk13[18].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(18),
PAD => MIO(18)
);
\genblk13[19].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(19),
PAD => MIO(19)
);
\genblk13[1].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(1),
PAD => MIO(1)
);
\genblk13[20].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(20),
PAD => MIO(20)
);
\genblk13[21].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(21),
PAD => MIO(21)
);
\genblk13[22].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(22),
PAD => MIO(22)
);
\genblk13[23].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(23),
PAD => MIO(23)
);
\genblk13[24].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(24),
PAD => MIO(24)
);
\genblk13[25].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(25),
PAD => MIO(25)
);
\genblk13[26].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(26),
PAD => MIO(26)
);
\genblk13[27].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(27),
PAD => MIO(27)
);
\genblk13[28].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(28),
PAD => MIO(28)
);
\genblk13[29].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(29),
PAD => MIO(29)
);
\genblk13[2].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(2),
PAD => MIO(2)
);
\genblk13[30].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(30),
PAD => MIO(30)
);
\genblk13[31].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(31),
PAD => MIO(31)
);
\genblk13[32].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(32),
PAD => MIO(32)
);
\genblk13[33].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(33),
PAD => MIO(33)
);
\genblk13[34].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(34),
PAD => MIO(34)
);
\genblk13[35].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(35),
PAD => MIO(35)
);
\genblk13[36].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(36),
PAD => MIO(36)
);
\genblk13[37].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(37),
PAD => MIO(37)
);
\genblk13[38].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(38),
PAD => MIO(38)
);
\genblk13[39].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(39),
PAD => MIO(39)
);
\genblk13[3].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(3),
PAD => MIO(3)
);
\genblk13[40].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(40),
PAD => MIO(40)
);
\genblk13[41].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(41),
PAD => MIO(41)
);
\genblk13[42].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(42),
PAD => MIO(42)
);
\genblk13[43].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(43),
PAD => MIO(43)
);
\genblk13[44].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(44),
PAD => MIO(44)
);
\genblk13[45].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(45),
PAD => MIO(45)
);
\genblk13[46].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(46),
PAD => MIO(46)
);
\genblk13[47].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(47),
PAD => MIO(47)
);
\genblk13[48].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(48),
PAD => MIO(48)
);
\genblk13[49].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(49),
PAD => MIO(49)
);
\genblk13[4].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(4),
PAD => MIO(4)
);
\genblk13[50].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(50),
PAD => MIO(50)
);
\genblk13[51].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(51),
PAD => MIO(51)
);
\genblk13[52].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(52),
PAD => MIO(52)
);
\genblk13[53].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(53),
PAD => MIO(53)
);
\genblk13[5].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(5),
PAD => MIO(5)
);
\genblk13[6].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(6),
PAD => MIO(6)
);
\genblk13[7].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(7),
PAD => MIO(7)
);
\genblk13[8].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(8),
PAD => MIO(8)
);
\genblk13[9].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(9),
PAD => MIO(9)
);
\genblk14[0].DDR_BankAddr_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_BankAddr(0),
PAD => DDR_BankAddr(0)
);
\genblk14[1].DDR_BankAddr_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_BankAddr(1),
PAD => DDR_BankAddr(1)
);
\genblk14[2].DDR_BankAddr_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_BankAddr(2),
PAD => DDR_BankAddr(2)
);
\genblk15[0].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_Addr(0),
PAD => DDR_Addr(0)
);
\genblk15[10].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_Addr(10),
PAD => DDR_Addr(10)
);
\genblk15[11].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_Addr(11),
PAD => DDR_Addr(11)
);
\genblk15[12].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_Addr(12),
PAD => DDR_Addr(12)
);
\genblk15[13].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_Addr(13),
PAD => DDR_Addr(13)
);
\genblk15[14].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_Addr(14),
PAD => DDR_Addr(14)
);
\genblk15[1].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_Addr(1),
PAD => DDR_Addr(1)
);
\genblk15[2].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_Addr(2),
PAD => DDR_Addr(2)
);
\genblk15[3].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_Addr(3),
PAD => DDR_Addr(3)
);
\genblk15[4].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_Addr(4),
PAD => DDR_Addr(4)
);
\genblk15[5].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_Addr(5),
PAD => DDR_Addr(5)
);
\genblk15[6].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_Addr(6),
PAD => DDR_Addr(6)
);
\genblk15[7].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_Addr(7),
PAD => DDR_Addr(7)
);
\genblk15[8].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_Addr(8),
PAD => DDR_Addr(8)
);
\genblk15[9].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_Addr(9),
PAD => DDR_Addr(9)
);
\genblk16[0].DDR_DM_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DM(0),
PAD => DDR_DM(0)
);
\genblk16[1].DDR_DM_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DM(1),
PAD => DDR_DM(1)
);
\genblk16[2].DDR_DM_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DM(2),
PAD => DDR_DM(2)
);
\genblk16[3].DDR_DM_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DM(3),
PAD => DDR_DM(3)
);
\genblk17[0].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(0),
PAD => DDR_DQ(0)
);
\genblk17[10].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(10),
PAD => DDR_DQ(10)
);
\genblk17[11].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(11),
PAD => DDR_DQ(11)
);
\genblk17[12].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(12),
PAD => DDR_DQ(12)
);
\genblk17[13].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(13),
PAD => DDR_DQ(13)
);
\genblk17[14].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(14),
PAD => DDR_DQ(14)
);
\genblk17[15].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(15),
PAD => DDR_DQ(15)
);
\genblk17[16].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(16),
PAD => DDR_DQ(16)
);
\genblk17[17].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(17),
PAD => DDR_DQ(17)
);
\genblk17[18].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(18),
PAD => DDR_DQ(18)
);
\genblk17[19].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(19),
PAD => DDR_DQ(19)
);
\genblk17[1].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(1),
PAD => DDR_DQ(1)
);
\genblk17[20].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(20),
PAD => DDR_DQ(20)
);
\genblk17[21].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(21),
PAD => DDR_DQ(21)
);
\genblk17[22].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(22),
PAD => DDR_DQ(22)
);
\genblk17[23].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(23),
PAD => DDR_DQ(23)
);
\genblk17[24].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(24),
PAD => DDR_DQ(24)
);
\genblk17[25].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(25),
PAD => DDR_DQ(25)
);
\genblk17[26].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(26),
PAD => DDR_DQ(26)
);
\genblk17[27].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(27),
PAD => DDR_DQ(27)
);
\genblk17[28].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(28),
PAD => DDR_DQ(28)
);
\genblk17[29].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(29),
PAD => DDR_DQ(29)
);
\genblk17[2].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(2),
PAD => DDR_DQ(2)
);
\genblk17[30].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(30),
PAD => DDR_DQ(30)
);
\genblk17[31].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(31),
PAD => DDR_DQ(31)
);
\genblk17[3].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(3),
PAD => DDR_DQ(3)
);
\genblk17[4].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(4),
PAD => DDR_DQ(4)
);
\genblk17[5].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(5),
PAD => DDR_DQ(5)
);
\genblk17[6].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(6),
PAD => DDR_DQ(6)
);
\genblk17[7].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(7),
PAD => DDR_DQ(7)
);
\genblk17[8].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(8),
PAD => DDR_DQ(8)
);
\genblk17[9].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(9),
PAD => DDR_DQ(9)
);
\genblk18[0].DDR_DQS_n_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQS_n(0),
PAD => DDR_DQS_n(0)
);
\genblk18[1].DDR_DQS_n_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQS_n(1),
PAD => DDR_DQS_n(1)
);
\genblk18[2].DDR_DQS_n_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQS_n(2),
PAD => DDR_DQS_n(2)
);
\genblk18[3].DDR_DQS_n_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQS_n(3),
PAD => DDR_DQS_n(3)
);
\genblk19[0].DDR_DQS_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQS(0),
PAD => DDR_DQS(0)
);
\genblk19[1].DDR_DQS_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQS(1),
PAD => DDR_DQS(1)
);
\genblk19[2].DDR_DQS_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQS(2),
PAD => DDR_DQS(2)
);
\genblk19[3].DDR_DQS_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQS(3),
PAD => DDR_DQS(3)
);
i_0: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_CTL_PIPE[0]\
);
i_1: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_DATA_PIPE[0]\(1)
);
i_10: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_DATA_PIPE[7]\(1)
);
i_11: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_DATA_PIPE[7]\(0)
);
i_12: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_DATA_PIPE[6]\(1)
);
i_13: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_DATA_PIPE[6]\(0)
);
i_14: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_DATA_PIPE[5]\(1)
);
i_15: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_DATA_PIPE[5]\(0)
);
i_16: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_DATA_PIPE[4]\(1)
);
i_17: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_DATA_PIPE[4]\(0)
);
i_18: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_DATA_PIPE[3]\(1)
);
i_19: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_DATA_PIPE[3]\(0)
);
i_2: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_DATA_PIPE[0]\(0)
);
i_20: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_DATA_PIPE[2]\(1)
);
i_21: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_DATA_PIPE[2]\(0)
);
i_22: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_DATA_PIPE[1]\(1)
);
i_23: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_DATA_PIPE[1]\(0)
);
i_3: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_CTL_PIPE[7]\
);
i_4: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_CTL_PIPE[6]\
);
i_5: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_CTL_PIPE[5]\
);
i_6: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_CTL_PIPE[4]\
);
i_7: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_CTL_PIPE[3]\
);
i_8: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_CTL_PIPE[2]\
);
i_9: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_CTL_PIPE[1]\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_processing_system7_0_2 is
port (
USB0_PORT_INDCTL : out STD_LOGIC_VECTOR ( 1 downto 0 );
USB0_VBUS_PWRSELECT : out STD_LOGIC;
USB0_VBUS_PWRFAULT : in STD_LOGIC;
M_AXI_GP0_ARVALID : out STD_LOGIC;
M_AXI_GP0_AWVALID : out STD_LOGIC;
M_AXI_GP0_BREADY : out STD_LOGIC;
M_AXI_GP0_RREADY : out STD_LOGIC;
M_AXI_GP0_WLAST : out STD_LOGIC;
M_AXI_GP0_WVALID : out STD_LOGIC;
M_AXI_GP0_ARID : out STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_AWID : out STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_WID : out STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_ARBURST : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_ARLOCK : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_ARSIZE : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP0_AWBURST : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_AWLOCK : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_AWSIZE : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP0_ARPROT : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP0_AWPROT : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP0_ARADDR : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_GP0_AWADDR : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_GP0_WDATA : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_GP0_ARCACHE : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_ARLEN : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_ARQOS : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_AWCACHE : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_AWLEN : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_AWQOS : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_WSTRB : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_ACLK : in STD_LOGIC;
M_AXI_GP0_ARREADY : in STD_LOGIC;
M_AXI_GP0_AWREADY : in STD_LOGIC;
M_AXI_GP0_BVALID : in STD_LOGIC;
M_AXI_GP0_RLAST : in STD_LOGIC;
M_AXI_GP0_RVALID : in STD_LOGIC;
M_AXI_GP0_WREADY : in STD_LOGIC;
M_AXI_GP0_BID : in STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_RID : in STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_BRESP : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_RRESP : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_RDATA : in STD_LOGIC_VECTOR ( 31 downto 0 );
IRQ_F2P : in STD_LOGIC_VECTOR ( 0 to 0 );
FCLK_CLK0 : out STD_LOGIC;
FCLK_RESET0_N : out STD_LOGIC;
MIO : inout STD_LOGIC_VECTOR ( 53 downto 0 );
DDR_CAS_n : inout STD_LOGIC;
DDR_CKE : inout STD_LOGIC;
DDR_Clk_n : inout STD_LOGIC;
DDR_Clk : inout STD_LOGIC;
DDR_CS_n : inout STD_LOGIC;
DDR_DRSTB : inout STD_LOGIC;
DDR_ODT : inout STD_LOGIC;
DDR_RAS_n : inout STD_LOGIC;
DDR_WEB : inout STD_LOGIC;
DDR_BankAddr : inout STD_LOGIC_VECTOR ( 2 downto 0 );
DDR_Addr : inout STD_LOGIC_VECTOR ( 14 downto 0 );
DDR_VRN : inout STD_LOGIC;
DDR_VRP : inout STD_LOGIC;
DDR_DM : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_DQ : inout STD_LOGIC_VECTOR ( 31 downto 0 );
DDR_DQS_n : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_DQS : inout STD_LOGIC_VECTOR ( 3 downto 0 );
PS_SRSTB : inout STD_LOGIC;
PS_CLK : inout STD_LOGIC;
PS_PORB : inout STD_LOGIC
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of design_1_processing_system7_0_2 : entity is true;
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of design_1_processing_system7_0_2 : entity is "design_1_processing_system7_0_2,processing_system7_v5_5_processing_system7,{}";
attribute DowngradeIPIdentifiedWarnings : string;
attribute DowngradeIPIdentifiedWarnings of design_1_processing_system7_0_2 : entity is "yes";
attribute X_CORE_INFO : string;
attribute X_CORE_INFO of design_1_processing_system7_0_2 : entity is "processing_system7_v5_5_processing_system7,Vivado 2018.2";
end design_1_processing_system7_0_2;
architecture STRUCTURE of design_1_processing_system7_0_2 is
signal NLW_inst_CAN0_PHY_TX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_CAN1_PHY_TX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_DMA0_DAVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_DMA0_DRREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_DMA0_RSTN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_DMA1_DAVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_DMA1_DRREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_DMA1_RSTN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_DMA2_DAVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_DMA2_DRREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_DMA2_RSTN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_DMA3_DAVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_DMA3_DRREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_DMA3_RSTN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET0_GMII_TX_EN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET0_GMII_TX_ER_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET0_MDIO_MDC_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET0_MDIO_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET0_MDIO_T_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET0_PTP_DELAY_REQ_RX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET0_PTP_DELAY_REQ_TX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET0_PTP_PDELAY_REQ_RX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET0_PTP_PDELAY_REQ_TX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET0_PTP_PDELAY_RESP_RX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET0_PTP_PDELAY_RESP_TX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET0_PTP_SYNC_FRAME_RX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET0_PTP_SYNC_FRAME_TX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET0_SOF_RX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET0_SOF_TX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET1_GMII_TX_EN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET1_GMII_TX_ER_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET1_MDIO_MDC_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET1_MDIO_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET1_MDIO_T_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET1_PTP_DELAY_REQ_RX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET1_PTP_DELAY_REQ_TX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET1_PTP_PDELAY_REQ_RX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET1_PTP_PDELAY_REQ_TX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET1_PTP_PDELAY_RESP_RX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET1_PTP_PDELAY_RESP_TX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET1_PTP_SYNC_FRAME_RX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET1_PTP_SYNC_FRAME_TX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET1_SOF_RX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET1_SOF_TX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_EVENT_EVENTO_UNCONNECTED : STD_LOGIC;
signal NLW_inst_FCLK_CLK1_UNCONNECTED : STD_LOGIC;
signal NLW_inst_FCLK_CLK2_UNCONNECTED : STD_LOGIC;
signal NLW_inst_FCLK_CLK3_UNCONNECTED : STD_LOGIC;
signal NLW_inst_FCLK_RESET1_N_UNCONNECTED : STD_LOGIC;
signal NLW_inst_FCLK_RESET2_N_UNCONNECTED : STD_LOGIC;
signal NLW_inst_FCLK_RESET3_N_UNCONNECTED : STD_LOGIC;
signal NLW_inst_FTMT_F2P_TRIGACK_0_UNCONNECTED : STD_LOGIC;
signal NLW_inst_FTMT_F2P_TRIGACK_1_UNCONNECTED : STD_LOGIC;
signal NLW_inst_FTMT_F2P_TRIGACK_2_UNCONNECTED : STD_LOGIC;
signal NLW_inst_FTMT_F2P_TRIGACK_3_UNCONNECTED : STD_LOGIC;
signal NLW_inst_FTMT_P2F_TRIG_0_UNCONNECTED : STD_LOGIC;
signal NLW_inst_FTMT_P2F_TRIG_1_UNCONNECTED : STD_LOGIC;
signal NLW_inst_FTMT_P2F_TRIG_2_UNCONNECTED : STD_LOGIC;
signal NLW_inst_FTMT_P2F_TRIG_3_UNCONNECTED : STD_LOGIC;
signal NLW_inst_I2C0_SCL_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_I2C0_SCL_T_UNCONNECTED : STD_LOGIC;
signal NLW_inst_I2C0_SDA_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_I2C0_SDA_T_UNCONNECTED : STD_LOGIC;
signal NLW_inst_I2C1_SCL_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_I2C1_SCL_T_UNCONNECTED : STD_LOGIC;
signal NLW_inst_I2C1_SDA_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_I2C1_SDA_T_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_CAN0_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_CAN1_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_CTI_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_DMAC0_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_DMAC1_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_DMAC2_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_DMAC3_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_DMAC4_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_DMAC5_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_DMAC6_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_DMAC7_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_DMAC_ABORT_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_ENET0_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_ENET1_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_ENET_WAKE0_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_ENET_WAKE1_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_GPIO_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_I2C0_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_I2C1_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_QSPI_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_SDIO0_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_SDIO1_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_SMC_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_SPI0_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_SPI1_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_UART0_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_UART1_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_USB0_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_USB1_UNCONNECTED : STD_LOGIC;
signal NLW_inst_M_AXI_GP0_ARESETN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_M_AXI_GP1_ARESETN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_M_AXI_GP1_ARVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_M_AXI_GP1_AWVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_M_AXI_GP1_BREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_M_AXI_GP1_RREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_M_AXI_GP1_WLAST_UNCONNECTED : STD_LOGIC;
signal NLW_inst_M_AXI_GP1_WVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_PJTAG_TDO_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SDIO0_BUSPOW_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SDIO0_CLK_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SDIO0_CMD_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SDIO0_CMD_T_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SDIO0_LED_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SDIO1_BUSPOW_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SDIO1_CLK_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SDIO1_CMD_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SDIO1_CMD_T_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SDIO1_LED_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI0_MISO_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI0_MISO_T_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI0_MOSI_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI0_MOSI_T_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI0_SCLK_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI0_SCLK_T_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI0_SS1_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI0_SS2_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI0_SS_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI0_SS_T_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI1_MISO_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI1_MISO_T_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI1_MOSI_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI1_MOSI_T_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI1_SCLK_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI1_SCLK_T_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI1_SS1_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI1_SS2_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI1_SS_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI1_SS_T_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_ACP_ARESETN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_ACP_ARREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_ACP_AWREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_ACP_BVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_ACP_RLAST_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_ACP_RVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_ACP_WREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_GP0_ARESETN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_GP0_ARREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_GP0_AWREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_GP0_BVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_GP0_RLAST_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_GP0_RVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_GP0_WREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_GP1_ARESETN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_GP1_ARREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_GP1_AWREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_GP1_BVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_GP1_RLAST_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_GP1_RVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_GP1_WREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP0_ARESETN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP0_ARREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP0_AWREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP0_BVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP0_RLAST_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP0_RVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP0_WREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP1_ARESETN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP1_ARREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP1_AWREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP1_BVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP1_RLAST_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP1_RVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP1_WREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP2_ARESETN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP2_ARREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP2_AWREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP2_BVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP2_RLAST_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP2_RVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP2_WREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP3_ARESETN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP3_ARREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP3_AWREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP3_BVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP3_RLAST_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP3_RVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP3_WREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_TRACE_CLK_OUT_UNCONNECTED : STD_LOGIC;
signal NLW_inst_TRACE_CTL_UNCONNECTED : STD_LOGIC;
signal NLW_inst_TTC0_WAVE0_OUT_UNCONNECTED : STD_LOGIC;
signal NLW_inst_TTC0_WAVE1_OUT_UNCONNECTED : STD_LOGIC;
signal NLW_inst_TTC0_WAVE2_OUT_UNCONNECTED : STD_LOGIC;
signal NLW_inst_TTC1_WAVE0_OUT_UNCONNECTED : STD_LOGIC;
signal NLW_inst_TTC1_WAVE1_OUT_UNCONNECTED : STD_LOGIC;
signal NLW_inst_TTC1_WAVE2_OUT_UNCONNECTED : STD_LOGIC;
signal NLW_inst_UART0_DTRN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_UART0_RTSN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_UART0_TX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_UART1_DTRN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_UART1_RTSN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_UART1_TX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_USB1_VBUS_PWRSELECT_UNCONNECTED : STD_LOGIC;
signal NLW_inst_WDT_RST_OUT_UNCONNECTED : STD_LOGIC;
signal NLW_inst_DMA0_DATYPE_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_DMA1_DATYPE_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_DMA2_DATYPE_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_DMA3_DATYPE_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_ENET0_GMII_TXD_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_inst_ENET1_GMII_TXD_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_inst_EVENT_STANDBYWFE_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_EVENT_STANDBYWFI_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_FTMT_P2F_DEBUG_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_inst_GPIO_O_UNCONNECTED : STD_LOGIC_VECTOR ( 63 downto 0 );
signal NLW_inst_GPIO_T_UNCONNECTED : STD_LOGIC_VECTOR ( 63 downto 0 );
signal NLW_inst_M_AXI_GP1_ARADDR_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_inst_M_AXI_GP1_ARBURST_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_M_AXI_GP1_ARCACHE_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_inst_M_AXI_GP1_ARID_UNCONNECTED : STD_LOGIC_VECTOR ( 11 downto 0 );
signal NLW_inst_M_AXI_GP1_ARLEN_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_inst_M_AXI_GP1_ARLOCK_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_M_AXI_GP1_ARPROT_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_inst_M_AXI_GP1_ARQOS_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_inst_M_AXI_GP1_ARSIZE_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_inst_M_AXI_GP1_AWADDR_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_inst_M_AXI_GP1_AWBURST_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_M_AXI_GP1_AWCACHE_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_inst_M_AXI_GP1_AWID_UNCONNECTED : STD_LOGIC_VECTOR ( 11 downto 0 );
signal NLW_inst_M_AXI_GP1_AWLEN_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_inst_M_AXI_GP1_AWLOCK_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_M_AXI_GP1_AWPROT_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_inst_M_AXI_GP1_AWQOS_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_inst_M_AXI_GP1_AWSIZE_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_inst_M_AXI_GP1_WDATA_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_inst_M_AXI_GP1_WID_UNCONNECTED : STD_LOGIC_VECTOR ( 11 downto 0 );
signal NLW_inst_M_AXI_GP1_WSTRB_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_inst_SDIO0_BUSVOLT_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_inst_SDIO0_DATA_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_inst_SDIO0_DATA_T_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_inst_SDIO1_BUSVOLT_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_inst_SDIO1_DATA_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_inst_SDIO1_DATA_T_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_inst_S_AXI_ACP_BID_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_inst_S_AXI_ACP_BRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_S_AXI_ACP_RDATA_UNCONNECTED : STD_LOGIC_VECTOR ( 63 downto 0 );
signal NLW_inst_S_AXI_ACP_RID_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_inst_S_AXI_ACP_RRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_S_AXI_GP0_BID_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_inst_S_AXI_GP0_BRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_S_AXI_GP0_RDATA_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_inst_S_AXI_GP0_RID_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_inst_S_AXI_GP0_RRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_S_AXI_GP1_BID_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_inst_S_AXI_GP1_BRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_S_AXI_GP1_RDATA_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_inst_S_AXI_GP1_RID_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_inst_S_AXI_GP1_RRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_S_AXI_HP0_BID_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_inst_S_AXI_HP0_BRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_S_AXI_HP0_RACOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_inst_S_AXI_HP0_RCOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_inst_S_AXI_HP0_RDATA_UNCONNECTED : STD_LOGIC_VECTOR ( 63 downto 0 );
signal NLW_inst_S_AXI_HP0_RID_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_inst_S_AXI_HP0_RRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_S_AXI_HP0_WACOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_inst_S_AXI_HP0_WCOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_inst_S_AXI_HP1_BID_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_inst_S_AXI_HP1_BRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_S_AXI_HP1_RACOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_inst_S_AXI_HP1_RCOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_inst_S_AXI_HP1_RDATA_UNCONNECTED : STD_LOGIC_VECTOR ( 63 downto 0 );
signal NLW_inst_S_AXI_HP1_RID_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_inst_S_AXI_HP1_RRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_S_AXI_HP1_WACOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_inst_S_AXI_HP1_WCOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_inst_S_AXI_HP2_BID_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_inst_S_AXI_HP2_BRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_S_AXI_HP2_RACOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_inst_S_AXI_HP2_RCOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_inst_S_AXI_HP2_RDATA_UNCONNECTED : STD_LOGIC_VECTOR ( 63 downto 0 );
signal NLW_inst_S_AXI_HP2_RID_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_inst_S_AXI_HP2_RRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_S_AXI_HP2_WACOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_inst_S_AXI_HP2_WCOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_inst_S_AXI_HP3_BID_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_inst_S_AXI_HP3_BRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_S_AXI_HP3_RACOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_inst_S_AXI_HP3_RCOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_inst_S_AXI_HP3_RDATA_UNCONNECTED : STD_LOGIC_VECTOR ( 63 downto 0 );
signal NLW_inst_S_AXI_HP3_RID_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_inst_S_AXI_HP3_RRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_S_AXI_HP3_WACOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_inst_S_AXI_HP3_WCOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_inst_TRACE_DATA_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_USB1_PORT_INDCTL_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute C_DM_WIDTH : integer;
attribute C_DM_WIDTH of inst : label is 4;
attribute C_DQS_WIDTH : integer;
attribute C_DQS_WIDTH of inst : label is 4;
attribute C_DQ_WIDTH : integer;
attribute C_DQ_WIDTH of inst : label is 32;
attribute C_EMIO_GPIO_WIDTH : integer;
attribute C_EMIO_GPIO_WIDTH of inst : label is 64;
attribute C_EN_EMIO_ENET0 : integer;
attribute C_EN_EMIO_ENET0 of inst : label is 0;
attribute C_EN_EMIO_ENET1 : integer;
attribute C_EN_EMIO_ENET1 of inst : label is 0;
attribute C_EN_EMIO_PJTAG : integer;
attribute C_EN_EMIO_PJTAG of inst : label is 0;
attribute C_EN_EMIO_TRACE : integer;
attribute C_EN_EMIO_TRACE of inst : label is 0;
attribute C_FCLK_CLK0_BUF : string;
attribute C_FCLK_CLK0_BUF of inst : label is "TRUE";
attribute C_FCLK_CLK1_BUF : string;
attribute C_FCLK_CLK1_BUF of inst : label is "FALSE";
attribute C_FCLK_CLK2_BUF : string;
attribute C_FCLK_CLK2_BUF of inst : label is "FALSE";
attribute C_FCLK_CLK3_BUF : string;
attribute C_FCLK_CLK3_BUF of inst : label is "FALSE";
attribute C_GP0_EN_MODIFIABLE_TXN : integer;
attribute C_GP0_EN_MODIFIABLE_TXN of inst : label is 1;
attribute C_GP1_EN_MODIFIABLE_TXN : integer;
attribute C_GP1_EN_MODIFIABLE_TXN of inst : label is 1;
attribute C_INCLUDE_ACP_TRANS_CHECK : integer;
attribute C_INCLUDE_ACP_TRANS_CHECK of inst : label is 0;
attribute C_INCLUDE_TRACE_BUFFER : integer;
attribute C_INCLUDE_TRACE_BUFFER of inst : label is 0;
attribute C_IRQ_F2P_MODE : string;
attribute C_IRQ_F2P_MODE of inst : label is "DIRECT";
attribute C_MIO_PRIMITIVE : integer;
attribute C_MIO_PRIMITIVE of inst : label is 54;
attribute C_M_AXI_GP0_ENABLE_STATIC_REMAP : integer;
attribute C_M_AXI_GP0_ENABLE_STATIC_REMAP of inst : label is 0;
attribute C_M_AXI_GP0_ID_WIDTH : integer;
attribute C_M_AXI_GP0_ID_WIDTH of inst : label is 12;
attribute C_M_AXI_GP0_THREAD_ID_WIDTH : integer;
attribute C_M_AXI_GP0_THREAD_ID_WIDTH of inst : label is 12;
attribute C_M_AXI_GP1_ENABLE_STATIC_REMAP : integer;
attribute C_M_AXI_GP1_ENABLE_STATIC_REMAP of inst : label is 0;
attribute C_M_AXI_GP1_ID_WIDTH : integer;
attribute C_M_AXI_GP1_ID_WIDTH of inst : label is 12;
attribute C_M_AXI_GP1_THREAD_ID_WIDTH : integer;
attribute C_M_AXI_GP1_THREAD_ID_WIDTH of inst : label is 12;
attribute C_NUM_F2P_INTR_INPUTS : integer;
attribute C_NUM_F2P_INTR_INPUTS of inst : label is 1;
attribute C_PACKAGE_NAME : string;
attribute C_PACKAGE_NAME of inst : label is "clg400";
attribute C_PS7_SI_REV : string;
attribute C_PS7_SI_REV of inst : label is "PRODUCTION";
attribute C_S_AXI_ACP_ARUSER_VAL : integer;
attribute C_S_AXI_ACP_ARUSER_VAL of inst : label is 31;
attribute C_S_AXI_ACP_AWUSER_VAL : integer;
attribute C_S_AXI_ACP_AWUSER_VAL of inst : label is 31;
attribute C_S_AXI_ACP_ID_WIDTH : integer;
attribute C_S_AXI_ACP_ID_WIDTH of inst : label is 3;
attribute C_S_AXI_GP0_ID_WIDTH : integer;
attribute C_S_AXI_GP0_ID_WIDTH of inst : label is 6;
attribute C_S_AXI_GP1_ID_WIDTH : integer;
attribute C_S_AXI_GP1_ID_WIDTH of inst : label is 6;
attribute C_S_AXI_HP0_DATA_WIDTH : integer;
attribute C_S_AXI_HP0_DATA_WIDTH of inst : label is 64;
attribute C_S_AXI_HP0_ID_WIDTH : integer;
attribute C_S_AXI_HP0_ID_WIDTH of inst : label is 6;
attribute C_S_AXI_HP1_DATA_WIDTH : integer;
attribute C_S_AXI_HP1_DATA_WIDTH of inst : label is 64;
attribute C_S_AXI_HP1_ID_WIDTH : integer;
attribute C_S_AXI_HP1_ID_WIDTH of inst : label is 6;
attribute C_S_AXI_HP2_DATA_WIDTH : integer;
attribute C_S_AXI_HP2_DATA_WIDTH of inst : label is 64;
attribute C_S_AXI_HP2_ID_WIDTH : integer;
attribute C_S_AXI_HP2_ID_WIDTH of inst : label is 6;
attribute C_S_AXI_HP3_DATA_WIDTH : integer;
attribute C_S_AXI_HP3_DATA_WIDTH of inst : label is 64;
attribute C_S_AXI_HP3_ID_WIDTH : integer;
attribute C_S_AXI_HP3_ID_WIDTH of inst : label is 6;
attribute C_TRACE_BUFFER_CLOCK_DELAY : integer;
attribute C_TRACE_BUFFER_CLOCK_DELAY of inst : label is 12;
attribute C_TRACE_BUFFER_FIFO_SIZE : integer;
attribute C_TRACE_BUFFER_FIFO_SIZE of inst : label is 128;
attribute C_TRACE_INTERNAL_WIDTH : integer;
attribute C_TRACE_INTERNAL_WIDTH of inst : label is 2;
attribute C_TRACE_PIPELINE_WIDTH : integer;
attribute C_TRACE_PIPELINE_WIDTH of inst : label is 8;
attribute C_USE_AXI_NONSECURE : integer;
attribute C_USE_AXI_NONSECURE of inst : label is 0;
attribute C_USE_DEFAULT_ACP_USER_VAL : integer;
attribute C_USE_DEFAULT_ACP_USER_VAL of inst : label is 0;
attribute C_USE_M_AXI_GP0 : integer;
attribute C_USE_M_AXI_GP0 of inst : label is 1;
attribute C_USE_M_AXI_GP1 : integer;
attribute C_USE_M_AXI_GP1 of inst : label is 0;
attribute C_USE_S_AXI_ACP : integer;
attribute C_USE_S_AXI_ACP of inst : label is 0;
attribute C_USE_S_AXI_GP0 : integer;
attribute C_USE_S_AXI_GP0 of inst : label is 0;
attribute C_USE_S_AXI_GP1 : integer;
attribute C_USE_S_AXI_GP1 of inst : label is 0;
attribute C_USE_S_AXI_HP0 : integer;
attribute C_USE_S_AXI_HP0 of inst : label is 0;
attribute C_USE_S_AXI_HP1 : integer;
attribute C_USE_S_AXI_HP1 of inst : label is 0;
attribute C_USE_S_AXI_HP2 : integer;
attribute C_USE_S_AXI_HP2 of inst : label is 0;
attribute C_USE_S_AXI_HP3 : integer;
attribute C_USE_S_AXI_HP3 of inst : label is 0;
attribute HW_HANDOFF : string;
attribute HW_HANDOFF of inst : label is "design_1_processing_system7_0_2.hwdef";
attribute POWER : string;
attribute POWER of inst : label is "<PROCESSOR name={system} numA9Cores={2} clockFreq={667} load={0.5} /><MEMORY name={code} memType={DDR3(LowVoltage)} dataWidth={32} clockFreq={533.333333} readRate={0.5} writeRate={0.5} /><IO interface={GPIO_Bank_1} ioStandard={LVCMOS18} bidis={2} ioBank={Vcco_p1} clockFreq={1} usageRate={0.5} /><IO interface={GPIO_Bank_0} ioStandard={LVCMOS33} bidis={9} ioBank={Vcco_p0} clockFreq={1} usageRate={0.5} /><IO interface={UART} ioStandard={LVCMOS18} bidis={2} ioBank={Vcco_p1} clockFreq={100.000000} usageRate={0.5} /><IO interface={SD} ioStandard={LVCMOS18} bidis={7} ioBank={Vcco_p1} clockFreq={50.000000} usageRate={0.5} /><IO interface={USB} ioStandard={LVCMOS18} bidis={12} ioBank={Vcco_p1} clockFreq={60} usageRate={0.5} /><IO interface={GigE} ioStandard={LVCMOS18} bidis={14} ioBank={Vcco_p1} clockFreq={125.000000} usageRate={0.5} /><IO interface={QSPI} ioStandard={LVCMOS33} bidis={7} ioBank={Vcco_p0} clockFreq={200} usageRate={0.5} /><PLL domain={Processor} vco={1333.333} /><PLL domain={Memory} vco={1066.667} /><PLL domain={IO} vco={1000.000} /><AXI interface={M_AXI_GP0} dataWidth={32} clockFreq={50} usageRate={0.5} />/>";
attribute USE_TRACE_DATA_EDGE_DETECTOR : integer;
attribute USE_TRACE_DATA_EDGE_DETECTOR of inst : label is 0;
attribute X_INTERFACE_INFO : string;
attribute X_INTERFACE_INFO of DDR_CAS_n : signal is "xilinx.com:interface:ddrx:1.0 DDR CAS_N";
attribute X_INTERFACE_INFO of DDR_CKE : signal is "xilinx.com:interface:ddrx:1.0 DDR CKE";
attribute X_INTERFACE_INFO of DDR_CS_n : signal is "xilinx.com:interface:ddrx:1.0 DDR CS_N";
attribute X_INTERFACE_INFO of DDR_Clk : signal is "xilinx.com:interface:ddrx:1.0 DDR CK_P";
attribute X_INTERFACE_INFO of DDR_Clk_n : signal is "xilinx.com:interface:ddrx:1.0 DDR CK_N";
attribute X_INTERFACE_INFO of DDR_DRSTB : signal is "xilinx.com:interface:ddrx:1.0 DDR RESET_N";
attribute X_INTERFACE_INFO of DDR_ODT : signal is "xilinx.com:interface:ddrx:1.0 DDR ODT";
attribute X_INTERFACE_INFO of DDR_RAS_n : signal is "xilinx.com:interface:ddrx:1.0 DDR RAS_N";
attribute X_INTERFACE_INFO of DDR_VRN : signal is "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO DDR_VRN";
attribute X_INTERFACE_INFO of DDR_VRP : signal is "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO DDR_VRP";
attribute X_INTERFACE_INFO of DDR_WEB : signal is "xilinx.com:interface:ddrx:1.0 DDR WE_N";
attribute X_INTERFACE_INFO of FCLK_CLK0 : signal is "xilinx.com:signal:clock:1.0 FCLK_CLK0 CLK";
attribute X_INTERFACE_PARAMETER : string;
attribute X_INTERFACE_PARAMETER of FCLK_CLK0 : signal is "XIL_INTERFACENAME FCLK_CLK0, FREQ_HZ 50000000, PHASE 0.000, CLK_DOMAIN design_1_processing_system7_0_2_FCLK_CLK0";
attribute X_INTERFACE_INFO of FCLK_RESET0_N : signal is "xilinx.com:signal:reset:1.0 FCLK_RESET0_N RST";
attribute X_INTERFACE_PARAMETER of FCLK_RESET0_N : signal is "XIL_INTERFACENAME FCLK_RESET0_N, POLARITY ACTIVE_LOW";
attribute X_INTERFACE_INFO of M_AXI_GP0_ACLK : signal is "xilinx.com:signal:clock:1.0 M_AXI_GP0_ACLK CLK";
attribute X_INTERFACE_PARAMETER of M_AXI_GP0_ACLK : signal is "XIL_INTERFACENAME M_AXI_GP0_ACLK, ASSOCIATED_BUSIF M_AXI_GP0, FREQ_HZ 50000000, PHASE 0.000, CLK_DOMAIN design_1_processing_system7_0_2_FCLK_CLK0";
attribute X_INTERFACE_INFO of M_AXI_GP0_ARREADY : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARREADY";
attribute X_INTERFACE_INFO of M_AXI_GP0_ARVALID : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARVALID";
attribute X_INTERFACE_INFO of M_AXI_GP0_AWREADY : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWREADY";
attribute X_INTERFACE_INFO of M_AXI_GP0_AWVALID : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWVALID";
attribute X_INTERFACE_INFO of M_AXI_GP0_BREADY : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 BREADY";
attribute X_INTERFACE_INFO of M_AXI_GP0_BVALID : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 BVALID";
attribute X_INTERFACE_INFO of M_AXI_GP0_RLAST : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 RLAST";
attribute X_INTERFACE_INFO of M_AXI_GP0_RREADY : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 RREADY";
attribute X_INTERFACE_INFO of M_AXI_GP0_RVALID : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 RVALID";
attribute X_INTERFACE_INFO of M_AXI_GP0_WLAST : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 WLAST";
attribute X_INTERFACE_INFO of M_AXI_GP0_WREADY : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 WREADY";
attribute X_INTERFACE_INFO of M_AXI_GP0_WVALID : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 WVALID";
attribute X_INTERFACE_INFO of PS_CLK : signal is "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO PS_CLK";
attribute X_INTERFACE_INFO of PS_PORB : signal is "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO PS_PORB";
attribute X_INTERFACE_PARAMETER of PS_PORB : signal is "XIL_INTERFACENAME FIXED_IO, CAN_DEBUG false";
attribute X_INTERFACE_INFO of PS_SRSTB : signal is "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO PS_SRSTB";
attribute X_INTERFACE_INFO of USB0_VBUS_PWRFAULT : signal is "xilinx.com:display_processing_system7:usbctrl:1.0 USBIND_0 VBUS_PWRFAULT";
attribute X_INTERFACE_INFO of USB0_VBUS_PWRSELECT : signal is "xilinx.com:display_processing_system7:usbctrl:1.0 USBIND_0 VBUS_PWRSELECT";
attribute X_INTERFACE_INFO of DDR_Addr : signal is "xilinx.com:interface:ddrx:1.0 DDR ADDR";
attribute X_INTERFACE_INFO of DDR_BankAddr : signal is "xilinx.com:interface:ddrx:1.0 DDR BA";
attribute X_INTERFACE_INFO of DDR_DM : signal is "xilinx.com:interface:ddrx:1.0 DDR DM";
attribute X_INTERFACE_INFO of DDR_DQ : signal is "xilinx.com:interface:ddrx:1.0 DDR DQ";
attribute X_INTERFACE_INFO of DDR_DQS : signal is "xilinx.com:interface:ddrx:1.0 DDR DQS_P";
attribute X_INTERFACE_PARAMETER of DDR_DQS : signal is "XIL_INTERFACENAME DDR, CAN_DEBUG false, TIMEPERIOD_PS 1250, MEMORY_TYPE COMPONENTS, DATA_WIDTH 8, CS_ENABLED true, DATA_MASK_ENABLED true, SLOT Single, MEM_ADDR_MAP ROW_COLUMN_BANK, BURST_LENGTH 8, AXI_ARBITRATION_SCHEME TDM, CAS_LATENCY 11, CAS_WRITE_LATENCY 11";
attribute X_INTERFACE_INFO of DDR_DQS_n : signal is "xilinx.com:interface:ddrx:1.0 DDR DQS_N";
attribute X_INTERFACE_INFO of IRQ_F2P : signal is "xilinx.com:signal:interrupt:1.0 IRQ_F2P INTERRUPT";
attribute X_INTERFACE_PARAMETER of IRQ_F2P : signal is "XIL_INTERFACENAME IRQ_F2P, SENSITIVITY LEVEL_HIGH, PortWidth 1";
attribute X_INTERFACE_INFO of MIO : signal is "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO MIO";
attribute X_INTERFACE_INFO of M_AXI_GP0_ARADDR : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARADDR";
attribute X_INTERFACE_INFO of M_AXI_GP0_ARBURST : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARBURST";
attribute X_INTERFACE_INFO of M_AXI_GP0_ARCACHE : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARCACHE";
attribute X_INTERFACE_INFO of M_AXI_GP0_ARID : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARID";
attribute X_INTERFACE_INFO of M_AXI_GP0_ARLEN : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARLEN";
attribute X_INTERFACE_INFO of M_AXI_GP0_ARLOCK : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARLOCK";
attribute X_INTERFACE_INFO of M_AXI_GP0_ARPROT : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARPROT";
attribute X_INTERFACE_INFO of M_AXI_GP0_ARQOS : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARQOS";
attribute X_INTERFACE_INFO of M_AXI_GP0_ARSIZE : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARSIZE";
attribute X_INTERFACE_INFO of M_AXI_GP0_AWADDR : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWADDR";
attribute X_INTERFACE_INFO of M_AXI_GP0_AWBURST : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWBURST";
attribute X_INTERFACE_INFO of M_AXI_GP0_AWCACHE : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWCACHE";
attribute X_INTERFACE_INFO of M_AXI_GP0_AWID : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWID";
attribute X_INTERFACE_INFO of M_AXI_GP0_AWLEN : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWLEN";
attribute X_INTERFACE_INFO of M_AXI_GP0_AWLOCK : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWLOCK";
attribute X_INTERFACE_INFO of M_AXI_GP0_AWPROT : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWPROT";
attribute X_INTERFACE_INFO of M_AXI_GP0_AWQOS : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWQOS";
attribute X_INTERFACE_INFO of M_AXI_GP0_AWSIZE : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWSIZE";
attribute X_INTERFACE_INFO of M_AXI_GP0_BID : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 BID";
attribute X_INTERFACE_INFO of M_AXI_GP0_BRESP : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 BRESP";
attribute X_INTERFACE_INFO of M_AXI_GP0_RDATA : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 RDATA";
attribute X_INTERFACE_PARAMETER of M_AXI_GP0_RDATA : signal is "XIL_INTERFACENAME M_AXI_GP0, SUPPORTS_NARROW_BURST 0, NUM_WRITE_OUTSTANDING 8, NUM_READ_OUTSTANDING 8, DATA_WIDTH 32, PROTOCOL AXI3, FREQ_HZ 50000000, ID_WIDTH 12, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 1, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 1, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, MAX_BURST_LENGTH 16, PHASE 0.000, CLK_DOMAIN design_1_processing_system7_0_2_FCLK_CLK0, NUM_READ_THREADS 4, NUM_WRITE_THREADS 4, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0";
attribute X_INTERFACE_INFO of M_AXI_GP0_RID : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 RID";
attribute X_INTERFACE_INFO of M_AXI_GP0_RRESP : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 RRESP";
attribute X_INTERFACE_INFO of M_AXI_GP0_WDATA : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 WDATA";
attribute X_INTERFACE_INFO of M_AXI_GP0_WID : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 WID";
attribute X_INTERFACE_INFO of M_AXI_GP0_WSTRB : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 WSTRB";
attribute X_INTERFACE_INFO of USB0_PORT_INDCTL : signal is "xilinx.com:display_processing_system7:usbctrl:1.0 USBIND_0 PORT_INDCTL";
begin
inst: entity work.design_1_processing_system7_0_2_processing_system7_v5_5_processing_system7
port map (
CAN0_PHY_RX => '0',
CAN0_PHY_TX => NLW_inst_CAN0_PHY_TX_UNCONNECTED,
CAN1_PHY_RX => '0',
CAN1_PHY_TX => NLW_inst_CAN1_PHY_TX_UNCONNECTED,
Core0_nFIQ => '0',
Core0_nIRQ => '0',
Core1_nFIQ => '0',
Core1_nIRQ => '0',
DDR_ARB(3 downto 0) => B"0000",
DDR_Addr(14 downto 0) => DDR_Addr(14 downto 0),
DDR_BankAddr(2 downto 0) => DDR_BankAddr(2 downto 0),
DDR_CAS_n => DDR_CAS_n,
DDR_CKE => DDR_CKE,
DDR_CS_n => DDR_CS_n,
DDR_Clk => DDR_Clk,
DDR_Clk_n => DDR_Clk_n,
DDR_DM(3 downto 0) => DDR_DM(3 downto 0),
DDR_DQ(31 downto 0) => DDR_DQ(31 downto 0),
DDR_DQS(3 downto 0) => DDR_DQS(3 downto 0),
DDR_DQS_n(3 downto 0) => DDR_DQS_n(3 downto 0),
DDR_DRSTB => DDR_DRSTB,
DDR_ODT => DDR_ODT,
DDR_RAS_n => DDR_RAS_n,
DDR_VRN => DDR_VRN,
DDR_VRP => DDR_VRP,
DDR_WEB => DDR_WEB,
DMA0_ACLK => '0',
DMA0_DAREADY => '0',
DMA0_DATYPE(1 downto 0) => NLW_inst_DMA0_DATYPE_UNCONNECTED(1 downto 0),
DMA0_DAVALID => NLW_inst_DMA0_DAVALID_UNCONNECTED,
DMA0_DRLAST => '0',
DMA0_DRREADY => NLW_inst_DMA0_DRREADY_UNCONNECTED,
DMA0_DRTYPE(1 downto 0) => B"00",
DMA0_DRVALID => '0',
DMA0_RSTN => NLW_inst_DMA0_RSTN_UNCONNECTED,
DMA1_ACLK => '0',
DMA1_DAREADY => '0',
DMA1_DATYPE(1 downto 0) => NLW_inst_DMA1_DATYPE_UNCONNECTED(1 downto 0),
DMA1_DAVALID => NLW_inst_DMA1_DAVALID_UNCONNECTED,
DMA1_DRLAST => '0',
DMA1_DRREADY => NLW_inst_DMA1_DRREADY_UNCONNECTED,
DMA1_DRTYPE(1 downto 0) => B"00",
DMA1_DRVALID => '0',
DMA1_RSTN => NLW_inst_DMA1_RSTN_UNCONNECTED,
DMA2_ACLK => '0',
DMA2_DAREADY => '0',
DMA2_DATYPE(1 downto 0) => NLW_inst_DMA2_DATYPE_UNCONNECTED(1 downto 0),
DMA2_DAVALID => NLW_inst_DMA2_DAVALID_UNCONNECTED,
DMA2_DRLAST => '0',
DMA2_DRREADY => NLW_inst_DMA2_DRREADY_UNCONNECTED,
DMA2_DRTYPE(1 downto 0) => B"00",
DMA2_DRVALID => '0',
DMA2_RSTN => NLW_inst_DMA2_RSTN_UNCONNECTED,
DMA3_ACLK => '0',
DMA3_DAREADY => '0',
DMA3_DATYPE(1 downto 0) => NLW_inst_DMA3_DATYPE_UNCONNECTED(1 downto 0),
DMA3_DAVALID => NLW_inst_DMA3_DAVALID_UNCONNECTED,
DMA3_DRLAST => '0',
DMA3_DRREADY => NLW_inst_DMA3_DRREADY_UNCONNECTED,
DMA3_DRTYPE(1 downto 0) => B"00",
DMA3_DRVALID => '0',
DMA3_RSTN => NLW_inst_DMA3_RSTN_UNCONNECTED,
ENET0_EXT_INTIN => '0',
ENET0_GMII_COL => '0',
ENET0_GMII_CRS => '0',
ENET0_GMII_RXD(7 downto 0) => B"00000000",
ENET0_GMII_RX_CLK => '0',
ENET0_GMII_RX_DV => '0',
ENET0_GMII_RX_ER => '0',
ENET0_GMII_TXD(7 downto 0) => NLW_inst_ENET0_GMII_TXD_UNCONNECTED(7 downto 0),
ENET0_GMII_TX_CLK => '0',
ENET0_GMII_TX_EN => NLW_inst_ENET0_GMII_TX_EN_UNCONNECTED,
ENET0_GMII_TX_ER => NLW_inst_ENET0_GMII_TX_ER_UNCONNECTED,
ENET0_MDIO_I => '0',
ENET0_MDIO_MDC => NLW_inst_ENET0_MDIO_MDC_UNCONNECTED,
ENET0_MDIO_O => NLW_inst_ENET0_MDIO_O_UNCONNECTED,
ENET0_MDIO_T => NLW_inst_ENET0_MDIO_T_UNCONNECTED,
ENET0_PTP_DELAY_REQ_RX => NLW_inst_ENET0_PTP_DELAY_REQ_RX_UNCONNECTED,
ENET0_PTP_DELAY_REQ_TX => NLW_inst_ENET0_PTP_DELAY_REQ_TX_UNCONNECTED,
ENET0_PTP_PDELAY_REQ_RX => NLW_inst_ENET0_PTP_PDELAY_REQ_RX_UNCONNECTED,
ENET0_PTP_PDELAY_REQ_TX => NLW_inst_ENET0_PTP_PDELAY_REQ_TX_UNCONNECTED,
ENET0_PTP_PDELAY_RESP_RX => NLW_inst_ENET0_PTP_PDELAY_RESP_RX_UNCONNECTED,
ENET0_PTP_PDELAY_RESP_TX => NLW_inst_ENET0_PTP_PDELAY_RESP_TX_UNCONNECTED,
ENET0_PTP_SYNC_FRAME_RX => NLW_inst_ENET0_PTP_SYNC_FRAME_RX_UNCONNECTED,
ENET0_PTP_SYNC_FRAME_TX => NLW_inst_ENET0_PTP_SYNC_FRAME_TX_UNCONNECTED,
ENET0_SOF_RX => NLW_inst_ENET0_SOF_RX_UNCONNECTED,
ENET0_SOF_TX => NLW_inst_ENET0_SOF_TX_UNCONNECTED,
ENET1_EXT_INTIN => '0',
ENET1_GMII_COL => '0',
ENET1_GMII_CRS => '0',
ENET1_GMII_RXD(7 downto 0) => B"00000000",
ENET1_GMII_RX_CLK => '0',
ENET1_GMII_RX_DV => '0',
ENET1_GMII_RX_ER => '0',
ENET1_GMII_TXD(7 downto 0) => NLW_inst_ENET1_GMII_TXD_UNCONNECTED(7 downto 0),
ENET1_GMII_TX_CLK => '0',
ENET1_GMII_TX_EN => NLW_inst_ENET1_GMII_TX_EN_UNCONNECTED,
ENET1_GMII_TX_ER => NLW_inst_ENET1_GMII_TX_ER_UNCONNECTED,
ENET1_MDIO_I => '0',
ENET1_MDIO_MDC => NLW_inst_ENET1_MDIO_MDC_UNCONNECTED,
ENET1_MDIO_O => NLW_inst_ENET1_MDIO_O_UNCONNECTED,
ENET1_MDIO_T => NLW_inst_ENET1_MDIO_T_UNCONNECTED,
ENET1_PTP_DELAY_REQ_RX => NLW_inst_ENET1_PTP_DELAY_REQ_RX_UNCONNECTED,
ENET1_PTP_DELAY_REQ_TX => NLW_inst_ENET1_PTP_DELAY_REQ_TX_UNCONNECTED,
ENET1_PTP_PDELAY_REQ_RX => NLW_inst_ENET1_PTP_PDELAY_REQ_RX_UNCONNECTED,
ENET1_PTP_PDELAY_REQ_TX => NLW_inst_ENET1_PTP_PDELAY_REQ_TX_UNCONNECTED,
ENET1_PTP_PDELAY_RESP_RX => NLW_inst_ENET1_PTP_PDELAY_RESP_RX_UNCONNECTED,
ENET1_PTP_PDELAY_RESP_TX => NLW_inst_ENET1_PTP_PDELAY_RESP_TX_UNCONNECTED,
ENET1_PTP_SYNC_FRAME_RX => NLW_inst_ENET1_PTP_SYNC_FRAME_RX_UNCONNECTED,
ENET1_PTP_SYNC_FRAME_TX => NLW_inst_ENET1_PTP_SYNC_FRAME_TX_UNCONNECTED,
ENET1_SOF_RX => NLW_inst_ENET1_SOF_RX_UNCONNECTED,
ENET1_SOF_TX => NLW_inst_ENET1_SOF_TX_UNCONNECTED,
EVENT_EVENTI => '0',
EVENT_EVENTO => NLW_inst_EVENT_EVENTO_UNCONNECTED,
EVENT_STANDBYWFE(1 downto 0) => NLW_inst_EVENT_STANDBYWFE_UNCONNECTED(1 downto 0),
EVENT_STANDBYWFI(1 downto 0) => NLW_inst_EVENT_STANDBYWFI_UNCONNECTED(1 downto 0),
FCLK_CLK0 => FCLK_CLK0,
FCLK_CLK1 => NLW_inst_FCLK_CLK1_UNCONNECTED,
FCLK_CLK2 => NLW_inst_FCLK_CLK2_UNCONNECTED,
FCLK_CLK3 => NLW_inst_FCLK_CLK3_UNCONNECTED,
FCLK_CLKTRIG0_N => '0',
FCLK_CLKTRIG1_N => '0',
FCLK_CLKTRIG2_N => '0',
FCLK_CLKTRIG3_N => '0',
FCLK_RESET0_N => FCLK_RESET0_N,
FCLK_RESET1_N => NLW_inst_FCLK_RESET1_N_UNCONNECTED,
FCLK_RESET2_N => NLW_inst_FCLK_RESET2_N_UNCONNECTED,
FCLK_RESET3_N => NLW_inst_FCLK_RESET3_N_UNCONNECTED,
FPGA_IDLE_N => '0',
FTMD_TRACEIN_ATID(3 downto 0) => B"0000",
FTMD_TRACEIN_CLK => '0',
FTMD_TRACEIN_DATA(31 downto 0) => B"00000000000000000000000000000000",
FTMD_TRACEIN_VALID => '0',
FTMT_F2P_DEBUG(31 downto 0) => B"00000000000000000000000000000000",
FTMT_F2P_TRIGACK_0 => NLW_inst_FTMT_F2P_TRIGACK_0_UNCONNECTED,
FTMT_F2P_TRIGACK_1 => NLW_inst_FTMT_F2P_TRIGACK_1_UNCONNECTED,
FTMT_F2P_TRIGACK_2 => NLW_inst_FTMT_F2P_TRIGACK_2_UNCONNECTED,
FTMT_F2P_TRIGACK_3 => NLW_inst_FTMT_F2P_TRIGACK_3_UNCONNECTED,
FTMT_F2P_TRIG_0 => '0',
FTMT_F2P_TRIG_1 => '0',
FTMT_F2P_TRIG_2 => '0',
FTMT_F2P_TRIG_3 => '0',
FTMT_P2F_DEBUG(31 downto 0) => NLW_inst_FTMT_P2F_DEBUG_UNCONNECTED(31 downto 0),
FTMT_P2F_TRIGACK_0 => '0',
FTMT_P2F_TRIGACK_1 => '0',
FTMT_P2F_TRIGACK_2 => '0',
FTMT_P2F_TRIGACK_3 => '0',
FTMT_P2F_TRIG_0 => NLW_inst_FTMT_P2F_TRIG_0_UNCONNECTED,
FTMT_P2F_TRIG_1 => NLW_inst_FTMT_P2F_TRIG_1_UNCONNECTED,
FTMT_P2F_TRIG_2 => NLW_inst_FTMT_P2F_TRIG_2_UNCONNECTED,
FTMT_P2F_TRIG_3 => NLW_inst_FTMT_P2F_TRIG_3_UNCONNECTED,
GPIO_I(63 downto 0) => B"0000000000000000000000000000000000000000000000000000000000000000",
GPIO_O(63 downto 0) => NLW_inst_GPIO_O_UNCONNECTED(63 downto 0),
GPIO_T(63 downto 0) => NLW_inst_GPIO_T_UNCONNECTED(63 downto 0),
I2C0_SCL_I => '0',
I2C0_SCL_O => NLW_inst_I2C0_SCL_O_UNCONNECTED,
I2C0_SCL_T => NLW_inst_I2C0_SCL_T_UNCONNECTED,
I2C0_SDA_I => '0',
I2C0_SDA_O => NLW_inst_I2C0_SDA_O_UNCONNECTED,
I2C0_SDA_T => NLW_inst_I2C0_SDA_T_UNCONNECTED,
I2C1_SCL_I => '0',
I2C1_SCL_O => NLW_inst_I2C1_SCL_O_UNCONNECTED,
I2C1_SCL_T => NLW_inst_I2C1_SCL_T_UNCONNECTED,
I2C1_SDA_I => '0',
I2C1_SDA_O => NLW_inst_I2C1_SDA_O_UNCONNECTED,
I2C1_SDA_T => NLW_inst_I2C1_SDA_T_UNCONNECTED,
IRQ_F2P(0) => IRQ_F2P(0),
IRQ_P2F_CAN0 => NLW_inst_IRQ_P2F_CAN0_UNCONNECTED,
IRQ_P2F_CAN1 => NLW_inst_IRQ_P2F_CAN1_UNCONNECTED,
IRQ_P2F_CTI => NLW_inst_IRQ_P2F_CTI_UNCONNECTED,
IRQ_P2F_DMAC0 => NLW_inst_IRQ_P2F_DMAC0_UNCONNECTED,
IRQ_P2F_DMAC1 => NLW_inst_IRQ_P2F_DMAC1_UNCONNECTED,
IRQ_P2F_DMAC2 => NLW_inst_IRQ_P2F_DMAC2_UNCONNECTED,
IRQ_P2F_DMAC3 => NLW_inst_IRQ_P2F_DMAC3_UNCONNECTED,
IRQ_P2F_DMAC4 => NLW_inst_IRQ_P2F_DMAC4_UNCONNECTED,
IRQ_P2F_DMAC5 => NLW_inst_IRQ_P2F_DMAC5_UNCONNECTED,
IRQ_P2F_DMAC6 => NLW_inst_IRQ_P2F_DMAC6_UNCONNECTED,
IRQ_P2F_DMAC7 => NLW_inst_IRQ_P2F_DMAC7_UNCONNECTED,
IRQ_P2F_DMAC_ABORT => NLW_inst_IRQ_P2F_DMAC_ABORT_UNCONNECTED,
IRQ_P2F_ENET0 => NLW_inst_IRQ_P2F_ENET0_UNCONNECTED,
IRQ_P2F_ENET1 => NLW_inst_IRQ_P2F_ENET1_UNCONNECTED,
IRQ_P2F_ENET_WAKE0 => NLW_inst_IRQ_P2F_ENET_WAKE0_UNCONNECTED,
IRQ_P2F_ENET_WAKE1 => NLW_inst_IRQ_P2F_ENET_WAKE1_UNCONNECTED,
IRQ_P2F_GPIO => NLW_inst_IRQ_P2F_GPIO_UNCONNECTED,
IRQ_P2F_I2C0 => NLW_inst_IRQ_P2F_I2C0_UNCONNECTED,
IRQ_P2F_I2C1 => NLW_inst_IRQ_P2F_I2C1_UNCONNECTED,
IRQ_P2F_QSPI => NLW_inst_IRQ_P2F_QSPI_UNCONNECTED,
IRQ_P2F_SDIO0 => NLW_inst_IRQ_P2F_SDIO0_UNCONNECTED,
IRQ_P2F_SDIO1 => NLW_inst_IRQ_P2F_SDIO1_UNCONNECTED,
IRQ_P2F_SMC => NLW_inst_IRQ_P2F_SMC_UNCONNECTED,
IRQ_P2F_SPI0 => NLW_inst_IRQ_P2F_SPI0_UNCONNECTED,
IRQ_P2F_SPI1 => NLW_inst_IRQ_P2F_SPI1_UNCONNECTED,
IRQ_P2F_UART0 => NLW_inst_IRQ_P2F_UART0_UNCONNECTED,
IRQ_P2F_UART1 => NLW_inst_IRQ_P2F_UART1_UNCONNECTED,
IRQ_P2F_USB0 => NLW_inst_IRQ_P2F_USB0_UNCONNECTED,
IRQ_P2F_USB1 => NLW_inst_IRQ_P2F_USB1_UNCONNECTED,
MIO(53 downto 0) => MIO(53 downto 0),
M_AXI_GP0_ACLK => M_AXI_GP0_ACLK,
M_AXI_GP0_ARADDR(31 downto 0) => M_AXI_GP0_ARADDR(31 downto 0),
M_AXI_GP0_ARBURST(1 downto 0) => M_AXI_GP0_ARBURST(1 downto 0),
M_AXI_GP0_ARCACHE(3 downto 0) => M_AXI_GP0_ARCACHE(3 downto 0),
M_AXI_GP0_ARESETN => NLW_inst_M_AXI_GP0_ARESETN_UNCONNECTED,
M_AXI_GP0_ARID(11 downto 0) => M_AXI_GP0_ARID(11 downto 0),
M_AXI_GP0_ARLEN(3 downto 0) => M_AXI_GP0_ARLEN(3 downto 0),
M_AXI_GP0_ARLOCK(1 downto 0) => M_AXI_GP0_ARLOCK(1 downto 0),
M_AXI_GP0_ARPROT(2 downto 0) => M_AXI_GP0_ARPROT(2 downto 0),
M_AXI_GP0_ARQOS(3 downto 0) => M_AXI_GP0_ARQOS(3 downto 0),
M_AXI_GP0_ARREADY => M_AXI_GP0_ARREADY,
M_AXI_GP0_ARSIZE(2 downto 0) => M_AXI_GP0_ARSIZE(2 downto 0),
M_AXI_GP0_ARVALID => M_AXI_GP0_ARVALID,
M_AXI_GP0_AWADDR(31 downto 0) => M_AXI_GP0_AWADDR(31 downto 0),
M_AXI_GP0_AWBURST(1 downto 0) => M_AXI_GP0_AWBURST(1 downto 0),
M_AXI_GP0_AWCACHE(3 downto 0) => M_AXI_GP0_AWCACHE(3 downto 0),
M_AXI_GP0_AWID(11 downto 0) => M_AXI_GP0_AWID(11 downto 0),
M_AXI_GP0_AWLEN(3 downto 0) => M_AXI_GP0_AWLEN(3 downto 0),
M_AXI_GP0_AWLOCK(1 downto 0) => M_AXI_GP0_AWLOCK(1 downto 0),
M_AXI_GP0_AWPROT(2 downto 0) => M_AXI_GP0_AWPROT(2 downto 0),
M_AXI_GP0_AWQOS(3 downto 0) => M_AXI_GP0_AWQOS(3 downto 0),
M_AXI_GP0_AWREADY => M_AXI_GP0_AWREADY,
M_AXI_GP0_AWSIZE(2 downto 0) => M_AXI_GP0_AWSIZE(2 downto 0),
M_AXI_GP0_AWVALID => M_AXI_GP0_AWVALID,
M_AXI_GP0_BID(11 downto 0) => M_AXI_GP0_BID(11 downto 0),
M_AXI_GP0_BREADY => M_AXI_GP0_BREADY,
M_AXI_GP0_BRESP(1 downto 0) => M_AXI_GP0_BRESP(1 downto 0),
M_AXI_GP0_BVALID => M_AXI_GP0_BVALID,
M_AXI_GP0_RDATA(31 downto 0) => M_AXI_GP0_RDATA(31 downto 0),
M_AXI_GP0_RID(11 downto 0) => M_AXI_GP0_RID(11 downto 0),
M_AXI_GP0_RLAST => M_AXI_GP0_RLAST,
M_AXI_GP0_RREADY => M_AXI_GP0_RREADY,
M_AXI_GP0_RRESP(1 downto 0) => M_AXI_GP0_RRESP(1 downto 0),
M_AXI_GP0_RVALID => M_AXI_GP0_RVALID,
M_AXI_GP0_WDATA(31 downto 0) => M_AXI_GP0_WDATA(31 downto 0),
M_AXI_GP0_WID(11 downto 0) => M_AXI_GP0_WID(11 downto 0),
M_AXI_GP0_WLAST => M_AXI_GP0_WLAST,
M_AXI_GP0_WREADY => M_AXI_GP0_WREADY,
M_AXI_GP0_WSTRB(3 downto 0) => M_AXI_GP0_WSTRB(3 downto 0),
M_AXI_GP0_WVALID => M_AXI_GP0_WVALID,
M_AXI_GP1_ACLK => '0',
M_AXI_GP1_ARADDR(31 downto 0) => NLW_inst_M_AXI_GP1_ARADDR_UNCONNECTED(31 downto 0),
M_AXI_GP1_ARBURST(1 downto 0) => NLW_inst_M_AXI_GP1_ARBURST_UNCONNECTED(1 downto 0),
M_AXI_GP1_ARCACHE(3 downto 0) => NLW_inst_M_AXI_GP1_ARCACHE_UNCONNECTED(3 downto 0),
M_AXI_GP1_ARESETN => NLW_inst_M_AXI_GP1_ARESETN_UNCONNECTED,
M_AXI_GP1_ARID(11 downto 0) => NLW_inst_M_AXI_GP1_ARID_UNCONNECTED(11 downto 0),
M_AXI_GP1_ARLEN(3 downto 0) => NLW_inst_M_AXI_GP1_ARLEN_UNCONNECTED(3 downto 0),
M_AXI_GP1_ARLOCK(1 downto 0) => NLW_inst_M_AXI_GP1_ARLOCK_UNCONNECTED(1 downto 0),
M_AXI_GP1_ARPROT(2 downto 0) => NLW_inst_M_AXI_GP1_ARPROT_UNCONNECTED(2 downto 0),
M_AXI_GP1_ARQOS(3 downto 0) => NLW_inst_M_AXI_GP1_ARQOS_UNCONNECTED(3 downto 0),
M_AXI_GP1_ARREADY => '0',
M_AXI_GP1_ARSIZE(2 downto 0) => NLW_inst_M_AXI_GP1_ARSIZE_UNCONNECTED(2 downto 0),
M_AXI_GP1_ARVALID => NLW_inst_M_AXI_GP1_ARVALID_UNCONNECTED,
M_AXI_GP1_AWADDR(31 downto 0) => NLW_inst_M_AXI_GP1_AWADDR_UNCONNECTED(31 downto 0),
M_AXI_GP1_AWBURST(1 downto 0) => NLW_inst_M_AXI_GP1_AWBURST_UNCONNECTED(1 downto 0),
M_AXI_GP1_AWCACHE(3 downto 0) => NLW_inst_M_AXI_GP1_AWCACHE_UNCONNECTED(3 downto 0),
M_AXI_GP1_AWID(11 downto 0) => NLW_inst_M_AXI_GP1_AWID_UNCONNECTED(11 downto 0),
M_AXI_GP1_AWLEN(3 downto 0) => NLW_inst_M_AXI_GP1_AWLEN_UNCONNECTED(3 downto 0),
M_AXI_GP1_AWLOCK(1 downto 0) => NLW_inst_M_AXI_GP1_AWLOCK_UNCONNECTED(1 downto 0),
M_AXI_GP1_AWPROT(2 downto 0) => NLW_inst_M_AXI_GP1_AWPROT_UNCONNECTED(2 downto 0),
M_AXI_GP1_AWQOS(3 downto 0) => NLW_inst_M_AXI_GP1_AWQOS_UNCONNECTED(3 downto 0),
M_AXI_GP1_AWREADY => '0',
M_AXI_GP1_AWSIZE(2 downto 0) => NLW_inst_M_AXI_GP1_AWSIZE_UNCONNECTED(2 downto 0),
M_AXI_GP1_AWVALID => NLW_inst_M_AXI_GP1_AWVALID_UNCONNECTED,
M_AXI_GP1_BID(11 downto 0) => B"000000000000",
M_AXI_GP1_BREADY => NLW_inst_M_AXI_GP1_BREADY_UNCONNECTED,
M_AXI_GP1_BRESP(1 downto 0) => B"00",
M_AXI_GP1_BVALID => '0',
M_AXI_GP1_RDATA(31 downto 0) => B"00000000000000000000000000000000",
M_AXI_GP1_RID(11 downto 0) => B"000000000000",
M_AXI_GP1_RLAST => '0',
M_AXI_GP1_RREADY => NLW_inst_M_AXI_GP1_RREADY_UNCONNECTED,
M_AXI_GP1_RRESP(1 downto 0) => B"00",
M_AXI_GP1_RVALID => '0',
M_AXI_GP1_WDATA(31 downto 0) => NLW_inst_M_AXI_GP1_WDATA_UNCONNECTED(31 downto 0),
M_AXI_GP1_WID(11 downto 0) => NLW_inst_M_AXI_GP1_WID_UNCONNECTED(11 downto 0),
M_AXI_GP1_WLAST => NLW_inst_M_AXI_GP1_WLAST_UNCONNECTED,
M_AXI_GP1_WREADY => '0',
M_AXI_GP1_WSTRB(3 downto 0) => NLW_inst_M_AXI_GP1_WSTRB_UNCONNECTED(3 downto 0),
M_AXI_GP1_WVALID => NLW_inst_M_AXI_GP1_WVALID_UNCONNECTED,
PJTAG_TCK => '0',
PJTAG_TDI => '0',
PJTAG_TDO => NLW_inst_PJTAG_TDO_UNCONNECTED,
PJTAG_TMS => '0',
PS_CLK => PS_CLK,
PS_PORB => PS_PORB,
PS_SRSTB => PS_SRSTB,
SDIO0_BUSPOW => NLW_inst_SDIO0_BUSPOW_UNCONNECTED,
SDIO0_BUSVOLT(2 downto 0) => NLW_inst_SDIO0_BUSVOLT_UNCONNECTED(2 downto 0),
SDIO0_CDN => '0',
SDIO0_CLK => NLW_inst_SDIO0_CLK_UNCONNECTED,
SDIO0_CLK_FB => '0',
SDIO0_CMD_I => '0',
SDIO0_CMD_O => NLW_inst_SDIO0_CMD_O_UNCONNECTED,
SDIO0_CMD_T => NLW_inst_SDIO0_CMD_T_UNCONNECTED,
SDIO0_DATA_I(3 downto 0) => B"0000",
SDIO0_DATA_O(3 downto 0) => NLW_inst_SDIO0_DATA_O_UNCONNECTED(3 downto 0),
SDIO0_DATA_T(3 downto 0) => NLW_inst_SDIO0_DATA_T_UNCONNECTED(3 downto 0),
SDIO0_LED => NLW_inst_SDIO0_LED_UNCONNECTED,
SDIO0_WP => '0',
SDIO1_BUSPOW => NLW_inst_SDIO1_BUSPOW_UNCONNECTED,
SDIO1_BUSVOLT(2 downto 0) => NLW_inst_SDIO1_BUSVOLT_UNCONNECTED(2 downto 0),
SDIO1_CDN => '0',
SDIO1_CLK => NLW_inst_SDIO1_CLK_UNCONNECTED,
SDIO1_CLK_FB => '0',
SDIO1_CMD_I => '0',
SDIO1_CMD_O => NLW_inst_SDIO1_CMD_O_UNCONNECTED,
SDIO1_CMD_T => NLW_inst_SDIO1_CMD_T_UNCONNECTED,
SDIO1_DATA_I(3 downto 0) => B"0000",
SDIO1_DATA_O(3 downto 0) => NLW_inst_SDIO1_DATA_O_UNCONNECTED(3 downto 0),
SDIO1_DATA_T(3 downto 0) => NLW_inst_SDIO1_DATA_T_UNCONNECTED(3 downto 0),
SDIO1_LED => NLW_inst_SDIO1_LED_UNCONNECTED,
SDIO1_WP => '0',
SPI0_MISO_I => '0',
SPI0_MISO_O => NLW_inst_SPI0_MISO_O_UNCONNECTED,
SPI0_MISO_T => NLW_inst_SPI0_MISO_T_UNCONNECTED,
SPI0_MOSI_I => '0',
SPI0_MOSI_O => NLW_inst_SPI0_MOSI_O_UNCONNECTED,
SPI0_MOSI_T => NLW_inst_SPI0_MOSI_T_UNCONNECTED,
SPI0_SCLK_I => '0',
SPI0_SCLK_O => NLW_inst_SPI0_SCLK_O_UNCONNECTED,
SPI0_SCLK_T => NLW_inst_SPI0_SCLK_T_UNCONNECTED,
SPI0_SS1_O => NLW_inst_SPI0_SS1_O_UNCONNECTED,
SPI0_SS2_O => NLW_inst_SPI0_SS2_O_UNCONNECTED,
SPI0_SS_I => '0',
SPI0_SS_O => NLW_inst_SPI0_SS_O_UNCONNECTED,
SPI0_SS_T => NLW_inst_SPI0_SS_T_UNCONNECTED,
SPI1_MISO_I => '0',
SPI1_MISO_O => NLW_inst_SPI1_MISO_O_UNCONNECTED,
SPI1_MISO_T => NLW_inst_SPI1_MISO_T_UNCONNECTED,
SPI1_MOSI_I => '0',
SPI1_MOSI_O => NLW_inst_SPI1_MOSI_O_UNCONNECTED,
SPI1_MOSI_T => NLW_inst_SPI1_MOSI_T_UNCONNECTED,
SPI1_SCLK_I => '0',
SPI1_SCLK_O => NLW_inst_SPI1_SCLK_O_UNCONNECTED,
SPI1_SCLK_T => NLW_inst_SPI1_SCLK_T_UNCONNECTED,
SPI1_SS1_O => NLW_inst_SPI1_SS1_O_UNCONNECTED,
SPI1_SS2_O => NLW_inst_SPI1_SS2_O_UNCONNECTED,
SPI1_SS_I => '0',
SPI1_SS_O => NLW_inst_SPI1_SS_O_UNCONNECTED,
SPI1_SS_T => NLW_inst_SPI1_SS_T_UNCONNECTED,
SRAM_INTIN => '0',
S_AXI_ACP_ACLK => '0',
S_AXI_ACP_ARADDR(31 downto 0) => B"00000000000000000000000000000000",
S_AXI_ACP_ARBURST(1 downto 0) => B"00",
S_AXI_ACP_ARCACHE(3 downto 0) => B"0000",
S_AXI_ACP_ARESETN => NLW_inst_S_AXI_ACP_ARESETN_UNCONNECTED,
S_AXI_ACP_ARID(2 downto 0) => B"000",
S_AXI_ACP_ARLEN(3 downto 0) => B"0000",
S_AXI_ACP_ARLOCK(1 downto 0) => B"00",
S_AXI_ACP_ARPROT(2 downto 0) => B"000",
S_AXI_ACP_ARQOS(3 downto 0) => B"0000",
S_AXI_ACP_ARREADY => NLW_inst_S_AXI_ACP_ARREADY_UNCONNECTED,
S_AXI_ACP_ARSIZE(2 downto 0) => B"000",
S_AXI_ACP_ARUSER(4 downto 0) => B"00000",
S_AXI_ACP_ARVALID => '0',
S_AXI_ACP_AWADDR(31 downto 0) => B"00000000000000000000000000000000",
S_AXI_ACP_AWBURST(1 downto 0) => B"00",
S_AXI_ACP_AWCACHE(3 downto 0) => B"0000",
S_AXI_ACP_AWID(2 downto 0) => B"000",
S_AXI_ACP_AWLEN(3 downto 0) => B"0000",
S_AXI_ACP_AWLOCK(1 downto 0) => B"00",
S_AXI_ACP_AWPROT(2 downto 0) => B"000",
S_AXI_ACP_AWQOS(3 downto 0) => B"0000",
S_AXI_ACP_AWREADY => NLW_inst_S_AXI_ACP_AWREADY_UNCONNECTED,
S_AXI_ACP_AWSIZE(2 downto 0) => B"000",
S_AXI_ACP_AWUSER(4 downto 0) => B"00000",
S_AXI_ACP_AWVALID => '0',
S_AXI_ACP_BID(2 downto 0) => NLW_inst_S_AXI_ACP_BID_UNCONNECTED(2 downto 0),
S_AXI_ACP_BREADY => '0',
S_AXI_ACP_BRESP(1 downto 0) => NLW_inst_S_AXI_ACP_BRESP_UNCONNECTED(1 downto 0),
S_AXI_ACP_BVALID => NLW_inst_S_AXI_ACP_BVALID_UNCONNECTED,
S_AXI_ACP_RDATA(63 downto 0) => NLW_inst_S_AXI_ACP_RDATA_UNCONNECTED(63 downto 0),
S_AXI_ACP_RID(2 downto 0) => NLW_inst_S_AXI_ACP_RID_UNCONNECTED(2 downto 0),
S_AXI_ACP_RLAST => NLW_inst_S_AXI_ACP_RLAST_UNCONNECTED,
S_AXI_ACP_RREADY => '0',
S_AXI_ACP_RRESP(1 downto 0) => NLW_inst_S_AXI_ACP_RRESP_UNCONNECTED(1 downto 0),
S_AXI_ACP_RVALID => NLW_inst_S_AXI_ACP_RVALID_UNCONNECTED,
S_AXI_ACP_WDATA(63 downto 0) => B"0000000000000000000000000000000000000000000000000000000000000000",
S_AXI_ACP_WID(2 downto 0) => B"000",
S_AXI_ACP_WLAST => '0',
S_AXI_ACP_WREADY => NLW_inst_S_AXI_ACP_WREADY_UNCONNECTED,
S_AXI_ACP_WSTRB(7 downto 0) => B"00000000",
S_AXI_ACP_WVALID => '0',
S_AXI_GP0_ACLK => '0',
S_AXI_GP0_ARADDR(31 downto 0) => B"00000000000000000000000000000000",
S_AXI_GP0_ARBURST(1 downto 0) => B"00",
S_AXI_GP0_ARCACHE(3 downto 0) => B"0000",
S_AXI_GP0_ARESETN => NLW_inst_S_AXI_GP0_ARESETN_UNCONNECTED,
S_AXI_GP0_ARID(5 downto 0) => B"000000",
S_AXI_GP0_ARLEN(3 downto 0) => B"0000",
S_AXI_GP0_ARLOCK(1 downto 0) => B"00",
S_AXI_GP0_ARPROT(2 downto 0) => B"000",
S_AXI_GP0_ARQOS(3 downto 0) => B"0000",
S_AXI_GP0_ARREADY => NLW_inst_S_AXI_GP0_ARREADY_UNCONNECTED,
S_AXI_GP0_ARSIZE(2 downto 0) => B"000",
S_AXI_GP0_ARVALID => '0',
S_AXI_GP0_AWADDR(31 downto 0) => B"00000000000000000000000000000000",
S_AXI_GP0_AWBURST(1 downto 0) => B"00",
S_AXI_GP0_AWCACHE(3 downto 0) => B"0000",
S_AXI_GP0_AWID(5 downto 0) => B"000000",
S_AXI_GP0_AWLEN(3 downto 0) => B"0000",
S_AXI_GP0_AWLOCK(1 downto 0) => B"00",
S_AXI_GP0_AWPROT(2 downto 0) => B"000",
S_AXI_GP0_AWQOS(3 downto 0) => B"0000",
S_AXI_GP0_AWREADY => NLW_inst_S_AXI_GP0_AWREADY_UNCONNECTED,
S_AXI_GP0_AWSIZE(2 downto 0) => B"000",
S_AXI_GP0_AWVALID => '0',
S_AXI_GP0_BID(5 downto 0) => NLW_inst_S_AXI_GP0_BID_UNCONNECTED(5 downto 0),
S_AXI_GP0_BREADY => '0',
S_AXI_GP0_BRESP(1 downto 0) => NLW_inst_S_AXI_GP0_BRESP_UNCONNECTED(1 downto 0),
S_AXI_GP0_BVALID => NLW_inst_S_AXI_GP0_BVALID_UNCONNECTED,
S_AXI_GP0_RDATA(31 downto 0) => NLW_inst_S_AXI_GP0_RDATA_UNCONNECTED(31 downto 0),
S_AXI_GP0_RID(5 downto 0) => NLW_inst_S_AXI_GP0_RID_UNCONNECTED(5 downto 0),
S_AXI_GP0_RLAST => NLW_inst_S_AXI_GP0_RLAST_UNCONNECTED,
S_AXI_GP0_RREADY => '0',
S_AXI_GP0_RRESP(1 downto 0) => NLW_inst_S_AXI_GP0_RRESP_UNCONNECTED(1 downto 0),
S_AXI_GP0_RVALID => NLW_inst_S_AXI_GP0_RVALID_UNCONNECTED,
S_AXI_GP0_WDATA(31 downto 0) => B"00000000000000000000000000000000",
S_AXI_GP0_WID(5 downto 0) => B"000000",
S_AXI_GP0_WLAST => '0',
S_AXI_GP0_WREADY => NLW_inst_S_AXI_GP0_WREADY_UNCONNECTED,
S_AXI_GP0_WSTRB(3 downto 0) => B"0000",
S_AXI_GP0_WVALID => '0',
S_AXI_GP1_ACLK => '0',
S_AXI_GP1_ARADDR(31 downto 0) => B"00000000000000000000000000000000",
S_AXI_GP1_ARBURST(1 downto 0) => B"00",
S_AXI_GP1_ARCACHE(3 downto 0) => B"0000",
S_AXI_GP1_ARESETN => NLW_inst_S_AXI_GP1_ARESETN_UNCONNECTED,
S_AXI_GP1_ARID(5 downto 0) => B"000000",
S_AXI_GP1_ARLEN(3 downto 0) => B"0000",
S_AXI_GP1_ARLOCK(1 downto 0) => B"00",
S_AXI_GP1_ARPROT(2 downto 0) => B"000",
S_AXI_GP1_ARQOS(3 downto 0) => B"0000",
S_AXI_GP1_ARREADY => NLW_inst_S_AXI_GP1_ARREADY_UNCONNECTED,
S_AXI_GP1_ARSIZE(2 downto 0) => B"000",
S_AXI_GP1_ARVALID => '0',
S_AXI_GP1_AWADDR(31 downto 0) => B"00000000000000000000000000000000",
S_AXI_GP1_AWBURST(1 downto 0) => B"00",
S_AXI_GP1_AWCACHE(3 downto 0) => B"0000",
S_AXI_GP1_AWID(5 downto 0) => B"000000",
S_AXI_GP1_AWLEN(3 downto 0) => B"0000",
S_AXI_GP1_AWLOCK(1 downto 0) => B"00",
S_AXI_GP1_AWPROT(2 downto 0) => B"000",
S_AXI_GP1_AWQOS(3 downto 0) => B"0000",
S_AXI_GP1_AWREADY => NLW_inst_S_AXI_GP1_AWREADY_UNCONNECTED,
S_AXI_GP1_AWSIZE(2 downto 0) => B"000",
S_AXI_GP1_AWVALID => '0',
S_AXI_GP1_BID(5 downto 0) => NLW_inst_S_AXI_GP1_BID_UNCONNECTED(5 downto 0),
S_AXI_GP1_BREADY => '0',
S_AXI_GP1_BRESP(1 downto 0) => NLW_inst_S_AXI_GP1_BRESP_UNCONNECTED(1 downto 0),
S_AXI_GP1_BVALID => NLW_inst_S_AXI_GP1_BVALID_UNCONNECTED,
S_AXI_GP1_RDATA(31 downto 0) => NLW_inst_S_AXI_GP1_RDATA_UNCONNECTED(31 downto 0),
S_AXI_GP1_RID(5 downto 0) => NLW_inst_S_AXI_GP1_RID_UNCONNECTED(5 downto 0),
S_AXI_GP1_RLAST => NLW_inst_S_AXI_GP1_RLAST_UNCONNECTED,
S_AXI_GP1_RREADY => '0',
S_AXI_GP1_RRESP(1 downto 0) => NLW_inst_S_AXI_GP1_RRESP_UNCONNECTED(1 downto 0),
S_AXI_GP1_RVALID => NLW_inst_S_AXI_GP1_RVALID_UNCONNECTED,
S_AXI_GP1_WDATA(31 downto 0) => B"00000000000000000000000000000000",
S_AXI_GP1_WID(5 downto 0) => B"000000",
S_AXI_GP1_WLAST => '0',
S_AXI_GP1_WREADY => NLW_inst_S_AXI_GP1_WREADY_UNCONNECTED,
S_AXI_GP1_WSTRB(3 downto 0) => B"0000",
S_AXI_GP1_WVALID => '0',
S_AXI_HP0_ACLK => '0',
S_AXI_HP0_ARADDR(31 downto 0) => B"00000000000000000000000000000000",
S_AXI_HP0_ARBURST(1 downto 0) => B"00",
S_AXI_HP0_ARCACHE(3 downto 0) => B"0000",
S_AXI_HP0_ARESETN => NLW_inst_S_AXI_HP0_ARESETN_UNCONNECTED,
S_AXI_HP0_ARID(5 downto 0) => B"000000",
S_AXI_HP0_ARLEN(3 downto 0) => B"0000",
S_AXI_HP0_ARLOCK(1 downto 0) => B"00",
S_AXI_HP0_ARPROT(2 downto 0) => B"000",
S_AXI_HP0_ARQOS(3 downto 0) => B"0000",
S_AXI_HP0_ARREADY => NLW_inst_S_AXI_HP0_ARREADY_UNCONNECTED,
S_AXI_HP0_ARSIZE(2 downto 0) => B"000",
S_AXI_HP0_ARVALID => '0',
S_AXI_HP0_AWADDR(31 downto 0) => B"00000000000000000000000000000000",
S_AXI_HP0_AWBURST(1 downto 0) => B"00",
S_AXI_HP0_AWCACHE(3 downto 0) => B"0000",
S_AXI_HP0_AWID(5 downto 0) => B"000000",
S_AXI_HP0_AWLEN(3 downto 0) => B"0000",
S_AXI_HP0_AWLOCK(1 downto 0) => B"00",
S_AXI_HP0_AWPROT(2 downto 0) => B"000",
S_AXI_HP0_AWQOS(3 downto 0) => B"0000",
S_AXI_HP0_AWREADY => NLW_inst_S_AXI_HP0_AWREADY_UNCONNECTED,
S_AXI_HP0_AWSIZE(2 downto 0) => B"000",
S_AXI_HP0_AWVALID => '0',
S_AXI_HP0_BID(5 downto 0) => NLW_inst_S_AXI_HP0_BID_UNCONNECTED(5 downto 0),
S_AXI_HP0_BREADY => '0',
S_AXI_HP0_BRESP(1 downto 0) => NLW_inst_S_AXI_HP0_BRESP_UNCONNECTED(1 downto 0),
S_AXI_HP0_BVALID => NLW_inst_S_AXI_HP0_BVALID_UNCONNECTED,
S_AXI_HP0_RACOUNT(2 downto 0) => NLW_inst_S_AXI_HP0_RACOUNT_UNCONNECTED(2 downto 0),
S_AXI_HP0_RCOUNT(7 downto 0) => NLW_inst_S_AXI_HP0_RCOUNT_UNCONNECTED(7 downto 0),
S_AXI_HP0_RDATA(63 downto 0) => NLW_inst_S_AXI_HP0_RDATA_UNCONNECTED(63 downto 0),
S_AXI_HP0_RDISSUECAP1_EN => '0',
S_AXI_HP0_RID(5 downto 0) => NLW_inst_S_AXI_HP0_RID_UNCONNECTED(5 downto 0),
S_AXI_HP0_RLAST => NLW_inst_S_AXI_HP0_RLAST_UNCONNECTED,
S_AXI_HP0_RREADY => '0',
S_AXI_HP0_RRESP(1 downto 0) => NLW_inst_S_AXI_HP0_RRESP_UNCONNECTED(1 downto 0),
S_AXI_HP0_RVALID => NLW_inst_S_AXI_HP0_RVALID_UNCONNECTED,
S_AXI_HP0_WACOUNT(5 downto 0) => NLW_inst_S_AXI_HP0_WACOUNT_UNCONNECTED(5 downto 0),
S_AXI_HP0_WCOUNT(7 downto 0) => NLW_inst_S_AXI_HP0_WCOUNT_UNCONNECTED(7 downto 0),
S_AXI_HP0_WDATA(63 downto 0) => B"0000000000000000000000000000000000000000000000000000000000000000",
S_AXI_HP0_WID(5 downto 0) => B"000000",
S_AXI_HP0_WLAST => '0',
S_AXI_HP0_WREADY => NLW_inst_S_AXI_HP0_WREADY_UNCONNECTED,
S_AXI_HP0_WRISSUECAP1_EN => '0',
S_AXI_HP0_WSTRB(7 downto 0) => B"00000000",
S_AXI_HP0_WVALID => '0',
S_AXI_HP1_ACLK => '0',
S_AXI_HP1_ARADDR(31 downto 0) => B"00000000000000000000000000000000",
S_AXI_HP1_ARBURST(1 downto 0) => B"00",
S_AXI_HP1_ARCACHE(3 downto 0) => B"0000",
S_AXI_HP1_ARESETN => NLW_inst_S_AXI_HP1_ARESETN_UNCONNECTED,
S_AXI_HP1_ARID(5 downto 0) => B"000000",
S_AXI_HP1_ARLEN(3 downto 0) => B"0000",
S_AXI_HP1_ARLOCK(1 downto 0) => B"00",
S_AXI_HP1_ARPROT(2 downto 0) => B"000",
S_AXI_HP1_ARQOS(3 downto 0) => B"0000",
S_AXI_HP1_ARREADY => NLW_inst_S_AXI_HP1_ARREADY_UNCONNECTED,
S_AXI_HP1_ARSIZE(2 downto 0) => B"000",
S_AXI_HP1_ARVALID => '0',
S_AXI_HP1_AWADDR(31 downto 0) => B"00000000000000000000000000000000",
S_AXI_HP1_AWBURST(1 downto 0) => B"00",
S_AXI_HP1_AWCACHE(3 downto 0) => B"0000",
S_AXI_HP1_AWID(5 downto 0) => B"000000",
S_AXI_HP1_AWLEN(3 downto 0) => B"0000",
S_AXI_HP1_AWLOCK(1 downto 0) => B"00",
S_AXI_HP1_AWPROT(2 downto 0) => B"000",
S_AXI_HP1_AWQOS(3 downto 0) => B"0000",
S_AXI_HP1_AWREADY => NLW_inst_S_AXI_HP1_AWREADY_UNCONNECTED,
S_AXI_HP1_AWSIZE(2 downto 0) => B"000",
S_AXI_HP1_AWVALID => '0',
S_AXI_HP1_BID(5 downto 0) => NLW_inst_S_AXI_HP1_BID_UNCONNECTED(5 downto 0),
S_AXI_HP1_BREADY => '0',
S_AXI_HP1_BRESP(1 downto 0) => NLW_inst_S_AXI_HP1_BRESP_UNCONNECTED(1 downto 0),
S_AXI_HP1_BVALID => NLW_inst_S_AXI_HP1_BVALID_UNCONNECTED,
S_AXI_HP1_RACOUNT(2 downto 0) => NLW_inst_S_AXI_HP1_RACOUNT_UNCONNECTED(2 downto 0),
S_AXI_HP1_RCOUNT(7 downto 0) => NLW_inst_S_AXI_HP1_RCOUNT_UNCONNECTED(7 downto 0),
S_AXI_HP1_RDATA(63 downto 0) => NLW_inst_S_AXI_HP1_RDATA_UNCONNECTED(63 downto 0),
S_AXI_HP1_RDISSUECAP1_EN => '0',
S_AXI_HP1_RID(5 downto 0) => NLW_inst_S_AXI_HP1_RID_UNCONNECTED(5 downto 0),
S_AXI_HP1_RLAST => NLW_inst_S_AXI_HP1_RLAST_UNCONNECTED,
S_AXI_HP1_RREADY => '0',
S_AXI_HP1_RRESP(1 downto 0) => NLW_inst_S_AXI_HP1_RRESP_UNCONNECTED(1 downto 0),
S_AXI_HP1_RVALID => NLW_inst_S_AXI_HP1_RVALID_UNCONNECTED,
S_AXI_HP1_WACOUNT(5 downto 0) => NLW_inst_S_AXI_HP1_WACOUNT_UNCONNECTED(5 downto 0),
S_AXI_HP1_WCOUNT(7 downto 0) => NLW_inst_S_AXI_HP1_WCOUNT_UNCONNECTED(7 downto 0),
S_AXI_HP1_WDATA(63 downto 0) => B"0000000000000000000000000000000000000000000000000000000000000000",
S_AXI_HP1_WID(5 downto 0) => B"000000",
S_AXI_HP1_WLAST => '0',
S_AXI_HP1_WREADY => NLW_inst_S_AXI_HP1_WREADY_UNCONNECTED,
S_AXI_HP1_WRISSUECAP1_EN => '0',
S_AXI_HP1_WSTRB(7 downto 0) => B"00000000",
S_AXI_HP1_WVALID => '0',
S_AXI_HP2_ACLK => '0',
S_AXI_HP2_ARADDR(31 downto 0) => B"00000000000000000000000000000000",
S_AXI_HP2_ARBURST(1 downto 0) => B"00",
S_AXI_HP2_ARCACHE(3 downto 0) => B"0000",
S_AXI_HP2_ARESETN => NLW_inst_S_AXI_HP2_ARESETN_UNCONNECTED,
S_AXI_HP2_ARID(5 downto 0) => B"000000",
S_AXI_HP2_ARLEN(3 downto 0) => B"0000",
S_AXI_HP2_ARLOCK(1 downto 0) => B"00",
S_AXI_HP2_ARPROT(2 downto 0) => B"000",
S_AXI_HP2_ARQOS(3 downto 0) => B"0000",
S_AXI_HP2_ARREADY => NLW_inst_S_AXI_HP2_ARREADY_UNCONNECTED,
S_AXI_HP2_ARSIZE(2 downto 0) => B"000",
S_AXI_HP2_ARVALID => '0',
S_AXI_HP2_AWADDR(31 downto 0) => B"00000000000000000000000000000000",
S_AXI_HP2_AWBURST(1 downto 0) => B"00",
S_AXI_HP2_AWCACHE(3 downto 0) => B"0000",
S_AXI_HP2_AWID(5 downto 0) => B"000000",
S_AXI_HP2_AWLEN(3 downto 0) => B"0000",
S_AXI_HP2_AWLOCK(1 downto 0) => B"00",
S_AXI_HP2_AWPROT(2 downto 0) => B"000",
S_AXI_HP2_AWQOS(3 downto 0) => B"0000",
S_AXI_HP2_AWREADY => NLW_inst_S_AXI_HP2_AWREADY_UNCONNECTED,
S_AXI_HP2_AWSIZE(2 downto 0) => B"000",
S_AXI_HP2_AWVALID => '0',
S_AXI_HP2_BID(5 downto 0) => NLW_inst_S_AXI_HP2_BID_UNCONNECTED(5 downto 0),
S_AXI_HP2_BREADY => '0',
S_AXI_HP2_BRESP(1 downto 0) => NLW_inst_S_AXI_HP2_BRESP_UNCONNECTED(1 downto 0),
S_AXI_HP2_BVALID => NLW_inst_S_AXI_HP2_BVALID_UNCONNECTED,
S_AXI_HP2_RACOUNT(2 downto 0) => NLW_inst_S_AXI_HP2_RACOUNT_UNCONNECTED(2 downto 0),
S_AXI_HP2_RCOUNT(7 downto 0) => NLW_inst_S_AXI_HP2_RCOUNT_UNCONNECTED(7 downto 0),
S_AXI_HP2_RDATA(63 downto 0) => NLW_inst_S_AXI_HP2_RDATA_UNCONNECTED(63 downto 0),
S_AXI_HP2_RDISSUECAP1_EN => '0',
S_AXI_HP2_RID(5 downto 0) => NLW_inst_S_AXI_HP2_RID_UNCONNECTED(5 downto 0),
S_AXI_HP2_RLAST => NLW_inst_S_AXI_HP2_RLAST_UNCONNECTED,
S_AXI_HP2_RREADY => '0',
S_AXI_HP2_RRESP(1 downto 0) => NLW_inst_S_AXI_HP2_RRESP_UNCONNECTED(1 downto 0),
S_AXI_HP2_RVALID => NLW_inst_S_AXI_HP2_RVALID_UNCONNECTED,
S_AXI_HP2_WACOUNT(5 downto 0) => NLW_inst_S_AXI_HP2_WACOUNT_UNCONNECTED(5 downto 0),
S_AXI_HP2_WCOUNT(7 downto 0) => NLW_inst_S_AXI_HP2_WCOUNT_UNCONNECTED(7 downto 0),
S_AXI_HP2_WDATA(63 downto 0) => B"0000000000000000000000000000000000000000000000000000000000000000",
S_AXI_HP2_WID(5 downto 0) => B"000000",
S_AXI_HP2_WLAST => '0',
S_AXI_HP2_WREADY => NLW_inst_S_AXI_HP2_WREADY_UNCONNECTED,
S_AXI_HP2_WRISSUECAP1_EN => '0',
S_AXI_HP2_WSTRB(7 downto 0) => B"00000000",
S_AXI_HP2_WVALID => '0',
S_AXI_HP3_ACLK => '0',
S_AXI_HP3_ARADDR(31 downto 0) => B"00000000000000000000000000000000",
S_AXI_HP3_ARBURST(1 downto 0) => B"00",
S_AXI_HP3_ARCACHE(3 downto 0) => B"0000",
S_AXI_HP3_ARESETN => NLW_inst_S_AXI_HP3_ARESETN_UNCONNECTED,
S_AXI_HP3_ARID(5 downto 0) => B"000000",
S_AXI_HP3_ARLEN(3 downto 0) => B"0000",
S_AXI_HP3_ARLOCK(1 downto 0) => B"00",
S_AXI_HP3_ARPROT(2 downto 0) => B"000",
S_AXI_HP3_ARQOS(3 downto 0) => B"0000",
S_AXI_HP3_ARREADY => NLW_inst_S_AXI_HP3_ARREADY_UNCONNECTED,
S_AXI_HP3_ARSIZE(2 downto 0) => B"000",
S_AXI_HP3_ARVALID => '0',
S_AXI_HP3_AWADDR(31 downto 0) => B"00000000000000000000000000000000",
S_AXI_HP3_AWBURST(1 downto 0) => B"00",
S_AXI_HP3_AWCACHE(3 downto 0) => B"0000",
S_AXI_HP3_AWID(5 downto 0) => B"000000",
S_AXI_HP3_AWLEN(3 downto 0) => B"0000",
S_AXI_HP3_AWLOCK(1 downto 0) => B"00",
S_AXI_HP3_AWPROT(2 downto 0) => B"000",
S_AXI_HP3_AWQOS(3 downto 0) => B"0000",
S_AXI_HP3_AWREADY => NLW_inst_S_AXI_HP3_AWREADY_UNCONNECTED,
S_AXI_HP3_AWSIZE(2 downto 0) => B"000",
S_AXI_HP3_AWVALID => '0',
S_AXI_HP3_BID(5 downto 0) => NLW_inst_S_AXI_HP3_BID_UNCONNECTED(5 downto 0),
S_AXI_HP3_BREADY => '0',
S_AXI_HP3_BRESP(1 downto 0) => NLW_inst_S_AXI_HP3_BRESP_UNCONNECTED(1 downto 0),
S_AXI_HP3_BVALID => NLW_inst_S_AXI_HP3_BVALID_UNCONNECTED,
S_AXI_HP3_RACOUNT(2 downto 0) => NLW_inst_S_AXI_HP3_RACOUNT_UNCONNECTED(2 downto 0),
S_AXI_HP3_RCOUNT(7 downto 0) => NLW_inst_S_AXI_HP3_RCOUNT_UNCONNECTED(7 downto 0),
S_AXI_HP3_RDATA(63 downto 0) => NLW_inst_S_AXI_HP3_RDATA_UNCONNECTED(63 downto 0),
S_AXI_HP3_RDISSUECAP1_EN => '0',
S_AXI_HP3_RID(5 downto 0) => NLW_inst_S_AXI_HP3_RID_UNCONNECTED(5 downto 0),
S_AXI_HP3_RLAST => NLW_inst_S_AXI_HP3_RLAST_UNCONNECTED,
S_AXI_HP3_RREADY => '0',
S_AXI_HP3_RRESP(1 downto 0) => NLW_inst_S_AXI_HP3_RRESP_UNCONNECTED(1 downto 0),
S_AXI_HP3_RVALID => NLW_inst_S_AXI_HP3_RVALID_UNCONNECTED,
S_AXI_HP3_WACOUNT(5 downto 0) => NLW_inst_S_AXI_HP3_WACOUNT_UNCONNECTED(5 downto 0),
S_AXI_HP3_WCOUNT(7 downto 0) => NLW_inst_S_AXI_HP3_WCOUNT_UNCONNECTED(7 downto 0),
S_AXI_HP3_WDATA(63 downto 0) => B"0000000000000000000000000000000000000000000000000000000000000000",
S_AXI_HP3_WID(5 downto 0) => B"000000",
S_AXI_HP3_WLAST => '0',
S_AXI_HP3_WREADY => NLW_inst_S_AXI_HP3_WREADY_UNCONNECTED,
S_AXI_HP3_WRISSUECAP1_EN => '0',
S_AXI_HP3_WSTRB(7 downto 0) => B"00000000",
S_AXI_HP3_WVALID => '0',
TRACE_CLK => '0',
TRACE_CLK_OUT => NLW_inst_TRACE_CLK_OUT_UNCONNECTED,
TRACE_CTL => NLW_inst_TRACE_CTL_UNCONNECTED,
TRACE_DATA(1 downto 0) => NLW_inst_TRACE_DATA_UNCONNECTED(1 downto 0),
TTC0_CLK0_IN => '0',
TTC0_CLK1_IN => '0',
TTC0_CLK2_IN => '0',
TTC0_WAVE0_OUT => NLW_inst_TTC0_WAVE0_OUT_UNCONNECTED,
TTC0_WAVE1_OUT => NLW_inst_TTC0_WAVE1_OUT_UNCONNECTED,
TTC0_WAVE2_OUT => NLW_inst_TTC0_WAVE2_OUT_UNCONNECTED,
TTC1_CLK0_IN => '0',
TTC1_CLK1_IN => '0',
TTC1_CLK2_IN => '0',
TTC1_WAVE0_OUT => NLW_inst_TTC1_WAVE0_OUT_UNCONNECTED,
TTC1_WAVE1_OUT => NLW_inst_TTC1_WAVE1_OUT_UNCONNECTED,
TTC1_WAVE2_OUT => NLW_inst_TTC1_WAVE2_OUT_UNCONNECTED,
UART0_CTSN => '0',
UART0_DCDN => '0',
UART0_DSRN => '0',
UART0_DTRN => NLW_inst_UART0_DTRN_UNCONNECTED,
UART0_RIN => '0',
UART0_RTSN => NLW_inst_UART0_RTSN_UNCONNECTED,
UART0_RX => '1',
UART0_TX => NLW_inst_UART0_TX_UNCONNECTED,
UART1_CTSN => '0',
UART1_DCDN => '0',
UART1_DSRN => '0',
UART1_DTRN => NLW_inst_UART1_DTRN_UNCONNECTED,
UART1_RIN => '0',
UART1_RTSN => NLW_inst_UART1_RTSN_UNCONNECTED,
UART1_RX => '1',
UART1_TX => NLW_inst_UART1_TX_UNCONNECTED,
USB0_PORT_INDCTL(1 downto 0) => USB0_PORT_INDCTL(1 downto 0),
USB0_VBUS_PWRFAULT => USB0_VBUS_PWRFAULT,
USB0_VBUS_PWRSELECT => USB0_VBUS_PWRSELECT,
USB1_PORT_INDCTL(1 downto 0) => NLW_inst_USB1_PORT_INDCTL_UNCONNECTED(1 downto 0),
USB1_VBUS_PWRFAULT => '0',
USB1_VBUS_PWRSELECT => NLW_inst_USB1_VBUS_PWRSELECT_UNCONNECTED,
WDT_CLK_IN => '0',
WDT_RST_OUT => NLW_inst_WDT_RST_OUT_UNCONNECTED
);
end STRUCTURE;
| mit | ceb1472f799e7bceace4caf86be23ded | 0.63915 | 2.765088 | false | false | false | false |
natsutan/NPU | fpga_implement/npu8/npu8.srcs/sources_1/ip/mult16_16/synth/mult16_16.vhd | 1 | 5,681 | -- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:mult_gen:12.0
-- IP Revision: 12
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY mult_gen_v12_0_12;
USE mult_gen_v12_0_12.mult_gen_v12_0_12;
ENTITY mult16_16 IS
PORT (
CLK : IN STD_LOGIC;
A : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
B : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
P : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END mult16_16;
ARCHITECTURE mult16_16_arch OF mult16_16 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF mult16_16_arch: ARCHITECTURE IS "yes";
COMPONENT mult_gen_v12_0_12 IS
GENERIC (
C_VERBOSITY : INTEGER;
C_MODEL_TYPE : INTEGER;
C_OPTIMIZE_GOAL : INTEGER;
C_XDEVICEFAMILY : STRING;
C_HAS_CE : INTEGER;
C_HAS_SCLR : INTEGER;
C_LATENCY : INTEGER;
C_A_WIDTH : INTEGER;
C_A_TYPE : INTEGER;
C_B_WIDTH : INTEGER;
C_B_TYPE : INTEGER;
C_OUT_HIGH : INTEGER;
C_OUT_LOW : INTEGER;
C_MULT_TYPE : INTEGER;
C_CE_OVERRIDES_SCLR : INTEGER;
C_CCM_IMP : INTEGER;
C_B_VALUE : STRING;
C_HAS_ZERO_DETECT : INTEGER;
C_ROUND_OUTPUT : INTEGER;
C_ROUND_PT : INTEGER
);
PORT (
CLK : IN STD_LOGIC;
A : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
B : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
CE : IN STD_LOGIC;
SCLR : IN STD_LOGIC;
P : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END COMPONENT mult_gen_v12_0_12;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF mult16_16_arch: ARCHITECTURE IS "mult_gen_v12_0_12,Vivado 2016.4";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF mult16_16_arch : ARCHITECTURE IS "mult16_16,mult_gen_v12_0_12,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF mult16_16_arch: ARCHITECTURE IS "mult16_16,mult_gen_v12_0_12,{x_ipProduct=Vivado 2016.4,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=mult_gen,x_ipVersion=12.0,x_ipCoreRevision=12,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_VERBOSITY=0,C_MODEL_TYPE=0,C_OPTIMIZE_GOAL=1,C_XDEVICEFAMILY=kintexu,C_HAS_CE=0,C_HAS_SCLR=0,C_LATENCY=4,C_A_WIDTH=16,C_A_TYPE=1,C_B_WIDTH=16,C_B_TYPE=1,C_OUT_HIGH=31,C_OUT_LOW=24,C_MULT_TYPE=0,C_CE_OVERRIDES_SCLR=0,C_CCM_IMP=0,C_B_VALUE=10000001,C_HAS_ZERO_DETECT=0,C_ROUND_OUTPUT=0,C_ROUND_PT=0}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF CLK: SIGNAL IS "xilinx.com:signal:clock:1.0 clk_intf CLK";
ATTRIBUTE X_INTERFACE_INFO OF A: SIGNAL IS "xilinx.com:signal:data:1.0 a_intf DATA";
ATTRIBUTE X_INTERFACE_INFO OF B: SIGNAL IS "xilinx.com:signal:data:1.0 b_intf DATA";
ATTRIBUTE X_INTERFACE_INFO OF P: SIGNAL IS "xilinx.com:signal:data:1.0 p_intf DATA";
BEGIN
U0 : mult_gen_v12_0_12
GENERIC MAP (
C_VERBOSITY => 0,
C_MODEL_TYPE => 0,
C_OPTIMIZE_GOAL => 1,
C_XDEVICEFAMILY => "kintexu",
C_HAS_CE => 0,
C_HAS_SCLR => 0,
C_LATENCY => 4,
C_A_WIDTH => 16,
C_A_TYPE => 1,
C_B_WIDTH => 16,
C_B_TYPE => 1,
C_OUT_HIGH => 31,
C_OUT_LOW => 24,
C_MULT_TYPE => 0,
C_CE_OVERRIDES_SCLR => 0,
C_CCM_IMP => 0,
C_B_VALUE => "10000001",
C_HAS_ZERO_DETECT => 0,
C_ROUND_OUTPUT => 0,
C_ROUND_PT => 0
)
PORT MAP (
CLK => CLK,
A => A,
B => B,
CE => '1',
SCLR => '0',
P => P
);
END mult16_16_arch;
| bsd-3-clause | 74ea9071f4514bb118475ef0a6c828e2 | 0.67981 | 3.363529 | false | false | false | false |
natsutan/NPU | fpga_implement/npu8/npu8.srcs/sources_1/ip/mul16_16/sim/mul16_16.vhd | 1 | 4,803 | -- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:mult_gen:12.0
-- IP Revision: 12
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY mult_gen_v12_0_12;
USE mult_gen_v12_0_12.mult_gen_v12_0_12;
ENTITY mul16_16 IS
PORT (
CLK : IN STD_LOGIC;
A : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
B : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
P : OUT STD_LOGIC_VECTOR(15 DOWNTO 0)
);
END mul16_16;
ARCHITECTURE mul16_16_arch OF mul16_16 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF mul16_16_arch: ARCHITECTURE IS "yes";
COMPONENT mult_gen_v12_0_12 IS
GENERIC (
C_VERBOSITY : INTEGER;
C_MODEL_TYPE : INTEGER;
C_OPTIMIZE_GOAL : INTEGER;
C_XDEVICEFAMILY : STRING;
C_HAS_CE : INTEGER;
C_HAS_SCLR : INTEGER;
C_LATENCY : INTEGER;
C_A_WIDTH : INTEGER;
C_A_TYPE : INTEGER;
C_B_WIDTH : INTEGER;
C_B_TYPE : INTEGER;
C_OUT_HIGH : INTEGER;
C_OUT_LOW : INTEGER;
C_MULT_TYPE : INTEGER;
C_CE_OVERRIDES_SCLR : INTEGER;
C_CCM_IMP : INTEGER;
C_B_VALUE : STRING;
C_HAS_ZERO_DETECT : INTEGER;
C_ROUND_OUTPUT : INTEGER;
C_ROUND_PT : INTEGER
);
PORT (
CLK : IN STD_LOGIC;
A : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
B : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
CE : IN STD_LOGIC;
SCLR : IN STD_LOGIC;
P : OUT STD_LOGIC_VECTOR(15 DOWNTO 0)
);
END COMPONENT mult_gen_v12_0_12;
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF CLK: SIGNAL IS "xilinx.com:signal:clock:1.0 clk_intf CLK";
ATTRIBUTE X_INTERFACE_INFO OF A: SIGNAL IS "xilinx.com:signal:data:1.0 a_intf DATA";
ATTRIBUTE X_INTERFACE_INFO OF B: SIGNAL IS "xilinx.com:signal:data:1.0 b_intf DATA";
ATTRIBUTE X_INTERFACE_INFO OF P: SIGNAL IS "xilinx.com:signal:data:1.0 p_intf DATA";
BEGIN
U0 : mult_gen_v12_0_12
GENERIC MAP (
C_VERBOSITY => 0,
C_MODEL_TYPE => 0,
C_OPTIMIZE_GOAL => 1,
C_XDEVICEFAMILY => "kintexu",
C_HAS_CE => 0,
C_HAS_SCLR => 0,
C_LATENCY => 4,
C_A_WIDTH => 16,
C_A_TYPE => 1,
C_B_WIDTH => 16,
C_B_TYPE => 1,
C_OUT_HIGH => 31,
C_OUT_LOW => 16,
C_MULT_TYPE => 0,
C_CE_OVERRIDES_SCLR => 0,
C_CCM_IMP => 0,
C_B_VALUE => "10000001",
C_HAS_ZERO_DETECT => 0,
C_ROUND_OUTPUT => 0,
C_ROUND_PT => 0
)
PORT MAP (
CLK => CLK,
A => A,
B => B,
CE => '1',
SCLR => '0',
P => P
);
END mul16_16_arch;
| bsd-3-clause | 1cc178688259da9fa9b0d6dbdb7dfa00 | 0.665834 | 3.578987 | false | false | false | false |
drhodes/jade2hdl | app-data/vhdl/prelude.vhdl | 1 | 10,183 | ------------------------------------------------------------------
-- VHDL PRELUDE --------------------------------------------------
-- /modmem1 ------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_textio.all;
use ieee.numeric_std.all;
use ieee.numeric_std_unsigned.all;
use std.textio.all;
-- modmem2 -- this is a prototype, eventually will be generated from JADE
-- memory unit parameters, but for now, it works for testing.
entity modmem2 is
port (ADDR_PORT1 : in std_logic_vector(1 downto 0);
OE_PORT1 : in std_logic_vector(0 downto 0);
WE_PORT1 : in std_logic_vector(0 downto 0);
CLK_PORT1 : in std_logic_vector(0 downto 0);
DATA_PORT1 : out std_logic_vector(1 downto 0));
end entity modmem2 ;
architecture behavioral of modmem2 is
type rom_array is array (NATURAL range <>) of std_logic_vector(1 downto 0);
constant data0: std_logic_vector (1 downto 0) := "00";
constant data1: std_logic_vector (1 downto 0) := "01";
constant data2: std_logic_vector (1 downto 0) := "10";
constant data3: std_logic_vector (1 downto 0) := "11";
constant rom: rom_array := (data0, data1, data2, data3);
begin
process (CLK_PORT1, OE_PORT1)
variable j: integer;
begin
j := to_integer(unsigned(ADDR_PORT1));
if falling_edge(CLK_PORT1(0)) then
DATA_PORT1 <= rom(j) when (OE_PORT1 = "1") else "UU";
end if;
end process;
end architecture behavioral ;
-- modmem1 -- this is a prototype, eventually will be generated from JADE
-- memory unit parameters, but for now, it works for testing.
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity modmem1 is
port (ADDR_PORT1 : in std_logic_vector(0 downto 0);
OE_PORT1 : in std_logic_vector(0 downto 0);
WE_PORT1 : in std_logic_vector(0 downto 0);
CLK_PORT1 : in std_logic_vector(0 downto 0);
DATA_PORT1 : out std_logic_vector(0 downto 0));
end entity modmem1 ;
architecture behavioral of modmem1 is
type rom_array is array (NATURAL range <>) of std_logic_vector(0 downto 0);
constant data0: std_logic_vector (0 downto 0) := "0";
constant data1: std_logic_vector (0 downto 0) := "1";
constant rom: rom_array := (data0, data1);
begin
process (CLK_PORT1, OE_PORT1)
variable j: integer;
begin
j := to_integer(unsigned(ADDR_PORT1));
if falling_edge(CLK_PORT1(0)) then
DATA_PORT1 <= rom(j) when (OE_PORT1 = "1") else "U";
end if;
end process;
end architecture behavioral ;
-- /gates/mod_gates_dreg ------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity mod_gates_dreg is
port (D : in std_logic_vector(0 downto 0);
CLK : in std_logic_vector(0 downto 0);
Q : out std_logic_vector(0 downto 0));
end entity mod_gates_dreg ;
architecture behavioral of mod_gates_dreg is
begin
process
begin
wait until CLK="1";
Q <= D;
end process;
end architecture behavioral ;
-- /gates/mod_gates_tristate ------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity mod_gates_tristate is
port (A : in std_logic_vector(0 downto 0);
E : in std_logic_vector(0 downto 0);
vout : out std_logic_vector(0 downto 0));
end entity mod_gates_tristate ;
architecture behavioral of mod_gates_tristate is
begin
vout <= A when (E = "1") else "U";
end architecture behavioral ;
-- /gates/and4 ------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity mod_gates_and4 is
port (a : in std_logic_vector(0 downto 0);
b : in std_logic_vector(0 downto 0);
c : in std_logic_vector(0 downto 0);
d : in std_logic_vector(0 downto 0);
vout : out std_logic_vector(0 downto 0));
end entity mod_gates_and4 ;
architecture behavioral of mod_gates_and4 is
begin
vout <= a and b and c and d;
end architecture behavioral ;
-- /gates/nand4 ------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity mod_gates_nand4 is
port (a : in std_logic_vector(0 downto 0);
b : in std_logic_vector(0 downto 0);
c : in std_logic_vector(0 downto 0);
d : in std_logic_vector(0 downto 0);
vout : out std_logic_vector(0 downto 0));
end entity mod_gates_nand4 ;
architecture behavioral of mod_gates_nand4 is
begin
vout <= not (a and b and c and d);
end architecture behavioral ;
-- /gates/nor4 ------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity mod_gates_nor4 is
port (a : in std_logic_vector(0 downto 0);
b : in std_logic_vector(0 downto 0);
c : in std_logic_vector(0 downto 0);
d : in std_logic_vector(0 downto 0);
vout : out std_logic_vector(0 downto 0));
end entity mod_gates_nor4 ;
architecture behavioral of mod_gates_nor4 is
begin
vout <= not (a or b or c or d);
end architecture behavioral ;
-- /gates/and3 ------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity mod_gates_and3 is
port (a : in std_logic_vector(0 downto 0);
b : in std_logic_vector(0 downto 0);
c : in std_logic_vector(0 downto 0);
vout : out std_logic_vector(0 downto 0));
end entity mod_gates_and3 ;
architecture behavioral of mod_gates_and3 is
begin
vout <= a and b and c;
end architecture behavioral ;
-- /gates/nand2 ------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity mod_gates_nand2 is
port (a : in std_logic_vector(0 downto 0);
b : in std_logic_vector(0 downto 0);
vout : out std_logic_vector(0 downto 0));
end entity mod_gates_nand2 ;
architecture behavioral of mod_gates_nand2 is
begin
vout <= a nand b;
end architecture behavioral ;
-- /gates/nor2 ------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity mod_gates_nor2 is
port (a : in std_logic_vector(0 downto 0);
b : in std_logic_vector(0 downto 0);
vout : out std_logic_vector(0 downto 0));
end entity mod_gates_nor2 ;
architecture behavioral of mod_gates_nor2 is
begin
vout <= a nor b;
end architecture behavioral ;
-- /gates/mux2 ------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity mod_gates_mux2 is
port (D0 : in std_logic_vector(0 downto 0);
D1 : in std_logic_vector(0 downto 0);
S : in std_logic_vector(0 downto 0);
Y : out std_logic_vector(0 downto 0)) ;
end entity mod_gates_mux2 ;
architecture behavioral of mod_gates_mux2 is
begin
Y <= D1 when (S = "1") else D0;
end architecture behavioral ;
-- /gates/mux4 ------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity mod_gates_mux4 is
port (D0 : in std_logic_vector(0 downto 0);
D1 : in std_logic_vector(0 downto 0);
D2 : in std_logic_vector(0 downto 0);
D3 : in std_logic_vector(0 downto 0);
S : in std_logic_vector(1 downto 0);
Y : out std_logic_vector(0 downto 0)) ;
end entity mod_gates_mux4 ;
architecture behavioral of mod_gates_mux4 is
begin
process (D0, D1, D2, D3, S, Y) is
begin
if (S="00") then Y <= D0;
elsif (S="01") then Y <= D1;
elsif (S="10") then Y <= D2;
elsif (S="11") then Y <= D3;
else Y <= "X";
end if;
end process;
end architecture behavioral ;
-- /gates/xor2 ------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity mod_gates_xor2 is
port (a : in std_logic_vector(0 downto 0);
b : in std_logic_vector(0 downto 0);
vout : out std_logic_vector(0 downto 0)) ;
end entity mod_gates_xor2 ;
architecture behavioral of mod_gates_xor2 is
begin
vout <= a xor b;
end architecture behavioral ;
-- /gates/and2 ------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity mod_gates_and2 is
port (a : in std_logic_vector(0 downto 0);
b : in std_logic_vector(0 downto 0);
vout : out std_logic_vector(0 downto 0)) ;
end entity mod_gates_and2 ;
architecture behavioral of mod_gates_and2 is
begin
vout <= a and b;
end architecture behavioral ;
-- /gates/inverter ------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity mod_gates_inverter is
port (a : in std_logic_vector(0 downto 0);
vout : out std_logic_vector(0 downto 0)) ;
end entity mod_gates_inverter ;
architecture behavioral of mod_gates_inverter is
begin
vout <= not a;
end architecture behavioral ;
-- /gates/buffer ------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity mod_gates_buffer is
port (a : in std_logic_vector(0 downto 0);
vout : out std_logic_vector(0 downto 0)) ;
end entity mod_gates_buffer ;
architecture behavioral of mod_gates_buffer is
begin
vout <= a;
end architecture behavioral ;
-- /gates/buffer_h ------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity mod_gates_buffer_h is
port (a : in std_logic_vector(0 downto 0);
vout : out std_logic_vector(0 downto 0)) ;
end entity mod_gates_buffer_h ;
architecture behavioral of mod_gates_buffer_h is
begin
vout <= a;
end architecture behavioral ;
-- /gates/or2 ------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity mod_gates_or2 is
port (a : in std_logic_vector(0 downto 0);
b : in std_logic_vector(0 downto 0);
vout : out std_logic_vector(0 downto 0)) ;
end entity mod_gates_or2 ;
architecture behavioral of mod_gates_or2 is
begin
vout <= a or b;
end architecture behavioral ;
-- END VHDL PRELUDE ----------------------------------------------
------------------------------------------------------------------
| bsd-3-clause | 688bcb47550aad6b73db5d6e9ebfed04 | 0.581656 | 3.579262 | false | false | false | false |
varunnagpaal/Digital-Hardware-Modelling | vhdl/filter/iir/bq/filter_device_memory_blocks.vhdl | 1 | 955 | library ieee;
use ieee.std_logic_1164.all;
entity device_ram_blocks is
generic ( INTENDED_DEVICE_FAMILY : string := "SmartFusion"; -- or "ZynqSoC"
WIDTH_AD : natural := 10; -- WIDTH_RDAD = WIDTH_WRAD
WIDTH_DATA : natural := 66; -- WIDTH_DATAIN = WIDTH_DATAOUT
OUP_REG : string := "UNREGISTERED" -- Set to "CLOCK0" if ouput data is to be registered
);
port( clock : in std_logic := '1';
aclr : in std_logic := '0';
rden : in std_logic := '1';
rdaddress : in std_logic_vector(WIDTH_AD-1 downto 0);
data_in : in std_logic_vector(WIDTH_DATA-1 downto 0);
wren : in std_logic := '0';
wraddress : in std_logic_vector(WIDTH_AD-1 downto 0);
data_out : out std_logic_vector(WIDTH_DATA-1 downto 0)
);
end entity device_ram_blocks;
architecture arch of device_ram_blocks is
begin
end arch;
| mit | 5c0aae2a833e0161b27f1e98587e8dd2 | 0.567539 | 3.183333 | false | false | false | false |
varunnagpaal/Digital-Hardware-Modelling | vhdl/filter/moving-avg/tb_fir_moving_avg_time_mux_multiple.vhdl | 1 | 6,024 | library IEEE;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
use ieee.std_logic_unsigned.all;
-- Testbench for FIR Moving Average filter which averages L points
entity Testbench is
end Testbench;
architecture test of Testbench is
-- Constants to initialize generics of DUT
constant L : natural := 256;
constant L_BW : natural := natural(ceil(log2(real(L))));
constant R : natural := 16;
constant R_BW : natural := natural(ceil(log2(real(R))));
constant M : natural := 16;
constant M_BW : natural := natural(ceil(log2(real(M))));
constant W : natural := 16;
-- Simulation control
constant CLK_CYCLE_TIME : time := 10 ns;
signal sim_end : boolean := false;
signal sample_cnt : natural := 256;--natural(2**(W-1));
-- Signals to connect ports of DUT
signal clk : std_logic := '0'; -- clock
signal reset_n : std_logic := '0'; -- active low asynchronous reset
signal fir_en : std_logic := '0'; -- handshake signal
signal fir_in : std_logic_vector( W-1 downto 0 ) := ( others => '0' ); -- sample inout x[n]
signal fir_out : std_logic_vector( W-1 downto 0 ) := ( others => '0' ); -- sample output y[n]
signal fir_rdy : std_logic := '0'; -- handshake signal
begin
-- create instance of FIR Filter (DUT)
DUT: entity work.fir(rtl)
generic map ( L => L, -- L = Filter length or number of points to be averaged
L_BW => L_BW, -- L_BW = Ceil(Log2(L))
R => R, -- R = Number of resources (adders and multiplexers)
R_BW => R_BW, -- R_BW = Ceil(Log2(R))
M => M, -- M = L/R = Samples to be processed per resource (adder)
M_BW => M_BW, -- M_BW = Ceil(Log2(M)) = number of select bits for M samples
W => W -- W = Bit width of input and output sample data (signed)
)
port map ( clk => clk, -- clock
reset_n => reset_n, -- active low asynchronous reset
fir_en => fir_en, -- handshake signal
fir_in => fir_in, -- sample inout x[n]
fir_out => fir_out, -- sample output y[n]
fir_rdy => fir_rdy -- handshake signal
);
-- Clock generation
clk_gen: process
begin
if( not sim_end ) then
clk <= '0';
wait for CLK_CYCLE_TIME/2;
clk <= '1';
wait for CLK_CYCLE_TIME/2;
else
wait;
end if;
end process clk_gen;
-- Reset generation
reset_n <= '0',
'1' after 1.3*CLK_CYCLE_TIME;
-- test vectors
stimulus : process
variable seed1, seed2 : positive := 1;
variable x: real := 0.0;
variable en: std_logic := '0';
procedure apply_stimulus( constant en : in std_logic;
constant x : in integer;
constant DELAY: in time ) is
begin
fir_en <= en;
fir_in <= std_logic_vector( to_signed( x, fir_in'LENGTH ) );
wait for DELAY;
end procedure apply_stimulus;
procedure apply_stimulus( constant en : in std_logic;
constant x : in integer ) is
begin
fir_en <= en;
fir_in <= std_logic_vector( to_signed( x, fir_in'LENGTH ) );
end procedure apply_stimulus;
begin
-- Reset
en := '0';
x := 0.0;
apply_stimulus( en, integer(x) );
wait until reset_n = '1';
for i in 1 to 4 loop
wait until falling_edge( clk );
end loop;
-- Enable filter and wait for M clock cycles (falling edges)
en := '1';
apply_stimulus( en, integer(x) );
for i in 1 to M loop
wait until falling_edge( clk );
end loop;
-- Apply simple increasing stimulus
for i in 0 to (sample_cnt-1) loop
apply_stimulus( en, i+1, M*CLK_CYCLE_TIME );
end loop;
-- Apply random stimulus
for i in 0 to (sample_cnt-1) loop
-- x = random number between 0.0 and 1.0 (exclusive)
uniform( seed1, seed2, x );
apply_stimulus( en, integer(floor(x * real(2**W - 1))), M*CLK_CYCLE_TIME );
end loop;
-- Apply upward trend stimulus
for i in 0 to (sample_cnt-1) loop
if ( i rem 4 = 0 ) then
-- x = random number between 0.0 and 1.0 (exclusive)
uniform( seed1, seed2, x );
apply_stimulus( en, integer(floor(x * real(2**W - 1))), M*CLK_CYCLE_TIME );
else
apply_stimulus( en, i, M*CLK_CYCLE_TIME );
end if;
end loop;
-- Apply downward trend stimulus
for i in (sample_cnt-1) downto 0 loop
wait until falling_edge( clk );
if ( i rem 4 = 0 ) then
-- x = random number between 0.0 and 1.0 (exclusive)
uniform( seed1, seed2, x );
apply_stimulus( en, integer(floor(x * real(2**W - 1))), M*CLK_CYCLE_TIME );
else
apply_stimulus( en, i, M*CLK_CYCLE_TIME );
end if;
end loop;
-- Disable the filter
en := '0';
apply_stimulus( en, 0, M*CLK_CYCLE_TIME );
-- End simulation
sim_end <= true;
wait;
end process stimulus;
end architecture test; | mit | e97ba8d7696e91d3149f41e0f81aaaa6 | 0.473108 | 4.075778 | false | false | false | false |
MartinCura/SistDig-TP4 | src/comps/adder.vhd | 1 | 917 | -- Sumador/Restador de N bits (A+-B)
-- Implementado con N full adders en cascada. Si control = '1', resta.
library ieee;
use ieee.std_logic_1164.all;
entity adder is
generic (N:natural:=8);
port(
A: in std_logic_vector(N-1 downto 0);
B: in std_logic_vector(N-1 downto 0);
control: in std_logic;
S: out std_logic_vector(N-1 downto 0);
Cout: out std_logic
);
end;
architecture adder_beh of adder is
signal Coutput: std_logic_vector(N downto 0);
signal B_aux: std_logic_vector(N-1 downto 0);
begin
Coutput(0) <= control;
ciclo: for i in 1 to N generate
B_aux(i-1) <= B(i-1) XOR control;
full_addr_1_bit_inst: entity work.full_addr_1_bit
port map(
A(i-1),
B_aux(i-1),
Coutput(i-1),
S(i-1),
Coutput(i)
);
end generate;
Cout <= Coutput(N);
end;
| gpl-3.0 | c7a98e5a4e349dc3b8280f318978865c | 0.559433 | 3.06689 | false | false | false | false |
varunnagpaal/Digital-Hardware-Modelling | xilinx-vivado/hls_tutorial_lab1/hls_tutorial_lab1.srcs/sources_1/bd/zybo_zynq_design/ip/zybo_zynq_design_auto_pc_0/zybo_zynq_design_auto_pc_0_sim_netlist.vhdl | 1 | 518,793 | -- Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2018.2 (win64) Build 2258646 Thu Jun 14 20:03:12 MDT 2018
-- Date : Sun Sep 22 02:35:49 2019
-- Host : varun-laptop running 64-bit Service Pack 1 (build 7601)
-- Command : write_vhdl -force -mode funcsim
-- d:/github/Digital-Hardware-Modelling/xilinx-vivado/hls_tutorial_lab1/hls_tutorial_lab1.srcs/sources_1/bd/zybo_zynq_design/ip/zybo_zynq_design_auto_pc_0/zybo_zynq_design_auto_pc_0_sim_netlist.vhdl
-- Design : zybo_zynq_design_auto_pc_0
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7z010clg400-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity zybo_zynq_design_auto_pc_0_axi_protocol_converter_v2_1_17_b2s_incr_cmd is
port (
next_pending_r_reg_0 : out STD_LOGIC;
\axaddr_incr_reg[0]_0\ : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 0 to 0 );
\axlen_cnt_reg[2]_0\ : out STD_LOGIC;
\axaddr_incr_reg[11]_0\ : out STD_LOGIC_VECTOR ( 10 downto 0 );
\m_axi_awaddr[11]\ : out STD_LOGIC;
\m_axi_awaddr[5]\ : out STD_LOGIC;
S : out STD_LOGIC_VECTOR ( 3 downto 0 );
incr_next_pending : in STD_LOGIC;
aclk : in STD_LOGIC;
sel_first_reg_0 : in STD_LOGIC;
E : in STD_LOGIC_VECTOR ( 0 to 0 );
\m_payload_i_reg[46]\ : in STD_LOGIC_VECTOR ( 9 downto 0 );
\m_payload_i_reg[47]\ : in STD_LOGIC;
\next\ : in STD_LOGIC;
axaddr_incr : in STD_LOGIC_VECTOR ( 11 downto 0 );
\state_reg[0]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\state_reg[1]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\state_reg[0]_rep\ : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of zybo_zynq_design_auto_pc_0_axi_protocol_converter_v2_1_17_b2s_incr_cmd : entity is "axi_protocol_converter_v2_1_17_b2s_incr_cmd";
end zybo_zynq_design_auto_pc_0_axi_protocol_converter_v2_1_17_b2s_incr_cmd;
architecture STRUCTURE of zybo_zynq_design_auto_pc_0_axi_protocol_converter_v2_1_17_b2s_incr_cmd is
signal \^q\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \axaddr_incr[0]_i_1_n_0\ : STD_LOGIC;
signal \axaddr_incr[10]_i_1_n_0\ : STD_LOGIC;
signal \axaddr_incr[11]_i_1_n_0\ : STD_LOGIC;
signal \axaddr_incr[11]_i_2_n_0\ : STD_LOGIC;
signal \axaddr_incr[1]_i_1_n_0\ : STD_LOGIC;
signal \axaddr_incr[2]_i_1_n_0\ : STD_LOGIC;
signal \axaddr_incr[3]_i_11_n_0\ : STD_LOGIC;
signal \axaddr_incr[3]_i_12_n_0\ : STD_LOGIC;
signal \axaddr_incr[3]_i_13_n_0\ : STD_LOGIC;
signal \axaddr_incr[3]_i_14_n_0\ : STD_LOGIC;
signal \axaddr_incr[3]_i_1_n_0\ : STD_LOGIC;
signal \axaddr_incr[4]_i_1_n_0\ : STD_LOGIC;
signal \axaddr_incr[5]_i_1_n_0\ : STD_LOGIC;
signal \axaddr_incr[6]_i_1_n_0\ : STD_LOGIC;
signal \axaddr_incr[7]_i_1_n_0\ : STD_LOGIC;
signal \axaddr_incr[8]_i_1_n_0\ : STD_LOGIC;
signal \axaddr_incr[9]_i_1_n_0\ : STD_LOGIC;
signal \^axaddr_incr_reg[0]_0\ : STD_LOGIC;
signal \^axaddr_incr_reg[11]_0\ : STD_LOGIC_VECTOR ( 10 downto 0 );
signal \axaddr_incr_reg[11]_i_4_n_1\ : STD_LOGIC;
signal \axaddr_incr_reg[11]_i_4_n_2\ : STD_LOGIC;
signal \axaddr_incr_reg[11]_i_4_n_3\ : STD_LOGIC;
signal \axaddr_incr_reg[11]_i_4_n_4\ : STD_LOGIC;
signal \axaddr_incr_reg[11]_i_4_n_5\ : STD_LOGIC;
signal \axaddr_incr_reg[11]_i_4_n_6\ : STD_LOGIC;
signal \axaddr_incr_reg[11]_i_4_n_7\ : STD_LOGIC;
signal \axaddr_incr_reg[3]_i_3_n_0\ : STD_LOGIC;
signal \axaddr_incr_reg[3]_i_3_n_1\ : STD_LOGIC;
signal \axaddr_incr_reg[3]_i_3_n_2\ : STD_LOGIC;
signal \axaddr_incr_reg[3]_i_3_n_3\ : STD_LOGIC;
signal \axaddr_incr_reg[3]_i_3_n_4\ : STD_LOGIC;
signal \axaddr_incr_reg[3]_i_3_n_5\ : STD_LOGIC;
signal \axaddr_incr_reg[3]_i_3_n_6\ : STD_LOGIC;
signal \axaddr_incr_reg[3]_i_3_n_7\ : STD_LOGIC;
signal \axaddr_incr_reg[7]_i_3_n_0\ : STD_LOGIC;
signal \axaddr_incr_reg[7]_i_3_n_1\ : STD_LOGIC;
signal \axaddr_incr_reg[7]_i_3_n_2\ : STD_LOGIC;
signal \axaddr_incr_reg[7]_i_3_n_3\ : STD_LOGIC;
signal \axaddr_incr_reg[7]_i_3_n_4\ : STD_LOGIC;
signal \axaddr_incr_reg[7]_i_3_n_5\ : STD_LOGIC;
signal \axaddr_incr_reg[7]_i_3_n_6\ : STD_LOGIC;
signal \axaddr_incr_reg[7]_i_3_n_7\ : STD_LOGIC;
signal \axaddr_incr_reg_n_0_[5]\ : STD_LOGIC;
signal \axlen_cnt[1]_i_1__0_n_0\ : STD_LOGIC;
signal \axlen_cnt[2]_i_1_n_0\ : STD_LOGIC;
signal \axlen_cnt[3]_i_2_n_0\ : STD_LOGIC;
signal \axlen_cnt[4]_i_1_n_0\ : STD_LOGIC;
signal \axlen_cnt[5]_i_1_n_0\ : STD_LOGIC;
signal \axlen_cnt[6]_i_1_n_0\ : STD_LOGIC;
signal \axlen_cnt[7]_i_2_n_0\ : STD_LOGIC;
signal \axlen_cnt[7]_i_3_n_0\ : STD_LOGIC;
signal \^axlen_cnt_reg[2]_0\ : STD_LOGIC;
signal \axlen_cnt_reg_n_0_[1]\ : STD_LOGIC;
signal \axlen_cnt_reg_n_0_[2]\ : STD_LOGIC;
signal \axlen_cnt_reg_n_0_[3]\ : STD_LOGIC;
signal \axlen_cnt_reg_n_0_[4]\ : STD_LOGIC;
signal \axlen_cnt_reg_n_0_[5]\ : STD_LOGIC;
signal \axlen_cnt_reg_n_0_[6]\ : STD_LOGIC;
signal \axlen_cnt_reg_n_0_[7]\ : STD_LOGIC;
signal next_pending_r_i_5_n_0 : STD_LOGIC;
signal \NLW_axaddr_incr_reg[11]_i_4_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \axaddr_incr[0]_i_1\ : label is "soft_lutpair116";
attribute SOFT_HLUTNM of \axaddr_incr[10]_i_1\ : label is "soft_lutpair117";
attribute SOFT_HLUTNM of \axaddr_incr[11]_i_2\ : label is "soft_lutpair116";
attribute SOFT_HLUTNM of \axaddr_incr[1]_i_1\ : label is "soft_lutpair117";
attribute SOFT_HLUTNM of \axaddr_incr[2]_i_1\ : label is "soft_lutpair115";
attribute SOFT_HLUTNM of \axaddr_incr[3]_i_1\ : label is "soft_lutpair120";
attribute SOFT_HLUTNM of \axaddr_incr[4]_i_1\ : label is "soft_lutpair118";
attribute SOFT_HLUTNM of \axaddr_incr[5]_i_1\ : label is "soft_lutpair119";
attribute SOFT_HLUTNM of \axaddr_incr[6]_i_1\ : label is "soft_lutpair119";
attribute SOFT_HLUTNM of \axaddr_incr[7]_i_1\ : label is "soft_lutpair120";
attribute SOFT_HLUTNM of \axaddr_incr[8]_i_1\ : label is "soft_lutpair118";
attribute SOFT_HLUTNM of \axaddr_incr[9]_i_1\ : label is "soft_lutpair115";
attribute SOFT_HLUTNM of \axlen_cnt[4]_i_1\ : label is "soft_lutpair112";
attribute SOFT_HLUTNM of \axlen_cnt[6]_i_1\ : label is "soft_lutpair114";
attribute SOFT_HLUTNM of \axlen_cnt[7]_i_2\ : label is "soft_lutpair114";
attribute SOFT_HLUTNM of \axlen_cnt[7]_i_3\ : label is "soft_lutpair112";
attribute SOFT_HLUTNM of \m_axi_awaddr[11]_INST_0_i_1\ : label is "soft_lutpair113";
attribute SOFT_HLUTNM of \m_axi_awaddr[5]_INST_0_i_1\ : label is "soft_lutpair113";
begin
Q(0) <= \^q\(0);
\axaddr_incr_reg[0]_0\ <= \^axaddr_incr_reg[0]_0\;
\axaddr_incr_reg[11]_0\(10 downto 0) <= \^axaddr_incr_reg[11]_0\(10 downto 0);
\axlen_cnt_reg[2]_0\ <= \^axlen_cnt_reg[2]_0\;
\axaddr_incr[0]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => axaddr_incr(0),
I1 => \^axaddr_incr_reg[0]_0\,
I2 => \axaddr_incr_reg[3]_i_3_n_7\,
O => \axaddr_incr[0]_i_1_n_0\
);
\axaddr_incr[10]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => axaddr_incr(10),
I1 => \^axaddr_incr_reg[0]_0\,
I2 => \axaddr_incr_reg[11]_i_4_n_5\,
O => \axaddr_incr[10]_i_1_n_0\
);
\axaddr_incr[11]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \^axaddr_incr_reg[0]_0\,
I1 => \next\,
O => \axaddr_incr[11]_i_1_n_0\
);
\axaddr_incr[11]_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => axaddr_incr(11),
I1 => \^axaddr_incr_reg[0]_0\,
I2 => \axaddr_incr_reg[11]_i_4_n_4\,
O => \axaddr_incr[11]_i_2_n_0\
);
\axaddr_incr[1]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => axaddr_incr(1),
I1 => \^axaddr_incr_reg[0]_0\,
I2 => \axaddr_incr_reg[3]_i_3_n_6\,
O => \axaddr_incr[1]_i_1_n_0\
);
\axaddr_incr[2]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => axaddr_incr(2),
I1 => \^axaddr_incr_reg[0]_0\,
I2 => \axaddr_incr_reg[3]_i_3_n_5\,
O => \axaddr_incr[2]_i_1_n_0\
);
\axaddr_incr[3]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => axaddr_incr(3),
I1 => \^axaddr_incr_reg[0]_0\,
I2 => \axaddr_incr_reg[3]_i_3_n_4\,
O => \axaddr_incr[3]_i_1_n_0\
);
\axaddr_incr[3]_i_10\: unisim.vcomponents.LUT4
generic map(
INIT => X"0102"
)
port map (
I0 => \m_payload_i_reg[46]\(0),
I1 => \m_payload_i_reg[46]\(6),
I2 => \m_payload_i_reg[46]\(5),
I3 => \next\,
O => S(0)
);
\axaddr_incr[3]_i_11\: unisim.vcomponents.LUT3
generic map(
INIT => X"6A"
)
port map (
I0 => \^axaddr_incr_reg[11]_0\(3),
I1 => \m_payload_i_reg[46]\(5),
I2 => \m_payload_i_reg[46]\(6),
O => \axaddr_incr[3]_i_11_n_0\
);
\axaddr_incr[3]_i_12\: unisim.vcomponents.LUT3
generic map(
INIT => X"9A"
)
port map (
I0 => \^axaddr_incr_reg[11]_0\(2),
I1 => \m_payload_i_reg[46]\(5),
I2 => \m_payload_i_reg[46]\(6),
O => \axaddr_incr[3]_i_12_n_0\
);
\axaddr_incr[3]_i_13\: unisim.vcomponents.LUT3
generic map(
INIT => X"9A"
)
port map (
I0 => \^axaddr_incr_reg[11]_0\(1),
I1 => \m_payload_i_reg[46]\(6),
I2 => \m_payload_i_reg[46]\(5),
O => \axaddr_incr[3]_i_13_n_0\
);
\axaddr_incr[3]_i_14\: unisim.vcomponents.LUT3
generic map(
INIT => X"A9"
)
port map (
I0 => \^axaddr_incr_reg[11]_0\(0),
I1 => \m_payload_i_reg[46]\(5),
I2 => \m_payload_i_reg[46]\(6),
O => \axaddr_incr[3]_i_14_n_0\
);
\axaddr_incr[3]_i_7\: unisim.vcomponents.LUT4
generic map(
INIT => X"6AAA"
)
port map (
I0 => \m_payload_i_reg[46]\(3),
I1 => \m_payload_i_reg[46]\(6),
I2 => \m_payload_i_reg[46]\(5),
I3 => \next\,
O => S(3)
);
\axaddr_incr[3]_i_8\: unisim.vcomponents.LUT4
generic map(
INIT => X"262A"
)
port map (
I0 => \m_payload_i_reg[46]\(2),
I1 => \m_payload_i_reg[46]\(6),
I2 => \m_payload_i_reg[46]\(5),
I3 => \next\,
O => S(2)
);
\axaddr_incr[3]_i_9\: unisim.vcomponents.LUT4
generic map(
INIT => X"060A"
)
port map (
I0 => \m_payload_i_reg[46]\(1),
I1 => \m_payload_i_reg[46]\(5),
I2 => \m_payload_i_reg[46]\(6),
I3 => \next\,
O => S(1)
);
\axaddr_incr[4]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => axaddr_incr(4),
I1 => \^axaddr_incr_reg[0]_0\,
I2 => \axaddr_incr_reg[7]_i_3_n_7\,
O => \axaddr_incr[4]_i_1_n_0\
);
\axaddr_incr[5]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => axaddr_incr(5),
I1 => \^axaddr_incr_reg[0]_0\,
I2 => \axaddr_incr_reg[7]_i_3_n_6\,
O => \axaddr_incr[5]_i_1_n_0\
);
\axaddr_incr[6]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => axaddr_incr(6),
I1 => \^axaddr_incr_reg[0]_0\,
I2 => \axaddr_incr_reg[7]_i_3_n_5\,
O => \axaddr_incr[6]_i_1_n_0\
);
\axaddr_incr[7]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => axaddr_incr(7),
I1 => \^axaddr_incr_reg[0]_0\,
I2 => \axaddr_incr_reg[7]_i_3_n_4\,
O => \axaddr_incr[7]_i_1_n_0\
);
\axaddr_incr[8]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => axaddr_incr(8),
I1 => \^axaddr_incr_reg[0]_0\,
I2 => \axaddr_incr_reg[11]_i_4_n_7\,
O => \axaddr_incr[8]_i_1_n_0\
);
\axaddr_incr[9]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => axaddr_incr(9),
I1 => \^axaddr_incr_reg[0]_0\,
I2 => \axaddr_incr_reg[11]_i_4_n_6\,
O => \axaddr_incr[9]_i_1_n_0\
);
\axaddr_incr_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \axaddr_incr[11]_i_1_n_0\,
D => \axaddr_incr[0]_i_1_n_0\,
Q => \^axaddr_incr_reg[11]_0\(0),
R => '0'
);
\axaddr_incr_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \axaddr_incr[11]_i_1_n_0\,
D => \axaddr_incr[10]_i_1_n_0\,
Q => \^axaddr_incr_reg[11]_0\(9),
R => '0'
);
\axaddr_incr_reg[11]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \axaddr_incr[11]_i_1_n_0\,
D => \axaddr_incr[11]_i_2_n_0\,
Q => \^axaddr_incr_reg[11]_0\(10),
R => '0'
);
\axaddr_incr_reg[11]_i_4\: unisim.vcomponents.CARRY4
port map (
CI => \axaddr_incr_reg[7]_i_3_n_0\,
CO(3) => \NLW_axaddr_incr_reg[11]_i_4_CO_UNCONNECTED\(3),
CO(2) => \axaddr_incr_reg[11]_i_4_n_1\,
CO(1) => \axaddr_incr_reg[11]_i_4_n_2\,
CO(0) => \axaddr_incr_reg[11]_i_4_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \axaddr_incr_reg[11]_i_4_n_4\,
O(2) => \axaddr_incr_reg[11]_i_4_n_5\,
O(1) => \axaddr_incr_reg[11]_i_4_n_6\,
O(0) => \axaddr_incr_reg[11]_i_4_n_7\,
S(3 downto 0) => \^axaddr_incr_reg[11]_0\(10 downto 7)
);
\axaddr_incr_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \axaddr_incr[11]_i_1_n_0\,
D => \axaddr_incr[1]_i_1_n_0\,
Q => \^axaddr_incr_reg[11]_0\(1),
R => '0'
);
\axaddr_incr_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \axaddr_incr[11]_i_1_n_0\,
D => \axaddr_incr[2]_i_1_n_0\,
Q => \^axaddr_incr_reg[11]_0\(2),
R => '0'
);
\axaddr_incr_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \axaddr_incr[11]_i_1_n_0\,
D => \axaddr_incr[3]_i_1_n_0\,
Q => \^axaddr_incr_reg[11]_0\(3),
R => '0'
);
\axaddr_incr_reg[3]_i_3\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \axaddr_incr_reg[3]_i_3_n_0\,
CO(2) => \axaddr_incr_reg[3]_i_3_n_1\,
CO(1) => \axaddr_incr_reg[3]_i_3_n_2\,
CO(0) => \axaddr_incr_reg[3]_i_3_n_3\,
CYINIT => '0',
DI(3 downto 0) => \^axaddr_incr_reg[11]_0\(3 downto 0),
O(3) => \axaddr_incr_reg[3]_i_3_n_4\,
O(2) => \axaddr_incr_reg[3]_i_3_n_5\,
O(1) => \axaddr_incr_reg[3]_i_3_n_6\,
O(0) => \axaddr_incr_reg[3]_i_3_n_7\,
S(3) => \axaddr_incr[3]_i_11_n_0\,
S(2) => \axaddr_incr[3]_i_12_n_0\,
S(1) => \axaddr_incr[3]_i_13_n_0\,
S(0) => \axaddr_incr[3]_i_14_n_0\
);
\axaddr_incr_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \axaddr_incr[11]_i_1_n_0\,
D => \axaddr_incr[4]_i_1_n_0\,
Q => \^axaddr_incr_reg[11]_0\(4),
R => '0'
);
\axaddr_incr_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \axaddr_incr[11]_i_1_n_0\,
D => \axaddr_incr[5]_i_1_n_0\,
Q => \axaddr_incr_reg_n_0_[5]\,
R => '0'
);
\axaddr_incr_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \axaddr_incr[11]_i_1_n_0\,
D => \axaddr_incr[6]_i_1_n_0\,
Q => \^axaddr_incr_reg[11]_0\(5),
R => '0'
);
\axaddr_incr_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \axaddr_incr[11]_i_1_n_0\,
D => \axaddr_incr[7]_i_1_n_0\,
Q => \^axaddr_incr_reg[11]_0\(6),
R => '0'
);
\axaddr_incr_reg[7]_i_3\: unisim.vcomponents.CARRY4
port map (
CI => \axaddr_incr_reg[3]_i_3_n_0\,
CO(3) => \axaddr_incr_reg[7]_i_3_n_0\,
CO(2) => \axaddr_incr_reg[7]_i_3_n_1\,
CO(1) => \axaddr_incr_reg[7]_i_3_n_2\,
CO(0) => \axaddr_incr_reg[7]_i_3_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \axaddr_incr_reg[7]_i_3_n_4\,
O(2) => \axaddr_incr_reg[7]_i_3_n_5\,
O(1) => \axaddr_incr_reg[7]_i_3_n_6\,
O(0) => \axaddr_incr_reg[7]_i_3_n_7\,
S(3 downto 2) => \^axaddr_incr_reg[11]_0\(6 downto 5),
S(1) => \axaddr_incr_reg_n_0_[5]\,
S(0) => \^axaddr_incr_reg[11]_0\(4)
);
\axaddr_incr_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \axaddr_incr[11]_i_1_n_0\,
D => \axaddr_incr[8]_i_1_n_0\,
Q => \^axaddr_incr_reg[11]_0\(7),
R => '0'
);
\axaddr_incr_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \axaddr_incr[11]_i_1_n_0\,
D => \axaddr_incr[9]_i_1_n_0\,
Q => \^axaddr_incr_reg[11]_0\(8),
R => '0'
);
\axlen_cnt[1]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"F88F8888"
)
port map (
I0 => E(0),
I1 => \m_payload_i_reg[46]\(8),
I2 => \axlen_cnt_reg_n_0_[1]\,
I3 => \^q\(0),
I4 => \^axlen_cnt_reg[2]_0\,
O => \axlen_cnt[1]_i_1__0_n_0\
);
\axlen_cnt[2]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFA900A900A900"
)
port map (
I0 => \axlen_cnt_reg_n_0_[2]\,
I1 => \^q\(0),
I2 => \axlen_cnt_reg_n_0_[1]\,
I3 => \^axlen_cnt_reg[2]_0\,
I4 => E(0),
I5 => \m_payload_i_reg[46]\(9),
O => \axlen_cnt[2]_i_1_n_0\
);
\axlen_cnt[3]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"EEEEEEEBAAAAAAAA"
)
port map (
I0 => \m_payload_i_reg[47]\,
I1 => \axlen_cnt_reg_n_0_[3]\,
I2 => \axlen_cnt_reg_n_0_[2]\,
I3 => \axlen_cnt_reg_n_0_[1]\,
I4 => \^q\(0),
I5 => \^axlen_cnt_reg[2]_0\,
O => \axlen_cnt[3]_i_2_n_0\
);
\axlen_cnt[4]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"AAAAAAA9"
)
port map (
I0 => \axlen_cnt_reg_n_0_[4]\,
I1 => \axlen_cnt_reg_n_0_[3]\,
I2 => \axlen_cnt_reg_n_0_[2]\,
I3 => \axlen_cnt_reg_n_0_[1]\,
I4 => \^q\(0),
O => \axlen_cnt[4]_i_1_n_0\
);
\axlen_cnt[5]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAAAAAAAAAAAAAA9"
)
port map (
I0 => \axlen_cnt_reg_n_0_[5]\,
I1 => \axlen_cnt_reg_n_0_[4]\,
I2 => \^q\(0),
I3 => \axlen_cnt_reg_n_0_[1]\,
I4 => \axlen_cnt_reg_n_0_[2]\,
I5 => \axlen_cnt_reg_n_0_[3]\,
O => \axlen_cnt[5]_i_1_n_0\
);
\axlen_cnt[6]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"9A"
)
port map (
I0 => \axlen_cnt_reg_n_0_[6]\,
I1 => \axlen_cnt_reg_n_0_[5]\,
I2 => \axlen_cnt[7]_i_3_n_0\,
O => \axlen_cnt[6]_i_1_n_0\
);
\axlen_cnt[7]_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"A9AA"
)
port map (
I0 => \axlen_cnt_reg_n_0_[7]\,
I1 => \axlen_cnt_reg_n_0_[6]\,
I2 => \axlen_cnt_reg_n_0_[5]\,
I3 => \axlen_cnt[7]_i_3_n_0\,
O => \axlen_cnt[7]_i_2_n_0\
);
\axlen_cnt[7]_i_3\: unisim.vcomponents.LUT5
generic map(
INIT => X"00000001"
)
port map (
I0 => \axlen_cnt_reg_n_0_[3]\,
I1 => \axlen_cnt_reg_n_0_[2]\,
I2 => \axlen_cnt_reg_n_0_[1]\,
I3 => \^q\(0),
I4 => \axlen_cnt_reg_n_0_[4]\,
O => \axlen_cnt[7]_i_3_n_0\
);
\axlen_cnt_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \state_reg[0]\(0),
D => \state_reg[1]\(0),
Q => \^q\(0),
R => '0'
);
\axlen_cnt_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \state_reg[0]\(0),
D => \axlen_cnt[1]_i_1__0_n_0\,
Q => \axlen_cnt_reg_n_0_[1]\,
R => '0'
);
\axlen_cnt_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \state_reg[0]\(0),
D => \axlen_cnt[2]_i_1_n_0\,
Q => \axlen_cnt_reg_n_0_[2]\,
R => '0'
);
\axlen_cnt_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \state_reg[0]\(0),
D => \axlen_cnt[3]_i_2_n_0\,
Q => \axlen_cnt_reg_n_0_[3]\,
R => '0'
);
\axlen_cnt_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \state_reg[0]\(0),
D => \axlen_cnt[4]_i_1_n_0\,
Q => \axlen_cnt_reg_n_0_[4]\,
R => \state_reg[0]_rep\
);
\axlen_cnt_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \state_reg[0]\(0),
D => \axlen_cnt[5]_i_1_n_0\,
Q => \axlen_cnt_reg_n_0_[5]\,
R => \state_reg[0]_rep\
);
\axlen_cnt_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \state_reg[0]\(0),
D => \axlen_cnt[6]_i_1_n_0\,
Q => \axlen_cnt_reg_n_0_[6]\,
R => \state_reg[0]_rep\
);
\axlen_cnt_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \state_reg[0]\(0),
D => \axlen_cnt[7]_i_2_n_0\,
Q => \axlen_cnt_reg_n_0_[7]\,
R => \state_reg[0]_rep\
);
\m_axi_awaddr[11]_INST_0_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"B"
)
port map (
I0 => \^axaddr_incr_reg[0]_0\,
I1 => \m_payload_i_reg[46]\(7),
O => \m_axi_awaddr[11]\
);
\m_axi_awaddr[5]_INST_0_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"EF40"
)
port map (
I0 => \^axaddr_incr_reg[0]_0\,
I1 => \axaddr_incr_reg_n_0_[5]\,
I2 => \m_payload_i_reg[46]\(7),
I3 => \m_payload_i_reg[46]\(4),
O => \m_axi_awaddr[5]\
);
\next_pending_r_i_3__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"55545555"
)
port map (
I0 => E(0),
I1 => \axlen_cnt_reg_n_0_[7]\,
I2 => \axlen_cnt_reg_n_0_[5]\,
I3 => \axlen_cnt_reg_n_0_[6]\,
I4 => next_pending_r_i_5_n_0,
O => \^axlen_cnt_reg[2]_0\
);
next_pending_r_i_5: unisim.vcomponents.LUT4
generic map(
INIT => X"0001"
)
port map (
I0 => \axlen_cnt_reg_n_0_[1]\,
I1 => \axlen_cnt_reg_n_0_[4]\,
I2 => \axlen_cnt_reg_n_0_[2]\,
I3 => \axlen_cnt_reg_n_0_[3]\,
O => next_pending_r_i_5_n_0
);
next_pending_r_reg: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => incr_next_pending,
Q => next_pending_r_reg_0,
R => '0'
);
sel_first_reg: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => sel_first_reg_0,
Q => \^axaddr_incr_reg[0]_0\,
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity zybo_zynq_design_auto_pc_0_axi_protocol_converter_v2_1_17_b2s_incr_cmd_2 is
port (
incr_next_pending : out STD_LOGIC;
\axaddr_incr_reg[0]_0\ : out STD_LOGIC;
\axlen_cnt_reg[0]_0\ : out STD_LOGIC;
\axaddr_incr_reg[11]_0\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
\m_axi_araddr[11]\ : out STD_LOGIC;
\m_axi_araddr[5]\ : out STD_LOGIC;
\m_axi_araddr[3]\ : out STD_LOGIC;
\m_axi_araddr[2]\ : out STD_LOGIC;
\m_axi_araddr[1]\ : out STD_LOGIC;
S : out STD_LOGIC_VECTOR ( 3 downto 0 );
aclk : in STD_LOGIC;
sel_first_reg_0 : in STD_LOGIC;
E : in STD_LOGIC_VECTOR ( 0 to 0 );
Q : in STD_LOGIC_VECTOR ( 10 downto 0 );
\m_payload_i_reg[47]\ : in STD_LOGIC;
\state_reg[1]_rep\ : in STD_LOGIC;
\m_payload_i_reg[47]_0\ : in STD_LOGIC;
O : in STD_LOGIC_VECTOR ( 3 downto 0 );
\m_payload_i_reg[7]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\m_payload_i_reg[3]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
si_rs_arvalid : in STD_LOGIC;
\state_reg[0]_rep\ : in STD_LOGIC;
m_valid_i_reg : in STD_LOGIC_VECTOR ( 0 to 0 );
\state_reg[1]\ : in STD_LOGIC;
sel_first_reg_1 : in STD_LOGIC_VECTOR ( 0 to 0 );
\state_reg[1]_0\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_arready : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of zybo_zynq_design_auto_pc_0_axi_protocol_converter_v2_1_17_b2s_incr_cmd_2 : entity is "axi_protocol_converter_v2_1_17_b2s_incr_cmd";
end zybo_zynq_design_auto_pc_0_axi_protocol_converter_v2_1_17_b2s_incr_cmd_2;
architecture STRUCTURE of zybo_zynq_design_auto_pc_0_axi_protocol_converter_v2_1_17_b2s_incr_cmd_2 is
signal \axaddr_incr[0]_i_1__0_n_0\ : STD_LOGIC;
signal \axaddr_incr[10]_i_1__0_n_0\ : STD_LOGIC;
signal \axaddr_incr[11]_i_2__0_n_0\ : STD_LOGIC;
signal \axaddr_incr[1]_i_1__0_n_0\ : STD_LOGIC;
signal \axaddr_incr[2]_i_1__0_n_0\ : STD_LOGIC;
signal \axaddr_incr[3]_i_11_n_0\ : STD_LOGIC;
signal \axaddr_incr[3]_i_12_n_0\ : STD_LOGIC;
signal \axaddr_incr[3]_i_13_n_0\ : STD_LOGIC;
signal \axaddr_incr[3]_i_14_n_0\ : STD_LOGIC;
signal \axaddr_incr[3]_i_1__0_n_0\ : STD_LOGIC;
signal \axaddr_incr[4]_i_1__0_n_0\ : STD_LOGIC;
signal \axaddr_incr[5]_i_1__0_n_0\ : STD_LOGIC;
signal \axaddr_incr[6]_i_1__0_n_0\ : STD_LOGIC;
signal \axaddr_incr[7]_i_1__0_n_0\ : STD_LOGIC;
signal \axaddr_incr[8]_i_1__0_n_0\ : STD_LOGIC;
signal \axaddr_incr[9]_i_1__0_n_0\ : STD_LOGIC;
signal \^axaddr_incr_reg[0]_0\ : STD_LOGIC;
signal \^axaddr_incr_reg[11]_0\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \axaddr_incr_reg[11]_i_4__0_n_1\ : STD_LOGIC;
signal \axaddr_incr_reg[11]_i_4__0_n_2\ : STD_LOGIC;
signal \axaddr_incr_reg[11]_i_4__0_n_3\ : STD_LOGIC;
signal \axaddr_incr_reg[11]_i_4__0_n_4\ : STD_LOGIC;
signal \axaddr_incr_reg[11]_i_4__0_n_5\ : STD_LOGIC;
signal \axaddr_incr_reg[11]_i_4__0_n_6\ : STD_LOGIC;
signal \axaddr_incr_reg[11]_i_4__0_n_7\ : STD_LOGIC;
signal \axaddr_incr_reg[3]_i_3__0_n_0\ : STD_LOGIC;
signal \axaddr_incr_reg[3]_i_3__0_n_1\ : STD_LOGIC;
signal \axaddr_incr_reg[3]_i_3__0_n_2\ : STD_LOGIC;
signal \axaddr_incr_reg[3]_i_3__0_n_3\ : STD_LOGIC;
signal \axaddr_incr_reg[3]_i_3__0_n_4\ : STD_LOGIC;
signal \axaddr_incr_reg[3]_i_3__0_n_5\ : STD_LOGIC;
signal \axaddr_incr_reg[3]_i_3__0_n_6\ : STD_LOGIC;
signal \axaddr_incr_reg[3]_i_3__0_n_7\ : STD_LOGIC;
signal \axaddr_incr_reg[7]_i_3__0_n_0\ : STD_LOGIC;
signal \axaddr_incr_reg[7]_i_3__0_n_1\ : STD_LOGIC;
signal \axaddr_incr_reg[7]_i_3__0_n_2\ : STD_LOGIC;
signal \axaddr_incr_reg[7]_i_3__0_n_3\ : STD_LOGIC;
signal \axaddr_incr_reg[7]_i_3__0_n_4\ : STD_LOGIC;
signal \axaddr_incr_reg[7]_i_3__0_n_5\ : STD_LOGIC;
signal \axaddr_incr_reg[7]_i_3__0_n_6\ : STD_LOGIC;
signal \axaddr_incr_reg[7]_i_3__0_n_7\ : STD_LOGIC;
signal \axaddr_incr_reg_n_0_[1]\ : STD_LOGIC;
signal \axaddr_incr_reg_n_0_[2]\ : STD_LOGIC;
signal \axaddr_incr_reg_n_0_[3]\ : STD_LOGIC;
signal \axaddr_incr_reg_n_0_[5]\ : STD_LOGIC;
signal \axlen_cnt[0]_i_1__2_n_0\ : STD_LOGIC;
signal \axlen_cnt[1]_i_1__1_n_0\ : STD_LOGIC;
signal \axlen_cnt[2]_i_1__1_n_0\ : STD_LOGIC;
signal \axlen_cnt[3]_i_2__0_n_0\ : STD_LOGIC;
signal \axlen_cnt[4]_i_1__0_n_0\ : STD_LOGIC;
signal \axlen_cnt[5]_i_1__0_n_0\ : STD_LOGIC;
signal \axlen_cnt[6]_i_1__0_n_0\ : STD_LOGIC;
signal \axlen_cnt[7]_i_2__0_n_0\ : STD_LOGIC;
signal \axlen_cnt[7]_i_3__0_n_0\ : STD_LOGIC;
signal \^axlen_cnt_reg[0]_0\ : STD_LOGIC;
signal \axlen_cnt_reg_n_0_[0]\ : STD_LOGIC;
signal \axlen_cnt_reg_n_0_[1]\ : STD_LOGIC;
signal \axlen_cnt_reg_n_0_[2]\ : STD_LOGIC;
signal \axlen_cnt_reg_n_0_[3]\ : STD_LOGIC;
signal \axlen_cnt_reg_n_0_[4]\ : STD_LOGIC;
signal \axlen_cnt_reg_n_0_[5]\ : STD_LOGIC;
signal \axlen_cnt_reg_n_0_[6]\ : STD_LOGIC;
signal \axlen_cnt_reg_n_0_[7]\ : STD_LOGIC;
signal \^incr_next_pending\ : STD_LOGIC;
signal \next_pending_r_i_2__0_n_0\ : STD_LOGIC;
signal \next_pending_r_i_4__0_n_0\ : STD_LOGIC;
signal next_pending_r_reg_n_0 : STD_LOGIC;
signal \NLW_axaddr_incr_reg[11]_i_4__0_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \axaddr_incr[0]_i_1__0\ : label is "soft_lutpair12";
attribute SOFT_HLUTNM of \axaddr_incr[10]_i_1__0\ : label is "soft_lutpair12";
attribute SOFT_HLUTNM of \axaddr_incr[11]_i_2__0\ : label is "soft_lutpair11";
attribute SOFT_HLUTNM of \axaddr_incr[1]_i_1__0\ : label is "soft_lutpair15";
attribute SOFT_HLUTNM of \axaddr_incr[2]_i_1__0\ : label is "soft_lutpair15";
attribute SOFT_HLUTNM of \axaddr_incr[3]_i_1__0\ : label is "soft_lutpair13";
attribute SOFT_HLUTNM of \axaddr_incr[4]_i_1__0\ : label is "soft_lutpair14";
attribute SOFT_HLUTNM of \axaddr_incr[5]_i_1__0\ : label is "soft_lutpair11";
attribute SOFT_HLUTNM of \axaddr_incr[6]_i_1__0\ : label is "soft_lutpair14";
attribute SOFT_HLUTNM of \axaddr_incr[7]_i_1__0\ : label is "soft_lutpair10";
attribute SOFT_HLUTNM of \axaddr_incr[8]_i_1__0\ : label is "soft_lutpair13";
attribute SOFT_HLUTNM of \axaddr_incr[9]_i_1__0\ : label is "soft_lutpair10";
attribute SOFT_HLUTNM of \axlen_cnt[3]_i_4\ : label is "soft_lutpair7";
attribute SOFT_HLUTNM of \axlen_cnt[4]_i_1__0\ : label is "soft_lutpair6";
attribute SOFT_HLUTNM of \axlen_cnt[6]_i_1__0\ : label is "soft_lutpair9";
attribute SOFT_HLUTNM of \axlen_cnt[7]_i_2__0\ : label is "soft_lutpair9";
attribute SOFT_HLUTNM of \axlen_cnt[7]_i_3__0\ : label is "soft_lutpair6";
attribute SOFT_HLUTNM of \m_axi_araddr[11]_INST_0_i_1\ : label is "soft_lutpair8";
attribute SOFT_HLUTNM of \m_axi_araddr[1]_INST_0_i_1\ : label is "soft_lutpair8";
attribute SOFT_HLUTNM of \next_pending_r_i_2__0\ : label is "soft_lutpair7";
begin
\axaddr_incr_reg[0]_0\ <= \^axaddr_incr_reg[0]_0\;
\axaddr_incr_reg[11]_0\(7 downto 0) <= \^axaddr_incr_reg[11]_0\(7 downto 0);
\axlen_cnt_reg[0]_0\ <= \^axlen_cnt_reg[0]_0\;
incr_next_pending <= \^incr_next_pending\;
\axaddr_incr[0]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \m_payload_i_reg[3]\(0),
I1 => \^axaddr_incr_reg[0]_0\,
I2 => \axaddr_incr_reg[3]_i_3__0_n_7\,
O => \axaddr_incr[0]_i_1__0_n_0\
);
\axaddr_incr[10]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => O(2),
I1 => \^axaddr_incr_reg[0]_0\,
I2 => \axaddr_incr_reg[11]_i_4__0_n_5\,
O => \axaddr_incr[10]_i_1__0_n_0\
);
\axaddr_incr[11]_i_2__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => O(3),
I1 => \^axaddr_incr_reg[0]_0\,
I2 => \axaddr_incr_reg[11]_i_4__0_n_4\,
O => \axaddr_incr[11]_i_2__0_n_0\
);
\axaddr_incr[1]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \m_payload_i_reg[3]\(1),
I1 => \^axaddr_incr_reg[0]_0\,
I2 => \axaddr_incr_reg[3]_i_3__0_n_6\,
O => \axaddr_incr[1]_i_1__0_n_0\
);
\axaddr_incr[2]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \m_payload_i_reg[3]\(2),
I1 => \^axaddr_incr_reg[0]_0\,
I2 => \axaddr_incr_reg[3]_i_3__0_n_5\,
O => \axaddr_incr[2]_i_1__0_n_0\
);
\axaddr_incr[3]_i_10\: unisim.vcomponents.LUT6
generic map(
INIT => X"0201020202020202"
)
port map (
I0 => Q(0),
I1 => Q(6),
I2 => Q(5),
I3 => \state_reg[1]_0\(1),
I4 => \state_reg[1]_0\(0),
I5 => m_axi_arready,
O => S(0)
);
\axaddr_incr[3]_i_11\: unisim.vcomponents.LUT3
generic map(
INIT => X"6A"
)
port map (
I0 => \axaddr_incr_reg_n_0_[3]\,
I1 => Q(5),
I2 => Q(6),
O => \axaddr_incr[3]_i_11_n_0\
);
\axaddr_incr[3]_i_12\: unisim.vcomponents.LUT3
generic map(
INIT => X"9A"
)
port map (
I0 => \axaddr_incr_reg_n_0_[2]\,
I1 => Q(5),
I2 => Q(6),
O => \axaddr_incr[3]_i_12_n_0\
);
\axaddr_incr[3]_i_13\: unisim.vcomponents.LUT3
generic map(
INIT => X"9A"
)
port map (
I0 => \axaddr_incr_reg_n_0_[1]\,
I1 => Q(6),
I2 => Q(5),
O => \axaddr_incr[3]_i_13_n_0\
);
\axaddr_incr[3]_i_14\: unisim.vcomponents.LUT3
generic map(
INIT => X"A9"
)
port map (
I0 => \^axaddr_incr_reg[11]_0\(0),
I1 => Q(5),
I2 => Q(6),
O => \axaddr_incr[3]_i_14_n_0\
);
\axaddr_incr[3]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \m_payload_i_reg[3]\(3),
I1 => \^axaddr_incr_reg[0]_0\,
I2 => \axaddr_incr_reg[3]_i_3__0_n_4\,
O => \axaddr_incr[3]_i_1__0_n_0\
);
\axaddr_incr[3]_i_7\: unisim.vcomponents.LUT6
generic map(
INIT => X"AA6AAAAAAAAAAAAA"
)
port map (
I0 => Q(3),
I1 => Q(6),
I2 => Q(5),
I3 => \state_reg[1]_0\(1),
I4 => \state_reg[1]_0\(0),
I5 => m_axi_arready,
O => S(3)
);
\axaddr_incr[3]_i_8\: unisim.vcomponents.LUT6
generic map(
INIT => X"2A262A2A2A2A2A2A"
)
port map (
I0 => Q(2),
I1 => Q(6),
I2 => Q(5),
I3 => \state_reg[1]_0\(1),
I4 => \state_reg[1]_0\(0),
I5 => m_axi_arready,
O => S(2)
);
\axaddr_incr[3]_i_9\: unisim.vcomponents.LUT6
generic map(
INIT => X"0A060A0A0A0A0A0A"
)
port map (
I0 => Q(1),
I1 => Q(5),
I2 => Q(6),
I3 => \state_reg[1]_0\(1),
I4 => \state_reg[1]_0\(0),
I5 => m_axi_arready,
O => S(1)
);
\axaddr_incr[4]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \m_payload_i_reg[7]\(0),
I1 => \^axaddr_incr_reg[0]_0\,
I2 => \axaddr_incr_reg[7]_i_3__0_n_7\,
O => \axaddr_incr[4]_i_1__0_n_0\
);
\axaddr_incr[5]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \m_payload_i_reg[7]\(1),
I1 => \^axaddr_incr_reg[0]_0\,
I2 => \axaddr_incr_reg[7]_i_3__0_n_6\,
O => \axaddr_incr[5]_i_1__0_n_0\
);
\axaddr_incr[6]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \m_payload_i_reg[7]\(2),
I1 => \^axaddr_incr_reg[0]_0\,
I2 => \axaddr_incr_reg[7]_i_3__0_n_5\,
O => \axaddr_incr[6]_i_1__0_n_0\
);
\axaddr_incr[7]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \m_payload_i_reg[7]\(3),
I1 => \^axaddr_incr_reg[0]_0\,
I2 => \axaddr_incr_reg[7]_i_3__0_n_4\,
O => \axaddr_incr[7]_i_1__0_n_0\
);
\axaddr_incr[8]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => O(0),
I1 => \^axaddr_incr_reg[0]_0\,
I2 => \axaddr_incr_reg[11]_i_4__0_n_7\,
O => \axaddr_incr[8]_i_1__0_n_0\
);
\axaddr_incr[9]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => O(1),
I1 => \^axaddr_incr_reg[0]_0\,
I2 => \axaddr_incr_reg[11]_i_4__0_n_6\,
O => \axaddr_incr[9]_i_1__0_n_0\
);
\axaddr_incr_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => sel_first_reg_1(0),
D => \axaddr_incr[0]_i_1__0_n_0\,
Q => \^axaddr_incr_reg[11]_0\(0),
R => '0'
);
\axaddr_incr_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => sel_first_reg_1(0),
D => \axaddr_incr[10]_i_1__0_n_0\,
Q => \^axaddr_incr_reg[11]_0\(6),
R => '0'
);
\axaddr_incr_reg[11]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => sel_first_reg_1(0),
D => \axaddr_incr[11]_i_2__0_n_0\,
Q => \^axaddr_incr_reg[11]_0\(7),
R => '0'
);
\axaddr_incr_reg[11]_i_4__0\: unisim.vcomponents.CARRY4
port map (
CI => \axaddr_incr_reg[7]_i_3__0_n_0\,
CO(3) => \NLW_axaddr_incr_reg[11]_i_4__0_CO_UNCONNECTED\(3),
CO(2) => \axaddr_incr_reg[11]_i_4__0_n_1\,
CO(1) => \axaddr_incr_reg[11]_i_4__0_n_2\,
CO(0) => \axaddr_incr_reg[11]_i_4__0_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \axaddr_incr_reg[11]_i_4__0_n_4\,
O(2) => \axaddr_incr_reg[11]_i_4__0_n_5\,
O(1) => \axaddr_incr_reg[11]_i_4__0_n_6\,
O(0) => \axaddr_incr_reg[11]_i_4__0_n_7\,
S(3 downto 0) => \^axaddr_incr_reg[11]_0\(7 downto 4)
);
\axaddr_incr_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => sel_first_reg_1(0),
D => \axaddr_incr[1]_i_1__0_n_0\,
Q => \axaddr_incr_reg_n_0_[1]\,
R => '0'
);
\axaddr_incr_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => sel_first_reg_1(0),
D => \axaddr_incr[2]_i_1__0_n_0\,
Q => \axaddr_incr_reg_n_0_[2]\,
R => '0'
);
\axaddr_incr_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => sel_first_reg_1(0),
D => \axaddr_incr[3]_i_1__0_n_0\,
Q => \axaddr_incr_reg_n_0_[3]\,
R => '0'
);
\axaddr_incr_reg[3]_i_3__0\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \axaddr_incr_reg[3]_i_3__0_n_0\,
CO(2) => \axaddr_incr_reg[3]_i_3__0_n_1\,
CO(1) => \axaddr_incr_reg[3]_i_3__0_n_2\,
CO(0) => \axaddr_incr_reg[3]_i_3__0_n_3\,
CYINIT => '0',
DI(3) => \axaddr_incr_reg_n_0_[3]\,
DI(2) => \axaddr_incr_reg_n_0_[2]\,
DI(1) => \axaddr_incr_reg_n_0_[1]\,
DI(0) => \^axaddr_incr_reg[11]_0\(0),
O(3) => \axaddr_incr_reg[3]_i_3__0_n_4\,
O(2) => \axaddr_incr_reg[3]_i_3__0_n_5\,
O(1) => \axaddr_incr_reg[3]_i_3__0_n_6\,
O(0) => \axaddr_incr_reg[3]_i_3__0_n_7\,
S(3) => \axaddr_incr[3]_i_11_n_0\,
S(2) => \axaddr_incr[3]_i_12_n_0\,
S(1) => \axaddr_incr[3]_i_13_n_0\,
S(0) => \axaddr_incr[3]_i_14_n_0\
);
\axaddr_incr_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => sel_first_reg_1(0),
D => \axaddr_incr[4]_i_1__0_n_0\,
Q => \^axaddr_incr_reg[11]_0\(1),
R => '0'
);
\axaddr_incr_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => sel_first_reg_1(0),
D => \axaddr_incr[5]_i_1__0_n_0\,
Q => \axaddr_incr_reg_n_0_[5]\,
R => '0'
);
\axaddr_incr_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => sel_first_reg_1(0),
D => \axaddr_incr[6]_i_1__0_n_0\,
Q => \^axaddr_incr_reg[11]_0\(2),
R => '0'
);
\axaddr_incr_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => sel_first_reg_1(0),
D => \axaddr_incr[7]_i_1__0_n_0\,
Q => \^axaddr_incr_reg[11]_0\(3),
R => '0'
);
\axaddr_incr_reg[7]_i_3__0\: unisim.vcomponents.CARRY4
port map (
CI => \axaddr_incr_reg[3]_i_3__0_n_0\,
CO(3) => \axaddr_incr_reg[7]_i_3__0_n_0\,
CO(2) => \axaddr_incr_reg[7]_i_3__0_n_1\,
CO(1) => \axaddr_incr_reg[7]_i_3__0_n_2\,
CO(0) => \axaddr_incr_reg[7]_i_3__0_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \axaddr_incr_reg[7]_i_3__0_n_4\,
O(2) => \axaddr_incr_reg[7]_i_3__0_n_5\,
O(1) => \axaddr_incr_reg[7]_i_3__0_n_6\,
O(0) => \axaddr_incr_reg[7]_i_3__0_n_7\,
S(3 downto 2) => \^axaddr_incr_reg[11]_0\(3 downto 2),
S(1) => \axaddr_incr_reg_n_0_[5]\,
S(0) => \^axaddr_incr_reg[11]_0\(1)
);
\axaddr_incr_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => sel_first_reg_1(0),
D => \axaddr_incr[8]_i_1__0_n_0\,
Q => \^axaddr_incr_reg[11]_0\(4),
R => '0'
);
\axaddr_incr_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => sel_first_reg_1(0),
D => \axaddr_incr[9]_i_1__0_n_0\,
Q => \^axaddr_incr_reg[11]_0\(5),
R => '0'
);
\axlen_cnt[0]_i_1__2\: unisim.vcomponents.LUT5
generic map(
INIT => X"20FF2020"
)
port map (
I0 => si_rs_arvalid,
I1 => \state_reg[0]_rep\,
I2 => Q(8),
I3 => \axlen_cnt_reg_n_0_[0]\,
I4 => \^axlen_cnt_reg[0]_0\,
O => \axlen_cnt[0]_i_1__2_n_0\
);
\axlen_cnt[1]_i_1__1\: unisim.vcomponents.LUT5
generic map(
INIT => X"F88F8888"
)
port map (
I0 => E(0),
I1 => Q(9),
I2 => \axlen_cnt_reg_n_0_[1]\,
I3 => \axlen_cnt_reg_n_0_[0]\,
I4 => \^axlen_cnt_reg[0]_0\,
O => \axlen_cnt[1]_i_1__1_n_0\
);
\axlen_cnt[2]_i_1__1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFA900A900A900"
)
port map (
I0 => \axlen_cnt_reg_n_0_[2]\,
I1 => \axlen_cnt_reg_n_0_[0]\,
I2 => \axlen_cnt_reg_n_0_[1]\,
I3 => \^axlen_cnt_reg[0]_0\,
I4 => E(0),
I5 => Q(10),
O => \axlen_cnt[2]_i_1__1_n_0\
);
\axlen_cnt[3]_i_2__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"EEEEEEEBAAAAAAAA"
)
port map (
I0 => \m_payload_i_reg[47]\,
I1 => \axlen_cnt_reg_n_0_[3]\,
I2 => \axlen_cnt_reg_n_0_[1]\,
I3 => \axlen_cnt_reg_n_0_[0]\,
I4 => \axlen_cnt_reg_n_0_[2]\,
I5 => \^axlen_cnt_reg[0]_0\,
O => \axlen_cnt[3]_i_2__0_n_0\
);
\axlen_cnt[3]_i_4\: unisim.vcomponents.LUT5
generic map(
INIT => X"55545555"
)
port map (
I0 => E(0),
I1 => \axlen_cnt_reg_n_0_[7]\,
I2 => \axlen_cnt_reg_n_0_[5]\,
I3 => \axlen_cnt_reg_n_0_[6]\,
I4 => \next_pending_r_i_4__0_n_0\,
O => \^axlen_cnt_reg[0]_0\
);
\axlen_cnt[4]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"AAAAAAA9"
)
port map (
I0 => \axlen_cnt_reg_n_0_[4]\,
I1 => \axlen_cnt_reg_n_0_[1]\,
I2 => \axlen_cnt_reg_n_0_[0]\,
I3 => \axlen_cnt_reg_n_0_[3]\,
I4 => \axlen_cnt_reg_n_0_[2]\,
O => \axlen_cnt[4]_i_1__0_n_0\
);
\axlen_cnt[5]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAAAAAAAAAAAAAA9"
)
port map (
I0 => \axlen_cnt_reg_n_0_[5]\,
I1 => \axlen_cnt_reg_n_0_[0]\,
I2 => \axlen_cnt_reg_n_0_[2]\,
I3 => \axlen_cnt_reg_n_0_[3]\,
I4 => \axlen_cnt_reg_n_0_[1]\,
I5 => \axlen_cnt_reg_n_0_[4]\,
O => \axlen_cnt[5]_i_1__0_n_0\
);
\axlen_cnt[6]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"9A"
)
port map (
I0 => \axlen_cnt_reg_n_0_[6]\,
I1 => \axlen_cnt_reg_n_0_[5]\,
I2 => \axlen_cnt[7]_i_3__0_n_0\,
O => \axlen_cnt[6]_i_1__0_n_0\
);
\axlen_cnt[7]_i_2__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"A9AA"
)
port map (
I0 => \axlen_cnt_reg_n_0_[7]\,
I1 => \axlen_cnt_reg_n_0_[6]\,
I2 => \axlen_cnt_reg_n_0_[5]\,
I3 => \axlen_cnt[7]_i_3__0_n_0\,
O => \axlen_cnt[7]_i_2__0_n_0\
);
\axlen_cnt[7]_i_3__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"00000001"
)
port map (
I0 => \axlen_cnt_reg_n_0_[4]\,
I1 => \axlen_cnt_reg_n_0_[1]\,
I2 => \axlen_cnt_reg_n_0_[3]\,
I3 => \axlen_cnt_reg_n_0_[2]\,
I4 => \axlen_cnt_reg_n_0_[0]\,
O => \axlen_cnt[7]_i_3__0_n_0\
);
\axlen_cnt_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axlen_cnt[0]_i_1__2_n_0\,
Q => \axlen_cnt_reg_n_0_[0]\,
R => '0'
);
\axlen_cnt_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axlen_cnt[1]_i_1__1_n_0\,
Q => \axlen_cnt_reg_n_0_[1]\,
R => '0'
);
\axlen_cnt_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axlen_cnt[2]_i_1__1_n_0\,
Q => \axlen_cnt_reg_n_0_[2]\,
R => '0'
);
\axlen_cnt_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axlen_cnt[3]_i_2__0_n_0\,
Q => \axlen_cnt_reg_n_0_[3]\,
R => '0'
);
\axlen_cnt_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axlen_cnt[4]_i_1__0_n_0\,
Q => \axlen_cnt_reg_n_0_[4]\,
R => \state_reg[1]\
);
\axlen_cnt_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axlen_cnt[5]_i_1__0_n_0\,
Q => \axlen_cnt_reg_n_0_[5]\,
R => \state_reg[1]\
);
\axlen_cnt_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axlen_cnt[6]_i_1__0_n_0\,
Q => \axlen_cnt_reg_n_0_[6]\,
R => \state_reg[1]\
);
\axlen_cnt_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axlen_cnt[7]_i_2__0_n_0\,
Q => \axlen_cnt_reg_n_0_[7]\,
R => \state_reg[1]\
);
\m_axi_araddr[11]_INST_0_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"B"
)
port map (
I0 => \^axaddr_incr_reg[0]_0\,
I1 => Q(7),
O => \m_axi_araddr[11]\
);
\m_axi_araddr[1]_INST_0_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"EF40"
)
port map (
I0 => \^axaddr_incr_reg[0]_0\,
I1 => \axaddr_incr_reg_n_0_[1]\,
I2 => Q(7),
I3 => Q(1),
O => \m_axi_araddr[1]\
);
\m_axi_araddr[2]_INST_0_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"EF40"
)
port map (
I0 => \^axaddr_incr_reg[0]_0\,
I1 => \axaddr_incr_reg_n_0_[2]\,
I2 => Q(7),
I3 => Q(2),
O => \m_axi_araddr[2]\
);
\m_axi_araddr[3]_INST_0_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"EF40"
)
port map (
I0 => \^axaddr_incr_reg[0]_0\,
I1 => \axaddr_incr_reg_n_0_[3]\,
I2 => Q(7),
I3 => Q(3),
O => \m_axi_araddr[3]\
);
\m_axi_araddr[5]_INST_0_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"EF40"
)
port map (
I0 => \^axaddr_incr_reg[0]_0\,
I1 => \axaddr_incr_reg_n_0_[5]\,
I2 => Q(7),
I3 => Q(4),
O => \m_axi_araddr[5]\
);
\next_pending_r_i_1__2\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFF505C"
)
port map (
I0 => \next_pending_r_i_2__0_n_0\,
I1 => next_pending_r_reg_n_0,
I2 => \state_reg[1]_rep\,
I3 => E(0),
I4 => \m_payload_i_reg[47]_0\,
O => \^incr_next_pending\
);
\next_pending_r_i_2__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"0002"
)
port map (
I0 => \next_pending_r_i_4__0_n_0\,
I1 => \axlen_cnt_reg_n_0_[6]\,
I2 => \axlen_cnt_reg_n_0_[5]\,
I3 => \axlen_cnt_reg_n_0_[7]\,
O => \next_pending_r_i_2__0_n_0\
);
\next_pending_r_i_4__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"0001"
)
port map (
I0 => \axlen_cnt_reg_n_0_[2]\,
I1 => \axlen_cnt_reg_n_0_[3]\,
I2 => \axlen_cnt_reg_n_0_[1]\,
I3 => \axlen_cnt_reg_n_0_[4]\,
O => \next_pending_r_i_4__0_n_0\
);
next_pending_r_reg: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \^incr_next_pending\,
Q => next_pending_r_reg_n_0,
R => '0'
);
sel_first_reg: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => sel_first_reg_0,
Q => \^axaddr_incr_reg[0]_0\,
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity zybo_zynq_design_auto_pc_0_axi_protocol_converter_v2_1_17_b2s_rd_cmd_fsm is
port (
\axlen_cnt_reg[7]\ : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 1 downto 0 );
r_push_r_reg : out STD_LOGIC;
\m_payload_i_reg[0]\ : out STD_LOGIC;
\m_payload_i_reg[0]_0\ : out STD_LOGIC;
D : out STD_LOGIC_VECTOR ( 0 to 0 );
\wrap_second_len_r_reg[0]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
E : out STD_LOGIC_VECTOR ( 0 to 0 );
sel_first_reg : out STD_LOGIC;
sel_first_reg_0 : out STD_LOGIC;
sel_first_i : out STD_LOGIC;
\wrap_cnt_r_reg[3]\ : out STD_LOGIC;
\axaddr_offset_r_reg[2]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\wrap_cnt_r_reg[3]_0\ : out STD_LOGIC;
\wrap_boundary_axaddr_r_reg[11]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\axaddr_incr_reg[0]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_arvalid : out STD_LOGIC;
m_valid_i0 : out STD_LOGIC;
s_ready_i0 : out STD_LOGIC;
\m_payload_i_reg[0]_1\ : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_arready : in STD_LOGIC;
si_rs_arvalid : in STD_LOGIC;
\axlen_cnt_reg[7]_0\ : in STD_LOGIC;
s_axburst_eq1_reg : in STD_LOGIC;
\cnt_read_reg[2]_rep__0\ : in STD_LOGIC;
\wrap_second_len_r_reg[0]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\axaddr_offset_r_reg[3]\ : in STD_LOGIC;
axaddr_offset : in STD_LOGIC_VECTOR ( 0 to 0 );
sel_first_reg_1 : in STD_LOGIC;
areset_d1 : in STD_LOGIC;
sel_first : in STD_LOGIC;
sel_first_reg_2 : in STD_LOGIC;
\axaddr_offset_r_reg[3]_0\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
\m_payload_i_reg[46]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\m_payload_i_reg[5]\ : in STD_LOGIC;
s_axi_arvalid : in STD_LOGIC;
s_ready_i_reg : in STD_LOGIC;
aclk : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of zybo_zynq_design_auto_pc_0_axi_protocol_converter_v2_1_17_b2s_rd_cmd_fsm : entity is "axi_protocol_converter_v2_1_17_b2s_rd_cmd_fsm";
end zybo_zynq_design_auto_pc_0_axi_protocol_converter_v2_1_17_b2s_rd_cmd_fsm;
architecture STRUCTURE of zybo_zynq_design_auto_pc_0_axi_protocol_converter_v2_1_17_b2s_rd_cmd_fsm is
signal \^q\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \^m_payload_i_reg[0]\ : STD_LOGIC;
signal \^m_payload_i_reg[0]_0\ : STD_LOGIC;
signal \next_state__0\ : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \axaddr_incr[11]_i_1__0\ : label is "soft_lutpair5";
attribute SOFT_HLUTNM of \axlen_cnt[3]_i_1__2\ : label is "soft_lutpair1";
attribute SOFT_HLUTNM of \axlen_cnt[7]_i_1\ : label is "soft_lutpair1";
attribute SOFT_HLUTNM of m_axi_arvalid_INST_0 : label is "soft_lutpair5";
attribute SOFT_HLUTNM of \m_payload_i[31]_i_1__0\ : label is "soft_lutpair4";
attribute SOFT_HLUTNM of \m_valid_i_i_1__1\ : label is "soft_lutpair0";
attribute SOFT_HLUTNM of r_push_r_i_1 : label is "soft_lutpair2";
attribute SOFT_HLUTNM of \s_ready_i_i_1__0\ : label is "soft_lutpair0";
attribute SOFT_HLUTNM of \state[1]_i_1\ : label is "soft_lutpair2";
attribute FSM_ENCODED_STATES : string;
attribute FSM_ENCODED_STATES of \state_reg[0]\ : label is "SM_IDLE:00,SM_CMD_EN:01,SM_CMD_ACCEPTED:10,SM_DONE:11";
attribute KEEP : string;
attribute KEEP of \state_reg[0]\ : label is "yes";
attribute ORIG_CELL_NAME : string;
attribute ORIG_CELL_NAME of \state_reg[0]\ : label is "state_reg[0]";
attribute FSM_ENCODED_STATES of \state_reg[0]_rep\ : label is "SM_IDLE:00,SM_CMD_EN:01,SM_CMD_ACCEPTED:10,SM_DONE:11";
attribute IS_FANOUT_CONSTRAINED : integer;
attribute IS_FANOUT_CONSTRAINED of \state_reg[0]_rep\ : label is 1;
attribute KEEP of \state_reg[0]_rep\ : label is "yes";
attribute ORIG_CELL_NAME of \state_reg[0]_rep\ : label is "state_reg[0]";
attribute FSM_ENCODED_STATES of \state_reg[1]\ : label is "SM_IDLE:00,SM_CMD_EN:01,SM_CMD_ACCEPTED:10,SM_DONE:11";
attribute KEEP of \state_reg[1]\ : label is "yes";
attribute ORIG_CELL_NAME of \state_reg[1]\ : label is "state_reg[1]";
attribute FSM_ENCODED_STATES of \state_reg[1]_rep\ : label is "SM_IDLE:00,SM_CMD_EN:01,SM_CMD_ACCEPTED:10,SM_DONE:11";
attribute IS_FANOUT_CONSTRAINED of \state_reg[1]_rep\ : label is 1;
attribute KEEP of \state_reg[1]_rep\ : label is "yes";
attribute ORIG_CELL_NAME of \state_reg[1]_rep\ : label is "state_reg[1]";
attribute SOFT_HLUTNM of \wrap_boundary_axaddr_r[11]_i_1__0\ : label is "soft_lutpair3";
attribute SOFT_HLUTNM of \wrap_cnt_r[3]_i_4__0\ : label is "soft_lutpair3";
attribute SOFT_HLUTNM of \wrap_cnt_r[3]_i_6__0\ : label is "soft_lutpair4";
begin
Q(1 downto 0) <= \^q\(1 downto 0);
\m_payload_i_reg[0]\ <= \^m_payload_i_reg[0]\;
\m_payload_i_reg[0]_0\ <= \^m_payload_i_reg[0]_0\;
\axaddr_incr[11]_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"AAEA"
)
port map (
I0 => sel_first,
I1 => m_axi_arready,
I2 => \^m_payload_i_reg[0]_0\,
I3 => \^m_payload_i_reg[0]\,
O => \axaddr_incr_reg[0]\(0)
);
\axaddr_offset_r[2]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAAAACAAAAAAA0AA"
)
port map (
I0 => \axaddr_offset_r_reg[3]_0\(0),
I1 => \m_payload_i_reg[46]\(0),
I2 => \^m_payload_i_reg[0]_0\,
I3 => si_rs_arvalid,
I4 => \^m_payload_i_reg[0]\,
I5 => \m_payload_i_reg[5]\,
O => \axaddr_offset_r_reg[2]\(0)
);
\axlen_cnt[3]_i_1__2\: unisim.vcomponents.LUT4
generic map(
INIT => X"00CA"
)
port map (
I0 => si_rs_arvalid,
I1 => m_axi_arready,
I2 => \^q\(0),
I3 => \^q\(1),
O => E(0)
);
\axlen_cnt[7]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"00005140"
)
port map (
I0 => \^q\(1),
I1 => \^q\(0),
I2 => m_axi_arready,
I3 => si_rs_arvalid,
I4 => \axlen_cnt_reg[7]_0\,
O => \axlen_cnt_reg[7]\
);
m_axi_arvalid_INST_0: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \^m_payload_i_reg[0]_0\,
I1 => \^m_payload_i_reg[0]\,
O => m_axi_arvalid
);
\m_payload_i[31]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"D5"
)
port map (
I0 => si_rs_arvalid,
I1 => \^m_payload_i_reg[0]\,
I2 => \^m_payload_i_reg[0]_0\,
O => \m_payload_i_reg[0]_1\(0)
);
\m_valid_i_i_1__1\: unisim.vcomponents.LUT5
generic map(
INIT => X"FF70FFFF"
)
port map (
I0 => \^m_payload_i_reg[0]_0\,
I1 => \^m_payload_i_reg[0]\,
I2 => si_rs_arvalid,
I3 => s_axi_arvalid,
I4 => s_ready_i_reg,
O => m_valid_i0
);
r_push_r_i_1: unisim.vcomponents.LUT3
generic map(
INIT => X"40"
)
port map (
I0 => \^m_payload_i_reg[0]\,
I1 => \^m_payload_i_reg[0]_0\,
I2 => m_axi_arready,
O => r_push_r_reg
);
\s_ready_i_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"8FFF8F8F"
)
port map (
I0 => \^m_payload_i_reg[0]_0\,
I1 => \^m_payload_i_reg[0]\,
I2 => si_rs_arvalid,
I3 => s_axi_arvalid,
I4 => s_ready_i_reg,
O => s_ready_i0
);
\sel_first_i_1__2\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFC4C4CFCC"
)
port map (
I0 => m_axi_arready,
I1 => sel_first_reg_1,
I2 => \^q\(1),
I3 => si_rs_arvalid,
I4 => \^q\(0),
I5 => areset_d1,
O => sel_first_reg
);
\sel_first_i_1__3\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFC4C4CFCC"
)
port map (
I0 => m_axi_arready,
I1 => sel_first,
I2 => \^m_payload_i_reg[0]\,
I3 => si_rs_arvalid,
I4 => \^m_payload_i_reg[0]_0\,
I5 => areset_d1,
O => sel_first_reg_0
);
\sel_first_i_1__4\: unisim.vcomponents.LUT6
generic map(
INIT => X"FCFFFFFFCCCECCCE"
)
port map (
I0 => si_rs_arvalid,
I1 => areset_d1,
I2 => \^m_payload_i_reg[0]\,
I3 => \^m_payload_i_reg[0]_0\,
I4 => m_axi_arready,
I5 => sel_first_reg_2,
O => sel_first_i
);
\state[0]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"003030303E3E3E3E"
)
port map (
I0 => si_rs_arvalid,
I1 => \^q\(1),
I2 => \^q\(0),
I3 => m_axi_arready,
I4 => s_axburst_eq1_reg,
I5 => \cnt_read_reg[2]_rep__0\,
O => \next_state__0\(0)
);
\state[1]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"00AAB000"
)
port map (
I0 => \cnt_read_reg[2]_rep__0\,
I1 => s_axburst_eq1_reg,
I2 => m_axi_arready,
I3 => \^m_payload_i_reg[0]_0\,
I4 => \^m_payload_i_reg[0]\,
O => \next_state__0\(1)
);
\state_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => \next_state__0\(0),
Q => \^q\(0),
R => areset_d1
);
\state_reg[0]_rep\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => \next_state__0\(0),
Q => \^m_payload_i_reg[0]_0\,
R => areset_d1
);
\state_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => \next_state__0\(1),
Q => \^q\(1),
R => areset_d1
);
\state_reg[1]_rep\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => \next_state__0\(1),
Q => \^m_payload_i_reg[0]\,
R => areset_d1
);
\wrap_boundary_axaddr_r[11]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"04"
)
port map (
I0 => \^m_payload_i_reg[0]\,
I1 => si_rs_arvalid,
I2 => \^m_payload_i_reg[0]_0\,
O => \wrap_boundary_axaddr_r_reg[11]\(0)
);
\wrap_cnt_r[0]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AA8A5575AA8A5545"
)
port map (
I0 => \wrap_second_len_r_reg[0]_0\(0),
I1 => \^q\(0),
I2 => si_rs_arvalid,
I3 => \^q\(1),
I4 => \axaddr_offset_r_reg[3]\,
I5 => axaddr_offset(0),
O => D(0)
);
\wrap_cnt_r[3]_i_4__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"AA8A"
)
port map (
I0 => \axaddr_offset_r_reg[3]_0\(1),
I1 => \^m_payload_i_reg[0]_0\,
I2 => si_rs_arvalid,
I3 => \^m_payload_i_reg[0]\,
O => \wrap_cnt_r_reg[3]\
);
\wrap_cnt_r[3]_i_6__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"AA8A"
)
port map (
I0 => \axaddr_offset_r_reg[3]_0\(0),
I1 => \^m_payload_i_reg[0]_0\,
I2 => si_rs_arvalid,
I3 => \^m_payload_i_reg[0]\,
O => \wrap_cnt_r_reg[3]_0\
);
\wrap_second_len_r[0]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AA8AAA8AAA8AAABA"
)
port map (
I0 => \wrap_second_len_r_reg[0]_0\(0),
I1 => \^q\(0),
I2 => si_rs_arvalid,
I3 => \^q\(1),
I4 => \axaddr_offset_r_reg[3]\,
I5 => axaddr_offset(0),
O => \wrap_second_len_r_reg[0]\(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity zybo_zynq_design_auto_pc_0_axi_protocol_converter_v2_1_17_b2s_simple_fifo is
port (
\cnt_read_reg[0]_rep__0_0\ : out STD_LOGIC;
\cnt_read_reg[1]_rep__0_0\ : out STD_LOGIC;
SR : out STD_LOGIC_VECTOR ( 0 to 0 );
D : out STD_LOGIC_VECTOR ( 0 to 0 );
bresp_push : out STD_LOGIC;
bvalid_i_reg : out STD_LOGIC;
\out\ : out STD_LOGIC_VECTOR ( 11 downto 0 );
b_push : in STD_LOGIC;
shandshake_r : in STD_LOGIC;
areset_d1 : in STD_LOGIC;
Q : in STD_LOGIC_VECTOR ( 1 downto 0 );
\bresp_cnt_reg[7]\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
mhandshake_r : in STD_LOGIC;
si_rs_bready : in STD_LOGIC;
bvalid_i_reg_0 : in STD_LOGIC;
\in\ : in STD_LOGIC_VECTOR ( 15 downto 0 );
aclk : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of zybo_zynq_design_auto_pc_0_axi_protocol_converter_v2_1_17_b2s_simple_fifo : entity is "axi_protocol_converter_v2_1_17_b2s_simple_fifo";
end zybo_zynq_design_auto_pc_0_axi_protocol_converter_v2_1_17_b2s_simple_fifo;
architecture STRUCTURE of zybo_zynq_design_auto_pc_0_axi_protocol_converter_v2_1_17_b2s_simple_fifo is
signal \bresp_cnt[7]_i_3_n_0\ : STD_LOGIC;
signal \bresp_cnt[7]_i_4_n_0\ : STD_LOGIC;
signal \bresp_cnt[7]_i_5_n_0\ : STD_LOGIC;
signal \^bresp_push\ : STD_LOGIC;
signal bvalid_i_i_2_n_0 : STD_LOGIC;
signal cnt_read : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \cnt_read[0]_i_1__2_n_0\ : STD_LOGIC;
signal \cnt_read[1]_i_1_n_0\ : STD_LOGIC;
signal \^cnt_read_reg[0]_rep__0_0\ : STD_LOGIC;
signal \cnt_read_reg[0]_rep_n_0\ : STD_LOGIC;
signal \^cnt_read_reg[1]_rep__0_0\ : STD_LOGIC;
signal \cnt_read_reg[1]_rep_n_0\ : STD_LOGIC;
signal \memory_reg[3][0]_srl4_i_2__0_n_0\ : STD_LOGIC;
signal \memory_reg[3][0]_srl4_i_3_n_0\ : STD_LOGIC;
signal \memory_reg[3][0]_srl4_n_0\ : STD_LOGIC;
signal \memory_reg[3][1]_srl4_n_0\ : STD_LOGIC;
signal \memory_reg[3][2]_srl4_n_0\ : STD_LOGIC;
signal \memory_reg[3][3]_srl4_n_0\ : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \cnt_read[0]_i_1__2\ : label is "soft_lutpair121";
attribute SOFT_HLUTNM of \cnt_read[1]_i_1\ : label is "soft_lutpair121";
attribute KEEP : string;
attribute KEEP of \cnt_read_reg[0]\ : label is "yes";
attribute ORIG_CELL_NAME : string;
attribute ORIG_CELL_NAME of \cnt_read_reg[0]\ : label is "cnt_read_reg[0]";
attribute IS_FANOUT_CONSTRAINED : integer;
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[0]_rep\ : label is 1;
attribute KEEP of \cnt_read_reg[0]_rep\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[0]_rep\ : label is "cnt_read_reg[0]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[0]_rep__0\ : label is 1;
attribute KEEP of \cnt_read_reg[0]_rep__0\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[0]_rep__0\ : label is "cnt_read_reg[0]";
attribute KEEP of \cnt_read_reg[1]\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[1]\ : label is "cnt_read_reg[1]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[1]_rep\ : label is 1;
attribute KEEP of \cnt_read_reg[1]_rep\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[1]_rep\ : label is "cnt_read_reg[1]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[1]_rep__0\ : label is 1;
attribute KEEP of \cnt_read_reg[1]_rep__0\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[1]_rep__0\ : label is "cnt_read_reg[1]";
attribute srl_bus_name : string;
attribute srl_bus_name of \memory_reg[3][0]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] ";
attribute srl_name : string;
attribute srl_name of \memory_reg[3][0]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][0]_srl4 ";
attribute srl_bus_name of \memory_reg[3][10]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] ";
attribute srl_name of \memory_reg[3][10]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][10]_srl4 ";
attribute srl_bus_name of \memory_reg[3][11]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] ";
attribute srl_name of \memory_reg[3][11]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][11]_srl4 ";
attribute srl_bus_name of \memory_reg[3][12]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] ";
attribute srl_name of \memory_reg[3][12]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][12]_srl4 ";
attribute srl_bus_name of \memory_reg[3][13]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] ";
attribute srl_name of \memory_reg[3][13]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][13]_srl4 ";
attribute srl_bus_name of \memory_reg[3][14]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] ";
attribute srl_name of \memory_reg[3][14]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][14]_srl4 ";
attribute srl_bus_name of \memory_reg[3][15]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] ";
attribute srl_name of \memory_reg[3][15]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][15]_srl4 ";
attribute srl_bus_name of \memory_reg[3][16]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] ";
attribute srl_name of \memory_reg[3][16]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][16]_srl4 ";
attribute srl_bus_name of \memory_reg[3][17]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] ";
attribute srl_name of \memory_reg[3][17]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][17]_srl4 ";
attribute srl_bus_name of \memory_reg[3][18]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] ";
attribute srl_name of \memory_reg[3][18]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][18]_srl4 ";
attribute srl_bus_name of \memory_reg[3][19]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] ";
attribute srl_name of \memory_reg[3][19]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][19]_srl4 ";
attribute srl_bus_name of \memory_reg[3][1]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] ";
attribute srl_name of \memory_reg[3][1]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][1]_srl4 ";
attribute srl_bus_name of \memory_reg[3][2]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] ";
attribute srl_name of \memory_reg[3][2]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][2]_srl4 ";
attribute srl_bus_name of \memory_reg[3][3]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] ";
attribute srl_name of \memory_reg[3][3]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][3]_srl4 ";
attribute srl_bus_name of \memory_reg[3][8]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] ";
attribute srl_name of \memory_reg[3][8]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][8]_srl4 ";
attribute srl_bus_name of \memory_reg[3][9]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] ";
attribute srl_name of \memory_reg[3][9]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][9]_srl4 ";
begin
bresp_push <= \^bresp_push\;
\cnt_read_reg[0]_rep__0_0\ <= \^cnt_read_reg[0]_rep__0_0\;
\cnt_read_reg[1]_rep__0_0\ <= \^cnt_read_reg[1]_rep__0_0\;
\bresp_cnt[7]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"ABAA"
)
port map (
I0 => areset_d1,
I1 => \bresp_cnt[7]_i_3_n_0\,
I2 => \bresp_cnt[7]_i_4_n_0\,
I3 => \bresp_cnt[7]_i_5_n_0\,
O => SR(0)
);
\bresp_cnt[7]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"EEFEFFFFFFFFEEFE"
)
port map (
I0 => \bresp_cnt_reg[7]\(7),
I1 => \bresp_cnt_reg[7]\(6),
I2 => \bresp_cnt_reg[7]\(0),
I3 => \memory_reg[3][0]_srl4_n_0\,
I4 => \bresp_cnt_reg[7]\(3),
I5 => \memory_reg[3][3]_srl4_n_0\,
O => \bresp_cnt[7]_i_3_n_0\
);
\bresp_cnt[7]_i_4\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFF6FFFF"
)
port map (
I0 => \bresp_cnt_reg[7]\(1),
I1 => \memory_reg[3][1]_srl4_n_0\,
I2 => \bresp_cnt_reg[7]\(4),
I3 => \bresp_cnt_reg[7]\(5),
I4 => mhandshake_r,
O => \bresp_cnt[7]_i_4_n_0\
);
\bresp_cnt[7]_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000D00DD00DD00D"
)
port map (
I0 => \memory_reg[3][0]_srl4_n_0\,
I1 => \bresp_cnt_reg[7]\(0),
I2 => \bresp_cnt_reg[7]\(2),
I3 => \memory_reg[3][2]_srl4_n_0\,
I4 => \^cnt_read_reg[1]_rep__0_0\,
I5 => \^cnt_read_reg[0]_rep__0_0\,
O => \bresp_cnt[7]_i_5_n_0\
);
bvalid_i_i_1: unisim.vcomponents.LUT4
generic map(
INIT => X"0444"
)
port map (
I0 => areset_d1,
I1 => bvalid_i_i_2_n_0,
I2 => si_rs_bready,
I3 => bvalid_i_reg_0,
O => bvalid_i_reg
);
bvalid_i_i_2: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFF00070707"
)
port map (
I0 => \^cnt_read_reg[1]_rep__0_0\,
I1 => \^cnt_read_reg[0]_rep__0_0\,
I2 => shandshake_r,
I3 => Q(1),
I4 => Q(0),
I5 => bvalid_i_reg_0,
O => bvalid_i_i_2_n_0
);
\cnt_read[0]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => \^bresp_push\,
I1 => shandshake_r,
I2 => Q(0),
O => D(0)
);
\cnt_read[0]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => \^cnt_read_reg[0]_rep__0_0\,
I1 => b_push,
I2 => shandshake_r,
O => \cnt_read[0]_i_1__2_n_0\
);
\cnt_read[1]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"E718"
)
port map (
I0 => \^cnt_read_reg[0]_rep__0_0\,
I1 => b_push,
I2 => shandshake_r,
I3 => \^cnt_read_reg[1]_rep__0_0\,
O => \cnt_read[1]_i_1_n_0\
);
\cnt_read_reg[0]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[0]_i_1__2_n_0\,
Q => cnt_read(0),
S => areset_d1
);
\cnt_read_reg[0]_rep\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[0]_i_1__2_n_0\,
Q => \cnt_read_reg[0]_rep_n_0\,
S => areset_d1
);
\cnt_read_reg[0]_rep__0\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[0]_i_1__2_n_0\,
Q => \^cnt_read_reg[0]_rep__0_0\,
S => areset_d1
);
\cnt_read_reg[1]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[1]_i_1_n_0\,
Q => cnt_read(1),
S => areset_d1
);
\cnt_read_reg[1]_rep\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[1]_i_1_n_0\,
Q => \cnt_read_reg[1]_rep_n_0\,
S => areset_d1
);
\cnt_read_reg[1]_rep__0\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[1]_i_1_n_0\,
Q => \^cnt_read_reg[1]_rep__0_0\,
S => areset_d1
);
\memory_reg[3][0]_srl4\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => \cnt_read_reg[0]_rep_n_0\,
A1 => \cnt_read_reg[1]_rep_n_0\,
A2 => '0',
A3 => '0',
CE => b_push,
CLK => aclk,
D => \in\(0),
Q => \memory_reg[3][0]_srl4_n_0\
);
\memory_reg[3][0]_srl4_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000041004141"
)
port map (
I0 => \memory_reg[3][0]_srl4_i_2__0_n_0\,
I1 => \memory_reg[3][2]_srl4_n_0\,
I2 => \bresp_cnt_reg[7]\(2),
I3 => \bresp_cnt_reg[7]\(0),
I4 => \memory_reg[3][0]_srl4_n_0\,
I5 => \memory_reg[3][0]_srl4_i_3_n_0\,
O => \^bresp_push\
);
\memory_reg[3][0]_srl4_i_2__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \^cnt_read_reg[1]_rep__0_0\,
I1 => \^cnt_read_reg[0]_rep__0_0\,
O => \memory_reg[3][0]_srl4_i_2__0_n_0\
);
\memory_reg[3][0]_srl4_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFBFFFFFFFFFFFB"
)
port map (
I0 => \bresp_cnt[7]_i_3_n_0\,
I1 => mhandshake_r,
I2 => \bresp_cnt_reg[7]\(5),
I3 => \bresp_cnt_reg[7]\(4),
I4 => \memory_reg[3][1]_srl4_n_0\,
I5 => \bresp_cnt_reg[7]\(1),
O => \memory_reg[3][0]_srl4_i_3_n_0\
);
\memory_reg[3][10]_srl4\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => \cnt_read_reg[0]_rep_n_0\,
A1 => \cnt_read_reg[1]_rep_n_0\,
A2 => '0',
A3 => '0',
CE => b_push,
CLK => aclk,
D => \in\(6),
Q => \out\(2)
);
\memory_reg[3][11]_srl4\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => \cnt_read_reg[0]_rep_n_0\,
A1 => \cnt_read_reg[1]_rep_n_0\,
A2 => '0',
A3 => '0',
CE => b_push,
CLK => aclk,
D => \in\(7),
Q => \out\(3)
);
\memory_reg[3][12]_srl4\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => cnt_read(0),
A1 => cnt_read(1),
A2 => '0',
A3 => '0',
CE => b_push,
CLK => aclk,
D => \in\(8),
Q => \out\(4)
);
\memory_reg[3][13]_srl4\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => cnt_read(0),
A1 => cnt_read(1),
A2 => '0',
A3 => '0',
CE => b_push,
CLK => aclk,
D => \in\(9),
Q => \out\(5)
);
\memory_reg[3][14]_srl4\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => cnt_read(0),
A1 => cnt_read(1),
A2 => '0',
A3 => '0',
CE => b_push,
CLK => aclk,
D => \in\(10),
Q => \out\(6)
);
\memory_reg[3][15]_srl4\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => cnt_read(0),
A1 => cnt_read(1),
A2 => '0',
A3 => '0',
CE => b_push,
CLK => aclk,
D => \in\(11),
Q => \out\(7)
);
\memory_reg[3][16]_srl4\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => cnt_read(0),
A1 => cnt_read(1),
A2 => '0',
A3 => '0',
CE => b_push,
CLK => aclk,
D => \in\(12),
Q => \out\(8)
);
\memory_reg[3][17]_srl4\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => cnt_read(0),
A1 => cnt_read(1),
A2 => '0',
A3 => '0',
CE => b_push,
CLK => aclk,
D => \in\(13),
Q => \out\(9)
);
\memory_reg[3][18]_srl4\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => cnt_read(0),
A1 => cnt_read(1),
A2 => '0',
A3 => '0',
CE => b_push,
CLK => aclk,
D => \in\(14),
Q => \out\(10)
);
\memory_reg[3][19]_srl4\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => cnt_read(0),
A1 => cnt_read(1),
A2 => '0',
A3 => '0',
CE => b_push,
CLK => aclk,
D => \in\(15),
Q => \out\(11)
);
\memory_reg[3][1]_srl4\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => \cnt_read_reg[0]_rep_n_0\,
A1 => \cnt_read_reg[1]_rep_n_0\,
A2 => '0',
A3 => '0',
CE => b_push,
CLK => aclk,
D => \in\(1),
Q => \memory_reg[3][1]_srl4_n_0\
);
\memory_reg[3][2]_srl4\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => \cnt_read_reg[0]_rep_n_0\,
A1 => \cnt_read_reg[1]_rep_n_0\,
A2 => '0',
A3 => '0',
CE => b_push,
CLK => aclk,
D => \in\(2),
Q => \memory_reg[3][2]_srl4_n_0\
);
\memory_reg[3][3]_srl4\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => \cnt_read_reg[0]_rep_n_0\,
A1 => \cnt_read_reg[1]_rep_n_0\,
A2 => '0',
A3 => '0',
CE => b_push,
CLK => aclk,
D => \in\(3),
Q => \memory_reg[3][3]_srl4_n_0\
);
\memory_reg[3][8]_srl4\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => \cnt_read_reg[0]_rep_n_0\,
A1 => \cnt_read_reg[1]_rep_n_0\,
A2 => '0',
A3 => '0',
CE => b_push,
CLK => aclk,
D => \in\(4),
Q => \out\(0)
);
\memory_reg[3][9]_srl4\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => \cnt_read_reg[0]_rep_n_0\,
A1 => \cnt_read_reg[1]_rep_n_0\,
A2 => '0',
A3 => '0',
CE => b_push,
CLK => aclk,
D => \in\(5),
Q => \out\(1)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \zybo_zynq_design_auto_pc_0_axi_protocol_converter_v2_1_17_b2s_simple_fifo__parameterized0\ is
port (
Q : out STD_LOGIC_VECTOR ( 1 downto 0 );
mhandshake : out STD_LOGIC;
m_axi_bready : out STD_LOGIC;
\skid_buffer_reg[1]\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
shandshake_r : in STD_LOGIC;
sel : in STD_LOGIC;
m_axi_bvalid : in STD_LOGIC;
mhandshake_r : in STD_LOGIC;
\in\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
aclk : in STD_LOGIC;
areset_d1 : in STD_LOGIC;
D : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \zybo_zynq_design_auto_pc_0_axi_protocol_converter_v2_1_17_b2s_simple_fifo__parameterized0\ : entity is "axi_protocol_converter_v2_1_17_b2s_simple_fifo";
end \zybo_zynq_design_auto_pc_0_axi_protocol_converter_v2_1_17_b2s_simple_fifo__parameterized0\;
architecture STRUCTURE of \zybo_zynq_design_auto_pc_0_axi_protocol_converter_v2_1_17_b2s_simple_fifo__parameterized0\ is
signal \^q\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \cnt_read[1]_i_1__0_n_0\ : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \cnt_read[1]_i_1__0\ : label is "soft_lutpair122";
attribute KEEP : string;
attribute KEEP of \cnt_read_reg[0]\ : label is "yes";
attribute KEEP of \cnt_read_reg[1]\ : label is "yes";
attribute SOFT_HLUTNM of m_axi_bready_INST_0 : label is "soft_lutpair122";
attribute srl_bus_name : string;
attribute srl_bus_name of \memory_reg[3][0]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bresp_fifo_0/memory_reg[3] ";
attribute srl_name : string;
attribute srl_name of \memory_reg[3][0]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bresp_fifo_0/memory_reg[3][0]_srl4 ";
attribute srl_bus_name of \memory_reg[3][1]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bresp_fifo_0/memory_reg[3] ";
attribute srl_name of \memory_reg[3][1]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bresp_fifo_0/memory_reg[3][1]_srl4 ";
begin
Q(1 downto 0) <= \^q\(1 downto 0);
\cnt_read[1]_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"A69A"
)
port map (
I0 => \^q\(1),
I1 => \^q\(0),
I2 => shandshake_r,
I3 => sel,
O => \cnt_read[1]_i_1__0_n_0\
);
\cnt_read_reg[0]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => D(0),
Q => \^q\(0),
S => areset_d1
);
\cnt_read_reg[1]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[1]_i_1__0_n_0\,
Q => \^q\(1),
S => areset_d1
);
m_axi_bready_INST_0: unisim.vcomponents.LUT3
generic map(
INIT => X"08"
)
port map (
I0 => \^q\(1),
I1 => \^q\(0),
I2 => mhandshake_r,
O => m_axi_bready
);
\memory_reg[3][0]_srl4\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => \^q\(0),
A1 => \^q\(1),
A2 => '0',
A3 => '0',
CE => sel,
CLK => aclk,
D => \in\(0),
Q => \skid_buffer_reg[1]\(0)
);
\memory_reg[3][1]_srl4\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => \^q\(0),
A1 => \^q\(1),
A2 => '0',
A3 => '0',
CE => sel,
CLK => aclk,
D => \in\(1),
Q => \skid_buffer_reg[1]\(1)
);
mhandshake_r_i_1: unisim.vcomponents.LUT4
generic map(
INIT => X"2000"
)
port map (
I0 => m_axi_bvalid,
I1 => mhandshake_r,
I2 => \^q\(0),
I3 => \^q\(1),
O => mhandshake
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \zybo_zynq_design_auto_pc_0_axi_protocol_converter_v2_1_17_b2s_simple_fifo__parameterized1\ is
port (
\cnt_read_reg[4]_rep__2_0\ : out STD_LOGIC;
\cnt_read_reg[4]_rep__2_1\ : out STD_LOGIC;
\cnt_read_reg[4]_rep__2_2\ : out STD_LOGIC;
m_axi_rready : out STD_LOGIC;
\state_reg[1]_rep\ : out STD_LOGIC;
\out\ : out STD_LOGIC_VECTOR ( 33 downto 0 );
s_ready_i_reg : in STD_LOGIC;
\cnt_read_reg[4]_rep__0_0\ : in STD_LOGIC;
si_rs_rready : in STD_LOGIC;
m_axi_rvalid : in STD_LOGIC;
\in\ : in STD_LOGIC_VECTOR ( 33 downto 0 );
aclk : in STD_LOGIC;
areset_d1 : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \zybo_zynq_design_auto_pc_0_axi_protocol_converter_v2_1_17_b2s_simple_fifo__parameterized1\ : entity is "axi_protocol_converter_v2_1_17_b2s_simple_fifo";
end \zybo_zynq_design_auto_pc_0_axi_protocol_converter_v2_1_17_b2s_simple_fifo__parameterized1\;
architecture STRUCTURE of \zybo_zynq_design_auto_pc_0_axi_protocol_converter_v2_1_17_b2s_simple_fifo__parameterized1\ is
signal cnt_read : STD_LOGIC_VECTOR ( 4 downto 0 );
signal \cnt_read[0]_i_1__1_n_0\ : STD_LOGIC;
signal \cnt_read[1]_i_1__2_n_0\ : STD_LOGIC;
signal \cnt_read[2]_i_1_n_0\ : STD_LOGIC;
signal \cnt_read[3]_i_1__0_n_0\ : STD_LOGIC;
signal \cnt_read[4]_i_1_n_0\ : STD_LOGIC;
signal \cnt_read[4]_i_3__0_n_0\ : STD_LOGIC;
signal \cnt_read[4]_i_5_n_0\ : STD_LOGIC;
signal \cnt_read_reg[0]_rep__0_n_0\ : STD_LOGIC;
signal \cnt_read_reg[0]_rep__1_n_0\ : STD_LOGIC;
signal \cnt_read_reg[0]_rep__2_n_0\ : STD_LOGIC;
signal \cnt_read_reg[0]_rep__3_n_0\ : STD_LOGIC;
signal \cnt_read_reg[0]_rep_n_0\ : STD_LOGIC;
signal \cnt_read_reg[1]_rep__0_n_0\ : STD_LOGIC;
signal \cnt_read_reg[1]_rep__1_n_0\ : STD_LOGIC;
signal \cnt_read_reg[1]_rep__2_n_0\ : STD_LOGIC;
signal \cnt_read_reg[1]_rep_n_0\ : STD_LOGIC;
signal \cnt_read_reg[2]_rep__0_n_0\ : STD_LOGIC;
signal \cnt_read_reg[2]_rep__1_n_0\ : STD_LOGIC;
signal \cnt_read_reg[2]_rep__2_n_0\ : STD_LOGIC;
signal \cnt_read_reg[2]_rep_n_0\ : STD_LOGIC;
signal \cnt_read_reg[3]_rep__0_n_0\ : STD_LOGIC;
signal \cnt_read_reg[3]_rep__1_n_0\ : STD_LOGIC;
signal \cnt_read_reg[3]_rep_n_0\ : STD_LOGIC;
signal \cnt_read_reg[4]_rep__0_n_0\ : STD_LOGIC;
signal \cnt_read_reg[4]_rep__1_n_0\ : STD_LOGIC;
signal \^cnt_read_reg[4]_rep__2_0\ : STD_LOGIC;
signal \^cnt_read_reg[4]_rep__2_1\ : STD_LOGIC;
signal \^cnt_read_reg[4]_rep__2_2\ : STD_LOGIC;
signal \cnt_read_reg[4]_rep_n_0\ : STD_LOGIC;
signal wr_en0 : STD_LOGIC;
signal \NLW_memory_reg[31][0]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][10]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][11]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][12]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][13]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][14]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][15]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][16]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][17]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][18]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][19]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][1]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][20]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][21]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][22]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][23]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][24]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][25]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][26]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][27]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][28]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][29]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][2]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][30]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][31]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][32]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][33]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][3]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][4]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][5]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][6]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][7]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][8]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][9]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \cnt_read[1]_i_1__2\ : label is "soft_lutpair18";
attribute SOFT_HLUTNM of \cnt_read[2]_i_1\ : label is "soft_lutpair18";
attribute KEEP : string;
attribute KEEP of \cnt_read_reg[0]\ : label is "yes";
attribute ORIG_CELL_NAME : string;
attribute ORIG_CELL_NAME of \cnt_read_reg[0]\ : label is "cnt_read_reg[0]";
attribute IS_FANOUT_CONSTRAINED : integer;
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[0]_rep\ : label is 1;
attribute KEEP of \cnt_read_reg[0]_rep\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[0]_rep\ : label is "cnt_read_reg[0]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[0]_rep__0\ : label is 1;
attribute KEEP of \cnt_read_reg[0]_rep__0\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[0]_rep__0\ : label is "cnt_read_reg[0]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[0]_rep__1\ : label is 1;
attribute KEEP of \cnt_read_reg[0]_rep__1\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[0]_rep__1\ : label is "cnt_read_reg[0]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[0]_rep__2\ : label is 1;
attribute KEEP of \cnt_read_reg[0]_rep__2\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[0]_rep__2\ : label is "cnt_read_reg[0]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[0]_rep__3\ : label is 1;
attribute KEEP of \cnt_read_reg[0]_rep__3\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[0]_rep__3\ : label is "cnt_read_reg[0]";
attribute KEEP of \cnt_read_reg[1]\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[1]\ : label is "cnt_read_reg[1]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[1]_rep\ : label is 1;
attribute KEEP of \cnt_read_reg[1]_rep\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[1]_rep\ : label is "cnt_read_reg[1]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[1]_rep__0\ : label is 1;
attribute KEEP of \cnt_read_reg[1]_rep__0\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[1]_rep__0\ : label is "cnt_read_reg[1]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[1]_rep__1\ : label is 1;
attribute KEEP of \cnt_read_reg[1]_rep__1\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[1]_rep__1\ : label is "cnt_read_reg[1]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[1]_rep__2\ : label is 1;
attribute KEEP of \cnt_read_reg[1]_rep__2\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[1]_rep__2\ : label is "cnt_read_reg[1]";
attribute KEEP of \cnt_read_reg[2]\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[2]\ : label is "cnt_read_reg[2]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[2]_rep\ : label is 1;
attribute KEEP of \cnt_read_reg[2]_rep\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[2]_rep\ : label is "cnt_read_reg[2]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[2]_rep__0\ : label is 1;
attribute KEEP of \cnt_read_reg[2]_rep__0\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[2]_rep__0\ : label is "cnt_read_reg[2]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[2]_rep__1\ : label is 1;
attribute KEEP of \cnt_read_reg[2]_rep__1\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[2]_rep__1\ : label is "cnt_read_reg[2]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[2]_rep__2\ : label is 1;
attribute KEEP of \cnt_read_reg[2]_rep__2\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[2]_rep__2\ : label is "cnt_read_reg[2]";
attribute KEEP of \cnt_read_reg[3]\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[3]\ : label is "cnt_read_reg[3]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[3]_rep\ : label is 1;
attribute KEEP of \cnt_read_reg[3]_rep\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[3]_rep\ : label is "cnt_read_reg[3]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[3]_rep__0\ : label is 1;
attribute KEEP of \cnt_read_reg[3]_rep__0\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[3]_rep__0\ : label is "cnt_read_reg[3]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[3]_rep__1\ : label is 1;
attribute KEEP of \cnt_read_reg[3]_rep__1\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[3]_rep__1\ : label is "cnt_read_reg[3]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[3]_rep__2\ : label is 1;
attribute KEEP of \cnt_read_reg[3]_rep__2\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[3]_rep__2\ : label is "cnt_read_reg[3]";
attribute KEEP of \cnt_read_reg[4]\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[4]\ : label is "cnt_read_reg[4]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[4]_rep\ : label is 1;
attribute KEEP of \cnt_read_reg[4]_rep\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[4]_rep\ : label is "cnt_read_reg[4]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[4]_rep__0\ : label is 1;
attribute KEEP of \cnt_read_reg[4]_rep__0\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[4]_rep__0\ : label is "cnt_read_reg[4]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[4]_rep__1\ : label is 1;
attribute KEEP of \cnt_read_reg[4]_rep__1\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[4]_rep__1\ : label is "cnt_read_reg[4]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[4]_rep__2\ : label is 1;
attribute KEEP of \cnt_read_reg[4]_rep__2\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[4]_rep__2\ : label is "cnt_read_reg[4]";
attribute SOFT_HLUTNM of m_axi_rready_INST_0 : label is "soft_lutpair19";
attribute srl_bus_name : string;
attribute srl_bus_name of \memory_reg[31][0]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name : string;
attribute srl_name of \memory_reg[31][0]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][0]_srl32 ";
attribute srl_bus_name of \memory_reg[31][10]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][10]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][10]_srl32 ";
attribute srl_bus_name of \memory_reg[31][11]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][11]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][11]_srl32 ";
attribute srl_bus_name of \memory_reg[31][12]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][12]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][12]_srl32 ";
attribute srl_bus_name of \memory_reg[31][13]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][13]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][13]_srl32 ";
attribute srl_bus_name of \memory_reg[31][14]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][14]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][14]_srl32 ";
attribute srl_bus_name of \memory_reg[31][15]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][15]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][15]_srl32 ";
attribute srl_bus_name of \memory_reg[31][16]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][16]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][16]_srl32 ";
attribute srl_bus_name of \memory_reg[31][17]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][17]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][17]_srl32 ";
attribute srl_bus_name of \memory_reg[31][18]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][18]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][18]_srl32 ";
attribute srl_bus_name of \memory_reg[31][19]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][19]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][19]_srl32 ";
attribute srl_bus_name of \memory_reg[31][1]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][1]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][1]_srl32 ";
attribute srl_bus_name of \memory_reg[31][20]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][20]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][20]_srl32 ";
attribute srl_bus_name of \memory_reg[31][21]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][21]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][21]_srl32 ";
attribute srl_bus_name of \memory_reg[31][22]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][22]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][22]_srl32 ";
attribute srl_bus_name of \memory_reg[31][23]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][23]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][23]_srl32 ";
attribute srl_bus_name of \memory_reg[31][24]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][24]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][24]_srl32 ";
attribute srl_bus_name of \memory_reg[31][25]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][25]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][25]_srl32 ";
attribute srl_bus_name of \memory_reg[31][26]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][26]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][26]_srl32 ";
attribute srl_bus_name of \memory_reg[31][27]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][27]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][27]_srl32 ";
attribute srl_bus_name of \memory_reg[31][28]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][28]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][28]_srl32 ";
attribute srl_bus_name of \memory_reg[31][29]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][29]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][29]_srl32 ";
attribute srl_bus_name of \memory_reg[31][2]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][2]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][2]_srl32 ";
attribute srl_bus_name of \memory_reg[31][30]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][30]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][30]_srl32 ";
attribute srl_bus_name of \memory_reg[31][31]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][31]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][31]_srl32 ";
attribute srl_bus_name of \memory_reg[31][32]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][32]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][32]_srl32 ";
attribute srl_bus_name of \memory_reg[31][33]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][33]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][33]_srl32 ";
attribute srl_bus_name of \memory_reg[31][3]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][3]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][3]_srl32 ";
attribute srl_bus_name of \memory_reg[31][4]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][4]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][4]_srl32 ";
attribute srl_bus_name of \memory_reg[31][5]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][5]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][5]_srl32 ";
attribute srl_bus_name of \memory_reg[31][6]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][6]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][6]_srl32 ";
attribute srl_bus_name of \memory_reg[31][7]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][7]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][7]_srl32 ";
attribute srl_bus_name of \memory_reg[31][8]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][8]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][8]_srl32 ";
attribute srl_bus_name of \memory_reg[31][9]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][9]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][9]_srl32 ";
attribute SOFT_HLUTNM of \state[1]_i_4\ : label is "soft_lutpair19";
begin
\cnt_read_reg[4]_rep__2_0\ <= \^cnt_read_reg[4]_rep__2_0\;
\cnt_read_reg[4]_rep__2_1\ <= \^cnt_read_reg[4]_rep__2_1\;
\cnt_read_reg[4]_rep__2_2\ <= \^cnt_read_reg[4]_rep__2_2\;
\cnt_read[0]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"69"
)
port map (
I0 => \cnt_read_reg[0]_rep__2_n_0\,
I1 => s_ready_i_reg,
I2 => \cnt_read[4]_i_5_n_0\,
O => \cnt_read[0]_i_1__1_n_0\
);
\cnt_read[1]_i_1__2\: unisim.vcomponents.LUT4
generic map(
INIT => X"9AA6"
)
port map (
I0 => \cnt_read_reg[1]_rep__2_n_0\,
I1 => \cnt_read_reg[0]_rep__2_n_0\,
I2 => s_ready_i_reg,
I3 => \cnt_read[4]_i_5_n_0\,
O => \cnt_read[1]_i_1__2_n_0\
);
\cnt_read[2]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"A9AAAA6A"
)
port map (
I0 => \cnt_read_reg[2]_rep__2_n_0\,
I1 => \cnt_read_reg[1]_rep__2_n_0\,
I2 => \cnt_read_reg[0]_rep__2_n_0\,
I3 => \cnt_read[4]_i_5_n_0\,
I4 => s_ready_i_reg,
O => \cnt_read[2]_i_1_n_0\
);
\cnt_read[3]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAAAAA6AA9AAAAAA"
)
port map (
I0 => \^cnt_read_reg[4]_rep__2_0\,
I1 => \cnt_read_reg[2]_rep__2_n_0\,
I2 => \cnt_read_reg[1]_rep__2_n_0\,
I3 => \cnt_read[4]_i_5_n_0\,
I4 => s_ready_i_reg,
I5 => \cnt_read_reg[0]_rep__2_n_0\,
O => \cnt_read[3]_i_1__0_n_0\
);
\cnt_read[4]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"99AA99AA99AA55A6"
)
port map (
I0 => \^cnt_read_reg[4]_rep__2_1\,
I1 => \^cnt_read_reg[4]_rep__2_0\,
I2 => \^cnt_read_reg[4]_rep__2_2\,
I3 => \cnt_read[4]_i_3__0_n_0\,
I4 => s_ready_i_reg,
I5 => \cnt_read[4]_i_5_n_0\,
O => \cnt_read[4]_i_1_n_0\
);
\cnt_read[4]_i_2__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"7F"
)
port map (
I0 => \cnt_read_reg[0]_rep__3_n_0\,
I1 => \cnt_read_reg[1]_rep__2_n_0\,
I2 => \cnt_read_reg[2]_rep__2_n_0\,
O => \^cnt_read_reg[4]_rep__2_2\
);
\cnt_read[4]_i_3__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000100000"
)
port map (
I0 => \cnt_read_reg[2]_rep__2_n_0\,
I1 => \cnt_read_reg[1]_rep__2_n_0\,
I2 => \cnt_read[4]_i_5_n_0\,
I3 => \cnt_read_reg[4]_rep__0_0\,
I4 => si_rs_rready,
I5 => \cnt_read_reg[0]_rep__2_n_0\,
O => \cnt_read[4]_i_3__0_n_0\
);
\cnt_read[4]_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"6000E000FFFFFFFF"
)
port map (
I0 => \cnt_read_reg[2]_rep__2_n_0\,
I1 => \cnt_read_reg[1]_rep__2_n_0\,
I2 => \^cnt_read_reg[4]_rep__2_1\,
I3 => \^cnt_read_reg[4]_rep__2_0\,
I4 => \cnt_read_reg[0]_rep__3_n_0\,
I5 => m_axi_rvalid,
O => \cnt_read[4]_i_5_n_0\
);
\cnt_read_reg[0]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[0]_i_1__1_n_0\,
Q => cnt_read(0),
S => areset_d1
);
\cnt_read_reg[0]_rep\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[0]_i_1__1_n_0\,
Q => \cnt_read_reg[0]_rep_n_0\,
S => areset_d1
);
\cnt_read_reg[0]_rep__0\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[0]_i_1__1_n_0\,
Q => \cnt_read_reg[0]_rep__0_n_0\,
S => areset_d1
);
\cnt_read_reg[0]_rep__1\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[0]_i_1__1_n_0\,
Q => \cnt_read_reg[0]_rep__1_n_0\,
S => areset_d1
);
\cnt_read_reg[0]_rep__2\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[0]_i_1__1_n_0\,
Q => \cnt_read_reg[0]_rep__2_n_0\,
S => areset_d1
);
\cnt_read_reg[0]_rep__3\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[0]_i_1__1_n_0\,
Q => \cnt_read_reg[0]_rep__3_n_0\,
S => areset_d1
);
\cnt_read_reg[1]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[1]_i_1__2_n_0\,
Q => cnt_read(1),
S => areset_d1
);
\cnt_read_reg[1]_rep\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[1]_i_1__2_n_0\,
Q => \cnt_read_reg[1]_rep_n_0\,
S => areset_d1
);
\cnt_read_reg[1]_rep__0\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[1]_i_1__2_n_0\,
Q => \cnt_read_reg[1]_rep__0_n_0\,
S => areset_d1
);
\cnt_read_reg[1]_rep__1\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[1]_i_1__2_n_0\,
Q => \cnt_read_reg[1]_rep__1_n_0\,
S => areset_d1
);
\cnt_read_reg[1]_rep__2\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[1]_i_1__2_n_0\,
Q => \cnt_read_reg[1]_rep__2_n_0\,
S => areset_d1
);
\cnt_read_reg[2]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[2]_i_1_n_0\,
Q => cnt_read(2),
S => areset_d1
);
\cnt_read_reg[2]_rep\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[2]_i_1_n_0\,
Q => \cnt_read_reg[2]_rep_n_0\,
S => areset_d1
);
\cnt_read_reg[2]_rep__0\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[2]_i_1_n_0\,
Q => \cnt_read_reg[2]_rep__0_n_0\,
S => areset_d1
);
\cnt_read_reg[2]_rep__1\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[2]_i_1_n_0\,
Q => \cnt_read_reg[2]_rep__1_n_0\,
S => areset_d1
);
\cnt_read_reg[2]_rep__2\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[2]_i_1_n_0\,
Q => \cnt_read_reg[2]_rep__2_n_0\,
S => areset_d1
);
\cnt_read_reg[3]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[3]_i_1__0_n_0\,
Q => cnt_read(3),
S => areset_d1
);
\cnt_read_reg[3]_rep\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[3]_i_1__0_n_0\,
Q => \cnt_read_reg[3]_rep_n_0\,
S => areset_d1
);
\cnt_read_reg[3]_rep__0\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[3]_i_1__0_n_0\,
Q => \cnt_read_reg[3]_rep__0_n_0\,
S => areset_d1
);
\cnt_read_reg[3]_rep__1\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[3]_i_1__0_n_0\,
Q => \cnt_read_reg[3]_rep__1_n_0\,
S => areset_d1
);
\cnt_read_reg[3]_rep__2\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[3]_i_1__0_n_0\,
Q => \^cnt_read_reg[4]_rep__2_0\,
S => areset_d1
);
\cnt_read_reg[4]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[4]_i_1_n_0\,
Q => cnt_read(4),
S => areset_d1
);
\cnt_read_reg[4]_rep\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[4]_i_1_n_0\,
Q => \cnt_read_reg[4]_rep_n_0\,
S => areset_d1
);
\cnt_read_reg[4]_rep__0\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[4]_i_1_n_0\,
Q => \cnt_read_reg[4]_rep__0_n_0\,
S => areset_d1
);
\cnt_read_reg[4]_rep__1\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[4]_i_1_n_0\,
Q => \cnt_read_reg[4]_rep__1_n_0\,
S => areset_d1
);
\cnt_read_reg[4]_rep__2\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[4]_i_1_n_0\,
Q => \^cnt_read_reg[4]_rep__2_1\,
S => areset_d1
);
m_axi_rready_INST_0: unisim.vcomponents.LUT5
generic map(
INIT => X"9FFF1FFF"
)
port map (
I0 => \cnt_read_reg[2]_rep__2_n_0\,
I1 => \cnt_read_reg[1]_rep__2_n_0\,
I2 => \^cnt_read_reg[4]_rep__2_1\,
I3 => \^cnt_read_reg[4]_rep__2_0\,
I4 => \cnt_read_reg[0]_rep__3_n_0\,
O => m_axi_rready
);
\memory_reg[31][0]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep__1_n_0\,
A(3) => \cnt_read_reg[3]_rep__1_n_0\,
A(2) => \cnt_read_reg[2]_rep__1_n_0\,
A(1) => \cnt_read_reg[1]_rep__1_n_0\,
A(0) => \cnt_read_reg[0]_rep__1_n_0\,
CE => wr_en0,
CLK => aclk,
D => \in\(0),
Q => \out\(0),
Q31 => \NLW_memory_reg[31][0]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][0]_srl32_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"8AAA0AAA0AAAAAAA"
)
port map (
I0 => m_axi_rvalid,
I1 => \cnt_read_reg[0]_rep__3_n_0\,
I2 => \^cnt_read_reg[4]_rep__2_0\,
I3 => \^cnt_read_reg[4]_rep__2_1\,
I4 => \cnt_read_reg[1]_rep__2_n_0\,
I5 => \cnt_read_reg[2]_rep__2_n_0\,
O => wr_en0
);
\memory_reg[31][10]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep__0_n_0\,
A(3) => \cnt_read_reg[3]_rep__0_n_0\,
A(2) => \cnt_read_reg[2]_rep__0_n_0\,
A(1) => \cnt_read_reg[1]_rep__0_n_0\,
A(0) => \cnt_read_reg[0]_rep__0_n_0\,
CE => wr_en0,
CLK => aclk,
D => \in\(10),
Q => \out\(10),
Q31 => \NLW_memory_reg[31][10]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][11]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep__0_n_0\,
A(3) => \cnt_read_reg[3]_rep__0_n_0\,
A(2) => \cnt_read_reg[2]_rep__0_n_0\,
A(1) => \cnt_read_reg[1]_rep__0_n_0\,
A(0) => \cnt_read_reg[0]_rep__0_n_0\,
CE => wr_en0,
CLK => aclk,
D => \in\(11),
Q => \out\(11),
Q31 => \NLW_memory_reg[31][11]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][12]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep__0_n_0\,
A(3) => \cnt_read_reg[3]_rep__0_n_0\,
A(2) => \cnt_read_reg[2]_rep__0_n_0\,
A(1) => \cnt_read_reg[1]_rep__0_n_0\,
A(0) => \cnt_read_reg[0]_rep__0_n_0\,
CE => wr_en0,
CLK => aclk,
D => \in\(12),
Q => \out\(12),
Q31 => \NLW_memory_reg[31][12]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][13]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep__0_n_0\,
A(3) => \cnt_read_reg[3]_rep__0_n_0\,
A(2) => \cnt_read_reg[2]_rep__0_n_0\,
A(1) => \cnt_read_reg[1]_rep__0_n_0\,
A(0) => \cnt_read_reg[0]_rep__0_n_0\,
CE => wr_en0,
CLK => aclk,
D => \in\(13),
Q => \out\(13),
Q31 => \NLW_memory_reg[31][13]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][14]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep__0_n_0\,
A(3) => \cnt_read_reg[3]_rep__0_n_0\,
A(2) => \cnt_read_reg[2]_rep__0_n_0\,
A(1) => \cnt_read_reg[1]_rep__0_n_0\,
A(0) => \cnt_read_reg[0]_rep__0_n_0\,
CE => wr_en0,
CLK => aclk,
D => \in\(14),
Q => \out\(14),
Q31 => \NLW_memory_reg[31][14]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][15]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep__0_n_0\,
A(3) => \cnt_read_reg[3]_rep__0_n_0\,
A(2) => \cnt_read_reg[2]_rep__0_n_0\,
A(1) => \cnt_read_reg[1]_rep__0_n_0\,
A(0) => \cnt_read_reg[0]_rep__0_n_0\,
CE => wr_en0,
CLK => aclk,
D => \in\(15),
Q => \out\(15),
Q31 => \NLW_memory_reg[31][15]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][16]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep_n_0\,
A(3) => \cnt_read_reg[3]_rep_n_0\,
A(2) => \cnt_read_reg[2]_rep_n_0\,
A(1) => \cnt_read_reg[1]_rep_n_0\,
A(0) => \cnt_read_reg[0]_rep_n_0\,
CE => wr_en0,
CLK => aclk,
D => \in\(16),
Q => \out\(16),
Q31 => \NLW_memory_reg[31][16]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][17]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep_n_0\,
A(3) => \cnt_read_reg[3]_rep_n_0\,
A(2) => \cnt_read_reg[2]_rep_n_0\,
A(1) => \cnt_read_reg[1]_rep_n_0\,
A(0) => \cnt_read_reg[0]_rep_n_0\,
CE => wr_en0,
CLK => aclk,
D => \in\(17),
Q => \out\(17),
Q31 => \NLW_memory_reg[31][17]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][18]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep_n_0\,
A(3) => \cnt_read_reg[3]_rep_n_0\,
A(2) => \cnt_read_reg[2]_rep_n_0\,
A(1) => \cnt_read_reg[1]_rep_n_0\,
A(0) => \cnt_read_reg[0]_rep_n_0\,
CE => wr_en0,
CLK => aclk,
D => \in\(18),
Q => \out\(18),
Q31 => \NLW_memory_reg[31][18]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][19]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep_n_0\,
A(3) => \cnt_read_reg[3]_rep_n_0\,
A(2) => \cnt_read_reg[2]_rep_n_0\,
A(1) => \cnt_read_reg[1]_rep_n_0\,
A(0) => \cnt_read_reg[0]_rep_n_0\,
CE => wr_en0,
CLK => aclk,
D => \in\(19),
Q => \out\(19),
Q31 => \NLW_memory_reg[31][19]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][1]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep__1_n_0\,
A(3) => \cnt_read_reg[3]_rep__1_n_0\,
A(2) => \cnt_read_reg[2]_rep__1_n_0\,
A(1) => \cnt_read_reg[1]_rep__1_n_0\,
A(0) => \cnt_read_reg[0]_rep__1_n_0\,
CE => wr_en0,
CLK => aclk,
D => \in\(1),
Q => \out\(1),
Q31 => \NLW_memory_reg[31][1]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][20]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep_n_0\,
A(3) => \cnt_read_reg[3]_rep_n_0\,
A(2) => \cnt_read_reg[2]_rep_n_0\,
A(1) => \cnt_read_reg[1]_rep_n_0\,
A(0) => \cnt_read_reg[0]_rep_n_0\,
CE => wr_en0,
CLK => aclk,
D => \in\(20),
Q => \out\(20),
Q31 => \NLW_memory_reg[31][20]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][21]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep_n_0\,
A(3) => \cnt_read_reg[3]_rep_n_0\,
A(2) => \cnt_read_reg[2]_rep_n_0\,
A(1) => \cnt_read_reg[1]_rep_n_0\,
A(0) => \cnt_read_reg[0]_rep_n_0\,
CE => wr_en0,
CLK => aclk,
D => \in\(21),
Q => \out\(21),
Q31 => \NLW_memory_reg[31][21]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][22]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep_n_0\,
A(3) => \cnt_read_reg[3]_rep_n_0\,
A(2) => \cnt_read_reg[2]_rep_n_0\,
A(1) => \cnt_read_reg[1]_rep_n_0\,
A(0) => \cnt_read_reg[0]_rep_n_0\,
CE => wr_en0,
CLK => aclk,
D => \in\(22),
Q => \out\(22),
Q31 => \NLW_memory_reg[31][22]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][23]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep_n_0\,
A(3) => \cnt_read_reg[3]_rep_n_0\,
A(2) => \cnt_read_reg[2]_rep_n_0\,
A(1) => \cnt_read_reg[1]_rep_n_0\,
A(0) => \cnt_read_reg[0]_rep_n_0\,
CE => wr_en0,
CLK => aclk,
D => \in\(23),
Q => \out\(23),
Q31 => \NLW_memory_reg[31][23]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][24]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep_n_0\,
A(3) => \cnt_read_reg[3]_rep_n_0\,
A(2) => \cnt_read_reg[2]_rep_n_0\,
A(1) => \cnt_read_reg[1]_rep_n_0\,
A(0) => \cnt_read_reg[0]_rep_n_0\,
CE => wr_en0,
CLK => aclk,
D => \in\(24),
Q => \out\(24),
Q31 => \NLW_memory_reg[31][24]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][25]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => cnt_read(4 downto 0),
CE => wr_en0,
CLK => aclk,
D => \in\(25),
Q => \out\(25),
Q31 => \NLW_memory_reg[31][25]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][26]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => cnt_read(4 downto 0),
CE => wr_en0,
CLK => aclk,
D => \in\(26),
Q => \out\(26),
Q31 => \NLW_memory_reg[31][26]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][27]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => cnt_read(4 downto 0),
CE => wr_en0,
CLK => aclk,
D => \in\(27),
Q => \out\(27),
Q31 => \NLW_memory_reg[31][27]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][28]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => cnt_read(4 downto 0),
CE => wr_en0,
CLK => aclk,
D => \in\(28),
Q => \out\(28),
Q31 => \NLW_memory_reg[31][28]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][29]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => cnt_read(4 downto 0),
CE => wr_en0,
CLK => aclk,
D => \in\(29),
Q => \out\(29),
Q31 => \NLW_memory_reg[31][29]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][2]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep__1_n_0\,
A(3) => \cnt_read_reg[3]_rep__1_n_0\,
A(2) => \cnt_read_reg[2]_rep__1_n_0\,
A(1) => \cnt_read_reg[1]_rep__1_n_0\,
A(0) => \cnt_read_reg[0]_rep__1_n_0\,
CE => wr_en0,
CLK => aclk,
D => \in\(2),
Q => \out\(2),
Q31 => \NLW_memory_reg[31][2]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][30]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => cnt_read(4 downto 0),
CE => wr_en0,
CLK => aclk,
D => \in\(30),
Q => \out\(30),
Q31 => \NLW_memory_reg[31][30]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][31]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => cnt_read(4 downto 0),
CE => wr_en0,
CLK => aclk,
D => \in\(31),
Q => \out\(31),
Q31 => \NLW_memory_reg[31][31]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][32]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => cnt_read(4 downto 0),
CE => wr_en0,
CLK => aclk,
D => \in\(32),
Q => \out\(32),
Q31 => \NLW_memory_reg[31][32]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][33]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => cnt_read(4 downto 0),
CE => wr_en0,
CLK => aclk,
D => \in\(33),
Q => \out\(33),
Q31 => \NLW_memory_reg[31][33]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][3]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep__1_n_0\,
A(3) => \cnt_read_reg[3]_rep__1_n_0\,
A(2) => \cnt_read_reg[2]_rep__1_n_0\,
A(1) => \cnt_read_reg[1]_rep__1_n_0\,
A(0) => \cnt_read_reg[0]_rep__1_n_0\,
CE => wr_en0,
CLK => aclk,
D => \in\(3),
Q => \out\(3),
Q31 => \NLW_memory_reg[31][3]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][4]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep__1_n_0\,
A(3) => \cnt_read_reg[3]_rep__1_n_0\,
A(2) => \cnt_read_reg[2]_rep__1_n_0\,
A(1) => \cnt_read_reg[1]_rep__1_n_0\,
A(0) => \cnt_read_reg[0]_rep__1_n_0\,
CE => wr_en0,
CLK => aclk,
D => \in\(4),
Q => \out\(4),
Q31 => \NLW_memory_reg[31][4]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][5]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep__1_n_0\,
A(3) => \cnt_read_reg[3]_rep__1_n_0\,
A(2) => \cnt_read_reg[2]_rep__1_n_0\,
A(1) => \cnt_read_reg[1]_rep__1_n_0\,
A(0) => \cnt_read_reg[0]_rep__1_n_0\,
CE => wr_en0,
CLK => aclk,
D => \in\(5),
Q => \out\(5),
Q31 => \NLW_memory_reg[31][5]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][6]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep__1_n_0\,
A(3) => \cnt_read_reg[3]_rep__1_n_0\,
A(2) => \cnt_read_reg[2]_rep__1_n_0\,
A(1) => \cnt_read_reg[1]_rep__1_n_0\,
A(0) => \cnt_read_reg[0]_rep__1_n_0\,
CE => wr_en0,
CLK => aclk,
D => \in\(6),
Q => \out\(6),
Q31 => \NLW_memory_reg[31][6]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][7]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep__0_n_0\,
A(3) => \cnt_read_reg[3]_rep__0_n_0\,
A(2) => \cnt_read_reg[2]_rep__0_n_0\,
A(1) => \cnt_read_reg[1]_rep__0_n_0\,
A(0) => \cnt_read_reg[0]_rep__0_n_0\,
CE => wr_en0,
CLK => aclk,
D => \in\(7),
Q => \out\(7),
Q31 => \NLW_memory_reg[31][7]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][8]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep__0_n_0\,
A(3) => \cnt_read_reg[3]_rep__0_n_0\,
A(2) => \cnt_read_reg[2]_rep__0_n_0\,
A(1) => \cnt_read_reg[1]_rep__0_n_0\,
A(0) => \cnt_read_reg[0]_rep__0_n_0\,
CE => wr_en0,
CLK => aclk,
D => \in\(8),
Q => \out\(8),
Q31 => \NLW_memory_reg[31][8]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][9]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep__0_n_0\,
A(3) => \cnt_read_reg[3]_rep__0_n_0\,
A(2) => \cnt_read_reg[2]_rep__0_n_0\,
A(1) => \cnt_read_reg[1]_rep__0_n_0\,
A(0) => \cnt_read_reg[0]_rep__0_n_0\,
CE => wr_en0,
CLK => aclk,
D => \in\(9),
Q => \out\(9),
Q31 => \NLW_memory_reg[31][9]_srl32_Q31_UNCONNECTED\
);
\state[1]_i_4\: unisim.vcomponents.LUT5
generic map(
INIT => X"40C0C000"
)
port map (
I0 => \cnt_read_reg[0]_rep__3_n_0\,
I1 => \^cnt_read_reg[4]_rep__2_0\,
I2 => \^cnt_read_reg[4]_rep__2_1\,
I3 => \cnt_read_reg[1]_rep__2_n_0\,
I4 => \cnt_read_reg[2]_rep__2_n_0\,
O => \state_reg[1]_rep\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \zybo_zynq_design_auto_pc_0_axi_protocol_converter_v2_1_17_b2s_simple_fifo__parameterized2\ is
port (
m_valid_i_reg : out STD_LOGIC;
\state_reg[1]_rep\ : out STD_LOGIC;
\skid_buffer_reg[46]\ : out STD_LOGIC_VECTOR ( 12 downto 0 );
s_ready_i_reg : in STD_LOGIC;
r_push_r : in STD_LOGIC;
si_rs_rready : in STD_LOGIC;
\cnt_read_reg[3]_rep__2\ : in STD_LOGIC;
\cnt_read_reg[4]_rep__2\ : in STD_LOGIC;
\cnt_read_reg[0]_rep__3\ : in STD_LOGIC;
\cnt_read_reg[0]_rep__3_0\ : in STD_LOGIC;
\in\ : in STD_LOGIC_VECTOR ( 12 downto 0 );
aclk : in STD_LOGIC;
areset_d1 : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \zybo_zynq_design_auto_pc_0_axi_protocol_converter_v2_1_17_b2s_simple_fifo__parameterized2\ : entity is "axi_protocol_converter_v2_1_17_b2s_simple_fifo";
end \zybo_zynq_design_auto_pc_0_axi_protocol_converter_v2_1_17_b2s_simple_fifo__parameterized2\;
architecture STRUCTURE of \zybo_zynq_design_auto_pc_0_axi_protocol_converter_v2_1_17_b2s_simple_fifo__parameterized2\ is
signal cnt_read : STD_LOGIC_VECTOR ( 4 downto 0 );
signal \cnt_read[0]_i_1__0_n_0\ : STD_LOGIC;
signal \cnt_read[1]_i_1__1_n_0\ : STD_LOGIC;
signal \cnt_read[2]_i_1__0_n_0\ : STD_LOGIC;
signal \cnt_read[3]_i_1_n_0\ : STD_LOGIC;
signal \cnt_read[4]_i_1__0_n_0\ : STD_LOGIC;
signal \cnt_read[4]_i_2_n_0\ : STD_LOGIC;
signal \cnt_read[4]_i_3_n_0\ : STD_LOGIC;
signal \cnt_read_reg[0]_rep__0_n_0\ : STD_LOGIC;
signal \cnt_read_reg[0]_rep__1_n_0\ : STD_LOGIC;
signal \cnt_read_reg[0]_rep_n_0\ : STD_LOGIC;
signal \cnt_read_reg[1]_rep__0_n_0\ : STD_LOGIC;
signal \cnt_read_reg[1]_rep_n_0\ : STD_LOGIC;
signal \cnt_read_reg[2]_rep__0_n_0\ : STD_LOGIC;
signal \cnt_read_reg[2]_rep_n_0\ : STD_LOGIC;
signal \cnt_read_reg[3]_rep__0_n_0\ : STD_LOGIC;
signal \cnt_read_reg[3]_rep_n_0\ : STD_LOGIC;
signal \cnt_read_reg[4]_rep__0_n_0\ : STD_LOGIC;
signal \cnt_read_reg[4]_rep_n_0\ : STD_LOGIC;
signal m_valid_i_i_3_n_0 : STD_LOGIC;
signal \^m_valid_i_reg\ : STD_LOGIC;
signal \NLW_memory_reg[31][0]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][10]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][11]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][12]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][1]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][2]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][3]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][4]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][5]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][6]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][7]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][8]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][9]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \cnt_read[1]_i_1__1\ : label is "soft_lutpair20";
attribute SOFT_HLUTNM of \cnt_read[2]_i_1__0\ : label is "soft_lutpair20";
attribute KEEP : string;
attribute KEEP of \cnt_read_reg[0]\ : label is "yes";
attribute ORIG_CELL_NAME : string;
attribute ORIG_CELL_NAME of \cnt_read_reg[0]\ : label is "cnt_read_reg[0]";
attribute IS_FANOUT_CONSTRAINED : integer;
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[0]_rep\ : label is 1;
attribute KEEP of \cnt_read_reg[0]_rep\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[0]_rep\ : label is "cnt_read_reg[0]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[0]_rep__0\ : label is 1;
attribute KEEP of \cnt_read_reg[0]_rep__0\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[0]_rep__0\ : label is "cnt_read_reg[0]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[0]_rep__1\ : label is 1;
attribute KEEP of \cnt_read_reg[0]_rep__1\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[0]_rep__1\ : label is "cnt_read_reg[0]";
attribute KEEP of \cnt_read_reg[1]\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[1]\ : label is "cnt_read_reg[1]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[1]_rep\ : label is 1;
attribute KEEP of \cnt_read_reg[1]_rep\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[1]_rep\ : label is "cnt_read_reg[1]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[1]_rep__0\ : label is 1;
attribute KEEP of \cnt_read_reg[1]_rep__0\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[1]_rep__0\ : label is "cnt_read_reg[1]";
attribute KEEP of \cnt_read_reg[2]\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[2]\ : label is "cnt_read_reg[2]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[2]_rep\ : label is 1;
attribute KEEP of \cnt_read_reg[2]_rep\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[2]_rep\ : label is "cnt_read_reg[2]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[2]_rep__0\ : label is 1;
attribute KEEP of \cnt_read_reg[2]_rep__0\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[2]_rep__0\ : label is "cnt_read_reg[2]";
attribute KEEP of \cnt_read_reg[3]\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[3]\ : label is "cnt_read_reg[3]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[3]_rep\ : label is 1;
attribute KEEP of \cnt_read_reg[3]_rep\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[3]_rep\ : label is "cnt_read_reg[3]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[3]_rep__0\ : label is 1;
attribute KEEP of \cnt_read_reg[3]_rep__0\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[3]_rep__0\ : label is "cnt_read_reg[3]";
attribute KEEP of \cnt_read_reg[4]\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[4]\ : label is "cnt_read_reg[4]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[4]_rep\ : label is 1;
attribute KEEP of \cnt_read_reg[4]_rep\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[4]_rep\ : label is "cnt_read_reg[4]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[4]_rep__0\ : label is 1;
attribute KEEP of \cnt_read_reg[4]_rep__0\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[4]_rep__0\ : label is "cnt_read_reg[4]";
attribute srl_bus_name : string;
attribute srl_bus_name of \memory_reg[31][0]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31] ";
attribute srl_name : string;
attribute srl_name of \memory_reg[31][0]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][0]_srl32 ";
attribute srl_bus_name of \memory_reg[31][10]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][10]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][10]_srl32 ";
attribute srl_bus_name of \memory_reg[31][11]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][11]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][11]_srl32 ";
attribute srl_bus_name of \memory_reg[31][12]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][12]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][12]_srl32 ";
attribute srl_bus_name of \memory_reg[31][1]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][1]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][1]_srl32 ";
attribute srl_bus_name of \memory_reg[31][2]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][2]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][2]_srl32 ";
attribute srl_bus_name of \memory_reg[31][3]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][3]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][3]_srl32 ";
attribute srl_bus_name of \memory_reg[31][4]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][4]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][4]_srl32 ";
attribute srl_bus_name of \memory_reg[31][5]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][5]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][5]_srl32 ";
attribute srl_bus_name of \memory_reg[31][6]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][6]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][6]_srl32 ";
attribute srl_bus_name of \memory_reg[31][7]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][7]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][7]_srl32 ";
attribute srl_bus_name of \memory_reg[31][8]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][8]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][8]_srl32 ";
attribute srl_bus_name of \memory_reg[31][9]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][9]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][9]_srl32 ";
begin
m_valid_i_reg <= \^m_valid_i_reg\;
\cnt_read[0]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => \cnt_read_reg[0]_rep__0_n_0\,
I1 => r_push_r,
I2 => s_ready_i_reg,
O => \cnt_read[0]_i_1__0_n_0\
);
\cnt_read[1]_i_1__1\: unisim.vcomponents.LUT4
generic map(
INIT => X"DB24"
)
port map (
I0 => \cnt_read_reg[0]_rep__0_n_0\,
I1 => s_ready_i_reg,
I2 => r_push_r,
I3 => \cnt_read_reg[1]_rep__0_n_0\,
O => \cnt_read[1]_i_1__1_n_0\
);
\cnt_read[2]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"9AAAAAA6"
)
port map (
I0 => \cnt_read_reg[2]_rep__0_n_0\,
I1 => s_ready_i_reg,
I2 => r_push_r,
I3 => \cnt_read_reg[0]_rep__0_n_0\,
I4 => \cnt_read_reg[1]_rep__0_n_0\,
O => \cnt_read[2]_i_1__0_n_0\
);
\cnt_read[3]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FF7F0080FEFF0100"
)
port map (
I0 => \cnt_read_reg[1]_rep__0_n_0\,
I1 => \cnt_read_reg[0]_rep__0_n_0\,
I2 => r_push_r,
I3 => s_ready_i_reg,
I4 => \cnt_read_reg[3]_rep__0_n_0\,
I5 => \cnt_read_reg[2]_rep__0_n_0\,
O => \cnt_read[3]_i_1_n_0\
);
\cnt_read[4]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"9A999AAA"
)
port map (
I0 => \cnt_read_reg[4]_rep__0_n_0\,
I1 => \cnt_read[4]_i_2_n_0\,
I2 => \cnt_read_reg[2]_rep__0_n_0\,
I3 => \cnt_read_reg[3]_rep__0_n_0\,
I4 => \cnt_read[4]_i_3_n_0\,
O => \cnt_read[4]_i_1__0_n_0\
);
\cnt_read[4]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"2AAAAAAA2AAA2AAA"
)
port map (
I0 => \cnt_read_reg[2]_rep__0_n_0\,
I1 => \cnt_read_reg[1]_rep__0_n_0\,
I2 => \cnt_read_reg[0]_rep__1_n_0\,
I3 => r_push_r,
I4 => \^m_valid_i_reg\,
I5 => si_rs_rready,
O => \cnt_read[4]_i_2_n_0\
);
\cnt_read[4]_i_3\: unisim.vcomponents.LUT5
generic map(
INIT => X"00000004"
)
port map (
I0 => r_push_r,
I1 => si_rs_rready,
I2 => \^m_valid_i_reg\,
I3 => \cnt_read_reg[0]_rep__1_n_0\,
I4 => \cnt_read_reg[1]_rep__0_n_0\,
O => \cnt_read[4]_i_3_n_0\
);
\cnt_read_reg[0]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[0]_i_1__0_n_0\,
Q => cnt_read(0),
S => areset_d1
);
\cnt_read_reg[0]_rep\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[0]_i_1__0_n_0\,
Q => \cnt_read_reg[0]_rep_n_0\,
S => areset_d1
);
\cnt_read_reg[0]_rep__0\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[0]_i_1__0_n_0\,
Q => \cnt_read_reg[0]_rep__0_n_0\,
S => areset_d1
);
\cnt_read_reg[0]_rep__1\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[0]_i_1__0_n_0\,
Q => \cnt_read_reg[0]_rep__1_n_0\,
S => areset_d1
);
\cnt_read_reg[1]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[1]_i_1__1_n_0\,
Q => cnt_read(1),
S => areset_d1
);
\cnt_read_reg[1]_rep\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[1]_i_1__1_n_0\,
Q => \cnt_read_reg[1]_rep_n_0\,
S => areset_d1
);
\cnt_read_reg[1]_rep__0\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[1]_i_1__1_n_0\,
Q => \cnt_read_reg[1]_rep__0_n_0\,
S => areset_d1
);
\cnt_read_reg[2]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[2]_i_1__0_n_0\,
Q => cnt_read(2),
S => areset_d1
);
\cnt_read_reg[2]_rep\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[2]_i_1__0_n_0\,
Q => \cnt_read_reg[2]_rep_n_0\,
S => areset_d1
);
\cnt_read_reg[2]_rep__0\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[2]_i_1__0_n_0\,
Q => \cnt_read_reg[2]_rep__0_n_0\,
S => areset_d1
);
\cnt_read_reg[3]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[3]_i_1_n_0\,
Q => cnt_read(3),
S => areset_d1
);
\cnt_read_reg[3]_rep\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[3]_i_1_n_0\,
Q => \cnt_read_reg[3]_rep_n_0\,
S => areset_d1
);
\cnt_read_reg[3]_rep__0\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[3]_i_1_n_0\,
Q => \cnt_read_reg[3]_rep__0_n_0\,
S => areset_d1
);
\cnt_read_reg[4]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[4]_i_1__0_n_0\,
Q => cnt_read(4),
S => areset_d1
);
\cnt_read_reg[4]_rep\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[4]_i_1__0_n_0\,
Q => \cnt_read_reg[4]_rep_n_0\,
S => areset_d1
);
\cnt_read_reg[4]_rep__0\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[4]_i_1__0_n_0\,
Q => \cnt_read_reg[4]_rep__0_n_0\,
S => areset_d1
);
m_valid_i_i_2: unisim.vcomponents.LUT6
generic map(
INIT => X"80808080FF808080"
)
port map (
I0 => \cnt_read_reg[4]_rep__0_n_0\,
I1 => \cnt_read_reg[3]_rep__0_n_0\,
I2 => m_valid_i_i_3_n_0,
I3 => \cnt_read_reg[3]_rep__2\,
I4 => \cnt_read_reg[4]_rep__2\,
I5 => \cnt_read_reg[0]_rep__3\,
O => \^m_valid_i_reg\
);
m_valid_i_i_3: unisim.vcomponents.LUT3
generic map(
INIT => X"80"
)
port map (
I0 => \cnt_read_reg[2]_rep__0_n_0\,
I1 => \cnt_read_reg[0]_rep__1_n_0\,
I2 => \cnt_read_reg[1]_rep__0_n_0\,
O => m_valid_i_i_3_n_0
);
\memory_reg[31][0]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep_n_0\,
A(3) => \cnt_read_reg[3]_rep_n_0\,
A(2) => \cnt_read_reg[2]_rep_n_0\,
A(1) => \cnt_read_reg[1]_rep_n_0\,
A(0) => \cnt_read_reg[0]_rep_n_0\,
CE => r_push_r,
CLK => aclk,
D => \in\(0),
Q => \skid_buffer_reg[46]\(0),
Q31 => \NLW_memory_reg[31][0]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][10]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => cnt_read(4 downto 0),
CE => r_push_r,
CLK => aclk,
D => \in\(10),
Q => \skid_buffer_reg[46]\(10),
Q31 => \NLW_memory_reg[31][10]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][11]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => cnt_read(4 downto 0),
CE => r_push_r,
CLK => aclk,
D => \in\(11),
Q => \skid_buffer_reg[46]\(11),
Q31 => \NLW_memory_reg[31][11]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][12]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => cnt_read(4 downto 0),
CE => r_push_r,
CLK => aclk,
D => \in\(12),
Q => \skid_buffer_reg[46]\(12),
Q31 => \NLW_memory_reg[31][12]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][1]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep_n_0\,
A(3) => \cnt_read_reg[3]_rep_n_0\,
A(2) => \cnt_read_reg[2]_rep_n_0\,
A(1) => \cnt_read_reg[1]_rep_n_0\,
A(0) => \cnt_read_reg[0]_rep_n_0\,
CE => r_push_r,
CLK => aclk,
D => \in\(1),
Q => \skid_buffer_reg[46]\(1),
Q31 => \NLW_memory_reg[31][1]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][2]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep_n_0\,
A(3) => \cnt_read_reg[3]_rep_n_0\,
A(2) => \cnt_read_reg[2]_rep_n_0\,
A(1) => \cnt_read_reg[1]_rep_n_0\,
A(0) => \cnt_read_reg[0]_rep_n_0\,
CE => r_push_r,
CLK => aclk,
D => \in\(2),
Q => \skid_buffer_reg[46]\(2),
Q31 => \NLW_memory_reg[31][2]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][3]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep_n_0\,
A(3) => \cnt_read_reg[3]_rep_n_0\,
A(2) => \cnt_read_reg[2]_rep_n_0\,
A(1) => \cnt_read_reg[1]_rep_n_0\,
A(0) => \cnt_read_reg[0]_rep_n_0\,
CE => r_push_r,
CLK => aclk,
D => \in\(3),
Q => \skid_buffer_reg[46]\(3),
Q31 => \NLW_memory_reg[31][3]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][4]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep_n_0\,
A(3) => \cnt_read_reg[3]_rep_n_0\,
A(2) => \cnt_read_reg[2]_rep_n_0\,
A(1) => \cnt_read_reg[1]_rep_n_0\,
A(0) => \cnt_read_reg[0]_rep_n_0\,
CE => r_push_r,
CLK => aclk,
D => \in\(4),
Q => \skid_buffer_reg[46]\(4),
Q31 => \NLW_memory_reg[31][4]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][5]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep_n_0\,
A(3) => \cnt_read_reg[3]_rep_n_0\,
A(2) => \cnt_read_reg[2]_rep_n_0\,
A(1) => \cnt_read_reg[1]_rep_n_0\,
A(0) => \cnt_read_reg[0]_rep_n_0\,
CE => r_push_r,
CLK => aclk,
D => \in\(5),
Q => \skid_buffer_reg[46]\(5),
Q31 => \NLW_memory_reg[31][5]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][6]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => cnt_read(4 downto 0),
CE => r_push_r,
CLK => aclk,
D => \in\(6),
Q => \skid_buffer_reg[46]\(6),
Q31 => \NLW_memory_reg[31][6]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][7]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => cnt_read(4 downto 0),
CE => r_push_r,
CLK => aclk,
D => \in\(7),
Q => \skid_buffer_reg[46]\(7),
Q31 => \NLW_memory_reg[31][7]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][8]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => cnt_read(4 downto 0),
CE => r_push_r,
CLK => aclk,
D => \in\(8),
Q => \skid_buffer_reg[46]\(8),
Q31 => \NLW_memory_reg[31][8]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][9]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => cnt_read(4 downto 0),
CE => r_push_r,
CLK => aclk,
D => \in\(9),
Q => \skid_buffer_reg[46]\(9),
Q31 => \NLW_memory_reg[31][9]_srl32_Q31_UNCONNECTED\
);
\state[1]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"BFEEAAAAAAAAAAAA"
)
port map (
I0 => \cnt_read_reg[0]_rep__3_0\,
I1 => \cnt_read_reg[2]_rep__0_n_0\,
I2 => \cnt_read_reg[0]_rep__1_n_0\,
I3 => \cnt_read_reg[1]_rep__0_n_0\,
I4 => \cnt_read_reg[3]_rep__0_n_0\,
I5 => \cnt_read_reg[4]_rep__0_n_0\,
O => \state_reg[1]_rep\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity zybo_zynq_design_auto_pc_0_axi_protocol_converter_v2_1_17_b2s_wr_cmd_fsm is
port (
\axlen_cnt_reg[7]\ : out STD_LOGIC;
\axlen_cnt_reg[7]_0\ : out STD_LOGIC;
\axlen_cnt_reg[7]_1\ : out STD_LOGIC;
\next\ : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 1 downto 0 );
D : out STD_LOGIC_VECTOR ( 0 to 0 );
\wrap_second_len_r_reg[0]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\axlen_cnt_reg[0]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axburst_eq0_reg : out STD_LOGIC;
incr_next_pending : out STD_LOGIC;
sel_first_i : out STD_LOGIC;
s_axburst_eq1_reg : out STD_LOGIC;
E : out STD_LOGIC_VECTOR ( 0 to 0 );
\axaddr_wrap_reg[11]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
sel_first_reg : out STD_LOGIC;
sel_first_reg_0 : out STD_LOGIC;
\wrap_cnt_r_reg[3]\ : out STD_LOGIC;
\axaddr_offset_r_reg[2]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\wrap_cnt_r_reg[3]_0\ : out STD_LOGIC;
\m_payload_i_reg[0]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
b_push : out STD_LOGIC;
m_axi_awvalid : out STD_LOGIC;
s_axburst_eq1_reg_0 : in STD_LOGIC;
\cnt_read_reg[1]_rep__0\ : in STD_LOGIC;
\cnt_read_reg[0]_rep__0\ : in STD_LOGIC;
m_axi_awready : in STD_LOGIC;
si_rs_awvalid : in STD_LOGIC;
\axlen_cnt_reg[7]_2\ : in STD_LOGIC;
\wrap_second_len_r_reg[0]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\axaddr_offset_r_reg[3]\ : in STD_LOGIC;
axaddr_offset : in STD_LOGIC_VECTOR ( 0 to 0 );
\m_payload_i_reg[46]\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
\axlen_cnt_reg[0]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 );
wrap_next_pending : in STD_LOGIC;
next_pending_r_reg : in STD_LOGIC;
\m_payload_i_reg[47]\ : in STD_LOGIC;
sel_first : in STD_LOGIC;
areset_d1 : in STD_LOGIC;
sel_first_0 : in STD_LOGIC;
sel_first_reg_1 : in STD_LOGIC;
\axaddr_offset_r_reg[3]_0\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
\m_payload_i_reg[5]\ : in STD_LOGIC;
aclk : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of zybo_zynq_design_auto_pc_0_axi_protocol_converter_v2_1_17_b2s_wr_cmd_fsm : entity is "axi_protocol_converter_v2_1_17_b2s_wr_cmd_fsm";
end zybo_zynq_design_auto_pc_0_axi_protocol_converter_v2_1_17_b2s_wr_cmd_fsm;
architecture STRUCTURE of zybo_zynq_design_auto_pc_0_axi_protocol_converter_v2_1_17_b2s_wr_cmd_fsm is
signal \^e\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \^q\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \^axlen_cnt_reg[7]\ : STD_LOGIC;
signal \^axlen_cnt_reg[7]_0\ : STD_LOGIC;
signal \^b_push\ : STD_LOGIC;
signal \^incr_next_pending\ : STD_LOGIC;
signal \^next\ : STD_LOGIC;
signal \^sel_first_i\ : STD_LOGIC;
signal \state[0]_i_1_n_0\ : STD_LOGIC;
signal \state[0]_i_2_n_0\ : STD_LOGIC;
signal \state[1]_i_1__0_n_0\ : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \axlen_cnt[3]_i_1__0\ : label is "soft_lutpair109";
attribute SOFT_HLUTNM of \axlen_cnt[7]_i_1__0\ : label is "soft_lutpair108";
attribute SOFT_HLUTNM of s_axburst_eq0_i_1 : label is "soft_lutpair110";
attribute SOFT_HLUTNM of s_axburst_eq1_i_1 : label is "soft_lutpair110";
attribute SOFT_HLUTNM of \state[0]_i_1\ : label is "soft_lutpair109";
attribute KEEP : string;
attribute KEEP of \state_reg[0]\ : label is "yes";
attribute ORIG_CELL_NAME : string;
attribute ORIG_CELL_NAME of \state_reg[0]\ : label is "state_reg[0]";
attribute IS_FANOUT_CONSTRAINED : integer;
attribute IS_FANOUT_CONSTRAINED of \state_reg[0]_rep\ : label is 1;
attribute KEEP of \state_reg[0]_rep\ : label is "yes";
attribute ORIG_CELL_NAME of \state_reg[0]_rep\ : label is "state_reg[0]";
attribute KEEP of \state_reg[1]\ : label is "yes";
attribute ORIG_CELL_NAME of \state_reg[1]\ : label is "state_reg[1]";
attribute IS_FANOUT_CONSTRAINED of \state_reg[1]_rep\ : label is 1;
attribute KEEP of \state_reg[1]_rep\ : label is "yes";
attribute ORIG_CELL_NAME of \state_reg[1]_rep\ : label is "state_reg[1]";
attribute SOFT_HLUTNM of \wrap_boundary_axaddr_r[11]_i_1\ : label is "soft_lutpair108";
attribute SOFT_HLUTNM of \wrap_cnt_r[3]_i_4\ : label is "soft_lutpair111";
attribute SOFT_HLUTNM of \wrap_cnt_r[3]_i_6\ : label is "soft_lutpair111";
begin
E(0) <= \^e\(0);
Q(1 downto 0) <= \^q\(1 downto 0);
\axlen_cnt_reg[7]\ <= \^axlen_cnt_reg[7]\;
\axlen_cnt_reg[7]_0\ <= \^axlen_cnt_reg[7]_0\;
b_push <= \^b_push\;
incr_next_pending <= \^incr_next_pending\;
\next\ <= \^next\;
sel_first_i <= \^sel_first_i\;
\axaddr_offset_r[2]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAAAACAAAAAAA0AA"
)
port map (
I0 => \axaddr_offset_r_reg[3]_0\(0),
I1 => \m_payload_i_reg[46]\(2),
I2 => \^axlen_cnt_reg[7]_0\,
I3 => si_rs_awvalid,
I4 => \^axlen_cnt_reg[7]\,
I5 => \m_payload_i_reg[5]\,
O => \axaddr_offset_r_reg[2]\(0)
);
\axlen_cnt[0]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"0400FFFF04000400"
)
port map (
I0 => \^q\(1),
I1 => si_rs_awvalid,
I2 => \^q\(0),
I3 => \m_payload_i_reg[46]\(1),
I4 => \axlen_cnt_reg[0]_0\(0),
I5 => \axlen_cnt_reg[7]_2\,
O => \axlen_cnt_reg[0]\(0)
);
\axlen_cnt[3]_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"FF04"
)
port map (
I0 => \^q\(0),
I1 => si_rs_awvalid,
I2 => \^q\(1),
I3 => \^next\,
O => \axaddr_wrap_reg[11]\(0)
);
\axlen_cnt[7]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"0000FF04"
)
port map (
I0 => \^axlen_cnt_reg[7]_0\,
I1 => si_rs_awvalid,
I2 => \^axlen_cnt_reg[7]\,
I3 => \^next\,
I4 => \axlen_cnt_reg[7]_2\,
O => \axlen_cnt_reg[7]_1\
);
m_axi_awvalid_INST_0: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \^axlen_cnt_reg[7]_0\,
I1 => \^axlen_cnt_reg[7]\,
O => m_axi_awvalid
);
\m_payload_i[31]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"B"
)
port map (
I0 => \^b_push\,
I1 => si_rs_awvalid,
O => \m_payload_i_reg[0]\(0)
);
\memory_reg[3][0]_srl4_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"88008888A800A8A8"
)
port map (
I0 => \^axlen_cnt_reg[7]_0\,
I1 => \^axlen_cnt_reg[7]\,
I2 => m_axi_awready,
I3 => \cnt_read_reg[0]_rep__0\,
I4 => \cnt_read_reg[1]_rep__0\,
I5 => s_axburst_eq1_reg_0,
O => \^b_push\
);
next_pending_r_i_1: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFFF404"
)
port map (
I0 => \^e\(0),
I1 => next_pending_r_reg,
I2 => \^next\,
I3 => \axlen_cnt_reg[7]_2\,
I4 => \m_payload_i_reg[47]\,
O => \^incr_next_pending\
);
next_pending_r_i_2: unisim.vcomponents.LUT6
generic map(
INIT => X"F3F3FFFF51000000"
)
port map (
I0 => s_axburst_eq1_reg_0,
I1 => \cnt_read_reg[1]_rep__0\,
I2 => \cnt_read_reg[0]_rep__0\,
I3 => m_axi_awready,
I4 => \^axlen_cnt_reg[7]_0\,
I5 => \^axlen_cnt_reg[7]\,
O => \^next\
);
s_axburst_eq0_i_1: unisim.vcomponents.LUT4
generic map(
INIT => X"BA8A"
)
port map (
I0 => \^incr_next_pending\,
I1 => \^sel_first_i\,
I2 => \m_payload_i_reg[46]\(0),
I3 => wrap_next_pending,
O => s_axburst_eq0_reg
);
s_axburst_eq1_i_1: unisim.vcomponents.LUT4
generic map(
INIT => X"FE02"
)
port map (
I0 => \^incr_next_pending\,
I1 => \m_payload_i_reg[46]\(0),
I2 => \^sel_first_i\,
I3 => wrap_next_pending,
O => s_axburst_eq1_reg
);
sel_first_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFF44444F44"
)
port map (
I0 => \^next\,
I1 => sel_first,
I2 => \^q\(1),
I3 => si_rs_awvalid,
I4 => \^q\(0),
I5 => areset_d1,
O => sel_first_reg
);
\sel_first_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFF44444F44"
)
port map (
I0 => \^next\,
I1 => sel_first_0,
I2 => \^q\(1),
I3 => si_rs_awvalid,
I4 => \^q\(0),
I5 => areset_d1,
O => sel_first_reg_0
);
\sel_first_i_1__1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FF04FFFFFF04FF04"
)
port map (
I0 => \^axlen_cnt_reg[7]\,
I1 => si_rs_awvalid,
I2 => \^axlen_cnt_reg[7]_0\,
I3 => areset_d1,
I4 => \^next\,
I5 => sel_first_reg_1,
O => \^sel_first_i\
);
\state[0]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"BBBA"
)
port map (
I0 => \state[0]_i_2_n_0\,
I1 => \^q\(0),
I2 => si_rs_awvalid,
I3 => \^q\(1),
O => \state[0]_i_1_n_0\
);
\state[0]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"00F000F055750000"
)
port map (
I0 => m_axi_awready,
I1 => s_axburst_eq1_reg_0,
I2 => \cnt_read_reg[1]_rep__0\,
I3 => \cnt_read_reg[0]_rep__0\,
I4 => \^axlen_cnt_reg[7]_0\,
I5 => \^axlen_cnt_reg[7]\,
O => \state[0]_i_2_n_0\
);
\state[1]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"0C0CAE0000000000"
)
port map (
I0 => s_axburst_eq1_reg_0,
I1 => \cnt_read_reg[1]_rep__0\,
I2 => \cnt_read_reg[0]_rep__0\,
I3 => m_axi_awready,
I4 => \^axlen_cnt_reg[7]\,
I5 => \^axlen_cnt_reg[7]_0\,
O => \state[1]_i_1__0_n_0\
);
\state_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => \state[0]_i_1_n_0\,
Q => \^q\(0),
R => areset_d1
);
\state_reg[0]_rep\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => \state[0]_i_1_n_0\,
Q => \^axlen_cnt_reg[7]_0\,
R => areset_d1
);
\state_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => \state[1]_i_1__0_n_0\,
Q => \^q\(1),
R => areset_d1
);
\state_reg[1]_rep\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => \state[1]_i_1__0_n_0\,
Q => \^axlen_cnt_reg[7]\,
R => areset_d1
);
\wrap_boundary_axaddr_r[11]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"04"
)
port map (
I0 => \^axlen_cnt_reg[7]\,
I1 => si_rs_awvalid,
I2 => \^axlen_cnt_reg[7]_0\,
O => \^e\(0)
);
\wrap_cnt_r[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AA8A5575AA8A5545"
)
port map (
I0 => \wrap_second_len_r_reg[0]_0\(0),
I1 => \^q\(0),
I2 => si_rs_awvalid,
I3 => \^q\(1),
I4 => \axaddr_offset_r_reg[3]\,
I5 => axaddr_offset(0),
O => D(0)
);
\wrap_cnt_r[3]_i_4\: unisim.vcomponents.LUT4
generic map(
INIT => X"AA8A"
)
port map (
I0 => \axaddr_offset_r_reg[3]_0\(1),
I1 => \^axlen_cnt_reg[7]_0\,
I2 => si_rs_awvalid,
I3 => \^axlen_cnt_reg[7]\,
O => \wrap_cnt_r_reg[3]\
);
\wrap_cnt_r[3]_i_6\: unisim.vcomponents.LUT4
generic map(
INIT => X"AA8A"
)
port map (
I0 => \axaddr_offset_r_reg[3]_0\(0),
I1 => \^axlen_cnt_reg[7]_0\,
I2 => si_rs_awvalid,
I3 => \^axlen_cnt_reg[7]\,
O => \wrap_cnt_r_reg[3]_0\
);
\wrap_second_len_r[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AA8AAA8AAA8AAABA"
)
port map (
I0 => \wrap_second_len_r_reg[0]_0\(0),
I1 => \^q\(0),
I2 => si_rs_awvalid,
I3 => \^q\(1),
I4 => \axaddr_offset_r_reg[3]\,
I5 => axaddr_offset(0),
O => \wrap_second_len_r_reg[0]\(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity zybo_zynq_design_auto_pc_0_axi_protocol_converter_v2_1_17_b2s_wrap_cmd is
port (
wrap_next_pending : out STD_LOGIC;
sel_first_reg_0 : out STD_LOGIC;
\wrap_cnt_r_reg[3]_0\ : out STD_LOGIC;
\wrap_second_len_r_reg[3]_0\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awaddr : out STD_LOGIC_VECTOR ( 11 downto 0 );
\axaddr_offset_r_reg[3]_0\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
aclk : in STD_LOGIC;
sel_first_reg_1 : in STD_LOGIC;
E : in STD_LOGIC_VECTOR ( 0 to 0 );
\m_payload_i_reg[47]\ : in STD_LOGIC_VECTOR ( 18 downto 0 );
\state_reg[1]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
si_rs_awvalid : in STD_LOGIC;
\axaddr_offset_r_reg[3]_1\ : in STD_LOGIC;
D : in STD_LOGIC_VECTOR ( 3 downto 0 );
\m_payload_i_reg[47]_0\ : in STD_LOGIC;
\next\ : in STD_LOGIC;
sel_first_reg_2 : in STD_LOGIC;
\axaddr_incr_reg[11]\ : in STD_LOGIC_VECTOR ( 10 downto 0 );
sel_first_reg_3 : in STD_LOGIC;
\axaddr_offset_r_reg[3]_2\ : in STD_LOGIC;
\wrap_second_len_r_reg[3]_1\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\state_reg[0]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\wrap_second_len_r_reg[3]_2\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
\m_payload_i_reg[6]\ : in STD_LOGIC_VECTOR ( 6 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of zybo_zynq_design_auto_pc_0_axi_protocol_converter_v2_1_17_b2s_wrap_cmd : entity is "axi_protocol_converter_v2_1_17_b2s_wrap_cmd";
end zybo_zynq_design_auto_pc_0_axi_protocol_converter_v2_1_17_b2s_wrap_cmd;
architecture STRUCTURE of zybo_zynq_design_auto_pc_0_axi_protocol_converter_v2_1_17_b2s_wrap_cmd is
signal axaddr_wrap : STD_LOGIC_VECTOR ( 11 downto 0 );
signal axaddr_wrap0 : STD_LOGIC_VECTOR ( 11 downto 0 );
signal \axaddr_wrap[0]_i_1_n_0\ : STD_LOGIC;
signal \axaddr_wrap[10]_i_1_n_0\ : STD_LOGIC;
signal \axaddr_wrap[11]_i_1_n_0\ : STD_LOGIC;
signal \axaddr_wrap[11]_i_2_n_0\ : STD_LOGIC;
signal \axaddr_wrap[11]_i_4_n_0\ : STD_LOGIC;
signal \axaddr_wrap[1]_i_1_n_0\ : STD_LOGIC;
signal \axaddr_wrap[2]_i_1_n_0\ : STD_LOGIC;
signal \axaddr_wrap[3]_i_1_n_0\ : STD_LOGIC;
signal \axaddr_wrap[3]_i_3_n_0\ : STD_LOGIC;
signal \axaddr_wrap[3]_i_4_n_0\ : STD_LOGIC;
signal \axaddr_wrap[3]_i_5_n_0\ : STD_LOGIC;
signal \axaddr_wrap[3]_i_6_n_0\ : STD_LOGIC;
signal \axaddr_wrap[4]_i_1_n_0\ : STD_LOGIC;
signal \axaddr_wrap[5]_i_1_n_0\ : STD_LOGIC;
signal \axaddr_wrap[6]_i_1_n_0\ : STD_LOGIC;
signal \axaddr_wrap[7]_i_1_n_0\ : STD_LOGIC;
signal \axaddr_wrap[8]_i_1_n_0\ : STD_LOGIC;
signal \axaddr_wrap[9]_i_1_n_0\ : STD_LOGIC;
signal \axaddr_wrap_reg[11]_i_3_n_1\ : STD_LOGIC;
signal \axaddr_wrap_reg[11]_i_3_n_2\ : STD_LOGIC;
signal \axaddr_wrap_reg[11]_i_3_n_3\ : STD_LOGIC;
signal \axaddr_wrap_reg[3]_i_2_n_0\ : STD_LOGIC;
signal \axaddr_wrap_reg[3]_i_2_n_1\ : STD_LOGIC;
signal \axaddr_wrap_reg[3]_i_2_n_2\ : STD_LOGIC;
signal \axaddr_wrap_reg[3]_i_2_n_3\ : STD_LOGIC;
signal \axaddr_wrap_reg[7]_i_2_n_0\ : STD_LOGIC;
signal \axaddr_wrap_reg[7]_i_2_n_1\ : STD_LOGIC;
signal \axaddr_wrap_reg[7]_i_2_n_2\ : STD_LOGIC;
signal \axaddr_wrap_reg[7]_i_2_n_3\ : STD_LOGIC;
signal \axlen_cnt[0]_i_1_n_0\ : STD_LOGIC;
signal \axlen_cnt[1]_i_1_n_0\ : STD_LOGIC;
signal \axlen_cnt[2]_i_1__0_n_0\ : STD_LOGIC;
signal \axlen_cnt[3]_i_1_n_0\ : STD_LOGIC;
signal \axlen_cnt_reg_n_0_[0]\ : STD_LOGIC;
signal \axlen_cnt_reg_n_0_[1]\ : STD_LOGIC;
signal \axlen_cnt_reg_n_0_[2]\ : STD_LOGIC;
signal \axlen_cnt_reg_n_0_[3]\ : STD_LOGIC;
signal \next_pending_r_i_2__1_n_0\ : STD_LOGIC;
signal next_pending_r_reg_n_0 : STD_LOGIC;
signal \^sel_first_reg_0\ : STD_LOGIC;
signal wrap_boundary_axaddr_r : STD_LOGIC_VECTOR ( 11 downto 0 );
signal wrap_cnt : STD_LOGIC_VECTOR ( 1 to 1 );
signal wrap_cnt_r : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \^wrap_next_pending\ : STD_LOGIC;
signal \^wrap_second_len_r_reg[3]_0\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_axaddr_wrap_reg[11]_i_3_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
begin
sel_first_reg_0 <= \^sel_first_reg_0\;
wrap_next_pending <= \^wrap_next_pending\;
\wrap_second_len_r_reg[3]_0\(3 downto 0) <= \^wrap_second_len_r_reg[3]_0\(3 downto 0);
\axaddr_offset_r_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => D(0),
Q => \axaddr_offset_r_reg[3]_0\(0),
R => '0'
);
\axaddr_offset_r_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => D(1),
Q => \axaddr_offset_r_reg[3]_0\(1),
R => '0'
);
\axaddr_offset_r_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => D(2),
Q => \axaddr_offset_r_reg[3]_0\(2),
R => '0'
);
\axaddr_offset_r_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => D(3),
Q => \axaddr_offset_r_reg[3]_0\(3),
R => '0'
);
\axaddr_wrap[0]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => wrap_boundary_axaddr_r(0),
I1 => \axaddr_wrap[11]_i_2_n_0\,
I2 => axaddr_wrap0(0),
I3 => \next\,
I4 => \m_payload_i_reg[47]\(0),
O => \axaddr_wrap[0]_i_1_n_0\
);
\axaddr_wrap[10]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => wrap_boundary_axaddr_r(10),
I1 => \axaddr_wrap[11]_i_2_n_0\,
I2 => axaddr_wrap0(10),
I3 => \next\,
I4 => \m_payload_i_reg[47]\(10),
O => \axaddr_wrap[10]_i_1_n_0\
);
\axaddr_wrap[11]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => wrap_boundary_axaddr_r(11),
I1 => \axaddr_wrap[11]_i_2_n_0\,
I2 => axaddr_wrap0(11),
I3 => \next\,
I4 => \m_payload_i_reg[47]\(11),
O => \axaddr_wrap[11]_i_1_n_0\
);
\axaddr_wrap[11]_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"41"
)
port map (
I0 => \axaddr_wrap[11]_i_4_n_0\,
I1 => wrap_cnt_r(3),
I2 => \axlen_cnt_reg_n_0_[3]\,
O => \axaddr_wrap[11]_i_2_n_0\
);
\axaddr_wrap[11]_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"6FF6FFFFFFFF6FF6"
)
port map (
I0 => wrap_cnt_r(0),
I1 => \axlen_cnt_reg_n_0_[0]\,
I2 => \axlen_cnt_reg_n_0_[1]\,
I3 => wrap_cnt_r(1),
I4 => \axlen_cnt_reg_n_0_[2]\,
I5 => wrap_cnt_r(2),
O => \axaddr_wrap[11]_i_4_n_0\
);
\axaddr_wrap[1]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => wrap_boundary_axaddr_r(1),
I1 => \axaddr_wrap[11]_i_2_n_0\,
I2 => axaddr_wrap0(1),
I3 => \next\,
I4 => \m_payload_i_reg[47]\(1),
O => \axaddr_wrap[1]_i_1_n_0\
);
\axaddr_wrap[2]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => wrap_boundary_axaddr_r(2),
I1 => \axaddr_wrap[11]_i_2_n_0\,
I2 => axaddr_wrap0(2),
I3 => \next\,
I4 => \m_payload_i_reg[47]\(2),
O => \axaddr_wrap[2]_i_1_n_0\
);
\axaddr_wrap[3]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => wrap_boundary_axaddr_r(3),
I1 => \axaddr_wrap[11]_i_2_n_0\,
I2 => axaddr_wrap0(3),
I3 => \next\,
I4 => \m_payload_i_reg[47]\(3),
O => \axaddr_wrap[3]_i_1_n_0\
);
\axaddr_wrap[3]_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"6A"
)
port map (
I0 => axaddr_wrap(3),
I1 => \m_payload_i_reg[47]\(12),
I2 => \m_payload_i_reg[47]\(13),
O => \axaddr_wrap[3]_i_3_n_0\
);
\axaddr_wrap[3]_i_4\: unisim.vcomponents.LUT3
generic map(
INIT => X"9A"
)
port map (
I0 => axaddr_wrap(2),
I1 => \m_payload_i_reg[47]\(12),
I2 => \m_payload_i_reg[47]\(13),
O => \axaddr_wrap[3]_i_4_n_0\
);
\axaddr_wrap[3]_i_5\: unisim.vcomponents.LUT3
generic map(
INIT => X"9A"
)
port map (
I0 => axaddr_wrap(1),
I1 => \m_payload_i_reg[47]\(13),
I2 => \m_payload_i_reg[47]\(12),
O => \axaddr_wrap[3]_i_5_n_0\
);
\axaddr_wrap[3]_i_6\: unisim.vcomponents.LUT3
generic map(
INIT => X"A9"
)
port map (
I0 => axaddr_wrap(0),
I1 => \m_payload_i_reg[47]\(12),
I2 => \m_payload_i_reg[47]\(13),
O => \axaddr_wrap[3]_i_6_n_0\
);
\axaddr_wrap[4]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => wrap_boundary_axaddr_r(4),
I1 => \axaddr_wrap[11]_i_2_n_0\,
I2 => axaddr_wrap0(4),
I3 => \next\,
I4 => \m_payload_i_reg[47]\(4),
O => \axaddr_wrap[4]_i_1_n_0\
);
\axaddr_wrap[5]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => wrap_boundary_axaddr_r(5),
I1 => \axaddr_wrap[11]_i_2_n_0\,
I2 => axaddr_wrap0(5),
I3 => \next\,
I4 => \m_payload_i_reg[47]\(5),
O => \axaddr_wrap[5]_i_1_n_0\
);
\axaddr_wrap[6]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => wrap_boundary_axaddr_r(6),
I1 => \axaddr_wrap[11]_i_2_n_0\,
I2 => axaddr_wrap0(6),
I3 => \next\,
I4 => \m_payload_i_reg[47]\(6),
O => \axaddr_wrap[6]_i_1_n_0\
);
\axaddr_wrap[7]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => wrap_boundary_axaddr_r(7),
I1 => \axaddr_wrap[11]_i_2_n_0\,
I2 => axaddr_wrap0(7),
I3 => \next\,
I4 => \m_payload_i_reg[47]\(7),
O => \axaddr_wrap[7]_i_1_n_0\
);
\axaddr_wrap[8]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => wrap_boundary_axaddr_r(8),
I1 => \axaddr_wrap[11]_i_2_n_0\,
I2 => axaddr_wrap0(8),
I3 => \next\,
I4 => \m_payload_i_reg[47]\(8),
O => \axaddr_wrap[8]_i_1_n_0\
);
\axaddr_wrap[9]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => wrap_boundary_axaddr_r(9),
I1 => \axaddr_wrap[11]_i_2_n_0\,
I2 => axaddr_wrap0(9),
I3 => \next\,
I4 => \m_payload_i_reg[47]\(9),
O => \axaddr_wrap[9]_i_1_n_0\
);
\axaddr_wrap_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \state_reg[0]\(0),
D => \axaddr_wrap[0]_i_1_n_0\,
Q => axaddr_wrap(0),
R => '0'
);
\axaddr_wrap_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \state_reg[0]\(0),
D => \axaddr_wrap[10]_i_1_n_0\,
Q => axaddr_wrap(10),
R => '0'
);
\axaddr_wrap_reg[11]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \state_reg[0]\(0),
D => \axaddr_wrap[11]_i_1_n_0\,
Q => axaddr_wrap(11),
R => '0'
);
\axaddr_wrap_reg[11]_i_3\: unisim.vcomponents.CARRY4
port map (
CI => \axaddr_wrap_reg[7]_i_2_n_0\,
CO(3) => \NLW_axaddr_wrap_reg[11]_i_3_CO_UNCONNECTED\(3),
CO(2) => \axaddr_wrap_reg[11]_i_3_n_1\,
CO(1) => \axaddr_wrap_reg[11]_i_3_n_2\,
CO(0) => \axaddr_wrap_reg[11]_i_3_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 0) => axaddr_wrap0(11 downto 8),
S(3 downto 0) => axaddr_wrap(11 downto 8)
);
\axaddr_wrap_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \state_reg[0]\(0),
D => \axaddr_wrap[1]_i_1_n_0\,
Q => axaddr_wrap(1),
R => '0'
);
\axaddr_wrap_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \state_reg[0]\(0),
D => \axaddr_wrap[2]_i_1_n_0\,
Q => axaddr_wrap(2),
R => '0'
);
\axaddr_wrap_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \state_reg[0]\(0),
D => \axaddr_wrap[3]_i_1_n_0\,
Q => axaddr_wrap(3),
R => '0'
);
\axaddr_wrap_reg[3]_i_2\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \axaddr_wrap_reg[3]_i_2_n_0\,
CO(2) => \axaddr_wrap_reg[3]_i_2_n_1\,
CO(1) => \axaddr_wrap_reg[3]_i_2_n_2\,
CO(0) => \axaddr_wrap_reg[3]_i_2_n_3\,
CYINIT => '0',
DI(3 downto 0) => axaddr_wrap(3 downto 0),
O(3 downto 0) => axaddr_wrap0(3 downto 0),
S(3) => \axaddr_wrap[3]_i_3_n_0\,
S(2) => \axaddr_wrap[3]_i_4_n_0\,
S(1) => \axaddr_wrap[3]_i_5_n_0\,
S(0) => \axaddr_wrap[3]_i_6_n_0\
);
\axaddr_wrap_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \state_reg[0]\(0),
D => \axaddr_wrap[4]_i_1_n_0\,
Q => axaddr_wrap(4),
R => '0'
);
\axaddr_wrap_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \state_reg[0]\(0),
D => \axaddr_wrap[5]_i_1_n_0\,
Q => axaddr_wrap(5),
R => '0'
);
\axaddr_wrap_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \state_reg[0]\(0),
D => \axaddr_wrap[6]_i_1_n_0\,
Q => axaddr_wrap(6),
R => '0'
);
\axaddr_wrap_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \state_reg[0]\(0),
D => \axaddr_wrap[7]_i_1_n_0\,
Q => axaddr_wrap(7),
R => '0'
);
\axaddr_wrap_reg[7]_i_2\: unisim.vcomponents.CARRY4
port map (
CI => \axaddr_wrap_reg[3]_i_2_n_0\,
CO(3) => \axaddr_wrap_reg[7]_i_2_n_0\,
CO(2) => \axaddr_wrap_reg[7]_i_2_n_1\,
CO(1) => \axaddr_wrap_reg[7]_i_2_n_2\,
CO(0) => \axaddr_wrap_reg[7]_i_2_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 0) => axaddr_wrap0(7 downto 4),
S(3 downto 0) => axaddr_wrap(7 downto 4)
);
\axaddr_wrap_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \state_reg[0]\(0),
D => \axaddr_wrap[8]_i_1_n_0\,
Q => axaddr_wrap(8),
R => '0'
);
\axaddr_wrap_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \state_reg[0]\(0),
D => \axaddr_wrap[9]_i_1_n_0\,
Q => axaddr_wrap(9),
R => '0'
);
\axlen_cnt[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"A3A3A3A3A3A3A3A0"
)
port map (
I0 => \m_payload_i_reg[47]\(15),
I1 => \axlen_cnt_reg_n_0_[0]\,
I2 => E(0),
I3 => \axlen_cnt_reg_n_0_[3]\,
I4 => \axlen_cnt_reg_n_0_[2]\,
I5 => \axlen_cnt_reg_n_0_[1]\,
O => \axlen_cnt[0]_i_1_n_0\
);
\axlen_cnt[1]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAC3AAC3AAC3AAC0"
)
port map (
I0 => \m_payload_i_reg[47]\(16),
I1 => \axlen_cnt_reg_n_0_[1]\,
I2 => \axlen_cnt_reg_n_0_[0]\,
I3 => E(0),
I4 => \axlen_cnt_reg_n_0_[3]\,
I5 => \axlen_cnt_reg_n_0_[2]\,
O => \axlen_cnt[1]_i_1_n_0\
);
\axlen_cnt[2]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFA9A80000A9A8"
)
port map (
I0 => \axlen_cnt_reg_n_0_[2]\,
I1 => \axlen_cnt_reg_n_0_[0]\,
I2 => \axlen_cnt_reg_n_0_[1]\,
I3 => \axlen_cnt_reg_n_0_[3]\,
I4 => E(0),
I5 => \m_payload_i_reg[47]\(17),
O => \axlen_cnt[2]_i_1__0_n_0\
);
\axlen_cnt[3]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAAAAAAACCCCCCC0"
)
port map (
I0 => \m_payload_i_reg[47]\(18),
I1 => \axlen_cnt_reg_n_0_[3]\,
I2 => \axlen_cnt_reg_n_0_[2]\,
I3 => \axlen_cnt_reg_n_0_[1]\,
I4 => \axlen_cnt_reg_n_0_[0]\,
I5 => E(0),
O => \axlen_cnt[3]_i_1_n_0\
);
\axlen_cnt_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \state_reg[0]\(0),
D => \axlen_cnt[0]_i_1_n_0\,
Q => \axlen_cnt_reg_n_0_[0]\,
R => '0'
);
\axlen_cnt_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \state_reg[0]\(0),
D => \axlen_cnt[1]_i_1_n_0\,
Q => \axlen_cnt_reg_n_0_[1]\,
R => '0'
);
\axlen_cnt_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \state_reg[0]\(0),
D => \axlen_cnt[2]_i_1__0_n_0\,
Q => \axlen_cnt_reg_n_0_[2]\,
R => '0'
);
\axlen_cnt_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \state_reg[0]\(0),
D => \axlen_cnt[3]_i_1_n_0\,
Q => \axlen_cnt_reg_n_0_[3]\,
R => '0'
);
\m_axi_awaddr[0]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"EF40EF4FEF40E040"
)
port map (
I0 => \^sel_first_reg_0\,
I1 => axaddr_wrap(0),
I2 => \m_payload_i_reg[47]\(14),
I3 => \m_payload_i_reg[47]\(0),
I4 => sel_first_reg_2,
I5 => \axaddr_incr_reg[11]\(0),
O => m_axi_awaddr(0)
);
\m_axi_awaddr[10]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"EF40EF4FEF40E040"
)
port map (
I0 => \^sel_first_reg_0\,
I1 => axaddr_wrap(10),
I2 => \m_payload_i_reg[47]\(14),
I3 => \m_payload_i_reg[47]\(10),
I4 => sel_first_reg_2,
I5 => \axaddr_incr_reg[11]\(9),
O => m_axi_awaddr(10)
);
\m_axi_awaddr[11]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"EF40EF4FEF40E040"
)
port map (
I0 => \^sel_first_reg_0\,
I1 => axaddr_wrap(11),
I2 => \m_payload_i_reg[47]\(14),
I3 => \m_payload_i_reg[47]\(11),
I4 => sel_first_reg_2,
I5 => \axaddr_incr_reg[11]\(10),
O => m_axi_awaddr(11)
);
\m_axi_awaddr[1]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"EF40EF4FEF40E040"
)
port map (
I0 => \^sel_first_reg_0\,
I1 => axaddr_wrap(1),
I2 => \m_payload_i_reg[47]\(14),
I3 => \m_payload_i_reg[47]\(1),
I4 => sel_first_reg_2,
I5 => \axaddr_incr_reg[11]\(1),
O => m_axi_awaddr(1)
);
\m_axi_awaddr[2]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"EF40EF4FEF40E040"
)
port map (
I0 => \^sel_first_reg_0\,
I1 => axaddr_wrap(2),
I2 => \m_payload_i_reg[47]\(14),
I3 => \m_payload_i_reg[47]\(2),
I4 => sel_first_reg_2,
I5 => \axaddr_incr_reg[11]\(2),
O => m_axi_awaddr(2)
);
\m_axi_awaddr[3]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"EF40EF4FEF40E040"
)
port map (
I0 => \^sel_first_reg_0\,
I1 => axaddr_wrap(3),
I2 => \m_payload_i_reg[47]\(14),
I3 => \m_payload_i_reg[47]\(3),
I4 => sel_first_reg_2,
I5 => \axaddr_incr_reg[11]\(3),
O => m_axi_awaddr(3)
);
\m_axi_awaddr[4]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"EF40EF4FEF40E040"
)
port map (
I0 => \^sel_first_reg_0\,
I1 => axaddr_wrap(4),
I2 => \m_payload_i_reg[47]\(14),
I3 => \m_payload_i_reg[47]\(4),
I4 => sel_first_reg_2,
I5 => \axaddr_incr_reg[11]\(4),
O => m_axi_awaddr(4)
);
\m_axi_awaddr[5]_INST_0\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => \m_payload_i_reg[47]\(5),
I1 => \^sel_first_reg_0\,
I2 => axaddr_wrap(5),
I3 => \m_payload_i_reg[47]\(14),
I4 => sel_first_reg_3,
O => m_axi_awaddr(5)
);
\m_axi_awaddr[6]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"EF40EF4FEF40E040"
)
port map (
I0 => \^sel_first_reg_0\,
I1 => axaddr_wrap(6),
I2 => \m_payload_i_reg[47]\(14),
I3 => \m_payload_i_reg[47]\(6),
I4 => sel_first_reg_2,
I5 => \axaddr_incr_reg[11]\(5),
O => m_axi_awaddr(6)
);
\m_axi_awaddr[7]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"EF40EF4FEF40E040"
)
port map (
I0 => \^sel_first_reg_0\,
I1 => axaddr_wrap(7),
I2 => \m_payload_i_reg[47]\(14),
I3 => \m_payload_i_reg[47]\(7),
I4 => sel_first_reg_2,
I5 => \axaddr_incr_reg[11]\(6),
O => m_axi_awaddr(7)
);
\m_axi_awaddr[8]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"EF40EF4FEF40E040"
)
port map (
I0 => \^sel_first_reg_0\,
I1 => axaddr_wrap(8),
I2 => \m_payload_i_reg[47]\(14),
I3 => \m_payload_i_reg[47]\(8),
I4 => sel_first_reg_2,
I5 => \axaddr_incr_reg[11]\(7),
O => m_axi_awaddr(8)
);
\m_axi_awaddr[9]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"EF40EF4FEF40E040"
)
port map (
I0 => \^sel_first_reg_0\,
I1 => axaddr_wrap(9),
I2 => \m_payload_i_reg[47]\(14),
I3 => \m_payload_i_reg[47]\(9),
I4 => sel_first_reg_2,
I5 => \axaddr_incr_reg[11]\(8),
O => m_axi_awaddr(9)
);
\next_pending_r_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"FEAAFEAE"
)
port map (
I0 => \m_payload_i_reg[47]_0\,
I1 => next_pending_r_reg_n_0,
I2 => \next\,
I3 => \next_pending_r_i_2__1_n_0\,
I4 => E(0),
O => \^wrap_next_pending\
);
\next_pending_r_i_2__1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FBFBFBFBFBFBFB00"
)
port map (
I0 => \state_reg[1]\(0),
I1 => si_rs_awvalid,
I2 => \state_reg[1]\(1),
I3 => \axlen_cnt_reg_n_0_[3]\,
I4 => \axlen_cnt_reg_n_0_[2]\,
I5 => \axlen_cnt_reg_n_0_[1]\,
O => \next_pending_r_i_2__1_n_0\
);
next_pending_r_reg: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \^wrap_next_pending\,
Q => next_pending_r_reg_n_0,
R => '0'
);
sel_first_reg: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => sel_first_reg_1,
Q => \^sel_first_reg_0\,
R => '0'
);
\wrap_boundary_axaddr_r_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \m_payload_i_reg[6]\(0),
Q => wrap_boundary_axaddr_r(0),
R => '0'
);
\wrap_boundary_axaddr_r_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \m_payload_i_reg[47]\(10),
Q => wrap_boundary_axaddr_r(10),
R => '0'
);
\wrap_boundary_axaddr_r_reg[11]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \m_payload_i_reg[47]\(11),
Q => wrap_boundary_axaddr_r(11),
R => '0'
);
\wrap_boundary_axaddr_r_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \m_payload_i_reg[6]\(1),
Q => wrap_boundary_axaddr_r(1),
R => '0'
);
\wrap_boundary_axaddr_r_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \m_payload_i_reg[6]\(2),
Q => wrap_boundary_axaddr_r(2),
R => '0'
);
\wrap_boundary_axaddr_r_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \m_payload_i_reg[6]\(3),
Q => wrap_boundary_axaddr_r(3),
R => '0'
);
\wrap_boundary_axaddr_r_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \m_payload_i_reg[6]\(4),
Q => wrap_boundary_axaddr_r(4),
R => '0'
);
\wrap_boundary_axaddr_r_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \m_payload_i_reg[6]\(5),
Q => wrap_boundary_axaddr_r(5),
R => '0'
);
\wrap_boundary_axaddr_r_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \m_payload_i_reg[6]\(6),
Q => wrap_boundary_axaddr_r(6),
R => '0'
);
\wrap_boundary_axaddr_r_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \m_payload_i_reg[47]\(7),
Q => wrap_boundary_axaddr_r(7),
R => '0'
);
\wrap_boundary_axaddr_r_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \m_payload_i_reg[47]\(8),
Q => wrap_boundary_axaddr_r(8),
R => '0'
);
\wrap_boundary_axaddr_r_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \m_payload_i_reg[47]\(9),
Q => wrap_boundary_axaddr_r(9),
R => '0'
);
\wrap_cnt_r[1]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"3D310E02"
)
port map (
I0 => \^wrap_second_len_r_reg[3]_0\(0),
I1 => E(0),
I2 => \axaddr_offset_r_reg[3]_2\,
I3 => D(1),
I4 => \^wrap_second_len_r_reg[3]_0\(1),
O => wrap_cnt(1)
);
\wrap_cnt_r[3]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"000CAAA8000C0000"
)
port map (
I0 => \^wrap_second_len_r_reg[3]_0\(1),
I1 => \axaddr_offset_r_reg[3]_1\,
I2 => D(1),
I3 => D(0),
I4 => E(0),
I5 => \^wrap_second_len_r_reg[3]_0\(0),
O => \wrap_cnt_r_reg[3]_0\
);
\wrap_cnt_r_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \wrap_second_len_r_reg[3]_2\(0),
Q => wrap_cnt_r(0),
R => '0'
);
\wrap_cnt_r_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => wrap_cnt(1),
Q => wrap_cnt_r(1),
R => '0'
);
\wrap_cnt_r_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \wrap_second_len_r_reg[3]_2\(1),
Q => wrap_cnt_r(2),
R => '0'
);
\wrap_cnt_r_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \wrap_second_len_r_reg[3]_2\(2),
Q => wrap_cnt_r(3),
R => '0'
);
\wrap_second_len_r_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \wrap_second_len_r_reg[3]_1\(0),
Q => \^wrap_second_len_r_reg[3]_0\(0),
R => '0'
);
\wrap_second_len_r_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \wrap_second_len_r_reg[3]_1\(1),
Q => \^wrap_second_len_r_reg[3]_0\(1),
R => '0'
);
\wrap_second_len_r_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \wrap_second_len_r_reg[3]_1\(2),
Q => \^wrap_second_len_r_reg[3]_0\(2),
R => '0'
);
\wrap_second_len_r_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \wrap_second_len_r_reg[3]_1\(3),
Q => \^wrap_second_len_r_reg[3]_0\(3),
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity zybo_zynq_design_auto_pc_0_axi_protocol_converter_v2_1_17_b2s_wrap_cmd_3 is
port (
sel_first_reg_0 : out STD_LOGIC;
\wrap_cnt_r_reg[3]_0\ : out STD_LOGIC;
\wrap_second_len_r_reg[3]_0\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
s_axburst_eq0_reg : out STD_LOGIC;
s_axburst_eq1_reg : out STD_LOGIC;
m_axi_araddr : out STD_LOGIC_VECTOR ( 11 downto 0 );
\axaddr_offset_r_reg[3]_0\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
aclk : in STD_LOGIC;
sel_first_reg_1 : in STD_LOGIC;
E : in STD_LOGIC_VECTOR ( 0 to 0 );
Q : in STD_LOGIC_VECTOR ( 18 downto 0 );
\state_reg[1]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
si_rs_arvalid : in STD_LOGIC;
\axaddr_offset_r_reg[3]_1\ : in STD_LOGIC;
D : in STD_LOGIC_VECTOR ( 3 downto 0 );
sel_first_i : in STD_LOGIC;
incr_next_pending : in STD_LOGIC;
\m_payload_i_reg[47]\ : in STD_LOGIC;
\state_reg[1]_rep\ : in STD_LOGIC;
sel_first_reg_2 : in STD_LOGIC;
\axaddr_incr_reg[11]\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
sel_first_reg_3 : in STD_LOGIC;
sel_first_reg_4 : in STD_LOGIC;
sel_first_reg_5 : in STD_LOGIC;
sel_first_reg_6 : in STD_LOGIC;
\axaddr_offset_r_reg[3]_2\ : in STD_LOGIC;
\wrap_second_len_r_reg[3]_1\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
m_valid_i_reg : in STD_LOGIC_VECTOR ( 0 to 0 );
\wrap_second_len_r_reg[3]_2\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
\m_payload_i_reg[6]\ : in STD_LOGIC_VECTOR ( 6 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of zybo_zynq_design_auto_pc_0_axi_protocol_converter_v2_1_17_b2s_wrap_cmd_3 : entity is "axi_protocol_converter_v2_1_17_b2s_wrap_cmd";
end zybo_zynq_design_auto_pc_0_axi_protocol_converter_v2_1_17_b2s_wrap_cmd_3;
architecture STRUCTURE of zybo_zynq_design_auto_pc_0_axi_protocol_converter_v2_1_17_b2s_wrap_cmd_3 is
signal \axaddr_wrap[0]_i_1__0_n_0\ : STD_LOGIC;
signal \axaddr_wrap[10]_i_1__0_n_0\ : STD_LOGIC;
signal \axaddr_wrap[11]_i_1__0_n_0\ : STD_LOGIC;
signal \axaddr_wrap[11]_i_2__0_n_0\ : STD_LOGIC;
signal \axaddr_wrap[11]_i_4__0_n_0\ : STD_LOGIC;
signal \axaddr_wrap[1]_i_1__0_n_0\ : STD_LOGIC;
signal \axaddr_wrap[2]_i_1__0_n_0\ : STD_LOGIC;
signal \axaddr_wrap[3]_i_1__0_n_0\ : STD_LOGIC;
signal \axaddr_wrap[3]_i_3_n_0\ : STD_LOGIC;
signal \axaddr_wrap[3]_i_4_n_0\ : STD_LOGIC;
signal \axaddr_wrap[3]_i_5_n_0\ : STD_LOGIC;
signal \axaddr_wrap[3]_i_6_n_0\ : STD_LOGIC;
signal \axaddr_wrap[4]_i_1__0_n_0\ : STD_LOGIC;
signal \axaddr_wrap[5]_i_1__0_n_0\ : STD_LOGIC;
signal \axaddr_wrap[6]_i_1__0_n_0\ : STD_LOGIC;
signal \axaddr_wrap[7]_i_1__0_n_0\ : STD_LOGIC;
signal \axaddr_wrap[8]_i_1__0_n_0\ : STD_LOGIC;
signal \axaddr_wrap[9]_i_1__0_n_0\ : STD_LOGIC;
signal \axaddr_wrap_reg[11]_i_3__0_n_1\ : STD_LOGIC;
signal \axaddr_wrap_reg[11]_i_3__0_n_2\ : STD_LOGIC;
signal \axaddr_wrap_reg[11]_i_3__0_n_3\ : STD_LOGIC;
signal \axaddr_wrap_reg[11]_i_3__0_n_4\ : STD_LOGIC;
signal \axaddr_wrap_reg[11]_i_3__0_n_5\ : STD_LOGIC;
signal \axaddr_wrap_reg[11]_i_3__0_n_6\ : STD_LOGIC;
signal \axaddr_wrap_reg[11]_i_3__0_n_7\ : STD_LOGIC;
signal \axaddr_wrap_reg[3]_i_2__0_n_0\ : STD_LOGIC;
signal \axaddr_wrap_reg[3]_i_2__0_n_1\ : STD_LOGIC;
signal \axaddr_wrap_reg[3]_i_2__0_n_2\ : STD_LOGIC;
signal \axaddr_wrap_reg[3]_i_2__0_n_3\ : STD_LOGIC;
signal \axaddr_wrap_reg[3]_i_2__0_n_4\ : STD_LOGIC;
signal \axaddr_wrap_reg[3]_i_2__0_n_5\ : STD_LOGIC;
signal \axaddr_wrap_reg[3]_i_2__0_n_6\ : STD_LOGIC;
signal \axaddr_wrap_reg[3]_i_2__0_n_7\ : STD_LOGIC;
signal \axaddr_wrap_reg[7]_i_2__0_n_0\ : STD_LOGIC;
signal \axaddr_wrap_reg[7]_i_2__0_n_1\ : STD_LOGIC;
signal \axaddr_wrap_reg[7]_i_2__0_n_2\ : STD_LOGIC;
signal \axaddr_wrap_reg[7]_i_2__0_n_3\ : STD_LOGIC;
signal \axaddr_wrap_reg[7]_i_2__0_n_4\ : STD_LOGIC;
signal \axaddr_wrap_reg[7]_i_2__0_n_5\ : STD_LOGIC;
signal \axaddr_wrap_reg[7]_i_2__0_n_6\ : STD_LOGIC;
signal \axaddr_wrap_reg[7]_i_2__0_n_7\ : STD_LOGIC;
signal \axaddr_wrap_reg_n_0_[0]\ : STD_LOGIC;
signal \axaddr_wrap_reg_n_0_[10]\ : STD_LOGIC;
signal \axaddr_wrap_reg_n_0_[11]\ : STD_LOGIC;
signal \axaddr_wrap_reg_n_0_[1]\ : STD_LOGIC;
signal \axaddr_wrap_reg_n_0_[2]\ : STD_LOGIC;
signal \axaddr_wrap_reg_n_0_[3]\ : STD_LOGIC;
signal \axaddr_wrap_reg_n_0_[4]\ : STD_LOGIC;
signal \axaddr_wrap_reg_n_0_[5]\ : STD_LOGIC;
signal \axaddr_wrap_reg_n_0_[6]\ : STD_LOGIC;
signal \axaddr_wrap_reg_n_0_[7]\ : STD_LOGIC;
signal \axaddr_wrap_reg_n_0_[8]\ : STD_LOGIC;
signal \axaddr_wrap_reg_n_0_[9]\ : STD_LOGIC;
signal \axlen_cnt[0]_i_1__1_n_0\ : STD_LOGIC;
signal \axlen_cnt[1]_i_1__2_n_0\ : STD_LOGIC;
signal \axlen_cnt[2]_i_1__2_n_0\ : STD_LOGIC;
signal \axlen_cnt[3]_i_1__1_n_0\ : STD_LOGIC;
signal \axlen_cnt_reg_n_0_[0]\ : STD_LOGIC;
signal \axlen_cnt_reg_n_0_[1]\ : STD_LOGIC;
signal \axlen_cnt_reg_n_0_[2]\ : STD_LOGIC;
signal \axlen_cnt_reg_n_0_[3]\ : STD_LOGIC;
signal \next_pending_r_i_2__2_n_0\ : STD_LOGIC;
signal next_pending_r_reg_n_0 : STD_LOGIC;
signal \^sel_first_reg_0\ : STD_LOGIC;
signal \wrap_boundary_axaddr_r_reg_n_0_[0]\ : STD_LOGIC;
signal \wrap_boundary_axaddr_r_reg_n_0_[10]\ : STD_LOGIC;
signal \wrap_boundary_axaddr_r_reg_n_0_[11]\ : STD_LOGIC;
signal \wrap_boundary_axaddr_r_reg_n_0_[1]\ : STD_LOGIC;
signal \wrap_boundary_axaddr_r_reg_n_0_[2]\ : STD_LOGIC;
signal \wrap_boundary_axaddr_r_reg_n_0_[3]\ : STD_LOGIC;
signal \wrap_boundary_axaddr_r_reg_n_0_[4]\ : STD_LOGIC;
signal \wrap_boundary_axaddr_r_reg_n_0_[5]\ : STD_LOGIC;
signal \wrap_boundary_axaddr_r_reg_n_0_[6]\ : STD_LOGIC;
signal \wrap_boundary_axaddr_r_reg_n_0_[7]\ : STD_LOGIC;
signal \wrap_boundary_axaddr_r_reg_n_0_[8]\ : STD_LOGIC;
signal \wrap_boundary_axaddr_r_reg_n_0_[9]\ : STD_LOGIC;
signal \wrap_cnt_r[1]_i_1__0_n_0\ : STD_LOGIC;
signal \wrap_cnt_r_reg_n_0_[0]\ : STD_LOGIC;
signal \wrap_cnt_r_reg_n_0_[1]\ : STD_LOGIC;
signal \wrap_cnt_r_reg_n_0_[2]\ : STD_LOGIC;
signal \wrap_cnt_r_reg_n_0_[3]\ : STD_LOGIC;
signal wrap_next_pending : STD_LOGIC;
signal \^wrap_second_len_r_reg[3]_0\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_axaddr_wrap_reg[11]_i_3__0_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \s_axburst_eq0_i_1__0\ : label is "soft_lutpair16";
attribute SOFT_HLUTNM of \s_axburst_eq1_i_1__0\ : label is "soft_lutpair16";
begin
sel_first_reg_0 <= \^sel_first_reg_0\;
\wrap_second_len_r_reg[3]_0\(3 downto 0) <= \^wrap_second_len_r_reg[3]_0\(3 downto 0);
\axaddr_offset_r_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => D(0),
Q => \axaddr_offset_r_reg[3]_0\(0),
R => '0'
);
\axaddr_offset_r_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => D(1),
Q => \axaddr_offset_r_reg[3]_0\(1),
R => '0'
);
\axaddr_offset_r_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => D(2),
Q => \axaddr_offset_r_reg[3]_0\(2),
R => '0'
);
\axaddr_offset_r_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => D(3),
Q => \axaddr_offset_r_reg[3]_0\(3),
R => '0'
);
\axaddr_wrap[0]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => \wrap_boundary_axaddr_r_reg_n_0_[0]\,
I1 => \axaddr_wrap[11]_i_2__0_n_0\,
I2 => \axaddr_wrap_reg[3]_i_2__0_n_7\,
I3 => \state_reg[1]_rep\,
I4 => Q(0),
O => \axaddr_wrap[0]_i_1__0_n_0\
);
\axaddr_wrap[10]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => \wrap_boundary_axaddr_r_reg_n_0_[10]\,
I1 => \axaddr_wrap[11]_i_2__0_n_0\,
I2 => \axaddr_wrap_reg[11]_i_3__0_n_5\,
I3 => \state_reg[1]_rep\,
I4 => Q(10),
O => \axaddr_wrap[10]_i_1__0_n_0\
);
\axaddr_wrap[11]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => \wrap_boundary_axaddr_r_reg_n_0_[11]\,
I1 => \axaddr_wrap[11]_i_2__0_n_0\,
I2 => \axaddr_wrap_reg[11]_i_3__0_n_4\,
I3 => \state_reg[1]_rep\,
I4 => Q(11),
O => \axaddr_wrap[11]_i_1__0_n_0\
);
\axaddr_wrap[11]_i_2__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"41"
)
port map (
I0 => \axaddr_wrap[11]_i_4__0_n_0\,
I1 => \wrap_cnt_r_reg_n_0_[3]\,
I2 => \axlen_cnt_reg_n_0_[3]\,
O => \axaddr_wrap[11]_i_2__0_n_0\
);
\axaddr_wrap[11]_i_4__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"6FF6FFFFFFFF6FF6"
)
port map (
I0 => \wrap_cnt_r_reg_n_0_[0]\,
I1 => \axlen_cnt_reg_n_0_[0]\,
I2 => \axlen_cnt_reg_n_0_[2]\,
I3 => \wrap_cnt_r_reg_n_0_[2]\,
I4 => \axlen_cnt_reg_n_0_[1]\,
I5 => \wrap_cnt_r_reg_n_0_[1]\,
O => \axaddr_wrap[11]_i_4__0_n_0\
);
\axaddr_wrap[1]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => \wrap_boundary_axaddr_r_reg_n_0_[1]\,
I1 => \axaddr_wrap[11]_i_2__0_n_0\,
I2 => \axaddr_wrap_reg[3]_i_2__0_n_6\,
I3 => \state_reg[1]_rep\,
I4 => Q(1),
O => \axaddr_wrap[1]_i_1__0_n_0\
);
\axaddr_wrap[2]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => \wrap_boundary_axaddr_r_reg_n_0_[2]\,
I1 => \axaddr_wrap[11]_i_2__0_n_0\,
I2 => \axaddr_wrap_reg[3]_i_2__0_n_5\,
I3 => \state_reg[1]_rep\,
I4 => Q(2),
O => \axaddr_wrap[2]_i_1__0_n_0\
);
\axaddr_wrap[3]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => \wrap_boundary_axaddr_r_reg_n_0_[3]\,
I1 => \axaddr_wrap[11]_i_2__0_n_0\,
I2 => \axaddr_wrap_reg[3]_i_2__0_n_4\,
I3 => \state_reg[1]_rep\,
I4 => Q(3),
O => \axaddr_wrap[3]_i_1__0_n_0\
);
\axaddr_wrap[3]_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"6A"
)
port map (
I0 => \axaddr_wrap_reg_n_0_[3]\,
I1 => Q(12),
I2 => Q(13),
O => \axaddr_wrap[3]_i_3_n_0\
);
\axaddr_wrap[3]_i_4\: unisim.vcomponents.LUT3
generic map(
INIT => X"9A"
)
port map (
I0 => \axaddr_wrap_reg_n_0_[2]\,
I1 => Q(12),
I2 => Q(13),
O => \axaddr_wrap[3]_i_4_n_0\
);
\axaddr_wrap[3]_i_5\: unisim.vcomponents.LUT3
generic map(
INIT => X"9A"
)
port map (
I0 => \axaddr_wrap_reg_n_0_[1]\,
I1 => Q(13),
I2 => Q(12),
O => \axaddr_wrap[3]_i_5_n_0\
);
\axaddr_wrap[3]_i_6\: unisim.vcomponents.LUT3
generic map(
INIT => X"A9"
)
port map (
I0 => \axaddr_wrap_reg_n_0_[0]\,
I1 => Q(12),
I2 => Q(13),
O => \axaddr_wrap[3]_i_6_n_0\
);
\axaddr_wrap[4]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => \wrap_boundary_axaddr_r_reg_n_0_[4]\,
I1 => \axaddr_wrap[11]_i_2__0_n_0\,
I2 => \axaddr_wrap_reg[7]_i_2__0_n_7\,
I3 => \state_reg[1]_rep\,
I4 => Q(4),
O => \axaddr_wrap[4]_i_1__0_n_0\
);
\axaddr_wrap[5]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => \wrap_boundary_axaddr_r_reg_n_0_[5]\,
I1 => \axaddr_wrap[11]_i_2__0_n_0\,
I2 => \axaddr_wrap_reg[7]_i_2__0_n_6\,
I3 => \state_reg[1]_rep\,
I4 => Q(5),
O => \axaddr_wrap[5]_i_1__0_n_0\
);
\axaddr_wrap[6]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => \wrap_boundary_axaddr_r_reg_n_0_[6]\,
I1 => \axaddr_wrap[11]_i_2__0_n_0\,
I2 => \axaddr_wrap_reg[7]_i_2__0_n_5\,
I3 => \state_reg[1]_rep\,
I4 => Q(6),
O => \axaddr_wrap[6]_i_1__0_n_0\
);
\axaddr_wrap[7]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => \wrap_boundary_axaddr_r_reg_n_0_[7]\,
I1 => \axaddr_wrap[11]_i_2__0_n_0\,
I2 => \axaddr_wrap_reg[7]_i_2__0_n_4\,
I3 => \state_reg[1]_rep\,
I4 => Q(7),
O => \axaddr_wrap[7]_i_1__0_n_0\
);
\axaddr_wrap[8]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => \wrap_boundary_axaddr_r_reg_n_0_[8]\,
I1 => \axaddr_wrap[11]_i_2__0_n_0\,
I2 => \axaddr_wrap_reg[11]_i_3__0_n_7\,
I3 => \state_reg[1]_rep\,
I4 => Q(8),
O => \axaddr_wrap[8]_i_1__0_n_0\
);
\axaddr_wrap[9]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => \wrap_boundary_axaddr_r_reg_n_0_[9]\,
I1 => \axaddr_wrap[11]_i_2__0_n_0\,
I2 => \axaddr_wrap_reg[11]_i_3__0_n_6\,
I3 => \state_reg[1]_rep\,
I4 => Q(9),
O => \axaddr_wrap[9]_i_1__0_n_0\
);
\axaddr_wrap_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axaddr_wrap[0]_i_1__0_n_0\,
Q => \axaddr_wrap_reg_n_0_[0]\,
R => '0'
);
\axaddr_wrap_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axaddr_wrap[10]_i_1__0_n_0\,
Q => \axaddr_wrap_reg_n_0_[10]\,
R => '0'
);
\axaddr_wrap_reg[11]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axaddr_wrap[11]_i_1__0_n_0\,
Q => \axaddr_wrap_reg_n_0_[11]\,
R => '0'
);
\axaddr_wrap_reg[11]_i_3__0\: unisim.vcomponents.CARRY4
port map (
CI => \axaddr_wrap_reg[7]_i_2__0_n_0\,
CO(3) => \NLW_axaddr_wrap_reg[11]_i_3__0_CO_UNCONNECTED\(3),
CO(2) => \axaddr_wrap_reg[11]_i_3__0_n_1\,
CO(1) => \axaddr_wrap_reg[11]_i_3__0_n_2\,
CO(0) => \axaddr_wrap_reg[11]_i_3__0_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \axaddr_wrap_reg[11]_i_3__0_n_4\,
O(2) => \axaddr_wrap_reg[11]_i_3__0_n_5\,
O(1) => \axaddr_wrap_reg[11]_i_3__0_n_6\,
O(0) => \axaddr_wrap_reg[11]_i_3__0_n_7\,
S(3) => \axaddr_wrap_reg_n_0_[11]\,
S(2) => \axaddr_wrap_reg_n_0_[10]\,
S(1) => \axaddr_wrap_reg_n_0_[9]\,
S(0) => \axaddr_wrap_reg_n_0_[8]\
);
\axaddr_wrap_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axaddr_wrap[1]_i_1__0_n_0\,
Q => \axaddr_wrap_reg_n_0_[1]\,
R => '0'
);
\axaddr_wrap_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axaddr_wrap[2]_i_1__0_n_0\,
Q => \axaddr_wrap_reg_n_0_[2]\,
R => '0'
);
\axaddr_wrap_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axaddr_wrap[3]_i_1__0_n_0\,
Q => \axaddr_wrap_reg_n_0_[3]\,
R => '0'
);
\axaddr_wrap_reg[3]_i_2__0\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \axaddr_wrap_reg[3]_i_2__0_n_0\,
CO(2) => \axaddr_wrap_reg[3]_i_2__0_n_1\,
CO(1) => \axaddr_wrap_reg[3]_i_2__0_n_2\,
CO(0) => \axaddr_wrap_reg[3]_i_2__0_n_3\,
CYINIT => '0',
DI(3) => \axaddr_wrap_reg_n_0_[3]\,
DI(2) => \axaddr_wrap_reg_n_0_[2]\,
DI(1) => \axaddr_wrap_reg_n_0_[1]\,
DI(0) => \axaddr_wrap_reg_n_0_[0]\,
O(3) => \axaddr_wrap_reg[3]_i_2__0_n_4\,
O(2) => \axaddr_wrap_reg[3]_i_2__0_n_5\,
O(1) => \axaddr_wrap_reg[3]_i_2__0_n_6\,
O(0) => \axaddr_wrap_reg[3]_i_2__0_n_7\,
S(3) => \axaddr_wrap[3]_i_3_n_0\,
S(2) => \axaddr_wrap[3]_i_4_n_0\,
S(1) => \axaddr_wrap[3]_i_5_n_0\,
S(0) => \axaddr_wrap[3]_i_6_n_0\
);
\axaddr_wrap_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axaddr_wrap[4]_i_1__0_n_0\,
Q => \axaddr_wrap_reg_n_0_[4]\,
R => '0'
);
\axaddr_wrap_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axaddr_wrap[5]_i_1__0_n_0\,
Q => \axaddr_wrap_reg_n_0_[5]\,
R => '0'
);
\axaddr_wrap_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axaddr_wrap[6]_i_1__0_n_0\,
Q => \axaddr_wrap_reg_n_0_[6]\,
R => '0'
);
\axaddr_wrap_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axaddr_wrap[7]_i_1__0_n_0\,
Q => \axaddr_wrap_reg_n_0_[7]\,
R => '0'
);
\axaddr_wrap_reg[7]_i_2__0\: unisim.vcomponents.CARRY4
port map (
CI => \axaddr_wrap_reg[3]_i_2__0_n_0\,
CO(3) => \axaddr_wrap_reg[7]_i_2__0_n_0\,
CO(2) => \axaddr_wrap_reg[7]_i_2__0_n_1\,
CO(1) => \axaddr_wrap_reg[7]_i_2__0_n_2\,
CO(0) => \axaddr_wrap_reg[7]_i_2__0_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \axaddr_wrap_reg[7]_i_2__0_n_4\,
O(2) => \axaddr_wrap_reg[7]_i_2__0_n_5\,
O(1) => \axaddr_wrap_reg[7]_i_2__0_n_6\,
O(0) => \axaddr_wrap_reg[7]_i_2__0_n_7\,
S(3) => \axaddr_wrap_reg_n_0_[7]\,
S(2) => \axaddr_wrap_reg_n_0_[6]\,
S(1) => \axaddr_wrap_reg_n_0_[5]\,
S(0) => \axaddr_wrap_reg_n_0_[4]\
);
\axaddr_wrap_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axaddr_wrap[8]_i_1__0_n_0\,
Q => \axaddr_wrap_reg_n_0_[8]\,
R => '0'
);
\axaddr_wrap_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axaddr_wrap[9]_i_1__0_n_0\,
Q => \axaddr_wrap_reg_n_0_[9]\,
R => '0'
);
\axlen_cnt[0]_i_1__1\: unisim.vcomponents.LUT6
generic map(
INIT => X"A3A3A3A3A3A3A3A0"
)
port map (
I0 => Q(15),
I1 => \axlen_cnt_reg_n_0_[0]\,
I2 => E(0),
I3 => \axlen_cnt_reg_n_0_[3]\,
I4 => \axlen_cnt_reg_n_0_[2]\,
I5 => \axlen_cnt_reg_n_0_[1]\,
O => \axlen_cnt[0]_i_1__1_n_0\
);
\axlen_cnt[1]_i_1__2\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAC3AAC3AAC3AAC0"
)
port map (
I0 => Q(16),
I1 => \axlen_cnt_reg_n_0_[1]\,
I2 => \axlen_cnt_reg_n_0_[0]\,
I3 => E(0),
I4 => \axlen_cnt_reg_n_0_[3]\,
I5 => \axlen_cnt_reg_n_0_[2]\,
O => \axlen_cnt[1]_i_1__2_n_0\
);
\axlen_cnt[2]_i_1__2\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFA9A80000A9A8"
)
port map (
I0 => \axlen_cnt_reg_n_0_[2]\,
I1 => \axlen_cnt_reg_n_0_[0]\,
I2 => \axlen_cnt_reg_n_0_[1]\,
I3 => \axlen_cnt_reg_n_0_[3]\,
I4 => E(0),
I5 => Q(17),
O => \axlen_cnt[2]_i_1__2_n_0\
);
\axlen_cnt[3]_i_1__1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAAAAAAACCCCCCC0"
)
port map (
I0 => Q(18),
I1 => \axlen_cnt_reg_n_0_[3]\,
I2 => \axlen_cnt_reg_n_0_[2]\,
I3 => \axlen_cnt_reg_n_0_[1]\,
I4 => \axlen_cnt_reg_n_0_[0]\,
I5 => E(0),
O => \axlen_cnt[3]_i_1__1_n_0\
);
\axlen_cnt_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axlen_cnt[0]_i_1__1_n_0\,
Q => \axlen_cnt_reg_n_0_[0]\,
R => '0'
);
\axlen_cnt_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axlen_cnt[1]_i_1__2_n_0\,
Q => \axlen_cnt_reg_n_0_[1]\,
R => '0'
);
\axlen_cnt_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axlen_cnt[2]_i_1__2_n_0\,
Q => \axlen_cnt_reg_n_0_[2]\,
R => '0'
);
\axlen_cnt_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axlen_cnt[3]_i_1__1_n_0\,
Q => \axlen_cnt_reg_n_0_[3]\,
R => '0'
);
\m_axi_araddr[0]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"EF40EF4FEF40E040"
)
port map (
I0 => \^sel_first_reg_0\,
I1 => \axaddr_wrap_reg_n_0_[0]\,
I2 => Q(14),
I3 => Q(0),
I4 => sel_first_reg_2,
I5 => \axaddr_incr_reg[11]\(0),
O => m_axi_araddr(0)
);
\m_axi_araddr[10]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"EF40EF4FEF40E040"
)
port map (
I0 => \^sel_first_reg_0\,
I1 => \axaddr_wrap_reg_n_0_[10]\,
I2 => Q(14),
I3 => Q(10),
I4 => sel_first_reg_2,
I5 => \axaddr_incr_reg[11]\(6),
O => m_axi_araddr(10)
);
\m_axi_araddr[11]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"EF40EF4FEF40E040"
)
port map (
I0 => \^sel_first_reg_0\,
I1 => \axaddr_wrap_reg_n_0_[11]\,
I2 => Q(14),
I3 => Q(11),
I4 => sel_first_reg_2,
I5 => \axaddr_incr_reg[11]\(7),
O => m_axi_araddr(11)
);
\m_axi_araddr[1]_INST_0\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => Q(1),
I1 => \^sel_first_reg_0\,
I2 => \axaddr_wrap_reg_n_0_[1]\,
I3 => Q(14),
I4 => sel_first_reg_6,
O => m_axi_araddr(1)
);
\m_axi_araddr[2]_INST_0\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => Q(2),
I1 => \^sel_first_reg_0\,
I2 => \axaddr_wrap_reg_n_0_[2]\,
I3 => Q(14),
I4 => sel_first_reg_5,
O => m_axi_araddr(2)
);
\m_axi_araddr[3]_INST_0\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => Q(3),
I1 => \^sel_first_reg_0\,
I2 => \axaddr_wrap_reg_n_0_[3]\,
I3 => Q(14),
I4 => sel_first_reg_4,
O => m_axi_araddr(3)
);
\m_axi_araddr[4]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"EF40EF4FEF40E040"
)
port map (
I0 => \^sel_first_reg_0\,
I1 => \axaddr_wrap_reg_n_0_[4]\,
I2 => Q(14),
I3 => Q(4),
I4 => sel_first_reg_2,
I5 => \axaddr_incr_reg[11]\(1),
O => m_axi_araddr(4)
);
\m_axi_araddr[5]_INST_0\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => Q(5),
I1 => \^sel_first_reg_0\,
I2 => \axaddr_wrap_reg_n_0_[5]\,
I3 => Q(14),
I4 => sel_first_reg_3,
O => m_axi_araddr(5)
);
\m_axi_araddr[6]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"EF40EF4FEF40E040"
)
port map (
I0 => \^sel_first_reg_0\,
I1 => \axaddr_wrap_reg_n_0_[6]\,
I2 => Q(14),
I3 => Q(6),
I4 => sel_first_reg_2,
I5 => \axaddr_incr_reg[11]\(2),
O => m_axi_araddr(6)
);
\m_axi_araddr[7]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"EF40EF4FEF40E040"
)
port map (
I0 => \^sel_first_reg_0\,
I1 => \axaddr_wrap_reg_n_0_[7]\,
I2 => Q(14),
I3 => Q(7),
I4 => sel_first_reg_2,
I5 => \axaddr_incr_reg[11]\(3),
O => m_axi_araddr(7)
);
\m_axi_araddr[8]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"EF40EF4FEF40E040"
)
port map (
I0 => \^sel_first_reg_0\,
I1 => \axaddr_wrap_reg_n_0_[8]\,
I2 => Q(14),
I3 => Q(8),
I4 => sel_first_reg_2,
I5 => \axaddr_incr_reg[11]\(4),
O => m_axi_araddr(8)
);
\m_axi_araddr[9]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"EF40EF4FEF40E040"
)
port map (
I0 => \^sel_first_reg_0\,
I1 => \axaddr_wrap_reg_n_0_[9]\,
I2 => Q(14),
I3 => Q(9),
I4 => sel_first_reg_2,
I5 => \axaddr_incr_reg[11]\(5),
O => m_axi_araddr(9)
);
\next_pending_r_i_1__1\: unisim.vcomponents.LUT5
generic map(
INIT => X"FEAAFEAE"
)
port map (
I0 => \m_payload_i_reg[47]\,
I1 => next_pending_r_reg_n_0,
I2 => \state_reg[1]_rep\,
I3 => \next_pending_r_i_2__2_n_0\,
I4 => E(0),
O => wrap_next_pending
);
\next_pending_r_i_2__2\: unisim.vcomponents.LUT6
generic map(
INIT => X"FBFBFBFBFBFBFB00"
)
port map (
I0 => \state_reg[1]\(0),
I1 => si_rs_arvalid,
I2 => \state_reg[1]\(1),
I3 => \axlen_cnt_reg_n_0_[3]\,
I4 => \axlen_cnt_reg_n_0_[2]\,
I5 => \axlen_cnt_reg_n_0_[1]\,
O => \next_pending_r_i_2__2_n_0\
);
next_pending_r_reg: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => wrap_next_pending,
Q => next_pending_r_reg_n_0,
R => '0'
);
\s_axburst_eq0_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => wrap_next_pending,
I1 => Q(14),
I2 => sel_first_i,
I3 => incr_next_pending,
O => s_axburst_eq0_reg
);
\s_axburst_eq1_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"ABA8"
)
port map (
I0 => wrap_next_pending,
I1 => Q(14),
I2 => sel_first_i,
I3 => incr_next_pending,
O => s_axburst_eq1_reg
);
sel_first_reg: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => sel_first_reg_1,
Q => \^sel_first_reg_0\,
R => '0'
);
\wrap_boundary_axaddr_r_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \m_payload_i_reg[6]\(0),
Q => \wrap_boundary_axaddr_r_reg_n_0_[0]\,
R => '0'
);
\wrap_boundary_axaddr_r_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => Q(10),
Q => \wrap_boundary_axaddr_r_reg_n_0_[10]\,
R => '0'
);
\wrap_boundary_axaddr_r_reg[11]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => Q(11),
Q => \wrap_boundary_axaddr_r_reg_n_0_[11]\,
R => '0'
);
\wrap_boundary_axaddr_r_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \m_payload_i_reg[6]\(1),
Q => \wrap_boundary_axaddr_r_reg_n_0_[1]\,
R => '0'
);
\wrap_boundary_axaddr_r_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \m_payload_i_reg[6]\(2),
Q => \wrap_boundary_axaddr_r_reg_n_0_[2]\,
R => '0'
);
\wrap_boundary_axaddr_r_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \m_payload_i_reg[6]\(3),
Q => \wrap_boundary_axaddr_r_reg_n_0_[3]\,
R => '0'
);
\wrap_boundary_axaddr_r_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \m_payload_i_reg[6]\(4),
Q => \wrap_boundary_axaddr_r_reg_n_0_[4]\,
R => '0'
);
\wrap_boundary_axaddr_r_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \m_payload_i_reg[6]\(5),
Q => \wrap_boundary_axaddr_r_reg_n_0_[5]\,
R => '0'
);
\wrap_boundary_axaddr_r_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \m_payload_i_reg[6]\(6),
Q => \wrap_boundary_axaddr_r_reg_n_0_[6]\,
R => '0'
);
\wrap_boundary_axaddr_r_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => Q(7),
Q => \wrap_boundary_axaddr_r_reg_n_0_[7]\,
R => '0'
);
\wrap_boundary_axaddr_r_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => Q(8),
Q => \wrap_boundary_axaddr_r_reg_n_0_[8]\,
R => '0'
);
\wrap_boundary_axaddr_r_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => Q(9),
Q => \wrap_boundary_axaddr_r_reg_n_0_[9]\,
R => '0'
);
\wrap_cnt_r[1]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"3D310E02"
)
port map (
I0 => \^wrap_second_len_r_reg[3]_0\(0),
I1 => E(0),
I2 => \axaddr_offset_r_reg[3]_2\,
I3 => D(1),
I4 => \^wrap_second_len_r_reg[3]_0\(1),
O => \wrap_cnt_r[1]_i_1__0_n_0\
);
\wrap_cnt_r[3]_i_2__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"000CAAA8000C0000"
)
port map (
I0 => \^wrap_second_len_r_reg[3]_0\(1),
I1 => \axaddr_offset_r_reg[3]_1\,
I2 => D(1),
I3 => D(0),
I4 => E(0),
I5 => \^wrap_second_len_r_reg[3]_0\(0),
O => \wrap_cnt_r_reg[3]_0\
);
\wrap_cnt_r_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \wrap_second_len_r_reg[3]_2\(0),
Q => \wrap_cnt_r_reg_n_0_[0]\,
R => '0'
);
\wrap_cnt_r_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \wrap_cnt_r[1]_i_1__0_n_0\,
Q => \wrap_cnt_r_reg_n_0_[1]\,
R => '0'
);
\wrap_cnt_r_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \wrap_second_len_r_reg[3]_2\(1),
Q => \wrap_cnt_r_reg_n_0_[2]\,
R => '0'
);
\wrap_cnt_r_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \wrap_second_len_r_reg[3]_2\(2),
Q => \wrap_cnt_r_reg_n_0_[3]\,
R => '0'
);
\wrap_second_len_r_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \wrap_second_len_r_reg[3]_1\(0),
Q => \^wrap_second_len_r_reg[3]_0\(0),
R => '0'
);
\wrap_second_len_r_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \wrap_second_len_r_reg[3]_1\(1),
Q => \^wrap_second_len_r_reg[3]_0\(1),
R => '0'
);
\wrap_second_len_r_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \wrap_second_len_r_reg[3]_1\(2),
Q => \^wrap_second_len_r_reg[3]_0\(2),
R => '0'
);
\wrap_second_len_r_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \wrap_second_len_r_reg[3]_1\(3),
Q => \^wrap_second_len_r_reg[3]_0\(3),
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity zybo_zynq_design_auto_pc_0_axi_register_slice_v2_1_17_axic_register_slice is
port (
s_axi_arready : out STD_LOGIC;
\axaddr_offset_r_reg[3]\ : out STD_LOGIC;
m_valid_i_reg_0 : out STD_LOGIC;
\axlen_cnt_reg[3]\ : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 54 downto 0 );
\axaddr_incr_reg[3]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
\axaddr_incr_reg[7]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
O : out STD_LOGIC_VECTOR ( 3 downto 0 );
\wrap_cnt_r_reg[3]\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
\wrap_second_len_r_reg[3]\ : out STD_LOGIC_VECTOR ( 2 downto 0 );
\wrap_cnt_r_reg[2]\ : out STD_LOGIC;
\axaddr_offset_r_reg[0]\ : out STD_LOGIC;
axaddr_offset_0 : out STD_LOGIC_VECTOR ( 1 downto 0 );
\wrap_cnt_r_reg[3]_0\ : out STD_LOGIC;
\axaddr_offset_r_reg[2]\ : out STD_LOGIC;
next_pending_r_reg : out STD_LOGIC;
\wrap_boundary_axaddr_r_reg[6]\ : out STD_LOGIC_VECTOR ( 6 downto 0 );
\aresetn_d_reg[0]\ : in STD_LOGIC;
s_ready_i0 : in STD_LOGIC;
aclk : in STD_LOGIC;
m_valid_i0 : in STD_LOGIC;
\aresetn_d_reg[0]_0\ : in STD_LOGIC;
\state_reg[1]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
\m_payload_i_reg[3]_0\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\wrap_second_len_r_reg[3]_0\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\state_reg[1]_rep\ : in STD_LOGIC;
\wrap_second_len_r_reg[1]\ : in STD_LOGIC;
\axaddr_offset_r_reg[2]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\axaddr_offset_r_reg[3]_0\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
\axaddr_offset_r_reg[3]_1\ : in STD_LOGIC;
\axaddr_offset_r_reg[2]_1\ : in STD_LOGIC;
\state_reg[0]_rep\ : in STD_LOGIC;
\state_reg[1]_rep_0\ : in STD_LOGIC;
s_axi_arid : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_arlen : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arsize : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
m_valid_i_reg_1 : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of zybo_zynq_design_auto_pc_0_axi_register_slice_v2_1_17_axic_register_slice : entity is "axi_register_slice_v2_1_17_axic_register_slice";
end zybo_zynq_design_auto_pc_0_axi_register_slice_v2_1_17_axic_register_slice;
architecture STRUCTURE of zybo_zynq_design_auto_pc_0_axi_register_slice_v2_1_17_axic_register_slice is
signal \^q\ : STD_LOGIC_VECTOR ( 54 downto 0 );
signal \axaddr_incr[3]_i_4__0_n_0\ : STD_LOGIC;
signal \axaddr_incr[3]_i_5__0_n_0\ : STD_LOGIC;
signal \axaddr_incr[3]_i_6__0_n_0\ : STD_LOGIC;
signal \axaddr_incr_reg[11]_i_3__0_n_1\ : STD_LOGIC;
signal \axaddr_incr_reg[11]_i_3__0_n_2\ : STD_LOGIC;
signal \axaddr_incr_reg[11]_i_3__0_n_3\ : STD_LOGIC;
signal \axaddr_incr_reg[3]_i_2__0_n_0\ : STD_LOGIC;
signal \axaddr_incr_reg[3]_i_2__0_n_1\ : STD_LOGIC;
signal \axaddr_incr_reg[3]_i_2__0_n_2\ : STD_LOGIC;
signal \axaddr_incr_reg[3]_i_2__0_n_3\ : STD_LOGIC;
signal \axaddr_incr_reg[7]_i_2__0_n_0\ : STD_LOGIC;
signal \axaddr_incr_reg[7]_i_2__0_n_1\ : STD_LOGIC;
signal \axaddr_incr_reg[7]_i_2__0_n_2\ : STD_LOGIC;
signal \axaddr_incr_reg[7]_i_2__0_n_3\ : STD_LOGIC;
signal \^axaddr_offset_0\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \axaddr_offset_r[0]_i_2__0_n_0\ : STD_LOGIC;
signal \axaddr_offset_r[1]_i_2__0_n_0\ : STD_LOGIC;
signal \axaddr_offset_r[3]_i_2__0_n_0\ : STD_LOGIC;
signal \^axaddr_offset_r_reg[0]\ : STD_LOGIC;
signal \^axaddr_offset_r_reg[2]\ : STD_LOGIC;
signal \^axaddr_offset_r_reg[3]\ : STD_LOGIC;
signal \^axlen_cnt_reg[3]\ : STD_LOGIC;
signal \m_payload_i[0]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[10]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[11]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[12]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[13]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[14]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[15]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[16]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[17]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[18]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[19]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[1]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[20]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[21]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[22]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[23]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[24]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[25]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[26]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[27]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[28]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[29]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[2]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[30]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[31]_i_2__0_n_0\ : STD_LOGIC;
signal \m_payload_i[32]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[33]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[34]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[35]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[36]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[38]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[39]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[3]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[44]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[45]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[46]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[47]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[4]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[50]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[51]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[52]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[53]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[54]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[55]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[56]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[57]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[58]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[59]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[5]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[60]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[61]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[6]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[7]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[8]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[9]_i_1__0_n_0\ : STD_LOGIC;
signal \^m_valid_i_reg_0\ : STD_LOGIC;
signal \^s_axi_arready\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[0]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[10]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[11]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[12]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[13]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[14]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[15]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[16]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[17]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[18]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[19]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[1]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[20]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[21]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[22]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[23]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[24]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[25]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[26]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[27]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[28]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[29]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[2]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[30]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[31]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[32]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[33]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[34]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[35]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[36]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[38]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[39]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[3]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[44]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[45]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[46]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[47]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[4]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[50]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[51]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[52]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[53]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[54]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[55]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[56]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[57]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[58]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[59]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[5]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[60]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[61]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[6]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[7]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[8]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[9]\ : STD_LOGIC;
signal \wrap_boundary_axaddr_r[3]_i_2__0_n_0\ : STD_LOGIC;
signal \wrap_cnt_r[3]_i_5__0_n_0\ : STD_LOGIC;
signal \^wrap_cnt_r_reg[2]\ : STD_LOGIC;
signal \wrap_second_len_r[3]_i_2__0_n_0\ : STD_LOGIC;
signal \wrap_second_len_r[3]_i_3__0_n_0\ : STD_LOGIC;
signal \^wrap_second_len_r_reg[3]\ : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \NLW_axaddr_incr_reg[11]_i_3__0_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \m_payload_i[10]_i_1__0\ : label is "soft_lutpair44";
attribute SOFT_HLUTNM of \m_payload_i[11]_i_1__0\ : label is "soft_lutpair43";
attribute SOFT_HLUTNM of \m_payload_i[12]_i_1__0\ : label is "soft_lutpair43";
attribute SOFT_HLUTNM of \m_payload_i[13]_i_1__1\ : label is "soft_lutpair42";
attribute SOFT_HLUTNM of \m_payload_i[14]_i_1__0\ : label is "soft_lutpair42";
attribute SOFT_HLUTNM of \m_payload_i[15]_i_1__0\ : label is "soft_lutpair41";
attribute SOFT_HLUTNM of \m_payload_i[16]_i_1__0\ : label is "soft_lutpair41";
attribute SOFT_HLUTNM of \m_payload_i[17]_i_1__0\ : label is "soft_lutpair40";
attribute SOFT_HLUTNM of \m_payload_i[18]_i_1__0\ : label is "soft_lutpair40";
attribute SOFT_HLUTNM of \m_payload_i[19]_i_1__0\ : label is "soft_lutpair39";
attribute SOFT_HLUTNM of \m_payload_i[1]_i_1__0\ : label is "soft_lutpair48";
attribute SOFT_HLUTNM of \m_payload_i[20]_i_1__0\ : label is "soft_lutpair39";
attribute SOFT_HLUTNM of \m_payload_i[21]_i_1__0\ : label is "soft_lutpair38";
attribute SOFT_HLUTNM of \m_payload_i[22]_i_1__0\ : label is "soft_lutpair38";
attribute SOFT_HLUTNM of \m_payload_i[23]_i_1__0\ : label is "soft_lutpair37";
attribute SOFT_HLUTNM of \m_payload_i[24]_i_1__0\ : label is "soft_lutpair37";
attribute SOFT_HLUTNM of \m_payload_i[25]_i_1__0\ : label is "soft_lutpair36";
attribute SOFT_HLUTNM of \m_payload_i[26]_i_1__0\ : label is "soft_lutpair36";
attribute SOFT_HLUTNM of \m_payload_i[27]_i_1__0\ : label is "soft_lutpair35";
attribute SOFT_HLUTNM of \m_payload_i[28]_i_1__0\ : label is "soft_lutpair35";
attribute SOFT_HLUTNM of \m_payload_i[29]_i_1__0\ : label is "soft_lutpair34";
attribute SOFT_HLUTNM of \m_payload_i[2]_i_1__0\ : label is "soft_lutpair48";
attribute SOFT_HLUTNM of \m_payload_i[30]_i_1__0\ : label is "soft_lutpair34";
attribute SOFT_HLUTNM of \m_payload_i[31]_i_2__0\ : label is "soft_lutpair33";
attribute SOFT_HLUTNM of \m_payload_i[32]_i_1__0\ : label is "soft_lutpair33";
attribute SOFT_HLUTNM of \m_payload_i[33]_i_1__0\ : label is "soft_lutpair32";
attribute SOFT_HLUTNM of \m_payload_i[34]_i_1__0\ : label is "soft_lutpair32";
attribute SOFT_HLUTNM of \m_payload_i[35]_i_1__0\ : label is "soft_lutpair31";
attribute SOFT_HLUTNM of \m_payload_i[36]_i_1__0\ : label is "soft_lutpair31";
attribute SOFT_HLUTNM of \m_payload_i[38]_i_1__0\ : label is "soft_lutpair30";
attribute SOFT_HLUTNM of \m_payload_i[39]_i_1__0\ : label is "soft_lutpair30";
attribute SOFT_HLUTNM of \m_payload_i[3]_i_1__0\ : label is "soft_lutpair47";
attribute SOFT_HLUTNM of \m_payload_i[44]_i_1__0\ : label is "soft_lutpair29";
attribute SOFT_HLUTNM of \m_payload_i[45]_i_1__0\ : label is "soft_lutpair29";
attribute SOFT_HLUTNM of \m_payload_i[46]_i_1__1\ : label is "soft_lutpair28";
attribute SOFT_HLUTNM of \m_payload_i[47]_i_1__0\ : label is "soft_lutpair28";
attribute SOFT_HLUTNM of \m_payload_i[4]_i_1__0\ : label is "soft_lutpair47";
attribute SOFT_HLUTNM of \m_payload_i[50]_i_1__0\ : label is "soft_lutpair27";
attribute SOFT_HLUTNM of \m_payload_i[51]_i_1__0\ : label is "soft_lutpair27";
attribute SOFT_HLUTNM of \m_payload_i[52]_i_1__0\ : label is "soft_lutpair26";
attribute SOFT_HLUTNM of \m_payload_i[53]_i_1__0\ : label is "soft_lutpair26";
attribute SOFT_HLUTNM of \m_payload_i[54]_i_1__0\ : label is "soft_lutpair25";
attribute SOFT_HLUTNM of \m_payload_i[55]_i_1__0\ : label is "soft_lutpair25";
attribute SOFT_HLUTNM of \m_payload_i[56]_i_1__0\ : label is "soft_lutpair24";
attribute SOFT_HLUTNM of \m_payload_i[57]_i_1__0\ : label is "soft_lutpair24";
attribute SOFT_HLUTNM of \m_payload_i[58]_i_1__0\ : label is "soft_lutpair23";
attribute SOFT_HLUTNM of \m_payload_i[59]_i_1__0\ : label is "soft_lutpair23";
attribute SOFT_HLUTNM of \m_payload_i[5]_i_1__0\ : label is "soft_lutpair46";
attribute SOFT_HLUTNM of \m_payload_i[60]_i_1__0\ : label is "soft_lutpair22";
attribute SOFT_HLUTNM of \m_payload_i[61]_i_1__0\ : label is "soft_lutpair22";
attribute SOFT_HLUTNM of \m_payload_i[6]_i_1__0\ : label is "soft_lutpair46";
attribute SOFT_HLUTNM of \m_payload_i[7]_i_1__0\ : label is "soft_lutpair45";
attribute SOFT_HLUTNM of \m_payload_i[8]_i_1__0\ : label is "soft_lutpair45";
attribute SOFT_HLUTNM of \m_payload_i[9]_i_1__0\ : label is "soft_lutpair44";
attribute SOFT_HLUTNM of \wrap_boundary_axaddr_r[3]_i_2__0\ : label is "soft_lutpair21";
attribute SOFT_HLUTNM of \wrap_boundary_axaddr_r[5]_i_1__0\ : label is "soft_lutpair21";
begin
Q(54 downto 0) <= \^q\(54 downto 0);
axaddr_offset_0(1 downto 0) <= \^axaddr_offset_0\(1 downto 0);
\axaddr_offset_r_reg[0]\ <= \^axaddr_offset_r_reg[0]\;
\axaddr_offset_r_reg[2]\ <= \^axaddr_offset_r_reg[2]\;
\axaddr_offset_r_reg[3]\ <= \^axaddr_offset_r_reg[3]\;
\axlen_cnt_reg[3]\ <= \^axlen_cnt_reg[3]\;
m_valid_i_reg_0 <= \^m_valid_i_reg_0\;
s_axi_arready <= \^s_axi_arready\;
\wrap_cnt_r_reg[2]\ <= \^wrap_cnt_r_reg[2]\;
\wrap_second_len_r_reg[3]\(2 downto 0) <= \^wrap_second_len_r_reg[3]\(2 downto 0);
\aresetn_d_reg[1]_inv\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \aresetn_d_reg[0]_0\,
Q => \^m_valid_i_reg_0\,
R => '0'
);
\axaddr_incr[3]_i_4__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"2A"
)
port map (
I0 => \^q\(2),
I1 => \^q\(35),
I2 => \^q\(36),
O => \axaddr_incr[3]_i_4__0_n_0\
);
\axaddr_incr[3]_i_5__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \^q\(1),
I1 => \^q\(36),
O => \axaddr_incr[3]_i_5__0_n_0\
);
\axaddr_incr[3]_i_6__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"02"
)
port map (
I0 => \^q\(0),
I1 => \^q\(35),
I2 => \^q\(36),
O => \axaddr_incr[3]_i_6__0_n_0\
);
\axaddr_incr_reg[11]_i_3__0\: unisim.vcomponents.CARRY4
port map (
CI => \axaddr_incr_reg[7]_i_2__0_n_0\,
CO(3) => \NLW_axaddr_incr_reg[11]_i_3__0_CO_UNCONNECTED\(3),
CO(2) => \axaddr_incr_reg[11]_i_3__0_n_1\,
CO(1) => \axaddr_incr_reg[11]_i_3__0_n_2\,
CO(0) => \axaddr_incr_reg[11]_i_3__0_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 0) => O(3 downto 0),
S(3 downto 0) => \^q\(11 downto 8)
);
\axaddr_incr_reg[3]_i_2__0\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \axaddr_incr_reg[3]_i_2__0_n_0\,
CO(2) => \axaddr_incr_reg[3]_i_2__0_n_1\,
CO(1) => \axaddr_incr_reg[3]_i_2__0_n_2\,
CO(0) => \axaddr_incr_reg[3]_i_2__0_n_3\,
CYINIT => '0',
DI(3) => \^q\(3),
DI(2) => \axaddr_incr[3]_i_4__0_n_0\,
DI(1) => \axaddr_incr[3]_i_5__0_n_0\,
DI(0) => \axaddr_incr[3]_i_6__0_n_0\,
O(3 downto 0) => \axaddr_incr_reg[3]\(3 downto 0),
S(3 downto 0) => \m_payload_i_reg[3]_0\(3 downto 0)
);
\axaddr_incr_reg[7]_i_2__0\: unisim.vcomponents.CARRY4
port map (
CI => \axaddr_incr_reg[3]_i_2__0_n_0\,
CO(3) => \axaddr_incr_reg[7]_i_2__0_n_0\,
CO(2) => \axaddr_incr_reg[7]_i_2__0_n_1\,
CO(1) => \axaddr_incr_reg[7]_i_2__0_n_2\,
CO(0) => \axaddr_incr_reg[7]_i_2__0_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 0) => \axaddr_incr_reg[7]\(3 downto 0),
S(3 downto 0) => \^q\(7 downto 4)
);
\axaddr_offset_r[0]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFF8FF00000800"
)
port map (
I0 => \axaddr_offset_r[0]_i_2__0_n_0\,
I1 => \^q\(39),
I2 => \state_reg[1]\(1),
I3 => \^axaddr_offset_r_reg[3]\,
I4 => \state_reg[1]\(0),
I5 => \axaddr_offset_r_reg[3]_0\(0),
O => \^axaddr_offset_r_reg[0]\
);
\axaddr_offset_r[0]_i_2__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \^q\(3),
I1 => \^q\(2),
I2 => \^q\(36),
I3 => \^q\(1),
I4 => \^q\(35),
I5 => \^q\(0),
O => \axaddr_offset_r[0]_i_2__0_n_0\
);
\axaddr_offset_r[1]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFF8FF00000800"
)
port map (
I0 => \axaddr_offset_r[1]_i_2__0_n_0\,
I1 => \^q\(40),
I2 => \state_reg[1]\(1),
I3 => \^axaddr_offset_r_reg[3]\,
I4 => \state_reg[1]\(0),
I5 => \axaddr_offset_r_reg[3]_0\(1),
O => \^axaddr_offset_0\(0)
);
\axaddr_offset_r[1]_i_2__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \^q\(4),
I1 => \^q\(3),
I2 => \^q\(36),
I3 => \^q\(2),
I4 => \^q\(35),
I5 => \^q\(1),
O => \axaddr_offset_r[1]_i_2__0_n_0\
);
\axaddr_offset_r[2]_i_2__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \^q\(5),
I1 => \^q\(4),
I2 => \^q\(36),
I3 => \^q\(3),
I4 => \^q\(35),
I5 => \^q\(2),
O => \^axaddr_offset_r_reg[2]\
);
\axaddr_offset_r[3]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFF8FF00000800"
)
port map (
I0 => \axaddr_offset_r[3]_i_2__0_n_0\,
I1 => \^q\(42),
I2 => \state_reg[1]\(1),
I3 => \^axaddr_offset_r_reg[3]\,
I4 => \state_reg[1]\(0),
I5 => \axaddr_offset_r_reg[3]_0\(2),
O => \^axaddr_offset_0\(1)
);
\axaddr_offset_r[3]_i_2__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \^q\(6),
I1 => \^q\(5),
I2 => \^q\(36),
I3 => \^q\(4),
I4 => \^q\(35),
I5 => \^q\(3),
O => \axaddr_offset_r[3]_i_2__0_n_0\
);
\axlen_cnt[3]_i_3__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"0020"
)
port map (
I0 => \^q\(42),
I1 => \state_reg[1]\(0),
I2 => \^axaddr_offset_r_reg[3]\,
I3 => \state_reg[1]\(1),
O => \^axlen_cnt_reg[3]\
);
\m_payload_i[0]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(0),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[0]\,
O => \m_payload_i[0]_i_1__0_n_0\
);
\m_payload_i[10]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(10),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[10]\,
O => \m_payload_i[10]_i_1__0_n_0\
);
\m_payload_i[11]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(11),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[11]\,
O => \m_payload_i[11]_i_1__0_n_0\
);
\m_payload_i[12]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(12),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[12]\,
O => \m_payload_i[12]_i_1__0_n_0\
);
\m_payload_i[13]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(13),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[13]\,
O => \m_payload_i[13]_i_1__1_n_0\
);
\m_payload_i[14]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(14),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[14]\,
O => \m_payload_i[14]_i_1__0_n_0\
);
\m_payload_i[15]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(15),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[15]\,
O => \m_payload_i[15]_i_1__0_n_0\
);
\m_payload_i[16]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(16),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[16]\,
O => \m_payload_i[16]_i_1__0_n_0\
);
\m_payload_i[17]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(17),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[17]\,
O => \m_payload_i[17]_i_1__0_n_0\
);
\m_payload_i[18]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(18),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[18]\,
O => \m_payload_i[18]_i_1__0_n_0\
);
\m_payload_i[19]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(19),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[19]\,
O => \m_payload_i[19]_i_1__0_n_0\
);
\m_payload_i[1]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(1),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[1]\,
O => \m_payload_i[1]_i_1__0_n_0\
);
\m_payload_i[20]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(20),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[20]\,
O => \m_payload_i[20]_i_1__0_n_0\
);
\m_payload_i[21]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(21),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[21]\,
O => \m_payload_i[21]_i_1__0_n_0\
);
\m_payload_i[22]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(22),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[22]\,
O => \m_payload_i[22]_i_1__0_n_0\
);
\m_payload_i[23]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(23),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[23]\,
O => \m_payload_i[23]_i_1__0_n_0\
);
\m_payload_i[24]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(24),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[24]\,
O => \m_payload_i[24]_i_1__0_n_0\
);
\m_payload_i[25]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(25),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[25]\,
O => \m_payload_i[25]_i_1__0_n_0\
);
\m_payload_i[26]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(26),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[26]\,
O => \m_payload_i[26]_i_1__0_n_0\
);
\m_payload_i[27]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(27),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[27]\,
O => \m_payload_i[27]_i_1__0_n_0\
);
\m_payload_i[28]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(28),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[28]\,
O => \m_payload_i[28]_i_1__0_n_0\
);
\m_payload_i[29]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(29),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[29]\,
O => \m_payload_i[29]_i_1__0_n_0\
);
\m_payload_i[2]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(2),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[2]\,
O => \m_payload_i[2]_i_1__0_n_0\
);
\m_payload_i[30]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(30),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[30]\,
O => \m_payload_i[30]_i_1__0_n_0\
);
\m_payload_i[31]_i_2__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(31),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[31]\,
O => \m_payload_i[31]_i_2__0_n_0\
);
\m_payload_i[32]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_arprot(0),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[32]\,
O => \m_payload_i[32]_i_1__0_n_0\
);
\m_payload_i[33]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_arprot(1),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[33]\,
O => \m_payload_i[33]_i_1__0_n_0\
);
\m_payload_i[34]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_arprot(2),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[34]\,
O => \m_payload_i[34]_i_1__0_n_0\
);
\m_payload_i[35]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_arsize(0),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[35]\,
O => \m_payload_i[35]_i_1__0_n_0\
);
\m_payload_i[36]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_arsize(1),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[36]\,
O => \m_payload_i[36]_i_1__0_n_0\
);
\m_payload_i[38]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_arburst(0),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[38]\,
O => \m_payload_i[38]_i_1__0_n_0\
);
\m_payload_i[39]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_arburst(1),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[39]\,
O => \m_payload_i[39]_i_1__0_n_0\
);
\m_payload_i[3]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(3),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[3]\,
O => \m_payload_i[3]_i_1__0_n_0\
);
\m_payload_i[44]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_arlen(0),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[44]\,
O => \m_payload_i[44]_i_1__0_n_0\
);
\m_payload_i[45]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_arlen(1),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[45]\,
O => \m_payload_i[45]_i_1__0_n_0\
);
\m_payload_i[46]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_arlen(2),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[46]\,
O => \m_payload_i[46]_i_1__1_n_0\
);
\m_payload_i[47]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_arlen(3),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[47]\,
O => \m_payload_i[47]_i_1__0_n_0\
);
\m_payload_i[4]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(4),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[4]\,
O => \m_payload_i[4]_i_1__0_n_0\
);
\m_payload_i[50]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_arid(0),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[50]\,
O => \m_payload_i[50]_i_1__0_n_0\
);
\m_payload_i[51]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_arid(1),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[51]\,
O => \m_payload_i[51]_i_1__0_n_0\
);
\m_payload_i[52]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_arid(2),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[52]\,
O => \m_payload_i[52]_i_1__0_n_0\
);
\m_payload_i[53]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_arid(3),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[53]\,
O => \m_payload_i[53]_i_1__0_n_0\
);
\m_payload_i[54]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_arid(4),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[54]\,
O => \m_payload_i[54]_i_1__0_n_0\
);
\m_payload_i[55]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_arid(5),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[55]\,
O => \m_payload_i[55]_i_1__0_n_0\
);
\m_payload_i[56]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_arid(6),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[56]\,
O => \m_payload_i[56]_i_1__0_n_0\
);
\m_payload_i[57]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_arid(7),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[57]\,
O => \m_payload_i[57]_i_1__0_n_0\
);
\m_payload_i[58]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_arid(8),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[58]\,
O => \m_payload_i[58]_i_1__0_n_0\
);
\m_payload_i[59]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_arid(9),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[59]\,
O => \m_payload_i[59]_i_1__0_n_0\
);
\m_payload_i[5]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(5),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[5]\,
O => \m_payload_i[5]_i_1__0_n_0\
);
\m_payload_i[60]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_arid(10),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[60]\,
O => \m_payload_i[60]_i_1__0_n_0\
);
\m_payload_i[61]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_arid(11),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[61]\,
O => \m_payload_i[61]_i_1__0_n_0\
);
\m_payload_i[6]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(6),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[6]\,
O => \m_payload_i[6]_i_1__0_n_0\
);
\m_payload_i[7]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(7),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[7]\,
O => \m_payload_i[7]_i_1__0_n_0\
);
\m_payload_i[8]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(8),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[8]\,
O => \m_payload_i[8]_i_1__0_n_0\
);
\m_payload_i[9]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(9),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[9]\,
O => \m_payload_i[9]_i_1__0_n_0\
);
\m_payload_i_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[0]_i_1__0_n_0\,
Q => \^q\(0),
R => '0'
);
\m_payload_i_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[10]_i_1__0_n_0\,
Q => \^q\(10),
R => '0'
);
\m_payload_i_reg[11]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[11]_i_1__0_n_0\,
Q => \^q\(11),
R => '0'
);
\m_payload_i_reg[12]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[12]_i_1__0_n_0\,
Q => \^q\(12),
R => '0'
);
\m_payload_i_reg[13]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[13]_i_1__1_n_0\,
Q => \^q\(13),
R => '0'
);
\m_payload_i_reg[14]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[14]_i_1__0_n_0\,
Q => \^q\(14),
R => '0'
);
\m_payload_i_reg[15]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[15]_i_1__0_n_0\,
Q => \^q\(15),
R => '0'
);
\m_payload_i_reg[16]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[16]_i_1__0_n_0\,
Q => \^q\(16),
R => '0'
);
\m_payload_i_reg[17]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[17]_i_1__0_n_0\,
Q => \^q\(17),
R => '0'
);
\m_payload_i_reg[18]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[18]_i_1__0_n_0\,
Q => \^q\(18),
R => '0'
);
\m_payload_i_reg[19]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[19]_i_1__0_n_0\,
Q => \^q\(19),
R => '0'
);
\m_payload_i_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[1]_i_1__0_n_0\,
Q => \^q\(1),
R => '0'
);
\m_payload_i_reg[20]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[20]_i_1__0_n_0\,
Q => \^q\(20),
R => '0'
);
\m_payload_i_reg[21]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[21]_i_1__0_n_0\,
Q => \^q\(21),
R => '0'
);
\m_payload_i_reg[22]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[22]_i_1__0_n_0\,
Q => \^q\(22),
R => '0'
);
\m_payload_i_reg[23]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[23]_i_1__0_n_0\,
Q => \^q\(23),
R => '0'
);
\m_payload_i_reg[24]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[24]_i_1__0_n_0\,
Q => \^q\(24),
R => '0'
);
\m_payload_i_reg[25]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[25]_i_1__0_n_0\,
Q => \^q\(25),
R => '0'
);
\m_payload_i_reg[26]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[26]_i_1__0_n_0\,
Q => \^q\(26),
R => '0'
);
\m_payload_i_reg[27]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[27]_i_1__0_n_0\,
Q => \^q\(27),
R => '0'
);
\m_payload_i_reg[28]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[28]_i_1__0_n_0\,
Q => \^q\(28),
R => '0'
);
\m_payload_i_reg[29]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[29]_i_1__0_n_0\,
Q => \^q\(29),
R => '0'
);
\m_payload_i_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[2]_i_1__0_n_0\,
Q => \^q\(2),
R => '0'
);
\m_payload_i_reg[30]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[30]_i_1__0_n_0\,
Q => \^q\(30),
R => '0'
);
\m_payload_i_reg[31]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[31]_i_2__0_n_0\,
Q => \^q\(31),
R => '0'
);
\m_payload_i_reg[32]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[32]_i_1__0_n_0\,
Q => \^q\(32),
R => '0'
);
\m_payload_i_reg[33]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[33]_i_1__0_n_0\,
Q => \^q\(33),
R => '0'
);
\m_payload_i_reg[34]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[34]_i_1__0_n_0\,
Q => \^q\(34),
R => '0'
);
\m_payload_i_reg[35]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[35]_i_1__0_n_0\,
Q => \^q\(35),
R => '0'
);
\m_payload_i_reg[36]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[36]_i_1__0_n_0\,
Q => \^q\(36),
R => '0'
);
\m_payload_i_reg[38]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[38]_i_1__0_n_0\,
Q => \^q\(37),
R => '0'
);
\m_payload_i_reg[39]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[39]_i_1__0_n_0\,
Q => \^q\(38),
R => '0'
);
\m_payload_i_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[3]_i_1__0_n_0\,
Q => \^q\(3),
R => '0'
);
\m_payload_i_reg[44]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[44]_i_1__0_n_0\,
Q => \^q\(39),
R => '0'
);
\m_payload_i_reg[45]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[45]_i_1__0_n_0\,
Q => \^q\(40),
R => '0'
);
\m_payload_i_reg[46]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[46]_i_1__1_n_0\,
Q => \^q\(41),
R => '0'
);
\m_payload_i_reg[47]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[47]_i_1__0_n_0\,
Q => \^q\(42),
R => '0'
);
\m_payload_i_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[4]_i_1__0_n_0\,
Q => \^q\(4),
R => '0'
);
\m_payload_i_reg[50]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[50]_i_1__0_n_0\,
Q => \^q\(43),
R => '0'
);
\m_payload_i_reg[51]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[51]_i_1__0_n_0\,
Q => \^q\(44),
R => '0'
);
\m_payload_i_reg[52]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[52]_i_1__0_n_0\,
Q => \^q\(45),
R => '0'
);
\m_payload_i_reg[53]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[53]_i_1__0_n_0\,
Q => \^q\(46),
R => '0'
);
\m_payload_i_reg[54]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[54]_i_1__0_n_0\,
Q => \^q\(47),
R => '0'
);
\m_payload_i_reg[55]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[55]_i_1__0_n_0\,
Q => \^q\(48),
R => '0'
);
\m_payload_i_reg[56]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[56]_i_1__0_n_0\,
Q => \^q\(49),
R => '0'
);
\m_payload_i_reg[57]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[57]_i_1__0_n_0\,
Q => \^q\(50),
R => '0'
);
\m_payload_i_reg[58]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[58]_i_1__0_n_0\,
Q => \^q\(51),
R => '0'
);
\m_payload_i_reg[59]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[59]_i_1__0_n_0\,
Q => \^q\(52),
R => '0'
);
\m_payload_i_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[5]_i_1__0_n_0\,
Q => \^q\(5),
R => '0'
);
\m_payload_i_reg[60]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[60]_i_1__0_n_0\,
Q => \^q\(53),
R => '0'
);
\m_payload_i_reg[61]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[61]_i_1__0_n_0\,
Q => \^q\(54),
R => '0'
);
\m_payload_i_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[6]_i_1__0_n_0\,
Q => \^q\(6),
R => '0'
);
\m_payload_i_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[7]_i_1__0_n_0\,
Q => \^q\(7),
R => '0'
);
\m_payload_i_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[8]_i_1__0_n_0\,
Q => \^q\(8),
R => '0'
);
\m_payload_i_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[9]_i_1__0_n_0\,
Q => \^q\(9),
R => '0'
);
m_valid_i_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => m_valid_i0,
Q => \^axaddr_offset_r_reg[3]\,
R => \^m_valid_i_reg_0\
);
next_pending_r_i_3: unisim.vcomponents.LUT5
generic map(
INIT => X"AAAAAAA8"
)
port map (
I0 => \state_reg[1]_rep\,
I1 => \^q\(42),
I2 => \^q\(40),
I3 => \^q\(39),
I4 => \^q\(41),
O => next_pending_r_reg
);
s_ready_i_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => s_ready_i0,
Q => \^s_axi_arready\,
R => \aresetn_d_reg[0]\
);
\skid_buffer_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(0),
Q => \skid_buffer_reg_n_0_[0]\,
R => '0'
);
\skid_buffer_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(10),
Q => \skid_buffer_reg_n_0_[10]\,
R => '0'
);
\skid_buffer_reg[11]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(11),
Q => \skid_buffer_reg_n_0_[11]\,
R => '0'
);
\skid_buffer_reg[12]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(12),
Q => \skid_buffer_reg_n_0_[12]\,
R => '0'
);
\skid_buffer_reg[13]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(13),
Q => \skid_buffer_reg_n_0_[13]\,
R => '0'
);
\skid_buffer_reg[14]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(14),
Q => \skid_buffer_reg_n_0_[14]\,
R => '0'
);
\skid_buffer_reg[15]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(15),
Q => \skid_buffer_reg_n_0_[15]\,
R => '0'
);
\skid_buffer_reg[16]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(16),
Q => \skid_buffer_reg_n_0_[16]\,
R => '0'
);
\skid_buffer_reg[17]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(17),
Q => \skid_buffer_reg_n_0_[17]\,
R => '0'
);
\skid_buffer_reg[18]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(18),
Q => \skid_buffer_reg_n_0_[18]\,
R => '0'
);
\skid_buffer_reg[19]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(19),
Q => \skid_buffer_reg_n_0_[19]\,
R => '0'
);
\skid_buffer_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(1),
Q => \skid_buffer_reg_n_0_[1]\,
R => '0'
);
\skid_buffer_reg[20]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(20),
Q => \skid_buffer_reg_n_0_[20]\,
R => '0'
);
\skid_buffer_reg[21]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(21),
Q => \skid_buffer_reg_n_0_[21]\,
R => '0'
);
\skid_buffer_reg[22]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(22),
Q => \skid_buffer_reg_n_0_[22]\,
R => '0'
);
\skid_buffer_reg[23]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(23),
Q => \skid_buffer_reg_n_0_[23]\,
R => '0'
);
\skid_buffer_reg[24]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(24),
Q => \skid_buffer_reg_n_0_[24]\,
R => '0'
);
\skid_buffer_reg[25]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(25),
Q => \skid_buffer_reg_n_0_[25]\,
R => '0'
);
\skid_buffer_reg[26]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(26),
Q => \skid_buffer_reg_n_0_[26]\,
R => '0'
);
\skid_buffer_reg[27]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(27),
Q => \skid_buffer_reg_n_0_[27]\,
R => '0'
);
\skid_buffer_reg[28]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(28),
Q => \skid_buffer_reg_n_0_[28]\,
R => '0'
);
\skid_buffer_reg[29]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(29),
Q => \skid_buffer_reg_n_0_[29]\,
R => '0'
);
\skid_buffer_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(2),
Q => \skid_buffer_reg_n_0_[2]\,
R => '0'
);
\skid_buffer_reg[30]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(30),
Q => \skid_buffer_reg_n_0_[30]\,
R => '0'
);
\skid_buffer_reg[31]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(31),
Q => \skid_buffer_reg_n_0_[31]\,
R => '0'
);
\skid_buffer_reg[32]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_arprot(0),
Q => \skid_buffer_reg_n_0_[32]\,
R => '0'
);
\skid_buffer_reg[33]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_arprot(1),
Q => \skid_buffer_reg_n_0_[33]\,
R => '0'
);
\skid_buffer_reg[34]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_arprot(2),
Q => \skid_buffer_reg_n_0_[34]\,
R => '0'
);
\skid_buffer_reg[35]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_arsize(0),
Q => \skid_buffer_reg_n_0_[35]\,
R => '0'
);
\skid_buffer_reg[36]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_arsize(1),
Q => \skid_buffer_reg_n_0_[36]\,
R => '0'
);
\skid_buffer_reg[38]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_arburst(0),
Q => \skid_buffer_reg_n_0_[38]\,
R => '0'
);
\skid_buffer_reg[39]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_arburst(1),
Q => \skid_buffer_reg_n_0_[39]\,
R => '0'
);
\skid_buffer_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(3),
Q => \skid_buffer_reg_n_0_[3]\,
R => '0'
);
\skid_buffer_reg[44]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_arlen(0),
Q => \skid_buffer_reg_n_0_[44]\,
R => '0'
);
\skid_buffer_reg[45]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_arlen(1),
Q => \skid_buffer_reg_n_0_[45]\,
R => '0'
);
\skid_buffer_reg[46]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_arlen(2),
Q => \skid_buffer_reg_n_0_[46]\,
R => '0'
);
\skid_buffer_reg[47]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_arlen(3),
Q => \skid_buffer_reg_n_0_[47]\,
R => '0'
);
\skid_buffer_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(4),
Q => \skid_buffer_reg_n_0_[4]\,
R => '0'
);
\skid_buffer_reg[50]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_arid(0),
Q => \skid_buffer_reg_n_0_[50]\,
R => '0'
);
\skid_buffer_reg[51]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_arid(1),
Q => \skid_buffer_reg_n_0_[51]\,
R => '0'
);
\skid_buffer_reg[52]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_arid(2),
Q => \skid_buffer_reg_n_0_[52]\,
R => '0'
);
\skid_buffer_reg[53]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_arid(3),
Q => \skid_buffer_reg_n_0_[53]\,
R => '0'
);
\skid_buffer_reg[54]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_arid(4),
Q => \skid_buffer_reg_n_0_[54]\,
R => '0'
);
\skid_buffer_reg[55]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_arid(5),
Q => \skid_buffer_reg_n_0_[55]\,
R => '0'
);
\skid_buffer_reg[56]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_arid(6),
Q => \skid_buffer_reg_n_0_[56]\,
R => '0'
);
\skid_buffer_reg[57]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_arid(7),
Q => \skid_buffer_reg_n_0_[57]\,
R => '0'
);
\skid_buffer_reg[58]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_arid(8),
Q => \skid_buffer_reg_n_0_[58]\,
R => '0'
);
\skid_buffer_reg[59]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_arid(9),
Q => \skid_buffer_reg_n_0_[59]\,
R => '0'
);
\skid_buffer_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(5),
Q => \skid_buffer_reg_n_0_[5]\,
R => '0'
);
\skid_buffer_reg[60]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_arid(10),
Q => \skid_buffer_reg_n_0_[60]\,
R => '0'
);
\skid_buffer_reg[61]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_arid(11),
Q => \skid_buffer_reg_n_0_[61]\,
R => '0'
);
\skid_buffer_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(6),
Q => \skid_buffer_reg_n_0_[6]\,
R => '0'
);
\skid_buffer_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(7),
Q => \skid_buffer_reg_n_0_[7]\,
R => '0'
);
\skid_buffer_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(8),
Q => \skid_buffer_reg_n_0_[8]\,
R => '0'
);
\skid_buffer_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(9),
Q => \skid_buffer_reg_n_0_[9]\,
R => '0'
);
\wrap_boundary_axaddr_r[0]_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"AA8A"
)
port map (
I0 => \^q\(0),
I1 => \^q\(35),
I2 => \^q\(39),
I3 => \^q\(36),
O => \wrap_boundary_axaddr_r_reg[6]\(0)
);
\wrap_boundary_axaddr_r[1]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"8A888AAA"
)
port map (
I0 => \^q\(1),
I1 => \^q\(36),
I2 => \^q\(39),
I3 => \^q\(35),
I4 => \^q\(40),
O => \wrap_boundary_axaddr_r_reg[6]\(1)
);
\wrap_boundary_axaddr_r[2]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"FF0F553300000000"
)
port map (
I0 => \^q\(40),
I1 => \^q\(41),
I2 => \^q\(39),
I3 => \^q\(35),
I4 => \^q\(36),
I5 => \^q\(2),
O => \wrap_boundary_axaddr_r_reg[6]\(2)
);
\wrap_boundary_axaddr_r[3]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"020202A2A2A202A2"
)
port map (
I0 => \^q\(3),
I1 => \wrap_boundary_axaddr_r[3]_i_2__0_n_0\,
I2 => \^q\(36),
I3 => \^q\(40),
I4 => \^q\(35),
I5 => \^q\(39),
O => \wrap_boundary_axaddr_r_reg[6]\(3)
);
\wrap_boundary_axaddr_r[3]_i_2__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \^q\(41),
I1 => \^q\(35),
I2 => \^q\(42),
O => \wrap_boundary_axaddr_r[3]_i_2__0_n_0\
);
\wrap_boundary_axaddr_r[4]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"503F5F3F00000000"
)
port map (
I0 => \^q\(40),
I1 => \^q\(41),
I2 => \^q\(36),
I3 => \^q\(35),
I4 => \^q\(42),
I5 => \^q\(4),
O => \wrap_boundary_axaddr_r_reg[6]\(4)
);
\wrap_boundary_axaddr_r[5]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"2A222AAA"
)
port map (
I0 => \^q\(5),
I1 => \^q\(36),
I2 => \^q\(41),
I3 => \^q\(35),
I4 => \^q\(42),
O => \wrap_boundary_axaddr_r_reg[6]\(5)
);
\wrap_boundary_axaddr_r[6]_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"2AAA"
)
port map (
I0 => \^q\(6),
I1 => \^q\(42),
I2 => \^q\(35),
I3 => \^q\(36),
O => \wrap_boundary_axaddr_r_reg[6]\(6)
);
\wrap_cnt_r[2]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAA6AA56AAAAAAAA"
)
port map (
I0 => \^wrap_second_len_r_reg[3]\(1),
I1 => \wrap_second_len_r_reg[3]_0\(0),
I2 => \state_reg[1]_rep\,
I3 => \^wrap_cnt_r_reg[2]\,
I4 => \^axaddr_offset_r_reg[0]\,
I5 => \^wrap_second_len_r_reg[3]\(0),
O => \wrap_cnt_r_reg[3]\(0)
);
\wrap_cnt_r[3]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"6A"
)
port map (
I0 => \^wrap_second_len_r_reg[3]\(2),
I1 => \wrap_second_len_r_reg[1]\,
I2 => \^wrap_second_len_r_reg[3]\(1),
O => \wrap_cnt_r_reg[3]\(1)
);
\wrap_cnt_r[3]_i_3__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFEAEAFFEA"
)
port map (
I0 => \axaddr_offset_r_reg[3]_1\,
I1 => \^axlen_cnt_reg[3]\,
I2 => \axaddr_offset_r[3]_i_2__0_n_0\,
I3 => \^axaddr_offset_r_reg[2]\,
I4 => \wrap_cnt_r[3]_i_5__0_n_0\,
I5 => \axaddr_offset_r_reg[2]_1\,
O => \wrap_cnt_r_reg[3]_0\
);
\wrap_cnt_r[3]_i_5__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFDF"
)
port map (
I0 => \^q\(41),
I1 => \state_reg[0]_rep\,
I2 => \^axaddr_offset_r_reg[3]\,
I3 => \state_reg[1]_rep_0\,
O => \wrap_cnt_r[3]_i_5__0_n_0\
);
\wrap_second_len_r[0]_i_2__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"0001000000010001"
)
port map (
I0 => \^axaddr_offset_r_reg[0]\,
I1 => \^axaddr_offset_0\(0),
I2 => \axaddr_offset_r_reg[2]_0\(0),
I3 => \wrap_second_len_r[3]_i_2__0_n_0\,
I4 => \state_reg[1]_rep\,
I5 => \axaddr_offset_r_reg[3]_0\(2),
O => \^wrap_cnt_r_reg[2]\
);
\wrap_second_len_r[1]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"F00EFFFFF00E0000"
)
port map (
I0 => \^axaddr_offset_0\(1),
I1 => \axaddr_offset_r_reg[2]_0\(0),
I2 => \^axaddr_offset_r_reg[0]\,
I3 => \^axaddr_offset_0\(0),
I4 => \state_reg[1]_rep\,
I5 => \wrap_second_len_r_reg[3]_0\(1),
O => \^wrap_second_len_r_reg[3]\(0)
);
\wrap_second_len_r[2]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"CCC2FFFFCCC20000"
)
port map (
I0 => \^axaddr_offset_0\(1),
I1 => \axaddr_offset_r_reg[2]_0\(0),
I2 => \^axaddr_offset_0\(0),
I3 => \^axaddr_offset_r_reg[0]\,
I4 => \state_reg[1]_rep\,
I5 => \wrap_second_len_r_reg[3]_0\(2),
O => \^wrap_second_len_r_reg[3]\(1)
);
\wrap_second_len_r[3]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"FE00FFFFFE00FE00"
)
port map (
I0 => \^axaddr_offset_r_reg[0]\,
I1 => \^axaddr_offset_0\(0),
I2 => \axaddr_offset_r_reg[2]_0\(0),
I3 => \wrap_second_len_r[3]_i_2__0_n_0\,
I4 => \state_reg[1]_rep\,
I5 => \wrap_second_len_r_reg[3]_0\(3),
O => \^wrap_second_len_r_reg[3]\(2)
);
\wrap_second_len_r[3]_i_2__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"A8A8A8080808A808"
)
port map (
I0 => \^axlen_cnt_reg[3]\,
I1 => \wrap_second_len_r[3]_i_3__0_n_0\,
I2 => \^q\(36),
I3 => \^q\(5),
I4 => \^q\(35),
I5 => \^q\(6),
O => \wrap_second_len_r[3]_i_2__0_n_0\
);
\wrap_second_len_r[3]_i_3__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \^q\(4),
I1 => \^q\(35),
I2 => \^q\(3),
O => \wrap_second_len_r[3]_i_3__0_n_0\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity zybo_zynq_design_auto_pc_0_axi_register_slice_v2_1_17_axic_register_slice_0 is
port (
s_axi_awready : out STD_LOGIC;
s_ready_i_reg_0 : out STD_LOGIC;
m_valid_i_reg_0 : out STD_LOGIC;
\axlen_cnt_reg[3]\ : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 54 downto 0 );
axaddr_incr : out STD_LOGIC_VECTOR ( 11 downto 0 );
D : out STD_LOGIC_VECTOR ( 1 downto 0 );
\wrap_second_len_r_reg[3]\ : out STD_LOGIC_VECTOR ( 2 downto 0 );
\wrap_cnt_r_reg[2]\ : out STD_LOGIC;
\axaddr_offset_r_reg[0]\ : out STD_LOGIC;
axaddr_offset : out STD_LOGIC_VECTOR ( 1 downto 0 );
\wrap_cnt_r_reg[3]\ : out STD_LOGIC;
\axaddr_offset_r_reg[2]\ : out STD_LOGIC;
next_pending_r_reg : out STD_LOGIC;
\wrap_boundary_axaddr_r_reg[6]\ : out STD_LOGIC_VECTOR ( 6 downto 0 );
\aresetn_d_reg[1]_inv\ : out STD_LOGIC;
aclk : in STD_LOGIC;
\aresetn_d_reg[1]_inv_0\ : in STD_LOGIC;
aresetn : in STD_LOGIC;
\state_reg[1]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
S : in STD_LOGIC_VECTOR ( 3 downto 0 );
\wrap_second_len_r_reg[3]_0\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\state_reg[1]_rep\ : in STD_LOGIC;
\wrap_second_len_r_reg[1]\ : in STD_LOGIC;
\axaddr_offset_r_reg[2]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\axaddr_offset_r_reg[3]\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
\axaddr_offset_r_reg[3]_0\ : in STD_LOGIC;
\axaddr_offset_r_reg[2]_1\ : in STD_LOGIC;
\state_reg[0]_rep\ : in STD_LOGIC;
\state_reg[1]_rep_0\ : in STD_LOGIC;
s_axi_awvalid : in STD_LOGIC;
b_push : in STD_LOGIC;
s_axi_awid : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_awlen : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awsize : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
E : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of zybo_zynq_design_auto_pc_0_axi_register_slice_v2_1_17_axic_register_slice_0 : entity is "axi_register_slice_v2_1_17_axic_register_slice";
end zybo_zynq_design_auto_pc_0_axi_register_slice_v2_1_17_axic_register_slice_0;
architecture STRUCTURE of zybo_zynq_design_auto_pc_0_axi_register_slice_v2_1_17_axic_register_slice_0 is
signal \^q\ : STD_LOGIC_VECTOR ( 54 downto 0 );
signal \aresetn_d_reg_n_0_[0]\ : STD_LOGIC;
signal \axaddr_incr[3]_i_4_n_0\ : STD_LOGIC;
signal \axaddr_incr[3]_i_5_n_0\ : STD_LOGIC;
signal \axaddr_incr[3]_i_6_n_0\ : STD_LOGIC;
signal \axaddr_incr_reg[11]_i_3_n_1\ : STD_LOGIC;
signal \axaddr_incr_reg[11]_i_3_n_2\ : STD_LOGIC;
signal \axaddr_incr_reg[11]_i_3_n_3\ : STD_LOGIC;
signal \axaddr_incr_reg[3]_i_2_n_0\ : STD_LOGIC;
signal \axaddr_incr_reg[3]_i_2_n_1\ : STD_LOGIC;
signal \axaddr_incr_reg[3]_i_2_n_2\ : STD_LOGIC;
signal \axaddr_incr_reg[3]_i_2_n_3\ : STD_LOGIC;
signal \axaddr_incr_reg[7]_i_2_n_0\ : STD_LOGIC;
signal \axaddr_incr_reg[7]_i_2_n_1\ : STD_LOGIC;
signal \axaddr_incr_reg[7]_i_2_n_2\ : STD_LOGIC;
signal \axaddr_incr_reg[7]_i_2_n_3\ : STD_LOGIC;
signal \^axaddr_offset\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \axaddr_offset_r[0]_i_2_n_0\ : STD_LOGIC;
signal \axaddr_offset_r[1]_i_2_n_0\ : STD_LOGIC;
signal \axaddr_offset_r[3]_i_2_n_0\ : STD_LOGIC;
signal \^axaddr_offset_r_reg[0]\ : STD_LOGIC;
signal \^axaddr_offset_r_reg[2]\ : STD_LOGIC;
signal \^axlen_cnt_reg[3]\ : STD_LOGIC;
signal m_valid_i0 : STD_LOGIC;
signal \^m_valid_i_reg_0\ : STD_LOGIC;
signal \^s_axi_awready\ : STD_LOGIC;
signal s_ready_i0 : STD_LOGIC;
signal \^s_ready_i_reg_0\ : STD_LOGIC;
signal skid_buffer : STD_LOGIC_VECTOR ( 61 downto 0 );
signal \skid_buffer_reg_n_0_[0]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[10]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[11]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[12]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[13]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[14]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[15]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[16]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[17]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[18]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[19]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[1]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[20]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[21]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[22]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[23]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[24]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[25]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[26]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[27]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[28]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[29]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[2]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[30]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[31]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[32]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[33]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[34]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[35]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[36]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[38]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[39]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[3]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[44]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[45]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[46]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[47]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[4]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[50]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[51]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[52]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[53]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[54]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[55]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[56]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[57]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[58]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[59]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[5]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[60]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[61]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[6]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[7]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[8]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[9]\ : STD_LOGIC;
signal \wrap_boundary_axaddr_r[3]_i_2_n_0\ : STD_LOGIC;
signal \wrap_cnt_r[3]_i_5_n_0\ : STD_LOGIC;
signal \^wrap_cnt_r_reg[2]\ : STD_LOGIC;
signal \wrap_second_len_r[3]_i_2_n_0\ : STD_LOGIC;
signal \wrap_second_len_r[3]_i_3_n_0\ : STD_LOGIC;
signal \^wrap_second_len_r_reg[3]\ : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \NLW_axaddr_incr_reg[11]_i_3_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \m_payload_i[10]_i_1\ : label is "soft_lutpair72";
attribute SOFT_HLUTNM of \m_payload_i[11]_i_1\ : label is "soft_lutpair71";
attribute SOFT_HLUTNM of \m_payload_i[12]_i_1\ : label is "soft_lutpair71";
attribute SOFT_HLUTNM of \m_payload_i[13]_i_1__0\ : label is "soft_lutpair70";
attribute SOFT_HLUTNM of \m_payload_i[14]_i_1\ : label is "soft_lutpair70";
attribute SOFT_HLUTNM of \m_payload_i[15]_i_1\ : label is "soft_lutpair69";
attribute SOFT_HLUTNM of \m_payload_i[16]_i_1\ : label is "soft_lutpair69";
attribute SOFT_HLUTNM of \m_payload_i[17]_i_1\ : label is "soft_lutpair68";
attribute SOFT_HLUTNM of \m_payload_i[18]_i_1\ : label is "soft_lutpair68";
attribute SOFT_HLUTNM of \m_payload_i[19]_i_1\ : label is "soft_lutpair67";
attribute SOFT_HLUTNM of \m_payload_i[1]_i_1\ : label is "soft_lutpair76";
attribute SOFT_HLUTNM of \m_payload_i[20]_i_1\ : label is "soft_lutpair67";
attribute SOFT_HLUTNM of \m_payload_i[21]_i_1\ : label is "soft_lutpair66";
attribute SOFT_HLUTNM of \m_payload_i[22]_i_1\ : label is "soft_lutpair66";
attribute SOFT_HLUTNM of \m_payload_i[23]_i_1\ : label is "soft_lutpair65";
attribute SOFT_HLUTNM of \m_payload_i[24]_i_1\ : label is "soft_lutpair65";
attribute SOFT_HLUTNM of \m_payload_i[25]_i_1\ : label is "soft_lutpair64";
attribute SOFT_HLUTNM of \m_payload_i[26]_i_1\ : label is "soft_lutpair64";
attribute SOFT_HLUTNM of \m_payload_i[27]_i_1\ : label is "soft_lutpair63";
attribute SOFT_HLUTNM of \m_payload_i[28]_i_1\ : label is "soft_lutpair63";
attribute SOFT_HLUTNM of \m_payload_i[29]_i_1\ : label is "soft_lutpair62";
attribute SOFT_HLUTNM of \m_payload_i[2]_i_1\ : label is "soft_lutpair76";
attribute SOFT_HLUTNM of \m_payload_i[30]_i_1\ : label is "soft_lutpair62";
attribute SOFT_HLUTNM of \m_payload_i[31]_i_2\ : label is "soft_lutpair61";
attribute SOFT_HLUTNM of \m_payload_i[32]_i_1\ : label is "soft_lutpair61";
attribute SOFT_HLUTNM of \m_payload_i[33]_i_1\ : label is "soft_lutpair60";
attribute SOFT_HLUTNM of \m_payload_i[34]_i_1\ : label is "soft_lutpair60";
attribute SOFT_HLUTNM of \m_payload_i[35]_i_1\ : label is "soft_lutpair59";
attribute SOFT_HLUTNM of \m_payload_i[36]_i_1\ : label is "soft_lutpair59";
attribute SOFT_HLUTNM of \m_payload_i[38]_i_1\ : label is "soft_lutpair58";
attribute SOFT_HLUTNM of \m_payload_i[39]_i_1\ : label is "soft_lutpair58";
attribute SOFT_HLUTNM of \m_payload_i[3]_i_1\ : label is "soft_lutpair75";
attribute SOFT_HLUTNM of \m_payload_i[44]_i_1\ : label is "soft_lutpair57";
attribute SOFT_HLUTNM of \m_payload_i[45]_i_1\ : label is "soft_lutpair57";
attribute SOFT_HLUTNM of \m_payload_i[46]_i_1__0\ : label is "soft_lutpair56";
attribute SOFT_HLUTNM of \m_payload_i[47]_i_1\ : label is "soft_lutpair56";
attribute SOFT_HLUTNM of \m_payload_i[4]_i_1\ : label is "soft_lutpair75";
attribute SOFT_HLUTNM of \m_payload_i[50]_i_1\ : label is "soft_lutpair55";
attribute SOFT_HLUTNM of \m_payload_i[51]_i_1\ : label is "soft_lutpair55";
attribute SOFT_HLUTNM of \m_payload_i[52]_i_1\ : label is "soft_lutpair54";
attribute SOFT_HLUTNM of \m_payload_i[53]_i_1\ : label is "soft_lutpair54";
attribute SOFT_HLUTNM of \m_payload_i[54]_i_1\ : label is "soft_lutpair53";
attribute SOFT_HLUTNM of \m_payload_i[55]_i_1\ : label is "soft_lutpair53";
attribute SOFT_HLUTNM of \m_payload_i[56]_i_1\ : label is "soft_lutpair52";
attribute SOFT_HLUTNM of \m_payload_i[57]_i_1\ : label is "soft_lutpair52";
attribute SOFT_HLUTNM of \m_payload_i[58]_i_1\ : label is "soft_lutpair51";
attribute SOFT_HLUTNM of \m_payload_i[59]_i_1\ : label is "soft_lutpair51";
attribute SOFT_HLUTNM of \m_payload_i[5]_i_1\ : label is "soft_lutpair74";
attribute SOFT_HLUTNM of \m_payload_i[60]_i_1\ : label is "soft_lutpair50";
attribute SOFT_HLUTNM of \m_payload_i[61]_i_1\ : label is "soft_lutpair50";
attribute SOFT_HLUTNM of \m_payload_i[6]_i_1\ : label is "soft_lutpair74";
attribute SOFT_HLUTNM of \m_payload_i[7]_i_1\ : label is "soft_lutpair73";
attribute SOFT_HLUTNM of \m_payload_i[8]_i_1\ : label is "soft_lutpair73";
attribute SOFT_HLUTNM of \m_payload_i[9]_i_1\ : label is "soft_lutpair72";
attribute SOFT_HLUTNM of \wrap_boundary_axaddr_r[3]_i_2\ : label is "soft_lutpair49";
attribute SOFT_HLUTNM of \wrap_boundary_axaddr_r[5]_i_1\ : label is "soft_lutpair49";
begin
Q(54 downto 0) <= \^q\(54 downto 0);
axaddr_offset(1 downto 0) <= \^axaddr_offset\(1 downto 0);
\axaddr_offset_r_reg[0]\ <= \^axaddr_offset_r_reg[0]\;
\axaddr_offset_r_reg[2]\ <= \^axaddr_offset_r_reg[2]\;
\axlen_cnt_reg[3]\ <= \^axlen_cnt_reg[3]\;
m_valid_i_reg_0 <= \^m_valid_i_reg_0\;
s_axi_awready <= \^s_axi_awready\;
s_ready_i_reg_0 <= \^s_ready_i_reg_0\;
\wrap_cnt_r_reg[2]\ <= \^wrap_cnt_r_reg[2]\;
\wrap_second_len_r_reg[3]\(2 downto 0) <= \^wrap_second_len_r_reg[3]\(2 downto 0);
\aresetn_d[1]_inv_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"7"
)
port map (
I0 => \aresetn_d_reg_n_0_[0]\,
I1 => aresetn,
O => \aresetn_d_reg[1]_inv\
);
\aresetn_d_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => aresetn,
Q => \aresetn_d_reg_n_0_[0]\,
R => '0'
);
\axaddr_incr[3]_i_4\: unisim.vcomponents.LUT3
generic map(
INIT => X"2A"
)
port map (
I0 => \^q\(2),
I1 => \^q\(35),
I2 => \^q\(36),
O => \axaddr_incr[3]_i_4_n_0\
);
\axaddr_incr[3]_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \^q\(1),
I1 => \^q\(36),
O => \axaddr_incr[3]_i_5_n_0\
);
\axaddr_incr[3]_i_6\: unisim.vcomponents.LUT3
generic map(
INIT => X"02"
)
port map (
I0 => \^q\(0),
I1 => \^q\(35),
I2 => \^q\(36),
O => \axaddr_incr[3]_i_6_n_0\
);
\axaddr_incr_reg[11]_i_3\: unisim.vcomponents.CARRY4
port map (
CI => \axaddr_incr_reg[7]_i_2_n_0\,
CO(3) => \NLW_axaddr_incr_reg[11]_i_3_CO_UNCONNECTED\(3),
CO(2) => \axaddr_incr_reg[11]_i_3_n_1\,
CO(1) => \axaddr_incr_reg[11]_i_3_n_2\,
CO(0) => \axaddr_incr_reg[11]_i_3_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 0) => axaddr_incr(11 downto 8),
S(3 downto 0) => \^q\(11 downto 8)
);
\axaddr_incr_reg[3]_i_2\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \axaddr_incr_reg[3]_i_2_n_0\,
CO(2) => \axaddr_incr_reg[3]_i_2_n_1\,
CO(1) => \axaddr_incr_reg[3]_i_2_n_2\,
CO(0) => \axaddr_incr_reg[3]_i_2_n_3\,
CYINIT => '0',
DI(3) => \^q\(3),
DI(2) => \axaddr_incr[3]_i_4_n_0\,
DI(1) => \axaddr_incr[3]_i_5_n_0\,
DI(0) => \axaddr_incr[3]_i_6_n_0\,
O(3 downto 0) => axaddr_incr(3 downto 0),
S(3 downto 0) => S(3 downto 0)
);
\axaddr_incr_reg[7]_i_2\: unisim.vcomponents.CARRY4
port map (
CI => \axaddr_incr_reg[3]_i_2_n_0\,
CO(3) => \axaddr_incr_reg[7]_i_2_n_0\,
CO(2) => \axaddr_incr_reg[7]_i_2_n_1\,
CO(1) => \axaddr_incr_reg[7]_i_2_n_2\,
CO(0) => \axaddr_incr_reg[7]_i_2_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 0) => axaddr_incr(7 downto 4),
S(3 downto 0) => \^q\(7 downto 4)
);
\axaddr_offset_r[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFF8FF00000800"
)
port map (
I0 => \axaddr_offset_r[0]_i_2_n_0\,
I1 => \^q\(39),
I2 => \state_reg[1]\(1),
I3 => \^m_valid_i_reg_0\,
I4 => \state_reg[1]\(0),
I5 => \axaddr_offset_r_reg[3]\(0),
O => \^axaddr_offset_r_reg[0]\
);
\axaddr_offset_r[0]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \^q\(3),
I1 => \^q\(2),
I2 => \^q\(36),
I3 => \^q\(1),
I4 => \^q\(35),
I5 => \^q\(0),
O => \axaddr_offset_r[0]_i_2_n_0\
);
\axaddr_offset_r[1]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFF8FF00000800"
)
port map (
I0 => \axaddr_offset_r[1]_i_2_n_0\,
I1 => \^q\(40),
I2 => \state_reg[1]\(1),
I3 => \^m_valid_i_reg_0\,
I4 => \state_reg[1]\(0),
I5 => \axaddr_offset_r_reg[3]\(1),
O => \^axaddr_offset\(0)
);
\axaddr_offset_r[1]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \^q\(4),
I1 => \^q\(3),
I2 => \^q\(36),
I3 => \^q\(2),
I4 => \^q\(35),
I5 => \^q\(1),
O => \axaddr_offset_r[1]_i_2_n_0\
);
\axaddr_offset_r[2]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \^q\(5),
I1 => \^q\(4),
I2 => \^q\(36),
I3 => \^q\(3),
I4 => \^q\(35),
I5 => \^q\(2),
O => \^axaddr_offset_r_reg[2]\
);
\axaddr_offset_r[3]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFF8FF00000800"
)
port map (
I0 => \axaddr_offset_r[3]_i_2_n_0\,
I1 => \^q\(42),
I2 => \state_reg[1]\(1),
I3 => \^m_valid_i_reg_0\,
I4 => \state_reg[1]\(0),
I5 => \axaddr_offset_r_reg[3]\(2),
O => \^axaddr_offset\(1)
);
\axaddr_offset_r[3]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \^q\(6),
I1 => \^q\(5),
I2 => \^q\(36),
I3 => \^q\(4),
I4 => \^q\(35),
I5 => \^q\(3),
O => \axaddr_offset_r[3]_i_2_n_0\
);
\axlen_cnt[3]_i_3\: unisim.vcomponents.LUT4
generic map(
INIT => X"0020"
)
port map (
I0 => \^q\(42),
I1 => \state_reg[1]\(0),
I2 => \^m_valid_i_reg_0\,
I3 => \state_reg[1]\(1),
O => \^axlen_cnt_reg[3]\
);
\m_payload_i[0]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(0),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[0]\,
O => skid_buffer(0)
);
\m_payload_i[10]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(10),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[10]\,
O => skid_buffer(10)
);
\m_payload_i[11]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(11),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[11]\,
O => skid_buffer(11)
);
\m_payload_i[12]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(12),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[12]\,
O => skid_buffer(12)
);
\m_payload_i[13]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(13),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[13]\,
O => skid_buffer(13)
);
\m_payload_i[14]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(14),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[14]\,
O => skid_buffer(14)
);
\m_payload_i[15]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(15),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[15]\,
O => skid_buffer(15)
);
\m_payload_i[16]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(16),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[16]\,
O => skid_buffer(16)
);
\m_payload_i[17]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(17),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[17]\,
O => skid_buffer(17)
);
\m_payload_i[18]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(18),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[18]\,
O => skid_buffer(18)
);
\m_payload_i[19]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(19),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[19]\,
O => skid_buffer(19)
);
\m_payload_i[1]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(1),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[1]\,
O => skid_buffer(1)
);
\m_payload_i[20]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(20),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[20]\,
O => skid_buffer(20)
);
\m_payload_i[21]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(21),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[21]\,
O => skid_buffer(21)
);
\m_payload_i[22]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(22),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[22]\,
O => skid_buffer(22)
);
\m_payload_i[23]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(23),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[23]\,
O => skid_buffer(23)
);
\m_payload_i[24]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(24),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[24]\,
O => skid_buffer(24)
);
\m_payload_i[25]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(25),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[25]\,
O => skid_buffer(25)
);
\m_payload_i[26]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(26),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[26]\,
O => skid_buffer(26)
);
\m_payload_i[27]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(27),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[27]\,
O => skid_buffer(27)
);
\m_payload_i[28]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(28),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[28]\,
O => skid_buffer(28)
);
\m_payload_i[29]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(29),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[29]\,
O => skid_buffer(29)
);
\m_payload_i[2]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(2),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[2]\,
O => skid_buffer(2)
);
\m_payload_i[30]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(30),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[30]\,
O => skid_buffer(30)
);
\m_payload_i[31]_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(31),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[31]\,
O => skid_buffer(31)
);
\m_payload_i[32]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awprot(0),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[32]\,
O => skid_buffer(32)
);
\m_payload_i[33]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awprot(1),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[33]\,
O => skid_buffer(33)
);
\m_payload_i[34]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awprot(2),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[34]\,
O => skid_buffer(34)
);
\m_payload_i[35]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awsize(0),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[35]\,
O => skid_buffer(35)
);
\m_payload_i[36]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awsize(1),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[36]\,
O => skid_buffer(36)
);
\m_payload_i[38]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awburst(0),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[38]\,
O => skid_buffer(38)
);
\m_payload_i[39]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awburst(1),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[39]\,
O => skid_buffer(39)
);
\m_payload_i[3]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(3),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[3]\,
O => skid_buffer(3)
);
\m_payload_i[44]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awlen(0),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[44]\,
O => skid_buffer(44)
);
\m_payload_i[45]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awlen(1),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[45]\,
O => skid_buffer(45)
);
\m_payload_i[46]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awlen(2),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[46]\,
O => skid_buffer(46)
);
\m_payload_i[47]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awlen(3),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[47]\,
O => skid_buffer(47)
);
\m_payload_i[4]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(4),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[4]\,
O => skid_buffer(4)
);
\m_payload_i[50]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awid(0),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[50]\,
O => skid_buffer(50)
);
\m_payload_i[51]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awid(1),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[51]\,
O => skid_buffer(51)
);
\m_payload_i[52]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awid(2),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[52]\,
O => skid_buffer(52)
);
\m_payload_i[53]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awid(3),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[53]\,
O => skid_buffer(53)
);
\m_payload_i[54]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awid(4),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[54]\,
O => skid_buffer(54)
);
\m_payload_i[55]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awid(5),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[55]\,
O => skid_buffer(55)
);
\m_payload_i[56]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awid(6),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[56]\,
O => skid_buffer(56)
);
\m_payload_i[57]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awid(7),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[57]\,
O => skid_buffer(57)
);
\m_payload_i[58]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awid(8),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[58]\,
O => skid_buffer(58)
);
\m_payload_i[59]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awid(9),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[59]\,
O => skid_buffer(59)
);
\m_payload_i[5]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(5),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[5]\,
O => skid_buffer(5)
);
\m_payload_i[60]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awid(10),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[60]\,
O => skid_buffer(60)
);
\m_payload_i[61]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awid(11),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[61]\,
O => skid_buffer(61)
);
\m_payload_i[6]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(6),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[6]\,
O => skid_buffer(6)
);
\m_payload_i[7]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(7),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[7]\,
O => skid_buffer(7)
);
\m_payload_i[8]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(8),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[8]\,
O => skid_buffer(8)
);
\m_payload_i[9]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(9),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[9]\,
O => skid_buffer(9)
);
\m_payload_i_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(0),
Q => \^q\(0),
R => '0'
);
\m_payload_i_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(10),
Q => \^q\(10),
R => '0'
);
\m_payload_i_reg[11]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(11),
Q => \^q\(11),
R => '0'
);
\m_payload_i_reg[12]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(12),
Q => \^q\(12),
R => '0'
);
\m_payload_i_reg[13]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(13),
Q => \^q\(13),
R => '0'
);
\m_payload_i_reg[14]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(14),
Q => \^q\(14),
R => '0'
);
\m_payload_i_reg[15]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(15),
Q => \^q\(15),
R => '0'
);
\m_payload_i_reg[16]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(16),
Q => \^q\(16),
R => '0'
);
\m_payload_i_reg[17]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(17),
Q => \^q\(17),
R => '0'
);
\m_payload_i_reg[18]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(18),
Q => \^q\(18),
R => '0'
);
\m_payload_i_reg[19]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(19),
Q => \^q\(19),
R => '0'
);
\m_payload_i_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(1),
Q => \^q\(1),
R => '0'
);
\m_payload_i_reg[20]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(20),
Q => \^q\(20),
R => '0'
);
\m_payload_i_reg[21]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(21),
Q => \^q\(21),
R => '0'
);
\m_payload_i_reg[22]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(22),
Q => \^q\(22),
R => '0'
);
\m_payload_i_reg[23]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(23),
Q => \^q\(23),
R => '0'
);
\m_payload_i_reg[24]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(24),
Q => \^q\(24),
R => '0'
);
\m_payload_i_reg[25]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(25),
Q => \^q\(25),
R => '0'
);
\m_payload_i_reg[26]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(26),
Q => \^q\(26),
R => '0'
);
\m_payload_i_reg[27]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(27),
Q => \^q\(27),
R => '0'
);
\m_payload_i_reg[28]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(28),
Q => \^q\(28),
R => '0'
);
\m_payload_i_reg[29]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(29),
Q => \^q\(29),
R => '0'
);
\m_payload_i_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(2),
Q => \^q\(2),
R => '0'
);
\m_payload_i_reg[30]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(30),
Q => \^q\(30),
R => '0'
);
\m_payload_i_reg[31]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(31),
Q => \^q\(31),
R => '0'
);
\m_payload_i_reg[32]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(32),
Q => \^q\(32),
R => '0'
);
\m_payload_i_reg[33]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(33),
Q => \^q\(33),
R => '0'
);
\m_payload_i_reg[34]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(34),
Q => \^q\(34),
R => '0'
);
\m_payload_i_reg[35]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(35),
Q => \^q\(35),
R => '0'
);
\m_payload_i_reg[36]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(36),
Q => \^q\(36),
R => '0'
);
\m_payload_i_reg[38]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(38),
Q => \^q\(37),
R => '0'
);
\m_payload_i_reg[39]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(39),
Q => \^q\(38),
R => '0'
);
\m_payload_i_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(3),
Q => \^q\(3),
R => '0'
);
\m_payload_i_reg[44]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(44),
Q => \^q\(39),
R => '0'
);
\m_payload_i_reg[45]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(45),
Q => \^q\(40),
R => '0'
);
\m_payload_i_reg[46]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(46),
Q => \^q\(41),
R => '0'
);
\m_payload_i_reg[47]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(47),
Q => \^q\(42),
R => '0'
);
\m_payload_i_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(4),
Q => \^q\(4),
R => '0'
);
\m_payload_i_reg[50]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(50),
Q => \^q\(43),
R => '0'
);
\m_payload_i_reg[51]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(51),
Q => \^q\(44),
R => '0'
);
\m_payload_i_reg[52]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(52),
Q => \^q\(45),
R => '0'
);
\m_payload_i_reg[53]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(53),
Q => \^q\(46),
R => '0'
);
\m_payload_i_reg[54]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(54),
Q => \^q\(47),
R => '0'
);
\m_payload_i_reg[55]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(55),
Q => \^q\(48),
R => '0'
);
\m_payload_i_reg[56]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(56),
Q => \^q\(49),
R => '0'
);
\m_payload_i_reg[57]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(57),
Q => \^q\(50),
R => '0'
);
\m_payload_i_reg[58]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(58),
Q => \^q\(51),
R => '0'
);
\m_payload_i_reg[59]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(59),
Q => \^q\(52),
R => '0'
);
\m_payload_i_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(5),
Q => \^q\(5),
R => '0'
);
\m_payload_i_reg[60]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(60),
Q => \^q\(53),
R => '0'
);
\m_payload_i_reg[61]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(61),
Q => \^q\(54),
R => '0'
);
\m_payload_i_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(6),
Q => \^q\(6),
R => '0'
);
\m_payload_i_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(7),
Q => \^q\(7),
R => '0'
);
\m_payload_i_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(8),
Q => \^q\(8),
R => '0'
);
\m_payload_i_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(9),
Q => \^q\(9),
R => '0'
);
m_valid_i_i_1: unisim.vcomponents.LUT4
generic map(
INIT => X"F4FF"
)
port map (
I0 => b_push,
I1 => \^m_valid_i_reg_0\,
I2 => s_axi_awvalid,
I3 => \^s_axi_awready\,
O => m_valid_i0
);
m_valid_i_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => m_valid_i0,
Q => \^m_valid_i_reg_0\,
R => \aresetn_d_reg[1]_inv_0\
);
next_pending_r_i_4: unisim.vcomponents.LUT5
generic map(
INIT => X"AAAAAAA8"
)
port map (
I0 => \state_reg[1]_rep\,
I1 => \^q\(42),
I2 => \^q\(40),
I3 => \^q\(39),
I4 => \^q\(41),
O => next_pending_r_reg
);
\s_ready_i_i_1__1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \aresetn_d_reg_n_0_[0]\,
O => \^s_ready_i_reg_0\
);
s_ready_i_i_2: unisim.vcomponents.LUT4
generic map(
INIT => X"F4FF"
)
port map (
I0 => s_axi_awvalid,
I1 => \^s_axi_awready\,
I2 => b_push,
I3 => \^m_valid_i_reg_0\,
O => s_ready_i0
);
s_ready_i_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => s_ready_i0,
Q => \^s_axi_awready\,
R => \^s_ready_i_reg_0\
);
\skid_buffer_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(0),
Q => \skid_buffer_reg_n_0_[0]\,
R => '0'
);
\skid_buffer_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(10),
Q => \skid_buffer_reg_n_0_[10]\,
R => '0'
);
\skid_buffer_reg[11]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(11),
Q => \skid_buffer_reg_n_0_[11]\,
R => '0'
);
\skid_buffer_reg[12]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(12),
Q => \skid_buffer_reg_n_0_[12]\,
R => '0'
);
\skid_buffer_reg[13]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(13),
Q => \skid_buffer_reg_n_0_[13]\,
R => '0'
);
\skid_buffer_reg[14]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(14),
Q => \skid_buffer_reg_n_0_[14]\,
R => '0'
);
\skid_buffer_reg[15]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(15),
Q => \skid_buffer_reg_n_0_[15]\,
R => '0'
);
\skid_buffer_reg[16]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(16),
Q => \skid_buffer_reg_n_0_[16]\,
R => '0'
);
\skid_buffer_reg[17]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(17),
Q => \skid_buffer_reg_n_0_[17]\,
R => '0'
);
\skid_buffer_reg[18]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(18),
Q => \skid_buffer_reg_n_0_[18]\,
R => '0'
);
\skid_buffer_reg[19]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(19),
Q => \skid_buffer_reg_n_0_[19]\,
R => '0'
);
\skid_buffer_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(1),
Q => \skid_buffer_reg_n_0_[1]\,
R => '0'
);
\skid_buffer_reg[20]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(20),
Q => \skid_buffer_reg_n_0_[20]\,
R => '0'
);
\skid_buffer_reg[21]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(21),
Q => \skid_buffer_reg_n_0_[21]\,
R => '0'
);
\skid_buffer_reg[22]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(22),
Q => \skid_buffer_reg_n_0_[22]\,
R => '0'
);
\skid_buffer_reg[23]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(23),
Q => \skid_buffer_reg_n_0_[23]\,
R => '0'
);
\skid_buffer_reg[24]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(24),
Q => \skid_buffer_reg_n_0_[24]\,
R => '0'
);
\skid_buffer_reg[25]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(25),
Q => \skid_buffer_reg_n_0_[25]\,
R => '0'
);
\skid_buffer_reg[26]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(26),
Q => \skid_buffer_reg_n_0_[26]\,
R => '0'
);
\skid_buffer_reg[27]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(27),
Q => \skid_buffer_reg_n_0_[27]\,
R => '0'
);
\skid_buffer_reg[28]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(28),
Q => \skid_buffer_reg_n_0_[28]\,
R => '0'
);
\skid_buffer_reg[29]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(29),
Q => \skid_buffer_reg_n_0_[29]\,
R => '0'
);
\skid_buffer_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(2),
Q => \skid_buffer_reg_n_0_[2]\,
R => '0'
);
\skid_buffer_reg[30]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(30),
Q => \skid_buffer_reg_n_0_[30]\,
R => '0'
);
\skid_buffer_reg[31]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(31),
Q => \skid_buffer_reg_n_0_[31]\,
R => '0'
);
\skid_buffer_reg[32]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awprot(0),
Q => \skid_buffer_reg_n_0_[32]\,
R => '0'
);
\skid_buffer_reg[33]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awprot(1),
Q => \skid_buffer_reg_n_0_[33]\,
R => '0'
);
\skid_buffer_reg[34]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awprot(2),
Q => \skid_buffer_reg_n_0_[34]\,
R => '0'
);
\skid_buffer_reg[35]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awsize(0),
Q => \skid_buffer_reg_n_0_[35]\,
R => '0'
);
\skid_buffer_reg[36]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awsize(1),
Q => \skid_buffer_reg_n_0_[36]\,
R => '0'
);
\skid_buffer_reg[38]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awburst(0),
Q => \skid_buffer_reg_n_0_[38]\,
R => '0'
);
\skid_buffer_reg[39]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awburst(1),
Q => \skid_buffer_reg_n_0_[39]\,
R => '0'
);
\skid_buffer_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(3),
Q => \skid_buffer_reg_n_0_[3]\,
R => '0'
);
\skid_buffer_reg[44]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awlen(0),
Q => \skid_buffer_reg_n_0_[44]\,
R => '0'
);
\skid_buffer_reg[45]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awlen(1),
Q => \skid_buffer_reg_n_0_[45]\,
R => '0'
);
\skid_buffer_reg[46]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awlen(2),
Q => \skid_buffer_reg_n_0_[46]\,
R => '0'
);
\skid_buffer_reg[47]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awlen(3),
Q => \skid_buffer_reg_n_0_[47]\,
R => '0'
);
\skid_buffer_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(4),
Q => \skid_buffer_reg_n_0_[4]\,
R => '0'
);
\skid_buffer_reg[50]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awid(0),
Q => \skid_buffer_reg_n_0_[50]\,
R => '0'
);
\skid_buffer_reg[51]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awid(1),
Q => \skid_buffer_reg_n_0_[51]\,
R => '0'
);
\skid_buffer_reg[52]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awid(2),
Q => \skid_buffer_reg_n_0_[52]\,
R => '0'
);
\skid_buffer_reg[53]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awid(3),
Q => \skid_buffer_reg_n_0_[53]\,
R => '0'
);
\skid_buffer_reg[54]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awid(4),
Q => \skid_buffer_reg_n_0_[54]\,
R => '0'
);
\skid_buffer_reg[55]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awid(5),
Q => \skid_buffer_reg_n_0_[55]\,
R => '0'
);
\skid_buffer_reg[56]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awid(6),
Q => \skid_buffer_reg_n_0_[56]\,
R => '0'
);
\skid_buffer_reg[57]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awid(7),
Q => \skid_buffer_reg_n_0_[57]\,
R => '0'
);
\skid_buffer_reg[58]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awid(8),
Q => \skid_buffer_reg_n_0_[58]\,
R => '0'
);
\skid_buffer_reg[59]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awid(9),
Q => \skid_buffer_reg_n_0_[59]\,
R => '0'
);
\skid_buffer_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(5),
Q => \skid_buffer_reg_n_0_[5]\,
R => '0'
);
\skid_buffer_reg[60]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awid(10),
Q => \skid_buffer_reg_n_0_[60]\,
R => '0'
);
\skid_buffer_reg[61]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awid(11),
Q => \skid_buffer_reg_n_0_[61]\,
R => '0'
);
\skid_buffer_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(6),
Q => \skid_buffer_reg_n_0_[6]\,
R => '0'
);
\skid_buffer_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(7),
Q => \skid_buffer_reg_n_0_[7]\,
R => '0'
);
\skid_buffer_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(8),
Q => \skid_buffer_reg_n_0_[8]\,
R => '0'
);
\skid_buffer_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(9),
Q => \skid_buffer_reg_n_0_[9]\,
R => '0'
);
\wrap_boundary_axaddr_r[0]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"AA8A"
)
port map (
I0 => \^q\(0),
I1 => \^q\(35),
I2 => \^q\(39),
I3 => \^q\(36),
O => \wrap_boundary_axaddr_r_reg[6]\(0)
);
\wrap_boundary_axaddr_r[1]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"8A888AAA"
)
port map (
I0 => \^q\(1),
I1 => \^q\(36),
I2 => \^q\(39),
I3 => \^q\(35),
I4 => \^q\(40),
O => \wrap_boundary_axaddr_r_reg[6]\(1)
);
\wrap_boundary_axaddr_r[2]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FF0F553300000000"
)
port map (
I0 => \^q\(40),
I1 => \^q\(41),
I2 => \^q\(39),
I3 => \^q\(35),
I4 => \^q\(36),
I5 => \^q\(2),
O => \wrap_boundary_axaddr_r_reg[6]\(2)
);
\wrap_boundary_axaddr_r[3]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"020202A2A2A202A2"
)
port map (
I0 => \^q\(3),
I1 => \wrap_boundary_axaddr_r[3]_i_2_n_0\,
I2 => \^q\(36),
I3 => \^q\(40),
I4 => \^q\(35),
I5 => \^q\(39),
O => \wrap_boundary_axaddr_r_reg[6]\(3)
);
\wrap_boundary_axaddr_r[3]_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \^q\(41),
I1 => \^q\(35),
I2 => \^q\(42),
O => \wrap_boundary_axaddr_r[3]_i_2_n_0\
);
\wrap_boundary_axaddr_r[4]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"503F5F3F00000000"
)
port map (
I0 => \^q\(40),
I1 => \^q\(41),
I2 => \^q\(36),
I3 => \^q\(35),
I4 => \^q\(42),
I5 => \^q\(4),
O => \wrap_boundary_axaddr_r_reg[6]\(4)
);
\wrap_boundary_axaddr_r[5]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"2A222AAA"
)
port map (
I0 => \^q\(5),
I1 => \^q\(36),
I2 => \^q\(41),
I3 => \^q\(35),
I4 => \^q\(42),
O => \wrap_boundary_axaddr_r_reg[6]\(5)
);
\wrap_boundary_axaddr_r[6]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"2AAA"
)
port map (
I0 => \^q\(6),
I1 => \^q\(42),
I2 => \^q\(35),
I3 => \^q\(36),
O => \wrap_boundary_axaddr_r_reg[6]\(6)
);
\wrap_cnt_r[2]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAA6AA56AAAAAAAA"
)
port map (
I0 => \^wrap_second_len_r_reg[3]\(1),
I1 => \wrap_second_len_r_reg[3]_0\(0),
I2 => \state_reg[1]_rep\,
I3 => \^wrap_cnt_r_reg[2]\,
I4 => \^axaddr_offset_r_reg[0]\,
I5 => \^wrap_second_len_r_reg[3]\(0),
O => D(0)
);
\wrap_cnt_r[3]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"6A"
)
port map (
I0 => \^wrap_second_len_r_reg[3]\(2),
I1 => \wrap_second_len_r_reg[1]\,
I2 => \^wrap_second_len_r_reg[3]\(1),
O => D(1)
);
\wrap_cnt_r[3]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFEAEAFFEA"
)
port map (
I0 => \axaddr_offset_r_reg[3]_0\,
I1 => \^axlen_cnt_reg[3]\,
I2 => \axaddr_offset_r[3]_i_2_n_0\,
I3 => \^axaddr_offset_r_reg[2]\,
I4 => \wrap_cnt_r[3]_i_5_n_0\,
I5 => \axaddr_offset_r_reg[2]_1\,
O => \wrap_cnt_r_reg[3]\
);
\wrap_cnt_r[3]_i_5\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFDF"
)
port map (
I0 => \^q\(41),
I1 => \state_reg[0]_rep\,
I2 => \^m_valid_i_reg_0\,
I3 => \state_reg[1]_rep_0\,
O => \wrap_cnt_r[3]_i_5_n_0\
);
\wrap_second_len_r[0]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"0001000000010001"
)
port map (
I0 => \^axaddr_offset_r_reg[0]\,
I1 => \^axaddr_offset\(0),
I2 => \axaddr_offset_r_reg[2]_0\(0),
I3 => \wrap_second_len_r[3]_i_2_n_0\,
I4 => \state_reg[1]_rep\,
I5 => \axaddr_offset_r_reg[3]\(2),
O => \^wrap_cnt_r_reg[2]\
);
\wrap_second_len_r[1]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"F00EFFFFF00E0000"
)
port map (
I0 => \^axaddr_offset\(1),
I1 => \axaddr_offset_r_reg[2]_0\(0),
I2 => \^axaddr_offset_r_reg[0]\,
I3 => \^axaddr_offset\(0),
I4 => \state_reg[1]_rep\,
I5 => \wrap_second_len_r_reg[3]_0\(1),
O => \^wrap_second_len_r_reg[3]\(0)
);
\wrap_second_len_r[2]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"CCC2FFFFCCC20000"
)
port map (
I0 => \^axaddr_offset\(1),
I1 => \axaddr_offset_r_reg[2]_0\(0),
I2 => \^axaddr_offset\(0),
I3 => \^axaddr_offset_r_reg[0]\,
I4 => \state_reg[1]_rep\,
I5 => \wrap_second_len_r_reg[3]_0\(2),
O => \^wrap_second_len_r_reg[3]\(1)
);
\wrap_second_len_r[3]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FE00FFFFFE00FE00"
)
port map (
I0 => \^axaddr_offset_r_reg[0]\,
I1 => \^axaddr_offset\(0),
I2 => \axaddr_offset_r_reg[2]_0\(0),
I3 => \wrap_second_len_r[3]_i_2_n_0\,
I4 => \state_reg[1]_rep\,
I5 => \wrap_second_len_r_reg[3]_0\(3),
O => \^wrap_second_len_r_reg[3]\(2)
);
\wrap_second_len_r[3]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"A8A8A8080808A808"
)
port map (
I0 => \^axlen_cnt_reg[3]\,
I1 => \wrap_second_len_r[3]_i_3_n_0\,
I2 => \^q\(36),
I3 => \^q\(5),
I4 => \^q\(35),
I5 => \^q\(6),
O => \wrap_second_len_r[3]_i_2_n_0\
);
\wrap_second_len_r[3]_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \^q\(4),
I1 => \^q\(35),
I2 => \^q\(3),
O => \wrap_second_len_r[3]_i_3_n_0\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \zybo_zynq_design_auto_pc_0_axi_register_slice_v2_1_17_axic_register_slice__parameterized1\ is
port (
s_axi_bvalid : out STD_LOGIC;
\skid_buffer_reg[0]_0\ : out STD_LOGIC;
\s_axi_bid[11]\ : out STD_LOGIC_VECTOR ( 13 downto 0 );
\aresetn_d_reg[1]_inv\ : in STD_LOGIC;
aclk : in STD_LOGIC;
\aresetn_d_reg[0]\ : in STD_LOGIC;
si_rs_bvalid : in STD_LOGIC;
s_axi_bready : in STD_LOGIC;
\out\ : in STD_LOGIC_VECTOR ( 11 downto 0 );
\s_bresp_acc_reg[1]\ : in STD_LOGIC_VECTOR ( 1 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \zybo_zynq_design_auto_pc_0_axi_register_slice_v2_1_17_axic_register_slice__parameterized1\ : entity is "axi_register_slice_v2_1_17_axic_register_slice";
end \zybo_zynq_design_auto_pc_0_axi_register_slice_v2_1_17_axic_register_slice__parameterized1\;
architecture STRUCTURE of \zybo_zynq_design_auto_pc_0_axi_register_slice_v2_1_17_axic_register_slice__parameterized1\ is
signal \m_payload_i[0]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[10]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[11]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[12]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[13]_i_2_n_0\ : STD_LOGIC;
signal \m_payload_i[1]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[2]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[3]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[4]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[5]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[6]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[7]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[8]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[9]_i_1__1_n_0\ : STD_LOGIC;
signal m_valid_i0 : STD_LOGIC;
signal p_1_in : STD_LOGIC;
signal \^s_axi_bvalid\ : STD_LOGIC;
signal s_ready_i0 : STD_LOGIC;
signal \^skid_buffer_reg[0]_0\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[0]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[10]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[11]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[12]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[13]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[1]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[2]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[3]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[4]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[5]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[6]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[7]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[8]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[9]\ : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \m_payload_i[0]_i_1__1\ : label is "soft_lutpair83";
attribute SOFT_HLUTNM of \m_payload_i[10]_i_1__1\ : label is "soft_lutpair78";
attribute SOFT_HLUTNM of \m_payload_i[11]_i_1__1\ : label is "soft_lutpair77";
attribute SOFT_HLUTNM of \m_payload_i[12]_i_1__1\ : label is "soft_lutpair78";
attribute SOFT_HLUTNM of \m_payload_i[13]_i_2\ : label is "soft_lutpair77";
attribute SOFT_HLUTNM of \m_payload_i[1]_i_1__1\ : label is "soft_lutpair83";
attribute SOFT_HLUTNM of \m_payload_i[2]_i_1__1\ : label is "soft_lutpair82";
attribute SOFT_HLUTNM of \m_payload_i[3]_i_1__1\ : label is "soft_lutpair82";
attribute SOFT_HLUTNM of \m_payload_i[4]_i_1__1\ : label is "soft_lutpair81";
attribute SOFT_HLUTNM of \m_payload_i[5]_i_1__1\ : label is "soft_lutpair81";
attribute SOFT_HLUTNM of \m_payload_i[6]_i_1__1\ : label is "soft_lutpair80";
attribute SOFT_HLUTNM of \m_payload_i[7]_i_1__1\ : label is "soft_lutpair80";
attribute SOFT_HLUTNM of \m_payload_i[8]_i_1__1\ : label is "soft_lutpair79";
attribute SOFT_HLUTNM of \m_payload_i[9]_i_1__1\ : label is "soft_lutpair79";
begin
s_axi_bvalid <= \^s_axi_bvalid\;
\skid_buffer_reg[0]_0\ <= \^skid_buffer_reg[0]_0\;
\m_payload_i[0]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \s_bresp_acc_reg[1]\(0),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[0]\,
O => \m_payload_i[0]_i_1__1_n_0\
);
\m_payload_i[10]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \out\(8),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[10]\,
O => \m_payload_i[10]_i_1__1_n_0\
);
\m_payload_i[11]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \out\(9),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[11]\,
O => \m_payload_i[11]_i_1__1_n_0\
);
\m_payload_i[12]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \out\(10),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[12]\,
O => \m_payload_i[12]_i_1__1_n_0\
);
\m_payload_i[13]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"B"
)
port map (
I0 => s_axi_bready,
I1 => \^s_axi_bvalid\,
O => p_1_in
);
\m_payload_i[13]_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \out\(11),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[13]\,
O => \m_payload_i[13]_i_2_n_0\
);
\m_payload_i[1]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \s_bresp_acc_reg[1]\(1),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[1]\,
O => \m_payload_i[1]_i_1__1_n_0\
);
\m_payload_i[2]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \out\(0),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[2]\,
O => \m_payload_i[2]_i_1__1_n_0\
);
\m_payload_i[3]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \out\(1),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[3]\,
O => \m_payload_i[3]_i_1__1_n_0\
);
\m_payload_i[4]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \out\(2),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[4]\,
O => \m_payload_i[4]_i_1__1_n_0\
);
\m_payload_i[5]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \out\(3),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[5]\,
O => \m_payload_i[5]_i_1__1_n_0\
);
\m_payload_i[6]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \out\(4),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[6]\,
O => \m_payload_i[6]_i_1__1_n_0\
);
\m_payload_i[7]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \out\(5),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[7]\,
O => \m_payload_i[7]_i_1__1_n_0\
);
\m_payload_i[8]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \out\(6),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[8]\,
O => \m_payload_i[8]_i_1__1_n_0\
);
\m_payload_i[9]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \out\(7),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[9]\,
O => \m_payload_i[9]_i_1__1_n_0\
);
\m_payload_i_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[0]_i_1__1_n_0\,
Q => \s_axi_bid[11]\(0),
R => '0'
);
\m_payload_i_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[10]_i_1__1_n_0\,
Q => \s_axi_bid[11]\(10),
R => '0'
);
\m_payload_i_reg[11]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[11]_i_1__1_n_0\,
Q => \s_axi_bid[11]\(11),
R => '0'
);
\m_payload_i_reg[12]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[12]_i_1__1_n_0\,
Q => \s_axi_bid[11]\(12),
R => '0'
);
\m_payload_i_reg[13]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[13]_i_2_n_0\,
Q => \s_axi_bid[11]\(13),
R => '0'
);
\m_payload_i_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[1]_i_1__1_n_0\,
Q => \s_axi_bid[11]\(1),
R => '0'
);
\m_payload_i_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[2]_i_1__1_n_0\,
Q => \s_axi_bid[11]\(2),
R => '0'
);
\m_payload_i_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[3]_i_1__1_n_0\,
Q => \s_axi_bid[11]\(3),
R => '0'
);
\m_payload_i_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[4]_i_1__1_n_0\,
Q => \s_axi_bid[11]\(4),
R => '0'
);
\m_payload_i_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[5]_i_1__1_n_0\,
Q => \s_axi_bid[11]\(5),
R => '0'
);
\m_payload_i_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[6]_i_1__1_n_0\,
Q => \s_axi_bid[11]\(6),
R => '0'
);
\m_payload_i_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[7]_i_1__1_n_0\,
Q => \s_axi_bid[11]\(7),
R => '0'
);
\m_payload_i_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[8]_i_1__1_n_0\,
Q => \s_axi_bid[11]\(8),
R => '0'
);
\m_payload_i_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[9]_i_1__1_n_0\,
Q => \s_axi_bid[11]\(9),
R => '0'
);
\m_valid_i_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"F4FF"
)
port map (
I0 => s_axi_bready,
I1 => \^s_axi_bvalid\,
I2 => si_rs_bvalid,
I3 => \^skid_buffer_reg[0]_0\,
O => m_valid_i0
);
m_valid_i_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => m_valid_i0,
Q => \^s_axi_bvalid\,
R => \aresetn_d_reg[1]_inv\
);
s_ready_i_i_1: unisim.vcomponents.LUT4
generic map(
INIT => X"F4FF"
)
port map (
I0 => si_rs_bvalid,
I1 => \^skid_buffer_reg[0]_0\,
I2 => s_axi_bready,
I3 => \^s_axi_bvalid\,
O => s_ready_i0
);
s_ready_i_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => s_ready_i0,
Q => \^skid_buffer_reg[0]_0\,
R => \aresetn_d_reg[0]\
);
\skid_buffer_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \s_bresp_acc_reg[1]\(0),
Q => \skid_buffer_reg_n_0_[0]\,
R => '0'
);
\skid_buffer_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \out\(8),
Q => \skid_buffer_reg_n_0_[10]\,
R => '0'
);
\skid_buffer_reg[11]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \out\(9),
Q => \skid_buffer_reg_n_0_[11]\,
R => '0'
);
\skid_buffer_reg[12]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \out\(10),
Q => \skid_buffer_reg_n_0_[12]\,
R => '0'
);
\skid_buffer_reg[13]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \out\(11),
Q => \skid_buffer_reg_n_0_[13]\,
R => '0'
);
\skid_buffer_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \s_bresp_acc_reg[1]\(1),
Q => \skid_buffer_reg_n_0_[1]\,
R => '0'
);
\skid_buffer_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \out\(0),
Q => \skid_buffer_reg_n_0_[2]\,
R => '0'
);
\skid_buffer_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \out\(1),
Q => \skid_buffer_reg_n_0_[3]\,
R => '0'
);
\skid_buffer_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \out\(2),
Q => \skid_buffer_reg_n_0_[4]\,
R => '0'
);
\skid_buffer_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \out\(3),
Q => \skid_buffer_reg_n_0_[5]\,
R => '0'
);
\skid_buffer_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \out\(4),
Q => \skid_buffer_reg_n_0_[6]\,
R => '0'
);
\skid_buffer_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \out\(5),
Q => \skid_buffer_reg_n_0_[7]\,
R => '0'
);
\skid_buffer_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \out\(6),
Q => \skid_buffer_reg_n_0_[8]\,
R => '0'
);
\skid_buffer_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \out\(7),
Q => \skid_buffer_reg_n_0_[9]\,
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \zybo_zynq_design_auto_pc_0_axi_register_slice_v2_1_17_axic_register_slice__parameterized2\ is
port (
s_axi_rvalid : out STD_LOGIC;
\skid_buffer_reg[0]_0\ : out STD_LOGIC;
\cnt_read_reg[2]_rep__0\ : out STD_LOGIC;
\s_axi_rid[11]\ : out STD_LOGIC_VECTOR ( 46 downto 0 );
\aresetn_d_reg[1]_inv\ : in STD_LOGIC;
aclk : in STD_LOGIC;
\aresetn_d_reg[0]\ : in STD_LOGIC;
\cnt_read_reg[4]_rep__0\ : in STD_LOGIC;
s_axi_rready : in STD_LOGIC;
r_push_r_reg : in STD_LOGIC_VECTOR ( 12 downto 0 );
\cnt_read_reg[4]\ : in STD_LOGIC_VECTOR ( 33 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \zybo_zynq_design_auto_pc_0_axi_register_slice_v2_1_17_axic_register_slice__parameterized2\ : entity is "axi_register_slice_v2_1_17_axic_register_slice";
end \zybo_zynq_design_auto_pc_0_axi_register_slice_v2_1_17_axic_register_slice__parameterized2\;
architecture STRUCTURE of \zybo_zynq_design_auto_pc_0_axi_register_slice_v2_1_17_axic_register_slice__parameterized2\ is
signal \m_payload_i[0]_i_1__2_n_0\ : STD_LOGIC;
signal \m_payload_i[10]_i_1__2_n_0\ : STD_LOGIC;
signal \m_payload_i[11]_i_1__2_n_0\ : STD_LOGIC;
signal \m_payload_i[12]_i_1__2_n_0\ : STD_LOGIC;
signal \m_payload_i[13]_i_1__2_n_0\ : STD_LOGIC;
signal \m_payload_i[14]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[15]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[16]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[17]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[18]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[19]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[1]_i_1__2_n_0\ : STD_LOGIC;
signal \m_payload_i[20]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[21]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[22]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[23]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[24]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[25]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[26]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[27]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[28]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[29]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[2]_i_1__2_n_0\ : STD_LOGIC;
signal \m_payload_i[30]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[31]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[32]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[33]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[34]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[35]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[36]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[37]_i_1_n_0\ : STD_LOGIC;
signal \m_payload_i[38]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[39]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[3]_i_1__2_n_0\ : STD_LOGIC;
signal \m_payload_i[40]_i_1_n_0\ : STD_LOGIC;
signal \m_payload_i[41]_i_1_n_0\ : STD_LOGIC;
signal \m_payload_i[42]_i_1_n_0\ : STD_LOGIC;
signal \m_payload_i[43]_i_1_n_0\ : STD_LOGIC;
signal \m_payload_i[44]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[45]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[46]_i_2_n_0\ : STD_LOGIC;
signal \m_payload_i[4]_i_1__2_n_0\ : STD_LOGIC;
signal \m_payload_i[5]_i_1__2_n_0\ : STD_LOGIC;
signal \m_payload_i[6]_i_1__2_n_0\ : STD_LOGIC;
signal \m_payload_i[7]_i_1__2_n_0\ : STD_LOGIC;
signal \m_payload_i[8]_i_1__2_n_0\ : STD_LOGIC;
signal \m_payload_i[9]_i_1__2_n_0\ : STD_LOGIC;
signal \m_valid_i_i_1__2_n_0\ : STD_LOGIC;
signal p_1_in : STD_LOGIC;
signal \^s_axi_rvalid\ : STD_LOGIC;
signal \s_ready_i_i_1__2_n_0\ : STD_LOGIC;
signal \^skid_buffer_reg[0]_0\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[0]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[10]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[11]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[12]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[13]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[14]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[15]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[16]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[17]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[18]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[19]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[1]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[20]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[21]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[22]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[23]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[24]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[25]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[26]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[27]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[28]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[29]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[2]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[30]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[31]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[32]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[33]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[34]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[35]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[36]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[37]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[38]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[39]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[3]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[40]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[41]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[42]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[43]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[44]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[45]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[46]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[4]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[5]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[6]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[7]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[8]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[9]\ : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \cnt_read[4]_i_4\ : label is "soft_lutpair84";
attribute SOFT_HLUTNM of \m_payload_i[10]_i_1__2\ : label is "soft_lutpair103";
attribute SOFT_HLUTNM of \m_payload_i[11]_i_1__2\ : label is "soft_lutpair102";
attribute SOFT_HLUTNM of \m_payload_i[12]_i_1__2\ : label is "soft_lutpair102";
attribute SOFT_HLUTNM of \m_payload_i[13]_i_1__2\ : label is "soft_lutpair101";
attribute SOFT_HLUTNM of \m_payload_i[14]_i_1__1\ : label is "soft_lutpair101";
attribute SOFT_HLUTNM of \m_payload_i[15]_i_1__1\ : label is "soft_lutpair100";
attribute SOFT_HLUTNM of \m_payload_i[16]_i_1__1\ : label is "soft_lutpair100";
attribute SOFT_HLUTNM of \m_payload_i[17]_i_1__1\ : label is "soft_lutpair99";
attribute SOFT_HLUTNM of \m_payload_i[18]_i_1__1\ : label is "soft_lutpair99";
attribute SOFT_HLUTNM of \m_payload_i[19]_i_1__1\ : label is "soft_lutpair98";
attribute SOFT_HLUTNM of \m_payload_i[1]_i_1__2\ : label is "soft_lutpair107";
attribute SOFT_HLUTNM of \m_payload_i[20]_i_1__1\ : label is "soft_lutpair98";
attribute SOFT_HLUTNM of \m_payload_i[21]_i_1__1\ : label is "soft_lutpair97";
attribute SOFT_HLUTNM of \m_payload_i[22]_i_1__1\ : label is "soft_lutpair97";
attribute SOFT_HLUTNM of \m_payload_i[23]_i_1__1\ : label is "soft_lutpair96";
attribute SOFT_HLUTNM of \m_payload_i[24]_i_1__1\ : label is "soft_lutpair96";
attribute SOFT_HLUTNM of \m_payload_i[25]_i_1__1\ : label is "soft_lutpair95";
attribute SOFT_HLUTNM of \m_payload_i[26]_i_1__1\ : label is "soft_lutpair95";
attribute SOFT_HLUTNM of \m_payload_i[27]_i_1__1\ : label is "soft_lutpair94";
attribute SOFT_HLUTNM of \m_payload_i[28]_i_1__1\ : label is "soft_lutpair94";
attribute SOFT_HLUTNM of \m_payload_i[29]_i_1__1\ : label is "soft_lutpair93";
attribute SOFT_HLUTNM of \m_payload_i[2]_i_1__2\ : label is "soft_lutpair107";
attribute SOFT_HLUTNM of \m_payload_i[30]_i_1__1\ : label is "soft_lutpair93";
attribute SOFT_HLUTNM of \m_payload_i[31]_i_1__1\ : label is "soft_lutpair92";
attribute SOFT_HLUTNM of \m_payload_i[32]_i_1__1\ : label is "soft_lutpair92";
attribute SOFT_HLUTNM of \m_payload_i[33]_i_1__1\ : label is "soft_lutpair91";
attribute SOFT_HLUTNM of \m_payload_i[34]_i_1__1\ : label is "soft_lutpair91";
attribute SOFT_HLUTNM of \m_payload_i[35]_i_1__1\ : label is "soft_lutpair90";
attribute SOFT_HLUTNM of \m_payload_i[36]_i_1__1\ : label is "soft_lutpair90";
attribute SOFT_HLUTNM of \m_payload_i[37]_i_1\ : label is "soft_lutpair89";
attribute SOFT_HLUTNM of \m_payload_i[38]_i_1__1\ : label is "soft_lutpair89";
attribute SOFT_HLUTNM of \m_payload_i[39]_i_1__1\ : label is "soft_lutpair88";
attribute SOFT_HLUTNM of \m_payload_i[3]_i_1__2\ : label is "soft_lutpair106";
attribute SOFT_HLUTNM of \m_payload_i[40]_i_1\ : label is "soft_lutpair88";
attribute SOFT_HLUTNM of \m_payload_i[41]_i_1\ : label is "soft_lutpair87";
attribute SOFT_HLUTNM of \m_payload_i[42]_i_1\ : label is "soft_lutpair87";
attribute SOFT_HLUTNM of \m_payload_i[43]_i_1\ : label is "soft_lutpair86";
attribute SOFT_HLUTNM of \m_payload_i[44]_i_1__1\ : label is "soft_lutpair85";
attribute SOFT_HLUTNM of \m_payload_i[45]_i_1__1\ : label is "soft_lutpair86";
attribute SOFT_HLUTNM of \m_payload_i[46]_i_2\ : label is "soft_lutpair85";
attribute SOFT_HLUTNM of \m_payload_i[4]_i_1__2\ : label is "soft_lutpair106";
attribute SOFT_HLUTNM of \m_payload_i[5]_i_1__2\ : label is "soft_lutpair105";
attribute SOFT_HLUTNM of \m_payload_i[6]_i_1__2\ : label is "soft_lutpair105";
attribute SOFT_HLUTNM of \m_payload_i[7]_i_1__2\ : label is "soft_lutpair104";
attribute SOFT_HLUTNM of \m_payload_i[8]_i_1__2\ : label is "soft_lutpair104";
attribute SOFT_HLUTNM of \m_payload_i[9]_i_1__2\ : label is "soft_lutpair103";
attribute SOFT_HLUTNM of \s_ready_i_i_1__2\ : label is "soft_lutpair84";
begin
s_axi_rvalid <= \^s_axi_rvalid\;
\skid_buffer_reg[0]_0\ <= \^skid_buffer_reg[0]_0\;
\cnt_read[4]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \^skid_buffer_reg[0]_0\,
I1 => \cnt_read_reg[4]_rep__0\,
O => \cnt_read_reg[2]_rep__0\
);
\m_payload_i[0]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(0),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[0]\,
O => \m_payload_i[0]_i_1__2_n_0\
);
\m_payload_i[10]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(10),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[10]\,
O => \m_payload_i[10]_i_1__2_n_0\
);
\m_payload_i[11]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(11),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[11]\,
O => \m_payload_i[11]_i_1__2_n_0\
);
\m_payload_i[12]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(12),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[12]\,
O => \m_payload_i[12]_i_1__2_n_0\
);
\m_payload_i[13]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(13),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[13]\,
O => \m_payload_i[13]_i_1__2_n_0\
);
\m_payload_i[14]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(14),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[14]\,
O => \m_payload_i[14]_i_1__1_n_0\
);
\m_payload_i[15]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(15),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[15]\,
O => \m_payload_i[15]_i_1__1_n_0\
);
\m_payload_i[16]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(16),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[16]\,
O => \m_payload_i[16]_i_1__1_n_0\
);
\m_payload_i[17]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(17),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[17]\,
O => \m_payload_i[17]_i_1__1_n_0\
);
\m_payload_i[18]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(18),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[18]\,
O => \m_payload_i[18]_i_1__1_n_0\
);
\m_payload_i[19]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(19),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[19]\,
O => \m_payload_i[19]_i_1__1_n_0\
);
\m_payload_i[1]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(1),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[1]\,
O => \m_payload_i[1]_i_1__2_n_0\
);
\m_payload_i[20]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(20),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[20]\,
O => \m_payload_i[20]_i_1__1_n_0\
);
\m_payload_i[21]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(21),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[21]\,
O => \m_payload_i[21]_i_1__1_n_0\
);
\m_payload_i[22]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(22),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[22]\,
O => \m_payload_i[22]_i_1__1_n_0\
);
\m_payload_i[23]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(23),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[23]\,
O => \m_payload_i[23]_i_1__1_n_0\
);
\m_payload_i[24]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(24),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[24]\,
O => \m_payload_i[24]_i_1__1_n_0\
);
\m_payload_i[25]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(25),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[25]\,
O => \m_payload_i[25]_i_1__1_n_0\
);
\m_payload_i[26]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(26),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[26]\,
O => \m_payload_i[26]_i_1__1_n_0\
);
\m_payload_i[27]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(27),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[27]\,
O => \m_payload_i[27]_i_1__1_n_0\
);
\m_payload_i[28]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(28),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[28]\,
O => \m_payload_i[28]_i_1__1_n_0\
);
\m_payload_i[29]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(29),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[29]\,
O => \m_payload_i[29]_i_1__1_n_0\
);
\m_payload_i[2]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(2),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[2]\,
O => \m_payload_i[2]_i_1__2_n_0\
);
\m_payload_i[30]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(30),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[30]\,
O => \m_payload_i[30]_i_1__1_n_0\
);
\m_payload_i[31]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(31),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[31]\,
O => \m_payload_i[31]_i_1__1_n_0\
);
\m_payload_i[32]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(32),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[32]\,
O => \m_payload_i[32]_i_1__1_n_0\
);
\m_payload_i[33]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(33),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[33]\,
O => \m_payload_i[33]_i_1__1_n_0\
);
\m_payload_i[34]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => r_push_r_reg(0),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[34]\,
O => \m_payload_i[34]_i_1__1_n_0\
);
\m_payload_i[35]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => r_push_r_reg(1),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[35]\,
O => \m_payload_i[35]_i_1__1_n_0\
);
\m_payload_i[36]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => r_push_r_reg(2),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[36]\,
O => \m_payload_i[36]_i_1__1_n_0\
);
\m_payload_i[37]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => r_push_r_reg(3),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[37]\,
O => \m_payload_i[37]_i_1_n_0\
);
\m_payload_i[38]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => r_push_r_reg(4),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[38]\,
O => \m_payload_i[38]_i_1__1_n_0\
);
\m_payload_i[39]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => r_push_r_reg(5),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[39]\,
O => \m_payload_i[39]_i_1__1_n_0\
);
\m_payload_i[3]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(3),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[3]\,
O => \m_payload_i[3]_i_1__2_n_0\
);
\m_payload_i[40]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => r_push_r_reg(6),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[40]\,
O => \m_payload_i[40]_i_1_n_0\
);
\m_payload_i[41]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => r_push_r_reg(7),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[41]\,
O => \m_payload_i[41]_i_1_n_0\
);
\m_payload_i[42]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => r_push_r_reg(8),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[42]\,
O => \m_payload_i[42]_i_1_n_0\
);
\m_payload_i[43]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => r_push_r_reg(9),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[43]\,
O => \m_payload_i[43]_i_1_n_0\
);
\m_payload_i[44]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => r_push_r_reg(10),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[44]\,
O => \m_payload_i[44]_i_1__1_n_0\
);
\m_payload_i[45]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => r_push_r_reg(11),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[45]\,
O => \m_payload_i[45]_i_1__1_n_0\
);
\m_payload_i[46]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"B"
)
port map (
I0 => s_axi_rready,
I1 => \^s_axi_rvalid\,
O => p_1_in
);
\m_payload_i[46]_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => r_push_r_reg(12),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[46]\,
O => \m_payload_i[46]_i_2_n_0\
);
\m_payload_i[4]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(4),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[4]\,
O => \m_payload_i[4]_i_1__2_n_0\
);
\m_payload_i[5]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(5),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[5]\,
O => \m_payload_i[5]_i_1__2_n_0\
);
\m_payload_i[6]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(6),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[6]\,
O => \m_payload_i[6]_i_1__2_n_0\
);
\m_payload_i[7]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(7),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[7]\,
O => \m_payload_i[7]_i_1__2_n_0\
);
\m_payload_i[8]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(8),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[8]\,
O => \m_payload_i[8]_i_1__2_n_0\
);
\m_payload_i[9]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(9),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[9]\,
O => \m_payload_i[9]_i_1__2_n_0\
);
\m_payload_i_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[0]_i_1__2_n_0\,
Q => \s_axi_rid[11]\(0),
R => '0'
);
\m_payload_i_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[10]_i_1__2_n_0\,
Q => \s_axi_rid[11]\(10),
R => '0'
);
\m_payload_i_reg[11]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[11]_i_1__2_n_0\,
Q => \s_axi_rid[11]\(11),
R => '0'
);
\m_payload_i_reg[12]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[12]_i_1__2_n_0\,
Q => \s_axi_rid[11]\(12),
R => '0'
);
\m_payload_i_reg[13]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[13]_i_1__2_n_0\,
Q => \s_axi_rid[11]\(13),
R => '0'
);
\m_payload_i_reg[14]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[14]_i_1__1_n_0\,
Q => \s_axi_rid[11]\(14),
R => '0'
);
\m_payload_i_reg[15]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[15]_i_1__1_n_0\,
Q => \s_axi_rid[11]\(15),
R => '0'
);
\m_payload_i_reg[16]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[16]_i_1__1_n_0\,
Q => \s_axi_rid[11]\(16),
R => '0'
);
\m_payload_i_reg[17]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[17]_i_1__1_n_0\,
Q => \s_axi_rid[11]\(17),
R => '0'
);
\m_payload_i_reg[18]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[18]_i_1__1_n_0\,
Q => \s_axi_rid[11]\(18),
R => '0'
);
\m_payload_i_reg[19]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[19]_i_1__1_n_0\,
Q => \s_axi_rid[11]\(19),
R => '0'
);
\m_payload_i_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[1]_i_1__2_n_0\,
Q => \s_axi_rid[11]\(1),
R => '0'
);
\m_payload_i_reg[20]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[20]_i_1__1_n_0\,
Q => \s_axi_rid[11]\(20),
R => '0'
);
\m_payload_i_reg[21]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[21]_i_1__1_n_0\,
Q => \s_axi_rid[11]\(21),
R => '0'
);
\m_payload_i_reg[22]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[22]_i_1__1_n_0\,
Q => \s_axi_rid[11]\(22),
R => '0'
);
\m_payload_i_reg[23]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[23]_i_1__1_n_0\,
Q => \s_axi_rid[11]\(23),
R => '0'
);
\m_payload_i_reg[24]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[24]_i_1__1_n_0\,
Q => \s_axi_rid[11]\(24),
R => '0'
);
\m_payload_i_reg[25]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[25]_i_1__1_n_0\,
Q => \s_axi_rid[11]\(25),
R => '0'
);
\m_payload_i_reg[26]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[26]_i_1__1_n_0\,
Q => \s_axi_rid[11]\(26),
R => '0'
);
\m_payload_i_reg[27]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[27]_i_1__1_n_0\,
Q => \s_axi_rid[11]\(27),
R => '0'
);
\m_payload_i_reg[28]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[28]_i_1__1_n_0\,
Q => \s_axi_rid[11]\(28),
R => '0'
);
\m_payload_i_reg[29]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[29]_i_1__1_n_0\,
Q => \s_axi_rid[11]\(29),
R => '0'
);
\m_payload_i_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[2]_i_1__2_n_0\,
Q => \s_axi_rid[11]\(2),
R => '0'
);
\m_payload_i_reg[30]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[30]_i_1__1_n_0\,
Q => \s_axi_rid[11]\(30),
R => '0'
);
\m_payload_i_reg[31]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[31]_i_1__1_n_0\,
Q => \s_axi_rid[11]\(31),
R => '0'
);
\m_payload_i_reg[32]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[32]_i_1__1_n_0\,
Q => \s_axi_rid[11]\(32),
R => '0'
);
\m_payload_i_reg[33]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[33]_i_1__1_n_0\,
Q => \s_axi_rid[11]\(33),
R => '0'
);
\m_payload_i_reg[34]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[34]_i_1__1_n_0\,
Q => \s_axi_rid[11]\(34),
R => '0'
);
\m_payload_i_reg[35]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[35]_i_1__1_n_0\,
Q => \s_axi_rid[11]\(35),
R => '0'
);
\m_payload_i_reg[36]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[36]_i_1__1_n_0\,
Q => \s_axi_rid[11]\(36),
R => '0'
);
\m_payload_i_reg[37]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[37]_i_1_n_0\,
Q => \s_axi_rid[11]\(37),
R => '0'
);
\m_payload_i_reg[38]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[38]_i_1__1_n_0\,
Q => \s_axi_rid[11]\(38),
R => '0'
);
\m_payload_i_reg[39]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[39]_i_1__1_n_0\,
Q => \s_axi_rid[11]\(39),
R => '0'
);
\m_payload_i_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[3]_i_1__2_n_0\,
Q => \s_axi_rid[11]\(3),
R => '0'
);
\m_payload_i_reg[40]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[40]_i_1_n_0\,
Q => \s_axi_rid[11]\(40),
R => '0'
);
\m_payload_i_reg[41]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[41]_i_1_n_0\,
Q => \s_axi_rid[11]\(41),
R => '0'
);
\m_payload_i_reg[42]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[42]_i_1_n_0\,
Q => \s_axi_rid[11]\(42),
R => '0'
);
\m_payload_i_reg[43]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[43]_i_1_n_0\,
Q => \s_axi_rid[11]\(43),
R => '0'
);
\m_payload_i_reg[44]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[44]_i_1__1_n_0\,
Q => \s_axi_rid[11]\(44),
R => '0'
);
\m_payload_i_reg[45]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[45]_i_1__1_n_0\,
Q => \s_axi_rid[11]\(45),
R => '0'
);
\m_payload_i_reg[46]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[46]_i_2_n_0\,
Q => \s_axi_rid[11]\(46),
R => '0'
);
\m_payload_i_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[4]_i_1__2_n_0\,
Q => \s_axi_rid[11]\(4),
R => '0'
);
\m_payload_i_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[5]_i_1__2_n_0\,
Q => \s_axi_rid[11]\(5),
R => '0'
);
\m_payload_i_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[6]_i_1__2_n_0\,
Q => \s_axi_rid[11]\(6),
R => '0'
);
\m_payload_i_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[7]_i_1__2_n_0\,
Q => \s_axi_rid[11]\(7),
R => '0'
);
\m_payload_i_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[8]_i_1__2_n_0\,
Q => \s_axi_rid[11]\(8),
R => '0'
);
\m_payload_i_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[9]_i_1__2_n_0\,
Q => \s_axi_rid[11]\(9),
R => '0'
);
\m_valid_i_i_1__2\: unisim.vcomponents.LUT4
generic map(
INIT => X"4FFF"
)
port map (
I0 => s_axi_rready,
I1 => \^s_axi_rvalid\,
I2 => \cnt_read_reg[4]_rep__0\,
I3 => \^skid_buffer_reg[0]_0\,
O => \m_valid_i_i_1__2_n_0\
);
m_valid_i_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => \m_valid_i_i_1__2_n_0\,
Q => \^s_axi_rvalid\,
R => \aresetn_d_reg[1]_inv\
);
\s_ready_i_i_1__2\: unisim.vcomponents.LUT4
generic map(
INIT => X"F8FF"
)
port map (
I0 => \cnt_read_reg[4]_rep__0\,
I1 => \^skid_buffer_reg[0]_0\,
I2 => s_axi_rready,
I3 => \^s_axi_rvalid\,
O => \s_ready_i_i_1__2_n_0\
);
s_ready_i_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => \s_ready_i_i_1__2_n_0\,
Q => \^skid_buffer_reg[0]_0\,
R => \aresetn_d_reg[0]\
);
\skid_buffer_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(0),
Q => \skid_buffer_reg_n_0_[0]\,
R => '0'
);
\skid_buffer_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(10),
Q => \skid_buffer_reg_n_0_[10]\,
R => '0'
);
\skid_buffer_reg[11]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(11),
Q => \skid_buffer_reg_n_0_[11]\,
R => '0'
);
\skid_buffer_reg[12]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(12),
Q => \skid_buffer_reg_n_0_[12]\,
R => '0'
);
\skid_buffer_reg[13]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(13),
Q => \skid_buffer_reg_n_0_[13]\,
R => '0'
);
\skid_buffer_reg[14]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(14),
Q => \skid_buffer_reg_n_0_[14]\,
R => '0'
);
\skid_buffer_reg[15]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(15),
Q => \skid_buffer_reg_n_0_[15]\,
R => '0'
);
\skid_buffer_reg[16]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(16),
Q => \skid_buffer_reg_n_0_[16]\,
R => '0'
);
\skid_buffer_reg[17]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(17),
Q => \skid_buffer_reg_n_0_[17]\,
R => '0'
);
\skid_buffer_reg[18]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(18),
Q => \skid_buffer_reg_n_0_[18]\,
R => '0'
);
\skid_buffer_reg[19]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(19),
Q => \skid_buffer_reg_n_0_[19]\,
R => '0'
);
\skid_buffer_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(1),
Q => \skid_buffer_reg_n_0_[1]\,
R => '0'
);
\skid_buffer_reg[20]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(20),
Q => \skid_buffer_reg_n_0_[20]\,
R => '0'
);
\skid_buffer_reg[21]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(21),
Q => \skid_buffer_reg_n_0_[21]\,
R => '0'
);
\skid_buffer_reg[22]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(22),
Q => \skid_buffer_reg_n_0_[22]\,
R => '0'
);
\skid_buffer_reg[23]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(23),
Q => \skid_buffer_reg_n_0_[23]\,
R => '0'
);
\skid_buffer_reg[24]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(24),
Q => \skid_buffer_reg_n_0_[24]\,
R => '0'
);
\skid_buffer_reg[25]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(25),
Q => \skid_buffer_reg_n_0_[25]\,
R => '0'
);
\skid_buffer_reg[26]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(26),
Q => \skid_buffer_reg_n_0_[26]\,
R => '0'
);
\skid_buffer_reg[27]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(27),
Q => \skid_buffer_reg_n_0_[27]\,
R => '0'
);
\skid_buffer_reg[28]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(28),
Q => \skid_buffer_reg_n_0_[28]\,
R => '0'
);
\skid_buffer_reg[29]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(29),
Q => \skid_buffer_reg_n_0_[29]\,
R => '0'
);
\skid_buffer_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(2),
Q => \skid_buffer_reg_n_0_[2]\,
R => '0'
);
\skid_buffer_reg[30]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(30),
Q => \skid_buffer_reg_n_0_[30]\,
R => '0'
);
\skid_buffer_reg[31]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(31),
Q => \skid_buffer_reg_n_0_[31]\,
R => '0'
);
\skid_buffer_reg[32]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(32),
Q => \skid_buffer_reg_n_0_[32]\,
R => '0'
);
\skid_buffer_reg[33]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(33),
Q => \skid_buffer_reg_n_0_[33]\,
R => '0'
);
\skid_buffer_reg[34]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => r_push_r_reg(0),
Q => \skid_buffer_reg_n_0_[34]\,
R => '0'
);
\skid_buffer_reg[35]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => r_push_r_reg(1),
Q => \skid_buffer_reg_n_0_[35]\,
R => '0'
);
\skid_buffer_reg[36]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => r_push_r_reg(2),
Q => \skid_buffer_reg_n_0_[36]\,
R => '0'
);
\skid_buffer_reg[37]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => r_push_r_reg(3),
Q => \skid_buffer_reg_n_0_[37]\,
R => '0'
);
\skid_buffer_reg[38]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => r_push_r_reg(4),
Q => \skid_buffer_reg_n_0_[38]\,
R => '0'
);
\skid_buffer_reg[39]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => r_push_r_reg(5),
Q => \skid_buffer_reg_n_0_[39]\,
R => '0'
);
\skid_buffer_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(3),
Q => \skid_buffer_reg_n_0_[3]\,
R => '0'
);
\skid_buffer_reg[40]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => r_push_r_reg(6),
Q => \skid_buffer_reg_n_0_[40]\,
R => '0'
);
\skid_buffer_reg[41]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => r_push_r_reg(7),
Q => \skid_buffer_reg_n_0_[41]\,
R => '0'
);
\skid_buffer_reg[42]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => r_push_r_reg(8),
Q => \skid_buffer_reg_n_0_[42]\,
R => '0'
);
\skid_buffer_reg[43]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => r_push_r_reg(9),
Q => \skid_buffer_reg_n_0_[43]\,
R => '0'
);
\skid_buffer_reg[44]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => r_push_r_reg(10),
Q => \skid_buffer_reg_n_0_[44]\,
R => '0'
);
\skid_buffer_reg[45]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => r_push_r_reg(11),
Q => \skid_buffer_reg_n_0_[45]\,
R => '0'
);
\skid_buffer_reg[46]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => r_push_r_reg(12),
Q => \skid_buffer_reg_n_0_[46]\,
R => '0'
);
\skid_buffer_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(4),
Q => \skid_buffer_reg_n_0_[4]\,
R => '0'
);
\skid_buffer_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(5),
Q => \skid_buffer_reg_n_0_[5]\,
R => '0'
);
\skid_buffer_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(6),
Q => \skid_buffer_reg_n_0_[6]\,
R => '0'
);
\skid_buffer_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(7),
Q => \skid_buffer_reg_n_0_[7]\,
R => '0'
);
\skid_buffer_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(8),
Q => \skid_buffer_reg_n_0_[8]\,
R => '0'
);
\skid_buffer_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(9),
Q => \skid_buffer_reg_n_0_[9]\,
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity zybo_zynq_design_auto_pc_0_axi_protocol_converter_v2_1_17_b2s_b_channel is
port (
si_rs_bvalid : out STD_LOGIC;
\cnt_read_reg[0]_rep__0\ : out STD_LOGIC;
\cnt_read_reg[1]_rep__0\ : out STD_LOGIC;
m_axi_bready : out STD_LOGIC;
\out\ : out STD_LOGIC_VECTOR ( 11 downto 0 );
\skid_buffer_reg[1]\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
areset_d1 : in STD_LOGIC;
aclk : in STD_LOGIC;
b_push : in STD_LOGIC;
si_rs_bready : in STD_LOGIC;
m_axi_bvalid : in STD_LOGIC;
\in\ : in STD_LOGIC_VECTOR ( 15 downto 0 );
m_axi_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of zybo_zynq_design_auto_pc_0_axi_protocol_converter_v2_1_17_b2s_b_channel : entity is "axi_protocol_converter_v2_1_17_b2s_b_channel";
end zybo_zynq_design_auto_pc_0_axi_protocol_converter_v2_1_17_b2s_b_channel;
architecture STRUCTURE of zybo_zynq_design_auto_pc_0_axi_protocol_converter_v2_1_17_b2s_b_channel is
signal bid_fifo_0_n_3 : STD_LOGIC;
signal bid_fifo_0_n_5 : STD_LOGIC;
signal \bresp_cnt[7]_i_6_n_0\ : STD_LOGIC;
signal \bresp_cnt_reg__0\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal bresp_push : STD_LOGIC;
signal cnt_read : STD_LOGIC_VECTOR ( 1 downto 0 );
signal mhandshake : STD_LOGIC;
signal mhandshake_r : STD_LOGIC;
signal p_0_in : STD_LOGIC_VECTOR ( 7 downto 0 );
signal s_bresp_acc0 : STD_LOGIC;
signal \s_bresp_acc[0]_i_1_n_0\ : STD_LOGIC;
signal \s_bresp_acc[1]_i_1_n_0\ : STD_LOGIC;
signal \s_bresp_acc_reg_n_0_[0]\ : STD_LOGIC;
signal \s_bresp_acc_reg_n_0_[1]\ : STD_LOGIC;
signal shandshake : STD_LOGIC;
signal shandshake_r : STD_LOGIC;
signal \^si_rs_bvalid\ : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \bresp_cnt[1]_i_1\ : label is "soft_lutpair125";
attribute SOFT_HLUTNM of \bresp_cnt[2]_i_1\ : label is "soft_lutpair125";
attribute SOFT_HLUTNM of \bresp_cnt[3]_i_1\ : label is "soft_lutpair123";
attribute SOFT_HLUTNM of \bresp_cnt[4]_i_1\ : label is "soft_lutpair123";
attribute SOFT_HLUTNM of \bresp_cnt[6]_i_1\ : label is "soft_lutpair124";
attribute SOFT_HLUTNM of \bresp_cnt[7]_i_2\ : label is "soft_lutpair124";
begin
si_rs_bvalid <= \^si_rs_bvalid\;
bid_fifo_0: entity work.zybo_zynq_design_auto_pc_0_axi_protocol_converter_v2_1_17_b2s_simple_fifo
port map (
D(0) => bid_fifo_0_n_3,
Q(1 downto 0) => cnt_read(1 downto 0),
SR(0) => s_bresp_acc0,
aclk => aclk,
areset_d1 => areset_d1,
b_push => b_push,
\bresp_cnt_reg[7]\(7 downto 0) => \bresp_cnt_reg__0\(7 downto 0),
bresp_push => bresp_push,
bvalid_i_reg => bid_fifo_0_n_5,
bvalid_i_reg_0 => \^si_rs_bvalid\,
\cnt_read_reg[0]_rep__0_0\ => \cnt_read_reg[0]_rep__0\,
\cnt_read_reg[1]_rep__0_0\ => \cnt_read_reg[1]_rep__0\,
\in\(15 downto 0) => \in\(15 downto 0),
mhandshake_r => mhandshake_r,
\out\(11 downto 0) => \out\(11 downto 0),
shandshake_r => shandshake_r,
si_rs_bready => si_rs_bready
);
\bresp_cnt[0]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \bresp_cnt_reg__0\(0),
O => p_0_in(0)
);
\bresp_cnt[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \bresp_cnt_reg__0\(1),
I1 => \bresp_cnt_reg__0\(0),
O => p_0_in(1)
);
\bresp_cnt[2]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"6A"
)
port map (
I0 => \bresp_cnt_reg__0\(2),
I1 => \bresp_cnt_reg__0\(0),
I2 => \bresp_cnt_reg__0\(1),
O => p_0_in(2)
);
\bresp_cnt[3]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"6AAA"
)
port map (
I0 => \bresp_cnt_reg__0\(3),
I1 => \bresp_cnt_reg__0\(1),
I2 => \bresp_cnt_reg__0\(0),
I3 => \bresp_cnt_reg__0\(2),
O => p_0_in(3)
);
\bresp_cnt[4]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"6AAAAAAA"
)
port map (
I0 => \bresp_cnt_reg__0\(4),
I1 => \bresp_cnt_reg__0\(2),
I2 => \bresp_cnt_reg__0\(0),
I3 => \bresp_cnt_reg__0\(1),
I4 => \bresp_cnt_reg__0\(3),
O => p_0_in(4)
);
\bresp_cnt[5]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"6AAAAAAAAAAAAAAA"
)
port map (
I0 => \bresp_cnt_reg__0\(5),
I1 => \bresp_cnt_reg__0\(3),
I2 => \bresp_cnt_reg__0\(1),
I3 => \bresp_cnt_reg__0\(0),
I4 => \bresp_cnt_reg__0\(2),
I5 => \bresp_cnt_reg__0\(4),
O => p_0_in(5)
);
\bresp_cnt[6]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \bresp_cnt_reg__0\(6),
I1 => \bresp_cnt[7]_i_6_n_0\,
O => p_0_in(6)
);
\bresp_cnt[7]_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"6A"
)
port map (
I0 => \bresp_cnt_reg__0\(7),
I1 => \bresp_cnt[7]_i_6_n_0\,
I2 => \bresp_cnt_reg__0\(6),
O => p_0_in(7)
);
\bresp_cnt[7]_i_6\: unisim.vcomponents.LUT6
generic map(
INIT => X"8000000000000000"
)
port map (
I0 => \bresp_cnt_reg__0\(5),
I1 => \bresp_cnt_reg__0\(3),
I2 => \bresp_cnt_reg__0\(1),
I3 => \bresp_cnt_reg__0\(0),
I4 => \bresp_cnt_reg__0\(2),
I5 => \bresp_cnt_reg__0\(4),
O => \bresp_cnt[7]_i_6_n_0\
);
\bresp_cnt_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => mhandshake_r,
D => p_0_in(0),
Q => \bresp_cnt_reg__0\(0),
R => s_bresp_acc0
);
\bresp_cnt_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => mhandshake_r,
D => p_0_in(1),
Q => \bresp_cnt_reg__0\(1),
R => s_bresp_acc0
);
\bresp_cnt_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => mhandshake_r,
D => p_0_in(2),
Q => \bresp_cnt_reg__0\(2),
R => s_bresp_acc0
);
\bresp_cnt_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => mhandshake_r,
D => p_0_in(3),
Q => \bresp_cnt_reg__0\(3),
R => s_bresp_acc0
);
\bresp_cnt_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => mhandshake_r,
D => p_0_in(4),
Q => \bresp_cnt_reg__0\(4),
R => s_bresp_acc0
);
\bresp_cnt_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => mhandshake_r,
D => p_0_in(5),
Q => \bresp_cnt_reg__0\(5),
R => s_bresp_acc0
);
\bresp_cnt_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => mhandshake_r,
D => p_0_in(6),
Q => \bresp_cnt_reg__0\(6),
R => s_bresp_acc0
);
\bresp_cnt_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => mhandshake_r,
D => p_0_in(7),
Q => \bresp_cnt_reg__0\(7),
R => s_bresp_acc0
);
bresp_fifo_0: entity work.\zybo_zynq_design_auto_pc_0_axi_protocol_converter_v2_1_17_b2s_simple_fifo__parameterized0\
port map (
D(0) => bid_fifo_0_n_3,
Q(1 downto 0) => cnt_read(1 downto 0),
aclk => aclk,
areset_d1 => areset_d1,
\in\(1) => \s_bresp_acc_reg_n_0_[1]\,
\in\(0) => \s_bresp_acc_reg_n_0_[0]\,
m_axi_bready => m_axi_bready,
m_axi_bvalid => m_axi_bvalid,
mhandshake => mhandshake,
mhandshake_r => mhandshake_r,
sel => bresp_push,
shandshake_r => shandshake_r,
\skid_buffer_reg[1]\(1 downto 0) => \skid_buffer_reg[1]\(1 downto 0)
);
bvalid_i_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => bid_fifo_0_n_5,
Q => \^si_rs_bvalid\,
R => '0'
);
mhandshake_r_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => mhandshake,
Q => mhandshake_r,
R => areset_d1
);
\s_bresp_acc[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000EACEAAAA"
)
port map (
I0 => \s_bresp_acc_reg_n_0_[0]\,
I1 => m_axi_bresp(0),
I2 => m_axi_bresp(1),
I3 => \s_bresp_acc_reg_n_0_[1]\,
I4 => mhandshake,
I5 => s_bresp_acc0,
O => \s_bresp_acc[0]_i_1_n_0\
);
\s_bresp_acc[1]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"00EC"
)
port map (
I0 => m_axi_bresp(1),
I1 => \s_bresp_acc_reg_n_0_[1]\,
I2 => mhandshake,
I3 => s_bresp_acc0,
O => \s_bresp_acc[1]_i_1_n_0\
);
\s_bresp_acc_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \s_bresp_acc[0]_i_1_n_0\,
Q => \s_bresp_acc_reg_n_0_[0]\,
R => '0'
);
\s_bresp_acc_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \s_bresp_acc[1]_i_1_n_0\,
Q => \s_bresp_acc_reg_n_0_[1]\,
R => '0'
);
shandshake_r_i_1: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \^si_rs_bvalid\,
I1 => si_rs_bready,
O => shandshake
);
shandshake_r_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => shandshake,
Q => shandshake_r,
R => areset_d1
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity zybo_zynq_design_auto_pc_0_axi_protocol_converter_v2_1_17_b2s_cmd_translator is
port (
next_pending_r_reg : out STD_LOGIC;
wrap_next_pending : out STD_LOGIC;
sel_first_reg_0 : out STD_LOGIC;
sel_first_0 : out STD_LOGIC;
sel_first : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 0 to 0 );
\axlen_cnt_reg[2]\ : out STD_LOGIC;
\wrap_cnt_r_reg[3]\ : out STD_LOGIC;
\wrap_second_len_r_reg[3]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
\state_reg[1]_rep\ : out STD_LOGIC;
m_axi_awaddr : out STD_LOGIC_VECTOR ( 11 downto 0 );
\axaddr_offset_r_reg[3]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
S : out STD_LOGIC_VECTOR ( 3 downto 0 );
incr_next_pending : in STD_LOGIC;
aclk : in STD_LOGIC;
sel_first_i : in STD_LOGIC;
\m_payload_i_reg[39]\ : in STD_LOGIC;
\m_payload_i_reg[39]_0\ : in STD_LOGIC;
sel_first_reg_1 : in STD_LOGIC;
sel_first_reg_2 : in STD_LOGIC;
E : in STD_LOGIC_VECTOR ( 0 to 0 );
\m_payload_i_reg[47]\ : in STD_LOGIC_VECTOR ( 19 downto 0 );
\state_reg[1]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
si_rs_awvalid : in STD_LOGIC;
\axaddr_offset_r_reg[3]_0\ : in STD_LOGIC;
D : in STD_LOGIC_VECTOR ( 3 downto 0 );
\m_payload_i_reg[47]_0\ : in STD_LOGIC;
\m_payload_i_reg[47]_1\ : in STD_LOGIC;
\next\ : in STD_LOGIC;
axaddr_incr : in STD_LOGIC_VECTOR ( 11 downto 0 );
\wrap_second_len_r_reg[3]_0\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
\axaddr_offset_r_reg[3]_1\ : in STD_LOGIC;
\state_reg[0]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\state_reg[1]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\state_reg[0]_rep\ : in STD_LOGIC;
\wrap_second_len_r_reg[3]_1\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\m_payload_i_reg[6]\ : in STD_LOGIC_VECTOR ( 6 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of zybo_zynq_design_auto_pc_0_axi_protocol_converter_v2_1_17_b2s_cmd_translator : entity is "axi_protocol_converter_v2_1_17_b2s_cmd_translator";
end zybo_zynq_design_auto_pc_0_axi_protocol_converter_v2_1_17_b2s_cmd_translator;
architecture STRUCTURE of zybo_zynq_design_auto_pc_0_axi_protocol_converter_v2_1_17_b2s_cmd_translator is
signal incr_cmd_0_n_10 : STD_LOGIC;
signal incr_cmd_0_n_11 : STD_LOGIC;
signal incr_cmd_0_n_12 : STD_LOGIC;
signal incr_cmd_0_n_13 : STD_LOGIC;
signal incr_cmd_0_n_14 : STD_LOGIC;
signal incr_cmd_0_n_15 : STD_LOGIC;
signal incr_cmd_0_n_16 : STD_LOGIC;
signal incr_cmd_0_n_4 : STD_LOGIC;
signal incr_cmd_0_n_5 : STD_LOGIC;
signal incr_cmd_0_n_6 : STD_LOGIC;
signal incr_cmd_0_n_7 : STD_LOGIC;
signal incr_cmd_0_n_8 : STD_LOGIC;
signal incr_cmd_0_n_9 : STD_LOGIC;
signal s_axburst_eq0 : STD_LOGIC;
signal s_axburst_eq1 : STD_LOGIC;
begin
incr_cmd_0: entity work.zybo_zynq_design_auto_pc_0_axi_protocol_converter_v2_1_17_b2s_incr_cmd
port map (
E(0) => E(0),
Q(0) => Q(0),
S(3 downto 0) => S(3 downto 0),
aclk => aclk,
axaddr_incr(11 downto 0) => axaddr_incr(11 downto 0),
\axaddr_incr_reg[0]_0\ => sel_first_0,
\axaddr_incr_reg[11]_0\(10) => incr_cmd_0_n_4,
\axaddr_incr_reg[11]_0\(9) => incr_cmd_0_n_5,
\axaddr_incr_reg[11]_0\(8) => incr_cmd_0_n_6,
\axaddr_incr_reg[11]_0\(7) => incr_cmd_0_n_7,
\axaddr_incr_reg[11]_0\(6) => incr_cmd_0_n_8,
\axaddr_incr_reg[11]_0\(5) => incr_cmd_0_n_9,
\axaddr_incr_reg[11]_0\(4) => incr_cmd_0_n_10,
\axaddr_incr_reg[11]_0\(3) => incr_cmd_0_n_11,
\axaddr_incr_reg[11]_0\(2) => incr_cmd_0_n_12,
\axaddr_incr_reg[11]_0\(1) => incr_cmd_0_n_13,
\axaddr_incr_reg[11]_0\(0) => incr_cmd_0_n_14,
\axlen_cnt_reg[2]_0\ => \axlen_cnt_reg[2]\,
incr_next_pending => incr_next_pending,
\m_axi_awaddr[11]\ => incr_cmd_0_n_15,
\m_axi_awaddr[5]\ => incr_cmd_0_n_16,
\m_payload_i_reg[46]\(9 downto 8) => \m_payload_i_reg[47]\(18 downto 17),
\m_payload_i_reg[46]\(7 downto 5) => \m_payload_i_reg[47]\(14 downto 12),
\m_payload_i_reg[46]\(4) => \m_payload_i_reg[47]\(5),
\m_payload_i_reg[46]\(3 downto 0) => \m_payload_i_reg[47]\(3 downto 0),
\m_payload_i_reg[47]\ => \m_payload_i_reg[47]_0\,
\next\ => \next\,
next_pending_r_reg_0 => next_pending_r_reg,
sel_first_reg_0 => sel_first_reg_1,
\state_reg[0]\(0) => \state_reg[0]\(0),
\state_reg[0]_rep\ => \state_reg[0]_rep\,
\state_reg[1]\(0) => \state_reg[1]_0\(0)
);
\memory_reg[3][0]_srl4_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axburst_eq1,
I1 => \m_payload_i_reg[47]\(15),
I2 => s_axburst_eq0,
O => \state_reg[1]_rep\
);
s_axburst_eq0_reg: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_payload_i_reg[39]\,
Q => s_axburst_eq0,
R => '0'
);
s_axburst_eq1_reg: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_payload_i_reg[39]_0\,
Q => s_axburst_eq1,
R => '0'
);
sel_first_reg: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => sel_first_i,
Q => sel_first_reg_0,
R => '0'
);
wrap_cmd_0: entity work.zybo_zynq_design_auto_pc_0_axi_protocol_converter_v2_1_17_b2s_wrap_cmd
port map (
D(3 downto 0) => D(3 downto 0),
E(0) => E(0),
aclk => aclk,
\axaddr_incr_reg[11]\(10) => incr_cmd_0_n_4,
\axaddr_incr_reg[11]\(9) => incr_cmd_0_n_5,
\axaddr_incr_reg[11]\(8) => incr_cmd_0_n_6,
\axaddr_incr_reg[11]\(7) => incr_cmd_0_n_7,
\axaddr_incr_reg[11]\(6) => incr_cmd_0_n_8,
\axaddr_incr_reg[11]\(5) => incr_cmd_0_n_9,
\axaddr_incr_reg[11]\(4) => incr_cmd_0_n_10,
\axaddr_incr_reg[11]\(3) => incr_cmd_0_n_11,
\axaddr_incr_reg[11]\(2) => incr_cmd_0_n_12,
\axaddr_incr_reg[11]\(1) => incr_cmd_0_n_13,
\axaddr_incr_reg[11]\(0) => incr_cmd_0_n_14,
\axaddr_offset_r_reg[3]_0\(3 downto 0) => \axaddr_offset_r_reg[3]\(3 downto 0),
\axaddr_offset_r_reg[3]_1\ => \axaddr_offset_r_reg[3]_0\,
\axaddr_offset_r_reg[3]_2\ => \axaddr_offset_r_reg[3]_1\,
m_axi_awaddr(11 downto 0) => m_axi_awaddr(11 downto 0),
\m_payload_i_reg[47]\(18 downto 14) => \m_payload_i_reg[47]\(19 downto 15),
\m_payload_i_reg[47]\(13 downto 0) => \m_payload_i_reg[47]\(13 downto 0),
\m_payload_i_reg[47]_0\ => \m_payload_i_reg[47]_1\,
\m_payload_i_reg[6]\(6 downto 0) => \m_payload_i_reg[6]\(6 downto 0),
\next\ => \next\,
sel_first_reg_0 => sel_first,
sel_first_reg_1 => sel_first_reg_2,
sel_first_reg_2 => incr_cmd_0_n_15,
sel_first_reg_3 => incr_cmd_0_n_16,
si_rs_awvalid => si_rs_awvalid,
\state_reg[0]\(0) => \state_reg[0]\(0),
\state_reg[1]\(1 downto 0) => \state_reg[1]\(1 downto 0),
\wrap_cnt_r_reg[3]_0\ => \wrap_cnt_r_reg[3]\,
wrap_next_pending => wrap_next_pending,
\wrap_second_len_r_reg[3]_0\(3 downto 0) => \wrap_second_len_r_reg[3]\(3 downto 0),
\wrap_second_len_r_reg[3]_1\(3 downto 0) => \wrap_second_len_r_reg[3]_1\(3 downto 0),
\wrap_second_len_r_reg[3]_2\(2 downto 0) => \wrap_second_len_r_reg[3]_0\(2 downto 0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity zybo_zynq_design_auto_pc_0_axi_protocol_converter_v2_1_17_b2s_cmd_translator_1 is
port (
sel_first_reg_0 : out STD_LOGIC;
sel_first : out STD_LOGIC;
sel_first_reg_1 : out STD_LOGIC;
\axlen_cnt_reg[0]\ : out STD_LOGIC;
\wrap_cnt_r_reg[3]\ : out STD_LOGIC;
\wrap_second_len_r_reg[3]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
r_rlast : out STD_LOGIC;
\state_reg[0]_rep\ : out STD_LOGIC;
m_axi_araddr : out STD_LOGIC_VECTOR ( 11 downto 0 );
\axaddr_offset_r_reg[3]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
S : out STD_LOGIC_VECTOR ( 3 downto 0 );
aclk : in STD_LOGIC;
sel_first_i : in STD_LOGIC;
sel_first_reg_2 : in STD_LOGIC;
sel_first_reg_3 : in STD_LOGIC;
E : in STD_LOGIC_VECTOR ( 0 to 0 );
Q : in STD_LOGIC_VECTOR ( 19 downto 0 );
\state_reg[1]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
si_rs_arvalid : in STD_LOGIC;
\m_payload_i_reg[47]\ : in STD_LOGIC;
\axaddr_offset_r_reg[3]_0\ : in STD_LOGIC;
D : in STD_LOGIC_VECTOR ( 3 downto 0 );
\m_payload_i_reg[47]_0\ : in STD_LOGIC;
\state_reg[1]_rep\ : in STD_LOGIC;
O : in STD_LOGIC_VECTOR ( 3 downto 0 );
\m_payload_i_reg[7]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\m_payload_i_reg[3]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\state_reg[0]_rep_0\ : in STD_LOGIC;
\axaddr_offset_r_reg[3]_1\ : in STD_LOGIC;
m_valid_i_reg : in STD_LOGIC_VECTOR ( 0 to 0 );
\state_reg[1]_0\ : in STD_LOGIC;
\wrap_second_len_r_reg[3]_0\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\wrap_second_len_r_reg[3]_1\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
\m_payload_i_reg[6]\ : in STD_LOGIC_VECTOR ( 6 downto 0 );
sel_first_reg_4 : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_arready : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of zybo_zynq_design_auto_pc_0_axi_protocol_converter_v2_1_17_b2s_cmd_translator_1 : entity is "axi_protocol_converter_v2_1_17_b2s_cmd_translator";
end zybo_zynq_design_auto_pc_0_axi_protocol_converter_v2_1_17_b2s_cmd_translator_1;
architecture STRUCTURE of zybo_zynq_design_auto_pc_0_axi_protocol_converter_v2_1_17_b2s_cmd_translator_1 is
signal incr_cmd_0_n_10 : STD_LOGIC;
signal incr_cmd_0_n_11 : STD_LOGIC;
signal incr_cmd_0_n_12 : STD_LOGIC;
signal incr_cmd_0_n_13 : STD_LOGIC;
signal incr_cmd_0_n_14 : STD_LOGIC;
signal incr_cmd_0_n_15 : STD_LOGIC;
signal incr_cmd_0_n_3 : STD_LOGIC;
signal incr_cmd_0_n_4 : STD_LOGIC;
signal incr_cmd_0_n_5 : STD_LOGIC;
signal incr_cmd_0_n_6 : STD_LOGIC;
signal incr_cmd_0_n_7 : STD_LOGIC;
signal incr_cmd_0_n_8 : STD_LOGIC;
signal incr_cmd_0_n_9 : STD_LOGIC;
signal incr_next_pending : STD_LOGIC;
signal s_axburst_eq0 : STD_LOGIC;
signal s_axburst_eq1 : STD_LOGIC;
signal wrap_cmd_0_n_6 : STD_LOGIC;
signal wrap_cmd_0_n_7 : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of r_rlast_r_i_1 : label is "soft_lutpair17";
attribute SOFT_HLUTNM of \state[1]_i_3\ : label is "soft_lutpair17";
begin
incr_cmd_0: entity work.zybo_zynq_design_auto_pc_0_axi_protocol_converter_v2_1_17_b2s_incr_cmd_2
port map (
E(0) => E(0),
O(3 downto 0) => O(3 downto 0),
Q(10 downto 8) => Q(18 downto 16),
Q(7 downto 5) => Q(14 downto 12),
Q(4) => Q(5),
Q(3 downto 0) => Q(3 downto 0),
S(3 downto 0) => S(3 downto 0),
aclk => aclk,
\axaddr_incr_reg[0]_0\ => sel_first,
\axaddr_incr_reg[11]_0\(7) => incr_cmd_0_n_3,
\axaddr_incr_reg[11]_0\(6) => incr_cmd_0_n_4,
\axaddr_incr_reg[11]_0\(5) => incr_cmd_0_n_5,
\axaddr_incr_reg[11]_0\(4) => incr_cmd_0_n_6,
\axaddr_incr_reg[11]_0\(3) => incr_cmd_0_n_7,
\axaddr_incr_reg[11]_0\(2) => incr_cmd_0_n_8,
\axaddr_incr_reg[11]_0\(1) => incr_cmd_0_n_9,
\axaddr_incr_reg[11]_0\(0) => incr_cmd_0_n_10,
\axlen_cnt_reg[0]_0\ => \axlen_cnt_reg[0]\,
incr_next_pending => incr_next_pending,
\m_axi_araddr[11]\ => incr_cmd_0_n_11,
\m_axi_araddr[1]\ => incr_cmd_0_n_15,
\m_axi_araddr[2]\ => incr_cmd_0_n_14,
\m_axi_araddr[3]\ => incr_cmd_0_n_13,
\m_axi_araddr[5]\ => incr_cmd_0_n_12,
m_axi_arready => m_axi_arready,
\m_payload_i_reg[3]\(3 downto 0) => \m_payload_i_reg[3]\(3 downto 0),
\m_payload_i_reg[47]\ => \m_payload_i_reg[47]\,
\m_payload_i_reg[47]_0\ => \m_payload_i_reg[47]_0\,
\m_payload_i_reg[7]\(3 downto 0) => \m_payload_i_reg[7]\(3 downto 0),
m_valid_i_reg(0) => m_valid_i_reg(0),
sel_first_reg_0 => sel_first_reg_2,
sel_first_reg_1(0) => sel_first_reg_4(0),
si_rs_arvalid => si_rs_arvalid,
\state_reg[0]_rep\ => \state_reg[0]_rep_0\,
\state_reg[1]\ => \state_reg[1]_0\,
\state_reg[1]_0\(1 downto 0) => \state_reg[1]\(1 downto 0),
\state_reg[1]_rep\ => \state_reg[1]_rep\
);
r_rlast_r_i_1: unisim.vcomponents.LUT3
generic map(
INIT => X"1D"
)
port map (
I0 => s_axburst_eq0,
I1 => Q(15),
I2 => s_axburst_eq1,
O => r_rlast
);
s_axburst_eq0_reg: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => wrap_cmd_0_n_6,
Q => s_axburst_eq0,
R => '0'
);
s_axburst_eq1_reg: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => wrap_cmd_0_n_7,
Q => s_axburst_eq1,
R => '0'
);
sel_first_reg: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => sel_first_i,
Q => sel_first_reg_0,
R => '0'
);
\state[1]_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axburst_eq1,
I1 => Q(15),
I2 => s_axburst_eq0,
O => \state_reg[0]_rep\
);
wrap_cmd_0: entity work.zybo_zynq_design_auto_pc_0_axi_protocol_converter_v2_1_17_b2s_wrap_cmd_3
port map (
D(3 downto 0) => D(3 downto 0),
E(0) => E(0),
Q(18 downto 14) => Q(19 downto 15),
Q(13 downto 0) => Q(13 downto 0),
aclk => aclk,
\axaddr_incr_reg[11]\(7) => incr_cmd_0_n_3,
\axaddr_incr_reg[11]\(6) => incr_cmd_0_n_4,
\axaddr_incr_reg[11]\(5) => incr_cmd_0_n_5,
\axaddr_incr_reg[11]\(4) => incr_cmd_0_n_6,
\axaddr_incr_reg[11]\(3) => incr_cmd_0_n_7,
\axaddr_incr_reg[11]\(2) => incr_cmd_0_n_8,
\axaddr_incr_reg[11]\(1) => incr_cmd_0_n_9,
\axaddr_incr_reg[11]\(0) => incr_cmd_0_n_10,
\axaddr_offset_r_reg[3]_0\(3 downto 0) => \axaddr_offset_r_reg[3]\(3 downto 0),
\axaddr_offset_r_reg[3]_1\ => \axaddr_offset_r_reg[3]_0\,
\axaddr_offset_r_reg[3]_2\ => \axaddr_offset_r_reg[3]_1\,
incr_next_pending => incr_next_pending,
m_axi_araddr(11 downto 0) => m_axi_araddr(11 downto 0),
\m_payload_i_reg[47]\ => \m_payload_i_reg[47]_0\,
\m_payload_i_reg[6]\(6 downto 0) => \m_payload_i_reg[6]\(6 downto 0),
m_valid_i_reg(0) => m_valid_i_reg(0),
s_axburst_eq0_reg => wrap_cmd_0_n_6,
s_axburst_eq1_reg => wrap_cmd_0_n_7,
sel_first_i => sel_first_i,
sel_first_reg_0 => sel_first_reg_1,
sel_first_reg_1 => sel_first_reg_3,
sel_first_reg_2 => incr_cmd_0_n_11,
sel_first_reg_3 => incr_cmd_0_n_12,
sel_first_reg_4 => incr_cmd_0_n_13,
sel_first_reg_5 => incr_cmd_0_n_14,
sel_first_reg_6 => incr_cmd_0_n_15,
si_rs_arvalid => si_rs_arvalid,
\state_reg[1]\(1 downto 0) => \state_reg[1]\(1 downto 0),
\state_reg[1]_rep\ => \state_reg[1]_rep\,
\wrap_cnt_r_reg[3]_0\ => \wrap_cnt_r_reg[3]\,
\wrap_second_len_r_reg[3]_0\(3 downto 0) => \wrap_second_len_r_reg[3]\(3 downto 0),
\wrap_second_len_r_reg[3]_1\(3 downto 0) => \wrap_second_len_r_reg[3]_0\(3 downto 0),
\wrap_second_len_r_reg[3]_2\(2 downto 0) => \wrap_second_len_r_reg[3]_1\(2 downto 0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity zybo_zynq_design_auto_pc_0_axi_protocol_converter_v2_1_17_b2s_r_channel is
port (
m_valid_i_reg : out STD_LOGIC;
\state_reg[1]_rep\ : out STD_LOGIC;
m_axi_rready : out STD_LOGIC;
\out\ : out STD_LOGIC_VECTOR ( 33 downto 0 );
\skid_buffer_reg[46]\ : out STD_LOGIC_VECTOR ( 12 downto 0 );
\state_reg[1]_rep_0\ : in STD_LOGIC;
aclk : in STD_LOGIC;
r_rlast : in STD_LOGIC;
s_ready_i_reg : in STD_LOGIC;
si_rs_rready : in STD_LOGIC;
m_axi_rvalid : in STD_LOGIC;
\in\ : in STD_LOGIC_VECTOR ( 33 downto 0 );
areset_d1 : in STD_LOGIC;
D : in STD_LOGIC_VECTOR ( 11 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of zybo_zynq_design_auto_pc_0_axi_protocol_converter_v2_1_17_b2s_r_channel : entity is "axi_protocol_converter_v2_1_17_b2s_r_channel";
end zybo_zynq_design_auto_pc_0_axi_protocol_converter_v2_1_17_b2s_r_channel;
architecture STRUCTURE of zybo_zynq_design_auto_pc_0_axi_protocol_converter_v2_1_17_b2s_r_channel is
signal \^m_valid_i_reg\ : STD_LOGIC;
signal r_push_r : STD_LOGIC;
signal rd_data_fifo_0_n_0 : STD_LOGIC;
signal rd_data_fifo_0_n_1 : STD_LOGIC;
signal rd_data_fifo_0_n_2 : STD_LOGIC;
signal rd_data_fifo_0_n_4 : STD_LOGIC;
signal trans_in : STD_LOGIC_VECTOR ( 12 downto 0 );
begin
m_valid_i_reg <= \^m_valid_i_reg\;
\r_arid_r_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => D(0),
Q => trans_in(1),
R => '0'
);
\r_arid_r_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => D(10),
Q => trans_in(11),
R => '0'
);
\r_arid_r_reg[11]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => D(11),
Q => trans_in(12),
R => '0'
);
\r_arid_r_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => D(1),
Q => trans_in(2),
R => '0'
);
\r_arid_r_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => D(2),
Q => trans_in(3),
R => '0'
);
\r_arid_r_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => D(3),
Q => trans_in(4),
R => '0'
);
\r_arid_r_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => D(4),
Q => trans_in(5),
R => '0'
);
\r_arid_r_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => D(5),
Q => trans_in(6),
R => '0'
);
\r_arid_r_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => D(6),
Q => trans_in(7),
R => '0'
);
\r_arid_r_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => D(7),
Q => trans_in(8),
R => '0'
);
\r_arid_r_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => D(8),
Q => trans_in(9),
R => '0'
);
\r_arid_r_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => D(9),
Q => trans_in(10),
R => '0'
);
r_push_r_reg: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \state_reg[1]_rep_0\,
Q => r_push_r,
R => '0'
);
r_rlast_r_reg: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => r_rlast,
Q => trans_in(0),
R => '0'
);
rd_data_fifo_0: entity work.\zybo_zynq_design_auto_pc_0_axi_protocol_converter_v2_1_17_b2s_simple_fifo__parameterized1\
port map (
aclk => aclk,
areset_d1 => areset_d1,
\cnt_read_reg[4]_rep__0_0\ => \^m_valid_i_reg\,
\cnt_read_reg[4]_rep__2_0\ => rd_data_fifo_0_n_0,
\cnt_read_reg[4]_rep__2_1\ => rd_data_fifo_0_n_1,
\cnt_read_reg[4]_rep__2_2\ => rd_data_fifo_0_n_2,
\in\(33 downto 0) => \in\(33 downto 0),
m_axi_rready => m_axi_rready,
m_axi_rvalid => m_axi_rvalid,
\out\(33 downto 0) => \out\(33 downto 0),
s_ready_i_reg => s_ready_i_reg,
si_rs_rready => si_rs_rready,
\state_reg[1]_rep\ => rd_data_fifo_0_n_4
);
transaction_fifo_0: entity work.\zybo_zynq_design_auto_pc_0_axi_protocol_converter_v2_1_17_b2s_simple_fifo__parameterized2\
port map (
aclk => aclk,
areset_d1 => areset_d1,
\cnt_read_reg[0]_rep__3\ => rd_data_fifo_0_n_2,
\cnt_read_reg[0]_rep__3_0\ => rd_data_fifo_0_n_4,
\cnt_read_reg[3]_rep__2\ => rd_data_fifo_0_n_0,
\cnt_read_reg[4]_rep__2\ => rd_data_fifo_0_n_1,
\in\(12 downto 0) => trans_in(12 downto 0),
m_valid_i_reg => \^m_valid_i_reg\,
r_push_r => r_push_r,
s_ready_i_reg => s_ready_i_reg,
si_rs_rready => si_rs_rready,
\skid_buffer_reg[46]\(12 downto 0) => \skid_buffer_reg[46]\(12 downto 0),
\state_reg[1]_rep\ => \state_reg[1]_rep\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity zybo_zynq_design_auto_pc_0_axi_register_slice_v2_1_17_axi_register_slice is
port (
s_axi_awready : out STD_LOGIC;
s_axi_arready : out STD_LOGIC;
si_rs_awvalid : out STD_LOGIC;
s_axi_bvalid : out STD_LOGIC;
si_rs_bready : out STD_LOGIC;
si_rs_arvalid : out STD_LOGIC;
s_axi_rvalid : out STD_LOGIC;
si_rs_rready : out STD_LOGIC;
\axlen_cnt_reg[3]\ : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 54 downto 0 );
\axlen_cnt_reg[3]_0\ : out STD_LOGIC;
\s_arid_r_reg[11]\ : out STD_LOGIC_VECTOR ( 54 downto 0 );
axaddr_incr : out STD_LOGIC_VECTOR ( 11 downto 0 );
\axaddr_incr_reg[3]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
\axaddr_incr_reg[7]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
O : out STD_LOGIC_VECTOR ( 3 downto 0 );
D : out STD_LOGIC_VECTOR ( 1 downto 0 );
\wrap_second_len_r_reg[3]\ : out STD_LOGIC_VECTOR ( 2 downto 0 );
\wrap_cnt_r_reg[2]\ : out STD_LOGIC;
axaddr_offset : out STD_LOGIC_VECTOR ( 2 downto 0 );
\wrap_cnt_r_reg[3]\ : out STD_LOGIC;
\axaddr_offset_r_reg[2]\ : out STD_LOGIC;
next_pending_r_reg : out STD_LOGIC;
\wrap_cnt_r_reg[3]_0\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
\wrap_second_len_r_reg[3]_0\ : out STD_LOGIC_VECTOR ( 2 downto 0 );
\wrap_cnt_r_reg[2]_0\ : out STD_LOGIC;
axaddr_offset_0 : out STD_LOGIC_VECTOR ( 2 downto 0 );
\wrap_cnt_r_reg[3]_1\ : out STD_LOGIC;
\axaddr_offset_r_reg[2]_0\ : out STD_LOGIC;
next_pending_r_reg_0 : out STD_LOGIC;
\cnt_read_reg[2]_rep__0\ : out STD_LOGIC;
\wrap_boundary_axaddr_r_reg[6]\ : out STD_LOGIC_VECTOR ( 6 downto 0 );
\wrap_boundary_axaddr_r_reg[6]_0\ : out STD_LOGIC_VECTOR ( 6 downto 0 );
\s_axi_bid[11]\ : out STD_LOGIC_VECTOR ( 13 downto 0 );
\s_axi_rid[11]\ : out STD_LOGIC_VECTOR ( 46 downto 0 );
aclk : in STD_LOGIC;
s_ready_i0 : in STD_LOGIC;
m_valid_i0 : in STD_LOGIC;
aresetn : in STD_LOGIC;
\state_reg[1]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
\state_reg[1]_0\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
\cnt_read_reg[4]_rep__0\ : in STD_LOGIC;
s_axi_rready : in STD_LOGIC;
S : in STD_LOGIC_VECTOR ( 3 downto 0 );
\m_payload_i_reg[3]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\wrap_second_len_r_reg[3]_1\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\state_reg[1]_rep\ : in STD_LOGIC;
\wrap_second_len_r_reg[1]\ : in STD_LOGIC;
\axaddr_offset_r_reg[2]_1\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\axaddr_offset_r_reg[3]\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
\axaddr_offset_r_reg[3]_0\ : in STD_LOGIC;
\axaddr_offset_r_reg[2]_2\ : in STD_LOGIC;
\state_reg[0]_rep\ : in STD_LOGIC;
\state_reg[1]_rep_0\ : in STD_LOGIC;
s_axi_awvalid : in STD_LOGIC;
b_push : in STD_LOGIC;
\wrap_second_len_r_reg[3]_2\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\state_reg[1]_rep_1\ : in STD_LOGIC;
\wrap_second_len_r_reg[1]_0\ : in STD_LOGIC;
\axaddr_offset_r_reg[2]_3\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\axaddr_offset_r_reg[3]_1\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
\axaddr_offset_r_reg[3]_2\ : in STD_LOGIC;
\axaddr_offset_r_reg[2]_4\ : in STD_LOGIC;
\state_reg[0]_rep_0\ : in STD_LOGIC;
\state_reg[1]_rep_2\ : in STD_LOGIC;
si_rs_bvalid : in STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_awid : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_awlen : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awsize : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_arid : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_arlen : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arsize : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
\out\ : in STD_LOGIC_VECTOR ( 11 downto 0 );
\s_bresp_acc_reg[1]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
r_push_r_reg : in STD_LOGIC_VECTOR ( 12 downto 0 );
\cnt_read_reg[4]\ : in STD_LOGIC_VECTOR ( 33 downto 0 );
E : in STD_LOGIC_VECTOR ( 0 to 0 );
m_valid_i_reg : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of zybo_zynq_design_auto_pc_0_axi_register_slice_v2_1_17_axi_register_slice : entity is "axi_register_slice_v2_1_17_axi_register_slice";
end zybo_zynq_design_auto_pc_0_axi_register_slice_v2_1_17_axi_register_slice;
architecture STRUCTURE of zybo_zynq_design_auto_pc_0_axi_register_slice_v2_1_17_axi_register_slice is
signal \ar.ar_pipe_n_2\ : STD_LOGIC;
signal \aw.aw_pipe_n_1\ : STD_LOGIC;
signal \aw.aw_pipe_n_90\ : STD_LOGIC;
begin
\ar.ar_pipe\: entity work.zybo_zynq_design_auto_pc_0_axi_register_slice_v2_1_17_axic_register_slice
port map (
O(3 downto 0) => O(3 downto 0),
Q(54 downto 0) => \s_arid_r_reg[11]\(54 downto 0),
aclk => aclk,
\aresetn_d_reg[0]\ => \aw.aw_pipe_n_1\,
\aresetn_d_reg[0]_0\ => \aw.aw_pipe_n_90\,
\axaddr_incr_reg[3]\(3 downto 0) => \axaddr_incr_reg[3]\(3 downto 0),
\axaddr_incr_reg[7]\(3 downto 0) => \axaddr_incr_reg[7]\(3 downto 0),
axaddr_offset_0(1 downto 0) => axaddr_offset_0(2 downto 1),
\axaddr_offset_r_reg[0]\ => axaddr_offset_0(0),
\axaddr_offset_r_reg[2]\ => \axaddr_offset_r_reg[2]_0\,
\axaddr_offset_r_reg[2]_0\(0) => \axaddr_offset_r_reg[2]_3\(0),
\axaddr_offset_r_reg[2]_1\ => \axaddr_offset_r_reg[2]_4\,
\axaddr_offset_r_reg[3]\ => si_rs_arvalid,
\axaddr_offset_r_reg[3]_0\(2 downto 0) => \axaddr_offset_r_reg[3]_1\(2 downto 0),
\axaddr_offset_r_reg[3]_1\ => \axaddr_offset_r_reg[3]_2\,
\axlen_cnt_reg[3]\ => \axlen_cnt_reg[3]_0\,
\m_payload_i_reg[3]_0\(3 downto 0) => \m_payload_i_reg[3]\(3 downto 0),
m_valid_i0 => m_valid_i0,
m_valid_i_reg_0 => \ar.ar_pipe_n_2\,
m_valid_i_reg_1(0) => m_valid_i_reg(0),
next_pending_r_reg => next_pending_r_reg_0,
s_axi_araddr(31 downto 0) => s_axi_araddr(31 downto 0),
s_axi_arburst(1 downto 0) => s_axi_arburst(1 downto 0),
s_axi_arid(11 downto 0) => s_axi_arid(11 downto 0),
s_axi_arlen(3 downto 0) => s_axi_arlen(3 downto 0),
s_axi_arprot(2 downto 0) => s_axi_arprot(2 downto 0),
s_axi_arready => s_axi_arready,
s_axi_arsize(1 downto 0) => s_axi_arsize(1 downto 0),
s_ready_i0 => s_ready_i0,
\state_reg[0]_rep\ => \state_reg[0]_rep_0\,
\state_reg[1]\(1 downto 0) => \state_reg[1]_0\(1 downto 0),
\state_reg[1]_rep\ => \state_reg[1]_rep_1\,
\state_reg[1]_rep_0\ => \state_reg[1]_rep_2\,
\wrap_boundary_axaddr_r_reg[6]\(6 downto 0) => \wrap_boundary_axaddr_r_reg[6]_0\(6 downto 0),
\wrap_cnt_r_reg[2]\ => \wrap_cnt_r_reg[2]_0\,
\wrap_cnt_r_reg[3]\(1 downto 0) => \wrap_cnt_r_reg[3]_0\(1 downto 0),
\wrap_cnt_r_reg[3]_0\ => \wrap_cnt_r_reg[3]_1\,
\wrap_second_len_r_reg[1]\ => \wrap_second_len_r_reg[1]_0\,
\wrap_second_len_r_reg[3]\(2 downto 0) => \wrap_second_len_r_reg[3]_0\(2 downto 0),
\wrap_second_len_r_reg[3]_0\(3 downto 0) => \wrap_second_len_r_reg[3]_2\(3 downto 0)
);
\aw.aw_pipe\: entity work.zybo_zynq_design_auto_pc_0_axi_register_slice_v2_1_17_axic_register_slice_0
port map (
D(1 downto 0) => D(1 downto 0),
E(0) => E(0),
Q(54 downto 0) => Q(54 downto 0),
S(3 downto 0) => S(3 downto 0),
aclk => aclk,
aresetn => aresetn,
\aresetn_d_reg[1]_inv\ => \aw.aw_pipe_n_90\,
\aresetn_d_reg[1]_inv_0\ => \ar.ar_pipe_n_2\,
axaddr_incr(11 downto 0) => axaddr_incr(11 downto 0),
axaddr_offset(1 downto 0) => axaddr_offset(2 downto 1),
\axaddr_offset_r_reg[0]\ => axaddr_offset(0),
\axaddr_offset_r_reg[2]\ => \axaddr_offset_r_reg[2]\,
\axaddr_offset_r_reg[2]_0\(0) => \axaddr_offset_r_reg[2]_1\(0),
\axaddr_offset_r_reg[2]_1\ => \axaddr_offset_r_reg[2]_2\,
\axaddr_offset_r_reg[3]\(2 downto 0) => \axaddr_offset_r_reg[3]\(2 downto 0),
\axaddr_offset_r_reg[3]_0\ => \axaddr_offset_r_reg[3]_0\,
\axlen_cnt_reg[3]\ => \axlen_cnt_reg[3]\,
b_push => b_push,
m_valid_i_reg_0 => si_rs_awvalid,
next_pending_r_reg => next_pending_r_reg,
s_axi_awaddr(31 downto 0) => s_axi_awaddr(31 downto 0),
s_axi_awburst(1 downto 0) => s_axi_awburst(1 downto 0),
s_axi_awid(11 downto 0) => s_axi_awid(11 downto 0),
s_axi_awlen(3 downto 0) => s_axi_awlen(3 downto 0),
s_axi_awprot(2 downto 0) => s_axi_awprot(2 downto 0),
s_axi_awready => s_axi_awready,
s_axi_awsize(1 downto 0) => s_axi_awsize(1 downto 0),
s_axi_awvalid => s_axi_awvalid,
s_ready_i_reg_0 => \aw.aw_pipe_n_1\,
\state_reg[0]_rep\ => \state_reg[0]_rep\,
\state_reg[1]\(1 downto 0) => \state_reg[1]\(1 downto 0),
\state_reg[1]_rep\ => \state_reg[1]_rep\,
\state_reg[1]_rep_0\ => \state_reg[1]_rep_0\,
\wrap_boundary_axaddr_r_reg[6]\(6 downto 0) => \wrap_boundary_axaddr_r_reg[6]\(6 downto 0),
\wrap_cnt_r_reg[2]\ => \wrap_cnt_r_reg[2]\,
\wrap_cnt_r_reg[3]\ => \wrap_cnt_r_reg[3]\,
\wrap_second_len_r_reg[1]\ => \wrap_second_len_r_reg[1]\,
\wrap_second_len_r_reg[3]\(2 downto 0) => \wrap_second_len_r_reg[3]\(2 downto 0),
\wrap_second_len_r_reg[3]_0\(3 downto 0) => \wrap_second_len_r_reg[3]_1\(3 downto 0)
);
\b.b_pipe\: entity work.\zybo_zynq_design_auto_pc_0_axi_register_slice_v2_1_17_axic_register_slice__parameterized1\
port map (
aclk => aclk,
\aresetn_d_reg[0]\ => \aw.aw_pipe_n_1\,
\aresetn_d_reg[1]_inv\ => \ar.ar_pipe_n_2\,
\out\(11 downto 0) => \out\(11 downto 0),
\s_axi_bid[11]\(13 downto 0) => \s_axi_bid[11]\(13 downto 0),
s_axi_bready => s_axi_bready,
s_axi_bvalid => s_axi_bvalid,
\s_bresp_acc_reg[1]\(1 downto 0) => \s_bresp_acc_reg[1]\(1 downto 0),
si_rs_bvalid => si_rs_bvalid,
\skid_buffer_reg[0]_0\ => si_rs_bready
);
\r.r_pipe\: entity work.\zybo_zynq_design_auto_pc_0_axi_register_slice_v2_1_17_axic_register_slice__parameterized2\
port map (
aclk => aclk,
\aresetn_d_reg[0]\ => \aw.aw_pipe_n_1\,
\aresetn_d_reg[1]_inv\ => \ar.ar_pipe_n_2\,
\cnt_read_reg[2]_rep__0\ => \cnt_read_reg[2]_rep__0\,
\cnt_read_reg[4]\(33 downto 0) => \cnt_read_reg[4]\(33 downto 0),
\cnt_read_reg[4]_rep__0\ => \cnt_read_reg[4]_rep__0\,
r_push_r_reg(12 downto 0) => r_push_r_reg(12 downto 0),
\s_axi_rid[11]\(46 downto 0) => \s_axi_rid[11]\(46 downto 0),
s_axi_rready => s_axi_rready,
s_axi_rvalid => s_axi_rvalid,
\skid_buffer_reg[0]_0\ => si_rs_rready
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity zybo_zynq_design_auto_pc_0_axi_protocol_converter_v2_1_17_b2s_ar_channel is
port (
\wrap_boundary_axaddr_r_reg[11]\ : out STD_LOGIC;
\state_reg[0]_rep\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
r_push_r_reg : out STD_LOGIC;
\m_payload_i_reg[0]\ : out STD_LOGIC;
\m_payload_i_reg[0]_0\ : out STD_LOGIC;
\wrap_second_len_r_reg[3]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
\wrap_cnt_r_reg[3]\ : out STD_LOGIC;
\wrap_cnt_r_reg[3]_0\ : out STD_LOGIC;
\axaddr_offset_r_reg[3]\ : out STD_LOGIC_VECTOR ( 2 downto 0 );
\axaddr_offset_r_reg[2]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\wrap_cnt_r_reg[3]_1\ : out STD_LOGIC;
m_axi_arvalid : out STD_LOGIC;
m_valid_i0 : out STD_LOGIC;
s_ready_i0 : out STD_LOGIC;
E : out STD_LOGIC_VECTOR ( 0 to 0 );
r_rlast : out STD_LOGIC;
m_axi_araddr : out STD_LOGIC_VECTOR ( 11 downto 0 );
\r_arid_r_reg[11]\ : out STD_LOGIC_VECTOR ( 11 downto 0 );
S : out STD_LOGIC_VECTOR ( 3 downto 0 );
aclk : in STD_LOGIC;
Q : in STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_arready : in STD_LOGIC;
si_rs_arvalid : in STD_LOGIC;
\cnt_read_reg[2]_rep__0\ : in STD_LOGIC;
\m_payload_i_reg[47]\ : in STD_LOGIC;
\axaddr_offset_r_reg[3]_0\ : in STD_LOGIC;
axaddr_offset : in STD_LOGIC_VECTOR ( 2 downto 0 );
\axaddr_offset_r_reg[3]_1\ : in STD_LOGIC;
D : in STD_LOGIC_VECTOR ( 2 downto 0 );
\m_payload_i_reg[47]_0\ : in STD_LOGIC;
areset_d1 : in STD_LOGIC;
\m_payload_i_reg[5]\ : in STD_LOGIC;
s_axi_arvalid : in STD_LOGIC;
s_ready_i_reg : in STD_LOGIC;
O : in STD_LOGIC_VECTOR ( 3 downto 0 );
\m_payload_i_reg[7]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\m_payload_i_reg[3]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\wrap_second_len_r_reg[3]_0\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
\m_payload_i_reg[6]\ : in STD_LOGIC_VECTOR ( 6 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of zybo_zynq_design_auto_pc_0_axi_protocol_converter_v2_1_17_b2s_ar_channel : entity is "axi_protocol_converter_v2_1_17_b2s_ar_channel";
end zybo_zynq_design_auto_pc_0_axi_protocol_converter_v2_1_17_b2s_ar_channel;
architecture STRUCTURE of zybo_zynq_design_auto_pc_0_axi_protocol_converter_v2_1_17_b2s_ar_channel is
signal ar_cmd_fsm_0_n_0 : STD_LOGIC;
signal ar_cmd_fsm_0_n_10 : STD_LOGIC;
signal ar_cmd_fsm_0_n_16 : STD_LOGIC;
signal ar_cmd_fsm_0_n_6 : STD_LOGIC;
signal ar_cmd_fsm_0_n_8 : STD_LOGIC;
signal ar_cmd_fsm_0_n_9 : STD_LOGIC;
signal \^axaddr_offset_r_reg[2]\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \^axaddr_offset_r_reg[3]\ : STD_LOGIC_VECTOR ( 2 downto 0 );
signal cmd_translator_0_n_0 : STD_LOGIC;
signal cmd_translator_0_n_10 : STD_LOGIC;
signal cmd_translator_0_n_2 : STD_LOGIC;
signal cmd_translator_0_n_3 : STD_LOGIC;
signal \incr_cmd_0/sel_first\ : STD_LOGIC;
signal \^m_payload_i_reg[0]_0\ : STD_LOGIC;
signal \^r_push_r_reg\ : STD_LOGIC;
signal sel_first_i : STD_LOGIC;
signal \^state_reg[0]_rep\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \^wrap_boundary_axaddr_r_reg[11]\ : STD_LOGIC;
signal \wrap_cmd_0/axaddr_offset_r\ : STD_LOGIC_VECTOR ( 2 to 2 );
signal \wrap_cmd_0/wrap_second_len\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \^wrap_second_len_r_reg[3]\ : STD_LOGIC_VECTOR ( 3 downto 0 );
begin
\axaddr_offset_r_reg[2]\(0) <= \^axaddr_offset_r_reg[2]\(0);
\axaddr_offset_r_reg[3]\(2 downto 0) <= \^axaddr_offset_r_reg[3]\(2 downto 0);
\m_payload_i_reg[0]_0\ <= \^m_payload_i_reg[0]_0\;
r_push_r_reg <= \^r_push_r_reg\;
\state_reg[0]_rep\(1 downto 0) <= \^state_reg[0]_rep\(1 downto 0);
\wrap_boundary_axaddr_r_reg[11]\ <= \^wrap_boundary_axaddr_r_reg[11]\;
\wrap_second_len_r_reg[3]\(3 downto 0) <= \^wrap_second_len_r_reg[3]\(3 downto 0);
ar_cmd_fsm_0: entity work.zybo_zynq_design_auto_pc_0_axi_protocol_converter_v2_1_17_b2s_rd_cmd_fsm
port map (
D(0) => ar_cmd_fsm_0_n_6,
E(0) => ar_cmd_fsm_0_n_8,
Q(1 downto 0) => \^state_reg[0]_rep\(1 downto 0),
aclk => aclk,
areset_d1 => areset_d1,
\axaddr_incr_reg[0]\(0) => ar_cmd_fsm_0_n_16,
axaddr_offset(0) => axaddr_offset(0),
\axaddr_offset_r_reg[2]\(0) => \^axaddr_offset_r_reg[2]\(0),
\axaddr_offset_r_reg[3]\ => \axaddr_offset_r_reg[3]_0\,
\axaddr_offset_r_reg[3]_0\(1) => \^axaddr_offset_r_reg[3]\(2),
\axaddr_offset_r_reg[3]_0\(0) => \wrap_cmd_0/axaddr_offset_r\(2),
\axlen_cnt_reg[7]\ => ar_cmd_fsm_0_n_0,
\axlen_cnt_reg[7]_0\ => cmd_translator_0_n_3,
\cnt_read_reg[2]_rep__0\ => \cnt_read_reg[2]_rep__0\,
m_axi_arready => m_axi_arready,
m_axi_arvalid => m_axi_arvalid,
\m_payload_i_reg[0]\ => \m_payload_i_reg[0]\,
\m_payload_i_reg[0]_0\ => \^m_payload_i_reg[0]_0\,
\m_payload_i_reg[0]_1\(0) => E(0),
\m_payload_i_reg[46]\(0) => Q(18),
\m_payload_i_reg[5]\ => \m_payload_i_reg[5]\,
m_valid_i0 => m_valid_i0,
r_push_r_reg => \^r_push_r_reg\,
s_axburst_eq1_reg => cmd_translator_0_n_10,
s_axi_arvalid => s_axi_arvalid,
s_ready_i0 => s_ready_i0,
s_ready_i_reg => s_ready_i_reg,
sel_first => \incr_cmd_0/sel_first\,
sel_first_i => sel_first_i,
sel_first_reg => ar_cmd_fsm_0_n_9,
sel_first_reg_0 => ar_cmd_fsm_0_n_10,
sel_first_reg_1 => cmd_translator_0_n_2,
sel_first_reg_2 => cmd_translator_0_n_0,
si_rs_arvalid => si_rs_arvalid,
\wrap_boundary_axaddr_r_reg[11]\(0) => \^wrap_boundary_axaddr_r_reg[11]\,
\wrap_cnt_r_reg[3]\ => \wrap_cnt_r_reg[3]_0\,
\wrap_cnt_r_reg[3]_0\ => \wrap_cnt_r_reg[3]_1\,
\wrap_second_len_r_reg[0]\(0) => \wrap_cmd_0/wrap_second_len\(0),
\wrap_second_len_r_reg[0]_0\(0) => \^wrap_second_len_r_reg[3]\(0)
);
cmd_translator_0: entity work.zybo_zynq_design_auto_pc_0_axi_protocol_converter_v2_1_17_b2s_cmd_translator_1
port map (
D(3) => axaddr_offset(2),
D(2) => \^axaddr_offset_r_reg[2]\(0),
D(1 downto 0) => axaddr_offset(1 downto 0),
E(0) => \^wrap_boundary_axaddr_r_reg[11]\,
O(3 downto 0) => O(3 downto 0),
Q(19 downto 0) => Q(19 downto 0),
S(3 downto 0) => S(3 downto 0),
aclk => aclk,
\axaddr_offset_r_reg[3]\(3) => \^axaddr_offset_r_reg[3]\(2),
\axaddr_offset_r_reg[3]\(2) => \wrap_cmd_0/axaddr_offset_r\(2),
\axaddr_offset_r_reg[3]\(1 downto 0) => \^axaddr_offset_r_reg[3]\(1 downto 0),
\axaddr_offset_r_reg[3]_0\ => \axaddr_offset_r_reg[3]_1\,
\axaddr_offset_r_reg[3]_1\ => \axaddr_offset_r_reg[3]_0\,
\axlen_cnt_reg[0]\ => cmd_translator_0_n_3,
m_axi_araddr(11 downto 0) => m_axi_araddr(11 downto 0),
m_axi_arready => m_axi_arready,
\m_payload_i_reg[3]\(3 downto 0) => \m_payload_i_reg[3]\(3 downto 0),
\m_payload_i_reg[47]\ => \m_payload_i_reg[47]\,
\m_payload_i_reg[47]_0\ => \m_payload_i_reg[47]_0\,
\m_payload_i_reg[6]\(6 downto 0) => \m_payload_i_reg[6]\(6 downto 0),
\m_payload_i_reg[7]\(3 downto 0) => \m_payload_i_reg[7]\(3 downto 0),
m_valid_i_reg(0) => ar_cmd_fsm_0_n_8,
r_rlast => r_rlast,
sel_first => \incr_cmd_0/sel_first\,
sel_first_i => sel_first_i,
sel_first_reg_0 => cmd_translator_0_n_0,
sel_first_reg_1 => cmd_translator_0_n_2,
sel_first_reg_2 => ar_cmd_fsm_0_n_10,
sel_first_reg_3 => ar_cmd_fsm_0_n_9,
sel_first_reg_4(0) => ar_cmd_fsm_0_n_16,
si_rs_arvalid => si_rs_arvalid,
\state_reg[0]_rep\ => cmd_translator_0_n_10,
\state_reg[0]_rep_0\ => \^m_payload_i_reg[0]_0\,
\state_reg[1]\(1 downto 0) => \^state_reg[0]_rep\(1 downto 0),
\state_reg[1]_0\ => ar_cmd_fsm_0_n_0,
\state_reg[1]_rep\ => \^r_push_r_reg\,
\wrap_cnt_r_reg[3]\ => \wrap_cnt_r_reg[3]\,
\wrap_second_len_r_reg[3]\(3 downto 0) => \^wrap_second_len_r_reg[3]\(3 downto 0),
\wrap_second_len_r_reg[3]_0\(3 downto 1) => D(2 downto 0),
\wrap_second_len_r_reg[3]_0\(0) => \wrap_cmd_0/wrap_second_len\(0),
\wrap_second_len_r_reg[3]_1\(2 downto 1) => \wrap_second_len_r_reg[3]_0\(1 downto 0),
\wrap_second_len_r_reg[3]_1\(0) => ar_cmd_fsm_0_n_6
);
\s_arid_r_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => Q(20),
Q => \r_arid_r_reg[11]\(0),
R => '0'
);
\s_arid_r_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => Q(30),
Q => \r_arid_r_reg[11]\(10),
R => '0'
);
\s_arid_r_reg[11]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => Q(31),
Q => \r_arid_r_reg[11]\(11),
R => '0'
);
\s_arid_r_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => Q(21),
Q => \r_arid_r_reg[11]\(1),
R => '0'
);
\s_arid_r_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => Q(22),
Q => \r_arid_r_reg[11]\(2),
R => '0'
);
\s_arid_r_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => Q(23),
Q => \r_arid_r_reg[11]\(3),
R => '0'
);
\s_arid_r_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => Q(24),
Q => \r_arid_r_reg[11]\(4),
R => '0'
);
\s_arid_r_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => Q(25),
Q => \r_arid_r_reg[11]\(5),
R => '0'
);
\s_arid_r_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => Q(26),
Q => \r_arid_r_reg[11]\(6),
R => '0'
);
\s_arid_r_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => Q(27),
Q => \r_arid_r_reg[11]\(7),
R => '0'
);
\s_arid_r_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => Q(28),
Q => \r_arid_r_reg[11]\(8),
R => '0'
);
\s_arid_r_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => Q(29),
Q => \r_arid_r_reg[11]\(9),
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity zybo_zynq_design_auto_pc_0_axi_protocol_converter_v2_1_17_b2s_aw_channel is
port (
\wrap_boundary_axaddr_r_reg[11]\ : out STD_LOGIC;
\state_reg[0]_rep\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
\axlen_cnt_reg[7]\ : out STD_LOGIC;
\axlen_cnt_reg[7]_0\ : out STD_LOGIC;
\wrap_second_len_r_reg[3]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
\wrap_cnt_r_reg[3]\ : out STD_LOGIC;
\wrap_cnt_r_reg[3]_0\ : out STD_LOGIC;
\axaddr_offset_r_reg[3]\ : out STD_LOGIC_VECTOR ( 2 downto 0 );
\axaddr_offset_r_reg[2]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\wrap_cnt_r_reg[3]_1\ : out STD_LOGIC;
E : out STD_LOGIC_VECTOR ( 0 to 0 );
b_push : out STD_LOGIC;
m_axi_awvalid : out STD_LOGIC;
m_axi_awaddr : out STD_LOGIC_VECTOR ( 11 downto 0 );
\in\ : out STD_LOGIC_VECTOR ( 15 downto 0 );
S : out STD_LOGIC_VECTOR ( 3 downto 0 );
aclk : in STD_LOGIC;
Q : in STD_LOGIC_VECTOR ( 31 downto 0 );
si_rs_awvalid : in STD_LOGIC;
\cnt_read_reg[1]_rep__0\ : in STD_LOGIC;
\cnt_read_reg[0]_rep__0\ : in STD_LOGIC;
m_axi_awready : in STD_LOGIC;
D : in STD_LOGIC_VECTOR ( 1 downto 0 );
\axaddr_offset_r_reg[3]_0\ : in STD_LOGIC;
axaddr_offset : in STD_LOGIC_VECTOR ( 2 downto 0 );
\axaddr_offset_r_reg[3]_1\ : in STD_LOGIC;
\wrap_second_len_r_reg[3]_0\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
\m_payload_i_reg[47]\ : in STD_LOGIC;
\m_payload_i_reg[47]_0\ : in STD_LOGIC;
areset_d1 : in STD_LOGIC;
\m_payload_i_reg[5]\ : in STD_LOGIC;
axaddr_incr : in STD_LOGIC_VECTOR ( 11 downto 0 );
\m_payload_i_reg[6]\ : in STD_LOGIC_VECTOR ( 6 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of zybo_zynq_design_auto_pc_0_axi_protocol_converter_v2_1_17_b2s_aw_channel : entity is "axi_protocol_converter_v2_1_17_b2s_aw_channel";
end zybo_zynq_design_auto_pc_0_axi_protocol_converter_v2_1_17_b2s_aw_channel;
architecture STRUCTURE of zybo_zynq_design_auto_pc_0_axi_protocol_converter_v2_1_17_b2s_aw_channel is
signal aw_cmd_fsm_0_n_12 : STD_LOGIC;
signal aw_cmd_fsm_0_n_14 : STD_LOGIC;
signal aw_cmd_fsm_0_n_15 : STD_LOGIC;
signal aw_cmd_fsm_0_n_16 : STD_LOGIC;
signal aw_cmd_fsm_0_n_2 : STD_LOGIC;
signal aw_cmd_fsm_0_n_8 : STD_LOGIC;
signal aw_cmd_fsm_0_n_9 : STD_LOGIC;
signal \^axaddr_offset_r_reg[2]\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \^axaddr_offset_r_reg[3]\ : STD_LOGIC_VECTOR ( 2 downto 0 );
signal cmd_translator_0_n_0 : STD_LOGIC;
signal cmd_translator_0_n_12 : STD_LOGIC;
signal cmd_translator_0_n_2 : STD_LOGIC;
signal cmd_translator_0_n_5 : STD_LOGIC;
signal cmd_translator_0_n_6 : STD_LOGIC;
signal \incr_cmd_0/sel_first\ : STD_LOGIC;
signal incr_next_pending : STD_LOGIC;
signal \next\ : STD_LOGIC;
signal sel_first : STD_LOGIC;
signal sel_first_i : STD_LOGIC;
signal \^state_reg[0]_rep\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \^wrap_boundary_axaddr_r_reg[11]\ : STD_LOGIC;
signal \wrap_cmd_0/axaddr_offset_r\ : STD_LOGIC_VECTOR ( 2 to 2 );
signal \wrap_cmd_0/wrap_second_len\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal wrap_cnt : STD_LOGIC_VECTOR ( 0 to 0 );
signal wrap_next_pending : STD_LOGIC;
signal \^wrap_second_len_r_reg[3]\ : STD_LOGIC_VECTOR ( 3 downto 0 );
begin
\axaddr_offset_r_reg[2]\(0) <= \^axaddr_offset_r_reg[2]\(0);
\axaddr_offset_r_reg[3]\(2 downto 0) <= \^axaddr_offset_r_reg[3]\(2 downto 0);
\state_reg[0]_rep\(1 downto 0) <= \^state_reg[0]_rep\(1 downto 0);
\wrap_boundary_axaddr_r_reg[11]\ <= \^wrap_boundary_axaddr_r_reg[11]\;
\wrap_second_len_r_reg[3]\(3 downto 0) <= \^wrap_second_len_r_reg[3]\(3 downto 0);
aw_cmd_fsm_0: entity work.zybo_zynq_design_auto_pc_0_axi_protocol_converter_v2_1_17_b2s_wr_cmd_fsm
port map (
D(0) => wrap_cnt(0),
E(0) => \^wrap_boundary_axaddr_r_reg[11]\,
Q(1 downto 0) => \^state_reg[0]_rep\(1 downto 0),
aclk => aclk,
areset_d1 => areset_d1,
axaddr_offset(0) => axaddr_offset(0),
\axaddr_offset_r_reg[2]\(0) => \^axaddr_offset_r_reg[2]\(0),
\axaddr_offset_r_reg[3]\ => \axaddr_offset_r_reg[3]_0\,
\axaddr_offset_r_reg[3]_0\(1) => \^axaddr_offset_r_reg[3]\(2),
\axaddr_offset_r_reg[3]_0\(0) => \wrap_cmd_0/axaddr_offset_r\(2),
\axaddr_wrap_reg[11]\(0) => aw_cmd_fsm_0_n_14,
\axlen_cnt_reg[0]\(0) => aw_cmd_fsm_0_n_8,
\axlen_cnt_reg[0]_0\(0) => cmd_translator_0_n_5,
\axlen_cnt_reg[7]\ => \axlen_cnt_reg[7]\,
\axlen_cnt_reg[7]_0\ => \axlen_cnt_reg[7]_0\,
\axlen_cnt_reg[7]_1\ => aw_cmd_fsm_0_n_2,
\axlen_cnt_reg[7]_2\ => cmd_translator_0_n_6,
b_push => b_push,
\cnt_read_reg[0]_rep__0\ => \cnt_read_reg[0]_rep__0\,
\cnt_read_reg[1]_rep__0\ => \cnt_read_reg[1]_rep__0\,
incr_next_pending => incr_next_pending,
m_axi_awready => m_axi_awready,
m_axi_awvalid => m_axi_awvalid,
\m_payload_i_reg[0]\(0) => E(0),
\m_payload_i_reg[46]\(2) => Q(18),
\m_payload_i_reg[46]\(1 downto 0) => Q(16 downto 15),
\m_payload_i_reg[47]\ => \m_payload_i_reg[47]_0\,
\m_payload_i_reg[5]\ => \m_payload_i_reg[5]\,
\next\ => \next\,
next_pending_r_reg => cmd_translator_0_n_0,
s_axburst_eq0_reg => aw_cmd_fsm_0_n_9,
s_axburst_eq1_reg => aw_cmd_fsm_0_n_12,
s_axburst_eq1_reg_0 => cmd_translator_0_n_12,
sel_first => sel_first,
sel_first_0 => \incr_cmd_0/sel_first\,
sel_first_i => sel_first_i,
sel_first_reg => aw_cmd_fsm_0_n_15,
sel_first_reg_0 => aw_cmd_fsm_0_n_16,
sel_first_reg_1 => cmd_translator_0_n_2,
si_rs_awvalid => si_rs_awvalid,
\wrap_cnt_r_reg[3]\ => \wrap_cnt_r_reg[3]_0\,
\wrap_cnt_r_reg[3]_0\ => \wrap_cnt_r_reg[3]_1\,
wrap_next_pending => wrap_next_pending,
\wrap_second_len_r_reg[0]\(0) => \wrap_cmd_0/wrap_second_len\(0),
\wrap_second_len_r_reg[0]_0\(0) => \^wrap_second_len_r_reg[3]\(0)
);
cmd_translator_0: entity work.zybo_zynq_design_auto_pc_0_axi_protocol_converter_v2_1_17_b2s_cmd_translator
port map (
D(3) => axaddr_offset(2),
D(2) => \^axaddr_offset_r_reg[2]\(0),
D(1 downto 0) => axaddr_offset(1 downto 0),
E(0) => \^wrap_boundary_axaddr_r_reg[11]\,
Q(0) => cmd_translator_0_n_5,
S(3 downto 0) => S(3 downto 0),
aclk => aclk,
axaddr_incr(11 downto 0) => axaddr_incr(11 downto 0),
\axaddr_offset_r_reg[3]\(3) => \^axaddr_offset_r_reg[3]\(2),
\axaddr_offset_r_reg[3]\(2) => \wrap_cmd_0/axaddr_offset_r\(2),
\axaddr_offset_r_reg[3]\(1 downto 0) => \^axaddr_offset_r_reg[3]\(1 downto 0),
\axaddr_offset_r_reg[3]_0\ => \axaddr_offset_r_reg[3]_1\,
\axaddr_offset_r_reg[3]_1\ => \axaddr_offset_r_reg[3]_0\,
\axlen_cnt_reg[2]\ => cmd_translator_0_n_6,
incr_next_pending => incr_next_pending,
m_axi_awaddr(11 downto 0) => m_axi_awaddr(11 downto 0),
\m_payload_i_reg[39]\ => aw_cmd_fsm_0_n_9,
\m_payload_i_reg[39]_0\ => aw_cmd_fsm_0_n_12,
\m_payload_i_reg[47]\(19 downto 0) => Q(19 downto 0),
\m_payload_i_reg[47]_0\ => \m_payload_i_reg[47]\,
\m_payload_i_reg[47]_1\ => \m_payload_i_reg[47]_0\,
\m_payload_i_reg[6]\(6 downto 0) => \m_payload_i_reg[6]\(6 downto 0),
\next\ => \next\,
next_pending_r_reg => cmd_translator_0_n_0,
sel_first => sel_first,
sel_first_0 => \incr_cmd_0/sel_first\,
sel_first_i => sel_first_i,
sel_first_reg_0 => cmd_translator_0_n_2,
sel_first_reg_1 => aw_cmd_fsm_0_n_16,
sel_first_reg_2 => aw_cmd_fsm_0_n_15,
si_rs_awvalid => si_rs_awvalid,
\state_reg[0]\(0) => aw_cmd_fsm_0_n_14,
\state_reg[0]_rep\ => aw_cmd_fsm_0_n_2,
\state_reg[1]\(1 downto 0) => \^state_reg[0]_rep\(1 downto 0),
\state_reg[1]_0\(0) => aw_cmd_fsm_0_n_8,
\state_reg[1]_rep\ => cmd_translator_0_n_12,
\wrap_cnt_r_reg[3]\ => \wrap_cnt_r_reg[3]\,
wrap_next_pending => wrap_next_pending,
\wrap_second_len_r_reg[3]\(3 downto 0) => \^wrap_second_len_r_reg[3]\(3 downto 0),
\wrap_second_len_r_reg[3]_0\(2 downto 1) => D(1 downto 0),
\wrap_second_len_r_reg[3]_0\(0) => wrap_cnt(0),
\wrap_second_len_r_reg[3]_1\(3 downto 1) => \wrap_second_len_r_reg[3]_0\(2 downto 0),
\wrap_second_len_r_reg[3]_1\(0) => \wrap_cmd_0/wrap_second_len\(0)
);
\s_awid_r_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => Q(20),
Q => \in\(4),
R => '0'
);
\s_awid_r_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => Q(30),
Q => \in\(14),
R => '0'
);
\s_awid_r_reg[11]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => Q(31),
Q => \in\(15),
R => '0'
);
\s_awid_r_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => Q(21),
Q => \in\(5),
R => '0'
);
\s_awid_r_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => Q(22),
Q => \in\(6),
R => '0'
);
\s_awid_r_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => Q(23),
Q => \in\(7),
R => '0'
);
\s_awid_r_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => Q(24),
Q => \in\(8),
R => '0'
);
\s_awid_r_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => Q(25),
Q => \in\(9),
R => '0'
);
\s_awid_r_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => Q(26),
Q => \in\(10),
R => '0'
);
\s_awid_r_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => Q(27),
Q => \in\(11),
R => '0'
);
\s_awid_r_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => Q(28),
Q => \in\(12),
R => '0'
);
\s_awid_r_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => Q(29),
Q => \in\(13),
R => '0'
);
\s_awlen_r_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => Q(16),
Q => \in\(0),
R => '0'
);
\s_awlen_r_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => Q(17),
Q => \in\(1),
R => '0'
);
\s_awlen_r_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => Q(18),
Q => \in\(2),
R => '0'
);
\s_awlen_r_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => Q(19),
Q => \in\(3),
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity zybo_zynq_design_auto_pc_0_axi_protocol_converter_v2_1_17_b2s is
port (
s_axi_rvalid : out STD_LOGIC;
s_axi_awready : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 22 downto 0 );
s_axi_arready : out STD_LOGIC;
\m_axi_arprot[2]\ : out STD_LOGIC_VECTOR ( 22 downto 0 );
s_axi_bvalid : out STD_LOGIC;
\s_axi_bid[11]\ : out STD_LOGIC_VECTOR ( 13 downto 0 );
\s_axi_rid[11]\ : out STD_LOGIC_VECTOR ( 46 downto 0 );
m_axi_awvalid : out STD_LOGIC;
m_axi_bready : out STD_LOGIC;
m_axi_arvalid : out STD_LOGIC;
m_axi_rready : out STD_LOGIC;
m_axi_awaddr : out STD_LOGIC_VECTOR ( 11 downto 0 );
m_axi_araddr : out STD_LOGIC_VECTOR ( 11 downto 0 );
m_axi_awready : in STD_LOGIC;
m_axi_arready : in STD_LOGIC;
s_axi_rready : in STD_LOGIC;
aclk : in STD_LOGIC;
\in\ : in STD_LOGIC_VECTOR ( 33 downto 0 );
s_axi_awid : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_awlen : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awsize : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arid : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_arlen : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arsize : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_awvalid : in STD_LOGIC;
m_axi_bvalid : in STD_LOGIC;
m_axi_rvalid : in STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_arvalid : in STD_LOGIC;
aresetn : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of zybo_zynq_design_auto_pc_0_axi_protocol_converter_v2_1_17_b2s : entity is "axi_protocol_converter_v2_1_17_b2s";
end zybo_zynq_design_auto_pc_0_axi_protocol_converter_v2_1_17_b2s;
architecture STRUCTURE of zybo_zynq_design_auto_pc_0_axi_protocol_converter_v2_1_17_b2s is
signal \RD.ar_channel_0_n_0\ : STD_LOGIC;
signal \RD.ar_channel_0_n_10\ : STD_LOGIC;
signal \RD.ar_channel_0_n_11\ : STD_LOGIC;
signal \RD.ar_channel_0_n_16\ : STD_LOGIC;
signal \RD.ar_channel_0_n_3\ : STD_LOGIC;
signal \RD.ar_channel_0_n_4\ : STD_LOGIC;
signal \RD.ar_channel_0_n_46\ : STD_LOGIC;
signal \RD.ar_channel_0_n_47\ : STD_LOGIC;
signal \RD.ar_channel_0_n_48\ : STD_LOGIC;
signal \RD.ar_channel_0_n_49\ : STD_LOGIC;
signal \RD.ar_channel_0_n_5\ : STD_LOGIC;
signal \RD.r_channel_0_n_0\ : STD_LOGIC;
signal \RD.r_channel_0_n_1\ : STD_LOGIC;
signal SI_REG_n_132 : STD_LOGIC;
signal SI_REG_n_133 : STD_LOGIC;
signal SI_REG_n_134 : STD_LOGIC;
signal SI_REG_n_135 : STD_LOGIC;
signal SI_REG_n_136 : STD_LOGIC;
signal SI_REG_n_137 : STD_LOGIC;
signal SI_REG_n_138 : STD_LOGIC;
signal SI_REG_n_139 : STD_LOGIC;
signal SI_REG_n_140 : STD_LOGIC;
signal SI_REG_n_141 : STD_LOGIC;
signal SI_REG_n_142 : STD_LOGIC;
signal SI_REG_n_143 : STD_LOGIC;
signal SI_REG_n_149 : STD_LOGIC;
signal SI_REG_n_153 : STD_LOGIC;
signal SI_REG_n_154 : STD_LOGIC;
signal SI_REG_n_155 : STD_LOGIC;
signal SI_REG_n_156 : STD_LOGIC;
signal SI_REG_n_157 : STD_LOGIC;
signal SI_REG_n_161 : STD_LOGIC;
signal SI_REG_n_165 : STD_LOGIC;
signal SI_REG_n_166 : STD_LOGIC;
signal SI_REG_n_167 : STD_LOGIC;
signal SI_REG_n_168 : STD_LOGIC;
signal SI_REG_n_169 : STD_LOGIC;
signal SI_REG_n_170 : STD_LOGIC;
signal SI_REG_n_171 : STD_LOGIC;
signal SI_REG_n_172 : STD_LOGIC;
signal SI_REG_n_173 : STD_LOGIC;
signal SI_REG_n_174 : STD_LOGIC;
signal SI_REG_n_175 : STD_LOGIC;
signal SI_REG_n_176 : STD_LOGIC;
signal SI_REG_n_177 : STD_LOGIC;
signal SI_REG_n_178 : STD_LOGIC;
signal SI_REG_n_179 : STD_LOGIC;
signal SI_REG_n_180 : STD_LOGIC;
signal SI_REG_n_181 : STD_LOGIC;
signal SI_REG_n_182 : STD_LOGIC;
signal SI_REG_n_26 : STD_LOGIC;
signal SI_REG_n_64 : STD_LOGIC;
signal SI_REG_n_8 : STD_LOGIC;
signal SI_REG_n_82 : STD_LOGIC;
signal \WR.aw_channel_0_n_0\ : STD_LOGIC;
signal \WR.aw_channel_0_n_10\ : STD_LOGIC;
signal \WR.aw_channel_0_n_15\ : STD_LOGIC;
signal \WR.aw_channel_0_n_3\ : STD_LOGIC;
signal \WR.aw_channel_0_n_4\ : STD_LOGIC;
signal \WR.aw_channel_0_n_47\ : STD_LOGIC;
signal \WR.aw_channel_0_n_48\ : STD_LOGIC;
signal \WR.aw_channel_0_n_49\ : STD_LOGIC;
signal \WR.aw_channel_0_n_50\ : STD_LOGIC;
signal \WR.aw_channel_0_n_9\ : STD_LOGIC;
signal \WR.b_channel_0_n_1\ : STD_LOGIC;
signal \WR.b_channel_0_n_2\ : STD_LOGIC;
signal \ar.ar_pipe/m_valid_i0\ : STD_LOGIC;
signal \ar.ar_pipe/p_1_in\ : STD_LOGIC;
signal \ar.ar_pipe/s_ready_i0\ : STD_LOGIC;
signal \ar_cmd_fsm_0/state\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal areset_d1 : STD_LOGIC;
signal areset_d1_i_1_n_0 : STD_LOGIC;
signal \aw.aw_pipe/p_1_in\ : STD_LOGIC;
signal \aw_cmd_fsm_0/state\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal axaddr_incr : STD_LOGIC_VECTOR ( 11 downto 0 );
signal b_awid : STD_LOGIC_VECTOR ( 11 downto 0 );
signal b_awlen : STD_LOGIC_VECTOR ( 3 downto 0 );
signal b_push : STD_LOGIC;
signal \cmd_translator_0/wrap_cmd_0/axaddr_offset\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \cmd_translator_0/wrap_cmd_0/axaddr_offset_0\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \cmd_translator_0/wrap_cmd_0/axaddr_offset_r\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \cmd_translator_0/wrap_cmd_0/axaddr_offset_r_2\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \cmd_translator_0/wrap_cmd_0/wrap_second_len\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \cmd_translator_0/wrap_cmd_0/wrap_second_len_1\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \cmd_translator_0/wrap_cmd_0/wrap_second_len_r\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \cmd_translator_0/wrap_cmd_0/wrap_second_len_r_3\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal r_rlast : STD_LOGIC;
signal s_arid : STD_LOGIC_VECTOR ( 11 downto 0 );
signal s_arid_r : STD_LOGIC_VECTOR ( 11 downto 0 );
signal s_awid : STD_LOGIC_VECTOR ( 11 downto 0 );
signal \^s_axi_arready\ : STD_LOGIC;
signal si_rs_araddr : STD_LOGIC_VECTOR ( 11 downto 0 );
signal si_rs_arburst : STD_LOGIC_VECTOR ( 1 to 1 );
signal si_rs_arlen : STD_LOGIC_VECTOR ( 3 downto 0 );
signal si_rs_arsize : STD_LOGIC_VECTOR ( 1 downto 0 );
signal si_rs_arvalid : STD_LOGIC;
signal si_rs_awaddr : STD_LOGIC_VECTOR ( 11 downto 0 );
signal si_rs_awburst : STD_LOGIC_VECTOR ( 1 to 1 );
signal si_rs_awlen : STD_LOGIC_VECTOR ( 3 downto 0 );
signal si_rs_awsize : STD_LOGIC_VECTOR ( 1 downto 0 );
signal si_rs_awvalid : STD_LOGIC;
signal si_rs_bid : STD_LOGIC_VECTOR ( 11 downto 0 );
signal si_rs_bready : STD_LOGIC;
signal si_rs_bresp : STD_LOGIC_VECTOR ( 1 downto 0 );
signal si_rs_bvalid : STD_LOGIC;
signal si_rs_rdata : STD_LOGIC_VECTOR ( 31 downto 0 );
signal si_rs_rid : STD_LOGIC_VECTOR ( 11 downto 0 );
signal si_rs_rlast : STD_LOGIC;
signal si_rs_rready : STD_LOGIC;
signal si_rs_rresp : STD_LOGIC_VECTOR ( 1 downto 0 );
signal wrap_cnt : STD_LOGIC_VECTOR ( 3 downto 2 );
begin
s_axi_arready <= \^s_axi_arready\;
\RD.ar_channel_0\: entity work.zybo_zynq_design_auto_pc_0_axi_protocol_converter_v2_1_17_b2s_ar_channel
port map (
D(2 downto 0) => \cmd_translator_0/wrap_cmd_0/wrap_second_len\(3 downto 1),
E(0) => \ar.ar_pipe/p_1_in\,
O(3) => SI_REG_n_140,
O(2) => SI_REG_n_141,
O(1) => SI_REG_n_142,
O(0) => SI_REG_n_143,
Q(31 downto 20) => s_arid(11 downto 0),
Q(19 downto 16) => si_rs_arlen(3 downto 0),
Q(15) => si_rs_arburst(1),
Q(14) => SI_REG_n_82,
Q(13 downto 12) => si_rs_arsize(1 downto 0),
Q(11 downto 0) => si_rs_araddr(11 downto 0),
S(3) => \RD.ar_channel_0_n_46\,
S(2) => \RD.ar_channel_0_n_47\,
S(1) => \RD.ar_channel_0_n_48\,
S(0) => \RD.ar_channel_0_n_49\,
aclk => aclk,
areset_d1 => areset_d1,
axaddr_offset(2) => \cmd_translator_0/wrap_cmd_0/axaddr_offset\(3),
axaddr_offset(1 downto 0) => \cmd_translator_0/wrap_cmd_0/axaddr_offset\(1 downto 0),
\axaddr_offset_r_reg[2]\(0) => \cmd_translator_0/wrap_cmd_0/axaddr_offset\(2),
\axaddr_offset_r_reg[3]\(2) => \cmd_translator_0/wrap_cmd_0/axaddr_offset_r\(3),
\axaddr_offset_r_reg[3]\(1 downto 0) => \cmd_translator_0/wrap_cmd_0/axaddr_offset_r\(1 downto 0),
\axaddr_offset_r_reg[3]_0\ => SI_REG_n_161,
\axaddr_offset_r_reg[3]_1\ => SI_REG_n_165,
\cnt_read_reg[2]_rep__0\ => \RD.r_channel_0_n_1\,
m_axi_araddr(11 downto 0) => m_axi_araddr(11 downto 0),
m_axi_arready => m_axi_arready,
m_axi_arvalid => m_axi_arvalid,
\m_payload_i_reg[0]\ => \RD.ar_channel_0_n_4\,
\m_payload_i_reg[0]_0\ => \RD.ar_channel_0_n_5\,
\m_payload_i_reg[3]\(3) => SI_REG_n_132,
\m_payload_i_reg[3]\(2) => SI_REG_n_133,
\m_payload_i_reg[3]\(1) => SI_REG_n_134,
\m_payload_i_reg[3]\(0) => SI_REG_n_135,
\m_payload_i_reg[47]\ => SI_REG_n_64,
\m_payload_i_reg[47]_0\ => SI_REG_n_167,
\m_payload_i_reg[5]\ => SI_REG_n_166,
\m_payload_i_reg[6]\(6) => SI_REG_n_176,
\m_payload_i_reg[6]\(5) => SI_REG_n_177,
\m_payload_i_reg[6]\(4) => SI_REG_n_178,
\m_payload_i_reg[6]\(3) => SI_REG_n_179,
\m_payload_i_reg[6]\(2) => SI_REG_n_180,
\m_payload_i_reg[6]\(1) => SI_REG_n_181,
\m_payload_i_reg[6]\(0) => SI_REG_n_182,
\m_payload_i_reg[7]\(3) => SI_REG_n_136,
\m_payload_i_reg[7]\(2) => SI_REG_n_137,
\m_payload_i_reg[7]\(1) => SI_REG_n_138,
\m_payload_i_reg[7]\(0) => SI_REG_n_139,
m_valid_i0 => \ar.ar_pipe/m_valid_i0\,
\r_arid_r_reg[11]\(11 downto 0) => s_arid_r(11 downto 0),
r_push_r_reg => \RD.ar_channel_0_n_3\,
r_rlast => r_rlast,
s_axi_arvalid => s_axi_arvalid,
s_ready_i0 => \ar.ar_pipe/s_ready_i0\,
s_ready_i_reg => \^s_axi_arready\,
si_rs_arvalid => si_rs_arvalid,
\state_reg[0]_rep\(1 downto 0) => \ar_cmd_fsm_0/state\(1 downto 0),
\wrap_boundary_axaddr_r_reg[11]\ => \RD.ar_channel_0_n_0\,
\wrap_cnt_r_reg[3]\ => \RD.ar_channel_0_n_10\,
\wrap_cnt_r_reg[3]_0\ => \RD.ar_channel_0_n_11\,
\wrap_cnt_r_reg[3]_1\ => \RD.ar_channel_0_n_16\,
\wrap_second_len_r_reg[3]\(3 downto 0) => \cmd_translator_0/wrap_cmd_0/wrap_second_len_r\(3 downto 0),
\wrap_second_len_r_reg[3]_0\(1) => SI_REG_n_156,
\wrap_second_len_r_reg[3]_0\(0) => SI_REG_n_157
);
\RD.r_channel_0\: entity work.zybo_zynq_design_auto_pc_0_axi_protocol_converter_v2_1_17_b2s_r_channel
port map (
D(11 downto 0) => s_arid_r(11 downto 0),
aclk => aclk,
areset_d1 => areset_d1,
\in\(33 downto 0) => \in\(33 downto 0),
m_axi_rready => m_axi_rready,
m_axi_rvalid => m_axi_rvalid,
m_valid_i_reg => \RD.r_channel_0_n_0\,
\out\(33 downto 32) => si_rs_rresp(1 downto 0),
\out\(31 downto 0) => si_rs_rdata(31 downto 0),
r_rlast => r_rlast,
s_ready_i_reg => SI_REG_n_168,
si_rs_rready => si_rs_rready,
\skid_buffer_reg[46]\(12 downto 1) => si_rs_rid(11 downto 0),
\skid_buffer_reg[46]\(0) => si_rs_rlast,
\state_reg[1]_rep\ => \RD.r_channel_0_n_1\,
\state_reg[1]_rep_0\ => \RD.ar_channel_0_n_3\
);
SI_REG: entity work.zybo_zynq_design_auto_pc_0_axi_register_slice_v2_1_17_axi_register_slice
port map (
D(1 downto 0) => wrap_cnt(3 downto 2),
E(0) => \aw.aw_pipe/p_1_in\,
O(3) => SI_REG_n_140,
O(2) => SI_REG_n_141,
O(1) => SI_REG_n_142,
O(0) => SI_REG_n_143,
Q(54 downto 43) => s_awid(11 downto 0),
Q(42 downto 39) => si_rs_awlen(3 downto 0),
Q(38) => si_rs_awburst(1),
Q(37) => SI_REG_n_26,
Q(36 downto 35) => si_rs_awsize(1 downto 0),
Q(34 downto 12) => Q(22 downto 0),
Q(11 downto 0) => si_rs_awaddr(11 downto 0),
S(3) => \WR.aw_channel_0_n_47\,
S(2) => \WR.aw_channel_0_n_48\,
S(1) => \WR.aw_channel_0_n_49\,
S(0) => \WR.aw_channel_0_n_50\,
aclk => aclk,
aresetn => aresetn,
axaddr_incr(11 downto 0) => axaddr_incr(11 downto 0),
\axaddr_incr_reg[3]\(3) => SI_REG_n_132,
\axaddr_incr_reg[3]\(2) => SI_REG_n_133,
\axaddr_incr_reg[3]\(1) => SI_REG_n_134,
\axaddr_incr_reg[3]\(0) => SI_REG_n_135,
\axaddr_incr_reg[7]\(3) => SI_REG_n_136,
\axaddr_incr_reg[7]\(2) => SI_REG_n_137,
\axaddr_incr_reg[7]\(1) => SI_REG_n_138,
\axaddr_incr_reg[7]\(0) => SI_REG_n_139,
axaddr_offset(2) => \cmd_translator_0/wrap_cmd_0/axaddr_offset_0\(3),
axaddr_offset(1 downto 0) => \cmd_translator_0/wrap_cmd_0/axaddr_offset_0\(1 downto 0),
axaddr_offset_0(2) => \cmd_translator_0/wrap_cmd_0/axaddr_offset\(3),
axaddr_offset_0(1 downto 0) => \cmd_translator_0/wrap_cmd_0/axaddr_offset\(1 downto 0),
\axaddr_offset_r_reg[2]\ => SI_REG_n_154,
\axaddr_offset_r_reg[2]_0\ => SI_REG_n_166,
\axaddr_offset_r_reg[2]_1\(0) => \cmd_translator_0/wrap_cmd_0/axaddr_offset_0\(2),
\axaddr_offset_r_reg[2]_2\ => \WR.aw_channel_0_n_15\,
\axaddr_offset_r_reg[2]_3\(0) => \cmd_translator_0/wrap_cmd_0/axaddr_offset\(2),
\axaddr_offset_r_reg[2]_4\ => \RD.ar_channel_0_n_16\,
\axaddr_offset_r_reg[3]\(2) => \cmd_translator_0/wrap_cmd_0/axaddr_offset_r_2\(3),
\axaddr_offset_r_reg[3]\(1 downto 0) => \cmd_translator_0/wrap_cmd_0/axaddr_offset_r_2\(1 downto 0),
\axaddr_offset_r_reg[3]_0\ => \WR.aw_channel_0_n_10\,
\axaddr_offset_r_reg[3]_1\(2) => \cmd_translator_0/wrap_cmd_0/axaddr_offset_r\(3),
\axaddr_offset_r_reg[3]_1\(1 downto 0) => \cmd_translator_0/wrap_cmd_0/axaddr_offset_r\(1 downto 0),
\axaddr_offset_r_reg[3]_2\ => \RD.ar_channel_0_n_11\,
\axlen_cnt_reg[3]\ => SI_REG_n_8,
\axlen_cnt_reg[3]_0\ => SI_REG_n_64,
b_push => b_push,
\cnt_read_reg[2]_rep__0\ => SI_REG_n_168,
\cnt_read_reg[4]\(33 downto 32) => si_rs_rresp(1 downto 0),
\cnt_read_reg[4]\(31 downto 0) => si_rs_rdata(31 downto 0),
\cnt_read_reg[4]_rep__0\ => \RD.r_channel_0_n_0\,
\m_payload_i_reg[3]\(3) => \RD.ar_channel_0_n_46\,
\m_payload_i_reg[3]\(2) => \RD.ar_channel_0_n_47\,
\m_payload_i_reg[3]\(1) => \RD.ar_channel_0_n_48\,
\m_payload_i_reg[3]\(0) => \RD.ar_channel_0_n_49\,
m_valid_i0 => \ar.ar_pipe/m_valid_i0\,
m_valid_i_reg(0) => \ar.ar_pipe/p_1_in\,
next_pending_r_reg => SI_REG_n_155,
next_pending_r_reg_0 => SI_REG_n_167,
\out\(11 downto 0) => si_rs_bid(11 downto 0),
r_push_r_reg(12 downto 1) => si_rs_rid(11 downto 0),
r_push_r_reg(0) => si_rs_rlast,
\s_arid_r_reg[11]\(54 downto 43) => s_arid(11 downto 0),
\s_arid_r_reg[11]\(42 downto 39) => si_rs_arlen(3 downto 0),
\s_arid_r_reg[11]\(38) => si_rs_arburst(1),
\s_arid_r_reg[11]\(37) => SI_REG_n_82,
\s_arid_r_reg[11]\(36 downto 35) => si_rs_arsize(1 downto 0),
\s_arid_r_reg[11]\(34 downto 12) => \m_axi_arprot[2]\(22 downto 0),
\s_arid_r_reg[11]\(11 downto 0) => si_rs_araddr(11 downto 0),
s_axi_araddr(31 downto 0) => s_axi_araddr(31 downto 0),
s_axi_arburst(1 downto 0) => s_axi_arburst(1 downto 0),
s_axi_arid(11 downto 0) => s_axi_arid(11 downto 0),
s_axi_arlen(3 downto 0) => s_axi_arlen(3 downto 0),
s_axi_arprot(2 downto 0) => s_axi_arprot(2 downto 0),
s_axi_arready => \^s_axi_arready\,
s_axi_arsize(1 downto 0) => s_axi_arsize(1 downto 0),
s_axi_awaddr(31 downto 0) => s_axi_awaddr(31 downto 0),
s_axi_awburst(1 downto 0) => s_axi_awburst(1 downto 0),
s_axi_awid(11 downto 0) => s_axi_awid(11 downto 0),
s_axi_awlen(3 downto 0) => s_axi_awlen(3 downto 0),
s_axi_awprot(2 downto 0) => s_axi_awprot(2 downto 0),
s_axi_awready => s_axi_awready,
s_axi_awsize(1 downto 0) => s_axi_awsize(1 downto 0),
s_axi_awvalid => s_axi_awvalid,
\s_axi_bid[11]\(13 downto 0) => \s_axi_bid[11]\(13 downto 0),
s_axi_bready => s_axi_bready,
s_axi_bvalid => s_axi_bvalid,
\s_axi_rid[11]\(46 downto 0) => \s_axi_rid[11]\(46 downto 0),
s_axi_rready => s_axi_rready,
s_axi_rvalid => s_axi_rvalid,
\s_bresp_acc_reg[1]\(1 downto 0) => si_rs_bresp(1 downto 0),
s_ready_i0 => \ar.ar_pipe/s_ready_i0\,
si_rs_arvalid => si_rs_arvalid,
si_rs_awvalid => si_rs_awvalid,
si_rs_bready => si_rs_bready,
si_rs_bvalid => si_rs_bvalid,
si_rs_rready => si_rs_rready,
\state_reg[0]_rep\ => \WR.aw_channel_0_n_4\,
\state_reg[0]_rep_0\ => \RD.ar_channel_0_n_5\,
\state_reg[1]\(1 downto 0) => \aw_cmd_fsm_0/state\(1 downto 0),
\state_reg[1]_0\(1 downto 0) => \ar_cmd_fsm_0/state\(1 downto 0),
\state_reg[1]_rep\ => \WR.aw_channel_0_n_0\,
\state_reg[1]_rep_0\ => \WR.aw_channel_0_n_3\,
\state_reg[1]_rep_1\ => \RD.ar_channel_0_n_0\,
\state_reg[1]_rep_2\ => \RD.ar_channel_0_n_4\,
\wrap_boundary_axaddr_r_reg[6]\(6) => SI_REG_n_169,
\wrap_boundary_axaddr_r_reg[6]\(5) => SI_REG_n_170,
\wrap_boundary_axaddr_r_reg[6]\(4) => SI_REG_n_171,
\wrap_boundary_axaddr_r_reg[6]\(3) => SI_REG_n_172,
\wrap_boundary_axaddr_r_reg[6]\(2) => SI_REG_n_173,
\wrap_boundary_axaddr_r_reg[6]\(1) => SI_REG_n_174,
\wrap_boundary_axaddr_r_reg[6]\(0) => SI_REG_n_175,
\wrap_boundary_axaddr_r_reg[6]_0\(6) => SI_REG_n_176,
\wrap_boundary_axaddr_r_reg[6]_0\(5) => SI_REG_n_177,
\wrap_boundary_axaddr_r_reg[6]_0\(4) => SI_REG_n_178,
\wrap_boundary_axaddr_r_reg[6]_0\(3) => SI_REG_n_179,
\wrap_boundary_axaddr_r_reg[6]_0\(2) => SI_REG_n_180,
\wrap_boundary_axaddr_r_reg[6]_0\(1) => SI_REG_n_181,
\wrap_boundary_axaddr_r_reg[6]_0\(0) => SI_REG_n_182,
\wrap_cnt_r_reg[2]\ => SI_REG_n_149,
\wrap_cnt_r_reg[2]_0\ => SI_REG_n_161,
\wrap_cnt_r_reg[3]\ => SI_REG_n_153,
\wrap_cnt_r_reg[3]_0\(1) => SI_REG_n_156,
\wrap_cnt_r_reg[3]_0\(0) => SI_REG_n_157,
\wrap_cnt_r_reg[3]_1\ => SI_REG_n_165,
\wrap_second_len_r_reg[1]\ => \WR.aw_channel_0_n_9\,
\wrap_second_len_r_reg[1]_0\ => \RD.ar_channel_0_n_10\,
\wrap_second_len_r_reg[3]\(2 downto 0) => \cmd_translator_0/wrap_cmd_0/wrap_second_len_1\(3 downto 1),
\wrap_second_len_r_reg[3]_0\(2 downto 0) => \cmd_translator_0/wrap_cmd_0/wrap_second_len\(3 downto 1),
\wrap_second_len_r_reg[3]_1\(3 downto 0) => \cmd_translator_0/wrap_cmd_0/wrap_second_len_r_3\(3 downto 0),
\wrap_second_len_r_reg[3]_2\(3 downto 0) => \cmd_translator_0/wrap_cmd_0/wrap_second_len_r\(3 downto 0)
);
\WR.aw_channel_0\: entity work.zybo_zynq_design_auto_pc_0_axi_protocol_converter_v2_1_17_b2s_aw_channel
port map (
D(1 downto 0) => wrap_cnt(3 downto 2),
E(0) => \aw.aw_pipe/p_1_in\,
Q(31 downto 20) => s_awid(11 downto 0),
Q(19 downto 16) => si_rs_awlen(3 downto 0),
Q(15) => si_rs_awburst(1),
Q(14) => SI_REG_n_26,
Q(13 downto 12) => si_rs_awsize(1 downto 0),
Q(11 downto 0) => si_rs_awaddr(11 downto 0),
S(3) => \WR.aw_channel_0_n_47\,
S(2) => \WR.aw_channel_0_n_48\,
S(1) => \WR.aw_channel_0_n_49\,
S(0) => \WR.aw_channel_0_n_50\,
aclk => aclk,
areset_d1 => areset_d1,
axaddr_incr(11 downto 0) => axaddr_incr(11 downto 0),
axaddr_offset(2) => \cmd_translator_0/wrap_cmd_0/axaddr_offset_0\(3),
axaddr_offset(1 downto 0) => \cmd_translator_0/wrap_cmd_0/axaddr_offset_0\(1 downto 0),
\axaddr_offset_r_reg[2]\(0) => \cmd_translator_0/wrap_cmd_0/axaddr_offset_0\(2),
\axaddr_offset_r_reg[3]\(2) => \cmd_translator_0/wrap_cmd_0/axaddr_offset_r_2\(3),
\axaddr_offset_r_reg[3]\(1 downto 0) => \cmd_translator_0/wrap_cmd_0/axaddr_offset_r_2\(1 downto 0),
\axaddr_offset_r_reg[3]_0\ => SI_REG_n_149,
\axaddr_offset_r_reg[3]_1\ => SI_REG_n_153,
\axlen_cnt_reg[7]\ => \WR.aw_channel_0_n_3\,
\axlen_cnt_reg[7]_0\ => \WR.aw_channel_0_n_4\,
b_push => b_push,
\cnt_read_reg[0]_rep__0\ => \WR.b_channel_0_n_1\,
\cnt_read_reg[1]_rep__0\ => \WR.b_channel_0_n_2\,
\in\(15 downto 4) => b_awid(11 downto 0),
\in\(3 downto 0) => b_awlen(3 downto 0),
m_axi_awaddr(11 downto 0) => m_axi_awaddr(11 downto 0),
m_axi_awready => m_axi_awready,
m_axi_awvalid => m_axi_awvalid,
\m_payload_i_reg[47]\ => SI_REG_n_8,
\m_payload_i_reg[47]_0\ => SI_REG_n_155,
\m_payload_i_reg[5]\ => SI_REG_n_154,
\m_payload_i_reg[6]\(6) => SI_REG_n_169,
\m_payload_i_reg[6]\(5) => SI_REG_n_170,
\m_payload_i_reg[6]\(4) => SI_REG_n_171,
\m_payload_i_reg[6]\(3) => SI_REG_n_172,
\m_payload_i_reg[6]\(2) => SI_REG_n_173,
\m_payload_i_reg[6]\(1) => SI_REG_n_174,
\m_payload_i_reg[6]\(0) => SI_REG_n_175,
si_rs_awvalid => si_rs_awvalid,
\state_reg[0]_rep\(1 downto 0) => \aw_cmd_fsm_0/state\(1 downto 0),
\wrap_boundary_axaddr_r_reg[11]\ => \WR.aw_channel_0_n_0\,
\wrap_cnt_r_reg[3]\ => \WR.aw_channel_0_n_9\,
\wrap_cnt_r_reg[3]_0\ => \WR.aw_channel_0_n_10\,
\wrap_cnt_r_reg[3]_1\ => \WR.aw_channel_0_n_15\,
\wrap_second_len_r_reg[3]\(3 downto 0) => \cmd_translator_0/wrap_cmd_0/wrap_second_len_r_3\(3 downto 0),
\wrap_second_len_r_reg[3]_0\(2 downto 0) => \cmd_translator_0/wrap_cmd_0/wrap_second_len_1\(3 downto 1)
);
\WR.b_channel_0\: entity work.zybo_zynq_design_auto_pc_0_axi_protocol_converter_v2_1_17_b2s_b_channel
port map (
aclk => aclk,
areset_d1 => areset_d1,
b_push => b_push,
\cnt_read_reg[0]_rep__0\ => \WR.b_channel_0_n_1\,
\cnt_read_reg[1]_rep__0\ => \WR.b_channel_0_n_2\,
\in\(15 downto 4) => b_awid(11 downto 0),
\in\(3 downto 0) => b_awlen(3 downto 0),
m_axi_bready => m_axi_bready,
m_axi_bresp(1 downto 0) => m_axi_bresp(1 downto 0),
m_axi_bvalid => m_axi_bvalid,
\out\(11 downto 0) => si_rs_bid(11 downto 0),
si_rs_bready => si_rs_bready,
si_rs_bvalid => si_rs_bvalid,
\skid_buffer_reg[1]\(1 downto 0) => si_rs_bresp(1 downto 0)
);
areset_d1_i_1: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => aresetn,
O => areset_d1_i_1_n_0
);
areset_d1_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => areset_d1_i_1_n_0,
Q => areset_d1,
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity zybo_zynq_design_auto_pc_0_axi_protocol_converter_v2_1_17_axi_protocol_converter is
port (
aclk : in STD_LOGIC;
aresetn : in STD_LOGIC;
s_axi_awid : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_awlen : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awlock : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awregion : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awuser : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_awready : out STD_LOGIC;
s_axi_wid : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_wlast : in STD_LOGIC;
s_axi_wuser : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_wvalid : in STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_bid : out STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_buser : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_bvalid : out STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_arid : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_arlen : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arlock : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arregion : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_aruser : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_arvalid : in STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_rid : out STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rlast : out STD_LOGIC;
s_axi_ruser : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_rvalid : out STD_LOGIC;
s_axi_rready : in STD_LOGIC;
m_axi_awid : out STD_LOGIC_VECTOR ( 11 downto 0 );
m_axi_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_awlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_awsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_awburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_awlock : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_awcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_awregion : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awuser : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_awvalid : out STD_LOGIC;
m_axi_awready : in STD_LOGIC;
m_axi_wid : out STD_LOGIC_VECTOR ( 11 downto 0 );
m_axi_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_wlast : out STD_LOGIC;
m_axi_wuser : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_wvalid : out STD_LOGIC;
m_axi_wready : in STD_LOGIC;
m_axi_bid : in STD_LOGIC_VECTOR ( 11 downto 0 );
m_axi_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_buser : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_bvalid : in STD_LOGIC;
m_axi_bready : out STD_LOGIC;
m_axi_arid : out STD_LOGIC_VECTOR ( 11 downto 0 );
m_axi_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_arlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_arsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_arburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_arlock : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_arcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_arregion : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_aruser : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_arvalid : out STD_LOGIC;
m_axi_arready : in STD_LOGIC;
m_axi_rid : in STD_LOGIC_VECTOR ( 11 downto 0 );
m_axi_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_rlast : in STD_LOGIC;
m_axi_ruser : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_rvalid : in STD_LOGIC;
m_axi_rready : out STD_LOGIC
);
attribute C_AXI_ADDR_WIDTH : integer;
attribute C_AXI_ADDR_WIDTH of zybo_zynq_design_auto_pc_0_axi_protocol_converter_v2_1_17_axi_protocol_converter : entity is 32;
attribute C_AXI_ARUSER_WIDTH : integer;
attribute C_AXI_ARUSER_WIDTH of zybo_zynq_design_auto_pc_0_axi_protocol_converter_v2_1_17_axi_protocol_converter : entity is 1;
attribute C_AXI_AWUSER_WIDTH : integer;
attribute C_AXI_AWUSER_WIDTH of zybo_zynq_design_auto_pc_0_axi_protocol_converter_v2_1_17_axi_protocol_converter : entity is 1;
attribute C_AXI_BUSER_WIDTH : integer;
attribute C_AXI_BUSER_WIDTH of zybo_zynq_design_auto_pc_0_axi_protocol_converter_v2_1_17_axi_protocol_converter : entity is 1;
attribute C_AXI_DATA_WIDTH : integer;
attribute C_AXI_DATA_WIDTH of zybo_zynq_design_auto_pc_0_axi_protocol_converter_v2_1_17_axi_protocol_converter : entity is 32;
attribute C_AXI_ID_WIDTH : integer;
attribute C_AXI_ID_WIDTH of zybo_zynq_design_auto_pc_0_axi_protocol_converter_v2_1_17_axi_protocol_converter : entity is 12;
attribute C_AXI_RUSER_WIDTH : integer;
attribute C_AXI_RUSER_WIDTH of zybo_zynq_design_auto_pc_0_axi_protocol_converter_v2_1_17_axi_protocol_converter : entity is 1;
attribute C_AXI_SUPPORTS_READ : integer;
attribute C_AXI_SUPPORTS_READ of zybo_zynq_design_auto_pc_0_axi_protocol_converter_v2_1_17_axi_protocol_converter : entity is 1;
attribute C_AXI_SUPPORTS_USER_SIGNALS : integer;
attribute C_AXI_SUPPORTS_USER_SIGNALS of zybo_zynq_design_auto_pc_0_axi_protocol_converter_v2_1_17_axi_protocol_converter : entity is 0;
attribute C_AXI_SUPPORTS_WRITE : integer;
attribute C_AXI_SUPPORTS_WRITE of zybo_zynq_design_auto_pc_0_axi_protocol_converter_v2_1_17_axi_protocol_converter : entity is 1;
attribute C_AXI_WUSER_WIDTH : integer;
attribute C_AXI_WUSER_WIDTH of zybo_zynq_design_auto_pc_0_axi_protocol_converter_v2_1_17_axi_protocol_converter : entity is 1;
attribute C_FAMILY : string;
attribute C_FAMILY of zybo_zynq_design_auto_pc_0_axi_protocol_converter_v2_1_17_axi_protocol_converter : entity is "zynq";
attribute C_IGNORE_ID : integer;
attribute C_IGNORE_ID of zybo_zynq_design_auto_pc_0_axi_protocol_converter_v2_1_17_axi_protocol_converter : entity is 0;
attribute C_M_AXI_PROTOCOL : integer;
attribute C_M_AXI_PROTOCOL of zybo_zynq_design_auto_pc_0_axi_protocol_converter_v2_1_17_axi_protocol_converter : entity is 2;
attribute C_S_AXI_PROTOCOL : integer;
attribute C_S_AXI_PROTOCOL of zybo_zynq_design_auto_pc_0_axi_protocol_converter_v2_1_17_axi_protocol_converter : entity is 1;
attribute C_TRANSLATION_MODE : integer;
attribute C_TRANSLATION_MODE of zybo_zynq_design_auto_pc_0_axi_protocol_converter_v2_1_17_axi_protocol_converter : entity is 2;
attribute DowngradeIPIdentifiedWarnings : string;
attribute DowngradeIPIdentifiedWarnings of zybo_zynq_design_auto_pc_0_axi_protocol_converter_v2_1_17_axi_protocol_converter : entity is "yes";
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of zybo_zynq_design_auto_pc_0_axi_protocol_converter_v2_1_17_axi_protocol_converter : entity is "axi_protocol_converter_v2_1_17_axi_protocol_converter";
attribute P_AXI3 : integer;
attribute P_AXI3 of zybo_zynq_design_auto_pc_0_axi_protocol_converter_v2_1_17_axi_protocol_converter : entity is 1;
attribute P_AXI4 : integer;
attribute P_AXI4 of zybo_zynq_design_auto_pc_0_axi_protocol_converter_v2_1_17_axi_protocol_converter : entity is 0;
attribute P_AXILITE : integer;
attribute P_AXILITE of zybo_zynq_design_auto_pc_0_axi_protocol_converter_v2_1_17_axi_protocol_converter : entity is 2;
attribute P_AXILITE_SIZE : string;
attribute P_AXILITE_SIZE of zybo_zynq_design_auto_pc_0_axi_protocol_converter_v2_1_17_axi_protocol_converter : entity is "3'b010";
attribute P_CONVERSION : integer;
attribute P_CONVERSION of zybo_zynq_design_auto_pc_0_axi_protocol_converter_v2_1_17_axi_protocol_converter : entity is 2;
attribute P_DECERR : string;
attribute P_DECERR of zybo_zynq_design_auto_pc_0_axi_protocol_converter_v2_1_17_axi_protocol_converter : entity is "2'b11";
attribute P_INCR : string;
attribute P_INCR of zybo_zynq_design_auto_pc_0_axi_protocol_converter_v2_1_17_axi_protocol_converter : entity is "2'b01";
attribute P_PROTECTION : integer;
attribute P_PROTECTION of zybo_zynq_design_auto_pc_0_axi_protocol_converter_v2_1_17_axi_protocol_converter : entity is 1;
attribute P_SLVERR : string;
attribute P_SLVERR of zybo_zynq_design_auto_pc_0_axi_protocol_converter_v2_1_17_axi_protocol_converter : entity is "2'b10";
end zybo_zynq_design_auto_pc_0_axi_protocol_converter_v2_1_17_axi_protocol_converter;
architecture STRUCTURE of zybo_zynq_design_auto_pc_0_axi_protocol_converter_v2_1_17_axi_protocol_converter is
signal \<const0>\ : STD_LOGIC;
signal \<const1>\ : STD_LOGIC;
signal \^m_axi_wready\ : STD_LOGIC;
signal \^s_axi_wdata\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \^s_axi_wstrb\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \^s_axi_wvalid\ : STD_LOGIC;
begin
\^m_axi_wready\ <= m_axi_wready;
\^s_axi_wdata\(31 downto 0) <= s_axi_wdata(31 downto 0);
\^s_axi_wstrb\(3 downto 0) <= s_axi_wstrb(3 downto 0);
\^s_axi_wvalid\ <= s_axi_wvalid;
m_axi_arburst(1) <= \<const0>\;
m_axi_arburst(0) <= \<const1>\;
m_axi_arcache(3) <= \<const0>\;
m_axi_arcache(2) <= \<const0>\;
m_axi_arcache(1) <= \<const0>\;
m_axi_arcache(0) <= \<const0>\;
m_axi_arid(11) <= \<const0>\;
m_axi_arid(10) <= \<const0>\;
m_axi_arid(9) <= \<const0>\;
m_axi_arid(8) <= \<const0>\;
m_axi_arid(7) <= \<const0>\;
m_axi_arid(6) <= \<const0>\;
m_axi_arid(5) <= \<const0>\;
m_axi_arid(4) <= \<const0>\;
m_axi_arid(3) <= \<const0>\;
m_axi_arid(2) <= \<const0>\;
m_axi_arid(1) <= \<const0>\;
m_axi_arid(0) <= \<const0>\;
m_axi_arlen(7) <= \<const0>\;
m_axi_arlen(6) <= \<const0>\;
m_axi_arlen(5) <= \<const0>\;
m_axi_arlen(4) <= \<const0>\;
m_axi_arlen(3) <= \<const0>\;
m_axi_arlen(2) <= \<const0>\;
m_axi_arlen(1) <= \<const0>\;
m_axi_arlen(0) <= \<const0>\;
m_axi_arlock(0) <= \<const0>\;
m_axi_arqos(3) <= \<const0>\;
m_axi_arqos(2) <= \<const0>\;
m_axi_arqos(1) <= \<const0>\;
m_axi_arqos(0) <= \<const0>\;
m_axi_arregion(3) <= \<const0>\;
m_axi_arregion(2) <= \<const0>\;
m_axi_arregion(1) <= \<const0>\;
m_axi_arregion(0) <= \<const0>\;
m_axi_arsize(2) <= \<const0>\;
m_axi_arsize(1) <= \<const1>\;
m_axi_arsize(0) <= \<const0>\;
m_axi_aruser(0) <= \<const0>\;
m_axi_awburst(1) <= \<const0>\;
m_axi_awburst(0) <= \<const1>\;
m_axi_awcache(3) <= \<const0>\;
m_axi_awcache(2) <= \<const0>\;
m_axi_awcache(1) <= \<const0>\;
m_axi_awcache(0) <= \<const0>\;
m_axi_awid(11) <= \<const0>\;
m_axi_awid(10) <= \<const0>\;
m_axi_awid(9) <= \<const0>\;
m_axi_awid(8) <= \<const0>\;
m_axi_awid(7) <= \<const0>\;
m_axi_awid(6) <= \<const0>\;
m_axi_awid(5) <= \<const0>\;
m_axi_awid(4) <= \<const0>\;
m_axi_awid(3) <= \<const0>\;
m_axi_awid(2) <= \<const0>\;
m_axi_awid(1) <= \<const0>\;
m_axi_awid(0) <= \<const0>\;
m_axi_awlen(7) <= \<const0>\;
m_axi_awlen(6) <= \<const0>\;
m_axi_awlen(5) <= \<const0>\;
m_axi_awlen(4) <= \<const0>\;
m_axi_awlen(3) <= \<const0>\;
m_axi_awlen(2) <= \<const0>\;
m_axi_awlen(1) <= \<const0>\;
m_axi_awlen(0) <= \<const0>\;
m_axi_awlock(0) <= \<const0>\;
m_axi_awqos(3) <= \<const0>\;
m_axi_awqos(2) <= \<const0>\;
m_axi_awqos(1) <= \<const0>\;
m_axi_awqos(0) <= \<const0>\;
m_axi_awregion(3) <= \<const0>\;
m_axi_awregion(2) <= \<const0>\;
m_axi_awregion(1) <= \<const0>\;
m_axi_awregion(0) <= \<const0>\;
m_axi_awsize(2) <= \<const0>\;
m_axi_awsize(1) <= \<const1>\;
m_axi_awsize(0) <= \<const0>\;
m_axi_awuser(0) <= \<const0>\;
m_axi_wdata(31 downto 0) <= \^s_axi_wdata\(31 downto 0);
m_axi_wid(11) <= \<const0>\;
m_axi_wid(10) <= \<const0>\;
m_axi_wid(9) <= \<const0>\;
m_axi_wid(8) <= \<const0>\;
m_axi_wid(7) <= \<const0>\;
m_axi_wid(6) <= \<const0>\;
m_axi_wid(5) <= \<const0>\;
m_axi_wid(4) <= \<const0>\;
m_axi_wid(3) <= \<const0>\;
m_axi_wid(2) <= \<const0>\;
m_axi_wid(1) <= \<const0>\;
m_axi_wid(0) <= \<const0>\;
m_axi_wlast <= \<const1>\;
m_axi_wstrb(3 downto 0) <= \^s_axi_wstrb\(3 downto 0);
m_axi_wuser(0) <= \<const0>\;
m_axi_wvalid <= \^s_axi_wvalid\;
s_axi_buser(0) <= \<const0>\;
s_axi_ruser(0) <= \<const0>\;
s_axi_wready <= \^m_axi_wready\;
GND: unisim.vcomponents.GND
port map (
G => \<const0>\
);
VCC: unisim.vcomponents.VCC
port map (
P => \<const1>\
);
\gen_axilite.gen_b2s_conv.axilite_b2s\: entity work.zybo_zynq_design_auto_pc_0_axi_protocol_converter_v2_1_17_b2s
port map (
Q(22 downto 20) => m_axi_awprot(2 downto 0),
Q(19 downto 0) => m_axi_awaddr(31 downto 12),
aclk => aclk,
aresetn => aresetn,
\in\(33 downto 32) => m_axi_rresp(1 downto 0),
\in\(31 downto 0) => m_axi_rdata(31 downto 0),
m_axi_araddr(11 downto 0) => m_axi_araddr(11 downto 0),
\m_axi_arprot[2]\(22 downto 20) => m_axi_arprot(2 downto 0),
\m_axi_arprot[2]\(19 downto 0) => m_axi_araddr(31 downto 12),
m_axi_arready => m_axi_arready,
m_axi_arvalid => m_axi_arvalid,
m_axi_awaddr(11 downto 0) => m_axi_awaddr(11 downto 0),
m_axi_awready => m_axi_awready,
m_axi_awvalid => m_axi_awvalid,
m_axi_bready => m_axi_bready,
m_axi_bresp(1 downto 0) => m_axi_bresp(1 downto 0),
m_axi_bvalid => m_axi_bvalid,
m_axi_rready => m_axi_rready,
m_axi_rvalid => m_axi_rvalid,
s_axi_araddr(31 downto 0) => s_axi_araddr(31 downto 0),
s_axi_arburst(1 downto 0) => s_axi_arburst(1 downto 0),
s_axi_arid(11 downto 0) => s_axi_arid(11 downto 0),
s_axi_arlen(3 downto 0) => s_axi_arlen(3 downto 0),
s_axi_arprot(2 downto 0) => s_axi_arprot(2 downto 0),
s_axi_arready => s_axi_arready,
s_axi_arsize(1 downto 0) => s_axi_arsize(1 downto 0),
s_axi_arvalid => s_axi_arvalid,
s_axi_awaddr(31 downto 0) => s_axi_awaddr(31 downto 0),
s_axi_awburst(1 downto 0) => s_axi_awburst(1 downto 0),
s_axi_awid(11 downto 0) => s_axi_awid(11 downto 0),
s_axi_awlen(3 downto 0) => s_axi_awlen(3 downto 0),
s_axi_awprot(2 downto 0) => s_axi_awprot(2 downto 0),
s_axi_awready => s_axi_awready,
s_axi_awsize(1 downto 0) => s_axi_awsize(1 downto 0),
s_axi_awvalid => s_axi_awvalid,
\s_axi_bid[11]\(13 downto 2) => s_axi_bid(11 downto 0),
\s_axi_bid[11]\(1 downto 0) => s_axi_bresp(1 downto 0),
s_axi_bready => s_axi_bready,
s_axi_bvalid => s_axi_bvalid,
\s_axi_rid[11]\(46 downto 35) => s_axi_rid(11 downto 0),
\s_axi_rid[11]\(34) => s_axi_rlast,
\s_axi_rid[11]\(33 downto 32) => s_axi_rresp(1 downto 0),
\s_axi_rid[11]\(31 downto 0) => s_axi_rdata(31 downto 0),
s_axi_rready => s_axi_rready,
s_axi_rvalid => s_axi_rvalid
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity zybo_zynq_design_auto_pc_0 is
port (
aclk : in STD_LOGIC;
aresetn : in STD_LOGIC;
s_axi_awid : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_awlen : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awlock : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_awready : out STD_LOGIC;
s_axi_wid : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_wlast : in STD_LOGIC;
s_axi_wvalid : in STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_bid : out STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_bvalid : out STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_arid : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_arlen : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arlock : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arvalid : in STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_rid : out STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rlast : out STD_LOGIC;
s_axi_rvalid : out STD_LOGIC;
s_axi_rready : in STD_LOGIC;
m_axi_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_awvalid : out STD_LOGIC;
m_axi_awready : in STD_LOGIC;
m_axi_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_wvalid : out STD_LOGIC;
m_axi_wready : in STD_LOGIC;
m_axi_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_bvalid : in STD_LOGIC;
m_axi_bready : out STD_LOGIC;
m_axi_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_arvalid : out STD_LOGIC;
m_axi_arready : in STD_LOGIC;
m_axi_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_rvalid : in STD_LOGIC;
m_axi_rready : out STD_LOGIC
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of zybo_zynq_design_auto_pc_0 : entity is true;
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of zybo_zynq_design_auto_pc_0 : entity is "zybo_zynq_design_auto_pc_0,axi_protocol_converter_v2_1_17_axi_protocol_converter,{}";
attribute DowngradeIPIdentifiedWarnings : string;
attribute DowngradeIPIdentifiedWarnings of zybo_zynq_design_auto_pc_0 : entity is "yes";
attribute X_CORE_INFO : string;
attribute X_CORE_INFO of zybo_zynq_design_auto_pc_0 : entity is "axi_protocol_converter_v2_1_17_axi_protocol_converter,Vivado 2018.2";
end zybo_zynq_design_auto_pc_0;
architecture STRUCTURE of zybo_zynq_design_auto_pc_0 is
signal NLW_inst_m_axi_wlast_UNCONNECTED : STD_LOGIC;
signal NLW_inst_m_axi_arburst_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_m_axi_arcache_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_inst_m_axi_arid_UNCONNECTED : STD_LOGIC_VECTOR ( 11 downto 0 );
signal NLW_inst_m_axi_arlen_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_inst_m_axi_arlock_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_m_axi_arqos_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_inst_m_axi_arregion_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_inst_m_axi_arsize_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_inst_m_axi_aruser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_m_axi_awburst_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_m_axi_awcache_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_inst_m_axi_awid_UNCONNECTED : STD_LOGIC_VECTOR ( 11 downto 0 );
signal NLW_inst_m_axi_awlen_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_inst_m_axi_awlock_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_m_axi_awqos_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_inst_m_axi_awregion_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_inst_m_axi_awsize_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_inst_m_axi_awuser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_m_axi_wid_UNCONNECTED : STD_LOGIC_VECTOR ( 11 downto 0 );
signal NLW_inst_m_axi_wuser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_s_axi_buser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_s_axi_ruser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
attribute C_AXI_ADDR_WIDTH : integer;
attribute C_AXI_ADDR_WIDTH of inst : label is 32;
attribute C_AXI_ARUSER_WIDTH : integer;
attribute C_AXI_ARUSER_WIDTH of inst : label is 1;
attribute C_AXI_AWUSER_WIDTH : integer;
attribute C_AXI_AWUSER_WIDTH of inst : label is 1;
attribute C_AXI_BUSER_WIDTH : integer;
attribute C_AXI_BUSER_WIDTH of inst : label is 1;
attribute C_AXI_DATA_WIDTH : integer;
attribute C_AXI_DATA_WIDTH of inst : label is 32;
attribute C_AXI_ID_WIDTH : integer;
attribute C_AXI_ID_WIDTH of inst : label is 12;
attribute C_AXI_RUSER_WIDTH : integer;
attribute C_AXI_RUSER_WIDTH of inst : label is 1;
attribute C_AXI_SUPPORTS_READ : integer;
attribute C_AXI_SUPPORTS_READ of inst : label is 1;
attribute C_AXI_SUPPORTS_USER_SIGNALS : integer;
attribute C_AXI_SUPPORTS_USER_SIGNALS of inst : label is 0;
attribute C_AXI_SUPPORTS_WRITE : integer;
attribute C_AXI_SUPPORTS_WRITE of inst : label is 1;
attribute C_AXI_WUSER_WIDTH : integer;
attribute C_AXI_WUSER_WIDTH of inst : label is 1;
attribute C_FAMILY : string;
attribute C_FAMILY of inst : label is "zynq";
attribute C_IGNORE_ID : integer;
attribute C_IGNORE_ID of inst : label is 0;
attribute C_M_AXI_PROTOCOL : integer;
attribute C_M_AXI_PROTOCOL of inst : label is 2;
attribute C_S_AXI_PROTOCOL : integer;
attribute C_S_AXI_PROTOCOL of inst : label is 1;
attribute C_TRANSLATION_MODE : integer;
attribute C_TRANSLATION_MODE of inst : label is 2;
attribute DowngradeIPIdentifiedWarnings of inst : label is "yes";
attribute P_AXI3 : integer;
attribute P_AXI3 of inst : label is 1;
attribute P_AXI4 : integer;
attribute P_AXI4 of inst : label is 0;
attribute P_AXILITE : integer;
attribute P_AXILITE of inst : label is 2;
attribute P_AXILITE_SIZE : string;
attribute P_AXILITE_SIZE of inst : label is "3'b010";
attribute P_CONVERSION : integer;
attribute P_CONVERSION of inst : label is 2;
attribute P_DECERR : string;
attribute P_DECERR of inst : label is "2'b11";
attribute P_INCR : string;
attribute P_INCR of inst : label is "2'b01";
attribute P_PROTECTION : integer;
attribute P_PROTECTION of inst : label is 1;
attribute P_SLVERR : string;
attribute P_SLVERR of inst : label is "2'b10";
attribute X_INTERFACE_INFO : string;
attribute X_INTERFACE_INFO of aclk : signal is "xilinx.com:signal:clock:1.0 CLK CLK";
attribute X_INTERFACE_PARAMETER : string;
attribute X_INTERFACE_PARAMETER of aclk : signal is "XIL_INTERFACENAME CLK, FREQ_HZ 100000000, PHASE 0.000, CLK_DOMAIN zybo_zynq_design_processing_system7_0_0_FCLK_CLK0, ASSOCIATED_BUSIF S_AXI:M_AXI, ASSOCIATED_RESET ARESETN";
attribute X_INTERFACE_INFO of aresetn : signal is "xilinx.com:signal:reset:1.0 RST RST";
attribute X_INTERFACE_PARAMETER of aresetn : signal is "XIL_INTERFACENAME RST, POLARITY ACTIVE_LOW, TYPE INTERCONNECT";
attribute X_INTERFACE_INFO of m_axi_arready : signal is "xilinx.com:interface:aximm:1.0 M_AXI ARREADY";
attribute X_INTERFACE_INFO of m_axi_arvalid : signal is "xilinx.com:interface:aximm:1.0 M_AXI ARVALID";
attribute X_INTERFACE_INFO of m_axi_awready : signal is "xilinx.com:interface:aximm:1.0 M_AXI AWREADY";
attribute X_INTERFACE_INFO of m_axi_awvalid : signal is "xilinx.com:interface:aximm:1.0 M_AXI AWVALID";
attribute X_INTERFACE_INFO of m_axi_bready : signal is "xilinx.com:interface:aximm:1.0 M_AXI BREADY";
attribute X_INTERFACE_INFO of m_axi_bvalid : signal is "xilinx.com:interface:aximm:1.0 M_AXI BVALID";
attribute X_INTERFACE_INFO of m_axi_rready : signal is "xilinx.com:interface:aximm:1.0 M_AXI RREADY";
attribute X_INTERFACE_PARAMETER of m_axi_rready : signal is "XIL_INTERFACENAME M_AXI, DATA_WIDTH 32, PROTOCOL AXI4LITE, FREQ_HZ 100000000, ID_WIDTH 0, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 1, HAS_CACHE 0, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 8, NUM_WRITE_OUTSTANDING 8, MAX_BURST_LENGTH 1, PHASE 0.000, CLK_DOMAIN zybo_zynq_design_processing_system7_0_0_FCLK_CLK0, NUM_READ_THREADS 4, NUM_WRITE_THREADS 4, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0";
attribute X_INTERFACE_INFO of m_axi_rvalid : signal is "xilinx.com:interface:aximm:1.0 M_AXI RVALID";
attribute X_INTERFACE_INFO of m_axi_wready : signal is "xilinx.com:interface:aximm:1.0 M_AXI WREADY";
attribute X_INTERFACE_INFO of m_axi_wvalid : signal is "xilinx.com:interface:aximm:1.0 M_AXI WVALID";
attribute X_INTERFACE_INFO of s_axi_arready : signal is "xilinx.com:interface:aximm:1.0 S_AXI ARREADY";
attribute X_INTERFACE_INFO of s_axi_arvalid : signal is "xilinx.com:interface:aximm:1.0 S_AXI ARVALID";
attribute X_INTERFACE_INFO of s_axi_awready : signal is "xilinx.com:interface:aximm:1.0 S_AXI AWREADY";
attribute X_INTERFACE_INFO of s_axi_awvalid : signal is "xilinx.com:interface:aximm:1.0 S_AXI AWVALID";
attribute X_INTERFACE_INFO of s_axi_bready : signal is "xilinx.com:interface:aximm:1.0 S_AXI BREADY";
attribute X_INTERFACE_INFO of s_axi_bvalid : signal is "xilinx.com:interface:aximm:1.0 S_AXI BVALID";
attribute X_INTERFACE_INFO of s_axi_rlast : signal is "xilinx.com:interface:aximm:1.0 S_AXI RLAST";
attribute X_INTERFACE_INFO of s_axi_rready : signal is "xilinx.com:interface:aximm:1.0 S_AXI RREADY";
attribute X_INTERFACE_PARAMETER of s_axi_rready : signal is "XIL_INTERFACENAME S_AXI, DATA_WIDTH 32, PROTOCOL AXI3, FREQ_HZ 100000000, ID_WIDTH 12, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 1, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 1, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 8, NUM_WRITE_OUTSTANDING 8, MAX_BURST_LENGTH 16, PHASE 0.000, CLK_DOMAIN zybo_zynq_design_processing_system7_0_0_FCLK_CLK0, NUM_READ_THREADS 4, NUM_WRITE_THREADS 4, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0";
attribute X_INTERFACE_INFO of s_axi_rvalid : signal is "xilinx.com:interface:aximm:1.0 S_AXI RVALID";
attribute X_INTERFACE_INFO of s_axi_wlast : signal is "xilinx.com:interface:aximm:1.0 S_AXI WLAST";
attribute X_INTERFACE_INFO of s_axi_wready : signal is "xilinx.com:interface:aximm:1.0 S_AXI WREADY";
attribute X_INTERFACE_INFO of s_axi_wvalid : signal is "xilinx.com:interface:aximm:1.0 S_AXI WVALID";
attribute X_INTERFACE_INFO of m_axi_araddr : signal is "xilinx.com:interface:aximm:1.0 M_AXI ARADDR";
attribute X_INTERFACE_INFO of m_axi_arprot : signal is "xilinx.com:interface:aximm:1.0 M_AXI ARPROT";
attribute X_INTERFACE_INFO of m_axi_awaddr : signal is "xilinx.com:interface:aximm:1.0 M_AXI AWADDR";
attribute X_INTERFACE_INFO of m_axi_awprot : signal is "xilinx.com:interface:aximm:1.0 M_AXI AWPROT";
attribute X_INTERFACE_INFO of m_axi_bresp : signal is "xilinx.com:interface:aximm:1.0 M_AXI BRESP";
attribute X_INTERFACE_INFO of m_axi_rdata : signal is "xilinx.com:interface:aximm:1.0 M_AXI RDATA";
attribute X_INTERFACE_INFO of m_axi_rresp : signal is "xilinx.com:interface:aximm:1.0 M_AXI RRESP";
attribute X_INTERFACE_INFO of m_axi_wdata : signal is "xilinx.com:interface:aximm:1.0 M_AXI WDATA";
attribute X_INTERFACE_INFO of m_axi_wstrb : signal is "xilinx.com:interface:aximm:1.0 M_AXI WSTRB";
attribute X_INTERFACE_INFO of s_axi_araddr : signal is "xilinx.com:interface:aximm:1.0 S_AXI ARADDR";
attribute X_INTERFACE_INFO of s_axi_arburst : signal is "xilinx.com:interface:aximm:1.0 S_AXI ARBURST";
attribute X_INTERFACE_INFO of s_axi_arcache : signal is "xilinx.com:interface:aximm:1.0 S_AXI ARCACHE";
attribute X_INTERFACE_INFO of s_axi_arid : signal is "xilinx.com:interface:aximm:1.0 S_AXI ARID";
attribute X_INTERFACE_INFO of s_axi_arlen : signal is "xilinx.com:interface:aximm:1.0 S_AXI ARLEN";
attribute X_INTERFACE_INFO of s_axi_arlock : signal is "xilinx.com:interface:aximm:1.0 S_AXI ARLOCK";
attribute X_INTERFACE_INFO of s_axi_arprot : signal is "xilinx.com:interface:aximm:1.0 S_AXI ARPROT";
attribute X_INTERFACE_INFO of s_axi_arqos : signal is "xilinx.com:interface:aximm:1.0 S_AXI ARQOS";
attribute X_INTERFACE_INFO of s_axi_arsize : signal is "xilinx.com:interface:aximm:1.0 S_AXI ARSIZE";
attribute X_INTERFACE_INFO of s_axi_awaddr : signal is "xilinx.com:interface:aximm:1.0 S_AXI AWADDR";
attribute X_INTERFACE_INFO of s_axi_awburst : signal is "xilinx.com:interface:aximm:1.0 S_AXI AWBURST";
attribute X_INTERFACE_INFO of s_axi_awcache : signal is "xilinx.com:interface:aximm:1.0 S_AXI AWCACHE";
attribute X_INTERFACE_INFO of s_axi_awid : signal is "xilinx.com:interface:aximm:1.0 S_AXI AWID";
attribute X_INTERFACE_INFO of s_axi_awlen : signal is "xilinx.com:interface:aximm:1.0 S_AXI AWLEN";
attribute X_INTERFACE_INFO of s_axi_awlock : signal is "xilinx.com:interface:aximm:1.0 S_AXI AWLOCK";
attribute X_INTERFACE_INFO of s_axi_awprot : signal is "xilinx.com:interface:aximm:1.0 S_AXI AWPROT";
attribute X_INTERFACE_INFO of s_axi_awqos : signal is "xilinx.com:interface:aximm:1.0 S_AXI AWQOS";
attribute X_INTERFACE_INFO of s_axi_awsize : signal is "xilinx.com:interface:aximm:1.0 S_AXI AWSIZE";
attribute X_INTERFACE_INFO of s_axi_bid : signal is "xilinx.com:interface:aximm:1.0 S_AXI BID";
attribute X_INTERFACE_INFO of s_axi_bresp : signal is "xilinx.com:interface:aximm:1.0 S_AXI BRESP";
attribute X_INTERFACE_INFO of s_axi_rdata : signal is "xilinx.com:interface:aximm:1.0 S_AXI RDATA";
attribute X_INTERFACE_INFO of s_axi_rid : signal is "xilinx.com:interface:aximm:1.0 S_AXI RID";
attribute X_INTERFACE_INFO of s_axi_rresp : signal is "xilinx.com:interface:aximm:1.0 S_AXI RRESP";
attribute X_INTERFACE_INFO of s_axi_wdata : signal is "xilinx.com:interface:aximm:1.0 S_AXI WDATA";
attribute X_INTERFACE_INFO of s_axi_wid : signal is "xilinx.com:interface:aximm:1.0 S_AXI WID";
attribute X_INTERFACE_INFO of s_axi_wstrb : signal is "xilinx.com:interface:aximm:1.0 S_AXI WSTRB";
begin
inst: entity work.zybo_zynq_design_auto_pc_0_axi_protocol_converter_v2_1_17_axi_protocol_converter
port map (
aclk => aclk,
aresetn => aresetn,
m_axi_araddr(31 downto 0) => m_axi_araddr(31 downto 0),
m_axi_arburst(1 downto 0) => NLW_inst_m_axi_arburst_UNCONNECTED(1 downto 0),
m_axi_arcache(3 downto 0) => NLW_inst_m_axi_arcache_UNCONNECTED(3 downto 0),
m_axi_arid(11 downto 0) => NLW_inst_m_axi_arid_UNCONNECTED(11 downto 0),
m_axi_arlen(7 downto 0) => NLW_inst_m_axi_arlen_UNCONNECTED(7 downto 0),
m_axi_arlock(0) => NLW_inst_m_axi_arlock_UNCONNECTED(0),
m_axi_arprot(2 downto 0) => m_axi_arprot(2 downto 0),
m_axi_arqos(3 downto 0) => NLW_inst_m_axi_arqos_UNCONNECTED(3 downto 0),
m_axi_arready => m_axi_arready,
m_axi_arregion(3 downto 0) => NLW_inst_m_axi_arregion_UNCONNECTED(3 downto 0),
m_axi_arsize(2 downto 0) => NLW_inst_m_axi_arsize_UNCONNECTED(2 downto 0),
m_axi_aruser(0) => NLW_inst_m_axi_aruser_UNCONNECTED(0),
m_axi_arvalid => m_axi_arvalid,
m_axi_awaddr(31 downto 0) => m_axi_awaddr(31 downto 0),
m_axi_awburst(1 downto 0) => NLW_inst_m_axi_awburst_UNCONNECTED(1 downto 0),
m_axi_awcache(3 downto 0) => NLW_inst_m_axi_awcache_UNCONNECTED(3 downto 0),
m_axi_awid(11 downto 0) => NLW_inst_m_axi_awid_UNCONNECTED(11 downto 0),
m_axi_awlen(7 downto 0) => NLW_inst_m_axi_awlen_UNCONNECTED(7 downto 0),
m_axi_awlock(0) => NLW_inst_m_axi_awlock_UNCONNECTED(0),
m_axi_awprot(2 downto 0) => m_axi_awprot(2 downto 0),
m_axi_awqos(3 downto 0) => NLW_inst_m_axi_awqos_UNCONNECTED(3 downto 0),
m_axi_awready => m_axi_awready,
m_axi_awregion(3 downto 0) => NLW_inst_m_axi_awregion_UNCONNECTED(3 downto 0),
m_axi_awsize(2 downto 0) => NLW_inst_m_axi_awsize_UNCONNECTED(2 downto 0),
m_axi_awuser(0) => NLW_inst_m_axi_awuser_UNCONNECTED(0),
m_axi_awvalid => m_axi_awvalid,
m_axi_bid(11 downto 0) => B"000000000000",
m_axi_bready => m_axi_bready,
m_axi_bresp(1 downto 0) => m_axi_bresp(1 downto 0),
m_axi_buser(0) => '0',
m_axi_bvalid => m_axi_bvalid,
m_axi_rdata(31 downto 0) => m_axi_rdata(31 downto 0),
m_axi_rid(11 downto 0) => B"000000000000",
m_axi_rlast => '1',
m_axi_rready => m_axi_rready,
m_axi_rresp(1 downto 0) => m_axi_rresp(1 downto 0),
m_axi_ruser(0) => '0',
m_axi_rvalid => m_axi_rvalid,
m_axi_wdata(31 downto 0) => m_axi_wdata(31 downto 0),
m_axi_wid(11 downto 0) => NLW_inst_m_axi_wid_UNCONNECTED(11 downto 0),
m_axi_wlast => NLW_inst_m_axi_wlast_UNCONNECTED,
m_axi_wready => m_axi_wready,
m_axi_wstrb(3 downto 0) => m_axi_wstrb(3 downto 0),
m_axi_wuser(0) => NLW_inst_m_axi_wuser_UNCONNECTED(0),
m_axi_wvalid => m_axi_wvalid,
s_axi_araddr(31 downto 0) => s_axi_araddr(31 downto 0),
s_axi_arburst(1 downto 0) => s_axi_arburst(1 downto 0),
s_axi_arcache(3 downto 0) => s_axi_arcache(3 downto 0),
s_axi_arid(11 downto 0) => s_axi_arid(11 downto 0),
s_axi_arlen(3 downto 0) => s_axi_arlen(3 downto 0),
s_axi_arlock(1 downto 0) => s_axi_arlock(1 downto 0),
s_axi_arprot(2 downto 0) => s_axi_arprot(2 downto 0),
s_axi_arqos(3 downto 0) => s_axi_arqos(3 downto 0),
s_axi_arready => s_axi_arready,
s_axi_arregion(3 downto 0) => B"0000",
s_axi_arsize(2 downto 0) => s_axi_arsize(2 downto 0),
s_axi_aruser(0) => '0',
s_axi_arvalid => s_axi_arvalid,
s_axi_awaddr(31 downto 0) => s_axi_awaddr(31 downto 0),
s_axi_awburst(1 downto 0) => s_axi_awburst(1 downto 0),
s_axi_awcache(3 downto 0) => s_axi_awcache(3 downto 0),
s_axi_awid(11 downto 0) => s_axi_awid(11 downto 0),
s_axi_awlen(3 downto 0) => s_axi_awlen(3 downto 0),
s_axi_awlock(1 downto 0) => s_axi_awlock(1 downto 0),
s_axi_awprot(2 downto 0) => s_axi_awprot(2 downto 0),
s_axi_awqos(3 downto 0) => s_axi_awqos(3 downto 0),
s_axi_awready => s_axi_awready,
s_axi_awregion(3 downto 0) => B"0000",
s_axi_awsize(2 downto 0) => s_axi_awsize(2 downto 0),
s_axi_awuser(0) => '0',
s_axi_awvalid => s_axi_awvalid,
s_axi_bid(11 downto 0) => s_axi_bid(11 downto 0),
s_axi_bready => s_axi_bready,
s_axi_bresp(1 downto 0) => s_axi_bresp(1 downto 0),
s_axi_buser(0) => NLW_inst_s_axi_buser_UNCONNECTED(0),
s_axi_bvalid => s_axi_bvalid,
s_axi_rdata(31 downto 0) => s_axi_rdata(31 downto 0),
s_axi_rid(11 downto 0) => s_axi_rid(11 downto 0),
s_axi_rlast => s_axi_rlast,
s_axi_rready => s_axi_rready,
s_axi_rresp(1 downto 0) => s_axi_rresp(1 downto 0),
s_axi_ruser(0) => NLW_inst_s_axi_ruser_UNCONNECTED(0),
s_axi_rvalid => s_axi_rvalid,
s_axi_wdata(31 downto 0) => s_axi_wdata(31 downto 0),
s_axi_wid(11 downto 0) => s_axi_wid(11 downto 0),
s_axi_wlast => s_axi_wlast,
s_axi_wready => s_axi_wready,
s_axi_wstrb(3 downto 0) => s_axi_wstrb(3 downto 0),
s_axi_wuser(0) => '0',
s_axi_wvalid => s_axi_wvalid
);
end STRUCTURE;
| mit | 8d6f7f19aa1e780e1b3a65499935f99d | 0.536355 | 2.547661 | false | false | false | false |
MartinCura/SistDig-TP4 | old/testers/det_angulos_tb.vhd | 1 | 2,715 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.cordic_lib.all;
--library ieee_proposed;
--use ieee_proposed.float_pkg.all;
library floatfixlib;
use floatfixlib.float_pkg.all;
entity det_angulos_tb is
generic(
N_BITS_COORD : integer := 32 --- REVISAR
);
port(
--clk_i: in std_logic; -- Clock general
alfa, beta, gama: out t_float := CERO
);
--attribute loc: string;
--attribute loc of clk_i: signal is "B8";
end;
architecture det_angulos_tb_arq of det_angulos_tb is
constant PASO_ANG : t_float := "00111111001101000000000000000000"; -- Paso angular ∆φ: 0.703125 grados
constant PASO_ANG_R : t_float := PI_PF * PASO_ANG / 180; -- Paso angular en radianes
-- Entrada
signal clk_t : std_logic := '1';
signal rot_x_ng, rot_y_ng, rot_z_ng, inc_alfa, inc_beta, inc_gama, rst_angs_t, rst_t : std_logic := '0';
-- Salida
-- signal rot_ena: std_logic := '0'; -- Enable de rotar
signal ena_o: std_logic := '1';
signal rst_angs: std_logic := '0';
signal alfa_aux, beta_aux, gama_aux: t_float := CERO;
signal off : std_logic := '0';
begin
clk_t <= not clk_t after 5 ns;
inc_alfa <= '1' after 20 ns, '0' after 25 ns, '1' after 100 ns, '0' after 105 ns, '1' after 160 ns, '0' after 165 ns;
inc_beta <= '1' after 40 ns, '0' after 45 ns, '1' after 100 ns, '0' after 115 ns, '1' after 220 ns, '0' after 225 ns;
inc_gama <= '1' after 60 ns, '0' after 65 ns, '1' after 100 ns, '0' after 105 ns, '1' after 160 ns, '0' after 175 ns;
rot_x_ng <= '1' after 150 ns;
---rot_y_ng <=
---rot_z_ng <=
ena_o <= '0' after 105 ns;
rst_angs_t <= '1' after 200 ns, '0' after 205 ns;
rst_t <= '1' after 240 ns;
off <= '1' after 260 ns;
-- *** LEER Y ROTAR ***
--- Si hiciéramos rotación constante:
--- 3 contadores de pasos angulares en cada eje,
--- se multiplican a la velocidad de rotación (lenta o rápida según rot_vel),
--- y eso son los 3 ángulos: alfa, beta, gama.
rst_angs <= rst_angs_t or rst_t;
-- Obtengo los ángulos de rotación para cada eje
angles: entity work.det_angulos
generic map(
C => 1
) port map(
clk_t,
ena_o, -- and rot_ena,
rst_angs,
inc_alfa, inc_beta, inc_gama,
rot_x_ng, rot_y_ng, rot_z_ng,
alfa_aux, beta_aux, gama_aux
);
alfa <= alfa_aux;
beta <= beta_aux;
gama <= gama_aux;
process(clk_t)
begin
if rising_edge(clk_t) then
if off = '0' then
report "alfa: " & integer'image(to_integer(to_signed(alfa_aux/PASO_ANG,32)))
& " beta: " & integer'image(to_integer(to_signed(beta_aux/PASO_ANG,32)))
& " gama: " & integer'image(to_integer(to_signed(gama_aux/PASO_ANG,32)))
severity note;
end if;
end if;
end process;
end;
| gpl-3.0 | 2ae8ae340fd8e61ad47866ccd4eaca28 | 0.62574 | 2.42947 | false | false | false | false |
varunnagpaal/Digital-Hardware-Modelling | vhdl/filter/fir/header.vhdl | 1 | 3,465 | library IEEE;
use IEEE.std_logic_1164.all;
entity inv is
port(inb: in STD_logic;
outb: out STD_Logic);
end inv;
architecture structure of inv is
begin
outb <= not (inb);
end structure;
library IEEE;
use IEEE.std_logic_1164.all;
entity nand2 is
port(a, b: in STD_logic;
outb: out STD_Logic);
end nand2;
architecture structure of nand2 is
begin
outb <= not(a and b);
end structure;
library IEEE;
use IEEE.std_logic_1164.all;
entity nand3 is
port(a, b, c: in STD_logic;
outb: out STD_Logic);
end nand3 ;
architecture structure of nand3 is
begin
outb <= not(a and b and c);
end structure;
library IEEE;
use IEEE.std_logic_1164.all;
entity nand4 is
port(a, b, c, d: in STD_logic;
outb: out STD_Logic);
end nand4 ;
architecture structure of nand4 is
begin
outb <= not(a and b and c and d);
end structure;
library IEEE;
use IEEE.std_logic_1164.all;
entity nor2 is
port(a, b: in STD_logic;
outb: out STD_Logic);
end nor2 ;
architecture structure of nor2 is
begin
outb <= not(a or b);
end structure;
library IEEE;
use IEEE.std_logic_1164.all;
entity nor3 is
port(a, b, c: in STD_logic;
outb: out STD_Logic);
end nor3 ;
architecture structure of nor3 is
begin
outb <= not(a or b or c);
end structure;
library IEEE;
use IEEE.std_logic_1164.all;
entity xor2 is
port(a, b: in STD_logic;
outb: out STD_Logic);
end xor2 ;
architecture structure of xor2 is
begin
outb <= (a xor b);
end structure;
library IEEE;
use IEEE.std_logic_1164.all;
entity aoi12 is
port(a, b, c: in STD_logic;
outb: out STD_Logic);
end aoi12 ;
architecture structure of aoi12 is
begin
outb <= not(a or (b and c));
end structure;
library IEEE;
use IEEE.std_logic_1164.all;
entity aoi22 is
port(a, b, c, d: in STD_logic;
outb: out STD_Logic);
end aoi22 ;
architecture structure of aoi22 is
begin
outb <= not((a and b) or (c and d));
end structure;
library IEEE;
use IEEE.std_logic_1164.all;
entity oai12 is
port(a, b, c: in STD_logic;
outb: out STD_Logic);
end oai12;
architecture structure of oai12 is
begin
outb <= not(a and (b or c));
end structure;
library IEEE;
use IEEE.std_logic_1164.all;
entity oai22 is
port(a, b, c, d: in STD_logic;
outb: out STD_Logic);
end oai22;
architecture structure of oai22 is
begin
outb <= not((a or b) and (c or d));
end structure;
library IEEE;
use IEEE.std_logic_1164.all;
entity dff is
port(d, gclk, rnot: in STD_logic;
q: out STD_Logic);
end dff;
architecture structure of dff is
begin
dff_mem: process(gclk,rnot)
begin
if ( rnot = '0' ) then
q <= '0';
elsif ( rising_edge(gclk) ) then
q <= d;
end if;
end process dff_mem;
end structure;
library IEEE;
use IEEE.std_logic_1164.all;
entity dff_asyncrsthl is
port(d, gclk, asyncrsthl: in STD_logic;
q: out STD_Logic);
end dff_asyncrsthl;
architecture structure of dff_asyncrsthl is
begin
dff_asyncrsthl_mem: process(gclk, asyncrsthl)
begin
if( asyncrsthl = '1' ) then
q <= '0';
elsif ( rising_edge(gclk) ) then
q <= d;
end if;
end process dff_asyncrsthl_mem;
end structure;
library IEEE;
use IEEE.std_logic_1164.all;
entity dff_asyncprehh is
port(d, gclk, asyncprehh: in STD_logic;
q: out STD_Logic);
end dff_asyncprehh;
architecture structure of dff_asyncprehh is
begin
dff_asyncprehh_mem: process(gclk, asyncprehh)
begin
if( asyncprehh = '1' ) then
q <= '1';
elsif ( rising_edge(gclk) ) then
q <= d;
end if;
end process dff_asyncprehh_mem;
end structure;
| mit | cb880bdf47e03017bf2db69263941fe9 | 0.689177 | 2.734807 | false | false | false | false |
kuba-moo/VHDL-lib | mod_uart_regs.vhd | 2 | 3,969 | -- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>
--
-- Copyright (C) 2014 Jakub Kicinski <[email protected]>
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_ARITH.all;
use IEEE.STD_LOGIC_UNSIGNED.all;
use work.globals.all;
-- bundle of uart rx/tx and reg master
entity mod_uart_regs is
generic (UART_RATE : integer;
REQ_SIZE : integer);
port (Clk : in std_logic;
Rst : in std_logic;
RsRx : in std_logic;
RsTx : out std_logic;
RegBusStart : out reg_bus_t;
RegBusEnd : in reg_bus_t);
end mod_uart_regs;
-- Dependencies:
-- uart_rx, freq_generator, uart_tx, reg_master_uart
--
-- Operation:
-- Create register bus master on UART.
-- This is a bundle created for convenience.
architecture Behavioral of mod_uart_regs is
component uart_rx is
generic (FREQUENCY : integer);
port (Clk : in std_logic;
Rst : in std_logic;
RsRx : in std_logic;
Byte : out byte_t;
Valid : out std_logic);
end component;
signal RxByte : byte_t;
signal RxValid : std_logic;
component freq_generator is
generic (FREQUENCY : integer; -- target freq
CLK_FREQUENCY : integer := FPGA_CLK_FREQ);
port (Clk : in std_logic;
Rst : in std_logic;
Output : out std_logic);
end component;
signal enTxFreq : std_logic;
component uart_tx is
port (Clk : in std_logic;
Rst : in std_logic;
FreqEn : in std_logic;
Byte : in std_logic_vector(7 downto 0);
Kick : in std_logic;
RsTx : out std_logic;
Busy : out std_logic);
end component;
signal TxKick, TxBusy : std_logic;
signal TxByte : byte_t;
component reg_master_uart is
generic (REQ_SIZE : integer); -- #bytes per req
port (Clk : in std_logic;
Rst : in std_logic;
RxByte : in byte_t;
RxValid : in std_logic;
TxByte : out byte_t;
TxKick : out std_logic;
TxBusy : in std_logic;
BusO : out reg_bus_t;
BusI : in reg_bus_t);
end component;
begin
rx : uart_rx
generic map(FREQUENCY => UART_RATE)
port map(Clk => Clk,
Rst => Rst,
RsRx => RsRx,
Byte => RxByte,
Valid => RxValid);
tx_freq : freq_generator
generic map(FREQUENCY => UART_RATE)
port map(Clk, Rst, enTxFreq);
tx : uart_tx
port map(Clk => Clk,
Rst => Rst,
FreqEn => enTxFreq,
Byte => TxByte,
Kick => TxKick,
RsTx => RsTx,
Busy => TxBusy);
master : reg_master_uart
generic map(REQ_SIZE => REQ_SIZE)
port map(Clk => Clk,
Rst => Rst,
RxByte => RxByte,
RxValid => RxValid,
TxByte => TxByte,
TxKick => TxKick,
TxBusy => TxBusy,
BusO => RegBusStart,
BusI => RegBusEnd);
end Behavioral;
| gpl-3.0 | aadf862468fa52c8243ca4d30fb0a7dc | 0.529101 | 3.949254 | false | false | false | false |
varunnagpaal/Digital-Hardware-Modelling | xilinx-vivado-hls/gcd/solution1/syn/vhdl/gcd.vhd | 3 | 12,561 | -- ==============================================================
-- RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2018.2
-- Copyright (C) 1986-2018 Xilinx, Inc. All Rights Reserved.
--
-- ===========================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity gcd is
generic (
C_S_AXI_GCD_BUS_ADDR_WIDTH : INTEGER := 6;
C_S_AXI_GCD_BUS_DATA_WIDTH : INTEGER := 32 );
port (
ap_clk : IN STD_LOGIC;
ap_rst_n : IN STD_LOGIC;
s_axi_gcd_bus_AWVALID : IN STD_LOGIC;
s_axi_gcd_bus_AWREADY : OUT STD_LOGIC;
s_axi_gcd_bus_AWADDR : IN STD_LOGIC_VECTOR (C_S_AXI_GCD_BUS_ADDR_WIDTH-1 downto 0);
s_axi_gcd_bus_WVALID : IN STD_LOGIC;
s_axi_gcd_bus_WREADY : OUT STD_LOGIC;
s_axi_gcd_bus_WDATA : IN STD_LOGIC_VECTOR (C_S_AXI_GCD_BUS_DATA_WIDTH-1 downto 0);
s_axi_gcd_bus_WSTRB : IN STD_LOGIC_VECTOR (C_S_AXI_GCD_BUS_DATA_WIDTH/8-1 downto 0);
s_axi_gcd_bus_ARVALID : IN STD_LOGIC;
s_axi_gcd_bus_ARREADY : OUT STD_LOGIC;
s_axi_gcd_bus_ARADDR : IN STD_LOGIC_VECTOR (C_S_AXI_GCD_BUS_ADDR_WIDTH-1 downto 0);
s_axi_gcd_bus_RVALID : OUT STD_LOGIC;
s_axi_gcd_bus_RREADY : IN STD_LOGIC;
s_axi_gcd_bus_RDATA : OUT STD_LOGIC_VECTOR (C_S_AXI_GCD_BUS_DATA_WIDTH-1 downto 0);
s_axi_gcd_bus_RRESP : OUT STD_LOGIC_VECTOR (1 downto 0);
s_axi_gcd_bus_BVALID : OUT STD_LOGIC;
s_axi_gcd_bus_BREADY : IN STD_LOGIC;
s_axi_gcd_bus_BRESP : OUT STD_LOGIC_VECTOR (1 downto 0);
interrupt : OUT STD_LOGIC );
end;
architecture behav of gcd is
attribute CORE_GENERATION_INFO : STRING;
attribute CORE_GENERATION_INFO of behav : architecture is
"gcd,hls_ip_2018_2,{HLS_INPUT_TYPE=c,HLS_INPUT_FLOAT=0,HLS_INPUT_FIXED=1,HLS_INPUT_PART=xc7z010clg400-1,HLS_INPUT_CLOCK=3.000000,HLS_INPUT_ARCH=others,HLS_SYN_CLOCK=2.429000,HLS_SYN_LAT=-1,HLS_SYN_TPT=none,HLS_SYN_MEM=0,HLS_SYN_DSP=0,HLS_SYN_FF=203,HLS_SYN_LUT=285,HLS_VERSION=2018_2}";
constant ap_const_logic_1 : STD_LOGIC := '1';
constant ap_const_logic_0 : STD_LOGIC := '0';
constant ap_ST_fsm_state1 : STD_LOGIC_VECTOR (3 downto 0) := "0001";
constant ap_ST_fsm_state2 : STD_LOGIC_VECTOR (3 downto 0) := "0010";
constant ap_ST_fsm_state3 : STD_LOGIC_VECTOR (3 downto 0) := "0100";
constant ap_ST_fsm_state4 : STD_LOGIC_VECTOR (3 downto 0) := "1000";
constant ap_const_lv32_0 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000000";
constant C_S_AXI_DATA_WIDTH : INTEGER range 63 downto 0 := 20;
constant ap_const_lv32_2 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000010";
constant ap_const_lv1_0 : STD_LOGIC_VECTOR (0 downto 0) := "0";
constant ap_const_lv32_3 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000011";
constant ap_const_lv32_1 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000001";
constant ap_const_lv1_1 : STD_LOGIC_VECTOR (0 downto 0) := "1";
constant ap_const_boolean_1 : BOOLEAN := true;
signal ap_rst_n_inv : STD_LOGIC;
signal ap_start : STD_LOGIC;
signal ap_done : STD_LOGIC;
signal ap_idle : STD_LOGIC;
signal ap_CS_fsm : STD_LOGIC_VECTOR (3 downto 0) := "0001";
attribute fsm_encoding : string;
attribute fsm_encoding of ap_CS_fsm : signal is "none";
signal ap_CS_fsm_state1 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state1 : signal is "none";
signal ap_ready : STD_LOGIC;
signal a : STD_LOGIC_VECTOR (15 downto 0);
signal b : STD_LOGIC_VECTOR (15 downto 0);
signal pResult_ap_vld : STD_LOGIC;
signal b_read_reg_102 : STD_LOGIC_VECTOR (15 downto 0);
signal a_read_reg_107 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_3_fu_72_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_3_reg_115 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_CS_fsm_state3 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state3 : signal is "none";
signal tmp_2_fu_66_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal a_assign_fu_78_p2 : STD_LOGIC_VECTOR (15 downto 0);
signal a_assign_reg_121 : STD_LOGIC_VECTOR (15 downto 0);
signal b_assign_fu_84_p2 : STD_LOGIC_VECTOR (15 downto 0);
signal b_assign_reg_126 : STD_LOGIC_VECTOR (15 downto 0);
signal b_assign_1_fu_90_p3 : STD_LOGIC_VECTOR (15 downto 0);
signal ap_CS_fsm_state4 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state4 : signal is "none";
signal a_assign_1_fu_96_p3 : STD_LOGIC_VECTOR (15 downto 0);
signal p_s_reg_45 : STD_LOGIC_VECTOR (15 downto 0);
signal ap_CS_fsm_state2 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state2 : signal is "none";
signal result_reg_56 : STD_LOGIC_VECTOR (15 downto 0);
signal ap_NS_fsm : STD_LOGIC_VECTOR (3 downto 0);
component gcd_gcd_bus_s_axi IS
generic (
C_S_AXI_ADDR_WIDTH : INTEGER;
C_S_AXI_DATA_WIDTH : INTEGER );
port (
AWVALID : IN STD_LOGIC;
AWREADY : OUT STD_LOGIC;
AWADDR : IN STD_LOGIC_VECTOR (C_S_AXI_ADDR_WIDTH-1 downto 0);
WVALID : IN STD_LOGIC;
WREADY : OUT STD_LOGIC;
WDATA : IN STD_LOGIC_VECTOR (C_S_AXI_DATA_WIDTH-1 downto 0);
WSTRB : IN STD_LOGIC_VECTOR (C_S_AXI_DATA_WIDTH/8-1 downto 0);
ARVALID : IN STD_LOGIC;
ARREADY : OUT STD_LOGIC;
ARADDR : IN STD_LOGIC_VECTOR (C_S_AXI_ADDR_WIDTH-1 downto 0);
RVALID : OUT STD_LOGIC;
RREADY : IN STD_LOGIC;
RDATA : OUT STD_LOGIC_VECTOR (C_S_AXI_DATA_WIDTH-1 downto 0);
RRESP : OUT STD_LOGIC_VECTOR (1 downto 0);
BVALID : OUT STD_LOGIC;
BREADY : IN STD_LOGIC;
BRESP : OUT STD_LOGIC_VECTOR (1 downto 0);
ACLK : IN STD_LOGIC;
ARESET : IN STD_LOGIC;
ACLK_EN : IN STD_LOGIC;
ap_start : OUT STD_LOGIC;
interrupt : OUT STD_LOGIC;
ap_ready : IN STD_LOGIC;
ap_done : IN STD_LOGIC;
ap_idle : IN STD_LOGIC;
a : OUT STD_LOGIC_VECTOR (15 downto 0);
b : OUT STD_LOGIC_VECTOR (15 downto 0);
pResult : IN STD_LOGIC_VECTOR (15 downto 0);
pResult_ap_vld : IN STD_LOGIC );
end component;
begin
gcd_gcd_bus_s_axi_U : component gcd_gcd_bus_s_axi
generic map (
C_S_AXI_ADDR_WIDTH => C_S_AXI_GCD_BUS_ADDR_WIDTH,
C_S_AXI_DATA_WIDTH => C_S_AXI_GCD_BUS_DATA_WIDTH)
port map (
AWVALID => s_axi_gcd_bus_AWVALID,
AWREADY => s_axi_gcd_bus_AWREADY,
AWADDR => s_axi_gcd_bus_AWADDR,
WVALID => s_axi_gcd_bus_WVALID,
WREADY => s_axi_gcd_bus_WREADY,
WDATA => s_axi_gcd_bus_WDATA,
WSTRB => s_axi_gcd_bus_WSTRB,
ARVALID => s_axi_gcd_bus_ARVALID,
ARREADY => s_axi_gcd_bus_ARREADY,
ARADDR => s_axi_gcd_bus_ARADDR,
RVALID => s_axi_gcd_bus_RVALID,
RREADY => s_axi_gcd_bus_RREADY,
RDATA => s_axi_gcd_bus_RDATA,
RRESP => s_axi_gcd_bus_RRESP,
BVALID => s_axi_gcd_bus_BVALID,
BREADY => s_axi_gcd_bus_BREADY,
BRESP => s_axi_gcd_bus_BRESP,
ACLK => ap_clk,
ARESET => ap_rst_n_inv,
ACLK_EN => ap_const_logic_1,
ap_start => ap_start,
interrupt => interrupt,
ap_ready => ap_ready,
ap_done => ap_done,
ap_idle => ap_idle,
a => a,
b => b,
pResult => p_s_reg_45,
pResult_ap_vld => pResult_ap_vld);
ap_CS_fsm_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_CS_fsm <= ap_ST_fsm_state1;
else
ap_CS_fsm <= ap_NS_fsm;
end if;
end if;
end process;
p_s_reg_45_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_CS_fsm_state4)) then
p_s_reg_45 <= b_assign_1_fu_90_p3;
elsif ((ap_const_logic_1 = ap_CS_fsm_state2)) then
p_s_reg_45 <= b_read_reg_102;
end if;
end if;
end process;
result_reg_56_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_CS_fsm_state4)) then
result_reg_56 <= a_assign_1_fu_96_p3;
elsif ((ap_const_logic_1 = ap_CS_fsm_state2)) then
result_reg_56 <= a_read_reg_107;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((tmp_2_fu_66_p2 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_state3))) then
a_assign_reg_121 <= a_assign_fu_78_p2;
b_assign_reg_126 <= b_assign_fu_84_p2;
tmp_3_reg_115 <= tmp_3_fu_72_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_state1) and (ap_start = ap_const_logic_1))) then
a_read_reg_107 <= a;
b_read_reg_102 <= b;
end if;
end if;
end process;
ap_NS_fsm_assign_proc : process (ap_start, ap_CS_fsm, ap_CS_fsm_state1, ap_CS_fsm_state3, tmp_2_fu_66_p2)
begin
case ap_CS_fsm is
when ap_ST_fsm_state1 =>
if (((ap_const_logic_1 = ap_CS_fsm_state1) and (ap_start = ap_const_logic_1))) then
ap_NS_fsm <= ap_ST_fsm_state2;
else
ap_NS_fsm <= ap_ST_fsm_state1;
end if;
when ap_ST_fsm_state2 =>
ap_NS_fsm <= ap_ST_fsm_state3;
when ap_ST_fsm_state3 =>
if (((tmp_2_fu_66_p2 = ap_const_lv1_1) and (ap_const_logic_1 = ap_CS_fsm_state3))) then
ap_NS_fsm <= ap_ST_fsm_state1;
else
ap_NS_fsm <= ap_ST_fsm_state4;
end if;
when ap_ST_fsm_state4 =>
ap_NS_fsm <= ap_ST_fsm_state3;
when others =>
ap_NS_fsm <= "XXXX";
end case;
end process;
a_assign_1_fu_96_p3 <=
a_assign_reg_121 when (tmp_3_reg_115(0) = '1') else
result_reg_56;
a_assign_fu_78_p2 <= std_logic_vector(unsigned(result_reg_56) - unsigned(p_s_reg_45));
ap_CS_fsm_state1 <= ap_CS_fsm(0);
ap_CS_fsm_state2 <= ap_CS_fsm(1);
ap_CS_fsm_state3 <= ap_CS_fsm(2);
ap_CS_fsm_state4 <= ap_CS_fsm(3);
ap_done_assign_proc : process(ap_CS_fsm_state3, tmp_2_fu_66_p2)
begin
if (((tmp_2_fu_66_p2 = ap_const_lv1_1) and (ap_const_logic_1 = ap_CS_fsm_state3))) then
ap_done <= ap_const_logic_1;
else
ap_done <= ap_const_logic_0;
end if;
end process;
ap_idle_assign_proc : process(ap_start, ap_CS_fsm_state1)
begin
if (((ap_start = ap_const_logic_0) and (ap_const_logic_1 = ap_CS_fsm_state1))) then
ap_idle <= ap_const_logic_1;
else
ap_idle <= ap_const_logic_0;
end if;
end process;
ap_ready_assign_proc : process(ap_CS_fsm_state3, tmp_2_fu_66_p2)
begin
if (((tmp_2_fu_66_p2 = ap_const_lv1_1) and (ap_const_logic_1 = ap_CS_fsm_state3))) then
ap_ready <= ap_const_logic_1;
else
ap_ready <= ap_const_logic_0;
end if;
end process;
ap_rst_n_inv_assign_proc : process(ap_rst_n)
begin
ap_rst_n_inv <= not(ap_rst_n);
end process;
b_assign_1_fu_90_p3 <=
p_s_reg_45 when (tmp_3_reg_115(0) = '1') else
b_assign_reg_126;
b_assign_fu_84_p2 <= std_logic_vector(unsigned(p_s_reg_45) - unsigned(result_reg_56));
pResult_ap_vld_assign_proc : process(ap_CS_fsm_state3, tmp_2_fu_66_p2)
begin
if (((tmp_2_fu_66_p2 = ap_const_lv1_1) and (ap_const_logic_1 = ap_CS_fsm_state3))) then
pResult_ap_vld <= ap_const_logic_1;
else
pResult_ap_vld <= ap_const_logic_0;
end if;
end process;
tmp_2_fu_66_p2 <= "1" when (result_reg_56 = p_s_reg_45) else "0";
tmp_3_fu_72_p2 <= "1" when (signed(result_reg_56) > signed(p_s_reg_45)) else "0";
end behav;
| mit | 5b6cddfaac86ec2a53e5a8d9c8978243 | 0.558077 | 3.025289 | false | false | false | false |
natsutan/NPU | fpga_implement/npu8/npu8.srcs/sources_1/ip/mul16_16/synth/mul16_16.vhd | 1 | 5,672 | -- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:mult_gen:12.0
-- IP Revision: 12
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY mult_gen_v12_0_12;
USE mult_gen_v12_0_12.mult_gen_v12_0_12;
ENTITY mul16_16 IS
PORT (
CLK : IN STD_LOGIC;
A : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
B : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
P : OUT STD_LOGIC_VECTOR(15 DOWNTO 0)
);
END mul16_16;
ARCHITECTURE mul16_16_arch OF mul16_16 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF mul16_16_arch: ARCHITECTURE IS "yes";
COMPONENT mult_gen_v12_0_12 IS
GENERIC (
C_VERBOSITY : INTEGER;
C_MODEL_TYPE : INTEGER;
C_OPTIMIZE_GOAL : INTEGER;
C_XDEVICEFAMILY : STRING;
C_HAS_CE : INTEGER;
C_HAS_SCLR : INTEGER;
C_LATENCY : INTEGER;
C_A_WIDTH : INTEGER;
C_A_TYPE : INTEGER;
C_B_WIDTH : INTEGER;
C_B_TYPE : INTEGER;
C_OUT_HIGH : INTEGER;
C_OUT_LOW : INTEGER;
C_MULT_TYPE : INTEGER;
C_CE_OVERRIDES_SCLR : INTEGER;
C_CCM_IMP : INTEGER;
C_B_VALUE : STRING;
C_HAS_ZERO_DETECT : INTEGER;
C_ROUND_OUTPUT : INTEGER;
C_ROUND_PT : INTEGER
);
PORT (
CLK : IN STD_LOGIC;
A : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
B : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
CE : IN STD_LOGIC;
SCLR : IN STD_LOGIC;
P : OUT STD_LOGIC_VECTOR(15 DOWNTO 0)
);
END COMPONENT mult_gen_v12_0_12;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF mul16_16_arch: ARCHITECTURE IS "mult_gen_v12_0_12,Vivado 2016.4";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF mul16_16_arch : ARCHITECTURE IS "mul16_16,mult_gen_v12_0_12,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF mul16_16_arch: ARCHITECTURE IS "mul16_16,mult_gen_v12_0_12,{x_ipProduct=Vivado 2016.4,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=mult_gen,x_ipVersion=12.0,x_ipCoreRevision=12,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_VERBOSITY=0,C_MODEL_TYPE=0,C_OPTIMIZE_GOAL=1,C_XDEVICEFAMILY=kintexu,C_HAS_CE=0,C_HAS_SCLR=0,C_LATENCY=4,C_A_WIDTH=16,C_A_TYPE=1,C_B_WIDTH=16,C_B_TYPE=1,C_OUT_HIGH=31,C_OUT_LOW=16,C_MULT_TYPE=0,C_CE_OVERRIDES_SCLR=0,C_CCM_IMP=0,C_B_VALUE=10000001,C_HAS_ZERO_DETECT=0,C_ROUND_OUTPUT=0,C_ROUND_PT=0}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF CLK: SIGNAL IS "xilinx.com:signal:clock:1.0 clk_intf CLK";
ATTRIBUTE X_INTERFACE_INFO OF A: SIGNAL IS "xilinx.com:signal:data:1.0 a_intf DATA";
ATTRIBUTE X_INTERFACE_INFO OF B: SIGNAL IS "xilinx.com:signal:data:1.0 b_intf DATA";
ATTRIBUTE X_INTERFACE_INFO OF P: SIGNAL IS "xilinx.com:signal:data:1.0 p_intf DATA";
BEGIN
U0 : mult_gen_v12_0_12
GENERIC MAP (
C_VERBOSITY => 0,
C_MODEL_TYPE => 0,
C_OPTIMIZE_GOAL => 1,
C_XDEVICEFAMILY => "kintexu",
C_HAS_CE => 0,
C_HAS_SCLR => 0,
C_LATENCY => 4,
C_A_WIDTH => 16,
C_A_TYPE => 1,
C_B_WIDTH => 16,
C_B_TYPE => 1,
C_OUT_HIGH => 31,
C_OUT_LOW => 16,
C_MULT_TYPE => 0,
C_CE_OVERRIDES_SCLR => 0,
C_CCM_IMP => 0,
C_B_VALUE => "10000001",
C_HAS_ZERO_DETECT => 0,
C_ROUND_OUTPUT => 0,
C_ROUND_PT => 0
)
PORT MAP (
CLK => CLK,
A => A,
B => B,
CE => '1',
SCLR => '0',
P => P
);
END mul16_16_arch;
| bsd-3-clause | 2c99ba1d793cb477859c306bf2aad0aa | 0.679302 | 3.3582 | false | false | false | false |
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