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jairov4/accel-oil
solution_virtex5_plb/impl/vhdl/bitset_next.vhd
1
25,480
-- ============================================================== -- RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC -- Version: 2014.1 -- Copyright (C) 2014 Xilinx Inc. All rights reserved. -- -- =========================================================== library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; entity bitset_next is port ( ap_clk : IN STD_LOGIC; ap_rst : IN STD_LOGIC; ap_start : IN STD_LOGIC; ap_done : OUT STD_LOGIC; ap_idle : OUT STD_LOGIC; ap_ready : OUT STD_LOGIC; ap_ce : IN STD_LOGIC; p_read : IN STD_LOGIC_VECTOR (31 downto 0); r_bit : IN STD_LOGIC_VECTOR (7 downto 0); r_bucket_index : IN STD_LOGIC_VECTOR (7 downto 0); r_bucket : IN STD_LOGIC_VECTOR (31 downto 0); ap_return_0 : OUT STD_LOGIC_VECTOR (7 downto 0); ap_return_1 : OUT STD_LOGIC_VECTOR (7 downto 0); ap_return_2 : OUT STD_LOGIC_VECTOR (31 downto 0); ap_return_3 : OUT STD_LOGIC_VECTOR (0 downto 0) ); end; architecture behav of bitset_next is constant ap_const_logic_1 : STD_LOGIC := '1'; constant ap_const_logic_0 : STD_LOGIC := '0'; constant ap_ST_pp0_stg0_fsm_0 : STD_LOGIC_VECTOR (0 downto 0) := "0"; constant ap_const_lv1_0 : STD_LOGIC_VECTOR (0 downto 0) := "0"; constant ap_const_lv32_0 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000000"; constant ap_const_lv1_1 : STD_LOGIC_VECTOR (0 downto 0) := "1"; constant ap_const_lv2_1 : STD_LOGIC_VECTOR (1 downto 0) := "01"; constant ap_const_lv2_2 : STD_LOGIC_VECTOR (1 downto 0) := "10"; constant ap_const_lv32_FFFFFFFF : STD_LOGIC_VECTOR (31 downto 0) := "11111111111111111111111111111111"; constant ap_const_lv2_0 : STD_LOGIC_VECTOR (1 downto 0) := "00"; constant ap_const_lv32_1 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000001"; constant ap_const_lv8_1 : STD_LOGIC_VECTOR (7 downto 0) := "00000001"; constant ap_true : BOOLEAN := true; signal ap_CS_fsm : STD_LOGIC_VECTOR (0 downto 0) := "0"; signal ap_reg_ppiten_pp0_it0 : STD_LOGIC; signal ap_reg_ppiten_pp0_it1 : STD_LOGIC := '0'; signal ap_reg_ppiten_pp0_it2 : STD_LOGIC := '0'; signal grp_p_bsf32_hw_fu_118_ap_return : STD_LOGIC_VECTOR (4 downto 0); signal reg_123 : STD_LOGIC_VECTOR (4 downto 0); signal tmp_5_fu_143_p2 : STD_LOGIC_VECTOR (0 downto 0); signal tmp_9_1_fu_148_p2 : STD_LOGIC_VECTOR (0 downto 0); signal tmp_11_1_fu_153_p2 : STD_LOGIC_VECTOR (0 downto 0); signal r_bit_read_reg_196 : STD_LOGIC_VECTOR (7 downto 0); signal p_read_1_reg_202 : STD_LOGIC_VECTOR (31 downto 0); signal ap_reg_ppstg_p_read_1_reg_202_pp0_it1 : STD_LOGIC_VECTOR (31 downto 0); signal tmp_fu_127_p1 : STD_LOGIC_VECTOR (1 downto 0); signal tmp_reg_210 : STD_LOGIC_VECTOR (1 downto 0); signal ap_reg_ppstg_tmp_reg_210_pp0_it1 : STD_LOGIC_VECTOR (1 downto 0); signal bus_assign_fu_137_p2 : STD_LOGIC_VECTOR (31 downto 0); signal bus_assign_reg_216 : STD_LOGIC_VECTOR (31 downto 0); signal ap_reg_ppstg_bus_assign_reg_216_pp0_it1 : STD_LOGIC_VECTOR (31 downto 0); signal tmp_5_reg_223 : STD_LOGIC_VECTOR (0 downto 0); signal tmp_9_1_reg_227 : STD_LOGIC_VECTOR (0 downto 0); signal tmp_11_1_reg_231 : STD_LOGIC_VECTOR (0 downto 0); signal grp_p_bsf32_hw_fu_118_bus_r : STD_LOGIC_VECTOR (31 downto 0); signal ap_reg_phiprechg_agg_result_bucket_write_assign_reg_54pp0_it2 : STD_LOGIC_VECTOR (31 downto 0); signal agg_result_bucket_write_assign_phi_fu_58_p8 : STD_LOGIC_VECTOR (31 downto 0); signal ap_reg_phiprechg_agg_result_bucket_write_assign_reg_54pp0_it1 : STD_LOGIC_VECTOR (31 downto 0); signal ap_reg_phiprechg_agg_result_end_write_assign_reg_69pp0_it2 : STD_LOGIC_VECTOR (0 downto 0); signal agg_result_end_write_assign_phi_fu_73_p8 : STD_LOGIC_VECTOR (0 downto 0); signal ap_reg_phiprechg_agg_result_end_write_assign_reg_69pp0_it1 : STD_LOGIC_VECTOR (0 downto 0); signal ap_reg_phiprechg_agg_result_bucket_index_write_assign_reg_87pp0_it2 : STD_LOGIC_VECTOR (1 downto 0); signal agg_result_bucket_index_write_assign_phi_fu_91_p8 : STD_LOGIC_VECTOR (1 downto 0); signal ap_reg_phiprechg_agg_result_bucket_index_write_assign_reg_87pp0_it1 : STD_LOGIC_VECTOR (1 downto 0); signal agg_result_bit_write_assign_trunc3_ext_fu_163_p1 : STD_LOGIC_VECTOR (7 downto 0); signal ap_reg_phiprechg_agg_result_bit_write_assign_reg_104pp0_it2 : STD_LOGIC_VECTOR (7 downto 0); signal agg_result_bit_write_assign_phi_fu_107_p8 : STD_LOGIC_VECTOR (7 downto 0); signal agg_result_bit_write_assign_trunc_ext_fu_158_p1 : STD_LOGIC_VECTOR (7 downto 0); signal ap_reg_phiprechg_agg_result_bit_write_assign_reg_104pp0_it1 : STD_LOGIC_VECTOR (7 downto 0); signal tmp_3_fu_131_p2 : STD_LOGIC_VECTOR (31 downto 0); signal agg_result_bucket_index_write_assign_cast_fu_168_p1 : STD_LOGIC_VECTOR (7 downto 0); signal ap_NS_fsm : STD_LOGIC_VECTOR (0 downto 0); signal ap_sig_pprstidle_pp0 : STD_LOGIC; signal ap_sig_bdd_113 : BOOLEAN; signal ap_sig_bdd_104 : BOOLEAN; signal ap_sig_bdd_121 : BOOLEAN; signal ap_sig_bdd_125 : BOOLEAN; signal ap_sig_bdd_61 : BOOLEAN; signal ap_sig_bdd_73 : BOOLEAN; signal ap_sig_bdd_59 : BOOLEAN; component p_bsf32_hw IS port ( bus_r : IN STD_LOGIC_VECTOR (31 downto 0); ap_return : OUT STD_LOGIC_VECTOR (4 downto 0) ); end component; begin grp_p_bsf32_hw_fu_118 : component p_bsf32_hw port map ( bus_r => grp_p_bsf32_hw_fu_118_bus_r, ap_return => grp_p_bsf32_hw_fu_118_ap_return); -- the current state (ap_CS_fsm) of the state machine. -- ap_CS_fsm_assign_proc : process(ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (ap_rst = '1') then ap_CS_fsm <= ap_ST_pp0_stg0_fsm_0; else ap_CS_fsm <= ap_NS_fsm; end if; end if; end process; -- ap_reg_ppiten_pp0_it1 assign process. -- ap_reg_ppiten_pp0_it1_assign_proc : process(ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (ap_rst = '1') then ap_reg_ppiten_pp0_it1 <= ap_const_logic_0; else if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or not((ap_const_logic_1 = ap_ce)))))) then ap_reg_ppiten_pp0_it1 <= ap_reg_ppiten_pp0_it0; end if; end if; end if; end process; -- ap_reg_ppiten_pp0_it2 assign process. -- ap_reg_ppiten_pp0_it2_assign_proc : process(ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (ap_rst = '1') then ap_reg_ppiten_pp0_it2 <= ap_const_logic_0; else if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or not((ap_const_logic_1 = ap_ce)))))) then ap_reg_ppiten_pp0_it2 <= ap_reg_ppiten_pp0_it1; end if; end if; end if; end process; -- ap_reg_phiprechg_agg_result_bit_write_assign_reg_104pp0_it2 assign process. -- ap_reg_phiprechg_agg_result_bit_write_assign_reg_104pp0_it2_assign_proc : process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if ((((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and not(((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0))) and (ap_const_logic_1 = ap_ce) and not((tmp_5_fu_143_p2 = ap_const_lv1_0)) and (ap_const_lv1_0 = tmp_9_1_fu_148_p2)) or ((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and not(((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0))) and (ap_const_logic_1 = ap_ce) and not((tmp_5_fu_143_p2 = ap_const_lv1_0)) and not((ap_const_lv1_0 = tmp_9_1_fu_148_p2)) and not((ap_const_lv1_0 = tmp_11_1_fu_153_p2))))) then ap_reg_phiprechg_agg_result_bit_write_assign_reg_104pp0_it2 <= r_bit_read_reg_196; elsif (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and not(((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0))) and (ap_const_logic_1 = ap_ce))) then ap_reg_phiprechg_agg_result_bit_write_assign_reg_104pp0_it2 <= ap_reg_phiprechg_agg_result_bit_write_assign_reg_104pp0_it1; end if; end if; end process; -- ap_reg_phiprechg_agg_result_bucket_index_write_assign_reg_87pp0_it2 assign process. -- ap_reg_phiprechg_agg_result_bucket_index_write_assign_reg_87pp0_it2_assign_proc : process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if ((((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and not(((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0))) and (ap_const_logic_1 = ap_ce) and not((tmp_5_fu_143_p2 = ap_const_lv1_0)) and (ap_const_lv1_0 = tmp_9_1_fu_148_p2)) or ((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and not(((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0))) and (ap_const_logic_1 = ap_ce) and not((tmp_5_fu_143_p2 = ap_const_lv1_0)) and not((ap_const_lv1_0 = tmp_9_1_fu_148_p2)) and not((ap_const_lv1_0 = tmp_11_1_fu_153_p2))))) then ap_reg_phiprechg_agg_result_bucket_index_write_assign_reg_87pp0_it2 <= ap_const_lv2_2; elsif (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and not(((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0))) and (ap_const_logic_1 = ap_ce))) then ap_reg_phiprechg_agg_result_bucket_index_write_assign_reg_87pp0_it2 <= ap_reg_phiprechg_agg_result_bucket_index_write_assign_reg_87pp0_it1; end if; end if; end process; -- ap_reg_phiprechg_agg_result_bucket_write_assign_reg_54pp0_it2 assign process. -- ap_reg_phiprechg_agg_result_bucket_write_assign_reg_54pp0_it2_assign_proc : process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (ap_sig_bdd_61) then if (ap_sig_bdd_125) then ap_reg_phiprechg_agg_result_bucket_write_assign_reg_54pp0_it2 <= p_read_1_reg_202; elsif (ap_sig_bdd_121) then ap_reg_phiprechg_agg_result_bucket_write_assign_reg_54pp0_it2 <= ap_const_lv32_0; elsif ((ap_true = ap_true)) then ap_reg_phiprechg_agg_result_bucket_write_assign_reg_54pp0_it2 <= ap_reg_phiprechg_agg_result_bucket_write_assign_reg_54pp0_it1; end if; end if; end if; end process; -- ap_reg_phiprechg_agg_result_end_write_assign_reg_69pp0_it2 assign process. -- ap_reg_phiprechg_agg_result_end_write_assign_reg_69pp0_it2_assign_proc : process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then end if; end process; -- assign process. -- process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and not(((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0))) and (ap_const_logic_1 = ap_ce))) then ap_reg_ppstg_bus_assign_reg_216_pp0_it1 <= bus_assign_reg_216; ap_reg_ppstg_p_read_1_reg_202_pp0_it1 <= p_read_1_reg_202; ap_reg_ppstg_tmp_reg_210_pp0_it1 <= tmp_reg_210; end if; end if; end process; -- assign process. -- process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and not(((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0))) and (ap_const_logic_1 = ap_ce))) then bus_assign_reg_216 <= bus_assign_fu_137_p2; p_read_1_reg_202 <= p_read; r_bit_read_reg_196 <= r_bit; tmp_reg_210 <= tmp_fu_127_p1; end if; end if; end process; -- assign process. -- process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if ((((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and not(((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0))) and (ap_const_logic_1 = ap_ce) and (tmp_5_fu_143_p2 = ap_const_lv1_0)) or ((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and not(((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0))) and (ap_const_logic_1 = ap_ce) and not((tmp_5_fu_143_p2 = ap_const_lv1_0)) and not((ap_const_lv1_0 = tmp_9_1_fu_148_p2)) and (ap_const_lv1_0 = tmp_11_1_fu_153_p2)))) then reg_123 <= grp_p_bsf32_hw_fu_118_ap_return; end if; end if; end process; -- assign process. -- process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and not(((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0))) and (ap_const_logic_1 = ap_ce) and not((tmp_5_fu_143_p2 = ap_const_lv1_0)) and not((ap_const_lv1_0 = tmp_9_1_fu_148_p2)))) then tmp_11_1_reg_231 <= tmp_11_1_fu_153_p2; end if; end if; end process; -- assign process. -- process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and not(((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0))) and (ap_const_logic_1 = ap_ce))) then tmp_5_reg_223 <= tmp_5_fu_143_p2; end if; end if; end process; -- assign process. -- process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and not(((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0))) and (ap_const_logic_1 = ap_ce) and not((tmp_5_fu_143_p2 = ap_const_lv1_0)))) then tmp_9_1_reg_227 <= tmp_9_1_fu_148_p2; end if; end if; end process; ap_reg_phiprechg_agg_result_end_write_assign_reg_69pp0_it2(0) <= '1'; -- the next state (ap_NS_fsm) of the state machine. -- ap_NS_fsm_assign_proc : process (ap_start , ap_CS_fsm , ap_reg_ppiten_pp0_it0 , ap_ce , ap_sig_pprstidle_pp0) begin case ap_CS_fsm is when ap_ST_pp0_stg0_fsm_0 => ap_NS_fsm <= ap_ST_pp0_stg0_fsm_0; when others => ap_NS_fsm <= "X"; end case; end process; -- agg_result_bit_write_assign_phi_fu_107_p8 assign process. -- agg_result_bit_write_assign_phi_fu_107_p8_assign_proc : process(tmp_5_reg_223, agg_result_bit_write_assign_trunc3_ext_fu_163_p1, ap_reg_phiprechg_agg_result_bit_write_assign_reg_104pp0_it2, agg_result_bit_write_assign_trunc_ext_fu_158_p1, ap_sig_bdd_113, ap_sig_bdd_104) begin if (ap_sig_bdd_104) then if ((ap_const_lv1_0 = tmp_5_reg_223)) then agg_result_bit_write_assign_phi_fu_107_p8 <= agg_result_bit_write_assign_trunc_ext_fu_158_p1; elsif (ap_sig_bdd_113) then agg_result_bit_write_assign_phi_fu_107_p8 <= agg_result_bit_write_assign_trunc3_ext_fu_163_p1; else agg_result_bit_write_assign_phi_fu_107_p8 <= ap_reg_phiprechg_agg_result_bit_write_assign_reg_104pp0_it2; end if; else agg_result_bit_write_assign_phi_fu_107_p8 <= ap_reg_phiprechg_agg_result_bit_write_assign_reg_104pp0_it2; end if; end process; agg_result_bit_write_assign_trunc3_ext_fu_163_p1 <= std_logic_vector(resize(unsigned(reg_123),8)); agg_result_bit_write_assign_trunc_ext_fu_158_p1 <= std_logic_vector(resize(unsigned(reg_123),8)); agg_result_bucket_index_write_assign_cast_fu_168_p1 <= std_logic_vector(resize(unsigned(agg_result_bucket_index_write_assign_phi_fu_91_p8),8)); -- agg_result_bucket_index_write_assign_phi_fu_91_p8 assign process. -- agg_result_bucket_index_write_assign_phi_fu_91_p8_assign_proc : process(ap_reg_ppstg_tmp_reg_210_pp0_it1, tmp_5_reg_223, ap_reg_phiprechg_agg_result_bucket_index_write_assign_reg_87pp0_it2, ap_sig_bdd_113, ap_sig_bdd_104) begin if (ap_sig_bdd_104) then if ((ap_const_lv1_0 = tmp_5_reg_223)) then agg_result_bucket_index_write_assign_phi_fu_91_p8 <= ap_reg_ppstg_tmp_reg_210_pp0_it1; elsif (ap_sig_bdd_113) then agg_result_bucket_index_write_assign_phi_fu_91_p8 <= ap_const_lv2_1; else agg_result_bucket_index_write_assign_phi_fu_91_p8 <= ap_reg_phiprechg_agg_result_bucket_index_write_assign_reg_87pp0_it2; end if; else agg_result_bucket_index_write_assign_phi_fu_91_p8 <= ap_reg_phiprechg_agg_result_bucket_index_write_assign_reg_87pp0_it2; end if; end process; -- agg_result_bucket_write_assign_phi_fu_58_p8 assign process. -- agg_result_bucket_write_assign_phi_fu_58_p8_assign_proc : process(ap_reg_ppstg_p_read_1_reg_202_pp0_it1, ap_reg_ppstg_bus_assign_reg_216_pp0_it1, tmp_5_reg_223, ap_reg_phiprechg_agg_result_bucket_write_assign_reg_54pp0_it2, ap_sig_bdd_113, ap_sig_bdd_104) begin if (ap_sig_bdd_104) then if ((ap_const_lv1_0 = tmp_5_reg_223)) then agg_result_bucket_write_assign_phi_fu_58_p8 <= ap_reg_ppstg_bus_assign_reg_216_pp0_it1; elsif (ap_sig_bdd_113) then agg_result_bucket_write_assign_phi_fu_58_p8 <= ap_reg_ppstg_p_read_1_reg_202_pp0_it1; else agg_result_bucket_write_assign_phi_fu_58_p8 <= ap_reg_phiprechg_agg_result_bucket_write_assign_reg_54pp0_it2; end if; else agg_result_bucket_write_assign_phi_fu_58_p8 <= ap_reg_phiprechg_agg_result_bucket_write_assign_reg_54pp0_it2; end if; end process; -- agg_result_end_write_assign_phi_fu_73_p8 assign process. -- agg_result_end_write_assign_phi_fu_73_p8_assign_proc : process(ap_CS_fsm, ap_reg_ppiten_pp0_it2, tmp_5_reg_223, tmp_9_1_reg_227, tmp_11_1_reg_231, ap_reg_phiprechg_agg_result_end_write_assign_reg_69pp0_it2) begin if ((((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2) and not((ap_const_lv1_0 = tmp_5_reg_223)) and not((ap_const_lv1_0 = tmp_9_1_reg_227)) and (ap_const_lv1_0 = tmp_11_1_reg_231)) or ((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2) and (ap_const_lv1_0 = tmp_5_reg_223)))) then agg_result_end_write_assign_phi_fu_73_p8 <= ap_const_lv1_0; else agg_result_end_write_assign_phi_fu_73_p8 <= ap_reg_phiprechg_agg_result_end_write_assign_reg_69pp0_it2; end if; end process; -- ap_done assign process. -- ap_done_assign_proc : process(ap_start, ap_CS_fsm, ap_reg_ppiten_pp0_it0, ap_reg_ppiten_pp0_it2, ap_ce) begin if (((not((ap_const_logic_1 = ap_start)) and (ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it0)) or ((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2) and not(((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0))) and (ap_const_logic_1 = ap_ce)))) then ap_done <= ap_const_logic_1; else ap_done <= ap_const_logic_0; end if; end process; -- ap_idle assign process. -- ap_idle_assign_proc : process(ap_start, ap_CS_fsm, ap_reg_ppiten_pp0_it0, ap_reg_ppiten_pp0_it1, ap_reg_ppiten_pp0_it2) begin if ((not((ap_const_logic_1 = ap_start)) and (ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it0) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it1) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it2))) then ap_idle <= ap_const_logic_1; else ap_idle <= ap_const_logic_0; end if; end process; -- ap_ready assign process. -- ap_ready_assign_proc : process(ap_start, ap_CS_fsm, ap_reg_ppiten_pp0_it0, ap_ce) begin if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and not(((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0))) and (ap_const_logic_1 = ap_ce))) then ap_ready <= ap_const_logic_1; else ap_ready <= ap_const_logic_0; end if; end process; ap_reg_phiprechg_agg_result_bit_write_assign_reg_104pp0_it1 <= ap_const_lv8_1; ap_reg_phiprechg_agg_result_bucket_index_write_assign_reg_87pp0_it1 <= ap_const_lv2_1; ap_reg_phiprechg_agg_result_bucket_write_assign_reg_54pp0_it1 <= ap_const_lv32_1; ap_reg_phiprechg_agg_result_end_write_assign_reg_69pp0_it1 <= ap_const_lv1_1; ap_reg_ppiten_pp0_it0 <= ap_start; ap_return_0 <= agg_result_bit_write_assign_phi_fu_107_p8; ap_return_1 <= agg_result_bucket_index_write_assign_cast_fu_168_p1; ap_return_2 <= agg_result_bucket_write_assign_phi_fu_58_p8; ap_return_3 <= agg_result_end_write_assign_phi_fu_73_p8; -- ap_sig_bdd_104 assign process. -- ap_sig_bdd_104_assign_proc : process(ap_CS_fsm, ap_reg_ppiten_pp0_it2) begin ap_sig_bdd_104 <= ((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2)); end process; -- ap_sig_bdd_113 assign process. -- ap_sig_bdd_113_assign_proc : process(tmp_5_reg_223, tmp_9_1_reg_227, tmp_11_1_reg_231) begin ap_sig_bdd_113 <= (not((ap_const_lv1_0 = tmp_5_reg_223)) and not((ap_const_lv1_0 = tmp_9_1_reg_227)) and (ap_const_lv1_0 = tmp_11_1_reg_231)); end process; -- ap_sig_bdd_121 assign process. -- ap_sig_bdd_121_assign_proc : process(tmp_5_fu_143_p2, tmp_9_1_fu_148_p2) begin ap_sig_bdd_121 <= (not((tmp_5_fu_143_p2 = ap_const_lv1_0)) and (ap_const_lv1_0 = tmp_9_1_fu_148_p2)); end process; -- ap_sig_bdd_125 assign process. -- ap_sig_bdd_125_assign_proc : process(tmp_5_fu_143_p2, tmp_9_1_fu_148_p2, tmp_11_1_fu_153_p2) begin ap_sig_bdd_125 <= (not((tmp_5_fu_143_p2 = ap_const_lv1_0)) and not((ap_const_lv1_0 = tmp_9_1_fu_148_p2)) and not((ap_const_lv1_0 = tmp_11_1_fu_153_p2))); end process; -- ap_sig_bdd_59 assign process. -- ap_sig_bdd_59_assign_proc : process(ap_CS_fsm, ap_reg_ppiten_pp0_it1) begin ap_sig_bdd_59 <= ((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)); end process; -- ap_sig_bdd_61 assign process. -- ap_sig_bdd_61_assign_proc : process(ap_start, ap_CS_fsm, ap_reg_ppiten_pp0_it0, ap_reg_ppiten_pp0_it1, ap_ce) begin ap_sig_bdd_61 <= ((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and not(((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0))) and (ap_const_logic_1 = ap_ce)); end process; -- ap_sig_bdd_73 assign process. -- ap_sig_bdd_73_assign_proc : process(tmp_5_fu_143_p2, tmp_9_1_fu_148_p2, tmp_11_1_fu_153_p2) begin ap_sig_bdd_73 <= (not((tmp_5_fu_143_p2 = ap_const_lv1_0)) and not((ap_const_lv1_0 = tmp_9_1_fu_148_p2)) and (ap_const_lv1_0 = tmp_11_1_fu_153_p2)); end process; -- ap_sig_pprstidle_pp0 assign process. -- ap_sig_pprstidle_pp0_assign_proc : process(ap_start, ap_reg_ppiten_pp0_it0, ap_reg_ppiten_pp0_it1) begin if (((ap_const_logic_0 = ap_reg_ppiten_pp0_it0) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it1) and (ap_const_logic_0 = ap_start))) then ap_sig_pprstidle_pp0 <= ap_const_logic_1; else ap_sig_pprstidle_pp0 <= ap_const_logic_0; end if; end process; bus_assign_fu_137_p2 <= (tmp_3_fu_131_p2 and r_bucket); -- grp_p_bsf32_hw_fu_118_bus_r assign process. -- grp_p_bsf32_hw_fu_118_bus_r_assign_proc : process(tmp_5_fu_143_p2, p_read_1_reg_202, bus_assign_reg_216, ap_sig_bdd_73, ap_sig_bdd_59) begin if (ap_sig_bdd_59) then if (ap_sig_bdd_73) then grp_p_bsf32_hw_fu_118_bus_r <= p_read_1_reg_202; elsif ((tmp_5_fu_143_p2 = ap_const_lv1_0)) then grp_p_bsf32_hw_fu_118_bus_r <= bus_assign_reg_216; else grp_p_bsf32_hw_fu_118_bus_r <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX"; end if; else grp_p_bsf32_hw_fu_118_bus_r <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX"; end if; end process; tmp_11_1_fu_153_p2 <= "1" when (p_read_1_reg_202 = ap_const_lv32_0) else "0"; tmp_3_fu_131_p2 <= std_logic_vector(unsigned(r_bucket) + unsigned(ap_const_lv32_FFFFFFFF)); tmp_5_fu_143_p2 <= "1" when (bus_assign_reg_216 = ap_const_lv32_0) else "0"; tmp_9_1_fu_148_p2 <= "1" when (tmp_reg_210 = ap_const_lv2_0) else "0"; tmp_fu_127_p1 <= r_bucket_index(2 - 1 downto 0); end behav;
lgpl-3.0
e7ca21e2c35b460444add516ba65bf78
0.612245
2.618167
false
false
false
false
grwlf/vsim
vhdl_ct/ct00382.vhd
1
102,226
-- NEED RESULT: ARCH00382.P1: Multi inertial transactions occurred on concurrent signal asg passed -- NEED RESULT: ARCH00382.P2: Multi inertial transactions occurred on concurrent signal asg passed -- NEED RESULT: ARCH00382.P3: Multi inertial transactions occurred on concurrent signal asg passed -- NEED RESULT: ARCH00382.P4: Multi inertial transactions occurred on concurrent signal asg passed -- NEED RESULT: ARCH00382.P5: Multi inertial transactions occurred on concurrent signal asg passed -- NEED RESULT: ARCH00382.P6: Multi inertial transactions occurred on concurrent signal asg passed -- NEED RESULT: ARCH00382.P7: Multi inertial transactions occurred on concurrent signal asg passed -- NEED RESULT: ARCH00382.P8: Multi inertial transactions occurred on concurrent signal asg passed -- NEED RESULT: ARCH00382.P9: Multi inertial transactions occurred on concurrent signal asg passed -- NEED RESULT: ARCH00382.P10: Multi inertial transactions occurred on concurrent signal asg passed -- NEED RESULT: ARCH00382.P11: Multi inertial transactions occurred on concurrent signal asg passed -- NEED RESULT: ARCH00382.P12: Multi inertial transactions occurred on concurrent signal asg passed -- NEED RESULT: ARCH00382.P13: Multi inertial transactions occurred on concurrent signal asg passed -- NEED RESULT: ARCH00382.P14: Multi inertial transactions occurred on concurrent signal asg passed -- NEED RESULT: ARCH00382.P15: Multi inertial transactions occurred on concurrent signal asg passed -- NEED RESULT: ARCH00382.P16: Multi inertial transactions occurred on concurrent signal asg passed -- NEED RESULT: ARCH00382.P17: Multi inertial transactions occurred on concurrent signal asg passed -- NEED RESULT: ARCH00382: One inertial transaction occurred on a concurrent signal asg passed -- NEED RESULT: ARCH00382: One inertial transaction occurred on a concurrent signal asg passed -- NEED RESULT: ARCH00382: One inertial transaction occurred on a concurrent signal asg passed -- NEED RESULT: ARCH00382: One inertial transaction occurred on a concurrent signal asg passed -- NEED RESULT: ARCH00382: One inertial transaction occurred on a concurrent signal asg passed -- NEED RESULT: ARCH00382: One inertial transaction occurred on a concurrent signal asg passed -- NEED RESULT: ARCH00382: One inertial transaction occurred on a concurrent signal asg passed -- NEED RESULT: ARCH00382: One inertial transaction occurred on a concurrent signal asg passed -- NEED RESULT: ARCH00382: One inertial transaction occurred on a concurrent signal asg passed -- NEED RESULT: ARCH00382: One inertial transaction occurred on a concurrent signal asg passed -- NEED RESULT: ARCH00382: One inertial transaction occurred on a concurrent signal asg passed -- NEED RESULT: ARCH00382: One inertial transaction occurred on a concurrent signal asg passed -- NEED RESULT: ARCH00382: One inertial transaction occurred on a concurrent signal asg passed -- NEED RESULT: ARCH00382: One inertial transaction occurred on a concurrent signal asg passed -- NEED RESULT: ARCH00382: One inertial transaction occurred on a concurrent signal asg passed -- NEED RESULT: ARCH00382: One inertial transaction occurred on a concurrent signal asg passed -- NEED RESULT: ARCH00382: One inertial transaction occurred on a concurrent signal asg passed -- NEED RESULT: ARCH00382: Old transactions were removed on a concurrent signal asg passed -- NEED RESULT: ARCH00382: Old transactions were removed on a concurrent signal asg passed -- NEED RESULT: ARCH00382: Old transactions were removed on a concurrent signal asg passed -- NEED RESULT: ARCH00382: Old transactions were removed on a concurrent signal asg passed -- NEED RESULT: ARCH00382: Old transactions were removed on a concurrent signal asg passed -- NEED RESULT: ARCH00382: Old transactions were removed on a concurrent signal asg passed -- NEED RESULT: ARCH00382: Old transactions were removed on a concurrent signal asg passed -- NEED RESULT: ARCH00382: Old transactions were removed on a concurrent signal asg passed -- NEED RESULT: ARCH00382: Old transactions were removed on a concurrent signal asg passed -- NEED RESULT: ARCH00382: Old transactions were removed on a concurrent signal asg passed -- NEED RESULT: ARCH00382: Old transactions were removed on a concurrent signal asg passed -- NEED RESULT: ARCH00382: Old transactions were removed on a concurrent signal asg passed -- NEED RESULT: ARCH00382: Old transactions were removed on a concurrent signal asg passed -- NEED RESULT: ARCH00382: Old transactions were removed on a concurrent signal asg passed -- NEED RESULT: ARCH00382: Old transactions were removed on a concurrent signal asg passed -- NEED RESULT: ARCH00382: Old transactions were removed on a concurrent signal asg passed -- NEED RESULT: ARCH00382: Old transactions were removed on a concurrent signal asg passed -- NEED RESULT: ARCH00382: One inertial transaction occurred on a concurrent signal asg passed -- NEED RESULT: ARCH00382: One inertial transaction occurred on a concurrent signal asg passed -- NEED RESULT: ARCH00382: One inertial transaction occurred on a concurrent signal asg passed -- NEED RESULT: ARCH00382: One inertial transaction occurred on a concurrent signal asg passed -- NEED RESULT: ARCH00382: One inertial transaction occurred on a concurrent signal asg passed -- NEED RESULT: ARCH00382: One inertial transaction occurred on a concurrent signal asg passed -- NEED RESULT: ARCH00382: One inertial transaction occurred on a concurrent signal asg passed -- NEED RESULT: ARCH00382: One inertial transaction occurred on a concurrent signal asg passed -- NEED RESULT: ARCH00382: One inertial transaction occurred on a concurrent signal asg passed -- NEED RESULT: ARCH00382: One inertial transaction occurred on a concurrent signal asg passed -- NEED RESULT: ARCH00382: One inertial transaction occurred on a concurrent signal asg passed -- NEED RESULT: ARCH00382: One inertial transaction occurred on a concurrent signal asg passed -- NEED RESULT: ARCH00382: One inertial transaction occurred on a concurrent signal asg passed -- NEED RESULT: ARCH00382: One inertial transaction occurred on a concurrent signal asg passed -- NEED RESULT: ARCH00382: One inertial transaction occurred on a concurrent signal asg passed -- NEED RESULT: ARCH00382: One inertial transaction occurred on a concurrent signal asg passed -- NEED RESULT: ARCH00382: One inertial transaction occurred on a concurrent signal asg passed -- NEED RESULT: ARCH00382: Inertial semantics check on a concurrent signal asg passed -- NEED RESULT: ARCH00382: Inertial semantics check on a concurrent signal asg passed -- NEED RESULT: ARCH00382: Inertial semantics check on a concurrent signal asg passed -- NEED RESULT: ARCH00382: Inertial semantics check on a concurrent signal asg passed -- NEED RESULT: ARCH00382: Inertial semantics check on a concurrent signal asg passed -- NEED RESULT: ARCH00382: Inertial semantics check on a concurrent signal asg passed -- NEED RESULT: ARCH00382: Inertial semantics check on a concurrent signal asg passed -- NEED RESULT: ARCH00382: Inertial semantics check on a concurrent signal asg passed -- NEED RESULT: ARCH00382: Inertial semantics check on a concurrent signal asg passed -- NEED RESULT: ARCH00382: Inertial semantics check on a concurrent signal asg passed -- NEED RESULT: ARCH00382: Inertial semantics check on a concurrent signal asg passed -- NEED RESULT: ARCH00382: Inertial semantics check on a concurrent signal asg passed -- NEED RESULT: ARCH00382: Inertial semantics check on a concurrent signal asg passed -- NEED RESULT: ARCH00382: Inertial semantics check on a concurrent signal asg passed -- NEED RESULT: ARCH00382: Inertial semantics check on a concurrent signal asg passed -- NEED RESULT: ARCH00382: Inertial semantics check on a concurrent signal asg passed -- NEED RESULT: ARCH00382: Inertial semantics check on a concurrent signal asg passed -- NEED RESULT: P17: Inertial transactions completed entirely passed -- NEED RESULT: P16: Inertial transactions completed entirely passed -- NEED RESULT: P15: Inertial transactions completed entirely passed -- NEED RESULT: P14: Inertial transactions completed entirely passed -- NEED RESULT: P13: Inertial transactions completed entirely passed -- NEED RESULT: P12: Inertial transactions completed entirely passed -- NEED RESULT: P11: Inertial transactions completed entirely passed -- NEED RESULT: P10: Inertial transactions completed entirely passed -- NEED RESULT: P9: Inertial transactions completed entirely passed -- NEED RESULT: P8: Inertial transactions completed entirely passed -- NEED RESULT: P7: Inertial transactions completed entirely passed -- NEED RESULT: P6: Inertial transactions completed entirely passed -- NEED RESULT: P5: Inertial transactions completed entirely passed -- NEED RESULT: P4: Inertial transactions completed entirely passed -- NEED RESULT: P3: Inertial transactions completed entirely passed -- NEED RESULT: P2: Inertial transactions completed entirely passed -- NEED RESULT: P1: Inertial transactions completed entirely passed ------------------------------------------------------------------------------- -- -- Copyright (c) 1989 by Intermetrics, Inc. -- All rights reserved. -- ------------------------------------------------------------------------------- -- -- TEST NAME: -- -- CT00382 -- -- AUTHOR: -- -- G. Tominovich -- -- TEST OBJECTIVES: -- -- 9.5 (3) -- 9.5.1 (1) -- 9.5.1 (2) -- -- DESIGN UNIT ORDERING: -- -- ENT00382(ARCH00382) -- ENT00382_Test_Bench(ARCH00382_Test_Bench) -- -- REVISION HISTORY: -- -- 30-JUL-1987 - initial revision -- -- NOTES: -- -- self-checking -- automatically generated -- use WORK.STANDARD_TYPES.all ; entity ENT00382 is end ENT00382 ; -- -- architecture ARCH00382 of ENT00382 is subtype chk_sig_type is integer range -1 to 100 ; signal chk_boolean : chk_sig_type := -1 ; signal chk_bit : chk_sig_type := -1 ; signal chk_severity_level : chk_sig_type := -1 ; signal chk_character : chk_sig_type := -1 ; signal chk_st_enum1 : chk_sig_type := -1 ; signal chk_integer : chk_sig_type := -1 ; signal chk_st_int1 : chk_sig_type := -1 ; signal chk_time : chk_sig_type := -1 ; signal chk_st_phys1 : chk_sig_type := -1 ; signal chk_real : chk_sig_type := -1 ; signal chk_st_real1 : chk_sig_type := -1 ; signal chk_st_rec1 : chk_sig_type := -1 ; signal chk_st_rec2 : chk_sig_type := -1 ; signal chk_st_rec3 : chk_sig_type := -1 ; signal chk_st_arr1 : chk_sig_type := -1 ; signal chk_st_arr2 : chk_sig_type := -1 ; signal chk_st_arr3 : chk_sig_type := -1 ; -- subtype chk_time_type is Time ; signal s_boolean_savt : chk_time_type := 0 ns ; signal s_bit_savt : chk_time_type := 0 ns ; signal s_severity_level_savt : chk_time_type := 0 ns ; signal s_character_savt : chk_time_type := 0 ns ; signal s_st_enum1_savt : chk_time_type := 0 ns ; signal s_integer_savt : chk_time_type := 0 ns ; signal s_st_int1_savt : chk_time_type := 0 ns ; signal s_time_savt : chk_time_type := 0 ns ; signal s_st_phys1_savt : chk_time_type := 0 ns ; signal s_real_savt : chk_time_type := 0 ns ; signal s_st_real1_savt : chk_time_type := 0 ns ; signal s_st_rec1_savt : chk_time_type := 0 ns ; signal s_st_rec2_savt : chk_time_type := 0 ns ; signal s_st_rec3_savt : chk_time_type := 0 ns ; signal s_st_arr1_savt : chk_time_type := 0 ns ; signal s_st_arr2_savt : chk_time_type := 0 ns ; signal s_st_arr3_savt : chk_time_type := 0 ns ; -- subtype chk_cnt_type is Integer ; signal s_boolean_cnt : chk_cnt_type := 0 ; signal s_bit_cnt : chk_cnt_type := 0 ; signal s_severity_level_cnt : chk_cnt_type := 0 ; signal s_character_cnt : chk_cnt_type := 0 ; signal s_st_enum1_cnt : chk_cnt_type := 0 ; signal s_integer_cnt : chk_cnt_type := 0 ; signal s_st_int1_cnt : chk_cnt_type := 0 ; signal s_time_cnt : chk_cnt_type := 0 ; signal s_st_phys1_cnt : chk_cnt_type := 0 ; signal s_real_cnt : chk_cnt_type := 0 ; signal s_st_real1_cnt : chk_cnt_type := 0 ; signal s_st_rec1_cnt : chk_cnt_type := 0 ; signal s_st_rec2_cnt : chk_cnt_type := 0 ; signal s_st_rec3_cnt : chk_cnt_type := 0 ; signal s_st_arr1_cnt : chk_cnt_type := 0 ; signal s_st_arr2_cnt : chk_cnt_type := 0 ; signal s_st_arr3_cnt : chk_cnt_type := 0 ; -- type select_type is range 1 to 6 ; signal boolean_select : select_type := 1 ; signal bit_select : select_type := 1 ; signal severity_level_select : select_type := 1 ; signal character_select : select_type := 1 ; signal st_enum1_select : select_type := 1 ; signal integer_select : select_type := 1 ; signal st_int1_select : select_type := 1 ; signal time_select : select_type := 1 ; signal st_phys1_select : select_type := 1 ; signal real_select : select_type := 1 ; signal st_real1_select : select_type := 1 ; signal st_rec1_select : select_type := 1 ; signal st_rec2_select : select_type := 1 ; signal st_rec3_select : select_type := 1 ; signal st_arr1_select : select_type := 1 ; signal st_arr2_select : select_type := 1 ; signal st_arr3_select : select_type := 1 ; -- signal s_boolean : boolean := c_boolean_1 ; signal s_bit : bit := c_bit_1 ; signal s_severity_level : severity_level := c_severity_level_1 ; signal s_character : character := c_character_1 ; signal s_st_enum1 : st_enum1 := c_st_enum1_1 ; signal s_integer : integer := c_integer_1 ; signal s_st_int1 : st_int1 := c_st_int1_1 ; signal s_time : time := c_time_1 ; signal s_st_phys1 : st_phys1 := c_st_phys1_1 ; signal s_real : real := c_real_1 ; signal s_st_real1 : st_real1 := c_st_real1_1 ; signal s_st_rec1 : st_rec1 := c_st_rec1_1 ; signal s_st_rec2 : st_rec2 := c_st_rec2_1 ; signal s_st_rec3 : st_rec3 := c_st_rec3_1 ; signal s_st_arr1 : st_arr1 := c_st_arr1_1 ; signal s_st_arr2 : st_arr2 := c_st_arr2_1 ; signal s_st_arr3 : st_arr3 := c_st_arr3_1 ; -- begin CHG1 : process variable correct : boolean ; begin case s_boolean_cnt is when 0 => null ; -- s_boolean <= -- c_boolean_2 after 10 ns, -- c_boolean_1 after 20 ns ; -- when 1 => correct := s_boolean = c_boolean_2 and (s_boolean_savt + 10 ns) = Std.Standard.Now ; -- when 2 => correct := correct and s_boolean = c_boolean_1 and (s_boolean_savt + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00382.P1" , "Multi inertial transactions occurred on " & "concurrent signal asg", correct ) ; -- boolean_select <= transport 2 ; -- s_boolean <= -- c_boolean_2 after 10 ns , -- c_boolean_1 after 20 ns , -- c_boolean_2 after 30 ns , -- c_boolean_1 after 40 ns ; -- when 3 => correct := s_boolean = c_boolean_2 and (s_boolean_savt + 10 ns) = Std.Standard.Now ; boolean_select <= transport 3 ; -- s_boolean <= -- c_boolean_1 after 5 ns ; -- when 4 => correct := correct and s_boolean = c_boolean_1 and (s_boolean_savt + 5 ns) = Std.Standard.Now ; test_report ( "ARCH00382" , "One inertial transaction occurred on a " & "concurrent signal asg", correct ) ; boolean_select <= transport 4 ; -- s_boolean <= -- c_boolean_1 after 100 ns ; -- when 5 => correct := correct and s_boolean = c_boolean_1 and (s_boolean_savt + 100 ns) = Std.Standard.Now ; test_report ( "ARCH00382" , "Old transactions were removed on a " & "concurrent signal asg", correct ) ; boolean_select <= transport 5 ; -- s_boolean <= -- c_boolean_2 after 10 ns , -- c_boolean_1 after 20 ns , -- c_boolean_2 after 30 ns , -- c_boolean_1 after 40 ns ; -- when 6 => correct := correct and s_boolean = c_boolean_2 and (s_boolean_savt + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00382" , "One inertial transaction occurred on a " & "concurrent signal asg", correct ) ; boolean_select <= transport 6 ; -- Last transaction above is marked -- s_boolean <= -- c_boolean_1 after 40 ns ; -- when 7 => correct := correct and s_boolean = c_boolean_1 and (s_boolean_savt + 30 ns) = Std.Standard.Now ; -- when 8 => correct := correct and s_boolean = c_boolean_1 and (s_boolean_savt + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00382" , "Inertial semantics check on a concurrent " & "signal asg", correct ) ; -- when others => -- No more transactions should have occurred test_report ( "ARCH00382" , "Inertial semantics check on a concurrent " & "signal asg", false ) ; -- end case ; -- s_boolean_savt <= transport Std.Standard.Now ; chk_boolean <= transport s_boolean_cnt after (1 us - Std.Standard.Now) ; s_boolean_cnt <= transport s_boolean_cnt + 1 ; wait until (not s_boolean'Quiet) and (s_boolean_savt /= Std.Standard.Now) ; -- end process CHG1 ; -- PGEN_CHKP_1 : process ( chk_boolean ) begin if Std.Standard.Now > 0 ns then test_report ( "P1" , "Inertial transactions completed entirely", chk_boolean = 8 ) ; end if ; end process PGEN_CHKP_1 ; -- -- s_boolean <= c_boolean_2 after 10 ns, c_boolean_1 after 20 ns when boolean_select = 1 else -- c_boolean_2 after 10 ns , c_boolean_1 after 20 ns , c_boolean_2 after 30 ns , c_boolean_1 after 40 ns when boolean_select = 2 else -- c_boolean_1 after 5 ns when boolean_select = 3 else -- c_boolean_1 after 100 ns when boolean_select = 4 else -- c_boolean_2 after 10 ns , c_boolean_1 after 20 ns , c_boolean_2 after 30 ns , c_boolean_1 after 40 ns when boolean_select = 5 else -- -- Last transaction above is marked c_boolean_1 after 40 ns ; -- CHG2 : process variable correct : boolean ; begin case s_bit_cnt is when 0 => null ; -- s_bit <= -- c_bit_2 after 10 ns, -- c_bit_1 after 20 ns ; -- when 1 => correct := s_bit = c_bit_2 and (s_bit_savt + 10 ns) = Std.Standard.Now ; -- when 2 => correct := correct and s_bit = c_bit_1 and (s_bit_savt + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00382.P2" , "Multi inertial transactions occurred on " & "concurrent signal asg", correct ) ; -- bit_select <= transport 2 ; -- s_bit <= -- c_bit_2 after 10 ns , -- c_bit_1 after 20 ns , -- c_bit_2 after 30 ns , -- c_bit_1 after 40 ns ; -- when 3 => correct := s_bit = c_bit_2 and (s_bit_savt + 10 ns) = Std.Standard.Now ; bit_select <= transport 3 ; -- s_bit <= -- c_bit_1 after 5 ns ; -- when 4 => correct := correct and s_bit = c_bit_1 and (s_bit_savt + 5 ns) = Std.Standard.Now ; test_report ( "ARCH00382" , "One inertial transaction occurred on a " & "concurrent signal asg", correct ) ; bit_select <= transport 4 ; -- s_bit <= -- c_bit_1 after 100 ns ; -- when 5 => correct := correct and s_bit = c_bit_1 and (s_bit_savt + 100 ns) = Std.Standard.Now ; test_report ( "ARCH00382" , "Old transactions were removed on a " & "concurrent signal asg", correct ) ; bit_select <= transport 5 ; -- s_bit <= -- c_bit_2 after 10 ns , -- c_bit_1 after 20 ns , -- c_bit_2 after 30 ns , -- c_bit_1 after 40 ns ; -- when 6 => correct := correct and s_bit = c_bit_2 and (s_bit_savt + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00382" , "One inertial transaction occurred on a " & "concurrent signal asg", correct ) ; bit_select <= transport 6 ; -- Last transaction above is marked -- s_bit <= -- c_bit_1 after 40 ns ; -- when 7 => correct := correct and s_bit = c_bit_1 and (s_bit_savt + 30 ns) = Std.Standard.Now ; -- when 8 => correct := correct and s_bit = c_bit_1 and (s_bit_savt + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00382" , "Inertial semantics check on a concurrent " & "signal asg", correct ) ; -- when others => -- No more transactions should have occurred test_report ( "ARCH00382" , "Inertial semantics check on a concurrent " & "signal asg", false ) ; -- end case ; -- s_bit_savt <= transport Std.Standard.Now ; chk_bit <= transport s_bit_cnt after (1 us - Std.Standard.Now) ; s_bit_cnt <= transport s_bit_cnt + 1 ; wait until (not s_bit'Quiet) and (s_bit_savt /= Std.Standard.Now) ; -- end process CHG2 ; -- PGEN_CHKP_2 : process ( chk_bit ) begin if Std.Standard.Now > 0 ns then test_report ( "P2" , "Inertial transactions completed entirely", chk_bit = 8 ) ; end if ; end process PGEN_CHKP_2 ; -- -- s_bit <= c_bit_2 after 10 ns, c_bit_1 after 20 ns when bit_select = 1 else -- c_bit_2 after 10 ns , c_bit_1 after 20 ns , c_bit_2 after 30 ns , c_bit_1 after 40 ns when bit_select = 2 else -- c_bit_1 after 5 ns when bit_select = 3 else -- c_bit_1 after 100 ns when bit_select = 4 else -- c_bit_2 after 10 ns , c_bit_1 after 20 ns , c_bit_2 after 30 ns , c_bit_1 after 40 ns when bit_select = 5 else -- -- Last transaction above is marked c_bit_1 after 40 ns ; -- CHG3 : process variable correct : boolean ; begin case s_severity_level_cnt is when 0 => null ; -- s_severity_level <= -- c_severity_level_2 after 10 ns, -- c_severity_level_1 after 20 ns ; -- when 1 => correct := s_severity_level = c_severity_level_2 and (s_severity_level_savt + 10 ns) = Std.Standard.Now ; -- when 2 => correct := correct and s_severity_level = c_severity_level_1 and (s_severity_level_savt + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00382.P3" , "Multi inertial transactions occurred on " & "concurrent signal asg", correct ) ; -- severity_level_select <= transport 2 ; -- s_severity_level <= -- c_severity_level_2 after 10 ns , -- c_severity_level_1 after 20 ns , -- c_severity_level_2 after 30 ns , -- c_severity_level_1 after 40 ns ; -- when 3 => correct := s_severity_level = c_severity_level_2 and (s_severity_level_savt + 10 ns) = Std.Standard.Now ; severity_level_select <= transport 3 ; -- s_severity_level <= -- c_severity_level_1 after 5 ns ; -- when 4 => correct := correct and s_severity_level = c_severity_level_1 and (s_severity_level_savt + 5 ns) = Std.Standard.Now ; test_report ( "ARCH00382" , "One inertial transaction occurred on a " & "concurrent signal asg", correct ) ; severity_level_select <= transport 4 ; -- s_severity_level <= -- c_severity_level_1 after 100 ns ; -- when 5 => correct := correct and s_severity_level = c_severity_level_1 and (s_severity_level_savt + 100 ns) = Std.Standard.Now ; test_report ( "ARCH00382" , "Old transactions were removed on a " & "concurrent signal asg", correct ) ; severity_level_select <= transport 5 ; -- s_severity_level <= -- c_severity_level_2 after 10 ns , -- c_severity_level_1 after 20 ns , -- c_severity_level_2 after 30 ns , -- c_severity_level_1 after 40 ns ; -- when 6 => correct := correct and s_severity_level = c_severity_level_2 and (s_severity_level_savt + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00382" , "One inertial transaction occurred on a " & "concurrent signal asg", correct ) ; severity_level_select <= transport 6 ; -- Last transaction above is marked -- s_severity_level <= -- c_severity_level_1 after 40 ns ; -- when 7 => correct := correct and s_severity_level = c_severity_level_1 and (s_severity_level_savt + 30 ns) = Std.Standard.Now ; -- when 8 => correct := correct and s_severity_level = c_severity_level_1 and (s_severity_level_savt + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00382" , "Inertial semantics check on a concurrent " & "signal asg", correct ) ; -- when others => -- No more transactions should have occurred test_report ( "ARCH00382" , "Inertial semantics check on a concurrent " & "signal asg", false ) ; -- end case ; -- s_severity_level_savt <= transport Std.Standard.Now ; chk_severity_level <= transport s_severity_level_cnt after (1 us - Std.Standard.Now) ; s_severity_level_cnt <= transport s_severity_level_cnt + 1 ; wait until (not s_severity_level'Quiet) and (s_severity_level_savt /= Std.Standard.Now) ; -- end process CHG3 ; -- PGEN_CHKP_3 : process ( chk_severity_level ) begin if Std.Standard.Now > 0 ns then test_report ( "P3" , "Inertial transactions completed entirely", chk_severity_level = 8 ) ; end if ; end process PGEN_CHKP_3 ; -- -- s_severity_level <= c_severity_level_2 after 10 ns, c_severity_level_1 after 20 ns when severity_level_select = 1 else -- c_severity_level_2 after 10 ns , c_severity_level_1 after 20 ns , c_severity_level_2 after 30 ns , c_severity_level_1 after 40 ns when severity_level_select = 2 else -- c_severity_level_1 after 5 ns when severity_level_select = 3 else -- c_severity_level_1 after 100 ns when severity_level_select = 4 else -- c_severity_level_2 after 10 ns , c_severity_level_1 after 20 ns , c_severity_level_2 after 30 ns , c_severity_level_1 after 40 ns when severity_level_select = 5 else -- -- Last transaction above is marked c_severity_level_1 after 40 ns ; -- CHG4 : process variable correct : boolean ; begin case s_character_cnt is when 0 => null ; -- s_character <= -- c_character_2 after 10 ns, -- c_character_1 after 20 ns ; -- when 1 => correct := s_character = c_character_2 and (s_character_savt + 10 ns) = Std.Standard.Now ; -- when 2 => correct := correct and s_character = c_character_1 and (s_character_savt + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00382.P4" , "Multi inertial transactions occurred on " & "concurrent signal asg", correct ) ; -- character_select <= transport 2 ; -- s_character <= -- c_character_2 after 10 ns , -- c_character_1 after 20 ns , -- c_character_2 after 30 ns , -- c_character_1 after 40 ns ; -- when 3 => correct := s_character = c_character_2 and (s_character_savt + 10 ns) = Std.Standard.Now ; character_select <= transport 3 ; -- s_character <= -- c_character_1 after 5 ns ; -- when 4 => correct := correct and s_character = c_character_1 and (s_character_savt + 5 ns) = Std.Standard.Now ; test_report ( "ARCH00382" , "One inertial transaction occurred on a " & "concurrent signal asg", correct ) ; character_select <= transport 4 ; -- s_character <= -- c_character_1 after 100 ns ; -- when 5 => correct := correct and s_character = c_character_1 and (s_character_savt + 100 ns) = Std.Standard.Now ; test_report ( "ARCH00382" , "Old transactions were removed on a " & "concurrent signal asg", correct ) ; character_select <= transport 5 ; -- s_character <= -- c_character_2 after 10 ns , -- c_character_1 after 20 ns , -- c_character_2 after 30 ns , -- c_character_1 after 40 ns ; -- when 6 => correct := correct and s_character = c_character_2 and (s_character_savt + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00382" , "One inertial transaction occurred on a " & "concurrent signal asg", correct ) ; character_select <= transport 6 ; -- Last transaction above is marked -- s_character <= -- c_character_1 after 40 ns ; -- when 7 => correct := correct and s_character = c_character_1 and (s_character_savt + 30 ns) = Std.Standard.Now ; -- when 8 => correct := correct and s_character = c_character_1 and (s_character_savt + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00382" , "Inertial semantics check on a concurrent " & "signal asg", correct ) ; -- when others => -- No more transactions should have occurred test_report ( "ARCH00382" , "Inertial semantics check on a concurrent " & "signal asg", false ) ; -- end case ; -- s_character_savt <= transport Std.Standard.Now ; chk_character <= transport s_character_cnt after (1 us - Std.Standard.Now) ; s_character_cnt <= transport s_character_cnt + 1 ; wait until (not s_character'Quiet) and (s_character_savt /= Std.Standard.Now) ; -- end process CHG4 ; -- PGEN_CHKP_4 : process ( chk_character ) begin if Std.Standard.Now > 0 ns then test_report ( "P4" , "Inertial transactions completed entirely", chk_character = 8 ) ; end if ; end process PGEN_CHKP_4 ; -- -- s_character <= c_character_2 after 10 ns, c_character_1 after 20 ns when character_select = 1 else -- c_character_2 after 10 ns , c_character_1 after 20 ns , c_character_2 after 30 ns , c_character_1 after 40 ns when character_select = 2 else -- c_character_1 after 5 ns when character_select = 3 else -- c_character_1 after 100 ns when character_select = 4 else -- c_character_2 after 10 ns , c_character_1 after 20 ns , c_character_2 after 30 ns , c_character_1 after 40 ns when character_select = 5 else -- -- Last transaction above is marked c_character_1 after 40 ns ; -- CHG5 : process variable correct : boolean ; begin case s_st_enum1_cnt is when 0 => null ; -- s_st_enum1 <= -- c_st_enum1_2 after 10 ns, -- c_st_enum1_1 after 20 ns ; -- when 1 => correct := s_st_enum1 = c_st_enum1_2 and (s_st_enum1_savt + 10 ns) = Std.Standard.Now ; -- when 2 => correct := correct and s_st_enum1 = c_st_enum1_1 and (s_st_enum1_savt + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00382.P5" , "Multi inertial transactions occurred on " & "concurrent signal asg", correct ) ; -- st_enum1_select <= transport 2 ; -- s_st_enum1 <= -- c_st_enum1_2 after 10 ns , -- c_st_enum1_1 after 20 ns , -- c_st_enum1_2 after 30 ns , -- c_st_enum1_1 after 40 ns ; -- when 3 => correct := s_st_enum1 = c_st_enum1_2 and (s_st_enum1_savt + 10 ns) = Std.Standard.Now ; st_enum1_select <= transport 3 ; -- s_st_enum1 <= -- c_st_enum1_1 after 5 ns ; -- when 4 => correct := correct and s_st_enum1 = c_st_enum1_1 and (s_st_enum1_savt + 5 ns) = Std.Standard.Now ; test_report ( "ARCH00382" , "One inertial transaction occurred on a " & "concurrent signal asg", correct ) ; st_enum1_select <= transport 4 ; -- s_st_enum1 <= -- c_st_enum1_1 after 100 ns ; -- when 5 => correct := correct and s_st_enum1 = c_st_enum1_1 and (s_st_enum1_savt + 100 ns) = Std.Standard.Now ; test_report ( "ARCH00382" , "Old transactions were removed on a " & "concurrent signal asg", correct ) ; st_enum1_select <= transport 5 ; -- s_st_enum1 <= -- c_st_enum1_2 after 10 ns , -- c_st_enum1_1 after 20 ns , -- c_st_enum1_2 after 30 ns , -- c_st_enum1_1 after 40 ns ; -- when 6 => correct := correct and s_st_enum1 = c_st_enum1_2 and (s_st_enum1_savt + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00382" , "One inertial transaction occurred on a " & "concurrent signal asg", correct ) ; st_enum1_select <= transport 6 ; -- Last transaction above is marked -- s_st_enum1 <= -- c_st_enum1_1 after 40 ns ; -- when 7 => correct := correct and s_st_enum1 = c_st_enum1_1 and (s_st_enum1_savt + 30 ns) = Std.Standard.Now ; -- when 8 => correct := correct and s_st_enum1 = c_st_enum1_1 and (s_st_enum1_savt + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00382" , "Inertial semantics check on a concurrent " & "signal asg", correct ) ; -- when others => -- No more transactions should have occurred test_report ( "ARCH00382" , "Inertial semantics check on a concurrent " & "signal asg", false ) ; -- end case ; -- s_st_enum1_savt <= transport Std.Standard.Now ; chk_st_enum1 <= transport s_st_enum1_cnt after (1 us - Std.Standard.Now) ; s_st_enum1_cnt <= transport s_st_enum1_cnt + 1 ; wait until (not s_st_enum1'Quiet) and (s_st_enum1_savt /= Std.Standard.Now) ; -- end process CHG5 ; -- PGEN_CHKP_5 : process ( chk_st_enum1 ) begin if Std.Standard.Now > 0 ns then test_report ( "P5" , "Inertial transactions completed entirely", chk_st_enum1 = 8 ) ; end if ; end process PGEN_CHKP_5 ; -- -- s_st_enum1 <= c_st_enum1_2 after 10 ns, c_st_enum1_1 after 20 ns when st_enum1_select = 1 else -- c_st_enum1_2 after 10 ns , c_st_enum1_1 after 20 ns , c_st_enum1_2 after 30 ns , c_st_enum1_1 after 40 ns when st_enum1_select = 2 else -- c_st_enum1_1 after 5 ns when st_enum1_select = 3 else -- c_st_enum1_1 after 100 ns when st_enum1_select = 4 else -- c_st_enum1_2 after 10 ns , c_st_enum1_1 after 20 ns , c_st_enum1_2 after 30 ns , c_st_enum1_1 after 40 ns when st_enum1_select = 5 else -- -- Last transaction above is marked c_st_enum1_1 after 40 ns ; -- CHG6 : process variable correct : boolean ; begin case s_integer_cnt is when 0 => null ; -- s_integer <= -- c_integer_2 after 10 ns, -- c_integer_1 after 20 ns ; -- when 1 => correct := s_integer = c_integer_2 and (s_integer_savt + 10 ns) = Std.Standard.Now ; -- when 2 => correct := correct and s_integer = c_integer_1 and (s_integer_savt + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00382.P6" , "Multi inertial transactions occurred on " & "concurrent signal asg", correct ) ; -- integer_select <= transport 2 ; -- s_integer <= -- c_integer_2 after 10 ns , -- c_integer_1 after 20 ns , -- c_integer_2 after 30 ns , -- c_integer_1 after 40 ns ; -- when 3 => correct := s_integer = c_integer_2 and (s_integer_savt + 10 ns) = Std.Standard.Now ; integer_select <= transport 3 ; -- s_integer <= -- c_integer_1 after 5 ns ; -- when 4 => correct := correct and s_integer = c_integer_1 and (s_integer_savt + 5 ns) = Std.Standard.Now ; test_report ( "ARCH00382" , "One inertial transaction occurred on a " & "concurrent signal asg", correct ) ; integer_select <= transport 4 ; -- s_integer <= -- c_integer_1 after 100 ns ; -- when 5 => correct := correct and s_integer = c_integer_1 and (s_integer_savt + 100 ns) = Std.Standard.Now ; test_report ( "ARCH00382" , "Old transactions were removed on a " & "concurrent signal asg", correct ) ; integer_select <= transport 5 ; -- s_integer <= -- c_integer_2 after 10 ns , -- c_integer_1 after 20 ns , -- c_integer_2 after 30 ns , -- c_integer_1 after 40 ns ; -- when 6 => correct := correct and s_integer = c_integer_2 and (s_integer_savt + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00382" , "One inertial transaction occurred on a " & "concurrent signal asg", correct ) ; integer_select <= transport 6 ; -- Last transaction above is marked -- s_integer <= -- c_integer_1 after 40 ns ; -- when 7 => correct := correct and s_integer = c_integer_1 and (s_integer_savt + 30 ns) = Std.Standard.Now ; -- when 8 => correct := correct and s_integer = c_integer_1 and (s_integer_savt + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00382" , "Inertial semantics check on a concurrent " & "signal asg", correct ) ; -- when others => -- No more transactions should have occurred test_report ( "ARCH00382" , "Inertial semantics check on a concurrent " & "signal asg", false ) ; -- end case ; -- s_integer_savt <= transport Std.Standard.Now ; chk_integer <= transport s_integer_cnt after (1 us - Std.Standard.Now) ; s_integer_cnt <= transport s_integer_cnt + 1 ; wait until (not s_integer'Quiet) and (s_integer_savt /= Std.Standard.Now) ; -- end process CHG6 ; -- PGEN_CHKP_6 : process ( chk_integer ) begin if Std.Standard.Now > 0 ns then test_report ( "P6" , "Inertial transactions completed entirely", chk_integer = 8 ) ; end if ; end process PGEN_CHKP_6 ; -- -- s_integer <= c_integer_2 after 10 ns, c_integer_1 after 20 ns when integer_select = 1 else -- c_integer_2 after 10 ns , c_integer_1 after 20 ns , c_integer_2 after 30 ns , c_integer_1 after 40 ns when integer_select = 2 else -- c_integer_1 after 5 ns when integer_select = 3 else -- c_integer_1 after 100 ns when integer_select = 4 else -- c_integer_2 after 10 ns , c_integer_1 after 20 ns , c_integer_2 after 30 ns , c_integer_1 after 40 ns when integer_select = 5 else -- -- Last transaction above is marked c_integer_1 after 40 ns ; -- CHG7 : process variable correct : boolean ; begin case s_st_int1_cnt is when 0 => null ; -- s_st_int1 <= -- c_st_int1_2 after 10 ns, -- c_st_int1_1 after 20 ns ; -- when 1 => correct := s_st_int1 = c_st_int1_2 and (s_st_int1_savt + 10 ns) = Std.Standard.Now ; -- when 2 => correct := correct and s_st_int1 = c_st_int1_1 and (s_st_int1_savt + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00382.P7" , "Multi inertial transactions occurred on " & "concurrent signal asg", correct ) ; -- st_int1_select <= transport 2 ; -- s_st_int1 <= -- c_st_int1_2 after 10 ns , -- c_st_int1_1 after 20 ns , -- c_st_int1_2 after 30 ns , -- c_st_int1_1 after 40 ns ; -- when 3 => correct := s_st_int1 = c_st_int1_2 and (s_st_int1_savt + 10 ns) = Std.Standard.Now ; st_int1_select <= transport 3 ; -- s_st_int1 <= -- c_st_int1_1 after 5 ns ; -- when 4 => correct := correct and s_st_int1 = c_st_int1_1 and (s_st_int1_savt + 5 ns) = Std.Standard.Now ; test_report ( "ARCH00382" , "One inertial transaction occurred on a " & "concurrent signal asg", correct ) ; st_int1_select <= transport 4 ; -- s_st_int1 <= -- c_st_int1_1 after 100 ns ; -- when 5 => correct := correct and s_st_int1 = c_st_int1_1 and (s_st_int1_savt + 100 ns) = Std.Standard.Now ; test_report ( "ARCH00382" , "Old transactions were removed on a " & "concurrent signal asg", correct ) ; st_int1_select <= transport 5 ; -- s_st_int1 <= -- c_st_int1_2 after 10 ns , -- c_st_int1_1 after 20 ns , -- c_st_int1_2 after 30 ns , -- c_st_int1_1 after 40 ns ; -- when 6 => correct := correct and s_st_int1 = c_st_int1_2 and (s_st_int1_savt + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00382" , "One inertial transaction occurred on a " & "concurrent signal asg", correct ) ; st_int1_select <= transport 6 ; -- Last transaction above is marked -- s_st_int1 <= -- c_st_int1_1 after 40 ns ; -- when 7 => correct := correct and s_st_int1 = c_st_int1_1 and (s_st_int1_savt + 30 ns) = Std.Standard.Now ; -- when 8 => correct := correct and s_st_int1 = c_st_int1_1 and (s_st_int1_savt + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00382" , "Inertial semantics check on a concurrent " & "signal asg", correct ) ; -- when others => -- No more transactions should have occurred test_report ( "ARCH00382" , "Inertial semantics check on a concurrent " & "signal asg", false ) ; -- end case ; -- s_st_int1_savt <= transport Std.Standard.Now ; chk_st_int1 <= transport s_st_int1_cnt after (1 us - Std.Standard.Now) ; s_st_int1_cnt <= transport s_st_int1_cnt + 1 ; wait until (not s_st_int1'Quiet) and (s_st_int1_savt /= Std.Standard.Now) ; -- end process CHG7 ; -- PGEN_CHKP_7 : process ( chk_st_int1 ) begin if Std.Standard.Now > 0 ns then test_report ( "P7" , "Inertial transactions completed entirely", chk_st_int1 = 8 ) ; end if ; end process PGEN_CHKP_7 ; -- -- s_st_int1 <= c_st_int1_2 after 10 ns, c_st_int1_1 after 20 ns when st_int1_select = 1 else -- c_st_int1_2 after 10 ns , c_st_int1_1 after 20 ns , c_st_int1_2 after 30 ns , c_st_int1_1 after 40 ns when st_int1_select = 2 else -- c_st_int1_1 after 5 ns when st_int1_select = 3 else -- c_st_int1_1 after 100 ns when st_int1_select = 4 else -- c_st_int1_2 after 10 ns , c_st_int1_1 after 20 ns , c_st_int1_2 after 30 ns , c_st_int1_1 after 40 ns when st_int1_select = 5 else -- -- Last transaction above is marked c_st_int1_1 after 40 ns ; -- CHG8 : process variable correct : boolean ; begin case s_time_cnt is when 0 => null ; -- s_time <= -- c_time_2 after 10 ns, -- c_time_1 after 20 ns ; -- when 1 => correct := s_time = c_time_2 and (s_time_savt + 10 ns) = Std.Standard.Now ; -- when 2 => correct := correct and s_time = c_time_1 and (s_time_savt + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00382.P8" , "Multi inertial transactions occurred on " & "concurrent signal asg", correct ) ; -- time_select <= transport 2 ; -- s_time <= -- c_time_2 after 10 ns , -- c_time_1 after 20 ns , -- c_time_2 after 30 ns , -- c_time_1 after 40 ns ; -- when 3 => correct := s_time = c_time_2 and (s_time_savt + 10 ns) = Std.Standard.Now ; time_select <= transport 3 ; -- s_time <= -- c_time_1 after 5 ns ; -- when 4 => correct := correct and s_time = c_time_1 and (s_time_savt + 5 ns) = Std.Standard.Now ; test_report ( "ARCH00382" , "One inertial transaction occurred on a " & "concurrent signal asg", correct ) ; time_select <= transport 4 ; -- s_time <= -- c_time_1 after 100 ns ; -- when 5 => correct := correct and s_time = c_time_1 and (s_time_savt + 100 ns) = Std.Standard.Now ; test_report ( "ARCH00382" , "Old transactions were removed on a " & "concurrent signal asg", correct ) ; time_select <= transport 5 ; -- s_time <= -- c_time_2 after 10 ns , -- c_time_1 after 20 ns , -- c_time_2 after 30 ns , -- c_time_1 after 40 ns ; -- when 6 => correct := correct and s_time = c_time_2 and (s_time_savt + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00382" , "One inertial transaction occurred on a " & "concurrent signal asg", correct ) ; time_select <= transport 6 ; -- Last transaction above is marked -- s_time <= -- c_time_1 after 40 ns ; -- when 7 => correct := correct and s_time = c_time_1 and (s_time_savt + 30 ns) = Std.Standard.Now ; -- when 8 => correct := correct and s_time = c_time_1 and (s_time_savt + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00382" , "Inertial semantics check on a concurrent " & "signal asg", correct ) ; -- when others => -- No more transactions should have occurred test_report ( "ARCH00382" , "Inertial semantics check on a concurrent " & "signal asg", false ) ; -- end case ; -- s_time_savt <= transport Std.Standard.Now ; chk_time <= transport s_time_cnt after (1 us - Std.Standard.Now) ; s_time_cnt <= transport s_time_cnt + 1 ; wait until (not s_time'Quiet) and (s_time_savt /= Std.Standard.Now) ; -- end process CHG8 ; -- PGEN_CHKP_8 : process ( chk_time ) begin if Std.Standard.Now > 0 ns then test_report ( "P8" , "Inertial transactions completed entirely", chk_time = 8 ) ; end if ; end process PGEN_CHKP_8 ; -- -- s_time <= c_time_2 after 10 ns, c_time_1 after 20 ns when time_select = 1 else -- c_time_2 after 10 ns , c_time_1 after 20 ns , c_time_2 after 30 ns , c_time_1 after 40 ns when time_select = 2 else -- c_time_1 after 5 ns when time_select = 3 else -- c_time_1 after 100 ns when time_select = 4 else -- c_time_2 after 10 ns , c_time_1 after 20 ns , c_time_2 after 30 ns , c_time_1 after 40 ns when time_select = 5 else -- -- Last transaction above is marked c_time_1 after 40 ns ; -- CHG9 : process variable correct : boolean ; begin case s_st_phys1_cnt is when 0 => null ; -- s_st_phys1 <= -- c_st_phys1_2 after 10 ns, -- c_st_phys1_1 after 20 ns ; -- when 1 => correct := s_st_phys1 = c_st_phys1_2 and (s_st_phys1_savt + 10 ns) = Std.Standard.Now ; -- when 2 => correct := correct and s_st_phys1 = c_st_phys1_1 and (s_st_phys1_savt + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00382.P9" , "Multi inertial transactions occurred on " & "concurrent signal asg", correct ) ; -- st_phys1_select <= transport 2 ; -- s_st_phys1 <= -- c_st_phys1_2 after 10 ns , -- c_st_phys1_1 after 20 ns , -- c_st_phys1_2 after 30 ns , -- c_st_phys1_1 after 40 ns ; -- when 3 => correct := s_st_phys1 = c_st_phys1_2 and (s_st_phys1_savt + 10 ns) = Std.Standard.Now ; st_phys1_select <= transport 3 ; -- s_st_phys1 <= -- c_st_phys1_1 after 5 ns ; -- when 4 => correct := correct and s_st_phys1 = c_st_phys1_1 and (s_st_phys1_savt + 5 ns) = Std.Standard.Now ; test_report ( "ARCH00382" , "One inertial transaction occurred on a " & "concurrent signal asg", correct ) ; st_phys1_select <= transport 4 ; -- s_st_phys1 <= -- c_st_phys1_1 after 100 ns ; -- when 5 => correct := correct and s_st_phys1 = c_st_phys1_1 and (s_st_phys1_savt + 100 ns) = Std.Standard.Now ; test_report ( "ARCH00382" , "Old transactions were removed on a " & "concurrent signal asg", correct ) ; st_phys1_select <= transport 5 ; -- s_st_phys1 <= -- c_st_phys1_2 after 10 ns , -- c_st_phys1_1 after 20 ns , -- c_st_phys1_2 after 30 ns , -- c_st_phys1_1 after 40 ns ; -- when 6 => correct := correct and s_st_phys1 = c_st_phys1_2 and (s_st_phys1_savt + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00382" , "One inertial transaction occurred on a " & "concurrent signal asg", correct ) ; st_phys1_select <= transport 6 ; -- Last transaction above is marked -- s_st_phys1 <= -- c_st_phys1_1 after 40 ns ; -- when 7 => correct := correct and s_st_phys1 = c_st_phys1_1 and (s_st_phys1_savt + 30 ns) = Std.Standard.Now ; -- when 8 => correct := correct and s_st_phys1 = c_st_phys1_1 and (s_st_phys1_savt + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00382" , "Inertial semantics check on a concurrent " & "signal asg", correct ) ; -- when others => -- No more transactions should have occurred test_report ( "ARCH00382" , "Inertial semantics check on a concurrent " & "signal asg", false ) ; -- end case ; -- s_st_phys1_savt <= transport Std.Standard.Now ; chk_st_phys1 <= transport s_st_phys1_cnt after (1 us - Std.Standard.Now) ; s_st_phys1_cnt <= transport s_st_phys1_cnt + 1 ; wait until (not s_st_phys1'Quiet) and (s_st_phys1_savt /= Std.Standard.Now) ; -- end process CHG9 ; -- PGEN_CHKP_9 : process ( chk_st_phys1 ) begin if Std.Standard.Now > 0 ns then test_report ( "P9" , "Inertial transactions completed entirely", chk_st_phys1 = 8 ) ; end if ; end process PGEN_CHKP_9 ; -- -- s_st_phys1 <= c_st_phys1_2 after 10 ns, c_st_phys1_1 after 20 ns when st_phys1_select = 1 else -- c_st_phys1_2 after 10 ns , c_st_phys1_1 after 20 ns , c_st_phys1_2 after 30 ns , c_st_phys1_1 after 40 ns when st_phys1_select = 2 else -- c_st_phys1_1 after 5 ns when st_phys1_select = 3 else -- c_st_phys1_1 after 100 ns when st_phys1_select = 4 else -- c_st_phys1_2 after 10 ns , c_st_phys1_1 after 20 ns , c_st_phys1_2 after 30 ns , c_st_phys1_1 after 40 ns when st_phys1_select = 5 else -- -- Last transaction above is marked c_st_phys1_1 after 40 ns ; -- CHG10 : process variable correct : boolean ; begin case s_real_cnt is when 0 => null ; -- s_real <= -- c_real_2 after 10 ns, -- c_real_1 after 20 ns ; -- when 1 => correct := s_real = c_real_2 and (s_real_savt + 10 ns) = Std.Standard.Now ; -- when 2 => correct := correct and s_real = c_real_1 and (s_real_savt + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00382.P10" , "Multi inertial transactions occurred on " & "concurrent signal asg", correct ) ; -- real_select <= transport 2 ; -- s_real <= -- c_real_2 after 10 ns , -- c_real_1 after 20 ns , -- c_real_2 after 30 ns , -- c_real_1 after 40 ns ; -- when 3 => correct := s_real = c_real_2 and (s_real_savt + 10 ns) = Std.Standard.Now ; real_select <= transport 3 ; -- s_real <= -- c_real_1 after 5 ns ; -- when 4 => correct := correct and s_real = c_real_1 and (s_real_savt + 5 ns) = Std.Standard.Now ; test_report ( "ARCH00382" , "One inertial transaction occurred on a " & "concurrent signal asg", correct ) ; real_select <= transport 4 ; -- s_real <= -- c_real_1 after 100 ns ; -- when 5 => correct := correct and s_real = c_real_1 and (s_real_savt + 100 ns) = Std.Standard.Now ; test_report ( "ARCH00382" , "Old transactions were removed on a " & "concurrent signal asg", correct ) ; real_select <= transport 5 ; -- s_real <= -- c_real_2 after 10 ns , -- c_real_1 after 20 ns , -- c_real_2 after 30 ns , -- c_real_1 after 40 ns ; -- when 6 => correct := correct and s_real = c_real_2 and (s_real_savt + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00382" , "One inertial transaction occurred on a " & "concurrent signal asg", correct ) ; real_select <= transport 6 ; -- Last transaction above is marked -- s_real <= -- c_real_1 after 40 ns ; -- when 7 => correct := correct and s_real = c_real_1 and (s_real_savt + 30 ns) = Std.Standard.Now ; -- when 8 => correct := correct and s_real = c_real_1 and (s_real_savt + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00382" , "Inertial semantics check on a concurrent " & "signal asg", correct ) ; -- when others => -- No more transactions should have occurred test_report ( "ARCH00382" , "Inertial semantics check on a concurrent " & "signal asg", false ) ; -- end case ; -- s_real_savt <= transport Std.Standard.Now ; chk_real <= transport s_real_cnt after (1 us - Std.Standard.Now) ; s_real_cnt <= transport s_real_cnt + 1 ; wait until (not s_real'Quiet) and (s_real_savt /= Std.Standard.Now) ; -- end process CHG10 ; -- PGEN_CHKP_10 : process ( chk_real ) begin if Std.Standard.Now > 0 ns then test_report ( "P10" , "Inertial transactions completed entirely", chk_real = 8 ) ; end if ; end process PGEN_CHKP_10 ; -- -- s_real <= c_real_2 after 10 ns, c_real_1 after 20 ns when real_select = 1 else -- c_real_2 after 10 ns , c_real_1 after 20 ns , c_real_2 after 30 ns , c_real_1 after 40 ns when real_select = 2 else -- c_real_1 after 5 ns when real_select = 3 else -- c_real_1 after 100 ns when real_select = 4 else -- c_real_2 after 10 ns , c_real_1 after 20 ns , c_real_2 after 30 ns , c_real_1 after 40 ns when real_select = 5 else -- -- Last transaction above is marked c_real_1 after 40 ns ; -- CHG11 : process variable correct : boolean ; begin case s_st_real1_cnt is when 0 => null ; -- s_st_real1 <= -- c_st_real1_2 after 10 ns, -- c_st_real1_1 after 20 ns ; -- when 1 => correct := s_st_real1 = c_st_real1_2 and (s_st_real1_savt + 10 ns) = Std.Standard.Now ; -- when 2 => correct := correct and s_st_real1 = c_st_real1_1 and (s_st_real1_savt + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00382.P11" , "Multi inertial transactions occurred on " & "concurrent signal asg", correct ) ; -- st_real1_select <= transport 2 ; -- s_st_real1 <= -- c_st_real1_2 after 10 ns , -- c_st_real1_1 after 20 ns , -- c_st_real1_2 after 30 ns , -- c_st_real1_1 after 40 ns ; -- when 3 => correct := s_st_real1 = c_st_real1_2 and (s_st_real1_savt + 10 ns) = Std.Standard.Now ; st_real1_select <= transport 3 ; -- s_st_real1 <= -- c_st_real1_1 after 5 ns ; -- when 4 => correct := correct and s_st_real1 = c_st_real1_1 and (s_st_real1_savt + 5 ns) = Std.Standard.Now ; test_report ( "ARCH00382" , "One inertial transaction occurred on a " & "concurrent signal asg", correct ) ; st_real1_select <= transport 4 ; -- s_st_real1 <= -- c_st_real1_1 after 100 ns ; -- when 5 => correct := correct and s_st_real1 = c_st_real1_1 and (s_st_real1_savt + 100 ns) = Std.Standard.Now ; test_report ( "ARCH00382" , "Old transactions were removed on a " & "concurrent signal asg", correct ) ; st_real1_select <= transport 5 ; -- s_st_real1 <= -- c_st_real1_2 after 10 ns , -- c_st_real1_1 after 20 ns , -- c_st_real1_2 after 30 ns , -- c_st_real1_1 after 40 ns ; -- when 6 => correct := correct and s_st_real1 = c_st_real1_2 and (s_st_real1_savt + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00382" , "One inertial transaction occurred on a " & "concurrent signal asg", correct ) ; st_real1_select <= transport 6 ; -- Last transaction above is marked -- s_st_real1 <= -- c_st_real1_1 after 40 ns ; -- when 7 => correct := correct and s_st_real1 = c_st_real1_1 and (s_st_real1_savt + 30 ns) = Std.Standard.Now ; -- when 8 => correct := correct and s_st_real1 = c_st_real1_1 and (s_st_real1_savt + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00382" , "Inertial semantics check on a concurrent " & "signal asg", correct ) ; -- when others => -- No more transactions should have occurred test_report ( "ARCH00382" , "Inertial semantics check on a concurrent " & "signal asg", false ) ; -- end case ; -- s_st_real1_savt <= transport Std.Standard.Now ; chk_st_real1 <= transport s_st_real1_cnt after (1 us - Std.Standard.Now) ; s_st_real1_cnt <= transport s_st_real1_cnt + 1 ; wait until (not s_st_real1'Quiet) and (s_st_real1_savt /= Std.Standard.Now) ; -- end process CHG11 ; -- PGEN_CHKP_11 : process ( chk_st_real1 ) begin if Std.Standard.Now > 0 ns then test_report ( "P11" , "Inertial transactions completed entirely", chk_st_real1 = 8 ) ; end if ; end process PGEN_CHKP_11 ; -- -- s_st_real1 <= c_st_real1_2 after 10 ns, c_st_real1_1 after 20 ns when st_real1_select = 1 else -- c_st_real1_2 after 10 ns , c_st_real1_1 after 20 ns , c_st_real1_2 after 30 ns , c_st_real1_1 after 40 ns when st_real1_select = 2 else -- c_st_real1_1 after 5 ns when st_real1_select = 3 else -- c_st_real1_1 after 100 ns when st_real1_select = 4 else -- c_st_real1_2 after 10 ns , c_st_real1_1 after 20 ns , c_st_real1_2 after 30 ns , c_st_real1_1 after 40 ns when st_real1_select = 5 else -- -- Last transaction above is marked c_st_real1_1 after 40 ns ; -- CHG12 : process variable correct : boolean ; begin case s_st_rec1_cnt is when 0 => null ; -- s_st_rec1 <= -- c_st_rec1_2 after 10 ns, -- c_st_rec1_1 after 20 ns ; -- when 1 => correct := s_st_rec1 = c_st_rec1_2 and (s_st_rec1_savt + 10 ns) = Std.Standard.Now ; -- when 2 => correct := correct and s_st_rec1 = c_st_rec1_1 and (s_st_rec1_savt + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00382.P12" , "Multi inertial transactions occurred on " & "concurrent signal asg", correct ) ; -- st_rec1_select <= transport 2 ; -- s_st_rec1 <= -- c_st_rec1_2 after 10 ns , -- c_st_rec1_1 after 20 ns , -- c_st_rec1_2 after 30 ns , -- c_st_rec1_1 after 40 ns ; -- when 3 => correct := s_st_rec1 = c_st_rec1_2 and (s_st_rec1_savt + 10 ns) = Std.Standard.Now ; st_rec1_select <= transport 3 ; -- s_st_rec1 <= -- c_st_rec1_1 after 5 ns ; -- when 4 => correct := correct and s_st_rec1 = c_st_rec1_1 and (s_st_rec1_savt + 5 ns) = Std.Standard.Now ; test_report ( "ARCH00382" , "One inertial transaction occurred on a " & "concurrent signal asg", correct ) ; st_rec1_select <= transport 4 ; -- s_st_rec1 <= -- c_st_rec1_1 after 100 ns ; -- when 5 => correct := correct and s_st_rec1 = c_st_rec1_1 and (s_st_rec1_savt + 100 ns) = Std.Standard.Now ; test_report ( "ARCH00382" , "Old transactions were removed on a " & "concurrent signal asg", correct ) ; st_rec1_select <= transport 5 ; -- s_st_rec1 <= -- c_st_rec1_2 after 10 ns , -- c_st_rec1_1 after 20 ns , -- c_st_rec1_2 after 30 ns , -- c_st_rec1_1 after 40 ns ; -- when 6 => correct := correct and s_st_rec1 = c_st_rec1_2 and (s_st_rec1_savt + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00382" , "One inertial transaction occurred on a " & "concurrent signal asg", correct ) ; st_rec1_select <= transport 6 ; -- Last transaction above is marked -- s_st_rec1 <= -- c_st_rec1_1 after 40 ns ; -- when 7 => correct := correct and s_st_rec1 = c_st_rec1_1 and (s_st_rec1_savt + 30 ns) = Std.Standard.Now ; -- when 8 => correct := correct and s_st_rec1 = c_st_rec1_1 and (s_st_rec1_savt + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00382" , "Inertial semantics check on a concurrent " & "signal asg", correct ) ; -- when others => -- No more transactions should have occurred test_report ( "ARCH00382" , "Inertial semantics check on a concurrent " & "signal asg", false ) ; -- end case ; -- s_st_rec1_savt <= transport Std.Standard.Now ; chk_st_rec1 <= transport s_st_rec1_cnt after (1 us - Std.Standard.Now) ; s_st_rec1_cnt <= transport s_st_rec1_cnt + 1 ; wait until (not s_st_rec1'Quiet) and (s_st_rec1_savt /= Std.Standard.Now) ; -- end process CHG12 ; -- PGEN_CHKP_12 : process ( chk_st_rec1 ) begin if Std.Standard.Now > 0 ns then test_report ( "P12" , "Inertial transactions completed entirely", chk_st_rec1 = 8 ) ; end if ; end process PGEN_CHKP_12 ; -- -- s_st_rec1 <= c_st_rec1_2 after 10 ns, c_st_rec1_1 after 20 ns when st_rec1_select = 1 else -- c_st_rec1_2 after 10 ns , c_st_rec1_1 after 20 ns , c_st_rec1_2 after 30 ns , c_st_rec1_1 after 40 ns when st_rec1_select = 2 else -- c_st_rec1_1 after 5 ns when st_rec1_select = 3 else -- c_st_rec1_1 after 100 ns when st_rec1_select = 4 else -- c_st_rec1_2 after 10 ns , c_st_rec1_1 after 20 ns , c_st_rec1_2 after 30 ns , c_st_rec1_1 after 40 ns when st_rec1_select = 5 else -- -- Last transaction above is marked c_st_rec1_1 after 40 ns ; -- CHG13 : process variable correct : boolean ; begin case s_st_rec2_cnt is when 0 => null ; -- s_st_rec2 <= -- c_st_rec2_2 after 10 ns, -- c_st_rec2_1 after 20 ns ; -- when 1 => correct := s_st_rec2 = c_st_rec2_2 and (s_st_rec2_savt + 10 ns) = Std.Standard.Now ; -- when 2 => correct := correct and s_st_rec2 = c_st_rec2_1 and (s_st_rec2_savt + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00382.P13" , "Multi inertial transactions occurred on " & "concurrent signal asg", correct ) ; -- st_rec2_select <= transport 2 ; -- s_st_rec2 <= -- c_st_rec2_2 after 10 ns , -- c_st_rec2_1 after 20 ns , -- c_st_rec2_2 after 30 ns , -- c_st_rec2_1 after 40 ns ; -- when 3 => correct := s_st_rec2 = c_st_rec2_2 and (s_st_rec2_savt + 10 ns) = Std.Standard.Now ; st_rec2_select <= transport 3 ; -- s_st_rec2 <= -- c_st_rec2_1 after 5 ns ; -- when 4 => correct := correct and s_st_rec2 = c_st_rec2_1 and (s_st_rec2_savt + 5 ns) = Std.Standard.Now ; test_report ( "ARCH00382" , "One inertial transaction occurred on a " & "concurrent signal asg", correct ) ; st_rec2_select <= transport 4 ; -- s_st_rec2 <= -- c_st_rec2_1 after 100 ns ; -- when 5 => correct := correct and s_st_rec2 = c_st_rec2_1 and (s_st_rec2_savt + 100 ns) = Std.Standard.Now ; test_report ( "ARCH00382" , "Old transactions were removed on a " & "concurrent signal asg", correct ) ; st_rec2_select <= transport 5 ; -- s_st_rec2 <= -- c_st_rec2_2 after 10 ns , -- c_st_rec2_1 after 20 ns , -- c_st_rec2_2 after 30 ns , -- c_st_rec2_1 after 40 ns ; -- when 6 => correct := correct and s_st_rec2 = c_st_rec2_2 and (s_st_rec2_savt + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00382" , "One inertial transaction occurred on a " & "concurrent signal asg", correct ) ; st_rec2_select <= transport 6 ; -- Last transaction above is marked -- s_st_rec2 <= -- c_st_rec2_1 after 40 ns ; -- when 7 => correct := correct and s_st_rec2 = c_st_rec2_1 and (s_st_rec2_savt + 30 ns) = Std.Standard.Now ; -- when 8 => correct := correct and s_st_rec2 = c_st_rec2_1 and (s_st_rec2_savt + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00382" , "Inertial semantics check on a concurrent " & "signal asg", correct ) ; -- when others => -- No more transactions should have occurred test_report ( "ARCH00382" , "Inertial semantics check on a concurrent " & "signal asg", false ) ; -- end case ; -- s_st_rec2_savt <= transport Std.Standard.Now ; chk_st_rec2 <= transport s_st_rec2_cnt after (1 us - Std.Standard.Now) ; s_st_rec2_cnt <= transport s_st_rec2_cnt + 1 ; wait until (not s_st_rec2'Quiet) and (s_st_rec2_savt /= Std.Standard.Now) ; -- end process CHG13 ; -- PGEN_CHKP_13 : process ( chk_st_rec2 ) begin if Std.Standard.Now > 0 ns then test_report ( "P13" , "Inertial transactions completed entirely", chk_st_rec2 = 8 ) ; end if ; end process PGEN_CHKP_13 ; -- -- s_st_rec2 <= c_st_rec2_2 after 10 ns, c_st_rec2_1 after 20 ns when st_rec2_select = 1 else -- c_st_rec2_2 after 10 ns , c_st_rec2_1 after 20 ns , c_st_rec2_2 after 30 ns , c_st_rec2_1 after 40 ns when st_rec2_select = 2 else -- c_st_rec2_1 after 5 ns when st_rec2_select = 3 else -- c_st_rec2_1 after 100 ns when st_rec2_select = 4 else -- c_st_rec2_2 after 10 ns , c_st_rec2_1 after 20 ns , c_st_rec2_2 after 30 ns , c_st_rec2_1 after 40 ns when st_rec2_select = 5 else -- -- Last transaction above is marked c_st_rec2_1 after 40 ns ; -- CHG14 : process variable correct : boolean ; begin case s_st_rec3_cnt is when 0 => null ; -- s_st_rec3 <= -- c_st_rec3_2 after 10 ns, -- c_st_rec3_1 after 20 ns ; -- when 1 => correct := s_st_rec3 = c_st_rec3_2 and (s_st_rec3_savt + 10 ns) = Std.Standard.Now ; -- when 2 => correct := correct and s_st_rec3 = c_st_rec3_1 and (s_st_rec3_savt + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00382.P14" , "Multi inertial transactions occurred on " & "concurrent signal asg", correct ) ; -- st_rec3_select <= transport 2 ; -- s_st_rec3 <= -- c_st_rec3_2 after 10 ns , -- c_st_rec3_1 after 20 ns , -- c_st_rec3_2 after 30 ns , -- c_st_rec3_1 after 40 ns ; -- when 3 => correct := s_st_rec3 = c_st_rec3_2 and (s_st_rec3_savt + 10 ns) = Std.Standard.Now ; st_rec3_select <= transport 3 ; -- s_st_rec3 <= -- c_st_rec3_1 after 5 ns ; -- when 4 => correct := correct and s_st_rec3 = c_st_rec3_1 and (s_st_rec3_savt + 5 ns) = Std.Standard.Now ; test_report ( "ARCH00382" , "One inertial transaction occurred on a " & "concurrent signal asg", correct ) ; st_rec3_select <= transport 4 ; -- s_st_rec3 <= -- c_st_rec3_1 after 100 ns ; -- when 5 => correct := correct and s_st_rec3 = c_st_rec3_1 and (s_st_rec3_savt + 100 ns) = Std.Standard.Now ; test_report ( "ARCH00382" , "Old transactions were removed on a " & "concurrent signal asg", correct ) ; st_rec3_select <= transport 5 ; -- s_st_rec3 <= -- c_st_rec3_2 after 10 ns , -- c_st_rec3_1 after 20 ns , -- c_st_rec3_2 after 30 ns , -- c_st_rec3_1 after 40 ns ; -- when 6 => correct := correct and s_st_rec3 = c_st_rec3_2 and (s_st_rec3_savt + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00382" , "One inertial transaction occurred on a " & "concurrent signal asg", correct ) ; st_rec3_select <= transport 6 ; -- Last transaction above is marked -- s_st_rec3 <= -- c_st_rec3_1 after 40 ns ; -- when 7 => correct := correct and s_st_rec3 = c_st_rec3_1 and (s_st_rec3_savt + 30 ns) = Std.Standard.Now ; -- when 8 => correct := correct and s_st_rec3 = c_st_rec3_1 and (s_st_rec3_savt + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00382" , "Inertial semantics check on a concurrent " & "signal asg", correct ) ; -- when others => -- No more transactions should have occurred test_report ( "ARCH00382" , "Inertial semantics check on a concurrent " & "signal asg", false ) ; -- end case ; -- s_st_rec3_savt <= transport Std.Standard.Now ; chk_st_rec3 <= transport s_st_rec3_cnt after (1 us - Std.Standard.Now) ; s_st_rec3_cnt <= transport s_st_rec3_cnt + 1 ; wait until (not s_st_rec3'Quiet) and (s_st_rec3_savt /= Std.Standard.Now) ; -- end process CHG14 ; -- PGEN_CHKP_14 : process ( chk_st_rec3 ) begin if Std.Standard.Now > 0 ns then test_report ( "P14" , "Inertial transactions completed entirely", chk_st_rec3 = 8 ) ; end if ; end process PGEN_CHKP_14 ; -- -- s_st_rec3 <= c_st_rec3_2 after 10 ns, c_st_rec3_1 after 20 ns when st_rec3_select = 1 else -- c_st_rec3_2 after 10 ns , c_st_rec3_1 after 20 ns , c_st_rec3_2 after 30 ns , c_st_rec3_1 after 40 ns when st_rec3_select = 2 else -- c_st_rec3_1 after 5 ns when st_rec3_select = 3 else -- c_st_rec3_1 after 100 ns when st_rec3_select = 4 else -- c_st_rec3_2 after 10 ns , c_st_rec3_1 after 20 ns , c_st_rec3_2 after 30 ns , c_st_rec3_1 after 40 ns when st_rec3_select = 5 else -- -- Last transaction above is marked c_st_rec3_1 after 40 ns ; -- CHG15 : process variable correct : boolean ; begin case s_st_arr1_cnt is when 0 => null ; -- s_st_arr1 <= -- c_st_arr1_2 after 10 ns, -- c_st_arr1_1 after 20 ns ; -- when 1 => correct := s_st_arr1 = c_st_arr1_2 and (s_st_arr1_savt + 10 ns) = Std.Standard.Now ; -- when 2 => correct := correct and s_st_arr1 = c_st_arr1_1 and (s_st_arr1_savt + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00382.P15" , "Multi inertial transactions occurred on " & "concurrent signal asg", correct ) ; -- st_arr1_select <= transport 2 ; -- s_st_arr1 <= -- c_st_arr1_2 after 10 ns , -- c_st_arr1_1 after 20 ns , -- c_st_arr1_2 after 30 ns , -- c_st_arr1_1 after 40 ns ; -- when 3 => correct := s_st_arr1 = c_st_arr1_2 and (s_st_arr1_savt + 10 ns) = Std.Standard.Now ; st_arr1_select <= transport 3 ; -- s_st_arr1 <= -- c_st_arr1_1 after 5 ns ; -- when 4 => correct := correct and s_st_arr1 = c_st_arr1_1 and (s_st_arr1_savt + 5 ns) = Std.Standard.Now ; test_report ( "ARCH00382" , "One inertial transaction occurred on a " & "concurrent signal asg", correct ) ; st_arr1_select <= transport 4 ; -- s_st_arr1 <= -- c_st_arr1_1 after 100 ns ; -- when 5 => correct := correct and s_st_arr1 = c_st_arr1_1 and (s_st_arr1_savt + 100 ns) = Std.Standard.Now ; test_report ( "ARCH00382" , "Old transactions were removed on a " & "concurrent signal asg", correct ) ; st_arr1_select <= transport 5 ; -- s_st_arr1 <= -- c_st_arr1_2 after 10 ns , -- c_st_arr1_1 after 20 ns , -- c_st_arr1_2 after 30 ns , -- c_st_arr1_1 after 40 ns ; -- when 6 => correct := correct and s_st_arr1 = c_st_arr1_2 and (s_st_arr1_savt + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00382" , "One inertial transaction occurred on a " & "concurrent signal asg", correct ) ; st_arr1_select <= transport 6 ; -- Last transaction above is marked -- s_st_arr1 <= -- c_st_arr1_1 after 40 ns ; -- when 7 => correct := correct and s_st_arr1 = c_st_arr1_1 and (s_st_arr1_savt + 30 ns) = Std.Standard.Now ; -- when 8 => correct := correct and s_st_arr1 = c_st_arr1_1 and (s_st_arr1_savt + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00382" , "Inertial semantics check on a concurrent " & "signal asg", correct ) ; -- when others => -- No more transactions should have occurred test_report ( "ARCH00382" , "Inertial semantics check on a concurrent " & "signal asg", false ) ; -- end case ; -- s_st_arr1_savt <= transport Std.Standard.Now ; chk_st_arr1 <= transport s_st_arr1_cnt after (1 us - Std.Standard.Now) ; s_st_arr1_cnt <= transport s_st_arr1_cnt + 1 ; wait until (not s_st_arr1'Quiet) and (s_st_arr1_savt /= Std.Standard.Now) ; -- end process CHG15 ; -- PGEN_CHKP_15 : process ( chk_st_arr1 ) begin if Std.Standard.Now > 0 ns then test_report ( "P15" , "Inertial transactions completed entirely", chk_st_arr1 = 8 ) ; end if ; end process PGEN_CHKP_15 ; -- -- s_st_arr1 <= c_st_arr1_2 after 10 ns, c_st_arr1_1 after 20 ns when st_arr1_select = 1 else -- c_st_arr1_2 after 10 ns , c_st_arr1_1 after 20 ns , c_st_arr1_2 after 30 ns , c_st_arr1_1 after 40 ns when st_arr1_select = 2 else -- c_st_arr1_1 after 5 ns when st_arr1_select = 3 else -- c_st_arr1_1 after 100 ns when st_arr1_select = 4 else -- c_st_arr1_2 after 10 ns , c_st_arr1_1 after 20 ns , c_st_arr1_2 after 30 ns , c_st_arr1_1 after 40 ns when st_arr1_select = 5 else -- -- Last transaction above is marked c_st_arr1_1 after 40 ns ; -- CHG16 : process variable correct : boolean ; begin case s_st_arr2_cnt is when 0 => null ; -- s_st_arr2 <= -- c_st_arr2_2 after 10 ns, -- c_st_arr2_1 after 20 ns ; -- when 1 => correct := s_st_arr2 = c_st_arr2_2 and (s_st_arr2_savt + 10 ns) = Std.Standard.Now ; -- when 2 => correct := correct and s_st_arr2 = c_st_arr2_1 and (s_st_arr2_savt + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00382.P16" , "Multi inertial transactions occurred on " & "concurrent signal asg", correct ) ; -- st_arr2_select <= transport 2 ; -- s_st_arr2 <= -- c_st_arr2_2 after 10 ns , -- c_st_arr2_1 after 20 ns , -- c_st_arr2_2 after 30 ns , -- c_st_arr2_1 after 40 ns ; -- when 3 => correct := s_st_arr2 = c_st_arr2_2 and (s_st_arr2_savt + 10 ns) = Std.Standard.Now ; st_arr2_select <= transport 3 ; -- s_st_arr2 <= -- c_st_arr2_1 after 5 ns ; -- when 4 => correct := correct and s_st_arr2 = c_st_arr2_1 and (s_st_arr2_savt + 5 ns) = Std.Standard.Now ; test_report ( "ARCH00382" , "One inertial transaction occurred on a " & "concurrent signal asg", correct ) ; st_arr2_select <= transport 4 ; -- s_st_arr2 <= -- c_st_arr2_1 after 100 ns ; -- when 5 => correct := correct and s_st_arr2 = c_st_arr2_1 and (s_st_arr2_savt + 100 ns) = Std.Standard.Now ; test_report ( "ARCH00382" , "Old transactions were removed on a " & "concurrent signal asg", correct ) ; st_arr2_select <= transport 5 ; -- s_st_arr2 <= -- c_st_arr2_2 after 10 ns , -- c_st_arr2_1 after 20 ns , -- c_st_arr2_2 after 30 ns , -- c_st_arr2_1 after 40 ns ; -- when 6 => correct := correct and s_st_arr2 = c_st_arr2_2 and (s_st_arr2_savt + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00382" , "One inertial transaction occurred on a " & "concurrent signal asg", correct ) ; st_arr2_select <= transport 6 ; -- Last transaction above is marked -- s_st_arr2 <= -- c_st_arr2_1 after 40 ns ; -- when 7 => correct := correct and s_st_arr2 = c_st_arr2_1 and (s_st_arr2_savt + 30 ns) = Std.Standard.Now ; -- when 8 => correct := correct and s_st_arr2 = c_st_arr2_1 and (s_st_arr2_savt + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00382" , "Inertial semantics check on a concurrent " & "signal asg", correct ) ; -- when others => -- No more transactions should have occurred test_report ( "ARCH00382" , "Inertial semantics check on a concurrent " & "signal asg", false ) ; -- end case ; -- s_st_arr2_savt <= transport Std.Standard.Now ; chk_st_arr2 <= transport s_st_arr2_cnt after (1 us - Std.Standard.Now) ; s_st_arr2_cnt <= transport s_st_arr2_cnt + 1 ; wait until (not s_st_arr2'Quiet) and (s_st_arr2_savt /= Std.Standard.Now) ; -- end process CHG16 ; -- PGEN_CHKP_16 : process ( chk_st_arr2 ) begin if Std.Standard.Now > 0 ns then test_report ( "P16" , "Inertial transactions completed entirely", chk_st_arr2 = 8 ) ; end if ; end process PGEN_CHKP_16 ; -- -- s_st_arr2 <= c_st_arr2_2 after 10 ns, c_st_arr2_1 after 20 ns when st_arr2_select = 1 else -- c_st_arr2_2 after 10 ns , c_st_arr2_1 after 20 ns , c_st_arr2_2 after 30 ns , c_st_arr2_1 after 40 ns when st_arr2_select = 2 else -- c_st_arr2_1 after 5 ns when st_arr2_select = 3 else -- c_st_arr2_1 after 100 ns when st_arr2_select = 4 else -- c_st_arr2_2 after 10 ns , c_st_arr2_1 after 20 ns , c_st_arr2_2 after 30 ns , c_st_arr2_1 after 40 ns when st_arr2_select = 5 else -- -- Last transaction above is marked c_st_arr2_1 after 40 ns ; -- CHG17 : process variable correct : boolean ; begin case s_st_arr3_cnt is when 0 => null ; -- s_st_arr3 <= -- c_st_arr3_2 after 10 ns, -- c_st_arr3_1 after 20 ns ; -- when 1 => correct := s_st_arr3 = c_st_arr3_2 and (s_st_arr3_savt + 10 ns) = Std.Standard.Now ; -- when 2 => correct := correct and s_st_arr3 = c_st_arr3_1 and (s_st_arr3_savt + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00382.P17" , "Multi inertial transactions occurred on " & "concurrent signal asg", correct ) ; -- st_arr3_select <= transport 2 ; -- s_st_arr3 <= -- c_st_arr3_2 after 10 ns , -- c_st_arr3_1 after 20 ns , -- c_st_arr3_2 after 30 ns , -- c_st_arr3_1 after 40 ns ; -- when 3 => correct := s_st_arr3 = c_st_arr3_2 and (s_st_arr3_savt + 10 ns) = Std.Standard.Now ; st_arr3_select <= transport 3 ; -- s_st_arr3 <= -- c_st_arr3_1 after 5 ns ; -- when 4 => correct := correct and s_st_arr3 = c_st_arr3_1 and (s_st_arr3_savt + 5 ns) = Std.Standard.Now ; test_report ( "ARCH00382" , "One inertial transaction occurred on a " & "concurrent signal asg", correct ) ; st_arr3_select <= transport 4 ; -- s_st_arr3 <= -- c_st_arr3_1 after 100 ns ; -- when 5 => correct := correct and s_st_arr3 = c_st_arr3_1 and (s_st_arr3_savt + 100 ns) = Std.Standard.Now ; test_report ( "ARCH00382" , "Old transactions were removed on a " & "concurrent signal asg", correct ) ; st_arr3_select <= transport 5 ; -- s_st_arr3 <= -- c_st_arr3_2 after 10 ns , -- c_st_arr3_1 after 20 ns , -- c_st_arr3_2 after 30 ns , -- c_st_arr3_1 after 40 ns ; -- when 6 => correct := correct and s_st_arr3 = c_st_arr3_2 and (s_st_arr3_savt + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00382" , "One inertial transaction occurred on a " & "concurrent signal asg", correct ) ; st_arr3_select <= transport 6 ; -- Last transaction above is marked -- s_st_arr3 <= -- c_st_arr3_1 after 40 ns ; -- when 7 => correct := correct and s_st_arr3 = c_st_arr3_1 and (s_st_arr3_savt + 30 ns) = Std.Standard.Now ; -- when 8 => correct := correct and s_st_arr3 = c_st_arr3_1 and (s_st_arr3_savt + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00382" , "Inertial semantics check on a concurrent " & "signal asg", correct ) ; -- when others => -- No more transactions should have occurred test_report ( "ARCH00382" , "Inertial semantics check on a concurrent " & "signal asg", false ) ; -- end case ; -- s_st_arr3_savt <= transport Std.Standard.Now ; chk_st_arr3 <= transport s_st_arr3_cnt after (1 us - Std.Standard.Now) ; s_st_arr3_cnt <= transport s_st_arr3_cnt + 1 ; wait until (not s_st_arr3'Quiet) and (s_st_arr3_savt /= Std.Standard.Now) ; -- end process CHG17 ; -- PGEN_CHKP_17 : process ( chk_st_arr3 ) begin if Std.Standard.Now > 0 ns then test_report ( "P17" , "Inertial transactions completed entirely", chk_st_arr3 = 8 ) ; end if ; end process PGEN_CHKP_17 ; -- -- s_st_arr3 <= c_st_arr3_2 after 10 ns, c_st_arr3_1 after 20 ns when st_arr3_select = 1 else -- c_st_arr3_2 after 10 ns , c_st_arr3_1 after 20 ns , c_st_arr3_2 after 30 ns , c_st_arr3_1 after 40 ns when st_arr3_select = 2 else -- c_st_arr3_1 after 5 ns when st_arr3_select = 3 else -- c_st_arr3_1 after 100 ns when st_arr3_select = 4 else -- c_st_arr3_2 after 10 ns , c_st_arr3_1 after 20 ns , c_st_arr3_2 after 30 ns , c_st_arr3_1 after 40 ns when st_arr3_select = 5 else -- -- Last transaction above is marked c_st_arr3_1 after 40 ns ; -- end ARCH00382 ; -- -- use WORK.STANDARD_TYPES.all ; entity ENT00382_Test_Bench is end ENT00382_Test_Bench ; -- -- architecture ARCH00382_Test_Bench of ENT00382_Test_Bench is begin L1: block component UUT end component ; -- for CIS1 : UUT use entity WORK.ENT00382 ( ARCH00382 ) ; begin CIS1 : UUT ; end block L1 ; end ARCH00382_Test_Bench ;
gpl-3.0
3a6731d4a0da9d8679d56120689bd8bc
0.471064
3.817965
false
false
false
false
grwlf/vsim
vhdl_ct/ct00048.vhd
1
52,737
-- NEED RESULT: ARCH00048.P1: Implicit array subtype conversion occurs for slices passed -- NEED RESULT: ARCH00048.P2: Implicit array subtype conversion occurs for slices passed -- NEED RESULT: ARCH00048.P3: Implicit array subtype conversion occurs for slices passed -- NEED RESULT: ARCH00048.P4: Implicit array subtype conversion occurs for slices passed ------------------------------------------------------------------------------- -- -- Copyright (c) 1989 by Intermetrics, Inc. -- All rights reserved. -- ------------------------------------------------------------------------------- -- -- TEST NAME: -- -- CT00048 -- -- AUTHOR: -- -- G. Tominovich -- -- TEST OBJECTIVES: -- -- 8.4 (2) -- 8.4.1 (1) -- -- DESIGN UNIT ORDERING: -- -- E00000(ARCH00048) -- ENT00048_Test_Bench(ARCH00048_Test_Bench) -- -- REVISION HISTORY: -- -- 29-JUN-1987 - initial revision -- -- NOTES: -- -- self-checking -- automatically generated -- use WORK.STANDARD_TYPES.all ; architecture ARCH00048 of E00000 is signal Dummy : Boolean := false ; -- begin P1 : process ( Dummy ) subtype boolean_vector_range_1 is integer range lowb+1 to highb+1 ; subtype boolean_vector_sr_1 is integer range lowb+2 to highb ; subtype boolean_vector_sr_2 is integer range lowb+1 to highb-1 ; subtype st_boolean_vector_1 is boolean_vector (boolean_vector_range_1) ; variable v_st_boolean_vector_1 : st_boolean_vector_1 := c_st_boolean_vector_1 ; -- subtype bit_vector_range_1 is integer range lowb+1 to highb+1 ; subtype bit_vector_sr_1 is integer range lowb+2 to highb ; subtype bit_vector_sr_2 is integer range lowb+1 to highb-1 ; subtype st_bit_vector_1 is bit_vector (bit_vector_range_1) ; variable v_st_bit_vector_1 : st_bit_vector_1 := c_st_bit_vector_1 ; -- subtype severity_level_vector_range_1 is integer range lowb+1 to highb+1 ; subtype severity_level_vector_sr_1 is integer range lowb+2 to highb ; subtype severity_level_vector_sr_2 is integer range lowb+1 to highb-1 ; subtype st_severity_level_vector_1 is severity_level_vector (severity_level_vector_range_1) ; variable v_st_severity_level_vector_1 : st_severity_level_vector_1 := c_st_severity_level_vector_1 ; -- subtype string_range_1 is integer range lowb+1 to highb+1 ; subtype string_sr_1 is integer range lowb+2 to highb ; subtype string_sr_2 is integer range lowb+1 to highb-1 ; subtype st_string_1 is string (string_range_1) ; variable v_st_string_1 : st_string_1 := c_st_string_1 ; -- subtype enum1_vector_range_1 is integer range lowb+1 to highb+1 ; subtype enum1_vector_sr_1 is integer range lowb+2 to highb ; subtype enum1_vector_sr_2 is integer range lowb+1 to highb-1 ; subtype st_enum1_vector_1 is enum1_vector (enum1_vector_range_1) ; variable v_st_enum1_vector_1 : st_enum1_vector_1 := c_st_enum1_vector_1 ; -- subtype integer_vector_range_1 is integer range lowb+1 to highb+1 ; subtype integer_vector_sr_1 is integer range lowb+2 to highb ; subtype integer_vector_sr_2 is integer range lowb+1 to highb-1 ; subtype st_integer_vector_1 is integer_vector (integer_vector_range_1) ; variable v_st_integer_vector_1 : st_integer_vector_1 := c_st_integer_vector_1 ; -- subtype int1_vector_range_1 is integer range lowb+1 to highb+1 ; subtype int1_vector_sr_1 is integer range lowb+2 to highb ; subtype int1_vector_sr_2 is integer range lowb+1 to highb-1 ; subtype st_int1_vector_1 is int1_vector (int1_vector_range_1) ; variable v_st_int1_vector_1 : st_int1_vector_1 := c_st_int1_vector_1 ; -- subtype time_vector_range_1 is integer range lowb+1 to highb+1 ; subtype time_vector_sr_1 is integer range lowb+2 to highb ; subtype time_vector_sr_2 is integer range lowb+1 to highb-1 ; subtype st_time_vector_1 is time_vector (time_vector_range_1) ; variable v_st_time_vector_1 : st_time_vector_1 := c_st_time_vector_1 ; -- subtype phys1_vector_range_1 is integer range lowb+1 to highb+1 ; subtype phys1_vector_sr_1 is integer range lowb+2 to highb ; subtype phys1_vector_sr_2 is integer range lowb+1 to highb-1 ; subtype st_phys1_vector_1 is phys1_vector (phys1_vector_range_1) ; variable v_st_phys1_vector_1 : st_phys1_vector_1 := c_st_phys1_vector_1 ; -- subtype real_vector_range_1 is integer range lowb+1 to highb+1 ; subtype real_vector_sr_1 is integer range lowb+2 to highb ; subtype real_vector_sr_2 is integer range lowb+1 to highb-1 ; subtype st_real_vector_1 is real_vector (real_vector_range_1) ; variable v_st_real_vector_1 : st_real_vector_1 := c_st_real_vector_1 ; -- subtype real1_vector_range_1 is integer range lowb+1 to highb+1 ; subtype real1_vector_sr_1 is integer range lowb+2 to highb ; subtype real1_vector_sr_2 is integer range lowb+1 to highb-1 ; subtype st_real1_vector_1 is real1_vector (real1_vector_range_1) ; variable v_st_real1_vector_1 : st_real1_vector_1 := c_st_real1_vector_1 ; -- subtype rec1_vector_range_1 is integer range lowb+1 to highb+1 ; subtype rec1_vector_sr_1 is integer range lowb+2 to highb ; subtype rec1_vector_sr_2 is integer range lowb+1 to highb-1 ; subtype st_rec1_vector_1 is rec1_vector (rec1_vector_range_1) ; variable v_st_rec1_vector_1 : st_rec1_vector_1 := c_st_rec1_vector_1 ; -- subtype rec2_vector_range_1 is integer range lowb+1 to highb+1 ; subtype rec2_vector_sr_1 is integer range lowb+2 to highb ; subtype rec2_vector_sr_2 is integer range lowb+1 to highb-1 ; subtype st_rec2_vector_1 is rec2_vector (rec2_vector_range_1) ; variable v_st_rec2_vector_1 : st_rec2_vector_1 := c_st_rec2_vector_1 ; -- subtype rec3_vector_range_1 is integer range lowb+1 to highb+1 ; subtype rec3_vector_sr_1 is integer range lowb+2 to highb ; subtype rec3_vector_sr_2 is integer range lowb+1 to highb-1 ; subtype st_rec3_vector_1 is rec3_vector (rec3_vector_range_1) ; variable v_st_rec3_vector_1 : st_rec3_vector_1 := c_st_rec3_vector_1 ; -- subtype arr1_vector_range_1 is integer range lowb+1 to highb+1 ; subtype arr1_vector_sr_1 is integer range lowb+2 to highb ; subtype arr1_vector_sr_2 is integer range lowb+1 to highb-1 ; subtype st_arr1_vector_1 is arr1_vector (arr1_vector_range_1) ; variable v_st_arr1_vector_1 : st_arr1_vector_1 := c_st_arr1_vector_1 ; -- subtype arr2_vector_range_1 is integer range lowb+1 to highb+1 ; subtype arr2_vector_sr_1 is integer range lowb+2 to highb ; subtype arr2_vector_sr_2 is integer range lowb+1 to highb-1 ; subtype st_arr2_vector_1 is arr2_vector (arr2_vector_range_1) ; variable v_st_arr2_vector_1 : st_arr2_vector_1 := c_st_arr2_vector_1 ; -- subtype arr3_vector_range_1 is integer range lowb+1 to highb+1 ; subtype arr3_vector_sr_1 is integer range lowb+2 to highb ; subtype arr3_vector_sr_2 is integer range lowb+1 to highb-1 ; subtype st_arr3_vector_1 is arr3_vector (arr3_vector_range_1) ; variable v_st_arr3_vector_1 : st_arr3_vector_1 := c_st_arr3_vector_1 ; -- -- variable correct : boolean := true ; begin v_st_boolean_vector_1 (boolean_vector_sr_1) := c_st_boolean_vector_2 (boolean_vector_sr_2) ; v_st_bit_vector_1 (bit_vector_sr_1) := c_st_bit_vector_2 (bit_vector_sr_2) ; v_st_severity_level_vector_1 (severity_level_vector_sr_1) := c_st_severity_level_vector_2 (severity_level_vector_sr_2) ; v_st_string_1 (string_sr_1) := c_st_string_2 (string_sr_2) ; v_st_enum1_vector_1 (enum1_vector_sr_1) := c_st_enum1_vector_2 (enum1_vector_sr_2) ; v_st_integer_vector_1 (integer_vector_sr_1) := c_st_integer_vector_2 (integer_vector_sr_2) ; v_st_int1_vector_1 (int1_vector_sr_1) := c_st_int1_vector_2 (int1_vector_sr_2) ; v_st_time_vector_1 (time_vector_sr_1) := c_st_time_vector_2 (time_vector_sr_2) ; v_st_phys1_vector_1 (phys1_vector_sr_1) := c_st_phys1_vector_2 (phys1_vector_sr_2) ; v_st_real_vector_1 (real_vector_sr_1) := c_st_real_vector_2 (real_vector_sr_2) ; v_st_real1_vector_1 (real1_vector_sr_1) := c_st_real1_vector_2 (real1_vector_sr_2) ; v_st_rec1_vector_1 (rec1_vector_sr_1) := c_st_rec1_vector_2 (rec1_vector_sr_2) ; v_st_rec2_vector_1 (rec2_vector_sr_1) := c_st_rec2_vector_2 (rec2_vector_sr_2) ; v_st_rec3_vector_1 (rec3_vector_sr_1) := c_st_rec3_vector_2 (rec3_vector_sr_2) ; v_st_arr1_vector_1 (arr1_vector_sr_1) := c_st_arr1_vector_2 (arr1_vector_sr_2) ; v_st_arr2_vector_1 (arr2_vector_sr_1) := c_st_arr2_vector_2 (arr2_vector_sr_2) ; v_st_arr3_vector_1 (arr3_vector_sr_1) := c_st_arr3_vector_2 (arr3_vector_sr_2) ; -- correct := correct and v_st_boolean_vector_1 (boolean_vector_sr_1) = c_st_boolean_vector_2 (boolean_vector_sr_2) ; correct := correct and v_st_bit_vector_1 (bit_vector_sr_1) = c_st_bit_vector_2 (bit_vector_sr_2) ; correct := correct and v_st_severity_level_vector_1 (severity_level_vector_sr_1) = c_st_severity_level_vector_2 (severity_level_vector_sr_2) ; correct := correct and v_st_string_1 (string_sr_1) = c_st_string_2 (string_sr_2) ; correct := correct and v_st_enum1_vector_1 (enum1_vector_sr_1) = c_st_enum1_vector_2 (enum1_vector_sr_2) ; correct := correct and v_st_integer_vector_1 (integer_vector_sr_1) = c_st_integer_vector_2 (integer_vector_sr_2) ; correct := correct and v_st_int1_vector_1 (int1_vector_sr_1) = c_st_int1_vector_2 (int1_vector_sr_2) ; correct := correct and v_st_time_vector_1 (time_vector_sr_1) = c_st_time_vector_2 (time_vector_sr_2) ; correct := correct and v_st_phys1_vector_1 (phys1_vector_sr_1) = c_st_phys1_vector_2 (phys1_vector_sr_2) ; correct := correct and v_st_real_vector_1 (real_vector_sr_1) = c_st_real_vector_2 (real_vector_sr_2) ; correct := correct and v_st_real1_vector_1 (real1_vector_sr_1) = c_st_real1_vector_2 (real1_vector_sr_2) ; correct := correct and v_st_rec1_vector_1 (rec1_vector_sr_1) = c_st_rec1_vector_2 (rec1_vector_sr_2) ; correct := correct and v_st_rec2_vector_1 (rec2_vector_sr_1) = c_st_rec2_vector_2 (rec2_vector_sr_2) ; correct := correct and v_st_rec3_vector_1 (rec3_vector_sr_1) = c_st_rec3_vector_2 (rec3_vector_sr_2) ; correct := correct and v_st_arr1_vector_1 (arr1_vector_sr_1) = c_st_arr1_vector_2 (arr1_vector_sr_2) ; correct := correct and v_st_arr2_vector_1 (arr2_vector_sr_1) = c_st_arr2_vector_2 (arr2_vector_sr_2) ; correct := correct and v_st_arr3_vector_1 (arr3_vector_sr_1) = c_st_arr3_vector_2 (arr3_vector_sr_2) ; -- test_report ( "ARCH00048.P1" , "Implicit array subtype conversion occurs "& "for slices", correct) ; end process P1 ; -- P2 : process ( Dummy ) variable correct : boolean := true ; -- procedure Proc1 is subtype boolean_vector_range_1 is integer range lowb+1 to highb+1 ; subtype boolean_vector_sr_1 is integer range lowb+2 to highb ; subtype boolean_vector_sr_2 is integer range lowb+1 to highb-1 ; subtype st_boolean_vector_1 is boolean_vector (boolean_vector_range_1) ; variable v_st_boolean_vector_1 : st_boolean_vector_1 := c_st_boolean_vector_1 ; -- subtype bit_vector_range_1 is integer range lowb+1 to highb+1 ; subtype bit_vector_sr_1 is integer range lowb+2 to highb ; subtype bit_vector_sr_2 is integer range lowb+1 to highb-1 ; subtype st_bit_vector_1 is bit_vector (bit_vector_range_1) ; variable v_st_bit_vector_1 : st_bit_vector_1 := c_st_bit_vector_1 ; -- subtype severity_level_vector_range_1 is integer range lowb+1 to highb+1 ; subtype severity_level_vector_sr_1 is integer range lowb+2 to highb ; subtype severity_level_vector_sr_2 is integer range lowb+1 to highb-1 ; subtype st_severity_level_vector_1 is severity_level_vector (severity_level_vector_range_1) ; variable v_st_severity_level_vector_1 : st_severity_level_vector_1 := c_st_severity_level_vector_1 ; -- subtype string_range_1 is integer range lowb+1 to highb+1 ; subtype string_sr_1 is integer range lowb+2 to highb ; subtype string_sr_2 is integer range lowb+1 to highb-1 ; subtype st_string_1 is string (string_range_1) ; variable v_st_string_1 : st_string_1 := c_st_string_1 ; -- subtype enum1_vector_range_1 is integer range lowb+1 to highb+1 ; subtype enum1_vector_sr_1 is integer range lowb+2 to highb ; subtype enum1_vector_sr_2 is integer range lowb+1 to highb-1 ; subtype st_enum1_vector_1 is enum1_vector (enum1_vector_range_1) ; variable v_st_enum1_vector_1 : st_enum1_vector_1 := c_st_enum1_vector_1 ; -- subtype integer_vector_range_1 is integer range lowb+1 to highb+1 ; subtype integer_vector_sr_1 is integer range lowb+2 to highb ; subtype integer_vector_sr_2 is integer range lowb+1 to highb-1 ; subtype st_integer_vector_1 is integer_vector (integer_vector_range_1) ; variable v_st_integer_vector_1 : st_integer_vector_1 := c_st_integer_vector_1 ; -- subtype int1_vector_range_1 is integer range lowb+1 to highb+1 ; subtype int1_vector_sr_1 is integer range lowb+2 to highb ; subtype int1_vector_sr_2 is integer range lowb+1 to highb-1 ; subtype st_int1_vector_1 is int1_vector (int1_vector_range_1) ; variable v_st_int1_vector_1 : st_int1_vector_1 := c_st_int1_vector_1 ; -- subtype time_vector_range_1 is integer range lowb+1 to highb+1 ; subtype time_vector_sr_1 is integer range lowb+2 to highb ; subtype time_vector_sr_2 is integer range lowb+1 to highb-1 ; subtype st_time_vector_1 is time_vector (time_vector_range_1) ; variable v_st_time_vector_1 : st_time_vector_1 := c_st_time_vector_1 ; -- subtype phys1_vector_range_1 is integer range lowb+1 to highb+1 ; subtype phys1_vector_sr_1 is integer range lowb+2 to highb ; subtype phys1_vector_sr_2 is integer range lowb+1 to highb-1 ; subtype st_phys1_vector_1 is phys1_vector (phys1_vector_range_1) ; variable v_st_phys1_vector_1 : st_phys1_vector_1 := c_st_phys1_vector_1 ; -- subtype real_vector_range_1 is integer range lowb+1 to highb+1 ; subtype real_vector_sr_1 is integer range lowb+2 to highb ; subtype real_vector_sr_2 is integer range lowb+1 to highb-1 ; subtype st_real_vector_1 is real_vector (real_vector_range_1) ; variable v_st_real_vector_1 : st_real_vector_1 := c_st_real_vector_1 ; -- subtype real1_vector_range_1 is integer range lowb+1 to highb+1 ; subtype real1_vector_sr_1 is integer range lowb+2 to highb ; subtype real1_vector_sr_2 is integer range lowb+1 to highb-1 ; subtype st_real1_vector_1 is real1_vector (real1_vector_range_1) ; variable v_st_real1_vector_1 : st_real1_vector_1 := c_st_real1_vector_1 ; -- subtype rec1_vector_range_1 is integer range lowb+1 to highb+1 ; subtype rec1_vector_sr_1 is integer range lowb+2 to highb ; subtype rec1_vector_sr_2 is integer range lowb+1 to highb-1 ; subtype st_rec1_vector_1 is rec1_vector (rec1_vector_range_1) ; variable v_st_rec1_vector_1 : st_rec1_vector_1 := c_st_rec1_vector_1 ; -- subtype rec2_vector_range_1 is integer range lowb+1 to highb+1 ; subtype rec2_vector_sr_1 is integer range lowb+2 to highb ; subtype rec2_vector_sr_2 is integer range lowb+1 to highb-1 ; subtype st_rec2_vector_1 is rec2_vector (rec2_vector_range_1) ; variable v_st_rec2_vector_1 : st_rec2_vector_1 := c_st_rec2_vector_1 ; -- subtype rec3_vector_range_1 is integer range lowb+1 to highb+1 ; subtype rec3_vector_sr_1 is integer range lowb+2 to highb ; subtype rec3_vector_sr_2 is integer range lowb+1 to highb-1 ; subtype st_rec3_vector_1 is rec3_vector (rec3_vector_range_1) ; variable v_st_rec3_vector_1 : st_rec3_vector_1 := c_st_rec3_vector_1 ; -- subtype arr1_vector_range_1 is integer range lowb+1 to highb+1 ; subtype arr1_vector_sr_1 is integer range lowb+2 to highb ; subtype arr1_vector_sr_2 is integer range lowb+1 to highb-1 ; subtype st_arr1_vector_1 is arr1_vector (arr1_vector_range_1) ; variable v_st_arr1_vector_1 : st_arr1_vector_1 := c_st_arr1_vector_1 ; -- subtype arr2_vector_range_1 is integer range lowb+1 to highb+1 ; subtype arr2_vector_sr_1 is integer range lowb+2 to highb ; subtype arr2_vector_sr_2 is integer range lowb+1 to highb-1 ; subtype st_arr2_vector_1 is arr2_vector (arr2_vector_range_1) ; variable v_st_arr2_vector_1 : st_arr2_vector_1 := c_st_arr2_vector_1 ; -- subtype arr3_vector_range_1 is integer range lowb+1 to highb+1 ; subtype arr3_vector_sr_1 is integer range lowb+2 to highb ; subtype arr3_vector_sr_2 is integer range lowb+1 to highb-1 ; subtype st_arr3_vector_1 is arr3_vector (arr3_vector_range_1) ; variable v_st_arr3_vector_1 : st_arr3_vector_1 := c_st_arr3_vector_1 ; -- -- begin v_st_boolean_vector_1 (boolean_vector_sr_1) := c_st_boolean_vector_2 (boolean_vector_sr_2) ; v_st_bit_vector_1 (bit_vector_sr_1) := c_st_bit_vector_2 (bit_vector_sr_2) ; v_st_severity_level_vector_1 (severity_level_vector_sr_1) := c_st_severity_level_vector_2 (severity_level_vector_sr_2) ; v_st_string_1 (string_sr_1) := c_st_string_2 (string_sr_2) ; v_st_enum1_vector_1 (enum1_vector_sr_1) := c_st_enum1_vector_2 (enum1_vector_sr_2) ; v_st_integer_vector_1 (integer_vector_sr_1) := c_st_integer_vector_2 (integer_vector_sr_2) ; v_st_int1_vector_1 (int1_vector_sr_1) := c_st_int1_vector_2 (int1_vector_sr_2) ; v_st_time_vector_1 (time_vector_sr_1) := c_st_time_vector_2 (time_vector_sr_2) ; v_st_phys1_vector_1 (phys1_vector_sr_1) := c_st_phys1_vector_2 (phys1_vector_sr_2) ; v_st_real_vector_1 (real_vector_sr_1) := c_st_real_vector_2 (real_vector_sr_2) ; v_st_real1_vector_1 (real1_vector_sr_1) := c_st_real1_vector_2 (real1_vector_sr_2) ; v_st_rec1_vector_1 (rec1_vector_sr_1) := c_st_rec1_vector_2 (rec1_vector_sr_2) ; v_st_rec2_vector_1 (rec2_vector_sr_1) := c_st_rec2_vector_2 (rec2_vector_sr_2) ; v_st_rec3_vector_1 (rec3_vector_sr_1) := c_st_rec3_vector_2 (rec3_vector_sr_2) ; v_st_arr1_vector_1 (arr1_vector_sr_1) := c_st_arr1_vector_2 (arr1_vector_sr_2) ; v_st_arr2_vector_1 (arr2_vector_sr_1) := c_st_arr2_vector_2 (arr2_vector_sr_2) ; v_st_arr3_vector_1 (arr3_vector_sr_1) := c_st_arr3_vector_2 (arr3_vector_sr_2) ; -- correct := correct and v_st_boolean_vector_1 (boolean_vector_sr_1) = c_st_boolean_vector_2 (boolean_vector_sr_2) ; correct := correct and v_st_bit_vector_1 (bit_vector_sr_1) = c_st_bit_vector_2 (bit_vector_sr_2) ; correct := correct and v_st_severity_level_vector_1 (severity_level_vector_sr_1) = c_st_severity_level_vector_2 (severity_level_vector_sr_2) ; correct := correct and v_st_string_1 (string_sr_1) = c_st_string_2 (string_sr_2) ; correct := correct and v_st_enum1_vector_1 (enum1_vector_sr_1) = c_st_enum1_vector_2 (enum1_vector_sr_2) ; correct := correct and v_st_integer_vector_1 (integer_vector_sr_1) = c_st_integer_vector_2 (integer_vector_sr_2) ; correct := correct and v_st_int1_vector_1 (int1_vector_sr_1) = c_st_int1_vector_2 (int1_vector_sr_2) ; correct := correct and v_st_time_vector_1 (time_vector_sr_1) = c_st_time_vector_2 (time_vector_sr_2) ; correct := correct and v_st_phys1_vector_1 (phys1_vector_sr_1) = c_st_phys1_vector_2 (phys1_vector_sr_2) ; correct := correct and v_st_real_vector_1 (real_vector_sr_1) = c_st_real_vector_2 (real_vector_sr_2) ; correct := correct and v_st_real1_vector_1 (real1_vector_sr_1) = c_st_real1_vector_2 (real1_vector_sr_2) ; correct := correct and v_st_rec1_vector_1 (rec1_vector_sr_1) = c_st_rec1_vector_2 (rec1_vector_sr_2) ; correct := correct and v_st_rec2_vector_1 (rec2_vector_sr_1) = c_st_rec2_vector_2 (rec2_vector_sr_2) ; correct := correct and v_st_rec3_vector_1 (rec3_vector_sr_1) = c_st_rec3_vector_2 (rec3_vector_sr_2) ; correct := correct and v_st_arr1_vector_1 (arr1_vector_sr_1) = c_st_arr1_vector_2 (arr1_vector_sr_2) ; correct := correct and v_st_arr2_vector_1 (arr2_vector_sr_1) = c_st_arr2_vector_2 (arr2_vector_sr_2) ; correct := correct and v_st_arr3_vector_1 (arr3_vector_sr_1) = c_st_arr3_vector_2 (arr3_vector_sr_2) ; -- end Proc1 ; begin Proc1 ; test_report ( "ARCH00048.P2" , "Implicit array subtype conversion occurs "& "for slices", correct) ; end process P2 ; -- P3 : process ( Dummy ) subtype boolean_vector_range_1 is integer range lowb+1 to highb+1 ; subtype boolean_vector_sr_1 is integer range lowb+2 to highb ; subtype boolean_vector_sr_2 is integer range lowb+1 to highb-1 ; subtype st_boolean_vector_1 is boolean_vector (boolean_vector_range_1) ; variable v_st_boolean_vector_1 : st_boolean_vector_1 := c_st_boolean_vector_1 ; -- subtype bit_vector_range_1 is integer range lowb+1 to highb+1 ; subtype bit_vector_sr_1 is integer range lowb+2 to highb ; subtype bit_vector_sr_2 is integer range lowb+1 to highb-1 ; subtype st_bit_vector_1 is bit_vector (bit_vector_range_1) ; variable v_st_bit_vector_1 : st_bit_vector_1 := c_st_bit_vector_1 ; -- subtype severity_level_vector_range_1 is integer range lowb+1 to highb+1 ; subtype severity_level_vector_sr_1 is integer range lowb+2 to highb ; subtype severity_level_vector_sr_2 is integer range lowb+1 to highb-1 ; subtype st_severity_level_vector_1 is severity_level_vector (severity_level_vector_range_1) ; variable v_st_severity_level_vector_1 : st_severity_level_vector_1 := c_st_severity_level_vector_1 ; -- subtype string_range_1 is integer range lowb+1 to highb+1 ; subtype string_sr_1 is integer range lowb+2 to highb ; subtype string_sr_2 is integer range lowb+1 to highb-1 ; subtype st_string_1 is string (string_range_1) ; variable v_st_string_1 : st_string_1 := c_st_string_1 ; -- subtype enum1_vector_range_1 is integer range lowb+1 to highb+1 ; subtype enum1_vector_sr_1 is integer range lowb+2 to highb ; subtype enum1_vector_sr_2 is integer range lowb+1 to highb-1 ; subtype st_enum1_vector_1 is enum1_vector (enum1_vector_range_1) ; variable v_st_enum1_vector_1 : st_enum1_vector_1 := c_st_enum1_vector_1 ; -- subtype integer_vector_range_1 is integer range lowb+1 to highb+1 ; subtype integer_vector_sr_1 is integer range lowb+2 to highb ; subtype integer_vector_sr_2 is integer range lowb+1 to highb-1 ; subtype st_integer_vector_1 is integer_vector (integer_vector_range_1) ; variable v_st_integer_vector_1 : st_integer_vector_1 := c_st_integer_vector_1 ; -- subtype int1_vector_range_1 is integer range lowb+1 to highb+1 ; subtype int1_vector_sr_1 is integer range lowb+2 to highb ; subtype int1_vector_sr_2 is integer range lowb+1 to highb-1 ; subtype st_int1_vector_1 is int1_vector (int1_vector_range_1) ; variable v_st_int1_vector_1 : st_int1_vector_1 := c_st_int1_vector_1 ; -- subtype time_vector_range_1 is integer range lowb+1 to highb+1 ; subtype time_vector_sr_1 is integer range lowb+2 to highb ; subtype time_vector_sr_2 is integer range lowb+1 to highb-1 ; subtype st_time_vector_1 is time_vector (time_vector_range_1) ; variable v_st_time_vector_1 : st_time_vector_1 := c_st_time_vector_1 ; -- subtype phys1_vector_range_1 is integer range lowb+1 to highb+1 ; subtype phys1_vector_sr_1 is integer range lowb+2 to highb ; subtype phys1_vector_sr_2 is integer range lowb+1 to highb-1 ; subtype st_phys1_vector_1 is phys1_vector (phys1_vector_range_1) ; variable v_st_phys1_vector_1 : st_phys1_vector_1 := c_st_phys1_vector_1 ; -- subtype real_vector_range_1 is integer range lowb+1 to highb+1 ; subtype real_vector_sr_1 is integer range lowb+2 to highb ; subtype real_vector_sr_2 is integer range lowb+1 to highb-1 ; subtype st_real_vector_1 is real_vector (real_vector_range_1) ; variable v_st_real_vector_1 : st_real_vector_1 := c_st_real_vector_1 ; -- subtype real1_vector_range_1 is integer range lowb+1 to highb+1 ; subtype real1_vector_sr_1 is integer range lowb+2 to highb ; subtype real1_vector_sr_2 is integer range lowb+1 to highb-1 ; subtype st_real1_vector_1 is real1_vector (real1_vector_range_1) ; variable v_st_real1_vector_1 : st_real1_vector_1 := c_st_real1_vector_1 ; -- subtype rec1_vector_range_1 is integer range lowb+1 to highb+1 ; subtype rec1_vector_sr_1 is integer range lowb+2 to highb ; subtype rec1_vector_sr_2 is integer range lowb+1 to highb-1 ; subtype st_rec1_vector_1 is rec1_vector (rec1_vector_range_1) ; variable v_st_rec1_vector_1 : st_rec1_vector_1 := c_st_rec1_vector_1 ; -- subtype rec2_vector_range_1 is integer range lowb+1 to highb+1 ; subtype rec2_vector_sr_1 is integer range lowb+2 to highb ; subtype rec2_vector_sr_2 is integer range lowb+1 to highb-1 ; subtype st_rec2_vector_1 is rec2_vector (rec2_vector_range_1) ; variable v_st_rec2_vector_1 : st_rec2_vector_1 := c_st_rec2_vector_1 ; -- subtype rec3_vector_range_1 is integer range lowb+1 to highb+1 ; subtype rec3_vector_sr_1 is integer range lowb+2 to highb ; subtype rec3_vector_sr_2 is integer range lowb+1 to highb-1 ; subtype st_rec3_vector_1 is rec3_vector (rec3_vector_range_1) ; variable v_st_rec3_vector_1 : st_rec3_vector_1 := c_st_rec3_vector_1 ; -- subtype arr1_vector_range_1 is integer range lowb+1 to highb+1 ; subtype arr1_vector_sr_1 is integer range lowb+2 to highb ; subtype arr1_vector_sr_2 is integer range lowb+1 to highb-1 ; subtype st_arr1_vector_1 is arr1_vector (arr1_vector_range_1) ; variable v_st_arr1_vector_1 : st_arr1_vector_1 := c_st_arr1_vector_1 ; -- subtype arr2_vector_range_1 is integer range lowb+1 to highb+1 ; subtype arr2_vector_sr_1 is integer range lowb+2 to highb ; subtype arr2_vector_sr_2 is integer range lowb+1 to highb-1 ; subtype st_arr2_vector_1 is arr2_vector (arr2_vector_range_1) ; variable v_st_arr2_vector_1 : st_arr2_vector_1 := c_st_arr2_vector_1 ; -- subtype arr3_vector_range_1 is integer range lowb+1 to highb+1 ; subtype arr3_vector_sr_1 is integer range lowb+2 to highb ; subtype arr3_vector_sr_2 is integer range lowb+1 to highb-1 ; subtype st_arr3_vector_1 is arr3_vector (arr3_vector_range_1) ; variable v_st_arr3_vector_1 : st_arr3_vector_1 := c_st_arr3_vector_1 ; -- -- variable correct : boolean := true ; -- procedure Proc1 is begin v_st_boolean_vector_1 (boolean_vector_sr_1) := c_st_boolean_vector_2 (boolean_vector_sr_2) ; v_st_bit_vector_1 (bit_vector_sr_1) := c_st_bit_vector_2 (bit_vector_sr_2) ; v_st_severity_level_vector_1 (severity_level_vector_sr_1) := c_st_severity_level_vector_2 (severity_level_vector_sr_2) ; v_st_string_1 (string_sr_1) := c_st_string_2 (string_sr_2) ; v_st_enum1_vector_1 (enum1_vector_sr_1) := c_st_enum1_vector_2 (enum1_vector_sr_2) ; v_st_integer_vector_1 (integer_vector_sr_1) := c_st_integer_vector_2 (integer_vector_sr_2) ; v_st_int1_vector_1 (int1_vector_sr_1) := c_st_int1_vector_2 (int1_vector_sr_2) ; v_st_time_vector_1 (time_vector_sr_1) := c_st_time_vector_2 (time_vector_sr_2) ; v_st_phys1_vector_1 (phys1_vector_sr_1) := c_st_phys1_vector_2 (phys1_vector_sr_2) ; v_st_real_vector_1 (real_vector_sr_1) := c_st_real_vector_2 (real_vector_sr_2) ; v_st_real1_vector_1 (real1_vector_sr_1) := c_st_real1_vector_2 (real1_vector_sr_2) ; v_st_rec1_vector_1 (rec1_vector_sr_1) := c_st_rec1_vector_2 (rec1_vector_sr_2) ; v_st_rec2_vector_1 (rec2_vector_sr_1) := c_st_rec2_vector_2 (rec2_vector_sr_2) ; v_st_rec3_vector_1 (rec3_vector_sr_1) := c_st_rec3_vector_2 (rec3_vector_sr_2) ; v_st_arr1_vector_1 (arr1_vector_sr_1) := c_st_arr1_vector_2 (arr1_vector_sr_2) ; v_st_arr2_vector_1 (arr2_vector_sr_1) := c_st_arr2_vector_2 (arr2_vector_sr_2) ; v_st_arr3_vector_1 (arr3_vector_sr_1) := c_st_arr3_vector_2 (arr3_vector_sr_2) ; -- end Proc1 ; begin Proc1 ; correct := correct and v_st_boolean_vector_1 (boolean_vector_sr_1) = c_st_boolean_vector_2 (boolean_vector_sr_2) ; correct := correct and v_st_bit_vector_1 (bit_vector_sr_1) = c_st_bit_vector_2 (bit_vector_sr_2) ; correct := correct and v_st_severity_level_vector_1 (severity_level_vector_sr_1) = c_st_severity_level_vector_2 (severity_level_vector_sr_2) ; correct := correct and v_st_string_1 (string_sr_1) = c_st_string_2 (string_sr_2) ; correct := correct and v_st_enum1_vector_1 (enum1_vector_sr_1) = c_st_enum1_vector_2 (enum1_vector_sr_2) ; correct := correct and v_st_integer_vector_1 (integer_vector_sr_1) = c_st_integer_vector_2 (integer_vector_sr_2) ; correct := correct and v_st_int1_vector_1 (int1_vector_sr_1) = c_st_int1_vector_2 (int1_vector_sr_2) ; correct := correct and v_st_time_vector_1 (time_vector_sr_1) = c_st_time_vector_2 (time_vector_sr_2) ; correct := correct and v_st_phys1_vector_1 (phys1_vector_sr_1) = c_st_phys1_vector_2 (phys1_vector_sr_2) ; correct := correct and v_st_real_vector_1 (real_vector_sr_1) = c_st_real_vector_2 (real_vector_sr_2) ; correct := correct and v_st_real1_vector_1 (real1_vector_sr_1) = c_st_real1_vector_2 (real1_vector_sr_2) ; correct := correct and v_st_rec1_vector_1 (rec1_vector_sr_1) = c_st_rec1_vector_2 (rec1_vector_sr_2) ; correct := correct and v_st_rec2_vector_1 (rec2_vector_sr_1) = c_st_rec2_vector_2 (rec2_vector_sr_2) ; correct := correct and v_st_rec3_vector_1 (rec3_vector_sr_1) = c_st_rec3_vector_2 (rec3_vector_sr_2) ; correct := correct and v_st_arr1_vector_1 (arr1_vector_sr_1) = c_st_arr1_vector_2 (arr1_vector_sr_2) ; correct := correct and v_st_arr2_vector_1 (arr2_vector_sr_1) = c_st_arr2_vector_2 (arr2_vector_sr_2) ; correct := correct and v_st_arr3_vector_1 (arr3_vector_sr_1) = c_st_arr3_vector_2 (arr3_vector_sr_2) ; -- test_report ( "ARCH00048.P3" , "Implicit array subtype conversion occurs "& "for slices", correct) ; end process P3 ; -- P4 : process ( Dummy ) subtype boolean_vector_range_1 is integer range lowb+1 to highb+1 ; subtype boolean_vector_sr_1 is integer range lowb+2 to highb ; subtype boolean_vector_sr_2 is integer range lowb+1 to highb-1 ; subtype st_boolean_vector_1 is boolean_vector (boolean_vector_range_1) ; variable v_st_boolean_vector_1 : st_boolean_vector_1 := c_st_boolean_vector_1 ; -- subtype bit_vector_range_1 is integer range lowb+1 to highb+1 ; subtype bit_vector_sr_1 is integer range lowb+2 to highb ; subtype bit_vector_sr_2 is integer range lowb+1 to highb-1 ; subtype st_bit_vector_1 is bit_vector (bit_vector_range_1) ; variable v_st_bit_vector_1 : st_bit_vector_1 := c_st_bit_vector_1 ; -- subtype severity_level_vector_range_1 is integer range lowb+1 to highb+1 ; subtype severity_level_vector_sr_1 is integer range lowb+2 to highb ; subtype severity_level_vector_sr_2 is integer range lowb+1 to highb-1 ; subtype st_severity_level_vector_1 is severity_level_vector (severity_level_vector_range_1) ; variable v_st_severity_level_vector_1 : st_severity_level_vector_1 := c_st_severity_level_vector_1 ; -- subtype string_range_1 is integer range lowb+1 to highb+1 ; subtype string_sr_1 is integer range lowb+2 to highb ; subtype string_sr_2 is integer range lowb+1 to highb-1 ; subtype st_string_1 is string (string_range_1) ; variable v_st_string_1 : st_string_1 := c_st_string_1 ; -- subtype enum1_vector_range_1 is integer range lowb+1 to highb+1 ; subtype enum1_vector_sr_1 is integer range lowb+2 to highb ; subtype enum1_vector_sr_2 is integer range lowb+1 to highb-1 ; subtype st_enum1_vector_1 is enum1_vector (enum1_vector_range_1) ; variable v_st_enum1_vector_1 : st_enum1_vector_1 := c_st_enum1_vector_1 ; -- subtype integer_vector_range_1 is integer range lowb+1 to highb+1 ; subtype integer_vector_sr_1 is integer range lowb+2 to highb ; subtype integer_vector_sr_2 is integer range lowb+1 to highb-1 ; subtype st_integer_vector_1 is integer_vector (integer_vector_range_1) ; variable v_st_integer_vector_1 : st_integer_vector_1 := c_st_integer_vector_1 ; -- subtype int1_vector_range_1 is integer range lowb+1 to highb+1 ; subtype int1_vector_sr_1 is integer range lowb+2 to highb ; subtype int1_vector_sr_2 is integer range lowb+1 to highb-1 ; subtype st_int1_vector_1 is int1_vector (int1_vector_range_1) ; variable v_st_int1_vector_1 : st_int1_vector_1 := c_st_int1_vector_1 ; -- subtype time_vector_range_1 is integer range lowb+1 to highb+1 ; subtype time_vector_sr_1 is integer range lowb+2 to highb ; subtype time_vector_sr_2 is integer range lowb+1 to highb-1 ; subtype st_time_vector_1 is time_vector (time_vector_range_1) ; variable v_st_time_vector_1 : st_time_vector_1 := c_st_time_vector_1 ; -- subtype phys1_vector_range_1 is integer range lowb+1 to highb+1 ; subtype phys1_vector_sr_1 is integer range lowb+2 to highb ; subtype phys1_vector_sr_2 is integer range lowb+1 to highb-1 ; subtype st_phys1_vector_1 is phys1_vector (phys1_vector_range_1) ; variable v_st_phys1_vector_1 : st_phys1_vector_1 := c_st_phys1_vector_1 ; -- subtype real_vector_range_1 is integer range lowb+1 to highb+1 ; subtype real_vector_sr_1 is integer range lowb+2 to highb ; subtype real_vector_sr_2 is integer range lowb+1 to highb-1 ; subtype st_real_vector_1 is real_vector (real_vector_range_1) ; variable v_st_real_vector_1 : st_real_vector_1 := c_st_real_vector_1 ; -- subtype real1_vector_range_1 is integer range lowb+1 to highb+1 ; subtype real1_vector_sr_1 is integer range lowb+2 to highb ; subtype real1_vector_sr_2 is integer range lowb+1 to highb-1 ; subtype st_real1_vector_1 is real1_vector (real1_vector_range_1) ; variable v_st_real1_vector_1 : st_real1_vector_1 := c_st_real1_vector_1 ; -- subtype rec1_vector_range_1 is integer range lowb+1 to highb+1 ; subtype rec1_vector_sr_1 is integer range lowb+2 to highb ; subtype rec1_vector_sr_2 is integer range lowb+1 to highb-1 ; subtype st_rec1_vector_1 is rec1_vector (rec1_vector_range_1) ; variable v_st_rec1_vector_1 : st_rec1_vector_1 := c_st_rec1_vector_1 ; -- subtype rec2_vector_range_1 is integer range lowb+1 to highb+1 ; subtype rec2_vector_sr_1 is integer range lowb+2 to highb ; subtype rec2_vector_sr_2 is integer range lowb+1 to highb-1 ; subtype st_rec2_vector_1 is rec2_vector (rec2_vector_range_1) ; variable v_st_rec2_vector_1 : st_rec2_vector_1 := c_st_rec2_vector_1 ; -- subtype rec3_vector_range_1 is integer range lowb+1 to highb+1 ; subtype rec3_vector_sr_1 is integer range lowb+2 to highb ; subtype rec3_vector_sr_2 is integer range lowb+1 to highb-1 ; subtype st_rec3_vector_1 is rec3_vector (rec3_vector_range_1) ; variable v_st_rec3_vector_1 : st_rec3_vector_1 := c_st_rec3_vector_1 ; -- subtype arr1_vector_range_1 is integer range lowb+1 to highb+1 ; subtype arr1_vector_sr_1 is integer range lowb+2 to highb ; subtype arr1_vector_sr_2 is integer range lowb+1 to highb-1 ; subtype st_arr1_vector_1 is arr1_vector (arr1_vector_range_1) ; variable v_st_arr1_vector_1 : st_arr1_vector_1 := c_st_arr1_vector_1 ; -- subtype arr2_vector_range_1 is integer range lowb+1 to highb+1 ; subtype arr2_vector_sr_1 is integer range lowb+2 to highb ; subtype arr2_vector_sr_2 is integer range lowb+1 to highb-1 ; subtype st_arr2_vector_1 is arr2_vector (arr2_vector_range_1) ; variable v_st_arr2_vector_1 : st_arr2_vector_1 := c_st_arr2_vector_1 ; -- subtype arr3_vector_range_1 is integer range lowb+1 to highb+1 ; subtype arr3_vector_sr_1 is integer range lowb+2 to highb ; subtype arr3_vector_sr_2 is integer range lowb+1 to highb-1 ; subtype st_arr3_vector_1 is arr3_vector (arr3_vector_range_1) ; variable v_st_arr3_vector_1 : st_arr3_vector_1 := c_st_arr3_vector_1 ; -- -- variable correct : boolean := true ; -- procedure Proc1 ( v_st_boolean_vector_1 : inout boolean_vector ; v_st_bit_vector_1 : inout bit_vector ; v_st_severity_level_vector_1 : inout severity_level_vector ; v_st_string_1 : inout string ; v_st_enum1_vector_1 : inout enum1_vector ; v_st_integer_vector_1 : inout integer_vector ; v_st_int1_vector_1 : inout int1_vector ; v_st_time_vector_1 : inout time_vector ; v_st_phys1_vector_1 : inout phys1_vector ; v_st_real_vector_1 : inout real_vector ; v_st_real1_vector_1 : inout real1_vector ; v_st_rec1_vector_1 : inout rec1_vector ; v_st_rec2_vector_1 : inout rec2_vector ; v_st_rec3_vector_1 : inout rec3_vector ; v_st_arr1_vector_1 : inout arr1_vector ; v_st_arr2_vector_1 : inout arr2_vector ; v_st_arr3_vector_1 : inout arr3_vector ) is begin v_st_boolean_vector_1 (boolean_vector_sr_1) := c_st_boolean_vector_2 (boolean_vector_sr_2) ; v_st_bit_vector_1 (bit_vector_sr_1) := c_st_bit_vector_2 (bit_vector_sr_2) ; v_st_severity_level_vector_1 (severity_level_vector_sr_1) := c_st_severity_level_vector_2 (severity_level_vector_sr_2) ; v_st_string_1 (string_sr_1) := c_st_string_2 (string_sr_2) ; v_st_enum1_vector_1 (enum1_vector_sr_1) := c_st_enum1_vector_2 (enum1_vector_sr_2) ; v_st_integer_vector_1 (integer_vector_sr_1) := c_st_integer_vector_2 (integer_vector_sr_2) ; v_st_int1_vector_1 (int1_vector_sr_1) := c_st_int1_vector_2 (int1_vector_sr_2) ; v_st_time_vector_1 (time_vector_sr_1) := c_st_time_vector_2 (time_vector_sr_2) ; v_st_phys1_vector_1 (phys1_vector_sr_1) := c_st_phys1_vector_2 (phys1_vector_sr_2) ; v_st_real_vector_1 (real_vector_sr_1) := c_st_real_vector_2 (real_vector_sr_2) ; v_st_real1_vector_1 (real1_vector_sr_1) := c_st_real1_vector_2 (real1_vector_sr_2) ; v_st_rec1_vector_1 (rec1_vector_sr_1) := c_st_rec1_vector_2 (rec1_vector_sr_2) ; v_st_rec2_vector_1 (rec2_vector_sr_1) := c_st_rec2_vector_2 (rec2_vector_sr_2) ; v_st_rec3_vector_1 (rec3_vector_sr_1) := c_st_rec3_vector_2 (rec3_vector_sr_2) ; v_st_arr1_vector_1 (arr1_vector_sr_1) := c_st_arr1_vector_2 (arr1_vector_sr_2) ; v_st_arr2_vector_1 (arr2_vector_sr_1) := c_st_arr2_vector_2 (arr2_vector_sr_2) ; v_st_arr3_vector_1 (arr3_vector_sr_1) := c_st_arr3_vector_2 (arr3_vector_sr_2) ; -- end Proc1 ; begin Proc1 ( v_st_boolean_vector_1 , v_st_bit_vector_1 , v_st_severity_level_vector_1 , v_st_string_1 , v_st_enum1_vector_1 , v_st_integer_vector_1 , v_st_int1_vector_1 , v_st_time_vector_1 , v_st_phys1_vector_1 , v_st_real_vector_1 , v_st_real1_vector_1 , v_st_rec1_vector_1 , v_st_rec2_vector_1 , v_st_rec3_vector_1 , v_st_arr1_vector_1 , v_st_arr2_vector_1 , v_st_arr3_vector_1 ) ; correct := correct and v_st_boolean_vector_1 (boolean_vector_sr_1) = c_st_boolean_vector_2 (boolean_vector_sr_2) ; correct := correct and v_st_bit_vector_1 (bit_vector_sr_1) = c_st_bit_vector_2 (bit_vector_sr_2) ; correct := correct and v_st_severity_level_vector_1 (severity_level_vector_sr_1) = c_st_severity_level_vector_2 (severity_level_vector_sr_2) ; correct := correct and v_st_string_1 (string_sr_1) = c_st_string_2 (string_sr_2) ; correct := correct and v_st_enum1_vector_1 (enum1_vector_sr_1) = c_st_enum1_vector_2 (enum1_vector_sr_2) ; correct := correct and v_st_integer_vector_1 (integer_vector_sr_1) = c_st_integer_vector_2 (integer_vector_sr_2) ; correct := correct and v_st_int1_vector_1 (int1_vector_sr_1) = c_st_int1_vector_2 (int1_vector_sr_2) ; correct := correct and v_st_time_vector_1 (time_vector_sr_1) = c_st_time_vector_2 (time_vector_sr_2) ; correct := correct and v_st_phys1_vector_1 (phys1_vector_sr_1) = c_st_phys1_vector_2 (phys1_vector_sr_2) ; correct := correct and v_st_real_vector_1 (real_vector_sr_1) = c_st_real_vector_2 (real_vector_sr_2) ; correct := correct and v_st_real1_vector_1 (real1_vector_sr_1) = c_st_real1_vector_2 (real1_vector_sr_2) ; correct := correct and v_st_rec1_vector_1 (rec1_vector_sr_1) = c_st_rec1_vector_2 (rec1_vector_sr_2) ; correct := correct and v_st_rec2_vector_1 (rec2_vector_sr_1) = c_st_rec2_vector_2 (rec2_vector_sr_2) ; correct := correct and v_st_rec3_vector_1 (rec3_vector_sr_1) = c_st_rec3_vector_2 (rec3_vector_sr_2) ; correct := correct and v_st_arr1_vector_1 (arr1_vector_sr_1) = c_st_arr1_vector_2 (arr1_vector_sr_2) ; correct := correct and v_st_arr2_vector_1 (arr2_vector_sr_1) = c_st_arr2_vector_2 (arr2_vector_sr_2) ; correct := correct and v_st_arr3_vector_1 (arr3_vector_sr_1) = c_st_arr3_vector_2 (arr3_vector_sr_2) ; -- test_report ( "ARCH00048.P4" , "Implicit array subtype conversion occurs "& "for slices", correct) ; end process P4 ; -- end ARCH00048 ; -- entity ENT00048_Test_Bench is end ENT00048_Test_Bench ; -- architecture ARCH00048_Test_Bench of ENT00048_Test_Bench is begin L1: block component UUT end component ; for CIS1 : UUT use entity WORK.E00000 ( ARCH00048 ) ; begin CIS1 : UUT ; end block L1 ; end ARCH00048_Test_Bench ;
gpl-3.0
597eb21fc4bb1857a0646d9075d88ee6
0.529761
3.338207
false
false
false
false
grwlf/vsim
vhdl/IEEE/mentor/std_logic_arith.vhdl
7
14,183
---------------------------------------------------------------------------- -- -- -- Copyright (c) 1993 by Mentor Graphics -- -- -- -- This source file is proprietary information of Mentor Graphics,Inc. -- -- It may be distributed in whole without restriction provided that -- -- this copyright statement is not removed from the file and that -- -- any derivative work contains this copyright notice. -- -- -- -- Package Name : std_logic_arith -- -- -- -- Purpose : This package is to allow the synthesis of the 1164 package. -- -- This package add the capability of SIGNED/UNSIGNED math. -- -- -- ---------------------------------------------------------------------------- LIBRARY ieee ; PACKAGE std_logic_arith IS USE ieee.std_logic_1164.ALL; TYPE SIGNED IS ARRAY (Natural RANGE <>) OF STD_LOGIC ; TYPE UNSIGNED IS ARRAY (Natural RANGE <>) OF STD_LOGIC ; FUNCTION std_ulogic_wired_or ( input : std_ulogic_vector ) RETURN std_ulogic; FUNCTION std_ulogic_wired_and ( input : std_ulogic_vector ) RETURN std_ulogic; ------------------------------------------------------------------------------- -- Note that all functions that take two vector arguments will -- handle unequal argument lengths ------------------------------------------------------------------------------- ------------------------------------------------------------------- -- Conversion Functions ------------------------------------------------------------------- -- Except for the to_integer and conv_integer functions for the -- signed argument all others assume the input vector to be of -- magnitude representation. The signed functions assume -- a 2's complement representation. FUNCTION to_integer ( arg1 : STD_ULOGIC_VECTOR; x : INTEGER := 0 ) RETURN INTEGER; FUNCTION to_integer ( arg1 : STD_LOGIC_VECTOR; x : INTEGER := 0 ) RETURN INTEGER; FUNCTION to_integer ( arg1 : STD_LOGIC; x : INTEGER := 0 ) RETURN NATURAL; FUNCTION to_integer ( arg1 : UNSIGNED; x : INTEGER := 0 ) RETURN NATURAL; FUNCTION to_integer ( arg1 : SIGNED; x : INTEGER := 0 ) RETURN INTEGER; FUNCTION conv_integer ( arg1 : STD_ULOGIC_VECTOR; x : INTEGER := 0 ) RETURN INTEGER; FUNCTION conv_integer ( arg1 : STD_LOGIC_VECTOR; x : INTEGER := 0 ) RETURN INTEGER; FUNCTION conv_integer ( arg1 : STD_LOGIC; x : INTEGER := 0 ) RETURN NATURAL; FUNCTION conv_integer ( arg1 : UNSIGNED; x : INTEGER := 0 ) RETURN NATURAL; FUNCTION conv_integer ( arg1 : SIGNED; x : INTEGER := 0 ) RETURN INTEGER; -- Following functions will return the natural argument in magnitude representation. FUNCTION to_stdlogic ( arg1 : BOOLEAN ) RETURN STD_LOGIC; FUNCTION to_stdlogicvector ( arg1 : INTEGER; size : NATURAL ) RETURN STD_LOGIC_VECTOR; FUNCTION to_stdulogicvector ( arg1 : INTEGER; size : NATURAL ) RETURN STD_ULOGIC_VECTOR; FUNCTION to_unsigned ( arg1 : NATURAL; size : NATURAL ) RETURN UNSIGNED; FUNCTION conv_unsigned ( arg1 : NATURAL; size : NATURAL ) RETURN UNSIGNED; -- The integer argument is returned in 2's complement representation. FUNCTION to_signed ( arg1 : INTEGER; size : NATURAL ) RETURN SIGNED; FUNCTION conv_signed ( arg1 : INTEGER; size : NATURAL ) RETURN SIGNED; ------------------------------------------------------------------------------- -- sign/zero extend FUNCTIONs ------------------------------------------------------------------------------- -- The zero_extend functions will perform zero padding to the input vector, -- returning a vector of length equal to size (the second argument). Note that -- if size is less than the length of the input argument an assertion will occur. FUNCTION zero_extend ( arg1 : STD_ULOGIC_VECTOR; size : NATURAL ) RETURN STD_ULOGIC_VECTOR; FUNCTION zero_extend ( arg1 : STD_LOGIC_VECTOR; size : NATURAL ) RETURN STD_LOGIC_VECTOR; FUNCTION zero_extend ( arg1 : STD_LOGIC; size : NATURAL ) RETURN STD_LOGIC_VECTOR; FUNCTION zero_extend ( arg1 : UNSIGNED; size : NATURAL ) RETURN UNSIGNED; FUNCTION sign_extend ( arg1 : SIGNED; size : NATURAL ) RETURN SIGNED; ------------------------------------------------------------------------------- -- Arithmetic functions ------------------------------------------------------------------------------- -- All arithmetic functions except multiplication will return a vector -- of size equal to the size of its largest argument. For multiplication, -- the resulting vector has a size equal to the sum of the size of its inputs. -- Note that arguments of unequal lengths are allowed. FUNCTION "+" ( arg1, arg2 : STD_LOGIC ) RETURN STD_LOGIC; FUNCTION "+" ( arg1, arg2 : STD_ULOGIC_VECTOR ) RETURN STD_ULOGIC_VECTOR; FUNCTION "+" ( arg1, arg2 : STD_LOGIC_VECTOR ) RETURN STD_LOGIC_VECTOR; FUNCTION "+" ( arg1, arg2 : UNSIGNED ) RETURN UNSIGNED ; FUNCTION "+" ( arg1, arg2 : SIGNED ) RETURN SIGNED ; FUNCTION "-" ( arg1, arg2 : STD_LOGIC ) RETURN STD_LOGIC; FUNCTION "-" ( arg1, arg2 : STD_ULOGIC_VECTOR ) RETURN STD_ULOGIC_VECTOR; FUNCTION "-" ( arg1, arg2 : STD_LOGIC_VECTOR ) RETURN STD_LOGIC_VECTOR; FUNCTION "-" ( arg1, arg2 : UNSIGNED ) RETURN UNSIGNED; FUNCTION "-" ( arg1, arg2 : SIGNED ) RETURN SIGNED; FUNCTION "+" ( arg1 : STD_ULOGIC_VECTOR ) RETURN STD_ULOGIC_VECTOR; FUNCTION "+" ( arg1 : STD_LOGIC_VECTOR ) RETURN STD_LOGIC_VECTOR; FUNCTION "+" ( arg1 : UNSIGNED ) RETURN UNSIGNED; FUNCTION "+" ( arg1 : SIGNED ) RETURN SIGNED; FUNCTION "-" ( arg1 : SIGNED ) RETURN SIGNED; FUNCTION "*" ( arg1, arg2 : STD_ULOGIC_VECTOR ) RETURN STD_ULOGIC_VECTOR; FUNCTION "*" ( arg1, arg2 : STD_LOGIC_VECTOR ) RETURN STD_LOGIC_VECTOR; FUNCTION "*" ( arg1, arg2 : UNSIGNED ) RETURN UNSIGNED ; FUNCTION "*" ( arg1, arg2 : SIGNED ) RETURN SIGNED ; FUNCTION "abs" ( arg1 : SIGNED) RETURN SIGNED; -- Vectorized Overloaded Arithmetic Operators, not supported for synthesis. -- The following operators are not supported for synthesis. FUNCTION "/" ( l, r : STD_ULOGIC_VECTOR ) RETURN STD_ULOGIC_VECTOR; FUNCTION "/" ( l, r : STD_LOGIC_VECTOR ) RETURN STD_LOGIC_VECTOR; FUNCTION "/" ( l, r : UNSIGNED ) RETURN UNSIGNED; FUNCTION "/" ( l, r : SIGNED ) RETURN SIGNED; FUNCTION "MOD" ( l, r : STD_ULOGIC_VECTOR ) RETURN STD_ULOGIC_VECTOR; FUNCTION "MOD" ( l, r : STD_LOGIC_VECTOR ) RETURN STD_LOGIC_VECTOR; FUNCTION "MOD" ( l, r : UNSIGNED ) RETURN UNSIGNED; FUNCTION "REM" ( l, r : STD_ULOGIC_VECTOR ) RETURN STD_ULOGIC_VECTOR; FUNCTION "REM" ( l, r : STD_LOGIC_VECTOR ) RETURN STD_LOGIC_VECTOR; FUNCTION "REM" ( l, r : UNSIGNED ) RETURN UNSIGNED; FUNCTION "**" ( l, r : STD_ULOGIC_VECTOR ) RETURN STD_ULOGIC_VECTOR; FUNCTION "**" ( l, r : STD_LOGIC_VECTOR ) RETURN STD_LOGIC_VECTOR; FUNCTION "**" ( l, r : UNSIGNED ) RETURN UNSIGNED; ------------------------------------------------------------------------------- -- Shift and rotate functions. ------------------------------------------------------------------------------- -- Note that all the shift and rotate functions below will change to overloaded -- operators in the train1 release. FUNCTION "sla" (arg1:UNSIGNED ; arg2:NATURAL) RETURN UNSIGNED ; FUNCTION "sla" (arg1:SIGNED ; arg2:NATURAL) RETURN SIGNED ; FUNCTION "sla" (arg1:STD_ULOGIC_VECTOR ; arg2:NATURAL) RETURN STD_ULOGIC_VECTOR ; FUNCTION "sla" (arg1:STD_LOGIC_VECTOR ; arg2:NATURAL) RETURN STD_LOGIC_VECTOR ; FUNCTION "sra" (arg1:UNSIGNED ; arg2:NATURAL) RETURN UNSIGNED ; FUNCTION "sra" (arg1:SIGNED ; arg2:NATURAL) RETURN SIGNED ; FUNCTION "sra" (arg1:STD_ULOGIC_VECTOR ; arg2:NATURAL) RETURN STD_ULOGIC_VECTOR ; FUNCTION "sra" (arg1:STD_LOGIC_VECTOR ; arg2:NATURAL) RETURN STD_LOGIC_VECTOR ; FUNCTION "sll" (arg1:UNSIGNED ; arg2:NATURAL) RETURN UNSIGNED ; FUNCTION "sll" (arg1:SIGNED ; arg2:NATURAL) RETURN SIGNED ; FUNCTION "sll" (arg1:STD_ULOGIC_VECTOR ; arg2:NATURAL) RETURN STD_ULOGIC_VECTOR ; FUNCTION "sll" (arg1:STD_LOGIC_VECTOR ; arg2:NATURAL) RETURN STD_LOGIC_VECTOR ; FUNCTION "srl" (arg1:UNSIGNED ; arg2:NATURAL) RETURN UNSIGNED ; FUNCTION "srl" (arg1:SIGNED ; arg2:NATURAL) RETURN SIGNED ; FUNCTION "srl" (arg1:STD_ULOGIC_VECTOR ; arg2:NATURAL) RETURN STD_ULOGIC_VECTOR ; FUNCTION "srl" (arg1:STD_LOGIC_VECTOR ; arg2:NATURAL) RETURN STD_LOGIC_VECTOR ; FUNCTION "rol" (arg1:UNSIGNED ; arg2:NATURAL) RETURN UNSIGNED ; FUNCTION "rol" (arg1:SIGNED ; arg2:NATURAL) RETURN SIGNED ; FUNCTION "rol" (arg1:STD_ULOGIC_VECTOR ; arg2:NATURAL) RETURN STD_ULOGIC_VECTOR ; FUNCTION "rol" (arg1:STD_LOGIC_VECTOR ; arg2:NATURAL) RETURN STD_LOGIC_VECTOR ; FUNCTION "ror" (arg1:UNSIGNED ; arg2:NATURAL) RETURN UNSIGNED ; FUNCTION "ror" (arg1:SIGNED ; arg2:NATURAL) RETURN SIGNED ; FUNCTION "ror" (arg1:STD_ULOGIC_VECTOR ; arg2:NATURAL) RETURN STD_ULOGIC_VECTOR ; FUNCTION "ror" (arg1:STD_LOGIC_VECTOR ; arg2:NATURAL) RETURN STD_LOGIC_VECTOR ; ------------------------------------------------------------------------------- -- Comparision functions and operators. ------------------------------------------------------------------------------- -- For all comparision operators, the default operator for signed and unsigned -- types has been overloaded to perform logical comparisions. Note that for -- other types the default operator is not overloaded and the use will result -- in literal comparisions which is not supported for synthesis. -- -- Unequal operator widths are supported for all the comparision functions. FUNCTION eq ( l, r : STD_LOGIC ) RETURN BOOLEAN; FUNCTION eq ( l, r : STD_ULOGIC_VECTOR ) RETURN BOOLEAN; FUNCTION eq ( l, r : STD_LOGIC_VECTOR ) RETURN BOOLEAN; FUNCTION eq ( l, r : UNSIGNED ) RETURN BOOLEAN ; FUNCTION eq ( l, r : SIGNED ) RETURN BOOLEAN ; FUNCTION "=" ( l, r : UNSIGNED ) RETURN BOOLEAN ; FUNCTION "=" ( l, r : SIGNED ) RETURN BOOLEAN ; FUNCTION ne ( l, r : STD_LOGIC ) RETURN BOOLEAN; FUNCTION ne ( l, r : STD_ULOGIC_VECTOR ) RETURN BOOLEAN; FUNCTION ne ( l, r : STD_LOGIC_VECTOR ) RETURN BOOLEAN; FUNCTION ne ( l, r : UNSIGNED ) RETURN BOOLEAN ; FUNCTION ne ( l, r : SIGNED ) RETURN BOOLEAN ; FUNCTION "/=" ( l, r : UNSIGNED ) RETURN BOOLEAN ; FUNCTION "/=" ( l, r : SIGNED ) RETURN BOOLEAN ; FUNCTION lt ( l, r : STD_LOGIC ) RETURN BOOLEAN; FUNCTION lt ( l, r : STD_ULOGIC_VECTOR ) RETURN BOOLEAN; FUNCTION lt ( l, r : STD_LOGIC_VECTOR ) RETURN BOOLEAN; FUNCTION lt ( l, r : UNSIGNED ) RETURN BOOLEAN ; FUNCTION lt ( l, r : SIGNED ) RETURN BOOLEAN ; FUNCTION "<" ( l, r : UNSIGNED ) RETURN BOOLEAN ; FUNCTION "<" ( l, r : SIGNED ) RETURN BOOLEAN ; FUNCTION gt ( l, r : STD_LOGIC ) RETURN BOOLEAN; FUNCTION gt ( l, r : STD_ULOGIC_VECTOR ) RETURN BOOLEAN; FUNCTION gt ( l, r : STD_LOGIC_VECTOR ) RETURN BOOLEAN; FUNCTION gt ( l, r : UNSIGNED ) RETURN BOOLEAN ; FUNCTION gt ( l, r : SIGNED ) RETURN BOOLEAN ; FUNCTION ">" ( l, r : UNSIGNED ) RETURN BOOLEAN ; FUNCTION ">" ( l, r : SIGNED ) RETURN BOOLEAN ; FUNCTION le ( l, r : STD_LOGIC ) RETURN BOOLEAN; FUNCTION le ( l, r : STD_ULOGIC_VECTOR ) RETURN BOOLEAN; FUNCTION le ( l, r : STD_LOGIC_VECTOR ) RETURN BOOLEAN; FUNCTION le ( l, r : UNSIGNED ) RETURN BOOLEAN ; FUNCTION le ( l, r : SIGNED ) RETURN BOOLEAN ; FUNCTION "<=" ( l, r : UNSIGNED ) RETURN BOOLEAN ; FUNCTION "<=" ( l, r : SIGNED ) RETURN BOOLEAN ; FUNCTION ge ( l, r : STD_LOGIC ) RETURN BOOLEAN; FUNCTION ge ( l, r : STD_ULOGIC_VECTOR ) RETURN BOOLEAN; FUNCTION ge ( l, r : STD_LOGIC_VECTOR ) RETURN BOOLEAN; FUNCTION ge ( l, r : UNSIGNED ) RETURN BOOLEAN ; FUNCTION ge ( l, r : SIGNED ) RETURN BOOLEAN ; FUNCTION ">=" ( l, r : UNSIGNED ) RETURN BOOLEAN ; FUNCTION ">=" ( l, r : SIGNED ) RETURN BOOLEAN ; ------------------------------------------------------------------------------- -- Logical operators. ------------------------------------------------------------------------------- -- allows operands of unequal lengths, return vector is -- equal to the size of the largest argument. FUNCTION "and" (arg1, arg2:SIGNED) RETURN SIGNED; FUNCTION "and" (arg1, arg2:UNSIGNED) RETURN UNSIGNED; FUNCTION "nand" (arg1, arg2:SIGNED) RETURN SIGNED; FUNCTION "nand" (arg1, arg2:UNSIGNED) RETURN UNSIGNED; FUNCTION "or" (arg1, arg2:SIGNED) RETURN SIGNED; FUNCTION "or" (arg1, arg2:UNSIGNED) RETURN UNSIGNED; FUNCTION "nor" (arg1, arg2:SIGNED) RETURN SIGNED; FUNCTION "nor" (arg1, arg2:UNSIGNED) RETURN UNSIGNED; FUNCTION "xor" (arg1, arg2:SIGNED) RETURN SIGNED; FUNCTION "xor" (arg1, arg2:UNSIGNED) RETURN UNSIGNED; FUNCTION "not" (arg1:SIGNED) RETURN SIGNED; FUNCTION "not" (arg1:UNSIGNED) RETURN UNSIGNED; FUNCTION "xnor" (arg1, arg2:STD_ULOGIC_VECTOR) RETURN STD_ULOGIC_VECTOR; FUNCTION "xnor" (arg1, arg2:STD_LOGIC_VECTOR) RETURN STD_LOGIC_VECTOR; FUNCTION "xnor" (arg1, arg2:SIGNED) RETURN SIGNED; FUNCTION "xnor" (arg1, arg2:UNSIGNED) RETURN UNSIGNED; END std_logic_arith ;
gpl-3.0
7dd8bf3042a727cc3adeca2e0d128ff5
0.568497
4.281014
false
false
false
false
jairov4/accel-oil
solution_spartan6/syn/vhdl/nfa_get_finals.vhd
3
12,962
-- ============================================================== -- RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC -- Version: 2013.4 -- Copyright (C) 2013 Xilinx Inc. All rights reserved. -- -- =========================================================== library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; entity nfa_get_finals is port ( ap_clk : IN STD_LOGIC; ap_rst : IN STD_LOGIC; ap_start : IN STD_LOGIC; ap_done : OUT STD_LOGIC; ap_idle : OUT STD_LOGIC; ap_ready : OUT STD_LOGIC; nfa_finals_buckets_req_din : OUT STD_LOGIC; nfa_finals_buckets_req_full_n : IN STD_LOGIC; nfa_finals_buckets_req_write : OUT STD_LOGIC; nfa_finals_buckets_rsp_empty_n : IN STD_LOGIC; nfa_finals_buckets_rsp_read : OUT STD_LOGIC; nfa_finals_buckets_address : OUT STD_LOGIC_VECTOR (31 downto 0); nfa_finals_buckets_datain : IN STD_LOGIC_VECTOR (31 downto 0); nfa_finals_buckets_dataout : OUT STD_LOGIC_VECTOR (31 downto 0); nfa_finals_buckets_size : OUT STD_LOGIC_VECTOR (31 downto 0); ap_ce : IN STD_LOGIC; ap_return_0 : OUT STD_LOGIC_VECTOR (31 downto 0); ap_return_1 : OUT STD_LOGIC_VECTOR (31 downto 0) ); end; architecture behav of nfa_get_finals is constant ap_const_logic_1 : STD_LOGIC := '1'; constant ap_const_logic_0 : STD_LOGIC := '0'; constant ap_ST_pp0_stg0_fsm_0 : STD_LOGIC_VECTOR (0 downto 0) := "1"; constant ap_ST_pp0_stg1_fsm_1 : STD_LOGIC_VECTOR (0 downto 0) := "0"; constant ap_const_lv32_1 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000001"; constant ap_const_lv32_0 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000000"; signal ap_CS_fsm : STD_LOGIC_VECTOR (0 downto 0) := "1"; signal ap_reg_ppiten_pp0_it0 : STD_LOGIC; signal ap_reg_ppiten_pp0_it1 : STD_LOGIC := '0'; signal nfa_finals_buckets_read_reg_55 : STD_LOGIC_VECTOR (31 downto 0); signal ap_reg_ppiten_pp0_it0_preg : STD_LOGIC := '0'; signal ap_NS_fsm : STD_LOGIC_VECTOR (0 downto 0); signal ap_sig_pprstidle_pp0 : STD_LOGIC; signal ap_sig_bdd_117 : BOOLEAN; signal ap_sig_bdd_119 : BOOLEAN; signal ap_sig_bdd_116 : BOOLEAN; begin -- the current state (ap_CS_fsm) of the state machine. -- ap_CS_fsm_assign_proc : process(ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (ap_rst = '1') then ap_CS_fsm <= ap_ST_pp0_stg0_fsm_0; else ap_CS_fsm <= ap_NS_fsm; end if; end if; end process; -- ap_reg_ppiten_pp0_it0_preg assign process. -- ap_reg_ppiten_pp0_it0_preg_assign_proc : process(ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (ap_rst = '1') then ap_reg_ppiten_pp0_it0_preg <= ap_const_logic_0; else if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and not((not((ap_const_logic_1 = ap_ce)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and (nfa_finals_buckets_rsp_empty_n = ap_const_logic_0)))))) then ap_reg_ppiten_pp0_it0_preg <= ap_start; end if; end if; end if; end process; -- ap_reg_ppiten_pp0_it1 assign process. -- ap_reg_ppiten_pp0_it1_assign_proc : process(ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (ap_rst = '1') then ap_reg_ppiten_pp0_it1 <= ap_const_logic_0; else if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and not((not((ap_const_logic_1 = ap_ce)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and (nfa_finals_buckets_rsp_empty_n = ap_const_logic_0)))) and not((ap_const_logic_1 = ap_reg_ppiten_pp0_it0)))) then ap_reg_ppiten_pp0_it1 <= ap_const_logic_0; elsif (((ap_ST_pp0_stg1_fsm_1 = ap_CS_fsm) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (nfa_finals_buckets_rsp_empty_n = ap_const_logic_0)) or not((ap_const_logic_1 = ap_ce)))))) then ap_reg_ppiten_pp0_it1 <= ap_reg_ppiten_pp0_it0; end if; end if; end if; end process; -- assign process. -- process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_ST_pp0_stg1_fsm_1 = ap_CS_fsm) and not(((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (nfa_finals_buckets_rsp_empty_n = ap_const_logic_0))) and (ap_const_logic_1 = ap_ce))) then nfa_finals_buckets_read_reg_55 <= nfa_finals_buckets_datain; end if; end if; end process; -- the next state (ap_NS_fsm) of the state machine. -- ap_NS_fsm_assign_proc : process (ap_start , ap_CS_fsm , ap_reg_ppiten_pp0_it0 , ap_reg_ppiten_pp0_it1 , nfa_finals_buckets_rsp_empty_n , ap_ce , ap_sig_pprstidle_pp0) begin case ap_CS_fsm is when ap_ST_pp0_stg0_fsm_0 => if ((not((not((ap_const_logic_1 = ap_ce)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and (nfa_finals_buckets_rsp_empty_n = ap_const_logic_0)))) and not((ap_const_logic_1 = ap_sig_pprstidle_pp0)) and not(((ap_const_logic_0 = ap_reg_ppiten_pp0_it1) and (ap_const_logic_0 = ap_start))))) then ap_NS_fsm <= ap_ST_pp0_stg1_fsm_1; elsif ((not((not((ap_const_logic_1 = ap_ce)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and (nfa_finals_buckets_rsp_empty_n = ap_const_logic_0)))) and (ap_const_logic_1 = ap_sig_pprstidle_pp0))) then ap_NS_fsm <= ap_ST_pp0_stg0_fsm_0; else ap_NS_fsm <= ap_ST_pp0_stg0_fsm_0; end if; when ap_ST_pp0_stg1_fsm_1 => if (not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (nfa_finals_buckets_rsp_empty_n = ap_const_logic_0)) or not((ap_const_logic_1 = ap_ce))))) then ap_NS_fsm <= ap_ST_pp0_stg0_fsm_0; else ap_NS_fsm <= ap_ST_pp0_stg1_fsm_1; end if; when others => ap_NS_fsm <= "X"; end case; end process; -- ap_done assign process. -- ap_done_assign_proc : process(ap_start, ap_CS_fsm, ap_reg_ppiten_pp0_it0, ap_reg_ppiten_pp0_it1, nfa_finals_buckets_rsp_empty_n, ap_ce) begin if (((not((ap_const_logic_1 = ap_start)) and (ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it0)) or ((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and (ap_const_logic_1 = ap_ce) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and (nfa_finals_buckets_rsp_empty_n = ap_const_logic_0))))))) then ap_done <= ap_const_logic_1; else ap_done <= ap_const_logic_0; end if; end process; -- ap_idle assign process. -- ap_idle_assign_proc : process(ap_start, ap_CS_fsm, ap_reg_ppiten_pp0_it0, ap_reg_ppiten_pp0_it1) begin if ((not((ap_const_logic_1 = ap_start)) and (ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it0) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it1))) then ap_idle <= ap_const_logic_1; else ap_idle <= ap_const_logic_0; end if; end process; -- ap_ready assign process. -- ap_ready_assign_proc : process(ap_CS_fsm, ap_reg_ppiten_pp0_it0, nfa_finals_buckets_rsp_empty_n, ap_ce) begin if (((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_ST_pp0_stg1_fsm_1 = ap_CS_fsm) and not(((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (nfa_finals_buckets_rsp_empty_n = ap_const_logic_0))) and (ap_const_logic_1 = ap_ce))) then ap_ready <= ap_const_logic_1; else ap_ready <= ap_const_logic_0; end if; end process; -- ap_reg_ppiten_pp0_it0 assign process. -- ap_reg_ppiten_pp0_it0_assign_proc : process(ap_start, ap_CS_fsm, ap_reg_ppiten_pp0_it0_preg) begin if ((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm)) then ap_reg_ppiten_pp0_it0 <= ap_start; else ap_reg_ppiten_pp0_it0 <= ap_reg_ppiten_pp0_it0_preg; end if; end process; ap_return_0 <= nfa_finals_buckets_read_reg_55; ap_return_1 <= nfa_finals_buckets_datain; -- ap_sig_bdd_116 assign process. -- ap_sig_bdd_116_assign_proc : process(ap_reg_ppiten_pp0_it0, ap_ce) begin ap_sig_bdd_116 <= ((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_const_logic_1 = ap_ce)); end process; -- ap_sig_bdd_117 assign process. -- ap_sig_bdd_117_assign_proc : process(ap_start, ap_CS_fsm, ap_reg_ppiten_pp0_it0, ap_reg_ppiten_pp0_it1, nfa_finals_buckets_rsp_empty_n) begin ap_sig_bdd_117 <= ((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and (nfa_finals_buckets_rsp_empty_n = ap_const_logic_0))))); end process; -- ap_sig_bdd_119 assign process. -- ap_sig_bdd_119_assign_proc : process(ap_CS_fsm, ap_reg_ppiten_pp0_it0, nfa_finals_buckets_rsp_empty_n) begin ap_sig_bdd_119 <= ((ap_ST_pp0_stg1_fsm_1 = ap_CS_fsm) and not(((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (nfa_finals_buckets_rsp_empty_n = ap_const_logic_0)))); end process; -- ap_sig_pprstidle_pp0 assign process. -- ap_sig_pprstidle_pp0_assign_proc : process(ap_start, ap_reg_ppiten_pp0_it0) begin if (((ap_const_logic_0 = ap_reg_ppiten_pp0_it0) and (ap_const_logic_0 = ap_start))) then ap_sig_pprstidle_pp0 <= ap_const_logic_1; else ap_sig_pprstidle_pp0 <= ap_const_logic_0; end if; end process; -- nfa_finals_buckets_address assign process. -- nfa_finals_buckets_address_assign_proc : process(ap_sig_bdd_117, ap_sig_bdd_119, ap_sig_bdd_116) begin if (ap_sig_bdd_116) then if (ap_sig_bdd_119) then nfa_finals_buckets_address <= ap_const_lv32_1; elsif (ap_sig_bdd_117) then nfa_finals_buckets_address <= ap_const_lv32_0; else nfa_finals_buckets_address <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX"; end if; else nfa_finals_buckets_address <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX"; end if; end process; nfa_finals_buckets_dataout <= ap_const_lv32_0; nfa_finals_buckets_req_din <= ap_const_logic_0; -- nfa_finals_buckets_req_write assign process. -- nfa_finals_buckets_req_write_assign_proc : process(ap_start, ap_CS_fsm, ap_reg_ppiten_pp0_it0, ap_reg_ppiten_pp0_it1, nfa_finals_buckets_rsp_empty_n, ap_ce) begin if ((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_ST_pp0_stg1_fsm_1 = ap_CS_fsm) and not(((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (nfa_finals_buckets_rsp_empty_n = ap_const_logic_0))) and (ap_const_logic_1 = ap_ce)) or ((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_const_logic_1 = ap_ce) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and (nfa_finals_buckets_rsp_empty_n = ap_const_logic_0))))))) then nfa_finals_buckets_req_write <= ap_const_logic_1; else nfa_finals_buckets_req_write <= ap_const_logic_0; end if; end process; -- nfa_finals_buckets_rsp_read assign process. -- nfa_finals_buckets_rsp_read_assign_proc : process(ap_start, ap_CS_fsm, ap_reg_ppiten_pp0_it0, ap_reg_ppiten_pp0_it1, nfa_finals_buckets_rsp_empty_n, ap_ce) begin if ((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_ST_pp0_stg1_fsm_1 = ap_CS_fsm) and not(((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (nfa_finals_buckets_rsp_empty_n = ap_const_logic_0))) and (ap_const_logic_1 = ap_ce)) or ((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and (ap_const_logic_1 = ap_ce) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and (nfa_finals_buckets_rsp_empty_n = ap_const_logic_0))))))) then nfa_finals_buckets_rsp_read <= ap_const_logic_1; else nfa_finals_buckets_rsp_read <= ap_const_logic_0; end if; end process; nfa_finals_buckets_size <= ap_const_lv32_1; end behav;
lgpl-3.0
10db3fdbc601cd94018820fb1f9c8549
0.59605
2.699292
false
false
false
false
wsoltys/AtomFpga
src/MC6522/m6522_v2.vhd
1
31,376
-- -- A simulation model of VIC20 hardware -- Copyright (c) MikeJ - March 2003 -- -- All rights reserved -- -- Redistribution and use in source and synthezised forms, with or without -- modification, are permitted provided that the following conditions are met: -- -- Redistributions of source code must retain the above copyright notice, -- this list of conditions and the following disclaimer. -- -- Redistributions in synthesized form must reproduce the above copyright -- notice, this list of conditions and the following disclaimer in the -- documentation and/or other materials provided with the distribution. -- -- Neither the name of the author nor the names of other contributors may -- be used to endorse or promote products derived from this software without -- specific prior written permission. -- -- THIS CODE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, -- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR -- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE -- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -- POSSIBILITY OF SUCH DAMAGE. -- -- You are responsible for any legal issues arising from your use of this code. -- -- The latest version of this file can be found at: www.fpgaarcade.com -- -- Email [email protected] -- -- -- Revision list -- -- Arnim Laeuger, 12-Jan-2009: -- Ported to numeric_std and simulation fix for signal initializations -- version 002 fix from Mark McDougall, untested -- version 001 initial release -- not very sure about the shift register, documentation is a bit light. library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity M6522_V2 is port ( I_RS : in std_logic_vector(3 downto 0); I_DATA : in std_logic_vector(7 downto 0); O_DATA : out std_logic_vector(7 downto 0); O_DATA_OE_L : out std_logic; I_RW_L : in std_logic; I_CS1 : in std_logic; I_CS2_L : in std_logic; O_IRQ_L : out std_logic; -- note, not open drain -- port a I_CA1 : in std_logic; I_CA2 : in std_logic; O_CA2 : out std_logic; O_CA2_OE_L : out std_logic; I_PA : in std_logic_vector(7 downto 0); O_PA : out std_logic_vector(7 downto 0); O_PA_OE_L : out std_logic_vector(7 downto 0); -- port b I_CB1 : in std_logic; O_CB1 : out std_logic; O_CB1_OE_L : out std_logic; I_CB2 : in std_logic; O_CB2 : out std_logic; O_CB2_OE_L : out std_logic; I_PB : in std_logic_vector(7 downto 0); O_PB : out std_logic_vector(7 downto 0); O_PB_OE_L : out std_logic_vector(7 downto 0); I_P2_H : in std_logic; -- high for phase 2 clock ____----__ RESET_L : in std_logic; ENA_4 : in std_logic; -- clk enable CLK : in std_logic ); end; architecture RTL of M6522_V2 is signal phase : std_logic_vector(1 downto 0); signal p2_h_t1 : std_logic; signal cs : std_logic; -- registers signal r_ddra : std_logic_vector(7 downto 0); signal r_ora : std_logic_vector(7 downto 0); signal r_ira : std_logic_vector(7 downto 0); signal r_ddrb : std_logic_vector(7 downto 0); signal r_orb : std_logic_vector(7 downto 0); signal r_irb : std_logic_vector(7 downto 0); signal r_t1l_l : std_logic_vector(7 downto 0) := (others => '0'); signal r_t1l_h : std_logic_vector(7 downto 0) := (others => '0'); signal r_t2l_l : std_logic_vector(7 downto 0) := (others => '0'); signal r_t2l_h : std_logic_vector(7 downto 0) := (others => '0'); -- not in real chip signal r_sr : std_logic_vector(7 downto 0); signal r_acr : std_logic_vector(7 downto 0); signal r_pcr : std_logic_vector(7 downto 0); signal r_ifr : std_logic_vector(7 downto 0); signal r_ier : std_logic_vector(6 downto 0); signal sr_write_ena : boolean; signal sr_read_ena : boolean; signal ifr_write_ena : boolean; signal ier_write_ena : boolean; signal clear_irq : std_logic_vector(7 downto 0); signal load_data : std_logic_vector(7 downto 0); -- timer 1 signal t1c : std_logic_vector(15 downto 0) := (others => '0'); signal t1c_active : boolean; signal t1c_done : boolean; signal t1_w_reset_int : boolean; signal t1_r_reset_int : boolean; signal t1_load_counter : boolean; signal t1_reload_counter : boolean; signal t1_toggle : std_logic; signal t1_irq : std_logic := '0'; -- timer 2 signal t2c : std_logic_vector(15 downto 0) := (others => '0'); signal t2c_active : boolean; signal t2c_done : boolean; signal t2_pb6 : std_logic; signal t2_pb6_t1 : std_logic; signal t2_w_reset_int : boolean; signal t2_r_reset_int : boolean; signal t2_load_counter : boolean; signal t2_reload_counter : boolean; signal t2_irq : std_logic := '0'; signal t2_sr_ena : boolean; -- shift reg signal sr_cnt : std_logic_vector(3 downto 0); signal sr_cb1_oe_l : std_logic; signal sr_cb1_out : std_logic; signal sr_drive_cb2 : std_logic; signal sr_strobe : std_logic; signal sr_strobe_t1 : std_logic; signal sr_strobe_falling : boolean; signal sr_strobe_rising : boolean; signal sr_irq : std_logic; signal sr_out : std_logic; signal sr_off_delay : std_logic; -- io signal w_orb_hs : std_logic; signal w_ora_hs : std_logic; signal r_irb_hs : std_logic; signal r_ira_hs : std_logic; signal ca_hs_sr : std_logic; signal ca_hs_pulse : std_logic; signal cb_hs_sr : std_logic; signal cb_hs_pulse : std_logic; signal cb1_in_mux : std_logic; signal ca1_ip_reg : std_logic; signal cb1_ip_reg : std_logic; signal ca1_int : boolean; signal cb1_int : boolean; signal ca1_irq : std_logic; signal cb1_irq : std_logic; signal ca2_ip_reg : std_logic; signal cb2_ip_reg : std_logic; signal ca2_int : boolean; signal cb2_int : boolean; signal ca2_irq : std_logic; signal cb2_irq : std_logic; signal final_irq : std_logic; begin p_phase : process begin -- internal clock phase wait until rising_edge(CLK); if (ENA_4 = '1') then p2_h_t1 <= I_P2_H; if (p2_h_t1 = '0') and (I_P2_H = '1') then phase <= "11"; else phase <= std_logic_vector(unsigned(phase) + 1); end if; end if; end process; p_cs : process(I_CS1, I_CS2_L, I_P2_H) begin cs <= '0'; if (I_CS1 = '1') and (I_CS2_L = '0') and (I_P2_H = '1') then cs <= '1'; end if; end process; -- peripheral control reg (pcr) -- 0 ca1 interrupt control (0 +ve edge, 1 -ve edge) -- 3..1 ca2 operation -- 000 input -ve edge -- 001 independend interrupt input -ve edge -- 010 input +ve edge -- 011 independend interrupt input +ve edge -- 100 handshake output -- 101 pulse output -- 110 low output -- 111 high output -- 7..4 as 3..0 for cb1,cb2 -- auxiliary control reg (acr) -- 0 input latch PA (0 disable, 1 enable) -- 1 input latch PB (0 disable, 1 enable) -- 4..2 shift reg control -- 000 disable -- 001 shift in using t2 -- 010 shift in using o2 -- 011 shift in using ext clk -- 100 shift out free running t2 rate -- 101 shift out using t2 -- 101 shift out using o2 -- 101 shift out using ext clk -- 5 t2 timer control (0 timed interrupt, 1 count down with pulses on pb6) -- 7..6 t1 timer control -- 00 timed interrupt each time t1 is loaded pb7 disable -- 01 continuous interrupts pb7 disable -- 00 timed interrupt each time t1 is loaded pb7 one shot output -- 01 continuous interrupts pb7 square wave output -- p_write_reg_reset : process(RESET_L, CLK) begin if (RESET_L = '0') then r_ora <= x"00"; r_orb <= x"00"; r_ddra <= x"00"; r_ddrb <= x"00"; r_acr <= x"00"; r_pcr <= x"00"; w_orb_hs <= '0'; w_ora_hs <= '0'; elsif rising_edge(CLK) then if (ENA_4 = '1') then w_orb_hs <= '0'; w_ora_hs <= '0'; if (cs = '1') and (I_RW_L = '0') then case I_RS is when x"0" => r_orb <= I_DATA; w_orb_hs <= '1'; when x"1" => r_ora <= I_DATA; w_ora_hs <= '1'; when x"2" => r_ddrb <= I_DATA; when x"3" => r_ddra <= I_DATA; when x"B" => r_acr <= I_DATA; when x"C" => r_pcr <= I_DATA; when x"F" => r_ora <= I_DATA; when others => null; end case; end if; if (r_acr(7) = '1') and (t1_toggle = '1') then r_orb(7) <= not r_orb(7); -- toggle end if; end if; end if; end process; p_write_reg : process begin wait until rising_edge(CLK); if (ENA_4 = '1') then t1_w_reset_int <= false; t1_load_counter <= false; t2_w_reset_int <= false; t2_load_counter <= false; load_data <= x"00"; sr_write_ena <= false; ifr_write_ena <= false; ier_write_ena <= false; if (cs = '1') and (I_RW_L = '0') then load_data <= I_DATA; case I_RS is when x"4" => r_t1l_l <= I_DATA; when x"5" => r_t1l_h <= I_DATA; t1_w_reset_int <= true; t1_load_counter <= true; when x"6" => r_t1l_l <= I_DATA; when x"7" => r_t1l_h <= I_DATA; t1_w_reset_int <= true; when x"8" => r_t2l_l <= I_DATA; when x"9" => r_t2l_h <= I_DATA; t2_w_reset_int <= true; t2_load_counter <= true; when x"A" => sr_write_ena <= true; when x"D" => ifr_write_ena <= true; when x"E" => ier_write_ena <= true; when others => null; end case; end if; end if; end process; p_oe : process(cs, I_RW_L) begin O_DATA_OE_L <= '1'; if (cs = '1') and (I_RW_L = '1') then O_DATA_OE_L <= '0'; end if; end process; p_read : process(cs, I_RW_L, I_RS, r_irb, r_ira, r_ddrb, r_ddra, t1c, r_t1l_l, r_t1l_h, t2c, r_sr, r_acr, r_pcr, r_ifr, r_ier, r_orb) begin t1_r_reset_int <= false; t2_r_reset_int <= false; sr_read_ena <= false; r_irb_hs <= '0'; r_ira_hs <= '0'; O_DATA <= x"00"; -- default if (cs = '1') and (I_RW_L = '1') then case I_RS is --when x"0" => O_DATA <= r_irb; r_irb_hs <= '1'; -- fix from Mark McDougall, untested when x"0" => O_DATA <= (r_irb and not r_ddrb) or (r_orb and r_ddrb); r_irb_hs <= '1'; --when x"1" => O_DATA <= r_ira; r_ira_hs <= '1'; when x"1" => O_DATA <= (r_ira and not r_ddra) or (r_ora and r_ddra); r_ira_hs <= '1'; when x"2" => O_DATA <= r_ddrb; when x"3" => O_DATA <= r_ddra; when x"4" => O_DATA <= t1c(7 downto 0); t1_r_reset_int <= true; when x"5" => O_DATA <= t1c(15 downto 8); when x"6" => O_DATA <= r_t1l_l; when x"7" => O_DATA <= r_t1l_h; when x"8" => O_DATA <= t2c(7 downto 0); t2_r_reset_int <= true; when x"9" => O_DATA <= t2c(15 downto 8); when x"A" => O_DATA <= r_sr; sr_read_ena <= true; when x"B" => O_DATA <= r_acr; when x"C" => O_DATA <= r_pcr; when x"D" => O_DATA <= r_ifr; when x"E" => O_DATA <= ('0' & r_ier); when x"F" => O_DATA <= r_ira; when others => null; end case; end if; end process; -- -- IO -- p_ca1_cb1_sel : process(sr_cb1_oe_l, sr_cb1_out, I_CB1) begin -- if the shift register is enabled, cb1 may be an output -- in this case, we should listen to the CB1_OUT for the interrupt if (sr_cb1_oe_l = '1') then cb1_in_mux <= I_CB1; else cb1_in_mux <= sr_cb1_out; end if; end process; p_ca1_cb1_int : process(r_pcr, ca1_ip_reg, I_CA1, cb1_ip_reg, cb1_in_mux) begin if (r_pcr(0) = '0') then -- ca1 control -- negative edge ca1_int <= (ca1_ip_reg = '1') and (I_CA1 = '0'); else -- positive edge ca1_int <= (ca1_ip_reg = '0') and (I_CA1 = '1'); end if; if (r_pcr(4) = '0') then -- cb1 control -- negative edge cb1_int <= (cb1_ip_reg = '1') and (cb1_in_mux = '0'); else -- positive edge cb1_int <= (cb1_ip_reg = '0') and (cb1_in_mux = '1'); end if; end process; p_ca2_cb2_int : process(r_pcr, ca2_ip_reg, I_CA2, cb2_ip_reg, I_CB2) begin ca2_int <= false; if (r_pcr(3) = '0') then -- ca2 input if (r_pcr(2) = '0') then -- ca2 edge -- negative edge ca2_int <= (ca2_ip_reg = '1') and (I_CA2 = '0'); else -- positive edge ca2_int <= (ca2_ip_reg = '0') and (I_CA2 = '1'); end if; end if; cb2_int <= false; if (r_pcr(7) = '0') then -- cb2 input if (r_pcr(6) = '0') then -- cb2 edge -- negative edge cb2_int <= (cb2_ip_reg = '1') and (I_CB2 = '0'); else -- positive edge cb2_int <= (cb2_ip_reg = '0') and (I_CB2 = '1'); end if; end if; end process; p_ca2_cb2 : process(RESET_L, CLK) begin if (RESET_L = '0') then O_CA2 <= '0'; O_CA2_OE_L <= '1'; O_CB2 <= '0'; O_CB2_OE_L <= '1'; ca_hs_sr <= '0'; ca_hs_pulse <= '0'; cb_hs_sr <= '0'; cb_hs_pulse <= '0'; elsif rising_edge(CLK) then if (ENA_4 = '1') then -- ca if (phase = "00") and ((w_ora_hs = '1') or (r_ira_hs = '1')) then ca_hs_sr <= '1'; elsif ca1_int then ca_hs_sr <= '0'; end if; if (phase = "00") then ca_hs_pulse <= w_ora_hs or r_ira_hs; end if; O_CA2_OE_L <= not r_pcr(3); -- ca2 output case r_pcr(3 downto 1) is when "000" => O_CA2 <= '0'; -- input when "001" => O_CA2 <= '0'; -- input when "010" => O_CA2 <= '0'; -- input when "011" => O_CA2 <= '0'; -- input when "100" => O_CA2 <= not (ca_hs_sr); -- handshake when "101" => O_CA2 <= not (ca_hs_pulse); -- pulse when "110" => O_CA2 <= '0'; -- low when "111" => O_CA2 <= '1'; -- high when others => null; end case; -- cb if (phase = "00") and (w_orb_hs = '1') then cb_hs_sr <= '1'; elsif cb1_int then cb_hs_sr <= '0'; end if; if (phase = "00") then cb_hs_pulse <= w_orb_hs; end if; O_CB2_OE_L <= not (r_pcr(7) or sr_drive_cb2); -- cb2 output or serial if (sr_drive_cb2 = '1') then -- serial output O_CB2 <= sr_out; else case r_pcr(7 downto 5) is when "000" => O_CB2 <= '0'; -- input when "001" => O_CB2 <= '0'; -- input when "010" => O_CB2 <= '0'; -- input when "011" => O_CB2 <= '0'; -- input when "100" => O_CB2 <= not (cb_hs_sr); -- handshake when "101" => O_CB2 <= not (cb_hs_pulse); -- pulse when "110" => O_CB2 <= '0'; -- low when "111" => O_CB2 <= '1'; -- high when others => null; end case; end if; end if; end if; end process; O_CB1 <= sr_cb1_out; O_CB1_OE_L <= sr_cb1_oe_l; p_ca_cb_irq : process(RESET_L, CLK) begin if (RESET_L = '0') then ca1_irq <= '0'; ca2_irq <= '0'; cb1_irq <= '0'; cb2_irq <= '0'; elsif rising_edge(CLK) then if (ENA_4 = '1') then -- not pretty if ca1_int then ca1_irq <= '1'; elsif (r_ira_hs = '1') or (w_ora_hs = '1') or (clear_irq(1) = '1') then ca1_irq <= '0'; end if; if ca2_int then ca2_irq <= '1'; else if (((r_ira_hs = '1') or (w_ora_hs = '1')) and (r_pcr(1) = '0')) or (clear_irq(0) = '1') then ca2_irq <= '0'; end if; end if; if cb1_int then cb1_irq <= '1'; elsif (r_irb_hs = '1') or (w_orb_hs = '1') or (clear_irq(4) = '1') then cb1_irq <= '0'; end if; if cb2_int then cb2_irq <= '1'; else if (((r_irb_hs = '1') or (w_orb_hs = '1')) and (r_pcr(5) = '0')) or (clear_irq(3) = '1') then cb2_irq <= '0'; end if; end if; end if; end if; end process; p_input_reg : process(RESET_L, CLK) begin if (RESET_L = '0') then ca1_ip_reg <= '0'; cb1_ip_reg <= '0'; ca2_ip_reg <= '0'; cb2_ip_reg <= '0'; r_ira <= x"00"; r_irb <= x"00"; elsif rising_edge(CLK) then if (ENA_4 = '1') then -- we have a fast clock, so we can have input registers ca1_ip_reg <= I_CA1; cb1_ip_reg <= cb1_in_mux; ca2_ip_reg <= I_CA2; cb2_ip_reg <= I_CB2; if (r_acr(0) = '0') then r_ira <= I_PA; else -- enable latching if ca1_int then r_ira <= I_PA; end if; end if; if (r_acr(1) = '0') then r_irb <= I_PB; else -- enable latching if cb1_int then r_irb <= I_PB; end if; end if; end if; end if; end process; p_buffers : process(r_ddra, r_ora, r_ddrb, r_acr, r_orb) begin -- data direction reg (ddr) 0 = input, 1 = output O_PA <= r_ora; O_PA_OE_L <= not r_ddra; if (r_acr(7) = '1') then -- not clear if r_ddrb(7) must be 1 as well O_PB_OE_L(7) <= '0'; -- an output if under t1 control else O_PB_OE_L(7) <= not (r_ddrb(7)); end if; O_PB_OE_L(6 downto 0) <= not r_ddrb(6 downto 0); O_PB(7 downto 0) <= r_orb(7 downto 0); end process; -- -- Timer 1 -- p_timer1_done : process variable done : boolean; begin wait until rising_edge(CLK); if (ENA_4 = '1') then done := (t1c = x"0000"); t1c_done <= done and (phase = "11"); if (phase = "11") then t1_reload_counter <= done and (r_acr(6) = '1'); end if; end if; end process; p_timer1 : process begin wait until rising_edge(CLK); if (ENA_4 = '1') then if t1_load_counter or (t1_reload_counter and phase = "11") then t1c(7 downto 0) <= r_t1l_l; t1c(15 downto 8) <= r_t1l_h; elsif (phase = "11") then t1c <= std_logic_vector(unsigned(t1c) - 1); end if; if t1_load_counter or t1_reload_counter then t1c_active <= true; elsif t1c_done then t1c_active <= false; end if; t1_toggle <= '0'; if t1c_active and t1c_done then t1_toggle <= '1'; t1_irq <= '1'; elsif t1_w_reset_int or t1_r_reset_int or (clear_irq(6) = '1') then t1_irq <= '0'; end if; end if; end process; -- -- Timer2 -- p_timer2_pb6_input : process begin wait until rising_edge(CLK); if (ENA_4 = '1') then if (phase = "01") then -- leading edge p2_h t2_pb6 <= I_PB(6); t2_pb6_t1 <= t2_pb6; end if; end if; end process; p_timer2_done : process variable done : boolean; begin wait until rising_edge(CLK); if (ENA_4 = '1') then done := (t2c = x"0000"); t2c_done <= done and (phase = "11"); if (phase = "11") then t2_reload_counter <= done; end if; end if; end process; p_timer2 : process variable ena : boolean; begin wait until rising_edge(CLK); if (ENA_4 = '1') then if (r_acr(5) = '0') then ena := true; else ena := (t2_pb6_t1 = '1') and (t2_pb6 = '0'); -- falling edge end if; if t2_load_counter or (t2_reload_counter and phase = "11") then -- not sure if t2c_reload should be here. Does timer2 just continue to -- count down, or is it reloaded ? Reloaded makes more sense if using -- it to generate a clock for the shift register. t2c(7 downto 0) <= r_t2l_l; t2c(15 downto 8) <= r_t2l_h; else if (phase = "11") and ena then -- or count mode t2c <= std_logic_vector(unsigned(t2c) - 1); end if; end if; t2_sr_ena <= (t2c(7 downto 0) = x"00") and (phase = "11"); if t2_load_counter then t2c_active <= true; elsif t2c_done then t2c_active <= false; end if; if t2c_active and t2c_done then t2_irq <= '1'; elsif t2_w_reset_int or t2_r_reset_int or (clear_irq(5) = '1') then t2_irq <= '0'; end if; end if; end process; -- -- Shift Register -- p_sr : process(RESET_L, CLK) variable dir_out : std_logic; variable ena : std_logic; variable cb1_op : std_logic; variable cb1_ip : std_logic; variable use_t2 : std_logic; variable free_run : std_logic; variable sr_count_ena : boolean; begin if (RESET_L = '0') then r_sr <= x"00"; sr_drive_cb2 <= '0'; sr_cb1_oe_l <= '1'; sr_cb1_out <= '0'; sr_strobe <= '1'; sr_cnt <= "0000"; sr_irq <= '0'; sr_out <= '1'; sr_off_delay <= '0'; elsif rising_edge(CLK) then if (ENA_4 = '1') then -- decode mode dir_out := r_acr(4); -- output on cb2 cb1_op := '0'; cb1_ip := '0'; use_t2 := '0'; free_run := '0'; case r_acr(4 downto 2) is when "000" => ena := '0'; when "001" => ena := '1'; cb1_op := '1'; use_t2 := '1'; when "010" => ena := '1'; cb1_op := '1'; when "011" => ena := '1'; cb1_ip := '1'; when "100" => ena := '1'; use_t2 := '1'; free_run := '1'; when "101" => ena := '1'; cb1_op := '1'; use_t2 := '1'; when "110" => ena := '1'; free_run := '1'; -- hack when "111" => ena := '1'; cb1_ip := '1'; when others => null; end case; -- clock select if (ena = '0') then sr_strobe <= '1'; else if (cb1_ip = '1') then sr_strobe <= I_CB1; else if (sr_cnt(3) = '0') and (free_run = '0') then sr_strobe <= '1'; else if ((use_t2 = '1') and t2_sr_ena) or ((use_t2 = '0') and (phase = "00")) then sr_strobe <= not sr_strobe; end if; end if; end if; end if; -- latch on rising edge, shift on falling edge if sr_write_ena then r_sr <= load_data; elsif (ena = '1') then -- use shift reg if (dir_out = '0') then -- input if (sr_cnt(3) = '1') or (cb1_ip = '1') then if sr_strobe_rising then r_sr(0) <= I_CB2; elsif sr_strobe_falling then r_sr(7 downto 1) <= r_sr(6 downto 0); end if; end if; sr_out <= '1'; else -- output if (sr_cnt(3) = '1') or (sr_off_delay = '1') or (cb1_ip = '1') or (free_run = '1') then if sr_strobe_falling then r_sr(7 downto 1) <= r_sr(6 downto 0); r_sr(0) <= r_sr(7); sr_out <= r_sr(7); end if; else sr_out <= '1'; end if; end if; end if; sr_count_ena := sr_strobe_rising; if sr_write_ena or sr_read_ena then -- some documentation says sr bit in IFR must be set as well ? sr_cnt <= "1000"; elsif sr_count_ena and (sr_cnt(3) = '1') then sr_cnt <= std_logic_vector(unsigned(sr_cnt) + 1); end if; if (phase = "00") then sr_off_delay <= sr_cnt(3); -- give some hold time when shifting out end if; if sr_count_ena and (sr_cnt = "1111") and (ena = '1') and (free_run = '0') then sr_irq <= '1'; elsif sr_write_ena or sr_read_ena or (clear_irq(2) = '1') then sr_irq <= '0'; end if; -- assign ops sr_drive_cb2 <= dir_out; sr_cb1_oe_l <= not cb1_op; sr_cb1_out <= sr_strobe; end if; end if; end process; p_sr_strobe_rise_fall : process begin wait until rising_edge(CLK); if (ENA_4 = '1') then sr_strobe_t1 <= sr_strobe; sr_strobe_rising <= (sr_strobe_t1 = '0') and (sr_strobe = '1'); sr_strobe_falling <= (sr_strobe_t1 = '1') and (sr_strobe = '0'); end if; end process; -- -- Interrupts -- p_ier : process(RESET_L, CLK) begin if (RESET_L = '0') then r_ier <= "0000000"; elsif rising_edge(CLK) then if (ENA_4 = '1') then if ier_write_ena then if (load_data(7) = '1') then -- set r_ier <= r_ier or load_data(6 downto 0); else -- clear r_ier <= r_ier and not load_data(6 downto 0); end if; end if; end if; end if; end process; p_ifr : process(t1_irq, t2_irq, final_irq, ca1_irq, ca2_irq, sr_irq, cb1_irq, cb2_irq) begin r_ifr(7) <= final_irq; r_ifr(6) <= t1_irq; r_ifr(5) <= t2_irq; r_ifr(4) <= cb1_irq; r_ifr(3) <= cb2_irq; r_ifr(2) <= sr_irq; r_ifr(1) <= ca1_irq; r_ifr(0) <= ca2_irq; O_IRQ_L <= not final_irq; end process; p_irq : process(RESET_L, CLK) begin if (RESET_L = '0') then final_irq <= '0'; elsif rising_edge(CLK) then if (ENA_4 = '1') then if ((r_ifr(6 downto 0) and r_ier(6 downto 0)) = "0000000") then final_irq <= '0'; -- no interrupts else final_irq <= '1'; end if; end if; end if; end process; p_clear_irq : process(ifr_write_ena, load_data) begin clear_irq <= x"00"; if ifr_write_ena then clear_irq <= load_data; end if; end process; end architecture RTL;
apache-2.0
a1c29cedf3f2683e7e4db7f4d337a229
0.429946
3.457791
false
false
false
false
MrDoomBringer/DSD-Labs
Lab 5/Lab5.vhd
1
1,670
LIBRARY ieee; USE ieee.std_logic_1164.ALL; USE ieee.numeric_std.ALL; USE ieee.std_logic_signed.ALL; ENTITY quad_bit_alu IS port( a: IN SIGNED (3 DOWNTO 0); b: IN SIGNED (3 DOWNTO 0); s: IN UNSIGNED (2 DOWNTO 0); z: OUT std_logic; r: OUT SIGNED (7 DOWNTO 0) ); END quad_bit_alu; ARCHITECTURE alu OF quad_bit_alu IS SIGNAL a_pad: SIGNED (7 DOWNTO 0); SIGNAL b_pad: SIGNED (7 DOWNTO 0); SIGNAL r_buff: SIGNED (7 DOWNTO 0); BEGIN -- Pad A pad_a: PROCESS(a) VARIABLE sign : std_logic; BEGIN sign:= a(3); IF (sign = '0') THEN a_pad <= ("0000" & a); ELSIF (sign = '1') THEN a_pad <= ("1111" & a); ELSE a_pad <= "00000000"; END IF; END PROCESS pad_a; -- Pad B pad_b: PROCESS(b) VARIABLE sign : std_logic; BEGIN sign:= b(3); IF (sign = '0') THEN b_pad <= ("0000" & b); ELSIF (sign = '1') THEN b_pad <= ("1111" & b); ELSE b_pad <= "00000000"; END IF; END PROCESS pad_b; -- Main ALU process op_select: PROCESS(s, a_pad, b_pad, a, b) BEGIN CASE s IS WHEN "000" => r_buff <= (a_pad AND b_pad); WHEN "001" => r_buff <= (a_pad OR b_pad); WHEN "010" => r_buff <= (a_pad XOR b_pad); WHEN "011" => r_buff <= (NOT a_pad); WHEN "100" => r_buff <= (a_pad + b_pad); WHEN "101" => r_buff <= (a_pad - b_pad); WHEN "110" => r_buff <= (a * b); WHEN "111" => r_buff <= (NOT(a_pad) + "00000001"); WHEN OTHERS => r_buff <= "00000000"; END CASE; END PROCESS op_select; -- Handle zero out condition zero_out:PROCESS (r_buff) BEGIN CASE r_buff IS WHEN "00000000" => z <= '1'; WHEN others => z <= '0'; END CASE; r <= r_buff; END PROCESS zero_out; END alu;
mit
0dcf8f9e59dd5220b3d7d92703d34816
0.562275
2.445095
false
false
false
false
grwlf/vsim
vhdl_ct/ct00330.vhd
1
5,947
-- NEED RESULT: ARCH00330_Test_Bench: Component may be instantiated more than once passed ------------------------------------------------------------------------------- -- -- Copyright (c) 1989 by Intermetrics, Inc. -- All rights reserved. -- ------------------------------------------------------------------------------- -- -- TEST NAME: -- -- CT00330 -- -- AUTHOR: -- -- G. Tominovich -- -- TEST OBJECTIVES: -- -- 9.6 (2) -- -- DESIGN UNIT ORDERING: -- -- ENT00330_1(ARCH00330_1) -- ENT00330_2(ARCH00330_2) -- ENT00330_Test_Bench(ARCH00330_Test_Bench) -- -- REVISION HISTORY: -- -- 30-JUL-1987 - initial revision -- 22-JUN-1988 - (KLM) added initialization expression for port Q in -- entities ENT00330_1 and ENT00330_2 -- -- NOTES: -- -- self-checking -- -- entity ENT00330_1 is generic ( G : Integer := 2 ) ; port ( P : in Integer := 1 ; Q : out Integer := 1 ) ; end ENT00330_1 ; architecture ARCH00330_1 of ENT00330_1 is begin P1 : process ( P ) variable First_Time : boolean := True ; begin if First_Time then First_Time := False ; else Q <= transport P*G after 10 ns ; end if ; end process P1 ; end ARCH00330_1 ; entity ENT00330_2 is generic ( G : REAL := 2.0 ) ; port ( P : in REAL := 1.0 ; Q : out REAL := 1.0 ) ; end ENT00330_2 ; architecture ARCH00330_2 of ENT00330_2 is begin P1 : process ( P ) variable First_Time : boolean := True ; begin if First_Time then First_Time := False ; else Q <= transport P*G after 10 ns ; end if ; end process P1 ; end ARCH00330_2 ; entity ENT00330_Test_Bench is end ENT00330_Test_Bench ; use WORK.STANDARD_TYPES.all ; architecture ARCH00330_Test_Bench of ENT00330_Test_Bench is begin L1: block function To_Int ( P : in Real ) return Integer is variable exp : Integer := 0 ; variable val, tempr : Real ; variable Result, tempi : Integer := 0 ; begin val := abs P ; while val >= 10.0 loop exp := exp + 1 ; val := val / 10.0 ; end loop ; loop if val < 1.0 then tempi := 0 ; tempr := 0.0 ; elsif val < 2.0 then tempi := 1 ; tempr := 1.0 ; elsif val < 3.0 then tempi := 2 ; tempr := 2.0 ; elsif val < 4.0 then tempi := 3 ; tempr := 3.0 ; elsif val < 5.0 then tempi := 4 ; tempr := 4.0 ; elsif val < 6.0 then tempi := 5 ; tempr := 5.0 ; elsif val < 7.0 then tempi := 6 ; tempr := 6.0 ; elsif val < 8.0 then tempi := 7 ; tempr := 7.0 ; elsif val < 9.0 then tempi := 8 ; tempr := 8.0 ; else tempi := 9 ; tempr := 9.0 ; end if ; result := result*10 + tempi ; exit when exp = 0 ; exp := exp - 1 ; val := (val - tempr)*10.0 ; end loop ; if P < 0.0 then return -1 * result ; else return result ; end if ; end To_Int ; function To_Real ( P : in Integer ) return Real is variable exp : Integer := 0 ; variable val, tempi, tempv : Integer ; variable Result, tempr : Real := 0.0 ; begin val := abs P ; loop tempv := val / 10 ; tempi := val - tempv*10; case tempi is when 0 => tempr := 0.0 ; when 1 => tempr := 1.0 ; when 2 => tempr := 2.0 ; when 3 => tempr := 3.0 ; when 4 => tempr := 4.0 ; when 5 => tempr := 5.0 ; when 6 => tempr := 6.0 ; when 7 => tempr := 7.0 ; when 8 => tempr := 8.0 ; when 9 => tempr := 9.0 ; when others => null ; end case ; result := result + tempr*(10.0**exp) ; exit when val < 10 ; val := tempv ; exp := exp + 1 ; end loop ; if P < 0 then return -1.0 * result ; else return result ; end if ; end To_Real ; component UUT1 generic ( G : Integer := 2) ; port ( P : in Integer ; Q : out Integer ) ; end component ; component UUT2 generic ( G : REAL := 2.0 ) ; port ( P : in REAL ; Q : out REAL ) ; end component ; for all : UUT1 use entity WORK.ENT00330_1 ( ARCH00330_1 ) ; for all : UUT2 use entity WORK.ENT00330_2 ( ARCH00330_2 ) ; signal In1 : Integer := -1 ; signal Out1, Out3, Out4 : Integer := 0 ; signal Out2 : Real := -1.0 ; signal Check : boolean := false; begin In1 <= transport 1 after 10 ns ; -- Get the ball rolling CIS1 : UUT1 generic map ( 3 ) port map ( In1 , -- 1 Out1 ) ; -- 3 CIS2 : UUT2 generic map ( G => 3.0 ) port map ( Q => Out2 , -- 9.0 P => To_Real (Out1) ) ; -- 3.0 CIS3 : UUT1 generic map ( open ) -- 2 port map ( To_Int ( Out2 ) , -- 9 Out3 ) ; -- 18 CIS4 : UUT2 generic map ( open ) -- 2.0 port map ( To_Int (Q) => Out4 , -- 36.0 P => To_Real (Out3) ) ; -- 18.0 Check <= transport true after 100 ns ; Check_it : process ( Check ) variable First_Time : boolean := true ; begin if First_Time then First_Time := false ; else test_report ( "ARCH00330_Test_Bench" , "Component may be instantiated more than once" , Out4 = 36 ) ; end if ; end process Check_it ; end block L1 ; end ARCH00330_Test_Bench ;
gpl-3.0
5da972dc08f773613676c6944d2c2e3b
0.453338
3.548329
false
false
false
false
grwlf/vsim
vhdl_ct/ct00418.vhd
1
7,606
-- NEED RESULT: ARCH00418.P1: Multi inertial transactions occurred on concurrent signal asg passed -- NEED RESULT: ARCH00418: One inertial transaction occurred on a concurrent signal asg passed -- NEED RESULT: ARCH00418: Old transactions were removed on a concurrent signal asg passed -- NEED RESULT: ARCH00418: One inertial transaction occurred on a concurrent signal asg passed -- NEED RESULT: ARCH00418: Inertial semantics check on a concurrent signal asg passed -- NEED RESULT: P1: Inertial transactions completed entirely passed ------------------------------------------------------------------------------- -- -- Copyright (c) 1989 by Intermetrics, Inc. -- All rights reserved. -- ------------------------------------------------------------------------------- -- -- TEST NAME: -- -- CT00418 -- -- AUTHOR: -- -- G. Tominovich -- -- TEST OBJECTIVES: -- -- 9.5 (3) -- 9.5.1 (1) -- 9.5.1 (2) -- -- DESIGN UNIT ORDERING: -- -- ENT00418(ARCH00418) -- ENT00418_Test_Bench(ARCH00418_Test_Bench) -- -- REVISION HISTORY: -- -- 30-JUL-1987 - initial revision -- -- NOTES: -- -- self-checking -- automatically generated -- use WORK.STANDARD_TYPES.all ; entity ENT00418 is end ENT00418 ; -- -- architecture ARCH00418 of ENT00418 is subtype chk_sig_type is integer range -1 to 100 ; signal chk_st_rec3 : chk_sig_type := -1 ; -- subtype chk_time_type is Time ; signal s_st_rec3_savt : chk_time_type := 0 ns ; -- subtype chk_cnt_type is Integer ; signal s_st_rec3_cnt : chk_cnt_type := 0 ; -- type select_type is range 1 to 6 ; signal st_rec3_select : select_type := 1 ; -- signal s_st_rec3 : st_rec3 := c_st_rec3_1 ; -- begin CHG1 : process variable correct : boolean ; begin case s_st_rec3_cnt is when 0 => null ; -- s_st_rec3.f2.f2 <= -- c_st_rec3_2.f2.f2 after 10 ns, -- c_st_rec3_1.f2.f2 after 20 ns ; -- when 1 => correct := s_st_rec3.f2.f2 = c_st_rec3_2.f2.f2 and (s_st_rec3_savt + 10 ns) = Std.Standard.Now ; -- when 2 => correct := correct and s_st_rec3.f2.f2 = c_st_rec3_1.f2.f2 and (s_st_rec3_savt + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00418.P1" , "Multi inertial transactions occurred on " & "concurrent signal asg", correct ) ; -- st_rec3_select <= transport 2 ; -- s_st_rec3.f2.f2 <= -- c_st_rec3_2.f2.f2 after 10 ns , -- c_st_rec3_1.f2.f2 after 20 ns , -- c_st_rec3_2.f2.f2 after 30 ns , -- c_st_rec3_1.f2.f2 after 40 ns ; -- when 3 => correct := s_st_rec3.f2.f2 = c_st_rec3_2.f2.f2 and (s_st_rec3_savt + 10 ns) = Std.Standard.Now ; st_rec3_select <= transport 3 ; -- s_st_rec3.f2.f2 <= -- c_st_rec3_1.f2.f2 after 5 ns ; -- when 4 => correct := correct and s_st_rec3.f2.f2 = c_st_rec3_1.f2.f2 and (s_st_rec3_savt + 5 ns) = Std.Standard.Now ; test_report ( "ARCH00418" , "One inertial transaction occurred on a " & "concurrent signal asg", correct ) ; st_rec3_select <= transport 4 ; -- s_st_rec3.f2.f2 <= -- c_st_rec3_1.f2.f2 after 100 ns ; -- when 5 => correct := correct and s_st_rec3.f2.f2 = c_st_rec3_1.f2.f2 and (s_st_rec3_savt + 100 ns) = Std.Standard.Now ; test_report ( "ARCH00418" , "Old transactions were removed on a " & "concurrent signal asg", correct ) ; st_rec3_select <= transport 5 ; -- s_st_rec3.f2.f2 <= -- c_st_rec3_2.f2.f2 after 10 ns , -- c_st_rec3_1.f2.f2 after 20 ns , -- c_st_rec3_2.f2.f2 after 30 ns , -- c_st_rec3_1.f2.f2 after 40 ns ; -- when 6 => correct := correct and s_st_rec3.f2.f2 = c_st_rec3_2.f2.f2 and (s_st_rec3_savt + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00418" , "One inertial transaction occurred on a " & "concurrent signal asg", correct ) ; st_rec3_select <= transport 6 ; -- Last transaction above is marked -- s_st_rec3.f2.f2 <= -- c_st_rec3_1.f2.f2 after 40 ns ; -- when 7 => correct := correct and s_st_rec3.f2.f2 = c_st_rec3_1.f2.f2 and (s_st_rec3_savt + 30 ns) = Std.Standard.Now ; -- when 8 => correct := correct and s_st_rec3.f2.f2 = c_st_rec3_1.f2.f2 and (s_st_rec3_savt + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00418" , "Inertial semantics check on a concurrent " & "signal asg", correct ) ; -- when others => -- No more transactions should have occurred test_report ( "ARCH00418" , "Inertial semantics check on a concurrent " & "signal asg", false ) ; -- end case ; -- s_st_rec3_savt <= transport Std.Standard.Now ; chk_st_rec3 <= transport s_st_rec3_cnt after (1 us - Std.Standard.Now) ; s_st_rec3_cnt <= transport s_st_rec3_cnt + 1 ; wait until (not s_st_rec3.f2.f2'Quiet) and (s_st_rec3_savt /= Std.Standard.Now) ; -- end process CHG1 ; -- PGEN_CHKP_1 : process ( chk_st_rec3 ) begin if Std.Standard.Now > 0 ns then test_report ( "P1" , "Inertial transactions completed entirely", chk_st_rec3 = 8 ) ; end if ; end process PGEN_CHKP_1 ; -- -- s_st_rec3.f2.f2 <= c_st_rec3_2.f2.f2 after 10 ns, c_st_rec3_1.f2.f2 after 20 ns when st_rec3_select = 1 else -- c_st_rec3_2.f2.f2 after 10 ns , c_st_rec3_1.f2.f2 after 20 ns , c_st_rec3_2.f2.f2 after 30 ns , c_st_rec3_1.f2.f2 after 40 ns when st_rec3_select = 2 else -- c_st_rec3_1.f2.f2 after 5 ns when st_rec3_select = 3 else -- c_st_rec3_1.f2.f2 after 100 ns when st_rec3_select = 4 else -- c_st_rec3_2.f2.f2 after 10 ns , c_st_rec3_1.f2.f2 after 20 ns , c_st_rec3_2.f2.f2 after 30 ns , c_st_rec3_1.f2.f2 after 40 ns when st_rec3_select = 5 else -- -- Last transaction above is marked c_st_rec3_1.f2.f2 after 40 ns ; -- end ARCH00418 ; -- -- use WORK.STANDARD_TYPES.all ; entity ENT00418_Test_Bench is end ENT00418_Test_Bench ; -- -- architecture ARCH00418_Test_Bench of ENT00418_Test_Bench is begin L1: block component UUT end component ; -- for CIS1 : UUT use entity WORK.ENT00418 ( ARCH00418 ) ; begin CIS1 : UUT ; end block L1 ; end ARCH00418_Test_Bench ;
gpl-3.0
3aaa7c8b185a606e6f401a9f83ce18d1
0.480016
3.154708
false
true
false
false
TWW12/lzw
ip_repo/axi_compression_1.0/src/input_fifo/input_fifo_sim_netlist.vhdl
2
172,274
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved. -- -------------------------------------------------------------------------------- -- Tool Version: Vivado v.2016.4 (win64) Build 1756540 Mon Jan 23 19:11:23 MST 2017 -- Date : Fri Mar 31 09:04:41 2017 -- Host : Shaun running 64-bit major release (build 9200) -- Command : write_vhdl -force -mode funcsim -- c:/Users/Shaun/Desktop/ip_repo/axi_compression_1.0/src/input_fifo/input_fifo_sim_netlist.vhdl -- Design : input_fifo -- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or -- synthesized. This netlist cannot be used for SDF annotated simulation. -- Device : xc7z020clg484-1 -- -------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity input_fifo_blk_mem_gen_prim_wrapper is port ( D : out STD_LOGIC_VECTOR ( 7 downto 0 ); clk : in STD_LOGIC; WEA : in STD_LOGIC_VECTOR ( 0 to 0 ); tmp_ram_rd_en : in STD_LOGIC; srst : in STD_LOGIC; Q : in STD_LOGIC_VECTOR ( 9 downto 0 ); \gc0.count_d1_reg[9]\ : in STD_LOGIC_VECTOR ( 9 downto 0 ); din : in STD_LOGIC_VECTOR ( 7 downto 0 ) ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of input_fifo_blk_mem_gen_prim_wrapper : entity is "blk_mem_gen_prim_wrapper"; end input_fifo_blk_mem_gen_prim_wrapper; architecture STRUCTURE of input_fifo_blk_mem_gen_prim_wrapper is signal \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_n_16\ : STD_LOGIC; signal \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_n_17\ : STD_LOGIC; signal \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_n_18\ : STD_LOGIC; signal \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_n_19\ : STD_LOGIC; signal \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_n_24\ : STD_LOGIC; signal \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_n_25\ : STD_LOGIC; signal \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_n_26\ : STD_LOGIC; signal \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_n_27\ : STD_LOGIC; signal \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_n_34\ : STD_LOGIC; signal \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_n_35\ : STD_LOGIC; signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 15 downto 0 ); signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 ); attribute CLOCK_DOMAINS : string; attribute CLOCK_DOMAINS of \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram\ : label is "COMMON"; attribute box_type : string; attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram\ : label is "PRIMITIVE"; begin \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram\: unisim.vcomponents.RAMB18E1 generic map( DOA_REG => 0, DOB_REG => 0, INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_A => X"00000", INIT_B => X"00000", INIT_FILE => "NONE", IS_CLKARDCLK_INVERTED => '0', IS_CLKBWRCLK_INVERTED => '0', IS_ENARDEN_INVERTED => '0', IS_ENBWREN_INVERTED => '0', IS_RSTRAMARSTRAM_INVERTED => '0', IS_RSTRAMB_INVERTED => '0', IS_RSTREGARSTREG_INVERTED => '0', IS_RSTREGB_INVERTED => '0', RAM_MODE => "TDP", RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE", READ_WIDTH_A => 18, READ_WIDTH_B => 18, RSTREG_PRIORITY_A => "REGCE", RSTREG_PRIORITY_B => "REGCE", SIM_COLLISION_CHECK => "ALL", SIM_DEVICE => "7SERIES", SRVAL_A => X"00000", SRVAL_B => X"00000", WRITE_MODE_A => "WRITE_FIRST", WRITE_MODE_B => "WRITE_FIRST", WRITE_WIDTH_A => 18, WRITE_WIDTH_B => 18 ) port map ( ADDRARDADDR(13 downto 4) => Q(9 downto 0), ADDRARDADDR(3 downto 0) => B"0000", ADDRBWRADDR(13 downto 4) => \gc0.count_d1_reg[9]\(9 downto 0), ADDRBWRADDR(3 downto 0) => B"0000", CLKARDCLK => clk, CLKBWRCLK => clk, DIADI(15 downto 12) => B"0000", DIADI(11 downto 8) => din(7 downto 4), DIADI(7 downto 4) => B"0000", DIADI(3 downto 0) => din(3 downto 0), DIBDI(15 downto 0) => B"0000000000000000", DIPADIP(1 downto 0) => B"00", DIPBDIP(1 downto 0) => B"00", DOADO(15 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_DOADO_UNCONNECTED\(15 downto 0), DOBDO(15) => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_n_16\, DOBDO(14) => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_n_17\, DOBDO(13) => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_n_18\, DOBDO(12) => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_n_19\, DOBDO(11 downto 8) => D(7 downto 4), DOBDO(7) => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_n_24\, DOBDO(6) => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_n_25\, DOBDO(5) => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_n_26\, DOBDO(4) => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_n_27\, DOBDO(3 downto 0) => D(3 downto 0), DOPADOP(1 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_DOPADOP_UNCONNECTED\(1 downto 0), DOPBDOP(1) => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_n_34\, DOPBDOP(0) => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_n_35\, ENARDEN => WEA(0), ENBWREN => tmp_ram_rd_en, REGCEAREGCE => '0', REGCEB => '0', RSTRAMARSTRAM => '0', RSTRAMB => srst, RSTREGARSTREG => '0', RSTREGB => '0', WEA(1) => WEA(0), WEA(0) => WEA(0), WEBWE(3 downto 0) => B"0000" ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity input_fifo_compare is port ( ram_full_fb_i_reg : out STD_LOGIC; v1_reg : in STD_LOGIC_VECTOR ( 4 downto 0 ); wr_en : in STD_LOGIC; comp1 : in STD_LOGIC; \out\ : in STD_LOGIC; E : in STD_LOGIC_VECTOR ( 0 to 0 ) ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of input_fifo_compare : entity is "compare"; end input_fifo_compare; architecture STRUCTURE of input_fifo_compare is signal carrynet_0 : STD_LOGIC; signal carrynet_1 : STD_LOGIC; signal carrynet_2 : STD_LOGIC; signal carrynet_3 : STD_LOGIC; signal comp0 : STD_LOGIC; signal \NLW_gmux.gm[0].gm1.m1_CARRY4_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); signal \NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 ); signal \NLW_gmux.gm[4].gms.ms_CARRY4_DI_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 ); signal \NLW_gmux.gm[4].gms.ms_CARRY4_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); signal \NLW_gmux.gm[4].gms.ms_CARRY4_S_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 ); attribute XILINX_LEGACY_PRIM : string; attribute XILINX_LEGACY_PRIM of \gmux.gm[0].gm1.m1_CARRY4\ : label is "(MUXCY,XORCY)"; attribute box_type : string; attribute box_type of \gmux.gm[0].gm1.m1_CARRY4\ : label is "PRIMITIVE"; attribute XILINX_LEGACY_PRIM of \gmux.gm[4].gms.ms_CARRY4\ : label is "(MUXCY,XORCY)"; attribute box_type of \gmux.gm[4].gms.ms_CARRY4\ : label is "PRIMITIVE"; begin \gmux.gm[0].gm1.m1_CARRY4\: unisim.vcomponents.CARRY4 port map ( CI => '0', CO(3) => carrynet_3, CO(2) => carrynet_2, CO(1) => carrynet_1, CO(0) => carrynet_0, CYINIT => '1', DI(3 downto 0) => B"0000", O(3 downto 0) => \NLW_gmux.gm[0].gm1.m1_CARRY4_O_UNCONNECTED\(3 downto 0), S(3 downto 0) => v1_reg(3 downto 0) ); \gmux.gm[4].gms.ms_CARRY4\: unisim.vcomponents.CARRY4 port map ( CI => carrynet_3, CO(3 downto 1) => \NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED\(3 downto 1), CO(0) => comp0, CYINIT => '0', DI(3 downto 1) => \NLW_gmux.gm[4].gms.ms_CARRY4_DI_UNCONNECTED\(3 downto 1), DI(0) => '0', O(3 downto 0) => \NLW_gmux.gm[4].gms.ms_CARRY4_O_UNCONNECTED\(3 downto 0), S(3 downto 1) => \NLW_gmux.gm[4].gms.ms_CARRY4_S_UNCONNECTED\(3 downto 1), S(0) => v1_reg(4) ); ram_full_fb_i_i_1: unisim.vcomponents.LUT5 generic map( INIT => X"5500FFC0" ) port map ( I0 => comp0, I1 => wr_en, I2 => comp1, I3 => \out\, I4 => E(0), O => ram_full_fb_i_reg ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity input_fifo_compare_0 is port ( comp1 : out STD_LOGIC; v1_reg_0 : in STD_LOGIC_VECTOR ( 4 downto 0 ) ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of input_fifo_compare_0 : entity is "compare"; end input_fifo_compare_0; architecture STRUCTURE of input_fifo_compare_0 is signal carrynet_0 : STD_LOGIC; signal carrynet_1 : STD_LOGIC; signal carrynet_2 : STD_LOGIC; signal carrynet_3 : STD_LOGIC; signal \NLW_gmux.gm[0].gm1.m1_CARRY4_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); signal \NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 ); signal \NLW_gmux.gm[4].gms.ms_CARRY4_DI_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 ); signal \NLW_gmux.gm[4].gms.ms_CARRY4_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); signal \NLW_gmux.gm[4].gms.ms_CARRY4_S_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 ); attribute XILINX_LEGACY_PRIM : string; attribute XILINX_LEGACY_PRIM of \gmux.gm[0].gm1.m1_CARRY4\ : label is "(MUXCY,XORCY)"; attribute box_type : string; attribute box_type of \gmux.gm[0].gm1.m1_CARRY4\ : label is "PRIMITIVE"; attribute XILINX_LEGACY_PRIM of \gmux.gm[4].gms.ms_CARRY4\ : label is "(MUXCY,XORCY)"; attribute box_type of \gmux.gm[4].gms.ms_CARRY4\ : label is "PRIMITIVE"; begin \gmux.gm[0].gm1.m1_CARRY4\: unisim.vcomponents.CARRY4 port map ( CI => '0', CO(3) => carrynet_3, CO(2) => carrynet_2, CO(1) => carrynet_1, CO(0) => carrynet_0, CYINIT => '1', DI(3 downto 0) => B"0000", O(3 downto 0) => \NLW_gmux.gm[0].gm1.m1_CARRY4_O_UNCONNECTED\(3 downto 0), S(3 downto 0) => v1_reg_0(3 downto 0) ); \gmux.gm[4].gms.ms_CARRY4\: unisim.vcomponents.CARRY4 port map ( CI => carrynet_3, CO(3 downto 1) => \NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED\(3 downto 1), CO(0) => comp1, CYINIT => '0', DI(3 downto 1) => \NLW_gmux.gm[4].gms.ms_CARRY4_DI_UNCONNECTED\(3 downto 1), DI(0) => '0', O(3 downto 0) => \NLW_gmux.gm[4].gms.ms_CARRY4_O_UNCONNECTED\(3 downto 0), S(3 downto 1) => \NLW_gmux.gm[4].gms.ms_CARRY4_S_UNCONNECTED\(3 downto 1), S(0) => v1_reg_0(4) ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity input_fifo_compare_1 is port ( ram_empty_i_reg : out STD_LOGIC; \gcc0.gc0.count_d1_reg[0]\ : in STD_LOGIC; \gcc0.gc0.count_d1_reg[2]\ : in STD_LOGIC; \gcc0.gc0.count_d1_reg[4]\ : in STD_LOGIC; \gcc0.gc0.count_d1_reg[6]\ : in STD_LOGIC; \gcc0.gc0.count_d1_reg[8]\ : in STD_LOGIC; \out\ : in STD_LOGIC; E : in STD_LOGIC_VECTOR ( 0 to 0 ); comp1 : in STD_LOGIC; wr_en : in STD_LOGIC; ram_full_fb_i_reg : in STD_LOGIC ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of input_fifo_compare_1 : entity is "compare"; end input_fifo_compare_1; architecture STRUCTURE of input_fifo_compare_1 is signal carrynet_0 : STD_LOGIC; signal carrynet_1 : STD_LOGIC; signal carrynet_2 : STD_LOGIC; signal carrynet_3 : STD_LOGIC; signal comp0 : STD_LOGIC; signal \NLW_gmux.gm[0].gm1.m1_CARRY4_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); signal \NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 ); signal \NLW_gmux.gm[4].gms.ms_CARRY4_DI_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 ); signal \NLW_gmux.gm[4].gms.ms_CARRY4_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); signal \NLW_gmux.gm[4].gms.ms_CARRY4_S_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 ); attribute XILINX_LEGACY_PRIM : string; attribute XILINX_LEGACY_PRIM of \gmux.gm[0].gm1.m1_CARRY4\ : label is "(MUXCY,XORCY)"; attribute box_type : string; attribute box_type of \gmux.gm[0].gm1.m1_CARRY4\ : label is "PRIMITIVE"; attribute XILINX_LEGACY_PRIM of \gmux.gm[4].gms.ms_CARRY4\ : label is "(MUXCY,XORCY)"; attribute box_type of \gmux.gm[4].gms.ms_CARRY4\ : label is "PRIMITIVE"; begin \gmux.gm[0].gm1.m1_CARRY4\: unisim.vcomponents.CARRY4 port map ( CI => '0', CO(3) => carrynet_3, CO(2) => carrynet_2, CO(1) => carrynet_1, CO(0) => carrynet_0, CYINIT => '1', DI(3 downto 0) => B"0000", O(3 downto 0) => \NLW_gmux.gm[0].gm1.m1_CARRY4_O_UNCONNECTED\(3 downto 0), S(3) => \gcc0.gc0.count_d1_reg[6]\, S(2) => \gcc0.gc0.count_d1_reg[4]\, S(1) => \gcc0.gc0.count_d1_reg[2]\, S(0) => \gcc0.gc0.count_d1_reg[0]\ ); \gmux.gm[4].gms.ms_CARRY4\: unisim.vcomponents.CARRY4 port map ( CI => carrynet_3, CO(3 downto 1) => \NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED\(3 downto 1), CO(0) => comp0, CYINIT => '0', DI(3 downto 1) => \NLW_gmux.gm[4].gms.ms_CARRY4_DI_UNCONNECTED\(3 downto 1), DI(0) => '0', O(3 downto 0) => \NLW_gmux.gm[4].gms.ms_CARRY4_O_UNCONNECTED\(3 downto 0), S(3 downto 1) => \NLW_gmux.gm[4].gms.ms_CARRY4_S_UNCONNECTED\(3 downto 1), S(0) => \gcc0.gc0.count_d1_reg[8]\ ); ram_empty_fb_i_i_1: unisim.vcomponents.LUT6 generic map( INIT => X"FCCCFCCC4444FCCC" ) port map ( I0 => comp0, I1 => \out\, I2 => E(0), I3 => comp1, I4 => wr_en, I5 => ram_full_fb_i_reg, O => ram_empty_i_reg ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity input_fifo_compare_2 is port ( comp1 : out STD_LOGIC; v1_reg : in STD_LOGIC_VECTOR ( 4 downto 0 ) ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of input_fifo_compare_2 : entity is "compare"; end input_fifo_compare_2; architecture STRUCTURE of input_fifo_compare_2 is signal carrynet_0 : STD_LOGIC; signal carrynet_1 : STD_LOGIC; signal carrynet_2 : STD_LOGIC; signal carrynet_3 : STD_LOGIC; signal \NLW_gmux.gm[0].gm1.m1_CARRY4_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); signal \NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 ); signal \NLW_gmux.gm[4].gms.ms_CARRY4_DI_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 ); signal \NLW_gmux.gm[4].gms.ms_CARRY4_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); signal \NLW_gmux.gm[4].gms.ms_CARRY4_S_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 ); attribute XILINX_LEGACY_PRIM : string; attribute XILINX_LEGACY_PRIM of \gmux.gm[0].gm1.m1_CARRY4\ : label is "(MUXCY,XORCY)"; attribute box_type : string; attribute box_type of \gmux.gm[0].gm1.m1_CARRY4\ : label is "PRIMITIVE"; attribute XILINX_LEGACY_PRIM of \gmux.gm[4].gms.ms_CARRY4\ : label is "(MUXCY,XORCY)"; attribute box_type of \gmux.gm[4].gms.ms_CARRY4\ : label is "PRIMITIVE"; begin \gmux.gm[0].gm1.m1_CARRY4\: unisim.vcomponents.CARRY4 port map ( CI => '0', CO(3) => carrynet_3, CO(2) => carrynet_2, CO(1) => carrynet_1, CO(0) => carrynet_0, CYINIT => '1', DI(3 downto 0) => B"0000", O(3 downto 0) => \NLW_gmux.gm[0].gm1.m1_CARRY4_O_UNCONNECTED\(3 downto 0), S(3 downto 0) => v1_reg(3 downto 0) ); \gmux.gm[4].gms.ms_CARRY4\: unisim.vcomponents.CARRY4 port map ( CI => carrynet_3, CO(3 downto 1) => \NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED\(3 downto 1), CO(0) => comp1, CYINIT => '0', DI(3 downto 1) => \NLW_gmux.gm[4].gms.ms_CARRY4_DI_UNCONNECTED\(3 downto 1), DI(0) => '0', O(3 downto 0) => \NLW_gmux.gm[4].gms.ms_CARRY4_O_UNCONNECTED\(3 downto 0), S(3 downto 1) => \NLW_gmux.gm[4].gms.ms_CARRY4_S_UNCONNECTED\(3 downto 1), S(0) => v1_reg(4) ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity input_fifo_rd_bin_cntr is port ( Q : out STD_LOGIC_VECTOR ( 9 downto 0 ); \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram\ : out STD_LOGIC_VECTOR ( 9 downto 0 ); srst : in STD_LOGIC; E : in STD_LOGIC_VECTOR ( 0 to 0 ); clk : in STD_LOGIC ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of input_fifo_rd_bin_cntr : entity is "rd_bin_cntr"; end input_fifo_rd_bin_cntr; architecture STRUCTURE of input_fifo_rd_bin_cntr is signal \^q\ : STD_LOGIC_VECTOR ( 9 downto 0 ); signal \gc0.count[9]_i_2_n_0\ : STD_LOGIC; signal plusOp : STD_LOGIC_VECTOR ( 9 downto 0 ); attribute SOFT_HLUTNM : string; attribute SOFT_HLUTNM of \gc0.count[1]_i_1\ : label is "soft_lutpair3"; attribute SOFT_HLUTNM of \gc0.count[2]_i_1\ : label is "soft_lutpair3"; attribute SOFT_HLUTNM of \gc0.count[3]_i_1\ : label is "soft_lutpair1"; attribute SOFT_HLUTNM of \gc0.count[4]_i_1\ : label is "soft_lutpair1"; attribute SOFT_HLUTNM of \gc0.count[6]_i_1\ : label is "soft_lutpair2"; attribute SOFT_HLUTNM of \gc0.count[7]_i_1\ : label is "soft_lutpair2"; attribute SOFT_HLUTNM of \gc0.count[8]_i_1\ : label is "soft_lutpair0"; attribute SOFT_HLUTNM of \gc0.count[9]_i_1\ : label is "soft_lutpair0"; begin Q(9 downto 0) <= \^q\(9 downto 0); \gc0.count[0]_i_1\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \^q\(0), O => plusOp(0) ); \gc0.count[1]_i_1\: unisim.vcomponents.LUT2 generic map( INIT => X"6" ) port map ( I0 => \^q\(0), I1 => \^q\(1), O => plusOp(1) ); \gc0.count[2]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"78" ) port map ( I0 => \^q\(0), I1 => \^q\(1), I2 => \^q\(2), O => plusOp(2) ); \gc0.count[3]_i_1\: unisim.vcomponents.LUT4 generic map( INIT => X"7F80" ) port map ( I0 => \^q\(1), I1 => \^q\(0), I2 => \^q\(2), I3 => \^q\(3), O => plusOp(3) ); \gc0.count[4]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"7FFF8000" ) port map ( I0 => \^q\(2), I1 => \^q\(0), I2 => \^q\(1), I3 => \^q\(3), I4 => \^q\(4), O => plusOp(4) ); \gc0.count[5]_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"7FFFFFFF80000000" ) port map ( I0 => \^q\(3), I1 => \^q\(1), I2 => \^q\(0), I3 => \^q\(2), I4 => \^q\(4), I5 => \^q\(5), O => plusOp(5) ); \gc0.count[6]_i_1\: unisim.vcomponents.LUT2 generic map( INIT => X"6" ) port map ( I0 => \gc0.count[9]_i_2_n_0\, I1 => \^q\(6), O => plusOp(6) ); \gc0.count[7]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"78" ) port map ( I0 => \gc0.count[9]_i_2_n_0\, I1 => \^q\(6), I2 => \^q\(7), O => plusOp(7) ); \gc0.count[8]_i_1\: unisim.vcomponents.LUT4 generic map( INIT => X"7F80" ) port map ( I0 => \^q\(6), I1 => \gc0.count[9]_i_2_n_0\, I2 => \^q\(7), I3 => \^q\(8), O => plusOp(8) ); \gc0.count[9]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"7FFF8000" ) port map ( I0 => \^q\(7), I1 => \gc0.count[9]_i_2_n_0\, I2 => \^q\(6), I3 => \^q\(8), I4 => \^q\(9), O => plusOp(9) ); \gc0.count[9]_i_2\: unisim.vcomponents.LUT6 generic map( INIT => X"8000000000000000" ) port map ( I0 => \^q\(5), I1 => \^q\(3), I2 => \^q\(1), I3 => \^q\(0), I4 => \^q\(2), I5 => \^q\(4), O => \gc0.count[9]_i_2_n_0\ ); \gc0.count_d1_reg[0]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => clk, CE => E(0), D => \^q\(0), Q => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram\(0), R => srst ); \gc0.count_d1_reg[1]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => clk, CE => E(0), D => \^q\(1), Q => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram\(1), R => srst ); \gc0.count_d1_reg[2]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => clk, CE => E(0), D => \^q\(2), Q => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram\(2), R => srst ); \gc0.count_d1_reg[3]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => clk, CE => E(0), D => \^q\(3), Q => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram\(3), R => srst ); \gc0.count_d1_reg[4]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => clk, CE => E(0), D => \^q\(4), Q => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram\(4), R => srst ); \gc0.count_d1_reg[5]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => clk, CE => E(0), D => \^q\(5), Q => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram\(5), R => srst ); \gc0.count_d1_reg[6]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => clk, CE => E(0), D => \^q\(6), Q => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram\(6), R => srst ); \gc0.count_d1_reg[7]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => clk, CE => E(0), D => \^q\(7), Q => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram\(7), R => srst ); \gc0.count_d1_reg[8]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => clk, CE => E(0), D => \^q\(8), Q => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram\(8), R => srst ); \gc0.count_d1_reg[9]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => clk, CE => E(0), D => \^q\(9), Q => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram\(9), R => srst ); \gc0.count_reg[0]\: unisim.vcomponents.FDSE generic map( INIT => '1' ) port map ( C => clk, CE => E(0), D => plusOp(0), Q => \^q\(0), S => srst ); \gc0.count_reg[1]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => clk, CE => E(0), D => plusOp(1), Q => \^q\(1), R => srst ); \gc0.count_reg[2]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => clk, CE => E(0), D => plusOp(2), Q => \^q\(2), R => srst ); \gc0.count_reg[3]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => clk, CE => E(0), D => plusOp(3), Q => \^q\(3), R => srst ); \gc0.count_reg[4]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => clk, CE => E(0), D => plusOp(4), Q => \^q\(4), R => srst ); \gc0.count_reg[5]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => clk, CE => E(0), D => plusOp(5), Q => \^q\(5), R => srst ); \gc0.count_reg[6]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => clk, CE => E(0), D => plusOp(6), Q => \^q\(6), R => srst ); \gc0.count_reg[7]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => clk, CE => E(0), D => plusOp(7), Q => \^q\(7), R => srst ); \gc0.count_reg[8]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => clk, CE => E(0), D => plusOp(8), Q => \^q\(8), R => srst ); \gc0.count_reg[9]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => clk, CE => E(0), D => plusOp(9), Q => \^q\(9), R => srst ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity input_fifo_rd_fwft is port ( empty : out STD_LOGIC; tmp_ram_rd_en : out STD_LOGIC; E : out STD_LOGIC_VECTOR ( 0 to 0 ); \goreg_bm.dout_i_reg[7]\ : out STD_LOGIC_VECTOR ( 0 to 0 ); srst : in STD_LOGIC; clk : in STD_LOGIC; rd_en : in STD_LOGIC; \out\ : in STD_LOGIC ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of input_fifo_rd_fwft : entity is "rd_fwft"; end input_fifo_rd_fwft; architecture STRUCTURE of input_fifo_rd_fwft is signal aempty_fwft_fb_i : STD_LOGIC; attribute DONT_TOUCH : boolean; attribute DONT_TOUCH of aempty_fwft_fb_i : signal is std.standard.true; signal aempty_fwft_i : STD_LOGIC; attribute DONT_TOUCH of aempty_fwft_i : signal is std.standard.true; signal \aempty_fwft_i0__6\ : STD_LOGIC; signal curr_fwft_state : STD_LOGIC_VECTOR ( 1 downto 0 ); attribute DONT_TOUCH of curr_fwft_state : signal is std.standard.true; signal empty_fwft_fb_i : STD_LOGIC; attribute DONT_TOUCH of empty_fwft_fb_i : signal is std.standard.true; signal empty_fwft_fb_o_i : STD_LOGIC; attribute DONT_TOUCH of empty_fwft_fb_o_i : signal is std.standard.true; signal empty_fwft_fb_o_i_reg0 : STD_LOGIC; signal empty_fwft_i : STD_LOGIC; attribute DONT_TOUCH of empty_fwft_i : signal is std.standard.true; signal \empty_fwft_i0__1\ : STD_LOGIC; signal next_fwft_state : STD_LOGIC_VECTOR ( 1 downto 0 ); signal user_valid : STD_LOGIC; attribute DONT_TOUCH of user_valid : signal is std.standard.true; attribute DONT_TOUCH of aempty_fwft_fb_i_reg : label is std.standard.true; attribute KEEP : string; attribute KEEP of aempty_fwft_fb_i_reg : label is "yes"; attribute equivalent_register_removal : string; attribute equivalent_register_removal of aempty_fwft_fb_i_reg : label is "no"; attribute DONT_TOUCH of aempty_fwft_i_reg : label is std.standard.true; attribute KEEP of aempty_fwft_i_reg : label is "yes"; attribute equivalent_register_removal of aempty_fwft_i_reg : label is "no"; attribute DONT_TOUCH of empty_fwft_fb_i_reg : label is std.standard.true; attribute KEEP of empty_fwft_fb_i_reg : label is "yes"; attribute equivalent_register_removal of empty_fwft_fb_i_reg : label is "no"; attribute DONT_TOUCH of empty_fwft_fb_o_i_reg : label is std.standard.true; attribute KEEP of empty_fwft_fb_o_i_reg : label is "yes"; attribute equivalent_register_removal of empty_fwft_fb_o_i_reg : label is "no"; attribute DONT_TOUCH of empty_fwft_i_reg : label is std.standard.true; attribute KEEP of empty_fwft_i_reg : label is "yes"; attribute equivalent_register_removal of empty_fwft_i_reg : label is "no"; attribute DONT_TOUCH of \gpregsm1.curr_fwft_state_reg[0]\ : label is std.standard.true; attribute KEEP of \gpregsm1.curr_fwft_state_reg[0]\ : label is "yes"; attribute equivalent_register_removal of \gpregsm1.curr_fwft_state_reg[0]\ : label is "no"; attribute DONT_TOUCH of \gpregsm1.curr_fwft_state_reg[1]\ : label is std.standard.true; attribute KEEP of \gpregsm1.curr_fwft_state_reg[1]\ : label is "yes"; attribute equivalent_register_removal of \gpregsm1.curr_fwft_state_reg[1]\ : label is "no"; attribute DONT_TOUCH of \gpregsm1.user_valid_reg\ : label is std.standard.true; attribute KEEP of \gpregsm1.user_valid_reg\ : label is "yes"; attribute equivalent_register_removal of \gpregsm1.user_valid_reg\ : label is "no"; begin empty <= empty_fwft_i; \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_i_2\: unisim.vcomponents.LUT5 generic map( INIT => X"BABBBBBB" ) port map ( I0 => srst, I1 => \out\, I2 => rd_en, I3 => curr_fwft_state(0), I4 => curr_fwft_state(1), O => tmp_ram_rd_en ); aempty_fwft_fb_i_i_1: unisim.vcomponents.LUT5 generic map( INIT => X"EEFD8000" ) port map ( I0 => curr_fwft_state(0), I1 => \out\, I2 => rd_en, I3 => curr_fwft_state(1), I4 => aempty_fwft_fb_i, O => \aempty_fwft_i0__6\ ); aempty_fwft_fb_i_reg: unisim.vcomponents.FDSE generic map( INIT => '1' ) port map ( C => clk, CE => '1', D => \aempty_fwft_i0__6\, Q => aempty_fwft_fb_i, S => srst ); aempty_fwft_i_reg: unisim.vcomponents.FDSE generic map( INIT => '1' ) port map ( C => clk, CE => '1', D => \aempty_fwft_i0__6\, Q => aempty_fwft_i, S => srst ); empty_fwft_fb_i_i_1: unisim.vcomponents.LUT4 generic map( INIT => X"F320" ) port map ( I0 => rd_en, I1 => curr_fwft_state(1), I2 => curr_fwft_state(0), I3 => empty_fwft_fb_i, O => \empty_fwft_i0__1\ ); empty_fwft_fb_i_reg: unisim.vcomponents.FDSE generic map( INIT => '1' ) port map ( C => clk, CE => '1', D => \empty_fwft_i0__1\, Q => empty_fwft_fb_i, S => srst ); empty_fwft_fb_o_i_i_1: unisim.vcomponents.LUT4 generic map( INIT => X"F320" ) port map ( I0 => rd_en, I1 => curr_fwft_state(1), I2 => curr_fwft_state(0), I3 => empty_fwft_fb_o_i, O => empty_fwft_fb_o_i_reg0 ); empty_fwft_fb_o_i_reg: unisim.vcomponents.FDSE generic map( INIT => '1' ) port map ( C => clk, CE => '1', D => empty_fwft_fb_o_i_reg0, Q => empty_fwft_fb_o_i, S => srst ); empty_fwft_i_reg: unisim.vcomponents.FDSE generic map( INIT => '1' ) port map ( C => clk, CE => '1', D => \empty_fwft_i0__1\, Q => empty_fwft_i, S => srst ); \gc0.count_d1[9]_i_1\: unisim.vcomponents.LUT4 generic map( INIT => X"00BF" ) port map ( I0 => rd_en, I1 => curr_fwft_state(0), I2 => curr_fwft_state(1), I3 => \out\, O => E(0) ); \goreg_bm.dout_i[7]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"A2" ) port map ( I0 => curr_fwft_state(1), I1 => curr_fwft_state(0), I2 => rd_en, O => \goreg_bm.dout_i_reg[7]\(0) ); \gpregsm1.curr_fwft_state[0]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"BA" ) port map ( I0 => curr_fwft_state(1), I1 => rd_en, I2 => curr_fwft_state(0), O => next_fwft_state(0) ); \gpregsm1.curr_fwft_state[1]_i_1\: unisim.vcomponents.LUT4 generic map( INIT => X"20FF" ) port map ( I0 => curr_fwft_state(1), I1 => rd_en, I2 => curr_fwft_state(0), I3 => \out\, O => next_fwft_state(1) ); \gpregsm1.curr_fwft_state_reg[0]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => clk, CE => '1', D => next_fwft_state(0), Q => curr_fwft_state(0), R => srst ); \gpregsm1.curr_fwft_state_reg[1]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => clk, CE => '1', D => next_fwft_state(1), Q => curr_fwft_state(1), R => srst ); \gpregsm1.user_valid_reg\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => clk, CE => '1', D => next_fwft_state(0), Q => user_valid, R => srst ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity input_fifo_wr_bin_cntr is port ( v1_reg_0 : out STD_LOGIC_VECTOR ( 4 downto 0 ); Q : out STD_LOGIC_VECTOR ( 9 downto 0 ); v1_reg : out STD_LOGIC_VECTOR ( 4 downto 0 ); v1_reg_1 : out STD_LOGIC_VECTOR ( 4 downto 0 ); ram_empty_i_reg : out STD_LOGIC; ram_empty_i_reg_0 : out STD_LOGIC; ram_empty_i_reg_1 : out STD_LOGIC; ram_empty_i_reg_2 : out STD_LOGIC; ram_empty_i_reg_3 : out STD_LOGIC; \gc0.count_d1_reg[9]\ : in STD_LOGIC_VECTOR ( 9 downto 0 ); \gc0.count_reg[9]\ : in STD_LOGIC_VECTOR ( 9 downto 0 ); srst : in STD_LOGIC; E : in STD_LOGIC_VECTOR ( 0 to 0 ); clk : in STD_LOGIC ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of input_fifo_wr_bin_cntr : entity is "wr_bin_cntr"; end input_fifo_wr_bin_cntr; architecture STRUCTURE of input_fifo_wr_bin_cntr is signal \^q\ : STD_LOGIC_VECTOR ( 9 downto 0 ); signal \gcc0.gc0.count[9]_i_2_n_0\ : STD_LOGIC; signal p_12_out : STD_LOGIC_VECTOR ( 9 downto 0 ); signal \plusOp__0\ : STD_LOGIC_VECTOR ( 9 downto 0 ); attribute SOFT_HLUTNM : string; attribute SOFT_HLUTNM of \gcc0.gc0.count[1]_i_1\ : label is "soft_lutpair7"; attribute SOFT_HLUTNM of \gcc0.gc0.count[2]_i_1\ : label is "soft_lutpair7"; attribute SOFT_HLUTNM of \gcc0.gc0.count[3]_i_1\ : label is "soft_lutpair5"; attribute SOFT_HLUTNM of \gcc0.gc0.count[4]_i_1\ : label is "soft_lutpair5"; attribute SOFT_HLUTNM of \gcc0.gc0.count[6]_i_1\ : label is "soft_lutpair6"; attribute SOFT_HLUTNM of \gcc0.gc0.count[7]_i_1\ : label is "soft_lutpair6"; attribute SOFT_HLUTNM of \gcc0.gc0.count[8]_i_1\ : label is "soft_lutpair4"; attribute SOFT_HLUTNM of \gcc0.gc0.count[9]_i_1\ : label is "soft_lutpair4"; begin Q(9 downto 0) <= \^q\(9 downto 0); \gcc0.gc0.count[0]_i_1\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => p_12_out(0), O => \plusOp__0\(0) ); \gcc0.gc0.count[1]_i_1\: unisim.vcomponents.LUT2 generic map( INIT => X"6" ) port map ( I0 => p_12_out(0), I1 => p_12_out(1), O => \plusOp__0\(1) ); \gcc0.gc0.count[2]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"78" ) port map ( I0 => p_12_out(0), I1 => p_12_out(1), I2 => p_12_out(2), O => \plusOp__0\(2) ); \gcc0.gc0.count[3]_i_1\: unisim.vcomponents.LUT4 generic map( INIT => X"7F80" ) port map ( I0 => p_12_out(1), I1 => p_12_out(0), I2 => p_12_out(2), I3 => p_12_out(3), O => \plusOp__0\(3) ); \gcc0.gc0.count[4]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"7FFF8000" ) port map ( I0 => p_12_out(2), I1 => p_12_out(0), I2 => p_12_out(1), I3 => p_12_out(3), I4 => p_12_out(4), O => \plusOp__0\(4) ); \gcc0.gc0.count[5]_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"7FFFFFFF80000000" ) port map ( I0 => p_12_out(3), I1 => p_12_out(1), I2 => p_12_out(0), I3 => p_12_out(2), I4 => p_12_out(4), I5 => p_12_out(5), O => \plusOp__0\(5) ); \gcc0.gc0.count[6]_i_1\: unisim.vcomponents.LUT2 generic map( INIT => X"6" ) port map ( I0 => \gcc0.gc0.count[9]_i_2_n_0\, I1 => p_12_out(6), O => \plusOp__0\(6) ); \gcc0.gc0.count[7]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"78" ) port map ( I0 => \gcc0.gc0.count[9]_i_2_n_0\, I1 => p_12_out(6), I2 => p_12_out(7), O => \plusOp__0\(7) ); \gcc0.gc0.count[8]_i_1\: unisim.vcomponents.LUT4 generic map( INIT => X"7F80" ) port map ( I0 => p_12_out(6), I1 => \gcc0.gc0.count[9]_i_2_n_0\, I2 => p_12_out(7), I3 => p_12_out(8), O => \plusOp__0\(8) ); \gcc0.gc0.count[9]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"7FFF8000" ) port map ( I0 => p_12_out(7), I1 => \gcc0.gc0.count[9]_i_2_n_0\, I2 => p_12_out(6), I3 => p_12_out(8), I4 => p_12_out(9), O => \plusOp__0\(9) ); \gcc0.gc0.count[9]_i_2\: unisim.vcomponents.LUT6 generic map( INIT => X"8000000000000000" ) port map ( I0 => p_12_out(5), I1 => p_12_out(3), I2 => p_12_out(1), I3 => p_12_out(0), I4 => p_12_out(2), I5 => p_12_out(4), O => \gcc0.gc0.count[9]_i_2_n_0\ ); \gcc0.gc0.count_d1_reg[0]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => clk, CE => E(0), D => p_12_out(0), Q => \^q\(0), R => srst ); \gcc0.gc0.count_d1_reg[1]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => clk, CE => E(0), D => p_12_out(1), Q => \^q\(1), R => srst ); \gcc0.gc0.count_d1_reg[2]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => clk, CE => E(0), D => p_12_out(2), Q => \^q\(2), R => srst ); \gcc0.gc0.count_d1_reg[3]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => clk, CE => E(0), D => p_12_out(3), Q => \^q\(3), R => srst ); \gcc0.gc0.count_d1_reg[4]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => clk, CE => E(0), D => p_12_out(4), Q => \^q\(4), R => srst ); \gcc0.gc0.count_d1_reg[5]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => clk, CE => E(0), D => p_12_out(5), Q => \^q\(5), R => srst ); \gcc0.gc0.count_d1_reg[6]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => clk, CE => E(0), D => p_12_out(6), Q => \^q\(6), R => srst ); \gcc0.gc0.count_d1_reg[7]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => clk, CE => E(0), D => p_12_out(7), Q => \^q\(7), R => srst ); \gcc0.gc0.count_d1_reg[8]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => clk, CE => E(0), D => p_12_out(8), Q => \^q\(8), R => srst ); \gcc0.gc0.count_d1_reg[9]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => clk, CE => E(0), D => p_12_out(9), Q => \^q\(9), R => srst ); \gcc0.gc0.count_reg[0]\: unisim.vcomponents.FDSE generic map( INIT => '1' ) port map ( C => clk, CE => E(0), D => \plusOp__0\(0), Q => p_12_out(0), S => srst ); \gcc0.gc0.count_reg[1]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => clk, CE => E(0), D => \plusOp__0\(1), Q => p_12_out(1), R => srst ); \gcc0.gc0.count_reg[2]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => clk, CE => E(0), D => \plusOp__0\(2), Q => p_12_out(2), R => srst ); \gcc0.gc0.count_reg[3]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => clk, CE => E(0), D => \plusOp__0\(3), Q => p_12_out(3), R => srst ); \gcc0.gc0.count_reg[4]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => clk, CE => E(0), D => \plusOp__0\(4), Q => p_12_out(4), R => srst ); \gcc0.gc0.count_reg[5]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => clk, CE => E(0), D => \plusOp__0\(5), Q => p_12_out(5), R => srst ); \gcc0.gc0.count_reg[6]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => clk, CE => E(0), D => \plusOp__0\(6), Q => p_12_out(6), R => srst ); \gcc0.gc0.count_reg[7]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => clk, CE => E(0), D => \plusOp__0\(7), Q => p_12_out(7), R => srst ); \gcc0.gc0.count_reg[8]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => clk, CE => E(0), D => \plusOp__0\(8), Q => p_12_out(8), R => srst ); \gcc0.gc0.count_reg[9]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => clk, CE => E(0), D => \plusOp__0\(9), Q => p_12_out(9), R => srst ); \gmux.gm[0].gm1.m1_i_1\: unisim.vcomponents.LUT4 generic map( INIT => X"9009" ) port map ( I0 => \^q\(0), I1 => \gc0.count_d1_reg[9]\(0), I2 => \^q\(1), I3 => \gc0.count_d1_reg[9]\(1), O => v1_reg_0(0) ); \gmux.gm[0].gm1.m1_i_1__0\: unisim.vcomponents.LUT4 generic map( INIT => X"9009" ) port map ( I0 => \^q\(0), I1 => \gc0.count_reg[9]\(0), I2 => \^q\(1), I3 => \gc0.count_reg[9]\(1), O => v1_reg(0) ); \gmux.gm[0].gm1.m1_i_1__1\: unisim.vcomponents.LUT4 generic map( INIT => X"9009" ) port map ( I0 => p_12_out(0), I1 => \gc0.count_d1_reg[9]\(0), I2 => p_12_out(1), I3 => \gc0.count_d1_reg[9]\(1), O => v1_reg_1(0) ); \gmux.gm[0].gm1.m1_i_1__2\: unisim.vcomponents.LUT4 generic map( INIT => X"9009" ) port map ( I0 => \^q\(0), I1 => \gc0.count_d1_reg[9]\(0), I2 => \^q\(1), I3 => \gc0.count_d1_reg[9]\(1), O => ram_empty_i_reg ); \gmux.gm[1].gms.ms_i_1\: unisim.vcomponents.LUT4 generic map( INIT => X"9009" ) port map ( I0 => \^q\(2), I1 => \gc0.count_d1_reg[9]\(2), I2 => \^q\(3), I3 => \gc0.count_d1_reg[9]\(3), O => v1_reg_0(1) ); \gmux.gm[1].gms.ms_i_1__0\: unisim.vcomponents.LUT4 generic map( INIT => X"9009" ) port map ( I0 => \^q\(2), I1 => \gc0.count_reg[9]\(2), I2 => \^q\(3), I3 => \gc0.count_reg[9]\(3), O => v1_reg(1) ); \gmux.gm[1].gms.ms_i_1__1\: unisim.vcomponents.LUT4 generic map( INIT => X"9009" ) port map ( I0 => p_12_out(2), I1 => \gc0.count_d1_reg[9]\(2), I2 => p_12_out(3), I3 => \gc0.count_d1_reg[9]\(3), O => v1_reg_1(1) ); \gmux.gm[1].gms.ms_i_1__2\: unisim.vcomponents.LUT4 generic map( INIT => X"9009" ) port map ( I0 => \^q\(2), I1 => \gc0.count_d1_reg[9]\(2), I2 => \^q\(3), I3 => \gc0.count_d1_reg[9]\(3), O => ram_empty_i_reg_0 ); \gmux.gm[2].gms.ms_i_1\: unisim.vcomponents.LUT4 generic map( INIT => X"9009" ) port map ( I0 => \^q\(4), I1 => \gc0.count_d1_reg[9]\(4), I2 => \^q\(5), I3 => \gc0.count_d1_reg[9]\(5), O => v1_reg_0(2) ); \gmux.gm[2].gms.ms_i_1__0\: unisim.vcomponents.LUT4 generic map( INIT => X"9009" ) port map ( I0 => \^q\(4), I1 => \gc0.count_reg[9]\(4), I2 => \^q\(5), I3 => \gc0.count_reg[9]\(5), O => v1_reg(2) ); \gmux.gm[2].gms.ms_i_1__1\: unisim.vcomponents.LUT4 generic map( INIT => X"9009" ) port map ( I0 => p_12_out(4), I1 => \gc0.count_d1_reg[9]\(4), I2 => p_12_out(5), I3 => \gc0.count_d1_reg[9]\(5), O => v1_reg_1(2) ); \gmux.gm[2].gms.ms_i_1__2\: unisim.vcomponents.LUT4 generic map( INIT => X"9009" ) port map ( I0 => \^q\(4), I1 => \gc0.count_d1_reg[9]\(4), I2 => \^q\(5), I3 => \gc0.count_d1_reg[9]\(5), O => ram_empty_i_reg_1 ); \gmux.gm[3].gms.ms_i_1\: unisim.vcomponents.LUT4 generic map( INIT => X"9009" ) port map ( I0 => \^q\(6), I1 => \gc0.count_d1_reg[9]\(6), I2 => \^q\(7), I3 => \gc0.count_d1_reg[9]\(7), O => v1_reg_0(3) ); \gmux.gm[3].gms.ms_i_1__0\: unisim.vcomponents.LUT4 generic map( INIT => X"9009" ) port map ( I0 => \^q\(6), I1 => \gc0.count_reg[9]\(6), I2 => \^q\(7), I3 => \gc0.count_reg[9]\(7), O => v1_reg(3) ); \gmux.gm[3].gms.ms_i_1__1\: unisim.vcomponents.LUT4 generic map( INIT => X"9009" ) port map ( I0 => p_12_out(6), I1 => \gc0.count_d1_reg[9]\(6), I2 => p_12_out(7), I3 => \gc0.count_d1_reg[9]\(7), O => v1_reg_1(3) ); \gmux.gm[3].gms.ms_i_1__2\: unisim.vcomponents.LUT4 generic map( INIT => X"9009" ) port map ( I0 => \^q\(6), I1 => \gc0.count_d1_reg[9]\(6), I2 => \^q\(7), I3 => \gc0.count_d1_reg[9]\(7), O => ram_empty_i_reg_2 ); \gmux.gm[4].gms.ms_i_1\: unisim.vcomponents.LUT4 generic map( INIT => X"9009" ) port map ( I0 => \^q\(8), I1 => \gc0.count_d1_reg[9]\(8), I2 => \^q\(9), I3 => \gc0.count_d1_reg[9]\(9), O => v1_reg_0(4) ); \gmux.gm[4].gms.ms_i_1__0\: unisim.vcomponents.LUT4 generic map( INIT => X"9009" ) port map ( I0 => \^q\(8), I1 => \gc0.count_reg[9]\(8), I2 => \^q\(9), I3 => \gc0.count_reg[9]\(9), O => v1_reg(4) ); \gmux.gm[4].gms.ms_i_1__1\: unisim.vcomponents.LUT4 generic map( INIT => X"9009" ) port map ( I0 => p_12_out(8), I1 => \gc0.count_d1_reg[9]\(8), I2 => p_12_out(9), I3 => \gc0.count_d1_reg[9]\(9), O => v1_reg_1(4) ); \gmux.gm[4].gms.ms_i_1__2\: unisim.vcomponents.LUT4 generic map( INIT => X"9009" ) port map ( I0 => \^q\(8), I1 => \gc0.count_d1_reg[9]\(8), I2 => \^q\(9), I3 => \gc0.count_d1_reg[9]\(9), O => ram_empty_i_reg_3 ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity input_fifo_blk_mem_gen_prim_width is port ( D : out STD_LOGIC_VECTOR ( 7 downto 0 ); clk : in STD_LOGIC; WEA : in STD_LOGIC_VECTOR ( 0 to 0 ); tmp_ram_rd_en : in STD_LOGIC; srst : in STD_LOGIC; Q : in STD_LOGIC_VECTOR ( 9 downto 0 ); \gc0.count_d1_reg[9]\ : in STD_LOGIC_VECTOR ( 9 downto 0 ); din : in STD_LOGIC_VECTOR ( 7 downto 0 ) ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of input_fifo_blk_mem_gen_prim_width : entity is "blk_mem_gen_prim_width"; end input_fifo_blk_mem_gen_prim_width; architecture STRUCTURE of input_fifo_blk_mem_gen_prim_width is begin \prim_noinit.ram\: entity work.input_fifo_blk_mem_gen_prim_wrapper port map ( D(7 downto 0) => D(7 downto 0), Q(9 downto 0) => Q(9 downto 0), WEA(0) => WEA(0), clk => clk, din(7 downto 0) => din(7 downto 0), \gc0.count_d1_reg[9]\(9 downto 0) => \gc0.count_d1_reg[9]\(9 downto 0), srst => srst, tmp_ram_rd_en => tmp_ram_rd_en ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity input_fifo_rd_status_flags_ss is port ( \out\ : out STD_LOGIC; \gcc0.gc0.count_d1_reg[0]\ : in STD_LOGIC; \gcc0.gc0.count_d1_reg[2]\ : in STD_LOGIC; \gcc0.gc0.count_d1_reg[4]\ : in STD_LOGIC; \gcc0.gc0.count_d1_reg[6]\ : in STD_LOGIC; \gcc0.gc0.count_d1_reg[8]\ : in STD_LOGIC; v1_reg : in STD_LOGIC_VECTOR ( 4 downto 0 ); srst : in STD_LOGIC; clk : in STD_LOGIC; E : in STD_LOGIC_VECTOR ( 0 to 0 ); wr_en : in STD_LOGIC; ram_full_fb_i_reg : in STD_LOGIC ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of input_fifo_rd_status_flags_ss : entity is "rd_status_flags_ss"; end input_fifo_rd_status_flags_ss; architecture STRUCTURE of input_fifo_rd_status_flags_ss is signal c1_n_0 : STD_LOGIC; signal comp1 : STD_LOGIC; signal ram_empty_fb_i : STD_LOGIC; attribute DONT_TOUCH : boolean; attribute DONT_TOUCH of ram_empty_fb_i : signal is std.standard.true; signal ram_empty_i : STD_LOGIC; attribute DONT_TOUCH of ram_empty_i : signal is std.standard.true; attribute DONT_TOUCH of ram_empty_fb_i_reg : label is std.standard.true; attribute KEEP : string; attribute KEEP of ram_empty_fb_i_reg : label is "yes"; attribute equivalent_register_removal : string; attribute equivalent_register_removal of ram_empty_fb_i_reg : label is "no"; attribute DONT_TOUCH of ram_empty_i_reg : label is std.standard.true; attribute KEEP of ram_empty_i_reg : label is "yes"; attribute equivalent_register_removal of ram_empty_i_reg : label is "no"; begin \out\ <= ram_empty_fb_i; c1: entity work.input_fifo_compare_1 port map ( E(0) => E(0), comp1 => comp1, \gcc0.gc0.count_d1_reg[0]\ => \gcc0.gc0.count_d1_reg[0]\, \gcc0.gc0.count_d1_reg[2]\ => \gcc0.gc0.count_d1_reg[2]\, \gcc0.gc0.count_d1_reg[4]\ => \gcc0.gc0.count_d1_reg[4]\, \gcc0.gc0.count_d1_reg[6]\ => \gcc0.gc0.count_d1_reg[6]\, \gcc0.gc0.count_d1_reg[8]\ => \gcc0.gc0.count_d1_reg[8]\, \out\ => ram_empty_fb_i, ram_empty_i_reg => c1_n_0, ram_full_fb_i_reg => ram_full_fb_i_reg, wr_en => wr_en ); c2: entity work.input_fifo_compare_2 port map ( comp1 => comp1, v1_reg(4 downto 0) => v1_reg(4 downto 0) ); ram_empty_fb_i_reg: unisim.vcomponents.FDSE generic map( INIT => '1' ) port map ( C => clk, CE => '1', D => c1_n_0, Q => ram_empty_fb_i, S => srst ); ram_empty_i_reg: unisim.vcomponents.FDSE generic map( INIT => '1' ) port map ( C => clk, CE => '1', D => c1_n_0, Q => ram_empty_i, S => srst ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity input_fifo_wr_status_flags_ss is port ( \out\ : out STD_LOGIC; full : out STD_LOGIC; \gcc0.gc0.count_d1_reg[9]\ : out STD_LOGIC_VECTOR ( 0 to 0 ); v1_reg : in STD_LOGIC_VECTOR ( 4 downto 0 ); v1_reg_0 : in STD_LOGIC_VECTOR ( 4 downto 0 ); srst : in STD_LOGIC; clk : in STD_LOGIC; wr_en : in STD_LOGIC; E : in STD_LOGIC_VECTOR ( 0 to 0 ) ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of input_fifo_wr_status_flags_ss : entity is "wr_status_flags_ss"; end input_fifo_wr_status_flags_ss; architecture STRUCTURE of input_fifo_wr_status_flags_ss is signal c0_n_0 : STD_LOGIC; signal comp1 : STD_LOGIC; signal ram_afull_fb : STD_LOGIC; attribute DONT_TOUCH : boolean; attribute DONT_TOUCH of ram_afull_fb : signal is std.standard.true; signal ram_afull_i : STD_LOGIC; attribute DONT_TOUCH of ram_afull_i : signal is std.standard.true; signal ram_full_fb_i : STD_LOGIC; attribute DONT_TOUCH of ram_full_fb_i : signal is std.standard.true; signal ram_full_i : STD_LOGIC; attribute DONT_TOUCH of ram_full_i : signal is std.standard.true; attribute DONT_TOUCH of ram_full_fb_i_reg : label is std.standard.true; attribute KEEP : string; attribute KEEP of ram_full_fb_i_reg : label is "yes"; attribute equivalent_register_removal : string; attribute equivalent_register_removal of ram_full_fb_i_reg : label is "no"; attribute DONT_TOUCH of ram_full_i_reg : label is std.standard.true; attribute KEEP of ram_full_i_reg : label is "yes"; attribute equivalent_register_removal of ram_full_i_reg : label is "no"; begin full <= ram_full_i; \out\ <= ram_full_fb_i; \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_i_1\: unisim.vcomponents.LUT2 generic map( INIT => X"2" ) port map ( I0 => wr_en, I1 => ram_full_fb_i, O => \gcc0.gc0.count_d1_reg[9]\(0) ); c0: entity work.input_fifo_compare port map ( E(0) => E(0), comp1 => comp1, \out\ => ram_full_fb_i, ram_full_fb_i_reg => c0_n_0, v1_reg(4 downto 0) => v1_reg(4 downto 0), wr_en => wr_en ); c1: entity work.input_fifo_compare_0 port map ( comp1 => comp1, v1_reg_0(4 downto 0) => v1_reg_0(4 downto 0) ); i_0: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => ram_afull_i ); i_1: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => ram_afull_fb ); ram_full_fb_i_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => clk, CE => '1', D => c0_n_0, Q => ram_full_fb_i, R => srst ); ram_full_i_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => clk, CE => '1', D => c0_n_0, Q => ram_full_i, R => srst ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity input_fifo_blk_mem_gen_generic_cstr is port ( D : out STD_LOGIC_VECTOR ( 7 downto 0 ); clk : in STD_LOGIC; WEA : in STD_LOGIC_VECTOR ( 0 to 0 ); tmp_ram_rd_en : in STD_LOGIC; srst : in STD_LOGIC; Q : in STD_LOGIC_VECTOR ( 9 downto 0 ); \gc0.count_d1_reg[9]\ : in STD_LOGIC_VECTOR ( 9 downto 0 ); din : in STD_LOGIC_VECTOR ( 7 downto 0 ) ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of input_fifo_blk_mem_gen_generic_cstr : entity is "blk_mem_gen_generic_cstr"; end input_fifo_blk_mem_gen_generic_cstr; architecture STRUCTURE of input_fifo_blk_mem_gen_generic_cstr is begin \ramloop[0].ram.r\: entity work.input_fifo_blk_mem_gen_prim_width port map ( D(7 downto 0) => D(7 downto 0), Q(9 downto 0) => Q(9 downto 0), WEA(0) => WEA(0), clk => clk, din(7 downto 0) => din(7 downto 0), \gc0.count_d1_reg[9]\(9 downto 0) => \gc0.count_d1_reg[9]\(9 downto 0), srst => srst, tmp_ram_rd_en => tmp_ram_rd_en ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity input_fifo_rd_logic is port ( empty : out STD_LOGIC; tmp_ram_rd_en : out STD_LOGIC; E : out STD_LOGIC_VECTOR ( 0 to 0 ); Q : out STD_LOGIC_VECTOR ( 9 downto 0 ); \goreg_bm.dout_i_reg[7]\ : out STD_LOGIC_VECTOR ( 0 to 0 ); \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram\ : out STD_LOGIC_VECTOR ( 9 downto 0 ); \gcc0.gc0.count_d1_reg[0]\ : in STD_LOGIC; \gcc0.gc0.count_d1_reg[2]\ : in STD_LOGIC; \gcc0.gc0.count_d1_reg[4]\ : in STD_LOGIC; \gcc0.gc0.count_d1_reg[6]\ : in STD_LOGIC; \gcc0.gc0.count_d1_reg[8]\ : in STD_LOGIC; v1_reg : in STD_LOGIC_VECTOR ( 4 downto 0 ); srst : in STD_LOGIC; clk : in STD_LOGIC; rd_en : in STD_LOGIC; wr_en : in STD_LOGIC; \out\ : in STD_LOGIC ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of input_fifo_rd_logic : entity is "rd_logic"; end input_fifo_rd_logic; architecture STRUCTURE of input_fifo_rd_logic is signal \^e\ : STD_LOGIC_VECTOR ( 0 to 0 ); signal p_2_out : STD_LOGIC; begin E(0) <= \^e\(0); \gr1.gr1_int.rfwft\: entity work.input_fifo_rd_fwft port map ( E(0) => \^e\(0), clk => clk, empty => empty, \goreg_bm.dout_i_reg[7]\(0) => \goreg_bm.dout_i_reg[7]\(0), \out\ => p_2_out, rd_en => rd_en, srst => srst, tmp_ram_rd_en => tmp_ram_rd_en ); \grss.rsts\: entity work.input_fifo_rd_status_flags_ss port map ( E(0) => \^e\(0), clk => clk, \gcc0.gc0.count_d1_reg[0]\ => \gcc0.gc0.count_d1_reg[0]\, \gcc0.gc0.count_d1_reg[2]\ => \gcc0.gc0.count_d1_reg[2]\, \gcc0.gc0.count_d1_reg[4]\ => \gcc0.gc0.count_d1_reg[4]\, \gcc0.gc0.count_d1_reg[6]\ => \gcc0.gc0.count_d1_reg[6]\, \gcc0.gc0.count_d1_reg[8]\ => \gcc0.gc0.count_d1_reg[8]\, \out\ => p_2_out, ram_full_fb_i_reg => \out\, srst => srst, v1_reg(4 downto 0) => v1_reg(4 downto 0), wr_en => wr_en ); rpntr: entity work.input_fifo_rd_bin_cntr port map ( \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram\(9 downto 0) => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram\(9 downto 0), E(0) => \^e\(0), Q(9 downto 0) => Q(9 downto 0), clk => clk, srst => srst ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity input_fifo_wr_logic is port ( \out\ : out STD_LOGIC; full : out STD_LOGIC; WEA : out STD_LOGIC_VECTOR ( 0 to 0 ); Q : out STD_LOGIC_VECTOR ( 9 downto 0 ); v1_reg : out STD_LOGIC_VECTOR ( 4 downto 0 ); ram_empty_i_reg : out STD_LOGIC; ram_empty_i_reg_0 : out STD_LOGIC; ram_empty_i_reg_1 : out STD_LOGIC; ram_empty_i_reg_2 : out STD_LOGIC; ram_empty_i_reg_3 : out STD_LOGIC; srst : in STD_LOGIC; clk : in STD_LOGIC; wr_en : in STD_LOGIC; E : in STD_LOGIC_VECTOR ( 0 to 0 ); \gc0.count_d1_reg[9]\ : in STD_LOGIC_VECTOR ( 9 downto 0 ); \gc0.count_reg[9]\ : in STD_LOGIC_VECTOR ( 9 downto 0 ) ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of input_fifo_wr_logic : entity is "wr_logic"; end input_fifo_wr_logic; architecture STRUCTURE of input_fifo_wr_logic is signal \^wea\ : STD_LOGIC_VECTOR ( 0 to 0 ); signal \c0/v1_reg\ : STD_LOGIC_VECTOR ( 4 downto 0 ); signal \c1/v1_reg\ : STD_LOGIC_VECTOR ( 4 downto 0 ); begin WEA(0) <= \^wea\(0); \gwss.wsts\: entity work.input_fifo_wr_status_flags_ss port map ( E(0) => E(0), clk => clk, full => full, \gcc0.gc0.count_d1_reg[9]\(0) => \^wea\(0), \out\ => \out\, srst => srst, v1_reg(4 downto 0) => \c0/v1_reg\(4 downto 0), v1_reg_0(4 downto 0) => \c1/v1_reg\(4 downto 0), wr_en => wr_en ); wpntr: entity work.input_fifo_wr_bin_cntr port map ( E(0) => \^wea\(0), Q(9 downto 0) => Q(9 downto 0), clk => clk, \gc0.count_d1_reg[9]\(9 downto 0) => \gc0.count_d1_reg[9]\(9 downto 0), \gc0.count_reg[9]\(9 downto 0) => \gc0.count_reg[9]\(9 downto 0), ram_empty_i_reg => ram_empty_i_reg, ram_empty_i_reg_0 => ram_empty_i_reg_0, ram_empty_i_reg_1 => ram_empty_i_reg_1, ram_empty_i_reg_2 => ram_empty_i_reg_2, ram_empty_i_reg_3 => ram_empty_i_reg_3, srst => srst, v1_reg(4 downto 0) => v1_reg(4 downto 0), v1_reg_0(4 downto 0) => \c0/v1_reg\(4 downto 0), v1_reg_1(4 downto 0) => \c1/v1_reg\(4 downto 0) ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity input_fifo_blk_mem_gen_top is port ( D : out STD_LOGIC_VECTOR ( 7 downto 0 ); clk : in STD_LOGIC; WEA : in STD_LOGIC_VECTOR ( 0 to 0 ); tmp_ram_rd_en : in STD_LOGIC; srst : in STD_LOGIC; Q : in STD_LOGIC_VECTOR ( 9 downto 0 ); \gc0.count_d1_reg[9]\ : in STD_LOGIC_VECTOR ( 9 downto 0 ); din : in STD_LOGIC_VECTOR ( 7 downto 0 ) ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of input_fifo_blk_mem_gen_top : entity is "blk_mem_gen_top"; end input_fifo_blk_mem_gen_top; architecture STRUCTURE of input_fifo_blk_mem_gen_top is begin \valid.cstr\: entity work.input_fifo_blk_mem_gen_generic_cstr port map ( D(7 downto 0) => D(7 downto 0), Q(9 downto 0) => Q(9 downto 0), WEA(0) => WEA(0), clk => clk, din(7 downto 0) => din(7 downto 0), \gc0.count_d1_reg[9]\(9 downto 0) => \gc0.count_d1_reg[9]\(9 downto 0), srst => srst, tmp_ram_rd_en => tmp_ram_rd_en ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity input_fifo_blk_mem_gen_v8_3_5_synth is port ( D : out STD_LOGIC_VECTOR ( 7 downto 0 ); clk : in STD_LOGIC; WEA : in STD_LOGIC_VECTOR ( 0 to 0 ); tmp_ram_rd_en : in STD_LOGIC; srst : in STD_LOGIC; Q : in STD_LOGIC_VECTOR ( 9 downto 0 ); \gc0.count_d1_reg[9]\ : in STD_LOGIC_VECTOR ( 9 downto 0 ); din : in STD_LOGIC_VECTOR ( 7 downto 0 ) ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of input_fifo_blk_mem_gen_v8_3_5_synth : entity is "blk_mem_gen_v8_3_5_synth"; end input_fifo_blk_mem_gen_v8_3_5_synth; architecture STRUCTURE of input_fifo_blk_mem_gen_v8_3_5_synth is begin \gnbram.gnativebmg.native_blk_mem_gen\: entity work.input_fifo_blk_mem_gen_top port map ( D(7 downto 0) => D(7 downto 0), Q(9 downto 0) => Q(9 downto 0), WEA(0) => WEA(0), clk => clk, din(7 downto 0) => din(7 downto 0), \gc0.count_d1_reg[9]\(9 downto 0) => \gc0.count_d1_reg[9]\(9 downto 0), srst => srst, tmp_ram_rd_en => tmp_ram_rd_en ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity input_fifo_blk_mem_gen_v8_3_5 is port ( D : out STD_LOGIC_VECTOR ( 7 downto 0 ); clk : in STD_LOGIC; WEA : in STD_LOGIC_VECTOR ( 0 to 0 ); tmp_ram_rd_en : in STD_LOGIC; srst : in STD_LOGIC; Q : in STD_LOGIC_VECTOR ( 9 downto 0 ); \gc0.count_d1_reg[9]\ : in STD_LOGIC_VECTOR ( 9 downto 0 ); din : in STD_LOGIC_VECTOR ( 7 downto 0 ) ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of input_fifo_blk_mem_gen_v8_3_5 : entity is "blk_mem_gen_v8_3_5"; end input_fifo_blk_mem_gen_v8_3_5; architecture STRUCTURE of input_fifo_blk_mem_gen_v8_3_5 is begin inst_blk_mem_gen: entity work.input_fifo_blk_mem_gen_v8_3_5_synth port map ( D(7 downto 0) => D(7 downto 0), Q(9 downto 0) => Q(9 downto 0), WEA(0) => WEA(0), clk => clk, din(7 downto 0) => din(7 downto 0), \gc0.count_d1_reg[9]\(9 downto 0) => \gc0.count_d1_reg[9]\(9 downto 0), srst => srst, tmp_ram_rd_en => tmp_ram_rd_en ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity input_fifo_memory is port ( dout : out STD_LOGIC_VECTOR ( 7 downto 0 ); clk : in STD_LOGIC; WEA : in STD_LOGIC_VECTOR ( 0 to 0 ); tmp_ram_rd_en : in STD_LOGIC; srst : in STD_LOGIC; Q : in STD_LOGIC_VECTOR ( 9 downto 0 ); \gc0.count_d1_reg[9]\ : in STD_LOGIC_VECTOR ( 9 downto 0 ); din : in STD_LOGIC_VECTOR ( 7 downto 0 ); E : in STD_LOGIC_VECTOR ( 0 to 0 ) ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of input_fifo_memory : entity is "memory"; end input_fifo_memory; architecture STRUCTURE of input_fifo_memory is signal doutb : STD_LOGIC_VECTOR ( 7 downto 0 ); begin \gbm.gbmg.gbmga.ngecc.bmg\: entity work.input_fifo_blk_mem_gen_v8_3_5 port map ( D(7 downto 0) => doutb(7 downto 0), Q(9 downto 0) => Q(9 downto 0), WEA(0) => WEA(0), clk => clk, din(7 downto 0) => din(7 downto 0), \gc0.count_d1_reg[9]\(9 downto 0) => \gc0.count_d1_reg[9]\(9 downto 0), srst => srst, tmp_ram_rd_en => tmp_ram_rd_en ); \goreg_bm.dout_i_reg[0]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => clk, CE => E(0), D => doutb(0), Q => dout(0), R => srst ); \goreg_bm.dout_i_reg[1]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => clk, CE => E(0), D => doutb(1), Q => dout(1), R => srst ); \goreg_bm.dout_i_reg[2]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => clk, CE => E(0), D => doutb(2), Q => dout(2), R => srst ); \goreg_bm.dout_i_reg[3]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => clk, CE => E(0), D => doutb(3), Q => dout(3), R => srst ); \goreg_bm.dout_i_reg[4]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => clk, CE => E(0), D => doutb(4), Q => dout(4), R => srst ); \goreg_bm.dout_i_reg[5]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => clk, CE => E(0), D => doutb(5), Q => dout(5), R => srst ); \goreg_bm.dout_i_reg[6]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => clk, CE => E(0), D => doutb(6), Q => dout(6), R => srst ); \goreg_bm.dout_i_reg[7]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => clk, CE => E(0), D => doutb(7), Q => dout(7), R => srst ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity input_fifo_fifo_generator_ramfifo is port ( empty : out STD_LOGIC; full : out STD_LOGIC; dout : out STD_LOGIC_VECTOR ( 7 downto 0 ); wr_en : in STD_LOGIC; clk : in STD_LOGIC; srst : in STD_LOGIC; din : in STD_LOGIC_VECTOR ( 7 downto 0 ); rd_en : in STD_LOGIC ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of input_fifo_fifo_generator_ramfifo : entity is "fifo_generator_ramfifo"; end input_fifo_fifo_generator_ramfifo; architecture STRUCTURE of input_fifo_fifo_generator_ramfifo is signal \gntv_or_sync_fifo.gl0.wr_n_0\ : STD_LOGIC; signal \gntv_or_sync_fifo.gl0.wr_n_18\ : STD_LOGIC; signal \gntv_or_sync_fifo.gl0.wr_n_19\ : STD_LOGIC; signal \gntv_or_sync_fifo.gl0.wr_n_2\ : STD_LOGIC; signal \gntv_or_sync_fifo.gl0.wr_n_20\ : STD_LOGIC; signal \gntv_or_sync_fifo.gl0.wr_n_21\ : STD_LOGIC; signal \gntv_or_sync_fifo.gl0.wr_n_22\ : STD_LOGIC; signal \grss.rsts/c2/v1_reg\ : STD_LOGIC_VECTOR ( 4 downto 0 ); signal p_0_out : STD_LOGIC_VECTOR ( 9 downto 0 ); signal p_11_out : STD_LOGIC_VECTOR ( 9 downto 0 ); signal p_5_out : STD_LOGIC; signal p_7_out : STD_LOGIC; signal rd_pntr_plus1 : STD_LOGIC_VECTOR ( 9 downto 0 ); signal tmp_ram_rd_en : STD_LOGIC; begin \gntv_or_sync_fifo.gl0.rd\: entity work.input_fifo_rd_logic port map ( \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram\(9 downto 0) => p_0_out(9 downto 0), E(0) => p_7_out, Q(9 downto 0) => rd_pntr_plus1(9 downto 0), clk => clk, empty => empty, \gcc0.gc0.count_d1_reg[0]\ => \gntv_or_sync_fifo.gl0.wr_n_18\, \gcc0.gc0.count_d1_reg[2]\ => \gntv_or_sync_fifo.gl0.wr_n_19\, \gcc0.gc0.count_d1_reg[4]\ => \gntv_or_sync_fifo.gl0.wr_n_20\, \gcc0.gc0.count_d1_reg[6]\ => \gntv_or_sync_fifo.gl0.wr_n_21\, \gcc0.gc0.count_d1_reg[8]\ => \gntv_or_sync_fifo.gl0.wr_n_22\, \goreg_bm.dout_i_reg[7]\(0) => p_5_out, \out\ => \gntv_or_sync_fifo.gl0.wr_n_0\, rd_en => rd_en, srst => srst, tmp_ram_rd_en => tmp_ram_rd_en, v1_reg(4 downto 0) => \grss.rsts/c2/v1_reg\(4 downto 0), wr_en => wr_en ); \gntv_or_sync_fifo.gl0.wr\: entity work.input_fifo_wr_logic port map ( E(0) => p_7_out, Q(9 downto 0) => p_11_out(9 downto 0), WEA(0) => \gntv_or_sync_fifo.gl0.wr_n_2\, clk => clk, full => full, \gc0.count_d1_reg[9]\(9 downto 0) => p_0_out(9 downto 0), \gc0.count_reg[9]\(9 downto 0) => rd_pntr_plus1(9 downto 0), \out\ => \gntv_or_sync_fifo.gl0.wr_n_0\, ram_empty_i_reg => \gntv_or_sync_fifo.gl0.wr_n_18\, ram_empty_i_reg_0 => \gntv_or_sync_fifo.gl0.wr_n_19\, ram_empty_i_reg_1 => \gntv_or_sync_fifo.gl0.wr_n_20\, ram_empty_i_reg_2 => \gntv_or_sync_fifo.gl0.wr_n_21\, ram_empty_i_reg_3 => \gntv_or_sync_fifo.gl0.wr_n_22\, srst => srst, v1_reg(4 downto 0) => \grss.rsts/c2/v1_reg\(4 downto 0), wr_en => wr_en ); \gntv_or_sync_fifo.mem\: entity work.input_fifo_memory port map ( E(0) => p_5_out, Q(9 downto 0) => p_11_out(9 downto 0), WEA(0) => \gntv_or_sync_fifo.gl0.wr_n_2\, clk => clk, din(7 downto 0) => din(7 downto 0), dout(7 downto 0) => dout(7 downto 0), \gc0.count_d1_reg[9]\(9 downto 0) => p_0_out(9 downto 0), srst => srst, tmp_ram_rd_en => tmp_ram_rd_en ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity input_fifo_fifo_generator_top is port ( empty : out STD_LOGIC; full : out STD_LOGIC; dout : out STD_LOGIC_VECTOR ( 7 downto 0 ); wr_en : in STD_LOGIC; clk : in STD_LOGIC; srst : in STD_LOGIC; din : in STD_LOGIC_VECTOR ( 7 downto 0 ); rd_en : in STD_LOGIC ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of input_fifo_fifo_generator_top : entity is "fifo_generator_top"; end input_fifo_fifo_generator_top; architecture STRUCTURE of input_fifo_fifo_generator_top is begin \grf.rf\: entity work.input_fifo_fifo_generator_ramfifo port map ( clk => clk, din(7 downto 0) => din(7 downto 0), dout(7 downto 0) => dout(7 downto 0), empty => empty, full => full, rd_en => rd_en, srst => srst, wr_en => wr_en ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity input_fifo_fifo_generator_v13_1_3_synth is port ( empty : out STD_LOGIC; full : out STD_LOGIC; dout : out STD_LOGIC_VECTOR ( 7 downto 0 ); wr_en : in STD_LOGIC; clk : in STD_LOGIC; srst : in STD_LOGIC; din : in STD_LOGIC_VECTOR ( 7 downto 0 ); rd_en : in STD_LOGIC ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of input_fifo_fifo_generator_v13_1_3_synth : entity is "fifo_generator_v13_1_3_synth"; end input_fifo_fifo_generator_v13_1_3_synth; architecture STRUCTURE of input_fifo_fifo_generator_v13_1_3_synth is begin \gconvfifo.rf\: entity work.input_fifo_fifo_generator_top port map ( clk => clk, din(7 downto 0) => din(7 downto 0), dout(7 downto 0) => dout(7 downto 0), empty => empty, full => full, rd_en => rd_en, srst => srst, wr_en => wr_en ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity input_fifo_fifo_generator_v13_1_3 is port ( backup : in STD_LOGIC; backup_marker : in STD_LOGIC; clk : in STD_LOGIC; rst : in STD_LOGIC; srst : in STD_LOGIC; wr_clk : in STD_LOGIC; wr_rst : in STD_LOGIC; rd_clk : in STD_LOGIC; rd_rst : in STD_LOGIC; din : in STD_LOGIC_VECTOR ( 7 downto 0 ); wr_en : in STD_LOGIC; rd_en : in STD_LOGIC; prog_empty_thresh : in STD_LOGIC_VECTOR ( 9 downto 0 ); prog_empty_thresh_assert : in STD_LOGIC_VECTOR ( 9 downto 0 ); prog_empty_thresh_negate : in STD_LOGIC_VECTOR ( 9 downto 0 ); prog_full_thresh : in STD_LOGIC_VECTOR ( 9 downto 0 ); prog_full_thresh_assert : in STD_LOGIC_VECTOR ( 9 downto 0 ); prog_full_thresh_negate : in STD_LOGIC_VECTOR ( 9 downto 0 ); int_clk : in STD_LOGIC; injectdbiterr : in STD_LOGIC; injectsbiterr : in STD_LOGIC; sleep : in STD_LOGIC; dout : out STD_LOGIC_VECTOR ( 7 downto 0 ); full : out STD_LOGIC; almost_full : out STD_LOGIC; wr_ack : out STD_LOGIC; overflow : out STD_LOGIC; empty : out STD_LOGIC; almost_empty : out STD_LOGIC; valid : out STD_LOGIC; underflow : out STD_LOGIC; data_count : out STD_LOGIC_VECTOR ( 10 downto 0 ); rd_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 ); wr_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 ); prog_full : out STD_LOGIC; prog_empty : out STD_LOGIC; sbiterr : out STD_LOGIC; dbiterr : out STD_LOGIC; wr_rst_busy : out STD_LOGIC; rd_rst_busy : out STD_LOGIC; m_aclk : in STD_LOGIC; s_aclk : in STD_LOGIC; s_aresetn : in STD_LOGIC; m_aclk_en : in STD_LOGIC; s_aclk_en : in STD_LOGIC; s_axi_awid : in STD_LOGIC_VECTOR ( 0 to 0 ); s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 ); s_axi_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 ); s_axi_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 ); s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 ); s_axi_awlock : in STD_LOGIC_VECTOR ( 0 to 0 ); s_axi_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 ); s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 ); s_axi_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 ); s_axi_awregion : in STD_LOGIC_VECTOR ( 3 downto 0 ); s_axi_awuser : in STD_LOGIC_VECTOR ( 0 to 0 ); s_axi_awvalid : in STD_LOGIC; s_axi_awready : out STD_LOGIC; s_axi_wid : in STD_LOGIC_VECTOR ( 0 to 0 ); s_axi_wdata : in STD_LOGIC_VECTOR ( 63 downto 0 ); s_axi_wstrb : in STD_LOGIC_VECTOR ( 7 downto 0 ); s_axi_wlast : in STD_LOGIC; s_axi_wuser : in STD_LOGIC_VECTOR ( 0 to 0 ); s_axi_wvalid : in STD_LOGIC; s_axi_wready : out STD_LOGIC; s_axi_bid : out STD_LOGIC_VECTOR ( 0 to 0 ); s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 ); s_axi_buser : out STD_LOGIC_VECTOR ( 0 to 0 ); s_axi_bvalid : out STD_LOGIC; s_axi_bready : in STD_LOGIC; m_axi_awid : out STD_LOGIC_VECTOR ( 0 to 0 ); m_axi_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 ); m_axi_awlen : out STD_LOGIC_VECTOR ( 7 downto 0 ); m_axi_awsize : out STD_LOGIC_VECTOR ( 2 downto 0 ); m_axi_awburst : out STD_LOGIC_VECTOR ( 1 downto 0 ); m_axi_awlock : out STD_LOGIC_VECTOR ( 0 to 0 ); m_axi_awcache : out STD_LOGIC_VECTOR ( 3 downto 0 ); m_axi_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 ); m_axi_awqos : out STD_LOGIC_VECTOR ( 3 downto 0 ); m_axi_awregion : out STD_LOGIC_VECTOR ( 3 downto 0 ); m_axi_awuser : out STD_LOGIC_VECTOR ( 0 to 0 ); m_axi_awvalid : out STD_LOGIC; m_axi_awready : in STD_LOGIC; m_axi_wid : out STD_LOGIC_VECTOR ( 0 to 0 ); m_axi_wdata : out STD_LOGIC_VECTOR ( 63 downto 0 ); m_axi_wstrb : out STD_LOGIC_VECTOR ( 7 downto 0 ); m_axi_wlast : out STD_LOGIC; m_axi_wuser : out STD_LOGIC_VECTOR ( 0 to 0 ); m_axi_wvalid : out STD_LOGIC; m_axi_wready : in STD_LOGIC; m_axi_bid : in STD_LOGIC_VECTOR ( 0 to 0 ); m_axi_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 ); m_axi_buser : in STD_LOGIC_VECTOR ( 0 to 0 ); m_axi_bvalid : in STD_LOGIC; m_axi_bready : out STD_LOGIC; s_axi_arid : in STD_LOGIC_VECTOR ( 0 to 0 ); s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 ); s_axi_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 ); s_axi_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 ); s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 ); s_axi_arlock : in STD_LOGIC_VECTOR ( 0 to 0 ); s_axi_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 ); s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 ); s_axi_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 ); s_axi_arregion : in STD_LOGIC_VECTOR ( 3 downto 0 ); s_axi_aruser : in STD_LOGIC_VECTOR ( 0 to 0 ); s_axi_arvalid : in STD_LOGIC; s_axi_arready : out STD_LOGIC; s_axi_rid : out STD_LOGIC_VECTOR ( 0 to 0 ); s_axi_rdata : out STD_LOGIC_VECTOR ( 63 downto 0 ); s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 ); s_axi_rlast : out STD_LOGIC; s_axi_ruser : out STD_LOGIC_VECTOR ( 0 to 0 ); s_axi_rvalid : out STD_LOGIC; s_axi_rready : in STD_LOGIC; m_axi_arid : out STD_LOGIC_VECTOR ( 0 to 0 ); m_axi_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 ); m_axi_arlen : out STD_LOGIC_VECTOR ( 7 downto 0 ); m_axi_arsize : out STD_LOGIC_VECTOR ( 2 downto 0 ); m_axi_arburst : out STD_LOGIC_VECTOR ( 1 downto 0 ); m_axi_arlock : out STD_LOGIC_VECTOR ( 0 to 0 ); m_axi_arcache : out STD_LOGIC_VECTOR ( 3 downto 0 ); m_axi_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 ); m_axi_arqos : out STD_LOGIC_VECTOR ( 3 downto 0 ); m_axi_arregion : out STD_LOGIC_VECTOR ( 3 downto 0 ); m_axi_aruser : out STD_LOGIC_VECTOR ( 0 to 0 ); m_axi_arvalid : out STD_LOGIC; m_axi_arready : in STD_LOGIC; m_axi_rid : in STD_LOGIC_VECTOR ( 0 to 0 ); m_axi_rdata : in STD_LOGIC_VECTOR ( 63 downto 0 ); m_axi_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 ); m_axi_rlast : in STD_LOGIC; m_axi_ruser : in STD_LOGIC_VECTOR ( 0 to 0 ); m_axi_rvalid : in STD_LOGIC; m_axi_rready : out STD_LOGIC; s_axis_tvalid : in STD_LOGIC; s_axis_tready : out STD_LOGIC; s_axis_tdata : in STD_LOGIC_VECTOR ( 7 downto 0 ); s_axis_tstrb : in STD_LOGIC_VECTOR ( 0 to 0 ); s_axis_tkeep : in STD_LOGIC_VECTOR ( 0 to 0 ); s_axis_tlast : in STD_LOGIC; s_axis_tid : in STD_LOGIC_VECTOR ( 0 to 0 ); s_axis_tdest : in STD_LOGIC_VECTOR ( 0 to 0 ); s_axis_tuser : in STD_LOGIC_VECTOR ( 3 downto 0 ); m_axis_tvalid : out STD_LOGIC; m_axis_tready : in STD_LOGIC; m_axis_tdata : out STD_LOGIC_VECTOR ( 7 downto 0 ); m_axis_tstrb : out STD_LOGIC_VECTOR ( 0 to 0 ); m_axis_tkeep : out STD_LOGIC_VECTOR ( 0 to 0 ); m_axis_tlast : out STD_LOGIC; m_axis_tid : out STD_LOGIC_VECTOR ( 0 to 0 ); m_axis_tdest : out STD_LOGIC_VECTOR ( 0 to 0 ); m_axis_tuser : out STD_LOGIC_VECTOR ( 3 downto 0 ); axi_aw_injectsbiterr : in STD_LOGIC; axi_aw_injectdbiterr : in STD_LOGIC; axi_aw_prog_full_thresh : in STD_LOGIC_VECTOR ( 3 downto 0 ); axi_aw_prog_empty_thresh : in STD_LOGIC_VECTOR ( 3 downto 0 ); axi_aw_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 ); axi_aw_wr_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 ); axi_aw_rd_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 ); axi_aw_sbiterr : out STD_LOGIC; axi_aw_dbiterr : out STD_LOGIC; axi_aw_overflow : out STD_LOGIC; axi_aw_underflow : out STD_LOGIC; axi_aw_prog_full : out STD_LOGIC; axi_aw_prog_empty : out STD_LOGIC; axi_w_injectsbiterr : in STD_LOGIC; axi_w_injectdbiterr : in STD_LOGIC; axi_w_prog_full_thresh : in STD_LOGIC_VECTOR ( 9 downto 0 ); axi_w_prog_empty_thresh : in STD_LOGIC_VECTOR ( 9 downto 0 ); axi_w_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 ); axi_w_wr_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 ); axi_w_rd_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 ); axi_w_sbiterr : out STD_LOGIC; axi_w_dbiterr : out STD_LOGIC; axi_w_overflow : out STD_LOGIC; axi_w_underflow : out STD_LOGIC; axi_w_prog_full : out STD_LOGIC; axi_w_prog_empty : out STD_LOGIC; axi_b_injectsbiterr : in STD_LOGIC; axi_b_injectdbiterr : in STD_LOGIC; axi_b_prog_full_thresh : in STD_LOGIC_VECTOR ( 3 downto 0 ); axi_b_prog_empty_thresh : in STD_LOGIC_VECTOR ( 3 downto 0 ); axi_b_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 ); axi_b_wr_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 ); axi_b_rd_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 ); axi_b_sbiterr : out STD_LOGIC; axi_b_dbiterr : out STD_LOGIC; axi_b_overflow : out STD_LOGIC; axi_b_underflow : out STD_LOGIC; axi_b_prog_full : out STD_LOGIC; axi_b_prog_empty : out STD_LOGIC; axi_ar_injectsbiterr : in STD_LOGIC; axi_ar_injectdbiterr : in STD_LOGIC; axi_ar_prog_full_thresh : in STD_LOGIC_VECTOR ( 3 downto 0 ); axi_ar_prog_empty_thresh : in STD_LOGIC_VECTOR ( 3 downto 0 ); axi_ar_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 ); axi_ar_wr_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 ); axi_ar_rd_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 ); axi_ar_sbiterr : out STD_LOGIC; axi_ar_dbiterr : out STD_LOGIC; axi_ar_overflow : out STD_LOGIC; axi_ar_underflow : out STD_LOGIC; axi_ar_prog_full : out STD_LOGIC; axi_ar_prog_empty : out STD_LOGIC; axi_r_injectsbiterr : in STD_LOGIC; axi_r_injectdbiterr : in STD_LOGIC; axi_r_prog_full_thresh : in STD_LOGIC_VECTOR ( 9 downto 0 ); axi_r_prog_empty_thresh : in STD_LOGIC_VECTOR ( 9 downto 0 ); axi_r_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 ); axi_r_wr_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 ); axi_r_rd_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 ); axi_r_sbiterr : out STD_LOGIC; axi_r_dbiterr : out STD_LOGIC; axi_r_overflow : out STD_LOGIC; axi_r_underflow : out STD_LOGIC; axi_r_prog_full : out STD_LOGIC; axi_r_prog_empty : out STD_LOGIC; axis_injectsbiterr : in STD_LOGIC; axis_injectdbiterr : in STD_LOGIC; axis_prog_full_thresh : in STD_LOGIC_VECTOR ( 9 downto 0 ); axis_prog_empty_thresh : in STD_LOGIC_VECTOR ( 9 downto 0 ); axis_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 ); axis_wr_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 ); axis_rd_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 ); axis_sbiterr : out STD_LOGIC; axis_dbiterr : out STD_LOGIC; axis_overflow : out STD_LOGIC; axis_underflow : out STD_LOGIC; axis_prog_full : out STD_LOGIC; axis_prog_empty : out STD_LOGIC ); attribute C_ADD_NGC_CONSTRAINT : integer; attribute C_ADD_NGC_CONSTRAINT of input_fifo_fifo_generator_v13_1_3 : entity is 0; attribute C_APPLICATION_TYPE_AXIS : integer; attribute C_APPLICATION_TYPE_AXIS of input_fifo_fifo_generator_v13_1_3 : entity is 0; attribute C_APPLICATION_TYPE_RACH : integer; attribute C_APPLICATION_TYPE_RACH of input_fifo_fifo_generator_v13_1_3 : entity is 0; attribute C_APPLICATION_TYPE_RDCH : integer; attribute C_APPLICATION_TYPE_RDCH of input_fifo_fifo_generator_v13_1_3 : entity is 0; attribute C_APPLICATION_TYPE_WACH : integer; attribute C_APPLICATION_TYPE_WACH of input_fifo_fifo_generator_v13_1_3 : entity is 0; attribute C_APPLICATION_TYPE_WDCH : integer; attribute C_APPLICATION_TYPE_WDCH of input_fifo_fifo_generator_v13_1_3 : entity is 0; attribute C_APPLICATION_TYPE_WRCH : integer; attribute C_APPLICATION_TYPE_WRCH of input_fifo_fifo_generator_v13_1_3 : entity is 0; attribute C_AXIS_TDATA_WIDTH : integer; attribute C_AXIS_TDATA_WIDTH of input_fifo_fifo_generator_v13_1_3 : entity is 8; attribute C_AXIS_TDEST_WIDTH : integer; attribute C_AXIS_TDEST_WIDTH of input_fifo_fifo_generator_v13_1_3 : entity is 1; attribute C_AXIS_TID_WIDTH : integer; attribute C_AXIS_TID_WIDTH of input_fifo_fifo_generator_v13_1_3 : entity is 1; attribute C_AXIS_TKEEP_WIDTH : integer; attribute C_AXIS_TKEEP_WIDTH of input_fifo_fifo_generator_v13_1_3 : entity is 1; attribute C_AXIS_TSTRB_WIDTH : integer; attribute C_AXIS_TSTRB_WIDTH of input_fifo_fifo_generator_v13_1_3 : entity is 1; attribute C_AXIS_TUSER_WIDTH : integer; attribute C_AXIS_TUSER_WIDTH of input_fifo_fifo_generator_v13_1_3 : entity is 4; attribute C_AXIS_TYPE : integer; attribute C_AXIS_TYPE of input_fifo_fifo_generator_v13_1_3 : entity is 0; attribute C_AXI_ADDR_WIDTH : integer; attribute C_AXI_ADDR_WIDTH of input_fifo_fifo_generator_v13_1_3 : entity is 32; attribute C_AXI_ARUSER_WIDTH : integer; attribute C_AXI_ARUSER_WIDTH of input_fifo_fifo_generator_v13_1_3 : entity is 1; attribute C_AXI_AWUSER_WIDTH : integer; attribute C_AXI_AWUSER_WIDTH of input_fifo_fifo_generator_v13_1_3 : entity is 1; attribute C_AXI_BUSER_WIDTH : integer; attribute C_AXI_BUSER_WIDTH of input_fifo_fifo_generator_v13_1_3 : entity is 1; attribute C_AXI_DATA_WIDTH : integer; attribute C_AXI_DATA_WIDTH of input_fifo_fifo_generator_v13_1_3 : entity is 64; attribute C_AXI_ID_WIDTH : integer; attribute C_AXI_ID_WIDTH of input_fifo_fifo_generator_v13_1_3 : entity is 1; attribute C_AXI_LEN_WIDTH : integer; attribute C_AXI_LEN_WIDTH of input_fifo_fifo_generator_v13_1_3 : entity is 8; attribute C_AXI_LOCK_WIDTH : integer; attribute C_AXI_LOCK_WIDTH of input_fifo_fifo_generator_v13_1_3 : entity is 1; attribute C_AXI_RUSER_WIDTH : integer; attribute C_AXI_RUSER_WIDTH of input_fifo_fifo_generator_v13_1_3 : entity is 1; attribute C_AXI_TYPE : integer; attribute C_AXI_TYPE of input_fifo_fifo_generator_v13_1_3 : entity is 1; attribute C_AXI_WUSER_WIDTH : integer; attribute C_AXI_WUSER_WIDTH of input_fifo_fifo_generator_v13_1_3 : entity is 1; attribute C_COMMON_CLOCK : integer; attribute C_COMMON_CLOCK of input_fifo_fifo_generator_v13_1_3 : entity is 1; attribute C_COUNT_TYPE : integer; attribute C_COUNT_TYPE of input_fifo_fifo_generator_v13_1_3 : entity is 0; attribute C_DATA_COUNT_WIDTH : integer; attribute C_DATA_COUNT_WIDTH of input_fifo_fifo_generator_v13_1_3 : entity is 11; attribute C_DEFAULT_VALUE : string; attribute C_DEFAULT_VALUE of input_fifo_fifo_generator_v13_1_3 : entity is "BlankString"; attribute C_DIN_WIDTH : integer; attribute C_DIN_WIDTH of input_fifo_fifo_generator_v13_1_3 : entity is 8; attribute C_DIN_WIDTH_AXIS : integer; attribute C_DIN_WIDTH_AXIS of input_fifo_fifo_generator_v13_1_3 : entity is 1; attribute C_DIN_WIDTH_RACH : integer; attribute C_DIN_WIDTH_RACH of input_fifo_fifo_generator_v13_1_3 : entity is 32; attribute C_DIN_WIDTH_RDCH : integer; attribute C_DIN_WIDTH_RDCH of input_fifo_fifo_generator_v13_1_3 : entity is 64; attribute C_DIN_WIDTH_WACH : integer; attribute C_DIN_WIDTH_WACH of input_fifo_fifo_generator_v13_1_3 : entity is 1; attribute C_DIN_WIDTH_WDCH : integer; attribute C_DIN_WIDTH_WDCH of input_fifo_fifo_generator_v13_1_3 : entity is 64; attribute C_DIN_WIDTH_WRCH : integer; attribute C_DIN_WIDTH_WRCH of input_fifo_fifo_generator_v13_1_3 : entity is 2; attribute C_DOUT_RST_VAL : string; attribute C_DOUT_RST_VAL of input_fifo_fifo_generator_v13_1_3 : entity is "0"; attribute C_DOUT_WIDTH : integer; attribute C_DOUT_WIDTH of input_fifo_fifo_generator_v13_1_3 : entity is 8; attribute C_ENABLE_RLOCS : integer; attribute C_ENABLE_RLOCS of input_fifo_fifo_generator_v13_1_3 : entity is 0; attribute C_ENABLE_RST_SYNC : integer; attribute C_ENABLE_RST_SYNC of input_fifo_fifo_generator_v13_1_3 : entity is 1; attribute C_EN_SAFETY_CKT : integer; attribute C_EN_SAFETY_CKT of input_fifo_fifo_generator_v13_1_3 : entity is 0; attribute C_ERROR_INJECTION_TYPE : integer; attribute C_ERROR_INJECTION_TYPE of input_fifo_fifo_generator_v13_1_3 : entity is 0; attribute C_ERROR_INJECTION_TYPE_AXIS : integer; attribute C_ERROR_INJECTION_TYPE_AXIS of input_fifo_fifo_generator_v13_1_3 : entity is 0; attribute C_ERROR_INJECTION_TYPE_RACH : integer; attribute C_ERROR_INJECTION_TYPE_RACH of input_fifo_fifo_generator_v13_1_3 : entity is 0; attribute C_ERROR_INJECTION_TYPE_RDCH : integer; attribute C_ERROR_INJECTION_TYPE_RDCH of input_fifo_fifo_generator_v13_1_3 : entity is 0; attribute C_ERROR_INJECTION_TYPE_WACH : integer; attribute C_ERROR_INJECTION_TYPE_WACH of input_fifo_fifo_generator_v13_1_3 : entity is 0; attribute C_ERROR_INJECTION_TYPE_WDCH : integer; attribute C_ERROR_INJECTION_TYPE_WDCH of input_fifo_fifo_generator_v13_1_3 : entity is 0; attribute C_ERROR_INJECTION_TYPE_WRCH : integer; attribute C_ERROR_INJECTION_TYPE_WRCH of input_fifo_fifo_generator_v13_1_3 : entity is 0; attribute C_FAMILY : string; attribute C_FAMILY of input_fifo_fifo_generator_v13_1_3 : entity is "zynq"; attribute C_FULL_FLAGS_RST_VAL : integer; attribute C_FULL_FLAGS_RST_VAL of input_fifo_fifo_generator_v13_1_3 : entity is 0; attribute C_HAS_ALMOST_EMPTY : integer; attribute C_HAS_ALMOST_EMPTY of input_fifo_fifo_generator_v13_1_3 : entity is 0; attribute C_HAS_ALMOST_FULL : integer; attribute C_HAS_ALMOST_FULL of input_fifo_fifo_generator_v13_1_3 : entity is 0; attribute C_HAS_AXIS_TDATA : integer; attribute C_HAS_AXIS_TDATA of input_fifo_fifo_generator_v13_1_3 : entity is 1; attribute C_HAS_AXIS_TDEST : integer; attribute C_HAS_AXIS_TDEST of input_fifo_fifo_generator_v13_1_3 : entity is 0; attribute C_HAS_AXIS_TID : integer; attribute C_HAS_AXIS_TID of input_fifo_fifo_generator_v13_1_3 : entity is 0; attribute C_HAS_AXIS_TKEEP : integer; attribute C_HAS_AXIS_TKEEP of input_fifo_fifo_generator_v13_1_3 : entity is 0; attribute C_HAS_AXIS_TLAST : integer; attribute C_HAS_AXIS_TLAST of input_fifo_fifo_generator_v13_1_3 : entity is 0; attribute C_HAS_AXIS_TREADY : integer; attribute C_HAS_AXIS_TREADY of input_fifo_fifo_generator_v13_1_3 : entity is 1; attribute C_HAS_AXIS_TSTRB : integer; attribute C_HAS_AXIS_TSTRB of input_fifo_fifo_generator_v13_1_3 : entity is 0; attribute C_HAS_AXIS_TUSER : integer; attribute C_HAS_AXIS_TUSER of input_fifo_fifo_generator_v13_1_3 : entity is 1; attribute C_HAS_AXI_ARUSER : integer; attribute C_HAS_AXI_ARUSER of input_fifo_fifo_generator_v13_1_3 : entity is 0; attribute C_HAS_AXI_AWUSER : integer; attribute C_HAS_AXI_AWUSER of input_fifo_fifo_generator_v13_1_3 : entity is 0; attribute C_HAS_AXI_BUSER : integer; attribute C_HAS_AXI_BUSER of input_fifo_fifo_generator_v13_1_3 : entity is 0; attribute C_HAS_AXI_ID : integer; attribute C_HAS_AXI_ID of input_fifo_fifo_generator_v13_1_3 : entity is 0; attribute C_HAS_AXI_RD_CHANNEL : integer; attribute C_HAS_AXI_RD_CHANNEL of input_fifo_fifo_generator_v13_1_3 : entity is 1; attribute C_HAS_AXI_RUSER : integer; attribute C_HAS_AXI_RUSER of input_fifo_fifo_generator_v13_1_3 : entity is 0; attribute C_HAS_AXI_WR_CHANNEL : integer; attribute C_HAS_AXI_WR_CHANNEL of input_fifo_fifo_generator_v13_1_3 : entity is 1; attribute C_HAS_AXI_WUSER : integer; attribute C_HAS_AXI_WUSER of input_fifo_fifo_generator_v13_1_3 : entity is 0; attribute C_HAS_BACKUP : integer; attribute C_HAS_BACKUP of input_fifo_fifo_generator_v13_1_3 : entity is 0; attribute C_HAS_DATA_COUNT : integer; attribute C_HAS_DATA_COUNT of input_fifo_fifo_generator_v13_1_3 : entity is 0; attribute C_HAS_DATA_COUNTS_AXIS : integer; attribute C_HAS_DATA_COUNTS_AXIS of input_fifo_fifo_generator_v13_1_3 : entity is 0; attribute C_HAS_DATA_COUNTS_RACH : integer; attribute C_HAS_DATA_COUNTS_RACH of input_fifo_fifo_generator_v13_1_3 : entity is 0; attribute C_HAS_DATA_COUNTS_RDCH : integer; attribute C_HAS_DATA_COUNTS_RDCH of input_fifo_fifo_generator_v13_1_3 : entity is 0; attribute C_HAS_DATA_COUNTS_WACH : integer; attribute C_HAS_DATA_COUNTS_WACH of input_fifo_fifo_generator_v13_1_3 : entity is 0; attribute C_HAS_DATA_COUNTS_WDCH : integer; attribute C_HAS_DATA_COUNTS_WDCH of input_fifo_fifo_generator_v13_1_3 : entity is 0; attribute C_HAS_DATA_COUNTS_WRCH : integer; attribute C_HAS_DATA_COUNTS_WRCH of input_fifo_fifo_generator_v13_1_3 : entity is 0; attribute C_HAS_INT_CLK : integer; attribute C_HAS_INT_CLK of input_fifo_fifo_generator_v13_1_3 : entity is 0; attribute C_HAS_MASTER_CE : integer; attribute C_HAS_MASTER_CE of input_fifo_fifo_generator_v13_1_3 : entity is 0; attribute C_HAS_MEMINIT_FILE : integer; attribute C_HAS_MEMINIT_FILE of input_fifo_fifo_generator_v13_1_3 : entity is 0; attribute C_HAS_OVERFLOW : integer; attribute C_HAS_OVERFLOW of input_fifo_fifo_generator_v13_1_3 : entity is 0; attribute C_HAS_PROG_FLAGS_AXIS : integer; attribute C_HAS_PROG_FLAGS_AXIS of input_fifo_fifo_generator_v13_1_3 : entity is 0; attribute C_HAS_PROG_FLAGS_RACH : integer; attribute C_HAS_PROG_FLAGS_RACH of input_fifo_fifo_generator_v13_1_3 : entity is 0; attribute C_HAS_PROG_FLAGS_RDCH : integer; attribute C_HAS_PROG_FLAGS_RDCH of input_fifo_fifo_generator_v13_1_3 : entity is 0; attribute C_HAS_PROG_FLAGS_WACH : integer; attribute C_HAS_PROG_FLAGS_WACH of input_fifo_fifo_generator_v13_1_3 : entity is 0; attribute C_HAS_PROG_FLAGS_WDCH : integer; attribute C_HAS_PROG_FLAGS_WDCH of input_fifo_fifo_generator_v13_1_3 : entity is 0; attribute C_HAS_PROG_FLAGS_WRCH : integer; attribute C_HAS_PROG_FLAGS_WRCH of input_fifo_fifo_generator_v13_1_3 : entity is 0; attribute C_HAS_RD_DATA_COUNT : integer; attribute C_HAS_RD_DATA_COUNT of input_fifo_fifo_generator_v13_1_3 : entity is 0; attribute C_HAS_RD_RST : integer; attribute C_HAS_RD_RST of input_fifo_fifo_generator_v13_1_3 : entity is 0; attribute C_HAS_RST : integer; attribute C_HAS_RST of input_fifo_fifo_generator_v13_1_3 : entity is 0; attribute C_HAS_SLAVE_CE : integer; attribute C_HAS_SLAVE_CE of input_fifo_fifo_generator_v13_1_3 : entity is 0; attribute C_HAS_SRST : integer; attribute C_HAS_SRST of input_fifo_fifo_generator_v13_1_3 : entity is 1; attribute C_HAS_UNDERFLOW : integer; attribute C_HAS_UNDERFLOW of input_fifo_fifo_generator_v13_1_3 : entity is 0; attribute C_HAS_VALID : integer; attribute C_HAS_VALID of input_fifo_fifo_generator_v13_1_3 : entity is 0; attribute C_HAS_WR_ACK : integer; attribute C_HAS_WR_ACK of input_fifo_fifo_generator_v13_1_3 : entity is 0; attribute C_HAS_WR_DATA_COUNT : integer; attribute C_HAS_WR_DATA_COUNT of input_fifo_fifo_generator_v13_1_3 : entity is 0; attribute C_HAS_WR_RST : integer; attribute C_HAS_WR_RST of input_fifo_fifo_generator_v13_1_3 : entity is 0; attribute C_IMPLEMENTATION_TYPE : integer; attribute C_IMPLEMENTATION_TYPE of input_fifo_fifo_generator_v13_1_3 : entity is 0; attribute C_IMPLEMENTATION_TYPE_AXIS : integer; attribute C_IMPLEMENTATION_TYPE_AXIS of input_fifo_fifo_generator_v13_1_3 : entity is 1; attribute C_IMPLEMENTATION_TYPE_RACH : integer; attribute C_IMPLEMENTATION_TYPE_RACH of input_fifo_fifo_generator_v13_1_3 : entity is 1; attribute C_IMPLEMENTATION_TYPE_RDCH : integer; attribute C_IMPLEMENTATION_TYPE_RDCH of input_fifo_fifo_generator_v13_1_3 : entity is 1; attribute C_IMPLEMENTATION_TYPE_WACH : integer; attribute C_IMPLEMENTATION_TYPE_WACH of input_fifo_fifo_generator_v13_1_3 : entity is 1; attribute C_IMPLEMENTATION_TYPE_WDCH : integer; attribute C_IMPLEMENTATION_TYPE_WDCH of input_fifo_fifo_generator_v13_1_3 : entity is 1; attribute C_IMPLEMENTATION_TYPE_WRCH : integer; attribute C_IMPLEMENTATION_TYPE_WRCH of input_fifo_fifo_generator_v13_1_3 : entity is 1; attribute C_INIT_WR_PNTR_VAL : integer; attribute C_INIT_WR_PNTR_VAL of input_fifo_fifo_generator_v13_1_3 : entity is 0; attribute C_INTERFACE_TYPE : integer; attribute C_INTERFACE_TYPE of input_fifo_fifo_generator_v13_1_3 : entity is 0; attribute C_MEMORY_TYPE : integer; attribute C_MEMORY_TYPE of input_fifo_fifo_generator_v13_1_3 : entity is 1; attribute C_MIF_FILE_NAME : string; attribute C_MIF_FILE_NAME of input_fifo_fifo_generator_v13_1_3 : entity is "BlankString"; attribute C_MSGON_VAL : integer; attribute C_MSGON_VAL of input_fifo_fifo_generator_v13_1_3 : entity is 1; attribute C_OPTIMIZATION_MODE : integer; attribute C_OPTIMIZATION_MODE of input_fifo_fifo_generator_v13_1_3 : entity is 0; attribute C_OVERFLOW_LOW : integer; attribute C_OVERFLOW_LOW of input_fifo_fifo_generator_v13_1_3 : entity is 0; attribute C_POWER_SAVING_MODE : integer; attribute C_POWER_SAVING_MODE of input_fifo_fifo_generator_v13_1_3 : entity is 0; attribute C_PRELOAD_LATENCY : integer; attribute C_PRELOAD_LATENCY of input_fifo_fifo_generator_v13_1_3 : entity is 0; attribute C_PRELOAD_REGS : integer; attribute C_PRELOAD_REGS of input_fifo_fifo_generator_v13_1_3 : entity is 1; attribute C_PRIM_FIFO_TYPE : string; attribute C_PRIM_FIFO_TYPE of input_fifo_fifo_generator_v13_1_3 : entity is "1kx18"; attribute C_PRIM_FIFO_TYPE_AXIS : string; attribute C_PRIM_FIFO_TYPE_AXIS of input_fifo_fifo_generator_v13_1_3 : entity is "1kx18"; attribute C_PRIM_FIFO_TYPE_RACH : string; attribute C_PRIM_FIFO_TYPE_RACH of input_fifo_fifo_generator_v13_1_3 : entity is "512x36"; attribute C_PRIM_FIFO_TYPE_RDCH : string; attribute C_PRIM_FIFO_TYPE_RDCH of input_fifo_fifo_generator_v13_1_3 : entity is "1kx36"; attribute C_PRIM_FIFO_TYPE_WACH : string; attribute C_PRIM_FIFO_TYPE_WACH of input_fifo_fifo_generator_v13_1_3 : entity is "512x36"; attribute C_PRIM_FIFO_TYPE_WDCH : string; attribute C_PRIM_FIFO_TYPE_WDCH of input_fifo_fifo_generator_v13_1_3 : entity is "1kx36"; attribute C_PRIM_FIFO_TYPE_WRCH : string; attribute C_PRIM_FIFO_TYPE_WRCH of input_fifo_fifo_generator_v13_1_3 : entity is "512x36"; attribute C_PROG_EMPTY_THRESH_ASSERT_VAL : integer; attribute C_PROG_EMPTY_THRESH_ASSERT_VAL of input_fifo_fifo_generator_v13_1_3 : entity is 4; attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS : integer; attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS of input_fifo_fifo_generator_v13_1_3 : entity is 1022; attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH : integer; attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH of input_fifo_fifo_generator_v13_1_3 : entity is 1022; attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH : integer; attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH of input_fifo_fifo_generator_v13_1_3 : entity is 1022; attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH : integer; attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH of input_fifo_fifo_generator_v13_1_3 : entity is 1022; attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH : integer; attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH of input_fifo_fifo_generator_v13_1_3 : entity is 1022; attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH : integer; attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH of input_fifo_fifo_generator_v13_1_3 : entity is 1022; attribute C_PROG_EMPTY_THRESH_NEGATE_VAL : integer; attribute C_PROG_EMPTY_THRESH_NEGATE_VAL of input_fifo_fifo_generator_v13_1_3 : entity is 5; attribute C_PROG_EMPTY_TYPE : integer; attribute C_PROG_EMPTY_TYPE of input_fifo_fifo_generator_v13_1_3 : entity is 0; attribute C_PROG_EMPTY_TYPE_AXIS : integer; attribute C_PROG_EMPTY_TYPE_AXIS of input_fifo_fifo_generator_v13_1_3 : entity is 0; attribute C_PROG_EMPTY_TYPE_RACH : integer; attribute C_PROG_EMPTY_TYPE_RACH of input_fifo_fifo_generator_v13_1_3 : entity is 0; attribute C_PROG_EMPTY_TYPE_RDCH : integer; attribute C_PROG_EMPTY_TYPE_RDCH of input_fifo_fifo_generator_v13_1_3 : entity is 0; attribute C_PROG_EMPTY_TYPE_WACH : integer; attribute C_PROG_EMPTY_TYPE_WACH of input_fifo_fifo_generator_v13_1_3 : entity is 0; attribute C_PROG_EMPTY_TYPE_WDCH : integer; attribute C_PROG_EMPTY_TYPE_WDCH of input_fifo_fifo_generator_v13_1_3 : entity is 0; attribute C_PROG_EMPTY_TYPE_WRCH : integer; attribute C_PROG_EMPTY_TYPE_WRCH of input_fifo_fifo_generator_v13_1_3 : entity is 0; attribute C_PROG_FULL_THRESH_ASSERT_VAL : integer; attribute C_PROG_FULL_THRESH_ASSERT_VAL of input_fifo_fifo_generator_v13_1_3 : entity is 1023; attribute C_PROG_FULL_THRESH_ASSERT_VAL_AXIS : integer; attribute C_PROG_FULL_THRESH_ASSERT_VAL_AXIS of input_fifo_fifo_generator_v13_1_3 : entity is 1023; attribute C_PROG_FULL_THRESH_ASSERT_VAL_RACH : integer; attribute C_PROG_FULL_THRESH_ASSERT_VAL_RACH of input_fifo_fifo_generator_v13_1_3 : entity is 1023; attribute C_PROG_FULL_THRESH_ASSERT_VAL_RDCH : integer; attribute C_PROG_FULL_THRESH_ASSERT_VAL_RDCH of input_fifo_fifo_generator_v13_1_3 : entity is 1023; attribute C_PROG_FULL_THRESH_ASSERT_VAL_WACH : integer; attribute C_PROG_FULL_THRESH_ASSERT_VAL_WACH of input_fifo_fifo_generator_v13_1_3 : entity is 1023; attribute C_PROG_FULL_THRESH_ASSERT_VAL_WDCH : integer; attribute C_PROG_FULL_THRESH_ASSERT_VAL_WDCH of input_fifo_fifo_generator_v13_1_3 : entity is 1023; attribute C_PROG_FULL_THRESH_ASSERT_VAL_WRCH : integer; attribute C_PROG_FULL_THRESH_ASSERT_VAL_WRCH of input_fifo_fifo_generator_v13_1_3 : entity is 1023; attribute C_PROG_FULL_THRESH_NEGATE_VAL : integer; attribute C_PROG_FULL_THRESH_NEGATE_VAL of input_fifo_fifo_generator_v13_1_3 : entity is 1022; attribute C_PROG_FULL_TYPE : integer; attribute C_PROG_FULL_TYPE of input_fifo_fifo_generator_v13_1_3 : entity is 0; attribute C_PROG_FULL_TYPE_AXIS : integer; attribute C_PROG_FULL_TYPE_AXIS of input_fifo_fifo_generator_v13_1_3 : entity is 0; attribute C_PROG_FULL_TYPE_RACH : integer; attribute C_PROG_FULL_TYPE_RACH of input_fifo_fifo_generator_v13_1_3 : entity is 0; attribute C_PROG_FULL_TYPE_RDCH : integer; attribute C_PROG_FULL_TYPE_RDCH of input_fifo_fifo_generator_v13_1_3 : entity is 0; attribute C_PROG_FULL_TYPE_WACH : integer; attribute C_PROG_FULL_TYPE_WACH of input_fifo_fifo_generator_v13_1_3 : entity is 0; attribute C_PROG_FULL_TYPE_WDCH : integer; attribute C_PROG_FULL_TYPE_WDCH of input_fifo_fifo_generator_v13_1_3 : entity is 0; attribute C_PROG_FULL_TYPE_WRCH : integer; attribute C_PROG_FULL_TYPE_WRCH of input_fifo_fifo_generator_v13_1_3 : entity is 0; attribute C_RACH_TYPE : integer; attribute C_RACH_TYPE of input_fifo_fifo_generator_v13_1_3 : entity is 0; attribute C_RDCH_TYPE : integer; attribute C_RDCH_TYPE of input_fifo_fifo_generator_v13_1_3 : entity is 0; attribute C_RD_DATA_COUNT_WIDTH : integer; attribute C_RD_DATA_COUNT_WIDTH of input_fifo_fifo_generator_v13_1_3 : entity is 11; attribute C_RD_DEPTH : integer; attribute C_RD_DEPTH of input_fifo_fifo_generator_v13_1_3 : entity is 1024; attribute C_RD_FREQ : integer; attribute C_RD_FREQ of input_fifo_fifo_generator_v13_1_3 : entity is 1; attribute C_RD_PNTR_WIDTH : integer; attribute C_RD_PNTR_WIDTH of input_fifo_fifo_generator_v13_1_3 : entity is 10; attribute C_REG_SLICE_MODE_AXIS : integer; attribute C_REG_SLICE_MODE_AXIS of input_fifo_fifo_generator_v13_1_3 : entity is 0; attribute C_REG_SLICE_MODE_RACH : integer; attribute C_REG_SLICE_MODE_RACH of input_fifo_fifo_generator_v13_1_3 : entity is 0; attribute C_REG_SLICE_MODE_RDCH : integer; attribute C_REG_SLICE_MODE_RDCH of input_fifo_fifo_generator_v13_1_3 : entity is 0; attribute C_REG_SLICE_MODE_WACH : integer; attribute C_REG_SLICE_MODE_WACH of input_fifo_fifo_generator_v13_1_3 : entity is 0; attribute C_REG_SLICE_MODE_WDCH : integer; attribute C_REG_SLICE_MODE_WDCH of input_fifo_fifo_generator_v13_1_3 : entity is 0; attribute C_REG_SLICE_MODE_WRCH : integer; attribute C_REG_SLICE_MODE_WRCH of input_fifo_fifo_generator_v13_1_3 : entity is 0; attribute C_SELECT_XPM : integer; attribute C_SELECT_XPM of input_fifo_fifo_generator_v13_1_3 : entity is 0; attribute C_SYNCHRONIZER_STAGE : integer; attribute C_SYNCHRONIZER_STAGE of input_fifo_fifo_generator_v13_1_3 : entity is 2; attribute C_UNDERFLOW_LOW : integer; attribute C_UNDERFLOW_LOW of input_fifo_fifo_generator_v13_1_3 : entity is 0; attribute C_USE_COMMON_OVERFLOW : integer; attribute C_USE_COMMON_OVERFLOW of input_fifo_fifo_generator_v13_1_3 : entity is 0; attribute C_USE_COMMON_UNDERFLOW : integer; attribute C_USE_COMMON_UNDERFLOW of input_fifo_fifo_generator_v13_1_3 : entity is 0; attribute C_USE_DEFAULT_SETTINGS : integer; attribute C_USE_DEFAULT_SETTINGS of input_fifo_fifo_generator_v13_1_3 : entity is 0; attribute C_USE_DOUT_RST : integer; attribute C_USE_DOUT_RST of input_fifo_fifo_generator_v13_1_3 : entity is 1; attribute C_USE_ECC : integer; attribute C_USE_ECC of input_fifo_fifo_generator_v13_1_3 : entity is 0; attribute C_USE_ECC_AXIS : integer; attribute C_USE_ECC_AXIS of input_fifo_fifo_generator_v13_1_3 : entity is 0; attribute C_USE_ECC_RACH : integer; attribute C_USE_ECC_RACH of input_fifo_fifo_generator_v13_1_3 : entity is 0; attribute C_USE_ECC_RDCH : integer; attribute C_USE_ECC_RDCH of input_fifo_fifo_generator_v13_1_3 : entity is 0; attribute C_USE_ECC_WACH : integer; attribute C_USE_ECC_WACH of input_fifo_fifo_generator_v13_1_3 : entity is 0; attribute C_USE_ECC_WDCH : integer; attribute C_USE_ECC_WDCH of input_fifo_fifo_generator_v13_1_3 : entity is 0; attribute C_USE_ECC_WRCH : integer; attribute C_USE_ECC_WRCH of input_fifo_fifo_generator_v13_1_3 : entity is 0; attribute C_USE_EMBEDDED_REG : integer; attribute C_USE_EMBEDDED_REG of input_fifo_fifo_generator_v13_1_3 : entity is 0; attribute C_USE_FIFO16_FLAGS : integer; attribute C_USE_FIFO16_FLAGS of input_fifo_fifo_generator_v13_1_3 : entity is 0; attribute C_USE_FWFT_DATA_COUNT : integer; attribute C_USE_FWFT_DATA_COUNT of input_fifo_fifo_generator_v13_1_3 : entity is 1; attribute C_USE_PIPELINE_REG : integer; attribute C_USE_PIPELINE_REG of input_fifo_fifo_generator_v13_1_3 : entity is 0; attribute C_VALID_LOW : integer; attribute C_VALID_LOW of input_fifo_fifo_generator_v13_1_3 : entity is 0; attribute C_WACH_TYPE : integer; attribute C_WACH_TYPE of input_fifo_fifo_generator_v13_1_3 : entity is 0; attribute C_WDCH_TYPE : integer; attribute C_WDCH_TYPE of input_fifo_fifo_generator_v13_1_3 : entity is 0; attribute C_WRCH_TYPE : integer; attribute C_WRCH_TYPE of input_fifo_fifo_generator_v13_1_3 : entity is 0; attribute C_WR_ACK_LOW : integer; attribute C_WR_ACK_LOW of input_fifo_fifo_generator_v13_1_3 : entity is 0; attribute C_WR_DATA_COUNT_WIDTH : integer; attribute C_WR_DATA_COUNT_WIDTH of input_fifo_fifo_generator_v13_1_3 : entity is 11; attribute C_WR_DEPTH : integer; attribute C_WR_DEPTH of input_fifo_fifo_generator_v13_1_3 : entity is 1024; attribute C_WR_DEPTH_AXIS : integer; attribute C_WR_DEPTH_AXIS of input_fifo_fifo_generator_v13_1_3 : entity is 1024; attribute C_WR_DEPTH_RACH : integer; attribute C_WR_DEPTH_RACH of input_fifo_fifo_generator_v13_1_3 : entity is 16; attribute C_WR_DEPTH_RDCH : integer; attribute C_WR_DEPTH_RDCH of input_fifo_fifo_generator_v13_1_3 : entity is 1024; attribute C_WR_DEPTH_WACH : integer; attribute C_WR_DEPTH_WACH of input_fifo_fifo_generator_v13_1_3 : entity is 16; attribute C_WR_DEPTH_WDCH : integer; attribute C_WR_DEPTH_WDCH of input_fifo_fifo_generator_v13_1_3 : entity is 1024; attribute C_WR_DEPTH_WRCH : integer; attribute C_WR_DEPTH_WRCH of input_fifo_fifo_generator_v13_1_3 : entity is 16; attribute C_WR_FREQ : integer; attribute C_WR_FREQ of input_fifo_fifo_generator_v13_1_3 : entity is 1; attribute C_WR_PNTR_WIDTH : integer; attribute C_WR_PNTR_WIDTH of input_fifo_fifo_generator_v13_1_3 : entity is 10; attribute C_WR_PNTR_WIDTH_AXIS : integer; attribute C_WR_PNTR_WIDTH_AXIS of input_fifo_fifo_generator_v13_1_3 : entity is 10; attribute C_WR_PNTR_WIDTH_RACH : integer; attribute C_WR_PNTR_WIDTH_RACH of input_fifo_fifo_generator_v13_1_3 : entity is 4; attribute C_WR_PNTR_WIDTH_RDCH : integer; attribute C_WR_PNTR_WIDTH_RDCH of input_fifo_fifo_generator_v13_1_3 : entity is 10; attribute C_WR_PNTR_WIDTH_WACH : integer; attribute C_WR_PNTR_WIDTH_WACH of input_fifo_fifo_generator_v13_1_3 : entity is 4; attribute C_WR_PNTR_WIDTH_WDCH : integer; attribute C_WR_PNTR_WIDTH_WDCH of input_fifo_fifo_generator_v13_1_3 : entity is 10; attribute C_WR_PNTR_WIDTH_WRCH : integer; attribute C_WR_PNTR_WIDTH_WRCH of input_fifo_fifo_generator_v13_1_3 : entity is 4; attribute C_WR_RESPONSE_LATENCY : integer; attribute C_WR_RESPONSE_LATENCY of input_fifo_fifo_generator_v13_1_3 : entity is 1; attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of input_fifo_fifo_generator_v13_1_3 : entity is "fifo_generator_v13_1_3"; end input_fifo_fifo_generator_v13_1_3; architecture STRUCTURE of input_fifo_fifo_generator_v13_1_3 is signal \<const0>\ : STD_LOGIC; signal \<const1>\ : STD_LOGIC; begin almost_empty <= \<const0>\; almost_full <= \<const0>\; axi_ar_data_count(4) <= \<const0>\; axi_ar_data_count(3) <= \<const0>\; axi_ar_data_count(2) <= \<const0>\; axi_ar_data_count(1) <= \<const0>\; axi_ar_data_count(0) <= \<const0>\; axi_ar_dbiterr <= \<const0>\; axi_ar_overflow <= \<const0>\; axi_ar_prog_empty <= \<const1>\; axi_ar_prog_full <= \<const0>\; axi_ar_rd_data_count(4) <= \<const0>\; axi_ar_rd_data_count(3) <= \<const0>\; axi_ar_rd_data_count(2) <= \<const0>\; axi_ar_rd_data_count(1) <= \<const0>\; axi_ar_rd_data_count(0) <= \<const0>\; axi_ar_sbiterr <= \<const0>\; axi_ar_underflow <= \<const0>\; axi_ar_wr_data_count(4) <= \<const0>\; axi_ar_wr_data_count(3) <= \<const0>\; axi_ar_wr_data_count(2) <= \<const0>\; axi_ar_wr_data_count(1) <= \<const0>\; axi_ar_wr_data_count(0) <= \<const0>\; axi_aw_data_count(4) <= \<const0>\; axi_aw_data_count(3) <= \<const0>\; axi_aw_data_count(2) <= \<const0>\; axi_aw_data_count(1) <= \<const0>\; axi_aw_data_count(0) <= \<const0>\; axi_aw_dbiterr <= \<const0>\; axi_aw_overflow <= \<const0>\; axi_aw_prog_empty <= \<const1>\; axi_aw_prog_full <= \<const0>\; axi_aw_rd_data_count(4) <= \<const0>\; axi_aw_rd_data_count(3) <= \<const0>\; axi_aw_rd_data_count(2) <= \<const0>\; axi_aw_rd_data_count(1) <= \<const0>\; axi_aw_rd_data_count(0) <= \<const0>\; axi_aw_sbiterr <= \<const0>\; axi_aw_underflow <= \<const0>\; axi_aw_wr_data_count(4) <= \<const0>\; axi_aw_wr_data_count(3) <= \<const0>\; axi_aw_wr_data_count(2) <= \<const0>\; axi_aw_wr_data_count(1) <= \<const0>\; axi_aw_wr_data_count(0) <= \<const0>\; axi_b_data_count(4) <= \<const0>\; axi_b_data_count(3) <= \<const0>\; axi_b_data_count(2) <= \<const0>\; axi_b_data_count(1) <= \<const0>\; axi_b_data_count(0) <= \<const0>\; axi_b_dbiterr <= \<const0>\; axi_b_overflow <= \<const0>\; axi_b_prog_empty <= \<const1>\; axi_b_prog_full <= \<const0>\; axi_b_rd_data_count(4) <= \<const0>\; axi_b_rd_data_count(3) <= \<const0>\; axi_b_rd_data_count(2) <= \<const0>\; axi_b_rd_data_count(1) <= \<const0>\; axi_b_rd_data_count(0) <= \<const0>\; axi_b_sbiterr <= \<const0>\; axi_b_underflow <= \<const0>\; axi_b_wr_data_count(4) <= \<const0>\; axi_b_wr_data_count(3) <= \<const0>\; axi_b_wr_data_count(2) <= \<const0>\; axi_b_wr_data_count(1) <= \<const0>\; axi_b_wr_data_count(0) <= \<const0>\; axi_r_data_count(10) <= \<const0>\; axi_r_data_count(9) <= \<const0>\; axi_r_data_count(8) <= \<const0>\; axi_r_data_count(7) <= \<const0>\; axi_r_data_count(6) <= \<const0>\; axi_r_data_count(5) <= \<const0>\; axi_r_data_count(4) <= \<const0>\; axi_r_data_count(3) <= \<const0>\; axi_r_data_count(2) <= \<const0>\; axi_r_data_count(1) <= \<const0>\; axi_r_data_count(0) <= \<const0>\; axi_r_dbiterr <= \<const0>\; axi_r_overflow <= \<const0>\; axi_r_prog_empty <= \<const1>\; axi_r_prog_full <= \<const0>\; axi_r_rd_data_count(10) <= \<const0>\; axi_r_rd_data_count(9) <= \<const0>\; axi_r_rd_data_count(8) <= \<const0>\; axi_r_rd_data_count(7) <= \<const0>\; axi_r_rd_data_count(6) <= \<const0>\; axi_r_rd_data_count(5) <= \<const0>\; axi_r_rd_data_count(4) <= \<const0>\; axi_r_rd_data_count(3) <= \<const0>\; axi_r_rd_data_count(2) <= \<const0>\; axi_r_rd_data_count(1) <= \<const0>\; axi_r_rd_data_count(0) <= \<const0>\; axi_r_sbiterr <= \<const0>\; axi_r_underflow <= \<const0>\; axi_r_wr_data_count(10) <= \<const0>\; axi_r_wr_data_count(9) <= \<const0>\; axi_r_wr_data_count(8) <= \<const0>\; axi_r_wr_data_count(7) <= \<const0>\; axi_r_wr_data_count(6) <= \<const0>\; axi_r_wr_data_count(5) <= \<const0>\; axi_r_wr_data_count(4) <= \<const0>\; axi_r_wr_data_count(3) <= \<const0>\; axi_r_wr_data_count(2) <= \<const0>\; axi_r_wr_data_count(1) <= \<const0>\; axi_r_wr_data_count(0) <= \<const0>\; axi_w_data_count(10) <= \<const0>\; axi_w_data_count(9) <= \<const0>\; axi_w_data_count(8) <= \<const0>\; axi_w_data_count(7) <= \<const0>\; axi_w_data_count(6) <= \<const0>\; axi_w_data_count(5) <= \<const0>\; axi_w_data_count(4) <= \<const0>\; axi_w_data_count(3) <= \<const0>\; axi_w_data_count(2) <= \<const0>\; axi_w_data_count(1) <= \<const0>\; axi_w_data_count(0) <= \<const0>\; axi_w_dbiterr <= \<const0>\; axi_w_overflow <= \<const0>\; axi_w_prog_empty <= \<const1>\; axi_w_prog_full <= \<const0>\; axi_w_rd_data_count(10) <= \<const0>\; axi_w_rd_data_count(9) <= \<const0>\; axi_w_rd_data_count(8) <= \<const0>\; axi_w_rd_data_count(7) <= \<const0>\; axi_w_rd_data_count(6) <= \<const0>\; axi_w_rd_data_count(5) <= \<const0>\; axi_w_rd_data_count(4) <= \<const0>\; axi_w_rd_data_count(3) <= \<const0>\; axi_w_rd_data_count(2) <= \<const0>\; axi_w_rd_data_count(1) <= \<const0>\; axi_w_rd_data_count(0) <= \<const0>\; axi_w_sbiterr <= \<const0>\; axi_w_underflow <= \<const0>\; axi_w_wr_data_count(10) <= \<const0>\; axi_w_wr_data_count(9) <= \<const0>\; axi_w_wr_data_count(8) <= \<const0>\; axi_w_wr_data_count(7) <= \<const0>\; axi_w_wr_data_count(6) <= \<const0>\; axi_w_wr_data_count(5) <= \<const0>\; axi_w_wr_data_count(4) <= \<const0>\; axi_w_wr_data_count(3) <= \<const0>\; axi_w_wr_data_count(2) <= \<const0>\; axi_w_wr_data_count(1) <= \<const0>\; axi_w_wr_data_count(0) <= \<const0>\; axis_data_count(10) <= \<const0>\; axis_data_count(9) <= \<const0>\; axis_data_count(8) <= \<const0>\; axis_data_count(7) <= \<const0>\; axis_data_count(6) <= \<const0>\; axis_data_count(5) <= \<const0>\; axis_data_count(4) <= \<const0>\; axis_data_count(3) <= \<const0>\; axis_data_count(2) <= \<const0>\; axis_data_count(1) <= \<const0>\; axis_data_count(0) <= \<const0>\; axis_dbiterr <= \<const0>\; axis_overflow <= \<const0>\; axis_prog_empty <= \<const1>\; axis_prog_full <= \<const0>\; axis_rd_data_count(10) <= \<const0>\; axis_rd_data_count(9) <= \<const0>\; axis_rd_data_count(8) <= \<const0>\; axis_rd_data_count(7) <= \<const0>\; axis_rd_data_count(6) <= \<const0>\; axis_rd_data_count(5) <= \<const0>\; axis_rd_data_count(4) <= \<const0>\; axis_rd_data_count(3) <= \<const0>\; axis_rd_data_count(2) <= \<const0>\; axis_rd_data_count(1) <= \<const0>\; axis_rd_data_count(0) <= \<const0>\; axis_sbiterr <= \<const0>\; axis_underflow <= \<const0>\; axis_wr_data_count(10) <= \<const0>\; axis_wr_data_count(9) <= \<const0>\; axis_wr_data_count(8) <= \<const0>\; axis_wr_data_count(7) <= \<const0>\; axis_wr_data_count(6) <= \<const0>\; axis_wr_data_count(5) <= \<const0>\; axis_wr_data_count(4) <= \<const0>\; axis_wr_data_count(3) <= \<const0>\; axis_wr_data_count(2) <= \<const0>\; axis_wr_data_count(1) <= \<const0>\; axis_wr_data_count(0) <= \<const0>\; data_count(10) <= \<const0>\; data_count(9) <= \<const0>\; data_count(8) <= \<const0>\; data_count(7) <= \<const0>\; data_count(6) <= \<const0>\; data_count(5) <= \<const0>\; data_count(4) <= \<const0>\; data_count(3) <= \<const0>\; data_count(2) <= \<const0>\; data_count(1) <= \<const0>\; data_count(0) <= \<const0>\; dbiterr <= \<const0>\; m_axi_araddr(31) <= \<const0>\; m_axi_araddr(30) <= \<const0>\; m_axi_araddr(29) <= \<const0>\; m_axi_araddr(28) <= \<const0>\; m_axi_araddr(27) <= \<const0>\; m_axi_araddr(26) <= \<const0>\; m_axi_araddr(25) <= \<const0>\; m_axi_araddr(24) <= \<const0>\; m_axi_araddr(23) <= \<const0>\; m_axi_araddr(22) <= \<const0>\; m_axi_araddr(21) <= \<const0>\; m_axi_araddr(20) <= \<const0>\; m_axi_araddr(19) <= \<const0>\; m_axi_araddr(18) <= \<const0>\; m_axi_araddr(17) <= \<const0>\; m_axi_araddr(16) <= \<const0>\; m_axi_araddr(15) <= \<const0>\; m_axi_araddr(14) <= \<const0>\; m_axi_araddr(13) <= \<const0>\; m_axi_araddr(12) <= \<const0>\; m_axi_araddr(11) <= \<const0>\; m_axi_araddr(10) <= \<const0>\; m_axi_araddr(9) <= \<const0>\; m_axi_araddr(8) <= \<const0>\; m_axi_araddr(7) <= \<const0>\; m_axi_araddr(6) <= \<const0>\; m_axi_araddr(5) <= \<const0>\; m_axi_araddr(4) <= \<const0>\; m_axi_araddr(3) <= \<const0>\; m_axi_araddr(2) <= \<const0>\; m_axi_araddr(1) <= \<const0>\; m_axi_araddr(0) <= \<const0>\; m_axi_arburst(1) <= \<const0>\; m_axi_arburst(0) <= \<const0>\; m_axi_arcache(3) <= \<const0>\; m_axi_arcache(2) <= \<const0>\; m_axi_arcache(1) <= \<const0>\; m_axi_arcache(0) <= \<const0>\; m_axi_arid(0) <= \<const0>\; m_axi_arlen(7) <= \<const0>\; m_axi_arlen(6) <= \<const0>\; m_axi_arlen(5) <= \<const0>\; m_axi_arlen(4) <= \<const0>\; m_axi_arlen(3) <= \<const0>\; m_axi_arlen(2) <= \<const0>\; m_axi_arlen(1) <= \<const0>\; m_axi_arlen(0) <= \<const0>\; m_axi_arlock(0) <= \<const0>\; m_axi_arprot(2) <= \<const0>\; m_axi_arprot(1) <= \<const0>\; m_axi_arprot(0) <= \<const0>\; m_axi_arqos(3) <= \<const0>\; m_axi_arqos(2) <= \<const0>\; m_axi_arqos(1) <= \<const0>\; m_axi_arqos(0) <= \<const0>\; m_axi_arregion(3) <= \<const0>\; m_axi_arregion(2) <= \<const0>\; m_axi_arregion(1) <= \<const0>\; m_axi_arregion(0) <= \<const0>\; m_axi_arsize(2) <= \<const0>\; m_axi_arsize(1) <= \<const0>\; m_axi_arsize(0) <= \<const0>\; m_axi_aruser(0) <= \<const0>\; m_axi_arvalid <= \<const0>\; m_axi_awaddr(31) <= \<const0>\; m_axi_awaddr(30) <= \<const0>\; m_axi_awaddr(29) <= \<const0>\; m_axi_awaddr(28) <= \<const0>\; m_axi_awaddr(27) <= \<const0>\; m_axi_awaddr(26) <= \<const0>\; m_axi_awaddr(25) <= \<const0>\; m_axi_awaddr(24) <= \<const0>\; m_axi_awaddr(23) <= \<const0>\; m_axi_awaddr(22) <= \<const0>\; m_axi_awaddr(21) <= \<const0>\; m_axi_awaddr(20) <= \<const0>\; m_axi_awaddr(19) <= \<const0>\; m_axi_awaddr(18) <= \<const0>\; m_axi_awaddr(17) <= \<const0>\; m_axi_awaddr(16) <= \<const0>\; m_axi_awaddr(15) <= \<const0>\; m_axi_awaddr(14) <= \<const0>\; m_axi_awaddr(13) <= \<const0>\; m_axi_awaddr(12) <= \<const0>\; m_axi_awaddr(11) <= \<const0>\; m_axi_awaddr(10) <= \<const0>\; m_axi_awaddr(9) <= \<const0>\; m_axi_awaddr(8) <= \<const0>\; m_axi_awaddr(7) <= \<const0>\; m_axi_awaddr(6) <= \<const0>\; m_axi_awaddr(5) <= \<const0>\; m_axi_awaddr(4) <= \<const0>\; m_axi_awaddr(3) <= \<const0>\; m_axi_awaddr(2) <= \<const0>\; m_axi_awaddr(1) <= \<const0>\; m_axi_awaddr(0) <= \<const0>\; m_axi_awburst(1) <= \<const0>\; m_axi_awburst(0) <= \<const0>\; m_axi_awcache(3) <= \<const0>\; m_axi_awcache(2) <= \<const0>\; m_axi_awcache(1) <= \<const0>\; m_axi_awcache(0) <= \<const0>\; m_axi_awid(0) <= \<const0>\; m_axi_awlen(7) <= \<const0>\; m_axi_awlen(6) <= \<const0>\; m_axi_awlen(5) <= \<const0>\; m_axi_awlen(4) <= \<const0>\; m_axi_awlen(3) <= \<const0>\; m_axi_awlen(2) <= \<const0>\; m_axi_awlen(1) <= \<const0>\; m_axi_awlen(0) <= \<const0>\; m_axi_awlock(0) <= \<const0>\; m_axi_awprot(2) <= \<const0>\; m_axi_awprot(1) <= \<const0>\; m_axi_awprot(0) <= \<const0>\; m_axi_awqos(3) <= \<const0>\; m_axi_awqos(2) <= \<const0>\; m_axi_awqos(1) <= \<const0>\; m_axi_awqos(0) <= \<const0>\; m_axi_awregion(3) <= \<const0>\; m_axi_awregion(2) <= \<const0>\; m_axi_awregion(1) <= \<const0>\; m_axi_awregion(0) <= \<const0>\; m_axi_awsize(2) <= \<const0>\; m_axi_awsize(1) <= \<const0>\; m_axi_awsize(0) <= \<const0>\; m_axi_awuser(0) <= \<const0>\; m_axi_awvalid <= \<const0>\; m_axi_bready <= \<const0>\; m_axi_rready <= \<const0>\; m_axi_wdata(63) <= \<const0>\; m_axi_wdata(62) <= \<const0>\; m_axi_wdata(61) <= \<const0>\; m_axi_wdata(60) <= \<const0>\; m_axi_wdata(59) <= \<const0>\; m_axi_wdata(58) <= \<const0>\; m_axi_wdata(57) <= \<const0>\; m_axi_wdata(56) <= \<const0>\; m_axi_wdata(55) <= \<const0>\; m_axi_wdata(54) <= \<const0>\; m_axi_wdata(53) <= \<const0>\; m_axi_wdata(52) <= \<const0>\; m_axi_wdata(51) <= \<const0>\; m_axi_wdata(50) <= \<const0>\; m_axi_wdata(49) <= \<const0>\; m_axi_wdata(48) <= \<const0>\; m_axi_wdata(47) <= \<const0>\; m_axi_wdata(46) <= \<const0>\; m_axi_wdata(45) <= \<const0>\; m_axi_wdata(44) <= \<const0>\; m_axi_wdata(43) <= \<const0>\; m_axi_wdata(42) <= \<const0>\; m_axi_wdata(41) <= \<const0>\; m_axi_wdata(40) <= \<const0>\; m_axi_wdata(39) <= \<const0>\; m_axi_wdata(38) <= \<const0>\; m_axi_wdata(37) <= \<const0>\; m_axi_wdata(36) <= \<const0>\; m_axi_wdata(35) <= \<const0>\; m_axi_wdata(34) <= \<const0>\; m_axi_wdata(33) <= \<const0>\; m_axi_wdata(32) <= \<const0>\; m_axi_wdata(31) <= \<const0>\; m_axi_wdata(30) <= \<const0>\; m_axi_wdata(29) <= \<const0>\; m_axi_wdata(28) <= \<const0>\; m_axi_wdata(27) <= \<const0>\; m_axi_wdata(26) <= \<const0>\; m_axi_wdata(25) <= \<const0>\; m_axi_wdata(24) <= \<const0>\; m_axi_wdata(23) <= \<const0>\; m_axi_wdata(22) <= \<const0>\; m_axi_wdata(21) <= \<const0>\; m_axi_wdata(20) <= \<const0>\; m_axi_wdata(19) <= \<const0>\; m_axi_wdata(18) <= \<const0>\; m_axi_wdata(17) <= \<const0>\; m_axi_wdata(16) <= \<const0>\; m_axi_wdata(15) <= \<const0>\; m_axi_wdata(14) <= \<const0>\; m_axi_wdata(13) <= \<const0>\; m_axi_wdata(12) <= \<const0>\; m_axi_wdata(11) <= \<const0>\; m_axi_wdata(10) <= \<const0>\; m_axi_wdata(9) <= \<const0>\; m_axi_wdata(8) <= \<const0>\; m_axi_wdata(7) <= \<const0>\; m_axi_wdata(6) <= \<const0>\; m_axi_wdata(5) <= \<const0>\; m_axi_wdata(4) <= \<const0>\; m_axi_wdata(3) <= \<const0>\; m_axi_wdata(2) <= \<const0>\; m_axi_wdata(1) <= \<const0>\; m_axi_wdata(0) <= \<const0>\; m_axi_wid(0) <= \<const0>\; m_axi_wlast <= \<const0>\; m_axi_wstrb(7) <= \<const0>\; m_axi_wstrb(6) <= \<const0>\; m_axi_wstrb(5) <= \<const0>\; m_axi_wstrb(4) <= \<const0>\; m_axi_wstrb(3) <= \<const0>\; m_axi_wstrb(2) <= \<const0>\; m_axi_wstrb(1) <= \<const0>\; m_axi_wstrb(0) <= \<const0>\; m_axi_wuser(0) <= \<const0>\; m_axi_wvalid <= \<const0>\; m_axis_tdata(7) <= \<const0>\; m_axis_tdata(6) <= \<const0>\; m_axis_tdata(5) <= \<const0>\; m_axis_tdata(4) <= \<const0>\; m_axis_tdata(3) <= \<const0>\; m_axis_tdata(2) <= \<const0>\; m_axis_tdata(1) <= \<const0>\; m_axis_tdata(0) <= \<const0>\; m_axis_tdest(0) <= \<const0>\; m_axis_tid(0) <= \<const0>\; m_axis_tkeep(0) <= \<const0>\; m_axis_tlast <= \<const0>\; m_axis_tstrb(0) <= \<const0>\; m_axis_tuser(3) <= \<const0>\; m_axis_tuser(2) <= \<const0>\; m_axis_tuser(1) <= \<const0>\; m_axis_tuser(0) <= \<const0>\; m_axis_tvalid <= \<const0>\; overflow <= \<const0>\; prog_empty <= \<const0>\; prog_full <= \<const0>\; rd_data_count(10) <= \<const0>\; rd_data_count(9) <= \<const0>\; rd_data_count(8) <= \<const0>\; rd_data_count(7) <= \<const0>\; rd_data_count(6) <= \<const0>\; rd_data_count(5) <= \<const0>\; rd_data_count(4) <= \<const0>\; rd_data_count(3) <= \<const0>\; rd_data_count(2) <= \<const0>\; rd_data_count(1) <= \<const0>\; rd_data_count(0) <= \<const0>\; rd_rst_busy <= \<const0>\; s_axi_arready <= \<const0>\; s_axi_awready <= \<const0>\; s_axi_bid(0) <= \<const0>\; s_axi_bresp(1) <= \<const0>\; s_axi_bresp(0) <= \<const0>\; s_axi_buser(0) <= \<const0>\; s_axi_bvalid <= \<const0>\; s_axi_rdata(63) <= \<const0>\; s_axi_rdata(62) <= \<const0>\; s_axi_rdata(61) <= \<const0>\; s_axi_rdata(60) <= \<const0>\; s_axi_rdata(59) <= \<const0>\; s_axi_rdata(58) <= \<const0>\; s_axi_rdata(57) <= \<const0>\; s_axi_rdata(56) <= \<const0>\; s_axi_rdata(55) <= \<const0>\; s_axi_rdata(54) <= \<const0>\; s_axi_rdata(53) <= \<const0>\; s_axi_rdata(52) <= \<const0>\; s_axi_rdata(51) <= \<const0>\; s_axi_rdata(50) <= \<const0>\; s_axi_rdata(49) <= \<const0>\; s_axi_rdata(48) <= \<const0>\; s_axi_rdata(47) <= \<const0>\; s_axi_rdata(46) <= \<const0>\; s_axi_rdata(45) <= \<const0>\; s_axi_rdata(44) <= \<const0>\; s_axi_rdata(43) <= \<const0>\; s_axi_rdata(42) <= \<const0>\; s_axi_rdata(41) <= \<const0>\; s_axi_rdata(40) <= \<const0>\; s_axi_rdata(39) <= \<const0>\; s_axi_rdata(38) <= \<const0>\; s_axi_rdata(37) <= \<const0>\; s_axi_rdata(36) <= \<const0>\; s_axi_rdata(35) <= \<const0>\; s_axi_rdata(34) <= \<const0>\; s_axi_rdata(33) <= \<const0>\; s_axi_rdata(32) <= \<const0>\; s_axi_rdata(31) <= \<const0>\; s_axi_rdata(30) <= \<const0>\; s_axi_rdata(29) <= \<const0>\; s_axi_rdata(28) <= \<const0>\; s_axi_rdata(27) <= \<const0>\; s_axi_rdata(26) <= \<const0>\; s_axi_rdata(25) <= \<const0>\; s_axi_rdata(24) <= \<const0>\; s_axi_rdata(23) <= \<const0>\; s_axi_rdata(22) <= \<const0>\; s_axi_rdata(21) <= \<const0>\; s_axi_rdata(20) <= \<const0>\; s_axi_rdata(19) <= \<const0>\; s_axi_rdata(18) <= \<const0>\; s_axi_rdata(17) <= \<const0>\; s_axi_rdata(16) <= \<const0>\; s_axi_rdata(15) <= \<const0>\; s_axi_rdata(14) <= \<const0>\; s_axi_rdata(13) <= \<const0>\; s_axi_rdata(12) <= \<const0>\; s_axi_rdata(11) <= \<const0>\; s_axi_rdata(10) <= \<const0>\; s_axi_rdata(9) <= \<const0>\; s_axi_rdata(8) <= \<const0>\; s_axi_rdata(7) <= \<const0>\; s_axi_rdata(6) <= \<const0>\; s_axi_rdata(5) <= \<const0>\; s_axi_rdata(4) <= \<const0>\; s_axi_rdata(3) <= \<const0>\; s_axi_rdata(2) <= \<const0>\; s_axi_rdata(1) <= \<const0>\; s_axi_rdata(0) <= \<const0>\; s_axi_rid(0) <= \<const0>\; s_axi_rlast <= \<const0>\; s_axi_rresp(1) <= \<const0>\; s_axi_rresp(0) <= \<const0>\; s_axi_ruser(0) <= \<const0>\; s_axi_rvalid <= \<const0>\; s_axi_wready <= \<const0>\; s_axis_tready <= \<const0>\; sbiterr <= \<const0>\; underflow <= \<const0>\; valid <= \<const0>\; wr_ack <= \<const0>\; wr_data_count(10) <= \<const0>\; wr_data_count(9) <= \<const0>\; wr_data_count(8) <= \<const0>\; wr_data_count(7) <= \<const0>\; wr_data_count(6) <= \<const0>\; wr_data_count(5) <= \<const0>\; wr_data_count(4) <= \<const0>\; wr_data_count(3) <= \<const0>\; wr_data_count(2) <= \<const0>\; wr_data_count(1) <= \<const0>\; wr_data_count(0) <= \<const0>\; wr_rst_busy <= \<const0>\; GND: unisim.vcomponents.GND port map ( G => \<const0>\ ); VCC: unisim.vcomponents.VCC port map ( P => \<const1>\ ); inst_fifo_gen: entity work.input_fifo_fifo_generator_v13_1_3_synth port map ( clk => clk, din(7 downto 0) => din(7 downto 0), dout(7 downto 0) => dout(7 downto 0), empty => empty, full => full, rd_en => rd_en, srst => srst, wr_en => wr_en ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity input_fifo is port ( clk : in STD_LOGIC; srst : in STD_LOGIC; din : in STD_LOGIC_VECTOR ( 7 downto 0 ); wr_en : in STD_LOGIC; rd_en : in STD_LOGIC; dout : out STD_LOGIC_VECTOR ( 7 downto 0 ); full : out STD_LOGIC; empty : out STD_LOGIC ); attribute NotValidForBitStream : boolean; attribute NotValidForBitStream of input_fifo : entity is true; attribute CHECK_LICENSE_TYPE : string; attribute CHECK_LICENSE_TYPE of input_fifo : entity is "input_fifo,fifo_generator_v13_1_3,{}"; attribute downgradeipidentifiedwarnings : string; attribute downgradeipidentifiedwarnings of input_fifo : entity is "yes"; attribute x_core_info : string; attribute x_core_info of input_fifo : entity is "fifo_generator_v13_1_3,Vivado 2016.4"; end input_fifo; architecture STRUCTURE of input_fifo is signal NLW_U0_almost_empty_UNCONNECTED : STD_LOGIC; signal NLW_U0_almost_full_UNCONNECTED : STD_LOGIC; signal NLW_U0_axi_ar_dbiterr_UNCONNECTED : STD_LOGIC; signal NLW_U0_axi_ar_overflow_UNCONNECTED : STD_LOGIC; signal NLW_U0_axi_ar_prog_empty_UNCONNECTED : STD_LOGIC; signal NLW_U0_axi_ar_prog_full_UNCONNECTED : STD_LOGIC; signal NLW_U0_axi_ar_sbiterr_UNCONNECTED : STD_LOGIC; signal NLW_U0_axi_ar_underflow_UNCONNECTED : STD_LOGIC; signal NLW_U0_axi_aw_dbiterr_UNCONNECTED : STD_LOGIC; signal NLW_U0_axi_aw_overflow_UNCONNECTED : STD_LOGIC; signal NLW_U0_axi_aw_prog_empty_UNCONNECTED : STD_LOGIC; signal NLW_U0_axi_aw_prog_full_UNCONNECTED : STD_LOGIC; signal NLW_U0_axi_aw_sbiterr_UNCONNECTED : STD_LOGIC; signal NLW_U0_axi_aw_underflow_UNCONNECTED : STD_LOGIC; signal NLW_U0_axi_b_dbiterr_UNCONNECTED : STD_LOGIC; signal NLW_U0_axi_b_overflow_UNCONNECTED : STD_LOGIC; signal NLW_U0_axi_b_prog_empty_UNCONNECTED : STD_LOGIC; signal NLW_U0_axi_b_prog_full_UNCONNECTED : STD_LOGIC; signal NLW_U0_axi_b_sbiterr_UNCONNECTED : STD_LOGIC; signal NLW_U0_axi_b_underflow_UNCONNECTED : STD_LOGIC; signal NLW_U0_axi_r_dbiterr_UNCONNECTED : STD_LOGIC; signal NLW_U0_axi_r_overflow_UNCONNECTED : STD_LOGIC; signal NLW_U0_axi_r_prog_empty_UNCONNECTED : STD_LOGIC; signal NLW_U0_axi_r_prog_full_UNCONNECTED : STD_LOGIC; signal NLW_U0_axi_r_sbiterr_UNCONNECTED : STD_LOGIC; signal NLW_U0_axi_r_underflow_UNCONNECTED : STD_LOGIC; signal NLW_U0_axi_w_dbiterr_UNCONNECTED : STD_LOGIC; signal NLW_U0_axi_w_overflow_UNCONNECTED : STD_LOGIC; signal NLW_U0_axi_w_prog_empty_UNCONNECTED : STD_LOGIC; signal NLW_U0_axi_w_prog_full_UNCONNECTED : STD_LOGIC; signal NLW_U0_axi_w_sbiterr_UNCONNECTED : STD_LOGIC; signal NLW_U0_axi_w_underflow_UNCONNECTED : STD_LOGIC; signal NLW_U0_axis_dbiterr_UNCONNECTED : STD_LOGIC; signal NLW_U0_axis_overflow_UNCONNECTED : STD_LOGIC; signal NLW_U0_axis_prog_empty_UNCONNECTED : STD_LOGIC; signal NLW_U0_axis_prog_full_UNCONNECTED : STD_LOGIC; signal NLW_U0_axis_sbiterr_UNCONNECTED : STD_LOGIC; signal NLW_U0_axis_underflow_UNCONNECTED : STD_LOGIC; signal NLW_U0_dbiterr_UNCONNECTED : STD_LOGIC; signal NLW_U0_m_axi_arvalid_UNCONNECTED : STD_LOGIC; signal NLW_U0_m_axi_awvalid_UNCONNECTED : STD_LOGIC; signal NLW_U0_m_axi_bready_UNCONNECTED : STD_LOGIC; signal NLW_U0_m_axi_rready_UNCONNECTED : STD_LOGIC; signal NLW_U0_m_axi_wlast_UNCONNECTED : STD_LOGIC; signal NLW_U0_m_axi_wvalid_UNCONNECTED : STD_LOGIC; signal NLW_U0_m_axis_tlast_UNCONNECTED : STD_LOGIC; signal NLW_U0_m_axis_tvalid_UNCONNECTED : STD_LOGIC; signal NLW_U0_overflow_UNCONNECTED : STD_LOGIC; signal NLW_U0_prog_empty_UNCONNECTED : STD_LOGIC; signal NLW_U0_prog_full_UNCONNECTED : STD_LOGIC; signal NLW_U0_rd_rst_busy_UNCONNECTED : STD_LOGIC; signal NLW_U0_s_axi_arready_UNCONNECTED : STD_LOGIC; signal NLW_U0_s_axi_awready_UNCONNECTED : STD_LOGIC; signal NLW_U0_s_axi_bvalid_UNCONNECTED : STD_LOGIC; signal NLW_U0_s_axi_rlast_UNCONNECTED : STD_LOGIC; signal NLW_U0_s_axi_rvalid_UNCONNECTED : STD_LOGIC; signal NLW_U0_s_axi_wready_UNCONNECTED : STD_LOGIC; signal NLW_U0_s_axis_tready_UNCONNECTED : STD_LOGIC; signal NLW_U0_sbiterr_UNCONNECTED : STD_LOGIC; signal NLW_U0_underflow_UNCONNECTED : STD_LOGIC; signal NLW_U0_valid_UNCONNECTED : STD_LOGIC; signal NLW_U0_wr_ack_UNCONNECTED : STD_LOGIC; signal NLW_U0_wr_rst_busy_UNCONNECTED : STD_LOGIC; signal NLW_U0_axi_ar_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 ); signal NLW_U0_axi_ar_rd_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 ); signal NLW_U0_axi_ar_wr_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 ); signal NLW_U0_axi_aw_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 ); signal NLW_U0_axi_aw_rd_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 ); signal NLW_U0_axi_aw_wr_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 ); signal NLW_U0_axi_b_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 ); signal NLW_U0_axi_b_rd_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 ); signal NLW_U0_axi_b_wr_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 ); signal NLW_U0_axi_r_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 ); signal NLW_U0_axi_r_rd_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 ); signal NLW_U0_axi_r_wr_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 ); signal NLW_U0_axi_w_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 ); signal NLW_U0_axi_w_rd_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 ); signal NLW_U0_axi_w_wr_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 ); signal NLW_U0_axis_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 ); signal NLW_U0_axis_rd_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 ); signal NLW_U0_axis_wr_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 ); signal NLW_U0_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 ); signal NLW_U0_m_axi_araddr_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 ); signal NLW_U0_m_axi_arburst_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 ); signal NLW_U0_m_axi_arcache_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 ); signal NLW_U0_m_axi_arid_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); signal NLW_U0_m_axi_arlen_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 ); signal NLW_U0_m_axi_arlock_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); signal NLW_U0_m_axi_arprot_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 ); signal NLW_U0_m_axi_arqos_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 ); signal NLW_U0_m_axi_arregion_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 ); signal NLW_U0_m_axi_arsize_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 ); signal NLW_U0_m_axi_aruser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); signal NLW_U0_m_axi_awaddr_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 ); signal NLW_U0_m_axi_awburst_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 ); signal NLW_U0_m_axi_awcache_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 ); signal NLW_U0_m_axi_awid_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); signal NLW_U0_m_axi_awlen_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 ); signal NLW_U0_m_axi_awlock_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); signal NLW_U0_m_axi_awprot_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 ); signal NLW_U0_m_axi_awqos_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 ); signal NLW_U0_m_axi_awregion_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 ); signal NLW_U0_m_axi_awsize_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 ); signal NLW_U0_m_axi_awuser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); signal NLW_U0_m_axi_wdata_UNCONNECTED : STD_LOGIC_VECTOR ( 63 downto 0 ); signal NLW_U0_m_axi_wid_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); signal NLW_U0_m_axi_wstrb_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 ); signal NLW_U0_m_axi_wuser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); signal NLW_U0_m_axis_tdata_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 ); signal NLW_U0_m_axis_tdest_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); signal NLW_U0_m_axis_tid_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); signal NLW_U0_m_axis_tkeep_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); signal NLW_U0_m_axis_tstrb_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); signal NLW_U0_m_axis_tuser_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 ); signal NLW_U0_rd_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 ); signal NLW_U0_s_axi_bid_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); signal NLW_U0_s_axi_bresp_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 ); signal NLW_U0_s_axi_buser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); signal NLW_U0_s_axi_rdata_UNCONNECTED : STD_LOGIC_VECTOR ( 63 downto 0 ); signal NLW_U0_s_axi_rid_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); signal NLW_U0_s_axi_rresp_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 ); signal NLW_U0_s_axi_ruser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); signal NLW_U0_wr_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 ); attribute C_ADD_NGC_CONSTRAINT : integer; attribute C_ADD_NGC_CONSTRAINT of U0 : label is 0; attribute C_APPLICATION_TYPE_AXIS : integer; attribute C_APPLICATION_TYPE_AXIS of U0 : label is 0; attribute C_APPLICATION_TYPE_RACH : integer; attribute C_APPLICATION_TYPE_RACH of U0 : label is 0; attribute C_APPLICATION_TYPE_RDCH : integer; attribute C_APPLICATION_TYPE_RDCH of U0 : label is 0; attribute C_APPLICATION_TYPE_WACH : integer; attribute C_APPLICATION_TYPE_WACH of U0 : label is 0; attribute C_APPLICATION_TYPE_WDCH : integer; attribute C_APPLICATION_TYPE_WDCH of U0 : label is 0; attribute C_APPLICATION_TYPE_WRCH : integer; attribute C_APPLICATION_TYPE_WRCH of U0 : label is 0; attribute C_AXIS_TDATA_WIDTH : integer; attribute C_AXIS_TDATA_WIDTH of U0 : label is 8; attribute C_AXIS_TDEST_WIDTH : integer; attribute C_AXIS_TDEST_WIDTH of U0 : label is 1; attribute C_AXIS_TID_WIDTH : integer; attribute C_AXIS_TID_WIDTH of U0 : label is 1; attribute C_AXIS_TKEEP_WIDTH : integer; attribute C_AXIS_TKEEP_WIDTH of U0 : label is 1; attribute C_AXIS_TSTRB_WIDTH : integer; attribute C_AXIS_TSTRB_WIDTH of U0 : label is 1; attribute C_AXIS_TUSER_WIDTH : integer; attribute C_AXIS_TUSER_WIDTH of U0 : label is 4; attribute C_AXIS_TYPE : integer; attribute C_AXIS_TYPE of U0 : label is 0; attribute C_AXI_ADDR_WIDTH : integer; attribute C_AXI_ADDR_WIDTH of U0 : label is 32; attribute C_AXI_ARUSER_WIDTH : integer; attribute C_AXI_ARUSER_WIDTH of U0 : label is 1; attribute C_AXI_AWUSER_WIDTH : integer; attribute C_AXI_AWUSER_WIDTH of U0 : label is 1; attribute C_AXI_BUSER_WIDTH : integer; attribute C_AXI_BUSER_WIDTH of U0 : label is 1; attribute C_AXI_DATA_WIDTH : integer; attribute C_AXI_DATA_WIDTH of U0 : label is 64; attribute C_AXI_ID_WIDTH : integer; attribute C_AXI_ID_WIDTH of U0 : label is 1; attribute C_AXI_LEN_WIDTH : integer; attribute C_AXI_LEN_WIDTH of U0 : label is 8; attribute C_AXI_LOCK_WIDTH : integer; attribute C_AXI_LOCK_WIDTH of U0 : label is 1; attribute C_AXI_RUSER_WIDTH : integer; attribute C_AXI_RUSER_WIDTH of U0 : label is 1; attribute C_AXI_TYPE : integer; attribute C_AXI_TYPE of U0 : label is 1; attribute C_AXI_WUSER_WIDTH : integer; attribute C_AXI_WUSER_WIDTH of U0 : label is 1; attribute C_COMMON_CLOCK : integer; attribute C_COMMON_CLOCK of U0 : label is 1; attribute C_COUNT_TYPE : integer; attribute C_COUNT_TYPE of U0 : label is 0; attribute C_DATA_COUNT_WIDTH : integer; attribute C_DATA_COUNT_WIDTH of U0 : label is 11; attribute C_DEFAULT_VALUE : string; attribute C_DEFAULT_VALUE of U0 : label is "BlankString"; attribute C_DIN_WIDTH : integer; attribute C_DIN_WIDTH of U0 : label is 8; attribute C_DIN_WIDTH_AXIS : integer; attribute C_DIN_WIDTH_AXIS of U0 : label is 1; attribute C_DIN_WIDTH_RACH : integer; attribute C_DIN_WIDTH_RACH of U0 : label is 32; attribute C_DIN_WIDTH_RDCH : integer; attribute C_DIN_WIDTH_RDCH of U0 : label is 64; attribute C_DIN_WIDTH_WACH : integer; attribute C_DIN_WIDTH_WACH of U0 : label is 1; attribute C_DIN_WIDTH_WDCH : integer; attribute C_DIN_WIDTH_WDCH of U0 : label is 64; attribute C_DIN_WIDTH_WRCH : integer; attribute C_DIN_WIDTH_WRCH of U0 : label is 2; attribute C_DOUT_RST_VAL : string; attribute C_DOUT_RST_VAL of U0 : label is "0"; attribute C_DOUT_WIDTH : integer; attribute C_DOUT_WIDTH of U0 : label is 8; attribute C_ENABLE_RLOCS : integer; attribute C_ENABLE_RLOCS of U0 : label is 0; attribute C_ENABLE_RST_SYNC : integer; attribute C_ENABLE_RST_SYNC of U0 : label is 1; attribute C_EN_SAFETY_CKT : integer; attribute C_EN_SAFETY_CKT of U0 : label is 0; attribute C_ERROR_INJECTION_TYPE : integer; attribute C_ERROR_INJECTION_TYPE of U0 : label is 0; attribute C_ERROR_INJECTION_TYPE_AXIS : integer; attribute C_ERROR_INJECTION_TYPE_AXIS of U0 : label is 0; attribute C_ERROR_INJECTION_TYPE_RACH : integer; attribute C_ERROR_INJECTION_TYPE_RACH of U0 : label is 0; attribute C_ERROR_INJECTION_TYPE_RDCH : integer; attribute C_ERROR_INJECTION_TYPE_RDCH of U0 : label is 0; attribute C_ERROR_INJECTION_TYPE_WACH : integer; attribute C_ERROR_INJECTION_TYPE_WACH of U0 : label is 0; attribute C_ERROR_INJECTION_TYPE_WDCH : integer; attribute C_ERROR_INJECTION_TYPE_WDCH of U0 : label is 0; attribute C_ERROR_INJECTION_TYPE_WRCH : integer; attribute C_ERROR_INJECTION_TYPE_WRCH of U0 : label is 0; attribute C_FAMILY : string; attribute C_FAMILY of U0 : label is "zynq"; attribute C_FULL_FLAGS_RST_VAL : integer; attribute C_FULL_FLAGS_RST_VAL of U0 : label is 0; attribute C_HAS_ALMOST_EMPTY : integer; attribute C_HAS_ALMOST_EMPTY of U0 : label is 0; attribute C_HAS_ALMOST_FULL : integer; attribute C_HAS_ALMOST_FULL of U0 : label is 0; attribute C_HAS_AXIS_TDATA : integer; attribute C_HAS_AXIS_TDATA of U0 : label is 1; attribute C_HAS_AXIS_TDEST : integer; attribute C_HAS_AXIS_TDEST of U0 : label is 0; attribute C_HAS_AXIS_TID : integer; attribute C_HAS_AXIS_TID of U0 : label is 0; attribute C_HAS_AXIS_TKEEP : integer; attribute C_HAS_AXIS_TKEEP of U0 : label is 0; attribute C_HAS_AXIS_TLAST : integer; attribute C_HAS_AXIS_TLAST of U0 : label is 0; attribute C_HAS_AXIS_TREADY : integer; attribute C_HAS_AXIS_TREADY of U0 : label is 1; attribute C_HAS_AXIS_TSTRB : integer; attribute C_HAS_AXIS_TSTRB of U0 : label is 0; attribute C_HAS_AXIS_TUSER : integer; attribute C_HAS_AXIS_TUSER of U0 : label is 1; attribute C_HAS_AXI_ARUSER : integer; attribute C_HAS_AXI_ARUSER of U0 : label is 0; attribute C_HAS_AXI_AWUSER : integer; attribute C_HAS_AXI_AWUSER of U0 : label is 0; attribute C_HAS_AXI_BUSER : integer; attribute C_HAS_AXI_BUSER of U0 : label is 0; attribute C_HAS_AXI_ID : integer; attribute C_HAS_AXI_ID of U0 : label is 0; attribute C_HAS_AXI_RD_CHANNEL : integer; attribute C_HAS_AXI_RD_CHANNEL of U0 : label is 1; attribute C_HAS_AXI_RUSER : integer; attribute C_HAS_AXI_RUSER of U0 : label is 0; attribute C_HAS_AXI_WR_CHANNEL : integer; attribute C_HAS_AXI_WR_CHANNEL of U0 : label is 1; attribute C_HAS_AXI_WUSER : integer; attribute C_HAS_AXI_WUSER of U0 : label is 0; attribute C_HAS_BACKUP : integer; attribute C_HAS_BACKUP of U0 : label is 0; attribute C_HAS_DATA_COUNT : integer; attribute C_HAS_DATA_COUNT of U0 : label is 0; attribute C_HAS_DATA_COUNTS_AXIS : integer; attribute C_HAS_DATA_COUNTS_AXIS of U0 : label is 0; attribute C_HAS_DATA_COUNTS_RACH : integer; attribute C_HAS_DATA_COUNTS_RACH of U0 : label is 0; attribute C_HAS_DATA_COUNTS_RDCH : integer; attribute C_HAS_DATA_COUNTS_RDCH of U0 : label is 0; attribute C_HAS_DATA_COUNTS_WACH : integer; attribute C_HAS_DATA_COUNTS_WACH of U0 : label is 0; attribute C_HAS_DATA_COUNTS_WDCH : integer; attribute C_HAS_DATA_COUNTS_WDCH of U0 : label is 0; attribute C_HAS_DATA_COUNTS_WRCH : integer; attribute C_HAS_DATA_COUNTS_WRCH of U0 : label is 0; attribute C_HAS_INT_CLK : integer; attribute C_HAS_INT_CLK of U0 : label is 0; attribute C_HAS_MASTER_CE : integer; attribute C_HAS_MASTER_CE of U0 : label is 0; attribute C_HAS_MEMINIT_FILE : integer; attribute C_HAS_MEMINIT_FILE of U0 : label is 0; attribute C_HAS_OVERFLOW : integer; attribute C_HAS_OVERFLOW of U0 : label is 0; attribute C_HAS_PROG_FLAGS_AXIS : integer; attribute C_HAS_PROG_FLAGS_AXIS of U0 : label is 0; attribute C_HAS_PROG_FLAGS_RACH : integer; attribute C_HAS_PROG_FLAGS_RACH of U0 : label is 0; attribute C_HAS_PROG_FLAGS_RDCH : integer; attribute C_HAS_PROG_FLAGS_RDCH of U0 : label is 0; attribute C_HAS_PROG_FLAGS_WACH : integer; attribute C_HAS_PROG_FLAGS_WACH of U0 : label is 0; attribute C_HAS_PROG_FLAGS_WDCH : integer; attribute C_HAS_PROG_FLAGS_WDCH of U0 : label is 0; attribute C_HAS_PROG_FLAGS_WRCH : integer; attribute C_HAS_PROG_FLAGS_WRCH of U0 : label is 0; attribute C_HAS_RD_DATA_COUNT : integer; attribute C_HAS_RD_DATA_COUNT of U0 : label is 0; attribute C_HAS_RD_RST : integer; attribute C_HAS_RD_RST of U0 : label is 0; attribute C_HAS_RST : integer; attribute C_HAS_RST of U0 : label is 0; attribute C_HAS_SLAVE_CE : integer; attribute C_HAS_SLAVE_CE of U0 : label is 0; attribute C_HAS_SRST : integer; attribute C_HAS_SRST of U0 : label is 1; attribute C_HAS_UNDERFLOW : integer; attribute C_HAS_UNDERFLOW of U0 : label is 0; attribute C_HAS_VALID : integer; attribute C_HAS_VALID of U0 : label is 0; attribute C_HAS_WR_ACK : integer; attribute C_HAS_WR_ACK of U0 : label is 0; attribute C_HAS_WR_DATA_COUNT : integer; attribute C_HAS_WR_DATA_COUNT of U0 : label is 0; attribute C_HAS_WR_RST : integer; attribute C_HAS_WR_RST of U0 : label is 0; attribute C_IMPLEMENTATION_TYPE : integer; attribute C_IMPLEMENTATION_TYPE of U0 : label is 0; attribute C_IMPLEMENTATION_TYPE_AXIS : integer; attribute C_IMPLEMENTATION_TYPE_AXIS of U0 : label is 1; attribute C_IMPLEMENTATION_TYPE_RACH : integer; attribute C_IMPLEMENTATION_TYPE_RACH of U0 : label is 1; attribute C_IMPLEMENTATION_TYPE_RDCH : integer; attribute C_IMPLEMENTATION_TYPE_RDCH of U0 : label is 1; attribute C_IMPLEMENTATION_TYPE_WACH : integer; attribute C_IMPLEMENTATION_TYPE_WACH of U0 : label is 1; attribute C_IMPLEMENTATION_TYPE_WDCH : integer; attribute C_IMPLEMENTATION_TYPE_WDCH of U0 : label is 1; attribute C_IMPLEMENTATION_TYPE_WRCH : integer; attribute C_IMPLEMENTATION_TYPE_WRCH of U0 : label is 1; attribute C_INIT_WR_PNTR_VAL : integer; attribute C_INIT_WR_PNTR_VAL of U0 : label is 0; attribute C_INTERFACE_TYPE : integer; attribute C_INTERFACE_TYPE of U0 : label is 0; attribute C_MEMORY_TYPE : integer; attribute C_MEMORY_TYPE of U0 : label is 1; attribute C_MIF_FILE_NAME : string; attribute C_MIF_FILE_NAME of U0 : label is "BlankString"; attribute C_MSGON_VAL : integer; attribute C_MSGON_VAL of U0 : label is 1; attribute C_OPTIMIZATION_MODE : integer; attribute C_OPTIMIZATION_MODE of U0 : label is 0; attribute C_OVERFLOW_LOW : integer; attribute C_OVERFLOW_LOW of U0 : label is 0; attribute C_POWER_SAVING_MODE : integer; attribute C_POWER_SAVING_MODE of U0 : label is 0; attribute C_PRELOAD_LATENCY : integer; attribute C_PRELOAD_LATENCY of U0 : label is 0; attribute C_PRELOAD_REGS : integer; attribute C_PRELOAD_REGS of U0 : label is 1; attribute C_PRIM_FIFO_TYPE : string; attribute C_PRIM_FIFO_TYPE of U0 : label is "1kx18"; attribute C_PRIM_FIFO_TYPE_AXIS : string; attribute C_PRIM_FIFO_TYPE_AXIS of U0 : label is "1kx18"; attribute C_PRIM_FIFO_TYPE_RACH : string; attribute C_PRIM_FIFO_TYPE_RACH of U0 : label is "512x36"; attribute C_PRIM_FIFO_TYPE_RDCH : string; attribute C_PRIM_FIFO_TYPE_RDCH of U0 : label is "1kx36"; attribute C_PRIM_FIFO_TYPE_WACH : string; attribute C_PRIM_FIFO_TYPE_WACH of U0 : label is "512x36"; attribute C_PRIM_FIFO_TYPE_WDCH : string; attribute C_PRIM_FIFO_TYPE_WDCH of U0 : label is "1kx36"; attribute C_PRIM_FIFO_TYPE_WRCH : string; attribute C_PRIM_FIFO_TYPE_WRCH of U0 : label is "512x36"; attribute C_PROG_EMPTY_THRESH_ASSERT_VAL : integer; attribute C_PROG_EMPTY_THRESH_ASSERT_VAL of U0 : label is 4; attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS : integer; attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS of U0 : label is 1022; attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH : integer; attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH of U0 : label is 1022; attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH : integer; attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH of U0 : label is 1022; attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH : integer; attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH of U0 : label is 1022; attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH : integer; attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH of U0 : label is 1022; attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH : integer; attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH of U0 : label is 1022; attribute C_PROG_EMPTY_THRESH_NEGATE_VAL : integer; attribute C_PROG_EMPTY_THRESH_NEGATE_VAL of U0 : label is 5; attribute C_PROG_EMPTY_TYPE : integer; attribute C_PROG_EMPTY_TYPE of U0 : label is 0; attribute C_PROG_EMPTY_TYPE_AXIS : integer; attribute C_PROG_EMPTY_TYPE_AXIS of U0 : label is 0; attribute C_PROG_EMPTY_TYPE_RACH : integer; attribute C_PROG_EMPTY_TYPE_RACH of U0 : label is 0; attribute C_PROG_EMPTY_TYPE_RDCH : integer; attribute C_PROG_EMPTY_TYPE_RDCH of U0 : label is 0; attribute C_PROG_EMPTY_TYPE_WACH : integer; attribute C_PROG_EMPTY_TYPE_WACH of U0 : label is 0; attribute C_PROG_EMPTY_TYPE_WDCH : integer; attribute C_PROG_EMPTY_TYPE_WDCH of U0 : label is 0; attribute C_PROG_EMPTY_TYPE_WRCH : integer; attribute C_PROG_EMPTY_TYPE_WRCH of U0 : label is 0; attribute C_PROG_FULL_THRESH_ASSERT_VAL : integer; attribute C_PROG_FULL_THRESH_ASSERT_VAL of U0 : label is 1023; attribute C_PROG_FULL_THRESH_ASSERT_VAL_AXIS : integer; attribute C_PROG_FULL_THRESH_ASSERT_VAL_AXIS of U0 : label is 1023; attribute C_PROG_FULL_THRESH_ASSERT_VAL_RACH : integer; attribute C_PROG_FULL_THRESH_ASSERT_VAL_RACH of U0 : label is 1023; attribute C_PROG_FULL_THRESH_ASSERT_VAL_RDCH : integer; attribute C_PROG_FULL_THRESH_ASSERT_VAL_RDCH of U0 : label is 1023; attribute C_PROG_FULL_THRESH_ASSERT_VAL_WACH : integer; attribute C_PROG_FULL_THRESH_ASSERT_VAL_WACH of U0 : label is 1023; attribute C_PROG_FULL_THRESH_ASSERT_VAL_WDCH : integer; attribute C_PROG_FULL_THRESH_ASSERT_VAL_WDCH of U0 : label is 1023; attribute C_PROG_FULL_THRESH_ASSERT_VAL_WRCH : integer; attribute C_PROG_FULL_THRESH_ASSERT_VAL_WRCH of U0 : label is 1023; attribute C_PROG_FULL_THRESH_NEGATE_VAL : integer; attribute C_PROG_FULL_THRESH_NEGATE_VAL of U0 : label is 1022; attribute C_PROG_FULL_TYPE : integer; attribute C_PROG_FULL_TYPE of U0 : label is 0; attribute C_PROG_FULL_TYPE_AXIS : integer; attribute C_PROG_FULL_TYPE_AXIS of U0 : label is 0; attribute C_PROG_FULL_TYPE_RACH : integer; attribute C_PROG_FULL_TYPE_RACH of U0 : label is 0; attribute C_PROG_FULL_TYPE_RDCH : integer; attribute C_PROG_FULL_TYPE_RDCH of U0 : label is 0; attribute C_PROG_FULL_TYPE_WACH : integer; attribute C_PROG_FULL_TYPE_WACH of U0 : label is 0; attribute C_PROG_FULL_TYPE_WDCH : integer; attribute C_PROG_FULL_TYPE_WDCH of U0 : label is 0; attribute C_PROG_FULL_TYPE_WRCH : integer; attribute C_PROG_FULL_TYPE_WRCH of U0 : label is 0; attribute C_RACH_TYPE : integer; attribute C_RACH_TYPE of U0 : label is 0; attribute C_RDCH_TYPE : integer; attribute C_RDCH_TYPE of U0 : label is 0; attribute C_RD_DATA_COUNT_WIDTH : integer; attribute C_RD_DATA_COUNT_WIDTH of U0 : label is 11; attribute C_RD_DEPTH : integer; attribute C_RD_DEPTH of U0 : label is 1024; attribute C_RD_FREQ : integer; attribute C_RD_FREQ of U0 : label is 1; attribute C_RD_PNTR_WIDTH : integer; attribute C_RD_PNTR_WIDTH of U0 : label is 10; attribute C_REG_SLICE_MODE_AXIS : integer; attribute C_REG_SLICE_MODE_AXIS of U0 : label is 0; attribute C_REG_SLICE_MODE_RACH : integer; attribute C_REG_SLICE_MODE_RACH of U0 : label is 0; attribute C_REG_SLICE_MODE_RDCH : integer; attribute C_REG_SLICE_MODE_RDCH of U0 : label is 0; attribute C_REG_SLICE_MODE_WACH : integer; attribute C_REG_SLICE_MODE_WACH of U0 : label is 0; attribute C_REG_SLICE_MODE_WDCH : integer; attribute C_REG_SLICE_MODE_WDCH of U0 : label is 0; attribute C_REG_SLICE_MODE_WRCH : integer; attribute C_REG_SLICE_MODE_WRCH of U0 : label is 0; attribute C_SELECT_XPM : integer; attribute C_SELECT_XPM of U0 : label is 0; attribute C_SYNCHRONIZER_STAGE : integer; attribute C_SYNCHRONIZER_STAGE of U0 : label is 2; attribute C_UNDERFLOW_LOW : integer; attribute C_UNDERFLOW_LOW of U0 : label is 0; attribute C_USE_COMMON_OVERFLOW : integer; attribute C_USE_COMMON_OVERFLOW of U0 : label is 0; attribute C_USE_COMMON_UNDERFLOW : integer; attribute C_USE_COMMON_UNDERFLOW of U0 : label is 0; attribute C_USE_DEFAULT_SETTINGS : integer; attribute C_USE_DEFAULT_SETTINGS of U0 : label is 0; attribute C_USE_DOUT_RST : integer; attribute C_USE_DOUT_RST of U0 : label is 1; attribute C_USE_ECC : integer; attribute C_USE_ECC of U0 : label is 0; attribute C_USE_ECC_AXIS : integer; attribute C_USE_ECC_AXIS of U0 : label is 0; attribute C_USE_ECC_RACH : integer; attribute C_USE_ECC_RACH of U0 : label is 0; attribute C_USE_ECC_RDCH : integer; attribute C_USE_ECC_RDCH of U0 : label is 0; attribute C_USE_ECC_WACH : integer; attribute C_USE_ECC_WACH of U0 : label is 0; attribute C_USE_ECC_WDCH : integer; attribute C_USE_ECC_WDCH of U0 : label is 0; attribute C_USE_ECC_WRCH : integer; attribute C_USE_ECC_WRCH of U0 : label is 0; attribute C_USE_EMBEDDED_REG : integer; attribute C_USE_EMBEDDED_REG of U0 : label is 0; attribute C_USE_FIFO16_FLAGS : integer; attribute C_USE_FIFO16_FLAGS of U0 : label is 0; attribute C_USE_FWFT_DATA_COUNT : integer; attribute C_USE_FWFT_DATA_COUNT of U0 : label is 1; attribute C_USE_PIPELINE_REG : integer; attribute C_USE_PIPELINE_REG of U0 : label is 0; attribute C_VALID_LOW : integer; attribute C_VALID_LOW of U0 : label is 0; attribute C_WACH_TYPE : integer; attribute C_WACH_TYPE of U0 : label is 0; attribute C_WDCH_TYPE : integer; attribute C_WDCH_TYPE of U0 : label is 0; attribute C_WRCH_TYPE : integer; attribute C_WRCH_TYPE of U0 : label is 0; attribute C_WR_ACK_LOW : integer; attribute C_WR_ACK_LOW of U0 : label is 0; attribute C_WR_DATA_COUNT_WIDTH : integer; attribute C_WR_DATA_COUNT_WIDTH of U0 : label is 11; attribute C_WR_DEPTH : integer; attribute C_WR_DEPTH of U0 : label is 1024; attribute C_WR_DEPTH_AXIS : integer; attribute C_WR_DEPTH_AXIS of U0 : label is 1024; attribute C_WR_DEPTH_RACH : integer; attribute C_WR_DEPTH_RACH of U0 : label is 16; attribute C_WR_DEPTH_RDCH : integer; attribute C_WR_DEPTH_RDCH of U0 : label is 1024; attribute C_WR_DEPTH_WACH : integer; attribute C_WR_DEPTH_WACH of U0 : label is 16; attribute C_WR_DEPTH_WDCH : integer; attribute C_WR_DEPTH_WDCH of U0 : label is 1024; attribute C_WR_DEPTH_WRCH : integer; attribute C_WR_DEPTH_WRCH of U0 : label is 16; attribute C_WR_FREQ : integer; attribute C_WR_FREQ of U0 : label is 1; attribute C_WR_PNTR_WIDTH : integer; attribute C_WR_PNTR_WIDTH of U0 : label is 10; attribute C_WR_PNTR_WIDTH_AXIS : integer; attribute C_WR_PNTR_WIDTH_AXIS of U0 : label is 10; attribute C_WR_PNTR_WIDTH_RACH : integer; attribute C_WR_PNTR_WIDTH_RACH of U0 : label is 4; attribute C_WR_PNTR_WIDTH_RDCH : integer; attribute C_WR_PNTR_WIDTH_RDCH of U0 : label is 10; attribute C_WR_PNTR_WIDTH_WACH : integer; attribute C_WR_PNTR_WIDTH_WACH of U0 : label is 4; attribute C_WR_PNTR_WIDTH_WDCH : integer; attribute C_WR_PNTR_WIDTH_WDCH of U0 : label is 10; attribute C_WR_PNTR_WIDTH_WRCH : integer; attribute C_WR_PNTR_WIDTH_WRCH of U0 : label is 4; attribute C_WR_RESPONSE_LATENCY : integer; attribute C_WR_RESPONSE_LATENCY of U0 : label is 1; begin U0: entity work.input_fifo_fifo_generator_v13_1_3 port map ( almost_empty => NLW_U0_almost_empty_UNCONNECTED, almost_full => NLW_U0_almost_full_UNCONNECTED, axi_ar_data_count(4 downto 0) => NLW_U0_axi_ar_data_count_UNCONNECTED(4 downto 0), axi_ar_dbiterr => NLW_U0_axi_ar_dbiterr_UNCONNECTED, axi_ar_injectdbiterr => '0', axi_ar_injectsbiterr => '0', axi_ar_overflow => NLW_U0_axi_ar_overflow_UNCONNECTED, axi_ar_prog_empty => NLW_U0_axi_ar_prog_empty_UNCONNECTED, axi_ar_prog_empty_thresh(3 downto 0) => B"0000", axi_ar_prog_full => NLW_U0_axi_ar_prog_full_UNCONNECTED, axi_ar_prog_full_thresh(3 downto 0) => B"0000", axi_ar_rd_data_count(4 downto 0) => NLW_U0_axi_ar_rd_data_count_UNCONNECTED(4 downto 0), axi_ar_sbiterr => NLW_U0_axi_ar_sbiterr_UNCONNECTED, axi_ar_underflow => NLW_U0_axi_ar_underflow_UNCONNECTED, axi_ar_wr_data_count(4 downto 0) => NLW_U0_axi_ar_wr_data_count_UNCONNECTED(4 downto 0), axi_aw_data_count(4 downto 0) => NLW_U0_axi_aw_data_count_UNCONNECTED(4 downto 0), axi_aw_dbiterr => NLW_U0_axi_aw_dbiterr_UNCONNECTED, axi_aw_injectdbiterr => '0', axi_aw_injectsbiterr => '0', axi_aw_overflow => NLW_U0_axi_aw_overflow_UNCONNECTED, axi_aw_prog_empty => NLW_U0_axi_aw_prog_empty_UNCONNECTED, axi_aw_prog_empty_thresh(3 downto 0) => B"0000", axi_aw_prog_full => NLW_U0_axi_aw_prog_full_UNCONNECTED, axi_aw_prog_full_thresh(3 downto 0) => B"0000", axi_aw_rd_data_count(4 downto 0) => NLW_U0_axi_aw_rd_data_count_UNCONNECTED(4 downto 0), axi_aw_sbiterr => NLW_U0_axi_aw_sbiterr_UNCONNECTED, axi_aw_underflow => NLW_U0_axi_aw_underflow_UNCONNECTED, axi_aw_wr_data_count(4 downto 0) => NLW_U0_axi_aw_wr_data_count_UNCONNECTED(4 downto 0), axi_b_data_count(4 downto 0) => NLW_U0_axi_b_data_count_UNCONNECTED(4 downto 0), axi_b_dbiterr => NLW_U0_axi_b_dbiterr_UNCONNECTED, axi_b_injectdbiterr => '0', axi_b_injectsbiterr => '0', axi_b_overflow => NLW_U0_axi_b_overflow_UNCONNECTED, axi_b_prog_empty => NLW_U0_axi_b_prog_empty_UNCONNECTED, axi_b_prog_empty_thresh(3 downto 0) => B"0000", axi_b_prog_full => NLW_U0_axi_b_prog_full_UNCONNECTED, axi_b_prog_full_thresh(3 downto 0) => B"0000", axi_b_rd_data_count(4 downto 0) => NLW_U0_axi_b_rd_data_count_UNCONNECTED(4 downto 0), axi_b_sbiterr => NLW_U0_axi_b_sbiterr_UNCONNECTED, axi_b_underflow => NLW_U0_axi_b_underflow_UNCONNECTED, axi_b_wr_data_count(4 downto 0) => NLW_U0_axi_b_wr_data_count_UNCONNECTED(4 downto 0), axi_r_data_count(10 downto 0) => NLW_U0_axi_r_data_count_UNCONNECTED(10 downto 0), axi_r_dbiterr => NLW_U0_axi_r_dbiterr_UNCONNECTED, axi_r_injectdbiterr => '0', axi_r_injectsbiterr => '0', axi_r_overflow => NLW_U0_axi_r_overflow_UNCONNECTED, axi_r_prog_empty => NLW_U0_axi_r_prog_empty_UNCONNECTED, axi_r_prog_empty_thresh(9 downto 0) => B"0000000000", axi_r_prog_full => NLW_U0_axi_r_prog_full_UNCONNECTED, axi_r_prog_full_thresh(9 downto 0) => B"0000000000", axi_r_rd_data_count(10 downto 0) => NLW_U0_axi_r_rd_data_count_UNCONNECTED(10 downto 0), axi_r_sbiterr => NLW_U0_axi_r_sbiterr_UNCONNECTED, axi_r_underflow => NLW_U0_axi_r_underflow_UNCONNECTED, axi_r_wr_data_count(10 downto 0) => NLW_U0_axi_r_wr_data_count_UNCONNECTED(10 downto 0), axi_w_data_count(10 downto 0) => NLW_U0_axi_w_data_count_UNCONNECTED(10 downto 0), axi_w_dbiterr => NLW_U0_axi_w_dbiterr_UNCONNECTED, axi_w_injectdbiterr => '0', axi_w_injectsbiterr => '0', axi_w_overflow => NLW_U0_axi_w_overflow_UNCONNECTED, axi_w_prog_empty => NLW_U0_axi_w_prog_empty_UNCONNECTED, axi_w_prog_empty_thresh(9 downto 0) => B"0000000000", axi_w_prog_full => NLW_U0_axi_w_prog_full_UNCONNECTED, axi_w_prog_full_thresh(9 downto 0) => B"0000000000", axi_w_rd_data_count(10 downto 0) => NLW_U0_axi_w_rd_data_count_UNCONNECTED(10 downto 0), axi_w_sbiterr => NLW_U0_axi_w_sbiterr_UNCONNECTED, axi_w_underflow => NLW_U0_axi_w_underflow_UNCONNECTED, axi_w_wr_data_count(10 downto 0) => NLW_U0_axi_w_wr_data_count_UNCONNECTED(10 downto 0), axis_data_count(10 downto 0) => NLW_U0_axis_data_count_UNCONNECTED(10 downto 0), axis_dbiterr => NLW_U0_axis_dbiterr_UNCONNECTED, axis_injectdbiterr => '0', axis_injectsbiterr => '0', axis_overflow => NLW_U0_axis_overflow_UNCONNECTED, axis_prog_empty => NLW_U0_axis_prog_empty_UNCONNECTED, axis_prog_empty_thresh(9 downto 0) => B"0000000000", axis_prog_full => NLW_U0_axis_prog_full_UNCONNECTED, axis_prog_full_thresh(9 downto 0) => B"0000000000", axis_rd_data_count(10 downto 0) => NLW_U0_axis_rd_data_count_UNCONNECTED(10 downto 0), axis_sbiterr => NLW_U0_axis_sbiterr_UNCONNECTED, axis_underflow => NLW_U0_axis_underflow_UNCONNECTED, axis_wr_data_count(10 downto 0) => NLW_U0_axis_wr_data_count_UNCONNECTED(10 downto 0), backup => '0', backup_marker => '0', clk => clk, data_count(10 downto 0) => NLW_U0_data_count_UNCONNECTED(10 downto 0), dbiterr => NLW_U0_dbiterr_UNCONNECTED, din(7 downto 0) => din(7 downto 0), dout(7 downto 0) => dout(7 downto 0), empty => empty, full => full, injectdbiterr => '0', injectsbiterr => '0', int_clk => '0', m_aclk => '0', m_aclk_en => '0', m_axi_araddr(31 downto 0) => NLW_U0_m_axi_araddr_UNCONNECTED(31 downto 0), m_axi_arburst(1 downto 0) => NLW_U0_m_axi_arburst_UNCONNECTED(1 downto 0), m_axi_arcache(3 downto 0) => NLW_U0_m_axi_arcache_UNCONNECTED(3 downto 0), m_axi_arid(0) => NLW_U0_m_axi_arid_UNCONNECTED(0), m_axi_arlen(7 downto 0) => NLW_U0_m_axi_arlen_UNCONNECTED(7 downto 0), m_axi_arlock(0) => NLW_U0_m_axi_arlock_UNCONNECTED(0), m_axi_arprot(2 downto 0) => NLW_U0_m_axi_arprot_UNCONNECTED(2 downto 0), m_axi_arqos(3 downto 0) => NLW_U0_m_axi_arqos_UNCONNECTED(3 downto 0), m_axi_arready => '0', m_axi_arregion(3 downto 0) => NLW_U0_m_axi_arregion_UNCONNECTED(3 downto 0), m_axi_arsize(2 downto 0) => NLW_U0_m_axi_arsize_UNCONNECTED(2 downto 0), m_axi_aruser(0) => NLW_U0_m_axi_aruser_UNCONNECTED(0), m_axi_arvalid => NLW_U0_m_axi_arvalid_UNCONNECTED, m_axi_awaddr(31 downto 0) => NLW_U0_m_axi_awaddr_UNCONNECTED(31 downto 0), m_axi_awburst(1 downto 0) => NLW_U0_m_axi_awburst_UNCONNECTED(1 downto 0), m_axi_awcache(3 downto 0) => NLW_U0_m_axi_awcache_UNCONNECTED(3 downto 0), m_axi_awid(0) => NLW_U0_m_axi_awid_UNCONNECTED(0), m_axi_awlen(7 downto 0) => NLW_U0_m_axi_awlen_UNCONNECTED(7 downto 0), m_axi_awlock(0) => NLW_U0_m_axi_awlock_UNCONNECTED(0), m_axi_awprot(2 downto 0) => NLW_U0_m_axi_awprot_UNCONNECTED(2 downto 0), m_axi_awqos(3 downto 0) => NLW_U0_m_axi_awqos_UNCONNECTED(3 downto 0), m_axi_awready => '0', m_axi_awregion(3 downto 0) => NLW_U0_m_axi_awregion_UNCONNECTED(3 downto 0), m_axi_awsize(2 downto 0) => NLW_U0_m_axi_awsize_UNCONNECTED(2 downto 0), m_axi_awuser(0) => NLW_U0_m_axi_awuser_UNCONNECTED(0), m_axi_awvalid => NLW_U0_m_axi_awvalid_UNCONNECTED, m_axi_bid(0) => '0', m_axi_bready => NLW_U0_m_axi_bready_UNCONNECTED, m_axi_bresp(1 downto 0) => B"00", m_axi_buser(0) => '0', m_axi_bvalid => '0', m_axi_rdata(63 downto 0) => B"0000000000000000000000000000000000000000000000000000000000000000", m_axi_rid(0) => '0', m_axi_rlast => '0', m_axi_rready => NLW_U0_m_axi_rready_UNCONNECTED, m_axi_rresp(1 downto 0) => B"00", m_axi_ruser(0) => '0', m_axi_rvalid => '0', m_axi_wdata(63 downto 0) => NLW_U0_m_axi_wdata_UNCONNECTED(63 downto 0), m_axi_wid(0) => NLW_U0_m_axi_wid_UNCONNECTED(0), m_axi_wlast => NLW_U0_m_axi_wlast_UNCONNECTED, m_axi_wready => '0', m_axi_wstrb(7 downto 0) => NLW_U0_m_axi_wstrb_UNCONNECTED(7 downto 0), m_axi_wuser(0) => NLW_U0_m_axi_wuser_UNCONNECTED(0), m_axi_wvalid => NLW_U0_m_axi_wvalid_UNCONNECTED, m_axis_tdata(7 downto 0) => NLW_U0_m_axis_tdata_UNCONNECTED(7 downto 0), m_axis_tdest(0) => NLW_U0_m_axis_tdest_UNCONNECTED(0), m_axis_tid(0) => NLW_U0_m_axis_tid_UNCONNECTED(0), m_axis_tkeep(0) => NLW_U0_m_axis_tkeep_UNCONNECTED(0), m_axis_tlast => NLW_U0_m_axis_tlast_UNCONNECTED, m_axis_tready => '0', m_axis_tstrb(0) => NLW_U0_m_axis_tstrb_UNCONNECTED(0), m_axis_tuser(3 downto 0) => NLW_U0_m_axis_tuser_UNCONNECTED(3 downto 0), m_axis_tvalid => NLW_U0_m_axis_tvalid_UNCONNECTED, overflow => NLW_U0_overflow_UNCONNECTED, prog_empty => NLW_U0_prog_empty_UNCONNECTED, prog_empty_thresh(9 downto 0) => B"0000000000", prog_empty_thresh_assert(9 downto 0) => B"0000000000", prog_empty_thresh_negate(9 downto 0) => B"0000000000", prog_full => NLW_U0_prog_full_UNCONNECTED, prog_full_thresh(9 downto 0) => B"0000000000", prog_full_thresh_assert(9 downto 0) => B"0000000000", prog_full_thresh_negate(9 downto 0) => B"0000000000", rd_clk => '0', rd_data_count(10 downto 0) => NLW_U0_rd_data_count_UNCONNECTED(10 downto 0), rd_en => rd_en, rd_rst => '0', rd_rst_busy => NLW_U0_rd_rst_busy_UNCONNECTED, rst => '0', s_aclk => '0', s_aclk_en => '0', s_aresetn => '0', s_axi_araddr(31 downto 0) => B"00000000000000000000000000000000", s_axi_arburst(1 downto 0) => B"00", s_axi_arcache(3 downto 0) => B"0000", s_axi_arid(0) => '0', s_axi_arlen(7 downto 0) => B"00000000", s_axi_arlock(0) => '0', s_axi_arprot(2 downto 0) => B"000", s_axi_arqos(3 downto 0) => B"0000", s_axi_arready => NLW_U0_s_axi_arready_UNCONNECTED, s_axi_arregion(3 downto 0) => B"0000", s_axi_arsize(2 downto 0) => B"000", s_axi_aruser(0) => '0', s_axi_arvalid => '0', s_axi_awaddr(31 downto 0) => B"00000000000000000000000000000000", s_axi_awburst(1 downto 0) => B"00", s_axi_awcache(3 downto 0) => B"0000", s_axi_awid(0) => '0', s_axi_awlen(7 downto 0) => B"00000000", s_axi_awlock(0) => '0', s_axi_awprot(2 downto 0) => B"000", s_axi_awqos(3 downto 0) => B"0000", s_axi_awready => NLW_U0_s_axi_awready_UNCONNECTED, s_axi_awregion(3 downto 0) => B"0000", s_axi_awsize(2 downto 0) => B"000", s_axi_awuser(0) => '0', s_axi_awvalid => '0', s_axi_bid(0) => NLW_U0_s_axi_bid_UNCONNECTED(0), s_axi_bready => '0', s_axi_bresp(1 downto 0) => NLW_U0_s_axi_bresp_UNCONNECTED(1 downto 0), s_axi_buser(0) => NLW_U0_s_axi_buser_UNCONNECTED(0), s_axi_bvalid => NLW_U0_s_axi_bvalid_UNCONNECTED, s_axi_rdata(63 downto 0) => NLW_U0_s_axi_rdata_UNCONNECTED(63 downto 0), s_axi_rid(0) => NLW_U0_s_axi_rid_UNCONNECTED(0), s_axi_rlast => NLW_U0_s_axi_rlast_UNCONNECTED, s_axi_rready => '0', s_axi_rresp(1 downto 0) => NLW_U0_s_axi_rresp_UNCONNECTED(1 downto 0), s_axi_ruser(0) => NLW_U0_s_axi_ruser_UNCONNECTED(0), s_axi_rvalid => NLW_U0_s_axi_rvalid_UNCONNECTED, s_axi_wdata(63 downto 0) => B"0000000000000000000000000000000000000000000000000000000000000000", s_axi_wid(0) => '0', s_axi_wlast => '0', s_axi_wready => NLW_U0_s_axi_wready_UNCONNECTED, s_axi_wstrb(7 downto 0) => B"00000000", s_axi_wuser(0) => '0', s_axi_wvalid => '0', s_axis_tdata(7 downto 0) => B"00000000", s_axis_tdest(0) => '0', s_axis_tid(0) => '0', s_axis_tkeep(0) => '0', s_axis_tlast => '0', s_axis_tready => NLW_U0_s_axis_tready_UNCONNECTED, s_axis_tstrb(0) => '0', s_axis_tuser(3 downto 0) => B"0000", s_axis_tvalid => '0', sbiterr => NLW_U0_sbiterr_UNCONNECTED, sleep => '0', srst => srst, underflow => NLW_U0_underflow_UNCONNECTED, valid => NLW_U0_valid_UNCONNECTED, wr_ack => NLW_U0_wr_ack_UNCONNECTED, wr_clk => '0', wr_data_count(10 downto 0) => NLW_U0_wr_data_count_UNCONNECTED(10 downto 0), wr_en => wr_en, wr_rst => '0', wr_rst_busy => NLW_U0_wr_rst_busy_UNCONNECTED ); end STRUCTURE;
unlicense
30b48a042ad1774ddabc38d07cbcdc41
0.62692
2.899748
false
false
false
false
jairov4/accel-oil
solution_spartan6/syn/vhdl/nfa_accept_samples_generic_hw_add_64ns_64ns_64_16.vhd
6
35,870
-- ============================================================== -- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC -- Version: 2013.4 -- Copyright (C) 2013 Xilinx Inc. All rights reserved. -- -- ============================================================== library IEEE; use IEEE.std_logic_1164.all; use ieee.std_logic_arith.all; entity nfa_accept_samples_generic_hw_add_64ns_64ns_64_16_AddSubnS_2 is port ( clk: in std_logic; reset: in std_logic; ce: in std_logic; a: in std_logic_vector(63 downto 0); b: in std_logic_vector(63 downto 0); s: out std_logic_vector(63 downto 0)); end entity; architecture behav of nfa_accept_samples_generic_hw_add_64ns_64ns_64_16_AddSubnS_2 is component nfa_accept_samples_generic_hw_add_64ns_64ns_64_16_AddSubnS_2_fadder is port ( faa : IN STD_LOGIC_VECTOR (4-1 downto 0); fab : IN STD_LOGIC_VECTOR (4-1 downto 0); facin : IN STD_LOGIC_VECTOR (0 downto 0); fas : OUT STD_LOGIC_VECTOR (4-1 downto 0); facout : OUT STD_LOGIC_VECTOR (0 downto 0)); end component; component nfa_accept_samples_generic_hw_add_64ns_64ns_64_16_AddSubnS_2_fadder_f is port ( faa : IN STD_LOGIC_VECTOR (4-1 downto 0); fab : IN STD_LOGIC_VECTOR (4-1 downto 0); facin : IN STD_LOGIC_VECTOR (0 downto 0); fas : OUT STD_LOGIC_VECTOR (4-1 downto 0); facout : OUT STD_LOGIC_VECTOR (0 downto 0)); end component; -- ---- register and wire type variables list here ---- -- wire for the primary inputs signal a_reg : std_logic_vector(63 downto 0); signal b_reg : std_logic_vector(63 downto 0); -- wires for each small adder signal a0_cb : std_logic_vector(3 downto 0); signal b0_cb : std_logic_vector(3 downto 0); signal a1_cb : std_logic_vector(7 downto 4); signal b1_cb : std_logic_vector(7 downto 4); signal a2_cb : std_logic_vector(11 downto 8); signal b2_cb : std_logic_vector(11 downto 8); signal a3_cb : std_logic_vector(15 downto 12); signal b3_cb : std_logic_vector(15 downto 12); signal a4_cb : std_logic_vector(19 downto 16); signal b4_cb : std_logic_vector(19 downto 16); signal a5_cb : std_logic_vector(23 downto 20); signal b5_cb : std_logic_vector(23 downto 20); signal a6_cb : std_logic_vector(27 downto 24); signal b6_cb : std_logic_vector(27 downto 24); signal a7_cb : std_logic_vector(31 downto 28); signal b7_cb : std_logic_vector(31 downto 28); signal a8_cb : std_logic_vector(35 downto 32); signal b8_cb : std_logic_vector(35 downto 32); signal a9_cb : std_logic_vector(39 downto 36); signal b9_cb : std_logic_vector(39 downto 36); signal a10_cb : std_logic_vector(43 downto 40); signal b10_cb : std_logic_vector(43 downto 40); signal a11_cb : std_logic_vector(47 downto 44); signal b11_cb : std_logic_vector(47 downto 44); signal a12_cb : std_logic_vector(51 downto 48); signal b12_cb : std_logic_vector(51 downto 48); signal a13_cb : std_logic_vector(55 downto 52); signal b13_cb : std_logic_vector(55 downto 52); signal a14_cb : std_logic_vector(59 downto 56); signal b14_cb : std_logic_vector(59 downto 56); signal a15_cb : std_logic_vector(63 downto 60); signal b15_cb : std_logic_vector(63 downto 60); -- registers for input register array type ramtypei0 is array (0 downto 0) of std_logic_vector(3 downto 0); signal a1_cb_regi1 : ramtypei0; signal b1_cb_regi1 : ramtypei0; type ramtypei1 is array (1 downto 0) of std_logic_vector(3 downto 0); signal a2_cb_regi2 : ramtypei1; signal b2_cb_regi2 : ramtypei1; type ramtypei2 is array (2 downto 0) of std_logic_vector(3 downto 0); signal a3_cb_regi3 : ramtypei2; signal b3_cb_regi3 : ramtypei2; type ramtypei3 is array (3 downto 0) of std_logic_vector(3 downto 0); signal a4_cb_regi4 : ramtypei3; signal b4_cb_regi4 : ramtypei3; type ramtypei4 is array (4 downto 0) of std_logic_vector(3 downto 0); signal a5_cb_regi5 : ramtypei4; signal b5_cb_regi5 : ramtypei4; type ramtypei5 is array (5 downto 0) of std_logic_vector(3 downto 0); signal a6_cb_regi6 : ramtypei5; signal b6_cb_regi6 : ramtypei5; type ramtypei6 is array (6 downto 0) of std_logic_vector(3 downto 0); signal a7_cb_regi7 : ramtypei6; signal b7_cb_regi7 : ramtypei6; type ramtypei7 is array (7 downto 0) of std_logic_vector(3 downto 0); signal a8_cb_regi8 : ramtypei7; signal b8_cb_regi8 : ramtypei7; type ramtypei8 is array (8 downto 0) of std_logic_vector(3 downto 0); signal a9_cb_regi9 : ramtypei8; signal b9_cb_regi9 : ramtypei8; type ramtypei9 is array (9 downto 0) of std_logic_vector(3 downto 0); signal a10_cb_regi10 : ramtypei9; signal b10_cb_regi10 : ramtypei9; type ramtypei10 is array (10 downto 0) of std_logic_vector(3 downto 0); signal a11_cb_regi11 : ramtypei10; signal b11_cb_regi11 : ramtypei10; type ramtypei11 is array (11 downto 0) of std_logic_vector(3 downto 0); signal a12_cb_regi12 : ramtypei11; signal b12_cb_regi12 : ramtypei11; type ramtypei12 is array (12 downto 0) of std_logic_vector(3 downto 0); signal a13_cb_regi13 : ramtypei12; signal b13_cb_regi13 : ramtypei12; type ramtypei13 is array (13 downto 0) of std_logic_vector(3 downto 0); signal a14_cb_regi14 : ramtypei13; signal b14_cb_regi14 : ramtypei13; type ramtypei14 is array (14 downto 0) of std_logic_vector(3 downto 0); signal a15_cb_regi15 : ramtypei14; signal b15_cb_regi15 : ramtypei14; -- wires for each full adder sum signal fas : std_logic_vector(63 downto 0); -- wires and register for carry out bit signal faccout_ini : std_logic_vector (0 downto 0); signal faccout0_co0 : std_logic_vector (0 downto 0); signal faccout1_co1 : std_logic_vector (0 downto 0); signal faccout2_co2 : std_logic_vector (0 downto 0); signal faccout3_co3 : std_logic_vector (0 downto 0); signal faccout4_co4 : std_logic_vector (0 downto 0); signal faccout5_co5 : std_logic_vector (0 downto 0); signal faccout6_co6 : std_logic_vector (0 downto 0); signal faccout7_co7 : std_logic_vector (0 downto 0); signal faccout8_co8 : std_logic_vector (0 downto 0); signal faccout9_co9 : std_logic_vector (0 downto 0); signal faccout10_co10 : std_logic_vector (0 downto 0); signal faccout11_co11 : std_logic_vector (0 downto 0); signal faccout12_co12 : std_logic_vector (0 downto 0); signal faccout13_co13 : std_logic_vector (0 downto 0); signal faccout14_co14 : std_logic_vector (0 downto 0); signal faccout15_co15 : std_logic_vector (0 downto 0); signal faccout0_co0_reg : std_logic_vector (0 downto 0); signal faccout1_co1_reg : std_logic_vector (0 downto 0); signal faccout2_co2_reg : std_logic_vector (0 downto 0); signal faccout3_co3_reg : std_logic_vector (0 downto 0); signal faccout4_co4_reg : std_logic_vector (0 downto 0); signal faccout5_co5_reg : std_logic_vector (0 downto 0); signal faccout6_co6_reg : std_logic_vector (0 downto 0); signal faccout7_co7_reg : std_logic_vector (0 downto 0); signal faccout8_co8_reg : std_logic_vector (0 downto 0); signal faccout9_co9_reg : std_logic_vector (0 downto 0); signal faccout10_co10_reg : std_logic_vector (0 downto 0); signal faccout11_co11_reg : std_logic_vector (0 downto 0); signal faccout12_co12_reg : std_logic_vector (0 downto 0); signal faccout13_co13_reg : std_logic_vector (0 downto 0); signal faccout14_co14_reg : std_logic_vector (0 downto 0); -- registers for output register array type ramtypeo14 is array (14 downto 0) of std_logic_vector(3 downto 0); signal s0_ca_rego0 : ramtypeo14; type ramtypeo13 is array (13 downto 0) of std_logic_vector(3 downto 0); signal s1_ca_rego1 : ramtypeo13; type ramtypeo12 is array (12 downto 0) of std_logic_vector(3 downto 0); signal s2_ca_rego2 : ramtypeo12; type ramtypeo11 is array (11 downto 0) of std_logic_vector(3 downto 0); signal s3_ca_rego3 : ramtypeo11; type ramtypeo10 is array (10 downto 0) of std_logic_vector(3 downto 0); signal s4_ca_rego4 : ramtypeo10; type ramtypeo9 is array (9 downto 0) of std_logic_vector(3 downto 0); signal s5_ca_rego5 : ramtypeo9; type ramtypeo8 is array (8 downto 0) of std_logic_vector(3 downto 0); signal s6_ca_rego6 : ramtypeo8; type ramtypeo7 is array (7 downto 0) of std_logic_vector(3 downto 0); signal s7_ca_rego7 : ramtypeo7; type ramtypeo6 is array (6 downto 0) of std_logic_vector(3 downto 0); signal s8_ca_rego8 : ramtypeo6; type ramtypeo5 is array (5 downto 0) of std_logic_vector(3 downto 0); signal s9_ca_rego9 : ramtypeo5; type ramtypeo4 is array (4 downto 0) of std_logic_vector(3 downto 0); signal s10_ca_rego10 : ramtypeo4; type ramtypeo3 is array (3 downto 0) of std_logic_vector(3 downto 0); signal s11_ca_rego11 : ramtypeo3; type ramtypeo2 is array (2 downto 0) of std_logic_vector(3 downto 0); signal s12_ca_rego12 : ramtypeo2; type ramtypeo1 is array (1 downto 0) of std_logic_vector(3 downto 0); signal s13_ca_rego13 : ramtypeo1; type ramtypeo0 is array (0 downto 0) of std_logic_vector(3 downto 0); signal s14_ca_rego14 : ramtypeo0; -- wire for the temporary output signal s_tmp : std_logic_vector(63 downto 0); -- ---- RTL code for assignment statements/always blocks/module instantiations here ---- begin a_reg <= a; b_reg <= b; -- small adder input assigments a0_cb <= a_reg(3 downto 0); b0_cb <= b_reg(3 downto 0); a1_cb <= a_reg(7 downto 4); b1_cb <= b_reg(7 downto 4); a2_cb <= a_reg(11 downto 8); b2_cb <= b_reg(11 downto 8); a3_cb <= a_reg(15 downto 12); b3_cb <= b_reg(15 downto 12); a4_cb <= a_reg(19 downto 16); b4_cb <= b_reg(19 downto 16); a5_cb <= a_reg(23 downto 20); b5_cb <= b_reg(23 downto 20); a6_cb <= a_reg(27 downto 24); b6_cb <= b_reg(27 downto 24); a7_cb <= a_reg(31 downto 28); b7_cb <= b_reg(31 downto 28); a8_cb <= a_reg(35 downto 32); b8_cb <= b_reg(35 downto 32); a9_cb <= a_reg(39 downto 36); b9_cb <= b_reg(39 downto 36); a10_cb <= a_reg(43 downto 40); b10_cb <= b_reg(43 downto 40); a11_cb <= a_reg(47 downto 44); b11_cb <= b_reg(47 downto 44); a12_cb <= a_reg(51 downto 48); b12_cb <= b_reg(51 downto 48); a13_cb <= a_reg(55 downto 52); b13_cb <= b_reg(55 downto 52); a14_cb <= a_reg(59 downto 56); b14_cb <= b_reg(59 downto 56); a15_cb <= a_reg(63 downto 60); b15_cb <= b_reg(63 downto 60); -- input register array process (clk) begin if (clk'event and clk='1') then if (ce='1') then a1_cb_regi1 (0) <= a1_cb; b1_cb_regi1 (0) <= b1_cb; a2_cb_regi2 (0) <= a2_cb; b2_cb_regi2 (0) <= b2_cb; a3_cb_regi3 (0) <= a3_cb; b3_cb_regi3 (0) <= b3_cb; a4_cb_regi4 (0) <= a4_cb; b4_cb_regi4 (0) <= b4_cb; a5_cb_regi5 (0) <= a5_cb; b5_cb_regi5 (0) <= b5_cb; a6_cb_regi6 (0) <= a6_cb; b6_cb_regi6 (0) <= b6_cb; a7_cb_regi7 (0) <= a7_cb; b7_cb_regi7 (0) <= b7_cb; a8_cb_regi8 (0) <= a8_cb; b8_cb_regi8 (0) <= b8_cb; a9_cb_regi9 (0) <= a9_cb; b9_cb_regi9 (0) <= b9_cb; a10_cb_regi10 (0) <= a10_cb; b10_cb_regi10 (0) <= b10_cb; a11_cb_regi11 (0) <= a11_cb; b11_cb_regi11 (0) <= b11_cb; a12_cb_regi12 (0) <= a12_cb; b12_cb_regi12 (0) <= b12_cb; a13_cb_regi13 (0) <= a13_cb; b13_cb_regi13 (0) <= b13_cb; a14_cb_regi14 (0) <= a14_cb; b14_cb_regi14 (0) <= b14_cb; a15_cb_regi15 (0) <= a15_cb; b15_cb_regi15 (0) <= b15_cb; a2_cb_regi2 (1) <= a2_cb_regi2 (0); b2_cb_regi2 (1) <= b2_cb_regi2 (0); a3_cb_regi3 (1) <= a3_cb_regi3 (0); b3_cb_regi3 (1) <= b3_cb_regi3 (0); a4_cb_regi4 (1) <= a4_cb_regi4 (0); b4_cb_regi4 (1) <= b4_cb_regi4 (0); a5_cb_regi5 (1) <= a5_cb_regi5 (0); b5_cb_regi5 (1) <= b5_cb_regi5 (0); a6_cb_regi6 (1) <= a6_cb_regi6 (0); b6_cb_regi6 (1) <= b6_cb_regi6 (0); a7_cb_regi7 (1) <= a7_cb_regi7 (0); b7_cb_regi7 (1) <= b7_cb_regi7 (0); a8_cb_regi8 (1) <= a8_cb_regi8 (0); b8_cb_regi8 (1) <= b8_cb_regi8 (0); a9_cb_regi9 (1) <= a9_cb_regi9 (0); b9_cb_regi9 (1) <= b9_cb_regi9 (0); a10_cb_regi10 (1) <= a10_cb_regi10 (0); b10_cb_regi10 (1) <= b10_cb_regi10 (0); a11_cb_regi11 (1) <= a11_cb_regi11 (0); b11_cb_regi11 (1) <= b11_cb_regi11 (0); a12_cb_regi12 (1) <= a12_cb_regi12 (0); b12_cb_regi12 (1) <= b12_cb_regi12 (0); a13_cb_regi13 (1) <= a13_cb_regi13 (0); b13_cb_regi13 (1) <= b13_cb_regi13 (0); a14_cb_regi14 (1) <= a14_cb_regi14 (0); b14_cb_regi14 (1) <= b14_cb_regi14 (0); a15_cb_regi15 (1) <= a15_cb_regi15 (0); b15_cb_regi15 (1) <= b15_cb_regi15 (0); a3_cb_regi3 (2) <= a3_cb_regi3 (1); b3_cb_regi3 (2) <= b3_cb_regi3 (1); a4_cb_regi4 (2) <= a4_cb_regi4 (1); b4_cb_regi4 (2) <= b4_cb_regi4 (1); a5_cb_regi5 (2) <= a5_cb_regi5 (1); b5_cb_regi5 (2) <= b5_cb_regi5 (1); a6_cb_regi6 (2) <= a6_cb_regi6 (1); b6_cb_regi6 (2) <= b6_cb_regi6 (1); a7_cb_regi7 (2) <= a7_cb_regi7 (1); b7_cb_regi7 (2) <= b7_cb_regi7 (1); a8_cb_regi8 (2) <= a8_cb_regi8 (1); b8_cb_regi8 (2) <= b8_cb_regi8 (1); a9_cb_regi9 (2) <= a9_cb_regi9 (1); b9_cb_regi9 (2) <= b9_cb_regi9 (1); a10_cb_regi10 (2) <= a10_cb_regi10 (1); b10_cb_regi10 (2) <= b10_cb_regi10 (1); a11_cb_regi11 (2) <= a11_cb_regi11 (1); b11_cb_regi11 (2) <= b11_cb_regi11 (1); a12_cb_regi12 (2) <= a12_cb_regi12 (1); b12_cb_regi12 (2) <= b12_cb_regi12 (1); a13_cb_regi13 (2) <= a13_cb_regi13 (1); b13_cb_regi13 (2) <= b13_cb_regi13 (1); a14_cb_regi14 (2) <= a14_cb_regi14 (1); b14_cb_regi14 (2) <= b14_cb_regi14 (1); a15_cb_regi15 (2) <= a15_cb_regi15 (1); b15_cb_regi15 (2) <= b15_cb_regi15 (1); a4_cb_regi4 (3) <= a4_cb_regi4 (2); b4_cb_regi4 (3) <= b4_cb_regi4 (2); a5_cb_regi5 (3) <= a5_cb_regi5 (2); b5_cb_regi5 (3) <= b5_cb_regi5 (2); a6_cb_regi6 (3) <= a6_cb_regi6 (2); b6_cb_regi6 (3) <= b6_cb_regi6 (2); a7_cb_regi7 (3) <= a7_cb_regi7 (2); b7_cb_regi7 (3) <= b7_cb_regi7 (2); a8_cb_regi8 (3) <= a8_cb_regi8 (2); b8_cb_regi8 (3) <= b8_cb_regi8 (2); a9_cb_regi9 (3) <= a9_cb_regi9 (2); b9_cb_regi9 (3) <= b9_cb_regi9 (2); a10_cb_regi10 (3) <= a10_cb_regi10 (2); b10_cb_regi10 (3) <= b10_cb_regi10 (2); a11_cb_regi11 (3) <= a11_cb_regi11 (2); b11_cb_regi11 (3) <= b11_cb_regi11 (2); a12_cb_regi12 (3) <= a12_cb_regi12 (2); b12_cb_regi12 (3) <= b12_cb_regi12 (2); a13_cb_regi13 (3) <= a13_cb_regi13 (2); b13_cb_regi13 (3) <= b13_cb_regi13 (2); a14_cb_regi14 (3) <= a14_cb_regi14 (2); b14_cb_regi14 (3) <= b14_cb_regi14 (2); a15_cb_regi15 (3) <= a15_cb_regi15 (2); b15_cb_regi15 (3) <= b15_cb_regi15 (2); a5_cb_regi5 (4) <= a5_cb_regi5 (3); b5_cb_regi5 (4) <= b5_cb_regi5 (3); a6_cb_regi6 (4) <= a6_cb_regi6 (3); b6_cb_regi6 (4) <= b6_cb_regi6 (3); a7_cb_regi7 (4) <= a7_cb_regi7 (3); b7_cb_regi7 (4) <= b7_cb_regi7 (3); a8_cb_regi8 (4) <= a8_cb_regi8 (3); b8_cb_regi8 (4) <= b8_cb_regi8 (3); a9_cb_regi9 (4) <= a9_cb_regi9 (3); b9_cb_regi9 (4) <= b9_cb_regi9 (3); a10_cb_regi10 (4) <= a10_cb_regi10 (3); b10_cb_regi10 (4) <= b10_cb_regi10 (3); a11_cb_regi11 (4) <= a11_cb_regi11 (3); b11_cb_regi11 (4) <= b11_cb_regi11 (3); a12_cb_regi12 (4) <= a12_cb_regi12 (3); b12_cb_regi12 (4) <= b12_cb_regi12 (3); a13_cb_regi13 (4) <= a13_cb_regi13 (3); b13_cb_regi13 (4) <= b13_cb_regi13 (3); a14_cb_regi14 (4) <= a14_cb_regi14 (3); b14_cb_regi14 (4) <= b14_cb_regi14 (3); a15_cb_regi15 (4) <= a15_cb_regi15 (3); b15_cb_regi15 (4) <= b15_cb_regi15 (3); a6_cb_regi6 (5) <= a6_cb_regi6 (4); b6_cb_regi6 (5) <= b6_cb_regi6 (4); a7_cb_regi7 (5) <= a7_cb_regi7 (4); b7_cb_regi7 (5) <= b7_cb_regi7 (4); a8_cb_regi8 (5) <= a8_cb_regi8 (4); b8_cb_regi8 (5) <= b8_cb_regi8 (4); a9_cb_regi9 (5) <= a9_cb_regi9 (4); b9_cb_regi9 (5) <= b9_cb_regi9 (4); a10_cb_regi10 (5) <= a10_cb_regi10 (4); b10_cb_regi10 (5) <= b10_cb_regi10 (4); a11_cb_regi11 (5) <= a11_cb_regi11 (4); b11_cb_regi11 (5) <= b11_cb_regi11 (4); a12_cb_regi12 (5) <= a12_cb_regi12 (4); b12_cb_regi12 (5) <= b12_cb_regi12 (4); a13_cb_regi13 (5) <= a13_cb_regi13 (4); b13_cb_regi13 (5) <= b13_cb_regi13 (4); a14_cb_regi14 (5) <= a14_cb_regi14 (4); b14_cb_regi14 (5) <= b14_cb_regi14 (4); a15_cb_regi15 (5) <= a15_cb_regi15 (4); b15_cb_regi15 (5) <= b15_cb_regi15 (4); a7_cb_regi7 (6) <= a7_cb_regi7 (5); b7_cb_regi7 (6) <= b7_cb_regi7 (5); a8_cb_regi8 (6) <= a8_cb_regi8 (5); b8_cb_regi8 (6) <= b8_cb_regi8 (5); a9_cb_regi9 (6) <= a9_cb_regi9 (5); b9_cb_regi9 (6) <= b9_cb_regi9 (5); a10_cb_regi10 (6) <= a10_cb_regi10 (5); b10_cb_regi10 (6) <= b10_cb_regi10 (5); a11_cb_regi11 (6) <= a11_cb_regi11 (5); b11_cb_regi11 (6) <= b11_cb_regi11 (5); a12_cb_regi12 (6) <= a12_cb_regi12 (5); b12_cb_regi12 (6) <= b12_cb_regi12 (5); a13_cb_regi13 (6) <= a13_cb_regi13 (5); b13_cb_regi13 (6) <= b13_cb_regi13 (5); a14_cb_regi14 (6) <= a14_cb_regi14 (5); b14_cb_regi14 (6) <= b14_cb_regi14 (5); a15_cb_regi15 (6) <= a15_cb_regi15 (5); b15_cb_regi15 (6) <= b15_cb_regi15 (5); a8_cb_regi8 (7) <= a8_cb_regi8 (6); b8_cb_regi8 (7) <= b8_cb_regi8 (6); a9_cb_regi9 (7) <= a9_cb_regi9 (6); b9_cb_regi9 (7) <= b9_cb_regi9 (6); a10_cb_regi10 (7) <= a10_cb_regi10 (6); b10_cb_regi10 (7) <= b10_cb_regi10 (6); a11_cb_regi11 (7) <= a11_cb_regi11 (6); b11_cb_regi11 (7) <= b11_cb_regi11 (6); a12_cb_regi12 (7) <= a12_cb_regi12 (6); b12_cb_regi12 (7) <= b12_cb_regi12 (6); a13_cb_regi13 (7) <= a13_cb_regi13 (6); b13_cb_regi13 (7) <= b13_cb_regi13 (6); a14_cb_regi14 (7) <= a14_cb_regi14 (6); b14_cb_regi14 (7) <= b14_cb_regi14 (6); a15_cb_regi15 (7) <= a15_cb_regi15 (6); b15_cb_regi15 (7) <= b15_cb_regi15 (6); a9_cb_regi9 (8) <= a9_cb_regi9 (7); b9_cb_regi9 (8) <= b9_cb_regi9 (7); a10_cb_regi10 (8) <= a10_cb_regi10 (7); b10_cb_regi10 (8) <= b10_cb_regi10 (7); a11_cb_regi11 (8) <= a11_cb_regi11 (7); b11_cb_regi11 (8) <= b11_cb_regi11 (7); a12_cb_regi12 (8) <= a12_cb_regi12 (7); b12_cb_regi12 (8) <= b12_cb_regi12 (7); a13_cb_regi13 (8) <= a13_cb_regi13 (7); b13_cb_regi13 (8) <= b13_cb_regi13 (7); a14_cb_regi14 (8) <= a14_cb_regi14 (7); b14_cb_regi14 (8) <= b14_cb_regi14 (7); a15_cb_regi15 (8) <= a15_cb_regi15 (7); b15_cb_regi15 (8) <= b15_cb_regi15 (7); a10_cb_regi10 (9) <= a10_cb_regi10 (8); b10_cb_regi10 (9) <= b10_cb_regi10 (8); a11_cb_regi11 (9) <= a11_cb_regi11 (8); b11_cb_regi11 (9) <= b11_cb_regi11 (8); a12_cb_regi12 (9) <= a12_cb_regi12 (8); b12_cb_regi12 (9) <= b12_cb_regi12 (8); a13_cb_regi13 (9) <= a13_cb_regi13 (8); b13_cb_regi13 (9) <= b13_cb_regi13 (8); a14_cb_regi14 (9) <= a14_cb_regi14 (8); b14_cb_regi14 (9) <= b14_cb_regi14 (8); a15_cb_regi15 (9) <= a15_cb_regi15 (8); b15_cb_regi15 (9) <= b15_cb_regi15 (8); a11_cb_regi11 (10) <= a11_cb_regi11 (9); b11_cb_regi11 (10) <= b11_cb_regi11 (9); a12_cb_regi12 (10) <= a12_cb_regi12 (9); b12_cb_regi12 (10) <= b12_cb_regi12 (9); a13_cb_regi13 (10) <= a13_cb_regi13 (9); b13_cb_regi13 (10) <= b13_cb_regi13 (9); a14_cb_regi14 (10) <= a14_cb_regi14 (9); b14_cb_regi14 (10) <= b14_cb_regi14 (9); a15_cb_regi15 (10) <= a15_cb_regi15 (9); b15_cb_regi15 (10) <= b15_cb_regi15 (9); a12_cb_regi12 (11) <= a12_cb_regi12 (10); b12_cb_regi12 (11) <= b12_cb_regi12 (10); a13_cb_regi13 (11) <= a13_cb_regi13 (10); b13_cb_regi13 (11) <= b13_cb_regi13 (10); a14_cb_regi14 (11) <= a14_cb_regi14 (10); b14_cb_regi14 (11) <= b14_cb_regi14 (10); a15_cb_regi15 (11) <= a15_cb_regi15 (10); b15_cb_regi15 (11) <= b15_cb_regi15 (10); a13_cb_regi13 (12) <= a13_cb_regi13 (11); b13_cb_regi13 (12) <= b13_cb_regi13 (11); a14_cb_regi14 (12) <= a14_cb_regi14 (11); b14_cb_regi14 (12) <= b14_cb_regi14 (11); a15_cb_regi15 (12) <= a15_cb_regi15 (11); b15_cb_regi15 (12) <= b15_cb_regi15 (11); a14_cb_regi14 (13) <= a14_cb_regi14 (12); b14_cb_regi14 (13) <= b14_cb_regi14 (12); a15_cb_regi15 (13) <= a15_cb_regi15 (12); b15_cb_regi15 (13) <= b15_cb_regi15 (12); a15_cb_regi15 (14) <= a15_cb_regi15 (13); b15_cb_regi15 (14) <= b15_cb_regi15 (13); end if; end if; end process; -- carry out bit processing process (clk) begin if (clk'event and clk='1') then if (ce='1') then faccout0_co0_reg <= faccout0_co0; faccout1_co1_reg <= faccout1_co1; faccout2_co2_reg <= faccout2_co2; faccout3_co3_reg <= faccout3_co3; faccout4_co4_reg <= faccout4_co4; faccout5_co5_reg <= faccout5_co5; faccout6_co6_reg <= faccout6_co6; faccout7_co7_reg <= faccout7_co7; faccout8_co8_reg <= faccout8_co8; faccout9_co9_reg <= faccout9_co9; faccout10_co10_reg <= faccout10_co10; faccout11_co11_reg <= faccout11_co11; faccout12_co12_reg <= faccout12_co12; faccout13_co13_reg <= faccout13_co13; faccout14_co14_reg <= faccout14_co14; end if; end if; end process; -- small adder generation u0 : nfa_accept_samples_generic_hw_add_64ns_64ns_64_16_AddSubnS_2_fadder port map (faa => a0_cb, fab => b0_cb, facin => faccout_ini, fas => fas(3 downto 0), facout => faccout0_co0); u1 : nfa_accept_samples_generic_hw_add_64ns_64ns_64_16_AddSubnS_2_fadder port map (faa => a1_cb_regi1(0), fab => b1_cb_regi1(0), facin => faccout0_co0_reg, fas => fas(7 downto 4), facout => faccout1_co1); u2 : nfa_accept_samples_generic_hw_add_64ns_64ns_64_16_AddSubnS_2_fadder port map (faa => a2_cb_regi2(1), fab => b2_cb_regi2(1), facin => faccout1_co1_reg, fas => fas(11 downto 8), facout => faccout2_co2); u3 : nfa_accept_samples_generic_hw_add_64ns_64ns_64_16_AddSubnS_2_fadder port map (faa => a3_cb_regi3(2), fab => b3_cb_regi3(2), facin => faccout2_co2_reg, fas => fas(15 downto 12), facout => faccout3_co3); u4 : nfa_accept_samples_generic_hw_add_64ns_64ns_64_16_AddSubnS_2_fadder port map (faa => a4_cb_regi4(3), fab => b4_cb_regi4(3), facin => faccout3_co3_reg, fas => fas(19 downto 16), facout => faccout4_co4); u5 : nfa_accept_samples_generic_hw_add_64ns_64ns_64_16_AddSubnS_2_fadder port map (faa => a5_cb_regi5(4), fab => b5_cb_regi5(4), facin => faccout4_co4_reg, fas => fas(23 downto 20), facout => faccout5_co5); u6 : nfa_accept_samples_generic_hw_add_64ns_64ns_64_16_AddSubnS_2_fadder port map (faa => a6_cb_regi6(5), fab => b6_cb_regi6(5), facin => faccout5_co5_reg, fas => fas(27 downto 24), facout => faccout6_co6); u7 : nfa_accept_samples_generic_hw_add_64ns_64ns_64_16_AddSubnS_2_fadder port map (faa => a7_cb_regi7(6), fab => b7_cb_regi7(6), facin => faccout6_co6_reg, fas => fas(31 downto 28), facout => faccout7_co7); u8 : nfa_accept_samples_generic_hw_add_64ns_64ns_64_16_AddSubnS_2_fadder port map (faa => a8_cb_regi8(7), fab => b8_cb_regi8(7), facin => faccout7_co7_reg, fas => fas(35 downto 32), facout => faccout8_co8); u9 : nfa_accept_samples_generic_hw_add_64ns_64ns_64_16_AddSubnS_2_fadder port map (faa => a9_cb_regi9(8), fab => b9_cb_regi9(8), facin => faccout8_co8_reg, fas => fas(39 downto 36), facout => faccout9_co9); u10 : nfa_accept_samples_generic_hw_add_64ns_64ns_64_16_AddSubnS_2_fadder port map (faa => a10_cb_regi10(9), fab => b10_cb_regi10(9), facin => faccout9_co9_reg, fas => fas(43 downto 40), facout => faccout10_co10); u11 : nfa_accept_samples_generic_hw_add_64ns_64ns_64_16_AddSubnS_2_fadder port map (faa => a11_cb_regi11(10), fab => b11_cb_regi11(10), facin => faccout10_co10_reg, fas => fas(47 downto 44), facout => faccout11_co11); u12 : nfa_accept_samples_generic_hw_add_64ns_64ns_64_16_AddSubnS_2_fadder port map (faa => a12_cb_regi12(11), fab => b12_cb_regi12(11), facin => faccout11_co11_reg, fas => fas(51 downto 48), facout => faccout12_co12); u13 : nfa_accept_samples_generic_hw_add_64ns_64ns_64_16_AddSubnS_2_fadder port map (faa => a13_cb_regi13(12), fab => b13_cb_regi13(12), facin => faccout12_co12_reg, fas => fas(55 downto 52), facout => faccout13_co13); u14 : nfa_accept_samples_generic_hw_add_64ns_64ns_64_16_AddSubnS_2_fadder port map (faa => a14_cb_regi14(13), fab => b14_cb_regi14(13), facin => faccout13_co13_reg, fas => fas(59 downto 56), facout => faccout14_co14); u15 : nfa_accept_samples_generic_hw_add_64ns_64ns_64_16_AddSubnS_2_fadder_f port map (faa => a15_cb_regi15(14), fab => b15_cb_regi15(14), facin => faccout14_co14_reg, fas => fas(63 downto 60), facout => faccout15_co15); faccout_ini <= "0"; -- output register array process (clk) begin if (clk'event and clk='1') then if (ce='1') then s0_ca_rego0 (0) <= fas(3 downto 0); s1_ca_rego1 (0) <= fas(7 downto 4); s2_ca_rego2 (0) <= fas(11 downto 8); s3_ca_rego3 (0) <= fas(15 downto 12); s4_ca_rego4 (0) <= fas(19 downto 16); s5_ca_rego5 (0) <= fas(23 downto 20); s6_ca_rego6 (0) <= fas(27 downto 24); s7_ca_rego7 (0) <= fas(31 downto 28); s8_ca_rego8 (0) <= fas(35 downto 32); s9_ca_rego9 (0) <= fas(39 downto 36); s10_ca_rego10 (0) <= fas(43 downto 40); s11_ca_rego11 (0) <= fas(47 downto 44); s12_ca_rego12 (0) <= fas(51 downto 48); s13_ca_rego13 (0) <= fas(55 downto 52); s14_ca_rego14 (0) <= fas(59 downto 56); s0_ca_rego0 (1) <= s0_ca_rego0 (0); s0_ca_rego0 (2) <= s0_ca_rego0 (1); s0_ca_rego0 (3) <= s0_ca_rego0 (2); s0_ca_rego0 (4) <= s0_ca_rego0 (3); s0_ca_rego0 (5) <= s0_ca_rego0 (4); s0_ca_rego0 (6) <= s0_ca_rego0 (5); s0_ca_rego0 (7) <= s0_ca_rego0 (6); s0_ca_rego0 (8) <= s0_ca_rego0 (7); s0_ca_rego0 (9) <= s0_ca_rego0 (8); s0_ca_rego0 (10) <= s0_ca_rego0 (9); s0_ca_rego0 (11) <= s0_ca_rego0 (10); s0_ca_rego0 (12) <= s0_ca_rego0 (11); s0_ca_rego0 (13) <= s0_ca_rego0 (12); s0_ca_rego0 (14) <= s0_ca_rego0 (13); s1_ca_rego1 (1) <= s1_ca_rego1 (0); s1_ca_rego1 (2) <= s1_ca_rego1 (1); s1_ca_rego1 (3) <= s1_ca_rego1 (2); s1_ca_rego1 (4) <= s1_ca_rego1 (3); s1_ca_rego1 (5) <= s1_ca_rego1 (4); s1_ca_rego1 (6) <= s1_ca_rego1 (5); s1_ca_rego1 (7) <= s1_ca_rego1 (6); s1_ca_rego1 (8) <= s1_ca_rego1 (7); s1_ca_rego1 (9) <= s1_ca_rego1 (8); s1_ca_rego1 (10) <= s1_ca_rego1 (9); s1_ca_rego1 (11) <= s1_ca_rego1 (10); s1_ca_rego1 (12) <= s1_ca_rego1 (11); s1_ca_rego1 (13) <= s1_ca_rego1 (12); s2_ca_rego2 (1) <= s2_ca_rego2 (0); s2_ca_rego2 (2) <= s2_ca_rego2 (1); s2_ca_rego2 (3) <= s2_ca_rego2 (2); s2_ca_rego2 (4) <= s2_ca_rego2 (3); s2_ca_rego2 (5) <= s2_ca_rego2 (4); s2_ca_rego2 (6) <= s2_ca_rego2 (5); s2_ca_rego2 (7) <= s2_ca_rego2 (6); s2_ca_rego2 (8) <= s2_ca_rego2 (7); s2_ca_rego2 (9) <= s2_ca_rego2 (8); s2_ca_rego2 (10) <= s2_ca_rego2 (9); s2_ca_rego2 (11) <= s2_ca_rego2 (10); s2_ca_rego2 (12) <= s2_ca_rego2 (11); s3_ca_rego3 (1) <= s3_ca_rego3 (0); s3_ca_rego3 (2) <= s3_ca_rego3 (1); s3_ca_rego3 (3) <= s3_ca_rego3 (2); s3_ca_rego3 (4) <= s3_ca_rego3 (3); s3_ca_rego3 (5) <= s3_ca_rego3 (4); s3_ca_rego3 (6) <= s3_ca_rego3 (5); s3_ca_rego3 (7) <= s3_ca_rego3 (6); s3_ca_rego3 (8) <= s3_ca_rego3 (7); s3_ca_rego3 (9) <= s3_ca_rego3 (8); s3_ca_rego3 (10) <= s3_ca_rego3 (9); s3_ca_rego3 (11) <= s3_ca_rego3 (10); s4_ca_rego4 (1) <= s4_ca_rego4 (0); s4_ca_rego4 (2) <= s4_ca_rego4 (1); s4_ca_rego4 (3) <= s4_ca_rego4 (2); s4_ca_rego4 (4) <= s4_ca_rego4 (3); s4_ca_rego4 (5) <= s4_ca_rego4 (4); s4_ca_rego4 (6) <= s4_ca_rego4 (5); s4_ca_rego4 (7) <= s4_ca_rego4 (6); s4_ca_rego4 (8) <= s4_ca_rego4 (7); s4_ca_rego4 (9) <= s4_ca_rego4 (8); s4_ca_rego4 (10) <= s4_ca_rego4 (9); s5_ca_rego5 (1) <= s5_ca_rego5 (0); s5_ca_rego5 (2) <= s5_ca_rego5 (1); s5_ca_rego5 (3) <= s5_ca_rego5 (2); s5_ca_rego5 (4) <= s5_ca_rego5 (3); s5_ca_rego5 (5) <= s5_ca_rego5 (4); s5_ca_rego5 (6) <= s5_ca_rego5 (5); s5_ca_rego5 (7) <= s5_ca_rego5 (6); s5_ca_rego5 (8) <= s5_ca_rego5 (7); s5_ca_rego5 (9) <= s5_ca_rego5 (8); s6_ca_rego6 (1) <= s6_ca_rego6 (0); s6_ca_rego6 (2) <= s6_ca_rego6 (1); s6_ca_rego6 (3) <= s6_ca_rego6 (2); s6_ca_rego6 (4) <= s6_ca_rego6 (3); s6_ca_rego6 (5) <= s6_ca_rego6 (4); s6_ca_rego6 (6) <= s6_ca_rego6 (5); s6_ca_rego6 (7) <= s6_ca_rego6 (6); s6_ca_rego6 (8) <= s6_ca_rego6 (7); s7_ca_rego7 (1) <= s7_ca_rego7 (0); s7_ca_rego7 (2) <= s7_ca_rego7 (1); s7_ca_rego7 (3) <= s7_ca_rego7 (2); s7_ca_rego7 (4) <= s7_ca_rego7 (3); s7_ca_rego7 (5) <= s7_ca_rego7 (4); s7_ca_rego7 (6) <= s7_ca_rego7 (5); s7_ca_rego7 (7) <= s7_ca_rego7 (6); s8_ca_rego8 (1) <= s8_ca_rego8 (0); s8_ca_rego8 (2) <= s8_ca_rego8 (1); s8_ca_rego8 (3) <= s8_ca_rego8 (2); s8_ca_rego8 (4) <= s8_ca_rego8 (3); s8_ca_rego8 (5) <= s8_ca_rego8 (4); s8_ca_rego8 (6) <= s8_ca_rego8 (5); s9_ca_rego9 (1) <= s9_ca_rego9 (0); s9_ca_rego9 (2) <= s9_ca_rego9 (1); s9_ca_rego9 (3) <= s9_ca_rego9 (2); s9_ca_rego9 (4) <= s9_ca_rego9 (3); s9_ca_rego9 (5) <= s9_ca_rego9 (4); s10_ca_rego10 (1) <= s10_ca_rego10 (0); s10_ca_rego10 (2) <= s10_ca_rego10 (1); s10_ca_rego10 (3) <= s10_ca_rego10 (2); s10_ca_rego10 (4) <= s10_ca_rego10 (3); s11_ca_rego11 (1) <= s11_ca_rego11 (0); s11_ca_rego11 (2) <= s11_ca_rego11 (1); s11_ca_rego11 (3) <= s11_ca_rego11 (2); s12_ca_rego12 (1) <= s12_ca_rego12 (0); s12_ca_rego12 (2) <= s12_ca_rego12 (1); s13_ca_rego13 (1) <= s13_ca_rego13 (0); end if; end if; end process; -- get the s_tmp, assign it to the primary output s_tmp(3 downto 0) <= s0_ca_rego0(14); s_tmp(7 downto 4) <= s1_ca_rego1(13); s_tmp(11 downto 8) <= s2_ca_rego2(12); s_tmp(15 downto 12) <= s3_ca_rego3(11); s_tmp(19 downto 16) <= s4_ca_rego4(10); s_tmp(23 downto 20) <= s5_ca_rego5(9); s_tmp(27 downto 24) <= s6_ca_rego6(8); s_tmp(31 downto 28) <= s7_ca_rego7(7); s_tmp(35 downto 32) <= s8_ca_rego8(6); s_tmp(39 downto 36) <= s9_ca_rego9(5); s_tmp(43 downto 40) <= s10_ca_rego10(4); s_tmp(47 downto 44) <= s11_ca_rego11(3); s_tmp(51 downto 48) <= s12_ca_rego12(2); s_tmp(55 downto 52) <= s13_ca_rego13(1); s_tmp(59 downto 56) <= s14_ca_rego14(0); s_tmp(63 downto 60) <= fas(63 downto 60); s <= s_tmp; end architecture; -- short adder library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; entity nfa_accept_samples_generic_hw_add_64ns_64ns_64_16_AddSubnS_2_fadder is generic(N : natural :=4); port ( faa : IN STD_LOGIC_VECTOR (N-1 downto 0); fab : IN STD_LOGIC_VECTOR (N-1 downto 0); facin : IN STD_LOGIC_VECTOR (0 downto 0); fas : OUT STD_LOGIC_VECTOR (N-1 downto 0); facout : OUT STD_LOGIC_VECTOR (0 downto 0)); end; architecture behav of nfa_accept_samples_generic_hw_add_64ns_64ns_64_16_AddSubnS_2_fadder is signal tmp : STD_LOGIC_VECTOR (N downto 0); begin tmp <= std_logic_vector(unsigned(std_logic_vector(unsigned(std_logic_vector(resize(unsigned(faa),N+1))) + unsigned(fab))) + unsigned(facin)); fas <= tmp(N-1 downto 0 ); facout <= tmp(N downto N); end behav; -- the final stage short adder library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; entity nfa_accept_samples_generic_hw_add_64ns_64ns_64_16_AddSubnS_2_fadder_f is generic(N : natural :=4); port ( faa : IN STD_LOGIC_VECTOR (N-1 downto 0); fab : IN STD_LOGIC_VECTOR (N-1 downto 0); facin : IN STD_LOGIC_VECTOR (0 downto 0); fas : OUT STD_LOGIC_VECTOR (N-1 downto 0); facout : OUT STD_LOGIC_VECTOR (0 downto 0)); end; architecture behav of nfa_accept_samples_generic_hw_add_64ns_64ns_64_16_AddSubnS_2_fadder_f is signal tmp : STD_LOGIC_VECTOR (N downto 0); begin tmp <= std_logic_vector(unsigned(std_logic_vector(unsigned(std_logic_vector(resize(unsigned(faa),N+1))) + unsigned(fab))) + unsigned(facin)); fas <= tmp(N-1 downto 0 ); facout <= tmp(N downto N); end behav; Library IEEE; use IEEE.std_logic_1164.all; entity nfa_accept_samples_generic_hw_add_64ns_64ns_64_16 is generic ( ID : INTEGER; NUM_STAGE : INTEGER; din0_WIDTH : INTEGER; din1_WIDTH : INTEGER; dout_WIDTH : INTEGER); port ( clk : IN STD_LOGIC; reset : IN STD_LOGIC; ce : IN STD_LOGIC; din0 : IN STD_LOGIC_VECTOR(din0_WIDTH - 1 DOWNTO 0); din1 : IN STD_LOGIC_VECTOR(din1_WIDTH - 1 DOWNTO 0); dout : OUT STD_LOGIC_VECTOR(dout_WIDTH - 1 DOWNTO 0)); end entity; architecture arch of nfa_accept_samples_generic_hw_add_64ns_64ns_64_16 is component nfa_accept_samples_generic_hw_add_64ns_64ns_64_16_AddSubnS_2 is port ( clk : IN STD_LOGIC; reset : IN STD_LOGIC; ce : IN STD_LOGIC; a : IN STD_LOGIC_VECTOR; b : IN STD_LOGIC_VECTOR; s : OUT STD_LOGIC_VECTOR); end component; begin nfa_accept_samples_generic_hw_add_64ns_64ns_64_16_AddSubnS_2_U : component nfa_accept_samples_generic_hw_add_64ns_64ns_64_16_AddSubnS_2 port map ( clk => clk, reset => reset, ce => ce, a => din0, b => din1, s => dout); end architecture;
lgpl-3.0
9e4e088f9d1dc0f8b66e50122a05af54
0.560022
2.455336
false
false
false
false
grwlf/vsim
vhdl_ct/ct00249.vhd
1
6,716
-- NEED RESULT: ARCH00249: All tests for Section 2.2 passed ------------------------------------------------------------------------------- -- -- Copyright (c) 1989 by Intermetrics, Inc. -- All rights reserved. -- ------------------------------------------------------------------------------- -- -- TEST NAME: -- -- CT00249 -- -- AUTHOR: -- -- D. Hyman -- -- TEST OBJECTIVES: -- -- 2.2 (1) -- 2.2 (2) -- 2.2 (3) -- 2.2 (4) -- 2.2 (5) -- 2.2 (6) -- 2.2 (7) -- 2.2 (8) -- -- DESIGN UNIT ORDERING: -- -- E00000(ARCH00249) -- ENT00249_Test_Bench(ARCH00249_Test_Bench) -- -- REVISION HISTORY: -- -- 15-JUL-1987 - initial revision -- 11-DEC-1989 - GDT: removed signal asg from function -- -- NOTES: -- -- self-checking -- -- Only objectives 2.2 (6) and 2.2 (7) are checked dynamically; the others -- are static compile-time checks. -- -- -- use WORK.STANDARD_TYPES.all ; architecture ARCH00249 of E00000 is constant c : integer := 25 ; signal s : integer ; -- the following proc shows that all admissable declarations may appear -- in a subprogram declaration part 2.2 (1) procedure proc_with_big_declarative_part is variable x : integer ; -- variable declaration procedure subprogram ( a,b,c : integer ) ; -- subprogram declaration procedure subprogram ( a,b,c : integer ) is -- subprogram body begin end ; type enum_type is (enum_0, enum_1, enum_2) ; -- type declaration subtype sub_enum_type is -- subtype declaration enum_type range enum_0 to enum_1 ; constant k : integer := 2 ; -- constant declaration type enum_file_type is file of enum_type ; file enum_file : enum_file_type is in "HOSTFILENAME"; -- file declaration alias alias_x : integer is x ; -- alias declaration attribute enum_attribute : enum_type ; -- attribute declaration attribute enum_attribute of all : signal is enum_0 ; -- attribute spec use WORK.all ; -- use clause use STANDARD_TYPES.all ; -- use clause begin end proc_with_big_declarative_part ; -- the following proc shows that the ending designator is optional 2.2 (2) -- and that a subprogram statement part need contain no statements 2.2 (4) -- and that the declaration of a subprogram is optional 2.2 (5) procedure proc_without_ending_designator is begin end ; -- the following proc & function shows that all sequential sttements can -- appear in a subprogram (except wait statements in a function) 2.2 (3) -- JW: signal parameter added so that the signal assign stm would be legal procedure proc_with_all_sequential_statements(signal s: inout integer) is variable b : boolean ; variable x : integer ; begin s <= 1 ; -- signal assign statement assert false report "false" ; -- assertion statement wait for 1 ns ; -- wait statement case b is -- case statement when false => null; -- null statement when true => proc_without_ending_designator;-- procedure call statement end case ; for i in 1 to 5 loop -- loop statement via "for" if i < 5 then -- if statement next ; -- next statement else exit; -- exit statement end if ; end loop ; while x < 5 loop -- loop statement via "while" x := x + 1 ; -- variable assign statement end loop ; return ; -- return statement end ; -- the following shows that subprograms can access constants outside -- their declarative regions 2.2 (6) and 2.2 (7) procedure proc_called_by_func ( n: inout integer ) is begin n := n + c ; end proc_called_by_func ; function func_calling_proc ( n: integer) return integer is variable v : integer; begin v := n; proc_called_by_func(v); return v + c ; end func_calling_proc ; -- the following shows that dynamically sized structures may be declared -- within a subroutine that contains a wait statement 2.2 (8) procedure proc_with_wait_statement ( n: integer ) is type dyn_array is array ( integer range <> ) of integer ; variable arr : dyn_array (1 to n) ; begin wait for 1 ns ; end proc_with_wait_statement ; begin JW: process -- JW: This function was moved into a process so that the signal assign -- statement would be legal. function func_with_all_sequential_statements return integer is variable b : boolean ; variable x : integer ; begin -- GDT 12-7-89: s <= 1 ; -- signal assign statement assert false report "false" ; -- assertion statement case b is -- case statement when false => null; -- null statement when true => proc_without_ending_designator;-- procedure call statement end case ; for i in 1 to 5 loop -- loop statement via "for" if i < 5 then -- if statement next ; -- next statement else exit; -- exit statement end if ; end loop ; while x < 5 loop -- loop statement via "while" x := x + 1 ; -- variable assign statement end loop ; return 0 ; -- return statement end ; begin wait ; end process; P : process begin test_report ( "ARCH00249" , "All tests for Section 2.2 " , func_calling_proc (20) = 20 + 2*25 ) ; wait ; end process P ; end ARCH00249 ; entity ENT00249_Test_Bench is end ENT00249_Test_Bench ; architecture ARCH00249_Test_Bench of ENT00249_Test_Bench is begin L1: block component UUT end component ; for CIS1 : UUT use entity WORK.E00000 ( ARCH00249 ) ; begin CIS1 : UUT ; end block L1 ; end ARCH00249_Test_Bench ;
gpl-3.0
79001aa4880f752418219f9b84d601d5
0.51623
4.294118
false
true
false
false
dcliche/mdsynth
rtl/src/sound/nco.vhd
1
2,489
-- MDSynth Sound Chip -- -- Copyright (c) 2012, Meldora Inc. -- All rights reserved. -- -- Redistribution and use in source and binary forms, with or without modification, are permitted provided that the -- following conditions are met: -- -- * Redistributions of source code must retain the above copyright notice, this list of conditions and the -- following disclaimer. -- * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the -- following disclaimer in the documentation and/or other materials provided with the distribution. -- -- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, -- INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -- DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -- SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR -- SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -- WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE -- USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -- -- Numerically-controlled oscillator -- library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.NUMERIC_STD.ALL; -- freq = (50E6 * (phase_delta * 2^octave)) / 2^32 entity nco is port ( clk: in std_logic; reset_phase: in std_logic; ena: in std_logic; phase_delta: in unsigned(11 downto 0); octave: in unsigned(3 downto 0); phase: out unsigned(7 downto 0)); end nco; architecture nco_arch of nco is signal phase_accumulator: unsigned(31 downto 0) := to_unsigned(0, 32); signal toggle: std_logic := '0' ; signal phase_delta_32: unsigned(31 downto 0) := to_unsigned(0, 32); begin process (clk) begin if (rising_edge(clk)) then phase_delta_32(11 downto 0) <= phase_delta; if (reset_phase = '1') then phase_accumulator <= to_unsigned(0, 32); elsif (ena = '1') then phase_accumulator <= phase_accumulator + (phase_delta_32 sll (to_integer(octave))); end if; phase <= phase_accumulator(31 downto 24); end if; end process; end nco_arch;
gpl-3.0
5415ee5b8558b47bf26bb03861a71eeb
0.691844
4.047154
false
false
false
false
jairov4/accel-oil
impl/impl_test_single/simulation/behavioral/nfa_accept_samples_generic_hw_top_v1_01_a/nfa_accept_samples_generic_hw/_primary.vhd
1
12,304
library verilog; use verilog.vl_types.all; entity nfa_accept_samples_generic_hw is generic( ap_const_logic_1: vl_logic := Hi1; ap_const_logic_0: vl_logic := Hi0; ap_ST_st1_fsm_0 : vl_logic_vector(0 to 5) := (Hi0, Hi0, Hi0, Hi0, Hi0, Hi0); ap_ST_st2_fsm_1 : vl_logic_vector(0 to 5) := (Hi0, Hi0, Hi0, Hi0, Hi0, Hi1); ap_ST_st3_fsm_2 : vl_logic_vector(0 to 5) := (Hi0, Hi0, Hi0, Hi0, Hi1, Hi0); ap_ST_st4_fsm_3 : vl_logic_vector(0 to 5) := (Hi0, Hi0, Hi0, Hi0, Hi1, Hi1); ap_ST_st5_fsm_4 : vl_logic_vector(0 to 5) := (Hi0, Hi0, Hi0, Hi1, Hi0, Hi0); ap_ST_st6_fsm_5 : vl_logic_vector(0 to 5) := (Hi0, Hi0, Hi0, Hi1, Hi0, Hi1); ap_ST_st7_fsm_6 : vl_logic_vector(0 to 5) := (Hi0, Hi0, Hi0, Hi1, Hi1, Hi0); ap_ST_st8_fsm_7 : vl_logic_vector(0 to 5) := (Hi0, Hi0, Hi0, Hi1, Hi1, Hi1); ap_ST_st9_fsm_8 : vl_logic_vector(0 to 5) := (Hi0, Hi0, Hi1, Hi0, Hi0, Hi0); ap_ST_st10_fsm_9: vl_logic_vector(0 to 5) := (Hi0, Hi0, Hi1, Hi0, Hi0, Hi1); ap_ST_st11_fsm_10: vl_logic_vector(0 to 5) := (Hi0, Hi0, Hi1, Hi0, Hi1, Hi0); ap_ST_st12_fsm_11: vl_logic_vector(0 to 5) := (Hi0, Hi0, Hi1, Hi0, Hi1, Hi1); ap_ST_st13_fsm_12: vl_logic_vector(0 to 5) := (Hi0, Hi0, Hi1, Hi1, Hi0, Hi0); ap_ST_st14_fsm_13: vl_logic_vector(0 to 5) := (Hi0, Hi0, Hi1, Hi1, Hi0, Hi1); ap_ST_st15_fsm_14: vl_logic_vector(0 to 5) := (Hi0, Hi0, Hi1, Hi1, Hi1, Hi0); ap_ST_st16_fsm_15: vl_logic_vector(0 to 5) := (Hi0, Hi0, Hi1, Hi1, Hi1, Hi1); ap_ST_st17_fsm_16: vl_logic_vector(0 to 5) := (Hi0, Hi1, Hi0, Hi0, Hi0, Hi0); ap_ST_st18_fsm_17: vl_logic_vector(0 to 5) := (Hi0, Hi1, Hi0, Hi0, Hi0, Hi1); ap_ST_st19_fsm_18: vl_logic_vector(0 to 5) := (Hi0, Hi1, Hi0, Hi0, Hi1, Hi0); ap_ST_st20_fsm_19: vl_logic_vector(0 to 5) := (Hi0, Hi1, Hi0, Hi0, Hi1, Hi1); ap_ST_st21_fsm_20: vl_logic_vector(0 to 5) := (Hi0, Hi1, Hi0, Hi1, Hi0, Hi0); ap_ST_st22_fsm_21: vl_logic_vector(0 to 5) := (Hi0, Hi1, Hi0, Hi1, Hi0, Hi1); ap_ST_st23_fsm_22: vl_logic_vector(0 to 5) := (Hi0, Hi1, Hi0, Hi1, Hi1, Hi0); ap_ST_st24_fsm_23: vl_logic_vector(0 to 5) := (Hi0, Hi1, Hi0, Hi1, Hi1, Hi1); ap_ST_st25_fsm_24: vl_logic_vector(0 to 5) := (Hi0, Hi1, Hi1, Hi0, Hi0, Hi0); ap_ST_st26_fsm_25: vl_logic_vector(0 to 5) := (Hi0, Hi1, Hi1, Hi0, Hi0, Hi1); ap_ST_st27_fsm_26: vl_logic_vector(0 to 5) := (Hi0, Hi1, Hi1, Hi0, Hi1, Hi0); ap_ST_st28_fsm_27: vl_logic_vector(0 to 5) := (Hi0, Hi1, Hi1, Hi0, Hi1, Hi1); ap_ST_st29_fsm_28: vl_logic_vector(0 to 5) := (Hi0, Hi1, Hi1, Hi1, Hi0, Hi0); ap_ST_st30_fsm_29: vl_logic_vector(0 to 5) := (Hi0, Hi1, Hi1, Hi1, Hi0, Hi1); ap_ST_st31_fsm_30: vl_logic_vector(0 to 5) := (Hi0, Hi1, Hi1, Hi1, Hi1, Hi0); ap_ST_st32_fsm_31: vl_logic_vector(0 to 5) := (Hi0, Hi1, Hi1, Hi1, Hi1, Hi1); ap_ST_st33_fsm_32: vl_logic_vector(0 to 5) := (Hi1, Hi0, Hi0, Hi0, Hi0, Hi0); ap_ST_st34_fsm_33: vl_logic_vector(0 to 5) := (Hi1, Hi0, Hi0, Hi0, Hi0, Hi1); ap_ST_st35_fsm_34: vl_logic_vector(0 to 5) := (Hi1, Hi0, Hi0, Hi0, Hi1, Hi0); ap_ST_st36_fsm_35: vl_logic_vector(0 to 5) := (Hi1, Hi0, Hi0, Hi0, Hi1, Hi1); ap_ST_st37_fsm_36: vl_logic_vector(0 to 5) := (Hi1, Hi0, Hi0, Hi1, Hi0, Hi0); ap_const_lv1_0 : vl_logic := Hi0; ap_const_lv16_0 : vl_logic_vector(0 to 15) := (Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0); ap_const_lv64_0 : vl_logic_vector(0 to 63) := (Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0); ap_const_lv1_1 : vl_logic := Hi1; ap_const_lv32_0 : integer := 0; ap_const_lv2_2 : vl_logic_vector(0 to 1) := (Hi1, Hi0); ap_const_lv32_1 : integer := 1; ap_const_lv64_1 : vl_logic_vector(0 to 63) := (Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi1); ap_const_lv16_1 : vl_logic_vector(0 to 15) := (Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi1); ap_const_lv5_0 : vl_logic_vector(0 to 4) := (Hi0, Hi0, Hi0, Hi0, Hi0); ap_const_lv8_0 : vl_logic_vector(0 to 7) := (Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0); ap_true : vl_logic := Hi1 ); port( ap_clk : in vl_logic; ap_rst : in vl_logic; ap_start : in vl_logic; ap_done : out vl_logic; ap_idle : out vl_logic; ap_ready : out vl_logic; nfa_initials_buckets_req_din: out vl_logic; nfa_initials_buckets_req_full_n: in vl_logic; nfa_initials_buckets_req_write: out vl_logic; nfa_initials_buckets_rsp_empty_n: in vl_logic; nfa_initials_buckets_rsp_read: out vl_logic; nfa_initials_buckets_address: out vl_logic_vector(31 downto 0); nfa_initials_buckets_datain: in vl_logic_vector(31 downto 0); nfa_initials_buckets_dataout: out vl_logic_vector(31 downto 0); nfa_initials_buckets_size: out vl_logic_vector(31 downto 0); nfa_finals_buckets_req_din: out vl_logic; nfa_finals_buckets_req_full_n: in vl_logic; nfa_finals_buckets_req_write: out vl_logic; nfa_finals_buckets_rsp_empty_n: in vl_logic; nfa_finals_buckets_rsp_read: out vl_logic; nfa_finals_buckets_address: out vl_logic_vector(31 downto 0); nfa_finals_buckets_datain: in vl_logic_vector(31 downto 0); nfa_finals_buckets_dataout: out vl_logic_vector(31 downto 0); nfa_finals_buckets_size: out vl_logic_vector(31 downto 0); nfa_forward_buckets_req_din: out vl_logic; nfa_forward_buckets_req_full_n: in vl_logic; nfa_forward_buckets_req_write: out vl_logic; nfa_forward_buckets_rsp_empty_n: in vl_logic; nfa_forward_buckets_rsp_read: out vl_logic; nfa_forward_buckets_address: out vl_logic_vector(31 downto 0); nfa_forward_buckets_datain: in vl_logic_vector(31 downto 0); nfa_forward_buckets_dataout: out vl_logic_vector(31 downto 0); nfa_forward_buckets_size: out vl_logic_vector(31 downto 0); nfa_symbols : in vl_logic_vector(7 downto 0); sample_buffer_req_din: out vl_logic; sample_buffer_req_full_n: in vl_logic; sample_buffer_req_write: out vl_logic; sample_buffer_rsp_empty_n: in vl_logic; sample_buffer_rsp_read: out vl_logic; sample_buffer_address: out vl_logic_vector(31 downto 0); sample_buffer_datain: in vl_logic_vector(7 downto 0); sample_buffer_dataout: out vl_logic_vector(7 downto 0); sample_buffer_size: out vl_logic_vector(31 downto 0); sample_buffer_length: in vl_logic_vector(31 downto 0); sample_length : in vl_logic_vector(15 downto 0); indices_req_din : out vl_logic; indices_req_full_n: in vl_logic; indices_req_write: out vl_logic; indices_rsp_empty_n: in vl_logic; indices_rsp_read: out vl_logic; indices_address : out vl_logic_vector(31 downto 0); indices_datain : in vl_logic_vector(55 downto 0); indices_dataout : out vl_logic_vector(55 downto 0); indices_size : out vl_logic_vector(31 downto 0); i_size : in vl_logic_vector(15 downto 0); begin_index : in vl_logic_vector(15 downto 0); begin_sample : in vl_logic_vector(15 downto 0); end_index : in vl_logic_vector(15 downto 0); end_sample : in vl_logic_vector(15 downto 0); stop_on_first : in vl_logic_vector(0 downto 0); accept : in vl_logic_vector(0 downto 0); ap_return : out vl_logic_vector(31 downto 0) ); attribute mti_svvh_generic_type : integer; attribute mti_svvh_generic_type of ap_const_logic_1 : constant is 1; attribute mti_svvh_generic_type of ap_const_logic_0 : constant is 1; attribute mti_svvh_generic_type of ap_ST_st1_fsm_0 : constant is 1; attribute mti_svvh_generic_type of ap_ST_st2_fsm_1 : constant is 1; attribute mti_svvh_generic_type of ap_ST_st3_fsm_2 : constant is 1; attribute mti_svvh_generic_type of ap_ST_st4_fsm_3 : constant is 1; attribute mti_svvh_generic_type of ap_ST_st5_fsm_4 : constant is 1; attribute mti_svvh_generic_type of ap_ST_st6_fsm_5 : constant is 1; attribute mti_svvh_generic_type of ap_ST_st7_fsm_6 : constant is 1; attribute mti_svvh_generic_type of ap_ST_st8_fsm_7 : constant is 1; attribute mti_svvh_generic_type of ap_ST_st9_fsm_8 : constant is 1; attribute mti_svvh_generic_type of ap_ST_st10_fsm_9 : constant is 1; attribute mti_svvh_generic_type of ap_ST_st11_fsm_10 : constant is 1; attribute mti_svvh_generic_type of ap_ST_st12_fsm_11 : constant is 1; attribute mti_svvh_generic_type of ap_ST_st13_fsm_12 : constant is 1; attribute mti_svvh_generic_type of ap_ST_st14_fsm_13 : constant is 1; attribute mti_svvh_generic_type of ap_ST_st15_fsm_14 : constant is 1; attribute mti_svvh_generic_type of ap_ST_st16_fsm_15 : constant is 1; attribute mti_svvh_generic_type of ap_ST_st17_fsm_16 : constant is 1; attribute mti_svvh_generic_type of ap_ST_st18_fsm_17 : constant is 1; attribute mti_svvh_generic_type of ap_ST_st19_fsm_18 : constant is 1; attribute mti_svvh_generic_type of ap_ST_st20_fsm_19 : constant is 1; attribute mti_svvh_generic_type of ap_ST_st21_fsm_20 : constant is 1; attribute mti_svvh_generic_type of ap_ST_st22_fsm_21 : constant is 1; attribute mti_svvh_generic_type of ap_ST_st23_fsm_22 : constant is 1; attribute mti_svvh_generic_type of ap_ST_st24_fsm_23 : constant is 1; attribute mti_svvh_generic_type of ap_ST_st25_fsm_24 : constant is 1; attribute mti_svvh_generic_type of ap_ST_st26_fsm_25 : constant is 1; attribute mti_svvh_generic_type of ap_ST_st27_fsm_26 : constant is 1; attribute mti_svvh_generic_type of ap_ST_st28_fsm_27 : constant is 1; attribute mti_svvh_generic_type of ap_ST_st29_fsm_28 : constant is 1; attribute mti_svvh_generic_type of ap_ST_st30_fsm_29 : constant is 1; attribute mti_svvh_generic_type of ap_ST_st31_fsm_30 : constant is 1; attribute mti_svvh_generic_type of ap_ST_st32_fsm_31 : constant is 1; attribute mti_svvh_generic_type of ap_ST_st33_fsm_32 : constant is 1; attribute mti_svvh_generic_type of ap_ST_st34_fsm_33 : constant is 1; attribute mti_svvh_generic_type of ap_ST_st35_fsm_34 : constant is 1; attribute mti_svvh_generic_type of ap_ST_st36_fsm_35 : constant is 1; attribute mti_svvh_generic_type of ap_ST_st37_fsm_36 : constant is 1; attribute mti_svvh_generic_type of ap_const_lv1_0 : constant is 1; attribute mti_svvh_generic_type of ap_const_lv16_0 : constant is 1; attribute mti_svvh_generic_type of ap_const_lv64_0 : constant is 1; attribute mti_svvh_generic_type of ap_const_lv1_1 : constant is 1; attribute mti_svvh_generic_type of ap_const_lv32_0 : constant is 1; attribute mti_svvh_generic_type of ap_const_lv2_2 : constant is 1; attribute mti_svvh_generic_type of ap_const_lv32_1 : constant is 1; attribute mti_svvh_generic_type of ap_const_lv64_1 : constant is 1; attribute mti_svvh_generic_type of ap_const_lv16_1 : constant is 1; attribute mti_svvh_generic_type of ap_const_lv5_0 : constant is 1; attribute mti_svvh_generic_type of ap_const_lv8_0 : constant is 1; attribute mti_svvh_generic_type of ap_true : constant is 1; end nfa_accept_samples_generic_hw;
lgpl-3.0
0e90068d234085e347074869fade2a8e
0.615003
2.561732
false
false
false
false
grwlf/vsim
vhdl_ct/ct00306.vhd
1
51,325
------------------------------------------------------------------------------- -- -- Copyright (c) 1989 by Intermetrics, Inc. -- All rights reserved. -- ------------------------------------------------------------------------------- -- -- TEST NAME: -- -- CT00306 -- -- AUTHOR: -- -- A. Wilmot -- -- TEST OBJECTIVES: -- -- 7.2.2 (1) -- 7.2.2 (2) -- 7.2.2 (6) -- 7.2.2 (9) -- 7.2.2 (10) -- 7.2.2 (11) -- -- DESIGN UNIT ORDERING: -- -- ENT00306(ARCH00306) -- GENERIC_STANDARD_TYPES(ARCH00306_1) -- ENT00306_Test_Bench(ARCH00306_Test_Bench) -- -- REVISION HISTORY: -- -- 21-JUL-1987 - initial revision -- -- NOTES: -- -- self-checking -- automatically generated -- use WORK.STANDARD_TYPES.all ; entity ENT00306 is generic ( i_boolean_1 : boolean := c_boolean_1 ; i_boolean_2 : boolean := c_boolean_2 ; i_bit_1 : bit := c_bit_1 ; i_bit_2 : bit := c_bit_2 ; i_severity_level_1 : severity_level := c_severity_level_1 ; i_severity_level_2 : severity_level := c_severity_level_2 ; i_character_1 : character := c_character_1 ; i_character_2 : character := c_character_2 ; i_t_enum1_1 : t_enum1 := c_t_enum1_1 ; i_t_enum1_2 : t_enum1 := c_t_enum1_2 ; i_st_enum1_1 : st_enum1 := c_st_enum1_1 ; i_st_enum1_2 : st_enum1 := c_st_enum1_2 ; i_integer_1 : integer := c_integer_1 ; i_integer_2 : integer := c_integer_2 ; i_t_int1_1 : t_int1 := c_t_int1_1 ; i_t_int1_2 : t_int1 := c_t_int1_2 ; i_st_int1_1 : st_int1 := c_st_int1_1 ; i_st_int1_2 : st_int1 := c_st_int1_2 ; i_time_1 : time := c_time_1 ; i_time_2 : time := c_time_2 ; i_t_phys1_1 : t_phys1 := c_t_phys1_1 ; i_t_phys1_2 : t_phys1 := c_t_phys1_2 ; i_st_phys1_1 : st_phys1 := c_st_phys1_1 ; i_st_phys1_2 : st_phys1 := c_st_phys1_2 ; i_real_1 : real := c_real_1 ; i_real_2 : real := c_real_2 ; i_t_real1_1 : t_real1 := c_t_real1_1 ; i_t_real1_2 : t_real1 := c_t_real1_2 ; i_st_real1_1 : st_real1 := c_st_real1_1 ; i_st_real1_2 : st_real1 := c_st_real1_2 ) ; port ( locally_static_correct : out boolean ; globally_static_correct : out boolean ; dynamic_correct : out boolean ) ; end ENT00306 ; architecture ARCH00306 of ENT00306 is begin process variable bool : boolean := true ; variable cons_correct, gen_correct, dyn_correct : boolean := true ; variable v_boolean_1 : boolean := c_boolean_1 ; variable v_boolean_2 : boolean := c_boolean_2 ; variable v_bit_1 : bit := c_bit_1 ; variable v_bit_2 : bit := c_bit_2 ; variable v_severity_level_1 : severity_level := c_severity_level_1 ; variable v_severity_level_2 : severity_level := c_severity_level_2 ; variable v_character_1 : character := c_character_1 ; variable v_character_2 : character := c_character_2 ; variable v_t_enum1_1 : t_enum1 := c_t_enum1_1 ; variable v_t_enum1_2 : t_enum1 := c_t_enum1_2 ; variable v_st_enum1_1 : st_enum1 := c_st_enum1_1 ; variable v_st_enum1_2 : st_enum1 := c_st_enum1_2 ; variable v_integer_1 : integer := c_integer_1 ; variable v_integer_2 : integer := c_integer_2 ; variable v_t_int1_1 : t_int1 := c_t_int1_1 ; variable v_t_int1_2 : t_int1 := c_t_int1_2 ; variable v_st_int1_1 : st_int1 := c_st_int1_1 ; variable v_st_int1_2 : st_int1 := c_st_int1_2 ; variable v_time_1 : time := c_time_1 ; variable v_time_2 : time := c_time_2 ; variable v_t_phys1_1 : t_phys1 := c_t_phys1_1 ; variable v_t_phys1_2 : t_phys1 := c_t_phys1_2 ; variable v_st_phys1_1 : st_phys1 := c_st_phys1_1 ; variable v_st_phys1_2 : st_phys1 := c_st_phys1_2 ; variable v_real_1 : real := c_real_1 ; variable v_real_2 : real := c_real_2 ; variable v_t_real1_1 : t_real1 := c_t_real1_1 ; variable v_t_real1_2 : t_real1 := c_t_real1_2 ; variable v_st_real1_1 : st_real1 := c_st_real1_1 ; variable v_st_real1_2 : st_real1 := c_st_real1_2 ; constant c2_boolean_1 : boolean := i_boolean_1 < i_boolean_2 and i_boolean_1 <= i_boolean_2 and i_boolean_2 <= c_boolean_2 and i_boolean_2 >= i_boolean_1 and i_boolean_1 >= c_boolean_1 and i_boolean_2 > i_boolean_1 and i_boolean_1 = c_boolean_1 and i_boolean_1 /= i_boolean_2 and not (i_boolean_1 = i_boolean_2) ; constant c2_bit_1 : boolean := i_bit_1 < i_bit_2 and i_bit_1 <= i_bit_2 and i_bit_2 <= c_bit_2 and i_bit_2 >= i_bit_1 and i_bit_1 >= c_bit_1 and i_bit_2 > i_bit_1 and i_bit_1 = c_bit_1 and i_bit_1 /= i_bit_2 and not (i_bit_1 = i_bit_2) ; constant c2_severity_level_1 : boolean := i_severity_level_1 < i_severity_level_2 and i_severity_level_1 <= i_severity_level_2 and i_severity_level_2 <= c_severity_level_2 and i_severity_level_2 >= i_severity_level_1 and i_severity_level_1 >= c_severity_level_1 and i_severity_level_2 > i_severity_level_1 and i_severity_level_1 = c_severity_level_1 and i_severity_level_1 /= i_severity_level_2 and not (i_severity_level_1 = i_severity_level_2) ; constant c2_character_1 : boolean := i_character_1 < i_character_2 and i_character_1 <= i_character_2 and i_character_2 <= c_character_2 and i_character_2 >= i_character_1 and i_character_1 >= c_character_1 and i_character_2 > i_character_1 and i_character_1 = c_character_1 and i_character_1 /= i_character_2 and not (i_character_1 = i_character_2) ; constant c2_t_enum1_1 : boolean := i_t_enum1_1 < i_t_enum1_2 and i_t_enum1_1 <= i_t_enum1_2 and i_t_enum1_2 <= c_t_enum1_2 and i_t_enum1_2 >= i_t_enum1_1 and i_t_enum1_1 >= c_t_enum1_1 and i_t_enum1_2 > i_t_enum1_1 and i_t_enum1_1 = c_t_enum1_1 and i_t_enum1_1 /= i_t_enum1_2 and not (i_t_enum1_1 = i_t_enum1_2) ; constant c2_st_enum1_1 : boolean := i_st_enum1_1 < i_st_enum1_2 and i_st_enum1_1 <= i_st_enum1_2 and i_st_enum1_2 <= c_st_enum1_2 and i_st_enum1_2 >= i_st_enum1_1 and i_st_enum1_1 >= c_st_enum1_1 and i_st_enum1_2 > i_st_enum1_1 and i_st_enum1_1 = c_st_enum1_1 and i_st_enum1_1 /= i_st_enum1_2 and not (i_st_enum1_1 = i_st_enum1_2) ; constant c2_integer_1 : boolean := i_integer_1 < i_integer_2 and i_integer_1 <= i_integer_2 and i_integer_2 <= c_integer_2 and i_integer_2 >= i_integer_1 and i_integer_1 >= c_integer_1 and i_integer_2 > i_integer_1 and i_integer_1 = c_integer_1 and i_integer_1 /= i_integer_2 and not (i_integer_1 = i_integer_2) ; constant c2_t_int1_1 : boolean := i_t_int1_1 < i_t_int1_2 and i_t_int1_1 <= i_t_int1_2 and i_t_int1_2 <= c_t_int1_2 and i_t_int1_2 >= i_t_int1_1 and i_t_int1_1 >= c_t_int1_1 and i_t_int1_2 > i_t_int1_1 and i_t_int1_1 = c_t_int1_1 and i_t_int1_1 /= i_t_int1_2 and not (i_t_int1_1 = i_t_int1_2) ; constant c2_st_int1_1 : boolean := i_st_int1_1 < i_st_int1_2 and i_st_int1_1 <= i_st_int1_2 and i_st_int1_2 <= c_st_int1_2 and i_st_int1_2 >= i_st_int1_1 and i_st_int1_1 >= c_st_int1_1 and i_st_int1_2 > i_st_int1_1 and i_st_int1_1 = c_st_int1_1 and i_st_int1_1 /= i_st_int1_2 and not (i_st_int1_1 = i_st_int1_2) ; constant c2_time_1 : boolean := i_time_1 < i_time_2 and i_time_1 <= i_time_2 and i_time_2 <= c_time_2 and i_time_2 >= i_time_1 and i_time_1 >= c_time_1 and i_time_2 > i_time_1 and i_time_1 = c_time_1 and i_time_1 /= i_time_2 and not (i_time_1 = i_time_2) ; constant c2_t_phys1_1 : boolean := i_t_phys1_1 < i_t_phys1_2 and i_t_phys1_1 <= i_t_phys1_2 and i_t_phys1_2 <= c_t_phys1_2 and i_t_phys1_2 >= i_t_phys1_1 and i_t_phys1_1 >= c_t_phys1_1 and i_t_phys1_2 > i_t_phys1_1 and i_t_phys1_1 = c_t_phys1_1 and i_t_phys1_1 /= i_t_phys1_2 and not (i_t_phys1_1 = i_t_phys1_2) ; constant c2_st_phys1_1 : boolean := i_st_phys1_1 < i_st_phys1_2 and i_st_phys1_1 <= i_st_phys1_2 and i_st_phys1_2 <= c_st_phys1_2 and i_st_phys1_2 >= i_st_phys1_1 and i_st_phys1_1 >= c_st_phys1_1 and i_st_phys1_2 > i_st_phys1_1 and i_st_phys1_1 = c_st_phys1_1 and i_st_phys1_1 /= i_st_phys1_2 and not (i_st_phys1_1 = i_st_phys1_2) ; constant c2_real_1 : boolean := i_real_1 < i_real_2 and i_real_1 <= i_real_2 and i_real_2 <= c_real_2 and i_real_2 >= i_real_1 and i_real_1 >= c_real_1 and i_real_2 > i_real_1 and i_real_1 = c_real_1 and i_real_1 /= i_real_2 and not (i_real_1 = i_real_2) ; constant c2_t_real1_1 : boolean := i_t_real1_1 < i_t_real1_2 and i_t_real1_1 <= i_t_real1_2 and i_t_real1_2 <= c_t_real1_2 and i_t_real1_2 >= i_t_real1_1 and i_t_real1_1 >= c_t_real1_1 and i_t_real1_2 > i_t_real1_1 and i_t_real1_1 = c_t_real1_1 and i_t_real1_1 /= i_t_real1_2 and not (i_t_real1_1 = i_t_real1_2) ; constant c2_st_real1_1 : boolean := i_st_real1_1 < i_st_real1_2 and i_st_real1_1 <= i_st_real1_2 and i_st_real1_2 <= c_st_real1_2 and i_st_real1_2 >= i_st_real1_1 and i_st_real1_1 >= c_st_real1_1 and i_st_real1_2 > i_st_real1_1 and i_st_real1_1 = c_st_real1_1 and i_st_real1_1 /= i_st_real1_2 and not (i_st_real1_1 = i_st_real1_2) ; begin case bool is when ( c_boolean_1 < c_boolean_2 and c_boolean_1 <= c_boolean_2 and c_boolean_2 <= c_boolean_2 and c_boolean_2 >= c_boolean_1 and c_boolean_1 >= c_boolean_1 and c_boolean_2 > c_boolean_1 and c_boolean_1 = c_boolean_1 and c_boolean_1 /= c_boolean_2 and not (c_boolean_1 = c_boolean_2) ) => cons_correct := cons_correct and true ; when others => cons_correct := false ; end case ; case bool is when ( c_bit_1 < c_bit_2 and c_bit_1 <= c_bit_2 and c_bit_2 <= c_bit_2 and c_bit_2 >= c_bit_1 and c_bit_1 >= c_bit_1 and c_bit_2 > c_bit_1 and c_bit_1 = c_bit_1 and c_bit_1 /= c_bit_2 and not (c_bit_1 = c_bit_2) ) => cons_correct := cons_correct and true ; when others => cons_correct := false ; end case ; case bool is when ( c_severity_level_1 < c_severity_level_2 and c_severity_level_1 <= c_severity_level_2 and c_severity_level_2 <= c_severity_level_2 and c_severity_level_2 >= c_severity_level_1 and c_severity_level_1 >= c_severity_level_1 and c_severity_level_2 > c_severity_level_1 and c_severity_level_1 = c_severity_level_1 and c_severity_level_1 /= c_severity_level_2 and not (c_severity_level_1 = c_severity_level_2) ) => cons_correct := cons_correct and true ; when others => cons_correct := false ; end case ; case bool is when ( c_character_1 < c_character_2 and c_character_1 <= c_character_2 and c_character_2 <= c_character_2 and c_character_2 >= c_character_1 and c_character_1 >= c_character_1 and c_character_2 > c_character_1 and c_character_1 = c_character_1 and c_character_1 /= c_character_2 and not (c_character_1 = c_character_2) ) => cons_correct := cons_correct and true ; when others => cons_correct := false ; end case ; case bool is when ( c_t_enum1_1 < c_t_enum1_2 and c_t_enum1_1 <= c_t_enum1_2 and c_t_enum1_2 <= c_t_enum1_2 and c_t_enum1_2 >= c_t_enum1_1 and c_t_enum1_1 >= c_t_enum1_1 and c_t_enum1_2 > c_t_enum1_1 and c_t_enum1_1 = c_t_enum1_1 and c_t_enum1_1 /= c_t_enum1_2 and not (c_t_enum1_1 = c_t_enum1_2) ) => cons_correct := cons_correct and true ; when others => cons_correct := false ; end case ; case bool is when ( c_st_enum1_1 < c_st_enum1_2 and c_st_enum1_1 <= c_st_enum1_2 and c_st_enum1_2 <= c_st_enum1_2 and c_st_enum1_2 >= c_st_enum1_1 and c_st_enum1_1 >= c_st_enum1_1 and c_st_enum1_2 > c_st_enum1_1 and c_st_enum1_1 = c_st_enum1_1 and c_st_enum1_1 /= c_st_enum1_2 and not (c_st_enum1_1 = c_st_enum1_2) ) => cons_correct := cons_correct and true ; when others => cons_correct := false ; end case ; case bool is when ( c_integer_1 < c_integer_2 and c_integer_1 <= c_integer_2 and c_integer_2 <= c_integer_2 and c_integer_2 >= c_integer_1 and c_integer_1 >= c_integer_1 and c_integer_2 > c_integer_1 and c_integer_1 = c_integer_1 and c_integer_1 /= c_integer_2 and not (c_integer_1 = c_integer_2) ) => cons_correct := cons_correct and true ; when others => cons_correct := false ; end case ; case bool is when ( c_t_int1_1 < c_t_int1_2 and c_t_int1_1 <= c_t_int1_2 and c_t_int1_2 <= c_t_int1_2 and c_t_int1_2 >= c_t_int1_1 and c_t_int1_1 >= c_t_int1_1 and c_t_int1_2 > c_t_int1_1 and c_t_int1_1 = c_t_int1_1 and c_t_int1_1 /= c_t_int1_2 and not (c_t_int1_1 = c_t_int1_2) ) => cons_correct := cons_correct and true ; when others => cons_correct := false ; end case ; case bool is when ( c_st_int1_1 < c_st_int1_2 and c_st_int1_1 <= c_st_int1_2 and c_st_int1_2 <= c_st_int1_2 and c_st_int1_2 >= c_st_int1_1 and c_st_int1_1 >= c_st_int1_1 and c_st_int1_2 > c_st_int1_1 and c_st_int1_1 = c_st_int1_1 and c_st_int1_1 /= c_st_int1_2 and not (c_st_int1_1 = c_st_int1_2) ) => cons_correct := cons_correct and true ; when others => cons_correct := false ; end case ; case bool is when ( c_time_1 < c_time_2 and c_time_1 <= c_time_2 and c_time_2 <= c_time_2 and c_time_2 >= c_time_1 and c_time_1 >= c_time_1 and c_time_2 > c_time_1 and c_time_1 = c_time_1 and c_time_1 /= c_time_2 and not (c_time_1 = c_time_2) ) => cons_correct := cons_correct and true ; when others => cons_correct := false ; end case ; case bool is when ( c_t_phys1_1 < c_t_phys1_2 and c_t_phys1_1 <= c_t_phys1_2 and c_t_phys1_2 <= c_t_phys1_2 and c_t_phys1_2 >= c_t_phys1_1 and c_t_phys1_1 >= c_t_phys1_1 and c_t_phys1_2 > c_t_phys1_1 and c_t_phys1_1 = c_t_phys1_1 and c_t_phys1_1 /= c_t_phys1_2 and not (c_t_phys1_1 = c_t_phys1_2) ) => cons_correct := cons_correct and true ; when others => cons_correct := false ; end case ; case bool is when ( c_st_phys1_1 < c_st_phys1_2 and c_st_phys1_1 <= c_st_phys1_2 and c_st_phys1_2 <= c_st_phys1_2 and c_st_phys1_2 >= c_st_phys1_1 and c_st_phys1_1 >= c_st_phys1_1 and c_st_phys1_2 > c_st_phys1_1 and c_st_phys1_1 = c_st_phys1_1 and c_st_phys1_1 /= c_st_phys1_2 and not (c_st_phys1_1 = c_st_phys1_2) ) => cons_correct := cons_correct and true ; when others => cons_correct := false ; end case ; case bool is when ( c_real_1 < c_real_2 and c_real_1 <= c_real_2 and c_real_2 <= c_real_2 and c_real_2 >= c_real_1 and c_real_1 >= c_real_1 and c_real_2 > c_real_1 and c_real_1 = c_real_1 and c_real_1 /= c_real_2 and not (c_real_1 = c_real_2) ) => cons_correct := cons_correct and true ; when others => cons_correct := false ; end case ; case bool is when ( c_t_real1_1 < c_t_real1_2 and c_t_real1_1 <= c_t_real1_2 and c_t_real1_2 <= c_t_real1_2 and c_t_real1_2 >= c_t_real1_1 and c_t_real1_1 >= c_t_real1_1 and c_t_real1_2 > c_t_real1_1 and c_t_real1_1 = c_t_real1_1 and c_t_real1_1 /= c_t_real1_2 and not (c_t_real1_1 = c_t_real1_2) ) => cons_correct := cons_correct and true ; when others => cons_correct := false ; end case ; case bool is when ( c_st_real1_1 < c_st_real1_2 and c_st_real1_1 <= c_st_real1_2 and c_st_real1_2 <= c_st_real1_2 and c_st_real1_2 >= c_st_real1_1 and c_st_real1_1 >= c_st_real1_1 and c_st_real1_2 > c_st_real1_1 and c_st_real1_1 = c_st_real1_1 and c_st_real1_1 /= c_st_real1_2 and not (c_st_real1_1 = c_st_real1_2) ) => cons_correct := cons_correct and true ; when others => cons_correct := false ; end case ; gen_correct := gen_correct and c2_boolean_1 = true ; gen_correct := gen_correct and c2_bit_1 = true ; gen_correct := gen_correct and c2_severity_level_1 = true ; gen_correct := gen_correct and c2_character_1 = true ; gen_correct := gen_correct and c2_t_enum1_1 = true ; gen_correct := gen_correct and c2_st_enum1_1 = true ; gen_correct := gen_correct and c2_integer_1 = true ; gen_correct := gen_correct and c2_t_int1_1 = true ; gen_correct := gen_correct and c2_st_int1_1 = true ; gen_correct := gen_correct and c2_time_1 = true ; gen_correct := gen_correct and c2_t_phys1_1 = true ; gen_correct := gen_correct and c2_st_phys1_1 = true ; gen_correct := gen_correct and c2_real_1 = true ; gen_correct := gen_correct and c2_t_real1_1 = true ; gen_correct := gen_correct and c2_st_real1_1 = true ; dyn_correct := dyn_correct and v_boolean_1 < v_boolean_2 and v_boolean_1 <= v_boolean_2 and v_boolean_2 <= c_boolean_2 and v_boolean_2 >= v_boolean_1 and v_boolean_1 >= c_boolean_1 and v_boolean_2 > v_boolean_1 and v_boolean_1 = c_boolean_1 and v_boolean_1 /= v_boolean_2 and not (v_boolean_1 = v_boolean_2) ; dyn_correct := dyn_correct and v_bit_1 < v_bit_2 and v_bit_1 <= v_bit_2 and v_bit_2 <= c_bit_2 and v_bit_2 >= v_bit_1 and v_bit_1 >= c_bit_1 and v_bit_2 > v_bit_1 and v_bit_1 = c_bit_1 and v_bit_1 /= v_bit_2 and not (v_bit_1 = v_bit_2) ; dyn_correct := dyn_correct and v_severity_level_1 < v_severity_level_2 and v_severity_level_1 <= v_severity_level_2 and v_severity_level_2 <= c_severity_level_2 and v_severity_level_2 >= v_severity_level_1 and v_severity_level_1 >= c_severity_level_1 and v_severity_level_2 > v_severity_level_1 and v_severity_level_1 = c_severity_level_1 and v_severity_level_1 /= v_severity_level_2 and not (v_severity_level_1 = v_severity_level_2) ; dyn_correct := dyn_correct and v_character_1 < v_character_2 and v_character_1 <= v_character_2 and v_character_2 <= c_character_2 and v_character_2 >= v_character_1 and v_character_1 >= c_character_1 and v_character_2 > v_character_1 and v_character_1 = c_character_1 and v_character_1 /= v_character_2 and not (v_character_1 = v_character_2) ; dyn_correct := dyn_correct and v_t_enum1_1 < v_t_enum1_2 and v_t_enum1_1 <= v_t_enum1_2 and v_t_enum1_2 <= c_t_enum1_2 and v_t_enum1_2 >= v_t_enum1_1 and v_t_enum1_1 >= c_t_enum1_1 and v_t_enum1_2 > v_t_enum1_1 and v_t_enum1_1 = c_t_enum1_1 and v_t_enum1_1 /= v_t_enum1_2 and not (v_t_enum1_1 = v_t_enum1_2) ; dyn_correct := dyn_correct and v_st_enum1_1 < v_st_enum1_2 and v_st_enum1_1 <= v_st_enum1_2 and v_st_enum1_2 <= c_st_enum1_2 and v_st_enum1_2 >= v_st_enum1_1 and v_st_enum1_1 >= c_st_enum1_1 and v_st_enum1_2 > v_st_enum1_1 and v_st_enum1_1 = c_st_enum1_1 and v_st_enum1_1 /= v_st_enum1_2 and not (v_st_enum1_1 = v_st_enum1_2) ; dyn_correct := dyn_correct and v_integer_1 < v_integer_2 and v_integer_1 <= v_integer_2 and v_integer_2 <= c_integer_2 and v_integer_2 >= v_integer_1 and v_integer_1 >= c_integer_1 and v_integer_2 > v_integer_1 and v_integer_1 = c_integer_1 and v_integer_1 /= v_integer_2 and not (v_integer_1 = v_integer_2) ; dyn_correct := dyn_correct and v_t_int1_1 < v_t_int1_2 and v_t_int1_1 <= v_t_int1_2 and v_t_int1_2 <= c_t_int1_2 and v_t_int1_2 >= v_t_int1_1 and v_t_int1_1 >= c_t_int1_1 and v_t_int1_2 > v_t_int1_1 and v_t_int1_1 = c_t_int1_1 and v_t_int1_1 /= v_t_int1_2 and not (v_t_int1_1 = v_t_int1_2) ; dyn_correct := dyn_correct and v_st_int1_1 < v_st_int1_2 and v_st_int1_1 <= v_st_int1_2 and v_st_int1_2 <= c_st_int1_2 and v_st_int1_2 >= v_st_int1_1 and v_st_int1_1 >= c_st_int1_1 and v_st_int1_2 > v_st_int1_1 and v_st_int1_1 = c_st_int1_1 and v_st_int1_1 /= v_st_int1_2 and not (v_st_int1_1 = v_st_int1_2) ; dyn_correct := dyn_correct and v_time_1 < v_time_2 and v_time_1 <= v_time_2 and v_time_2 <= c_time_2 and v_time_2 >= v_time_1 and v_time_1 >= c_time_1 and v_time_2 > v_time_1 and v_time_1 = c_time_1 and v_time_1 /= v_time_2 and not (v_time_1 = v_time_2) ; dyn_correct := dyn_correct and v_t_phys1_1 < v_t_phys1_2 and v_t_phys1_1 <= v_t_phys1_2 and v_t_phys1_2 <= c_t_phys1_2 and v_t_phys1_2 >= v_t_phys1_1 and v_t_phys1_1 >= c_t_phys1_1 and v_t_phys1_2 > v_t_phys1_1 and v_t_phys1_1 = c_t_phys1_1 and v_t_phys1_1 /= v_t_phys1_2 and not (v_t_phys1_1 = v_t_phys1_2) ; dyn_correct := dyn_correct and v_st_phys1_1 < v_st_phys1_2 and v_st_phys1_1 <= v_st_phys1_2 and v_st_phys1_2 <= c_st_phys1_2 and v_st_phys1_2 >= v_st_phys1_1 and v_st_phys1_1 >= c_st_phys1_1 and v_st_phys1_2 > v_st_phys1_1 and v_st_phys1_1 = c_st_phys1_1 and v_st_phys1_1 /= v_st_phys1_2 and not (v_st_phys1_1 = v_st_phys1_2) ; dyn_correct := dyn_correct and v_real_1 < v_real_2 and v_real_1 <= v_real_2 and v_real_2 <= c_real_2 and v_real_2 >= v_real_1 and v_real_1 >= c_real_1 and v_real_2 > v_real_1 and v_real_1 = c_real_1 and v_real_1 /= v_real_2 and not (v_real_1 = v_real_2) ; dyn_correct := dyn_correct and v_t_real1_1 < v_t_real1_2 and v_t_real1_1 <= v_t_real1_2 and v_t_real1_2 <= c_t_real1_2 and v_t_real1_2 >= v_t_real1_1 and v_t_real1_1 >= c_t_real1_1 and v_t_real1_2 > v_t_real1_1 and v_t_real1_1 = c_t_real1_1 and v_t_real1_1 /= v_t_real1_2 and not (v_t_real1_1 = v_t_real1_2) ; dyn_correct := dyn_correct and v_st_real1_1 < v_st_real1_2 and v_st_real1_1 <= v_st_real1_2 and v_st_real1_2 <= c_st_real1_2 and v_st_real1_2 >= v_st_real1_1 and v_st_real1_1 >= c_st_real1_1 and v_st_real1_2 > v_st_real1_1 and v_st_real1_1 = c_st_real1_1 and v_st_real1_1 /= v_st_real1_2 and not (v_st_real1_1 = v_st_real1_2) ; locally_static_correct <= cons_correct ; globally_static_correct <= gen_correct ; dynamic_correct <= dyn_correct ; wait; end process ; end ARCH00306 ; architecture ARCH00306_1 of GENERIC_STANDARD_TYPES is begin B : block generic ( i_boolean_1 : boolean := c_boolean_1 ; i_boolean_2 : boolean := c_boolean_2 ; i_bit_1 : bit := c_bit_1 ; i_bit_2 : bit := c_bit_2 ; i_severity_level_1 : severity_level := c_severity_level_1 ; i_severity_level_2 : severity_level := c_severity_level_2 ; i_character_1 : character := c_character_1 ; i_character_2 : character := c_character_2 ; i_t_enum1_1 : t_enum1 := c_t_enum1_1 ; i_t_enum1_2 : t_enum1 := c_t_enum1_2 ; i_st_enum1_1 : st_enum1 := c_st_enum1_1 ; i_st_enum1_2 : st_enum1 := c_st_enum1_2 ; i_integer_1 : integer := c_integer_1 ; i_integer_2 : integer := c_integer_2 ; i_t_int1_1 : t_int1 := c_t_int1_1 ; i_t_int1_2 : t_int1 := c_t_int1_2 ; i_st_int1_1 : st_int1 := c_st_int1_1 ; i_st_int1_2 : st_int1 := c_st_int1_2 ; i_time_1 : time := c_time_1 ; i_time_2 : time := c_time_2 ; i_t_phys1_1 : t_phys1 := c_t_phys1_1 ; i_t_phys1_2 : t_phys1 := c_t_phys1_2 ; i_st_phys1_1 : st_phys1 := c_st_phys1_1 ; i_st_phys1_2 : st_phys1 := c_st_phys1_2 ; i_real_1 : real := c_real_1 ; i_real_2 : real := c_real_2 ; i_t_real1_1 : t_real1 := c_t_real1_1 ; i_t_real1_2 : t_real1 := c_t_real1_2 ; i_st_real1_1 : st_real1 := c_st_real1_1 ; i_st_real1_2 : st_real1 := c_st_real1_2 ) ; begin process variable bool : boolean := true ; variable gen_correct, dyn_correct : boolean := true ; variable v_boolean_1 : boolean := c_boolean_1 ; variable v_boolean_2 : boolean := c_boolean_2 ; variable v_bit_1 : bit := c_bit_1 ; variable v_bit_2 : bit := c_bit_2 ; variable v_severity_level_1 : severity_level := c_severity_level_1 ; variable v_severity_level_2 : severity_level := c_severity_level_2 ; variable v_character_1 : character := c_character_1 ; variable v_character_2 : character := c_character_2 ; variable v_t_enum1_1 : t_enum1 := c_t_enum1_1 ; variable v_t_enum1_2 : t_enum1 := c_t_enum1_2 ; variable v_st_enum1_1 : st_enum1 := c_st_enum1_1 ; variable v_st_enum1_2 : st_enum1 := c_st_enum1_2 ; variable v_integer_1 : integer := c_integer_1 ; variable v_integer_2 : integer := c_integer_2 ; variable v_t_int1_1 : t_int1 := c_t_int1_1 ; variable v_t_int1_2 : t_int1 := c_t_int1_2 ; variable v_st_int1_1 : st_int1 := c_st_int1_1 ; variable v_st_int1_2 : st_int1 := c_st_int1_2 ; variable v_time_1 : time := c_time_1 ; variable v_time_2 : time := c_time_2 ; variable v_t_phys1_1 : t_phys1 := c_t_phys1_1 ; variable v_t_phys1_2 : t_phys1 := c_t_phys1_2 ; variable v_st_phys1_1 : st_phys1 := c_st_phys1_1 ; variable v_st_phys1_2 : st_phys1 := c_st_phys1_2 ; variable v_real_1 : real := c_real_1 ; variable v_real_2 : real := c_real_2 ; variable v_t_real1_1 : t_real1 := c_t_real1_1 ; variable v_t_real1_2 : t_real1 := c_t_real1_2 ; variable v_st_real1_1 : st_real1 := c_st_real1_1 ; variable v_st_real1_2 : st_real1 := c_st_real1_2 ; constant c2_boolean_1 : boolean := i_boolean_1 < i_boolean_2 and i_boolean_1 <= i_boolean_2 and i_boolean_2 <= c_boolean_2 and i_boolean_2 >= i_boolean_1 and i_boolean_1 >= c_boolean_1 and i_boolean_2 > i_boolean_1 and i_boolean_1 = c_boolean_1 and i_boolean_1 /= i_boolean_2 and not (i_boolean_1 = i_boolean_2) ; constant c2_bit_1 : boolean := i_bit_1 < i_bit_2 and i_bit_1 <= i_bit_2 and i_bit_2 <= c_bit_2 and i_bit_2 >= i_bit_1 and i_bit_1 >= c_bit_1 and i_bit_2 > i_bit_1 and i_bit_1 = c_bit_1 and i_bit_1 /= i_bit_2 and not (i_bit_1 = i_bit_2) ; constant c2_severity_level_1 : boolean := i_severity_level_1 < i_severity_level_2 and i_severity_level_1 <= i_severity_level_2 and i_severity_level_2 <= c_severity_level_2 and i_severity_level_2 >= i_severity_level_1 and i_severity_level_1 >= c_severity_level_1 and i_severity_level_2 > i_severity_level_1 and i_severity_level_1 = c_severity_level_1 and i_severity_level_1 /= i_severity_level_2 and not (i_severity_level_1 = i_severity_level_2) ; constant c2_character_1 : boolean := i_character_1 < i_character_2 and i_character_1 <= i_character_2 and i_character_2 <= c_character_2 and i_character_2 >= i_character_1 and i_character_1 >= c_character_1 and i_character_2 > i_character_1 and i_character_1 = c_character_1 and i_character_1 /= i_character_2 and not (i_character_1 = i_character_2) ; constant c2_t_enum1_1 : boolean := i_t_enum1_1 < i_t_enum1_2 and i_t_enum1_1 <= i_t_enum1_2 and i_t_enum1_2 <= c_t_enum1_2 and i_t_enum1_2 >= i_t_enum1_1 and i_t_enum1_1 >= c_t_enum1_1 and i_t_enum1_2 > i_t_enum1_1 and i_t_enum1_1 = c_t_enum1_1 and i_t_enum1_1 /= i_t_enum1_2 and not (i_t_enum1_1 = i_t_enum1_2) ; constant c2_st_enum1_1 : boolean := i_st_enum1_1 < i_st_enum1_2 and i_st_enum1_1 <= i_st_enum1_2 and i_st_enum1_2 <= c_st_enum1_2 and i_st_enum1_2 >= i_st_enum1_1 and i_st_enum1_1 >= c_st_enum1_1 and i_st_enum1_2 > i_st_enum1_1 and i_st_enum1_1 = c_st_enum1_1 and i_st_enum1_1 /= i_st_enum1_2 and not (i_st_enum1_1 = i_st_enum1_2) ; constant c2_integer_1 : boolean := i_integer_1 < i_integer_2 and i_integer_1 <= i_integer_2 and i_integer_2 <= c_integer_2 and i_integer_2 >= i_integer_1 and i_integer_1 >= c_integer_1 and i_integer_2 > i_integer_1 and i_integer_1 = c_integer_1 and i_integer_1 /= i_integer_2 and not (i_integer_1 = i_integer_2) ; constant c2_t_int1_1 : boolean := i_t_int1_1 < i_t_int1_2 and i_t_int1_1 <= i_t_int1_2 and i_t_int1_2 <= c_t_int1_2 and i_t_int1_2 >= i_t_int1_1 and i_t_int1_1 >= c_t_int1_1 and i_t_int1_2 > i_t_int1_1 and i_t_int1_1 = c_t_int1_1 and i_t_int1_1 /= i_t_int1_2 and not (i_t_int1_1 = i_t_int1_2) ; constant c2_st_int1_1 : boolean := i_st_int1_1 < i_st_int1_2 and i_st_int1_1 <= i_st_int1_2 and i_st_int1_2 <= c_st_int1_2 and i_st_int1_2 >= i_st_int1_1 and i_st_int1_1 >= c_st_int1_1 and i_st_int1_2 > i_st_int1_1 and i_st_int1_1 = c_st_int1_1 and i_st_int1_1 /= i_st_int1_2 and not (i_st_int1_1 = i_st_int1_2) ; constant c2_time_1 : boolean := i_time_1 < i_time_2 and i_time_1 <= i_time_2 and i_time_2 <= c_time_2 and i_time_2 >= i_time_1 and i_time_1 >= c_time_1 and i_time_2 > i_time_1 and i_time_1 = c_time_1 and i_time_1 /= i_time_2 and not (i_time_1 = i_time_2) ; constant c2_t_phys1_1 : boolean := i_t_phys1_1 < i_t_phys1_2 and i_t_phys1_1 <= i_t_phys1_2 and i_t_phys1_2 <= c_t_phys1_2 and i_t_phys1_2 >= i_t_phys1_1 and i_t_phys1_1 >= c_t_phys1_1 and i_t_phys1_2 > i_t_phys1_1 and i_t_phys1_1 = c_t_phys1_1 and i_t_phys1_1 /= i_t_phys1_2 and not (i_t_phys1_1 = i_t_phys1_2) ; constant c2_st_phys1_1 : boolean := i_st_phys1_1 < i_st_phys1_2 and i_st_phys1_1 <= i_st_phys1_2 and i_st_phys1_2 <= c_st_phys1_2 and i_st_phys1_2 >= i_st_phys1_1 and i_st_phys1_1 >= c_st_phys1_1 and i_st_phys1_2 > i_st_phys1_1 and i_st_phys1_1 = c_st_phys1_1 and i_st_phys1_1 /= i_st_phys1_2 and not (i_st_phys1_1 = i_st_phys1_2) ; constant c2_real_1 : boolean := i_real_1 < i_real_2 and i_real_1 <= i_real_2 and i_real_2 <= c_real_2 and i_real_2 >= i_real_1 and i_real_1 >= c_real_1 and i_real_2 > i_real_1 and i_real_1 = c_real_1 and i_real_1 /= i_real_2 and not (i_real_1 = i_real_2) ; constant c2_t_real1_1 : boolean := i_t_real1_1 < i_t_real1_2 and i_t_real1_1 <= i_t_real1_2 and i_t_real1_2 <= c_t_real1_2 and i_t_real1_2 >= i_t_real1_1 and i_t_real1_1 >= c_t_real1_1 and i_t_real1_2 > i_t_real1_1 and i_t_real1_1 = c_t_real1_1 and i_t_real1_1 /= i_t_real1_2 and not (i_t_real1_1 = i_t_real1_2) ; constant c2_st_real1_1 : boolean := i_st_real1_1 < i_st_real1_2 and i_st_real1_1 <= i_st_real1_2 and i_st_real1_2 <= c_st_real1_2 and i_st_real1_2 >= i_st_real1_1 and i_st_real1_1 >= c_st_real1_1 and i_st_real1_2 > i_st_real1_1 and i_st_real1_1 = c_st_real1_1 and i_st_real1_1 /= i_st_real1_2 and not (i_st_real1_1 = i_st_real1_2) ; begin dyn_correct := dyn_correct and v_boolean_1 < v_boolean_2 and v_boolean_1 <= v_boolean_2 and v_boolean_2 <= c_boolean_2 and v_boolean_2 >= v_boolean_1 and v_boolean_1 >= c_boolean_1 and v_boolean_2 > v_boolean_1 and v_boolean_1 = c_boolean_1 and v_boolean_1 /= v_boolean_2 and not (v_boolean_1 = v_boolean_2) ; dyn_correct := dyn_correct and v_bit_1 < v_bit_2 and v_bit_1 <= v_bit_2 and v_bit_2 <= c_bit_2 and v_bit_2 >= v_bit_1 and v_bit_1 >= c_bit_1 and v_bit_2 > v_bit_1 and v_bit_1 = c_bit_1 and v_bit_1 /= v_bit_2 and not (v_bit_1 = v_bit_2) ; dyn_correct := dyn_correct and v_severity_level_1 < v_severity_level_2 and v_severity_level_1 <= v_severity_level_2 and v_severity_level_2 <= c_severity_level_2 and v_severity_level_2 >= v_severity_level_1 and v_severity_level_1 >= c_severity_level_1 and v_severity_level_2 > v_severity_level_1 and v_severity_level_1 = c_severity_level_1 and v_severity_level_1 /= v_severity_level_2 and not (v_severity_level_1 = v_severity_level_2) ; dyn_correct := dyn_correct and v_character_1 < v_character_2 and v_character_1 <= v_character_2 and v_character_2 <= c_character_2 and v_character_2 >= v_character_1 and v_character_1 >= c_character_1 and v_character_2 > v_character_1 and v_character_1 = c_character_1 and v_character_1 /= v_character_2 and not (v_character_1 = v_character_2) ; dyn_correct := dyn_correct and v_t_enum1_1 < v_t_enum1_2 and v_t_enum1_1 <= v_t_enum1_2 and v_t_enum1_2 <= c_t_enum1_2 and v_t_enum1_2 >= v_t_enum1_1 and v_t_enum1_1 >= c_t_enum1_1 and v_t_enum1_2 > v_t_enum1_1 and v_t_enum1_1 = c_t_enum1_1 and v_t_enum1_1 /= v_t_enum1_2 and not (v_t_enum1_1 = v_t_enum1_2) ; dyn_correct := dyn_correct and v_st_enum1_1 < v_st_enum1_2 and v_st_enum1_1 <= v_st_enum1_2 and v_st_enum1_2 <= c_st_enum1_2 and v_st_enum1_2 >= v_st_enum1_1 and v_st_enum1_1 >= c_st_enum1_1 and v_st_enum1_2 > v_st_enum1_1 and v_st_enum1_1 = c_st_enum1_1 and v_st_enum1_1 /= v_st_enum1_2 and not (v_st_enum1_1 = v_st_enum1_2) ; dyn_correct := dyn_correct and v_integer_1 < v_integer_2 and v_integer_1 <= v_integer_2 and v_integer_2 <= c_integer_2 and v_integer_2 >= v_integer_1 and v_integer_1 >= c_integer_1 and v_integer_2 > v_integer_1 and v_integer_1 = c_integer_1 and v_integer_1 /= v_integer_2 and not (v_integer_1 = v_integer_2) ; dyn_correct := dyn_correct and v_t_int1_1 < v_t_int1_2 and v_t_int1_1 <= v_t_int1_2 and v_t_int1_2 <= c_t_int1_2 and v_t_int1_2 >= v_t_int1_1 and v_t_int1_1 >= c_t_int1_1 and v_t_int1_2 > v_t_int1_1 and v_t_int1_1 = c_t_int1_1 and v_t_int1_1 /= v_t_int1_2 and not (v_t_int1_1 = v_t_int1_2) ; dyn_correct := dyn_correct and v_st_int1_1 < v_st_int1_2 and v_st_int1_1 <= v_st_int1_2 and v_st_int1_2 <= c_st_int1_2 and v_st_int1_2 >= v_st_int1_1 and v_st_int1_1 >= c_st_int1_1 and v_st_int1_2 > v_st_int1_1 and v_st_int1_1 = c_st_int1_1 and v_st_int1_1 /= v_st_int1_2 and not (v_st_int1_1 = v_st_int1_2) ; dyn_correct := dyn_correct and v_time_1 < v_time_2 and v_time_1 <= v_time_2 and v_time_2 <= c_time_2 and v_time_2 >= v_time_1 and v_time_1 >= c_time_1 and v_time_2 > v_time_1 and v_time_1 = c_time_1 and v_time_1 /= v_time_2 and not (v_time_1 = v_time_2) ; dyn_correct := dyn_correct and v_t_phys1_1 < v_t_phys1_2 and v_t_phys1_1 <= v_t_phys1_2 and v_t_phys1_2 <= c_t_phys1_2 and v_t_phys1_2 >= v_t_phys1_1 and v_t_phys1_1 >= c_t_phys1_1 and v_t_phys1_2 > v_t_phys1_1 and v_t_phys1_1 = c_t_phys1_1 and v_t_phys1_1 /= v_t_phys1_2 and not (v_t_phys1_1 = v_t_phys1_2) ; dyn_correct := dyn_correct and v_st_phys1_1 < v_st_phys1_2 and v_st_phys1_1 <= v_st_phys1_2 and v_st_phys1_2 <= c_st_phys1_2 and v_st_phys1_2 >= v_st_phys1_1 and v_st_phys1_1 >= c_st_phys1_1 and v_st_phys1_2 > v_st_phys1_1 and v_st_phys1_1 = c_st_phys1_1 and v_st_phys1_1 /= v_st_phys1_2 and not (v_st_phys1_1 = v_st_phys1_2) ; dyn_correct := dyn_correct and v_real_1 < v_real_2 and v_real_1 <= v_real_2 and v_real_2 <= c_real_2 and v_real_2 >= v_real_1 and v_real_1 >= c_real_1 and v_real_2 > v_real_1 and v_real_1 = c_real_1 and v_real_1 /= v_real_2 and not (v_real_1 = v_real_2) ; dyn_correct := dyn_correct and v_t_real1_1 < v_t_real1_2 and v_t_real1_1 <= v_t_real1_2 and v_t_real1_2 <= c_t_real1_2 and v_t_real1_2 >= v_t_real1_1 and v_t_real1_1 >= c_t_real1_1 and v_t_real1_2 > v_t_real1_1 and v_t_real1_1 = c_t_real1_1 and v_t_real1_1 /= v_t_real1_2 and not (v_t_real1_1 = v_t_real1_2) ; dyn_correct := dyn_correct and v_st_real1_1 < v_st_real1_2 and v_st_real1_1 <= v_st_real1_2 and v_st_real1_2 <= c_st_real1_2 and v_st_real1_2 >= v_st_real1_1 and v_st_real1_1 >= c_st_real1_1 and v_st_real1_2 > v_st_real1_1 and v_st_real1_1 = c_st_real1_1 and v_st_real1_1 /= v_st_real1_2 and not (v_st_real1_1 = v_st_real1_2) ; if gen_correct and dyn_correct then work.standard_types.test_report ( "ARCH&(TEST_NUM)" , "Relational operators are correctly predefined" & " for generically sized types" , true ) ; else work.standard_types.test_report ( "ARCH&(TEST_NUM)" , "Relational operators are correctly predefined" & " for generically sized types" , false ) ; end if ; wait; end process ; end block ; end ARCH00306_1 ; use WORK.STANDARD_TYPES.all ; entity ENT00306_Test_Bench is end ENT00306_Test_Bench ; architecture ARCH00306_Test_Bench of ENT00306_Test_Bench is begin L1: block signal locally_static_correct, globally_static_correct, dynamic_correct : boolean := false ; component UUT end component ; component UUT_1 port ( locally_static_correct, globally_static_correct, dynamic_correct : out boolean ) ; end component ; for CIS2 : UUT_1 use entity WORK.ENT00306 ( ARCH00306 ) ; for CIS1 : UUT use entity WORK.GENERIC_STANDARD_TYPES ( ARCH00306_1 ) ; begin CIS2 : UUT_1 port map ( locally_static_correct, globally_static_correct, dynamic_correct ) ; CIS1 : UUT ; process ( locally_static_correct, globally_static_correct, dynamic_correct ) begin if locally_static_correct and globally_static_correct and dynamic_correct then test_report ( "ARCH&(TEST_NUM)" , "Relational operators are correctly predefined" & " for types" , true ) ; end if ; end process ; end block L1 ; end ARCH00306_Test_Bench ;
gpl-3.0
16d577893bde5772863a466d04e12b9a
0.42303
3.147614
false
false
false
false
dcliche/mdsynth
rtl/test_benches/channel_tb/src/div_by_12.vhd
1
3,671
-- MDSynth Sound Chip -- -- Copyright (c) 2012, Meldora Inc. -- All rights reserved. -- -- Redistribution and use in source and binary forms, with or without modification, are permitted provided that the -- following conditions are met: -- -- * Redistributions of source code must retain the above copyright notice, this list of conditions and the -- following disclaimer. -- * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the -- following disclaimer in the documentation and/or other materials provided with the distribution. -- -- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, -- INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -- DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -- SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR -- SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -- WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE -- USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -- -- Based on the Music Box example at www.fpga4fun.com -- library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.NUMERIC_STD.ALL; entity div_by_12 is Port ( numerator: in unsigned(6 downto 0); quotient: out unsigned(3 downto 0); remain: out unsigned(3 downto 0)); end div_by_12; architecture div_by_12_arch of div_by_12 is signal r: unsigned(1 downto 0); begin -- We divide by 3 on the remaining bits process (numerator(6 downto 2)) begin case numerator(6 downto 2) is when "00000" => quotient <= "0000"; r <= "00"; when "00001" => quotient <= "0000"; r <= "01"; when "00010" => quotient <= "0000"; r <= "10"; when "00011" => quotient <= "0001"; r <= "00"; when "00100" => quotient <= "0001"; r <= "01"; when "00101" => quotient <= "0001"; r <= "10"; when "00110" => quotient <= "0010"; r <= "00"; when "00111" => quotient <= "0010"; r <= "01"; when "01000" => quotient <= "0010"; r <= "10"; when "01001" => quotient <= "0011"; r <= "00"; when "01010" => quotient <= "0011"; r <= "01"; when "01011" => quotient <= "0011"; r <= "10"; when "01100" => quotient <= "0100"; r <= "00"; when "01101" => quotient <= "0100"; r <= "01"; when "01110" => quotient <= "0100"; r <= "10"; when "01111" => quotient <= "0101"; r <= "00"; when "10000" => quotient <= "0101"; r <= "01"; when "10001" => quotient <= "0101"; r <= "10"; when "10010" => quotient <= "0110"; r <= "00"; when "10011" => quotient <= "0110"; r <= "01"; when "10100" => quotient <= "0110"; r <= "10"; when "10101" => quotient <= "0111"; r <= "00"; when "10110" => quotient <= "0111"; r <= "01"; when "10111" => quotient <= "0111"; r <= "10"; when "11000" => quotient <= "1000"; r <= "00"; when "11001" => quotient <= "1000"; r <= "01"; when "11010" => quotient <= "1000"; r <= "10"; when "11011" => quotient <= "1001"; r <= "00"; when "11100" => quotient <= "1001"; r <= "01"; when "11101" => quotient <= "1001"; r <= "10"; when "11110" => quotient <= "1010"; r <= "00"; when "11111" => quotient <= "1010"; r <= "01"; when others => quotient <= "0000"; r <= "00"; -- Should not happen end case; end process; remain <= r(1) & r(0) & numerator(1 downto 0); end div_by_12_arch;
gpl-3.0
206fc09cde93101ca53a4b85cfbaf658
0.620539
3.489544
false
false
false
false
grwlf/vsim
vhdl_ct/ct00519.vhd
1
10,055
------------------------------------------------------------------------------- -- -- Copyright (c) 1989 by Intermetrics, Inc. -- All rights reserved. -- ------------------------------------------------------------------------------- -- -- TEST NAME: -- -- CT00519 -- -- AUTHOR: -- -- G. Tominovich -- -- TEST OBJECTIVES: -- -- 10.3 (1) -- 10.3 (2) -- -- DESIGN UNIT ORDERING: -- -- ENT00519_1(ARCH00519_1) -- ENT00519(ARCH00519) -- ENT00519_Test_Bench(ARCH00519_Test_Bench) -- -- REVISION HISTORY: -- -- 11-AUG-1987 - initial revision -- 28-NOV-1989 - (ESL) change files to be of mode out -- -- NOTES: -- -- self-checking -- -- use WORK.STANDARD_TYPES.all ; entity ENT00519_1 is generic ( G : boolean := false ) ; port ( P : boolean := false ) ; end ENT00519_1 ; architecture ARCH00519_1 of ENT00519_1 is begin process begin test_report ( "ARCH00519" , "Declarative region direct visibility test"& "For Component declaration/instantiation" , P and G ) ; wait ; end process ; end ARCH00519_1 ; use WORK.STANDARD_TYPES.all ; entity ENT00519 is generic ( EntGeneric : boolean := false ) ; port ( EntPort : boolean := false ) ; function To_Boolean ( p : bit ) return boolean is begin case p is when '0' => return false ; when '1' => return true ; end case ; end To_Boolean ; subtype EntSubtype is Bit_Vector (1 to 3) ; type EntType is record f1 : boolean ; f2 : EntSubtype ; end record ; constant EntCons : EntType := (f1 => EntGeneric, f2 => EntSubtype'(others => '1')) ; signal EntSig : EntSubtype := ('0', EntCons.f2(2), '0') ; alias EntAlias : bit is EntSig(2) ; type EntFileType is file of boolean ; file EntFile : EntFileType is out "ct00519.dat"; attribute EntAttr : boolean ; attribute EntAttr of EntLabel : label is EntCons.f1 ; procedure EntProc2 (parm1 : boolean) ; procedure EntProc (parm1 : boolean) is subtype SubpSubtype is EntSubtype ; type SubpType is record f1 : boolean ; f2 : SubpSubtype ; end record ; constant SubpCons : EntType := (f1 => EntGeneric, f2 => EntCons.f2 ) ; variable SubpVar : SubpSubtype := SubpCons.f2; alias SubpAlias : bit is SubpVar(2) ; file SubpFile : EntFileType is out "ct00519.dat"; attribute EntAttr of SubpLabel : label is EntCons.f1 ; variable correct : boolean ; begin correct := EntGeneric and EntPort and EntCons.f1 and (EntCons.f2 = EntSubtype'(others => '1')) and (EntSig(2) = EntAlias) and EntLabel'EntAttr and (SubpCons = EntCons) and (SubpVar(2) = SubpAlias) and SubpLabel'Entattr ; test_report ( "ENT00519.EntProc" , "Declarative region direct visibility test" , correct ) ; if parm1 then EntProc (Not parm1) ; end if ; SubpLabel : while True loop exit; end loop; end EntProc ; begin EntLabel : process begin wait; end process; end ENT00519 ; architecture ARCH00519 of ENT00519 is component ArchComp generic ( G : boolean ) ; port ( P : boolean ) ; end component ; for CIS1 : ArchComp use entity WORK.ENT00519_1 ( ARCH00519_1 ); subtype ArchSubtype is EntSubtype ; type ArchType is record f1 : boolean ; f2 : ArchSubtype ; end record ; constant ArchCons : ArchType := (f1 => EntGeneric, f2 => EntCons.f2) ; signal ArchSig : ArchSubtype := ('0', ArchCons.f2(2), '0') ; alias ArchAlias : bit is ArchSig(2) ; file ArchFile : EntFileType is out "ct00519.dat"; constant ArchLabel : integer := 1 ; attribute EntAttr of ArchLabel : constant is ArchCons.f1 ; procedure EntProc2 (parm1 : boolean) is subtype SubpSubtype is EntSubtype ; type SubpType is record f1 : boolean ; f2 : SubpSubtype ; end record ; constant SubpCons : EntType := (f1 => EntGeneric, f2 => EntCons.f2 ) ; variable SubpVar : SubpSubtype := SubpCons.f2; alias SubpAlias : bit is SubpVar(2) ; file SubpFile : EntFileType is out "ct00519.dat"; constant SubpLabel : integer := 1 ; attribute EntAttr of SubpLabel : Constant is EntCons.f1 ; variable correct : boolean ; begin correct := EntGeneric and EntPort and EntCons.f1 and (EntCons.f2 = EntSubtype'(others => '1')) and (EntSig(2) = EntAlias) and EntLabel'EntAttr and ArchCons.f1 and (ArchCons.f2 = ArchSubtype'(others => '1')) and (ArchSig(2) = ArchAlias) and ArchLabel'EntAttr and (SubpCons = EntCons) and (SubpVar(2) = SubpAlias) and SubpLabel'EntAttr ; test_report ( "ENT00519.EntProc2" , "Declarative region direct visibility test" , correct ) ; if parm1 then EntProc2 (Not parm1) ; end if ; end EntProc2 ; begin CIS1 : ArchComp generic map ( G => True ) port map ( P => To_Boolean (ArchAlias) ) ; L1 : block component BlkComp generic ( G : boolean ) ; port ( P : boolean ) ; end component ; for CIS1 : ArchComp use entity WORK.ENT00519_1 ( ARCH00519_1 ); for CIS2 : BLKComp use entity WORK.ENT00519_1 ( ARCH00519_1 ); subtype BlkSubtype is EntSubtype ; type BlkType is record f1 : boolean ; f2 : BlkSubtype ; end record ; constant BlkCons : BlkType := (f1 => EntGeneric, f2 => EntCons.f2) ; signal BlkSig : BlkSubtype := ('0', BlkCons.f2(2), '1'); alias BlkAlias : bit is BlkSig(2) ; file BlkFile : EntFileType is out "ct00519.dat"; constant BlkLabel : integer := 1 ; attribute EntAttr of BlkLabel : constant is BlkCons.f1 ; procedure BlkProc (parm1 : boolean) is subtype SubpSubtype is EntSubtype ; type SubpType is record f1 : boolean ; f2 : SubpSubtype ; end record ; constant SubpCons : EntType := (f1 => EntGeneric, f2 => EntCons.f2 ) ; variable SubpVar : SubpSubtype := SubpCons.f2; alias SubpAlias : bit is SubpVar(2) ; file SubpFile : EntFileType is out "ct00519.dat"; constant SubpLabel : integer := 1 ; attribute EntAttr of SubpLabel : Constant is EntCons.f1 ; variable correct : boolean ; begin correct := EntGeneric and EntPort and EntCons.f1 and (EntCons.f2 = EntSubtype'(others => '1')) and (EntSig(2) = EntAlias) and EntLabel'EntAttr and ArchCons.f1 and (ArchCons.f2 = ArchSubtype'(others => '1')) and (ArchSig(2) = ArchAlias) and ArchLabel'EntAttr and BlkCons.f1 and (BlkCons.f2 = BlkSubtype'(others => '1')) and (BlkSig(2) = BlkAlias) and BlkLabel'EntAttr and (SubpCons = EntCons) and (SubpVar(2) = SubpAlias) and SubpLabel'EntAttr ; test_report ( "ENT00519.BlkProc" , "Declarative region direct visibility test" , correct ) ; if parm1 then BlkProc (Not parm1) ; end if ; end BlkProc ; begin CIS1 : ArchComp generic map ( G => True ) port map ( P => To_Boolean (ArchAlias) ) ; CIS2 : BlkComp generic map ( G => True ) port map ( P => To_Boolean (BlkAlias) ) ; process subtype PcsSubtype is EntSubtype ; type PcsType is record f1 : boolean ; f2 : PcsSubtype ; end record ; constant PcsCons : EntType := (f1 => EntGeneric, f2 => EntCons.f2 ) ; variable PcsVar : PcsSubtype := PcsCons.f2 ; alias PcsAlias : bit is PcsVar(2) ; file PcsFile : EntFileType is out "ct00519.dat"; constant PcsLabel : integer := 1 ; attribute EntAttr of PcsLabel : Constant is EntCons.f1 ; variable correct : boolean ; begin EntProc (True) ; EntProc2 (True) ; BlkProc (True) ; correct := EntGeneric and EntPort and EntCons.f1 and (EntCons.f2 = EntSubtype'(others => '1')) and (EntSig(2) = EntAlias) and EntLabel'EntAttr and ArchCons.f1 and (ArchCons.f2 = ArchSubtype'(others => '1')) and (ArchSig(2) = ArchAlias) and ArchLabel'EntAttr and BlkCons.f1 and (BlkCons.f2 = BlkSubtype'(others => '1')) and (BlkSig(2) = BlkAlias) and BlkLabel'EntAttr and (PcsCons = EntCons) and (PcsVar(2) = PcsAlias) and PcsLabel'EntAttr ; test_report ( "ENT00519.Process" , "Declarative region direct visibility test" , correct ) ; wait ; end process ; end block L1 ; end ARCH00519 ; entity ENT00519_Test_Bench is end ENT00519_Test_Bench ; architecture ARCH00519_Test_Bench of ENT00519_Test_Bench is begin L1: block component UUT generic ( EntGeneric : boolean ) ; port ( EntPort : boolean ) ; end component ; for CIS1 : UUT use entity WORK.ENT00519 ( ARCH00519 ) ; signal Dummy : boolean := True ; begin CIS1 : UUT generic map ( True ) port map ( Dummy ) ; end block L1 ; end ARCH00519_Test_Bench ;
gpl-3.0
357207c629609186bc6cecc34d7b4114
0.537444
3.79434
false
true
false
false
grwlf/vsim
vhdl_ct/ct00582.vhd
1
5,511
-- NEED RESULT: ARCH00582: Attribute declarations - scalar static subtypes with dynamic initial values passed ------------------------------------------------------------------------------- -- -- Copyright (c) 1989 by Intermetrics, Inc. -- All rights reserved. -- ------------------------------------------------------------------------------- -- -- TEST NAME: -- -- CT00582 -- -- AUTHOR: -- -- A. Wilmot -- -- TEST OBJECTIVES: -- -- 4.4 (3) -- 4.4 (4) -- -- DESIGN UNIT ORDERING: -- -- E00000(ARCH00582) -- ENT00582_Test_Bench(ARCH00582_Test_Bench) -- -- REVISION HISTORY: -- -- 19-AUG-1987 - initial revision -- -- NOTES: -- -- self-checking -- automatically generated -- use WORK.STANDARD_TYPES.all ; architecture ARCH00582 of E00000 is attribute at_boolean_1 : boolean ; attribute at_bit_1 : bit ; attribute at_severity_level_1 : severity_level ; attribute at_character_1 : character ; attribute at_t_enum1_1 : t_enum1 ; attribute at_st_enum1_1 : st_enum1 ; attribute at_integer_1 : integer ; attribute at_t_int1_1 : t_int1 ; attribute at_st_int1_1 : st_int1 ; attribute at_time_1 : time ; attribute at_t_phys1_1 : t_phys1 ; attribute at_st_phys1_1 : st_phys1 ; attribute at_real_1 : real ; attribute at_t_real1_1 : t_real1 ; attribute at_st_real1_1 : st_real1 ; procedure p2 ( i_boolean_1, i_boolean_2 : boolean := c_boolean_1 ; i_bit_1, i_bit_2 : bit := c_bit_1 ; i_severity_level_1, i_severity_level_2 : severity_level := c_severity_level_1 ; i_character_1, i_character_2 : character := c_character_1 ; i_t_enum1_1, i_t_enum1_2 : t_enum1 := c_t_enum1_1 ; i_st_enum1_1, i_st_enum1_2 : st_enum1 := c_st_enum1_1 ; i_integer_1, i_integer_2 : integer := c_integer_1 ; i_t_int1_1, i_t_int1_2 : t_int1 := c_t_int1_1 ; i_st_int1_1, i_st_int1_2 : st_int1 := c_st_int1_1 ; i_time_1, i_time_2 : time := c_time_1 ; i_t_phys1_1, i_t_phys1_2 : t_phys1 := c_t_phys1_1 ; i_st_phys1_1, i_st_phys1_2 : st_phys1 := c_st_phys1_1 ; i_real_1, i_real_2 : real := c_real_1 ; i_t_real1_1, i_t_real1_2 : t_real1 := c_t_real1_1 ; i_st_real1_1, i_st_real1_2 : st_real1 := c_st_real1_1 ) is procedure p1 ; attribute at_boolean_1 of p1 : procedure is i_boolean_1 ; attribute at_bit_1 of p1 : procedure is i_bit_1 ; attribute at_severity_level_1 of p1 : procedure is i_severity_level_1 ; attribute at_character_1 of p1 : procedure is i_character_1 ; attribute at_t_enum1_1 of p1 : procedure is i_t_enum1_1 ; attribute at_st_enum1_1 of p1 : procedure is i_st_enum1_1 ; attribute at_integer_1 of p1 : procedure is i_integer_1 ; attribute at_t_int1_1 of p1 : procedure is i_t_int1_1 ; attribute at_st_int1_1 of p1 : procedure is i_st_int1_1 ; attribute at_time_1 of p1 : procedure is i_time_1 ; attribute at_t_phys1_1 of p1 : procedure is i_t_phys1_1 ; attribute at_st_phys1_1 of p1 : procedure is i_st_phys1_1 ; attribute at_real_1 of p1 : procedure is i_real_1 ; attribute at_t_real1_1 of p1 : procedure is i_t_real1_1 ; attribute at_st_real1_1 of p1 : procedure is i_st_real1_1 ; procedure p1 is variable correct : boolean := true ; begin correct := correct and p1'at_boolean_1 = c_boolean_1 ; correct := correct and p1'at_bit_1 = c_bit_1 ; correct := correct and p1'at_severity_level_1 = c_severity_level_1 ; correct := correct and p1'at_character_1 = c_character_1 ; correct := correct and p1'at_t_enum1_1 = c_t_enum1_1 ; correct := correct and p1'at_st_enum1_1 = c_st_enum1_1 ; correct := correct and p1'at_integer_1 = c_integer_1 ; correct := correct and p1'at_t_int1_1 = c_t_int1_1 ; correct := correct and p1'at_st_int1_1 = c_st_int1_1 ; correct := correct and p1'at_time_1 = c_time_1 ; correct := correct and p1'at_t_phys1_1 = c_t_phys1_1 ; correct := correct and p1'at_st_phys1_1 = c_st_phys1_1 ; correct := correct and p1'at_real_1 = c_real_1 ; correct := correct and p1'at_t_real1_1 = c_t_real1_1 ; correct := correct and p1'at_st_real1_1 = c_st_real1_1 ; test_report ( "ARCH00582" , "Attribute declarations - scalar static subtypes" & " with dynamic initial values" , correct) ; end p1 ; begin p1 ; end p2 ; begin process begin p2 ; wait ; end process ; end ARCH00582 ; -- entity ENT00582_Test_Bench is end ENT00582_Test_Bench ; -- architecture ARCH00582_Test_Bench of ENT00582_Test_Bench is begin L1: block component UUT end component ; for CIS1 : UUT use entity WORK.E00000 ( ARCH00582 ) ; begin CIS1 : UUT ; end block L1 ; end ARCH00582_Test_Bench ;
gpl-3.0
ad99c28bd09bc7ae494c36d4a42effc2
0.518055
3.053186
false
true
false
false
grwlf/vsim
vhdl/assign3.vhd
1
44,498
-- 1000 variable assignments in 1 process. Assigning a signal. GHC fails to -- compile this one. entity main is end entity main ; architecture arch of main is signal clk : integer := 0; constant CYCLES : integer := 1000; begin main: process(clk) --{{{ variable a0001 : integer; variable a0002 : integer; variable a0003 : integer; variable a0004 : integer; variable a0005 : integer; variable a0006 : integer; variable a0007 : integer; variable a0008 : integer; variable a0009 : integer; variable a0010 : integer; variable a0011 : integer; variable a0012 : integer; variable a0013 : integer; variable a0014 : integer; variable a0015 : integer; variable a0016 : integer; variable a0017 : integer; variable a0018 : integer; variable a0019 : integer; variable a0020 : integer; variable a0021 : integer; variable a0022 : integer; variable a0023 : integer; variable a0024 : integer; variable a0025 : integer; variable a0026 : integer; variable a0027 : integer; variable a0028 : integer; variable a0029 : integer; variable a0030 : integer; variable a0031 : integer; variable a0032 : integer; variable a0033 : integer; variable a0034 : integer; variable a0035 : integer; variable a0036 : integer; variable a0037 : integer; variable a0038 : integer; variable a0039 : integer; variable a0040 : integer; variable a0041 : integer; variable a0042 : integer; variable a0043 : integer; variable a0044 : integer; variable a0045 : integer; variable a0046 : integer; variable a0047 : integer; variable a0048 : integer; variable a0049 : integer; variable a0050 : integer; variable a0051 : integer; variable a0052 : integer; variable a0053 : integer; variable a0054 : integer; variable a0055 : integer; variable a0056 : integer; variable a0057 : integer; variable a0058 : integer; variable a0059 : integer; variable a0060 : integer; variable a0061 : integer; variable a0062 : integer; variable a0063 : integer; variable a0064 : integer; variable a0065 : integer; variable a0066 : integer; variable a0067 : integer; variable a0068 : integer; variable a0069 : integer; variable a0070 : integer; variable a0071 : integer; variable a0072 : integer; variable a0073 : integer; variable a0074 : integer; variable a0075 : integer; variable a0076 : integer; variable a0077 : integer; variable a0078 : integer; variable a0079 : integer; variable a0080 : integer; variable a0081 : integer; variable a0082 : integer; variable a0083 : integer; variable a0084 : integer; variable a0085 : integer; variable a0086 : integer; variable a0087 : integer; variable a0088 : integer; variable a0089 : integer; variable a0090 : integer; variable a0091 : integer; variable a0092 : integer; variable a0093 : integer; variable a0094 : integer; variable a0095 : integer; variable a0096 : integer; variable a0097 : integer; variable a0098 : integer; variable a0099 : integer; variable a0100 : integer; variable a0101 : integer; variable a0102 : integer; variable a0103 : integer; variable a0104 : integer; variable a0105 : integer; variable a0106 : integer; variable a0107 : integer; variable a0108 : integer; variable a0109 : integer; variable a0110 : integer; variable a0111 : integer; variable a0112 : integer; variable a0113 : integer; variable a0114 : integer; variable a0115 : integer; variable a0116 : integer; variable a0117 : integer; variable a0118 : integer; variable a0119 : integer; variable a0120 : integer; variable a0121 : integer; variable a0122 : integer; variable a0123 : integer; variable a0124 : integer; variable a0125 : integer; variable a0126 : integer; variable a0127 : integer; variable a0128 : integer; variable a0129 : integer; variable a0130 : integer; variable a0131 : integer; variable a0132 : integer; variable a0133 : integer; variable a0134 : integer; variable a0135 : integer; variable a0136 : integer; variable a0137 : integer; variable a0138 : integer; variable a0139 : integer; variable a0140 : integer; variable a0141 : integer; variable a0142 : integer; variable a0143 : integer; variable a0144 : integer; variable a0145 : integer; variable a0146 : integer; variable a0147 : integer; variable a0148 : integer; variable a0149 : integer; variable a0150 : integer; variable a0151 : integer; variable a0152 : integer; variable a0153 : integer; variable a0154 : integer; variable a0155 : integer; variable a0156 : integer; variable a0157 : integer; variable a0158 : integer; variable a0159 : integer; variable a0160 : integer; variable a0161 : integer; variable a0162 : integer; variable a0163 : integer; variable a0164 : integer; variable a0165 : integer; variable a0166 : integer; variable a0167 : integer; variable a0168 : integer; variable a0169 : integer; variable a0170 : integer; variable a0171 : integer; variable a0172 : integer; variable a0173 : integer; variable a0174 : integer; variable a0175 : integer; variable a0176 : integer; variable a0177 : integer; variable a0178 : integer; variable a0179 : integer; variable a0180 : integer; variable a0181 : integer; variable a0182 : integer; variable a0183 : integer; variable a0184 : integer; variable a0185 : integer; variable a0186 : integer; variable a0187 : integer; variable a0188 : integer; variable a0189 : integer; variable a0190 : integer; variable a0191 : integer; variable a0192 : integer; variable a0193 : integer; variable a0194 : integer; variable a0195 : integer; variable a0196 : integer; variable a0197 : integer; variable a0198 : integer; variable a0199 : integer; variable a0200 : integer; variable a0201 : integer; variable a0202 : integer; variable a0203 : integer; variable a0204 : integer; variable a0205 : integer; variable a0206 : integer; variable a0207 : integer; variable a0208 : integer; variable a0209 : integer; variable a0210 : integer; variable a0211 : integer; variable a0212 : integer; variable a0213 : integer; variable a0214 : integer; variable a0215 : integer; variable a0216 : integer; variable a0217 : integer; variable a0218 : integer; variable a0219 : integer; variable a0220 : integer; variable a0221 : integer; variable a0222 : integer; variable a0223 : integer; variable a0224 : integer; variable a0225 : integer; variable a0226 : integer; variable a0227 : integer; variable a0228 : integer; variable a0229 : integer; variable a0230 : integer; variable a0231 : integer; variable a0232 : integer; variable a0233 : integer; variable a0234 : integer; variable a0235 : integer; variable a0236 : integer; variable a0237 : integer; variable a0238 : integer; variable a0239 : integer; variable a0240 : integer; variable a0241 : integer; variable a0242 : integer; variable a0243 : integer; variable a0244 : integer; variable a0245 : integer; variable a0246 : integer; variable a0247 : integer; variable a0248 : integer; variable a0249 : integer; variable a0250 : integer; variable a0251 : integer; variable a0252 : integer; variable a0253 : integer; variable a0254 : integer; variable a0255 : integer; variable a0256 : integer; variable a0257 : integer; variable a0258 : integer; variable a0259 : integer; variable a0260 : integer; variable a0261 : integer; variable a0262 : integer; variable a0263 : integer; variable a0264 : integer; variable a0265 : integer; variable a0266 : integer; variable a0267 : integer; variable a0268 : integer; variable a0269 : integer; variable a0270 : integer; variable a0271 : integer; variable a0272 : integer; variable a0273 : integer; variable a0274 : integer; variable a0275 : integer; variable a0276 : integer; variable a0277 : integer; variable a0278 : integer; variable a0279 : integer; variable a0280 : integer; variable a0281 : integer; variable a0282 : integer; variable a0283 : integer; variable a0284 : integer; variable a0285 : integer; variable a0286 : integer; variable a0287 : integer; variable a0288 : integer; variable a0289 : integer; variable a0290 : integer; variable a0291 : integer; variable a0292 : integer; variable a0293 : integer; variable a0294 : integer; variable a0295 : integer; variable a0296 : integer; variable a0297 : integer; variable a0298 : integer; variable a0299 : integer; variable a0300 : integer; variable a0301 : integer; variable a0302 : integer; variable a0303 : integer; variable a0304 : integer; variable a0305 : integer; variable a0306 : integer; variable a0307 : integer; variable a0308 : integer; variable a0309 : integer; variable a0310 : integer; variable a0311 : integer; variable a0312 : integer; variable a0313 : integer; variable a0314 : integer; variable a0315 : integer; variable a0316 : integer; variable a0317 : integer; variable a0318 : integer; variable a0319 : integer; variable a0320 : integer; variable a0321 : integer; variable a0322 : integer; variable a0323 : integer; variable a0324 : integer; variable a0325 : integer; variable a0326 : integer; variable a0327 : integer; variable a0328 : integer; variable a0329 : integer; variable a0330 : integer; variable a0331 : integer; variable a0332 : integer; variable a0333 : integer; variable a0334 : integer; variable a0335 : integer; variable a0336 : integer; variable a0337 : integer; variable a0338 : integer; variable a0339 : integer; variable a0340 : integer; variable a0341 : integer; variable a0342 : integer; variable a0343 : integer; variable a0344 : integer; variable a0345 : integer; variable a0346 : integer; variable a0347 : integer; variable a0348 : integer; variable a0349 : integer; variable a0350 : integer; variable a0351 : integer; variable a0352 : integer; variable a0353 : integer; variable a0354 : integer; variable a0355 : integer; variable a0356 : integer; variable a0357 : integer; variable a0358 : integer; variable a0359 : integer; variable a0360 : integer; variable a0361 : integer; variable a0362 : integer; variable a0363 : integer; variable a0364 : integer; variable a0365 : integer; variable a0366 : integer; variable a0367 : integer; variable a0368 : integer; variable a0369 : integer; variable a0370 : integer; variable a0371 : integer; variable a0372 : integer; variable a0373 : integer; variable a0374 : integer; variable a0375 : integer; variable a0376 : integer; variable a0377 : integer; variable a0378 : integer; variable a0379 : integer; variable a0380 : integer; variable a0381 : integer; variable a0382 : integer; variable a0383 : integer; variable a0384 : integer; variable a0385 : integer; variable a0386 : integer; variable a0387 : integer; variable a0388 : integer; variable a0389 : integer; variable a0390 : integer; variable a0391 : integer; variable a0392 : integer; variable a0393 : integer; variable a0394 : integer; variable a0395 : integer; variable a0396 : integer; variable a0397 : integer; variable a0398 : integer; variable a0399 : integer; variable a0400 : integer; variable a0401 : integer; variable a0402 : integer; variable a0403 : integer; variable a0404 : integer; variable a0405 : integer; variable a0406 : integer; variable a0407 : integer; variable a0408 : integer; variable a0409 : integer; variable a0410 : integer; variable a0411 : integer; variable a0412 : integer; variable a0413 : integer; variable a0414 : integer; variable a0415 : integer; variable a0416 : integer; variable a0417 : integer; variable a0418 : integer; variable a0419 : integer; variable a0420 : integer; variable a0421 : integer; variable a0422 : integer; variable a0423 : integer; variable a0424 : integer; variable a0425 : integer; variable a0426 : integer; variable a0427 : integer; variable a0428 : integer; variable a0429 : integer; variable a0430 : integer; variable a0431 : integer; variable a0432 : integer; variable a0433 : integer; variable a0434 : integer; variable a0435 : integer; variable a0436 : integer; variable a0437 : integer; variable a0438 : integer; variable a0439 : integer; variable a0440 : integer; variable a0441 : integer; variable a0442 : integer; variable a0443 : integer; variable a0444 : integer; variable a0445 : integer; variable a0446 : integer; variable a0447 : integer; variable a0448 : integer; variable a0449 : integer; variable a0450 : integer; variable a0451 : integer; variable a0452 : integer; variable a0453 : integer; variable a0454 : integer; variable a0455 : integer; variable a0456 : integer; variable a0457 : integer; variable a0458 : integer; variable a0459 : integer; variable a0460 : integer; variable a0461 : integer; variable a0462 : integer; variable a0463 : integer; variable a0464 : integer; variable a0465 : integer; variable a0466 : integer; variable a0467 : integer; variable a0468 : integer; variable a0469 : integer; variable a0470 : integer; variable a0471 : integer; variable a0472 : integer; variable a0473 : integer; variable a0474 : integer; variable a0475 : integer; variable a0476 : integer; variable a0477 : integer; variable a0478 : integer; variable a0479 : integer; variable a0480 : integer; variable a0481 : integer; variable a0482 : integer; variable a0483 : integer; variable a0484 : integer; variable a0485 : integer; variable a0486 : integer; variable a0487 : integer; variable a0488 : integer; variable a0489 : integer; variable a0490 : integer; variable a0491 : integer; variable a0492 : integer; variable a0493 : integer; variable a0494 : integer; variable a0495 : integer; variable a0496 : integer; variable a0497 : integer; variable a0498 : integer; variable a0499 : integer; variable a0500 : integer; variable a0501 : integer; variable a0502 : integer; variable a0503 : integer; variable a0504 : integer; variable a0505 : integer; variable a0506 : integer; variable a0507 : integer; variable a0508 : integer; variable a0509 : integer; variable a0510 : integer; variable a0511 : integer; variable a0512 : integer; variable a0513 : integer; variable a0514 : integer; variable a0515 : integer; variable a0516 : integer; variable a0517 : integer; variable a0518 : integer; variable a0519 : integer; variable a0520 : integer; variable a0521 : integer; variable a0522 : integer; variable a0523 : integer; variable a0524 : integer; variable a0525 : integer; variable a0526 : integer; variable a0527 : integer; variable a0528 : integer; variable a0529 : integer; variable a0530 : integer; variable a0531 : integer; variable a0532 : integer; variable a0533 : integer; variable a0534 : integer; variable a0535 : integer; variable a0536 : integer; variable a0537 : integer; variable a0538 : integer; variable a0539 : integer; variable a0540 : integer; variable a0541 : integer; variable a0542 : integer; variable a0543 : integer; variable a0544 : integer; variable a0545 : integer; variable a0546 : integer; variable a0547 : integer; variable a0548 : integer; variable a0549 : integer; variable a0550 : integer; variable a0551 : integer; variable a0552 : integer; variable a0553 : integer; variable a0554 : integer; variable a0555 : integer; variable a0556 : integer; variable a0557 : integer; variable a0558 : integer; variable a0559 : integer; variable a0560 : integer; variable a0561 : integer; variable a0562 : integer; variable a0563 : integer; variable a0564 : integer; variable a0565 : integer; variable a0566 : integer; variable a0567 : integer; variable a0568 : integer; variable a0569 : integer; variable a0570 : integer; variable a0571 : integer; variable a0572 : integer; variable a0573 : integer; variable a0574 : integer; variable a0575 : integer; variable a0576 : integer; variable a0577 : integer; variable a0578 : integer; variable a0579 : integer; variable a0580 : integer; variable a0581 : integer; variable a0582 : integer; variable a0583 : integer; variable a0584 : integer; variable a0585 : integer; variable a0586 : integer; variable a0587 : integer; variable a0588 : integer; variable a0589 : integer; variable a0590 : integer; variable a0591 : integer; variable a0592 : integer; variable a0593 : integer; variable a0594 : integer; variable a0595 : integer; variable a0596 : integer; variable a0597 : integer; variable a0598 : integer; variable a0599 : integer; variable a0600 : integer; variable a0601 : integer; variable a0602 : integer; variable a0603 : integer; variable a0604 : integer; variable a0605 : integer; variable a0606 : integer; variable a0607 : integer; variable a0608 : integer; variable a0609 : integer; variable a0610 : integer; variable a0611 : integer; variable a0612 : integer; variable a0613 : integer; variable a0614 : integer; variable a0615 : integer; variable a0616 : integer; variable a0617 : integer; variable a0618 : integer; variable a0619 : integer; variable a0620 : integer; variable a0621 : integer; variable a0622 : integer; variable a0623 : integer; variable a0624 : integer; variable a0625 : integer; variable a0626 : integer; variable a0627 : integer; variable a0628 : integer; variable a0629 : integer; variable a0630 : integer; variable a0631 : integer; variable a0632 : integer; variable a0633 : integer; variable a0634 : integer; variable a0635 : integer; variable a0636 : integer; variable a0637 : integer; variable a0638 : integer; variable a0639 : integer; variable a0640 : integer; variable a0641 : integer; variable a0642 : integer; variable a0643 : integer; variable a0644 : integer; variable a0645 : integer; variable a0646 : integer; variable a0647 : integer; variable a0648 : integer; variable a0649 : integer; variable a0650 : integer; variable a0651 : integer; variable a0652 : integer; variable a0653 : integer; variable a0654 : integer; variable a0655 : integer; variable a0656 : integer; variable a0657 : integer; variable a0658 : integer; variable a0659 : integer; variable a0660 : integer; variable a0661 : integer; variable a0662 : integer; variable a0663 : integer; variable a0664 : integer; variable a0665 : integer; variable a0666 : integer; variable a0667 : integer; variable a0668 : integer; variable a0669 : integer; variable a0670 : integer; variable a0671 : integer; variable a0672 : integer; variable a0673 : integer; variable a0674 : integer; variable a0675 : integer; variable a0676 : integer; variable a0677 : integer; variable a0678 : integer; variable a0679 : integer; variable a0680 : integer; variable a0681 : integer; variable a0682 : integer; variable a0683 : integer; variable a0684 : integer; variable a0685 : integer; variable a0686 : integer; variable a0687 : integer; variable a0688 : integer; variable a0689 : integer; variable a0690 : integer; variable a0691 : integer; variable a0692 : integer; variable a0693 : integer; variable a0694 : integer; variable a0695 : integer; variable a0696 : integer; variable a0697 : integer; variable a0698 : integer; variable a0699 : integer; variable a0700 : integer; variable a0701 : integer; variable a0702 : integer; variable a0703 : integer; variable a0704 : integer; variable a0705 : integer; variable a0706 : integer; variable a0707 : integer; variable a0708 : integer; variable a0709 : integer; variable a0710 : integer; variable a0711 : integer; variable a0712 : integer; variable a0713 : integer; variable a0714 : integer; variable a0715 : integer; variable a0716 : integer; variable a0717 : integer; variable a0718 : integer; variable a0719 : integer; variable a0720 : integer; variable a0721 : integer; variable a0722 : integer; variable a0723 : integer; variable a0724 : integer; variable a0725 : integer; variable a0726 : integer; variable a0727 : integer; variable a0728 : integer; variable a0729 : integer; variable a0730 : integer; variable a0731 : integer; variable a0732 : integer; variable a0733 : integer; variable a0734 : integer; variable a0735 : integer; variable a0736 : integer; variable a0737 : integer; variable a0738 : integer; variable a0739 : integer; variable a0740 : integer; variable a0741 : integer; variable a0742 : integer; variable a0743 : integer; variable a0744 : integer; variable a0745 : integer; variable a0746 : integer; variable a0747 : integer; variable a0748 : integer; variable a0749 : integer; variable a0750 : integer; variable a0751 : integer; variable a0752 : integer; variable a0753 : integer; variable a0754 : integer; variable a0755 : integer; variable a0756 : integer; variable a0757 : integer; variable a0758 : integer; variable a0759 : integer; variable a0760 : integer; variable a0761 : integer; variable a0762 : integer; variable a0763 : integer; variable a0764 : integer; variable a0765 : integer; variable a0766 : integer; variable a0767 : integer; variable a0768 : integer; variable a0769 : integer; variable a0770 : integer; variable a0771 : integer; variable a0772 : integer; variable a0773 : integer; variable a0774 : integer; variable a0775 : integer; variable a0776 : integer; variable a0777 : integer; variable a0778 : integer; variable a0779 : integer; variable a0780 : integer; variable a0781 : integer; variable a0782 : integer; variable a0783 : integer; variable a0784 : integer; variable a0785 : integer; variable a0786 : integer; variable a0787 : integer; variable a0788 : integer; variable a0789 : integer; variable a0790 : integer; variable a0791 : integer; variable a0792 : integer; variable a0793 : integer; variable a0794 : integer; variable a0795 : integer; variable a0796 : integer; variable a0797 : integer; variable a0798 : integer; variable a0799 : integer; variable a0800 : integer; variable a0801 : integer; variable a0802 : integer; variable a0803 : integer; variable a0804 : integer; variable a0805 : integer; variable a0806 : integer; variable a0807 : integer; variable a0808 : integer; variable a0809 : integer; variable a0810 : integer; variable a0811 : integer; variable a0812 : integer; variable a0813 : integer; variable a0814 : integer; variable a0815 : integer; variable a0816 : integer; variable a0817 : integer; variable a0818 : integer; variable a0819 : integer; variable a0820 : integer; variable a0821 : integer; variable a0822 : integer; variable a0823 : integer; variable a0824 : integer; variable a0825 : integer; variable a0826 : integer; variable a0827 : integer; variable a0828 : integer; variable a0829 : integer; variable a0830 : integer; variable a0831 : integer; variable a0832 : integer; variable a0833 : integer; variable a0834 : integer; variable a0835 : integer; variable a0836 : integer; variable a0837 : integer; variable a0838 : integer; variable a0839 : integer; variable a0840 : integer; variable a0841 : integer; variable a0842 : integer; variable a0843 : integer; variable a0844 : integer; variable a0845 : integer; variable a0846 : integer; variable a0847 : integer; variable a0848 : integer; variable a0849 : integer; variable a0850 : integer; variable a0851 : integer; variable a0852 : integer; variable a0853 : integer; variable a0854 : integer; variable a0855 : integer; variable a0856 : integer; variable a0857 : integer; variable a0858 : integer; variable a0859 : integer; variable a0860 : integer; variable a0861 : integer; variable a0862 : integer; variable a0863 : integer; variable a0864 : integer; variable a0865 : integer; variable a0866 : integer; variable a0867 : integer; variable a0868 : integer; variable a0869 : integer; variable a0870 : integer; variable a0871 : integer; variable a0872 : integer; variable a0873 : integer; variable a0874 : integer; variable a0875 : integer; variable a0876 : integer; variable a0877 : integer; variable a0878 : integer; variable a0879 : integer; variable a0880 : integer; variable a0881 : integer; variable a0882 : integer; variable a0883 : integer; variable a0884 : integer; variable a0885 : integer; variable a0886 : integer; variable a0887 : integer; variable a0888 : integer; variable a0889 : integer; variable a0890 : integer; variable a0891 : integer; variable a0892 : integer; variable a0893 : integer; variable a0894 : integer; variable a0895 : integer; variable a0896 : integer; variable a0897 : integer; variable a0898 : integer; variable a0899 : integer; variable a0900 : integer; variable a0901 : integer; variable a0902 : integer; variable a0903 : integer; variable a0904 : integer; variable a0905 : integer; variable a0906 : integer; variable a0907 : integer; variable a0908 : integer; variable a0909 : integer; variable a0910 : integer; variable a0911 : integer; variable a0912 : integer; variable a0913 : integer; variable a0914 : integer; variable a0915 : integer; variable a0916 : integer; variable a0917 : integer; variable a0918 : integer; variable a0919 : integer; variable a0920 : integer; variable a0921 : integer; variable a0922 : integer; variable a0923 : integer; variable a0924 : integer; variable a0925 : integer; variable a0926 : integer; variable a0927 : integer; variable a0928 : integer; variable a0929 : integer; variable a0930 : integer; variable a0931 : integer; variable a0932 : integer; variable a0933 : integer; variable a0934 : integer; variable a0935 : integer; variable a0936 : integer; variable a0937 : integer; variable a0938 : integer; variable a0939 : integer; variable a0940 : integer; variable a0941 : integer; variable a0942 : integer; variable a0943 : integer; variable a0944 : integer; variable a0945 : integer; variable a0946 : integer; variable a0947 : integer; variable a0948 : integer; variable a0949 : integer; variable a0950 : integer; variable a0951 : integer; variable a0952 : integer; variable a0953 : integer; variable a0954 : integer; variable a0955 : integer; variable a0956 : integer; variable a0957 : integer; variable a0958 : integer; variable a0959 : integer; variable a0960 : integer; variable a0961 : integer; variable a0962 : integer; variable a0963 : integer; variable a0964 : integer; variable a0965 : integer; variable a0966 : integer; variable a0967 : integer; variable a0968 : integer; variable a0969 : integer; variable a0970 : integer; variable a0971 : integer; variable a0972 : integer; variable a0973 : integer; variable a0974 : integer; variable a0975 : integer; variable a0976 : integer; variable a0977 : integer; variable a0978 : integer; variable a0979 : integer; variable a0980 : integer; variable a0981 : integer; variable a0982 : integer; variable a0983 : integer; variable a0984 : integer; variable a0985 : integer; variable a0986 : integer; variable a0987 : integer; variable a0988 : integer; variable a0989 : integer; variable a0990 : integer; variable a0991 : integer; variable a0992 : integer; variable a0993 : integer; variable a0994 : integer; variable a0995 : integer; variable a0996 : integer; variable a0997 : integer; variable a0998 : integer; variable a0999 : integer; variable a1000 : integer; begin a0001 := clk; a0002 := clk; a0003 := clk; a0004 := clk; a0005 := clk; a0006 := clk; a0007 := clk; a0008 := clk; a0009 := clk; a0010 := clk; a0011 := clk; a0012 := clk; a0013 := clk; a0014 := clk; a0015 := clk; a0016 := clk; a0017 := clk; a0018 := clk; a0019 := clk; a0020 := clk; a0021 := clk; a0022 := clk; a0023 := clk; a0024 := clk; a0025 := clk; a0026 := clk; a0027 := clk; a0028 := clk; a0029 := clk; a0030 := clk; a0031 := clk; a0032 := clk; a0033 := clk; a0034 := clk; a0035 := clk; a0036 := clk; a0037 := clk; a0038 := clk; a0039 := clk; a0040 := clk; a0041 := clk; a0042 := clk; a0043 := clk; a0044 := clk; a0045 := clk; a0046 := clk; a0047 := clk; a0048 := clk; a0049 := clk; a0050 := clk; a0051 := clk; a0052 := clk; a0053 := clk; a0054 := clk; a0055 := clk; a0056 := clk; a0057 := clk; a0058 := clk; a0059 := clk; a0060 := clk; a0061 := clk; a0062 := clk; a0063 := clk; a0064 := clk; a0065 := clk; a0066 := clk; a0067 := clk; a0068 := clk; a0069 := clk; a0070 := clk; a0071 := clk; a0072 := clk; a0073 := clk; a0074 := clk; a0075 := clk; a0076 := clk; a0077 := clk; a0078 := clk; a0079 := clk; a0080 := clk; a0081 := clk; a0082 := clk; a0083 := clk; a0084 := clk; a0085 := clk; a0086 := clk; a0087 := clk; a0088 := clk; a0089 := clk; a0090 := clk; a0091 := clk; a0092 := clk; a0093 := clk; a0094 := clk; a0095 := clk; a0096 := clk; a0097 := clk; a0098 := clk; a0099 := clk; a0100 := clk; a0101 := clk; a0102 := clk; a0103 := clk; a0104 := clk; a0105 := clk; a0106 := clk; a0107 := clk; a0108 := clk; a0109 := clk; a0110 := clk; a0111 := clk; a0112 := clk; a0113 := clk; a0114 := clk; a0115 := clk; a0116 := clk; a0117 := clk; a0118 := clk; a0119 := clk; a0120 := clk; a0121 := clk; a0122 := clk; a0123 := clk; a0124 := clk; a0125 := clk; a0126 := clk; a0127 := clk; a0128 := clk; a0129 := clk; a0130 := clk; a0131 := clk; a0132 := clk; a0133 := clk; a0134 := clk; a0135 := clk; a0136 := clk; a0137 := clk; a0138 := clk; a0139 := clk; a0140 := clk; a0141 := clk; a0142 := clk; a0143 := clk; a0144 := clk; a0145 := clk; a0146 := clk; a0147 := clk; a0148 := clk; a0149 := clk; a0150 := clk; a0151 := clk; a0152 := clk; a0153 := clk; a0154 := clk; a0155 := clk; a0156 := clk; a0157 := clk; a0158 := clk; a0159 := clk; a0160 := clk; a0161 := clk; a0162 := clk; a0163 := clk; a0164 := clk; a0165 := clk; a0166 := clk; a0167 := clk; a0168 := clk; a0169 := clk; a0170 := clk; a0171 := clk; a0172 := clk; a0173 := clk; a0174 := clk; a0175 := clk; a0176 := clk; a0177 := clk; a0178 := clk; a0179 := clk; a0180 := clk; a0181 := clk; a0182 := clk; a0183 := clk; a0184 := clk; a0185 := clk; a0186 := clk; a0187 := clk; a0188 := clk; a0189 := clk; a0190 := clk; a0191 := clk; a0192 := clk; a0193 := clk; a0194 := clk; a0195 := clk; a0196 := clk; a0197 := clk; a0198 := clk; a0199 := clk; a0200 := clk; a0201 := clk; a0202 := clk; a0203 := clk; a0204 := clk; a0205 := clk; a0206 := clk; a0207 := clk; a0208 := clk; a0209 := clk; a0210 := clk; a0211 := clk; a0212 := clk; a0213 := clk; a0214 := clk; a0215 := clk; a0216 := clk; a0217 := clk; a0218 := clk; a0219 := clk; a0220 := clk; a0221 := clk; a0222 := clk; a0223 := clk; a0224 := clk; a0225 := clk; a0226 := clk; a0227 := clk; a0228 := clk; a0229 := clk; a0230 := clk; a0231 := clk; a0232 := clk; a0233 := clk; a0234 := clk; a0235 := clk; a0236 := clk; a0237 := clk; a0238 := clk; a0239 := clk; a0240 := clk; a0241 := clk; a0242 := clk; a0243 := clk; a0244 := clk; a0245 := clk; a0246 := clk; a0247 := clk; a0248 := clk; a0249 := clk; a0250 := clk; a0251 := clk; a0252 := clk; a0253 := clk; a0254 := clk; a0255 := clk; a0256 := clk; a0257 := clk; a0258 := clk; a0259 := clk; a0260 := clk; a0261 := clk; a0262 := clk; a0263 := clk; a0264 := clk; a0265 := clk; a0266 := clk; a0267 := clk; a0268 := clk; a0269 := clk; a0270 := clk; a0271 := clk; a0272 := clk; a0273 := clk; a0274 := clk; a0275 := clk; a0276 := clk; a0277 := clk; a0278 := clk; a0279 := clk; a0280 := clk; a0281 := clk; a0282 := clk; a0283 := clk; a0284 := clk; a0285 := clk; a0286 := clk; a0287 := clk; a0288 := clk; a0289 := clk; a0290 := clk; a0291 := clk; a0292 := clk; a0293 := clk; a0294 := clk; a0295 := clk; a0296 := clk; a0297 := clk; a0298 := clk; a0299 := clk; a0300 := clk; a0301 := clk; a0302 := clk; a0303 := clk; a0304 := clk; a0305 := clk; a0306 := clk; a0307 := clk; a0308 := clk; a0309 := clk; a0310 := clk; a0311 := clk; a0312 := clk; a0313 := clk; a0314 := clk; a0315 := clk; a0316 := clk; a0317 := clk; a0318 := clk; a0319 := clk; a0320 := clk; a0321 := clk; a0322 := clk; a0323 := clk; a0324 := clk; a0325 := clk; a0326 := clk; a0327 := clk; a0328 := clk; a0329 := clk; a0330 := clk; a0331 := clk; a0332 := clk; a0333 := clk; a0334 := clk; a0335 := clk; a0336 := clk; a0337 := clk; a0338 := clk; a0339 := clk; a0340 := clk; a0341 := clk; a0342 := clk; a0343 := clk; a0344 := clk; a0345 := clk; a0346 := clk; a0347 := clk; a0348 := clk; a0349 := clk; a0350 := clk; a0351 := clk; a0352 := clk; a0353 := clk; a0354 := clk; a0355 := clk; a0356 := clk; a0357 := clk; a0358 := clk; a0359 := clk; a0360 := clk; a0361 := clk; a0362 := clk; a0363 := clk; a0364 := clk; a0365 := clk; a0366 := clk; a0367 := clk; a0368 := clk; a0369 := clk; a0370 := clk; a0371 := clk; a0372 := clk; a0373 := clk; a0374 := clk; a0375 := clk; a0376 := clk; a0377 := clk; a0378 := clk; a0379 := clk; a0380 := clk; a0381 := clk; a0382 := clk; a0383 := clk; a0384 := clk; a0385 := clk; a0386 := clk; a0387 := clk; a0388 := clk; a0389 := clk; a0390 := clk; a0391 := clk; a0392 := clk; a0393 := clk; a0394 := clk; a0395 := clk; a0396 := clk; a0397 := clk; a0398 := clk; a0399 := clk; a0400 := clk; a0401 := clk; a0402 := clk; a0403 := clk; a0404 := clk; a0405 := clk; a0406 := clk; a0407 := clk; a0408 := clk; a0409 := clk; a0410 := clk; a0411 := clk; a0412 := clk; a0413 := clk; a0414 := clk; a0415 := clk; a0416 := clk; a0417 := clk; a0418 := clk; a0419 := clk; a0420 := clk; a0421 := clk; a0422 := clk; a0423 := clk; a0424 := clk; a0425 := clk; a0426 := clk; a0427 := clk; a0428 := clk; a0429 := clk; a0430 := clk; a0431 := clk; a0432 := clk; a0433 := clk; a0434 := clk; a0435 := clk; a0436 := clk; a0437 := clk; a0438 := clk; a0439 := clk; a0440 := clk; a0441 := clk; a0442 := clk; a0443 := clk; a0444 := clk; a0445 := clk; a0446 := clk; a0447 := clk; a0448 := clk; a0449 := clk; a0450 := clk; a0451 := clk; a0452 := clk; a0453 := clk; a0454 := clk; a0455 := clk; a0456 := clk; a0457 := clk; a0458 := clk; a0459 := clk; a0460 := clk; a0461 := clk; a0462 := clk; a0463 := clk; a0464 := clk; a0465 := clk; a0466 := clk; a0467 := clk; a0468 := clk; a0469 := clk; a0470 := clk; a0471 := clk; a0472 := clk; a0473 := clk; a0474 := clk; a0475 := clk; a0476 := clk; a0477 := clk; a0478 := clk; a0479 := clk; a0480 := clk; a0481 := clk; a0482 := clk; a0483 := clk; a0484 := clk; a0485 := clk; a0486 := clk; a0487 := clk; a0488 := clk; a0489 := clk; a0490 := clk; a0491 := clk; a0492 := clk; a0493 := clk; a0494 := clk; a0495 := clk; a0496 := clk; a0497 := clk; a0498 := clk; a0499 := clk; a0500 := clk; a0501 := clk; a0502 := clk; a0503 := clk; a0504 := clk; a0505 := clk; a0506 := clk; a0507 := clk; a0508 := clk; a0509 := clk; a0510 := clk; a0511 := clk; a0512 := clk; a0513 := clk; a0514 := clk; a0515 := clk; a0516 := clk; a0517 := clk; a0518 := clk; a0519 := clk; a0520 := clk; a0521 := clk; a0522 := clk; a0523 := clk; a0524 := clk; a0525 := clk; a0526 := clk; a0527 := clk; a0528 := clk; a0529 := clk; a0530 := clk; a0531 := clk; a0532 := clk; a0533 := clk; a0534 := clk; a0535 := clk; a0536 := clk; a0537 := clk; a0538 := clk; a0539 := clk; a0540 := clk; a0541 := clk; a0542 := clk; a0543 := clk; a0544 := clk; a0545 := clk; a0546 := clk; a0547 := clk; a0548 := clk; a0549 := clk; a0550 := clk; a0551 := clk; a0552 := clk; a0553 := clk; a0554 := clk; a0555 := clk; a0556 := clk; a0557 := clk; a0558 := clk; a0559 := clk; a0560 := clk; a0561 := clk; a0562 := clk; a0563 := clk; a0564 := clk; a0565 := clk; a0566 := clk; a0567 := clk; a0568 := clk; a0569 := clk; a0570 := clk; a0571 := clk; a0572 := clk; a0573 := clk; a0574 := clk; a0575 := clk; a0576 := clk; a0577 := clk; a0578 := clk; a0579 := clk; a0580 := clk; a0581 := clk; a0582 := clk; a0583 := clk; a0584 := clk; a0585 := clk; a0586 := clk; a0587 := clk; a0588 := clk; a0589 := clk; a0590 := clk; a0591 := clk; a0592 := clk; a0593 := clk; a0594 := clk; a0595 := clk; a0596 := clk; a0597 := clk; a0598 := clk; a0599 := clk; a0600 := clk; a0601 := clk; a0602 := clk; a0603 := clk; a0604 := clk; a0605 := clk; a0606 := clk; a0607 := clk; a0608 := clk; a0609 := clk; a0610 := clk; a0611 := clk; a0612 := clk; a0613 := clk; a0614 := clk; a0615 := clk; a0616 := clk; a0617 := clk; a0618 := clk; a0619 := clk; a0620 := clk; a0621 := clk; a0622 := clk; a0623 := clk; a0624 := clk; a0625 := clk; a0626 := clk; a0627 := clk; a0628 := clk; a0629 := clk; a0630 := clk; a0631 := clk; a0632 := clk; a0633 := clk; a0634 := clk; a0635 := clk; a0636 := clk; a0637 := clk; a0638 := clk; a0639 := clk; a0640 := clk; a0641 := clk; a0642 := clk; a0643 := clk; a0644 := clk; a0645 := clk; a0646 := clk; a0647 := clk; a0648 := clk; a0649 := clk; a0650 := clk; a0651 := clk; a0652 := clk; a0653 := clk; a0654 := clk; a0655 := clk; a0656 := clk; a0657 := clk; a0658 := clk; a0659 := clk; a0660 := clk; a0661 := clk; a0662 := clk; a0663 := clk; a0664 := clk; a0665 := clk; a0666 := clk; a0667 := clk; a0668 := clk; a0669 := clk; a0670 := clk; a0671 := clk; a0672 := clk; a0673 := clk; a0674 := clk; a0675 := clk; a0676 := clk; a0677 := clk; a0678 := clk; a0679 := clk; a0680 := clk; a0681 := clk; a0682 := clk; a0683 := clk; a0684 := clk; a0685 := clk; a0686 := clk; a0687 := clk; a0688 := clk; a0689 := clk; a0690 := clk; a0691 := clk; a0692 := clk; a0693 := clk; a0694 := clk; a0695 := clk; a0696 := clk; a0697 := clk; a0698 := clk; a0699 := clk; a0700 := clk; a0701 := clk; a0702 := clk; a0703 := clk; a0704 := clk; a0705 := clk; a0706 := clk; a0707 := clk; a0708 := clk; a0709 := clk; a0710 := clk; a0711 := clk; a0712 := clk; a0713 := clk; a0714 := clk; a0715 := clk; a0716 := clk; a0717 := clk; a0718 := clk; a0719 := clk; a0720 := clk; a0721 := clk; a0722 := clk; a0723 := clk; a0724 := clk; a0725 := clk; a0726 := clk; a0727 := clk; a0728 := clk; a0729 := clk; a0730 := clk; a0731 := clk; a0732 := clk; a0733 := clk; a0734 := clk; a0735 := clk; a0736 := clk; a0737 := clk; a0738 := clk; a0739 := clk; a0740 := clk; a0741 := clk; a0742 := clk; a0743 := clk; a0744 := clk; a0745 := clk; a0746 := clk; a0747 := clk; a0748 := clk; a0749 := clk; a0750 := clk; a0751 := clk; a0752 := clk; a0753 := clk; a0754 := clk; a0755 := clk; a0756 := clk; a0757 := clk; a0758 := clk; a0759 := clk; a0760 := clk; a0761 := clk; a0762 := clk; a0763 := clk; a0764 := clk; a0765 := clk; a0766 := clk; a0767 := clk; a0768 := clk; a0769 := clk; a0770 := clk; a0771 := clk; a0772 := clk; a0773 := clk; a0774 := clk; a0775 := clk; a0776 := clk; a0777 := clk; a0778 := clk; a0779 := clk; a0780 := clk; a0781 := clk; a0782 := clk; a0783 := clk; a0784 := clk; a0785 := clk; a0786 := clk; a0787 := clk; a0788 := clk; a0789 := clk; a0790 := clk; a0791 := clk; a0792 := clk; a0793 := clk; a0794 := clk; a0795 := clk; a0796 := clk; a0797 := clk; a0798 := clk; a0799 := clk; a0800 := clk; a0801 := clk; a0802 := clk; a0803 := clk; a0804 := clk; a0805 := clk; a0806 := clk; a0807 := clk; a0808 := clk; a0809 := clk; a0810 := clk; a0811 := clk; a0812 := clk; a0813 := clk; a0814 := clk; a0815 := clk; a0816 := clk; a0817 := clk; a0818 := clk; a0819 := clk; a0820 := clk; a0821 := clk; a0822 := clk; a0823 := clk; a0824 := clk; a0825 := clk; a0826 := clk; a0827 := clk; a0828 := clk; a0829 := clk; a0830 := clk; a0831 := clk; a0832 := clk; a0833 := clk; a0834 := clk; a0835 := clk; a0836 := clk; a0837 := clk; a0838 := clk; a0839 := clk; a0840 := clk; a0841 := clk; a0842 := clk; a0843 := clk; a0844 := clk; a0845 := clk; a0846 := clk; a0847 := clk; a0848 := clk; a0849 := clk; a0850 := clk; a0851 := clk; a0852 := clk; a0853 := clk; a0854 := clk; a0855 := clk; a0856 := clk; a0857 := clk; a0858 := clk; a0859 := clk; a0860 := clk; a0861 := clk; a0862 := clk; a0863 := clk; a0864 := clk; a0865 := clk; a0866 := clk; a0867 := clk; a0868 := clk; a0869 := clk; a0870 := clk; a0871 := clk; a0872 := clk; a0873 := clk; a0874 := clk; a0875 := clk; a0876 := clk; a0877 := clk; a0878 := clk; a0879 := clk; a0880 := clk; a0881 := clk; a0882 := clk; a0883 := clk; a0884 := clk; a0885 := clk; a0886 := clk; a0887 := clk; a0888 := clk; a0889 := clk; a0890 := clk; a0891 := clk; a0892 := clk; a0893 := clk; a0894 := clk; a0895 := clk; a0896 := clk; a0897 := clk; a0898 := clk; a0899 := clk; a0900 := clk; a0901 := clk; a0902 := clk; a0903 := clk; a0904 := clk; a0905 := clk; a0906 := clk; a0907 := clk; a0908 := clk; a0909 := clk; a0910 := clk; a0911 := clk; a0912 := clk; a0913 := clk; a0914 := clk; a0915 := clk; a0916 := clk; a0917 := clk; a0918 := clk; a0919 := clk; a0920 := clk; a0921 := clk; a0922 := clk; a0923 := clk; a0924 := clk; a0925 := clk; a0926 := clk; a0927 := clk; a0928 := clk; a0929 := clk; a0930 := clk; a0931 := clk; a0932 := clk; a0933 := clk; a0934 := clk; a0935 := clk; a0936 := clk; a0937 := clk; a0938 := clk; a0939 := clk; a0940 := clk; a0941 := clk; a0942 := clk; a0943 := clk; a0944 := clk; a0945 := clk; a0946 := clk; a0947 := clk; a0948 := clk; a0949 := clk; a0950 := clk; a0951 := clk; a0952 := clk; a0953 := clk; a0954 := clk; a0955 := clk; a0956 := clk; a0957 := clk; a0958 := clk; a0959 := clk; a0960 := clk; a0961 := clk; a0962 := clk; a0963 := clk; a0964 := clk; a0965 := clk; a0966 := clk; a0967 := clk; a0968 := clk; a0969 := clk; a0970 := clk; a0971 := clk; a0972 := clk; a0973 := clk; a0974 := clk; a0975 := clk; a0976 := clk; a0977 := clk; a0978 := clk; a0979 := clk; a0980 := clk; a0981 := clk; a0982 := clk; a0983 := clk; a0984 := clk; a0985 := clk; a0986 := clk; a0987 := clk; a0988 := clk; a0989 := clk; a0990 := clk; a0991 := clk; a0992 := clk; a0993 := clk; a0994 := clk; a0995 := clk; a0996 := clk; a0997 := clk; a0998 := clk; a0999 := clk; a1000 := clk; --}}} end process; terminator : process(clk) begin if clk >= CYCLES then assert false report "end of simulation" severity failure; -- else -- report "tick"; end if; end process; clk <= (clk+1) after 1 us; end;
gpl-3.0
659844729c13e71b38d056e2cbcb1d0c
0.636703
2.795276
false
false
false
false
grwlf/vsim
vhdl_ct/ct00698.vhd
1
2,968
-- NEED RESULT: ARCH00698: Formal parameters of mode in may be left unspecified in association list if they have default expressions passed ------------------------------------------------------------------------------- -- -- Copyright (c) 1989 by Intermetrics, Inc. -- All rights reserved. -- ------------------------------------------------------------------------------- -- -- TEST NAME: -- -- CT00698 -- -- AUTHOR: -- -- A. Wilmot -- -- TEST OBJECTIVES: -- -- 4.3.3.2 (7) -- -- DESIGN UNIT ORDERING: -- -- ENT00698(ARCH00698) -- ENT00698_Test_Bench(ARCH00698_Test_Bench) -- -- REVISION HISTORY: -- -- 09-SEP-1987 - initial revision -- -- NOTES: -- -- self-checking -- use WORK.STANDARD_TYPES.all ; entity ENT00698 is port ( p_integer : integer := 5 ; p_boolean : boolean := true ; p_st_arr3 : st_arr3 := c_st_arr3_1 ) ; end ENT00698 ; -- architecture ARCH00698 of ENT00698 is procedure p1 ( pc_integer : integer := -4 ; pc_boolean : boolean := false ; pc_st_arr3 : st_arr3 := c_st_arr3_2 ; pv_integer : integer := 3 ; pv_boolean : boolean := true ; pv_st_arr3 : st_arr3 := c_st_arr3_1 ; signal ps_integer : integer ; signal ps_boolean : boolean ; signal ps_st_arr3 : st_arr3 ) is variable correct : boolean := true ; begin correct := correct and pc_integer = -4 ; correct := correct and not pc_boolean ; correct := correct and pc_st_arr3 = c_st_arr3_2 ; correct := correct and pv_integer = 0 ; correct := correct and pv_boolean ; correct := correct and pv_st_arr3 = c_st_arr3_1 ; correct := correct and ps_integer = 5 ; correct := correct and ps_boolean ; correct := correct and ps_st_arr3 = c_st_arr3_1 ; test_report ( "ARCH00698" , "Formal parameters of mode in may be left unspecified" & " in association list if they have default expressions" , correct ) ; end p1 ; begin process variable v_integer : integer := 0 ; variable v_boolean : boolean := true ; variable v_st_arr3 : st_arr3 := c_st_arr3_1 ; begin p1 ( ps_integer => p_integer , ps_boolean => p_boolean , ps_st_arr3 => p_st_arr3 , pv_integer => 0 ) ; wait ; end process ; end ARCH00698 ; -- use WORK.STANDARD_TYPES.all ; entity ENT00698_Test_Bench is end ENT00698_Test_Bench ; -- architecture ARCH00698_Test_Bench of ENT00698_Test_Bench is begin L1: block component UUT end component ; for CIS1 : UUT use entity WORK.ENT00698 ( ARCH00698 ) ; begin CIS1 : UUT ; end block L1 ; end ARCH00698_Test_Bench ; --
gpl-3.0
7947dfd625e573ed6557a3b281fe56e6
0.508086
3.537545
false
true
false
false
grwlf/vsim
vhdl_ct/ct00294.vhd
1
4,064
-- NEED RESULT: ARCH00294: Type of result is type of left operand for logical operators passed ------------------------------------------------------------------------------- -- -- Copyright (c) 1989 by Intermetrics, Inc. -- All rights reserved. -- ------------------------------------------------------------------------------- -- -- TEST NAME: -- -- CT00294 -- -- AUTHOR: -- -- A. Wilmot -- -- TEST OBJECTIVES: -- -- 7.2.1 (4) -- 7.2.1 (5) -- -- DESIGN UNIT ORDERING: -- -- E00000(ARCH00294) -- ENT00294_Test_Bench(ARCH00294_Test_Bench) -- -- REVISION HISTORY: -- -- 24-JUL-1987 - initial revision -- -- NOTES: -- -- self-checking -- use WORK.STANDARD_TYPES.all ; architecture ARCH00294 of E00000 is type tbit is array ( integer range <> ) of bit ; subtype tbit1 is tbit ( 1 to 4 ) ; subtype tbit2 is tbit ( 5 downto 2 ) ; type tboolean is array ( integer range <> ) of boolean ; subtype tboolean1 is tboolean ( 1 to 4 ) ; subtype tboolean2 is tboolean ( 5 downto 2 ) ; begin P00294 : process variable bit1_1, bit1_2 : tbit1 ; variable bit2_1, bit2_2 : tbit2 ; variable boolean1_1, boolean1_2 : tboolean1 ; variable boolean2_1, boolean2_2 : tboolean2 ; variable vbit : boolean ; variable vboolean, bool : boolean := True ; begin bit1_1 := b"0011" ; bit2_1 := ('0', '1', '0', '1') ; -- bit1_2 := bit1_1 and bit2_1 ; bool := bool and bit1_2 = b"0001" ; bit1_2 := bit1_1 or bit2_1 ; bool := bool and bit1_2 = b"0111" ; bit1_2 := bit1_1 nand bit2_1 ; bool := bool and bit1_2 = b"1110" ; bit1_2 := bit1_1 nor bit2_1 ; bool := bool and bit1_2 = b"1000" ; bit1_2 := bit1_1 xor bit2_1 ; bool := bool and bit1_2 = b"0110" ; bit2_2 := bit2_1 and bit1_1 ; bool := bool and bit2_2 = b"0001" ; bit2_2 := bit2_1 or bit1_1 ; bool := bool and bit2_2 = b"0111" ; bit2_2 := bit2_1 nand bit1_1 ; bool := bool and bit2_2 = b"1110" ; bit2_2 := bit2_1 nor bit1_1 ; bool := bool and bit2_2 = b"1000" ; bit2_2 := bit2_1 xor bit1_1 ; bool := bool and bit2_2 = b"0110" ; boolean1_1 := (false, false, true, true) ; boolean2_1 := (false, true, false, true) ; -- boolean1_2 := boolean1_1 and boolean2_1 ; bool := bool and boolean1_2 = (false, false, false, true) ; boolean1_2 := boolean1_1 or boolean2_1 ; bool := bool and boolean1_2 = (false, true, true, true) ; boolean1_2 := boolean1_1 nand boolean2_1 ; bool := bool and boolean1_2 = (true, true, true, false) ; boolean1_2 := boolean1_1 nor boolean2_1 ; bool := bool and boolean1_2 = (true, false, false, false) ; boolean1_2 := boolean1_1 xor boolean2_1 ; bool := bool and boolean1_2 = (false, true, true, false) ; boolean2_2 := boolean2_1 and boolean1_1 ; bool := bool and boolean2_2 = (false, false, false, true) ; boolean2_2 := boolean2_1 or boolean1_1 ; bool := bool and boolean2_2 = (false, true, true, true) ; boolean2_2 := boolean2_1 nand boolean1_1 ; bool := bool and boolean2_2 = (true, true, true, false) ; boolean2_2 := boolean2_1 nor boolean1_1 ; bool := bool and boolean2_2 = (true, false, false, false) ; boolean2_2 := boolean2_1 xor boolean1_1 ; bool := bool and boolean2_2 = (false, true, true, false) ; test_report ( "ARCH00294" , "Type of result is type of left operand for" & " logical operators" , bool ) ; wait ; end process P00294 ; end ARCH00294 ; entity ENT00294_Test_Bench is end ENT00294_Test_Bench ; architecture ARCH00294_Test_Bench of ENT00294_Test_Bench is begin L1: block component UUT end component ; for CIS1 : UUT use entity WORK.E00000 ( ARCH00294 ) ; begin CIS1 : UUT ; end block L1 ; end ARCH00294_Test_Bench ;
gpl-3.0
e96eb6037ea000ac4ad6c113cfbcb133
0.537648
3.114176
false
true
false
false
TWW12/lzw
final_project_sim/lzw/lzw.srcs/sources_1/ip/bram_1024_3/bram_1024_3_sim_netlist.vhdl
1
50,604
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved. -- -------------------------------------------------------------------------------- -- Tool Version: Vivado v.2016.4 (win64) Build 1756540 Mon Jan 23 19:11:23 MST 2017 -- Date : Tue Apr 18 23:18:55 2017 -- Host : DESKTOP-I9J3TQJ running 64-bit major release (build 9200) -- Command : write_vhdl -force -mode funcsim -- X:/final_project_sim/lzw/lzw.srcs/sources_1/ip/bram_1024_3/bram_1024_3_sim_netlist.vhdl -- Design : bram_1024_3 -- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or -- synthesized. This netlist cannot be used for SDF annotated simulation. -- Device : xc7z020clg484-1 -- -------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity bram_1024_3_blk_mem_gen_prim_wrapper_init is port ( douta : out STD_LOGIC_VECTOR ( 19 downto 0 ); clka : in STD_LOGIC; ena : in STD_LOGIC; addra : in STD_LOGIC_VECTOR ( 9 downto 0 ); dina : in STD_LOGIC_VECTOR ( 19 downto 0 ); wea : in STD_LOGIC_VECTOR ( 0 to 0 ) ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of bram_1024_3_blk_mem_gen_prim_wrapper_init : entity is "blk_mem_gen_prim_wrapper_init"; end bram_1024_3_blk_mem_gen_prim_wrapper_init; architecture STRUCTURE of bram_1024_3_blk_mem_gen_prim_wrapper_init is signal \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_21\ : STD_LOGIC; signal \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_22\ : STD_LOGIC; signal \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_23\ : STD_LOGIC; signal \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_29\ : STD_LOGIC; signal \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_30\ : STD_LOGIC; signal \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_31\ : STD_LOGIC; signal \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_37\ : STD_LOGIC; signal \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_38\ : STD_LOGIC; signal \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_39\ : STD_LOGIC; signal \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_45\ : STD_LOGIC; signal \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_46\ : STD_LOGIC; signal \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_47\ : STD_LOGIC; signal \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_85\ : STD_LOGIC; signal \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_86\ : STD_LOGIC; signal \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_87\ : STD_LOGIC; signal \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_88\ : STD_LOGIC; signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC; signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC; signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\ : STD_LOGIC; signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\ : STD_LOGIC; signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 ); signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 ); signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 ); attribute CLOCK_DOMAINS : string; attribute CLOCK_DOMAINS of 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X"0000000000000000000000000000000000000000000000000000000000000000", INIT_70 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_71 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_72 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_73 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_74 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_A => X"000000000", INIT_B => X"000000000", INIT_FILE => "NONE", IS_CLKARDCLK_INVERTED => '0', IS_CLKBWRCLK_INVERTED => '0', IS_ENARDEN_INVERTED => '0', IS_ENBWREN_INVERTED => '0', IS_RSTRAMARSTRAM_INVERTED => '0', IS_RSTRAMB_INVERTED => '0', IS_RSTREGARSTREG_INVERTED => '0', IS_RSTREGB_INVERTED => '0', RAM_EXTENSION_A => "NONE", RAM_EXTENSION_B => "NONE", RAM_MODE => "TDP", RDADDR_COLLISION_HWCONFIG => "PERFORMANCE", READ_WIDTH_A => 36, READ_WIDTH_B => 36, RSTREG_PRIORITY_A => "REGCE", RSTREG_PRIORITY_B => "REGCE", SIM_COLLISION_CHECK => "ALL", SIM_DEVICE => "7SERIES", SRVAL_A => X"000000000", SRVAL_B => X"000000000", WRITE_MODE_A => "WRITE_FIRST", WRITE_MODE_B => "WRITE_FIRST", WRITE_WIDTH_A => 36, WRITE_WIDTH_B => 36 ) port map ( ADDRARDADDR(15) => '1', ADDRARDADDR(14 downto 5) => addra(9 downto 0), ADDRARDADDR(4 downto 0) => B"11111", ADDRBWRADDR(15 downto 0) => B"0000000000000000", CASCADEINA => '0', CASCADEINB => '0', CASCADEOUTA => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\, CASCADEOUTB => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\, CLKARDCLK => clka, CLKBWRCLK => clka, DBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\, DIADI(31 downto 29) => B"000", DIADI(28 downto 24) => dina(19 downto 15), DIADI(23 downto 21) => B"000", DIADI(20 downto 16) => dina(14 downto 10), DIADI(15 downto 13) => B"000", DIADI(12 downto 8) => dina(9 downto 5), DIADI(7 downto 5) => B"000", DIADI(4 downto 0) => dina(4 downto 0), DIBDI(31 downto 0) => B"00000000000000000000000000000000", DIPADIP(3 downto 0) => B"0000", DIPBDIP(3 downto 0) => B"0000", DOADO(31) => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_21\, DOADO(30) => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_22\, DOADO(29) => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_23\, DOADO(28 downto 24) => douta(19 downto 15), DOADO(23) => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_29\, DOADO(22) => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_30\, DOADO(21) => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_31\, DOADO(20 downto 16) => douta(14 downto 10), DOADO(15) => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_37\, DOADO(14) => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_38\, DOADO(13) => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_39\, DOADO(12 downto 8) => douta(9 downto 5), DOADO(7) => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_45\, DOADO(6) => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_46\, DOADO(5) => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_47\, DOADO(4 downto 0) => douta(4 downto 0), DOBDO(31 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\(31 downto 0), DOPADOP(3) => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_85\, DOPADOP(2) => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_86\, DOPADOP(1) => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_87\, DOPADOP(0) => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_88\, DOPBDOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\(3 downto 0), ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\(7 downto 0), ENARDEN => ena, ENBWREN => '0', INJECTDBITERR => '0', INJECTSBITERR => '0', RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\(8 downto 0), REGCEAREGCE => ena, REGCEB => '0', RSTRAMARSTRAM => '0', RSTRAMB => '0', RSTREGARSTREG => '0', RSTREGB => '0', SBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\, WEA(3) => wea(0), WEA(2) => wea(0), WEA(1) => wea(0), WEA(0) => wea(0), WEBWE(7 downto 0) => B"00000000" ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity bram_1024_3_blk_mem_gen_prim_width is port ( douta : out STD_LOGIC_VECTOR ( 19 downto 0 ); clka : in STD_LOGIC; ena : in STD_LOGIC; addra : in STD_LOGIC_VECTOR ( 9 downto 0 ); dina : in STD_LOGIC_VECTOR ( 19 downto 0 ); wea : in STD_LOGIC_VECTOR ( 0 to 0 ) ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of bram_1024_3_blk_mem_gen_prim_width : entity is "blk_mem_gen_prim_width"; end bram_1024_3_blk_mem_gen_prim_width; architecture STRUCTURE of bram_1024_3_blk_mem_gen_prim_width is begin \prim_init.ram\: entity work.bram_1024_3_blk_mem_gen_prim_wrapper_init port map ( addra(9 downto 0) => addra(9 downto 0), clka => clka, dina(19 downto 0) => dina(19 downto 0), douta(19 downto 0) => douta(19 downto 0), ena => ena, wea(0) => wea(0) ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity bram_1024_3_blk_mem_gen_generic_cstr is port ( douta : out STD_LOGIC_VECTOR ( 19 downto 0 ); clka : in STD_LOGIC; ena : in STD_LOGIC; addra : in STD_LOGIC_VECTOR ( 9 downto 0 ); dina : in STD_LOGIC_VECTOR ( 19 downto 0 ); wea : in STD_LOGIC_VECTOR ( 0 to 0 ) ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of bram_1024_3_blk_mem_gen_generic_cstr : entity is "blk_mem_gen_generic_cstr"; end bram_1024_3_blk_mem_gen_generic_cstr; architecture STRUCTURE of bram_1024_3_blk_mem_gen_generic_cstr is begin \ramloop[0].ram.r\: entity work.bram_1024_3_blk_mem_gen_prim_width port map ( addra(9 downto 0) => addra(9 downto 0), clka => clka, dina(19 downto 0) => dina(19 downto 0), douta(19 downto 0) => douta(19 downto 0), ena => ena, wea(0) => wea(0) ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity bram_1024_3_blk_mem_gen_top is port ( douta : out STD_LOGIC_VECTOR ( 19 downto 0 ); clka : in STD_LOGIC; ena : in STD_LOGIC; addra : in STD_LOGIC_VECTOR ( 9 downto 0 ); dina : in STD_LOGIC_VECTOR ( 19 downto 0 ); wea : in STD_LOGIC_VECTOR ( 0 to 0 ) ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of bram_1024_3_blk_mem_gen_top : entity is "blk_mem_gen_top"; end bram_1024_3_blk_mem_gen_top; architecture STRUCTURE of bram_1024_3_blk_mem_gen_top is begin \valid.cstr\: entity work.bram_1024_3_blk_mem_gen_generic_cstr port map ( addra(9 downto 0) => addra(9 downto 0), clka => clka, dina(19 downto 0) => dina(19 downto 0), douta(19 downto 0) => douta(19 downto 0), ena => ena, wea(0) => wea(0) ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity bram_1024_3_blk_mem_gen_v8_3_5_synth is port ( douta : out STD_LOGIC_VECTOR ( 19 downto 0 ); clka : in STD_LOGIC; ena : in STD_LOGIC; addra : in STD_LOGIC_VECTOR ( 9 downto 0 ); dina : in STD_LOGIC_VECTOR ( 19 downto 0 ); wea : in STD_LOGIC_VECTOR ( 0 to 0 ) ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of bram_1024_3_blk_mem_gen_v8_3_5_synth : entity is "blk_mem_gen_v8_3_5_synth"; end bram_1024_3_blk_mem_gen_v8_3_5_synth; architecture STRUCTURE of bram_1024_3_blk_mem_gen_v8_3_5_synth is begin \gnbram.gnativebmg.native_blk_mem_gen\: entity work.bram_1024_3_blk_mem_gen_top port map ( addra(9 downto 0) => addra(9 downto 0), clka => clka, dina(19 downto 0) => dina(19 downto 0), douta(19 downto 0) => douta(19 downto 0), ena => ena, wea(0) => wea(0) ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity bram_1024_3_blk_mem_gen_v8_3_5 is port ( clka : in STD_LOGIC; rsta : in STD_LOGIC; ena : in STD_LOGIC; regcea : in STD_LOGIC; wea : in STD_LOGIC_VECTOR ( 0 to 0 ); addra : in STD_LOGIC_VECTOR ( 9 downto 0 ); dina : in STD_LOGIC_VECTOR ( 19 downto 0 ); douta : out STD_LOGIC_VECTOR ( 19 downto 0 ); clkb : in STD_LOGIC; rstb : in STD_LOGIC; enb : in STD_LOGIC; regceb : in STD_LOGIC; web : in STD_LOGIC_VECTOR ( 0 to 0 ); addrb : in STD_LOGIC_VECTOR ( 9 downto 0 ); dinb : in STD_LOGIC_VECTOR ( 19 downto 0 ); doutb : out STD_LOGIC_VECTOR ( 19 downto 0 ); injectsbiterr : in STD_LOGIC; injectdbiterr : in STD_LOGIC; eccpipece : in STD_LOGIC; sbiterr : out STD_LOGIC; dbiterr : out STD_LOGIC; rdaddrecc : out STD_LOGIC_VECTOR ( 9 downto 0 ); sleep : in STD_LOGIC; deepsleep : in STD_LOGIC; shutdown : in STD_LOGIC; rsta_busy : out STD_LOGIC; rstb_busy : out STD_LOGIC; s_aclk : in STD_LOGIC; s_aresetn : in STD_LOGIC; s_axi_awid : in STD_LOGIC_VECTOR ( 3 downto 0 ); s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 ); s_axi_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 ); s_axi_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 ); s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 ); s_axi_awvalid : in STD_LOGIC; s_axi_awready : out STD_LOGIC; s_axi_wdata : in STD_LOGIC_VECTOR ( 19 downto 0 ); s_axi_wstrb : in STD_LOGIC_VECTOR ( 0 to 0 ); s_axi_wlast : in STD_LOGIC; s_axi_wvalid : in STD_LOGIC; s_axi_wready : out STD_LOGIC; s_axi_bid : out STD_LOGIC_VECTOR ( 3 downto 0 ); s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 ); s_axi_bvalid : out STD_LOGIC; s_axi_bready : in STD_LOGIC; s_axi_arid : in STD_LOGIC_VECTOR ( 3 downto 0 ); s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 ); s_axi_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 ); s_axi_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 ); s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 ); s_axi_arvalid : in STD_LOGIC; s_axi_arready : out STD_LOGIC; s_axi_rid : out STD_LOGIC_VECTOR ( 3 downto 0 ); s_axi_rdata : out STD_LOGIC_VECTOR ( 19 downto 0 ); s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 ); s_axi_rlast : out STD_LOGIC; s_axi_rvalid : out STD_LOGIC; s_axi_rready : in STD_LOGIC; s_axi_injectsbiterr : in STD_LOGIC; s_axi_injectdbiterr : in STD_LOGIC; s_axi_sbiterr : out STD_LOGIC; s_axi_dbiterr : out STD_LOGIC; s_axi_rdaddrecc : out STD_LOGIC_VECTOR ( 9 downto 0 ) ); attribute C_ADDRA_WIDTH : integer; attribute C_ADDRA_WIDTH of bram_1024_3_blk_mem_gen_v8_3_5 : entity is 10; attribute C_ADDRB_WIDTH : integer; attribute C_ADDRB_WIDTH of bram_1024_3_blk_mem_gen_v8_3_5 : entity is 10; attribute C_ALGORITHM : integer; attribute C_ALGORITHM of bram_1024_3_blk_mem_gen_v8_3_5 : entity is 1; attribute C_AXI_ID_WIDTH : integer; attribute C_AXI_ID_WIDTH of bram_1024_3_blk_mem_gen_v8_3_5 : entity is 4; attribute C_AXI_SLAVE_TYPE : integer; attribute C_AXI_SLAVE_TYPE of bram_1024_3_blk_mem_gen_v8_3_5 : entity is 0; attribute C_AXI_TYPE : integer; attribute C_AXI_TYPE of bram_1024_3_blk_mem_gen_v8_3_5 : entity is 1; attribute C_BYTE_SIZE : integer; attribute C_BYTE_SIZE of bram_1024_3_blk_mem_gen_v8_3_5 : entity is 9; attribute C_COMMON_CLK : integer; attribute C_COMMON_CLK of bram_1024_3_blk_mem_gen_v8_3_5 : entity is 0; attribute C_COUNT_18K_BRAM : string; attribute C_COUNT_18K_BRAM of bram_1024_3_blk_mem_gen_v8_3_5 : entity is "0"; attribute C_COUNT_36K_BRAM : string; attribute C_COUNT_36K_BRAM of bram_1024_3_blk_mem_gen_v8_3_5 : entity is "1"; attribute C_CTRL_ECC_ALGO : string; attribute C_CTRL_ECC_ALGO of bram_1024_3_blk_mem_gen_v8_3_5 : entity is "NONE"; attribute C_DEFAULT_DATA : string; attribute C_DEFAULT_DATA of bram_1024_3_blk_mem_gen_v8_3_5 : entity is "0"; attribute C_DISABLE_WARN_BHV_COLL : integer; attribute C_DISABLE_WARN_BHV_COLL of bram_1024_3_blk_mem_gen_v8_3_5 : entity is 0; attribute C_DISABLE_WARN_BHV_RANGE : integer; attribute C_DISABLE_WARN_BHV_RANGE of bram_1024_3_blk_mem_gen_v8_3_5 : entity is 0; attribute C_ELABORATION_DIR : string; attribute C_ELABORATION_DIR of bram_1024_3_blk_mem_gen_v8_3_5 : entity is "./"; attribute C_ENABLE_32BIT_ADDRESS : integer; attribute C_ENABLE_32BIT_ADDRESS of bram_1024_3_blk_mem_gen_v8_3_5 : entity is 0; attribute C_EN_DEEPSLEEP_PIN : integer; attribute C_EN_DEEPSLEEP_PIN of bram_1024_3_blk_mem_gen_v8_3_5 : entity is 0; attribute C_EN_ECC_PIPE : integer; attribute C_EN_ECC_PIPE of bram_1024_3_blk_mem_gen_v8_3_5 : entity is 0; attribute C_EN_RDADDRA_CHG : integer; attribute C_EN_RDADDRA_CHG of bram_1024_3_blk_mem_gen_v8_3_5 : entity is 0; attribute C_EN_RDADDRB_CHG : integer; attribute C_EN_RDADDRB_CHG of bram_1024_3_blk_mem_gen_v8_3_5 : entity is 0; attribute C_EN_SAFETY_CKT : integer; attribute C_EN_SAFETY_CKT of bram_1024_3_blk_mem_gen_v8_3_5 : entity is 0; attribute C_EN_SHUTDOWN_PIN : integer; attribute C_EN_SHUTDOWN_PIN of bram_1024_3_blk_mem_gen_v8_3_5 : entity is 0; attribute C_EN_SLEEP_PIN : integer; attribute C_EN_SLEEP_PIN of bram_1024_3_blk_mem_gen_v8_3_5 : entity is 0; attribute C_EST_POWER_SUMMARY : string; attribute C_EST_POWER_SUMMARY of bram_1024_3_blk_mem_gen_v8_3_5 : entity is "Estimated Power for IP : 2.74095 mW"; attribute C_FAMILY : string; attribute C_FAMILY of bram_1024_3_blk_mem_gen_v8_3_5 : entity is "zynq"; attribute C_HAS_AXI_ID : integer; attribute C_HAS_AXI_ID of bram_1024_3_blk_mem_gen_v8_3_5 : entity is 0; attribute C_HAS_ENA : integer; attribute C_HAS_ENA of bram_1024_3_blk_mem_gen_v8_3_5 : entity is 1; attribute C_HAS_ENB : integer; attribute C_HAS_ENB of bram_1024_3_blk_mem_gen_v8_3_5 : entity is 0; attribute C_HAS_INJECTERR : integer; attribute C_HAS_INJECTERR of bram_1024_3_blk_mem_gen_v8_3_5 : entity is 0; attribute C_HAS_MEM_OUTPUT_REGS_A : integer; attribute C_HAS_MEM_OUTPUT_REGS_A of bram_1024_3_blk_mem_gen_v8_3_5 : entity is 1; attribute C_HAS_MEM_OUTPUT_REGS_B : integer; attribute C_HAS_MEM_OUTPUT_REGS_B of bram_1024_3_blk_mem_gen_v8_3_5 : entity is 0; attribute C_HAS_MUX_OUTPUT_REGS_A : integer; attribute C_HAS_MUX_OUTPUT_REGS_A of bram_1024_3_blk_mem_gen_v8_3_5 : entity is 0; attribute C_HAS_MUX_OUTPUT_REGS_B : integer; attribute C_HAS_MUX_OUTPUT_REGS_B of bram_1024_3_blk_mem_gen_v8_3_5 : entity is 0; attribute C_HAS_REGCEA : integer; attribute C_HAS_REGCEA of bram_1024_3_blk_mem_gen_v8_3_5 : entity is 0; attribute C_HAS_REGCEB : integer; attribute C_HAS_REGCEB of bram_1024_3_blk_mem_gen_v8_3_5 : entity is 0; attribute C_HAS_RSTA : integer; attribute C_HAS_RSTA of bram_1024_3_blk_mem_gen_v8_3_5 : entity is 0; attribute C_HAS_RSTB : integer; attribute C_HAS_RSTB of bram_1024_3_blk_mem_gen_v8_3_5 : entity is 0; attribute C_HAS_SOFTECC_INPUT_REGS_A : integer; attribute C_HAS_SOFTECC_INPUT_REGS_A of bram_1024_3_blk_mem_gen_v8_3_5 : entity is 0; attribute C_HAS_SOFTECC_OUTPUT_REGS_B : integer; attribute C_HAS_SOFTECC_OUTPUT_REGS_B of bram_1024_3_blk_mem_gen_v8_3_5 : entity is 0; attribute C_INITA_VAL : string; attribute C_INITA_VAL of bram_1024_3_blk_mem_gen_v8_3_5 : entity is "0"; attribute C_INITB_VAL : string; attribute C_INITB_VAL of bram_1024_3_blk_mem_gen_v8_3_5 : entity is "0"; attribute C_INIT_FILE : string; attribute C_INIT_FILE of bram_1024_3_blk_mem_gen_v8_3_5 : entity is "bram_1024_3.mem"; attribute C_INIT_FILE_NAME : string; attribute C_INIT_FILE_NAME of bram_1024_3_blk_mem_gen_v8_3_5 : entity is "bram_1024_3.mif"; attribute C_INTERFACE_TYPE : integer; attribute C_INTERFACE_TYPE of bram_1024_3_blk_mem_gen_v8_3_5 : entity is 0; attribute C_LOAD_INIT_FILE : integer; attribute C_LOAD_INIT_FILE of bram_1024_3_blk_mem_gen_v8_3_5 : entity is 1; attribute C_MEM_TYPE : integer; attribute C_MEM_TYPE of bram_1024_3_blk_mem_gen_v8_3_5 : entity is 0; attribute C_MUX_PIPELINE_STAGES : integer; attribute C_MUX_PIPELINE_STAGES of bram_1024_3_blk_mem_gen_v8_3_5 : entity is 0; attribute C_PRIM_TYPE : integer; attribute C_PRIM_TYPE of bram_1024_3_blk_mem_gen_v8_3_5 : entity is 1; attribute C_READ_DEPTH_A : integer; attribute C_READ_DEPTH_A of bram_1024_3_blk_mem_gen_v8_3_5 : entity is 1024; attribute C_READ_DEPTH_B : integer; attribute C_READ_DEPTH_B of bram_1024_3_blk_mem_gen_v8_3_5 : entity is 1024; attribute C_READ_WIDTH_A : integer; attribute C_READ_WIDTH_A of bram_1024_3_blk_mem_gen_v8_3_5 : entity is 20; attribute C_READ_WIDTH_B : integer; attribute C_READ_WIDTH_B of bram_1024_3_blk_mem_gen_v8_3_5 : entity is 20; attribute C_RSTRAM_A : integer; attribute C_RSTRAM_A of bram_1024_3_blk_mem_gen_v8_3_5 : entity is 0; attribute C_RSTRAM_B : integer; attribute C_RSTRAM_B of bram_1024_3_blk_mem_gen_v8_3_5 : entity is 0; attribute C_RST_PRIORITY_A : string; attribute C_RST_PRIORITY_A of bram_1024_3_blk_mem_gen_v8_3_5 : entity is "CE"; attribute C_RST_PRIORITY_B : string; attribute C_RST_PRIORITY_B of bram_1024_3_blk_mem_gen_v8_3_5 : entity is "CE"; attribute C_SIM_COLLISION_CHECK : string; attribute C_SIM_COLLISION_CHECK of bram_1024_3_blk_mem_gen_v8_3_5 : entity is "ALL"; attribute C_USE_BRAM_BLOCK : integer; attribute C_USE_BRAM_BLOCK of bram_1024_3_blk_mem_gen_v8_3_5 : entity is 0; attribute C_USE_BYTE_WEA : integer; attribute C_USE_BYTE_WEA of bram_1024_3_blk_mem_gen_v8_3_5 : entity is 0; attribute C_USE_BYTE_WEB : integer; attribute C_USE_BYTE_WEB of bram_1024_3_blk_mem_gen_v8_3_5 : entity is 0; attribute C_USE_DEFAULT_DATA : integer; attribute C_USE_DEFAULT_DATA of bram_1024_3_blk_mem_gen_v8_3_5 : entity is 0; attribute C_USE_ECC : integer; attribute C_USE_ECC of bram_1024_3_blk_mem_gen_v8_3_5 : entity is 0; attribute C_USE_SOFTECC : integer; attribute C_USE_SOFTECC of bram_1024_3_blk_mem_gen_v8_3_5 : entity is 0; attribute C_USE_URAM : integer; attribute C_USE_URAM of bram_1024_3_blk_mem_gen_v8_3_5 : entity is 0; attribute C_WEA_WIDTH : integer; attribute C_WEA_WIDTH of bram_1024_3_blk_mem_gen_v8_3_5 : entity is 1; attribute C_WEB_WIDTH : integer; attribute C_WEB_WIDTH of bram_1024_3_blk_mem_gen_v8_3_5 : entity is 1; attribute C_WRITE_DEPTH_A : integer; attribute C_WRITE_DEPTH_A of bram_1024_3_blk_mem_gen_v8_3_5 : entity is 1024; attribute C_WRITE_DEPTH_B : integer; attribute C_WRITE_DEPTH_B of bram_1024_3_blk_mem_gen_v8_3_5 : entity is 1024; attribute C_WRITE_MODE_A : string; attribute C_WRITE_MODE_A of bram_1024_3_blk_mem_gen_v8_3_5 : entity is "WRITE_FIRST"; attribute C_WRITE_MODE_B : string; attribute C_WRITE_MODE_B of bram_1024_3_blk_mem_gen_v8_3_5 : entity is "WRITE_FIRST"; attribute C_WRITE_WIDTH_A : integer; attribute C_WRITE_WIDTH_A of bram_1024_3_blk_mem_gen_v8_3_5 : entity is 20; attribute C_WRITE_WIDTH_B : integer; attribute C_WRITE_WIDTH_B of bram_1024_3_blk_mem_gen_v8_3_5 : entity is 20; attribute C_XDEVICEFAMILY : string; attribute C_XDEVICEFAMILY of bram_1024_3_blk_mem_gen_v8_3_5 : entity is "zynq"; attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of bram_1024_3_blk_mem_gen_v8_3_5 : entity is "blk_mem_gen_v8_3_5"; attribute downgradeipidentifiedwarnings : string; attribute downgradeipidentifiedwarnings of bram_1024_3_blk_mem_gen_v8_3_5 : entity is "yes"; end bram_1024_3_blk_mem_gen_v8_3_5; architecture STRUCTURE of bram_1024_3_blk_mem_gen_v8_3_5 is signal \<const0>\ : STD_LOGIC; begin dbiterr <= \<const0>\; doutb(19) <= \<const0>\; doutb(18) <= \<const0>\; doutb(17) <= \<const0>\; doutb(16) <= \<const0>\; doutb(15) <= \<const0>\; doutb(14) <= \<const0>\; doutb(13) <= \<const0>\; doutb(12) <= \<const0>\; doutb(11) <= \<const0>\; doutb(10) <= \<const0>\; doutb(9) <= \<const0>\; doutb(8) <= \<const0>\; doutb(7) <= \<const0>\; doutb(6) <= \<const0>\; doutb(5) <= \<const0>\; doutb(4) <= \<const0>\; doutb(3) <= \<const0>\; doutb(2) <= \<const0>\; doutb(1) <= \<const0>\; doutb(0) <= \<const0>\; rdaddrecc(9) <= \<const0>\; rdaddrecc(8) <= \<const0>\; rdaddrecc(7) <= \<const0>\; rdaddrecc(6) <= \<const0>\; rdaddrecc(5) <= \<const0>\; rdaddrecc(4) <= \<const0>\; rdaddrecc(3) <= \<const0>\; rdaddrecc(2) <= \<const0>\; rdaddrecc(1) <= \<const0>\; rdaddrecc(0) <= \<const0>\; rsta_busy <= \<const0>\; rstb_busy <= \<const0>\; s_axi_arready <= \<const0>\; s_axi_awready <= \<const0>\; s_axi_bid(3) <= \<const0>\; s_axi_bid(2) <= \<const0>\; s_axi_bid(1) <= \<const0>\; s_axi_bid(0) <= \<const0>\; s_axi_bresp(1) <= \<const0>\; s_axi_bresp(0) <= \<const0>\; s_axi_bvalid <= \<const0>\; s_axi_dbiterr <= \<const0>\; s_axi_rdaddrecc(9) <= \<const0>\; s_axi_rdaddrecc(8) <= \<const0>\; s_axi_rdaddrecc(7) <= \<const0>\; s_axi_rdaddrecc(6) <= \<const0>\; s_axi_rdaddrecc(5) <= \<const0>\; s_axi_rdaddrecc(4) <= \<const0>\; s_axi_rdaddrecc(3) <= \<const0>\; s_axi_rdaddrecc(2) <= \<const0>\; s_axi_rdaddrecc(1) <= \<const0>\; s_axi_rdaddrecc(0) <= \<const0>\; s_axi_rdata(19) <= \<const0>\; s_axi_rdata(18) <= \<const0>\; s_axi_rdata(17) <= \<const0>\; s_axi_rdata(16) <= \<const0>\; s_axi_rdata(15) <= \<const0>\; s_axi_rdata(14) <= \<const0>\; s_axi_rdata(13) <= \<const0>\; s_axi_rdata(12) <= \<const0>\; s_axi_rdata(11) <= \<const0>\; s_axi_rdata(10) <= \<const0>\; s_axi_rdata(9) <= \<const0>\; s_axi_rdata(8) <= \<const0>\; s_axi_rdata(7) <= \<const0>\; s_axi_rdata(6) <= \<const0>\; s_axi_rdata(5) <= \<const0>\; s_axi_rdata(4) <= \<const0>\; s_axi_rdata(3) <= \<const0>\; s_axi_rdata(2) <= \<const0>\; s_axi_rdata(1) <= \<const0>\; s_axi_rdata(0) <= \<const0>\; s_axi_rid(3) <= \<const0>\; s_axi_rid(2) <= \<const0>\; s_axi_rid(1) <= \<const0>\; s_axi_rid(0) <= \<const0>\; s_axi_rlast <= \<const0>\; s_axi_rresp(1) <= \<const0>\; s_axi_rresp(0) <= \<const0>\; s_axi_rvalid <= \<const0>\; s_axi_sbiterr <= \<const0>\; s_axi_wready <= \<const0>\; sbiterr <= \<const0>\; GND: unisim.vcomponents.GND port map ( G => \<const0>\ ); inst_blk_mem_gen: entity work.bram_1024_3_blk_mem_gen_v8_3_5_synth port map ( addra(9 downto 0) => addra(9 downto 0), clka => clka, dina(19 downto 0) => dina(19 downto 0), douta(19 downto 0) => douta(19 downto 0), ena => ena, wea(0) => wea(0) ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity bram_1024_3 is port ( clka : in STD_LOGIC; ena : in STD_LOGIC; wea : in STD_LOGIC_VECTOR ( 0 to 0 ); addra : in STD_LOGIC_VECTOR ( 9 downto 0 ); dina : in STD_LOGIC_VECTOR ( 19 downto 0 ); douta : out STD_LOGIC_VECTOR ( 19 downto 0 ) ); attribute NotValidForBitStream : boolean; attribute NotValidForBitStream of bram_1024_3 : entity is true; attribute CHECK_LICENSE_TYPE : string; attribute CHECK_LICENSE_TYPE of bram_1024_3 : entity is "bram_1024_3,blk_mem_gen_v8_3_5,{}"; attribute downgradeipidentifiedwarnings : string; attribute downgradeipidentifiedwarnings of bram_1024_3 : entity is "yes"; attribute x_core_info : string; attribute x_core_info of bram_1024_3 : entity is "blk_mem_gen_v8_3_5,Vivado 2016.4"; end bram_1024_3; architecture STRUCTURE of bram_1024_3 is signal NLW_U0_dbiterr_UNCONNECTED : STD_LOGIC; signal NLW_U0_rsta_busy_UNCONNECTED : STD_LOGIC; signal NLW_U0_rstb_busy_UNCONNECTED : STD_LOGIC; signal NLW_U0_s_axi_arready_UNCONNECTED : STD_LOGIC; signal NLW_U0_s_axi_awready_UNCONNECTED : STD_LOGIC; signal NLW_U0_s_axi_bvalid_UNCONNECTED : STD_LOGIC; signal NLW_U0_s_axi_dbiterr_UNCONNECTED : STD_LOGIC; signal NLW_U0_s_axi_rlast_UNCONNECTED : STD_LOGIC; signal NLW_U0_s_axi_rvalid_UNCONNECTED : STD_LOGIC; signal NLW_U0_s_axi_sbiterr_UNCONNECTED : STD_LOGIC; signal NLW_U0_s_axi_wready_UNCONNECTED : STD_LOGIC; signal NLW_U0_sbiterr_UNCONNECTED : STD_LOGIC; signal NLW_U0_doutb_UNCONNECTED : STD_LOGIC_VECTOR ( 19 downto 0 ); signal NLW_U0_rdaddrecc_UNCONNECTED : STD_LOGIC_VECTOR ( 9 downto 0 ); signal NLW_U0_s_axi_bid_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 ); signal NLW_U0_s_axi_bresp_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 ); signal NLW_U0_s_axi_rdaddrecc_UNCONNECTED : STD_LOGIC_VECTOR ( 9 downto 0 ); signal NLW_U0_s_axi_rdata_UNCONNECTED : STD_LOGIC_VECTOR ( 19 downto 0 ); signal NLW_U0_s_axi_rid_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 ); signal NLW_U0_s_axi_rresp_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 ); attribute C_ADDRA_WIDTH : integer; attribute C_ADDRA_WIDTH of U0 : label is 10; attribute C_ADDRB_WIDTH : integer; attribute C_ADDRB_WIDTH of U0 : label is 10; attribute C_ALGORITHM : integer; attribute C_ALGORITHM of U0 : label is 1; attribute C_AXI_ID_WIDTH : integer; attribute C_AXI_ID_WIDTH of U0 : label is 4; attribute C_AXI_SLAVE_TYPE : integer; attribute C_AXI_SLAVE_TYPE of U0 : label is 0; attribute C_AXI_TYPE : integer; attribute C_AXI_TYPE of U0 : label is 1; attribute C_BYTE_SIZE : integer; attribute C_BYTE_SIZE of U0 : label is 9; attribute C_COMMON_CLK : integer; attribute C_COMMON_CLK of U0 : label is 0; attribute C_COUNT_18K_BRAM : string; attribute C_COUNT_18K_BRAM of U0 : label is "0"; attribute C_COUNT_36K_BRAM : string; attribute C_COUNT_36K_BRAM of U0 : label is "1"; attribute C_CTRL_ECC_ALGO : string; attribute C_CTRL_ECC_ALGO of U0 : label is "NONE"; attribute C_DEFAULT_DATA : string; attribute C_DEFAULT_DATA of U0 : label is "0"; attribute C_DISABLE_WARN_BHV_COLL : integer; attribute C_DISABLE_WARN_BHV_COLL of U0 : label is 0; attribute C_DISABLE_WARN_BHV_RANGE : integer; attribute C_DISABLE_WARN_BHV_RANGE of U0 : label is 0; attribute C_ELABORATION_DIR : string; attribute C_ELABORATION_DIR of U0 : label is "./"; attribute C_ENABLE_32BIT_ADDRESS : integer; attribute C_ENABLE_32BIT_ADDRESS of U0 : label is 0; attribute C_EN_DEEPSLEEP_PIN : integer; attribute C_EN_DEEPSLEEP_PIN of U0 : label is 0; attribute C_EN_ECC_PIPE : integer; attribute C_EN_ECC_PIPE of U0 : label is 0; attribute C_EN_RDADDRA_CHG : integer; attribute C_EN_RDADDRA_CHG of U0 : label is 0; attribute C_EN_RDADDRB_CHG : integer; attribute C_EN_RDADDRB_CHG of U0 : label is 0; attribute C_EN_SAFETY_CKT : integer; attribute C_EN_SAFETY_CKT of U0 : label is 0; attribute C_EN_SHUTDOWN_PIN : integer; attribute C_EN_SHUTDOWN_PIN of U0 : label is 0; attribute C_EN_SLEEP_PIN : integer; attribute C_EN_SLEEP_PIN of U0 : label is 0; attribute C_EST_POWER_SUMMARY : string; attribute C_EST_POWER_SUMMARY of U0 : label is "Estimated Power for IP : 2.74095 mW"; attribute C_FAMILY : string; attribute C_FAMILY of U0 : label is "zynq"; attribute C_HAS_AXI_ID : integer; attribute C_HAS_AXI_ID of U0 : label is 0; attribute C_HAS_ENA : integer; attribute C_HAS_ENA of U0 : label is 1; attribute C_HAS_ENB : integer; attribute C_HAS_ENB of U0 : label is 0; attribute C_HAS_INJECTERR : integer; attribute C_HAS_INJECTERR of U0 : label is 0; attribute C_HAS_MEM_OUTPUT_REGS_A : integer; attribute C_HAS_MEM_OUTPUT_REGS_A of U0 : label is 1; attribute C_HAS_MEM_OUTPUT_REGS_B : integer; attribute C_HAS_MEM_OUTPUT_REGS_B of U0 : label is 0; attribute C_HAS_MUX_OUTPUT_REGS_A : integer; attribute C_HAS_MUX_OUTPUT_REGS_A of U0 : label is 0; attribute C_HAS_MUX_OUTPUT_REGS_B : integer; attribute C_HAS_MUX_OUTPUT_REGS_B of U0 : label is 0; attribute C_HAS_REGCEA : integer; attribute C_HAS_REGCEA of U0 : label is 0; attribute C_HAS_REGCEB : integer; attribute C_HAS_REGCEB of U0 : label is 0; attribute C_HAS_RSTA : integer; attribute C_HAS_RSTA of U0 : label is 0; attribute C_HAS_RSTB : integer; attribute C_HAS_RSTB of U0 : label is 0; attribute C_HAS_SOFTECC_INPUT_REGS_A : integer; attribute C_HAS_SOFTECC_INPUT_REGS_A of U0 : label is 0; attribute C_HAS_SOFTECC_OUTPUT_REGS_B : integer; attribute C_HAS_SOFTECC_OUTPUT_REGS_B of U0 : label is 0; attribute C_INITA_VAL : string; attribute C_INITA_VAL of U0 : label is "0"; attribute C_INITB_VAL : string; attribute C_INITB_VAL of U0 : label is "0"; attribute C_INIT_FILE : string; attribute C_INIT_FILE of U0 : label is "bram_1024_3.mem"; attribute C_INIT_FILE_NAME : string; attribute C_INIT_FILE_NAME of U0 : label is "bram_1024_3.mif"; attribute C_INTERFACE_TYPE : integer; attribute C_INTERFACE_TYPE of U0 : label is 0; attribute C_LOAD_INIT_FILE : integer; attribute C_LOAD_INIT_FILE of U0 : label is 1; attribute C_MEM_TYPE : integer; attribute C_MEM_TYPE of U0 : label is 0; attribute C_MUX_PIPELINE_STAGES : integer; attribute C_MUX_PIPELINE_STAGES of U0 : label is 0; attribute C_PRIM_TYPE : integer; attribute C_PRIM_TYPE of U0 : label is 1; attribute C_READ_DEPTH_A : integer; attribute C_READ_DEPTH_A of U0 : label is 1024; attribute C_READ_DEPTH_B : integer; attribute C_READ_DEPTH_B of U0 : label is 1024; attribute C_READ_WIDTH_A : integer; attribute C_READ_WIDTH_A of U0 : label is 20; attribute C_READ_WIDTH_B : integer; attribute C_READ_WIDTH_B of U0 : label is 20; attribute C_RSTRAM_A : integer; attribute C_RSTRAM_A of U0 : label is 0; attribute C_RSTRAM_B : integer; attribute C_RSTRAM_B of U0 : label is 0; attribute C_RST_PRIORITY_A : string; attribute C_RST_PRIORITY_A of U0 : label is "CE"; attribute C_RST_PRIORITY_B : string; attribute C_RST_PRIORITY_B of U0 : label is "CE"; attribute C_SIM_COLLISION_CHECK : string; attribute C_SIM_COLLISION_CHECK of U0 : label is "ALL"; attribute C_USE_BRAM_BLOCK : integer; attribute C_USE_BRAM_BLOCK of U0 : label is 0; attribute C_USE_BYTE_WEA : integer; attribute C_USE_BYTE_WEA of U0 : label is 0; attribute C_USE_BYTE_WEB : integer; attribute C_USE_BYTE_WEB of U0 : label is 0; attribute C_USE_DEFAULT_DATA : integer; attribute C_USE_DEFAULT_DATA of U0 : label is 0; attribute C_USE_ECC : integer; attribute C_USE_ECC of U0 : label is 0; attribute C_USE_SOFTECC : integer; attribute C_USE_SOFTECC of U0 : label is 0; attribute C_USE_URAM : integer; attribute C_USE_URAM of U0 : label is 0; attribute C_WEA_WIDTH : integer; attribute C_WEA_WIDTH of U0 : label is 1; attribute C_WEB_WIDTH : integer; attribute C_WEB_WIDTH of U0 : label is 1; attribute C_WRITE_DEPTH_A : integer; attribute C_WRITE_DEPTH_A of U0 : label is 1024; attribute C_WRITE_DEPTH_B : integer; attribute C_WRITE_DEPTH_B of U0 : label is 1024; attribute C_WRITE_MODE_A : string; attribute C_WRITE_MODE_A of U0 : label is "WRITE_FIRST"; attribute C_WRITE_MODE_B : string; attribute C_WRITE_MODE_B of U0 : label is "WRITE_FIRST"; attribute C_WRITE_WIDTH_A : integer; attribute C_WRITE_WIDTH_A of U0 : label is 20; attribute C_WRITE_WIDTH_B : integer; attribute C_WRITE_WIDTH_B of U0 : label is 20; attribute C_XDEVICEFAMILY : string; attribute C_XDEVICEFAMILY of U0 : label is "zynq"; attribute downgradeipidentifiedwarnings of U0 : label is "yes"; begin U0: entity work.bram_1024_3_blk_mem_gen_v8_3_5 port map ( addra(9 downto 0) => addra(9 downto 0), addrb(9 downto 0) => B"0000000000", clka => clka, clkb => '0', dbiterr => NLW_U0_dbiterr_UNCONNECTED, deepsleep => '0', dina(19 downto 0) => dina(19 downto 0), dinb(19 downto 0) => B"00000000000000000000", douta(19 downto 0) => douta(19 downto 0), doutb(19 downto 0) => NLW_U0_doutb_UNCONNECTED(19 downto 0), eccpipece => '0', ena => ena, enb => '0', injectdbiterr => '0', injectsbiterr => '0', rdaddrecc(9 downto 0) => NLW_U0_rdaddrecc_UNCONNECTED(9 downto 0), regcea => '0', regceb => '0', rsta => '0', rsta_busy => NLW_U0_rsta_busy_UNCONNECTED, rstb => '0', rstb_busy => NLW_U0_rstb_busy_UNCONNECTED, s_aclk => '0', s_aresetn => '0', s_axi_araddr(31 downto 0) => B"00000000000000000000000000000000", s_axi_arburst(1 downto 0) => B"00", s_axi_arid(3 downto 0) => B"0000", s_axi_arlen(7 downto 0) => B"00000000", s_axi_arready => NLW_U0_s_axi_arready_UNCONNECTED, s_axi_arsize(2 downto 0) => B"000", s_axi_arvalid => '0', s_axi_awaddr(31 downto 0) => B"00000000000000000000000000000000", s_axi_awburst(1 downto 0) => B"00", s_axi_awid(3 downto 0) => B"0000", s_axi_awlen(7 downto 0) => B"00000000", s_axi_awready => NLW_U0_s_axi_awready_UNCONNECTED, s_axi_awsize(2 downto 0) => B"000", s_axi_awvalid => '0', s_axi_bid(3 downto 0) => NLW_U0_s_axi_bid_UNCONNECTED(3 downto 0), s_axi_bready => '0', s_axi_bresp(1 downto 0) => NLW_U0_s_axi_bresp_UNCONNECTED(1 downto 0), s_axi_bvalid => NLW_U0_s_axi_bvalid_UNCONNECTED, s_axi_dbiterr => NLW_U0_s_axi_dbiterr_UNCONNECTED, s_axi_injectdbiterr => '0', s_axi_injectsbiterr => '0', s_axi_rdaddrecc(9 downto 0) => NLW_U0_s_axi_rdaddrecc_UNCONNECTED(9 downto 0), s_axi_rdata(19 downto 0) => NLW_U0_s_axi_rdata_UNCONNECTED(19 downto 0), s_axi_rid(3 downto 0) => NLW_U0_s_axi_rid_UNCONNECTED(3 downto 0), s_axi_rlast => NLW_U0_s_axi_rlast_UNCONNECTED, s_axi_rready => '0', s_axi_rresp(1 downto 0) => NLW_U0_s_axi_rresp_UNCONNECTED(1 downto 0), s_axi_rvalid => NLW_U0_s_axi_rvalid_UNCONNECTED, s_axi_sbiterr => NLW_U0_s_axi_sbiterr_UNCONNECTED, s_axi_wdata(19 downto 0) => B"00000000000000000000", s_axi_wlast => '0', s_axi_wready => NLW_U0_s_axi_wready_UNCONNECTED, s_axi_wstrb(0) => '0', s_axi_wvalid => '0', sbiterr => NLW_U0_sbiterr_UNCONNECTED, shutdown => '0', sleep => '0', wea(0) => wea(0), web(0) => '0' ); end STRUCTURE;
unlicense
d5360f92792751785bdd4af91b0be774
0.698719
3.46579
false
false
false
false
grwlf/vsim
vhdl/STD/standard_orig.vhd
1
2,611
-- This is Package STANDARD as defined in the VHDL 1992 Language Reference Manual. package standard is type boolean is (false,true); type bit is ('0', '1'); type character is ( nul, soh, stx, etx, eot, enq, ack, bel, bs, ht, lf, vt, ff, cr, so, si, dle, dc1, dc2, dc3, dc4, nak, syn, etb, can, em, sub, esc, fsp, gsp, rsp, usp, ' ', '!', '"', '#', '$', '%', '&', ''', '(', ')', '*', '+', ',', '-', '.', '/', '0', '1', '2', '3', '4', '5', '6', '7', '8', '9', ':', ';', '<', '=', '>', '?', '@', 'A', 'B', 'C', 'D', 'E', 'F', 'G', 'H', 'I', 'J', 'K', 'L', 'M', 'N', 'O', 'P', 'Q', 'R', 'S', 'T', 'U', 'V', 'W', 'X', 'Y', 'Z', '[', '\', ']', '^', '_', '`', 'a', 'b', 'c', 'd', 'e', 'f', 'g', 'h', 'i', 'j', 'k', 'l', 'm', 'n', 'o', 'p', 'q', 'r', 's', 't', 'u', 'v', 'w', 'x', 'y', 'z', '{', '|', '}', '~', del, c128, c129, c130, c131, c132, c133, c134, c135, c136, c137, c138, c139, c140, c141, c142, c143, c144, c145, c146, c147, c148, c149, c150, c151, c152, c153, c154, c155, c156, c157, c158, c159, -- the character code for 160 is there (NBSP), -- but prints as no char ' ', '¡', '¢', '£', '¤', '¥', '¦', '§', '¨', '©', 'ª', '«', '¬', '­', '®', '¯', '°', '±', '²', '³', '´', 'µ', '¶', '·', '¸', '¹', 'º', '»', '¼', '½', '¾', '¿', 'À', 'Á', 'Â', 'Ã', 'Ä', 'Å', 'Æ', 'Ç', 'È', 'É', 'Ê', 'Ë', 'Ì', 'Í', 'Î', 'Ï', 'Ð', 'Ñ', 'Ò', 'Ó', 'Ô', 'Õ', 'Ö', '×', 'Ø', 'Ù', 'Ú', 'Û', 'Ü', 'Ý', 'Þ', 'ß', 'à', 'á', 'â', 'ã', 'ä', 'å', 'æ', 'ç', 'è', 'é', 'ê', 'ë', 'ì', 'í', 'î', 'ï', 'ð', 'ñ', 'ò', 'ó', 'ô', 'õ', 'ö', '÷', 'ø', 'ù', 'ú', 'û', 'ü', 'ý', 'þ', 'ÿ' ); type severity_level is (note, warning, error, failure); type integer is range -2147483647 to 2147483647; type real is range -1.0E308 to 1.0E308; type time is range -2147483647 to 2147483647 units fs; ps = 1000 fs; ns = 1000 ps; us = 1000 ns; ms = 1000 us; sec = 1000 ms; min = 60 sec; hr = 60 min; end units; subtype delay_length is time range 0 fs to time'high; impure function now return delay_length; subtype natural is integer range 0 to integer'high; subtype positive is integer range 1 to integer'high; type string is array (positive range <>) of character; type bit_vector is array (natural range <>) of bit; type file_open_kind is ( read_mode, write_mode, append_mode); type file_open_status is ( open_ok, status_error, name_error, mode_error); attribute foreign : string; end standard;
gpl-3.0
9f43687ad3bd4e08f978f5c14e1ddad9
0.430103
2.365036
false
false
false
false
grwlf/vsim
vhdl/STD/textio.vhdl
2
5,335
-- Std.Textio package declaration. This file is part of GHDL. -- This file was written from the clause 14.3 of the VHDL LRM. -- Copyright (C) 2002, 2003, 2004, 2005 Tristan Gingold -- -- GHDL is free software; you can redistribute it and/or modify it under -- the terms of the GNU General Public License as published by the Free -- Software Foundation; either version 2, or (at your option) any later -- version. -- -- GHDL is distributed in the hope that it will be useful, but WITHOUT ANY -- WARRANTY; without even the implied warranty of MERCHANTABILITY or -- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -- for more details. -- -- You should have received a copy of the GNU General Public License -- along with GCC; see the file COPYING. If not, write to the Free -- Software Foundation, 59 Temple Place - Suite 330, Boston, MA -- 02111-1307, USA. package textio is -- type definitions for text i/o -- a LINE is a pointer to a string value. type line is access string; -- A file of variable-length ASCII records. -- Note: in order to work correctly, the TEXT file type must be declared in -- the textio package of library std. Otherwise, a file of string has a -- non-ASCII format. type text is file of string; type side is (right, left); -- For justifying ouput data within fields. subtype width is natural; -- For specifying widths of output fields. -- standard text files file input: text is in "STD_INPUT"; --V87 file output: text is out "STD_OUTPUT"; --V87 file input : text open read_mode is "STD_INPUT"; --V93 file output : text open write_mode is "STD_OUTPUT"; --V93 -- input routines for standard types procedure readline (variable f: in text; l: inout line); --V87 procedure readline (file f: text; l: inout line); --V93 -- For READ procedures: -- In this implementation, any L is accepted (ie, there is no constraints -- on direction, or left bound). Therefore, even variable of type LINE -- not initialized by READLINE are accepted. Strictly speaking, this is -- not required by LRM, nor prevented. However, other implementations may -- fail at parsing such strings. -- -- Also, in case of error (GOOD is false), this implementation do not -- modify L (as specified by the LRM) nor VALUE. -- -- For READ procedures without a GOOD argument, an assertion fails in case -- of error. -- -- In case of overflow (ie, if the number is out of the bounds of the type), -- the procedure will fail with an execution error. -- FIXME: this should not occur for a bad string. procedure read (l: inout line; value: out bit; good: out boolean); procedure read (l: inout line; value: out bit); procedure read (l: inout line; value: out bit_vector; good: out boolean); procedure read (l: inout line; value: out bit_vector); procedure read (l: inout line; value: out boolean; good: out boolean); procedure read (l: inout line; value: out boolean); procedure read (l: inout line; value: out character; good: out boolean); procedure read (l: inout line; value: out character); procedure read (l: inout line; value: out integer; good: out boolean); procedure read (l: inout line; value: out integer); procedure read (l: inout line; value: out real; good: out boolean); procedure read (l: inout line; value: out real); procedure read (l: inout line; value: out string; good: out boolean); procedure read (l: inout line; value: out string); -- This implementation requires no space after the unit identifier, -- ie "7.5 nsv" is parsed as 7.5 ns. -- The unit identifier can be in lower case, upper case or mixed case. procedure read (l: inout line; value: out time; good: out boolean); procedure read (l: inout line; value: out time); -- output routines for standard types procedure writeline (variable f: out text; l: inout line); --V87 procedure writeline (file f: text; l: inout line); --V93 -- This implementation accept any value for all the types. procedure write (l: inout line; value: in bit; justified: in side := right; field: in width := 0); procedure write (l: inout line; value: in bit_vector; justified: in side := right; field: in width := 0); procedure write (l: inout line; value: in boolean; justified: in side := right; field: in width := 0); procedure write (l: inout line; value: in character; justified: in side := right; field: in width := 0); procedure write (l: inout line; value: in integer; justified: in side := right; field: in width := 0); procedure write (L: inout line; value: in real; justified: in side := right; field: in width := 0; digits: in natural := 0); procedure write (l: inout line; value: in string; justified: in side := right; field: in width := 0); -- UNIT must be a unit name declared in std.standard. Of course, no rules -- in the core VHDL language prevent you from using a value that is not a -- unit (eg: 10 ns or even 5 fs). -- An assertion error message is generated in this case, and question mark -- (?) is written at the place of the unit name. procedure write (l: inout line; value : in time; justified: in side := right; field: in width := 0; unit : in TIME := ns); end textio;
gpl-3.0
d7a5e1799e2bab99c7a64f0e56c42b9b
0.685848
3.813438
false
false
false
false
jairov4/accel-oil
impl/impl_test_pcie/hdl/system_mdm_0_wrapper.vhd
1
39,103
------------------------------------------------------------------------------- -- system_mdm_0_wrapper.vhd ------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; library mdm_v2_10_a; use mdm_v2_10_a.all; entity system_mdm_0_wrapper is port ( Interrupt : out std_logic; Debug_SYS_Rst : out std_logic; Ext_BRK : out std_logic; Ext_NM_BRK : out std_logic; S_AXI_ACLK : in std_logic; S_AXI_ARESETN : in std_logic; S_AXI_AWADDR : in std_logic_vector(31 downto 0); S_AXI_AWVALID : in std_logic; S_AXI_AWREADY : out std_logic; S_AXI_WDATA : in std_logic_vector(31 downto 0); S_AXI_WSTRB : in std_logic_vector(3 downto 0); S_AXI_WVALID : in std_logic; S_AXI_WREADY : out std_logic; S_AXI_BRESP : out std_logic_vector(1 downto 0); S_AXI_BVALID : out std_logic; S_AXI_BREADY : in std_logic; S_AXI_ARADDR : in std_logic_vector(31 downto 0); S_AXI_ARVALID : in std_logic; S_AXI_ARREADY : out std_logic; S_AXI_RDATA : out std_logic_vector(31 downto 0); S_AXI_RRESP : out std_logic_vector(1 downto 0); S_AXI_RVALID : out std_logic; S_AXI_RREADY : in std_logic; SPLB_Clk : in std_logic; SPLB_Rst : in std_logic; PLB_ABus : in std_logic_vector(0 to 31); PLB_UABus : in std_logic_vector(0 to 31); PLB_PAValid : in std_logic; PLB_SAValid : in std_logic; PLB_rdPrim : in std_logic; PLB_wrPrim : in std_logic; PLB_masterID : in std_logic_vector(0 to 2); PLB_abort : in std_logic; PLB_busLock : in std_logic; PLB_RNW : in std_logic; PLB_BE : in std_logic_vector(0 to 7); PLB_MSize : in std_logic_vector(0 to 1); PLB_size : in std_logic_vector(0 to 3); PLB_type : in std_logic_vector(0 to 2); PLB_lockErr : in std_logic; PLB_wrDBus : in std_logic_vector(0 to 63); PLB_wrBurst : in std_logic; PLB_rdBurst : in std_logic; PLB_wrPendReq : in std_logic; PLB_rdPendReq : in std_logic; PLB_wrPendPri : in std_logic_vector(0 to 1); PLB_rdPendPri : in std_logic_vector(0 to 1); PLB_reqPri : in std_logic_vector(0 to 1); PLB_TAttribute : in std_logic_vector(0 to 15); Sl_addrAck : out std_logic; Sl_SSize : out std_logic_vector(0 to 1); Sl_wait : out std_logic; Sl_rearbitrate : out std_logic; Sl_wrDAck : out std_logic; Sl_wrComp : out std_logic; Sl_wrBTerm : out std_logic; Sl_rdDBus : out std_logic_vector(0 to 63); Sl_rdWdAddr : out std_logic_vector(0 to 3); Sl_rdDAck : out std_logic; Sl_rdComp : out std_logic; Sl_rdBTerm : out std_logic; Sl_MBusy : out std_logic_vector(0 to 5); Sl_MWrErr : out std_logic_vector(0 to 5); Sl_MRdErr : out std_logic_vector(0 to 5); Sl_MIRQ : out std_logic_vector(0 to 5); Dbg_Clk_0 : out std_logic; Dbg_TDI_0 : out std_logic; Dbg_TDO_0 : in std_logic; Dbg_Reg_En_0 : out std_logic_vector(0 to 7); Dbg_Capture_0 : out std_logic; Dbg_Shift_0 : out std_logic; Dbg_Update_0 : out std_logic; Dbg_Rst_0 : out std_logic; Dbg_Clk_1 : out std_logic; Dbg_TDI_1 : out std_logic; Dbg_TDO_1 : in std_logic; Dbg_Reg_En_1 : out std_logic_vector(0 to 7); Dbg_Capture_1 : out std_logic; Dbg_Shift_1 : out std_logic; Dbg_Update_1 : out std_logic; Dbg_Rst_1 : out std_logic; Dbg_Clk_2 : out std_logic; Dbg_TDI_2 : out std_logic; Dbg_TDO_2 : in std_logic; Dbg_Reg_En_2 : out std_logic_vector(0 to 7); Dbg_Capture_2 : out std_logic; Dbg_Shift_2 : out std_logic; Dbg_Update_2 : out std_logic; Dbg_Rst_2 : out std_logic; Dbg_Clk_3 : out std_logic; Dbg_TDI_3 : out std_logic; Dbg_TDO_3 : in std_logic; Dbg_Reg_En_3 : out std_logic_vector(0 to 7); Dbg_Capture_3 : out std_logic; Dbg_Shift_3 : out std_logic; Dbg_Update_3 : out std_logic; Dbg_Rst_3 : out std_logic; Dbg_Clk_4 : out std_logic; Dbg_TDI_4 : out std_logic; Dbg_TDO_4 : in std_logic; Dbg_Reg_En_4 : out std_logic_vector(0 to 7); Dbg_Capture_4 : out std_logic; Dbg_Shift_4 : out std_logic; Dbg_Update_4 : out std_logic; Dbg_Rst_4 : out std_logic; Dbg_Clk_5 : out std_logic; Dbg_TDI_5 : out std_logic; Dbg_TDO_5 : in std_logic; Dbg_Reg_En_5 : out std_logic_vector(0 to 7); Dbg_Capture_5 : out std_logic; Dbg_Shift_5 : out std_logic; Dbg_Update_5 : out std_logic; Dbg_Rst_5 : out std_logic; Dbg_Clk_6 : out std_logic; Dbg_TDI_6 : out std_logic; Dbg_TDO_6 : in std_logic; Dbg_Reg_En_6 : out std_logic_vector(0 to 7); Dbg_Capture_6 : out std_logic; Dbg_Shift_6 : out std_logic; Dbg_Update_6 : out std_logic; Dbg_Rst_6 : out std_logic; Dbg_Clk_7 : out std_logic; Dbg_TDI_7 : out std_logic; Dbg_TDO_7 : in std_logic; Dbg_Reg_En_7 : out std_logic_vector(0 to 7); Dbg_Capture_7 : out std_logic; Dbg_Shift_7 : out std_logic; Dbg_Update_7 : out std_logic; Dbg_Rst_7 : out std_logic; Dbg_Clk_8 : out std_logic; Dbg_TDI_8 : out std_logic; Dbg_TDO_8 : in std_logic; Dbg_Reg_En_8 : out std_logic_vector(0 to 7); Dbg_Capture_8 : out std_logic; Dbg_Shift_8 : out std_logic; Dbg_Update_8 : out std_logic; Dbg_Rst_8 : out std_logic; Dbg_Clk_9 : out std_logic; Dbg_TDI_9 : out std_logic; Dbg_TDO_9 : in std_logic; Dbg_Reg_En_9 : out std_logic_vector(0 to 7); Dbg_Capture_9 : out std_logic; Dbg_Shift_9 : out std_logic; Dbg_Update_9 : out std_logic; Dbg_Rst_9 : out std_logic; Dbg_Clk_10 : out std_logic; Dbg_TDI_10 : out std_logic; Dbg_TDO_10 : in std_logic; Dbg_Reg_En_10 : out std_logic_vector(0 to 7); Dbg_Capture_10 : out std_logic; Dbg_Shift_10 : out std_logic; Dbg_Update_10 : out std_logic; Dbg_Rst_10 : out std_logic; Dbg_Clk_11 : out std_logic; Dbg_TDI_11 : out std_logic; Dbg_TDO_11 : in std_logic; Dbg_Reg_En_11 : out std_logic_vector(0 to 7); Dbg_Capture_11 : out std_logic; Dbg_Shift_11 : out std_logic; Dbg_Update_11 : out std_logic; Dbg_Rst_11 : out std_logic; Dbg_Clk_12 : out std_logic; Dbg_TDI_12 : out std_logic; Dbg_TDO_12 : in std_logic; Dbg_Reg_En_12 : out std_logic_vector(0 to 7); Dbg_Capture_12 : out std_logic; Dbg_Shift_12 : out std_logic; Dbg_Update_12 : out std_logic; Dbg_Rst_12 : out std_logic; Dbg_Clk_13 : out std_logic; Dbg_TDI_13 : out std_logic; Dbg_TDO_13 : in std_logic; Dbg_Reg_En_13 : out std_logic_vector(0 to 7); Dbg_Capture_13 : out std_logic; Dbg_Shift_13 : out std_logic; Dbg_Update_13 : out std_logic; Dbg_Rst_13 : out std_logic; Dbg_Clk_14 : out std_logic; Dbg_TDI_14 : out std_logic; Dbg_TDO_14 : in std_logic; Dbg_Reg_En_14 : out std_logic_vector(0 to 7); Dbg_Capture_14 : out std_logic; Dbg_Shift_14 : out std_logic; Dbg_Update_14 : out std_logic; Dbg_Rst_14 : out std_logic; Dbg_Clk_15 : out std_logic; Dbg_TDI_15 : out std_logic; Dbg_TDO_15 : in std_logic; Dbg_Reg_En_15 : out std_logic_vector(0 to 7); Dbg_Capture_15 : out std_logic; Dbg_Shift_15 : out std_logic; Dbg_Update_15 : out std_logic; Dbg_Rst_15 : out std_logic; Dbg_Clk_16 : out std_logic; Dbg_TDI_16 : out std_logic; Dbg_TDO_16 : in std_logic; Dbg_Reg_En_16 : out std_logic_vector(0 to 7); Dbg_Capture_16 : out std_logic; Dbg_Shift_16 : out std_logic; Dbg_Update_16 : out std_logic; Dbg_Rst_16 : out std_logic; Dbg_Clk_17 : out std_logic; Dbg_TDI_17 : out std_logic; Dbg_TDO_17 : in std_logic; Dbg_Reg_En_17 : out std_logic_vector(0 to 7); Dbg_Capture_17 : out std_logic; Dbg_Shift_17 : out std_logic; Dbg_Update_17 : out std_logic; Dbg_Rst_17 : out std_logic; Dbg_Clk_18 : out std_logic; Dbg_TDI_18 : out std_logic; Dbg_TDO_18 : in std_logic; Dbg_Reg_En_18 : out std_logic_vector(0 to 7); Dbg_Capture_18 : out std_logic; Dbg_Shift_18 : out std_logic; Dbg_Update_18 : out std_logic; Dbg_Rst_18 : out std_logic; Dbg_Clk_19 : out std_logic; Dbg_TDI_19 : out std_logic; Dbg_TDO_19 : in std_logic; Dbg_Reg_En_19 : out std_logic_vector(0 to 7); Dbg_Capture_19 : out std_logic; Dbg_Shift_19 : out std_logic; Dbg_Update_19 : out std_logic; Dbg_Rst_19 : out std_logic; Dbg_Clk_20 : out std_logic; Dbg_TDI_20 : out std_logic; Dbg_TDO_20 : in std_logic; Dbg_Reg_En_20 : out std_logic_vector(0 to 7); Dbg_Capture_20 : out std_logic; Dbg_Shift_20 : out std_logic; Dbg_Update_20 : out std_logic; Dbg_Rst_20 : out std_logic; Dbg_Clk_21 : out std_logic; Dbg_TDI_21 : out std_logic; Dbg_TDO_21 : in std_logic; Dbg_Reg_En_21 : out std_logic_vector(0 to 7); Dbg_Capture_21 : out std_logic; Dbg_Shift_21 : out std_logic; Dbg_Update_21 : out std_logic; Dbg_Rst_21 : out std_logic; Dbg_Clk_22 : out std_logic; Dbg_TDI_22 : out std_logic; Dbg_TDO_22 : in std_logic; Dbg_Reg_En_22 : out std_logic_vector(0 to 7); Dbg_Capture_22 : out std_logic; Dbg_Shift_22 : out std_logic; Dbg_Update_22 : out std_logic; Dbg_Rst_22 : out std_logic; Dbg_Clk_23 : out std_logic; Dbg_TDI_23 : out std_logic; Dbg_TDO_23 : in std_logic; Dbg_Reg_En_23 : out std_logic_vector(0 to 7); Dbg_Capture_23 : out std_logic; Dbg_Shift_23 : out std_logic; Dbg_Update_23 : out std_logic; Dbg_Rst_23 : out std_logic; Dbg_Clk_24 : out std_logic; Dbg_TDI_24 : out std_logic; Dbg_TDO_24 : in std_logic; Dbg_Reg_En_24 : out std_logic_vector(0 to 7); Dbg_Capture_24 : out std_logic; Dbg_Shift_24 : out std_logic; Dbg_Update_24 : out std_logic; Dbg_Rst_24 : out std_logic; Dbg_Clk_25 : out std_logic; Dbg_TDI_25 : out std_logic; Dbg_TDO_25 : in std_logic; Dbg_Reg_En_25 : out std_logic_vector(0 to 7); Dbg_Capture_25 : out std_logic; Dbg_Shift_25 : out std_logic; Dbg_Update_25 : out std_logic; Dbg_Rst_25 : out std_logic; Dbg_Clk_26 : out std_logic; Dbg_TDI_26 : out std_logic; Dbg_TDO_26 : in std_logic; Dbg_Reg_En_26 : out std_logic_vector(0 to 7); Dbg_Capture_26 : out std_logic; Dbg_Shift_26 : out std_logic; Dbg_Update_26 : out std_logic; Dbg_Rst_26 : out std_logic; Dbg_Clk_27 : out std_logic; Dbg_TDI_27 : out std_logic; Dbg_TDO_27 : in std_logic; Dbg_Reg_En_27 : out std_logic_vector(0 to 7); Dbg_Capture_27 : out std_logic; Dbg_Shift_27 : out std_logic; Dbg_Update_27 : out std_logic; Dbg_Rst_27 : out std_logic; Dbg_Clk_28 : out std_logic; Dbg_TDI_28 : out std_logic; Dbg_TDO_28 : in std_logic; Dbg_Reg_En_28 : out std_logic_vector(0 to 7); Dbg_Capture_28 : out std_logic; Dbg_Shift_28 : out std_logic; Dbg_Update_28 : out std_logic; Dbg_Rst_28 : out std_logic; Dbg_Clk_29 : out std_logic; Dbg_TDI_29 : out std_logic; Dbg_TDO_29 : in std_logic; Dbg_Reg_En_29 : out std_logic_vector(0 to 7); Dbg_Capture_29 : out std_logic; Dbg_Shift_29 : out std_logic; Dbg_Update_29 : out std_logic; Dbg_Rst_29 : out std_logic; Dbg_Clk_30 : out std_logic; Dbg_TDI_30 : out std_logic; Dbg_TDO_30 : in std_logic; Dbg_Reg_En_30 : out std_logic_vector(0 to 7); Dbg_Capture_30 : out std_logic; Dbg_Shift_30 : out std_logic; Dbg_Update_30 : out std_logic; Dbg_Rst_30 : out std_logic; Dbg_Clk_31 : out std_logic; Dbg_TDI_31 : out std_logic; Dbg_TDO_31 : in std_logic; Dbg_Reg_En_31 : out std_logic_vector(0 to 7); Dbg_Capture_31 : out std_logic; Dbg_Shift_31 : out std_logic; Dbg_Update_31 : out std_logic; Dbg_Rst_31 : out std_logic; bscan_tdi : out std_logic; bscan_reset : out std_logic; bscan_shift : out std_logic; bscan_update : out std_logic; bscan_capture : out std_logic; bscan_sel1 : out std_logic; bscan_drck1 : out std_logic; bscan_tdo1 : in std_logic; bscan_ext_tdi : in std_logic; bscan_ext_reset : in std_logic; bscan_ext_shift : in std_logic; bscan_ext_update : in std_logic; bscan_ext_capture : in std_logic; bscan_ext_sel : in std_logic; bscan_ext_drck : in std_logic; bscan_ext_tdo : out std_logic; Ext_JTAG_DRCK : out std_logic; Ext_JTAG_RESET : out std_logic; Ext_JTAG_SEL : out std_logic; Ext_JTAG_CAPTURE : out std_logic; Ext_JTAG_SHIFT : out std_logic; Ext_JTAG_UPDATE : out std_logic; Ext_JTAG_TDI : out std_logic; Ext_JTAG_TDO : in std_logic ); attribute x_core_info : STRING; attribute x_core_info of system_mdm_0_wrapper : entity is "mdm_v2_10_a"; end system_mdm_0_wrapper; architecture STRUCTURE of system_mdm_0_wrapper is component mdm is generic ( C_FAMILY : STRING; C_JTAG_CHAIN : INTEGER; C_INTERCONNECT : INTEGER; C_BASEADDR : STD_LOGIC_VECTOR; C_HIGHADDR : STD_LOGIC_VECTOR; C_SPLB_AWIDTH : INTEGER; C_SPLB_DWIDTH : INTEGER; C_SPLB_P2P : INTEGER; C_SPLB_MID_WIDTH : INTEGER; C_SPLB_NUM_MASTERS : INTEGER; C_SPLB_NATIVE_DWIDTH : INTEGER; C_SPLB_SUPPORT_BURSTS : INTEGER; C_MB_DBG_PORTS : INTEGER; C_USE_UART : INTEGER; C_USE_BSCAN : integer; C_S_AXI_ADDR_WIDTH : INTEGER; C_S_AXI_DATA_WIDTH : INTEGER ); port ( Interrupt : out std_logic; Debug_SYS_Rst : out std_logic; Ext_BRK : out std_logic; Ext_NM_BRK : out std_logic; S_AXI_ACLK : in std_logic; S_AXI_ARESETN : in std_logic; S_AXI_AWADDR : in std_logic_vector((C_S_AXI_ADDR_WIDTH-1) downto 0); S_AXI_AWVALID : in std_logic; S_AXI_AWREADY : out std_logic; S_AXI_WDATA : in std_logic_vector((C_S_AXI_DATA_WIDTH-1) downto 0); S_AXI_WSTRB : in std_logic_vector((C_S_AXI_DATA_WIDTH/8-1) downto 0); S_AXI_WVALID : in std_logic; S_AXI_WREADY : out std_logic; S_AXI_BRESP : out std_logic_vector(1 downto 0); S_AXI_BVALID : out std_logic; S_AXI_BREADY : in std_logic; S_AXI_ARADDR : in std_logic_vector((C_S_AXI_ADDR_WIDTH-1) downto 0); S_AXI_ARVALID : in std_logic; S_AXI_ARREADY : out std_logic; S_AXI_RDATA : out std_logic_vector((C_S_AXI_DATA_WIDTH-1) downto 0); S_AXI_RRESP : out std_logic_vector(1 downto 0); S_AXI_RVALID : out std_logic; S_AXI_RREADY : in std_logic; SPLB_Clk : in std_logic; SPLB_Rst : in std_logic; PLB_ABus : in std_logic_vector(0 to 31); PLB_UABus : in std_logic_vector(0 to 31); PLB_PAValid : in std_logic; PLB_SAValid : in std_logic; PLB_rdPrim : in std_logic; PLB_wrPrim : in std_logic; PLB_masterID : in std_logic_vector(0 to (C_SPLB_MID_WIDTH-1)); PLB_abort : in std_logic; PLB_busLock : in std_logic; PLB_RNW : in std_logic; PLB_BE : in std_logic_vector(0 to ((C_SPLB_DWIDTH/8)-1)); PLB_MSize : in std_logic_vector(0 to 1); PLB_size : in std_logic_vector(0 to 3); PLB_type : in std_logic_vector(0 to 2); PLB_lockErr : in std_logic; PLB_wrDBus : in std_logic_vector(0 to (C_SPLB_DWIDTH-1)); PLB_wrBurst : in std_logic; PLB_rdBurst : in std_logic; PLB_wrPendReq : in std_logic; PLB_rdPendReq : in std_logic; PLB_wrPendPri : in std_logic_vector(0 to 1); PLB_rdPendPri : in std_logic_vector(0 to 1); PLB_reqPri : in std_logic_vector(0 to 1); PLB_TAttribute : in std_logic_vector(0 to 15); Sl_addrAck : out std_logic; Sl_SSize : out std_logic_vector(0 to 1); Sl_wait : out std_logic; Sl_rearbitrate : out std_logic; Sl_wrDAck : out std_logic; Sl_wrComp : out std_logic; Sl_wrBTerm : out std_logic; Sl_rdDBus : out std_logic_vector(0 to (C_SPLB_DWIDTH-1)); Sl_rdWdAddr : out std_logic_vector(0 to 3); Sl_rdDAck : out std_logic; Sl_rdComp : out std_logic; Sl_rdBTerm : out std_logic; Sl_MBusy : out std_logic_vector(0 to (C_SPLB_NUM_MASTERS-1)); Sl_MWrErr : out std_logic_vector(0 to (C_SPLB_NUM_MASTERS-1)); Sl_MRdErr : out std_logic_vector(0 to (C_SPLB_NUM_MASTERS-1)); Sl_MIRQ : out std_logic_vector(0 to (C_SPLB_NUM_MASTERS-1)); Dbg_Clk_0 : out std_logic; Dbg_TDI_0 : out std_logic; Dbg_TDO_0 : in std_logic; Dbg_Reg_En_0 : out std_logic_vector(0 to 7); Dbg_Capture_0 : out std_logic; Dbg_Shift_0 : out std_logic; Dbg_Update_0 : out std_logic; Dbg_Rst_0 : out std_logic; Dbg_Clk_1 : out std_logic; Dbg_TDI_1 : out std_logic; Dbg_TDO_1 : in std_logic; Dbg_Reg_En_1 : out std_logic_vector(0 to 7); Dbg_Capture_1 : out std_logic; Dbg_Shift_1 : out std_logic; Dbg_Update_1 : out std_logic; Dbg_Rst_1 : out std_logic; Dbg_Clk_2 : out std_logic; Dbg_TDI_2 : out std_logic; Dbg_TDO_2 : in std_logic; Dbg_Reg_En_2 : out std_logic_vector(0 to 7); Dbg_Capture_2 : out std_logic; Dbg_Shift_2 : out std_logic; Dbg_Update_2 : out std_logic; Dbg_Rst_2 : out std_logic; Dbg_Clk_3 : out std_logic; Dbg_TDI_3 : out std_logic; Dbg_TDO_3 : in std_logic; Dbg_Reg_En_3 : out std_logic_vector(0 to 7); Dbg_Capture_3 : out std_logic; Dbg_Shift_3 : out std_logic; Dbg_Update_3 : out std_logic; Dbg_Rst_3 : out std_logic; Dbg_Clk_4 : out std_logic; Dbg_TDI_4 : out std_logic; Dbg_TDO_4 : in std_logic; Dbg_Reg_En_4 : out std_logic_vector(0 to 7); Dbg_Capture_4 : out std_logic; Dbg_Shift_4 : out std_logic; Dbg_Update_4 : out std_logic; Dbg_Rst_4 : out std_logic; Dbg_Clk_5 : out std_logic; Dbg_TDI_5 : out std_logic; Dbg_TDO_5 : in std_logic; Dbg_Reg_En_5 : out std_logic_vector(0 to 7); Dbg_Capture_5 : out std_logic; Dbg_Shift_5 : out std_logic; Dbg_Update_5 : out std_logic; Dbg_Rst_5 : out std_logic; Dbg_Clk_6 : out std_logic; Dbg_TDI_6 : out std_logic; Dbg_TDO_6 : in std_logic; Dbg_Reg_En_6 : out std_logic_vector(0 to 7); Dbg_Capture_6 : out std_logic; Dbg_Shift_6 : out std_logic; Dbg_Update_6 : out std_logic; Dbg_Rst_6 : out std_logic; Dbg_Clk_7 : out std_logic; Dbg_TDI_7 : out std_logic; Dbg_TDO_7 : in std_logic; Dbg_Reg_En_7 : out std_logic_vector(0 to 7); Dbg_Capture_7 : out std_logic; Dbg_Shift_7 : out std_logic; Dbg_Update_7 : out std_logic; Dbg_Rst_7 : out std_logic; Dbg_Clk_8 : out std_logic; Dbg_TDI_8 : out std_logic; Dbg_TDO_8 : in std_logic; Dbg_Reg_En_8 : out std_logic_vector(0 to 7); Dbg_Capture_8 : out std_logic; Dbg_Shift_8 : out std_logic; Dbg_Update_8 : out std_logic; Dbg_Rst_8 : out std_logic; Dbg_Clk_9 : out std_logic; Dbg_TDI_9 : out std_logic; Dbg_TDO_9 : in std_logic; Dbg_Reg_En_9 : out std_logic_vector(0 to 7); Dbg_Capture_9 : out std_logic; Dbg_Shift_9 : out std_logic; Dbg_Update_9 : out std_logic; Dbg_Rst_9 : out std_logic; Dbg_Clk_10 : out std_logic; Dbg_TDI_10 : out std_logic; Dbg_TDO_10 : in std_logic; Dbg_Reg_En_10 : out std_logic_vector(0 to 7); Dbg_Capture_10 : out std_logic; Dbg_Shift_10 : out std_logic; Dbg_Update_10 : out std_logic; Dbg_Rst_10 : out std_logic; Dbg_Clk_11 : out std_logic; Dbg_TDI_11 : out std_logic; Dbg_TDO_11 : in std_logic; Dbg_Reg_En_11 : out std_logic_vector(0 to 7); Dbg_Capture_11 : out std_logic; Dbg_Shift_11 : out std_logic; Dbg_Update_11 : out std_logic; Dbg_Rst_11 : out std_logic; Dbg_Clk_12 : out std_logic; Dbg_TDI_12 : out std_logic; Dbg_TDO_12 : in std_logic; Dbg_Reg_En_12 : out std_logic_vector(0 to 7); Dbg_Capture_12 : out std_logic; Dbg_Shift_12 : out std_logic; Dbg_Update_12 : out std_logic; Dbg_Rst_12 : out std_logic; Dbg_Clk_13 : out std_logic; Dbg_TDI_13 : out std_logic; Dbg_TDO_13 : in std_logic; Dbg_Reg_En_13 : out std_logic_vector(0 to 7); Dbg_Capture_13 : out std_logic; Dbg_Shift_13 : out std_logic; Dbg_Update_13 : out std_logic; Dbg_Rst_13 : out std_logic; Dbg_Clk_14 : out std_logic; Dbg_TDI_14 : out std_logic; Dbg_TDO_14 : in std_logic; Dbg_Reg_En_14 : out std_logic_vector(0 to 7); Dbg_Capture_14 : out std_logic; Dbg_Shift_14 : out std_logic; Dbg_Update_14 : out std_logic; Dbg_Rst_14 : out std_logic; Dbg_Clk_15 : out std_logic; Dbg_TDI_15 : out std_logic; Dbg_TDO_15 : in std_logic; Dbg_Reg_En_15 : out std_logic_vector(0 to 7); Dbg_Capture_15 : out std_logic; Dbg_Shift_15 : out std_logic; Dbg_Update_15 : out std_logic; Dbg_Rst_15 : out std_logic; Dbg_Clk_16 : out std_logic; Dbg_TDI_16 : out std_logic; Dbg_TDO_16 : in std_logic; Dbg_Reg_En_16 : out std_logic_vector(0 to 7); Dbg_Capture_16 : out std_logic; Dbg_Shift_16 : out std_logic; Dbg_Update_16 : out std_logic; Dbg_Rst_16 : out std_logic; Dbg_Clk_17 : out std_logic; Dbg_TDI_17 : out std_logic; Dbg_TDO_17 : in std_logic; Dbg_Reg_En_17 : out std_logic_vector(0 to 7); Dbg_Capture_17 : out std_logic; Dbg_Shift_17 : out std_logic; Dbg_Update_17 : out std_logic; Dbg_Rst_17 : out std_logic; Dbg_Clk_18 : out std_logic; Dbg_TDI_18 : out std_logic; Dbg_TDO_18 : in std_logic; Dbg_Reg_En_18 : out std_logic_vector(0 to 7); Dbg_Capture_18 : out std_logic; Dbg_Shift_18 : out std_logic; Dbg_Update_18 : out std_logic; Dbg_Rst_18 : out std_logic; Dbg_Clk_19 : out std_logic; Dbg_TDI_19 : out std_logic; Dbg_TDO_19 : in std_logic; Dbg_Reg_En_19 : out std_logic_vector(0 to 7); Dbg_Capture_19 : out std_logic; Dbg_Shift_19 : out std_logic; Dbg_Update_19 : out std_logic; Dbg_Rst_19 : out std_logic; Dbg_Clk_20 : out std_logic; Dbg_TDI_20 : out std_logic; Dbg_TDO_20 : in std_logic; Dbg_Reg_En_20 : out std_logic_vector(0 to 7); Dbg_Capture_20 : out std_logic; Dbg_Shift_20 : out std_logic; Dbg_Update_20 : out std_logic; Dbg_Rst_20 : out std_logic; Dbg_Clk_21 : out std_logic; Dbg_TDI_21 : out std_logic; Dbg_TDO_21 : in std_logic; Dbg_Reg_En_21 : out std_logic_vector(0 to 7); Dbg_Capture_21 : out std_logic; Dbg_Shift_21 : out std_logic; Dbg_Update_21 : out std_logic; Dbg_Rst_21 : out std_logic; Dbg_Clk_22 : out std_logic; Dbg_TDI_22 : out std_logic; Dbg_TDO_22 : in std_logic; Dbg_Reg_En_22 : out std_logic_vector(0 to 7); Dbg_Capture_22 : out std_logic; Dbg_Shift_22 : out std_logic; Dbg_Update_22 : out std_logic; Dbg_Rst_22 : out std_logic; Dbg_Clk_23 : out std_logic; Dbg_TDI_23 : out std_logic; Dbg_TDO_23 : in std_logic; Dbg_Reg_En_23 : out std_logic_vector(0 to 7); Dbg_Capture_23 : out std_logic; Dbg_Shift_23 : out std_logic; Dbg_Update_23 : out std_logic; Dbg_Rst_23 : out std_logic; Dbg_Clk_24 : out std_logic; Dbg_TDI_24 : out std_logic; Dbg_TDO_24 : in std_logic; Dbg_Reg_En_24 : out std_logic_vector(0 to 7); Dbg_Capture_24 : out std_logic; Dbg_Shift_24 : out std_logic; Dbg_Update_24 : out std_logic; Dbg_Rst_24 : out std_logic; Dbg_Clk_25 : out std_logic; Dbg_TDI_25 : out std_logic; Dbg_TDO_25 : in std_logic; Dbg_Reg_En_25 : out std_logic_vector(0 to 7); Dbg_Capture_25 : out std_logic; Dbg_Shift_25 : out std_logic; Dbg_Update_25 : out std_logic; Dbg_Rst_25 : out std_logic; Dbg_Clk_26 : out std_logic; Dbg_TDI_26 : out std_logic; Dbg_TDO_26 : in std_logic; Dbg_Reg_En_26 : out std_logic_vector(0 to 7); Dbg_Capture_26 : out std_logic; Dbg_Shift_26 : out std_logic; Dbg_Update_26 : out std_logic; Dbg_Rst_26 : out std_logic; Dbg_Clk_27 : out std_logic; Dbg_TDI_27 : out std_logic; Dbg_TDO_27 : in std_logic; Dbg_Reg_En_27 : out std_logic_vector(0 to 7); Dbg_Capture_27 : out std_logic; Dbg_Shift_27 : out std_logic; Dbg_Update_27 : out std_logic; Dbg_Rst_27 : out std_logic; Dbg_Clk_28 : out std_logic; Dbg_TDI_28 : out std_logic; Dbg_TDO_28 : in std_logic; Dbg_Reg_En_28 : out std_logic_vector(0 to 7); Dbg_Capture_28 : out std_logic; Dbg_Shift_28 : out std_logic; Dbg_Update_28 : out std_logic; Dbg_Rst_28 : out std_logic; Dbg_Clk_29 : out std_logic; Dbg_TDI_29 : out std_logic; Dbg_TDO_29 : in std_logic; Dbg_Reg_En_29 : out std_logic_vector(0 to 7); Dbg_Capture_29 : out std_logic; Dbg_Shift_29 : out std_logic; Dbg_Update_29 : out std_logic; Dbg_Rst_29 : out std_logic; Dbg_Clk_30 : out std_logic; Dbg_TDI_30 : out std_logic; Dbg_TDO_30 : in std_logic; Dbg_Reg_En_30 : out std_logic_vector(0 to 7); Dbg_Capture_30 : out std_logic; Dbg_Shift_30 : out std_logic; Dbg_Update_30 : out std_logic; Dbg_Rst_30 : out std_logic; Dbg_Clk_31 : out std_logic; Dbg_TDI_31 : out std_logic; Dbg_TDO_31 : in std_logic; Dbg_Reg_En_31 : out std_logic_vector(0 to 7); Dbg_Capture_31 : out std_logic; Dbg_Shift_31 : out std_logic; Dbg_Update_31 : out std_logic; Dbg_Rst_31 : out std_logic; bscan_tdi : out std_logic; bscan_reset : out std_logic; bscan_shift : out std_logic; bscan_update : out std_logic; bscan_capture : out std_logic; bscan_sel1 : out std_logic; bscan_drck1 : out std_logic; bscan_tdo1 : in std_logic; bscan_ext_tdi : in std_logic; bscan_ext_reset : in std_logic; bscan_ext_shift : in std_logic; bscan_ext_update : in std_logic; bscan_ext_capture : in std_logic; bscan_ext_sel : in std_logic; bscan_ext_drck : in std_logic; bscan_ext_tdo : out std_logic; Ext_JTAG_DRCK : out std_logic; Ext_JTAG_RESET : out std_logic; Ext_JTAG_SEL : out std_logic; Ext_JTAG_CAPTURE : out std_logic; Ext_JTAG_SHIFT : out std_logic; Ext_JTAG_UPDATE : out std_logic; Ext_JTAG_TDI : out std_logic; Ext_JTAG_TDO : in std_logic ); end component; begin mdm_0 : mdm generic map ( C_FAMILY => "virtex5", C_JTAG_CHAIN => 2, C_INTERCONNECT => 1, C_BASEADDR => X"84400000", C_HIGHADDR => X"8440ffff", C_SPLB_AWIDTH => 32, C_SPLB_DWIDTH => 64, C_SPLB_P2P => 0, C_SPLB_MID_WIDTH => 3, C_SPLB_NUM_MASTERS => 6, C_SPLB_NATIVE_DWIDTH => 32, C_SPLB_SUPPORT_BURSTS => 1, C_MB_DBG_PORTS => 1, C_USE_UART => 1, C_USE_BSCAN => 0, C_S_AXI_ADDR_WIDTH => 32, C_S_AXI_DATA_WIDTH => 32 ) port map ( Interrupt => Interrupt, Debug_SYS_Rst => Debug_SYS_Rst, Ext_BRK => Ext_BRK, Ext_NM_BRK => Ext_NM_BRK, S_AXI_ACLK => S_AXI_ACLK, S_AXI_ARESETN => S_AXI_ARESETN, S_AXI_AWADDR => S_AXI_AWADDR, S_AXI_AWVALID => S_AXI_AWVALID, S_AXI_AWREADY => S_AXI_AWREADY, S_AXI_WDATA => S_AXI_WDATA, S_AXI_WSTRB => S_AXI_WSTRB, S_AXI_WVALID => S_AXI_WVALID, S_AXI_WREADY => S_AXI_WREADY, S_AXI_BRESP => S_AXI_BRESP, S_AXI_BVALID => S_AXI_BVALID, S_AXI_BREADY => S_AXI_BREADY, S_AXI_ARADDR => S_AXI_ARADDR, S_AXI_ARVALID => S_AXI_ARVALID, S_AXI_ARREADY => S_AXI_ARREADY, S_AXI_RDATA => S_AXI_RDATA, S_AXI_RRESP => S_AXI_RRESP, S_AXI_RVALID => S_AXI_RVALID, S_AXI_RREADY => S_AXI_RREADY, SPLB_Clk => SPLB_Clk, SPLB_Rst => SPLB_Rst, PLB_ABus => PLB_ABus, PLB_UABus => PLB_UABus, PLB_PAValid => PLB_PAValid, PLB_SAValid => PLB_SAValid, PLB_rdPrim => PLB_rdPrim, PLB_wrPrim => PLB_wrPrim, PLB_masterID => PLB_masterID, PLB_abort => PLB_abort, PLB_busLock => PLB_busLock, PLB_RNW => PLB_RNW, PLB_BE => PLB_BE, PLB_MSize => PLB_MSize, PLB_size => PLB_size, PLB_type => PLB_type, PLB_lockErr => PLB_lockErr, PLB_wrDBus => PLB_wrDBus, PLB_wrBurst => PLB_wrBurst, PLB_rdBurst => PLB_rdBurst, PLB_wrPendReq => PLB_wrPendReq, PLB_rdPendReq => PLB_rdPendReq, PLB_wrPendPri => PLB_wrPendPri, PLB_rdPendPri => PLB_rdPendPri, PLB_reqPri => PLB_reqPri, PLB_TAttribute => PLB_TAttribute, Sl_addrAck => Sl_addrAck, Sl_SSize => Sl_SSize, Sl_wait => Sl_wait, Sl_rearbitrate => Sl_rearbitrate, Sl_wrDAck => Sl_wrDAck, Sl_wrComp => Sl_wrComp, Sl_wrBTerm => Sl_wrBTerm, Sl_rdDBus => Sl_rdDBus, Sl_rdWdAddr => Sl_rdWdAddr, Sl_rdDAck => Sl_rdDAck, Sl_rdComp => Sl_rdComp, Sl_rdBTerm => Sl_rdBTerm, Sl_MBusy => Sl_MBusy, Sl_MWrErr => Sl_MWrErr, Sl_MRdErr => Sl_MRdErr, Sl_MIRQ => Sl_MIRQ, Dbg_Clk_0 => Dbg_Clk_0, Dbg_TDI_0 => Dbg_TDI_0, Dbg_TDO_0 => Dbg_TDO_0, Dbg_Reg_En_0 => Dbg_Reg_En_0, Dbg_Capture_0 => Dbg_Capture_0, Dbg_Shift_0 => Dbg_Shift_0, Dbg_Update_0 => Dbg_Update_0, Dbg_Rst_0 => Dbg_Rst_0, Dbg_Clk_1 => Dbg_Clk_1, Dbg_TDI_1 => Dbg_TDI_1, Dbg_TDO_1 => Dbg_TDO_1, Dbg_Reg_En_1 => Dbg_Reg_En_1, Dbg_Capture_1 => Dbg_Capture_1, Dbg_Shift_1 => Dbg_Shift_1, Dbg_Update_1 => Dbg_Update_1, Dbg_Rst_1 => Dbg_Rst_1, Dbg_Clk_2 => Dbg_Clk_2, Dbg_TDI_2 => Dbg_TDI_2, Dbg_TDO_2 => Dbg_TDO_2, Dbg_Reg_En_2 => Dbg_Reg_En_2, Dbg_Capture_2 => Dbg_Capture_2, Dbg_Shift_2 => Dbg_Shift_2, Dbg_Update_2 => Dbg_Update_2, Dbg_Rst_2 => Dbg_Rst_2, Dbg_Clk_3 => Dbg_Clk_3, Dbg_TDI_3 => Dbg_TDI_3, Dbg_TDO_3 => Dbg_TDO_3, Dbg_Reg_En_3 => Dbg_Reg_En_3, Dbg_Capture_3 => Dbg_Capture_3, Dbg_Shift_3 => Dbg_Shift_3, Dbg_Update_3 => Dbg_Update_3, Dbg_Rst_3 => Dbg_Rst_3, Dbg_Clk_4 => Dbg_Clk_4, Dbg_TDI_4 => Dbg_TDI_4, Dbg_TDO_4 => Dbg_TDO_4, Dbg_Reg_En_4 => Dbg_Reg_En_4, Dbg_Capture_4 => Dbg_Capture_4, Dbg_Shift_4 => Dbg_Shift_4, Dbg_Update_4 => Dbg_Update_4, Dbg_Rst_4 => Dbg_Rst_4, Dbg_Clk_5 => Dbg_Clk_5, Dbg_TDI_5 => Dbg_TDI_5, Dbg_TDO_5 => Dbg_TDO_5, Dbg_Reg_En_5 => Dbg_Reg_En_5, Dbg_Capture_5 => Dbg_Capture_5, Dbg_Shift_5 => Dbg_Shift_5, Dbg_Update_5 => Dbg_Update_5, Dbg_Rst_5 => Dbg_Rst_5, Dbg_Clk_6 => Dbg_Clk_6, Dbg_TDI_6 => Dbg_TDI_6, Dbg_TDO_6 => Dbg_TDO_6, Dbg_Reg_En_6 => Dbg_Reg_En_6, Dbg_Capture_6 => Dbg_Capture_6, Dbg_Shift_6 => Dbg_Shift_6, Dbg_Update_6 => Dbg_Update_6, Dbg_Rst_6 => Dbg_Rst_6, Dbg_Clk_7 => Dbg_Clk_7, Dbg_TDI_7 => Dbg_TDI_7, Dbg_TDO_7 => Dbg_TDO_7, Dbg_Reg_En_7 => Dbg_Reg_En_7, Dbg_Capture_7 => Dbg_Capture_7, Dbg_Shift_7 => Dbg_Shift_7, Dbg_Update_7 => Dbg_Update_7, Dbg_Rst_7 => Dbg_Rst_7, Dbg_Clk_8 => Dbg_Clk_8, Dbg_TDI_8 => Dbg_TDI_8, Dbg_TDO_8 => Dbg_TDO_8, Dbg_Reg_En_8 => Dbg_Reg_En_8, Dbg_Capture_8 => Dbg_Capture_8, Dbg_Shift_8 => Dbg_Shift_8, Dbg_Update_8 => Dbg_Update_8, Dbg_Rst_8 => Dbg_Rst_8, Dbg_Clk_9 => Dbg_Clk_9, Dbg_TDI_9 => Dbg_TDI_9, Dbg_TDO_9 => Dbg_TDO_9, Dbg_Reg_En_9 => Dbg_Reg_En_9, Dbg_Capture_9 => Dbg_Capture_9, Dbg_Shift_9 => Dbg_Shift_9, Dbg_Update_9 => Dbg_Update_9, Dbg_Rst_9 => Dbg_Rst_9, Dbg_Clk_10 => Dbg_Clk_10, Dbg_TDI_10 => Dbg_TDI_10, Dbg_TDO_10 => Dbg_TDO_10, Dbg_Reg_En_10 => Dbg_Reg_En_10, Dbg_Capture_10 => Dbg_Capture_10, Dbg_Shift_10 => Dbg_Shift_10, Dbg_Update_10 => Dbg_Update_10, Dbg_Rst_10 => Dbg_Rst_10, Dbg_Clk_11 => Dbg_Clk_11, Dbg_TDI_11 => Dbg_TDI_11, Dbg_TDO_11 => Dbg_TDO_11, Dbg_Reg_En_11 => Dbg_Reg_En_11, Dbg_Capture_11 => Dbg_Capture_11, Dbg_Shift_11 => Dbg_Shift_11, Dbg_Update_11 => Dbg_Update_11, Dbg_Rst_11 => Dbg_Rst_11, Dbg_Clk_12 => Dbg_Clk_12, Dbg_TDI_12 => Dbg_TDI_12, Dbg_TDO_12 => Dbg_TDO_12, Dbg_Reg_En_12 => Dbg_Reg_En_12, Dbg_Capture_12 => Dbg_Capture_12, Dbg_Shift_12 => Dbg_Shift_12, Dbg_Update_12 => Dbg_Update_12, Dbg_Rst_12 => Dbg_Rst_12, Dbg_Clk_13 => Dbg_Clk_13, Dbg_TDI_13 => Dbg_TDI_13, Dbg_TDO_13 => Dbg_TDO_13, Dbg_Reg_En_13 => Dbg_Reg_En_13, Dbg_Capture_13 => Dbg_Capture_13, Dbg_Shift_13 => Dbg_Shift_13, Dbg_Update_13 => Dbg_Update_13, Dbg_Rst_13 => Dbg_Rst_13, Dbg_Clk_14 => Dbg_Clk_14, Dbg_TDI_14 => Dbg_TDI_14, Dbg_TDO_14 => Dbg_TDO_14, Dbg_Reg_En_14 => Dbg_Reg_En_14, Dbg_Capture_14 => Dbg_Capture_14, Dbg_Shift_14 => Dbg_Shift_14, Dbg_Update_14 => Dbg_Update_14, Dbg_Rst_14 => Dbg_Rst_14, Dbg_Clk_15 => Dbg_Clk_15, Dbg_TDI_15 => Dbg_TDI_15, Dbg_TDO_15 => Dbg_TDO_15, Dbg_Reg_En_15 => Dbg_Reg_En_15, Dbg_Capture_15 => Dbg_Capture_15, Dbg_Shift_15 => Dbg_Shift_15, Dbg_Update_15 => Dbg_Update_15, Dbg_Rst_15 => Dbg_Rst_15, Dbg_Clk_16 => Dbg_Clk_16, Dbg_TDI_16 => Dbg_TDI_16, Dbg_TDO_16 => Dbg_TDO_16, Dbg_Reg_En_16 => Dbg_Reg_En_16, Dbg_Capture_16 => Dbg_Capture_16, Dbg_Shift_16 => Dbg_Shift_16, Dbg_Update_16 => Dbg_Update_16, Dbg_Rst_16 => Dbg_Rst_16, Dbg_Clk_17 => Dbg_Clk_17, Dbg_TDI_17 => Dbg_TDI_17, Dbg_TDO_17 => Dbg_TDO_17, Dbg_Reg_En_17 => Dbg_Reg_En_17, Dbg_Capture_17 => Dbg_Capture_17, Dbg_Shift_17 => Dbg_Shift_17, Dbg_Update_17 => Dbg_Update_17, Dbg_Rst_17 => Dbg_Rst_17, Dbg_Clk_18 => Dbg_Clk_18, Dbg_TDI_18 => Dbg_TDI_18, Dbg_TDO_18 => Dbg_TDO_18, Dbg_Reg_En_18 => Dbg_Reg_En_18, Dbg_Capture_18 => Dbg_Capture_18, Dbg_Shift_18 => Dbg_Shift_18, Dbg_Update_18 => Dbg_Update_18, Dbg_Rst_18 => Dbg_Rst_18, Dbg_Clk_19 => Dbg_Clk_19, Dbg_TDI_19 => Dbg_TDI_19, Dbg_TDO_19 => Dbg_TDO_19, Dbg_Reg_En_19 => Dbg_Reg_En_19, Dbg_Capture_19 => Dbg_Capture_19, Dbg_Shift_19 => Dbg_Shift_19, Dbg_Update_19 => Dbg_Update_19, Dbg_Rst_19 => Dbg_Rst_19, Dbg_Clk_20 => Dbg_Clk_20, Dbg_TDI_20 => Dbg_TDI_20, Dbg_TDO_20 => Dbg_TDO_20, Dbg_Reg_En_20 => Dbg_Reg_En_20, Dbg_Capture_20 => Dbg_Capture_20, Dbg_Shift_20 => Dbg_Shift_20, Dbg_Update_20 => Dbg_Update_20, Dbg_Rst_20 => Dbg_Rst_20, Dbg_Clk_21 => Dbg_Clk_21, Dbg_TDI_21 => Dbg_TDI_21, Dbg_TDO_21 => Dbg_TDO_21, Dbg_Reg_En_21 => Dbg_Reg_En_21, Dbg_Capture_21 => Dbg_Capture_21, Dbg_Shift_21 => Dbg_Shift_21, Dbg_Update_21 => Dbg_Update_21, Dbg_Rst_21 => Dbg_Rst_21, Dbg_Clk_22 => Dbg_Clk_22, Dbg_TDI_22 => Dbg_TDI_22, Dbg_TDO_22 => Dbg_TDO_22, Dbg_Reg_En_22 => Dbg_Reg_En_22, Dbg_Capture_22 => Dbg_Capture_22, Dbg_Shift_22 => Dbg_Shift_22, Dbg_Update_22 => Dbg_Update_22, Dbg_Rst_22 => Dbg_Rst_22, Dbg_Clk_23 => Dbg_Clk_23, Dbg_TDI_23 => Dbg_TDI_23, Dbg_TDO_23 => Dbg_TDO_23, Dbg_Reg_En_23 => Dbg_Reg_En_23, Dbg_Capture_23 => Dbg_Capture_23, Dbg_Shift_23 => Dbg_Shift_23, Dbg_Update_23 => Dbg_Update_23, Dbg_Rst_23 => Dbg_Rst_23, Dbg_Clk_24 => Dbg_Clk_24, Dbg_TDI_24 => Dbg_TDI_24, Dbg_TDO_24 => Dbg_TDO_24, Dbg_Reg_En_24 => Dbg_Reg_En_24, Dbg_Capture_24 => Dbg_Capture_24, Dbg_Shift_24 => Dbg_Shift_24, Dbg_Update_24 => Dbg_Update_24, Dbg_Rst_24 => Dbg_Rst_24, Dbg_Clk_25 => Dbg_Clk_25, Dbg_TDI_25 => Dbg_TDI_25, Dbg_TDO_25 => Dbg_TDO_25, Dbg_Reg_En_25 => Dbg_Reg_En_25, Dbg_Capture_25 => Dbg_Capture_25, Dbg_Shift_25 => Dbg_Shift_25, Dbg_Update_25 => Dbg_Update_25, Dbg_Rst_25 => Dbg_Rst_25, Dbg_Clk_26 => Dbg_Clk_26, Dbg_TDI_26 => Dbg_TDI_26, Dbg_TDO_26 => Dbg_TDO_26, Dbg_Reg_En_26 => Dbg_Reg_En_26, Dbg_Capture_26 => Dbg_Capture_26, Dbg_Shift_26 => Dbg_Shift_26, Dbg_Update_26 => Dbg_Update_26, Dbg_Rst_26 => Dbg_Rst_26, Dbg_Clk_27 => Dbg_Clk_27, Dbg_TDI_27 => Dbg_TDI_27, Dbg_TDO_27 => Dbg_TDO_27, Dbg_Reg_En_27 => Dbg_Reg_En_27, Dbg_Capture_27 => Dbg_Capture_27, Dbg_Shift_27 => Dbg_Shift_27, Dbg_Update_27 => Dbg_Update_27, Dbg_Rst_27 => Dbg_Rst_27, Dbg_Clk_28 => Dbg_Clk_28, Dbg_TDI_28 => Dbg_TDI_28, Dbg_TDO_28 => Dbg_TDO_28, Dbg_Reg_En_28 => Dbg_Reg_En_28, Dbg_Capture_28 => Dbg_Capture_28, Dbg_Shift_28 => Dbg_Shift_28, Dbg_Update_28 => Dbg_Update_28, Dbg_Rst_28 => Dbg_Rst_28, Dbg_Clk_29 => Dbg_Clk_29, Dbg_TDI_29 => Dbg_TDI_29, Dbg_TDO_29 => Dbg_TDO_29, Dbg_Reg_En_29 => Dbg_Reg_En_29, Dbg_Capture_29 => Dbg_Capture_29, Dbg_Shift_29 => Dbg_Shift_29, Dbg_Update_29 => Dbg_Update_29, Dbg_Rst_29 => Dbg_Rst_29, Dbg_Clk_30 => Dbg_Clk_30, Dbg_TDI_30 => Dbg_TDI_30, Dbg_TDO_30 => Dbg_TDO_30, Dbg_Reg_En_30 => Dbg_Reg_En_30, Dbg_Capture_30 => Dbg_Capture_30, Dbg_Shift_30 => Dbg_Shift_30, Dbg_Update_30 => Dbg_Update_30, Dbg_Rst_30 => Dbg_Rst_30, Dbg_Clk_31 => Dbg_Clk_31, Dbg_TDI_31 => Dbg_TDI_31, Dbg_TDO_31 => Dbg_TDO_31, Dbg_Reg_En_31 => Dbg_Reg_En_31, Dbg_Capture_31 => Dbg_Capture_31, Dbg_Shift_31 => Dbg_Shift_31, Dbg_Update_31 => Dbg_Update_31, Dbg_Rst_31 => Dbg_Rst_31, bscan_tdi => bscan_tdi, bscan_reset => bscan_reset, bscan_shift => bscan_shift, bscan_update => bscan_update, bscan_capture => bscan_capture, bscan_sel1 => bscan_sel1, bscan_drck1 => bscan_drck1, bscan_tdo1 => bscan_tdo1, bscan_ext_tdi => bscan_ext_tdi, bscan_ext_reset => bscan_ext_reset, bscan_ext_shift => bscan_ext_shift, bscan_ext_update => bscan_ext_update, bscan_ext_capture => bscan_ext_capture, bscan_ext_sel => bscan_ext_sel, bscan_ext_drck => bscan_ext_drck, bscan_ext_tdo => bscan_ext_tdo, Ext_JTAG_DRCK => Ext_JTAG_DRCK, Ext_JTAG_RESET => Ext_JTAG_RESET, Ext_JTAG_SEL => Ext_JTAG_SEL, Ext_JTAG_CAPTURE => Ext_JTAG_CAPTURE, Ext_JTAG_SHIFT => Ext_JTAG_SHIFT, Ext_JTAG_UPDATE => Ext_JTAG_UPDATE, Ext_JTAG_TDI => Ext_JTAG_TDI, Ext_JTAG_TDO => Ext_JTAG_TDO ); end architecture STRUCTURE;
lgpl-3.0
0a87f17f16a24a4e3518ba6bd6d09846
0.575864
2.800272
false
false
false
false
grwlf/vsim
vhdl_ct/ct00067.vhd
1
3,275
-- NEED RESULT: ARCH00067.P1_1: Exit with a label and no condition only effects labeled loop passed -- NEED RESULT: ARCH00067.P1_1: Exit with a label and no condition only effects labeled loop passed -- NEED RESULT: ARCH00067.P1_1: Exit statement does not effect outer loop passed -- NEED RESULT: ARCH00067.P1_2: Exit with a label and condition only effects labeled loop passed ------------------------------------------------------------------------------- -- -- Copyright (c) 1989 by Intermetrics, Inc. -- All rights reserved. -- ------------------------------------------------------------------------------- -- -- TEST NAME: -- -- CT00067 -- -- AUTHOR: -- -- G. Tominovich -- -- TEST OBJECTIVES: -- -- 8.10 (2) -- 8.10 (3) -- 8.10 (4) -- -- DESIGN UNIT ORDERING: -- -- E00000(ARCH00067) -- ENT00067_Test_Bench(ARCH00067_Test_Bench) -- -- REVISION HISTORY: -- -- 06-JUL-1987 - initial revision -- -- NOTES: -- -- self-checking -- automatically generated -- use WORK.STANDARD_TYPES.all ; architecture ARCH00067 of E00000 is signal Dummy : Boolean := false ; begin P1_1 : process ( Dummy ) variable correct : boolean ; variable counter : integer := 0 ; begin L1 : for i in boolean loop -- correct := true ; L2 : for j in 1 to 3 loop correct := (j = 1) and correct ; exit L2 ; correct := false ; end loop L2 ; -- test_report ( "ARCH00067.P1_1" , "Exit with a label and no condition only effects " & "labeled loop", correct ) ; -- counter := counter + 1 ; -- end loop L1 ; correct := counter = (boolean'Pos (boolean'High) - boolean'Pos (boolean'Low) + 1) ; test_report ( "ARCH00067.P1_1" , "Exit statement does not effect outer " & "loop", correct ) ; -- end process P1_1 ; -- P1_2 : process ( Dummy ) variable correct : boolean := true ; variable done : boolean := false ; variable counter : integer := 0 ; variable v_boolean : boolean := c_boolean_1 ; -- begin L1 : while v_boolean /= c_boolean_2 loop -- correct := (not done) and correct ; done := true ; v_boolean := c_boolean_2 ; for j in 1 to 3 loop correct := (j = 1) and correct ; exit L1 when j = j ; end loop ; -- counter := counter + 1 ; -- end loop L1 ; -- correct := (counter = 0) and correct ; test_report ( "ARCH00067.P1_2" , "Exit with a label and condition only effects " & "labeled loop", correct ) ; -- end process P1_2 ; -- -- end ARCH00067 ; -- entity ENT00067_Test_Bench is end ENT00067_Test_Bench ; -- architecture ARCH00067_Test_Bench of ENT00067_Test_Bench is begin L1: block component UUT end component ; for CIS1 : UUT use entity WORK.E00000 ( ARCH00067 ) ; begin CIS1 : UUT ; end block L1 ; end ARCH00067_Test_Bench ;
gpl-3.0
7461f57f87eacc2630db5353e1ffa19e
0.500763
3.704751
false
true
false
false
jairov4/accel-oil
solution_spartan6/syn/vhdl/nfa_accept_samples_generic_hw_add_32ns_32ns_32_8.vhd
6
15,868
-- ============================================================== -- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC -- Version: 2013.4 -- Copyright (C) 2013 Xilinx Inc. All rights reserved. -- -- ============================================================== library IEEE; use IEEE.std_logic_1164.all; use ieee.std_logic_arith.all; entity nfa_accept_samples_generic_hw_add_32ns_32ns_32_8_AddSubnS_0 is port ( clk: in std_logic; reset: in std_logic; ce: in std_logic; a: in std_logic_vector(31 downto 0); b: in std_logic_vector(31 downto 0); s: out std_logic_vector(31 downto 0)); end entity; architecture behav of nfa_accept_samples_generic_hw_add_32ns_32ns_32_8_AddSubnS_0 is component nfa_accept_samples_generic_hw_add_32ns_32ns_32_8_AddSubnS_0_fadder is port ( faa : IN STD_LOGIC_VECTOR (4-1 downto 0); fab : IN STD_LOGIC_VECTOR (4-1 downto 0); facin : IN STD_LOGIC_VECTOR (0 downto 0); fas : OUT STD_LOGIC_VECTOR (4-1 downto 0); facout : OUT STD_LOGIC_VECTOR (0 downto 0)); end component; component nfa_accept_samples_generic_hw_add_32ns_32ns_32_8_AddSubnS_0_fadder_f is port ( faa : IN STD_LOGIC_VECTOR (4-1 downto 0); fab : IN STD_LOGIC_VECTOR (4-1 downto 0); facin : IN STD_LOGIC_VECTOR (0 downto 0); fas : OUT STD_LOGIC_VECTOR (4-1 downto 0); facout : OUT STD_LOGIC_VECTOR (0 downto 0)); end component; -- ---- register and wire type variables list here ---- -- wire for the primary inputs signal a_reg : std_logic_vector(31 downto 0); signal b_reg : std_logic_vector(31 downto 0); -- wires for each small adder signal a0_cb : std_logic_vector(3 downto 0); signal b0_cb : std_logic_vector(3 downto 0); signal a1_cb : std_logic_vector(7 downto 4); signal b1_cb : std_logic_vector(7 downto 4); signal a2_cb : std_logic_vector(11 downto 8); signal b2_cb : std_logic_vector(11 downto 8); signal a3_cb : std_logic_vector(15 downto 12); signal b3_cb : std_logic_vector(15 downto 12); signal a4_cb : std_logic_vector(19 downto 16); signal b4_cb : std_logic_vector(19 downto 16); signal a5_cb : std_logic_vector(23 downto 20); signal b5_cb : std_logic_vector(23 downto 20); signal a6_cb : std_logic_vector(27 downto 24); signal b6_cb : std_logic_vector(27 downto 24); signal a7_cb : std_logic_vector(31 downto 28); signal b7_cb : std_logic_vector(31 downto 28); -- registers for input register array type ramtypei0 is array (0 downto 0) of std_logic_vector(3 downto 0); signal a1_cb_regi1 : ramtypei0; signal b1_cb_regi1 : ramtypei0; type ramtypei1 is array (1 downto 0) of std_logic_vector(3 downto 0); signal a2_cb_regi2 : ramtypei1; signal b2_cb_regi2 : ramtypei1; type ramtypei2 is array (2 downto 0) of std_logic_vector(3 downto 0); signal a3_cb_regi3 : ramtypei2; signal b3_cb_regi3 : ramtypei2; type ramtypei3 is array (3 downto 0) of std_logic_vector(3 downto 0); signal a4_cb_regi4 : ramtypei3; signal b4_cb_regi4 : ramtypei3; type ramtypei4 is array (4 downto 0) of std_logic_vector(3 downto 0); signal a5_cb_regi5 : ramtypei4; signal b5_cb_regi5 : ramtypei4; type ramtypei5 is array (5 downto 0) of std_logic_vector(3 downto 0); signal a6_cb_regi6 : ramtypei5; signal b6_cb_regi6 : ramtypei5; type ramtypei6 is array (6 downto 0) of std_logic_vector(3 downto 0); signal a7_cb_regi7 : ramtypei6; signal b7_cb_regi7 : ramtypei6; -- wires for each full adder sum signal fas : std_logic_vector(31 downto 0); -- wires and register for carry out bit signal faccout_ini : std_logic_vector (0 downto 0); signal faccout0_co0 : std_logic_vector (0 downto 0); signal faccout1_co1 : std_logic_vector (0 downto 0); signal faccout2_co2 : std_logic_vector (0 downto 0); signal faccout3_co3 : std_logic_vector (0 downto 0); signal faccout4_co4 : std_logic_vector (0 downto 0); signal faccout5_co5 : std_logic_vector (0 downto 0); signal faccout6_co6 : std_logic_vector (0 downto 0); signal faccout7_co7 : std_logic_vector (0 downto 0); signal faccout0_co0_reg : std_logic_vector (0 downto 0); signal faccout1_co1_reg : std_logic_vector (0 downto 0); signal faccout2_co2_reg : std_logic_vector (0 downto 0); signal faccout3_co3_reg : std_logic_vector (0 downto 0); signal faccout4_co4_reg : std_logic_vector (0 downto 0); signal faccout5_co5_reg : std_logic_vector (0 downto 0); signal faccout6_co6_reg : std_logic_vector (0 downto 0); -- registers for output register array type ramtypeo6 is array (6 downto 0) of std_logic_vector(3 downto 0); signal s0_ca_rego0 : ramtypeo6; type ramtypeo5 is array (5 downto 0) of std_logic_vector(3 downto 0); signal s1_ca_rego1 : ramtypeo5; type ramtypeo4 is array (4 downto 0) of std_logic_vector(3 downto 0); signal s2_ca_rego2 : ramtypeo4; type ramtypeo3 is array (3 downto 0) of std_logic_vector(3 downto 0); signal s3_ca_rego3 : ramtypeo3; type ramtypeo2 is array (2 downto 0) of std_logic_vector(3 downto 0); signal s4_ca_rego4 : ramtypeo2; type ramtypeo1 is array (1 downto 0) of std_logic_vector(3 downto 0); signal s5_ca_rego5 : ramtypeo1; type ramtypeo0 is array (0 downto 0) of std_logic_vector(3 downto 0); signal s6_ca_rego6 : ramtypeo0; -- wire for the temporary output signal s_tmp : std_logic_vector(31 downto 0); -- ---- RTL code for assignment statements/always blocks/module instantiations here ---- begin a_reg <= a; b_reg <= b; -- small adder input assigments a0_cb <= a_reg(3 downto 0); b0_cb <= b_reg(3 downto 0); a1_cb <= a_reg(7 downto 4); b1_cb <= b_reg(7 downto 4); a2_cb <= a_reg(11 downto 8); b2_cb <= b_reg(11 downto 8); a3_cb <= a_reg(15 downto 12); b3_cb <= b_reg(15 downto 12); a4_cb <= a_reg(19 downto 16); b4_cb <= b_reg(19 downto 16); a5_cb <= a_reg(23 downto 20); b5_cb <= b_reg(23 downto 20); a6_cb <= a_reg(27 downto 24); b6_cb <= b_reg(27 downto 24); a7_cb <= a_reg(31 downto 28); b7_cb <= b_reg(31 downto 28); -- input register array process (clk) begin if (clk'event and clk='1') then if (ce='1') then a1_cb_regi1 (0) <= a1_cb; b1_cb_regi1 (0) <= b1_cb; a2_cb_regi2 (0) <= a2_cb; b2_cb_regi2 (0) <= b2_cb; a3_cb_regi3 (0) <= a3_cb; b3_cb_regi3 (0) <= b3_cb; a4_cb_regi4 (0) <= a4_cb; b4_cb_regi4 (0) <= b4_cb; a5_cb_regi5 (0) <= a5_cb; b5_cb_regi5 (0) <= b5_cb; a6_cb_regi6 (0) <= a6_cb; b6_cb_regi6 (0) <= b6_cb; a7_cb_regi7 (0) <= a7_cb; b7_cb_regi7 (0) <= b7_cb; a2_cb_regi2 (1) <= a2_cb_regi2 (0); b2_cb_regi2 (1) <= b2_cb_regi2 (0); a3_cb_regi3 (1) <= a3_cb_regi3 (0); b3_cb_regi3 (1) <= b3_cb_regi3 (0); a4_cb_regi4 (1) <= a4_cb_regi4 (0); b4_cb_regi4 (1) <= b4_cb_regi4 (0); a5_cb_regi5 (1) <= a5_cb_regi5 (0); b5_cb_regi5 (1) <= b5_cb_regi5 (0); a6_cb_regi6 (1) <= a6_cb_regi6 (0); b6_cb_regi6 (1) <= b6_cb_regi6 (0); a7_cb_regi7 (1) <= a7_cb_regi7 (0); b7_cb_regi7 (1) <= b7_cb_regi7 (0); a3_cb_regi3 (2) <= a3_cb_regi3 (1); b3_cb_regi3 (2) <= b3_cb_regi3 (1); a4_cb_regi4 (2) <= a4_cb_regi4 (1); b4_cb_regi4 (2) <= b4_cb_regi4 (1); a5_cb_regi5 (2) <= a5_cb_regi5 (1); b5_cb_regi5 (2) <= b5_cb_regi5 (1); a6_cb_regi6 (2) <= a6_cb_regi6 (1); b6_cb_regi6 (2) <= b6_cb_regi6 (1); a7_cb_regi7 (2) <= a7_cb_regi7 (1); b7_cb_regi7 (2) <= b7_cb_regi7 (1); a4_cb_regi4 (3) <= a4_cb_regi4 (2); b4_cb_regi4 (3) <= b4_cb_regi4 (2); a5_cb_regi5 (3) <= a5_cb_regi5 (2); b5_cb_regi5 (3) <= b5_cb_regi5 (2); a6_cb_regi6 (3) <= a6_cb_regi6 (2); b6_cb_regi6 (3) <= b6_cb_regi6 (2); a7_cb_regi7 (3) <= a7_cb_regi7 (2); b7_cb_regi7 (3) <= b7_cb_regi7 (2); a5_cb_regi5 (4) <= a5_cb_regi5 (3); b5_cb_regi5 (4) <= b5_cb_regi5 (3); a6_cb_regi6 (4) <= a6_cb_regi6 (3); b6_cb_regi6 (4) <= b6_cb_regi6 (3); a7_cb_regi7 (4) <= a7_cb_regi7 (3); b7_cb_regi7 (4) <= b7_cb_regi7 (3); a6_cb_regi6 (5) <= a6_cb_regi6 (4); b6_cb_regi6 (5) <= b6_cb_regi6 (4); a7_cb_regi7 (5) <= a7_cb_regi7 (4); b7_cb_regi7 (5) <= b7_cb_regi7 (4); a7_cb_regi7 (6) <= a7_cb_regi7 (5); b7_cb_regi7 (6) <= b7_cb_regi7 (5); end if; end if; end process; -- carry out bit processing process (clk) begin if (clk'event and clk='1') then if (ce='1') then faccout0_co0_reg <= faccout0_co0; faccout1_co1_reg <= faccout1_co1; faccout2_co2_reg <= faccout2_co2; faccout3_co3_reg <= faccout3_co3; faccout4_co4_reg <= faccout4_co4; faccout5_co5_reg <= faccout5_co5; faccout6_co6_reg <= faccout6_co6; end if; end if; end process; -- small adder generation u0 : nfa_accept_samples_generic_hw_add_32ns_32ns_32_8_AddSubnS_0_fadder port map (faa => a0_cb, fab => b0_cb, facin => faccout_ini, fas => fas(3 downto 0), facout => faccout0_co0); u1 : nfa_accept_samples_generic_hw_add_32ns_32ns_32_8_AddSubnS_0_fadder port map (faa => a1_cb_regi1(0), fab => b1_cb_regi1(0), facin => faccout0_co0_reg, fas => fas(7 downto 4), facout => faccout1_co1); u2 : nfa_accept_samples_generic_hw_add_32ns_32ns_32_8_AddSubnS_0_fadder port map (faa => a2_cb_regi2(1), fab => b2_cb_regi2(1), facin => faccout1_co1_reg, fas => fas(11 downto 8), facout => faccout2_co2); u3 : nfa_accept_samples_generic_hw_add_32ns_32ns_32_8_AddSubnS_0_fadder port map (faa => a3_cb_regi3(2), fab => b3_cb_regi3(2), facin => faccout2_co2_reg, fas => fas(15 downto 12), facout => faccout3_co3); u4 : nfa_accept_samples_generic_hw_add_32ns_32ns_32_8_AddSubnS_0_fadder port map (faa => a4_cb_regi4(3), fab => b4_cb_regi4(3), facin => faccout3_co3_reg, fas => fas(19 downto 16), facout => faccout4_co4); u5 : nfa_accept_samples_generic_hw_add_32ns_32ns_32_8_AddSubnS_0_fadder port map (faa => a5_cb_regi5(4), fab => b5_cb_regi5(4), facin => faccout4_co4_reg, fas => fas(23 downto 20), facout => faccout5_co5); u6 : nfa_accept_samples_generic_hw_add_32ns_32ns_32_8_AddSubnS_0_fadder port map (faa => a6_cb_regi6(5), fab => b6_cb_regi6(5), facin => faccout5_co5_reg, fas => fas(27 downto 24), facout => faccout6_co6); u7 : nfa_accept_samples_generic_hw_add_32ns_32ns_32_8_AddSubnS_0_fadder_f port map (faa => a7_cb_regi7(6), fab => b7_cb_regi7(6), facin => faccout6_co6_reg, fas => fas(31 downto 28), facout => faccout7_co7); faccout_ini <= "0"; -- output register array process (clk) begin if (clk'event and clk='1') then if (ce='1') then s0_ca_rego0 (0) <= fas(3 downto 0); s1_ca_rego1 (0) <= fas(7 downto 4); s2_ca_rego2 (0) <= fas(11 downto 8); s3_ca_rego3 (0) <= fas(15 downto 12); s4_ca_rego4 (0) <= fas(19 downto 16); s5_ca_rego5 (0) <= fas(23 downto 20); s6_ca_rego6 (0) <= fas(27 downto 24); s0_ca_rego0 (1) <= s0_ca_rego0 (0); s0_ca_rego0 (2) <= s0_ca_rego0 (1); s0_ca_rego0 (3) <= s0_ca_rego0 (2); s0_ca_rego0 (4) <= s0_ca_rego0 (3); s0_ca_rego0 (5) <= s0_ca_rego0 (4); s0_ca_rego0 (6) <= s0_ca_rego0 (5); s1_ca_rego1 (1) <= s1_ca_rego1 (0); s1_ca_rego1 (2) <= s1_ca_rego1 (1); s1_ca_rego1 (3) <= s1_ca_rego1 (2); s1_ca_rego1 (4) <= s1_ca_rego1 (3); s1_ca_rego1 (5) <= s1_ca_rego1 (4); s2_ca_rego2 (1) <= s2_ca_rego2 (0); s2_ca_rego2 (2) <= s2_ca_rego2 (1); s2_ca_rego2 (3) <= s2_ca_rego2 (2); s2_ca_rego2 (4) <= s2_ca_rego2 (3); s3_ca_rego3 (1) <= s3_ca_rego3 (0); s3_ca_rego3 (2) <= s3_ca_rego3 (1); s3_ca_rego3 (3) <= s3_ca_rego3 (2); s4_ca_rego4 (1) <= s4_ca_rego4 (0); s4_ca_rego4 (2) <= s4_ca_rego4 (1); s5_ca_rego5 (1) <= s5_ca_rego5 (0); end if; end if; end process; -- get the s_tmp, assign it to the primary output s_tmp(3 downto 0) <= s0_ca_rego0(6); s_tmp(7 downto 4) <= s1_ca_rego1(5); s_tmp(11 downto 8) <= s2_ca_rego2(4); s_tmp(15 downto 12) <= s3_ca_rego3(3); s_tmp(19 downto 16) <= s4_ca_rego4(2); s_tmp(23 downto 20) <= s5_ca_rego5(1); s_tmp(27 downto 24) <= s6_ca_rego6(0); s_tmp(31 downto 28) <= fas(31 downto 28); s <= s_tmp; end architecture; -- short adder library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; entity nfa_accept_samples_generic_hw_add_32ns_32ns_32_8_AddSubnS_0_fadder is generic(N : natural :=4); port ( faa : IN STD_LOGIC_VECTOR (N-1 downto 0); fab : IN STD_LOGIC_VECTOR (N-1 downto 0); facin : IN STD_LOGIC_VECTOR (0 downto 0); fas : OUT STD_LOGIC_VECTOR (N-1 downto 0); facout : OUT STD_LOGIC_VECTOR (0 downto 0)); end; architecture behav of nfa_accept_samples_generic_hw_add_32ns_32ns_32_8_AddSubnS_0_fadder is signal tmp : STD_LOGIC_VECTOR (N downto 0); begin tmp <= std_logic_vector(unsigned(std_logic_vector(unsigned(std_logic_vector(resize(unsigned(faa),N+1))) + unsigned(fab))) + unsigned(facin)); fas <= tmp(N-1 downto 0 ); facout <= tmp(N downto N); end behav; -- the final stage short adder library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; entity nfa_accept_samples_generic_hw_add_32ns_32ns_32_8_AddSubnS_0_fadder_f is generic(N : natural :=4); port ( faa : IN STD_LOGIC_VECTOR (N-1 downto 0); fab : IN STD_LOGIC_VECTOR (N-1 downto 0); facin : IN STD_LOGIC_VECTOR (0 downto 0); fas : OUT STD_LOGIC_VECTOR (N-1 downto 0); facout : OUT STD_LOGIC_VECTOR (0 downto 0)); end; architecture behav of nfa_accept_samples_generic_hw_add_32ns_32ns_32_8_AddSubnS_0_fadder_f is signal tmp : STD_LOGIC_VECTOR (N downto 0); begin tmp <= std_logic_vector(unsigned(std_logic_vector(unsigned(std_logic_vector(resize(unsigned(faa),N+1))) + unsigned(fab))) + unsigned(facin)); fas <= tmp(N-1 downto 0 ); facout <= tmp(N downto N); end behav; Library IEEE; use IEEE.std_logic_1164.all; entity nfa_accept_samples_generic_hw_add_32ns_32ns_32_8 is generic ( ID : INTEGER; NUM_STAGE : INTEGER; din0_WIDTH : INTEGER; din1_WIDTH : INTEGER; dout_WIDTH : INTEGER); port ( clk : IN STD_LOGIC; reset : IN STD_LOGIC; ce : IN STD_LOGIC; din0 : IN STD_LOGIC_VECTOR(din0_WIDTH - 1 DOWNTO 0); din1 : IN STD_LOGIC_VECTOR(din1_WIDTH - 1 DOWNTO 0); dout : OUT STD_LOGIC_VECTOR(dout_WIDTH - 1 DOWNTO 0)); end entity; architecture arch of nfa_accept_samples_generic_hw_add_32ns_32ns_32_8 is component nfa_accept_samples_generic_hw_add_32ns_32ns_32_8_AddSubnS_0 is port ( clk : IN STD_LOGIC; reset : IN STD_LOGIC; ce : IN STD_LOGIC; a : IN STD_LOGIC_VECTOR; b : IN STD_LOGIC_VECTOR; s : OUT STD_LOGIC_VECTOR); end component; begin nfa_accept_samples_generic_hw_add_32ns_32ns_32_8_AddSubnS_0_U : component nfa_accept_samples_generic_hw_add_32ns_32ns_32_8_AddSubnS_0 port map ( clk => clk, reset => reset, ce => ce, a => din0, b => din1, s => dout); end architecture;
lgpl-3.0
b3d7559c90513f32b1a5c10f5b73eb66
0.584699
2.633693
false
false
false
false
grwlf/vsim
vhdl_ct/pro000022.vhd
1
14,306
-- Prosoft VHDL tests. -- -- Copyright (C) 2011 Prosoft. -- -- Author: Zefirov, Karavaev. -- -- This is a set of simplest tests for isolated tests of VHDL features. -- -- Nothing more than standard package should be required. -- -- Categories: entity, architecture, process, type, case, enumerations, scalar-type-attributes. entity ENT00022_Test_Bench is end ENT00022_Test_Bench; architecture ARCH00022_Test_Bench of ENT00022_Test_Bench is type IntArray is array (natural range <>) of integer; type enum is (a_v, b_v, c_v, d_v, e_v, f_v); type BooleanVector is array (integer range <>) of boolean; type StateType is (init, assign, analize, waiting); signal state : StateType := init; begin process (state) variable b, b_image : bit; variable n : natural; variable s2 : string(1 to 2); variable s1 : string(1 to 1); variable s3, s4, s5 : string (1 to 3); variable bva : bit_vector(1 to 4) := x"0"; variable int : IntArray(1 to 4) := (others => 0); type RealArray is array (integer range <>) of real; variable ra : RealArray(1 to 4) := (others => 0.0); variable bool : BooleanVector(1 to 9) := (others => false); variable bv2 : bit_vector(7 downto 0) := x"AC"; type EnumArray is array (integer range <>) of enum; variable ea : EnumArray(1 to 4) := (others => a_v); variable e1 : enum := c_v; variable e2 : enum := a_v; begin case state is when init => s1 := "1"; s2 := "10"; s4 := "d_v"; e1 := c_v; b_image := '1'; state <= assign; when assign => b := bit'Value(s1); n := natural'Value(s2); s3 := bit'image(b_image); s5 := enum'image(e1); e2 := enum'Value(s4); -- bit bva(1) := bit'low; bva(2) := bit'high; bva(3) := bit'left; bva(4) := bit'right; bool(5) := bit'ascending; -- boolean bool(1) := boolean'low; bool(2) := boolean'high; bool(3) := boolean'left; bool(4) := boolean'right; bool(6) := boolean'ascending; -- integer int(1) := integer'low; int(2) := integer'high; int(3) := integer'left; int(4) := integer'right; bool(7) := integer'ascending; -- real ra(1) := real'low; ra(2) := real'high; ra(3) := real'left; ra(4) := real'right; bool(8) := real'ascending; -- enumeration bool(9) := enum'ascending; ea(1) := enum'low; ea(2) := enum'high; ea(3) := enum'left; ea(4) := enum'right; state <= analize; when analize => state <= waiting; -- T'Image assert s3 /= "'1'" report "Scalar type attribute T'Image worked with the type Bit correctly" severity NOTE; assert s3 = "'1'" report "Scalar type attribute T'Image does not with the type Bit" severity NOTE; assert s5 /= "c_v" report "Scalar type attribute T'Image worked with the Enumerations correctly" severity NOTE; assert s5 = "c_v" report "Scalar type attribute T'Image does not with the Enumerations" severity NOTE; -- T'Value assert b /= '1' report "Scalar type attribute T'Value worked with the type Bit correctly" severity NOTE; assert b = '1' report "Scalar type attribute T'Value does not with the type Bit" severity NOTE; assert n /= 10 report "Scalar type attribute T'Value worked with the subtype Natural correctly" severity NOTE; assert n = 10 report "Scalar type attribute T'Value does not with the subtype Natural" severity NOTE; assert e2 /= d_v report "Scalar type attribute T'Value worked with the Enumerations correctly" severity NOTE; assert e2 = d_v report "Scalar type attribute T'Value does not with the Enumerations" severity NOTE; -- boolean assert bool(1) report "Scalar type attribute T'Low worked with the type Boolean correctly" severity NOTE; assert not bool(1) report "Scalar type attribute T'Low does not work with the type Boolean" severity NOTE; assert not bool(2) report "Scalar type attribute T'High worked with the type Boolean correctly" severity NOTE; assert bool(2) report "Scalar type attribute T'High does not work with the type Boolean" severity NOTE; assert bool(3) report "Scalar type attribute T'Left worked with the type Boolean correctly" severity NOTE; assert not bool(3) report "Scalar type attribute T'Left does not work with the type Boolean" severity NOTE; assert not bool(4) report "Scalar type attribute T'Right worked with the type Boolean correctly" severity NOTE; assert bool(4) report "Scalar type attribute T'Right does not work with the type Boolean" severity NOTE; -- bit assert bva(1) = '1' report "Scalar type attribute T'Low worked with the type Bit correctly" severity NOTE; assert bva(1) = '0' report "Scalar type attribute T'Low does not work with the type Bit" severity NOTE; assert bva(2) = '0' report "Scalar type attribute T'High worked with the type Bit correctly" severity NOTE; assert bva(2) = '1' report "Scalar type attribute T'High does not work with the type Bit" severity NOTE; assert bva(3) = '1' report "Scalar type attribute T'Left worked with the type Bit correctly" severity NOTE; assert bva(3) = '0' report "Scalar type attribute T'Left does not work with the type Bit" severity NOTE; assert bva(4) = '0' report "Scalar type attribute T'Right worked with the type Bit correctly" severity NOTE; assert bva(4) = '1' report "Scalar type attribute T'Right does not work with the type Bit" severity NOTE; -- integer -- assert int(1) /= -16#80000000# assert int(1) /= -16#7FFFFFFF# - 1 report "Scalar type attribute T'Low worked with the type Integer correctly" severity NOTE; -- assert int(1) = -16#80000000# assert int(1) = -16#7FFFFFFF# - 1 report "Scalar type attribute T'Low does not work with the type Integer" severity NOTE; assert int(2) /= 16#7FFFFFFF# report "Scalar type attribute T'High worked with the type Integer correctly" severity NOTE; assert int(2) = 16#7FFFFFFF# report "Scalar type attribute T'High does not work with the type Integer" severity NOTE; -- assert int(3) /= -16#80000000# assert int(3) /= -16#7FFFFFFF# - 1 report "Scalar type attribute T'Left worked with the type Integer correctly" severity NOTE; -- assert int(3) = -16#80000000# assert int(3) = -16#7FFFFFFF# - 1 report "Scalar type attribute T'Left does not work with the type Integer" severity NOTE; assert int(4) /= 16#7FFFFFFF# report "Scalar type attribute T'Right worked with the type Integer correctly" severity NOTE; assert int(4) = 16#7FFFFFFF# report "Scalar type attribute T'Right does not work with the type Integer" severity NOTE; -- real -- assert ra(1) /= -1.0e+308 assert ra(1) /= -1.79769e+308 report "Scalar type attribute T'Low worked with the type Real correctly" severity NOTE; assert ra(1) = -1.79769e+308 report "Scalar type attribute T'Low does not work with the type Real" severity NOTE; assert ra(2) /= 1.79769e+308 report "Scalar type attribute T'High worked with the type Real correctly" severity NOTE; assert ra(2) = 1.79769e+308 report "Scalar type attribute T'High does not work with the type Real" severity NOTE; assert ra(3) /= -1.79769e+308 report "Scalar type attribute T'Left worked with the type Real correctly" severity NOTE; assert ra(3) = -1.79769e+308 report "Scalar type attribute T'Left does not work with the type Real" severity NOTE; assert ra(4) /= 1.79769e+308 report "Scalar type attribute T'Right worked with the type Real correctly" severity NOTE; assert ra(4) = 1.79769e+308 report "Scalar type attribute T'Right does not work with the type Real" severity NOTE; -- enumeration assert ea(1) /= a_v report "Scalar type attribute T'Low worked with the Enumerations correctly" severity NOTE; assert ea(1) = a_v report "Scalar type attribute T'Low does not work with the Enumerations" severity NOTE; assert ea(2) /= f_v report "Scalar type attribute T'High worked with the Enumerations correctly" severity NOTE; assert ea(2) = f_v report "Scalar type attribute T'High does not work with the Enumerations" severity NOTE; assert ea(3) /= a_v report "Scalar type attribute T'Left worked with the Enumerations correctly" severity NOTE; assert ea(3) = a_v report "Scalar type attribute T'Left does not work with the Enumerations" severity NOTE; assert ea(4) /= f_v report "Scalar type attribute T'Right worked with the Enumerations correctly" severity NOTE; assert ea(4) = f_v report "Scalar type attribute T'Right does not work with the Enumerations" severity NOTE; -- ascending -- boolean assert not bool(6) report "Scalar type attribute T'Ascending worked with the type Boolean correctly" severity NOTE; assert bool(6) report "Scalar type attribute T'Ascending does not work with the type Boolean" severity NOTE; -- bit assert not bool(5) report "Scalar type attribute T'Ascending worked with the type Bit correctly" severity NOTE; assert bool(5) report "Scalar type attribute T'Ascending does not work with the type Bit" severity NOTE; -- integer assert not bool(7) report "Scalar type attribute T'Ascending worked with the type Integer correctly" severity NOTE; assert bool(7) report "Scalar type attribute T'Ascending does not work with the type Integer" severity NOTE; -- real assert not bool(8) report "Scalar type attribute T'Ascending worked with the type Real correctly" severity NOTE; assert bool(8) report "Scalar type attribute T'Ascending does not work with the type Real" severity NOTE; -- enumeration assert not bool(9) report "Scalar type attribute T'Ascending worked with the Enumerations correctly" severity NOTE; assert bool(9) report "Scalar type attribute T'Ascending does not work with the Enumerations" severity NOTE; when waiting => null; end case; end process; end ARCH00022_Test_Bench ;
gpl-3.0
c300e535fc5d13d189de893edacc9247
0.479589
5.080256
false
false
false
false
wsoltys/AtomFpga
src/ROM/kernel.vhd
1
172,876
-- generated with romgen v3.0.1r4 by MikeJ truhy and eD library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; use ieee.numeric_std.all; library UNISIM; --use UNISIM.Vcomponents.all; entity atomkernal is port ( CLK : in std_logic; ADDR : in std_logic_vector(11 downto 0); DATA : out std_logic_vector(7 downto 0) ); end; architecture RTL of atomkernal is signal rom_addr : std_logic_vector(11 downto 0); begin p_addr : process(ADDR) begin rom_addr <= (others => '0'); rom_addr(11 downto 0) <= ADDR; end process; p_rom : process begin wait until rising_edge(CLK); DATA <= (others => '0'); case rom_addr is when x"000" => DATA <= x"50"; when x"001" => DATA <= x"4C"; when x"002" => DATA <= x"4F"; when x"003" => DATA <= x"54"; when x"004" => DATA <= x"F5"; when x"005" => DATA <= x"4E"; when x"006" => DATA <= x"44"; when x"007" => DATA <= x"52"; when x"008" => DATA <= x"41"; when x"009" => DATA <= x"57"; when x"00A" => DATA <= x"F5"; when x"00B" => DATA <= x"42"; when x"00C" => DATA <= x"4D"; when x"00D" => DATA <= x"4F"; when x"00E" => DATA <= x"56"; when x"00F" => DATA <= x"45"; when x"010" => DATA <= x"F5"; when x"011" => DATA <= x"46"; when x"012" => DATA <= x"43"; when x"013" => DATA <= x"4C"; when x"014" => DATA <= x"45"; when x"015" => DATA <= x"41"; when x"016" => DATA <= x"52"; when x"017" => DATA <= x"F6"; when x"018" => DATA <= x"7B"; when x"019" => DATA <= x"44"; when x"01A" => DATA <= x"49"; when x"01B" => DATA <= x"4D"; when x"01C" => DATA <= x"F0"; when x"01D" => DATA <= x"AE"; when x"01E" => DATA <= x"5B"; when x"01F" => DATA <= x"F2"; when x"020" => DATA <= x"A1"; when x"021" => DATA <= x"4F"; when x"022" => DATA <= x"4C"; when x"023" => DATA <= x"44"; when x"024" => DATA <= x"F5"; when x"025" => DATA <= x"31"; when x"026" => DATA <= x"57"; when x"027" => DATA <= x"41"; when x"028" => DATA <= x"49"; when x"029" => DATA <= x"54"; when x"02A" => DATA <= x"F1"; when x"02B" => DATA <= x"4C"; when x"02C" => DATA <= x"C5"; when x"02D" => DATA <= x"50"; when x"02E" => DATA <= x"A4"; when x"02F" => DATA <= x"5E"; when x"030" => DATA <= x"B1"; when x"031" => DATA <= x"05"; when x"032" => DATA <= x"C9"; when x"033" => DATA <= x"40"; when x"034" => DATA <= x"90"; when x"035" => DATA <= x"12"; when x"036" => DATA <= x"C9"; when x"037" => DATA <= x"5B"; when x"038" => DATA <= x"B0"; when x"039" => DATA <= x"0E"; when x"03A" => DATA <= x"C8"; when x"03B" => DATA <= x"D1"; when x"03C" => DATA <= x"05"; when x"03D" => DATA <= x"D0"; when x"03E" => DATA <= x"09"; when x"03F" => DATA <= x"20"; when x"040" => DATA <= x"8B"; when x"041" => DATA <= x"F0"; when x"042" => DATA <= x"20"; when x"043" => DATA <= x"4F"; when x"044" => DATA <= x"C9"; when x"045" => DATA <= x"4C"; when x"046" => DATA <= x"62"; when x"047" => DATA <= x"C9"; when x"048" => DATA <= x"4C"; when x"049" => DATA <= x"24"; when x"04A" => DATA <= x"CA"; when x"04B" => DATA <= x"A2"; when x"04C" => DATA <= x"FF"; when x"04D" => DATA <= x"A4"; when x"04E" => DATA <= x"5E"; when x"04F" => DATA <= x"C6"; when x"050" => DATA <= x"5E"; when x"051" => DATA <= x"B1"; when x"052" => DATA <= x"05"; when x"053" => DATA <= x"C9"; when x"054" => DATA <= x"40"; when x"055" => DATA <= x"90"; when x"056" => DATA <= x"09"; when x"057" => DATA <= x"C9"; when x"058" => DATA <= x"5B"; when x"059" => DATA <= x"B0"; when x"05A" => DATA <= x"05"; when x"05B" => DATA <= x"C8"; when x"05C" => DATA <= x"D1"; when x"05D" => DATA <= x"05"; when x"05E" => DATA <= x"F0"; when x"05F" => DATA <= x"25"; when x"060" => DATA <= x"A4"; when x"061" => DATA <= x"5E"; when x"062" => DATA <= x"E8"; when x"063" => DATA <= x"C8"; when x"064" => DATA <= x"BD"; when x"065" => DATA <= x"00"; when x"066" => DATA <= x"F0"; when x"067" => DATA <= x"30"; when x"068" => DATA <= x"0C"; when x"069" => DATA <= x"D1"; when x"06A" => DATA <= x"05"; when x"06B" => DATA <= x"F0"; when x"06C" => DATA <= x"F5"; when x"06D" => DATA <= x"E8"; when x"06E" => DATA <= x"BD"; when x"06F" => DATA <= x"FF"; when x"070" => DATA <= x"EF"; when x"071" => DATA <= x"10"; when x"072" => DATA <= x"FA"; when x"073" => DATA <= x"D0"; when x"074" => DATA <= x"EB"; when x"075" => DATA <= x"85"; when x"076" => DATA <= x"53"; when x"077" => DATA <= x"BD"; when x"078" => DATA <= x"01"; when x"079" => DATA <= x"F0"; when x"07A" => DATA <= x"85"; when x"07B" => DATA <= x"52"; when x"07C" => DATA <= x"84"; when x"07D" => DATA <= x"03"; when x"07E" => DATA <= x"A6"; when x"07F" => DATA <= x"04"; when x"080" => DATA <= x"E6"; when x"081" => DATA <= x"5E"; when x"082" => DATA <= x"6C"; when x"083" => DATA <= x"52"; when x"084" => DATA <= x"00"; when x"085" => DATA <= x"20"; when x"086" => DATA <= x"8B"; when x"087" => DATA <= x"F0"; when x"088" => DATA <= x"4C"; when x"089" => DATA <= x"F1"; when x"08A" => DATA <= x"C3"; when x"08B" => DATA <= x"C8"; when x"08C" => DATA <= x"84"; when x"08D" => DATA <= x"03"; when x"08E" => DATA <= x"E9"; when x"08F" => DATA <= x"40"; when x"090" => DATA <= x"48"; when x"091" => DATA <= x"20"; when x"092" => DATA <= x"BC"; when x"093" => DATA <= x"C8"; when x"094" => DATA <= x"68"; when x"095" => DATA <= x"A8"; when x"096" => DATA <= x"B5"; when x"097" => DATA <= x"15"; when x"098" => DATA <= x"0A"; when x"099" => DATA <= x"36"; when x"09A" => DATA <= x"24"; when x"09B" => DATA <= x"0A"; when x"09C" => DATA <= x"36"; when x"09D" => DATA <= x"24"; when x"09E" => DATA <= x"18"; when x"09F" => DATA <= x"79"; when x"0A0" => DATA <= x"EB"; when x"0A1" => DATA <= x"02"; when x"0A2" => DATA <= x"95"; when x"0A3" => DATA <= x"15"; when x"0A4" => DATA <= x"B5"; when x"0A5" => DATA <= x"24"; when x"0A6" => DATA <= x"79"; when x"0A7" => DATA <= x"06"; when x"0A8" => DATA <= x"03"; when x"0A9" => DATA <= x"95"; when x"0AA" => DATA <= x"24"; when x"0AB" => DATA <= x"B0"; when x"0AC" => DATA <= x"D7"; when x"0AD" => DATA <= x"60"; when x"0AE" => DATA <= x"A5"; when x"0AF" => DATA <= x"01"; when x"0B0" => DATA <= x"05"; when x"0B1" => DATA <= x"02"; when x"0B2" => DATA <= x"F0"; when x"0B3" => DATA <= x"22"; when x"0B4" => DATA <= x"20"; when x"0B5" => DATA <= x"34"; when x"0B6" => DATA <= x"C4"; when x"0B7" => DATA <= x"90"; when x"0B8" => DATA <= x"1E"; when x"0B9" => DATA <= x"20"; when x"0BA" => DATA <= x"BC"; when x"0BB" => DATA <= x"C8"; when x"0BC" => DATA <= x"CA"; when x"0BD" => DATA <= x"CA"; when x"0BE" => DATA <= x"86"; when x"0BF" => DATA <= x"04"; when x"0C0" => DATA <= x"B4"; when x"0C1" => DATA <= x"16"; when x"0C2" => DATA <= x"38"; when x"0C3" => DATA <= x"A5"; when x"0C4" => DATA <= x"23"; when x"0C5" => DATA <= x"99"; when x"0C6" => DATA <= x"21"; when x"0C7" => DATA <= x"03"; when x"0C8" => DATA <= x"75"; when x"0C9" => DATA <= x"17"; when x"0CA" => DATA <= x"85"; when x"0CB" => DATA <= x"23"; when x"0CC" => DATA <= x"A5"; when x"0CD" => DATA <= x"24"; when x"0CE" => DATA <= x"99"; when x"0CF" => DATA <= x"3C"; when x"0D0" => DATA <= x"03"; when x"0D1" => DATA <= x"75"; when x"0D2" => DATA <= x"26"; when x"0D3" => DATA <= x"4C"; when x"0D4" => DATA <= x"19"; when x"0D5" => DATA <= x"F1"; when x"0D6" => DATA <= x"00"; when x"0D7" => DATA <= x"A4"; when x"0D8" => DATA <= x"03"; when x"0D9" => DATA <= x"B1"; when x"0DA" => DATA <= x"05"; when x"0DB" => DATA <= x"C9"; when x"0DC" => DATA <= x"40"; when x"0DD" => DATA <= x"90"; when x"0DE" => DATA <= x"F7"; when x"0DF" => DATA <= x"C9"; when x"0E0" => DATA <= x"5B"; when x"0E1" => DATA <= x"B0"; when x"0E2" => DATA <= x"F3"; when x"0E3" => DATA <= x"C8"; when x"0E4" => DATA <= x"D1"; when x"0E5" => DATA <= x"05"; when x"0E6" => DATA <= x"D0"; when x"0E7" => DATA <= x"EE"; when x"0E8" => DATA <= x"E9"; when x"0E9" => DATA <= x"40"; when x"0EA" => DATA <= x"48"; when x"0EB" => DATA <= x"C8"; when x"0EC" => DATA <= x"84"; when x"0ED" => DATA <= x"03"; when x"0EE" => DATA <= x"20"; when x"0EF" => DATA <= x"BC"; when x"0F0" => DATA <= x"C8"; when x"0F1" => DATA <= x"68"; when x"0F2" => DATA <= x"A8"; when x"0F3" => DATA <= x"A5"; when x"0F4" => DATA <= x"23"; when x"0F5" => DATA <= x"99"; when x"0F6" => DATA <= x"EB"; when x"0F7" => DATA <= x"02"; when x"0F8" => DATA <= x"A5"; when x"0F9" => DATA <= x"24"; when x"0FA" => DATA <= x"99"; when x"0FB" => DATA <= x"06"; when x"0FC" => DATA <= x"03"; when x"0FD" => DATA <= x"CA"; when x"0FE" => DATA <= x"86"; when x"0FF" => DATA <= x"04"; when x"100" => DATA <= x"B4"; when x"101" => DATA <= x"16"; when x"102" => DATA <= x"C8"; when x"103" => DATA <= x"D0"; when x"104" => DATA <= x"02"; when x"105" => DATA <= x"F6"; when x"106" => DATA <= x"25"; when x"107" => DATA <= x"98"; when x"108" => DATA <= x"0A"; when x"109" => DATA <= x"36"; when x"10A" => DATA <= x"25"; when x"10B" => DATA <= x"0A"; when x"10C" => DATA <= x"36"; when x"10D" => DATA <= x"25"; when x"10E" => DATA <= x"18"; when x"10F" => DATA <= x"65"; when x"110" => DATA <= x"23"; when x"111" => DATA <= x"85"; when x"112" => DATA <= x"23"; when x"113" => DATA <= x"B5"; when x"114" => DATA <= x"25"; when x"115" => DATA <= x"65"; when x"116" => DATA <= x"24"; when x"117" => DATA <= x"B0"; when x"118" => DATA <= x"BD"; when x"119" => DATA <= x"85"; when x"11A" => DATA <= x"24"; when x"11B" => DATA <= x"A0"; when x"11C" => DATA <= x"00"; when x"11D" => DATA <= x"A9"; when x"11E" => DATA <= x"AA"; when x"11F" => DATA <= x"91"; when x"120" => DATA <= x"23"; when x"121" => DATA <= x"D1"; when x"122" => DATA <= x"23"; when x"123" => DATA <= x"D0"; when x"124" => DATA <= x"F7"; when x"125" => DATA <= x"4A"; when x"126" => DATA <= x"91"; when x"127" => DATA <= x"23"; when x"128" => DATA <= x"D1"; when x"129" => DATA <= x"23"; when x"12A" => DATA <= x"D0"; when x"12B" => DATA <= x"F0"; when x"12C" => DATA <= x"20"; when x"12D" => DATA <= x"34"; when x"12E" => DATA <= x"C4"; when x"12F" => DATA <= x"B0"; when x"130" => DATA <= x"A5"; when x"131" => DATA <= x"A4"; when x"132" => DATA <= x"03"; when x"133" => DATA <= x"B1"; when x"134" => DATA <= x"05"; when x"135" => DATA <= x"C9"; when x"136" => DATA <= x"2C"; when x"137" => DATA <= x"D0"; when x"138" => DATA <= x"05"; when x"139" => DATA <= x"E6"; when x"13A" => DATA <= x"03"; when x"13B" => DATA <= x"4C"; when x"13C" => DATA <= x"AE"; when x"13D" => DATA <= x"F0"; when x"13E" => DATA <= x"4C"; when x"13F" => DATA <= x"58"; when x"140" => DATA <= x"C5"; when x"141" => DATA <= x"A5"; when x"142" => DATA <= x"0D"; when x"143" => DATA <= x"85"; when x"144" => DATA <= x"23"; when x"145" => DATA <= x"A5"; when x"146" => DATA <= x"0E"; when x"147" => DATA <= x"85"; when x"148" => DATA <= x"24"; when x"149" => DATA <= x"4C"; when x"14A" => DATA <= x"83"; when x"14B" => DATA <= x"CE"; when x"14C" => DATA <= x"20"; when x"14D" => DATA <= x"E4"; when x"14E" => DATA <= x"C4"; when x"14F" => DATA <= x"20"; when x"150" => DATA <= x"66"; when x"151" => DATA <= x"FE"; when x"152" => DATA <= x"4C"; when x"153" => DATA <= x"5B"; when x"154" => DATA <= x"C5"; when x"155" => DATA <= x"1C"; when x"156" => DATA <= x"8A"; when x"157" => DATA <= x"1C"; when x"158" => DATA <= x"23"; when x"159" => DATA <= x"5D"; when x"15A" => DATA <= x"8B"; when x"15B" => DATA <= x"1B"; when x"15C" => DATA <= x"A1"; when x"15D" => DATA <= x"9D"; when x"15E" => DATA <= x"8A"; when x"15F" => DATA <= x"1D"; when x"160" => DATA <= x"23"; when x"161" => DATA <= x"9D"; when x"162" => DATA <= x"8B"; when x"163" => DATA <= x"1D"; when x"164" => DATA <= x"A1"; when x"165" => DATA <= x"00"; when x"166" => DATA <= x"29"; when x"167" => DATA <= x"19"; when x"168" => DATA <= x"AE"; when x"169" => DATA <= x"69"; when x"16A" => DATA <= x"A8"; when x"16B" => DATA <= x"19"; when x"16C" => DATA <= x"23"; when x"16D" => DATA <= x"24"; when x"16E" => DATA <= x"53"; when x"16F" => DATA <= x"1B"; when x"170" => DATA <= x"23"; when x"171" => DATA <= x"24"; when x"172" => DATA <= x"53"; when x"173" => DATA <= x"19"; when x"174" => DATA <= x"A1"; when x"175" => DATA <= x"00"; when x"176" => DATA <= x"1A"; when x"177" => DATA <= x"5B"; when x"178" => DATA <= x"5B"; when x"179" => DATA <= x"A5"; when x"17A" => DATA <= x"69"; when x"17B" => DATA <= x"24"; when x"17C" => DATA <= x"24"; when x"17D" => DATA <= x"AE"; when x"17E" => DATA <= x"AE"; when x"17F" => DATA <= x"A8"; when x"180" => DATA <= x"AD"; when x"181" => DATA <= x"29"; when x"182" => DATA <= x"00"; when x"183" => DATA <= x"7C"; when x"184" => DATA <= x"00"; when x"185" => DATA <= x"15"; when x"186" => DATA <= x"9C"; when x"187" => DATA <= x"6D"; when x"188" => DATA <= x"9C"; when x"189" => DATA <= x"A5"; when x"18A" => DATA <= x"69"; when x"18B" => DATA <= x"29"; when x"18C" => DATA <= x"53"; when x"18D" => DATA <= x"84"; when x"18E" => DATA <= x"13"; when x"18F" => DATA <= x"34"; when x"190" => DATA <= x"11"; when x"191" => DATA <= x"A5"; when x"192" => DATA <= x"69"; when x"193" => DATA <= x"23"; when x"194" => DATA <= x"A0"; when x"195" => DATA <= x"D8"; when x"196" => DATA <= x"62"; when x"197" => DATA <= x"5A"; when x"198" => DATA <= x"48"; when x"199" => DATA <= x"26"; when x"19A" => DATA <= x"62"; when x"19B" => DATA <= x"94"; when x"19C" => DATA <= x"88"; when x"19D" => DATA <= x"54"; when x"19E" => DATA <= x"44"; when x"19F" => DATA <= x"C8"; when x"1A0" => DATA <= x"54"; when x"1A1" => DATA <= x"68"; when x"1A2" => DATA <= x"44"; when x"1A3" => DATA <= x"E8"; when x"1A4" => DATA <= x"94"; when x"1A5" => DATA <= x"00"; when x"1A6" => DATA <= x"B4"; when x"1A7" => DATA <= x"08"; when x"1A8" => DATA <= x"84"; when x"1A9" => DATA <= x"74"; when x"1AA" => DATA <= x"B4"; when x"1AB" => DATA <= x"28"; when x"1AC" => DATA <= x"6E"; when x"1AD" => DATA <= x"74"; when x"1AE" => DATA <= x"F4"; when x"1AF" => DATA <= x"CC"; when x"1B0" => DATA <= x"4A"; when x"1B1" => DATA <= x"72"; when x"1B2" => DATA <= x"F2"; when x"1B3" => DATA <= x"A4"; when x"1B4" => DATA <= x"8A"; when x"1B5" => DATA <= x"00"; when x"1B6" => DATA <= x"AA"; when x"1B7" => DATA <= x"A2"; when x"1B8" => DATA <= x"A2"; when x"1B9" => DATA <= x"74"; when x"1BA" => DATA <= x"74"; when x"1BB" => DATA <= x"74"; when x"1BC" => DATA <= x"72"; when x"1BD" => DATA <= x"44"; when x"1BE" => DATA <= x"68"; when x"1BF" => DATA <= x"B2"; when x"1C0" => DATA <= x"32"; when x"1C1" => DATA <= x"B2"; when x"1C2" => DATA <= x"00"; when x"1C3" => DATA <= x"22"; when x"1C4" => DATA <= x"00"; when x"1C5" => DATA <= x"1A"; when x"1C6" => DATA <= x"1A"; when x"1C7" => DATA <= x"26"; when x"1C8" => DATA <= x"26"; when x"1C9" => DATA <= x"72"; when x"1CA" => DATA <= x"72"; when x"1CB" => DATA <= x"88"; when x"1CC" => DATA <= x"C8"; when x"1CD" => DATA <= x"C4"; when x"1CE" => DATA <= x"CA"; when x"1CF" => DATA <= x"26"; when x"1D0" => DATA <= x"48"; when x"1D1" => DATA <= x"44"; when x"1D2" => DATA <= x"44"; when x"1D3" => DATA <= x"A2"; when x"1D4" => DATA <= x"C8"; when x"1D5" => DATA <= x"00"; when x"1D6" => DATA <= x"02"; when x"1D7" => DATA <= x"00"; when x"1D8" => DATA <= x"08"; when x"1D9" => DATA <= x"F2"; when x"1DA" => DATA <= x"FF"; when x"1DB" => DATA <= x"80"; when x"1DC" => DATA <= x"01"; when x"1DD" => DATA <= x"C0"; when x"1DE" => DATA <= x"E2"; when x"1DF" => DATA <= x"C0"; when x"1E0" => DATA <= x"C0"; when x"1E1" => DATA <= x"FF"; when x"1E2" => DATA <= x"00"; when x"1E3" => DATA <= x"00"; when x"1E4" => DATA <= x"08"; when x"1E5" => DATA <= x"00"; when x"1E6" => DATA <= x"10"; when x"1E7" => DATA <= x"80"; when x"1E8" => DATA <= x"40"; when x"1E9" => DATA <= x"C0"; when x"1EA" => DATA <= x"00"; when x"1EB" => DATA <= x"C0"; when x"1EC" => DATA <= x"00"; when x"1ED" => DATA <= x"40"; when x"1EE" => DATA <= x"00"; when x"1EF" => DATA <= x"00"; when x"1F0" => DATA <= x"E4"; when x"1F1" => DATA <= x"20"; when x"1F2" => DATA <= x"80"; when x"1F3" => DATA <= x"00"; when x"1F4" => DATA <= x"FC"; when x"1F5" => DATA <= x"00"; when x"1F6" => DATA <= x"08"; when x"1F7" => DATA <= x"08"; when x"1F8" => DATA <= x"F8"; when x"1F9" => DATA <= x"FC"; when x"1FA" => DATA <= x"F4"; when x"1FB" => DATA <= x"0C"; when x"1FC" => DATA <= x"10"; when x"1FD" => DATA <= x"04"; when x"1FE" => DATA <= x"F4"; when x"1FF" => DATA <= x"00"; when x"200" => DATA <= x"20"; when x"201" => DATA <= x"10"; when x"202" => DATA <= x"00"; when x"203" => DATA <= x"00"; when x"204" => DATA <= x"0F"; when x"205" => DATA <= x"01"; when x"206" => DATA <= x"01"; when x"207" => DATA <= x"01"; when x"208" => DATA <= x"11"; when x"209" => DATA <= x"11"; when x"20A" => DATA <= x"02"; when x"20B" => DATA <= x"02"; when x"20C" => DATA <= x"11"; when x"20D" => DATA <= x"11"; when x"20E" => DATA <= x"02"; when x"20F" => DATA <= x"12"; when x"210" => DATA <= x"02"; when x"211" => DATA <= x"00"; when x"212" => DATA <= x"08"; when x"213" => DATA <= x"10"; when x"214" => DATA <= x"18"; when x"215" => DATA <= x"20"; when x"216" => DATA <= x"28"; when x"217" => DATA <= x"30"; when x"218" => DATA <= x"38"; when x"219" => DATA <= x"40"; when x"21A" => DATA <= x"48"; when x"21B" => DATA <= x"50"; when x"21C" => DATA <= x"58"; when x"21D" => DATA <= x"60"; when x"21E" => DATA <= x"68"; when x"21F" => DATA <= x"70"; when x"220" => DATA <= x"78"; when x"221" => DATA <= x"80"; when x"222" => DATA <= x"88"; when x"223" => DATA <= x"90"; when x"224" => DATA <= x"98"; when x"225" => DATA <= x"A0"; when x"226" => DATA <= x"A8"; when x"227" => DATA <= x"B0"; when x"228" => DATA <= x"B8"; when x"229" => DATA <= x"C0"; when x"22A" => DATA <= x"C8"; when x"22B" => DATA <= x"D0"; when x"22C" => DATA <= x"D8"; when x"22D" => DATA <= x"E0"; when x"22E" => DATA <= x"E8"; when x"22F" => DATA <= x"F0"; when x"230" => DATA <= x"F8"; when x"231" => DATA <= x"0C"; when x"232" => DATA <= x"2C"; when x"233" => DATA <= x"4C"; when x"234" => DATA <= x"4C"; when x"235" => DATA <= x"8C"; when x"236" => DATA <= x"AC"; when x"237" => DATA <= x"CC"; when x"238" => DATA <= x"EC"; when x"239" => DATA <= x"8A"; when x"23A" => DATA <= x"9A"; when x"23B" => DATA <= x"AA"; when x"23C" => DATA <= x"BA"; when x"23D" => DATA <= x"CA"; when x"23E" => DATA <= x"DA"; when x"23F" => DATA <= x"EA"; when x"240" => DATA <= x"FA"; when x"241" => DATA <= x"0E"; when x"242" => DATA <= x"2E"; when x"243" => DATA <= x"4E"; when x"244" => DATA <= x"6E"; when x"245" => DATA <= x"8E"; when x"246" => DATA <= x"AE"; when x"247" => DATA <= x"CE"; when x"248" => DATA <= x"EE"; when x"249" => DATA <= x"0D"; when x"24A" => DATA <= x"2D"; when x"24B" => DATA <= x"4D"; when x"24C" => DATA <= x"6D"; when x"24D" => DATA <= x"8D"; when x"24E" => DATA <= x"AD"; when x"24F" => DATA <= x"CD"; when x"250" => DATA <= x"ED"; when x"251" => DATA <= x"0D"; when x"252" => DATA <= x"0D"; when x"253" => DATA <= x"0C"; when x"254" => DATA <= x"0D"; when x"255" => DATA <= x"0E"; when x"256" => DATA <= x"0D"; when x"257" => DATA <= x"0C"; when x"258" => DATA <= x"0D"; when x"259" => DATA <= x"0D"; when x"25A" => DATA <= x"0D"; when x"25B" => DATA <= x"0C"; when x"25C" => DATA <= x"0D"; when x"25D" => DATA <= x"0D"; when x"25E" => DATA <= x"0D"; when x"25F" => DATA <= x"0C"; when x"260" => DATA <= x"0D"; when x"261" => DATA <= x"0F"; when x"262" => DATA <= x"0D"; when x"263" => DATA <= x"0C"; when x"264" => DATA <= x"0D"; when x"265" => DATA <= x"09"; when x"266" => DATA <= x"0D"; when x"267" => DATA <= x"0C"; when x"268" => DATA <= x"0D"; when x"269" => DATA <= x"08"; when x"26A" => DATA <= x"0D"; when x"26B" => DATA <= x"0C"; when x"26C" => DATA <= x"0D"; when x"26D" => DATA <= x"08"; when x"26E" => DATA <= x"0D"; when x"26F" => DATA <= x"0C"; when x"270" => DATA <= x"0D"; when x"271" => DATA <= x"0F"; when x"272" => DATA <= x"06"; when x"273" => DATA <= x"0B"; when x"274" => DATA <= x"0B"; when x"275" => DATA <= x"04"; when x"276" => DATA <= x"0A"; when x"277" => DATA <= x"08"; when x"278" => DATA <= x"08"; when x"279" => DATA <= x"0D"; when x"27A" => DATA <= x"0D"; when x"27B" => DATA <= x"0D"; when x"27C" => DATA <= x"0D"; when x"27D" => DATA <= x"0D"; when x"27E" => DATA <= x"0F"; when x"27F" => DATA <= x"0D"; when x"280" => DATA <= x"0F"; when x"281" => DATA <= x"07"; when x"282" => DATA <= x"07"; when x"283" => DATA <= x"07"; when x"284" => DATA <= x"07"; when x"285" => DATA <= x"05"; when x"286" => DATA <= x"09"; when x"287" => DATA <= x"03"; when x"288" => DATA <= x"03"; when x"289" => DATA <= x"01"; when x"28A" => DATA <= x"01"; when x"28B" => DATA <= x"01"; when x"28C" => DATA <= x"01"; when x"28D" => DATA <= x"02"; when x"28E" => DATA <= x"01"; when x"28F" => DATA <= x"01"; when x"290" => DATA <= x"01"; when x"291" => DATA <= x"A4"; when x"292" => DATA <= x"03"; when x"293" => DATA <= x"B1"; when x"294" => DATA <= x"05"; when x"295" => DATA <= x"E6"; when x"296" => DATA <= x"03"; when x"297" => DATA <= x"C9"; when x"298" => DATA <= x"20"; when x"299" => DATA <= x"F0"; when x"29A" => DATA <= x"F6"; when x"29B" => DATA <= x"60"; when x"29C" => DATA <= x"E6"; when x"29D" => DATA <= x"03"; when x"29E" => DATA <= x"4C"; when x"29F" => DATA <= x"1B"; when x"2A0" => DATA <= x"C3"; when x"2A1" => DATA <= x"B1"; when x"2A2" => DATA <= x"05"; when x"2A3" => DATA <= x"C9"; when x"2A4" => DATA <= x"5D"; when x"2A5" => DATA <= x"F0"; when x"2A6" => DATA <= x"F5"; when x"2A7" => DATA <= x"20"; when x"2A8" => DATA <= x"F6"; when x"2A9" => DATA <= x"C4"; when x"2AA" => DATA <= x"C6"; when x"2AB" => DATA <= x"03"; when x"2AC" => DATA <= x"20"; when x"2AD" => DATA <= x"8E"; when x"2AE" => DATA <= x"F3"; when x"2AF" => DATA <= x"C6"; when x"2B0" => DATA <= x"03"; when x"2B1" => DATA <= x"A5"; when x"2B2" => DATA <= x"52"; when x"2B3" => DATA <= x"48"; when x"2B4" => DATA <= x"A5"; when x"2B5" => DATA <= x"53"; when x"2B6" => DATA <= x"48"; when x"2B7" => DATA <= x"AD"; when x"2B8" => DATA <= x"21"; when x"2B9" => DATA <= x"03"; when x"2BA" => DATA <= x"48"; when x"2BB" => DATA <= x"A9"; when x"2BC" => DATA <= x"00"; when x"2BD" => DATA <= x"85"; when x"2BE" => DATA <= x"34"; when x"2BF" => DATA <= x"85"; when x"2C0" => DATA <= x"43"; when x"2C1" => DATA <= x"A9"; when x"2C2" => DATA <= x"05"; when x"2C3" => DATA <= x"8D"; when x"2C4" => DATA <= x"21"; when x"2C5" => DATA <= x"03"; when x"2C6" => DATA <= x"A5"; when x"2C7" => DATA <= x"01"; when x"2C8" => DATA <= x"85"; when x"2C9" => DATA <= x"16"; when x"2CA" => DATA <= x"A5"; when x"2CB" => DATA <= x"02"; when x"2CC" => DATA <= x"85"; when x"2CD" => DATA <= x"25"; when x"2CE" => DATA <= x"20"; when x"2CF" => DATA <= x"89"; when x"2D0" => DATA <= x"C5"; when x"2D1" => DATA <= x"20"; when x"2D2" => DATA <= x"79"; when x"2D3" => DATA <= x"F3"; when x"2D4" => DATA <= x"68"; when x"2D5" => DATA <= x"8D"; when x"2D6" => DATA <= x"21"; when x"2D7" => DATA <= x"03"; when x"2D8" => DATA <= x"68"; when x"2D9" => DATA <= x"20"; when x"2DA" => DATA <= x"7E"; when x"2DB" => DATA <= x"F3"; when x"2DC" => DATA <= x"68"; when x"2DD" => DATA <= x"20"; when x"2DE" => DATA <= x"76"; when x"2DF" => DATA <= x"F3"; when x"2E0" => DATA <= x"A0"; when x"2E1" => DATA <= x"00"; when x"2E2" => DATA <= x"C4"; when x"2E3" => DATA <= x"00"; when x"2E4" => DATA <= x"F0"; when x"2E5" => DATA <= x"09"; when x"2E6" => DATA <= x"B9"; when x"2E7" => DATA <= x"66"; when x"2E8" => DATA <= x"00"; when x"2E9" => DATA <= x"20"; when x"2EA" => DATA <= x"76"; when x"2EB" => DATA <= x"F3"; when x"2EC" => DATA <= x"C8"; when x"2ED" => DATA <= x"D0"; when x"2EE" => DATA <= x"F3"; when x"2EF" => DATA <= x"C0"; when x"2F0" => DATA <= x"03"; when x"2F1" => DATA <= x"F0"; when x"2F2" => DATA <= x"0C"; when x"2F3" => DATA <= x"20"; when x"2F4" => DATA <= x"79"; when x"2F5" => DATA <= x"F3"; when x"2F6" => DATA <= x"20"; when x"2F7" => DATA <= x"4C"; when x"2F8" => DATA <= x"CA"; when x"2F9" => DATA <= x"20"; when x"2FA" => DATA <= x"4C"; when x"2FB" => DATA <= x"CA"; when x"2FC" => DATA <= x"C8"; when x"2FD" => DATA <= x"D0"; when x"2FE" => DATA <= x"F0"; when x"2FF" => DATA <= x"A0"; when x"300" => DATA <= x"00"; when x"301" => DATA <= x"B1"; when x"302" => DATA <= x"05"; when x"303" => DATA <= x"C9"; when x"304" => DATA <= x"3B"; when x"305" => DATA <= x"F0"; when x"306" => DATA <= x"0A"; when x"307" => DATA <= x"C9"; when x"308" => DATA <= x"0D"; when x"309" => DATA <= x"F0"; when x"30A" => DATA <= x"06"; when x"30B" => DATA <= x"20"; when x"30C" => DATA <= x"4C"; when x"30D" => DATA <= x"CA"; when x"30E" => DATA <= x"C8"; when x"30F" => DATA <= x"D0"; when x"310" => DATA <= x"F0"; when x"311" => DATA <= x"20"; when x"312" => DATA <= x"54"; when x"313" => DATA <= x"CD"; when x"314" => DATA <= x"20"; when x"315" => DATA <= x"E4"; when x"316" => DATA <= x"C4"; when x"317" => DATA <= x"88"; when x"318" => DATA <= x"B1"; when x"319" => DATA <= x"05"; when x"31A" => DATA <= x"C8"; when x"31B" => DATA <= x"C9"; when x"31C" => DATA <= x"3B"; when x"31D" => DATA <= x"F0"; when x"31E" => DATA <= x"0C"; when x"31F" => DATA <= x"A5"; when x"320" => DATA <= x"06"; when x"321" => DATA <= x"C9"; when x"322" => DATA <= x"01"; when x"323" => DATA <= x"D0"; when x"324" => DATA <= x"03"; when x"325" => DATA <= x"4C"; when x"326" => DATA <= x"CF"; when x"327" => DATA <= x"C2"; when x"328" => DATA <= x"20"; when x"329" => DATA <= x"1D"; when x"32A" => DATA <= x"C5"; when x"32B" => DATA <= x"4C"; when x"32C" => DATA <= x"A1"; when x"32D" => DATA <= x"F2"; when x"32E" => DATA <= x"20"; when x"32F" => DATA <= x"91"; when x"330" => DATA <= x"F2"; when x"331" => DATA <= x"85"; when x"332" => DATA <= x"66"; when x"333" => DATA <= x"20"; when x"334" => DATA <= x"91"; when x"335" => DATA <= x"F2"; when x"336" => DATA <= x"C5"; when x"337" => DATA <= x"66"; when x"338" => DATA <= x"D0"; when x"339" => DATA <= x"10"; when x"33A" => DATA <= x"C9"; when x"33B" => DATA <= x"40"; when x"33C" => DATA <= x"90"; when x"33D" => DATA <= x"0C"; when x"33E" => DATA <= x"C9"; when x"33F" => DATA <= x"5B"; when x"340" => DATA <= x"B0"; when x"341" => DATA <= x"08"; when x"342" => DATA <= x"38"; when x"343" => DATA <= x"20"; when x"344" => DATA <= x"8E"; when x"345" => DATA <= x"F0"; when x"346" => DATA <= x"20"; when x"347" => DATA <= x"CB"; when x"348" => DATA <= x"C3"; when x"349" => DATA <= x"A0"; when x"34A" => DATA <= x"00"; when x"34B" => DATA <= x"AD"; when x"34C" => DATA <= x"31"; when x"34D" => DATA <= x"03"; when x"34E" => DATA <= x"91"; when x"34F" => DATA <= x"52"; when x"350" => DATA <= x"AD"; when x"351" => DATA <= x"4C"; when x"352" => DATA <= x"03"; when x"353" => DATA <= x"C8"; when x"354" => DATA <= x"91"; when x"355" => DATA <= x"52"; when x"356" => DATA <= x"A9"; when x"357" => DATA <= x"00"; when x"358" => DATA <= x"C8"; when x"359" => DATA <= x"91"; when x"35A" => DATA <= x"52"; when x"35B" => DATA <= x"C8"; when x"35C" => DATA <= x"91"; when x"35D" => DATA <= x"52"; when x"35E" => DATA <= x"D0"; when x"35F" => DATA <= x"36"; when x"360" => DATA <= x"20"; when x"361" => DATA <= x"91"; when x"362" => DATA <= x"F2"; when x"363" => DATA <= x"C9"; when x"364" => DATA <= x"3B"; when x"365" => DATA <= x"F0"; when x"366" => DATA <= x"04"; when x"367" => DATA <= x"C9"; when x"368" => DATA <= x"0D"; when x"369" => DATA <= x"D0"; when x"36A" => DATA <= x"F5"; when x"36B" => DATA <= x"AD"; when x"36C" => DATA <= x"31"; when x"36D" => DATA <= x"03"; when x"36E" => DATA <= x"85"; when x"36F" => DATA <= x"52"; when x"370" => DATA <= x"AD"; when x"371" => DATA <= x"4C"; when x"372" => DATA <= x"03"; when x"373" => DATA <= x"85"; when x"374" => DATA <= x"53"; when x"375" => DATA <= x"60"; when x"376" => DATA <= x"20"; when x"377" => DATA <= x"7E"; when x"378" => DATA <= x"F3"; when x"379" => DATA <= x"A9"; when x"37A" => DATA <= x"20"; when x"37B" => DATA <= x"4C"; when x"37C" => DATA <= x"4C"; when x"37D" => DATA <= x"CA"; when x"37E" => DATA <= x"A2"; when x"37F" => DATA <= x"FF"; when x"380" => DATA <= x"48"; when x"381" => DATA <= x"4A"; when x"382" => DATA <= x"4A"; when x"383" => DATA <= x"4A"; when x"384" => DATA <= x"4A"; when x"385" => DATA <= x"20"; when x"386" => DATA <= x"F9"; when x"387" => DATA <= x"C5"; when x"388" => DATA <= x"68"; when x"389" => DATA <= x"29"; when x"38A" => DATA <= x"0F"; when x"38B" => DATA <= x"4C"; when x"38C" => DATA <= x"F9"; when x"38D" => DATA <= x"C5"; when x"38E" => DATA <= x"A2"; when x"38F" => DATA <= x"00"; when x"390" => DATA <= x"86"; when x"391" => DATA <= x"00"; when x"392" => DATA <= x"86"; when x"393" => DATA <= x"64"; when x"394" => DATA <= x"86"; when x"395" => DATA <= x"65"; when x"396" => DATA <= x"20"; when x"397" => DATA <= x"91"; when x"398" => DATA <= x"F2"; when x"399" => DATA <= x"C9"; when x"39A" => DATA <= x"3A"; when x"39B" => DATA <= x"F0"; when x"39C" => DATA <= x"91"; when x"39D" => DATA <= x"C9"; when x"39E" => DATA <= x"3B"; when x"39F" => DATA <= x"F0"; when x"3A0" => DATA <= x"CA"; when x"3A1" => DATA <= x"C9"; when x"3A2" => DATA <= x"0D"; when x"3A3" => DATA <= x"F0"; when x"3A4" => DATA <= x"C6"; when x"3A5" => DATA <= x"C9"; when x"3A6" => DATA <= x"5C"; when x"3A7" => DATA <= x"F0"; when x"3A8" => DATA <= x"B7"; when x"3A9" => DATA <= x"A0"; when x"3AA" => DATA <= x"05"; when x"3AB" => DATA <= x"38"; when x"3AC" => DATA <= x"69"; when x"3AD" => DATA <= x"00"; when x"3AE" => DATA <= x"0A"; when x"3AF" => DATA <= x"0A"; when x"3B0" => DATA <= x"0A"; when x"3B1" => DATA <= x"0A"; when x"3B2" => DATA <= x"26"; when x"3B3" => DATA <= x"6A"; when x"3B4" => DATA <= x"26"; when x"3B5" => DATA <= x"69"; when x"3B6" => DATA <= x"88"; when x"3B7" => DATA <= x"D0"; when x"3B8" => DATA <= x"F8"; when x"3B9" => DATA <= x"E8"; when x"3BA" => DATA <= x"E0"; when x"3BB" => DATA <= x"03"; when x"3BC" => DATA <= x"D0"; when x"3BD" => DATA <= x"D8"; when x"3BE" => DATA <= x"06"; when x"3BF" => DATA <= x"6A"; when x"3C0" => DATA <= x"26"; when x"3C1" => DATA <= x"69"; when x"3C2" => DATA <= x"A2"; when x"3C3" => DATA <= x"40"; when x"3C4" => DATA <= x"A5"; when x"3C5" => DATA <= x"69"; when x"3C6" => DATA <= x"DD"; when x"3C7" => DATA <= x"54"; when x"3C8" => DATA <= x"F1"; when x"3C9" => DATA <= x"F0"; when x"3CA" => DATA <= x"04"; when x"3CB" => DATA <= x"CA"; when x"3CC" => DATA <= x"D0"; when x"3CD" => DATA <= x"F8"; when x"3CE" => DATA <= x"00"; when x"3CF" => DATA <= x"BC"; when x"3D0" => DATA <= x"94"; when x"3D1" => DATA <= x"F1"; when x"3D2" => DATA <= x"C4"; when x"3D3" => DATA <= x"6A"; when x"3D4" => DATA <= x"D0"; when x"3D5" => DATA <= x"F5"; when x"3D6" => DATA <= x"BD"; when x"3D7" => DATA <= x"10"; when x"3D8" => DATA <= x"F2"; when x"3D9" => DATA <= x"85"; when x"3DA" => DATA <= x"66"; when x"3DB" => DATA <= x"BC"; when x"3DC" => DATA <= x"50"; when x"3DD" => DATA <= x"F2"; when x"3DE" => DATA <= x"84"; when x"3DF" => DATA <= x"0F"; when x"3E0" => DATA <= x"66"; when x"3E1" => DATA <= x"64"; when x"3E2" => DATA <= x"66"; when x"3E3" => DATA <= x"65"; when x"3E4" => DATA <= x"88"; when x"3E5" => DATA <= x"D0"; when x"3E6" => DATA <= x"F9"; when x"3E7" => DATA <= x"A4"; when x"3E8" => DATA <= x"0F"; when x"3E9" => DATA <= x"C0"; when x"3EA" => DATA <= x"0D"; when x"3EB" => DATA <= x"D0"; when x"3EC" => DATA <= x"05"; when x"3ED" => DATA <= x"A2"; when x"3EE" => DATA <= x"00"; when x"3EF" => DATA <= x"4C"; when x"3F0" => DATA <= x"9B"; when x"3F1" => DATA <= x"F4"; when x"3F2" => DATA <= x"20"; when x"3F3" => DATA <= x"91"; when x"3F4" => DATA <= x"F2"; when x"3F5" => DATA <= x"C9"; when x"3F6" => DATA <= x"40"; when x"3F7" => DATA <= x"F0"; when x"3F8" => DATA <= x"5B"; when x"3F9" => DATA <= x"C9"; when x"3FA" => DATA <= x"28"; when x"3FB" => DATA <= x"F0"; when x"3FC" => DATA <= x"65"; when x"3FD" => DATA <= x"A2"; when x"3FE" => DATA <= x"01"; when x"3FF" => DATA <= x"C9"; when x"400" => DATA <= x"41"; when x"401" => DATA <= x"F0"; when x"402" => DATA <= x"EC"; when x"403" => DATA <= x"C6"; when x"404" => DATA <= x"03"; when x"405" => DATA <= x"20"; when x"406" => DATA <= x"8B"; when x"407" => DATA <= x"C7"; when x"408" => DATA <= x"20"; when x"409" => DATA <= x"91"; when x"40A" => DATA <= x"F2"; when x"40B" => DATA <= x"C9"; when x"40C" => DATA <= x"2C"; when x"40D" => DATA <= x"D0"; when x"40E" => DATA <= x"31"; when x"40F" => DATA <= x"20"; when x"410" => DATA <= x"91"; when x"411" => DATA <= x"F2"; when x"412" => DATA <= x"A4"; when x"413" => DATA <= x"25"; when x"414" => DATA <= x"F0"; when x"415" => DATA <= x"15"; when x"416" => DATA <= x"A2"; when x"417" => DATA <= x"09"; when x"418" => DATA <= x"C9"; when x"419" => DATA <= x"58"; when x"41A" => DATA <= x"F0"; when x"41B" => DATA <= x"7F"; when x"41C" => DATA <= x"CA"; when x"41D" => DATA <= x"C9"; when x"41E" => DATA <= x"59"; when x"41F" => DATA <= x"D0"; when x"420" => DATA <= x"79"; when x"421" => DATA <= x"A5"; when x"422" => DATA <= x"0F"; when x"423" => DATA <= x"C9"; when x"424" => DATA <= x"09"; when x"425" => DATA <= x"D0"; when x"426" => DATA <= x"74"; when x"427" => DATA <= x"A2"; when x"428" => DATA <= x"0E"; when x"429" => DATA <= x"D0"; when x"42A" => DATA <= x"70"; when x"42B" => DATA <= x"A2"; when x"42C" => DATA <= x"04"; when x"42D" => DATA <= x"C9"; when x"42E" => DATA <= x"58"; when x"42F" => DATA <= x"F0"; when x"430" => DATA <= x"6A"; when x"431" => DATA <= x"C9"; when x"432" => DATA <= x"59"; when x"433" => DATA <= x"D0"; when x"434" => DATA <= x"65"; when x"435" => DATA <= x"CA"; when x"436" => DATA <= x"A4"; when x"437" => DATA <= x"0F"; when x"438" => DATA <= x"C0"; when x"439" => DATA <= x"03"; when x"43A" => DATA <= x"B0"; when x"43B" => DATA <= x"5F"; when x"43C" => DATA <= x"A2"; when x"43D" => DATA <= x"08"; when x"43E" => DATA <= x"D0"; when x"43F" => DATA <= x"5B"; when x"440" => DATA <= x"C6"; when x"441" => DATA <= x"03"; when x"442" => DATA <= x"A2"; when x"443" => DATA <= x"02"; when x"444" => DATA <= x"A4"; when x"445" => DATA <= x"0F"; when x"446" => DATA <= x"C0"; when x"447" => DATA <= x"0C"; when x"448" => DATA <= x"F0"; when x"449" => DATA <= x"51"; when x"44A" => DATA <= x"A2"; when x"44B" => DATA <= x"05"; when x"44C" => DATA <= x"A5"; when x"44D" => DATA <= x"25"; when x"44E" => DATA <= x"F0"; when x"44F" => DATA <= x"4B"; when x"450" => DATA <= x"A2"; when x"451" => DATA <= x"0C"; when x"452" => DATA <= x"D0"; when x"453" => DATA <= x"47"; when x"454" => DATA <= x"20"; when x"455" => DATA <= x"8B"; when x"456" => DATA <= x"C7"; when x"457" => DATA <= x"A5"; when x"458" => DATA <= x"0F"; when x"459" => DATA <= x"A2"; when x"45A" => DATA <= x"06"; when x"45B" => DATA <= x"C9"; when x"45C" => DATA <= x"01"; when x"45D" => DATA <= x"F0"; when x"45E" => DATA <= x"3C"; when x"45F" => DATA <= x"E8"; when x"460" => DATA <= x"D0"; when x"461" => DATA <= x"39"; when x"462" => DATA <= x"20"; when x"463" => DATA <= x"8B"; when x"464" => DATA <= x"C7"; when x"465" => DATA <= x"20"; when x"466" => DATA <= x"91"; when x"467" => DATA <= x"F2"; when x"468" => DATA <= x"C9"; when x"469" => DATA <= x"29"; when x"46A" => DATA <= x"F0"; when x"46B" => DATA <= x"16"; when x"46C" => DATA <= x"C9"; when x"46D" => DATA <= x"2C"; when x"46E" => DATA <= x"D0"; when x"46F" => DATA <= x"2A"; when x"470" => DATA <= x"20"; when x"471" => DATA <= x"91"; when x"472" => DATA <= x"F2"; when x"473" => DATA <= x"C9"; when x"474" => DATA <= x"58"; when x"475" => DATA <= x"D0"; when x"476" => DATA <= x"23"; when x"477" => DATA <= x"20"; when x"478" => DATA <= x"91"; when x"479" => DATA <= x"F2"; when x"47A" => DATA <= x"C9"; when x"47B" => DATA <= x"29"; when x"47C" => DATA <= x"D0"; when x"47D" => DATA <= x"1C"; when x"47E" => DATA <= x"A2"; when x"47F" => DATA <= x"0B"; when x"480" => DATA <= x"D0"; when x"481" => DATA <= x"19"; when x"482" => DATA <= x"A2"; when x"483" => DATA <= x"0D"; when x"484" => DATA <= x"A5"; when x"485" => DATA <= x"0F"; when x"486" => DATA <= x"C9"; when x"487" => DATA <= x"0B"; when x"488" => DATA <= x"F0"; when x"489" => DATA <= x"11"; when x"48A" => DATA <= x"A2"; when x"48B" => DATA <= x"0A"; when x"48C" => DATA <= x"20"; when x"48D" => DATA <= x"91"; when x"48E" => DATA <= x"F2"; when x"48F" => DATA <= x"C9"; when x"490" => DATA <= x"2C"; when x"491" => DATA <= x"D0"; when x"492" => DATA <= x"07"; when x"493" => DATA <= x"20"; when x"494" => DATA <= x"91"; when x"495" => DATA <= x"F2"; when x"496" => DATA <= x"C9"; when x"497" => DATA <= x"59"; when x"498" => DATA <= x"F0"; when x"499" => DATA <= x"01"; when x"49A" => DATA <= x"00"; when x"49B" => DATA <= x"20"; when x"49C" => DATA <= x"60"; when x"49D" => DATA <= x"F3"; when x"49E" => DATA <= x"BD"; when x"49F" => DATA <= x"D5"; when x"4A0" => DATA <= x"F1"; when x"4A1" => DATA <= x"F0"; when x"4A2" => DATA <= x"04"; when x"4A3" => DATA <= x"25"; when x"4A4" => DATA <= x"64"; when x"4A5" => DATA <= x"D0"; when x"4A6" => DATA <= x"07"; when x"4A7" => DATA <= x"BD"; when x"4A8" => DATA <= x"E4"; when x"4A9" => DATA <= x"F1"; when x"4AA" => DATA <= x"25"; when x"4AB" => DATA <= x"65"; when x"4AC" => DATA <= x"F0"; when x"4AD" => DATA <= x"EC"; when x"4AE" => DATA <= x"18"; when x"4AF" => DATA <= x"BD"; when x"4B0" => DATA <= x"F3"; when x"4B1" => DATA <= x"F1"; when x"4B2" => DATA <= x"65"; when x"4B3" => DATA <= x"66"; when x"4B4" => DATA <= x"85"; when x"4B5" => DATA <= x"66"; when x"4B6" => DATA <= x"BD"; when x"4B7" => DATA <= x"02"; when x"4B8" => DATA <= x"F2"; when x"4B9" => DATA <= x"A2"; when x"4BA" => DATA <= x"00"; when x"4BB" => DATA <= x"86"; when x"4BC" => DATA <= x"04"; when x"4BD" => DATA <= x"A4"; when x"4BE" => DATA <= x"16"; when x"4BF" => DATA <= x"84"; when x"4C0" => DATA <= x"67"; when x"4C1" => DATA <= x"A4"; when x"4C2" => DATA <= x"25"; when x"4C3" => DATA <= x"84"; when x"4C4" => DATA <= x"68"; when x"4C5" => DATA <= x"C9"; when x"4C6" => DATA <= x"0F"; when x"4C7" => DATA <= x"F0"; when x"4C8" => DATA <= x"23"; when x"4C9" => DATA <= x"29"; when x"4CA" => DATA <= x"0F"; when x"4CB" => DATA <= x"A8"; when x"4CC" => DATA <= x"C8"; when x"4CD" => DATA <= x"84"; when x"4CE" => DATA <= x"00"; when x"4CF" => DATA <= x"C0"; when x"4D0" => DATA <= x"02"; when x"4D1" => DATA <= x"D0"; when x"4D2" => DATA <= x"04"; when x"4D3" => DATA <= x"A4"; when x"4D4" => DATA <= x"68"; when x"4D5" => DATA <= x"D0"; when x"4D6" => DATA <= x"C3"; when x"4D7" => DATA <= x"A0"; when x"4D8" => DATA <= x"00"; when x"4D9" => DATA <= x"B9"; when x"4DA" => DATA <= x"66"; when x"4DB" => DATA <= x"00"; when x"4DC" => DATA <= x"91"; when x"4DD" => DATA <= x"52"; when x"4DE" => DATA <= x"C8"; when x"4DF" => DATA <= x"EE"; when x"4E0" => DATA <= x"31"; when x"4E1" => DATA <= x"03"; when x"4E2" => DATA <= x"D0"; when x"4E3" => DATA <= x"03"; when x"4E4" => DATA <= x"EE"; when x"4E5" => DATA <= x"4C"; when x"4E6" => DATA <= x"03"; when x"4E7" => DATA <= x"C4"; when x"4E8" => DATA <= x"00"; when x"4E9" => DATA <= x"D0"; when x"4EA" => DATA <= x"EE"; when x"4EB" => DATA <= x"60"; when x"4EC" => DATA <= x"A9"; when x"4ED" => DATA <= x"02"; when x"4EE" => DATA <= x"85"; when x"4EF" => DATA <= x"00"; when x"4F0" => DATA <= x"38"; when x"4F1" => DATA <= x"A5"; when x"4F2" => DATA <= x"67"; when x"4F3" => DATA <= x"ED"; when x"4F4" => DATA <= x"31"; when x"4F5" => DATA <= x"03"; when x"4F6" => DATA <= x"85"; when x"4F7" => DATA <= x"67"; when x"4F8" => DATA <= x"A5"; when x"4F9" => DATA <= x"68"; when x"4FA" => DATA <= x"ED"; when x"4FB" => DATA <= x"4C"; when x"4FC" => DATA <= x"03"; when x"4FD" => DATA <= x"85"; when x"4FE" => DATA <= x"68"; when x"4FF" => DATA <= x"38"; when x"500" => DATA <= x"A5"; when x"501" => DATA <= x"67"; when x"502" => DATA <= x"E9"; when x"503" => DATA <= x"02"; when x"504" => DATA <= x"85"; when x"505" => DATA <= x"67"; when x"506" => DATA <= x"A8"; when x"507" => DATA <= x"A5"; when x"508" => DATA <= x"68"; when x"509" => DATA <= x"E9"; when x"50A" => DATA <= x"00"; when x"50B" => DATA <= x"F0"; when x"50C" => DATA <= x"1F"; when x"50D" => DATA <= x"C9"; when x"50E" => DATA <= x"FF"; when x"50F" => DATA <= x"F0"; when x"510" => DATA <= x"16"; when x"511" => DATA <= x"20"; when x"512" => DATA <= x"D1"; when x"513" => DATA <= x"F7"; when x"514" => DATA <= x"4F"; when x"515" => DATA <= x"55"; when x"516" => DATA <= x"54"; when x"517" => DATA <= x"20"; when x"518" => DATA <= x"4F"; when x"519" => DATA <= x"46"; when x"51A" => DATA <= x"20"; when x"51B" => DATA <= x"52"; when x"51C" => DATA <= x"41"; when x"51D" => DATA <= x"4E"; when x"51E" => DATA <= x"47"; when x"51F" => DATA <= x"45"; when x"520" => DATA <= x"3A"; when x"521" => DATA <= x"0A"; when x"522" => DATA <= x"0D"; when x"523" => DATA <= x"84"; when x"524" => DATA <= x"67"; when x"525" => DATA <= x"30"; when x"526" => DATA <= x"B0"; when x"527" => DATA <= x"98"; when x"528" => DATA <= x"30"; when x"529" => DATA <= x"AD"; when x"52A" => DATA <= x"10"; when x"52B" => DATA <= x"E5"; when x"52C" => DATA <= x"98"; when x"52D" => DATA <= x"10"; when x"52E" => DATA <= x"A8"; when x"52F" => DATA <= x"30"; when x"530" => DATA <= x"E0"; when x"531" => DATA <= x"20"; when x"532" => DATA <= x"E4"; when x"533" => DATA <= x"C4"; when x"534" => DATA <= x"88"; when x"535" => DATA <= x"84"; when x"536" => DATA <= x"52"; when x"537" => DATA <= x"A5"; when x"538" => DATA <= x"12"; when x"539" => DATA <= x"85"; when x"53A" => DATA <= x"53"; when x"53B" => DATA <= x"98"; when x"53C" => DATA <= x"C8"; when x"53D" => DATA <= x"91"; when x"53E" => DATA <= x"52"; when x"53F" => DATA <= x"4C"; when x"540" => DATA <= x"9B"; when x"541" => DATA <= x"CD"; when x"542" => DATA <= x"A2"; when x"543" => DATA <= x"05"; when x"544" => DATA <= x"D0"; when x"545" => DATA <= x"02"; when x"546" => DATA <= x"A2"; when x"547" => DATA <= x"0C"; when x"548" => DATA <= x"86"; when x"549" => DATA <= x"16"; when x"54A" => DATA <= x"E6"; when x"54B" => DATA <= x"04"; when x"54C" => DATA <= x"D0"; when x"54D" => DATA <= x"06"; when x"54E" => DATA <= x"20"; when x"54F" => DATA <= x"BC"; when x"550" => DATA <= x"C8"; when x"551" => DATA <= x"20"; when x"552" => DATA <= x"31"; when x"553" => DATA <= x"C2"; when x"554" => DATA <= x"20"; when x"555" => DATA <= x"BC"; when x"556" => DATA <= x"C8"; when x"557" => DATA <= x"20"; when x"558" => DATA <= x"31"; when x"559" => DATA <= x"C2"; when x"55A" => DATA <= x"20"; when x"55B" => DATA <= x"BC"; when x"55C" => DATA <= x"C8"; when x"55D" => DATA <= x"20"; when x"55E" => DATA <= x"E4"; when x"55F" => DATA <= x"C4"; when x"560" => DATA <= x"B5"; when x"561" => DATA <= x"15"; when x"562" => DATA <= x"85"; when x"563" => DATA <= x"5C"; when x"564" => DATA <= x"B5"; when x"565" => DATA <= x"24"; when x"566" => DATA <= x"85"; when x"567" => DATA <= x"5D"; when x"568" => DATA <= x"B5"; when x"569" => DATA <= x"14"; when x"56A" => DATA <= x"85"; when x"56B" => DATA <= x"5A"; when x"56C" => DATA <= x"B5"; when x"56D" => DATA <= x"23"; when x"56E" => DATA <= x"85"; when x"56F" => DATA <= x"5B"; when x"570" => DATA <= x"A2"; when x"571" => DATA <= x"00"; when x"572" => DATA <= x"86"; when x"573" => DATA <= x"04"; when x"574" => DATA <= x"A2"; when x"575" => DATA <= x"03"; when x"576" => DATA <= x"BD"; when x"577" => DATA <= x"C1"; when x"578" => DATA <= x"03"; when x"579" => DATA <= x"95"; when x"57A" => DATA <= x"52"; when x"57B" => DATA <= x"CA"; when x"57C" => DATA <= x"10"; when x"57D" => DATA <= x"F8"; when x"57E" => DATA <= x"A5"; when x"57F" => DATA <= x"16"; when x"580" => DATA <= x"29"; when x"581" => DATA <= x"04"; when x"582" => DATA <= x"D0"; when x"583" => DATA <= x"13"; when x"584" => DATA <= x"A2"; when x"585" => DATA <= x"02"; when x"586" => DATA <= x"18"; when x"587" => DATA <= x"B5"; when x"588" => DATA <= x"5A"; when x"589" => DATA <= x"75"; when x"58A" => DATA <= x"52"; when x"58B" => DATA <= x"95"; when x"58C" => DATA <= x"5A"; when x"58D" => DATA <= x"B5"; when x"58E" => DATA <= x"5B"; when x"58F" => DATA <= x"75"; when x"590" => DATA <= x"53"; when x"591" => DATA <= x"95"; when x"592" => DATA <= x"5B"; when x"593" => DATA <= x"CA"; when x"594" => DATA <= x"CA"; when x"595" => DATA <= x"10"; when x"596" => DATA <= x"EF"; when x"597" => DATA <= x"A2"; when x"598" => DATA <= x"03"; when x"599" => DATA <= x"B5"; when x"59A" => DATA <= x"5A"; when x"59B" => DATA <= x"9D"; when x"59C" => DATA <= x"C1"; when x"59D" => DATA <= x"03"; when x"59E" => DATA <= x"CA"; when x"59F" => DATA <= x"10"; when x"5A0" => DATA <= x"F8"; when x"5A1" => DATA <= x"A5"; when x"5A2" => DATA <= x"16"; when x"5A3" => DATA <= x"29"; when x"5A4" => DATA <= x"03"; when x"5A5" => DATA <= x"F0"; when x"5A6" => DATA <= x"0B"; when x"5A7" => DATA <= x"85"; when x"5A8" => DATA <= x"5E"; when x"5A9" => DATA <= x"A5"; when x"5AA" => DATA <= x"16"; when x"5AB" => DATA <= x"29"; when x"5AC" => DATA <= x"08"; when x"5AD" => DATA <= x"F0"; when x"5AE" => DATA <= x"06"; when x"5AF" => DATA <= x"20"; when x"5B0" => DATA <= x"78"; when x"5B1" => DATA <= x"F6"; when x"5B2" => DATA <= x"4C"; when x"5B3" => DATA <= x"5B"; when x"5B4" => DATA <= x"C5"; when x"5B5" => DATA <= x"A2"; when x"5B6" => DATA <= x"02"; when x"5B7" => DATA <= x"38"; when x"5B8" => DATA <= x"B5"; when x"5B9" => DATA <= x"5A"; when x"5BA" => DATA <= x"F5"; when x"5BB" => DATA <= x"52"; when x"5BC" => DATA <= x"B4"; when x"5BD" => DATA <= x"52"; when x"5BE" => DATA <= x"94"; when x"5BF" => DATA <= x"5A"; when x"5C0" => DATA <= x"95"; when x"5C1" => DATA <= x"52"; when x"5C2" => DATA <= x"B4"; when x"5C3" => DATA <= x"53"; when x"5C4" => DATA <= x"B5"; when x"5C5" => DATA <= x"5B"; when x"5C6" => DATA <= x"F5"; when x"5C7" => DATA <= x"53"; when x"5C8" => DATA <= x"94"; when x"5C9" => DATA <= x"5B"; when x"5CA" => DATA <= x"95"; when x"5CB" => DATA <= x"53"; when x"5CC" => DATA <= x"95"; when x"5CD" => DATA <= x"56"; when x"5CE" => DATA <= x"10"; when x"5CF" => DATA <= x"0D"; when x"5D0" => DATA <= x"A9"; when x"5D1" => DATA <= x"00"; when x"5D2" => DATA <= x"38"; when x"5D3" => DATA <= x"F5"; when x"5D4" => DATA <= x"52"; when x"5D5" => DATA <= x"95"; when x"5D6" => DATA <= x"52"; when x"5D7" => DATA <= x"A9"; when x"5D8" => DATA <= x"00"; when x"5D9" => DATA <= x"F5"; when x"5DA" => DATA <= x"53"; when x"5DB" => DATA <= x"95"; when x"5DC" => DATA <= x"53"; when x"5DD" => DATA <= x"CA"; when x"5DE" => DATA <= x"CA"; when x"5DF" => DATA <= x"10"; when x"5E0" => DATA <= x"D6"; when x"5E1" => DATA <= x"A5"; when x"5E2" => DATA <= x"54"; when x"5E3" => DATA <= x"C5"; when x"5E4" => DATA <= x"52"; when x"5E5" => DATA <= x"A5"; when x"5E6" => DATA <= x"55"; when x"5E7" => DATA <= x"E5"; when x"5E8" => DATA <= x"53"; when x"5E9" => DATA <= x"90"; when x"5EA" => DATA <= x"31"; when x"5EB" => DATA <= x"A9"; when x"5EC" => DATA <= x"00"; when x"5ED" => DATA <= x"E5"; when x"5EE" => DATA <= x"54"; when x"5EF" => DATA <= x"85"; when x"5F0" => DATA <= x"57"; when x"5F1" => DATA <= x"A9"; when x"5F2" => DATA <= x"00"; when x"5F3" => DATA <= x"E5"; when x"5F4" => DATA <= x"55"; when x"5F5" => DATA <= x"38"; when x"5F6" => DATA <= x"6A"; when x"5F7" => DATA <= x"85"; when x"5F8" => DATA <= x"59"; when x"5F9" => DATA <= x"66"; when x"5FA" => DATA <= x"57"; when x"5FB" => DATA <= x"20"; when x"5FC" => DATA <= x"78"; when x"5FD" => DATA <= x"F6"; when x"5FE" => DATA <= x"A5"; when x"5FF" => DATA <= x"5C"; when x"600" => DATA <= x"CD"; when x"601" => DATA <= x"C3"; when x"602" => DATA <= x"03"; when x"603" => DATA <= x"D0"; when x"604" => DATA <= x"0A"; when x"605" => DATA <= x"A5"; when x"606" => DATA <= x"5D"; when x"607" => DATA <= x"CD"; when x"608" => DATA <= x"C4"; when x"609" => DATA <= x"03"; when x"60A" => DATA <= x"D0"; when x"60B" => DATA <= x"03"; when x"60C" => DATA <= x"4C"; when x"60D" => DATA <= x"5B"; when x"60E" => DATA <= x"C5"; when x"60F" => DATA <= x"20"; when x"610" => DATA <= x"55"; when x"611" => DATA <= x"F6"; when x"612" => DATA <= x"A5"; when x"613" => DATA <= x"59"; when x"614" => DATA <= x"30"; when x"615" => DATA <= x"E5"; when x"616" => DATA <= x"20"; when x"617" => DATA <= x"44"; when x"618" => DATA <= x"F6"; when x"619" => DATA <= x"4C"; when x"61A" => DATA <= x"FB"; when x"61B" => DATA <= x"F5"; when x"61C" => DATA <= x"A5"; when x"61D" => DATA <= x"53"; when x"61E" => DATA <= x"4A"; when x"61F" => DATA <= x"85"; when x"620" => DATA <= x"59"; when x"621" => DATA <= x"A5"; when x"622" => DATA <= x"52"; when x"623" => DATA <= x"6A"; when x"624" => DATA <= x"85"; when x"625" => DATA <= x"57"; when x"626" => DATA <= x"20"; when x"627" => DATA <= x"78"; when x"628" => DATA <= x"F6"; when x"629" => DATA <= x"A5"; when x"62A" => DATA <= x"5A"; when x"62B" => DATA <= x"CD"; when x"62C" => DATA <= x"C1"; when x"62D" => DATA <= x"03"; when x"62E" => DATA <= x"D0"; when x"62F" => DATA <= x"07"; when x"630" => DATA <= x"A5"; when x"631" => DATA <= x"5B"; when x"632" => DATA <= x"CD"; when x"633" => DATA <= x"C2"; when x"634" => DATA <= x"03"; when x"635" => DATA <= x"F0"; when x"636" => DATA <= x"D5"; when x"637" => DATA <= x"20"; when x"638" => DATA <= x"44"; when x"639" => DATA <= x"F6"; when x"63A" => DATA <= x"A5"; when x"63B" => DATA <= x"59"; when x"63C" => DATA <= x"10"; when x"63D" => DATA <= x"E8"; when x"63E" => DATA <= x"20"; when x"63F" => DATA <= x"55"; when x"640" => DATA <= x"F6"; when x"641" => DATA <= x"4C"; when x"642" => DATA <= x"26"; when x"643" => DATA <= x"F6"; when x"644" => DATA <= x"38"; when x"645" => DATA <= x"A5"; when x"646" => DATA <= x"57"; when x"647" => DATA <= x"E5"; when x"648" => DATA <= x"54"; when x"649" => DATA <= x"85"; when x"64A" => DATA <= x"57"; when x"64B" => DATA <= x"A5"; when x"64C" => DATA <= x"59"; when x"64D" => DATA <= x"E5"; when x"64E" => DATA <= x"55"; when x"64F" => DATA <= x"85"; when x"650" => DATA <= x"59"; when x"651" => DATA <= x"A2"; when x"652" => DATA <= x"00"; when x"653" => DATA <= x"F0"; when x"654" => DATA <= x"0F"; when x"655" => DATA <= x"18"; when x"656" => DATA <= x"A5"; when x"657" => DATA <= x"57"; when x"658" => DATA <= x"65"; when x"659" => DATA <= x"52"; when x"65A" => DATA <= x"85"; when x"65B" => DATA <= x"57"; when x"65C" => DATA <= x"A5"; when x"65D" => DATA <= x"59"; when x"65E" => DATA <= x"65"; when x"65F" => DATA <= x"53"; when x"660" => DATA <= x"85"; when x"661" => DATA <= x"59"; when x"662" => DATA <= x"A2"; when x"663" => DATA <= x"02"; when x"664" => DATA <= x"B5"; when x"665" => DATA <= x"56"; when x"666" => DATA <= x"10"; when x"667" => DATA <= x"09"; when x"668" => DATA <= x"B5"; when x"669" => DATA <= x"5A"; when x"66A" => DATA <= x"D0"; when x"66B" => DATA <= x"02"; when x"66C" => DATA <= x"D6"; when x"66D" => DATA <= x"5B"; when x"66E" => DATA <= x"D6"; when x"66F" => DATA <= x"5A"; when x"670" => DATA <= x"60"; when x"671" => DATA <= x"F6"; when x"672" => DATA <= x"5A"; when x"673" => DATA <= x"D0"; when x"674" => DATA <= x"FB"; when x"675" => DATA <= x"F6"; when x"676" => DATA <= x"5B"; when x"677" => DATA <= x"60"; when x"678" => DATA <= x"6C"; when x"679" => DATA <= x"FE"; when x"67A" => DATA <= x"03"; when x"67B" => DATA <= x"20"; when x"67C" => DATA <= x"C8"; when x"67D" => DATA <= x"C3"; when x"67E" => DATA <= x"A0"; when x"67F" => DATA <= x"00"; when x"680" => DATA <= x"A5"; when x"681" => DATA <= x"52"; when x"682" => DATA <= x"F0"; when x"683" => DATA <= x"3E"; when x"684" => DATA <= x"C9"; when x"685" => DATA <= x"05"; when x"686" => DATA <= x"90"; when x"687" => DATA <= x"02"; when x"688" => DATA <= x"A9"; when x"689" => DATA <= x"04"; when x"68A" => DATA <= x"A2"; when x"68B" => DATA <= x"80"; when x"68C" => DATA <= x"86"; when x"68D" => DATA <= x"54"; when x"68E" => DATA <= x"84"; when x"68F" => DATA <= x"53"; when x"690" => DATA <= x"85"; when x"691" => DATA <= x"52"; when x"692" => DATA <= x"AA"; when x"693" => DATA <= x"BD"; when x"694" => DATA <= x"CE"; when x"695" => DATA <= x"F6"; when x"696" => DATA <= x"A6"; when x"697" => DATA <= x"12"; when x"698" => DATA <= x"10"; when x"699" => DATA <= x"04"; when x"69A" => DATA <= x"C5"; when x"69B" => DATA <= x"12"; when x"69C" => DATA <= x"B0"; when x"69D" => DATA <= x"E1"; when x"69E" => DATA <= x"AA"; when x"69F" => DATA <= x"98"; when x"6A0" => DATA <= x"91"; when x"6A1" => DATA <= x"53"; when x"6A2" => DATA <= x"88"; when x"6A3" => DATA <= x"D0"; when x"6A4" => DATA <= x"FB"; when x"6A5" => DATA <= x"E6"; when x"6A6" => DATA <= x"54"; when x"6A7" => DATA <= x"E4"; when x"6A8" => DATA <= x"54"; when x"6A9" => DATA <= x"D0"; when x"6AA" => DATA <= x"F5"; when x"6AB" => DATA <= x"A4"; when x"6AC" => DATA <= x"52"; when x"6AD" => DATA <= x"B9"; when x"6AE" => DATA <= x"D8"; when x"6AF" => DATA <= x"F6"; when x"6B0" => DATA <= x"8D"; when x"6B1" => DATA <= x"FF"; when x"6B2" => DATA <= x"03"; when x"6B3" => DATA <= x"B9"; when x"6B4" => DATA <= x"D3"; when x"6B5" => DATA <= x"F6"; when x"6B6" => DATA <= x"8D"; when x"6B7" => DATA <= x"FE"; when x"6B8" => DATA <= x"03"; when x"6B9" => DATA <= x"B9"; when x"6BA" => DATA <= x"DD"; when x"6BB" => DATA <= x"F6"; when x"6BC" => DATA <= x"8D"; when x"6BD" => DATA <= x"00"; when x"6BE" => DATA <= x"B0"; when x"6BF" => DATA <= x"4C"; when x"6C0" => DATA <= x"58"; when x"6C1" => DATA <= x"C5"; when x"6C2" => DATA <= x"A9"; when x"6C3" => DATA <= x"40"; when x"6C4" => DATA <= x"99"; when x"6C5" => DATA <= x"00"; when x"6C6" => DATA <= x"80"; when x"6C7" => DATA <= x"99"; when x"6C8" => DATA <= x"00"; when x"6C9" => DATA <= x"81"; when x"6CA" => DATA <= x"88"; when x"6CB" => DATA <= x"D0"; when x"6CC" => DATA <= x"F7"; when x"6CD" => DATA <= x"F0"; when x"6CE" => DATA <= x"DC"; when x"6CF" => DATA <= x"84"; when x"6D0" => DATA <= x"86"; when x"6D1" => DATA <= x"8C"; when x"6D2" => DATA <= x"98"; when x"6D3" => DATA <= x"E2"; when x"6D4" => DATA <= x"3B"; when x"6D5" => DATA <= x"54"; when x"6D6" => DATA <= x"6D"; when x"6D7" => DATA <= x"AA"; when x"6D8" => DATA <= x"F6"; when x"6D9" => DATA <= x"F7"; when x"6DA" => DATA <= x"F7"; when x"6DB" => DATA <= x"F7"; when x"6DC" => DATA <= x"F7"; when x"6DD" => DATA <= x"00"; when x"6DE" => DATA <= x"30"; when x"6DF" => DATA <= x"70"; when x"6E0" => DATA <= x"B0"; when x"6E1" => DATA <= x"F0"; when x"6E2" => DATA <= x"A5"; when x"6E3" => DATA <= x"5B"; when x"6E4" => DATA <= x"05"; when x"6E5" => DATA <= x"5D"; when x"6E6" => DATA <= x"D0"; when x"6E7" => DATA <= x"52"; when x"6E8" => DATA <= x"A5"; when x"6E9" => DATA <= x"5A"; when x"6EA" => DATA <= x"C9"; when x"6EB" => DATA <= x"40"; when x"6EC" => DATA <= x"B0"; when x"6ED" => DATA <= x"4C"; when x"6EE" => DATA <= x"4A"; when x"6EF" => DATA <= x"85"; when x"6F0" => DATA <= x"5F"; when x"6F1" => DATA <= x"A9"; when x"6F2" => DATA <= x"2F"; when x"6F3" => DATA <= x"38"; when x"6F4" => DATA <= x"E5"; when x"6F5" => DATA <= x"5C"; when x"6F6" => DATA <= x"C9"; when x"6F7" => DATA <= x"30"; when x"6F8" => DATA <= x"B0"; when x"6F9" => DATA <= x"40"; when x"6FA" => DATA <= x"A2"; when x"6FB" => DATA <= x"FF"; when x"6FC" => DATA <= x"38"; when x"6FD" => DATA <= x"E8"; when x"6FE" => DATA <= x"E9"; when x"6FF" => DATA <= x"03"; when x"700" => DATA <= x"B0"; when x"701" => DATA <= x"FB"; when x"702" => DATA <= x"69"; when x"703" => DATA <= x"03"; when x"704" => DATA <= x"85"; when x"705" => DATA <= x"61"; when x"706" => DATA <= x"8A"; when x"707" => DATA <= x"0A"; when x"708" => DATA <= x"0A"; when x"709" => DATA <= x"0A"; when x"70A" => DATA <= x"0A"; when x"70B" => DATA <= x"0A"; when x"70C" => DATA <= x"05"; when x"70D" => DATA <= x"5F"; when x"70E" => DATA <= x"85"; when x"70F" => DATA <= x"5F"; when x"710" => DATA <= x"A9"; when x"711" => DATA <= x"80"; when x"712" => DATA <= x"69"; when x"713" => DATA <= x"00"; when x"714" => DATA <= x"85"; when x"715" => DATA <= x"60"; when x"716" => DATA <= x"A5"; when x"717" => DATA <= x"5A"; when x"718" => DATA <= x"4A"; when x"719" => DATA <= x"A5"; when x"71A" => DATA <= x"61"; when x"71B" => DATA <= x"2A"; when x"71C" => DATA <= x"A8"; when x"71D" => DATA <= x"B9"; when x"71E" => DATA <= x"CB"; when x"71F" => DATA <= x"F7"; when x"720" => DATA <= x"A0"; when x"721" => DATA <= x"00"; when x"722" => DATA <= x"A6"; when x"723" => DATA <= x"5E"; when x"724" => DATA <= x"CA"; when x"725" => DATA <= x"F0"; when x"726" => DATA <= x"0F"; when x"727" => DATA <= x"CA"; when x"728" => DATA <= x"F0"; when x"729" => DATA <= x"07"; when x"72A" => DATA <= x"49"; when x"72B" => DATA <= x"FF"; when x"72C" => DATA <= x"31"; when x"72D" => DATA <= x"5F"; when x"72E" => DATA <= x"91"; when x"72F" => DATA <= x"5F"; when x"730" => DATA <= x"60"; when x"731" => DATA <= x"51"; when x"732" => DATA <= x"5F"; when x"733" => DATA <= x"91"; when x"734" => DATA <= x"5F"; when x"735" => DATA <= x"60"; when x"736" => DATA <= x"11"; when x"737" => DATA <= x"5F"; when x"738" => DATA <= x"91"; when x"739" => DATA <= x"5F"; when x"73A" => DATA <= x"60"; when x"73B" => DATA <= x"A5"; when x"73C" => DATA <= x"5B"; when x"73D" => DATA <= x"05"; when x"73E" => DATA <= x"5D"; when x"73F" => DATA <= x"D0"; when x"740" => DATA <= x"F9"; when x"741" => DATA <= x"A5"; when x"742" => DATA <= x"5A"; when x"743" => DATA <= x"30"; when x"744" => DATA <= x"F5"; when x"745" => DATA <= x"4A"; when x"746" => DATA <= x"4A"; when x"747" => DATA <= x"4A"; when x"748" => DATA <= x"85"; when x"749" => DATA <= x"5F"; when x"74A" => DATA <= x"A9"; when x"74B" => DATA <= x"3F"; when x"74C" => DATA <= x"38"; when x"74D" => DATA <= x"E5"; when x"74E" => DATA <= x"5C"; when x"74F" => DATA <= x"C9"; when x"750" => DATA <= x"40"; when x"751" => DATA <= x"90"; when x"752" => DATA <= x"32"; when x"753" => DATA <= x"60"; when x"754" => DATA <= x"A5"; when x"755" => DATA <= x"5B"; when x"756" => DATA <= x"05"; when x"757" => DATA <= x"5D"; when x"758" => DATA <= x"D0"; when x"759" => DATA <= x"E0"; when x"75A" => DATA <= x"A5"; when x"75B" => DATA <= x"5A"; when x"75C" => DATA <= x"30"; when x"75D" => DATA <= x"DC"; when x"75E" => DATA <= x"4A"; when x"75F" => DATA <= x"4A"; when x"760" => DATA <= x"4A"; when x"761" => DATA <= x"85"; when x"762" => DATA <= x"5F"; when x"763" => DATA <= x"A9"; when x"764" => DATA <= x"5F"; when x"765" => DATA <= x"38"; when x"766" => DATA <= x"E5"; when x"767" => DATA <= x"5C"; when x"768" => DATA <= x"C9"; when x"769" => DATA <= x"60"; when x"76A" => DATA <= x"90"; when x"76B" => DATA <= x"19"; when x"76C" => DATA <= x"60"; when x"76D" => DATA <= x"A5"; when x"76E" => DATA <= x"5B"; when x"76F" => DATA <= x"05"; when x"770" => DATA <= x"5D"; when x"771" => DATA <= x"D0"; when x"772" => DATA <= x"C7"; when x"773" => DATA <= x"A5"; when x"774" => DATA <= x"5A"; when x"775" => DATA <= x"30"; when x"776" => DATA <= x"C3"; when x"777" => DATA <= x"4A"; when x"778" => DATA <= x"4A"; when x"779" => DATA <= x"4A"; when x"77A" => DATA <= x"85"; when x"77B" => DATA <= x"5F"; when x"77C" => DATA <= x"A9"; when x"77D" => DATA <= x"BF"; when x"77E" => DATA <= x"38"; when x"77F" => DATA <= x"E5"; when x"780" => DATA <= x"5C"; when x"781" => DATA <= x"C9"; when x"782" => DATA <= x"C0"; when x"783" => DATA <= x"B0"; when x"784" => DATA <= x"B5"; when x"785" => DATA <= x"A0"; when x"786" => DATA <= x"00"; when x"787" => DATA <= x"84"; when x"788" => DATA <= x"60"; when x"789" => DATA <= x"0A"; when x"78A" => DATA <= x"26"; when x"78B" => DATA <= x"60"; when x"78C" => DATA <= x"0A"; when x"78D" => DATA <= x"26"; when x"78E" => DATA <= x"60"; when x"78F" => DATA <= x"0A"; when x"790" => DATA <= x"26"; when x"791" => DATA <= x"60"; when x"792" => DATA <= x"0A"; when x"793" => DATA <= x"26"; when x"794" => DATA <= x"60"; when x"795" => DATA <= x"65"; when x"796" => DATA <= x"5F"; when x"797" => DATA <= x"85"; when x"798" => DATA <= x"5F"; when x"799" => DATA <= x"A5"; when x"79A" => DATA <= x"60"; when x"79B" => DATA <= x"69"; when x"79C" => DATA <= x"80"; when x"79D" => DATA <= x"85"; when x"79E" => DATA <= x"60"; when x"79F" => DATA <= x"A5"; when x"7A0" => DATA <= x"5A"; when x"7A1" => DATA <= x"29"; when x"7A2" => DATA <= x"07"; when x"7A3" => DATA <= x"A8"; when x"7A4" => DATA <= x"B9"; when x"7A5" => DATA <= x"C9"; when x"7A6" => DATA <= x"F7"; when x"7A7" => DATA <= x"4C"; when x"7A8" => DATA <= x"20"; when x"7A9" => DATA <= x"F7"; when x"7AA" => DATA <= x"A5"; when x"7AB" => DATA <= x"5B"; when x"7AC" => DATA <= x"05"; when x"7AD" => DATA <= x"5D"; when x"7AE" => DATA <= x"D0"; when x"7AF" => DATA <= x"BC"; when x"7B0" => DATA <= x"A5"; when x"7B1" => DATA <= x"5A"; when x"7B2" => DATA <= x"4A"; when x"7B3" => DATA <= x"4A"; when x"7B4" => DATA <= x"4A"; when x"7B5" => DATA <= x"85"; when x"7B6" => DATA <= x"5F"; when x"7B7" => DATA <= x"A9"; when x"7B8" => DATA <= x"BF"; when x"7B9" => DATA <= x"38"; when x"7BA" => DATA <= x"E5"; when x"7BB" => DATA <= x"5C"; when x"7BC" => DATA <= x"C9"; when x"7BD" => DATA <= x"C0"; when x"7BE" => DATA <= x"B0"; when x"7BF" => DATA <= x"AC"; when x"7C0" => DATA <= x"A0"; when x"7C1" => DATA <= x"00"; when x"7C2" => DATA <= x"84"; when x"7C3" => DATA <= x"60"; when x"7C4" => DATA <= x"0A"; when x"7C5" => DATA <= x"26"; when x"7C6" => DATA <= x"60"; when x"7C7" => DATA <= x"10"; when x"7C8" => DATA <= x"C0"; when x"7C9" => DATA <= x"80"; when x"7CA" => DATA <= x"40"; when x"7CB" => DATA <= x"20"; when x"7CC" => DATA <= x"10"; when x"7CD" => DATA <= x"08"; when x"7CE" => DATA <= x"04"; when x"7CF" => DATA <= x"02"; when x"7D0" => DATA <= x"01"; when x"7D1" => DATA <= x"68"; when x"7D2" => DATA <= x"85"; when x"7D3" => DATA <= x"E8"; when x"7D4" => DATA <= x"68"; when x"7D5" => DATA <= x"85"; when x"7D6" => DATA <= x"E9"; when x"7D7" => DATA <= x"A0"; when x"7D8" => DATA <= x"00"; when x"7D9" => DATA <= x"E6"; when x"7DA" => DATA <= x"E8"; when x"7DB" => DATA <= x"D0"; when x"7DC" => DATA <= x"02"; when x"7DD" => DATA <= x"E6"; when x"7DE" => DATA <= x"E9"; when x"7DF" => DATA <= x"B1"; when x"7E0" => DATA <= x"E8"; when x"7E1" => DATA <= x"30"; when x"7E2" => DATA <= x"06"; when x"7E3" => DATA <= x"20"; when x"7E4" => DATA <= x"F4"; when x"7E5" => DATA <= x"FF"; when x"7E6" => DATA <= x"4C"; when x"7E7" => DATA <= x"D7"; when x"7E8" => DATA <= x"F7"; when x"7E9" => DATA <= x"6C"; when x"7EA" => DATA <= x"E8"; when x"7EB" => DATA <= x"00"; when x"7EC" => DATA <= x"A2"; when x"7ED" => DATA <= x"D4"; when x"7EE" => DATA <= x"20"; when x"7EF" => DATA <= x"F1"; when x"7F0" => DATA <= x"F7"; when x"7F1" => DATA <= x"B5"; when x"7F2" => DATA <= x"01"; when x"7F3" => DATA <= x"20"; when x"7F4" => DATA <= x"02"; when x"7F5" => DATA <= x"F8"; when x"7F6" => DATA <= x"E8"; when x"7F7" => DATA <= x"E8"; when x"7F8" => DATA <= x"B5"; when x"7F9" => DATA <= x"FE"; when x"7FA" => DATA <= x"20"; when x"7FB" => DATA <= x"02"; when x"7FC" => DATA <= x"F8"; when x"7FD" => DATA <= x"A9"; when x"7FE" => DATA <= x"20"; when x"7FF" => DATA <= x"4C"; when x"800" => DATA <= x"F4"; when x"801" => DATA <= x"FF"; when x"802" => DATA <= x"48"; when x"803" => DATA <= x"4A"; when x"804" => DATA <= x"4A"; when x"805" => DATA <= x"4A"; when x"806" => DATA <= x"4A"; when x"807" => DATA <= x"20"; when x"808" => DATA <= x"0B"; when x"809" => DATA <= x"F8"; when x"80A" => DATA <= x"68"; when x"80B" => DATA <= x"29"; when x"80C" => DATA <= x"0F"; when x"80D" => DATA <= x"C9"; when x"80E" => DATA <= x"0A"; when x"80F" => DATA <= x"90"; when x"810" => DATA <= x"02"; when x"811" => DATA <= x"69"; when x"812" => DATA <= x"06"; when x"813" => DATA <= x"69"; when x"814" => DATA <= x"30"; when x"815" => DATA <= x"4C"; when x"816" => DATA <= x"F4"; when x"817" => DATA <= x"FF"; when x"818" => DATA <= x"20"; when x"819" => DATA <= x"76"; when x"81A" => DATA <= x"F8"; when x"81B" => DATA <= x"A2"; when x"81C" => DATA <= x"00"; when x"81D" => DATA <= x"C9"; when x"81E" => DATA <= x"22"; when x"81F" => DATA <= x"F0"; when x"820" => DATA <= x"06"; when x"821" => DATA <= x"E8"; when x"822" => DATA <= x"D0"; when x"823" => DATA <= x"1B"; when x"824" => DATA <= x"4C"; when x"825" => DATA <= x"7D"; when x"826" => DATA <= x"FA"; when x"827" => DATA <= x"C8"; when x"828" => DATA <= x"B9"; when x"829" => DATA <= x"00"; when x"82A" => DATA <= x"01"; when x"82B" => DATA <= x"C9"; when x"82C" => DATA <= x"0D"; when x"82D" => DATA <= x"F0"; when x"82E" => DATA <= x"F5"; when x"82F" => DATA <= x"9D"; when x"830" => DATA <= x"40"; when x"831" => DATA <= x"01"; when x"832" => DATA <= x"E8"; when x"833" => DATA <= x"C9"; when x"834" => DATA <= x"22"; when x"835" => DATA <= x"D0"; when x"836" => DATA <= x"F0"; when x"837" => DATA <= x"C8"; when x"838" => DATA <= x"B9"; when x"839" => DATA <= x"00"; when x"83A" => DATA <= x"01"; when x"83B" => DATA <= x"C9"; when x"83C" => DATA <= x"22"; when x"83D" => DATA <= x"F0"; when x"83E" => DATA <= x"E8"; when x"83F" => DATA <= x"A9"; when x"840" => DATA <= x"0D"; when x"841" => DATA <= x"9D"; when x"842" => DATA <= x"3F"; when x"843" => DATA <= x"01"; when x"844" => DATA <= x"A9"; when x"845" => DATA <= x"40"; when x"846" => DATA <= x"85"; when x"847" => DATA <= x"C9"; when x"848" => DATA <= x"A9"; when x"849" => DATA <= x"01"; when x"84A" => DATA <= x"85"; when x"84B" => DATA <= x"CA"; when x"84C" => DATA <= x"A2"; when x"84D" => DATA <= x"C9"; when x"84E" => DATA <= x"60"; when x"84F" => DATA <= x"A0"; when x"850" => DATA <= x"00"; when x"851" => DATA <= x"B5"; when x"852" => DATA <= x"00"; when x"853" => DATA <= x"99"; when x"854" => DATA <= x"C9"; when x"855" => DATA <= x"00"; when x"856" => DATA <= x"E8"; when x"857" => DATA <= x"C8"; when x"858" => DATA <= x"C0"; when x"859" => DATA <= x"0A"; when x"85A" => DATA <= x"90"; when x"85B" => DATA <= x"F5"; when x"85C" => DATA <= x"A0"; when x"85D" => DATA <= x"FF"; when x"85E" => DATA <= x"A9"; when x"85F" => DATA <= x"0D"; when x"860" => DATA <= x"C8"; when x"861" => DATA <= x"C0"; when x"862" => DATA <= x"0E"; when x"863" => DATA <= x"B0"; when x"864" => DATA <= x"07"; when x"865" => DATA <= x"D1"; when x"866" => DATA <= x"C9"; when x"867" => DATA <= x"D0"; when x"868" => DATA <= x"F7"; when x"869" => DATA <= x"C0"; when x"86A" => DATA <= x"00"; when x"86B" => DATA <= x"60"; when x"86C" => DATA <= x"20"; when x"86D" => DATA <= x"D1"; when x"86E" => DATA <= x"F7"; when x"86F" => DATA <= x"4E"; when x"870" => DATA <= x"41"; when x"871" => DATA <= x"4D"; when x"872" => DATA <= x"45"; when x"873" => DATA <= x"EA"; when x"874" => DATA <= x"00"; when x"875" => DATA <= x"C8"; when x"876" => DATA <= x"B9"; when x"877" => DATA <= x"00"; when x"878" => DATA <= x"01"; when x"879" => DATA <= x"C9"; when x"87A" => DATA <= x"20"; when x"87B" => DATA <= x"F0"; when x"87C" => DATA <= x"F8"; when x"87D" => DATA <= x"60"; when x"87E" => DATA <= x"C9"; when x"87F" => DATA <= x"30"; when x"880" => DATA <= x"90"; when x"881" => DATA <= x"0F"; when x"882" => DATA <= x"C9"; when x"883" => DATA <= x"3A"; when x"884" => DATA <= x"90"; when x"885" => DATA <= x"08"; when x"886" => DATA <= x"E9"; when x"887" => DATA <= x"07"; when x"888" => DATA <= x"90"; when x"889" => DATA <= x"07"; when x"88A" => DATA <= x"C9"; when x"88B" => DATA <= x"40"; when x"88C" => DATA <= x"B0"; when x"88D" => DATA <= x"02"; when x"88E" => DATA <= x"29"; when x"88F" => DATA <= x"0F"; when x"890" => DATA <= x"60"; when x"891" => DATA <= x"38"; when x"892" => DATA <= x"60"; when x"893" => DATA <= x"A9"; when x"894" => DATA <= x"00"; when x"895" => DATA <= x"95"; when x"896" => DATA <= x"00"; when x"897" => DATA <= x"95"; when x"898" => DATA <= x"01"; when x"899" => DATA <= x"95"; when x"89A" => DATA <= x"02"; when x"89B" => DATA <= x"20"; when x"89C" => DATA <= x"76"; when x"89D" => DATA <= x"F8"; when x"89E" => DATA <= x"B9"; when x"89F" => DATA <= x"00"; when x"8A0" => DATA <= x"01"; when x"8A1" => DATA <= x"20"; when x"8A2" => DATA <= x"7E"; when x"8A3" => DATA <= x"F8"; when x"8A4" => DATA <= x"B0"; when x"8A5" => DATA <= x"15"; when x"8A6" => DATA <= x"0A"; when x"8A7" => DATA <= x"0A"; when x"8A8" => DATA <= x"0A"; when x"8A9" => DATA <= x"0A"; when x"8AA" => DATA <= x"94"; when x"8AB" => DATA <= x"02"; when x"8AC" => DATA <= x"A0"; when x"8AD" => DATA <= x"04"; when x"8AE" => DATA <= x"0A"; when x"8AF" => DATA <= x"36"; when x"8B0" => DATA <= x"00"; when x"8B1" => DATA <= x"36"; when x"8B2" => DATA <= x"01"; when x"8B3" => DATA <= x"88"; when x"8B4" => DATA <= x"D0"; when x"8B5" => DATA <= x"F8"; when x"8B6" => DATA <= x"B4"; when x"8B7" => DATA <= x"02"; when x"8B8" => DATA <= x"C8"; when x"8B9" => DATA <= x"D0"; when x"8BA" => DATA <= x"E3"; when x"8BB" => DATA <= x"B5"; when x"8BC" => DATA <= x"02"; when x"8BD" => DATA <= x"60"; when x"8BE" => DATA <= x"43"; when x"8BF" => DATA <= x"41"; when x"8C0" => DATA <= x"54"; when x"8C1" => DATA <= x"FA"; when x"8C2" => DATA <= x"2A"; when x"8C3" => DATA <= x"4C"; when x"8C4" => DATA <= x"4F"; when x"8C5" => DATA <= x"41"; when x"8C6" => DATA <= x"44"; when x"8C7" => DATA <= x"F9"; when x"8C8" => DATA <= x"58"; when x"8C9" => DATA <= x"53"; when x"8CA" => DATA <= x"41"; when x"8CB" => DATA <= x"56"; when x"8CC" => DATA <= x"45"; when x"8CD" => DATA <= x"FA"; when x"8CE" => DATA <= x"BB"; when x"8CF" => DATA <= x"52"; when x"8D0" => DATA <= x"55"; when x"8D1" => DATA <= x"4E"; when x"8D2" => DATA <= x"FA"; when x"8D3" => DATA <= x"20"; when x"8D4" => DATA <= x"4D"; when x"8D5" => DATA <= x"4F"; when x"8D6" => DATA <= x"4E"; when x"8D7" => DATA <= x"FA"; when x"8D8" => DATA <= x"1A"; when x"8D9" => DATA <= x"4E"; when x"8DA" => DATA <= x"4F"; when x"8DB" => DATA <= x"4D"; when x"8DC" => DATA <= x"4F"; when x"8DD" => DATA <= x"4E"; when x"8DE" => DATA <= x"FA"; when x"8DF" => DATA <= x"19"; when x"8E0" => DATA <= x"46"; when x"8E1" => DATA <= x"4C"; when x"8E2" => DATA <= x"4F"; when x"8E3" => DATA <= x"41"; when x"8E4" => DATA <= x"44"; when x"8E5" => DATA <= x"F9"; when x"8E6" => DATA <= x"55"; when x"8E7" => DATA <= x"44"; when x"8E8" => DATA <= x"4F"; when x"8E9" => DATA <= x"53"; when x"8EA" => DATA <= x"CC"; when x"8EB" => DATA <= x"EF"; when x"8EC" => DATA <= x"00"; when x"8ED" => DATA <= x"F9"; when x"8EE" => DATA <= x"26"; when x"8EF" => DATA <= x"A2"; when x"8F0" => DATA <= x"FF"; when x"8F1" => DATA <= x"D8"; when x"8F2" => DATA <= x"A0"; when x"8F3" => DATA <= x"00"; when x"8F4" => DATA <= x"84"; when x"8F5" => DATA <= x"DD"; when x"8F6" => DATA <= x"20"; when x"8F7" => DATA <= x"76"; when x"8F8" => DATA <= x"F8"; when x"8F9" => DATA <= x"88"; when x"8FA" => DATA <= x"C8"; when x"8FB" => DATA <= x"E8"; when x"8FC" => DATA <= x"BD"; when x"8FD" => DATA <= x"BE"; when x"8FE" => DATA <= x"F8"; when x"8FF" => DATA <= x"30"; when x"900" => DATA <= x"18"; when x"901" => DATA <= x"D9"; when x"902" => DATA <= x"00"; when x"903" => DATA <= x"01"; when x"904" => DATA <= x"F0"; when x"905" => DATA <= x"F4"; when x"906" => DATA <= x"CA"; when x"907" => DATA <= x"E8"; when x"908" => DATA <= x"BD"; when x"909" => DATA <= x"BE"; when x"90A" => DATA <= x"F8"; when x"90B" => DATA <= x"10"; when x"90C" => DATA <= x"FA"; when x"90D" => DATA <= x"E8"; when x"90E" => DATA <= x"B9"; when x"90F" => DATA <= x"00"; when x"910" => DATA <= x"01"; when x"911" => DATA <= x"C9"; when x"912" => DATA <= x"2E"; when x"913" => DATA <= x"D0"; when x"914" => DATA <= x"DD"; when x"915" => DATA <= x"C8"; when x"916" => DATA <= x"CA"; when x"917" => DATA <= x"B0"; when x"918" => DATA <= x"E3"; when x"919" => DATA <= x"85"; when x"91A" => DATA <= x"CA"; when x"91B" => DATA <= x"BD"; when x"91C" => DATA <= x"BF"; when x"91D" => DATA <= x"F8"; when x"91E" => DATA <= x"85"; when x"91F" => DATA <= x"C9"; when x"920" => DATA <= x"18"; when x"921" => DATA <= x"A2"; when x"922" => DATA <= x"00"; when x"923" => DATA <= x"6C"; when x"924" => DATA <= x"C9"; when x"925" => DATA <= x"00"; when x"926" => DATA <= x"20"; when x"927" => DATA <= x"D1"; when x"928" => DATA <= x"F7"; when x"929" => DATA <= x"43"; when x"92A" => DATA <= x"4F"; when x"92B" => DATA <= x"4D"; when x"92C" => DATA <= x"3F"; when x"92D" => DATA <= x"EA"; when x"92E" => DATA <= x"00"; when x"92F" => DATA <= x"20"; when x"930" => DATA <= x"8E"; when x"931" => DATA <= x"FB"; when x"932" => DATA <= x"50"; when x"933" => DATA <= x"FA"; when x"934" => DATA <= x"F0"; when x"935" => DATA <= x"F9"; when x"936" => DATA <= x"20"; when x"937" => DATA <= x"2B"; when x"938" => DATA <= x"FC"; when x"939" => DATA <= x"A0"; when x"93A" => DATA <= x"00"; when x"93B" => DATA <= x"20"; when x"93C" => DATA <= x"D4"; when x"93D" => DATA <= x"FF"; when x"93E" => DATA <= x"91"; when x"93F" => DATA <= x"CB"; when x"940" => DATA <= x"E6"; when x"941" => DATA <= x"CB"; when x"942" => DATA <= x"D0"; when x"943" => DATA <= x"02"; when x"944" => DATA <= x"E6"; when x"945" => DATA <= x"CC"; when x"946" => DATA <= x"A2"; when x"947" => DATA <= x"D4"; when x"948" => DATA <= x"20"; when x"949" => DATA <= x"08"; when x"94A" => DATA <= x"FA"; when x"94B" => DATA <= x"D0"; when x"94C" => DATA <= x"EE"; when x"94D" => DATA <= x"38"; when x"94E" => DATA <= x"66"; when x"94F" => DATA <= x"DD"; when x"950" => DATA <= x"18"; when x"951" => DATA <= x"66"; when x"952" => DATA <= x"DD"; when x"953" => DATA <= x"28"; when x"954" => DATA <= x"60"; when x"955" => DATA <= x"38"; when x"956" => DATA <= x"66"; when x"957" => DATA <= x"DD"; when x"958" => DATA <= x"20"; when x"959" => DATA <= x"18"; when x"95A" => DATA <= x"F8"; when x"95B" => DATA <= x"A2"; when x"95C" => DATA <= x"CB"; when x"95D" => DATA <= x"20"; when x"95E" => DATA <= x"93"; when x"95F" => DATA <= x"F8"; when x"960" => DATA <= x"F0"; when x"961" => DATA <= x"04"; when x"962" => DATA <= x"A9"; when x"963" => DATA <= x"FF"; when x"964" => DATA <= x"85"; when x"965" => DATA <= x"CD"; when x"966" => DATA <= x"20"; when x"967" => DATA <= x"76"; when x"968" => DATA <= x"FA"; when x"969" => DATA <= x"A2"; when x"96A" => DATA <= x"C9"; when x"96B" => DATA <= x"6C"; when x"96C" => DATA <= x"0C"; when x"96D" => DATA <= x"02"; when x"96E" => DATA <= x"08"; when x"96F" => DATA <= x"78"; when x"970" => DATA <= x"20"; when x"971" => DATA <= x"4F"; when x"972" => DATA <= x"F8"; when x"973" => DATA <= x"08"; when x"974" => DATA <= x"20"; when x"975" => DATA <= x"3E"; when x"976" => DATA <= x"FC"; when x"977" => DATA <= x"28"; when x"978" => DATA <= x"F0"; when x"979" => DATA <= x"B5"; when x"97A" => DATA <= x"A9"; when x"97B" => DATA <= x"00"; when x"97C" => DATA <= x"85"; when x"97D" => DATA <= x"D0"; when x"97E" => DATA <= x"85"; when x"97F" => DATA <= x"D1"; when x"980" => DATA <= x"20"; when x"981" => DATA <= x"A2"; when x"982" => DATA <= x"F9"; when x"983" => DATA <= x"90"; when x"984" => DATA <= x"C9"; when x"985" => DATA <= x"E6"; when x"986" => DATA <= x"D0"; when x"987" => DATA <= x"E6"; when x"988" => DATA <= x"CC"; when x"989" => DATA <= x"D0"; when x"98A" => DATA <= x"F5"; when x"98B" => DATA <= x"18"; when x"98C" => DATA <= x"90"; when x"98D" => DATA <= x"C0"; when x"98E" => DATA <= x"20"; when x"98F" => DATA <= x"F4"; when x"990" => DATA <= x"FF"; when x"991" => DATA <= x"C8"; when x"992" => DATA <= x"B9"; when x"993" => DATA <= x"ED"; when x"994" => DATA <= x"00"; when x"995" => DATA <= x"C9"; when x"996" => DATA <= x"0D"; when x"997" => DATA <= x"D0"; when x"998" => DATA <= x"F5"; when x"999" => DATA <= x"C8"; when x"99A" => DATA <= x"20"; when x"99B" => DATA <= x"FD"; when x"99C" => DATA <= x"F7"; when x"99D" => DATA <= x"C0"; when x"99E" => DATA <= x"0E"; when x"99F" => DATA <= x"90"; when x"9A0" => DATA <= x"F8"; when x"9A1" => DATA <= x"60"; when x"9A2" => DATA <= x"A9"; when x"9A3" => DATA <= x"00"; when x"9A4" => DATA <= x"85"; when x"9A5" => DATA <= x"DC"; when x"9A6" => DATA <= x"20"; when x"9A7" => DATA <= x"8E"; when x"9A8" => DATA <= x"FB"; when x"9A9" => DATA <= x"50"; when x"9AA" => DATA <= x"F8"; when x"9AB" => DATA <= x"D0"; when x"9AC" => DATA <= x"F5"; when x"9AD" => DATA <= x"20"; when x"9AE" => DATA <= x"C9"; when x"9AF" => DATA <= x"FB"; when x"9B0" => DATA <= x"08"; when x"9B1" => DATA <= x"20"; when x"9B2" => DATA <= x"E2"; when x"9B3" => DATA <= x"FB"; when x"9B4" => DATA <= x"28"; when x"9B5" => DATA <= x"F0"; when x"9B6" => DATA <= x"10"; when x"9B7" => DATA <= x"A5"; when x"9B8" => DATA <= x"DB"; when x"9B9" => DATA <= x"29"; when x"9BA" => DATA <= x"20"; when x"9BB" => DATA <= x"05"; when x"9BC" => DATA <= x"EA"; when x"9BD" => DATA <= x"D0"; when x"9BE" => DATA <= x"E3"; when x"9BF" => DATA <= x"20"; when x"9C0" => DATA <= x"92"; when x"9C1" => DATA <= x"F9"; when x"9C2" => DATA <= x"20"; when x"9C3" => DATA <= x"ED"; when x"9C4" => DATA <= x"FF"; when x"9C5" => DATA <= x"D0"; when x"9C6" => DATA <= x"DB"; when x"9C7" => DATA <= x"A2"; when x"9C8" => DATA <= x"02"; when x"9C9" => DATA <= x"A5"; when x"9CA" => DATA <= x"DD"; when x"9CB" => DATA <= x"30"; when x"9CC" => DATA <= x"13"; when x"9CD" => DATA <= x"B5"; when x"9CE" => DATA <= x"CF"; when x"9CF" => DATA <= x"D5"; when x"9D0" => DATA <= x"D8"; when x"9D1" => DATA <= x"B0"; when x"9D2" => DATA <= x"08"; when x"9D3" => DATA <= x"A9"; when x"9D4" => DATA <= x"05"; when x"9D5" => DATA <= x"20"; when x"9D6" => DATA <= x"40"; when x"9D7" => DATA <= x"FC"; when x"9D8" => DATA <= x"20"; when x"9D9" => DATA <= x"3E"; when x"9DA" => DATA <= x"FC"; when x"9DB" => DATA <= x"D0"; when x"9DC" => DATA <= x"C5"; when x"9DD" => DATA <= x"CA"; when x"9DE" => DATA <= x"D0"; when x"9DF" => DATA <= x"ED"; when x"9E0" => DATA <= x"20"; when x"9E1" => DATA <= x"2B"; when x"9E2" => DATA <= x"FC"; when x"9E3" => DATA <= x"24"; when x"9E4" => DATA <= x"DB"; when x"9E5" => DATA <= x"50"; when x"9E6" => DATA <= x"0B"; when x"9E7" => DATA <= x"88"; when x"9E8" => DATA <= x"C8"; when x"9E9" => DATA <= x"20"; when x"9EA" => DATA <= x"D4"; when x"9EB" => DATA <= x"FF"; when x"9EC" => DATA <= x"91"; when x"9ED" => DATA <= x"CB"; when x"9EE" => DATA <= x"C4"; when x"9EF" => DATA <= x"D8"; when x"9F0" => DATA <= x"D0"; when x"9F1" => DATA <= x"F6"; when x"9F2" => DATA <= x"A5"; when x"9F3" => DATA <= x"DC"; when x"9F4" => DATA <= x"85"; when x"9F5" => DATA <= x"CE"; when x"9F6" => DATA <= x"20"; when x"9F7" => DATA <= x"D4"; when x"9F8" => DATA <= x"FF"; when x"9F9" => DATA <= x"C5"; when x"9FA" => DATA <= x"CE"; when x"9FB" => DATA <= x"F0"; when x"9FC" => DATA <= x"08"; when x"9FD" => DATA <= x"20"; when x"9FE" => DATA <= x"D1"; when x"9FF" => DATA <= x"F7"; when x"A00" => DATA <= x"53"; when x"A01" => DATA <= x"55"; when x"A02" => DATA <= x"4D"; when x"A03" => DATA <= x"EA"; when x"A04" => DATA <= x"00"; when x"A05" => DATA <= x"26"; when x"A06" => DATA <= x"DB"; when x"A07" => DATA <= x"60"; when x"A08" => DATA <= x"F6"; when x"A09" => DATA <= x"00"; when x"A0A" => DATA <= x"D0"; when x"A0B" => DATA <= x"02"; when x"A0C" => DATA <= x"F6"; when x"A0D" => DATA <= x"01"; when x"A0E" => DATA <= x"B5"; when x"A0F" => DATA <= x"00"; when x"A10" => DATA <= x"D5"; when x"A11" => DATA <= x"02"; when x"A12" => DATA <= x"D0"; when x"A13" => DATA <= x"04"; when x"A14" => DATA <= x"B5"; when x"A15" => DATA <= x"01"; when x"A16" => DATA <= x"D5"; when x"A17" => DATA <= x"03"; when x"A18" => DATA <= x"60"; when x"A19" => DATA <= x"CA"; when x"A1A" => DATA <= x"20"; when x"A1B" => DATA <= x"76"; when x"A1C" => DATA <= x"FA"; when x"A1D" => DATA <= x"86"; when x"A1E" => DATA <= x"EA"; when x"A1F" => DATA <= x"60"; when x"A20" => DATA <= x"20"; when x"A21" => DATA <= x"58"; when x"A22" => DATA <= x"F9"; when x"A23" => DATA <= x"24"; when x"A24" => DATA <= x"DD"; when x"A25" => DATA <= x"70"; when x"A26" => DATA <= x"4C"; when x"A27" => DATA <= x"6C"; when x"A28" => DATA <= x"D6"; when x"A29" => DATA <= x"00"; when x"A2A" => DATA <= x"08"; when x"A2B" => DATA <= x"20"; when x"A2C" => DATA <= x"76"; when x"A2D" => DATA <= x"FA"; when x"A2E" => DATA <= x"20"; when x"A2F" => DATA <= x"3E"; when x"A30" => DATA <= x"FC"; when x"A31" => DATA <= x"20"; when x"A32" => DATA <= x"8E"; when x"A33" => DATA <= x"FB"; when x"A34" => DATA <= x"70"; when x"A35" => DATA <= x"02"; when x"A36" => DATA <= x"28"; when x"A37" => DATA <= x"60"; when x"A38" => DATA <= x"F0"; when x"A39" => DATA <= x"0A"; when x"A3A" => DATA <= x"A0"; when x"A3B" => DATA <= x"00"; when x"A3C" => DATA <= x"20"; when x"A3D" => DATA <= x"99"; when x"A3E" => DATA <= x"F9"; when x"A3F" => DATA <= x"20"; when x"A40" => DATA <= x"EC"; when x"A41" => DATA <= x"F7"; when x"A42" => DATA <= x"D0"; when x"A43" => DATA <= x"19"; when x"A44" => DATA <= x"20"; when x"A45" => DATA <= x"C9"; when x"A46" => DATA <= x"FB"; when x"A47" => DATA <= x"20"; when x"A48" => DATA <= x"E2"; when x"A49" => DATA <= x"FB"; when x"A4A" => DATA <= x"20"; when x"A4B" => DATA <= x"92"; when x"A4C" => DATA <= x"F9"; when x"A4D" => DATA <= x"20"; when x"A4E" => DATA <= x"EC"; when x"A4F" => DATA <= x"F7"; when x"A50" => DATA <= x"26"; when x"A51" => DATA <= x"DB"; when x"A52" => DATA <= x"10"; when x"A53" => DATA <= x"09"; when x"A54" => DATA <= x"E8"; when x"A55" => DATA <= x"20"; when x"A56" => DATA <= x"F1"; when x"A57" => DATA <= x"F7"; when x"A58" => DATA <= x"B5"; when x"A59" => DATA <= x"FD"; when x"A5A" => DATA <= x"20"; when x"A5B" => DATA <= x"02"; when x"A5C" => DATA <= x"F8"; when x"A5D" => DATA <= x"20"; when x"A5E" => DATA <= x"ED"; when x"A5F" => DATA <= x"FF"; when x"A60" => DATA <= x"D0"; when x"A61" => DATA <= x"CF"; when x"A62" => DATA <= x"4C"; when x"A63" => DATA <= x"ED"; when x"A64" => DATA <= x"FF"; when x"A65" => DATA <= x"20"; when x"A66" => DATA <= x"93"; when x"A67" => DATA <= x"F8"; when x"A68" => DATA <= x"F0"; when x"A69" => DATA <= x"13"; when x"A6A" => DATA <= x"60"; when x"A6B" => DATA <= x"A2"; when x"A6C" => DATA <= x"CB"; when x"A6D" => DATA <= x"20"; when x"A6E" => DATA <= x"65"; when x"A6F" => DATA <= x"FA"; when x"A70" => DATA <= x"20"; when x"A71" => DATA <= x"76"; when x"A72" => DATA <= x"FA"; when x"A73" => DATA <= x"6C"; when x"A74" => DATA <= x"CB"; when x"A75" => DATA <= x"00"; when x"A76" => DATA <= x"20"; when x"A77" => DATA <= x"76"; when x"A78" => DATA <= x"F8"; when x"A79" => DATA <= x"C9"; when x"A7A" => DATA <= x"0D"; when x"A7B" => DATA <= x"F0"; when x"A7C" => DATA <= x"A2"; when x"A7D" => DATA <= x"20"; when x"A7E" => DATA <= x"D1"; when x"A7F" => DATA <= x"F7"; when x"A80" => DATA <= x"53"; when x"A81" => DATA <= x"59"; when x"A82" => DATA <= x"4E"; when x"A83" => DATA <= x"3F"; when x"A84" => DATA <= x"EA"; when x"A85" => DATA <= x"00"; when x"A86" => DATA <= x"38"; when x"A87" => DATA <= x"A5"; when x"A88" => DATA <= x"D1"; when x"A89" => DATA <= x"E5"; when x"A8A" => DATA <= x"CF"; when x"A8B" => DATA <= x"48"; when x"A8C" => DATA <= x"A5"; when x"A8D" => DATA <= x"D2"; when x"A8E" => DATA <= x"E5"; when x"A8F" => DATA <= x"D0"; when x"A90" => DATA <= x"A8"; when x"A91" => DATA <= x"68"; when x"A92" => DATA <= x"18"; when x"A93" => DATA <= x"65"; when x"A94" => DATA <= x"CB"; when x"A95" => DATA <= x"85"; when x"A96" => DATA <= x"CD"; when x"A97" => DATA <= x"98"; when x"A98" => DATA <= x"65"; when x"A99" => DATA <= x"CC"; when x"A9A" => DATA <= x"85"; when x"A9B" => DATA <= x"CE"; when x"A9C" => DATA <= x"A0"; when x"A9D" => DATA <= x"04"; when x"A9E" => DATA <= x"B9"; when x"A9F" => DATA <= x"CA"; when x"AA0" => DATA <= x"00"; when x"AA1" => DATA <= x"20"; when x"AA2" => DATA <= x"D1"; when x"AA3" => DATA <= x"FF"; when x"AA4" => DATA <= x"88"; when x"AA5" => DATA <= x"D0"; when x"AA6" => DATA <= x"F7"; when x"AA7" => DATA <= x"B1"; when x"AA8" => DATA <= x"CF"; when x"AA9" => DATA <= x"20"; when x"AAA" => DATA <= x"D1"; when x"AAB" => DATA <= x"FF"; when x"AAC" => DATA <= x"E6"; when x"AAD" => DATA <= x"CF"; when x"AAE" => DATA <= x"D0"; when x"AAF" => DATA <= x"02"; when x"AB0" => DATA <= x"E6"; when x"AB1" => DATA <= x"D0"; when x"AB2" => DATA <= x"A2"; when x"AB3" => DATA <= x"CB"; when x"AB4" => DATA <= x"20"; when x"AB5" => DATA <= x"08"; when x"AB6" => DATA <= x"FA"; when x"AB7" => DATA <= x"D0"; when x"AB8" => DATA <= x"EE"; when x"AB9" => DATA <= x"28"; when x"ABA" => DATA <= x"60"; when x"ABB" => DATA <= x"20"; when x"ABC" => DATA <= x"18"; when x"ABD" => DATA <= x"F8"; when x"ABE" => DATA <= x"A2"; when x"ABF" => DATA <= x"CB"; when x"AC0" => DATA <= x"20"; when x"AC1" => DATA <= x"65"; when x"AC2" => DATA <= x"FA"; when x"AC3" => DATA <= x"A2"; when x"AC4" => DATA <= x"D1"; when x"AC5" => DATA <= x"20"; when x"AC6" => DATA <= x"65"; when x"AC7" => DATA <= x"FA"; when x"AC8" => DATA <= x"A2"; when x"AC9" => DATA <= x"CD"; when x"ACA" => DATA <= x"20"; when x"ACB" => DATA <= x"93"; when x"ACC" => DATA <= x"F8"; when x"ACD" => DATA <= x"08"; when x"ACE" => DATA <= x"A5"; when x"ACF" => DATA <= x"CB"; when x"AD0" => DATA <= x"A6"; when x"AD1" => DATA <= x"CC"; when x"AD2" => DATA <= x"28"; when x"AD3" => DATA <= x"D0"; when x"AD4" => DATA <= x"04"; when x"AD5" => DATA <= x"85"; when x"AD6" => DATA <= x"CD"; when x"AD7" => DATA <= x"86"; when x"AD8" => DATA <= x"CE"; when x"AD9" => DATA <= x"85"; when x"ADA" => DATA <= x"CF"; when x"ADB" => DATA <= x"86"; when x"ADC" => DATA <= x"D0"; when x"ADD" => DATA <= x"20"; when x"ADE" => DATA <= x"76"; when x"ADF" => DATA <= x"FA"; when x"AE0" => DATA <= x"A2"; when x"AE1" => DATA <= x"C9"; when x"AE2" => DATA <= x"6C"; when x"AE3" => DATA <= x"0E"; when x"AE4" => DATA <= x"02"; when x"AE5" => DATA <= x"08"; when x"AE6" => DATA <= x"78"; when x"AE7" => DATA <= x"20"; when x"AE8" => DATA <= x"4F"; when x"AE9" => DATA <= x"F8"; when x"AEA" => DATA <= x"08"; when x"AEB" => DATA <= x"A9"; when x"AEC" => DATA <= x"06"; when x"AED" => DATA <= x"20"; when x"AEE" => DATA <= x"40"; when x"AEF" => DATA <= x"FC"; when x"AF0" => DATA <= x"A2"; when x"AF1" => DATA <= x"07"; when x"AF2" => DATA <= x"20"; when x"AF3" => DATA <= x"7A"; when x"AF4" => DATA <= x"FB"; when x"AF5" => DATA <= x"28"; when x"AF6" => DATA <= x"F0"; when x"AF7" => DATA <= x"8E"; when x"AF8" => DATA <= x"A2"; when x"AF9" => DATA <= x"04"; when x"AFA" => DATA <= x"B5"; when x"AFB" => DATA <= x"CE"; when x"AFC" => DATA <= x"95"; when x"AFD" => DATA <= x"D2"; when x"AFE" => DATA <= x"CA"; when x"AFF" => DATA <= x"D0"; when x"B00" => DATA <= x"F9"; when x"B01" => DATA <= x"86"; when x"B02" => DATA <= x"D0"; when x"B03" => DATA <= x"86"; when x"B04" => DATA <= x"D1"; when x"B05" => DATA <= x"A5"; when x"B06" => DATA <= x"D5"; when x"B07" => DATA <= x"D0"; when x"B08" => DATA <= x"02"; when x"B09" => DATA <= x"C6"; when x"B0A" => DATA <= x"D6"; when x"B0B" => DATA <= x"C6"; when x"B0C" => DATA <= x"D5"; when x"B0D" => DATA <= x"18"; when x"B0E" => DATA <= x"66"; when x"B0F" => DATA <= x"D2"; when x"B10" => DATA <= x"38"; when x"B11" => DATA <= x"A2"; when x"B12" => DATA <= x"FF"; when x"B13" => DATA <= x"A5"; when x"B14" => DATA <= x"D5"; when x"B15" => DATA <= x"E5"; when x"B16" => DATA <= x"D3"; when x"B17" => DATA <= x"85"; when x"B18" => DATA <= x"CF"; when x"B19" => DATA <= x"A5"; when x"B1A" => DATA <= x"D6"; when x"B1B" => DATA <= x"E5"; when x"B1C" => DATA <= x"D4"; when x"B1D" => DATA <= x"08"; when x"B1E" => DATA <= x"66"; when x"B1F" => DATA <= x"D2"; when x"B20" => DATA <= x"28"; when x"B21" => DATA <= x"90"; when x"B22" => DATA <= x"06"; when x"B23" => DATA <= x"18"; when x"B24" => DATA <= x"F0"; when x"B25" => DATA <= x"03"; when x"B26" => DATA <= x"86"; when x"B27" => DATA <= x"CF"; when x"B28" => DATA <= x"38"; when x"B29" => DATA <= x"66"; when x"B2A" => DATA <= x"D2"; when x"B2B" => DATA <= x"E8"; when x"B2C" => DATA <= x"20"; when x"B2D" => DATA <= x"3B"; when x"B2E" => DATA <= x"FB"; when x"B2F" => DATA <= x"E6"; when x"B30" => DATA <= x"D0"; when x"B31" => DATA <= x"E6"; when x"B32" => DATA <= x"D4"; when x"B33" => DATA <= x"E6"; when x"B34" => DATA <= x"CC"; when x"B35" => DATA <= x"26"; when x"B36" => DATA <= x"D2"; when x"B37" => DATA <= x"B0"; when x"B38" => DATA <= x"D5"; when x"B39" => DATA <= x"28"; when x"B3A" => DATA <= x"60"; when x"B3B" => DATA <= x"A2"; when x"B3C" => DATA <= x"07"; when x"B3D" => DATA <= x"20"; when x"B3E" => DATA <= x"7A"; when x"B3F" => DATA <= x"FB"; when x"B40" => DATA <= x"86"; when x"B41" => DATA <= x"DC"; when x"B42" => DATA <= x"A0"; when x"B43" => DATA <= x"04"; when x"B44" => DATA <= x"A9"; when x"B45" => DATA <= x"2A"; when x"B46" => DATA <= x"20"; when x"B47" => DATA <= x"D1"; when x"B48" => DATA <= x"FF"; when x"B49" => DATA <= x"88"; when x"B4A" => DATA <= x"D0"; when x"B4B" => DATA <= x"F8"; when x"B4C" => DATA <= x"B1"; when x"B4D" => DATA <= x"C9"; when x"B4E" => DATA <= x"20"; when x"B4F" => DATA <= x"D1"; when x"B50" => DATA <= x"FF"; when x"B51" => DATA <= x"C8"; when x"B52" => DATA <= x"C9"; when x"B53" => DATA <= x"0D"; when x"B54" => DATA <= x"D0"; when x"B55" => DATA <= x"F6"; when x"B56" => DATA <= x"A0"; when x"B57" => DATA <= x"08"; when x"B58" => DATA <= x"B9"; when x"B59" => DATA <= x"CA"; when x"B5A" => DATA <= x"00"; when x"B5B" => DATA <= x"20"; when x"B5C" => DATA <= x"D1"; when x"B5D" => DATA <= x"FF"; when x"B5E" => DATA <= x"88"; when x"B5F" => DATA <= x"D0"; when x"B60" => DATA <= x"F7"; when x"B61" => DATA <= x"20"; when x"B62" => DATA <= x"81"; when x"B63" => DATA <= x"FB"; when x"B64" => DATA <= x"24"; when x"B65" => DATA <= x"D2"; when x"B66" => DATA <= x"50"; when x"B67" => DATA <= x"0B"; when x"B68" => DATA <= x"88"; when x"B69" => DATA <= x"C8"; when x"B6A" => DATA <= x"B1"; when x"B6B" => DATA <= x"D3"; when x"B6C" => DATA <= x"20"; when x"B6D" => DATA <= x"D1"; when x"B6E" => DATA <= x"FF"; when x"B6F" => DATA <= x"C4"; when x"B70" => DATA <= x"CF"; when x"B71" => DATA <= x"D0"; when x"B72" => DATA <= x"F6"; when x"B73" => DATA <= x"A5"; when x"B74" => DATA <= x"DC"; when x"B75" => DATA <= x"20"; when x"B76" => DATA <= x"D1"; when x"B77" => DATA <= x"FF"; when x"B78" => DATA <= x"A2"; when x"B79" => DATA <= x"04"; when x"B7A" => DATA <= x"8E"; when x"B7B" => DATA <= x"02"; when x"B7C" => DATA <= x"B0"; when x"B7D" => DATA <= x"A2"; when x"B7E" => DATA <= x"78"; when x"B7F" => DATA <= x"D0"; when x"B80" => DATA <= x"02"; when x"B81" => DATA <= x"A2"; when x"B82" => DATA <= x"1E"; when x"B83" => DATA <= x"20"; when x"B84" => DATA <= x"66"; when x"B85" => DATA <= x"FE"; when x"B86" => DATA <= x"CA"; when x"B87" => DATA <= x"D0"; when x"B88" => DATA <= x"FA"; when x"B89" => DATA <= x"60"; when x"B8A" => DATA <= x"A2"; when x"B8B" => DATA <= x"06"; when x"B8C" => DATA <= x"D0"; when x"B8D" => DATA <= x"F5"; when x"B8E" => DATA <= x"2C"; when x"B8F" => DATA <= x"01"; when x"B90" => DATA <= x"B0"; when x"B91" => DATA <= x"10"; when x"B92" => DATA <= x"FB"; when x"B93" => DATA <= x"50"; when x"B94" => DATA <= x"F9"; when x"B95" => DATA <= x"A0"; when x"B96" => DATA <= x"00"; when x"B97" => DATA <= x"85"; when x"B98" => DATA <= x"C3"; when x"B99" => DATA <= x"A9"; when x"B9A" => DATA <= x"10"; when x"B9B" => DATA <= x"85"; when x"B9C" => DATA <= x"C2"; when x"B9D" => DATA <= x"2C"; when x"B9E" => DATA <= x"01"; when x"B9F" => DATA <= x"B0"; when x"BA0" => DATA <= x"10"; when x"BA1" => DATA <= x"0F"; when x"BA2" => DATA <= x"50"; when x"BA3" => DATA <= x"0D"; when x"BA4" => DATA <= x"20"; when x"BA5" => DATA <= x"BD"; when x"BA6" => DATA <= x"FC"; when x"BA7" => DATA <= x"B0"; when x"BA8" => DATA <= x"EC"; when x"BA9" => DATA <= x"C6"; when x"BAA" => DATA <= x"C3"; when x"BAB" => DATA <= x"D0"; when x"BAC" => DATA <= x"F0"; when x"BAD" => DATA <= x"C6"; when x"BAE" => DATA <= x"C2"; when x"BAF" => DATA <= x"D0"; when x"BB0" => DATA <= x"EC"; when x"BB1" => DATA <= x"70"; when x"BB2" => DATA <= x"01"; when x"BB3" => DATA <= x"60"; when x"BB4" => DATA <= x"A0"; when x"BB5" => DATA <= x"04"; when x"BB6" => DATA <= x"08"; when x"BB7" => DATA <= x"20"; when x"BB8" => DATA <= x"E4"; when x"BB9" => DATA <= x"FB"; when x"BBA" => DATA <= x"28"; when x"BBB" => DATA <= x"A0"; when x"BBC" => DATA <= x"04"; when x"BBD" => DATA <= x"A9"; when x"BBE" => DATA <= x"2A"; when x"BBF" => DATA <= x"D9"; when x"BC0" => DATA <= x"D3"; when x"BC1" => DATA <= x"00"; when x"BC2" => DATA <= x"D0"; when x"BC3" => DATA <= x"03"; when x"BC4" => DATA <= x"88"; when x"BC5" => DATA <= x"D0"; when x"BC6" => DATA <= x"F8"; when x"BC7" => DATA <= x"60"; when x"BC8" => DATA <= x"C8"; when x"BC9" => DATA <= x"20"; when x"BCA" => DATA <= x"D4"; when x"BCB" => DATA <= x"FF"; when x"BCC" => DATA <= x"99"; when x"BCD" => DATA <= x"ED"; when x"BCE" => DATA <= x"00"; when x"BCF" => DATA <= x"C9"; when x"BD0" => DATA <= x"0D"; when x"BD1" => DATA <= x"D0"; when x"BD2" => DATA <= x"F5"; when x"BD3" => DATA <= x"A0"; when x"BD4" => DATA <= x"FF"; when x"BD5" => DATA <= x"C8"; when x"BD6" => DATA <= x"B1"; when x"BD7" => DATA <= x"C9"; when x"BD8" => DATA <= x"D9"; when x"BD9" => DATA <= x"ED"; when x"BDA" => DATA <= x"00"; when x"BDB" => DATA <= x"D0"; when x"BDC" => DATA <= x"EA"; when x"BDD" => DATA <= x"C9"; when x"BDE" => DATA <= x"0D"; when x"BDF" => DATA <= x"D0"; when x"BE0" => DATA <= x"F4"; when x"BE1" => DATA <= x"60"; when x"BE2" => DATA <= x"A0"; when x"BE3" => DATA <= x"08"; when x"BE4" => DATA <= x"20"; when x"BE5" => DATA <= x"D4"; when x"BE6" => DATA <= x"FF"; when x"BE7" => DATA <= x"99"; when x"BE8" => DATA <= x"D3"; when x"BE9" => DATA <= x"00"; when x"BEA" => DATA <= x"88"; when x"BEB" => DATA <= x"D0"; when x"BEC" => DATA <= x"F7"; when x"BED" => DATA <= x"60"; when x"BEE" => DATA <= x"86"; when x"BEF" => DATA <= x"EC"; when x"BF0" => DATA <= x"84"; when x"BF1" => DATA <= x"C3"; when x"BF2" => DATA <= x"08"; when x"BF3" => DATA <= x"78"; when x"BF4" => DATA <= x"A9"; when x"BF5" => DATA <= x"78"; when x"BF6" => DATA <= x"85"; when x"BF7" => DATA <= x"C0"; when x"BF8" => DATA <= x"20"; when x"BF9" => DATA <= x"BD"; when x"BFA" => DATA <= x"FC"; when x"BFB" => DATA <= x"90"; when x"BFC" => DATA <= x"F7"; when x"BFD" => DATA <= x"E6"; when x"BFE" => DATA <= x"C0"; when x"BFF" => DATA <= x"10"; when x"C00" => DATA <= x"F7"; when x"C01" => DATA <= x"A9"; when x"C02" => DATA <= x"53"; when x"C03" => DATA <= x"85"; when x"C04" => DATA <= x"C4"; when x"C05" => DATA <= x"A2"; when x"C06" => DATA <= x"00"; when x"C07" => DATA <= x"AC"; when x"C08" => DATA <= x"02"; when x"C09" => DATA <= x"B0"; when x"C0A" => DATA <= x"20"; when x"C0B" => DATA <= x"CD"; when x"C0C" => DATA <= x"FC"; when x"C0D" => DATA <= x"F0"; when x"C0E" => DATA <= x"00"; when x"C0F" => DATA <= x"F0"; when x"C10" => DATA <= x"01"; when x"C11" => DATA <= x"E8"; when x"C12" => DATA <= x"C6"; when x"C13" => DATA <= x"C4"; when x"C14" => DATA <= x"D0"; when x"C15" => DATA <= x"F4"; when x"C16" => DATA <= x"E0"; when x"C17" => DATA <= x"0C"; when x"C18" => DATA <= x"66"; when x"C19" => DATA <= x"C0"; when x"C1A" => DATA <= x"90"; when x"C1B" => DATA <= x"E5"; when x"C1C" => DATA <= x"A5"; when x"C1D" => DATA <= x"C0"; when x"C1E" => DATA <= x"28"; when x"C1F" => DATA <= x"A4"; when x"C20" => DATA <= x"C3"; when x"C21" => DATA <= x"A6"; when x"C22" => DATA <= x"EC"; when x"C23" => DATA <= x"48"; when x"C24" => DATA <= x"18"; when x"C25" => DATA <= x"65"; when x"C26" => DATA <= x"DC"; when x"C27" => DATA <= x"85"; when x"C28" => DATA <= x"DC"; when x"C29" => DATA <= x"68"; when x"C2A" => DATA <= x"60"; when x"C2B" => DATA <= x"A5"; when x"C2C" => DATA <= x"CD"; when x"C2D" => DATA <= x"30"; when x"C2E" => DATA <= x"08"; when x"C2F" => DATA <= x"A5"; when x"C30" => DATA <= x"D4"; when x"C31" => DATA <= x"85"; when x"C32" => DATA <= x"CB"; when x"C33" => DATA <= x"A5"; when x"C34" => DATA <= x"D5"; when x"C35" => DATA <= x"85"; when x"C36" => DATA <= x"CC"; when x"C37" => DATA <= x"60"; when x"C38" => DATA <= x"B0"; when x"C39" => DATA <= x"04"; when x"C3A" => DATA <= x"A9"; when x"C3B" => DATA <= x"06"; when x"C3C" => DATA <= x"D0"; when x"C3D" => DATA <= x"02"; when x"C3E" => DATA <= x"A9"; when x"C3F" => DATA <= x"04"; when x"C40" => DATA <= x"A2"; when x"C41" => DATA <= x"07"; when x"C42" => DATA <= x"8E"; when x"C43" => DATA <= x"02"; when x"C44" => DATA <= x"B0"; when x"C45" => DATA <= x"24"; when x"C46" => DATA <= x"EA"; when x"C47" => DATA <= x"D0"; when x"C48" => DATA <= x"2D"; when x"C49" => DATA <= x"C9"; when x"C4A" => DATA <= x"05"; when x"C4B" => DATA <= x"F0"; when x"C4C" => DATA <= x"16"; when x"C4D" => DATA <= x"B0"; when x"C4E" => DATA <= x"09"; when x"C4F" => DATA <= x"20"; when x"C50" => DATA <= x"D1"; when x"C51" => DATA <= x"F7"; when x"C52" => DATA <= x"50"; when x"C53" => DATA <= x"4C"; when x"C54" => DATA <= x"41"; when x"C55" => DATA <= x"59"; when x"C56" => DATA <= x"D0"; when x"C57" => DATA <= x"15"; when x"C58" => DATA <= x"20"; when x"C59" => DATA <= x"D1"; when x"C5A" => DATA <= x"F7"; when x"C5B" => DATA <= x"52"; when x"C5C" => DATA <= x"45"; when x"C5D" => DATA <= x"43"; when x"C5E" => DATA <= x"4F"; when x"C5F" => DATA <= x"52"; when x"C60" => DATA <= x"44"; when x"C61" => DATA <= x"D0"; when x"C62" => DATA <= x"0A"; when x"C63" => DATA <= x"20"; when x"C64" => DATA <= x"D1"; when x"C65" => DATA <= x"F7"; when x"C66" => DATA <= x"52"; when x"C67" => DATA <= x"45"; when x"C68" => DATA <= x"57"; when x"C69" => DATA <= x"49"; when x"C6A" => DATA <= x"4E"; when x"C6B" => DATA <= x"44"; when x"C6C" => DATA <= x"EA"; when x"C6D" => DATA <= x"20"; when x"C6E" => DATA <= x"D1"; when x"C6F" => DATA <= x"F7"; when x"C70" => DATA <= x"20"; when x"C71" => DATA <= x"54"; when x"C72" => DATA <= x"41"; when x"C73" => DATA <= x"50"; when x"C74" => DATA <= x"45"; when x"C75" => DATA <= x"EA"; when x"C76" => DATA <= x"20"; when x"C77" => DATA <= x"E3"; when x"C78" => DATA <= x"FF"; when x"C79" => DATA <= x"4C"; when x"C7A" => DATA <= x"ED"; when x"C7B" => DATA <= x"FF"; when x"C7C" => DATA <= x"86"; when x"C7D" => DATA <= x"EC"; when x"C7E" => DATA <= x"84"; when x"C7F" => DATA <= x"C3"; when x"C80" => DATA <= x"08"; when x"C81" => DATA <= x"78"; when x"C82" => DATA <= x"48"; when x"C83" => DATA <= x"20"; when x"C84" => DATA <= x"23"; when x"C85" => DATA <= x"FC"; when x"C86" => DATA <= x"85"; when x"C87" => DATA <= x"C0"; when x"C88" => DATA <= x"20"; when x"C89" => DATA <= x"D8"; when x"C8A" => DATA <= x"FC"; when x"C8B" => DATA <= x"A9"; when x"C8C" => DATA <= x"0A"; when x"C8D" => DATA <= x"85"; when x"C8E" => DATA <= x"C1"; when x"C8F" => DATA <= x"18"; when x"C90" => DATA <= x"90"; when x"C91" => DATA <= x"0A"; when x"C92" => DATA <= x"A2"; when x"C93" => DATA <= x"07"; when x"C94" => DATA <= x"8E"; when x"C95" => DATA <= x"02"; when x"C96" => DATA <= x"B0"; when x"C97" => DATA <= x"20"; when x"C98" => DATA <= x"DA"; when x"C99" => DATA <= x"FC"; when x"C9A" => DATA <= x"30"; when x"C9B" => DATA <= x"13"; when x"C9C" => DATA <= x"A0"; when x"C9D" => DATA <= x"04"; when x"C9E" => DATA <= x"A9"; when x"C9F" => DATA <= x"04"; when x"CA0" => DATA <= x"8D"; when x"CA1" => DATA <= x"02"; when x"CA2" => DATA <= x"B0"; when x"CA3" => DATA <= x"20"; when x"CA4" => DATA <= x"D8"; when x"CA5" => DATA <= x"FC"; when x"CA6" => DATA <= x"EE"; when x"CA7" => DATA <= x"02"; when x"CA8" => DATA <= x"B0"; when x"CA9" => DATA <= x"20"; when x"CAA" => DATA <= x"D8"; when x"CAB" => DATA <= x"FC"; when x"CAC" => DATA <= x"88"; when x"CAD" => DATA <= x"D0"; when x"CAE" => DATA <= x"EF"; when x"CAF" => DATA <= x"38"; when x"CB0" => DATA <= x"66"; when x"CB1" => DATA <= x"C0"; when x"CB2" => DATA <= x"C6"; when x"CB3" => DATA <= x"C1"; when x"CB4" => DATA <= x"D0"; when x"CB5" => DATA <= x"DA"; when x"CB6" => DATA <= x"A4"; when x"CB7" => DATA <= x"C3"; when x"CB8" => DATA <= x"A6"; when x"CB9" => DATA <= x"EC"; when x"CBA" => DATA <= x"68"; when x"CBB" => DATA <= x"28"; when x"CBC" => DATA <= x"60"; when x"CBD" => DATA <= x"A2"; when x"CBE" => DATA <= x"00"; when x"CBF" => DATA <= x"AC"; when x"CC0" => DATA <= x"02"; when x"CC1" => DATA <= x"B0"; when x"CC2" => DATA <= x"E8"; when x"CC3" => DATA <= x"F0"; when x"CC4" => DATA <= x"07"; when x"CC5" => DATA <= x"20"; when x"CC6" => DATA <= x"CD"; when x"CC7" => DATA <= x"FC"; when x"CC8" => DATA <= x"F0"; when x"CC9" => DATA <= x"F8"; when x"CCA" => DATA <= x"E0"; when x"CCB" => DATA <= x"08"; when x"CCC" => DATA <= x"60"; when x"CCD" => DATA <= x"84"; when x"CCE" => DATA <= x"C5"; when x"CCF" => DATA <= x"AD"; when x"CD0" => DATA <= x"02"; when x"CD1" => DATA <= x"B0"; when x"CD2" => DATA <= x"A8"; when x"CD3" => DATA <= x"45"; when x"CD4" => DATA <= x"C5"; when x"CD5" => DATA <= x"29"; when x"CD6" => DATA <= x"20"; when x"CD7" => DATA <= x"60"; when x"CD8" => DATA <= x"A2"; when x"CD9" => DATA <= x"00"; when x"CDA" => DATA <= x"A9"; when x"CDB" => DATA <= x"10"; when x"CDC" => DATA <= x"2C"; when x"CDD" => DATA <= x"02"; when x"CDE" => DATA <= x"B0"; when x"CDF" => DATA <= x"F0"; when x"CE0" => DATA <= x"FB"; when x"CE1" => DATA <= x"2C"; when x"CE2" => DATA <= x"02"; when x"CE3" => DATA <= x"B0"; when x"CE4" => DATA <= x"D0"; when x"CE5" => DATA <= x"FB"; when x"CE6" => DATA <= x"CA"; when x"CE7" => DATA <= x"10"; when x"CE8" => DATA <= x"F3"; when x"CE9" => DATA <= x"60"; when x"CEA" => DATA <= x"C9"; when x"CEB" => DATA <= x"06"; when x"CEC" => DATA <= x"F0"; when x"CED" => DATA <= x"1D"; when x"CEE" => DATA <= x"C9"; when x"CEF" => DATA <= x"15"; when x"CF0" => DATA <= x"F0"; when x"CF1" => DATA <= x"1F"; when x"CF2" => DATA <= x"A4"; when x"CF3" => DATA <= x"E0"; when x"CF4" => DATA <= x"30"; when x"CF5" => DATA <= x"23"; when x"CF6" => DATA <= x"C9"; when x"CF7" => DATA <= x"1B"; when x"CF8" => DATA <= x"F0"; when x"CF9" => DATA <= x"11"; when x"CFA" => DATA <= x"C9"; when x"CFB" => DATA <= x"07"; when x"CFC" => DATA <= x"F0"; when x"CFD" => DATA <= x"1C"; when x"CFE" => DATA <= x"20"; when x"CFF" => DATA <= x"44"; when x"D00" => DATA <= x"FD"; when x"D01" => DATA <= x"A2"; when x"D02" => DATA <= x"0A"; when x"D03" => DATA <= x"20"; when x"D04" => DATA <= x"C5"; when x"D05" => DATA <= x"FE"; when x"D06" => DATA <= x"D0"; when x"D07" => DATA <= x"21"; when x"D08" => DATA <= x"4C"; when x"D09" => DATA <= x"B7"; when x"D0A" => DATA <= x"FE"; when x"D0B" => DATA <= x"18"; when x"D0C" => DATA <= x"A2"; when x"D0D" => DATA <= x"00"; when x"D0E" => DATA <= x"8E"; when x"D0F" => DATA <= x"00"; when x"D10" => DATA <= x"B0"; when x"D11" => DATA <= x"A2"; when x"D12" => DATA <= x"02"; when x"D13" => DATA <= x"08"; when x"D14" => DATA <= x"16"; when x"D15" => DATA <= x"DE"; when x"D16" => DATA <= x"28"; when x"D17" => DATA <= x"76"; when x"D18" => DATA <= x"DE"; when x"D19" => DATA <= x"60"; when x"D1A" => DATA <= x"A9"; when x"D1B" => DATA <= x"05"; when x"D1C" => DATA <= x"A8"; when x"D1D" => DATA <= x"8D"; when x"D1E" => DATA <= x"03"; when x"D1F" => DATA <= x"B0"; when x"D20" => DATA <= x"CA"; when x"D21" => DATA <= x"D0"; when x"D22" => DATA <= x"FD"; when x"D23" => DATA <= x"49"; when x"D24" => DATA <= x"01"; when x"D25" => DATA <= x"C8"; when x"D26" => DATA <= x"10"; when x"D27" => DATA <= x"F5"; when x"D28" => DATA <= x"60"; when x"D29" => DATA <= x"C9"; when x"D2A" => DATA <= x"20"; when x"D2B" => DATA <= x"90"; when x"D2C" => DATA <= x"17"; when x"D2D" => DATA <= x"69"; when x"D2E" => DATA <= x"1F"; when x"D2F" => DATA <= x"30"; when x"D30" => DATA <= x"02"; when x"D31" => DATA <= x"49"; when x"D32" => DATA <= x"60"; when x"D33" => DATA <= x"20"; when x"D34" => DATA <= x"6B"; when x"D35" => DATA <= x"FE"; when x"D36" => DATA <= x"91"; when x"D37" => DATA <= x"DE"; when x"D38" => DATA <= x"C8"; when x"D39" => DATA <= x"C0"; when x"D3A" => DATA <= x"20"; when x"D3B" => DATA <= x"90"; when x"D3C" => DATA <= x"05"; when x"D3D" => DATA <= x"20"; when x"D3E" => DATA <= x"EC"; when x"D3F" => DATA <= x"FD"; when x"D40" => DATA <= x"A0"; when x"D41" => DATA <= x"00"; when x"D42" => DATA <= x"84"; when x"D43" => DATA <= x"E0"; when x"D44" => DATA <= x"48"; when x"D45" => DATA <= x"20"; when x"D46" => DATA <= x"6B"; when x"D47" => DATA <= x"FE"; when x"D48" => DATA <= x"B1"; when x"D49" => DATA <= x"DE"; when x"D4A" => DATA <= x"45"; when x"D4B" => DATA <= x"E1"; when x"D4C" => DATA <= x"91"; when x"D4D" => DATA <= x"DE"; when x"D4E" => DATA <= x"68"; when x"D4F" => DATA <= x"60"; when x"D50" => DATA <= x"20"; when x"D51" => DATA <= x"35"; when x"D52" => DATA <= x"FE"; when x"D53" => DATA <= x"A9"; when x"D54" => DATA <= x"20"; when x"D55" => DATA <= x"20"; when x"D56" => DATA <= x"6B"; when x"D57" => DATA <= x"FE"; when x"D58" => DATA <= x"91"; when x"D59" => DATA <= x"DE"; when x"D5A" => DATA <= x"10"; when x"D5B" => DATA <= x"E6"; when x"D5C" => DATA <= x"20"; when x"D5D" => DATA <= x"35"; when x"D5E" => DATA <= x"FE"; when x"D5F" => DATA <= x"4C"; when x"D60" => DATA <= x"42"; when x"D61" => DATA <= x"FD"; when x"D62" => DATA <= x"20"; when x"D63" => DATA <= x"EC"; when x"D64" => DATA <= x"FD"; when x"D65" => DATA <= x"A4"; when x"D66" => DATA <= x"E0"; when x"D67" => DATA <= x"10"; when x"D68" => DATA <= x"D9"; when x"D69" => DATA <= x"A0"; when x"D6A" => DATA <= x"80"; when x"D6B" => DATA <= x"84"; when x"D6C" => DATA <= x"E1"; when x"D6D" => DATA <= x"A0"; when x"D6E" => DATA <= x"00"; when x"D6F" => DATA <= x"8C"; when x"D70" => DATA <= x"00"; when x"D71" => DATA <= x"B0"; when x"D72" => DATA <= x"A9"; when x"D73" => DATA <= x"20"; when x"D74" => DATA <= x"99"; when x"D75" => DATA <= x"00"; when x"D76" => DATA <= x"80"; when x"D77" => DATA <= x"99"; when x"D78" => DATA <= x"00"; when x"D79" => DATA <= x"81"; when x"D7A" => DATA <= x"C8"; when x"D7B" => DATA <= x"D0"; when x"D7C" => DATA <= x"F7"; when x"D7D" => DATA <= x"A9"; when x"D7E" => DATA <= x"80"; when x"D7F" => DATA <= x"A0"; when x"D80" => DATA <= x"00"; when x"D81" => DATA <= x"85"; when x"D82" => DATA <= x"DF"; when x"D83" => DATA <= x"84"; when x"D84" => DATA <= x"DE"; when x"D85" => DATA <= x"F0"; when x"D86" => DATA <= x"BB"; when x"D87" => DATA <= x"20"; when x"D88" => DATA <= x"3A"; when x"D89" => DATA <= x"FE"; when x"D8A" => DATA <= x"4C"; when x"D8B" => DATA <= x"42"; when x"D8C" => DATA <= x"FD"; when x"D8D" => DATA <= x"18"; when x"D8E" => DATA <= x"A9"; when x"D8F" => DATA <= x"10"; when x"D90" => DATA <= x"85"; when x"D91" => DATA <= x"E6"; when x"D92" => DATA <= x"A2"; when x"D93" => DATA <= x"08"; when x"D94" => DATA <= x"20"; when x"D95" => DATA <= x"13"; when x"D96" => DATA <= x"FD"; when x"D97" => DATA <= x"4C"; when x"D98" => DATA <= x"44"; when x"D99" => DATA <= x"FD"; when x"D9A" => DATA <= x"A5"; when x"D9B" => DATA <= x"E7"; when x"D9C" => DATA <= x"49"; when x"D9D" => DATA <= x"60"; when x"D9E" => DATA <= x"85"; when x"D9F" => DATA <= x"E7"; when x"DA0" => DATA <= x"B0"; when x"DA1" => DATA <= x"09"; when x"DA2" => DATA <= x"29"; when x"DA3" => DATA <= x"05"; when x"DA4" => DATA <= x"2E"; when x"DA5" => DATA <= x"01"; when x"DA6" => DATA <= x"B0"; when x"DA7" => DATA <= x"2A"; when x"DA8" => DATA <= x"20"; when x"DA9" => DATA <= x"EA"; when x"DAA" => DATA <= x"FC"; when x"DAB" => DATA <= x"4C"; when x"DAC" => DATA <= x"9A"; when x"DAD" => DATA <= x"FE"; when x"DAE" => DATA <= x"A4"; when x"DAF" => DATA <= x"E0"; when x"DB0" => DATA <= x"20"; when x"DB1" => DATA <= x"6B"; when x"DB2" => DATA <= x"FE"; when x"DB3" => DATA <= x"B1"; when x"DB4" => DATA <= x"DE"; when x"DB5" => DATA <= x"45"; when x"DB6" => DATA <= x"E1"; when x"DB7" => DATA <= x"30"; when x"DB8" => DATA <= x"02"; when x"DB9" => DATA <= x"49"; when x"DBA" => DATA <= x"60"; when x"DBB" => DATA <= x"E9"; when x"DBC" => DATA <= x"20"; when x"DBD" => DATA <= x"4C"; when x"DBE" => DATA <= x"E9"; when x"DBF" => DATA <= x"FD"; when x"DC0" => DATA <= x"A9"; when x"DC1" => DATA <= x"5F"; when x"DC2" => DATA <= x"49"; when x"DC3" => DATA <= x"20"; when x"DC4" => DATA <= x"D0"; when x"DC5" => DATA <= x"23"; when x"DC6" => DATA <= x"45"; when x"DC7" => DATA <= x"E7"; when x"DC8" => DATA <= x"2C"; when x"DC9" => DATA <= x"01"; when x"DCA" => DATA <= x"B0"; when x"DCB" => DATA <= x"30"; when x"DCC" => DATA <= x"02"; when x"DCD" => DATA <= x"49"; when x"DCE" => DATA <= x"60"; when x"DCF" => DATA <= x"4C"; when x"DD0" => DATA <= x"DF"; when x"DD1" => DATA <= x"FD"; when x"DD2" => DATA <= x"69"; when x"DD3" => DATA <= x"39"; when x"DD4" => DATA <= x"90"; when x"DD5" => DATA <= x"F2"; when x"DD6" => DATA <= x"49"; when x"DD7" => DATA <= x"10"; when x"DD8" => DATA <= x"2C"; when x"DD9" => DATA <= x"01"; when x"DDA" => DATA <= x"B0"; when x"DDB" => DATA <= x"30"; when x"DDC" => DATA <= x"02"; when x"DDD" => DATA <= x"49"; when x"DDE" => DATA <= x"10"; when x"DDF" => DATA <= x"18"; when x"DE0" => DATA <= x"69"; when x"DE1" => DATA <= x"20"; when x"DE2" => DATA <= x"2C"; when x"DE3" => DATA <= x"01"; when x"DE4" => DATA <= x"B0"; when x"DE5" => DATA <= x"70"; when x"DE6" => DATA <= x"02"; when x"DE7" => DATA <= x"29"; when x"DE8" => DATA <= x"1F"; when x"DE9" => DATA <= x"4C"; when x"DEA" => DATA <= x"60"; when x"DEB" => DATA <= x"FE"; when x"DEC" => DATA <= x"A5"; when x"DED" => DATA <= x"DE"; when x"DEE" => DATA <= x"A4"; when x"DEF" => DATA <= x"DF"; when x"DF0" => DATA <= x"C0"; when x"DF1" => DATA <= x"81"; when x"DF2" => DATA <= x"90"; when x"DF3" => DATA <= x"38"; when x"DF4" => DATA <= x"C9"; when x"DF5" => DATA <= x"E0"; when x"DF6" => DATA <= x"90"; when x"DF7" => DATA <= x"34"; when x"DF8" => DATA <= x"A4"; when x"DF9" => DATA <= x"E6"; when x"DFA" => DATA <= x"30"; when x"DFB" => DATA <= x"0C"; when x"DFC" => DATA <= x"88"; when x"DFD" => DATA <= x"D0"; when x"DFE" => DATA <= x"07"; when x"DFF" => DATA <= x"20"; when x"E00" => DATA <= x"71"; when x"E01" => DATA <= x"FE"; when x"E02" => DATA <= x"B0"; when x"E03" => DATA <= x"FB"; when x"E04" => DATA <= x"A0"; when x"E05" => DATA <= x"10"; when x"E06" => DATA <= x"84"; when x"E07" => DATA <= x"E6"; when x"E08" => DATA <= x"A0"; when x"E09" => DATA <= x"20"; when x"E0A" => DATA <= x"20"; when x"E0B" => DATA <= x"66"; when x"E0C" => DATA <= x"FE"; when x"E0D" => DATA <= x"B9"; when x"E0E" => DATA <= x"00"; when x"E0F" => DATA <= x"80"; when x"E10" => DATA <= x"99"; when x"E11" => DATA <= x"E0"; when x"E12" => DATA <= x"7F"; when x"E13" => DATA <= x"C8"; when x"E14" => DATA <= x"D0"; when x"E15" => DATA <= x"F7"; when x"E16" => DATA <= x"20"; when x"E17" => DATA <= x"6B"; when x"E18" => DATA <= x"FE"; when x"E19" => DATA <= x"B9"; when x"E1A" => DATA <= x"00"; when x"E1B" => DATA <= x"81"; when x"E1C" => DATA <= x"99"; when x"E1D" => DATA <= x"E0"; when x"E1E" => DATA <= x"80"; when x"E1F" => DATA <= x"C8"; when x"E20" => DATA <= x"D0"; when x"E21" => DATA <= x"F7"; when x"E22" => DATA <= x"A0"; when x"E23" => DATA <= x"1F"; when x"E24" => DATA <= x"A9"; when x"E25" => DATA <= x"20"; when x"E26" => DATA <= x"91"; when x"E27" => DATA <= x"DE"; when x"E28" => DATA <= x"88"; when x"E29" => DATA <= x"10"; when x"E2A" => DATA <= x"FB"; when x"E2B" => DATA <= x"60"; when x"E2C" => DATA <= x"69"; when x"E2D" => DATA <= x"20"; when x"E2E" => DATA <= x"85"; when x"E2F" => DATA <= x"DE"; when x"E30" => DATA <= x"D0"; when x"E31" => DATA <= x"02"; when x"E32" => DATA <= x"E6"; when x"E33" => DATA <= x"DF"; when x"E34" => DATA <= x"60"; when x"E35" => DATA <= x"88"; when x"E36" => DATA <= x"10"; when x"E37" => DATA <= x"19"; when x"E38" => DATA <= x"A0"; when x"E39" => DATA <= x"1F"; when x"E3A" => DATA <= x"A5"; when x"E3B" => DATA <= x"DE"; when x"E3C" => DATA <= x"D0"; when x"E3D" => DATA <= x"0B"; when x"E3E" => DATA <= x"A6"; when x"E3F" => DATA <= x"DF"; when x"E40" => DATA <= x"E0"; when x"E41" => DATA <= x"80"; when x"E42" => DATA <= x"D0"; when x"E43" => DATA <= x"05"; when x"E44" => DATA <= x"68"; when x"E45" => DATA <= x"68"; when x"E46" => DATA <= x"4C"; when x"E47" => DATA <= x"65"; when x"E48" => DATA <= x"FD"; when x"E49" => DATA <= x"E9"; when x"E4A" => DATA <= x"20"; when x"E4B" => DATA <= x"85"; when x"E4C" => DATA <= x"DE"; when x"E4D" => DATA <= x"B0"; when x"E4E" => DATA <= x"02"; when x"E4F" => DATA <= x"C6"; when x"E50" => DATA <= x"DF"; when x"E51" => DATA <= x"60"; when x"E52" => DATA <= x"20"; when x"E53" => DATA <= x"FB"; when x"E54" => DATA <= x"FE"; when x"E55" => DATA <= x"08"; when x"E56" => DATA <= x"48"; when x"E57" => DATA <= x"D8"; when x"E58" => DATA <= x"84"; when x"E59" => DATA <= x"E5"; when x"E5A" => DATA <= x"86"; when x"E5B" => DATA <= x"E4"; when x"E5C" => DATA <= x"20"; when x"E5D" => DATA <= x"EA"; when x"E5E" => DATA <= x"FC"; when x"E5F" => DATA <= x"68"; when x"E60" => DATA <= x"A6"; when x"E61" => DATA <= x"E4"; when x"E62" => DATA <= x"A4"; when x"E63" => DATA <= x"E5"; when x"E64" => DATA <= x"28"; when x"E65" => DATA <= x"60"; when x"E66" => DATA <= x"2C"; when x"E67" => DATA <= x"02"; when x"E68" => DATA <= x"B0"; when x"E69" => DATA <= x"10"; when x"E6A" => DATA <= x"FB"; when x"E6B" => DATA <= x"2C"; when x"E6C" => DATA <= x"02"; when x"E6D" => DATA <= x"B0"; when x"E6E" => DATA <= x"30"; when x"E6F" => DATA <= x"FB"; when x"E70" => DATA <= x"60"; when x"E71" => DATA <= x"A0"; when x"E72" => DATA <= x"3B"; when x"E73" => DATA <= x"18"; when x"E74" => DATA <= x"A9"; when x"E75" => DATA <= x"20"; when x"E76" => DATA <= x"A2"; when x"E77" => DATA <= x"0A"; when x"E78" => DATA <= x"2C"; when x"E79" => DATA <= x"01"; when x"E7A" => DATA <= x"B0"; when x"E7B" => DATA <= x"F0"; when x"E7C" => DATA <= x"08"; when x"E7D" => DATA <= x"EE"; when x"E7E" => DATA <= x"00"; when x"E7F" => DATA <= x"B0"; when x"E80" => DATA <= x"88"; when x"E81" => DATA <= x"CA"; when x"E82" => DATA <= x"D0"; when x"E83" => DATA <= x"F4"; when x"E84" => DATA <= x"4A"; when x"E85" => DATA <= x"08"; when x"E86" => DATA <= x"48"; when x"E87" => DATA <= x"AD"; when x"E88" => DATA <= x"00"; when x"E89" => DATA <= x"B0"; when x"E8A" => DATA <= x"29"; when x"E8B" => DATA <= x"F0"; when x"E8C" => DATA <= x"8D"; when x"E8D" => DATA <= x"00"; when x"E8E" => DATA <= x"B0"; when x"E8F" => DATA <= x"68"; when x"E90" => DATA <= x"28"; when x"E91" => DATA <= x"D0"; when x"E92" => DATA <= x"E3"; when x"E93" => DATA <= x"60"; when x"E94" => DATA <= x"08"; when x"E95" => DATA <= x"D8"; when x"E96" => DATA <= x"86"; when x"E97" => DATA <= x"E4"; when x"E98" => DATA <= x"84"; when x"E99" => DATA <= x"E5"; when x"E9A" => DATA <= x"2C"; when x"E9B" => DATA <= x"02"; when x"E9C" => DATA <= x"B0"; when x"E9D" => DATA <= x"50"; when x"E9E" => DATA <= x"05"; when x"E9F" => DATA <= x"20"; when x"EA0" => DATA <= x"71"; when x"EA1" => DATA <= x"FE"; when x"EA2" => DATA <= x"90"; when x"EA3" => DATA <= x"F6"; when x"EA4" => DATA <= x"20"; when x"EA5" => DATA <= x"8A"; when x"EA6" => DATA <= x"FB"; when x"EA7" => DATA <= x"20"; when x"EA8" => DATA <= x"71"; when x"EA9" => DATA <= x"FE"; when x"EAA" => DATA <= x"B0"; when x"EAB" => DATA <= x"FB"; when x"EAC" => DATA <= x"20"; when x"EAD" => DATA <= x"71"; when x"EAE" => DATA <= x"FE"; when x"EAF" => DATA <= x"B0"; when x"EB0" => DATA <= x"F6"; when x"EB1" => DATA <= x"98"; when x"EB2" => DATA <= x"A2"; when x"EB3" => DATA <= x"17"; when x"EB4" => DATA <= x"20"; when x"EB5" => DATA <= x"C5"; when x"EB6" => DATA <= x"FE"; when x"EB7" => DATA <= x"BD"; when x"EB8" => DATA <= x"E3"; when x"EB9" => DATA <= x"FE"; when x"EBA" => DATA <= x"85"; when x"EBB" => DATA <= x"E2"; when x"EBC" => DATA <= x"A9"; when x"EBD" => DATA <= x"FD"; when x"EBE" => DATA <= x"85"; when x"EBF" => DATA <= x"E3"; when x"EC0" => DATA <= x"98"; when x"EC1" => DATA <= x"6C"; when x"EC2" => DATA <= x"E2"; when x"EC3" => DATA <= x"00"; when x"EC4" => DATA <= x"CA"; when x"EC5" => DATA <= x"DD"; when x"EC6" => DATA <= x"CB"; when x"EC7" => DATA <= x"FE"; when x"EC8" => DATA <= x"90"; when x"EC9" => DATA <= x"FA"; when x"ECA" => DATA <= x"60"; when x"ECB" => DATA <= x"00"; when x"ECC" => DATA <= x"08"; when x"ECD" => DATA <= x"09"; when x"ECE" => DATA <= x"0A"; when x"ECF" => DATA <= x"0B"; when x"ED0" => DATA <= x"0C"; when x"ED1" => DATA <= x"0D"; when x"ED2" => DATA <= x"0E"; when x"ED3" => DATA <= x"0F"; when x"ED4" => DATA <= x"1E"; when x"ED5" => DATA <= x"7F"; when x"ED6" => DATA <= x"00"; when x"ED7" => DATA <= x"01"; when x"ED8" => DATA <= x"05"; when x"ED9" => DATA <= x"06"; when x"EDA" => DATA <= x"08"; when x"EDB" => DATA <= x"0E"; when x"EDC" => DATA <= x"0F"; when x"EDD" => DATA <= x"10"; when x"EDE" => DATA <= x"11"; when x"EDF" => DATA <= x"1C"; when x"EE0" => DATA <= x"20"; when x"EE1" => DATA <= x"21"; when x"EE2" => DATA <= x"3B"; when x"EE3" => DATA <= x"44"; when x"EE4" => DATA <= x"5C"; when x"EE5" => DATA <= x"38"; when x"EE6" => DATA <= x"62"; when x"EE7" => DATA <= x"87"; when x"EE8" => DATA <= x"69"; when x"EE9" => DATA <= x"40"; when x"EEA" => DATA <= x"8D"; when x"EEB" => DATA <= x"92"; when x"EEC" => DATA <= x"7D"; when x"EED" => DATA <= x"50"; when x"EEE" => DATA <= x"DF"; when x"EEF" => DATA <= x"D2"; when x"EF0" => DATA <= x"9A"; when x"EF1" => DATA <= x"A2"; when x"EF2" => DATA <= x"E2"; when x"EF3" => DATA <= x"AE"; when x"EF4" => DATA <= x"C0"; when x"EF5" => DATA <= x"DF"; when x"EF6" => DATA <= x"D8"; when x"EF7" => DATA <= x"D6"; when x"EF8" => DATA <= x"C8"; when x"EF9" => DATA <= x"C6"; when x"EFA" => DATA <= x"C2"; when x"EFB" => DATA <= x"48"; when x"EFC" => DATA <= x"C9"; when x"EFD" => DATA <= x"02"; when x"EFE" => DATA <= x"F0"; when x"EFF" => DATA <= x"27"; when x"F00" => DATA <= x"C9"; when x"F01" => DATA <= x"03"; when x"F02" => DATA <= x"F0"; when x"F03" => DATA <= x"34"; when x"F04" => DATA <= x"C5"; when x"F05" => DATA <= x"FE"; when x"F06" => DATA <= x"F0"; when x"F07" => DATA <= x"2E"; when x"F08" => DATA <= x"AD"; when x"F09" => DATA <= x"0C"; when x"F0A" => DATA <= x"B8"; when x"F0B" => DATA <= x"29"; when x"F0C" => DATA <= x"0E"; when x"F0D" => DATA <= x"F0"; when x"F0E" => DATA <= x"27"; when x"F0F" => DATA <= x"68"; when x"F10" => DATA <= x"2C"; when x"F11" => DATA <= x"01"; when x"F12" => DATA <= x"B8"; when x"F13" => DATA <= x"30"; when x"F14" => DATA <= x"FB"; when x"F15" => DATA <= x"8D"; when x"F16" => DATA <= x"01"; when x"F17" => DATA <= x"B8"; when x"F18" => DATA <= x"48"; when x"F19" => DATA <= x"AD"; when x"F1A" => DATA <= x"0C"; when x"F1B" => DATA <= x"B8"; when x"F1C" => DATA <= x"29"; when x"F1D" => DATA <= x"F0"; when x"F1E" => DATA <= x"09"; when x"F1F" => DATA <= x"0C"; when x"F20" => DATA <= x"8D"; when x"F21" => DATA <= x"0C"; when x"F22" => DATA <= x"B8"; when x"F23" => DATA <= x"09"; when x"F24" => DATA <= x"02"; when x"F25" => DATA <= x"D0"; when x"F26" => DATA <= x"0C"; when x"F27" => DATA <= x"A9"; when x"F28" => DATA <= x"7F"; when x"F29" => DATA <= x"8D"; when x"F2A" => DATA <= x"03"; when x"F2B" => DATA <= x"B8"; when x"F2C" => DATA <= x"AD"; when x"F2D" => DATA <= x"0C"; when x"F2E" => DATA <= x"B8"; when x"F2F" => DATA <= x"29"; when x"F30" => DATA <= x"F0"; when x"F31" => DATA <= x"09"; when x"F32" => DATA <= x"0E"; when x"F33" => DATA <= x"8D"; when x"F34" => DATA <= x"0C"; when x"F35" => DATA <= x"B8"; when x"F36" => DATA <= x"68"; when x"F37" => DATA <= x"60"; when x"F38" => DATA <= x"AD"; when x"F39" => DATA <= x"0C"; when x"F3A" => DATA <= x"B8"; when x"F3B" => DATA <= x"29"; when x"F3C" => DATA <= x"F0"; when x"F3D" => DATA <= x"B0"; when x"F3E" => DATA <= x"F4"; when x"F3F" => DATA <= x"A2"; when x"F40" => DATA <= x"17"; when x"F41" => DATA <= x"BD"; when x"F42" => DATA <= x"9A"; when x"F43" => DATA <= x"FF"; when x"F44" => DATA <= x"9D"; when x"F45" => DATA <= x"04"; when x"F46" => DATA <= x"02"; when x"F47" => DATA <= x"CA"; when x"F48" => DATA <= x"10"; when x"F49" => DATA <= x"F7"; when x"F4A" => DATA <= x"9A"; when x"F4B" => DATA <= x"8A"; when x"F4C" => DATA <= x"E8"; when x"F4D" => DATA <= x"86"; when x"F4E" => DATA <= x"EA"; when x"F4F" => DATA <= x"86"; when x"F50" => DATA <= x"E1"; when x"F51" => DATA <= x"86"; when x"F52" => DATA <= x"E7"; when x"F53" => DATA <= x"A2"; when x"F54" => DATA <= x"33"; when x"F55" => DATA <= x"9D"; when x"F56" => DATA <= x"EB"; when x"F57" => DATA <= x"02"; when x"F58" => DATA <= x"CA"; when x"F59" => DATA <= x"10"; when x"F5A" => DATA <= x"FA"; when x"F5B" => DATA <= x"A9"; when x"F5C" => DATA <= x"0A"; when x"F5D" => DATA <= x"85"; when x"F5E" => DATA <= x"FE"; when x"F5F" => DATA <= x"A9"; when x"F60" => DATA <= x"8A"; when x"F61" => DATA <= x"8D"; when x"F62" => DATA <= x"03"; when x"F63" => DATA <= x"B0"; when x"F64" => DATA <= x"A9"; when x"F65" => DATA <= x"07"; when x"F66" => DATA <= x"8D"; when x"F67" => DATA <= x"02"; when x"F68" => DATA <= x"B0"; when x"F69" => DATA <= x"20"; when x"F6A" => DATA <= x"D1"; when x"F6B" => DATA <= x"F7"; when x"F6C" => DATA <= x"06"; when x"F6D" => DATA <= x"0C"; when x"F6E" => DATA <= x"0F"; when x"F6F" => DATA <= x"41"; when x"F70" => DATA <= x"43"; when x"F71" => DATA <= x"4F"; when x"F72" => DATA <= x"52"; when x"F73" => DATA <= x"4E"; when x"F74" => DATA <= x"20"; when x"F75" => DATA <= x"41"; when x"F76" => DATA <= x"54"; when x"F77" => DATA <= x"4F"; when x"F78" => DATA <= x"4D"; when x"F79" => DATA <= x"0A"; when x"F7A" => DATA <= x"0A"; when x"F7B" => DATA <= x"0D"; when x"F7C" => DATA <= x"A9"; when x"F7D" => DATA <= x"82"; when x"F7E" => DATA <= x"85"; when x"F7F" => DATA <= x"12"; when x"F80" => DATA <= x"58"; when x"F81" => DATA <= x"A9"; when x"F82" => DATA <= x"55"; when x"F83" => DATA <= x"8D"; when x"F84" => DATA <= x"01"; when x"F85" => DATA <= x"29"; when x"F86" => DATA <= x"CD"; when x"F87" => DATA <= x"01"; when x"F88" => DATA <= x"29"; when x"F89" => DATA <= x"D0"; when x"F8A" => DATA <= x"0C"; when x"F8B" => DATA <= x"0A"; when x"F8C" => DATA <= x"8D"; when x"F8D" => DATA <= x"01"; when x"F8E" => DATA <= x"29"; when x"F8F" => DATA <= x"CD"; when x"F90" => DATA <= x"01"; when x"F91" => DATA <= x"29"; when x"F92" => DATA <= x"D0"; when x"F93" => DATA <= x"03"; when x"F94" => DATA <= x"4C"; when x"F95" => DATA <= x"00"; when x"F96" => DATA <= x"E0"; when x"F97" => DATA <= x"4C"; when x"F98" => DATA <= x"B6"; when x"F99" => DATA <= x"C2"; when x"F9A" => DATA <= x"00"; when x"F9B" => DATA <= x"A0"; when x"F9C" => DATA <= x"EF"; when x"F9D" => DATA <= x"F8"; when x"F9E" => DATA <= x"52"; when x"F9F" => DATA <= x"FE"; when x"FA0" => DATA <= x"94"; when x"FA1" => DATA <= x"FE"; when x"FA2" => DATA <= x"6E"; when x"FA3" => DATA <= x"F9"; when x"FA4" => DATA <= x"E5"; when x"FA5" => DATA <= x"FA"; when x"FA6" => DATA <= x"AC"; when x"FA7" => DATA <= x"C2"; when x"FA8" => DATA <= x"AC"; when x"FA9" => DATA <= x"C2"; when x"FAA" => DATA <= x"EE"; when x"FAB" => DATA <= x"FB"; when x"FAC" => DATA <= x"7C"; when x"FAD" => DATA <= x"FC"; when x"FAE" => DATA <= x"38"; when x"FAF" => DATA <= x"FC"; when x"FB0" => DATA <= x"78"; when x"FB1" => DATA <= x"C2"; when x"FB2" => DATA <= x"85"; when x"FB3" => DATA <= x"FF"; when x"FB4" => DATA <= x"68"; when x"FB5" => DATA <= x"48"; when x"FB6" => DATA <= x"29"; when x"FB7" => DATA <= x"10"; when x"FB8" => DATA <= x"D0"; when x"FB9" => DATA <= x"06"; when x"FBA" => DATA <= x"A5"; when x"FBB" => DATA <= x"FF"; when x"FBC" => DATA <= x"48"; when x"FBD" => DATA <= x"6C"; when x"FBE" => DATA <= x"04"; when x"FBF" => DATA <= x"02"; when x"FC0" => DATA <= x"A5"; when x"FC1" => DATA <= x"FF"; when x"FC2" => DATA <= x"28"; when x"FC3" => DATA <= x"08"; when x"FC4" => DATA <= x"6C"; when x"FC5" => DATA <= x"02"; when x"FC6" => DATA <= x"02"; when x"FC7" => DATA <= x"48"; when x"FC8" => DATA <= x"6C"; when x"FC9" => DATA <= x"00"; when x"FCA" => DATA <= x"02"; when x"FCB" => DATA <= x"6C"; when x"FCC" => DATA <= x"1A"; when x"FCD" => DATA <= x"02"; when x"FCE" => DATA <= x"6C"; when x"FCF" => DATA <= x"18"; when x"FD0" => DATA <= x"02"; when x"FD1" => DATA <= x"6C"; when x"FD2" => DATA <= x"16"; when x"FD3" => DATA <= x"02"; when x"FD4" => DATA <= x"6C"; when x"FD5" => DATA <= x"14"; when x"FD6" => DATA <= x"02"; when x"FD7" => DATA <= x"6C"; when x"FD8" => DATA <= x"12"; when x"FD9" => DATA <= x"02"; when x"FDA" => DATA <= x"6C"; when x"FDB" => DATA <= x"10"; when x"FDC" => DATA <= x"02"; when x"FDD" => DATA <= x"6C"; when x"FDE" => DATA <= x"0E"; when x"FDF" => DATA <= x"02"; when x"FE0" => DATA <= x"6C"; when x"FE1" => DATA <= x"0C"; when x"FE2" => DATA <= x"02"; when x"FE3" => DATA <= x"6C"; when x"FE4" => DATA <= x"0A"; when x"FE5" => DATA <= x"02"; when x"FE6" => DATA <= x"20"; when x"FE7" => DATA <= x"E3"; when x"FE8" => DATA <= x"FF"; when x"FE9" => DATA <= x"C9"; when x"FEA" => DATA <= x"0D"; when x"FEB" => DATA <= x"D0"; when x"FEC" => DATA <= x"07"; when x"FED" => DATA <= x"A9"; when x"FEE" => DATA <= x"0A"; when x"FEF" => DATA <= x"20"; when x"FF0" => DATA <= x"F4"; when x"FF1" => DATA <= x"FF"; when x"FF2" => DATA <= x"A9"; when x"FF3" => DATA <= x"0D"; when x"FF4" => DATA <= x"6C"; when x"FF5" => DATA <= x"08"; when x"FF6" => DATA <= x"02"; when x"FF7" => DATA <= x"6C"; when x"FF8" => DATA <= x"06"; when x"FF9" => DATA <= x"02"; when x"FFA" => DATA <= x"C7"; when x"FFB" => DATA <= x"FF"; when x"FFC" => DATA <= x"3F"; when x"FFD" => DATA <= x"FF"; when x"FFE" => DATA <= x"B2"; when x"FFF" => DATA <= x"FF"; when others => DATA <= (others => '0'); end case; end process; end RTL;
apache-2.0
1717c64f7415b2c669d5dc51cc786e15
0.358257
2.919118
false
false
false
false
progranism/Open-Source-FPGA-Bitcoin-Miner
projects/VC707_experimental/VC707_experimental.srcs/sources_1/ip/golden_ticket_fifo/fifo_generator_v10_0/common/wr_pf_as.vhd
9
27,228
`protect begin_protected `protect version = 1 `protect encrypt_agent = "XILINX" `protect encrypt_agent_info = "Xilinx Encryption Tool 2013" `protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64) `protect key_block oN0wWrBe0rGnQ0ZpmkHwkCAUrYr/Gio1+Il/P3mSrzFjyZ0gie82Yw7x94FIXMRv8N6PeTNfKpl9 5/Y8ky3xhQ== `protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block QtY7k/NolrYKkecpqallF9Cek/S8HeKmSLIzCRo85yPnV+ZHMQR9E5Y+AKXGtTh7Df6gTThcfZwA R93ZUBnlyewMZb5HEDc05neqsbfC0s/c28ug1OUpnHi96wykhCKHOumKaJz8wr0xV4s6RDETZ8yd UXmKpTZhuOjqrjBiGsc= `protect key_keyowner = "Xilinx", key_keyname= "xilinx_rsa_key", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block 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gpl-3.0
28935da9527debefeb3b9719c9bb8412
0.946489
1.838612
false
false
false
false
grwlf/vsim
vhdl_ct/ct00303.vhd
1
2,479
-- NEED RESULT: ARCH00303: Block port clause and port map passed -- NEED RESULT: ARCH00303: Block with a port clause but no port map passed -- NEED RESULT: ARCH00303: Blocks optional port map test completed correctly passed ------------------------------------------------------------------------------- -- -- Copyright (c) 1989 by Intermetrics, Inc. -- All rights reserved. -- ------------------------------------------------------------------------------- -- -- TEST NAME: -- -- CT00303 -- -- AUTHOR: -- -- G. Tominovich -- -- TEST OBJECTIVES: -- -- 9.1 (8) -- -- DESIGN UNIT ORDERING: -- -- E00000(ARCH00303) -- ENT00303_Test_Bench(ARCH00303_Test_Bench) -- -- REVISION HISTORY: -- -- 24-JUL-1987 - initial revision -- -- NOTES: -- -- self-checking -- -- use WORK.STANDARD_TYPES.all ; architecture ARCH00303 of E00000 is function To_Boolean ( p : in bit ) return boolean is begin return Boolean'Val(Bit'Pos(p)) ; end To_Boolean ; function To_Bit ( p : in boolean ) return bit is begin return Bit'Val(Boolean'Pos(p)) ; end To_Bit ; signal s1 : bit := '0' ; signal s2 : boolean := false ; begin B1 : block port ( p1 : inout boolean ) ; port map ( To_Bit (p1) => To_Boolean (s1) ) ; begin process begin p1 <= transport Not p1 after 10 ns ; test_report ( "ARCH00303" , "Block port clause and port map" , True ) ; wait ; end process ; end block B1 ; B2 : block port ( p1 : in boolean := true) ; begin process begin s2 <= transport ((Not s2) and p1) after 10 ns ; test_report ( "ARCH00303" , "Block with a port clause but no port map" , True ) ; wait ; end process ; end block B2 ; P1 : process begin wait for 11 ns ; test_report ( "ARCH00303" , "Blocks optional port map test completed correctly" , (s1 = '1') and s2 ) ; wait ; end process P1 ; end ARCH00303 ; entity ENT00303_Test_Bench is end ENT00303_Test_Bench ; architecture ARCH00303_Test_Bench of ENT00303_Test_Bench is begin L1: block component UUT end component ; for CIS1 : UUT use entity WORK.E00000 ( ARCH00303 ) ; begin CIS1 : UUT ; end block L1 ; end ARCH00303_Test_Bench ;
gpl-3.0
8460a380aa244b1e3c42c0d8bbf60f6b
0.519161
3.531339
false
true
false
false
grwlf/vsim
vhdl_ct/ct00670.vhd
1
4,998
-- NEED RESULT: ARCH00670: Variable default initial values - dynamic subtypes passed ------------------------------------------------------------------------------- -- -- Copyright (c) 1989 by Intermetrics, Inc. -- All rights reserved. -- ------------------------------------------------------------------------------- -- -- TEST NAME: -- -- CT00670 -- -- AUTHOR: -- -- A. Wilmot -- -- TEST OBJECTIVES: -- -- 4.3.1.3 (1) -- 4.3.1.3 (2) -- 4.3.1.3 (3) -- 4.3.1.3 (4) -- -- DESIGN UNIT ORDERING: -- -- E00000(ARCH00670) -- ENT00670_Test_Bench(ARCH00670_Test_Bench) -- -- REVISION HISTORY: -- -- 01-SEP-1987 - initial revision -- -- NOTES: -- -- self-checking -- automatically generated -- use WORK.STANDARD_TYPES.all ; -- architecture ARCH00670 of E00000 is procedure p1 is variable correct : boolean := true ; variable va_boolean_1 : boolean ; variable va_boolean_2 : boolean := d_boolean ; variable va_bit_1 : bit ; variable va_bit_2 : bit := d_bit ; variable va_severity_level_1 : severity_level ; variable va_severity_level_2 : severity_level := d_severity_level ; variable va_character_1 : character ; variable va_character_2 : character := d_character ; variable va_t_enum1_1 : t_enum1 ; variable va_t_enum1_2 : t_enum1 := d_t_enum1 ; variable va_st_enum1_1 : st_enum1 ; variable va_st_enum1_2 : st_enum1 := d_st_enum1 ; variable va_integer_1 : integer ; variable va_integer_2 : integer := d_integer ; variable va_t_int1_1 : t_int1 ; variable va_t_int1_2 : t_int1 := d_t_int1 ; variable va_st_int1_1 : st_int1 ; variable va_st_int1_2 : st_int1 := d_st_int1 ; variable va_time_1 : time ; variable va_time_2 : time := d_time ; variable va_t_phys1_1 : t_phys1 ; variable va_t_phys1_2 : t_phys1 := d_t_phys1 ; variable va_st_phys1_1 : st_phys1 ; variable va_st_phys1_2 : st_phys1 := d_st_phys1 ; variable va_real_1 : real ; variable va_real_2 : real := d_real ; variable va_t_real1_1 : t_real1 ; variable va_t_real1_2 : t_real1 := d_t_real1 ; variable va_st_real1_1 : st_real1 ; variable va_st_real1_2 : st_real1 := d_st_real1 ; begin correct := correct and va_boolean_1 = va_boolean_2 and va_boolean_2 = d_boolean ; correct := correct and va_bit_1 = va_bit_2 and va_bit_2 = d_bit ; correct := correct and va_severity_level_1 = va_severity_level_2 and va_severity_level_2 = d_severity_level ; correct := correct and va_character_1 = va_character_2 and va_character_2 = d_character ; correct := correct and va_t_enum1_1 = va_t_enum1_2 and va_t_enum1_2 = d_t_enum1 ; correct := correct and va_st_enum1_1 = va_st_enum1_2 and va_st_enum1_2 = d_st_enum1 ; correct := correct and va_integer_1 = va_integer_2 and va_integer_2 = d_integer ; correct := correct and va_t_int1_1 = va_t_int1_2 and va_t_int1_2 = d_t_int1 ; correct := correct and va_st_int1_1 = va_st_int1_2 and va_st_int1_2 = d_st_int1 ; correct := correct and va_time_1 = va_time_2 and va_time_2 = d_time ; correct := correct and va_t_phys1_1 = va_t_phys1_2 and va_t_phys1_2 = d_t_phys1 ; correct := correct and va_st_phys1_1 = va_st_phys1_2 and va_st_phys1_2 = d_st_phys1 ; correct := correct and va_real_1 = va_real_2 and va_real_2 = d_real ; correct := correct and va_t_real1_1 = va_t_real1_2 and va_t_real1_2 = d_t_real1 ; correct := correct and va_st_real1_1 = va_st_real1_2 and va_st_real1_2 = d_st_real1 ; test_report ( "ARCH00670" , "Variable default initial values - dynamic subtypes" , correct) ; end p1 ; begin process begin p1 ; wait ; end process ; end ARCH00670 ; -- entity ENT00670_Test_Bench is end ENT00670_Test_Bench ; -- architecture ARCH00670_Test_Bench of ENT00670_Test_Bench is begin L1: block component UUT end component ; for CIS1 : UUT use entity WORK.E00000 ( ARCH00670 ) ; begin CIS1 : UUT ; end block L1 ; end ARCH00670_Test_Bench ;
gpl-3.0
82488e29b2d6bb0b64ea5872cd997aea
0.484594
3.365657
false
true
false
false
jairov4/accel-oil
solution_virtex5/impl/pcores/nfa_accept_samples_generic_hw_top_v1_00_a/simhdl/vhdl/nfa_forward_buckets_if_async_fifo.vhd
1
5,843
library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity nfa_forward_buckets_if_async_fifo is generic ( DATA_WIDTH : integer := 32; ADDR_WIDTH : integer := 3; DEPTH : integer := 8); port ( clk_w : in std_logic; clk_r : in std_logic; reset : in std_logic; if_din : in std_logic_vector(DATA_WIDTH - 1 downto 0); if_full_n : out std_logic; if_write_ce: in std_logic := '1'; if_write : in std_logic; if_dout : out std_logic_vector(DATA_WIDTH - 1 downto 0); if_empty_n : out std_logic; if_read_ce : in std_logic := '1'; if_read : in std_logic); function calc_addr_width(x : integer) return integer is begin if (x < 1) then return 1; else return x; end if; end function; end entity; architecture rtl of nfa_forward_buckets_if_async_fifo is constant DEPTH_BITS : integer := calc_addr_width(ADDR_WIDTH); constant REAL_DEPTH : integer := 2 ** DEPTH_BITS; constant ALL_ONE : unsigned(DEPTH_BITS downto 0) := (others => '1'); constant MASK : std_logic_vector(DEPTH_BITS downto 0) := std_logic_vector(ALL_ONE sll (DEPTH_BITS - 1)); type memtype is array (0 to REAL_DEPTH - 1) of std_logic_vector(DATA_WIDTH - 1 downto 0); signal mem : memtype; signal full : std_logic := '0'; signal empty : std_logic := '1'; signal full_next : std_logic; signal empty_next : std_logic; signal wraddr_bin : std_logic_vector(DEPTH_BITS downto 0) := (others => '0'); signal rdaddr_bin : std_logic_vector(DEPTH_BITS downto 0) := (others => '0'); signal wraddr : std_logic_vector(DEPTH_BITS - 1 downto 0); signal rdaddr : std_logic_vector(DEPTH_BITS - 1 downto 0); signal wraddr_bin_next : std_logic_vector(DEPTH_BITS downto 0); signal rdaddr_bin_next : std_logic_vector(DEPTH_BITS downto 0); signal wraddr_gray_next : std_logic_vector(DEPTH_BITS downto 0); signal rdaddr_gray_next : std_logic_vector(DEPTH_BITS downto 0); signal wraddr_gray_sync0 : std_logic_vector(DEPTH_BITS downto 0) := (others => '0'); signal rdaddr_gray_sync0 : std_logic_vector(DEPTH_BITS downto 0) := (others => '0'); signal wraddr_gray_sync1 : std_logic_vector(DEPTH_BITS downto 0) := (others => '0'); signal rdaddr_gray_sync1 : std_logic_vector(DEPTH_BITS downto 0) := (others => '0'); signal wraddr_gray_sync2 : std_logic_vector(DEPTH_BITS downto 0) := (others => '0'); signal rdaddr_gray_sync2 : std_logic_vector(DEPTH_BITS downto 0) := (others => '0'); signal dout_buf : std_logic_vector(DATA_WIDTH - 1 downto 0) := (others => '0'); attribute ram_style : string; attribute ram_style of mem : signal is "block"; begin if_full_n <= not full; if_empty_n <= not empty; if_dout <= dout_buf; full_next <= '1' when (wraddr_gray_next = (rdaddr_gray_sync2 xor MASK)) else '0'; empty_next <= '1' when (rdaddr_gray_next = wraddr_gray_sync2) else '0'; wraddr <= wraddr_bin(DEPTH_BITS - 1 downto 0); rdaddr <= rdaddr_bin_next(DEPTH_BITS - 1 downto 0); wraddr_bin_next <= std_logic_vector(unsigned(wraddr_bin) + 1) when (full = '0' and if_write = '1') else wraddr_bin; rdaddr_bin_next <= std_logic_vector(unsigned(rdaddr_bin) + 1) when (empty = '0' and if_read = '1') else rdaddr_bin; wraddr_gray_next <= wraddr_bin_next xor std_logic_vector(unsigned(wraddr_bin_next) srl 1); rdaddr_gray_next <= rdaddr_bin_next xor std_logic_vector(unsigned(rdaddr_bin_next) srl 1); -- full, wraddr_bin, wraddr_gray_sync0, rdaddr_gray_sync1, rdaddr_gray_sync2 -- @ clk_w domain process(clk_w, reset) begin if (reset = '1') then full <= '0'; wraddr_bin <= (others => '0'); wraddr_gray_sync0 <= (others => '0'); rdaddr_gray_sync1 <= (others => '0'); rdaddr_gray_sync2 <= (others => '0'); elsif (clk_w'event and clk_w = '1' and if_write_ce = '1') then full <= full_next; wraddr_bin <= wraddr_bin_next; wraddr_gray_sync0 <= wraddr_gray_next; rdaddr_gray_sync1 <= rdaddr_gray_sync0; rdaddr_gray_sync2 <= rdaddr_gray_sync1; end if; end process; -- empty, rdaddr_bin, rdaddr_gray_sync0, wraddr_gray_sync1, wraddr_gray_sync2 -- @ clk_r domain process(clk_r, reset) begin if (reset = '1') then empty <= '1'; rdaddr_bin <= (others => '0'); rdaddr_gray_sync0 <= (others => '0'); wraddr_gray_sync1 <= (others => '0'); wraddr_gray_sync2 <= (others => '0'); elsif (clk_r'event and clk_r = '1' and if_read_ce = '1') then empty <= empty_next; rdaddr_bin <= rdaddr_bin_next; rdaddr_gray_sync0 <= rdaddr_gray_next; wraddr_gray_sync1 <= wraddr_gray_sync0; wraddr_gray_sync2 <= wraddr_gray_sync1; end if; end process; -- write mem process(clk_w) begin if (clk_w'event and clk_w = '1' and if_write_ce = '1') then if (full = '0' and if_write = '1') then mem(to_integer(unsigned(wraddr))) <= if_din; end if; end if; end process; -- read mem process(clk_r) begin if (clk_r'event and clk_r = '1' and if_read_ce = '1') then dout_buf <= mem(to_integer(unsigned(rdaddr))); end if; end process; end architecture;
lgpl-3.0
87f1e0e79960edaf8f7fa9dee5dfe058
0.553312
3.405012
false
false
false
false
grwlf/vsim
vhdl_ct/ct00049.vhd
1
11,391
-- NEED RESULT: ARCH00049.P1: Implicit subtype conversion occurs for universal real/integer passed -- NEED RESULT: ARCH00049.P2: Implicit subtype conversion occurs for universal real/integer passed -- NEED RESULT: ARCH00049.P3: Implicit subtype conversion occurs for universal real/integer passed -- NEED RESULT: ARCH00049.P4: Implicit subtype conversion occurs for universal real/integer passed ------------------------------------------------------------------------------- -- -- Copyright (c) 1989 by Intermetrics, Inc. -- All rights reserved. -- ------------------------------------------------------------------------------- -- -- TEST NAME: -- -- CT00049 -- -- AUTHOR: -- -- G. Tominovich -- -- TEST OBJECTIVES: -- -- 8.4 (4) -- -- DESIGN UNIT ORDERING: -- -- E00000(ARCH00049) -- ENT00049_Test_Bench(ARCH00049_Test_Bench) -- -- REVISION HISTORY: -- -- 29-JUN-1987 - initial revision -- -- NOTES: -- -- self-checking -- automatically generated -- use WORK.STANDARD_TYPES.all ; architecture ARCH00049 of E00000 is signal Dummy : Boolean := false ; -- begin P1 : process ( Dummy ) variable v_integer : integer := c_integer_1 ; variable v_t_int1 : t_int1 := c_t_int1_1 ; variable v_st_int1 : st_int1 := c_st_int1_1 ; variable v_real : real := c_real_1 ; variable v_t_real1 : t_real1 := c_t_real1_1 ; variable v_st_real1 : st_real1 := c_st_real1_1 ; variable v_st_integer_vector : st_integer_vector := c_st_integer_vector_1 ; variable v_st_int1_vector : st_int1_vector := c_st_int1_vector_1 ; variable v_st_real_vector : st_real_vector := c_st_real_vector_1 ; variable v_st_real1_vector : st_real1_vector := c_st_real1_vector_1 ; -- variable correct : boolean := true ; begin v_integer := 50 ; v_t_int1 := 50 ; v_st_int1 := 50 ; v_real := 50.0 ; v_t_real1 := 50.0 ; v_st_real1 := 50.0 ; v_st_integer_vector := (others => 50) ; v_st_int1_vector := (others => 50) ; v_st_real_vector := (others => 50.0) ; v_st_real1_vector := (others => 50.0) ; -- correct := correct and v_integer = 50 ; correct := correct and v_t_int1 = 50 ; correct := correct and v_st_int1 = 50 ; correct := correct and v_real = 50.0 ; correct := correct and v_t_real1 = 50.0 ; correct := correct and v_st_real1 = 50.0 ; correct := correct and v_st_integer_vector = st_integer_vector'((others => 50)) ; correct := correct and v_st_int1_vector = st_int1_vector'((others => 50)) ; correct := correct and v_st_real_vector = st_real_vector'((others => 50.0)) ; correct := correct and v_st_real1_vector = st_real1_vector'((others => 50.0)) ; -- test_report ( "ARCH00049.P1" , "Implicit subtype conversion occurs "& "for universal real/integer", correct) ; end process P1 ; -- P2 : process ( Dummy ) variable correct : boolean := true ; -- procedure Proc1 is variable v_integer : integer := c_integer_1 ; variable v_t_int1 : t_int1 := c_t_int1_1 ; variable v_st_int1 : st_int1 := c_st_int1_1 ; variable v_real : real := c_real_1 ; variable v_t_real1 : t_real1 := c_t_real1_1 ; variable v_st_real1 : st_real1 := c_st_real1_1 ; variable v_st_integer_vector : st_integer_vector := c_st_integer_vector_1 ; variable v_st_int1_vector : st_int1_vector := c_st_int1_vector_1 ; variable v_st_real_vector : st_real_vector := c_st_real_vector_1 ; variable v_st_real1_vector : st_real1_vector := c_st_real1_vector_1 ; -- begin v_integer := 50 ; v_t_int1 := 50 ; v_st_int1 := 50 ; v_real := 50.0 ; v_t_real1 := 50.0 ; v_st_real1 := 50.0 ; v_st_integer_vector := (others => 50) ; v_st_int1_vector := (others => 50) ; v_st_real_vector := (others => 50.0) ; v_st_real1_vector := (others => 50.0) ; -- correct := correct and v_integer = 50 ; correct := correct and v_t_int1 = 50 ; correct := correct and v_st_int1 = 50 ; correct := correct and v_real = 50.0 ; correct := correct and v_t_real1 = 50.0 ; correct := correct and v_st_real1 = 50.0 ; correct := correct and v_st_integer_vector = st_integer_vector'((others => 50)) ; correct := correct and v_st_int1_vector = st_int1_vector'((others => 50)) ; correct := correct and v_st_real_vector = st_real_vector'((others => 50.0)) ; correct := correct and v_st_real1_vector = st_real1_vector'((others => 50.0)) ; -- end Proc1 ; begin Proc1 ; test_report ( "ARCH00049.P2" , "Implicit subtype conversion occurs "& "for universal real/integer", correct) ; end process P2 ; -- P3 : process ( Dummy ) variable v_integer : integer := c_integer_1 ; variable v_t_int1 : t_int1 := c_t_int1_1 ; variable v_st_int1 : st_int1 := c_st_int1_1 ; variable v_real : real := c_real_1 ; variable v_t_real1 : t_real1 := c_t_real1_1 ; variable v_st_real1 : st_real1 := c_st_real1_1 ; variable v_st_integer_vector : st_integer_vector := c_st_integer_vector_1 ; variable v_st_int1_vector : st_int1_vector := c_st_int1_vector_1 ; variable v_st_real_vector : st_real_vector := c_st_real_vector_1 ; variable v_st_real1_vector : st_real1_vector := c_st_real1_vector_1 ; -- variable correct : boolean := true ; -- procedure Proc1 is begin v_integer := 50 ; v_t_int1 := 50 ; v_st_int1 := 50 ; v_real := 50.0 ; v_t_real1 := 50.0 ; v_st_real1 := 50.0 ; v_st_integer_vector := (others => 50) ; v_st_int1_vector := (others => 50) ; v_st_real_vector := (others => 50.0) ; v_st_real1_vector := (others => 50.0) ; -- end Proc1 ; begin Proc1 ; correct := correct and v_integer = 50 ; correct := correct and v_t_int1 = 50 ; correct := correct and v_st_int1 = 50 ; correct := correct and v_real = 50.0 ; correct := correct and v_t_real1 = 50.0 ; correct := correct and v_st_real1 = 50.0 ; correct := correct and v_st_integer_vector = st_integer_vector'((others => 50)) ; correct := correct and v_st_int1_vector = st_int1_vector'((others => 50)) ; correct := correct and v_st_real_vector = st_real_vector'((others => 50.0)) ; correct := correct and v_st_real1_vector = st_real1_vector'((others => 50.0)) ; -- test_report ( "ARCH00049.P3" , "Implicit subtype conversion occurs "& "for universal real/integer", correct) ; end process P3 ; -- P4 : process ( Dummy ) variable v_integer : integer := c_integer_1 ; variable v_t_int1 : t_int1 := c_t_int1_1 ; variable v_st_int1 : st_int1 := c_st_int1_1 ; variable v_real : real := c_real_1 ; variable v_t_real1 : t_real1 := c_t_real1_1 ; variable v_st_real1 : st_real1 := c_st_real1_1 ; variable v_st_integer_vector : st_integer_vector := c_st_integer_vector_1 ; variable v_st_int1_vector : st_int1_vector := c_st_int1_vector_1 ; variable v_st_real_vector : st_real_vector := c_st_real_vector_1 ; variable v_st_real1_vector : st_real1_vector := c_st_real1_vector_1 ; -- variable correct : boolean := true ; -- procedure Proc1 ( v_integer : inout integer ; v_t_int1 : inout t_int1 ; v_st_int1 : inout st_int1 ; v_real : inout real ; v_t_real1 : inout t_real1 ; v_st_real1 : inout st_real1 ; v_st_integer_vector : inout st_integer_vector ; v_st_int1_vector : inout st_int1_vector ; v_st_real_vector : inout st_real_vector ; v_st_real1_vector : inout st_real1_vector ) is begin v_integer := 50 ; v_t_int1 := 50 ; v_st_int1 := 50 ; v_real := 50.0 ; v_t_real1 := 50.0 ; v_st_real1 := 50.0 ; v_st_integer_vector := (others => 50) ; v_st_int1_vector := (others => 50) ; v_st_real_vector := (others => 50.0) ; v_st_real1_vector := (others => 50.0) ; -- end Proc1 ; begin Proc1 ( v_integer , v_t_int1 , v_st_int1 , v_real , v_t_real1 , v_st_real1 , v_st_integer_vector , v_st_int1_vector , v_st_real_vector , v_st_real1_vector ) ; correct := correct and v_integer = 50 ; correct := correct and v_t_int1 = 50 ; correct := correct and v_st_int1 = 50 ; correct := correct and v_real = 50.0 ; correct := correct and v_t_real1 = 50.0 ; correct := correct and v_st_real1 = 50.0 ; correct := correct and v_st_integer_vector = st_integer_vector'((others => 50)) ; correct := correct and v_st_int1_vector = st_int1_vector'((others => 50)) ; correct := correct and v_st_real_vector = st_real_vector'((others => 50.0)) ; correct := correct and v_st_real1_vector = st_real1_vector'((others => 50.0)) ; -- test_report ( "ARCH00049.P4" , "Implicit subtype conversion occurs "& "for universal real/integer", correct) ; end process P4 ; -- end ARCH00049 ; -- entity ENT00049_Test_Bench is end ENT00049_Test_Bench ; -- architecture ARCH00049_Test_Bench of ENT00049_Test_Bench is begin L1: block component UUT end component ; for CIS1 : UUT use entity WORK.E00000 ( ARCH00049 ) ; begin CIS1 : UUT ; end block L1 ; end ARCH00049_Test_Bench ;
gpl-3.0
e25d50efc9f040f4da981270a85f298b
0.474322
3.518999
false
false
false
false
wsoltys/AtomFpga
src/Atomic_core.vhd
1
25,599
-------------------------------------------------------------------------------- -- Copyright (c) 2009 Alan Daly. All rights reserved. -------------------------------------------------------------------------------- -- ____ ____ -- / /\/ / -- /___/ \ / -- \ \ \/ -- \ \ -- / / Filename : Atomic_top.vhf -- /___/ /\ Timestamp : 02/03/2013 06:17:50 -- \ \ / \ -- \___\/\___\ -- --Design Name: Atomic_top --Device: spartan3A library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; use ieee.numeric_std.all; entity Atomic_core is generic ( CImplSDDOS : boolean; CImplGraphicsExt : boolean; CImplSoftChar : boolean; CImplSID : boolean; CImplVGA80x40 : boolean; CImplHWScrolling : boolean; CImplMouse : boolean; CImplUart : boolean; MainClockSpeed : integer; DefaultBaud : integer ); port (clk_vga : in std_logic; clk_16M00 : in std_logic; clk_32M00 : in std_logic; ps2_clk : in std_logic; ps2_data : in std_logic; ps2_mouse_clk : inout std_logic; ps2_mouse_data : inout std_logic; ERSTn : in std_logic; IRSTn : out std_logic; red : out std_logic_vector (2 downto 0); green : out std_logic_vector (2 downto 0); blue : out std_logic_vector (2 downto 0); vsync : out std_logic; hsync : out std_logic; RamCE : out std_logic; RomCE : out std_logic; Phi2 : out std_logic; ExternWE : out std_logic; ExternA : out std_logic_vector (16 downto 0); ExternDin : out std_logic_vector (7 downto 0); ExternDout: in std_logic_vector (7 downto 0); audiol : out std_logic; audioR : out std_logic; SDMISO : in std_logic; SDSS : out std_logic; SDCLK : out std_logic; SDMOSI : out std_logic; uart_RxD : in std_logic; uart_TxD : out std_logic; LED1 : out std_logic; LED2 : out std_logic ); end Atomic_core; architecture BEHAVIORAL of Atomic_core is component T65 port( Mode : in std_logic_vector(1 downto 0); Res_n : in std_logic; Enable : in std_logic; Clk : in std_logic; Rdy : in std_logic; Abort_n : in std_logic; IRQ_n : in std_logic; NMI_n : in std_logic; SO_n : in std_logic; DI : in std_logic_vector(7 downto 0); R_W_n : out std_logic; Sync : out std_logic; EF : out std_logic; MF : out std_logic; XF : out std_logic; ML_n : out std_logic; VP_n : out std_logic; VDA : out std_logic; VPA : out std_logic; A : out std_logic_vector(23 downto 0); DO : out std_logic_vector(7 downto 0)); end component; component I82C55 port ( I_ADDR : in std_logic_vector(1 downto 0); -- A1-A0 I_DATA : in std_logic_vector(7 downto 0); -- D7-D0 O_DATA : out std_logic_vector(7 downto 0); CS_H : in std_logic; WR_L : in std_logic; O_PA : out std_logic_vector(7 downto 0); I_PB : in std_logic_vector(7 downto 0); I_PC : in std_logic_vector(3 downto 0); O_PC : out std_logic_vector(3 downto 0); RESET : in std_logic; ENA : in std_logic; CLK : in std_logic ); end component; component keyboard port ( CLOCK : in std_logic; nRESET : in std_logic; CLKEN_1MHZ : in std_logic; PS2_CLK : in std_logic; PS2_DATA : in std_logic; KEYOUT : out std_logic_vector(5 downto 0); ROW : in std_logic_vector(3 downto 0); ESC_IN : in std_logic; BREAK_IN : in std_logic; SHIFT_OUT : out std_logic; CTRL_OUT : out std_logic; REPEAT_OUT : out std_logic; BREAK_OUT : out std_logic; TURBO : out std_logic_vector(1 downto 0); ESC_OUT : out std_logic); end component; component M6522 port ( I_RS : in std_logic_vector(3 downto 0); I_DATA : in std_logic_vector(7 downto 0); O_DATA : out std_logic_vector(7 downto 0); I_RW_L : in std_logic; I_CS1 : in std_logic; I_CS2_L : in std_logic; O_IRQ_L : out std_logic; I_CA1 : in std_logic; I_CA2 : in std_logic; O_CA2 : out std_logic; I_PA : in std_logic_vector(7 downto 0); O_PA : out std_logic_vector(7 downto 0); I_CB1 : in std_logic; O_CB1 : out std_logic; I_CB2 : in std_logic; O_CB2 : out std_logic; I_PB : in std_logic_vector(7 downto 0); O_PB : out std_logic_vector(7 downto 0); I_P2_H : in std_logic_vector(1 downto 0); RESET_L : in std_logic; ENA_4 : in std_logic; CLK : in std_logic ); end component; component SPI_Port port ( nRST : in std_logic; clk : in std_logic; enable : in std_logic; nwe : in std_logic; address : in std_logic_vector (2 downto 0); datain : in std_logic_vector (7 downto 0); dataout : out std_logic_vector (7 downto 0); MISO : in std_logic; MOSI : out std_logic; NSS : out std_logic; SPICLK : out std_logic ); end component; component AtomGodilVideo generic ( CImplGraphicsExt : boolean; CImplSoftChar : boolean; CImplSID : boolean; CImplVGA80x40 : boolean; CImplHWScrolling : boolean; CImplMouse : boolean; CImplUart : boolean; MainClockSpeed : integer; DefaultBaud : integer ); port ( -- clock_vga is a full speed VGA clock (25MHz ish) clock_vga : in std_logic; -- clock_main is the main clock clock_main : in std_logic; -- A fixed 32MHz clock for the SID clock_sid_32MHz : in std_logic; -- As fast a clock as possible for the SID DAC clock_sid_dac : in std_logic; -- Reset signal (active high) reset : in std_logic; -- Reset signal to 6847 (active high), not currently used reset_vid : in std_logic; -- Main Address / Data Bus din : in std_logic_vector (7 downto 0); dout : out std_logic_vector (7 downto 0); addr : in std_logic_vector (12 downto 0); -- 6847 Control Signals CSS : in std_logic; AG : in std_logic; GM : in std_logic_vector (2 downto 0); nFS : out std_logic; -- RAM signals ram_we : in std_logic; -- SID signals reg_cs : in std_logic; reg_we : in std_logic; -- SID signals sid_cs : in std_logic; sid_we : in std_logic; sid_audio : out std_logic; -- PS/2 Mouse PS2_CLK : inout std_logic; PS2_DATA : inout std_logic; -- UART signals uart_cs : in std_logic; uart_we : in std_logic; uart_RxD : in std_logic; uart_TxD : out std_logic; uart_escape : out std_logic; uart_break : out std_logic; -- VGA Signals final_red : out std_logic; final_green1 : out std_logic; final_green0 : out std_logic; final_blue : out std_logic; final_vsync : out std_logic; final_hsync : out std_logic ); end component; ------------------------------------------------- -- cpu signals names ------------------------------------------------- signal cpu_R_W_n : std_logic; signal cpu_addr : std_logic_vector (15 downto 0); signal cpu_din : std_logic_vector (7 downto 0); signal cpu_dout : std_logic_vector (7 downto 0); signal cpu_IRQ_n : std_logic; --cpu clock and enables signal clken_counter : std_logic_vector (3 downto 0); signal cpu_cycle : std_logic; signal cpu_clken : std_logic; signal not_cpu_R_W_n : std_logic; signal phi : std_logic; --------------------------------------------------- -- VDG signals names --------------------------------------------------- signal RSTn : std_logic; signal vdg_fs_n : std_logic; signal vdg_an_g : std_logic; signal vdg_gm : std_logic_vector(2 downto 0); signal vdg_css : std_logic; -- VGA output signal vdg_red : std_logic; signal vdg_green1 : std_logic; signal vdg_green0 : std_logic; signal vdg_blue : std_logic; signal vdg_hsync : std_logic; signal vdg_vsync : std_logic; signal vdg_hblank : std_logic; signal vdg_vblank : std_logic; ---------------------------------------------------- -- enables ---------------------------------------------------- signal mc6522_enable : std_logic; signal i8255_enable : std_logic; signal extern_rom_enable : std_logic; signal extern_ram_enable : std_logic; signal video_ram_enable : std_logic; signal reg_enable : std_logic; signal sid_enable : std_logic; signal uart_enable : std_logic; signal gated_we : std_logic; signal video_ram_we : std_logic; signal reg_we : std_logic; signal sid_we : std_logic; signal uart_we : std_logic; ---------------------------------------------------- -- ram/roms ---------------------------------------------------- signal extern_data : std_logic_vector(7 downto 0); signal godil_data : std_logic_vector(7 downto 0); ---------------------------------------------------- -- ---------------------------------------------------- signal via_clk : std_logic; signal via4_clken : std_logic; signal via1_clken : std_logic; signal cpu_phase : std_logic_vector(1 downto 0); signal mc6522_data : std_logic_vector(7 downto 0); signal mc6522_irq : std_logic; signal mc6522_ca1 : std_logic; signal mc6522_ca2 : std_logic; signal mc6522_cb1 : std_logic; signal mc6522_cb2 : std_logic; signal mc6522_porta : std_logic_vector(7 downto 0); signal mc6522_portb : std_logic_vector(7 downto 0); signal i8255_pa_data : std_logic_vector(7 downto 0); signal i8255_pb_data : std_logic_vector(7 downto 0); signal i8255_pb_idata : std_logic_vector(7 downto 0); signal i8255_pc_data : std_logic_vector(7 downto 0); signal i8255_pc_idata : std_logic_vector(7 downto 0); signal i8255_data : std_logic_vector(7 downto 0); signal i8255_rd : std_logic; signal inpurps2dat : std_logic; signal inpurps2clk : std_logic; signal ps2dataout : std_logic_vector(5 downto 0); signal key_shift : std_logic; signal key_ctrl : std_logic; signal key_repeat : std_logic; signal key_break : std_logic; signal key_escape : std_logic; signal key_turbo : std_logic_vector(1 downto 0); signal sid_audio : std_logic; signal spi_enable : std_logic; signal spi_data : std_logic_vector (7 downto 0); signal uart_escape : std_logic; signal uart_break : std_logic; -------------------------------------------------------------------- -- here it begin :) -------------------------------------------------------------------- begin --------------------------------------------------------------------- -- --------------------------------------------------------------------- cpu : T65 port map ( Mode => "00", Abort_n => '1', SO_n => '1', Res_n => RSTn, Enable => cpu_clken, Clk => clk_16M00, Rdy => '1', IRQ_n => cpu_IRQ_n, NMI_n => '1', R_W_n => cpu_R_W_n, Sync => open, A(23 downto 16) => open, A(15 downto 0) => cpu_addr(15 downto 0), DI(7 downto 0) => cpu_din(7 downto 0), DO(7 downto 0) => cpu_dout(7 downto 0)); --------------------------------------------------------------------- -- --------------------------------------------------------------------- Inst_AtomGodilVideo : AtomGodilVideo generic map ( CImplGraphicsExt => CImplGraphicsExt, CImplSoftChar => CImplSoftChar, CImplSID => CImplSID, CImplVGA80x40 => CImplVGA80x40, CImplHWScrolling => CImplHWScrolling, CImplMouse => CImplMouse, CImplUart => CImplUart, MainClockSpeed => MainClockSpeed, DefaultBaud => DefaultBaud ) port map ( clock_vga => clk_vga, clock_main => clk_16M00, clock_sid_32Mhz => clk_32M00, clock_sid_dac => clk_32M00, reset => not RSTn, reset_vid => '0', din => cpu_dout, dout => godil_data, addr => cpu_addr(12 downto 0), CSS => vdg_css, AG => vdg_an_g, GM => vdg_gm, nFS => vdg_fs_n, ram_we => video_ram_we, reg_cs => reg_enable, reg_we => reg_we, sid_cs => sid_enable, sid_we => sid_we, sid_audio => sid_audio, PS2_CLK => ps2_mouse_clk, PS2_DATA => ps2_mouse_data, uart_cs => uart_enable, uart_we => uart_we, uart_RxD => uart_RxD, uart_TxD => uart_TxD, uart_escape => uart_escape, uart_break => uart_break, final_red => vdg_red, final_green1 => vdg_green1, final_green0 => vdg_green0, final_blue => vdg_blue, final_vsync => vdg_vsync, final_hsync => vdg_hsync ); --------------------------------------------------------------------- -- --------------------------------------------------------------------- pia : I82C55 port map( I_ADDR => cpu_addr(1 downto 0), -- A1-A0 I_DATA => cpu_dout(7 downto 0), -- D7-D0 O_DATA => i8255_data, CS_H => i8255_enable, WR_L => cpu_R_W_n, O_PA => i8255_pa_data, I_PB => i8255_pb_idata, I_PC => i8255_pc_idata(7 downto 4), O_PC => i8255_pc_data(3 downto 0), RESET => RSTn, ENA => cpu_clken, CLK => clk_16M00); --------------------------------------------------------------------- -- --------------------------------------------------------------------- input : keyboard port map( CLOCK => clk_16M00, nRESET => ERSTn, CLKEN_1MHZ => cpu_clken, PS2_CLK => inpurps2clk, PS2_DATA => inpurps2dat, KEYOUT => ps2dataout, ROW => i8255_pa_data(3 downto 0), ESC_IN => uart_escape, BREAK_IN => uart_break, SHIFT_OUT => key_shift, CTRL_OUT => key_ctrl, REPEAT_OUT => key_repeat, BREAK_OUT => key_break, TURBO => key_turbo, ESC_OUT => key_escape); --------------------------------------------------------------------- -- --------------------------------------------------------------------- via : M6522 port map( I_RS => cpu_addr(3 downto 0), I_DATA => cpu_dout(7 downto 0), O_DATA => mc6522_data(7 downto 0), I_RW_L => cpu_R_W_n, I_CS1 => mc6522_enable, I_CS2_L => '0', O_IRQ_L => mc6522_irq, I_CA1 => mc6522_ca1, I_CA2 => mc6522_ca2, O_CA2 => mc6522_ca2, I_PA => mc6522_porta(7 downto 0), O_PA => mc6522_porta(7 downto 0), I_CB1 => mc6522_cb1, O_CB1 => mc6522_cb1, I_CB2 => mc6522_cb2, O_CB2 => mc6522_cb2, I_PB => mc6522_portb(7 downto 0), O_PB => mc6522_portb(7 downto 0), RESET_L => RSTn, I_P2_H => cpu_phase, ENA_4 => via4_clken, CLK => via_clk); Inst_spi: if (CImplSDDOS) generate Inst_spi_comp : component SPI_Port port map ( nRST => RSTn, clk => clk_16M00, enable => spi_enable, nwe => cpu_R_W_n, address => cpu_addr(2 downto 0), datain => cpu_dout(7 downto 0), dataout => spi_data, MISO => SDMISO, MOSI => SDMOSI, NSS => SDSS, SPICLK => SDCLK ); end generate; --------------------------------------------------------------------- -- --------------------------------------------------------------------- gated_we <= not_cpu_R_W_n; uart_we <= gated_we; video_ram_we <= gated_we and video_ram_enable; reg_we <= gated_we; sid_we <= gated_we; RSTn <= ERSTn and key_break; IRSTn <= RSTn; mc6522_ca1 <= '1'; inpurps2clk <= ps2_clk; inpurps2dat <= ps2_data; not_cpu_R_W_n <= not cpu_R_W_n; cpu_IRQ_n <= mc6522_irq; audiol <= sid_audio; audioR <= i8255_pc_data(2); i8255_pc_idata <= vdg_fs_n & key_repeat & "11" & i8255_pc_data (3 downto 0); i8255_pb_idata <= key_shift & key_ctrl & ps2dataout; vdg_gm <= i8255_pa_data(7 downto 5) when RSTn='1' else "000"; vdg_an_g <= i8255_pa_data(4) when RSTn='1' else '0'; vdg_css <= i8255_pc_data(3) when RSTn='1' else '0'; red(2 downto 0) <= vdg_red & vdg_red & vdg_red; green(2 downto 0) <= vdg_green1 & vdg_green0 & vdg_green0; blue(2 downto 0) <= vdg_blue & vdg_blue & vdg_blue; vsync <= vdg_vsync; hsync <= vdg_hsync; -- enables process(cpu_addr) begin -- All regions normally de-selected mc6522_enable <= '0'; i8255_enable <= '0'; extern_ram_enable <= '0'; extern_rom_enable <= '0'; video_ram_enable <= '0'; sid_enable <= '0'; spi_enable <= '0'; reg_enable <= '0'; uart_enable <= '0'; case cpu_addr(15 downto 12) is when x"0" => extern_ram_enable <= '1'; -- 0x0000 -- 0x03ff is RAM when x"1" => extern_ram_enable <= '1'; when x"2" => extern_ram_enable <= '1'; when x"3" => extern_ram_enable <= '1'; when x"4" => extern_ram_enable <= '1'; when x"5" => extern_ram_enable <= '1'; when x"6" => extern_ram_enable <= '1'; when x"7" => extern_ram_enable <= '1'; when x"8" => video_ram_enable <= '1'; -- 0x8000 -- 0x9fff is RAM when x"9" => video_ram_enable <= '1'; when x"A" => extern_rom_enable <= '1'; when x"B" => if cpu_addr(11 downto 8) = "0000" then -- 0xb000 8255 PIA i8255_enable <= '1'; elsif cpu_addr(11 downto 8) = "1000" then -- 0xb800 6522 VIA (optional) mc6522_enable <= '1'; elsif cpu_addr(11 downto 10) = "01" then spi_enable <= '1'; -- 0xb400-0xb7ff SPI elsif cpu_addr(11 downto 4) = "11011011" then uart_enable <= '1'; -- 0xbdb0-0xbdbf UART elsif cpu_addr(11 downto 5) = "1101110" then sid_enable <= '1'; -- 0xbdc0-0xbddf SID elsif cpu_addr(11 downto 5) = "1101111" then reg_enable <= '1'; -- 0xbde0-0xbdff GODIL Registers end if; when x"C" => extern_rom_enable <= '1'; when x"D" => extern_rom_enable <= '1'; when x"E" => extern_rom_enable <= '1'; when x"F" => extern_rom_enable <= '1'; when others => null; end case; end process; cpu_din <= extern_data when extern_ram_enable = '1' else godil_data when video_ram_enable = '1' else i8255_data when i8255_enable = '1' else mc6522_data when mc6522_enable = '1' else godil_data when sid_enable = '1' and CImplSID else godil_data when uart_enable = '1' and CImplUart else godil_data when reg_enable = '1' else -- TODO add CImpl constraint spi_data when spi_enable = '1' and CImplSDDOS else extern_data when spi_enable = '1' and not CImplSDDOS else extern_data when extern_rom_enable = '1' else x"f1"; -- un-decoded locations ExternWE <= not_cpu_R_W_n; RamCE <= extern_ram_enable; RomCE <= extern_rom_enable; ExternA <= '0' & cpu_addr(15 downto 0); ExternDin <= cpu_dout(7 downto 0); extern_data <= ExternDout; -------------------------------------------------------- -- clock enable generator -------------------------------------------------------- clk_gen : process(clk_16M00, RSTn) begin if RSTn = '0' then clken_counter <= (others => '0'); cpu_clken <= '0'; phi <= '0'; phi2 <= '0'; elsif rising_edge(clk_16M00) then clken_counter <= clken_counter + 1; case (key_turbo) is when "01" => -- 2MHz -- cpu_clken active on cycle 0, 8 -- address/data changes on cycle 1, 9 -- phi2 active on cycle 2..5, 10..13 cpu_clken <= clken_counter(0) and clken_counter(1) and clken_counter(2); -- on cycles 0, 8 phi <= not clken_counter(2); when "10" => -- 4MHz -- cpu_clken active on cycle 0, 4, 8, 12 -- address/data changes on cycle 1, 5, 9, 13 -- phi2 active on cycle 2..3, 6..7 10..11 14..15 cpu_clken <= clken_counter(0) and clken_counter(1); phi <= not clken_counter(1); when "11" => -- 8MHz -- cpu_clken active on cycle 0, 2, 4, 6, 8, 10, 12, 14 -- address/data changes on cycle 1, 3, 5, 7, 9, 11, 13, 15 -- phi2 active on cycle 1, 3, 5, 7, 9, 11, 13, 15 -- NOTE: this case is not ideal, because no matter how you time phi2, one or other -- edge will change at the same time as address/data changes. -- (1) Address Setup at start of write cycle -- (2) Data hold and end of write cycle -- For now we will optimise for (2) cpu_clken <= clken_counter(0); phi <= clken_counter(0); -- not negated, see note above when others => -- 1MHz -- cpu_clken active on cycle 0 -- address/data changes on cycle 1 -- phi2 active on cycle 2..9 cpu_clken <= clken_counter(0) and clken_counter(1) and clken_counter(2) and clken_counter(3); phi <= not clken_counter(3); end case; -- delay by 1 cycle so address and data will be stable for 62.5ns before phi2 phi2 <= phi; end if; end process; cpu_phase <= clken_counter(3) & clken_counter(2); via4_clken <= not (clken_counter(0) or clken_counter(1)); via_clk <= clk_16M00; LED1 <= '0'; LED2 <= '0'; end BEHAVIORAL;
apache-2.0
c20cfb8ce933dfba08a8a74316570691
0.432126
3.781799
false
false
false
false
grwlf/vsim
vhdl_ct/pro000016.vhd
1
3,931
-- Prosoft VHDL tests. -- -- Copyright (C) 2011 Prosoft. -- -- Author: Zefirov, Karavaev. -- -- This is a set of simplest tests for isolated tests of VHDL features. -- -- Nothing more than standard package should be required. -- -- Categories: entity, architecture, process, after, if-then-else, enumerations, array, record, case, for-loop, signals-attributes. use work.std_logic_1164_for_tst.all; entity ENT00013_Test_Bench is end ENT00013_Test_Bench; architecture ARCH00013_Test_Bench of ENT00013_Test_Bench is type std_array_array is array (0 to 3, 1 to 4) of std_ulogic; signal I_saa : std_array_array := (others => x"B"); subtype byte is bit_vector(7 downto 0); subtype byte2 is bit_vector(0 to 7); signal b1 : byte := x"00"; signal b2 : byte2 := x"00"; type bit_array_array is array (0 to 3, 4 downto 1) of bit; signal I_baa : bit_array_array := (others => x"A"); type NatArray is array (natural range <>) of natural; type std_array is array (0 to 7) of std_logic; signal I_sa : std_array := "10101010"; type enum is (a_v, b_v, c_v, d_v, e_v, f_v); type enum_array is array (integer range <>) of enum; type rec is record f1 : integer; f2 : boolean; f3 : bit; f4 : enum; f5 : enum_array(0 to 3); f6 : NatArray(7 downto 0); f7 : bit_vector(7 downto 0); end record; type rec_array is array (integer range <>) of rec; signal e : enum := a_v; signal ea : enum_array(0 to 3) := (others => a_v); signal r : rec := ( f1 => 10 , f2 => true , f3 => '1' , f4 => a_v , f5 => (others => a_v) , f6 => (0 => 10, 7 => 3, others => 0) , f7 => x"33" ); signal ra : rec_array(0 to 3) := (others => ( f1 => 10 , f2 => true , f3 => '1' , f4 => a_v , f5 => (others => a_v) , f6 => (0 => 10, 7 => 3, others => 0) , f7 => x"33" ) ); signal bv : bit_vector(15 downto 0) := x"CCCC"; signal clk : std_ulogic := '0'; signal clk2 : std_ulogic := '0'; type BoolVector is array (integer range <>) of boolean; signal bool : BoolVector(1 to 60); begin bool(25) <= bv'Event; bool(26) <= ra'Event; bool(27) <= r'Event; bool(28) <= ea'Event; bool(29) <= e'Event; bool(30) <= I_sa'Event; bool(31) <= I_baa'Event; bool(32) <= I_saa'Event; bool(33) <= b1'Event; bool(34) <= b2'Event; bool(35) <= clk'Event; bool(36) <= clk2'Event; clk <= not clk after 1 us; clk2 <= not clk2 after 3 us; process (clk) begin if clk'event and clk = '1' then b1 <= b1(6 downto 0) & not b1(7); case e is when a_v => e <= b_v; when b_v => e <= c_v; when c_v => e <= d_v; when d_v => e <= e_v; when e_v => e <= f_v; when f_v => e <= a_v; end case; ea(0) <= e; ea_loop: for i in 1 to ea'length-1 loop ea(i) <= ea(i-1); end loop ea_loop; elsif falling_edge(clk) then bv <= bv(bv'left-1 downto bv'low) & bv(bv'high); r.f1 <= r.f1 + 1; r.f2 <= not r.f2; r.f3 <= not r.f3; r.f4 <= e; r.f5 <= ea; r_f6_loop: for i in r.f6'low to r.f6'high loop r.f6(i) <= r.f6(i) + 1; end loop r_f6_loop; r.f7 <= r.f7(6 downto 0) & r.f7(7); ra(ra'high) <= r; ra_loop: for i in ra'high-1 downto 0 loop ra(i) <= ra(i+1); end loop; end if; end process; process (clk2) begin if rising_edge(clk2) then I_sa <= I_sa(I_sa'length-1) & I_sa(0 to I_sa'length-2); elsif clk2'event and clk2 = '0' then I_saa_loop_1: for i in 0 to 3 loop I_saa_loop_2: for j in 1 to 4 loop I_saa(i,j) <= I_sa(i+j); end loop I_saa_loop_2; end loop I_saa_loop_1; I_baa_loop_1: for i in 0 to 3 loop I_baa_loop_2: for j in 1 to 4 loop I_baa(i,j) <= bv(i*j); end loop I_baa_loop_2; end loop I_baa_loop_1; end if; end process; end ARCH00013_Test_Bench ;
gpl-3.0
8957cc9ba804c5c6f74d5206c1b94538
0.543373
2.466123
false
false
false
false
wsoltys/AtomFpga
src/AVR8/Memory/XDM4Kx8.vhd
1
2,292
--************************************************************************************************ -- 4Kx8(16 KB) DM RAM for AVR Core(Xilinx) -- Version 0.2 -- Designed by Ruslan Lepetenok -- Jack Gassett for use with Papilio -- Modified 30.07.2005 --************************************************************************************************ library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_unsigned.all; use WORK.SynthCtrlPack.all; -- Synthesis control -- For Synplicity Synplify --library virtexe; --use virtexe.components.all; -- Aldec library unisim; use unisim.vcomponents.all; entity XDM4Kx8 is port( cp2 : in std_logic; ce : in std_logic; address : in std_logic_vector(CDATAMEMSIZE downto 0); din : in std_logic_vector(7 downto 0); dout : out std_logic_vector(7 downto 0); we : in std_logic ); end XDM4Kx8; architecture RTL of XDM4Kx8 is type RAMBlDOut_Type is array(2**(address'length-11)-1 downto 0) of std_logic_vector(dout'range); signal RAMBlDOut : RAMBlDOut_Type; signal WEB : std_logic_vector(2**(address'length-11)-1 downto 0); signal cp2n : std_logic; signal gnd : std_logic; signal DIP : STD_LOGIC_VECTOR(0 downto 0) := "1"; signal SSR : STD_LOGIC := '0'; -- Don't use the output resets. begin gnd <= '0'; WEB_Dcd:for i in WEB'range generate WEB(i) <= '1' when (we='1' and address(address'high downto 11)=i) else '0'; end generate ; RAM_Inst:for i in 0 to 2**(address'length-11)-1 generate RAM_Byte:component RAMB16_S9 port map( DO => RAMBlDOut(i)(7 downto 0), ADDR => address(10 downto 0), DI => din(7 downto 0), DIP => DIP, EN => ce, SSR => SSR, CLK => cp2, WE => WEB(i) ); end generate; -- Output data mux dout <= RAMBlDOut(CONV_INTEGER(address(address'high downto 11))); end RTL;
apache-2.0
95fef3a16fa0a929066ccf45b7c98dab
0.469895
3.769737
false
false
false
false
TWW12/lzw
final_project_sim/lzw/lzw.srcs/sources_1/ip/bram_1024_1/bram_1024_1_sim_netlist.vhdl
1
50,604
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved. -- -------------------------------------------------------------------------------- -- Tool Version: Vivado v.2016.4 (win64) Build 1756540 Mon Jan 23 19:11:23 MST 2017 -- Date : Tue Apr 18 23:15:14 2017 -- Host : DESKTOP-I9J3TQJ running 64-bit major release (build 9200) -- Command : write_vhdl -force -mode funcsim -- X:/final_project_sim/lzw/lzw.srcs/sources_1/ip/bram_1024_1/bram_1024_1_sim_netlist.vhdl -- Design : bram_1024_1 -- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or -- synthesized. This netlist cannot be used for SDF annotated simulation. -- Device : xc7z020clg484-1 -- -------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity bram_1024_1_blk_mem_gen_prim_wrapper_init is port ( douta : out STD_LOGIC_VECTOR ( 19 downto 0 ); clka : in STD_LOGIC; ena : in STD_LOGIC; addra : in STD_LOGIC_VECTOR ( 9 downto 0 ); dina : in STD_LOGIC_VECTOR ( 19 downto 0 ); wea : in STD_LOGIC_VECTOR ( 0 to 0 ) ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of bram_1024_1_blk_mem_gen_prim_wrapper_init : entity is "blk_mem_gen_prim_wrapper_init"; end bram_1024_1_blk_mem_gen_prim_wrapper_init; architecture STRUCTURE of bram_1024_1_blk_mem_gen_prim_wrapper_init is signal \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_21\ : STD_LOGIC; signal \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_22\ : STD_LOGIC; signal \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_23\ : STD_LOGIC; signal \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_29\ : STD_LOGIC; signal \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_30\ : STD_LOGIC; signal \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_31\ : STD_LOGIC; signal \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_37\ : STD_LOGIC; signal \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_38\ : STD_LOGIC; signal \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_39\ : STD_LOGIC; signal \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_45\ : STD_LOGIC; signal \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_46\ : STD_LOGIC; signal \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_47\ : STD_LOGIC; signal \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_85\ : STD_LOGIC; signal \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_86\ : STD_LOGIC; signal \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_87\ : STD_LOGIC; signal \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_88\ : STD_LOGIC; signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC; signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC; signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\ : STD_LOGIC; signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\ : STD_LOGIC; signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 ); signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 ); signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 ); attribute CLOCK_DOMAINS : string; attribute CLOCK_DOMAINS of \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\ : label is "COMMON"; attribute box_type : string; attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\ : label is "PRIMITIVE"; begin \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\: unisim.vcomponents.RAMB36E1 generic map( DOA_REG => 1, DOB_REG => 0, EN_ECC_READ => false, EN_ECC_WRITE => false, INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_0A => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_00 => X"0000001E0000001A00000016000000120000000E0000000A0000000600000002", INIT_01 => X"0000011E0000011A00000116000001120000010E0000010A0000010600000102", INIT_02 => X"0000021E0000021A00000216000002120000020E0000020A0000020600000202", INIT_03 => X"0000031E0000031A00000316000003120000030E0000030A0000030600000302", INIT_04 => X"0000041E0000041A00000416000004120000040E0000040A0000040600000402", INIT_05 => X"0000051E0000051A00000516000005120000050E0000050A0000050600000502", INIT_06 => X"0000061E0000061A00000616000006120000060E0000060A0000060600000602", INIT_07 => X"0000071E0000071A00000716000007120000070E0000070A0000070600000702", INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0F => 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X"0000000000000000000000000000000000000000000000000000000000000000", INIT_58 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_59 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_5A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_5B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_5C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_5D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_5E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_5F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_60 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_61 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_62 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_63 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_64 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_65 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_66 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_67 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_68 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_69 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_6A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_6B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_6D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_6E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_6F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_70 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_71 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_72 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_73 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_74 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_A => X"000000000", INIT_B => X"000000000", INIT_FILE => "NONE", IS_CLKARDCLK_INVERTED => '0', IS_CLKBWRCLK_INVERTED => '0', IS_ENARDEN_INVERTED => '0', IS_ENBWREN_INVERTED => '0', IS_RSTRAMARSTRAM_INVERTED => '0', IS_RSTRAMB_INVERTED => '0', IS_RSTREGARSTREG_INVERTED => '0', IS_RSTREGB_INVERTED => '0', RAM_EXTENSION_A => "NONE", RAM_EXTENSION_B => "NONE", RAM_MODE => "TDP", RDADDR_COLLISION_HWCONFIG => "PERFORMANCE", READ_WIDTH_A => 36, READ_WIDTH_B => 36, RSTREG_PRIORITY_A => "REGCE", RSTREG_PRIORITY_B => "REGCE", SIM_COLLISION_CHECK => "ALL", SIM_DEVICE => "7SERIES", SRVAL_A => X"000000000", SRVAL_B => X"000000000", WRITE_MODE_A => "WRITE_FIRST", WRITE_MODE_B => "WRITE_FIRST", WRITE_WIDTH_A => 36, WRITE_WIDTH_B => 36 ) port map ( ADDRARDADDR(15) => '1', ADDRARDADDR(14 downto 5) => addra(9 downto 0), ADDRARDADDR(4 downto 0) => B"11111", ADDRBWRADDR(15 downto 0) => B"0000000000000000", CASCADEINA => '0', CASCADEINB => '0', CASCADEOUTA => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\, CASCADEOUTB => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\, CLKARDCLK => clka, CLKBWRCLK => clka, DBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\, DIADI(31 downto 29) => B"000", DIADI(28 downto 24) => dina(19 downto 15), DIADI(23 downto 21) => B"000", DIADI(20 downto 16) => dina(14 downto 10), DIADI(15 downto 13) => B"000", DIADI(12 downto 8) => dina(9 downto 5), DIADI(7 downto 5) => B"000", DIADI(4 downto 0) => dina(4 downto 0), DIBDI(31 downto 0) => B"00000000000000000000000000000000", DIPADIP(3 downto 0) => B"0000", DIPBDIP(3 downto 0) => B"0000", DOADO(31) => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_21\, DOADO(30) => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_22\, DOADO(29) => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_23\, DOADO(28 downto 24) => douta(19 downto 15), DOADO(23) => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_29\, DOADO(22) => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_30\, DOADO(21) => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_31\, DOADO(20 downto 16) => douta(14 downto 10), DOADO(15) => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_37\, DOADO(14) => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_38\, DOADO(13) => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_39\, DOADO(12 downto 8) => douta(9 downto 5), DOADO(7) => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_45\, DOADO(6) => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_46\, DOADO(5) => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_47\, DOADO(4 downto 0) => douta(4 downto 0), DOBDO(31 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\(31 downto 0), DOPADOP(3) => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_85\, DOPADOP(2) => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_86\, DOPADOP(1) => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_87\, DOPADOP(0) => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_88\, DOPBDOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\(3 downto 0), ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\(7 downto 0), ENARDEN => ena, ENBWREN => '0', INJECTDBITERR => '0', INJECTSBITERR => '0', RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\(8 downto 0), REGCEAREGCE => ena, REGCEB => '0', RSTRAMARSTRAM => '0', RSTRAMB => '0', RSTREGARSTREG => '0', RSTREGB => '0', SBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\, WEA(3) => wea(0), WEA(2) => wea(0), WEA(1) => wea(0), WEA(0) => wea(0), WEBWE(7 downto 0) => B"00000000" ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity bram_1024_1_blk_mem_gen_prim_width is port ( douta : out STD_LOGIC_VECTOR ( 19 downto 0 ); clka : in STD_LOGIC; ena : in STD_LOGIC; addra : in STD_LOGIC_VECTOR ( 9 downto 0 ); dina : in STD_LOGIC_VECTOR ( 19 downto 0 ); wea : in STD_LOGIC_VECTOR ( 0 to 0 ) ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of bram_1024_1_blk_mem_gen_prim_width : entity is "blk_mem_gen_prim_width"; end bram_1024_1_blk_mem_gen_prim_width; architecture STRUCTURE of bram_1024_1_blk_mem_gen_prim_width is begin \prim_init.ram\: entity work.bram_1024_1_blk_mem_gen_prim_wrapper_init port map ( addra(9 downto 0) => addra(9 downto 0), clka => clka, dina(19 downto 0) => dina(19 downto 0), douta(19 downto 0) => douta(19 downto 0), ena => ena, wea(0) => wea(0) ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity bram_1024_1_blk_mem_gen_generic_cstr is port ( douta : out STD_LOGIC_VECTOR ( 19 downto 0 ); clka : in STD_LOGIC; ena : in STD_LOGIC; addra : in STD_LOGIC_VECTOR ( 9 downto 0 ); dina : in STD_LOGIC_VECTOR ( 19 downto 0 ); wea : in STD_LOGIC_VECTOR ( 0 to 0 ) ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of bram_1024_1_blk_mem_gen_generic_cstr : entity is "blk_mem_gen_generic_cstr"; end bram_1024_1_blk_mem_gen_generic_cstr; architecture STRUCTURE of bram_1024_1_blk_mem_gen_generic_cstr is begin \ramloop[0].ram.r\: entity work.bram_1024_1_blk_mem_gen_prim_width port map ( addra(9 downto 0) => addra(9 downto 0), clka => clka, dina(19 downto 0) => dina(19 downto 0), douta(19 downto 0) => douta(19 downto 0), ena => ena, wea(0) => wea(0) ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity bram_1024_1_blk_mem_gen_top is port ( douta : out STD_LOGIC_VECTOR ( 19 downto 0 ); clka : in STD_LOGIC; ena : in STD_LOGIC; addra : in STD_LOGIC_VECTOR ( 9 downto 0 ); dina : in STD_LOGIC_VECTOR ( 19 downto 0 ); wea : in STD_LOGIC_VECTOR ( 0 to 0 ) ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of bram_1024_1_blk_mem_gen_top : entity is "blk_mem_gen_top"; end bram_1024_1_blk_mem_gen_top; architecture STRUCTURE of bram_1024_1_blk_mem_gen_top is begin \valid.cstr\: entity work.bram_1024_1_blk_mem_gen_generic_cstr port map ( addra(9 downto 0) => addra(9 downto 0), clka => clka, dina(19 downto 0) => dina(19 downto 0), douta(19 downto 0) => douta(19 downto 0), ena => ena, wea(0) => wea(0) ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity bram_1024_1_blk_mem_gen_v8_3_5_synth is port ( douta : out STD_LOGIC_VECTOR ( 19 downto 0 ); clka : in STD_LOGIC; ena : in STD_LOGIC; addra : in STD_LOGIC_VECTOR ( 9 downto 0 ); dina : in STD_LOGIC_VECTOR ( 19 downto 0 ); wea : in STD_LOGIC_VECTOR ( 0 to 0 ) ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of bram_1024_1_blk_mem_gen_v8_3_5_synth : entity is "blk_mem_gen_v8_3_5_synth"; end bram_1024_1_blk_mem_gen_v8_3_5_synth; architecture STRUCTURE of bram_1024_1_blk_mem_gen_v8_3_5_synth is begin \gnbram.gnativebmg.native_blk_mem_gen\: entity work.bram_1024_1_blk_mem_gen_top port map ( addra(9 downto 0) => addra(9 downto 0), clka => clka, dina(19 downto 0) => dina(19 downto 0), douta(19 downto 0) => douta(19 downto 0), ena => ena, wea(0) => wea(0) ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity bram_1024_1_blk_mem_gen_v8_3_5 is port ( clka : in STD_LOGIC; rsta : in STD_LOGIC; ena : in STD_LOGIC; regcea : in STD_LOGIC; wea : in STD_LOGIC_VECTOR ( 0 to 0 ); addra : in STD_LOGIC_VECTOR ( 9 downto 0 ); dina : in STD_LOGIC_VECTOR ( 19 downto 0 ); douta : out STD_LOGIC_VECTOR ( 19 downto 0 ); clkb : in STD_LOGIC; rstb : in STD_LOGIC; enb : in STD_LOGIC; regceb : in STD_LOGIC; web : in STD_LOGIC_VECTOR ( 0 to 0 ); addrb : in STD_LOGIC_VECTOR ( 9 downto 0 ); dinb : in STD_LOGIC_VECTOR ( 19 downto 0 ); doutb : out STD_LOGIC_VECTOR ( 19 downto 0 ); injectsbiterr : in STD_LOGIC; injectdbiterr : in STD_LOGIC; eccpipece : in STD_LOGIC; sbiterr : out STD_LOGIC; dbiterr : out STD_LOGIC; rdaddrecc : out STD_LOGIC_VECTOR ( 9 downto 0 ); sleep : in STD_LOGIC; deepsleep : in STD_LOGIC; shutdown : in STD_LOGIC; rsta_busy : out STD_LOGIC; rstb_busy : out STD_LOGIC; s_aclk : in STD_LOGIC; s_aresetn : in STD_LOGIC; s_axi_awid : in STD_LOGIC_VECTOR ( 3 downto 0 ); s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 ); s_axi_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 ); s_axi_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 ); s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 ); s_axi_awvalid : in STD_LOGIC; s_axi_awready : out STD_LOGIC; s_axi_wdata : in STD_LOGIC_VECTOR ( 19 downto 0 ); s_axi_wstrb : in STD_LOGIC_VECTOR ( 0 to 0 ); s_axi_wlast : in STD_LOGIC; s_axi_wvalid : in STD_LOGIC; s_axi_wready : out STD_LOGIC; s_axi_bid : out STD_LOGIC_VECTOR ( 3 downto 0 ); s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 ); s_axi_bvalid : out STD_LOGIC; s_axi_bready : in STD_LOGIC; s_axi_arid : in STD_LOGIC_VECTOR ( 3 downto 0 ); s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 ); s_axi_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 ); s_axi_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 ); s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 ); s_axi_arvalid : in STD_LOGIC; s_axi_arready : out STD_LOGIC; s_axi_rid : out STD_LOGIC_VECTOR ( 3 downto 0 ); s_axi_rdata : out STD_LOGIC_VECTOR ( 19 downto 0 ); s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 ); s_axi_rlast : out STD_LOGIC; s_axi_rvalid : out STD_LOGIC; s_axi_rready : in STD_LOGIC; s_axi_injectsbiterr : in STD_LOGIC; s_axi_injectdbiterr : in STD_LOGIC; s_axi_sbiterr : out STD_LOGIC; s_axi_dbiterr : out STD_LOGIC; s_axi_rdaddrecc : out STD_LOGIC_VECTOR ( 9 downto 0 ) ); attribute C_ADDRA_WIDTH : integer; attribute C_ADDRA_WIDTH of bram_1024_1_blk_mem_gen_v8_3_5 : entity is 10; attribute C_ADDRB_WIDTH : integer; attribute C_ADDRB_WIDTH of bram_1024_1_blk_mem_gen_v8_3_5 : entity is 10; attribute C_ALGORITHM : integer; attribute C_ALGORITHM of bram_1024_1_blk_mem_gen_v8_3_5 : entity is 1; attribute C_AXI_ID_WIDTH : integer; attribute C_AXI_ID_WIDTH of bram_1024_1_blk_mem_gen_v8_3_5 : entity is 4; attribute C_AXI_SLAVE_TYPE : integer; attribute C_AXI_SLAVE_TYPE of bram_1024_1_blk_mem_gen_v8_3_5 : entity is 0; attribute C_AXI_TYPE : integer; attribute C_AXI_TYPE of bram_1024_1_blk_mem_gen_v8_3_5 : entity is 1; attribute C_BYTE_SIZE : integer; attribute C_BYTE_SIZE of bram_1024_1_blk_mem_gen_v8_3_5 : entity is 9; attribute C_COMMON_CLK : integer; attribute C_COMMON_CLK of bram_1024_1_blk_mem_gen_v8_3_5 : entity is 0; attribute C_COUNT_18K_BRAM : string; attribute C_COUNT_18K_BRAM of bram_1024_1_blk_mem_gen_v8_3_5 : entity is "0"; attribute C_COUNT_36K_BRAM : string; attribute C_COUNT_36K_BRAM of bram_1024_1_blk_mem_gen_v8_3_5 : entity is "1"; attribute C_CTRL_ECC_ALGO : string; attribute C_CTRL_ECC_ALGO of bram_1024_1_blk_mem_gen_v8_3_5 : entity is "NONE"; attribute C_DEFAULT_DATA : string; attribute C_DEFAULT_DATA of bram_1024_1_blk_mem_gen_v8_3_5 : entity is "0"; attribute C_DISABLE_WARN_BHV_COLL : integer; attribute C_DISABLE_WARN_BHV_COLL of bram_1024_1_blk_mem_gen_v8_3_5 : entity is 0; attribute C_DISABLE_WARN_BHV_RANGE : integer; attribute C_DISABLE_WARN_BHV_RANGE of bram_1024_1_blk_mem_gen_v8_3_5 : entity is 0; attribute C_ELABORATION_DIR : string; attribute C_ELABORATION_DIR of bram_1024_1_blk_mem_gen_v8_3_5 : entity is "./"; attribute C_ENABLE_32BIT_ADDRESS : integer; attribute C_ENABLE_32BIT_ADDRESS of bram_1024_1_blk_mem_gen_v8_3_5 : entity is 0; attribute C_EN_DEEPSLEEP_PIN : integer; attribute C_EN_DEEPSLEEP_PIN of bram_1024_1_blk_mem_gen_v8_3_5 : entity is 0; attribute C_EN_ECC_PIPE : integer; attribute C_EN_ECC_PIPE of bram_1024_1_blk_mem_gen_v8_3_5 : entity is 0; attribute C_EN_RDADDRA_CHG : integer; attribute C_EN_RDADDRA_CHG of bram_1024_1_blk_mem_gen_v8_3_5 : entity is 0; attribute C_EN_RDADDRB_CHG : integer; attribute C_EN_RDADDRB_CHG of bram_1024_1_blk_mem_gen_v8_3_5 : entity is 0; attribute C_EN_SAFETY_CKT : integer; attribute C_EN_SAFETY_CKT of bram_1024_1_blk_mem_gen_v8_3_5 : entity is 0; attribute C_EN_SHUTDOWN_PIN : integer; attribute C_EN_SHUTDOWN_PIN of bram_1024_1_blk_mem_gen_v8_3_5 : entity is 0; attribute C_EN_SLEEP_PIN : integer; attribute C_EN_SLEEP_PIN of bram_1024_1_blk_mem_gen_v8_3_5 : entity is 0; attribute C_EST_POWER_SUMMARY : string; attribute C_EST_POWER_SUMMARY of bram_1024_1_blk_mem_gen_v8_3_5 : entity is "Estimated Power for IP : 2.74095 mW"; attribute C_FAMILY : string; attribute C_FAMILY of bram_1024_1_blk_mem_gen_v8_3_5 : entity is "zynq"; attribute C_HAS_AXI_ID : integer; attribute C_HAS_AXI_ID of bram_1024_1_blk_mem_gen_v8_3_5 : entity is 0; attribute C_HAS_ENA : integer; attribute C_HAS_ENA of bram_1024_1_blk_mem_gen_v8_3_5 : entity is 1; attribute C_HAS_ENB : integer; attribute C_HAS_ENB of bram_1024_1_blk_mem_gen_v8_3_5 : entity is 0; attribute C_HAS_INJECTERR : integer; attribute C_HAS_INJECTERR of bram_1024_1_blk_mem_gen_v8_3_5 : entity is 0; attribute C_HAS_MEM_OUTPUT_REGS_A : integer; attribute C_HAS_MEM_OUTPUT_REGS_A of bram_1024_1_blk_mem_gen_v8_3_5 : entity is 1; attribute C_HAS_MEM_OUTPUT_REGS_B : integer; attribute C_HAS_MEM_OUTPUT_REGS_B of bram_1024_1_blk_mem_gen_v8_3_5 : entity is 0; attribute C_HAS_MUX_OUTPUT_REGS_A : integer; attribute C_HAS_MUX_OUTPUT_REGS_A of bram_1024_1_blk_mem_gen_v8_3_5 : entity is 0; attribute C_HAS_MUX_OUTPUT_REGS_B : integer; attribute C_HAS_MUX_OUTPUT_REGS_B of bram_1024_1_blk_mem_gen_v8_3_5 : entity is 0; attribute C_HAS_REGCEA : integer; attribute C_HAS_REGCEA of bram_1024_1_blk_mem_gen_v8_3_5 : entity is 0; attribute C_HAS_REGCEB : integer; attribute C_HAS_REGCEB of bram_1024_1_blk_mem_gen_v8_3_5 : entity is 0; attribute C_HAS_RSTA : integer; attribute C_HAS_RSTA of bram_1024_1_blk_mem_gen_v8_3_5 : entity is 0; attribute C_HAS_RSTB : integer; attribute C_HAS_RSTB of bram_1024_1_blk_mem_gen_v8_3_5 : entity is 0; attribute C_HAS_SOFTECC_INPUT_REGS_A : integer; attribute C_HAS_SOFTECC_INPUT_REGS_A of bram_1024_1_blk_mem_gen_v8_3_5 : entity is 0; attribute C_HAS_SOFTECC_OUTPUT_REGS_B : integer; attribute C_HAS_SOFTECC_OUTPUT_REGS_B of bram_1024_1_blk_mem_gen_v8_3_5 : entity is 0; attribute C_INITA_VAL : string; attribute C_INITA_VAL of bram_1024_1_blk_mem_gen_v8_3_5 : entity is "0"; attribute C_INITB_VAL : string; attribute C_INITB_VAL of bram_1024_1_blk_mem_gen_v8_3_5 : entity is "0"; attribute C_INIT_FILE : string; attribute C_INIT_FILE of bram_1024_1_blk_mem_gen_v8_3_5 : entity is "bram_1024_1.mem"; attribute C_INIT_FILE_NAME : string; attribute C_INIT_FILE_NAME of bram_1024_1_blk_mem_gen_v8_3_5 : entity is "bram_1024_1.mif"; attribute C_INTERFACE_TYPE : integer; attribute C_INTERFACE_TYPE of bram_1024_1_blk_mem_gen_v8_3_5 : entity is 0; attribute C_LOAD_INIT_FILE : integer; attribute C_LOAD_INIT_FILE of bram_1024_1_blk_mem_gen_v8_3_5 : entity is 1; attribute C_MEM_TYPE : integer; attribute C_MEM_TYPE of bram_1024_1_blk_mem_gen_v8_3_5 : entity is 0; attribute C_MUX_PIPELINE_STAGES : integer; attribute C_MUX_PIPELINE_STAGES of bram_1024_1_blk_mem_gen_v8_3_5 : entity is 0; attribute C_PRIM_TYPE : integer; attribute C_PRIM_TYPE of bram_1024_1_blk_mem_gen_v8_3_5 : entity is 1; attribute C_READ_DEPTH_A : integer; attribute C_READ_DEPTH_A of bram_1024_1_blk_mem_gen_v8_3_5 : entity is 1024; attribute C_READ_DEPTH_B : integer; attribute C_READ_DEPTH_B of bram_1024_1_blk_mem_gen_v8_3_5 : entity is 1024; attribute C_READ_WIDTH_A : integer; attribute C_READ_WIDTH_A of bram_1024_1_blk_mem_gen_v8_3_5 : entity is 20; attribute C_READ_WIDTH_B : integer; attribute C_READ_WIDTH_B of bram_1024_1_blk_mem_gen_v8_3_5 : entity is 20; attribute C_RSTRAM_A : integer; attribute C_RSTRAM_A of bram_1024_1_blk_mem_gen_v8_3_5 : entity is 0; attribute C_RSTRAM_B : integer; attribute C_RSTRAM_B of bram_1024_1_blk_mem_gen_v8_3_5 : entity is 0; attribute C_RST_PRIORITY_A : string; attribute C_RST_PRIORITY_A of bram_1024_1_blk_mem_gen_v8_3_5 : entity is "CE"; attribute C_RST_PRIORITY_B : string; attribute C_RST_PRIORITY_B of bram_1024_1_blk_mem_gen_v8_3_5 : entity is "CE"; attribute C_SIM_COLLISION_CHECK : string; attribute C_SIM_COLLISION_CHECK of bram_1024_1_blk_mem_gen_v8_3_5 : entity is "ALL"; attribute C_USE_BRAM_BLOCK : integer; attribute C_USE_BRAM_BLOCK of bram_1024_1_blk_mem_gen_v8_3_5 : entity is 0; attribute C_USE_BYTE_WEA : integer; attribute C_USE_BYTE_WEA of bram_1024_1_blk_mem_gen_v8_3_5 : entity is 0; attribute C_USE_BYTE_WEB : integer; attribute C_USE_BYTE_WEB of bram_1024_1_blk_mem_gen_v8_3_5 : entity is 0; attribute C_USE_DEFAULT_DATA : integer; attribute C_USE_DEFAULT_DATA of bram_1024_1_blk_mem_gen_v8_3_5 : entity is 0; attribute C_USE_ECC : integer; attribute C_USE_ECC of bram_1024_1_blk_mem_gen_v8_3_5 : entity is 0; attribute C_USE_SOFTECC : integer; attribute C_USE_SOFTECC of bram_1024_1_blk_mem_gen_v8_3_5 : entity is 0; attribute C_USE_URAM : integer; attribute C_USE_URAM of bram_1024_1_blk_mem_gen_v8_3_5 : entity is 0; attribute C_WEA_WIDTH : integer; attribute C_WEA_WIDTH of bram_1024_1_blk_mem_gen_v8_3_5 : entity is 1; attribute C_WEB_WIDTH : integer; attribute C_WEB_WIDTH of bram_1024_1_blk_mem_gen_v8_3_5 : entity is 1; attribute C_WRITE_DEPTH_A : integer; attribute C_WRITE_DEPTH_A of bram_1024_1_blk_mem_gen_v8_3_5 : entity is 1024; attribute C_WRITE_DEPTH_B : integer; attribute C_WRITE_DEPTH_B of bram_1024_1_blk_mem_gen_v8_3_5 : entity is 1024; attribute C_WRITE_MODE_A : string; attribute C_WRITE_MODE_A of bram_1024_1_blk_mem_gen_v8_3_5 : entity is "WRITE_FIRST"; attribute C_WRITE_MODE_B : string; attribute C_WRITE_MODE_B of bram_1024_1_blk_mem_gen_v8_3_5 : entity is "WRITE_FIRST"; attribute C_WRITE_WIDTH_A : integer; attribute C_WRITE_WIDTH_A of bram_1024_1_blk_mem_gen_v8_3_5 : entity is 20; attribute C_WRITE_WIDTH_B : integer; attribute C_WRITE_WIDTH_B of bram_1024_1_blk_mem_gen_v8_3_5 : entity is 20; attribute C_XDEVICEFAMILY : string; attribute C_XDEVICEFAMILY of bram_1024_1_blk_mem_gen_v8_3_5 : entity is "zynq"; attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of bram_1024_1_blk_mem_gen_v8_3_5 : entity is "blk_mem_gen_v8_3_5"; attribute downgradeipidentifiedwarnings : string; attribute downgradeipidentifiedwarnings of bram_1024_1_blk_mem_gen_v8_3_5 : entity is "yes"; end bram_1024_1_blk_mem_gen_v8_3_5; architecture STRUCTURE of bram_1024_1_blk_mem_gen_v8_3_5 is signal \<const0>\ : STD_LOGIC; begin dbiterr <= \<const0>\; doutb(19) <= \<const0>\; doutb(18) <= \<const0>\; doutb(17) <= \<const0>\; doutb(16) <= \<const0>\; doutb(15) <= \<const0>\; doutb(14) <= \<const0>\; doutb(13) <= \<const0>\; doutb(12) <= \<const0>\; doutb(11) <= \<const0>\; doutb(10) <= \<const0>\; doutb(9) <= \<const0>\; doutb(8) <= \<const0>\; doutb(7) <= \<const0>\; doutb(6) <= \<const0>\; doutb(5) <= \<const0>\; doutb(4) <= \<const0>\; doutb(3) <= \<const0>\; doutb(2) <= \<const0>\; doutb(1) <= \<const0>\; doutb(0) <= \<const0>\; rdaddrecc(9) <= \<const0>\; rdaddrecc(8) <= \<const0>\; rdaddrecc(7) <= \<const0>\; rdaddrecc(6) <= \<const0>\; rdaddrecc(5) <= \<const0>\; rdaddrecc(4) <= \<const0>\; rdaddrecc(3) <= \<const0>\; rdaddrecc(2) <= \<const0>\; rdaddrecc(1) <= \<const0>\; rdaddrecc(0) <= \<const0>\; rsta_busy <= \<const0>\; rstb_busy <= \<const0>\; s_axi_arready <= \<const0>\; s_axi_awready <= \<const0>\; s_axi_bid(3) <= \<const0>\; s_axi_bid(2) <= \<const0>\; s_axi_bid(1) <= \<const0>\; s_axi_bid(0) <= \<const0>\; s_axi_bresp(1) <= \<const0>\; s_axi_bresp(0) <= \<const0>\; s_axi_bvalid <= \<const0>\; s_axi_dbiterr <= \<const0>\; s_axi_rdaddrecc(9) <= \<const0>\; s_axi_rdaddrecc(8) <= \<const0>\; s_axi_rdaddrecc(7) <= \<const0>\; s_axi_rdaddrecc(6) <= \<const0>\; s_axi_rdaddrecc(5) <= \<const0>\; s_axi_rdaddrecc(4) <= \<const0>\; s_axi_rdaddrecc(3) <= \<const0>\; s_axi_rdaddrecc(2) <= \<const0>\; s_axi_rdaddrecc(1) <= \<const0>\; s_axi_rdaddrecc(0) <= \<const0>\; s_axi_rdata(19) <= \<const0>\; s_axi_rdata(18) <= \<const0>\; s_axi_rdata(17) <= \<const0>\; s_axi_rdata(16) <= \<const0>\; s_axi_rdata(15) <= \<const0>\; s_axi_rdata(14) <= \<const0>\; s_axi_rdata(13) <= \<const0>\; s_axi_rdata(12) <= \<const0>\; s_axi_rdata(11) <= \<const0>\; s_axi_rdata(10) <= \<const0>\; s_axi_rdata(9) <= \<const0>\; s_axi_rdata(8) <= \<const0>\; s_axi_rdata(7) <= \<const0>\; s_axi_rdata(6) <= \<const0>\; s_axi_rdata(5) <= \<const0>\; s_axi_rdata(4) <= \<const0>\; s_axi_rdata(3) <= \<const0>\; s_axi_rdata(2) <= \<const0>\; s_axi_rdata(1) <= \<const0>\; s_axi_rdata(0) <= \<const0>\; s_axi_rid(3) <= \<const0>\; s_axi_rid(2) <= \<const0>\; s_axi_rid(1) <= \<const0>\; s_axi_rid(0) <= \<const0>\; s_axi_rlast <= \<const0>\; s_axi_rresp(1) <= \<const0>\; s_axi_rresp(0) <= \<const0>\; s_axi_rvalid <= \<const0>\; s_axi_sbiterr <= \<const0>\; s_axi_wready <= \<const0>\; sbiterr <= \<const0>\; GND: unisim.vcomponents.GND port map ( G => \<const0>\ ); inst_blk_mem_gen: entity work.bram_1024_1_blk_mem_gen_v8_3_5_synth port map ( addra(9 downto 0) => addra(9 downto 0), clka => clka, dina(19 downto 0) => dina(19 downto 0), douta(19 downto 0) => douta(19 downto 0), ena => ena, wea(0) => wea(0) ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity bram_1024_1 is port ( clka : in STD_LOGIC; ena : in STD_LOGIC; wea : in STD_LOGIC_VECTOR ( 0 to 0 ); addra : in STD_LOGIC_VECTOR ( 9 downto 0 ); dina : in STD_LOGIC_VECTOR ( 19 downto 0 ); douta : out STD_LOGIC_VECTOR ( 19 downto 0 ) ); attribute NotValidForBitStream : boolean; attribute NotValidForBitStream of bram_1024_1 : entity is true; attribute CHECK_LICENSE_TYPE : string; attribute CHECK_LICENSE_TYPE of bram_1024_1 : entity is "bram_1024_1,blk_mem_gen_v8_3_5,{}"; attribute downgradeipidentifiedwarnings : string; attribute downgradeipidentifiedwarnings of bram_1024_1 : entity is "yes"; attribute x_core_info : string; attribute x_core_info of bram_1024_1 : entity is "blk_mem_gen_v8_3_5,Vivado 2016.4"; end bram_1024_1; architecture STRUCTURE of bram_1024_1 is signal NLW_U0_dbiterr_UNCONNECTED : STD_LOGIC; signal NLW_U0_rsta_busy_UNCONNECTED : STD_LOGIC; signal NLW_U0_rstb_busy_UNCONNECTED : STD_LOGIC; signal NLW_U0_s_axi_arready_UNCONNECTED : STD_LOGIC; signal NLW_U0_s_axi_awready_UNCONNECTED : STD_LOGIC; signal NLW_U0_s_axi_bvalid_UNCONNECTED : STD_LOGIC; signal NLW_U0_s_axi_dbiterr_UNCONNECTED : STD_LOGIC; signal NLW_U0_s_axi_rlast_UNCONNECTED : STD_LOGIC; signal NLW_U0_s_axi_rvalid_UNCONNECTED : STD_LOGIC; signal NLW_U0_s_axi_sbiterr_UNCONNECTED : STD_LOGIC; signal NLW_U0_s_axi_wready_UNCONNECTED : STD_LOGIC; signal NLW_U0_sbiterr_UNCONNECTED : STD_LOGIC; signal NLW_U0_doutb_UNCONNECTED : STD_LOGIC_VECTOR ( 19 downto 0 ); signal NLW_U0_rdaddrecc_UNCONNECTED : STD_LOGIC_VECTOR ( 9 downto 0 ); signal NLW_U0_s_axi_bid_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 ); signal NLW_U0_s_axi_bresp_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 ); signal NLW_U0_s_axi_rdaddrecc_UNCONNECTED : STD_LOGIC_VECTOR ( 9 downto 0 ); signal NLW_U0_s_axi_rdata_UNCONNECTED : STD_LOGIC_VECTOR ( 19 downto 0 ); signal NLW_U0_s_axi_rid_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 ); signal NLW_U0_s_axi_rresp_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 ); attribute C_ADDRA_WIDTH : integer; attribute C_ADDRA_WIDTH of U0 : label is 10; attribute C_ADDRB_WIDTH : integer; attribute C_ADDRB_WIDTH of U0 : label is 10; attribute C_ALGORITHM : integer; attribute C_ALGORITHM of U0 : label is 1; attribute C_AXI_ID_WIDTH : integer; attribute C_AXI_ID_WIDTH of U0 : label is 4; attribute C_AXI_SLAVE_TYPE : integer; attribute C_AXI_SLAVE_TYPE of U0 : label is 0; attribute C_AXI_TYPE : integer; attribute C_AXI_TYPE of U0 : label is 1; attribute C_BYTE_SIZE : integer; attribute C_BYTE_SIZE of U0 : label is 9; attribute C_COMMON_CLK : integer; attribute C_COMMON_CLK of U0 : label is 0; attribute C_COUNT_18K_BRAM : string; attribute C_COUNT_18K_BRAM of U0 : label is "0"; attribute C_COUNT_36K_BRAM : string; attribute C_COUNT_36K_BRAM of U0 : label is "1"; attribute C_CTRL_ECC_ALGO : string; attribute C_CTRL_ECC_ALGO of U0 : label is "NONE"; attribute C_DEFAULT_DATA : string; attribute C_DEFAULT_DATA of U0 : label is "0"; attribute C_DISABLE_WARN_BHV_COLL : integer; attribute C_DISABLE_WARN_BHV_COLL of U0 : label is 0; attribute C_DISABLE_WARN_BHV_RANGE : integer; attribute C_DISABLE_WARN_BHV_RANGE of U0 : label is 0; attribute C_ELABORATION_DIR : string; attribute C_ELABORATION_DIR of U0 : label is "./"; attribute C_ENABLE_32BIT_ADDRESS : integer; attribute C_ENABLE_32BIT_ADDRESS of U0 : label is 0; attribute C_EN_DEEPSLEEP_PIN : integer; attribute C_EN_DEEPSLEEP_PIN of U0 : label is 0; attribute C_EN_ECC_PIPE : integer; attribute C_EN_ECC_PIPE of U0 : label is 0; attribute C_EN_RDADDRA_CHG : integer; attribute C_EN_RDADDRA_CHG of U0 : label is 0; attribute C_EN_RDADDRB_CHG : integer; attribute C_EN_RDADDRB_CHG of U0 : label is 0; attribute C_EN_SAFETY_CKT : integer; attribute C_EN_SAFETY_CKT of U0 : label is 0; attribute C_EN_SHUTDOWN_PIN : integer; attribute C_EN_SHUTDOWN_PIN of U0 : label is 0; attribute C_EN_SLEEP_PIN : integer; attribute C_EN_SLEEP_PIN of U0 : label is 0; attribute C_EST_POWER_SUMMARY : string; attribute C_EST_POWER_SUMMARY of U0 : label is "Estimated Power for IP : 2.74095 mW"; attribute C_FAMILY : string; attribute C_FAMILY of U0 : label is "zynq"; attribute C_HAS_AXI_ID : integer; attribute C_HAS_AXI_ID of U0 : label is 0; attribute C_HAS_ENA : integer; attribute C_HAS_ENA of U0 : label is 1; attribute C_HAS_ENB : integer; attribute C_HAS_ENB of U0 : label is 0; attribute C_HAS_INJECTERR : integer; attribute C_HAS_INJECTERR of U0 : label is 0; attribute C_HAS_MEM_OUTPUT_REGS_A : integer; attribute C_HAS_MEM_OUTPUT_REGS_A of U0 : label is 1; attribute C_HAS_MEM_OUTPUT_REGS_B : integer; attribute C_HAS_MEM_OUTPUT_REGS_B of U0 : label is 0; attribute C_HAS_MUX_OUTPUT_REGS_A : integer; attribute C_HAS_MUX_OUTPUT_REGS_A of U0 : label is 0; attribute C_HAS_MUX_OUTPUT_REGS_B : integer; attribute C_HAS_MUX_OUTPUT_REGS_B of U0 : label is 0; attribute C_HAS_REGCEA : integer; attribute C_HAS_REGCEA of U0 : label is 0; attribute C_HAS_REGCEB : integer; attribute C_HAS_REGCEB of U0 : label is 0; attribute C_HAS_RSTA : integer; attribute C_HAS_RSTA of U0 : label is 0; attribute C_HAS_RSTB : integer; attribute C_HAS_RSTB of U0 : label is 0; attribute C_HAS_SOFTECC_INPUT_REGS_A : integer; attribute C_HAS_SOFTECC_INPUT_REGS_A of U0 : label is 0; attribute C_HAS_SOFTECC_OUTPUT_REGS_B : integer; attribute C_HAS_SOFTECC_OUTPUT_REGS_B of U0 : label is 0; attribute C_INITA_VAL : string; attribute C_INITA_VAL of U0 : label is "0"; attribute C_INITB_VAL : string; attribute C_INITB_VAL of U0 : label is "0"; attribute C_INIT_FILE : string; attribute C_INIT_FILE of U0 : label is "bram_1024_1.mem"; attribute C_INIT_FILE_NAME : string; attribute C_INIT_FILE_NAME of U0 : label is "bram_1024_1.mif"; attribute C_INTERFACE_TYPE : integer; attribute C_INTERFACE_TYPE of U0 : label is 0; attribute C_LOAD_INIT_FILE : integer; attribute C_LOAD_INIT_FILE of U0 : label is 1; attribute C_MEM_TYPE : integer; attribute C_MEM_TYPE of U0 : label is 0; attribute C_MUX_PIPELINE_STAGES : integer; attribute C_MUX_PIPELINE_STAGES of U0 : label is 0; attribute C_PRIM_TYPE : integer; attribute C_PRIM_TYPE of U0 : label is 1; attribute C_READ_DEPTH_A : integer; attribute C_READ_DEPTH_A of U0 : label is 1024; attribute C_READ_DEPTH_B : integer; attribute C_READ_DEPTH_B of U0 : label is 1024; attribute C_READ_WIDTH_A : integer; attribute C_READ_WIDTH_A of U0 : label is 20; attribute C_READ_WIDTH_B : integer; attribute C_READ_WIDTH_B of U0 : label is 20; attribute C_RSTRAM_A : integer; attribute C_RSTRAM_A of U0 : label is 0; attribute C_RSTRAM_B : integer; attribute C_RSTRAM_B of U0 : label is 0; attribute C_RST_PRIORITY_A : string; attribute C_RST_PRIORITY_A of U0 : label is "CE"; attribute C_RST_PRIORITY_B : string; attribute C_RST_PRIORITY_B of U0 : label is "CE"; attribute C_SIM_COLLISION_CHECK : string; attribute C_SIM_COLLISION_CHECK of U0 : label is "ALL"; attribute C_USE_BRAM_BLOCK : integer; attribute C_USE_BRAM_BLOCK of U0 : label is 0; attribute C_USE_BYTE_WEA : integer; attribute C_USE_BYTE_WEA of U0 : label is 0; attribute C_USE_BYTE_WEB : integer; attribute C_USE_BYTE_WEB of U0 : label is 0; attribute C_USE_DEFAULT_DATA : integer; attribute C_USE_DEFAULT_DATA of U0 : label is 0; attribute C_USE_ECC : integer; attribute C_USE_ECC of U0 : label is 0; attribute C_USE_SOFTECC : integer; attribute C_USE_SOFTECC of U0 : label is 0; attribute C_USE_URAM : integer; attribute C_USE_URAM of U0 : label is 0; attribute C_WEA_WIDTH : integer; attribute C_WEA_WIDTH of U0 : label is 1; attribute C_WEB_WIDTH : integer; attribute C_WEB_WIDTH of U0 : label is 1; attribute C_WRITE_DEPTH_A : integer; attribute C_WRITE_DEPTH_A of U0 : label is 1024; attribute C_WRITE_DEPTH_B : integer; attribute C_WRITE_DEPTH_B of U0 : label is 1024; attribute C_WRITE_MODE_A : string; attribute C_WRITE_MODE_A of U0 : label is "WRITE_FIRST"; attribute C_WRITE_MODE_B : string; attribute C_WRITE_MODE_B of U0 : label is "WRITE_FIRST"; attribute C_WRITE_WIDTH_A : integer; attribute C_WRITE_WIDTH_A of U0 : label is 20; attribute C_WRITE_WIDTH_B : integer; attribute C_WRITE_WIDTH_B of U0 : label is 20; attribute C_XDEVICEFAMILY : string; attribute C_XDEVICEFAMILY of U0 : label is "zynq"; attribute downgradeipidentifiedwarnings of U0 : label is "yes"; begin U0: entity work.bram_1024_1_blk_mem_gen_v8_3_5 port map ( addra(9 downto 0) => addra(9 downto 0), addrb(9 downto 0) => B"0000000000", clka => clka, clkb => '0', dbiterr => NLW_U0_dbiterr_UNCONNECTED, deepsleep => '0', dina(19 downto 0) => dina(19 downto 0), dinb(19 downto 0) => B"00000000000000000000", douta(19 downto 0) => douta(19 downto 0), doutb(19 downto 0) => NLW_U0_doutb_UNCONNECTED(19 downto 0), eccpipece => '0', ena => ena, enb => '0', injectdbiterr => '0', injectsbiterr => '0', rdaddrecc(9 downto 0) => NLW_U0_rdaddrecc_UNCONNECTED(9 downto 0), regcea => '0', regceb => '0', rsta => '0', rsta_busy => NLW_U0_rsta_busy_UNCONNECTED, rstb => '0', rstb_busy => NLW_U0_rstb_busy_UNCONNECTED, s_aclk => '0', s_aresetn => '0', s_axi_araddr(31 downto 0) => B"00000000000000000000000000000000", s_axi_arburst(1 downto 0) => B"00", s_axi_arid(3 downto 0) => B"0000", s_axi_arlen(7 downto 0) => B"00000000", s_axi_arready => NLW_U0_s_axi_arready_UNCONNECTED, s_axi_arsize(2 downto 0) => B"000", s_axi_arvalid => '0', s_axi_awaddr(31 downto 0) => B"00000000000000000000000000000000", s_axi_awburst(1 downto 0) => B"00", s_axi_awid(3 downto 0) => B"0000", s_axi_awlen(7 downto 0) => B"00000000", s_axi_awready => NLW_U0_s_axi_awready_UNCONNECTED, s_axi_awsize(2 downto 0) => B"000", s_axi_awvalid => '0', s_axi_bid(3 downto 0) => NLW_U0_s_axi_bid_UNCONNECTED(3 downto 0), s_axi_bready => '0', s_axi_bresp(1 downto 0) => NLW_U0_s_axi_bresp_UNCONNECTED(1 downto 0), s_axi_bvalid => NLW_U0_s_axi_bvalid_UNCONNECTED, s_axi_dbiterr => NLW_U0_s_axi_dbiterr_UNCONNECTED, s_axi_injectdbiterr => '0', s_axi_injectsbiterr => '0', s_axi_rdaddrecc(9 downto 0) => NLW_U0_s_axi_rdaddrecc_UNCONNECTED(9 downto 0), s_axi_rdata(19 downto 0) => NLW_U0_s_axi_rdata_UNCONNECTED(19 downto 0), s_axi_rid(3 downto 0) => NLW_U0_s_axi_rid_UNCONNECTED(3 downto 0), s_axi_rlast => NLW_U0_s_axi_rlast_UNCONNECTED, s_axi_rready => '0', s_axi_rresp(1 downto 0) => NLW_U0_s_axi_rresp_UNCONNECTED(1 downto 0), s_axi_rvalid => NLW_U0_s_axi_rvalid_UNCONNECTED, s_axi_sbiterr => NLW_U0_s_axi_sbiterr_UNCONNECTED, s_axi_wdata(19 downto 0) => B"00000000000000000000", s_axi_wlast => '0', s_axi_wready => NLW_U0_s_axi_wready_UNCONNECTED, s_axi_wstrb(0) => '0', s_axi_wvalid => '0', sbiterr => NLW_U0_sbiterr_UNCONNECTED, shutdown => '0', sleep => '0', wea(0) => wea(0), web(0) => '0' ); end STRUCTURE;
unlicense
2dea3fdfbc3994b42b583557debf7d8a
0.698719
3.460339
false
false
false
false
grwlf/vsim
vhdl/IEEE/old/numeric_std.vhd
1
92,891
-- ---------------------------------------------------------------------------- -- Title : NUMERIC_STD arithmetic package for synthesis -- : Rev. 1.7 (Nov. 23 1994) -- : -- Library : This package shall be compiled into a library symbolically -- : named IEEE. -- : -- Developers : IEEE DASC Synthesis Working Group, PAR 1076.3 -- : -- Purpose : This package defines numeric types and arithmetic functions -- : for use with synthesis tools. Two numeric types are defined: -- : --> UNSIGNED : represents UNSIGNED number in vector form -- : --> SIGNED : represents a SIGNED number in vector form -- : The base element type is type STD_LOGIC. -- : The leftmost bit is treated as the most significant bit. -- : Signed vectors are represented in two's complement form. -- : This package contains overloaded arithmetic operators on -- : the SIGNED and UNSIGNED types. The package also contains -- : useful type conversions functions. -- : -- : If any argument to a function is a null array, a null array is -- : returned (exceptions, if any, are noted individually). -- : -- Note : No declarations or definitions shall be included in, or -- : excluded from, this package. The package declaration declares -- : the functions that can be used by a user. The package body -- : shall be considered the formal definition of the semantics of -- : this package. Tool developers may choose to implement the -- : package body in the most efficient manner available to them. -- : -- ---------------------------------------------------------------------------- library ieee; use ieee.STD_LOGIC_1164.all; Package numeric_std is --=========================================================================== -- Numeric array type definitions --=========================================================================== type UNSIGNED is array ( NATURAL range <> ) of STD_LOGIC; type SIGNED is array ( NATURAL range <> ) of STD_LOGIC; --=========================================================================== -- Arithmetic Operators: --=========================================================================== -- Id: A.1 function "abs" ( X : SIGNED) return SIGNED; -- Result subtype: SIGNED(X'LENGTH-1 downto 0). -- Result: Returns the absolute value of a SIGNED vector X. -- Id: A.2 function "-" ( ARG: SIGNED) return SIGNED; -- Result subtype: SIGNED(ARG'LENGTH-1 downto 0). -- Result: Returns the value of the unary minus operation on a -- SIGNED vector ARG. --============================================================================ -- Id: A.3 function "+" (L,R: UNSIGNED ) return UNSIGNED; -- Result subtype: UNSIGNED(MAX(L'LENGTH, R'LENGTH)-1 downto 0). -- Result: Adds two UNSIGNED vectors that may be of different lengths. -- Id: A.4 function "+" ( L,R: SIGNED) return SIGNED; -- Result subtype: SIGNED(MAX(L'LENGTH, R'LENGTH)-1 downto 0). -- Result: Adds two SIGNED vectors that may be of different lengths. -- Id: A.5 function "+" ( L: UNSIGNED; R: NATURAL) return UNSIGNED; -- Result subtype: UNSIGNED(L'LENGTH-1 downto 0). -- Result: Adds an UNSIGNED vector, L, with a non-negative INTEGER, R. -- Id: A.6 function "+" ( L: NATURAL; R: UNSIGNED) return UNSIGNED; -- Result subtype: UNSIGNED(R'LENGTH-1 downto 0). -- Result: Adds a non-negative INTEGER, L, with an UNSIGNED vector, R. -- Id: A.7 function "+" ( L: INTEGER; R: SIGNED) return SIGNED; -- Result subtype: SIGNED (R'LENGTH-1 downto 0). -- Result: Adds an INTEGER, L (may be positive or negative), to a SIGNED -- vector, R. -- Id: A.8 function "+" ( L: SIGNED; R: INTEGER) return SIGNED; -- Result subtype: SIGNED (L'LENGTH-1 downto 0). -- Result: Adds a SIGNED vector, L, to an INTEGER, R. --============================================================================ -- Id: A.9 function "-" (L,R: UNSIGNED ) return UNSIGNED; -- Result subtype: UNSIGNED(MAX(L'LENGTH, R'LENGTH)-1 downto 0). -- Result: Subtracts two UNSIGNED vectors that may be of different lengths. -- Id: A.10 function "-" ( L,R: SIGNED) return SIGNED; -- Result subtype: SIGNED(MAX(L'LENGTH, R'LENGTH)-1 downto 0). -- Result: Subtracts a SIGNED vector, R, from another SIGNED vector, L, -- that may possibly be of different lengths. -- Id: A.11 function "-" ( L: UNSIGNED;R: NATURAL) return UNSIGNED; -- Result subtype: UNSIGNED (L'LENGTH-1 downto 0). -- Result: Subtracts a non-negative INTEGER, R, from an UNSIGNED vector, L. -- Id: A.12 function "-" ( L: NATURAL; R: UNSIGNED) return UNSIGNED; -- Result subtype: UNSIGNED(R'LENGTH-1 downto 0). -- Result: Subtracts an UNSIGNED vector, R, from a non-negative INTEGER, L. -- Id: A.13 function "-" ( L: SIGNED; R: INTEGER) return SIGNED; -- Result subtype: SIGNED (L'LENGTH-1 downto 0). -- Result: Subtracts an INTEGER, R, from a SIGNED vector, L. -- Id: A.14 function "-" ( L: INTEGER; R: SIGNED) return SIGNED; -- Result subtype: SIGNED(R'LENGTH-1 downto 0). -- Result: Subtracts a SIGNED vector, R, from an INTEGER, L. --============================================================================ -- Id: A.15 function "*" (L,R: UNSIGNED ) return UNSIGNED; -- Result subtype: UNSIGNED((L'length+R'length-1) downto 0). -- Result: Performs the multiplication operation on two UNSIGNED vectors -- that may possibly be of different lengths. -- Id: A.16 function "*" ( L,R: SIGNED) return SIGNED; -- Result subtype: SIGNED((L'length+R'length-1) downto 0) -- Result: Multiplies two SIGNED vectors that may possibly be of -- different lengths. -- Id: A.17 function "*" ( L: UNSIGNED; R: NATURAL) return UNSIGNED; -- Result subtype: UNSIGNED((L'length+L'length-1) downto 0). -- Result: Multiplies an UNSIGNED vector, L, with a non-negative -- INTEGER, R. R is converted to an UNSIGNED vector of -- SIZE L'length before multiplication. -- Id: A.18 function "*" ( L: NATURAL; R: UNSIGNED) return UNSIGNED; -- Result subtype: UNSIGNED((R'length+R'length-1) downto 0). -- Result: Multiplies an UNSIGNED vector, R, with a non-negative -- INTEGER, L. L is converted to an UNSIGNED vector of -- SIZE R'length before multiplication. -- Id: A.19 function "*" ( L: SIGNED; R: INTEGER) return SIGNED; -- Result subtype: SIGNED((L'length+L'length-1) downto 0) -- Result: Multiplies a SIGNED vector, L, with an INTEGER, R. R is -- converted to a SIGNED vector of SIZE L'length before -- multiplication. -- Id: A.20 function "*" ( L: INTEGER; R: SIGNED) return SIGNED; -- Result subtype: SIGNED((R'length+R'length-1) downto 0) -- Result: Multiplies a SIGNED vector, R, with an INTEGER, L. L is -- converted to a SIGNED vector of SIZE R'length before -- multiplication. --============================================================================ -- -- NOTE: If second argument is zero for "/" operator, a severity level -- of ERROR is issued. -- Id: A.21 function "/" (L,R: UNSIGNED ) return UNSIGNED; -- Result subtype: UNSIGNED (L'LENGTH-1 downto 0) -- Result: Divides an UNSIGNED vector, L, by another UNSIGNED vector, R. -- Id: A.22 function "/" ( L,R: SIGNED) return SIGNED; -- Result subtype: SIGNED (L'LENGTH-1 downto 0) -- Result: Divides an SIGNED vector, L, by another SIGNED vector, R. -- Id: A.23 function "/" ( L: UNSIGNED; R: NATURAL) return UNSIGNED; -- Result subtype: UNSIGNED (L'LENGTH-1 downto 0) -- Result: Divides an UNSIGNED vector, L, by a non-negative INTEGER, R. -- If NO_OF_BITS(R) > L'LENGTH, then R is truncated to L'LENGTH. -- Id: A.24 function "/" ( L: NATURAL; R: UNSIGNED) return UNSIGNED; -- Result subtype: UNSIGNED (R'LENGTH-1 downto 0) -- Result: Divides a non-negative INTEGER, L, by an UNSIGNED vector, R. -- If NO_OF_BITS(L) > R'LENGTH, then L is truncated to R'LENGTH. -- Id: A.25 function "/" ( L: SIGNED; R: INTEGER) return SIGNED; -- Result subtype: SIGNED (L'LENGTH-1 downto 0) -- Result: Divides a SIGNED vector, L, by an INTEGER, R. -- If NO_OF_BITS(R) > L'LENGTH, then R is truncated to L'LENGTH. -- Id: A.26 function "/" ( L: INTEGER; R: SIGNED) return SIGNED; -- Result subtype: SIGNED (R'LENGTH-1 downto 0) -- Result: Divides an INTEGER, L, by a SIGNED vector, R. -- If NO_OF_BITS(L) > R'LENGTH, then L is truncated to R'LENGTH. --============================================================================ -- -- NOTE: If second argument is zero for "rem" operator, a severity level -- of ERROR is issued. -- Id: A.27 function "rem" (L,R: UNSIGNED ) return UNSIGNED; -- Result subtype: UNSIGNED(L'LENGTH-1 downto 0) -- Result: Computes "L rem R" where L and R are UNSIGNED vectors. -- Id: A.28 function "rem" ( L,R: SIGNED) return SIGNED; -- Result subtype: SIGNED(L'LENGTH-1 downto 0) -- Result: Computes "L rem R" where L and R are SIGNED vectors. -- Id: A.29 function "rem" ( L: UNSIGNED; R: NATURAL) return UNSIGNED; -- Result subtype: UNSIGNED(L'LENGTH-1 downto 0) -- Result: Computes "L rem R" where L is an UNSIGNED vector and R is a -- non-negative INTEGER. -- If NO_OF_BITS(R) > L'LENGTH, then R is truncated to L'LENGTH. -- Id: A.30 function "rem" ( L: NATURAL; R: UNSIGNED) return UNSIGNED; -- Result subtype: UNSIGNED(R'LENGTH-1 downto 0) -- Result: Computes "L rem R" where R is an UNSIGNED vector and L is a -- non-negative INTEGER. -- If NO_OF_BITS(L) > R'LENGTH, then L is truncated to R'LENGTH. -- Id: A.31 function "rem" ( L: SIGNED; R: INTEGER) return SIGNED; -- Result subtype: SIGNED(L'LENGTH-1 downto 0) -- Result: Computes "L rem R" where L is SIGNED vector and R is an INTEGER. -- If NO_OF_BITS(R) > L'LENGTH, then R is truncated to L'LENGTH. -- Id: A.32 function "rem" ( L: INTEGER; R: SIGNED) return SIGNED; -- Result subtype: SIGNED(R'LENGTH-1 downto 0) -- Result: Computes "L rem R" where R is SIGNED vector and L is an INTEGER. -- If NO_OF_BITS(L) > R'LENGTH, then L is truncated to R'LENGTH. --============================================================================ -- -- NOTE: If second argument is zero for "mod" operator, a severity level -- of ERROR is issued. -- Id: A.33 function "mod" (L,R: UNSIGNED ) return UNSIGNED; -- Result subtype: UNSIGNED(L'LENGTH-1 downto 0) -- Result: Computes "L mod R" where L and R are UNSIGNED vectors. -- Id: A.34 function "mod" ( L,R: SIGNED) return SIGNED; -- Result subtype: SIGNED(L'LENGTH-1 downto 0) -- Result: Computes "L mod R" where L and R are SIGNED vectors. -- Id: A.35 function "mod" ( L: UNSIGNED; R: NATURAL) return UNSIGNED; -- Result subtype: UNSIGNED(L'LENGTH-1 downto 0) -- Result: Computes "L mod R" where L is an UNSIGNED vector and R -- is a non-negative INTEGER. -- If NO_OF_BITS(R) > L'LENGTH, then R is truncated to L'LENGTH. -- Id: A.36 function "mod" ( L: NATURAL; R: UNSIGNED) return UNSIGNED; -- Result subtype: UNSIGNED(R'LENGTH-1 downto 0) -- Result: Computes "L mod R" where R is an UNSIGNED vector and L -- is a non-negative INTEGER. -- If NO_OF_BITS(L) > R'LENGTH, then L is truncated to R'LENGTH. -- Id: A.37 function "mod" ( L: SIGNED; R: INTEGER) return SIGNED; -- Result subtype: SIGNED(L'LENGTH-1 downto 0) -- Result: Computes "L mod R" where L is a SIGNED vector and -- R is an INTEGER. -- If NO_OF_BITS(R) > L'LENGTH, then R is truncated to L'LENGTH. -- Id: A.38 function "mod" ( L: INTEGER; R: SIGNED) return SIGNED; -- Result subtype: SIGNED(R'LENGTH-1 downto 0) -- Result: Computes "L mod R" where L is an INTEGER and -- R is a SIGNED vector. -- If NO_OF_BITS(L) > R'LENGTH, then L is truncated to R'LENGTH. --============================================================================ -- Comparison Operators --============================================================================ -- Id: C.1 function ">" (L,R: UNSIGNED ) return BOOLEAN; -- Result subtype: BOOLEAN -- Result: Computes "L > R" where L and R are UNSIGNED vectors possibly -- of different lengths. -- Id: C.2 function ">" ( L,R: SIGNED) return BOOLEAN; -- Result subtype: BOOLEAN -- Result: Computes "L > R" where L and R are SIGNED vectors possibly -- of different lengths. -- Id: C.3 function ">" ( L: NATURAL; R: UNSIGNED) return BOOLEAN; -- Result subtype: BOOLEAN -- Result: Computes "L > R" where L is a non-negative INTEGER and -- R is an UNSIGNED vector. -- Id: C.4 function ">" ( L: INTEGER; R: SIGNED) return BOOLEAN; -- Result subtype: BOOLEAN -- Result: Computes "L > R" where L is a INTEGER and -- R is a SIGNED vector. -- Id: C.5 function ">" ( L: UNSIGNED; R: NATURAL) return BOOLEAN; -- Result subtype: BOOLEAN -- Result: Computes "L > R" where L is an UNSIGNED vector and -- R is a non-negative INTEGER. -- Id: C.6 function ">" ( L: SIGNED; R: INTEGER) return BOOLEAN; -- Result subtype: BOOLEAN -- Result: Computes "L > R" where L is a SIGNED vector and -- R is a INTEGER. --============================================================================ -- Id: C.7 function "<" (L,R: UNSIGNED ) return BOOLEAN; -- Result subtype: BOOLEAN -- Result: Computes "L < R" where L and R are UNSIGNED vectors possibly -- of different lengths. -- Id: C.8 function "<" ( L,R: SIGNED) return BOOLEAN; -- Result subtype: BOOLEAN -- Result: Computes "L < R" where L and R are SIGNED vectors possibly -- of different lengths. -- Id: C.9 function "<" ( L: NATURAL; R: UNSIGNED) return BOOLEAN; -- Result subtype: BOOLEAN -- Result: Computes "L < R" where L is a non-negative INTEGER and -- R is an UNSIGNED vector. -- Id: C.10 function "<" ( L: INTEGER; R: SIGNED) return BOOLEAN; -- Result subtype: BOOLEAN -- Result: Computes "L < R" where L is an INTEGER and -- R is a SIGNED vector. -- Id: C.11 function "<" ( L: UNSIGNED; R: NATURAL) return BOOLEAN; -- Result subtype: BOOLEAN -- Result: Computes "L < R" where L is an UNSIGNED vector and -- R is a non-negative INTEGER. -- Id: C.12 function "<" ( L: SIGNED; R: INTEGER) return BOOLEAN; -- Result subtype: BOOLEAN -- Result: Computes "L < R" where L is a SIGNED vector and -- R is an INTEGER. --============================================================================ -- Id: C.13 function "<=" (L,R: UNSIGNED ) return BOOLEAN; -- Result subtype: BOOLEAN -- Result: Computes "L <= R" where L and R are UNSIGNED vectors possibly -- of different lengths. -- Id: C.14 function "<=" ( L,R: SIGNED) return BOOLEAN; -- Result subtype: BOOLEAN -- Result: Computes "L <= R" where L and R are SIGNED vectors possibly -- of different lengths. -- Id: C.15 function "<=" ( L: NATURAL; R: UNSIGNED) return BOOLEAN; -- Result subtype: BOOLEAN -- Result: Computes "L <= R" where L is a non-negative INTEGER and -- R is an UNSIGNED vector. -- Id: C.16 function "<=" ( L: INTEGER; R: SIGNED) return BOOLEAN; -- Result subtype: BOOLEAN -- Result: Computes "L <= R" where L is an INTEGER and -- R is a SIGNED vector. -- Id: C.17 function "<=" ( L: UNSIGNED; R: NATURAL) return BOOLEAN; -- Result subtype: BOOLEAN -- Result: Computes "L <= R" where L is an UNSIGNED vector and -- R is a non-negative INTEGER. -- Id: C.18 function "<=" ( L: SIGNED; R: INTEGER) return BOOLEAN; -- Result subtype: BOOLEAN -- Result: Computes "L <= R" where L is a SIGNED vector and -- R is an INTEGER. --============================================================================ -- Id: C.19 function ">=" (L,R: UNSIGNED ) return BOOLEAN; -- Result subtype: BOOLEAN -- Result: Computes "L >= R" where L and R are UNSIGNED vectors possibly -- of different lengths. -- Id: C.20 function ">=" ( L,R: SIGNED) return BOOLEAN; -- Result subtype: BOOLEAN -- Result: Computes "L >= R" where L and R are SIGNED vectors possibly -- of different lengths. -- Id: C.21 function ">=" ( L: NATURAL; R: UNSIGNED) return BOOLEAN; -- Result subtype: BOOLEAN -- Result: Computes "L >= R" where L is a non-negative INTEGER and -- R is an UNSIGNED vector. -- Id: C.22 function ">=" ( L: INTEGER; R: SIGNED) return BOOLEAN; -- Result subtype: BOOLEAN -- Result: Computes "L >= R" where L is an INTEGER and -- R is a SIGNED vector. -- Id: C.23 function ">=" ( L: UNSIGNED; R: NATURAL) return BOOLEAN; -- Result subtype: BOOLEAN -- Result: Computes "L >= R" where L is an UNSIGNED vector and -- R is a non-negative INTEGER. -- Id: C.24 function ">=" ( L: SIGNED; R: INTEGER) return BOOLEAN; -- Result subtype: BOOLEAN -- Result: Computes "L >= R" where L is a SIGNED vector and -- R is an INTEGER. --============================================================================ -- Id: C.25 function "=" (L,R: UNSIGNED ) return BOOLEAN; -- Result subtype: BOOLEAN -- Result: Computes "L = R" where L and R are UNSIGNED vectors possibly -- of different lengths. -- Id: C.26 function "=" ( L,R: SIGNED) return BOOLEAN; -- Result subtype: BOOLEAN -- Result: Computes "L = R" where L and R are SIGNED vectors possibly -- of different lengths. -- Id: C.27 function "=" ( L: NATURAL; R: UNSIGNED) return BOOLEAN; -- Result subtype: BOOLEAN -- Result: Computes "L = R" where L is a non-negative INTEGER and -- R is an UNSIGNED vector. -- Id: C.28 function "=" ( L: INTEGER; R: SIGNED) return BOOLEAN; -- Result subtype: BOOLEAN -- Result: Computes "L = R" where L is an INTEGER and -- R is a SIGNED vector. -- Id: C.29 function "=" ( L: UNSIGNED; R: NATURAL) return BOOLEAN; -- Result subtype: BOOLEAN -- Result: Computes "L = R" where L is an UNSIGNED vector and -- R is a non-negative INTEGER. -- Id: C.30 function "=" ( L: SIGNED; R: INTEGER) return BOOLEAN; -- Result subtype: BOOLEAN -- Result: Computes "L = R" where L is a SIGNED vector and -- R is an INTEGER. --============================================================================ -- Id: C.31 function "/=" (L,R: UNSIGNED ) return BOOLEAN; -- Result subtype: BOOLEAN -- Result: Computes "L /= R" where L and R are UNSIGNED vectors possibly -- of different lengths. -- Id: C.32 function "/=" ( L,R: SIGNED) return BOOLEAN; -- Result subtype: BOOLEAN -- Result: Computes "L /= R" where L and R are SIGNED vectors possibly -- of different lengths. -- Id: C.33 function "/=" ( L: NATURAL; R: UNSIGNED) return BOOLEAN; -- Result subtype: BOOLEAN -- Result: Computes "L /= R" where L is a non-negative INTEGER and -- R is an UNSIGNED vector. -- Id: C.34 function "/=" ( L: INTEGER; R: SIGNED) return BOOLEAN; -- Result subtype: BOOLEAN -- Result: Computes "L /= R" where L is an INTEGER and -- R is a SIGNED vector. -- Id: C.35 function "/=" ( L: UNSIGNED; R: NATURAL) return BOOLEAN; -- Result subtype: BOOLEAN -- Result: Computes "L /= R" where L is an UNSIGNED vector and -- R is a non-negative INTEGER. -- Id: C.36 function "/=" ( L: SIGNED; R: INTEGER) return BOOLEAN; -- Result subtype: BOOLEAN -- Result: Computes "L /= R" where L is a SIGNED vector and -- R is an INTEGER. --============================================================================ -- Shift and Rotate Functions --============================================================================ -- Id: S.1 function shift_left ( ARG: UNSIGNED; COUNT: NATURAL) return UNSIGNED; -- Result subtype: UNSIGNED (ARG'LENGTH-1 downto 0) -- Result: Performs a shift-left on an UNSIGNED vector COUNT times. -- The vacated positions are filled with Bit '0'. -- The COUNT leftmost bits are lost. -- Id: S.2 function shift_right ( ARG: UNSIGNED; COUNT: NATURAL) return UNSIGNED; -- Result subtype: UNSIGNED (ARG'LENGTH-1 downto 0) -- Result: Performs a shift-right on an UNSIGNED vector COUNT times. -- The vacated positions are filled with Bit '0'. -- The COUNT rightmost bits are lost. -- Id: S.3 function shift_left ( ARG: SIGNED; COUNT: NATURAL) return SIGNED; -- Result subtype: SIGNED (ARG'LENGTH-1 downto 0) -- Result: Performs a shift-left on a SIGNED vector COUNT times. -- All bits of ARG, except ARG'LEFT, are shifted left COUNT times. -- The vacated positions are filled with Bit '0'. -- The COUNT leftmost bits, except ARG'LEFT, are lost. -- Id: S.4 function shift_right ( ARG: SIGNED; COUNT: NATURAL) return SIGNED; -- Result subtype: SIGNED (ARG'LENGTH-1 downto 0) -- Result: Performs a shift-right on a SIGNED vector COUNT times. -- The vacated positions are filled with the leftmost bit,ARG'LEFT. -- The COUNT rightmost bits are lost. --============================================================================ --============================================================================ -- Id: S.5 function rotate_left ( ARG: UNSIGNED; COUNT: NATURAL) return UNSIGNED; -- Result subtype: UNSIGNED (ARG'LENGTH-1 downto 0) -- Result: Performs a rotate_left of an UNSIGNED vector COUNT times. -- Id: S.6 function rotate_right ( ARG: UNSIGNED; COUNT: NATURAL) return UNSIGNED; -- Result subtype: UNSIGNED (ARG'LENGTH-1 downto 0) -- Result: Performs a rotate_right of an UNSIGNED vector COUNT times. -- Id: S.7 function rotate_left ( ARG: SIGNED; COUNT: NATURAL) return SIGNED; -- Result subtype: SIGNED (ARG'LENGTH-1 downto 0) -- Result: Performs a logical rotate-left of a SIGNED -- vector COUNT times. -- Id: S.8 function rotate_right ( ARG: SIGNED; COUNT: NATURAL) return SIGNED; -- Result subtype: SIGNED (ARG'LENGTH-1 downto 0) -- Result: Performs a logical rotate-right of a SIGNED -- vector COUNT times. --============================================================================ -- RESIZE Functions --============================================================================ -- Id: R.1 function RESIZE ( ARG: SIGNED; NEW_SIZE: NATURAL) return SIGNED; -- Result subtype: SIGNED(ARG'LENGTH-1 downto 0) -- Result: ReSIZEs the SIGNED vector ARG to the specified SIZE. -- To create a larger vector, the new [leftmost] bit positions -- are filled with the sign bit (ARG'LEFT). When truncating, -- the sign bit is retained along with the rightmost part. -- Id: R.2 function RESIZE ( ARG: UNSIGNED; NEW_SIZE: NATURAL) return UNSIGNED; -- Result subtype: UNSIGNED(ARG'LENGTH-1 downto 0) -- Result: ReSIZEs the SIGNED vector ARG to the specified SIZE. -- To create a larger vector, the new [leftmost] bit positions -- are filled with '0'. When truncating, the leftmost bits -- are dropped. --============================================================================ -- Conversion Functions --============================================================================ -- Id: D.1 function TO_INTEGER ( ARG: UNSIGNED) return NATURAL; -- Result subtype: NATURAL. Value cannot be negative since parameter is an -- UNSIGNED vector. -- Result: Converts the UNSIGNED vector to an INTEGER. -- Id: D.2 function TO_INTEGER ( ARG: SIGNED) return INTEGER; -- Result subtype: INTEGER -- Result: Converts a SIGNED vector to an INTEGER. -- Id: D.3 function TO_UNSIGNED ( ARG,SIZE: NATURAL) return UNSIGNED; -- Result subtype: UNSIGNED (SIZE-1 downto 0) -- Result: Converts a non-negative INTEGER to an UNSIGNED vector with -- the specified SIZE. -- Id: D.4 function TO_SIGNED ( ARG: INTEGER; SIZE: NATURAL) return SIGNED; -- Result subtype: SIGNED (SIZE-1 downto 0) -- Result: Converts an INTEGER to a SIGNED vector of the specified SIZE. -- Id: D.5 function TO_UNSIGNED ( ARG: STD_LOGIC_VECTOR) return UNSIGNED; -- Result subtype: UNSIGNED, same range as input ARG -- Result: Converts STD_LOGIC_VECTOR to UNSIGNED. -- Id: D.6 function TO_SIGNED ( ARG: STD_LOGIC_VECTOR) return SIGNED; -- Result subtype: SIGNED, same range as input ARG -- Result: Converts STD_LOGIC_VECTOR to SIGNED. -- Id: D.7 function TO_STDLOGICVECTOR ( ARG: UNSIGNED) return STD_LOGIC_VECTOR; -- Result subtype: STD_LOGIC_VECTOR, same range as input ARG -- Result: Converts UNSIGNED to STD_LOGIC_VECTOR. -- Id: D.8 function TO_STDLOGICVECTOR ( ARG: SIGNED) return STD_LOGIC_VECTOR; -- Result subtype: STD_LOGIC_VECTOR, same range as input ARG -- Result: Converts SIGNED to STD_LOGIC_VECTOR. --============================================================================ -- Logical Operators --============================================================================ -- Id: L.1 function "not" ( L: UNSIGNED ) return UNSIGNED; -- Result subtype: UNSIGNED, same range as input L -- Result: Termwise inversion -- Id: L.2 function "and" ( L,R: UNSIGNED ) return UNSIGNED; -- Result subtype: UNSIGNED, same range as input L -- Result: Vector AND operation -- Id: L.3 function "or" ( L,R: UNSIGNED ) return UNSIGNED; -- Result subtype: UNSIGNED, same range as input L -- Result: Vector OR operation -- Id: L.4 function "nand" ( L,R: UNSIGNED ) return UNSIGNED; -- Result subtype: UNSIGNED, same range as input L -- Result: Vector NAND operation -- Id: L.5 function "nor" ( L,R: UNSIGNED ) return UNSIGNED; -- Result subtype: UNSIGNED, same range as input L -- Result: Vector NOR operation -- Id: L.6 function "xor" ( L,R: UNSIGNED ) return UNSIGNED; -- Result subtype: UNSIGNED, same range as input L -- Result: Vector XOR operation -- ----------------------------------------------------------------------- -- Note : The declaration and implementation of the "xnor" function is -- specifically commented until at which time the VHDL language has been -- officially adopted as containing such a function. At such a point, -- the following comments may be removed along with this notice without -- further "official" ballotting of this 1076.3 package. It is -- the intent of this effort to provide such a function once it becomes -- available in the VHDL standard. -- ----------------------------------------------------------------------- -- Id: L.7 -- function "xnor" ( L,R: UNSIGNED ) return UNSIGNED; -- Result subtype: UNSIGNED, same range as input L -- Result: Vector XNOR operation -- Id: L.8 function "not" ( L: SIGNED) return SIGNED; -- Result subtype: SIGNED, same range as input L -- Result: Termwise inversion -- Id: L.9 function "and" ( L,R: SIGNED ) return SIGNED; -- Result subtype: SIGNED, same range as input L -- Result: Vector AND operation -- Id: L.10 function "or" ( L,R: SIGNED ) return SIGNED; -- Result subtype: SIGNED, same range as input L -- Result: Vector OR operation -- Id: L.11 function "nand" ( L,R: SIGNED ) return SIGNED; -- Result subtype: SIGNED, same range as input L -- Result: Vector NAND operation -- Id: L.12 function "nor" ( L,R: SIGNED ) return SIGNED; -- Result subtype: SIGNED, same range as input L -- Result: Vector NOR operation -- Id: L.13 function "xor" ( L,R: SIGNED ) return SIGNED; -- Result subtype: SIGNED, same range as input L -- Result: Vector XOR operation -- ----------------------------------------------------------------------- -- Note : The declaration and implementation of the "xnor" function is -- specifically commented until at which time the VHDL language has been -- officially adopted as containing such a function. At such a point, -- the following comments may be removed along with this notice without -- further "official" ballotting of this 1076.3 package. It is -- the intent of this effort to provide such a function once it becomes -- available in the VHDL standard. -- ----------------------------------------------------------------------- -- Id: L.14 -- function "xnor" ( L,R: SIGNED ) return SIGNED; -- Result subtype: SIGNED, same range as input L -- Result: Vector XNOR operation --============================================================================ -- Match Functions --============================================================================ -- Id: M.1 function STD_MATCH (L, R: STD_ULOGIC) return BOOLEAN; -- Result: terms compared per STD_LOGIC_1164 intent -- Id: M.2 function STD_MATCH (L, R: STD_LOGIC_VECTOR) return BOOLEAN; -- Result: termwise comparison per STD_LOGIC_1164 intent end numeric_std; --============================================================================= --======================= Package Body =============================== --============================================================================= Package body numeric_std is -- null range array constants constant NAU : UNSIGNED (0 downto 1) := (others => '0'); constant NAS : SIGNED (0 downto 1) := (others => '0'); -- implementation controls constant NO_WARNING : boolean := FALSE; -- default to emit warnings --=========================Local Subprograms================================= function MAX(LEFT, RIGHT: INTEGER) return INTEGER is begin if LEFT > RIGHT then return LEFT; else return RIGHT; end if; end; function MIN(LEFT, RIGHT: INTEGER) return INTEGER is begin if LEFT < RIGHT then return LEFT; else return RIGHT; end if; end; function Signed_NUM_BITS ( ARG: INTEGER) return natural is variable nBits: natural; variable N: natural; begin if ARG>=0 then N:=ARG; else N:=-(ARG+1); end if; nBits:=1; while N>0 loop nBits:=nBits+1; N:= N / 2; end loop; return nBits; end; function UNSIGNED_NUM_BITS (ARG: natural) return natural is variable nBits: natural; variable N: natural; begin N:=ARG; nBits:=1; while N>1 loop nBits:=nBits+1; N:= N / 2; end loop; return nBits; end; ------------------------------------------------------------------------ -- this internal function computes the addition of two UNSIGNED -- with input CARRY -- * the two arguments are of the same length function ADD_UNSIGNED ( L,R: UNSIGNED; C: STD_LOGIC ) return UNSIGNED is constant L_left:INTEGER:= L'length-1; alias XL: UNSIGNED(L_left downto 0) is L; alias XR: UNSIGNED(L_left downto 0) is R; variable RESULT: UNSIGNED(L_left downto 0); variable CBIT : STD_LOGIC:= C; begin for i in 0 to L_left loop RESULT(i) := CBIT xor XL(i) xor XR(i); CBIT := (CBIT and XL(i)) or (CBIT and XR(i)) or (XL(i) and XR(i)); end loop; return RESULT; end ADD_UNSIGNED; -- this internal function computes the addition of two SIGNED -- with input CARRY -- * the two arguments are of the same length function ADD_SIGNED ( L,R: SIGNED; C: STD_LOGIC ) return SIGNED is constant L_left:INTEGER:= L'length-1; alias XL: SIGNED(L_left downto 0) is L; alias XR: SIGNED(L_left downto 0) is R; variable RESULT: SIGNED(L_left downto 0); variable CBIT: STD_LOGIC:= C; begin for i in 0 to L_left loop RESULT(i) := CBIT xor XL(i) xor XR(i); CBIT := (CBIT and XL(i)) or (CBIT and XR(i)) or (XL(i) and XR(i)); end loop; return RESULT; end ADD_SIGNED; ------------------------------------------------------------------------ -- this internal procedure computes UNSIGNED division -- giving the quotient and remainder. procedure divMod (num, XDENOM: UNSIGNED; xquot, xremain: out UNSIGNED) is variable TEMP: UNSIGNED(num'length-1 downto 0); variable quot: UNSIGNED(MAX(num'length,XDENOM'length)-1 downto 0); variable diff: UNSIGNED(XDENOM'length downto 0); alias DENOM : UNSIGNED (XDENOM'length-1 downto 0) is XDENOM; variable CARRY: STD_LOGIC; variable TOPBIT: natural; variable isZero: boolean; begin isZero:=TRUE; for j in XDENOM'range loop CARRY:=DENOM(j); if CARRY/='0' then isZero:=FALSE; end if; end loop; assert not isZero report "DIV,MOD,or REM by zero" severity error; TEMP:=num; quot:= (others =>'0'); TOPBIT:=0; for j in DENOM'range loop if DENOM(j)='1' then TOPBIT:=j; exit; end if; end loop; CARRY:='0'; for j in num'length-(TOPBIT+1) downto 0 loop -- lexical ordering works okay for this comparison, no overloaded -- function is needed. if CARRY&TEMP(TOPBIT+j downto j) >= "0"&DENOM(TOPBIT downto 0) then diff(TOPBIT+1 downto 0) := (CARRY&TEMP(TOPBIT+j downto j)) -("0"&DENOM(TOPBIT downto 0)); assert diff(TOPBIT+1)='0' report "internal error in the division algorithm" severity error; CARRY:=diff(TOPBIT); if TOPBIT+j+1<=TEMP'left then TEMP(TOPBIT+j+1):='0'; end if; TEMP(TOPBIT+j downto j):=diff(TOPBIT downto 0); quot(j):='1'; else assert CARRY='0' report "internal error in the division algorithm" severity error; CARRY:=TEMP(TOPBIT+j); end if; end loop; xquot:=quot(num'length-1 downto 0); xremain:=TEMP(num'length-1 downto 0); end divMod; -----------------Local Subprograms - shift/rotate ops------------------------- function XSLL(ARG: STD_LOGIC_VECTOR; COUNT: NATURAL) return STD_LOGIC_VECTOR is constant ARG_L:INTEGER:= ARG'length-1; alias XARG: STD_LOGIC_VECTOR(ARG_L downto 0) is ARG; variable RESULT: STD_LOGIC_VECTOR(ARG_L downto 0) := (others=>'0'); begin if COUNT <= ARG_L then RESULT(ARG_L downto COUNT):=XARG(ARG_L-COUNT downto 0); end if; return RESULT; end; function XSRL(ARG: STD_LOGIC_VECTOR; COUNT: NATURAL) return STD_LOGIC_VECTOR is constant ARG_L:INTEGER:= ARG'length-1; alias XARG: STD_LOGIC_VECTOR(ARG_L downto 0) is ARG; variable RESULT: STD_LOGIC_VECTOR(ARG_L downto 0) := (others=>'0'); begin if COUNT <= ARG_L then RESULT(ARG_L-COUNT downto 0):=XARG(ARG_L downto COUNT); end if; return RESULT; end; function XSRA(ARG: STD_LOGIC_VECTOR; COUNT: NATURAL) return STD_LOGIC_VECTOR is constant ARG_L:INTEGER:= ARG'length-1; alias XARG: STD_LOGIC_VECTOR(ARG_L downto 0) is ARG; variable RESULT: STD_LOGIC_VECTOR(ARG_L downto 0); variable XCOUNT: natural := COUNT; begin if ((ARG'length <= 1) or (xCOUNT = 0)) then return ARG; else if (XCOUNT > ARG_L) then xCOUNT:= ARG_L; end if; RESULT(ARG_L-XCOUNT downto 0):=XARG(ARG_L downto XCOUNT); RESULT(ARG_L downto (ARG_L - XCOUNT + 1)) := (others=>XARG(ARG_L)); end if; return RESULT; end; function XROL(ARG: STD_LOGIC_VECTOR; COUNT: NATURAL) return STD_LOGIC_VECTOR is constant ARG_L:INTEGER:= ARG'length-1; alias XARG: STD_LOGIC_VECTOR(ARG_L downto 0) is ARG; variable RESULT: STD_LOGIC_VECTOR(ARG_L downto 0) := XARG; variable COUNTM: INTEGER; begin COUNTM:= COUNT mod (ARG_L + 1); if COUNTM /= 0 then RESULT(ARG_L downto COUNTM):=XARG(ARG_L-COUNTM downto 0); RESULT(COUNTM-1 downto 0):=XARG(ARG_L downto ARG_L-COUNTM+1); end if; return RESULT; end; function XROR(ARG: STD_LOGIC_VECTOR; COUNT: NATURAL) return STD_LOGIC_VECTOR is constant ARG_L:INTEGER:= ARG'length-1; alias XARG: STD_LOGIC_VECTOR(ARG_L downto 0) is ARG; variable RESULT: STD_LOGIC_VECTOR(ARG_L downto 0) := XARG; variable COUNTM: INTEGER; begin COUNTM:= COUNT mod (ARG_L + 1); if COUNTM /= 0 then RESULT(ARG_L-COUNTM downto 0):=XARG(ARG_L downto COUNTM); RESULT(ARG_L downto ARG_L-COUNTM+1):=XARG(COUNTM-1 downto 0); end if; return RESULT; end; -----------------Local Subprograms - Relational ops-------------------------- -- -- General "=" for UNSIGNED vectors, same length -- function UNSIGNED_equal ( L,R: UNSIGNED) return BOOLEAN is begin return STD_LOGIC_VECTOR (L) = STD_LOGIC_VECTOR (R) ; end; -- -- General "=" for SIGNED vectors, same length -- function SIGNED_equal ( L,R: SIGNED) return BOOLEAN is begin return STD_LOGIC_VECTOR (L) = STD_LOGIC_VECTOR (R) ; end; -- -- General "<" for UNSIGNED vectors, same length -- function UNSIGNED_LESS ( L,R: UNSIGNED) return BOOLEAN is begin return STD_LOGIC_VECTOR (L) < STD_LOGIC_VECTOR (R) ; end UNSIGNED_LESS ; -- -- General "<" function for SIGNED vectors, same length -- function SIGNED_LESS ( L,R: SIGNED) return BOOLEAN is variable intern_l : SIGNED (0 to L'LENGTH-1); variable intern_r : SIGNED (0 to R'LENGTH-1); begin intern_l:=l; intern_r:=r; intern_l(0):=not intern_l(0); intern_r(0):=not intern_r(0); return STD_LOGIC_VECTOR (intern_L) < STD_LOGIC_VECTOR (intern_R) ; end; -- -- General "<=" function for UNSIGNED vectors, same length -- function UNSIGNED_LESS_OR_EQUAL ( L,R: UNSIGNED) return BOOLEAN is begin return STD_LOGIC_VECTOR (L) <= STD_LOGIC_VECTOR (R) ; end; -- -- General "<=" function for SIGNED vectors, same length -- function SIGNED_LESS_OR_EQUAL ( L,R: SIGNED) return BOOLEAN is -- Need aliasses to assure index direction variable intern_l : SIGNED (0 to L'LENGTH-1); variable intern_r : SIGNED (0 to R'LENGTH-1); begin intern_l:=l; intern_r:=r; intern_l(0):=not intern_l(0); intern_r(0):=not intern_r(0); return STD_LOGIC_VECTOR (intern_L) <= STD_LOGIC_VECTOR (intern_R) ; end; -- function TO_01 is used to convert vectors to the -- correct form for exported functions, -- and to report if there is an element which -- is not in (0,1,h,l). -- Assume the vector is normalized and non-null. -- The function is duplicated for SIGNED and UNSIGNED types. function TO_01(S : SIGNED ; xmap : STD_LOGIC:= '0') return SIGNED is variable RESULT: SIGNED(S'length-1 downto 0); variable bad_element : boolean := FALSE; alias xs : SIGNED(s'length-1 downto 0) is S; begin for i in RESULT'range loop case xs(i) is when '0' | 'L' => RESULT(i):='0'; when '1' | 'H' => RESULT(i):='1'; when others => bad_element := TRUE; end case; end loop; if bad_element then assert NO_WARNING report "numeric_std.TO_01: Array Element not in {0,1,H,L}" severity warning; for i in RESULT'range loop RESULT(i) := xmap; -- standard fixup end loop; end if; return RESULT; end TO_01; function TO_01(S : UNSIGNED ; xmap : STD_LOGIC:= '0') return UNSIGNED is variable RESULT: UNSIGNED(S'length-1 downto 0); variable bad_element : boolean := FALSE; alias xs : UNSIGNED(S'length-1 downto 0) is S; begin for i in RESULT'range loop case xs(i) is when '0' | 'L' => RESULT(i):='0'; when '1' | 'H' => RESULT(i):='1'; when others => bad_element := TRUE; end case; end loop; if bad_element then assert NO_WARNING report "numeric_std.TO_01: Array Element not in {0,1,H,L}" severity warning; for i in RESULT'range loop RESULT(i) := xmap; -- standard fixup end loop; end if; return RESULT; end TO_01; --=========================Exported Functions================================= -- Id: A.1 function "abs" ( X : SIGNED) return SIGNED is constant ARG_LEFT:INTEGER:= X'length-1; alias XX : SIGNED(ARG_LEFT downto 0) is X; variable RESULT: SIGNED (ARG_LEFT downto 0); begin if X'length<1 then return NAS; end if; RESULT:=TO_01(xx,std_logic' ('X')); if (RESULT(RESULT'left)='X') then return RESULT; end if; if RESULT(RESULT'left) = '1' then RESULT:= -RESULT; end if; return RESULT; end; -- "abs" -- Id: A.2 function "-" ( ARG: SIGNED) return SIGNED is constant ARG_LEFT:INTEGER:= ARG'length-1; alias XARG: SIGNED(ARG_LEFT downto 0) is ARG; variable RESULT,XARG01 : SIGNED(ARG_LEFT downto 0); variable CBIT : STD_LOGIC:= '1'; begin if ARG'length<1 then return NAS; end if; XARG01 := TO_01(ARG,std_logic' ('X')); if (XARG01(XARG01'left)='X') then return XARG01; end if; for i in 0 to RESULT'left loop RESULT(i) := not(XARG01(i)) xor CBIT; CBIT := CBIT and not(XARG01(i)); end loop; return RESULT; end; -- "-" --============================================================================= -- Id: A.3 function "+" ( L,R: UNSIGNED ) return UNSIGNED is constant SIZE: NATURAL:= MAX (L'LENGTH, R'LENGTH) ; variable L01 : UNSIGNED(SIZE-1 downto 0); variable R01 : UNSIGNED(SIZE-1 downto 0); begin if ((L'length<1) or (R'length<1)) then return NAU; end if; L01 := TO_01(RESIZE(L,SIZE), 'X'); if (L01(L01'left)='X') then return L01; end if; R01 := TO_01(RESIZE(R,SIZE),std_logic' ('X')); if (R01(R01'left)='X') then return R01; end if; return ADD_UNSIGNED (L01, R01, std_logic' ('0')) ; end; -- Id: A.4 function "+" ( L,R: SIGNED ) return SIGNED is constant SIZE: NATURAL:= MAX (L'LENGTH, R'LENGTH) ; variable L01 : SIGNED(SIZE-1 downto 0); variable R01 : SIGNED(SIZE-1 downto 0); begin if ((L'length<1) or (R'length<1)) then return NAS; end if; L01 := TO_01(RESIZE(L,SIZE),std_logic' ('X')); if (L01(L01'left)='X') then return L01; end if; R01 := TO_01(RESIZE(R,SIZE),std_logic' ('X')); if (R01(R01'left)='X') then return R01; end if; return ADD_SIGNED (L01, R01, std_logic' ('0')) ; end; -- Id: A.5 function "+" ( L: UNSIGNED; R: NATURAL) return UNSIGNED is begin return L + TO_UNSIGNED( R , L'length); end; -- Id: A.6 function "+" ( L: NATURAL; R: UNSIGNED) return UNSIGNED is begin return TO_UNSIGNED( L , R'length) + R; end; -- Id: A.7 function "+" ( L: SIGNED; R: INTEGER) return SIGNED is begin return L + TO_SIGNED( R , L'length); end; -- Id: A.8 function "+" ( L: INTEGER; R: SIGNED) return SIGNED is begin return TO_SIGNED( L , R'length) + R; end; --============================================================================= -- Id: A.9 function "-" ( L,R: UNSIGNED) return UNSIGNED is constant SIZE: NATURAL:= MAX (L'LENGTH, R'LENGTH) ; variable L01 : UNSIGNED(SIZE-1 downto 0); variable R01 : UNSIGNED(SIZE-1 downto 0); begin if ((L'length<1) or (R'length<1)) then return NAU; end if; L01 := TO_01(RESIZE(L,SIZE),std_logic' ('X')); if (L01(L01'left)='X') then return L01; end if; R01 := TO_01(RESIZE(R,SIZE),std_logic' ('X')); if (R01(R01'left)='X') then return R01; end if; return ADD_UNSIGNED (L01,not(R01),std_logic' ('1')); end; -- Id: A.10 function "-" ( L,R: SIGNED) return SIGNED is constant SIZE: NATURAL:= MAX (L'LENGTH, R'LENGTH) ; variable L01 : SIGNED(SIZE-1 downto 0); variable R01 : SIGNED(SIZE-1 downto 0); begin if ((L'length<1) or (R'length<1)) then return NAS; end if; L01 := TO_01(RESIZE(L,SIZE),std_logic' ('X')); if (L01(L01'left)='X') then return L01; end if; R01 := TO_01(RESIZE(R,SIZE),std_logic' ('X')); if (R01(R01'left)='X') then return R01; end if; return ADD_SIGNED (L01,not(R01),std_logic' ('1')); end; -- Id: A.11 function "-" ( L: UNSIGNED; R: NATURAL) return UNSIGNED is begin return L - TO_UNSIGNED( R , L'length); end; -- Id: A.12 function "-" ( L: NATURAL; R: UNSIGNED) return UNSIGNED is begin return TO_UNSIGNED( L , R'length) - R; end; -- Id: A.13 function "-" ( L: SIGNED; R: INTEGER) return SIGNED is begin return L - TO_SIGNED( R , L'length); end; -- Id: A.14 function "-" ( L: INTEGER; R: SIGNED) return SIGNED is begin return TO_SIGNED( L , R'length) - R ; end; --============================================================================= -- Id: A.15 function "*" ( L,R: UNSIGNED) return UNSIGNED is constant L_left:INTEGER:= L'length-1; constant R_left:INTEGER:= R'length-1; alias xxl : UNSIGNED(L_left downto 0) is L; alias xxr : UNSIGNED(R_left downto 0) is R; variable xl : UNSIGNED(L_left downto 0); variable xr : UNSIGNED(R_left downto 0); variable RESULT: UNSIGNED((L'length+R'length-1) downto 0) :=(others=>'0'); variable adval : UNSIGNED((L'length+R'length-1) downto 0); begin if ((L'length<1) or (R'length<1)) then return NAU; end if; xl := TO_01(xxl,std_logic' ('X')); xr := TO_01(xxr,std_logic' ('X')); if ((xl(xl'left)='X') or (xr(xr'left)='X')) then RESULT:= (others=>'X'); return RESULT; end if; adval := RESIZE(xr,RESULT'length); for i in 0 to L_left loop if xl(i)='1' then RESULT:= RESULT + adval; end if; adval := shift_left(adval,1); end loop; return RESULT; end; -- Id: A.16 function "*" ( L,R: SIGNED) return SIGNED is constant L_left:INTEGER:= L'length-1; constant R_left:INTEGER:= R'length-1; alias xxl : SIGNED(L_left downto 0) is L; alias xxr : SIGNED(R_left downto 0) is R; variable xl : SIGNED(L_left downto 0); variable xr : SIGNED(R_left downto 0); variable RESULT: SIGNED((L'length+R'length-1) downto 0) :=(others=>'0'); variable adval : SIGNED((L'length+R'length-1) downto 0); variable invt : STD_LOGIC:= '0'; begin if ((L'length<1) or (R'length<1)) then return NAS; end if; xl := TO_01(xxl,std_logic' ('X')); xr := TO_01(xxr,std_logic' ('X')); if ((xl(xl'left)='X') or (xr(xr'left)='X')) then RESULT:= (others=>'X'); return RESULT; end if; adval := RESIZE(xr,RESULT'length); if xl(xl'left)='1' then adval := -(adval); invt := '1'; end if; for i in 0 to L_left loop if (invt xor xl(i))='1' then RESULT:= RESULT + adval; end if; adval := shift_left(adval,1); end loop; return RESULT; end; -- Id: A.17 function "*" ( L: UNSIGNED; R: NATURAL) return UNSIGNED is begin return L * TO_UNSIGNED( R , L'length); end; -- Id: A.18 function "*" ( L: NATURAL; R: UNSIGNED) return UNSIGNED is begin return TO_UNSIGNED( L , R'length) * R; end; -- Id: A.19 function "*" ( L: SIGNED; R: INTEGER) return SIGNED is begin return L * TO_SIGNED( R , L'length); end; -- Id: A.20 function "*" ( L: INTEGER; R: SIGNED) return SIGNED is begin return TO_SIGNED( L , R'length) * R ; end; --============================================================================= -- Id: A.21 function "/" ( L,R: UNSIGNED) return UNSIGNED is constant L_left:INTEGER:= L'length-1; constant R_left:INTEGER:= R'length-1; alias xxl : UNSIGNED(L_left downto 0) is L; alias xxr : UNSIGNED(R_left downto 0) is R; variable xl : UNSIGNED(L_left downto 0); variable xr : UNSIGNED(R_left downto 0); variable fquot,fremain : UNSIGNED(L'length-1 downto 0); begin if ((L'length<1) or (R'length<1)) then return NAU; end if; xl := TO_01(xxl,std_logic' ('X')); xr := TO_01(xxr,std_logic' ('X')); if ((xl(xl'left)='X') or (xr(xr'left)='X')) then fquot := (others=>'X'); return fquot; end if; divMod(xl,xr,fquot,fremain); return fquot; end; -- Id: A.22 function "/" ( L,R: SIGNED) return SIGNED is constant L_left:INTEGER:= L'length-1; constant R_left:INTEGER:= R'length-1; alias xxl : SIGNED(L_left downto 0) is L; alias xxr : SIGNED(R_left downto 0) is R; variable xl : SIGNED(L_left downto 0); variable xr : SIGNED(R_left downto 0); variable fquot,fremain : UNSIGNED(L'length-1 downto 0); variable xnum: UNSIGNED(L'length-1 downto 0); variable XDENOM: UNSIGNED(R'length-1 downto 0); variable qneg: boolean := FALSE; begin if ((L'length<1) or (R'length<1)) then return NAS; end if; xl := TO_01(xxl,std_logic' ('X')); xr := TO_01(xxr,std_logic' ('X')); if ((xl(xl'left)='X') or (xr(xr'left)='X')) then fquot := (others=>'X'); return SIGNED(fquot); end if; if xl(xl'left)='1' then xnum:=UNSIGNED(-xl); qNeg:=TRUE; else xnum:=UNSIGNED(xl); end if; if xr(xr'left)='1' then xdenom:=UNSIGNED(-xr); qNeg:=not qNeg; else xdenom:=UNSIGNED(xr); end if; divMod(xnum,XDENOM,fquot,fremain); if qNeg then fquot:="0"-fquot; end if; return SIGNED(fquot); end; -- Id: A.23 function "/" ( L : UNSIGNED; R : NATURAL) return UNSIGNED is constant R_Length : Natural := max(L'Length, unsigned_num_bits(R)); variable XR,Quot : unsigned (R_Length-1 downto 0); begin XR := TO_UNSIGNED(R, R_Length); Quot := L / XR; if R_Length>L'Length and Quot(0)/='X' and Quot(R_Length-1 downto L'Length)/=(R_Length-1 downto L'Length => '0') then ASSERT no_warning report "Numeric_std.""/"": Quotient Truncated" severity warning; end if; return Quot(L'Length-1 downto 0); end; -- Id: A.24 function "/" ( L : NATURAL; R : UNSIGNED) return UNSIGNED is constant L_Length : Natural := max(unsigned_num_bits(L), R'length); variable XL,Quot : UNSIGNED (L_Length-1 downto 0); begin XL := TO_UNSIGNED(L,L_LENGTH); QUOT := XL / R; if L_LENGTH>R'LENGTH and Quot(0)/='X' and QUOT(L_LENGTH-1 downto R'Length)/=(L_LENGTH-1 downto R'Length => '0') then ASSERT no_warning report "Numeric_std.""/"": Quotient Truncated" severity warning; end if; return Quot(R'Length-1 downto 0); end; -- Id: A.25 function "/" ( L : SIGNED; R : INTEGER ) return SIGNED is constant R_Length : Natural := max(L'Length, signed_num_bits(R)); variable XR,Quot : signed (R_Length-1 downto 0); begin XR := TO_SIGNED(R, R_Length); Quot := L / XR; if R_Length>L'Length and Quot(0)/='X' and Quot(R_Length-1 downto L'Length) /= (R_Length-1 downto L'Length => Quot(L'Length-1)) then ASSERT no_warning report "Numeric_std.""/"": Quotient Truncated" severity warning; end if; return Quot(L'Length-1 downto 0); end; -- Id: A.26 function "/" ( L : INTEGER; R : SIGNED) return SIGNED is constant L_Length : Natural := max(signed_num_bits(L), R'length); variable XL,Quot : SIGNED (L_Length-1 downto 0); begin XL := TO_SIGNED(L,L_LENGTH); QUOT := XL / R; if L_LENGTH>R'LENGTH and Quot(0)/='X' and QUOT(L_LENGTH-1 downto R'Length) /= (L_LENGTH-1 downto R'Length => Quot(R'Length-1)) then ASSERT no_warning report "Numeric_std.""/"": Quotient Truncated" severity warning; end if; return Quot(R'Length-1 downto 0); end; --============================================================================= -- Id: A.27 function "rem" ( L,R: UNSIGNED) return UNSIGNED is constant L_left:INTEGER:= L'length-1; constant R_left:INTEGER:= R'length-1; alias xxl : UNSIGNED(L_left downto 0) is L; alias xxr : UNSIGNED(R_left downto 0) is R; variable xl : UNSIGNED(L_left downto 0); variable xr : UNSIGNED(R_left downto 0); variable fquot,fremain : UNSIGNED(l'length-1 downto 0); begin if ((L'length<1) or (R'length<1)) then return NAU; end if; xl := TO_01(xxl,std_logic' ('X')); xr := TO_01(xxr,std_logic' ('X')); if ((xl(xl'left)='X') or (xr(xr'left)='X')) then fremain := (others=>'X'); return fremain; end if; divMod(xl,xr,fquot,fremain); return fremain; end; -- Id: A.28 function "rem" ( L,R: SIGNED) return SIGNED is constant L_left:INTEGER:= L'length-1; constant R_left:INTEGER:= R'length-1; alias xxl : SIGNED(L_left downto 0) is L; alias xxr : SIGNED(R_left downto 0) is R; variable fquot,fremain : UNSIGNED(l'length-1 downto 0); variable xnum: UNSIGNED(l'length-1 downto 0); variable XDENOM: UNSIGNED(r'length-1 downto 0); variable rneg: boolean := FALSE; begin if ((L'length<1) or (R'length<1)) then return NAS; end if; xnum := UNSIGNED(TO_01(xxl,std_logic' ('X'))); XDENOM := UNSIGNED(TO_01(xxr,std_logic' ('X'))); if ((xnum(xnum'left)='X') or (xdenom(xnum'left)='X')) then fremain := (others=>'X'); return SIGNED(fremain); end if; if xnum(xnum'left)='1' then xnum:=UNSIGNED(-SIGNED(xnum)); rNeg:=TRUE; else xNum:=UNSIGNED(xnum); end if; if XDENOM(XDENOM'left)='1' then XDENOM:=UNSIGNED(-SIGNED(XDENOM)); else XDENOM:=UNSIGNED(XDENOM); end if; divMod(xnum,XDENOM,fquot,fremain); if rNeg then fremain:="0"-fremain; end if; return SIGNED(fremain); end; -- Id: A.29 function "rem" ( L : UNSIGNED; R : NATURAL) return UNSIGNED is constant R_Length : Natural := max(L'Length, unsigned_num_bits(R)); variable XR,XRem : unsigned (R_Length-1 downto 0); begin XR := TO_UNSIGNED(R, R_Length); XRem := L rem XR; if R_Length>L'Length and XRem(0)/='X' and XRem(R_Length-1 downto L'Length) /= (R_Length-1 downto L'Length => '0') then ASSERT no_warning report "Numeric_std.""rem"": Remainder Truncated" severity warning; end if; return XRem(L'Length-1 downto 0); end; -- Id: A.30 function "rem" ( L : NATURAL; R : UNSIGNED) return UNSIGNED is constant L_Length : Natural := max(unsigned_num_bits(L), R'Length); variable XL,XRem : unsigned (L_Length-1 downto 0); begin XL := TO_UNSIGNED(L, L_Length); XRem := XL rem R; if L_Length>R'Length and XRem(0)/='X' and XRem(L_Length-1 downto R'Length) /= (L_Length-1 downto R'Length => '0') then ASSERT no_warning report "Numeric_std.""rem"": Remainder Truncated" severity warning; end if; return XRem(R'Length-1 downto 0); end; -- Id: A.31 function "rem" ( L : SIGNED; R : INTEGER ) return SIGNED is constant R_Length : Natural := max(L'Length, signed_num_bits(R)); variable XR,XRem : signed (R_Length-1 downto 0); begin XR := TO_SIGNED(R, R_Length); XRem := L rem XR; if R_Length>L'Length and XRem(0)/='X' and XRem(R_Length-1 downto L'Length) /= (R_Length-1 downto L'Length => XRem(L'Length-1)) then ASSERT no_warning report "Numeric_std.""rem"": Remainder Truncated" severity warning; end if; return XRem(L'Length-1 downto 0); end; -- Id: A.32 function "rem" ( L : INTEGER; R : SIGNED) return SIGNED is constant L_Length : Natural := max(signed_num_bits(L), R'Length); variable XL,XRem : signed (L_Length-1 downto 0); begin XL := TO_SIGNED(L, L_Length); XRem := XL rem R; if L_Length>R'Length and XRem(0)/='X' and XRem(L_Length-1 downto R'Length) /= (L_Length-1 downto R'Length => XRem(R'Length-1)) then ASSERT no_warning report "Numeric_std.""rem"": Remainder Truncated" severity warning; end if; return XRem(R'Length-1 downto 0); end; --============================================================================= -- Id: A.33 function "mod" ( L,R: UNSIGNED) return UNSIGNED is constant L_left:INTEGER:= L'length-1; constant R_left:INTEGER:= R'length-1; alias xxl : UNSIGNED(L_left downto 0) is L; alias xxr : UNSIGNED(R_left downto 0) is R; variable xl : UNSIGNED(L_left downto 0); variable xr : UNSIGNED(R_left downto 0); variable fquot,fremain : UNSIGNED(l'length-1 downto 0); begin if ((L'length<1) or (R'length<1)) then return NAU; end if; xl := TO_01(xxl,std_logic' ('X')); xr := TO_01(xxr,std_logic' ('X')); if ((xl(xl'left)='X') or (xr(xr'left)='X')) then fremain := (others=>'X'); return fremain; end if; divMod(xl,xr,fquot,fremain); return fremain; end; -- Id: A.34 function "mod" ( L,R: SIGNED) return SIGNED is constant L_left:INTEGER:= L'length-1; constant R_left:INTEGER:= R'length-1; alias xxl : SIGNED(L_left downto 0) is L; alias xxr : SIGNED(R_left downto 0) is R; variable xl : SIGNED(L_left downto 0); variable xr : SIGNED(R_left downto 0); variable fquot,fremain : UNSIGNED(l'length-1 downto 0); variable xnum: UNSIGNED(l'length-1 downto 0); variable XDENOM: UNSIGNED(r'length-1 downto 0); variable rneg: boolean := FALSE; begin if ((L'length<1) or (R'length<1)) then return NAS; end if; xl := TO_01(xxl,std_logic' ('X')); xr := TO_01(xxr,std_logic' ('X')); if ((xl(xl'left)='X') or (xr(xr'left)='X')) then fremain := (others=>'X'); return SIGNED(fremain); end if; if xl(xl'left)='1' then xnum:=UNSIGNED(-xl); else xNum:=UNSIGNED(xl); end if; if xr(xr'left)='1' then XDENOM:=UNSIGNED(-xr); rNeg:=TRUE; else XDENOM:=UNSIGNED(xr); end if; divMod(xnum,XDENOM,fquot,fremain); if rNeg and l(l'left)='1' then fremain:="0"-fremain; elsif rNeg then fremain:=fremain-XDENOM; elsif l(l'left)='1' then fremain:=XDENOM-fremain; end if; return SIGNED(fremain); end; -- Id: A.35 function "mod" ( L : UNSIGNED; R : NATURAL) return UNSIGNED is constant R_Length : Natural := max(L'Length, unsigned_num_bits(R)); variable XR,XRem : unsigned (R_Length-1 downto 0); begin XR := TO_UNSIGNED(R, R_Length); XRem := L mod XR; if R_Length>L'Length and XRem(0)/='X' and XRem(R_Length-1 downto L'Length) /= (R_Length-1 downto L'Length => '0') then ASSERT no_warning report "Numeric_std.""mod"": Modulus Truncated" severity warning; end if; return XRem(L'Length-1 downto 0); end; -- Id: A.36 function "mod" ( L : NATURAL; R : UNSIGNED) return UNSIGNED is constant L_Length : Natural := max(unsigned_num_bits(L), R'Length); variable XL,XRem : unsigned (L_Length-1 downto 0); begin XL := TO_UNSIGNED(L, L_Length); XRem := XL mod R; if L_Length>R'Length and XRem(0)/='X' and XRem(L_Length-1 downto R'Length) /= (L_Length-1 downto R'Length => '0') then ASSERT no_warning report "Numeric_std.""mod"": Modulus Truncated" severity warning; end if; return XRem(R'Length-1 downto 0); end; -- Id: A.37 function "mod" ( L : SIGNED; R : INTEGER ) return SIGNED is constant R_Length : Natural := max(L'Length, signed_num_bits(R)); variable XR,XRem : signed (R_Length-1 downto 0); begin XR := TO_SIGNED(R, R_Length); XRem := L mod XR; if R_Length>L'Length and XRem(0)/='X' and XRem(R_Length-1 downto L'Length) /= (R_Length-1 downto L'Length => XRem(L'Length-1)) then ASSERT no_warning report "Numeric_std.""mod"": Modulus Truncated" severity warning; end if; return XRem(L'Length-1 downto 0); end; -- Id: A.38 function "mod" ( L : INTEGER; R : SIGNED) return SIGNED is constant L_Length : Natural := max(signed_num_bits(L), R'Length); variable XL,XRem : signed (L_Length-1 downto 0); begin XL := TO_SIGNED(L, L_Length); XRem := XL mod R; if L_Length>R'Length and XRem(0)/='X' and XRem(L_Length-1 downto R'Length) /= (L_Length-1 downto R'Length => XRem(R'Length-1)) then ASSERT no_warning report "Numeric_std.""mod"": Modulus Truncated" severity warning; end if; return XRem(R'Length-1 downto 0); end; --============================================================================= -- Id: C.1 function ">" ( L,R: UNSIGNED) return BOOLEAN is constant L_left:INTEGER:= L'length-1; constant R_left:INTEGER:= R'length-1; alias XL: UNSIGNED(L_left downto 0) is L; alias XR: UNSIGNED(R_left downto 0) is R; constant SIZE: NATURAL:= MAX (L'LENGTH, R'LENGTH) ; variable L01 : UNSIGNED(L_left downto 0); variable R01 : UNSIGNED(R_left downto 0); begin if ((L'length<1) or (R'length<1)) then return FALSE; end if; L01 := TO_01(XL,std_logic' ('X')); R01 := TO_01(XR,std_logic' ('X')); if ((L01(L01'left)='X') or (R01(R01'left)='X')) then return FALSE; end if; return not UNSIGNED_LESS_OR_EQUAL (RESIZE(L01,SIZE), RESIZE(R01,SIZE)) ; end ">" ; -- Id: C.2 function ">" ( L,R: SIGNED) return BOOLEAN is constant L_left:INTEGER:= L'length-1; constant R_left:INTEGER:= R'length-1; alias XL: SIGNED(L_left downto 0) is L; alias XR: SIGNED(R_left downto 0) is R; constant SIZE: NATURAL:= MAX (L'LENGTH, R'LENGTH) ; variable L01 : SIGNED(L_left downto 0); variable R01 : SIGNED(R_left downto 0); begin if ((L'length<1) or (R'length<1)) then return FALSE; end if; L01 := TO_01(XL,std_logic' ('X')); R01 := TO_01(XR,std_logic' ('X')); if ((L01(L01'left)='X') or (R01(R01'left)='X')) then return FALSE; end if; return not SIGNED_LESS_OR_EQUAL (RESIZE(L01,SIZE), RESIZE(R01,SIZE)) ; end ">" ; -- Id: C.3 function ">" ( L: NATURAL; R: UNSIGNED) return BOOLEAN is constant R_left:INTEGER:= R'length-1; alias XR: UNSIGNED(R_left downto 0) is R; variable R01 : UNSIGNED(R_left downto 0); begin if (R'length<1) then return FALSE; end if; R01 := TO_01(XR,std_logic' ('X')); if (R01(R01'left)='X') then return FALSE; end if; if UNSIGNED_NUM_BITS(l)>R'length then return TRUE; end if; return not UNSIGNED_LESS_OR_EQUAL (TO_UNSIGNED (L,R01'LENGTH), R01) ; end ">" ; -- Id: C.4 function ">" ( L: INTEGER; R: SIGNED) return BOOLEAN is constant R_left:INTEGER:= R'length-1; alias XR: SIGNED(R_left downto 0) is R; variable R01 : SIGNED(R_left downto 0); begin if (R'length<1) then return FALSE; end if; R01 := TO_01(XR,std_logic' ('X')); if (R01(R01'left)='X') then return FALSE; end if; if Signed_NUM_BITS(l)>R'length then return L>0; end if; return not SIGNED_LESS_OR_EQUAL (TO_SIGNED(L,R01'LENGTH), R01) ; end ">" ; -- Id: C.5 function ">" ( L: UNSIGNED; R: NATURAL) return BOOLEAN is constant L_left:INTEGER:= L'length-1; alias XL: UNSIGNED(L_left downto 0) is L; variable L01 : UNSIGNED(L_left downto 0); begin if (L'length<1) then return FALSE; end if; L01 := TO_01(XL,std_logic' ('X')); if (L01(L01'left)='X') then return FALSE; end if; if UNSIGNED_NUM_BITS(R)>L'length then return FALSE; end if; return not UNSIGNED_LESS_OR_EQUAL (L01, TO_UNSIGNED (R,L01'LENGTH)) ; end ">" ; -- Id: C.6 function ">" ( L: SIGNED; R: INTEGER) return BOOLEAN is constant L_left:INTEGER:= L'length-1; alias XL: SIGNED(L_left downto 0) is L; variable L01 : SIGNED(L_left downto 0); begin if (L'length<1) then return FALSE; end if; L01 := TO_01(XL,std_logic' ('X')); if (L01(L01'left)='X') then return FALSE; end if; if Signed_NUM_BITS(R)>L'length then return 0>R; end if; return not SIGNED_LESS_OR_EQUAL (L01, TO_SIGNED(R,L01'LENGTH)) ; end ">" ; --============================================================================= -- Id: C.7 function "<" ( L,R: UNSIGNED) return BOOLEAN is constant L_left:INTEGER:= L'length-1; constant R_left:INTEGER:= R'length-1; alias XL: UNSIGNED(L_left downto 0) is L; alias XR: UNSIGNED(R_left downto 0) is R; constant SIZE: NATURAL:= MAX (L'LENGTH, R'LENGTH) ; variable L01 : UNSIGNED(L_left downto 0); variable R01 : UNSIGNED(R_left downto 0); begin if ((L'length<1) or (R'length<1)) then return FALSE; end if; L01 := TO_01(XL,std_logic' ('X')); R01 := TO_01(XR,std_logic' ('X')); if ((L01(L01'left)='X') or (R01(R01'left)='X')) then return FALSE; end if; return UNSIGNED_LESS (RESIZE(L01,SIZE), RESIZE(R01,SIZE)) ; end "<" ; -- Id: C.8 function "<" ( L,R: SIGNED) return BOOLEAN is constant L_left:INTEGER:= L'length-1; constant R_left:INTEGER:= R'length-1; alias XL: SIGNED(L_left downto 0) is L; alias XR: SIGNED(R_left downto 0) is R; constant SIZE: NATURAL:= MAX (L'LENGTH, R'LENGTH) ; variable L01 : SIGNED(L_left downto 0); variable R01 : SIGNED(R_left downto 0); begin if ((L'length<1) or (R'length<1)) then return FALSE; end if; L01 := TO_01(XL,std_logic' ('X')); R01 := TO_01(XR,std_logic' ('X')); if ((L01(L01'left)='X') or (R01(R01'left)='X')) then return FALSE; end if; return SIGNED_LESS (RESIZE(L01,SIZE), RESIZE(R01,SIZE)) ; end "<" ; -- Id: C.9 function "<" ( L: NATURAL; R: UNSIGNED) return BOOLEAN is constant R_left:INTEGER:= R'length-1; alias XR: UNSIGNED(R_left downto 0) is R; variable R01 : UNSIGNED(R_left downto 0); begin if (R'length<1) then return FALSE; end if; R01 := TO_01(XR,std_logic' ('X')); if (R01(R01'left)='X') then return FALSE; end if; if UNSIGNED_NUM_BITS(L)>R'length then return L<0; end if; return UNSIGNED_LESS (TO_UNSIGNED(L,R01'LENGTH), R01) ; end "<" ; -- Id: C.10 function "<" ( L: INTEGER; R: SIGNED) return BOOLEAN is constant R_left:INTEGER:= R'length-1; alias XR: SIGNED(R_left downto 0) is R; variable R01 : SIGNED(R_left downto 0); begin if (R'length<1) then return FALSE; end if; R01 := TO_01(XR,std_logic' ('X')); if (R01(R01'left)='X') then return FALSE; end if; if Signed_NUM_BITS(L)>R'length then return L<0; end if; return SIGNED_LESS (TO_SIGNED(L,R01'LENGTH), R01) ; end "<" ; -- Id: C.11 function "<" ( L: UNSIGNED; R: NATURAL) return BOOLEAN is constant L_left:INTEGER:= L'length-1; alias XL: UNSIGNED(L_left downto 0) is L; variable L01 : UNSIGNED(L_left downto 0); begin if (L'length<1) then return FALSE; end if; L01 := TO_01(XL,std_logic' ('X')); if (L01(L01'left)='X') then return FALSE; end if; if UNSIGNED_NUM_BITS(R)>L'length then return 0<R; end if; return UNSIGNED_LESS (L01, TO_UNSIGNED (R,L01'LENGTH)) ; end "<" ; -- Id: C.12 function "<" ( L: SIGNED; R: INTEGER) return BOOLEAN is constant L_left:INTEGER:= L'length-1; alias XL: SIGNED(L_left downto 0) is L; variable L01 : SIGNED(L_left downto 0); begin if (L'length<1) then return FALSE; end if; L01 := TO_01(XL,std_logic' ('X')); if (L01(L01'left)='X') then return FALSE; end if; if Signed_NUM_BITS(R)>L'length then return 0<R; end if; return SIGNED_LESS (L01, TO_SIGNED (R,L01'LENGTH)) ; end "<" ; --============================================================================= -- Id: C.13 function "<=" ( L,R: UNSIGNED) return BOOLEAN is constant L_left:INTEGER:= L'length-1; constant R_left:INTEGER:= R'length-1; alias XL: UNSIGNED(L_left downto 0) is L; alias XR: UNSIGNED(R_left downto 0) is R; constant SIZE: NATURAL:= MAX (L'LENGTH, R'LENGTH) ; variable L01 : UNSIGNED(L_left downto 0); variable R01 : UNSIGNED(R_left downto 0); begin if ((L'length<1) or (R'length<1)) then return FALSE; end if; L01 := TO_01(XL,std_logic' ('X')); R01 := TO_01(XR,std_logic' ('X')); if ((L01(L01'left)='X') or (R01(R01'left)='X')) then return FALSE; end if; return UNSIGNED_LESS_OR_EQUAL (RESIZE(L01,SIZE), RESIZE(R01,SIZE)) ; end "<=" ; -- Id: C.14 function "<=" ( L,R: SIGNED) return BOOLEAN is constant L_left:INTEGER:= L'length-1; constant R_left:INTEGER:= R'length-1; alias XL: SIGNED(L_left downto 0) is L; alias XR: SIGNED(R_left downto 0) is R; constant SIZE: NATURAL:= MAX (L'LENGTH, R'LENGTH) ; variable L01 : SIGNED(L_left downto 0); variable R01 : SIGNED(R_left downto 0); begin if ((L'length<1) or (R'length<1)) then return FALSE; end if; L01 := TO_01(XL,std_logic' ('X')); R01 := TO_01(XR,std_logic' ('X')); if ((L01(L01'left)='X') or (R01(R01'left)='X')) then return FALSE; end if; return SIGNED_LESS_OR_EQUAL (RESIZE(L01,SIZE), RESIZE(R01,SIZE)) ; end "<=" ; -- Id: C.15 function "<=" ( L: NATURAL; R: UNSIGNED) return BOOLEAN is constant R_left:INTEGER:= R'length-1; alias XR: UNSIGNED(R_left downto 0) is R; variable R01 : UNSIGNED(R_left downto 0); begin if (R'length<1) then return FALSE; end if; R01 := TO_01(XR,std_logic' ('X')); if (R01(R01'left)='X') then return FALSE; end if; if UNSIGNED_NUM_BITS(L)>R'length then return L<0; end if; return UNSIGNED_LESS_OR_EQUAL (TO_UNSIGNED(L,R01'LENGTH), R01) ; end "<=" ; -- Id: C.16 function "<=" ( L: INTEGER; R: SIGNED) return BOOLEAN is constant R_left:INTEGER:= R'length-1; alias XR: SIGNED(R_left downto 0) is R; variable R01 : SIGNED(R_left downto 0); begin if (R'length<1) then return FALSE; end if; R01 := TO_01(XR,std_logic' ('X')); if (R01(R01'left)='X') then return FALSE; end if; if Signed_NUM_BITS(L)>R'length then return L<0; end if; return SIGNED_LESS_OR_EQUAL (TO_SIGNED(L,R01'LENGTH), R01) ; end "<=" ; -- Id: C.17 function "<=" ( L: UNSIGNED; R: NATURAL) return BOOLEAN is constant L_left:INTEGER:= L'length-1; alias XL: UNSIGNED(L_left downto 0) is L; variable L01 : UNSIGNED(L_left downto 0); begin if (L_left<0) then return FALSE; end if; L01 := TO_01(XL,std_logic' ('X')); if (L01(L01'left)='X') then return FALSE; end if; if UNSIGNED_NUM_BITS(R)>L'length then return 0<R; end if; return UNSIGNED_LESS_OR_EQUAL (L01, TO_UNSIGNED(R,L01'LENGTH)) ; end "<=" ; -- Id: C.18 function "<=" ( L: SIGNED; R: INTEGER) return BOOLEAN is constant L_left:INTEGER:= L'length-1; alias XL: SIGNED(L_left downto 0) is L; variable L01 : SIGNED(L_left downto 0); begin if (L_left<0) then return FALSE; end if; L01 := TO_01(XL,std_logic' ('X')); if (L01(L01'left)='X') then return FALSE; end if; if Signed_NUM_BITS(R)>L'length then return 0<R; end if; return SIGNED_LESS_OR_EQUAL (L01, TO_SIGNED(R,L01'LENGTH)) ; end "<=" ; --============================================================================= -- Id: C.19 function ">=" ( L,R: UNSIGNED) return BOOLEAN is constant L_left:INTEGER:= L'length-1; constant R_left:INTEGER:= R'length-1; alias XL: UNSIGNED(L_left downto 0) is L; alias XR: UNSIGNED(R_left downto 0) is R; constant SIZE: NATURAL:= MAX (L'LENGTH, R'LENGTH) ; variable L01 : UNSIGNED(L_left downto 0); variable R01 : UNSIGNED(R_left downto 0); begin if ((L'length<1) or (R'length<1)) then return FALSE; end if; L01 := TO_01(XL,std_logic' ('X')); R01 := TO_01(XR,std_logic' ('X')); if ((L01(L01'left)='X') or (R01(R01'left)='X')) then return FALSE; end if; return not UNSIGNED_LESS (RESIZE(L01,SIZE), RESIZE(R01,SIZE)) ; end ">=" ; -- Id: C.20 function ">=" ( L,R: SIGNED) return BOOLEAN is constant L_left:INTEGER:= L'length-1; constant R_left:INTEGER:= R'length-1; alias XL: SIGNED(L_left downto 0) is L; alias XR: SIGNED(R_left downto 0) is R; constant SIZE: NATURAL:= MAX (L'LENGTH, R'LENGTH) ; variable L01 : SIGNED(L_left downto 0); variable R01 : SIGNED(R_left downto 0); begin if ((L'length<1) or (R'length<1)) then return FALSE; end if; L01 := TO_01(XL,std_logic' ('X')); R01 := TO_01(XR,std_logic' ('X')); if ((L01(L01'left)='X') or (R01(R01'left)='X')) then return FALSE; end if; return not SIGNED_LESS (RESIZE(L01,SIZE), RESIZE(R01,SIZE)) ; end ">=" ; -- Id: C.21 function ">=" ( L: NATURAL; R: UNSIGNED) return BOOLEAN is constant R_left:INTEGER:= R'length-1; alias XR: UNSIGNED(R_left downto 0) is R; variable R01 : UNSIGNED(R_left downto 0); begin if (R'length<1) then return FALSE; end if; R01 := TO_01(XR,std_logic' ('X')); if (R01(R01'left)='X') then return FALSE; end if; if UNSIGNED_NUM_BITS(L)>R'length then return L>0; end if; return not UNSIGNED_LESS (TO_UNSIGNED(L,R01'LENGTH), R01) ; end ">=" ; -- Id: C.22 function ">=" ( L: INTEGER; R: SIGNED) return BOOLEAN is constant R_left:INTEGER:= R'length-1; alias XR: SIGNED(R_left downto 0) is R; variable R01 : SIGNED(R_left downto 0); begin if (R'length<1) then return FALSE; end if; R01 := TO_01(XR,std_logic' ('X')); if (R01(R01'left)='X') then return FALSE; end if; if Signed_NUM_BITS(L)>R'length then return L>0; end if; return not SIGNED_LESS (TO_SIGNED (L,R01'LENGTH), R01) ; end ">=" ; -- Id: C.23 function ">=" ( L: UNSIGNED; R: NATURAL) return BOOLEAN is constant L_left:INTEGER:= L'length-1; alias XL: UNSIGNED(L_left downto 0) is L; variable L01 : UNSIGNED(L_left downto 0); begin if (L'length<1) then return FALSE; end if; L01 := TO_01(XL,std_logic' ('X')); if (L01(L01'left)='X') then return FALSE; end if; if UNSIGNED_NUM_BITS(R)>L'length then return 0>R; end if; return not UNSIGNED_LESS(L01, TO_UNSIGNED(R,L01'LENGTH)) ; end ">=" ; -- Id: C.24 function ">=" ( L: SIGNED; R: INTEGER) return BOOLEAN is constant L_left:INTEGER:= L'length-1; alias XL: SIGNED(L_left downto 0) is L; variable L01 : SIGNED(L_left downto 0); begin if (L'length<1) then return FALSE; end if; L01 := TO_01(XL,std_logic' ('X')); if (L01(L01'left)='X') then return FALSE; end if; if Signed_NUM_BITS(R)>L'length then return 0>R; end if; return not SIGNED_LESS (L01, TO_SIGNED(R,L01'LENGTH)) ; end ">=" ; --============================================================================= -- Id: C.25 function "=" ( L,R: UNSIGNED) return BOOLEAN is constant L_left:INTEGER:= L'length-1; constant R_left:INTEGER:= R'length-1; alias XL: UNSIGNED(L_left downto 0) is L; alias XR: UNSIGNED(R_left downto 0) is R; constant SIZE: NATURAL:= MAX (L'LENGTH, R'LENGTH) ; variable L01 : UNSIGNED(L_left downto 0); variable R01 : UNSIGNED(R_left downto 0); begin if ((L'length<1) or (R'length<1)) then return FALSE; end if; L01 := TO_01(XL,std_logic' ('X')); R01 := TO_01(XR,std_logic' ('X')); if ((L01(L01'left)='X') or (R01(R01'left)='X')) then return FALSE; end if; return UNSIGNED_equal (RESIZE(L01,SIZE),RESIZE(R01,SIZE)) ; end "=" ; -- Id: C.26 function "=" ( L,R: SIGNED) return BOOLEAN is constant L_left:INTEGER:= L'length-1; constant R_left:INTEGER:= R'length-1; alias XL: SIGNED(L_left downto 0) is L; alias XR: SIGNED(R_left downto 0) is R; constant SIZE: NATURAL:= MAX (L'LENGTH, R'LENGTH) ; variable L01 : SIGNED(L_left downto 0); variable R01 : SIGNED(R_left downto 0); begin if ((L'length<1) or (R'length<1)) then return FALSE; end if; L01 := TO_01(XL,std_logic' ('X')); R01 := TO_01(XR,std_logic' ('X')); if ((L01(L01'left)='X') or (R01(R01'left)='X')) then return FALSE; end if; return SIGNED_equal (RESIZE(L01,SIZE), RESIZE(R01,SIZE)) ; end "=" ; -- Id: C.27 function "=" ( L: NATURAL; R: UNSIGNED) return BOOLEAN is constant R_left:INTEGER:= R'length-1; alias XR: UNSIGNED(R_left downto 0) is R; variable R01 : UNSIGNED(R_left downto 0); begin if (R'length<1) then return FALSE; end if; R01 := TO_01(XR,std_logic' ('X')); if (R01(R01'left)='X') then return FALSE; end if; if UNSIGNED_NUM_BITS(L)>R'Length then return FALSE; end if; return UNSIGNED_equal ( TO_UNSIGNED(L,R01'LENGTH), R01); end "=" ; -- Id: C.28 function "=" ( L: INTEGER; R: SIGNED) return BOOLEAN is constant R_left:INTEGER:= R'length-1; alias XR: SIGNED(R_left downto 0) is R; variable R01 : SIGNED(R_left downto 0); begin if (R'length<1) then return FALSE; end if; R01 := TO_01(XR,std_logic' ('X')); if (R01(R01'left)='X') then return FALSE; end if; if UNSIGNED_NUM_BITS(L)>R'Length then return FALSE; end if; return SIGNED_equal ( TO_SIGNED(L,R01'LENGTH), R01) ; end "=" ; -- Id: C.29 function "=" ( L: UNSIGNED; R: NATURAL) return BOOLEAN is constant L_left:INTEGER:= L'length-1; alias XL: UNSIGNED(L_left downto 0) is L; variable L01 : UNSIGNED(L_left downto 0); begin if (L'length<1) then return FALSE; end if; L01 := TO_01(XL,std_logic' ('X')); if (L01(L01'left)='X') then return FALSE; end if; if UNSIGNED_NUM_BITS(R)>L'length then return FALSE; end if; return UNSIGNED_equal (L01, TO_UNSIGNED (R,L01'LENGTH)) ; end "=" ; -- Id: C.30 function "=" ( L: SIGNED; R: INTEGER) return BOOLEAN is constant L_left:INTEGER:= L'length-1; alias XL: SIGNED(L_left downto 0) is L; variable L01 : SIGNED(L_left downto 0); begin if (L'length<1) then return FALSE; end if; L01 := TO_01(XL,std_logic' ('X')); if (L01(L01'left)='X') then return FALSE; end if; if UNSIGNED_NUM_BITS(R)>L'length then return FALSE; end if; return SIGNED_equal (L01, TO_SIGNED (R,L01'LENGTH)) ; end "=" ; --============================================================================= -- Id: C.31 function "/=" ( L,R: UNSIGNED) return BOOLEAN is constant L_left:INTEGER:= L'length-1; constant R_left:INTEGER:= R'length-1; alias XL: UNSIGNED(L_left downto 0) is L; alias XR: UNSIGNED(R_left downto 0) is R; constant SIZE: NATURAL:= MAX (L'LENGTH, R'LENGTH) ; variable L01 : UNSIGNED(L_left downto 0); variable R01 : UNSIGNED(R_left downto 0); begin if ((L'length<1) or (R'length<1)) then return FALSE; end if; L01 := TO_01(XL); R01 := TO_01(XR); if ((L01(L01'left)='X') or (R01(R01'left)='X')) then return TRUE; end if; return not(UNSIGNED_equal (RESIZE(L01,SIZE),RESIZE(R01,SIZE))) ; end "/=" ; -- Id: C.32 function "/=" ( L,R: SIGNED) return BOOLEAN is constant L_left:INTEGER:= L'length-1; constant R_left:INTEGER:= R'length-1; alias XL: SIGNED(L_left downto 0) is L; alias XR: SIGNED(R_left downto 0) is R; constant SIZE: NATURAL:= MAX (L'LENGTH, R'LENGTH) ; variable L01 : SIGNED(L_left downto 0); variable R01 : SIGNED(R_left downto 0); begin if ((L'length<1) or (R'length<1)) then return FALSE; end if; L01 := TO_01(XL); R01 := TO_01(XR); if ((L01(L01'left)='X') or (R01(R01'left)='X')) then return TRUE; end if; return not(SIGNED_equal (RESIZE(L01,SIZE), RESIZE(R01,SIZE))) ; end "/=" ; -- Id: C.33 function "/=" ( L: NATURAL; R: UNSIGNED) return BOOLEAN is constant R_left:INTEGER:= R'length-1; alias XR: UNSIGNED(R_left downto 0) is R; variable R01 : UNSIGNED(R_left downto 0); begin if (R'length<1) then return FALSE; end if; R01 := TO_01(XR); if (R01(R01'left)='X') then return TRUE; end if; if UNSIGNED_NUM_BITS(L)>R'Length then return TRUE; end if; return not(UNSIGNED_equal ( TO_UNSIGNED(L,R01'LENGTH), R01)); end "/=" ; -- Id: C.34 function "/=" ( L: INTEGER; R: SIGNED) return BOOLEAN is constant R_left:INTEGER:= R'length-1; alias XR: SIGNED(R_left downto 0) is R; variable R01 : SIGNED(R_left downto 0); begin if (R'length<1) then return FALSE; end if; R01 := TO_01(XR); if (R01(R01'left)='X') then return TRUE; end if; if Signed_NUM_BITS(L)>R'Length then return TRUE; end if; return not(SIGNED_equal ( TO_SIGNED(L,R01'LENGTH), R01)) ; end "/=" ; -- Id: C.35 function "/=" ( L: UNSIGNED; R: NATURAL) return BOOLEAN is constant L_left:INTEGER:= L'length-1; alias XL: UNSIGNED(L_left downto 0) is L; variable L01 : UNSIGNED(L_left downto 0); begin if (L'length<1) then return FALSE; end if; L01 := TO_01(XL); if (L01(L01'left)='X') then return TRUE; end if; if UNSIGNED_NUM_BITS(R)>L'Length then return TRUE; end if; return not(UNSIGNED_equal (L01, TO_UNSIGNED (R,L01'LENGTH))) ; end "/=" ; -- Id: C.36 function "/=" ( L: SIGNED; R: INTEGER) return BOOLEAN is constant L_left:INTEGER:= L'length-1; alias XL: SIGNED(L_left downto 0) is L; variable L01 : SIGNED(L_left downto 0); begin if (L'length<1) then return FALSE; end if; L01 := TO_01(XL); if (L01(L01'left)='X') then return TRUE; end if; if Signed_NUM_BITS(R)>L'Length then return TRUE; end if; return not(SIGNED_equal (L01, TO_SIGNED (R,L01'LENGTH))) ; end "/=" ; --============================================================================= -- Id: S.1 function shift_left(ARG: UNSIGNED; COUNT: NATURAL) return UNSIGNED is begin if (ARG'length<1) then return NAU; end if; return UNSIGNED(XSLL(STD_LOGIC_VECTOR(ARG),COUNT)); end; -- Id: S.2 function shift_right(ARG: UNSIGNED; COUNT: NATURAL) return UNSIGNED is begin if (ARG'length<1) then return NAU; end if; return UNSIGNED(XSRL(STD_LOGIC_VECTOR(ARG),COUNT)); end; -- Id: S.3 function shift_left(ARG: SIGNED; COUNT: NATURAL) return SIGNED is begin if (ARG'length<1) then return NAS; end if; return SIGNED(XSLL(STD_LOGIC_VECTOR(ARG),COUNT)); end; -- Id: S.4 function shift_right(ARG: SIGNED; COUNT: NATURAL) return SIGNED is begin if (ARG'length<1) then return NAS; end if; return SIGNED(XSRA(STD_LOGIC_VECTOR(ARG),COUNT)); end; --============================================================================= -- Id: S.5 function rotate_left(ARG: UNSIGNED; COUNT: NATURAL) return UNSIGNED is begin if (ARG'length<1) then return NAU; end if; return UNSIGNED(XROL(STD_LOGIC_VECTOR(ARG),COUNT)); end; -- Id: S.6 function rotate_right(ARG: UNSIGNED; COUNT: NATURAL) return UNSIGNED is begin if (ARG'length<1) then return NAU; end if; return UNSIGNED(XROR(STD_LOGIC_VECTOR(ARG),COUNT)); end; -- Id: S.7 function rotate_left(ARG: SIGNED; COUNT: NATURAL) return SIGNED is begin if (ARG'length<1) then return NAS; end if; return SIGNED(XROL(STD_LOGIC_VECTOR(ARG),COUNT)); end; -- Id: S.8 function rotate_right(ARG: SIGNED; COUNT: NATURAL) return SIGNED is begin if (ARG'length<1) then return NAS; end if; return SIGNED(XROR(STD_LOGIC_VECTOR(ARG),COUNT)); end; --============================================================================= -- Id: D.1 function TO_INTEGER(ARG: UNSIGNED) return NATURAL is constant ARG_LEFT:INTEGER:= ARG'length-1; alias XXARG:UNSIGNED(ARG_LEFT downto 0) is ARG; variable XARG:UNSIGNED(ARG_LEFT downto 0); variable RESULT: NATURAL:= 0; variable w : INTEGER:= 1; -- weight factor begin if (ARG'length<1) then assert NO_WARNING report "numeric_std.TO_INTEGER: null arg" severity warning; return 0; end if; XARG:= TO_01(XXARG); if (XARG(XARG'left)='X') then assert NO_WARNING report "numeric_std.TO_INTEGER: metavalue arg set to 0" severity warning; return 0; end if; for i in XARG'reverse_range loop if XARG (i) = '1' then RESULT:= RESULT + w; end if; if (i /= XARG'left) then w := w + w; end if; end loop; return RESULT; end TO_INTEGER; -- Id: D.2 function TO_INTEGER(ARG: SIGNED) return INTEGER is begin if ARG(ARG'left) = '0' then return TO_INTEGER( UNSIGNED (ARG)) ; else return (- (TO_INTEGER( UNSIGNED ( - (ARG + 1)))) -1); end if; end TO_INTEGER; -- Id: D.3 function TO_UNSIGNED(ARG,SIZE: NATURAL) return UNSIGNED is variable RESULT: UNSIGNED (SIZE-1 downto 0) ; variable i_val:natural := ARG; begin if (SIZE < 1) then return NAU; end if; for i in 0 to RESULT'left loop if (i_val MOD 2) = 0 then RESULT(i) := '0'; else RESULT(i) := '1' ; end if; i_val := i_val/2 ; end loop; if not(i_val=0) then assert NO_WARNING report "numeric_std.TO_UNSIGNED : vector truncated" severity WARNING ; end if; return RESULT ; end TO_UNSIGNED; -- Id: D.4 function TO_SIGNED(ARG: INTEGER; SIZE: NATURAL) return SIGNED is variable RESULT: SIGNED (SIZE-1 downto 0) ; variable b_val : STD_LOGIC:= '0' ; variable i_val : INTEGER:= ARG ; begin if (SIZE < 1) then return NAS; end if; if (ARG<0) then b_val := '1' ; i_val := -(ARG+1) ; end if ; for i in 0 to RESULT'left loop if (i_val MOD 2) = 0 then RESULT(i) := b_val; else RESULT(i) := not b_val ; end if; i_val := i_val/2 ; end loop; if ((i_val/=0) or (b_val/=RESULT(RESULT'left))) then assert NO_WARNING report "numeric_std.TO_SIGNED : vector truncated" severity WARNING ; end if; return RESULT; end TO_SIGNED; -- Id: D.5 function TO_UNSIGNED(ARG: STD_LOGIC_VECTOR) return UNSIGNED is begin return UNSIGNED(ARG); end TO_UNSIGNED; -- Id: D.6 function TO_SIGNED(ARG: STD_LOGIC_VECTOR) return SIGNED is begin return SIGNED(ARG); end TO_SIGNED; -- Id: D.7 function TO_STDLOGICVECTOR(ARG: UNSIGNED) return STD_LOGIC_VECTOR is begin return STD_LOGIC_VECTOR(ARG); end TO_STDLOGICVECTOR; -- Id: D.8 function TO_STDLOGICVECTOR(ARG: SIGNED) return STD_LOGIC_VECTOR is begin return STD_LOGIC_VECTOR(ARG); end TO_STDLOGICVECTOR; --============================================================================= -- Id: R.1 function RESIZE (ARG: SIGNED; NEW_SIZE: NATURAL) return SIGNED is alias invec : SIGNED (ARG'length-1 downto 0) is ARG ; variable RESULT: SIGNED (NEW_SIZE-1 downto 0) ; constant bound : NATURAL:= MIN(ARG'length,RESULT'length)-2 ; begin if (NEW_SIZE<1) then return NAS; end if; RESULT:= (others=>ARG(ARG'left)) ; if bound >= 0 then RESULT(bound downto 0) := invec(bound downto 0) ; end if; return RESULT; end RESIZE ; -- Id: R.2 function RESIZE ( ARG: UNSIGNED; NEW_SIZE: NATURAL) return UNSIGNED is constant ARG_LEFT:INTEGER:= ARG'length-1; alias XARG: UNSIGNED(ARG_LEFT downto 0) is ARG; variable RESULT: UNSIGNED(NEW_SIZE-1 downto 0) := (others=>'0'); begin if (NEW_SIZE<1) then return NAU; end if; if XARG'length=0 then return RESULT; end if; if (RESULT'length < ARG'length) then RESULT(RESULT'left downto 0) := XARG(RESULT'left downto 0); else RESULT(RESULT'left downto XARG'left+1) := (others => '0'); RESULT(XARG'left downto 0) := XARG; end if; return RESULT; end RESIZE; --============================================================================ -- Id: L.1 function "not" ( L: UNSIGNED) return UNSIGNED is variable RESULT: UNSIGNED (L'range); begin RESULT:= UNSIGNED(not(STD_LOGIC_VECTOR(L))); return RESULT; end "not"; -- Id: L.2 function "and" ( L,R: UNSIGNED ) return UNSIGNED is variable RESULT: UNSIGNED (L'range); begin RESULT:= UNSIGNED(STD_LOGIC_VECTOR(L) and STD_LOGIC_VECTOR(R)); return RESULT; end "and"; -- Id: L.3 function "or" ( L,R: UNSIGNED ) return UNSIGNED is variable RESULT: UNSIGNED (L'range); begin RESULT:= UNSIGNED(STD_LOGIC_VECTOR(L) or STD_LOGIC_VECTOR(R)); return RESULT; end "or"; -- Id: L.4 function "nand" ( L,R: UNSIGNED ) return UNSIGNED is variable RESULT: UNSIGNED (L'range); begin RESULT:= UNSIGNED(STD_LOGIC_VECTOR(L) nand STD_LOGIC_VECTOR(R)); return RESULT; end "nand"; -- Id: L.5 function "nor" ( L,R: UNSIGNED ) return UNSIGNED is variable RESULT: UNSIGNED (L'range); begin RESULT:= UNSIGNED(STD_LOGIC_VECTOR(L) nor STD_LOGIC_VECTOR(R)); return RESULT; end "nor"; -- Id: L.6 function "xor" ( L,R: UNSIGNED ) return UNSIGNED is variable RESULT: UNSIGNED (L'range); begin RESULT:= UNSIGNED(STD_LOGIC_VECTOR(L) xor STD_LOGIC_VECTOR(R)); return RESULT; end "xor"; -- ----------------------------------------------------------------------- -- Note : The declaration and implementation of the "xnor" function is -- specifically commented until at which time the VHDL language has been -- officially adopted as containing such a function. At such a point, -- the following comments may be removed along with this notice without -- further "official" ballotting of this 1076.3 package. It is -- the intent of this effort to provide such a function once it becomes -- available in the VHDL standard. -- ----------------------------------------------------------------------- -- Id: L.7 --function "xnor" ( L,R: UNSIGNED ) return UNSIGNED is --variable RESULT: UNSIGNED (L'range); --begin -- RESULT:= UNSIGNED(STD_LOGIC_VECTOR(L) xnor STD_LOGIC_VECTOR(R)); -- return RESULT; -- end "xnor"; -- Id: L.8 function "not" ( L: SIGNED) return SIGNED is variable RESULT: SIGNED (L'range); begin RESULT:= SIGNED(not(STD_LOGIC_VECTOR(L))); return RESULT; end "not"; -- Id: L.9 function "and" ( L,R: SIGNED ) return SIGNED is variable RESULT: SIGNED (L'range); begin RESULT:= SIGNED(STD_LOGIC_VECTOR(L) and STD_LOGIC_VECTOR(R)); return RESULT; end "and"; -- Id: L.10 function "or" ( L,R: SIGNED ) return SIGNED is variable RESULT: SIGNED (L'range); begin RESULT:= SIGNED(STD_LOGIC_VECTOR(L) or STD_LOGIC_VECTOR(R)); return RESULT; end "or"; -- Id: L.11 function "nand" ( L,R: SIGNED ) return SIGNED is variable RESULT: SIGNED (L'range); begin RESULT:= SIGNED(STD_LOGIC_VECTOR(L) nand STD_LOGIC_VECTOR(R)); return RESULT; end "nand"; -- Id: L.12 function "nor" ( L,R: SIGNED ) return SIGNED is variable RESULT: SIGNED (L'range); begin RESULT:= SIGNED(STD_LOGIC_VECTOR(L) nor STD_LOGIC_VECTOR(R)); return RESULT; end "nor"; -- Id: L.13 function "xor" ( L,R: SIGNED ) return SIGNED is variable RESULT: SIGNED (L'range); begin RESULT:= SIGNED(STD_LOGIC_VECTOR(L) xor STD_LOGIC_VECTOR(R)); return RESULT; end "xor"; -- ----------------------------------------------------------------------- -- Note : The declaration and implementation of the "xnor" function is -- specifically commented until at which time the VHDL language has been -- officially adopted as containing such a function. At such a point, -- the following comments may be removed along with this notice without -- further "official" ballotting of this 1076.3 package. It is -- the intent of this effort to provide such a function once it becomes -- available in the VHDL standard. -- ----------------------------------------------------------------------- -- Id: L.14 --function "xnor" ( L,R: SIGNED ) return SIGNED is --variable RESULT: SIGNED (L'range); --begin -- RESULT:= SIGNED(STD_LOGIC_VECTOR(L) xnor STD_LOGIC_VECTOR(R)); -- return RESULT; -- end "xnor"; --============================================================================= -- support constants for STD_MATCH: type STDULOGIC_TABLE is array(STD_ULOGIC, STD_ULOGIC) of STD_ULOGIC; -- truth table for "and" function constant AND_TABLE : STDULOGIC_TABLE := ( -- ---------------------------------------------------- -- | U X 0 1 Z W L H - | | -- ---------------------------------------------------- ( 'U', 'U', '0', 'U', 'U', 'U', '0', 'U', 'U' ), -- | U | ( 'U', 'X', '0', 'X', 'X', 'X', '0', 'X', 'X' ), -- | X | ( '0', '0', '0', '0', '0', '0', '0', '0', '0' ), -- | 0 | ( 'U', 'X', '0', '1', 'X', 'X', '0', '1', 'X' ), -- | 1 | ( 'U', 'X', '0', 'X', 'X', 'X', '0', 'X', 'X' ), -- | Z | ( 'U', 'X', '0', 'X', 'X', 'X', '0', 'X', 'X' ), -- | W | ( '0', '0', '0', '0', '0', '0', '0', '0', '0' ), -- | L | ( 'U', 'X', '0', '1', 'X', 'X', '0', '1', 'X' ), -- | H | ( 'U', 'X', '0', 'X', 'X', 'X', '0', 'X', 'X' ) -- | - | ); -- truth table for STD_MATCH function constant MATCH_TABLE : STDULOGIC_TABLE := ( -- ---------------------------------------------------- -- | U X 0 1 Z W L H - | | -- ---------------------------------------------------- ( 'U', 'U', 'U', 'U', 'U', 'U', 'U', 'U', '1' ), -- | U | ( 'U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', '1' ), -- | X | ( 'U', 'X', '1', '0', 'X', 'X', '1', '0', '1' ), -- | 0 | ( 'U', 'X', '0', '1', 'X', 'X', '0', '1', '1' ), -- | 1 | ( 'U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', '1' ), -- | Z | ( 'U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', '1' ), -- | W | ( 'U', 'X', '1', '0', 'X', 'X', '1', '0', '1' ), -- | L | ( 'U', 'X', '0', '1', 'X', 'X', '0', '1', '1' ), -- | H | ( '1', '1', '1', '1', '1', '1', '1', '1', '1' ) -- | - | ); -- Id: M.1 function STD_MATCH (L, R: STD_ULOGIC) return BOOLEAN is variable VALUE : STD_ULOGIC; begin VALUE := MATCH_TABLE(L, R); return VALUE = '1'; end STD_MATCH; -- Id: M.2 function STD_MATCH (L, R: STD_LOGIC_VECTOR) return BOOLEAN is alias LV: STD_LOGIC_VECTOR ( 1 to L'LENGTH ) is L; alias RV: STD_LOGIC_VECTOR ( 1 to R'LENGTH ) is R; variable VALUE: STD_ULOGIC:= '1'; begin -- Check that both input vectors are the same length. if LV'LENGTH /= RV'LENGTH then assert NO_WARNING report "STD_MATCH input arguments are not of equal length" severity warning; return FALSE; else for i in LV'LOW to LV'HIGH loop VALUE := AND_TABLE(MATCH_TABLE(LV(i), RV(i)), VALUE); end loop; return VALUE = '1'; end if; end STD_MATCH; --============================================================================= end numeric_std;
gpl-3.0
f27136c6d35d3c8cae87752e3a8bb763
0.585816
3.412852
false
false
false
false
jairov4/accel-oil
solution_virtex5/impl/pcores/nfa_accept_samples_generic_hw_top_v1_00_a/simhdl/vhdl/nfa_finals_buckets_if_async_fifo.vhd
1
5,841
library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity nfa_finals_buckets_if_async_fifo is generic ( DATA_WIDTH : integer := 32; ADDR_WIDTH : integer := 3; DEPTH : integer := 8); port ( clk_w : in std_logic; clk_r : in std_logic; reset : in std_logic; if_din : in std_logic_vector(DATA_WIDTH - 1 downto 0); if_full_n : out std_logic; if_write_ce: in std_logic := '1'; if_write : in std_logic; if_dout : out std_logic_vector(DATA_WIDTH - 1 downto 0); if_empty_n : out std_logic; if_read_ce : in std_logic := '1'; if_read : in std_logic); function calc_addr_width(x : integer) return integer is begin if (x < 1) then return 1; else return x; end if; end function; end entity; architecture rtl of nfa_finals_buckets_if_async_fifo is constant DEPTH_BITS : integer := calc_addr_width(ADDR_WIDTH); constant REAL_DEPTH : integer := 2 ** DEPTH_BITS; constant ALL_ONE : unsigned(DEPTH_BITS downto 0) := (others => '1'); constant MASK : std_logic_vector(DEPTH_BITS downto 0) := std_logic_vector(ALL_ONE sll (DEPTH_BITS - 1)); type memtype is array (0 to REAL_DEPTH - 1) of std_logic_vector(DATA_WIDTH - 1 downto 0); signal mem : memtype; signal full : std_logic := '0'; signal empty : std_logic := '1'; signal full_next : std_logic; signal empty_next : std_logic; signal wraddr_bin : std_logic_vector(DEPTH_BITS downto 0) := (others => '0'); signal rdaddr_bin : std_logic_vector(DEPTH_BITS downto 0) := (others => '0'); signal wraddr : std_logic_vector(DEPTH_BITS - 1 downto 0); signal rdaddr : std_logic_vector(DEPTH_BITS - 1 downto 0); signal wraddr_bin_next : std_logic_vector(DEPTH_BITS downto 0); signal rdaddr_bin_next : std_logic_vector(DEPTH_BITS downto 0); signal wraddr_gray_next : std_logic_vector(DEPTH_BITS downto 0); signal rdaddr_gray_next : std_logic_vector(DEPTH_BITS downto 0); signal wraddr_gray_sync0 : std_logic_vector(DEPTH_BITS downto 0) := (others => '0'); signal rdaddr_gray_sync0 : std_logic_vector(DEPTH_BITS downto 0) := (others => '0'); signal wraddr_gray_sync1 : std_logic_vector(DEPTH_BITS downto 0) := (others => '0'); signal rdaddr_gray_sync1 : std_logic_vector(DEPTH_BITS downto 0) := (others => '0'); signal wraddr_gray_sync2 : std_logic_vector(DEPTH_BITS downto 0) := (others => '0'); signal rdaddr_gray_sync2 : std_logic_vector(DEPTH_BITS downto 0) := (others => '0'); signal dout_buf : std_logic_vector(DATA_WIDTH - 1 downto 0) := (others => '0'); attribute ram_style : string; attribute ram_style of mem : signal is "block"; begin if_full_n <= not full; if_empty_n <= not empty; if_dout <= dout_buf; full_next <= '1' when (wraddr_gray_next = (rdaddr_gray_sync2 xor MASK)) else '0'; empty_next <= '1' when (rdaddr_gray_next = wraddr_gray_sync2) else '0'; wraddr <= wraddr_bin(DEPTH_BITS - 1 downto 0); rdaddr <= rdaddr_bin_next(DEPTH_BITS - 1 downto 0); wraddr_bin_next <= std_logic_vector(unsigned(wraddr_bin) + 1) when (full = '0' and if_write = '1') else wraddr_bin; rdaddr_bin_next <= std_logic_vector(unsigned(rdaddr_bin) + 1) when (empty = '0' and if_read = '1') else rdaddr_bin; wraddr_gray_next <= wraddr_bin_next xor std_logic_vector(unsigned(wraddr_bin_next) srl 1); rdaddr_gray_next <= rdaddr_bin_next xor std_logic_vector(unsigned(rdaddr_bin_next) srl 1); -- full, wraddr_bin, wraddr_gray_sync0, rdaddr_gray_sync1, rdaddr_gray_sync2 -- @ clk_w domain process(clk_w, reset) begin if (reset = '1') then full <= '0'; wraddr_bin <= (others => '0'); wraddr_gray_sync0 <= (others => '0'); rdaddr_gray_sync1 <= (others => '0'); rdaddr_gray_sync2 <= (others => '0'); elsif (clk_w'event and clk_w = '1' and if_write_ce = '1') then full <= full_next; wraddr_bin <= wraddr_bin_next; wraddr_gray_sync0 <= wraddr_gray_next; rdaddr_gray_sync1 <= rdaddr_gray_sync0; rdaddr_gray_sync2 <= rdaddr_gray_sync1; end if; end process; -- empty, rdaddr_bin, rdaddr_gray_sync0, wraddr_gray_sync1, wraddr_gray_sync2 -- @ clk_r domain process(clk_r, reset) begin if (reset = '1') then empty <= '1'; rdaddr_bin <= (others => '0'); rdaddr_gray_sync0 <= (others => '0'); wraddr_gray_sync1 <= (others => '0'); wraddr_gray_sync2 <= (others => '0'); elsif (clk_r'event and clk_r = '1' and if_read_ce = '1') then empty <= empty_next; rdaddr_bin <= rdaddr_bin_next; rdaddr_gray_sync0 <= rdaddr_gray_next; wraddr_gray_sync1 <= wraddr_gray_sync0; wraddr_gray_sync2 <= wraddr_gray_sync1; end if; end process; -- write mem process(clk_w) begin if (clk_w'event and clk_w = '1' and if_write_ce = '1') then if (full = '0' and if_write = '1') then mem(to_integer(unsigned(wraddr))) <= if_din; end if; end if; end process; -- read mem process(clk_r) begin if (clk_r'event and clk_r = '1' and if_read_ce = '1') then dout_buf <= mem(to_integer(unsigned(rdaddr))); end if; end process; end architecture;
lgpl-3.0
c47398d2792038f23f31e00b58ad7256
0.553159
3.399884
false
false
false
false
grwlf/vsim
vhdl_ct/ct00308.vhd
1
4,453
-- NEED RESULT: ARCH00308: Access types passed ------------------------------------------------------------------------------- -- -- Copyright (c) 1989 by Intermetrics, Inc. -- All rights reserved. -- ------------------------------------------------------------------------------- -- -- TEST NAME: -- -- CT00308 -- -- AUTHOR: -- -- D. Hyman -- -- TEST OBJECTIVES: -- -- 3.3 (1) -- 3.3 (2) -- 3.3 (3) -- 3.3 (4) -- 3.3 (5) -- 3.3 (6) -- 3.3 (7) -- 3.3.1 (1) -- 3.3.1 (2) -- 3.3.2 (1) -- -- DESIGN UNIT ORDERING: -- -- ENT00308(ARCH00308) -- ENT00308_Test_Bench(ARCH00308_Test_Bench) -- -- REVISION HISTORY: -- -- 27-JUL-1987 - initial revision -- -- NOTES: -- -- self-checking -- -- ONLY 3.3 (1) IS DYNAMICALLY TESTED. -- -- use WORK.STANDARD_TYPES.all ; entity ENT00308 is generic ( gen1, gen2 : integer := 5 ) ; begin end ENT00308 ; architecture ARCH00308 of ENT00308 is -- this tests 3.3 (7) procedure proc ( v1, v2 : integer ) is type t1 is array (v1 to 10) of boolean; type t2 is array (v1 to v2) of bit; type t3 is array (1 to v2) of integer; type rec is record a1 : t1 ; a2 : t2 ; a3 : t3 ; end record ; type access_t1 is access t1 ; type access_t2 is access t2 ; type access_t3 is access t3 ; type access_rec is access rec ; variable a_t1 : access_t1 ; -- this tests 3.3 (2) variable a_t2 : access_t1 ; variable a_t3 : access_t1 ; variable a_r : access_t1 ; begin end proc ; begin P : process -- 3.3 (3), 3.3 (4), and 3.3 (5) are tested by the access types -- declared in STANDARD_TYPES, except for access of access types, -- which is the following: type access_access is access WORK.STANDARD_TYPES.a_bit ; -- these will test 3.3 (6) type t1 is array (1 to 10) of boolean; type t2 is array (gen1 to gen2) of bit; type record_with_array_elements is record a1 : t1 ; a2 : t2 ; end record ; type access_t1 is access t1 ; type access_record is access record_with_array_elements ; variable a_a : access_access ; variable a_t : access_t1 ; variable a_r : access_record ; -- these test 3.3.1 (1) and 3.3.2 (2) type object_1 ; type object_2 ; type access_object_1 is access object_1 ; type access_object_2 is access object_2 ; type object_1 is ('*') ; type object_2 is ('*') ; type array_1 is array ( integer range <> ) of access_object_1 ; type array_2 is array ( integer range <> ) of access_object_2 ; type access_array_1 is access array_1 ; type access_array_2 is access array_2 ; type structure_1 is record data1 : integer ; data2 : integer ; link : access_array_2 ; end record ; type structure_2 is record data1 : integer ; data2 : integer ; link : access_array_1 ; end record ; variable a_o_1 : access_object_1 ; variable a_o_2 : access_object_2 ; variable a_a_1 : access_array_1 ; variable a_a_2 : access_array_2 ; begin test_report ( "ARCH00308" , "Access types" , (a_a = null) and -- this tests 3.3 (1) (a_t = null) and (a_r = null) and (a_o_1 = null) and (a_o_2 = null) and (a_a_1 = null) and (a_a_2 = null) ) ; -- these test 3.3.2 (1) deallocate (a_a) ; deallocate (a_t) ; deallocate (a_r) ; deallocate (a_o_1) ; deallocate (a_o_2) ; deallocate (a_a_1) ; deallocate (a_a_2) ; wait ; end process P ; end ARCH00308 ; entity ENT00308_Test_Bench is end ENT00308_Test_Bench ; architecture ARCH00308_Test_Bench of ENT00308_Test_Bench is begin L1: block component UUT end component ; for CIS1 : UUT use entity WORK.ENT00308 ( ARCH00308 ) ; begin CIS1 : UUT ; end block L1 ; end ARCH00308_Test_Bench ;
gpl-3.0
d35f92931477d80698a3dcd750793f7b
0.48327
3.360755
false
true
false
false
grwlf/vsim
vhdl_ct/ct00400.vhd
1
16,624
-- NEED RESULT: ARCH00400.P1: Multi inertial transactions occurred on concurrent signal asg passed -- NEED RESULT: ARCH00400.P2: Multi inertial transactions occurred on concurrent signal asg passed -- NEED RESULT: ARCH00400: One inertial transaction occurred on a concurrent signal asg passed -- NEED RESULT: ARCH00400: One inertial transaction occurred on a concurrent signal asg passed -- NEED RESULT: ARCH00400: Old transactions were removed on a concurrent signal asg passed -- NEED RESULT: ARCH00400: Old transactions were removed on a concurrent signal asg passed -- NEED RESULT: ARCH00400: One inertial transaction occurred on a concurrent signal asg passed -- NEED RESULT: ARCH00400: One inertial transaction occurred on a concurrent signal asg passed -- NEED RESULT: ARCH00400: Inertial semantics check on a concurrent signal asg passed -- NEED RESULT: ARCH00400: Inertial semantics check on a concurrent signal asg passed -- NEED RESULT: P2: Inertial transactions completed entirely passed -- NEED RESULT: P1: Inertial transactions completed entirely passed ------------------------------------------------------------------------------- -- -- Copyright (c) 1989 by Intermetrics, Inc. -- All rights reserved. -- ------------------------------------------------------------------------------- -- -- TEST NAME: -- -- CT00400 -- -- AUTHOR: -- -- G. Tominovich -- -- TEST OBJECTIVES: -- -- 9.5 (3) -- 9.5.1 (1) -- 9.5.1 (2) -- -- DESIGN UNIT ORDERING: -- -- ENT00400(ARCH00400) -- ENT00400_Test_Bench(ARCH00400_Test_Bench) -- -- REVISION HISTORY: -- -- 30-JUL-1987 - initial revision -- -- NOTES: -- -- self-checking -- automatically generated -- use WORK.STANDARD_TYPES.all ; entity ENT00400 is port ( s_st_arr2_vector : inout st_arr2_vector ; s_st_arr3_vector : inout st_arr3_vector ) ; subtype chk_sig_type is integer range -1 to 100 ; signal chk_st_arr2_vector : chk_sig_type := -1 ; signal chk_st_arr3_vector : chk_sig_type := -1 ; -- end ENT00400 ; -- -- architecture ARCH00400 of ENT00400 is subtype chk_time_type is Time ; signal s_st_arr2_vector_savt : chk_time_type := 0 ns ; signal s_st_arr3_vector_savt : chk_time_type := 0 ns ; -- subtype chk_cnt_type is Integer ; signal s_st_arr2_vector_cnt : chk_cnt_type := 0 ; signal s_st_arr3_vector_cnt : chk_cnt_type := 0 ; -- type select_type is range 1 to 6 ; signal st_arr2_vector_select : select_type := 1 ; signal st_arr3_vector_select : select_type := 1 ; -- begin CHG1 : process variable correct : boolean ; begin case s_st_arr2_vector_cnt is when 0 => null ; -- s_st_arr2_vector(lowb)(highb,false) <= -- c_st_arr2_vector_2(lowb)(highb,false) after 10 ns, -- c_st_arr2_vector_1(lowb)(highb,false) after 20 ns ; -- when 1 => correct := s_st_arr2_vector(lowb)(highb,false) = c_st_arr2_vector_2(lowb)(highb,false) and (s_st_arr2_vector_savt + 10 ns) = Std.Standard.Now ; -- when 2 => correct := correct and s_st_arr2_vector(lowb)(highb,false) = c_st_arr2_vector_1(lowb)(highb,false) and (s_st_arr2_vector_savt + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00400.P1" , "Multi inertial transactions occurred on " & "concurrent signal asg", correct ) ; -- st_arr2_vector_select <= transport 2 ; -- s_st_arr2_vector(lowb)(highb,false) <= -- c_st_arr2_vector_2(lowb)(highb,false) after 10 ns , -- c_st_arr2_vector_1(lowb)(highb,false) after 20 ns , -- c_st_arr2_vector_2(lowb)(highb,false) after 30 ns , -- c_st_arr2_vector_1(lowb)(highb,false) after 40 ns ; -- when 3 => correct := s_st_arr2_vector(lowb)(highb,false) = c_st_arr2_vector_2(lowb)(highb,false) and (s_st_arr2_vector_savt + 10 ns) = Std.Standard.Now ; st_arr2_vector_select <= transport 3 ; -- s_st_arr2_vector(lowb)(highb,false) <= -- c_st_arr2_vector_1(lowb)(highb,false) after 5 ns ; -- when 4 => correct := correct and s_st_arr2_vector(lowb)(highb,false) = c_st_arr2_vector_1(lowb)(highb,false) and (s_st_arr2_vector_savt + 5 ns) = Std.Standard.Now ; test_report ( "ARCH00400" , "One inertial transaction occurred on a " & "concurrent signal asg", correct ) ; st_arr2_vector_select <= transport 4 ; -- s_st_arr2_vector(lowb)(highb,false) <= -- c_st_arr2_vector_1(lowb)(highb,false) after 100 ns ; -- when 5 => correct := correct and s_st_arr2_vector(lowb)(highb,false) = c_st_arr2_vector_1(lowb)(highb,false) and (s_st_arr2_vector_savt + 100 ns) = Std.Standard.Now ; test_report ( "ARCH00400" , "Old transactions were removed on a " & "concurrent signal asg", correct ) ; st_arr2_vector_select <= transport 5 ; -- s_st_arr2_vector(lowb)(highb,false) <= -- c_st_arr2_vector_2(lowb)(highb,false) after 10 ns , -- c_st_arr2_vector_1(lowb)(highb,false) after 20 ns , -- c_st_arr2_vector_2(lowb)(highb,false) after 30 ns , -- c_st_arr2_vector_1(lowb)(highb,false) after 40 ns ; -- when 6 => correct := correct and s_st_arr2_vector(lowb)(highb,false) = c_st_arr2_vector_2(lowb)(highb,false) and (s_st_arr2_vector_savt + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00400" , "One inertial transaction occurred on a " & "concurrent signal asg", correct ) ; st_arr2_vector_select <= transport 6 ; -- Last transaction above is marked -- s_st_arr2_vector(lowb)(highb,false) <= -- c_st_arr2_vector_1(lowb)(highb,false) after 40 ns ; -- when 7 => correct := correct and s_st_arr2_vector(lowb)(highb,false) = c_st_arr2_vector_1(lowb)(highb,false) and (s_st_arr2_vector_savt + 30 ns) = Std.Standard.Now ; -- when 8 => correct := correct and s_st_arr2_vector(lowb)(highb,false) = c_st_arr2_vector_1(lowb)(highb,false) and (s_st_arr2_vector_savt + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00400" , "Inertial semantics check on a concurrent " & "signal asg", correct ) ; -- when others => -- No more transactions should have occurred test_report ( "ARCH00400" , "Inertial semantics check on a concurrent " & "signal asg", false ) ; -- end case ; -- s_st_arr2_vector_savt <= transport Std.Standard.Now ; chk_st_arr2_vector <= transport s_st_arr2_vector_cnt after (1 us - Std.Standard.Now) ; s_st_arr2_vector_cnt <= transport s_st_arr2_vector_cnt + 1 ; wait until (not s_st_arr2_vector(lowb)(highb,false)'Quiet) and (s_st_arr2_vector_savt /= Std.Standard.Now) ; -- end process CHG1 ; -- PGEN_CHKP_1 : process ( chk_st_arr2_vector ) begin if Std.Standard.Now > 0 ns then test_report ( "P1" , "Inertial transactions completed entirely", chk_st_arr2_vector = 8 ) ; end if ; end process PGEN_CHKP_1 ; -- -- s_st_arr2_vector(lowb)(highb,false) <= c_st_arr2_vector_2(lowb)(highb,false) after 10 ns, c_st_arr2_vector_1(lowb)(highb,false) after 20 ns when st_arr2_vector_select = 1 else -- c_st_arr2_vector_2(lowb)(highb,false) after 10 ns , c_st_arr2_vector_1(lowb)(highb,false) after 20 ns , c_st_arr2_vector_2(lowb)(highb,false) after 30 ns , c_st_arr2_vector_1(lowb)(highb,false) after 40 ns when st_arr2_vector_select = 2 else -- c_st_arr2_vector_1(lowb)(highb,false) after 5 ns when st_arr2_vector_select = 3 else -- c_st_arr2_vector_1(lowb)(highb,false) after 100 ns when st_arr2_vector_select = 4 else -- c_st_arr2_vector_2(lowb)(highb,false) after 10 ns , c_st_arr2_vector_1(lowb)(highb,false) after 20 ns , c_st_arr2_vector_2(lowb)(highb,false) after 30 ns , c_st_arr2_vector_1(lowb)(highb,false) after 40 ns when st_arr2_vector_select = 5 else -- -- Last transaction above is marked c_st_arr2_vector_1(lowb)(highb,false) after 40 ns ; -- CHG2 : process variable correct : boolean ; begin case s_st_arr3_vector_cnt is when 0 => null ; -- s_st_arr3_vector(highb)(lowb,true) <= -- c_st_arr3_vector_2(highb)(lowb,true) after 10 ns, -- c_st_arr3_vector_1(highb)(lowb,true) after 20 ns ; -- when 1 => correct := s_st_arr3_vector(highb)(lowb,true) = c_st_arr3_vector_2(highb)(lowb,true) and (s_st_arr3_vector_savt + 10 ns) = Std.Standard.Now ; -- when 2 => correct := correct and s_st_arr3_vector(highb)(lowb,true) = c_st_arr3_vector_1(highb)(lowb,true) and (s_st_arr3_vector_savt + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00400.P2" , "Multi inertial transactions occurred on " & "concurrent signal asg", correct ) ; -- st_arr3_vector_select <= transport 2 ; -- s_st_arr3_vector(highb)(lowb,true) <= -- c_st_arr3_vector_2(highb)(lowb,true) after 10 ns , -- c_st_arr3_vector_1(highb)(lowb,true) after 20 ns , -- c_st_arr3_vector_2(highb)(lowb,true) after 30 ns , -- c_st_arr3_vector_1(highb)(lowb,true) after 40 ns ; -- when 3 => correct := s_st_arr3_vector(highb)(lowb,true) = c_st_arr3_vector_2(highb)(lowb,true) and (s_st_arr3_vector_savt + 10 ns) = Std.Standard.Now ; st_arr3_vector_select <= transport 3 ; -- s_st_arr3_vector(highb)(lowb,true) <= -- c_st_arr3_vector_1(highb)(lowb,true) after 5 ns ; -- when 4 => correct := correct and s_st_arr3_vector(highb)(lowb,true) = c_st_arr3_vector_1(highb)(lowb,true) and (s_st_arr3_vector_savt + 5 ns) = Std.Standard.Now ; test_report ( "ARCH00400" , "One inertial transaction occurred on a " & "concurrent signal asg", correct ) ; st_arr3_vector_select <= transport 4 ; -- s_st_arr3_vector(highb)(lowb,true) <= -- c_st_arr3_vector_1(highb)(lowb,true) after 100 ns ; -- when 5 => correct := correct and s_st_arr3_vector(highb)(lowb,true) = c_st_arr3_vector_1(highb)(lowb,true) and (s_st_arr3_vector_savt + 100 ns) = Std.Standard.Now ; test_report ( "ARCH00400" , "Old transactions were removed on a " & "concurrent signal asg", correct ) ; st_arr3_vector_select <= transport 5 ; -- s_st_arr3_vector(highb)(lowb,true) <= -- c_st_arr3_vector_2(highb)(lowb,true) after 10 ns , -- c_st_arr3_vector_1(highb)(lowb,true) after 20 ns , -- c_st_arr3_vector_2(highb)(lowb,true) after 30 ns , -- c_st_arr3_vector_1(highb)(lowb,true) after 40 ns ; -- when 6 => correct := correct and s_st_arr3_vector(highb)(lowb,true) = c_st_arr3_vector_2(highb)(lowb,true) and (s_st_arr3_vector_savt + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00400" , "One inertial transaction occurred on a " & "concurrent signal asg", correct ) ; st_arr3_vector_select <= transport 6 ; -- Last transaction above is marked -- s_st_arr3_vector(highb)(lowb,true) <= -- c_st_arr3_vector_1(highb)(lowb,true) after 40 ns ; -- when 7 => correct := correct and s_st_arr3_vector(highb)(lowb,true) = c_st_arr3_vector_1(highb)(lowb,true) and (s_st_arr3_vector_savt + 30 ns) = Std.Standard.Now ; -- when 8 => correct := correct and s_st_arr3_vector(highb)(lowb,true) = c_st_arr3_vector_1(highb)(lowb,true) and (s_st_arr3_vector_savt + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00400" , "Inertial semantics check on a concurrent " & "signal asg", correct ) ; -- when others => -- No more transactions should have occurred test_report ( "ARCH00400" , "Inertial semantics check on a concurrent " & "signal asg", false ) ; -- end case ; -- s_st_arr3_vector_savt <= transport Std.Standard.Now ; chk_st_arr3_vector <= transport s_st_arr3_vector_cnt after (1 us - Std.Standard.Now) ; s_st_arr3_vector_cnt <= transport s_st_arr3_vector_cnt + 1 ; wait until (not s_st_arr3_vector(highb)(lowb,true)'Quiet) and (s_st_arr3_vector_savt /= Std.Standard.Now) ; -- end process CHG2 ; -- PGEN_CHKP_2 : process ( chk_st_arr3_vector ) begin if Std.Standard.Now > 0 ns then test_report ( "P2" , "Inertial transactions completed entirely", chk_st_arr3_vector = 8 ) ; end if ; end process PGEN_CHKP_2 ; -- -- s_st_arr3_vector(highb)(lowb,true) <= c_st_arr3_vector_2(highb)(lowb,true) after 10 ns, c_st_arr3_vector_1(highb)(lowb,true) after 20 ns when st_arr3_vector_select = 1 else -- c_st_arr3_vector_2(highb)(lowb,true) after 10 ns , c_st_arr3_vector_1(highb)(lowb,true) after 20 ns , c_st_arr3_vector_2(highb)(lowb,true) after 30 ns , c_st_arr3_vector_1(highb)(lowb,true) after 40 ns when st_arr3_vector_select = 2 else -- c_st_arr3_vector_1(highb)(lowb,true) after 5 ns when st_arr3_vector_select = 3 else -- c_st_arr3_vector_1(highb)(lowb,true) after 100 ns when st_arr3_vector_select = 4 else -- c_st_arr3_vector_2(highb)(lowb,true) after 10 ns , c_st_arr3_vector_1(highb)(lowb,true) after 20 ns , c_st_arr3_vector_2(highb)(lowb,true) after 30 ns , c_st_arr3_vector_1(highb)(lowb,true) after 40 ns when st_arr3_vector_select = 5 else -- -- Last transaction above is marked c_st_arr3_vector_1(highb)(lowb,true) after 40 ns ; -- end ARCH00400 ; -- -- use WORK.STANDARD_TYPES.all ; entity ENT00400_Test_Bench is signal s_st_arr2_vector : st_arr2_vector := c_st_arr2_vector_1 ; signal s_st_arr3_vector : st_arr3_vector := c_st_arr3_vector_1 ; -- end ENT00400_Test_Bench ; -- -- architecture ARCH00400_Test_Bench of ENT00400_Test_Bench is begin L1: block component UUT port ( s_st_arr2_vector : inout st_arr2_vector ; s_st_arr3_vector : inout st_arr3_vector ) ; end component ; -- for CIS1 : UUT use entity WORK.ENT00400 ( ARCH00400 ) ; begin CIS1 : UUT port map ( s_st_arr2_vector , s_st_arr3_vector ) ; end block L1 ; end ARCH00400_Test_Bench ;
gpl-3.0
96187a93cfd669d400f3cf7200f88b4d
0.524423
3.280837
false
true
false
false
grwlf/vsim
vhdl_ct/ct00583.vhd
1
5,821
-- NEED RESULT: ARCH00583: Attribute declarations - scalar generic subtypes with dynamic initial values passed ------------------------------------------------------------------------------- -- -- Copyright (c) 1989 by Intermetrics, Inc. -- All rights reserved. -- ------------------------------------------------------------------------------- -- -- TEST NAME: -- -- CT00583 -- -- AUTHOR: -- -- A. Wilmot -- -- TEST OBJECTIVES: -- -- 4.4 (5) -- -- DESIGN UNIT ORDERING: -- -- GENERIC_STANDARD_TYPES(ARCH00583) -- ENT00583_Test_Bench(ARCH00583_Test_Bench) -- -- REVISION HISTORY: -- -- 19-AUG-1987 - initial revision -- -- NOTES: -- -- self-checking -- automatically generated -- use WORK.STANDARD_TYPES.test_report ; -- architecture ARCH00583 of GENERIC_STANDARD_TYPES is attribute at_boolean_1 : boolean ; attribute at_bit_1 : bit ; attribute at_severity_level_1 : severity_level ; attribute at_character_1 : character ; attribute at_t_enum1_1 : t_enum1 ; attribute at_st_enum1_1 : st_enum1 ; attribute at_integer_1 : integer ; attribute at_t_int1_1 : t_int1 ; attribute at_st_int1_1 : st_int1 ; attribute at_time_1 : time ; attribute at_t_phys1_1 : t_phys1 ; attribute at_st_phys1_1 : st_phys1 ; attribute at_real_1 : real ; attribute at_t_real1_1 : t_real1 ; attribute at_st_real1_1 : st_real1 ; procedure p2 ( i_boolean_1, i_boolean_2 : boolean := c_boolean_1 ; i_bit_1, i_bit_2 : bit := c_bit_1 ; i_severity_level_1, i_severity_level_2 : severity_level := c_severity_level_1 ; i_character_1, i_character_2 : character := c_character_1 ; i_t_enum1_1, i_t_enum1_2 : t_enum1 := c_t_enum1_1 ; i_st_enum1_1, i_st_enum1_2 : st_enum1 := c_st_enum1_1 ; i_integer_1, i_integer_2 : integer := c_integer_1 ; i_t_int1_1, i_t_int1_2 : t_int1 := c_t_int1_1 ; i_st_int1_1, i_st_int1_2 : st_int1 := c_st_int1_1 ; i_time_1, i_time_2 : time := c_time_1 ; i_t_phys1_1, i_t_phys1_2 : t_phys1 := c_t_phys1_1 ; i_st_phys1_1, i_st_phys1_2 : st_phys1 := c_st_phys1_1 ; i_real_1, i_real_2 : real := c_real_1 ; i_t_real1_1, i_t_real1_2 : t_real1 := c_t_real1_1 ; i_st_real1_1, i_st_real1_2 : st_real1 := c_st_real1_1 ) is procedure p1 ; attribute at_boolean_1 of p1 : procedure is i_boolean_1 ; attribute at_bit_1 of p1 : procedure is i_bit_1 ; attribute at_severity_level_1 of p1 : procedure is i_severity_level_1 ; attribute at_character_1 of p1 : procedure is i_character_1 ; attribute at_t_enum1_1 of p1 : procedure is i_t_enum1_1 ; attribute at_st_enum1_1 of p1 : procedure is i_st_enum1_1 ; attribute at_integer_1 of p1 : procedure is i_integer_1 ; attribute at_t_int1_1 of p1 : procedure is i_t_int1_1 ; attribute at_st_int1_1 of p1 : procedure is i_st_int1_1 ; attribute at_time_1 of p1 : procedure is i_time_1 ; attribute at_t_phys1_1 of p1 : procedure is i_t_phys1_1 ; attribute at_st_phys1_1 of p1 : procedure is i_st_phys1_1 ; attribute at_real_1 of p1 : procedure is i_real_1 ; attribute at_t_real1_1 of p1 : procedure is i_t_real1_1 ; attribute at_st_real1_1 of p1 : procedure is i_st_real1_1 ; procedure p1 is variable correct : boolean := true ; begin correct := correct and p1'at_boolean_1 = c_boolean_1 ; correct := correct and p1'at_bit_1 = c_bit_1 ; correct := correct and p1'at_severity_level_1 = c_severity_level_1 ; correct := correct and p1'at_character_1 = c_character_1 ; correct := correct and p1'at_t_enum1_1 = c_t_enum1_1 ; correct := correct and p1'at_st_enum1_1 = c_st_enum1_1 ; correct := correct and p1'at_integer_1 = c_integer_1 ; correct := correct and p1'at_t_int1_1 = c_t_int1_1 ; correct := correct and p1'at_st_int1_1 = c_st_int1_1 ; correct := correct and p1'at_time_1 = c_time_1 ; correct := correct and p1'at_t_phys1_1 = c_t_phys1_1 ; correct := correct and p1'at_st_phys1_1 = c_st_phys1_1 ; correct := correct and p1'at_real_1 = c_real_1 ; correct := correct and p1'at_t_real1_1 = c_t_real1_1 ; correct := correct and p1'at_st_real1_1 = c_st_real1_1 ; test_report ( "ARCH00583" , "Attribute declarations - scalar generic subtypes" & " with dynamic initial values" , correct) ; end p1 ; begin p1 ; end p2 ; begin process begin p2 ; wait ; end process ; end ARCH00583 ; -- entity ENT00583_Test_Bench is end ENT00583_Test_Bench ; -- architecture ARCH00583_Test_Bench of ENT00583_Test_Bench is begin L1: block component UUT end component ; for CIS1 : UUT use entity WORK.GENERIC_STANDARD_TYPES ( ARCH00583 ) ; begin CIS1 : UUT ; end block L1 ; end ARCH00583_Test_Bench ;
gpl-3.0
7b05619800bb91dc65035f7567e09496
0.498712
3.21958
false
true
false
false
jairov4/accel-oil
impl/impl_test_single/hdl/system_clock_generator_0_wrapper.vhd
1
3,263
------------------------------------------------------------------------------- -- system_clock_generator_0_wrapper.vhd ------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; library clock_generator_0_v4_03_a; use clock_generator_0_v4_03_a.all; library clock_generator_v4_03_a; use clock_generator_v4_03_a.all; entity system_clock_generator_0_wrapper is port ( CLKIN : in std_logic; CLKOUT0 : out std_logic; CLKOUT1 : out std_logic; CLKOUT2 : out std_logic; CLKOUT3 : out std_logic; CLKOUT4 : out std_logic; CLKOUT5 : out std_logic; CLKOUT6 : out std_logic; CLKOUT7 : out std_logic; CLKOUT8 : out std_logic; CLKOUT9 : out std_logic; CLKOUT10 : out std_logic; CLKOUT11 : out std_logic; CLKOUT12 : out std_logic; CLKOUT13 : out std_logic; CLKOUT14 : out std_logic; CLKOUT15 : out std_logic; CLKFBIN : in std_logic; CLKFBOUT : out std_logic; PSCLK : in std_logic; PSEN : in std_logic; PSINCDEC : in std_logic; PSDONE : out std_logic; RST : in std_logic; LOCKED : out std_logic ); attribute x_core_info : STRING; attribute x_core_info of system_clock_generator_0_wrapper : entity is "clock_generator_v4_03_a"; end system_clock_generator_0_wrapper; architecture STRUCTURE of system_clock_generator_0_wrapper is component clock_generator is generic ( C_FAMILY : STRING; C_DEVICE : STRING; C_PACKAGE : STRING; C_SPEEDGRADE : STRING ); port ( CLKIN : in std_logic; CLKOUT0 : out std_logic; CLKOUT1 : out std_logic; CLKOUT2 : out std_logic; CLKOUT3 : out std_logic; CLKOUT4 : out std_logic; CLKOUT5 : out std_logic; CLKOUT6 : out std_logic; CLKOUT7 : out std_logic; CLKOUT8 : out std_logic; CLKOUT9 : out std_logic; CLKOUT10 : out std_logic; CLKOUT11 : out std_logic; CLKOUT12 : out std_logic; CLKOUT13 : out std_logic; CLKOUT14 : out std_logic; CLKOUT15 : out std_logic; CLKFBIN : in std_logic; CLKFBOUT : out std_logic; PSCLK : in std_logic; PSEN : in std_logic; PSINCDEC : in std_logic; PSDONE : out std_logic; RST : in std_logic; LOCKED : out std_logic ); end component; begin clock_generator_0 : clock_generator generic map ( C_FAMILY => "virtex5", C_DEVICE => "5vlx50t", C_PACKAGE => "ff1136", C_SPEEDGRADE => "-2" ) port map ( CLKIN => CLKIN, CLKOUT0 => CLKOUT0, CLKOUT1 => CLKOUT1, CLKOUT2 => CLKOUT2, CLKOUT3 => CLKOUT3, CLKOUT4 => CLKOUT4, CLKOUT5 => CLKOUT5, CLKOUT6 => CLKOUT6, CLKOUT7 => CLKOUT7, CLKOUT8 => CLKOUT8, CLKOUT9 => CLKOUT9, CLKOUT10 => CLKOUT10, CLKOUT11 => CLKOUT11, CLKOUT12 => CLKOUT12, CLKOUT13 => CLKOUT13, CLKOUT14 => CLKOUT14, CLKOUT15 => CLKOUT15, CLKFBIN => CLKFBIN, CLKFBOUT => CLKFBOUT, PSCLK => PSCLK, PSEN => PSEN, PSINCDEC => PSINCDEC, PSDONE => PSDONE, RST => RST, LOCKED => LOCKED ); end architecture STRUCTURE;
lgpl-3.0
408c61dbbf045694839910f051558a91
0.57585
3.637681
false
false
false
false
jairov4/accel-oil
solution_spartan3/syn/vhdl/nfa_accept_samples_generic_hw.vhd
1
85,839
-- ============================================================== -- RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC -- Version: 2013.4 -- Copyright (C) 2013 Xilinx Inc. All rights reserved. -- -- =========================================================== library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; entity nfa_accept_samples_generic_hw is port ( ap_clk : IN STD_LOGIC; ap_rst : IN STD_LOGIC; ap_start : IN STD_LOGIC; ap_done : OUT STD_LOGIC; ap_idle : OUT STD_LOGIC; ap_ready : OUT STD_LOGIC; nfa_initials_buckets_req_din : OUT STD_LOGIC; nfa_initials_buckets_req_full_n : IN STD_LOGIC; nfa_initials_buckets_req_write : OUT STD_LOGIC; nfa_initials_buckets_rsp_empty_n : IN STD_LOGIC; nfa_initials_buckets_rsp_read : OUT STD_LOGIC; nfa_initials_buckets_address : OUT STD_LOGIC_VECTOR (31 downto 0); nfa_initials_buckets_datain : IN STD_LOGIC_VECTOR (31 downto 0); nfa_initials_buckets_dataout : OUT STD_LOGIC_VECTOR (31 downto 0); nfa_initials_buckets_size : OUT STD_LOGIC_VECTOR (31 downto 0); nfa_finals_buckets_req_din : OUT STD_LOGIC; nfa_finals_buckets_req_full_n : IN STD_LOGIC; nfa_finals_buckets_req_write : OUT STD_LOGIC; nfa_finals_buckets_rsp_empty_n : IN STD_LOGIC; nfa_finals_buckets_rsp_read : OUT STD_LOGIC; nfa_finals_buckets_address : OUT STD_LOGIC_VECTOR (31 downto 0); nfa_finals_buckets_datain : IN STD_LOGIC_VECTOR (31 downto 0); nfa_finals_buckets_dataout : OUT STD_LOGIC_VECTOR (31 downto 0); nfa_finals_buckets_size : OUT STD_LOGIC_VECTOR (31 downto 0); nfa_forward_buckets_req_din : OUT STD_LOGIC; nfa_forward_buckets_req_full_n : IN STD_LOGIC; nfa_forward_buckets_req_write : OUT STD_LOGIC; nfa_forward_buckets_rsp_empty_n : IN STD_LOGIC; nfa_forward_buckets_rsp_read : OUT STD_LOGIC; nfa_forward_buckets_address : OUT STD_LOGIC_VECTOR (31 downto 0); nfa_forward_buckets_datain : IN STD_LOGIC_VECTOR (31 downto 0); nfa_forward_buckets_dataout : OUT STD_LOGIC_VECTOR (31 downto 0); nfa_forward_buckets_size : OUT STD_LOGIC_VECTOR (31 downto 0); nfa_symbols : IN STD_LOGIC_VECTOR (7 downto 0); sample_buffer_req_din : OUT STD_LOGIC; sample_buffer_req_full_n : IN STD_LOGIC; sample_buffer_req_write : OUT STD_LOGIC; sample_buffer_rsp_empty_n : IN STD_LOGIC; sample_buffer_rsp_read : OUT STD_LOGIC; sample_buffer_address : OUT STD_LOGIC_VECTOR (31 downto 0); sample_buffer_datain : IN STD_LOGIC_VECTOR (7 downto 0); sample_buffer_dataout : OUT STD_LOGIC_VECTOR (7 downto 0); sample_buffer_size : OUT STD_LOGIC_VECTOR (31 downto 0); sample_buffer_length : IN STD_LOGIC_VECTOR (31 downto 0); sample_length : IN STD_LOGIC_VECTOR (15 downto 0); indices_begin_req_din : OUT STD_LOGIC; indices_begin_req_full_n : IN STD_LOGIC; indices_begin_req_write : OUT STD_LOGIC; indices_begin_rsp_empty_n : IN STD_LOGIC; indices_begin_rsp_read : OUT STD_LOGIC; indices_begin_address : OUT STD_LOGIC_VECTOR (31 downto 0); indices_begin_datain : IN STD_LOGIC_VECTOR (31 downto 0); indices_begin_dataout : OUT STD_LOGIC_VECTOR (31 downto 0); indices_begin_size : OUT STD_LOGIC_VECTOR (31 downto 0); indices_samples_req_din : OUT STD_LOGIC; indices_samples_req_full_n : IN STD_LOGIC; indices_samples_req_write : OUT STD_LOGIC; indices_samples_rsp_empty_n : IN STD_LOGIC; indices_samples_rsp_read : OUT STD_LOGIC; indices_samples_address : OUT STD_LOGIC_VECTOR (31 downto 0); indices_samples_datain : IN STD_LOGIC_VECTOR (15 downto 0); indices_samples_dataout : OUT STD_LOGIC_VECTOR (15 downto 0); indices_samples_size : OUT STD_LOGIC_VECTOR (31 downto 0); indices_stride_req_din : OUT STD_LOGIC; indices_stride_req_full_n : IN STD_LOGIC; indices_stride_req_write : OUT STD_LOGIC; indices_stride_rsp_empty_n : IN STD_LOGIC; indices_stride_rsp_read : OUT STD_LOGIC; indices_stride_address : OUT STD_LOGIC_VECTOR (31 downto 0); indices_stride_datain : IN STD_LOGIC_VECTOR (7 downto 0); indices_stride_dataout : OUT STD_LOGIC_VECTOR (7 downto 0); indices_stride_size : OUT STD_LOGIC_VECTOR (31 downto 0); i_size : IN STD_LOGIC_VECTOR (15 downto 0); begin_index : IN STD_LOGIC_VECTOR (15 downto 0); begin_sample : IN STD_LOGIC_VECTOR (15 downto 0); end_index : IN STD_LOGIC_VECTOR (15 downto 0); end_sample : IN STD_LOGIC_VECTOR (15 downto 0); stop_on_first : IN STD_LOGIC_VECTOR (0 downto 0); accept : IN STD_LOGIC_VECTOR (0 downto 0); ap_return : OUT STD_LOGIC_VECTOR (31 downto 0) ); end; architecture behav of nfa_accept_samples_generic_hw is attribute CORE_GENERATION_INFO : STRING; attribute CORE_GENERATION_INFO of behav : architecture is "nfa_accept_samples_generic_hw,hls_ip_2013_4,{HLS_INPUT_TYPE=c,HLS_INPUT_FLOAT=0,HLS_INPUT_FIXED=0,HLS_INPUT_PART=xc3s200avq100-5,HLS_INPUT_CLOCK=1.000000,HLS_INPUT_ARCH=others,HLS_SYN_CLOCK=3.449000,HLS_SYN_LAT=117874014,HLS_SYN_TPT=none,HLS_SYN_MEM=0,HLS_SYN_DSP=0,HLS_SYN_FF=0,HLS_SYN_LUT=0}"; constant ap_const_logic_1 : STD_LOGIC := '1'; constant ap_const_logic_0 : STD_LOGIC := '0'; constant ap_ST_st1_fsm_0 : STD_LOGIC_VECTOR (5 downto 0) := "000000"; constant ap_ST_st2_fsm_1 : STD_LOGIC_VECTOR (5 downto 0) := "000001"; constant ap_ST_st3_fsm_2 : STD_LOGIC_VECTOR (5 downto 0) := "000010"; constant ap_ST_st4_fsm_3 : STD_LOGIC_VECTOR (5 downto 0) := "000011"; constant ap_ST_st5_fsm_4 : STD_LOGIC_VECTOR (5 downto 0) := "000100"; constant ap_ST_st6_fsm_5 : STD_LOGIC_VECTOR (5 downto 0) := "000101"; constant ap_ST_st7_fsm_6 : STD_LOGIC_VECTOR (5 downto 0) := "000110"; constant ap_ST_st8_fsm_7 : STD_LOGIC_VECTOR (5 downto 0) := "000111"; constant ap_ST_st9_fsm_8 : STD_LOGIC_VECTOR (5 downto 0) := "001000"; constant ap_ST_st10_fsm_9 : STD_LOGIC_VECTOR (5 downto 0) := "001001"; constant ap_ST_st11_fsm_10 : STD_LOGIC_VECTOR (5 downto 0) := "001010"; constant ap_ST_st12_fsm_11 : STD_LOGIC_VECTOR (5 downto 0) := "001011"; constant ap_ST_st13_fsm_12 : STD_LOGIC_VECTOR (5 downto 0) := "001100"; constant ap_ST_st14_fsm_13 : STD_LOGIC_VECTOR (5 downto 0) := "001101"; constant ap_ST_st15_fsm_14 : STD_LOGIC_VECTOR (5 downto 0) := "001110"; constant ap_ST_st16_fsm_15 : STD_LOGIC_VECTOR (5 downto 0) := "001111"; constant ap_ST_st17_fsm_16 : STD_LOGIC_VECTOR (5 downto 0) := "010000"; constant ap_ST_st18_fsm_17 : STD_LOGIC_VECTOR (5 downto 0) := "010001"; constant ap_ST_st19_fsm_18 : STD_LOGIC_VECTOR (5 downto 0) := "010010"; constant ap_ST_st20_fsm_19 : STD_LOGIC_VECTOR (5 downto 0) := "010011"; constant ap_ST_st21_fsm_20 : STD_LOGIC_VECTOR (5 downto 0) := "010100"; constant ap_ST_st22_fsm_21 : STD_LOGIC_VECTOR (5 downto 0) := "010101"; constant ap_ST_st23_fsm_22 : STD_LOGIC_VECTOR (5 downto 0) := "010110"; constant ap_ST_st24_fsm_23 : STD_LOGIC_VECTOR (5 downto 0) := "010111"; constant ap_ST_st25_fsm_24 : STD_LOGIC_VECTOR (5 downto 0) := "011000"; constant ap_ST_st26_fsm_25 : STD_LOGIC_VECTOR (5 downto 0) := "011001"; constant ap_ST_st27_fsm_26 : STD_LOGIC_VECTOR (5 downto 0) := "011010"; constant ap_ST_st28_fsm_27 : STD_LOGIC_VECTOR (5 downto 0) := "011011"; constant ap_ST_st29_fsm_28 : STD_LOGIC_VECTOR (5 downto 0) := "011100"; constant ap_ST_st30_fsm_29 : STD_LOGIC_VECTOR (5 downto 0) := "011101"; constant ap_ST_st31_fsm_30 : STD_LOGIC_VECTOR (5 downto 0) := "011110"; constant ap_ST_st32_fsm_31 : STD_LOGIC_VECTOR (5 downto 0) := "011111"; constant ap_ST_st33_fsm_32 : STD_LOGIC_VECTOR (5 downto 0) := "100000"; constant ap_ST_st34_fsm_33 : STD_LOGIC_VECTOR (5 downto 0) := "100001"; constant ap_ST_st35_fsm_34 : STD_LOGIC_VECTOR (5 downto 0) := "100010"; constant ap_ST_st36_fsm_35 : STD_LOGIC_VECTOR (5 downto 0) := "100011"; constant ap_ST_st37_fsm_36 : STD_LOGIC_VECTOR (5 downto 0) := "100100"; constant ap_ST_st38_fsm_37 : STD_LOGIC_VECTOR (5 downto 0) := "100101"; constant ap_ST_st39_fsm_38 : STD_LOGIC_VECTOR (5 downto 0) := "100110"; constant ap_ST_st40_fsm_39 : STD_LOGIC_VECTOR (5 downto 0) := "100111"; constant ap_const_lv1_0 : STD_LOGIC_VECTOR (0 downto 0) := "0"; constant ap_const_lv32_1 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000001"; constant ap_const_lv32_0 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000000"; signal ap_CS_fsm : STD_LOGIC_VECTOR (5 downto 0) := "000000"; signal stop_on_first_read_read_fu_102_p2 : STD_LOGIC_VECTOR (0 downto 0); signal tmp_i_fu_228_p2 : STD_LOGIC_VECTOR (0 downto 0); signal tmp_i_reg_313 : STD_LOGIC_VECTOR (0 downto 0); signal tmp_i_10_fu_233_p2 : STD_LOGIC_VECTOR (0 downto 0); signal tmp_i_10_reg_318 : STD_LOGIC_VECTOR (0 downto 0); signal tmp_i_11_fu_238_p2 : STD_LOGIC_VECTOR (0 downto 0); signal tmp_i_11_reg_323 : STD_LOGIC_VECTOR (0 downto 0); signal c_load_reg_327 : STD_LOGIC_VECTOR (31 downto 0); signal grp_sample_iterator_get_offset_fu_192_ap_return : STD_LOGIC_VECTOR (31 downto 0); signal offset_reg_333 : STD_LOGIC_VECTOR (31 downto 0); signal grp_nfa_accept_sample_fu_176_ap_return : STD_LOGIC_VECTOR (0 downto 0); signal r_reg_338 : STD_LOGIC_VECTOR (0 downto 0); signal grp_nfa_accept_sample_fu_176_ap_done : STD_LOGIC; signal or_cond_fu_245_p2 : STD_LOGIC_VECTOR (0 downto 0); signal or_cond_reg_343 : STD_LOGIC_VECTOR (0 downto 0); signal grp_fu_249_p2 : STD_LOGIC_VECTOR (31 downto 0); signal c_1_reg_347 : STD_LOGIC_VECTOR (31 downto 0); signal grp_nfa_accept_sample_fu_176_ap_start : STD_LOGIC; signal grp_nfa_accept_sample_fu_176_ap_idle : STD_LOGIC; signal grp_nfa_accept_sample_fu_176_ap_ready : STD_LOGIC; signal grp_nfa_accept_sample_fu_176_nfa_initials_buckets_req_din : STD_LOGIC; signal grp_nfa_accept_sample_fu_176_nfa_initials_buckets_req_full_n : STD_LOGIC; signal grp_nfa_accept_sample_fu_176_nfa_initials_buckets_req_write : STD_LOGIC; signal grp_nfa_accept_sample_fu_176_nfa_initials_buckets_rsp_empty_n : STD_LOGIC; signal grp_nfa_accept_sample_fu_176_nfa_initials_buckets_rsp_read : STD_LOGIC; signal grp_nfa_accept_sample_fu_176_nfa_initials_buckets_address : STD_LOGIC_VECTOR (31 downto 0); signal grp_nfa_accept_sample_fu_176_nfa_initials_buckets_datain : STD_LOGIC_VECTOR (31 downto 0); signal grp_nfa_accept_sample_fu_176_nfa_initials_buckets_dataout : STD_LOGIC_VECTOR (31 downto 0); signal grp_nfa_accept_sample_fu_176_nfa_initials_buckets_size : STD_LOGIC_VECTOR (31 downto 0); signal grp_nfa_accept_sample_fu_176_nfa_finals_buckets_req_din : STD_LOGIC; signal grp_nfa_accept_sample_fu_176_nfa_finals_buckets_req_full_n : STD_LOGIC; signal grp_nfa_accept_sample_fu_176_nfa_finals_buckets_req_write : STD_LOGIC; signal grp_nfa_accept_sample_fu_176_nfa_finals_buckets_rsp_empty_n : STD_LOGIC; signal grp_nfa_accept_sample_fu_176_nfa_finals_buckets_rsp_read : STD_LOGIC; signal grp_nfa_accept_sample_fu_176_nfa_finals_buckets_address : STD_LOGIC_VECTOR (31 downto 0); signal grp_nfa_accept_sample_fu_176_nfa_finals_buckets_datain : STD_LOGIC_VECTOR (31 downto 0); signal grp_nfa_accept_sample_fu_176_nfa_finals_buckets_dataout : STD_LOGIC_VECTOR (31 downto 0); signal grp_nfa_accept_sample_fu_176_nfa_finals_buckets_size : STD_LOGIC_VECTOR (31 downto 0); signal grp_nfa_accept_sample_fu_176_nfa_forward_buckets_req_din : STD_LOGIC; signal grp_nfa_accept_sample_fu_176_nfa_forward_buckets_req_full_n : STD_LOGIC; signal grp_nfa_accept_sample_fu_176_nfa_forward_buckets_req_write : STD_LOGIC; signal grp_nfa_accept_sample_fu_176_nfa_forward_buckets_rsp_empty_n : STD_LOGIC; signal grp_nfa_accept_sample_fu_176_nfa_forward_buckets_rsp_read : STD_LOGIC; signal grp_nfa_accept_sample_fu_176_nfa_forward_buckets_address : STD_LOGIC_VECTOR (31 downto 0); signal grp_nfa_accept_sample_fu_176_nfa_forward_buckets_datain : STD_LOGIC_VECTOR (31 downto 0); signal grp_nfa_accept_sample_fu_176_nfa_forward_buckets_dataout : STD_LOGIC_VECTOR (31 downto 0); signal grp_nfa_accept_sample_fu_176_nfa_forward_buckets_size : STD_LOGIC_VECTOR (31 downto 0); signal grp_nfa_accept_sample_fu_176_nfa_symbols : STD_LOGIC_VECTOR (7 downto 0); signal grp_nfa_accept_sample_fu_176_sample_req_din : STD_LOGIC; signal grp_nfa_accept_sample_fu_176_sample_req_full_n : STD_LOGIC; signal grp_nfa_accept_sample_fu_176_sample_req_write : STD_LOGIC; signal grp_nfa_accept_sample_fu_176_sample_rsp_empty_n : STD_LOGIC; signal grp_nfa_accept_sample_fu_176_sample_rsp_read : STD_LOGIC; signal grp_nfa_accept_sample_fu_176_sample_address : STD_LOGIC_VECTOR (31 downto 0); signal grp_nfa_accept_sample_fu_176_sample_datain : STD_LOGIC_VECTOR (7 downto 0); signal grp_nfa_accept_sample_fu_176_sample_dataout : STD_LOGIC_VECTOR (7 downto 0); signal grp_nfa_accept_sample_fu_176_sample_size : STD_LOGIC_VECTOR (31 downto 0); signal grp_nfa_accept_sample_fu_176_empty : STD_LOGIC_VECTOR (31 downto 0); signal grp_nfa_accept_sample_fu_176_length_r : STD_LOGIC_VECTOR (15 downto 0); signal grp_sample_iterator_get_offset_fu_192_ap_start : STD_LOGIC; signal grp_sample_iterator_get_offset_fu_192_ap_done : STD_LOGIC; signal grp_sample_iterator_get_offset_fu_192_ap_idle : STD_LOGIC; signal grp_sample_iterator_get_offset_fu_192_ap_ready : STD_LOGIC; signal grp_sample_iterator_get_offset_fu_192_indices_stride_req_din : STD_LOGIC; signal grp_sample_iterator_get_offset_fu_192_indices_stride_req_full_n : STD_LOGIC; signal grp_sample_iterator_get_offset_fu_192_indices_stride_req_write : STD_LOGIC; signal grp_sample_iterator_get_offset_fu_192_indices_stride_rsp_empty_n : STD_LOGIC; signal grp_sample_iterator_get_offset_fu_192_indices_stride_rsp_read : STD_LOGIC; signal grp_sample_iterator_get_offset_fu_192_indices_stride_address : STD_LOGIC_VECTOR (31 downto 0); signal grp_sample_iterator_get_offset_fu_192_indices_stride_datain : STD_LOGIC_VECTOR (7 downto 0); signal grp_sample_iterator_get_offset_fu_192_indices_stride_dataout : STD_LOGIC_VECTOR (7 downto 0); signal grp_sample_iterator_get_offset_fu_192_indices_stride_size : STD_LOGIC_VECTOR (31 downto 0); signal grp_sample_iterator_get_offset_fu_192_indices_begin_req_din : STD_LOGIC; signal grp_sample_iterator_get_offset_fu_192_indices_begin_req_full_n : STD_LOGIC; signal grp_sample_iterator_get_offset_fu_192_indices_begin_req_write : STD_LOGIC; signal grp_sample_iterator_get_offset_fu_192_indices_begin_rsp_empty_n : STD_LOGIC; signal grp_sample_iterator_get_offset_fu_192_indices_begin_rsp_read : STD_LOGIC; signal grp_sample_iterator_get_offset_fu_192_indices_begin_address : STD_LOGIC_VECTOR (31 downto 0); signal grp_sample_iterator_get_offset_fu_192_indices_begin_datain : STD_LOGIC_VECTOR (31 downto 0); signal grp_sample_iterator_get_offset_fu_192_indices_begin_dataout : STD_LOGIC_VECTOR (31 downto 0); signal grp_sample_iterator_get_offset_fu_192_indices_begin_size : STD_LOGIC_VECTOR (31 downto 0); signal grp_sample_iterator_get_offset_fu_192_ap_ce : STD_LOGIC; signal grp_sample_iterator_get_offset_fu_192_i_index : STD_LOGIC_VECTOR (15 downto 0); signal grp_sample_iterator_get_offset_fu_192_i_sample : STD_LOGIC_VECTOR (15 downto 0); signal grp_sample_iterator_get_offset_fu_192_indices_samples_req_din : STD_LOGIC; signal grp_sample_iterator_get_offset_fu_192_indices_samples_req_full_n : STD_LOGIC; signal grp_sample_iterator_get_offset_fu_192_indices_samples_req_write : STD_LOGIC; signal grp_sample_iterator_get_offset_fu_192_indices_samples_rsp_empty_n : STD_LOGIC; signal grp_sample_iterator_get_offset_fu_192_indices_samples_rsp_read : STD_LOGIC; signal grp_sample_iterator_get_offset_fu_192_indices_samples_address : STD_LOGIC_VECTOR (31 downto 0); signal grp_sample_iterator_get_offset_fu_192_indices_samples_datain : STD_LOGIC_VECTOR (15 downto 0); signal grp_sample_iterator_get_offset_fu_192_indices_samples_dataout : STD_LOGIC_VECTOR (15 downto 0); signal grp_sample_iterator_get_offset_fu_192_indices_samples_size : STD_LOGIC_VECTOR (31 downto 0); signal grp_sample_iterator_get_offset_fu_192_sample_buffer_size : STD_LOGIC_VECTOR (31 downto 0); signal grp_sample_iterator_get_offset_fu_192_sample_length : STD_LOGIC_VECTOR (15 downto 0); signal grp_sample_iterator_next_fu_209_ap_start : STD_LOGIC; signal grp_sample_iterator_next_fu_209_ap_done : STD_LOGIC; signal grp_sample_iterator_next_fu_209_ap_idle : STD_LOGIC; signal grp_sample_iterator_next_fu_209_ap_ready : STD_LOGIC; signal grp_sample_iterator_next_fu_209_indices_samples_req_din : STD_LOGIC; signal grp_sample_iterator_next_fu_209_indices_samples_req_full_n : STD_LOGIC; signal grp_sample_iterator_next_fu_209_indices_samples_req_write : STD_LOGIC; signal grp_sample_iterator_next_fu_209_indices_samples_rsp_empty_n : STD_LOGIC; signal grp_sample_iterator_next_fu_209_indices_samples_rsp_read : STD_LOGIC; signal grp_sample_iterator_next_fu_209_indices_samples_address : STD_LOGIC_VECTOR (31 downto 0); signal grp_sample_iterator_next_fu_209_indices_samples_datain : STD_LOGIC_VECTOR (15 downto 0); signal grp_sample_iterator_next_fu_209_indices_samples_dataout : STD_LOGIC_VECTOR (15 downto 0); signal grp_sample_iterator_next_fu_209_indices_samples_size : STD_LOGIC_VECTOR (31 downto 0); signal grp_sample_iterator_next_fu_209_ap_ce : STD_LOGIC; signal grp_sample_iterator_next_fu_209_indices_begin_req_din : STD_LOGIC; signal grp_sample_iterator_next_fu_209_indices_begin_req_full_n : STD_LOGIC; signal grp_sample_iterator_next_fu_209_indices_begin_req_write : STD_LOGIC; signal grp_sample_iterator_next_fu_209_indices_begin_rsp_empty_n : STD_LOGIC; signal grp_sample_iterator_next_fu_209_indices_begin_rsp_read : STD_LOGIC; signal grp_sample_iterator_next_fu_209_indices_begin_address : STD_LOGIC_VECTOR (31 downto 0); signal grp_sample_iterator_next_fu_209_indices_begin_datain : STD_LOGIC_VECTOR (31 downto 0); signal grp_sample_iterator_next_fu_209_indices_begin_dataout : STD_LOGIC_VECTOR (31 downto 0); signal grp_sample_iterator_next_fu_209_indices_begin_size : STD_LOGIC_VECTOR (31 downto 0); signal grp_sample_iterator_next_fu_209_indices_stride_req_din : STD_LOGIC; signal grp_sample_iterator_next_fu_209_indices_stride_req_full_n : STD_LOGIC; signal grp_sample_iterator_next_fu_209_indices_stride_req_write : STD_LOGIC; signal grp_sample_iterator_next_fu_209_indices_stride_rsp_empty_n : STD_LOGIC; signal grp_sample_iterator_next_fu_209_indices_stride_rsp_read : STD_LOGIC; signal grp_sample_iterator_next_fu_209_indices_stride_address : STD_LOGIC_VECTOR (31 downto 0); signal grp_sample_iterator_next_fu_209_indices_stride_datain : STD_LOGIC_VECTOR (7 downto 0); signal grp_sample_iterator_next_fu_209_indices_stride_dataout : STD_LOGIC_VECTOR (7 downto 0); signal grp_sample_iterator_next_fu_209_indices_stride_size : STD_LOGIC_VECTOR (31 downto 0); signal grp_sample_iterator_next_fu_209_i_index : STD_LOGIC_VECTOR (15 downto 0); signal grp_sample_iterator_next_fu_209_i_sample : STD_LOGIC_VECTOR (15 downto 0); signal grp_sample_iterator_next_fu_209_ap_return_0 : STD_LOGIC_VECTOR (15 downto 0); signal grp_sample_iterator_next_fu_209_ap_return_1 : STD_LOGIC_VECTOR (15 downto 0); signal i_index_reg_144 : STD_LOGIC_VECTOR (15 downto 0); signal i_sample_reg_154 : STD_LOGIC_VECTOR (15 downto 0); signal p_0_reg_164 : STD_LOGIC_VECTOR (31 downto 0); signal grp_nfa_accept_sample_fu_176_ap_start_ap_start_reg : STD_LOGIC := '0'; signal grp_sample_iterator_get_offset_fu_192_ap_start_ap_start_reg : STD_LOGIC := '0'; signal ap_NS_fsm : STD_LOGIC_VECTOR (5 downto 0); signal grp_sample_iterator_next_fu_209_ap_start_ap_start_reg : STD_LOGIC := '0'; signal c_fu_92 : STD_LOGIC_VECTOR (31 downto 0); signal grp_fu_249_p0 : STD_LOGIC_VECTOR (31 downto 0); signal grp_fu_249_p1 : STD_LOGIC_VECTOR (31 downto 0); signal grp_fu_249_ce : STD_LOGIC; component nfa_accept_sample IS port ( ap_clk : IN STD_LOGIC; ap_rst : IN STD_LOGIC; ap_start : IN STD_LOGIC; ap_done : OUT STD_LOGIC; ap_idle : OUT STD_LOGIC; ap_ready : OUT STD_LOGIC; nfa_initials_buckets_req_din : OUT STD_LOGIC; nfa_initials_buckets_req_full_n : IN STD_LOGIC; nfa_initials_buckets_req_write : OUT STD_LOGIC; nfa_initials_buckets_rsp_empty_n : IN STD_LOGIC; nfa_initials_buckets_rsp_read : OUT STD_LOGIC; nfa_initials_buckets_address : OUT STD_LOGIC_VECTOR (31 downto 0); nfa_initials_buckets_datain : IN STD_LOGIC_VECTOR (31 downto 0); nfa_initials_buckets_dataout : OUT STD_LOGIC_VECTOR (31 downto 0); nfa_initials_buckets_size : OUT STD_LOGIC_VECTOR (31 downto 0); nfa_finals_buckets_req_din : OUT STD_LOGIC; nfa_finals_buckets_req_full_n : IN STD_LOGIC; nfa_finals_buckets_req_write : OUT STD_LOGIC; nfa_finals_buckets_rsp_empty_n : IN STD_LOGIC; nfa_finals_buckets_rsp_read : OUT STD_LOGIC; nfa_finals_buckets_address : OUT STD_LOGIC_VECTOR (31 downto 0); nfa_finals_buckets_datain : IN STD_LOGIC_VECTOR (31 downto 0); nfa_finals_buckets_dataout : OUT STD_LOGIC_VECTOR (31 downto 0); nfa_finals_buckets_size : OUT STD_LOGIC_VECTOR (31 downto 0); nfa_forward_buckets_req_din : OUT STD_LOGIC; nfa_forward_buckets_req_full_n : IN STD_LOGIC; nfa_forward_buckets_req_write : OUT STD_LOGIC; nfa_forward_buckets_rsp_empty_n : IN STD_LOGIC; nfa_forward_buckets_rsp_read : OUT STD_LOGIC; nfa_forward_buckets_address : OUT STD_LOGIC_VECTOR (31 downto 0); nfa_forward_buckets_datain : IN STD_LOGIC_VECTOR (31 downto 0); nfa_forward_buckets_dataout : OUT STD_LOGIC_VECTOR (31 downto 0); nfa_forward_buckets_size : OUT STD_LOGIC_VECTOR (31 downto 0); nfa_symbols : IN STD_LOGIC_VECTOR (7 downto 0); sample_req_din : OUT STD_LOGIC; sample_req_full_n : IN STD_LOGIC; sample_req_write : OUT STD_LOGIC; sample_rsp_empty_n : IN STD_LOGIC; sample_rsp_read : OUT STD_LOGIC; sample_address : OUT STD_LOGIC_VECTOR (31 downto 0); sample_datain : IN STD_LOGIC_VECTOR (7 downto 0); sample_dataout : OUT STD_LOGIC_VECTOR (7 downto 0); sample_size : OUT STD_LOGIC_VECTOR (31 downto 0); empty : IN STD_LOGIC_VECTOR (31 downto 0); length_r : IN STD_LOGIC_VECTOR (15 downto 0); ap_return : OUT STD_LOGIC_VECTOR (0 downto 0) ); end component; component sample_iterator_get_offset IS port ( ap_clk : IN STD_LOGIC; ap_rst : IN STD_LOGIC; ap_start : IN STD_LOGIC; ap_done : OUT STD_LOGIC; ap_idle : OUT STD_LOGIC; ap_ready : OUT STD_LOGIC; indices_stride_req_din : OUT STD_LOGIC; indices_stride_req_full_n : IN STD_LOGIC; indices_stride_req_write : OUT STD_LOGIC; indices_stride_rsp_empty_n : IN STD_LOGIC; indices_stride_rsp_read : OUT STD_LOGIC; indices_stride_address : OUT STD_LOGIC_VECTOR (31 downto 0); indices_stride_datain : IN STD_LOGIC_VECTOR (7 downto 0); indices_stride_dataout : OUT STD_LOGIC_VECTOR (7 downto 0); indices_stride_size : OUT STD_LOGIC_VECTOR (31 downto 0); indices_begin_req_din : OUT STD_LOGIC; indices_begin_req_full_n : IN STD_LOGIC; indices_begin_req_write : OUT STD_LOGIC; indices_begin_rsp_empty_n : IN STD_LOGIC; indices_begin_rsp_read : OUT STD_LOGIC; indices_begin_address : OUT STD_LOGIC_VECTOR (31 downto 0); indices_begin_datain : IN STD_LOGIC_VECTOR (31 downto 0); indices_begin_dataout : OUT STD_LOGIC_VECTOR (31 downto 0); indices_begin_size : OUT STD_LOGIC_VECTOR (31 downto 0); ap_ce : IN STD_LOGIC; i_index : IN STD_LOGIC_VECTOR (15 downto 0); i_sample : IN STD_LOGIC_VECTOR (15 downto 0); indices_samples_req_din : OUT STD_LOGIC; indices_samples_req_full_n : IN STD_LOGIC; indices_samples_req_write : OUT STD_LOGIC; indices_samples_rsp_empty_n : IN STD_LOGIC; indices_samples_rsp_read : OUT STD_LOGIC; indices_samples_address : OUT STD_LOGIC_VECTOR (31 downto 0); indices_samples_datain : IN STD_LOGIC_VECTOR (15 downto 0); indices_samples_dataout : OUT STD_LOGIC_VECTOR (15 downto 0); indices_samples_size : OUT STD_LOGIC_VECTOR (31 downto 0); sample_buffer_size : IN STD_LOGIC_VECTOR (31 downto 0); sample_length : IN STD_LOGIC_VECTOR (15 downto 0); ap_return : OUT STD_LOGIC_VECTOR (31 downto 0) ); end component; component sample_iterator_next IS port ( ap_clk : IN STD_LOGIC; ap_rst : IN STD_LOGIC; ap_start : IN STD_LOGIC; ap_done : OUT STD_LOGIC; ap_idle : OUT STD_LOGIC; ap_ready : OUT STD_LOGIC; indices_samples_req_din : OUT STD_LOGIC; indices_samples_req_full_n : IN STD_LOGIC; indices_samples_req_write : OUT STD_LOGIC; indices_samples_rsp_empty_n : IN STD_LOGIC; indices_samples_rsp_read : OUT STD_LOGIC; indices_samples_address : OUT STD_LOGIC_VECTOR (31 downto 0); indices_samples_datain : IN STD_LOGIC_VECTOR (15 downto 0); indices_samples_dataout : OUT STD_LOGIC_VECTOR (15 downto 0); indices_samples_size : OUT STD_LOGIC_VECTOR (31 downto 0); ap_ce : IN STD_LOGIC; indices_begin_req_din : OUT STD_LOGIC; indices_begin_req_full_n : IN STD_LOGIC; indices_begin_req_write : OUT STD_LOGIC; indices_begin_rsp_empty_n : IN STD_LOGIC; indices_begin_rsp_read : OUT STD_LOGIC; indices_begin_address : OUT STD_LOGIC_VECTOR (31 downto 0); indices_begin_datain : IN STD_LOGIC_VECTOR (31 downto 0); indices_begin_dataout : OUT STD_LOGIC_VECTOR (31 downto 0); indices_begin_size : OUT STD_LOGIC_VECTOR (31 downto 0); indices_stride_req_din : OUT STD_LOGIC; indices_stride_req_full_n : IN STD_LOGIC; indices_stride_req_write : OUT STD_LOGIC; indices_stride_rsp_empty_n : IN STD_LOGIC; indices_stride_rsp_read : OUT STD_LOGIC; indices_stride_address : OUT STD_LOGIC_VECTOR (31 downto 0); indices_stride_datain : IN STD_LOGIC_VECTOR (7 downto 0); indices_stride_dataout : OUT STD_LOGIC_VECTOR (7 downto 0); indices_stride_size : OUT STD_LOGIC_VECTOR (31 downto 0); i_index : IN STD_LOGIC_VECTOR (15 downto 0); i_sample : IN STD_LOGIC_VECTOR (15 downto 0); ap_return_0 : OUT STD_LOGIC_VECTOR (15 downto 0); ap_return_1 : OUT STD_LOGIC_VECTOR (15 downto 0) ); end component; component nfa_accept_samples_generic_hw_add_32ns_32ns_32_8 IS generic ( ID : INTEGER; NUM_STAGE : INTEGER; din0_WIDTH : INTEGER; din1_WIDTH : INTEGER; dout_WIDTH : INTEGER ); port ( clk : IN STD_LOGIC; reset : IN STD_LOGIC; din0 : IN STD_LOGIC_VECTOR (31 downto 0); din1 : IN STD_LOGIC_VECTOR (31 downto 0); ce : IN STD_LOGIC; dout : OUT STD_LOGIC_VECTOR (31 downto 0) ); end component; begin grp_nfa_accept_sample_fu_176 : component nfa_accept_sample port map ( ap_clk => ap_clk, ap_rst => ap_rst, ap_start => grp_nfa_accept_sample_fu_176_ap_start, ap_done => grp_nfa_accept_sample_fu_176_ap_done, ap_idle => grp_nfa_accept_sample_fu_176_ap_idle, ap_ready => grp_nfa_accept_sample_fu_176_ap_ready, nfa_initials_buckets_req_din => grp_nfa_accept_sample_fu_176_nfa_initials_buckets_req_din, nfa_initials_buckets_req_full_n => grp_nfa_accept_sample_fu_176_nfa_initials_buckets_req_full_n, nfa_initials_buckets_req_write => grp_nfa_accept_sample_fu_176_nfa_initials_buckets_req_write, nfa_initials_buckets_rsp_empty_n => grp_nfa_accept_sample_fu_176_nfa_initials_buckets_rsp_empty_n, nfa_initials_buckets_rsp_read => grp_nfa_accept_sample_fu_176_nfa_initials_buckets_rsp_read, nfa_initials_buckets_address => grp_nfa_accept_sample_fu_176_nfa_initials_buckets_address, nfa_initials_buckets_datain => grp_nfa_accept_sample_fu_176_nfa_initials_buckets_datain, nfa_initials_buckets_dataout => grp_nfa_accept_sample_fu_176_nfa_initials_buckets_dataout, nfa_initials_buckets_size => grp_nfa_accept_sample_fu_176_nfa_initials_buckets_size, nfa_finals_buckets_req_din => grp_nfa_accept_sample_fu_176_nfa_finals_buckets_req_din, nfa_finals_buckets_req_full_n => grp_nfa_accept_sample_fu_176_nfa_finals_buckets_req_full_n, nfa_finals_buckets_req_write => grp_nfa_accept_sample_fu_176_nfa_finals_buckets_req_write, nfa_finals_buckets_rsp_empty_n => grp_nfa_accept_sample_fu_176_nfa_finals_buckets_rsp_empty_n, nfa_finals_buckets_rsp_read => grp_nfa_accept_sample_fu_176_nfa_finals_buckets_rsp_read, nfa_finals_buckets_address => grp_nfa_accept_sample_fu_176_nfa_finals_buckets_address, nfa_finals_buckets_datain => grp_nfa_accept_sample_fu_176_nfa_finals_buckets_datain, nfa_finals_buckets_dataout => grp_nfa_accept_sample_fu_176_nfa_finals_buckets_dataout, nfa_finals_buckets_size => grp_nfa_accept_sample_fu_176_nfa_finals_buckets_size, nfa_forward_buckets_req_din => grp_nfa_accept_sample_fu_176_nfa_forward_buckets_req_din, nfa_forward_buckets_req_full_n => grp_nfa_accept_sample_fu_176_nfa_forward_buckets_req_full_n, nfa_forward_buckets_req_write => grp_nfa_accept_sample_fu_176_nfa_forward_buckets_req_write, nfa_forward_buckets_rsp_empty_n => grp_nfa_accept_sample_fu_176_nfa_forward_buckets_rsp_empty_n, nfa_forward_buckets_rsp_read => grp_nfa_accept_sample_fu_176_nfa_forward_buckets_rsp_read, nfa_forward_buckets_address => grp_nfa_accept_sample_fu_176_nfa_forward_buckets_address, nfa_forward_buckets_datain => grp_nfa_accept_sample_fu_176_nfa_forward_buckets_datain, nfa_forward_buckets_dataout => grp_nfa_accept_sample_fu_176_nfa_forward_buckets_dataout, nfa_forward_buckets_size => grp_nfa_accept_sample_fu_176_nfa_forward_buckets_size, nfa_symbols => grp_nfa_accept_sample_fu_176_nfa_symbols, sample_req_din => grp_nfa_accept_sample_fu_176_sample_req_din, sample_req_full_n => grp_nfa_accept_sample_fu_176_sample_req_full_n, sample_req_write => grp_nfa_accept_sample_fu_176_sample_req_write, sample_rsp_empty_n => grp_nfa_accept_sample_fu_176_sample_rsp_empty_n, sample_rsp_read => grp_nfa_accept_sample_fu_176_sample_rsp_read, sample_address => grp_nfa_accept_sample_fu_176_sample_address, sample_datain => grp_nfa_accept_sample_fu_176_sample_datain, sample_dataout => grp_nfa_accept_sample_fu_176_sample_dataout, sample_size => grp_nfa_accept_sample_fu_176_sample_size, empty => grp_nfa_accept_sample_fu_176_empty, length_r => grp_nfa_accept_sample_fu_176_length_r, ap_return => grp_nfa_accept_sample_fu_176_ap_return); grp_sample_iterator_get_offset_fu_192 : component sample_iterator_get_offset port map ( ap_clk => ap_clk, ap_rst => ap_rst, ap_start => grp_sample_iterator_get_offset_fu_192_ap_start, ap_done => grp_sample_iterator_get_offset_fu_192_ap_done, ap_idle => grp_sample_iterator_get_offset_fu_192_ap_idle, ap_ready => grp_sample_iterator_get_offset_fu_192_ap_ready, indices_stride_req_din => grp_sample_iterator_get_offset_fu_192_indices_stride_req_din, indices_stride_req_full_n => grp_sample_iterator_get_offset_fu_192_indices_stride_req_full_n, indices_stride_req_write => grp_sample_iterator_get_offset_fu_192_indices_stride_req_write, indices_stride_rsp_empty_n => grp_sample_iterator_get_offset_fu_192_indices_stride_rsp_empty_n, indices_stride_rsp_read => grp_sample_iterator_get_offset_fu_192_indices_stride_rsp_read, indices_stride_address => grp_sample_iterator_get_offset_fu_192_indices_stride_address, indices_stride_datain => grp_sample_iterator_get_offset_fu_192_indices_stride_datain, indices_stride_dataout => grp_sample_iterator_get_offset_fu_192_indices_stride_dataout, indices_stride_size => grp_sample_iterator_get_offset_fu_192_indices_stride_size, indices_begin_req_din => grp_sample_iterator_get_offset_fu_192_indices_begin_req_din, indices_begin_req_full_n => grp_sample_iterator_get_offset_fu_192_indices_begin_req_full_n, indices_begin_req_write => grp_sample_iterator_get_offset_fu_192_indices_begin_req_write, indices_begin_rsp_empty_n => grp_sample_iterator_get_offset_fu_192_indices_begin_rsp_empty_n, indices_begin_rsp_read => grp_sample_iterator_get_offset_fu_192_indices_begin_rsp_read, indices_begin_address => grp_sample_iterator_get_offset_fu_192_indices_begin_address, indices_begin_datain => grp_sample_iterator_get_offset_fu_192_indices_begin_datain, indices_begin_dataout => grp_sample_iterator_get_offset_fu_192_indices_begin_dataout, indices_begin_size => grp_sample_iterator_get_offset_fu_192_indices_begin_size, ap_ce => grp_sample_iterator_get_offset_fu_192_ap_ce, i_index => grp_sample_iterator_get_offset_fu_192_i_index, i_sample => grp_sample_iterator_get_offset_fu_192_i_sample, indices_samples_req_din => grp_sample_iterator_get_offset_fu_192_indices_samples_req_din, indices_samples_req_full_n => grp_sample_iterator_get_offset_fu_192_indices_samples_req_full_n, indices_samples_req_write => grp_sample_iterator_get_offset_fu_192_indices_samples_req_write, indices_samples_rsp_empty_n => grp_sample_iterator_get_offset_fu_192_indices_samples_rsp_empty_n, indices_samples_rsp_read => grp_sample_iterator_get_offset_fu_192_indices_samples_rsp_read, indices_samples_address => grp_sample_iterator_get_offset_fu_192_indices_samples_address, indices_samples_datain => grp_sample_iterator_get_offset_fu_192_indices_samples_datain, indices_samples_dataout => grp_sample_iterator_get_offset_fu_192_indices_samples_dataout, indices_samples_size => grp_sample_iterator_get_offset_fu_192_indices_samples_size, sample_buffer_size => grp_sample_iterator_get_offset_fu_192_sample_buffer_size, sample_length => grp_sample_iterator_get_offset_fu_192_sample_length, ap_return => grp_sample_iterator_get_offset_fu_192_ap_return); grp_sample_iterator_next_fu_209 : component sample_iterator_next port map ( ap_clk => ap_clk, ap_rst => ap_rst, ap_start => grp_sample_iterator_next_fu_209_ap_start, ap_done => grp_sample_iterator_next_fu_209_ap_done, ap_idle => grp_sample_iterator_next_fu_209_ap_idle, ap_ready => grp_sample_iterator_next_fu_209_ap_ready, indices_samples_req_din => grp_sample_iterator_next_fu_209_indices_samples_req_din, indices_samples_req_full_n => grp_sample_iterator_next_fu_209_indices_samples_req_full_n, indices_samples_req_write => grp_sample_iterator_next_fu_209_indices_samples_req_write, indices_samples_rsp_empty_n => grp_sample_iterator_next_fu_209_indices_samples_rsp_empty_n, indices_samples_rsp_read => grp_sample_iterator_next_fu_209_indices_samples_rsp_read, indices_samples_address => grp_sample_iterator_next_fu_209_indices_samples_address, indices_samples_datain => grp_sample_iterator_next_fu_209_indices_samples_datain, indices_samples_dataout => grp_sample_iterator_next_fu_209_indices_samples_dataout, indices_samples_size => grp_sample_iterator_next_fu_209_indices_samples_size, ap_ce => grp_sample_iterator_next_fu_209_ap_ce, indices_begin_req_din => grp_sample_iterator_next_fu_209_indices_begin_req_din, indices_begin_req_full_n => grp_sample_iterator_next_fu_209_indices_begin_req_full_n, indices_begin_req_write => grp_sample_iterator_next_fu_209_indices_begin_req_write, indices_begin_rsp_empty_n => grp_sample_iterator_next_fu_209_indices_begin_rsp_empty_n, indices_begin_rsp_read => grp_sample_iterator_next_fu_209_indices_begin_rsp_read, indices_begin_address => grp_sample_iterator_next_fu_209_indices_begin_address, indices_begin_datain => grp_sample_iterator_next_fu_209_indices_begin_datain, indices_begin_dataout => grp_sample_iterator_next_fu_209_indices_begin_dataout, indices_begin_size => grp_sample_iterator_next_fu_209_indices_begin_size, indices_stride_req_din => grp_sample_iterator_next_fu_209_indices_stride_req_din, indices_stride_req_full_n => grp_sample_iterator_next_fu_209_indices_stride_req_full_n, indices_stride_req_write => grp_sample_iterator_next_fu_209_indices_stride_req_write, indices_stride_rsp_empty_n => grp_sample_iterator_next_fu_209_indices_stride_rsp_empty_n, indices_stride_rsp_read => grp_sample_iterator_next_fu_209_indices_stride_rsp_read, indices_stride_address => grp_sample_iterator_next_fu_209_indices_stride_address, indices_stride_datain => grp_sample_iterator_next_fu_209_indices_stride_datain, indices_stride_dataout => grp_sample_iterator_next_fu_209_indices_stride_dataout, indices_stride_size => grp_sample_iterator_next_fu_209_indices_stride_size, i_index => grp_sample_iterator_next_fu_209_i_index, i_sample => grp_sample_iterator_next_fu_209_i_sample, ap_return_0 => grp_sample_iterator_next_fu_209_ap_return_0, ap_return_1 => grp_sample_iterator_next_fu_209_ap_return_1); nfa_accept_samples_generic_hw_add_32ns_32ns_32_8_U38 : component nfa_accept_samples_generic_hw_add_32ns_32ns_32_8 generic map ( ID => 38, NUM_STAGE => 8, din0_WIDTH => 32, din1_WIDTH => 32, dout_WIDTH => 32) port map ( clk => ap_clk, reset => ap_rst, din0 => grp_fu_249_p0, din1 => grp_fu_249_p1, ce => grp_fu_249_ce, dout => grp_fu_249_p2); -- the current state (ap_CS_fsm) of the state machine. -- ap_CS_fsm_assign_proc : process(ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (ap_rst = '1') then ap_CS_fsm <= ap_ST_st1_fsm_0; else ap_CS_fsm <= ap_NS_fsm; end if; end if; end process; -- grp_nfa_accept_sample_fu_176_ap_start_ap_start_reg assign process. -- grp_nfa_accept_sample_fu_176_ap_start_ap_start_reg_assign_proc : process(ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (ap_rst = '1') then grp_nfa_accept_sample_fu_176_ap_start_ap_start_reg <= ap_const_logic_0; else if ((ap_ST_st22_fsm_21 = ap_CS_fsm)) then grp_nfa_accept_sample_fu_176_ap_start_ap_start_reg <= ap_const_logic_1; elsif ((ap_const_logic_1 = grp_nfa_accept_sample_fu_176_ap_ready)) then grp_nfa_accept_sample_fu_176_ap_start_ap_start_reg <= ap_const_logic_0; end if; end if; end if; end process; -- grp_sample_iterator_get_offset_fu_192_ap_start_ap_start_reg assign process. -- grp_sample_iterator_get_offset_fu_192_ap_start_ap_start_reg_assign_proc : process(ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (ap_rst = '1') then grp_sample_iterator_get_offset_fu_192_ap_start_ap_start_reg <= ap_const_logic_0; else if (((ap_ST_st3_fsm_2 = ap_CS_fsm) and (ap_ST_st4_fsm_3 = ap_NS_fsm) and (tmp_i_11_fu_238_p2 = ap_const_lv1_0))) then grp_sample_iterator_get_offset_fu_192_ap_start_ap_start_reg <= ap_const_logic_1; elsif ((ap_const_logic_1 = grp_sample_iterator_get_offset_fu_192_ap_ready)) then grp_sample_iterator_get_offset_fu_192_ap_start_ap_start_reg <= ap_const_logic_0; end if; end if; end if; end process; -- grp_sample_iterator_next_fu_209_ap_start_ap_start_reg assign process. -- grp_sample_iterator_next_fu_209_ap_start_ap_start_reg_assign_proc : process(ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (ap_rst = '1') then grp_sample_iterator_next_fu_209_ap_start_ap_start_reg <= ap_const_logic_0; else if (((ap_ST_st32_fsm_31 = ap_NS_fsm) and ((ap_ST_st24_fsm_23 = ap_CS_fsm) or (ap_ST_st31_fsm_30 = ap_CS_fsm)))) then grp_sample_iterator_next_fu_209_ap_start_ap_start_reg <= ap_const_logic_1; elsif ((ap_const_logic_1 = grp_sample_iterator_next_fu_209_ap_ready)) then grp_sample_iterator_next_fu_209_ap_start_ap_start_reg <= ap_const_logic_0; end if; end if; end if; end process; -- c_fu_92 assign process. -- c_fu_92_assign_proc : process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((ap_ST_st32_fsm_31 = ap_CS_fsm) and (or_cond_reg_343 = ap_const_lv1_0))) then c_fu_92 <= c_1_reg_347; elsif (((ap_ST_st1_fsm_0 = ap_CS_fsm) and not((ap_start = ap_const_logic_0)))) then c_fu_92 <= ap_const_lv32_0; end if; end if; end process; -- i_index_reg_144 assign process. -- i_index_reg_144_assign_proc : process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if ((ap_ST_st39_fsm_38 = ap_CS_fsm)) then i_index_reg_144 <= grp_sample_iterator_next_fu_209_ap_return_0; elsif (((ap_ST_st1_fsm_0 = ap_CS_fsm) and not((ap_start = ap_const_logic_0)))) then i_index_reg_144 <= begin_index; end if; end if; end process; -- i_sample_reg_154 assign process. -- i_sample_reg_154_assign_proc : process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if ((ap_ST_st39_fsm_38 = ap_CS_fsm)) then i_sample_reg_154 <= grp_sample_iterator_next_fu_209_ap_return_1; elsif (((ap_ST_st1_fsm_0 = ap_CS_fsm) and not((ap_start = ap_const_logic_0)))) then i_sample_reg_154 <= begin_sample; end if; end if; end process; -- p_0_reg_164 assign process. -- p_0_reg_164_assign_proc : process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((ap_ST_st24_fsm_23 = ap_CS_fsm) and not((stop_on_first_read_read_fu_102_p2 = ap_const_lv1_0)) and (or_cond_fu_245_p2 = ap_const_lv1_0))) then p_0_reg_164 <= ap_const_lv32_1; elsif (((ap_ST_st4_fsm_3 = ap_CS_fsm) and not((tmp_i_11_reg_323 = ap_const_lv1_0)))) then p_0_reg_164 <= c_fu_92; end if; end if; end process; -- assign process. -- process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if ((ap_ST_st31_fsm_30 = ap_CS_fsm)) then c_1_reg_347 <= grp_fu_249_p2; end if; end if; end process; -- assign process. -- process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if ((ap_ST_st4_fsm_3 = ap_CS_fsm)) then c_load_reg_327 <= c_fu_92; end if; end if; end process; -- assign process. -- process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if ((ap_ST_st22_fsm_21 = ap_CS_fsm)) then offset_reg_333 <= grp_sample_iterator_get_offset_fu_192_ap_return; end if; end if; end process; -- assign process. -- process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if ((ap_ST_st24_fsm_23 = ap_CS_fsm)) then or_cond_reg_343 <= or_cond_fu_245_p2; end if; end if; end process; -- assign process. -- process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((ap_ST_st23_fsm_22 = ap_CS_fsm) and not((ap_const_logic_0 = grp_nfa_accept_sample_fu_176_ap_done)))) then r_reg_338 <= grp_nfa_accept_sample_fu_176_ap_return; end if; end if; end process; -- assign process. -- process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if ((ap_ST_st2_fsm_1 = ap_CS_fsm)) then tmp_i_10_reg_318 <= tmp_i_10_fu_233_p2; tmp_i_reg_313 <= tmp_i_fu_228_p2; end if; end if; end process; -- assign process. -- process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if ((ap_ST_st3_fsm_2 = ap_CS_fsm)) then tmp_i_11_reg_323 <= tmp_i_11_fu_238_p2; end if; end if; end process; -- the next state (ap_NS_fsm) of the state machine. -- ap_NS_fsm_assign_proc : process (ap_start , ap_CS_fsm , stop_on_first_read_read_fu_102_p2 , tmp_i_11_reg_323 , grp_nfa_accept_sample_fu_176_ap_done , or_cond_fu_245_p2) begin case ap_CS_fsm is when ap_ST_st1_fsm_0 => if (not((ap_start = ap_const_logic_0))) then ap_NS_fsm <= ap_ST_st2_fsm_1; else ap_NS_fsm <= ap_ST_st1_fsm_0; end if; when ap_ST_st2_fsm_1 => ap_NS_fsm <= ap_ST_st3_fsm_2; when ap_ST_st3_fsm_2 => ap_NS_fsm <= ap_ST_st4_fsm_3; when ap_ST_st4_fsm_3 => if (not((tmp_i_11_reg_323 = ap_const_lv1_0))) then ap_NS_fsm <= ap_ST_st40_fsm_39; else ap_NS_fsm <= ap_ST_st5_fsm_4; end if; when ap_ST_st5_fsm_4 => ap_NS_fsm <= ap_ST_st6_fsm_5; when ap_ST_st6_fsm_5 => ap_NS_fsm <= ap_ST_st7_fsm_6; when ap_ST_st7_fsm_6 => ap_NS_fsm <= ap_ST_st8_fsm_7; when ap_ST_st8_fsm_7 => ap_NS_fsm <= ap_ST_st9_fsm_8; when ap_ST_st9_fsm_8 => ap_NS_fsm <= ap_ST_st10_fsm_9; when ap_ST_st10_fsm_9 => ap_NS_fsm <= ap_ST_st11_fsm_10; when ap_ST_st11_fsm_10 => ap_NS_fsm <= ap_ST_st12_fsm_11; when ap_ST_st12_fsm_11 => ap_NS_fsm <= ap_ST_st13_fsm_12; when ap_ST_st13_fsm_12 => ap_NS_fsm <= ap_ST_st14_fsm_13; when ap_ST_st14_fsm_13 => ap_NS_fsm <= ap_ST_st15_fsm_14; when ap_ST_st15_fsm_14 => ap_NS_fsm <= ap_ST_st16_fsm_15; when ap_ST_st16_fsm_15 => ap_NS_fsm <= ap_ST_st17_fsm_16; when ap_ST_st17_fsm_16 => ap_NS_fsm <= ap_ST_st18_fsm_17; when ap_ST_st18_fsm_17 => ap_NS_fsm <= ap_ST_st19_fsm_18; when ap_ST_st19_fsm_18 => ap_NS_fsm <= ap_ST_st20_fsm_19; when ap_ST_st20_fsm_19 => ap_NS_fsm <= ap_ST_st21_fsm_20; when ap_ST_st21_fsm_20 => ap_NS_fsm <= ap_ST_st22_fsm_21; when ap_ST_st22_fsm_21 => ap_NS_fsm <= ap_ST_st23_fsm_22; when ap_ST_st23_fsm_22 => if (not((ap_const_logic_0 = grp_nfa_accept_sample_fu_176_ap_done))) then ap_NS_fsm <= ap_ST_st24_fsm_23; else ap_NS_fsm <= ap_ST_st23_fsm_22; end if; when ap_ST_st24_fsm_23 => if ((not((stop_on_first_read_read_fu_102_p2 = ap_const_lv1_0)) and (or_cond_fu_245_p2 = ap_const_lv1_0))) then ap_NS_fsm <= ap_ST_st40_fsm_39; elsif (((stop_on_first_read_read_fu_102_p2 = ap_const_lv1_0) and (or_cond_fu_245_p2 = ap_const_lv1_0))) then ap_NS_fsm <= ap_ST_st25_fsm_24; else ap_NS_fsm <= ap_ST_st32_fsm_31; end if; when ap_ST_st25_fsm_24 => ap_NS_fsm <= ap_ST_st26_fsm_25; when ap_ST_st26_fsm_25 => ap_NS_fsm <= ap_ST_st27_fsm_26; when ap_ST_st27_fsm_26 => ap_NS_fsm <= ap_ST_st28_fsm_27; when ap_ST_st28_fsm_27 => ap_NS_fsm <= ap_ST_st29_fsm_28; when ap_ST_st29_fsm_28 => ap_NS_fsm <= ap_ST_st30_fsm_29; when ap_ST_st30_fsm_29 => ap_NS_fsm <= ap_ST_st31_fsm_30; when ap_ST_st31_fsm_30 => ap_NS_fsm <= ap_ST_st32_fsm_31; when ap_ST_st32_fsm_31 => ap_NS_fsm <= ap_ST_st33_fsm_32; when ap_ST_st33_fsm_32 => ap_NS_fsm <= ap_ST_st34_fsm_33; when ap_ST_st34_fsm_33 => ap_NS_fsm <= ap_ST_st35_fsm_34; when ap_ST_st35_fsm_34 => ap_NS_fsm <= ap_ST_st36_fsm_35; when ap_ST_st36_fsm_35 => ap_NS_fsm <= ap_ST_st37_fsm_36; when ap_ST_st37_fsm_36 => ap_NS_fsm <= ap_ST_st38_fsm_37; when ap_ST_st38_fsm_37 => ap_NS_fsm <= ap_ST_st39_fsm_38; when ap_ST_st39_fsm_38 => ap_NS_fsm <= ap_ST_st2_fsm_1; when ap_ST_st40_fsm_39 => ap_NS_fsm <= ap_ST_st1_fsm_0; when others => ap_NS_fsm <= "XXXXXX"; end case; end process; -- ap_done assign process. -- ap_done_assign_proc : process(ap_CS_fsm) begin if ((ap_ST_st40_fsm_39 = ap_CS_fsm)) then ap_done <= ap_const_logic_1; else ap_done <= ap_const_logic_0; end if; end process; -- ap_idle assign process. -- ap_idle_assign_proc : process(ap_start, ap_CS_fsm) begin if ((not((ap_const_logic_1 = ap_start)) and (ap_ST_st1_fsm_0 = ap_CS_fsm))) then ap_idle <= ap_const_logic_1; else ap_idle <= ap_const_logic_0; end if; end process; -- ap_ready assign process. -- ap_ready_assign_proc : process(ap_CS_fsm) begin if ((ap_ST_st40_fsm_39 = ap_CS_fsm)) then ap_ready <= ap_const_logic_1; else ap_ready <= ap_const_logic_0; end if; end process; ap_return <= p_0_reg_164; grp_fu_249_ce <= ap_const_logic_1; grp_fu_249_p0 <= c_load_reg_327; grp_fu_249_p1 <= ap_const_lv32_1; grp_nfa_accept_sample_fu_176_ap_start <= grp_nfa_accept_sample_fu_176_ap_start_ap_start_reg; grp_nfa_accept_sample_fu_176_empty <= offset_reg_333; grp_nfa_accept_sample_fu_176_length_r <= sample_length; grp_nfa_accept_sample_fu_176_nfa_finals_buckets_datain <= nfa_finals_buckets_datain; grp_nfa_accept_sample_fu_176_nfa_finals_buckets_req_full_n <= nfa_finals_buckets_req_full_n; grp_nfa_accept_sample_fu_176_nfa_finals_buckets_rsp_empty_n <= nfa_finals_buckets_rsp_empty_n; grp_nfa_accept_sample_fu_176_nfa_forward_buckets_datain <= nfa_forward_buckets_datain; grp_nfa_accept_sample_fu_176_nfa_forward_buckets_req_full_n <= nfa_forward_buckets_req_full_n; grp_nfa_accept_sample_fu_176_nfa_forward_buckets_rsp_empty_n <= nfa_forward_buckets_rsp_empty_n; grp_nfa_accept_sample_fu_176_nfa_initials_buckets_datain <= nfa_initials_buckets_datain; grp_nfa_accept_sample_fu_176_nfa_initials_buckets_req_full_n <= nfa_initials_buckets_req_full_n; grp_nfa_accept_sample_fu_176_nfa_initials_buckets_rsp_empty_n <= nfa_initials_buckets_rsp_empty_n; grp_nfa_accept_sample_fu_176_nfa_symbols <= nfa_symbols; grp_nfa_accept_sample_fu_176_sample_datain <= sample_buffer_datain; grp_nfa_accept_sample_fu_176_sample_req_full_n <= sample_buffer_req_full_n; grp_nfa_accept_sample_fu_176_sample_rsp_empty_n <= sample_buffer_rsp_empty_n; grp_sample_iterator_get_offset_fu_192_ap_ce <= ap_const_logic_1; grp_sample_iterator_get_offset_fu_192_ap_start <= grp_sample_iterator_get_offset_fu_192_ap_start_ap_start_reg; grp_sample_iterator_get_offset_fu_192_i_index <= i_index_reg_144; grp_sample_iterator_get_offset_fu_192_i_sample <= i_sample_reg_154; grp_sample_iterator_get_offset_fu_192_indices_begin_datain <= indices_begin_datain; grp_sample_iterator_get_offset_fu_192_indices_begin_req_full_n <= indices_begin_req_full_n; grp_sample_iterator_get_offset_fu_192_indices_begin_rsp_empty_n <= indices_begin_rsp_empty_n; grp_sample_iterator_get_offset_fu_192_indices_samples_datain <= indices_samples_datain; grp_sample_iterator_get_offset_fu_192_indices_samples_req_full_n <= indices_samples_req_full_n; grp_sample_iterator_get_offset_fu_192_indices_samples_rsp_empty_n <= indices_samples_rsp_empty_n; grp_sample_iterator_get_offset_fu_192_indices_stride_datain <= indices_stride_datain; grp_sample_iterator_get_offset_fu_192_indices_stride_req_full_n <= indices_stride_req_full_n; grp_sample_iterator_get_offset_fu_192_indices_stride_rsp_empty_n <= indices_stride_rsp_empty_n; grp_sample_iterator_get_offset_fu_192_sample_buffer_size <= sample_buffer_length; grp_sample_iterator_get_offset_fu_192_sample_length <= sample_length; grp_sample_iterator_next_fu_209_ap_ce <= ap_const_logic_1; grp_sample_iterator_next_fu_209_ap_start <= grp_sample_iterator_next_fu_209_ap_start_ap_start_reg; grp_sample_iterator_next_fu_209_i_index <= i_index_reg_144; grp_sample_iterator_next_fu_209_i_sample <= i_sample_reg_154; grp_sample_iterator_next_fu_209_indices_begin_datain <= indices_begin_datain; grp_sample_iterator_next_fu_209_indices_begin_req_full_n <= indices_begin_req_full_n; grp_sample_iterator_next_fu_209_indices_begin_rsp_empty_n <= indices_begin_rsp_empty_n; grp_sample_iterator_next_fu_209_indices_samples_datain <= indices_samples_datain; grp_sample_iterator_next_fu_209_indices_samples_req_full_n <= indices_samples_req_full_n; grp_sample_iterator_next_fu_209_indices_samples_rsp_empty_n <= indices_samples_rsp_empty_n; grp_sample_iterator_next_fu_209_indices_stride_datain <= indices_stride_datain; grp_sample_iterator_next_fu_209_indices_stride_req_full_n <= indices_stride_req_full_n; grp_sample_iterator_next_fu_209_indices_stride_rsp_empty_n <= indices_stride_rsp_empty_n; -- indices_begin_address assign process. -- indices_begin_address_assign_proc : process(ap_CS_fsm, tmp_i_11_reg_323, grp_sample_iterator_get_offset_fu_192_indices_begin_address, grp_sample_iterator_next_fu_209_indices_begin_address) begin if (((ap_ST_st39_fsm_38 = ap_CS_fsm) or (ap_ST_st32_fsm_31 = ap_CS_fsm) or (ap_ST_st33_fsm_32 = ap_CS_fsm) or (ap_ST_st34_fsm_33 = ap_CS_fsm) or (ap_ST_st35_fsm_34 = ap_CS_fsm) or (ap_ST_st36_fsm_35 = ap_CS_fsm) or (ap_ST_st37_fsm_36 = ap_CS_fsm) or (ap_ST_st38_fsm_37 = ap_CS_fsm))) then indices_begin_address <= grp_sample_iterator_next_fu_209_indices_begin_address; elsif (((ap_ST_st22_fsm_21 = ap_CS_fsm) or ((ap_ST_st4_fsm_3 = ap_CS_fsm) and (tmp_i_11_reg_323 = ap_const_lv1_0)) or (ap_ST_st5_fsm_4 = ap_CS_fsm) or (ap_ST_st6_fsm_5 = ap_CS_fsm) or (ap_ST_st7_fsm_6 = ap_CS_fsm) or (ap_ST_st8_fsm_7 = ap_CS_fsm) or (ap_ST_st9_fsm_8 = ap_CS_fsm) or (ap_ST_st10_fsm_9 = ap_CS_fsm) or (ap_ST_st11_fsm_10 = ap_CS_fsm) or (ap_ST_st12_fsm_11 = ap_CS_fsm) or (ap_ST_st13_fsm_12 = ap_CS_fsm) or (ap_ST_st14_fsm_13 = ap_CS_fsm) or (ap_ST_st15_fsm_14 = ap_CS_fsm) or (ap_ST_st16_fsm_15 = ap_CS_fsm) or (ap_ST_st17_fsm_16 = ap_CS_fsm) or (ap_ST_st18_fsm_17 = ap_CS_fsm) or (ap_ST_st19_fsm_18 = ap_CS_fsm) or (ap_ST_st20_fsm_19 = ap_CS_fsm) or (ap_ST_st21_fsm_20 = ap_CS_fsm))) then indices_begin_address <= grp_sample_iterator_get_offset_fu_192_indices_begin_address; else indices_begin_address <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX"; end if; end process; -- indices_begin_dataout assign process. -- indices_begin_dataout_assign_proc : process(ap_CS_fsm, tmp_i_11_reg_323, grp_sample_iterator_get_offset_fu_192_indices_begin_dataout, grp_sample_iterator_next_fu_209_indices_begin_dataout) begin if (((ap_ST_st39_fsm_38 = ap_CS_fsm) or (ap_ST_st32_fsm_31 = ap_CS_fsm) or (ap_ST_st33_fsm_32 = ap_CS_fsm) or (ap_ST_st34_fsm_33 = ap_CS_fsm) or (ap_ST_st35_fsm_34 = ap_CS_fsm) or (ap_ST_st36_fsm_35 = ap_CS_fsm) or (ap_ST_st37_fsm_36 = ap_CS_fsm) or (ap_ST_st38_fsm_37 = ap_CS_fsm))) then indices_begin_dataout <= grp_sample_iterator_next_fu_209_indices_begin_dataout; elsif (((ap_ST_st22_fsm_21 = ap_CS_fsm) or ((ap_ST_st4_fsm_3 = ap_CS_fsm) and (tmp_i_11_reg_323 = ap_const_lv1_0)) or (ap_ST_st5_fsm_4 = ap_CS_fsm) or (ap_ST_st6_fsm_5 = ap_CS_fsm) or (ap_ST_st7_fsm_6 = ap_CS_fsm) or (ap_ST_st8_fsm_7 = ap_CS_fsm) or (ap_ST_st9_fsm_8 = ap_CS_fsm) or (ap_ST_st10_fsm_9 = ap_CS_fsm) or (ap_ST_st11_fsm_10 = ap_CS_fsm) or (ap_ST_st12_fsm_11 = ap_CS_fsm) or (ap_ST_st13_fsm_12 = ap_CS_fsm) or (ap_ST_st14_fsm_13 = ap_CS_fsm) or (ap_ST_st15_fsm_14 = ap_CS_fsm) or (ap_ST_st16_fsm_15 = ap_CS_fsm) or (ap_ST_st17_fsm_16 = ap_CS_fsm) or (ap_ST_st18_fsm_17 = ap_CS_fsm) or (ap_ST_st19_fsm_18 = ap_CS_fsm) or (ap_ST_st20_fsm_19 = ap_CS_fsm) or (ap_ST_st21_fsm_20 = ap_CS_fsm))) then indices_begin_dataout <= grp_sample_iterator_get_offset_fu_192_indices_begin_dataout; else indices_begin_dataout <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX"; end if; end process; -- indices_begin_req_din assign process. -- indices_begin_req_din_assign_proc : process(ap_CS_fsm, tmp_i_11_reg_323, grp_sample_iterator_get_offset_fu_192_indices_begin_req_din, grp_sample_iterator_next_fu_209_indices_begin_req_din) begin if (((ap_ST_st39_fsm_38 = ap_CS_fsm) or (ap_ST_st32_fsm_31 = ap_CS_fsm) or (ap_ST_st33_fsm_32 = ap_CS_fsm) or (ap_ST_st34_fsm_33 = ap_CS_fsm) or (ap_ST_st35_fsm_34 = ap_CS_fsm) or (ap_ST_st36_fsm_35 = ap_CS_fsm) or (ap_ST_st37_fsm_36 = ap_CS_fsm) or (ap_ST_st38_fsm_37 = ap_CS_fsm))) then indices_begin_req_din <= grp_sample_iterator_next_fu_209_indices_begin_req_din; elsif (((ap_ST_st22_fsm_21 = ap_CS_fsm) or ((ap_ST_st4_fsm_3 = ap_CS_fsm) and (tmp_i_11_reg_323 = ap_const_lv1_0)) or (ap_ST_st5_fsm_4 = ap_CS_fsm) or (ap_ST_st6_fsm_5 = ap_CS_fsm) or (ap_ST_st7_fsm_6 = ap_CS_fsm) or (ap_ST_st8_fsm_7 = ap_CS_fsm) or (ap_ST_st9_fsm_8 = ap_CS_fsm) or (ap_ST_st10_fsm_9 = ap_CS_fsm) or (ap_ST_st11_fsm_10 = ap_CS_fsm) or (ap_ST_st12_fsm_11 = ap_CS_fsm) or (ap_ST_st13_fsm_12 = ap_CS_fsm) or (ap_ST_st14_fsm_13 = ap_CS_fsm) or (ap_ST_st15_fsm_14 = ap_CS_fsm) or (ap_ST_st16_fsm_15 = ap_CS_fsm) or (ap_ST_st17_fsm_16 = ap_CS_fsm) or (ap_ST_st18_fsm_17 = ap_CS_fsm) or (ap_ST_st19_fsm_18 = ap_CS_fsm) or (ap_ST_st20_fsm_19 = ap_CS_fsm) or (ap_ST_st21_fsm_20 = ap_CS_fsm))) then indices_begin_req_din <= grp_sample_iterator_get_offset_fu_192_indices_begin_req_din; else indices_begin_req_din <= 'X'; end if; end process; -- indices_begin_req_write assign process. -- indices_begin_req_write_assign_proc : process(ap_CS_fsm, tmp_i_11_reg_323, grp_sample_iterator_get_offset_fu_192_indices_begin_req_write, grp_sample_iterator_next_fu_209_indices_begin_req_write) begin if (((ap_ST_st39_fsm_38 = ap_CS_fsm) or (ap_ST_st32_fsm_31 = ap_CS_fsm) or (ap_ST_st33_fsm_32 = ap_CS_fsm) or (ap_ST_st34_fsm_33 = ap_CS_fsm) or (ap_ST_st35_fsm_34 = ap_CS_fsm) or (ap_ST_st36_fsm_35 = ap_CS_fsm) or (ap_ST_st37_fsm_36 = ap_CS_fsm) or (ap_ST_st38_fsm_37 = ap_CS_fsm))) then indices_begin_req_write <= grp_sample_iterator_next_fu_209_indices_begin_req_write; elsif (((ap_ST_st22_fsm_21 = ap_CS_fsm) or ((ap_ST_st4_fsm_3 = ap_CS_fsm) and (tmp_i_11_reg_323 = ap_const_lv1_0)) or (ap_ST_st5_fsm_4 = ap_CS_fsm) or (ap_ST_st6_fsm_5 = ap_CS_fsm) or (ap_ST_st7_fsm_6 = ap_CS_fsm) or (ap_ST_st8_fsm_7 = ap_CS_fsm) or (ap_ST_st9_fsm_8 = ap_CS_fsm) or (ap_ST_st10_fsm_9 = ap_CS_fsm) or (ap_ST_st11_fsm_10 = ap_CS_fsm) or (ap_ST_st12_fsm_11 = ap_CS_fsm) or (ap_ST_st13_fsm_12 = ap_CS_fsm) or (ap_ST_st14_fsm_13 = ap_CS_fsm) or (ap_ST_st15_fsm_14 = ap_CS_fsm) or (ap_ST_st16_fsm_15 = ap_CS_fsm) or (ap_ST_st17_fsm_16 = ap_CS_fsm) or (ap_ST_st18_fsm_17 = ap_CS_fsm) or (ap_ST_st19_fsm_18 = ap_CS_fsm) or (ap_ST_st20_fsm_19 = ap_CS_fsm) or (ap_ST_st21_fsm_20 = ap_CS_fsm))) then indices_begin_req_write <= grp_sample_iterator_get_offset_fu_192_indices_begin_req_write; else indices_begin_req_write <= 'X'; end if; end process; -- indices_begin_rsp_read assign process. -- indices_begin_rsp_read_assign_proc : process(ap_CS_fsm, tmp_i_11_reg_323, grp_sample_iterator_get_offset_fu_192_indices_begin_rsp_read, grp_sample_iterator_next_fu_209_indices_begin_rsp_read) begin if (((ap_ST_st39_fsm_38 = ap_CS_fsm) or (ap_ST_st32_fsm_31 = ap_CS_fsm) or (ap_ST_st33_fsm_32 = ap_CS_fsm) or (ap_ST_st34_fsm_33 = ap_CS_fsm) or (ap_ST_st35_fsm_34 = ap_CS_fsm) or (ap_ST_st36_fsm_35 = ap_CS_fsm) or (ap_ST_st37_fsm_36 = ap_CS_fsm) or (ap_ST_st38_fsm_37 = ap_CS_fsm))) then indices_begin_rsp_read <= grp_sample_iterator_next_fu_209_indices_begin_rsp_read; elsif (((ap_ST_st22_fsm_21 = ap_CS_fsm) or ((ap_ST_st4_fsm_3 = ap_CS_fsm) and (tmp_i_11_reg_323 = ap_const_lv1_0)) or (ap_ST_st5_fsm_4 = ap_CS_fsm) or (ap_ST_st6_fsm_5 = ap_CS_fsm) or (ap_ST_st7_fsm_6 = ap_CS_fsm) or (ap_ST_st8_fsm_7 = ap_CS_fsm) or (ap_ST_st9_fsm_8 = ap_CS_fsm) or (ap_ST_st10_fsm_9 = ap_CS_fsm) or (ap_ST_st11_fsm_10 = ap_CS_fsm) or (ap_ST_st12_fsm_11 = ap_CS_fsm) or (ap_ST_st13_fsm_12 = ap_CS_fsm) or (ap_ST_st14_fsm_13 = ap_CS_fsm) or (ap_ST_st15_fsm_14 = ap_CS_fsm) or (ap_ST_st16_fsm_15 = ap_CS_fsm) or (ap_ST_st17_fsm_16 = ap_CS_fsm) or (ap_ST_st18_fsm_17 = ap_CS_fsm) or (ap_ST_st19_fsm_18 = ap_CS_fsm) or (ap_ST_st20_fsm_19 = ap_CS_fsm) or (ap_ST_st21_fsm_20 = ap_CS_fsm))) then indices_begin_rsp_read <= grp_sample_iterator_get_offset_fu_192_indices_begin_rsp_read; else indices_begin_rsp_read <= 'X'; end if; end process; -- indices_begin_size assign process. -- indices_begin_size_assign_proc : process(ap_CS_fsm, tmp_i_11_reg_323, grp_sample_iterator_get_offset_fu_192_indices_begin_size, grp_sample_iterator_next_fu_209_indices_begin_size) begin if (((ap_ST_st39_fsm_38 = ap_CS_fsm) or (ap_ST_st32_fsm_31 = ap_CS_fsm) or (ap_ST_st33_fsm_32 = ap_CS_fsm) or (ap_ST_st34_fsm_33 = ap_CS_fsm) or (ap_ST_st35_fsm_34 = ap_CS_fsm) or (ap_ST_st36_fsm_35 = ap_CS_fsm) or (ap_ST_st37_fsm_36 = ap_CS_fsm) or (ap_ST_st38_fsm_37 = ap_CS_fsm))) then indices_begin_size <= grp_sample_iterator_next_fu_209_indices_begin_size; elsif (((ap_ST_st22_fsm_21 = ap_CS_fsm) or ((ap_ST_st4_fsm_3 = ap_CS_fsm) and (tmp_i_11_reg_323 = ap_const_lv1_0)) or (ap_ST_st5_fsm_4 = ap_CS_fsm) or (ap_ST_st6_fsm_5 = ap_CS_fsm) or (ap_ST_st7_fsm_6 = ap_CS_fsm) or (ap_ST_st8_fsm_7 = ap_CS_fsm) or (ap_ST_st9_fsm_8 = ap_CS_fsm) or (ap_ST_st10_fsm_9 = ap_CS_fsm) or (ap_ST_st11_fsm_10 = ap_CS_fsm) or (ap_ST_st12_fsm_11 = ap_CS_fsm) or (ap_ST_st13_fsm_12 = ap_CS_fsm) or (ap_ST_st14_fsm_13 = ap_CS_fsm) or (ap_ST_st15_fsm_14 = ap_CS_fsm) or (ap_ST_st16_fsm_15 = ap_CS_fsm) or (ap_ST_st17_fsm_16 = ap_CS_fsm) or (ap_ST_st18_fsm_17 = ap_CS_fsm) or (ap_ST_st19_fsm_18 = ap_CS_fsm) or (ap_ST_st20_fsm_19 = ap_CS_fsm) or (ap_ST_st21_fsm_20 = ap_CS_fsm))) then indices_begin_size <= grp_sample_iterator_get_offset_fu_192_indices_begin_size; else indices_begin_size <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX"; end if; end process; -- indices_samples_address assign process. -- indices_samples_address_assign_proc : process(ap_CS_fsm, tmp_i_11_reg_323, grp_sample_iterator_get_offset_fu_192_indices_samples_address, grp_sample_iterator_next_fu_209_indices_samples_address) begin if (((ap_ST_st39_fsm_38 = ap_CS_fsm) or (ap_ST_st32_fsm_31 = ap_CS_fsm) or (ap_ST_st33_fsm_32 = ap_CS_fsm) or (ap_ST_st34_fsm_33 = ap_CS_fsm) or (ap_ST_st35_fsm_34 = ap_CS_fsm) or (ap_ST_st36_fsm_35 = ap_CS_fsm) or (ap_ST_st37_fsm_36 = ap_CS_fsm) or (ap_ST_st38_fsm_37 = ap_CS_fsm))) then indices_samples_address <= grp_sample_iterator_next_fu_209_indices_samples_address; elsif (((ap_ST_st22_fsm_21 = ap_CS_fsm) or ((ap_ST_st4_fsm_3 = ap_CS_fsm) and (tmp_i_11_reg_323 = ap_const_lv1_0)) or (ap_ST_st5_fsm_4 = ap_CS_fsm) or (ap_ST_st6_fsm_5 = ap_CS_fsm) or (ap_ST_st7_fsm_6 = ap_CS_fsm) or (ap_ST_st8_fsm_7 = ap_CS_fsm) or (ap_ST_st9_fsm_8 = ap_CS_fsm) or (ap_ST_st10_fsm_9 = ap_CS_fsm) or (ap_ST_st11_fsm_10 = ap_CS_fsm) or (ap_ST_st12_fsm_11 = ap_CS_fsm) or (ap_ST_st13_fsm_12 = ap_CS_fsm) or (ap_ST_st14_fsm_13 = ap_CS_fsm) or (ap_ST_st15_fsm_14 = ap_CS_fsm) or (ap_ST_st16_fsm_15 = ap_CS_fsm) or (ap_ST_st17_fsm_16 = ap_CS_fsm) or (ap_ST_st18_fsm_17 = ap_CS_fsm) or (ap_ST_st19_fsm_18 = ap_CS_fsm) or (ap_ST_st20_fsm_19 = ap_CS_fsm) or (ap_ST_st21_fsm_20 = ap_CS_fsm))) then indices_samples_address <= grp_sample_iterator_get_offset_fu_192_indices_samples_address; else indices_samples_address <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX"; end if; end process; -- indices_samples_dataout assign process. -- indices_samples_dataout_assign_proc : process(ap_CS_fsm, tmp_i_11_reg_323, grp_sample_iterator_get_offset_fu_192_indices_samples_dataout, grp_sample_iterator_next_fu_209_indices_samples_dataout) begin if (((ap_ST_st39_fsm_38 = ap_CS_fsm) or (ap_ST_st32_fsm_31 = ap_CS_fsm) or (ap_ST_st33_fsm_32 = ap_CS_fsm) or (ap_ST_st34_fsm_33 = ap_CS_fsm) or (ap_ST_st35_fsm_34 = ap_CS_fsm) or (ap_ST_st36_fsm_35 = ap_CS_fsm) or (ap_ST_st37_fsm_36 = ap_CS_fsm) or (ap_ST_st38_fsm_37 = ap_CS_fsm))) then indices_samples_dataout <= grp_sample_iterator_next_fu_209_indices_samples_dataout; elsif (((ap_ST_st22_fsm_21 = ap_CS_fsm) or ((ap_ST_st4_fsm_3 = ap_CS_fsm) and (tmp_i_11_reg_323 = ap_const_lv1_0)) or (ap_ST_st5_fsm_4 = ap_CS_fsm) or (ap_ST_st6_fsm_5 = ap_CS_fsm) or (ap_ST_st7_fsm_6 = ap_CS_fsm) or (ap_ST_st8_fsm_7 = ap_CS_fsm) or (ap_ST_st9_fsm_8 = ap_CS_fsm) or (ap_ST_st10_fsm_9 = ap_CS_fsm) or (ap_ST_st11_fsm_10 = ap_CS_fsm) or (ap_ST_st12_fsm_11 = ap_CS_fsm) or (ap_ST_st13_fsm_12 = ap_CS_fsm) or (ap_ST_st14_fsm_13 = ap_CS_fsm) or (ap_ST_st15_fsm_14 = ap_CS_fsm) or (ap_ST_st16_fsm_15 = ap_CS_fsm) or (ap_ST_st17_fsm_16 = ap_CS_fsm) or (ap_ST_st18_fsm_17 = ap_CS_fsm) or (ap_ST_st19_fsm_18 = ap_CS_fsm) or (ap_ST_st20_fsm_19 = ap_CS_fsm) or (ap_ST_st21_fsm_20 = ap_CS_fsm))) then indices_samples_dataout <= grp_sample_iterator_get_offset_fu_192_indices_samples_dataout; else indices_samples_dataout <= "XXXXXXXXXXXXXXXX"; end if; end process; -- indices_samples_req_din assign process. -- indices_samples_req_din_assign_proc : process(ap_CS_fsm, tmp_i_11_reg_323, grp_sample_iterator_get_offset_fu_192_indices_samples_req_din, grp_sample_iterator_next_fu_209_indices_samples_req_din) begin if (((ap_ST_st39_fsm_38 = ap_CS_fsm) or (ap_ST_st32_fsm_31 = ap_CS_fsm) or (ap_ST_st33_fsm_32 = ap_CS_fsm) or (ap_ST_st34_fsm_33 = ap_CS_fsm) or (ap_ST_st35_fsm_34 = ap_CS_fsm) or (ap_ST_st36_fsm_35 = ap_CS_fsm) or (ap_ST_st37_fsm_36 = ap_CS_fsm) or (ap_ST_st38_fsm_37 = ap_CS_fsm))) then indices_samples_req_din <= grp_sample_iterator_next_fu_209_indices_samples_req_din; elsif (((ap_ST_st22_fsm_21 = ap_CS_fsm) or ((ap_ST_st4_fsm_3 = ap_CS_fsm) and (tmp_i_11_reg_323 = ap_const_lv1_0)) or (ap_ST_st5_fsm_4 = ap_CS_fsm) or (ap_ST_st6_fsm_5 = ap_CS_fsm) or (ap_ST_st7_fsm_6 = ap_CS_fsm) or (ap_ST_st8_fsm_7 = ap_CS_fsm) or (ap_ST_st9_fsm_8 = ap_CS_fsm) or (ap_ST_st10_fsm_9 = ap_CS_fsm) or (ap_ST_st11_fsm_10 = ap_CS_fsm) or (ap_ST_st12_fsm_11 = ap_CS_fsm) or (ap_ST_st13_fsm_12 = ap_CS_fsm) or (ap_ST_st14_fsm_13 = ap_CS_fsm) or (ap_ST_st15_fsm_14 = ap_CS_fsm) or (ap_ST_st16_fsm_15 = ap_CS_fsm) or (ap_ST_st17_fsm_16 = ap_CS_fsm) or (ap_ST_st18_fsm_17 = ap_CS_fsm) or (ap_ST_st19_fsm_18 = ap_CS_fsm) or (ap_ST_st20_fsm_19 = ap_CS_fsm) or (ap_ST_st21_fsm_20 = ap_CS_fsm))) then indices_samples_req_din <= grp_sample_iterator_get_offset_fu_192_indices_samples_req_din; else indices_samples_req_din <= 'X'; end if; end process; -- indices_samples_req_write assign process. -- indices_samples_req_write_assign_proc : process(ap_CS_fsm, tmp_i_11_reg_323, grp_sample_iterator_get_offset_fu_192_indices_samples_req_write, grp_sample_iterator_next_fu_209_indices_samples_req_write) begin if (((ap_ST_st39_fsm_38 = ap_CS_fsm) or (ap_ST_st32_fsm_31 = ap_CS_fsm) or (ap_ST_st33_fsm_32 = ap_CS_fsm) or (ap_ST_st34_fsm_33 = ap_CS_fsm) or (ap_ST_st35_fsm_34 = ap_CS_fsm) or (ap_ST_st36_fsm_35 = ap_CS_fsm) or (ap_ST_st37_fsm_36 = ap_CS_fsm) or (ap_ST_st38_fsm_37 = ap_CS_fsm))) then indices_samples_req_write <= grp_sample_iterator_next_fu_209_indices_samples_req_write; elsif (((ap_ST_st22_fsm_21 = ap_CS_fsm) or ((ap_ST_st4_fsm_3 = ap_CS_fsm) and (tmp_i_11_reg_323 = ap_const_lv1_0)) or (ap_ST_st5_fsm_4 = ap_CS_fsm) or (ap_ST_st6_fsm_5 = ap_CS_fsm) or (ap_ST_st7_fsm_6 = ap_CS_fsm) or (ap_ST_st8_fsm_7 = ap_CS_fsm) or (ap_ST_st9_fsm_8 = ap_CS_fsm) or (ap_ST_st10_fsm_9 = ap_CS_fsm) or (ap_ST_st11_fsm_10 = ap_CS_fsm) or (ap_ST_st12_fsm_11 = ap_CS_fsm) or (ap_ST_st13_fsm_12 = ap_CS_fsm) or (ap_ST_st14_fsm_13 = ap_CS_fsm) or (ap_ST_st15_fsm_14 = ap_CS_fsm) or (ap_ST_st16_fsm_15 = ap_CS_fsm) or (ap_ST_st17_fsm_16 = ap_CS_fsm) or (ap_ST_st18_fsm_17 = ap_CS_fsm) or (ap_ST_st19_fsm_18 = ap_CS_fsm) or (ap_ST_st20_fsm_19 = ap_CS_fsm) or (ap_ST_st21_fsm_20 = ap_CS_fsm))) then indices_samples_req_write <= grp_sample_iterator_get_offset_fu_192_indices_samples_req_write; else indices_samples_req_write <= 'X'; end if; end process; -- indices_samples_rsp_read assign process. -- indices_samples_rsp_read_assign_proc : process(ap_CS_fsm, tmp_i_11_reg_323, grp_sample_iterator_get_offset_fu_192_indices_samples_rsp_read, grp_sample_iterator_next_fu_209_indices_samples_rsp_read) begin if (((ap_ST_st39_fsm_38 = ap_CS_fsm) or (ap_ST_st32_fsm_31 = ap_CS_fsm) or (ap_ST_st33_fsm_32 = ap_CS_fsm) or (ap_ST_st34_fsm_33 = ap_CS_fsm) or (ap_ST_st35_fsm_34 = ap_CS_fsm) or (ap_ST_st36_fsm_35 = ap_CS_fsm) or (ap_ST_st37_fsm_36 = ap_CS_fsm) or (ap_ST_st38_fsm_37 = ap_CS_fsm))) then indices_samples_rsp_read <= grp_sample_iterator_next_fu_209_indices_samples_rsp_read; elsif (((ap_ST_st22_fsm_21 = ap_CS_fsm) or ((ap_ST_st4_fsm_3 = ap_CS_fsm) and (tmp_i_11_reg_323 = ap_const_lv1_0)) or (ap_ST_st5_fsm_4 = ap_CS_fsm) or (ap_ST_st6_fsm_5 = ap_CS_fsm) or (ap_ST_st7_fsm_6 = ap_CS_fsm) or (ap_ST_st8_fsm_7 = ap_CS_fsm) or (ap_ST_st9_fsm_8 = ap_CS_fsm) or (ap_ST_st10_fsm_9 = ap_CS_fsm) or (ap_ST_st11_fsm_10 = ap_CS_fsm) or (ap_ST_st12_fsm_11 = ap_CS_fsm) or (ap_ST_st13_fsm_12 = ap_CS_fsm) or (ap_ST_st14_fsm_13 = ap_CS_fsm) or (ap_ST_st15_fsm_14 = ap_CS_fsm) or (ap_ST_st16_fsm_15 = ap_CS_fsm) or (ap_ST_st17_fsm_16 = ap_CS_fsm) or (ap_ST_st18_fsm_17 = ap_CS_fsm) or (ap_ST_st19_fsm_18 = ap_CS_fsm) or (ap_ST_st20_fsm_19 = ap_CS_fsm) or (ap_ST_st21_fsm_20 = ap_CS_fsm))) then indices_samples_rsp_read <= grp_sample_iterator_get_offset_fu_192_indices_samples_rsp_read; else indices_samples_rsp_read <= 'X'; end if; end process; -- indices_samples_size assign process. -- indices_samples_size_assign_proc : process(ap_CS_fsm, tmp_i_11_reg_323, grp_sample_iterator_get_offset_fu_192_indices_samples_size, grp_sample_iterator_next_fu_209_indices_samples_size) begin if (((ap_ST_st39_fsm_38 = ap_CS_fsm) or (ap_ST_st32_fsm_31 = ap_CS_fsm) or (ap_ST_st33_fsm_32 = ap_CS_fsm) or (ap_ST_st34_fsm_33 = ap_CS_fsm) or (ap_ST_st35_fsm_34 = ap_CS_fsm) or (ap_ST_st36_fsm_35 = ap_CS_fsm) or (ap_ST_st37_fsm_36 = ap_CS_fsm) or (ap_ST_st38_fsm_37 = ap_CS_fsm))) then indices_samples_size <= grp_sample_iterator_next_fu_209_indices_samples_size; elsif (((ap_ST_st22_fsm_21 = ap_CS_fsm) or ((ap_ST_st4_fsm_3 = ap_CS_fsm) and (tmp_i_11_reg_323 = ap_const_lv1_0)) or (ap_ST_st5_fsm_4 = ap_CS_fsm) or (ap_ST_st6_fsm_5 = ap_CS_fsm) or (ap_ST_st7_fsm_6 = ap_CS_fsm) or (ap_ST_st8_fsm_7 = ap_CS_fsm) or (ap_ST_st9_fsm_8 = ap_CS_fsm) or (ap_ST_st10_fsm_9 = ap_CS_fsm) or (ap_ST_st11_fsm_10 = ap_CS_fsm) or (ap_ST_st12_fsm_11 = ap_CS_fsm) or (ap_ST_st13_fsm_12 = ap_CS_fsm) or (ap_ST_st14_fsm_13 = ap_CS_fsm) or (ap_ST_st15_fsm_14 = ap_CS_fsm) or (ap_ST_st16_fsm_15 = ap_CS_fsm) or (ap_ST_st17_fsm_16 = ap_CS_fsm) or (ap_ST_st18_fsm_17 = ap_CS_fsm) or (ap_ST_st19_fsm_18 = ap_CS_fsm) or (ap_ST_st20_fsm_19 = ap_CS_fsm) or (ap_ST_st21_fsm_20 = ap_CS_fsm))) then indices_samples_size <= grp_sample_iterator_get_offset_fu_192_indices_samples_size; else indices_samples_size <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX"; end if; end process; -- indices_stride_address assign process. -- indices_stride_address_assign_proc : process(ap_CS_fsm, tmp_i_11_reg_323, grp_sample_iterator_get_offset_fu_192_indices_stride_address, grp_sample_iterator_next_fu_209_indices_stride_address) begin if (((ap_ST_st39_fsm_38 = ap_CS_fsm) or (ap_ST_st32_fsm_31 = ap_CS_fsm) or (ap_ST_st33_fsm_32 = ap_CS_fsm) or (ap_ST_st34_fsm_33 = ap_CS_fsm) or (ap_ST_st35_fsm_34 = ap_CS_fsm) or (ap_ST_st36_fsm_35 = ap_CS_fsm) or (ap_ST_st37_fsm_36 = ap_CS_fsm) or (ap_ST_st38_fsm_37 = ap_CS_fsm))) then indices_stride_address <= grp_sample_iterator_next_fu_209_indices_stride_address; elsif (((ap_ST_st22_fsm_21 = ap_CS_fsm) or ((ap_ST_st4_fsm_3 = ap_CS_fsm) and (tmp_i_11_reg_323 = ap_const_lv1_0)) or (ap_ST_st5_fsm_4 = ap_CS_fsm) or (ap_ST_st6_fsm_5 = ap_CS_fsm) or (ap_ST_st7_fsm_6 = ap_CS_fsm) or (ap_ST_st8_fsm_7 = ap_CS_fsm) or (ap_ST_st9_fsm_8 = ap_CS_fsm) or (ap_ST_st10_fsm_9 = ap_CS_fsm) or (ap_ST_st11_fsm_10 = ap_CS_fsm) or (ap_ST_st12_fsm_11 = ap_CS_fsm) or (ap_ST_st13_fsm_12 = ap_CS_fsm) or (ap_ST_st14_fsm_13 = ap_CS_fsm) or (ap_ST_st15_fsm_14 = ap_CS_fsm) or (ap_ST_st16_fsm_15 = ap_CS_fsm) or (ap_ST_st17_fsm_16 = ap_CS_fsm) or (ap_ST_st18_fsm_17 = ap_CS_fsm) or (ap_ST_st19_fsm_18 = ap_CS_fsm) or (ap_ST_st20_fsm_19 = ap_CS_fsm) or (ap_ST_st21_fsm_20 = ap_CS_fsm))) then indices_stride_address <= grp_sample_iterator_get_offset_fu_192_indices_stride_address; else indices_stride_address <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX"; end if; end process; -- indices_stride_dataout assign process. -- indices_stride_dataout_assign_proc : process(ap_CS_fsm, tmp_i_11_reg_323, grp_sample_iterator_get_offset_fu_192_indices_stride_dataout, grp_sample_iterator_next_fu_209_indices_stride_dataout) begin if (((ap_ST_st39_fsm_38 = ap_CS_fsm) or (ap_ST_st32_fsm_31 = ap_CS_fsm) or (ap_ST_st33_fsm_32 = ap_CS_fsm) or (ap_ST_st34_fsm_33 = ap_CS_fsm) or (ap_ST_st35_fsm_34 = ap_CS_fsm) or (ap_ST_st36_fsm_35 = ap_CS_fsm) or (ap_ST_st37_fsm_36 = ap_CS_fsm) or (ap_ST_st38_fsm_37 = ap_CS_fsm))) then indices_stride_dataout <= grp_sample_iterator_next_fu_209_indices_stride_dataout; elsif (((ap_ST_st22_fsm_21 = ap_CS_fsm) or ((ap_ST_st4_fsm_3 = ap_CS_fsm) and (tmp_i_11_reg_323 = ap_const_lv1_0)) or (ap_ST_st5_fsm_4 = ap_CS_fsm) or (ap_ST_st6_fsm_5 = ap_CS_fsm) or (ap_ST_st7_fsm_6 = ap_CS_fsm) or (ap_ST_st8_fsm_7 = ap_CS_fsm) or (ap_ST_st9_fsm_8 = ap_CS_fsm) or (ap_ST_st10_fsm_9 = ap_CS_fsm) or (ap_ST_st11_fsm_10 = ap_CS_fsm) or (ap_ST_st12_fsm_11 = ap_CS_fsm) or (ap_ST_st13_fsm_12 = ap_CS_fsm) or (ap_ST_st14_fsm_13 = ap_CS_fsm) or (ap_ST_st15_fsm_14 = ap_CS_fsm) or (ap_ST_st16_fsm_15 = ap_CS_fsm) or (ap_ST_st17_fsm_16 = ap_CS_fsm) or (ap_ST_st18_fsm_17 = ap_CS_fsm) or (ap_ST_st19_fsm_18 = ap_CS_fsm) or (ap_ST_st20_fsm_19 = ap_CS_fsm) or (ap_ST_st21_fsm_20 = ap_CS_fsm))) then indices_stride_dataout <= grp_sample_iterator_get_offset_fu_192_indices_stride_dataout; else indices_stride_dataout <= "XXXXXXXX"; end if; end process; -- indices_stride_req_din assign process. -- indices_stride_req_din_assign_proc : process(ap_CS_fsm, tmp_i_11_reg_323, grp_sample_iterator_get_offset_fu_192_indices_stride_req_din, grp_sample_iterator_next_fu_209_indices_stride_req_din) begin if (((ap_ST_st39_fsm_38 = ap_CS_fsm) or (ap_ST_st32_fsm_31 = ap_CS_fsm) or (ap_ST_st33_fsm_32 = ap_CS_fsm) or (ap_ST_st34_fsm_33 = ap_CS_fsm) or (ap_ST_st35_fsm_34 = ap_CS_fsm) or (ap_ST_st36_fsm_35 = ap_CS_fsm) or (ap_ST_st37_fsm_36 = ap_CS_fsm) or (ap_ST_st38_fsm_37 = ap_CS_fsm))) then indices_stride_req_din <= grp_sample_iterator_next_fu_209_indices_stride_req_din; elsif (((ap_ST_st22_fsm_21 = ap_CS_fsm) or ((ap_ST_st4_fsm_3 = ap_CS_fsm) and (tmp_i_11_reg_323 = ap_const_lv1_0)) or (ap_ST_st5_fsm_4 = ap_CS_fsm) or (ap_ST_st6_fsm_5 = ap_CS_fsm) or (ap_ST_st7_fsm_6 = ap_CS_fsm) or (ap_ST_st8_fsm_7 = ap_CS_fsm) or (ap_ST_st9_fsm_8 = ap_CS_fsm) or (ap_ST_st10_fsm_9 = ap_CS_fsm) or (ap_ST_st11_fsm_10 = ap_CS_fsm) or (ap_ST_st12_fsm_11 = ap_CS_fsm) or (ap_ST_st13_fsm_12 = ap_CS_fsm) or (ap_ST_st14_fsm_13 = ap_CS_fsm) or (ap_ST_st15_fsm_14 = ap_CS_fsm) or (ap_ST_st16_fsm_15 = ap_CS_fsm) or (ap_ST_st17_fsm_16 = ap_CS_fsm) or (ap_ST_st18_fsm_17 = ap_CS_fsm) or (ap_ST_st19_fsm_18 = ap_CS_fsm) or (ap_ST_st20_fsm_19 = ap_CS_fsm) or (ap_ST_st21_fsm_20 = ap_CS_fsm))) then indices_stride_req_din <= grp_sample_iterator_get_offset_fu_192_indices_stride_req_din; else indices_stride_req_din <= 'X'; end if; end process; -- indices_stride_req_write assign process. -- indices_stride_req_write_assign_proc : process(ap_CS_fsm, tmp_i_11_reg_323, grp_sample_iterator_get_offset_fu_192_indices_stride_req_write, grp_sample_iterator_next_fu_209_indices_stride_req_write) begin if (((ap_ST_st39_fsm_38 = ap_CS_fsm) or (ap_ST_st32_fsm_31 = ap_CS_fsm) or (ap_ST_st33_fsm_32 = ap_CS_fsm) or (ap_ST_st34_fsm_33 = ap_CS_fsm) or (ap_ST_st35_fsm_34 = ap_CS_fsm) or (ap_ST_st36_fsm_35 = ap_CS_fsm) or (ap_ST_st37_fsm_36 = ap_CS_fsm) or (ap_ST_st38_fsm_37 = ap_CS_fsm))) then indices_stride_req_write <= grp_sample_iterator_next_fu_209_indices_stride_req_write; elsif (((ap_ST_st22_fsm_21 = ap_CS_fsm) or ((ap_ST_st4_fsm_3 = ap_CS_fsm) and (tmp_i_11_reg_323 = ap_const_lv1_0)) or (ap_ST_st5_fsm_4 = ap_CS_fsm) or (ap_ST_st6_fsm_5 = ap_CS_fsm) or (ap_ST_st7_fsm_6 = ap_CS_fsm) or (ap_ST_st8_fsm_7 = ap_CS_fsm) or (ap_ST_st9_fsm_8 = ap_CS_fsm) or (ap_ST_st10_fsm_9 = ap_CS_fsm) or (ap_ST_st11_fsm_10 = ap_CS_fsm) or (ap_ST_st12_fsm_11 = ap_CS_fsm) or (ap_ST_st13_fsm_12 = ap_CS_fsm) or (ap_ST_st14_fsm_13 = ap_CS_fsm) or (ap_ST_st15_fsm_14 = ap_CS_fsm) or (ap_ST_st16_fsm_15 = ap_CS_fsm) or (ap_ST_st17_fsm_16 = ap_CS_fsm) or (ap_ST_st18_fsm_17 = ap_CS_fsm) or (ap_ST_st19_fsm_18 = ap_CS_fsm) or (ap_ST_st20_fsm_19 = ap_CS_fsm) or (ap_ST_st21_fsm_20 = ap_CS_fsm))) then indices_stride_req_write <= grp_sample_iterator_get_offset_fu_192_indices_stride_req_write; else indices_stride_req_write <= 'X'; end if; end process; -- indices_stride_rsp_read assign process. -- indices_stride_rsp_read_assign_proc : process(ap_CS_fsm, tmp_i_11_reg_323, grp_sample_iterator_get_offset_fu_192_indices_stride_rsp_read, grp_sample_iterator_next_fu_209_indices_stride_rsp_read) begin if (((ap_ST_st39_fsm_38 = ap_CS_fsm) or (ap_ST_st32_fsm_31 = ap_CS_fsm) or (ap_ST_st33_fsm_32 = ap_CS_fsm) or (ap_ST_st34_fsm_33 = ap_CS_fsm) or (ap_ST_st35_fsm_34 = ap_CS_fsm) or (ap_ST_st36_fsm_35 = ap_CS_fsm) or (ap_ST_st37_fsm_36 = ap_CS_fsm) or (ap_ST_st38_fsm_37 = ap_CS_fsm))) then indices_stride_rsp_read <= grp_sample_iterator_next_fu_209_indices_stride_rsp_read; elsif (((ap_ST_st22_fsm_21 = ap_CS_fsm) or ((ap_ST_st4_fsm_3 = ap_CS_fsm) and (tmp_i_11_reg_323 = ap_const_lv1_0)) or (ap_ST_st5_fsm_4 = ap_CS_fsm) or (ap_ST_st6_fsm_5 = ap_CS_fsm) or (ap_ST_st7_fsm_6 = ap_CS_fsm) or (ap_ST_st8_fsm_7 = ap_CS_fsm) or (ap_ST_st9_fsm_8 = ap_CS_fsm) or (ap_ST_st10_fsm_9 = ap_CS_fsm) or (ap_ST_st11_fsm_10 = ap_CS_fsm) or (ap_ST_st12_fsm_11 = ap_CS_fsm) or (ap_ST_st13_fsm_12 = ap_CS_fsm) or (ap_ST_st14_fsm_13 = ap_CS_fsm) or (ap_ST_st15_fsm_14 = ap_CS_fsm) or (ap_ST_st16_fsm_15 = ap_CS_fsm) or (ap_ST_st17_fsm_16 = ap_CS_fsm) or (ap_ST_st18_fsm_17 = ap_CS_fsm) or (ap_ST_st19_fsm_18 = ap_CS_fsm) or (ap_ST_st20_fsm_19 = ap_CS_fsm) or (ap_ST_st21_fsm_20 = ap_CS_fsm))) then indices_stride_rsp_read <= grp_sample_iterator_get_offset_fu_192_indices_stride_rsp_read; else indices_stride_rsp_read <= 'X'; end if; end process; -- indices_stride_size assign process. -- indices_stride_size_assign_proc : process(ap_CS_fsm, tmp_i_11_reg_323, grp_sample_iterator_get_offset_fu_192_indices_stride_size, grp_sample_iterator_next_fu_209_indices_stride_size) begin if (((ap_ST_st39_fsm_38 = ap_CS_fsm) or (ap_ST_st32_fsm_31 = ap_CS_fsm) or (ap_ST_st33_fsm_32 = ap_CS_fsm) or (ap_ST_st34_fsm_33 = ap_CS_fsm) or (ap_ST_st35_fsm_34 = ap_CS_fsm) or (ap_ST_st36_fsm_35 = ap_CS_fsm) or (ap_ST_st37_fsm_36 = ap_CS_fsm) or (ap_ST_st38_fsm_37 = ap_CS_fsm))) then indices_stride_size <= grp_sample_iterator_next_fu_209_indices_stride_size; elsif (((ap_ST_st22_fsm_21 = ap_CS_fsm) or ((ap_ST_st4_fsm_3 = ap_CS_fsm) and (tmp_i_11_reg_323 = ap_const_lv1_0)) or (ap_ST_st5_fsm_4 = ap_CS_fsm) or (ap_ST_st6_fsm_5 = ap_CS_fsm) or (ap_ST_st7_fsm_6 = ap_CS_fsm) or (ap_ST_st8_fsm_7 = ap_CS_fsm) or (ap_ST_st9_fsm_8 = ap_CS_fsm) or (ap_ST_st10_fsm_9 = ap_CS_fsm) or (ap_ST_st11_fsm_10 = ap_CS_fsm) or (ap_ST_st12_fsm_11 = ap_CS_fsm) or (ap_ST_st13_fsm_12 = ap_CS_fsm) or (ap_ST_st14_fsm_13 = ap_CS_fsm) or (ap_ST_st15_fsm_14 = ap_CS_fsm) or (ap_ST_st16_fsm_15 = ap_CS_fsm) or (ap_ST_st17_fsm_16 = ap_CS_fsm) or (ap_ST_st18_fsm_17 = ap_CS_fsm) or (ap_ST_st19_fsm_18 = ap_CS_fsm) or (ap_ST_st20_fsm_19 = ap_CS_fsm) or (ap_ST_st21_fsm_20 = ap_CS_fsm))) then indices_stride_size <= grp_sample_iterator_get_offset_fu_192_indices_stride_size; else indices_stride_size <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX"; end if; end process; nfa_finals_buckets_address <= grp_nfa_accept_sample_fu_176_nfa_finals_buckets_address; nfa_finals_buckets_dataout <= grp_nfa_accept_sample_fu_176_nfa_finals_buckets_dataout; nfa_finals_buckets_req_din <= grp_nfa_accept_sample_fu_176_nfa_finals_buckets_req_din; nfa_finals_buckets_req_write <= grp_nfa_accept_sample_fu_176_nfa_finals_buckets_req_write; nfa_finals_buckets_rsp_read <= grp_nfa_accept_sample_fu_176_nfa_finals_buckets_rsp_read; nfa_finals_buckets_size <= grp_nfa_accept_sample_fu_176_nfa_finals_buckets_size; nfa_forward_buckets_address <= grp_nfa_accept_sample_fu_176_nfa_forward_buckets_address; nfa_forward_buckets_dataout <= grp_nfa_accept_sample_fu_176_nfa_forward_buckets_dataout; nfa_forward_buckets_req_din <= grp_nfa_accept_sample_fu_176_nfa_forward_buckets_req_din; nfa_forward_buckets_req_write <= grp_nfa_accept_sample_fu_176_nfa_forward_buckets_req_write; nfa_forward_buckets_rsp_read <= grp_nfa_accept_sample_fu_176_nfa_forward_buckets_rsp_read; nfa_forward_buckets_size <= grp_nfa_accept_sample_fu_176_nfa_forward_buckets_size; nfa_initials_buckets_address <= grp_nfa_accept_sample_fu_176_nfa_initials_buckets_address; nfa_initials_buckets_dataout <= grp_nfa_accept_sample_fu_176_nfa_initials_buckets_dataout; nfa_initials_buckets_req_din <= grp_nfa_accept_sample_fu_176_nfa_initials_buckets_req_din; nfa_initials_buckets_req_write <= grp_nfa_accept_sample_fu_176_nfa_initials_buckets_req_write; nfa_initials_buckets_rsp_read <= grp_nfa_accept_sample_fu_176_nfa_initials_buckets_rsp_read; nfa_initials_buckets_size <= grp_nfa_accept_sample_fu_176_nfa_initials_buckets_size; or_cond_fu_245_p2 <= (r_reg_338 xor accept); sample_buffer_address <= grp_nfa_accept_sample_fu_176_sample_address; sample_buffer_dataout <= grp_nfa_accept_sample_fu_176_sample_dataout; sample_buffer_req_din <= grp_nfa_accept_sample_fu_176_sample_req_din; sample_buffer_req_write <= grp_nfa_accept_sample_fu_176_sample_req_write; sample_buffer_rsp_read <= grp_nfa_accept_sample_fu_176_sample_rsp_read; sample_buffer_size <= grp_nfa_accept_sample_fu_176_sample_size; stop_on_first_read_read_fu_102_p2 <= stop_on_first; tmp_i_10_fu_233_p2 <= "1" when (i_index_reg_144 = end_index) else "0"; tmp_i_11_fu_238_p2 <= (tmp_i_reg_313 and tmp_i_10_reg_318); tmp_i_fu_228_p2 <= "1" when (i_sample_reg_154 = end_sample) else "0"; end behav;
lgpl-3.0
dad8fae2cdb3b867d6c00294594648eb
0.64282
2.654678
false
false
false
false
grwlf/vsim
vhdl_ct/ct00190.vhd
1
17,821
------------------------------------------------------------------------------- -- -- Copyright (c) 1989 by Intermetrics, Inc. -- All rights reserved. -- ------------------------------------------------------------------------------- -- -- TEST NAME: -- -- CT00190 -- -- AUTHOR: -- -- G. Tominovich -- -- TEST OBJECTIVES: -- -- 8.3 (1) -- 8.3 (2) -- 8.3 (4) -- 8.3 (5) -- 8.3.1 (4) -- -- DESIGN UNIT ORDERING: -- -- PKG00190 -- PKG00190/BODY -- ENT00190(ARCH00190) -- ENT00190_Test_Bench(ARCH00190_Test_Bench) -- -- REVISION HISTORY: -- -- 08-JUL-1987 - initial revision -- -- NOTES: -- -- self-checking -- automatically generated -- use WORK.STANDARD_TYPES.all ; package PKG00190 is type r_st_rec1 is record f1 : integer ; f2 : st_rec1 ; end record ; function c_r_st_rec1_1 return r_st_rec1 ; -- (c_integer_1, c_st_rec1_1) ; function c_r_st_rec1_2 return r_st_rec1 ; -- (c_integer_2, c_st_rec1_2) ; -- type r_st_rec2 is record f1 : integer ; f2 : st_rec2 ; end record ; function c_r_st_rec2_1 return r_st_rec2 ; -- (c_integer_1, c_st_rec2_1) ; function c_r_st_rec2_2 return r_st_rec2 ; -- (c_integer_2, c_st_rec2_2) ; -- type r_st_rec3 is record f1 : integer ; f2 : st_rec3 ; end record ; function c_r_st_rec3_1 return r_st_rec3 ; -- (c_integer_1, c_st_rec3_1) ; function c_r_st_rec3_2 return r_st_rec3 ; -- (c_integer_2, c_st_rec3_2) ; -- -- end PKG00190 ; -- package body PKG00190 is function c_r_st_rec1_1 return r_st_rec1 is begin return (c_integer_1, c_st_rec1_1) ; end c_r_st_rec1_1 ; -- function c_r_st_rec1_2 return r_st_rec1 is begin return (c_integer_2, c_st_rec1_2) ; end c_r_st_rec1_2 ; -- -- function c_r_st_rec2_1 return r_st_rec2 is begin return (c_integer_1, c_st_rec2_1) ; end c_r_st_rec2_1 ; -- function c_r_st_rec2_2 return r_st_rec2 is begin return (c_integer_2, c_st_rec2_2) ; end c_r_st_rec2_2 ; -- -- function c_r_st_rec3_1 return r_st_rec3 is begin return (c_integer_1, c_st_rec3_1) ; end c_r_st_rec3_1 ; -- function c_r_st_rec3_2 return r_st_rec3 is begin return (c_integer_2, c_st_rec3_2) ; end c_r_st_rec3_2 ; -- -- -- end PKG00190 ; -- use WORK.STANDARD_TYPES.all ; use WORK.PKG00190.all ; entity ENT00190 is port ( s_r_st_rec1 : inout r_st_rec1 ; s_r_st_rec2 : inout r_st_rec2 ; s_r_st_rec3 : inout r_st_rec3 ) ; subtype chk_sig_type is integer range -1 to 100 ; signal chk_r_st_rec1 : chk_sig_type := -1 ; signal chk_r_st_rec2 : chk_sig_type := -1 ; signal chk_r_st_rec3 : chk_sig_type := -1 ; -- -- procedure Proc1 ( signal s_r_st_rec1 : inout r_st_rec1 ; variable counter : inout integer ; variable correct : inout boolean ; variable savtime : inout time ; signal chk_r_st_rec1 : out chk_sig_type ) is begin case counter is when 0 => s_r_st_rec1.f2.f2 <= c_r_st_rec1_2.f2.f2 after 10 ns, c_r_st_rec1_1.f2.f2 after 20 ns ; -- when 1 => correct := s_r_st_rec1.f2.f2 = c_r_st_rec1_2.f2.f2 and (savtime + 10 ns) = Std.Standard.Now ; -- when 2 => correct := correct and s_r_st_rec1.f2.f2 = c_r_st_rec1_1.f2.f2 and (savtime + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00190.P1" , "Multi inertial transactions occurred on signal " & "asg with selected name prefixed by a selected name on LHS", correct ) ; s_r_st_rec1.f2.f2 <= c_r_st_rec1_2.f2.f2 after 10 ns , c_r_st_rec1_1.f2.f2 after 20 ns , c_r_st_rec1_2.f2.f2 after 30 ns , c_r_st_rec1_1.f2.f2 after 40 ns ; -- when 3 => correct := s_r_st_rec1.f2.f2 = c_r_st_rec1_2.f2.f2 and (savtime + 10 ns) = Std.Standard.Now ; s_r_st_rec1.f2.f2 <= c_r_st_rec1_1.f2.f2 after 5 ns ; -- when 4 => correct := correct and s_r_st_rec1.f2.f2 = c_r_st_rec1_1.f2.f2 and (savtime + 5 ns) = Std.Standard.Now ; test_report ( "ARCH00190" , "One inertial transaction occurred on signal " & "asg with selected name prefixed by an selected name on LHS", correct ) ; s_r_st_rec1.f2.f2 <= transport c_r_st_rec1_1.f2.f2 after 100 ns ; -- when 5 => correct := s_r_st_rec1.f2.f2 = c_r_st_rec1_1.f2.f2 and (savtime + 100 ns) = Std.Standard.Now ; test_report ( "ARCH00190" , "Old transactions were removed on signal " & "asg with selected name prefixed by an selected name on LHS", correct ) ; s_r_st_rec1.f2.f2 <= c_r_st_rec1_2.f2.f2 after 10 ns , c_r_st_rec1_1.f2.f2 after 20 ns , c_r_st_rec1_2.f2.f2 after 30 ns , c_r_st_rec1_1.f2.f2 after 40 ns ; -- when 6 => correct := s_r_st_rec1.f2.f2 = c_r_st_rec1_2.f2.f2 and (savtime + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00190" , "One inertial transaction occurred on signal " & "asg with selected name prefixed by an selected name on LHS", correct ) ; -- Last transaction above is marked s_r_st_rec1.f2.f2 <= c_r_st_rec1_1.f2.f2 after 40 ns ; -- when 7 => correct := s_r_st_rec1.f2.f2 = c_r_st_rec1_1.f2.f2 and (savtime + 30 ns) = Std.Standard.Now ; -- when 8 => correct := correct and s_r_st_rec1.f2.f2 = c_r_st_rec1_1.f2.f2 and (savtime + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00190" , "Inertial semantics check on a signal " & "asg with selected name prefixed by an selected name on LHS", correct ) ; -- when others => test_report ( "ARCH00190" , "Inertial semantics check on a signal " & "asg with selected name prefixed by an selected name on LHS", false ) ; -- end case ; -- savtime := Std.Standard.Now ; chk_r_st_rec1 <= transport counter after (1 us - savtime) ; counter := counter + 1; -- end Proc1 ; -- procedure Proc2 ( signal s_r_st_rec2 : inout r_st_rec2 ; variable counter : inout integer ; variable correct : inout boolean ; variable savtime : inout time ; signal chk_r_st_rec2 : out chk_sig_type ) is begin case counter is when 0 => s_r_st_rec2.f2.f2 <= c_r_st_rec2_2.f2.f2 after 10 ns, c_r_st_rec2_1.f2.f2 after 20 ns ; -- when 1 => correct := s_r_st_rec2.f2.f2 = c_r_st_rec2_2.f2.f2 and (savtime + 10 ns) = Std.Standard.Now ; -- when 2 => correct := correct and s_r_st_rec2.f2.f2 = c_r_st_rec2_1.f2.f2 and (savtime + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00190.P2" , "Multi inertial transactions occurred on signal " & "asg with selected name prefixed by a selected name on LHS", correct ) ; s_r_st_rec2.f2.f2 <= c_r_st_rec2_2.f2.f2 after 10 ns , c_r_st_rec2_1.f2.f2 after 20 ns , c_r_st_rec2_2.f2.f2 after 30 ns , c_r_st_rec2_1.f2.f2 after 40 ns ; -- when 3 => correct := s_r_st_rec2.f2.f2 = c_r_st_rec2_2.f2.f2 and (savtime + 10 ns) = Std.Standard.Now ; s_r_st_rec2.f2.f2 <= c_r_st_rec2_1.f2.f2 after 5 ns ; -- when 4 => correct := correct and s_r_st_rec2.f2.f2 = c_r_st_rec2_1.f2.f2 and (savtime + 5 ns) = Std.Standard.Now ; test_report ( "ARCH00190" , "One inertial transaction occurred on signal " & "asg with selected name prefixed by an selected name on LHS", correct ) ; s_r_st_rec2.f2.f2 <= transport c_r_st_rec2_1.f2.f2 after 100 ns ; -- when 5 => correct := s_r_st_rec2.f2.f2 = c_r_st_rec2_1.f2.f2 and (savtime + 100 ns) = Std.Standard.Now ; test_report ( "ARCH00190" , "Old transactions were removed on signal " & "asg with selected name prefixed by an selected name on LHS", correct ) ; s_r_st_rec2.f2.f2 <= c_r_st_rec2_2.f2.f2 after 10 ns , c_r_st_rec2_1.f2.f2 after 20 ns , c_r_st_rec2_2.f2.f2 after 30 ns , c_r_st_rec2_1.f2.f2 after 40 ns ; -- when 6 => correct := s_r_st_rec2.f2.f2 = c_r_st_rec2_2.f2.f2 and (savtime + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00190" , "One inertial transaction occurred on signal " & "asg with selected name prefixed by an selected name on LHS", correct ) ; -- Last transaction above is marked s_r_st_rec2.f2.f2 <= c_r_st_rec2_1.f2.f2 after 40 ns ; -- when 7 => correct := s_r_st_rec2.f2.f2 = c_r_st_rec2_1.f2.f2 and (savtime + 30 ns) = Std.Standard.Now ; -- when 8 => correct := correct and s_r_st_rec2.f2.f2 = c_r_st_rec2_1.f2.f2 and (savtime + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00190" , "Inertial semantics check on a signal " & "asg with selected name prefixed by an selected name on LHS", correct ) ; -- when others => test_report ( "ARCH00190" , "Inertial semantics check on a signal " & "asg with selected name prefixed by an selected name on LHS", false ) ; -- end case ; -- savtime := Std.Standard.Now ; chk_r_st_rec2 <= transport counter after (1 us - savtime) ; counter := counter + 1; -- end Proc2 ; -- procedure Proc3 ( signal s_r_st_rec3 : inout r_st_rec3 ; variable counter : inout integer ; variable correct : inout boolean ; variable savtime : inout time ; signal chk_r_st_rec3 : out chk_sig_type ) is begin case counter is when 0 => s_r_st_rec3.f2.f2 <= c_r_st_rec3_2.f2.f2 after 10 ns, c_r_st_rec3_1.f2.f2 after 20 ns ; -- when 1 => correct := s_r_st_rec3.f2.f2 = c_r_st_rec3_2.f2.f2 and (savtime + 10 ns) = Std.Standard.Now ; -- when 2 => correct := correct and s_r_st_rec3.f2.f2 = c_r_st_rec3_1.f2.f2 and (savtime + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00190.P3" , "Multi inertial transactions occurred on signal " & "asg with selected name prefixed by a selected name on LHS", correct ) ; s_r_st_rec3.f2.f2 <= c_r_st_rec3_2.f2.f2 after 10 ns , c_r_st_rec3_1.f2.f2 after 20 ns , c_r_st_rec3_2.f2.f2 after 30 ns , c_r_st_rec3_1.f2.f2 after 40 ns ; -- when 3 => correct := s_r_st_rec3.f2.f2 = c_r_st_rec3_2.f2.f2 and (savtime + 10 ns) = Std.Standard.Now ; s_r_st_rec3.f2.f2 <= c_r_st_rec3_1.f2.f2 after 5 ns ; -- when 4 => correct := correct and s_r_st_rec3.f2.f2 = c_r_st_rec3_1.f2.f2 and (savtime + 5 ns) = Std.Standard.Now ; test_report ( "ARCH00190" , "One inertial transaction occurred on signal " & "asg with selected name prefixed by an selected name on LHS", correct ) ; s_r_st_rec3.f2.f2 <= transport c_r_st_rec3_1.f2.f2 after 100 ns ; -- when 5 => correct := s_r_st_rec3.f2.f2 = c_r_st_rec3_1.f2.f2 and (savtime + 100 ns) = Std.Standard.Now ; test_report ( "ARCH00190" , "Old transactions were removed on signal " & "asg with selected name prefixed by an selected name on LHS", correct ) ; s_r_st_rec3.f2.f2 <= c_r_st_rec3_2.f2.f2 after 10 ns , c_r_st_rec3_1.f2.f2 after 20 ns , c_r_st_rec3_2.f2.f2 after 30 ns , c_r_st_rec3_1.f2.f2 after 40 ns ; -- when 6 => correct := s_r_st_rec3.f2.f2 = c_r_st_rec3_2.f2.f2 and (savtime + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00190" , "One inertial transaction occurred on signal " & "asg with selected name prefixed by an selected name on LHS", correct ) ; -- Last transaction above is marked s_r_st_rec3.f2.f2 <= c_r_st_rec3_1.f2.f2 after 40 ns ; -- when 7 => correct := s_r_st_rec3.f2.f2 = c_r_st_rec3_1.f2.f2 and (savtime + 30 ns) = Std.Standard.Now ; -- when 8 => correct := correct and s_r_st_rec3.f2.f2 = c_r_st_rec3_1.f2.f2 and (savtime + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00190" , "Inertial semantics check on a signal " & "asg with selected name prefixed by an selected name on LHS", correct ) ; -- when others => test_report ( "ARCH00190" , "Inertial semantics check on a signal " & "asg with selected name prefixed by an selected name on LHS", false ) ; -- end case ; -- savtime := Std.Standard.Now ; chk_r_st_rec3 <= transport counter after (1 us - savtime) ; counter := counter + 1; -- end Proc3 ; -- -- end ENT00190 ; -- architecture ARCH00190 of ENT00190 is begin P1 : process variable counter : integer := 0 ; variable correct : boolean ; variable savtime : time ; begin Proc1 ( s_r_st_rec1, counter, correct, savtime, chk_r_st_rec1 ) ; wait until (not s_r_st_rec1'Quiet) and (savtime /= Std.Standard.Now) ; -- end process P1 ; -- PGEN_CHKP_1 : process ( chk_r_st_rec1 ) begin if Std.Standard.Now > 0 ns then test_report ( "P1" , "Inertial transactions entirely completed", chk_r_st_rec1 = 8 ) ; end if ; end process PGEN_CHKP_1 ; -- -- P2 : process variable counter : integer := 0 ; variable correct : boolean ; variable savtime : time ; begin Proc2 ( s_r_st_rec2, counter, correct, savtime, chk_r_st_rec2 ) ; wait until (not s_r_st_rec2'Quiet) and (savtime /= Std.Standard.Now) ; -- end process P2 ; -- PGEN_CHKP_2 : process ( chk_r_st_rec2 ) begin if Std.Standard.Now > 0 ns then test_report ( "P2" , "Inertial transactions entirely completed", chk_r_st_rec2 = 8 ) ; end if ; end process PGEN_CHKP_2 ; -- -- P3 : process variable counter : integer := 0 ; variable correct : boolean ; variable savtime : time ; begin Proc3 ( s_r_st_rec3, counter, correct, savtime, chk_r_st_rec3 ) ; wait until (not s_r_st_rec3'Quiet) and (savtime /= Std.Standard.Now) ; -- end process P3 ; -- PGEN_CHKP_3 : process ( chk_r_st_rec3 ) begin if Std.Standard.Now > 0 ns then test_report ( "P3" , "Inertial transactions entirely completed", chk_r_st_rec3 = 8 ) ; end if ; end process PGEN_CHKP_3 ; -- -- -- end ARCH00190 ; -- use WORK.STANDARD_TYPES.all ; use WORK.PKG00190.all ; entity ENT00190_Test_Bench is signal s_r_st_rec1 : r_st_rec1 := c_r_st_rec1_1 ; signal s_r_st_rec2 : r_st_rec2 := c_r_st_rec2_1 ; signal s_r_st_rec3 : r_st_rec3 := c_r_st_rec3_1 ; -- end ENT00190_Test_Bench ; -- architecture ARCH00190_Test_Bench of ENT00190_Test_Bench is begin L1: block component UUT port ( s_r_st_rec1 : inout r_st_rec1 ; s_r_st_rec2 : inout r_st_rec2 ; s_r_st_rec3 : inout r_st_rec3 ) ; end component ; -- for CIS1 : UUT use entity WORK.ENT00190 ( ARCH00190 ) ; begin CIS1 : UUT port map ( s_r_st_rec1 , s_r_st_rec2 , s_r_st_rec3 ) ; end block L1 ; end ARCH00190_Test_Bench ;
gpl-3.0
dbfcfd3fda72585cbff99d5549f219a8
0.479154
3.136948
false
false
false
false
jairov4/accel-oil
solution_virtex5_plb/impl/vhdl/nfa_get_finals.vhd
3
12,263
-- ============================================================== -- RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC -- Version: 2014.1 -- Copyright (C) 2014 Xilinx Inc. All rights reserved. -- -- =========================================================== library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; entity nfa_get_finals is port ( ap_clk : IN STD_LOGIC; ap_rst : IN STD_LOGIC; ap_start : IN STD_LOGIC; ap_done : OUT STD_LOGIC; ap_idle : OUT STD_LOGIC; ap_ready : OUT STD_LOGIC; ap_ce : IN STD_LOGIC; nfa_finals_buckets_req_din : OUT STD_LOGIC; nfa_finals_buckets_req_full_n : IN STD_LOGIC; nfa_finals_buckets_req_write : OUT STD_LOGIC; nfa_finals_buckets_rsp_empty_n : IN STD_LOGIC; nfa_finals_buckets_rsp_read : OUT STD_LOGIC; nfa_finals_buckets_address : OUT STD_LOGIC_VECTOR (31 downto 0); nfa_finals_buckets_datain : IN STD_LOGIC_VECTOR (31 downto 0); nfa_finals_buckets_dataout : OUT STD_LOGIC_VECTOR (31 downto 0); nfa_finals_buckets_size : OUT STD_LOGIC_VECTOR (31 downto 0); ap_return_0 : OUT STD_LOGIC_VECTOR (31 downto 0); ap_return_1 : OUT STD_LOGIC_VECTOR (31 downto 0) ); end; architecture behav of nfa_get_finals is constant ap_const_logic_1 : STD_LOGIC := '1'; constant ap_const_logic_0 : STD_LOGIC := '0'; constant ap_ST_pp0_stg0_fsm_0 : STD_LOGIC_VECTOR (1 downto 0) := "10"; constant ap_ST_pp0_stg1_fsm_1 : STD_LOGIC_VECTOR (1 downto 0) := "00"; constant ap_ST_pp0_stg2_fsm_2 : STD_LOGIC_VECTOR (1 downto 0) := "01"; constant ap_ST_pp0_stg3_fsm_3 : STD_LOGIC_VECTOR (1 downto 0) := "11"; constant ap_const_lv64_1 : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000000000000000000000000000000000000000000000001"; constant ap_const_lv32_0 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000000"; constant ap_const_lv32_1 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000001"; signal ap_CS_fsm : STD_LOGIC_VECTOR (1 downto 0) := "10"; signal ap_reg_ppiten_pp0_it0 : STD_LOGIC; signal ap_reg_ppiten_pp0_it1 : STD_LOGIC := '0'; signal nfa_finals_buckets_read_reg_59 : STD_LOGIC_VECTOR (31 downto 0); signal ap_reg_ppiten_pp0_it0_preg : STD_LOGIC := '0'; signal ap_NS_fsm : STD_LOGIC_VECTOR (1 downto 0); signal ap_sig_pprstidle_pp0 : STD_LOGIC; signal ap_sig_bdd_131 : BOOLEAN; signal ap_sig_bdd_130 : BOOLEAN; begin -- the current state (ap_CS_fsm) of the state machine. -- ap_CS_fsm_assign_proc : process(ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (ap_rst = '1') then ap_CS_fsm <= ap_ST_pp0_stg0_fsm_0; else ap_CS_fsm <= ap_NS_fsm; end if; end if; end process; -- ap_reg_ppiten_pp0_it0_preg assign process. -- ap_reg_ppiten_pp0_it0_preg_assign_proc : process(ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (ap_rst = '1') then ap_reg_ppiten_pp0_it0_preg <= ap_const_logic_0; else if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and not((not((ap_const_logic_1 = ap_ce)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)))))) then ap_reg_ppiten_pp0_it0_preg <= ap_start; end if; end if; end if; end process; -- ap_reg_ppiten_pp0_it1 assign process. -- ap_reg_ppiten_pp0_it1_assign_proc : process(ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (ap_rst = '1') then ap_reg_ppiten_pp0_it1 <= ap_const_logic_0; else if (((ap_ST_pp0_stg1_fsm_1 = ap_CS_fsm) and not((not((ap_const_logic_1 = ap_ce)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and (nfa_finals_buckets_rsp_empty_n = ap_const_logic_0)))) and not((ap_const_logic_1 = ap_reg_ppiten_pp0_it0)))) then ap_reg_ppiten_pp0_it1 <= ap_const_logic_0; elsif (((ap_ST_pp0_stg3_fsm_3 = ap_CS_fsm) and (ap_const_logic_1 = ap_ce))) then ap_reg_ppiten_pp0_it1 <= ap_reg_ppiten_pp0_it0; end if; end if; end if; end process; -- assign process. -- process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_const_logic_1 = ap_ce) and (ap_ST_pp0_stg2_fsm_2 = ap_CS_fsm) and not(((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (nfa_finals_buckets_rsp_empty_n = ap_const_logic_0))))) then nfa_finals_buckets_read_reg_59 <= nfa_finals_buckets_datain; end if; end if; end process; -- the next state (ap_NS_fsm) of the state machine. -- ap_NS_fsm_assign_proc : process (ap_start , ap_CS_fsm , ap_reg_ppiten_pp0_it0 , ap_reg_ppiten_pp0_it1 , ap_ce , nfa_finals_buckets_rsp_empty_n , ap_sig_pprstidle_pp0) begin case ap_CS_fsm is when ap_ST_pp0_stg0_fsm_0 => if ((not((not((ap_const_logic_1 = ap_ce)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)))) and not(((ap_const_logic_0 = ap_reg_ppiten_pp0_it1) and (ap_const_logic_0 = ap_start))))) then ap_NS_fsm <= ap_ST_pp0_stg1_fsm_1; else ap_NS_fsm <= ap_ST_pp0_stg0_fsm_0; end if; when ap_ST_pp0_stg1_fsm_1 => if ((not((not((ap_const_logic_1 = ap_ce)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and (nfa_finals_buckets_rsp_empty_n = ap_const_logic_0)))) and not((ap_const_logic_1 = ap_sig_pprstidle_pp0)))) then ap_NS_fsm <= ap_ST_pp0_stg2_fsm_2; elsif ((not((not((ap_const_logic_1 = ap_ce)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and (nfa_finals_buckets_rsp_empty_n = ap_const_logic_0)))) and (ap_const_logic_1 = ap_sig_pprstidle_pp0))) then ap_NS_fsm <= ap_ST_pp0_stg0_fsm_0; else ap_NS_fsm <= ap_ST_pp0_stg1_fsm_1; end if; when ap_ST_pp0_stg2_fsm_2 => if (not((not((ap_const_logic_1 = ap_ce)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (nfa_finals_buckets_rsp_empty_n = ap_const_logic_0))))) then ap_NS_fsm <= ap_ST_pp0_stg3_fsm_3; else ap_NS_fsm <= ap_ST_pp0_stg2_fsm_2; end if; when ap_ST_pp0_stg3_fsm_3 => if ((ap_const_logic_1 = ap_ce)) then ap_NS_fsm <= ap_ST_pp0_stg0_fsm_0; else ap_NS_fsm <= ap_ST_pp0_stg3_fsm_3; end if; when others => ap_NS_fsm <= "XX"; end case; end process; -- ap_done assign process. -- ap_done_assign_proc : process(ap_start, ap_CS_fsm, ap_reg_ppiten_pp0_it0, ap_reg_ppiten_pp0_it1, ap_ce, nfa_finals_buckets_rsp_empty_n) begin if (((not((ap_const_logic_1 = ap_start)) and (ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and (ap_const_logic_1 = ap_ce) and (ap_ST_pp0_stg1_fsm_1 = ap_CS_fsm) and not(((ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and (nfa_finals_buckets_rsp_empty_n = ap_const_logic_0)))))) then ap_done <= ap_const_logic_1; else ap_done <= ap_const_logic_0; end if; end process; -- ap_idle assign process. -- ap_idle_assign_proc : process(ap_start, ap_CS_fsm, ap_reg_ppiten_pp0_it0, ap_reg_ppiten_pp0_it1) begin if ((not((ap_const_logic_1 = ap_start)) and (ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it0) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it1))) then ap_idle <= ap_const_logic_1; else ap_idle <= ap_const_logic_0; end if; end process; -- ap_ready assign process. -- ap_ready_assign_proc : process(ap_CS_fsm, ap_reg_ppiten_pp0_it0, ap_ce) begin if (((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_ST_pp0_stg3_fsm_3 = ap_CS_fsm) and (ap_const_logic_1 = ap_ce))) then ap_ready <= ap_const_logic_1; else ap_ready <= ap_const_logic_0; end if; end process; -- ap_reg_ppiten_pp0_it0 assign process. -- ap_reg_ppiten_pp0_it0_assign_proc : process(ap_start, ap_CS_fsm, ap_reg_ppiten_pp0_it0_preg) begin if ((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm)) then ap_reg_ppiten_pp0_it0 <= ap_start; else ap_reg_ppiten_pp0_it0 <= ap_reg_ppiten_pp0_it0_preg; end if; end process; ap_return_0 <= nfa_finals_buckets_read_reg_59; ap_return_1 <= nfa_finals_buckets_datain; -- ap_sig_bdd_130 assign process. -- ap_sig_bdd_130_assign_proc : process(ap_reg_ppiten_pp0_it0, ap_ce) begin ap_sig_bdd_130 <= ((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_const_logic_1 = ap_ce)); end process; -- ap_sig_bdd_131 assign process. -- ap_sig_bdd_131_assign_proc : process(ap_start, ap_CS_fsm, ap_reg_ppiten_pp0_it0) begin ap_sig_bdd_131 <= ((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and not(((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)))); end process; -- ap_sig_pprstidle_pp0 assign process. -- ap_sig_pprstidle_pp0_assign_proc : process(ap_start, ap_reg_ppiten_pp0_it0) begin if (((ap_const_logic_0 = ap_reg_ppiten_pp0_it0) and (ap_const_logic_0 = ap_start))) then ap_sig_pprstidle_pp0 <= ap_const_logic_1; else ap_sig_pprstidle_pp0 <= ap_const_logic_0; end if; end process; -- nfa_finals_buckets_address assign process. -- nfa_finals_buckets_address_assign_proc : process(ap_CS_fsm, ap_sig_bdd_131, ap_sig_bdd_130) begin if (ap_sig_bdd_130) then if ((ap_ST_pp0_stg3_fsm_3 = ap_CS_fsm)) then nfa_finals_buckets_address <= ap_const_lv64_1(32 - 1 downto 0); elsif (ap_sig_bdd_131) then nfa_finals_buckets_address <= ap_const_lv32_0; else nfa_finals_buckets_address <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX"; end if; else nfa_finals_buckets_address <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX"; end if; end process; nfa_finals_buckets_dataout <= ap_const_lv32_0; nfa_finals_buckets_req_din <= ap_const_logic_0; -- nfa_finals_buckets_req_write assign process. -- nfa_finals_buckets_req_write_assign_proc : process(ap_start, ap_CS_fsm, ap_reg_ppiten_pp0_it0, ap_ce) begin if ((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_ST_pp0_stg3_fsm_3 = ap_CS_fsm) and (ap_const_logic_1 = ap_ce)) or ((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_const_logic_1 = ap_ce) and not(((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)))))) then nfa_finals_buckets_req_write <= ap_const_logic_1; else nfa_finals_buckets_req_write <= ap_const_logic_0; end if; end process; -- nfa_finals_buckets_rsp_read assign process. -- nfa_finals_buckets_rsp_read_assign_proc : process(ap_CS_fsm, ap_reg_ppiten_pp0_it0, ap_reg_ppiten_pp0_it1, ap_ce, nfa_finals_buckets_rsp_empty_n) begin if ((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_const_logic_1 = ap_ce) and (ap_ST_pp0_stg2_fsm_2 = ap_CS_fsm) and not(((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (nfa_finals_buckets_rsp_empty_n = ap_const_logic_0)))) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and (ap_const_logic_1 = ap_ce) and (ap_ST_pp0_stg1_fsm_1 = ap_CS_fsm) and not(((ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and (nfa_finals_buckets_rsp_empty_n = ap_const_logic_0)))))) then nfa_finals_buckets_rsp_read <= ap_const_logic_1; else nfa_finals_buckets_rsp_read <= ap_const_logic_0; end if; end process; nfa_finals_buckets_size <= ap_const_lv32_1; end behav;
lgpl-3.0
2dadc872121b813224f1cb5805cb8b34
0.579467
2.781987
false
false
false
false
takeshineshiro/fpga_fibre_scan
HUCB2P0_150701/adc/ADS58C48.vhd
1
5,037
--***************************************************************************** -- @Copyright 2013 by SIAT_HFUS_TEAM, All rights reserved. -- Module name : ADS58C48 -- Call by : -- Description : this module is the top module of ADS58C48. -- IC : 5CGXFC7D7F31C8N -- Version : A -- Note: : -- Author : Peitian Mu -- Date : 2013.12.02 -- Update : --***************************************************************************** library IEEE; use IEEE.std_logic_1164.ALL; use IEEE.std_logic_arith.all; use IEEE.std_logic_unsigned.all; entity ADS58C48 is port ( O_adca_sen : out std_logic; I_adca_sd : in std_logic; O_adca_sdata : out std_logic; O_adca_sclk : out std_logic; O_adca_rst : out std_logic; O_adca_pdn : out std_logic; O_adca_snrb0 : out std_logic; O_adca_snrb1 : out std_logic; I_adca_oclk : in std_logic; I_adca_d : in std_logic_vector(5 downto 0); I_adcb_d : in std_logic_vector(5 downto 0); I_adcc_d : in std_logic_vector(5 downto 0); I_adcd_d : in std_logic_vector(5 downto 0); O_adca_data : out std_logic_vector(11 downto 0); O_adcb_data : out std_logic_vector(11 downto 0); O_adcc_data : out std_logic_vector(11 downto 0); O_adcd_data : out std_logic_vector(11 downto 0) ); end ADS58C48; architecture rtl of ADS58C48 is component ADC_DDIO port( datain : IN STD_LOGIC_VECTOR (5 DOWNTO 0); inclock : IN STD_LOGIC ; dataout_h : OUT STD_LOGIC_VECTOR (5 DOWNTO 0); dataout_l : OUT STD_LOGIC_VECTOR (5 DOWNTO 0) ); end component; signal S_adca_ad_12 : std_logic_vector(11 downto 0); signal S_adcb_ad_12 : std_logic_vector(11 downto 0); signal S_adcc_ad_12 : std_logic_vector(11 downto 0); signal S_adcd_ad_12 : std_logic_vector(11 downto 0); begin U0_ddio_in_a: ADC_DDIO port map( datain => I_adca_d, inclock => I_adca_oclk, dataout_h => S_adca_ad_12(11 downto 6), dataout_l => S_adca_ad_12(5 downto 0) ); O_adca_data(11) <= S_adca_ad_12(11); O_adca_data(10) <= S_adca_ad_12(5); O_adca_data(9) <= S_adca_ad_12(10); O_adca_data(8) <= S_adca_ad_12(4); O_adca_data(7) <= S_adca_ad_12(9); O_adca_data(6) <= S_adca_ad_12(3); O_adca_data(5) <= S_adca_ad_12(8); O_adca_data(4) <= S_adca_ad_12(2); O_adca_data(3) <= S_adca_ad_12(7); O_adca_data(2) <= S_adca_ad_12(1); O_adca_data(1) <= S_adca_ad_12(6); O_adca_data(0) <= S_adca_ad_12(0); U1_ddio_in_b: ADC_DDIO port map( datain => I_adcb_d, inclock => I_adca_oclk, dataout_h => S_adcb_ad_12(11 downto 6), dataout_l => S_adcb_ad_12(5 downto 0) ); O_adcb_data(11) <= S_adcb_ad_12(11); O_adcb_data(10) <= S_adcb_ad_12(5); O_adcb_data(9) <= S_adcb_ad_12(10); O_adcb_data(8) <= S_adcb_ad_12(4); O_adcb_data(7) <= S_adcb_ad_12(9); O_adcb_data(6) <= S_adcb_ad_12(3); O_adcb_data(5) <= S_adcb_ad_12(8); O_adcb_data(4) <= S_adcb_ad_12(2); O_adcb_data(3) <= S_adcb_ad_12(7); O_adcb_data(2) <= S_adcb_ad_12(1); O_adcb_data(1) <= S_adcb_ad_12(6); O_adcb_data(0) <= S_adcb_ad_12(0); U2_ddio_in_c: ADC_DDIO port map( datain => I_adcc_d, inclock => I_adca_oclk, dataout_h => S_adcc_ad_12(11 downto 6), dataout_l => S_adcc_ad_12(5 downto 0) ); O_adcc_data(11) <= S_adcc_ad_12(11); O_adcc_data(10) <= S_adcc_ad_12(5); O_adcc_data(9) <= S_adcc_ad_12(10); O_adcc_data(8) <= S_adcc_ad_12(4); O_adcc_data(7) <= S_adcc_ad_12(9); O_adcc_data(6) <= S_adcc_ad_12(3); O_adcc_data(5) <= S_adcc_ad_12(8); O_adcc_data(4) <= S_adcc_ad_12(2); O_adcc_data(3) <= S_adcc_ad_12(7); O_adcc_data(2) <= S_adcc_ad_12(1); O_adcc_data(1) <= S_adcc_ad_12(6); O_adcc_data(0) <= S_adcc_ad_12(0); U3_ddio_in_d: ADC_DDIO port map( datain => I_adcd_d, inclock => I_adca_oclk, dataout_h => S_adcd_ad_12(11 downto 6), dataout_l => S_adcd_ad_12(5 downto 0) ); O_adcd_data(11) <= S_adcd_ad_12(11); O_adcd_data(10) <= S_adcd_ad_12(5); O_adcd_data(9) <= S_adcd_ad_12(10); O_adcd_data(8) <= S_adcd_ad_12(4); O_adcd_data(7) <= S_adcd_ad_12(9); O_adcd_data(6) <= S_adcd_ad_12(3); O_adcd_data(5) <= S_adcd_ad_12(8); O_adcd_data(4) <= S_adcd_ad_12(2); O_adcd_data(3) <= S_adcd_ad_12(7); O_adcd_data(2) <= S_adcd_ad_12(1); O_adcd_data(1) <= S_adcd_ad_12(6); O_adcd_data(0) <= S_adcd_ad_12(0); end rtl;
apache-2.0
d1c8a3f89beb36a465a594f6f4141571
0.485011
2.392874
false
false
false
false
dcliche/mdsynth
rtl/src/timer.vhd
1
5,653
--===========================================================================-- -- -- -- Synthesizable 8 bit Timer -- -- -- --===========================================================================-- -- -- File name : timer.vhd -- -- Entity name : timer -- -- Purpose : 8 bit timer module for System09 -- -- Dependencies : ieee.std_logic_1164 -- ieee.std_logic_unsigned -- -- Uses : None -- -- Author : John E. Kent -- -- Email : [email protected] -- -- Web : http://opencores.org/project,system09 -- -- Registers : -- -- IO address + 0 Read - Down Count register -- Bits[7..0] = Counter Value -- -- IO address + 0 Write - Preset Count register -- Bits[7..0] = Preset Value -- -- IO address + 1 Read - Status register -- Bit[7] = Interrupt Flag -- Bits[6..0] = undefined -- -- IO address + 1 Write - Control register -- Bit[7] = Interrupt Enable -- Bits[6..1] = Unedfined -- Bit[0] = Counter enable -- -- Operation : -- -- Write count to counter register -- Enable counter by setting bit 0 of the control register -- Enable interrupts by setting bit 7 of the control register -- Counter will count down to zero -- When it reaches zero the terminal flag is set -- If the interrupt is enabled an interrupt is generated -- The interrupt may be disabled by writing a 0 to bit 7 -- of the control register or by loading a new down count -- into the counter register. -- -- Copyright (C) 2002 - 2010 John Kent -- -- This program is free software: you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by -- the Free Software Foundation, either version 3 of the License, or -- (at your option) any later version. -- -- This program is distributed in the hope that it will be useful, -- but WITHOUT ANY WARRANTY; without even the implied warranty of -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -- GNU General Public License for more details. -- -- You should have received a copy of the GNU General Public License -- along with this program. If not, see <http://www.gnu.org/licenses/>. -- --===========================================================================-- -- -- -- Revision History -- -- -- --===========================================================================-- -- -- Version Date Author Changes -- -- 0.1 2002-09-06 John Kent Converted to a single timer -- Made synchronous with system clock -- 1.0 2003-09-06 John Kent Changed Clock Edge -- Released to opencores.org -- 2.0 2008-02-05 John Kent Removed Timer inputs and outputs -- Made into a simple 8 bit interrupt down counter -- 2.1 2010-06-17 John Kent Updated header and added GPL -- -- library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity timer is port ( clk : in std_logic; rst : in std_logic; cs : in std_logic; addr : in std_logic; rw : in std_logic; data_in : in std_logic_vector(7 downto 0); data_out : out std_logic_vector(7 downto 0); irq : out std_logic ); end; architecture rtl of timer is signal timer_ctrl : std_logic_vector(7 downto 0); signal timer_stat : std_logic_vector(7 downto 0); signal timer_count : std_logic_vector(7 downto 0); signal timer_term : std_logic; -- Timer terminal count -- -- control/status register bits -- constant BIT_ENB : integer := 0; -- 0=disable, 1=enabled constant BIT_IRQ : integer := 7; -- 0=disabled, 1-enabled begin -------------------------------- -- -- write control registers -- -------------------------------- timer_control : process( clk, rst, cs, rw, addr, data_in, timer_ctrl, timer_term, timer_count ) begin if clk'event and clk = '0' then if rst = '1' then timer_count <= (others=>'0'); timer_ctrl <= (others=>'0'); timer_term <= '0'; elsif cs = '1' and rw = '0' then if addr='0' then timer_count <= data_in; timer_term <= '0'; else timer_ctrl <= data_in; end if; else if (timer_ctrl(BIT_ENB) = '1') then if (timer_count = "00000000" ) then timer_term <= '1'; else timer_count <= timer_count - 1; end if; end if; end if; end if; end process; -- -- timer status register -- timer_status : process( timer_ctrl, timer_term ) begin timer_stat(6 downto 0) <= timer_ctrl(6 downto 0); timer_stat(BIT_IRQ) <= timer_term; end process; -- -- timer data output mux -- timer_data_out : process( addr, timer_count, timer_stat ) begin if addr = '0' then data_out <= timer_count; else data_out <= timer_stat; end if; end process; -- -- read timer strobe to reset interrupts -- timer_interrupt : process( timer_term, timer_ctrl ) begin irq <= timer_term and timer_ctrl(BIT_IRQ); end process; end rtl;
gpl-3.0
abd0fd38e5233ace790449d4262dec6d
0.506103
4.084538
false
false
false
false
grwlf/vsim
vhdl_ct/ct00526.vhd
1
3,112
------------------------------------------------------------------------------- -- -- Copyright (c) 1989 by Intermetrics, Inc. -- All rights reserved. -- ------------------------------------------------------------------------------- -- -- TEST NAME: -- -- CT00526 -- -- AUTHOR: -- -- G. Tominovich -- -- TEST OBJECTIVES: -- -- 10.3 (5) -- -- DESIGN UNIT ORDERING: -- -- PKG00526_1 -- PKG00526_2 -- PKG00526_2/BODY -- ENT00526(ARCH00526) -- ENT00526_Test_Bench(ARCH00526_Test_Bench) -- -- REVISION HISTORY: -- -- 14-AUG-1987 - initial revision -- 28-NOV-1989 - (ESL) remove test where entity name is used as prefix -- -- NOTES: -- -- self-checking -- -- package PKG00526_1 is type A1 is range 1 to 5; type B1 is range 1.0 to 10.0; type CC is (C1, C2, C3) ; end PKG00526_1; package PKG00526_2 is subtype A is CHARACTER range '1' to '5'; constant C : PKG00526_2.A := '4'; -- selected name is also directly visible function Func return boolean ; end PKG00526_2; package body PKG00526_2 is constant CC : A := PKG00526_2.C ; -- selected name is also directly visible function Func return boolean is constant CCC : A := PKG00526_2.C ; begin Lp : for i in True to True loop return (CC = C) and (Func.CCC = C) and (Lp.i) ; end loop Lp ; end Func ; end PKG00526_2 ; entity ENT00526 is end ENT00526 ; use WORK.STANDARD_TYPES.all, WORK.PKG00526_1, WORK.PKG00526_2; architecture ARCH00526 of ENT00526 is constant ArchCons : boolean := True ; use PKG00526_1."=" ; use PKG00526_2."=" ; begin B1 : block constant F : boolean := true ; begin Pcs : process variable B : integer := 5; variable D : PKG00526_1.B1 := 2.3; constant Q : PKG00526_1.CC := PKG00526_1.C2; begin test_report ( "ARCH00526.B1" , "Selected names whose suffix is a package are allowed" , (Pcs.B = 5) and (Pcs.D = 2.3) and (Pcs.Q = PKG00526_1.C2) and (PKG00526_2.Func) and (ARCH00526.ArchCons) ) ; wait ; end process; B2 : block constant F : bit := '1' ; constant G : bit := B1.B2.F; constant H : PKG00526_2.A := PKG00526_2.C; signal S : PKG00526_1.A1 := 3 ; begin process begin test_report ( "ARCH00526.B2" , "Selected names whose suffix is a package are allowed" , (B2.F = '1') and (B1.B2.G = '1') and (B2.H = '4') and (B1.B2.S = 3) ); wait ; end process ; end block B2 ; end block B1 ; end ARCH00526 ; entity ENT00526_Test_Bench is end ENT00526_Test_Bench ; architecture ARCH00526_Test_Bench of ENT00526_Test_Bench is begin L1: block component UUT end component ; for CIS1 : UUT use entity WORK.ENT00526 ( ARCH00526 ) ; begin CIS1 : UUT ; end block L1 ; end ARCH00526_Test_Bench ;
gpl-3.0
e7813bad1d8e2801ef911e5ac0277771
0.518959
3.434879
false
true
false
false
jairov4/accel-oil
impl/impl_test_pcie/simulation/behavioral/system_microblaze_0_wrapper.vhd
1
93,821
------------------------------------------------------------------------------- -- system_microblaze_0_wrapper.vhd ------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; library microblaze_v8_50_c; use microblaze_v8_50_c.all; entity system_microblaze_0_wrapper is port ( CLK : in std_logic; RESET : in std_logic; MB_RESET : in std_logic; INTERRUPT : in std_logic; INTERRUPT_ADDRESS : in std_logic_vector(0 to 31); INTERRUPT_ACK : out std_logic_vector(0 to 1); EXT_BRK : in std_logic; EXT_NM_BRK : in std_logic; DBG_STOP : in std_logic; MB_Halted : out std_logic; MB_Error : out std_logic; WAKEUP : in std_logic_vector(0 to 1); SLEEP : out std_logic; DBG_WAKEUP : out std_logic; LOCKSTEP_MASTER_OUT : out std_logic_vector(0 to 4095); LOCKSTEP_SLAVE_IN : in std_logic_vector(0 to 4095); LOCKSTEP_OUT : out std_logic_vector(0 to 4095); INSTR : in std_logic_vector(0 to 31); IREADY : in std_logic; IWAIT : in std_logic; ICE : in std_logic; IUE : in std_logic; INSTR_ADDR : out std_logic_vector(0 to 31); IFETCH : out std_logic; I_AS : out std_logic; IPLB_M_ABort : out std_logic; IPLB_M_ABus : out std_logic_vector(0 to 31); IPLB_M_UABus : out std_logic_vector(0 to 31); IPLB_M_BE : out std_logic_vector(0 to 7); IPLB_M_busLock : out std_logic; IPLB_M_lockErr : out std_logic; IPLB_M_MSize : out std_logic_vector(0 to 1); IPLB_M_priority : out std_logic_vector(0 to 1); IPLB_M_rdBurst : out std_logic; IPLB_M_request : out std_logic; IPLB_M_RNW : out std_logic; IPLB_M_size : out std_logic_vector(0 to 3); IPLB_M_TAttribute : out std_logic_vector(0 to 15); IPLB_M_type : out std_logic_vector(0 to 2); IPLB_M_wrBurst : out std_logic; IPLB_M_wrDBus : out std_logic_vector(0 to 63); IPLB_MBusy : in std_logic; IPLB_MRdErr : in std_logic; IPLB_MWrErr : in std_logic; IPLB_MIRQ : in std_logic; IPLB_MWrBTerm : in std_logic; IPLB_MWrDAck : in std_logic; IPLB_MAddrAck : in std_logic; IPLB_MRdBTerm : in std_logic; IPLB_MRdDAck : in std_logic; IPLB_MRdDBus : in std_logic_vector(0 to 63); IPLB_MRdWdAddr : in std_logic_vector(0 to 3); IPLB_MRearbitrate : in std_logic; IPLB_MSSize : in std_logic_vector(0 to 1); IPLB_MTimeout : in std_logic; DATA_READ : in std_logic_vector(0 to 31); DREADY : in std_logic; DWAIT : in std_logic; DCE : in std_logic; DUE : in std_logic; DATA_WRITE : out std_logic_vector(0 to 31); DATA_ADDR : out std_logic_vector(0 to 31); D_AS : out std_logic; READ_STROBE : out std_logic; WRITE_STROBE : out std_logic; BYTE_ENABLE : out std_logic_vector(0 to 3); DPLB_M_ABort : out std_logic; DPLB_M_ABus : out std_logic_vector(0 to 31); DPLB_M_UABus : out std_logic_vector(0 to 31); DPLB_M_BE : out std_logic_vector(0 to 7); DPLB_M_busLock : out std_logic; DPLB_M_lockErr : out std_logic; DPLB_M_MSize : out std_logic_vector(0 to 1); DPLB_M_priority : out std_logic_vector(0 to 1); DPLB_M_rdBurst : out std_logic; DPLB_M_request : out std_logic; DPLB_M_RNW : out std_logic; DPLB_M_size : out std_logic_vector(0 to 3); DPLB_M_TAttribute : out std_logic_vector(0 to 15); DPLB_M_type : out std_logic_vector(0 to 2); DPLB_M_wrBurst : out std_logic; DPLB_M_wrDBus : out std_logic_vector(0 to 63); DPLB_MBusy : in std_logic; DPLB_MRdErr : in std_logic; DPLB_MWrErr : in std_logic; DPLB_MIRQ : in std_logic; DPLB_MWrBTerm : in std_logic; DPLB_MWrDAck : in std_logic; DPLB_MAddrAck : in std_logic; DPLB_MRdBTerm : in std_logic; DPLB_MRdDAck : in std_logic; DPLB_MRdDBus : in std_logic_vector(0 to 63); DPLB_MRdWdAddr : in std_logic_vector(0 to 3); DPLB_MRearbitrate : in std_logic; DPLB_MSSize : in std_logic_vector(0 to 1); DPLB_MTimeout : in std_logic; M_AXI_IP_AWID : out std_logic_vector(0 downto 0); M_AXI_IP_AWADDR : out std_logic_vector(31 downto 0); M_AXI_IP_AWLEN : out std_logic_vector(7 downto 0); M_AXI_IP_AWSIZE : out std_logic_vector(2 downto 0); M_AXI_IP_AWBURST : out std_logic_vector(1 downto 0); M_AXI_IP_AWLOCK : out std_logic; M_AXI_IP_AWCACHE : out std_logic_vector(3 downto 0); M_AXI_IP_AWPROT : out std_logic_vector(2 downto 0); M_AXI_IP_AWQOS : out std_logic_vector(3 downto 0); M_AXI_IP_AWVALID : out std_logic; M_AXI_IP_AWREADY : in std_logic; M_AXI_IP_WDATA : out std_logic_vector(31 downto 0); M_AXI_IP_WSTRB : out std_logic_vector(3 downto 0); M_AXI_IP_WLAST : out std_logic; M_AXI_IP_WVALID : out std_logic; M_AXI_IP_WREADY : in std_logic; M_AXI_IP_BID : in std_logic_vector(0 downto 0); M_AXI_IP_BRESP : in std_logic_vector(1 downto 0); M_AXI_IP_BVALID : in std_logic; M_AXI_IP_BREADY : out std_logic; M_AXI_IP_ARID : out std_logic_vector(0 downto 0); M_AXI_IP_ARADDR : out std_logic_vector(31 downto 0); M_AXI_IP_ARLEN : out std_logic_vector(7 downto 0); M_AXI_IP_ARSIZE : out std_logic_vector(2 downto 0); M_AXI_IP_ARBURST : out std_logic_vector(1 downto 0); M_AXI_IP_ARLOCK : out std_logic; M_AXI_IP_ARCACHE : out std_logic_vector(3 downto 0); M_AXI_IP_ARPROT : out std_logic_vector(2 downto 0); M_AXI_IP_ARQOS : out std_logic_vector(3 downto 0); M_AXI_IP_ARVALID : out std_logic; M_AXI_IP_ARREADY : in std_logic; M_AXI_IP_RID : in std_logic_vector(0 downto 0); M_AXI_IP_RDATA : in std_logic_vector(31 downto 0); M_AXI_IP_RRESP : in std_logic_vector(1 downto 0); M_AXI_IP_RLAST : in std_logic; M_AXI_IP_RVALID : in std_logic; M_AXI_IP_RREADY : out std_logic; M_AXI_DP_AWID : out std_logic_vector(0 downto 0); M_AXI_DP_AWADDR : out std_logic_vector(31 downto 0); M_AXI_DP_AWLEN : out std_logic_vector(7 downto 0); M_AXI_DP_AWSIZE : out std_logic_vector(2 downto 0); M_AXI_DP_AWBURST : out std_logic_vector(1 downto 0); M_AXI_DP_AWLOCK : out std_logic; M_AXI_DP_AWCACHE : out std_logic_vector(3 downto 0); M_AXI_DP_AWPROT : out std_logic_vector(2 downto 0); M_AXI_DP_AWQOS : out std_logic_vector(3 downto 0); M_AXI_DP_AWVALID : out std_logic; M_AXI_DP_AWREADY : in std_logic; M_AXI_DP_WDATA : out std_logic_vector(31 downto 0); M_AXI_DP_WSTRB : out std_logic_vector(3 downto 0); M_AXI_DP_WLAST : out std_logic; M_AXI_DP_WVALID : out std_logic; M_AXI_DP_WREADY : in std_logic; M_AXI_DP_BID : in std_logic_vector(0 downto 0); M_AXI_DP_BRESP : in std_logic_vector(1 downto 0); M_AXI_DP_BVALID : in std_logic; M_AXI_DP_BREADY : out std_logic; M_AXI_DP_ARID : out std_logic_vector(0 downto 0); M_AXI_DP_ARADDR : out std_logic_vector(31 downto 0); M_AXI_DP_ARLEN : out std_logic_vector(7 downto 0); M_AXI_DP_ARSIZE : out std_logic_vector(2 downto 0); M_AXI_DP_ARBURST : out std_logic_vector(1 downto 0); M_AXI_DP_ARLOCK : out std_logic; M_AXI_DP_ARCACHE : out std_logic_vector(3 downto 0); M_AXI_DP_ARPROT : out std_logic_vector(2 downto 0); M_AXI_DP_ARQOS : out std_logic_vector(3 downto 0); M_AXI_DP_ARVALID : out std_logic; M_AXI_DP_ARREADY : in std_logic; M_AXI_DP_RID : in std_logic_vector(0 downto 0); M_AXI_DP_RDATA : in std_logic_vector(31 downto 0); M_AXI_DP_RRESP : in std_logic_vector(1 downto 0); M_AXI_DP_RLAST : in std_logic; M_AXI_DP_RVALID : in std_logic; M_AXI_DP_RREADY : out std_logic; M_AXI_IC_AWID : out std_logic_vector(0 downto 0); M_AXI_IC_AWADDR : out std_logic_vector(31 downto 0); M_AXI_IC_AWLEN : out std_logic_vector(7 downto 0); M_AXI_IC_AWSIZE : out std_logic_vector(2 downto 0); M_AXI_IC_AWBURST : out std_logic_vector(1 downto 0); M_AXI_IC_AWLOCK : out std_logic; M_AXI_IC_AWCACHE : out std_logic_vector(3 downto 0); M_AXI_IC_AWPROT : out std_logic_vector(2 downto 0); M_AXI_IC_AWQOS : out std_logic_vector(3 downto 0); M_AXI_IC_AWVALID : out std_logic; M_AXI_IC_AWREADY : in std_logic; M_AXI_IC_AWUSER : out std_logic_vector(4 downto 0); M_AXI_IC_AWDOMAIN : out std_logic_vector(1 downto 0); M_AXI_IC_AWSNOOP : out std_logic_vector(2 downto 0); M_AXI_IC_AWBAR : out std_logic_vector(1 downto 0); M_AXI_IC_WDATA : out std_logic_vector(31 downto 0); M_AXI_IC_WSTRB : out std_logic_vector(3 downto 0); M_AXI_IC_WLAST : out std_logic; M_AXI_IC_WVALID : out std_logic; M_AXI_IC_WREADY : in std_logic; M_AXI_IC_WUSER : out std_logic_vector(0 downto 0); M_AXI_IC_BID : in std_logic_vector(0 downto 0); M_AXI_IC_BRESP : in std_logic_vector(1 downto 0); M_AXI_IC_BVALID : in std_logic; M_AXI_IC_BREADY : out std_logic; M_AXI_IC_BUSER : in std_logic_vector(0 downto 0); M_AXI_IC_WACK : out std_logic; M_AXI_IC_ARID : out std_logic_vector(0 downto 0); M_AXI_IC_ARADDR : out std_logic_vector(31 downto 0); M_AXI_IC_ARLEN : out std_logic_vector(7 downto 0); M_AXI_IC_ARSIZE : out std_logic_vector(2 downto 0); M_AXI_IC_ARBURST : out std_logic_vector(1 downto 0); M_AXI_IC_ARLOCK : out std_logic; M_AXI_IC_ARCACHE : out std_logic_vector(3 downto 0); M_AXI_IC_ARPROT : out std_logic_vector(2 downto 0); M_AXI_IC_ARQOS : out std_logic_vector(3 downto 0); M_AXI_IC_ARVALID : out std_logic; M_AXI_IC_ARREADY : in std_logic; M_AXI_IC_ARUSER : out std_logic_vector(4 downto 0); M_AXI_IC_ARDOMAIN : out std_logic_vector(1 downto 0); M_AXI_IC_ARSNOOP : out std_logic_vector(3 downto 0); M_AXI_IC_ARBAR : out std_logic_vector(1 downto 0); M_AXI_IC_RID : in std_logic_vector(0 downto 0); M_AXI_IC_RDATA : in std_logic_vector(31 downto 0); M_AXI_IC_RRESP : in std_logic_vector(1 downto 0); M_AXI_IC_RLAST : in std_logic; M_AXI_IC_RVALID : in std_logic; M_AXI_IC_RREADY : out std_logic; M_AXI_IC_RUSER : in std_logic_vector(0 downto 0); M_AXI_IC_RACK : out std_logic; M_AXI_IC_ACVALID : in std_logic; M_AXI_IC_ACADDR : in std_logic_vector(31 downto 0); M_AXI_IC_ACSNOOP : in std_logic_vector(3 downto 0); M_AXI_IC_ACPROT : in std_logic_vector(2 downto 0); M_AXI_IC_ACREADY : out std_logic; M_AXI_IC_CRREADY : in std_logic; M_AXI_IC_CRVALID : out std_logic; M_AXI_IC_CRRESP : out std_logic_vector(4 downto 0); M_AXI_IC_CDVALID : out std_logic; M_AXI_IC_CDREADY : in std_logic; M_AXI_IC_CDDATA : out std_logic_vector(31 downto 0); M_AXI_IC_CDLAST : out std_logic; M_AXI_DC_AWID : out std_logic_vector(0 downto 0); M_AXI_DC_AWADDR : out std_logic_vector(31 downto 0); M_AXI_DC_AWLEN : out std_logic_vector(7 downto 0); M_AXI_DC_AWSIZE : out std_logic_vector(2 downto 0); M_AXI_DC_AWBURST : out std_logic_vector(1 downto 0); M_AXI_DC_AWLOCK : out std_logic; M_AXI_DC_AWCACHE : out std_logic_vector(3 downto 0); M_AXI_DC_AWPROT : out std_logic_vector(2 downto 0); M_AXI_DC_AWQOS : out std_logic_vector(3 downto 0); M_AXI_DC_AWVALID : out std_logic; M_AXI_DC_AWREADY : in std_logic; M_AXI_DC_AWUSER : out std_logic_vector(4 downto 0); M_AXI_DC_AWDOMAIN : out std_logic_vector(1 downto 0); M_AXI_DC_AWSNOOP : out std_logic_vector(2 downto 0); M_AXI_DC_AWBAR : out std_logic_vector(1 downto 0); M_AXI_DC_WDATA : out std_logic_vector(31 downto 0); M_AXI_DC_WSTRB : out std_logic_vector(3 downto 0); M_AXI_DC_WLAST : out std_logic; M_AXI_DC_WVALID : out std_logic; M_AXI_DC_WREADY : in std_logic; M_AXI_DC_WUSER : out std_logic_vector(0 downto 0); M_AXI_DC_BID : in std_logic_vector(0 downto 0); M_AXI_DC_BRESP : in std_logic_vector(1 downto 0); M_AXI_DC_BVALID : in std_logic; M_AXI_DC_BREADY : out std_logic; M_AXI_DC_BUSER : in std_logic_vector(0 downto 0); M_AXI_DC_WACK : out std_logic; M_AXI_DC_ARID : out std_logic_vector(0 downto 0); M_AXI_DC_ARADDR : out std_logic_vector(31 downto 0); M_AXI_DC_ARLEN : out std_logic_vector(7 downto 0); M_AXI_DC_ARSIZE : out std_logic_vector(2 downto 0); M_AXI_DC_ARBURST : out std_logic_vector(1 downto 0); M_AXI_DC_ARLOCK : out std_logic; M_AXI_DC_ARCACHE : out std_logic_vector(3 downto 0); M_AXI_DC_ARPROT : out std_logic_vector(2 downto 0); M_AXI_DC_ARQOS : out std_logic_vector(3 downto 0); M_AXI_DC_ARVALID : out std_logic; M_AXI_DC_ARREADY : in std_logic; M_AXI_DC_ARUSER : out std_logic_vector(4 downto 0); M_AXI_DC_ARDOMAIN : out std_logic_vector(1 downto 0); M_AXI_DC_ARSNOOP : out std_logic_vector(3 downto 0); M_AXI_DC_ARBAR : out std_logic_vector(1 downto 0); M_AXI_DC_RID : in std_logic_vector(0 downto 0); M_AXI_DC_RDATA : in std_logic_vector(31 downto 0); M_AXI_DC_RRESP : in std_logic_vector(1 downto 0); M_AXI_DC_RLAST : in std_logic; M_AXI_DC_RVALID : in std_logic; M_AXI_DC_RREADY : out std_logic; M_AXI_DC_RUSER : in std_logic_vector(0 downto 0); M_AXI_DC_RACK : out std_logic; M_AXI_DC_ACVALID : in std_logic; M_AXI_DC_ACADDR : in std_logic_vector(31 downto 0); M_AXI_DC_ACSNOOP : in std_logic_vector(3 downto 0); M_AXI_DC_ACPROT : in std_logic_vector(2 downto 0); M_AXI_DC_ACREADY : out std_logic; M_AXI_DC_CRREADY : in std_logic; M_AXI_DC_CRVALID : out std_logic; M_AXI_DC_CRRESP : out std_logic_vector(4 downto 0); M_AXI_DC_CDVALID : out std_logic; M_AXI_DC_CDREADY : in std_logic; M_AXI_DC_CDDATA : out std_logic_vector(31 downto 0); M_AXI_DC_CDLAST : out std_logic; DBG_CLK : in std_logic; DBG_TDI : in std_logic; DBG_TDO : out std_logic; DBG_REG_EN : in std_logic_vector(0 to 7); DBG_SHIFT : in std_logic; DBG_CAPTURE : in std_logic; DBG_UPDATE : in std_logic; DEBUG_RST : in std_logic; Trace_Instruction : out std_logic_vector(0 to 31); Trace_Valid_Instr : out std_logic; Trace_PC : out std_logic_vector(0 to 31); Trace_Reg_Write : out std_logic; Trace_Reg_Addr : out std_logic_vector(0 to 4); Trace_MSR_Reg : out std_logic_vector(0 to 14); Trace_PID_Reg : out std_logic_vector(0 to 7); Trace_New_Reg_Value : out std_logic_vector(0 to 31); Trace_Exception_Taken : out std_logic; Trace_Exception_Kind : out std_logic_vector(0 to 4); Trace_Jump_Taken : out std_logic; Trace_Delay_Slot : out std_logic; Trace_Data_Address : out std_logic_vector(0 to 31); Trace_Data_Access : out std_logic; Trace_Data_Read : out std_logic; Trace_Data_Write : out std_logic; Trace_Data_Write_Value : out std_logic_vector(0 to 31); Trace_Data_Byte_Enable : out std_logic_vector(0 to 3); Trace_DCache_Req : out std_logic; Trace_DCache_Hit : out std_logic; Trace_DCache_Rdy : out std_logic; Trace_DCache_Read : out std_logic; Trace_ICache_Req : out std_logic; Trace_ICache_Hit : out std_logic; Trace_ICache_Rdy : out std_logic; Trace_OF_PipeRun : out std_logic; Trace_EX_PipeRun : out std_logic; Trace_MEM_PipeRun : out std_logic; Trace_MB_Halted : out std_logic; Trace_Jump_Hit : out std_logic; FSL0_S_CLK : out std_logic; FSL0_S_READ : out std_logic; FSL0_S_DATA : in std_logic_vector(0 to 31); FSL0_S_CONTROL : in std_logic; FSL0_S_EXISTS : in std_logic; FSL0_M_CLK : out std_logic; FSL0_M_WRITE : out std_logic; FSL0_M_DATA : out std_logic_vector(0 to 31); FSL0_M_CONTROL : out std_logic; FSL0_M_FULL : in std_logic; FSL1_S_CLK : out std_logic; FSL1_S_READ : out std_logic; FSL1_S_DATA : in std_logic_vector(0 to 31); FSL1_S_CONTROL : in std_logic; FSL1_S_EXISTS : in std_logic; FSL1_M_CLK : out std_logic; FSL1_M_WRITE : out std_logic; FSL1_M_DATA : out std_logic_vector(0 to 31); FSL1_M_CONTROL : out std_logic; FSL1_M_FULL : in std_logic; FSL2_S_CLK : out std_logic; FSL2_S_READ : out std_logic; FSL2_S_DATA : in std_logic_vector(0 to 31); FSL2_S_CONTROL : in std_logic; FSL2_S_EXISTS : in std_logic; FSL2_M_CLK : out std_logic; FSL2_M_WRITE : out std_logic; FSL2_M_DATA : out std_logic_vector(0 to 31); FSL2_M_CONTROL : out std_logic; FSL2_M_FULL : in std_logic; FSL3_S_CLK : out std_logic; FSL3_S_READ : out std_logic; FSL3_S_DATA : in std_logic_vector(0 to 31); FSL3_S_CONTROL : in std_logic; FSL3_S_EXISTS : in std_logic; FSL3_M_CLK : out std_logic; FSL3_M_WRITE : out std_logic; FSL3_M_DATA : out std_logic_vector(0 to 31); FSL3_M_CONTROL : out std_logic; FSL3_M_FULL : in std_logic; FSL4_S_CLK : out std_logic; FSL4_S_READ : out std_logic; FSL4_S_DATA : in std_logic_vector(0 to 31); FSL4_S_CONTROL : in std_logic; FSL4_S_EXISTS : in std_logic; FSL4_M_CLK : out std_logic; FSL4_M_WRITE : out std_logic; FSL4_M_DATA : out std_logic_vector(0 to 31); FSL4_M_CONTROL : out std_logic; FSL4_M_FULL : in std_logic; FSL5_S_CLK : out std_logic; FSL5_S_READ : out std_logic; FSL5_S_DATA : in std_logic_vector(0 to 31); FSL5_S_CONTROL : in std_logic; FSL5_S_EXISTS : in std_logic; FSL5_M_CLK : out std_logic; FSL5_M_WRITE : out std_logic; FSL5_M_DATA : out std_logic_vector(0 to 31); FSL5_M_CONTROL : out std_logic; FSL5_M_FULL : in std_logic; FSL6_S_CLK : out std_logic; FSL6_S_READ : out std_logic; FSL6_S_DATA : in std_logic_vector(0 to 31); FSL6_S_CONTROL : in std_logic; FSL6_S_EXISTS : in std_logic; FSL6_M_CLK : out std_logic; FSL6_M_WRITE : out std_logic; FSL6_M_DATA : out std_logic_vector(0 to 31); FSL6_M_CONTROL : out std_logic; FSL6_M_FULL : in std_logic; FSL7_S_CLK : out std_logic; FSL7_S_READ : out std_logic; FSL7_S_DATA : in std_logic_vector(0 to 31); FSL7_S_CONTROL : in std_logic; FSL7_S_EXISTS : in std_logic; FSL7_M_CLK : out std_logic; FSL7_M_WRITE : out std_logic; FSL7_M_DATA : out std_logic_vector(0 to 31); FSL7_M_CONTROL : out std_logic; FSL7_M_FULL : in std_logic; FSL8_S_CLK : out std_logic; FSL8_S_READ : out std_logic; FSL8_S_DATA : in std_logic_vector(0 to 31); FSL8_S_CONTROL : in std_logic; FSL8_S_EXISTS : in std_logic; FSL8_M_CLK : out std_logic; FSL8_M_WRITE : out std_logic; FSL8_M_DATA : out std_logic_vector(0 to 31); FSL8_M_CONTROL : out std_logic; FSL8_M_FULL : in std_logic; FSL9_S_CLK : out std_logic; FSL9_S_READ : out std_logic; FSL9_S_DATA : in std_logic_vector(0 to 31); FSL9_S_CONTROL : in std_logic; FSL9_S_EXISTS : in std_logic; FSL9_M_CLK : out std_logic; FSL9_M_WRITE : out std_logic; FSL9_M_DATA : out std_logic_vector(0 to 31); FSL9_M_CONTROL : out std_logic; FSL9_M_FULL : in std_logic; FSL10_S_CLK : out std_logic; FSL10_S_READ : out std_logic; FSL10_S_DATA : in std_logic_vector(0 to 31); FSL10_S_CONTROL : in std_logic; FSL10_S_EXISTS : in std_logic; FSL10_M_CLK : out std_logic; FSL10_M_WRITE : out std_logic; FSL10_M_DATA : out std_logic_vector(0 to 31); FSL10_M_CONTROL : out std_logic; FSL10_M_FULL : in std_logic; FSL11_S_CLK : out std_logic; FSL11_S_READ : out std_logic; FSL11_S_DATA : in std_logic_vector(0 to 31); FSL11_S_CONTROL : in std_logic; FSL11_S_EXISTS : in std_logic; FSL11_M_CLK : out std_logic; FSL11_M_WRITE : out std_logic; FSL11_M_DATA : out std_logic_vector(0 to 31); FSL11_M_CONTROL : out std_logic; FSL11_M_FULL : in std_logic; FSL12_S_CLK : out std_logic; FSL12_S_READ : out std_logic; FSL12_S_DATA : in std_logic_vector(0 to 31); FSL12_S_CONTROL : in std_logic; FSL12_S_EXISTS : in std_logic; FSL12_M_CLK : out std_logic; FSL12_M_WRITE : out std_logic; FSL12_M_DATA : out std_logic_vector(0 to 31); FSL12_M_CONTROL : out std_logic; FSL12_M_FULL : in std_logic; FSL13_S_CLK : out std_logic; FSL13_S_READ : out std_logic; FSL13_S_DATA : in std_logic_vector(0 to 31); FSL13_S_CONTROL : in std_logic; FSL13_S_EXISTS : in std_logic; FSL13_M_CLK : out std_logic; FSL13_M_WRITE : out std_logic; FSL13_M_DATA : out std_logic_vector(0 to 31); FSL13_M_CONTROL : out std_logic; FSL13_M_FULL : in std_logic; FSL14_S_CLK : out std_logic; FSL14_S_READ : out std_logic; FSL14_S_DATA : in std_logic_vector(0 to 31); FSL14_S_CONTROL : in std_logic; FSL14_S_EXISTS : in std_logic; FSL14_M_CLK : out std_logic; FSL14_M_WRITE : out std_logic; FSL14_M_DATA : out std_logic_vector(0 to 31); FSL14_M_CONTROL : out std_logic; FSL14_M_FULL : in std_logic; FSL15_S_CLK : out std_logic; FSL15_S_READ : out std_logic; FSL15_S_DATA : in std_logic_vector(0 to 31); FSL15_S_CONTROL : in std_logic; FSL15_S_EXISTS : in std_logic; FSL15_M_CLK : out std_logic; FSL15_M_WRITE : out std_logic; FSL15_M_DATA : out std_logic_vector(0 to 31); FSL15_M_CONTROL : out std_logic; FSL15_M_FULL : in std_logic; M0_AXIS_TLAST : out std_logic; M0_AXIS_TDATA : out std_logic_vector(31 downto 0); M0_AXIS_TVALID : out std_logic; M0_AXIS_TREADY : in std_logic; S0_AXIS_TLAST : in std_logic; S0_AXIS_TDATA : in std_logic_vector(31 downto 0); S0_AXIS_TVALID : in std_logic; S0_AXIS_TREADY : out std_logic; M1_AXIS_TLAST : out std_logic; M1_AXIS_TDATA : out std_logic_vector(31 downto 0); M1_AXIS_TVALID : out std_logic; M1_AXIS_TREADY : in std_logic; S1_AXIS_TLAST : in std_logic; S1_AXIS_TDATA : in std_logic_vector(31 downto 0); S1_AXIS_TVALID : in std_logic; S1_AXIS_TREADY : out std_logic; M2_AXIS_TLAST : out std_logic; M2_AXIS_TDATA : out std_logic_vector(31 downto 0); M2_AXIS_TVALID : out std_logic; M2_AXIS_TREADY : in std_logic; S2_AXIS_TLAST : in std_logic; S2_AXIS_TDATA : in std_logic_vector(31 downto 0); S2_AXIS_TVALID : in std_logic; S2_AXIS_TREADY : out std_logic; M3_AXIS_TLAST : out std_logic; M3_AXIS_TDATA : out std_logic_vector(31 downto 0); M3_AXIS_TVALID : out std_logic; M3_AXIS_TREADY : in std_logic; S3_AXIS_TLAST : in std_logic; S3_AXIS_TDATA : in std_logic_vector(31 downto 0); S3_AXIS_TVALID : in std_logic; S3_AXIS_TREADY : out std_logic; M4_AXIS_TLAST : out std_logic; M4_AXIS_TDATA : out std_logic_vector(31 downto 0); M4_AXIS_TVALID : out std_logic; M4_AXIS_TREADY : in std_logic; S4_AXIS_TLAST : in std_logic; S4_AXIS_TDATA : in std_logic_vector(31 downto 0); S4_AXIS_TVALID : in std_logic; S4_AXIS_TREADY : out std_logic; M5_AXIS_TLAST : out std_logic; M5_AXIS_TDATA : out std_logic_vector(31 downto 0); M5_AXIS_TVALID : out std_logic; M5_AXIS_TREADY : in std_logic; S5_AXIS_TLAST : in std_logic; S5_AXIS_TDATA : in std_logic_vector(31 downto 0); S5_AXIS_TVALID : in std_logic; S5_AXIS_TREADY : out std_logic; M6_AXIS_TLAST : out std_logic; M6_AXIS_TDATA : out std_logic_vector(31 downto 0); M6_AXIS_TVALID : out std_logic; M6_AXIS_TREADY : in std_logic; S6_AXIS_TLAST : in std_logic; S6_AXIS_TDATA : in std_logic_vector(31 downto 0); S6_AXIS_TVALID : in std_logic; S6_AXIS_TREADY : out std_logic; M7_AXIS_TLAST : out std_logic; M7_AXIS_TDATA : out std_logic_vector(31 downto 0); M7_AXIS_TVALID : out std_logic; M7_AXIS_TREADY : in std_logic; S7_AXIS_TLAST : in std_logic; S7_AXIS_TDATA : in std_logic_vector(31 downto 0); S7_AXIS_TVALID : in std_logic; S7_AXIS_TREADY : out std_logic; M8_AXIS_TLAST : out std_logic; M8_AXIS_TDATA : out std_logic_vector(31 downto 0); M8_AXIS_TVALID : out std_logic; M8_AXIS_TREADY : in std_logic; S8_AXIS_TLAST : in std_logic; S8_AXIS_TDATA : in std_logic_vector(31 downto 0); S8_AXIS_TVALID : in std_logic; S8_AXIS_TREADY : out std_logic; M9_AXIS_TLAST : out std_logic; M9_AXIS_TDATA : out std_logic_vector(31 downto 0); M9_AXIS_TVALID : out std_logic; M9_AXIS_TREADY : in std_logic; S9_AXIS_TLAST : in std_logic; S9_AXIS_TDATA : in std_logic_vector(31 downto 0); S9_AXIS_TVALID : in std_logic; S9_AXIS_TREADY : out std_logic; M10_AXIS_TLAST : out std_logic; M10_AXIS_TDATA : out std_logic_vector(31 downto 0); M10_AXIS_TVALID : out std_logic; M10_AXIS_TREADY : in std_logic; S10_AXIS_TLAST : in std_logic; S10_AXIS_TDATA : in std_logic_vector(31 downto 0); S10_AXIS_TVALID : in std_logic; S10_AXIS_TREADY : out std_logic; M11_AXIS_TLAST : out std_logic; M11_AXIS_TDATA : out std_logic_vector(31 downto 0); M11_AXIS_TVALID : out std_logic; M11_AXIS_TREADY : in std_logic; S11_AXIS_TLAST : in std_logic; S11_AXIS_TDATA : in std_logic_vector(31 downto 0); S11_AXIS_TVALID : in std_logic; S11_AXIS_TREADY : out std_logic; M12_AXIS_TLAST : out std_logic; M12_AXIS_TDATA : out std_logic_vector(31 downto 0); M12_AXIS_TVALID : out std_logic; M12_AXIS_TREADY : in std_logic; S12_AXIS_TLAST : in std_logic; S12_AXIS_TDATA : in std_logic_vector(31 downto 0); S12_AXIS_TVALID : in std_logic; S12_AXIS_TREADY : out std_logic; M13_AXIS_TLAST : out std_logic; M13_AXIS_TDATA : out std_logic_vector(31 downto 0); M13_AXIS_TVALID : out std_logic; M13_AXIS_TREADY : in std_logic; S13_AXIS_TLAST : in std_logic; S13_AXIS_TDATA : in std_logic_vector(31 downto 0); S13_AXIS_TVALID : in std_logic; S13_AXIS_TREADY : out std_logic; M14_AXIS_TLAST : out std_logic; M14_AXIS_TDATA : out std_logic_vector(31 downto 0); M14_AXIS_TVALID : out std_logic; M14_AXIS_TREADY : in std_logic; S14_AXIS_TLAST : in std_logic; S14_AXIS_TDATA : in std_logic_vector(31 downto 0); S14_AXIS_TVALID : in std_logic; S14_AXIS_TREADY : out std_logic; M15_AXIS_TLAST : out std_logic; M15_AXIS_TDATA : out std_logic_vector(31 downto 0); M15_AXIS_TVALID : out std_logic; M15_AXIS_TREADY : in std_logic; S15_AXIS_TLAST : in std_logic; S15_AXIS_TDATA : in std_logic_vector(31 downto 0); S15_AXIS_TVALID : in std_logic; S15_AXIS_TREADY : out std_logic; ICACHE_FSL_IN_CLK : out std_logic; ICACHE_FSL_IN_READ : out std_logic; ICACHE_FSL_IN_DATA : in std_logic_vector(0 to 31); ICACHE_FSL_IN_CONTROL : in std_logic; ICACHE_FSL_IN_EXISTS : in std_logic; ICACHE_FSL_OUT_CLK : out std_logic; ICACHE_FSL_OUT_WRITE : out std_logic; ICACHE_FSL_OUT_DATA : out std_logic_vector(0 to 31); ICACHE_FSL_OUT_CONTROL : out std_logic; ICACHE_FSL_OUT_FULL : in std_logic; DCACHE_FSL_IN_CLK : out std_logic; DCACHE_FSL_IN_READ : out std_logic; DCACHE_FSL_IN_DATA : in std_logic_vector(0 to 31); DCACHE_FSL_IN_CONTROL : in std_logic; DCACHE_FSL_IN_EXISTS : in std_logic; DCACHE_FSL_OUT_CLK : out std_logic; DCACHE_FSL_OUT_WRITE : out std_logic; DCACHE_FSL_OUT_DATA : out std_logic_vector(0 to 31); DCACHE_FSL_OUT_CONTROL : out std_logic; DCACHE_FSL_OUT_FULL : in std_logic ); end system_microblaze_0_wrapper; architecture STRUCTURE of system_microblaze_0_wrapper is component microblaze is generic ( C_SCO : integer; C_FREQ : integer; C_DATA_SIZE : integer; C_DYNAMIC_BUS_SIZING : integer; C_FAMILY : string; C_INSTANCE : string; C_AVOID_PRIMITIVES : integer; C_FAULT_TOLERANT : integer; C_ECC_USE_CE_EXCEPTION : integer; C_LOCKSTEP_SLAVE : integer; C_ENDIANNESS : integer; C_AREA_OPTIMIZED : integer; C_OPTIMIZATION : integer; C_INTERCONNECT : integer; C_STREAM_INTERCONNECT : integer; C_BASE_VECTORS : std_logic_vector; C_DPLB_DWIDTH : integer; C_DPLB_NATIVE_DWIDTH : integer; C_DPLB_BURST_EN : integer; C_DPLB_P2P : integer; C_IPLB_DWIDTH : integer; C_IPLB_NATIVE_DWIDTH : integer; C_IPLB_BURST_EN : integer; C_IPLB_P2P : integer; C_M_AXI_DP_THREAD_ID_WIDTH : integer; C_M_AXI_DP_DATA_WIDTH : integer; C_M_AXI_DP_ADDR_WIDTH : integer; C_M_AXI_DP_EXCLUSIVE_ACCESS : integer; C_M_AXI_IP_THREAD_ID_WIDTH : integer; C_M_AXI_IP_DATA_WIDTH : integer; C_M_AXI_IP_ADDR_WIDTH : integer; C_D_AXI : integer; C_D_PLB : integer; C_D_LMB : integer; C_I_AXI : integer; C_I_PLB : integer; C_I_LMB : integer; C_USE_MSR_INSTR : integer; C_USE_PCMP_INSTR : integer; C_USE_BARREL : integer; C_USE_DIV : integer; C_USE_HW_MUL : integer; C_USE_FPU : integer; C_USE_REORDER_INSTR : integer; C_UNALIGNED_EXCEPTIONS : integer; C_ILL_OPCODE_EXCEPTION : integer; C_M_AXI_I_BUS_EXCEPTION : integer; C_M_AXI_D_BUS_EXCEPTION : integer; C_IPLB_BUS_EXCEPTION : integer; C_DPLB_BUS_EXCEPTION : integer; C_DIV_ZERO_EXCEPTION : integer; C_FPU_EXCEPTION : integer; C_FSL_EXCEPTION : integer; C_USE_STACK_PROTECTION : integer; C_PVR : integer; C_PVR_USER1 : std_logic_vector(0 to 7); C_PVR_USER2 : std_logic_vector(0 to 31); C_DEBUG_ENABLED : integer; C_NUMBER_OF_PC_BRK : integer; C_NUMBER_OF_RD_ADDR_BRK : integer; C_NUMBER_OF_WR_ADDR_BRK : integer; C_INTERRUPT_IS_EDGE : integer; C_EDGE_IS_POSITIVE : integer; C_RESET_MSR : std_logic_vector; C_OPCODE_0x0_ILLEGAL : integer; C_FSL_LINKS : integer; C_FSL_DATA_SIZE : integer; C_USE_EXTENDED_FSL_INSTR : integer; C_M0_AXIS_DATA_WIDTH : integer; C_S0_AXIS_DATA_WIDTH : integer; C_M1_AXIS_DATA_WIDTH : integer; C_S1_AXIS_DATA_WIDTH : integer; C_M2_AXIS_DATA_WIDTH : integer; C_S2_AXIS_DATA_WIDTH : integer; C_M3_AXIS_DATA_WIDTH : integer; C_S3_AXIS_DATA_WIDTH : integer; C_M4_AXIS_DATA_WIDTH : integer; C_S4_AXIS_DATA_WIDTH : integer; C_M5_AXIS_DATA_WIDTH : integer; C_S5_AXIS_DATA_WIDTH : integer; C_M6_AXIS_DATA_WIDTH : integer; C_S6_AXIS_DATA_WIDTH : integer; C_M7_AXIS_DATA_WIDTH : integer; C_S7_AXIS_DATA_WIDTH : integer; C_M8_AXIS_DATA_WIDTH : integer; C_S8_AXIS_DATA_WIDTH : integer; C_M9_AXIS_DATA_WIDTH : integer; C_S9_AXIS_DATA_WIDTH : integer; C_M10_AXIS_DATA_WIDTH : integer; C_S10_AXIS_DATA_WIDTH : integer; C_M11_AXIS_DATA_WIDTH : integer; C_S11_AXIS_DATA_WIDTH : integer; C_M12_AXIS_DATA_WIDTH : integer; C_S12_AXIS_DATA_WIDTH : integer; C_M13_AXIS_DATA_WIDTH : integer; C_S13_AXIS_DATA_WIDTH : integer; C_M14_AXIS_DATA_WIDTH : integer; C_S14_AXIS_DATA_WIDTH : integer; C_M15_AXIS_DATA_WIDTH : integer; C_S15_AXIS_DATA_WIDTH : integer; C_ICACHE_BASEADDR : std_logic_vector; C_ICACHE_HIGHADDR : std_logic_vector; C_USE_ICACHE : integer; C_ALLOW_ICACHE_WR : integer; C_ADDR_TAG_BITS : integer; C_CACHE_BYTE_SIZE : integer; C_ICACHE_USE_FSL : integer; C_ICACHE_LINE_LEN : integer; C_ICACHE_ALWAYS_USED : integer; C_ICACHE_INTERFACE : integer; C_ICACHE_VICTIMS : integer; C_ICACHE_STREAMS : integer; C_ICACHE_FORCE_TAG_LUTRAM : integer; C_ICACHE_DATA_WIDTH : integer; C_M_AXI_IC_THREAD_ID_WIDTH : integer; C_M_AXI_IC_DATA_WIDTH : integer; C_M_AXI_IC_ADDR_WIDTH : integer; C_M_AXI_IC_USER_VALUE : integer; C_M_AXI_IC_AWUSER_WIDTH : integer; C_M_AXI_IC_ARUSER_WIDTH : integer; C_M_AXI_IC_WUSER_WIDTH : integer; C_M_AXI_IC_RUSER_WIDTH : integer; C_M_AXI_IC_BUSER_WIDTH : integer; C_DCACHE_BASEADDR : std_logic_vector; C_DCACHE_HIGHADDR : std_logic_vector; C_USE_DCACHE : integer; C_ALLOW_DCACHE_WR : integer; C_DCACHE_ADDR_TAG : integer; C_DCACHE_BYTE_SIZE : integer; C_DCACHE_USE_FSL : integer; C_DCACHE_LINE_LEN : integer; C_DCACHE_ALWAYS_USED : integer; C_DCACHE_INTERFACE : integer; C_DCACHE_USE_WRITEBACK : integer; C_DCACHE_VICTIMS : integer; C_DCACHE_FORCE_TAG_LUTRAM : integer; C_DCACHE_DATA_WIDTH : integer; C_M_AXI_DC_THREAD_ID_WIDTH : integer; C_M_AXI_DC_DATA_WIDTH : integer; C_M_AXI_DC_ADDR_WIDTH : integer; C_M_AXI_DC_EXCLUSIVE_ACCESS : integer; C_M_AXI_DC_USER_VALUE : integer; C_M_AXI_DC_AWUSER_WIDTH : integer; C_M_AXI_DC_ARUSER_WIDTH : integer; C_M_AXI_DC_WUSER_WIDTH : integer; C_M_AXI_DC_RUSER_WIDTH : integer; C_M_AXI_DC_BUSER_WIDTH : integer; C_USE_MMU : integer; C_MMU_DTLB_SIZE : integer; C_MMU_ITLB_SIZE : integer; C_MMU_TLB_ACCESS : integer; C_MMU_ZONES : integer; C_MMU_PRIVILEGED_INSTR : integer; C_USE_INTERRUPT : integer; C_USE_EXT_BRK : integer; C_USE_EXT_NM_BRK : integer; C_USE_BRANCH_TARGET_CACHE : integer; C_BRANCH_TARGET_CACHE_SIZE : integer; C_PC_WIDTH : integer ); port ( CLK : in std_logic; RESET : in std_logic; MB_RESET : in std_logic; INTERRUPT : in std_logic; INTERRUPT_ADDRESS : in std_logic_vector(0 to 31); INTERRUPT_ACK : out std_logic_vector(0 to 1); EXT_BRK : in std_logic; EXT_NM_BRK : in std_logic; DBG_STOP : in std_logic; MB_Halted : out std_logic; MB_Error : out std_logic; WAKEUP : in std_logic_vector(0 to 1); SLEEP : out std_logic; DBG_WAKEUP : out std_logic; LOCKSTEP_MASTER_OUT : out std_logic_vector(0 to 4095); LOCKSTEP_SLAVE_IN : in std_logic_vector(0 to 4095); LOCKSTEP_OUT : out std_logic_vector(0 to 4095); INSTR : in std_logic_vector(0 to 31); IREADY : in std_logic; IWAIT : in std_logic; ICE : in std_logic; IUE : in std_logic; INSTR_ADDR : out std_logic_vector(0 to 31); IFETCH : out std_logic; I_AS : out std_logic; IPLB_M_ABort : out std_logic; IPLB_M_ABus : out std_logic_vector(0 to 31); IPLB_M_UABus : out std_logic_vector(0 to 31); IPLB_M_BE : out std_logic_vector(0 to (C_IPLB_DWIDTH-1)/8); IPLB_M_busLock : out std_logic; IPLB_M_lockErr : out std_logic; IPLB_M_MSize : out std_logic_vector(0 to 1); IPLB_M_priority : out std_logic_vector(0 to 1); IPLB_M_rdBurst : out std_logic; IPLB_M_request : out std_logic; IPLB_M_RNW : out std_logic; IPLB_M_size : out std_logic_vector(0 to 3); IPLB_M_TAttribute : out std_logic_vector(0 to 15); IPLB_M_type : out std_logic_vector(0 to 2); IPLB_M_wrBurst : out std_logic; IPLB_M_wrDBus : out std_logic_vector(0 to C_IPLB_DWIDTH-1); IPLB_MBusy : in std_logic; IPLB_MRdErr : in std_logic; IPLB_MWrErr : in std_logic; IPLB_MIRQ : in std_logic; IPLB_MWrBTerm : in std_logic; IPLB_MWrDAck : in std_logic; IPLB_MAddrAck : in std_logic; IPLB_MRdBTerm : in std_logic; IPLB_MRdDAck : in std_logic; IPLB_MRdDBus : in std_logic_vector(0 to C_IPLB_DWIDTH-1); IPLB_MRdWdAddr : in std_logic_vector(0 to 3); IPLB_MRearbitrate : in std_logic; IPLB_MSSize : in std_logic_vector(0 to 1); IPLB_MTimeout : in std_logic; DATA_READ : in std_logic_vector(0 to 31); DREADY : in std_logic; DWAIT : in std_logic; DCE : in std_logic; DUE : in std_logic; DATA_WRITE : out std_logic_vector(0 to 31); DATA_ADDR : out std_logic_vector(0 to 31); D_AS : out std_logic; READ_STROBE : out std_logic; WRITE_STROBE : out std_logic; BYTE_ENABLE : out std_logic_vector(0 to 3); DPLB_M_ABort : out std_logic; DPLB_M_ABus : out std_logic_vector(0 to 31); DPLB_M_UABus : out std_logic_vector(0 to 31); DPLB_M_BE : out std_logic_vector(0 to (C_DPLB_DWIDTH-1)/8); DPLB_M_busLock : out std_logic; DPLB_M_lockErr : out std_logic; DPLB_M_MSize : out std_logic_vector(0 to 1); DPLB_M_priority : out std_logic_vector(0 to 1); DPLB_M_rdBurst : out std_logic; DPLB_M_request : out std_logic; DPLB_M_RNW : out std_logic; DPLB_M_size : out std_logic_vector(0 to 3); DPLB_M_TAttribute : out std_logic_vector(0 to 15); DPLB_M_type : out std_logic_vector(0 to 2); DPLB_M_wrBurst : out std_logic; DPLB_M_wrDBus : out std_logic_vector(0 to C_DPLB_DWIDTH-1); DPLB_MBusy : in std_logic; DPLB_MRdErr : in std_logic; DPLB_MWrErr : in std_logic; DPLB_MIRQ : in std_logic; DPLB_MWrBTerm : in std_logic; DPLB_MWrDAck : in std_logic; DPLB_MAddrAck : in std_logic; DPLB_MRdBTerm : in std_logic; DPLB_MRdDAck : in std_logic; DPLB_MRdDBus : in std_logic_vector(0 to C_DPLB_DWIDTH-1); DPLB_MRdWdAddr : in std_logic_vector(0 to 3); DPLB_MRearbitrate : in std_logic; DPLB_MSSize : in std_logic_vector(0 to 1); DPLB_MTimeout : in std_logic; M_AXI_IP_AWID : out std_logic_vector((C_M_AXI_IP_THREAD_ID_WIDTH-1) downto 0); M_AXI_IP_AWADDR : out std_logic_vector((C_M_AXI_IP_ADDR_WIDTH-1) downto 0); M_AXI_IP_AWLEN : out std_logic_vector(7 downto 0); M_AXI_IP_AWSIZE : out std_logic_vector(2 downto 0); M_AXI_IP_AWBURST : out std_logic_vector(1 downto 0); M_AXI_IP_AWLOCK : out std_logic; M_AXI_IP_AWCACHE : out std_logic_vector(3 downto 0); M_AXI_IP_AWPROT : out std_logic_vector(2 downto 0); M_AXI_IP_AWQOS : out std_logic_vector(3 downto 0); M_AXI_IP_AWVALID : out std_logic; M_AXI_IP_AWREADY : in std_logic; M_AXI_IP_WDATA : out std_logic_vector((C_M_AXI_IP_DATA_WIDTH-1) downto 0); M_AXI_IP_WSTRB : out std_logic_vector(((C_M_AXI_IP_DATA_WIDTH/8)-1) downto 0); M_AXI_IP_WLAST : out std_logic; M_AXI_IP_WVALID : out std_logic; M_AXI_IP_WREADY : in std_logic; M_AXI_IP_BID : in std_logic_vector((C_M_AXI_IP_THREAD_ID_WIDTH-1) downto 0); M_AXI_IP_BRESP : in std_logic_vector(1 downto 0); M_AXI_IP_BVALID : in std_logic; M_AXI_IP_BREADY : out std_logic; M_AXI_IP_ARID : out std_logic_vector((C_M_AXI_IP_THREAD_ID_WIDTH-1) downto 0); M_AXI_IP_ARADDR : out std_logic_vector((C_M_AXI_IP_ADDR_WIDTH-1) downto 0); M_AXI_IP_ARLEN : out std_logic_vector(7 downto 0); M_AXI_IP_ARSIZE : out std_logic_vector(2 downto 0); M_AXI_IP_ARBURST : out std_logic_vector(1 downto 0); M_AXI_IP_ARLOCK : out std_logic; M_AXI_IP_ARCACHE : out std_logic_vector(3 downto 0); M_AXI_IP_ARPROT : out std_logic_vector(2 downto 0); M_AXI_IP_ARQOS : out std_logic_vector(3 downto 0); M_AXI_IP_ARVALID : out std_logic; M_AXI_IP_ARREADY : in std_logic; M_AXI_IP_RID : in std_logic_vector((C_M_AXI_IP_THREAD_ID_WIDTH-1) downto 0); M_AXI_IP_RDATA : in std_logic_vector((C_M_AXI_IP_DATA_WIDTH-1) downto 0); M_AXI_IP_RRESP : in std_logic_vector(1 downto 0); M_AXI_IP_RLAST : in std_logic; M_AXI_IP_RVALID : in std_logic; M_AXI_IP_RREADY : out std_logic; M_AXI_DP_AWID : out std_logic_vector((C_M_AXI_DP_THREAD_ID_WIDTH-1) downto 0); M_AXI_DP_AWADDR : out std_logic_vector((C_M_AXI_DP_ADDR_WIDTH-1) downto 0); M_AXI_DP_AWLEN : out std_logic_vector(7 downto 0); M_AXI_DP_AWSIZE : out std_logic_vector(2 downto 0); M_AXI_DP_AWBURST : out std_logic_vector(1 downto 0); M_AXI_DP_AWLOCK : out std_logic; M_AXI_DP_AWCACHE : out std_logic_vector(3 downto 0); M_AXI_DP_AWPROT : out std_logic_vector(2 downto 0); M_AXI_DP_AWQOS : out std_logic_vector(3 downto 0); M_AXI_DP_AWVALID : out std_logic; M_AXI_DP_AWREADY : in std_logic; M_AXI_DP_WDATA : out std_logic_vector((C_M_AXI_DP_DATA_WIDTH-1) downto 0); M_AXI_DP_WSTRB : out std_logic_vector(((C_M_AXI_DP_DATA_WIDTH/8)-1) downto 0); M_AXI_DP_WLAST : out std_logic; M_AXI_DP_WVALID : out std_logic; M_AXI_DP_WREADY : in std_logic; M_AXI_DP_BID : in std_logic_vector((C_M_AXI_DP_THREAD_ID_WIDTH-1) downto 0); M_AXI_DP_BRESP : in std_logic_vector(1 downto 0); M_AXI_DP_BVALID : in std_logic; M_AXI_DP_BREADY : out std_logic; M_AXI_DP_ARID : out std_logic_vector((C_M_AXI_DP_THREAD_ID_WIDTH-1) downto 0); M_AXI_DP_ARADDR : out std_logic_vector((C_M_AXI_DP_ADDR_WIDTH-1) downto 0); M_AXI_DP_ARLEN : out std_logic_vector(7 downto 0); M_AXI_DP_ARSIZE : out std_logic_vector(2 downto 0); M_AXI_DP_ARBURST : out std_logic_vector(1 downto 0); M_AXI_DP_ARLOCK : out std_logic; M_AXI_DP_ARCACHE : out std_logic_vector(3 downto 0); M_AXI_DP_ARPROT : out std_logic_vector(2 downto 0); M_AXI_DP_ARQOS : out std_logic_vector(3 downto 0); M_AXI_DP_ARVALID : out std_logic; M_AXI_DP_ARREADY : in std_logic; M_AXI_DP_RID : in std_logic_vector((C_M_AXI_DP_THREAD_ID_WIDTH-1) downto 0); M_AXI_DP_RDATA : in std_logic_vector((C_M_AXI_DP_DATA_WIDTH-1) downto 0); M_AXI_DP_RRESP : in std_logic_vector(1 downto 0); M_AXI_DP_RLAST : in std_logic; M_AXI_DP_RVALID : in std_logic; M_AXI_DP_RREADY : out std_logic; M_AXI_IC_AWID : out std_logic_vector((C_M_AXI_IC_THREAD_ID_WIDTH-1) downto 0); M_AXI_IC_AWADDR : out std_logic_vector((C_M_AXI_IC_ADDR_WIDTH-1) downto 0); M_AXI_IC_AWLEN : out std_logic_vector(7 downto 0); M_AXI_IC_AWSIZE : out std_logic_vector(2 downto 0); M_AXI_IC_AWBURST : out std_logic_vector(1 downto 0); M_AXI_IC_AWLOCK : out std_logic; M_AXI_IC_AWCACHE : out std_logic_vector(3 downto 0); M_AXI_IC_AWPROT : out std_logic_vector(2 downto 0); M_AXI_IC_AWQOS : out std_logic_vector(3 downto 0); M_AXI_IC_AWVALID : out std_logic; M_AXI_IC_AWREADY : in std_logic; M_AXI_IC_AWUSER : out std_logic_vector((C_M_AXI_IC_AWUSER_WIDTH-1) downto 0); M_AXI_IC_AWDOMAIN : out std_logic_vector(1 downto 0); M_AXI_IC_AWSNOOP : out std_logic_vector(2 downto 0); M_AXI_IC_AWBAR : out std_logic_vector(1 downto 0); M_AXI_IC_WDATA : out std_logic_vector((C_M_AXI_IC_DATA_WIDTH-1) downto 0); M_AXI_IC_WSTRB : out std_logic_vector(((C_M_AXI_IC_DATA_WIDTH/8)-1) downto 0); M_AXI_IC_WLAST : out std_logic; M_AXI_IC_WVALID : out std_logic; M_AXI_IC_WREADY : in std_logic; M_AXI_IC_WUSER : out std_logic_vector((C_M_AXI_IC_WUSER_WIDTH-1) downto 0); M_AXI_IC_BID : in std_logic_vector((C_M_AXI_IC_THREAD_ID_WIDTH-1) downto 0); M_AXI_IC_BRESP : in std_logic_vector(1 downto 0); M_AXI_IC_BVALID : in std_logic; M_AXI_IC_BREADY : out std_logic; M_AXI_IC_BUSER : in std_logic_vector((C_M_AXI_IC_BUSER_WIDTH-1) downto 0); M_AXI_IC_WACK : out std_logic; M_AXI_IC_ARID : out std_logic_vector((C_M_AXI_IC_THREAD_ID_WIDTH-1) downto 0); M_AXI_IC_ARADDR : out std_logic_vector((C_M_AXI_IC_ADDR_WIDTH-1) downto 0); M_AXI_IC_ARLEN : out std_logic_vector(7 downto 0); M_AXI_IC_ARSIZE : out std_logic_vector(2 downto 0); M_AXI_IC_ARBURST : out std_logic_vector(1 downto 0); M_AXI_IC_ARLOCK : out std_logic; M_AXI_IC_ARCACHE : out std_logic_vector(3 downto 0); M_AXI_IC_ARPROT : out std_logic_vector(2 downto 0); M_AXI_IC_ARQOS : out std_logic_vector(3 downto 0); M_AXI_IC_ARVALID : out std_logic; M_AXI_IC_ARREADY : in std_logic; M_AXI_IC_ARUSER : out std_logic_vector((C_M_AXI_IC_ARUSER_WIDTH-1) downto 0); M_AXI_IC_ARDOMAIN : out std_logic_vector(1 downto 0); M_AXI_IC_ARSNOOP : out std_logic_vector(3 downto 0); M_AXI_IC_ARBAR : out std_logic_vector(1 downto 0); M_AXI_IC_RID : in std_logic_vector((C_M_AXI_IC_THREAD_ID_WIDTH-1) downto 0); M_AXI_IC_RDATA : in std_logic_vector((C_M_AXI_IC_DATA_WIDTH-1) downto 0); M_AXI_IC_RRESP : in std_logic_vector(1+2*((C_INTERCONNECT-1)/2) downto 0); M_AXI_IC_RLAST : in std_logic; M_AXI_IC_RVALID : in std_logic; M_AXI_IC_RREADY : out std_logic; M_AXI_IC_RUSER : in std_logic_vector((C_M_AXI_IC_RUSER_WIDTH-1) downto 0); M_AXI_IC_RACK : out std_logic; M_AXI_IC_ACVALID : in std_logic; M_AXI_IC_ACADDR : in std_logic_vector((C_M_AXI_IC_ADDR_WIDTH-1) downto 0); M_AXI_IC_ACSNOOP : in std_logic_vector(3 downto 0); M_AXI_IC_ACPROT : in std_logic_vector(2 downto 0); M_AXI_IC_ACREADY : out std_logic; M_AXI_IC_CRREADY : in std_logic; M_AXI_IC_CRVALID : out std_logic; M_AXI_IC_CRRESP : out std_logic_vector(4 downto 0); M_AXI_IC_CDVALID : out std_logic; M_AXI_IC_CDREADY : in std_logic; M_AXI_IC_CDDATA : out std_logic_vector((C_M_AXI_IC_DATA_WIDTH-1) downto 0); M_AXI_IC_CDLAST : out std_logic; M_AXI_DC_AWID : out std_logic_vector((C_M_AXI_DC_THREAD_ID_WIDTH-1) downto 0); M_AXI_DC_AWADDR : out std_logic_vector((C_M_AXI_DC_ADDR_WIDTH-1) downto 0); M_AXI_DC_AWLEN : out std_logic_vector(7 downto 0); M_AXI_DC_AWSIZE : out std_logic_vector(2 downto 0); M_AXI_DC_AWBURST : out std_logic_vector(1 downto 0); M_AXI_DC_AWLOCK : out std_logic; M_AXI_DC_AWCACHE : out std_logic_vector(3 downto 0); M_AXI_DC_AWPROT : out std_logic_vector(2 downto 0); M_AXI_DC_AWQOS : out std_logic_vector(3 downto 0); M_AXI_DC_AWVALID : out std_logic; M_AXI_DC_AWREADY : in std_logic; M_AXI_DC_AWUSER : out std_logic_vector((C_M_AXI_DC_AWUSER_WIDTH-1) downto 0); M_AXI_DC_AWDOMAIN : out std_logic_vector(1 downto 0); M_AXI_DC_AWSNOOP : out std_logic_vector(2 downto 0); M_AXI_DC_AWBAR : out std_logic_vector(1 downto 0); M_AXI_DC_WDATA : out std_logic_vector((C_M_AXI_DC_DATA_WIDTH-1) downto 0); M_AXI_DC_WSTRB : out std_logic_vector(((C_M_AXI_DC_DATA_WIDTH/8)-1) downto 0); M_AXI_DC_WLAST : out std_logic; M_AXI_DC_WVALID : out std_logic; M_AXI_DC_WREADY : in std_logic; M_AXI_DC_WUSER : out std_logic_vector((C_M_AXI_DC_WUSER_WIDTH-1) downto 0); M_AXI_DC_BID : in std_logic_vector((C_M_AXI_DC_THREAD_ID_WIDTH-1) downto 0); M_AXI_DC_BRESP : in std_logic_vector(1 downto 0); M_AXI_DC_BVALID : in std_logic; M_AXI_DC_BREADY : out std_logic; M_AXI_DC_BUSER : in std_logic_vector((C_M_AXI_DC_BUSER_WIDTH-1) downto 0); M_AXI_DC_WACK : out std_logic; M_AXI_DC_ARID : out std_logic_vector((C_M_AXI_DC_THREAD_ID_WIDTH-1) downto 0); M_AXI_DC_ARADDR : out std_logic_vector((C_M_AXI_DC_ADDR_WIDTH-1) downto 0); M_AXI_DC_ARLEN : out std_logic_vector(7 downto 0); M_AXI_DC_ARSIZE : out std_logic_vector(2 downto 0); M_AXI_DC_ARBURST : out std_logic_vector(1 downto 0); M_AXI_DC_ARLOCK : out std_logic; M_AXI_DC_ARCACHE : out std_logic_vector(3 downto 0); M_AXI_DC_ARPROT : out std_logic_vector(2 downto 0); M_AXI_DC_ARQOS : out std_logic_vector(3 downto 0); M_AXI_DC_ARVALID : out std_logic; M_AXI_DC_ARREADY : in std_logic; M_AXI_DC_ARUSER : out std_logic_vector((C_M_AXI_DC_ARUSER_WIDTH-1) downto 0); M_AXI_DC_ARDOMAIN : out std_logic_vector(1 downto 0); M_AXI_DC_ARSNOOP : out std_logic_vector(3 downto 0); M_AXI_DC_ARBAR : out std_logic_vector(1 downto 0); M_AXI_DC_RID : in std_logic_vector((C_M_AXI_DC_THREAD_ID_WIDTH-1) downto 0); M_AXI_DC_RDATA : in std_logic_vector((C_M_AXI_DC_DATA_WIDTH-1) downto 0); M_AXI_DC_RRESP : in std_logic_vector(1+2*((C_INTERCONNECT-1)/2) downto 0); M_AXI_DC_RLAST : in std_logic; M_AXI_DC_RVALID : in std_logic; M_AXI_DC_RREADY : out std_logic; M_AXI_DC_RUSER : in std_logic_vector((C_M_AXI_DC_RUSER_WIDTH-1) downto 0); M_AXI_DC_RACK : out std_logic; M_AXI_DC_ACVALID : in std_logic; M_AXI_DC_ACADDR : in std_logic_vector((C_M_AXI_DC_ADDR_WIDTH-1) downto 0); M_AXI_DC_ACSNOOP : in std_logic_vector(3 downto 0); M_AXI_DC_ACPROT : in std_logic_vector(2 downto 0); M_AXI_DC_ACREADY : out std_logic; M_AXI_DC_CRREADY : in std_logic; M_AXI_DC_CRVALID : out std_logic; M_AXI_DC_CRRESP : out std_logic_vector(4 downto 0); M_AXI_DC_CDVALID : out std_logic; M_AXI_DC_CDREADY : in std_logic; M_AXI_DC_CDDATA : out std_logic_vector((C_M_AXI_DC_DATA_WIDTH-1) downto 0); M_AXI_DC_CDLAST : out std_logic; DBG_CLK : in std_logic; DBG_TDI : in std_logic; DBG_TDO : out std_logic; DBG_REG_EN : in std_logic_vector(0 to 7); DBG_SHIFT : in std_logic; DBG_CAPTURE : in std_logic; DBG_UPDATE : in std_logic; DEBUG_RST : in std_logic; Trace_Instruction : out std_logic_vector(0 to 31); Trace_Valid_Instr : out std_logic; Trace_PC : out std_logic_vector(0 to 31); Trace_Reg_Write : out std_logic; Trace_Reg_Addr : out std_logic_vector(0 to 4); Trace_MSR_Reg : out std_logic_vector(0 to 14); Trace_PID_Reg : out std_logic_vector(0 to 7); Trace_New_Reg_Value : out std_logic_vector(0 to 31); Trace_Exception_Taken : out std_logic; Trace_Exception_Kind : out std_logic_vector(0 to 4); Trace_Jump_Taken : out std_logic; Trace_Delay_Slot : out std_logic; Trace_Data_Address : out std_logic_vector(0 to 31); Trace_Data_Access : out std_logic; Trace_Data_Read : out std_logic; Trace_Data_Write : out std_logic; Trace_Data_Write_Value : out std_logic_vector(0 to 31); Trace_Data_Byte_Enable : out std_logic_vector(0 to 3); Trace_DCache_Req : out std_logic; Trace_DCache_Hit : out std_logic; Trace_DCache_Rdy : out std_logic; Trace_DCache_Read : out std_logic; Trace_ICache_Req : out std_logic; Trace_ICache_Hit : out std_logic; Trace_ICache_Rdy : out std_logic; Trace_OF_PipeRun : out std_logic; Trace_EX_PipeRun : out std_logic; Trace_MEM_PipeRun : out std_logic; Trace_MB_Halted : out std_logic; Trace_Jump_Hit : out std_logic; FSL0_S_CLK : out std_logic; FSL0_S_READ : out std_logic; FSL0_S_DATA : in std_logic_vector(0 to C_FSL_DATA_SIZE-1); FSL0_S_CONTROL : in std_logic; FSL0_S_EXISTS : in std_logic; FSL0_M_CLK : out std_logic; FSL0_M_WRITE : out std_logic; FSL0_M_DATA : out std_logic_vector(0 to C_FSL_DATA_SIZE-1); FSL0_M_CONTROL : out std_logic; FSL0_M_FULL : in std_logic; FSL1_S_CLK : out std_logic; FSL1_S_READ : out std_logic; FSL1_S_DATA : in std_logic_vector(0 to C_FSL_DATA_SIZE-1); FSL1_S_CONTROL : in std_logic; FSL1_S_EXISTS : in std_logic; FSL1_M_CLK : out std_logic; FSL1_M_WRITE : out std_logic; FSL1_M_DATA : out std_logic_vector(0 to C_FSL_DATA_SIZE-1); FSL1_M_CONTROL : out std_logic; FSL1_M_FULL : in std_logic; FSL2_S_CLK : out std_logic; FSL2_S_READ : out std_logic; FSL2_S_DATA : in std_logic_vector(0 to C_FSL_DATA_SIZE-1); FSL2_S_CONTROL : in std_logic; FSL2_S_EXISTS : in std_logic; FSL2_M_CLK : out std_logic; FSL2_M_WRITE : out std_logic; FSL2_M_DATA : out std_logic_vector(0 to C_FSL_DATA_SIZE-1); FSL2_M_CONTROL : out std_logic; FSL2_M_FULL : in std_logic; FSL3_S_CLK : out std_logic; FSL3_S_READ : out std_logic; FSL3_S_DATA : in std_logic_vector(0 to C_FSL_DATA_SIZE-1); FSL3_S_CONTROL : in std_logic; FSL3_S_EXISTS : in std_logic; FSL3_M_CLK : out std_logic; FSL3_M_WRITE : out std_logic; FSL3_M_DATA : out std_logic_vector(0 to C_FSL_DATA_SIZE-1); FSL3_M_CONTROL : out std_logic; FSL3_M_FULL : in std_logic; FSL4_S_CLK : out std_logic; FSL4_S_READ : out std_logic; FSL4_S_DATA : in std_logic_vector(0 to C_FSL_DATA_SIZE-1); FSL4_S_CONTROL : in std_logic; FSL4_S_EXISTS : in std_logic; FSL4_M_CLK : out std_logic; FSL4_M_WRITE : out std_logic; FSL4_M_DATA : out std_logic_vector(0 to C_FSL_DATA_SIZE-1); FSL4_M_CONTROL : out std_logic; FSL4_M_FULL : in std_logic; FSL5_S_CLK : out std_logic; FSL5_S_READ : out std_logic; FSL5_S_DATA : in std_logic_vector(0 to C_FSL_DATA_SIZE-1); FSL5_S_CONTROL : in std_logic; FSL5_S_EXISTS : in std_logic; FSL5_M_CLK : out std_logic; FSL5_M_WRITE : out std_logic; FSL5_M_DATA : out std_logic_vector(0 to C_FSL_DATA_SIZE-1); FSL5_M_CONTROL : out std_logic; FSL5_M_FULL : in std_logic; FSL6_S_CLK : out std_logic; FSL6_S_READ : out std_logic; FSL6_S_DATA : in std_logic_vector(0 to C_FSL_DATA_SIZE-1); FSL6_S_CONTROL : in std_logic; FSL6_S_EXISTS : in std_logic; FSL6_M_CLK : out std_logic; FSL6_M_WRITE : out std_logic; FSL6_M_DATA : out std_logic_vector(0 to C_FSL_DATA_SIZE-1); FSL6_M_CONTROL : out std_logic; FSL6_M_FULL : in std_logic; FSL7_S_CLK : out std_logic; FSL7_S_READ : out std_logic; FSL7_S_DATA : in std_logic_vector(0 to C_FSL_DATA_SIZE-1); FSL7_S_CONTROL : in std_logic; FSL7_S_EXISTS : in std_logic; FSL7_M_CLK : out std_logic; FSL7_M_WRITE : out std_logic; FSL7_M_DATA : out std_logic_vector(0 to C_FSL_DATA_SIZE-1); FSL7_M_CONTROL : out std_logic; FSL7_M_FULL : in std_logic; FSL8_S_CLK : out std_logic; FSL8_S_READ : out std_logic; FSL8_S_DATA : in std_logic_vector(0 to C_FSL_DATA_SIZE-1); FSL8_S_CONTROL : in std_logic; FSL8_S_EXISTS : in std_logic; FSL8_M_CLK : out std_logic; FSL8_M_WRITE : out std_logic; FSL8_M_DATA : out std_logic_vector(0 to C_FSL_DATA_SIZE-1); FSL8_M_CONTROL : out std_logic; FSL8_M_FULL : in std_logic; FSL9_S_CLK : out std_logic; FSL9_S_READ : out std_logic; FSL9_S_DATA : in std_logic_vector(0 to C_FSL_DATA_SIZE-1); FSL9_S_CONTROL : in std_logic; FSL9_S_EXISTS : in std_logic; FSL9_M_CLK : out std_logic; FSL9_M_WRITE : out std_logic; FSL9_M_DATA : out std_logic_vector(0 to C_FSL_DATA_SIZE-1); FSL9_M_CONTROL : out std_logic; FSL9_M_FULL : in std_logic; FSL10_S_CLK : out std_logic; FSL10_S_READ : out std_logic; FSL10_S_DATA : in std_logic_vector(0 to C_FSL_DATA_SIZE-1); FSL10_S_CONTROL : in std_logic; FSL10_S_EXISTS : in std_logic; FSL10_M_CLK : out std_logic; FSL10_M_WRITE : out std_logic; FSL10_M_DATA : out std_logic_vector(0 to C_FSL_DATA_SIZE-1); FSL10_M_CONTROL : out std_logic; FSL10_M_FULL : in std_logic; FSL11_S_CLK : out std_logic; FSL11_S_READ : out std_logic; FSL11_S_DATA : in std_logic_vector(0 to C_FSL_DATA_SIZE-1); FSL11_S_CONTROL : in std_logic; FSL11_S_EXISTS : in std_logic; FSL11_M_CLK : out std_logic; FSL11_M_WRITE : out std_logic; FSL11_M_DATA : out std_logic_vector(0 to C_FSL_DATA_SIZE-1); FSL11_M_CONTROL : out std_logic; FSL11_M_FULL : in std_logic; FSL12_S_CLK : out std_logic; FSL12_S_READ : out std_logic; FSL12_S_DATA : in std_logic_vector(0 to C_FSL_DATA_SIZE-1); FSL12_S_CONTROL : in std_logic; FSL12_S_EXISTS : in std_logic; FSL12_M_CLK : out std_logic; FSL12_M_WRITE : out std_logic; FSL12_M_DATA : out std_logic_vector(0 to C_FSL_DATA_SIZE-1); FSL12_M_CONTROL : out std_logic; FSL12_M_FULL : in std_logic; FSL13_S_CLK : out std_logic; FSL13_S_READ : out std_logic; FSL13_S_DATA : in std_logic_vector(0 to C_FSL_DATA_SIZE-1); FSL13_S_CONTROL : in std_logic; FSL13_S_EXISTS : in std_logic; FSL13_M_CLK : out std_logic; FSL13_M_WRITE : out std_logic; FSL13_M_DATA : out std_logic_vector(0 to C_FSL_DATA_SIZE-1); FSL13_M_CONTROL : out std_logic; FSL13_M_FULL : in std_logic; FSL14_S_CLK : out std_logic; FSL14_S_READ : out std_logic; FSL14_S_DATA : in std_logic_vector(0 to C_FSL_DATA_SIZE-1); FSL14_S_CONTROL : in std_logic; FSL14_S_EXISTS : in std_logic; FSL14_M_CLK : out std_logic; FSL14_M_WRITE : out std_logic; FSL14_M_DATA : out std_logic_vector(0 to C_FSL_DATA_SIZE-1); FSL14_M_CONTROL : out std_logic; FSL14_M_FULL : in std_logic; FSL15_S_CLK : out std_logic; FSL15_S_READ : out std_logic; FSL15_S_DATA : in std_logic_vector(0 to C_FSL_DATA_SIZE-1); FSL15_S_CONTROL : in std_logic; FSL15_S_EXISTS : in std_logic; FSL15_M_CLK : out std_logic; FSL15_M_WRITE : out std_logic; FSL15_M_DATA : out std_logic_vector(0 to C_FSL_DATA_SIZE-1); FSL15_M_CONTROL : out std_logic; FSL15_M_FULL : in std_logic; M0_AXIS_TLAST : out std_logic; M0_AXIS_TDATA : out std_logic_vector(C_M0_AXIS_DATA_WIDTH-1 downto 0); M0_AXIS_TVALID : out std_logic; M0_AXIS_TREADY : in std_logic; S0_AXIS_TLAST : in std_logic; S0_AXIS_TDATA : in std_logic_vector(C_S0_AXIS_DATA_WIDTH-1 downto 0); S0_AXIS_TVALID : in std_logic; S0_AXIS_TREADY : out std_logic; M1_AXIS_TLAST : out std_logic; M1_AXIS_TDATA : out std_logic_vector(C_M1_AXIS_DATA_WIDTH-1 downto 0); M1_AXIS_TVALID : out std_logic; M1_AXIS_TREADY : in std_logic; S1_AXIS_TLAST : in std_logic; S1_AXIS_TDATA : in std_logic_vector(C_S1_AXIS_DATA_WIDTH-1 downto 0); S1_AXIS_TVALID : in std_logic; S1_AXIS_TREADY : out std_logic; M2_AXIS_TLAST : out std_logic; M2_AXIS_TDATA : out std_logic_vector(C_M2_AXIS_DATA_WIDTH-1 downto 0); M2_AXIS_TVALID : out std_logic; M2_AXIS_TREADY : in std_logic; S2_AXIS_TLAST : in std_logic; S2_AXIS_TDATA : in std_logic_vector(C_S2_AXIS_DATA_WIDTH-1 downto 0); S2_AXIS_TVALID : in std_logic; S2_AXIS_TREADY : out std_logic; M3_AXIS_TLAST : out std_logic; M3_AXIS_TDATA : out std_logic_vector(C_M3_AXIS_DATA_WIDTH-1 downto 0); M3_AXIS_TVALID : out std_logic; M3_AXIS_TREADY : in std_logic; S3_AXIS_TLAST : in std_logic; S3_AXIS_TDATA : in std_logic_vector(C_S3_AXIS_DATA_WIDTH-1 downto 0); S3_AXIS_TVALID : in std_logic; S3_AXIS_TREADY : out std_logic; M4_AXIS_TLAST : out std_logic; M4_AXIS_TDATA : out std_logic_vector(C_M4_AXIS_DATA_WIDTH-1 downto 0); M4_AXIS_TVALID : out std_logic; M4_AXIS_TREADY : in std_logic; S4_AXIS_TLAST : in std_logic; S4_AXIS_TDATA : in std_logic_vector(C_S4_AXIS_DATA_WIDTH-1 downto 0); S4_AXIS_TVALID : in std_logic; S4_AXIS_TREADY : out std_logic; M5_AXIS_TLAST : out std_logic; M5_AXIS_TDATA : out std_logic_vector(C_M5_AXIS_DATA_WIDTH-1 downto 0); M5_AXIS_TVALID : out std_logic; M5_AXIS_TREADY : in std_logic; S5_AXIS_TLAST : in std_logic; S5_AXIS_TDATA : in std_logic_vector(C_S5_AXIS_DATA_WIDTH-1 downto 0); S5_AXIS_TVALID : in std_logic; S5_AXIS_TREADY : out std_logic; M6_AXIS_TLAST : out std_logic; M6_AXIS_TDATA : out std_logic_vector(C_M6_AXIS_DATA_WIDTH-1 downto 0); M6_AXIS_TVALID : out std_logic; M6_AXIS_TREADY : in std_logic; S6_AXIS_TLAST : in std_logic; S6_AXIS_TDATA : in std_logic_vector(C_S6_AXIS_DATA_WIDTH-1 downto 0); S6_AXIS_TVALID : in std_logic; S6_AXIS_TREADY : out std_logic; M7_AXIS_TLAST : out std_logic; M7_AXIS_TDATA : out std_logic_vector(C_M7_AXIS_DATA_WIDTH-1 downto 0); M7_AXIS_TVALID : out std_logic; M7_AXIS_TREADY : in std_logic; S7_AXIS_TLAST : in std_logic; S7_AXIS_TDATA : in std_logic_vector(C_S7_AXIS_DATA_WIDTH-1 downto 0); S7_AXIS_TVALID : in std_logic; S7_AXIS_TREADY : out std_logic; M8_AXIS_TLAST : out std_logic; M8_AXIS_TDATA : out std_logic_vector(C_M8_AXIS_DATA_WIDTH-1 downto 0); M8_AXIS_TVALID : out std_logic; M8_AXIS_TREADY : in std_logic; S8_AXIS_TLAST : in std_logic; S8_AXIS_TDATA : in std_logic_vector(C_S8_AXIS_DATA_WIDTH-1 downto 0); S8_AXIS_TVALID : in std_logic; S8_AXIS_TREADY : out std_logic; M9_AXIS_TLAST : out std_logic; M9_AXIS_TDATA : out std_logic_vector(C_M9_AXIS_DATA_WIDTH-1 downto 0); M9_AXIS_TVALID : out std_logic; M9_AXIS_TREADY : in std_logic; S9_AXIS_TLAST : in std_logic; S9_AXIS_TDATA : in std_logic_vector(C_S9_AXIS_DATA_WIDTH-1 downto 0); S9_AXIS_TVALID : in std_logic; S9_AXIS_TREADY : out std_logic; M10_AXIS_TLAST : out std_logic; M10_AXIS_TDATA : out std_logic_vector(C_M10_AXIS_DATA_WIDTH-1 downto 0); M10_AXIS_TVALID : out std_logic; M10_AXIS_TREADY : in std_logic; S10_AXIS_TLAST : in std_logic; S10_AXIS_TDATA : in std_logic_vector(C_S10_AXIS_DATA_WIDTH-1 downto 0); S10_AXIS_TVALID : in std_logic; S10_AXIS_TREADY : out std_logic; M11_AXIS_TLAST : out std_logic; M11_AXIS_TDATA : out std_logic_vector(C_M11_AXIS_DATA_WIDTH-1 downto 0); M11_AXIS_TVALID : out std_logic; M11_AXIS_TREADY : in std_logic; S11_AXIS_TLAST : in std_logic; S11_AXIS_TDATA : in std_logic_vector(C_S11_AXIS_DATA_WIDTH-1 downto 0); S11_AXIS_TVALID : in std_logic; S11_AXIS_TREADY : out std_logic; M12_AXIS_TLAST : out std_logic; M12_AXIS_TDATA : out std_logic_vector(C_M12_AXIS_DATA_WIDTH-1 downto 0); M12_AXIS_TVALID : out std_logic; M12_AXIS_TREADY : in std_logic; S12_AXIS_TLAST : in std_logic; S12_AXIS_TDATA : in std_logic_vector(C_S12_AXIS_DATA_WIDTH-1 downto 0); S12_AXIS_TVALID : in std_logic; S12_AXIS_TREADY : out std_logic; M13_AXIS_TLAST : out std_logic; M13_AXIS_TDATA : out std_logic_vector(C_M13_AXIS_DATA_WIDTH-1 downto 0); M13_AXIS_TVALID : out std_logic; M13_AXIS_TREADY : in std_logic; S13_AXIS_TLAST : in std_logic; S13_AXIS_TDATA : in std_logic_vector(C_S13_AXIS_DATA_WIDTH-1 downto 0); S13_AXIS_TVALID : in std_logic; S13_AXIS_TREADY : out std_logic; M14_AXIS_TLAST : out std_logic; M14_AXIS_TDATA : out std_logic_vector(C_M14_AXIS_DATA_WIDTH-1 downto 0); M14_AXIS_TVALID : out std_logic; M14_AXIS_TREADY : in std_logic; S14_AXIS_TLAST : in std_logic; S14_AXIS_TDATA : in std_logic_vector(C_S14_AXIS_DATA_WIDTH-1 downto 0); S14_AXIS_TVALID : in std_logic; S14_AXIS_TREADY : out std_logic; M15_AXIS_TLAST : out std_logic; M15_AXIS_TDATA : out std_logic_vector(C_M15_AXIS_DATA_WIDTH-1 downto 0); M15_AXIS_TVALID : out std_logic; M15_AXIS_TREADY : in std_logic; S15_AXIS_TLAST : in std_logic; S15_AXIS_TDATA : in std_logic_vector(C_S15_AXIS_DATA_WIDTH-1 downto 0); S15_AXIS_TVALID : in std_logic; S15_AXIS_TREADY : out std_logic; ICACHE_FSL_IN_CLK : out std_logic; ICACHE_FSL_IN_READ : out std_logic; ICACHE_FSL_IN_DATA : in std_logic_vector(0 to 31); ICACHE_FSL_IN_CONTROL : in std_logic; ICACHE_FSL_IN_EXISTS : in std_logic; ICACHE_FSL_OUT_CLK : out std_logic; ICACHE_FSL_OUT_WRITE : out std_logic; ICACHE_FSL_OUT_DATA : out std_logic_vector(0 to 31); ICACHE_FSL_OUT_CONTROL : out std_logic; ICACHE_FSL_OUT_FULL : in std_logic; DCACHE_FSL_IN_CLK : out std_logic; DCACHE_FSL_IN_READ : out std_logic; DCACHE_FSL_IN_DATA : in std_logic_vector(0 to 31); DCACHE_FSL_IN_CONTROL : in std_logic; DCACHE_FSL_IN_EXISTS : in std_logic; DCACHE_FSL_OUT_CLK : out std_logic; DCACHE_FSL_OUT_WRITE : out std_logic; DCACHE_FSL_OUT_DATA : out std_logic_vector(0 to 31); DCACHE_FSL_OUT_CONTROL : out std_logic; DCACHE_FSL_OUT_FULL : in std_logic ); end component; begin microblaze_0 : microblaze generic map ( C_SCO => 0, C_FREQ => 125000000, C_DATA_SIZE => 32, C_DYNAMIC_BUS_SIZING => 1, C_FAMILY => "virtex5", C_INSTANCE => "microblaze_0", C_AVOID_PRIMITIVES => 0, C_FAULT_TOLERANT => 0, C_ECC_USE_CE_EXCEPTION => 0, C_LOCKSTEP_SLAVE => 0, C_ENDIANNESS => 0, C_AREA_OPTIMIZED => 0, C_OPTIMIZATION => 0, C_INTERCONNECT => 1, C_STREAM_INTERCONNECT => 0, C_BASE_VECTORS => X"00000000", C_DPLB_DWIDTH => 64, C_DPLB_NATIVE_DWIDTH => 32, C_DPLB_BURST_EN => 0, C_DPLB_P2P => 0, C_IPLB_DWIDTH => 64, C_IPLB_NATIVE_DWIDTH => 32, C_IPLB_BURST_EN => 0, C_IPLB_P2P => 0, C_M_AXI_DP_THREAD_ID_WIDTH => 1, C_M_AXI_DP_DATA_WIDTH => 32, C_M_AXI_DP_ADDR_WIDTH => 32, C_M_AXI_DP_EXCLUSIVE_ACCESS => 0, C_M_AXI_IP_THREAD_ID_WIDTH => 1, C_M_AXI_IP_DATA_WIDTH => 32, C_M_AXI_IP_ADDR_WIDTH => 32, C_D_AXI => 0, C_D_PLB => 1, C_D_LMB => 1, C_I_AXI => 0, C_I_PLB => 1, C_I_LMB => 1, C_USE_MSR_INSTR => 0, C_USE_PCMP_INSTR => 0, C_USE_BARREL => 0, C_USE_DIV => 0, C_USE_HW_MUL => 0, C_USE_FPU => 0, C_USE_REORDER_INSTR => 0, C_UNALIGNED_EXCEPTIONS => 0, C_ILL_OPCODE_EXCEPTION => 0, C_M_AXI_I_BUS_EXCEPTION => 0, C_M_AXI_D_BUS_EXCEPTION => 0, C_IPLB_BUS_EXCEPTION => 0, C_DPLB_BUS_EXCEPTION => 0, C_DIV_ZERO_EXCEPTION => 0, C_FPU_EXCEPTION => 0, C_FSL_EXCEPTION => 0, C_USE_STACK_PROTECTION => 0, C_PVR => 0, C_PVR_USER1 => X"00", C_PVR_USER2 => X"00000000", C_DEBUG_ENABLED => 1, C_NUMBER_OF_PC_BRK => 1, C_NUMBER_OF_RD_ADDR_BRK => 0, C_NUMBER_OF_WR_ADDR_BRK => 0, C_INTERRUPT_IS_EDGE => 0, C_EDGE_IS_POSITIVE => 1, C_RESET_MSR => X"00000000", C_OPCODE_0x0_ILLEGAL => 0, C_FSL_LINKS => 0, C_FSL_DATA_SIZE => 32, C_USE_EXTENDED_FSL_INSTR => 0, C_M0_AXIS_DATA_WIDTH => 32, C_S0_AXIS_DATA_WIDTH => 32, C_M1_AXIS_DATA_WIDTH => 32, C_S1_AXIS_DATA_WIDTH => 32, C_M2_AXIS_DATA_WIDTH => 32, C_S2_AXIS_DATA_WIDTH => 32, C_M3_AXIS_DATA_WIDTH => 32, C_S3_AXIS_DATA_WIDTH => 32, C_M4_AXIS_DATA_WIDTH => 32, C_S4_AXIS_DATA_WIDTH => 32, C_M5_AXIS_DATA_WIDTH => 32, C_S5_AXIS_DATA_WIDTH => 32, C_M6_AXIS_DATA_WIDTH => 32, C_S6_AXIS_DATA_WIDTH => 32, C_M7_AXIS_DATA_WIDTH => 32, C_S7_AXIS_DATA_WIDTH => 32, C_M8_AXIS_DATA_WIDTH => 32, C_S8_AXIS_DATA_WIDTH => 32, C_M9_AXIS_DATA_WIDTH => 32, C_S9_AXIS_DATA_WIDTH => 32, C_M10_AXIS_DATA_WIDTH => 32, C_S10_AXIS_DATA_WIDTH => 32, C_M11_AXIS_DATA_WIDTH => 32, C_S11_AXIS_DATA_WIDTH => 32, C_M12_AXIS_DATA_WIDTH => 32, C_S12_AXIS_DATA_WIDTH => 32, C_M13_AXIS_DATA_WIDTH => 32, C_S13_AXIS_DATA_WIDTH => 32, C_M14_AXIS_DATA_WIDTH => 32, C_S14_AXIS_DATA_WIDTH => 32, C_M15_AXIS_DATA_WIDTH => 32, C_S15_AXIS_DATA_WIDTH => 32, C_ICACHE_BASEADDR => X"00000000", C_ICACHE_HIGHADDR => X"3FFFFFFF", C_USE_ICACHE => 0, C_ALLOW_ICACHE_WR => 1, C_ADDR_TAG_BITS => 0, C_CACHE_BYTE_SIZE => 2048, C_ICACHE_USE_FSL => 1, C_ICACHE_LINE_LEN => 4, C_ICACHE_ALWAYS_USED => 0, C_ICACHE_INTERFACE => 0, C_ICACHE_VICTIMS => 0, C_ICACHE_STREAMS => 0, C_ICACHE_FORCE_TAG_LUTRAM => 0, C_ICACHE_DATA_WIDTH => 0, C_M_AXI_IC_THREAD_ID_WIDTH => 1, C_M_AXI_IC_DATA_WIDTH => 32, C_M_AXI_IC_ADDR_WIDTH => 32, C_M_AXI_IC_USER_VALUE => 2#11111#, C_M_AXI_IC_AWUSER_WIDTH => 5, C_M_AXI_IC_ARUSER_WIDTH => 5, C_M_AXI_IC_WUSER_WIDTH => 1, C_M_AXI_IC_RUSER_WIDTH => 1, C_M_AXI_IC_BUSER_WIDTH => 1, C_DCACHE_BASEADDR => X"00000000", C_DCACHE_HIGHADDR => X"3FFFFFFF", C_USE_DCACHE => 0, C_ALLOW_DCACHE_WR => 1, C_DCACHE_ADDR_TAG => 0, C_DCACHE_BYTE_SIZE => 2048, C_DCACHE_USE_FSL => 1, C_DCACHE_LINE_LEN => 4, C_DCACHE_ALWAYS_USED => 0, C_DCACHE_INTERFACE => 0, C_DCACHE_USE_WRITEBACK => 0, C_DCACHE_VICTIMS => 0, C_DCACHE_FORCE_TAG_LUTRAM => 0, C_DCACHE_DATA_WIDTH => 0, C_M_AXI_DC_THREAD_ID_WIDTH => 1, C_M_AXI_DC_DATA_WIDTH => 32, C_M_AXI_DC_ADDR_WIDTH => 32, C_M_AXI_DC_EXCLUSIVE_ACCESS => 0, C_M_AXI_DC_USER_VALUE => 2#11111#, C_M_AXI_DC_AWUSER_WIDTH => 5, C_M_AXI_DC_ARUSER_WIDTH => 5, C_M_AXI_DC_WUSER_WIDTH => 1, C_M_AXI_DC_RUSER_WIDTH => 1, C_M_AXI_DC_BUSER_WIDTH => 1, C_USE_MMU => 0, C_MMU_DTLB_SIZE => 4, C_MMU_ITLB_SIZE => 2, C_MMU_TLB_ACCESS => 3, C_MMU_ZONES => 16, C_MMU_PRIVILEGED_INSTR => 0, C_USE_INTERRUPT => 1, C_USE_EXT_BRK => 1, C_USE_EXT_NM_BRK => 1, C_USE_BRANCH_TARGET_CACHE => 0, C_BRANCH_TARGET_CACHE_SIZE => 0, C_PC_WIDTH => 32 ) port map ( CLK => CLK, RESET => RESET, MB_RESET => MB_RESET, INTERRUPT => INTERRUPT, INTERRUPT_ADDRESS => INTERRUPT_ADDRESS, INTERRUPT_ACK => INTERRUPT_ACK, EXT_BRK => EXT_BRK, EXT_NM_BRK => EXT_NM_BRK, DBG_STOP => DBG_STOP, MB_Halted => MB_Halted, MB_Error => MB_Error, WAKEUP => WAKEUP, SLEEP => SLEEP, DBG_WAKEUP => DBG_WAKEUP, LOCKSTEP_MASTER_OUT => LOCKSTEP_MASTER_OUT, LOCKSTEP_SLAVE_IN => LOCKSTEP_SLAVE_IN, LOCKSTEP_OUT => LOCKSTEP_OUT, INSTR => INSTR, IREADY => IREADY, IWAIT => IWAIT, ICE => ICE, IUE => IUE, INSTR_ADDR => INSTR_ADDR, IFETCH => IFETCH, I_AS => I_AS, IPLB_M_ABort => IPLB_M_ABort, IPLB_M_ABus => IPLB_M_ABus, IPLB_M_UABus => IPLB_M_UABus, IPLB_M_BE => IPLB_M_BE, IPLB_M_busLock => IPLB_M_busLock, IPLB_M_lockErr => IPLB_M_lockErr, IPLB_M_MSize => IPLB_M_MSize, IPLB_M_priority => IPLB_M_priority, IPLB_M_rdBurst => IPLB_M_rdBurst, IPLB_M_request => IPLB_M_request, IPLB_M_RNW => IPLB_M_RNW, IPLB_M_size => IPLB_M_size, IPLB_M_TAttribute => IPLB_M_TAttribute, IPLB_M_type => IPLB_M_type, IPLB_M_wrBurst => IPLB_M_wrBurst, IPLB_M_wrDBus => IPLB_M_wrDBus, IPLB_MBusy => IPLB_MBusy, IPLB_MRdErr => IPLB_MRdErr, IPLB_MWrErr => IPLB_MWrErr, IPLB_MIRQ => IPLB_MIRQ, IPLB_MWrBTerm => IPLB_MWrBTerm, IPLB_MWrDAck => IPLB_MWrDAck, IPLB_MAddrAck => IPLB_MAddrAck, IPLB_MRdBTerm => IPLB_MRdBTerm, IPLB_MRdDAck => IPLB_MRdDAck, IPLB_MRdDBus => IPLB_MRdDBus, IPLB_MRdWdAddr => IPLB_MRdWdAddr, IPLB_MRearbitrate => IPLB_MRearbitrate, IPLB_MSSize => IPLB_MSSize, IPLB_MTimeout => IPLB_MTimeout, DATA_READ => DATA_READ, DREADY => DREADY, DWAIT => DWAIT, DCE => DCE, DUE => DUE, DATA_WRITE => DATA_WRITE, DATA_ADDR => DATA_ADDR, D_AS => D_AS, READ_STROBE => READ_STROBE, WRITE_STROBE => WRITE_STROBE, BYTE_ENABLE => BYTE_ENABLE, DPLB_M_ABort => DPLB_M_ABort, DPLB_M_ABus => DPLB_M_ABus, DPLB_M_UABus => DPLB_M_UABus, DPLB_M_BE => DPLB_M_BE, DPLB_M_busLock => DPLB_M_busLock, DPLB_M_lockErr => DPLB_M_lockErr, DPLB_M_MSize => DPLB_M_MSize, DPLB_M_priority => DPLB_M_priority, DPLB_M_rdBurst => DPLB_M_rdBurst, DPLB_M_request => DPLB_M_request, DPLB_M_RNW => DPLB_M_RNW, DPLB_M_size => DPLB_M_size, DPLB_M_TAttribute => DPLB_M_TAttribute, DPLB_M_type => DPLB_M_type, DPLB_M_wrBurst => DPLB_M_wrBurst, DPLB_M_wrDBus => DPLB_M_wrDBus, DPLB_MBusy => DPLB_MBusy, DPLB_MRdErr => DPLB_MRdErr, DPLB_MWrErr => DPLB_MWrErr, DPLB_MIRQ => DPLB_MIRQ, DPLB_MWrBTerm => DPLB_MWrBTerm, DPLB_MWrDAck => DPLB_MWrDAck, DPLB_MAddrAck => DPLB_MAddrAck, DPLB_MRdBTerm => DPLB_MRdBTerm, DPLB_MRdDAck => DPLB_MRdDAck, DPLB_MRdDBus => DPLB_MRdDBus, DPLB_MRdWdAddr => DPLB_MRdWdAddr, DPLB_MRearbitrate => DPLB_MRearbitrate, DPLB_MSSize => DPLB_MSSize, DPLB_MTimeout => DPLB_MTimeout, M_AXI_IP_AWID => M_AXI_IP_AWID, M_AXI_IP_AWADDR => M_AXI_IP_AWADDR, M_AXI_IP_AWLEN => M_AXI_IP_AWLEN, M_AXI_IP_AWSIZE => M_AXI_IP_AWSIZE, M_AXI_IP_AWBURST => M_AXI_IP_AWBURST, M_AXI_IP_AWLOCK => M_AXI_IP_AWLOCK, M_AXI_IP_AWCACHE => M_AXI_IP_AWCACHE, M_AXI_IP_AWPROT => M_AXI_IP_AWPROT, M_AXI_IP_AWQOS => M_AXI_IP_AWQOS, M_AXI_IP_AWVALID => M_AXI_IP_AWVALID, M_AXI_IP_AWREADY => M_AXI_IP_AWREADY, M_AXI_IP_WDATA => M_AXI_IP_WDATA, M_AXI_IP_WSTRB => M_AXI_IP_WSTRB, M_AXI_IP_WLAST => M_AXI_IP_WLAST, M_AXI_IP_WVALID => M_AXI_IP_WVALID, M_AXI_IP_WREADY => M_AXI_IP_WREADY, M_AXI_IP_BID => M_AXI_IP_BID, M_AXI_IP_BRESP => M_AXI_IP_BRESP, M_AXI_IP_BVALID => M_AXI_IP_BVALID, M_AXI_IP_BREADY => M_AXI_IP_BREADY, M_AXI_IP_ARID => M_AXI_IP_ARID, M_AXI_IP_ARADDR => M_AXI_IP_ARADDR, M_AXI_IP_ARLEN => M_AXI_IP_ARLEN, M_AXI_IP_ARSIZE => M_AXI_IP_ARSIZE, M_AXI_IP_ARBURST => M_AXI_IP_ARBURST, M_AXI_IP_ARLOCK => M_AXI_IP_ARLOCK, M_AXI_IP_ARCACHE => M_AXI_IP_ARCACHE, M_AXI_IP_ARPROT => M_AXI_IP_ARPROT, M_AXI_IP_ARQOS => M_AXI_IP_ARQOS, M_AXI_IP_ARVALID => M_AXI_IP_ARVALID, M_AXI_IP_ARREADY => M_AXI_IP_ARREADY, M_AXI_IP_RID => M_AXI_IP_RID, M_AXI_IP_RDATA => M_AXI_IP_RDATA, M_AXI_IP_RRESP => M_AXI_IP_RRESP, M_AXI_IP_RLAST => M_AXI_IP_RLAST, M_AXI_IP_RVALID => M_AXI_IP_RVALID, M_AXI_IP_RREADY => M_AXI_IP_RREADY, M_AXI_DP_AWID => M_AXI_DP_AWID, M_AXI_DP_AWADDR => M_AXI_DP_AWADDR, M_AXI_DP_AWLEN => M_AXI_DP_AWLEN, M_AXI_DP_AWSIZE => M_AXI_DP_AWSIZE, M_AXI_DP_AWBURST => M_AXI_DP_AWBURST, M_AXI_DP_AWLOCK => M_AXI_DP_AWLOCK, M_AXI_DP_AWCACHE => M_AXI_DP_AWCACHE, M_AXI_DP_AWPROT => M_AXI_DP_AWPROT, M_AXI_DP_AWQOS => M_AXI_DP_AWQOS, M_AXI_DP_AWVALID => M_AXI_DP_AWVALID, M_AXI_DP_AWREADY => M_AXI_DP_AWREADY, M_AXI_DP_WDATA => M_AXI_DP_WDATA, M_AXI_DP_WSTRB => M_AXI_DP_WSTRB, M_AXI_DP_WLAST => M_AXI_DP_WLAST, M_AXI_DP_WVALID => M_AXI_DP_WVALID, M_AXI_DP_WREADY => M_AXI_DP_WREADY, M_AXI_DP_BID => M_AXI_DP_BID, M_AXI_DP_BRESP => M_AXI_DP_BRESP, M_AXI_DP_BVALID => M_AXI_DP_BVALID, M_AXI_DP_BREADY => M_AXI_DP_BREADY, M_AXI_DP_ARID => M_AXI_DP_ARID, M_AXI_DP_ARADDR => M_AXI_DP_ARADDR, M_AXI_DP_ARLEN => M_AXI_DP_ARLEN, M_AXI_DP_ARSIZE => M_AXI_DP_ARSIZE, M_AXI_DP_ARBURST => M_AXI_DP_ARBURST, M_AXI_DP_ARLOCK => M_AXI_DP_ARLOCK, M_AXI_DP_ARCACHE => M_AXI_DP_ARCACHE, M_AXI_DP_ARPROT => M_AXI_DP_ARPROT, M_AXI_DP_ARQOS => M_AXI_DP_ARQOS, M_AXI_DP_ARVALID => M_AXI_DP_ARVALID, M_AXI_DP_ARREADY => M_AXI_DP_ARREADY, M_AXI_DP_RID => M_AXI_DP_RID, M_AXI_DP_RDATA => M_AXI_DP_RDATA, M_AXI_DP_RRESP => M_AXI_DP_RRESP, M_AXI_DP_RLAST => M_AXI_DP_RLAST, M_AXI_DP_RVALID => M_AXI_DP_RVALID, M_AXI_DP_RREADY => M_AXI_DP_RREADY, M_AXI_IC_AWID => M_AXI_IC_AWID, M_AXI_IC_AWADDR => M_AXI_IC_AWADDR, M_AXI_IC_AWLEN => M_AXI_IC_AWLEN, M_AXI_IC_AWSIZE => M_AXI_IC_AWSIZE, M_AXI_IC_AWBURST => M_AXI_IC_AWBURST, M_AXI_IC_AWLOCK => M_AXI_IC_AWLOCK, M_AXI_IC_AWCACHE => M_AXI_IC_AWCACHE, M_AXI_IC_AWPROT => M_AXI_IC_AWPROT, M_AXI_IC_AWQOS => M_AXI_IC_AWQOS, M_AXI_IC_AWVALID => M_AXI_IC_AWVALID, M_AXI_IC_AWREADY => M_AXI_IC_AWREADY, M_AXI_IC_AWUSER => M_AXI_IC_AWUSER, M_AXI_IC_AWDOMAIN => M_AXI_IC_AWDOMAIN, M_AXI_IC_AWSNOOP => M_AXI_IC_AWSNOOP, M_AXI_IC_AWBAR => M_AXI_IC_AWBAR, M_AXI_IC_WDATA => M_AXI_IC_WDATA, M_AXI_IC_WSTRB => M_AXI_IC_WSTRB, M_AXI_IC_WLAST => M_AXI_IC_WLAST, M_AXI_IC_WVALID => M_AXI_IC_WVALID, M_AXI_IC_WREADY => M_AXI_IC_WREADY, M_AXI_IC_WUSER => M_AXI_IC_WUSER, M_AXI_IC_BID => M_AXI_IC_BID, M_AXI_IC_BRESP => M_AXI_IC_BRESP, M_AXI_IC_BVALID => M_AXI_IC_BVALID, M_AXI_IC_BREADY => M_AXI_IC_BREADY, M_AXI_IC_BUSER => M_AXI_IC_BUSER, M_AXI_IC_WACK => M_AXI_IC_WACK, M_AXI_IC_ARID => M_AXI_IC_ARID, M_AXI_IC_ARADDR => M_AXI_IC_ARADDR, M_AXI_IC_ARLEN => M_AXI_IC_ARLEN, M_AXI_IC_ARSIZE => M_AXI_IC_ARSIZE, M_AXI_IC_ARBURST => M_AXI_IC_ARBURST, M_AXI_IC_ARLOCK => M_AXI_IC_ARLOCK, M_AXI_IC_ARCACHE => M_AXI_IC_ARCACHE, M_AXI_IC_ARPROT => M_AXI_IC_ARPROT, M_AXI_IC_ARQOS => M_AXI_IC_ARQOS, M_AXI_IC_ARVALID => M_AXI_IC_ARVALID, M_AXI_IC_ARREADY => M_AXI_IC_ARREADY, M_AXI_IC_ARUSER => M_AXI_IC_ARUSER, M_AXI_IC_ARDOMAIN => M_AXI_IC_ARDOMAIN, M_AXI_IC_ARSNOOP => M_AXI_IC_ARSNOOP, M_AXI_IC_ARBAR => M_AXI_IC_ARBAR, M_AXI_IC_RID => M_AXI_IC_RID, M_AXI_IC_RDATA => M_AXI_IC_RDATA, M_AXI_IC_RRESP => M_AXI_IC_RRESP, M_AXI_IC_RLAST => M_AXI_IC_RLAST, M_AXI_IC_RVALID => M_AXI_IC_RVALID, M_AXI_IC_RREADY => M_AXI_IC_RREADY, M_AXI_IC_RUSER => M_AXI_IC_RUSER, M_AXI_IC_RACK => M_AXI_IC_RACK, M_AXI_IC_ACVALID => M_AXI_IC_ACVALID, M_AXI_IC_ACADDR => M_AXI_IC_ACADDR, M_AXI_IC_ACSNOOP => M_AXI_IC_ACSNOOP, M_AXI_IC_ACPROT => M_AXI_IC_ACPROT, M_AXI_IC_ACREADY => M_AXI_IC_ACREADY, M_AXI_IC_CRREADY => M_AXI_IC_CRREADY, M_AXI_IC_CRVALID => M_AXI_IC_CRVALID, M_AXI_IC_CRRESP => M_AXI_IC_CRRESP, M_AXI_IC_CDVALID => M_AXI_IC_CDVALID, M_AXI_IC_CDREADY => M_AXI_IC_CDREADY, M_AXI_IC_CDDATA => M_AXI_IC_CDDATA, M_AXI_IC_CDLAST => M_AXI_IC_CDLAST, M_AXI_DC_AWID => M_AXI_DC_AWID, M_AXI_DC_AWADDR => M_AXI_DC_AWADDR, M_AXI_DC_AWLEN => M_AXI_DC_AWLEN, M_AXI_DC_AWSIZE => M_AXI_DC_AWSIZE, M_AXI_DC_AWBURST => M_AXI_DC_AWBURST, M_AXI_DC_AWLOCK => M_AXI_DC_AWLOCK, M_AXI_DC_AWCACHE => M_AXI_DC_AWCACHE, M_AXI_DC_AWPROT => M_AXI_DC_AWPROT, M_AXI_DC_AWQOS => M_AXI_DC_AWQOS, M_AXI_DC_AWVALID => M_AXI_DC_AWVALID, M_AXI_DC_AWREADY => M_AXI_DC_AWREADY, M_AXI_DC_AWUSER => M_AXI_DC_AWUSER, M_AXI_DC_AWDOMAIN => M_AXI_DC_AWDOMAIN, M_AXI_DC_AWSNOOP => M_AXI_DC_AWSNOOP, M_AXI_DC_AWBAR => M_AXI_DC_AWBAR, M_AXI_DC_WDATA => M_AXI_DC_WDATA, M_AXI_DC_WSTRB => M_AXI_DC_WSTRB, M_AXI_DC_WLAST => M_AXI_DC_WLAST, M_AXI_DC_WVALID => M_AXI_DC_WVALID, M_AXI_DC_WREADY => M_AXI_DC_WREADY, M_AXI_DC_WUSER => M_AXI_DC_WUSER, M_AXI_DC_BID => M_AXI_DC_BID, M_AXI_DC_BRESP => M_AXI_DC_BRESP, M_AXI_DC_BVALID => M_AXI_DC_BVALID, M_AXI_DC_BREADY => M_AXI_DC_BREADY, M_AXI_DC_BUSER => M_AXI_DC_BUSER, M_AXI_DC_WACK => M_AXI_DC_WACK, M_AXI_DC_ARID => M_AXI_DC_ARID, M_AXI_DC_ARADDR => M_AXI_DC_ARADDR, M_AXI_DC_ARLEN => M_AXI_DC_ARLEN, M_AXI_DC_ARSIZE => M_AXI_DC_ARSIZE, M_AXI_DC_ARBURST => M_AXI_DC_ARBURST, M_AXI_DC_ARLOCK => M_AXI_DC_ARLOCK, M_AXI_DC_ARCACHE => M_AXI_DC_ARCACHE, M_AXI_DC_ARPROT => M_AXI_DC_ARPROT, M_AXI_DC_ARQOS => M_AXI_DC_ARQOS, M_AXI_DC_ARVALID => M_AXI_DC_ARVALID, M_AXI_DC_ARREADY => M_AXI_DC_ARREADY, M_AXI_DC_ARUSER => M_AXI_DC_ARUSER, M_AXI_DC_ARDOMAIN => M_AXI_DC_ARDOMAIN, M_AXI_DC_ARSNOOP => M_AXI_DC_ARSNOOP, M_AXI_DC_ARBAR => M_AXI_DC_ARBAR, M_AXI_DC_RID => M_AXI_DC_RID, M_AXI_DC_RDATA => M_AXI_DC_RDATA, M_AXI_DC_RRESP => M_AXI_DC_RRESP, M_AXI_DC_RLAST => M_AXI_DC_RLAST, M_AXI_DC_RVALID => M_AXI_DC_RVALID, M_AXI_DC_RREADY => M_AXI_DC_RREADY, M_AXI_DC_RUSER => M_AXI_DC_RUSER, M_AXI_DC_RACK => M_AXI_DC_RACK, M_AXI_DC_ACVALID => M_AXI_DC_ACVALID, M_AXI_DC_ACADDR => M_AXI_DC_ACADDR, M_AXI_DC_ACSNOOP => M_AXI_DC_ACSNOOP, M_AXI_DC_ACPROT => M_AXI_DC_ACPROT, M_AXI_DC_ACREADY => M_AXI_DC_ACREADY, M_AXI_DC_CRREADY => M_AXI_DC_CRREADY, M_AXI_DC_CRVALID => M_AXI_DC_CRVALID, M_AXI_DC_CRRESP => M_AXI_DC_CRRESP, M_AXI_DC_CDVALID => M_AXI_DC_CDVALID, M_AXI_DC_CDREADY => M_AXI_DC_CDREADY, M_AXI_DC_CDDATA => M_AXI_DC_CDDATA, M_AXI_DC_CDLAST => M_AXI_DC_CDLAST, DBG_CLK => DBG_CLK, DBG_TDI => DBG_TDI, DBG_TDO => DBG_TDO, DBG_REG_EN => DBG_REG_EN, DBG_SHIFT => DBG_SHIFT, DBG_CAPTURE => DBG_CAPTURE, DBG_UPDATE => DBG_UPDATE, DEBUG_RST => DEBUG_RST, Trace_Instruction => Trace_Instruction, Trace_Valid_Instr => Trace_Valid_Instr, Trace_PC => Trace_PC, Trace_Reg_Write => Trace_Reg_Write, Trace_Reg_Addr => Trace_Reg_Addr, Trace_MSR_Reg => Trace_MSR_Reg, Trace_PID_Reg => Trace_PID_Reg, Trace_New_Reg_Value => Trace_New_Reg_Value, Trace_Exception_Taken => Trace_Exception_Taken, Trace_Exception_Kind => Trace_Exception_Kind, Trace_Jump_Taken => Trace_Jump_Taken, Trace_Delay_Slot => Trace_Delay_Slot, Trace_Data_Address => Trace_Data_Address, Trace_Data_Access => Trace_Data_Access, Trace_Data_Read => Trace_Data_Read, Trace_Data_Write => Trace_Data_Write, Trace_Data_Write_Value => Trace_Data_Write_Value, Trace_Data_Byte_Enable => Trace_Data_Byte_Enable, Trace_DCache_Req => Trace_DCache_Req, Trace_DCache_Hit => Trace_DCache_Hit, Trace_DCache_Rdy => Trace_DCache_Rdy, Trace_DCache_Read => Trace_DCache_Read, Trace_ICache_Req => Trace_ICache_Req, Trace_ICache_Hit => Trace_ICache_Hit, Trace_ICache_Rdy => Trace_ICache_Rdy, Trace_OF_PipeRun => Trace_OF_PipeRun, Trace_EX_PipeRun => Trace_EX_PipeRun, Trace_MEM_PipeRun => Trace_MEM_PipeRun, Trace_MB_Halted => Trace_MB_Halted, Trace_Jump_Hit => Trace_Jump_Hit, FSL0_S_CLK => FSL0_S_CLK, FSL0_S_READ => FSL0_S_READ, FSL0_S_DATA => FSL0_S_DATA, FSL0_S_CONTROL => FSL0_S_CONTROL, FSL0_S_EXISTS => FSL0_S_EXISTS, FSL0_M_CLK => FSL0_M_CLK, FSL0_M_WRITE => FSL0_M_WRITE, FSL0_M_DATA => FSL0_M_DATA, FSL0_M_CONTROL => FSL0_M_CONTROL, FSL0_M_FULL => FSL0_M_FULL, FSL1_S_CLK => FSL1_S_CLK, FSL1_S_READ => FSL1_S_READ, FSL1_S_DATA => FSL1_S_DATA, FSL1_S_CONTROL => FSL1_S_CONTROL, FSL1_S_EXISTS => FSL1_S_EXISTS, FSL1_M_CLK => FSL1_M_CLK, FSL1_M_WRITE => FSL1_M_WRITE, FSL1_M_DATA => FSL1_M_DATA, FSL1_M_CONTROL => FSL1_M_CONTROL, FSL1_M_FULL => FSL1_M_FULL, FSL2_S_CLK => FSL2_S_CLK, FSL2_S_READ => FSL2_S_READ, FSL2_S_DATA => FSL2_S_DATA, FSL2_S_CONTROL => FSL2_S_CONTROL, FSL2_S_EXISTS => FSL2_S_EXISTS, FSL2_M_CLK => FSL2_M_CLK, FSL2_M_WRITE => FSL2_M_WRITE, FSL2_M_DATA => FSL2_M_DATA, FSL2_M_CONTROL => FSL2_M_CONTROL, FSL2_M_FULL => FSL2_M_FULL, FSL3_S_CLK => FSL3_S_CLK, FSL3_S_READ => FSL3_S_READ, FSL3_S_DATA => FSL3_S_DATA, FSL3_S_CONTROL => FSL3_S_CONTROL, FSL3_S_EXISTS => FSL3_S_EXISTS, FSL3_M_CLK => FSL3_M_CLK, FSL3_M_WRITE => FSL3_M_WRITE, FSL3_M_DATA => FSL3_M_DATA, FSL3_M_CONTROL => FSL3_M_CONTROL, FSL3_M_FULL => FSL3_M_FULL, FSL4_S_CLK => FSL4_S_CLK, FSL4_S_READ => FSL4_S_READ, FSL4_S_DATA => FSL4_S_DATA, FSL4_S_CONTROL => FSL4_S_CONTROL, FSL4_S_EXISTS => FSL4_S_EXISTS, FSL4_M_CLK => FSL4_M_CLK, FSL4_M_WRITE => FSL4_M_WRITE, FSL4_M_DATA => FSL4_M_DATA, FSL4_M_CONTROL => FSL4_M_CONTROL, FSL4_M_FULL => FSL4_M_FULL, FSL5_S_CLK => FSL5_S_CLK, FSL5_S_READ => FSL5_S_READ, FSL5_S_DATA => FSL5_S_DATA, FSL5_S_CONTROL => FSL5_S_CONTROL, FSL5_S_EXISTS => FSL5_S_EXISTS, FSL5_M_CLK => FSL5_M_CLK, FSL5_M_WRITE => FSL5_M_WRITE, FSL5_M_DATA => FSL5_M_DATA, FSL5_M_CONTROL => FSL5_M_CONTROL, FSL5_M_FULL => FSL5_M_FULL, FSL6_S_CLK => FSL6_S_CLK, FSL6_S_READ => FSL6_S_READ, FSL6_S_DATA => FSL6_S_DATA, FSL6_S_CONTROL => FSL6_S_CONTROL, FSL6_S_EXISTS => FSL6_S_EXISTS, FSL6_M_CLK => FSL6_M_CLK, FSL6_M_WRITE => FSL6_M_WRITE, FSL6_M_DATA => FSL6_M_DATA, FSL6_M_CONTROL => FSL6_M_CONTROL, FSL6_M_FULL => FSL6_M_FULL, FSL7_S_CLK => FSL7_S_CLK, FSL7_S_READ => FSL7_S_READ, FSL7_S_DATA => FSL7_S_DATA, FSL7_S_CONTROL => FSL7_S_CONTROL, FSL7_S_EXISTS => FSL7_S_EXISTS, FSL7_M_CLK => FSL7_M_CLK, FSL7_M_WRITE => FSL7_M_WRITE, FSL7_M_DATA => FSL7_M_DATA, FSL7_M_CONTROL => FSL7_M_CONTROL, FSL7_M_FULL => FSL7_M_FULL, FSL8_S_CLK => FSL8_S_CLK, FSL8_S_READ => FSL8_S_READ, FSL8_S_DATA => FSL8_S_DATA, FSL8_S_CONTROL => FSL8_S_CONTROL, FSL8_S_EXISTS => FSL8_S_EXISTS, FSL8_M_CLK => FSL8_M_CLK, FSL8_M_WRITE => FSL8_M_WRITE, FSL8_M_DATA => FSL8_M_DATA, FSL8_M_CONTROL => FSL8_M_CONTROL, FSL8_M_FULL => FSL8_M_FULL, FSL9_S_CLK => FSL9_S_CLK, FSL9_S_READ => FSL9_S_READ, FSL9_S_DATA => FSL9_S_DATA, FSL9_S_CONTROL => FSL9_S_CONTROL, FSL9_S_EXISTS => FSL9_S_EXISTS, FSL9_M_CLK => FSL9_M_CLK, FSL9_M_WRITE => FSL9_M_WRITE, FSL9_M_DATA => FSL9_M_DATA, FSL9_M_CONTROL => FSL9_M_CONTROL, FSL9_M_FULL => FSL9_M_FULL, FSL10_S_CLK => FSL10_S_CLK, FSL10_S_READ => FSL10_S_READ, FSL10_S_DATA => FSL10_S_DATA, FSL10_S_CONTROL => FSL10_S_CONTROL, FSL10_S_EXISTS => FSL10_S_EXISTS, FSL10_M_CLK => FSL10_M_CLK, FSL10_M_WRITE => FSL10_M_WRITE, FSL10_M_DATA => FSL10_M_DATA, FSL10_M_CONTROL => FSL10_M_CONTROL, FSL10_M_FULL => FSL10_M_FULL, FSL11_S_CLK => FSL11_S_CLK, FSL11_S_READ => FSL11_S_READ, FSL11_S_DATA => FSL11_S_DATA, FSL11_S_CONTROL => FSL11_S_CONTROL, FSL11_S_EXISTS => FSL11_S_EXISTS, FSL11_M_CLK => FSL11_M_CLK, FSL11_M_WRITE => FSL11_M_WRITE, FSL11_M_DATA => FSL11_M_DATA, FSL11_M_CONTROL => FSL11_M_CONTROL, FSL11_M_FULL => FSL11_M_FULL, FSL12_S_CLK => FSL12_S_CLK, FSL12_S_READ => FSL12_S_READ, FSL12_S_DATA => FSL12_S_DATA, FSL12_S_CONTROL => FSL12_S_CONTROL, FSL12_S_EXISTS => FSL12_S_EXISTS, FSL12_M_CLK => FSL12_M_CLK, FSL12_M_WRITE => FSL12_M_WRITE, FSL12_M_DATA => FSL12_M_DATA, FSL12_M_CONTROL => FSL12_M_CONTROL, FSL12_M_FULL => FSL12_M_FULL, FSL13_S_CLK => FSL13_S_CLK, FSL13_S_READ => FSL13_S_READ, FSL13_S_DATA => FSL13_S_DATA, FSL13_S_CONTROL => FSL13_S_CONTROL, FSL13_S_EXISTS => FSL13_S_EXISTS, FSL13_M_CLK => FSL13_M_CLK, FSL13_M_WRITE => FSL13_M_WRITE, FSL13_M_DATA => FSL13_M_DATA, FSL13_M_CONTROL => FSL13_M_CONTROL, FSL13_M_FULL => FSL13_M_FULL, FSL14_S_CLK => FSL14_S_CLK, FSL14_S_READ => FSL14_S_READ, FSL14_S_DATA => FSL14_S_DATA, FSL14_S_CONTROL => FSL14_S_CONTROL, FSL14_S_EXISTS => FSL14_S_EXISTS, FSL14_M_CLK => FSL14_M_CLK, FSL14_M_WRITE => FSL14_M_WRITE, FSL14_M_DATA => FSL14_M_DATA, FSL14_M_CONTROL => FSL14_M_CONTROL, FSL14_M_FULL => FSL14_M_FULL, FSL15_S_CLK => FSL15_S_CLK, FSL15_S_READ => FSL15_S_READ, FSL15_S_DATA => FSL15_S_DATA, FSL15_S_CONTROL => FSL15_S_CONTROL, FSL15_S_EXISTS => FSL15_S_EXISTS, FSL15_M_CLK => FSL15_M_CLK, FSL15_M_WRITE => FSL15_M_WRITE, FSL15_M_DATA => FSL15_M_DATA, FSL15_M_CONTROL => FSL15_M_CONTROL, FSL15_M_FULL => FSL15_M_FULL, M0_AXIS_TLAST => M0_AXIS_TLAST, M0_AXIS_TDATA => M0_AXIS_TDATA, M0_AXIS_TVALID => M0_AXIS_TVALID, M0_AXIS_TREADY => M0_AXIS_TREADY, S0_AXIS_TLAST => S0_AXIS_TLAST, S0_AXIS_TDATA => S0_AXIS_TDATA, S0_AXIS_TVALID => S0_AXIS_TVALID, S0_AXIS_TREADY => S0_AXIS_TREADY, M1_AXIS_TLAST => M1_AXIS_TLAST, M1_AXIS_TDATA => M1_AXIS_TDATA, M1_AXIS_TVALID => M1_AXIS_TVALID, M1_AXIS_TREADY => M1_AXIS_TREADY, S1_AXIS_TLAST => S1_AXIS_TLAST, S1_AXIS_TDATA => S1_AXIS_TDATA, S1_AXIS_TVALID => S1_AXIS_TVALID, S1_AXIS_TREADY => S1_AXIS_TREADY, M2_AXIS_TLAST => M2_AXIS_TLAST, M2_AXIS_TDATA => M2_AXIS_TDATA, M2_AXIS_TVALID => M2_AXIS_TVALID, M2_AXIS_TREADY => M2_AXIS_TREADY, S2_AXIS_TLAST => S2_AXIS_TLAST, S2_AXIS_TDATA => S2_AXIS_TDATA, S2_AXIS_TVALID => S2_AXIS_TVALID, S2_AXIS_TREADY => S2_AXIS_TREADY, M3_AXIS_TLAST => M3_AXIS_TLAST, M3_AXIS_TDATA => M3_AXIS_TDATA, M3_AXIS_TVALID => M3_AXIS_TVALID, M3_AXIS_TREADY => M3_AXIS_TREADY, S3_AXIS_TLAST => S3_AXIS_TLAST, S3_AXIS_TDATA => S3_AXIS_TDATA, S3_AXIS_TVALID => S3_AXIS_TVALID, S3_AXIS_TREADY => S3_AXIS_TREADY, M4_AXIS_TLAST => M4_AXIS_TLAST, M4_AXIS_TDATA => M4_AXIS_TDATA, M4_AXIS_TVALID => M4_AXIS_TVALID, M4_AXIS_TREADY => M4_AXIS_TREADY, S4_AXIS_TLAST => S4_AXIS_TLAST, S4_AXIS_TDATA => S4_AXIS_TDATA, S4_AXIS_TVALID => S4_AXIS_TVALID, S4_AXIS_TREADY => S4_AXIS_TREADY, M5_AXIS_TLAST => M5_AXIS_TLAST, M5_AXIS_TDATA => M5_AXIS_TDATA, M5_AXIS_TVALID => M5_AXIS_TVALID, M5_AXIS_TREADY => M5_AXIS_TREADY, S5_AXIS_TLAST => S5_AXIS_TLAST, S5_AXIS_TDATA => S5_AXIS_TDATA, S5_AXIS_TVALID => S5_AXIS_TVALID, S5_AXIS_TREADY => S5_AXIS_TREADY, M6_AXIS_TLAST => M6_AXIS_TLAST, M6_AXIS_TDATA => M6_AXIS_TDATA, M6_AXIS_TVALID => M6_AXIS_TVALID, M6_AXIS_TREADY => M6_AXIS_TREADY, S6_AXIS_TLAST => S6_AXIS_TLAST, S6_AXIS_TDATA => S6_AXIS_TDATA, S6_AXIS_TVALID => S6_AXIS_TVALID, S6_AXIS_TREADY => S6_AXIS_TREADY, M7_AXIS_TLAST => M7_AXIS_TLAST, M7_AXIS_TDATA => M7_AXIS_TDATA, M7_AXIS_TVALID => M7_AXIS_TVALID, M7_AXIS_TREADY => M7_AXIS_TREADY, S7_AXIS_TLAST => S7_AXIS_TLAST, S7_AXIS_TDATA => S7_AXIS_TDATA, S7_AXIS_TVALID => S7_AXIS_TVALID, S7_AXIS_TREADY => S7_AXIS_TREADY, M8_AXIS_TLAST => M8_AXIS_TLAST, M8_AXIS_TDATA => M8_AXIS_TDATA, M8_AXIS_TVALID => M8_AXIS_TVALID, M8_AXIS_TREADY => M8_AXIS_TREADY, S8_AXIS_TLAST => S8_AXIS_TLAST, S8_AXIS_TDATA => S8_AXIS_TDATA, S8_AXIS_TVALID => S8_AXIS_TVALID, S8_AXIS_TREADY => S8_AXIS_TREADY, M9_AXIS_TLAST => M9_AXIS_TLAST, M9_AXIS_TDATA => M9_AXIS_TDATA, M9_AXIS_TVALID => M9_AXIS_TVALID, M9_AXIS_TREADY => M9_AXIS_TREADY, S9_AXIS_TLAST => S9_AXIS_TLAST, S9_AXIS_TDATA => S9_AXIS_TDATA, S9_AXIS_TVALID => S9_AXIS_TVALID, S9_AXIS_TREADY => S9_AXIS_TREADY, M10_AXIS_TLAST => M10_AXIS_TLAST, M10_AXIS_TDATA => M10_AXIS_TDATA, M10_AXIS_TVALID => M10_AXIS_TVALID, M10_AXIS_TREADY => M10_AXIS_TREADY, S10_AXIS_TLAST => S10_AXIS_TLAST, S10_AXIS_TDATA => S10_AXIS_TDATA, S10_AXIS_TVALID => S10_AXIS_TVALID, S10_AXIS_TREADY => S10_AXIS_TREADY, M11_AXIS_TLAST => M11_AXIS_TLAST, M11_AXIS_TDATA => M11_AXIS_TDATA, M11_AXIS_TVALID => M11_AXIS_TVALID, M11_AXIS_TREADY => M11_AXIS_TREADY, S11_AXIS_TLAST => S11_AXIS_TLAST, S11_AXIS_TDATA => S11_AXIS_TDATA, S11_AXIS_TVALID => S11_AXIS_TVALID, S11_AXIS_TREADY => S11_AXIS_TREADY, M12_AXIS_TLAST => M12_AXIS_TLAST, M12_AXIS_TDATA => M12_AXIS_TDATA, M12_AXIS_TVALID => M12_AXIS_TVALID, M12_AXIS_TREADY => M12_AXIS_TREADY, S12_AXIS_TLAST => S12_AXIS_TLAST, S12_AXIS_TDATA => S12_AXIS_TDATA, S12_AXIS_TVALID => S12_AXIS_TVALID, S12_AXIS_TREADY => S12_AXIS_TREADY, M13_AXIS_TLAST => M13_AXIS_TLAST, M13_AXIS_TDATA => M13_AXIS_TDATA, M13_AXIS_TVALID => M13_AXIS_TVALID, M13_AXIS_TREADY => M13_AXIS_TREADY, S13_AXIS_TLAST => S13_AXIS_TLAST, S13_AXIS_TDATA => S13_AXIS_TDATA, S13_AXIS_TVALID => S13_AXIS_TVALID, S13_AXIS_TREADY => S13_AXIS_TREADY, M14_AXIS_TLAST => M14_AXIS_TLAST, M14_AXIS_TDATA => M14_AXIS_TDATA, M14_AXIS_TVALID => M14_AXIS_TVALID, M14_AXIS_TREADY => M14_AXIS_TREADY, S14_AXIS_TLAST => S14_AXIS_TLAST, S14_AXIS_TDATA => S14_AXIS_TDATA, S14_AXIS_TVALID => S14_AXIS_TVALID, S14_AXIS_TREADY => S14_AXIS_TREADY, M15_AXIS_TLAST => M15_AXIS_TLAST, M15_AXIS_TDATA => M15_AXIS_TDATA, M15_AXIS_TVALID => M15_AXIS_TVALID, M15_AXIS_TREADY => M15_AXIS_TREADY, S15_AXIS_TLAST => S15_AXIS_TLAST, S15_AXIS_TDATA => S15_AXIS_TDATA, S15_AXIS_TVALID => S15_AXIS_TVALID, S15_AXIS_TREADY => S15_AXIS_TREADY, ICACHE_FSL_IN_CLK => ICACHE_FSL_IN_CLK, ICACHE_FSL_IN_READ => ICACHE_FSL_IN_READ, ICACHE_FSL_IN_DATA => ICACHE_FSL_IN_DATA, ICACHE_FSL_IN_CONTROL => ICACHE_FSL_IN_CONTROL, ICACHE_FSL_IN_EXISTS => ICACHE_FSL_IN_EXISTS, ICACHE_FSL_OUT_CLK => ICACHE_FSL_OUT_CLK, ICACHE_FSL_OUT_WRITE => ICACHE_FSL_OUT_WRITE, ICACHE_FSL_OUT_DATA => ICACHE_FSL_OUT_DATA, ICACHE_FSL_OUT_CONTROL => ICACHE_FSL_OUT_CONTROL, ICACHE_FSL_OUT_FULL => ICACHE_FSL_OUT_FULL, DCACHE_FSL_IN_CLK => DCACHE_FSL_IN_CLK, DCACHE_FSL_IN_READ => DCACHE_FSL_IN_READ, DCACHE_FSL_IN_DATA => DCACHE_FSL_IN_DATA, DCACHE_FSL_IN_CONTROL => DCACHE_FSL_IN_CONTROL, DCACHE_FSL_IN_EXISTS => DCACHE_FSL_IN_EXISTS, DCACHE_FSL_OUT_CLK => DCACHE_FSL_OUT_CLK, DCACHE_FSL_OUT_WRITE => DCACHE_FSL_OUT_WRITE, DCACHE_FSL_OUT_DATA => DCACHE_FSL_OUT_DATA, DCACHE_FSL_OUT_CONTROL => DCACHE_FSL_OUT_CONTROL, DCACHE_FSL_OUT_FULL => DCACHE_FSL_OUT_FULL ); end architecture STRUCTURE;
lgpl-3.0
da5f242e2bd715ec064a4fb10cd84700
0.606549
2.748206
false
false
false
false
grwlf/vsim
vhdl_ct/ct00066.vhd
1
5,954
-- NEED RESULT: ARCH00066.P1_1: exit with no label or condition only effects innermost (labeled) loop passed -- NEED RESULT: ARCH00066.P1_1: exit with no label or condition only effects innermost (unlabeled) loop passed -- NEED RESULT: ARCH00066.P1_1: exit with no label or condition only effects innermost (unlabeled) loop passed -- NEED RESULT: ARCH00066.P1_1: exit with no label or condition only effects innermost (labeled) loop passed -- NEED RESULT: ARCH00066.P1_1: exit with no label or condition only effects innermost (unlabeled) loop passed -- NEED RESULT: ARCH00066.P1_1: exit with no label or condition only effects innermost (unlabeled) loop passed -- NEED RESULT: ARCH00066.P1_1: exit statement does not effect outer loop passed -- NEED RESULT: ARCH00066.P1_2: exit with no label only effects innermost (unlabeled) loop passed -- NEED RESULT: ARCH00066.P1_2: exit with no label only effects innermost (labeled) loop passed -- NEED RESULT: ARCH00066.P1_2: exit with no label only effects innermost (labeled) loop passed -- NEED RESULT: ARCH00066.P1_2: exit statement does not effect outer loop passed ------------------------------------------------------------------------------- -- -- Copyright (c) 1989 by Intermetrics, Inc. -- All rights reserved. -- ------------------------------------------------------------------------------- -- -- TEST NAME: -- -- CT00066 -- -- AUTHOR: -- -- G. Tominovich -- -- TEST OBJECTIVES: -- -- 8.10 (1) -- 8.10 (3) -- 8.10 (4) -- -- DESIGN UNIT ORDERING: -- -- E00000(ARCH00066) -- ENT00066_Test_Bench(ARCH00066_Test_Bench) -- -- REVISION HISTORY: -- -- 06-JUL-1987 - initial revision -- -- NOTES: -- -- self-checking -- automatically generated -- use WORK.STANDARD_TYPES.all ; architecture ARCH00066 of E00000 is signal Dummy : Boolean := false ; begin P1_1 : process ( Dummy ) variable correct : boolean ; variable counter : integer := 0 ; variable done : boolean := false ; begin L1 : for i in boolean loop -- correct := true ; L2 : for j in 1 to 3 loop correct := (j = 1) and correct ; exit ; correct := false ; end loop L2 ; -- test_report ( "ARCH00066.P1_1" , "exit with no label or condition only effects " & "innermost (labeled) loop", correct ) ; -- correct := true ; while not done loop correct := (not done) and correct ; done := true ; exit ; correct := false ; end loop ; -- test_report ( "ARCH00066.P1_1" , "exit with no label or condition only effects " & "innermost (unlabeled) loop", correct ) ; -- correct := true ; done := false ; loop correct := (not done) and correct ; done := true ; exit ; correct := false ; end loop ; -- test_report ( "ARCH00066.P1_1" , "exit with no label or condition only effects " & "innermost (unlabeled) loop", correct ) ; -- counter := counter + 1 ; -- end loop L1 ; correct := counter = (boolean'Pos (boolean'High) - boolean'Pos (boolean'Low) + 1) ; test_report ( "ARCH00066.P1_1" , "exit statement does not effect outer " & "loop", correct ) ; -- end process P1_1 ; -- P1_2 : process ( Dummy ) variable correct : boolean := true ; variable counter : integer := 0 ; variable done : boolean := false ; variable v_boolean : boolean := c_boolean_1 ; -- begin L1 : while v_boolean /= boolean'High loop -- correct := true ; for j in 1 to 3 loop correct := correct and (j = 1) ; exit when j = j ; correct := false ; end loop ; -- test_report ( "ARCH00066.P1_2" , "exit with no label only effects " & "innermost (unlabeled) loop", correct ) ; -- correct := true ; L2 : while not done loop correct := (not done) and correct ; done := true ; exit when done = done ; correct := false ; end loop L2 ; -- test_report ( "ARCH00066.P1_2" , "exit with no label only effects " & "innermost (labeled) loop", correct ) ; -- correct := true ; done := false ; L3 : loop correct := (not done) and correct ; done := true ; exit when done = done ; correct := false ; end loop L3 ; -- test_report ( "ARCH00066.P1_2" , "exit with no label only effects " & "innermost (labeled) loop", correct ) ; -- v_boolean := boolean'Succ (v_boolean) ; counter := counter + 1 ; -- end loop L1 ; correct := counter = (boolean'Pos (boolean'High) - boolean'Pos (c_boolean_1) ) ; test_report ( "ARCH00066.P1_2" , "exit statement does not effect outer " & "loop", correct ) ; -- end process P1_2 ; -- -- end ARCH00066 ; -- entity ENT00066_Test_Bench is end ENT00066_Test_Bench ; -- architecture ARCH00066_Test_Bench of ENT00066_Test_Bench is begin L1: block component UUT end component ; for CIS1 : UUT use entity WORK.E00000 ( ARCH00066 ) ; begin CIS1 : UUT ; end block L1 ; end ARCH00066_Test_Bench ;
gpl-3.0
a4cb97b7256375c83499ef5ea7e3d04f
0.50655
3.987944
false
true
false
false
dcliche/mdsynth
rtl/src/mdsynth.vhd
1
24,953
-- MDSynth Top Level -- -- Authors : John E. Kent ([email protected]) -- Daniel Cliche ([email protected]) -- -- Copyright (C) 2003 - 2010 John Kent -- Copyright (C) 2011 Meldora Inc. -- -- This program is free software: you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by -- the Free Software Foundation, either version 3 of the License, or -- (at your option) any later version. -- -- This program is distributed in the hope that it will be useful, -- but WITHOUT ANY WARRANTY; without even the implied warranty of -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -- GNU General Public License for more details. -- -- You should have received a copy of the GNU General Public License -- along with this program. If not, see <http://www.gnu.org/licenses/>. -- -- Memory Map : -- -- $0000 - $7FFF System Block RAM -- $E000 - ACIA (SWTPc) -- $E010 - MIDI ACIA -- $E020 - Keyboard -- $E030 - VDU -- $E040 - Reserved for SWTPc MP-T (was Compact Flash) -- $E050 - Timer -- $E060 - Bus Trap (Hardware Breakpoint Interrupt Logic) -- $E070 - PIA Single Step Timer (was Reserved for Trace Buffer) -- $E080 - Sound Voice 0 -- $E090 - Sound Voice 1 -- $E0A0 - Sound Voice 2 -- $E0B0 - Sound Voice 3 -- $E0C0 - Reserved -- $E100 - $E13F Reserved IDE / Compact Flash Card -- $E140 - $E17F Reserved for Ethernet MAC (XESS) -- $E180 - $E1BF Reserved for Expansion Slot 0 (XESS) -- $E1C0 - $E1FF Reserved for Expansion Slot 1 (XESS) -- $E200 - $EFFF Dual Port RAM interface -- $F000 - $F7FF Reserved SWTPc DMAF-2 -- $F800 - $FFFF Sys09bug ROM (Read only) -- $FFF0 - $FFFF Reserved for DAT - Dynamic Address Translation (Write Only) library ieee; use ieee.std_logic_1164.all; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; use ieee.numeric_std.all; entity mdsynth is port( CLK_50MHZ : in Std_Logic; -- System Clock input BTN_SOUTH : in Std_Logic; -- PS/2 Keyboard PS2_CLK : inout Std_logic; PS2_DATA : inout Std_Logic; -- CRTC output signals VGA_VSYNC : out Std_Logic; VGA_HSYNC : out Std_Logic; VGA_B : out std_logic_vector(3 downto 0); VGA_G : out std_logic_vector(3 downto 0); VGA_R : out std_logic_vector(3 downto 0); -- Uart Interface RS232_DCE_RXD : in std_logic; RS232_DCE_TXD : out std_logic; -- MIDI Interface MIDI_RS232_DCE_RXD : in std_logic; MIDI_RS232_DCE_TXD : out std_logic; -- LEDS & Switches LED : out std_logic_vector(7 downto 0); -- Audio AUD_L : out std_logic; AUD_R : out std_logic; AUX_AUD_L : out std_logic; AUX_AUD_R : out std_logic ); end mdsynth; ------------------------------------------------------------------------------- -- Architecture for System09 ------------------------------------------------------------------------------- architecture my_computer of mdsynth is ----------------------------------------------------------------------------- -- constants ----------------------------------------------------------------------------- constant SYS_CLK_FREQ : integer := 50000000; -- FPGA System Clock constant VGA_CLK_FREQ : integer := 25000000; -- VGA Pixel Clock constant CPU_CLK_FREQ : integer := 25000000; -- CPU Clock constant BAUD_RATE : integer := 57600; -- Baud Rate constant ACIA_CLK_FREQ : integer := BAUD_RATE * 16; constant MIDI_BAUD_RATE : integer := 31250; -- MIDI Baud Rate constant MIDI_ACIA_CLK_FREQ : integer := MIDI_BAUD_RATE * 16; ----------------------------------------------------------------------------- -- Signals ----------------------------------------------------------------------------- -- Clocks signal sys_clk : std_logic; signal vga_clk : std_logic; -- BOOT ROM signal rom_cs : Std_logic; signal rom_data_out : Std_Logic_Vector(7 downto 0); -- UART Interface signals signal uart_data_out : Std_Logic_Vector(7 downto 0); signal uart_cs : Std_Logic; signal uart_irq : Std_Logic; signal uart_clk : Std_Logic; -- MIDI UART Interface signals signal midi_uart_data_out : Std_Logic_Vector(7 downto 0); signal midi_uart_cs : Std_Logic; signal midi_uart_irq : Std_Logic; signal midi_uart_clk : Std_Logic; -- timer signal timer_data_out : std_logic_vector(7 downto 0); signal timer_cs : std_logic; signal timer_irq : std_logic; -- trap signal trap_cs : std_logic; signal trap_data_out : std_logic_vector(7 downto 0); signal trap_irq : std_logic; -- PIA Interface signals signal pia_data_out : Std_Logic_Vector(7 downto 0); signal pia_cs : Std_Logic; signal pia_irq_a : Std_Logic; signal pia_irq_b : Std_Logic; -- keyboard port signal kbd_data_out : std_logic_vector(7 downto 0); signal kbd_cs : std_logic; signal kbd_irq : std_logic; -- Video Display Unit signal vdu_cs : std_logic; signal vdu_data_out : std_logic_vector(7 downto 0); signal vga_blue : std_logic; signal vga_green : std_logic; signal vga_red : std_logic; -- Sound signal sound_cs : std_logic; signal sound_data_out : std_logic_vector(7 downto 0); -- RAM signal ram_cs : std_logic; -- memory chip select signal ram_data_out : std_logic_vector(7 downto 0); -- CPU Interface signals signal cpu_rst : Std_Logic; signal cpu_clk : Std_Logic; signal cpu_rw : std_logic; signal cpu_vma : std_logic; signal cpu_halt : std_logic; signal cpu_hold : std_logic; signal cpu_firq : std_logic; signal cpu_irq : std_logic; signal cpu_nmi : std_logic; signal cpu_addr : std_logic_vector(15 downto 0); signal cpu_data_in : std_logic_vector(7 downto 0); signal cpu_data_out : std_logic_vector(7 downto 0); signal audio_left : std_logic; signal audio_right : std_logic; ----------------------------------------------------------------- -- -- Clock generator -- ----------------------------------------------------------------- component clock_div port( clk_in : in std_Logic; -- System Clock input sys_clk : out std_logic; -- System Clock Out (1/1) vga_clk : out std_logic; -- VGA Pixel Clock Out (1/2) cpu_clk : out std_logic -- CPU Clock Out (1/4) ); end component; ----------------------------------------------------------------- -- -- LED Flasher -- ----------------------------------------------------------------- component flasher port ( clk : in std_logic; -- Clock input rst : in std_logic; -- Reset input (active high) LED : out Std_Logic -- LED output ); end component; ----------------------------------------------------------------- -- -- CPU09 CPU core -- ----------------------------------------------------------------- component cpu09 port ( clk : in std_logic; rst : in std_logic; vma : out std_logic; addr : out std_logic_vector(15 downto 0); rw : out std_logic; data_out : out std_logic_vector(7 downto 0); data_in : in std_logic_vector(7 downto 0); irq : in std_logic; nmi : in std_logic; firq : in std_logic; halt : in std_logic; hold : in std_logic ); end component; ---------------------------------------- -- -- Block RAM Monitor ROM -- ---------------------------------------- component mon_rom Port ( clk : in std_logic; rst : in std_logic; cs : in std_logic; rw : in std_logic; addr : in std_logic_vector (10 downto 0); data_in : in std_logic_vector (7 downto 0); data_out : out std_logic_vector (7 downto 0) ); end component; ---------------------------------------- -- -- Block RAM Monitor -- ---------------------------------------- component ram_32k Port ( clk : in std_logic; rst : in std_logic; cs : in std_logic; addr : in std_logic_vector (14 downto 0); rw : in std_logic; data_in : in std_logic_vector (7 downto 0); data_out : out std_logic_vector (7 downto 0) ); end component; ----------------------------------------------------------------- -- -- 6822 compatible PIA with counters -- ----------------------------------------------------------------- component pia_timer port ( clk : in std_logic; rst : in std_logic; cs : in std_logic; addr : in std_logic_vector(1 downto 0); rw : in std_logic; data_in : in std_logic_vector(7 downto 0); data_out : out std_logic_vector(7 downto 0); irqa : out std_logic; irqb : out std_logic ); end component; ----------------------------------------------------------------- -- -- 6850 ACIA/UART -- ----------------------------------------------------------------- component acia6850 port ( clk : in Std_Logic; -- System Clock rst : in Std_Logic; -- Reset input (active high) cs : in Std_Logic; -- miniUART Chip Select rw : in Std_Logic; -- Read / Not Write addr : in Std_Logic; -- Register Select data_in : in Std_Logic_Vector(7 downto 0); -- Data Bus In data_out : out Std_Logic_Vector(7 downto 0); -- Data Bus Out irq : out Std_Logic; -- Interrupt RxC : in Std_Logic; -- Receive Baud Clock TxC : in Std_Logic; -- Transmit Baud Clock RxD : in Std_Logic; -- Receive Data TxD : out Std_Logic; -- Transmit Data DCD_n : in Std_Logic; -- Data Carrier Detect CTS_n : in Std_Logic; -- Clear To Send RTS_n : out Std_Logic ); -- Request To send end component; ----------------------------------------------------------------- -- -- ACIA Clock divider -- ----------------------------------------------------------------- component ACIA_Clock generic ( SYS_CLK_FREQ : integer := SYS_CLK_FREQ; ACIA_CLK_FREQ : integer := ACIA_CLK_FREQ ); port ( clk : in Std_Logic; -- System Clock Input ACIA_clk : out Std_logic -- ACIA Clock output ); end component; ---------------------------------------- -- -- Timer module -- ---------------------------------------- component timer port ( clk : in std_logic; rst : in std_logic; cs : in std_logic; addr : in std_logic; rw : in std_logic; data_in : in std_logic_vector(7 downto 0); data_out : out std_logic_vector(7 downto 0); irq : out std_logic ); end component; ------------------------------------------------------------ -- -- Bus Trap logic -- ------------------------------------------------------------ component trap port ( clk : in std_logic; rst : in std_logic; cs : in std_logic; vma : in std_logic; rw : in std_logic; addr : in std_logic_vector(15 downto 0); data_in : in std_logic_vector(7 downto 0); data_out : out std_logic_vector(7 downto 0); irq : out std_logic ); end component; ---------------------------------------- -- -- PS/2 Keyboard -- ---------------------------------------- component keyboard generic( KBD_CLK_FREQ : integer := CPU_CLK_FREQ ); port( clk : in std_logic; rst : in std_logic; cs : in std_logic; addr : in std_logic; rw : in std_logic; data_in : in std_logic_vector(7 downto 0); data_out : out std_logic_vector(7 downto 0); irq : out std_logic; kbd_clk : inout std_logic; kbd_data : inout std_logic ); end component; ---------------------------------------- -- -- Video Display Unit. -- ---------------------------------------- component vdu8 generic( VGA_CLK_FREQ : integer := VGA_CLK_FREQ; -- 25MHz VGA_HOR_CHARS : integer := 80; -- CHARACTERS 25.6us VGA_HOR_CHAR_PIXELS : integer := 8; -- PIXELS 0.32us VGA_HOR_FRONT_PORCH : integer := 16; -- PIXELS 0.64us (0.94us) VGA_HOR_SYNC : integer := 96; -- PIXELS 3.84us (3.77us) VGA_HOR_BACK_PORCH : integer := 48; -- PIXELS 1.92us (1.89us) VGA_VER_CHARS : integer := 25; -- CHARACTERS 12.8ms VGA_VER_CHAR_LINES : integer := 16; -- LINES 0.512ms VGA_VER_FRONT_PORCH : integer := 10; -- LINES 0.320ms VGA_VER_SYNC : integer := 2; -- LINES 0.064ms VGA_VER_BACK_PORCH : integer := 34 -- LINES 1.088ms ); port( -- control register interface vdu_clk : in std_logic; -- CPU Clock - 12.5MHz vdu_rst : in std_logic; vdu_cs : in std_logic; vdu_rw : in std_logic; vdu_addr : in std_logic_vector(2 downto 0); vdu_data_in : in std_logic_vector(7 downto 0); vdu_data_out : out std_logic_vector(7 downto 0); -- vga port connections vga_clk : in std_logic; -- VGA Pixel Clock - 25 MHz vga_red_o : out std_logic; vga_green_o : out std_logic; vga_blue_o : out std_logic; vga_hsync_o : out std_logic; vga_vsync_o : out std_logic ); end component; ---------------------------------------- -- -- Sound -- ---------------------------------------- component sound is port ( clk : in std_logic; clk_50 : in std_logic; rst : in std_logic; cs : in std_logic; addr : in std_logic_vector(5 downto 0); rw : in std_logic; data_in : in std_logic_vector(7 downto 0); data_out : out std_logic_vector(7 downto 0); audio_out : out std_logic ); end component; begin ----------------------------------------------------------------------------- -- Instantiation of internal components ----------------------------------------------------------------------------- ---------------------------------------- -- -- Clock generator -- ---------------------------------------- my_clock_div: clock_div port map ( clk_in => CLK_50MHZ, -- Clock input sys_clk => sys_clk, -- System Clock Out (1/1) vga_clk => vga_clk, -- CPU/VGA Pixel Clock Out (1/2) cpu_clk => open -- (1/4) ); ----------------------------------------- -- -- LED Flasher -- ----------------------------------------- my_LED_flasher : flasher port map ( clk => cpu_clk, rst => cpu_rst, LED => LED(0) ); ---------------------------------------- -- -- 6809 compatible CPU -- ---------------------------------------- my_cpu : cpu09 port map ( clk => cpu_clk, rst => cpu_rst, vma => cpu_vma, addr => cpu_addr(15 downto 0), rw => cpu_rw, data_out => cpu_data_out, data_in => cpu_data_in, irq => cpu_irq, nmi => cpu_nmi, firq => cpu_firq, halt => cpu_halt, hold => cpu_hold ); my_rom : mon_rom port map ( clk => cpu_clk, rst => cpu_rst, cs => rom_cs, addr => cpu_addr(10 downto 0), rw => '1', data_in => cpu_data_out, data_out => rom_data_out ); my_ram : ram_32k port map ( clk => cpu_clk, rst => cpu_rst, cs => ram_cs, addr => cpu_addr(14 downto 0), rw => cpu_rw, data_in => cpu_data_out, data_out => ram_data_out ); my_pia : pia_timer port map ( clk => cpu_clk, rst => cpu_rst, cs => pia_cs, addr => cpu_addr(1 downto 0), rw => cpu_rw, data_in => cpu_data_out, data_out => pia_data_out, irqa => pia_irq_a, irqb => pia_irq_b ); ---------------------------------------- -- -- ACIA/UART Serial interface -- ---------------------------------------- my_ACIA : acia6850 port map ( clk => cpu_clk, rst => cpu_rst, cs => uart_cs, addr => cpu_addr(0), rw => cpu_rw, data_in => cpu_data_out, data_out => uart_data_out, irq => uart_irq, RxC => uart_clk, TxC => uart_clk, RxD => RS232_DCE_RXD, TxD => RS232_DCE_TXD, DCD_n => '0', CTS_n => '0', RTS_n => open ); ---------------------------------------- -- -- MIDI ACIA/UART Serial interface -- ---------------------------------------- my_MIDI_ACIA : acia6850 port map ( clk => cpu_clk, rst => cpu_rst, cs => midi_uart_cs, addr => cpu_addr(0), rw => cpu_rw, data_in => cpu_data_out, data_out => midi_uart_data_out, irq => midi_uart_irq, RxC => midi_uart_clk, TxC => midi_uart_clk, RxD => MIDI_RS232_DCE_RXD, TxD => MIDI_RS232_DCE_TXD, DCD_n => '0', CTS_n => '0', RTS_n => open ); ---------------------------------------- -- -- ACIA Clock -- ---------------------------------------- my_ACIA_Clock : ACIA_Clock generic map( SYS_CLK_FREQ => SYS_CLK_FREQ, ACIA_CLK_FREQ => ACIA_CLK_FREQ ) port map( clk => sys_clk, acia_clk => uart_clk ); ---------------------------------------- -- -- MIDI ACIA Clock -- ---------------------------------------- my_MIDI_ACIA_Clock : ACIA_Clock generic map( SYS_CLK_FREQ => SYS_CLK_FREQ, ACIA_CLK_FREQ => MIDI_ACIA_CLK_FREQ ) port map( clk => sys_clk, acia_clk => midi_uart_clk ); ---------------------------------------- -- -- PS/2 Keyboard Interface -- ---------------------------------------- my_keyboard : keyboard generic map ( KBD_CLK_FREQ => CPU_CLK_FREQ ) port map( clk => cpu_clk, rst => cpu_rst, cs => kbd_cs, addr => cpu_addr(0), rw => cpu_rw, data_in => cpu_data_out(7 downto 0), data_out => kbd_data_out(7 downto 0), irq => kbd_irq, kbd_clk => PS2_CLK, kbd_data => PS2_DATA ); ---------------------------------------- -- -- Video Display Unit instantiation -- ---------------------------------------- my_vdu : vdu8 generic map( VGA_CLK_FREQ => VGA_CLK_FREQ, -- HZ VGA_HOR_CHARS => 80, -- CHARACTERS VGA_HOR_CHAR_PIXELS => 8, -- PIXELS VGA_HOR_FRONT_PORCH => 16, -- PIXELS VGA_HOR_SYNC => 96, -- PIXELS VGA_HOR_BACK_PORCH => 48, -- PIXELS VGA_VER_CHARS => 25, -- CHARACTERS VGA_VER_CHAR_LINES => 16, -- LINES VGA_VER_FRONT_PORCH => 10, -- LINES VGA_VER_SYNC => 2, -- LINES VGA_VER_BACK_PORCH => 34 -- LINES ) port map( -- Control Registers vdu_clk => cpu_clk, -- 25 MHz System Clock in vdu_rst => cpu_rst, vdu_cs => vdu_cs, vdu_addr => cpu_addr(2 downto 0), vdu_rw => cpu_rw, vdu_data_in => cpu_data_out, vdu_data_out => vdu_data_out, -- vga port connections vga_clk => vga_clk, -- 25 MHz VDU pixel clock vga_red_o => vga_red, vga_green_o => vga_green, vga_blue_o => vga_blue, vga_hsync_o => vga_hsync, vga_vsync_o => vga_vsync ); ---------------------------------------- -- -- Timer Module -- ---------------------------------------- my_timer : timer port map ( clk => cpu_clk, rst => cpu_rst, cs => timer_cs, rw => cpu_rw, addr => cpu_addr(0), data_in => cpu_data_out, data_out => timer_data_out, irq => timer_irq ); ---------------------------------------- -- -- Bus Trap Interrupt logic -- ---------------------------------------- my_trap : trap port map ( clk => cpu_clk, rst => cpu_rst, cs => trap_cs, rw => cpu_rw, vma => cpu_vma, addr => cpu_addr, data_in => cpu_data_out, data_out => trap_data_out, irq => trap_irq ); ---------------------------------------- -- -- Sound -- ---------------------------------------- my_sound : sound port map ( clk => cpu_clk, clk_50 => sys_clk, rst => cpu_rst, cs => sound_cs, addr => cpu_addr(5 downto 0), rw => cpu_rw, data_in => cpu_data_out, data_out => sound_data_out, audio_out => audio_left ); vga_colors: process(vga_red, vga_green, vga_blue) begin vga_r <= vga_red & vga_red & vga_red & vga_red; vga_g <= vga_green & vga_green & vga_green & vga_green; vga_b <= vga_blue & vga_blue & vga_blue & vga_blue; end process; ---------------------------------------------------------------------- -- -- Process to decode memory map -- ---------------------------------------------------------------------- mem_decode: process( cpu_addr, cpu_rw, cpu_vma, rom_data_out, ram_data_out, timer_data_out, trap_data_out, pia_data_out, uart_data_out, kbd_data_out, vdu_data_out ) begin rom_cs <= '0'; ram_cs <= '0'; uart_cs <= '0'; midi_uart_cs <= '0'; timer_cs <= '0'; trap_cs <= '0'; pia_cs <= '0'; kbd_cs <= '0'; vdu_cs <= '0'; sound_cs <= '0'; case cpu_addr(15 downto 12) is -- -- SBUG/KBUG/SYS09BUG Monitor ROM $F800 - $FFFF -- when "1111" => -- $F000 - $FFFF cpu_data_in <= rom_data_out; rom_cs <= cpu_vma; -- read ROM -- -- IO Devices $E000 - $EFFF -- when "1110" => -- $E000 - $E7FF case cpu_addr(7 downto 4) is -- -- UART / ACIA $E000 -- when "0000" => -- $E000 cpu_data_in <= uart_data_out; uart_cs <= cpu_vma; -- -- MIDI UART / ACIA $E010-$E01F -- when "0001" => -- $E010 cpu_data_in <= midi_uart_data_out; midi_uart_cs <= cpu_vma; -- -- Keyboard port $E020 - $E02F -- when "0010" => -- $E020 cpu_data_in <= kbd_data_out; kbd_cs <= cpu_vma; -- -- VDU port $E030 - $E03F -- when "0011" => -- $E030 cpu_data_in <= vdu_data_out; vdu_cs <= cpu_vma; -- -- Compact Flash $E040 - $E04F -- when "0100" => -- $E040 cpu_data_in <= (others => '0'); -- -- Timer $E050 - $E05F -- when "0101" => -- $E050 cpu_data_in <= timer_data_out; timer_cs <= cpu_vma; -- -- Bus Trap Logic $E060 - $E06F -- when "0110" => -- $E060 cpu_data_in <= trap_data_out; trap_cs <= cpu_vma; -- -- PIA Timer $E070 - $E07F -- when "0111" => -- $E070 cpu_data_in <= pia_data_out; pia_cs <= cpu_vma; -- -- Sound $E080 - $E09F -- when "1000" => -- $E080 -- voice 0 cpu_data_in <= sound_data_out; sound_cs <= cpu_vma; when "1001" => -- $E090 -- voice 1 cpu_data_in <= sound_data_out; sound_cs <= cpu_vma; when "1010" => -- $E0A0 -- voice 2 cpu_data_in <= sound_data_out; sound_cs <= cpu_vma; when "1011" => -- $E0B0 -- voice 3 cpu_data_in <= sound_data_out; sound_cs <= cpu_vma; when others => -- $E0D0 to $E7FF cpu_data_in <= (others => '0'); end case; -- -- $8000 to $DFFF = null -- when "1101" | "1100" | "1011" | "1010" | "1001" | "1000" => cpu_data_in <= (others => '0'); -- -- Everything else is RAM -- when others => cpu_data_in <= ram_data_out; ram_cs <= cpu_vma; end case; end process; -- -- Assign CPU clock, reset, interrupt, halt & hold signals -- as well as LED signals -- assign_signals : process( vga_clk, BTN_SOUTH, pia_irq_a, pia_irq_b, uart_irq, midi_uart_irq, trap_irq, timer_irq, kbd_irq ) begin cpu_clk <= vga_clk; cpu_rst <= BTN_SOUTH; -- CPU reset is active high cpu_irq <= uart_irq or midi_uart_irq or kbd_irq; cpu_nmi <= pia_irq_a or trap_irq; cpu_firq <= pia_irq_b or timer_irq; cpu_halt <= '0'; cpu_hold <= '0'; -- LED outputs LED(7 downto 1) <= (others=>'1'); end process; process(audio_left, audio_right) begin aud_l <= audio_left; aud_r <= audio_left; aux_aud_l <= audio_left; aux_aud_r <= audio_left; end process; end my_computer; --===================== End of architecture =======================--
gpl-3.0
77a74b55072818b870b6222c26aedad6
0.458302
3.429966
false
false
false
false
grwlf/vsim
vhdl_ct/ct00619.vhd
1
11,470
-- NEED RESULT: ARCH00619: Concurrent proc call 1 passed -- NEED RESULT: ARCH00619: Concurrent proc call 1 passed -- NEED RESULT: ARCH00619.P1: Multi transport transactions occurred on concurrent signal asg passed -- NEED RESULT: ARCH00619.P2: Multi transport transactions occurred on concurrent signal asg passed -- NEED RESULT: ARCH00619: Concurrent proc call 2 passed -- NEED RESULT: ARCH00619: Concurrent proc call 2 passed -- NEED RESULT: ARCH00619: One transport transaction occurred on a concurrent signal asg passed -- NEED RESULT: ARCH00619: Old transactions were removed on a concurrent signal asg passed -- NEED RESULT: ARCH00619: One transport transaction occurred on a concurrent signal asg passed -- NEED RESULT: ARCH00619: Old transactions were removed on a concurrent signal asg passed -- NEED RESULT: P2: Transport transactions completed entirely passed -- NEED RESULT: P1: Transport transactions completed entirely passed ------------------------------------------------------------------------------- -- -- Copyright (c) 1989 by Intermetrics, Inc. -- All rights reserved. -- ------------------------------------------------------------------------------- -- -- TEST NAME: -- -- CT00619 -- -- AUTHOR: -- -- G. Tominovich -- -- TEST OBJECTIVES: -- -- 9.3 (3) -- -- DESIGN UNIT ORDERING: -- -- ENT00619(ARCH00619) -- ENT00619_Test_Bench(ARCH00619_Test_Bench) -- -- REVISION HISTORY: -- -- 24-AUG-1987 - initial revision -- -- NOTES: -- -- self-checking -- automatically generated -- use WORK.STANDARD_TYPES.all ; entity ENT00619 is end ENT00619 ; -- -- architecture ARCH00619 of ENT00619 is subtype chk_sig_type is integer range -1 to 100 ; signal chk_st_arr2_vector : chk_sig_type := -1 ; signal chk_st_arr3_vector : chk_sig_type := -1 ; -- subtype chk_time_type is Time ; signal s_st_arr2_vector_savt : chk_time_type := 0 ns ; signal s_st_arr3_vector_savt : chk_time_type := 0 ns ; -- subtype chk_cnt_type is Integer ; signal s_st_arr2_vector_cnt : chk_cnt_type := 0 ; signal s_st_arr3_vector_cnt : chk_cnt_type := 0 ; -- type select_type is range 1 to 3 ; signal st_arr2_vector_select : select_type := 1 ; signal st_arr3_vector_select : select_type := 1 ; -- signal s_st_arr2_vector : st_arr2_vector := c_st_arr2_vector_1 ; signal s_st_arr3_vector : st_arr3_vector := c_st_arr3_vector_1 ; -- procedure P1 (signal s_st_arr2_vector : in st_arr2_vector ; signal select_sig : out Select_Type ; signal savtime : out Chk_Time_Type ; signal chk_sig : out Chk_Sig_Type ; signal count : out Integer) is variable correct : boolean ; begin case s_st_arr2_vector_cnt is when 0 => null ; -- s_st_arr2_vector(lowb)(highb,false) <= transport -- c_st_arr2_vector_2(lowb)(highb,false) after 10 ns, -- c_st_arr2_vector_1(lowb)(highb,false) after 20 ns ; -- when 1 => correct := s_st_arr2_vector(lowb)(highb,false) = c_st_arr2_vector_2(lowb)(highb,false) and (s_st_arr2_vector_savt + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00619" , "Concurrent proc call 1", correct ) ; -- when 2 => correct := s_st_arr2_vector(lowb)(highb,false) = c_st_arr2_vector_1(lowb)(highb,false) and (s_st_arr2_vector_savt + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00619.P1" , "Multi transport transactions occurred on " & "concurrent signal asg", correct ) ; -- select_sig <= transport 2 ; -- s_st_arr2_vector(lowb)(highb,false) <= transport -- c_st_arr2_vector_2(lowb)(highb,false) after 10 ns , -- c_st_arr2_vector_1(lowb)(highb,false) after 20 ns , -- c_st_arr2_vector_2(lowb)(highb,false) after 30 ns , -- c_st_arr2_vector_1(lowb)(highb,false) after 40 ns ; -- when 3 => correct := s_st_arr2_vector(lowb)(highb,false) = c_st_arr2_vector_2(lowb)(highb,false) and (s_st_arr2_vector_savt + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00619" , "Concurrent proc call 2", correct ) ; select_sig <= transport 3 ; -- s_st_arr2_vector(lowb)(highb,false) <= transport -- c_st_arr2_vector_1(lowb)(highb,false) after 5 ns ; -- when 4 => correct := s_st_arr2_vector(lowb)(highb,false) = c_st_arr2_vector_1(lowb)(highb,false) and (s_st_arr2_vector_savt + 5 ns) = Std.Standard.Now ; test_report ( "ARCH00619" , "One transport transaction occurred on a " & "concurrent signal asg", correct ) ; test_report ( "ARCH00619" , "Old transactions were removed on a " & "concurrent signal asg", correct ) ; -- when others => -- No more transactions should have occurred test_report ( "ARCH00619" , "Old transactions were removed on a " & "concurrent signal asg", false ) ; -- end case ; -- savtime <= transport Std.Standard.Now ; chk_sig <= transport s_st_arr2_vector_cnt after (1 us - Std.Standard.Now) ; count <= transport s_st_arr2_vector_cnt + 1 ; -- end ; -- procedure P2 (signal s_st_arr3_vector : in st_arr3_vector ; signal select_sig : out Select_Type ; signal savtime : out Chk_Time_Type ; signal chk_sig : out Chk_Sig_Type ; signal count : out Integer) is variable correct : boolean ; begin case s_st_arr3_vector_cnt is when 0 => null ; -- s_st_arr3_vector(highb)(lowb,true) <= transport -- c_st_arr3_vector_2(highb)(lowb,true) after 10 ns, -- c_st_arr3_vector_1(highb)(lowb,true) after 20 ns ; -- when 1 => correct := s_st_arr3_vector(highb)(lowb,true) = c_st_arr3_vector_2(highb)(lowb,true) and (s_st_arr3_vector_savt + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00619" , "Concurrent proc call 1", correct ) ; -- when 2 => correct := s_st_arr3_vector(highb)(lowb,true) = c_st_arr3_vector_1(highb)(lowb,true) and (s_st_arr3_vector_savt + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00619.P2" , "Multi transport transactions occurred on " & "concurrent signal asg", correct ) ; -- select_sig <= transport 2 ; -- s_st_arr3_vector(highb)(lowb,true) <= transport -- c_st_arr3_vector_2(highb)(lowb,true) after 10 ns , -- c_st_arr3_vector_1(highb)(lowb,true) after 20 ns , -- c_st_arr3_vector_2(highb)(lowb,true) after 30 ns , -- c_st_arr3_vector_1(highb)(lowb,true) after 40 ns ; -- when 3 => correct := s_st_arr3_vector(highb)(lowb,true) = c_st_arr3_vector_2(highb)(lowb,true) and (s_st_arr3_vector_savt + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00619" , "Concurrent proc call 2", correct ) ; select_sig <= transport 3 ; -- s_st_arr3_vector(highb)(lowb,true) <= transport -- c_st_arr3_vector_1(highb)(lowb,true) after 5 ns ; -- when 4 => correct := s_st_arr3_vector(highb)(lowb,true) = c_st_arr3_vector_1(highb)(lowb,true) and (s_st_arr3_vector_savt + 5 ns) = Std.Standard.Now ; test_report ( "ARCH00619" , "One transport transaction occurred on a " & "concurrent signal asg", correct ) ; test_report ( "ARCH00619" , "Old transactions were removed on a " & "concurrent signal asg", correct ) ; -- when others => -- No more transactions should have occurred test_report ( "ARCH00619" , "Old transactions were removed on a " & "concurrent signal asg", false ) ; -- end case ; -- savtime <= transport Std.Standard.Now ; chk_sig <= transport s_st_arr3_vector_cnt after (1 us - Std.Standard.Now) ; count <= transport s_st_arr3_vector_cnt + 1 ; -- end ; -- begin CHG1 : P1( s_st_arr2_vector , st_arr2_vector_select , s_st_arr2_vector_savt , chk_st_arr2_vector , s_st_arr2_vector_cnt ) ; -- PGEN_CHKP_1 : process ( chk_st_arr2_vector ) begin if Std.Standard.Now > 0 ns then test_report ( "P1" , "Transport transactions completed entirely", chk_st_arr2_vector = 4 ) ; end if ; end process PGEN_CHKP_1 ; -- -- with st_arr2_vector_select select s_st_arr2_vector(lowb)(highb,false) <= transport c_st_arr2_vector_2(lowb)(highb,false) after 10 ns, c_st_arr2_vector_1(lowb)(highb,false) after 20 ns when 1, -- c_st_arr2_vector_2(lowb)(highb,false) after 10 ns , c_st_arr2_vector_1(lowb)(highb,false) after 20 ns , c_st_arr2_vector_2(lowb)(highb,false) after 30 ns , c_st_arr2_vector_1(lowb)(highb,false) after 40 ns when 2, -- c_st_arr2_vector_1(lowb)(highb,false) after 5 ns when 3 ; -- CHG2 : P2( s_st_arr3_vector , st_arr3_vector_select , s_st_arr3_vector_savt , chk_st_arr3_vector , s_st_arr3_vector_cnt ) ; -- PGEN_CHKP_2 : process ( chk_st_arr3_vector ) begin if Std.Standard.Now > 0 ns then test_report ( "P2" , "Transport transactions completed entirely", chk_st_arr3_vector = 4 ) ; end if ; end process PGEN_CHKP_2 ; -- -- with st_arr3_vector_select select s_st_arr3_vector(highb)(lowb,true) <= transport c_st_arr3_vector_2(highb)(lowb,true) after 10 ns, c_st_arr3_vector_1(highb)(lowb,true) after 20 ns when 1, -- c_st_arr3_vector_2(highb)(lowb,true) after 10 ns , c_st_arr3_vector_1(highb)(lowb,true) after 20 ns , c_st_arr3_vector_2(highb)(lowb,true) after 30 ns , c_st_arr3_vector_1(highb)(lowb,true) after 40 ns when 2, -- c_st_arr3_vector_1(highb)(lowb,true) after 5 ns when 3 ; -- end ARCH00619 ; -- -- use WORK.STANDARD_TYPES.all ; entity ENT00619_Test_Bench is end ENT00619_Test_Bench ; -- -- architecture ARCH00619_Test_Bench of ENT00619_Test_Bench is begin L1: block component UUT end component ; -- for CIS1 : UUT use entity WORK.ENT00619 ( ARCH00619 ) ; begin CIS1 : UUT ; end block L1 ; end ARCH00619_Test_Bench ;
gpl-3.0
e26000f655d672e3a5f8a44168f55859
0.533653
3.312157
false
true
false
false
grwlf/vsim
vhdl_ct/ct00672.vhd
1
7,207
-- NEED RESULT: ARCH00672: Signal default initial values - generic subtypes passed ------------------------------------------------------------------------------- -- -- Copyright (c) 1989 by Intermetrics, Inc. -- All rights reserved. -- ------------------------------------------------------------------------------- -- -- TEST NAME: -- -- CT00672 -- -- AUTHOR: -- -- A. Wilmot -- -- TEST OBJECTIVES: -- -- 4.3.1.2 (2) -- -- DESIGN UNIT ORDERING: -- -- GENERIC_STANDARD_TYPES(ARCH00672) -- ENT00672_Test_Bench(ARCH00672_Test_Bench) -- -- REVISION HISTORY: -- -- 01-SEP-1987 - initial revision -- -- NOTES: -- -- self-checking -- automatically generated -- use WORK.STANDARD_TYPES.all ; architecture ARCH00672 of GENERIC_STANDARD_TYPES is signal si_boolean_1 : boolean ; signal si_boolean_2 : boolean := d_boolean ; signal si_bit_1 : bit ; signal si_bit_2 : bit := d_bit ; signal si_severity_level_1 : severity_level ; signal si_severity_level_2 : severity_level := d_severity_level ; signal si_character_1 : character ; signal si_character_2 : character := d_character ; signal si_t_enum1_1 : t_enum1 ; signal si_t_enum1_2 : t_enum1 := d_t_enum1 ; signal si_st_enum1_1 : st_enum1 ; signal si_st_enum1_2 : st_enum1 := d_st_enum1 ; signal si_integer_1 : integer ; signal si_integer_2 : integer := d_integer ; signal si_t_int1_1 : t_int1 ; signal si_t_int1_2 : t_int1 := d_t_int1 ; signal si_st_int1_1 : st_int1 ; signal si_st_int1_2 : st_int1 := d_st_int1 ; signal si_time_1 : time ; signal si_time_2 : time := d_time ; signal si_t_phys1_1 : t_phys1 ; signal si_t_phys1_2 : t_phys1 := d_t_phys1 ; signal si_st_phys1_1 : st_phys1 ; signal si_st_phys1_2 : st_phys1 := d_st_phys1 ; signal si_real_1 : real ; signal si_real_2 : real := d_real ; signal si_t_real1_1 : t_real1 ; signal si_t_real1_2 : t_real1 := d_t_real1 ; signal si_st_real1_1 : st_real1 ; signal si_st_real1_2 : st_real1 := d_st_real1 ; signal si_st_bit_vector_1 : st_bit_vector ; signal si_st_bit_vector_2 : st_bit_vector := d_st_bit_vector ; signal si_st_string_1 : st_string ; signal si_st_string_2 : st_string := d_st_string ; signal si_t_rec1_1 : t_rec1 ; signal si_t_rec1_2 : t_rec1 := d_t_rec1 ; signal si_st_rec1_1 : st_rec1 ; signal si_st_rec1_2 : st_rec1 := d_st_rec1 ; signal si_t_rec2_1 : t_rec2 ; signal si_t_rec2_2 : t_rec2 := d_t_rec2 ; signal si_st_rec2_1 : st_rec2 ; signal si_st_rec2_2 : st_rec2 := d_st_rec2 ; signal si_t_rec3_1 : t_rec3 ; signal si_t_rec3_2 : t_rec3 := d_t_rec3 ; signal si_st_rec3_1 : st_rec3 ; signal si_st_rec3_2 : st_rec3 := d_st_rec3 ; signal si_st_arr1_1 : st_arr1 ; signal si_st_arr1_2 : st_arr1 := d_st_arr1 ; signal si_st_arr2_1 : st_arr2 ; signal si_st_arr2_2 : st_arr2 := d_st_arr2 ; signal si_st_arr3_1 : st_arr3 ; signal si_st_arr3_2 : st_arr3 := d_st_arr3 ; begin process variable correct : boolean := true ; begin correct := correct and si_boolean_1 = si_boolean_2 and si_boolean_2 = d_boolean ; correct := correct and si_bit_1 = si_bit_2 and si_bit_2 = d_bit ; correct := correct and si_severity_level_1 = si_severity_level_2 and si_severity_level_2 = d_severity_level ; correct := correct and si_character_1 = si_character_2 and si_character_2 = d_character ; correct := correct and si_t_enum1_1 = si_t_enum1_2 and si_t_enum1_2 = d_t_enum1 ; correct := correct and si_st_enum1_1 = si_st_enum1_2 and si_st_enum1_2 = d_st_enum1 ; correct := correct and si_integer_1 = si_integer_2 and si_integer_2 = d_integer ; correct := correct and si_t_int1_1 = si_t_int1_2 and si_t_int1_2 = d_t_int1 ; correct := correct and si_st_int1_1 = si_st_int1_2 and si_st_int1_2 = d_st_int1 ; correct := correct and si_time_1 = si_time_2 and si_time_2 = d_time ; correct := correct and si_t_phys1_1 = si_t_phys1_2 and si_t_phys1_2 = d_t_phys1 ; correct := correct and si_st_phys1_1 = si_st_phys1_2 and si_st_phys1_2 = d_st_phys1 ; correct := correct and si_real_1 = si_real_2 and si_real_2 = d_real ; correct := correct and si_t_real1_1 = si_t_real1_2 and si_t_real1_2 = d_t_real1 ; correct := correct and si_st_real1_1 = si_st_real1_2 and si_st_real1_2 = d_st_real1 ; correct := correct and si_st_bit_vector_1 = si_st_bit_vector_2 and si_st_bit_vector_2 = d_st_bit_vector ; correct := correct and si_st_string_1 = si_st_string_2 and si_st_string_2 = d_st_string ; correct := correct and si_t_rec1_1 = si_t_rec1_2 and si_t_rec1_2 = d_t_rec1 ; correct := correct and si_st_rec1_1 = si_st_rec1_2 and si_st_rec1_2 = d_st_rec1 ; correct := correct and si_t_rec2_1 = si_t_rec2_2 and si_t_rec2_2 = d_t_rec2 ; correct := correct and si_st_rec2_1 = si_st_rec2_2 and si_st_rec2_2 = d_st_rec2 ; correct := correct and si_t_rec3_1 = si_t_rec3_2 and si_t_rec3_2 = d_t_rec3 ; correct := correct and si_st_rec3_1 = si_st_rec3_2 and si_st_rec3_2 = d_st_rec3 ; correct := correct and si_st_arr1_1 = si_st_arr1_2 and si_st_arr1_2 = d_st_arr1 ; correct := correct and si_st_arr2_1 = si_st_arr2_2 and si_st_arr2_2 = d_st_arr2 ; correct := correct and si_st_arr3_1 = si_st_arr3_2 and si_st_arr3_2 = d_st_arr3 ; test_report ( "ARCH00672" , "Signal default initial values - generic subtypes" , correct) ; wait ; end process ; end ARCH00672 ; -- entity ENT00672_Test_Bench is end ENT00672_Test_Bench ; -- architecture ARCH00672_Test_Bench of ENT00672_Test_Bench is begin L1: block component UUT end component ; for CIS1 : UUT use entity WORK.GENERIC_STANDARD_TYPES ( ARCH00672 ) ; begin CIS1 : UUT ; end block L1 ; end ARCH00672_Test_Bench ;
gpl-3.0
1c09760720d902df8a24a20cf7625a06
0.489663
3.101119
false
false
false
false
takeshineshiro/fpga_fibre_scan
HUCB2P0_150701/frontend/r2p_cordic.vhd
1
2,252
-- -- VHDL implementation of cordic algorithm -- -- File: cordic.vhd -- author: Richard Herveille -- rev. 1.0 initial release -- rev. 1.1 changed CordicPipe component declaration, Xilinx WebPack issue -- rev. 1.2 Revised entire core. Made is simpler and easier to understand. library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; entity r2p_cordic is generic( PIPELINE : integer := 15; WIDTH : integer := 16; EXT_PRECISION : integer := 4 ); port( clk : in std_logic; ena : in std_logic; Xi : in signed(WIDTH-1 downto 0); Yi : in signed(WIDTH-1 downto 0); Zi : in signed(19 downto 0) := (others => '0'); Xo : out signed(WIDTH + EXT_PRECISION -1 downto 0); Zo : out signed(19 downto 0) ); end r2p_cordic; architecture dataflow of r2p_cordic is -- -- TYPE defenitions -- type XYVector is array(PIPELINE downto 0) of signed(WIDTH + EXT_PRECISION -1 downto 0); type ZVector is array(PIPELINE downto 0) of signed(19 downto 0); -- -- COMPONENT declarations -- component r2p_CordicPipe generic( WIDTH : natural := 16; PIPEID : natural := 1 ); port( clk : in std_logic; ena : in std_logic; Xi : in signed(WIDTH -1 downto 0); Yi : in signed(WIDTH -1 downto 0); Zi : in signed(19 downto 0); Xo : out signed(WIDTH -1 downto 0); Yo : out signed(WIDTH -1 downto 0); Zo : out signed(19 downto 0) ); end component r2p_CordicPipe; -- -- SIGNALS -- signal X, Y : XYVector; signal Z : ZVector; -- -- ACHITECTURE BODY -- begin -- fill first nodes X(0)(WIDTH + EXT_PRECISION -1 downto EXT_PRECISION) <= Xi; -- fill MSBs with input data X(0)(EXT_PRECISION -1 downto 0) <= (others => '0'); -- fill LSBs with '0' Y(0)(WIDTH + EXT_PRECISION -1 downto EXT_PRECISION) <= Yi; -- fill MSBs with input data Y(0)(EXT_PRECISION -1 downto 0) <= (others => '0'); -- fill LSBs with '0' Z(0) <= Zi; -- -- generate pipeline -- gen_pipe: for n in 1 to PIPELINE generate Pipe: r2p_CordicPipe generic map(WIDTH => WIDTH+EXT_PRECISION, PIPEID => n -1) port map ( clk, ena, X(n-1), Y(n-1), Z(n-1), X(n), Y(n), Z(n) ); end generate gen_pipe; -- -- assign outputs -- Xo <= X(PIPELINE); Zo <= Z(PIPELINE); end dataflow;
apache-2.0
3630b138fd92e1cbc154db57f1d0c8e0
0.62833
2.804483
false
false
false
false
jairov4/accel-oil
impl/impl_test_single/simulation/behavioral/system_clock_generator_0_wrapper.vhd
1
3,128
------------------------------------------------------------------------------- -- system_clock_generator_0_wrapper.vhd ------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; library clock_generator_0_v4_03_a; use clock_generator_0_v4_03_a.all; library clock_generator_v4_03_a; use clock_generator_v4_03_a.all; entity system_clock_generator_0_wrapper is port ( CLKIN : in std_logic; CLKOUT0 : out std_logic; CLKOUT1 : out std_logic; CLKOUT2 : out std_logic; CLKOUT3 : out std_logic; CLKOUT4 : out std_logic; CLKOUT5 : out std_logic; CLKOUT6 : out std_logic; CLKOUT7 : out std_logic; CLKOUT8 : out std_logic; CLKOUT9 : out std_logic; CLKOUT10 : out std_logic; CLKOUT11 : out std_logic; CLKOUT12 : out std_logic; CLKOUT13 : out std_logic; CLKOUT14 : out std_logic; CLKOUT15 : out std_logic; CLKFBIN : in std_logic; CLKFBOUT : out std_logic; PSCLK : in std_logic; PSEN : in std_logic; PSINCDEC : in std_logic; PSDONE : out std_logic; RST : in std_logic; LOCKED : out std_logic ); end system_clock_generator_0_wrapper; architecture STRUCTURE of system_clock_generator_0_wrapper is component clock_generator is generic ( C_FAMILY : STRING; C_DEVICE : STRING; C_PACKAGE : STRING; C_SPEEDGRADE : STRING ); port ( CLKIN : in std_logic; CLKOUT0 : out std_logic; CLKOUT1 : out std_logic; CLKOUT2 : out std_logic; CLKOUT3 : out std_logic; CLKOUT4 : out std_logic; CLKOUT5 : out std_logic; CLKOUT6 : out std_logic; CLKOUT7 : out std_logic; CLKOUT8 : out std_logic; CLKOUT9 : out std_logic; CLKOUT10 : out std_logic; CLKOUT11 : out std_logic; CLKOUT12 : out std_logic; CLKOUT13 : out std_logic; CLKOUT14 : out std_logic; CLKOUT15 : out std_logic; CLKFBIN : in std_logic; CLKFBOUT : out std_logic; PSCLK : in std_logic; PSEN : in std_logic; PSINCDEC : in std_logic; PSDONE : out std_logic; RST : in std_logic; LOCKED : out std_logic ); end component; begin clock_generator_0 : clock_generator generic map ( C_FAMILY => "virtex5", C_DEVICE => "5vlx50t", C_PACKAGE => "ff1136", C_SPEEDGRADE => "-2" ) port map ( CLKIN => CLKIN, CLKOUT0 => CLKOUT0, CLKOUT1 => CLKOUT1, CLKOUT2 => CLKOUT2, CLKOUT3 => CLKOUT3, CLKOUT4 => CLKOUT4, CLKOUT5 => CLKOUT5, CLKOUT6 => CLKOUT6, CLKOUT7 => CLKOUT7, CLKOUT8 => CLKOUT8, CLKOUT9 => CLKOUT9, CLKOUT10 => CLKOUT10, CLKOUT11 => CLKOUT11, CLKOUT12 => CLKOUT12, CLKOUT13 => CLKOUT13, CLKOUT14 => CLKOUT14, CLKOUT15 => CLKOUT15, CLKFBIN => CLKFBIN, CLKFBOUT => CLKFBOUT, PSCLK => PSCLK, PSEN => PSEN, PSINCDEC => PSINCDEC, PSDONE => PSDONE, RST => RST, LOCKED => LOCKED ); end architecture STRUCTURE;
lgpl-3.0
6b74273734900ee637efac2ecfa91a2e
0.569054
3.662763
false
false
false
false
grwlf/vsim
vhdl_ct/ct00231.vhd
1
10,055
-- NEED RESULT: ENT00231.P00231: Associated scalar out ports with static subtypes passed -- NEED RESULT: ENT00231: Associated scalar out ports with static subtypes passed -- NEED RESULT: ENT00231.P00231: Associated scalar out ports with static subtypes passed ------------------------------------------------------------------------------- -- -- Copyright (c) 1989 by Intermetrics, Inc. -- All rights reserved. -- ------------------------------------------------------------------------------- -- -- TEST NAME: -- -- CT00231 -- -- AUTHOR: -- -- A. Wilmot -- -- TEST OBJECTIVES: -- -- 1.1.1.2 (4) -- 1.1.1.2 (5) -- -- DESIGN UNIT ORDERING: -- -- ENT00231(ARCH00231) -- ENT00231_Test_Bench(ARCH00231_Test_Bench) -- -- REVISION HISTORY: -- -- 25-JUN-1987 - initial revision -- -- NOTES: -- -- self-checking -- automatically generated -- use WORK.STANDARD_TYPES.all ; entity ENT00231 is port ( toggle : out switch := down; i_boolean_1, i_boolean_2 : out boolean := c_boolean_1 ; i_bit_1, i_bit_2 : out bit := c_bit_1 ; i_severity_level_1, i_severity_level_2 : out severity_level := c_severity_level_1 ; i_character_1, i_character_2 : out character := c_character_1 ; i_t_enum1_1, i_t_enum1_2 : out t_enum1 := c_t_enum1_1 ; i_st_enum1_1, i_st_enum1_2 : out st_enum1 := c_st_enum1_1 ; i_integer_1, i_integer_2 : out integer := c_integer_1 ; i_t_int1_1, i_t_int1_2 : out t_int1 := c_t_int1_1 ; i_st_int1_1, i_st_int1_2 : out st_int1 := c_st_int1_1 ; i_time_1, i_time_2 : out time := c_time_1 ; i_t_phys1_1, i_t_phys1_2 : out t_phys1 := c_t_phys1_1 ; i_st_phys1_1, i_st_phys1_2 : out st_phys1 := c_st_phys1_1 ; i_real_1, i_real_2 : out real := c_real_1 ; i_t_real1_1, i_t_real1_2 : out t_real1 := c_t_real1_1 ; i_st_real1_1, i_st_real1_2 : out st_real1 := c_st_real1_1 ) ; begin end ENT00231 ; -- architecture ARCH00231 of ENT00231 is begin process variable correct : boolean := true ; begin test_report ( "ENT00231" , "Associated scalar out ports with static subtypes" , correct) ; -- toggle <= up ; i_boolean_1 <= c_boolean_2 ; i_boolean_2 <= c_boolean_2 ; i_bit_1 <= c_bit_2 ; i_bit_2 <= c_bit_2 ; i_severity_level_1 <= c_severity_level_2 ; i_severity_level_2 <= c_severity_level_2 ; i_character_1 <= c_character_2 ; i_character_2 <= c_character_2 ; i_t_enum1_1 <= c_t_enum1_2 ; i_t_enum1_2 <= c_t_enum1_2 ; i_st_enum1_1 <= c_st_enum1_2 ; i_st_enum1_2 <= c_st_enum1_2 ; i_integer_1 <= c_integer_2 ; i_integer_2 <= c_integer_2 ; i_t_int1_1 <= c_t_int1_2 ; i_t_int1_2 <= c_t_int1_2 ; i_st_int1_1 <= c_st_int1_2 ; i_st_int1_2 <= c_st_int1_2 ; i_time_1 <= c_time_2 ; i_time_2 <= c_time_2 ; i_t_phys1_1 <= c_t_phys1_2 ; i_t_phys1_2 <= c_t_phys1_2 ; i_st_phys1_1 <= c_st_phys1_2 ; i_st_phys1_2 <= c_st_phys1_2 ; i_real_1 <= c_real_2 ; i_real_2 <= c_real_2 ; i_t_real1_1 <= c_t_real1_2 ; i_t_real1_2 <= c_t_real1_2 ; i_st_real1_1 <= c_st_real1_2 ; i_st_real1_2 <= c_st_real1_2 ; wait ; end process ; end ARCH00231 ; -- use WORK.STANDARD_TYPES.all ; entity ENT00231_Test_Bench is end ENT00231_Test_Bench ; -- architecture ARCH00231_Test_Bench of ENT00231_Test_Bench is begin L1: block signal i_boolean_1, i_boolean_2 : boolean := c_boolean_1 ; signal i_bit_1, i_bit_2 : bit := c_bit_1 ; signal i_severity_level_1, i_severity_level_2 : severity_level := c_severity_level_1 ; signal i_character_1, i_character_2 : character := c_character_1 ; signal i_t_enum1_1, i_t_enum1_2 : t_enum1 := c_t_enum1_1 ; signal i_st_enum1_1, i_st_enum1_2 : st_enum1 := c_st_enum1_1 ; signal i_integer_1, i_integer_2 : integer := c_integer_1 ; signal i_t_int1_1, i_t_int1_2 : t_int1 := c_t_int1_1 ; signal i_st_int1_1, i_st_int1_2 : st_int1 := c_st_int1_1 ; signal i_time_1, i_time_2 : time := c_time_1 ; signal i_t_phys1_1, i_t_phys1_2 : t_phys1 := c_t_phys1_1 ; signal i_st_phys1_1, i_st_phys1_2 : st_phys1 := c_st_phys1_1 ; signal i_real_1, i_real_2 : real := c_real_1 ; signal i_t_real1_1, i_t_real1_2 : t_real1 := c_t_real1_1 ; signal i_st_real1_1, i_st_real1_2 : st_real1 := c_st_real1_1 ; -- component UUT port ( toggle : out switch ; i_boolean_1, i_boolean_2 : out boolean := c_boolean_1 ; i_bit_1, i_bit_2 : out bit := c_bit_1 ; i_severity_level_1, i_severity_level_2 : out severity_level := c_severity_level_1 ; i_character_1, i_character_2 : out character := c_character_1 ; i_t_enum1_1, i_t_enum1_2 : out t_enum1 := c_t_enum1_1 ; i_st_enum1_1, i_st_enum1_2 : out st_enum1 := c_st_enum1_1 ; i_integer_1, i_integer_2 : out integer := c_integer_1 ; i_t_int1_1, i_t_int1_2 : out t_int1 := c_t_int1_1 ; i_st_int1_1, i_st_int1_2 : out st_int1 := c_st_int1_1 ; i_time_1, i_time_2 : out time := c_time_1 ; i_t_phys1_1, i_t_phys1_2 : out t_phys1 := c_t_phys1_1 ; i_st_phys1_1, i_st_phys1_2 : out st_phys1 := c_st_phys1_1 ; i_real_1, i_real_2 : out real := c_real_1 ; i_t_real1_1, i_t_real1_2 : out t_real1 := c_t_real1_1 ; i_st_real1_1, i_st_real1_2 : out st_real1 := c_st_real1_1 ) ; end component ; -- for CIS1 : UUT use entity WORK.ENT00231 ( ARCH00231 ) ; -- begin CIS1 : UUT port map ( toggle , i_boolean_1, i_boolean_2, i_bit_1, i_bit_2, i_severity_level_1, i_severity_level_2, i_character_1, i_character_2, i_t_enum1_1, i_t_enum1_2, i_st_enum1_1, i_st_enum1_2, i_integer_1, i_integer_2, i_t_int1_1, i_t_int1_2, i_st_int1_1, i_st_int1_2, i_time_1, i_time_2, i_t_phys1_1, i_t_phys1_2, i_st_phys1_1, i_st_phys1_2, i_real_1, i_real_2, i_t_real1_1, i_t_real1_2, i_st_real1_1, i_st_real1_2 ) ; P00231 : process ( toggle ) variable correct : boolean := true ; begin if toggle = up then correct := correct and i_boolean_1 = c_boolean_2 and i_boolean_2 = c_boolean_2 ; correct := correct and i_bit_1 = c_bit_2 and i_bit_2 = c_bit_2 ; correct := correct and i_severity_level_1 = c_severity_level_2 and i_severity_level_2 = c_severity_level_2 ; correct := correct and i_character_1 = c_character_2 and i_character_2 = c_character_2 ; correct := correct and i_t_enum1_1 = c_t_enum1_2 and i_t_enum1_2 = c_t_enum1_2 ; correct := correct and i_st_enum1_1 = c_st_enum1_2 and i_st_enum1_2 = c_st_enum1_2 ; correct := correct and i_integer_1 = c_integer_2 and i_integer_2 = c_integer_2 ; correct := correct and i_t_int1_1 = c_t_int1_2 and i_t_int1_2 = c_t_int1_2 ; correct := correct and i_st_int1_1 = c_st_int1_2 and i_st_int1_2 = c_st_int1_2 ; correct := correct and i_time_1 = c_time_2 and i_time_2 = c_time_2 ; correct := correct and i_t_phys1_1 = c_t_phys1_2 and i_t_phys1_2 = c_t_phys1_2 ; correct := correct and i_st_phys1_1 = c_st_phys1_2 and i_st_phys1_2 = c_st_phys1_2 ; correct := correct and i_real_1 = c_real_2 and i_real_2 = c_real_2 ; correct := correct and i_t_real1_1 = c_t_real1_2 and i_t_real1_2 = c_t_real1_2 ; correct := correct and i_st_real1_1 = c_st_real1_2 and i_st_real1_2 = c_st_real1_2 ; end if ; -- test_report ( "ENT00231.P00231" , "Associated scalar out ports with static subtypes", correct) ; end process P00231 ; end block L1 ; end ARCH00231_Test_Bench ;
gpl-3.0
e4fc70e8364ef652ecb9830028e4be5d
0.430134
3.069292
false
false
false
false
grwlf/vsim
vhdl_ct/ct00415.vhd
1
8,976
-- NEED RESULT: ARCH00415.P1: Multi inertial transactions occurred on concurrent signal asg passed -- NEED RESULT: ARCH00415: One inertial transaction occurred on a concurrent signal asg passed -- NEED RESULT: ARCH00415: Old transactions were removed on a concurrent signal asg passed -- NEED RESULT: ARCH00415: One inertial transaction occurred on a concurrent signal asg passed -- NEED RESULT: ARCH00415: Inertial semantics check on a concurrent signal asg passed -- NEED RESULT: P1: Inertial transactions completed entirely passed ------------------------------------------------------------------------------- -- -- Copyright (c) 1989 by Intermetrics, Inc. -- All rights reserved. -- ------------------------------------------------------------------------------- -- -- TEST NAME: -- -- CT00415 -- -- AUTHOR: -- -- G. Tominovich -- -- TEST OBJECTIVES: -- -- 9.5 (3) -- 9.5.2 (1) -- -- DESIGN UNIT ORDERING: -- -- ENT00415(ARCH00415) -- ENT00415_Test_Bench(ARCH00415_Test_Bench) -- -- REVISION HISTORY: -- -- 30-JUL-1987 - initial revision -- -- NOTES: -- -- self-checking -- automatically generated -- use WORK.STANDARD_TYPES.all ; entity ENT00415 is port ( s_st_rec3 : inout st_rec3 ) ; subtype chk_sig_type is integer range -1 to 100 ; signal chk_st_rec3 : chk_sig_type := -1 ; -- end ENT00415 ; -- -- architecture ARCH00415 of ENT00415 is subtype chk_time_type is Time ; signal s_st_rec3_savt : chk_time_type := 0 ns ; -- subtype chk_cnt_type is Integer ; signal s_st_rec3_cnt : chk_cnt_type := 0 ; -- type select_type is range 1 to 6 ; signal st_rec3_select : select_type := 1 ; -- begin CHG1 : process variable correct : boolean ; begin case s_st_rec3_cnt is when 0 => null ; -- s_st_rec3.f3(lowb,true)(lowb to highb-1) <= -- c_st_rec3_2.f3(lowb,true)(lowb to highb-1) after 10 ns, -- c_st_rec3_1.f3(lowb,true)(lowb to highb-1) after 20 ns ; -- when 1 => correct := s_st_rec3.f3(lowb,true)(lowb to highb-1) = c_st_rec3_2.f3(lowb,true)(lowb to highb-1) and (s_st_rec3_savt + 10 ns) = Std.Standard.Now ; -- when 2 => correct := correct and s_st_rec3.f3(lowb,true)(lowb to highb-1) = c_st_rec3_1.f3(lowb,true)(lowb to highb-1) and (s_st_rec3_savt + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00415.P1" , "Multi inertial transactions occurred on " & "concurrent signal asg", correct ) ; -- st_rec3_select <= transport 2 ; -- s_st_rec3.f3(lowb,true)(lowb to highb-1) <= -- c_st_rec3_2.f3(lowb,true)(lowb to highb-1) after 10 ns , -- c_st_rec3_1.f3(lowb,true)(lowb to highb-1) after 20 ns , -- c_st_rec3_2.f3(lowb,true)(lowb to highb-1) after 30 ns , -- c_st_rec3_1.f3(lowb,true)(lowb to highb-1) after 40 ns ; -- when 3 => correct := s_st_rec3.f3(lowb,true)(lowb to highb-1) = c_st_rec3_2.f3(lowb,true)(lowb to highb-1) and (s_st_rec3_savt + 10 ns) = Std.Standard.Now ; st_rec3_select <= transport 3 ; -- s_st_rec3.f3(lowb,true)(lowb to highb-1) <= -- c_st_rec3_1.f3(lowb,true)(lowb to highb-1) after 5 ns ; -- when 4 => correct := correct and s_st_rec3.f3(lowb,true)(lowb to highb-1) = c_st_rec3_1.f3(lowb,true)(lowb to highb-1) and (s_st_rec3_savt + 5 ns) = Std.Standard.Now ; test_report ( "ARCH00415" , "One inertial transaction occurred on a " & "concurrent signal asg", correct ) ; st_rec3_select <= transport 4 ; -- s_st_rec3.f3(lowb,true)(lowb to highb-1) <= -- c_st_rec3_1.f3(lowb,true)(lowb to highb-1) after 100 ns ; -- when 5 => correct := correct and s_st_rec3.f3(lowb,true)(lowb to highb-1) = c_st_rec3_1.f3(lowb,true)(lowb to highb-1) and (s_st_rec3_savt + 100 ns) = Std.Standard.Now ; test_report ( "ARCH00415" , "Old transactions were removed on a " & "concurrent signal asg", correct ) ; st_rec3_select <= transport 5 ; -- s_st_rec3.f3(lowb,true)(lowb to highb-1) <= -- c_st_rec3_2.f3(lowb,true)(lowb to highb-1) after 10 ns , -- c_st_rec3_1.f3(lowb,true)(lowb to highb-1) after 20 ns , -- c_st_rec3_2.f3(lowb,true)(lowb to highb-1) after 30 ns , -- c_st_rec3_1.f3(lowb,true)(lowb to highb-1) after 40 ns ; -- when 6 => correct := correct and s_st_rec3.f3(lowb,true)(lowb to highb-1) = c_st_rec3_2.f3(lowb,true)(lowb to highb-1) and (s_st_rec3_savt + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00415" , "One inertial transaction occurred on a " & "concurrent signal asg", correct ) ; st_rec3_select <= transport 6 ; -- Last transaction above is marked -- s_st_rec3.f3(lowb,true)(lowb to highb-1) <= -- c_st_rec3_1.f3(lowb,true)(lowb to highb-1) after 40 ns ; -- when 7 => correct := correct and s_st_rec3.f3(lowb,true)(lowb to highb-1) = c_st_rec3_1.f3(lowb,true)(lowb to highb-1) and (s_st_rec3_savt + 30 ns) = Std.Standard.Now ; -- when 8 => correct := correct and s_st_rec3.f3(lowb,true)(lowb to highb-1) = c_st_rec3_1.f3(lowb,true)(lowb to highb-1) and (s_st_rec3_savt + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00415" , "Inertial semantics check on a concurrent " & "signal asg", correct ) ; -- when others => -- No more transactions should have occurred test_report ( "ARCH00415" , "Inertial semantics check on a concurrent " & "signal asg", false ) ; -- end case ; -- s_st_rec3_savt <= transport Std.Standard.Now ; chk_st_rec3 <= transport s_st_rec3_cnt after (1 us - Std.Standard.Now) ; s_st_rec3_cnt <= transport s_st_rec3_cnt + 1 ; wait until (not s_st_rec3.f3(lowb,true)(lowb to highb-1)'Quiet) and (s_st_rec3_savt /= Std.Standard.Now) ; -- end process CHG1 ; -- PGEN_CHKP_1 : process ( chk_st_rec3 ) begin if Std.Standard.Now > 0 ns then test_report ( "P1" , "Inertial transactions completed entirely", chk_st_rec3 = 8 ) ; end if ; end process PGEN_CHKP_1 ; -- -- with st_rec3_select select s_st_rec3.f3(lowb,true)(lowb to highb-1) <= c_st_rec3_2.f3(lowb,true)(lowb to highb-1) after 10 ns, c_st_rec3_1.f3(lowb,true)(lowb to highb-1) after 20 ns when 1, -- c_st_rec3_2.f3(lowb,true)(lowb to highb-1) after 10 ns , c_st_rec3_1.f3(lowb,true)(lowb to highb-1) after 20 ns , c_st_rec3_2.f3(lowb,true)(lowb to highb-1) after 30 ns , c_st_rec3_1.f3(lowb,true)(lowb to highb-1) after 40 ns when 2, -- c_st_rec3_1.f3(lowb,true)(lowb to highb-1) after 5 ns when 3, -- c_st_rec3_1.f3(lowb,true)(lowb to highb-1) after 100 ns when 4, -- c_st_rec3_2.f3(lowb,true)(lowb to highb-1) after 10 ns , c_st_rec3_1.f3(lowb,true)(lowb to highb-1) after 20 ns , c_st_rec3_2.f3(lowb,true)(lowb to highb-1) after 30 ns , c_st_rec3_1.f3(lowb,true)(lowb to highb-1) after 40 ns when 5, -- -- Last transaction above is marked c_st_rec3_1.f3(lowb,true)(lowb to highb-1) after 40 ns when 6 ; -- end ARCH00415 ; -- -- use WORK.STANDARD_TYPES.all ; entity ENT00415_Test_Bench is signal s_st_rec3 : st_rec3 := c_st_rec3_1 ; -- end ENT00415_Test_Bench ; -- -- architecture ARCH00415_Test_Bench of ENT00415_Test_Bench is begin L1: block component UUT port ( s_st_rec3 : inout st_rec3 ) ; end component ; -- for CIS1 : UUT use entity WORK.ENT00415 ( ARCH00415 ) ; begin CIS1 : UUT port map ( s_st_rec3 ) ; end block L1 ; end ARCH00415_Test_Bench ;
gpl-3.0
556ba69ecbe4d3cad6d242a375ff8c56
0.50713
3.097308
false
true
false
false
jairov4/accel-oil
impl/impl_test_pcie/simulation/behavioral/system_xps_intc_0_wrapper.vhd
1
6,997
------------------------------------------------------------------------------- -- system_xps_intc_0_wrapper.vhd ------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; library xps_intc_v2_01_a; use xps_intc_v2_01_a.all; entity system_xps_intc_0_wrapper is port ( SPLB_Clk : in std_logic; SPLB_Rst : in std_logic; PLB_ABus : in std_logic_vector(0 to 31); PLB_PAValid : in std_logic; PLB_masterID : in std_logic_vector(0 to 2); PLB_RNW : in std_logic; PLB_BE : in std_logic_vector(0 to 7); PLB_size : in std_logic_vector(0 to 3); PLB_type : in std_logic_vector(0 to 2); PLB_wrDBus : in std_logic_vector(0 to 63); PLB_UABus : in std_logic_vector(0 to 31); PLB_SAValid : in std_logic; PLB_rdPrim : in std_logic; PLB_wrPrim : in std_logic; PLB_abort : in std_logic; PLB_busLock : in std_logic; PLB_MSize : in std_logic_vector(0 to 1); PLB_lockErr : in std_logic; PLB_wrBurst : in std_logic; PLB_rdBurst : in std_logic; PLB_wrPendReq : in std_logic; PLB_rdPendReq : in std_logic; PLB_wrPendPri : in std_logic_vector(0 to 1); PLB_rdPendPri : in std_logic_vector(0 to 1); PLB_reqPri : in std_logic_vector(0 to 1); PLB_TAttribute : in std_logic_vector(0 to 15); Sl_addrAck : out std_logic; Sl_SSize : out std_logic_vector(0 to 1); Sl_wait : out std_logic; Sl_rearbitrate : out std_logic; Sl_wrDAck : out std_logic; Sl_wrComp : out std_logic; Sl_rdDBus : out std_logic_vector(0 to 63); Sl_rdDAck : out std_logic; Sl_rdComp : out std_logic; Sl_MBusy : out std_logic_vector(0 to 5); Sl_MWrErr : out std_logic_vector(0 to 5); Sl_MRdErr : out std_logic_vector(0 to 5); Sl_wrBTerm : out std_logic; Sl_rdWdAddr : out std_logic_vector(0 to 3); Sl_rdBTerm : out std_logic; Sl_MIRQ : out std_logic_vector(0 to 5); Intr : in std_logic_vector(1 downto 0); Irq : out std_logic ); end system_xps_intc_0_wrapper; architecture STRUCTURE of system_xps_intc_0_wrapper is component xps_intc is generic ( C_FAMILY : STRING; C_BASEADDR : std_logic_vector(0 to 31); C_HIGHADDR : std_logic_vector(0 to 31); C_SPLB_AWIDTH : INTEGER; C_SPLB_DWIDTH : INTEGER; C_SPLB_P2P : INTEGER; C_SPLB_NUM_MASTERS : INTEGER; C_SPLB_MID_WIDTH : INTEGER; C_SPLB_NATIVE_DWIDTH : INTEGER; C_SPLB_SUPPORT_BURSTS : INTEGER; C_NUM_INTR_INPUTS : INTEGER; C_KIND_OF_INTR : std_logic_vector(31 downto 0); C_KIND_OF_EDGE : std_logic_vector(31 downto 0); C_KIND_OF_LVL : std_logic_vector(31 downto 0); C_HAS_IPR : INTEGER; C_HAS_SIE : INTEGER; C_HAS_CIE : INTEGER; C_HAS_IVR : INTEGER; C_IRQ_IS_LEVEL : INTEGER; C_IRQ_ACTIVE : std_logic ); port ( SPLB_Clk : in std_logic; SPLB_Rst : in std_logic; PLB_ABus : in std_logic_vector(0 to 31); PLB_PAValid : in std_logic; PLB_masterID : in std_logic_vector(0 to (C_SPLB_MID_WIDTH-1)); PLB_RNW : in std_logic; PLB_BE : in std_logic_vector(0 to ((C_SPLB_DWIDTH/8)-1)); PLB_size : in std_logic_vector(0 to 3); PLB_type : in std_logic_vector(0 to 2); PLB_wrDBus : in std_logic_vector(0 to (C_SPLB_DWIDTH-1)); PLB_UABus : in std_logic_vector(0 to 31); PLB_SAValid : in std_logic; PLB_rdPrim : in std_logic; PLB_wrPrim : in std_logic; PLB_abort : in std_logic; PLB_busLock : in std_logic; PLB_MSize : in std_logic_vector(0 to 1); PLB_lockErr : in std_logic; PLB_wrBurst : in std_logic; PLB_rdBurst : in std_logic; PLB_wrPendReq : in std_logic; PLB_rdPendReq : in std_logic; PLB_wrPendPri : in std_logic_vector(0 to 1); PLB_rdPendPri : in std_logic_vector(0 to 1); PLB_reqPri : in std_logic_vector(0 to 1); PLB_TAttribute : in std_logic_vector(0 to 15); Sl_addrAck : out std_logic; Sl_SSize : out std_logic_vector(0 to 1); Sl_wait : out std_logic; Sl_rearbitrate : out std_logic; Sl_wrDAck : out std_logic; Sl_wrComp : out std_logic; Sl_rdDBus : out std_logic_vector(0 to (C_SPLB_DWIDTH-1)); Sl_rdDAck : out std_logic; Sl_rdComp : out std_logic; Sl_MBusy : out std_logic_vector(0 to (C_SPLB_NUM_MASTERS-1)); Sl_MWrErr : out std_logic_vector(0 to (C_SPLB_NUM_MASTERS-1)); Sl_MRdErr : out std_logic_vector(0 to (C_SPLB_NUM_MASTERS-1)); Sl_wrBTerm : out std_logic; Sl_rdWdAddr : out std_logic_vector(0 to 3); Sl_rdBTerm : out std_logic; Sl_MIRQ : out std_logic_vector(0 to (C_SPLB_NUM_MASTERS-1)); Intr : in std_logic_vector((C_NUM_INTR_INPUTS-1) downto 0); Irq : out std_logic ); end component; begin xps_intc_0 : xps_intc generic map ( C_FAMILY => "virtex5", C_BASEADDR => X"81800000", C_HIGHADDR => X"8180ffff", C_SPLB_AWIDTH => 32, C_SPLB_DWIDTH => 64, C_SPLB_P2P => 0, C_SPLB_NUM_MASTERS => 6, C_SPLB_MID_WIDTH => 3, C_SPLB_NATIVE_DWIDTH => 32, C_SPLB_SUPPORT_BURSTS => 0, C_NUM_INTR_INPUTS => 2, C_KIND_OF_INTR => B"11111111111111111111111111111100", C_KIND_OF_EDGE => B"11111111111111111111111111111111", C_KIND_OF_LVL => B"11111111111111111111111111111111", C_HAS_IPR => 1, C_HAS_SIE => 1, C_HAS_CIE => 1, C_HAS_IVR => 1, C_IRQ_IS_LEVEL => 1, C_IRQ_ACTIVE => '1' ) port map ( SPLB_Clk => SPLB_Clk, SPLB_Rst => SPLB_Rst, PLB_ABus => PLB_ABus, PLB_PAValid => PLB_PAValid, PLB_masterID => PLB_masterID, PLB_RNW => PLB_RNW, PLB_BE => PLB_BE, PLB_size => PLB_size, PLB_type => PLB_type, PLB_wrDBus => PLB_wrDBus, PLB_UABus => PLB_UABus, PLB_SAValid => PLB_SAValid, PLB_rdPrim => PLB_rdPrim, PLB_wrPrim => PLB_wrPrim, PLB_abort => PLB_abort, PLB_busLock => PLB_busLock, PLB_MSize => PLB_MSize, PLB_lockErr => PLB_lockErr, PLB_wrBurst => PLB_wrBurst, PLB_rdBurst => PLB_rdBurst, PLB_wrPendReq => PLB_wrPendReq, PLB_rdPendReq => PLB_rdPendReq, PLB_wrPendPri => PLB_wrPendPri, PLB_rdPendPri => PLB_rdPendPri, PLB_reqPri => PLB_reqPri, PLB_TAttribute => PLB_TAttribute, Sl_addrAck => Sl_addrAck, Sl_SSize => Sl_SSize, Sl_wait => Sl_wait, Sl_rearbitrate => Sl_rearbitrate, Sl_wrDAck => Sl_wrDAck, Sl_wrComp => Sl_wrComp, Sl_rdDBus => Sl_rdDBus, Sl_rdDAck => Sl_rdDAck, Sl_rdComp => Sl_rdComp, Sl_MBusy => Sl_MBusy, Sl_MWrErr => Sl_MWrErr, Sl_MRdErr => Sl_MRdErr, Sl_wrBTerm => Sl_wrBTerm, Sl_rdWdAddr => Sl_rdWdAddr, Sl_rdBTerm => Sl_rdBTerm, Sl_MIRQ => Sl_MIRQ, Intr => Intr, Irq => Irq ); end architecture STRUCTURE;
lgpl-3.0
85e42d73a6b3e66bbe98534a207e4cef
0.582107
3.197898
false
false
false
false
grwlf/vsim
vhdl_ct/ct00240.vhd
1
5,405
-- NEED RESULT: ENT00240: Associated composite linkage ports with static subtypes passed ------------------------------------------------------------------------------- -- -- Copyright (c) 1989 by Intermetrics, Inc. -- All rights reserved. -- ------------------------------------------------------------------------------- -- -- TEST NAME: -- -- CT00240 -- -- AUTHOR: -- -- A. Wilmot -- -- TEST OBJECTIVES: -- -- 1.1.1.2 (4) -- 1.1.1.2 (7) -- -- DESIGN UNIT ORDERING: -- -- ENT00240(ARCH00240) -- ENT00240_Test_Bench(ARCH00240_Test_Bench) -- -- REVISION HISTORY: -- -- 25-JUN-1987 - initial revision -- -- NOTES: -- -- self-checking -- automatically generated -- use WORK.STANDARD_TYPES.all ; entity ENT00240 is port ( i_bit_vector_1, i_bit_vector_2 : linkage bit_vector ; i_string_1, i_string_2 : linkage string ; i_t_rec1_1, i_t_rec1_2 : linkage t_rec1 ; i_st_rec1_1, i_st_rec1_2 : linkage st_rec1 ; i_t_rec2_1, i_t_rec2_2 : linkage t_rec2 ; i_st_rec2_1, i_st_rec2_2 : linkage st_rec2 ; i_t_rec3_1, i_t_rec3_2 : linkage t_rec3 ; i_st_rec3_1, i_st_rec3_2 : linkage st_rec3 ; i_t_arr1_1, i_t_arr1_2 : linkage t_arr1 ; i_st_arr1_1, i_st_arr1_2 : linkage st_arr1 ; i_t_arr2_1, i_t_arr2_2 : linkage t_arr2 ; i_st_arr2_1, i_st_arr2_2 : linkage st_arr2 ; i_t_arr3_1, i_t_arr3_2 : linkage t_arr3 ; i_st_arr3_1, i_st_arr3_2 : linkage st_arr3 ) ; begin end ENT00240 ; -- architecture ARCH00240 of ENT00240 is begin process variable correct : boolean := true ; begin test_report ( "ENT00240" , "Associated composite linkage ports with static subtypes" , correct) ; wait ; end process ; end ARCH00240 ; -- use WORK.STANDARD_TYPES.all ; entity ENT00240_Test_Bench is end ENT00240_Test_Bench ; -- architecture ARCH00240_Test_Bench of ENT00240_Test_Bench is begin L1: block signal i_bit_vector_1, i_bit_vector_2 : st_bit_vector := c_st_bit_vector_1 ; signal i_string_1, i_string_2 : st_string := c_st_string_1 ; signal i_t_rec1_1, i_t_rec1_2 : st_rec1 := c_st_rec1_1 ; signal i_st_rec1_1, i_st_rec1_2 : st_rec1 := c_st_rec1_1 ; signal i_t_rec2_1, i_t_rec2_2 : st_rec2 := c_st_rec2_1 ; signal i_st_rec2_1, i_st_rec2_2 : st_rec2 := c_st_rec2_1 ; signal i_t_rec3_1, i_t_rec3_2 : st_rec3 := c_st_rec3_1 ; signal i_st_rec3_1, i_st_rec3_2 : st_rec3 := c_st_rec3_1 ; signal i_t_arr1_1, i_t_arr1_2 : st_arr1 := c_st_arr1_1 ; signal i_st_arr1_1, i_st_arr1_2 : st_arr1 := c_st_arr1_1 ; signal i_t_arr2_1, i_t_arr2_2 : st_arr2 := c_st_arr2_1 ; signal i_st_arr2_1, i_st_arr2_2 : st_arr2 := c_st_arr2_1 ; signal i_t_arr3_1, i_t_arr3_2 : st_arr3 := c_st_arr3_1 ; signal i_st_arr3_1, i_st_arr3_2 : st_arr3 := c_st_arr3_1 ; -- component UUT port ( i_bit_vector_1, i_bit_vector_2 : linkage bit_vector ; i_string_1, i_string_2 : linkage string ; i_t_rec1_1, i_t_rec1_2 : linkage t_rec1 ; i_st_rec1_1, i_st_rec1_2 : linkage st_rec1 ; i_t_rec2_1, i_t_rec2_2 : linkage t_rec2 ; i_st_rec2_1, i_st_rec2_2 : linkage st_rec2 ; i_t_rec3_1, i_t_rec3_2 : linkage t_rec3 ; i_st_rec3_1, i_st_rec3_2 : linkage st_rec3 ; i_t_arr1_1, i_t_arr1_2 : linkage t_arr1 ; i_st_arr1_1, i_st_arr1_2 : linkage st_arr1 ; i_t_arr2_1, i_t_arr2_2 : linkage t_arr2 ; i_st_arr2_1, i_st_arr2_2 : linkage st_arr2 ; i_t_arr3_1, i_t_arr3_2 : linkage t_arr3 ; i_st_arr3_1, i_st_arr3_2 : linkage st_arr3 ) ; end component ; -- for CIS1 : UUT use entity WORK.ENT00240 ( ARCH00240 ) ; -- begin CIS1 : UUT port map ( i_bit_vector_1, i_bit_vector_2, i_string_1, i_string_2, i_t_rec1_1, i_t_rec1_2, i_st_rec1_1, i_st_rec1_2, i_t_rec2_1, i_t_rec2_2, i_st_rec2_1, i_st_rec2_2, i_t_rec3_1, i_t_rec3_2, i_st_rec3_1, i_st_rec3_2, i_t_arr1_1, i_t_arr1_2, i_st_arr1_1, i_st_arr1_2, i_t_arr2_1, i_t_arr2_2, i_st_arr2_1, i_st_arr2_2, i_t_arr3_1, i_t_arr3_2, i_st_arr3_1, i_st_arr3_2 ) ; end block L1 ; end ARCH00240_Test_Bench ;
gpl-3.0
da054b6a8fea953edcc61512170d61ea
0.430897
2.831325
false
true
false
false
jairov4/accel-oil
solution_spartan3/syn/vhdl/nfa_accept_sample.vhd
1
62,393
-- ============================================================== -- RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC -- Version: 2013.4 -- Copyright (C) 2013 Xilinx Inc. All rights reserved. -- -- =========================================================== library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; entity nfa_accept_sample is port ( ap_clk : IN STD_LOGIC; ap_rst : IN STD_LOGIC; ap_start : IN STD_LOGIC; ap_done : OUT STD_LOGIC; ap_idle : OUT STD_LOGIC; ap_ready : OUT STD_LOGIC; nfa_initials_buckets_req_din : OUT STD_LOGIC; nfa_initials_buckets_req_full_n : IN STD_LOGIC; nfa_initials_buckets_req_write : OUT STD_LOGIC; nfa_initials_buckets_rsp_empty_n : IN STD_LOGIC; nfa_initials_buckets_rsp_read : OUT STD_LOGIC; nfa_initials_buckets_address : OUT STD_LOGIC_VECTOR (31 downto 0); nfa_initials_buckets_datain : IN STD_LOGIC_VECTOR (31 downto 0); nfa_initials_buckets_dataout : OUT STD_LOGIC_VECTOR (31 downto 0); nfa_initials_buckets_size : OUT STD_LOGIC_VECTOR (31 downto 0); nfa_finals_buckets_req_din : OUT STD_LOGIC; nfa_finals_buckets_req_full_n : IN STD_LOGIC; nfa_finals_buckets_req_write : OUT STD_LOGIC; nfa_finals_buckets_rsp_empty_n : IN STD_LOGIC; nfa_finals_buckets_rsp_read : OUT STD_LOGIC; nfa_finals_buckets_address : OUT STD_LOGIC_VECTOR (31 downto 0); nfa_finals_buckets_datain : IN STD_LOGIC_VECTOR (31 downto 0); nfa_finals_buckets_dataout : OUT STD_LOGIC_VECTOR (31 downto 0); nfa_finals_buckets_size : OUT STD_LOGIC_VECTOR (31 downto 0); nfa_forward_buckets_req_din : OUT STD_LOGIC; nfa_forward_buckets_req_full_n : IN STD_LOGIC; nfa_forward_buckets_req_write : OUT STD_LOGIC; nfa_forward_buckets_rsp_empty_n : IN STD_LOGIC; nfa_forward_buckets_rsp_read : OUT STD_LOGIC; nfa_forward_buckets_address : OUT STD_LOGIC_VECTOR (31 downto 0); nfa_forward_buckets_datain : IN STD_LOGIC_VECTOR (31 downto 0); nfa_forward_buckets_dataout : OUT STD_LOGIC_VECTOR (31 downto 0); nfa_forward_buckets_size : OUT STD_LOGIC_VECTOR (31 downto 0); nfa_symbols : IN STD_LOGIC_VECTOR (7 downto 0); sample_req_din : OUT STD_LOGIC; sample_req_full_n : IN STD_LOGIC; sample_req_write : OUT STD_LOGIC; sample_rsp_empty_n : IN STD_LOGIC; sample_rsp_read : OUT STD_LOGIC; sample_address : OUT STD_LOGIC_VECTOR (31 downto 0); sample_datain : IN STD_LOGIC_VECTOR (7 downto 0); sample_dataout : OUT STD_LOGIC_VECTOR (7 downto 0); sample_size : OUT STD_LOGIC_VECTOR (31 downto 0); empty : IN STD_LOGIC_VECTOR (31 downto 0); length_r : IN STD_LOGIC_VECTOR (15 downto 0); ap_return : OUT STD_LOGIC_VECTOR (0 downto 0) ); end; architecture behav of nfa_accept_sample is constant ap_const_logic_1 : STD_LOGIC := '1'; constant ap_const_logic_0 : STD_LOGIC := '0'; constant ap_ST_st1_fsm_0 : STD_LOGIC_VECTOR (5 downto 0) := "000000"; constant ap_ST_st2_fsm_1 : STD_LOGIC_VECTOR (5 downto 0) := "000001"; constant ap_ST_st3_fsm_2 : STD_LOGIC_VECTOR (5 downto 0) := "000010"; constant ap_ST_st4_fsm_3 : STD_LOGIC_VECTOR (5 downto 0) := "000011"; constant ap_ST_st5_fsm_4 : STD_LOGIC_VECTOR (5 downto 0) := "000100"; constant ap_ST_st6_fsm_5 : STD_LOGIC_VECTOR (5 downto 0) := "000101"; constant ap_ST_st7_fsm_6 : STD_LOGIC_VECTOR (5 downto 0) := "000110"; constant ap_ST_st8_fsm_7 : STD_LOGIC_VECTOR (5 downto 0) := "000111"; constant ap_ST_st9_fsm_8 : STD_LOGIC_VECTOR (5 downto 0) := "001000"; constant ap_ST_st10_fsm_9 : STD_LOGIC_VECTOR (5 downto 0) := "001001"; constant ap_ST_st11_fsm_10 : STD_LOGIC_VECTOR (5 downto 0) := "001010"; constant ap_ST_st12_fsm_11 : STD_LOGIC_VECTOR (5 downto 0) := "001011"; constant ap_ST_st13_fsm_12 : STD_LOGIC_VECTOR (5 downto 0) := "001100"; constant ap_ST_st14_fsm_13 : STD_LOGIC_VECTOR (5 downto 0) := "001101"; constant ap_ST_st15_fsm_14 : STD_LOGIC_VECTOR (5 downto 0) := "001110"; constant ap_ST_st16_fsm_15 : STD_LOGIC_VECTOR (5 downto 0) := "001111"; constant ap_ST_st17_fsm_16 : STD_LOGIC_VECTOR (5 downto 0) := "010000"; constant ap_ST_st18_fsm_17 : STD_LOGIC_VECTOR (5 downto 0) := "010001"; constant ap_ST_st19_fsm_18 : STD_LOGIC_VECTOR (5 downto 0) := "010010"; constant ap_ST_st20_fsm_19 : STD_LOGIC_VECTOR (5 downto 0) := "010011"; constant ap_ST_st21_fsm_20 : STD_LOGIC_VECTOR (5 downto 0) := "010100"; constant ap_ST_st22_fsm_21 : STD_LOGIC_VECTOR (5 downto 0) := "010101"; constant ap_ST_st23_fsm_22 : STD_LOGIC_VECTOR (5 downto 0) := "010110"; constant ap_ST_st24_fsm_23 : STD_LOGIC_VECTOR (5 downto 0) := "010111"; constant ap_ST_st25_fsm_24 : STD_LOGIC_VECTOR (5 downto 0) := "011000"; constant ap_ST_st26_fsm_25 : STD_LOGIC_VECTOR (5 downto 0) := "011001"; constant ap_ST_st27_fsm_26 : STD_LOGIC_VECTOR (5 downto 0) := "011010"; constant ap_ST_st28_fsm_27 : STD_LOGIC_VECTOR (5 downto 0) := "011011"; constant ap_ST_st29_fsm_28 : STD_LOGIC_VECTOR (5 downto 0) := "011100"; constant ap_ST_st30_fsm_29 : STD_LOGIC_VECTOR (5 downto 0) := "011101"; constant ap_ST_st31_fsm_30 : STD_LOGIC_VECTOR (5 downto 0) := "011110"; constant ap_ST_st32_fsm_31 : STD_LOGIC_VECTOR (5 downto 0) := "011111"; constant ap_ST_st33_fsm_32 : STD_LOGIC_VECTOR (5 downto 0) := "100000"; constant ap_ST_st34_fsm_33 : STD_LOGIC_VECTOR (5 downto 0) := "100001"; constant ap_ST_st35_fsm_34 : STD_LOGIC_VECTOR (5 downto 0) := "100010"; constant ap_ST_st36_fsm_35 : STD_LOGIC_VECTOR (5 downto 0) := "100011"; constant ap_ST_st37_fsm_36 : STD_LOGIC_VECTOR (5 downto 0) := "100100"; constant ap_ST_st38_fsm_37 : STD_LOGIC_VECTOR (5 downto 0) := "100101"; constant ap_ST_st39_fsm_38 : STD_LOGIC_VECTOR (5 downto 0) := "100110"; constant ap_ST_st40_fsm_39 : STD_LOGIC_VECTOR (5 downto 0) := "100111"; constant ap_ST_st41_fsm_40 : STD_LOGIC_VECTOR (5 downto 0) := "101000"; constant ap_ST_st42_fsm_41 : STD_LOGIC_VECTOR (5 downto 0) := "101001"; constant ap_ST_st43_fsm_42 : STD_LOGIC_VECTOR (5 downto 0) := "101010"; constant ap_ST_st44_fsm_43 : STD_LOGIC_VECTOR (5 downto 0) := "101011"; constant ap_ST_st45_fsm_44 : STD_LOGIC_VECTOR (5 downto 0) := "101100"; constant ap_ST_st46_fsm_45 : STD_LOGIC_VECTOR (5 downto 0) := "101101"; constant ap_ST_st47_fsm_46 : STD_LOGIC_VECTOR (5 downto 0) := "101110"; constant ap_ST_st48_fsm_47 : STD_LOGIC_VECTOR (5 downto 0) := "101111"; constant ap_ST_st49_fsm_48 : STD_LOGIC_VECTOR (5 downto 0) := "110000"; constant ap_ST_st50_fsm_49 : STD_LOGIC_VECTOR (5 downto 0) := "110001"; constant ap_const_lv1_0 : STD_LOGIC_VECTOR (0 downto 0) := "0"; constant ap_const_lv16_0 : STD_LOGIC_VECTOR (15 downto 0) := "0000000000000000"; constant ap_const_lv32_0 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000000"; constant ap_const_lv1_1 : STD_LOGIC_VECTOR (0 downto 0) := "1"; constant ap_const_lv2_2 : STD_LOGIC_VECTOR (1 downto 0) := "10"; constant ap_const_lv32_1 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000001"; constant ap_const_lv16_1 : STD_LOGIC_VECTOR (15 downto 0) := "0000000000000001"; constant ap_const_lv5_0 : STD_LOGIC_VECTOR (4 downto 0) := "00000"; constant ap_const_lv8_0 : STD_LOGIC_VECTOR (7 downto 0) := "00000000"; signal ap_CS_fsm : STD_LOGIC_VECTOR (5 downto 0) := "000000"; signal reg_374 : STD_LOGIC_VECTOR (31 downto 0); signal current_buckets_0_reg_577 : STD_LOGIC_VECTOR (31 downto 0); signal current_buckets_1_reg_582 : STD_LOGIC_VECTOR (31 downto 0); signal tmp_s_fu_397_p2 : STD_LOGIC_VECTOR (0 downto 0); signal tmp_s_reg_597 : STD_LOGIC_VECTOR (0 downto 0); signal grp_fu_402_p2 : STD_LOGIC_VECTOR (15 downto 0); signal i_1_reg_601 : STD_LOGIC_VECTOR (15 downto 0); signal sample_addr_1_reg_606 : STD_LOGIC_VECTOR (31 downto 0); signal tmp_17_i_fu_420_p2 : STD_LOGIC_VECTOR (0 downto 0); signal tmp_17_i_reg_612 : STD_LOGIC_VECTOR (0 downto 0); signal grp_fu_414_p2 : STD_LOGIC_VECTOR (31 downto 0); signal p_rec_reg_616 : STD_LOGIC_VECTOR (31 downto 0); signal sym_reg_621 : STD_LOGIC_VECTOR (7 downto 0); signal tmp_17_1_i_fu_426_p2 : STD_LOGIC_VECTOR (0 downto 0); signal tmp_17_1_i_reg_626 : STD_LOGIC_VECTOR (0 downto 0); signal grp_p_bsf32_hw_fu_368_ap_return : STD_LOGIC_VECTOR (4 downto 0); signal r_bit_reg_630 : STD_LOGIC_VECTOR (4 downto 0); signal agg_result_bucket_index_0_lcssa4_i_cast_cast_fu_432_p1 : STD_LOGIC_VECTOR (1 downto 0); signal j_bucket_index1_ph_cast_fu_436_p1 : STD_LOGIC_VECTOR (7 downto 0); signal j_bit1_ph_cast_fu_440_p1 : STD_LOGIC_VECTOR (7 downto 0); signal tmp_7_i_cast_fu_444_p1 : STD_LOGIC_VECTOR (13 downto 0); signal tmp_7_i_cast_reg_650 : STD_LOGIC_VECTOR (13 downto 0); signal j_end_phi_fu_312_p4 : STD_LOGIC_VECTOR (0 downto 0); signal grp_fu_463_p2 : STD_LOGIC_VECTOR (5 downto 0); signal state_reg_665 : STD_LOGIC_VECTOR (5 downto 0); signal grp_fu_476_p2 : STD_LOGIC_VECTOR (13 downto 0); signal tmp_6_i_reg_680 : STD_LOGIC_VECTOR (13 downto 0); signal j_bit_reg_685 : STD_LOGIC_VECTOR (7 downto 0); signal j_bucket_index_reg_690 : STD_LOGIC_VECTOR (7 downto 0); signal j_bucket_reg_695 : STD_LOGIC_VECTOR (31 downto 0); signal p_s_reg_700 : STD_LOGIC_VECTOR (0 downto 0); signal grp_fu_482_p2 : STD_LOGIC_VECTOR (13 downto 0); signal offset_i_reg_705 : STD_LOGIC_VECTOR (13 downto 0); signal next_buckets_0_1_fu_538_p2 : STD_LOGIC_VECTOR (31 downto 0); signal next_buckets_0_1_reg_721 : STD_LOGIC_VECTOR (31 downto 0); signal next_buckets_1_1_fu_544_p2 : STD_LOGIC_VECTOR (31 downto 0); signal tmp_buckets_0_reg_731 : STD_LOGIC_VECTOR (31 downto 0); signal tmp_buckets_1_reg_736 : STD_LOGIC_VECTOR (31 downto 0); signal current_buckets_0_1_fu_558_p2 : STD_LOGIC_VECTOR (31 downto 0); signal current_buckets_0_1_reg_741 : STD_LOGIC_VECTOR (31 downto 0); signal current_buckets_1_1_fu_563_p2 : STD_LOGIC_VECTOR (31 downto 0); signal current_buckets_1_1_reg_746 : STD_LOGIC_VECTOR (31 downto 0); signal tmp_1_fu_568_p2 : STD_LOGIC_VECTOR (31 downto 0); signal tmp_1_reg_751 : STD_LOGIC_VECTOR (31 downto 0); signal tmp_2_fu_572_p2 : STD_LOGIC_VECTOR (0 downto 0); signal tmp_2_reg_756 : STD_LOGIC_VECTOR (0 downto 0); signal grp_bitset_next_fu_344_p_read : STD_LOGIC_VECTOR (31 downto 0); signal grp_bitset_next_fu_344_r_bit : STD_LOGIC_VECTOR (7 downto 0); signal grp_bitset_next_fu_344_r_bucket_index : STD_LOGIC_VECTOR (7 downto 0); signal grp_bitset_next_fu_344_r_bucket : STD_LOGIC_VECTOR (31 downto 0); signal grp_bitset_next_fu_344_ap_return_0 : STD_LOGIC_VECTOR (7 downto 0); signal grp_bitset_next_fu_344_ap_return_1 : STD_LOGIC_VECTOR (7 downto 0); signal grp_bitset_next_fu_344_ap_return_2 : STD_LOGIC_VECTOR (31 downto 0); signal grp_bitset_next_fu_344_ap_return_3 : STD_LOGIC_VECTOR (0 downto 0); signal grp_bitset_next_fu_344_ap_ce : STD_LOGIC; signal grp_nfa_get_initials_fu_356_ap_start : STD_LOGIC; signal grp_nfa_get_initials_fu_356_ap_done : STD_LOGIC; signal grp_nfa_get_initials_fu_356_ap_idle : STD_LOGIC; signal grp_nfa_get_initials_fu_356_ap_ready : STD_LOGIC; signal grp_nfa_get_initials_fu_356_nfa_initials_buckets_req_din : STD_LOGIC; signal grp_nfa_get_initials_fu_356_nfa_initials_buckets_req_full_n : STD_LOGIC; signal grp_nfa_get_initials_fu_356_nfa_initials_buckets_req_write : STD_LOGIC; signal grp_nfa_get_initials_fu_356_nfa_initials_buckets_rsp_empty_n : STD_LOGIC; signal grp_nfa_get_initials_fu_356_nfa_initials_buckets_rsp_read : STD_LOGIC; signal grp_nfa_get_initials_fu_356_nfa_initials_buckets_address : STD_LOGIC_VECTOR (31 downto 0); signal grp_nfa_get_initials_fu_356_nfa_initials_buckets_datain : STD_LOGIC_VECTOR (31 downto 0); signal grp_nfa_get_initials_fu_356_nfa_initials_buckets_dataout : STD_LOGIC_VECTOR (31 downto 0); signal grp_nfa_get_initials_fu_356_nfa_initials_buckets_size : STD_LOGIC_VECTOR (31 downto 0); signal grp_nfa_get_initials_fu_356_ap_ce : STD_LOGIC; signal grp_nfa_get_initials_fu_356_ap_return_0 : STD_LOGIC_VECTOR (31 downto 0); signal grp_nfa_get_initials_fu_356_ap_return_1 : STD_LOGIC_VECTOR (31 downto 0); signal grp_nfa_get_finals_fu_362_ap_start : STD_LOGIC; signal grp_nfa_get_finals_fu_362_ap_done : STD_LOGIC; signal grp_nfa_get_finals_fu_362_ap_idle : STD_LOGIC; signal grp_nfa_get_finals_fu_362_ap_ready : STD_LOGIC; signal grp_nfa_get_finals_fu_362_nfa_finals_buckets_req_din : STD_LOGIC; signal grp_nfa_get_finals_fu_362_nfa_finals_buckets_req_full_n : STD_LOGIC; signal grp_nfa_get_finals_fu_362_nfa_finals_buckets_req_write : STD_LOGIC; signal grp_nfa_get_finals_fu_362_nfa_finals_buckets_rsp_empty_n : STD_LOGIC; signal grp_nfa_get_finals_fu_362_nfa_finals_buckets_rsp_read : STD_LOGIC; signal grp_nfa_get_finals_fu_362_nfa_finals_buckets_address : STD_LOGIC_VECTOR (31 downto 0); signal grp_nfa_get_finals_fu_362_nfa_finals_buckets_datain : STD_LOGIC_VECTOR (31 downto 0); signal grp_nfa_get_finals_fu_362_nfa_finals_buckets_dataout : STD_LOGIC_VECTOR (31 downto 0); signal grp_nfa_get_finals_fu_362_nfa_finals_buckets_size : STD_LOGIC_VECTOR (31 downto 0); signal grp_nfa_get_finals_fu_362_ap_ce : STD_LOGIC; signal grp_nfa_get_finals_fu_362_ap_return_0 : STD_LOGIC_VECTOR (31 downto 0); signal grp_nfa_get_finals_fu_362_ap_return_1 : STD_LOGIC_VECTOR (31 downto 0); signal grp_p_bsf32_hw_fu_368_bus_r : STD_LOGIC_VECTOR (31 downto 0); signal grp_p_bsf32_hw_fu_368_ap_ce : STD_LOGIC; signal i_reg_134 : STD_LOGIC_VECTOR (15 downto 0); signal any_phi_fu_324_p4 : STD_LOGIC_VECTOR (0 downto 0); signal p_01_rec_reg_146 : STD_LOGIC_VECTOR (31 downto 0); signal next_buckets_1_reg_158 : STD_LOGIC_VECTOR (31 downto 0); signal next_buckets_0_reg_168 : STD_LOGIC_VECTOR (31 downto 0); signal bus_assign_reg_178 : STD_LOGIC_VECTOR (31 downto 0); signal agg_result_bucket_index_0_lcssa4_i_reg_190 : STD_LOGIC_VECTOR (0 downto 0); signal j_bucket1_ph_reg_203 : STD_LOGIC_VECTOR (31 downto 0); signal j_bucket_index1_ph_reg_216 : STD_LOGIC_VECTOR (1 downto 0); signal j_bit1_ph_reg_227 : STD_LOGIC_VECTOR (4 downto 0); signal j_end_ph_reg_238 : STD_LOGIC_VECTOR (0 downto 0); signal tmp_buckets_1_3_reg_252 : STD_LOGIC_VECTOR (31 downto 0); signal tmp_buckets_0_3_reg_265 : STD_LOGIC_VECTOR (31 downto 0); signal j_bucket1_reg_278 : STD_LOGIC_VECTOR (31 downto 0); signal j_bucket_index1_reg_289 : STD_LOGIC_VECTOR (7 downto 0); signal j_bit1_reg_299 : STD_LOGIC_VECTOR (7 downto 0); signal j_end_reg_309 : STD_LOGIC_VECTOR (0 downto 0); signal any_reg_319 : STD_LOGIC_VECTOR (0 downto 0); signal p_0_reg_332 : STD_LOGIC_VECTOR (0 downto 0); signal ap_NS_fsm : STD_LOGIC_VECTOR (5 downto 0); signal grp_nfa_get_finals_fu_362_ap_start_ap_start_reg : STD_LOGIC := '0'; signal grp_fu_392_p2 : STD_LOGIC_VECTOR (31 downto 0); signal tmp_4_i_cast_fu_509_p1 : STD_LOGIC_VECTOR (31 downto 0); signal tmp_8_i_cast_fu_527_p1 : STD_LOGIC_VECTOR (31 downto 0); signal grp_fu_392_p0 : STD_LOGIC_VECTOR (31 downto 0); signal grp_fu_392_p1 : STD_LOGIC_VECTOR (31 downto 0); signal grp_fu_402_p0 : STD_LOGIC_VECTOR (15 downto 0); signal grp_fu_402_p1 : STD_LOGIC_VECTOR (15 downto 0); signal grp_fu_414_p0 : STD_LOGIC_VECTOR (31 downto 0); signal grp_fu_414_p1 : STD_LOGIC_VECTOR (31 downto 0); signal tmp_5_fu_447_p1 : STD_LOGIC_VECTOR (0 downto 0); signal grp_fu_463_p0 : STD_LOGIC_VECTOR (5 downto 0); signal grp_fu_463_p1 : STD_LOGIC_VECTOR (5 downto 0); signal grp_fu_476_p0 : STD_LOGIC_VECTOR (7 downto 0); signal grp_fu_476_p1 : STD_LOGIC_VECTOR (5 downto 0); signal grp_fu_482_p0 : STD_LOGIC_VECTOR (13 downto 0); signal grp_fu_482_p1 : STD_LOGIC_VECTOR (13 downto 0); signal tmp_4_i_fu_502_p3 : STD_LOGIC_VECTOR (14 downto 0); signal tmp_8_i_fu_520_p3 : STD_LOGIC_VECTOR (14 downto 0); signal grp_fu_392_ce : STD_LOGIC; signal grp_fu_402_ce : STD_LOGIC; signal grp_fu_414_ce : STD_LOGIC; signal grp_fu_463_ce : STD_LOGIC; signal grp_fu_476_ce : STD_LOGIC; signal grp_fu_482_ce : STD_LOGIC; signal ap_return_preg : STD_LOGIC_VECTOR (0 downto 0) := "0"; signal grp_fu_476_p00 : STD_LOGIC_VECTOR (13 downto 0); signal grp_fu_476_p10 : STD_LOGIC_VECTOR (13 downto 0); component bitset_next IS port ( ap_clk : IN STD_LOGIC; ap_rst : IN STD_LOGIC; p_read : IN STD_LOGIC_VECTOR (31 downto 0); r_bit : IN STD_LOGIC_VECTOR (7 downto 0); r_bucket_index : IN STD_LOGIC_VECTOR (7 downto 0); r_bucket : IN STD_LOGIC_VECTOR (31 downto 0); ap_return_0 : OUT STD_LOGIC_VECTOR (7 downto 0); ap_return_1 : OUT STD_LOGIC_VECTOR (7 downto 0); ap_return_2 : OUT STD_LOGIC_VECTOR (31 downto 0); ap_return_3 : OUT STD_LOGIC_VECTOR (0 downto 0); ap_ce : IN STD_LOGIC ); end component; component nfa_get_initials IS port ( ap_clk : IN STD_LOGIC; ap_rst : IN STD_LOGIC; ap_start : IN STD_LOGIC; ap_done : OUT STD_LOGIC; ap_idle : OUT STD_LOGIC; ap_ready : OUT STD_LOGIC; nfa_initials_buckets_req_din : OUT STD_LOGIC; nfa_initials_buckets_req_full_n : IN STD_LOGIC; nfa_initials_buckets_req_write : OUT STD_LOGIC; nfa_initials_buckets_rsp_empty_n : IN STD_LOGIC; nfa_initials_buckets_rsp_read : OUT STD_LOGIC; nfa_initials_buckets_address : OUT STD_LOGIC_VECTOR (31 downto 0); nfa_initials_buckets_datain : IN STD_LOGIC_VECTOR (31 downto 0); nfa_initials_buckets_dataout : OUT STD_LOGIC_VECTOR (31 downto 0); nfa_initials_buckets_size : OUT STD_LOGIC_VECTOR (31 downto 0); ap_ce : IN STD_LOGIC; ap_return_0 : OUT STD_LOGIC_VECTOR (31 downto 0); ap_return_1 : OUT STD_LOGIC_VECTOR (31 downto 0) ); end component; component nfa_get_finals IS port ( ap_clk : IN STD_LOGIC; ap_rst : IN STD_LOGIC; ap_start : IN STD_LOGIC; ap_done : OUT STD_LOGIC; ap_idle : OUT STD_LOGIC; ap_ready : OUT STD_LOGIC; nfa_finals_buckets_req_din : OUT STD_LOGIC; nfa_finals_buckets_req_full_n : IN STD_LOGIC; nfa_finals_buckets_req_write : OUT STD_LOGIC; nfa_finals_buckets_rsp_empty_n : IN STD_LOGIC; nfa_finals_buckets_rsp_read : OUT STD_LOGIC; nfa_finals_buckets_address : OUT STD_LOGIC_VECTOR (31 downto 0); nfa_finals_buckets_datain : IN STD_LOGIC_VECTOR (31 downto 0); nfa_finals_buckets_dataout : OUT STD_LOGIC_VECTOR (31 downto 0); nfa_finals_buckets_size : OUT STD_LOGIC_VECTOR (31 downto 0); ap_ce : IN STD_LOGIC; ap_return_0 : OUT STD_LOGIC_VECTOR (31 downto 0); ap_return_1 : OUT STD_LOGIC_VECTOR (31 downto 0) ); end component; component p_bsf32_hw IS port ( ap_clk : IN STD_LOGIC; ap_rst : IN STD_LOGIC; bus_r : IN STD_LOGIC_VECTOR (31 downto 0); ap_return : OUT STD_LOGIC_VECTOR (4 downto 0); ap_ce : IN STD_LOGIC ); end component; component nfa_accept_samples_generic_hw_add_32ns_32ns_32_8 IS generic ( ID : INTEGER; NUM_STAGE : INTEGER; din0_WIDTH : INTEGER; din1_WIDTH : INTEGER; dout_WIDTH : INTEGER ); port ( clk : IN STD_LOGIC; reset : IN STD_LOGIC; din0 : IN STD_LOGIC_VECTOR (31 downto 0); din1 : IN STD_LOGIC_VECTOR (31 downto 0); ce : IN STD_LOGIC; dout : OUT STD_LOGIC_VECTOR (31 downto 0) ); end component; component nfa_accept_samples_generic_hw_add_16ns_16ns_16_4 IS generic ( ID : INTEGER; NUM_STAGE : INTEGER; din0_WIDTH : INTEGER; din1_WIDTH : INTEGER; dout_WIDTH : INTEGER ); port ( clk : IN STD_LOGIC; reset : IN STD_LOGIC; din0 : IN STD_LOGIC_VECTOR (15 downto 0); din1 : IN STD_LOGIC_VECTOR (15 downto 0); ce : IN STD_LOGIC; dout : OUT STD_LOGIC_VECTOR (15 downto 0) ); end component; component nfa_accept_samples_generic_hw_add_6ns_6ns_6_2 IS generic ( ID : INTEGER; NUM_STAGE : INTEGER; din0_WIDTH : INTEGER; din1_WIDTH : INTEGER; dout_WIDTH : INTEGER ); port ( clk : IN STD_LOGIC; reset : IN STD_LOGIC; din0 : IN STD_LOGIC_VECTOR (5 downto 0); din1 : IN STD_LOGIC_VECTOR (5 downto 0); ce : IN STD_LOGIC; dout : OUT STD_LOGIC_VECTOR (5 downto 0) ); end component; component nfa_accept_samples_generic_hw_mul_8ns_6ns_14_9 IS generic ( ID : INTEGER; NUM_STAGE : INTEGER; din0_WIDTH : INTEGER; din1_WIDTH : INTEGER; dout_WIDTH : INTEGER ); port ( clk : IN STD_LOGIC; reset : IN STD_LOGIC; din0 : IN STD_LOGIC_VECTOR (7 downto 0); din1 : IN STD_LOGIC_VECTOR (5 downto 0); ce : IN STD_LOGIC; dout : OUT STD_LOGIC_VECTOR (13 downto 0) ); end component; component nfa_accept_samples_generic_hw_add_14ns_14ns_14_4 IS generic ( ID : INTEGER; NUM_STAGE : INTEGER; din0_WIDTH : INTEGER; din1_WIDTH : INTEGER; dout_WIDTH : INTEGER ); port ( clk : IN STD_LOGIC; reset : IN STD_LOGIC; din0 : IN STD_LOGIC_VECTOR (13 downto 0); din1 : IN STD_LOGIC_VECTOR (13 downto 0); ce : IN STD_LOGIC; dout : OUT STD_LOGIC_VECTOR (13 downto 0) ); end component; begin grp_bitset_next_fu_344 : component bitset_next port map ( ap_clk => ap_clk, ap_rst => ap_rst, p_read => grp_bitset_next_fu_344_p_read, r_bit => grp_bitset_next_fu_344_r_bit, r_bucket_index => grp_bitset_next_fu_344_r_bucket_index, r_bucket => grp_bitset_next_fu_344_r_bucket, ap_return_0 => grp_bitset_next_fu_344_ap_return_0, ap_return_1 => grp_bitset_next_fu_344_ap_return_1, ap_return_2 => grp_bitset_next_fu_344_ap_return_2, ap_return_3 => grp_bitset_next_fu_344_ap_return_3, ap_ce => grp_bitset_next_fu_344_ap_ce); grp_nfa_get_initials_fu_356 : component nfa_get_initials port map ( ap_clk => ap_clk, ap_rst => ap_rst, ap_start => grp_nfa_get_initials_fu_356_ap_start, ap_done => grp_nfa_get_initials_fu_356_ap_done, ap_idle => grp_nfa_get_initials_fu_356_ap_idle, ap_ready => grp_nfa_get_initials_fu_356_ap_ready, nfa_initials_buckets_req_din => grp_nfa_get_initials_fu_356_nfa_initials_buckets_req_din, nfa_initials_buckets_req_full_n => grp_nfa_get_initials_fu_356_nfa_initials_buckets_req_full_n, nfa_initials_buckets_req_write => grp_nfa_get_initials_fu_356_nfa_initials_buckets_req_write, nfa_initials_buckets_rsp_empty_n => grp_nfa_get_initials_fu_356_nfa_initials_buckets_rsp_empty_n, nfa_initials_buckets_rsp_read => grp_nfa_get_initials_fu_356_nfa_initials_buckets_rsp_read, nfa_initials_buckets_address => grp_nfa_get_initials_fu_356_nfa_initials_buckets_address, nfa_initials_buckets_datain => grp_nfa_get_initials_fu_356_nfa_initials_buckets_datain, nfa_initials_buckets_dataout => grp_nfa_get_initials_fu_356_nfa_initials_buckets_dataout, nfa_initials_buckets_size => grp_nfa_get_initials_fu_356_nfa_initials_buckets_size, ap_ce => grp_nfa_get_initials_fu_356_ap_ce, ap_return_0 => grp_nfa_get_initials_fu_356_ap_return_0, ap_return_1 => grp_nfa_get_initials_fu_356_ap_return_1); grp_nfa_get_finals_fu_362 : component nfa_get_finals port map ( ap_clk => ap_clk, ap_rst => ap_rst, ap_start => grp_nfa_get_finals_fu_362_ap_start, ap_done => grp_nfa_get_finals_fu_362_ap_done, ap_idle => grp_nfa_get_finals_fu_362_ap_idle, ap_ready => grp_nfa_get_finals_fu_362_ap_ready, nfa_finals_buckets_req_din => grp_nfa_get_finals_fu_362_nfa_finals_buckets_req_din, nfa_finals_buckets_req_full_n => grp_nfa_get_finals_fu_362_nfa_finals_buckets_req_full_n, nfa_finals_buckets_req_write => grp_nfa_get_finals_fu_362_nfa_finals_buckets_req_write, nfa_finals_buckets_rsp_empty_n => grp_nfa_get_finals_fu_362_nfa_finals_buckets_rsp_empty_n, nfa_finals_buckets_rsp_read => grp_nfa_get_finals_fu_362_nfa_finals_buckets_rsp_read, nfa_finals_buckets_address => grp_nfa_get_finals_fu_362_nfa_finals_buckets_address, nfa_finals_buckets_datain => grp_nfa_get_finals_fu_362_nfa_finals_buckets_datain, nfa_finals_buckets_dataout => grp_nfa_get_finals_fu_362_nfa_finals_buckets_dataout, nfa_finals_buckets_size => grp_nfa_get_finals_fu_362_nfa_finals_buckets_size, ap_ce => grp_nfa_get_finals_fu_362_ap_ce, ap_return_0 => grp_nfa_get_finals_fu_362_ap_return_0, ap_return_1 => grp_nfa_get_finals_fu_362_ap_return_1); grp_p_bsf32_hw_fu_368 : component p_bsf32_hw port map ( ap_clk => ap_clk, ap_rst => ap_rst, bus_r => grp_p_bsf32_hw_fu_368_bus_r, ap_return => grp_p_bsf32_hw_fu_368_ap_return, ap_ce => grp_p_bsf32_hw_fu_368_ap_ce); nfa_accept_samples_generic_hw_add_32ns_32ns_32_8_U17 : component nfa_accept_samples_generic_hw_add_32ns_32ns_32_8 generic map ( ID => 17, NUM_STAGE => 8, din0_WIDTH => 32, din1_WIDTH => 32, dout_WIDTH => 32) port map ( clk => ap_clk, reset => ap_rst, din0 => grp_fu_392_p0, din1 => grp_fu_392_p1, ce => grp_fu_392_ce, dout => grp_fu_392_p2); nfa_accept_samples_generic_hw_add_16ns_16ns_16_4_U18 : component nfa_accept_samples_generic_hw_add_16ns_16ns_16_4 generic map ( ID => 18, NUM_STAGE => 4, din0_WIDTH => 16, din1_WIDTH => 16, dout_WIDTH => 16) port map ( clk => ap_clk, reset => ap_rst, din0 => grp_fu_402_p0, din1 => grp_fu_402_p1, ce => grp_fu_402_ce, dout => grp_fu_402_p2); nfa_accept_samples_generic_hw_add_32ns_32ns_32_8_U19 : component nfa_accept_samples_generic_hw_add_32ns_32ns_32_8 generic map ( ID => 19, NUM_STAGE => 8, din0_WIDTH => 32, din1_WIDTH => 32, dout_WIDTH => 32) port map ( clk => ap_clk, reset => ap_rst, din0 => grp_fu_414_p0, din1 => grp_fu_414_p1, ce => grp_fu_414_ce, dout => grp_fu_414_p2); nfa_accept_samples_generic_hw_add_6ns_6ns_6_2_U20 : component nfa_accept_samples_generic_hw_add_6ns_6ns_6_2 generic map ( ID => 20, NUM_STAGE => 2, din0_WIDTH => 6, din1_WIDTH => 6, dout_WIDTH => 6) port map ( clk => ap_clk, reset => ap_rst, din0 => grp_fu_463_p0, din1 => grp_fu_463_p1, ce => grp_fu_463_ce, dout => grp_fu_463_p2); nfa_accept_samples_generic_hw_mul_8ns_6ns_14_9_U21 : component nfa_accept_samples_generic_hw_mul_8ns_6ns_14_9 generic map ( ID => 21, NUM_STAGE => 9, din0_WIDTH => 8, din1_WIDTH => 6, dout_WIDTH => 14) port map ( clk => ap_clk, reset => ap_rst, din0 => grp_fu_476_p0, din1 => grp_fu_476_p1, ce => grp_fu_476_ce, dout => grp_fu_476_p2); nfa_accept_samples_generic_hw_add_14ns_14ns_14_4_U22 : component nfa_accept_samples_generic_hw_add_14ns_14ns_14_4 generic map ( ID => 22, NUM_STAGE => 4, din0_WIDTH => 14, din1_WIDTH => 14, dout_WIDTH => 14) port map ( clk => ap_clk, reset => ap_rst, din0 => grp_fu_482_p0, din1 => grp_fu_482_p1, ce => grp_fu_482_ce, dout => grp_fu_482_p2); -- the current state (ap_CS_fsm) of the state machine. -- ap_CS_fsm_assign_proc : process(ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (ap_rst = '1') then ap_CS_fsm <= ap_ST_st1_fsm_0; else ap_CS_fsm <= ap_NS_fsm; end if; end if; end process; -- ap_return_preg assign process. -- ap_return_preg_assign_proc : process(ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (ap_rst = '1') then ap_return_preg <= ap_const_lv1_0; else if ((ap_ST_st50_fsm_49 = ap_CS_fsm)) then ap_return_preg <= p_0_reg_332; end if; end if; end if; end process; -- grp_nfa_get_finals_fu_362_ap_start_ap_start_reg assign process. -- grp_nfa_get_finals_fu_362_ap_start_ap_start_reg_assign_proc : process(ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (ap_rst = '1') then grp_nfa_get_finals_fu_362_ap_start_ap_start_reg <= ap_const_logic_0; else if (((ap_ST_st12_fsm_11 = ap_NS_fsm) and (ap_ST_st11_fsm_10 = ap_CS_fsm) and (tmp_s_reg_597 = ap_const_lv1_0))) then grp_nfa_get_finals_fu_362_ap_start_ap_start_reg <= ap_const_logic_1; elsif ((ap_const_logic_1 = grp_nfa_get_finals_fu_362_ap_ready)) then grp_nfa_get_finals_fu_362_ap_start_ap_start_reg <= ap_const_logic_0; end if; end if; end if; end process; -- agg_result_bucket_index_0_lcssa4_i_reg_190 assign process. -- agg_result_bucket_index_0_lcssa4_i_reg_190_assign_proc : process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((ap_ST_st20_fsm_19 = ap_CS_fsm) and (tmp_17_1_i_reg_626 = ap_const_lv1_0))) then agg_result_bucket_index_0_lcssa4_i_reg_190 <= ap_const_lv1_1; elsif (((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((sample_rsp_empty_n = ap_const_logic_0)) and (tmp_17_i_reg_612 = ap_const_lv1_0))) then agg_result_bucket_index_0_lcssa4_i_reg_190 <= ap_const_lv1_0; end if; end if; end process; -- any_reg_319 assign process. -- any_reg_319_assign_proc : process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if ((ap_ST_st24_fsm_23 = ap_CS_fsm)) then any_reg_319 <= ap_const_lv1_0; elsif ((ap_ST_st43_fsm_42 = ap_CS_fsm)) then any_reg_319 <= ap_const_lv1_1; end if; end if; end process; -- bus_assign_reg_178 assign process. -- bus_assign_reg_178_assign_proc : process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((ap_ST_st20_fsm_19 = ap_CS_fsm) and (tmp_17_1_i_reg_626 = ap_const_lv1_0))) then bus_assign_reg_178 <= next_buckets_1_reg_158; elsif (((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((sample_rsp_empty_n = ap_const_logic_0)) and (tmp_17_i_reg_612 = ap_const_lv1_0))) then bus_assign_reg_178 <= next_buckets_0_reg_168; end if; end if; end process; -- i_reg_134 assign process. -- i_reg_134_assign_proc : process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((ap_ST_st25_fsm_24 = ap_CS_fsm) and not((ap_const_lv1_0 = j_end_phi_fu_312_p4)) and not((ap_const_lv1_0 = any_phi_fu_324_p4)))) then i_reg_134 <= i_1_reg_601; elsif ((ap_ST_st4_fsm_3 = ap_CS_fsm)) then i_reg_134 <= ap_const_lv16_0; end if; end if; end process; -- j_bit1_reg_299 assign process. -- j_bit1_reg_299_assign_proc : process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if ((ap_ST_st24_fsm_23 = ap_CS_fsm)) then j_bit1_reg_299 <= j_bit1_ph_cast_fu_440_p1; elsif ((ap_ST_st43_fsm_42 = ap_CS_fsm)) then j_bit1_reg_299 <= j_bit_reg_685; end if; end if; end process; -- j_bucket1_ph_reg_203 assign process. -- j_bucket1_ph_reg_203_assign_proc : process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if ((ap_ST_st23_fsm_22 = ap_CS_fsm)) then j_bucket1_ph_reg_203 <= bus_assign_reg_178; elsif (((ap_ST_st20_fsm_19 = ap_CS_fsm) and not((tmp_17_1_i_reg_626 = ap_const_lv1_0)))) then j_bucket1_ph_reg_203 <= ap_const_lv32_0; end if; end if; end process; -- j_bucket1_reg_278 assign process. -- j_bucket1_reg_278_assign_proc : process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if ((ap_ST_st24_fsm_23 = ap_CS_fsm)) then j_bucket1_reg_278 <= j_bucket1_ph_reg_203; elsif ((ap_ST_st43_fsm_42 = ap_CS_fsm)) then j_bucket1_reg_278 <= j_bucket_reg_695; end if; end if; end process; -- j_bucket_index1_ph_reg_216 assign process. -- j_bucket_index1_ph_reg_216_assign_proc : process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if ((ap_ST_st23_fsm_22 = ap_CS_fsm)) then j_bucket_index1_ph_reg_216 <= agg_result_bucket_index_0_lcssa4_i_cast_cast_fu_432_p1; elsif (((ap_ST_st20_fsm_19 = ap_CS_fsm) and not((tmp_17_1_i_reg_626 = ap_const_lv1_0)))) then j_bucket_index1_ph_reg_216 <= ap_const_lv2_2; end if; end if; end process; -- j_bucket_index1_reg_289 assign process. -- j_bucket_index1_reg_289_assign_proc : process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if ((ap_ST_st24_fsm_23 = ap_CS_fsm)) then j_bucket_index1_reg_289 <= j_bucket_index1_ph_cast_fu_436_p1; elsif ((ap_ST_st43_fsm_42 = ap_CS_fsm)) then j_bucket_index1_reg_289 <= j_bucket_index_reg_690; end if; end if; end process; -- j_end_ph_reg_238 assign process. -- j_end_ph_reg_238_assign_proc : process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if ((ap_ST_st23_fsm_22 = ap_CS_fsm)) then j_end_ph_reg_238 <= ap_const_lv1_0; elsif (((ap_ST_st20_fsm_19 = ap_CS_fsm) and not((tmp_17_1_i_reg_626 = ap_const_lv1_0)))) then j_end_ph_reg_238 <= ap_const_lv1_1; end if; end if; end process; -- j_end_reg_309 assign process. -- j_end_reg_309_assign_proc : process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if ((ap_ST_st24_fsm_23 = ap_CS_fsm)) then j_end_reg_309 <= j_end_ph_reg_238; elsif ((ap_ST_st43_fsm_42 = ap_CS_fsm)) then j_end_reg_309 <= p_s_reg_700; end if; end if; end process; -- next_buckets_0_reg_168 assign process. -- next_buckets_0_reg_168_assign_proc : process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((ap_ST_st25_fsm_24 = ap_CS_fsm) and not((ap_const_lv1_0 = j_end_phi_fu_312_p4)) and not((ap_const_lv1_0 = any_phi_fu_324_p4)))) then next_buckets_0_reg_168 <= tmp_buckets_0_3_reg_265; elsif ((ap_ST_st4_fsm_3 = ap_CS_fsm)) then next_buckets_0_reg_168 <= current_buckets_0_reg_577; end if; end if; end process; -- next_buckets_1_reg_158 assign process. -- next_buckets_1_reg_158_assign_proc : process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((ap_ST_st25_fsm_24 = ap_CS_fsm) and not((ap_const_lv1_0 = j_end_phi_fu_312_p4)) and not((ap_const_lv1_0 = any_phi_fu_324_p4)))) then next_buckets_1_reg_158 <= tmp_buckets_1_3_reg_252; elsif ((ap_ST_st4_fsm_3 = ap_CS_fsm)) then next_buckets_1_reg_158 <= current_buckets_1_reg_582; end if; end if; end process; -- p_01_rec_reg_146 assign process. -- p_01_rec_reg_146_assign_proc : process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((ap_ST_st25_fsm_24 = ap_CS_fsm) and not((ap_const_lv1_0 = j_end_phi_fu_312_p4)) and not((ap_const_lv1_0 = any_phi_fu_324_p4)))) then p_01_rec_reg_146 <= p_rec_reg_616; elsif ((ap_ST_st4_fsm_3 = ap_CS_fsm)) then p_01_rec_reg_146 <= ap_const_lv32_0; end if; end if; end process; -- p_0_reg_332 assign process. -- p_0_reg_332_assign_proc : process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((ap_ST_st25_fsm_24 = ap_CS_fsm) and not((ap_const_lv1_0 = j_end_phi_fu_312_p4)) and (ap_const_lv1_0 = any_phi_fu_324_p4))) then p_0_reg_332 <= ap_const_lv1_0; elsif ((ap_ST_st49_fsm_48 = ap_CS_fsm)) then p_0_reg_332 <= tmp_2_reg_756; end if; end if; end process; -- tmp_buckets_0_3_reg_265 assign process. -- tmp_buckets_0_3_reg_265_assign_proc : process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if ((ap_ST_st24_fsm_23 = ap_CS_fsm)) then tmp_buckets_0_3_reg_265 <= ap_const_lv32_0; elsif ((ap_ST_st43_fsm_42 = ap_CS_fsm)) then tmp_buckets_0_3_reg_265 <= next_buckets_0_1_reg_721; end if; end if; end process; -- tmp_buckets_1_3_reg_252 assign process. -- tmp_buckets_1_3_reg_252_assign_proc : process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if ((ap_ST_st24_fsm_23 = ap_CS_fsm)) then tmp_buckets_1_3_reg_252 <= ap_const_lv32_0; elsif ((ap_ST_st43_fsm_42 = ap_CS_fsm)) then tmp_buckets_1_3_reg_252 <= next_buckets_1_1_fu_544_p2; end if; end if; end process; -- assign process. -- process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if ((ap_ST_st46_fsm_45 = ap_CS_fsm)) then current_buckets_0_1_reg_741 <= current_buckets_0_1_fu_558_p2; current_buckets_1_1_reg_746 <= current_buckets_1_1_fu_563_p2; end if; end if; end process; -- assign process. -- process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if ((ap_ST_st3_fsm_2 = ap_CS_fsm)) then current_buckets_0_reg_577 <= grp_nfa_get_initials_fu_356_ap_return_0; current_buckets_1_reg_582 <= grp_nfa_get_initials_fu_356_ap_return_1; end if; end if; end process; -- assign process. -- process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if ((ap_ST_st8_fsm_7 = ap_CS_fsm)) then i_1_reg_601 <= grp_fu_402_p2; end if; end if; end process; -- assign process. -- process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if ((ap_ST_st23_fsm_22 = ap_CS_fsm)) then j_bit1_ph_reg_227 <= r_bit_reg_630; end if; end if; end process; -- assign process. -- process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if ((ap_ST_st36_fsm_35 = ap_CS_fsm)) then j_bit_reg_685 <= grp_bitset_next_fu_344_ap_return_0; j_bucket_index_reg_690 <= grp_bitset_next_fu_344_ap_return_1; j_bucket_reg_695 <= grp_bitset_next_fu_344_ap_return_2; p_s_reg_700 <= grp_bitset_next_fu_344_ap_return_3; end if; end if; end process; -- assign process. -- process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if ((not((nfa_forward_buckets_rsp_empty_n = ap_const_logic_0)) and (ap_ST_st42_fsm_41 = ap_CS_fsm))) then next_buckets_0_1_reg_721 <= next_buckets_0_1_fu_538_p2; end if; end if; end process; -- assign process. -- process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if ((ap_ST_st39_fsm_38 = ap_CS_fsm)) then offset_i_reg_705 <= grp_fu_482_p2; end if; end if; end process; -- assign process. -- process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((sample_rsp_empty_n = ap_const_logic_0)))) then p_rec_reg_616 <= grp_fu_414_p2; sym_reg_621 <= sample_datain; end if; end if; end process; -- assign process. -- process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if ((ap_ST_st22_fsm_21 = ap_CS_fsm)) then r_bit_reg_630 <= grp_p_bsf32_hw_fu_368_ap_return; end if; end if; end process; -- assign process. -- process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if ((((ap_ST_st41_fsm_40 = ap_CS_fsm) and not((nfa_forward_buckets_rsp_empty_n = ap_const_logic_0))) or (not((nfa_forward_buckets_rsp_empty_n = ap_const_logic_0)) and (ap_ST_st42_fsm_41 = ap_CS_fsm)))) then reg_374 <= nfa_forward_buckets_datain; end if; end if; end process; -- assign process. -- process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if ((ap_ST_st12_fsm_11 = ap_CS_fsm)) then sample_addr_1_reg_606 <= grp_fu_392_p2; end if; end if; end process; -- assign process. -- process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if ((ap_ST_st26_fsm_25 = ap_CS_fsm)) then state_reg_665 <= grp_fu_463_p2; end if; end if; end process; -- assign process. -- process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((sample_rsp_empty_n = ap_const_logic_0)) and not((tmp_17_i_reg_612 = ap_const_lv1_0)))) then tmp_17_1_i_reg_626 <= tmp_17_1_i_fu_426_p2; end if; end if; end process; -- assign process. -- process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if ((ap_ST_st18_fsm_17 = ap_CS_fsm)) then tmp_17_i_reg_612 <= tmp_17_i_fu_420_p2; end if; end if; end process; -- assign process. -- process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if ((ap_ST_st47_fsm_46 = ap_CS_fsm)) then tmp_1_reg_751 <= tmp_1_fu_568_p2; end if; end if; end process; -- assign process. -- process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if ((ap_ST_st48_fsm_47 = ap_CS_fsm)) then tmp_2_reg_756 <= tmp_2_fu_572_p2; end if; end if; end process; -- assign process. -- process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if ((ap_ST_st35_fsm_34 = ap_CS_fsm)) then tmp_6_i_reg_680 <= grp_fu_476_p2; end if; end if; end process; -- assign process. -- process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if ((ap_ST_st24_fsm_23 = ap_CS_fsm)) then tmp_7_i_cast_reg_650(0) <= tmp_7_i_cast_fu_444_p1(0); tmp_7_i_cast_reg_650(1) <= tmp_7_i_cast_fu_444_p1(1); tmp_7_i_cast_reg_650(2) <= tmp_7_i_cast_fu_444_p1(2); tmp_7_i_cast_reg_650(3) <= tmp_7_i_cast_fu_444_p1(3); tmp_7_i_cast_reg_650(4) <= tmp_7_i_cast_fu_444_p1(4); tmp_7_i_cast_reg_650(5) <= tmp_7_i_cast_fu_444_p1(5); tmp_7_i_cast_reg_650(6) <= tmp_7_i_cast_fu_444_p1(6); tmp_7_i_cast_reg_650(7) <= tmp_7_i_cast_fu_444_p1(7); end if; end if; end process; -- assign process. -- process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if ((ap_ST_st45_fsm_44 = ap_CS_fsm)) then tmp_buckets_0_reg_731 <= grp_nfa_get_finals_fu_362_ap_return_0; tmp_buckets_1_reg_736 <= grp_nfa_get_finals_fu_362_ap_return_1; end if; end if; end process; -- assign process. -- process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if ((ap_ST_st5_fsm_4 = ap_CS_fsm)) then tmp_s_reg_597 <= tmp_s_fu_397_p2; end if; end if; end process; tmp_7_i_cast_reg_650(13 downto 8) <= "000000"; -- the next state (ap_NS_fsm) of the state machine. -- ap_NS_fsm_assign_proc : process (ap_start , ap_CS_fsm , nfa_forward_buckets_rsp_empty_n , sample_rsp_empty_n , tmp_s_reg_597 , tmp_17_i_reg_612 , tmp_17_1_i_reg_626 , j_end_phi_fu_312_p4 , any_phi_fu_324_p4) begin case ap_CS_fsm is when ap_ST_st1_fsm_0 => if (not((ap_start = ap_const_logic_0))) then ap_NS_fsm <= ap_ST_st2_fsm_1; else ap_NS_fsm <= ap_ST_st1_fsm_0; end if; when ap_ST_st2_fsm_1 => ap_NS_fsm <= ap_ST_st3_fsm_2; when ap_ST_st3_fsm_2 => ap_NS_fsm <= ap_ST_st4_fsm_3; when ap_ST_st4_fsm_3 => ap_NS_fsm <= ap_ST_st5_fsm_4; when ap_ST_st5_fsm_4 => ap_NS_fsm <= ap_ST_st6_fsm_5; when ap_ST_st6_fsm_5 => ap_NS_fsm <= ap_ST_st7_fsm_6; when ap_ST_st7_fsm_6 => ap_NS_fsm <= ap_ST_st8_fsm_7; when ap_ST_st8_fsm_7 => ap_NS_fsm <= ap_ST_st9_fsm_8; when ap_ST_st9_fsm_8 => ap_NS_fsm <= ap_ST_st10_fsm_9; when ap_ST_st10_fsm_9 => ap_NS_fsm <= ap_ST_st11_fsm_10; when ap_ST_st11_fsm_10 => ap_NS_fsm <= ap_ST_st12_fsm_11; when ap_ST_st12_fsm_11 => if ((tmp_s_reg_597 = ap_const_lv1_0)) then ap_NS_fsm <= ap_ST_st44_fsm_43; else ap_NS_fsm <= ap_ST_st13_fsm_12; end if; when ap_ST_st13_fsm_12 => ap_NS_fsm <= ap_ST_st14_fsm_13; when ap_ST_st14_fsm_13 => ap_NS_fsm <= ap_ST_st15_fsm_14; when ap_ST_st15_fsm_14 => ap_NS_fsm <= ap_ST_st16_fsm_15; when ap_ST_st16_fsm_15 => ap_NS_fsm <= ap_ST_st17_fsm_16; when ap_ST_st17_fsm_16 => ap_NS_fsm <= ap_ST_st18_fsm_17; when ap_ST_st18_fsm_17 => ap_NS_fsm <= ap_ST_st19_fsm_18; when ap_ST_st19_fsm_18 => if ((not((sample_rsp_empty_n = ap_const_logic_0)) and (tmp_17_i_reg_612 = ap_const_lv1_0))) then ap_NS_fsm <= ap_ST_st21_fsm_20; elsif ((not((sample_rsp_empty_n = ap_const_logic_0)) and not((tmp_17_i_reg_612 = ap_const_lv1_0)))) then ap_NS_fsm <= ap_ST_st20_fsm_19; else ap_NS_fsm <= ap_ST_st19_fsm_18; end if; when ap_ST_st20_fsm_19 => if (not((tmp_17_1_i_reg_626 = ap_const_lv1_0))) then ap_NS_fsm <= ap_ST_st24_fsm_23; else ap_NS_fsm <= ap_ST_st21_fsm_20; end if; when ap_ST_st21_fsm_20 => ap_NS_fsm <= ap_ST_st22_fsm_21; when ap_ST_st22_fsm_21 => ap_NS_fsm <= ap_ST_st23_fsm_22; when ap_ST_st23_fsm_22 => ap_NS_fsm <= ap_ST_st24_fsm_23; when ap_ST_st24_fsm_23 => ap_NS_fsm <= ap_ST_st25_fsm_24; when ap_ST_st25_fsm_24 => if ((not((ap_const_lv1_0 = j_end_phi_fu_312_p4)) and not((ap_const_lv1_0 = any_phi_fu_324_p4)))) then ap_NS_fsm <= ap_ST_st5_fsm_4; elsif ((not((ap_const_lv1_0 = j_end_phi_fu_312_p4)) and (ap_const_lv1_0 = any_phi_fu_324_p4))) then ap_NS_fsm <= ap_ST_st50_fsm_49; else ap_NS_fsm <= ap_ST_st26_fsm_25; end if; when ap_ST_st26_fsm_25 => ap_NS_fsm <= ap_ST_st27_fsm_26; when ap_ST_st27_fsm_26 => ap_NS_fsm <= ap_ST_st28_fsm_27; when ap_ST_st28_fsm_27 => ap_NS_fsm <= ap_ST_st29_fsm_28; when ap_ST_st29_fsm_28 => ap_NS_fsm <= ap_ST_st30_fsm_29; when ap_ST_st30_fsm_29 => ap_NS_fsm <= ap_ST_st31_fsm_30; when ap_ST_st31_fsm_30 => ap_NS_fsm <= ap_ST_st32_fsm_31; when ap_ST_st32_fsm_31 => ap_NS_fsm <= ap_ST_st33_fsm_32; when ap_ST_st33_fsm_32 => ap_NS_fsm <= ap_ST_st34_fsm_33; when ap_ST_st34_fsm_33 => ap_NS_fsm <= ap_ST_st35_fsm_34; when ap_ST_st35_fsm_34 => ap_NS_fsm <= ap_ST_st36_fsm_35; when ap_ST_st36_fsm_35 => ap_NS_fsm <= ap_ST_st37_fsm_36; when ap_ST_st37_fsm_36 => ap_NS_fsm <= ap_ST_st38_fsm_37; when ap_ST_st38_fsm_37 => ap_NS_fsm <= ap_ST_st39_fsm_38; when ap_ST_st39_fsm_38 => ap_NS_fsm <= ap_ST_st40_fsm_39; when ap_ST_st40_fsm_39 => ap_NS_fsm <= ap_ST_st41_fsm_40; when ap_ST_st41_fsm_40 => if (not((nfa_forward_buckets_rsp_empty_n = ap_const_logic_0))) then ap_NS_fsm <= ap_ST_st42_fsm_41; else ap_NS_fsm <= ap_ST_st41_fsm_40; end if; when ap_ST_st42_fsm_41 => if (not((nfa_forward_buckets_rsp_empty_n = ap_const_logic_0))) then ap_NS_fsm <= ap_ST_st43_fsm_42; else ap_NS_fsm <= ap_ST_st42_fsm_41; end if; when ap_ST_st43_fsm_42 => ap_NS_fsm <= ap_ST_st25_fsm_24; when ap_ST_st44_fsm_43 => ap_NS_fsm <= ap_ST_st45_fsm_44; when ap_ST_st45_fsm_44 => ap_NS_fsm <= ap_ST_st46_fsm_45; when ap_ST_st46_fsm_45 => ap_NS_fsm <= ap_ST_st47_fsm_46; when ap_ST_st47_fsm_46 => ap_NS_fsm <= ap_ST_st48_fsm_47; when ap_ST_st48_fsm_47 => ap_NS_fsm <= ap_ST_st49_fsm_48; when ap_ST_st49_fsm_48 => ap_NS_fsm <= ap_ST_st50_fsm_49; when ap_ST_st50_fsm_49 => ap_NS_fsm <= ap_ST_st1_fsm_0; when others => ap_NS_fsm <= "XXXXXX"; end case; end process; agg_result_bucket_index_0_lcssa4_i_cast_cast_fu_432_p1 <= std_logic_vector(resize(unsigned(agg_result_bucket_index_0_lcssa4_i_reg_190),2)); any_phi_fu_324_p4 <= any_reg_319; -- ap_done assign process. -- ap_done_assign_proc : process(ap_start, ap_CS_fsm) begin if (((not((ap_const_logic_1 = ap_start)) and (ap_ST_st1_fsm_0 = ap_CS_fsm)) or (ap_ST_st50_fsm_49 = ap_CS_fsm))) then ap_done <= ap_const_logic_1; else ap_done <= ap_const_logic_0; end if; end process; -- ap_idle assign process. -- ap_idle_assign_proc : process(ap_start, ap_CS_fsm) begin if ((not((ap_const_logic_1 = ap_start)) and (ap_ST_st1_fsm_0 = ap_CS_fsm))) then ap_idle <= ap_const_logic_1; else ap_idle <= ap_const_logic_0; end if; end process; -- ap_ready assign process. -- ap_ready_assign_proc : process(ap_CS_fsm) begin if ((ap_ST_st50_fsm_49 = ap_CS_fsm)) then ap_ready <= ap_const_logic_1; else ap_ready <= ap_const_logic_0; end if; end process; -- ap_return assign process. -- ap_return_assign_proc : process(ap_CS_fsm, p_0_reg_332, ap_return_preg) begin if ((ap_ST_st50_fsm_49 = ap_CS_fsm)) then ap_return <= p_0_reg_332; else ap_return <= ap_return_preg; end if; end process; current_buckets_0_1_fu_558_p2 <= (next_buckets_0_reg_168 and tmp_buckets_0_reg_731); current_buckets_1_1_fu_563_p2 <= (next_buckets_1_reg_158 and tmp_buckets_1_reg_736); -- grp_bitset_next_fu_344_ap_ce assign process. -- grp_bitset_next_fu_344_ap_ce_assign_proc : process(ap_CS_fsm, j_end_phi_fu_312_p4) begin if ((((ap_ST_st25_fsm_24 = ap_CS_fsm) and (ap_const_lv1_0 = j_end_phi_fu_312_p4)) or (ap_ST_st26_fsm_25 = ap_CS_fsm) or (ap_ST_st27_fsm_26 = ap_CS_fsm) or (ap_ST_st35_fsm_34 = ap_CS_fsm) or (ap_ST_st36_fsm_35 = ap_CS_fsm) or (ap_ST_st28_fsm_27 = ap_CS_fsm) or (ap_ST_st29_fsm_28 = ap_CS_fsm) or (ap_ST_st30_fsm_29 = ap_CS_fsm) or (ap_ST_st31_fsm_30 = ap_CS_fsm) or (ap_ST_st32_fsm_31 = ap_CS_fsm) or (ap_ST_st33_fsm_32 = ap_CS_fsm) or (ap_ST_st34_fsm_33 = ap_CS_fsm))) then grp_bitset_next_fu_344_ap_ce <= ap_const_logic_1; else grp_bitset_next_fu_344_ap_ce <= ap_const_logic_0; end if; end process; grp_bitset_next_fu_344_p_read <= next_buckets_1_reg_158; grp_bitset_next_fu_344_r_bit <= j_bit1_reg_299; grp_bitset_next_fu_344_r_bucket <= j_bucket1_reg_278; grp_bitset_next_fu_344_r_bucket_index <= j_bucket_index1_reg_289; grp_fu_392_ce <= ap_const_logic_1; grp_fu_392_p0 <= p_01_rec_reg_146; grp_fu_392_p1 <= empty; grp_fu_402_ce <= ap_const_logic_1; grp_fu_402_p0 <= i_reg_134; grp_fu_402_p1 <= ap_const_lv16_1; -- grp_fu_414_ce assign process. -- grp_fu_414_ce_assign_proc : process(ap_CS_fsm, sample_rsp_empty_n, tmp_s_reg_597) begin if (((ap_ST_st18_fsm_17 = ap_CS_fsm) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((sample_rsp_empty_n = ap_const_logic_0))) or ((ap_ST_st12_fsm_11 = ap_CS_fsm) and not((tmp_s_reg_597 = ap_const_lv1_0))) or (ap_ST_st13_fsm_12 = ap_CS_fsm) or (ap_ST_st14_fsm_13 = ap_CS_fsm) or (ap_ST_st15_fsm_14 = ap_CS_fsm) or (ap_ST_st16_fsm_15 = ap_CS_fsm) or (ap_ST_st17_fsm_16 = ap_CS_fsm))) then grp_fu_414_ce <= ap_const_logic_1; else grp_fu_414_ce <= ap_const_logic_0; end if; end process; grp_fu_414_p0 <= p_01_rec_reg_146; grp_fu_414_p1 <= ap_const_lv32_1; grp_fu_463_ce <= ap_const_logic_1; grp_fu_463_p0 <= (tmp_5_fu_447_p1 & ap_const_lv5_0); grp_fu_463_p1 <= j_bit1_reg_299(6 - 1 downto 0); grp_fu_476_ce <= ap_const_logic_1; grp_fu_476_p0 <= grp_fu_476_p00(8 - 1 downto 0); grp_fu_476_p00 <= std_logic_vector(resize(unsigned(nfa_symbols),14)); grp_fu_476_p1 <= grp_fu_476_p10(6 - 1 downto 0); grp_fu_476_p10 <= std_logic_vector(resize(unsigned(state_reg_665),14)); grp_fu_482_ce <= ap_const_logic_1; grp_fu_482_p0 <= tmp_6_i_reg_680; grp_fu_482_p1 <= tmp_7_i_cast_reg_650; grp_nfa_get_finals_fu_362_ap_ce <= ap_const_logic_1; grp_nfa_get_finals_fu_362_ap_start <= grp_nfa_get_finals_fu_362_ap_start_ap_start_reg; grp_nfa_get_finals_fu_362_nfa_finals_buckets_datain <= nfa_finals_buckets_datain; grp_nfa_get_finals_fu_362_nfa_finals_buckets_req_full_n <= nfa_finals_buckets_req_full_n; grp_nfa_get_finals_fu_362_nfa_finals_buckets_rsp_empty_n <= nfa_finals_buckets_rsp_empty_n; grp_nfa_get_initials_fu_356_ap_ce <= ap_const_logic_1; -- grp_nfa_get_initials_fu_356_ap_start assign process. -- grp_nfa_get_initials_fu_356_ap_start_assign_proc : process(ap_start, ap_CS_fsm) begin if (((ap_ST_st1_fsm_0 = ap_CS_fsm) and not((ap_start = ap_const_logic_0)))) then grp_nfa_get_initials_fu_356_ap_start <= ap_const_logic_1; else grp_nfa_get_initials_fu_356_ap_start <= ap_const_logic_0; end if; end process; grp_nfa_get_initials_fu_356_nfa_initials_buckets_datain <= nfa_initials_buckets_datain; grp_nfa_get_initials_fu_356_nfa_initials_buckets_req_full_n <= nfa_initials_buckets_req_full_n; grp_nfa_get_initials_fu_356_nfa_initials_buckets_rsp_empty_n <= nfa_initials_buckets_rsp_empty_n; -- grp_p_bsf32_hw_fu_368_ap_ce assign process. -- grp_p_bsf32_hw_fu_368_ap_ce_assign_proc : process(ap_CS_fsm) begin if (((ap_ST_st22_fsm_21 = ap_CS_fsm) or (ap_ST_st21_fsm_20 = ap_CS_fsm))) then grp_p_bsf32_hw_fu_368_ap_ce <= ap_const_logic_1; else grp_p_bsf32_hw_fu_368_ap_ce <= ap_const_logic_0; end if; end process; grp_p_bsf32_hw_fu_368_bus_r <= bus_assign_reg_178; j_bit1_ph_cast_fu_440_p1 <= std_logic_vector(resize(unsigned(j_bit1_ph_reg_227),8)); j_bucket_index1_ph_cast_fu_436_p1 <= std_logic_vector(resize(unsigned(j_bucket_index1_ph_reg_216),8)); j_end_phi_fu_312_p4 <= j_end_reg_309; next_buckets_0_1_fu_538_p2 <= (tmp_buckets_0_3_reg_265 or reg_374); next_buckets_1_1_fu_544_p2 <= (tmp_buckets_1_3_reg_252 or reg_374); nfa_finals_buckets_address <= grp_nfa_get_finals_fu_362_nfa_finals_buckets_address; nfa_finals_buckets_dataout <= grp_nfa_get_finals_fu_362_nfa_finals_buckets_dataout; nfa_finals_buckets_req_din <= grp_nfa_get_finals_fu_362_nfa_finals_buckets_req_din; nfa_finals_buckets_req_write <= grp_nfa_get_finals_fu_362_nfa_finals_buckets_req_write; nfa_finals_buckets_rsp_read <= grp_nfa_get_finals_fu_362_nfa_finals_buckets_rsp_read; nfa_finals_buckets_size <= grp_nfa_get_finals_fu_362_nfa_finals_buckets_size; -- nfa_forward_buckets_address assign process. -- nfa_forward_buckets_address_assign_proc : process(ap_CS_fsm, nfa_forward_buckets_rsp_empty_n, tmp_4_i_cast_fu_509_p1, tmp_8_i_cast_fu_527_p1) begin if (((ap_ST_st41_fsm_40 = ap_CS_fsm) and not((nfa_forward_buckets_rsp_empty_n = ap_const_logic_0)))) then nfa_forward_buckets_address <= tmp_8_i_cast_fu_527_p1; elsif ((ap_ST_st40_fsm_39 = ap_CS_fsm)) then nfa_forward_buckets_address <= tmp_4_i_cast_fu_509_p1; else nfa_forward_buckets_address <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX"; end if; end process; nfa_forward_buckets_dataout <= ap_const_lv32_0; nfa_forward_buckets_req_din <= ap_const_logic_0; -- nfa_forward_buckets_req_write assign process. -- nfa_forward_buckets_req_write_assign_proc : process(ap_CS_fsm, nfa_forward_buckets_rsp_empty_n) begin if ((((ap_ST_st41_fsm_40 = ap_CS_fsm) and not((nfa_forward_buckets_rsp_empty_n = ap_const_logic_0))) or (ap_ST_st40_fsm_39 = ap_CS_fsm))) then nfa_forward_buckets_req_write <= ap_const_logic_1; else nfa_forward_buckets_req_write <= ap_const_logic_0; end if; end process; -- nfa_forward_buckets_rsp_read assign process. -- nfa_forward_buckets_rsp_read_assign_proc : process(ap_CS_fsm, nfa_forward_buckets_rsp_empty_n) begin if ((((ap_ST_st41_fsm_40 = ap_CS_fsm) and not((nfa_forward_buckets_rsp_empty_n = ap_const_logic_0))) or (not((nfa_forward_buckets_rsp_empty_n = ap_const_logic_0)) and (ap_ST_st42_fsm_41 = ap_CS_fsm)))) then nfa_forward_buckets_rsp_read <= ap_const_logic_1; else nfa_forward_buckets_rsp_read <= ap_const_logic_0; end if; end process; nfa_forward_buckets_size <= ap_const_lv32_1; nfa_initials_buckets_address <= grp_nfa_get_initials_fu_356_nfa_initials_buckets_address; nfa_initials_buckets_dataout <= grp_nfa_get_initials_fu_356_nfa_initials_buckets_dataout; nfa_initials_buckets_req_din <= grp_nfa_get_initials_fu_356_nfa_initials_buckets_req_din; nfa_initials_buckets_req_write <= grp_nfa_get_initials_fu_356_nfa_initials_buckets_req_write; nfa_initials_buckets_rsp_read <= grp_nfa_get_initials_fu_356_nfa_initials_buckets_rsp_read; nfa_initials_buckets_size <= grp_nfa_get_initials_fu_356_nfa_initials_buckets_size; sample_address <= sample_addr_1_reg_606; sample_dataout <= ap_const_lv8_0; sample_req_din <= ap_const_logic_0; -- sample_req_write assign process. -- sample_req_write_assign_proc : process(ap_CS_fsm) begin if ((ap_ST_st18_fsm_17 = ap_CS_fsm)) then sample_req_write <= ap_const_logic_1; else sample_req_write <= ap_const_logic_0; end if; end process; -- sample_rsp_read assign process. -- sample_rsp_read_assign_proc : process(ap_CS_fsm, sample_rsp_empty_n) begin if (((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((sample_rsp_empty_n = ap_const_logic_0)))) then sample_rsp_read <= ap_const_logic_1; else sample_rsp_read <= ap_const_logic_0; end if; end process; sample_size <= ap_const_lv32_1; tmp_17_1_i_fu_426_p2 <= "1" when (next_buckets_1_reg_158 = ap_const_lv32_0) else "0"; tmp_17_i_fu_420_p2 <= "1" when (next_buckets_0_reg_168 = ap_const_lv32_0) else "0"; tmp_1_fu_568_p2 <= (current_buckets_1_1_reg_746 or current_buckets_0_1_reg_741); tmp_2_fu_572_p2 <= "0" when (tmp_1_reg_751 = ap_const_lv32_0) else "1"; tmp_4_i_cast_fu_509_p1 <= std_logic_vector(resize(unsigned(tmp_4_i_fu_502_p3),32)); tmp_4_i_fu_502_p3 <= (offset_i_reg_705 & ap_const_lv1_0); tmp_5_fu_447_p1 <= j_bucket_index1_reg_289(1 - 1 downto 0); tmp_7_i_cast_fu_444_p1 <= std_logic_vector(resize(unsigned(sym_reg_621),14)); tmp_8_i_cast_fu_527_p1 <= std_logic_vector(resize(unsigned(tmp_8_i_fu_520_p3),32)); tmp_8_i_fu_520_p3 <= (offset_i_reg_705 & ap_const_lv1_1); tmp_s_fu_397_p2 <= "1" when (unsigned(i_reg_134) < unsigned(length_r)) else "0"; end behav;
lgpl-3.0
055516ae7254078b03faeb552aec72e1
0.578446
2.765402
false
false
false
false
takeshineshiro/fpga_fibre_scan
HUCB2P0_150701/driver/pulse.vhd
1
4,889
--***************************************************************************** -- @Copyright 2010 by guyoubao, All rights reserved. -- Module name : Pulse control -- Call by : -- Description : -- IC : EP3C16F484C6 -- Version : A -- Note: : -- Author : guyoubao -- Date : 2010.08.28 -- Update : -- 160MHz-- 38M peak, 11-68M -6dB -- O_trig(0-1) -- A1 -- O_trig(14-15) -- A8 -- --***************************************************************************** library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; entity pulse is port ( I_clk : in std_logic; I_reset_n : in std_logic; I_pulse_trig : in std_logic; O_pulse : out std_logic_vector(3 downto 0) ); end pulse; architecture ARC_pulse of pulse is signal S_cnt : std_logic_vector(7 downto 0); signal s_case : std_logic_vector(1 downto 0); signal s_pulse_buf : std_logic; signal s_pulse : std_logic_vector(3 downto 0); begin O_pulse <= s_pulse; process(I_reset_n,I_clk) begin if I_reset_n = '0' then s_case <= (others=>'0'); S_cnt <= (others=>'0'); s_pulse(0) <= '0'; s_pulse(1) <= '1'; s_pulse(2) <= '0'; s_pulse_buf <= '0'; elsif rising_edge(I_clk) then s_pulse_buf <= I_pulse_trig; case s_case is when "00" => if(s_pulse_buf = '0' and I_pulse_trig = '1')then --rise s_case <= "01"; S_cnt <= S_cnt + '1'; else s_case <= (others=>'0'); S_cnt <= (others=>'0'); s_pulse(0) <= '0'; s_pulse(1) <= '0'; s_pulse(2) <= '0'; end if; when "01" => -- 60M时钟,5M发射,6个N6个P6个拉回零,可结合TC8220的发射时序,6个N+6个P=12个周期,60/12=5M,即为发射频率。 S_cnt <= S_cnt + '1'; if(S_cnt >= 5 and S_cnt <= 10)then s_pulse(0) <= '1'; else s_pulse(0) <= '0'; end if; if(S_cnt >= 11 and S_cnt <= 16)then --monocycle, positive first s_pulse(1) <= '1'; else s_pulse(1) <= '0'; end if; if(S_cnt >= 17 and S_cnt <= 22)then s_pulse(2) <= '1'; else s_pulse(2) <= '0'; end if; if(S_cnt = 0)then s_case <= (others=>'0'); end if; when others => s_case <= (others=>'0'); S_cnt <= (others=>'0'); s_pulse(0) <= '0'; s_pulse(1) <= '0'; s_pulse(2) <= '0'; end case; end if; end process; --process(I_reset,I_clk) --begin -- if I_reset = '0' then -- s_case <= (others=>'0'); -- S_cnt <= (others=>'0'); -- s_pulse(0) <= '0'; -- s_pulse(1) <= '1'; -- s_pulse_buf <= '0'; -- elsif rising_edge(I_clk) then -- -- s_pulse_buf <= I_pulse_trig; -- -- case s_case is -- when "00" => -- if(s_pulse_buf = '0' and I_pulse_trig = '1')then -- s_case <= "01"; -- S_cnt <= S_cnt + '1'; -- else -- s_case <= (others=>'0'); -- S_cnt <= (others=>'0'); -- s_pulse(0) <= '0'; -- s_pulse(1) <= '1'; -- end if; -- -- when "01" => -- S_cnt <= S_cnt + '1'; -- if(S_cnt >= 4 and S_cnt <= 5)then --monocycle, positive first 35MHz at 300MHz clk -- s_pulse(1) <= '0'; -- else -- s_pulse(1) <= '1'; -- end if; -- -- if(S_cnt >= 2 and S_cnt <= 3)then -- s_pulse(0) <= '1'; -- else -- s_pulse(0) <= '0'; -- end if; -- -- if(S_cnt = 0)then -- s_case <= (others=>'0'); -- end if; -- -- when others => -- s_case <= (others=>'0'); -- S_cnt <= (others=>'0'); -- s_pulse(0) <= '0'; -- s_pulse(1) <= '1'; -- -- end case; -- -- end if; --end process; end ARC_pulse;
apache-2.0
7c7ec9ea10649ec30c46f265c53bef4b
0.336309
3.162837
false
false
false
false
grwlf/vsim
vhdl_ct/ct00669.vhd
1
7,610
-- NEED RESULT: ARCH00669: Variable default initial values - generic subtypes passed ------------------------------------------------------------------------------- -- -- Copyright (c) 1989 by Intermetrics, Inc. -- All rights reserved. -- ------------------------------------------------------------------------------- -- -- TEST NAME: -- -- CT00669 -- -- AUTHOR: -- -- A. Wilmot -- -- TEST OBJECTIVES: -- -- 4.3.1.3 (1) -- 4.3.1.3 (2) -- 4.3.1.3 (3) -- 4.3.1.3 (4) -- -- DESIGN UNIT ORDERING: -- -- GENERIC_STANDARD_TYPES(ARCH00669) -- ENT00669_Test_Bench(ARCH00669_Test_Bench) -- -- REVISION HISTORY: -- -- 01-SEP-1987 - initial revision -- -- NOTES: -- -- self-checking -- automatically generated -- use WORK.STANDARD_TYPES.all ; -- architecture ARCH00669 of GENERIC_STANDARD_TYPES is begin process variable correct : boolean := true ; variable va_boolean_1 : boolean ; variable va_boolean_2 : boolean := d_boolean ; variable va_bit_1 : bit ; variable va_bit_2 : bit := d_bit ; variable va_severity_level_1 : severity_level ; variable va_severity_level_2 : severity_level := d_severity_level ; variable va_character_1 : character ; variable va_character_2 : character := d_character ; variable va_t_enum1_1 : t_enum1 ; variable va_t_enum1_2 : t_enum1 := d_t_enum1 ; variable va_st_enum1_1 : st_enum1 ; variable va_st_enum1_2 : st_enum1 := d_st_enum1 ; variable va_integer_1 : integer ; variable va_integer_2 : integer := d_integer ; variable va_t_int1_1 : t_int1 ; variable va_t_int1_2 : t_int1 := d_t_int1 ; variable va_st_int1_1 : st_int1 ; variable va_st_int1_2 : st_int1 := d_st_int1 ; variable va_time_1 : time ; variable va_time_2 : time := d_time ; variable va_t_phys1_1 : t_phys1 ; variable va_t_phys1_2 : t_phys1 := d_t_phys1 ; variable va_st_phys1_1 : st_phys1 ; variable va_st_phys1_2 : st_phys1 := d_st_phys1 ; variable va_real_1 : real ; variable va_real_2 : real := d_real ; variable va_t_real1_1 : t_real1 ; variable va_t_real1_2 : t_real1 := d_t_real1 ; variable va_st_real1_1 : st_real1 ; variable va_st_real1_2 : st_real1 := d_st_real1 ; variable va_st_bit_vector_1 : st_bit_vector ; variable va_st_bit_vector_2 : st_bit_vector := d_st_bit_vector ; variable va_st_string_1 : st_string ; variable va_st_string_2 : st_string := d_st_string ; variable va_t_rec1_1 : t_rec1 ; variable va_t_rec1_2 : t_rec1 := d_t_rec1 ; variable va_st_rec1_1 : st_rec1 ; variable va_st_rec1_2 : st_rec1 := d_st_rec1 ; variable va_t_rec2_1 : t_rec2 ; variable va_t_rec2_2 : t_rec2 := d_t_rec2 ; variable va_st_rec2_1 : st_rec2 ; variable va_st_rec2_2 : st_rec2 := d_st_rec2 ; variable va_t_rec3_1 : t_rec3 ; variable va_t_rec3_2 : t_rec3 := d_t_rec3 ; variable va_st_rec3_1 : st_rec3 ; variable va_st_rec3_2 : st_rec3 := d_st_rec3 ; variable va_st_arr1_1 : st_arr1 ; variable va_st_arr1_2 : st_arr1 := d_st_arr1 ; variable va_st_arr2_1 : st_arr2 ; variable va_st_arr2_2 : st_arr2 := d_st_arr2 ; variable va_st_arr3_1 : st_arr3 ; variable va_st_arr3_2 : st_arr3 := d_st_arr3 ; begin correct := correct and va_boolean_1 = va_boolean_2 and va_boolean_2 = d_boolean ; correct := correct and va_bit_1 = va_bit_2 and va_bit_2 = d_bit ; correct := correct and va_severity_level_1 = va_severity_level_2 and va_severity_level_2 = d_severity_level ; correct := correct and va_character_1 = va_character_2 and va_character_2 = d_character ; correct := correct and va_t_enum1_1 = va_t_enum1_2 and va_t_enum1_2 = d_t_enum1 ; correct := correct and va_st_enum1_1 = va_st_enum1_2 and va_st_enum1_2 = d_st_enum1 ; correct := correct and va_integer_1 = va_integer_2 and va_integer_2 = d_integer ; correct := correct and va_t_int1_1 = va_t_int1_2 and va_t_int1_2 = d_t_int1 ; correct := correct and va_st_int1_1 = va_st_int1_2 and va_st_int1_2 = d_st_int1 ; correct := correct and va_time_1 = va_time_2 and va_time_2 = d_time ; correct := correct and va_t_phys1_1 = va_t_phys1_2 and va_t_phys1_2 = d_t_phys1 ; correct := correct and va_st_phys1_1 = va_st_phys1_2 and va_st_phys1_2 = d_st_phys1 ; correct := correct and va_real_1 = va_real_2 and va_real_2 = d_real ; correct := correct and va_t_real1_1 = va_t_real1_2 and va_t_real1_2 = d_t_real1 ; correct := correct and va_st_real1_1 = va_st_real1_2 and va_st_real1_2 = d_st_real1 ; correct := correct and va_st_bit_vector_1 = va_st_bit_vector_2 and va_st_bit_vector_2 = d_st_bit_vector ; correct := correct and va_st_string_1 = va_st_string_2 and va_st_string_2 = d_st_string ; correct := correct and va_t_rec1_1 = va_t_rec1_2 and va_t_rec1_2 = d_t_rec1 ; correct := correct and va_st_rec1_1 = va_st_rec1_2 and va_st_rec1_2 = d_st_rec1 ; correct := correct and va_t_rec2_1 = va_t_rec2_2 and va_t_rec2_2 = d_t_rec2 ; correct := correct and va_st_rec2_1 = va_st_rec2_2 and va_st_rec2_2 = d_st_rec2 ; correct := correct and va_t_rec3_1 = va_t_rec3_2 and va_t_rec3_2 = d_t_rec3 ; correct := correct and va_st_rec3_1 = va_st_rec3_2 and va_st_rec3_2 = d_st_rec3 ; correct := correct and va_st_arr1_1 = va_st_arr1_2 and va_st_arr1_2 = d_st_arr1 ; correct := correct and va_st_arr2_1 = va_st_arr2_2 and va_st_arr2_2 = d_st_arr2 ; correct := correct and va_st_arr3_1 = va_st_arr3_2 and va_st_arr3_2 = d_st_arr3 ; test_report ( "ARCH00669" , "Variable default initial values - generic subtypes" , correct) ; wait ; end process ; end ARCH00669 ; -- entity ENT00669_Test_Bench is end ENT00669_Test_Bench ; -- architecture ARCH00669_Test_Bench of ENT00669_Test_Bench is begin L1: block component UUT end component ; for CIS1 : UUT use entity WORK.GENERIC_STANDARD_TYPES ( ARCH00669 ) ; begin CIS1 : UUT ; end block L1 ; end ARCH00669_Test_Bench ;
gpl-3.0
3ce154c7ebd7f93dfcd20a9d7281722f
0.479895
3.193454
false
false
false
false
jairov4/accel-oil
solution_virtex5/impl/pcores/nfa_accept_samples_generic_hw_top_v1_00_a/synhdl/vhdl/nfa_initials_buckets_if_ap_fifo_af.vhd
2
6,306
-- ============================================================== -- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC -- Version: 2014.1 -- Copyright (C) 2014 Xilinx Inc. All rights reserved. -- -- ============================================================== library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity nfa_initials_buckets_if_ap_fifo_af_ram is generic( mem_style : string := "block"; dwidth : integer := 64; awidth : integer := 6; mem_size : integer := 64 ); port ( clk : in std_logic; din : in std_logic_vector(dwidth-1 downto 0); w_addr : in std_logic_vector(awidth-1 downto 0); we : in std_logic; r_addr : in std_logic_vector(awidth-1 downto 0); dout : out std_logic_vector(dwidth-1 downto 0) ); end entity; architecture rtl of nfa_initials_buckets_if_ap_fifo_af_ram is type mem_array is array (mem_size-1 downto 0) of std_logic_vector (dwidth-1 downto 0); signal mem : mem_array; attribute ram_style : string; attribute ram_style of mem : signal is mem_style; begin p_memory_read: process (clk) begin if (clk = '1' and clk'event) then if (we = '1') then mem(CONV_INTEGER(w_addr)) <= din; end if; dout <= mem(CONV_INTEGER(r_addr)); end if; end process; end rtl; library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; entity nfa_initials_buckets_if_ap_fifo_af is generic ( MEM_STYLE : string := "block"; DATA_WIDTH : integer := 64; ADDR_WIDTH : integer := 6; DEPTH : integer := 64; ALMOST_FULL_MARGIN : integer := 2); port ( clk : IN STD_LOGIC; reset : IN STD_LOGIC; if_empty_n : OUT STD_LOGIC; if_read : IN STD_LOGIC; if_dout : OUT STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0); if_full_n : OUT STD_LOGIC; if_write : IN STD_LOGIC; if_din : IN STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0)); end entity; architecture rtl of nfa_initials_buckets_if_ap_fifo_af is component nfa_initials_buckets_if_ap_fifo_af_ram is generic( mem_style : string := "block"; dwidth : integer := 64; awidth : integer := 6; mem_size : integer := 64 ); port ( clk : in std_logic; din : in std_logic_vector(dwidth-1 downto 0); w_addr : in std_logic_vector(awidth-1 downto 0); we : in std_logic; r_addr : in std_logic_vector(awidth-1 downto 0); dout : out std_logic_vector(dwidth-1 downto 0) ); end component; signal mInPtr, mOutPtr : STD_LOGIC_VECTOR(ADDR_WIDTH - 1 downto 0); signal mInPtr_next, mOutPtr_next : STD_LOGIC_VECTOR(ADDR_WIDTH - 1 downto 0); signal ram_raddr, ram_waddr : STD_LOGIC_VECTOR(ADDR_WIDTH - 1 downto 0); signal ram_din, ram_dout : STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0); signal conflict_buff : STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0); signal conflict_buff_valid : STD_LOGIC; signal ram_we : STD_LOGIC; signal wordUsed : STD_LOGIC_VECTOR(ADDR_WIDTH downto 0); signal internal_empty_n, internal_full_n: STD_LOGIC; begin if_empty_n <= internal_empty_n; if_full_n <= internal_full_n; ram_din <= if_din; process (wordUsed, conflict_buff_valid, conflict_buff, ram_dout) begin if ( wordUsed = 1 and conflict_buff_valid = '1' ) then if_dout <= conflict_buff; else if_dout <= ram_dout; end if; end process; process (mOutPtr) begin if ( mOutPtr < DEPTH -1 ) then mOutPtr_next <= mOutPtr + 1; else mOutPtr_next <= (others => '0'); end if; end process; process (mInPtr) begin if ( mInPtr < DEPTH -1 ) then mInPtr_next <= mInPtr + 1; else mInPtr_next <= (others => '0'); end if; end process; process (clk, reset) begin if reset = '1' then mInPtr <= (others => '0'); mOutPtr <= (others => '0'); wordUsed <= (others => '0'); internal_empty_n <= '0'; internal_full_n <= '1'; conflict_buff <= (others => '0'); conflict_buff_valid <= '0'; else if clk'event and clk = '1' then if if_read = '1' and internal_empty_n = '1' then mOutPtr <= mOutPtr_next; end if; if (if_write = '1') then mInPtr <= mInPtr_next; end if; if (if_read = '1' and internal_empty_n = '1' and if_write = '0') then wordUsed <= wordUsed -1; if (wordUsed = 1) then internal_empty_n <= '0'; end if; internal_full_n <= '1'; elsif (if_read = '0' or internal_empty_n = '0') and (if_write = '1') then wordUsed <= wordUsed +1; internal_empty_n <= '1'; if (wordUsed + ALMOST_FULL_MARGIN = DEPTH -1) then internal_full_n <= '0'; end if; end if; conflict_buff <= if_din; conflict_buff_valid <= if_write and internal_full_n; end if; end if; end process; ram_waddr <= mInPtr; ram_raddr <= mOutPtr_next when if_read = '1' and internal_empty_n = '1' else mOutPtr; -- if a read occur on the following clock edge, prepare next read data in advance ram_we <= if_write; -- caller should check almost_full signal U_nfa_initials_buckets_if_ap_fifo_af_ram : nfa_initials_buckets_if_ap_fifo_af_ram generic map ( mem_style => MEM_STYLE, dwidth => DATA_WIDTH, awidth => ADDR_WIDTH, mem_size => DEPTH) port map ( clk => clk, din => ram_din, w_addr => ram_waddr, we => ram_we, r_addr => ram_raddr, dout => ram_dout); end rtl;
lgpl-3.0
c1b3e391734f9a425a20e907097b4b02
0.517444
3.597262
false
false
false
false
grwlf/vsim
vhdl/IEEE/std_logic_1164.vhdl
1
44,159
-- -------------------------------------------------------------------- -- -- Title : std_logic_1164 multi-value logic system -- Library : This package shall be compiled into a library -- : symbolically named IEEE. -- : -- Developers: IEEE model standards group (par 1164) -- Purpose : This packages defines a standard for designers -- : to use in describing the interconnection data types -- : used in vhdl modeling. -- : -- Limitation: The logic system defined in this package may -- : be insufficient for modeling switched transistors, -- : since such a requirement is out of the scope of this -- : effort. Furthermore, mathematics, primitives, -- : timing standards, etc. are considered orthogonal -- : issues as it relates to this package and are therefore -- : beyond the scope of this effort. -- : -- Note : No declarations or definitions shall be included in, -- : or excluded from this package. The "package declaration" -- : defines the types, subtypes and declarations of -- : std_logic_1164. The std_logic_1164 package body shall be -- : considered the formal definition of the semantics of -- : this package. Tool developers may choose to implement -- : the package body in the most efficient manner available -- : to them. -- : -- -------------------------------------------------------------------- -- modification history : -- -------------------------------------------------------------------- -- version | mod. date:| -- v4.200 | 01/02/92 | -- -------------------------------------------------------------------- PACKAGE std_logic_1164 IS ------------------------------------------------------------------- -- logic state system (unresolved) ------------------------------------------------------------------- TYPE std_ulogic IS ( 'U', -- Uninitialized 'X', -- Forcing Unknown '0', -- Forcing 0 '1', -- Forcing 1 'Z', -- High Impedance 'W', -- Weak Unknown 'L', -- Weak 0 'H', -- Weak 1 '-' -- Don't care ); ------------------------------------------------------------------- -- unconstrained array of std_ulogic for use with the resolution function ------------------------------------------------------------------- TYPE std_ulogic_vector IS ARRAY ( NATURAL RANGE <> ) OF std_ulogic; ------------------------------------------------------------------- -- resolution function ------------------------------------------------------------------- FUNCTION resolved ( s : std_ulogic_vector ) RETURN std_ulogic; ------------------------------------------------------------------- -- *** industry standard logic type *** ------------------------------------------------------------------- SUBTYPE std_logic IS resolved std_ulogic; ------------------------------------------------------------------- -- unconstrained array of std_logic for use in declaring signal arrays ------------------------------------------------------------------- TYPE std_logic_vector IS ARRAY ( NATURAL RANGE <>) OF std_logic; ------------------------------------------------------------------- -- common subtypes ------------------------------------------------------------------- SUBTYPE X01 IS resolved std_ulogic RANGE 'X' TO '1'; -- ('X','0','1') SUBTYPE X01Z IS resolved std_ulogic RANGE 'X' TO 'Z'; -- ('X','0','1','Z') SUBTYPE UX01 IS resolved std_ulogic RANGE 'U' TO '1'; -- ('U','X','0','1') SUBTYPE UX01Z IS resolved std_ulogic RANGE 'U' TO 'Z'; -- ('U','X','0','1','Z') ------------------------------------------------------------------- -- overloaded logical operators ------------------------------------------------------------------- FUNCTION "and" ( l : std_ulogic; r : std_ulogic ) RETURN UX01; FUNCTION "nand" ( l : std_ulogic; r : std_ulogic ) RETURN UX01; FUNCTION "or" ( l : std_ulogic; r : std_ulogic ) RETURN UX01; FUNCTION "nor" ( l : std_ulogic; r : std_ulogic ) RETURN UX01; FUNCTION "xor" ( l : std_ulogic; r : std_ulogic ) RETURN UX01; FUNCTION "xnor" ( l : std_ulogic; r : std_ulogic ) RETURN UX01; --V93 FUNCTION "not" ( l : std_ulogic ) RETURN UX01; ------------------------------------------------------------------- -- vectorized overloaded logical operators ------------------------------------------------------------------- FUNCTION "and" ( l, r : std_logic_vector ) RETURN std_logic_vector; FUNCTION "and" ( l, r : std_ulogic_vector ) RETURN std_ulogic_vector; FUNCTION "nand" ( l, r : std_logic_vector ) RETURN std_logic_vector; FUNCTION "nand" ( l, r : std_ulogic_vector ) RETURN std_ulogic_vector; FUNCTION "or" ( l, r : std_logic_vector ) RETURN std_logic_vector; FUNCTION "or" ( l, r : std_ulogic_vector ) RETURN std_ulogic_vector; FUNCTION "nor" ( l, r : std_logic_vector ) RETURN std_logic_vector; FUNCTION "nor" ( l, r : std_ulogic_vector ) RETURN std_ulogic_vector; FUNCTION "xor" ( l, r : std_logic_vector ) RETURN std_logic_vector; FUNCTION "xor" ( l, r : std_ulogic_vector ) RETURN std_ulogic_vector; -- ----------------------------------------------------------------------- -- Note : The declaration and implementation of the "xnor" function is -- specifically commented until at which time the VHDL language has been -- officially adopted as containing such a function. At such a point, -- the following comments may be removed along with this notice without -- further "official" ballotting of this std_logic_1164 package. It is -- the intent of this effort to provide such a function once it becomes -- available in the VHDL standard. -- ----------------------------------------------------------------------- FUNCTION "xnor" ( l, r : std_logic_vector ) RETURN std_logic_vector; --V93 FUNCTION "xnor" ( l, r : std_ulogic_vector ) RETURN std_ulogic_vector;--V93 FUNCTION "not" ( l : std_logic_vector ) RETURN std_logic_vector; FUNCTION "not" ( l : std_ulogic_vector ) RETURN std_ulogic_vector; ------------------------------------------------------------------- -- conversion functions ------------------------------------------------------------------- FUNCTION To_bit ( s : std_ulogic; xmap : BIT := '0') RETURN BIT; FUNCTION To_bitvector ( s : std_logic_vector ; xmap : BIT := '0') RETURN BIT_VECTOR; FUNCTION To_bitvector ( s : std_ulogic_vector; xmap : BIT := '0') RETURN BIT_VECTOR; FUNCTION To_StdULogic ( b : BIT ) RETURN std_ulogic; FUNCTION To_StdLogicVector ( b : BIT_VECTOR ) RETURN std_logic_vector; FUNCTION To_StdLogicVector ( s : std_ulogic_vector ) RETURN std_logic_vector; FUNCTION To_StdULogicVector ( b : BIT_VECTOR ) RETURN std_ulogic_vector; FUNCTION To_StdULogicVector ( s : std_logic_vector ) RETURN std_ulogic_vector; ------------------------------------------------------------------- -- strength strippers and type convertors ------------------------------------------------------------------- FUNCTION To_X01 ( s : std_logic_vector ) RETURN std_logic_vector; FUNCTION To_X01 ( s : std_ulogic_vector ) RETURN std_ulogic_vector; FUNCTION To_X01 ( s : std_ulogic ) RETURN X01; FUNCTION To_X01 ( b : BIT_VECTOR ) RETURN std_logic_vector; FUNCTION To_X01 ( b : BIT_VECTOR ) RETURN std_ulogic_vector; FUNCTION To_X01 ( b : BIT ) RETURN X01; FUNCTION To_X01Z ( s : std_logic_vector ) RETURN std_logic_vector; FUNCTION To_X01Z ( s : std_ulogic_vector ) RETURN std_ulogic_vector; FUNCTION To_X01Z ( s : std_ulogic ) RETURN X01Z; FUNCTION To_X01Z ( b : BIT_VECTOR ) RETURN std_logic_vector; FUNCTION To_X01Z ( b : BIT_VECTOR ) RETURN std_ulogic_vector; FUNCTION To_X01Z ( b : BIT ) RETURN X01Z; FUNCTION To_UX01 ( s : std_logic_vector ) RETURN std_logic_vector; FUNCTION To_UX01 ( s : std_ulogic_vector ) RETURN std_ulogic_vector; FUNCTION To_UX01 ( s : std_ulogic ) RETURN UX01; FUNCTION To_UX01 ( b : BIT_VECTOR ) RETURN std_logic_vector; FUNCTION To_UX01 ( b : BIT_VECTOR ) RETURN std_ulogic_vector; FUNCTION To_UX01 ( b : BIT ) RETURN UX01; ------------------------------------------------------------------- -- edge detection ------------------------------------------------------------------- FUNCTION rising_edge (SIGNAL s : std_ulogic) RETURN BOOLEAN; FUNCTION falling_edge (SIGNAL s : std_ulogic) RETURN BOOLEAN; ------------------------------------------------------------------- -- object contains an unknown ------------------------------------------------------------------- FUNCTION Is_X ( s : std_ulogic_vector ) RETURN BOOLEAN; FUNCTION Is_X ( s : std_logic_vector ) RETURN BOOLEAN; FUNCTION Is_X ( s : std_ulogic ) RETURN BOOLEAN; END std_logic_1164; -- -------------------------------------------------------------------- -- -- Title : std_logic_1164 multi-value logic system -- Library : This package shall be compiled into a library -- : symbolically named IEEE. -- : -- Developers: IEEE model standards group (par 1164) -- Purpose : This packages defines a standard for designers -- : to use in describing the interconnection data types -- : used in vhdl modeling. -- : -- Limitation: The logic system defined in this package may -- : be insufficient for modeling switched transistors, -- : since such a requirement is out of the scope of this -- : effort. Furthermore, mathematics, primitives, -- : timing standards, etc. are considered orthogonal -- : issues as it relates to this package and are therefore -- : beyond the scope of this effort. -- : -- Note : No declarations or definitions shall be included in, -- : or excluded from this package. The "package declaration" -- : defines the types, subtypes and declarations of -- : std_logic_1164. The std_logic_1164 package body shall be -- : considered the formal definition of the semantics of -- : this package. Tool developers may choose to implement -- : the package body in the most efficient manner available -- : to them. -- : -- -------------------------------------------------------------------- -- modification history : -- -------------------------------------------------------------------- -- version | mod. date:| -- v4.200 | 01/02/91 | -- -------------------------------------------------------------------- PACKAGE BODY std_logic_1164 IS ------------------------------------------------------------------- -- local types ------------------------------------------------------------------- TYPE stdlogic_1d IS ARRAY (std_ulogic) OF std_ulogic; TYPE stdlogic_table IS ARRAY(std_ulogic, std_ulogic) OF std_ulogic; ------------------------------------------------------------------- -- resolution function ------------------------------------------------------------------- CONSTANT resolution_table : stdlogic_table := ( -- --------------------------------------------------------- -- | U X 0 1 Z W L H - | | -- --------------------------------------------------------- ( 'U', 'U', 'U', 'U', 'U', 'U', 'U', 'U', 'U' ), -- | U | ( 'U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', 'X' ), -- | X | ( 'U', 'X', '0', 'X', '0', '0', '0', '0', 'X' ), -- | 0 | ( 'U', 'X', 'X', '1', '1', '1', '1', '1', 'X' ), -- | 1 | ( 'U', 'X', '0', '1', 'Z', 'W', 'L', 'H', 'X' ), -- | Z | ( 'U', 'X', '0', '1', 'W', 'W', 'W', 'W', 'X' ), -- | W | ( 'U', 'X', '0', '1', 'L', 'W', 'L', 'W', 'X' ), -- | L | ( 'U', 'X', '0', '1', 'H', 'W', 'W', 'H', 'X' ), -- | H | ( 'U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', 'X' ) -- | - | ); FUNCTION resolved ( s : std_ulogic_vector ) RETURN std_ulogic IS VARIABLE result : std_ulogic := 'Z'; -- weakest state default BEGIN -- the test for a single driver is essential otherwise the -- loop would return 'X' for a single driver of '-' and that -- would conflict with the value of a single driver unresolved -- signal. IF (s'LENGTH = 1) THEN RETURN s(s'LOW); ELSE FOR i IN s'RANGE LOOP result := resolution_table(result, s(i)); END LOOP; END IF; RETURN result; END resolved; ------------------------------------------------------------------- -- tables for logical operations ------------------------------------------------------------------- -- truth table for "and" function CONSTANT and_table : stdlogic_table := ( -- ---------------------------------------------------- -- | U X 0 1 Z W L H - | | -- ---------------------------------------------------- ( 'U', 'U', '0', 'U', 'U', 'U', '0', 'U', 'U' ), -- | U | ( 'U', 'X', '0', 'X', 'X', 'X', '0', 'X', 'X' ), -- | X | ( '0', '0', '0', '0', '0', '0', '0', '0', '0' ), -- | 0 | ( 'U', 'X', '0', '1', 'X', 'X', '0', '1', 'X' ), -- | 1 | ( 'U', 'X', '0', 'X', 'X', 'X', '0', 'X', 'X' ), -- | Z | ( 'U', 'X', '0', 'X', 'X', 'X', '0', 'X', 'X' ), -- | W | ( '0', '0', '0', '0', '0', '0', '0', '0', '0' ), -- | L | ( 'U', 'X', '0', '1', 'X', 'X', '0', '1', 'X' ), -- | H | ( 'U', 'X', '0', 'X', 'X', 'X', '0', 'X', 'X' ) -- | - | ); -- truth table for "or" function CONSTANT or_table : stdlogic_table := ( -- ---------------------------------------------------- -- | U X 0 1 Z W L H - | | -- ---------------------------------------------------- ( 'U', 'U', 'U', '1', 'U', 'U', 'U', '1', 'U' ), -- | U | ( 'U', 'X', 'X', '1', 'X', 'X', 'X', '1', 'X' ), -- | X | ( 'U', 'X', '0', '1', 'X', 'X', '0', '1', 'X' ), -- | 0 | ( '1', '1', '1', '1', '1', '1', '1', '1', '1' ), -- | 1 | ( 'U', 'X', 'X', '1', 'X', 'X', 'X', '1', 'X' ), -- | Z | ( 'U', 'X', 'X', '1', 'X', 'X', 'X', '1', 'X' ), -- | W | ( 'U', 'X', '0', '1', 'X', 'X', '0', '1', 'X' ), -- | L | ( '1', '1', '1', '1', '1', '1', '1', '1', '1' ), -- | H | ( 'U', 'X', 'X', '1', 'X', 'X', 'X', '1', 'X' ) -- | - | ); -- truth table for "xor" function CONSTANT xor_table : stdlogic_table := ( -- ---------------------------------------------------- -- | U X 0 1 Z W L H - | | -- ---------------------------------------------------- ( 'U', 'U', 'U', 'U', 'U', 'U', 'U', 'U', 'U' ), -- | U | ( 'U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', 'X' ), -- | X | ( 'U', 'X', '0', '1', 'X', 'X', '0', '1', 'X' ), -- | 0 | ( 'U', 'X', '1', '0', 'X', 'X', '1', '0', 'X' ), -- | 1 | ( 'U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', 'X' ), -- | Z | ( 'U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', 'X' ), -- | W | ( 'U', 'X', '0', '1', 'X', 'X', '0', '1', 'X' ), -- | L | ( 'U', 'X', '1', '0', 'X', 'X', '1', '0', 'X' ), -- | H | ( 'U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', 'X' ) -- | - | ); -- truth table for "not" function CONSTANT not_table: stdlogic_1d := -- ------------------------------------------------- -- | U X 0 1 Z W L H - | -- ------------------------------------------------- ( 'U', 'X', '1', '0', 'X', 'X', '1', '0', 'X' ); ------------------------------------------------------------------- -- overloaded logical operators ( with optimizing hints ) ------------------------------------------------------------------- FUNCTION "and" ( l : std_ulogic; r : std_ulogic ) RETURN UX01 IS BEGIN RETURN (and_table(l, r)); END "and"; FUNCTION "nand" ( l : std_ulogic; r : std_ulogic ) RETURN UX01 IS BEGIN RETURN (not_table ( and_table(l, r))); END "nand"; FUNCTION "or" ( l : std_ulogic; r : std_ulogic ) RETURN UX01 IS BEGIN RETURN (or_table(l, r)); END "or"; FUNCTION "nor" ( l : std_ulogic; r : std_ulogic ) RETURN UX01 IS BEGIN RETURN (not_table ( or_table( l, r ))); END "nor"; FUNCTION "xor" ( l : std_ulogic; r : std_ulogic ) RETURN UX01 IS BEGIN RETURN (xor_table(l, r)); END "xor"; --START-V93 FUNCTION "xnor" ( l : std_ulogic; r : std_ulogic ) RETURN UX01 IS BEGIN RETURN not_table(xor_table(l, r)); END "xnor"; --END-V93 FUNCTION "not" ( l : std_ulogic ) RETURN UX01 IS BEGIN RETURN (not_table(l)); END "not"; ------------------------------------------------------------------- -- and ------------------------------------------------------------------- FUNCTION "and" ( l,r : std_logic_vector ) RETURN std_logic_vector IS ALIAS lv : std_logic_vector ( 1 TO l'LENGTH ) IS l; ALIAS rv : std_logic_vector ( 1 TO r'LENGTH ) IS r; VARIABLE result : std_logic_vector ( 1 TO l'LENGTH ); BEGIN IF ( l'LENGTH /= r'LENGTH ) THEN ASSERT FALSE REPORT "arguments of overloaded 'and' operator are not of the same length" SEVERITY FAILURE; ELSE FOR i IN result'RANGE LOOP result(i) := and_table (lv(i), rv(i)); END LOOP; END IF; RETURN result; END "and"; --------------------------------------------------------------------- FUNCTION "and" ( l,r : std_ulogic_vector ) RETURN std_ulogic_vector IS ALIAS lv : std_ulogic_vector ( 1 TO l'LENGTH ) IS l; ALIAS rv : std_ulogic_vector ( 1 TO r'LENGTH ) IS r; VARIABLE result : std_ulogic_vector ( 1 TO l'LENGTH ); BEGIN IF ( l'LENGTH /= r'LENGTH ) THEN ASSERT FALSE REPORT "arguments of overloaded 'and' operator are not of the same length" SEVERITY FAILURE; ELSE FOR i IN result'RANGE LOOP result(i) := and_table (lv(i), rv(i)); END LOOP; END IF; RETURN result; END "and"; ------------------------------------------------------------------- -- nand ------------------------------------------------------------------- FUNCTION "nand" ( l,r : std_logic_vector ) RETURN std_logic_vector IS ALIAS lv : std_logic_vector ( 1 TO l'LENGTH ) IS l; ALIAS rv : std_logic_vector ( 1 TO r'LENGTH ) IS r; VARIABLE result : std_logic_vector ( 1 TO l'LENGTH ); BEGIN IF ( l'LENGTH /= r'LENGTH ) THEN ASSERT FALSE REPORT "arguments of overloaded 'nand' operator are not of the same length" SEVERITY FAILURE; ELSE FOR i IN result'RANGE LOOP result(i) := not_table(and_table (lv(i), rv(i))); END LOOP; END IF; RETURN result; END "nand"; --------------------------------------------------------------------- FUNCTION "nand" ( l,r : std_ulogic_vector ) RETURN std_ulogic_vector IS ALIAS lv : std_ulogic_vector ( 1 TO l'LENGTH ) IS l; ALIAS rv : std_ulogic_vector ( 1 TO r'LENGTH ) IS r; VARIABLE result : std_ulogic_vector ( 1 TO l'LENGTH ); BEGIN IF ( l'LENGTH /= r'LENGTH ) THEN ASSERT FALSE REPORT "arguments of overloaded 'nand' operator are not of the same length" SEVERITY FAILURE; ELSE FOR i IN result'RANGE LOOP result(i) := not_table(and_table (lv(i), rv(i))); END LOOP; END IF; RETURN result; END "nand"; ------------------------------------------------------------------- -- or ------------------------------------------------------------------- FUNCTION "or" ( l,r : std_logic_vector ) RETURN std_logic_vector IS ALIAS lv : std_logic_vector ( 1 TO l'LENGTH ) IS l; ALIAS rv : std_logic_vector ( 1 TO r'LENGTH ) IS r; VARIABLE result : std_logic_vector ( 1 TO l'LENGTH ); BEGIN IF ( l'LENGTH /= r'LENGTH ) THEN ASSERT FALSE REPORT "arguments of overloaded 'or' operator are not of the same length" SEVERITY FAILURE; ELSE FOR i IN result'RANGE LOOP result(i) := or_table (lv(i), rv(i)); END LOOP; END IF; RETURN result; END "or"; --------------------------------------------------------------------- FUNCTION "or" ( l,r : std_ulogic_vector ) RETURN std_ulogic_vector IS ALIAS lv : std_ulogic_vector ( 1 TO l'LENGTH ) IS l; ALIAS rv : std_ulogic_vector ( 1 TO r'LENGTH ) IS r; VARIABLE result : std_ulogic_vector ( 1 TO l'LENGTH ); BEGIN IF ( l'LENGTH /= r'LENGTH ) THEN ASSERT FALSE REPORT "arguments of overloaded 'or' operator are not of the same length" SEVERITY FAILURE; ELSE FOR i IN result'RANGE LOOP result(i) := or_table (lv(i), rv(i)); END LOOP; END IF; RETURN result; END "or"; ------------------------------------------------------------------- -- nor ------------------------------------------------------------------- FUNCTION "nor" ( l,r : std_logic_vector ) RETURN std_logic_vector IS ALIAS lv : std_logic_vector ( 1 TO l'LENGTH ) IS l; ALIAS rv : std_logic_vector ( 1 TO r'LENGTH ) IS r; VARIABLE result : std_logic_vector ( 1 TO l'LENGTH ); BEGIN IF ( l'LENGTH /= r'LENGTH ) THEN ASSERT FALSE REPORT "arguments of overloaded 'nor' operator are not of the same length" SEVERITY FAILURE; ELSE FOR i IN result'RANGE LOOP result(i) := not_table(or_table (lv(i), rv(i))); END LOOP; END IF; RETURN result; END "nor"; --------------------------------------------------------------------- FUNCTION "nor" ( l,r : std_ulogic_vector ) RETURN std_ulogic_vector IS ALIAS lv : std_ulogic_vector ( 1 TO l'LENGTH ) IS l; ALIAS rv : std_ulogic_vector ( 1 TO r'LENGTH ) IS r; VARIABLE result : std_ulogic_vector ( 1 TO l'LENGTH ); BEGIN IF ( l'LENGTH /= r'LENGTH ) THEN ASSERT FALSE REPORT "arguments of overloaded 'nor' operator are not of the same length" SEVERITY FAILURE; ELSE FOR i IN result'RANGE LOOP result(i) := not_table(or_table (lv(i), rv(i))); END LOOP; END IF; RETURN result; END "nor"; --------------------------------------------------------------------- -- xor ------------------------------------------------------------------- FUNCTION "xor" ( l,r : std_logic_vector ) RETURN std_logic_vector IS ALIAS lv : std_logic_vector ( 1 TO l'LENGTH ) IS l; ALIAS rv : std_logic_vector ( 1 TO r'LENGTH ) IS r; VARIABLE result : std_logic_vector ( 1 TO l'LENGTH ); BEGIN IF ( l'LENGTH /= r'LENGTH ) THEN ASSERT FALSE REPORT "arguments of overloaded 'xor' operator are not of the same length" SEVERITY FAILURE; ELSE FOR i IN result'RANGE LOOP result(i) := xor_table (lv(i), rv(i)); END LOOP; END IF; RETURN result; END "xor"; --------------------------------------------------------------------- FUNCTION "xor" ( l,r : std_ulogic_vector ) RETURN std_ulogic_vector IS ALIAS lv : std_ulogic_vector ( 1 TO l'LENGTH ) IS l; ALIAS rv : std_ulogic_vector ( 1 TO r'LENGTH ) IS r; VARIABLE result : std_ulogic_vector ( 1 TO l'LENGTH ); BEGIN IF ( l'LENGTH /= r'LENGTH ) THEN ASSERT FALSE REPORT "arguments of overloaded 'xor' operator are not of the same length" SEVERITY FAILURE; ELSE FOR i IN result'RANGE LOOP result(i) := xor_table (lv(i), rv(i)); END LOOP; END IF; RETURN result; END "xor"; -- ------------------------------------------------------------------- -- -- xnor -- ------------------------------------------------------------------- -- ----------------------------------------------------------------------- -- Note : The declaration and implementation of the "xnor" function is -- specifically commented until at which time the VHDL language has been -- officially adopted as containing such a function. At such a point, -- the following comments may be removed along with this notice without -- further "official" ballotting of this std_logic_1164 package. It is -- the intent of this effort to provide such a function once it becomes -- available in the VHDL standard. -- ----------------------------------------------------------------------- --START-V93 FUNCTION "xnor" ( l,r : std_logic_vector ) RETURN std_logic_vector IS ALIAS lv : std_logic_vector ( 1 TO l'LENGTH ) IS l; ALIAS rv : std_logic_vector ( 1 TO r'LENGTH ) IS r; VARIABLE result : std_logic_vector ( 1 TO l'LENGTH ); BEGIN IF ( l'LENGTH /= r'LENGTH ) THEN ASSERT FALSE REPORT "arguments of overloaded 'xnor' operator are not of the same length" SEVERITY FAILURE; ELSE FOR i IN result'RANGE LOOP result(i) := not_table(xor_table (lv(i), rv(i))); END LOOP; END IF; RETURN result; END "xnor"; --------------------------------------------------------------------- FUNCTION "xnor" ( l,r : std_ulogic_vector ) RETURN std_ulogic_vector IS ALIAS lv : std_ulogic_vector ( 1 TO l'LENGTH ) IS l; ALIAS rv : std_ulogic_vector ( 1 TO r'LENGTH ) IS r; VARIABLE result : std_ulogic_vector ( 1 TO l'LENGTH ); BEGIN IF ( l'LENGTH /= r'LENGTH ) THEN ASSERT FALSE REPORT "arguments of overloaded 'xnor' operator are not of the same length" SEVERITY FAILURE; ELSE FOR i IN result'RANGE LOOP result(i) := not_table(xor_table (lv(i), rv(i))); END LOOP; END IF; RETURN result; END "xnor"; --END-V93 ------------------------------------------------------------------- -- not ------------------------------------------------------------------- FUNCTION "not" ( l : std_logic_vector ) RETURN std_logic_vector IS ALIAS lv : std_logic_vector ( 1 TO l'LENGTH ) IS l; VARIABLE result : std_logic_vector ( 1 TO l'LENGTH ) := (OTHERS => 'X'); BEGIN FOR i IN result'RANGE LOOP result(i) := not_table( lv(i) ); END LOOP; RETURN result; END; --------------------------------------------------------------------- FUNCTION "not" ( l : std_ulogic_vector ) RETURN std_ulogic_vector IS ALIAS lv : std_ulogic_vector ( 1 TO l'LENGTH ) IS l; VARIABLE result : std_ulogic_vector ( 1 TO l'LENGTH ) := (OTHERS => 'X'); BEGIN FOR i IN result'RANGE LOOP result(i) := not_table( lv(i) ); END LOOP; RETURN result; END; ------------------------------------------------------------------- -- conversion tables ------------------------------------------------------------------- TYPE logic_x01_table IS ARRAY (std_ulogic'LOW TO std_ulogic'HIGH) OF X01; TYPE logic_x01z_table IS ARRAY (std_ulogic'LOW TO std_ulogic'HIGH) OF X01Z; TYPE logic_ux01_table IS ARRAY (std_ulogic'LOW TO std_ulogic'HIGH) OF UX01; ---------------------------------------------------------- -- table name : cvt_to_x01 -- -- parameters : -- in : std_ulogic -- some logic value -- returns : x01 -- state value of logic value -- purpose : to convert state-strength to state only -- -- example : if (cvt_to_x01 (input_signal) = '1' ) then ... -- ---------------------------------------------------------- CONSTANT cvt_to_x01 : logic_x01_table := ( 'X', -- 'U' 'X', -- 'X' '0', -- '0' '1', -- '1' 'X', -- 'Z' 'X', -- 'W' '0', -- 'L' '1', -- 'H' 'X' -- '-' ); ---------------------------------------------------------- -- table name : cvt_to_x01z -- -- parameters : -- in : std_ulogic -- some logic value -- returns : x01z -- state value of logic value -- purpose : to convert state-strength to state only -- -- example : if (cvt_to_x01z (input_signal) = '1' ) then ... -- ---------------------------------------------------------- CONSTANT cvt_to_x01z : logic_x01z_table := ( 'X', -- 'U' 'X', -- 'X' '0', -- '0' '1', -- '1' 'Z', -- 'Z' 'X', -- 'W' '0', -- 'L' '1', -- 'H' 'X' -- '-' ); ---------------------------------------------------------- -- table name : cvt_to_ux01 -- -- parameters : -- in : std_ulogic -- some logic value -- returns : ux01 -- state value of logic value -- purpose : to convert state-strength to state only -- -- example : if (cvt_to_ux01 (input_signal) = '1' ) then ... -- ---------------------------------------------------------- CONSTANT cvt_to_ux01 : logic_ux01_table := ( 'U', -- 'U' 'X', -- 'X' '0', -- '0' '1', -- '1' 'X', -- 'Z' 'X', -- 'W' '0', -- 'L' '1', -- 'H' 'X' -- '-' ); ------------------------------------------------------------------- -- conversion functions ------------------------------------------------------------------- FUNCTION To_bit ( s : std_ulogic; xmap : BIT := '0') RETURN BIT IS BEGIN CASE s IS WHEN '0' | 'L' => RETURN ('0'); WHEN '1' | 'H' => RETURN ('1'); WHEN OTHERS => RETURN xmap; END CASE; END; -------------------------------------------------------------------- FUNCTION To_bitvector ( s : std_logic_vector ; xmap : BIT := '0') RETURN BIT_VECTOR IS ALIAS sv : std_logic_vector ( s'LENGTH-1 DOWNTO 0 ) IS s; VARIABLE result : BIT_VECTOR ( s'LENGTH-1 DOWNTO 0 ); BEGIN FOR i IN result'RANGE LOOP CASE sv(i) IS WHEN '0' | 'L' => result(i) := '0'; WHEN '1' | 'H' => result(i) := '1'; WHEN OTHERS => result(i) := xmap; END CASE; END LOOP; RETURN result; END; -------------------------------------------------------------------- FUNCTION To_bitvector ( s : std_ulogic_vector; xmap : BIT := '0') RETURN BIT_VECTOR IS ALIAS sv : std_ulogic_vector ( s'LENGTH-1 DOWNTO 0 ) IS s; VARIABLE result : BIT_VECTOR ( s'LENGTH-1 DOWNTO 0 ); BEGIN FOR i IN result'RANGE LOOP CASE sv(i) IS WHEN '0' | 'L' => result(i) := '0'; WHEN '1' | 'H' => result(i) := '1'; WHEN OTHERS => result(i) := xmap; END CASE; END LOOP; RETURN result; END; -------------------------------------------------------------------- FUNCTION To_StdULogic ( b : BIT ) RETURN std_ulogic IS BEGIN CASE b IS WHEN '0' => RETURN '0'; WHEN '1' => RETURN '1'; END CASE; END; -------------------------------------------------------------------- FUNCTION To_StdLogicVector ( b : BIT_VECTOR ) RETURN std_logic_vector IS ALIAS bv : BIT_VECTOR ( b'LENGTH-1 DOWNTO 0 ) IS b; VARIABLE result : std_logic_vector ( b'LENGTH-1 DOWNTO 0 ); BEGIN FOR i IN result'RANGE LOOP CASE bv(i) IS WHEN '0' => result(i) := '0'; WHEN '1' => result(i) := '1'; END CASE; END LOOP; RETURN result; END; -------------------------------------------------------------------- FUNCTION To_StdLogicVector ( s : std_ulogic_vector ) RETURN std_logic_vector IS ALIAS sv : std_ulogic_vector ( s'LENGTH-1 DOWNTO 0 ) IS s; VARIABLE result : std_logic_vector ( s'LENGTH-1 DOWNTO 0 ); BEGIN FOR i IN result'RANGE LOOP result(i) := sv(i); END LOOP; RETURN result; END; -------------------------------------------------------------------- FUNCTION To_StdULogicVector ( b : BIT_VECTOR ) RETURN std_ulogic_vector IS ALIAS bv : BIT_VECTOR ( b'LENGTH-1 DOWNTO 0 ) IS b; VARIABLE result : std_ulogic_vector ( b'LENGTH-1 DOWNTO 0 ); BEGIN FOR i IN result'RANGE LOOP CASE bv(i) IS WHEN '0' => result(i) := '0'; WHEN '1' => result(i) := '1'; END CASE; END LOOP; RETURN result; END; -------------------------------------------------------------------- FUNCTION To_StdULogicVector ( s : std_logic_vector ) RETURN std_ulogic_vector IS ALIAS sv : std_logic_vector ( s'LENGTH-1 DOWNTO 0 ) IS s; VARIABLE result : std_ulogic_vector ( s'LENGTH-1 DOWNTO 0 ); BEGIN FOR i IN result'RANGE LOOP result(i) := sv(i); END LOOP; RETURN result; END; ------------------------------------------------------------------- -- strength strippers and type convertors ------------------------------------------------------------------- -- to_x01 ------------------------------------------------------------------- FUNCTION To_X01 ( s : std_logic_vector ) RETURN std_logic_vector IS ALIAS sv : std_logic_vector ( 1 TO s'LENGTH ) IS s; VARIABLE result : std_logic_vector ( 1 TO s'LENGTH ); BEGIN FOR i IN result'RANGE LOOP result(i) := cvt_to_x01 (sv(i)); END LOOP; RETURN result; END; -------------------------------------------------------------------- FUNCTION To_X01 ( s : std_ulogic_vector ) RETURN std_ulogic_vector IS ALIAS sv : std_ulogic_vector ( 1 TO s'LENGTH ) IS s; VARIABLE result : std_ulogic_vector ( 1 TO s'LENGTH ); BEGIN FOR i IN result'RANGE LOOP result(i) := cvt_to_x01 (sv(i)); END LOOP; RETURN result; END; -------------------------------------------------------------------- FUNCTION To_X01 ( s : std_ulogic ) RETURN X01 IS BEGIN RETURN (cvt_to_x01(s)); END; -------------------------------------------------------------------- FUNCTION To_X01 ( b : BIT_VECTOR ) RETURN std_logic_vector IS ALIAS bv : BIT_VECTOR ( 1 TO b'LENGTH ) IS b; VARIABLE result : std_logic_vector ( 1 TO b'LENGTH ); BEGIN FOR i IN result'RANGE LOOP CASE bv(i) IS WHEN '0' => result(i) := '0'; WHEN '1' => result(i) := '1'; END CASE; END LOOP; RETURN result; END; -------------------------------------------------------------------- FUNCTION To_X01 ( b : BIT_VECTOR ) RETURN std_ulogic_vector IS ALIAS bv : BIT_VECTOR ( 1 TO b'LENGTH ) IS b; VARIABLE result : std_ulogic_vector ( 1 TO b'LENGTH ); BEGIN FOR i IN result'RANGE LOOP CASE bv(i) IS WHEN '0' => result(i) := '0'; WHEN '1' => result(i) := '1'; END CASE; END LOOP; RETURN result; END; -------------------------------------------------------------------- FUNCTION To_X01 ( b : BIT ) RETURN X01 IS BEGIN CASE b IS WHEN '0' => RETURN('0'); WHEN '1' => RETURN('1'); END CASE; END; -------------------------------------------------------------------- -- to_x01z ------------------------------------------------------------------- FUNCTION To_X01Z ( s : std_logic_vector ) RETURN std_logic_vector IS ALIAS sv : std_logic_vector ( 1 TO s'LENGTH ) IS s; VARIABLE result : std_logic_vector ( 1 TO s'LENGTH ); BEGIN FOR i IN result'RANGE LOOP result(i) := cvt_to_x01z (sv(i)); END LOOP; RETURN result; END; -------------------------------------------------------------------- FUNCTION To_X01Z ( s : std_ulogic_vector ) RETURN std_ulogic_vector IS ALIAS sv : std_ulogic_vector ( 1 TO s'LENGTH ) IS s; VARIABLE result : std_ulogic_vector ( 1 TO s'LENGTH ); BEGIN FOR i IN result'RANGE LOOP result(i) := cvt_to_x01z (sv(i)); END LOOP; RETURN result; END; -------------------------------------------------------------------- FUNCTION To_X01Z ( s : std_ulogic ) RETURN X01Z IS BEGIN RETURN (cvt_to_x01z(s)); END; -------------------------------------------------------------------- FUNCTION To_X01Z ( b : BIT_VECTOR ) RETURN std_logic_vector IS ALIAS bv : BIT_VECTOR ( 1 TO b'LENGTH ) IS b; VARIABLE result : std_logic_vector ( 1 TO b'LENGTH ); BEGIN FOR i IN result'RANGE LOOP CASE bv(i) IS WHEN '0' => result(i) := '0'; WHEN '1' => result(i) := '1'; END CASE; END LOOP; RETURN result; END; -------------------------------------------------------------------- FUNCTION To_X01Z ( b : BIT_VECTOR ) RETURN std_ulogic_vector IS ALIAS bv : BIT_VECTOR ( 1 TO b'LENGTH ) IS b; VARIABLE result : std_ulogic_vector ( 1 TO b'LENGTH ); BEGIN FOR i IN result'RANGE LOOP CASE bv(i) IS WHEN '0' => result(i) := '0'; WHEN '1' => result(i) := '1'; END CASE; END LOOP; RETURN result; END; -------------------------------------------------------------------- FUNCTION To_X01Z ( b : BIT ) RETURN X01Z IS BEGIN CASE b IS WHEN '0' => RETURN('0'); WHEN '1' => RETURN('1'); END CASE; END; -------------------------------------------------------------------- -- to_ux01 ------------------------------------------------------------------- FUNCTION To_UX01 ( s : std_logic_vector ) RETURN std_logic_vector IS ALIAS sv : std_logic_vector ( 1 TO s'LENGTH ) IS s; VARIABLE result : std_logic_vector ( 1 TO s'LENGTH ); BEGIN FOR i IN result'RANGE LOOP result(i) := cvt_to_ux01 (sv(i)); END LOOP; RETURN result; END; -------------------------------------------------------------------- FUNCTION To_UX01 ( s : std_ulogic_vector ) RETURN std_ulogic_vector IS ALIAS sv : std_ulogic_vector ( 1 TO s'LENGTH ) IS s; VARIABLE result : std_ulogic_vector ( 1 TO s'LENGTH ); BEGIN FOR i IN result'RANGE LOOP result(i) := cvt_to_ux01 (sv(i)); END LOOP; RETURN result; END; -------------------------------------------------------------------- FUNCTION To_UX01 ( s : std_ulogic ) RETURN UX01 IS BEGIN RETURN (cvt_to_ux01(s)); END; -------------------------------------------------------------------- FUNCTION To_UX01 ( b : BIT_VECTOR ) RETURN std_logic_vector IS ALIAS bv : BIT_VECTOR ( 1 TO b'LENGTH ) IS b; VARIABLE result : std_logic_vector ( 1 TO b'LENGTH ); BEGIN FOR i IN result'RANGE LOOP CASE bv(i) IS WHEN '0' => result(i) := '0'; WHEN '1' => result(i) := '1'; END CASE; END LOOP; RETURN result; END; -------------------------------------------------------------------- FUNCTION To_UX01 ( b : BIT_VECTOR ) RETURN std_ulogic_vector IS ALIAS bv : BIT_VECTOR ( 1 TO b'LENGTH ) IS b; VARIABLE result : std_ulogic_vector ( 1 TO b'LENGTH ); BEGIN FOR i IN result'RANGE LOOP CASE bv(i) IS WHEN '0' => result(i) := '0'; WHEN '1' => result(i) := '1'; END CASE; END LOOP; RETURN result; END; -------------------------------------------------------------------- FUNCTION To_UX01 ( b : BIT ) RETURN UX01 IS BEGIN CASE b IS WHEN '0' => RETURN('0'); WHEN '1' => RETURN('1'); END CASE; END; ------------------------------------------------------------------- -- edge detection ------------------------------------------------------------------- FUNCTION rising_edge (SIGNAL s : std_ulogic) RETURN BOOLEAN IS BEGIN RETURN (s'EVENT AND (To_X01(s) = '1') AND (To_X01(s'LAST_VALUE) = '0')); END; FUNCTION falling_edge (SIGNAL s : std_ulogic) RETURN BOOLEAN IS BEGIN RETURN (s'EVENT AND (To_X01(s) = '0') AND (To_X01(s'LAST_VALUE) = '1')); END; ------------------------------------------------------------------- -- object contains an unknown ------------------------------------------------------------------- FUNCTION Is_X ( s : std_ulogic_vector ) RETURN BOOLEAN IS BEGIN FOR i IN s'RANGE LOOP CASE s(i) IS WHEN 'U' | 'X' | 'Z' | 'W' | '-' => RETURN TRUE; WHEN OTHERS => NULL; END CASE; END LOOP; RETURN FALSE; END; -------------------------------------------------------------------- FUNCTION Is_X ( s : std_logic_vector ) RETURN BOOLEAN IS BEGIN FOR i IN s'RANGE LOOP CASE s(i) IS WHEN 'U' | 'X' | 'Z' | 'W' | '-' => RETURN TRUE; WHEN OTHERS => NULL; END CASE; END LOOP; RETURN FALSE; END; -------------------------------------------------------------------- FUNCTION Is_X ( s : std_ulogic ) RETURN BOOLEAN IS BEGIN CASE s IS WHEN 'U' | 'X' | 'Z' | 'W' | '-' => RETURN TRUE; WHEN OTHERS => NULL; END CASE; RETURN FALSE; END; END std_logic_1164;
gpl-3.0
b550fa12f6bf6b4b695337e3e7c92924
0.404176
4.266158
false
false
false
false
progranism/Open-Source-FPGA-Bitcoin-Miner
projects/VC707_experimental/VC707_experimental.srcs/sources_1/ip/golden_ticket_fifo/fifo_generator_v10_0/fifo16_patch/input_block_fifo16_patch.vhd
9
15,036
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gpl-3.0
f7f81b5324ae020c83c8fd104caebd4b
0.935488
1.887522
false
false
false
false
MrDoomBringer/DSD-Labs
Lab 8/reaction.vhd
1
4,056
-- FPGA reaction time tester for Altera DE-2 board -- Cliff Chapman -- 10/27/2013 -- -- Lab 8 - Digital Systems Design LIBRARY ieee; USE ieee.std_logic_1164.ALL; USE ieee.numeric_std.ALL; USE ieee.std_logic_signed.ALL; ENTITY reaction IS PORT ( -- Reset system rst : IN STD_LOGIC; -- Set time interval set : IN STD_LOGIC_VECTOR (7 DOWNTO 0); -- Trigger button trig : IN STD_LOGIC; -- 50 Mhz external clock clk : IN STD_LOGIC; -- Sevenseg displays d_HEX0 : OUT STD_LOGIC_VECTOR (6 DOWNTO 0); d_HEX1 : OUT STD_LOGIC_VECTOR (6 DOWNTO 0); d_HEX2 : OUT STD_LOGIC_VECTOR (6 DOWNTO 0); d_HEX3 : OUT STD_LOGIC_VECTOR (6 DOWNTO 0); -- Trigger light LEDR : OUT STD_LOGIC ); END reaction; ARCHITECTURE rtl OF reaction IS COMPONENT sevenseg_bcd_display PORT ( r : IN STD_LOGIC_VECTOR (7 DOWNTO 0); s : IN STD_LOGIC := '1'; -- Select tied to '1' by default to show numeric values HEX0, HEX1, HEX2 : OUT STD_LOGIC_VECTOR (6 DOWNTO 0) ); END COMPONENT; -- This feels like a GREAT way to screw yourself over with -- overloading common names. Maybe that's just me. -- Either way that's why we have the _s hungarian postfix on these. TYPE state_type IS (idle_s, wait_s, runprep_s, run_s, hold_s); SIGNAL state : state_type; SIGNAL clock_1 : STD_LOGIC := '0'; SIGNAL cnt_rst : STD_LOGIC; SIGNAL disp_buf: STD_LOGIC_VECTOR (15 DOWNTO 0) := x"0000"; SIGNAL mil_cnt : STD_LOGIC_VECTOR (15 DOWNTO 0) := x"0000"; SIGNAL cnt : STD_LOGIC_VECTOR (15 DOWNTO 0) := x"0000"; SIGNAL cnt_div :STD_LOGIC_VECTOR (31 DOWNTO 0) := x"00000000"; BEGIN -- Milliseconds elapsed display disp_low: sevenseg_bcd_display PORT MAP ( r => disp_buf (15 DOWNTO 8), s => '0', HEX2 => OPEN, HEX1 => d_hex3, HEX0 => d_hex2 ); disp_high: sevenseg_bcd_display PORT MAP ( r => disp_buf (7 DOWNTO 0), s => '0', HEX2 => OPEN, HEX1 => d_hex1, HEX0 => d_hex0 ); -- Clock divider for millisecond from 50Mhz clock_div: PROCESS (clk, rst) BEGIN IF (rising_edge(clk)) THEN IF (cnt_div >= x"61A7") THEN cnt_div <= x"00000000"; clock_1 <= NOT clock_1; ELSE cnt_div <= cnt_div+1; END IF; END IF; END PROCESS clock_div; -- Counter for milliseconds timer mil_clock : PROCESS (clock_1, cnt_rst, state, cnt) BEGIN IF (cnt_rst = '0') THEN cnt <= x"0000"; ELSIF (rising_edge(clock_1) AND cnt_rst = '1') THEN cnt <= cnt + '1'; ELSE cnt <= cnt; END IF; mil_cnt <= cnt; END PROCESS mil_clock; state_monitor: PROCESS (state, clk, rst) BEGIN IF (rst = '0') THEN state <= idle_s; ELSIF (rising_edge(clk) AND rst = '1') THEN CASE state IS WHEN idle_s => IF (trig = '0') THEN state <= wait_s; ELSE state <= idle_s; END IF; WHEN wait_s => IF (mil_cnt >= ((x"00" & set) * x"3E8")) THEN state <= runprep_s; ELSE state <= wait_s; END IF; WHEN runprep_s => IF (mil_cnt = x"0000") THEN state <= run_s; ELSE state <= runprep_s; END IF; WHEN run_s => IF (trig = '0') THEN state <= hold_s; ELSE state <= run_s; END IF; WHEN hold_s => state <= hold_s; WHEN OTHERS => state <= idle_s; END CASE; END IF; END PROCESS state_monitor; output_monitor: PROCESS (state, clk, rst, mil_cnt) BEGIN IF (rst = '0') THEN cnt_rst <= '0'; LEDR <= '0'; disp_buf <= x"0000"; ELSIF (rst = '1' AND rising_edge(clk)) THEN CASE (state) IS WHEN idle_s => LEDR <= '0'; cnt_rst <= '0'; disp_buf <= x"0000"; WHEN wait_s => LEDR <= '1'; cnt_rst <= '1'; disp_buf <= x"0000"; WHEN runprep_s => LEDR <= '1'; cnt_rst <= '0'; disp_buf <= x"0000"; WHEN run_s => LEDR <= '0'; cnt_rst <= '1'; disp_buf <= mil_cnt; WHEN hold_s => LEDR <= '0'; cnt_rst <= '1'; disp_buf <= disp_buf; WHEN OTHERS => cnt_rst <= '0'; LEDR <= '0'; disp_buf <= x"0000"; END CASE; END IF; END PROCESS output_monitor; END ARCHITECTURE;
mit
afddd9b8e1799b23d1b5bd0ae61aaa6d
0.578649
2.73869
false
false
false
false
dcliche/mdsynth
rtl/src/ram32k_b16.vhd
1
96,680
-- $Id: ram32k_b16.vhd,v 1.2 2008/03/14 15:52:43 dilbert57 Exp $ --===========================================================================-- -- -- -- ram32k_b16.vhd - 32KByte Block RAM Component for Spartan 3/3E -- -- -- --===========================================================================-- -- -- File name : ram32k_b16.vhd -- -- Entity name : ram_32k -- -- Purpose : Implements 32K of Synchronous Static RAM -- using 16 x Spartan 3/3E RAMB16_S9 block rams -- Used in the Digilent Spartan 3E500 System09 design -- -- Dependencies : ieee.Std_Logic_1164 -- ieee.std_logic_arith -- unisim.vcomponents -- -- Uses : RAMB16_S9 -- -- Author : John E. Kent -- -- Email : [email protected] -- -- Web : http://opencores.org/project,system09 -- -- -- Copyright (C) 2005 - 2010 John Kent -- -- This program is free software: you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by -- the Free Software Foundation, either version 3 of the License, or -- (at your option) any later version. -- -- This program is distributed in the hope that it will be useful, -- but WITHOUT ANY WARRANTY; without even the implied warranty of -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -- GNU General Public License for more details. -- -- You should have received a copy of the GNU General Public License -- along with this program. If not, see <http://www.gnu.org/licenses/>. -- --===========================================================================-- -- -- -- Revision History -- -- -- --===========================================================================-- -- -- Version Author Date Changes -- -- 0.1 John Kent 2006-04-24 Initial release -- 0.2 John Kent 2005-06-29 Added CS term to CE decodes. (date ???) -- 0.3 John Kent 2010-09-14 Renamed "rdata" to "data_out" -- Renamed "wdata" to "data_in" -- Added header description -- library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; library unisim; use unisim.vcomponents.all; entity ram_32k is Port ( clk : in std_logic; rst : in std_logic; cs : in std_logic; addr : in std_logic_vector (14 downto 0); rw : in std_logic; data_in : in std_logic_vector (7 downto 0); data_out : out std_logic_vector (7 downto 0) ); end ram_32k; architecture rtl of ram_32k is signal we : std_logic; signal dp : std_logic_vector(15 downto 0); signal ce : std_logic_vector(15 downto 0); signal data_out_0 : std_logic_vector(7 downto 0); signal data_out_1 : std_logic_vector(7 downto 0); signal data_out_2 : std_logic_vector(7 downto 0); signal data_out_3 : std_logic_vector(7 downto 0); signal data_out_4 : std_logic_vector(7 downto 0); signal data_out_5 : std_logic_vector(7 downto 0); signal data_out_6 : std_logic_vector(7 downto 0); signal data_out_7 : std_logic_vector(7 downto 0); signal data_out_8 : std_logic_vector(7 downto 0); signal data_out_9 : std_logic_vector(7 downto 0); signal data_out_a : std_logic_vector(7 downto 0); signal data_out_b : std_logic_vector(7 downto 0); signal data_out_c : std_logic_vector(7 downto 0); signal data_out_d : std_logic_vector(7 downto 0); signal data_out_e : std_logic_vector(7 downto 0); signal data_out_f : std_logic_vector(7 downto 0); begin RAM0 : RAMB16_S9 generic map ( INIT_00 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_01 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_02 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_03 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_04 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_05 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_06 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_07 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_08 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_09 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_0A => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_0B => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_0C => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_0D => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_0E => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_0F => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_10 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_11 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_12 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_13 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_14 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_15 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_16 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_17 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_18 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_19 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_1A => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_1B => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_1C => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_1D => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_1E => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_1F => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_20 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_21 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_22 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_23 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_24 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_25 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_26 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_27 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_28 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_29 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_2A => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_2B => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_2C => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_2D => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_2E => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_2F => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_30 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_31 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_32 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_33 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_34 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_35 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_36 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_37 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_38 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_39 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_3A => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_3B => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_3C => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_3D => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_3E => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_3F => x"0000000000000000000000000000000000000000000000000000000000000000" ) port map ( do => data_out_0, dop(0) => dp(0), addr => addr(10 downto 0), clk => clk, di => data_in, dip(0) => dp(0), en => ce(0), ssr => rst, we => we ); RAM1 : RAMB16_S9 generic map ( INIT_00 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_01 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_02 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_03 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_04 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_05 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_06 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_07 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_08 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_09 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_0A => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_0B => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_0C => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_0D => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_0E => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_0F => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_10 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_11 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_12 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_13 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_14 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_15 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_16 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_17 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_18 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_19 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_1A => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_1B => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_1C => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_1D => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_1E => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_1F => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_20 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_21 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_22 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_23 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_24 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_25 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_26 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_27 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_28 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_29 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_2A => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_2B => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_2C => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_2D => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_2E => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_2F => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_30 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_31 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_32 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_33 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_34 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_35 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_36 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_37 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_38 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_39 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_3A => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_3B => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_3C => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_3D => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_3E => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_3F => x"0000000000000000000000000000000000000000000000000000000000000000" ) port map ( do => data_out_1, dop(0) => dp(1), addr => addr(10 downto 0), clk => clk, di => data_in, dip(0) => dp(1), en => ce(1), ssr => rst, we => we ); RAM2 : RAMB16_S9 generic map ( INIT_00 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_01 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_02 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_03 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_04 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_05 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_06 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_07 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_08 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_09 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_0A => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_0B => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_0C => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_0D => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_0E => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_0F => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_10 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_11 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_12 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_13 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_14 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_15 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_16 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_17 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_18 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_19 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_1A => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_1B => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_1C => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_1D => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_1E => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_1F => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_20 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_21 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_22 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_23 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_24 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_25 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_26 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_27 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_28 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_29 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_2A => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_2B => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_2C => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_2D => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_2E => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_2F => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_30 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_31 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_32 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_33 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_34 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_35 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_36 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_37 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_38 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_39 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_3A => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_3B => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_3C => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_3D => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_3E => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_3F => x"0000000000000000000000000000000000000000000000000000000000000000" ) port map ( do => data_out_2, dop(0) => dp(2), addr => addr(10 downto 0), clk => clk, di => data_in, dip(0) => dp(2), en => ce(2), ssr => rst, we => we ); RAM3 : RAMB16_S9 generic map ( INIT_00 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_01 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_02 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_03 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_04 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_05 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_06 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_07 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_08 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_09 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_0A => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_0B => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_0C => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_0D => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_0E => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_0F => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_10 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_11 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_12 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_13 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_14 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_15 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_16 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_17 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_18 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_19 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_1A => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_1B => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_1C => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_1D => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_1E => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_1F => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_20 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_21 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_22 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_23 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_24 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_25 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_26 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_27 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_28 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_29 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_2A => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_2B => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_2C => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_2D => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_2E => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_2F => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_30 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_31 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_32 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_33 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_34 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_35 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_36 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_37 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_38 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_39 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_3A => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_3B => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_3C => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_3D => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_3E => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_3F => x"0000000000000000000000000000000000000000000000000000000000000000" ) port map ( do => data_out_3, dop(0) => dp(3), addr => addr(10 downto 0), clk => clk, di => data_in, dip(0) => dp(3), en => ce(3), ssr => rst, we => we ); RAM4 : RAMB16_S9 generic map ( INIT_00 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_01 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_02 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_03 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_04 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_05 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_06 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_07 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_08 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_09 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_0A => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_0B => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_0C => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_0D => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_0E => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_0F => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_10 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_11 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_12 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_13 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_14 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_15 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_16 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_17 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_18 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_19 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_1A => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_1B => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_1C => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_1D => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_1E => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_1F => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_20 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_21 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_22 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_23 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_24 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_25 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_26 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_27 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_28 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_29 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_2A => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_2B => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_2C => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_2D => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_2E => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_2F => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_30 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_31 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_32 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_33 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_34 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_35 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_36 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_37 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_38 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_39 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_3A => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_3B => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_3C => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_3D => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_3E => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_3F => x"0000000000000000000000000000000000000000000000000000000000000000" ) port map ( do => data_out_4, dop(0) => dp(4), addr => addr(10 downto 0), clk => clk, di => data_in, dip(0) => dp(4), en => ce(4), ssr => rst, we => we ); RAM5 : RAMB16_S9 generic map ( INIT_00 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_01 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_02 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_03 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_04 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_05 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_06 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_07 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_08 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_09 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_0A => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_0B => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_0C => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_0D => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_0E => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_0F => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_10 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_11 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_12 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_13 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_14 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_15 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_16 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_17 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_18 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_19 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_1A => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_1B => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_1C => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_1D => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_1E => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_1F => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_20 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_21 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_22 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_23 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_24 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_25 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_26 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_27 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_28 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_29 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_2A => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_2B => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_2C => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_2D => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_2E => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_2F => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_30 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_31 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_32 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_33 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_34 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_35 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_36 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_37 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_38 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_39 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_3A => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_3B => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_3C => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_3D => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_3E => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_3F => x"0000000000000000000000000000000000000000000000000000000000000000" ) port map ( do => data_out_5, dop(0) => dp(5), addr => addr(10 downto 0), clk => clk, di => data_in, dip(0) => dp(5), en => ce(5), ssr => rst, we => we ); RAM6 : RAMB16_S9 generic map ( INIT_00 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_01 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_02 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_03 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_04 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_05 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_06 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_07 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_08 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_09 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_0A => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_0B => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_0C => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_0D => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_0E => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_0F => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_10 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_11 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_12 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_13 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_14 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_15 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_16 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_17 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_18 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_19 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_1A => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_1B => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_1C => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_1D => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_1E => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_1F => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_20 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_21 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_22 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_23 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_24 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_25 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_26 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_27 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_28 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_29 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_2A => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_2B => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_2C => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_2D => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_2E => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_2F => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_30 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_31 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_32 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_33 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_34 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_35 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_36 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_37 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_38 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_39 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_3A => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_3B => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_3C => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_3D => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_3E => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_3F => x"0000000000000000000000000000000000000000000000000000000000000000" ) port map ( do => data_out_6, dop(0) => dp(6), addr => addr(10 downto 0), clk => clk, di => data_in, dip(0) => dp(6), en => ce(6), ssr => rst, we => we ); RAM7 : RAMB16_S9 generic map ( INIT_00 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_01 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_02 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_03 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_04 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_05 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_06 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_07 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_08 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_09 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_0A => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_0B => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_0C => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_0D => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_0E => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_0F => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_10 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_11 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_12 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_13 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_14 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_15 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_16 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_17 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_18 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_19 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_1A => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_1B => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_1C => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_1D => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_1E => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_1F => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_20 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_21 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_22 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_23 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_24 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_25 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_26 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_27 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_28 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_29 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_2A => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_2B => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_2C => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_2D => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_2E => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_2F => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_30 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_31 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_32 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_33 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_34 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_35 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_36 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_37 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_38 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_39 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_3A => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_3B => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_3C => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_3D => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_3E => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_3F => x"0000000000000000000000000000000000000000000000000000000000000000" ) port map ( do => data_out_7, dop(0) => dp(7), addr => addr(10 downto 0), clk => clk, di => data_in, dip(0) => dp(7), en => ce(7), ssr => rst, we => we ); RAM8 : RAMB16_S9 generic map ( INIT_00 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_01 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_02 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_03 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_04 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_05 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_06 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_07 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_08 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_09 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_0A => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_0B => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_0C => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_0D => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_0E => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_0F => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_10 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_11 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_12 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_13 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_14 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_15 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_16 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_17 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_18 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_19 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_1A => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_1B => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_1C => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_1D => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_1E => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_1F => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_20 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_21 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_22 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_23 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_24 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_25 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_26 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_27 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_28 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_29 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_2A => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_2B => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_2C => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_2D => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_2E => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_2F => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_30 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_31 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_32 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_33 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_34 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_35 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_36 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_37 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_38 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_39 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_3A => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_3B => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_3C => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_3D => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_3E => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_3F => x"0000000000000000000000000000000000000000000000000000000000000000" ) port map ( do => data_out_8, dop(0) => dp(8), addr => addr(10 downto 0), clk => clk, di => data_in, dip(0) => dp(8), en => ce(8), ssr => rst, we => we ); RAM9 : RAMB16_S9 generic map ( INIT_00 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_01 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_02 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_03 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_04 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_05 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_06 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_07 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_08 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_09 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_0A => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_0B => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_0C => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_0D => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_0E => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_0F => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_10 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_11 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_12 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_13 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_14 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_15 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_16 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_17 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_18 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_19 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_1A => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_1B => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_1C => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_1D => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_1E => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_1F => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_20 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_21 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_22 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_23 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_24 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_25 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_26 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_27 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_28 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_29 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_2A => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_2B => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_2C => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_2D => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_2E => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_2F => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_30 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_31 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_32 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_33 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_34 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_35 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_36 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_37 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_38 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_39 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_3A => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_3B => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_3C => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_3D => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_3E => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_3F => x"0000000000000000000000000000000000000000000000000000000000000000" ) port map ( do => data_out_9, dop(0) => dp(9), addr => addr(10 downto 0), clk => clk, di => data_in, dip(0) => dp(9), en => ce(9), ssr => rst, we => we ); RAMA : RAMB16_S9 generic map ( INIT_00 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_01 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_02 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_03 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_04 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_05 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_06 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_07 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_08 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_09 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_0A => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_0B => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_0C => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_0D => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_0E => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_0F => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_10 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_11 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_12 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_13 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_14 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_15 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_16 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_17 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_18 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_19 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_1A => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_1B => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_1C => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_1D => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_1E => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_1F => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_20 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_21 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_22 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_23 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_24 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_25 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_26 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_27 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_28 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_29 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_2A => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_2B => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_2C => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_2D => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_2E => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_2F => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_30 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_31 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_32 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_33 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_34 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_35 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_36 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_37 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_38 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_39 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_3A => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_3B => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_3C => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_3D => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_3E => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_3F => x"0000000000000000000000000000000000000000000000000000000000000000" ) port map ( do => data_out_a, dop(0) => dp(10), addr => addr(10 downto 0), clk => clk, di => data_in, dip(0) => dp(10), en => ce(10), ssr => rst, we => we ); RAMB : RAMB16_S9 generic map ( INIT_00 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_01 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_02 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_03 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_04 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_05 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_06 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_07 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_08 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_09 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_0A => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_0B => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_0C => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_0D => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_0E => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_0F => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_10 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_11 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_12 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_13 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_14 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_15 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_16 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_17 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_18 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_19 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_1A => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_1B => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_1C => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_1D => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_1E => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_1F => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_20 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_21 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_22 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_23 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_24 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_25 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_26 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_27 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_28 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_29 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_2A => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_2B => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_2C => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_2D => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_2E => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_2F => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_30 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_31 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_32 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_33 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_34 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_35 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_36 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_37 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_38 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_39 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_3A => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_3B => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_3C => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_3D => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_3E => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_3F => x"0000000000000000000000000000000000000000000000000000000000000000" ) port map ( do => data_out_b, dop(0) => dp(11), addr => addr(10 downto 0), clk => clk, di => data_in, dip(0) => dp(11), en => ce(11), ssr => rst, we => we ); RAMC : RAMB16_S9 generic map ( INIT_00 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_01 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_02 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_03 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_04 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_05 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_06 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_07 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_08 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_09 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_0A => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_0B => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_0C => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_0D => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_0E => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_0F => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_10 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_11 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_12 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_13 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_14 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_15 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_16 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_17 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_18 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_19 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_1A => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_1B => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_1C => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_1D => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_1E => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_1F => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_20 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_21 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_22 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_23 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_24 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_25 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_26 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_27 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_28 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_29 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_2A => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_2B => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_2C => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_2D => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_2E => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_2F => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_30 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_31 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_32 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_33 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_34 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_35 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_36 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_37 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_38 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_39 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_3A => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_3B => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_3C => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_3D => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_3E => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_3F => x"0000000000000000000000000000000000000000000000000000000000000000" ) port map ( do => data_out_c, dop(0) => dp(12), addr => addr(10 downto 0), clk => clk, di => data_in, dip(0) => dp(12), en => ce(12), ssr => rst, we => we ); RAMD : RAMB16_S9 generic map ( INIT_00 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_01 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_02 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_03 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_04 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_05 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_06 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_07 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_08 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_09 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_0A => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_0B => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_0C => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_0D => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_0E => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_0F => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_10 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_11 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_12 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_13 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_14 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_15 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_16 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_17 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_18 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_19 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_1A => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_1B => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_1C => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_1D => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_1E => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_1F => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_20 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_21 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_22 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_23 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_24 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_25 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_26 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_27 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_28 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_29 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_2A => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_2B => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_2C => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_2D => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_2E => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_2F => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_30 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_31 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_32 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_33 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_34 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_35 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_36 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_37 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_38 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_39 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_3A => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_3B => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_3C => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_3D => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_3E => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_3F => x"0000000000000000000000000000000000000000000000000000000000000000" ) port map ( do => data_out_d, dop(0) => dp(13), addr => addr(10 downto 0), clk => clk, di => data_in, dip(0) => dp(13), en => ce(13), ssr => rst, we => we ); RAME : RAMB16_S9 generic map ( INIT_00 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_01 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_02 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_03 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_04 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_05 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_06 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_07 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_08 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_09 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_0A => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_0B => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_0C => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_0D => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_0E => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_0F => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_10 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_11 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_12 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_13 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_14 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_15 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_16 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_17 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_18 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_19 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_1A => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_1B => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_1C => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_1D => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_1E => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_1F => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_20 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_21 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_22 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_23 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_24 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_25 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_26 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_27 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_28 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_29 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_2A => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_2B => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_2C => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_2D => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_2E => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_2F => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_30 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_31 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_32 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_33 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_34 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_35 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_36 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_37 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_38 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_39 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_3A => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_3B => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_3C => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_3D => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_3E => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_3F => x"0000000000000000000000000000000000000000000000000000000000000000" ) port map ( do => data_out_e, dop(0) => dp(14), addr => addr(10 downto 0), clk => clk, di => data_in, dip(0) => dp(14), en => ce(14), ssr => rst, we => we ); RAMF : RAMB16_S9 generic map ( INIT_00 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_01 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_02 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_03 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_04 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_05 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_06 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_07 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_08 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_09 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_0A => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_0B => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_0C => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_0D => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_0E => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_0F => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_10 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_11 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_12 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_13 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_14 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_15 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_16 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_17 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_18 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_19 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_1A => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_1B => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_1C => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_1D => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_1E => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_1F => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_20 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_21 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_22 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_23 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_24 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_25 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_26 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_27 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_28 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_29 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_2A => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_2B => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_2C => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_2D => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_2E => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_2F => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_30 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_31 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_32 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_33 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_34 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_35 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_36 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_37 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_38 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_39 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_3A => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_3B => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_3C => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_3D => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_3E => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_3F => x"0000000000000000000000000000000000000000000000000000000000000000" ) port map ( do => data_out_f, dop(0) => dp(15), addr => addr(10 downto 0), clk => clk, di => data_in, dip(0) => dp(15), en => ce(15), ssr => rst, we => we ); my_ram_32k : process ( cs, rw, addr, data_out_0, data_out_1, data_out_2, data_out_3, data_out_4, data_out_5, data_out_6, data_out_7, data_out_8, data_out_9, data_out_a, data_out_b, data_out_c, data_out_d, data_out_e, data_out_f ) begin we <= not rw; case addr(14 downto 11) is when "0000" => data_out <= data_out_0; when "0001" => data_out <= data_out_1; when "0010" => data_out <= data_out_2; when "0011" => data_out <= data_out_3; when "0100" => data_out <= data_out_4; when "0101" => data_out <= data_out_5; when "0110" => data_out <= data_out_6; when "0111" => data_out <= data_out_7; when "1000" => data_out <= data_out_8; when "1001" => data_out <= data_out_9; when "1010" => data_out <= data_out_a; when "1011" => data_out <= data_out_b; when "1100" => data_out <= data_out_c; when "1101" => data_out <= data_out_d; when "1110" => data_out <= data_out_e; when "1111" => data_out <= data_out_f; when others => null; end case; ce(0) <= cs and not( addr(14) ) and not( addr(13) ) and not( addr(12) ) and not( addr(11) ); ce(1) <= cs and not( addr(14) ) and not( addr(13) ) and not( addr(12) ) and addr(11) ; ce(2) <= cs and not( addr(14) ) and not( addr(13) ) and addr(12) and not( addr(11) ); ce(3) <= cs and not( addr(14) ) and not( addr(13) ) and addr(12) and addr(11) ; ce(4) <= cs and not( addr(14) ) and addr(13) and not( addr(12) ) and not( addr(11) ); ce(5) <= cs and not( addr(14) ) and addr(13) and not( addr(12) ) and addr(11) ; ce(6) <= cs and not( addr(14) ) and addr(13) and addr(12) and not( addr(11) ); ce(7) <= cs and not( addr(14) ) and addr(13) and addr(12) and addr(11) ; ce(8) <= cs and addr(14) and not( addr(13) ) and not( addr(12) ) and not( addr(11) ); ce(9) <= cs and addr(14) and not( addr(13) ) and not( addr(12) ) and addr(11) ; ce(10) <= cs and addr(14) and not( addr(13) ) and addr(12) and not( addr(11) ); ce(11) <= cs and addr(14) and not( addr(13) ) and addr(12) and addr(11) ; ce(12) <= cs and addr(14) and addr(13) and not( addr(12) ) and not( addr(11) ); ce(13) <= cs and addr(14) and addr(13) and not( addr(12) ) and addr(11) ; ce(14) <= cs and addr(14) and addr(13) and addr(12) and not( addr(11) ); ce(15) <= cs and addr(14) and addr(13) and addr(12) and addr(11) ; end process; end architecture rtl;
gpl-3.0
6cc563058275b2355df7f31c71349b97
0.803817
7.339255
false
false
false
false
dcliche/mdsynth
rtl/test_benches/channel_tb/src/channel_tb.vhd
1
5,447
-- MDSynth Sound Chip Test Bench -- -- Copyright (c) 2012-2022, Daniel Cliche -- All rights reserved. -- -- Redistribution and use in source and binary forms, with or without modification, are permitted provided that the -- following conditions are met: -- -- * Redistributions of source code must retain the above copyright notice, this list of conditions and the -- following disclaimer. -- * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the -- following disclaimer in the documentation and/or other materials provided with the distribution. -- -- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, -- INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -- DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -- SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR -- SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -- WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE -- USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.NUMERIC_STD.ALL; entity channel_tb is port ( clk_50mhz: in std_logic; btn_south: in std_logic; btn_north: in std_logic; sw: in std_logic_vector(3 downto 0); aud_l: out std_logic; aud_r: out std_logic; aux_aud_l: out std_logic; aux_aud_r: out std_logic ); end entity channel_tb; architecture channel_tb_arch of channel_tb is component pitch_to_freq is port ( pitch: in unsigned(6 downto 0); -- 60 = C4 phase_delta: out unsigned(11 downto 0); octave: out unsigned(3 downto 0)); end component; component dac is generic( MSBI : integer := 9 ); port ( clk: in std_logic; dac_in: in std_logic_vector(MSBI downto 0); reset: in std_logic; dac_out: out std_logic); end component dac; signal channel_out: std_logic; signal pitch_message: unsigned (6 downto 0) := to_unsigned(69, 7); signal pitch_carrier: unsigned (6 downto 0) := to_unsigned(69, 7); signal counter: unsigned (31 downto 0) := to_unsigned(0, 32); signal waveform: std_logic_vector(2 downto 0) := "100"; signal phase_delta_message: unsigned(11 downto 0); signal phase_delta_carrier: unsigned(11 downto 0); signal octave_message: unsigned(3 downto 0); signal octave_carrier: unsigned(3 downto 0); signal gain_message: unsigned(5 downto 0) := to_unsigned(63, 6); signal gain_modulated: unsigned(5 downto 0) := to_unsigned(63, 6); signal reset_phase: std_logic := '0'; signal dac_direct_value: std_logic_vector(7 downto 0) := "00000000"; signal note_on: std_logic := '0'; signal waveform_message: std_logic_vector(1 downto 0) := "00"; signal waveform_modulated: std_logic_vector(1 downto 0) := "00"; signal attack_rate: unsigned(3 downto 0) := to_unsigned(10, 4); signal release_rate: unsigned(3 downto 0) := to_unsigned(5, 4); signal dac_in: std_logic_vector(7 downto 0); begin pitch_to_freq_carrier0: pitch_to_freq port map (pitch => pitch_message, phase_delta => phase_delta_message, octave => octave_message); pitch_to_freq_message0: pitch_to_freq port map (pitch => pitch_carrier, phase_delta => phase_delta_carrier, octave => octave_carrier); channel0: entity work.channel port map ( clk => clk_50mhz, reset => btn_south, waveform => waveform, note_on => note_on, gain_message => gain_message, gain_modulated => gain_modulated, phase_delta => phase_delta_message, -- Note: phase_delta_carrier is not used octave_message => octave_message, octave_carrier => octave_carrier, waveform_message => waveform_message, waveform_modulated => waveform_modulated, attack_rate => attack_rate, release_rate => release_rate, reset_phase => reset_phase, dac_direct_value => dac_direct_value, output => dac_in); dac0 : dac generic map (MSBI => 7) port map (clk => clk_50mhz, dac_in => dac_in, reset => btn_south, dac_out => channel_out); waveform <= sw(2 downto 0); aud_l <= channel_out; aud_r <= channel_out; aux_aud_l <= channel_out; aux_aud_r <= channel_out; process (clk_50mhz, btn_south) begin if (btn_south = '1') then reset_phase <= '1'; elsif (rising_edge(clk_50mhz)) then reset_phase <= '0'; note_on <= btn_north; -- if (counter = 0) then --counter <= to_unsigned(5000000, 32); -- counter <= to_unsigned(200, 32); -- note_on <= not note_on; -- pitch_message <= pitch_message + 1; -- if (pitch_message = 0) then -- gain_message <= gain_message - 8; -- gain_modulated <= gain_modulated - 8; -- end if; -- else -- counter <= counter - 1; -- end if; end if; end process; end architecture channel_tb_arch;
gpl-3.0
52c50ca97ad90b13bdee2c389acb238c
0.639067
3.690379
false
false
false
false
jairov4/accel-oil
impl/impl_test_single/hdl/elaborate/lmb_bram_elaborate_v1_00_a/hdl/vhdl/lmb_bram_elaborate.vhd
1
13,280
------------------------------------------------------------------------------- -- lmb_bram_elaborate.vhd ------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity lmb_bram_elaborate is generic ( C_MEMSIZE : integer; C_PORT_DWIDTH : integer; C_PORT_AWIDTH : integer; C_NUM_WE : integer; C_FAMILY : string ); port ( BRAM_Rst_A : in std_logic; BRAM_Clk_A : in std_logic; BRAM_EN_A : in std_logic; BRAM_WEN_A : in std_logic_vector(0 to C_NUM_WE-1); BRAM_Addr_A : in std_logic_vector(0 to C_PORT_AWIDTH-1); BRAM_Din_A : out std_logic_vector(0 to C_PORT_DWIDTH-1); BRAM_Dout_A : in std_logic_vector(0 to C_PORT_DWIDTH-1); BRAM_Rst_B : in std_logic; BRAM_Clk_B : in std_logic; BRAM_EN_B : in std_logic; BRAM_WEN_B : in std_logic_vector(0 to C_NUM_WE-1); BRAM_Addr_B : in std_logic_vector(0 to C_PORT_AWIDTH-1); BRAM_Din_B : out std_logic_vector(0 to C_PORT_DWIDTH-1); BRAM_Dout_B : in std_logic_vector(0 to C_PORT_DWIDTH-1) ); attribute keep_hierarchy : STRING; attribute keep_hierarchy of lmb_bram_elaborate : entity is "yes"; end lmb_bram_elaborate; architecture STRUCTURE of lmb_bram_elaborate is component RAMB36 is generic ( WRITE_MODE_A : string; WRITE_MODE_B : string; INIT_FILE : string; READ_WIDTH_A : integer; READ_WIDTH_B : integer; WRITE_WIDTH_A : integer; WRITE_WIDTH_B : integer; RAM_EXTENSION_A : string; RAM_EXTENSION_B : string ); port ( ADDRA : in std_logic_vector(15 downto 0); CASCADEINLATA : in std_logic; CASCADEINREGA : in std_logic; CASCADEOUTLATA : out std_logic; CASCADEOUTREGA : out std_logic; CLKA : in std_logic; DIA : in std_logic_vector(31 downto 0); DIPA : in std_logic_vector(3 downto 0); DOA : out std_logic_vector(31 downto 0); DOPA : out std_logic_vector(3 downto 0); ENA : in std_logic; REGCEA : in std_logic; SSRA : in std_logic; WEA : in std_logic_vector(3 downto 0); ADDRB : in std_logic_vector(15 downto 0); CASCADEINLATB : in std_logic; CASCADEINREGB : in std_logic; CASCADEOUTLATB : out std_logic; CASCADEOUTREGB : out std_logic; CLKB : in std_logic; DIB : in std_logic_vector(31 downto 0); DIPB : in std_logic_vector(3 downto 0); DOB : out std_logic_vector(31 downto 0); DOPB : out std_logic_vector(3 downto 0); ENB : in std_logic; REGCEB : in std_logic; SSRB : in std_logic; WEB : in std_logic_vector(3 downto 0) ); end component; attribute BMM_INFO : STRING; attribute BMM_INFO of ramb36_0: label is " "; attribute BMM_INFO of ramb36_1: label is " "; attribute BMM_INFO of ramb36_2: label is " "; attribute BMM_INFO of ramb36_3: label is " "; -- Internal signals signal net_gnd0 : std_logic; signal net_gnd4 : std_logic_vector(3 downto 0); signal pgassign1 : std_logic_vector(0 to 0); signal pgassign2 : std_logic_vector(0 to 2); signal pgassign3 : std_logic_vector(0 to 23); signal pgassign4 : std_logic_vector(15 downto 0); signal pgassign5 : std_logic_vector(31 downto 0); signal pgassign6 : std_logic_vector(31 downto 0); signal pgassign7 : std_logic_vector(3 downto 0); signal pgassign8 : std_logic_vector(15 downto 0); signal pgassign9 : std_logic_vector(31 downto 0); signal pgassign10 : std_logic_vector(31 downto 0); signal pgassign11 : std_logic_vector(3 downto 0); signal pgassign12 : std_logic_vector(15 downto 0); signal pgassign13 : std_logic_vector(31 downto 0); signal pgassign14 : std_logic_vector(31 downto 0); signal pgassign15 : std_logic_vector(3 downto 0); signal pgassign16 : std_logic_vector(15 downto 0); signal pgassign17 : std_logic_vector(31 downto 0); signal pgassign18 : std_logic_vector(31 downto 0); signal pgassign19 : std_logic_vector(3 downto 0); signal pgassign20 : std_logic_vector(15 downto 0); signal pgassign21 : std_logic_vector(31 downto 0); signal pgassign22 : std_logic_vector(31 downto 0); signal pgassign23 : std_logic_vector(3 downto 0); signal pgassign24 : std_logic_vector(15 downto 0); signal pgassign25 : std_logic_vector(31 downto 0); signal pgassign26 : std_logic_vector(31 downto 0); signal pgassign27 : std_logic_vector(3 downto 0); signal pgassign28 : std_logic_vector(15 downto 0); signal pgassign29 : std_logic_vector(31 downto 0); signal pgassign30 : std_logic_vector(31 downto 0); signal pgassign31 : std_logic_vector(3 downto 0); signal pgassign32 : std_logic_vector(15 downto 0); signal pgassign33 : std_logic_vector(31 downto 0); signal pgassign34 : std_logic_vector(31 downto 0); signal pgassign35 : std_logic_vector(3 downto 0); begin -- Internal assignments pgassign1(0 to 0) <= B"1"; pgassign2(0 to 2) <= B"000"; pgassign3(0 to 23) <= B"000000000000000000000000"; pgassign4(15 downto 15) <= B"1"; pgassign4(14 downto 3) <= BRAM_Addr_A(18 to 29); pgassign4(2 downto 0) <= B"000"; pgassign5(31 downto 8) <= B"000000000000000000000000"; pgassign5(7 downto 0) <= BRAM_Dout_A(0 to 7); BRAM_Din_A(0 to 7) <= pgassign6(7 downto 0); pgassign7(3 downto 3) <= BRAM_WEN_A(0 to 0); pgassign7(2 downto 2) <= BRAM_WEN_A(0 to 0); pgassign7(1 downto 1) <= BRAM_WEN_A(0 to 0); pgassign7(0 downto 0) <= BRAM_WEN_A(0 to 0); pgassign8(15 downto 15) <= B"1"; pgassign8(14 downto 3) <= BRAM_Addr_B(18 to 29); pgassign8(2 downto 0) <= B"000"; pgassign9(31 downto 8) <= B"000000000000000000000000"; pgassign9(7 downto 0) <= BRAM_Dout_B(0 to 7); BRAM_Din_B(0 to 7) <= pgassign10(7 downto 0); pgassign11(3 downto 3) <= BRAM_WEN_B(0 to 0); pgassign11(2 downto 2) <= BRAM_WEN_B(0 to 0); pgassign11(1 downto 1) <= BRAM_WEN_B(0 to 0); pgassign11(0 downto 0) <= BRAM_WEN_B(0 to 0); pgassign12(15 downto 15) <= B"1"; pgassign12(14 downto 3) <= BRAM_Addr_A(18 to 29); pgassign12(2 downto 0) <= B"000"; pgassign13(31 downto 8) <= B"000000000000000000000000"; pgassign13(7 downto 0) <= BRAM_Dout_A(8 to 15); BRAM_Din_A(8 to 15) <= pgassign14(7 downto 0); pgassign15(3 downto 3) <= BRAM_WEN_A(1 to 1); pgassign15(2 downto 2) <= BRAM_WEN_A(1 to 1); pgassign15(1 downto 1) <= BRAM_WEN_A(1 to 1); pgassign15(0 downto 0) <= BRAM_WEN_A(1 to 1); pgassign16(15 downto 15) <= B"1"; pgassign16(14 downto 3) <= BRAM_Addr_B(18 to 29); pgassign16(2 downto 0) <= B"000"; pgassign17(31 downto 8) <= B"000000000000000000000000"; pgassign17(7 downto 0) <= BRAM_Dout_B(8 to 15); BRAM_Din_B(8 to 15) <= pgassign18(7 downto 0); pgassign19(3 downto 3) <= BRAM_WEN_B(1 to 1); pgassign19(2 downto 2) <= BRAM_WEN_B(1 to 1); pgassign19(1 downto 1) <= BRAM_WEN_B(1 to 1); pgassign19(0 downto 0) <= BRAM_WEN_B(1 to 1); pgassign20(15 downto 15) <= B"1"; pgassign20(14 downto 3) <= BRAM_Addr_A(18 to 29); pgassign20(2 downto 0) <= B"000"; pgassign21(31 downto 8) <= B"000000000000000000000000"; pgassign21(7 downto 0) <= BRAM_Dout_A(16 to 23); BRAM_Din_A(16 to 23) <= pgassign22(7 downto 0); pgassign23(3 downto 3) <= BRAM_WEN_A(2 to 2); pgassign23(2 downto 2) <= BRAM_WEN_A(2 to 2); pgassign23(1 downto 1) <= BRAM_WEN_A(2 to 2); pgassign23(0 downto 0) <= BRAM_WEN_A(2 to 2); pgassign24(15 downto 15) <= B"1"; pgassign24(14 downto 3) <= BRAM_Addr_B(18 to 29); pgassign24(2 downto 0) <= B"000"; pgassign25(31 downto 8) <= B"000000000000000000000000"; pgassign25(7 downto 0) <= BRAM_Dout_B(16 to 23); BRAM_Din_B(16 to 23) <= pgassign26(7 downto 0); pgassign27(3 downto 3) <= BRAM_WEN_B(2 to 2); pgassign27(2 downto 2) <= BRAM_WEN_B(2 to 2); pgassign27(1 downto 1) <= BRAM_WEN_B(2 to 2); pgassign27(0 downto 0) <= BRAM_WEN_B(2 to 2); pgassign28(15 downto 15) <= B"1"; pgassign28(14 downto 3) <= BRAM_Addr_A(18 to 29); pgassign28(2 downto 0) <= B"000"; pgassign29(31 downto 8) <= B"000000000000000000000000"; pgassign29(7 downto 0) <= BRAM_Dout_A(24 to 31); BRAM_Din_A(24 to 31) <= pgassign30(7 downto 0); pgassign31(3 downto 3) <= BRAM_WEN_A(3 to 3); pgassign31(2 downto 2) <= BRAM_WEN_A(3 to 3); pgassign31(1 downto 1) <= BRAM_WEN_A(3 to 3); pgassign31(0 downto 0) <= BRAM_WEN_A(3 to 3); pgassign32(15 downto 15) <= B"1"; pgassign32(14 downto 3) <= BRAM_Addr_B(18 to 29); pgassign32(2 downto 0) <= B"000"; pgassign33(31 downto 8) <= B"000000000000000000000000"; pgassign33(7 downto 0) <= BRAM_Dout_B(24 to 31); BRAM_Din_B(24 to 31) <= pgassign34(7 downto 0); pgassign35(3 downto 3) <= BRAM_WEN_B(3 to 3); pgassign35(2 downto 2) <= BRAM_WEN_B(3 to 3); pgassign35(1 downto 1) <= BRAM_WEN_B(3 to 3); pgassign35(0 downto 0) <= BRAM_WEN_B(3 to 3); net_gnd0 <= '0'; net_gnd4(3 downto 0) <= B"0000"; ramb36_0 : RAMB36 generic map ( WRITE_MODE_A => "WRITE_FIRST", WRITE_MODE_B => "WRITE_FIRST", INIT_FILE => "lmb_bram_combined_0.mem", READ_WIDTH_A => 9, READ_WIDTH_B => 9, WRITE_WIDTH_A => 9, WRITE_WIDTH_B => 9, RAM_EXTENSION_A => "NONE", RAM_EXTENSION_B => "NONE" ) port map ( ADDRA => pgassign4, CASCADEINLATA => net_gnd0, CASCADEINREGA => net_gnd0, CASCADEOUTLATA => open, CASCADEOUTREGA => open, CLKA => BRAM_Clk_A, DIA => pgassign5, DIPA => net_gnd4, DOA => pgassign6, DOPA => open, ENA => BRAM_EN_A, REGCEA => net_gnd0, SSRA => BRAM_Rst_A, WEA => pgassign7, ADDRB => pgassign8, CASCADEINLATB => net_gnd0, CASCADEINREGB => net_gnd0, CASCADEOUTLATB => open, CASCADEOUTREGB => open, CLKB => BRAM_Clk_B, DIB => pgassign9, DIPB => net_gnd4, DOB => pgassign10, DOPB => open, ENB => BRAM_EN_B, REGCEB => net_gnd0, SSRB => BRAM_Rst_B, WEB => pgassign11 ); ramb36_1 : RAMB36 generic map ( WRITE_MODE_A => "WRITE_FIRST", WRITE_MODE_B => "WRITE_FIRST", INIT_FILE => "lmb_bram_combined_1.mem", READ_WIDTH_A => 9, READ_WIDTH_B => 9, WRITE_WIDTH_A => 9, WRITE_WIDTH_B => 9, RAM_EXTENSION_A => "NONE", RAM_EXTENSION_B => "NONE" ) port map ( ADDRA => pgassign12, CASCADEINLATA => net_gnd0, CASCADEINREGA => net_gnd0, CASCADEOUTLATA => open, CASCADEOUTREGA => open, CLKA => BRAM_Clk_A, DIA => pgassign13, DIPA => net_gnd4, DOA => pgassign14, DOPA => open, ENA => BRAM_EN_A, REGCEA => net_gnd0, SSRA => BRAM_Rst_A, WEA => pgassign15, ADDRB => pgassign16, CASCADEINLATB => net_gnd0, CASCADEINREGB => net_gnd0, CASCADEOUTLATB => open, CASCADEOUTREGB => open, CLKB => BRAM_Clk_B, DIB => pgassign17, DIPB => net_gnd4, DOB => pgassign18, DOPB => open, ENB => BRAM_EN_B, REGCEB => net_gnd0, SSRB => BRAM_Rst_B, WEB => pgassign19 ); ramb36_2 : RAMB36 generic map ( WRITE_MODE_A => "WRITE_FIRST", WRITE_MODE_B => "WRITE_FIRST", INIT_FILE => "lmb_bram_combined_2.mem", READ_WIDTH_A => 9, READ_WIDTH_B => 9, WRITE_WIDTH_A => 9, WRITE_WIDTH_B => 9, RAM_EXTENSION_A => "NONE", RAM_EXTENSION_B => "NONE" ) port map ( ADDRA => pgassign20, CASCADEINLATA => net_gnd0, CASCADEINREGA => net_gnd0, CASCADEOUTLATA => open, CASCADEOUTREGA => open, CLKA => BRAM_Clk_A, DIA => pgassign21, DIPA => net_gnd4, DOA => pgassign22, DOPA => open, ENA => BRAM_EN_A, REGCEA => net_gnd0, SSRA => BRAM_Rst_A, WEA => pgassign23, ADDRB => pgassign24, CASCADEINLATB => net_gnd0, CASCADEINREGB => net_gnd0, CASCADEOUTLATB => open, CASCADEOUTREGB => open, CLKB => BRAM_Clk_B, DIB => pgassign25, DIPB => net_gnd4, DOB => pgassign26, DOPB => open, ENB => BRAM_EN_B, REGCEB => net_gnd0, SSRB => BRAM_Rst_B, WEB => pgassign27 ); ramb36_3 : RAMB36 generic map ( WRITE_MODE_A => "WRITE_FIRST", WRITE_MODE_B => "WRITE_FIRST", INIT_FILE => "lmb_bram_combined_3.mem", READ_WIDTH_A => 9, READ_WIDTH_B => 9, WRITE_WIDTH_A => 9, WRITE_WIDTH_B => 9, RAM_EXTENSION_A => "NONE", RAM_EXTENSION_B => "NONE" ) port map ( ADDRA => pgassign28, CASCADEINLATA => net_gnd0, CASCADEINREGA => net_gnd0, CASCADEOUTLATA => open, CASCADEOUTREGA => open, CLKA => BRAM_Clk_A, DIA => pgassign29, DIPA => net_gnd4, DOA => pgassign30, DOPA => open, ENA => BRAM_EN_A, REGCEA => net_gnd0, SSRA => BRAM_Rst_A, WEA => pgassign31, ADDRB => pgassign32, CASCADEINLATB => net_gnd0, CASCADEINREGB => net_gnd0, CASCADEOUTLATB => open, CASCADEOUTREGB => open, CLKB => BRAM_Clk_B, DIB => pgassign33, DIPB => net_gnd4, DOB => pgassign34, DOPB => open, ENB => BRAM_EN_B, REGCEB => net_gnd0, SSRB => BRAM_Rst_B, WEB => pgassign35 ); end architecture STRUCTURE;
lgpl-3.0
9575c9d53ea2900eb046f1cf33bd5694
0.602108
3.220175
false
false
false
false
jairov4/accel-oil
solution_virtex5_plb/impl/pcores/nfa_accept_samples_generic_hw_top_v1_01_a/simhdl/vhdl/nfa_forward_buckets_if_ap_fifo.vhd
2
2,843
-- ============================================================== -- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC -- Version: 2014.1 -- Copyright (C) 2014 Xilinx Inc. All rights reserved. -- -- ============================================================== library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; entity nfa_forward_buckets_if_ap_fifo is generic ( DATA_WIDTH : integer := 32; ADDR_WIDTH : integer := 16; DEPTH : integer := 1); port ( clk : IN STD_LOGIC; reset : IN STD_LOGIC; if_empty_n : OUT STD_LOGIC; if_read_ce : IN STD_LOGIC := '1'; if_read : IN STD_LOGIC; if_dout : OUT STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0); if_full_n : OUT STD_LOGIC; if_write_ce : IN STD_LOGIC := '1'; if_write : IN STD_LOGIC; if_din : IN STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0)); end entity; architecture rtl of nfa_forward_buckets_if_ap_fifo is type memtype is array (0 to DEPTH - 1) of STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0); signal mStorage : memtype := (others => (others => '0')); signal mInPtr : UNSIGNED(ADDR_WIDTH - 1 downto 0) := (others => '0'); signal mOutPtr : UNSIGNED(ADDR_WIDTH - 1 downto 0) := (others => '0'); signal internal_empty_n, internal_full_n : STD_LOGIC; signal mFlag_nEF_hint : STD_LOGIC := '0'; -- 0: empty hint, 1: full hint begin if_dout <= mStorage(CONV_INTEGER(mOutPtr)); if_empty_n <= internal_empty_n; if_full_n <= internal_full_n; internal_empty_n <= '0' when mInPtr = mOutPtr and mFlag_nEF_hint = '0' else '1'; internal_full_n <= '0' when mInptr = mOutPtr and mFlag_nEF_hint = '1' else '1'; process (clk, reset) begin if reset = '1' then mInPtr <= (others => '0'); mOutPtr <= (others => '0'); mFlag_nEF_hint <= '0'; -- empty hint elsif clk'event and clk = '1' then if if_read_ce = '1' and if_read = '1' and internal_empty_n = '1' then if (mOutPtr = DEPTH -1) then mOutPtr <= (others => '0'); mFlag_nEF_hint <= not mFlag_nEF_hint; else mOutPtr <= mOutPtr + 1; end if; end if; if if_write_ce = '1' and if_write = '1' and internal_full_n = '1' then mStorage(CONV_INTEGER(mInPtr)) <= if_din; if (mInPtr = DEPTH -1) then mInPtr <= (others => '0'); mFlag_nEF_hint <= not mFlag_nEF_hint; else mInPtr <= mInPtr + 1; end if; end if; end if; end process; end architecture;
lgpl-3.0
65248f71cd1ce413a0a5e14d9d9c1b16
0.495603
3.649551
false
false
false
false
grwlf/vsim
vhdl_ct/ct00159.vhd
1
25,028
-- NEED RESULT: ARCH00159.P1: Multi inertial transactions occurred on signal asg with indexed name prefixed by an indexed name on LHS passed -- NEED RESULT: ARCH00159.P2: Multi inertial transactions occurred on signal asg with indexed name prefixed by an indexed name on LHS passed -- NEED RESULT: ARCH00159.P3: Multi inertial transactions occurred on signal asg with indexed name prefixed by an indexed name on LHS passed -- NEED RESULT: ARCH00159: One inertial transaction occurred on signal asg with indexed name prefixed by an indexed name on LHS passed -- NEED RESULT: ARCH00159: One inertial transaction occurred on signal asg with indexed name prefixed by an indexed name on LHS passed -- NEED RESULT: ARCH00159: One inertial transaction occurred on signal asg with indexed name prefixed by an indexed name on LHS passed -- NEED RESULT: ARCH00159: Old transactions were removed on signal asg with indexed name prefixed by an indexed name on LHS passed -- NEED RESULT: ARCH00159: Old transactions were removed on signal asg with indexed name prefixed by an indexed name on LHS passed -- NEED RESULT: ARCH00159: Old transactions were removed on signal asg with indexed name prefixed by an indexed name on LHS passed -- NEED RESULT: ARCH00159: One inertial transaction occurred on signal asg with indexed name prefixed by an indexed name on LHS passed -- NEED RESULT: ARCH00159: One inertial transaction occurred on signal asg with indexed name prefixed by an indexed name on LHS passed -- NEED RESULT: ARCH00159: One inertial transaction occurred on signal asg with indexed name prefixed by an indexed name on LHS passed -- NEED RESULT: ARCH00159: Inertial semantics check on a signal asg with indexed name prefixed by an indexed name on LHS passed -- NEED RESULT: ARCH00159: Inertial semantics check on a signal asg with indexed name prefixed by an indexed name on LHS passed -- NEED RESULT: ARCH00159: Inertial semantics check on a signal asg with indexed name prefixed by an indexed name on LHS passed -- NEED RESULT: P3: Inertial transactions entirely completed passed -- NEED RESULT: P2: Inertial transactions entirely completed passed -- NEED RESULT: P1: Inertial transactions entirely completed passed ------------------------------------------------------------------------------- -- -- Copyright (c) 1989 by Intermetrics, Inc. -- All rights reserved. -- ------------------------------------------------------------------------------- -- -- TEST NAME: -- -- CT00159 -- -- AUTHOR: -- -- G. Tominovich -- -- TEST OBJECTIVES: -- -- 8.3 (1) -- 8.3 (2) -- 8.3 (4) -- 8.3 (5) -- 8.3.1 (4) -- -- DESIGN UNIT ORDERING: -- -- ENT00159(ARCH00159) -- ENT00159_Test_Bench(ARCH00159_Test_Bench) -- -- REVISION HISTORY: -- -- 08-JUL-1987 - initial revision -- -- NOTES: -- -- self-checking -- automatically generated -- use WORK.STANDARD_TYPES.all ; entity ENT00159 is port ( s_st_arr1_vector : inout st_arr1_vector ; s_st_arr2_vector : inout st_arr2_vector ; s_st_arr3_vector : inout st_arr3_vector ) ; subtype chk_sig_type is integer range -1 to 100 ; signal chk_st_arr1_vector : chk_sig_type := -1 ; signal chk_st_arr2_vector : chk_sig_type := -1 ; signal chk_st_arr3_vector : chk_sig_type := -1 ; -- end ENT00159 ; -- architecture ARCH00159 of ENT00159 is begin P1 : process variable correct : boolean ; variable counter : integer := 0 ; variable savtime : time ; -- procedure Proc1 is begin case counter is when 0 => s_st_arr1_vector(lowb) ( st_arr1'Left) <= c_st_arr1_vector_2(highb) ( st_arr1'Right) after 10 ns, c_st_arr1_vector_1(highb) ( st_arr1'Right) after 20 ns ; -- when 1 => correct := s_st_arr1_vector(lowb) ( st_arr1'Left) = c_st_arr1_vector_2(highb) ( st_arr1'Right) and (savtime + 10 ns) = Std.Standard.Now ; -- when 2 => correct := correct and s_st_arr1_vector(lowb) ( st_arr1'Left) = c_st_arr1_vector_1(highb) ( st_arr1'Right) and (savtime + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00159.P1" , "Multi inertial transactions occurred on signal " & "asg with indexed name prefixed by an indexed name on LHS", correct ) ; s_st_arr1_vector(lowb) ( st_arr1'Left) <= c_st_arr1_vector_2(highb) ( st_arr1'Right) after 10 ns, c_st_arr1_vector_1(highb) ( st_arr1'Right) after 20 ns, c_st_arr1_vector_2(highb) ( st_arr1'Right) after 30 ns, c_st_arr1_vector_1(highb) ( st_arr1'Right) after 40 ns ; -- when 3 => correct := s_st_arr1_vector(lowb) ( st_arr1'Left) = c_st_arr1_vector_2(highb) ( st_arr1'Right) and (savtime + 10 ns) = Std.Standard.Now ; s_st_arr1_vector(lowb) ( st_arr1'Left) <= c_st_arr1_vector_1(highb) ( st_arr1'Right) after 5 ns; -- when 4 => correct := correct and s_st_arr1_vector(lowb) ( st_arr1'Left) = c_st_arr1_vector_1(highb) ( st_arr1'Right) and (savtime + 5 ns) = Std.Standard.Now ; test_report ( "ARCH00159" , "One inertial transaction occurred on signal " & "asg with indexed name prefixed by an indexed name on LHS", correct ) ; s_st_arr1_vector(lowb) ( st_arr1'Left) <= transport c_st_arr1_vector_1(highb) ( st_arr1'Right) after 100 ns; -- when 5 => correct := s_st_arr1_vector(lowb) ( st_arr1'Left) = c_st_arr1_vector_1(highb) ( st_arr1'Right) and (savtime + 100 ns) = Std.Standard.Now ; test_report ( "ARCH00159" , "Old transactions were removed on signal " & "asg with indexed name prefixed by an indexed name on LHS", correct ) ; s_st_arr1_vector(lowb) ( st_arr1'Left) <= c_st_arr1_vector_2(highb) ( st_arr1'Right) after 10 ns, c_st_arr1_vector_1(highb) ( st_arr1'Right) after 20 ns, c_st_arr1_vector_2(highb) ( st_arr1'Right) after 30 ns, c_st_arr1_vector_1(highb) ( st_arr1'Right) after 40 ns ; -- when 6 => correct := s_st_arr1_vector(lowb) ( st_arr1'Left) = c_st_arr1_vector_2(highb) ( st_arr1'Right) and (savtime + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00159" , "One inertial transaction occurred on signal " & "asg with indexed name prefixed by an indexed name on LHS", correct ) ; -- The following will mark last transaction above s_st_arr1_vector(lowb) ( st_arr1'Left) <= c_st_arr1_vector_1(highb) ( st_arr1'Right) after 40 ns; -- when 7 => correct := s_st_arr1_vector(lowb) ( st_arr1'Left) = c_st_arr1_vector_1(highb) ( st_arr1'Right) and (savtime + 30 ns) = Std.Standard.Now ; -- when 8 => correct := correct and s_st_arr1_vector(lowb) ( st_arr1'Left) = c_st_arr1_vector_1(highb) ( st_arr1'Right) and (savtime + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00159" , "Inertial semantics check on a signal " & "asg with indexed name prefixed by an indexed name on LHS", correct ) ; -- when others => -- No more transactions should have occurred test_report ( "ARCH00159" , "Inertial semantics check on a signal " & "asg with indexed name prefixed by an indexed name on LHS", false ) ; -- end case ; -- savtime := Std.Standard.Now ; chk_st_arr1_vector <= transport counter after (1 us - savtime) ; counter := counter + 1; -- end Proc1 ; -- begin Proc1 ; wait until (not s_st_arr1_Vector'Quiet) and (savtime /= Std.Standard.Now) ; -- end process P1 ; -- PGEN_CHKP_1 : process ( chk_st_arr1_Vector ) begin if Std.Standard.Now > 0 ns then test_report ( "P1" , "Inertial transactions entirely completed", chk_st_arr1_Vector = 8 ) ; end if ; end process PGEN_CHKP_1 ; -- -- P2 : process variable correct : boolean ; variable counter : integer := 0 ; variable savtime : time ; -- procedure Proc1 is begin case counter is when 0 => s_st_arr2_vector(lowb) ( st_arr2'Left(1),st_arr2'Left(2)) <= c_st_arr2_vector_2(highb) ( st_arr2'Right(1),st_arr2'Right(2)) after 10 ns, c_st_arr2_vector_1(highb) ( st_arr2'Right(1),st_arr2'Right(2)) after 20 ns ; -- when 1 => correct := s_st_arr2_vector(lowb) ( st_arr2'Left(1),st_arr2'Left(2)) = c_st_arr2_vector_2(highb) ( st_arr2'Right(1),st_arr2'Right(2)) and (savtime + 10 ns) = Std.Standard.Now ; -- when 2 => correct := correct and s_st_arr2_vector(lowb) ( st_arr2'Left(1),st_arr2'Left(2)) = c_st_arr2_vector_1(highb) ( st_arr2'Right(1),st_arr2'Right(2)) and (savtime + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00159.P2" , "Multi inertial transactions occurred on signal " & "asg with indexed name prefixed by an indexed name on LHS", correct ) ; s_st_arr2_vector(lowb) ( st_arr2'Left(1),st_arr2'Left(2)) <= c_st_arr2_vector_2(highb) ( st_arr2'Right(1),st_arr2'Right(2)) after 10 ns, c_st_arr2_vector_1(highb) ( st_arr2'Right(1),st_arr2'Right(2)) after 20 ns, c_st_arr2_vector_2(highb) ( st_arr2'Right(1),st_arr2'Right(2)) after 30 ns, c_st_arr2_vector_1(highb) ( st_arr2'Right(1),st_arr2'Right(2)) after 40 ns ; -- when 3 => correct := s_st_arr2_vector(lowb) ( st_arr2'Left(1),st_arr2'Left(2)) = c_st_arr2_vector_2(highb) ( st_arr2'Right(1),st_arr2'Right(2)) and (savtime + 10 ns) = Std.Standard.Now ; s_st_arr2_vector(lowb) ( st_arr2'Left(1),st_arr2'Left(2)) <= c_st_arr2_vector_1(highb) ( st_arr2'Right(1),st_arr2'Right(2)) after 5 ns; -- when 4 => correct := correct and s_st_arr2_vector(lowb) ( st_arr2'Left(1),st_arr2'Left(2)) = c_st_arr2_vector_1(highb) ( st_arr2'Right(1),st_arr2'Right(2)) and (savtime + 5 ns) = Std.Standard.Now ; test_report ( "ARCH00159" , "One inertial transaction occurred on signal " & "asg with indexed name prefixed by an indexed name on LHS", correct ) ; s_st_arr2_vector(lowb) ( st_arr2'Left(1),st_arr2'Left(2)) <= transport c_st_arr2_vector_1(highb) ( st_arr2'Right(1),st_arr2'Right(2)) after 100 ns; -- when 5 => correct := s_st_arr2_vector(lowb) ( st_arr2'Left(1),st_arr2'Left(2)) = c_st_arr2_vector_1(highb) ( st_arr2'Right(1),st_arr2'Right(2)) and (savtime + 100 ns) = Std.Standard.Now ; test_report ( "ARCH00159" , "Old transactions were removed on signal " & "asg with indexed name prefixed by an indexed name on LHS", correct ) ; s_st_arr2_vector(lowb) ( st_arr2'Left(1),st_arr2'Left(2)) <= c_st_arr2_vector_2(highb) ( st_arr2'Right(1),st_arr2'Right(2)) after 10 ns, c_st_arr2_vector_1(highb) ( st_arr2'Right(1),st_arr2'Right(2)) after 20 ns, c_st_arr2_vector_2(highb) ( st_arr2'Right(1),st_arr2'Right(2)) after 30 ns, c_st_arr2_vector_1(highb) ( st_arr2'Right(1),st_arr2'Right(2)) after 40 ns ; -- when 6 => correct := s_st_arr2_vector(lowb) ( st_arr2'Left(1),st_arr2'Left(2)) = c_st_arr2_vector_2(highb) ( st_arr2'Right(1),st_arr2'Right(2)) and (savtime + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00159" , "One inertial transaction occurred on signal " & "asg with indexed name prefixed by an indexed name on LHS", correct ) ; -- The following will mark last transaction above s_st_arr2_vector(lowb) ( st_arr2'Left(1),st_arr2'Left(2)) <= c_st_arr2_vector_1(highb) ( st_arr2'Right(1),st_arr2'Right(2)) after 40 ns; -- when 7 => correct := s_st_arr2_vector(lowb) ( st_arr2'Left(1),st_arr2'Left(2)) = c_st_arr2_vector_1(highb) ( st_arr2'Right(1),st_arr2'Right(2)) and (savtime + 30 ns) = Std.Standard.Now ; -- when 8 => correct := correct and s_st_arr2_vector(lowb) ( st_arr2'Left(1),st_arr2'Left(2)) = c_st_arr2_vector_1(highb) ( st_arr2'Right(1),st_arr2'Right(2)) and (savtime + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00159" , "Inertial semantics check on a signal " & "asg with indexed name prefixed by an indexed name on LHS", correct ) ; -- when others => -- No more transactions should have occurred test_report ( "ARCH00159" , "Inertial semantics check on a signal " & "asg with indexed name prefixed by an indexed name on LHS", false ) ; -- end case ; -- savtime := Std.Standard.Now ; chk_st_arr2_vector <= transport counter after (1 us - savtime) ; counter := counter + 1; -- end Proc1 ; -- begin Proc1 ; wait until (not s_st_arr2_Vector'Quiet) and (savtime /= Std.Standard.Now) ; -- end process P2 ; -- PGEN_CHKP_2 : process ( chk_st_arr2_Vector ) begin if Std.Standard.Now > 0 ns then test_report ( "P2" , "Inertial transactions entirely completed", chk_st_arr2_Vector = 8 ) ; end if ; end process PGEN_CHKP_2 ; -- -- P3 : process variable correct : boolean ; variable counter : integer := 0 ; variable savtime : time ; -- procedure Proc1 is begin case counter is when 0 => s_st_arr3_vector(lowb) ( st_arr3'Left(1),st_arr3'Left(2)) <= c_st_arr3_vector_2(highb) ( st_arr3'Right(1),st_arr3'Right(2)) after 10 ns, c_st_arr3_vector_1(highb) ( st_arr3'Right(1),st_arr3'Right(2)) after 20 ns ; -- when 1 => correct := s_st_arr3_vector(lowb) ( st_arr3'Left(1),st_arr3'Left(2)) = c_st_arr3_vector_2(highb) ( st_arr3'Right(1),st_arr3'Right(2)) and (savtime + 10 ns) = Std.Standard.Now ; -- when 2 => correct := correct and s_st_arr3_vector(lowb) ( st_arr3'Left(1),st_arr3'Left(2)) = c_st_arr3_vector_1(highb) ( st_arr3'Right(1),st_arr3'Right(2)) and (savtime + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00159.P3" , "Multi inertial transactions occurred on signal " & "asg with indexed name prefixed by an indexed name on LHS", correct ) ; s_st_arr3_vector(lowb) ( st_arr3'Left(1),st_arr3'Left(2)) <= c_st_arr3_vector_2(highb) ( st_arr3'Right(1),st_arr3'Right(2)) after 10 ns, c_st_arr3_vector_1(highb) ( st_arr3'Right(1),st_arr3'Right(2)) after 20 ns, c_st_arr3_vector_2(highb) ( st_arr3'Right(1),st_arr3'Right(2)) after 30 ns, c_st_arr3_vector_1(highb) ( st_arr3'Right(1),st_arr3'Right(2)) after 40 ns ; -- when 3 => correct := s_st_arr3_vector(lowb) ( st_arr3'Left(1),st_arr3'Left(2)) = c_st_arr3_vector_2(highb) ( st_arr3'Right(1),st_arr3'Right(2)) and (savtime + 10 ns) = Std.Standard.Now ; s_st_arr3_vector(lowb) ( st_arr3'Left(1),st_arr3'Left(2)) <= c_st_arr3_vector_1(highb) ( st_arr3'Right(1),st_arr3'Right(2)) after 5 ns; -- when 4 => correct := correct and s_st_arr3_vector(lowb) ( st_arr3'Left(1),st_arr3'Left(2)) = c_st_arr3_vector_1(highb) ( st_arr3'Right(1),st_arr3'Right(2)) and (savtime + 5 ns) = Std.Standard.Now ; test_report ( "ARCH00159" , "One inertial transaction occurred on signal " & "asg with indexed name prefixed by an indexed name on LHS", correct ) ; s_st_arr3_vector(lowb) ( st_arr3'Left(1),st_arr3'Left(2)) <= transport c_st_arr3_vector_1(highb) ( st_arr3'Right(1),st_arr3'Right(2)) after 100 ns; -- when 5 => correct := s_st_arr3_vector(lowb) ( st_arr3'Left(1),st_arr3'Left(2)) = c_st_arr3_vector_1(highb) ( st_arr3'Right(1),st_arr3'Right(2)) and (savtime + 100 ns) = Std.Standard.Now ; test_report ( "ARCH00159" , "Old transactions were removed on signal " & "asg with indexed name prefixed by an indexed name on LHS", correct ) ; s_st_arr3_vector(lowb) ( st_arr3'Left(1),st_arr3'Left(2)) <= c_st_arr3_vector_2(highb) ( st_arr3'Right(1),st_arr3'Right(2)) after 10 ns, c_st_arr3_vector_1(highb) ( st_arr3'Right(1),st_arr3'Right(2)) after 20 ns, c_st_arr3_vector_2(highb) ( st_arr3'Right(1),st_arr3'Right(2)) after 30 ns, c_st_arr3_vector_1(highb) ( st_arr3'Right(1),st_arr3'Right(2)) after 40 ns ; -- when 6 => correct := s_st_arr3_vector(lowb) ( st_arr3'Left(1),st_arr3'Left(2)) = c_st_arr3_vector_2(highb) ( st_arr3'Right(1),st_arr3'Right(2)) and (savtime + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00159" , "One inertial transaction occurred on signal " & "asg with indexed name prefixed by an indexed name on LHS", correct ) ; -- The following will mark last transaction above s_st_arr3_vector(lowb) ( st_arr3'Left(1),st_arr3'Left(2)) <= c_st_arr3_vector_1(highb) ( st_arr3'Right(1),st_arr3'Right(2)) after 40 ns; -- when 7 => correct := s_st_arr3_vector(lowb) ( st_arr3'Left(1),st_arr3'Left(2)) = c_st_arr3_vector_1(highb) ( st_arr3'Right(1),st_arr3'Right(2)) and (savtime + 30 ns) = Std.Standard.Now ; -- when 8 => correct := correct and s_st_arr3_vector(lowb) ( st_arr3'Left(1),st_arr3'Left(2)) = c_st_arr3_vector_1(highb) ( st_arr3'Right(1),st_arr3'Right(2)) and (savtime + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00159" , "Inertial semantics check on a signal " & "asg with indexed name prefixed by an indexed name on LHS", correct ) ; -- when others => -- No more transactions should have occurred test_report ( "ARCH00159" , "Inertial semantics check on a signal " & "asg with indexed name prefixed by an indexed name on LHS", false ) ; -- end case ; -- savtime := Std.Standard.Now ; chk_st_arr3_vector <= transport counter after (1 us - savtime) ; counter := counter + 1; -- end Proc1 ; -- begin Proc1 ; wait until (not s_st_arr3_Vector'Quiet) and (savtime /= Std.Standard.Now) ; -- end process P3 ; -- PGEN_CHKP_3 : process ( chk_st_arr3_Vector ) begin if Std.Standard.Now > 0 ns then test_report ( "P3" , "Inertial transactions entirely completed", chk_st_arr3_Vector = 8 ) ; end if ; end process PGEN_CHKP_3 ; -- -- -- end ARCH00159 ; -- use WORK.STANDARD_TYPES.all ; entity ENT00159_Test_Bench is signal s_st_arr1_vector : st_arr1_vector := c_st_arr1_vector_1 ; signal s_st_arr2_vector : st_arr2_vector := c_st_arr2_vector_1 ; signal s_st_arr3_vector : st_arr3_vector := c_st_arr3_vector_1 ; -- end ENT00159_Test_Bench ; -- architecture ARCH00159_Test_Bench of ENT00159_Test_Bench is begin L1: block component UUT port ( s_st_arr1_vector : inout st_arr1_vector ; s_st_arr2_vector : inout st_arr2_vector ; s_st_arr3_vector : inout st_arr3_vector ) ; end component ; -- for CIS1 : UUT use entity WORK.ENT00159 ( ARCH00159 ) ; begin CIS1 : UUT port map ( s_st_arr1_vector , s_st_arr2_vector , s_st_arr3_vector ) ; end block L1 ; end ARCH00159_Test_Bench ;
gpl-3.0
986dd74d572266f9cd5b32ab791e6dbe
0.467716
3.718318
false
false
false
false
takeshineshiro/fpga_fibre_scan
HUCB2P0_150701/driver/pll_intf.vhd
1
8,291
--***************************************************************************** -- @Copyright All rights reserved. -- Module name : adc_intf -- Call by : -- Description : adc_intf,ADS5517 ADC�������ܣ� -- �������ݲ���16λ,����MSB��������. -- I_ADC_trig,�������������뵽�ڲ���λ�Ĵ���, -- ADC��һ����������O_ADC_ready�ź� -- IC : -- Version : A -- Note: : -- Author : Derek Qiu -- Date : 2010.08 -- Update : -- 2010.08.05 updated for PLL in Pulser board, change the name to pll_conf -- Set the sending data to 24 bits. -- The maximal speed for SPI clock is 25MHz, sclk is 16 divide for main clock -- For the sclk, write data are registered on the rising edge, read data are registered on the falling edge -- --***************************************************************************** library IEEE; use IEEE.std_logic_1164.ALL; use IEEE.std_logic_arith.all; use IEEE.std_logic_unsigned.all; entity pll_intf is port ( I_clk : in std_logic; I_reset_n : in std_logic; I_ADC_data : in std_logic_vector(23 downto 0); O_ADC_ready : out std_logic; --���໷��������״̬,�ߵ�ƽ��ʾ���� I_ADC_trig : in std_logic; --���໷���ô����ź�,������ͬʱ����ʱ�����ٱ������clock���� O_FPGA_ADC_d : out std_logic; O_FPGA_ADC_clk : out std_logic; O_FPGA_ADC_en : out std_logic; O_FPGA_ADC_reset : out std_logic ); end pll_intf; architecture rtl of pll_intf is signal S_ADC_data : std_logic_vector(23 downto 0);--���໷�����Ĵ��� signal S_trig_1buf : std_logic; --���������źŻ��� signal S_trig_2buf : std_logic; --���������źŻ��� signal S_trig_3buf : std_logic; --���������źŻ��� signal S_adcclk_cn : std_logic_vector(3 downto 0); --adc����ʱ������,������λ���ɼ����� signal S_adc_cn : std_logic_vector(4 downto 0); --adc���������� signal S_adc_ready : std_logic; --adc��������״̬ signal S_ready_timeout : std_logic_vector(11 downto 0);--æ״̬��ʱ������ signal S_adc_flag : std_logic; --�������� signal S_FPGA_ADC_clk : std_logic; signal S_FPGA_ADC_en : std_logic; signal S_reset_cnt : std_logic_vector(15 downto 0); signal S_FPGA_ADC_reset : std_logic; constant C_DATA_WIDTH : std_logic_vector := "11000"; --The width of pending data is 24 bit begin O_ADC_ready <= S_adc_ready and (not S_FPGA_ADC_reset);--����״̬���� --O_FPGA_ADC_clk <= not S_FPGA_ADC_clk; --Falling edge to register data O_FPGA_ADC_clk <= S_FPGA_ADC_clk; --rising edge to register data O_FPGA_ADC_en <= S_FPGA_ADC_en; O_FPGA_ADC_reset <= S_FPGA_ADC_reset; -- O_5517reset <= '1'; -- O_5517sclk <= '0'; -- O_5517sdata <= '0'; -- O_5517sen <= '1'; -------------------------------------------------------------------------------------------------- --ȡtrig�ź�������,��������������ADC_reg,��ʼ���������� -------------------------------------------------------------------------------------------------- process(I_reset_n,I_clk) begin if(I_reset_n = '0')then S_trig_1buf <= '0'; S_trig_2buf <= '0'; S_adc_flag <= '0'; S_ADC_data <= (others => '0'); S_adcclk_cn <= (others => '0'); S_adc_cn <= (others => '0'); S_FPGA_ADC_en <= '1'; elsif(I_clk'event and I_clk = '1')then S_trig_2buf <= S_trig_1buf; S_trig_1buf <= I_ADC_trig; --trig�ź������ؽ����ݴ���reg if(S_trig_2buf = '0')and (S_trig_1buf = '1')then S_ADC_data <= I_ADC_data; S_adc_flag <= '1'; S_adcclk_cn <= (others => '0'); S_adc_cn <= (others => '0'); S_FPGA_ADC_en <= '0'; --��ʼ���������� elsif(S_adc_flag = '1')then S_adcclk_cn <= S_adcclk_cn + '1'; if( S_adcclk_cn = x"F")then if(S_adc_cn = C_DATA_WIDTH)then --last data is arriving S_adc_flag <= '0'; S_adcclk_cn <= (others => '0'); S_adc_cn <= (others => '0'); S_FPGA_ADC_en <= '1'; else S_adc_cn <= S_adc_cn + '1'; S_ADC_data(23 downto 1) <= S_ADC_data(22 downto 0); end if; end if; end if; end if; end process; -------------------------------------------------------------------------------------------------- --״̬���, -------------------------------------------------------------------------------------------------- process(I_reset_n,I_clk) begin if(I_reset_n = '0')then S_adc_ready <= '1'; S_ready_timeout <= (others => '0'); elsif(I_clk'event and I_clk = '1')then if(S_trig_2buf = '0')and (S_trig_1buf = '1')then--�������� S_adc_ready <= '0'; elsif(S_ready_timeout(11) = '1')or(S_adc_flag = '0')then--æ״̬timeout,��һ������������������������̬ S_adc_ready <= '1'; end if; --æ״̬�������� if(S_adc_ready = '0')then--adc����æ S_ready_timeout <= S_ready_timeout + '1'; else S_ready_timeout <= (others => '0'); end if; end if; end process; -------------------------------------------------------------------------------------------------- --ADC�������� -------------------------------------------------------------------------------------------------- process(I_reset_n,I_clk) begin if(I_reset_n = '0')then O_FPGA_ADC_d <= '0'; S_FPGA_ADC_clk <= '0'; elsif(I_clk'event and I_clk = '1')then if(S_adc_flag = '1')then if(S_adc_cn =C_DATA_WIDTH)then --��le�ź�, last data is arriving O_FPGA_ADC_d <= '0'; S_FPGA_ADC_clk <= '0'; else--���������� O_FPGA_ADC_d <= S_ADC_data(23); S_FPGA_ADC_clk <= S_adcclk_cn(3); --sclk is 16 divide for the main clock end if; else O_FPGA_ADC_d <= '0'; S_FPGA_ADC_clk <= '0'; end if; end if; end process; -------------------------------------------------------------------------------------------------- --Reset -------------------------------------------------------------------------------------------------- process(I_reset_n,I_clk) begin if(I_reset_n = '0')then S_FPGA_ADC_reset <= '1'; S_reset_cnt <= (others => '0'); elsif(I_clk'event and I_clk = '1')then -- S_FPGA_ADC_reset <= '0'; S_reset_cnt <= S_reset_cnt + 1; if(S_reset_cnt = x"FF00")then--adc����æ S_FPGA_ADC_reset <= '1'; elsif((S_reset_cnt = x"FFFE"))then S_FPGA_ADC_reset <= '0'; S_reset_cnt <= S_reset_cnt - 1; elsif(S_trig_2buf = '0')and (S_trig_1buf = '1') and (I_ADC_data = x"FFFFFF")then S_reset_cnt <= x"FEFF"; end if; end if; end process; end rtl;
apache-2.0
6a2601a1ffa22ef952e2fb23def28ae5
0.376769
3.225668
false
false
false
false
grwlf/vsim
vhdl_ct/ct00503.vhd
1
5,752
-- NEED RESULT: ARCH00503: Aggregates in attribute specifications (locally static) passed ------------------------------------------------------------------------------- -- -- Copyright (c) 1989 by Intermetrics, Inc. -- All rights reserved. -- ------------------------------------------------------------------------------- -- -- TEST NAME: -- -- CT00503 -- -- AUTHOR: -- -- A. Wilmot -- -- TEST OBJECTIVES: -- -- 7.3.2.2 (10) -- 7.3.2.2 (11) -- -- DESIGN UNIT ORDERING: -- -- ENT00503(ARCH00503) -- ENT00503_Test_Bench(ARCH00503_Test_Bench) -- -- REVISION HISTORY: -- -- 10-AUG-1987 - initial revision -- -- NOTES: -- -- self-checking -- automatically generated -- use WORK.STANDARD_TYPES.all ; entity ENT00503 is generic ( constant g_a11 : boolean := false ; constant g_a12 : boolean := true ; constant g_a21 : integer := 1 ; constant g_a22 : integer := 5 ; constant g_b11 : integer := 0 ; constant g_b12 : integer := 0 ; constant g_b21 : integer := -5 ; constant g_b22 : integer := -3 ; constant g_c1 : integer := 0 ; constant g_c2 : integer := 4 ; constant g_d1 : integer := 3 ; constant g_d2 : integer := 5 ; constant g_r1 : integer := 1 ) ; constant r1 : integer := 1 ; constant a11 : boolean := false ; constant a12 : boolean := true ; constant a21 : integer := 1 ; constant a22 : integer := 5 ; constant b11 : integer := 0 ; constant b12 : integer := 0 ; constant b21 : integer := -5 ; constant b22 : integer := -3 ; constant c1 : integer := 0 ; constant c2 : integer := 4 ; constant d1 : integer := 3 ; constant d2 : integer := 5 ; -- type rec_arr is array ( integer range <> ) of boolean ; type rec_1 is record f1 : integer range - r1 to r1 ; -- f2 : rec_arr (-r1 to r1) ; f3, f4 : integer ; end record ; -- constant c_rec_arr : rec_arr (-r1 to r1) := -- (true, false, false) ; -- constant c_rec_1_1 : rec_1 := (1, (true, false, false), 1, 0) ; -- constant c_rec_1_2 : rec_1 := (0, (true, false, false), 0, 1) ; constant c_rec_1_1 : rec_1 := (1, 1, 0) ; constant c_rec_1_2 : rec_1 := (0, 0, 1) ; -- type arr_1 is array ( boolean range <> , integer range <> ) of rec_1 ; type time_matrix is array ( integer range <> , integer range <> ) of time ; -- -- subtype arange1 is boolean range a11 to a12 ; subtype arange2 is integer range a21 to a22 ; subtype brange1 is integer range b11 to b12 ; subtype brange2 is integer range b21 to b22 ; subtype crange is integer range c1 to c2 ; subtype drange is integer range d1 to d2 ; -- subtype st_arr_1 is arr_1 ( arange1 , arange2 ) ; subtype st_time_matrix is time_matrix ( brange1 , brange2 ) ; subtype st_bit_vector is bit_vector ( crange ) ; subtype st_string is string ( drange ) ; -- -- end ENT00503 ; -- architecture ARCH00503 of ENT00503 is begin B1 : block -- procedure p1 ( constant p_arr_1 : arr_1 := st_arr_1' ( ( c_rec_1_1, others => c_rec_1_2 ), others => (others => c_rec_1_1) ) ; constant p_time_matrix : time_matrix := st_time_matrix' ( st_time_matrix'right(1) => ( st_time_matrix'right(2) => 10 ns, others => 5 fs), others => (brange2'left => 10 ps, others => 15ms) ) ; constant p_bit_vector : bit_vector := st_bit_vector' ( 0 => '1', 2 => '1', others => '0' ) ; constant p_string : string := st_string' ( 3 => 'a', 4 => 'b', others => '0' ) ; constant p_rec_1 : rec_1 := rec_1' -- ( f2 => (r1 => true, others => false), f3 => 1, others => 0) ( f3 => 1, others => 0) ) is -- variable bool : boolean := true ; -- begin -- bool := bool and p_arr_1(false, 1) = c_rec_1_1 ; for i in 2 to 5 loop bool := bool and p_arr_1(false, i) = c_rec_1_2 ; end loop ; for i in 1 to 5 loop bool := bool and p_arr_1(true, i) = c_rec_1_1 ; end loop ; -- bool := bool and p_time_matrix(0, -3) = 10 ns ; for i in integer'(-5) to -4 loop bool := bool and p_time_matrix(0, i) = 5 fs ; end loop ; -- bool := bool and p_bit_vector = B"10100" ; -- bool := bool and p_string = "ab0" ; -- bool := bool and p_rec_1.f1 = 0 and p_rec_1.f4 = 0 and p_rec_1.f3 = 1 ; -- bool := bool and p_rec_1.f2(1) = true -- and p_rec_1.f2(0) = false and -- p_rec_1.f2(-1) = false ; -- test_report ( "ARCH00503" , "Aggregates in attribute specifications" & " (locally static)" , bool ) ; end p1 ; begin process begin p1 (open, open, open, open, open) ; wait ; end process ; end block B1 ; end ARCH00503 ; -- entity ENT00503_Test_Bench is end ENT00503_Test_Bench ; -- architecture ARCH00503_Test_Bench of ENT00503_Test_Bench is begin L1: block component UUT end component ; -- for CIS1 : UUT use entity WORK.ENT00503 ( ARCH00503 ) ; begin CIS1 : UUT ; end block L1 ; end ARCH00503_Test_Bench ;
gpl-3.0
ee5648a6f554c1ab19a6c5aceff9a956
0.475139
3.324855
false
true
false
false
grwlf/vsim
vhdl_ct/ct00521.vhd
1
12,609
------------------------------------------------------------------------------- -- -- Copyright (c) 1989 by Intermetrics, Inc. -- All rights reserved. -- ------------------------------------------------------------------------------- -- -- TEST NAME: -- -- CT00521 -- -- AUTHOR: -- -- A. Wilmot -- -- TEST OBJECTIVES: -- -- 7.3.2.2 (12) -- 7.3.2.2 (13) -- 7.3.2.2 (16) -- -- DESIGN UNIT ORDERING: -- -- PKG00521 -- ENT00521(ARCH00521) -- ENT00521_Test_Bench(ARCH00521_Test_Bench) -- -- REVISION HISTORY: -- -- 12-AUG-1987 - initial revision -- 11-APR-1988 - JW: Test was really bogus. -- -- NOTES: -- -- self-checking -- package PKG00521 is type rec_1 is record f1 : integer ; f2 : boolean ; end record ; subtype brange is integer range 4 downto 0 ; subtype crange is integer range 1 downto 1 ; subtype drange is integer range 0 to 2 ; subtype rev_integer is integer range integer'right downto integer'left ; type arr_1 is array ( boolean range <> , rev_integer range <> ) of rec_1 ; type time_matrix is array ( integer range <> , rev_integer range <> ) of time ; type bit_matrix is array ( rev_integer range <> , integer range <> ) of bit ; type bit_arr_vec is array ( rev_integer range <> ) of bit_vector ( 0 to 2 ) ; end PKG00521 ; use WORK.STANDARD_TYPES.all ; use WORK.PKG00521.all ; entity ENT00521 is generic ( g_arr_1 : arr_1 ; g_time_matrix : time_matrix ; g_bit_matrix : bit_matrix ; g_bitarr_vec : bit_arr_vec ; g_string : string ; g_bit_vector : bit_vector ) ; -- JW: Added default values to ports. port ( p_arr_1 : arr_1 := ( true => (1 => (1, true)), false => (1 => (0, false)) ) ; p_time_matrix : time_matrix := ( 0 => (0 => 15 ns, 1=> 15ms, 2 => 15 ps, 3 => 15 fs, 4 => 9 ns), 2 => (4 | 3 => 10 ns, 2 => 10 ps, 1 => 10 fs, 0 => 6 ns), 1 => (3 => 5 ns, 2 | 1 => 5ms, 0 => 5 fs, 4 => 3 ns) ) ; p_bit_matrix : bit_matrix := ( 4 downto 2 => B"000", 1=> B"010", 0 => B"111" ) ; p_bitarr_vec : bit_arr_vec := ( 4 downto 2 => B"000", 1=> B"010", 0 => B"111" ) ; p_string : string := ( 2 => 'a', 6 => 'c', 1 | 3 to 5 => 'b' ) ; p_bit_vector : bit_vector := ( (2 downto 0 => '1') ) ) ; procedure p1 ( p_arr_1 : arr_1 ; p_time_matrix : time_matrix ; p_bit_matrix : bit_matrix ; p_bitarr_vec : bit_arr_vec ; p_string : string ; p_bit_vector : bit_vector ) is variable correct : boolean := true ; subtype rg_arr_11 is boolean range g_arr_1'range(1) ; subtype rg_arr_12 is integer range g_arr_1'range(2) ; subtype rg_time_matrix1 is integer range g_time_matrix'range(1) ; subtype rg_time_matrix2 is integer range g_time_matrix'range(2) ; subtype rg_bit_matrix1 is integer range g_bit_matrix'range(1) ; subtype rg_bit_matrix2 is integer range g_bit_matrix'range(2) ; subtype rg_bitarr_vec1 is integer range g_bitarr_vec'range(1) ; subtype rg_string is integer range g_string'range ; subtype rg_bit_vector is integer range g_bit_vector'range ; subtype rp_arr_11 is boolean range p_arr_1'range(1) ; subtype rp_arr_12 is integer range p_arr_1'range(2) ; subtype rp_time_matrix1 is integer range p_time_matrix'range(1) ; subtype rp_time_matrix2 is integer range p_time_matrix'range(2) ; subtype rp_bit_matrix1 is integer range p_bit_matrix'range(1) ; subtype rp_bit_matrix2 is integer range p_bit_matrix'range(2) ; subtype rp_bitarr_vec1 is integer range p_bitarr_vec'range(1) ; subtype rp_string is integer range p_string'range ; subtype rp_bit_vector is integer range p_bit_vector'range ; begin correct := correct and rg_arr_11'left <= rg_arr_11'right ; correct := correct and rg_arr_11'left = false and rg_arr_11'right = true ; correct := correct and rg_arr_12'right <= rg_arr_12'left ; correct := correct and rg_arr_12'left = 1 and rg_arr_12'right = 1 ; correct := correct and rg_time_matrix1'left <= rg_time_matrix1'right ; correct := correct and rg_time_matrix1'left = 0 and rg_time_matrix1'right = 2 ; correct := correct and rg_time_matrix2'right <= rg_time_matrix2'left ; correct := correct and rg_time_matrix2'left = 4 and rg_time_matrix2'right = 0 ; correct := correct and rg_bit_matrix1'right <= rg_bit_matrix1'left ; correct := correct and rg_bit_matrix1'left = 4 and rg_bit_matrix1'right = 0 ; correct := correct and rg_bit_matrix2'left <= rg_bit_matrix2'right ; correct := correct and rg_bit_matrix2'left = integer'left and rg_bit_matrix2'right = integer'left + 2 ; correct := correct and rg_bitarr_vec1'right <= rg_bitarr_vec1'left ; correct := correct and rg_bitarr_vec1'left = 4 and rg_bitarr_vec1'right = 0 ; correct := correct and rg_string'left <= rg_string'right ; correct := correct and rg_string'left = 1 and rg_string'right = 6 ; correct := correct and rg_bit_vector'left <= rg_bit_vector'right ; correct := correct and rg_bit_vector'left = 0 and rg_bit_vector'right = 2 ; correct := correct and rp_arr_11'left <= rp_arr_11'right ; correct := correct and rp_arr_11'left = false and rp_arr_11'right = true ; correct := correct and rp_arr_12'right <= rp_arr_12'left ; correct := correct and rp_arr_12'left = 1 and rp_arr_12'right = 1 ; correct := correct and rp_time_matrix1'left <= rp_time_matrix1'right ; correct := correct and rp_time_matrix1'left = 0 and rp_time_matrix1'right = 2 ; correct := correct and rp_time_matrix2'right <= rp_time_matrix2'left ; correct := correct and rp_time_matrix2'left = 4 and rp_time_matrix2'right = 0 ; correct := correct and rp_bit_matrix1'right <= rp_bit_matrix1'left ; correct := correct and rp_bit_matrix1'left = 4 and rp_bit_matrix1'right = 0 ; correct := correct and rp_bit_matrix2'left <= rp_bit_matrix2'right ; correct := correct and rp_bit_matrix2'left = integer'left and rp_bit_matrix2'right = integer'left + 2 ; correct := correct and rp_bitarr_vec1'right <= rp_bitarr_vec1'left ; correct := correct and rp_bitarr_vec1'left = 4 and rp_bitarr_vec1'right = 0 ; correct := correct and rp_string'left <= rp_string'right ; correct := correct and rp_string'left = 1 and rp_string'right = 6 ; correct := correct and rp_bit_vector'left <= rp_bit_vector'right ; correct := correct and rp_bit_vector'left = 0 and rp_bit_vector'right = 2 ; test_report ( "ARCH00521" , "Named aggregates associated with unconstrained" & " generics and parameters" , correct ) ; end p1 ; end ENT00521 ; architecture ARCH00521 of ENT00521 is begin process variable correct : boolean := true ; subtype rp_arr_11 is boolean range p_arr_1'range(1) ; subtype rp_arr_12 is integer range p_arr_1'range(2) ; subtype rp_time_matrix1 is integer range p_time_matrix'range(1) ; subtype rp_time_matrix2 is integer range p_time_matrix'range(2) ; subtype rp_bit_matrix1 is integer range p_bit_matrix'range(1) ; subtype rp_bit_matrix2 is integer range p_bit_matrix'range(2) ; subtype rp_bitarr_vec1 is integer range p_bitarr_vec'range(1) ; subtype rp_string is integer range p_string'range ; subtype rp_bit_vector is integer range p_bit_vector'range ; begin p1 ( ( true => (1 => (1, true)), false => (1 => (0, false)) ) , ( 0 => (0 => 15 ns, 1=> 15ms, 2 => 15 ps, 3 => 15 fs, 4 => 9 ns), 2 => (4 | 3 => 10 ns, 2 => 10 ps, 1 => 10 fs, 0 => 6 ns), 1 => (3 => 5 ns, 2 | 1 => 5ms, 0 => 5 fs, 4 => 3 ns) ) , ( 4 downto 2 => B"000", 1=> B"010", 0 => B"111" ) , ( 4 downto 2 => B"000", 1=> B"010", 0 => B"111" ) , ( 2 => 'a', 6 => 'c', 1 | 3 to 5 => 'b' ) , ( (2 downto 0 => '1') ) ) ; correct := correct and rp_arr_11'left <= rp_arr_11'right ; correct := correct and rp_arr_11'left = false and rp_arr_11'right = true ; correct := correct and rp_arr_12'right <= rp_arr_12'left ; correct := correct and rp_arr_12'left = 1 and rp_arr_12'right = 1 ; correct := correct and rp_time_matrix1'left <= rp_time_matrix1'right ; correct := correct and rp_time_matrix1'left = 0 and rp_time_matrix1'right = 2 ; correct := correct and rp_time_matrix2'right <= rp_time_matrix2'left ; correct := correct and rp_time_matrix2'left = 4 and rp_time_matrix2'right = 0 ; correct := correct and rp_bit_matrix1'right <= rp_bit_matrix1'left ; correct := correct and rp_bit_matrix1'left = 4 and rp_bit_matrix1'right = 0 ; correct := correct and rp_bit_matrix2'left <= rp_bit_matrix2'right ; correct := correct and rp_bit_matrix2'left = integer'left and rp_bit_matrix2'right = integer'left + 2 ; correct := correct and rp_bitarr_vec1'right <= rp_bitarr_vec1'left ; correct := correct and rp_bitarr_vec1'left = 4 and rp_bitarr_vec1'right = 0 ; correct := correct and rp_string'left <= rp_string'right ; correct := correct and rp_string'left = 1 and rp_string'right = 6 ; correct := correct and rp_bit_vector'left <= rp_bit_vector'right ; correct := correct and rp_bit_vector'left = 0 and rp_bit_vector'right = 2 ; test_report ( "ARCH00521" , "Named aggregates associated with unconstrained" & " signals" , correct ) ; wait ; end process ; end ARCH00521 ; use WORK.PKG00521.all ; entity ENT00521_Test_Bench is end ENT00521_Test_Bench ; architecture ARCH00521_Test_Bench of ENT00521_Test_Bench is begin L1: block component UUT -- JW: Added generic port decls. generic ( g_arr_1 : arr_1 ; g_time_matrix : time_matrix ; g_bit_matrix : bit_matrix ; g_bitarr_vec : bit_arr_vec ; g_string : string ; g_bit_vector : bit_vector ) ; end component ; for CIS1 : UUT use entity WORK.ENT00521 ( ARCH00521 ) ; begin CIS1 : UUT generic map ( ( true => (1 => (1, true)), false => (1 => (0, false)) ) , ( 0 => (0 => 15 ns, 1=> 15ms, 2 => 15 ps, 3 => 15 fs, 4 => 9 ns), 2 => (4 | 3 => 10 ns, 2 => 10 ps, 1 => 10 fs, 0 => 6 ns), 1 => (3 => 5 ns, 2 | 1 => 5ms, 0 => 5 fs, 4 => 3 ns) ) , ( 4 downto 2 => B"000", 1=> B"010", 0 => B"111" ) , ( 4 downto 2 => B"000", 1=> B"010", 0 => B"111" ) , ( 2 => 'a', 6 => 'c', 1 | 3 to 5 => 'b' ) , ( (2 downto 0 => '1') ) ) ; -- JW: Removed port map which was attempting to associate literals with ports. end block L1 ; end ARCH00521_Test_Bench ;
gpl-3.0
2d050a53ba535c1c4a511dc30e01b0ef
0.501229
3.651607
false
false
false
false
grwlf/vsim
vhdl/STD/standard.vhd
1
17,409
-- The sven STANDARD package. -- This design unit contains some special tokens, which are only -- recognized by the analyzer when it is in special "bootstrap" mode. package STANDARD is -- predefined enumeration types: type BOOLEAN is (FALSE, TRUE); type INTEGER is range 0 to 2147483647; type REAL is range 0.0 to 1.79769e+308; function "-" ( a, b: integer ) return integer; function "+" ( a, b: integer ) return integer; function "*" ( a, b: integer ) return integer; function "/" ( a, b: integer ) return integer; function "mod" ( a, b: integer ) return integer; function "rem" (anonymous, anonymous2: integer) return integer; function "**" ( a, b: integer ) return integer; function "=" (anonymous, anonymous2: real) return BOOLEAN; function "/=" (anonymous, anonymous2: real) return BOOLEAN; function "<" (anonymous, anonymous2: real) return BOOLEAN; function "<=" (anonymous, anonymous2: real) return BOOLEAN; function ">" (anonymous, anonymous2: real) return BOOLEAN; function ">=" (anonymous, anonymous2: real) return BOOLEAN; function "+" (anonymous: real) return real; function "-" (anonymous: real) return real; function "abs" (anonymous: real) return real; function "+" (anonymous, anonymous2: real) return real; function "-" (anonymous, anonymous2: real) return real; function "*" (anonymous, anonymous2: real) return real; function "/" (anonymous, anonymous2: real) return real; function "*" (anonymous: real; anonymous: integer) return real; function "*" (anonymous: integer; anonymous: real) return real; function "/" (anonymous: real; anonymous: integer) return real; type INTEGER is range -2147483647-1 to 2147483647; -- -2147483648 doesn't work, seems that it parsed as unary minus 2147483648 type REAL is range -1.79769e+308 to 1.79769e+308; function "and" (anonymous1, anonymous2: BOOLEAN) return BOOLEAN; function "or" (anonymous1, anonymous2: BOOLEAN) return BOOLEAN; function "nand" (anonymous1, anonymous2: BOOLEAN) return BOOLEAN; function "nor" (anonymous1, anonymous2: BOOLEAN) return BOOLEAN; function "xor" (anonymous1, anonymous2: BOOLEAN) return BOOLEAN; function "xnor" (anonymous1, anonymous2: BOOLEAN) return BOOLEAN; function "not" (anonymous1: BOOLEAN) return BOOLEAN; function "=" (anonymous1, anonymous2: BOOLEAN) return BOOLEAN; function "/=" (anonymous1, anonymous2: BOOLEAN) return BOOLEAN; function "<" (anonymous1, anonymous2: BOOLEAN) return BOOLEAN; function "<=" (anonymous1, anonymous2: BOOLEAN) return BOOLEAN; function ">" (anonymous1, anonymous2: BOOLEAN) return BOOLEAN; function ">=" (anonymous1, anonymous2: BOOLEAN) return BOOLEAN; type BIT is ('0', '1'); --The predefined operators for this type are as follows: function "and" (anonymous, anonymous: BIT) return BIT; function "or" (anonymous, anonymous: BIT) return BIT; function "nand" (anonymous, anonymous: BIT) return BIT; function "nor" (anonymous, anonymous: BIT) return BIT; function "xor" (anonymous, anonymous: BIT) return BIT; function "xnor" (anonymous, anonymous: BIT) return BIT; function "not" (anonymous: BIT) return BIT; function "=" (anonymous, anonymous: BIT) return BOOLEAN; function "/=" (anonymous, anonymous: BIT) return BOOLEAN; function "<" (anonymous, anonymous: BIT) return BOOLEAN; function "<=" (anonymous, anonymous: BIT) return BOOLEAN; function ">" (anonymous, anonymous: BIT) return BOOLEAN; function ">=" (anonymous, anonymous: BIT) return BOOLEAN; type CHARACTER is ( NUL, SOH, STX, ETX, EOT, ENQ, ACK, BEL, BS, HT, LF, VT, FF, CR, SO, SI, DLE, DC1, DC2, DC3, DC4, NAK, SYN, ETB, CAN, EM, SUB, ESC, FSP, GSP, RSP, USP, ' ', '!', '"', '#', '$', '%', '&', ''', '(', ')', '*', '+', ',', '-', '.', '/', '0', '1', '2', '3', '4', '5', '6', '7', '8', '9', ':', ';', '<', '=', '>', '?', '@', 'A', 'B', 'C', 'D', 'E', 'F', 'G', 'H', 'I', 'J', 'K', 'L', 'M', 'N', 'O', 'P', 'Q', 'R', 'S', 'T', 'U', 'V', 'W', 'X', 'Y', 'Z', '[', '\', ']', '^', '_', '`', 'a', 'b', 'c', 'd', 'e', 'f', 'g', 'h', 'i', 'j', 'k', 'l', 'm', 'n', 'o', 'p', 'q', 'r', 's', 't', 'u', 'v', 'w', 'x', 'y', 'z', '{', '|', '}', '~', DEL, C128, C129, C130, C131, C132, C133, C134, C135, C136, C137, C138, C139, C140, C141, C142, C143, C144, C145, C146, C147, C148, C149, C150, C151, C152, C153, C154, C155, C156, C157, C158, C159 --, -- ' ', '¡', '¢', '£', '¤', '¥', '¦', '§', -- '¨', '©', 'ª', '«', '¬', '­', '®', '¯', -- '°', '±', '²', '³', '´', 'µ', '¶', '·', -- '¸', '¹', 'º', '»', '¼', '½', '¾', '¿', -- 'À', 'Á', 'Â', 'Ã', 'Ä', 'Å', 'Æ', 'Ç', -- 'È', 'É', 'Ê', 'Ë', 'Ì', 'Í', 'Î', 'Ï', -- 'Ð', 'Ñ', 'Ò', 'Ó', 'Ô', 'Õ', 'Ö', '×', -- 'Ø', 'Ù', 'Ú', 'Û', 'Ü', 'Ý', 'Þ', 'ß', -- 'à', 'á', 'â', 'ã', 'ä', 'å', 'æ', 'ç', -- 'è', 'é', 'ê', 'ë', 'ì', 'í', 'î', 'ï', -- 'ð', 'ñ', 'ò', 'ó', 'ô', 'õ', 'ö', '÷', -- 'ø', 'ù', 'ú', 'û', 'ü', 'ý', 'þ', 'ÿ' ); type SEVERITY_LEVEL is (NOTE, WARNING, ERROR, FAILURE); -- predefined numeric types: -- Do INTEGER first to aid implicit declarations of "**". -- type INTEGER is range -2147483647 to 2147483647; -- type $UNIVERSAL_INTEGER is range $- to $+; -- type $real is range $-. to $+.; function "*" (LEFT: real; RIGHT: INTEGER) return real; function "*" (LEFT: INTEGER; RIGHT: REAL) return REAL; function "/" (LEFT: REAL; RIGHT: INTEGER) return REAL; -- type REAL is range $-. to $+.; -- predefined type TIME: type TIME is range -1000000 to +100000000 units fs; -- femtosecond ps = 1000 fs; -- picosecond ns = 1000 ps; -- nanosecond us = 1000 ns; -- microsecond ms = 1000 us; -- millisecond sec = 1000 ms; -- second min = 60 sec; -- minute hr = 60 min; -- hour; end units; function "=" (anonymous1, anonymous2: TIME) return BOOLEAN; function "/=" (anonymous1, anonymous2: TIME) return BOOLEAN; function "<" (anonymous1, anonymous2: TIME) return BOOLEAN; function "<=" (anonymous1, anonymous2: TIME) return BOOLEAN; function ">" (anonymous1, anonymous2: TIME) return BOOLEAN; function ">=" (anonymous1, anonymous2: TIME) return BOOLEAN; function "+" (anonymous1: TIME) return TIME; function "-" (anonymous1: TIME) return TIME; function "abs" (anonymous1: TIME) return TIME; function "+" (anonymous1, anonymous2: TIME) return TIME; function "-" (anonymous1, anonymous2: TIME) return TIME; function "*" (anonymous1: TIME; anonymous2: INTEGER) return TIME; function "*" (anonymous1: TIME; anonymous2: REAL) return TIME; function "*" (anonymous1: INTEGER; anonymous2: TIME) return TIME; function "*" (anonymous1: REAL; anonymous2: TIME) return TIME; function "/" (anonymous1: TIME; anonymous2: INTEGER) return TIME; function "/" (anonymous1: TIME; anonymous2: REAL) return TIME; function "/" (anonymous1, anonymous2: TIME) return INTEGER; function "**" (anonymous: real; anonymous: INTEGER) return real; -- subtype used internally for checking time expressions for non-negativness: -- subtype $NATURAL_TIME is TIME range 0 sec to TIME'HIGH; subtype DELAY_LENGTH is TIME range 0 fs to TIME'HIGH; -- function that returns the current simulation time: impure function NOW return TIME; -- predefined numeric subtypes: subtype NATURAL is INTEGER range 0 to INTEGER'HIGH; subtype POSITIVE is INTEGER range 1 to INTEGER'HIGH; -- predefined array types: type STRING is array (POSITIVE range <>) of CHARACTER; function "&" ( a, b: STRING ) return STRING; type BIT_VECTOR is array (NATURAL range <>) of BIT; --type FILE_OPEN_KIND is (READ_OPEN, WRITE_OPEN, APPEND_OPEN); type FILE_OPEN_KIND is (READ_MODE, WRITE_MODE, APPEND_MODE); type FILE_OPEN_STATUS is (OPEN_OK, STATUS_ERROR, NAME_ERROR, MODE_ERROR); attribute FOREIGN: STRING; -- -- The rest of this package is SVEN specific stuff required to make -- this implementation go. -- Note that all things are declared use leading $ characters, so we don't -- trample the user's name space. -- -- attribute $BUILTIN: BOOLEAN; -- procedure $RTINDEX (I: NATURAL; FIRSTARG: INTEGER; PASSAP,SAVEFREGS: BOOLEAN); -- procedure $RTSYMBOL (S: STRING; FIRSTARG: INTEGER; PASSAP,SAVEFREGS: BOOLEAN); -- attribute $BUILTIN of all: function is TRUE; -- attribute $BUILTIN of all: procedure is TRUE; function "and" (l, r: BIT_VECTOR) return BIT_VECTOR; -- function "and" (anonymous, anonymous2: BIT_VECTOR) return BIT_VECTOR; function "or" (l, r: BIT_VECTOR) return BIT_VECTOR; function "nand" (anonymous, anonymous2: BIT_VECTOR) return BIT_VECTOR; function "nor" (anonymous, anonymous2: BIT_VECTOR) return BIT_VECTOR; function "xor" (l, r: BIT_VECTOR) return BIT_VECTOR; function "xnor" (anonymous, anonymous2: BIT_VECTOR) return BIT_VECTOR; function "not" (l: BIT_VECTOR) return BIT_VECTOR; -- function "not" (anonymous: BIT_VECTOR) return BIT_VECTOR; function "sll" (ARG: BIT_VECTOR; COUNT: INTEGER) return BIT_VECTOR; function "srl" (ARG: BIT_VECTOR; COUNT: INTEGER) return BIT_VECTOR; -- function "sll" (anonymous: BIT_VECTOR; anonymous2: INTEGER) -- return BIT_VECTOR; -- function "srl" (anonymous: BIT_VECTOR; anonymous2: INTEGER) -- return BIT_VECTOR; function "sla" (anonymous: BIT_VECTOR; anonymous2: INTEGER) return BIT_VECTOR; function "sra" (anonymous: BIT_VECTOR; anonymous2: INTEGER) return BIT_VECTOR; function "rol" (ARG: BIT_VECTOR; COUNT: INTEGER) return BIT_VECTOR; function "ror" (ARG: BIT_VECTOR; COUNT: INTEGER) return BIT_VECTOR; -- function "rol" (anonymous: BIT_VECTOR; anonymous2: INTEGER) -- return BIT_VECTOR; -- function "ror" (anonymous: BIT_VECTOR; anonymous2: INTEGER) -- return BIT_VECTOR; function "=" (anonymous, anonymous2: BIT_VECTOR) return BOOLEAN; function "/=" (anonymous, anonymous2: BIT_VECTOR) return BOOLEAN; function "<" (anonymous, anonymous2: BIT_VECTOR) return BOOLEAN; function "<=" (anonymous, anonymous2: BIT_VECTOR) return BOOLEAN; function ">" (anonymous, anonymous2: BIT_VECTOR) return BOOLEAN; function ">=" (anonymous, anonymous2: BIT_VECTOR) return BOOLEAN; function "&" (anonymous: BIT_VECTOR; anonymous2: BIT_VECTOR) return BIT_VECTOR; function "&" (anonymous: BIT_VECTOR; anonymous2: BIT) return BIT_VECTOR; function "&" (anonymous: BIT; anonymous2: BIT_VECTOR) return BIT_VECTOR; function "&" (anonymous: BIT; anonymous2: BIT) return BIT_VECTOR; end STANDARD; PACKAGE BODY STANDARD IS -- logic and shift functions on bit_vector are not builtin FUNCTION "and" ( l,r : BIT_VECTOR ) RETURN BIT_VECTOR IS ALIAS lv : BIT_VECTOR ( 1 TO l'LENGTH ) IS l; ALIAS rv : BIT_VECTOR ( 1 TO r'LENGTH ) IS r; VARIABLE result : BIT_VECTOR ( 1 TO l'LENGTH ); BEGIN IF ( l'LENGTH /= r'LENGTH ) THEN ASSERT FALSE -- REPORT "arguments of overloaded 'and' operator are not of the same length" SEVERITY FAILURE; ELSE FOR i IN result'RANGE LOOP result(i) := lv(i) and rv(i); END LOOP; END IF; RETURN result; END "and"; FUNCTION "or" ( l,r : BIT_VECTOR ) RETURN BIT_VECTOR IS ALIAS lv : BIT_VECTOR ( 1 TO l'LENGTH ) IS l; ALIAS rv : BIT_VECTOR ( 1 TO r'LENGTH ) IS r; VARIABLE result : BIT_VECTOR ( 1 TO l'LENGTH ); BEGIN IF ( l'LENGTH /= r'LENGTH ) THEN ASSERT FALSE -- REPORT "arguments of overloaded 'or' operator are not of the same length" SEVERITY FAILURE; ELSE FOR i IN result'RANGE LOOP result(i) := lv(i) or rv(i); END LOOP; END IF; RETURN result; END "or"; FUNCTION "xor" ( l,r : BIT_VECTOR ) RETURN BIT_VECTOR IS ALIAS lv : BIT_VECTOR ( 1 TO l'LENGTH ) IS l; ALIAS rv : BIT_VECTOR ( 1 TO r'LENGTH ) IS r; VARIABLE result : BIT_VECTOR ( 1 TO l'LENGTH ); BEGIN IF ( l'LENGTH /= r'LENGTH ) THEN ASSERT FALSE -- REPORT "arguments of overloaded 'xor' operator are not of the same length" SEVERITY FAILURE; ELSE FOR i IN result'RANGE LOOP result(i) := lv(i) xor rv(i); END LOOP; END IF; RETURN result; END "xor"; FUNCTION "not" ( l : BIT_VECTOR ) RETURN BIT_VECTOR IS -- strange, but translator raises NPE if we rename 'l' to -- something else ALIAS lv : BIT_VECTOR ( 1 TO l'LENGTH ) IS l; VARIABLE result : BIT_VECTOR ( 1 TO l'LENGTH ) := (OTHERS => '0'); BEGIN FOR i IN result'RANGE LOOP result(i) := not lv(i); END LOOP; RETURN result; END; function XSLL (ARG: BIT_VECTOR; COUNT: NATURAL) return BIT_VECTOR is constant ARG_L: INTEGER := ARG'LENGTH-1; alias XARG: BIT_VECTOR(ARG_L downto 0) is ARG; variable RESULT: BIT_VECTOR(ARG_L downto 0) := (others => '0'); begin if COUNT <= ARG_L then RESULT(ARG_L downto COUNT) := XARG(ARG_L-COUNT downto 0); end if; return RESULT; end XSLL; function XSRL (ARG: BIT_VECTOR; COUNT: NATURAL) return BIT_VECTOR is constant ARG_L: INTEGER := ARG'LENGTH-1; alias XARG: BIT_VECTOR(ARG_L downto 0) is ARG; variable RESULT: BIT_VECTOR(ARG_L downto 0) := (others => '0'); begin if COUNT <= ARG_L then RESULT(ARG_L-COUNT downto 0) := XARG(ARG_L downto COUNT); end if; return RESULT; end XSRL; function XSRA (ARG: BIT_VECTOR; COUNT: NATURAL) return BIT_VECTOR is constant ARG_L: INTEGER := ARG'LENGTH-1; alias XARG: BIT_VECTOR(ARG_L downto 0) is ARG; variable RESULT: BIT_VECTOR(ARG_L downto 0); variable XCOUNT: NATURAL := COUNT; begin if ((ARG'LENGTH <= 1) or (XCOUNT = 0)) then return ARG; else if (XCOUNT > ARG_L) then XCOUNT := ARG_L; end if; RESULT(ARG_L-XCOUNT downto 0) := XARG(ARG_L downto XCOUNT); RESULT(ARG_L downto (ARG_L - XCOUNT + 1)) := (others => XARG(ARG_L)); end if; return RESULT; end XSRA; function XROL (ARG: BIT_VECTOR; COUNT: NATURAL) return BIT_VECTOR is constant ARG_L: INTEGER := ARG'LENGTH-1; alias XARG: BIT_VECTOR(ARG_L downto 0) is ARG; variable RESULT: BIT_VECTOR(ARG_L downto 0) := XARG; variable COUNTM: INTEGER; begin COUNTM := COUNT mod (ARG_L + 1); if COUNTM /= 0 then RESULT(ARG_L downto COUNTM) := XARG(ARG_L-COUNTM downto 0); RESULT(COUNTM-1 downto 0) := XARG(ARG_L downto ARG_L-COUNTM+1); end if; return RESULT; end XROL; function XROR (ARG: BIT_VECTOR; COUNT: NATURAL) return BIT_VECTOR is constant ARG_L: INTEGER := ARG'LENGTH-1; alias XARG: BIT_VECTOR(ARG_L downto 0) is ARG; variable RESULT: BIT_VECTOR(ARG_L downto 0) := XARG; variable COUNTM: INTEGER; begin COUNTM := COUNT mod (ARG_L + 1); if COUNTM /= 0 then RESULT(ARG_L-COUNTM downto 0) := XARG(ARG_L downto COUNTM); RESULT(ARG_L downto ARG_L-COUNTM+1) := XARG(COUNTM-1 downto 0); end if; return RESULT; end XROR; constant NAU: BIT_VECTOR(0 downto 1) := (others => '0'); -- Id: S.1 function SHIFT_LEFT (ARG: BIT_VECTOR; COUNT: NATURAL) return BIT_VECTOR is begin if (ARG'LENGTH < 1) then return NAU; end if; return (XSLL((ARG), COUNT)); end SHIFT_LEFT; -- Id: S.2 function SHIFT_RIGHT (ARG: BIT_VECTOR; COUNT: NATURAL) return BIT_VECTOR is begin if (ARG'LENGTH < 1) then return NAU; end if; return (XSRL((ARG), COUNT)); end SHIFT_RIGHT; --============================================================================ -- Id: S.5 function ROTATE_LEFT (ARG: BIT_VECTOR; COUNT: NATURAL) return BIT_VECTOR is begin if (ARG'LENGTH < 1) then return NAU; end if; return (XROL((ARG), COUNT)); end ROTATE_LEFT; -- Id: S.6 function ROTATE_RIGHT (ARG: BIT_VECTOR; COUNT: NATURAL) return BIT_VECTOR is begin if (ARG'LENGTH < 1) then return NAU; end if; return (XROR((ARG), COUNT)); end ROTATE_RIGHT; --============================================================================ function "sll" (ARG: BIT_VECTOR; COUNT: INTEGER) return BIT_VECTOR is begin if (COUNT >= 0) then return SHIFT_LEFT(ARG, COUNT); else return SHIFT_RIGHT(ARG, -COUNT); end if; end "sll"; function "srl" (ARG: BIT_VECTOR; COUNT: INTEGER) return BIT_VECTOR is begin if (COUNT >= 0) then return SHIFT_RIGHT(ARG, COUNT); else return SHIFT_LEFT(ARG, -COUNT); end if; end "srl"; function "rol" (ARG: BIT_VECTOR; COUNT: INTEGER) return BIT_VECTOR is begin if (COUNT >= 0) then return ROTATE_LEFT(ARG, COUNT); else return ROTATE_RIGHT(ARG, -COUNT); end if; end "rol"; function "ror" (ARG: BIT_VECTOR; COUNT: INTEGER) return BIT_VECTOR is begin if (COUNT >= 0) then return ROTATE_RIGHT(ARG, COUNT); else return ROTATE_LEFT(ARG, -COUNT); end if; end "ror"; end STANDARD;
gpl-3.0
6bb52d06e519bc7811386209d2f4604e
0.603309
3.356922
false
false
false
false
grwlf/vsim
vhdl_ct/ct00287.vhd
1
2,141
-- NEED RESULT: ARCH00287: 'Abs' does not require parentheses around argument passed -- NEED RESULT: ARCH00287: 'Not' does not require parentheses around argument passed ------------------------------------------------------------------------------- -- -- Copyright (c) 1989 by Intermetrics, Inc. -- All rights reserved. -- ------------------------------------------------------------------------------- -- -- TEST NAME: -- -- CT00287 -- -- AUTHOR: -- -- A. Wilmot -- -- TEST OBJECTIVES: -- -- 7.1 (2) -- -- DESIGN UNIT ORDERING: -- -- E00000(ARCH00287) -- ENT00287_Test_Bench(ARCH00287_Test_Bench) -- -- REVISION HISTORY: -- -- 22-JUL-1987 - initial revision -- -- NOTES: -- -- self-checking -- use WORK.STANDARD_TYPES.all ; architecture ARCH00287 of E00000 is begin P00287 : process variable bool1 : boolean := false ; function fbool1 return boolean is begin return false ; end fbool1 ; variable int1 : integer := -4 ; function fint1 ( pint : integer ) return integer is begin return - pint ; end fint1 ; begin if abs int1 = 4 and abs 2 = 2 and abs fint1 (-10) = 10 and abs integer'(fint1(10)) = 10 and abs integer (fint1(3)) = 3 then test_report ( "ARCH00287" , "'Abs' does not require parentheses around argument" , true ) ; end if ; test_report ( "ARCH00287" , "'Not' does not require parentheses around argument" , not bool1 and not false and not fbool1 and not boolean'(fbool1) and not boolean' (fbool1) ) ; wait ; end process P00287 ; end ARCH00287 ; entity ENT00287_Test_Bench is end ENT00287_Test_Bench ; architecture ARCH00287_Test_Bench of ENT00287_Test_Bench is begin L1: block component UUT end component ; for CIS1 : UUT use entity WORK.E00000 ( ARCH00287 ) ; begin CIS1 : UUT ; end block L1 ; end ARCH00287_Test_Bench ;
gpl-3.0
255936e33970961ec72381faa996daac
0.519851
3.672384
false
true
false
false
jairov4/accel-oil
impl/impl_test_pcie/simulation/behavioral/system_sram_wrapper.vhd
1
18,308
------------------------------------------------------------------------------- -- system_sram_wrapper.vhd ------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; library xps_mch_emc_v3_01_a; use xps_mch_emc_v3_01_a.all; entity system_sram_wrapper is port ( MCH_SPLB_Clk : in std_logic; RdClk : in std_logic; MCH_SPLB_Rst : in std_logic; MCH0_Access_Control : in std_logic; MCH0_Access_Data : in std_logic_vector(0 to 31); MCH0_Access_Write : in std_logic; MCH0_Access_Full : out std_logic; MCH0_ReadData_Control : out std_logic; MCH0_ReadData_Data : out std_logic_vector(0 to 31); MCH0_ReadData_Read : in std_logic; MCH0_ReadData_Exists : out std_logic; MCH1_Access_Control : in std_logic; MCH1_Access_Data : in std_logic_vector(0 to 31); MCH1_Access_Write : in std_logic; MCH1_Access_Full : out std_logic; MCH1_ReadData_Control : out std_logic; MCH1_ReadData_Data : out std_logic_vector(0 to 31); MCH1_ReadData_Read : in std_logic; MCH1_ReadData_Exists : out std_logic; MCH2_Access_Control : in std_logic; MCH2_Access_Data : in std_logic_vector(0 to 31); MCH2_Access_Write : in std_logic; MCH2_Access_Full : out std_logic; MCH2_ReadData_Control : out std_logic; MCH2_ReadData_Data : out std_logic_vector(0 to 31); MCH2_ReadData_Read : in std_logic; MCH2_ReadData_Exists : out std_logic; MCH3_Access_Control : in std_logic; MCH3_Access_Data : in std_logic_vector(0 to 31); MCH3_Access_Write : in std_logic; MCH3_Access_Full : out std_logic; MCH3_ReadData_Control : out std_logic; MCH3_ReadData_Data : out std_logic_vector(0 to 31); MCH3_ReadData_Read : in std_logic; MCH3_ReadData_Exists : out std_logic; PLB_ABus : in std_logic_vector(0 to 31); PLB_UABus : in std_logic_vector(0 to 31); PLB_PAValid : in std_logic; PLB_SAValid : in std_logic; PLB_rdPrim : in std_logic; PLB_wrPrim : in std_logic; PLB_masterID : in std_logic_vector(0 to 2); PLB_abort : in std_logic; PLB_busLock : in std_logic; PLB_RNW : in std_logic; PLB_BE : in std_logic_vector(0 to 7); PLB_MSize : in std_logic_vector(0 to 1); PLB_size : in std_logic_vector(0 to 3); PLB_type : in std_logic_vector(0 to 2); PLB_lockErr : in std_logic; PLB_wrDBus : in std_logic_vector(0 to 63); PLB_wrBurst : in std_logic; PLB_rdBurst : in std_logic; PLB_wrPendReq : in std_logic; PLB_rdPendReq : in std_logic; PLB_wrPendPri : in std_logic_vector(0 to 1); PLB_rdPendPri : in std_logic_vector(0 to 1); PLB_reqPri : in std_logic_vector(0 to 1); PLB_TAttribute : in std_logic_vector(0 to 15); Sl_addrAck : out std_logic; Sl_SSize : out std_logic_vector(0 to 1); Sl_wait : out std_logic; Sl_rearbitrate : out std_logic; Sl_wrDAck : out std_logic; Sl_wrComp : out std_logic; Sl_wrBTerm : out std_logic; Sl_rdDBus : out std_logic_vector(0 to 63); Sl_rdWdAddr : out std_logic_vector(0 to 3); Sl_rdDAck : out std_logic; Sl_rdComp : out std_logic; Sl_rdBTerm : out std_logic; Sl_MBusy : out std_logic_vector(0 to 5); Sl_MWrErr : out std_logic_vector(0 to 5); Sl_MRdErr : out std_logic_vector(0 to 5); Sl_MIRQ : out std_logic_vector(0 to 5); Mem_DQ_I : in std_logic_vector(0 to 31); Mem_DQ_O : out std_logic_vector(0 to 31); Mem_DQ_T : out std_logic_vector(0 to 31); Mem_A : out std_logic_vector(0 to 31); Mem_RPN : out std_logic; Mem_CEN : out std_logic_vector(0 to 0); Mem_OEN : out std_logic_vector(0 to 0); Mem_WEN : out std_logic; Mem_QWEN : out std_logic_vector(0 to 3); Mem_BEN : out std_logic_vector(0 to 3); Mem_CE : out std_logic_vector(0 to 0); Mem_ADV_LDN : out std_logic; Mem_LBON : out std_logic; Mem_CKEN : out std_logic; Mem_RNW : out std_logic ); end system_sram_wrapper; architecture STRUCTURE of system_sram_wrapper is component xps_mch_emc is generic ( C_FAMILY : STRING; C_NUM_BANKS_MEM : INTEGER; C_NUM_CHANNELS : INTEGER; C_PRIORITY_MODE : INTEGER; C_INCLUDE_PLB_IPIF : INTEGER; C_INCLUDE_WRBUF : INTEGER; C_SPLB_MID_WIDTH : INTEGER; C_SPLB_NUM_MASTERS : INTEGER; C_SPLB_P2P : INTEGER; C_SPLB_DWIDTH : INTEGER; C_MCH_SPLB_AWIDTH : INTEGER; C_SPLB_SMALLEST_MASTER : INTEGER; C_MCH_NATIVE_DWIDTH : INTEGER; C_MCH_SPLB_CLK_PERIOD_PS : INTEGER; C_MEM0_BASEADDR : std_logic_vector; C_MEM0_HIGHADDR : std_logic_vector; C_MEM1_BASEADDR : std_logic_vector; C_MEM1_HIGHADDR : std_logic_vector; C_MEM2_BASEADDR : std_logic_vector; C_MEM2_HIGHADDR : std_logic_vector; C_MEM3_BASEADDR : std_logic_vector; C_MEM3_HIGHADDR : std_logic_vector; C_PAGEMODE_FLASH_0 : INTEGER; C_PAGEMODE_FLASH_1 : INTEGER; C_PAGEMODE_FLASH_2 : INTEGER; C_PAGEMODE_FLASH_3 : INTEGER; C_INCLUDE_NEGEDGE_IOREGS : INTEGER; C_MEM0_WIDTH : INTEGER; C_MEM1_WIDTH : INTEGER; C_MEM2_WIDTH : INTEGER; C_MEM3_WIDTH : INTEGER; C_MAX_MEM_WIDTH : INTEGER; C_INCLUDE_DATAWIDTH_MATCHING_0 : INTEGER; C_INCLUDE_DATAWIDTH_MATCHING_1 : INTEGER; C_INCLUDE_DATAWIDTH_MATCHING_2 : INTEGER; C_INCLUDE_DATAWIDTH_MATCHING_3 : INTEGER; C_SYNCH_MEM_0 : INTEGER; C_SYNCH_PIPEDELAY_0 : INTEGER; C_TCEDV_PS_MEM_0 : INTEGER; C_TAVDV_PS_MEM_0 : INTEGER; C_TPACC_PS_FLASH_0 : INTEGER; C_THZCE_PS_MEM_0 : INTEGER; C_THZOE_PS_MEM_0 : INTEGER; C_TWC_PS_MEM_0 : INTEGER; C_TWP_PS_MEM_0 : INTEGER; C_TLZWE_PS_MEM_0 : INTEGER; C_SYNCH_MEM_1 : INTEGER; C_SYNCH_PIPEDELAY_1 : INTEGER; C_TCEDV_PS_MEM_1 : INTEGER; C_TAVDV_PS_MEM_1 : INTEGER; C_TPACC_PS_FLASH_1 : INTEGER; C_THZCE_PS_MEM_1 : INTEGER; C_THZOE_PS_MEM_1 : INTEGER; C_TWC_PS_MEM_1 : INTEGER; C_TWP_PS_MEM_1 : INTEGER; C_TLZWE_PS_MEM_1 : INTEGER; C_SYNCH_MEM_2 : INTEGER; C_SYNCH_PIPEDELAY_2 : INTEGER; C_TCEDV_PS_MEM_2 : INTEGER; C_TAVDV_PS_MEM_2 : INTEGER; C_TPACC_PS_FLASH_2 : INTEGER; C_THZCE_PS_MEM_2 : INTEGER; C_THZOE_PS_MEM_2 : INTEGER; C_TWC_PS_MEM_2 : INTEGER; C_TWP_PS_MEM_2 : INTEGER; C_TLZWE_PS_MEM_2 : INTEGER; C_SYNCH_MEM_3 : INTEGER; C_SYNCH_PIPEDELAY_3 : INTEGER; C_TCEDV_PS_MEM_3 : INTEGER; C_TAVDV_PS_MEM_3 : INTEGER; C_TPACC_PS_FLASH_3 : INTEGER; C_THZCE_PS_MEM_3 : INTEGER; C_THZOE_PS_MEM_3 : INTEGER; C_TWC_PS_MEM_3 : INTEGER; C_TWP_PS_MEM_3 : INTEGER; C_TLZWE_PS_MEM_3 : INTEGER; C_MCH0_PROTOCOL : INTEGER; C_MCH0_ACCESSBUF_DEPTH : INTEGER; C_MCH0_RDDATABUF_DEPTH : INTEGER; C_MCH1_PROTOCOL : INTEGER; C_MCH1_ACCESSBUF_DEPTH : INTEGER; C_MCH1_RDDATABUF_DEPTH : INTEGER; C_MCH2_PROTOCOL : INTEGER; C_MCH2_ACCESSBUF_DEPTH : INTEGER; C_MCH2_RDDATABUF_DEPTH : INTEGER; C_MCH3_PROTOCOL : INTEGER; C_MCH3_ACCESSBUF_DEPTH : INTEGER; C_MCH3_RDDATABUF_DEPTH : INTEGER; C_XCL0_LINESIZE : INTEGER; C_XCL0_WRITEXFER : INTEGER; C_XCL1_LINESIZE : INTEGER; C_XCL1_WRITEXFER : INTEGER; C_XCL2_LINESIZE : INTEGER; C_XCL2_WRITEXFER : INTEGER; C_XCL3_LINESIZE : INTEGER; C_XCL3_WRITEXFER : INTEGER ); port ( MCH_SPLB_Clk : in std_logic; RdClk : in std_logic; MCH_SPLB_Rst : in std_logic; MCH0_Access_Control : in std_logic; MCH0_Access_Data : in std_logic_vector(0 to (C_MCH_NATIVE_DWIDTH-1)); MCH0_Access_Write : in std_logic; MCH0_Access_Full : out std_logic; MCH0_ReadData_Control : out std_logic; MCH0_ReadData_Data : out std_logic_vector(0 to (C_MCH_NATIVE_DWIDTH-1)); MCH0_ReadData_Read : in std_logic; MCH0_ReadData_Exists : out std_logic; MCH1_Access_Control : in std_logic; MCH1_Access_Data : in std_logic_vector(0 to (C_MCH_NATIVE_DWIDTH-1)); MCH1_Access_Write : in std_logic; MCH1_Access_Full : out std_logic; MCH1_ReadData_Control : out std_logic; MCH1_ReadData_Data : out std_logic_vector(0 to (C_MCH_NATIVE_DWIDTH-1)); MCH1_ReadData_Read : in std_logic; MCH1_ReadData_Exists : out std_logic; MCH2_Access_Control : in std_logic; MCH2_Access_Data : in std_logic_vector(0 to (C_MCH_NATIVE_DWIDTH-1)); MCH2_Access_Write : in std_logic; MCH2_Access_Full : out std_logic; MCH2_ReadData_Control : out std_logic; MCH2_ReadData_Data : out std_logic_vector(0 to (C_MCH_NATIVE_DWIDTH-1)); MCH2_ReadData_Read : in std_logic; MCH2_ReadData_Exists : out std_logic; MCH3_Access_Control : in std_logic; MCH3_Access_Data : in std_logic_vector(0 to (C_MCH_NATIVE_DWIDTH-1)); MCH3_Access_Write : in std_logic; MCH3_Access_Full : out std_logic; MCH3_ReadData_Control : out std_logic; MCH3_ReadData_Data : out std_logic_vector(0 to (C_MCH_NATIVE_DWIDTH-1)); MCH3_ReadData_Read : in std_logic; MCH3_ReadData_Exists : out std_logic; PLB_ABus : in std_logic_vector(0 to 31); PLB_UABus : in std_logic_vector(0 to 31); PLB_PAValid : in std_logic; PLB_SAValid : in std_logic; PLB_rdPrim : in std_logic; PLB_wrPrim : in std_logic; PLB_masterID : in std_logic_vector(0 to (C_SPLB_MID_WIDTH-1)); PLB_abort : in std_logic; PLB_busLock : in std_logic; PLB_RNW : in std_logic; PLB_BE : in std_logic_vector(0 to ((C_SPLB_DWIDTH/8)-1)); PLB_MSize : in std_logic_vector(0 to 1); PLB_size : in std_logic_vector(0 to 3); PLB_type : in std_logic_vector(0 to 2); PLB_lockErr : in std_logic; PLB_wrDBus : in std_logic_vector(0 to (C_SPLB_DWIDTH-1)); PLB_wrBurst : in std_logic; PLB_rdBurst : in std_logic; PLB_wrPendReq : in std_logic; PLB_rdPendReq : in std_logic; PLB_wrPendPri : in std_logic_vector(0 to 1); PLB_rdPendPri : in std_logic_vector(0 to 1); PLB_reqPri : in std_logic_vector(0 to 1); PLB_TAttribute : in std_logic_vector(0 to 15); Sl_addrAck : out std_logic; Sl_SSize : out std_logic_vector(0 to 1); Sl_wait : out std_logic; Sl_rearbitrate : out std_logic; Sl_wrDAck : out std_logic; Sl_wrComp : out std_logic; Sl_wrBTerm : out std_logic; Sl_rdDBus : out std_logic_vector(0 to (C_SPLB_DWIDTH-1)); Sl_rdWdAddr : out std_logic_vector(0 to 3); Sl_rdDAck : out std_logic; Sl_rdComp : out std_logic; Sl_rdBTerm : out std_logic; Sl_MBusy : out std_logic_vector(0 to (C_SPLB_NUM_MASTERS-1)); Sl_MWrErr : out std_logic_vector(0 to (C_SPLB_NUM_MASTERS-1)); Sl_MRdErr : out std_logic_vector(0 to (C_SPLB_NUM_MASTERS-1)); Sl_MIRQ : out std_logic_vector(0 to (C_SPLB_NUM_MASTERS-1)); Mem_DQ_I : in std_logic_vector(0 to (C_MAX_MEM_WIDTH-1)); Mem_DQ_O : out std_logic_vector(0 to (C_MAX_MEM_WIDTH-1)); Mem_DQ_T : out std_logic_vector(0 to (C_MAX_MEM_WIDTH-1)); Mem_A : out std_logic_vector(0 to (C_MCH_SPLB_AWIDTH-1)); Mem_RPN : out std_logic; Mem_CEN : out std_logic_vector(0 to (C_NUM_BANKS_MEM-1)); Mem_OEN : out std_logic_vector(0 to (C_NUM_BANKS_MEM-1)); Mem_WEN : out std_logic; Mem_QWEN : out std_logic_vector(0 to ((C_MAX_MEM_WIDTH/8)-1)); Mem_BEN : out std_logic_vector(0 to ((C_MAX_MEM_WIDTH/8)-1)); Mem_CE : out std_logic_vector(0 to (C_NUM_BANKS_MEM-1)); Mem_ADV_LDN : out std_logic; Mem_LBON : out std_logic; Mem_CKEN : out std_logic; Mem_RNW : out std_logic ); end component; begin SRAM : xps_mch_emc generic map ( C_FAMILY => "virtex5", C_NUM_BANKS_MEM => 1, C_NUM_CHANNELS => 0, C_PRIORITY_MODE => 0, C_INCLUDE_PLB_IPIF => 1, C_INCLUDE_WRBUF => 1, C_SPLB_MID_WIDTH => 3, C_SPLB_NUM_MASTERS => 6, C_SPLB_P2P => 0, C_SPLB_DWIDTH => 64, C_MCH_SPLB_AWIDTH => 32, C_SPLB_SMALLEST_MASTER => 32, C_MCH_NATIVE_DWIDTH => 32, C_MCH_SPLB_CLK_PERIOD_PS => 8000, C_MEM0_BASEADDR => X"9af00000", C_MEM0_HIGHADDR => X"9affffff", C_MEM1_BASEADDR => X"ffffffff", C_MEM1_HIGHADDR => X"00000000", C_MEM2_BASEADDR => X"ffffffff", C_MEM2_HIGHADDR => X"00000000", C_MEM3_BASEADDR => X"ffffffff", C_MEM3_HIGHADDR => X"00000000", C_PAGEMODE_FLASH_0 => 0, C_PAGEMODE_FLASH_1 => 0, C_PAGEMODE_FLASH_2 => 0, C_PAGEMODE_FLASH_3 => 0, C_INCLUDE_NEGEDGE_IOREGS => 0, C_MEM0_WIDTH => 32, C_MEM1_WIDTH => 32, C_MEM2_WIDTH => 32, C_MEM3_WIDTH => 32, C_MAX_MEM_WIDTH => 32, C_INCLUDE_DATAWIDTH_MATCHING_0 => 0, C_INCLUDE_DATAWIDTH_MATCHING_1 => 0, C_INCLUDE_DATAWIDTH_MATCHING_2 => 0, C_INCLUDE_DATAWIDTH_MATCHING_3 => 0, C_SYNCH_MEM_0 => 1, C_SYNCH_PIPEDELAY_0 => 2, C_TCEDV_PS_MEM_0 => 0, C_TAVDV_PS_MEM_0 => 0, C_TPACC_PS_FLASH_0 => 25000, C_THZCE_PS_MEM_0 => 0, C_THZOE_PS_MEM_0 => 0, C_TWC_PS_MEM_0 => 0, C_TWP_PS_MEM_0 => 0, C_TLZWE_PS_MEM_0 => 0, C_SYNCH_MEM_1 => 0, C_SYNCH_PIPEDELAY_1 => 2, C_TCEDV_PS_MEM_1 => 15000, C_TAVDV_PS_MEM_1 => 15000, C_TPACC_PS_FLASH_1 => 25000, C_THZCE_PS_MEM_1 => 7000, C_THZOE_PS_MEM_1 => 7000, C_TWC_PS_MEM_1 => 15000, C_TWP_PS_MEM_1 => 12000, C_TLZWE_PS_MEM_1 => 0, C_SYNCH_MEM_2 => 0, C_SYNCH_PIPEDELAY_2 => 2, C_TCEDV_PS_MEM_2 => 15000, C_TAVDV_PS_MEM_2 => 15000, C_TPACC_PS_FLASH_2 => 25000, C_THZCE_PS_MEM_2 => 7000, C_THZOE_PS_MEM_2 => 7000, C_TWC_PS_MEM_2 => 15000, C_TWP_PS_MEM_2 => 12000, C_TLZWE_PS_MEM_2 => 0, C_SYNCH_MEM_3 => 0, C_SYNCH_PIPEDELAY_3 => 2, C_TCEDV_PS_MEM_3 => 15000, C_TAVDV_PS_MEM_3 => 15000, C_TPACC_PS_FLASH_3 => 25000, C_THZCE_PS_MEM_3 => 7000, C_THZOE_PS_MEM_3 => 7000, C_TWC_PS_MEM_3 => 15000, C_TWP_PS_MEM_3 => 12000, C_TLZWE_PS_MEM_3 => 0, C_MCH0_PROTOCOL => 0, C_MCH0_ACCESSBUF_DEPTH => 16, C_MCH0_RDDATABUF_DEPTH => 16, C_MCH1_PROTOCOL => 0, C_MCH1_ACCESSBUF_DEPTH => 16, C_MCH1_RDDATABUF_DEPTH => 16, C_MCH2_PROTOCOL => 0, C_MCH2_ACCESSBUF_DEPTH => 16, C_MCH2_RDDATABUF_DEPTH => 16, C_MCH3_PROTOCOL => 0, C_MCH3_ACCESSBUF_DEPTH => 16, C_MCH3_RDDATABUF_DEPTH => 16, C_XCL0_LINESIZE => 4, C_XCL0_WRITEXFER => 1, C_XCL1_LINESIZE => 4, C_XCL1_WRITEXFER => 1, C_XCL2_LINESIZE => 4, C_XCL2_WRITEXFER => 1, C_XCL3_LINESIZE => 4, C_XCL3_WRITEXFER => 1 ) port map ( MCH_SPLB_Clk => MCH_SPLB_Clk, RdClk => RdClk, MCH_SPLB_Rst => MCH_SPLB_Rst, MCH0_Access_Control => MCH0_Access_Control, MCH0_Access_Data => MCH0_Access_Data, MCH0_Access_Write => MCH0_Access_Write, MCH0_Access_Full => MCH0_Access_Full, MCH0_ReadData_Control => MCH0_ReadData_Control, MCH0_ReadData_Data => MCH0_ReadData_Data, MCH0_ReadData_Read => MCH0_ReadData_Read, MCH0_ReadData_Exists => MCH0_ReadData_Exists, MCH1_Access_Control => MCH1_Access_Control, MCH1_Access_Data => MCH1_Access_Data, MCH1_Access_Write => MCH1_Access_Write, MCH1_Access_Full => MCH1_Access_Full, MCH1_ReadData_Control => MCH1_ReadData_Control, MCH1_ReadData_Data => MCH1_ReadData_Data, MCH1_ReadData_Read => MCH1_ReadData_Read, MCH1_ReadData_Exists => MCH1_ReadData_Exists, MCH2_Access_Control => MCH2_Access_Control, MCH2_Access_Data => MCH2_Access_Data, MCH2_Access_Write => MCH2_Access_Write, MCH2_Access_Full => MCH2_Access_Full, MCH2_ReadData_Control => MCH2_ReadData_Control, MCH2_ReadData_Data => MCH2_ReadData_Data, MCH2_ReadData_Read => MCH2_ReadData_Read, MCH2_ReadData_Exists => MCH2_ReadData_Exists, MCH3_Access_Control => MCH3_Access_Control, MCH3_Access_Data => MCH3_Access_Data, MCH3_Access_Write => MCH3_Access_Write, MCH3_Access_Full => MCH3_Access_Full, MCH3_ReadData_Control => MCH3_ReadData_Control, MCH3_ReadData_Data => MCH3_ReadData_Data, MCH3_ReadData_Read => MCH3_ReadData_Read, MCH3_ReadData_Exists => MCH3_ReadData_Exists, PLB_ABus => PLB_ABus, PLB_UABus => PLB_UABus, PLB_PAValid => PLB_PAValid, PLB_SAValid => PLB_SAValid, PLB_rdPrim => PLB_rdPrim, PLB_wrPrim => PLB_wrPrim, PLB_masterID => PLB_masterID, PLB_abort => PLB_abort, PLB_busLock => PLB_busLock, PLB_RNW => PLB_RNW, PLB_BE => PLB_BE, PLB_MSize => PLB_MSize, PLB_size => PLB_size, PLB_type => PLB_type, PLB_lockErr => PLB_lockErr, PLB_wrDBus => PLB_wrDBus, PLB_wrBurst => PLB_wrBurst, PLB_rdBurst => PLB_rdBurst, PLB_wrPendReq => PLB_wrPendReq, PLB_rdPendReq => PLB_rdPendReq, PLB_wrPendPri => PLB_wrPendPri, PLB_rdPendPri => PLB_rdPendPri, PLB_reqPri => PLB_reqPri, PLB_TAttribute => PLB_TAttribute, Sl_addrAck => Sl_addrAck, Sl_SSize => Sl_SSize, Sl_wait => Sl_wait, Sl_rearbitrate => Sl_rearbitrate, Sl_wrDAck => Sl_wrDAck, Sl_wrComp => Sl_wrComp, Sl_wrBTerm => Sl_wrBTerm, Sl_rdDBus => Sl_rdDBus, Sl_rdWdAddr => Sl_rdWdAddr, Sl_rdDAck => Sl_rdDAck, Sl_rdComp => Sl_rdComp, Sl_rdBTerm => Sl_rdBTerm, Sl_MBusy => Sl_MBusy, Sl_MWrErr => Sl_MWrErr, Sl_MRdErr => Sl_MRdErr, Sl_MIRQ => Sl_MIRQ, Mem_DQ_I => Mem_DQ_I, Mem_DQ_O => Mem_DQ_O, Mem_DQ_T => Mem_DQ_T, Mem_A => Mem_A, Mem_RPN => Mem_RPN, Mem_CEN => Mem_CEN, Mem_OEN => Mem_OEN, Mem_WEN => Mem_WEN, Mem_QWEN => Mem_QWEN, Mem_BEN => Mem_BEN, Mem_CE => Mem_CE, Mem_ADV_LDN => Mem_ADV_LDN, Mem_LBON => Mem_LBON, Mem_CKEN => Mem_CKEN, Mem_RNW => Mem_RNW ); end architecture STRUCTURE;
lgpl-3.0
343b0ed835a8ab1a0971cecf12225fcf
0.595204
2.982245
false
false
false
false
grwlf/vsim
vhdl/IEEE/old/mathpack.vhd
1
49,158
------------------------------------------------------------------------ -- -- This source file may be used and distributed without restriction. -- No declarations or definitions shall be added to this package. -- This package cannot be sold or distributed for profit. -- -- **************************************************************** -- * * -- * W A R N I N G * -- * * -- * This DRAFT version IS NOT endorsed or approved by IEEE * -- * * -- **************************************************************** -- -- Title: PACKAGE MATH_REAL -- -- Library: This package shall be compiled into a library -- symbolically named IEEE. -- -- Purpose: VHDL declarations for mathematical package MATH_REAL -- which contains common real constants, common real -- functions, and real trascendental functions. -- -- Author: IEEE VHDL Math Package Study Group -- -- Notes: -- The package body shall be considered the formal definition of -- the semantics of this package. Tool developers may choose to implement -- the package body in the most efficient manner available to them. -- -- History: -- Version 0.1 (Strawman) Jose A. Torres 6/22/92 -- Version 0.2 Jose A. Torres 1/15/93 -- Version 0.3 Jose A. Torres 4/13/93 -- Version 0.4 Jose A. Torres 4/19/93 -- Version 0.5 Jose A. Torres 4/20/93 Added RANDOM() -- Version 0.6 Jose A. Torres 4/23/93 Renamed RANDOM as -- UNIFORM. Modified -- rights banner. -- Version 0.7 Jose A. Torres 5/28/93 Rev up for compatibility -- with package body. ------------------------------------------------------------- Library IEEE; Package MATH_REAL is -- -- commonly used constants -- constant MATH_E : real := 2.71828_18284_59045_23536; -- value of e constant MATH_1_E: real := 0.36787_94411_71442_32160; -- value of 1/e constant MATH_PI : real := 3.14159_26535_89793_23846; -- value of pi constant MATH_1_PI : real := 0.31830_98861_83790_67154; -- value of 1/pi constant MATH_LOG_OF_2: real := 0.69314_71805_59945_30942; -- natural log of 2 constant MATH_LOG_OF_10: real := 2.30258_50929_94045_68402; -- natural log of10 constant MATH_LOG2_OF_E: real := 1.44269_50408_88963_4074; -- log base 2 of e constant MATH_LOG10_OF_E: real := 0.43429_44819_03251_82765; -- log base 10 of e constant MATH_SQRT2: real := 1.41421_35623_73095_04880; -- sqrt of 2 constant MATH_SQRT1_2: real := 0.70710_67811_86547_52440; -- sqrt of 1/2 constant MATH_SQRT_PI: real := 1.77245_38509_05516_02730; -- sqrt of pi constant MATH_DEG_TO_RAD: real := 0.01745_32925_19943_29577; -- conversion factor from degree to radian constant MATH_RAD_TO_DEG: real := 57.29577_95130_82320_87685; -- conversion factor from radian to degree -- -- attribute for functions whose implementation is foreign (C native) -- attribute FOREIGN : string; -- predefined attribute in VHDL-1992 -- -- function declarations -- function SIGN (X: real ) return real; -- returns 1.0 if X > 0.0; 0.0 if X == 0.0; -1.0 if X < 0.0 function CEIL (X : real ) return real; -- returns smallest integer value (as real) not less than X function FLOOR (X : real ) return real; -- returns largest integer value (as real) not greater than X function ROUND (X : real ) return real; -- returns integer FLOOR(X + 0.5) if X > 0; -- return integer CEIL(X - 0.5) if X < 0 function FMAX (X, Y : real ) return real; -- returns the algebraically larger of X and Y function FMIN (X, Y : real ) return real; -- returns the algebraically smaller of X and Y procedure UNIFORM (variable Seed1,Seed2:inout integer; variable X:out real); -- returns a pseudo-random number with uniform distribution in the -- interval (0.0, 1.0). -- Before the first call to UNIFORM, the seed values (Seed1, Seed2) must -- be initialized to values in the range [1, 2147483562] and -- [1, 2147483398] respectively. The seed values are modified after -- each call to UNIFORM. -- This random number generator is portable for 32-bit computers, and -- it has period ~2.30584*(10**18) for each set of seed values. -- -- For VHDL-1992, the seeds will be global variables, functions to -- initialize their values (INIT_SEED) will be provided, and the UNIFORM -- procedure call will be modified accordingly. function SRAND (seed: in integer ) return integer; -- -- sets value of seed for sequence of -- pseudo-random numbers. -- It uses the foreign native C function srand(). attribute FOREIGN of SRAND : function is "C_NATIVE"; function RAND return integer; -- -- returns an integer pseudo-random number with uniform distribution. -- It uses the foreign native C function rand(). -- Seed for the sequence is initialized with the -- SRAND() function and value of the seed is changed every -- time SRAND() is called, but it is not visible. -- The range of generated values is platform dependent. attribute FOREIGN of RAND : function is "C_NATIVE"; function GET_RAND_MAX return integer; -- -- returns the upper bound of the range of the -- pseudo-random numbers generated by RAND(). -- The support for this function is platform dependent, and -- it uses foreign native C functions or constants. -- It may not be available in some platforms. -- Note: the value of (RAND() / GET_RAND_MAX()) is a -- pseudo-random number distributed between 0 & 1. attribute FOREIGN of GET_RAND_MAX : function is "C_NATIVE"; function SQRT (X : real ) return real; -- returns square root of X; X >= 0 function CBRT (X : real ) return real; -- returns cube root of X function "**" (X : integer; Y : real) return real; -- returns Y power of X ==> X**Y; -- error if X = 0 and Y <= 0.0 -- error if X < 0 and Y does not have an integer value function "**" (X : real; Y : real) return real; -- returns Y power of X ==> X**Y; -- error if X = 0.0 and Y <= 0.0 -- error if X < 0.0 and Y does not have an integer value function EXP (X : real ) return real; -- returns e**X; where e = MATH_E function LOG (X : real ) return real; -- returns natural logarithm of X; X > 0 function LOG (BASE: positive; X : real) return real; -- returns logarithm base BASE of X; X > 0 function SIN (X : real ) return real; -- returns sin X; X in radians function COS ( X : real ) return real; -- returns cos X; X in radians function TAN (X : real ) return real; -- returns tan X; X in radians -- X /= ((2k+1) * PI/2), where k is an integer function ASIN (X : real ) return real; -- returns -PI/2 < asin X < PI/2; | X | <= 1 function ACOS (X : real ) return real; -- returns 0 < acos X < PI; | X | <= 1 function ATAN (X : real) return real; -- returns -PI/2 < atan X < PI/2 function ATAN2 (X : real; Y : real) return real; -- returns atan (X/Y); -PI < atan2(X,Y) < PI; Y /= 0.0 function SINH (X : real) return real; -- hyperbolic sine; returns (e**X - e**(-X))/2 function COSH (X : real) return real; -- hyperbolic cosine; returns (e**X + e**(-X))/2 function TANH (X : real) return real; -- hyperbolic tangent; -- returns (e**X - e**(-X))/(e**X + e**(-X)) function ASINH (X : real) return real; -- returns ln( X + sqrt( X**2 + 1)) function ACOSH (X : real) return real; -- returns ln( X + sqrt( X**2 - 1)); X >= 1 function ATANH (X : real) return real; -- returns (ln( (1 + X)/(1 - X)))/2 ; | X | < 1 end MATH_REAL; --------------------------------------------------------------- -- -- This source file may be used and distributed without restriction. -- No declarations or definitions shall be included in this package. -- This package cannot be sold or distributed for profit. -- -- **************************************************************** -- * * -- * W A R N I N G * -- * * -- * This DRAFT version IS NOT endorsed or approved by IEEE * -- * * -- **************************************************************** -- -- Title: PACKAGE MATH_COMPLEX -- -- Purpose: VHDL declarations for mathematical package MATH_COMPLEX -- which contains common complex constants and basic complex -- functions and operations. -- -- Author: IEEE VHDL Math Package Study Group -- -- Notes: -- The package body uses package IEEE.MATH_REAL -- -- The package body shall be considered the formal definition of -- the semantics of this package. Tool developers may choose to implement -- the package body in the most efficient manner available to them. -- -- History: -- Version 0.1 (Strawman) Jose A. Torres 6/22/92 -- Version 0.2 Jose A. Torres 1/15/93 -- Version 0.3 Jose A. Torres 4/13/93 -- Version 0.4 Jose A. Torres 4/19/93 -- Version 0.5 Jose A. Torres 4/20/93 -- Version 0.6 Jose A. Torres 4/23/93 Added unary minus -- and CONJ for polar -- Version 0.7 Jose A. Torres 5/28/93 Rev up for compatibility -- with package body. ------------------------------------------------------------- Library IEEE; Package MATH_COMPLEX is type COMPLEX is record RE, IM: real; end record; type COMPLEX_VECTOR is array (integer range <>) of COMPLEX; type COMPLEX_POLAR is record MAG: real; ARG: real; end record; constant CBASE_1: complex := COMPLEX'(1.0, 0.0); constant CBASE_j: complex := COMPLEX'(0.0, 1.0); constant CZERO: complex := COMPLEX'(0.0, 0.0); function CABS(Z: in complex ) return real; -- returns absolute value (magnitude) of Z function CARG(Z: in complex ) return real; -- returns argument (angle) in radians of a complex number function CMPLX(X: in real; Y: in real:= 0.0 ) return complex; -- returns complex number X + iY function "-" (Z: in complex ) return complex; -- unary minus function "-" (Z: in complex_polar ) return complex_polar; -- unary minus function CONJ (Z: in complex) return complex; -- returns complex conjugate function CONJ (Z: in complex_polar) return complex_polar; -- returns complex conjugate function CSQRT(Z: in complex ) return complex_vector; -- returns square root of Z; 2 values function CEXP(Z: in complex ) return complex; -- returns e**Z function COMPLEX_TO_POLAR(Z: in complex ) return complex_polar; -- converts complex to complex_polar function POLAR_TO_COMPLEX(Z: in complex_polar ) return complex; -- converts complex_polar to complex -- arithmetic operators function "+" ( L: in complex; R: in complex ) return complex; function "+" ( L: in complex_polar; R: in complex_polar) return complex; function "+" ( L: in complex_polar; R: in complex ) return complex; function "+" ( L: in complex; R: in complex_polar) return complex; function "+" ( L: in real; R: in complex ) return complex; function "+" ( L: in complex; R: in real ) return complex; function "+" ( L: in real; R: in complex_polar) return complex; function "+" ( L: in complex_polar; R: in real) return complex; function "-" ( L: in complex; R: in complex ) return complex; function "-" ( L: in complex_polar; R: in complex_polar) return complex; function "-" ( L: in complex_polar; R: in complex ) return complex; function "-" ( L: in complex; R: in complex_polar) return complex; function "-" ( L: in real; R: in complex ) return complex; function "-" ( L: in complex; R: in real ) return complex; function "-" ( L: in real; R: in complex_polar) return complex; function "-" ( L: in complex_polar; R: in real) return complex; function "*" ( L: in complex; R: in complex ) return complex; function "*" ( L: in complex_polar; R: in complex_polar) return complex; function "*" ( L: in complex_polar; R: in complex ) return complex; function "*" ( L: in complex; R: in complex_polar) return complex; function "*" ( L: in real; R: in complex ) return complex; function "*" ( L: in complex; R: in real ) return complex; function "*" ( L: in real; R: in complex_polar) return complex; function "*" ( L: in complex_polar; R: in real) return complex; function "/" ( L: in complex; R: in complex ) return complex; function "/" ( L: in complex_polar; R: in complex_polar) return complex; function "/" ( L: in complex_polar; R: in complex ) return complex; function "/" ( L: in complex; R: in complex_polar) return complex; function "/" ( L: in real; R: in complex ) return complex; function "/" ( L: in complex; R: in real ) return complex; function "/" ( L: in real; R: in complex_polar) return complex; function "/" ( L: in complex_polar; R: in real) return complex; end MATH_COMPLEX; --------------------------------------------------------------- -- -- This source file may be used and distributed without restriction. -- No declarations or definitions shall be added to this package. -- This package cannot be sold or distributed for profit. -- -- **************************************************************** -- * * -- * W A R N I N G * -- * * -- * This DRAFT version IS NOT endorsed or approved by IEEE * -- * * -- **************************************************************** -- -- Title: PACKAGE BODY MATH_REAL -- -- Library: This package shall be compiled into a library -- symbolically named IEEE. -- -- Purpose: VHDL declarations for mathematical package MATH_REAL -- which contains common real constants, common real -- functions, and real trascendental functions. -- -- Author: IEEE VHDL Math Package Study Group -- -- Notes: -- The package body shall be considered the formal definition of -- the semantics of this package. Tool developers may choose to implement -- the package body in the most efficient manner available to them. -- -- Source code and algorithms for this package body comes from the -- following sources: -- IEEE VHDL Math Package Study Group participants, -- U. of Mississippi, Mentor Graphics, Synopsys, -- Viewlogic/Vantage, Communications of the ACM (June 1988, Vol -- 31, Number 6, pp. 747, Pierre L'Ecuyer, Efficient and Portable -- Random Number Generators), Handbook of Mathematical Functions -- by Milton Abramowitz and Irene A. Stegun (Dover). -- -- History: -- Version 0.1 Jose A. Torres 4/23/93 First draft -- Version 0.2 Jose A. Torres 5/28/93 Fixed potentially illegal code ------------------------------------------------------------- Library IEEE; Package body MATH_REAL is -- -- some constants for use in the package body only -- constant Q_PI : real := MATH_PI/4.0; constant HALF_PI : real := MATH_PI/2.0; constant TWO_PI : real := MATH_PI*2.0; constant MAX_ITER: integer := 27; -- max precision factor for cordic -- -- some type declarations for cordic operations -- constant KC : REAL := 6.0725293500888142e-01; -- constant for cordic type REAL_VECTOR is array (NATURAL range <>) of REAL; type NATURAL_VECTOR is array (NATURAL range <>) of NATURAL; subtype REAL_VECTOR_N is REAL_VECTOR (0 to max_iter); subtype REAL_ARR_2 is REAL_VECTOR (0 to 1); subtype REAL_ARR_3 is REAL_VECTOR (0 to 2); subtype QUADRANT is INTEGER range 0 to 3; type CORDIC_MODE_TYPE is (ROTATION, VECTORING); -- -- auxiliary functions for cordic algorithms -- function POWER_OF_2_SERIES (d : NATURAL_VECTOR; initial_value : REAL; number_of_values : NATURAL) return REAL_VECTOR is variable v : REAL_VECTOR (0 to number_of_values); variable temp : REAL := initial_value; variable flag : boolean := true; begin for i in 0 to number_of_values loop v(i) := temp; for p in d'range loop if i = d(p) then flag := false; end if; end loop; if flag then temp := temp/2.0; end if; flag := true; end loop; return v; end POWER_OF_2_SERIES; constant two_at_minus : REAL_VECTOR := POWER_OF_2_SERIES( NATURAL_VECTOR'(100, 90),1.0, MAX_ITER); constant epsilon : REAL_VECTOR_N := ( 7.8539816339744827e-01, 4.6364760900080606e-01, 2.4497866312686413e-01, 1.2435499454676144e-01, 6.2418809995957351e-02, 3.1239833430268277e-02, 1.5623728620476830e-02, 7.8123410601011116e-03, 3.9062301319669717e-03, 1.9531225164788189e-03, 9.7656218955931937e-04, 4.8828121119489829e-04, 2.4414062014936175e-04, 1.2207031189367021e-04, 6.1035156174208768e-05, 3.0517578115526093e-05, 1.5258789061315760e-05, 7.6293945311019699e-06, 3.8146972656064960e-06, 1.9073486328101870e-06, 9.5367431640596080e-07, 4.7683715820308876e-07, 2.3841857910155801e-07, 1.1920928955078067e-07, 5.9604644775390553e-08, 2.9802322387695303e-08, 1.4901161193847654e-08, 7.4505805969238281e-09 ); function CORDIC ( x0 : REAL; y0 : REAL; z0 : REAL; n : NATURAL; -- precision factor CORDIC_MODE : CORDIC_MODE_TYPE -- rotation (z -> 0) -- or vectoring (y -> 0) ) return REAL_ARR_3 is variable x : REAL := x0; variable y : REAL := y0; variable z : REAL := z0; variable x_temp : REAL; begin if CORDIC_MODE = ROTATION then for k in 0 to n loop x_temp := x; if ( z >= 0.0) then x := x - y * two_at_minus(k); y := y + x_temp * two_at_minus(k); z := z - epsilon(k); else x := x + y * two_at_minus(k); y := y - x_temp * two_at_minus(k); z := z + epsilon(k); end if; end loop; else for k in 0 to n loop x_temp := x; if ( y < 0.0) then x := x - y * two_at_minus(k); y := y + x_temp * two_at_minus(k); z := z - epsilon(k); else x := x + y * two_at_minus(k); y := y - x_temp * two_at_minus(k); z := z + epsilon(k); end if; end loop; end if; return REAL_ARR_3'(x, y, z); end CORDIC; -- -- non-trascendental functions -- function SIGN (X: real ) return real is -- returns 1.0 if X > 0.0; 0.0 if X == 0.0; -1.0 if X < 0.0 begin if ( X > 0.0 ) then return 1.0; elsif ( X < 0.0 ) then return -1.0; else return 0.0; end if; end SIGN; function CEIL (X : real ) return real is -- returns smallest integer value (as real) not less than X -- No conversion to an integer type is expected, so truncate cannot -- overflow for large arguments. variable large: real := 1073741824.0; type long is range -1073741824 to 1073741824; -- 2**30 is longer than any single-precision mantissa variable rd: real; begin if abs( X) >= large then return X; else rd := real ( long( X)); if X > 0.0 then if rd >= X then return rd; else return rd + 1.0; end if; elsif X = 0.0 then return 0.0; else if rd <= X then return rd; else return rd - 1.0; end if; end if; end if; end CEIL; function FLOOR (X : real ) return real is -- returns largest integer value (as real) not greater than X -- No conversion to an integer type is expected, so truncate -- cannot overflow for large arguments. -- variable large: real := 1073741824.0; type long is range -1073741824 to 1073741824; -- 2**30 is longer than any single-precision mantissa variable rd: real; begin if abs( X ) >= large then return X; else rd := real ( long( X)); if X > 0.0 then if rd <= X then return rd; else return rd - 1.0; end if; elsif X = 0.0 then return 0.0; else if rd >= X then return rd; else return rd + 1.0; end if; end if; end if; end FLOOR; function ROUND (X : real ) return real is -- returns integer FLOOR(X + 0.5) if X > 0; -- return integer CEIL(X - 0.5) if X < 0 begin if X > 0.0 then return FLOOR(X + 0.5); elsif X < 0.0 then return CEIL( X - 0.5); else return 0.0; end if; end ROUND; function FMAX (X, Y : real ) return real is -- returns the algebraically larger of X and Y begin if X > Y then return X; else return Y; end if; end FMAX; function FMIN (X, Y : real ) return real is -- returns the algebraically smaller of X and Y begin if X < Y then return X; else return Y; end if; end FMIN; -- -- Pseudo-random number generators -- procedure UNIFORM(variable Seed1,Seed2:inout integer;variable X:out real) is -- returns a pseudo-random number with uniform distribution in the -- interval (0.0, 1.0). -- Before the first call to UNIFORM, the seed values (Seed1, Seed2) must -- be initialized to values in the range [1, 2147483562] and -- [1, 2147483398] respectively. The seed values are modified after -- each call to UNIFORM. -- This random number generator is portable for 32-bit computers, and -- it has period ~2.30584*(10**18) for each set of seed values. -- -- For VHDL-1992, the seeds will be global variables, functions to -- initialize their values (INIT_SEED) will be provided, and the UNIFORM -- procedure call will be modified accordingly. variable z, k: integer; begin k := Seed1/53668; Seed1 := 40014 * (Seed1 - k * 53668) - k * 12211; if Seed1 < 0 then Seed1 := Seed1 + 2147483563; end if; k := Seed2/52774; Seed2 := 40692 * (Seed2 - k * 52774) - k * 3791; if Seed2 < 0 then Seed2 := Seed2 + 2147483399; end if; z := Seed1 - Seed2; if z < 1 then z := z + 2147483562; end if; X := REAL(Z)*4.656613e-10; end UNIFORM; function SRAND (seed: in integer ) return integer is -- -- sets value of seed for sequence of -- pseudo-random numbers. -- Returns the value of the seed. -- It uses the foreign native C function srand(). begin end SRAND; function RAND return integer is -- -- returns an integer pseudo-random number with uniform distribution. -- It uses the foreign native C function rand(). -- Seed for the sequence is initialized with the -- SRAND() function and value of the seed is changed every -- time SRAND() is called, but it is not visible. -- The range of generated values is platform dependent. begin end RAND; function GET_RAND_MAX return integer is -- -- returns the upper bound of the range of the -- pseudo-random numbers generated by RAND(). -- The support for this function is platform dependent, and -- it uses foreign native C functions or constants. -- It may not be available in some platforms. -- Note: the value of (RAND / GET_RAND_MAX) is a -- pseudo-random number distributed between 0 & 1. begin end GET_RAND_MAX; -- -- trascendental and trigonometric functions -- function SQRT (X : real ) return real is -- returns square root of X; X >= 0 -- -- Computes square root using the Newton-Raphson approximation: -- F(n+1) = 0.5*[F(n) + x/F(n)]; -- constant inival: real := 1.5; constant eps : real := 0.000001; constant relative_err : real := eps*X; variable oldval : real ; variable newval : real ; begin -- check validity of argument if ( X < 0.0 ) then assert false report "X < 0 in SQRT(X)" severity ERROR; return (0.0); end if; -- get the square root for special cases if X = 0.0 then return 0.0; else if ( X = 1.0 ) then return 1.0; -- return exact value end if; end if; -- get the square root for general cases oldval := inival; newval := (X/oldval + oldval)/2.0; while ( abs(newval -oldval) > relative_err ) loop oldval := newval; newval := (X/oldval + oldval)/2.0; end loop; return newval; end SQRT; function CBRT (X : real ) return real is -- returns cube root of X -- Computes square root using the Newton-Raphson approximation: -- F(n+1) = (1/3)*[2*F(n) + x/F(n)**2]; -- constant inival: real := 1.5; constant eps : real := 0.000001; constant relative_err : real := eps*abs(X); variable xlocal : real := X; variable negative : boolean := X < 0.0; variable oldval : real ; variable newval : real ; begin -- compute root for special cases if X = 0.0 then return 0.0; elsif ( X = 1.0 ) then return 1.0; else if X = -1.0 then return -1.0; end if; end if; -- compute root for general cases if negative then xlocal := -X; end if; oldval := inival; newval := (xlocal/(oldval*oldval) + 2.0*oldval)/3.0; while ( abs(newval -oldval) > relative_err ) loop oldval := newval; newval :=(xlocal/(oldval*oldval) + 2.0*oldval)/3.0; end loop; if negative then newval := -newval; end if; return newval; end CBRT; function "**" (X : integer; Y : real) return real is -- returns Y power of X ==> X**Y; -- error if X = 0 and Y <= 0.0 -- error if X < 0 and Y does not have an integer value begin -- check validity of argument if ( X = 0 ) and ( Y <= 0.0 ) then assert false report "X = 0 and Y <= 0.0 in X**Y" severity ERROR; return (0.0); end if; if ( X < 0 ) and ( Y /= REAL(INTEGER(Y)) ) then assert false report "X < 0 and Y \= integer in X**Y" severity ERROR; return (0.0); end if; -- compute the result return EXP (Y * LOG (REAL(X))); end "**"; function "**" (X : real; Y : real) return real is -- returns Y power of X ==> X**Y; -- error if X = 0.0 and Y <= 0.0 -- error if X < 0.0 and Y does not have an integer value begin -- check validity of argument if ( X = 0.0 ) and ( Y <= 0.0 ) then assert false report "X = 0.0 and Y <= 0.0 in X**Y" severity ERROR; return (0.0); end if; if ( X < 0.0 ) and ( Y /= REAL(INTEGER(Y)) ) then assert false report "X < 0.0 and Y \= integer in X**Y" severity ERROR; return (0.0); end if; -- compute the result return EXP (Y * LOG (X)); end "**"; function EXP (X : real ) return real is -- returns e**X; where e = MATH_E -- -- This function computes the exponential using the following series: -- exp(x) = 1 + x + x**2/2! + x**3/3! + ... ; x > 0 -- constant eps : real := 0.000001; -- precision criteria variable reciprocal: boolean := x < 0.0;-- check sign of argument variable xlocal : real := abs(x); -- use positive value variable oldval: real ; -- following variables are variable num: real ; -- used for series evaluation variable count: integer ; variable denom: real ; variable newval: real ; begin -- compute value for special cases if X = 0.0 then return 1.0; else if X = 1.0 then return MATH_E; end if; end if; -- compute value for general cases oldval := 1.0; num := xlocal; count := 1; denom := 1.0; newval:= oldval + num/denom; while ( abs(newval - oldval) > eps ) loop oldval := newval; num := num*xlocal; count := count +1; denom := denom*(real(count)); newval := oldval + num/denom; end loop; if reciprocal then newval := 1.0/newval; end if; return newval; end EXP; function LOG (X : real ) return real is -- returns natural logarithm of X; X > 0 -- -- This function computes the exponential using the following series: -- log(x) = 2[ (x-1)/(x+1) + (((x-1)/(x+1))**3)/3.0 + ...] ; x > 0 -- constant eps : real := 0.000001; -- precision criteria variable xlocal: real ; -- following variables are variable oldval: real ; -- used to evaluate the series variable xlocalsqr: real ; variable factor : real ; variable count: integer ; variable newval: real ; begin -- check validity of argument if ( x <= 0.0 ) then assert false report "X <= 0 in LOG(X)" severity ERROR; return(REAL'LOW); end if; -- compute value for special cases if ( X = 1.0 ) then return 0.0; else if ( X = MATH_E ) then return 1.0; end if; end if; -- compute value for general cases xlocal := (X - 1.0)/(X + 1.0); oldval := xlocal; xlocalsqr := xlocal*xlocal; factor := xlocal*xlocalsqr; count := 3; newval := oldval + (factor/real(count)); while ( abs(newval - oldval) > eps ) loop oldval := newval; count := count +2; factor := factor * xlocalsqr; newval := oldval + factor/real(count); end loop; newval := newval * 2.0; return newval; end LOG; function LOG (BASE: positive; X : real) return real is -- returns logarithm base BASE of X; X > 0 begin -- check validity of argument if ( BASE <= 0 ) or ( x <= 0.0 ) then assert false report "BASE <= 0 or X <= 0.0 in LOG(BASE, X)" severity ERROR; return(REAL'LOW); end if; -- compute the value return ( LOG(X)/LOG(REAL(BASE))); end LOG; function SIN (X : real ) return real is -- returns sin X; X in radians variable n : INTEGER; begin if (x < 1.6 ) and (x > -1.6) then return CORDIC( KC, 0.0, x, 27, ROTATION)(1); end if; n := INTEGER( x / HALF_PI ); case QUADRANT( n mod 4 ) is when 0 => return CORDIC( KC, 0.0, x - REAL(n) * HALF_PI, 27, ROTATION)(1); when 1 => return CORDIC( KC, 0.0, x - REAL(n) * HALF_PI, 27, ROTATION)(0); when 2 => return -CORDIC( KC, 0.0, x - REAL(n) * HALF_PI, 27, ROTATION)(1); when 3 => return -CORDIC( KC, 0.0, x - REAL(n) * HALF_PI, 27, ROTATION)(0); end case; end SIN; function COS (x : REAL) return REAL is -- returns cos X; X in radians variable n : INTEGER; begin if (x < 1.6 ) and (x > -1.6) then return CORDIC( KC, 0.0, x, 27, ROTATION)(0); end if; n := INTEGER( x / HALF_PI ); case QUADRANT( n mod 4 ) is when 0 => return CORDIC( KC, 0.0, x - REAL(n) * HALF_PI, 27, ROTATION)(0); when 1 => return -CORDIC( KC, 0.0, x - REAL(n) * HALF_PI, 27, ROTATION)(1); when 2 => return -CORDIC( KC, 0.0, x - REAL(n) * HALF_PI, 27, ROTATION)(0); when 3 => return CORDIC( KC, 0.0, x - REAL(n) * HALF_PI, 27, ROTATION)(1); end case; end COS; function TAN (x : REAL) return REAL is -- returns tan X; X in radians -- X /= ((2k+1) * PI/2), where k is an integer variable n : INTEGER := INTEGER( x / HALF_PI ); variable v : REAL_ARR_3 := CORDIC( KC, 0.0, x - REAL(n) * HALF_PI, 27, ROTATION); begin if n mod 2 = 0 then return v(1)/v(0); else return -v(0)/v(1); end if; end TAN; function ASIN (x : real ) return real is -- returns -PI/2 < asin X < PI/2; | X | <= 1 begin if abs x > 1.0 then assert false report "Out of range parameter passed to ASIN" severity ERROR; return x; elsif abs x < 0.9 then return atan(x/(sqrt(1.0 - x*x))); elsif x > 0.0 then return HALF_PI - atan(sqrt(1.0 - x*x)/x); else return - HALF_PI + atan((sqrt(1.0 - x*x))/x); end if; end ASIN; function ACOS (x : REAL) return REAL is -- returns 0 < acos X < PI; | X | <= 1 begin if abs x > 1.0 then assert false report "Out of range parameter passed to ACOS" severity ERROR; return x; elsif abs x > 0.9 then if x > 0.0 then return atan(sqrt(1.0 - x*x)/x); else return MATH_PI - atan(sqrt(1.0 - x*x)/x); end if; else return HALF_PI - atan(x/sqrt(1.0 - x*x)); end if; end ACOS; function ATAN (x : REAL) return REAL is -- returns -PI/2 < atan X < PI/2 begin return CORDIC( 1.0, x, 0.0, 27, VECTORING )(2); end ATAN; function ATAN2 (x : REAL; y : REAL) return REAL is -- returns atan (X/Y); -PI < atan2(X,Y) < PI; Y /= 0.0 begin if y = 0.0 then if x = 0.0 then assert false report "atan2(0.0, 0.0) is undetermined, returned 0,0" severity NOTE; return 0.0; elsif x > 0.0 then return 0.0; else return MATH_PI; end if; elsif x > 0.0 then return CORDIC( x, y, 0.0, 27, VECTORING )(2); else return MATH_PI + CORDIC( x, y, 0.0, 27, VECTORING )(2); end if; end ATAN2; function SINH (X : real) return real is -- hyperbolic sine; returns (e**X - e**(-X))/2 begin return ( (EXP(X) - EXP(-X))/2.0 ); end SINH; function COSH (X : real) return real is -- hyperbolic cosine; returns (e**X + e**(-X))/2 begin return ( (EXP(X) + EXP(-X))/2.0 ); end COSH; function TANH (X : real) return real is -- hyperbolic tangent; -- returns (e**X - e**(-X))/(e**X + e**(-X)) begin return ( (EXP(X) - EXP(-X))/(EXP(X) + EXP(-X)) ); end TANH; function ASINH (X : real) return real is -- returns ln( X + sqrt( X**2 + 1)) begin return ( LOG( X + SQRT( X**2 + 1.0)) ); end ASINH; function ACOSH (X : real) return real is -- returns ln( X + sqrt( X**2 - 1)); X >= 1 begin if abs x >= 1.0 then assert false report "Out of range parameter passed to ACOSH" severity ERROR; return x; end if; return ( LOG( X + SQRT( X**2 - 1.0)) ); end ACOSH; function ATANH (X : real) return real is -- returns (ln( (1 + X)/(1 - X)))/2 ; | X | < 1 begin if abs x < 1.0 then assert false report "Out of range parameter passed to ATANH" severity ERROR; return x; end if; return( LOG( (1.0+X)/(1.0-X) )/2.0 ); end ATANH; end MATH_REAL; --------------------------------------------------------------- -- -- This source file may be used and distributed without restriction. -- No declarations or definitions shall be included in this package. -- This package cannot be sold or distributed for profit. -- -- **************************************************************** -- * * -- * W A R N I N G * -- * * -- * This DRAFT version IS NOT endorsed or approved by IEEE * -- * * -- **************************************************************** -- -- Title: PACKAGE BODY MATH_COMPLEX -- -- Purpose: VHDL declarations for mathematical package MATH_COMPLEX -- which contains common complex constants and basic complex -- functions and operations. -- -- Author: IEEE VHDL Math Package Study Group -- -- Notes: -- The package body uses package IEEE.MATH_REAL -- -- The package body shall be considered the formal definition of -- the semantics of this package. Tool developers may choose to implement -- the package body in the most efficient manner available to them. -- -- Source code for this package body comes from the following -- following sources: -- IEEE VHDL Math Package Study Group participants, -- U. of Mississippi, Mentor Graphics, Synopsys, -- Viewlogic/Vantage, Communications of the ACM (June 1988, Vol -- 31, Number 6, pp. 747, Pierre L'Ecuyer, Efficient and Portable -- Random Number Generators, Handbook of Mathematical Functions -- by Milton Abramowitz and Irene A. Stegun (Dover). -- -- History: -- Version 0.1 Jose A. Torres 4/23/93 First draft -- Version 0.2 Jose A. Torres 5/28/93 Fixed potentially illegal code -- ------------------------------------------------------------- Library IEEE; Use IEEE.MATH_REAL.all; -- real trascendental operations Package body MATH_COMPLEX is function CABS(Z: in complex ) return real is -- returns absolute value (magnitude) of Z variable ztemp : complex_polar; begin ztemp := COMPLEX_TO_POLAR(Z); return ztemp.mag; end CABS; function CARG(Z: in complex ) return real is -- returns argument (angle) in radians of a complex number variable ztemp : complex_polar; begin ztemp := COMPLEX_TO_POLAR(Z); return ztemp.arg; end CARG; function CMPLX(X: in real; Y: in real := 0.0 ) return complex is -- returns complex number X + iY begin return COMPLEX'(X, Y); end CMPLX; function "-" (Z: in complex ) return complex is -- unary minus; returns -x -jy for z= x + jy begin return COMPLEX'(-z.Re, -z.Im); end "-"; function "-" (Z: in complex_polar ) return complex_polar is -- unary minus; returns (z.mag, z.arg + MATH_PI) begin return COMPLEX_POLAR'(z.mag, z.arg + MATH_PI); end "-"; function CONJ (Z: in complex) return complex is -- returns complex conjugate (x-jy for z = x+ jy) begin return COMPLEX'(z.Re, -z.Im); end CONJ; function CONJ (Z: in complex_polar) return complex_polar is -- returns complex conjugate (z.mag, -z.arg) begin return COMPLEX_POLAR'(z.mag, -z.arg); end CONJ; function CSQRT(Z: in complex ) return complex_vector is -- returns square root of Z; 2 values variable ztemp : complex_polar; variable zout : complex_vector (0 to 1); variable temp : real; begin ztemp := COMPLEX_TO_POLAR(Z); temp := SQRT(ztemp.mag); zout(0).re := temp*COS(ztemp.arg/2.0); zout(0).im := temp*SIN(ztemp.arg/2.0); zout(1).re := temp*COS(ztemp.arg/2.0 + MATH_PI); zout(1).im := temp*SIN(ztemp.arg/2.0 + MATH_PI); return zout; end CSQRT; function CEXP(Z: in complex ) return complex is -- returns e**Z begin return COMPLEX'(EXP(Z.re)*COS(Z.im), EXP(Z.re)*SIN(Z.im)); end CEXP; function COMPLEX_TO_POLAR(Z: in complex ) return complex_polar is -- converts complex to complex_polar begin return COMPLEX_POLAR'(sqrt(z.re**2 + z.im**2),atan2(z.re,z.im)); end COMPLEX_TO_POLAR; function POLAR_TO_COMPLEX(Z: in complex_polar ) return complex is -- converts complex_polar to complex begin return COMPLEX'( z.mag*cos(z.arg), z.mag*sin(z.arg) ); end POLAR_TO_COMPLEX; -- -- arithmetic operators -- function "+" ( L: in complex; R: in complex ) return complex is begin return COMPLEX'(L.Re + R.Re, L.Im + R.Im); end "+"; function "+" (L: in complex_polar; R: in complex_polar) return complex is variable zL, zR : complex; begin zL := POLAR_TO_COMPLEX( L ); zR := POLAR_TO_COMPLEX( R ); return COMPLEX'(zL.Re + zR.Re, zL.Im + zR.Im); end "+"; function "+" ( L: in complex_polar; R: in complex ) return complex is variable zL : complex; begin zL := POLAR_TO_COMPLEX( L ); return COMPLEX'(zL.Re + R.Re, zL.Im + R.Im); end "+"; function "+" ( L: in complex; R: in complex_polar) return complex is variable zR : complex; begin zR := POLAR_TO_COMPLEX( R ); return COMPLEX'(L.Re + zR.Re, L.Im + zR.Im); end "+"; function "+" ( L: in real; R: in complex ) return complex is begin return COMPLEX'(L + R.Re, R.Im); end "+"; function "+" ( L: in complex; R: in real ) return complex is begin return COMPLEX'(L.Re + R, L.Im); end "+"; function "+" ( L: in real; R: in complex_polar) return complex is variable zR : complex; begin zR := POLAR_TO_COMPLEX( R ); return COMPLEX'(L + zR.Re, zR.Im); end "+"; function "+" ( L: in complex_polar; R: in real) return complex is variable zL : complex; begin zL := POLAR_TO_COMPLEX( L ); return COMPLEX'(zL.Re + R, zL.Im); end "+"; function "-" ( L: in complex; R: in complex ) return complex is begin return COMPLEX'(L.Re - R.Re, L.Im - R.Im); end "-"; function "-" ( L: in complex_polar; R: in complex_polar) return complex is variable zL, zR : complex; begin zL := POLAR_TO_COMPLEX( L ); zR := POLAR_TO_COMPLEX( R ); return COMPLEX'(zL.Re - zR.Re, zL.Im - zR.Im); end "-"; function "-" ( L: in complex_polar; R: in complex ) return complex is variable zL : complex; begin zL := POLAR_TO_COMPLEX( L ); return COMPLEX'(zL.Re - R.Re, zL.Im - R.Im); end "-"; function "-" ( L: in complex; R: in complex_polar) return complex is variable zR : complex; begin zR := POLAR_TO_COMPLEX( R ); return COMPLEX'(L.Re - zR.Re, L.Im - zR.Im); end "-"; function "-" ( L: in real; R: in complex ) return complex is begin return COMPLEX'(L - R.Re, -1.0 * R.Im); end "-"; function "-" ( L: in complex; R: in real ) return complex is begin return COMPLEX'(L.Re - R, L.Im); end "-"; function "-" ( L: in real; R: in complex_polar) return complex is variable zR : complex; begin zR := POLAR_TO_COMPLEX( R ); return COMPLEX'(L - zR.Re, -1.0*zR.Im); end "-"; function "-" ( L: in complex_polar; R: in real) return complex is variable zL : complex; begin zL := POLAR_TO_COMPLEX( L ); return COMPLEX'(zL.Re - R, zL.Im); end "-"; function "*" ( L: in complex; R: in complex ) return complex is begin return COMPLEX'(L.Re * R.Re - L.Im * R.Im, L.Re * R.Im + L.Im * R.Re); end "*"; function "*" ( L: in complex_polar; R: in complex_polar) return complex is variable zout : complex_polar; begin zout.mag := L.mag * R.mag; zout.arg := L.arg + R.arg; return POLAR_TO_COMPLEX(zout); end "*"; function "*" ( L: in complex_polar; R: in complex ) return complex is variable zL : complex; begin zL := POLAR_TO_COMPLEX( L ); return COMPLEX'(zL.Re*R.Re - zL.Im * R.Im, zL.Re * R.Im + zL.Im*R.Re); end "*"; function "*" ( L: in complex; R: in complex_polar) return complex is variable zR : complex; begin zR := POLAR_TO_COMPLEX( R ); return COMPLEX'(L.Re*zR.Re - L.Im * zR.Im, L.Re * zR.Im + L.Im*zR.Re); end "*"; function "*" ( L: in real; R: in complex ) return complex is begin return COMPLEX'(L * R.Re, L * R.Im); end "*"; function "*" ( L: in complex; R: in real ) return complex is begin return COMPLEX'(L.Re * R, L.Im * R); end "*"; function "*" ( L: in real; R: in complex_polar) return complex is variable zR : complex; begin zR := POLAR_TO_COMPLEX( R ); return COMPLEX'(L * zR.Re, L * zR.Im); end "*"; function "*" ( L: in complex_polar; R: in real) return complex is variable zL : complex; begin zL := POLAR_TO_COMPLEX( L ); return COMPLEX'(zL.Re * R, zL.Im * R); end "*"; function "/" ( L: in complex; R: in complex ) return complex is variable magrsq : REAL := R.Re ** 2 + R.Im ** 2; begin if (magrsq = 0.0) then assert FALSE report "Attempt to divide by (0,0)" severity ERROR; return COMPLEX'(REAL'RIGHT, REAL'RIGHT); else return COMPLEX'( (L.Re * R.Re + L.Im * R.Im) / magrsq, (L.Im * R.Re - L.Re * R.Im) / magrsq); end if; end "/"; function "/" ( L: in complex_polar; R: in complex_polar) return complex is variable zout : complex_polar; begin if (R.mag = 0.0) then assert FALSE report "Attempt to divide by (0,0)" severity ERROR; return COMPLEX'(REAL'RIGHT, REAL'RIGHT); else zout.mag := L.mag/R.mag; zout.arg := L.arg - R.arg; return POLAR_TO_COMPLEX(zout); end if; end "/"; function "/" ( L: in complex_polar; R: in complex ) return complex is variable zL : complex; variable temp : REAL := R.Re ** 2 + R.Im ** 2; begin if (temp = 0.0) then assert FALSE report "Attempt to divide by (0.0,0.0)" severity ERROR; return COMPLEX'(REAL'RIGHT, REAL'RIGHT); else zL := POLAR_TO_COMPLEX( L ); return COMPLEX'( (zL.Re * R.Re + zL.Im * R.Im) / temp, (zL.Im * R.Re - zL.Re * R.Im) / temp); end if; end "/"; function "/" ( L: in complex; R: in complex_polar) return complex is variable zR : complex := POLAR_TO_COMPLEX( R ); variable temp : REAL := zR.Re ** 2 + zR.Im ** 2; begin if (R.mag = 0.0) or (temp = 0.0) then assert FALSE report "Attempt to divide by (0.0,0.0)" severity ERROR; return COMPLEX'(REAL'RIGHT, REAL'RIGHT); else return COMPLEX'( (L.Re * zR.Re + L.Im * zR.Im) / temp, (L.Im * zR.Re - L.Re * zR.Im) / temp); end if; end "/"; function "/" ( L: in real; R: in complex ) return complex is variable temp : REAL := R.Re ** 2 + R.Im ** 2; begin if (temp = 0.0) then assert FALSE report "Attempt to divide by (0.0,0.0)" severity ERROR; return COMPLEX'(REAL'RIGHT, REAL'RIGHT); else temp := L / temp; return COMPLEX'( temp * R.Re, -temp * R.Im ); end if; end "/"; function "/" ( L: in complex; R: in real ) return complex is begin if (R = 0.0) then assert FALSE report "Attempt to divide by (0.0,0.0)" severity ERROR; return COMPLEX'(REAL'RIGHT, REAL'RIGHT); else return COMPLEX'(L.Re / R, L.Im / R); end if; end "/"; function "/" ( L: in real; R: in complex_polar) return complex is variable zR : complex := POLAR_TO_COMPLEX( R ); variable temp : REAL := zR.Re ** 2 + zR.Im ** 2; begin if (R.mag = 0.0) or (temp = 0.0) then assert FALSE report "Attempt to divide by (0.0,0.0)" severity ERROR; return COMPLEX'(REAL'RIGHT, REAL'RIGHT); else temp := L / temp; return COMPLEX'( temp * zR.Re, -temp * zR.Im ); end if; end "/"; function "/" ( L: in complex_polar; R: in real) return complex is variable zL : complex := POLAR_TO_COMPLEX( L ); begin if (R = 0.0) then assert FALSE report "Attempt to divide by (0.0,0.0)" severity ERROR; return COMPLEX'(REAL'RIGHT, REAL'RIGHT); else return COMPLEX'(zL.Re / R, zL.Im / R); end if; end "/"; end MATH_COMPLEX;
gpl-3.0
014b427abbe676483db85b29d93ea624
0.547561
3.508529
false
false
false
false
jairov4/accel-oil
solution_spartan3/impl/vhdl/bitset_next.vhd
2
25,988
-- ============================================================== -- RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC -- Version: 2013.4 -- Copyright (C) 2013 Xilinx Inc. All rights reserved. -- -- =========================================================== library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; entity bitset_next is port ( ap_clk : IN STD_LOGIC; ap_rst : IN STD_LOGIC; p_read : IN STD_LOGIC_VECTOR (31 downto 0); r_bit : IN STD_LOGIC_VECTOR (7 downto 0); r_bucket_index : IN STD_LOGIC_VECTOR (7 downto 0); r_bucket : IN STD_LOGIC_VECTOR (31 downto 0); ap_return_0 : OUT STD_LOGIC_VECTOR (7 downto 0); ap_return_1 : OUT STD_LOGIC_VECTOR (7 downto 0); ap_return_2 : OUT STD_LOGIC_VECTOR (31 downto 0); ap_return_3 : OUT STD_LOGIC_VECTOR (0 downto 0); ap_ce : IN STD_LOGIC ); end; architecture behav of bitset_next is constant ap_const_logic_1 : STD_LOGIC := '1'; constant ap_const_logic_0 : STD_LOGIC := '0'; constant ap_true : BOOLEAN := true; constant ap_const_lv1_0 : STD_LOGIC_VECTOR (0 downto 0) := "0"; constant ap_const_lv32_0 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000000"; constant ap_const_lv1_1 : STD_LOGIC_VECTOR (0 downto 0) := "1"; constant ap_const_lv2_1 : STD_LOGIC_VECTOR (1 downto 0) := "01"; constant ap_const_lv2_2 : STD_LOGIC_VECTOR (1 downto 0) := "10"; constant ap_const_lv32_FFFFFFFF : STD_LOGIC_VECTOR (31 downto 0) := "11111111111111111111111111111111"; constant ap_const_lv2_0 : STD_LOGIC_VECTOR (1 downto 0) := "00"; constant ap_const_lv32_1 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000001"; constant ap_const_lv8_1 : STD_LOGIC_VECTOR (7 downto 0) := "00000001"; signal grp_p_bsf32_hw_fu_118_ap_return : STD_LOGIC_VECTOR (4 downto 0); signal reg_123 : STD_LOGIC_VECTOR (4 downto 0); signal tmp_3_reg_232 : STD_LOGIC_VECTOR (0 downto 0); signal tmp_26_1_reg_236 : STD_LOGIC_VECTOR (0 downto 0); signal tmp_28_1_reg_240 : STD_LOGIC_VECTOR (0 downto 0); signal r_bucket_read_reg_194 : STD_LOGIC_VECTOR (31 downto 0); signal ap_reg_ppstg_r_bucket_read_reg_194_pp0_it1 : STD_LOGIC_VECTOR (31 downto 0); signal ap_reg_ppstg_r_bucket_read_reg_194_pp0_it2 : STD_LOGIC_VECTOR (31 downto 0); signal ap_reg_ppstg_r_bucket_read_reg_194_pp0_it3 : STD_LOGIC_VECTOR (31 downto 0); signal ap_reg_ppstg_r_bucket_read_reg_194_pp0_it4 : STD_LOGIC_VECTOR (31 downto 0); signal ap_reg_ppstg_r_bucket_read_reg_194_pp0_it5 : STD_LOGIC_VECTOR (31 downto 0); signal ap_reg_ppstg_r_bucket_read_reg_194_pp0_it6 : STD_LOGIC_VECTOR (31 downto 0); signal ap_reg_ppstg_r_bucket_read_reg_194_pp0_it7 : STD_LOGIC_VECTOR (31 downto 0); signal r_bit_read_reg_200 : STD_LOGIC_VECTOR (7 downto 0); signal ap_reg_ppstg_r_bit_read_reg_200_pp0_it1 : STD_LOGIC_VECTOR (7 downto 0); signal ap_reg_ppstg_r_bit_read_reg_200_pp0_it2 : STD_LOGIC_VECTOR (7 downto 0); signal ap_reg_ppstg_r_bit_read_reg_200_pp0_it3 : STD_LOGIC_VECTOR (7 downto 0); signal ap_reg_ppstg_r_bit_read_reg_200_pp0_it4 : STD_LOGIC_VECTOR (7 downto 0); signal ap_reg_ppstg_r_bit_read_reg_200_pp0_it5 : STD_LOGIC_VECTOR (7 downto 0); signal ap_reg_ppstg_r_bit_read_reg_200_pp0_it6 : STD_LOGIC_VECTOR (7 downto 0); signal ap_reg_ppstg_r_bit_read_reg_200_pp0_it7 : STD_LOGIC_VECTOR (7 downto 0); signal ap_reg_ppstg_r_bit_read_reg_200_pp0_it8 : STD_LOGIC_VECTOR (7 downto 0); signal ap_reg_ppstg_r_bit_read_reg_200_pp0_it9 : STD_LOGIC_VECTOR (7 downto 0); signal p_read_1_reg_206 : STD_LOGIC_VECTOR (31 downto 0); signal ap_reg_ppstg_p_read_1_reg_206_pp0_it1 : STD_LOGIC_VECTOR (31 downto 0); signal ap_reg_ppstg_p_read_1_reg_206_pp0_it2 : STD_LOGIC_VECTOR (31 downto 0); signal ap_reg_ppstg_p_read_1_reg_206_pp0_it3 : STD_LOGIC_VECTOR (31 downto 0); signal ap_reg_ppstg_p_read_1_reg_206_pp0_it4 : STD_LOGIC_VECTOR (31 downto 0); signal ap_reg_ppstg_p_read_1_reg_206_pp0_it5 : STD_LOGIC_VECTOR (31 downto 0); signal ap_reg_ppstg_p_read_1_reg_206_pp0_it6 : STD_LOGIC_VECTOR (31 downto 0); signal ap_reg_ppstg_p_read_1_reg_206_pp0_it7 : STD_LOGIC_VECTOR (31 downto 0); signal ap_reg_ppstg_p_read_1_reg_206_pp0_it8 : STD_LOGIC_VECTOR (31 downto 0); signal ap_reg_ppstg_p_read_1_reg_206_pp0_it9 : STD_LOGIC_VECTOR (31 downto 0); signal ap_reg_ppstg_p_read_1_reg_206_pp0_it10 : STD_LOGIC_VECTOR (31 downto 0); signal tmp_fu_127_p1 : STD_LOGIC_VECTOR (1 downto 0); signal tmp_reg_214 : STD_LOGIC_VECTOR (1 downto 0); signal ap_reg_ppstg_tmp_reg_214_pp0_it1 : STD_LOGIC_VECTOR (1 downto 0); signal ap_reg_ppstg_tmp_reg_214_pp0_it2 : STD_LOGIC_VECTOR (1 downto 0); signal ap_reg_ppstg_tmp_reg_214_pp0_it3 : STD_LOGIC_VECTOR (1 downto 0); signal ap_reg_ppstg_tmp_reg_214_pp0_it4 : STD_LOGIC_VECTOR (1 downto 0); signal ap_reg_ppstg_tmp_reg_214_pp0_it5 : STD_LOGIC_VECTOR (1 downto 0); signal ap_reg_ppstg_tmp_reg_214_pp0_it6 : STD_LOGIC_VECTOR (1 downto 0); signal ap_reg_ppstg_tmp_reg_214_pp0_it7 : STD_LOGIC_VECTOR (1 downto 0); signal ap_reg_ppstg_tmp_reg_214_pp0_it8 : STD_LOGIC_VECTOR (1 downto 0); signal ap_reg_ppstg_tmp_reg_214_pp0_it9 : STD_LOGIC_VECTOR (1 downto 0); signal ap_reg_ppstg_tmp_reg_214_pp0_it10 : STD_LOGIC_VECTOR (1 downto 0); signal grp_fu_131_p2 : STD_LOGIC_VECTOR (31 downto 0); signal tmp_1_reg_220 : STD_LOGIC_VECTOR (31 downto 0); signal bus_assign_fu_137_p2 : STD_LOGIC_VECTOR (31 downto 0); signal bus_assign_reg_225 : STD_LOGIC_VECTOR (31 downto 0); signal ap_reg_ppstg_bus_assign_reg_225_pp0_it9 : STD_LOGIC_VECTOR (31 downto 0); signal ap_reg_ppstg_bus_assign_reg_225_pp0_it10 : STD_LOGIC_VECTOR (31 downto 0); signal tmp_3_fu_141_p2 : STD_LOGIC_VECTOR (0 downto 0); signal ap_reg_ppstg_tmp_3_reg_232_pp0_it10 : STD_LOGIC_VECTOR (0 downto 0); signal tmp_26_1_fu_146_p2 : STD_LOGIC_VECTOR (0 downto 0); signal ap_reg_ppstg_tmp_26_1_reg_236_pp0_it10 : STD_LOGIC_VECTOR (0 downto 0); signal tmp_28_1_fu_151_p2 : STD_LOGIC_VECTOR (0 downto 0); signal ap_reg_ppstg_tmp_28_1_reg_240_pp0_it10 : STD_LOGIC_VECTOR (0 downto 0); signal grp_p_bsf32_hw_fu_118_bus_r : STD_LOGIC_VECTOR (31 downto 0); signal grp_p_bsf32_hw_fu_118_ap_ce : STD_LOGIC; signal ap_reg_phiprechg_agg_result_bucket_write_assign_reg_54pp0_it11 : STD_LOGIC_VECTOR (31 downto 0); signal agg_result_bucket_write_assign_phi_fu_58_p8 : STD_LOGIC_VECTOR (31 downto 0); signal ap_reg_phiprechg_agg_result_bucket_write_assign_reg_54pp0_it10 : STD_LOGIC_VECTOR (31 downto 0); signal ap_reg_phiprechg_agg_result_end_write_assign_reg_69pp0_it11 : STD_LOGIC_VECTOR (0 downto 0); signal agg_result_end_write_assign_phi_fu_73_p8 : STD_LOGIC_VECTOR (0 downto 0); signal ap_reg_phiprechg_agg_result_end_write_assign_reg_69pp0_it10 : STD_LOGIC_VECTOR (0 downto 0); signal ap_reg_phiprechg_agg_result_bucket_index_write_assign_reg_87pp0_it11 : STD_LOGIC_VECTOR (1 downto 0); signal agg_result_bucket_index_write_assign_phi_fu_91_p8 : STD_LOGIC_VECTOR (1 downto 0); signal ap_reg_phiprechg_agg_result_bucket_index_write_assign_reg_87pp0_it10 : STD_LOGIC_VECTOR (1 downto 0); signal agg_result_bit_write_assign_trunc3_ext_fu_161_p1 : STD_LOGIC_VECTOR (7 downto 0); signal ap_reg_phiprechg_agg_result_bit_write_assign_reg_104pp0_it11 : STD_LOGIC_VECTOR (7 downto 0); signal agg_result_bit_write_assign_phi_fu_107_p8 : STD_LOGIC_VECTOR (7 downto 0); signal agg_result_bit_write_assign_trunc_ext_fu_156_p1 : STD_LOGIC_VECTOR (7 downto 0); signal ap_reg_phiprechg_agg_result_bit_write_assign_reg_104pp0_it10 : STD_LOGIC_VECTOR (7 downto 0); signal grp_fu_131_p0 : STD_LOGIC_VECTOR (31 downto 0); signal grp_fu_131_p1 : STD_LOGIC_VECTOR (31 downto 0); signal agg_result_bucket_index_write_assign_cast_fu_166_p1 : STD_LOGIC_VECTOR (7 downto 0); signal grp_fu_131_ce : STD_LOGIC; signal ap_sig_bdd_139 : BOOLEAN; signal ap_sig_bdd_143 : BOOLEAN; component p_bsf32_hw IS port ( ap_clk : IN STD_LOGIC; ap_rst : IN STD_LOGIC; bus_r : IN STD_LOGIC_VECTOR (31 downto 0); ap_return : OUT STD_LOGIC_VECTOR (4 downto 0); ap_ce : IN STD_LOGIC ); end component; component nfa_accept_samples_generic_hw_add_32ns_32s_32_8 IS generic ( ID : INTEGER; NUM_STAGE : INTEGER; din0_WIDTH : INTEGER; din1_WIDTH : INTEGER; dout_WIDTH : INTEGER ); port ( clk : IN STD_LOGIC; reset : IN STD_LOGIC; din0 : IN STD_LOGIC_VECTOR (31 downto 0); din1 : IN STD_LOGIC_VECTOR (31 downto 0); ce : IN STD_LOGIC; dout : OUT STD_LOGIC_VECTOR (31 downto 0) ); end component; begin grp_p_bsf32_hw_fu_118 : component p_bsf32_hw port map ( ap_clk => ap_clk, ap_rst => ap_rst, bus_r => grp_p_bsf32_hw_fu_118_bus_r, ap_return => grp_p_bsf32_hw_fu_118_ap_return, ap_ce => grp_p_bsf32_hw_fu_118_ap_ce); nfa_accept_samples_generic_hw_add_32ns_32s_32_8_U11 : component nfa_accept_samples_generic_hw_add_32ns_32s_32_8 generic map ( ID => 11, NUM_STAGE => 8, din0_WIDTH => 32, din1_WIDTH => 32, dout_WIDTH => 32) port map ( clk => ap_clk, reset => ap_rst, din0 => grp_fu_131_p0, din1 => grp_fu_131_p1, ce => grp_fu_131_ce, dout => grp_fu_131_p2); -- ap_reg_phiprechg_agg_result_bit_write_assign_reg_104pp0_it11 assign process. -- ap_reg_phiprechg_agg_result_bit_write_assign_reg_104pp0_it11_assign_proc : process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if ((((ap_const_logic_1 = ap_ce) and not((tmp_3_reg_232 = ap_const_lv1_0)) and (ap_const_lv1_0 = tmp_26_1_reg_236)) or ((ap_const_logic_1 = ap_ce) and not((tmp_3_reg_232 = ap_const_lv1_0)) and not((ap_const_lv1_0 = tmp_26_1_reg_236)) and not((ap_const_lv1_0 = tmp_28_1_reg_240))))) then ap_reg_phiprechg_agg_result_bit_write_assign_reg_104pp0_it11 <= ap_reg_ppstg_r_bit_read_reg_200_pp0_it9; elsif ((ap_const_logic_1 = ap_ce)) then ap_reg_phiprechg_agg_result_bit_write_assign_reg_104pp0_it11 <= ap_reg_phiprechg_agg_result_bit_write_assign_reg_104pp0_it10; end if; end if; end process; -- ap_reg_phiprechg_agg_result_bucket_index_write_assign_reg_87pp0_it11 assign process. -- ap_reg_phiprechg_agg_result_bucket_index_write_assign_reg_87pp0_it11_assign_proc : process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if ((((ap_const_logic_1 = ap_ce) and not((tmp_3_reg_232 = ap_const_lv1_0)) and (ap_const_lv1_0 = tmp_26_1_reg_236)) or ((ap_const_logic_1 = ap_ce) and not((tmp_3_reg_232 = ap_const_lv1_0)) and not((ap_const_lv1_0 = tmp_26_1_reg_236)) and not((ap_const_lv1_0 = tmp_28_1_reg_240))))) then ap_reg_phiprechg_agg_result_bucket_index_write_assign_reg_87pp0_it11 <= ap_const_lv2_2; elsif ((ap_const_logic_1 = ap_ce)) then ap_reg_phiprechg_agg_result_bucket_index_write_assign_reg_87pp0_it11 <= ap_reg_phiprechg_agg_result_bucket_index_write_assign_reg_87pp0_it10; end if; end if; end process; -- ap_reg_phiprechg_agg_result_bucket_write_assign_reg_54pp0_it11 assign process. -- ap_reg_phiprechg_agg_result_bucket_write_assign_reg_54pp0_it11_assign_proc : process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if ((ap_const_logic_1 = ap_ce)) then if (ap_sig_bdd_143) then ap_reg_phiprechg_agg_result_bucket_write_assign_reg_54pp0_it11 <= ap_reg_ppstg_p_read_1_reg_206_pp0_it9; elsif (ap_sig_bdd_139) then ap_reg_phiprechg_agg_result_bucket_write_assign_reg_54pp0_it11 <= ap_const_lv32_0; elsif ((ap_true = ap_true)) then ap_reg_phiprechg_agg_result_bucket_write_assign_reg_54pp0_it11 <= ap_reg_phiprechg_agg_result_bucket_write_assign_reg_54pp0_it10; end if; end if; end if; end process; -- ap_reg_phiprechg_agg_result_end_write_assign_reg_69pp0_it11 assign process. -- ap_reg_phiprechg_agg_result_end_write_assign_reg_69pp0_it11_assign_proc : process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then end if; end process; -- assign process. -- process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if ((ap_const_logic_1 = ap_ce)) then ap_reg_ppstg_bus_assign_reg_225_pp0_it10 <= ap_reg_ppstg_bus_assign_reg_225_pp0_it9; ap_reg_ppstg_bus_assign_reg_225_pp0_it9 <= bus_assign_reg_225; ap_reg_ppstg_p_read_1_reg_206_pp0_it1 <= p_read_1_reg_206; ap_reg_ppstg_p_read_1_reg_206_pp0_it10 <= ap_reg_ppstg_p_read_1_reg_206_pp0_it9; ap_reg_ppstg_p_read_1_reg_206_pp0_it2 <= ap_reg_ppstg_p_read_1_reg_206_pp0_it1; ap_reg_ppstg_p_read_1_reg_206_pp0_it3 <= ap_reg_ppstg_p_read_1_reg_206_pp0_it2; ap_reg_ppstg_p_read_1_reg_206_pp0_it4 <= ap_reg_ppstg_p_read_1_reg_206_pp0_it3; ap_reg_ppstg_p_read_1_reg_206_pp0_it5 <= ap_reg_ppstg_p_read_1_reg_206_pp0_it4; ap_reg_ppstg_p_read_1_reg_206_pp0_it6 <= ap_reg_ppstg_p_read_1_reg_206_pp0_it5; ap_reg_ppstg_p_read_1_reg_206_pp0_it7 <= ap_reg_ppstg_p_read_1_reg_206_pp0_it6; ap_reg_ppstg_p_read_1_reg_206_pp0_it8 <= ap_reg_ppstg_p_read_1_reg_206_pp0_it7; ap_reg_ppstg_p_read_1_reg_206_pp0_it9 <= ap_reg_ppstg_p_read_1_reg_206_pp0_it8; ap_reg_ppstg_r_bit_read_reg_200_pp0_it1 <= r_bit_read_reg_200; ap_reg_ppstg_r_bit_read_reg_200_pp0_it2 <= ap_reg_ppstg_r_bit_read_reg_200_pp0_it1; ap_reg_ppstg_r_bit_read_reg_200_pp0_it3 <= ap_reg_ppstg_r_bit_read_reg_200_pp0_it2; ap_reg_ppstg_r_bit_read_reg_200_pp0_it4 <= ap_reg_ppstg_r_bit_read_reg_200_pp0_it3; ap_reg_ppstg_r_bit_read_reg_200_pp0_it5 <= ap_reg_ppstg_r_bit_read_reg_200_pp0_it4; ap_reg_ppstg_r_bit_read_reg_200_pp0_it6 <= ap_reg_ppstg_r_bit_read_reg_200_pp0_it5; ap_reg_ppstg_r_bit_read_reg_200_pp0_it7 <= ap_reg_ppstg_r_bit_read_reg_200_pp0_it6; ap_reg_ppstg_r_bit_read_reg_200_pp0_it8 <= ap_reg_ppstg_r_bit_read_reg_200_pp0_it7; ap_reg_ppstg_r_bit_read_reg_200_pp0_it9 <= ap_reg_ppstg_r_bit_read_reg_200_pp0_it8; ap_reg_ppstg_r_bucket_read_reg_194_pp0_it1 <= r_bucket_read_reg_194; ap_reg_ppstg_r_bucket_read_reg_194_pp0_it2 <= ap_reg_ppstg_r_bucket_read_reg_194_pp0_it1; ap_reg_ppstg_r_bucket_read_reg_194_pp0_it3 <= ap_reg_ppstg_r_bucket_read_reg_194_pp0_it2; ap_reg_ppstg_r_bucket_read_reg_194_pp0_it4 <= ap_reg_ppstg_r_bucket_read_reg_194_pp0_it3; ap_reg_ppstg_r_bucket_read_reg_194_pp0_it5 <= ap_reg_ppstg_r_bucket_read_reg_194_pp0_it4; ap_reg_ppstg_r_bucket_read_reg_194_pp0_it6 <= ap_reg_ppstg_r_bucket_read_reg_194_pp0_it5; ap_reg_ppstg_r_bucket_read_reg_194_pp0_it7 <= ap_reg_ppstg_r_bucket_read_reg_194_pp0_it6; ap_reg_ppstg_tmp_26_1_reg_236_pp0_it10 <= tmp_26_1_reg_236; ap_reg_ppstg_tmp_28_1_reg_240_pp0_it10 <= tmp_28_1_reg_240; ap_reg_ppstg_tmp_3_reg_232_pp0_it10 <= tmp_3_reg_232; ap_reg_ppstg_tmp_reg_214_pp0_it1 <= tmp_reg_214; ap_reg_ppstg_tmp_reg_214_pp0_it10 <= ap_reg_ppstg_tmp_reg_214_pp0_it9; ap_reg_ppstg_tmp_reg_214_pp0_it2 <= ap_reg_ppstg_tmp_reg_214_pp0_it1; ap_reg_ppstg_tmp_reg_214_pp0_it3 <= ap_reg_ppstg_tmp_reg_214_pp0_it2; ap_reg_ppstg_tmp_reg_214_pp0_it4 <= ap_reg_ppstg_tmp_reg_214_pp0_it3; ap_reg_ppstg_tmp_reg_214_pp0_it5 <= ap_reg_ppstg_tmp_reg_214_pp0_it4; ap_reg_ppstg_tmp_reg_214_pp0_it6 <= ap_reg_ppstg_tmp_reg_214_pp0_it5; ap_reg_ppstg_tmp_reg_214_pp0_it7 <= ap_reg_ppstg_tmp_reg_214_pp0_it6; ap_reg_ppstg_tmp_reg_214_pp0_it8 <= ap_reg_ppstg_tmp_reg_214_pp0_it7; ap_reg_ppstg_tmp_reg_214_pp0_it9 <= ap_reg_ppstg_tmp_reg_214_pp0_it8; bus_assign_reg_225 <= bus_assign_fu_137_p2; p_read_1_reg_206 <= p_read; r_bit_read_reg_200 <= r_bit; r_bucket_read_reg_194 <= r_bucket; tmp_1_reg_220 <= grp_fu_131_p2; tmp_3_reg_232 <= tmp_3_fu_141_p2; tmp_reg_214 <= tmp_fu_127_p1; end if; end if; end process; -- assign process. -- process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if ((((ap_const_logic_1 = ap_ce) and (tmp_3_reg_232 = ap_const_lv1_0)) or ((ap_const_logic_1 = ap_ce) and not((tmp_3_reg_232 = ap_const_lv1_0)) and not((ap_const_lv1_0 = tmp_26_1_reg_236)) and (ap_const_lv1_0 = tmp_28_1_reg_240)))) then reg_123 <= grp_p_bsf32_hw_fu_118_ap_return; end if; end if; end process; -- assign process. -- process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((ap_const_logic_1 = ap_ce) and not((ap_const_lv1_0 = tmp_3_fu_141_p2)))) then tmp_26_1_reg_236 <= tmp_26_1_fu_146_p2; end if; end if; end process; -- assign process. -- process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((ap_const_logic_1 = ap_ce) and not((ap_const_lv1_0 = tmp_3_fu_141_p2)) and not((ap_const_lv1_0 = tmp_26_1_fu_146_p2)))) then tmp_28_1_reg_240 <= tmp_28_1_fu_151_p2; end if; end if; end process; ap_reg_phiprechg_agg_result_end_write_assign_reg_69pp0_it11(0) <= '1'; -- agg_result_bit_write_assign_phi_fu_107_p8 assign process. -- agg_result_bit_write_assign_phi_fu_107_p8_assign_proc : process(ap_reg_ppstg_tmp_3_reg_232_pp0_it10, ap_reg_ppstg_tmp_26_1_reg_236_pp0_it10, ap_reg_ppstg_tmp_28_1_reg_240_pp0_it10, agg_result_bit_write_assign_trunc3_ext_fu_161_p1, ap_reg_phiprechg_agg_result_bit_write_assign_reg_104pp0_it11, agg_result_bit_write_assign_trunc_ext_fu_156_p1) begin if ((ap_const_lv1_0 = ap_reg_ppstg_tmp_3_reg_232_pp0_it10)) then agg_result_bit_write_assign_phi_fu_107_p8 <= agg_result_bit_write_assign_trunc_ext_fu_156_p1; elsif ((not((ap_const_lv1_0 = ap_reg_ppstg_tmp_3_reg_232_pp0_it10)) and not((ap_const_lv1_0 = ap_reg_ppstg_tmp_26_1_reg_236_pp0_it10)) and (ap_const_lv1_0 = ap_reg_ppstg_tmp_28_1_reg_240_pp0_it10))) then agg_result_bit_write_assign_phi_fu_107_p8 <= agg_result_bit_write_assign_trunc3_ext_fu_161_p1; else agg_result_bit_write_assign_phi_fu_107_p8 <= ap_reg_phiprechg_agg_result_bit_write_assign_reg_104pp0_it11; end if; end process; agg_result_bit_write_assign_trunc3_ext_fu_161_p1 <= std_logic_vector(resize(unsigned(reg_123),8)); agg_result_bit_write_assign_trunc_ext_fu_156_p1 <= std_logic_vector(resize(unsigned(reg_123),8)); agg_result_bucket_index_write_assign_cast_fu_166_p1 <= std_logic_vector(resize(unsigned(agg_result_bucket_index_write_assign_phi_fu_91_p8),8)); -- agg_result_bucket_index_write_assign_phi_fu_91_p8 assign process. -- agg_result_bucket_index_write_assign_phi_fu_91_p8_assign_proc : process(ap_reg_ppstg_tmp_reg_214_pp0_it10, ap_reg_ppstg_tmp_3_reg_232_pp0_it10, ap_reg_ppstg_tmp_26_1_reg_236_pp0_it10, ap_reg_ppstg_tmp_28_1_reg_240_pp0_it10, ap_reg_phiprechg_agg_result_bucket_index_write_assign_reg_87pp0_it11) begin if ((ap_const_lv1_0 = ap_reg_ppstg_tmp_3_reg_232_pp0_it10)) then agg_result_bucket_index_write_assign_phi_fu_91_p8 <= ap_reg_ppstg_tmp_reg_214_pp0_it10; elsif ((not((ap_const_lv1_0 = ap_reg_ppstg_tmp_3_reg_232_pp0_it10)) and not((ap_const_lv1_0 = ap_reg_ppstg_tmp_26_1_reg_236_pp0_it10)) and (ap_const_lv1_0 = ap_reg_ppstg_tmp_28_1_reg_240_pp0_it10))) then agg_result_bucket_index_write_assign_phi_fu_91_p8 <= ap_const_lv2_1; else agg_result_bucket_index_write_assign_phi_fu_91_p8 <= ap_reg_phiprechg_agg_result_bucket_index_write_assign_reg_87pp0_it11; end if; end process; -- agg_result_bucket_write_assign_phi_fu_58_p8 assign process. -- agg_result_bucket_write_assign_phi_fu_58_p8_assign_proc : process(ap_reg_ppstg_p_read_1_reg_206_pp0_it10, ap_reg_ppstg_bus_assign_reg_225_pp0_it10, ap_reg_ppstg_tmp_3_reg_232_pp0_it10, ap_reg_ppstg_tmp_26_1_reg_236_pp0_it10, ap_reg_ppstg_tmp_28_1_reg_240_pp0_it10, ap_reg_phiprechg_agg_result_bucket_write_assign_reg_54pp0_it11) begin if ((ap_const_lv1_0 = ap_reg_ppstg_tmp_3_reg_232_pp0_it10)) then agg_result_bucket_write_assign_phi_fu_58_p8 <= ap_reg_ppstg_bus_assign_reg_225_pp0_it10; elsif ((not((ap_const_lv1_0 = ap_reg_ppstg_tmp_3_reg_232_pp0_it10)) and not((ap_const_lv1_0 = ap_reg_ppstg_tmp_26_1_reg_236_pp0_it10)) and (ap_const_lv1_0 = ap_reg_ppstg_tmp_28_1_reg_240_pp0_it10))) then agg_result_bucket_write_assign_phi_fu_58_p8 <= ap_reg_ppstg_p_read_1_reg_206_pp0_it10; else agg_result_bucket_write_assign_phi_fu_58_p8 <= ap_reg_phiprechg_agg_result_bucket_write_assign_reg_54pp0_it11; end if; end process; -- agg_result_end_write_assign_phi_fu_73_p8 assign process. -- agg_result_end_write_assign_phi_fu_73_p8_assign_proc : process(ap_reg_ppstg_tmp_3_reg_232_pp0_it10, ap_reg_ppstg_tmp_26_1_reg_236_pp0_it10, ap_reg_ppstg_tmp_28_1_reg_240_pp0_it10, ap_reg_phiprechg_agg_result_end_write_assign_reg_69pp0_it11) begin if (((ap_const_lv1_0 = ap_reg_ppstg_tmp_3_reg_232_pp0_it10) or (not((ap_const_lv1_0 = ap_reg_ppstg_tmp_3_reg_232_pp0_it10)) and not((ap_const_lv1_0 = ap_reg_ppstg_tmp_26_1_reg_236_pp0_it10)) and (ap_const_lv1_0 = ap_reg_ppstg_tmp_28_1_reg_240_pp0_it10)))) then agg_result_end_write_assign_phi_fu_73_p8 <= ap_const_lv1_0; else agg_result_end_write_assign_phi_fu_73_p8 <= ap_reg_phiprechg_agg_result_end_write_assign_reg_69pp0_it11; end if; end process; ap_reg_phiprechg_agg_result_bit_write_assign_reg_104pp0_it10 <= ap_const_lv8_1; ap_reg_phiprechg_agg_result_bucket_index_write_assign_reg_87pp0_it10 <= ap_const_lv2_1; ap_reg_phiprechg_agg_result_bucket_write_assign_reg_54pp0_it10 <= ap_const_lv32_1; ap_reg_phiprechg_agg_result_end_write_assign_reg_69pp0_it10 <= ap_const_lv1_1; ap_return_0 <= agg_result_bit_write_assign_phi_fu_107_p8; ap_return_1 <= agg_result_bucket_index_write_assign_cast_fu_166_p1; ap_return_2 <= agg_result_bucket_write_assign_phi_fu_58_p8; ap_return_3 <= agg_result_end_write_assign_phi_fu_73_p8; -- ap_sig_bdd_139 assign process. -- ap_sig_bdd_139_assign_proc : process(tmp_3_reg_232, tmp_26_1_reg_236) begin ap_sig_bdd_139 <= (not((tmp_3_reg_232 = ap_const_lv1_0)) and (ap_const_lv1_0 = tmp_26_1_reg_236)); end process; -- ap_sig_bdd_143 assign process. -- ap_sig_bdd_143_assign_proc : process(tmp_3_reg_232, tmp_26_1_reg_236, tmp_28_1_reg_240) begin ap_sig_bdd_143 <= (not((tmp_3_reg_232 = ap_const_lv1_0)) and not((ap_const_lv1_0 = tmp_26_1_reg_236)) and not((ap_const_lv1_0 = tmp_28_1_reg_240))); end process; bus_assign_fu_137_p2 <= (tmp_1_reg_220 and ap_reg_ppstg_r_bucket_read_reg_194_pp0_it7); -- grp_fu_131_ce assign process. -- grp_fu_131_ce_assign_proc : process(ap_ce) begin if (not((ap_const_logic_1 = ap_ce))) then grp_fu_131_ce <= ap_const_logic_0; else grp_fu_131_ce <= ap_const_logic_1; end if; end process; grp_fu_131_p0 <= r_bucket; grp_fu_131_p1 <= ap_const_lv32_FFFFFFFF; -- grp_p_bsf32_hw_fu_118_ap_ce assign process. -- grp_p_bsf32_hw_fu_118_ap_ce_assign_proc : process(ap_ce, tmp_3_reg_232, tmp_26_1_reg_236, tmp_28_1_reg_240, tmp_3_fu_141_p2, tmp_26_1_fu_146_p2, tmp_28_1_fu_151_p2) begin if (((ap_const_logic_1 = ap_ce) and ((tmp_3_reg_232 = ap_const_lv1_0) or (not((tmp_3_reg_232 = ap_const_lv1_0)) and not((ap_const_lv1_0 = tmp_26_1_reg_236)) and (ap_const_lv1_0 = tmp_28_1_reg_240)) or (ap_const_lv1_0 = tmp_3_fu_141_p2) or (not((ap_const_lv1_0 = tmp_3_fu_141_p2)) and not((ap_const_lv1_0 = tmp_26_1_fu_146_p2)) and (ap_const_lv1_0 = tmp_28_1_fu_151_p2))))) then grp_p_bsf32_hw_fu_118_ap_ce <= ap_const_logic_1; else grp_p_bsf32_hw_fu_118_ap_ce <= ap_const_logic_0; end if; end process; -- grp_p_bsf32_hw_fu_118_bus_r assign process. -- grp_p_bsf32_hw_fu_118_bus_r_assign_proc : process(ap_reg_ppstg_p_read_1_reg_206_pp0_it8, bus_assign_reg_225, tmp_3_fu_141_p2, tmp_26_1_fu_146_p2, tmp_28_1_fu_151_p2) begin if ((not((ap_const_lv1_0 = tmp_3_fu_141_p2)) and not((ap_const_lv1_0 = tmp_26_1_fu_146_p2)) and (ap_const_lv1_0 = tmp_28_1_fu_151_p2))) then grp_p_bsf32_hw_fu_118_bus_r <= ap_reg_ppstg_p_read_1_reg_206_pp0_it8; elsif ((ap_const_lv1_0 = tmp_3_fu_141_p2)) then grp_p_bsf32_hw_fu_118_bus_r <= bus_assign_reg_225; else grp_p_bsf32_hw_fu_118_bus_r <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX"; end if; end process; tmp_26_1_fu_146_p2 <= "1" when (ap_reg_ppstg_tmp_reg_214_pp0_it8 = ap_const_lv2_0) else "0"; tmp_28_1_fu_151_p2 <= "1" when (ap_reg_ppstg_p_read_1_reg_206_pp0_it8 = ap_const_lv32_0) else "0"; tmp_3_fu_141_p2 <= "1" when (bus_assign_reg_225 = ap_const_lv32_0) else "0"; tmp_fu_127_p1 <= r_bucket_index(2 - 1 downto 0); end behav;
lgpl-3.0
c77a5f3bb31d0eed4fbf90e527f0a1b5
0.629021
2.543853
false
false
false
false
jairov4/accel-oil
solution_spartan6/syn/vhdl/nfa_accept_samples_generic_hw_add_17ns_17s_17_4.vhd
3
9,502
-- ============================================================== -- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC -- Version: 2013.4 -- Copyright (C) 2013 Xilinx Inc. All rights reserved. -- -- ============================================================== library IEEE; use IEEE.std_logic_1164.all; use ieee.std_logic_arith.all; entity nfa_accept_samples_generic_hw_add_17ns_17s_17_4_AddSubnS_5 is port ( clk: in std_logic; reset: in std_logic; ce: in std_logic; a: in std_logic_vector(16 downto 0); b: in std_logic_vector(16 downto 0); s: out std_logic_vector(16 downto 0)); end entity; architecture behav of nfa_accept_samples_generic_hw_add_17ns_17s_17_4_AddSubnS_5 is component nfa_accept_samples_generic_hw_add_17ns_17s_17_4_AddSubnS_5_fadder is port ( faa : IN STD_LOGIC_VECTOR (5-1 downto 0); fab : IN STD_LOGIC_VECTOR (5-1 downto 0); facin : IN STD_LOGIC_VECTOR (0 downto 0); fas : OUT STD_LOGIC_VECTOR (5-1 downto 0); facout : OUT STD_LOGIC_VECTOR (0 downto 0)); end component; component nfa_accept_samples_generic_hw_add_17ns_17s_17_4_AddSubnS_5_fadder_f is port ( faa : IN STD_LOGIC_VECTOR (2-1 downto 0); fab : IN STD_LOGIC_VECTOR (2-1 downto 0); facin : IN STD_LOGIC_VECTOR (0 downto 0); fas : OUT STD_LOGIC_VECTOR (2-1 downto 0); facout : OUT STD_LOGIC_VECTOR (0 downto 0)); end component; -- ---- register and wire type variables list here ---- -- wire for the primary inputs signal a_reg : std_logic_vector(16 downto 0); signal b_reg : std_logic_vector(16 downto 0); -- wires for each small adder signal a0_cb : std_logic_vector(4 downto 0); signal b0_cb : std_logic_vector(4 downto 0); signal a1_cb : std_logic_vector(9 downto 5); signal b1_cb : std_logic_vector(9 downto 5); signal a2_cb : std_logic_vector(14 downto 10); signal b2_cb : std_logic_vector(14 downto 10); signal a3_cb : std_logic_vector(16 downto 15); signal b3_cb : std_logic_vector(16 downto 15); -- registers for input register array type ramtypei0 is array (0 downto 0) of std_logic_vector(4 downto 0); signal a1_cb_regi1 : ramtypei0; signal b1_cb_regi1 : ramtypei0; type ramtypei1 is array (1 downto 0) of std_logic_vector(4 downto 0); signal a2_cb_regi2 : ramtypei1; signal b2_cb_regi2 : ramtypei1; type ramtypei2 is array (2 downto 0) of std_logic_vector(1 downto 0); signal a3_cb_regi3 : ramtypei2; signal b3_cb_regi3 : ramtypei2; -- wires for each full adder sum signal fas : std_logic_vector(16 downto 0); -- wires and register for carry out bit signal faccout_ini : std_logic_vector (0 downto 0); signal faccout0_co0 : std_logic_vector (0 downto 0); signal faccout1_co1 : std_logic_vector (0 downto 0); signal faccout2_co2 : std_logic_vector (0 downto 0); signal faccout3_co3 : std_logic_vector (0 downto 0); signal faccout0_co0_reg : std_logic_vector (0 downto 0); signal faccout1_co1_reg : std_logic_vector (0 downto 0); signal faccout2_co2_reg : std_logic_vector (0 downto 0); -- registers for output register array type ramtypeo2 is array (2 downto 0) of std_logic_vector(4 downto 0); signal s0_ca_rego0 : ramtypeo2; type ramtypeo1 is array (1 downto 0) of std_logic_vector(4 downto 0); signal s1_ca_rego1 : ramtypeo1; type ramtypeo0 is array (0 downto 0) of std_logic_vector(4 downto 0); signal s2_ca_rego2 : ramtypeo0; -- wire for the temporary output signal s_tmp : std_logic_vector(16 downto 0); -- ---- RTL code for assignment statements/always blocks/module instantiations here ---- begin a_reg <= a; b_reg <= b; -- small adder input assigments a0_cb <= a_reg(4 downto 0); b0_cb <= b_reg(4 downto 0); a1_cb <= a_reg(9 downto 5); b1_cb <= b_reg(9 downto 5); a2_cb <= a_reg(14 downto 10); b2_cb <= b_reg(14 downto 10); a3_cb <= a_reg(16 downto 15); b3_cb <= b_reg(16 downto 15); -- input register array process (clk) begin if (clk'event and clk='1') then if (ce='1') then a1_cb_regi1 (0) <= a1_cb; b1_cb_regi1 (0) <= b1_cb; a2_cb_regi2 (0) <= a2_cb; b2_cb_regi2 (0) <= b2_cb; a3_cb_regi3 (0) <= a3_cb; b3_cb_regi3 (0) <= b3_cb; a2_cb_regi2 (1) <= a2_cb_regi2 (0); b2_cb_regi2 (1) <= b2_cb_regi2 (0); a3_cb_regi3 (1) <= a3_cb_regi3 (0); b3_cb_regi3 (1) <= b3_cb_regi3 (0); a3_cb_regi3 (2) <= a3_cb_regi3 (1); b3_cb_regi3 (2) <= b3_cb_regi3 (1); end if; end if; end process; -- carry out bit processing process (clk) begin if (clk'event and clk='1') then if (ce='1') then faccout0_co0_reg <= faccout0_co0; faccout1_co1_reg <= faccout1_co1; faccout2_co2_reg <= faccout2_co2; end if; end if; end process; -- small adder generation u0 : nfa_accept_samples_generic_hw_add_17ns_17s_17_4_AddSubnS_5_fadder port map (faa => a0_cb, fab => b0_cb, facin => faccout_ini, fas => fas(4 downto 0), facout => faccout0_co0); u1 : nfa_accept_samples_generic_hw_add_17ns_17s_17_4_AddSubnS_5_fadder port map (faa => a1_cb_regi1(0), fab => b1_cb_regi1(0), facin => faccout0_co0_reg, fas => fas(9 downto 5), facout => faccout1_co1); u2 : nfa_accept_samples_generic_hw_add_17ns_17s_17_4_AddSubnS_5_fadder port map (faa => a2_cb_regi2(1), fab => b2_cb_regi2(1), facin => faccout1_co1_reg, fas => fas(14 downto 10), facout => faccout2_co2); u3 : nfa_accept_samples_generic_hw_add_17ns_17s_17_4_AddSubnS_5_fadder_f port map (faa => a3_cb_regi3(2), fab => b3_cb_regi3(2), facin => faccout2_co2_reg, fas => fas(16 downto 15), facout => faccout3_co3); faccout_ini <= "0"; -- output register array process (clk) begin if (clk'event and clk='1') then if (ce='1') then s0_ca_rego0 (0) <= fas(4 downto 0); s1_ca_rego1 (0) <= fas(9 downto 5); s2_ca_rego2 (0) <= fas(14 downto 10); s0_ca_rego0 (1) <= s0_ca_rego0 (0); s0_ca_rego0 (2) <= s0_ca_rego0 (1); s1_ca_rego1 (1) <= s1_ca_rego1 (0); end if; end if; end process; -- get the s_tmp, assign it to the primary output s_tmp(4 downto 0) <= s0_ca_rego0(2); s_tmp(9 downto 5) <= s1_ca_rego1(1); s_tmp(14 downto 10) <= s2_ca_rego2(0); s_tmp(16 downto 15) <= fas(16 downto 15); s <= s_tmp; end architecture; -- short adder library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; entity nfa_accept_samples_generic_hw_add_17ns_17s_17_4_AddSubnS_5_fadder is generic(N : natural :=5); port ( faa : IN STD_LOGIC_VECTOR (N-1 downto 0); fab : IN STD_LOGIC_VECTOR (N-1 downto 0); facin : IN STD_LOGIC_VECTOR (0 downto 0); fas : OUT STD_LOGIC_VECTOR (N-1 downto 0); facout : OUT STD_LOGIC_VECTOR (0 downto 0)); end; architecture behav of nfa_accept_samples_generic_hw_add_17ns_17s_17_4_AddSubnS_5_fadder is signal tmp : STD_LOGIC_VECTOR (N downto 0); begin tmp <= std_logic_vector(unsigned(std_logic_vector(unsigned(std_logic_vector(resize(unsigned(faa),N+1))) + unsigned(fab))) + unsigned(facin)); fas <= tmp(N-1 downto 0 ); facout <= tmp(N downto N); end behav; -- the final stage short adder library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; entity nfa_accept_samples_generic_hw_add_17ns_17s_17_4_AddSubnS_5_fadder_f is generic(N : natural :=2); port ( faa : IN STD_LOGIC_VECTOR (N-1 downto 0); fab : IN STD_LOGIC_VECTOR (N-1 downto 0); facin : IN STD_LOGIC_VECTOR (0 downto 0); fas : OUT STD_LOGIC_VECTOR (N-1 downto 0); facout : OUT STD_LOGIC_VECTOR (0 downto 0)); end; architecture behav of nfa_accept_samples_generic_hw_add_17ns_17s_17_4_AddSubnS_5_fadder_f is signal tmp : STD_LOGIC_VECTOR (N downto 0); begin tmp <= std_logic_vector(unsigned(std_logic_vector(unsigned(std_logic_vector(resize(unsigned(faa),N+1))) + unsigned(fab))) + unsigned(facin)); fas <= tmp(N-1 downto 0 ); facout <= tmp(N downto N); end behav; Library IEEE; use IEEE.std_logic_1164.all; entity nfa_accept_samples_generic_hw_add_17ns_17s_17_4 is generic ( ID : INTEGER; NUM_STAGE : INTEGER; din0_WIDTH : INTEGER; din1_WIDTH : INTEGER; dout_WIDTH : INTEGER); port ( clk : IN STD_LOGIC; reset : IN STD_LOGIC; ce : IN STD_LOGIC; din0 : IN STD_LOGIC_VECTOR(din0_WIDTH - 1 DOWNTO 0); din1 : IN STD_LOGIC_VECTOR(din1_WIDTH - 1 DOWNTO 0); dout : OUT STD_LOGIC_VECTOR(dout_WIDTH - 1 DOWNTO 0)); end entity; architecture arch of nfa_accept_samples_generic_hw_add_17ns_17s_17_4 is component nfa_accept_samples_generic_hw_add_17ns_17s_17_4_AddSubnS_5 is port ( clk : IN STD_LOGIC; reset : IN STD_LOGIC; ce : IN STD_LOGIC; a : IN STD_LOGIC_VECTOR; b : IN STD_LOGIC_VECTOR; s : OUT STD_LOGIC_VECTOR); end component; begin nfa_accept_samples_generic_hw_add_17ns_17s_17_4_AddSubnS_5_U : component nfa_accept_samples_generic_hw_add_17ns_17s_17_4_AddSubnS_5 port map ( clk => clk, reset => reset, ce => ce, a => din0, b => din1, s => dout); end architecture;
lgpl-3.0
f271de654c2cb1461534656757cc70af
0.608293
2.864637
false
false
false
false
grwlf/vsim
vhdl_ct/ct00057.vhd
1
3,182
-- NEED RESULT: ARCH00057.P1: Loop statement without an iteration scheme may be left by a next statement passed -- NEED RESULT: ARCH00057.P2: Loop statement without an iteration scheme may be left by a exit statement passed -- NEED RESULT: ARCH00057.P3: Loop statement without an iteration scheme may be left by a return statement passed ------------------------------------------------------------------------------- -- -- Copyright (c) 1989 by Intermetrics, Inc. -- All rights reserved. -- ------------------------------------------------------------------------------- -- -- TEST NAME: -- -- CT00057 -- -- AUTHOR: -- -- G. Tominovich -- -- TEST OBJECTIVES: -- -- 8.8 (2) -- -- DESIGN UNIT ORDERING: -- -- E00000(ARCH00057) -- ENT00057_Test_Bench(ARCH00057_Test_Bench) -- -- REVISION HISTORY: -- -- 02-JUL-1987 - initial revision -- -- NOTES: -- -- self-checking -- automatically generated -- use WORK.STANDARD_TYPES.all ; architecture ARCH00057 of E00000 is signal Dummy : Boolean := false ; begin P1 : process ( Dummy ) variable correct : boolean := true ; procedure Proc ( variable parm : inout boolean ) is variable more : boolean := true ; begin L0 : while more loop more := false ; L1 : loop next L0 ; parm := false ; end loop L1 ; end loop L0 ; end Proc ; -- begin Proc (correct) ; test_report ( "ARCH00057.P1" , "Loop statement without an iteration scheme " & "may be left by a " & "next statement", correct ) ; -- end process P1 ; -- P2 : process ( Dummy ) variable correct : boolean := true ; procedure Proc ( variable parm : inout boolean ) is begin L1 : loop exit ; parm := false ; end loop L1 ; end Proc ; -- begin Proc (correct) ; test_report ( "ARCH00057.P2" , "Loop statement without an iteration scheme " & "may be left by a " & "exit statement", correct ) ; -- end process P2 ; -- P3 : process ( Dummy ) variable correct : boolean := true ; procedure Proc ( variable parm : inout boolean ) is begin L1 : loop return ; parm := false ; end loop L1 ; end Proc ; -- begin Proc (correct) ; test_report ( "ARCH00057.P3" , "Loop statement without an iteration scheme " & "may be left by a " & "return statement", correct ) ; -- end process P3 ; -- -- end ARCH00057 ; -- entity ENT00057_Test_Bench is end ENT00057_Test_Bench ; -- architecture ARCH00057_Test_Bench of ENT00057_Test_Bench is begin L1: block component UUT end component ; for CIS1 : UUT use entity WORK.E00000 ( ARCH00057 ) ; begin CIS1 : UUT ; end block L1 ; end ARCH00057_Test_Bench ;
gpl-3.0
9e6a6eda984e155e41510e943fd24ab1
0.500314
4.022756
false
true
false
false
TWW12/lzw
final_project_sim/lzw/lzw.srcs/sources_1/ip/bram_4096/bram_4096_sim_netlist.vhdl
1
83,476
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved. -- -------------------------------------------------------------------------------- -- Tool Version: Vivado v.2016.4 (win64) Build 1756540 Mon Jan 23 19:11:23 MST 2017 -- Date : Tue Apr 18 23:15:20 2017 -- Host : DESKTOP-I9J3TQJ running 64-bit major release (build 9200) -- Command : write_vhdl -force -mode funcsim -- X:/final_project_sim/lzw/lzw.srcs/sources_1/ip/bram_4096/bram_4096_sim_netlist.vhdl -- Design : bram_4096 -- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or -- synthesized. This netlist cannot be used for SDF annotated simulation. -- Device : xc7z020clg484-1 -- -------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity bram_4096_blk_mem_gen_prim_wrapper_init is port ( DOADO : out STD_LOGIC_VECTOR ( 3 downto 0 ); clka : in STD_LOGIC; ena : in STD_LOGIC; addra : in STD_LOGIC_VECTOR ( 11 downto 0 ); dina : in STD_LOGIC_VECTOR ( 3 downto 0 ); wea : in STD_LOGIC_VECTOR ( 0 to 0 ) ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of bram_4096_blk_mem_gen_prim_wrapper_init : entity is "blk_mem_gen_prim_wrapper_init"; end bram_4096_blk_mem_gen_prim_wrapper_init; architecture STRUCTURE of bram_4096_blk_mem_gen_prim_wrapper_init is signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 15 downto 4 ); signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 15 downto 0 ); signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 ); signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 ); attribute CLOCK_DOMAINS : string; attribute CLOCK_DOMAINS of \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram\ : label is "COMMON"; attribute box_type : string; attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram\ : label is "PRIMITIVE"; begin \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram\: unisim.vcomponents.RAMB18E1 generic map( DOA_REG => 1, DOB_REG => 0, INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_00 => X"0FEDCBA9876543210FEDCBA9876543210FEDCBA9876543210FEDCBA987654321", INIT_01 => X"0FEDCBA9876543210FEDCBA9876543210FEDCBA9876543210FEDCBA987654321", INIT_02 => X"0FEDCBA9876543210FEDCBA9876543210FEDCBA9876543210FEDCBA987654321", INIT_03 => X"0FEDCBA9876543210FEDCBA9876543210FEDCBA9876543210FEDCBA987654321", INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_A => X"00000", INIT_B => X"00000", INIT_FILE => "NONE", IS_CLKARDCLK_INVERTED => '0', IS_CLKBWRCLK_INVERTED => '0', IS_ENARDEN_INVERTED => '0', IS_ENBWREN_INVERTED => '0', IS_RSTRAMARSTRAM_INVERTED => '0', IS_RSTRAMB_INVERTED => '0', IS_RSTREGARSTREG_INVERTED => '0', IS_RSTREGB_INVERTED => '0', RAM_MODE => "TDP", RDADDR_COLLISION_HWCONFIG => "PERFORMANCE", READ_WIDTH_A => 4, READ_WIDTH_B => 4, RSTREG_PRIORITY_A => "REGCE", RSTREG_PRIORITY_B => "REGCE", SIM_COLLISION_CHECK => "ALL", SIM_DEVICE => "7SERIES", SRVAL_A => X"00000", SRVAL_B => X"00000", WRITE_MODE_A => "WRITE_FIRST", WRITE_MODE_B => "WRITE_FIRST", WRITE_WIDTH_A => 4, WRITE_WIDTH_B => 4 ) port map ( ADDRARDADDR(13 downto 2) => addra(11 downto 0), ADDRARDADDR(1 downto 0) => B"00", ADDRBWRADDR(13 downto 0) => B"00000000000000", CLKARDCLK => clka, CLKBWRCLK => clka, DIADI(15 downto 4) => B"000000000000", DIADI(3 downto 0) => dina(3 downto 0), DIBDI(15 downto 0) => B"0000000000000000", DIPADIP(1 downto 0) => B"00", DIPBDIP(1 downto 0) => B"00", DOADO(15 downto 4) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_DOADO_UNCONNECTED\(15 downto 4), DOADO(3 downto 0) => DOADO(3 downto 0), DOBDO(15 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_DOBDO_UNCONNECTED\(15 downto 0), DOPADOP(1 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_DOPADOP_UNCONNECTED\(1 downto 0), DOPBDOP(1 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_DOPBDOP_UNCONNECTED\(1 downto 0), ENARDEN => ena, ENBWREN => '0', REGCEAREGCE => ena, REGCEB => '0', RSTRAMARSTRAM => '0', RSTRAMB => '0', RSTREGARSTREG => '0', RSTREGB => '0', WEA(1) => wea(0), WEA(0) => wea(0), WEBWE(3 downto 0) => B"0000" ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity \bram_4096_blk_mem_gen_prim_wrapper_init__parameterized0\ is port ( douta_array : out STD_LOGIC_VECTOR ( 8 downto 0 ); clka : in STD_LOGIC; ena : in STD_LOGIC; addra : in STD_LOGIC_VECTOR ( 11 downto 0 ); dina : in STD_LOGIC_VECTOR ( 8 downto 0 ); wea : in STD_LOGIC_VECTOR ( 0 to 0 ) ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of \bram_4096_blk_mem_gen_prim_wrapper_init__parameterized0\ : entity is "blk_mem_gen_prim_wrapper_init"; end \bram_4096_blk_mem_gen_prim_wrapper_init__parameterized0\; architecture STRUCTURE of \bram_4096_blk_mem_gen_prim_wrapper_init__parameterized0\ is signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC; signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC; signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\ : STD_LOGIC; signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\ : STD_LOGIC; signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 8 ); signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 ); signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 ); signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 ); signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 ); attribute CLOCK_DOMAINS : string; attribute CLOCK_DOMAINS of \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\ : label is "COMMON"; attribute box_type : string; attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\ : label is "PRIMITIVE"; begin \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\: unisim.vcomponents.RAMB36E1 generic map( DOA_REG => 1, DOB_REG => 0, EN_ECC_READ => false, EN_ECC_WRITE => false, INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_0A => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_00 => X"0201010101010101010101010101010101000000000000000000000000000000", INIT_01 => X"0403030303030303030303030303030303020202020202020202020202020202", INIT_02 => X"0605050505050505050505050505050505040404040404040404040404040404", INIT_03 => X"0807070707070707070707070707070707060606060606060606060606060606", INIT_04 => X"0A09090909090909090909090909090909080808080808080808080808080808", INIT_05 => X"0C0B0B0B0B0B0B0B0B0B0B0B0B0B0B0B0B0A0A0A0A0A0A0A0A0A0A0A0A0A0A0A", INIT_06 => X"0E0D0D0D0D0D0D0D0D0D0D0D0D0D0D0D0D0C0C0C0C0C0C0C0C0C0C0C0C0C0C0C", INIT_07 => X"000F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E", INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_40 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_41 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_42 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_43 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_44 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_45 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_46 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_47 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_48 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_49 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_4A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_4B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_4C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_4D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_4E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_4F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_50 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_51 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_52 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_53 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_54 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_55 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_56 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_57 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_58 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_59 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_5A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_5B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_5C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_5D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_5E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_5F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_60 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_61 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_62 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_63 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_64 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_65 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_66 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_67 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_68 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_69 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_6A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_6B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_6D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_6E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_6F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_70 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_71 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_72 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_73 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_74 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_A => X"000000000", INIT_B => X"000000000", INIT_FILE => "NONE", IS_CLKARDCLK_INVERTED => '0', IS_CLKBWRCLK_INVERTED => '0', IS_ENARDEN_INVERTED => '0', IS_ENBWREN_INVERTED => '0', IS_RSTRAMARSTRAM_INVERTED => '0', IS_RSTRAMB_INVERTED => '0', IS_RSTREGARSTREG_INVERTED => '0', IS_RSTREGB_INVERTED => '0', RAM_EXTENSION_A => "NONE", RAM_EXTENSION_B => "NONE", RAM_MODE => "TDP", RDADDR_COLLISION_HWCONFIG => "PERFORMANCE", READ_WIDTH_A => 9, READ_WIDTH_B => 9, RSTREG_PRIORITY_A => "REGCE", RSTREG_PRIORITY_B => "REGCE", SIM_COLLISION_CHECK => "ALL", SIM_DEVICE => "7SERIES", SRVAL_A => X"000000000", SRVAL_B => X"000000000", WRITE_MODE_A => "WRITE_FIRST", WRITE_MODE_B => "WRITE_FIRST", WRITE_WIDTH_A => 9, WRITE_WIDTH_B => 9 ) port map ( ADDRARDADDR(15) => '1', ADDRARDADDR(14 downto 3) => addra(11 downto 0), ADDRARDADDR(2 downto 0) => B"111", ADDRBWRADDR(15 downto 0) => B"0000000000000000", CASCADEINA => '0', CASCADEINB => '0', CASCADEOUTA => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\, CASCADEOUTB => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\, CLKARDCLK => clka, CLKBWRCLK => clka, DBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\, DIADI(31 downto 8) => B"000000000000000000000000", DIADI(7 downto 0) => dina(7 downto 0), DIBDI(31 downto 0) => B"00000000000000000000000000000000", DIPADIP(3 downto 1) => B"000", DIPADIP(0) => dina(8), DIPBDIP(3 downto 0) => B"0000", DOADO(31 downto 8) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\(31 downto 8), DOADO(7 downto 0) => douta_array(7 downto 0), DOBDO(31 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\(31 downto 0), DOPADOP(3 downto 1) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\(3 downto 1), DOPADOP(0) => douta_array(8), DOPBDOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\(3 downto 0), ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\(7 downto 0), ENARDEN => ena, ENBWREN => '0', INJECTDBITERR => '0', INJECTSBITERR => '0', RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\(8 downto 0), REGCEAREGCE => ena, REGCEB => '0', RSTRAMARSTRAM => '0', RSTRAMB => '0', RSTREGARSTREG => '0', RSTREGB => '0', SBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\, WEA(3) => wea(0), WEA(2) => wea(0), WEA(1) => wea(0), WEA(0) => wea(0), WEBWE(7 downto 0) => B"00000000" ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity \bram_4096_blk_mem_gen_prim_wrapper_init__parameterized1\ is port ( DOADO : out STD_LOGIC_VECTOR ( 6 downto 0 ); clka : in STD_LOGIC; ena : in STD_LOGIC; addra : in STD_LOGIC_VECTOR ( 11 downto 0 ); dina : in STD_LOGIC_VECTOR ( 6 downto 0 ); wea : in STD_LOGIC_VECTOR ( 0 to 0 ) ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of \bram_4096_blk_mem_gen_prim_wrapper_init__parameterized1\ : entity is "blk_mem_gen_prim_wrapper_init"; end \bram_4096_blk_mem_gen_prim_wrapper_init__parameterized1\; architecture STRUCTURE of \bram_4096_blk_mem_gen_prim_wrapper_init__parameterized1\ is signal \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_45\ : STD_LOGIC; signal \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_88\ : STD_LOGIC; signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC; signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC; signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\ : STD_LOGIC; signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\ : STD_LOGIC; signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 8 ); signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 ); signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 ); signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 ); signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 ); attribute CLOCK_DOMAINS : string; attribute CLOCK_DOMAINS of \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\ : label is "COMMON"; attribute box_type : string; attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\ : label is "PRIMITIVE"; begin \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\: unisim.vcomponents.RAMB36E1 generic map( DOA_REG => 1, DOB_REG => 0, EN_ECC_READ => false, EN_ECC_WRITE => false, INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_04 => 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X"0000000000000000000000000000000000000000000000000000000000000000", INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_24 => 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X"0000000000000000000000000000000000000000000000000000000000000000", INIT_6D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_6E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_6F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_70 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_71 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_72 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_73 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_74 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_A => X"000000000", INIT_B => X"000000000", INIT_FILE => "NONE", IS_CLKARDCLK_INVERTED => '0', IS_CLKBWRCLK_INVERTED => '0', IS_ENARDEN_INVERTED => '0', IS_ENBWREN_INVERTED => '0', IS_RSTRAMARSTRAM_INVERTED => '0', IS_RSTRAMB_INVERTED => '0', IS_RSTREGARSTREG_INVERTED => '0', IS_RSTREGB_INVERTED => '0', RAM_EXTENSION_A => "NONE", RAM_EXTENSION_B => "NONE", RAM_MODE => "TDP", RDADDR_COLLISION_HWCONFIG => "PERFORMANCE", READ_WIDTH_A => 9, READ_WIDTH_B => 9, RSTREG_PRIORITY_A => "REGCE", RSTREG_PRIORITY_B => "REGCE", SIM_COLLISION_CHECK => "ALL", SIM_DEVICE => "7SERIES", SRVAL_A => X"000000000", SRVAL_B => X"000000000", WRITE_MODE_A => "WRITE_FIRST", WRITE_MODE_B => "WRITE_FIRST", WRITE_WIDTH_A => 9, WRITE_WIDTH_B => 9 ) port map ( ADDRARDADDR(15) => '1', ADDRARDADDR(14 downto 3) => addra(11 downto 0), ADDRARDADDR(2 downto 0) => B"111", ADDRBWRADDR(15 downto 0) => B"0000000000000000", CASCADEINA => '0', CASCADEINB => '0', CASCADEOUTA => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\, CASCADEOUTB => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\, CLKARDCLK => clka, CLKBWRCLK => clka, DBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\, DIADI(31 downto 7) => B"0000000000000000000000000", DIADI(6 downto 0) => dina(6 downto 0), DIBDI(31 downto 0) => B"00000000000000000000000000000000", DIPADIP(3 downto 0) => B"0000", DIPBDIP(3 downto 0) => B"0000", DOADO(31 downto 8) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\(31 downto 8), DOADO(7) => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_45\, DOADO(6 downto 0) => DOADO(6 downto 0), DOBDO(31 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\(31 downto 0), DOPADOP(3 downto 1) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\(3 downto 1), DOPADOP(0) => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_88\, DOPBDOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\(3 downto 0), ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\(7 downto 0), ENARDEN => ena, ENBWREN => '0', INJECTDBITERR => '0', INJECTSBITERR => '0', RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\(8 downto 0), REGCEAREGCE => ena, REGCEB => '0', RSTRAMARSTRAM => '0', RSTRAMB => '0', RSTREGARSTREG => '0', RSTREGB => '0', SBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\, WEA(3) => wea(0), WEA(2) => wea(0), WEA(1) => wea(0), WEA(0) => wea(0), WEBWE(7 downto 0) => B"00000000" ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity bram_4096_blk_mem_gen_prim_width is port ( DOADO : out STD_LOGIC_VECTOR ( 3 downto 0 ); clka : in STD_LOGIC; ena : in STD_LOGIC; addra : in STD_LOGIC_VECTOR ( 11 downto 0 ); dina : in STD_LOGIC_VECTOR ( 3 downto 0 ); wea : in STD_LOGIC_VECTOR ( 0 to 0 ) ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of bram_4096_blk_mem_gen_prim_width : entity is "blk_mem_gen_prim_width"; end bram_4096_blk_mem_gen_prim_width; architecture STRUCTURE of bram_4096_blk_mem_gen_prim_width is begin \prim_init.ram\: entity work.bram_4096_blk_mem_gen_prim_wrapper_init port map ( DOADO(3 downto 0) => DOADO(3 downto 0), addra(11 downto 0) => addra(11 downto 0), clka => clka, dina(3 downto 0) => dina(3 downto 0), ena => ena, wea(0) => wea(0) ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity \bram_4096_blk_mem_gen_prim_width__parameterized0\ is port ( douta_array : out STD_LOGIC_VECTOR ( 8 downto 0 ); clka : in STD_LOGIC; ena : in STD_LOGIC; addra : in STD_LOGIC_VECTOR ( 11 downto 0 ); dina : in STD_LOGIC_VECTOR ( 8 downto 0 ); wea : in STD_LOGIC_VECTOR ( 0 to 0 ) ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of \bram_4096_blk_mem_gen_prim_width__parameterized0\ : entity is "blk_mem_gen_prim_width"; end \bram_4096_blk_mem_gen_prim_width__parameterized0\; architecture STRUCTURE of \bram_4096_blk_mem_gen_prim_width__parameterized0\ is begin \prim_init.ram\: entity work.\bram_4096_blk_mem_gen_prim_wrapper_init__parameterized0\ port map ( addra(11 downto 0) => addra(11 downto 0), clka => clka, dina(8 downto 0) => dina(8 downto 0), douta_array(8 downto 0) => douta_array(8 downto 0), ena => ena, wea(0) => wea(0) ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity \bram_4096_blk_mem_gen_prim_width__parameterized1\ is port ( DOADO : out STD_LOGIC_VECTOR ( 6 downto 0 ); clka : in STD_LOGIC; ena : in STD_LOGIC; addra : in STD_LOGIC_VECTOR ( 11 downto 0 ); dina : in STD_LOGIC_VECTOR ( 6 downto 0 ); wea : in STD_LOGIC_VECTOR ( 0 to 0 ) ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of \bram_4096_blk_mem_gen_prim_width__parameterized1\ : entity is "blk_mem_gen_prim_width"; end \bram_4096_blk_mem_gen_prim_width__parameterized1\; architecture STRUCTURE of \bram_4096_blk_mem_gen_prim_width__parameterized1\ is begin \prim_init.ram\: entity work.\bram_4096_blk_mem_gen_prim_wrapper_init__parameterized1\ port map ( DOADO(6 downto 0) => DOADO(6 downto 0), addra(11 downto 0) => addra(11 downto 0), clka => clka, dina(6 downto 0) => dina(6 downto 0), ena => ena, wea(0) => wea(0) ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity bram_4096_blk_mem_gen_generic_cstr is port ( douta : out STD_LOGIC_VECTOR ( 19 downto 0 ); clka : in STD_LOGIC; ena : in STD_LOGIC; addra : in STD_LOGIC_VECTOR ( 11 downto 0 ); dina : in STD_LOGIC_VECTOR ( 19 downto 0 ); wea : in STD_LOGIC_VECTOR ( 0 to 0 ) ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of bram_4096_blk_mem_gen_generic_cstr : entity is "blk_mem_gen_generic_cstr"; end bram_4096_blk_mem_gen_generic_cstr; architecture STRUCTURE of bram_4096_blk_mem_gen_generic_cstr is signal douta_array : STD_LOGIC_VECTOR ( 19 downto 0 ); begin \mux_a_wire.mux_reg.ce_pri.douta_i_reg[0]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => clka, CE => ena, D => douta_array(0), Q => douta(0), R => '0' ); \mux_a_wire.mux_reg.ce_pri.douta_i_reg[10]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => clka, CE => ena, D => douta_array(10), Q => douta(10), R => '0' ); \mux_a_wire.mux_reg.ce_pri.douta_i_reg[11]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => clka, CE => ena, D => douta_array(11), Q => douta(11), R => '0' ); \mux_a_wire.mux_reg.ce_pri.douta_i_reg[12]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => clka, CE => ena, D => douta_array(12), Q => douta(12), R => '0' ); \mux_a_wire.mux_reg.ce_pri.douta_i_reg[13]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => clka, CE => ena, D => douta_array(13), Q => douta(13), R => '0' ); \mux_a_wire.mux_reg.ce_pri.douta_i_reg[14]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => clka, CE => ena, D => douta_array(14), Q => douta(14), R => '0' ); \mux_a_wire.mux_reg.ce_pri.douta_i_reg[15]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => clka, CE => ena, D => douta_array(15), Q => douta(15), R => '0' ); \mux_a_wire.mux_reg.ce_pri.douta_i_reg[16]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => clka, CE => ena, D => douta_array(16), Q => douta(16), R => '0' ); \mux_a_wire.mux_reg.ce_pri.douta_i_reg[17]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => clka, CE => ena, D => douta_array(17), Q => douta(17), R => '0' ); \mux_a_wire.mux_reg.ce_pri.douta_i_reg[18]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => clka, CE => ena, D => douta_array(18), Q => douta(18), R => '0' ); \mux_a_wire.mux_reg.ce_pri.douta_i_reg[19]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => clka, CE => ena, D => douta_array(19), Q => douta(19), R => '0' ); \mux_a_wire.mux_reg.ce_pri.douta_i_reg[1]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => clka, CE => ena, D => douta_array(1), Q => douta(1), R => '0' ); \mux_a_wire.mux_reg.ce_pri.douta_i_reg[2]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => clka, CE => ena, D => douta_array(2), Q => douta(2), R => '0' ); \mux_a_wire.mux_reg.ce_pri.douta_i_reg[3]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => clka, CE => ena, D => douta_array(3), Q => douta(3), R => '0' ); \mux_a_wire.mux_reg.ce_pri.douta_i_reg[4]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => clka, CE => ena, D => douta_array(4), Q => douta(4), R => '0' ); \mux_a_wire.mux_reg.ce_pri.douta_i_reg[5]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => clka, CE => ena, D => douta_array(5), Q => douta(5), R => '0' ); \mux_a_wire.mux_reg.ce_pri.douta_i_reg[6]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => clka, CE => ena, D => douta_array(6), Q => douta(6), R => '0' ); \mux_a_wire.mux_reg.ce_pri.douta_i_reg[7]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => clka, CE => ena, D => douta_array(7), Q => douta(7), R => '0' ); \mux_a_wire.mux_reg.ce_pri.douta_i_reg[8]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => clka, CE => ena, D => douta_array(8), Q => douta(8), R => '0' ); \mux_a_wire.mux_reg.ce_pri.douta_i_reg[9]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => clka, CE => ena, D => douta_array(9), Q => douta(9), R => '0' ); \ramloop[0].ram.r\: entity work.bram_4096_blk_mem_gen_prim_width port map ( DOADO(3 downto 0) => douta_array(3 downto 0), addra(11 downto 0) => addra(11 downto 0), clka => clka, dina(3 downto 0) => dina(3 downto 0), ena => ena, wea(0) => wea(0) ); \ramloop[1].ram.r\: entity work.\bram_4096_blk_mem_gen_prim_width__parameterized0\ port map ( addra(11 downto 0) => addra(11 downto 0), clka => clka, dina(8 downto 0) => dina(12 downto 4), douta_array(8 downto 0) => douta_array(12 downto 4), ena => ena, wea(0) => wea(0) ); \ramloop[2].ram.r\: entity work.\bram_4096_blk_mem_gen_prim_width__parameterized1\ port map ( DOADO(6 downto 0) => douta_array(19 downto 13), addra(11 downto 0) => addra(11 downto 0), clka => clka, dina(6 downto 0) => dina(19 downto 13), ena => ena, wea(0) => wea(0) ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity bram_4096_blk_mem_gen_top is port ( douta : out STD_LOGIC_VECTOR ( 19 downto 0 ); clka : in STD_LOGIC; ena : in STD_LOGIC; addra : in STD_LOGIC_VECTOR ( 11 downto 0 ); dina : in STD_LOGIC_VECTOR ( 19 downto 0 ); wea : in STD_LOGIC_VECTOR ( 0 to 0 ) ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of bram_4096_blk_mem_gen_top : entity is "blk_mem_gen_top"; end bram_4096_blk_mem_gen_top; architecture STRUCTURE of bram_4096_blk_mem_gen_top is begin \valid.cstr\: entity work.bram_4096_blk_mem_gen_generic_cstr port map ( addra(11 downto 0) => addra(11 downto 0), clka => clka, dina(19 downto 0) => dina(19 downto 0), douta(19 downto 0) => douta(19 downto 0), ena => ena, wea(0) => wea(0) ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity bram_4096_blk_mem_gen_v8_3_5_synth is port ( douta : out STD_LOGIC_VECTOR ( 19 downto 0 ); clka : in STD_LOGIC; ena : in STD_LOGIC; addra : in STD_LOGIC_VECTOR ( 11 downto 0 ); dina : in STD_LOGIC_VECTOR ( 19 downto 0 ); wea : in STD_LOGIC_VECTOR ( 0 to 0 ) ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of bram_4096_blk_mem_gen_v8_3_5_synth : entity is "blk_mem_gen_v8_3_5_synth"; end bram_4096_blk_mem_gen_v8_3_5_synth; architecture STRUCTURE of bram_4096_blk_mem_gen_v8_3_5_synth is begin \gnbram.gnativebmg.native_blk_mem_gen\: entity work.bram_4096_blk_mem_gen_top port map ( addra(11 downto 0) => addra(11 downto 0), clka => clka, dina(19 downto 0) => dina(19 downto 0), douta(19 downto 0) => douta(19 downto 0), ena => ena, wea(0) => wea(0) ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity bram_4096_blk_mem_gen_v8_3_5 is port ( clka : in STD_LOGIC; rsta : in STD_LOGIC; ena : in STD_LOGIC; regcea : in STD_LOGIC; wea : in STD_LOGIC_VECTOR ( 0 to 0 ); addra : in STD_LOGIC_VECTOR ( 11 downto 0 ); dina : in STD_LOGIC_VECTOR ( 19 downto 0 ); douta : out STD_LOGIC_VECTOR ( 19 downto 0 ); clkb : in STD_LOGIC; rstb : in STD_LOGIC; enb : in STD_LOGIC; regceb : in STD_LOGIC; web : in STD_LOGIC_VECTOR ( 0 to 0 ); addrb : in STD_LOGIC_VECTOR ( 11 downto 0 ); dinb : in STD_LOGIC_VECTOR ( 19 downto 0 ); doutb : out STD_LOGIC_VECTOR ( 19 downto 0 ); injectsbiterr : in STD_LOGIC; injectdbiterr : in STD_LOGIC; eccpipece : in STD_LOGIC; sbiterr : out STD_LOGIC; dbiterr : out STD_LOGIC; rdaddrecc : out STD_LOGIC_VECTOR ( 11 downto 0 ); sleep : in STD_LOGIC; deepsleep : in STD_LOGIC; shutdown : in STD_LOGIC; rsta_busy : out STD_LOGIC; rstb_busy : out STD_LOGIC; s_aclk : in STD_LOGIC; s_aresetn : in STD_LOGIC; s_axi_awid : in STD_LOGIC_VECTOR ( 3 downto 0 ); s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 ); s_axi_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 ); s_axi_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 ); s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 ); s_axi_awvalid : in STD_LOGIC; s_axi_awready : out STD_LOGIC; s_axi_wdata : in STD_LOGIC_VECTOR ( 19 downto 0 ); s_axi_wstrb : in STD_LOGIC_VECTOR ( 0 to 0 ); s_axi_wlast : in STD_LOGIC; s_axi_wvalid : in STD_LOGIC; s_axi_wready : out STD_LOGIC; s_axi_bid : out STD_LOGIC_VECTOR ( 3 downto 0 ); s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 ); s_axi_bvalid : out STD_LOGIC; s_axi_bready : in STD_LOGIC; s_axi_arid : in STD_LOGIC_VECTOR ( 3 downto 0 ); s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 ); s_axi_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 ); s_axi_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 ); s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 ); s_axi_arvalid : in STD_LOGIC; s_axi_arready : out STD_LOGIC; s_axi_rid : out STD_LOGIC_VECTOR ( 3 downto 0 ); s_axi_rdata : out STD_LOGIC_VECTOR ( 19 downto 0 ); s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 ); s_axi_rlast : out STD_LOGIC; s_axi_rvalid : out STD_LOGIC; s_axi_rready : in STD_LOGIC; s_axi_injectsbiterr : in STD_LOGIC; s_axi_injectdbiterr : in STD_LOGIC; s_axi_sbiterr : out STD_LOGIC; s_axi_dbiterr : out STD_LOGIC; s_axi_rdaddrecc : out STD_LOGIC_VECTOR ( 11 downto 0 ) ); attribute C_ADDRA_WIDTH : integer; attribute C_ADDRA_WIDTH of bram_4096_blk_mem_gen_v8_3_5 : entity is 12; attribute C_ADDRB_WIDTH : integer; attribute C_ADDRB_WIDTH of bram_4096_blk_mem_gen_v8_3_5 : entity is 12; attribute C_ALGORITHM : integer; attribute C_ALGORITHM of bram_4096_blk_mem_gen_v8_3_5 : entity is 1; attribute C_AXI_ID_WIDTH : integer; attribute C_AXI_ID_WIDTH of bram_4096_blk_mem_gen_v8_3_5 : entity is 4; attribute C_AXI_SLAVE_TYPE : integer; attribute C_AXI_SLAVE_TYPE of bram_4096_blk_mem_gen_v8_3_5 : entity is 0; attribute C_AXI_TYPE : integer; attribute C_AXI_TYPE of bram_4096_blk_mem_gen_v8_3_5 : entity is 1; attribute C_BYTE_SIZE : integer; attribute C_BYTE_SIZE of bram_4096_blk_mem_gen_v8_3_5 : entity is 9; attribute C_COMMON_CLK : integer; attribute C_COMMON_CLK of bram_4096_blk_mem_gen_v8_3_5 : entity is 0; attribute C_COUNT_18K_BRAM : string; attribute C_COUNT_18K_BRAM of bram_4096_blk_mem_gen_v8_3_5 : entity is "1"; attribute C_COUNT_36K_BRAM : string; attribute C_COUNT_36K_BRAM of bram_4096_blk_mem_gen_v8_3_5 : entity is "2"; attribute C_CTRL_ECC_ALGO : string; attribute C_CTRL_ECC_ALGO of bram_4096_blk_mem_gen_v8_3_5 : entity is "NONE"; attribute C_DEFAULT_DATA : string; attribute C_DEFAULT_DATA of bram_4096_blk_mem_gen_v8_3_5 : entity is "0"; attribute C_DISABLE_WARN_BHV_COLL : integer; attribute C_DISABLE_WARN_BHV_COLL of bram_4096_blk_mem_gen_v8_3_5 : entity is 0; attribute C_DISABLE_WARN_BHV_RANGE : integer; attribute C_DISABLE_WARN_BHV_RANGE of bram_4096_blk_mem_gen_v8_3_5 : entity is 0; attribute C_ELABORATION_DIR : string; attribute C_ELABORATION_DIR of bram_4096_blk_mem_gen_v8_3_5 : entity is "./"; attribute C_ENABLE_32BIT_ADDRESS : integer; attribute C_ENABLE_32BIT_ADDRESS of bram_4096_blk_mem_gen_v8_3_5 : entity is 0; attribute C_EN_DEEPSLEEP_PIN : integer; attribute C_EN_DEEPSLEEP_PIN of bram_4096_blk_mem_gen_v8_3_5 : entity is 0; attribute C_EN_ECC_PIPE : integer; attribute C_EN_ECC_PIPE of bram_4096_blk_mem_gen_v8_3_5 : entity is 0; attribute C_EN_RDADDRA_CHG : integer; attribute C_EN_RDADDRA_CHG of bram_4096_blk_mem_gen_v8_3_5 : entity is 0; attribute C_EN_RDADDRB_CHG : integer; attribute C_EN_RDADDRB_CHG of bram_4096_blk_mem_gen_v8_3_5 : entity is 0; attribute C_EN_SAFETY_CKT : integer; attribute C_EN_SAFETY_CKT of bram_4096_blk_mem_gen_v8_3_5 : entity is 0; attribute C_EN_SHUTDOWN_PIN : integer; attribute C_EN_SHUTDOWN_PIN of bram_4096_blk_mem_gen_v8_3_5 : entity is 0; attribute C_EN_SLEEP_PIN : integer; attribute C_EN_SLEEP_PIN of bram_4096_blk_mem_gen_v8_3_5 : entity is 0; attribute C_EST_POWER_SUMMARY : string; attribute C_EST_POWER_SUMMARY of bram_4096_blk_mem_gen_v8_3_5 : entity is "Estimated Power for IP : 6.3587 mW"; attribute C_FAMILY : string; attribute C_FAMILY of bram_4096_blk_mem_gen_v8_3_5 : entity is "zynq"; attribute C_HAS_AXI_ID : integer; attribute C_HAS_AXI_ID of bram_4096_blk_mem_gen_v8_3_5 : entity is 0; attribute C_HAS_ENA : integer; attribute C_HAS_ENA of bram_4096_blk_mem_gen_v8_3_5 : entity is 1; attribute C_HAS_ENB : integer; attribute C_HAS_ENB of bram_4096_blk_mem_gen_v8_3_5 : entity is 0; attribute C_HAS_INJECTERR : integer; attribute C_HAS_INJECTERR of bram_4096_blk_mem_gen_v8_3_5 : entity is 0; attribute C_HAS_MEM_OUTPUT_REGS_A : integer; attribute C_HAS_MEM_OUTPUT_REGS_A of bram_4096_blk_mem_gen_v8_3_5 : entity is 1; attribute C_HAS_MEM_OUTPUT_REGS_B : integer; attribute C_HAS_MEM_OUTPUT_REGS_B of bram_4096_blk_mem_gen_v8_3_5 : entity is 0; attribute C_HAS_MUX_OUTPUT_REGS_A : integer; attribute C_HAS_MUX_OUTPUT_REGS_A of bram_4096_blk_mem_gen_v8_3_5 : entity is 1; attribute C_HAS_MUX_OUTPUT_REGS_B : integer; attribute C_HAS_MUX_OUTPUT_REGS_B of bram_4096_blk_mem_gen_v8_3_5 : entity is 0; attribute C_HAS_REGCEA : integer; attribute C_HAS_REGCEA of bram_4096_blk_mem_gen_v8_3_5 : entity is 0; attribute C_HAS_REGCEB : integer; attribute C_HAS_REGCEB of bram_4096_blk_mem_gen_v8_3_5 : entity is 0; attribute C_HAS_RSTA : integer; attribute C_HAS_RSTA of bram_4096_blk_mem_gen_v8_3_5 : entity is 0; attribute C_HAS_RSTB : integer; attribute C_HAS_RSTB of bram_4096_blk_mem_gen_v8_3_5 : entity is 0; attribute C_HAS_SOFTECC_INPUT_REGS_A : integer; attribute C_HAS_SOFTECC_INPUT_REGS_A of bram_4096_blk_mem_gen_v8_3_5 : entity is 0; attribute C_HAS_SOFTECC_OUTPUT_REGS_B : integer; attribute C_HAS_SOFTECC_OUTPUT_REGS_B of bram_4096_blk_mem_gen_v8_3_5 : entity is 0; attribute C_INITA_VAL : string; attribute C_INITA_VAL of bram_4096_blk_mem_gen_v8_3_5 : entity is "0"; attribute C_INITB_VAL : string; attribute C_INITB_VAL of bram_4096_blk_mem_gen_v8_3_5 : entity is "0"; attribute C_INIT_FILE : string; attribute C_INIT_FILE of bram_4096_blk_mem_gen_v8_3_5 : entity is "bram_4096.mem"; attribute C_INIT_FILE_NAME : string; attribute C_INIT_FILE_NAME of bram_4096_blk_mem_gen_v8_3_5 : entity is "bram_4096.mif"; attribute C_INTERFACE_TYPE : integer; attribute C_INTERFACE_TYPE of bram_4096_blk_mem_gen_v8_3_5 : entity is 0; attribute C_LOAD_INIT_FILE : integer; attribute C_LOAD_INIT_FILE of bram_4096_blk_mem_gen_v8_3_5 : entity is 1; attribute C_MEM_TYPE : integer; attribute C_MEM_TYPE of bram_4096_blk_mem_gen_v8_3_5 : entity is 0; attribute C_MUX_PIPELINE_STAGES : integer; attribute C_MUX_PIPELINE_STAGES of bram_4096_blk_mem_gen_v8_3_5 : entity is 0; attribute C_PRIM_TYPE : integer; attribute C_PRIM_TYPE of bram_4096_blk_mem_gen_v8_3_5 : entity is 1; attribute C_READ_DEPTH_A : integer; attribute C_READ_DEPTH_A of bram_4096_blk_mem_gen_v8_3_5 : entity is 4096; attribute C_READ_DEPTH_B : integer; attribute C_READ_DEPTH_B of bram_4096_blk_mem_gen_v8_3_5 : entity is 4096; attribute C_READ_WIDTH_A : integer; attribute C_READ_WIDTH_A of bram_4096_blk_mem_gen_v8_3_5 : entity is 20; attribute C_READ_WIDTH_B : integer; attribute C_READ_WIDTH_B of bram_4096_blk_mem_gen_v8_3_5 : entity is 20; attribute C_RSTRAM_A : integer; attribute C_RSTRAM_A of bram_4096_blk_mem_gen_v8_3_5 : entity is 0; attribute C_RSTRAM_B : integer; attribute C_RSTRAM_B of bram_4096_blk_mem_gen_v8_3_5 : entity is 0; attribute C_RST_PRIORITY_A : string; attribute C_RST_PRIORITY_A of bram_4096_blk_mem_gen_v8_3_5 : entity is "CE"; attribute C_RST_PRIORITY_B : string; attribute C_RST_PRIORITY_B of bram_4096_blk_mem_gen_v8_3_5 : entity is "CE"; attribute C_SIM_COLLISION_CHECK : string; attribute C_SIM_COLLISION_CHECK of bram_4096_blk_mem_gen_v8_3_5 : entity is "ALL"; attribute C_USE_BRAM_BLOCK : integer; attribute C_USE_BRAM_BLOCK of bram_4096_blk_mem_gen_v8_3_5 : entity is 0; attribute C_USE_BYTE_WEA : integer; attribute C_USE_BYTE_WEA of bram_4096_blk_mem_gen_v8_3_5 : entity is 0; attribute C_USE_BYTE_WEB : integer; attribute C_USE_BYTE_WEB of bram_4096_blk_mem_gen_v8_3_5 : entity is 0; attribute C_USE_DEFAULT_DATA : integer; attribute C_USE_DEFAULT_DATA of bram_4096_blk_mem_gen_v8_3_5 : entity is 1; attribute C_USE_ECC : integer; attribute C_USE_ECC of bram_4096_blk_mem_gen_v8_3_5 : entity is 0; attribute C_USE_SOFTECC : integer; attribute C_USE_SOFTECC of bram_4096_blk_mem_gen_v8_3_5 : entity is 0; attribute C_USE_URAM : integer; attribute C_USE_URAM of bram_4096_blk_mem_gen_v8_3_5 : entity is 0; attribute C_WEA_WIDTH : integer; attribute C_WEA_WIDTH of bram_4096_blk_mem_gen_v8_3_5 : entity is 1; attribute C_WEB_WIDTH : integer; attribute C_WEB_WIDTH of bram_4096_blk_mem_gen_v8_3_5 : entity is 1; attribute C_WRITE_DEPTH_A : integer; attribute C_WRITE_DEPTH_A of bram_4096_blk_mem_gen_v8_3_5 : entity is 4096; attribute C_WRITE_DEPTH_B : integer; attribute C_WRITE_DEPTH_B of bram_4096_blk_mem_gen_v8_3_5 : entity is 4096; attribute C_WRITE_MODE_A : string; attribute C_WRITE_MODE_A of bram_4096_blk_mem_gen_v8_3_5 : entity is "WRITE_FIRST"; attribute C_WRITE_MODE_B : string; attribute C_WRITE_MODE_B of bram_4096_blk_mem_gen_v8_3_5 : entity is "WRITE_FIRST"; attribute C_WRITE_WIDTH_A : integer; attribute C_WRITE_WIDTH_A of bram_4096_blk_mem_gen_v8_3_5 : entity is 20; attribute C_WRITE_WIDTH_B : integer; attribute C_WRITE_WIDTH_B of bram_4096_blk_mem_gen_v8_3_5 : entity is 20; attribute C_XDEVICEFAMILY : string; attribute C_XDEVICEFAMILY of bram_4096_blk_mem_gen_v8_3_5 : entity is "zynq"; attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of bram_4096_blk_mem_gen_v8_3_5 : entity is "blk_mem_gen_v8_3_5"; attribute downgradeipidentifiedwarnings : string; attribute downgradeipidentifiedwarnings of bram_4096_blk_mem_gen_v8_3_5 : entity is "yes"; end bram_4096_blk_mem_gen_v8_3_5; architecture STRUCTURE of bram_4096_blk_mem_gen_v8_3_5 is signal \<const0>\ : STD_LOGIC; begin dbiterr <= \<const0>\; doutb(19) <= \<const0>\; doutb(18) <= \<const0>\; doutb(17) <= \<const0>\; doutb(16) <= \<const0>\; doutb(15) <= \<const0>\; doutb(14) <= \<const0>\; doutb(13) <= \<const0>\; doutb(12) <= \<const0>\; doutb(11) <= \<const0>\; doutb(10) <= \<const0>\; doutb(9) <= \<const0>\; doutb(8) <= \<const0>\; doutb(7) <= \<const0>\; doutb(6) <= \<const0>\; doutb(5) <= \<const0>\; doutb(4) <= \<const0>\; doutb(3) <= \<const0>\; doutb(2) <= \<const0>\; doutb(1) <= \<const0>\; doutb(0) <= \<const0>\; rdaddrecc(11) <= \<const0>\; rdaddrecc(10) <= \<const0>\; rdaddrecc(9) <= \<const0>\; rdaddrecc(8) <= \<const0>\; rdaddrecc(7) <= \<const0>\; rdaddrecc(6) <= \<const0>\; rdaddrecc(5) <= \<const0>\; rdaddrecc(4) <= \<const0>\; rdaddrecc(3) <= \<const0>\; rdaddrecc(2) <= \<const0>\; rdaddrecc(1) <= \<const0>\; rdaddrecc(0) <= \<const0>\; rsta_busy <= \<const0>\; rstb_busy <= \<const0>\; s_axi_arready <= \<const0>\; s_axi_awready <= \<const0>\; s_axi_bid(3) <= \<const0>\; s_axi_bid(2) <= \<const0>\; s_axi_bid(1) <= \<const0>\; s_axi_bid(0) <= \<const0>\; s_axi_bresp(1) <= \<const0>\; s_axi_bresp(0) <= \<const0>\; s_axi_bvalid <= \<const0>\; s_axi_dbiterr <= \<const0>\; s_axi_rdaddrecc(11) <= \<const0>\; s_axi_rdaddrecc(10) <= \<const0>\; s_axi_rdaddrecc(9) <= \<const0>\; s_axi_rdaddrecc(8) <= \<const0>\; s_axi_rdaddrecc(7) <= \<const0>\; s_axi_rdaddrecc(6) <= \<const0>\; s_axi_rdaddrecc(5) <= \<const0>\; s_axi_rdaddrecc(4) <= \<const0>\; s_axi_rdaddrecc(3) <= \<const0>\; s_axi_rdaddrecc(2) <= \<const0>\; s_axi_rdaddrecc(1) <= \<const0>\; s_axi_rdaddrecc(0) <= \<const0>\; s_axi_rdata(19) <= \<const0>\; s_axi_rdata(18) <= \<const0>\; s_axi_rdata(17) <= \<const0>\; s_axi_rdata(16) <= \<const0>\; s_axi_rdata(15) <= \<const0>\; s_axi_rdata(14) <= \<const0>\; s_axi_rdata(13) <= \<const0>\; s_axi_rdata(12) <= \<const0>\; s_axi_rdata(11) <= \<const0>\; s_axi_rdata(10) <= \<const0>\; s_axi_rdata(9) <= \<const0>\; s_axi_rdata(8) <= \<const0>\; s_axi_rdata(7) <= \<const0>\; s_axi_rdata(6) <= \<const0>\; s_axi_rdata(5) <= \<const0>\; s_axi_rdata(4) <= \<const0>\; s_axi_rdata(3) <= \<const0>\; s_axi_rdata(2) <= \<const0>\; s_axi_rdata(1) <= \<const0>\; s_axi_rdata(0) <= \<const0>\; s_axi_rid(3) <= \<const0>\; s_axi_rid(2) <= \<const0>\; s_axi_rid(1) <= \<const0>\; s_axi_rid(0) <= \<const0>\; s_axi_rlast <= \<const0>\; s_axi_rresp(1) <= \<const0>\; s_axi_rresp(0) <= \<const0>\; s_axi_rvalid <= \<const0>\; s_axi_sbiterr <= \<const0>\; s_axi_wready <= \<const0>\; sbiterr <= \<const0>\; GND: unisim.vcomponents.GND port map ( G => \<const0>\ ); inst_blk_mem_gen: entity work.bram_4096_blk_mem_gen_v8_3_5_synth port map ( addra(11 downto 0) => addra(11 downto 0), clka => clka, dina(19 downto 0) => dina(19 downto 0), douta(19 downto 0) => douta(19 downto 0), ena => ena, wea(0) => wea(0) ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity bram_4096 is port ( clka : in STD_LOGIC; ena : in STD_LOGIC; wea : in STD_LOGIC_VECTOR ( 0 to 0 ); addra : in STD_LOGIC_VECTOR ( 11 downto 0 ); dina : in STD_LOGIC_VECTOR ( 19 downto 0 ); douta : out STD_LOGIC_VECTOR ( 19 downto 0 ) ); attribute NotValidForBitStream : boolean; attribute NotValidForBitStream of bram_4096 : entity is true; attribute CHECK_LICENSE_TYPE : string; attribute CHECK_LICENSE_TYPE of bram_4096 : entity is "bram_4096,blk_mem_gen_v8_3_5,{}"; attribute downgradeipidentifiedwarnings : string; attribute downgradeipidentifiedwarnings of bram_4096 : entity is "yes"; attribute x_core_info : string; attribute x_core_info of bram_4096 : entity is "blk_mem_gen_v8_3_5,Vivado 2016.4"; end bram_4096; architecture STRUCTURE of bram_4096 is signal NLW_U0_dbiterr_UNCONNECTED : STD_LOGIC; signal NLW_U0_rsta_busy_UNCONNECTED : STD_LOGIC; signal NLW_U0_rstb_busy_UNCONNECTED : STD_LOGIC; signal NLW_U0_s_axi_arready_UNCONNECTED : STD_LOGIC; signal NLW_U0_s_axi_awready_UNCONNECTED : STD_LOGIC; signal NLW_U0_s_axi_bvalid_UNCONNECTED : STD_LOGIC; signal NLW_U0_s_axi_dbiterr_UNCONNECTED : STD_LOGIC; signal NLW_U0_s_axi_rlast_UNCONNECTED : STD_LOGIC; signal NLW_U0_s_axi_rvalid_UNCONNECTED : STD_LOGIC; signal NLW_U0_s_axi_sbiterr_UNCONNECTED : STD_LOGIC; signal NLW_U0_s_axi_wready_UNCONNECTED : STD_LOGIC; signal NLW_U0_sbiterr_UNCONNECTED : STD_LOGIC; signal NLW_U0_doutb_UNCONNECTED : STD_LOGIC_VECTOR ( 19 downto 0 ); signal NLW_U0_rdaddrecc_UNCONNECTED : STD_LOGIC_VECTOR ( 11 downto 0 ); signal NLW_U0_s_axi_bid_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 ); signal NLW_U0_s_axi_bresp_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 ); signal NLW_U0_s_axi_rdaddrecc_UNCONNECTED : STD_LOGIC_VECTOR ( 11 downto 0 ); signal NLW_U0_s_axi_rdata_UNCONNECTED : STD_LOGIC_VECTOR ( 19 downto 0 ); signal NLW_U0_s_axi_rid_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 ); signal NLW_U0_s_axi_rresp_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 ); attribute C_ADDRA_WIDTH : integer; attribute C_ADDRA_WIDTH of U0 : label is 12; attribute C_ADDRB_WIDTH : integer; attribute C_ADDRB_WIDTH of U0 : label is 12; attribute C_ALGORITHM : integer; attribute C_ALGORITHM of U0 : label is 1; attribute C_AXI_ID_WIDTH : integer; attribute C_AXI_ID_WIDTH of U0 : label is 4; attribute C_AXI_SLAVE_TYPE : integer; attribute C_AXI_SLAVE_TYPE of U0 : label is 0; attribute C_AXI_TYPE : integer; attribute C_AXI_TYPE of U0 : label is 1; attribute C_BYTE_SIZE : integer; attribute C_BYTE_SIZE of U0 : label is 9; attribute C_COMMON_CLK : integer; attribute C_COMMON_CLK of U0 : label is 0; attribute C_COUNT_18K_BRAM : string; attribute C_COUNT_18K_BRAM of U0 : label is "1"; attribute C_COUNT_36K_BRAM : string; attribute C_COUNT_36K_BRAM of U0 : label is "2"; attribute C_CTRL_ECC_ALGO : string; attribute C_CTRL_ECC_ALGO of U0 : label is "NONE"; attribute C_DEFAULT_DATA : string; attribute C_DEFAULT_DATA of U0 : label is "0"; attribute C_DISABLE_WARN_BHV_COLL : integer; attribute C_DISABLE_WARN_BHV_COLL of U0 : label is 0; attribute C_DISABLE_WARN_BHV_RANGE : integer; attribute C_DISABLE_WARN_BHV_RANGE of U0 : label is 0; attribute C_ELABORATION_DIR : string; attribute C_ELABORATION_DIR of U0 : label is "./"; attribute C_ENABLE_32BIT_ADDRESS : integer; attribute C_ENABLE_32BIT_ADDRESS of U0 : label is 0; attribute C_EN_DEEPSLEEP_PIN : integer; attribute C_EN_DEEPSLEEP_PIN of U0 : label is 0; attribute C_EN_ECC_PIPE : integer; attribute C_EN_ECC_PIPE of U0 : label is 0; attribute C_EN_RDADDRA_CHG : integer; attribute C_EN_RDADDRA_CHG of U0 : label is 0; attribute C_EN_RDADDRB_CHG : integer; attribute C_EN_RDADDRB_CHG of U0 : label is 0; attribute C_EN_SAFETY_CKT : integer; attribute C_EN_SAFETY_CKT of U0 : label is 0; attribute C_EN_SHUTDOWN_PIN : integer; attribute C_EN_SHUTDOWN_PIN of U0 : label is 0; attribute C_EN_SLEEP_PIN : integer; attribute C_EN_SLEEP_PIN of U0 : label is 0; attribute C_EST_POWER_SUMMARY : string; attribute C_EST_POWER_SUMMARY of U0 : label is "Estimated Power for IP : 6.3587 mW"; attribute C_FAMILY : string; attribute C_FAMILY of U0 : label is "zynq"; attribute C_HAS_AXI_ID : integer; attribute C_HAS_AXI_ID of U0 : label is 0; attribute C_HAS_ENA : integer; attribute C_HAS_ENA of U0 : label is 1; attribute C_HAS_ENB : integer; attribute C_HAS_ENB of U0 : label is 0; attribute C_HAS_INJECTERR : integer; attribute C_HAS_INJECTERR of U0 : label is 0; attribute C_HAS_MEM_OUTPUT_REGS_A : integer; attribute C_HAS_MEM_OUTPUT_REGS_A of U0 : label is 1; attribute C_HAS_MEM_OUTPUT_REGS_B : integer; attribute C_HAS_MEM_OUTPUT_REGS_B of U0 : label is 0; attribute C_HAS_MUX_OUTPUT_REGS_A : integer; attribute C_HAS_MUX_OUTPUT_REGS_A of U0 : label is 1; attribute C_HAS_MUX_OUTPUT_REGS_B : integer; attribute C_HAS_MUX_OUTPUT_REGS_B of U0 : label is 0; attribute C_HAS_REGCEA : integer; attribute C_HAS_REGCEA of U0 : label is 0; attribute C_HAS_REGCEB : integer; attribute C_HAS_REGCEB of U0 : label is 0; attribute C_HAS_RSTA : integer; attribute C_HAS_RSTA of U0 : label is 0; attribute C_HAS_RSTB : integer; attribute C_HAS_RSTB of U0 : label is 0; attribute C_HAS_SOFTECC_INPUT_REGS_A : integer; attribute C_HAS_SOFTECC_INPUT_REGS_A of U0 : label is 0; attribute C_HAS_SOFTECC_OUTPUT_REGS_B : integer; attribute C_HAS_SOFTECC_OUTPUT_REGS_B of U0 : label is 0; attribute C_INITA_VAL : string; attribute C_INITA_VAL of U0 : label is "0"; attribute C_INITB_VAL : string; attribute C_INITB_VAL of U0 : label is "0"; attribute C_INIT_FILE : string; attribute C_INIT_FILE of U0 : label is "bram_4096.mem"; attribute C_INIT_FILE_NAME : string; attribute C_INIT_FILE_NAME of U0 : label is "bram_4096.mif"; attribute C_INTERFACE_TYPE : integer; attribute C_INTERFACE_TYPE of U0 : label is 0; attribute C_LOAD_INIT_FILE : integer; attribute C_LOAD_INIT_FILE of U0 : label is 1; attribute C_MEM_TYPE : integer; attribute C_MEM_TYPE of U0 : label is 0; attribute C_MUX_PIPELINE_STAGES : integer; attribute C_MUX_PIPELINE_STAGES of U0 : label is 0; attribute C_PRIM_TYPE : integer; attribute C_PRIM_TYPE of U0 : label is 1; attribute C_READ_DEPTH_A : integer; attribute C_READ_DEPTH_A of U0 : label is 4096; attribute C_READ_DEPTH_B : integer; attribute C_READ_DEPTH_B of U0 : label is 4096; attribute C_READ_WIDTH_A : integer; attribute C_READ_WIDTH_A of U0 : label is 20; attribute C_READ_WIDTH_B : integer; attribute C_READ_WIDTH_B of U0 : label is 20; attribute C_RSTRAM_A : integer; attribute C_RSTRAM_A of U0 : label is 0; attribute C_RSTRAM_B : integer; attribute C_RSTRAM_B of U0 : label is 0; attribute C_RST_PRIORITY_A : string; attribute C_RST_PRIORITY_A of U0 : label is "CE"; attribute C_RST_PRIORITY_B : string; attribute C_RST_PRIORITY_B of U0 : label is "CE"; attribute C_SIM_COLLISION_CHECK : string; attribute C_SIM_COLLISION_CHECK of U0 : label is "ALL"; attribute C_USE_BRAM_BLOCK : integer; attribute C_USE_BRAM_BLOCK of U0 : label is 0; attribute C_USE_BYTE_WEA : integer; attribute C_USE_BYTE_WEA of U0 : label is 0; attribute C_USE_BYTE_WEB : integer; attribute C_USE_BYTE_WEB of U0 : label is 0; attribute C_USE_DEFAULT_DATA : integer; attribute C_USE_DEFAULT_DATA of U0 : label is 1; attribute C_USE_ECC : integer; attribute C_USE_ECC of U0 : label is 0; attribute C_USE_SOFTECC : integer; attribute C_USE_SOFTECC of U0 : label is 0; attribute C_USE_URAM : integer; attribute C_USE_URAM of U0 : label is 0; attribute C_WEA_WIDTH : integer; attribute C_WEA_WIDTH of U0 : label is 1; attribute C_WEB_WIDTH : integer; attribute C_WEB_WIDTH of U0 : label is 1; attribute C_WRITE_DEPTH_A : integer; attribute C_WRITE_DEPTH_A of U0 : label is 4096; attribute C_WRITE_DEPTH_B : integer; attribute C_WRITE_DEPTH_B of U0 : label is 4096; attribute C_WRITE_MODE_A : string; attribute C_WRITE_MODE_A of U0 : label is "WRITE_FIRST"; attribute C_WRITE_MODE_B : string; attribute C_WRITE_MODE_B of U0 : label is "WRITE_FIRST"; attribute C_WRITE_WIDTH_A : integer; attribute C_WRITE_WIDTH_A of U0 : label is 20; attribute C_WRITE_WIDTH_B : integer; attribute C_WRITE_WIDTH_B of U0 : label is 20; attribute C_XDEVICEFAMILY : string; attribute C_XDEVICEFAMILY of U0 : label is "zynq"; attribute downgradeipidentifiedwarnings of U0 : label is "yes"; begin U0: entity work.bram_4096_blk_mem_gen_v8_3_5 port map ( addra(11 downto 0) => addra(11 downto 0), addrb(11 downto 0) => B"000000000000", clka => clka, clkb => '0', dbiterr => NLW_U0_dbiterr_UNCONNECTED, deepsleep => '0', dina(19 downto 0) => dina(19 downto 0), dinb(19 downto 0) => B"00000000000000000000", douta(19 downto 0) => douta(19 downto 0), doutb(19 downto 0) => NLW_U0_doutb_UNCONNECTED(19 downto 0), eccpipece => '0', ena => ena, enb => '0', injectdbiterr => '0', injectsbiterr => '0', rdaddrecc(11 downto 0) => NLW_U0_rdaddrecc_UNCONNECTED(11 downto 0), regcea => '0', regceb => '0', rsta => '0', rsta_busy => NLW_U0_rsta_busy_UNCONNECTED, rstb => '0', rstb_busy => NLW_U0_rstb_busy_UNCONNECTED, s_aclk => '0', s_aresetn => '0', s_axi_araddr(31 downto 0) => B"00000000000000000000000000000000", s_axi_arburst(1 downto 0) => B"00", s_axi_arid(3 downto 0) => B"0000", s_axi_arlen(7 downto 0) => B"00000000", s_axi_arready => NLW_U0_s_axi_arready_UNCONNECTED, s_axi_arsize(2 downto 0) => B"000", s_axi_arvalid => '0', s_axi_awaddr(31 downto 0) => B"00000000000000000000000000000000", s_axi_awburst(1 downto 0) => B"00", s_axi_awid(3 downto 0) => B"0000", s_axi_awlen(7 downto 0) => B"00000000", s_axi_awready => NLW_U0_s_axi_awready_UNCONNECTED, s_axi_awsize(2 downto 0) => B"000", s_axi_awvalid => '0', s_axi_bid(3 downto 0) => NLW_U0_s_axi_bid_UNCONNECTED(3 downto 0), s_axi_bready => '0', s_axi_bresp(1 downto 0) => NLW_U0_s_axi_bresp_UNCONNECTED(1 downto 0), s_axi_bvalid => NLW_U0_s_axi_bvalid_UNCONNECTED, s_axi_dbiterr => NLW_U0_s_axi_dbiterr_UNCONNECTED, s_axi_injectdbiterr => '0', s_axi_injectsbiterr => '0', s_axi_rdaddrecc(11 downto 0) => NLW_U0_s_axi_rdaddrecc_UNCONNECTED(11 downto 0), s_axi_rdata(19 downto 0) => NLW_U0_s_axi_rdata_UNCONNECTED(19 downto 0), s_axi_rid(3 downto 0) => NLW_U0_s_axi_rid_UNCONNECTED(3 downto 0), s_axi_rlast => NLW_U0_s_axi_rlast_UNCONNECTED, s_axi_rready => '0', s_axi_rresp(1 downto 0) => NLW_U0_s_axi_rresp_UNCONNECTED(1 downto 0), s_axi_rvalid => NLW_U0_s_axi_rvalid_UNCONNECTED, s_axi_sbiterr => NLW_U0_s_axi_sbiterr_UNCONNECTED, s_axi_wdata(19 downto 0) => B"00000000000000000000", s_axi_wlast => '0', s_axi_wready => NLW_U0_s_axi_wready_UNCONNECTED, s_axi_wstrb(0) => '0', s_axi_wvalid => '0', sbiterr => NLW_U0_sbiterr_UNCONNECTED, shutdown => '0', sleep => '0', wea(0) => wea(0), web(0) => '0' ); end STRUCTURE;
unlicense
5885bbbc2b595820e75ead37664d5abf
0.70661
3.973534
false
false
false
false
grwlf/vsim
vhdl_ct/ct00110.vhd
1
12,585
-- NEED RESULT: ARCH00110.P1: Multi transport transactions occurred on signal asg with selected name prefixed by an indexed name on LHS passed -- NEED RESULT: ARCH00110.P2: Multi transport transactions occurred on signal asg with selected name prefixed by an indexed name on LHS passed -- NEED RESULT: ARCH00110.P3: Multi transport transactions occurred on signal asg with selected name prefixed by an indexed name on LHS passed -- NEED RESULT: ARCH00110: One transport transaction occurred on signal asg with selected name prefixed by an indexed name on LHS passed -- NEED RESULT: ARCH00110: Old transactions were removed on signal asg with selected name prefixed by an indexed name on LHS passed -- NEED RESULT: ARCH00110: One transport transaction occurred on signal asg with selected name prefixed by an indexed name on LHS passed -- NEED RESULT: ARCH00110: Old transactions were removed on signal asg with selected name prefixed by an indexed name on LHS passed -- NEED RESULT: ARCH00110: One transport transaction occurred on signal asg with selected name prefixed by an indexed name on LHS passed -- NEED RESULT: ARCH00110: Old transactions were removed on signal asg with selected name prefixed by an indexed name on LHS passed -- NEED RESULT: P3: Transport transactions entirely completed passed -- NEED RESULT: P2: Transport transactions entirely completed passed -- NEED RESULT: P1: Transport transactions entirely completed passed ------------------------------------------------------------------------------- -- -- Copyright (c) 1989 by Intermetrics, Inc. -- All rights reserved. -- ------------------------------------------------------------------------------- -- -- TEST NAME: -- -- CT00110 -- -- AUTHOR: -- -- G. Tominovich -- -- TEST OBJECTIVES: -- -- 8.3 (2) -- 8.3 (3) -- 8.3 (5) -- 8.3.1 (3) -- -- DESIGN UNIT ORDERING: -- -- ENT00110(ARCH00110) -- ENT00110_Test_Bench(ARCH00110_Test_Bench) -- -- REVISION HISTORY: -- -- 07-JUL-1987 - initial revision -- -- NOTES: -- -- self-checking -- automatically generated -- use WORK.STANDARD_TYPES.all ; entity ENT00110 is port ( s_st_rec1_vector : inout st_rec1_vector ; s_st_rec2_vector : inout st_rec2_vector ; s_st_rec3_vector : inout st_rec3_vector ) ; subtype chk_sig_type is integer range -1 to 100 ; signal chk_st_rec1_vector : chk_sig_type := -1 ; signal chk_st_rec2_vector : chk_sig_type := -1 ; signal chk_st_rec3_vector : chk_sig_type := -1 ; -- end ENT00110 ; -- architecture ARCH00110 of ENT00110 is begin PGEN_CHKP_1 : process ( chk_st_rec1_vector ) begin if Std.Standard.Now > 0 ns then test_report ( "P1" , "Transport transactions entirely completed", chk_st_rec1_vector = 4 ) ; end if ; end process PGEN_CHKP_1 ; -- P1 : process ( s_st_rec1_vector ) variable correct : boolean ; variable counter : integer := 0 ; variable savtime : time ; begin case counter is when 0 => s_st_rec1_vector(lowb).f2 <= transport c_st_rec1_vector_2(highb).f2 after 10 ns, c_st_rec1_vector_1(highb).f2 after 20 ns ; -- when 1 => correct := s_st_rec1_vector(lowb).f2 = c_st_rec1_vector_2(highb).f2 and (savtime + 10 ns) = Std.Standard.Now ; -- when 2 => correct := correct and s_st_rec1_vector(lowb).f2 = c_st_rec1_vector_1(highb).f2 and (savtime + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00110.P1" , "Multi transport transactions occurred on signal " & "asg with selected name prefixed by an indexed name on LHS", correct ) ; s_st_rec1_vector(lowb).f2 <= transport c_st_rec1_vector_2(highb).f2 after 10 ns , c_st_rec1_vector_1(highb).f2 after 20 ns , c_st_rec1_vector_2(highb).f2 after 30 ns , c_st_rec1_vector_1(highb).f2 after 40 ns ; -- when 3 => correct := s_st_rec1_vector(lowb).f2 = c_st_rec1_vector_2(highb).f2 and (savtime + 10 ns) = Std.Standard.Now ; s_st_rec1_vector(lowb).f2 <= transport c_st_rec1_vector_1(highb).f2 after 5 ns ; -- when 4 => correct := correct and s_st_rec1_vector(lowb).f2 = c_st_rec1_vector_1(highb).f2 and (savtime + 5 ns) = Std.Standard.Now ; test_report ( "ARCH00110" , "One transport transaction occurred on signal " & "asg with selected name prefixed by an indexed name on LHS", correct ) ; test_report ( "ARCH00110" , "Old transactions were removed on signal " & "asg with selected name prefixed by an indexed name on LHS", correct ) ; -- when others => -- No more transactions should have occurred test_report ( "ARCH00110" , "Old transactions were removed on signal " & "asg with selected name prefixed by an indexed name on LHS", false ) ; -- end case ; -- savtime := Std.Standard.Now ; chk_st_rec1_vector <= transport counter after (1 us - savtime) ; counter := counter + 1; -- end process P1 ; -- PGEN_CHKP_2 : process ( chk_st_rec2_vector ) begin if Std.Standard.Now > 0 ns then test_report ( "P2" , "Transport transactions entirely completed", chk_st_rec2_vector = 4 ) ; end if ; end process PGEN_CHKP_2 ; -- P2 : process ( s_st_rec2_vector ) variable correct : boolean ; variable counter : integer := 0 ; variable savtime : time ; begin case counter is when 0 => s_st_rec2_vector(lowb).f2 <= transport c_st_rec2_vector_2(highb).f2 after 10 ns, c_st_rec2_vector_1(highb).f2 after 20 ns ; -- when 1 => correct := s_st_rec2_vector(lowb).f2 = c_st_rec2_vector_2(highb).f2 and (savtime + 10 ns) = Std.Standard.Now ; -- when 2 => correct := correct and s_st_rec2_vector(lowb).f2 = c_st_rec2_vector_1(highb).f2 and (savtime + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00110.P2" , "Multi transport transactions occurred on signal " & "asg with selected name prefixed by an indexed name on LHS", correct ) ; s_st_rec2_vector(lowb).f2 <= transport c_st_rec2_vector_2(highb).f2 after 10 ns , c_st_rec2_vector_1(highb).f2 after 20 ns , c_st_rec2_vector_2(highb).f2 after 30 ns , c_st_rec2_vector_1(highb).f2 after 40 ns ; -- when 3 => correct := s_st_rec2_vector(lowb).f2 = c_st_rec2_vector_2(highb).f2 and (savtime + 10 ns) = Std.Standard.Now ; s_st_rec2_vector(lowb).f2 <= transport c_st_rec2_vector_1(highb).f2 after 5 ns ; -- when 4 => correct := correct and s_st_rec2_vector(lowb).f2 = c_st_rec2_vector_1(highb).f2 and (savtime + 5 ns) = Std.Standard.Now ; test_report ( "ARCH00110" , "One transport transaction occurred on signal " & "asg with selected name prefixed by an indexed name on LHS", correct ) ; test_report ( "ARCH00110" , "Old transactions were removed on signal " & "asg with selected name prefixed by an indexed name on LHS", correct ) ; -- when others => -- No more transactions should have occurred test_report ( "ARCH00110" , "Old transactions were removed on signal " & "asg with selected name prefixed by an indexed name on LHS", false ) ; -- end case ; -- savtime := Std.Standard.Now ; chk_st_rec2_vector <= transport counter after (1 us - savtime) ; counter := counter + 1; -- end process P2 ; -- PGEN_CHKP_3 : process ( chk_st_rec3_vector ) begin if Std.Standard.Now > 0 ns then test_report ( "P3" , "Transport transactions entirely completed", chk_st_rec3_vector = 4 ) ; end if ; end process PGEN_CHKP_3 ; -- P3 : process ( s_st_rec3_vector ) variable correct : boolean ; variable counter : integer := 0 ; variable savtime : time ; begin case counter is when 0 => s_st_rec3_vector(lowb).f2 <= transport c_st_rec3_vector_2(highb).f2 after 10 ns, c_st_rec3_vector_1(highb).f2 after 20 ns ; -- when 1 => correct := s_st_rec3_vector(lowb).f2 = c_st_rec3_vector_2(highb).f2 and (savtime + 10 ns) = Std.Standard.Now ; -- when 2 => correct := correct and s_st_rec3_vector(lowb).f2 = c_st_rec3_vector_1(highb).f2 and (savtime + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00110.P3" , "Multi transport transactions occurred on signal " & "asg with selected name prefixed by an indexed name on LHS", correct ) ; s_st_rec3_vector(lowb).f2 <= transport c_st_rec3_vector_2(highb).f2 after 10 ns , c_st_rec3_vector_1(highb).f2 after 20 ns , c_st_rec3_vector_2(highb).f2 after 30 ns , c_st_rec3_vector_1(highb).f2 after 40 ns ; -- when 3 => correct := s_st_rec3_vector(lowb).f2 = c_st_rec3_vector_2(highb).f2 and (savtime + 10 ns) = Std.Standard.Now ; s_st_rec3_vector(lowb).f2 <= transport c_st_rec3_vector_1(highb).f2 after 5 ns ; -- when 4 => correct := correct and s_st_rec3_vector(lowb).f2 = c_st_rec3_vector_1(highb).f2 and (savtime + 5 ns) = Std.Standard.Now ; test_report ( "ARCH00110" , "One transport transaction occurred on signal " & "asg with selected name prefixed by an indexed name on LHS", correct ) ; test_report ( "ARCH00110" , "Old transactions were removed on signal " & "asg with selected name prefixed by an indexed name on LHS", correct ) ; -- when others => -- No more transactions should have occurred test_report ( "ARCH00110" , "Old transactions were removed on signal " & "asg with selected name prefixed by an indexed name on LHS", false ) ; -- end case ; -- savtime := Std.Standard.Now ; chk_st_rec3_vector <= transport counter after (1 us - savtime) ; counter := counter + 1; -- end process P3 ; -- -- end ARCH00110 ; -- use WORK.STANDARD_TYPES.all ; entity ENT00110_Test_Bench is signal s_st_rec1_vector : st_rec1_vector := c_st_rec1_vector_1 ; signal s_st_rec2_vector : st_rec2_vector := c_st_rec2_vector_1 ; signal s_st_rec3_vector : st_rec3_vector := c_st_rec3_vector_1 ; -- end ENT00110_Test_Bench ; -- architecture ARCH00110_Test_Bench of ENT00110_Test_Bench is begin L1: block component UUT port ( s_st_rec1_vector : inout st_rec1_vector ; s_st_rec2_vector : inout st_rec2_vector ; s_st_rec3_vector : inout st_rec3_vector ) ; end component ; -- for CIS1 : UUT use entity WORK.ENT00110 ( ARCH00110 ) ; begin CIS1 : UUT port map ( s_st_rec1_vector , s_st_rec2_vector , s_st_rec3_vector ) ; end block L1 ; end ARCH00110_Test_Bench ;
gpl-3.0
e48ab1ed5cab272ffadfce56f3304ce4
0.532062
3.689534
false
true
false
false
grwlf/vsim
vhdl/IEEE/numeric_std.vhdl
1
117,361
-- -------------------------------------------------------------------- -- -- Copyright 1995 by IEEE. All rights reserved. -- -- This source file is considered by the IEEE to be an essential part of the use -- of the standard 1076.3 and as such may be distributed without change, except -- as permitted by the standard. This source file may not be sold or distributed -- for profit. This package may be modified to include additional data required -- by tools, but must in no way change the external interfaces or simulation -- behaviour of the description. It is permissible to add comments and/or -- attributes to the package declarations, but not to change or delete any -- original lines of the approved package declaration. The package body may be -- changed only in accordance with the terms of clauses 7.1 and 7.2 of the -- standard. -- -- Title : Standard VHDL Synthesis Package (1076.3, NUMERIC_STD) -- -- Library : This package shall be compiled into a library symbolically -- : named IEEE. -- -- Developers : IEEE DASC Synthesis Working Group, PAR 1076.3 -- -- Purpose : This package defines numeric types and arithmetic functions -- : for use with synthesis tools. Two numeric types are defined: -- : -- > UNSIGNED: represents UNSIGNED number in vector form -- : -- > SIGNED: represents a SIGNED number in vector form -- : The base element type is type STD_LOGIC. -- : The leftmost bit is treated as the most significant bit. -- : Signed vectors are represented in two's complement form. -- : This package contains overloaded arithmetic operators on -- : the SIGNED and UNSIGNED types. The package also contains -- : useful type conversions functions. -- : -- : If any argument to a function is a null array, a null array is -- : returned (exceptions, if any, are noted individually). -- -- Limitation : -- -- Note : No declarations or definitions shall be included in, -- : or excluded from this package. The "package declaration" -- : defines the types, subtypes and declarations of -- : NUMERIC_STD. The NUMERIC_STD package body shall be -- : considered the formal definition of the semantics of -- : this package. Tool developers may choose to implement -- : the package body in the most efficient manner available -- : to them. -- -- -------------------------------------------------------------------- -- modification history : -- -------------------------------------------------------------------- -- Version: 2.4 -- Date : 12 April 1995 -- ----------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.all; package NUMERIC_STD is constant CopyRightNotice: STRING := "Copyright 1995 IEEE. All rights reserved."; --============================================================================ -- Numeric array type definitions --============================================================================ type UNSIGNED is array (NATURAL range <>) of STD_LOGIC; type SIGNED is array (NATURAL range <>) of STD_LOGIC; --============================================================================ -- Arithmetic Operators: --=========================================================================== -- Id: A.1 function "abs" (ARG: SIGNED) return SIGNED; -- Result subtype: SIGNED(ARG'LENGTH-1 downto 0). -- Result: Returns the absolute value of a SIGNED vector ARG. -- Id: A.2 function "-" (ARG: SIGNED) return SIGNED; -- Result subtype: SIGNED(ARG'LENGTH-1 downto 0). -- Result: Returns the value of the unary minus operation on a -- SIGNED vector ARG. --============================================================================ -- Id: A.3 function "+" (L, R: UNSIGNED) return UNSIGNED; -- Result subtype: UNSIGNED(MAX(L'LENGTH, R'LENGTH)-1 downto 0). -- Result: Adds two UNSIGNED vectors that may be of different lengths. -- Id: A.4 function "+" (L, R: SIGNED) return SIGNED; -- Result subtype: SIGNED(MAX(L'LENGTH, R'LENGTH)-1 downto 0). -- Result: Adds two SIGNED vectors that may be of different lengths. -- Id: A.5 function "+" (L: UNSIGNED; R: NATURAL) return UNSIGNED; -- Result subtype: UNSIGNED(L'LENGTH-1 downto 0). -- Result: Adds an UNSIGNED vector, L, with a non-negative INTEGER, R. -- Id: A.6 function "+" (L: NATURAL; R: UNSIGNED) return UNSIGNED; -- Result subtype: UNSIGNED(R'LENGTH-1 downto 0). -- Result: Adds a non-negative INTEGER, L, with an UNSIGNED vector, R. -- Id: A.7 function "+" (L: INTEGER; R: SIGNED) return SIGNED; -- Result subtype: SIGNED(R'LENGTH-1 downto 0). -- Result: Adds an INTEGER, L(may be positive or negative), to a SIGNED -- vector, R. -- Id: A.8 function "+" (L: SIGNED; R: INTEGER) return SIGNED; -- Result subtype: SIGNED(L'LENGTH-1 downto 0). -- Result: Adds a SIGNED vector, L, to an INTEGER, R. --============================================================================ -- Id: A.9 function "-" (L, R: UNSIGNED) return UNSIGNED; -- Result subtype: UNSIGNED(MAX(L'LENGTH, R'LENGTH)-1 downto 0). -- Result: Subtracts two UNSIGNED vectors that may be of different lengths. -- Id: A.10 function "-" (L, R: SIGNED) return SIGNED; -- Result subtype: SIGNED(MAX(L'LENGTH, R'LENGTH)-1 downto 0). -- Result: Subtracts a SIGNED vector, R, from another SIGNED vector, L, -- that may possibly be of different lengths. -- Id: A.11 function "-" (L: UNSIGNED;R: NATURAL) return UNSIGNED; -- Result subtype: UNSIGNED(L'LENGTH-1 downto 0). -- Result: Subtracts a non-negative INTEGER, R, from an UNSIGNED vector, L. -- Id: A.12 function "-" (L: NATURAL; R: UNSIGNED) return UNSIGNED; -- Result subtype: UNSIGNED(R'LENGTH-1 downto 0). -- Result: Subtracts an UNSIGNED vector, R, from a non-negative INTEGER, L. -- Id: A.13 function "-" (L: SIGNED; R: INTEGER) return SIGNED; -- Result subtype: SIGNED(L'LENGTH-1 downto 0). -- Result: Subtracts an INTEGER, R, from a SIGNED vector, L. -- Id: A.14 function "-" (L: INTEGER; R: SIGNED) return SIGNED; -- Result subtype: SIGNED(R'LENGTH-1 downto 0). -- Result: Subtracts a SIGNED vector, R, from an INTEGER, L. --============================================================================ -- Id: A.15 function "*" (L, R: UNSIGNED) return UNSIGNED; -- Result subtype: UNSIGNED((L'LENGTH+R'LENGTH-1) downto 0). -- Result: Performs the multiplication operation on two UNSIGNED vectors -- that may possibly be of different lengths. -- Id: A.16 function "*" (L, R: SIGNED) return SIGNED; -- Result subtype: SIGNED((L'LENGTH+R'LENGTH-1) downto 0) -- Result: Multiplies two SIGNED vectors that may possibly be of -- different lengths. -- Id: A.17 function "*" (L: UNSIGNED; R: NATURAL) return UNSIGNED; -- Result subtype: UNSIGNED((L'LENGTH+L'LENGTH-1) downto 0). -- Result: Multiplies an UNSIGNED vector, L, with a non-negative -- INTEGER, R. R is converted to an UNSIGNED vector of -- SIZE L'LENGTH before multiplication. -- Id: A.18 function "*" (L: NATURAL; R: UNSIGNED) return UNSIGNED; -- Result subtype: UNSIGNED((R'LENGTH+R'LENGTH-1) downto 0). -- Result: Multiplies an UNSIGNED vector, R, with a non-negative -- INTEGER, L. L is converted to an UNSIGNED vector of -- SIZE R'LENGTH before multiplication. -- Id: A.19 function "*" (L: SIGNED; R: INTEGER) return SIGNED; -- Result subtype: SIGNED((L'LENGTH+L'LENGTH-1) downto 0) -- Result: Multiplies a SIGNED vector, L, with an INTEGER, R. R is -- converted to a SIGNED vector of SIZE L'LENGTH before -- multiplication. -- Id: A.20 function "*" (L: INTEGER; R: SIGNED) return SIGNED; -- Result subtype: SIGNED((R'LENGTH+R'LENGTH-1) downto 0) -- Result: Multiplies a SIGNED vector, R, with an INTEGER, L. L is -- converted to a SIGNED vector of SIZE R'LENGTH before -- multiplication. --============================================================================ -- -- NOTE: If second argument is zero for "/" operator, a severity level -- of ERROR is issued. -- Id: A.21 function "/" (L, R: UNSIGNED) return UNSIGNED; -- Result subtype: UNSIGNED(L'LENGTH-1 downto 0) -- Result: Divides an UNSIGNED vector, L, by another UNSIGNED vector, R. -- Id: A.22 function "/" (L, R: SIGNED) return SIGNED; -- Result subtype: SIGNED(L'LENGTH-1 downto 0) -- Result: Divides an SIGNED vector, L, by another SIGNED vector, R. -- Id: A.23 function "/" (L: UNSIGNED; R: NATURAL) return UNSIGNED; -- Result subtype: UNSIGNED(L'LENGTH-1 downto 0) -- Result: Divides an UNSIGNED vector, L, by a non-negative INTEGER, R. -- If NO_OF_BITS(R) > L'LENGTH, result is truncated to L'LENGTH. -- Id: A.24 function "/" (L: NATURAL; R: UNSIGNED) return UNSIGNED; -- Result subtype: UNSIGNED(R'LENGTH-1 downto 0) -- Result: Divides a non-negative INTEGER, L, by an UNSIGNED vector, R. -- If NO_OF_BITS(L) > R'LENGTH, result is truncated to R'LENGTH. -- Id: A.25 function "/" (L: SIGNED; R: INTEGER) return SIGNED; -- Result subtype: SIGNED(L'LENGTH-1 downto 0) -- Result: Divides a SIGNED vector, L, by an INTEGER, R. -- If NO_OF_BITS(R) > L'LENGTH, result is truncated to L'LENGTH. -- Id: A.26 function "/" (L: INTEGER; R: SIGNED) return SIGNED; -- Result subtype: SIGNED(R'LENGTH-1 downto 0) -- Result: Divides an INTEGER, L, by a SIGNED vector, R. -- If NO_OF_BITS(L) > R'LENGTH, result is truncated to R'LENGTH. --============================================================================ -- -- NOTE: If second argument is zero for "rem" operator, a severity level -- of ERROR is issued. -- Id: A.27 function "rem" (L, R: UNSIGNED) return UNSIGNED; -- Result subtype: UNSIGNED(R'LENGTH-1 downto 0) -- Result: Computes "L rem R" where L and R are UNSIGNED vectors. -- Id: A.28 function "rem" (L, R: SIGNED) return SIGNED; -- Result subtype: SIGNED(R'LENGTH-1 downto 0) -- Result: Computes "L rem R" where L and R are SIGNED vectors. -- Id: A.29 function "rem" (L: UNSIGNED; R: NATURAL) return UNSIGNED; -- Result subtype: UNSIGNED(L'LENGTH-1 downto 0) -- Result: Computes "L rem R" where L is an UNSIGNED vector and R is a -- non-negative INTEGER. -- If NO_OF_BITS(R) > L'LENGTH, result is truncated to L'LENGTH. -- Id: A.30 function "rem" (L: NATURAL; R: UNSIGNED) return UNSIGNED; -- Result subtype: UNSIGNED(R'LENGTH-1 downto 0) -- Result: Computes "L rem R" where R is an UNSIGNED vector and L is a -- non-negative INTEGER. -- If NO_OF_BITS(L) > R'LENGTH, result is truncated to R'LENGTH. -- Id: A.31 function "rem" (L: SIGNED; R: INTEGER) return SIGNED; -- Result subtype: SIGNED(L'LENGTH-1 downto 0) -- Result: Computes "L rem R" where L is SIGNED vector and R is an INTEGER. -- If NO_OF_BITS(R) > L'LENGTH, result is truncated to L'LENGTH. -- Id: A.32 function "rem" (L: INTEGER; R: SIGNED) return SIGNED; -- Result subtype: SIGNED(R'LENGTH-1 downto 0) -- Result: Computes "L rem R" where R is SIGNED vector and L is an INTEGER. -- If NO_OF_BITS(L) > R'LENGTH, result is truncated to R'LENGTH. --============================================================================ -- -- NOTE: If second argument is zero for "mod" operator, a severity level -- of ERROR is issued. -- Id: A.33 function "mod" (L, R: UNSIGNED) return UNSIGNED; -- Result subtype: UNSIGNED(R'LENGTH-1 downto 0) -- Result: Computes "L mod R" where L and R are UNSIGNED vectors. -- Id: A.34 function "mod" (L, R: SIGNED) return SIGNED; -- Result subtype: SIGNED(R'LENGTH-1 downto 0) -- Result: Computes "L mod R" where L and R are SIGNED vectors. -- Id: A.35 function "mod" (L: UNSIGNED; R: NATURAL) return UNSIGNED; -- Result subtype: UNSIGNED(L'LENGTH-1 downto 0) -- Result: Computes "L mod R" where L is an UNSIGNED vector and R -- is a non-negative INTEGER. -- If NO_OF_BITS(R) > L'LENGTH, result is truncated to L'LENGTH. -- Id: A.36 function "mod" (L: NATURAL; R: UNSIGNED) return UNSIGNED; -- Result subtype: UNSIGNED(R'LENGTH-1 downto 0) -- Result: Computes "L mod R" where R is an UNSIGNED vector and L -- is a non-negative INTEGER. -- If NO_OF_BITS(L) > R'LENGTH, result is truncated to R'LENGTH. -- Id: A.37 function "mod" (L: SIGNED; R: INTEGER) return SIGNED; -- Result subtype: SIGNED(L'LENGTH-1 downto 0) -- Result: Computes "L mod R" where L is a SIGNED vector and -- R is an INTEGER. -- If NO_OF_BITS(R) > L'LENGTH, result is truncated to L'LENGTH. -- Id: A.38 function "mod" (L: INTEGER; R: SIGNED) return SIGNED; -- Result subtype: SIGNED(R'LENGTH-1 downto 0) -- Result: Computes "L mod R" where L is an INTEGER and -- R is a SIGNED vector. -- If NO_OF_BITS(L) > R'LENGTH, result is truncated to R'LENGTH. --============================================================================ -- Comparison Operators --============================================================================ -- Id: C.1 function ">" (L, R: UNSIGNED) return BOOLEAN; -- Result subtype: BOOLEAN -- Result: Computes "L > R" where L and R are UNSIGNED vectors possibly -- of different lengths. -- Id: C.2 function ">" (L, R: SIGNED) return BOOLEAN; -- Result subtype: BOOLEAN -- Result: Computes "L > R" where L and R are SIGNED vectors possibly -- of different lengths. -- Id: C.3 function ">" (L: NATURAL; R: UNSIGNED) return BOOLEAN; -- Result subtype: BOOLEAN -- Result: Computes "L > R" where L is a non-negative INTEGER and -- R is an UNSIGNED vector. -- Id: C.4 function ">" (L: INTEGER; R: SIGNED) return BOOLEAN; -- Result subtype: BOOLEAN -- Result: Computes "L > R" where L is a INTEGER and -- R is a SIGNED vector. -- Id: C.5 function ">" (L: UNSIGNED; R: NATURAL) return BOOLEAN; -- Result subtype: BOOLEAN -- Result: Computes "L > R" where L is an UNSIGNED vector and -- R is a non-negative INTEGER. -- Id: C.6 function ">" (L: SIGNED; R: INTEGER) return BOOLEAN; -- Result subtype: BOOLEAN -- Result: Computes "L > R" where L is a SIGNED vector and -- R is a INTEGER. --============================================================================ -- Id: C.7 function "<" (L, R: UNSIGNED) return BOOLEAN; -- Result subtype: BOOLEAN -- Result: Computes "L < R" where L and R are UNSIGNED vectors possibly -- of different lengths. -- Id: C.8 function "<" (L, R: SIGNED) return BOOLEAN; -- Result subtype: BOOLEAN -- Result: Computes "L < R" where L and R are SIGNED vectors possibly -- of different lengths. -- Id: C.9 function "<" (L: NATURAL; R: UNSIGNED) return BOOLEAN; -- Result subtype: BOOLEAN -- Result: Computes "L < R" where L is a non-negative INTEGER and -- R is an UNSIGNED vector. -- Id: C.10 function "<" (L: INTEGER; R: SIGNED) return BOOLEAN; -- Result subtype: BOOLEAN -- Result: Computes "L < R" where L is an INTEGER and -- R is a SIGNED vector. -- Id: C.11 function "<" (L: UNSIGNED; R: NATURAL) return BOOLEAN; -- Result subtype: BOOLEAN -- Result: Computes "L < R" where L is an UNSIGNED vector and -- R is a non-negative INTEGER. -- Id: C.12 function "<" (L: SIGNED; R: INTEGER) return BOOLEAN; -- Result subtype: BOOLEAN -- Result: Computes "L < R" where L is a SIGNED vector and -- R is an INTEGER. --============================================================================ -- Id: C.13 function "<=" (L, R: UNSIGNED) return BOOLEAN; -- Result subtype: BOOLEAN -- Result: Computes "L <= R" where L and R are UNSIGNED vectors possibly -- of different lengths. -- Id: C.14 function "<=" (L, R: SIGNED) return BOOLEAN; -- Result subtype: BOOLEAN -- Result: Computes "L <= R" where L and R are SIGNED vectors possibly -- of different lengths. -- Id: C.15 function "<=" (L: NATURAL; R: UNSIGNED) return BOOLEAN; -- Result subtype: BOOLEAN -- Result: Computes "L <= R" where L is a non-negative INTEGER and -- R is an UNSIGNED vector. -- Id: C.16 function "<=" (L: INTEGER; R: SIGNED) return BOOLEAN; -- Result subtype: BOOLEAN -- Result: Computes "L <= R" where L is an INTEGER and -- R is a SIGNED vector. -- Id: C.17 function "<=" (L: UNSIGNED; R: NATURAL) return BOOLEAN; -- Result subtype: BOOLEAN -- Result: Computes "L <= R" where L is an UNSIGNED vector and -- R is a non-negative INTEGER. -- Id: C.18 function "<=" (L: SIGNED; R: INTEGER) return BOOLEAN; -- Result subtype: BOOLEAN -- Result: Computes "L <= R" where L is a SIGNED vector and -- R is an INTEGER. --============================================================================ -- Id: C.19 function ">=" (L, R: UNSIGNED) return BOOLEAN; -- Result subtype: BOOLEAN -- Result: Computes "L >= R" where L and R are UNSIGNED vectors possibly -- of different lengths. -- Id: C.20 function ">=" (L, R: SIGNED) return BOOLEAN; -- Result subtype: BOOLEAN -- Result: Computes "L >= R" where L and R are SIGNED vectors possibly -- of different lengths. -- Id: C.21 function ">=" (L: NATURAL; R: UNSIGNED) return BOOLEAN; -- Result subtype: BOOLEAN -- Result: Computes "L >= R" where L is a non-negative INTEGER and -- R is an UNSIGNED vector. -- Id: C.22 function ">=" (L: INTEGER; R: SIGNED) return BOOLEAN; -- Result subtype: BOOLEAN -- Result: Computes "L >= R" where L is an INTEGER and -- R is a SIGNED vector. -- Id: C.23 function ">=" (L: UNSIGNED; R: NATURAL) return BOOLEAN; -- Result subtype: BOOLEAN -- Result: Computes "L >= R" where L is an UNSIGNED vector and -- R is a non-negative INTEGER. -- Id: C.24 function ">=" (L: SIGNED; R: INTEGER) return BOOLEAN; -- Result subtype: BOOLEAN -- Result: Computes "L >= R" where L is a SIGNED vector and -- R is an INTEGER. --============================================================================ -- Id: C.25 function "=" (L, R: UNSIGNED) return BOOLEAN; -- Result subtype: BOOLEAN -- Result: Computes "L = R" where L and R are UNSIGNED vectors possibly -- of different lengths. -- Id: C.26 function "=" (L, R: SIGNED) return BOOLEAN; -- Result subtype: BOOLEAN -- Result: Computes "L = R" where L and R are SIGNED vectors possibly -- of different lengths. -- Id: C.27 function "=" (L: NATURAL; R: UNSIGNED) return BOOLEAN; -- Result subtype: BOOLEAN -- Result: Computes "L = R" where L is a non-negative INTEGER and -- R is an UNSIGNED vector. -- Id: C.28 function "=" (L: INTEGER; R: SIGNED) return BOOLEAN; -- Result subtype: BOOLEAN -- Result: Computes "L = R" where L is an INTEGER and -- R is a SIGNED vector. -- Id: C.29 function "=" (L: UNSIGNED; R: NATURAL) return BOOLEAN; -- Result subtype: BOOLEAN -- Result: Computes "L = R" where L is an UNSIGNED vector and -- R is a non-negative INTEGER. -- Id: C.30 function "=" (L: SIGNED; R: INTEGER) return BOOLEAN; -- Result subtype: BOOLEAN -- Result: Computes "L = R" where L is a SIGNED vector and -- R is an INTEGER. --============================================================================ -- Id: C.31 function "/=" (L, R: UNSIGNED) return BOOLEAN; -- Result subtype: BOOLEAN -- Result: Computes "L /= R" where L and R are UNSIGNED vectors possibly -- of different lengths. -- Id: C.32 function "/=" (L, R: SIGNED) return BOOLEAN; -- Result subtype: BOOLEAN -- Result: Computes "L /= R" where L and R are SIGNED vectors possibly -- of different lengths. -- Id: C.33 function "/=" (L: NATURAL; R: UNSIGNED) return BOOLEAN; -- Result subtype: BOOLEAN -- Result: Computes "L /= R" where L is a non-negative INTEGER and -- R is an UNSIGNED vector. -- Id: C.34 function "/=" (L: INTEGER; R: SIGNED) return BOOLEAN; -- Result subtype: BOOLEAN -- Result: Computes "L /= R" where L is an INTEGER and -- R is a SIGNED vector. -- Id: C.35 function "/=" (L: UNSIGNED; R: NATURAL) return BOOLEAN; -- Result subtype: BOOLEAN -- Result: Computes "L /= R" where L is an UNSIGNED vector and -- R is a non-negative INTEGER. -- Id: C.36 function "/=" (L: SIGNED; R: INTEGER) return BOOLEAN; -- Result subtype: BOOLEAN -- Result: Computes "L /= R" where L is a SIGNED vector and -- R is an INTEGER. --============================================================================ -- Shift and Rotate Functions --============================================================================ -- Id: S.1 function SHIFT_LEFT (ARG: UNSIGNED; COUNT: NATURAL) return UNSIGNED; -- Result subtype: UNSIGNED(ARG'LENGTH-1 downto 0) -- Result: Performs a shift-left on an UNSIGNED vector COUNT times. -- The vacated positions are filled with '0'. -- The COUNT leftmost elements are lost. -- Id: S.2 function SHIFT_RIGHT (ARG: UNSIGNED; COUNT: NATURAL) return UNSIGNED; -- Result subtype: UNSIGNED(ARG'LENGTH-1 downto 0) -- Result: Performs a shift-right on an UNSIGNED vector COUNT times. -- The vacated positions are filled with '0'. -- The COUNT rightmost elements are lost. -- Id: S.3 function SHIFT_LEFT (ARG: SIGNED; COUNT: NATURAL) return SIGNED; -- Result subtype: SIGNED(ARG'LENGTH-1 downto 0) -- Result: Performs a shift-left on a SIGNED vector COUNT times. -- The vacated positions are filled with '0'. -- The COUNT leftmost elements are lost. -- Id: S.4 function SHIFT_RIGHT (ARG: SIGNED; COUNT: NATURAL) return SIGNED; -- Result subtype: SIGNED(ARG'LENGTH-1 downto 0) -- Result: Performs a shift-right on a SIGNED vector COUNT times. -- The vacated positions are filled with the leftmost -- element, ARG'LEFT. The COUNT rightmost elements are lost. --============================================================================ -- Id: S.5 function ROTATE_LEFT (ARG: UNSIGNED; COUNT: NATURAL) return UNSIGNED; -- Result subtype: UNSIGNED(ARG'LENGTH-1 downto 0) -- Result: Performs a rotate-left of an UNSIGNED vector COUNT times. -- Id: S.6 function ROTATE_RIGHT (ARG: UNSIGNED; COUNT: NATURAL) return UNSIGNED; -- Result subtype: UNSIGNED(ARG'LENGTH-1 downto 0) -- Result: Performs a rotate-right of an UNSIGNED vector COUNT times. -- Id: S.7 function ROTATE_LEFT (ARG: SIGNED; COUNT: NATURAL) return SIGNED; -- Result subtype: SIGNED(ARG'LENGTH-1 downto 0) -- Result: Performs a logical rotate-left of a SIGNED -- vector COUNT times. -- Id: S.8 function ROTATE_RIGHT (ARG: SIGNED; COUNT: NATURAL) return SIGNED; -- Result subtype: SIGNED(ARG'LENGTH-1 downto 0) -- Result: Performs a logical rotate-right of a SIGNED -- vector COUNT times. --============================================================================ --============================================================================ ------------------------------------------------------------------------------ -- Note : Function S.9 is not compatible with VHDL 1076-1987. Comment -- out the function (declaration and body) for VHDL 1076-1987 compatibility. ------------------------------------------------------------------------------ -- Id: S.9 function "sll" (ARG: UNSIGNED; COUNT: INTEGER) return UNSIGNED; --V93 -- Result subtype: UNSIGNED(ARG'LENGTH-1 downto 0) -- Result: SHIFT_LEFT(ARG, COUNT) ------------------------------------------------------------------------------ -- Note : Function S.10 is not compatible with VHDL 1076-1987. Comment -- out the function (declaration and body) for VHDL 1076-1987 compatibility. ------------------------------------------------------------------------------ -- Id: S.10 function "sll" (ARG: SIGNED; COUNT: INTEGER) return SIGNED; --V93 -- Result subtype: SIGNED(ARG'LENGTH-1 downto 0) -- Result: SHIFT_LEFT(ARG, COUNT) ------------------------------------------------------------------------------ -- Note : Function S.11 is not compatible with VHDL 1076-1987. Comment -- out the function (declaration and body) for VHDL 1076-1987 compatibility. ------------------------------------------------------------------------------ -- Id: S.11 function "srl" (ARG: UNSIGNED; COUNT: INTEGER) return UNSIGNED; --V93 -- Result subtype: UNSIGNED(ARG'LENGTH-1 downto 0) -- Result: SHIFT_RIGHT(ARG, COUNT) ------------------------------------------------------------------------------ -- Note : Function S.12 is not compatible with VHDL 1076-1987. Comment -- out the function (declaration and body) for VHDL 1076-1987 compatibility. ------------------------------------------------------------------------------ -- Id: S.12 function "srl" (ARG: SIGNED; COUNT: INTEGER) return SIGNED; --V93 -- Result subtype: SIGNED(ARG'LENGTH-1 downto 0) -- Result: SIGNED(SHIFT_RIGHT(UNSIGNED(ARG), COUNT)) ------------------------------------------------------------------------------ -- Note : Function S.13 is not compatible with VHDL 1076-1987. Comment -- out the function (declaration and body) for VHDL 1076-1987 compatibility. ------------------------------------------------------------------------------ -- Id: S.13 function "rol" (ARG: UNSIGNED; COUNT: INTEGER) return UNSIGNED; --V93 -- Result subtype: UNSIGNED(ARG'LENGTH-1 downto 0) -- Result: ROTATE_LEFT(ARG, COUNT) ------------------------------------------------------------------------------ -- Note : Function S.14 is not compatible with VHDL 1076-1987. Comment -- out the function (declaration and body) for VHDL 1076-1987 compatibility. ------------------------------------------------------------------------------ -- Id: S.14 function "rol" (ARG: SIGNED; COUNT: INTEGER) return SIGNED; --V93 -- Result subtype: SIGNED(ARG'LENGTH-1 downto 0) -- Result: ROTATE_LEFT(ARG, COUNT) ------------------------------------------------------------------------------ -- Note : Function S.15 is not compatible with VHDL 1076-1987. Comment -- out the function (declaration and body) for VHDL 1076-1987 compatibility. ------------------------------------------------------------------------------ -- Id: S.15 function "ror" (ARG: UNSIGNED; COUNT: INTEGER) return UNSIGNED; --V93 -- Result subtype: UNSIGNED(ARG'LENGTH-1 downto 0) -- Result: ROTATE_RIGHT(ARG, COUNT) ------------------------------------------------------------------------------ -- Note : Function S.16 is not compatible with VHDL 1076-1987. Comment -- out the function (declaration and body) for VHDL 1076-1987 compatibility. ------------------------------------------------------------------------------ -- Id: S.16 function "ror" (ARG: SIGNED; COUNT: INTEGER) return SIGNED; --V93 -- Result subtype: SIGNED(ARG'LENGTH-1 downto 0) -- Result: ROTATE_RIGHT(ARG, COUNT) --============================================================================ -- RESIZE Functions --============================================================================ -- Id: R.1 function RESIZE (ARG: SIGNED; NEW_SIZE: NATURAL) return SIGNED; -- Result subtype: SIGNED(NEW_SIZE-1 downto 0) -- Result: Resizes the SIGNED vector ARG to the specified size. -- To create a larger vector, the new [leftmost] bit positions -- are filled with the sign bit (ARG'LEFT). When truncating, -- the sign bit is retained along with the rightmost part. -- Id: R.2 function RESIZE (ARG: UNSIGNED; NEW_SIZE: NATURAL) return UNSIGNED; -- Result subtype: UNSIGNED(NEW_SIZE-1 downto 0) -- Result: Resizes the SIGNED vector ARG to the specified size. -- To create a larger vector, the new [leftmost] bit positions -- are filled with '0'. When truncating, the leftmost bits -- are dropped. --============================================================================ -- Conversion Functions --============================================================================ -- Id: D.1 function TO_INTEGER (ARG: UNSIGNED) return NATURAL; -- Result subtype: NATURAL. Value cannot be negative since parameter is an -- UNSIGNED vector. -- Result: Converts the UNSIGNED vector to an INTEGER. -- Id: D.2 function TO_INTEGER (ARG: SIGNED) return INTEGER; -- Result subtype: INTEGER -- Result: Converts a SIGNED vector to an INTEGER. -- Id: D.3 function TO_UNSIGNED (ARG, SIZE: NATURAL) return UNSIGNED; -- Result subtype: UNSIGNED(SIZE-1 downto 0) -- Result: Converts a non-negative INTEGER to an UNSIGNED vector with -- the specified SIZE. -- Id: D.4 function TO_SIGNED (ARG: INTEGER; SIZE: NATURAL) return SIGNED; -- Result subtype: SIGNED(SIZE-1 downto 0) -- Result: Converts an INTEGER to a SIGNED vector of the specified SIZE. --============================================================================ -- Logical Operators --============================================================================ -- Id: L.1 function "not" (L: UNSIGNED) return UNSIGNED; -- Result subtype: UNSIGNED(L'LENGTH-1 downto 0) -- Result: Termwise inversion -- Id: L.2 function "and" (L, R: UNSIGNED) return UNSIGNED; -- Result subtype: UNSIGNED(L'LENGTH-1 downto 0) -- Result: Vector AND operation -- Id: L.3 function "or" (L, R: UNSIGNED) return UNSIGNED; -- Result subtype: UNSIGNED(L'LENGTH-1 downto 0) -- Result: Vector OR operation -- Id: L.4 function "nand" (L, R: UNSIGNED) return UNSIGNED; -- Result subtype: UNSIGNED(L'LENGTH-1 downto 0) -- Result: Vector NAND operation -- Id: L.5 function "nor" (L, R: UNSIGNED) return UNSIGNED; -- Result subtype: UNSIGNED(L'LENGTH-1 downto 0) -- Result: Vector NOR operation -- Id: L.6 function "xor" (L, R: UNSIGNED) return UNSIGNED; -- Result subtype: UNSIGNED(L'LENGTH-1 downto 0) -- Result: Vector XOR operation -- --------------------------------------------------------------------------- -- Note : Function L.7 is not compatible with VHDL 1076-1987. Comment -- out the function (declaration and body) for VHDL 1076-1987 compatibility. -- --------------------------------------------------------------------------- -- Id: L.7 function "xnor" (L, R: UNSIGNED) return UNSIGNED; --V93 -- Result subtype: UNSIGNED(L'LENGTH-1 downto 0) -- Result: Vector XNOR operation -- Id: L.8 function "not" (L: SIGNED) return SIGNED; -- Result subtype: SIGNED(L'LENGTH-1 downto 0) -- Result: Termwise inversion -- Id: L.9 function "and" (L, R: SIGNED) return SIGNED; -- Result subtype: SIGNED(L'LENGTH-1 downto 0) -- Result: Vector AND operation -- Id: L.10 function "or" (L, R: SIGNED) return SIGNED; -- Result subtype: SIGNED(L'LENGTH-1 downto 0) -- Result: Vector OR operation -- Id: L.11 function "nand" (L, R: SIGNED) return SIGNED; -- Result subtype: SIGNED(L'LENGTH-1 downto 0) -- Result: Vector NAND operation -- Id: L.12 function "nor" (L, R: SIGNED) return SIGNED; -- Result subtype: SIGNED(L'LENGTH-1 downto 0) -- Result: Vector NOR operation -- Id: L.13 function "xor" (L, R: SIGNED) return SIGNED; -- Result subtype: SIGNED(L'LENGTH-1 downto 0) -- Result: Vector XOR operation -- --------------------------------------------------------------------------- -- Note : Function L.14 is not compatible with VHDL 1076-1987. Comment -- out the function (declaration and body) for VHDL 1076-1987 compatibility. -- --------------------------------------------------------------------------- -- Id: L.14 function "xnor" (L, R: SIGNED) return SIGNED; --V93 -- Result subtype: SIGNED(L'LENGTH-1 downto 0) -- Result: Vector XNOR operation --============================================================================ -- Match Functions --============================================================================ -- Id: M.1 function STD_MATCH (L, R: STD_ULOGIC) return BOOLEAN; -- Result subtype: BOOLEAN -- Result: terms compared per STD_LOGIC_1164 intent -- Id: M.2 function STD_MATCH (L, R: UNSIGNED) return BOOLEAN; -- Result subtype: BOOLEAN -- Result: terms compared per STD_LOGIC_1164 intent -- Id: M.3 function STD_MATCH (L, R: SIGNED) return BOOLEAN; -- Result subtype: BOOLEAN -- Result: terms compared per STD_LOGIC_1164 intent -- Id: M.4 function STD_MATCH (L, R: STD_LOGIC_VECTOR) return BOOLEAN; -- Result subtype: BOOLEAN -- Result: terms compared per STD_LOGIC_1164 intent -- Id: M.5 function STD_MATCH (L, R: STD_ULOGIC_VECTOR) return BOOLEAN; -- Result subtype: BOOLEAN -- Result: terms compared per STD_LOGIC_1164 intent --============================================================================ -- Translation Functions --============================================================================ -- Id: T.1 function TO_01 (S: UNSIGNED; XMAP: STD_LOGIC := '0') return UNSIGNED; -- Result subtype: UNSIGNED(S'RANGE) -- Result: Termwise, 'H' is translated to '1', and 'L' is translated -- to '0'. If a value other than '0'|'1'|'H'|'L' is found, -- the array is set to (others => XMAP), and a warning is -- issued. -- Id: T.2 function TO_01 (S: SIGNED; XMAP: STD_LOGIC := '0') return SIGNED; -- Result subtype: SIGNED(S'RANGE) -- Result: Termwise, 'H' is translated to '1', and 'L' is translated -- to '0'. If a value other than '0'|'1'|'H'|'L' is found, -- the array is set to (others => XMAP), and a warning is -- issued. end NUMERIC_STD; -- -------------------------------------------------------------------- -- -- Copyright 1995 by IEEE. All rights reserved. -- -- This source file is considered by the IEEE to be an essential part of the use -- of the standard 1076.3 and as such may be distributed without change, except -- as permitted by the standard. This source file may not be sold or distributed -- for profit. This package may be modified to include additional data required -- by tools, but must in no way change the external interfaces or simulation -- behaviour of the description. It is permissible to add comments and/or -- attributes to the package declarations, but not to change or delete any -- original lines of the approved package declaration. The package body may be -- changed only in accordance with the terms of clauses 7.1 and 7.2 of the -- standard. -- -- Title : Standard VHDL Synthesis Package (1076.3, NUMERIC_STD) -- -- Library : This package shall be compiled into a library symbolically -- : named IEEE. -- -- Developers : IEEE DASC Synthesis Working Group, PAR 1076.3 -- -- Purpose : This package defines numeric types and arithmetic functions -- : for use with synthesis tools. Two numeric types are defined: -- : -- > UNSIGNED: represents UNSIGNED number in vector form -- : -- > SIGNED: represents a SIGNED number in vector form -- : The base element type is type STD_LOGIC. -- : The leftmost bit is treated as the most significant bit. -- : Signed vectors are represented in two's complement form. -- : This package contains overloaded arithmetic operators on -- : the SIGNED and UNSIGNED types. The package also contains -- : useful type conversions functions. -- : -- : If any argument to a function is a null array, a null array is -- : returned (exceptions, if any, are noted individually). -- -- Limitation : -- -- Note : No declarations or definitions shall be included in, -- : or excluded from this package. The "package declaration" -- : defines the types, subtypes and declarations of -- : NUMERIC_STD. The NUMERIC_STD package body shall be -- : considered the formal definition of the semantics of -- : this package. Tool developers may choose to implement -- : the package body in the most efficient manner available -- : to them. -- -- -------------------------------------------------------------------- -- modification history : -- -------------------------------------------------------------------- -- Version: 2.4 -- Date : 12 April 1995 -- ----------------------------------------------------------------------------- --============================================================================== --============================= Package Body =================================== --============================================================================== package body NUMERIC_STD is -- null range array constants constant NAU: UNSIGNED(0 downto 1) := (others => '0'); constant NAS: SIGNED(0 downto 1) := (others => '0'); -- implementation controls constant NO_WARNING: BOOLEAN := FALSE; -- default to emit warnings --=========================Local Subprograms ================================= function MAX (LEFT, RIGHT: INTEGER) return INTEGER is begin if LEFT > RIGHT then return LEFT; else return RIGHT; end if; end MAX; function MIN (LEFT, RIGHT: INTEGER) return INTEGER is begin if LEFT < RIGHT then return LEFT; else return RIGHT; end if; end MIN; function SIGNED_NUM_BITS (ARG: INTEGER) return NATURAL is variable NBITS: NATURAL; variable N: NATURAL; begin if ARG >= 0 then N := ARG; else N := -(ARG+1); end if; NBITS := 1; while N > 0 loop NBITS := NBITS+1; N := N / 2; end loop; return NBITS; end SIGNED_NUM_BITS; function UNSIGNED_NUM_BITS (ARG: NATURAL) return NATURAL is variable NBITS: NATURAL; variable N: NATURAL; begin N := ARG; NBITS := 1; while N > 1 loop NBITS := NBITS+1; N := N / 2; end loop; return NBITS; end UNSIGNED_NUM_BITS; ------------------------------------------------------------------------ -- this internal function computes the addition of two UNSIGNED -- with input CARRY -- * the two arguments are of the same length function ADD_UNSIGNED (L, R: UNSIGNED; C: STD_LOGIC) return UNSIGNED is constant L_LEFT: INTEGER := L'LENGTH-1; alias XL: UNSIGNED(L_LEFT downto 0) is L; alias XR: UNSIGNED(L_LEFT downto 0) is R; variable RESULT: UNSIGNED(L_LEFT downto 0); variable CBIT: STD_LOGIC := C; begin for I in 0 to L_LEFT loop RESULT(I) := CBIT xor XL(I) xor XR(I); CBIT := (CBIT and XL(I)) or (CBIT and XR(I)) or (XL(I) and XR(I)); end loop; return RESULT; end ADD_UNSIGNED; -- this internal function computes the addition of two SIGNED -- with input CARRY -- * the two arguments are of the same length function ADD_SIGNED (L, R: SIGNED; C: STD_LOGIC) return SIGNED is constant L_LEFT: INTEGER := L'LENGTH-1; alias XL: SIGNED(L_LEFT downto 0) is L; alias XR: SIGNED(L_LEFT downto 0) is R; variable RESULT: SIGNED(L_LEFT downto 0); variable CBIT: STD_LOGIC := C; begin for I in 0 to L_LEFT loop RESULT(I) := CBIT xor XL(I) xor XR(I); CBIT := (CBIT and XL(I)) or (CBIT and XR(I)) or (XL(I) and XR(I)); end loop; return RESULT; end ADD_SIGNED; ----------------------------------------------------------------------------- -- this internal procedure computes UNSIGNED division -- giving the quotient and remainder. procedure DIVMOD (NUM, XDENOM: UNSIGNED; XQUOT, XREMAIN: out UNSIGNED) is variable TEMP: UNSIGNED(NUM'LENGTH downto 0); variable QUOT: UNSIGNED(MAX(NUM'LENGTH, XDENOM'LENGTH)-1 downto 0); alias DENOM: UNSIGNED(XDENOM'LENGTH-1 downto 0) is XDENOM; variable TOPBIT: INTEGER; begin TEMP := "0"&NUM; QUOT := (others => '0'); TOPBIT := -1; for J in DENOM'RANGE loop if DENOM(J)='1' then TOPBIT := J; exit; end if; end loop; assert TOPBIT >= 0 report "DIV, MOD, or REM by zero" severity ERROR; for J in NUM'LENGTH-(TOPBIT+1) downto 0 loop if TEMP(TOPBIT+J+1 downto J) >= "0"&DENOM(TOPBIT downto 0) then TEMP(TOPBIT+J+1 downto J) := (TEMP(TOPBIT+J+1 downto J)) -("0"&DENOM(TOPBIT downto 0)); QUOT(J) := '1'; end if; assert TEMP(TOPBIT+J+1)='0' report "internal error in the division algorithm" severity ERROR; end loop; XQUOT := RESIZE(QUOT, XQUOT'LENGTH); XREMAIN := RESIZE(TEMP, XREMAIN'LENGTH); end DIVMOD; -----------------Local Subprograms - shift/rotate ops------------------------- function XSLL (ARG: STD_LOGIC_VECTOR; COUNT: NATURAL) return STD_LOGIC_VECTOR is constant ARG_L: INTEGER := ARG'LENGTH-1; alias XARG: STD_LOGIC_VECTOR(ARG_L downto 0) is ARG; variable RESULT: STD_LOGIC_VECTOR(ARG_L downto 0) := (others => '0'); begin if COUNT <= ARG_L then RESULT(ARG_L downto COUNT) := XARG(ARG_L-COUNT downto 0); end if; return RESULT; end XSLL; function XSRL (ARG: STD_LOGIC_VECTOR; COUNT: NATURAL) return STD_LOGIC_VECTOR is constant ARG_L: INTEGER := ARG'LENGTH-1; alias XARG: STD_LOGIC_VECTOR(ARG_L downto 0) is ARG; variable RESULT: STD_LOGIC_VECTOR(ARG_L downto 0) := (others => '0'); begin if COUNT <= ARG_L then RESULT(ARG_L-COUNT downto 0) := XARG(ARG_L downto COUNT); end if; return RESULT; end XSRL; function XSRA (ARG: STD_LOGIC_VECTOR; COUNT: NATURAL) return STD_LOGIC_VECTOR is constant ARG_L: INTEGER := ARG'LENGTH-1; alias XARG: STD_LOGIC_VECTOR(ARG_L downto 0) is ARG; variable RESULT: STD_LOGIC_VECTOR(ARG_L downto 0); variable XCOUNT: NATURAL := COUNT; begin if ((ARG'LENGTH <= 1) or (XCOUNT = 0)) then return ARG; else if (XCOUNT > ARG_L) then XCOUNT := ARG_L; end if; RESULT(ARG_L-XCOUNT downto 0) := XARG(ARG_L downto XCOUNT); RESULT(ARG_L downto (ARG_L - XCOUNT + 1)) := (others => XARG(ARG_L)); end if; return RESULT; end XSRA; function XROL (ARG: STD_LOGIC_VECTOR; COUNT: NATURAL) return STD_LOGIC_VECTOR is constant ARG_L: INTEGER := ARG'LENGTH-1; alias XARG: STD_LOGIC_VECTOR(ARG_L downto 0) is ARG; variable RESULT: STD_LOGIC_VECTOR(ARG_L downto 0) := XARG; variable COUNTM: INTEGER; begin COUNTM := COUNT mod (ARG_L + 1); if COUNTM /= 0 then RESULT(ARG_L downto COUNTM) := XARG(ARG_L-COUNTM downto 0); RESULT(COUNTM-1 downto 0) := XARG(ARG_L downto ARG_L-COUNTM+1); end if; return RESULT; end XROL; function XROR (ARG: STD_LOGIC_VECTOR; COUNT: NATURAL) return STD_LOGIC_VECTOR is constant ARG_L: INTEGER := ARG'LENGTH-1; alias XARG: STD_LOGIC_VECTOR(ARG_L downto 0) is ARG; variable RESULT: STD_LOGIC_VECTOR(ARG_L downto 0) := XARG; variable COUNTM: INTEGER; begin COUNTM := COUNT mod (ARG_L + 1); if COUNTM /= 0 then RESULT(ARG_L-COUNTM downto 0) := XARG(ARG_L downto COUNTM); RESULT(ARG_L downto ARG_L-COUNTM+1) := XARG(COUNTM-1 downto 0); end if; return RESULT; end XROR; -----------------Local Subprograms - Relational ops--------------------------- -- -- General "=" for UNSIGNED vectors, same length -- function UNSIGNED_EQUAL (L, R: UNSIGNED) return BOOLEAN is begin return STD_LOGIC_VECTOR(L) = STD_LOGIC_VECTOR(R); end UNSIGNED_EQUAL; -- -- General "=" for SIGNED vectors, same length -- function SIGNED_EQUAL (L, R: SIGNED) return BOOLEAN is begin return STD_LOGIC_VECTOR(L) = STD_LOGIC_VECTOR(R); end SIGNED_EQUAL; -- -- General "<" for UNSIGNED vectors, same length -- function UNSIGNED_LESS (L, R: UNSIGNED) return BOOLEAN is begin return STD_LOGIC_VECTOR(L) < STD_LOGIC_VECTOR(R); end UNSIGNED_LESS; -- -- General "<" function for SIGNED vectors, same length -- function SIGNED_LESS (L, R: SIGNED) return BOOLEAN is variable INTERN_L: SIGNED(0 to L'LENGTH-1); variable INTERN_R: SIGNED(0 to R'LENGTH-1); begin INTERN_L := L; INTERN_R := R; INTERN_L(0) := not INTERN_L(0); INTERN_R(0) := not INTERN_R(0); return STD_LOGIC_VECTOR(INTERN_L) < STD_LOGIC_VECTOR(INTERN_R); end SIGNED_LESS; -- -- General "<=" function for UNSIGNED vectors, same length -- function UNSIGNED_LESS_OR_EQUAL (L, R: UNSIGNED) return BOOLEAN is begin return STD_LOGIC_VECTOR(L) <= STD_LOGIC_VECTOR(R); end UNSIGNED_LESS_OR_EQUAL; -- -- General "<=" function for SIGNED vectors, same length -- function SIGNED_LESS_OR_EQUAL (L, R: SIGNED) return BOOLEAN is -- Need aliases to assure index direction variable INTERN_L: SIGNED(0 to L'LENGTH-1); variable INTERN_R: SIGNED(0 to R'LENGTH-1); begin INTERN_L := L; INTERN_R := R; INTERN_L(0) := not INTERN_L(0); INTERN_R(0) := not INTERN_R(0); return STD_LOGIC_VECTOR(INTERN_L) <= STD_LOGIC_VECTOR(INTERN_R); end SIGNED_LESS_OR_EQUAL; --=========================Exported Functions ========================== -- Id: A.1 function "abs" (ARG: SIGNED) return SIGNED is constant ARG_LEFT: INTEGER := ARG'LENGTH-1; alias XARG: SIGNED(ARG_LEFT downto 0) is ARG; variable RESULT: SIGNED(ARG_LEFT downto 0); begin if ARG'LENGTH < 1 then return NAS; end if; RESULT := TO_01(XARG, 'X'); if (RESULT(RESULT'LEFT)='X') then return RESULT; end if; if RESULT(RESULT'LEFT) = '1' then RESULT := -RESULT; end if; return RESULT; end "abs"; -- Id: A.2 function "-" (ARG: SIGNED) return SIGNED is constant ARG_LEFT: INTEGER := ARG'LENGTH-1; alias XARG: SIGNED(ARG_LEFT downto 0) is ARG; variable RESULT, XARG01 : SIGNED(ARG_LEFT downto 0); variable CBIT: STD_LOGIC := '1'; begin if ARG'LENGTH < 1 then return NAS; end if; XARG01 := TO_01(ARG, 'X'); if (XARG01(XARG01'LEFT)='X') then return XARG01; end if; for I in 0 to RESULT'LEFT loop RESULT(I) := not(XARG01(I)) xor CBIT; CBIT := CBIT and not(XARG01(I)); end loop; return RESULT; end "-"; --============================================================================ -- Id: A.3 function "+" (L, R: UNSIGNED) return UNSIGNED is constant SIZE: NATURAL := MAX(L'LENGTH, R'LENGTH); variable L01 : UNSIGNED(SIZE-1 downto 0); variable R01 : UNSIGNED(SIZE-1 downto 0); begin if ((L'LENGTH < 1) or (R'LENGTH < 1)) then return NAU; end if; L01 := TO_01(RESIZE(L, SIZE), 'X'); if (L01(L01'LEFT)='X') then return L01; end if; R01 := TO_01(RESIZE(R, SIZE), 'X'); if (R01(R01'LEFT)='X') then return R01; end if; return ADD_UNSIGNED(L01, R01, '0'); end "+"; -- Id: A.4 function "+" (L, R: SIGNED) return SIGNED is constant SIZE: NATURAL := MAX(L'LENGTH, R'LENGTH); variable L01 : SIGNED(SIZE-1 downto 0); variable R01 : SIGNED(SIZE-1 downto 0); begin if ((L'LENGTH < 1) or (R'LENGTH < 1)) then return NAS; end if; L01 := TO_01(RESIZE(L, SIZE), 'X'); if (L01(L01'LEFT)='X') then return L01; end if; R01 := TO_01(RESIZE(R, SIZE), 'X'); if (R01(R01'LEFT)='X') then return R01; end if; return ADD_SIGNED(L01, R01, '0'); end "+"; -- Id: A.5 function "+" (L: UNSIGNED; R: NATURAL) return UNSIGNED is begin return L + TO_UNSIGNED(R, L'LENGTH); end "+"; -- Id: A.6 function "+" (L: NATURAL; R: UNSIGNED) return UNSIGNED is begin return TO_UNSIGNED(L, R'LENGTH) + R; end "+"; -- Id: A.7 function "+" (L: SIGNED; R: INTEGER) return SIGNED is begin return L + TO_SIGNED(R, L'LENGTH); end "+"; -- Id: A.8 function "+" (L: INTEGER; R: SIGNED) return SIGNED is begin return TO_SIGNED(L, R'LENGTH) + R; end "+"; --============================================================================ -- Id: A.9 function "-" (L, R: UNSIGNED) return UNSIGNED is constant SIZE: NATURAL := MAX(L'LENGTH, R'LENGTH); variable L01 : UNSIGNED(SIZE-1 downto 0); variable R01 : UNSIGNED(SIZE-1 downto 0); begin if ((L'LENGTH < 1) or (R'LENGTH < 1)) then return NAU; end if; L01 := TO_01(RESIZE(L, SIZE), 'X'); if (L01(L01'LEFT)='X') then return L01; end if; R01 := TO_01(RESIZE(R, SIZE), 'X'); if (R01(R01'LEFT)='X') then return R01; end if; return ADD_UNSIGNED(L01, not(R01), '1'); end "-"; -- Id: A.10 function "-" (L, R: SIGNED) return SIGNED is constant SIZE: NATURAL := MAX(L'LENGTH, R'LENGTH); variable L01 : SIGNED(SIZE-1 downto 0); variable R01 : SIGNED(SIZE-1 downto 0); begin if ((L'LENGTH < 1) or (R'LENGTH < 1)) then return NAS; end if; L01 := TO_01(RESIZE(L, SIZE), 'X'); if (L01(L01'LEFT)='X') then return L01; end if; R01 := TO_01(RESIZE(R, SIZE), 'X'); if (R01(R01'LEFT)='X') then return R01; end if; return ADD_SIGNED(L01, not(R01), '1'); end "-"; -- Id: A.11 function "-" (L: UNSIGNED; R: NATURAL) return UNSIGNED is begin return L - TO_UNSIGNED(R, L'LENGTH); end "-"; -- Id: A.12 function "-" (L: NATURAL; R: UNSIGNED) return UNSIGNED is begin return TO_UNSIGNED(L, R'LENGTH) - R; end "-"; -- Id: A.13 function "-" (L: SIGNED; R: INTEGER) return SIGNED is begin return L - TO_SIGNED(R, L'LENGTH); end "-"; -- Id: A.14 function "-" (L: INTEGER; R: SIGNED) return SIGNED is begin return TO_SIGNED(L, R'LENGTH) - R; end "-"; --============================================================================ -- Id: A.15 function "*" (L, R: UNSIGNED) return UNSIGNED is constant L_LEFT: INTEGER := L'LENGTH-1; constant R_LEFT: INTEGER := R'LENGTH-1; alias XXL: UNSIGNED(L_LEFT downto 0) is L; alias XXR: UNSIGNED(R_LEFT downto 0) is R; variable XL: UNSIGNED(L_LEFT downto 0); variable XR: UNSIGNED(R_LEFT downto 0); variable RESULT: UNSIGNED((L'LENGTH+R'LENGTH-1) downto 0) := (others => '0'); variable ADVAL: UNSIGNED((L'LENGTH+R'LENGTH-1) downto 0); begin if ((L'LENGTH < 1) or (R'LENGTH < 1)) then return NAU; end if; XL := TO_01(XXL, 'X'); XR := TO_01(XXR, 'X'); if ((XL(XL'LEFT)='X') or (XR(XR'LEFT)='X')) then RESULT := (others => 'X'); return RESULT; end if; ADVAL := RESIZE(XR, RESULT'LENGTH); for I in 0 to L_LEFT loop if XL(I)='1' then RESULT := RESULT + ADVAL; end if; ADVAL := SHIFT_LEFT(ADVAL, 1); end loop; return RESULT; end "*"; -- Id: A.16 function "*" (L, R: SIGNED) return SIGNED is constant L_LEFT: INTEGER := L'LENGTH-1; constant R_LEFT: INTEGER := R'LENGTH-1; variable XL: SIGNED(L_LEFT downto 0); variable XR: SIGNED(R_LEFT downto 0); variable RESULT: SIGNED((L_LEFT+R_LEFT+1) downto 0) := (others => '0'); variable ADVAL: SIGNED((L_LEFT+R_LEFT+1) downto 0); begin if ((L_LEFT < 0) or (R_LEFT < 0)) then return NAS; end if; XL := TO_01(L, 'X'); XR := TO_01(R, 'X'); if ((XL(L_LEFT)='X') or (XR(R_LEFT)='X')) then RESULT := (others => 'X'); return RESULT; end if; ADVAL := RESIZE(XR, RESULT'LENGTH); for I in 0 to L_LEFT-1 loop if XL(I)='1' then RESULT := RESULT + ADVAL; end if; ADVAL := SHIFT_LEFT(ADVAL, 1); end loop; if XL(L_LEFT)='1' then RESULT := RESULT - ADVAL; end if; return RESULT; end "*"; -- Id: A.17 function "*" (L: UNSIGNED; R: NATURAL) return UNSIGNED is begin return L * TO_UNSIGNED(R, L'LENGTH); end "*"; -- Id: A.18 function "*" (L: NATURAL; R: UNSIGNED) return UNSIGNED is begin return TO_UNSIGNED(L, R'LENGTH) * R; end "*"; -- Id: A.19 function "*" (L: SIGNED; R: INTEGER) return SIGNED is begin return L * TO_SIGNED(R, L'LENGTH); end "*"; -- Id: A.20 function "*" (L: INTEGER; R: SIGNED) return SIGNED is begin return TO_SIGNED(L, R'LENGTH) * R; end "*"; --============================================================================ -- Id: A.21 function "/" (L, R: UNSIGNED) return UNSIGNED is constant L_LEFT: INTEGER := L'LENGTH-1; constant R_LEFT: INTEGER := R'LENGTH-1; alias XXL: UNSIGNED(L_LEFT downto 0) is L; alias XXR: UNSIGNED(R_LEFT downto 0) is R; variable XL: UNSIGNED(L_LEFT downto 0); variable XR: UNSIGNED(R_LEFT downto 0); variable FQUOT: UNSIGNED(L'LENGTH-1 downto 0); variable FREMAIN: UNSIGNED(R'LENGTH-1 downto 0); begin if ((L'LENGTH < 1) or (R'LENGTH < 1)) then return NAU; end if; XL := TO_01(XXL, 'X'); XR := TO_01(XXR, 'X'); if ((XL(XL'LEFT)='X') or (XR(XR'LEFT)='X')) then FQUOT := (others => 'X'); return FQUOT; end if; DIVMOD(XL, XR, FQUOT, FREMAIN); return FQUOT; end "/"; -- Id: A.22 function "/" (L, R: SIGNED) return SIGNED is constant L_LEFT: INTEGER := L'LENGTH-1; constant R_LEFT: INTEGER := R'LENGTH-1; alias XXL: SIGNED(L_LEFT downto 0) is L; alias XXR: SIGNED(R_LEFT downto 0) is R; variable XL: SIGNED(L_LEFT downto 0); variable XR: SIGNED(R_LEFT downto 0); variable FQUOT: UNSIGNED(L'LENGTH-1 downto 0); variable FREMAIN: UNSIGNED(R'LENGTH-1 downto 0); variable XNUM: UNSIGNED(L'LENGTH-1 downto 0); variable XDENOM: UNSIGNED(R'LENGTH-1 downto 0); variable QNEG: BOOLEAN := FALSE; begin if ((L'LENGTH < 1) or (R'LENGTH < 1)) then return NAS; end if; XL := TO_01(XXL, 'X'); XR := TO_01(XXR, 'X'); if ((XL(XL'LEFT)='X') or (XR(XR'LEFT)='X')) then FQUOT := (others => 'X'); return SIGNED(FQUOT); end if; if XL(XL'LEFT)='1' then XNUM := UNSIGNED(-XL); QNEG := TRUE; else XNUM := UNSIGNED(XL); end if; if XR(XR'LEFT)='1' then XDENOM := UNSIGNED(-XR); QNEG := not QNEG; else XDENOM := UNSIGNED(XR); end if; DIVMOD(XNUM, XDENOM, FQUOT, FREMAIN); if QNEG then FQUOT := "0"-FQUOT; end if; return SIGNED(FQUOT); end "/"; -- Id: A.23 function "/" (L: UNSIGNED; R: NATURAL) return UNSIGNED is constant R_LENGTH: NATURAL := MAX(L'LENGTH, UNSIGNED_NUM_BITS(R)); variable XR, QUOT: UNSIGNED(R_LENGTH-1 downto 0); begin if (L'LENGTH < 1) then return NAU; end if; if (R_LENGTH > L'LENGTH) then QUOT := (others => '0'); return RESIZE(QUOT, L'LENGTH); end if; XR := TO_UNSIGNED(R, R_LENGTH); QUOT := RESIZE((L / XR), QUOT'LENGTH); return RESIZE(QUOT, L'LENGTH); end "/"; -- Id: A.24 function "/" (L: NATURAL; R: UNSIGNED) return UNSIGNED is constant L_LENGTH: NATURAL := MAX(UNSIGNED_NUM_BITS(L), R'LENGTH); variable XL, QUOT: UNSIGNED(L_LENGTH-1 downto 0); begin if (R'LENGTH < 1) then return NAU; end if; XL := TO_UNSIGNED(L, L_LENGTH); QUOT := RESIZE((XL / R), QUOT'LENGTH); if L_LENGTH > R'LENGTH and QUOT(0)/='X' and QUOT(L_LENGTH-1 downto R'LENGTH) /= (L_LENGTH-1 downto R'LENGTH => '0') then assert NO_WARNING report "NUMERIC_STD.""/"": Quotient Truncated" severity WARNING; end if; return RESIZE(QUOT, R'LENGTH); end "/"; -- Id: A.25 function "/" (L: SIGNED; R: INTEGER) return SIGNED is constant R_LENGTH: NATURAL := MAX(L'LENGTH, SIGNED_NUM_BITS(R)); variable XR, QUOT: SIGNED(R_LENGTH-1 downto 0); begin if (L'LENGTH < 1) then return NAS; end if; if (R_LENGTH > L'LENGTH) then QUOT := (others => '0'); return RESIZE(QUOT, L'LENGTH); end if; XR := TO_SIGNED(R, R_LENGTH); QUOT := RESIZE((L / XR), QUOT'LENGTH); return RESIZE(QUOT, L'LENGTH); end "/"; -- Id: A.26 function "/" (L: INTEGER; R: SIGNED) return SIGNED is constant L_LENGTH: NATURAL := MAX(SIGNED_NUM_BITS(L), R'LENGTH); variable XL, QUOT: SIGNED(L_LENGTH-1 downto 0); begin if (R'LENGTH < 1) then return NAS; end if; XL := TO_SIGNED(L, L_LENGTH); QUOT := RESIZE((XL / R), QUOT'LENGTH); if L_LENGTH > R'LENGTH and QUOT(0)/='X' and QUOT(L_LENGTH-1 downto R'LENGTH) /= (L_LENGTH-1 downto R'LENGTH => QUOT(R'LENGTH-1)) then assert NO_WARNING report "NUMERIC_STD.""/"": Quotient Truncated" severity WARNING; end if; return RESIZE(QUOT, R'LENGTH); end "/"; --============================================================================ -- Id: A.27 function "rem" (L, R: UNSIGNED) return UNSIGNED is constant L_LEFT: INTEGER := L'LENGTH-1; constant R_LEFT: INTEGER := R'LENGTH-1; alias XXL: UNSIGNED(L_LEFT downto 0) is L; alias XXR: UNSIGNED(R_LEFT downto 0) is R; variable XL: UNSIGNED(L_LEFT downto 0); variable XR: UNSIGNED(R_LEFT downto 0); variable FQUOT: UNSIGNED(L'LENGTH-1 downto 0); variable FREMAIN: UNSIGNED(R'LENGTH-1 downto 0); begin if ((L'LENGTH < 1) or (R'LENGTH < 1)) then return NAU; end if; XL := TO_01(XXL, 'X'); XR := TO_01(XXR, 'X'); if ((XL(XL'LEFT)='X') or (XR(XR'LEFT)='X')) then FREMAIN := (others => 'X'); return FREMAIN; end if; DIVMOD(XL, XR, FQUOT, FREMAIN); return FREMAIN; end "rem"; -- Id: A.28 function "rem" (L, R: SIGNED) return SIGNED is constant L_LEFT: INTEGER := L'LENGTH-1; constant R_LEFT: INTEGER := R'LENGTH-1; alias XXL: SIGNED(L_LEFT downto 0) is L; alias XXR: SIGNED(R_LEFT downto 0) is R; variable FQUOT: UNSIGNED(L'LENGTH-1 downto 0); variable FREMAIN: UNSIGNED(R'LENGTH-1 downto 0); variable XNUM: UNSIGNED(L'LENGTH-1 downto 0); variable XDENOM: UNSIGNED(R'LENGTH-1 downto 0); variable RNEG: BOOLEAN := FALSE; begin if ((L'LENGTH < 1) or (R'LENGTH < 1)) then return NAS; end if; XNUM := UNSIGNED(TO_01(XXL, 'X')); XDENOM := UNSIGNED(TO_01(XXR, 'X')); if ((XNUM(XNUM'LEFT)='X') or (XDENOM(XDENOM'LEFT)='X')) then FREMAIN := (others => 'X'); return SIGNED(FREMAIN); end if; if XNUM(XNUM'LEFT)='1' then XNUM := UNSIGNED(-SIGNED(XNUM)); RNEG := TRUE; else XNUM := UNSIGNED(XNUM); end if; if XDENOM(XDENOM'LEFT)='1' then XDENOM := UNSIGNED(-SIGNED(XDENOM)); else XDENOM := UNSIGNED(XDENOM); end if; DIVMOD(XNUM, XDENOM, FQUOT, FREMAIN); if RNEG then FREMAIN := "0"-FREMAIN; end if; return SIGNED(FREMAIN); end "rem"; -- Id: A.29 function "rem" (L: UNSIGNED; R: NATURAL) return UNSIGNED is constant R_LENGTH: NATURAL := MAX(L'LENGTH, UNSIGNED_NUM_BITS(R)); variable XR, XREM: UNSIGNED(R_LENGTH-1 downto 0); begin if (L'LENGTH < 1) then return NAU; end if; XR := TO_UNSIGNED(R, R_LENGTH); XREM := L rem XR; if R_LENGTH > L'LENGTH and XREM(0)/='X' and XREM(R_LENGTH-1 downto L'LENGTH) /= (R_LENGTH-1 downto L'LENGTH => '0') then assert NO_WARNING report "NUMERIC_STD.""rem"": Remainder Truncated" severity WARNING; end if; return RESIZE(XREM, L'LENGTH); end "rem"; -- Id: A.30 function "rem" (L: NATURAL; R: UNSIGNED) return UNSIGNED is constant L_LENGTH: NATURAL := MAX(UNSIGNED_NUM_BITS(L), R'LENGTH); variable XL, XREM: UNSIGNED(L_LENGTH-1 downto 0); begin XL := TO_UNSIGNED(L, L_LENGTH); XREM := XL rem R; if L_LENGTH > R'LENGTH and XREM(0)/='X' and XREM(L_LENGTH-1 downto R'LENGTH) /= (L_LENGTH-1 downto R'LENGTH => '0') then assert NO_WARNING report "NUMERIC_STD.""rem"": Remainder Truncated" severity WARNING; end if; return RESIZE(XREM, R'LENGTH); end "rem"; -- Id: A.31 function "rem" (L: SIGNED; R: INTEGER) return SIGNED is constant R_LENGTH: NATURAL := MAX(L'LENGTH, SIGNED_NUM_BITS(R)); variable XR, XREM: SIGNED(R_LENGTH-1 downto 0); begin if (L'LENGTH < 1) then return NAS; end if; XR := TO_SIGNED(R, R_LENGTH); XREM := RESIZE((L rem XR), XREM'LENGTH); if R_LENGTH > L'LENGTH and XREM(0)/='X' and XREM(R_LENGTH-1 downto L'LENGTH) /= (R_LENGTH-1 downto L'LENGTH => XREM(L'LENGTH-1)) then assert NO_WARNING report "NUMERIC_STD.""rem"": Remainder Truncated" severity WARNING; end if; return RESIZE(XREM, L'LENGTH); end "rem"; -- Id: A.32 function "rem" (L: INTEGER; R: SIGNED) return SIGNED is constant L_LENGTH: NATURAL := MAX(SIGNED_NUM_BITS(L), R'LENGTH); variable XL, XREM: SIGNED(L_LENGTH-1 downto 0); begin if (R'LENGTH < 1) then return NAS; end if; XL := TO_SIGNED(L, L_LENGTH); XREM := RESIZE((XL rem R), XREM'LENGTH); if L_LENGTH > R'LENGTH and XREM(0)/='X' and XREM(L_LENGTH-1 downto R'LENGTH) /= (L_LENGTH-1 downto R'LENGTH => XREM(R'LENGTH-1)) then assert NO_WARNING report "NUMERIC_STD.""rem"": Remainder Truncated" severity WARNING; end if; return RESIZE(XREM, R'LENGTH); end "rem"; --============================================================================ -- Id: A.33 function "mod" (L, R: UNSIGNED) return UNSIGNED is constant L_LEFT: INTEGER := L'LENGTH-1; constant R_LEFT: INTEGER := R'LENGTH-1; alias XXL: UNSIGNED(L_LEFT downto 0) is L; alias XXR: UNSIGNED(R_LEFT downto 0) is R; variable XL: UNSIGNED(L_LEFT downto 0); variable XR: UNSIGNED(R_LEFT downto 0); variable FQUOT: UNSIGNED(L'LENGTH-1 downto 0); variable FREMAIN: UNSIGNED(R'LENGTH-1 downto 0); begin if ((L'LENGTH < 1) or (R'LENGTH < 1)) then return NAU; end if; XL := TO_01(XXL, 'X'); XR := TO_01(XXR, 'X'); if ((XL(XL'LEFT)='X') or (XR(XR'LEFT)='X')) then FREMAIN := (others => 'X'); return FREMAIN; end if; DIVMOD(XL, XR, FQUOT, FREMAIN); return FREMAIN; end "mod"; -- Id: A.34 function "mod" (L, R: SIGNED) return SIGNED is constant L_LEFT: INTEGER := L'LENGTH-1; constant R_LEFT: INTEGER := R'LENGTH-1; alias XXL: SIGNED(L_LEFT downto 0) is L; alias XXR: SIGNED(R_LEFT downto 0) is R; variable XL: SIGNED(L_LEFT downto 0); variable XR: SIGNED(R_LEFT downto 0); variable FQUOT: UNSIGNED(L'LENGTH-1 downto 0); variable FREMAIN: UNSIGNED(R'LENGTH-1 downto 0); variable XNUM: UNSIGNED(L'LENGTH-1 downto 0); variable XDENOM: UNSIGNED(R'LENGTH-1 downto 0); variable RNEG: BOOLEAN := FALSE; begin if ((L'LENGTH < 1) or (R'LENGTH < 1)) then return NAS; end if; XL := TO_01(XXL, 'X'); XR := TO_01(XXR, 'X'); if ((XL(XL'LEFT)='X') or (XR(XR'LEFT)='X')) then FREMAIN := (others => 'X'); return SIGNED(FREMAIN); end if; if XL(XL'LEFT)='1' then XNUM := UNSIGNED(-XL); else XNUM := UNSIGNED(XL); end if; if XR(XR'LEFT)='1' then XDENOM := UNSIGNED(-XR); RNEG := TRUE; else XDENOM := UNSIGNED(XR); end if; DIVMOD(XNUM, XDENOM, FQUOT, FREMAIN); if RNEG and L(L'LEFT)='1' then FREMAIN := "0"-FREMAIN; elsif RNEG and FREMAIN/="0" then FREMAIN := FREMAIN-XDENOM; elsif L(L'LEFT)='1' and FREMAIN/="0" then FREMAIN := XDENOM-FREMAIN; end if; return SIGNED(FREMAIN); end "mod"; -- Id: A.35 function "mod" (L: UNSIGNED; R: NATURAL) return UNSIGNED is constant R_LENGTH: NATURAL := MAX(L'LENGTH, UNSIGNED_NUM_BITS(R)); variable XR, XREM: UNSIGNED(R_LENGTH-1 downto 0); begin if (L'LENGTH < 1) then return NAU; end if; XR := TO_UNSIGNED(R, R_LENGTH); XREM := RESIZE((L mod XR), XREM'LENGTH); if R_LENGTH > L'LENGTH and XREM(0)/='X' and XREM(R_LENGTH-1 downto L'LENGTH) /= (R_LENGTH-1 downto L'LENGTH => '0') then assert NO_WARNING report "NUMERIC_STD.""mod"": Modulus Truncated" severity WARNING; end if; return RESIZE(XREM, L'LENGTH); end "mod"; -- Id: A.36 function "mod" (L: NATURAL; R: UNSIGNED) return UNSIGNED is constant L_LENGTH: NATURAL := MAX(UNSIGNED_NUM_BITS(L), R'LENGTH); variable XL, XREM: UNSIGNED(L_LENGTH-1 downto 0); begin if (R'LENGTH < 1) then return NAU; end if; XL := TO_UNSIGNED(L, L_LENGTH); XREM := RESIZE((XL mod R), XREM'LENGTH); if L_LENGTH > R'LENGTH and XREM(0)/='X' and XREM(L_LENGTH-1 downto R'LENGTH) /= (L_LENGTH-1 downto R'LENGTH => '0') then assert NO_WARNING report "NUMERIC_STD.""mod"": Modulus Truncated" severity WARNING; end if; return RESIZE(XREM, R'LENGTH); end "mod"; -- Id: A.37 function "mod" (L: SIGNED; R: INTEGER) return SIGNED is constant R_LENGTH: NATURAL := MAX(L'LENGTH, SIGNED_NUM_BITS(R)); variable XR, XREM: SIGNED(R_LENGTH-1 downto 0); begin if (L'LENGTH < 1) then return NAS; end if; XR := TO_SIGNED(R, R_LENGTH); XREM := RESIZE((L mod XR), XREM'LENGTH); if R_LENGTH > L'LENGTH and XREM(0)/='X' and XREM(R_LENGTH-1 downto L'LENGTH) /= (R_LENGTH-1 downto L'LENGTH => XREM(L'LENGTH-1)) then assert NO_WARNING report "NUMERIC_STD.""mod"": Modulus Truncated" severity WARNING; end if; return RESIZE(XREM, L'LENGTH); end "mod"; -- Id: A.38 function "mod" (L: INTEGER; R: SIGNED) return SIGNED is constant L_LENGTH: NATURAL := MAX(SIGNED_NUM_BITS(L), R'LENGTH); variable XL, XREM: SIGNED(L_LENGTH-1 downto 0); begin if (R'LENGTH < 1) then return NAS; end if; XL := TO_SIGNED(L, L_LENGTH); XREM := RESIZE((XL mod R), XREM'LENGTH); if L_LENGTH > R'LENGTH and XREM(0)/='X' and XREM(L_LENGTH-1 downto R'LENGTH) /= (L_LENGTH-1 downto R'LENGTH => XREM(R'LENGTH-1)) then assert NO_WARNING report "NUMERIC_STD.""mod"": Modulus Truncated" severity WARNING; end if; return RESIZE(XREM, R'LENGTH); end "mod"; --============================================================================ -- Id: C.1 function ">" (L, R: UNSIGNED) return BOOLEAN is constant L_LEFT: INTEGER := L'LENGTH-1; constant R_LEFT: INTEGER := R'LENGTH-1; alias XL: UNSIGNED(L_LEFT downto 0) is L; alias XR: UNSIGNED(R_LEFT downto 0) is R; constant SIZE: NATURAL := MAX(L'LENGTH, R'LENGTH); variable L01 : UNSIGNED(L_LEFT downto 0); variable R01 : UNSIGNED(R_LEFT downto 0); begin if ((L'LENGTH < 1) or (R'LENGTH < 1)) then assert NO_WARNING report "NUMERIC_STD."">"": null argument detected, returning FALSE" severity WARNING; return FALSE; end if; L01 := TO_01(XL, 'X'); R01 := TO_01(XR, 'X'); if ((L01(L01'LEFT)='X') or (R01(R01'LEFT)='X')) then assert NO_WARNING report "NUMERIC_STD."">"": metavalue detected, returning FALSE" severity WARNING; return FALSE; end if; return not UNSIGNED_LESS_OR_EQUAL(RESIZE(L01, SIZE), RESIZE(R01, SIZE)); end ">"; -- Id: C.2 function ">" (L, R: SIGNED) return BOOLEAN is constant L_LEFT: INTEGER := L'LENGTH-1; constant R_LEFT: INTEGER := R'LENGTH-1; alias XL: SIGNED(L_LEFT downto 0) is L; alias XR: SIGNED(R_LEFT downto 0) is R; constant SIZE: NATURAL := MAX(L'LENGTH, R'LENGTH); variable L01 : SIGNED(L_LEFT downto 0); variable R01 : SIGNED(R_LEFT downto 0); begin if ((L'LENGTH < 1) or (R'LENGTH < 1)) then assert NO_WARNING report "NUMERIC_STD."">"": null argument detected, returning FALSE" severity WARNING; return FALSE; end if; L01 := TO_01(XL, 'X'); R01 := TO_01(XR, 'X'); if ((L01(L01'LEFT)='X') or (R01(R01'LEFT)='X')) then assert NO_WARNING report "NUMERIC_STD."">"": metavalue detected, returning FALSE" severity WARNING; return FALSE; end if; return not SIGNED_LESS_OR_EQUAL(RESIZE(L01, SIZE), RESIZE(R01, SIZE)); end ">"; -- Id: C.3 function ">" (L: NATURAL; R: UNSIGNED) return BOOLEAN is constant R_LEFT: INTEGER := R'LENGTH-1; alias XR: UNSIGNED(R_LEFT downto 0) is R; variable R01 : UNSIGNED(R_LEFT downto 0); begin if (R'LENGTH < 1) then assert NO_WARNING report "NUMERIC_STD."">"": null argument detected, returning FALSE" severity WARNING; return FALSE; end if; R01 := TO_01(XR, 'X'); if (R01(R01'LEFT)='X') then assert NO_WARNING report "NUMERIC_STD."">"": metavalue detected, returning FALSE" severity WARNING; return FALSE; end if; if UNSIGNED_NUM_BITS(L) > R'LENGTH then return TRUE; end if; return not UNSIGNED_LESS_OR_EQUAL(TO_UNSIGNED(L, R01'LENGTH), R01); end ">"; -- Id: C.4 function ">" (L: INTEGER; R: SIGNED) return BOOLEAN is constant R_LEFT: INTEGER := R'LENGTH-1; alias XR: SIGNED(R_LEFT downto 0) is R; variable R01 : SIGNED(R_LEFT downto 0); begin if (R'LENGTH < 1) then assert NO_WARNING report "NUMERIC_STD."">"": null argument detected, returning FALSE" severity WARNING; return FALSE; end if; R01 := TO_01(XR, 'X'); if (R01(R01'LEFT)='X') then assert NO_WARNING report "NUMERIC_STD."">"": metavalue detected, returning FALSE" severity WARNING; return FALSE; end if; if SIGNED_NUM_BITS(L) > R'LENGTH then return L > 0; end if; return not SIGNED_LESS_OR_EQUAL(TO_SIGNED(L, R01'LENGTH), R01); end ">"; -- Id: C.5 function ">" (L: UNSIGNED; R: NATURAL) return BOOLEAN is constant L_LEFT: INTEGER := L'LENGTH-1; alias XL: UNSIGNED(L_LEFT downto 0) is L; variable L01 : UNSIGNED(L_LEFT downto 0); begin if (L'LENGTH < 1) then assert NO_WARNING report "NUMERIC_STD."">"": null argument detected, returning FALSE" severity WARNING; return FALSE; end if; L01 := TO_01(XL, 'X'); if (L01(L01'LEFT)='X') then assert NO_WARNING report "NUMERIC_STD."">"": metavalue detected, returning FALSE" severity WARNING; return FALSE; end if; if UNSIGNED_NUM_BITS(R) > L'LENGTH then return FALSE; end if; return not UNSIGNED_LESS_OR_EQUAL(L01, TO_UNSIGNED(R, L01'LENGTH)); end ">"; -- Id: C.6 function ">" (L: SIGNED; R: INTEGER) return BOOLEAN is constant L_LEFT: INTEGER := L'LENGTH-1; alias XL: SIGNED(L_LEFT downto 0) is L; variable L01 : SIGNED(L_LEFT downto 0); begin if (L'LENGTH < 1) then assert NO_WARNING report "NUMERIC_STD."">"": null argument detected, returning FALSE" severity WARNING; return FALSE; end if; L01 := TO_01(XL, 'X'); if (L01(L01'LEFT)='X') then assert NO_WARNING report "NUMERIC_STD."">"": metavalue detected, returning FALSE" severity WARNING; return FALSE; end if; if SIGNED_NUM_BITS(R) > L'LENGTH then return 0 > R; end if; return not SIGNED_LESS_OR_EQUAL(L01, TO_SIGNED(R, L01'LENGTH)); end ">"; --============================================================================ -- Id: C.7 function "<" (L, R: UNSIGNED) return BOOLEAN is constant L_LEFT: INTEGER := L'LENGTH-1; constant R_LEFT: INTEGER := R'LENGTH-1; alias XL: UNSIGNED(L_LEFT downto 0) is L; alias XR: UNSIGNED(R_LEFT downto 0) is R; constant SIZE: NATURAL := MAX(L'LENGTH, R'LENGTH); variable L01 : UNSIGNED(L_LEFT downto 0); variable R01 : UNSIGNED(R_LEFT downto 0); begin if ((L'LENGTH < 1) or (R'LENGTH < 1)) then assert NO_WARNING report "NUMERIC_STD.""<"": null argument detected, returning FALSE" severity WARNING; return FALSE; end if; L01 := TO_01(XL, 'X'); R01 := TO_01(XR, 'X'); if ((L01(L01'LEFT)='X') or (R01(R01'LEFT)='X')) then assert NO_WARNING report "NUMERIC_STD.""<"": metavalue detected, returning FALSE" severity WARNING; return FALSE; end if; return UNSIGNED_LESS(RESIZE(L01, SIZE), RESIZE(R01, SIZE)); end "<"; -- Id: C.8 function "<" (L, R: SIGNED) return BOOLEAN is constant L_LEFT: INTEGER := L'LENGTH-1; constant R_LEFT: INTEGER := R'LENGTH-1; alias XL: SIGNED(L_LEFT downto 0) is L; alias XR: SIGNED(R_LEFT downto 0) is R; constant SIZE: NATURAL := MAX(L'LENGTH, R'LENGTH); variable L01 : SIGNED(L_LEFT downto 0); variable R01 : SIGNED(R_LEFT downto 0); begin if ((L'LENGTH < 1) or (R'LENGTH < 1)) then assert NO_WARNING report "NUMERIC_STD.""<"": null argument detected, returning FALSE" severity WARNING; return FALSE; end if; L01 := TO_01(XL, 'X'); R01 := TO_01(XR, 'X'); if ((L01(L01'LEFT)='X') or (R01(R01'LEFT)='X')) then assert NO_WARNING report "NUMERIC_STD.""<"": metavalue detected, returning FALSE" severity WARNING; return FALSE; end if; return SIGNED_LESS(RESIZE(L01, SIZE), RESIZE(R01, SIZE)); end "<"; -- Id: C.9 function "<" (L: NATURAL; R: UNSIGNED) return BOOLEAN is constant R_LEFT: INTEGER := R'LENGTH-1; alias XR: UNSIGNED(R_LEFT downto 0) is R; variable R01 : UNSIGNED(R_LEFT downto 0); begin if (R'LENGTH < 1) then assert NO_WARNING report "NUMERIC_STD.""<"": null argument detected, returning FALSE" severity WARNING; return FALSE; end if; R01 := TO_01(XR, 'X'); if (R01(R01'LEFT)='X') then assert NO_WARNING report "NUMERIC_STD.""<"": metavalue detected, returning FALSE" severity WARNING; return FALSE; end if; if UNSIGNED_NUM_BITS(L) > R'LENGTH then return L < 0; end if; return UNSIGNED_LESS(TO_UNSIGNED(L, R01'LENGTH), R01); end "<"; -- Id: C.10 function "<" (L: INTEGER; R: SIGNED) return BOOLEAN is constant R_LEFT: INTEGER := R'LENGTH-1; alias XR: SIGNED(R_LEFT downto 0) is R; variable R01 : SIGNED(R_LEFT downto 0); begin if (R'LENGTH < 1) then assert NO_WARNING report "NUMERIC_STD.""<"": null argument detected, returning FALSE" severity WARNING; return FALSE; end if; R01 := TO_01(XR, 'X'); if (R01(R01'LEFT)='X') then assert NO_WARNING report "NUMERIC_STD.""<"": metavalue detected, returning FALSE" severity WARNING; return FALSE; end if; if SIGNED_NUM_BITS(L) > R'LENGTH then return L < 0; end if; return SIGNED_LESS(TO_SIGNED(L, R01'LENGTH), R01); end "<"; -- Id: C.11 function "<" (L: UNSIGNED; R: NATURAL) return BOOLEAN is constant L_LEFT: INTEGER := L'LENGTH-1; alias XL: UNSIGNED(L_LEFT downto 0) is L; variable L01 : UNSIGNED(L_LEFT downto 0); begin if (L'LENGTH < 1) then assert NO_WARNING report "NUMERIC_STD.""<"": null argument detected, returning FALSE" severity WARNING; return FALSE; end if; L01 := TO_01(XL, 'X'); if (L01(L01'LEFT)='X') then assert NO_WARNING report "NUMERIC_STD.""<"": metavalue detected, returning FALSE" severity WARNING; return FALSE; end if; if UNSIGNED_NUM_BITS(R) > L'LENGTH then return 0 < R; end if; return UNSIGNED_LESS(L01, TO_UNSIGNED(R, L01'LENGTH)); end "<"; -- Id: C.12 function "<" (L: SIGNED; R: INTEGER) return BOOLEAN is constant L_LEFT: INTEGER := L'LENGTH-1; alias XL: SIGNED(L_LEFT downto 0) is L; variable L01 : SIGNED(L_LEFT downto 0); begin if (L'LENGTH < 1) then assert NO_WARNING report "NUMERIC_STD.""<"": null argument detected, returning FALSE" severity WARNING; return FALSE; end if; L01 := TO_01(XL, 'X'); if (L01(L01'LEFT)='X') then assert NO_WARNING report "NUMERIC_STD.""<"": metavalue detected, returning FALSE" severity WARNING; return FALSE; end if; if SIGNED_NUM_BITS(R) > L'LENGTH then return 0 < R; end if; return SIGNED_LESS(L01, TO_SIGNED(R, L01'LENGTH)); end "<"; --============================================================================ -- Id: C.13 function "<=" (L, R: UNSIGNED) return BOOLEAN is constant L_LEFT: INTEGER := L'LENGTH-1; constant R_LEFT: INTEGER := R'LENGTH-1; alias XL: UNSIGNED(L_LEFT downto 0) is L; alias XR: UNSIGNED(R_LEFT downto 0) is R; constant SIZE: NATURAL := MAX(L'LENGTH, R'LENGTH); variable L01 : UNSIGNED(L_LEFT downto 0); variable R01 : UNSIGNED(R_LEFT downto 0); begin if ((L'LENGTH < 1) or (R'LENGTH < 1)) then assert NO_WARNING report "NUMERIC_STD.""<="": null argument detected, returning FALSE" severity WARNING; return FALSE; end if; L01 := TO_01(XL, 'X'); R01 := TO_01(XR, 'X'); if ((L01(L01'LEFT)='X') or (R01(R01'LEFT)='X')) then assert NO_WARNING report "NUMERIC_STD.""<="": metavalue detected, returning FALSE" severity WARNING; return FALSE; end if; return UNSIGNED_LESS_OR_EQUAL(RESIZE(L01, SIZE), RESIZE(R01, SIZE)); end "<="; -- Id: C.14 function "<=" (L, R: SIGNED) return BOOLEAN is constant L_LEFT: INTEGER := L'LENGTH-1; constant R_LEFT: INTEGER := R'LENGTH-1; alias XL: SIGNED(L_LEFT downto 0) is L; alias XR: SIGNED(R_LEFT downto 0) is R; constant SIZE: NATURAL := MAX(L'LENGTH, R'LENGTH); variable L01 : SIGNED(L_LEFT downto 0); variable R01 : SIGNED(R_LEFT downto 0); begin if ((L'LENGTH < 1) or (R'LENGTH < 1)) then assert NO_WARNING report "NUMERIC_STD.""<="": null argument detected, returning FALSE" severity WARNING; return FALSE; end if; L01 := TO_01(XL, 'X'); R01 := TO_01(XR, 'X'); if ((L01(L01'LEFT)='X') or (R01(R01'LEFT)='X')) then assert NO_WARNING report "NUMERIC_STD.""<="": metavalue detected, returning FALSE" severity WARNING; return FALSE; end if; return SIGNED_LESS_OR_EQUAL(RESIZE(L01, SIZE), RESIZE(R01, SIZE)); end "<="; -- Id: C.15 function "<=" (L: NATURAL; R: UNSIGNED) return BOOLEAN is constant R_LEFT: INTEGER := R'LENGTH-1; alias XR: UNSIGNED(R_LEFT downto 0) is R; variable R01 : UNSIGNED(R_LEFT downto 0); begin if (R'LENGTH < 1) then assert NO_WARNING report "NUMERIC_STD.""<="": null argument detected, returning FALSE" severity WARNING; return FALSE; end if; R01 := TO_01(XR, 'X'); if (R01(R01'LEFT)='X') then assert NO_WARNING report "NUMERIC_STD.""<="": metavalue detected, returning FALSE" severity WARNING; return FALSE; end if; if UNSIGNED_NUM_BITS(L) > R'LENGTH then return L < 0; end if; return UNSIGNED_LESS_OR_EQUAL(TO_UNSIGNED(L, R01'LENGTH), R01); end "<="; -- Id: C.16 function "<=" (L: INTEGER; R: SIGNED) return BOOLEAN is constant R_LEFT: INTEGER := R'LENGTH-1; alias XR: SIGNED(R_LEFT downto 0) is R; variable R01 : SIGNED(R_LEFT downto 0); begin if (R'LENGTH < 1) then assert NO_WARNING report "NUMERIC_STD.""<="": null argument detected, returning FALSE" severity WARNING; return FALSE; end if; R01 := TO_01(XR, 'X'); if (R01(R01'LEFT)='X') then assert NO_WARNING report "NUMERIC_STD.""<="": metavalue detected, returning FALSE" severity WARNING; return FALSE; end if; if SIGNED_NUM_BITS(L) > R'LENGTH then return L < 0; end if; return SIGNED_LESS_OR_EQUAL(TO_SIGNED(L, R01'LENGTH), R01); end "<="; -- Id: C.17 function "<=" (L: UNSIGNED; R: NATURAL) return BOOLEAN is constant L_LEFT: INTEGER := L'LENGTH-1; alias XL: UNSIGNED(L_LEFT downto 0) is L; variable L01 : UNSIGNED(L_LEFT downto 0); begin if (L_LEFT < 0) then assert NO_WARNING report "NUMERIC_STD.""<="": null argument detected, returning FALSE" severity WARNING; return FALSE; end if; L01 := TO_01(XL, 'X'); if (L01(L01'LEFT)='X') then assert NO_WARNING report "NUMERIC_STD.""<="": metavalue detected, returning FALSE" severity WARNING; return FALSE; end if; if UNSIGNED_NUM_BITS(R) > L'LENGTH then return 0 < R; end if; return UNSIGNED_LESS_OR_EQUAL(L01, TO_UNSIGNED(R, L01'LENGTH)); end "<="; -- Id: C.18 function "<=" (L: SIGNED; R: INTEGER) return BOOLEAN is constant L_LEFT: INTEGER := L'LENGTH-1; alias XL: SIGNED(L_LEFT downto 0) is L; variable L01 : SIGNED(L_LEFT downto 0); begin if (L_LEFT < 0) then assert NO_WARNING report "NUMERIC_STD.""<="": null argument detected, returning FALSE" severity WARNING; return FALSE; end if; L01 := TO_01(XL, 'X'); if (L01(L01'LEFT)='X') then assert NO_WARNING report "NUMERIC_STD.""<="": metavalue detected, returning FALSE" severity WARNING; return FALSE; end if; if SIGNED_NUM_BITS(R) > L'LENGTH then return 0 < R; end if; return SIGNED_LESS_OR_EQUAL(L01, TO_SIGNED(R, L01'LENGTH)); end "<="; --============================================================================ -- Id: C.19 function ">=" (L, R: UNSIGNED) return BOOLEAN is constant L_LEFT: INTEGER := L'LENGTH-1; constant R_LEFT: INTEGER := R'LENGTH-1; alias XL: UNSIGNED(L_LEFT downto 0) is L; alias XR: UNSIGNED(R_LEFT downto 0) is R; constant SIZE: NATURAL := MAX(L'LENGTH, R'LENGTH); variable L01 : UNSIGNED(L_LEFT downto 0); variable R01 : UNSIGNED(R_LEFT downto 0); begin if ((L'LENGTH < 1) or (R'LENGTH < 1)) then assert NO_WARNING report "NUMERIC_STD."">="": null argument detected, returning FALSE" severity WARNING; return FALSE; end if; L01 := TO_01(XL, 'X'); R01 := TO_01(XR, 'X'); if ((L01(L01'LEFT)='X') or (R01(R01'LEFT)='X')) then assert NO_WARNING report "NUMERIC_STD."">="": metavalue detected, returning FALSE" severity WARNING; return FALSE; end if; return not UNSIGNED_LESS(RESIZE(L01, SIZE), RESIZE(R01, SIZE)); end ">="; -- Id: C.20 function ">=" (L, R: SIGNED) return BOOLEAN is constant L_LEFT: INTEGER := L'LENGTH-1; constant R_LEFT: INTEGER := R'LENGTH-1; alias XL: SIGNED(L_LEFT downto 0) is L; alias XR: SIGNED(R_LEFT downto 0) is R; constant SIZE: NATURAL := MAX(L'LENGTH, R'LENGTH); variable L01 : SIGNED(L_LEFT downto 0); variable R01 : SIGNED(R_LEFT downto 0); begin if ((L'LENGTH < 1) or (R'LENGTH < 1)) then assert NO_WARNING report "NUMERIC_STD."">="": null argument detected, returning FALSE" severity WARNING; return FALSE; end if; L01 := TO_01(XL, 'X'); R01 := TO_01(XR, 'X'); if ((L01(L01'LEFT)='X') or (R01(R01'LEFT)='X')) then assert NO_WARNING report "NUMERIC_STD."">="": metavalue detected, returning FALSE" severity WARNING; return FALSE; end if; return not SIGNED_LESS(RESIZE(L01, SIZE), RESIZE(R01, SIZE)); end ">="; -- Id: C.21 function ">=" (L: NATURAL; R: UNSIGNED) return BOOLEAN is constant R_LEFT: INTEGER := R'LENGTH-1; alias XR: UNSIGNED(R_LEFT downto 0) is R; variable R01 : UNSIGNED(R_LEFT downto 0); begin if (R'LENGTH < 1) then assert NO_WARNING report "NUMERIC_STD."">="": null argument detected, returning FALSE" severity WARNING; return FALSE; end if; R01 := TO_01(XR, 'X'); if (R01(R01'LEFT)='X') then assert NO_WARNING report "NUMERIC_STD."">="": metavalue detected, returning FALSE" severity WARNING; return FALSE; end if; if UNSIGNED_NUM_BITS(L) > R'LENGTH then return L > 0; end if; return not UNSIGNED_LESS(TO_UNSIGNED(L, R01'LENGTH), R01); end ">="; -- Id: C.22 function ">=" (L: INTEGER; R: SIGNED) return BOOLEAN is constant R_LEFT: INTEGER := R'LENGTH-1; alias XR: SIGNED(R_LEFT downto 0) is R; variable R01 : SIGNED(R_LEFT downto 0); begin if (R'LENGTH < 1) then assert NO_WARNING report "NUMERIC_STD."">="": null argument detected, returning FALSE" severity WARNING; return FALSE; end if; R01 := TO_01(XR, 'X'); if (R01(R01'LEFT)='X') then assert NO_WARNING report "NUMERIC_STD."">="": metavalue detected, returning FALSE" severity WARNING; return FALSE; end if; if SIGNED_NUM_BITS(L) > R'LENGTH then return L > 0; end if; return not SIGNED_LESS(TO_SIGNED(L, R01'LENGTH), R01); end ">="; -- Id: C.23 function ">=" (L: UNSIGNED; R: NATURAL) return BOOLEAN is constant L_LEFT: INTEGER := L'LENGTH-1; alias XL: UNSIGNED(L_LEFT downto 0) is L; variable L01 : UNSIGNED(L_LEFT downto 0); begin if (L'LENGTH < 1) then assert NO_WARNING report "NUMERIC_STD."">="": null argument detected, returning FALSE" severity WARNING; return FALSE; end if; L01 := TO_01(XL, 'X'); if (L01(L01'LEFT)='X') then assert NO_WARNING report "NUMERIC_STD."">="": metavalue detected, returning FALSE" severity WARNING; return FALSE; end if; if UNSIGNED_NUM_BITS(R) > L'LENGTH then return 0 > R; end if; return not UNSIGNED_LESS(L01, TO_UNSIGNED(R, L01'LENGTH)); end ">="; -- Id: C.24 function ">=" (L: SIGNED; R: INTEGER) return BOOLEAN is constant L_LEFT: INTEGER := L'LENGTH-1; alias XL: SIGNED(L_LEFT downto 0) is L; variable L01 : SIGNED(L_LEFT downto 0); begin if (L'LENGTH < 1) then assert NO_WARNING report "NUMERIC_STD."">="": null argument detected, returning FALSE" severity WARNING; return FALSE; end if; L01 := TO_01(XL, 'X'); if (L01(L01'LEFT)='X') then assert NO_WARNING report "NUMERIC_STD."">="": metavalue detected, returning FALSE" severity WARNING; return FALSE; end if; if SIGNED_NUM_BITS(R) > L'LENGTH then return 0 > R; end if; return not SIGNED_LESS(L01, TO_SIGNED(R, L01'LENGTH)); end ">="; --============================================================================ -- Id: C.25 function "=" (L, R: UNSIGNED) return BOOLEAN is constant L_LEFT: INTEGER := L'LENGTH-1; constant R_LEFT: INTEGER := R'LENGTH-1; alias XL: UNSIGNED(L_LEFT downto 0) is L; alias XR: UNSIGNED(R_LEFT downto 0) is R; constant SIZE: NATURAL := MAX(L'LENGTH, R'LENGTH); variable L01 : UNSIGNED(L_LEFT downto 0); variable R01 : UNSIGNED(R_LEFT downto 0); begin if ((L'LENGTH < 1) or (R'LENGTH < 1)) then assert NO_WARNING report "NUMERIC_STD.""="": null argument detected, returning FALSE" severity WARNING; return FALSE; end if; L01 := TO_01(XL, 'X'); R01 := TO_01(XR, 'X'); if ((L01(L01'LEFT)='X') or (R01(R01'LEFT)='X')) then assert NO_WARNING report "NUMERIC_STD.""="": metavalue detected, returning FALSE" severity WARNING; return FALSE; end if; return UNSIGNED_EQUAL(RESIZE(L01, SIZE), RESIZE(R01, SIZE)); end "="; -- Id: C.26 function "=" (L, R: SIGNED) return BOOLEAN is constant L_LEFT: INTEGER := L'LENGTH-1; constant R_LEFT: INTEGER := R'LENGTH-1; alias XL: SIGNED(L_LEFT downto 0) is L; alias XR: SIGNED(R_LEFT downto 0) is R; constant SIZE: NATURAL := MAX(L'LENGTH, R'LENGTH); variable L01 : SIGNED(L_LEFT downto 0); variable R01 : SIGNED(R_LEFT downto 0); begin if ((L'LENGTH < 1) or (R'LENGTH < 1)) then assert NO_WARNING report "NUMERIC_STD.""="": null argument detected, returning FALSE" severity WARNING; return FALSE; end if; L01 := TO_01(XL, 'X'); R01 := TO_01(XR, 'X'); if ((L01(L01'LEFT)='X') or (R01(R01'LEFT)='X')) then assert NO_WARNING report "NUMERIC_STD.""="": metavalue detected, returning FALSE" severity WARNING; return FALSE; end if; return SIGNED_EQUAL(RESIZE(L01, SIZE), RESIZE(R01, SIZE)); end "="; -- Id: C.27 function "=" (L: NATURAL; R: UNSIGNED) return BOOLEAN is constant R_LEFT: INTEGER := R'LENGTH-1; alias XR: UNSIGNED(R_LEFT downto 0) is R; variable R01 : UNSIGNED(R_LEFT downto 0); begin if (R'LENGTH < 1) then assert NO_WARNING report "NUMERIC_STD.""="": null argument detected, returning FALSE" severity WARNING; return FALSE; end if; R01 := TO_01(XR, 'X'); if (R01(R01'LEFT)='X') then assert NO_WARNING report "NUMERIC_STD.""="": metavalue detected, returning FALSE" severity WARNING; return FALSE; end if; if UNSIGNED_NUM_BITS(L) > R'LENGTH then return FALSE; end if; return UNSIGNED_EQUAL(TO_UNSIGNED(L, R01'LENGTH), R01); end "="; -- Id: C.28 function "=" (L: INTEGER; R: SIGNED) return BOOLEAN is constant R_LEFT: INTEGER := R'LENGTH-1; alias XR: SIGNED(R_LEFT downto 0) is R; variable R01 : SIGNED(R_LEFT downto 0); begin if (R'LENGTH < 1) then assert NO_WARNING report "NUMERIC_STD.""="": null argument detected, returning FALSE" severity WARNING; return FALSE; end if; R01 := TO_01(XR, 'X'); if (R01(R01'LEFT)='X') then assert NO_WARNING report "NUMERIC_STD.""="": metavalue detected, returning FALSE" severity WARNING; return FALSE; end if; if SIGNED_NUM_BITS(L) > R'LENGTH then return FALSE; end if; return SIGNED_EQUAL(TO_SIGNED(L, R01'LENGTH), R01); end "="; -- Id: C.29 function "=" (L: UNSIGNED; R: NATURAL) return BOOLEAN is constant L_LEFT: INTEGER := L'LENGTH-1; alias XL: UNSIGNED(L_LEFT downto 0) is L; variable L01 : UNSIGNED(L_LEFT downto 0); begin if (L'LENGTH < 1) then assert NO_WARNING report "NUMERIC_STD.""="": null argument detected, returning FALSE" severity WARNING; return FALSE; end if; L01 := TO_01(XL, 'X'); if (L01(L01'LEFT)='X') then assert NO_WARNING report "NUMERIC_STD.""="": metavalue detected, returning FALSE" severity WARNING; return FALSE; end if; if UNSIGNED_NUM_BITS(R) > L'LENGTH then return FALSE; end if; return UNSIGNED_EQUAL(L01, TO_UNSIGNED(R, L01'LENGTH)); end "="; -- Id: C.30 function "=" (L: SIGNED; R: INTEGER) return BOOLEAN is constant L_LEFT: INTEGER := L'LENGTH-1; alias XL: SIGNED(L_LEFT downto 0) is L; variable L01 : SIGNED(L_LEFT downto 0); begin if (L'LENGTH < 1) then assert NO_WARNING report "NUMERIC_STD.""="": null argument detected, returning FALSE" severity WARNING; return FALSE; end if; L01 := TO_01(XL, 'X'); if (L01(L01'LEFT)='X') then assert NO_WARNING report "NUMERIC_STD.""="": metavalue detected, returning FALSE" severity WARNING; return FALSE; end if; if SIGNED_NUM_BITS(R) > L'LENGTH then return FALSE; end if; return SIGNED_EQUAL(L01, TO_SIGNED(R, L01'LENGTH)); end "="; --============================================================================ -- Id: C.31 function "/=" (L, R: UNSIGNED) return BOOLEAN is constant L_LEFT: INTEGER := L'LENGTH-1; constant R_LEFT: INTEGER := R'LENGTH-1; alias XL: UNSIGNED(L_LEFT downto 0) is L; alias XR: UNSIGNED(R_LEFT downto 0) is R; constant SIZE: NATURAL := MAX(L'LENGTH, R'LENGTH); variable L01 : UNSIGNED(L_LEFT downto 0); variable R01 : UNSIGNED(R_LEFT downto 0); begin if ((L'LENGTH < 1) or (R'LENGTH < 1)) then assert NO_WARNING report "NUMERIC_STD.""/="": null argument detected, returning TRUE" severity WARNING; return TRUE; end if; L01 := TO_01(XL, 'X'); R01 := TO_01(XR, 'X'); if ((L01(L01'LEFT)='X') or (R01(R01'LEFT)='X')) then assert NO_WARNING report "NUMERIC_STD.""/="": metavalue detected, returning TRUE" severity WARNING; return TRUE; end if; return not(UNSIGNED_EQUAL(RESIZE(L01, SIZE), RESIZE(R01, SIZE))); end "/="; -- Id: C.32 function "/=" (L, R: SIGNED) return BOOLEAN is constant L_LEFT: INTEGER := L'LENGTH-1; constant R_LEFT: INTEGER := R'LENGTH-1; alias XL: SIGNED(L_LEFT downto 0) is L; alias XR: SIGNED(R_LEFT downto 0) is R; constant SIZE: NATURAL := MAX(L'LENGTH, R'LENGTH); variable L01 : SIGNED(L_LEFT downto 0); variable R01 : SIGNED(R_LEFT downto 0); begin if ((L'LENGTH < 1) or (R'LENGTH < 1)) then assert NO_WARNING report "NUMERIC_STD.""/="": null argument detected, returning TRUE" severity WARNING; return TRUE; end if; L01 := TO_01(XL, 'X'); R01 := TO_01(XR, 'X'); if ((L01(L01'LEFT)='X') or (R01(R01'LEFT)='X')) then assert NO_WARNING report "NUMERIC_STD.""/="": metavalue detected, returning TRUE" severity WARNING; return TRUE; end if; return not(SIGNED_EQUAL(RESIZE(L01, SIZE), RESIZE(R01, SIZE))); end "/="; -- Id: C.33 function "/=" (L: NATURAL; R: UNSIGNED) return BOOLEAN is constant R_LEFT: INTEGER := R'LENGTH-1; alias XR: UNSIGNED(R_LEFT downto 0) is R; variable R01 : UNSIGNED(R_LEFT downto 0); begin if (R'LENGTH < 1) then assert NO_WARNING report "NUMERIC_STD.""/="": null argument detected, returning TRUE" severity WARNING; return TRUE; end if; R01 := TO_01(XR, 'X'); if (R01(R01'LEFT)='X') then assert NO_WARNING report "NUMERIC_STD.""/="": metavalue detected, returning TRUE" severity WARNING; return TRUE; end if; if UNSIGNED_NUM_BITS(L) > R'LENGTH then return TRUE; end if; return not(UNSIGNED_EQUAL(TO_UNSIGNED(L, R01'LENGTH), R01)); end "/="; -- Id: C.34 function "/=" (L: INTEGER; R: SIGNED) return BOOLEAN is constant R_LEFT: INTEGER := R'LENGTH-1; alias XR: SIGNED(R_LEFT downto 0) is R; variable R01 : SIGNED(R_LEFT downto 0); begin if (R'LENGTH < 1) then assert NO_WARNING report "NUMERIC_STD.""/="": null argument detected, returning TRUE" severity WARNING; return TRUE; end if; R01 := TO_01(XR, 'X'); if (R01(R01'LEFT)='X') then assert NO_WARNING report "NUMERIC_STD.""/="": metavalue detected, returning TRUE" severity WARNING; return TRUE; end if; if SIGNED_NUM_BITS(L) > R'LENGTH then return TRUE; end if; return not(SIGNED_EQUAL(TO_SIGNED(L, R01'LENGTH), R01)); end "/="; -- Id: C.35 function "/=" (L: UNSIGNED; R: NATURAL) return BOOLEAN is constant L_LEFT: INTEGER := L'LENGTH-1; alias XL: UNSIGNED(L_LEFT downto 0) is L; variable L01 : UNSIGNED(L_LEFT downto 0); begin if (L'LENGTH < 1) then assert NO_WARNING report "NUMERIC_STD.""/="": null argument detected, returning TRUE" severity WARNING; return TRUE; end if; L01 := TO_01(XL, 'X'); if (L01(L01'LEFT)='X') then assert NO_WARNING report "NUMERIC_STD.""/="": metavalue detected, returning TRUE" severity WARNING; return TRUE; end if; if UNSIGNED_NUM_BITS(R) > L'LENGTH then return TRUE; end if; return not(UNSIGNED_EQUAL(L01, TO_UNSIGNED(R, L01'LENGTH))); end "/="; -- Id: C.36 function "/=" (L: SIGNED; R: INTEGER) return BOOLEAN is constant L_LEFT: INTEGER := L'LENGTH-1; alias XL: SIGNED(L_LEFT downto 0) is L; variable L01 : SIGNED(L_LEFT downto 0); begin if (L'LENGTH < 1) then assert NO_WARNING report "NUMERIC_STD.""/="": null argument detected, returning TRUE" severity WARNING; return TRUE; end if; L01 := TO_01(XL, 'X'); if (L01(L01'LEFT)='X') then assert NO_WARNING report "NUMERIC_STD.""/="": metavalue detected, returning TRUE" severity WARNING; return TRUE; end if; if SIGNED_NUM_BITS(R) > L'LENGTH then return TRUE; end if; return not(SIGNED_EQUAL(L01, TO_SIGNED(R, L01'LENGTH))); end "/="; --============================================================================ -- Id: S.1 function SHIFT_LEFT (ARG: UNSIGNED; COUNT: NATURAL) return UNSIGNED is begin if (ARG'LENGTH < 1) then return NAU; end if; return UNSIGNED(XSLL(STD_LOGIC_VECTOR(ARG), COUNT)); end SHIFT_LEFT; -- Id: S.2 function SHIFT_RIGHT (ARG: UNSIGNED; COUNT: NATURAL) return UNSIGNED is begin if (ARG'LENGTH < 1) then return NAU; end if; return UNSIGNED(XSRL(STD_LOGIC_VECTOR(ARG), COUNT)); end SHIFT_RIGHT; -- Id: S.3 function SHIFT_LEFT (ARG: SIGNED; COUNT: NATURAL) return SIGNED is begin if (ARG'LENGTH < 1) then return NAS; end if; return SIGNED(XSLL(STD_LOGIC_VECTOR(ARG), COUNT)); end SHIFT_LEFT; -- Id: S.4 function SHIFT_RIGHT (ARG: SIGNED; COUNT: NATURAL) return SIGNED is begin if (ARG'LENGTH < 1) then return NAS; end if; return SIGNED(XSRA(STD_LOGIC_VECTOR(ARG), COUNT)); end SHIFT_RIGHT; --============================================================================ -- Id: S.5 function ROTATE_LEFT (ARG: UNSIGNED; COUNT: NATURAL) return UNSIGNED is begin if (ARG'LENGTH < 1) then return NAU; end if; return UNSIGNED(XROL(STD_LOGIC_VECTOR(ARG), COUNT)); end ROTATE_LEFT; -- Id: S.6 function ROTATE_RIGHT (ARG: UNSIGNED; COUNT: NATURAL) return UNSIGNED is begin if (ARG'LENGTH < 1) then return NAU; end if; return UNSIGNED(XROR(STD_LOGIC_VECTOR(ARG), COUNT)); end ROTATE_RIGHT; -- Id: S.7 function ROTATE_LEFT (ARG: SIGNED; COUNT: NATURAL) return SIGNED is begin if (ARG'LENGTH < 1) then return NAS; end if; return SIGNED(XROL(STD_LOGIC_VECTOR(ARG), COUNT)); end ROTATE_LEFT; -- Id: S.8 function ROTATE_RIGHT (ARG: SIGNED; COUNT: NATURAL) return SIGNED is begin if (ARG'LENGTH < 1) then return NAS; end if; return SIGNED(XROR(STD_LOGIC_VECTOR(ARG), COUNT)); end ROTATE_RIGHT; --============================================================================ --START-V93 ------------------------------------------------------------------------------ -- Note : Function S.9 is not compatible with VHDL 1076-1987. Comment -- out the function (declaration and body) for VHDL 1076-1987 compatibility. ------------------------------------------------------------------------------ -- Id: S.9 function "sll" (ARG: UNSIGNED; COUNT: INTEGER) return UNSIGNED is begin if (COUNT >= 0) then return SHIFT_LEFT(ARG, COUNT); else return SHIFT_RIGHT(ARG, -COUNT); end if; end "sll"; ------------------------------------------------------------------------------ -- Note : Function S.10 is not compatible with VHDL 1076-1987. Comment -- out the function (declaration and body) for VHDL 1076-1987 compatibility. ------------------------------------------------------------------------------ -- Id: S.10 function "sll" (ARG: SIGNED; COUNT: INTEGER) return SIGNED is begin if (COUNT >= 0) then return SHIFT_LEFT(ARG, COUNT); else return SIGNED(SHIFT_RIGHT(UNSIGNED(ARG), -COUNT)); end if; end "sll"; ------------------------------------------------------------------------------ -- Note : Function S.11 is not compatible with VHDL 1076-1987. Comment -- out the function (declaration and body) for VHDL 1076-1987 compatibility. ------------------------------------------------------------------------------ -- Id: S.11 function "srl" (ARG: UNSIGNED; COUNT: INTEGER) return UNSIGNED is begin if (COUNT >= 0) then return SHIFT_RIGHT(ARG, COUNT); else return SHIFT_LEFT(ARG, -COUNT); end if; end "srl"; ------------------------------------------------------------------------------ -- Note : Function S.12 is not compatible with VHDL 1076-1987. Comment -- out the function (declaration and body) for VHDL 1076-1987 compatibility. ------------------------------------------------------------------------------ -- Id: S.12 function "srl" (ARG: SIGNED; COUNT: INTEGER) return SIGNED is begin if (COUNT >= 0) then return SIGNED(SHIFT_RIGHT(UNSIGNED(ARG), COUNT)); else return SHIFT_LEFT(ARG, -COUNT); end if; end "srl"; ------------------------------------------------------------------------------ -- Note : Function S.13 is not compatible with VHDL 1076-1987. Comment -- out the function (declaration and body) for VHDL 1076-1987 compatibility. ------------------------------------------------------------------------------ -- Id: S.13 function "rol" (ARG: UNSIGNED; COUNT: INTEGER) return UNSIGNED is begin if (COUNT >= 0) then return ROTATE_LEFT(ARG, COUNT); else return ROTATE_RIGHT(ARG, -COUNT); end if; end "rol"; ------------------------------------------------------------------------------ -- Note : Function S.14 is not compatible with VHDL 1076-1987. Comment -- out the function (declaration and body) for VHDL 1076-1987 compatibility. ------------------------------------------------------------------------------ -- Id: S.14 function "rol" (ARG: SIGNED; COUNT: INTEGER) return SIGNED is begin if (COUNT >= 0) then return ROTATE_LEFT(ARG, COUNT); else return ROTATE_RIGHT(ARG, -COUNT); end if; end "rol"; ------------------------------------------------------------------------------ -- Note : Function S.15 is not compatible with VHDL 1076-1987. Comment -- out the function (declaration and body) for VHDL 1076-1987 compatibility. ------------------------------------------------------------------------------ -- Id: S.15 function "ror" (ARG: UNSIGNED; COUNT: INTEGER) return UNSIGNED is begin if (COUNT >= 0) then return ROTATE_RIGHT(ARG, COUNT); else return ROTATE_LEFT(ARG, -COUNT); end if; end "ror"; ------------------------------------------------------------------------------ -- Note : Function S.16 is not compatible with VHDL 1076-1987. Comment -- out the function (declaration and body) for VHDL 1076-1987 compatibility. ------------------------------------------------------------------------------ -- Id: S.16 function "ror" (ARG: SIGNED; COUNT: INTEGER) return SIGNED is begin if (COUNT >= 0) then return ROTATE_RIGHT(ARG, COUNT); else return ROTATE_LEFT(ARG, -COUNT); end if; end "ror"; --END-V93 --============================================================================ -- Id: D.1 function TO_INTEGER (ARG: UNSIGNED) return NATURAL is constant ARG_LEFT: INTEGER := ARG'LENGTH-1; alias XXARG: UNSIGNED(ARG_LEFT downto 0) is ARG; variable XARG: UNSIGNED(ARG_LEFT downto 0); variable RESULT: NATURAL := 0; begin if (ARG'LENGTH < 1) then assert NO_WARNING report "NUMERIC_STD.TO_INTEGER: null detected, returning 0" severity WARNING; return 0; end if; XARG := TO_01(XXARG, 'X'); if (XARG(XARG'LEFT)='X') then assert NO_WARNING report "NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0" severity WARNING; return 0; end if; for I in XARG'RANGE loop RESULT := RESULT+RESULT; if XARG(I) = '1' then RESULT := RESULT + 1; end if; end loop; return RESULT; end TO_INTEGER; -- Id: D.2 function TO_INTEGER (ARG: SIGNED) return INTEGER is variable XARG: SIGNED(ARG'LENGTH-1 downto 0); begin if (ARG'LENGTH < 1) then assert NO_WARNING report "NUMERIC_STD.TO_INTEGER: null detected, returning 0" severity WARNING; return 0; end if; XARG := TO_01(ARG, 'X'); if (XARG(XARG'LEFT)='X') then assert NO_WARNING report "NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0" severity WARNING; return 0; end if; if XARG(XARG'LEFT) = '0' then return TO_INTEGER(UNSIGNED(XARG)); else return (- (TO_INTEGER(UNSIGNED(- (XARG + 1)))) -1); end if; end TO_INTEGER; -- Id: D.3 function TO_UNSIGNED (ARG, SIZE: NATURAL) return UNSIGNED is variable RESULT: UNSIGNED(SIZE-1 downto 0); variable I_VAL: NATURAL := ARG; begin if (SIZE < 1) then return NAU; end if; for I in 0 to RESULT'LEFT loop if (I_VAL mod 2) = 0 then RESULT(I) := '0'; else RESULT(I) := '1'; end if; I_VAL := I_VAL/2; end loop; if not(I_VAL =0) then assert NO_WARNING report "NUMERIC_STD.TO_UNSIGNED: vector truncated" severity WARNING; end if; return RESULT; end TO_UNSIGNED; -- Id: D.4 function TO_SIGNED (ARG: INTEGER; SIZE: NATURAL) return SIGNED is variable RESULT: SIGNED(SIZE-1 downto 0); variable B_VAL: STD_LOGIC := '0'; variable I_VAL: INTEGER := ARG; begin if (SIZE < 1) then return NAS; end if; if (ARG < 0) then B_VAL := '1'; I_VAL := -(ARG+1); end if; for I in 0 to RESULT'LEFT loop if (I_VAL mod 2) = 0 then RESULT(I) := B_VAL; else RESULT(I) := not B_VAL; end if; I_VAL := I_VAL/2; end loop; if ((I_VAL/=0) or (B_VAL/=RESULT(RESULT'LEFT))) then assert NO_WARNING report "NUMERIC_STD.TO_SIGNED: vector truncated" severity WARNING; end if; return RESULT; end TO_SIGNED; --============================================================================ -- Id: R.1 function RESIZE (ARG: SIGNED; NEW_SIZE: NATURAL) return SIGNED is alias INVEC: SIGNED(ARG'LENGTH-1 downto 0) is ARG; variable RESULT: SIGNED(NEW_SIZE-1 downto 0) := (others => '0'); constant BOUND: INTEGER := MIN(ARG'LENGTH, RESULT'LENGTH)-2; begin if (NEW_SIZE < 1) then return NAS; end if; if (ARG'LENGTH = 0) then return RESULT; end if; RESULT := (others => ARG(ARG'LEFT)); if BOUND >= 0 then RESULT(BOUND downto 0) := INVEC(BOUND downto 0); end if; return RESULT; end RESIZE; -- Id: R.2 function RESIZE (ARG: UNSIGNED; NEW_SIZE: NATURAL) return UNSIGNED is constant ARG_LEFT: INTEGER := ARG'LENGTH-1; alias XARG: UNSIGNED(ARG_LEFT downto 0) is ARG; variable RESULT: UNSIGNED(NEW_SIZE-1 downto 0) := (others => '0'); begin if (NEW_SIZE < 1) then return NAU; end if; if XARG'LENGTH =0 then return RESULT; end if; if (RESULT'LENGTH < ARG'LENGTH) then RESULT(RESULT'LEFT downto 0) := XARG(RESULT'LEFT downto 0); else RESULT(RESULT'LEFT downto XARG'LEFT+1) := (others => '0'); RESULT(XARG'LEFT downto 0) := XARG; end if; return RESULT; end RESIZE; --============================================================================ -- Id: L.1 function "not" (L: UNSIGNED) return UNSIGNED is variable RESULT: UNSIGNED(L'LENGTH-1 downto 0); begin RESULT := UNSIGNED(not(STD_LOGIC_VECTOR(L))); return RESULT; end "not"; -- Id: L.2 function "and" (L, R: UNSIGNED) return UNSIGNED is variable RESULT: UNSIGNED(L'LENGTH-1 downto 0); begin RESULT := UNSIGNED(STD_LOGIC_VECTOR(L) and STD_LOGIC_VECTOR(R)); return RESULT; end "and"; -- Id: L.3 function "or" (L, R: UNSIGNED) return UNSIGNED is variable RESULT: UNSIGNED(L'LENGTH-1 downto 0); begin RESULT := UNSIGNED(STD_LOGIC_VECTOR(L) or STD_LOGIC_VECTOR(R)); return RESULT; end "or"; -- Id: L.4 function "nand" (L, R: UNSIGNED) return UNSIGNED is variable RESULT: UNSIGNED(L'LENGTH-1 downto 0); begin RESULT := UNSIGNED(STD_LOGIC_VECTOR(L) nand STD_LOGIC_VECTOR(R)); return RESULT; end "nand"; -- Id: L.5 function "nor" (L, R: UNSIGNED) return UNSIGNED is variable RESULT: UNSIGNED(L'LENGTH-1 downto 0); begin RESULT := UNSIGNED(STD_LOGIC_VECTOR(L) nor STD_LOGIC_VECTOR(R)); return RESULT; end "nor"; -- Id: L.6 function "xor" (L, R: UNSIGNED) return UNSIGNED is variable RESULT: UNSIGNED(L'LENGTH-1 downto 0); begin RESULT := UNSIGNED(STD_LOGIC_VECTOR(L) xor STD_LOGIC_VECTOR(R)); return RESULT; end "xor"; --START-V93 ------------------------------------------------------------------------------ -- Note : Function L.7 is not compatible with VHDL 1076-1987. Comment -- out the function (declaration and body) for VHDL 1076-1987 compatibility. ------------------------------------------------------------------------------ -- Id: L.7 function "xnor" (L, R: UNSIGNED) return UNSIGNED is variable RESULT: UNSIGNED(L'LENGTH-1 downto 0); begin RESULT := UNSIGNED(STD_LOGIC_VECTOR(L) xnor STD_LOGIC_VECTOR(R)); return RESULT; end "xnor"; --END-V93 -- Id: L.8 function "not" (L: SIGNED) return SIGNED is variable RESULT: SIGNED(L'LENGTH-1 downto 0); begin RESULT := SIGNED(not(STD_LOGIC_VECTOR(L))); return RESULT; end "not"; -- Id: L.9 function "and" (L, R: SIGNED) return SIGNED is variable RESULT: SIGNED(L'LENGTH-1 downto 0); begin RESULT := SIGNED(STD_LOGIC_VECTOR(L) and STD_LOGIC_VECTOR(R)); return RESULT; end "and"; -- Id: L.10 function "or" (L, R: SIGNED) return SIGNED is variable RESULT: SIGNED(L'LENGTH-1 downto 0); begin RESULT := SIGNED(STD_LOGIC_VECTOR(L) or STD_LOGIC_VECTOR(R)); return RESULT; end "or"; -- Id: L.11 function "nand" (L, R: SIGNED) return SIGNED is variable RESULT: SIGNED(L'LENGTH-1 downto 0); begin RESULT := SIGNED(STD_LOGIC_VECTOR(L) nand STD_LOGIC_VECTOR(R)); return RESULT; end "nand"; -- Id: L.12 function "nor" (L, R: SIGNED) return SIGNED is variable RESULT: SIGNED(L'LENGTH-1 downto 0); begin RESULT := SIGNED(STD_LOGIC_VECTOR(L) nor STD_LOGIC_VECTOR(R)); return RESULT; end "nor"; -- Id: L.13 function "xor" (L, R: SIGNED) return SIGNED is variable RESULT: SIGNED(L'LENGTH-1 downto 0); begin RESULT := SIGNED(STD_LOGIC_VECTOR(L) xor STD_LOGIC_VECTOR(R)); return RESULT; end "xor"; --START-V93 ------------------------------------------------------------------------------ -- Note : Function L.14 is not compatible with VHDL 1076-1987. Comment -- out the function (declaration and body) for VHDL 1076-1987 compatibility. ------------------------------------------------------------------------------ -- Id: L.14 function "xnor" (L, R: SIGNED) return SIGNED is variable RESULT: SIGNED(L'LENGTH-1 downto 0); begin RESULT := SIGNED(STD_LOGIC_VECTOR(L) xnor STD_LOGIC_VECTOR(R)); return RESULT; end "xnor"; --END-V93 --============================================================================ -- support constants for STD_MATCH: type BOOLEAN_TABLE is array(STD_ULOGIC, STD_ULOGIC) of BOOLEAN; constant MATCH_TABLE: BOOLEAN_TABLE := ( -------------------------------------------------------------------------- -- U X 0 1 Z W L H - -------------------------------------------------------------------------- (FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, TRUE), -- | U | (FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, TRUE), -- | X | (FALSE, FALSE, TRUE, FALSE, FALSE, FALSE, TRUE, FALSE, TRUE), -- | 0 | (FALSE, FALSE, FALSE, TRUE, FALSE, FALSE, FALSE, TRUE, TRUE), -- | 1 | (FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, TRUE), -- | Z | (FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, TRUE), -- | W | (FALSE, FALSE, TRUE, FALSE, FALSE, FALSE, TRUE, FALSE, TRUE), -- | L | (FALSE, FALSE, FALSE, TRUE, FALSE, FALSE, FALSE, TRUE, TRUE), -- | H | ( TRUE, TRUE, TRUE, TRUE, TRUE, TRUE, TRUE, TRUE, TRUE) -- | - | ); -- Id: M.1 function STD_MATCH (L, R: STD_ULOGIC) return BOOLEAN is variable VALUE: STD_ULOGIC; begin return MATCH_TABLE(L, R); end STD_MATCH; -- Id: M.2 function STD_MATCH (L, R: UNSIGNED) return BOOLEAN is alias LV: UNSIGNED(1 to L'LENGTH) is L; alias RV: UNSIGNED(1 to R'LENGTH) is R; begin if ((L'LENGTH < 1) or (R'LENGTH < 1)) then assert NO_WARNING report "NUMERIC_STD.STD_MATCH: null detected, returning FALSE" severity WARNING; return FALSE; end if; if LV'LENGTH /= RV'LENGTH then assert NO_WARNING report "NUMERIC_STD.STD_MATCH: L'LENGTH /= R'LENGTH, returning FALSE" severity WARNING; return FALSE; else for I in LV'LOW to LV'HIGH loop if not (MATCH_TABLE(LV(I), RV(I))) then return FALSE; end if; end loop; return TRUE; end if; end STD_MATCH; -- Id: M.3 function STD_MATCH (L, R: SIGNED) return BOOLEAN is alias LV: SIGNED(1 to L'LENGTH) is L; alias RV: SIGNED(1 to R'LENGTH) is R; begin if ((L'LENGTH < 1) or (R'LENGTH < 1)) then assert NO_WARNING report "NUMERIC_STD.STD_MATCH: null detected, returning FALSE" severity WARNING; return FALSE; end if; if LV'LENGTH /= RV'LENGTH then assert NO_WARNING report "NUMERIC_STD.STD_MATCH: L'LENGTH /= R'LENGTH, returning FALSE" severity WARNING; return FALSE; else for I in LV'LOW to LV'HIGH loop if not (MATCH_TABLE(LV(I), RV(I))) then return FALSE; end if; end loop; return TRUE; end if; end STD_MATCH; -- Id: M.4 function STD_MATCH (L, R: STD_LOGIC_VECTOR) return BOOLEAN is alias LV: STD_LOGIC_VECTOR(1 to L'LENGTH) is L; alias RV: STD_LOGIC_VECTOR(1 to R'LENGTH) is R; begin if ((L'LENGTH < 1) or (R'LENGTH < 1)) then assert NO_WARNING report "NUMERIC_STD.STD_MATCH: null detected, returning FALSE" severity WARNING; return FALSE; end if; if LV'LENGTH /= RV'LENGTH then assert NO_WARNING report "NUMERIC_STD.STD_MATCH: L'LENGTH /= R'LENGTH, returning FALSE" severity WARNING; return FALSE; else for I in LV'LOW to LV'HIGH loop if not (MATCH_TABLE(LV(I), RV(I))) then return FALSE; end if; end loop; return TRUE; end if; end STD_MATCH; -- Id: M.5 function STD_MATCH (L, R: STD_ULOGIC_VECTOR) return BOOLEAN is alias LV: STD_ULOGIC_VECTOR(1 to L'LENGTH) is L; alias RV: STD_ULOGIC_VECTOR(1 to R'LENGTH) is R; begin if ((L'LENGTH < 1) or (R'LENGTH < 1)) then assert NO_WARNING report "NUMERIC_STD.STD_MATCH: null detected, returning FALSE" severity WARNING; return FALSE; end if; if LV'LENGTH /= RV'LENGTH then assert NO_WARNING report "NUMERIC_STD.STD_MATCH: L'LENGTH /= R'LENGTH, returning FALSE" severity WARNING; return FALSE; else for I in LV'LOW to LV'HIGH loop if not (MATCH_TABLE(LV(I), RV(I))) then return FALSE; end if; end loop; return TRUE; end if; end STD_MATCH; --============================================================================ -- function TO_01 is used to convert vectors to the -- correct form for exported functions, -- and to report if there is an element which -- is not in (0, 1, H, L). -- Id: T.1 function TO_01 (S: UNSIGNED; XMAP: STD_LOGIC := '0') return UNSIGNED is variable RESULT: UNSIGNED(S'LENGTH-1 downto 0); variable BAD_ELEMENT: BOOLEAN := FALSE; alias XS: UNSIGNED(S'LENGTH-1 downto 0) is S; begin if (S'LENGTH < 1) then assert NO_WARNING report "NUMERIC_STD.TO_01: null detected, returning NAU" severity WARNING; return NAU; end if; for I in RESULT'RANGE loop case XS(I) is when '0' | 'L' => RESULT(I) := '0'; when '1' | 'H' => RESULT(I) := '1'; when others => BAD_ELEMENT := TRUE; end case; end loop; if BAD_ELEMENT then for I in RESULT'RANGE loop RESULT(I) := XMAP; -- standard fixup end loop; end if; return RESULT; end TO_01; -- Id: T.2 function TO_01 (S: SIGNED; XMAP: STD_LOGIC := '0') return SIGNED is variable RESULT: SIGNED(S'LENGTH-1 downto 0); variable BAD_ELEMENT: BOOLEAN := FALSE; alias XS: SIGNED(S'LENGTH-1 downto 0) is S; begin if (S'LENGTH < 1) then assert NO_WARNING report "NUMERIC_STD.TO_01: null detected, returning NAS" severity WARNING; return NAS; end if; for I in RESULT'RANGE loop case XS(I) is when '0' | 'L' => RESULT(I) := '0'; when '1' | 'H' => RESULT(I) := '1'; when others => BAD_ELEMENT := TRUE; end case; end loop; if BAD_ELEMENT then for I in RESULT'RANGE loop RESULT(I) := XMAP; -- standard fixup end loop; end if; return RESULT; end TO_01; --============================================================================ end NUMERIC_STD;
gpl-3.0
1c18be271236e656ec36f7c9fcd06d42
0.56817
3.781447
false
false
false
false
yansyaf/cmake-verilog-vhdl-fpga-template
src/xilinx/fifo.vhd
2
10,044
-------------------------------------------------------------------------------- -- This file is owned and controlled by Xilinx and must be used solely -- -- for design, simulation, implementation and creation of design files -- -- limited to Xilinx devices or technologies. Use with non-Xilinx -- -- devices or technologies is expressly prohibited and immediately -- -- terminates your license. -- -- -- -- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY -- -- FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY -- -- PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE -- -- IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS -- -- MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY -- -- CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY -- -- RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY -- -- DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE -- -- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR -- -- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF -- -- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A -- -- PARTICULAR PURPOSE. -- -- -- -- Xilinx products are not intended for use in life support appliances, -- -- devices, or systems. Use in such applications are expressly -- -- prohibited. -- -- -- -- (c) Copyright 1995-2013 Xilinx, Inc. -- -- All rights reserved. -- -------------------------------------------------------------------------------- -------------------------------------------------------------------------------- -- You must compile the wrapper file fifo.vhd when simulating -- the core, fifo. When compiling the wrapper file, be sure to -- reference the XilinxCoreLib VHDL simulation library. For detailed -- instructions, please refer to the "CORE Generator Help". -- The synthesis directives "translate_off/translate_on" specified -- below are supported by Xilinx, Mentor Graphics and Synplicity -- synthesis tools. Ensure they are correct for your synthesis tool(s). LIBRARY ieee; USE ieee.std_logic_1164.ALL; -- synthesis translate_off LIBRARY XilinxCoreLib; -- synthesis translate_on ENTITY fifo IS PORT ( clk : IN STD_LOGIC; rst : IN STD_LOGIC; din : IN STD_LOGIC_VECTOR(31 DOWNTO 0); wr_en : IN STD_LOGIC; rd_en : IN STD_LOGIC; dout : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); full : OUT STD_LOGIC; empty : OUT STD_LOGIC ); END fifo; ARCHITECTURE fifo_a OF fifo IS -- synthesis translate_off COMPONENT wrapped_fifo PORT ( clk : IN STD_LOGIC; rst : IN STD_LOGIC; din : IN STD_LOGIC_VECTOR(31 DOWNTO 0); wr_en : IN STD_LOGIC; rd_en : IN STD_LOGIC; dout : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); full : OUT STD_LOGIC; empty : OUT STD_LOGIC ); END COMPONENT; -- Configuration specification FOR ALL : wrapped_fifo USE ENTITY XilinxCoreLib.fifo_generator_v8_4(behavioral) GENERIC MAP ( c_add_ngc_constraint => 0, c_application_type_axis => 0, c_application_type_rach => 0, c_application_type_rdch => 0, c_application_type_wach => 0, c_application_type_wdch => 0, c_application_type_wrch => 0, c_axi_addr_width => 32, c_axi_aruser_width => 1, c_axi_awuser_width => 1, c_axi_buser_width => 1, c_axi_data_width => 64, c_axi_id_width => 4, c_axi_ruser_width => 1, c_axi_type => 0, c_axi_wuser_width => 1, c_axis_tdata_width => 64, c_axis_tdest_width => 4, c_axis_tid_width => 8, c_axis_tkeep_width => 4, c_axis_tstrb_width => 4, c_axis_tuser_width => 4, c_axis_type => 0, c_common_clock => 1, c_count_type => 0, c_data_count_width => 10, c_default_value => "BlankString", c_din_width => 32, c_din_width_axis => 1, c_din_width_rach => 32, c_din_width_rdch => 64, c_din_width_wach => 32, c_din_width_wdch => 64, c_din_width_wrch => 2, c_dout_rst_val => "0", c_dout_width => 32, c_enable_rlocs => 0, c_enable_rst_sync => 1, c_error_injection_type => 0, c_error_injection_type_axis => 0, c_error_injection_type_rach => 0, c_error_injection_type_rdch => 0, c_error_injection_type_wach => 0, c_error_injection_type_wdch => 0, c_error_injection_type_wrch => 0, c_family => "spartan6", c_full_flags_rst_val => 1, c_has_almost_empty => 0, c_has_almost_full => 0, c_has_axi_aruser => 0, c_has_axi_awuser => 0, c_has_axi_buser => 0, c_has_axi_rd_channel => 0, c_has_axi_ruser => 0, c_has_axi_wr_channel => 0, c_has_axi_wuser => 0, c_has_axis_tdata => 0, c_has_axis_tdest => 0, c_has_axis_tid => 0, c_has_axis_tkeep => 0, c_has_axis_tlast => 0, c_has_axis_tready => 1, c_has_axis_tstrb => 0, c_has_axis_tuser => 0, c_has_backup => 0, c_has_data_count => 0, c_has_data_counts_axis => 0, c_has_data_counts_rach => 0, c_has_data_counts_rdch => 0, c_has_data_counts_wach => 0, c_has_data_counts_wdch => 0, c_has_data_counts_wrch => 0, c_has_int_clk => 0, c_has_master_ce => 0, c_has_meminit_file => 0, c_has_overflow => 0, c_has_prog_flags_axis => 0, c_has_prog_flags_rach => 0, c_has_prog_flags_rdch => 0, c_has_prog_flags_wach => 0, c_has_prog_flags_wdch => 0, c_has_prog_flags_wrch => 0, c_has_rd_data_count => 0, c_has_rd_rst => 0, c_has_rst => 1, c_has_slave_ce => 0, c_has_srst => 0, c_has_underflow => 0, c_has_valid => 0, c_has_wr_ack => 0, c_has_wr_data_count => 0, c_has_wr_rst => 0, c_implementation_type => 0, c_implementation_type_axis => 1, c_implementation_type_rach => 1, c_implementation_type_rdch => 1, c_implementation_type_wach => 1, c_implementation_type_wdch => 1, c_implementation_type_wrch => 1, c_init_wr_pntr_val => 0, c_interface_type => 0, c_memory_type => 1, c_mif_file_name => "BlankString", c_msgon_val => 1, c_optimization_mode => 0, c_overflow_low => 0, c_preload_latency => 1, c_preload_regs => 0, c_prim_fifo_type => "1kx36", c_prog_empty_thresh_assert_val => 2, c_prog_empty_thresh_assert_val_axis => 1022, c_prog_empty_thresh_assert_val_rach => 1022, c_prog_empty_thresh_assert_val_rdch => 1022, c_prog_empty_thresh_assert_val_wach => 1022, c_prog_empty_thresh_assert_val_wdch => 1022, c_prog_empty_thresh_assert_val_wrch => 1022, c_prog_empty_thresh_negate_val => 3, c_prog_empty_type => 0, c_prog_empty_type_axis => 5, c_prog_empty_type_rach => 5, c_prog_empty_type_rdch => 5, c_prog_empty_type_wach => 5, c_prog_empty_type_wdch => 5, c_prog_empty_type_wrch => 5, c_prog_full_thresh_assert_val => 1022, c_prog_full_thresh_assert_val_axis => 1023, c_prog_full_thresh_assert_val_rach => 1023, c_prog_full_thresh_assert_val_rdch => 1023, c_prog_full_thresh_assert_val_wach => 1023, c_prog_full_thresh_assert_val_wdch => 1023, c_prog_full_thresh_assert_val_wrch => 1023, c_prog_full_thresh_negate_val => 1021, c_prog_full_type => 0, c_prog_full_type_axis => 5, c_prog_full_type_rach => 5, c_prog_full_type_rdch => 5, c_prog_full_type_wach => 5, c_prog_full_type_wdch => 5, c_prog_full_type_wrch => 5, c_rach_type => 0, c_rd_data_count_width => 10, c_rd_depth => 1024, c_rd_freq => 1, c_rd_pntr_width => 10, c_rdch_type => 0, c_reg_slice_mode_axis => 0, c_reg_slice_mode_rach => 0, c_reg_slice_mode_rdch => 0, c_reg_slice_mode_wach => 0, c_reg_slice_mode_wdch => 0, c_reg_slice_mode_wrch => 0, c_synchronizer_stage => 2, c_underflow_low => 0, c_use_common_overflow => 0, c_use_common_underflow => 0, c_use_default_settings => 0, c_use_dout_rst => 1, c_use_ecc => 0, c_use_ecc_axis => 0, c_use_ecc_rach => 0, c_use_ecc_rdch => 0, c_use_ecc_wach => 0, c_use_ecc_wdch => 0, c_use_ecc_wrch => 0, c_use_embedded_reg => 0, c_use_fifo16_flags => 0, c_use_fwft_data_count => 0, c_valid_low => 0, c_wach_type => 0, c_wdch_type => 0, c_wr_ack_low => 0, c_wr_data_count_width => 10, c_wr_depth => 1024, c_wr_depth_axis => 1024, c_wr_depth_rach => 16, c_wr_depth_rdch => 1024, c_wr_depth_wach => 16, c_wr_depth_wdch => 1024, c_wr_depth_wrch => 16, c_wr_freq => 1, c_wr_pntr_width => 10, c_wr_pntr_width_axis => 10, c_wr_pntr_width_rach => 4, c_wr_pntr_width_rdch => 10, c_wr_pntr_width_wach => 4, c_wr_pntr_width_wdch => 10, c_wr_pntr_width_wrch => 4, c_wr_response_latency => 1, c_wrch_type => 0 ); -- synthesis translate_on BEGIN -- synthesis translate_off U0 : wrapped_fifo PORT MAP ( clk => clk, rst => rst, din => din, wr_en => wr_en, rd_en => rd_en, dout => dout, full => full, empty => empty ); -- synthesis translate_on END fifo_a;
apache-2.0
8e3e6853de5aa4eb87aff15d0c53833f
0.534648
3.353589
false
false
false
false
grwlf/vsim
vhdl_ct/ct00339.vhd
1
65,482
-- NEED RESULT: ARCH00339.P1: Multi transport transactions occurred on concurrent signal asg passed -- NEED RESULT: ARCH00339.P2: Multi transport transactions occurred on concurrent signal asg passed -- NEED RESULT: ARCH00339.P3: Multi transport transactions occurred on concurrent signal asg passed -- NEED RESULT: ARCH00339.P4: Multi transport transactions occurred on concurrent signal asg passed -- NEED RESULT: ARCH00339.P5: Multi transport transactions occurred on concurrent signal asg passed -- NEED RESULT: ARCH00339.P6: Multi transport transactions occurred on concurrent signal asg passed -- NEED RESULT: ARCH00339.P7: Multi transport transactions occurred on concurrent signal asg passed -- NEED RESULT: ARCH00339.P8: Multi transport transactions occurred on concurrent signal asg passed -- NEED RESULT: ARCH00339.P9: Multi transport transactions occurred on concurrent signal asg passed -- NEED RESULT: ARCH00339.P10: Multi transport transactions occurred on concurrent signal asg passed -- NEED RESULT: ARCH00339.P11: Multi transport transactions occurred on concurrent signal asg passed -- NEED RESULT: ARCH00339.P12: Multi transport transactions occurred on concurrent signal asg passed -- NEED RESULT: ARCH00339.P13: Multi transport transactions occurred on concurrent signal asg passed -- NEED RESULT: ARCH00339.P14: Multi transport transactions occurred on concurrent signal asg passed -- NEED RESULT: ARCH00339.P15: Multi transport transactions occurred on concurrent signal asg passed -- NEED RESULT: ARCH00339.P16: Multi transport transactions occurred on concurrent signal asg passed -- NEED RESULT: ARCH00339.P17: Multi transport transactions occurred on concurrent signal asg passed -- NEED RESULT: ARCH00339: One transport transaction occurred on a concurrent signal asg passed -- NEED RESULT: ARCH00339: Old transactions were removed on a concurrent signal asg passed -- NEED RESULT: ARCH00339: One transport transaction occurred on a concurrent signal asg passed -- NEED RESULT: ARCH00339: Old transactions were removed on a concurrent signal asg passed -- NEED RESULT: ARCH00339: One transport transaction occurred on a concurrent signal asg passed -- NEED RESULT: ARCH00339: Old transactions were removed on a concurrent signal asg passed -- NEED RESULT: ARCH00339: One transport transaction occurred on a concurrent signal asg passed -- NEED RESULT: ARCH00339: Old transactions were removed on a concurrent signal asg passed -- NEED RESULT: ARCH00339: One transport transaction occurred on a concurrent signal asg passed -- NEED RESULT: ARCH00339: Old transactions were removed on a concurrent signal asg passed -- NEED RESULT: ARCH00339: One transport transaction occurred on a concurrent signal asg passed -- NEED RESULT: ARCH00339: Old transactions were removed on a concurrent signal asg passed -- NEED RESULT: ARCH00339: One transport transaction occurred on a concurrent signal asg passed -- NEED RESULT: ARCH00339: Old transactions were removed on a concurrent signal asg passed -- NEED RESULT: ARCH00339: One transport transaction occurred on a concurrent signal asg passed -- NEED RESULT: ARCH00339: Old transactions were removed on a concurrent signal asg passed -- NEED RESULT: ARCH00339: One transport transaction occurred on a concurrent signal asg passed -- NEED RESULT: ARCH00339: Old transactions were removed on a concurrent signal asg passed -- NEED RESULT: ARCH00339: One transport transaction occurred on a concurrent signal asg passed -- NEED RESULT: ARCH00339: Old transactions were removed on a concurrent signal asg passed -- NEED RESULT: ARCH00339: One transport transaction occurred on a concurrent signal asg passed -- NEED RESULT: ARCH00339: Old transactions were removed on a concurrent signal asg passed -- NEED RESULT: ARCH00339: One transport transaction occurred on a concurrent signal asg passed -- NEED RESULT: ARCH00339: Old transactions were removed on a concurrent signal asg passed -- NEED RESULT: ARCH00339: One transport transaction occurred on a concurrent signal asg passed -- NEED RESULT: ARCH00339: Old transactions were removed on a concurrent signal asg passed -- NEED RESULT: ARCH00339: One transport transaction occurred on a concurrent signal asg passed -- NEED RESULT: ARCH00339: Old transactions were removed on a concurrent signal asg passed -- NEED RESULT: ARCH00339: One transport transaction occurred on a concurrent signal asg passed -- NEED RESULT: ARCH00339: Old transactions were removed on a concurrent signal asg passed -- NEED RESULT: ARCH00339: One transport transaction occurred on a concurrent signal asg passed -- NEED RESULT: ARCH00339: Old transactions were removed on a concurrent signal asg passed -- NEED RESULT: ARCH00339: One transport transaction occurred on a concurrent signal asg passed -- NEED RESULT: ARCH00339: Old transactions were removed on a concurrent signal asg passed -- NEED RESULT: P17: Transport transactions completed entirely passed -- NEED RESULT: P16: Transport transactions completed entirely passed -- NEED RESULT: P15: Transport transactions completed entirely passed -- NEED RESULT: P14: Transport transactions completed entirely passed -- NEED RESULT: P13: Transport transactions completed entirely passed -- NEED RESULT: P12: Transport transactions completed entirely passed -- NEED RESULT: P11: Transport transactions completed entirely passed -- NEED RESULT: P10: Transport transactions completed entirely passed -- NEED RESULT: P9: Transport transactions completed entirely passed -- NEED RESULT: P8: Transport transactions completed entirely passed -- NEED RESULT: P7: Transport transactions completed entirely passed -- NEED RESULT: P6: Transport transactions completed entirely passed -- NEED RESULT: P5: Transport transactions completed entirely passed -- NEED RESULT: P4: Transport transactions completed entirely passed -- NEED RESULT: P3: Transport transactions completed entirely passed -- NEED RESULT: P2: Transport transactions completed entirely passed -- NEED RESULT: P1: Transport transactions completed entirely passed ------------------------------------------------------------------------------- -- -- Copyright (c) 1989 by Intermetrics, Inc. -- All rights reserved. -- ------------------------------------------------------------------------------- -- -- TEST NAME: -- -- CT00339 -- -- AUTHOR: -- -- G. Tominovich -- -- TEST OBJECTIVES: -- -- 9.5 (2) -- 9.5.1 (1) -- 9.5.1 (2) -- -- DESIGN UNIT ORDERING: -- -- ENT00339(ARCH00339) -- ENT00339_Test_Bench(ARCH00339_Test_Bench) -- -- REVISION HISTORY: -- -- 30-JUL-1987 - initial revision -- -- NOTES: -- -- self-checking -- automatically generated -- use WORK.STANDARD_TYPES.all ; entity ENT00339 is port ( s_boolean : inout boolean ; s_bit : inout bit ; s_severity_level : inout severity_level ; s_character : inout character ; s_st_enum1 : inout st_enum1 ; s_integer : inout integer ; s_st_int1 : inout st_int1 ; s_time : inout time ; s_st_phys1 : inout st_phys1 ; s_real : inout real ; s_st_real1 : inout st_real1 ; s_st_rec1 : inout st_rec1 ; s_st_rec2 : inout st_rec2 ; s_st_rec3 : inout st_rec3 ; s_st_arr1 : inout st_arr1 ; s_st_arr2 : inout st_arr2 ; s_st_arr3 : inout st_arr3 ) ; subtype chk_sig_type is integer range -1 to 100 ; signal chk_boolean : chk_sig_type := -1 ; signal chk_bit : chk_sig_type := -1 ; signal chk_severity_level : chk_sig_type := -1 ; signal chk_character : chk_sig_type := -1 ; signal chk_st_enum1 : chk_sig_type := -1 ; signal chk_integer : chk_sig_type := -1 ; signal chk_st_int1 : chk_sig_type := -1 ; signal chk_time : chk_sig_type := -1 ; signal chk_st_phys1 : chk_sig_type := -1 ; signal chk_real : chk_sig_type := -1 ; signal chk_st_real1 : chk_sig_type := -1 ; signal chk_st_rec1 : chk_sig_type := -1 ; signal chk_st_rec2 : chk_sig_type := -1 ; signal chk_st_rec3 : chk_sig_type := -1 ; signal chk_st_arr1 : chk_sig_type := -1 ; signal chk_st_arr2 : chk_sig_type := -1 ; signal chk_st_arr3 : chk_sig_type := -1 ; -- end ENT00339 ; -- -- architecture ARCH00339 of ENT00339 is subtype chk_time_type is Time ; signal s_boolean_savt : chk_time_type := 0 ns ; signal s_bit_savt : chk_time_type := 0 ns ; signal s_severity_level_savt : chk_time_type := 0 ns ; signal s_character_savt : chk_time_type := 0 ns ; signal s_st_enum1_savt : chk_time_type := 0 ns ; signal s_integer_savt : chk_time_type := 0 ns ; signal s_st_int1_savt : chk_time_type := 0 ns ; signal s_time_savt : chk_time_type := 0 ns ; signal s_st_phys1_savt : chk_time_type := 0 ns ; signal s_real_savt : chk_time_type := 0 ns ; signal s_st_real1_savt : chk_time_type := 0 ns ; signal s_st_rec1_savt : chk_time_type := 0 ns ; signal s_st_rec2_savt : chk_time_type := 0 ns ; signal s_st_rec3_savt : chk_time_type := 0 ns ; signal s_st_arr1_savt : chk_time_type := 0 ns ; signal s_st_arr2_savt : chk_time_type := 0 ns ; signal s_st_arr3_savt : chk_time_type := 0 ns ; -- subtype chk_cnt_type is Integer ; signal s_boolean_cnt : chk_cnt_type := 0 ; signal s_bit_cnt : chk_cnt_type := 0 ; signal s_severity_level_cnt : chk_cnt_type := 0 ; signal s_character_cnt : chk_cnt_type := 0 ; signal s_st_enum1_cnt : chk_cnt_type := 0 ; signal s_integer_cnt : chk_cnt_type := 0 ; signal s_st_int1_cnt : chk_cnt_type := 0 ; signal s_time_cnt : chk_cnt_type := 0 ; signal s_st_phys1_cnt : chk_cnt_type := 0 ; signal s_real_cnt : chk_cnt_type := 0 ; signal s_st_real1_cnt : chk_cnt_type := 0 ; signal s_st_rec1_cnt : chk_cnt_type := 0 ; signal s_st_rec2_cnt : chk_cnt_type := 0 ; signal s_st_rec3_cnt : chk_cnt_type := 0 ; signal s_st_arr1_cnt : chk_cnt_type := 0 ; signal s_st_arr2_cnt : chk_cnt_type := 0 ; signal s_st_arr3_cnt : chk_cnt_type := 0 ; -- type select_type is range 1 to 3 ; signal boolean_select : select_type := 1 ; signal bit_select : select_type := 1 ; signal severity_level_select : select_type := 1 ; signal character_select : select_type := 1 ; signal st_enum1_select : select_type := 1 ; signal integer_select : select_type := 1 ; signal st_int1_select : select_type := 1 ; signal time_select : select_type := 1 ; signal st_phys1_select : select_type := 1 ; signal real_select : select_type := 1 ; signal st_real1_select : select_type := 1 ; signal st_rec1_select : select_type := 1 ; signal st_rec2_select : select_type := 1 ; signal st_rec3_select : select_type := 1 ; signal st_arr1_select : select_type := 1 ; signal st_arr2_select : select_type := 1 ; signal st_arr3_select : select_type := 1 ; -- begin CHG1 : process ( s_boolean ) variable correct : boolean ; begin case s_boolean_cnt is when 0 => null ; -- s_boolean <= transport -- c_boolean_2 after 10 ns, -- c_boolean_1 after 20 ns ; -- when 1 => correct := s_boolean = c_boolean_2 and (s_boolean_savt + 10 ns) = Std.Standard.Now ; -- when 2 => correct := correct and s_boolean = c_boolean_1 and (s_boolean_savt + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00339.P1" , "Multi transport transactions occurred on " & "concurrent signal asg", correct ) ; -- boolean_select <= transport 2 ; -- s_boolean <= transport -- c_boolean_2 after 10 ns , -- c_boolean_1 after 20 ns , -- c_boolean_2 after 30 ns , -- c_boolean_1 after 40 ns ; -- when 3 => correct := s_boolean = c_boolean_2 and (s_boolean_savt + 10 ns) = Std.Standard.Now ; boolean_select <= transport 3 ; -- s_boolean <= transport -- c_boolean_1 after 5 ns ; -- when 4 => correct := correct and s_boolean = c_boolean_1 and (s_boolean_savt + 5 ns) = Std.Standard.Now ; test_report ( "ARCH00339" , "One transport transaction occurred on a " & "concurrent signal asg", correct ) ; test_report ( "ARCH00339" , "Old transactions were removed on a " & "concurrent signal asg", correct ) ; -- when others => -- No more transactions should have occurred test_report ( "ARCH00339" , "Old transactions were removed on a " & "concurrent signal asg", false ) ; -- end case ; -- s_boolean_savt <= transport Std.Standard.Now ; chk_boolean <= transport s_boolean_cnt after (1 us - Std.Standard.Now) ; s_boolean_cnt <= transport s_boolean_cnt + 1 ; -- end process CHG1 ; -- PGEN_CHKP_1 : process ( chk_boolean ) begin if Std.Standard.Now > 0 ns then test_report ( "P1" , "Transport transactions completed entirely", chk_boolean = 4 ) ; end if ; end process PGEN_CHKP_1 ; -- -- s_boolean <= transport c_boolean_2 after 10 ns, c_boolean_1 after 20 ns when boolean_select = 1 else -- c_boolean_2 after 10 ns , c_boolean_1 after 20 ns , c_boolean_2 after 30 ns , c_boolean_1 after 40 ns when boolean_select = 2 else -- c_boolean_1 after 5 ns ; -- CHG2 : process ( s_bit ) variable correct : boolean ; begin case s_bit_cnt is when 0 => null ; -- s_bit <= transport -- c_bit_2 after 10 ns, -- c_bit_1 after 20 ns ; -- when 1 => correct := s_bit = c_bit_2 and (s_bit_savt + 10 ns) = Std.Standard.Now ; -- when 2 => correct := correct and s_bit = c_bit_1 and (s_bit_savt + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00339.P2" , "Multi transport transactions occurred on " & "concurrent signal asg", correct ) ; -- bit_select <= transport 2 ; -- s_bit <= transport -- c_bit_2 after 10 ns , -- c_bit_1 after 20 ns , -- c_bit_2 after 30 ns , -- c_bit_1 after 40 ns ; -- when 3 => correct := s_bit = c_bit_2 and (s_bit_savt + 10 ns) = Std.Standard.Now ; bit_select <= transport 3 ; -- s_bit <= transport -- c_bit_1 after 5 ns ; -- when 4 => correct := correct and s_bit = c_bit_1 and (s_bit_savt + 5 ns) = Std.Standard.Now ; test_report ( "ARCH00339" , "One transport transaction occurred on a " & "concurrent signal asg", correct ) ; test_report ( "ARCH00339" , "Old transactions were removed on a " & "concurrent signal asg", correct ) ; -- when others => -- No more transactions should have occurred test_report ( "ARCH00339" , "Old transactions were removed on a " & "concurrent signal asg", false ) ; -- end case ; -- s_bit_savt <= transport Std.Standard.Now ; chk_bit <= transport s_bit_cnt after (1 us - Std.Standard.Now) ; s_bit_cnt <= transport s_bit_cnt + 1 ; -- end process CHG2 ; -- PGEN_CHKP_2 : process ( chk_bit ) begin if Std.Standard.Now > 0 ns then test_report ( "P2" , "Transport transactions completed entirely", chk_bit = 4 ) ; end if ; end process PGEN_CHKP_2 ; -- -- s_bit <= transport c_bit_2 after 10 ns, c_bit_1 after 20 ns when bit_select = 1 else -- c_bit_2 after 10 ns , c_bit_1 after 20 ns , c_bit_2 after 30 ns , c_bit_1 after 40 ns when bit_select = 2 else -- c_bit_1 after 5 ns ; -- CHG3 : process ( s_severity_level ) variable correct : boolean ; begin case s_severity_level_cnt is when 0 => null ; -- s_severity_level <= transport -- c_severity_level_2 after 10 ns, -- c_severity_level_1 after 20 ns ; -- when 1 => correct := s_severity_level = c_severity_level_2 and (s_severity_level_savt + 10 ns) = Std.Standard.Now ; -- when 2 => correct := correct and s_severity_level = c_severity_level_1 and (s_severity_level_savt + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00339.P3" , "Multi transport transactions occurred on " & "concurrent signal asg", correct ) ; -- severity_level_select <= transport 2 ; -- s_severity_level <= transport -- c_severity_level_2 after 10 ns , -- c_severity_level_1 after 20 ns , -- c_severity_level_2 after 30 ns , -- c_severity_level_1 after 40 ns ; -- when 3 => correct := s_severity_level = c_severity_level_2 and (s_severity_level_savt + 10 ns) = Std.Standard.Now ; severity_level_select <= transport 3 ; -- s_severity_level <= transport -- c_severity_level_1 after 5 ns ; -- when 4 => correct := correct and s_severity_level = c_severity_level_1 and (s_severity_level_savt + 5 ns) = Std.Standard.Now ; test_report ( "ARCH00339" , "One transport transaction occurred on a " & "concurrent signal asg", correct ) ; test_report ( "ARCH00339" , "Old transactions were removed on a " & "concurrent signal asg", correct ) ; -- when others => -- No more transactions should have occurred test_report ( "ARCH00339" , "Old transactions were removed on a " & "concurrent signal asg", false ) ; -- end case ; -- s_severity_level_savt <= transport Std.Standard.Now ; chk_severity_level <= transport s_severity_level_cnt after (1 us - Std.Standard.Now) ; s_severity_level_cnt <= transport s_severity_level_cnt + 1 ; -- end process CHG3 ; -- PGEN_CHKP_3 : process ( chk_severity_level ) begin if Std.Standard.Now > 0 ns then test_report ( "P3" , "Transport transactions completed entirely", chk_severity_level = 4 ) ; end if ; end process PGEN_CHKP_3 ; -- -- s_severity_level <= transport c_severity_level_2 after 10 ns, c_severity_level_1 after 20 ns when severity_level_select = 1 else -- c_severity_level_2 after 10 ns , c_severity_level_1 after 20 ns , c_severity_level_2 after 30 ns , c_severity_level_1 after 40 ns when severity_level_select = 2 else -- c_severity_level_1 after 5 ns ; -- CHG4 : process ( s_character ) variable correct : boolean ; begin case s_character_cnt is when 0 => null ; -- s_character <= transport -- c_character_2 after 10 ns, -- c_character_1 after 20 ns ; -- when 1 => correct := s_character = c_character_2 and (s_character_savt + 10 ns) = Std.Standard.Now ; -- when 2 => correct := correct and s_character = c_character_1 and (s_character_savt + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00339.P4" , "Multi transport transactions occurred on " & "concurrent signal asg", correct ) ; -- character_select <= transport 2 ; -- s_character <= transport -- c_character_2 after 10 ns , -- c_character_1 after 20 ns , -- c_character_2 after 30 ns , -- c_character_1 after 40 ns ; -- when 3 => correct := s_character = c_character_2 and (s_character_savt + 10 ns) = Std.Standard.Now ; character_select <= transport 3 ; -- s_character <= transport -- c_character_1 after 5 ns ; -- when 4 => correct := correct and s_character = c_character_1 and (s_character_savt + 5 ns) = Std.Standard.Now ; test_report ( "ARCH00339" , "One transport transaction occurred on a " & "concurrent signal asg", correct ) ; test_report ( "ARCH00339" , "Old transactions were removed on a " & "concurrent signal asg", correct ) ; -- when others => -- No more transactions should have occurred test_report ( "ARCH00339" , "Old transactions were removed on a " & "concurrent signal asg", false ) ; -- end case ; -- s_character_savt <= transport Std.Standard.Now ; chk_character <= transport s_character_cnt after (1 us - Std.Standard.Now) ; s_character_cnt <= transport s_character_cnt + 1 ; -- end process CHG4 ; -- PGEN_CHKP_4 : process ( chk_character ) begin if Std.Standard.Now > 0 ns then test_report ( "P4" , "Transport transactions completed entirely", chk_character = 4 ) ; end if ; end process PGEN_CHKP_4 ; -- -- s_character <= transport c_character_2 after 10 ns, c_character_1 after 20 ns when character_select = 1 else -- c_character_2 after 10 ns , c_character_1 after 20 ns , c_character_2 after 30 ns , c_character_1 after 40 ns when character_select = 2 else -- c_character_1 after 5 ns ; -- CHG5 : process ( s_st_enum1 ) variable correct : boolean ; begin case s_st_enum1_cnt is when 0 => null ; -- s_st_enum1 <= transport -- c_st_enum1_2 after 10 ns, -- c_st_enum1_1 after 20 ns ; -- when 1 => correct := s_st_enum1 = c_st_enum1_2 and (s_st_enum1_savt + 10 ns) = Std.Standard.Now ; -- when 2 => correct := correct and s_st_enum1 = c_st_enum1_1 and (s_st_enum1_savt + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00339.P5" , "Multi transport transactions occurred on " & "concurrent signal asg", correct ) ; -- st_enum1_select <= transport 2 ; -- s_st_enum1 <= transport -- c_st_enum1_2 after 10 ns , -- c_st_enum1_1 after 20 ns , -- c_st_enum1_2 after 30 ns , -- c_st_enum1_1 after 40 ns ; -- when 3 => correct := s_st_enum1 = c_st_enum1_2 and (s_st_enum1_savt + 10 ns) = Std.Standard.Now ; st_enum1_select <= transport 3 ; -- s_st_enum1 <= transport -- c_st_enum1_1 after 5 ns ; -- when 4 => correct := correct and s_st_enum1 = c_st_enum1_1 and (s_st_enum1_savt + 5 ns) = Std.Standard.Now ; test_report ( "ARCH00339" , "One transport transaction occurred on a " & "concurrent signal asg", correct ) ; test_report ( "ARCH00339" , "Old transactions were removed on a " & "concurrent signal asg", correct ) ; -- when others => -- No more transactions should have occurred test_report ( "ARCH00339" , "Old transactions were removed on a " & "concurrent signal asg", false ) ; -- end case ; -- s_st_enum1_savt <= transport Std.Standard.Now ; chk_st_enum1 <= transport s_st_enum1_cnt after (1 us - Std.Standard.Now) ; s_st_enum1_cnt <= transport s_st_enum1_cnt + 1 ; -- end process CHG5 ; -- PGEN_CHKP_5 : process ( chk_st_enum1 ) begin if Std.Standard.Now > 0 ns then test_report ( "P5" , "Transport transactions completed entirely", chk_st_enum1 = 4 ) ; end if ; end process PGEN_CHKP_5 ; -- -- s_st_enum1 <= transport c_st_enum1_2 after 10 ns, c_st_enum1_1 after 20 ns when st_enum1_select = 1 else -- c_st_enum1_2 after 10 ns , c_st_enum1_1 after 20 ns , c_st_enum1_2 after 30 ns , c_st_enum1_1 after 40 ns when st_enum1_select = 2 else -- c_st_enum1_1 after 5 ns ; -- CHG6 : process ( s_integer ) variable correct : boolean ; begin case s_integer_cnt is when 0 => null ; -- s_integer <= transport -- c_integer_2 after 10 ns, -- c_integer_1 after 20 ns ; -- when 1 => correct := s_integer = c_integer_2 and (s_integer_savt + 10 ns) = Std.Standard.Now ; -- when 2 => correct := correct and s_integer = c_integer_1 and (s_integer_savt + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00339.P6" , "Multi transport transactions occurred on " & "concurrent signal asg", correct ) ; -- integer_select <= transport 2 ; -- s_integer <= transport -- c_integer_2 after 10 ns , -- c_integer_1 after 20 ns , -- c_integer_2 after 30 ns , -- c_integer_1 after 40 ns ; -- when 3 => correct := s_integer = c_integer_2 and (s_integer_savt + 10 ns) = Std.Standard.Now ; integer_select <= transport 3 ; -- s_integer <= transport -- c_integer_1 after 5 ns ; -- when 4 => correct := correct and s_integer = c_integer_1 and (s_integer_savt + 5 ns) = Std.Standard.Now ; test_report ( "ARCH00339" , "One transport transaction occurred on a " & "concurrent signal asg", correct ) ; test_report ( "ARCH00339" , "Old transactions were removed on a " & "concurrent signal asg", correct ) ; -- when others => -- No more transactions should have occurred test_report ( "ARCH00339" , "Old transactions were removed on a " & "concurrent signal asg", false ) ; -- end case ; -- s_integer_savt <= transport Std.Standard.Now ; chk_integer <= transport s_integer_cnt after (1 us - Std.Standard.Now) ; s_integer_cnt <= transport s_integer_cnt + 1 ; -- end process CHG6 ; -- PGEN_CHKP_6 : process ( chk_integer ) begin if Std.Standard.Now > 0 ns then test_report ( "P6" , "Transport transactions completed entirely", chk_integer = 4 ) ; end if ; end process PGEN_CHKP_6 ; -- -- s_integer <= transport c_integer_2 after 10 ns, c_integer_1 after 20 ns when integer_select = 1 else -- c_integer_2 after 10 ns , c_integer_1 after 20 ns , c_integer_2 after 30 ns , c_integer_1 after 40 ns when integer_select = 2 else -- c_integer_1 after 5 ns ; -- CHG7 : process ( s_st_int1 ) variable correct : boolean ; begin case s_st_int1_cnt is when 0 => null ; -- s_st_int1 <= transport -- c_st_int1_2 after 10 ns, -- c_st_int1_1 after 20 ns ; -- when 1 => correct := s_st_int1 = c_st_int1_2 and (s_st_int1_savt + 10 ns) = Std.Standard.Now ; -- when 2 => correct := correct and s_st_int1 = c_st_int1_1 and (s_st_int1_savt + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00339.P7" , "Multi transport transactions occurred on " & "concurrent signal asg", correct ) ; -- st_int1_select <= transport 2 ; -- s_st_int1 <= transport -- c_st_int1_2 after 10 ns , -- c_st_int1_1 after 20 ns , -- c_st_int1_2 after 30 ns , -- c_st_int1_1 after 40 ns ; -- when 3 => correct := s_st_int1 = c_st_int1_2 and (s_st_int1_savt + 10 ns) = Std.Standard.Now ; st_int1_select <= transport 3 ; -- s_st_int1 <= transport -- c_st_int1_1 after 5 ns ; -- when 4 => correct := correct and s_st_int1 = c_st_int1_1 and (s_st_int1_savt + 5 ns) = Std.Standard.Now ; test_report ( "ARCH00339" , "One transport transaction occurred on a " & "concurrent signal asg", correct ) ; test_report ( "ARCH00339" , "Old transactions were removed on a " & "concurrent signal asg", correct ) ; -- when others => -- No more transactions should have occurred test_report ( "ARCH00339" , "Old transactions were removed on a " & "concurrent signal asg", false ) ; -- end case ; -- s_st_int1_savt <= transport Std.Standard.Now ; chk_st_int1 <= transport s_st_int1_cnt after (1 us - Std.Standard.Now) ; s_st_int1_cnt <= transport s_st_int1_cnt + 1 ; -- end process CHG7 ; -- PGEN_CHKP_7 : process ( chk_st_int1 ) begin if Std.Standard.Now > 0 ns then test_report ( "P7" , "Transport transactions completed entirely", chk_st_int1 = 4 ) ; end if ; end process PGEN_CHKP_7 ; -- -- s_st_int1 <= transport c_st_int1_2 after 10 ns, c_st_int1_1 after 20 ns when st_int1_select = 1 else -- c_st_int1_2 after 10 ns , c_st_int1_1 after 20 ns , c_st_int1_2 after 30 ns , c_st_int1_1 after 40 ns when st_int1_select = 2 else -- c_st_int1_1 after 5 ns ; -- CHG8 : process ( s_time ) variable correct : boolean ; begin case s_time_cnt is when 0 => null ; -- s_time <= transport -- c_time_2 after 10 ns, -- c_time_1 after 20 ns ; -- when 1 => correct := s_time = c_time_2 and (s_time_savt + 10 ns) = Std.Standard.Now ; -- when 2 => correct := correct and s_time = c_time_1 and (s_time_savt + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00339.P8" , "Multi transport transactions occurred on " & "concurrent signal asg", correct ) ; -- time_select <= transport 2 ; -- s_time <= transport -- c_time_2 after 10 ns , -- c_time_1 after 20 ns , -- c_time_2 after 30 ns , -- c_time_1 after 40 ns ; -- when 3 => correct := s_time = c_time_2 and (s_time_savt + 10 ns) = Std.Standard.Now ; time_select <= transport 3 ; -- s_time <= transport -- c_time_1 after 5 ns ; -- when 4 => correct := correct and s_time = c_time_1 and (s_time_savt + 5 ns) = Std.Standard.Now ; test_report ( "ARCH00339" , "One transport transaction occurred on a " & "concurrent signal asg", correct ) ; test_report ( "ARCH00339" , "Old transactions were removed on a " & "concurrent signal asg", correct ) ; -- when others => -- No more transactions should have occurred test_report ( "ARCH00339" , "Old transactions were removed on a " & "concurrent signal asg", false ) ; -- end case ; -- s_time_savt <= transport Std.Standard.Now ; chk_time <= transport s_time_cnt after (1 us - Std.Standard.Now) ; s_time_cnt <= transport s_time_cnt + 1 ; -- end process CHG8 ; -- PGEN_CHKP_8 : process ( chk_time ) begin if Std.Standard.Now > 0 ns then test_report ( "P8" , "Transport transactions completed entirely", chk_time = 4 ) ; end if ; end process PGEN_CHKP_8 ; -- -- s_time <= transport c_time_2 after 10 ns, c_time_1 after 20 ns when time_select = 1 else -- c_time_2 after 10 ns , c_time_1 after 20 ns , c_time_2 after 30 ns , c_time_1 after 40 ns when time_select = 2 else -- c_time_1 after 5 ns ; -- CHG9 : process ( s_st_phys1 ) variable correct : boolean ; begin case s_st_phys1_cnt is when 0 => null ; -- s_st_phys1 <= transport -- c_st_phys1_2 after 10 ns, -- c_st_phys1_1 after 20 ns ; -- when 1 => correct := s_st_phys1 = c_st_phys1_2 and (s_st_phys1_savt + 10 ns) = Std.Standard.Now ; -- when 2 => correct := correct and s_st_phys1 = c_st_phys1_1 and (s_st_phys1_savt + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00339.P9" , "Multi transport transactions occurred on " & "concurrent signal asg", correct ) ; -- st_phys1_select <= transport 2 ; -- s_st_phys1 <= transport -- c_st_phys1_2 after 10 ns , -- c_st_phys1_1 after 20 ns , -- c_st_phys1_2 after 30 ns , -- c_st_phys1_1 after 40 ns ; -- when 3 => correct := s_st_phys1 = c_st_phys1_2 and (s_st_phys1_savt + 10 ns) = Std.Standard.Now ; st_phys1_select <= transport 3 ; -- s_st_phys1 <= transport -- c_st_phys1_1 after 5 ns ; -- when 4 => correct := correct and s_st_phys1 = c_st_phys1_1 and (s_st_phys1_savt + 5 ns) = Std.Standard.Now ; test_report ( "ARCH00339" , "One transport transaction occurred on a " & "concurrent signal asg", correct ) ; test_report ( "ARCH00339" , "Old transactions were removed on a " & "concurrent signal asg", correct ) ; -- when others => -- No more transactions should have occurred test_report ( "ARCH00339" , "Old transactions were removed on a " & "concurrent signal asg", false ) ; -- end case ; -- s_st_phys1_savt <= transport Std.Standard.Now ; chk_st_phys1 <= transport s_st_phys1_cnt after (1 us - Std.Standard.Now) ; s_st_phys1_cnt <= transport s_st_phys1_cnt + 1 ; -- end process CHG9 ; -- PGEN_CHKP_9 : process ( chk_st_phys1 ) begin if Std.Standard.Now > 0 ns then test_report ( "P9" , "Transport transactions completed entirely", chk_st_phys1 = 4 ) ; end if ; end process PGEN_CHKP_9 ; -- -- s_st_phys1 <= transport c_st_phys1_2 after 10 ns, c_st_phys1_1 after 20 ns when st_phys1_select = 1 else -- c_st_phys1_2 after 10 ns , c_st_phys1_1 after 20 ns , c_st_phys1_2 after 30 ns , c_st_phys1_1 after 40 ns when st_phys1_select = 2 else -- c_st_phys1_1 after 5 ns ; -- CHG10 : process ( s_real ) variable correct : boolean ; begin case s_real_cnt is when 0 => null ; -- s_real <= transport -- c_real_2 after 10 ns, -- c_real_1 after 20 ns ; -- when 1 => correct := s_real = c_real_2 and (s_real_savt + 10 ns) = Std.Standard.Now ; -- when 2 => correct := correct and s_real = c_real_1 and (s_real_savt + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00339.P10" , "Multi transport transactions occurred on " & "concurrent signal asg", correct ) ; -- real_select <= transport 2 ; -- s_real <= transport -- c_real_2 after 10 ns , -- c_real_1 after 20 ns , -- c_real_2 after 30 ns , -- c_real_1 after 40 ns ; -- when 3 => correct := s_real = c_real_2 and (s_real_savt + 10 ns) = Std.Standard.Now ; real_select <= transport 3 ; -- s_real <= transport -- c_real_1 after 5 ns ; -- when 4 => correct := correct and s_real = c_real_1 and (s_real_savt + 5 ns) = Std.Standard.Now ; test_report ( "ARCH00339" , "One transport transaction occurred on a " & "concurrent signal asg", correct ) ; test_report ( "ARCH00339" , "Old transactions were removed on a " & "concurrent signal asg", correct ) ; -- when others => -- No more transactions should have occurred test_report ( "ARCH00339" , "Old transactions were removed on a " & "concurrent signal asg", false ) ; -- end case ; -- s_real_savt <= transport Std.Standard.Now ; chk_real <= transport s_real_cnt after (1 us - Std.Standard.Now) ; s_real_cnt <= transport s_real_cnt + 1 ; -- end process CHG10 ; -- PGEN_CHKP_10 : process ( chk_real ) begin if Std.Standard.Now > 0 ns then test_report ( "P10" , "Transport transactions completed entirely", chk_real = 4 ) ; end if ; end process PGEN_CHKP_10 ; -- -- s_real <= transport c_real_2 after 10 ns, c_real_1 after 20 ns when real_select = 1 else -- c_real_2 after 10 ns , c_real_1 after 20 ns , c_real_2 after 30 ns , c_real_1 after 40 ns when real_select = 2 else -- c_real_1 after 5 ns ; -- CHG11 : process ( s_st_real1 ) variable correct : boolean ; begin case s_st_real1_cnt is when 0 => null ; -- s_st_real1 <= transport -- c_st_real1_2 after 10 ns, -- c_st_real1_1 after 20 ns ; -- when 1 => correct := s_st_real1 = c_st_real1_2 and (s_st_real1_savt + 10 ns) = Std.Standard.Now ; -- when 2 => correct := correct and s_st_real1 = c_st_real1_1 and (s_st_real1_savt + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00339.P11" , "Multi transport transactions occurred on " & "concurrent signal asg", correct ) ; -- st_real1_select <= transport 2 ; -- s_st_real1 <= transport -- c_st_real1_2 after 10 ns , -- c_st_real1_1 after 20 ns , -- c_st_real1_2 after 30 ns , -- c_st_real1_1 after 40 ns ; -- when 3 => correct := s_st_real1 = c_st_real1_2 and (s_st_real1_savt + 10 ns) = Std.Standard.Now ; st_real1_select <= transport 3 ; -- s_st_real1 <= transport -- c_st_real1_1 after 5 ns ; -- when 4 => correct := correct and s_st_real1 = c_st_real1_1 and (s_st_real1_savt + 5 ns) = Std.Standard.Now ; test_report ( "ARCH00339" , "One transport transaction occurred on a " & "concurrent signal asg", correct ) ; test_report ( "ARCH00339" , "Old transactions were removed on a " & "concurrent signal asg", correct ) ; -- when others => -- No more transactions should have occurred test_report ( "ARCH00339" , "Old transactions were removed on a " & "concurrent signal asg", false ) ; -- end case ; -- s_st_real1_savt <= transport Std.Standard.Now ; chk_st_real1 <= transport s_st_real1_cnt after (1 us - Std.Standard.Now) ; s_st_real1_cnt <= transport s_st_real1_cnt + 1 ; -- end process CHG11 ; -- PGEN_CHKP_11 : process ( chk_st_real1 ) begin if Std.Standard.Now > 0 ns then test_report ( "P11" , "Transport transactions completed entirely", chk_st_real1 = 4 ) ; end if ; end process PGEN_CHKP_11 ; -- -- s_st_real1 <= transport c_st_real1_2 after 10 ns, c_st_real1_1 after 20 ns when st_real1_select = 1 else -- c_st_real1_2 after 10 ns , c_st_real1_1 after 20 ns , c_st_real1_2 after 30 ns , c_st_real1_1 after 40 ns when st_real1_select = 2 else -- c_st_real1_1 after 5 ns ; -- CHG12 : process ( s_st_rec1 ) variable correct : boolean ; begin case s_st_rec1_cnt is when 0 => null ; -- s_st_rec1 <= transport -- c_st_rec1_2 after 10 ns, -- c_st_rec1_1 after 20 ns ; -- when 1 => correct := s_st_rec1 = c_st_rec1_2 and (s_st_rec1_savt + 10 ns) = Std.Standard.Now ; -- when 2 => correct := correct and s_st_rec1 = c_st_rec1_1 and (s_st_rec1_savt + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00339.P12" , "Multi transport transactions occurred on " & "concurrent signal asg", correct ) ; -- st_rec1_select <= transport 2 ; -- s_st_rec1 <= transport -- c_st_rec1_2 after 10 ns , -- c_st_rec1_1 after 20 ns , -- c_st_rec1_2 after 30 ns , -- c_st_rec1_1 after 40 ns ; -- when 3 => correct := s_st_rec1 = c_st_rec1_2 and (s_st_rec1_savt + 10 ns) = Std.Standard.Now ; st_rec1_select <= transport 3 ; -- s_st_rec1 <= transport -- c_st_rec1_1 after 5 ns ; -- when 4 => correct := correct and s_st_rec1 = c_st_rec1_1 and (s_st_rec1_savt + 5 ns) = Std.Standard.Now ; test_report ( "ARCH00339" , "One transport transaction occurred on a " & "concurrent signal asg", correct ) ; test_report ( "ARCH00339" , "Old transactions were removed on a " & "concurrent signal asg", correct ) ; -- when others => -- No more transactions should have occurred test_report ( "ARCH00339" , "Old transactions were removed on a " & "concurrent signal asg", false ) ; -- end case ; -- s_st_rec1_savt <= transport Std.Standard.Now ; chk_st_rec1 <= transport s_st_rec1_cnt after (1 us - Std.Standard.Now) ; s_st_rec1_cnt <= transport s_st_rec1_cnt + 1 ; -- end process CHG12 ; -- PGEN_CHKP_12 : process ( chk_st_rec1 ) begin if Std.Standard.Now > 0 ns then test_report ( "P12" , "Transport transactions completed entirely", chk_st_rec1 = 4 ) ; end if ; end process PGEN_CHKP_12 ; -- -- s_st_rec1 <= transport c_st_rec1_2 after 10 ns, c_st_rec1_1 after 20 ns when st_rec1_select = 1 else -- c_st_rec1_2 after 10 ns , c_st_rec1_1 after 20 ns , c_st_rec1_2 after 30 ns , c_st_rec1_1 after 40 ns when st_rec1_select = 2 else -- c_st_rec1_1 after 5 ns ; -- CHG13 : process ( s_st_rec2 ) variable correct : boolean ; begin case s_st_rec2_cnt is when 0 => null ; -- s_st_rec2 <= transport -- c_st_rec2_2 after 10 ns, -- c_st_rec2_1 after 20 ns ; -- when 1 => correct := s_st_rec2 = c_st_rec2_2 and (s_st_rec2_savt + 10 ns) = Std.Standard.Now ; -- when 2 => correct := correct and s_st_rec2 = c_st_rec2_1 and (s_st_rec2_savt + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00339.P13" , "Multi transport transactions occurred on " & "concurrent signal asg", correct ) ; -- st_rec2_select <= transport 2 ; -- s_st_rec2 <= transport -- c_st_rec2_2 after 10 ns , -- c_st_rec2_1 after 20 ns , -- c_st_rec2_2 after 30 ns , -- c_st_rec2_1 after 40 ns ; -- when 3 => correct := s_st_rec2 = c_st_rec2_2 and (s_st_rec2_savt + 10 ns) = Std.Standard.Now ; st_rec2_select <= transport 3 ; -- s_st_rec2 <= transport -- c_st_rec2_1 after 5 ns ; -- when 4 => correct := correct and s_st_rec2 = c_st_rec2_1 and (s_st_rec2_savt + 5 ns) = Std.Standard.Now ; test_report ( "ARCH00339" , "One transport transaction occurred on a " & "concurrent signal asg", correct ) ; test_report ( "ARCH00339" , "Old transactions were removed on a " & "concurrent signal asg", correct ) ; -- when others => -- No more transactions should have occurred test_report ( "ARCH00339" , "Old transactions were removed on a " & "concurrent signal asg", false ) ; -- end case ; -- s_st_rec2_savt <= transport Std.Standard.Now ; chk_st_rec2 <= transport s_st_rec2_cnt after (1 us - Std.Standard.Now) ; s_st_rec2_cnt <= transport s_st_rec2_cnt + 1 ; -- end process CHG13 ; -- PGEN_CHKP_13 : process ( chk_st_rec2 ) begin if Std.Standard.Now > 0 ns then test_report ( "P13" , "Transport transactions completed entirely", chk_st_rec2 = 4 ) ; end if ; end process PGEN_CHKP_13 ; -- -- s_st_rec2 <= transport c_st_rec2_2 after 10 ns, c_st_rec2_1 after 20 ns when st_rec2_select = 1 else -- c_st_rec2_2 after 10 ns , c_st_rec2_1 after 20 ns , c_st_rec2_2 after 30 ns , c_st_rec2_1 after 40 ns when st_rec2_select = 2 else -- c_st_rec2_1 after 5 ns ; -- CHG14 : process ( s_st_rec3 ) variable correct : boolean ; begin case s_st_rec3_cnt is when 0 => null ; -- s_st_rec3 <= transport -- c_st_rec3_2 after 10 ns, -- c_st_rec3_1 after 20 ns ; -- when 1 => correct := s_st_rec3 = c_st_rec3_2 and (s_st_rec3_savt + 10 ns) = Std.Standard.Now ; -- when 2 => correct := correct and s_st_rec3 = c_st_rec3_1 and (s_st_rec3_savt + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00339.P14" , "Multi transport transactions occurred on " & "concurrent signal asg", correct ) ; -- st_rec3_select <= transport 2 ; -- s_st_rec3 <= transport -- c_st_rec3_2 after 10 ns , -- c_st_rec3_1 after 20 ns , -- c_st_rec3_2 after 30 ns , -- c_st_rec3_1 after 40 ns ; -- when 3 => correct := s_st_rec3 = c_st_rec3_2 and (s_st_rec3_savt + 10 ns) = Std.Standard.Now ; st_rec3_select <= transport 3 ; -- s_st_rec3 <= transport -- c_st_rec3_1 after 5 ns ; -- when 4 => correct := correct and s_st_rec3 = c_st_rec3_1 and (s_st_rec3_savt + 5 ns) = Std.Standard.Now ; test_report ( "ARCH00339" , "One transport transaction occurred on a " & "concurrent signal asg", correct ) ; test_report ( "ARCH00339" , "Old transactions were removed on a " & "concurrent signal asg", correct ) ; -- when others => -- No more transactions should have occurred test_report ( "ARCH00339" , "Old transactions were removed on a " & "concurrent signal asg", false ) ; -- end case ; -- s_st_rec3_savt <= transport Std.Standard.Now ; chk_st_rec3 <= transport s_st_rec3_cnt after (1 us - Std.Standard.Now) ; s_st_rec3_cnt <= transport s_st_rec3_cnt + 1 ; -- end process CHG14 ; -- PGEN_CHKP_14 : process ( chk_st_rec3 ) begin if Std.Standard.Now > 0 ns then test_report ( "P14" , "Transport transactions completed entirely", chk_st_rec3 = 4 ) ; end if ; end process PGEN_CHKP_14 ; -- -- s_st_rec3 <= transport c_st_rec3_2 after 10 ns, c_st_rec3_1 after 20 ns when st_rec3_select = 1 else -- c_st_rec3_2 after 10 ns , c_st_rec3_1 after 20 ns , c_st_rec3_2 after 30 ns , c_st_rec3_1 after 40 ns when st_rec3_select = 2 else -- c_st_rec3_1 after 5 ns ; -- CHG15 : process ( s_st_arr1 ) variable correct : boolean ; begin case s_st_arr1_cnt is when 0 => null ; -- s_st_arr1 <= transport -- c_st_arr1_2 after 10 ns, -- c_st_arr1_1 after 20 ns ; -- when 1 => correct := s_st_arr1 = c_st_arr1_2 and (s_st_arr1_savt + 10 ns) = Std.Standard.Now ; -- when 2 => correct := correct and s_st_arr1 = c_st_arr1_1 and (s_st_arr1_savt + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00339.P15" , "Multi transport transactions occurred on " & "concurrent signal asg", correct ) ; -- st_arr1_select <= transport 2 ; -- s_st_arr1 <= transport -- c_st_arr1_2 after 10 ns , -- c_st_arr1_1 after 20 ns , -- c_st_arr1_2 after 30 ns , -- c_st_arr1_1 after 40 ns ; -- when 3 => correct := s_st_arr1 = c_st_arr1_2 and (s_st_arr1_savt + 10 ns) = Std.Standard.Now ; st_arr1_select <= transport 3 ; -- s_st_arr1 <= transport -- c_st_arr1_1 after 5 ns ; -- when 4 => correct := correct and s_st_arr1 = c_st_arr1_1 and (s_st_arr1_savt + 5 ns) = Std.Standard.Now ; test_report ( "ARCH00339" , "One transport transaction occurred on a " & "concurrent signal asg", correct ) ; test_report ( "ARCH00339" , "Old transactions were removed on a " & "concurrent signal asg", correct ) ; -- when others => -- No more transactions should have occurred test_report ( "ARCH00339" , "Old transactions were removed on a " & "concurrent signal asg", false ) ; -- end case ; -- s_st_arr1_savt <= transport Std.Standard.Now ; chk_st_arr1 <= transport s_st_arr1_cnt after (1 us - Std.Standard.Now) ; s_st_arr1_cnt <= transport s_st_arr1_cnt + 1 ; -- end process CHG15 ; -- PGEN_CHKP_15 : process ( chk_st_arr1 ) begin if Std.Standard.Now > 0 ns then test_report ( "P15" , "Transport transactions completed entirely", chk_st_arr1 = 4 ) ; end if ; end process PGEN_CHKP_15 ; -- -- s_st_arr1 <= transport c_st_arr1_2 after 10 ns, c_st_arr1_1 after 20 ns when st_arr1_select = 1 else -- c_st_arr1_2 after 10 ns , c_st_arr1_1 after 20 ns , c_st_arr1_2 after 30 ns , c_st_arr1_1 after 40 ns when st_arr1_select = 2 else -- c_st_arr1_1 after 5 ns ; -- CHG16 : process ( s_st_arr2 ) variable correct : boolean ; begin case s_st_arr2_cnt is when 0 => null ; -- s_st_arr2 <= transport -- c_st_arr2_2 after 10 ns, -- c_st_arr2_1 after 20 ns ; -- when 1 => correct := s_st_arr2 = c_st_arr2_2 and (s_st_arr2_savt + 10 ns) = Std.Standard.Now ; -- when 2 => correct := correct and s_st_arr2 = c_st_arr2_1 and (s_st_arr2_savt + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00339.P16" , "Multi transport transactions occurred on " & "concurrent signal asg", correct ) ; -- st_arr2_select <= transport 2 ; -- s_st_arr2 <= transport -- c_st_arr2_2 after 10 ns , -- c_st_arr2_1 after 20 ns , -- c_st_arr2_2 after 30 ns , -- c_st_arr2_1 after 40 ns ; -- when 3 => correct := s_st_arr2 = c_st_arr2_2 and (s_st_arr2_savt + 10 ns) = Std.Standard.Now ; st_arr2_select <= transport 3 ; -- s_st_arr2 <= transport -- c_st_arr2_1 after 5 ns ; -- when 4 => correct := correct and s_st_arr2 = c_st_arr2_1 and (s_st_arr2_savt + 5 ns) = Std.Standard.Now ; test_report ( "ARCH00339" , "One transport transaction occurred on a " & "concurrent signal asg", correct ) ; test_report ( "ARCH00339" , "Old transactions were removed on a " & "concurrent signal asg", correct ) ; -- when others => -- No more transactions should have occurred test_report ( "ARCH00339" , "Old transactions were removed on a " & "concurrent signal asg", false ) ; -- end case ; -- s_st_arr2_savt <= transport Std.Standard.Now ; chk_st_arr2 <= transport s_st_arr2_cnt after (1 us - Std.Standard.Now) ; s_st_arr2_cnt <= transport s_st_arr2_cnt + 1 ; -- end process CHG16 ; -- PGEN_CHKP_16 : process ( chk_st_arr2 ) begin if Std.Standard.Now > 0 ns then test_report ( "P16" , "Transport transactions completed entirely", chk_st_arr2 = 4 ) ; end if ; end process PGEN_CHKP_16 ; -- -- s_st_arr2 <= transport c_st_arr2_2 after 10 ns, c_st_arr2_1 after 20 ns when st_arr2_select = 1 else -- c_st_arr2_2 after 10 ns , c_st_arr2_1 after 20 ns , c_st_arr2_2 after 30 ns , c_st_arr2_1 after 40 ns when st_arr2_select = 2 else -- c_st_arr2_1 after 5 ns ; -- CHG17 : process ( s_st_arr3 ) variable correct : boolean ; begin case s_st_arr3_cnt is when 0 => null ; -- s_st_arr3 <= transport -- c_st_arr3_2 after 10 ns, -- c_st_arr3_1 after 20 ns ; -- when 1 => correct := s_st_arr3 = c_st_arr3_2 and (s_st_arr3_savt + 10 ns) = Std.Standard.Now ; -- when 2 => correct := correct and s_st_arr3 = c_st_arr3_1 and (s_st_arr3_savt + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00339.P17" , "Multi transport transactions occurred on " & "concurrent signal asg", correct ) ; -- st_arr3_select <= transport 2 ; -- s_st_arr3 <= transport -- c_st_arr3_2 after 10 ns , -- c_st_arr3_1 after 20 ns , -- c_st_arr3_2 after 30 ns , -- c_st_arr3_1 after 40 ns ; -- when 3 => correct := s_st_arr3 = c_st_arr3_2 and (s_st_arr3_savt + 10 ns) = Std.Standard.Now ; st_arr3_select <= transport 3 ; -- s_st_arr3 <= transport -- c_st_arr3_1 after 5 ns ; -- when 4 => correct := correct and s_st_arr3 = c_st_arr3_1 and (s_st_arr3_savt + 5 ns) = Std.Standard.Now ; test_report ( "ARCH00339" , "One transport transaction occurred on a " & "concurrent signal asg", correct ) ; test_report ( "ARCH00339" , "Old transactions were removed on a " & "concurrent signal asg", correct ) ; -- when others => -- No more transactions should have occurred test_report ( "ARCH00339" , "Old transactions were removed on a " & "concurrent signal asg", false ) ; -- end case ; -- s_st_arr3_savt <= transport Std.Standard.Now ; chk_st_arr3 <= transport s_st_arr3_cnt after (1 us - Std.Standard.Now) ; s_st_arr3_cnt <= transport s_st_arr3_cnt + 1 ; -- end process CHG17 ; -- PGEN_CHKP_17 : process ( chk_st_arr3 ) begin if Std.Standard.Now > 0 ns then test_report ( "P17" , "Transport transactions completed entirely", chk_st_arr3 = 4 ) ; end if ; end process PGEN_CHKP_17 ; -- -- s_st_arr3 <= transport c_st_arr3_2 after 10 ns, c_st_arr3_1 after 20 ns when st_arr3_select = 1 else -- c_st_arr3_2 after 10 ns , c_st_arr3_1 after 20 ns , c_st_arr3_2 after 30 ns , c_st_arr3_1 after 40 ns when st_arr3_select = 2 else -- c_st_arr3_1 after 5 ns ; -- end ARCH00339 ; -- -- use WORK.STANDARD_TYPES.all ; entity ENT00339_Test_Bench is signal s_boolean : boolean := c_boolean_1 ; signal s_bit : bit := c_bit_1 ; signal s_severity_level : severity_level := c_severity_level_1 ; signal s_character : character := c_character_1 ; signal s_st_enum1 : st_enum1 := c_st_enum1_1 ; signal s_integer : integer := c_integer_1 ; signal s_st_int1 : st_int1 := c_st_int1_1 ; signal s_time : time := c_time_1 ; signal s_st_phys1 : st_phys1 := c_st_phys1_1 ; signal s_real : real := c_real_1 ; signal s_st_real1 : st_real1 := c_st_real1_1 ; signal s_st_rec1 : st_rec1 := c_st_rec1_1 ; signal s_st_rec2 : st_rec2 := c_st_rec2_1 ; signal s_st_rec3 : st_rec3 := c_st_rec3_1 ; signal s_st_arr1 : st_arr1 := c_st_arr1_1 ; signal s_st_arr2 : st_arr2 := c_st_arr2_1 ; signal s_st_arr3 : st_arr3 := c_st_arr3_1 ; -- end ENT00339_Test_Bench ; -- -- architecture ARCH00339_Test_Bench of ENT00339_Test_Bench is begin L1: block component UUT port ( s_boolean : inout boolean ; s_bit : inout bit ; s_severity_level : inout severity_level ; s_character : inout character ; s_st_enum1 : inout st_enum1 ; s_integer : inout integer ; s_st_int1 : inout st_int1 ; s_time : inout time ; s_st_phys1 : inout st_phys1 ; s_real : inout real ; s_st_real1 : inout st_real1 ; s_st_rec1 : inout st_rec1 ; s_st_rec2 : inout st_rec2 ; s_st_rec3 : inout st_rec3 ; s_st_arr1 : inout st_arr1 ; s_st_arr2 : inout st_arr2 ; s_st_arr3 : inout st_arr3 ) ; end component ; -- for CIS1 : UUT use entity WORK.ENT00339 ( ARCH00339 ) ; begin CIS1 : UUT port map ( s_boolean , s_bit , s_severity_level , s_character , s_st_enum1 , s_integer , s_st_int1 , s_time , s_st_phys1 , s_real , s_st_real1 , s_st_rec1 , s_st_rec2 , s_st_rec3 , s_st_arr1 , s_st_arr2 , s_st_arr3 ) ; end block L1 ; end ARCH00339_Test_Bench ;
gpl-3.0
bfeafe07c5d73b5662cd4c6c53eec262
0.488302
3.724165
false
false
false
false
grwlf/vsim
vhdl_ct/ct00426.vhd
1
5,421
------------------------------------------------------------------------------- -- -- Copyright (c) 1989 by Intermetrics, Inc. -- All rights reserved. -- ------------------------------------------------------------------------------- -- -- TEST NAME: -- -- CT00426 -- -- AUTHOR: -- -- A. Wilmot -- -- TEST OBJECTIVES: -- -- 7.2.3 (4) -- 7.2.3 (9) -- 7.2.3 (10) -- 7.2.3 (11) -- -- DESIGN UNIT ORDERING: -- -- PKG00426 -- ENT00426(ARCH00426) -- ENT00426_Test_Bench(ARCH00426_Test_Bench) -- -- REVISION HISTORY: -- -- 30-JUL-1987 - initial revision -- -- NOTES: -- -- self-checking -- package PKG00426 is type complex1 is record fl : integer ; f2 : integer ; end record ; type complex is array ( positive range <> ) of complex1 ; constant c_bit_vector_1 : bit_vector ( 1 downto 2 ) := (others => '0') ; constant c_bit_vector_2 : bit_vector := B"1100" ; constant c_string_1 : string := "" ; constant c_string_2 : string := "abc" ; constant c_complex1_1 : complex1 := (others => 5) ; constant c_complex1_2 : complex1 := (others => 7) ; constant c_complex_1 : complex ( 1 to 2 ) := (others => c_complex1_1) ; constant c_complex_2 : complex ( 2 downto 3 ) := (others => c_complex1_2) ; constant c_complex_3 : complex ( 1 to 2 ) := ( 1 to 2 => c_complex1_1, others => c_complex1_2 ) ; subtype st_bit_vector is bit_vector ( 0 to 3 ) ; subtype st_string is string ( 1 to 3 ) ; subtype st_complex is complex ( 1 to 2 ) ; end PKG00426 ; use WORK.PKG00426.all ; entity ENT00426 is generic ( i_bit_vector_1 : bit_vector ( 1 downto 2 ) := (others => '0') ; i_bit_vector_2 : bit_vector := B"1100" ; i_string_1 : string := "" ; i_string_2 : string := "abc" ; i_complex_1 : complex := c_complex_1 ; i_complex_2 : complex := c_complex_2 ) ; port ( locally_static_correct : out boolean ; globally_static_correct : out boolean ; dynamic_correct : out boolean ) ; end ENT00426 ; architecture ARCH00426 of ENT00426 is begin process variable bool : boolean := true ; variable cons_correct, gen_correct, dyn_correct : boolean := true ; -- variable v_bit_vector_1 : bit_vector ( 1 downto 4 ) := c_bit_vector_1 ; variable v_bit_vector_2 : bit_vector ( 0 to 3 ) := c_bit_vector_2 ; variable v_string_1 : string ( 3 to 1 ) := c_string_1 ; variable v_string_2 : string ( 1 to 3 ):= c_string_2 ; variable v_complex_1 : complex ( 1 to 2 ) := c_complex_1 ; variable v_complex_2 : complex ( 1 downto 2 ) := c_complex_2 ; constant c2_bit_vector_2 : bit_vector ( 1 to 4 ) := st_bit_vector' (i_bit_vector_2 & i_bit_vector_1) ; constant c2_bit_vector_3 : bit_vector ( 1 to 4 ) := st_bit_vector' (i_bit_vector_1 & i_bit_vector_2) ; constant c2_string_2 : string ( 1 to 3 ) := st_string' (i_string_2 & i_string_1) ; constant c2_string_3 : string ( 1 to 3 ) := st_string' (i_string_1 & i_string_2) ; constant c2_complex_1 : complex ( 1 to 2 ) := st_complex' (i_complex_1 & i_complex_2) ; constant c2_complex_2 : complex ( 1 to 2 ) := st_complex' (i_complex_2 & i_complex_1) ; begin gen_correct := c2_bit_vector_2 = B"1100" and c2_bit_vector_3 = B"1100" and c2_string_2 = "abc" and c2_string_3 = "abc" and c2_complex_1 = c_complex_3 and c2_complex_2 = c_complex_3 ; locally_static_correct <= cons_correct ; globally_static_correct <= gen_correct ; dyn_correct := st_bit_vector' (v_bit_vector_2 & i_bit_vector_1) = B"1100" and st_bit_vector' (v_bit_vector_1 & v_bit_vector_2) = B"1100" and st_string' (v_string_2 & i_string_1) = "abc" and st_string' (v_string_1 & v_string_2) = "abc" and st_complex' (v_complex_2 & v_complex_1) = c_complex_3 and st_complex' (v_complex_1 & v_complex_2) = c_complex_3 ; dynamic_correct <= dyn_correct ; wait ; end process ; end ARCH00426 ; use WORK.STANDARD_TYPES.all ; entity ENT00426_Test_Bench is end ENT00426_Test_Bench ; architecture ARCH00426_Test_Bench of ENT00426_Test_Bench is begin L1: block signal locally_static_correct, globally_static_correct, dynamic_correct : boolean := false ; component UUT port ( locally_static_correct : out boolean := false ; globally_static_correct : out boolean := false ; dynamic_correct : out boolean := false ) ; end component ; for CIS1 : UUT use entity WORK.ENT00426 ( ARCH00426 ) ; begin CIS1 : UUT port map ( locally_static_correct, globally_static_correct, dynamic_correct ) ; process ( locally_static_correct, globally_static_correct, dynamic_correct ) begin if locally_static_correct and globally_static_correct and dynamic_correct then test_report ( "ARCH00426" , "& correctly predefined for array operands with null" & " array operands" , true ) ; end if ; end process ; end block L1 ; end ARCH00426_Test_Bench ;
gpl-3.0
204d72c954a6f34e30f8540113945755
0.541966
3.392365
false
true
false
false
jairov4/accel-oil
solution_spartan3/syn/vhdl/bitset_next.vhd
2
25,988
-- ============================================================== -- RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC -- Version: 2013.4 -- Copyright (C) 2013 Xilinx Inc. All rights reserved. -- -- =========================================================== library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; entity bitset_next is port ( ap_clk : IN STD_LOGIC; ap_rst : IN STD_LOGIC; p_read : IN STD_LOGIC_VECTOR (31 downto 0); r_bit : IN STD_LOGIC_VECTOR (7 downto 0); r_bucket_index : IN STD_LOGIC_VECTOR (7 downto 0); r_bucket : IN STD_LOGIC_VECTOR (31 downto 0); ap_return_0 : OUT STD_LOGIC_VECTOR (7 downto 0); ap_return_1 : OUT STD_LOGIC_VECTOR (7 downto 0); ap_return_2 : OUT STD_LOGIC_VECTOR (31 downto 0); ap_return_3 : OUT STD_LOGIC_VECTOR (0 downto 0); ap_ce : IN STD_LOGIC ); end; architecture behav of bitset_next is constant ap_const_logic_1 : STD_LOGIC := '1'; constant ap_const_logic_0 : STD_LOGIC := '0'; constant ap_true : BOOLEAN := true; constant ap_const_lv1_0 : STD_LOGIC_VECTOR (0 downto 0) := "0"; constant ap_const_lv32_0 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000000"; constant ap_const_lv1_1 : STD_LOGIC_VECTOR (0 downto 0) := "1"; constant ap_const_lv2_1 : STD_LOGIC_VECTOR (1 downto 0) := "01"; constant ap_const_lv2_2 : STD_LOGIC_VECTOR (1 downto 0) := "10"; constant ap_const_lv32_FFFFFFFF : STD_LOGIC_VECTOR (31 downto 0) := "11111111111111111111111111111111"; constant ap_const_lv2_0 : STD_LOGIC_VECTOR (1 downto 0) := "00"; constant ap_const_lv32_1 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000001"; constant ap_const_lv8_1 : STD_LOGIC_VECTOR (7 downto 0) := "00000001"; signal grp_p_bsf32_hw_fu_118_ap_return : STD_LOGIC_VECTOR (4 downto 0); signal reg_123 : STD_LOGIC_VECTOR (4 downto 0); signal tmp_3_reg_232 : STD_LOGIC_VECTOR (0 downto 0); signal tmp_24_1_reg_236 : STD_LOGIC_VECTOR (0 downto 0); signal tmp_26_1_reg_240 : STD_LOGIC_VECTOR (0 downto 0); signal r_bucket_read_reg_194 : STD_LOGIC_VECTOR (31 downto 0); signal ap_reg_ppstg_r_bucket_read_reg_194_pp0_it1 : STD_LOGIC_VECTOR (31 downto 0); signal ap_reg_ppstg_r_bucket_read_reg_194_pp0_it2 : STD_LOGIC_VECTOR (31 downto 0); signal ap_reg_ppstg_r_bucket_read_reg_194_pp0_it3 : STD_LOGIC_VECTOR (31 downto 0); signal ap_reg_ppstg_r_bucket_read_reg_194_pp0_it4 : STD_LOGIC_VECTOR (31 downto 0); signal ap_reg_ppstg_r_bucket_read_reg_194_pp0_it5 : STD_LOGIC_VECTOR (31 downto 0); signal ap_reg_ppstg_r_bucket_read_reg_194_pp0_it6 : STD_LOGIC_VECTOR (31 downto 0); signal ap_reg_ppstg_r_bucket_read_reg_194_pp0_it7 : STD_LOGIC_VECTOR (31 downto 0); signal r_bit_read_reg_200 : STD_LOGIC_VECTOR (7 downto 0); signal ap_reg_ppstg_r_bit_read_reg_200_pp0_it1 : STD_LOGIC_VECTOR (7 downto 0); signal ap_reg_ppstg_r_bit_read_reg_200_pp0_it2 : STD_LOGIC_VECTOR (7 downto 0); signal ap_reg_ppstg_r_bit_read_reg_200_pp0_it3 : STD_LOGIC_VECTOR (7 downto 0); signal ap_reg_ppstg_r_bit_read_reg_200_pp0_it4 : STD_LOGIC_VECTOR (7 downto 0); signal ap_reg_ppstg_r_bit_read_reg_200_pp0_it5 : STD_LOGIC_VECTOR (7 downto 0); signal ap_reg_ppstg_r_bit_read_reg_200_pp0_it6 : STD_LOGIC_VECTOR (7 downto 0); signal ap_reg_ppstg_r_bit_read_reg_200_pp0_it7 : STD_LOGIC_VECTOR (7 downto 0); signal ap_reg_ppstg_r_bit_read_reg_200_pp0_it8 : STD_LOGIC_VECTOR (7 downto 0); signal ap_reg_ppstg_r_bit_read_reg_200_pp0_it9 : STD_LOGIC_VECTOR (7 downto 0); signal p_read_1_reg_206 : STD_LOGIC_VECTOR (31 downto 0); signal ap_reg_ppstg_p_read_1_reg_206_pp0_it1 : STD_LOGIC_VECTOR (31 downto 0); signal ap_reg_ppstg_p_read_1_reg_206_pp0_it2 : STD_LOGIC_VECTOR (31 downto 0); signal ap_reg_ppstg_p_read_1_reg_206_pp0_it3 : STD_LOGIC_VECTOR (31 downto 0); signal ap_reg_ppstg_p_read_1_reg_206_pp0_it4 : STD_LOGIC_VECTOR (31 downto 0); signal ap_reg_ppstg_p_read_1_reg_206_pp0_it5 : STD_LOGIC_VECTOR (31 downto 0); signal ap_reg_ppstg_p_read_1_reg_206_pp0_it6 : STD_LOGIC_VECTOR (31 downto 0); signal ap_reg_ppstg_p_read_1_reg_206_pp0_it7 : STD_LOGIC_VECTOR (31 downto 0); signal ap_reg_ppstg_p_read_1_reg_206_pp0_it8 : STD_LOGIC_VECTOR (31 downto 0); signal ap_reg_ppstg_p_read_1_reg_206_pp0_it9 : STD_LOGIC_VECTOR (31 downto 0); signal ap_reg_ppstg_p_read_1_reg_206_pp0_it10 : STD_LOGIC_VECTOR (31 downto 0); signal tmp_fu_127_p1 : STD_LOGIC_VECTOR (1 downto 0); signal tmp_reg_214 : STD_LOGIC_VECTOR (1 downto 0); signal ap_reg_ppstg_tmp_reg_214_pp0_it1 : STD_LOGIC_VECTOR (1 downto 0); signal ap_reg_ppstg_tmp_reg_214_pp0_it2 : STD_LOGIC_VECTOR (1 downto 0); signal ap_reg_ppstg_tmp_reg_214_pp0_it3 : STD_LOGIC_VECTOR (1 downto 0); signal ap_reg_ppstg_tmp_reg_214_pp0_it4 : STD_LOGIC_VECTOR (1 downto 0); signal ap_reg_ppstg_tmp_reg_214_pp0_it5 : STD_LOGIC_VECTOR (1 downto 0); signal ap_reg_ppstg_tmp_reg_214_pp0_it6 : STD_LOGIC_VECTOR (1 downto 0); signal ap_reg_ppstg_tmp_reg_214_pp0_it7 : STD_LOGIC_VECTOR (1 downto 0); signal ap_reg_ppstg_tmp_reg_214_pp0_it8 : STD_LOGIC_VECTOR (1 downto 0); signal ap_reg_ppstg_tmp_reg_214_pp0_it9 : STD_LOGIC_VECTOR (1 downto 0); signal ap_reg_ppstg_tmp_reg_214_pp0_it10 : STD_LOGIC_VECTOR (1 downto 0); signal grp_fu_131_p2 : STD_LOGIC_VECTOR (31 downto 0); signal tmp_1_reg_220 : STD_LOGIC_VECTOR (31 downto 0); signal bus_assign_fu_137_p2 : STD_LOGIC_VECTOR (31 downto 0); signal bus_assign_reg_225 : STD_LOGIC_VECTOR (31 downto 0); signal ap_reg_ppstg_bus_assign_reg_225_pp0_it9 : STD_LOGIC_VECTOR (31 downto 0); signal ap_reg_ppstg_bus_assign_reg_225_pp0_it10 : STD_LOGIC_VECTOR (31 downto 0); signal tmp_3_fu_141_p2 : STD_LOGIC_VECTOR (0 downto 0); signal ap_reg_ppstg_tmp_3_reg_232_pp0_it10 : STD_LOGIC_VECTOR (0 downto 0); signal tmp_24_1_fu_146_p2 : STD_LOGIC_VECTOR (0 downto 0); signal ap_reg_ppstg_tmp_24_1_reg_236_pp0_it10 : STD_LOGIC_VECTOR (0 downto 0); signal tmp_26_1_fu_151_p2 : STD_LOGIC_VECTOR (0 downto 0); signal ap_reg_ppstg_tmp_26_1_reg_240_pp0_it10 : STD_LOGIC_VECTOR (0 downto 0); signal grp_p_bsf32_hw_fu_118_bus_r : STD_LOGIC_VECTOR (31 downto 0); signal grp_p_bsf32_hw_fu_118_ap_ce : STD_LOGIC; signal ap_reg_phiprechg_agg_result_bucket_write_assign_reg_54pp0_it11 : STD_LOGIC_VECTOR (31 downto 0); signal agg_result_bucket_write_assign_phi_fu_58_p8 : STD_LOGIC_VECTOR (31 downto 0); signal ap_reg_phiprechg_agg_result_bucket_write_assign_reg_54pp0_it10 : STD_LOGIC_VECTOR (31 downto 0); signal ap_reg_phiprechg_agg_result_end_write_assign_reg_69pp0_it11 : STD_LOGIC_VECTOR (0 downto 0); signal agg_result_end_write_assign_phi_fu_73_p8 : STD_LOGIC_VECTOR (0 downto 0); signal ap_reg_phiprechg_agg_result_end_write_assign_reg_69pp0_it10 : STD_LOGIC_VECTOR (0 downto 0); signal ap_reg_phiprechg_agg_result_bucket_index_write_assign_reg_87pp0_it11 : STD_LOGIC_VECTOR (1 downto 0); signal agg_result_bucket_index_write_assign_phi_fu_91_p8 : STD_LOGIC_VECTOR (1 downto 0); signal ap_reg_phiprechg_agg_result_bucket_index_write_assign_reg_87pp0_it10 : STD_LOGIC_VECTOR (1 downto 0); signal agg_result_bit_write_assign_trunc3_ext_fu_161_p1 : STD_LOGIC_VECTOR (7 downto 0); signal ap_reg_phiprechg_agg_result_bit_write_assign_reg_104pp0_it11 : STD_LOGIC_VECTOR (7 downto 0); signal agg_result_bit_write_assign_phi_fu_107_p8 : STD_LOGIC_VECTOR (7 downto 0); signal agg_result_bit_write_assign_trunc_ext_fu_156_p1 : STD_LOGIC_VECTOR (7 downto 0); signal ap_reg_phiprechg_agg_result_bit_write_assign_reg_104pp0_it10 : STD_LOGIC_VECTOR (7 downto 0); signal grp_fu_131_p0 : STD_LOGIC_VECTOR (31 downto 0); signal grp_fu_131_p1 : STD_LOGIC_VECTOR (31 downto 0); signal agg_result_bucket_index_write_assign_cast_fu_166_p1 : STD_LOGIC_VECTOR (7 downto 0); signal grp_fu_131_ce : STD_LOGIC; signal ap_sig_bdd_139 : BOOLEAN; signal ap_sig_bdd_143 : BOOLEAN; component p_bsf32_hw IS port ( ap_clk : IN STD_LOGIC; ap_rst : IN STD_LOGIC; bus_r : IN STD_LOGIC_VECTOR (31 downto 0); ap_return : OUT STD_LOGIC_VECTOR (4 downto 0); ap_ce : IN STD_LOGIC ); end component; component nfa_accept_samples_generic_hw_add_32ns_32s_32_8 IS generic ( ID : INTEGER; NUM_STAGE : INTEGER; din0_WIDTH : INTEGER; din1_WIDTH : INTEGER; dout_WIDTH : INTEGER ); port ( clk : IN STD_LOGIC; reset : IN STD_LOGIC; din0 : IN STD_LOGIC_VECTOR (31 downto 0); din1 : IN STD_LOGIC_VECTOR (31 downto 0); ce : IN STD_LOGIC; dout : OUT STD_LOGIC_VECTOR (31 downto 0) ); end component; begin grp_p_bsf32_hw_fu_118 : component p_bsf32_hw port map ( ap_clk => ap_clk, ap_rst => ap_rst, bus_r => grp_p_bsf32_hw_fu_118_bus_r, ap_return => grp_p_bsf32_hw_fu_118_ap_return, ap_ce => grp_p_bsf32_hw_fu_118_ap_ce); nfa_accept_samples_generic_hw_add_32ns_32s_32_8_U11 : component nfa_accept_samples_generic_hw_add_32ns_32s_32_8 generic map ( ID => 11, NUM_STAGE => 8, din0_WIDTH => 32, din1_WIDTH => 32, dout_WIDTH => 32) port map ( clk => ap_clk, reset => ap_rst, din0 => grp_fu_131_p0, din1 => grp_fu_131_p1, ce => grp_fu_131_ce, dout => grp_fu_131_p2); -- ap_reg_phiprechg_agg_result_bit_write_assign_reg_104pp0_it11 assign process. -- ap_reg_phiprechg_agg_result_bit_write_assign_reg_104pp0_it11_assign_proc : process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if ((((ap_const_logic_1 = ap_ce) and not((tmp_3_reg_232 = ap_const_lv1_0)) and (ap_const_lv1_0 = tmp_24_1_reg_236)) or ((ap_const_logic_1 = ap_ce) and not((tmp_3_reg_232 = ap_const_lv1_0)) and not((ap_const_lv1_0 = tmp_24_1_reg_236)) and not((ap_const_lv1_0 = tmp_26_1_reg_240))))) then ap_reg_phiprechg_agg_result_bit_write_assign_reg_104pp0_it11 <= ap_reg_ppstg_r_bit_read_reg_200_pp0_it9; elsif ((ap_const_logic_1 = ap_ce)) then ap_reg_phiprechg_agg_result_bit_write_assign_reg_104pp0_it11 <= ap_reg_phiprechg_agg_result_bit_write_assign_reg_104pp0_it10; end if; end if; end process; -- ap_reg_phiprechg_agg_result_bucket_index_write_assign_reg_87pp0_it11 assign process. -- ap_reg_phiprechg_agg_result_bucket_index_write_assign_reg_87pp0_it11_assign_proc : process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if ((((ap_const_logic_1 = ap_ce) and not((tmp_3_reg_232 = ap_const_lv1_0)) and (ap_const_lv1_0 = tmp_24_1_reg_236)) or ((ap_const_logic_1 = ap_ce) and not((tmp_3_reg_232 = ap_const_lv1_0)) and not((ap_const_lv1_0 = tmp_24_1_reg_236)) and not((ap_const_lv1_0 = tmp_26_1_reg_240))))) then ap_reg_phiprechg_agg_result_bucket_index_write_assign_reg_87pp0_it11 <= ap_const_lv2_2; elsif ((ap_const_logic_1 = ap_ce)) then ap_reg_phiprechg_agg_result_bucket_index_write_assign_reg_87pp0_it11 <= ap_reg_phiprechg_agg_result_bucket_index_write_assign_reg_87pp0_it10; end if; end if; end process; -- ap_reg_phiprechg_agg_result_bucket_write_assign_reg_54pp0_it11 assign process. -- ap_reg_phiprechg_agg_result_bucket_write_assign_reg_54pp0_it11_assign_proc : process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if ((ap_const_logic_1 = ap_ce)) then if (ap_sig_bdd_143) then ap_reg_phiprechg_agg_result_bucket_write_assign_reg_54pp0_it11 <= ap_reg_ppstg_p_read_1_reg_206_pp0_it9; elsif (ap_sig_bdd_139) then ap_reg_phiprechg_agg_result_bucket_write_assign_reg_54pp0_it11 <= ap_const_lv32_0; elsif ((ap_true = ap_true)) then ap_reg_phiprechg_agg_result_bucket_write_assign_reg_54pp0_it11 <= ap_reg_phiprechg_agg_result_bucket_write_assign_reg_54pp0_it10; end if; end if; end if; end process; -- ap_reg_phiprechg_agg_result_end_write_assign_reg_69pp0_it11 assign process. -- ap_reg_phiprechg_agg_result_end_write_assign_reg_69pp0_it11_assign_proc : process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then end if; end process; -- assign process. -- process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if ((ap_const_logic_1 = ap_ce)) then ap_reg_ppstg_bus_assign_reg_225_pp0_it10 <= ap_reg_ppstg_bus_assign_reg_225_pp0_it9; ap_reg_ppstg_bus_assign_reg_225_pp0_it9 <= bus_assign_reg_225; ap_reg_ppstg_p_read_1_reg_206_pp0_it1 <= p_read_1_reg_206; ap_reg_ppstg_p_read_1_reg_206_pp0_it10 <= ap_reg_ppstg_p_read_1_reg_206_pp0_it9; ap_reg_ppstg_p_read_1_reg_206_pp0_it2 <= ap_reg_ppstg_p_read_1_reg_206_pp0_it1; ap_reg_ppstg_p_read_1_reg_206_pp0_it3 <= ap_reg_ppstg_p_read_1_reg_206_pp0_it2; ap_reg_ppstg_p_read_1_reg_206_pp0_it4 <= ap_reg_ppstg_p_read_1_reg_206_pp0_it3; ap_reg_ppstg_p_read_1_reg_206_pp0_it5 <= ap_reg_ppstg_p_read_1_reg_206_pp0_it4; ap_reg_ppstg_p_read_1_reg_206_pp0_it6 <= ap_reg_ppstg_p_read_1_reg_206_pp0_it5; ap_reg_ppstg_p_read_1_reg_206_pp0_it7 <= ap_reg_ppstg_p_read_1_reg_206_pp0_it6; ap_reg_ppstg_p_read_1_reg_206_pp0_it8 <= ap_reg_ppstg_p_read_1_reg_206_pp0_it7; ap_reg_ppstg_p_read_1_reg_206_pp0_it9 <= ap_reg_ppstg_p_read_1_reg_206_pp0_it8; ap_reg_ppstg_r_bit_read_reg_200_pp0_it1 <= r_bit_read_reg_200; ap_reg_ppstg_r_bit_read_reg_200_pp0_it2 <= ap_reg_ppstg_r_bit_read_reg_200_pp0_it1; ap_reg_ppstg_r_bit_read_reg_200_pp0_it3 <= ap_reg_ppstg_r_bit_read_reg_200_pp0_it2; ap_reg_ppstg_r_bit_read_reg_200_pp0_it4 <= ap_reg_ppstg_r_bit_read_reg_200_pp0_it3; ap_reg_ppstg_r_bit_read_reg_200_pp0_it5 <= ap_reg_ppstg_r_bit_read_reg_200_pp0_it4; ap_reg_ppstg_r_bit_read_reg_200_pp0_it6 <= ap_reg_ppstg_r_bit_read_reg_200_pp0_it5; ap_reg_ppstg_r_bit_read_reg_200_pp0_it7 <= ap_reg_ppstg_r_bit_read_reg_200_pp0_it6; ap_reg_ppstg_r_bit_read_reg_200_pp0_it8 <= ap_reg_ppstg_r_bit_read_reg_200_pp0_it7; ap_reg_ppstg_r_bit_read_reg_200_pp0_it9 <= ap_reg_ppstg_r_bit_read_reg_200_pp0_it8; ap_reg_ppstg_r_bucket_read_reg_194_pp0_it1 <= r_bucket_read_reg_194; ap_reg_ppstg_r_bucket_read_reg_194_pp0_it2 <= ap_reg_ppstg_r_bucket_read_reg_194_pp0_it1; ap_reg_ppstg_r_bucket_read_reg_194_pp0_it3 <= ap_reg_ppstg_r_bucket_read_reg_194_pp0_it2; ap_reg_ppstg_r_bucket_read_reg_194_pp0_it4 <= ap_reg_ppstg_r_bucket_read_reg_194_pp0_it3; ap_reg_ppstg_r_bucket_read_reg_194_pp0_it5 <= ap_reg_ppstg_r_bucket_read_reg_194_pp0_it4; ap_reg_ppstg_r_bucket_read_reg_194_pp0_it6 <= ap_reg_ppstg_r_bucket_read_reg_194_pp0_it5; ap_reg_ppstg_r_bucket_read_reg_194_pp0_it7 <= ap_reg_ppstg_r_bucket_read_reg_194_pp0_it6; ap_reg_ppstg_tmp_24_1_reg_236_pp0_it10 <= tmp_24_1_reg_236; ap_reg_ppstg_tmp_26_1_reg_240_pp0_it10 <= tmp_26_1_reg_240; ap_reg_ppstg_tmp_3_reg_232_pp0_it10 <= tmp_3_reg_232; ap_reg_ppstg_tmp_reg_214_pp0_it1 <= tmp_reg_214; ap_reg_ppstg_tmp_reg_214_pp0_it10 <= ap_reg_ppstg_tmp_reg_214_pp0_it9; ap_reg_ppstg_tmp_reg_214_pp0_it2 <= ap_reg_ppstg_tmp_reg_214_pp0_it1; ap_reg_ppstg_tmp_reg_214_pp0_it3 <= ap_reg_ppstg_tmp_reg_214_pp0_it2; ap_reg_ppstg_tmp_reg_214_pp0_it4 <= ap_reg_ppstg_tmp_reg_214_pp0_it3; ap_reg_ppstg_tmp_reg_214_pp0_it5 <= ap_reg_ppstg_tmp_reg_214_pp0_it4; ap_reg_ppstg_tmp_reg_214_pp0_it6 <= ap_reg_ppstg_tmp_reg_214_pp0_it5; ap_reg_ppstg_tmp_reg_214_pp0_it7 <= ap_reg_ppstg_tmp_reg_214_pp0_it6; ap_reg_ppstg_tmp_reg_214_pp0_it8 <= ap_reg_ppstg_tmp_reg_214_pp0_it7; ap_reg_ppstg_tmp_reg_214_pp0_it9 <= ap_reg_ppstg_tmp_reg_214_pp0_it8; bus_assign_reg_225 <= bus_assign_fu_137_p2; p_read_1_reg_206 <= p_read; r_bit_read_reg_200 <= r_bit; r_bucket_read_reg_194 <= r_bucket; tmp_1_reg_220 <= grp_fu_131_p2; tmp_3_reg_232 <= tmp_3_fu_141_p2; tmp_reg_214 <= tmp_fu_127_p1; end if; end if; end process; -- assign process. -- process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if ((((ap_const_logic_1 = ap_ce) and (tmp_3_reg_232 = ap_const_lv1_0)) or ((ap_const_logic_1 = ap_ce) and not((tmp_3_reg_232 = ap_const_lv1_0)) and not((ap_const_lv1_0 = tmp_24_1_reg_236)) and (ap_const_lv1_0 = tmp_26_1_reg_240)))) then reg_123 <= grp_p_bsf32_hw_fu_118_ap_return; end if; end if; end process; -- assign process. -- process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((ap_const_logic_1 = ap_ce) and not((ap_const_lv1_0 = tmp_3_fu_141_p2)))) then tmp_24_1_reg_236 <= tmp_24_1_fu_146_p2; end if; end if; end process; -- assign process. -- process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((ap_const_logic_1 = ap_ce) and not((ap_const_lv1_0 = tmp_3_fu_141_p2)) and not((ap_const_lv1_0 = tmp_24_1_fu_146_p2)))) then tmp_26_1_reg_240 <= tmp_26_1_fu_151_p2; end if; end if; end process; ap_reg_phiprechg_agg_result_end_write_assign_reg_69pp0_it11(0) <= '1'; -- agg_result_bit_write_assign_phi_fu_107_p8 assign process. -- agg_result_bit_write_assign_phi_fu_107_p8_assign_proc : process(ap_reg_ppstg_tmp_3_reg_232_pp0_it10, ap_reg_ppstg_tmp_24_1_reg_236_pp0_it10, ap_reg_ppstg_tmp_26_1_reg_240_pp0_it10, agg_result_bit_write_assign_trunc3_ext_fu_161_p1, ap_reg_phiprechg_agg_result_bit_write_assign_reg_104pp0_it11, agg_result_bit_write_assign_trunc_ext_fu_156_p1) begin if ((ap_const_lv1_0 = ap_reg_ppstg_tmp_3_reg_232_pp0_it10)) then agg_result_bit_write_assign_phi_fu_107_p8 <= agg_result_bit_write_assign_trunc_ext_fu_156_p1; elsif ((not((ap_const_lv1_0 = ap_reg_ppstg_tmp_3_reg_232_pp0_it10)) and not((ap_const_lv1_0 = ap_reg_ppstg_tmp_24_1_reg_236_pp0_it10)) and (ap_const_lv1_0 = ap_reg_ppstg_tmp_26_1_reg_240_pp0_it10))) then agg_result_bit_write_assign_phi_fu_107_p8 <= agg_result_bit_write_assign_trunc3_ext_fu_161_p1; else agg_result_bit_write_assign_phi_fu_107_p8 <= ap_reg_phiprechg_agg_result_bit_write_assign_reg_104pp0_it11; end if; end process; agg_result_bit_write_assign_trunc3_ext_fu_161_p1 <= std_logic_vector(resize(unsigned(reg_123),8)); agg_result_bit_write_assign_trunc_ext_fu_156_p1 <= std_logic_vector(resize(unsigned(reg_123),8)); agg_result_bucket_index_write_assign_cast_fu_166_p1 <= std_logic_vector(resize(unsigned(agg_result_bucket_index_write_assign_phi_fu_91_p8),8)); -- agg_result_bucket_index_write_assign_phi_fu_91_p8 assign process. -- agg_result_bucket_index_write_assign_phi_fu_91_p8_assign_proc : process(ap_reg_ppstg_tmp_reg_214_pp0_it10, ap_reg_ppstg_tmp_3_reg_232_pp0_it10, ap_reg_ppstg_tmp_24_1_reg_236_pp0_it10, ap_reg_ppstg_tmp_26_1_reg_240_pp0_it10, ap_reg_phiprechg_agg_result_bucket_index_write_assign_reg_87pp0_it11) begin if ((ap_const_lv1_0 = ap_reg_ppstg_tmp_3_reg_232_pp0_it10)) then agg_result_bucket_index_write_assign_phi_fu_91_p8 <= ap_reg_ppstg_tmp_reg_214_pp0_it10; elsif ((not((ap_const_lv1_0 = ap_reg_ppstg_tmp_3_reg_232_pp0_it10)) and not((ap_const_lv1_0 = ap_reg_ppstg_tmp_24_1_reg_236_pp0_it10)) and (ap_const_lv1_0 = ap_reg_ppstg_tmp_26_1_reg_240_pp0_it10))) then agg_result_bucket_index_write_assign_phi_fu_91_p8 <= ap_const_lv2_1; else agg_result_bucket_index_write_assign_phi_fu_91_p8 <= ap_reg_phiprechg_agg_result_bucket_index_write_assign_reg_87pp0_it11; end if; end process; -- agg_result_bucket_write_assign_phi_fu_58_p8 assign process. -- agg_result_bucket_write_assign_phi_fu_58_p8_assign_proc : process(ap_reg_ppstg_p_read_1_reg_206_pp0_it10, ap_reg_ppstg_bus_assign_reg_225_pp0_it10, ap_reg_ppstg_tmp_3_reg_232_pp0_it10, ap_reg_ppstg_tmp_24_1_reg_236_pp0_it10, ap_reg_ppstg_tmp_26_1_reg_240_pp0_it10, ap_reg_phiprechg_agg_result_bucket_write_assign_reg_54pp0_it11) begin if ((ap_const_lv1_0 = ap_reg_ppstg_tmp_3_reg_232_pp0_it10)) then agg_result_bucket_write_assign_phi_fu_58_p8 <= ap_reg_ppstg_bus_assign_reg_225_pp0_it10; elsif ((not((ap_const_lv1_0 = ap_reg_ppstg_tmp_3_reg_232_pp0_it10)) and not((ap_const_lv1_0 = ap_reg_ppstg_tmp_24_1_reg_236_pp0_it10)) and (ap_const_lv1_0 = ap_reg_ppstg_tmp_26_1_reg_240_pp0_it10))) then agg_result_bucket_write_assign_phi_fu_58_p8 <= ap_reg_ppstg_p_read_1_reg_206_pp0_it10; else agg_result_bucket_write_assign_phi_fu_58_p8 <= ap_reg_phiprechg_agg_result_bucket_write_assign_reg_54pp0_it11; end if; end process; -- agg_result_end_write_assign_phi_fu_73_p8 assign process. -- agg_result_end_write_assign_phi_fu_73_p8_assign_proc : process(ap_reg_ppstg_tmp_3_reg_232_pp0_it10, ap_reg_ppstg_tmp_24_1_reg_236_pp0_it10, ap_reg_ppstg_tmp_26_1_reg_240_pp0_it10, ap_reg_phiprechg_agg_result_end_write_assign_reg_69pp0_it11) begin if (((ap_const_lv1_0 = ap_reg_ppstg_tmp_3_reg_232_pp0_it10) or (not((ap_const_lv1_0 = ap_reg_ppstg_tmp_3_reg_232_pp0_it10)) and not((ap_const_lv1_0 = ap_reg_ppstg_tmp_24_1_reg_236_pp0_it10)) and (ap_const_lv1_0 = ap_reg_ppstg_tmp_26_1_reg_240_pp0_it10)))) then agg_result_end_write_assign_phi_fu_73_p8 <= ap_const_lv1_0; else agg_result_end_write_assign_phi_fu_73_p8 <= ap_reg_phiprechg_agg_result_end_write_assign_reg_69pp0_it11; end if; end process; ap_reg_phiprechg_agg_result_bit_write_assign_reg_104pp0_it10 <= ap_const_lv8_1; ap_reg_phiprechg_agg_result_bucket_index_write_assign_reg_87pp0_it10 <= ap_const_lv2_1; ap_reg_phiprechg_agg_result_bucket_write_assign_reg_54pp0_it10 <= ap_const_lv32_1; ap_reg_phiprechg_agg_result_end_write_assign_reg_69pp0_it10 <= ap_const_lv1_1; ap_return_0 <= agg_result_bit_write_assign_phi_fu_107_p8; ap_return_1 <= agg_result_bucket_index_write_assign_cast_fu_166_p1; ap_return_2 <= agg_result_bucket_write_assign_phi_fu_58_p8; ap_return_3 <= agg_result_end_write_assign_phi_fu_73_p8; -- ap_sig_bdd_139 assign process. -- ap_sig_bdd_139_assign_proc : process(tmp_3_reg_232, tmp_24_1_reg_236) begin ap_sig_bdd_139 <= (not((tmp_3_reg_232 = ap_const_lv1_0)) and (ap_const_lv1_0 = tmp_24_1_reg_236)); end process; -- ap_sig_bdd_143 assign process. -- ap_sig_bdd_143_assign_proc : process(tmp_3_reg_232, tmp_24_1_reg_236, tmp_26_1_reg_240) begin ap_sig_bdd_143 <= (not((tmp_3_reg_232 = ap_const_lv1_0)) and not((ap_const_lv1_0 = tmp_24_1_reg_236)) and not((ap_const_lv1_0 = tmp_26_1_reg_240))); end process; bus_assign_fu_137_p2 <= (tmp_1_reg_220 and ap_reg_ppstg_r_bucket_read_reg_194_pp0_it7); -- grp_fu_131_ce assign process. -- grp_fu_131_ce_assign_proc : process(ap_ce) begin if (not((ap_const_logic_1 = ap_ce))) then grp_fu_131_ce <= ap_const_logic_0; else grp_fu_131_ce <= ap_const_logic_1; end if; end process; grp_fu_131_p0 <= r_bucket; grp_fu_131_p1 <= ap_const_lv32_FFFFFFFF; -- grp_p_bsf32_hw_fu_118_ap_ce assign process. -- grp_p_bsf32_hw_fu_118_ap_ce_assign_proc : process(ap_ce, tmp_3_reg_232, tmp_24_1_reg_236, tmp_26_1_reg_240, tmp_3_fu_141_p2, tmp_24_1_fu_146_p2, tmp_26_1_fu_151_p2) begin if (((ap_const_logic_1 = ap_ce) and ((tmp_3_reg_232 = ap_const_lv1_0) or (not((tmp_3_reg_232 = ap_const_lv1_0)) and not((ap_const_lv1_0 = tmp_24_1_reg_236)) and (ap_const_lv1_0 = tmp_26_1_reg_240)) or (ap_const_lv1_0 = tmp_3_fu_141_p2) or (not((ap_const_lv1_0 = tmp_3_fu_141_p2)) and not((ap_const_lv1_0 = tmp_24_1_fu_146_p2)) and (ap_const_lv1_0 = tmp_26_1_fu_151_p2))))) then grp_p_bsf32_hw_fu_118_ap_ce <= ap_const_logic_1; else grp_p_bsf32_hw_fu_118_ap_ce <= ap_const_logic_0; end if; end process; -- grp_p_bsf32_hw_fu_118_bus_r assign process. -- grp_p_bsf32_hw_fu_118_bus_r_assign_proc : process(ap_reg_ppstg_p_read_1_reg_206_pp0_it8, bus_assign_reg_225, tmp_3_fu_141_p2, tmp_24_1_fu_146_p2, tmp_26_1_fu_151_p2) begin if ((not((ap_const_lv1_0 = tmp_3_fu_141_p2)) and not((ap_const_lv1_0 = tmp_24_1_fu_146_p2)) and (ap_const_lv1_0 = tmp_26_1_fu_151_p2))) then grp_p_bsf32_hw_fu_118_bus_r <= ap_reg_ppstg_p_read_1_reg_206_pp0_it8; elsif ((ap_const_lv1_0 = tmp_3_fu_141_p2)) then grp_p_bsf32_hw_fu_118_bus_r <= bus_assign_reg_225; else grp_p_bsf32_hw_fu_118_bus_r <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX"; end if; end process; tmp_24_1_fu_146_p2 <= "1" when (ap_reg_ppstg_tmp_reg_214_pp0_it8 = ap_const_lv2_0) else "0"; tmp_26_1_fu_151_p2 <= "1" when (ap_reg_ppstg_p_read_1_reg_206_pp0_it8 = ap_const_lv32_0) else "0"; tmp_3_fu_141_p2 <= "1" when (bus_assign_reg_225 = ap_const_lv32_0) else "0"; tmp_fu_127_p1 <= r_bucket_index(2 - 1 downto 0); end behav;
lgpl-3.0
726f5b8e793628aadd3fbbcb075e3fc8
0.629021
2.543853
false
false
false
false
grwlf/vsim
vhdl_ct/pro000021.vhd
1
2,123
-- Prosoft VHDL tests. -- -- Copyright (C) 2011 Prosoft. -- -- Author: Zefirov, Karavaev. -- -- This is a set of simplest tests for isolated tests of VHDL features. -- -- Nothing more than standard package should be required. -- -- Categories: entity, architecture, process, after, enumerations, physical-types, attributes-of-discrete-or-physical-types-and-subtypes. entity ENT00021_Test_Bench is end ENT00021_Test_Bench; architecture ARCH00021_Test_Bench of ENT00021_Test_Bench is type enum is (a_v, b_v, c_v, d_v, e_v, f_v); signal clk : bit := '0'; type uph_t is range -100000 to 100000 units f_uph; p_uph = 10 f_uph; n_uph = 10 p_uph; u_uph = 10 n_uph; m_uph = 10 u_uph; uph = 10 m_uph; end units; begin clk <= not clk after 1 us; process (clk) variable bv2_b1, bv2_b2, bv2_b3, bv2_b4, bv2_b5, bv2_b6, bv2_b7, bv2_b8 : bit; variable na1_i1, na1_i2, na1_i3, na1_i4, na1_i5, na1_i6, na1_i7, na1_i8, na1_i9 : integer; variable e1, e2, e3, e4, e5, e6 : enum; variable int_00 : integer; variable t1, t2, t3, t4, t5 : time; variable v_uph1, v_uph2, v_uph3, v_uph4, v_uph5 : uph_t; begin e1 := enum'Val(3); e2 := enum'Succ(b_v); e3 := enum'Pred(b_v); e4 := enum'Leftof(d_v); e5 := enum'Rightof(d_v); int_00 := enum'Pos(e_v); t1 := time'Val(3); t2 := time'Succ(3 us); t3 := time'Pred(1 us); t4 := time'Leftof(2 ns); t5 := time'Rightof(1 fs); na1_i8 := time'Pos(1 us); v_uph1 := uph_t'Val(3); v_uph2 := uph_t'Succ(3 u_uph); v_uph3 := uph_t'Pred(1 u_uph); v_uph4 := uph_t'Leftof(2 n_uph); v_uph5 := uph_t'Rightof(1 f_uph); na1_i9 := uph_t'Pos(1 u_uph); na1_i1 := integer'Val(3); na1_i2 := integer'Succ(7); na1_i3 := integer'Pred(3); na1_i4 := integer'Leftof(-1); na1_i5 := integer'Rightof(9); na1_i6 := integer'Pos(0); bv2_b1 := bit'Val(0); bv2_b2 := bit'Succ('0'); bv2_b3 := bit'Pred('1'); bv2_b4 := bit'Leftof('1'); bv2_b5 := bit'Rightof('0'); na1_i7 := bit'Pos('1'); end process; end ARCH00021_Test_Bench ;
gpl-3.0
7659f20130710280c67e319e7b089b10
0.579369
2.204569
false
true
false
false
grwlf/vsim
vhdl/assign4.vhd
1
41,483
entity ENT00001_Test_Bench is end entity ENT00001_Test_Bench; architecture arch of ENT00001_Test_Bench is signal clk : integer := 0; constant CYCLES : integer := 10000; -- {{{ signal a0001 : integer; signal a0002 : integer; signal a0003 : integer; signal a0004 : integer; signal a0005 : integer; signal a0006 : integer; signal a0007 : integer; signal a0008 : integer; signal a0009 : integer; signal a0010 : integer; signal a0011 : integer; signal a0012 : integer; signal a0013 : integer; signal a0014 : integer; signal a0015 : integer; signal a0016 : integer; signal a0017 : integer; signal a0018 : integer; signal a0019 : integer; signal a0020 : integer; signal a0021 : integer; signal a0022 : integer; signal a0023 : integer; signal a0024 : integer; signal a0025 : integer; signal a0026 : integer; signal a0027 : integer; signal a0028 : integer; signal a0029 : integer; signal a0030 : integer; signal a0031 : integer; signal a0032 : integer; signal a0033 : integer; signal a0034 : integer; signal a0035 : integer; signal a0036 : integer; signal a0037 : integer; signal a0038 : integer; signal a0039 : integer; signal a0040 : integer; signal a0041 : integer; signal a0042 : integer; signal a0043 : integer; signal a0044 : integer; signal a0045 : integer; signal a0046 : integer; signal a0047 : integer; signal a0048 : integer; signal a0049 : integer; signal a0050 : integer; signal a0051 : integer; signal a0052 : integer; signal a0053 : integer; signal a0054 : integer; signal a0055 : integer; signal a0056 : integer; signal a0057 : integer; signal a0058 : integer; signal a0059 : integer; signal a0060 : integer; signal a0061 : integer; signal a0062 : integer; signal a0063 : integer; signal a0064 : integer; signal a0065 : integer; signal a0066 : integer; signal a0067 : integer; signal a0068 : integer; signal a0069 : integer; signal a0070 : integer; signal a0071 : integer; signal a0072 : integer; signal a0073 : integer; signal a0074 : integer; signal a0075 : integer; signal a0076 : integer; signal a0077 : integer; signal a0078 : integer; signal a0079 : integer; signal a0080 : integer; signal a0081 : integer; signal a0082 : integer; signal a0083 : integer; signal a0084 : integer; signal a0085 : integer; signal a0086 : integer; signal a0087 : integer; signal a0088 : integer; signal a0089 : integer; signal a0090 : integer; signal a0091 : integer; signal a0092 : integer; signal a0093 : integer; signal a0094 : integer; signal a0095 : integer; signal a0096 : integer; signal a0097 : integer; signal a0098 : integer; signal a0099 : integer; signal a0100 : integer; signal a0101 : integer; signal a0102 : integer; signal a0103 : integer; signal a0104 : integer; signal a0105 : integer; signal a0106 : integer; signal a0107 : integer; signal a0108 : integer; signal a0109 : integer; signal a0110 : integer; signal a0111 : integer; signal a0112 : integer; signal a0113 : integer; signal a0114 : integer; signal a0115 : integer; signal a0116 : integer; signal a0117 : integer; signal a0118 : integer; signal a0119 : integer; signal a0120 : integer; signal a0121 : integer; signal a0122 : integer; signal a0123 : integer; signal a0124 : integer; signal a0125 : integer; signal a0126 : integer; signal a0127 : integer; signal a0128 : integer; signal a0129 : integer; signal a0130 : integer; signal a0131 : integer; signal a0132 : integer; signal a0133 : integer; signal a0134 : integer; signal a0135 : integer; signal a0136 : integer; signal a0137 : integer; signal a0138 : integer; signal a0139 : integer; signal a0140 : integer; signal a0141 : integer; signal a0142 : integer; signal a0143 : integer; signal a0144 : integer; signal a0145 : integer; signal a0146 : integer; signal a0147 : integer; signal a0148 : integer; signal a0149 : integer; signal a0150 : integer; signal a0151 : integer; signal a0152 : integer; signal a0153 : integer; signal a0154 : integer; signal a0155 : integer; signal a0156 : integer; signal a0157 : integer; signal a0158 : integer; signal a0159 : integer; signal a0160 : integer; signal a0161 : integer; signal a0162 : integer; signal a0163 : integer; signal a0164 : integer; signal a0165 : integer; signal a0166 : integer; signal a0167 : integer; signal a0168 : integer; signal a0169 : integer; signal a0170 : integer; signal a0171 : integer; signal a0172 : integer; signal a0173 : integer; signal a0174 : integer; signal a0175 : integer; signal a0176 : integer; signal a0177 : integer; signal a0178 : integer; signal a0179 : integer; signal a0180 : integer; signal a0181 : integer; signal a0182 : integer; signal a0183 : integer; signal a0184 : integer; signal a0185 : integer; signal a0186 : integer; signal a0187 : integer; signal a0188 : integer; signal a0189 : integer; signal a0190 : integer; signal a0191 : integer; signal a0192 : integer; signal a0193 : integer; signal a0194 : integer; signal a0195 : integer; signal a0196 : integer; signal a0197 : integer; signal a0198 : integer; signal a0199 : integer; signal a0200 : integer; signal a0201 : integer; signal a0202 : integer; signal a0203 : integer; signal a0204 : integer; signal a0205 : integer; signal a0206 : integer; signal a0207 : integer; signal a0208 : integer; signal a0209 : integer; signal a0210 : integer; signal a0211 : integer; signal a0212 : integer; signal a0213 : integer; signal a0214 : integer; signal a0215 : integer; signal a0216 : integer; signal a0217 : integer; signal a0218 : integer; signal a0219 : integer; signal a0220 : integer; signal a0221 : integer; signal a0222 : integer; signal a0223 : integer; signal a0224 : integer; signal a0225 : integer; signal a0226 : integer; signal a0227 : integer; signal a0228 : integer; signal a0229 : integer; signal a0230 : integer; signal a0231 : integer; signal a0232 : integer; signal a0233 : integer; signal a0234 : integer; signal a0235 : integer; signal a0236 : integer; signal a0237 : integer; signal a0238 : integer; signal a0239 : integer; signal a0240 : integer; signal a0241 : integer; signal a0242 : integer; signal a0243 : integer; signal a0244 : integer; signal a0245 : integer; signal a0246 : integer; signal a0247 : integer; signal a0248 : integer; signal a0249 : integer; signal a0250 : integer; signal a0251 : integer; signal a0252 : integer; signal a0253 : integer; signal a0254 : integer; signal a0255 : integer; signal a0256 : integer; signal a0257 : integer; signal a0258 : integer; signal a0259 : integer; signal a0260 : integer; signal a0261 : integer; signal a0262 : integer; signal a0263 : integer; signal a0264 : integer; signal a0265 : integer; signal a0266 : integer; signal a0267 : integer; signal a0268 : integer; signal a0269 : integer; signal a0270 : integer; signal a0271 : integer; signal a0272 : integer; signal a0273 : integer; signal a0274 : integer; signal a0275 : integer; signal a0276 : integer; signal a0277 : integer; signal a0278 : integer; signal a0279 : integer; signal a0280 : integer; signal a0281 : integer; signal a0282 : integer; signal a0283 : integer; signal a0284 : integer; signal a0285 : integer; signal a0286 : integer; signal a0287 : integer; signal a0288 : integer; signal a0289 : integer; signal a0290 : integer; signal a0291 : integer; signal a0292 : integer; signal a0293 : integer; signal a0294 : integer; signal a0295 : integer; signal a0296 : integer; signal a0297 : integer; signal a0298 : integer; signal a0299 : integer; signal a0300 : integer; signal a0301 : integer; signal a0302 : integer; signal a0303 : integer; signal a0304 : integer; signal a0305 : integer; signal a0306 : integer; signal a0307 : integer; signal a0308 : integer; signal a0309 : integer; signal a0310 : integer; signal a0311 : integer; signal a0312 : integer; signal a0313 : integer; signal a0314 : integer; signal a0315 : integer; signal a0316 : integer; signal a0317 : integer; signal a0318 : integer; signal a0319 : integer; signal a0320 : integer; signal a0321 : integer; signal a0322 : integer; signal a0323 : integer; signal a0324 : integer; signal a0325 : integer; signal a0326 : integer; signal a0327 : integer; signal a0328 : integer; signal a0329 : integer; signal a0330 : integer; signal a0331 : integer; signal a0332 : integer; signal a0333 : integer; signal a0334 : integer; signal a0335 : integer; signal a0336 : integer; signal a0337 : integer; signal a0338 : integer; signal a0339 : integer; signal a0340 : integer; signal a0341 : integer; signal a0342 : integer; signal a0343 : integer; signal a0344 : integer; signal a0345 : integer; signal a0346 : integer; signal a0347 : integer; signal a0348 : integer; signal a0349 : integer; signal a0350 : integer; signal a0351 : integer; signal a0352 : integer; signal a0353 : integer; signal a0354 : integer; signal a0355 : integer; signal a0356 : integer; signal a0357 : integer; signal a0358 : integer; signal a0359 : integer; signal a0360 : integer; signal a0361 : integer; signal a0362 : integer; signal a0363 : integer; signal a0364 : integer; signal a0365 : integer; signal a0366 : integer; signal a0367 : integer; signal a0368 : integer; signal a0369 : integer; signal a0370 : integer; signal a0371 : integer; signal a0372 : integer; signal a0373 : integer; signal a0374 : integer; signal a0375 : integer; signal a0376 : integer; signal a0377 : integer; signal a0378 : integer; signal a0379 : integer; signal a0380 : integer; signal a0381 : integer; signal a0382 : integer; signal a0383 : integer; signal a0384 : integer; signal a0385 : integer; signal a0386 : integer; signal a0387 : integer; signal a0388 : integer; signal a0389 : integer; signal a0390 : integer; signal a0391 : integer; signal a0392 : integer; signal a0393 : integer; signal a0394 : integer; signal a0395 : integer; signal a0396 : integer; signal a0397 : integer; signal a0398 : integer; signal a0399 : integer; signal a0400 : integer; signal a0401 : integer; signal a0402 : integer; signal a0403 : integer; signal a0404 : integer; signal a0405 : integer; signal a0406 : integer; signal a0407 : integer; signal a0408 : integer; signal a0409 : integer; signal a0410 : integer; signal a0411 : integer; signal a0412 : integer; signal a0413 : integer; signal a0414 : integer; signal a0415 : integer; signal a0416 : integer; signal a0417 : integer; signal a0418 : integer; signal a0419 : integer; signal a0420 : integer; signal a0421 : integer; signal a0422 : integer; signal a0423 : integer; signal a0424 : integer; signal a0425 : integer; signal a0426 : integer; signal a0427 : integer; signal a0428 : integer; signal a0429 : integer; signal a0430 : integer; signal a0431 : integer; signal a0432 : integer; signal a0433 : integer; signal a0434 : integer; signal a0435 : integer; signal a0436 : integer; signal a0437 : integer; signal a0438 : integer; signal a0439 : integer; signal a0440 : integer; signal a0441 : integer; signal a0442 : integer; signal a0443 : integer; signal a0444 : integer; signal a0445 : integer; signal a0446 : integer; signal a0447 : integer; signal a0448 : integer; signal a0449 : integer; signal a0450 : integer; signal a0451 : integer; signal a0452 : integer; signal a0453 : integer; signal a0454 : integer; signal a0455 : integer; signal a0456 : integer; signal a0457 : integer; signal a0458 : integer; signal a0459 : integer; signal a0460 : integer; signal a0461 : integer; signal a0462 : integer; signal a0463 : integer; signal a0464 : integer; signal a0465 : integer; signal a0466 : integer; signal a0467 : integer; signal a0468 : integer; signal a0469 : integer; signal a0470 : integer; signal a0471 : integer; signal a0472 : integer; signal a0473 : integer; signal a0474 : integer; signal a0475 : integer; signal a0476 : integer; signal a0477 : integer; signal a0478 : integer; signal a0479 : integer; signal a0480 : integer; signal a0481 : integer; signal a0482 : integer; signal a0483 : integer; signal a0484 : integer; signal a0485 : integer; signal a0486 : integer; signal a0487 : integer; signal a0488 : integer; signal a0489 : integer; signal a0490 : integer; signal a0491 : integer; signal a0492 : integer; signal a0493 : integer; signal a0494 : integer; signal a0495 : integer; signal a0496 : integer; signal a0497 : integer; signal a0498 : integer; signal a0499 : integer; signal a0500 : integer; signal a0501 : integer; signal a0502 : integer; signal a0503 : integer; signal a0504 : integer; signal a0505 : integer; signal a0506 : integer; signal a0507 : integer; signal a0508 : integer; signal a0509 : integer; signal a0510 : integer; signal a0511 : integer; signal a0512 : integer; signal a0513 : integer; signal a0514 : integer; signal a0515 : integer; signal a0516 : integer; signal a0517 : integer; signal a0518 : integer; signal a0519 : integer; signal a0520 : integer; signal a0521 : integer; signal a0522 : integer; signal a0523 : integer; signal a0524 : integer; signal a0525 : integer; signal a0526 : integer; signal a0527 : integer; signal a0528 : integer; signal a0529 : integer; signal a0530 : integer; signal a0531 : integer; signal a0532 : integer; signal a0533 : integer; signal a0534 : integer; signal a0535 : integer; signal a0536 : integer; signal a0537 : integer; signal a0538 : integer; signal a0539 : integer; signal a0540 : integer; signal a0541 : integer; signal a0542 : integer; signal a0543 : integer; signal a0544 : integer; signal a0545 : integer; signal a0546 : integer; signal a0547 : integer; signal a0548 : integer; signal a0549 : integer; signal a0550 : integer; signal a0551 : integer; signal a0552 : integer; signal a0553 : integer; signal a0554 : integer; signal a0555 : integer; signal a0556 : integer; signal a0557 : integer; signal a0558 : integer; signal a0559 : integer; signal a0560 : integer; signal a0561 : integer; signal a0562 : integer; signal a0563 : integer; signal a0564 : integer; signal a0565 : integer; signal a0566 : integer; signal a0567 : integer; signal a0568 : integer; signal a0569 : integer; signal a0570 : integer; signal a0571 : integer; signal a0572 : integer; signal a0573 : integer; signal a0574 : integer; signal a0575 : integer; signal a0576 : integer; signal a0577 : integer; signal a0578 : integer; signal a0579 : integer; signal a0580 : integer; signal a0581 : integer; signal a0582 : integer; signal a0583 : integer; signal a0584 : integer; signal a0585 : integer; signal a0586 : integer; signal a0587 : integer; signal a0588 : integer; signal a0589 : integer; signal a0590 : integer; signal a0591 : integer; signal a0592 : integer; signal a0593 : integer; signal a0594 : integer; signal a0595 : integer; signal a0596 : integer; signal a0597 : integer; signal a0598 : integer; signal a0599 : integer; signal a0600 : integer; signal a0601 : integer; signal a0602 : integer; signal a0603 : integer; signal a0604 : integer; signal a0605 : integer; signal a0606 : integer; signal a0607 : integer; signal a0608 : integer; signal a0609 : integer; signal a0610 : integer; signal a0611 : integer; signal a0612 : integer; signal a0613 : integer; signal a0614 : integer; signal a0615 : integer; signal a0616 : integer; signal a0617 : integer; signal a0618 : integer; signal a0619 : integer; signal a0620 : integer; signal a0621 : integer; signal a0622 : integer; signal a0623 : integer; signal a0624 : integer; signal a0625 : integer; signal a0626 : integer; signal a0627 : integer; signal a0628 : integer; signal a0629 : integer; signal a0630 : integer; signal a0631 : integer; signal a0632 : integer; signal a0633 : integer; signal a0634 : integer; signal a0635 : integer; signal a0636 : integer; signal a0637 : integer; signal a0638 : integer; signal a0639 : integer; signal a0640 : integer; signal a0641 : integer; signal a0642 : integer; signal a0643 : integer; signal a0644 : integer; signal a0645 : integer; signal a0646 : integer; signal a0647 : integer; signal a0648 : integer; signal a0649 : integer; signal a0650 : integer; signal a0651 : integer; signal a0652 : integer; signal a0653 : integer; signal a0654 : integer; signal a0655 : integer; signal a0656 : integer; signal a0657 : integer; signal a0658 : integer; signal a0659 : integer; signal a0660 : integer; signal a0661 : integer; signal a0662 : integer; signal a0663 : integer; signal a0664 : integer; signal a0665 : integer; signal a0666 : integer; signal a0667 : integer; signal a0668 : integer; signal a0669 : integer; signal a0670 : integer; signal a0671 : integer; signal a0672 : integer; signal a0673 : integer; signal a0674 : integer; signal a0675 : integer; signal a0676 : integer; signal a0677 : integer; signal a0678 : integer; signal a0679 : integer; signal a0680 : integer; signal a0681 : integer; signal a0682 : integer; signal a0683 : integer; signal a0684 : integer; signal a0685 : integer; signal a0686 : integer; signal a0687 : integer; signal a0688 : integer; signal a0689 : integer; signal a0690 : integer; signal a0691 : integer; signal a0692 : integer; signal a0693 : integer; signal a0694 : integer; signal a0695 : integer; signal a0696 : integer; signal a0697 : integer; signal a0698 : integer; signal a0699 : integer; signal a0700 : integer; signal a0701 : integer; signal a0702 : integer; signal a0703 : integer; signal a0704 : integer; signal a0705 : integer; signal a0706 : integer; signal a0707 : integer; signal a0708 : integer; signal a0709 : integer; signal a0710 : integer; signal a0711 : integer; signal a0712 : integer; signal a0713 : integer; signal a0714 : integer; signal a0715 : integer; signal a0716 : integer; signal a0717 : integer; signal a0718 : integer; signal a0719 : integer; signal a0720 : integer; signal a0721 : integer; signal a0722 : integer; signal a0723 : integer; signal a0724 : integer; signal a0725 : integer; signal a0726 : integer; signal a0727 : integer; signal a0728 : integer; signal a0729 : integer; signal a0730 : integer; signal a0731 : integer; signal a0732 : integer; signal a0733 : integer; signal a0734 : integer; signal a0735 : integer; signal a0736 : integer; signal a0737 : integer; signal a0738 : integer; signal a0739 : integer; signal a0740 : integer; signal a0741 : integer; signal a0742 : integer; signal a0743 : integer; signal a0744 : integer; signal a0745 : integer; signal a0746 : integer; signal a0747 : integer; signal a0748 : integer; signal a0749 : integer; signal a0750 : integer; signal a0751 : integer; signal a0752 : integer; signal a0753 : integer; signal a0754 : integer; signal a0755 : integer; signal a0756 : integer; signal a0757 : integer; signal a0758 : integer; signal a0759 : integer; signal a0760 : integer; signal a0761 : integer; signal a0762 : integer; signal a0763 : integer; signal a0764 : integer; signal a0765 : integer; signal a0766 : integer; signal a0767 : integer; signal a0768 : integer; signal a0769 : integer; signal a0770 : integer; signal a0771 : integer; signal a0772 : integer; signal a0773 : integer; signal a0774 : integer; signal a0775 : integer; signal a0776 : integer; signal a0777 : integer; signal a0778 : integer; signal a0779 : integer; signal a0780 : integer; signal a0781 : integer; signal a0782 : integer; signal a0783 : integer; signal a0784 : integer; signal a0785 : integer; signal a0786 : integer; signal a0787 : integer; signal a0788 : integer; signal a0789 : integer; signal a0790 : integer; signal a0791 : integer; signal a0792 : integer; signal a0793 : integer; signal a0794 : integer; signal a0795 : integer; signal a0796 : integer; signal a0797 : integer; signal a0798 : integer; signal a0799 : integer; signal a0800 : integer; signal a0801 : integer; signal a0802 : integer; signal a0803 : integer; signal a0804 : integer; signal a0805 : integer; signal a0806 : integer; signal a0807 : integer; signal a0808 : integer; signal a0809 : integer; signal a0810 : integer; signal a0811 : integer; signal a0812 : integer; signal a0813 : integer; signal a0814 : integer; signal a0815 : integer; signal a0816 : integer; signal a0817 : integer; signal a0818 : integer; signal a0819 : integer; signal a0820 : integer; signal a0821 : integer; signal a0822 : integer; signal a0823 : integer; signal a0824 : integer; signal a0825 : integer; signal a0826 : integer; signal a0827 : integer; signal a0828 : integer; signal a0829 : integer; signal a0830 : integer; signal a0831 : integer; signal a0832 : integer; signal a0833 : integer; signal a0834 : integer; signal a0835 : integer; signal a0836 : integer; signal a0837 : integer; signal a0838 : integer; signal a0839 : integer; signal a0840 : integer; signal a0841 : integer; signal a0842 : integer; signal a0843 : integer; signal a0844 : integer; signal a0845 : integer; signal a0846 : integer; signal a0847 : integer; signal a0848 : integer; signal a0849 : integer; signal a0850 : integer; signal a0851 : integer; signal a0852 : integer; signal a0853 : integer; signal a0854 : integer; signal a0855 : integer; signal a0856 : integer; signal a0857 : integer; signal a0858 : integer; signal a0859 : integer; signal a0860 : integer; signal a0861 : integer; signal a0862 : integer; signal a0863 : integer; signal a0864 : integer; signal a0865 : integer; signal a0866 : integer; signal a0867 : integer; signal a0868 : integer; signal a0869 : integer; signal a0870 : integer; signal a0871 : integer; signal a0872 : integer; signal a0873 : integer; signal a0874 : integer; signal a0875 : integer; signal a0876 : integer; signal a0877 : integer; signal a0878 : integer; signal a0879 : integer; signal a0880 : integer; signal a0881 : integer; signal a0882 : integer; signal a0883 : integer; signal a0884 : integer; signal a0885 : integer; signal a0886 : integer; signal a0887 : integer; signal a0888 : integer; signal a0889 : integer; signal a0890 : integer; signal a0891 : integer; signal a0892 : integer; signal a0893 : integer; signal a0894 : integer; signal a0895 : integer; signal a0896 : integer; signal a0897 : integer; signal a0898 : integer; signal a0899 : integer; signal a0900 : integer; signal a0901 : integer; signal a0902 : integer; signal a0903 : integer; signal a0904 : integer; signal a0905 : integer; signal a0906 : integer; signal a0907 : integer; signal a0908 : integer; signal a0909 : integer; signal a0910 : integer; signal a0911 : integer; signal a0912 : integer; signal a0913 : integer; signal a0914 : integer; signal a0915 : integer; signal a0916 : integer; signal a0917 : integer; signal a0918 : integer; signal a0919 : integer; signal a0920 : integer; signal a0921 : integer; signal a0922 : integer; signal a0923 : integer; signal a0924 : integer; signal a0925 : integer; signal a0926 : integer; signal a0927 : integer; signal a0928 : integer; signal a0929 : integer; signal a0930 : integer; signal a0931 : integer; signal a0932 : integer; signal a0933 : integer; signal a0934 : integer; signal a0935 : integer; signal a0936 : integer; signal a0937 : integer; signal a0938 : integer; signal a0939 : integer; signal a0940 : integer; signal a0941 : integer; signal a0942 : integer; signal a0943 : integer; signal a0944 : integer; signal a0945 : integer; signal a0946 : integer; signal a0947 : integer; signal a0948 : integer; signal a0949 : integer; signal a0950 : integer; signal a0951 : integer; signal a0952 : integer; signal a0953 : integer; signal a0954 : integer; signal a0955 : integer; signal a0956 : integer; signal a0957 : integer; signal a0958 : integer; signal a0959 : integer; signal a0960 : integer; signal a0961 : integer; signal a0962 : integer; signal a0963 : integer; signal a0964 : integer; signal a0965 : integer; signal a0966 : integer; signal a0967 : integer; signal a0968 : integer; signal a0969 : integer; signal a0970 : integer; signal a0971 : integer; signal a0972 : integer; signal a0973 : integer; signal a0974 : integer; signal a0975 : integer; signal a0976 : integer; signal a0977 : integer; signal a0978 : integer; signal a0979 : integer; signal a0980 : integer; signal a0981 : integer; signal a0982 : integer; signal a0983 : integer; signal a0984 : integer; signal a0985 : integer; signal a0986 : integer; signal a0987 : integer; signal a0988 : integer; signal a0989 : integer; signal a0990 : integer; signal a0991 : integer; signal a0992 : integer; signal a0993 : integer; signal a0994 : integer; signal a0995 : integer; signal a0996 : integer; signal a0997 : integer; signal a0998 : integer; signal a0999 : integer; signal a1000 : integer; -- }}} begin main: process(clk) --{{{ begin a0001 <= clk; a0002 <= clk; a0003 <= clk; a0004 <= clk; a0005 <= clk; a0006 <= clk; a0007 <= clk; a0008 <= clk; a0009 <= clk; a0010 <= clk; a0011 <= clk; a0012 <= clk; a0013 <= clk; a0014 <= clk; a0015 <= clk; a0016 <= clk; a0017 <= clk; a0018 <= clk; a0019 <= clk; a0020 <= clk; a0021 <= clk; a0022 <= clk; a0023 <= clk; a0024 <= clk; a0025 <= clk; a0026 <= clk; a0027 <= clk; a0028 <= clk; a0029 <= clk; a0030 <= clk; a0031 <= clk; a0032 <= clk; a0033 <= clk; a0034 <= clk; a0035 <= clk; a0036 <= clk; a0037 <= clk; a0038 <= clk; a0039 <= clk; a0040 <= clk; a0041 <= clk; a0042 <= clk; a0043 <= clk; a0044 <= clk; a0045 <= clk; a0046 <= clk; a0047 <= clk; a0048 <= clk; a0049 <= clk; a0050 <= clk; a0051 <= clk; a0052 <= clk; a0053 <= clk; a0054 <= clk; a0055 <= clk; a0056 <= clk; a0057 <= clk; a0058 <= clk; a0059 <= clk; a0060 <= clk; a0061 <= clk; a0062 <= clk; a0063 <= clk; a0064 <= clk; a0065 <= clk; a0066 <= clk; a0067 <= clk; a0068 <= clk; a0069 <= clk; a0070 <= clk; a0071 <= clk; a0072 <= clk; a0073 <= clk; a0074 <= clk; a0075 <= clk; a0076 <= clk; a0077 <= clk; a0078 <= clk; a0079 <= clk; a0080 <= clk; a0081 <= clk; a0082 <= clk; a0083 <= clk; a0084 <= clk; a0085 <= clk; a0086 <= clk; a0087 <= clk; a0088 <= clk; a0089 <= clk; a0090 <= clk; a0091 <= clk; a0092 <= clk; a0093 <= clk; a0094 <= clk; a0095 <= clk; a0096 <= clk; a0097 <= clk; a0098 <= clk; a0099 <= clk; a0100 <= clk; a0101 <= clk; a0102 <= clk; a0103 <= clk; a0104 <= clk; a0105 <= clk; a0106 <= clk; a0107 <= clk; a0108 <= clk; a0109 <= clk; a0110 <= clk; a0111 <= clk; a0112 <= clk; a0113 <= clk; a0114 <= clk; a0115 <= clk; a0116 <= clk; a0117 <= clk; a0118 <= clk; a0119 <= clk; a0120 <= clk; a0121 <= clk; a0122 <= clk; a0123 <= clk; a0124 <= clk; a0125 <= clk; a0126 <= clk; a0127 <= clk; a0128 <= clk; a0129 <= clk; a0130 <= clk; a0131 <= clk; a0132 <= clk; a0133 <= clk; a0134 <= clk; a0135 <= clk; a0136 <= clk; a0137 <= clk; a0138 <= clk; a0139 <= clk; a0140 <= clk; a0141 <= clk; a0142 <= clk; a0143 <= clk; a0144 <= clk; a0145 <= clk; a0146 <= clk; a0147 <= clk; a0148 <= clk; a0149 <= clk; a0150 <= clk; a0151 <= clk; a0152 <= clk; a0153 <= clk; a0154 <= clk; a0155 <= clk; a0156 <= clk; a0157 <= clk; a0158 <= clk; a0159 <= clk; a0160 <= clk; a0161 <= clk; a0162 <= clk; a0163 <= clk; a0164 <= clk; a0165 <= clk; a0166 <= clk; a0167 <= clk; a0168 <= clk; a0169 <= clk; a0170 <= clk; a0171 <= clk; a0172 <= clk; a0173 <= clk; a0174 <= clk; a0175 <= clk; a0176 <= clk; a0177 <= clk; a0178 <= clk; a0179 <= clk; a0180 <= clk; a0181 <= clk; a0182 <= clk; a0183 <= clk; a0184 <= clk; a0185 <= clk; a0186 <= clk; a0187 <= clk; a0188 <= clk; a0189 <= clk; a0190 <= clk; a0191 <= clk; a0192 <= clk; a0193 <= clk; a0194 <= clk; a0195 <= clk; a0196 <= clk; a0197 <= clk; a0198 <= clk; a0199 <= clk; a0200 <= clk; a0201 <= clk; a0202 <= clk; a0203 <= clk; a0204 <= clk; a0205 <= clk; a0206 <= clk; a0207 <= clk; a0208 <= clk; a0209 <= clk; a0210 <= clk; a0211 <= clk; a0212 <= clk; a0213 <= clk; a0214 <= clk; a0215 <= clk; a0216 <= clk; a0217 <= clk; a0218 <= clk; a0219 <= clk; a0220 <= clk; a0221 <= clk; a0222 <= clk; a0223 <= clk; a0224 <= clk; a0225 <= clk; a0226 <= clk; a0227 <= clk; a0228 <= clk; a0229 <= clk; a0230 <= clk; a0231 <= clk; a0232 <= clk; a0233 <= clk; a0234 <= clk; a0235 <= clk; a0236 <= clk; a0237 <= clk; a0238 <= clk; a0239 <= clk; a0240 <= clk; a0241 <= clk; a0242 <= clk; a0243 <= clk; a0244 <= clk; a0245 <= clk; a0246 <= clk; a0247 <= clk; a0248 <= clk; a0249 <= clk; a0250 <= clk; a0251 <= clk; a0252 <= clk; a0253 <= clk; a0254 <= clk; a0255 <= clk; a0256 <= clk; a0257 <= clk; a0258 <= clk; a0259 <= clk; a0260 <= clk; a0261 <= clk; a0262 <= clk; a0263 <= clk; a0264 <= clk; a0265 <= clk; a0266 <= clk; a0267 <= clk; a0268 <= clk; a0269 <= clk; a0270 <= clk; a0271 <= clk; a0272 <= clk; a0273 <= clk; a0274 <= clk; a0275 <= clk; a0276 <= clk; a0277 <= clk; a0278 <= clk; a0279 <= clk; a0280 <= clk; a0281 <= clk; a0282 <= clk; a0283 <= clk; a0284 <= clk; a0285 <= clk; a0286 <= clk; a0287 <= clk; a0288 <= clk; a0289 <= clk; a0290 <= clk; a0291 <= clk; a0292 <= clk; a0293 <= clk; a0294 <= clk; a0295 <= clk; a0296 <= clk; a0297 <= clk; a0298 <= clk; a0299 <= clk; a0300 <= clk; a0301 <= clk; a0302 <= clk; a0303 <= clk; a0304 <= clk; a0305 <= clk; a0306 <= clk; a0307 <= clk; a0308 <= clk; a0309 <= clk; a0310 <= clk; a0311 <= clk; a0312 <= clk; a0313 <= clk; a0314 <= clk; a0315 <= clk; a0316 <= clk; a0317 <= clk; a0318 <= clk; a0319 <= clk; a0320 <= clk; a0321 <= clk; a0322 <= clk; a0323 <= clk; a0324 <= clk; a0325 <= clk; a0326 <= clk; a0327 <= clk; a0328 <= clk; a0329 <= clk; a0330 <= clk; a0331 <= clk; a0332 <= clk; a0333 <= clk; a0334 <= clk; a0335 <= clk; a0336 <= clk; a0337 <= clk; a0338 <= clk; a0339 <= clk; a0340 <= clk; a0341 <= clk; a0342 <= clk; a0343 <= clk; a0344 <= clk; a0345 <= clk; a0346 <= clk; a0347 <= clk; a0348 <= clk; a0349 <= clk; a0350 <= clk; a0351 <= clk; a0352 <= clk; a0353 <= clk; a0354 <= clk; a0355 <= clk; a0356 <= clk; a0357 <= clk; a0358 <= clk; a0359 <= clk; a0360 <= clk; a0361 <= clk; a0362 <= clk; a0363 <= clk; a0364 <= clk; a0365 <= clk; a0366 <= clk; a0367 <= clk; a0368 <= clk; a0369 <= clk; a0370 <= clk; a0371 <= clk; a0372 <= clk; a0373 <= clk; a0374 <= clk; a0375 <= clk; a0376 <= clk; a0377 <= clk; a0378 <= clk; a0379 <= clk; a0380 <= clk; a0381 <= clk; a0382 <= clk; a0383 <= clk; a0384 <= clk; a0385 <= clk; a0386 <= clk; a0387 <= clk; a0388 <= clk; a0389 <= clk; a0390 <= clk; a0391 <= clk; a0392 <= clk; a0393 <= clk; a0394 <= clk; a0395 <= clk; a0396 <= clk; a0397 <= clk; a0398 <= clk; a0399 <= clk; a0400 <= clk; a0401 <= clk; a0402 <= clk; a0403 <= clk; a0404 <= clk; a0405 <= clk; a0406 <= clk; a0407 <= clk; a0408 <= clk; a0409 <= clk; a0410 <= clk; a0411 <= clk; a0412 <= clk; a0413 <= clk; a0414 <= clk; a0415 <= clk; a0416 <= clk; a0417 <= clk; a0418 <= clk; a0419 <= clk; a0420 <= clk; a0421 <= clk; a0422 <= clk; a0423 <= clk; a0424 <= clk; a0425 <= clk; a0426 <= clk; a0427 <= clk; a0428 <= clk; a0429 <= clk; a0430 <= clk; a0431 <= clk; a0432 <= clk; a0433 <= clk; a0434 <= clk; a0435 <= clk; a0436 <= clk; a0437 <= clk; a0438 <= clk; a0439 <= clk; a0440 <= clk; a0441 <= clk; a0442 <= clk; a0443 <= clk; a0444 <= clk; a0445 <= clk; a0446 <= clk; a0447 <= clk; a0448 <= clk; a0449 <= clk; a0450 <= clk; a0451 <= clk; a0452 <= clk; a0453 <= clk; a0454 <= clk; a0455 <= clk; a0456 <= clk; a0457 <= clk; a0458 <= clk; a0459 <= clk; a0460 <= clk; a0461 <= clk; a0462 <= clk; a0463 <= clk; a0464 <= clk; a0465 <= clk; a0466 <= clk; a0467 <= clk; a0468 <= clk; a0469 <= clk; a0470 <= clk; a0471 <= clk; a0472 <= clk; a0473 <= clk; a0474 <= clk; a0475 <= clk; a0476 <= clk; a0477 <= clk; a0478 <= clk; a0479 <= clk; a0480 <= clk; a0481 <= clk; a0482 <= clk; a0483 <= clk; a0484 <= clk; a0485 <= clk; a0486 <= clk; a0487 <= clk; a0488 <= clk; a0489 <= clk; a0490 <= clk; a0491 <= clk; a0492 <= clk; a0493 <= clk; a0494 <= clk; a0495 <= clk; a0496 <= clk; a0497 <= clk; a0498 <= clk; a0499 <= clk; a0500 <= clk; a0501 <= clk; a0502 <= clk; a0503 <= clk; a0504 <= clk; a0505 <= clk; a0506 <= clk; a0507 <= clk; a0508 <= clk; a0509 <= clk; a0510 <= clk; a0511 <= clk; a0512 <= clk; a0513 <= clk; a0514 <= clk; a0515 <= clk; a0516 <= clk; a0517 <= clk; a0518 <= clk; a0519 <= clk; a0520 <= clk; a0521 <= clk; a0522 <= clk; a0523 <= clk; a0524 <= clk; a0525 <= clk; a0526 <= clk; a0527 <= clk; a0528 <= clk; a0529 <= clk; a0530 <= clk; a0531 <= clk; a0532 <= clk; a0533 <= clk; a0534 <= clk; a0535 <= clk; a0536 <= clk; a0537 <= clk; a0538 <= clk; a0539 <= clk; a0540 <= clk; a0541 <= clk; a0542 <= clk; a0543 <= clk; a0544 <= clk; a0545 <= clk; a0546 <= clk; a0547 <= clk; a0548 <= clk; a0549 <= clk; a0550 <= clk; a0551 <= clk; a0552 <= clk; a0553 <= clk; a0554 <= clk; a0555 <= clk; a0556 <= clk; a0557 <= clk; a0558 <= clk; a0559 <= clk; a0560 <= clk; a0561 <= clk; a0562 <= clk; a0563 <= clk; a0564 <= clk; a0565 <= clk; a0566 <= clk; a0567 <= clk; a0568 <= clk; a0569 <= clk; a0570 <= clk; a0571 <= clk; a0572 <= clk; a0573 <= clk; a0574 <= clk; a0575 <= clk; a0576 <= clk; a0577 <= clk; a0578 <= clk; a0579 <= clk; a0580 <= clk; a0581 <= clk; a0582 <= clk; a0583 <= clk; a0584 <= clk; a0585 <= clk; a0586 <= clk; a0587 <= clk; a0588 <= clk; a0589 <= clk; a0590 <= clk; a0591 <= clk; a0592 <= clk; a0593 <= clk; a0594 <= clk; a0595 <= clk; a0596 <= clk; a0597 <= clk; a0598 <= clk; a0599 <= clk; a0600 <= clk; a0601 <= clk; a0602 <= clk; a0603 <= clk; a0604 <= clk; a0605 <= clk; a0606 <= clk; a0607 <= clk; a0608 <= clk; a0609 <= clk; a0610 <= clk; a0611 <= clk; a0612 <= clk; a0613 <= clk; a0614 <= clk; a0615 <= clk; a0616 <= clk; a0617 <= clk; a0618 <= clk; a0619 <= clk; a0620 <= clk; a0621 <= clk; a0622 <= clk; a0623 <= clk; a0624 <= clk; a0625 <= clk; a0626 <= clk; a0627 <= clk; a0628 <= clk; a0629 <= clk; a0630 <= clk; a0631 <= clk; a0632 <= clk; a0633 <= clk; a0634 <= clk; a0635 <= clk; a0636 <= clk; a0637 <= clk; a0638 <= clk; a0639 <= clk; a0640 <= clk; a0641 <= clk; a0642 <= clk; a0643 <= clk; a0644 <= clk; a0645 <= clk; a0646 <= clk; a0647 <= clk; a0648 <= clk; a0649 <= clk; a0650 <= clk; a0651 <= clk; a0652 <= clk; a0653 <= clk; a0654 <= clk; a0655 <= clk; a0656 <= clk; a0657 <= clk; a0658 <= clk; a0659 <= clk; a0660 <= clk; a0661 <= clk; a0662 <= clk; a0663 <= clk; a0664 <= clk; a0665 <= clk; a0666 <= clk; a0667 <= clk; a0668 <= clk; a0669 <= clk; a0670 <= clk; a0671 <= clk; a0672 <= clk; a0673 <= clk; a0674 <= clk; a0675 <= clk; a0676 <= clk; a0677 <= clk; a0678 <= clk; a0679 <= clk; a0680 <= clk; a0681 <= clk; a0682 <= clk; a0683 <= clk; a0684 <= clk; a0685 <= clk; a0686 <= clk; a0687 <= clk; a0688 <= clk; a0689 <= clk; a0690 <= clk; a0691 <= clk; a0692 <= clk; a0693 <= clk; a0694 <= clk; a0695 <= clk; a0696 <= clk; a0697 <= clk; a0698 <= clk; a0699 <= clk; a0700 <= clk; a0701 <= clk; a0702 <= clk; a0703 <= clk; a0704 <= clk; a0705 <= clk; a0706 <= clk; a0707 <= clk; a0708 <= clk; a0709 <= clk; a0710 <= clk; a0711 <= clk; a0712 <= clk; a0713 <= clk; a0714 <= clk; a0715 <= clk; a0716 <= clk; a0717 <= clk; a0718 <= clk; a0719 <= clk; a0720 <= clk; a0721 <= clk; a0722 <= clk; a0723 <= clk; a0724 <= clk; a0725 <= clk; a0726 <= clk; a0727 <= clk; a0728 <= clk; a0729 <= clk; a0730 <= clk; a0731 <= clk; a0732 <= clk; a0733 <= clk; a0734 <= clk; a0735 <= clk; a0736 <= clk; a0737 <= clk; a0738 <= clk; a0739 <= clk; a0740 <= clk; a0741 <= clk; a0742 <= clk; a0743 <= clk; a0744 <= clk; a0745 <= clk; a0746 <= clk; a0747 <= clk; a0748 <= clk; a0749 <= clk; a0750 <= clk; a0751 <= clk; a0752 <= clk; a0753 <= clk; a0754 <= clk; a0755 <= clk; a0756 <= clk; a0757 <= clk; a0758 <= clk; a0759 <= clk; a0760 <= clk; a0761 <= clk; a0762 <= clk; a0763 <= clk; a0764 <= clk; a0765 <= clk; a0766 <= clk; a0767 <= clk; a0768 <= clk; a0769 <= clk; a0770 <= clk; a0771 <= clk; a0772 <= clk; a0773 <= clk; a0774 <= clk; a0775 <= clk; a0776 <= clk; a0777 <= clk; a0778 <= clk; a0779 <= clk; a0780 <= clk; a0781 <= clk; a0782 <= clk; a0783 <= clk; a0784 <= clk; a0785 <= clk; a0786 <= clk; a0787 <= clk; a0788 <= clk; a0789 <= clk; a0790 <= clk; a0791 <= clk; a0792 <= clk; a0793 <= clk; a0794 <= clk; a0795 <= clk; a0796 <= clk; a0797 <= clk; a0798 <= clk; a0799 <= clk; a0800 <= clk; a0801 <= clk; a0802 <= clk; a0803 <= clk; a0804 <= clk; a0805 <= clk; a0806 <= clk; a0807 <= clk; a0808 <= clk; a0809 <= clk; a0810 <= clk; a0811 <= clk; a0812 <= clk; a0813 <= clk; a0814 <= clk; a0815 <= clk; a0816 <= clk; a0817 <= clk; a0818 <= clk; a0819 <= clk; a0820 <= clk; a0821 <= clk; a0822 <= clk; a0823 <= clk; a0824 <= clk; a0825 <= clk; a0826 <= clk; a0827 <= clk; a0828 <= clk; a0829 <= clk; a0830 <= clk; a0831 <= clk; a0832 <= clk; a0833 <= clk; a0834 <= clk; a0835 <= clk; a0836 <= clk; a0837 <= clk; a0838 <= clk; a0839 <= clk; a0840 <= clk; a0841 <= clk; a0842 <= clk; a0843 <= clk; a0844 <= clk; a0845 <= clk; a0846 <= clk; a0847 <= clk; a0848 <= clk; a0849 <= clk; a0850 <= clk; a0851 <= clk; a0852 <= clk; a0853 <= clk; a0854 <= clk; a0855 <= clk; a0856 <= clk; a0857 <= clk; a0858 <= clk; a0859 <= clk; a0860 <= clk; a0861 <= clk; a0862 <= clk; a0863 <= clk; a0864 <= clk; a0865 <= clk; a0866 <= clk; a0867 <= clk; a0868 <= clk; a0869 <= clk; a0870 <= clk; a0871 <= clk; a0872 <= clk; a0873 <= clk; a0874 <= clk; a0875 <= clk; a0876 <= clk; a0877 <= clk; a0878 <= clk; a0879 <= clk; a0880 <= clk; a0881 <= clk; a0882 <= clk; a0883 <= clk; a0884 <= clk; a0885 <= clk; a0886 <= clk; a0887 <= clk; a0888 <= clk; a0889 <= clk; a0890 <= clk; a0891 <= clk; a0892 <= clk; a0893 <= clk; a0894 <= clk; a0895 <= clk; a0896 <= clk; a0897 <= clk; a0898 <= clk; a0899 <= clk; a0900 <= clk; a0901 <= clk; a0902 <= clk; a0903 <= clk; a0904 <= clk; a0905 <= clk; a0906 <= clk; a0907 <= clk; a0908 <= clk; a0909 <= clk; a0910 <= clk; a0911 <= clk; a0912 <= clk; a0913 <= clk; a0914 <= clk; a0915 <= clk; a0916 <= clk; a0917 <= clk; a0918 <= clk; a0919 <= clk; a0920 <= clk; a0921 <= clk; a0922 <= clk; a0923 <= clk; a0924 <= clk; a0925 <= clk; a0926 <= clk; a0927 <= clk; a0928 <= clk; a0929 <= clk; a0930 <= clk; a0931 <= clk; a0932 <= clk; a0933 <= clk; a0934 <= clk; a0935 <= clk; a0936 <= clk; a0937 <= clk; a0938 <= clk; a0939 <= clk; a0940 <= clk; a0941 <= clk; a0942 <= clk; a0943 <= clk; a0944 <= clk; a0945 <= clk; a0946 <= clk; a0947 <= clk; a0948 <= clk; a0949 <= clk; a0950 <= clk; a0951 <= clk; a0952 <= clk; a0953 <= clk; a0954 <= clk; a0955 <= clk; a0956 <= clk; a0957 <= clk; a0958 <= clk; a0959 <= clk; a0960 <= clk; a0961 <= clk; a0962 <= clk; a0963 <= clk; a0964 <= clk; a0965 <= clk; a0966 <= clk; a0967 <= clk; a0968 <= clk; a0969 <= clk; a0970 <= clk; a0971 <= clk; a0972 <= clk; a0973 <= clk; a0974 <= clk; a0975 <= clk; a0976 <= clk; a0977 <= clk; a0978 <= clk; a0979 <= clk; a0980 <= clk; a0981 <= clk; a0982 <= clk; a0983 <= clk; a0984 <= clk; a0985 <= clk; a0986 <= clk; a0987 <= clk; a0988 <= clk; a0989 <= clk; a0990 <= clk; a0991 <= clk; a0992 <= clk; a0993 <= clk; a0994 <= clk; a0995 <= clk; a0996 <= clk; a0997 <= clk; a0998 <= clk; a0999 <= clk; a1000 <= clk; report "tick"; --}}} end process; terminator : process(clk) begin if clk >= CYCLES then assert false report "end of simulation" severity failure; -- else -- report "tick"; end if; end process; clk <= (clk+1) after 1 us; end;
gpl-3.0
8ca2a75a44617ff349f417e795776475
0.634212
2.605552
false
false
false
false
Given-Jiang/Binarization
tb_Binarization/db/alt_dspbuilder_decoder.vhd
2
2,555
-- This file is not intended for synthesis, is is present so that simulators -- see a complete view of the system. -- You may use the entity declaration from this file as the basis for a -- component declaration in a VHDL file instantiating this entity. library IEEE; use IEEE.std_logic_1164.all; use IEEE.NUMERIC_STD.all; entity alt_dspbuilder_decoder is generic ( DECODE : string := "00000000"; PIPELINE : natural := 0; WIDTH : natural := 8 ); port ( dec : out std_logic; clock : in std_logic := '0'; sclr : in std_logic := '0'; data : in std_logic_vector(width-1 downto 0) := (others=>'0'); aclr : in std_logic := '0'; ena : in std_logic := '0' ); end entity alt_dspbuilder_decoder; architecture rtl of alt_dspbuilder_decoder is component alt_dspbuilder_decoder_GNSCEXJCJK is generic ( DECODE : string := "000000000000000000001111"; PIPELINE : natural := 0; WIDTH : natural := 24 ); port ( aclr : in std_logic := '0'; clock : in std_logic := '0'; data : in std_logic_vector(24-1 downto 0) := (others=>'0'); dec : out std_logic; ena : in std_logic := '0'; sclr : in std_logic := '0' ); end component alt_dspbuilder_decoder_GNSCEXJCJK; component alt_dspbuilder_decoder_GNM4LOIHXZ is generic ( DECODE : string := "01"; PIPELINE : natural := 1; WIDTH : natural := 2 ); port ( aclr : in std_logic := '0'; clock : in std_logic := '0'; data : in std_logic_vector(2-1 downto 0) := (others=>'0'); dec : out std_logic; ena : in std_logic := '0'; sclr : in std_logic := '0' ); end component alt_dspbuilder_decoder_GNM4LOIHXZ; begin alt_dspbuilder_decoder_GNSCEXJCJK_0: if ((DECODE = "000000000000000000001111") and (PIPELINE = 0) and (WIDTH = 24)) generate inst_alt_dspbuilder_decoder_GNSCEXJCJK_0: alt_dspbuilder_decoder_GNSCEXJCJK generic map(DECODE => "000000000000000000001111", PIPELINE => 0, WIDTH => 24) port map(aclr => aclr, clock => clock, data => data, dec => dec, ena => ena, sclr => sclr); end generate; alt_dspbuilder_decoder_GNM4LOIHXZ_1: if ((DECODE = "01") and (PIPELINE = 1) and (WIDTH = 2)) generate inst_alt_dspbuilder_decoder_GNM4LOIHXZ_1: alt_dspbuilder_decoder_GNM4LOIHXZ generic map(DECODE => "01", PIPELINE => 1, WIDTH => 2) port map(aclr => aclr, clock => clock, data => data, dec => dec, ena => ena, sclr => sclr); end generate; assert not (((DECODE = "000000000000000000001111") and (PIPELINE = 0) and (WIDTH = 24)) or ((DECODE = "01") and (PIPELINE = 1) and (WIDTH = 2))) report "Please run generate again" severity error; end architecture rtl;
mit
9d1a2bb14a5395c203a0168b6b8ab851
0.666536
3.238276
false
false
false
false
wsoltys/AtomFpga
src/AtomGodilVideo/src/VGA80x40/ctrm.vhd
1
2,085
-- Hi Emacs, this is -*- mode: vhdl; -*- ---------------------------------------------------------------------------------------------------- -- -- Up Syncronous counter of N bits with a/syncronous reset -- -- Copyright (c) 2007 Javier Valcarce García, [email protected] -- $Id$ -- ---------------------------------------------------------------------------------------------------- -- This program is free software: you can redistribute it and/or modify -- it under the terms of the GNU Lesser General Public License as published by -- the Free Software Foundation, either version 3 of the License, or -- (at your option) any later version. -- This program is distributed in the hope that it will be useful, -- but WITHOUT ANY WARRANTY; without even the implied warranty of -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -- GNU Lesser General Public License for more details. -- -- You should have received a copy of the GNU Lesser General Public License -- along with this program. If not, see <http://www.gnu.org/licenses/>. ---------------------------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity ctrm is generic ( M : integer := 08); port ( reset : in std_logic; -- asyncronous reset clk : in std_logic; ce : in std_logic; -- enable counting rs : in std_logic; -- syncronous reset do : out integer range (M-1) downto 0 ); end ctrm; ------------------------------------------------------------------------------- ------------------------------------------------------------------------------- architecture arch of ctrm is signal c : integer range (M-1) downto 0; begin do <= c; process(reset, clk) begin if reset = '1' then c <= 0; elsif rising_edge(clk) then if ce = '1' then if rs = '1' then c <= 0; else c <= c + 1; end if; end if; end if; end process; end arch;
apache-2.0
978e2baed37ff445b328ed29e0fe4299
0.489209
4.582418
false
false
false
false
TWW12/lzw
final_project_sim/lzw/lzw.cache/ip/1ef49ae738cde1e4/bram_2048_0_sim_netlist.vhdl
1
63,423
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved. -- -------------------------------------------------------------------------------- -- Tool Version: Vivado v.2016.4 (win64) Build 1756540 Mon Jan 23 19:11:23 MST 2017 -- Date : Tue Apr 18 23:15:16 2017 -- Host : DESKTOP-I9J3TQJ running 64-bit major release (build 9200) -- Command : write_vhdl -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix -- decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ bram_2048_0_sim_netlist.vhdl -- Design : bram_2048_0 -- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or -- synthesized. This netlist cannot be used for SDF annotated simulation. -- Device : xc7z020clg484-1 -- -------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper_init is port ( douta : out STD_LOGIC_VECTOR ( 8 downto 0 ); clka : in STD_LOGIC; ena : in STD_LOGIC; addra : in STD_LOGIC_VECTOR ( 10 downto 0 ); dina : in STD_LOGIC_VECTOR ( 8 downto 0 ); wea : in STD_LOGIC_VECTOR ( 0 to 0 ) ); end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper_init; architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper_init is signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 15 downto 8 ); signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 15 downto 0 ); signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 to 1 ); signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 ); attribute CLOCK_DOMAINS : string; attribute CLOCK_DOMAINS of \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram\ : label is "COMMON"; attribute box_type : string; attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram\ : label is "PRIMITIVE"; begin \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram\: unisim.vcomponents.RAMB18E1 generic map( DOA_REG => 1, DOB_REG => 0, INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_00 => X"3F3D3B39373533312F2D2B29272523211F1D1B19171513110F0D0B0907050301", INIT_01 => X"7F7D7B79777573716F6D6B69676563615F5D5B59575553514F4D4B4947454341", INIT_02 => X"BFBDBBB9B7B5B3B1AFADABA9A7A5A3A19F9D9B99979593918F8D8B8987858381", INIT_03 => X"FFFDFBF9F7F5F3F1EFEDEBE9E7E5E3E1DFDDDBD9D7D5D3D1CFCDCBC9C7C5C3C1", INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_A => X"00000", INIT_B => X"00000", INIT_FILE => "NONE", IS_CLKARDCLK_INVERTED => '0', IS_CLKBWRCLK_INVERTED => '0', IS_ENARDEN_INVERTED => '0', IS_ENBWREN_INVERTED => '0', IS_RSTRAMARSTRAM_INVERTED => '0', IS_RSTRAMB_INVERTED => '0', IS_RSTREGARSTREG_INVERTED => '0', IS_RSTREGB_INVERTED => '0', RAM_MODE => "TDP", RDADDR_COLLISION_HWCONFIG => "PERFORMANCE", READ_WIDTH_A => 9, READ_WIDTH_B => 9, RSTREG_PRIORITY_A => "REGCE", RSTREG_PRIORITY_B => "REGCE", SIM_COLLISION_CHECK => "ALL", SIM_DEVICE => "7SERIES", SRVAL_A => X"00000", SRVAL_B => X"00000", WRITE_MODE_A => "WRITE_FIRST", WRITE_MODE_B => "WRITE_FIRST", WRITE_WIDTH_A => 9, WRITE_WIDTH_B => 9 ) port map ( ADDRARDADDR(13 downto 3) => addra(10 downto 0), ADDRARDADDR(2 downto 0) => B"000", ADDRBWRADDR(13 downto 0) => B"00000000000000", CLKARDCLK => clka, CLKBWRCLK => clka, DIADI(15 downto 8) => B"00000000", DIADI(7 downto 0) => dina(7 downto 0), DIBDI(15 downto 0) => B"0000000000000000", DIPADIP(1) => '0', DIPADIP(0) => dina(8), DIPBDIP(1 downto 0) => B"00", DOADO(15 downto 8) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_DOADO_UNCONNECTED\(15 downto 8), DOADO(7 downto 0) => douta(7 downto 0), DOBDO(15 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_DOBDO_UNCONNECTED\(15 downto 0), DOPADOP(1) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_DOPADOP_UNCONNECTED\(1), DOPADOP(0) => douta(8), DOPBDOP(1 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_DOPBDOP_UNCONNECTED\(1 downto 0), ENARDEN => ena, ENBWREN => '0', REGCEAREGCE => ena, REGCEB => '0', RSTRAMARSTRAM => '0', RSTRAMB => '0', RSTREGARSTREG => '0', RSTREGB => '0', WEA(1) => wea(0), WEA(0) => wea(0), WEBWE(3 downto 0) => B"0000" ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper_init__parameterized0\ is port ( douta : out STD_LOGIC_VECTOR ( 10 downto 0 ); clka : in STD_LOGIC; ena : in STD_LOGIC; addra : in STD_LOGIC_VECTOR ( 10 downto 0 ); dina : in STD_LOGIC_VECTOR ( 10 downto 0 ); wea : in STD_LOGIC_VECTOR ( 0 to 0 ) ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper_init__parameterized0\ : entity is "blk_mem_gen_prim_wrapper_init"; end \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper_init__parameterized0\; architecture STRUCTURE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper_init__parameterized0\ is signal \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_37\ : STD_LOGIC; signal \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_38\ : STD_LOGIC; signal \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_39\ : STD_LOGIC; signal \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_45\ : STD_LOGIC; signal \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_46\ : STD_LOGIC; signal \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_87\ : STD_LOGIC; signal \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_88\ : STD_LOGIC; signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC; signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC; signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\ : STD_LOGIC; signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\ : STD_LOGIC; signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 16 ); signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 ); signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 ); signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 ); signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 ); attribute CLOCK_DOMAINS : string; attribute CLOCK_DOMAINS of \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\ : label is "COMMON"; attribute box_type : string; attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\ : label is "PRIMITIVE"; begin \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\: unisim.vcomponents.RAMB36E1 generic map( DOA_REG => 1, DOB_REG => 0, EN_ECC_READ => false, EN_ECC_WRITE => false, INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_08 => 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X"0000000000000000000000000000000000000000000000000000000000000000", INIT_59 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_5A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_5B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_5C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_5D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_5E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_5F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_60 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_61 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_62 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_63 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_64 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_65 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_66 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_67 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_68 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_69 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_6A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_6B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_6D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_6E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_6F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_70 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_71 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_72 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_73 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_74 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_A => X"000000000", INIT_B => X"000000000", INIT_FILE => "NONE", IS_CLKARDCLK_INVERTED => '0', IS_CLKBWRCLK_INVERTED => '0', IS_ENARDEN_INVERTED => '0', IS_ENBWREN_INVERTED => '0', IS_RSTRAMARSTRAM_INVERTED => '0', IS_RSTRAMB_INVERTED => '0', IS_RSTREGARSTREG_INVERTED => '0', IS_RSTREGB_INVERTED => '0', RAM_EXTENSION_A => "NONE", RAM_EXTENSION_B => "NONE", RAM_MODE => "TDP", RDADDR_COLLISION_HWCONFIG => "PERFORMANCE", READ_WIDTH_A => 18, READ_WIDTH_B => 18, RSTREG_PRIORITY_A => "REGCE", RSTREG_PRIORITY_B => "REGCE", SIM_COLLISION_CHECK => "ALL", SIM_DEVICE => "7SERIES", SRVAL_A => X"000000000", SRVAL_B => X"000000000", WRITE_MODE_A => "WRITE_FIRST", WRITE_MODE_B => "WRITE_FIRST", WRITE_WIDTH_A => 18, WRITE_WIDTH_B => 18 ) port map ( ADDRARDADDR(15) => '1', ADDRARDADDR(14 downto 4) => addra(10 downto 0), ADDRARDADDR(3 downto 0) => B"1111", ADDRBWRADDR(15 downto 0) => B"0000000000000000", CASCADEINA => '0', CASCADEINB => '0', CASCADEOUTA => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\, CASCADEOUTB => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\, CLKARDCLK => clka, CLKBWRCLK => clka, DBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\, DIADI(31 downto 13) => B"0000000000000000000", DIADI(12 downto 8) => dina(10 downto 6), DIADI(7 downto 6) => B"00", DIADI(5 downto 0) => dina(5 downto 0), DIBDI(31 downto 0) => B"00000000000000000000000000000000", DIPADIP(3 downto 0) => B"0000", DIPBDIP(3 downto 0) => B"0000", DOADO(31 downto 16) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\(31 downto 16), DOADO(15) => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_37\, DOADO(14) => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_38\, DOADO(13) => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_39\, DOADO(12 downto 8) => douta(10 downto 6), DOADO(7) => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_45\, DOADO(6) => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_46\, DOADO(5 downto 0) => douta(5 downto 0), DOBDO(31 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\(31 downto 0), DOPADOP(3 downto 2) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\(3 downto 2), DOPADOP(1) => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_87\, DOPADOP(0) => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_88\, DOPBDOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\(3 downto 0), ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\(7 downto 0), ENARDEN => ena, ENBWREN => '0', INJECTDBITERR => '0', INJECTSBITERR => '0', RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\(8 downto 0), REGCEAREGCE => ena, REGCEB => '0', RSTRAMARSTRAM => '0', RSTRAMB => '0', RSTREGARSTREG => '0', RSTREGB => '0', SBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\, WEA(3) => wea(0), WEA(2) => wea(0), WEA(1) => wea(0), WEA(0) => wea(0), WEBWE(7 downto 0) => B"00000000" ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width is port ( douta : out STD_LOGIC_VECTOR ( 8 downto 0 ); clka : in STD_LOGIC; ena : in STD_LOGIC; addra : in STD_LOGIC_VECTOR ( 10 downto 0 ); dina : in STD_LOGIC_VECTOR ( 8 downto 0 ); wea : in STD_LOGIC_VECTOR ( 0 to 0 ) ); end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width; architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width is begin \prim_init.ram\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper_init port map ( addra(10 downto 0) => addra(10 downto 0), clka => clka, dina(8 downto 0) => dina(8 downto 0), douta(8 downto 0) => douta(8 downto 0), ena => ena, wea(0) => wea(0) ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized0\ is port ( douta : out STD_LOGIC_VECTOR ( 10 downto 0 ); clka : in STD_LOGIC; ena : in STD_LOGIC; addra : in STD_LOGIC_VECTOR ( 10 downto 0 ); dina : in STD_LOGIC_VECTOR ( 10 downto 0 ); wea : in STD_LOGIC_VECTOR ( 0 to 0 ) ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized0\ : entity is "blk_mem_gen_prim_width"; end \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized0\; architecture STRUCTURE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized0\ is begin \prim_init.ram\: entity work.\decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper_init__parameterized0\ port map ( addra(10 downto 0) => addra(10 downto 0), clka => clka, dina(10 downto 0) => dina(10 downto 0), douta(10 downto 0) => douta(10 downto 0), ena => ena, wea(0) => wea(0) ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_generic_cstr is port ( douta : out STD_LOGIC_VECTOR ( 19 downto 0 ); clka : in STD_LOGIC; ena : in STD_LOGIC; addra : in STD_LOGIC_VECTOR ( 10 downto 0 ); dina : in STD_LOGIC_VECTOR ( 19 downto 0 ); wea : in STD_LOGIC_VECTOR ( 0 to 0 ) ); end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_generic_cstr; architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_generic_cstr is begin \ramloop[0].ram.r\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width port map ( addra(10 downto 0) => addra(10 downto 0), clka => clka, dina(8 downto 0) => dina(8 downto 0), douta(8 downto 0) => douta(8 downto 0), ena => ena, wea(0) => wea(0) ); \ramloop[1].ram.r\: entity work.\decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized0\ port map ( addra(10 downto 0) => addra(10 downto 0), clka => clka, dina(10 downto 0) => dina(19 downto 9), douta(10 downto 0) => douta(19 downto 9), ena => ena, wea(0) => wea(0) ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_top is port ( douta : out STD_LOGIC_VECTOR ( 19 downto 0 ); clka : in STD_LOGIC; ena : in STD_LOGIC; addra : in STD_LOGIC_VECTOR ( 10 downto 0 ); dina : in STD_LOGIC_VECTOR ( 19 downto 0 ); wea : in STD_LOGIC_VECTOR ( 0 to 0 ) ); end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_top; architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_top is begin \valid.cstr\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_generic_cstr port map ( addra(10 downto 0) => addra(10 downto 0), clka => clka, dina(19 downto 0) => dina(19 downto 0), douta(19 downto 0) => douta(19 downto 0), ena => ena, wea(0) => wea(0) ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5_synth is port ( douta : out STD_LOGIC_VECTOR ( 19 downto 0 ); clka : in STD_LOGIC; ena : in STD_LOGIC; addra : in STD_LOGIC_VECTOR ( 10 downto 0 ); dina : in STD_LOGIC_VECTOR ( 19 downto 0 ); wea : in STD_LOGIC_VECTOR ( 0 to 0 ) ); end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5_synth; architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5_synth is begin \gnbram.gnativebmg.native_blk_mem_gen\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_top port map ( addra(10 downto 0) => addra(10 downto 0), clka => clka, dina(19 downto 0) => dina(19 downto 0), douta(19 downto 0) => douta(19 downto 0), ena => ena, wea(0) => wea(0) ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 is port ( clka : in STD_LOGIC; rsta : in STD_LOGIC; ena : in STD_LOGIC; regcea : in STD_LOGIC; wea : in STD_LOGIC_VECTOR ( 0 to 0 ); addra : in STD_LOGIC_VECTOR ( 10 downto 0 ); dina : in STD_LOGIC_VECTOR ( 19 downto 0 ); douta : out STD_LOGIC_VECTOR ( 19 downto 0 ); clkb : in STD_LOGIC; rstb : in STD_LOGIC; enb : in STD_LOGIC; regceb : in STD_LOGIC; web : in STD_LOGIC_VECTOR ( 0 to 0 ); addrb : in STD_LOGIC_VECTOR ( 10 downto 0 ); dinb : in STD_LOGIC_VECTOR ( 19 downto 0 ); doutb : out STD_LOGIC_VECTOR ( 19 downto 0 ); injectsbiterr : in STD_LOGIC; injectdbiterr : in STD_LOGIC; eccpipece : in STD_LOGIC; sbiterr : out STD_LOGIC; dbiterr : out STD_LOGIC; rdaddrecc : out STD_LOGIC_VECTOR ( 10 downto 0 ); sleep : in STD_LOGIC; deepsleep : in STD_LOGIC; shutdown : in STD_LOGIC; rsta_busy : out STD_LOGIC; rstb_busy : out STD_LOGIC; s_aclk : in STD_LOGIC; s_aresetn : in STD_LOGIC; s_axi_awid : in STD_LOGIC_VECTOR ( 3 downto 0 ); s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 ); s_axi_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 ); s_axi_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 ); s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 ); s_axi_awvalid : in STD_LOGIC; s_axi_awready : out STD_LOGIC; s_axi_wdata : in STD_LOGIC_VECTOR ( 19 downto 0 ); s_axi_wstrb : in STD_LOGIC_VECTOR ( 0 to 0 ); s_axi_wlast : in STD_LOGIC; s_axi_wvalid : in STD_LOGIC; s_axi_wready : out STD_LOGIC; s_axi_bid : out STD_LOGIC_VECTOR ( 3 downto 0 ); s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 ); s_axi_bvalid : out STD_LOGIC; s_axi_bready : in STD_LOGIC; s_axi_arid : in STD_LOGIC_VECTOR ( 3 downto 0 ); s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 ); s_axi_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 ); s_axi_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 ); s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 ); s_axi_arvalid : in STD_LOGIC; s_axi_arready : out STD_LOGIC; s_axi_rid : out STD_LOGIC_VECTOR ( 3 downto 0 ); s_axi_rdata : out STD_LOGIC_VECTOR ( 19 downto 0 ); s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 ); s_axi_rlast : out STD_LOGIC; s_axi_rvalid : out STD_LOGIC; s_axi_rready : in STD_LOGIC; s_axi_injectsbiterr : in STD_LOGIC; s_axi_injectdbiterr : in STD_LOGIC; s_axi_sbiterr : out STD_LOGIC; s_axi_dbiterr : out STD_LOGIC; s_axi_rdaddrecc : out STD_LOGIC_VECTOR ( 10 downto 0 ) ); attribute C_ADDRA_WIDTH : integer; attribute C_ADDRA_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is 11; attribute C_ADDRB_WIDTH : integer; attribute C_ADDRB_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is 11; attribute C_ALGORITHM : integer; attribute C_ALGORITHM of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is 1; attribute C_AXI_ID_WIDTH : integer; attribute C_AXI_ID_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is 4; attribute C_AXI_SLAVE_TYPE : integer; attribute C_AXI_SLAVE_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is 0; attribute C_AXI_TYPE : integer; attribute C_AXI_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is 1; attribute C_BYTE_SIZE : integer; attribute C_BYTE_SIZE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is 9; attribute C_COMMON_CLK : integer; attribute C_COMMON_CLK of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is 0; attribute C_COUNT_18K_BRAM : string; attribute C_COUNT_18K_BRAM of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is "1"; attribute C_COUNT_36K_BRAM : string; attribute C_COUNT_36K_BRAM of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is "1"; attribute C_CTRL_ECC_ALGO : string; attribute C_CTRL_ECC_ALGO of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is "NONE"; attribute C_DEFAULT_DATA : string; attribute C_DEFAULT_DATA of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is "0"; attribute C_DISABLE_WARN_BHV_COLL : integer; attribute C_DISABLE_WARN_BHV_COLL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is 0; attribute C_DISABLE_WARN_BHV_RANGE : integer; attribute C_DISABLE_WARN_BHV_RANGE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is 0; attribute C_ELABORATION_DIR : string; attribute C_ELABORATION_DIR of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is "./"; attribute C_ENABLE_32BIT_ADDRESS : integer; attribute C_ENABLE_32BIT_ADDRESS of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is 0; attribute C_EN_DEEPSLEEP_PIN : integer; attribute C_EN_DEEPSLEEP_PIN of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is 0; attribute C_EN_ECC_PIPE : integer; attribute C_EN_ECC_PIPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is 0; attribute C_EN_RDADDRA_CHG : integer; attribute C_EN_RDADDRA_CHG of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is 0; attribute C_EN_RDADDRB_CHG : integer; attribute C_EN_RDADDRB_CHG of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is 0; attribute C_EN_SAFETY_CKT : integer; attribute C_EN_SAFETY_CKT of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is 0; attribute C_EN_SHUTDOWN_PIN : integer; attribute C_EN_SHUTDOWN_PIN of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is 0; attribute C_EN_SLEEP_PIN : integer; attribute C_EN_SLEEP_PIN of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is 0; attribute C_EST_POWER_SUMMARY : string; attribute C_EST_POWER_SUMMARY of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is "Estimated Power for IP : 3.9373 mW"; attribute C_FAMILY : string; attribute C_FAMILY of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is "zynq"; attribute C_HAS_AXI_ID : integer; attribute C_HAS_AXI_ID of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is 0; attribute C_HAS_ENA : integer; attribute C_HAS_ENA of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is 1; attribute C_HAS_ENB : integer; attribute C_HAS_ENB of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is 0; attribute C_HAS_INJECTERR : integer; attribute C_HAS_INJECTERR of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is 0; attribute C_HAS_MEM_OUTPUT_REGS_A : integer; attribute C_HAS_MEM_OUTPUT_REGS_A of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is 1; attribute C_HAS_MEM_OUTPUT_REGS_B : integer; attribute C_HAS_MEM_OUTPUT_REGS_B of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is 0; attribute C_HAS_MUX_OUTPUT_REGS_A : integer; attribute C_HAS_MUX_OUTPUT_REGS_A of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is 0; attribute C_HAS_MUX_OUTPUT_REGS_B : integer; attribute C_HAS_MUX_OUTPUT_REGS_B of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is 0; attribute C_HAS_REGCEA : integer; attribute C_HAS_REGCEA of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is 0; attribute C_HAS_REGCEB : integer; attribute C_HAS_REGCEB of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is 0; attribute C_HAS_RSTA : integer; attribute C_HAS_RSTA of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is 0; attribute C_HAS_RSTB : integer; attribute C_HAS_RSTB of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is 0; attribute C_HAS_SOFTECC_INPUT_REGS_A : integer; attribute C_HAS_SOFTECC_INPUT_REGS_A of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is 0; attribute C_HAS_SOFTECC_OUTPUT_REGS_B : integer; attribute C_HAS_SOFTECC_OUTPUT_REGS_B of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is 0; attribute C_INITA_VAL : string; attribute C_INITA_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is "0"; attribute C_INITB_VAL : string; attribute C_INITB_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is "0"; attribute C_INIT_FILE : string; attribute C_INIT_FILE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is "bram_2048_0.mem"; attribute C_INIT_FILE_NAME : string; attribute C_INIT_FILE_NAME of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is "bram_2048_0.mif"; attribute C_INTERFACE_TYPE : integer; attribute C_INTERFACE_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is 0; attribute C_LOAD_INIT_FILE : integer; attribute C_LOAD_INIT_FILE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is 1; attribute C_MEM_TYPE : integer; attribute C_MEM_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is 0; attribute C_MUX_PIPELINE_STAGES : integer; attribute C_MUX_PIPELINE_STAGES of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is 0; attribute C_PRIM_TYPE : integer; attribute C_PRIM_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is 1; attribute C_READ_DEPTH_A : integer; attribute C_READ_DEPTH_A of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is 2048; attribute C_READ_DEPTH_B : integer; attribute C_READ_DEPTH_B of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is 2048; attribute C_READ_WIDTH_A : integer; attribute C_READ_WIDTH_A of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is 20; attribute C_READ_WIDTH_B : integer; attribute C_READ_WIDTH_B of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is 20; attribute C_RSTRAM_A : integer; attribute C_RSTRAM_A of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is 0; attribute C_RSTRAM_B : integer; attribute C_RSTRAM_B of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is 0; attribute C_RST_PRIORITY_A : string; attribute C_RST_PRIORITY_A of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is "CE"; attribute C_RST_PRIORITY_B : string; attribute C_RST_PRIORITY_B of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is "CE"; attribute C_SIM_COLLISION_CHECK : string; attribute C_SIM_COLLISION_CHECK of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is "ALL"; attribute C_USE_BRAM_BLOCK : integer; attribute C_USE_BRAM_BLOCK of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is 0; attribute C_USE_BYTE_WEA : integer; attribute C_USE_BYTE_WEA of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is 0; attribute C_USE_BYTE_WEB : integer; attribute C_USE_BYTE_WEB of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is 0; attribute C_USE_DEFAULT_DATA : integer; attribute C_USE_DEFAULT_DATA of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is 0; attribute C_USE_ECC : integer; attribute C_USE_ECC of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is 0; attribute C_USE_SOFTECC : integer; attribute C_USE_SOFTECC of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is 0; attribute C_USE_URAM : integer; attribute C_USE_URAM of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is 0; attribute C_WEA_WIDTH : integer; attribute C_WEA_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is 1; attribute C_WEB_WIDTH : integer; attribute C_WEB_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is 1; attribute C_WRITE_DEPTH_A : integer; attribute C_WRITE_DEPTH_A of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is 2048; attribute C_WRITE_DEPTH_B : integer; attribute C_WRITE_DEPTH_B of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is 2048; attribute C_WRITE_MODE_A : string; attribute C_WRITE_MODE_A of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is "WRITE_FIRST"; attribute C_WRITE_MODE_B : string; attribute C_WRITE_MODE_B of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is "WRITE_FIRST"; attribute C_WRITE_WIDTH_A : integer; attribute C_WRITE_WIDTH_A of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is 20; attribute C_WRITE_WIDTH_B : integer; attribute C_WRITE_WIDTH_B of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is 20; attribute C_XDEVICEFAMILY : string; attribute C_XDEVICEFAMILY of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is "zynq"; attribute downgradeipidentifiedwarnings : string; attribute downgradeipidentifiedwarnings of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is "yes"; end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5; architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 is signal \<const0>\ : STD_LOGIC; begin dbiterr <= \<const0>\; doutb(19) <= \<const0>\; doutb(18) <= \<const0>\; doutb(17) <= \<const0>\; doutb(16) <= \<const0>\; doutb(15) <= \<const0>\; doutb(14) <= \<const0>\; doutb(13) <= \<const0>\; doutb(12) <= \<const0>\; doutb(11) <= \<const0>\; doutb(10) <= \<const0>\; doutb(9) <= \<const0>\; doutb(8) <= \<const0>\; doutb(7) <= \<const0>\; doutb(6) <= \<const0>\; doutb(5) <= \<const0>\; doutb(4) <= \<const0>\; doutb(3) <= \<const0>\; doutb(2) <= \<const0>\; doutb(1) <= \<const0>\; doutb(0) <= \<const0>\; rdaddrecc(10) <= \<const0>\; rdaddrecc(9) <= \<const0>\; rdaddrecc(8) <= \<const0>\; rdaddrecc(7) <= \<const0>\; rdaddrecc(6) <= \<const0>\; rdaddrecc(5) <= \<const0>\; rdaddrecc(4) <= \<const0>\; rdaddrecc(3) <= \<const0>\; rdaddrecc(2) <= \<const0>\; rdaddrecc(1) <= \<const0>\; rdaddrecc(0) <= \<const0>\; rsta_busy <= \<const0>\; rstb_busy <= \<const0>\; s_axi_arready <= \<const0>\; s_axi_awready <= \<const0>\; s_axi_bid(3) <= \<const0>\; s_axi_bid(2) <= \<const0>\; s_axi_bid(1) <= \<const0>\; s_axi_bid(0) <= \<const0>\; s_axi_bresp(1) <= \<const0>\; s_axi_bresp(0) <= \<const0>\; s_axi_bvalid <= \<const0>\; s_axi_dbiterr <= \<const0>\; s_axi_rdaddrecc(10) <= \<const0>\; s_axi_rdaddrecc(9) <= \<const0>\; s_axi_rdaddrecc(8) <= \<const0>\; s_axi_rdaddrecc(7) <= \<const0>\; s_axi_rdaddrecc(6) <= \<const0>\; s_axi_rdaddrecc(5) <= \<const0>\; s_axi_rdaddrecc(4) <= \<const0>\; s_axi_rdaddrecc(3) <= \<const0>\; s_axi_rdaddrecc(2) <= \<const0>\; s_axi_rdaddrecc(1) <= \<const0>\; s_axi_rdaddrecc(0) <= \<const0>\; s_axi_rdata(19) <= \<const0>\; s_axi_rdata(18) <= \<const0>\; s_axi_rdata(17) <= \<const0>\; s_axi_rdata(16) <= \<const0>\; s_axi_rdata(15) <= \<const0>\; s_axi_rdata(14) <= \<const0>\; s_axi_rdata(13) <= \<const0>\; s_axi_rdata(12) <= \<const0>\; s_axi_rdata(11) <= \<const0>\; s_axi_rdata(10) <= \<const0>\; s_axi_rdata(9) <= \<const0>\; s_axi_rdata(8) <= \<const0>\; s_axi_rdata(7) <= \<const0>\; s_axi_rdata(6) <= \<const0>\; s_axi_rdata(5) <= \<const0>\; s_axi_rdata(4) <= \<const0>\; s_axi_rdata(3) <= \<const0>\; s_axi_rdata(2) <= \<const0>\; s_axi_rdata(1) <= \<const0>\; s_axi_rdata(0) <= \<const0>\; s_axi_rid(3) <= \<const0>\; s_axi_rid(2) <= \<const0>\; s_axi_rid(1) <= \<const0>\; s_axi_rid(0) <= \<const0>\; s_axi_rlast <= \<const0>\; s_axi_rresp(1) <= \<const0>\; s_axi_rresp(0) <= \<const0>\; s_axi_rvalid <= \<const0>\; s_axi_sbiterr <= \<const0>\; s_axi_wready <= \<const0>\; sbiterr <= \<const0>\; GND: unisim.vcomponents.GND port map ( G => \<const0>\ ); inst_blk_mem_gen: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5_synth port map ( addra(10 downto 0) => addra(10 downto 0), clka => clka, dina(19 downto 0) => dina(19 downto 0), douta(19 downto 0) => douta(19 downto 0), ena => ena, wea(0) => wea(0) ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is port ( clka : in STD_LOGIC; ena : in STD_LOGIC; wea : in STD_LOGIC_VECTOR ( 0 to 0 ); addra : in STD_LOGIC_VECTOR ( 10 downto 0 ); dina : in STD_LOGIC_VECTOR ( 19 downto 0 ); douta : out STD_LOGIC_VECTOR ( 19 downto 0 ) ); attribute NotValidForBitStream : boolean; attribute NotValidForBitStream of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is true; attribute CHECK_LICENSE_TYPE : string; attribute CHECK_LICENSE_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "bram_2048_0,blk_mem_gen_v8_3_5,{}"; attribute downgradeipidentifiedwarnings : string; attribute downgradeipidentifiedwarnings of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "yes"; attribute x_core_info : string; attribute x_core_info of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "blk_mem_gen_v8_3_5,Vivado 2016.4"; end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix; architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is signal NLW_U0_dbiterr_UNCONNECTED : STD_LOGIC; signal NLW_U0_rsta_busy_UNCONNECTED : STD_LOGIC; signal NLW_U0_rstb_busy_UNCONNECTED : STD_LOGIC; signal NLW_U0_s_axi_arready_UNCONNECTED : STD_LOGIC; signal NLW_U0_s_axi_awready_UNCONNECTED : STD_LOGIC; signal NLW_U0_s_axi_bvalid_UNCONNECTED : STD_LOGIC; signal NLW_U0_s_axi_dbiterr_UNCONNECTED : STD_LOGIC; signal NLW_U0_s_axi_rlast_UNCONNECTED : STD_LOGIC; signal NLW_U0_s_axi_rvalid_UNCONNECTED : STD_LOGIC; signal NLW_U0_s_axi_sbiterr_UNCONNECTED : STD_LOGIC; signal NLW_U0_s_axi_wready_UNCONNECTED : STD_LOGIC; signal NLW_U0_sbiterr_UNCONNECTED : STD_LOGIC; signal NLW_U0_doutb_UNCONNECTED : STD_LOGIC_VECTOR ( 19 downto 0 ); signal NLW_U0_rdaddrecc_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 ); signal NLW_U0_s_axi_bid_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 ); signal NLW_U0_s_axi_bresp_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 ); signal NLW_U0_s_axi_rdaddrecc_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 ); signal NLW_U0_s_axi_rdata_UNCONNECTED : STD_LOGIC_VECTOR ( 19 downto 0 ); signal NLW_U0_s_axi_rid_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 ); signal NLW_U0_s_axi_rresp_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 ); attribute C_ADDRA_WIDTH : integer; attribute C_ADDRA_WIDTH of U0 : label is 11; attribute C_ADDRB_WIDTH : integer; attribute C_ADDRB_WIDTH of U0 : label is 11; attribute C_ALGORITHM : integer; attribute C_ALGORITHM of U0 : label is 1; attribute C_AXI_ID_WIDTH : integer; attribute C_AXI_ID_WIDTH of U0 : label is 4; attribute C_AXI_SLAVE_TYPE : integer; attribute C_AXI_SLAVE_TYPE of U0 : label is 0; attribute C_AXI_TYPE : integer; attribute C_AXI_TYPE of U0 : label is 1; attribute C_BYTE_SIZE : integer; attribute C_BYTE_SIZE of U0 : label is 9; attribute C_COMMON_CLK : integer; attribute C_COMMON_CLK of U0 : label is 0; attribute C_COUNT_18K_BRAM : string; attribute C_COUNT_18K_BRAM of U0 : label is "1"; attribute C_COUNT_36K_BRAM : string; attribute C_COUNT_36K_BRAM of U0 : label is "1"; attribute C_CTRL_ECC_ALGO : string; attribute C_CTRL_ECC_ALGO of U0 : label is "NONE"; attribute C_DEFAULT_DATA : string; attribute C_DEFAULT_DATA of U0 : label is "0"; attribute C_DISABLE_WARN_BHV_COLL : integer; attribute C_DISABLE_WARN_BHV_COLL of U0 : label is 0; attribute C_DISABLE_WARN_BHV_RANGE : integer; attribute C_DISABLE_WARN_BHV_RANGE of U0 : label is 0; attribute C_ELABORATION_DIR : string; attribute C_ELABORATION_DIR of U0 : label is "./"; attribute C_ENABLE_32BIT_ADDRESS : integer; attribute C_ENABLE_32BIT_ADDRESS of U0 : label is 0; attribute C_EN_DEEPSLEEP_PIN : integer; attribute C_EN_DEEPSLEEP_PIN of U0 : label is 0; attribute C_EN_ECC_PIPE : integer; attribute C_EN_ECC_PIPE of U0 : label is 0; attribute C_EN_RDADDRA_CHG : integer; attribute C_EN_RDADDRA_CHG of U0 : label is 0; attribute C_EN_RDADDRB_CHG : integer; attribute C_EN_RDADDRB_CHG of U0 : label is 0; attribute C_EN_SAFETY_CKT : integer; attribute C_EN_SAFETY_CKT of U0 : label is 0; attribute C_EN_SHUTDOWN_PIN : integer; attribute C_EN_SHUTDOWN_PIN of U0 : label is 0; attribute C_EN_SLEEP_PIN : integer; attribute C_EN_SLEEP_PIN of U0 : label is 0; attribute C_EST_POWER_SUMMARY : string; attribute C_EST_POWER_SUMMARY of U0 : label is "Estimated Power for IP : 3.9373 mW"; attribute C_FAMILY : string; attribute C_FAMILY of U0 : label is "zynq"; attribute C_HAS_AXI_ID : integer; attribute C_HAS_AXI_ID of U0 : label is 0; attribute C_HAS_ENA : integer; attribute C_HAS_ENA of U0 : label is 1; attribute C_HAS_ENB : integer; attribute C_HAS_ENB of U0 : label is 0; attribute C_HAS_INJECTERR : integer; attribute C_HAS_INJECTERR of U0 : label is 0; attribute C_HAS_MEM_OUTPUT_REGS_A : integer; attribute C_HAS_MEM_OUTPUT_REGS_A of U0 : label is 1; attribute C_HAS_MEM_OUTPUT_REGS_B : integer; attribute C_HAS_MEM_OUTPUT_REGS_B of U0 : label is 0; attribute C_HAS_MUX_OUTPUT_REGS_A : integer; attribute C_HAS_MUX_OUTPUT_REGS_A of U0 : label is 0; attribute C_HAS_MUX_OUTPUT_REGS_B : integer; attribute C_HAS_MUX_OUTPUT_REGS_B of U0 : label is 0; attribute C_HAS_REGCEA : integer; attribute C_HAS_REGCEA of U0 : label is 0; attribute C_HAS_REGCEB : integer; attribute C_HAS_REGCEB of U0 : label is 0; attribute C_HAS_RSTA : integer; attribute C_HAS_RSTA of U0 : label is 0; attribute C_HAS_RSTB : integer; attribute C_HAS_RSTB of U0 : label is 0; attribute C_HAS_SOFTECC_INPUT_REGS_A : integer; attribute C_HAS_SOFTECC_INPUT_REGS_A of U0 : label is 0; attribute C_HAS_SOFTECC_OUTPUT_REGS_B : integer; attribute C_HAS_SOFTECC_OUTPUT_REGS_B of U0 : label is 0; attribute C_INITA_VAL : string; attribute C_INITA_VAL of U0 : label is "0"; attribute C_INITB_VAL : string; attribute C_INITB_VAL of U0 : label is "0"; attribute C_INIT_FILE : string; attribute C_INIT_FILE of U0 : label is "bram_2048_0.mem"; attribute C_INIT_FILE_NAME : string; attribute C_INIT_FILE_NAME of U0 : label is "bram_2048_0.mif"; attribute C_INTERFACE_TYPE : integer; attribute C_INTERFACE_TYPE of U0 : label is 0; attribute C_LOAD_INIT_FILE : integer; attribute C_LOAD_INIT_FILE of U0 : label is 1; attribute C_MEM_TYPE : integer; attribute C_MEM_TYPE of U0 : label is 0; attribute C_MUX_PIPELINE_STAGES : integer; attribute C_MUX_PIPELINE_STAGES of U0 : label is 0; attribute C_PRIM_TYPE : integer; attribute C_PRIM_TYPE of U0 : label is 1; attribute C_READ_DEPTH_A : integer; attribute C_READ_DEPTH_A of U0 : label is 2048; attribute C_READ_DEPTH_B : integer; attribute C_READ_DEPTH_B of U0 : label is 2048; attribute C_READ_WIDTH_A : integer; attribute C_READ_WIDTH_A of U0 : label is 20; attribute C_READ_WIDTH_B : integer; attribute C_READ_WIDTH_B of U0 : label is 20; attribute C_RSTRAM_A : integer; attribute C_RSTRAM_A of U0 : label is 0; attribute C_RSTRAM_B : integer; attribute C_RSTRAM_B of U0 : label is 0; attribute C_RST_PRIORITY_A : string; attribute C_RST_PRIORITY_A of U0 : label is "CE"; attribute C_RST_PRIORITY_B : string; attribute C_RST_PRIORITY_B of U0 : label is "CE"; attribute C_SIM_COLLISION_CHECK : string; attribute C_SIM_COLLISION_CHECK of U0 : label is "ALL"; attribute C_USE_BRAM_BLOCK : integer; attribute C_USE_BRAM_BLOCK of U0 : label is 0; attribute C_USE_BYTE_WEA : integer; attribute C_USE_BYTE_WEA of U0 : label is 0; attribute C_USE_BYTE_WEB : integer; attribute C_USE_BYTE_WEB of U0 : label is 0; attribute C_USE_DEFAULT_DATA : integer; attribute C_USE_DEFAULT_DATA of U0 : label is 0; attribute C_USE_ECC : integer; attribute C_USE_ECC of U0 : label is 0; attribute C_USE_SOFTECC : integer; attribute C_USE_SOFTECC of U0 : label is 0; attribute C_USE_URAM : integer; attribute C_USE_URAM of U0 : label is 0; attribute C_WEA_WIDTH : integer; attribute C_WEA_WIDTH of U0 : label is 1; attribute C_WEB_WIDTH : integer; attribute C_WEB_WIDTH of U0 : label is 1; attribute C_WRITE_DEPTH_A : integer; attribute C_WRITE_DEPTH_A of U0 : label is 2048; attribute C_WRITE_DEPTH_B : integer; attribute C_WRITE_DEPTH_B of U0 : label is 2048; attribute C_WRITE_MODE_A : string; attribute C_WRITE_MODE_A of U0 : label is "WRITE_FIRST"; attribute C_WRITE_MODE_B : string; attribute C_WRITE_MODE_B of U0 : label is "WRITE_FIRST"; attribute C_WRITE_WIDTH_A : integer; attribute C_WRITE_WIDTH_A of U0 : label is 20; attribute C_WRITE_WIDTH_B : integer; attribute C_WRITE_WIDTH_B of U0 : label is 20; attribute C_XDEVICEFAMILY : string; attribute C_XDEVICEFAMILY of U0 : label is "zynq"; attribute downgradeipidentifiedwarnings of U0 : label is "yes"; begin U0: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 port map ( addra(10 downto 0) => addra(10 downto 0), addrb(10 downto 0) => B"00000000000", clka => clka, clkb => '0', dbiterr => NLW_U0_dbiterr_UNCONNECTED, deepsleep => '0', dina(19 downto 0) => dina(19 downto 0), dinb(19 downto 0) => B"00000000000000000000", douta(19 downto 0) => douta(19 downto 0), doutb(19 downto 0) => NLW_U0_doutb_UNCONNECTED(19 downto 0), eccpipece => '0', ena => ena, enb => '0', injectdbiterr => '0', injectsbiterr => '0', rdaddrecc(10 downto 0) => NLW_U0_rdaddrecc_UNCONNECTED(10 downto 0), regcea => '0', regceb => '0', rsta => '0', rsta_busy => NLW_U0_rsta_busy_UNCONNECTED, rstb => '0', rstb_busy => NLW_U0_rstb_busy_UNCONNECTED, s_aclk => '0', s_aresetn => '0', s_axi_araddr(31 downto 0) => B"00000000000000000000000000000000", s_axi_arburst(1 downto 0) => B"00", s_axi_arid(3 downto 0) => B"0000", s_axi_arlen(7 downto 0) => B"00000000", s_axi_arready => NLW_U0_s_axi_arready_UNCONNECTED, s_axi_arsize(2 downto 0) => B"000", s_axi_arvalid => '0', s_axi_awaddr(31 downto 0) => B"00000000000000000000000000000000", s_axi_awburst(1 downto 0) => B"00", s_axi_awid(3 downto 0) => B"0000", s_axi_awlen(7 downto 0) => B"00000000", s_axi_awready => NLW_U0_s_axi_awready_UNCONNECTED, s_axi_awsize(2 downto 0) => B"000", s_axi_awvalid => '0', s_axi_bid(3 downto 0) => NLW_U0_s_axi_bid_UNCONNECTED(3 downto 0), s_axi_bready => '0', s_axi_bresp(1 downto 0) => NLW_U0_s_axi_bresp_UNCONNECTED(1 downto 0), s_axi_bvalid => NLW_U0_s_axi_bvalid_UNCONNECTED, s_axi_dbiterr => NLW_U0_s_axi_dbiterr_UNCONNECTED, s_axi_injectdbiterr => '0', s_axi_injectsbiterr => '0', s_axi_rdaddrecc(10 downto 0) => NLW_U0_s_axi_rdaddrecc_UNCONNECTED(10 downto 0), s_axi_rdata(19 downto 0) => NLW_U0_s_axi_rdata_UNCONNECTED(19 downto 0), s_axi_rid(3 downto 0) => NLW_U0_s_axi_rid_UNCONNECTED(3 downto 0), s_axi_rlast => NLW_U0_s_axi_rlast_UNCONNECTED, s_axi_rready => '0', s_axi_rresp(1 downto 0) => NLW_U0_s_axi_rresp_UNCONNECTED(1 downto 0), s_axi_rvalid => NLW_U0_s_axi_rvalid_UNCONNECTED, s_axi_sbiterr => NLW_U0_s_axi_sbiterr_UNCONNECTED, s_axi_wdata(19 downto 0) => B"00000000000000000000", s_axi_wlast => '0', s_axi_wready => NLW_U0_s_axi_wready_UNCONNECTED, s_axi_wstrb(0) => '0', s_axi_wvalid => '0', sbiterr => NLW_U0_sbiterr_UNCONNECTED, shutdown => '0', sleep => '0', wea(0) => wea(0), web(0) => '0' ); end STRUCTURE;
unlicense
cc67caf1fdc6e649db5357f0d8c63068
0.713669
3.666069
false
false
false
false
grwlf/vsim
vhdl_ct/ct00455.vhd
1
4,353
------------------------------------------------------------------------------- -- -- Copyright (c) 1989 by Intermetrics, Inc. -- All rights reserved. -- ------------------------------------------------------------------------------- -- -- TEST NAME: -- -- CT00455 -- -- AUTHOR: -- -- A. Wilmot -- -- TEST OBJECTIVES: -- -- 7.2.4 (7) -- 7.2.4 (11) -- 7.2.4 (12) -- 7.2.4 (13) -- -- DESIGN UNIT ORDERING: -- -- ENT00455(ARCH00455) -- ENT00455_Test_Bench(ARCH00455_Test_Bench) -- -- REVISION HISTORY: -- -- 29-JUL-1987 - initial revision -- -- NOTES: -- -- self-checking -- use WORK.STANDARD_TYPES ; use WORK.ARITHMETIC.ALL ; entity ENT00455 is generic ( i_integer_1 : integer := c_int_1 ; i_integer_2 : integer := c_int_2 ; i_intt_1 : intt := c_intt_1 ; i_intt_2 : intt := c_intt_2 ; i_intst_1 : intst := c_intst_1 ; i_intst_2 : intst := c_intst_2 ; i_time_1 : time := c_time_1 ; i_time_2 : time := c_time_2 ; i_t_phys_1 : t_phys := c_t_phys_1 ; i_t_phys_2 : t_phys := c_t_phys_2 ; i_st_phys_1 : st_phys := c_st_phys_1 ; i_st_phys_2 : st_phys := c_st_phys_2 ) ; constant c2_time_1 : time := i_time_1 / i_intst_1 + i_time_2 / i_integer_1 + 0 ns / i_integer_2 ; constant c2_t_phys_1 : t_phys := i_t_phys_1 / i_intst_1 + c_t_phys_2 / i_integer_1 + i_t_phys_1 / i_intt_2 + i_t_phys_2 / c_int_2 ; constant c2_st_phys_1 : st_phys := i_st_phys_1 / i_intst_1 + c_t_phys_2 / i_integer_1 + i_t_phys_1 / i_intt_2 + i_st_phys_2 / c_int_2 ; end ENT00455 ; architecture ARCH00455 of ENT00455 is begin process variable bool : boolean := true ; variable cons_correct, gen_correct, dyn_correct : boolean := true ; -- variable v_time_1, v2_time_1 : time := i_time_1 ; variable v_time_2, v2_time_2 : time := i_time_2 ; variable v_t_phys_1, v2_t_phys_1 : t_phys := i_t_phys_1 ; variable v_t_phys_2, v2_t_phys_2 : t_phys := i_t_phys_2 ; variable v_st_phys_1, v2_st_phys_1 : st_phys := i_st_phys_1 ; variable v_st_phys_2, v2_st_phys_2 : st_phys := i_st_phys_2 ; variable v_integer_1 : integer := i_integer_1 ; variable v_integer_2 : integer := i_integer_2 ; variable v_intt_1 : intt := i_intt_1 ; variable v_intt_2 : intt := i_intt_2 ; variable v_intst_1 : intst := i_intst_1 ; variable v_intst_2 : intst := i_intst_2 ; -- begin -- static expression case bool is when ( c_time_1 / c_intst_1 + c_time_2 / c_int_1 + 0 ns / c_int_2 = 200_001 fs and --xx and c_t_phys_1 / c_intst_1 + c_t_phys_2 / c_int_1 + c_t_phys_1 / c_intt_2 + c_t_phys_2 / c_int_2 = -66 ones and --xx and c_st_phys_1 / c_intst_1 + c_t_phys_2 / c_int_1 + c_t_phys_1 / c_intt_2 + c_st_phys_2 / c_int_2 = -160 ones --xx ) => null ; when others => cons_correct := false ; end case ; -- generic expression gen_correct := c2_time_1 = 200_001 fs and --xx and c2_t_phys_1 = -66 ones and --xx and c2_st_phys_1 = -160 ones ; --xx ; -- dynamic expression v2_time_1 := v_time_1 / i_intst_1 + v_time_2 / v_integer_1 + 0 ns / v_integer_2 ; v2_t_phys_1 := v_t_phys_1 / v_intst_1 + i_t_phys_2 / v_integer_1 + v_t_phys_1 / v_intt_2 + v_t_phys_2 / c_int_2 ; v2_st_phys_1 := v_st_phys_1 / v_intst_1 + c_t_phys_2 / v_integer_1 + i_t_phys_1 / v_intt_2 + v_st_phys_2 / c_int_2 ; dyn_correct := v2_time_1 = 200_001 fs and --xx and v2_t_phys_1 = -66 ones and --xx and v2_st_phys_1 = -160 ones ; --xx ; STANDARD_TYPES.test_report ( "ARCH00455" , "/ predefined for physical and integer types" , dyn_correct and cons_correct and gen_correct ) ; wait ; end process ; end ARCH00455 ; entity ENT00455_Test_Bench is end ENT00455_Test_Bench ; architecture ARCH00455_Test_Bench of ENT00455_Test_Bench is begin L1: block component UUT end component ; for CIS1 : UUT use entity WORK.ENT00455 ( ARCH00455 ) ; begin CIS1 : UUT ; end block L1 ; end ARCH00455_Test_Bench ;
gpl-3.0
5cdf4c3b079b2e8636545bbebc339946
0.50425
2.672192
false
true
false
false
grwlf/vsim
vhdl_ct/ct00690.vhd
1
5,819
-- NEED RESULT: ARCH00690: Allocators with generic scalar qualified expression passed ------------------------------------------------------------------------------- -- -- Copyright (c) 1989 by Intermetrics, Inc. -- All rights reserved. -- ------------------------------------------------------------------------------- -- -- TEST NAME: -- -- CT00690 -- -- AUTHOR: -- -- A. Wilmot -- -- TEST OBJECTIVES: -- -- 7.3.6 (3) -- 7.3.6 (6) -- -- DESIGN UNIT ORDERING: -- -- GENERIC_STANDARD_TYPES(ARCH00690) -- ENT00690_Test_Bench(ARCH00690_Test_Bench) -- -- REVISION HISTORY: -- -- 08-SEP-1987 - initial revision -- -- NOTES: -- -- self-checking -- automatically generated -- use WORK.STANDARD_TYPES.all ; architecture ARCH00690 of GENERIC_STANDARD_TYPES is begin process variable correct : boolean := true ; type a_boolean is access boolean ; variable va_boolean_1, va_boolean_2 : a_boolean := new boolean ; type a_bit is access bit ; variable va_bit_1, va_bit_2 : a_bit := new bit ; type a_severity_level is access severity_level ; variable va_severity_level_1, va_severity_level_2 : a_severity_level := new severity_level ; type a_character is access character ; variable va_character_1, va_character_2 : a_character := new character ; type a_t_enum1 is access t_enum1 ; variable va_t_enum1_1, va_t_enum1_2 : a_t_enum1 := new t_enum1 ; type a_st_enum1 is access st_enum1 ; variable va_st_enum1_1, va_st_enum1_2 : a_st_enum1 := new st_enum1 ; type a_integer is access integer ; variable va_integer_1, va_integer_2 : a_integer := new integer ; type a_t_int1 is access t_int1 ; variable va_t_int1_1, va_t_int1_2 : a_t_int1 := new t_int1 ; type a_st_int1 is access st_int1 ; variable va_st_int1_1, va_st_int1_2 : a_st_int1 := new st_int1 ; type a_time is access time ; variable va_time_1, va_time_2 : a_time := new time ; type a_t_phys1 is access t_phys1 ; variable va_t_phys1_1, va_t_phys1_2 : a_t_phys1 := new t_phys1 ; type a_st_phys1 is access st_phys1 ; variable va_st_phys1_1, va_st_phys1_2 : a_st_phys1 := new st_phys1 ; type a_real is access real ; variable va_real_1, va_real_2 : a_real := new real ; type a_t_real1 is access t_real1 ; variable va_t_real1_1, va_t_real1_2 : a_t_real1 := new t_real1 ; type a_st_real1 is access st_real1 ; variable va_st_real1_1, va_st_real1_2 : a_st_real1 := new st_real1 ; begin va_boolean_1 := new boolean ' (c_boolean_1) ; va_bit_1 := new bit ' (c_bit_1) ; va_severity_level_1 := new severity_level ' (c_severity_level_1) ; va_character_1 := new character ' (c_character_1) ; va_t_enum1_1 := new t_enum1 ' (c_t_enum1_1) ; va_st_enum1_1 := new st_enum1 ' (c_st_enum1_1) ; va_integer_1 := new integer ' (c_integer_1) ; va_t_int1_1 := new t_int1 ' (c_t_int1_1) ; va_st_int1_1 := new st_int1 ' (c_st_int1_1) ; va_time_1 := new time ' (c_time_1) ; va_t_phys1_1 := new t_phys1 ' (c_t_phys1_1) ; va_st_phys1_1 := new st_phys1 ' (c_st_phys1_1) ; va_real_1 := new real ' (c_real_1) ; va_t_real1_1 := new t_real1 ' (c_t_real1_1) ; va_st_real1_1 := new st_real1 ' (c_st_real1_1) ; correct := correct and va_boolean_1.all = c_boolean_1 ; correct := correct and va_bit_1.all = c_bit_1 ; correct := correct and va_severity_level_1.all = c_severity_level_1 ; correct := correct and va_character_1.all = c_character_1 ; correct := correct and va_t_enum1_1.all = c_t_enum1_1 ; correct := correct and va_st_enum1_1.all = c_st_enum1_1 ; correct := correct and va_integer_1.all = c_integer_1 ; correct := correct and va_t_int1_1.all = c_t_int1_1 ; correct := correct and va_st_int1_1.all = c_st_int1_1 ; correct := correct and va_time_1.all = c_time_1 ; correct := correct and va_t_phys1_1.all = c_t_phys1_1 ; correct := correct and va_st_phys1_1.all = c_st_phys1_1 ; correct := correct and va_real_1.all = c_real_1 ; correct := correct and va_t_real1_1.all = c_t_real1_1 ; correct := correct and va_st_real1_1.all = c_st_real1_1 ; test_report ( "ARCH00690" , "Allocators with generic scalar qualified expression" , correct) ; wait ; end process ; end ARCH00690 ; -- entity ENT00690_Test_Bench is end ENT00690_Test_Bench ; -- architecture ARCH00690_Test_Bench of ENT00690_Test_Bench is begin L1: block component UUT end component ; for CIS1 : UUT use entity WORK.GENERIC_STANDARD_TYPES ( ARCH00690 ) ; begin CIS1 : UUT ; end block L1 ; end ARCH00690_Test_Bench ;
gpl-3.0
24632147d151802fc3e345343ba19a50
0.479808
3.37921
false
true
false
false
jairov4/accel-oil
solution_virtex5_plb/impl/pcores/nfa_accept_samples_generic_hw_top_v1_01_a/synhdl/vhdl/sample_buffer_if.vhd
4
27,537
-- ============================================================== -- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC -- Version: 2014.1 -- Copyright (C) 2014 Xilinx Inc. All rights reserved. -- -- ============================================================== library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; entity sample_buffer_if is generic ( C_PLB_AWIDTH : integer := 32; C_PLB_DWIDTH : integer := 64; PLB_ADDR_SHIFT : integer := 3; USER_DATA_WIDTH : integer := 8; USER_DATA_WIDTH_2N : integer := 8; USER_ADDR_SHIFT : integer := 0; -- log2(byte_count_of_data_width) REMOTE_DESTINATION_ADDRESS : std_logic_vector(0 to 31):= X"00000000" ); port ( -- Bus protocol ports, do not add to or delete MPLB_Clk : in std_logic; MPLB_Rst : in std_logic; M_request : out std_logic; M_priority : out std_logic_vector(0 to 1); M_busLock : out std_logic; M_RNW : out std_logic; M_BE : out std_logic_vector(0 to C_PLB_DWIDTH/8-1); M_MSize : out std_logic_vector(0 to 1); M_size : out std_logic_vector(0 to 3); M_type : out std_logic_vector(0 to 2); M_TAttribute : out std_logic_vector(0 to 15); M_lockErr : out std_logic; M_abort : out std_logic; M_ABus : out std_logic_vector(0 to C_PLB_AWIDTH-1); M_UABus : out std_logic_vector(0 to 31); M_wrDBus : out std_logic_vector(0 to C_PLB_DWIDTH-1); M_wrBurst : out std_logic; M_rdBurst : out std_logic; PLB_MAddrAck : in std_logic; PLB_MSSize : in std_logic_vector(0 to 1); PLB_MRearbitrate : in std_logic; PLB_MTimeout : in std_logic; PLB_MBusy : in std_logic; PLB_MRdErr : in std_logic; PLB_MWrErr : in std_logic; PLB_MIRQ : in std_logic; PLB_MRdDBus : in std_logic_vector(0 to (C_PLB_DWIDTH-1)); PLB_MRdWdAddr : in std_logic_vector(0 to 3); PLB_MRdDAck : in std_logic; PLB_MRdBTerm : in std_logic; PLB_MWrDAck : in std_logic; PLB_MWrBTerm : in std_logic; -- signals from user logic USER_RdData : out std_logic_vector(USER_DATA_WIDTH - 1 downto 0); -- Bus read return data to user_logic USER_WrData : in std_logic_vector(USER_DATA_WIDTH - 1 downto 0); -- Bus write data USER_address : in std_logic_vector(31 downto 0); -- word offset from BASE_ADDRESS USER_size : in std_logic_vector(31 downto 0); -- burst size of word USER_req_nRW : in std_logic; -- req type 0: Read, 1: write USER_req_full_n : out std_logic; -- req Fifo full USER_req_push : in std_logic; -- req Fifo push (new request in) USER_rsp_empty_n : out std_logic; -- return data FIFO empty USER_rsp_pop : in std_logic -- return data FIFO pop ); attribute SIGIS : string; attribute SIGIS of MPLB_Clk : signal is "Clk"; attribute SIGIS of MPLB_Rst : signal is "Rst"; end entity; ------------------------------------------------------------------------------ -- Architecture section ------------------------------------------------------------------------------ architecture IMP of sample_buffer_if is component sample_buffer_if_ap_fifo is generic ( DATA_WIDTH : integer := 32; ADDR_WIDTH : integer := 4; DEPTH : integer := 16); port ( clk : IN STD_LOGIC; reset : IN STD_LOGIC; if_empty_n : OUT STD_LOGIC; if_read : IN STD_LOGIC; if_dout : OUT STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0); if_full_n : OUT STD_LOGIC; if_write : IN STD_LOGIC; if_din : IN STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0) ); end component; component sample_buffer_if_plb_master_if is generic ( C_PLB_AWIDTH : integer := 32; C_PLB_DWIDTH : integer := 64; PLB_ADDR_SHIFT : integer := 3); port ( -- Bus protocol ports, do not add to or delete PLB_Clk : in std_logic; PLB_Rst : in std_logic; M_abort : out std_logic; M_ABus : out std_logic_vector(0 to C_PLB_AWIDTH-1); M_BE : out std_logic_vector(0 to C_PLB_DWIDTH/8-1); M_busLock : out std_logic; M_lockErr : out std_logic; M_MSize : out std_logic_vector(0 to 1); M_priority : out std_logic_vector(0 to 1); M_rdBurst : out std_logic; M_request : out std_logic; M_RNW : out std_logic; M_size : out std_logic_vector(0 to 3); M_type : out std_logic_vector(0 to 2); M_wrBurst : out std_logic; M_wrDBus : out std_logic_vector(0 to C_PLB_DWIDTH-1); PLB_MBusy : in std_logic; PLB_MWrBTerm : in std_logic; PLB_MWrDAck : in std_logic; PLB_MAddrAck : in std_logic; PLB_MRdBTerm : in std_logic; PLB_MRdDAck : in std_logic; PLB_MRdDBus : in std_logic_vector(0 to (C_PLB_DWIDTH-1)); PLB_MRdWdAddr : in std_logic_vector(0 to 3); PLB_MRearbitrate : in std_logic; PLB_MSSize : in std_logic_vector(0 to 1); -- signals from user logic BUS_RdData : out std_logic_vector(C_PLB_DWIDTH-1 downto 0); -- Bus read return data to user_logic BUS_WrData : in std_logic_vector(C_PLB_DWIDTH-1 downto 0); -- Bus write data BUS_address : in std_logic_vector(31 downto 0); -- word offset from BASE_ADDRESS BUS_size : in std_logic_vector(31 downto 0); -- burst size of word BUS_req_nRW : in std_logic; -- req type 0: Read, 1: write BUS_req_BE : in std_logic_vector(C_PLB_DWIDTH/8 -1 downto 0); -- Bus write data byte enable BUS_req_full_n : out std_logic; -- req Fifo full BUS_req_push : in std_logic; -- req Fifo push (new request in) BUS_rsp_nRW : out std_logic; -- return data FIFO rsp type BUS_rsp_empty_n : out std_logic; -- return data FIFO empty BUS_rsp_pop : in std_logic -- return data FIFO pop ); end component; -- type state_type is (IDLE, ); -- signal cs, ns : st_type; constant PLB_BW : integer := C_PLB_DWIDTH; constant PLB_BYTE_COUNT : integer := C_PLB_DWIDTH/8; constant USER_DATA_BYTE_COUNT : integer := USER_DATA_WIDTH_2N/8; constant REQ_FIFO_DATA_WIDTH : integer := 1 + 32 + 32 + USER_DATA_WIDTH_2N; -- nRW + addr + size + wr_data constant REQ_FIFO_ADDR_WIDTH : integer := 5; constant REQ_FIFO_DEPTH : integer := 32; constant ALIGN_DATA_WIDTH : integer := USER_DATA_WIDTH_2N + PLB_BW; constant ALIGN_DATA_BE_WIDTH : integer := (USER_DATA_WIDTH_2N + PLB_BW)/8; signal user_phy_address : STD_LOGIC_VECTOR(31 downto 0); -- request FIFO signal req_fifo_empty_n : STD_LOGIC; signal req_fifo_pop : STD_LOGIC; signal req_fifo_dout : STD_LOGIC_VECTOR(REQ_FIFO_DATA_WIDTH - 1 downto 0); signal req_fifo_full_n : STD_LOGIC; signal req_fifo_push : STD_LOGIC; signal req_fifo_din : STD_LOGIC_VECTOR(REQ_FIFO_DATA_WIDTH - 1 downto 0); signal user_WrData_2N : STD_LOGIC_VECTOR(USER_DATA_WIDTH_2N-1 downto 0); signal req_fifo_dout_req_nRW : STD_LOGIC; signal req_fifo_dout_req_address : STD_LOGIC_VECTOR(31 downto 0); signal req_fifo_dout_req_size, req_fifo_dout_req_size_normalize : STD_LOGIC_VECTOR(31 downto 0); -- internal request information signal req_nRW : STD_LOGIC; signal req_address : STD_LOGIC_VECTOR(31 downto 0); signal req_size, burst_size : STD_LOGIC_VECTOR(31 downto 0); signal req_size_user : STD_LOGIC_VECTOR(31 downto 0); signal req_BE : STD_LOGIC_VECTOR(PLB_BYTE_COUNT-1 downto 0); signal req_WrData : STD_LOGIC_VECTOR(ALIGN_DATA_WIDTH -1 downto 0); signal req_WrData_BE : STD_LOGIC_VECTOR(ALIGN_DATA_BE_WIDTH -1 downto 0); signal req_WrData_byte_p : STD_LOGIC_VECTOR(PLB_ADDR_SHIFT-1 downto 0); signal req_valid, req_SOP, req_EOP_user, req_EOP : STD_LOGIC; signal req_burst_write_counter : STD_LOGIC_VECTOR(31 downto 0); signal req_burst_mode, req_last_burst: STD_LOGIC; -- interface to PLB_master_if module signal PLB_master_if_req_full_n : STD_LOGIC; signal PLB_master_if_req_push : STD_LOGIC; signal PLB_master_if_dataout : STD_LOGIC_VECTOR(PLB_BW-1 downto 0); signal PLB_master_if_rsp_nRW : STD_LOGIC; signal PLB_master_if_rsp_empty_n : STD_LOGIC; signal PLB_master_if_rsp_pop : STD_LOGIC; signal USER_size_local: STD_LOGIC_VECTOR(31 downto 0); -- rsp FIFO constant RSP_FIFO_DATA_WIDTH : integer := PLB_ADDR_SHIFT + 32; -- addr + size constant RSP_FIFO_ADDR_WIDTH : integer := 6; constant RSP_FIFO_DEPTH : integer := 64; signal rsp_fifo_empty_n : STD_LOGIC; signal rsp_fifo_pop : STD_LOGIC; signal rsp_fifo_dout : STD_LOGIC_VECTOR(RSP_FIFO_DATA_WIDTH -1 downto 0); signal rsp_fifo_full_n : STD_LOGIC; signal rsp_fifo_push : STD_LOGIC; signal rsp_fifo_din : STD_LOGIC_VECTOR(RSP_FIFO_DATA_WIDTH -1 downto 0); signal rsp_valid, rsp_SOP : STD_LOGIC; signal rsp_addr : STD_LOGIC_VECTOR(PLB_ADDR_SHIFT-1 downto 0); signal rsp_size : STD_LOGIC_VECTOR(31 downto 0); signal rsp_rd_data : STD_LOGIC_VECTOR(ALIGN_DATA_WIDTH -1 downto 0); signal rsp_rd_data_byte_count : STD_LOGIC_VECTOR(4 downto 0); -- rd data user FIFO signal rd_data_user_fifo_empty_n : STD_LOGIC; signal rd_data_user_fifo_pop : STD_LOGIC; signal rd_data_user_fifo_dout : STD_LOGIC_VECTOR(USER_DATA_WIDTH -1 downto 0); signal rd_data_user_fifo_full_n : STD_LOGIC; signal rd_data_user_fifo_push : STD_LOGIC; signal rd_data_user_fifo_din : STD_LOGIC_VECTOR(USER_DATA_WIDTH -1 downto 0); signal rd_data_user_fifo_din_2N : STD_LOGIC_VECTOR(USER_DATA_WIDTH_2N -1 downto 0); signal BE_ALL_ONE : STD_LOGIC_VECTOR(PLB_BYTE_COUNT -1 downto 0); begin BE_ALL_ONE <= (others => '1'); M_UABus <= (others => '0'); M_TAttribute <= (others => '0'); -- interface to user logic user_phy_address(31 downto 0) <= REMOTE_DESTINATION_ADDRESS(0 to C_PLB_AWIDTH -1) + USER_address(31 downto 0); USER_size_local <= X"00000001" when conv_integer(USER_size(31 downto 1)) = 0 else USER_size; USER_req_full_n <= req_fifo_full_n; process(USER_WrData) variable i: integer; begin user_WrData_2N <= (others=> '0'); for i in 0 to USER_WrData'length -1 loop user_WrData_2N (USER_DATA_WIDTH_2N-1 -i) <= USER_WrData(i); end loop; end process; req_fifo_din(REQ_FIFO_DATA_WIDTH-1) <= USER_req_nRW; req_fifo_din(REQ_FIFO_DATA_WIDTH-1-1 downto REQ_FIFO_DATA_WIDTH -1-32) <= user_phy_address; req_fifo_din(REQ_FIFO_DATA_WIDTH-1-32-1 downto REQ_FIFO_DATA_WIDTH -1-32-32) <= USER_size_local; req_fifo_din(USER_DATA_WIDTH_2N -1 downto 0) <= user_WrData_2N(USER_DATA_WIDTH_2N-1 downto 0); req_fifo_push <= USER_req_push; U_sample_buffer_if_req_fifo: component sample_buffer_if_ap_fifo generic map( DATA_WIDTH => REQ_FIFO_DATA_WIDTH, ADDR_WIDTH => REQ_FIFO_ADDR_WIDTH, DEPTH => REQ_FIFO_DEPTH) port map( clk => MPLB_Clk, reset => MPLB_Rst, if_empty_n => req_fifo_empty_n, if_read => req_fifo_pop, if_dout => req_fifo_dout, if_full_n => req_fifo_full_n, if_write => req_fifo_push, if_din => req_fifo_din ); req_fifo_dout_req_nRW <= req_fifo_dout(REQ_FIFO_DATA_WIDTH -1); req_fifo_dout_req_size <= req_fifo_dout(REQ_FIFO_DATA_WIDTH-1-32-1 downto REQ_FIFO_DATA_WIDTH -1-32-32); req_fifo_dout_req_address <= req_fifo_dout(REQ_FIFO_DATA_WIDTH-1-1 downto REQ_FIFO_DATA_WIDTH -1-32); req_fifo_dout_req_size_normalize <= req_fifo_dout_req_size; process(req_fifo_empty_n, req_valid) begin req_fifo_pop <= '0'; if (req_fifo_empty_n = '1' and req_valid = '0') then -- lunch next request req_fifo_pop <= '1'; end if; end process; process (MPLB_Clk, MPLB_Rst) variable offset: integer; begin if (MPLB_Rst = '1') then req_nRW <= '0'; burst_size <= (others => '0'); req_size_user <= (others => '0'); req_address <= (others => '0'); req_WrData <= (others => '0'); -- set possible MSB to ZERO req_WrData_BE <= (others => '0'); -- set possible MSB to ZERO req_WrData_byte_p <= (others => '0'); -- set possible MSB to ZERO req_valid <= '0'; req_EOP <= '0'; req_burst_write_counter <= (others => '0'); req_burst_mode <= '0'; elsif (MPLB_Clk'event and MPLB_Clk = '1') then if (req_fifo_pop = '1') then -- lunch next request req_valid <= '1'; if (req_burst_mode = '0') then if (req_fifo_dout_req_nRW = '0') then if (req_fifo_dout_req_size_normalize(PLB_ADDR_SHIFT-1 downto 0) = CONV_STD_LOGIC_VECTOR(0,PLB_ADDR_SHIFT) and req_fifo_dout_req_address(PLB_ADDR_SHIFT-1 downto 0) = CONV_STD_LOGIC_VECTOR(0,PLB_ADDR_SHIFT)) then burst_size(31-PLB_ADDR_SHIFT downto 0) <= req_fifo_dout_req_size_normalize(31 downto PLB_ADDR_SHIFT); elsif (('0'&req_fifo_dout_req_size_normalize(PLB_ADDR_SHIFT-1 downto 0)) + ('0'&req_fifo_dout_req_address(PLB_ADDR_SHIFT-1 downto 0)) <= PLB_BYTE_COUNT) then burst_size(31-PLB_ADDR_SHIFT downto 0) <= req_fifo_dout_req_size_normalize(31 downto PLB_ADDR_SHIFT) + 1; else burst_size(31-PLB_ADDR_SHIFT downto 0) <= req_fifo_dout_req_size_normalize(31 downto PLB_ADDR_SHIFT) + 2; end if; else burst_size <= X"00000001"; -- single by default if (req_fifo_dout_req_size_normalize(31 downto PLB_ADDR_SHIFT+1) /= CONV_STD_LOGIC_VECTOR(0,31-PLB_ADDR_SHIFT)) then -- may burst burst_size(31 downto 32-PLB_ADDR_SHIFT) <= (others=>'0'); -- burst_size for write operation if (req_fifo_dout_req_address(PLB_ADDR_SHIFT-1 downto 0) = CONV_STD_LOGIC_VECTOR(0, PLB_ADDR_SHIFT)) or (conv_integer(req_fifo_dout_req_address(PLB_ADDR_SHIFT-1 downto 0)) + conv_integer(req_fifo_dout_req_size_normalize(PLB_ADDR_SHIFT-1 downto 0)) >= PLB_BYTE_COUNT) then burst_size(31-PLB_ADDR_SHIFT downto 0) <= req_fifo_dout_req_size_normalize(31 downto PLB_ADDR_SHIFT); else burst_size(31-PLB_ADDR_SHIFT downto 0) <= req_fifo_dout_req_size_normalize(31 downto PLB_ADDR_SHIFT)-1; end if; end if; end if; offset := conv_integer(req_fifo_dout_req_address(PLB_ADDR_SHIFT-1 downto 0)); if (req_fifo_dout_req_nRW = '1') then req_WrData(USER_DATA_WIDTH_2N +offset*8 -1 downto offset*8) <= req_fifo_dout(USER_DATA_WIDTH_2N -1 downto 0); req_WrData_BE(USER_DATA_BYTE_COUNT+offset-1 downto offset) <= (others => '1'); end if; req_size_user <= req_fifo_dout_req_size; -- for read operation req_nRW <= req_fifo_dout_req_nRW; req_EOP <= '1'; req_address <= req_fifo_dout_req_address; req_burst_write_counter <= req_fifo_dout_req_size; req_WrData_byte_p <= req_fifo_dout_req_address(PLB_ADDR_SHIFT-1 downto 0) + USER_DATA_BYTE_COUNT; if (req_fifo_dout_req_nRW = '1' and req_fifo_dout_req_size(31 downto 1) /= "0000000000000000000000000000000") then req_burst_mode <= '1'; req_EOP <= '0'; end if; else -- in a burst write process req_burst_write_counter <= req_burst_write_counter -1; offset := conv_integer(req_WrData_byte_p); req_WrData(USER_DATA_WIDTH_2N +offset*8 -1 downto offset*8) <= req_fifo_dout(USER_DATA_WIDTH_2N -1 downto 0); req_WrData_BE(USER_DATA_BYTE_COUNT+offset-1 downto offset) <= (others => '1'); req_WrData_byte_p <= req_WrData_byte_p + USER_DATA_BYTE_COUNT; if (req_last_burst = '1') then req_burst_mode <= '0'; req_EOP <= '1'; end if; end if; elsif (req_valid = '1') then if (req_nRW = '0' and PLB_master_if_req_push = '1') then req_valid <= '0'; elsif (req_nRW = '1') then if (req_EOP = '1' and PLB_master_if_req_push = '1') then -- last burst request if (req_WrData_BE(ALIGN_DATA_BE_WIDTH-1 downto PLB_BYTE_COUNT) = CONV_STD_LOGIC_VECTOR(0, ALIGN_DATA_BE_WIDTH-PLB_BYTE_COUNT)) then req_valid <= '0'; req_EOP <= '0'; req_WrData <= (others=>'0'); req_WrData_BE <= (others => '0'); else req_WrData(USER_DATA_WIDTH_2N + PLB_BW -1 downto USER_DATA_WIDTH_2N) <= (others => '0'); req_WrData(USER_DATA_WIDTH_2N -1 downto 0) <= req_WrData(USER_DATA_WIDTH_2N +PLB_BW -1 downto PLB_BW); req_WrData_BE(ALIGN_DATA_BE_WIDTH -1 downto ALIGN_DATA_BE_WIDTH-PLB_BYTE_COUNT) <= (others => '0'); req_WrData_BE(ALIGN_DATA_BE_WIDTH -PLB_BYTE_COUNT-1 downto 0) <= req_WrData_BE(ALIGN_DATA_BE_WIDTH -1 downto PLB_BYTE_COUNT); req_address(31 downto PLB_ADDR_SHIFT) <= req_address(31 downto PLB_ADDR_SHIFT) +1; req_address(PLB_ADDR_SHIFT-1 downto 0) <= (others=>'0'); end if; elsif (req_EOP = '0') then if (req_WrData_BE(PLB_BYTE_COUNT-1) = '0') then req_valid <= '0'; elsif (req_WrData_BE(PLB_BYTE_COUNT-1) = '1' and PLB_master_if_req_push = '1') then req_WrData(USER_DATA_WIDTH_2N + PLB_BW -1 downto USER_DATA_WIDTH_2N) <= (others => '0'); req_WrData(USER_DATA_WIDTH_2N -1 downto 0) <= req_WrData(USER_DATA_WIDTH_2N +PLB_BW -1 downto PLB_BW); req_WrData_BE(ALIGN_DATA_BE_WIDTH -1 downto ALIGN_DATA_BE_WIDTH-PLB_BYTE_COUNT) <= (others => '0'); req_WrData_BE(ALIGN_DATA_BE_WIDTH-PLB_BYTE_COUNT-1 downto 0) <= req_WrData_BE(ALIGN_DATA_BE_WIDTH -1 downto PLB_BYTE_COUNT); req_address(31 downto PLB_ADDR_SHIFT) <= req_address(31 downto PLB_ADDR_SHIFT) +1; req_address(PLB_ADDR_SHIFT-1 downto 0) <= (others=>'0'); end if; end if; end if; end if; end if; end process; req_last_burst <= '1' when (req_burst_mode = '1' and req_burst_write_counter(31 downto 0) = X"00000002") else '0'; process(req_nRW, req_WrData_BE, burst_size) begin req_size <= (others => '0'); if (req_nRW = '0') then req_size <= burst_size; elsif (req_WrData_BE(PLB_BYTE_COUNT-1 downto 0) = BE_ALL_ONE) then req_size <= burst_size; else req_size <= X"00000001"; end if; end process; process(req_valid, PLB_master_if_req_full_n, req_nRW, req_WrData_BE) begin PLB_master_if_req_push <= '0'; if (req_valid = '1' and PLB_master_if_req_full_n = '1') then if (req_nRW = '0') then PLB_master_if_req_push <= '1'; -- only push when the last byte been push elsif (req_WrData_BE(PLB_BYTE_COUNT-1) = '1' or (req_EOP = '1' and req_WrData_BE(PLB_BYTE_COUNT-1 downto 0) /= CONV_STD_LOGIC_VECTOR(0, PLB_BYTE_COUNT))) then PLB_master_if_req_push <= '1'; -- only push when the last byte been push end if; end if; end process; req_BE <= req_WrData_BE(PLB_BYTE_COUNT-1 downto 0) when req_nRW = '1' else (others => '1'); U_sample_buffer_if_plb_master_if: component sample_buffer_if_plb_master_if generic map( C_PLB_AWIDTH => C_PLB_AWIDTH, C_PLB_DWIDTH => C_PLB_DWIDTH, PLB_ADDR_SHIFT => PLB_ADDR_SHIFT) port map ( -- Bus protocol ports, do not add to or delete PLB_Clk => MPLB_Clk, PLB_Rst => MPLB_Rst, M_abort => M_abort, M_ABus => M_ABus, M_BE => M_BE, M_busLock => M_busLock, M_lockErr => M_lockErr, M_MSize => M_MSize, M_priority => M_priority, M_rdBurst => M_rdBurst, M_request => M_request, M_RNW => M_RNW, M_size => M_size, M_type => M_type, M_wrBurst => M_wrBurst, M_wrDBus => M_wrDBus, PLB_MBusy => PLB_MBusy, PLB_MWrBTerm => PLB_MWrBTerm, PLB_MWrDAck => PLB_MWrDAck, PLB_MAddrAck => PLB_MAddrAck, PLB_MRdBTerm => PLB_MRdBTerm, PLB_MRdDAck => PLB_MRdDAck, PLB_MRdDBus => PLB_MRdDBus, PLB_MRdWdAddr => PLB_MRdWdAddr, PLB_MRearbitrate => PLB_MRearbitrate, PLB_MSSize => PLB_MSSize, -- signals from user logic BUS_RdData => PLB_master_if_dataout, BUS_WrData => req_WrData(PLB_BW-1 downto 0), BUS_address => req_address, BUS_size => req_size, BUS_req_nRW => req_nRW, BUS_req_BE => req_BE, BUS_req_full_n => PLB_master_if_req_full_n, BUS_req_push => PLB_master_if_req_push, BUS_rsp_nRW => PLB_master_if_rsp_nRW, BUS_rsp_empty_n => PLB_master_if_rsp_empty_n, BUS_rsp_pop => PLB_master_if_rsp_pop ); -- below is the response (bus read data) part U_sample_buffer_if_rsp_fifo: component sample_buffer_if_ap_fifo generic map( DATA_WIDTH => RSP_FIFO_DATA_WIDTH, ADDR_WIDTH => RSP_FIFO_ADDR_WIDTH, DEPTH => RSP_FIFO_DEPTH) port map( clk => MPLB_Clk, reset => MPLB_Rst, if_empty_n => rsp_fifo_empty_n, if_read => rsp_fifo_pop, if_dout => rsp_fifo_dout, if_full_n => rsp_fifo_full_n, if_write => rsp_fifo_push, if_din => rsp_fifo_din ); rsp_fifo_din(32+PLB_ADDR_SHIFT-1 downto 32) <= req_address(PLB_ADDR_SHIFT-1 downto 0); rsp_fifo_din(31 downto 0) <= req_size_user; rsp_fifo_push <= PLB_master_if_req_push and (not req_nRW); process (rsp_valid, PLB_master_if_rsp_empty_n, rsp_rd_data_byte_count) begin PLB_master_if_rsp_pop <= '0'; -- fetch data to rsp_rd_data until enough bytes if (rsp_valid = '1' and PLB_master_if_rsp_empty_n = '1' and CONV_INTEGER(rsp_rd_data_byte_count) < USER_DATA_BYTE_COUNT) then PLB_master_if_rsp_pop <= '1'; end if; end process; process (MPLB_Clk, MPLB_Rst) begin if (MPLB_Rst = '1') then rsp_valid <= '0'; rsp_addr <= (others=> '0'); rsp_size <= (others=> '0'); rsp_SOP <= '1'; rsp_rd_data_byte_count <= (others => '0'); rsp_rd_data <= (others=>'0'); rsp_fifo_pop <= '0'; elsif (MPLB_Clk'event and MPLB_Clk = '1') then rsp_fifo_pop <= '0'; if (rsp_valid = '0' and rsp_fifo_empty_n = '1') then rsp_valid <= '1'; rsp_addr <= rsp_fifo_dout(32+PLB_ADDR_SHIFT-1 downto 32); rsp_size <= rsp_fifo_dout(31 downto 0); rsp_fifo_pop <= '1'; rsp_rd_data_byte_count <= (others=>'0'); rsp_SOP <= '1'; end if; -- fetch data to rsp_rd_data until enough bytes if (PLB_master_if_rsp_pop = '1') then rsp_rd_data(USER_DATA_WIDTH_2N-1 downto 0) <= rsp_rd_data(USER_DATA_WIDTH_2N + PLB_BW -1 downto PLB_BW); rsp_rd_data(USER_DATA_WIDTH_2N +PLB_BW -1 downto USER_DATA_WIDTH_2N) <= PLB_master_if_dataout; if (rsp_SOP = '1') then rsp_rd_data_byte_count <= rsp_rd_data_byte_count + PLB_BYTE_COUNT - rsp_addr; rsp_SOP <= '0'; else rsp_rd_data_byte_count <= rsp_rd_data_byte_count + PLB_BYTE_COUNT; end if; end if; -- write one unit of data to USER LOGIC if (rd_data_user_fifo_push = '1') then rsp_size <= rsp_size -1; rsp_rd_data_byte_count <= rsp_rd_data_byte_count - USER_DATA_BYTE_COUNT; rsp_addr <= rsp_addr + USER_DATA_BYTE_COUNT; if (rsp_size = X"00000001") then rsp_valid <= '0'; end if; end if; end if; end process; process(rsp_addr, rsp_rd_data,rsp_valid, rd_data_user_fifo_full_n, rsp_rd_data_byte_count, rd_data_user_fifo_din_2N) variable i: integer; begin case CONV_INTEGER(rsp_addr) is when 0 => rd_data_user_fifo_din_2N <= rsp_rd_data(USER_DATA_WIDTH_2N +8 -1 downto 8); when 1 => rd_data_user_fifo_din_2N <= rsp_rd_data(USER_DATA_WIDTH_2N +16 -1 downto 16); when 2 => rd_data_user_fifo_din_2N <= rsp_rd_data(USER_DATA_WIDTH_2N +24 -1 downto 24); when 3 => rd_data_user_fifo_din_2N <= rsp_rd_data(USER_DATA_WIDTH_2N +32 -1 downto 32); when 4 => rd_data_user_fifo_din_2N <= rsp_rd_data(USER_DATA_WIDTH_2N +40 -1 downto 40); when 5 => rd_data_user_fifo_din_2N <= rsp_rd_data(USER_DATA_WIDTH_2N +48 -1 downto 48); when 6 => rd_data_user_fifo_din_2N <= rsp_rd_data(USER_DATA_WIDTH_2N +56 -1 downto 56); when 7 => rd_data_user_fifo_din_2N <= rsp_rd_data(USER_DATA_WIDTH_2N +64 -1 downto 64); when others => null; end case; for i in 0 to USER_DATA_WIDTH -1 loop rd_data_user_fifo_din(i) <= rd_data_user_fifo_din_2N(USER_DATA_WIDTH_2N-1-i); end loop; rd_data_user_fifo_push <= '0'; if (rsp_valid = '1' and rd_data_user_fifo_full_n = '1' and CONV_INTEGER(rsp_rd_data_byte_count)>= USER_DATA_BYTE_COUNT) then rd_data_user_fifo_push <= '1'; end if; end process; U_sample_buffer_if_rd_data_user_fifo: component sample_buffer_if_ap_fifo generic map( DATA_WIDTH => USER_DATA_WIDTH, ADDR_WIDTH => 5, DEPTH => 32) port map( clk => MPLB_Clk, reset => MPLB_Rst, if_empty_n => rd_data_user_fifo_empty_n, if_read => USER_rsp_pop, if_dout => rd_data_user_fifo_dout, if_full_n => rd_data_user_fifo_full_n, if_write => rd_data_user_fifo_push, if_din => rd_data_user_fifo_din ); USER_RdData <= rd_data_user_fifo_dout; USER_rsp_empty_n <= rd_data_user_fifo_empty_n; end IMP;
lgpl-3.0
78d543d7c0d9c67b21a95bbd931c8d04
0.54937
3.277434
false
false
false
false
TWW12/lzw
final_project_sim/lzw/lzw.srcs/sim_1/imports/temp/lzw_tb.vhd
1
2,909
library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.NUMERIC_STD.ALL; entity lzw_tb is end lzw_tb; architecture Behavioral of lzw_tb is --the rain in Spain falls mainly on the plain constant str_len : integer := 43; signal test_vector : std_logic_vector(str_len*8-1 downto 0) := x"746865207261696e20696e20537061696e2066616c6c73206d61696e6c79206f6e2074686520706c61696e"; constant result_len : integer := 33; signal result_vector : std_logic_vector(result_len*12-1 downto 0) := x"07406806502007206106906E02010602005307010510706606106C06C07302006D10D06C07902006F10710010207006C10D"; signal clk : std_logic; signal rst : std_logic; signal char_in : std_logic_vector(7 downto 0) := x"00"; signal input_valid : std_logic := '0'; signal input_rd : std_logic; signal prefix_out : std_logic_vector(11 downto 0); signal expected : std_logic_vector(11 downto 0); signal output_valid : std_logic; signal done : std_logic; signal file_size : std_logic_vector(15 downto 0) := std_logic_vector(to_unsigned(str_len,16)); begin UUT : entity work.lzw port map( clk => clk, rst => rst, char_in => char_in, input_valid => input_valid, input_rd => input_rd, file_size => file_size, prefix_out => prefix_out, done => done, output_valid => output_valid); clk_proc: process begin clk <= '1'; wait for 5 ns; clk <= '0'; wait for 5 ns; end process; input_proc: process variable i : integer := str_len-1; begin rst <= '1'; wait for 30 ns; rst <= '0'; input_valid <= '1'; char_in <= test_vector(str_len*8-1 downto (str_len-1)*8); while i /= 0 loop if input_rd = '1' then char_in <= test_vector(i*8-1 downto (i-1)*8); i := i-1; end if; wait for 10 ns; end loop; char_in <= test_vector(7 downto 0); wait until input_rd = '1'; input_valid <= '0'; wait for 10 ns; char_in <= x"00"; wait; end process; output_proc : process variable i : integer := result_len; begin wait for 10 ns; expected <= result_vector(i*12-1 downto (i-1)*12); if output_valid = '1' then assert result_vector(i*12-1 downto (i-1)*12) = prefix_out report "Output prefix does not match." severity warning; i := i-1; end if; if i = 1 then report "Testbench completed." severity note; wait; end if; end process; end Behavioral;
unlicense
ea237c3140f6fd546ffaaf5e6a3bfbb7
0.529392
3.63625
false
false
false
false
grwlf/vsim
vhdl_ct/ct00543.vhd
1
1,841
-- NEED RESULT: ARCH00543: Predefined attribute visibility test passed ------------------------------------------------------------------------------- -- -- Copyright (c) 1989 by Intermetrics, Inc. -- All rights reserved. -- ------------------------------------------------------------------------------- -- -- TEST NAME: -- -- CT00543 -- -- AUTHOR: -- -- G. Tominovich -- -- TEST OBJECTIVES: -- -- 10.3 (10) -- -- DESIGN UNIT ORDERING: -- -- PKG00543 -- PKG00543/BODY -- ENT00543_Test_Bench(ARCH00543_Test_Bench) -- -- REVISION HISTORY: -- -- 19-AUG-1987 - initial revision -- -- NOTES: -- -- self-checking -- -- package PKG00543 is -- Note: Names not denoting predefined attributes will -- be in lower case type base is (B1, B2, B3, B4, B5, B6) ; subtype left is base range B1 to B3; subtype right is base range B3 to B5; constant high : base := base'BASE'HIGH; constant low : left := left'LEFT; constant pos : INTEGER := base'POS (right'LEFT) ; Function pred return BOOLEAN ; end PKG00543 ; package body PKG00543 is Function pred return BOOLEAN is begin return ( (low = base'BASE'LOW) and (base'PRED (base'BASE'HIGH) = right'RIGHT) and (pos = base'POS (left'LEFT) + 2) and (right'BASE'POS (high) = 5) ) ; end pred ; end PKG00543 ; use WORK.STANDARD_TYPES.all ; use WORK.PKG00543.all ; entity ENT00543_Test_Bench is end ENT00543_Test_Bench ; architecture ARCH00543_Test_Bench of ENT00543_Test_Bench is begin process begin test_report ( "ARCH00543" , "Predefined attribute visibility test" , pred ) ; wait ; end process ; end ARCH00543_Test_Bench ; --
gpl-3.0
de2aa3979012ae4f203f4f3ca4210669
0.527431
3.396679
false
true
false
false