repo_name
stringlengths 6
79
| path
stringlengths 6
236
| copies
int64 1
472
| size
int64 137
1.04M
| content
stringlengths 137
1.04M
| license
stringclasses 15
values | hash
stringlengths 32
32
| alpha_frac
float64 0.25
0.96
| ratio
float64 1.51
17.5
| autogenerated
bool 1
class | config_or_test
bool 2
classes | has_no_keywords
bool 1
class | has_few_assignments
bool 1
class |
|---|---|---|---|---|---|---|---|---|---|---|---|---|
TWW12/lzw | final_project/lzw_compression/lzw_compression.srcs/sources_1/bd/design_1/ip/design_1_rst_ps7_0_100M_0/synth/design_1_rst_ps7_0_100M_0.vhd | 1 | 6,594 | -- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:proc_sys_reset:5.0
-- IP Revision: 10
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY design_1_rst_ps7_0_100M_0 IS
PORT (
slowest_sync_clk : IN STD_LOGIC;
ext_reset_in : IN STD_LOGIC;
aux_reset_in : IN STD_LOGIC;
mb_debug_sys_rst : IN STD_LOGIC;
dcm_locked : IN STD_LOGIC;
mb_reset : OUT STD_LOGIC;
bus_struct_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
peripheral_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
interconnect_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
peripheral_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0)
);
END design_1_rst_ps7_0_100M_0;
ARCHITECTURE design_1_rst_ps7_0_100M_0_arch OF design_1_rst_ps7_0_100M_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF design_1_rst_ps7_0_100M_0_arch: ARCHITECTURE IS "yes";
COMPONENT proc_sys_reset IS
GENERIC (
C_FAMILY : STRING;
C_EXT_RST_WIDTH : INTEGER;
C_AUX_RST_WIDTH : INTEGER;
C_EXT_RESET_HIGH : STD_LOGIC;
C_AUX_RESET_HIGH : STD_LOGIC;
C_NUM_BUS_RST : INTEGER;
C_NUM_PERP_RST : INTEGER;
C_NUM_INTERCONNECT_ARESETN : INTEGER;
C_NUM_PERP_ARESETN : INTEGER
);
PORT (
slowest_sync_clk : IN STD_LOGIC;
ext_reset_in : IN STD_LOGIC;
aux_reset_in : IN STD_LOGIC;
mb_debug_sys_rst : IN STD_LOGIC;
dcm_locked : IN STD_LOGIC;
mb_reset : OUT STD_LOGIC;
bus_struct_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
peripheral_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
interconnect_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
peripheral_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0)
);
END COMPONENT proc_sys_reset;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF design_1_rst_ps7_0_100M_0_arch: ARCHITECTURE IS "proc_sys_reset,Vivado 2016.4";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF design_1_rst_ps7_0_100M_0_arch : ARCHITECTURE IS "design_1_rst_ps7_0_100M_0,proc_sys_reset,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF design_1_rst_ps7_0_100M_0_arch: ARCHITECTURE IS "design_1_rst_ps7_0_100M_0,proc_sys_reset,{x_ipProduct=Vivado 2016.4,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=proc_sys_reset,x_ipVersion=5.0,x_ipCoreRevision=10,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,C_FAMILY=zynq,C_EXT_RST_WIDTH=4,C_AUX_RST_WIDTH=4,C_EXT_RESET_HIGH=0,C_AUX_RESET_HIGH=0,C_NUM_BUS_RST=1,C_NUM_PERP_RST=1,C_NUM_INTERCONNECT_ARESETN=1,C_NUM_PERP_ARESETN=1}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF slowest_sync_clk: SIGNAL IS "xilinx.com:signal:clock:1.0 clock CLK";
ATTRIBUTE X_INTERFACE_INFO OF ext_reset_in: SIGNAL IS "xilinx.com:signal:reset:1.0 ext_reset RST";
ATTRIBUTE X_INTERFACE_INFO OF aux_reset_in: SIGNAL IS "xilinx.com:signal:reset:1.0 aux_reset RST";
ATTRIBUTE X_INTERFACE_INFO OF mb_debug_sys_rst: SIGNAL IS "xilinx.com:signal:reset:1.0 dbg_reset RST";
ATTRIBUTE X_INTERFACE_INFO OF mb_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 mb_rst RST";
ATTRIBUTE X_INTERFACE_INFO OF bus_struct_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 bus_struct_reset RST";
ATTRIBUTE X_INTERFACE_INFO OF peripheral_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 peripheral_high_rst RST";
ATTRIBUTE X_INTERFACE_INFO OF interconnect_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 interconnect_low_rst RST";
ATTRIBUTE X_INTERFACE_INFO OF peripheral_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 peripheral_low_rst RST";
BEGIN
U0 : proc_sys_reset
GENERIC MAP (
C_FAMILY => "zynq",
C_EXT_RST_WIDTH => 4,
C_AUX_RST_WIDTH => 4,
C_EXT_RESET_HIGH => '0',
C_AUX_RESET_HIGH => '0',
C_NUM_BUS_RST => 1,
C_NUM_PERP_RST => 1,
C_NUM_INTERCONNECT_ARESETN => 1,
C_NUM_PERP_ARESETN => 1
)
PORT MAP (
slowest_sync_clk => slowest_sync_clk,
ext_reset_in => ext_reset_in,
aux_reset_in => aux_reset_in,
mb_debug_sys_rst => mb_debug_sys_rst,
dcm_locked => dcm_locked,
mb_reset => mb_reset,
bus_struct_reset => bus_struct_reset,
peripheral_reset => peripheral_reset,
interconnect_aresetn => interconnect_aresetn,
peripheral_aresetn => peripheral_aresetn
);
END design_1_rst_ps7_0_100M_0_arch;
| unlicense | 5219914b06a8978195dea3691ee48fea | 0.711859 | 3.413043 | false | false | false | false |
grwlf/vsim | vhdl_ct/ct00209.vhd | 1 | 3,663 | -- NEED RESULT: ENT00209: Wait statement longest static prefix check passed
-- NEED RESULT: ENT00209: Wait statement longest static prefix check passed
-- NEED RESULT: P1: Wait longest static prefix test completed passed
-------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
-------------------------------------------------------------------------------
--
-- TEST NAME:
--
-- CT00209
--
-- AUTHOR:
--
-- G. Tominovich
--
-- TEST OBJECTIVES:
--
-- 8.1 (5)
--
-- DESIGN UNIT ORDERING:
--
-- ENT00209(ARCH00209)
-- ENT00209_Test_Bench(ARCH00209_Test_Bench)
--
-- REVISION HISTORY:
--
-- 10-JUL-1987 - initial revision
--
-- NOTES:
--
-- self-checking
-- automatically generated
--
use WORK.STANDARD_TYPES.all ;
entity ENT00209 is
generic (G : integer) ;
port (
s_st_rec3 : inout st_rec3
) ;
--
constant CG : integer := G+1;
attribute attr : integer ;
attribute attr of CG : constant is CG+1;
--
end ENT00209 ;
--
--
architecture ARCH00209 of ENT00209 is
subtype chk_sig_type is integer range -1 to 100 ;
signal chk_st_rec3 : chk_sig_type := -1 ;
--
begin
P1 :
process
variable counter : integer := 0 ;
variable correct : boolean ;
variable savtime : time := 0 ns ;
begin
case counter is
when 0
=>
s_st_rec3.f1 <= transport
c_st_rec3_2.f1 ;
s_st_rec3.f2 <= transport
c_st_rec3_2.f2 after 10 ns ;
wait until s_st_rec3.f2 =
c_st_rec3_2.f2 ;
Test_Report (
"ENT00209",
"Wait statement longest static prefix check",
((savtime + 10 ns) = Std.Standard.Now) and
(s_st_rec3.f2 =
c_st_rec3_2.f2 )) ;
--
when 1
=>
s_st_rec3.f1 <= transport
c_st_rec3_1.f1 ;
s_st_rec3.f3 <= transport
c_st_rec3_2.f3 after 10 ns ;
wait until s_st_rec3.f3 =
c_st_rec3_2.f3 ;
Test_Report (
"ENT00209",
"Wait statement longest static prefix check",
((savtime + 10 ns) = Std.Standard.Now) and
(s_st_rec3.f3 =
c_st_rec3_2.f3 )) ;
--
when others
=> wait ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_st_rec3 <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
end process P1 ;
--
PGEN_CHKP_1 :
process ( chk_st_rec3 )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P1" ,
"Wait longest static prefix test completed",
chk_st_rec3 = 1 ) ;
end if ;
end process PGEN_CHKP_1 ;
--
--
end ARCH00209 ;
--
--
use WORK.STANDARD_TYPES.all ;
entity ENT00209_Test_Bench is
end ENT00209_Test_Bench ;
--
--
architecture ARCH00209_Test_Bench of ENT00209_Test_Bench is
begin
L1:
block
signal s_st_rec3 : st_rec3
:= c_st_rec3_1 ;
--
component UUT
generic (G : integer) ;
port (
s_st_rec3 : inout st_rec3
) ;
end component ;
--
for CIS1 : UUT use entity WORK.ENT00209 ( ARCH00209 ) ;
begin
CIS1 : UUT
generic map (lowb+2)
port map (
s_st_rec3
)
;
end block L1 ;
end ARCH00209_Test_Bench ;
| gpl-3.0 | c2b2a95a6fa7905c56989e5844c12013 | 0.480207 | 3.401114 | false | true | false | false |
jairov4/accel-oil | impl/impl_test_pcie/simulation/behavioral/system_tb.vhd | 1 | 7,847 | -------------------------------------------------------------------------------
-- system_tb.vhd
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
-- START USER CODE (Do not remove this line)
-- User: Put your libraries here. Code in this
-- section will not be overwritten.
-- END USER CODE (Do not remove this line)
entity system_tb is
end system_tb;
architecture STRUCTURE of system_tb is
constant fpga_0_SRAM_ZBT_CLK_FB_pin_PERIOD : time := 8000.000000 ps;
constant fpga_0_clk_1_sys_clk_pin_PERIOD : time := 10000.000000 ps;
constant fpga_0_rst_1_sys_rst_pin_LENGTH : time := 160000 ps;
component system is
port (
fpga_0_DDR2_SDRAM_DDR2_Clk_pin : out std_logic_vector(1 downto 0);
fpga_0_DDR2_SDRAM_DDR2_Clk_n_pin : out std_logic_vector(1 downto 0);
fpga_0_DDR2_SDRAM_DDR2_CE_pin : out std_logic_vector(1 downto 0);
fpga_0_DDR2_SDRAM_DDR2_CS_n_pin : out std_logic_vector(1 downto 0);
fpga_0_DDR2_SDRAM_DDR2_ODT_pin : out std_logic_vector(1 downto 0);
fpga_0_DDR2_SDRAM_DDR2_RAS_n_pin : out std_logic;
fpga_0_DDR2_SDRAM_DDR2_CAS_n_pin : out std_logic;
fpga_0_DDR2_SDRAM_DDR2_WE_n_pin : out std_logic;
fpga_0_DDR2_SDRAM_DDR2_BankAddr_pin : out std_logic_vector(1 downto 0);
fpga_0_DDR2_SDRAM_DDR2_Addr_pin : out std_logic_vector(12 downto 0);
fpga_0_DDR2_SDRAM_DDR2_DQ_pin : inout std_logic_vector(63 downto 0);
fpga_0_DDR2_SDRAM_DDR2_DM_pin : out std_logic_vector(7 downto 0);
fpga_0_DDR2_SDRAM_DDR2_DQS_pin : inout std_logic_vector(7 downto 0);
fpga_0_DDR2_SDRAM_DDR2_DQS_n_pin : inout std_logic_vector(7 downto 0);
fpga_0_SRAM_Mem_A_pin : out std_logic_vector(7 to 30);
fpga_0_SRAM_Mem_CEN_pin : out std_logic;
fpga_0_SRAM_Mem_OEN_pin : out std_logic;
fpga_0_SRAM_Mem_WEN_pin : out std_logic;
fpga_0_SRAM_Mem_BEN_pin : out std_logic_vector(0 to 3);
fpga_0_SRAM_Mem_ADV_LDN_pin : out std_logic;
fpga_0_SRAM_Mem_DQ_pin : inout std_logic_vector(0 to 31);
fpga_0_SRAM_ZBT_CLK_OUT_pin : out std_logic;
fpga_0_SRAM_ZBT_CLK_FB_pin : in std_logic;
fpga_0_PCIe_Bridge_RXN_pin : in std_logic;
fpga_0_PCIe_Bridge_RXP_pin : in std_logic;
fpga_0_PCIe_Bridge_TXN_pin : out std_logic;
fpga_0_PCIe_Bridge_TXP_pin : out std_logic;
fpga_0_clk_1_sys_clk_pin : in std_logic;
fpga_0_rst_1_sys_rst_pin : in std_logic;
fpga_0_PCIe_Diff_Clk_IBUF_DS_P_pin : in std_logic;
fpga_0_PCIe_Diff_Clk_IBUF_DS_N_pin : in std_logic
);
end component;
-- Internal signals
signal fpga_0_DDR2_SDRAM_DDR2_Addr_pin : std_logic_vector(12 downto 0);
signal fpga_0_DDR2_SDRAM_DDR2_BankAddr_pin : std_logic_vector(1 downto 0);
signal fpga_0_DDR2_SDRAM_DDR2_CAS_n_pin : std_logic;
signal fpga_0_DDR2_SDRAM_DDR2_CE_pin : std_logic_vector(1 downto 0);
signal fpga_0_DDR2_SDRAM_DDR2_CS_n_pin : std_logic_vector(1 downto 0);
signal fpga_0_DDR2_SDRAM_DDR2_Clk_n_pin : std_logic_vector(1 downto 0);
signal fpga_0_DDR2_SDRAM_DDR2_Clk_pin : std_logic_vector(1 downto 0);
signal fpga_0_DDR2_SDRAM_DDR2_DM_pin : std_logic_vector(7 downto 0);
signal fpga_0_DDR2_SDRAM_DDR2_DQS_n_pin : std_logic_vector(7 downto 0);
signal fpga_0_DDR2_SDRAM_DDR2_DQS_pin : std_logic_vector(7 downto 0);
signal fpga_0_DDR2_SDRAM_DDR2_DQ_pin : std_logic_vector(63 downto 0);
signal fpga_0_DDR2_SDRAM_DDR2_ODT_pin : std_logic_vector(1 downto 0);
signal fpga_0_DDR2_SDRAM_DDR2_RAS_n_pin : std_logic;
signal fpga_0_DDR2_SDRAM_DDR2_WE_n_pin : std_logic;
signal fpga_0_PCIe_Bridge_RXN_pin : std_logic;
signal fpga_0_PCIe_Bridge_RXP_pin : std_logic;
signal fpga_0_PCIe_Bridge_TXN_pin : std_logic;
signal fpga_0_PCIe_Bridge_TXP_pin : std_logic;
signal fpga_0_PCIe_Diff_Clk_IBUF_DS_N_pin : std_logic;
signal fpga_0_PCIe_Diff_Clk_IBUF_DS_P_pin : std_logic;
signal fpga_0_SRAM_Mem_ADV_LDN_pin : std_logic;
signal fpga_0_SRAM_Mem_A_pin : std_logic_vector(7 to 30);
signal fpga_0_SRAM_Mem_BEN_pin : std_logic_vector(0 to 3);
signal fpga_0_SRAM_Mem_CEN_pin : std_logic;
signal fpga_0_SRAM_Mem_DQ_pin : std_logic_vector(0 to 31);
signal fpga_0_SRAM_Mem_OEN_pin : std_logic;
signal fpga_0_SRAM_Mem_WEN_pin : std_logic;
signal fpga_0_SRAM_ZBT_CLK_FB_pin : std_logic;
signal fpga_0_SRAM_ZBT_CLK_OUT_pin : std_logic;
signal fpga_0_clk_1_sys_clk_pin : std_logic;
signal fpga_0_rst_1_sys_rst_pin : std_logic;
-- START USER CODE (Do not remove this line)
-- User: Put your signals here. Code in this
-- section will not be overwritten.
-- END USER CODE (Do not remove this line)
begin
dut : system
port map (
fpga_0_DDR2_SDRAM_DDR2_Clk_pin => fpga_0_DDR2_SDRAM_DDR2_Clk_pin,
fpga_0_DDR2_SDRAM_DDR2_Clk_n_pin => fpga_0_DDR2_SDRAM_DDR2_Clk_n_pin,
fpga_0_DDR2_SDRAM_DDR2_CE_pin => fpga_0_DDR2_SDRAM_DDR2_CE_pin,
fpga_0_DDR2_SDRAM_DDR2_CS_n_pin => fpga_0_DDR2_SDRAM_DDR2_CS_n_pin,
fpga_0_DDR2_SDRAM_DDR2_ODT_pin => fpga_0_DDR2_SDRAM_DDR2_ODT_pin,
fpga_0_DDR2_SDRAM_DDR2_RAS_n_pin => fpga_0_DDR2_SDRAM_DDR2_RAS_n_pin,
fpga_0_DDR2_SDRAM_DDR2_CAS_n_pin => fpga_0_DDR2_SDRAM_DDR2_CAS_n_pin,
fpga_0_DDR2_SDRAM_DDR2_WE_n_pin => fpga_0_DDR2_SDRAM_DDR2_WE_n_pin,
fpga_0_DDR2_SDRAM_DDR2_BankAddr_pin => fpga_0_DDR2_SDRAM_DDR2_BankAddr_pin,
fpga_0_DDR2_SDRAM_DDR2_Addr_pin => fpga_0_DDR2_SDRAM_DDR2_Addr_pin,
fpga_0_DDR2_SDRAM_DDR2_DQ_pin => fpga_0_DDR2_SDRAM_DDR2_DQ_pin,
fpga_0_DDR2_SDRAM_DDR2_DM_pin => fpga_0_DDR2_SDRAM_DDR2_DM_pin,
fpga_0_DDR2_SDRAM_DDR2_DQS_pin => fpga_0_DDR2_SDRAM_DDR2_DQS_pin,
fpga_0_DDR2_SDRAM_DDR2_DQS_n_pin => fpga_0_DDR2_SDRAM_DDR2_DQS_n_pin,
fpga_0_SRAM_Mem_A_pin => fpga_0_SRAM_Mem_A_pin,
fpga_0_SRAM_Mem_CEN_pin => fpga_0_SRAM_Mem_CEN_pin,
fpga_0_SRAM_Mem_OEN_pin => fpga_0_SRAM_Mem_OEN_pin,
fpga_0_SRAM_Mem_WEN_pin => fpga_0_SRAM_Mem_WEN_pin,
fpga_0_SRAM_Mem_BEN_pin => fpga_0_SRAM_Mem_BEN_pin,
fpga_0_SRAM_Mem_ADV_LDN_pin => fpga_0_SRAM_Mem_ADV_LDN_pin,
fpga_0_SRAM_Mem_DQ_pin => fpga_0_SRAM_Mem_DQ_pin,
fpga_0_SRAM_ZBT_CLK_OUT_pin => fpga_0_SRAM_ZBT_CLK_OUT_pin,
fpga_0_SRAM_ZBT_CLK_FB_pin => fpga_0_SRAM_ZBT_CLK_FB_pin,
fpga_0_PCIe_Bridge_RXN_pin => fpga_0_PCIe_Bridge_RXN_pin,
fpga_0_PCIe_Bridge_RXP_pin => fpga_0_PCIe_Bridge_RXP_pin,
fpga_0_PCIe_Bridge_TXN_pin => fpga_0_PCIe_Bridge_TXN_pin,
fpga_0_PCIe_Bridge_TXP_pin => fpga_0_PCIe_Bridge_TXP_pin,
fpga_0_clk_1_sys_clk_pin => fpga_0_clk_1_sys_clk_pin,
fpga_0_rst_1_sys_rst_pin => fpga_0_rst_1_sys_rst_pin,
fpga_0_PCIe_Diff_Clk_IBUF_DS_P_pin => fpga_0_PCIe_Diff_Clk_IBUF_DS_P_pin,
fpga_0_PCIe_Diff_Clk_IBUF_DS_N_pin => fpga_0_PCIe_Diff_Clk_IBUF_DS_N_pin
);
-- Clock generator for fpga_0_SRAM_ZBT_CLK_FB_pin
process
begin
fpga_0_SRAM_ZBT_CLK_FB_pin <= '0';
loop
wait for (fpga_0_SRAM_ZBT_CLK_FB_pin_PERIOD/2);
fpga_0_SRAM_ZBT_CLK_FB_pin <= not fpga_0_SRAM_ZBT_CLK_FB_pin;
end loop;
end process;
-- Clock generator for fpga_0_clk_1_sys_clk_pin
process
begin
fpga_0_clk_1_sys_clk_pin <= '0';
loop
wait for (fpga_0_clk_1_sys_clk_pin_PERIOD/2);
fpga_0_clk_1_sys_clk_pin <= not fpga_0_clk_1_sys_clk_pin;
end loop;
end process;
-- Reset Generator for fpga_0_rst_1_sys_rst_pin
process
begin
fpga_0_rst_1_sys_rst_pin <= '0';
wait for (fpga_0_rst_1_sys_rst_pin_LENGTH);
fpga_0_rst_1_sys_rst_pin <= not fpga_0_rst_1_sys_rst_pin;
wait;
end process;
-- START USER CODE (Do not remove this line)
-- User: Put your stimulus here. Code in this
-- section will not be overwritten.
-- END USER CODE (Do not remove this line)
end architecture STRUCTURE;
| lgpl-3.0 | 38acddd05cefa5ec380187972cacb373 | 0.649675 | 2.592336 | false | false | false | false |
grwlf/vsim | vhdl_ct/ct00557.vhd | 1 | 4,775 | -- NEED RESULT: ARCH00557: Variable declarations - scalar globally static subtypes passed
-------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
-------------------------------------------------------------------------------
--
-- TEST NAME:
--
-- CT00557
--
-- AUTHOR:
--
-- A. Wilmot
--
-- TEST OBJECTIVES:
--
-- 4.3.1.3 (9)
--
-- DESIGN UNIT ORDERING:
--
-- GENERIC_STANDARD_TYPES(ARCH00557)
-- ENT00557_Test_Bench(ARCH00557_Test_Bench)
--
-- REVISION HISTORY:
--
-- 19-AUG-1987 - initial revision
--
-- NOTES:
--
-- self-checking
-- automatically generated
--
use WORK.STANDARD_TYPES.all ;
architecture ARCH00557 of GENERIC_STANDARD_TYPES is
begin
process
variable correct : boolean := true ;
variable va_boolean_1 : boolean
:= c_boolean_1 ;
variable va_bit_1 : bit
:= c_bit_1 ;
variable va_severity_level_1 : severity_level
:= c_severity_level_1 ;
variable va_character_1 : character
:= c_character_1 ;
variable va_t_enum1_1 : t_enum1
:= c_t_enum1_1 ;
variable va_st_enum1_1 : st_enum1
:= c_st_enum1_1 ;
variable va_integer_1 : integer
:= c_integer_1 ;
variable va_t_int1_1 : t_int1
:= c_t_int1_1 ;
variable va_st_int1_1 : st_int1
:= c_st_int1_1 ;
variable va_time_1 : time
:= c_time_1 ;
variable va_t_phys1_1 : t_phys1
:= c_t_phys1_1 ;
variable va_st_phys1_1 : st_phys1
:= c_st_phys1_1 ;
variable va_real_1 : real
:= c_real_1 ;
variable va_t_real1_1 : t_real1
:= c_t_real1_1 ;
variable va_st_real1_1 : st_real1
:= c_st_real1_1 ;
begin
correct := correct and va_boolean_1 = c_boolean_1 ;
correct := correct and va_bit_1 = c_bit_1 ;
correct := correct and va_severity_level_1 = c_severity_level_1 ;
correct := correct and va_character_1 = c_character_1 ;
correct := correct and va_t_enum1_1 = c_t_enum1_1 ;
correct := correct and va_st_enum1_1 = c_st_enum1_1 ;
correct := correct and va_integer_1 = c_integer_1 ;
correct := correct and va_t_int1_1 = c_t_int1_1 ;
correct := correct and va_st_int1_1 = c_st_int1_1 ;
correct := correct and va_time_1 = c_time_1 ;
correct := correct and va_t_phys1_1 = c_t_phys1_1 ;
correct := correct and va_st_phys1_1 = c_st_phys1_1 ;
correct := correct and va_real_1 = c_real_1 ;
correct := correct and va_t_real1_1 = c_t_real1_1 ;
correct := correct and va_st_real1_1 = c_st_real1_1 ;
va_boolean_1 := c_boolean_2 ;
va_bit_1 := c_bit_2 ;
va_severity_level_1 := c_severity_level_2 ;
va_character_1 := c_character_2 ;
va_t_enum1_1 := c_t_enum1_2 ;
va_st_enum1_1 := c_st_enum1_2 ;
va_integer_1 := c_integer_2 ;
va_t_int1_1 := c_t_int1_2 ;
va_st_int1_1 := c_st_int1_2 ;
va_time_1 := c_time_2 ;
va_t_phys1_1 := c_t_phys1_2 ;
va_st_phys1_1 := c_st_phys1_2 ;
va_real_1 := c_real_2 ;
va_t_real1_1 := c_t_real1_2 ;
va_st_real1_1 := c_st_real1_2 ;
correct := correct and va_boolean_1 = c_boolean_2 ;
correct := correct and va_bit_1 = c_bit_2 ;
correct := correct and va_severity_level_1 = c_severity_level_2 ;
correct := correct and va_character_1 = c_character_2 ;
correct := correct and va_t_enum1_1 = c_t_enum1_2 ;
correct := correct and va_st_enum1_1 = c_st_enum1_2 ;
correct := correct and va_integer_1 = c_integer_2 ;
correct := correct and va_t_int1_1 = c_t_int1_2 ;
correct := correct and va_st_int1_1 = c_st_int1_2 ;
correct := correct and va_time_1 = c_time_2 ;
correct := correct and va_t_phys1_1 = c_t_phys1_2 ;
correct := correct and va_st_phys1_1 = c_st_phys1_2 ;
correct := correct and va_real_1 = c_real_2 ;
correct := correct and va_t_real1_1 = c_t_real1_2 ;
correct := correct and va_st_real1_1 = c_st_real1_2 ;
test_report ( "ARCH00557" ,
"Variable declarations - scalar globally static subtypes" ,
correct) ;
wait ;
end process ;
end ARCH00557 ;
--
entity ENT00557_Test_Bench is
end ENT00557_Test_Bench ;
--
architecture ARCH00557_Test_Bench of ENT00557_Test_Bench is
begin
L1:
block
component UUT
end component ;
for CIS1 : UUT use entity WORK.GENERIC_STANDARD_TYPES ( ARCH00557 ) ;
begin
CIS1 : UUT ;
end block L1 ;
end ARCH00557_Test_Bench ;
| gpl-3.0 | 79cbc9ead79aa9f3ff788a9badec7a16 | 0.53801 | 2.989981 | false | true | false | false |
grwlf/vsim | vhdl_ct/ct00671.vhd | 1 | 7,161 | -- NEED RESULT: ARCH00671: Signal default initial values - static subtypes passed
-------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
-------------------------------------------------------------------------------
--
-- TEST NAME:
--
-- CT00671
--
-- AUTHOR:
--
-- A. Wilmot
--
-- TEST OBJECTIVES:
--
-- 4.3.1.2 (2)
--
-- DESIGN UNIT ORDERING:
--
-- E00000(ARCH00671)
-- ENT00671_Test_Bench(ARCH00671_Test_Bench)
--
-- REVISION HISTORY:
--
-- 01-SEP-1987 - initial revision
--
-- NOTES:
--
-- self-checking
-- automatically generated
--
use WORK.STANDARD_TYPES.all ;
--
architecture ARCH00671 of E00000 is
signal si_boolean_1 : boolean ;
signal si_boolean_2 : boolean
:= d_boolean ;
signal si_bit_1 : bit ;
signal si_bit_2 : bit
:= d_bit ;
signal si_severity_level_1 : severity_level ;
signal si_severity_level_2 : severity_level
:= d_severity_level ;
signal si_character_1 : character ;
signal si_character_2 : character
:= d_character ;
signal si_t_enum1_1 : t_enum1 ;
signal si_t_enum1_2 : t_enum1
:= d_t_enum1 ;
signal si_st_enum1_1 : st_enum1 ;
signal si_st_enum1_2 : st_enum1
:= d_st_enum1 ;
signal si_integer_1 : integer ;
signal si_integer_2 : integer
:= d_integer ;
signal si_t_int1_1 : t_int1 ;
signal si_t_int1_2 : t_int1
:= d_t_int1 ;
signal si_st_int1_1 : st_int1 ;
signal si_st_int1_2 : st_int1
:= d_st_int1 ;
signal si_time_1 : time ;
signal si_time_2 : time
:= d_time ;
signal si_t_phys1_1 : t_phys1 ;
signal si_t_phys1_2 : t_phys1
:= d_t_phys1 ;
signal si_st_phys1_1 : st_phys1 ;
signal si_st_phys1_2 : st_phys1
:= d_st_phys1 ;
signal si_real_1 : real ;
signal si_real_2 : real
:= d_real ;
signal si_t_real1_1 : t_real1 ;
signal si_t_real1_2 : t_real1
:= d_t_real1 ;
signal si_st_real1_1 : st_real1 ;
signal si_st_real1_2 : st_real1
:= d_st_real1 ;
signal si_st_bit_vector_1 : st_bit_vector ;
signal si_st_bit_vector_2 : st_bit_vector
:= d_st_bit_vector ;
signal si_st_string_1 : st_string ;
signal si_st_string_2 : st_string
:= d_st_string ;
signal si_t_rec1_1 : t_rec1 ;
signal si_t_rec1_2 : t_rec1
:= d_t_rec1 ;
signal si_st_rec1_1 : st_rec1 ;
signal si_st_rec1_2 : st_rec1
:= d_st_rec1 ;
signal si_t_rec2_1 : t_rec2 ;
signal si_t_rec2_2 : t_rec2
:= d_t_rec2 ;
signal si_st_rec2_1 : st_rec2 ;
signal si_st_rec2_2 : st_rec2
:= d_st_rec2 ;
signal si_t_rec3_1 : t_rec3 ;
signal si_t_rec3_2 : t_rec3
:= d_t_rec3 ;
signal si_st_rec3_1 : st_rec3 ;
signal si_st_rec3_2 : st_rec3
:= d_st_rec3 ;
signal si_st_arr1_1 : st_arr1 ;
signal si_st_arr1_2 : st_arr1
:= d_st_arr1 ;
signal si_st_arr2_1 : st_arr2 ;
signal si_st_arr2_2 : st_arr2
:= d_st_arr2 ;
signal si_st_arr3_1 : st_arr3 ;
signal si_st_arr3_2 : st_arr3
:= d_st_arr3 ;
begin
process
variable correct : boolean := true ;
begin
correct := correct and
si_boolean_1 = si_boolean_2 and
si_boolean_2 = d_boolean ;
correct := correct and
si_bit_1 = si_bit_2 and
si_bit_2 = d_bit ;
correct := correct and
si_severity_level_1 = si_severity_level_2 and
si_severity_level_2 = d_severity_level ;
correct := correct and
si_character_1 = si_character_2 and
si_character_2 = d_character ;
correct := correct and
si_t_enum1_1 = si_t_enum1_2 and
si_t_enum1_2 = d_t_enum1 ;
correct := correct and
si_st_enum1_1 = si_st_enum1_2 and
si_st_enum1_2 = d_st_enum1 ;
correct := correct and
si_integer_1 = si_integer_2 and
si_integer_2 = d_integer ;
correct := correct and
si_t_int1_1 = si_t_int1_2 and
si_t_int1_2 = d_t_int1 ;
correct := correct and
si_st_int1_1 = si_st_int1_2 and
si_st_int1_2 = d_st_int1 ;
correct := correct and
si_time_1 = si_time_2 and
si_time_2 = d_time ;
correct := correct and
si_t_phys1_1 = si_t_phys1_2 and
si_t_phys1_2 = d_t_phys1 ;
correct := correct and
si_st_phys1_1 = si_st_phys1_2 and
si_st_phys1_2 = d_st_phys1 ;
correct := correct and
si_real_1 = si_real_2 and
si_real_2 = d_real ;
correct := correct and
si_t_real1_1 = si_t_real1_2 and
si_t_real1_2 = d_t_real1 ;
correct := correct and
si_st_real1_1 = si_st_real1_2 and
si_st_real1_2 = d_st_real1 ;
correct := correct and
si_st_bit_vector_1 = si_st_bit_vector_2 and
si_st_bit_vector_2 = d_st_bit_vector ;
correct := correct and
si_st_string_1 = si_st_string_2 and
si_st_string_2 = d_st_string ;
correct := correct and
si_t_rec1_1 = si_t_rec1_2 and
si_t_rec1_2 = d_t_rec1 ;
correct := correct and
si_st_rec1_1 = si_st_rec1_2 and
si_st_rec1_2 = d_st_rec1 ;
correct := correct and
si_t_rec2_1 = si_t_rec2_2 and
si_t_rec2_2 = d_t_rec2 ;
correct := correct and
si_st_rec2_1 = si_st_rec2_2 and
si_st_rec2_2 = d_st_rec2 ;
correct := correct and
si_t_rec3_1 = si_t_rec3_2 and
si_t_rec3_2 = d_t_rec3 ;
correct := correct and
si_st_rec3_1 = si_st_rec3_2 and
si_st_rec3_2 = d_st_rec3 ;
correct := correct and
si_st_arr1_1 = si_st_arr1_2 and
si_st_arr1_2 = d_st_arr1 ;
correct := correct and
si_st_arr2_1 = si_st_arr2_2 and
si_st_arr2_2 = d_st_arr2 ;
correct := correct and
si_st_arr3_1 = si_st_arr3_2 and
si_st_arr3_2 = d_st_arr3 ;
test_report ( "ARCH00671" ,
"Signal default initial values - static subtypes" ,
correct) ;
wait ;
end process ;
end ARCH00671 ;
--
entity ENT00671_Test_Bench is
end ENT00671_Test_Bench ;
--
architecture ARCH00671_Test_Bench of ENT00671_Test_Bench is
begin
L1:
block
component UUT
end component ;
for CIS1 : UUT use entity WORK.E00000 ( ARCH00671 ) ;
begin
CIS1 : UUT ;
end block L1 ;
end ARCH00671_Test_Bench ;
| gpl-3.0 | c1836a236d5b23a95d4dd43de69e69cf | 0.486664 | 3.070755 | false | false | false | false |
jairov4/accel-oil | solution_virtex5_plb/impl/pcores/nfa_accept_samples_generic_hw_top_v1_01_a/synhdl/vhdl/nfa_initials_buckets_if_plb_master_if.vhd | 2 | 37,025 | -- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2014.1
-- Copyright (C) 2014 Xilinx Inc. All rights reserved.
--
-- ==============================================================
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity nfa_initials_buckets_if_ap_fifo_uw is
generic (
DATA_WIDTH : integer := 32;
ADDR_WIDTH : integer := 4;
DEPTH : integer := 16);
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
if_empty_n : OUT STD_LOGIC;
if_read : IN STD_LOGIC;
if_dout : OUT STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0);
if_full_n : OUT STD_LOGIC;
if_write : IN STD_LOGIC;
if_din : IN STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0);
use_word: OUT STD_LOGIC_VECTOR(ADDR_WIDTH -1 downto 0));
end entity;
architecture rtl of nfa_initials_buckets_if_ap_fifo_uw is
type memtype is array (0 to DEPTH - 1) of STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0);
signal mStorage : memtype;
signal mInPtr, mNextInPtr, mOutPtr : UNSIGNED(ADDR_WIDTH - 1 downto 0);
signal internal_empty_n, internal_full_n : STD_LOGIC;
signal internal_use_word : STD_LOGIC_VECTOR(ADDR_WIDTH -1 downto 0);
begin
mNextInPtr <= mInPtr + 1;
if_dout <= mStorage(CONV_INTEGER(mOutPtr));
if_empty_n <= internal_empty_n;
if_full_n <= internal_full_n;
use_word <= internal_use_word;
process (clk, reset)
begin
if reset = '1' then
mInPtr <= (others => '0');
mOutPtr <= (others => '0');
internal_use_word <= (others => '0');
else
if clk'event and clk = '1' then
if if_read = '1' and internal_empty_n = '1' then
mOutPtr <= mOutPtr + 1;
end if;
if if_write = '1' and internal_full_n = '1' then
mStorage(CONV_INTEGER(mInPtr)) <= if_din;
mInPtr <= mNextInPtr;
end if;
if (if_read = '1' and if_write = '0') then
internal_use_word <= internal_use_word - '1';
elsif (if_read = '0' and if_write = '1') then
internal_use_word <= internal_use_word + '1';
end if;
end if;
end if;
end process;
process (mInPtr, mOutPtr, mNextInPtr)
begin
if mInPtr = mOutPtr then
internal_empty_n <= '0';
else
internal_empty_n <= '1';
end if;
if mNextInPtr = mOutPtr then
internal_full_n <= '0';
else
internal_full_n <= '1';
end if;
end process;
end architecture;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity nfa_initials_buckets_if_plb_master_if is
generic
(
C_PLB_AWIDTH : integer := 32;
C_PLB_DWIDTH : integer := 64;
PLB_ADDR_SHIFT : integer := 3
);
port
(
-- ADD USER PORTS BELOW THIS LINE ------------------
--USER ports added here
-- ADD USER PORTS ABOVE THIS LINE ------------------
-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol ports, do not add to or delete
PLB_Clk : in std_logic;
PLB_Rst : in std_logic;
M_abort : out std_logic;
M_ABus : out std_logic_vector(0 to C_PLB_AWIDTH-1);
M_BE : out std_logic_vector(0 to C_PLB_DWIDTH/8-1);
M_busLock : out std_logic;
M_lockErr : out std_logic;
M_MSize : out std_logic_vector(0 to 1);
M_priority : out std_logic_vector(0 to 1);
M_rdBurst : out std_logic;
M_request : out std_logic;
M_RNW : out std_logic;
M_size : out std_logic_vector(0 to 3);
M_type : out std_logic_vector(0 to 2);
M_wrBurst : out std_logic;
M_wrDBus : out std_logic_vector(0 to C_PLB_DWIDTH-1);
PLB_MBusy : in std_logic;
PLB_MWrBTerm : in std_logic;
PLB_MWrDAck : in std_logic;
PLB_MAddrAck : in std_logic;
PLB_MRdBTerm : in std_logic;
PLB_MRdDAck : in std_logic;
PLB_MRdDBus : in std_logic_vector(0 to (C_PLB_DWIDTH-1));
PLB_MRdWdAddr : in std_logic_vector(0 to 3);
PLB_MRearbitrate : in std_logic;
PLB_MSSize : in std_logic_vector(0 to 1);
-- signals from user logic
BUS_RdData : out std_logic_vector(C_PLB_DWIDTH-1 downto 0); -- Bus read return data to user_logic
BUS_WrData : in std_logic_vector(C_PLB_DWIDTH-1 downto 0); -- Bus write data
BUS_address : in std_logic_vector(31 downto 0); -- physical address
BUS_size : in std_logic_vector(31 downto 0); -- burst size of word
BUS_req_nRW : in std_logic; -- req type 0: Read, 1: write
BUS_req_BE : in std_logic_vector(C_PLB_DWIDTH/8-1 downto 0); -- Bus write data byte enable
BUS_req_full_n : out std_logic; -- req Fifo full
BUS_req_push : in std_logic; -- req Fifo push (new request in)
BUS_rsp_nRW : out std_logic; -- return data FIFO rsp type
BUS_rsp_empty_n: out std_logic; -- return data FIFO empty
BUS_rsp_pop : in std_logic -- return data FIFO pop
);
attribute SIGIS : string;
attribute SIGIS of PLB_Clk : signal is "Clk";
attribute SIGIS of PLB_Rst : signal is "Rst";
end entity;
------------------------------------------------------------------------------
-- Architecture section
------------------------------------------------------------------------------
architecture IMP of nfa_initials_buckets_if_plb_master_if is
component nfa_initials_buckets_if_ap_fifo is
generic (
DATA_WIDTH : integer := 32;
ADDR_WIDTH : integer := 4;
DEPTH : integer := 16);
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
if_empty_n : OUT STD_LOGIC;
if_read : IN STD_LOGIC;
if_dout : OUT STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0);
if_full_n : OUT STD_LOGIC;
if_write : IN STD_LOGIC;
if_din : IN STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0));
end component;
component nfa_initials_buckets_if_ap_fifo_uw is
generic (
DATA_WIDTH : integer := 32;
ADDR_WIDTH : integer := 4;
DEPTH : integer := 16);
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
if_empty_n : OUT STD_LOGIC;
if_read : IN STD_LOGIC;
if_dout : OUT STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0);
if_full_n : OUT STD_LOGIC;
if_write : IN STD_LOGIC;
if_din : IN STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0);
use_word: OUT STD_LOGIC_VECTOR(ADDR_WIDTH -1 downto 0));
end component;
constant PLB_DW : integer := C_PLB_DWIDTH;
constant PLB_BYTE_COUNT : integer := PLB_DW/8;
constant REQ_FIFO_WIDTH : integer := 1 + PLB_BYTE_COUNT + 32 + 32; --nRW + BE + 32 bits phy addr + size
constant FIFO_ADDR_WIDTH : integer := 5;
constant FIFO_DEPTH : integer := 32;
-- request FIFO
signal req_fifo_empty_n : STD_LOGIC;
signal req_fifo_pop : STD_LOGIC;
signal req_fifo_dout : STD_LOGIC_VECTOR(REQ_FIFO_WIDTH - 1 downto 0);
signal req_fifo_full_n : STD_LOGIC;
signal req_fifo_push : STD_LOGIC;
signal req_fifo_din : STD_LOGIC_VECTOR(REQ_FIFO_WIDTH - 1 downto 0);
-- burst write counter (only push burst data in and ignore all burst write request except the first one)
signal req_burst_write: STD_LOGIC; -- whether last request is a burst write
signal req_burst_write_counter: STD_LOGIC_VECTOR(31 downto 0);
-- write data FIFO (for bus write data)
signal wd_fifo_empty_n : STD_LOGIC;
signal wd_fifo_pop : STD_LOGIC;
signal wd_fifo_dout : STD_LOGIC_VECTOR(PLB_DW - 1 downto 0);
signal wd_fifo_dout_mirror : STD_LOGIC_VECTOR(PLB_DW - 1 downto 0);
signal wd_fifo_full_n : STD_LOGIC;
signal wd_fifo_push : STD_LOGIC;
signal wd_fifo_din : STD_LOGIC_VECTOR(PLB_DW - 1 downto 0);
signal wd_fifo_use_word: STD_LOGIC_VECTOR(FIFO_ADDR_WIDTH -1 downto 0);
-- read data FIFO (for bus read returned data)
signal rd_fifo_empty_n : STD_LOGIC;
signal rd_fifo_pop : STD_LOGIC;
signal rd_fifo_dout : STD_LOGIC_VECTOR(PLB_DW - 1 downto 0);
signal rd_fifo_full_n : STD_LOGIC;
signal rd_fifo_push : STD_LOGIC;
signal rd_fifo_din : STD_LOGIC_VECTOR(PLB_DW - 1 downto 0);
signal rd_fifo_use_word: STD_LOGIC_VECTOR(FIFO_ADDR_WIDTH -1 downto 0);
signal req_address : std_logic_vector(0 to C_PLB_AWIDTH -1);-- bus request word address
signal req_fifo_dout_req_size : std_logic_vector(31 downto 0); -- req_size -1
signal req_size : std_logic_vector(0 to 27); -- burst size of 16 word block
signal request, req_nRW: std_logic;
signal req_BE : std_logic_vector(PLB_BYTE_COUNT-1 downto 0);
signal pending_rd_req_burst_mode: std_logic;
signal pending_rd_req_burst_size: std_logic_vector(3 downto 0);
signal pending_wr_req_burst_mode: std_logic;
signal pending_wr_req_burst_size: std_logic_vector(3 downto 0);
signal pending_read, pending_write: std_logic;
signal burst_mode, burst_last : std_logic;
signal burst_size : std_logic_vector(3 downto 0); -- maximum burst 16 words
--signals for write data mirror
signal conv_mode_comb : std_logic_vector(1 downto 0); -- 00: NO conv, 01: 128/32, 10: 64/32, 11: 128/64
signal conv_counter_comb: std_logic_vector(1 downto 0);
signal wr_data_phase : std_logic;
signal dataConv_last: std_logic;
signal dp_dataConv_last: std_logic;
signal dp_dataConv_word_addr: std_logic_vector(1 downto 0);
signal dp_dataConv_wd_conv_mode : std_logic_vector(1 downto 0); -- 00:NO conv, 01:128/32, 10:64/32, 11:128/64
signal dp_dataConv_wd_burst_counter: std_logic_vector(1 downto 0);
signal dp_dataConv_wd_BE: std_logic_vector(PLB_BYTE_COUNT-1 downto 0);
signal dp_PLB_MSSize : std_logic_vector(1 downto 0);
--signals for read data mirror
signal PLB_MRdDAck_reg : std_logic;
signal dp_dataConv_rd_conv_mode : std_logic_vector(1 downto 0);-- 00: NO conv, 01: 128/32, 10: 64/32, 11: 128/64
signal dp_dataConv_rd_burst_counter, dp_dataConv_rd_burst_counter_reg: std_logic_vector(1 downto 0);
signal PLB_MRdDBus_reverse : std_logic_vector(PLB_DW-1 downto 0);
-- signals with dp_ prefix stand for data phase signals
-- signals with req_ prefix stand for request phase signals
begin
-- interface to user logic
BUS_RdData <= rd_fifo_dout;
BUS_req_full_n <= req_fifo_full_n and wd_fifo_full_n;
BUS_rsp_nRW <= '0';
BUS_rsp_empty_n <= rd_fifo_empty_n;
-- interface to PLB
M_abort <= '0';
M_busLock <= '0';
M_lockErr <= '0';
M_MSize <= "01"; -- 00:32b dev, 01:64b, 10:128b, 11:256b
M_size <= "0000" when (burst_mode = '0' or burst_size = "0000") else "1011"; -- single rw or 64 bits burst
M_type <= "000"; -- memory trans
M_priority <= "00";
M_RNW <= not req_nRW;
M_rdBurst <= '1' when pending_rd_req_burst_mode = '1' and
(pending_rd_req_burst_size /= "0000" or dp_dataConv_rd_burst_counter /="00") else '0';
process (PLB_MSSize)
begin
M_wrBurst <= '0';
if (pending_wr_req_burst_mode = '1' and
(pending_wr_req_burst_size /= "0000" or dp_dataConv_wd_burst_counter /="00")) then
M_wrBurst <= '1';
elsif (request = '1' and req_nRW = '1' and pending_write = '0' and
burst_mode = '1' and burst_size /="0000" and wd_fifo_use_word > burst_size) then
M_wrBurst <= '1';
end if;
end process;
-- write data mirror section
process (PLB_MSSize)
begin
if (C_PLB_DWIDTH = 64 and PLB_MSSize = "00") then
conv_mode_comb <= "10"; -- conv 64:32
conv_counter_comb <= "01";
elsif (C_PLB_DWIDTH = 128 and PLB_MSSize = "01") then
conv_mode_comb <= "11"; -- conv 128:64
conv_counter_comb <= "01";
elsif (C_PLB_DWIDTH = 128 and PLB_MSSize = "00") then
conv_mode_comb <= "01"; -- conv 128:32
conv_counter_comb <= "11";
else
conv_mode_comb <= "00"; -- do not need conv
conv_counter_comb <= "00";
end if;
end process;
process (burst_mode, burst_size, conv_mode_comb, req_address, req_BE)
begin
dataConv_last <= '0';
if (burst_mode = '0' or burst_size = "0000") then
if (conv_mode_comb = "00") then -- no conv
dataConv_last <= '1';
elsif (conv_mode_comb = "10") then -- 64:32 conv
if (req_address(29)='1' or req_BE(PLB_BYTE_COUNT-1 downto PLB_BYTE_COUNT/2)=CONV_STD_LOGIC_VECTOR(0,PLB_BYTE_COUNT/2)) then
dataConv_last <= '1';
end if;
elsif (conv_mode_comb = "11") then -- 128:64 conv
if (req_address(28)='1' or req_BE(PLB_BYTE_COUNT-1 downto PLB_BYTE_COUNT/2)=CONV_STD_LOGIC_VECTOR(0,PLB_BYTE_COUNT/2)) then
dataConv_last <= '1';
end if;
elsif (conv_mode_comb = "01") then -- 128:32 conv
if (req_address(28 to 29) = "00" and req_BE(PLB_BYTE_COUNT-1 downto PLB_BYTE_COUNT/4)=CONV_STD_LOGIC_VECTOR(0,PLB_BYTE_COUNT*3/4)) then
dataConv_last <= '1';
elsif (req_address(28 to 29) = "01" and req_BE(PLB_BYTE_COUNT-1 downto PLB_BYTE_COUNT/2)=CONV_STD_LOGIC_VECTOR(0,PLB_BYTE_COUNT/2)) then
dataConv_last <= '1';
elsif (req_address(28 to 29) = "10" and req_BE(PLB_BYTE_COUNT-1 downto PLB_BYTE_COUNT*3/4)=CONV_STD_LOGIC_VECTOR(0,PLB_BYTE_COUNT/4)) then
dataConv_last <= '1';
elsif (req_address(28 to 29) = "11") then
dataConv_last <= '1';
end if;
end if;
end if;
end process;
process (PLB_Clk, PLB_Rst)
begin
if (PLB_Rst = '1') then
dp_dataConv_word_addr <= (others => '0');
dp_dataConv_wd_conv_mode <= (others =>'0');
dp_dataConv_wd_burst_counter <= (others => '0');
dp_dataConv_wd_BE <= (others => '0');
dp_dataConv_last <= '0';
wr_data_phase <= '0';
elsif (PLB_Clk'event and PLB_Clk = '1') then
if (PLB_MAddrAck = '1' and req_nRW = '1') then
dp_dataConv_wd_BE <= req_BE;
dp_dataConv_last <= dataConv_last;
end if;
if (PLB_MAddrAck = '1' and req_nRW = '1' and
(PLB_MWrDAck = '0' or (burst_mode = '1' and burst_size /= "0000"))) then
wr_data_phase <= '1';
end if;
if (PLB_MWrDAck = '1' and wr_data_phase = '1') then
if ((pending_wr_req_burst_size = "0000" and dp_dataConv_wd_burst_counter = "00") or
(pending_wr_req_burst_mode = '0')) then
wr_data_phase <= '0';
end if;
end if;
if (PLB_MAddrAck = '1' and req_nRW = '1' and dp_dataConv_wd_conv_mode = "00") then
if (PLB_MWrDAck = '0') then
-- only AddrAck asserted
dp_dataConv_wd_conv_mode <= conv_mode_comb;
dp_dataConv_word_addr <= req_address(28 to 29);
dp_dataConv_wd_burst_counter <= conv_counter_comb;
else
-- Xilinx PLB v4.6 support assert addrAck & wrDAck at the same cycle
if (dataConv_last = '0') then
dp_dataConv_wd_conv_mode <= conv_mode_comb;
end if;
if (PLB_MSSize = "00") then -- 32 bits slave
dp_dataConv_word_addr <= req_address(28 to 29) +1;
elsif (PLB_MSSize = "01") then -- 64 bits slave
dp_dataConv_word_addr <= req_address(28 to 29) +2;
end if;
if (conv_mode_comb /= "00") then -- need conv
dp_dataConv_wd_burst_counter <= conv_counter_comb -1;
end if;
end if;
end if;
if (wr_data_phase = '1' and PLB_MWrDAck = '1' and
((pending_wr_req_burst_mode = '1' and pending_wr_req_burst_size = "0000" and dp_dataConv_wd_burst_counter = "00") or
(pending_wr_req_burst_mode = '0' and dp_dataConv_last = '1'))) then
dp_dataConv_wd_conv_mode <= "00";
end if;
if (PLB_MWrDAck = '1' and wr_data_phase = '1') then
if (dp_PLB_MSSize = "01") then -- 64 bits slave
dp_dataConv_word_addr <= dp_dataConv_word_addr +2;
else
dp_dataConv_word_addr <= dp_dataConv_word_addr +1;
end if;
if ((pending_wr_req_burst_mode = '1' and pending_wr_req_burst_size /= "0000") or
dp_dataConv_wd_burst_counter /= "00") then
if (dp_dataConv_wd_burst_counter = "00") then
if (dp_dataConv_wd_conv_mode = "01") then -- 128/32
dp_dataConv_wd_burst_counter <= "11";
elsif (dp_dataConv_wd_conv_mode(1) = '1') then -- 64/32 or 128/64
dp_dataConv_wd_burst_counter <= "01";
end if;
else
dp_dataConv_wd_burst_counter <= dp_dataConv_wd_burst_counter -1;
end if;
end if;
end if;
end if;
end process;
process(PLB_MWrDAck, wr_data_phase, dp_dataConv_wd_burst_counter, burst_mode, conv_counter_comb, conv_mode_comb, req_BE)
begin
wd_fifo_pop <= '0';
if (PLB_MWrDAck = '1') then
if (wr_data_phase = '1') then
if ((pending_wr_req_burst_mode = '1' and dp_dataConv_wd_burst_counter = "00") or
(dp_dataConv_wd_conv_mode /= "00" and dp_dataConv_last = '1') or
dp_dataConv_wd_conv_mode = "00" )then
wd_fifo_pop <= '1';
end if;
else
-- got addrAck and wrDAck at the same cycle
if (burst_mode = '1' and burst_size /= "0000" and conv_counter_comb = "00") then
wd_fifo_pop <= '1';
elsif ((burst_mode = '0' or burst_size = "0000") and dataConv_last = '1') then
wd_fifo_pop <= '1';
end if;
end if;
end if;
end process;
process(wd_fifo_dout, wr_data_phase, req_address, dp_dataConv_wd_conv_mode, dp_dataConv_word_addr)
begin
wd_fifo_dout_mirror <= wd_fifo_dout;
if (wr_data_phase = '0') then -- we do not know slave bus width, perform default convert
if (C_PLB_DWIDTH = 32) then
wd_fifo_dout_mirror <= wd_fifo_dout;
elsif (C_PLB_DWIDTH = 64) then
if (req_address(29) = '0') then
wd_fifo_dout_mirror <= wd_fifo_dout;
else
wd_fifo_dout_mirror(PLB_DW/2-1 downto 0) <= wd_fifo_dout(PLB_DW-1 downto PLB_DW/2);
wd_fifo_dout_mirror(PLB_DW-1 downto PLB_DW/2) <= wd_fifo_dout(PLB_DW-1 downto PLB_DW/2);
end if;
elsif (C_PLB_DWIDTH = 128) then
case req_address(28 to 29) is
when "00" =>
wd_fifo_dout_mirror <= wd_fifo_dout;
when "01" =>
wd_fifo_dout_mirror(C_PLB_DWIDTH/4-1 downto 0) <= wd_fifo_dout(C_PLB_DWIDTH/2-1 downto C_PLB_DWIDTH/4);
wd_fifo_dout_mirror(C_PLB_DWIDTH-1 downto C_PLB_DWIDTH/4) <= wd_fifo_dout(C_PLB_DWIDTH-1 downto C_PLB_DWIDTH/4);
when "10" =>
wd_fifo_dout_mirror(C_PLB_DWIDTH/2-1 downto 0) <= wd_fifo_dout(C_PLB_DWIDTH-1 downto C_PLB_DWIDTH/2);
wd_fifo_dout_mirror(C_PLB_DWIDTH-1 downto C_PLB_DWIDTH/2) <= wd_fifo_dout(C_PLB_DWIDTH-1 downto C_PLB_DWIDTH/2);
when "11" =>
wd_fifo_dout_mirror(C_PLB_DWIDTH/4-1 downto 0) <= wd_fifo_dout(C_PLB_DWIDTH-1 downto C_PLB_DWIDTH*3/4);
wd_fifo_dout_mirror(C_PLB_DWIDTH/2-1 downto C_PLB_DWIDTH/4) <= wd_fifo_dout(C_PLB_DWIDTH-1 downto C_PLB_DWIDTH*3/4);
wd_fifo_dout_mirror(C_PLB_DWIDTH*3/4-1 downto C_PLB_DWIDTH/2) <= wd_fifo_dout(C_PLB_DWIDTH-1 downto C_PLB_DWIDTH*3/4);
wd_fifo_dout_mirror(C_PLB_DWIDTH-1 downto C_PLB_DWIDTH*3/4) <= wd_fifo_dout(C_PLB_DWIDTH-1 downto C_PLB_DWIDTH*3/4);
when others => null;
end case;
end if;
else -- in data phase
wd_fifo_dout_mirror <= wd_fifo_dout;
if ((dp_dataConv_wd_conv_mode = "10" and dp_dataConv_word_addr(0) = '1') or
(dp_dataConv_wd_conv_mode = "11" and dp_dataConv_word_addr(1) = '1')) then -- conv 64:32 or 128:64
wd_fifo_dout_mirror(C_PLB_DWIDTH/2-1 downto 0) <= wd_fifo_dout(C_PLB_DWIDTH-1 downto C_PLB_DWIDTH/2);
wd_fifo_dout_mirror(C_PLB_DWIDTH-1 downto C_PLB_DWIDTH/2) <= wd_fifo_dout(C_PLB_DWIDTH-1 downto C_PLB_DWIDTH/2);
elsif (dp_dataConv_wd_conv_mode = "01") then -- conv 128:32
case dp_dataConv_word_addr is
when "00" =>
wd_fifo_dout_mirror <= wd_fifo_dout;
when "01" =>
wd_fifo_dout_mirror(C_PLB_DWIDTH/4-1 downto 0) <= wd_fifo_dout(C_PLB_DWIDTH/2-1 downto C_PLB_DWIDTH/4);
when "10" =>
wd_fifo_dout_mirror(C_PLB_DWIDTH/4-1 downto 0) <= wd_fifo_dout(C_PLB_DWIDTH*3/4-1 downto C_PLB_DWIDTH/2);
when "11" =>
wd_fifo_dout_mirror(C_PLB_DWIDTH/4-1 downto 0) <= wd_fifo_dout(C_PLB_DWIDTH-1 downto C_PLB_DWIDTH*3/4);
when others => null;
end case;
end if;
end if;
end process;
process(wd_fifo_dout_mirror)
variable i: integer;
begin
for i in 0 to C_PLB_DWIDTH-1 loop
M_wrDBus(i) <= wd_fifo_dout_mirror(i);
end loop;
end process;
process (request, req_nRW, pending_read, burst_mode, rd_fifo_full_n, rd_fifo_use_word,
pending_write, wd_fifo_empty_n, wd_fifo_use_word, burst_size)
begin
M_request <= '0';
if (request = '1') then
if (req_nRW = '0' and pending_read = '0') then -- read request
if ((burst_mode = '0' or burst_size = "0000") and rd_fifo_full_n = '1') then
M_request <= '1';
elsif (rd_fifo_use_word(4) = '0') then -- 16 words slots available
M_request <= '1';
end if;
elsif (req_nRW = '1' and pending_write = '0') then -- write request
if ((burst_mode = '0' or burst_size = "0000") and wd_fifo_empty_n = '1') then
M_request <= '1';
elsif (wd_fifo_use_word > burst_size) then
M_request <= '1';
end if;
end if;
end if;
end process;
M_ABus(0 to C_PLB_AWIDTH - 1) <= req_address;
process(req_nRW, burst_mode, burst_size, req_BE)
variable i:integer;
begin
M_BE <= (others => '0');
if (burst_mode = '1') then
if (burst_size = "0000") then
M_BE <= (others => '1'); -- first single,then burst 16
else
M_BE(0 to 3) <= burst_size; -- fixed length burst
end if;
elsif (req_nRW = '0') then
M_BE <= (others => '1');
else
for i in 0 to PLB_BYTE_COUNT-1 loop
M_BE(i) <= req_BE(i);
end loop;
end if;
end process;
-- user req FIFO, for both read request and write request
U_req_nfa_initials_buckets_if_fifo: component nfa_initials_buckets_if_ap_fifo
generic map(
DATA_WIDTH => REQ_FIFO_WIDTH,
ADDR_WIDTH => FIFO_ADDR_WIDTH,
DEPTH => FIFO_DEPTH)
port map(
clk => PLB_Clk,
reset => PLB_Rst,
if_empty_n => req_fifo_empty_n,
if_read => req_fifo_pop,
if_dout => req_fifo_dout,
if_full_n => req_fifo_full_n,
if_write => req_fifo_push,
if_din => req_fifo_din
);
req_fifo_push <= BUS_req_push and not req_burst_write;
req_fifo_din <= BUS_req_nRW & BUS_req_BE & BUS_address & BUS_size;
req_fifo_dout_req_size <= req_fifo_dout(31 downto 0) -1;
process (PLB_Clk, PLB_Rst)
begin
if (PLB_Rst = '1') then
req_burst_write <= '0';
req_burst_write_counter <= (others => '0');
elsif (PLB_Clk'event and PLB_Clk = '1') then
if (req_fifo_push = '1' and BUS_req_nRW = '1' and BUS_size(31 downto 1) /= "0000000000000000000000000000000") then
req_burst_write <= '1';
req_burst_write_counter <= BUS_size - 1;
end if;
if (BUS_req_push = '1' and BUS_req_nRW = '1' and req_burst_write = '1') then
req_burst_write_counter <= req_burst_write_counter -1;
end if;
if (BUS_req_push = '1' and BUS_req_nRW = '1' and req_burst_write_counter = X"00000001") then-- last burst write data
req_burst_write <= '0';
end if;
end if;
end process;
process (PLB_Clk, PLB_Rst)
begin
if (PLB_Rst = '1') then
request <= '0';
req_size <= (others => '0');
req_nRW <= '0';
req_address(0 to C_PLB_AWIDTH - 1) <= (others => '0');
burst_mode <= '0';
burst_size <= (others => '0');
req_fifo_pop <= '0';
elsif (PLB_Clk'event and PLB_Clk = '1') then
req_fifo_pop <= '0';
if ((request = '0' and req_fifo_empty_n = '1') or PLB_MAddrAck = '1') then
if (PLB_MAddrAck = '1' and (burst_mode = '0' or burst_size ="0000") and dataConv_last = '0') then
request <= '1';
if (conv_mode_comb(1) = '1') then -- 2:1 conv
req_BE(PLB_BYTE_COUNT/2-1 downto 0) <= (others => '0');
else -- 128:32
if (req_address(28 to 29) = "00") then
req_BE(PLB_BYTE_COUNT/4-1 downto 0) <= (others => '0');
elsif (req_address(28 to 29) = "01") then
req_BE(PLB_BYTE_COUNT/2-1 downto PLB_BYTE_COUNT/4) <= (others => '0');
elsif (req_address(28 to 29) = "10") then
req_BE(PLB_BYTE_COUNT*3/4-1 downto PLB_BYTE_COUNT/2) <= (others => '0');
end if;
end if;
if (PLB_MSSize = "00") then -- 32 bits slave
req_address <= req_address + 4;
elsif (PLB_MSSize = "01") then -- 64 slave
req_address <= req_address + 8;
end if;-- 128 bits slave does not need conversion cycle
elsif (PLB_MAddrAck = '1' and burst_mode = '1' and burst_last = '0') then
request <= '1'; -- req next burst section, this will be pending until previous burst finished
req_size(0 to 27) <= req_size(0 to 27) - 1;
req_address(0 to C_PLB_AWIDTH - PLB_ADDR_SHIFT - 1) <= req_address(0 to C_PLB_AWIDTH -PLB_ADDR_SHIFT -1) + burst_size +1;
req_address(C_PLB_AWIDTH-PLB_ADDR_SHIFT to C_PLB_AWIDTH-1) <= (others => '0');
-- low bits of addr must be reset for possible data_conv modifications of 10 lines above
burst_mode <= '1';
burst_size <= "1111"; -- burst 16 words
else
if (req_fifo_empty_n = '1') then
req_fifo_pop <= '1';
end if;
request <= req_fifo_empty_n; -- fetch next user_req, may be a vaild req or a null req
req_size(0 to 27) <= req_fifo_dout_req_size(31 downto 4); --remaining burst transfer except current one
req_nRW <= req_fifo_dout(REQ_FIFO_WIDTH-1);
req_BE <= req_fifo_dout(REQ_FIFO_WIDTH-2 downto 64);
req_address <= req_fifo_dout(63 downto 32);
if (req_fifo_dout(REQ_FIFO_WIDTH-1) = '0') then -- read request
req_address(C_PLB_AWIDTH-PLB_ADDR_SHIFT to C_PLB_AWIDTH-1) <= (others => '0');
end if;
-- long burst request will be split to 1stReq: 1-16 words, all next req: 16 words
if (req_fifo_dout_req_size /= X"00000000") then -- more than 1 word, burst
burst_mode <= req_fifo_empty_n; -- fetched req may be null req
-- req of burst 17 will be single + burst 16, please check burst_size also
else
burst_mode <= '0';
end if;
burst_size(3 downto 0) <= req_fifo_dout_req_size(3 downto 0);-- 0:single, 1-15: burst 2-16words
end if;
end if;
end if;
end process;
process (PLB_Clk, PLB_Rst)
begin
if (PLB_Rst = '1') then
pending_read <= '0';
pending_write <= '0';
dp_PLB_MSSize <= (others => '0');
elsif (PLB_Clk'event and PLB_Clk = '1') then
if (PLB_MRdDAck = '1' and
((pending_rd_req_burst_mode = '1' and pending_rd_req_burst_size = "0000" and dp_dataConv_rd_burst_counter = "00") or
(pending_rd_req_burst_mode = '0'))) then
pending_read <= '0';
elsif (PLB_MAddrAck = '1' and req_nRW='0') then
pending_read <= '1';
end if;
if (PLB_MWrDAck = '1' and wr_data_phase = '1' and
((pending_wr_req_burst_mode = '1' and pending_wr_req_burst_size = "0000" and dp_dataConv_wd_burst_counter = "00") or
pending_wr_req_burst_mode = '0')) then
pending_write <= '0';
elsif (PLB_MAddrAck = '1' and req_nRW='1' and
(PLB_MWrDAck = '0' or burst_size /= "0000")) then
pending_write <= '1';
end if;
if (PLB_MAddrAck = '1') then
dp_PLB_MSSize <= PLB_MSSize;
end if;
end if;
end process;
process(req_size)
begin
if (req_size(0 to 27) = "000000000000000000000000000") then
burst_last <= '1'; -- one request is ok
else
burst_last <= '0';
end if;
end process;
-- user write data FIFO, for data of bus write request
U_wd_nfa_initials_buckets_if_fifo: component nfa_initials_buckets_if_ap_fifo_uw
generic map(
DATA_WIDTH => PLB_DW,
ADDR_WIDTH => FIFO_ADDR_WIDTH,
DEPTH => FIFO_DEPTH)
port map(
clk => PLB_Clk,
reset => PLB_Rst,
if_empty_n => wd_fifo_empty_n,
if_read => wd_fifo_pop,
if_dout => wd_fifo_dout,
if_full_n => wd_fifo_full_n,
if_write => wd_fifo_push,
if_din => wd_fifo_din,
use_word => wd_fifo_use_word
);
wd_fifo_push <= BUS_req_push and BUS_req_nRW;
wd_fifo_din <= BUS_WrData;
-- returned bus read data fifo
U_rd_nfa_initials_buckets_if_fifo: component nfa_initials_buckets_if_ap_fifo_uw
generic map(
DATA_WIDTH => PLB_DW,
ADDR_WIDTH => FIFO_ADDR_WIDTH,
DEPTH => FIFO_DEPTH)
port map(
clk => PLB_Clk,
reset => PLB_Rst,
if_empty_n => rd_fifo_empty_n,
if_read => rd_fifo_pop,
if_dout => rd_fifo_dout,
if_full_n => rd_fifo_full_n,
if_write => rd_fifo_push,
if_din => rd_fifo_din,
use_word => rd_fifo_use_word
);
process (PLB_Clk, PLB_Rst)
begin
if (PLB_Rst = '1') then
dp_dataConv_rd_conv_mode <= (others =>'0');
dp_dataConv_rd_burst_counter <= (others => '0');
dp_dataConv_rd_burst_counter_reg <= (others => '0');
PLB_MRdDAck_reg <= '0';
elsif (PLB_Clk'event and PLB_Clk = '1') then
if (PLB_MAddrAck = '1' and req_nRW = '0' and dp_dataConv_rd_conv_mode = "00") then
dp_dataConv_rd_conv_mode <= conv_mode_comb;
dp_dataConv_rd_burst_counter <= conv_counter_comb;
end if;
if (PLB_MRdDAck = '1' and
((pending_rd_req_burst_mode = '1' and (pending_rd_req_burst_size = "0000" and dp_dataConv_rd_burst_counter = "00")) or
(pending_rd_req_burst_mode = '0' and dp_dataConv_rd_burst_counter = "00")))then
dp_dataConv_rd_conv_mode <= "00";
end if;
if (PLB_MRdDAck = '1' and
((pending_rd_req_burst_mode = '1' and (pending_rd_req_burst_size /= "0000" or dp_dataConv_rd_burst_counter /= "00")) or
(pending_rd_req_burst_mode = '0' and dp_dataConv_rd_burst_counter /= "00")))then
if (dp_dataConv_rd_burst_counter = "00") then
if (dp_dataConv_rd_conv_mode = "01") then -- 128/32
dp_dataConv_rd_burst_counter <= "11";
elsif (dp_dataConv_rd_conv_mode(1) = '1') then -- 64/32 or 128/64
dp_dataConv_rd_burst_counter <= "01";
end if;
else
dp_dataConv_rd_burst_counter <= dp_dataConv_rd_burst_counter -1;
end if;
end if;
dp_dataConv_rd_burst_counter_reg <= dp_dataConv_rd_burst_counter;
PLB_MRdDAck_reg <= PLB_MRdDAck;
end if;
end process;
rd_fifo_push <= '1' when PLB_MRdDAck_reg = '1' and dp_dataConv_rd_burst_counter_reg = "00" else '0';
process(PLB_MRdDBus)
variable i: integer;
begin
-- change to little endian
for i in 0 to C_PLB_DWIDTH-1 loop
PLB_MRdDBus_reverse(i) <= PLB_MRdDBus(i);
end loop;
end process;
process(PLB_Clk, PLB_Rst)
begin
if (PLB_Rst = '1') then
rd_fifo_din <= (others => '0');
elsif (PLB_Clk'event and PLB_Clk = '1') then
if (PLB_MRdDAck = '1') then
case dp_dataConv_rd_conv_mode is
when "00" => rd_fifo_din <= PLB_MRdDBus_reverse;
when "10" | "11" =>
if (dp_dataConv_rd_burst_counter = "00") then
rd_fifo_din(PLB_DW-1 downto PLB_DW/2) <= PLB_MRdDBus_reverse(PLB_DW/2-1 downto 0);
else
rd_fifo_din(PLB_DW/2-1 downto 0) <= PLB_MRdDBus_reverse(PLB_DW/2-1 downto 0);
end if;
when "01" =>
case dp_dataConv_rd_burst_counter is
when "00" =>
rd_fifo_din(PLB_DW-1 downto PLB_DW*3/4) <= PLB_MRdDBus_reverse(PLB_DW/4-1 downto 0);
when "01" =>
rd_fifo_din(PLB_DW*3/4-1 downto PLB_DW/2) <= PLB_MRdDBus_reverse(PLB_DW/4-1 downto 0);
when "10" =>
rd_fifo_din(PLB_DW/2-1 downto PLB_DW/4) <= PLB_MRdDBus_reverse(PLB_DW/4-1 downto 0);
when "11" =>
rd_fifo_din(PLB_DW/4-1 downto 0) <= PLB_MRdDBus_reverse(PLB_DW/4-1 downto 0);
when others => null;
end case;
when others => null;
end case;
end if;
end if;
end process;
rd_fifo_pop <= BUS_rsp_pop;
pending_read_req_p: process (PLB_Clk, PLB_Rst)
begin
if (PLB_Rst = '1') then
pending_rd_req_burst_mode <= '0';
pending_rd_req_burst_size <= (others => '0');
elsif (PLB_Clk'event and PLB_Clk = '1') then
if (PLB_MAddrAck = '1' and req_nRW = '0') then
if (burst_mode = '1' and burst_size /= "0000") then
pending_rd_req_burst_mode <= burst_mode;
end if;
pending_rd_req_burst_size <= burst_size;
elsif (PLB_MRdDAck = '1' and pending_rd_req_burst_mode = '1') then
if (dp_dataConv_rd_burst_counter = "00") then
pending_rd_req_burst_size <= pending_rd_req_burst_size - 1;
if (pending_rd_req_burst_size = "0000") then
pending_rd_req_burst_mode <= '0';
end if;
end if;
end if;
end if;
end process;
pending_write_req_p: process (PLB_Clk, PLB_Rst)
begin
if (PLB_Rst = '1') then
pending_wr_req_burst_mode <= '0';
pending_wr_req_burst_size <= (others => '0');
elsif (PLB_Clk'event and PLB_Clk = '1') then
if (PLB_MAddrAck = '1' and req_nRW = '1') then
if (burst_mode = '1' and burst_size /= "0000") then
pending_wr_req_burst_mode <= '1';
end if;
pending_wr_req_burst_size <= burst_size;
if (PLB_MWrDAck = '1') then
if (conv_counter_comb = "00") then
pending_wr_req_burst_size <= burst_size -1;
else
pending_wr_req_burst_size <= burst_size;
end if;
end if;
elsif (PLB_MWrDAck = '1' and pending_wr_req_burst_mode = '1') then
if (dp_dataConv_wd_burst_counter = "00") then
pending_wr_req_burst_size <= pending_wr_req_burst_size - 1;
if (pending_wr_req_burst_size = "0000") then
pending_wr_req_burst_mode <= '0';
end if;
end if;
end if;
end if;
end process;
end IMP;
| lgpl-3.0 | 513033388cffbb5dcab1fe3030864951 | 0.535152 | 3.309349 | false | false | false | false |
grwlf/vsim | vhdl/overload1.vhd | 1 | 681 | -- Demonstrates overloading of procedures
entity main is
end entity main;
architecture main of main is
type arr01 is array (0 to 1) of integer;
procedure p1(variable f1 : in integer; variable f2 : out integer) is
begin
f2 := f1;
end procedure p1;
procedure p1(variable f1 : in integer; variable f2 : out arr01) is
begin
f2(0) := f1;
end procedure p1;
begin
main: process
variable a : arr01 := (others => 33);
variable i : integer := 1;
variable o : integer := 0;
begin
p1(i, o);
p1(i, a);
assert false report "end of simulation" severity failure;
end process;
end architecture main;
| gpl-3.0 | 0bb59763700291a1a62c0580d21c9b13 | 0.621145 | 3.422111 | false | false | false | false |
grwlf/vsim | vhdl_ct/ct00542.vhd | 1 | 8,398 | -- NEED RESULT: ARCH00542: Ranges of various signal attributes passed
-------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
-------------------------------------------------------------------------------
--
-- TEST NAME:
--
-- CT00542
--
-- AUTHOR:
--
-- D. Hyman
--
-- TEST OBJECTIVES:
--
-- 14.1 (16) (MOSTLY TBD)
--
-- DESIGN UNIT ORDERING:
--
-- E00000(ARCH00542)
-- ENT00542_Test_Bench(ARCH00542_Test_Bench)
--
-- REVISION HISTORY:
--
-- 18-AUG-1987 - initial revision
--
-- NOTES:
--
-- self-checking
--
-- THIS IS A STATIC TEST ONLY
--
--
use WORK.STANDARD_TYPES.all ;
architecture ARCH00542 of E00000 is
signal sig_string : st_string ;
signal sig_bit_vector : st_bit_vector ;
signal sig_boolean_vector : st_boolean_vector ;
signal sig_severity_level_vector : st_severity_level_vector ;
signal sig_integer_vector : st_integer_vector ;
signal sig_arr3_vector : st_arr3_vector ;
signal sig_enum1 : st_enum1 ;
signal sig_int1 : st_int1 ;
signal sig_phys1 : st_phys1 ;
signal sig_real1 : st_real1 ;
signal sig_rec1 : st_rec1 ;
signal sig_rec2 : st_rec2 ;
signal sig_rec3 : st_rec3 ;
signal sig_arr1 : st_arr1 ;
signal sig_arr2 : st_arr2 ;
signal sig_arr3 : st_arr3 ;
signal sig_bit : bit ;
signal sig_boolean : boolean ;
signal sig_character : character ;
signal sig_integer : integer ;
signal sig_real : real ;
signal sig_time : time ;
------ [block_declarative_item]...
begin
P :
process
variable t,u : time ;
variable a,b,c,d : boolean;
------ [process_declarative_item]...
begin
a := sig_string'stable and
sig_bit_vector'stable and
sig_boolean_vector'stable and
sig_severity_level_vector'stable and
sig_integer_vector'stable and
sig_arr3_vector'stable and
sig_enum1'stable and
sig_int1'stable and
sig_phys1'stable and
sig_real1'stable and
sig_rec1'stable and
sig_rec2'stable and
sig_rec3'stable and
sig_arr1'stable and
sig_arr2'stable and
sig_arr3'stable and
sig_bit'stable and
sig_boolean'stable and
sig_character'stable and
sig_integer'stable and
sig_real'stable and
sig_time'stable ;
b := sig_string'quiet and
sig_bit_vector'quiet and
sig_boolean_vector'quiet and
sig_severity_level_vector'quiet and
sig_integer_vector'quiet and
sig_arr3_vector'quiet and
sig_enum1'quiet and
sig_int1'quiet and
sig_phys1'quiet and
sig_real1'quiet and
sig_rec1'quiet and
sig_rec2'quiet and
sig_rec3'quiet and
sig_arr1'quiet and
sig_arr2'quiet and
sig_arr3'quiet and
sig_bit'quiet and
sig_boolean'quiet and
sig_character'quiet and
sig_integer'quiet and
sig_real'quiet and
sig_time'quiet ;
c := sig_string'event and
sig_bit_vector'event and
sig_boolean_vector'event and
sig_severity_level_vector'event and
sig_integer_vector'event and
sig_arr3_vector'event and
sig_enum1'event and
sig_int1'event and
sig_phys1'event and
sig_real1'event and
sig_rec1'event and
sig_rec2'event and
sig_rec3'event and
sig_arr1'event and
sig_arr2'event and
sig_arr3'event and
sig_bit'event and
sig_boolean'event and
sig_character'event and
sig_integer'event and
sig_real'event and
sig_time'event ;
d := sig_string'active and
sig_bit_vector'active and
sig_boolean_vector'active and
sig_severity_level_vector'active and
sig_integer_vector'active and
sig_arr3_vector'active and
sig_enum1'active and
sig_int1'active and
sig_phys1'active and
sig_real1'active and
sig_rec1'active and
sig_rec2'active and
sig_rec3'active and
sig_arr1'active and
sig_arr2'active and
sig_arr3'active and
sig_bit'active and
sig_boolean'active and
sig_character'active and
sig_integer'active and
sig_real'active and
sig_time'active ;
t := sig_string'last_event +
sig_bit_vector'last_event +
sig_boolean_vector'last_event +
sig_severity_level_vector'last_event +
sig_integer_vector'last_event +
sig_arr3_vector'last_event +
sig_enum1'last_event +
sig_int1'last_event +
sig_phys1'last_event +
sig_real1'last_event +
sig_rec1'last_event +
sig_rec2'last_event +
sig_rec3'last_event +
sig_arr1'last_event +
sig_arr2'last_event +
sig_arr3'last_event +
sig_bit'last_event +
sig_boolean'last_event +
sig_character'last_event +
sig_integer'last_event +
sig_real'last_event +
sig_time'last_event ;
u := sig_string'last_active +
sig_bit_vector'last_active +
sig_boolean_vector'last_active +
sig_severity_level_vector'last_active +
sig_integer_vector'last_active +
sig_arr3_vector'last_active +
sig_enum1'last_active +
sig_int1'last_active +
sig_phys1'last_active +
sig_real1'last_active +
sig_rec1'last_active +
sig_rec2'last_active +
sig_rec3'last_active +
sig_arr1'last_active +
sig_arr2'last_active +
sig_arr3'last_active +
sig_bit'last_active +
sig_boolean'last_active +
sig_character'last_active +
sig_integer'last_active +
sig_real'last_active +
sig_time'last_active ;
-- sig_string'delayed(1 ns) <= sig_string'last_value;
-- sig_bit_vector'delayed(1 ns) <= sig_bit_vector'last_value;
-- sig_boolean_vector'delayed(1 ns) <= sig_boolean_vector'last_value;
-- sig_severity_level_vector'delayed(1 ns) <=
-- sig_severity_level_vector'last_value;
-- sig_integer_vector'delayed(1 ns) <= sig_integer_vector'last_value;
-- sig_arr3_vector'delayed(1 ns) <= sig_arr3_vector'last_value;
-- sig_enum1'delayed(1 ns) <= sig_enum1'last_value;
-- sig_int1'delayed(1 ns) <= sig_int1'last_value;
-- sig_phys1'delayed(1 ns) <= sig_phys1'last_value;
-- sig_real1'delayed(1 ns) <= sig_real1'last_value;
-- sig_rec1'delayed(1 ns) <= sig_rec1'last_value;
-- sig_rec2'delayed(1 ns) <= sig_rec2'last_value;
-- sig_rec3'delayed(1 ns) <= sig_rec3'last_value;
-- sig_arr1'delayed(1 ns) <= sig_arr1'last_value;
-- sig_arr2'delayed(1 ns) <= sig_arr2'last_value;
-- sig_arr3'delayed(1 ns) <= sig_arr3'last_value;
-- sig_bit'delayed(1 ns) <= sig_bit'last_value;
-- sig_boolean'delayed(1 ns) <= sig_boolean'last_value;
-- sig_character'delayed(1 ns) <= sig_character'last_value;
-- sig_integer'delayed(1 ns) <= sig_integer'last_value;
-- sig_real'delayed(1 ns) <= sig_real'last_value;
-- sig_time'delayed(1 ns) <= sig_time'last_value;
test_report ( "ARCH00542" ,
"Ranges of various signal attributes" ,
true ) ;
wait ;
------ [sequential_statement]...
end process P ;
end ARCH00542 ;
--
entity ENT00542_Test_Bench is
end ENT00542_Test_Bench ;
architecture ARCH00542_Test_Bench of ENT00542_Test_Bench is
begin
L1:
block
component UUT
end component ;
for CIS1 : UUT use entity WORK.E00000 ( ARCH00542 ) ;
begin
CIS1 : UUT ;
end block L1 ;
end ARCH00542_Test_Bench ;
--
| gpl-3.0 | 2ea27b83b2e3dd1eb866af86f53008d4 | 0.544177 | 3.487542 | false | false | false | false |
grwlf/vsim | vhdl_ct/ct00149.vhd | 1 | 14,056 | -- NEED RESULT: ARCH00149.P1: Multi inertial transactions occurred on signal asg with selected name on LHS passed
-- NEED RESULT: ARCH00149.P2: Multi inertial transactions occurred on signal asg with selected name on LHS passed
-- NEED RESULT: ARCH00149.P3: Multi inertial transactions occurred on signal asg with selected name on LHS passed
-- NEED RESULT: ARCH00149: One inertial transaction occurred on signal asg with selected name on LHS passed
-- NEED RESULT: ARCH00149: One inertial transaction occurred on signal asg with selected name on LHS passed
-- NEED RESULT: ARCH00149: One inertial transaction occurred on signal asg with selected name on LHS passed
-- NEED RESULT: P3: Inertial transactions entirely completed failed
-- NEED RESULT: P2: Inertial transactions entirely completed failed
-- NEED RESULT: P1: Inertial transactions entirely completed failed
-------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
-------------------------------------------------------------------------------
--
-- TEST NAME:
--
-- CT00149
--
-- AUTHOR:
--
-- G. Tominovich
--
-- TEST OBJECTIVES:
--
-- 8.3 (1)
-- 8.3 (2)
-- 8.3 (4)
-- 8.3 (5)
-- 8.3.1 (4)
--
-- DESIGN UNIT ORDERING:
--
-- E00000(ARCH00149)
-- ENT00149_Test_Bench(ARCH00149_Test_Bench)
--
-- REVISION HISTORY:
--
-- 08-JUL-1987 - initial revision
--
-- NOTES:
--
-- self-checking
-- automatically generated
--
use WORK.STANDARD_TYPES.all ;
architecture ARCH00149 of E00000 is
subtype chk_sig_type is integer range -1 to 100 ;
signal chk_st_rec1 : chk_sig_type := -1 ;
signal chk_st_rec2 : chk_sig_type := -1 ;
signal chk_st_rec3 : chk_sig_type := -1 ;
--
signal s_st_rec1 : st_rec1
:= c_st_rec1_1 ;
signal s_st_rec2 : st_rec2
:= c_st_rec2_1 ;
signal s_st_rec3 : st_rec3
:= c_st_rec3_1 ;
--
begin
P1 :
process
variable correct : boolean ;
variable counter : integer := 0 ;
variable savtime : time ;
begin
case counter is
when 0
=> s_st_rec1.f2 <=
c_st_rec1_2.f2 after 10 ns,
c_st_rec1_1.f2 after 20 ns ;
--
when 1
=> correct :=
s_st_rec1.f2 = c_st_rec1_2.f2 and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_rec1.f2 = c_st_rec1_1.f2 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00149.P1" ,
"Multi inertial transactions occurred on signal " &
"asg with selected name on LHS",
correct ) ;
s_st_rec1.f2 <=
c_st_rec1_2.f2 after 10 ns ,
c_st_rec1_1.f2 after 20 ns ,
c_st_rec1_2.f2 after 30 ns ,
c_st_rec1_1.f2 after 40 ns ;
--
when 3
=> correct :=
s_st_rec1.f2 = c_st_rec1_2.f2 and
(savtime + 10 ns) = Std.Standard.Now ;
s_st_rec1.f2 <= c_st_rec1_1.f2 after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_rec1.f2 = c_st_rec1_1.f2 and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00149" ,
"One inertial transaction occurred on signal " &
"asg with selected name on LHS",
correct ) ;
s_st_rec1.f2 <= transport
c_st_rec1_1.f2 after 100 ns ;
--
when 5
=> correct :=
s_st_rec1.f2 = c_st_rec1_1.f2 and
(savtime + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00149" ,
"Old transactions were removed on signal " &
"asg with selected name on LHS",
correct ) ;
s_st_rec1.f2 <=
c_st_rec1_2.f2 after 10 ns ,
c_st_rec1_1.f2 after 20 ns ,
c_st_rec1_2.f2 after 30 ns ,
c_st_rec1_1.f2 after 40 ns ;
--
when 6
=> correct :=
s_st_rec1.f2 = c_st_rec1_2.f2 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00149" ,
"One inertial transaction occurred on signal " &
"asg with selected name on LHS",
correct ) ;
s_st_rec1.f2 <= -- Last transaction above is marked
c_st_rec1_1.f2 after 40 ns ;
--
when 7
=> correct :=
s_st_rec1.f2 = c_st_rec1_1.f2 and
(savtime + 30 ns) = Std.Standard.Now ;
--
when 8
=> correct := correct and
s_st_rec1.f2 = c_st_rec1_1.f2 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00149" ,
"Inertial semantics check on a signal " &
"asg with selected name on LHS",
correct ) ;
--
when others
=>
test_report ( "ARCH00149" ,
"Inertial semantics check on a signal " &
"asg with selected name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_st_rec1 <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
wait until (not s_st_rec1'Quiet) and
(savtime /= Std.Standard.Now) ;
--
end process P1 ;
--
PGEN_CHKP_1 :
process ( chk_st_rec1 )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P1" ,
"Inertial transactions entirely completed",
chk_st_rec1 = 8 ) ;
end if ;
end process PGEN_CHKP_1 ;
--
P2 :
process
variable correct : boolean ;
variable counter : integer := 0 ;
variable savtime : time ;
begin
case counter is
when 0
=> s_st_rec2.f2 <=
c_st_rec2_2.f2 after 10 ns,
c_st_rec2_1.f2 after 20 ns ;
--
when 1
=> correct :=
s_st_rec2.f2 = c_st_rec2_2.f2 and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_rec2.f2 = c_st_rec2_1.f2 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00149.P2" ,
"Multi inertial transactions occurred on signal " &
"asg with selected name on LHS",
correct ) ;
s_st_rec2.f2 <=
c_st_rec2_2.f2 after 10 ns ,
c_st_rec2_1.f2 after 20 ns ,
c_st_rec2_2.f2 after 30 ns ,
c_st_rec2_1.f2 after 40 ns ;
--
when 3
=> correct :=
s_st_rec2.f2 = c_st_rec2_2.f2 and
(savtime + 10 ns) = Std.Standard.Now ;
s_st_rec2.f2 <= c_st_rec2_1.f2 after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_rec2.f2 = c_st_rec2_1.f2 and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00149" ,
"One inertial transaction occurred on signal " &
"asg with selected name on LHS",
correct ) ;
s_st_rec2.f2 <= transport
c_st_rec2_1.f2 after 100 ns ;
--
when 5
=> correct :=
s_st_rec2.f2 = c_st_rec2_1.f2 and
(savtime + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00149" ,
"Old transactions were removed on signal " &
"asg with selected name on LHS",
correct ) ;
s_st_rec2.f2 <=
c_st_rec2_2.f2 after 10 ns ,
c_st_rec2_1.f2 after 20 ns ,
c_st_rec2_2.f2 after 30 ns ,
c_st_rec2_1.f2 after 40 ns ;
--
when 6
=> correct :=
s_st_rec2.f2 = c_st_rec2_2.f2 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00149" ,
"One inertial transaction occurred on signal " &
"asg with selected name on LHS",
correct ) ;
s_st_rec2.f2 <= -- Last transaction above is marked
c_st_rec2_1.f2 after 40 ns ;
--
when 7
=> correct :=
s_st_rec2.f2 = c_st_rec2_1.f2 and
(savtime + 30 ns) = Std.Standard.Now ;
--
when 8
=> correct := correct and
s_st_rec2.f2 = c_st_rec2_1.f2 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00149" ,
"Inertial semantics check on a signal " &
"asg with selected name on LHS",
correct ) ;
--
when others
=>
test_report ( "ARCH00149" ,
"Inertial semantics check on a signal " &
"asg with selected name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_st_rec2 <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
wait until (not s_st_rec2'Quiet) and
(savtime /= Std.Standard.Now) ;
--
end process P2 ;
--
PGEN_CHKP_2 :
process ( chk_st_rec2 )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P2" ,
"Inertial transactions entirely completed",
chk_st_rec2 = 8 ) ;
end if ;
end process PGEN_CHKP_2 ;
--
P3 :
process
variable correct : boolean ;
variable counter : integer := 0 ;
variable savtime : time ;
begin
case counter is
when 0
=> s_st_rec3.f2 <=
c_st_rec3_2.f2 after 10 ns,
c_st_rec3_1.f2 after 20 ns ;
--
when 1
=> correct :=
s_st_rec3.f2 = c_st_rec3_2.f2 and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_rec3.f2 = c_st_rec3_1.f2 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00149.P3" ,
"Multi inertial transactions occurred on signal " &
"asg with selected name on LHS",
correct ) ;
s_st_rec3.f2 <=
c_st_rec3_2.f2 after 10 ns ,
c_st_rec3_1.f2 after 20 ns ,
c_st_rec3_2.f2 after 30 ns ,
c_st_rec3_1.f2 after 40 ns ;
--
when 3
=> correct :=
s_st_rec3.f2 = c_st_rec3_2.f2 and
(savtime + 10 ns) = Std.Standard.Now ;
s_st_rec3.f2 <= c_st_rec3_1.f2 after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_rec3.f2 = c_st_rec3_1.f2 and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00149" ,
"One inertial transaction occurred on signal " &
"asg with selected name on LHS",
correct ) ;
s_st_rec3.f2 <= transport
c_st_rec3_1.f2 after 100 ns ;
--
when 5
=> correct :=
s_st_rec3.f2 = c_st_rec3_1.f2 and
(savtime + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00149" ,
"Old transactions were removed on signal " &
"asg with selected name on LHS",
correct ) ;
s_st_rec3.f2 <=
c_st_rec3_2.f2 after 10 ns ,
c_st_rec3_1.f2 after 20 ns ,
c_st_rec3_2.f2 after 30 ns ,
c_st_rec3_1.f2 after 40 ns ;
--
when 6
=> correct :=
s_st_rec3.f2 = c_st_rec3_2.f2 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00149" ,
"One inertial transaction occurred on signal " &
"asg with selected name on LHS",
correct ) ;
s_st_rec3.f2 <= -- Last transaction above is marked
c_st_rec3_1.f2 after 40 ns ;
--
when 7
=> correct :=
s_st_rec3.f2 = c_st_rec3_1.f2 and
(savtime + 30 ns) = Std.Standard.Now ;
--
when 8
=> correct := correct and
s_st_rec3.f2 = c_st_rec3_1.f2 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00149" ,
"Inertial semantics check on a signal " &
"asg with selected name on LHS",
correct ) ;
--
when others
=>
test_report ( "ARCH00149" ,
"Inertial semantics check on a signal " &
"asg with selected name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_st_rec3 <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
wait until (not s_st_rec3'Quiet) and
(savtime /= Std.Standard.Now) ;
--
end process P3 ;
--
PGEN_CHKP_3 :
process ( chk_st_rec3 )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P3" ,
"Inertial transactions entirely completed",
chk_st_rec3 = 8 ) ;
end if ;
end process PGEN_CHKP_3 ;
--
--
end ARCH00149 ;
--
entity ENT00149_Test_Bench is
end ENT00149_Test_Bench ;
--
architecture ARCH00149_Test_Bench of ENT00149_Test_Bench is
begin
L1:
block
component UUT
end component ;
for CIS1 : UUT use entity WORK.E00000 ( ARCH00149 ) ;
begin
CIS1 : UUT ;
end block L1 ;
end ARCH00149_Test_Bench ;
| gpl-3.0 | ea021bba8249b0639e3f9c6688c13c84 | 0.47325 | 3.545913 | false | true | false | false |
grwlf/vsim | vhdl/STD/textio_body.vhdl | 2 | 34,586 | -- Std.Textio package body. This file is part of GHDL.
-- Copyright (C) 2002, 2003, 2004, 2005 Tristan Gingold
--
-- GHDL is free software; you can redistribute it and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation; either version 2, or (at your option) any later
-- version.
--
-- GHDL is distributed in the hope that it will be useful, but WITHOUT ANY
-- WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with GCC; see the file COPYING. If not, write to the Free
-- Software Foundation, 59 Temple Place - Suite 330, Boston, MA
-- 02111-1307, USA.
package body textio is
-- output routines for standard types
-- TIME_NAMES associates time units with textual names.
-- Textual names are in lower cases, since according to LRM93 14.3:
-- when written, the identifier is expressed in lowercase characters.
-- The length of the names are 3 characters, the last one may be a space
-- for 2 characters long names.
type time_unit is
record
val : time;
name : string (1 to 3);
end record;
type time_names_type is array (1 to 8) of time_unit;
constant time_names : time_names_type :=
((fs, "fs "), (ps, "ps "), (ns, "ns "), (us, "us "),
(ms, "ms "), (sec, "sec"), (min, "min"), (hr, "hr "));
-- Non breaking space character. --V93
constant nbsp : character := character'val (160); --V93
procedure writeline (f: out text; l: inout line) is --V87
procedure writeline (file f: text; l: inout line) is --V93
begin
if l = null then
-- LRM93 14.3
-- If parameter L contains a null access value at the start of the call,
-- the a null string is written to the file.
write (f, "");
else
-- LRM93 14.3
-- Procedure WRITELINE causes the current line designated by parameter L
-- to be written to the file and returns with the value of parameter L
-- designating a null string.
write (f, l.all);
deallocate (l);
l := new string'("");
end if;
end writeline;
procedure write
(l: inout line; value: in string;
justified: in side := right; field: in width := 0)
is
variable length: natural;
variable nl: line;
begin
-- l can be null.
if l = null then
length := 0;
else
length := l.all'length;
end if;
if value'length < field then
nl := new string (1 to length + field);
if length /= 0 then
nl (1 to length) := l.all;
end if;
if justified = right then
nl (length + 1 to length + field - value'length) := (others => ' ');
nl (nl.all'high - value'length + 1 to nl.all'high) := value;
else
nl (length + 1 to length + value'length) := value;
nl (length + value'length + 1 to nl.all'high) := (others => ' ');
end if;
else
nl := new string (1 to length + value'length);
if length /= 0 then
nl (1 to length) := l.all;
end if;
nl (length + 1 to nl.all'high) := value;
end if;
deallocate (l);
l := nl;
end write;
procedure write
(l: inout line; value: in integer;
justified: in side := right; field: in width := 0)
is
variable str: string (11 downto 1);
variable val: integer := value;
variable digit: natural;
variable index: natural := 0;
begin
-- Note: the absolute value of VAL cannot be directly taken, since
-- it may be greather that the maximum value of an INTEGER.
loop
-- LRM93 7.2.6
-- (A rem B) has the sign of A and an absolute value less then
-- the absoulte value of B.
digit := abs (val rem 10);
val := val / 10;
index := index + 1;
str (index) := character'val(48 + digit);
exit when val = 0;
end loop;
if value < 0 then
index := index + 1;
str(index) := '-';
end if;
write (l, str (index downto 1), justified, field);
end write;
procedure write
(l: inout line; value: in boolean;
justified: in side := right; field: in width := 0)
is
begin
if value then
write (l, string'("TRUE"), justified, field);
else
write (l, string'("FALSE"), justified, field);
end if;
end write;
procedure write
(l: inout line; value: in character;
justified: in side := right; field: in width := 0)
is
variable str: string (1 to 1);
begin
str (1) := value;
write (l, str, justified, field);
end write;
function bit_to_char (value : in bit) return character is
begin
case value is
when '0' =>
return '0';
when '1' =>
return '1';
end case;
end bit_to_char;
procedure write
(l: inout line; value: in bit;
justified: in side := right; field: in width := 0)
is
variable str : string (1 to 1);
begin
str (1) := bit_to_char (value);
write (l, str, justified, field);
end write;
procedure write
(l: inout line; value: in bit_vector;
justified: in side := right; field: in width := 0)
is
constant length : natural := value'length;
alias n_value : bit_vector (1 to value'length) is value;
variable str : string (1 to length);
begin
for i in str'range loop
str (i) := bit_to_char (n_value (i));
end loop;
write (l, str, justified, field);
end write;
procedure write
(l: inout line; value : in time;
justified: in side := right; field: in width := 0; unit : in TIME := ns)
is
-- Copy of VALUE on which we are working.
variable val : time := value;
-- Copy of UNIT on which we are working.
variable un : time := unit;
-- Digit extract from VAL/UN.
variable d : integer; -- natural range 0 to 9;
-- Index for unit name.
variable n : integer;
-- Result.
variable str : string (1 to 28);
-- Current character in RES.
variable pos : natural := 1;
-- Add a character to STR.
procedure add_char (c : character) is
begin
str (pos) := c;
pos := pos + 1;
end add_char;
begin
-- Note:
-- Care is taken to avoid overflow. Time may be 64 bits while integer
-- may be only 32 bits.
-- Handle sign.
-- Note: VAL cannot be negated since its range may be not symetric
-- around 0.
if val < 0 ns then
add_char ('-');
end if;
-- Search for the first digit.
-- Note: we must start from unit, since all units are not a power of 10.
-- Note: UN can be multiplied only after we know it is possible. This
-- is a to avoid overflow.
if un <= 0 fs then
assert false report "UNIT argument is not positive" severity error;
un := 1 ns;
end if;
while val / 10 >= un or val / 10 <= -un loop
un := un * 10;
end loop;
-- Extract digits one per one.
loop
d := val / un;
add_char (character'val (abs d + character'pos ('0')));
val := val - d * un;
exit when val = 0 ns and un <= unit;
if un = unit then
add_char ('.');
end if;
-- Stop as soon as precision will be lost.
-- This can happen only for hr and min.
-- FIXME: change the algorithm to display all the digits.
exit when (un / 10) * 10 /= un;
un := un / 10;
end loop;
add_char (' ');
-- Search the time unit name in the time table.
n := 0;
for i in time_names'range loop
if time_names (i).val = unit then
n := i;
exit;
end if;
end loop;
assert n /= 0 report "UNIT argument is not a unit name" severity error;
if n = 0 then
add_char ('?');
else
add_char (time_names (n).name (1));
add_char (time_names (n).name (2));
if time_names (n).name (3) /= ' ' then
add_char (time_names (n).name (3));
end if;
end if;
-- Write the result.
write (l, str (1 to pos - 1), justified, field);
end write;
-- Parameter DIGITS specifies how many digits to the right of the decimal
-- point are to be output when writing a real number; the default value 0
-- indicates that the number should be output in standard form, consisting
-- of a normalized mantissa plus exponent (e.g., 1.079236E23). If DIGITS is
-- nonzero, then the real number is output as an integer part followed by
-- '.' followed by the fractional part, using the specified number of digits
-- (e.g., 3.14159).
-- Note: Nan, +Inf, -Inf are not to be considered, since these numbers are
-- not in the bounds defined by any real range.
procedure write (L: inout line; value: in real;
justified: in side := right; field: in width := 0;
digits: in natural := 0)
is
-- STR contains the result of the conversion.
variable str : string (1 to 320);
-- POS is the index of the next character to be put in STR.
variable pos : positive := str'left;
-- VAL contains the value to be converted.
variable val : real;
-- The exponent or mantissa computed is stored in MANTISSA. This is
-- a signed number.
variable mantissa : integer;
variable b : boolean;
variable d : natural;
-- Append character C in STR.
procedure add_char (c : character) is
begin
str (pos) := c;
pos := pos + 1;
end add_char;
-- Add digit V in STR.
procedure add_digit (v : natural) is
begin
add_char (character'val (character'pos ('0') + v));
end add_digit;
-- Add leading digit and substract it.
procedure extract_leading_digit is
variable d : natural range 0 to 10;
begin
-- Note: We need truncation but type conversion does rounding.
-- FIXME: should consider precision.
d := natural (val);
if real (d) > val then
d := d - 1;
end if;
val := (val - real (d)) * 10.0;
add_digit (d);
end extract_leading_digit;
begin
-- Handle sign.
-- There is no overflow here, since with IEEE implementations, sign is
-- independant of the mantissa.
-- LRM93 14.3
-- The sign is never written if the value is non-negative.
if value < 0.0 then
add_char ('-');
val := -value;
else
val := value;
end if;
-- Compute the mantissa.
-- FIXME: should do a dichotomy.
if val = 0.0 then
mantissa := 0;
elsif val < 1.0 then
mantissa := -1;
while val * (10.0 ** (-mantissa)) < 1.0 loop
mantissa := mantissa - 1;
end loop;
else
mantissa := 0;
while val / (10.0 ** mantissa) >= 10.0 loop
mantissa := mantissa + 1;
end loop;
end if;
-- Normalize VAL: in [0; 10[
if mantissa >= 0 then
val := val / (10.0 ** mantissa);
else
val := val * 10.0 ** (-mantissa);
end if;
if digits = 0 then
for i in 0 to 15 loop
extract_leading_digit;
if i = 0 then
add_char ('.');
end if;
exit when i > 0 and val < 10.0 ** (i + 1 - 15);
end loop;
-- LRM93 14.3
-- if the exponent is present, the `e' is written as a lower case
-- character.
add_char ('e');
if mantissa < 0 then
add_char ('-');
mantissa := -mantissa;
end if;
b := false;
for i in 4 downto 0 loop
d := (mantissa / 10000) mod 10;
if d /= 0 or b or i = 0 then
add_digit (d);
b := true;
end if;
mantissa := (mantissa - d * 10000) * 10;
end loop;
else
if mantissa < 0 then
add_char ('0');
mantissa := mantissa + 1;
else
loop
extract_leading_digit;
exit when mantissa = 0;
mantissa := mantissa - 1;
end loop;
end if;
add_char ('.');
for i in 1 to digits loop
if mantissa = 0 then
extract_leading_digit;
else
add_char ('0');
mantissa := mantissa + 1;
end if;
end loop;
end if;
write (l, str (1 to pos - 1), justified, field);
end write;
procedure untruncated_text_read --V87
(variable f : text; str : out string; len : out natural); --V87
procedure untruncated_text_read --V93
(file f : text; str : out string; len : out natural); --V93
attribute foreign : string; --V87
attribute foreign of untruncated_text_read : procedure is "GHDL intrinsic";
procedure untruncated_text_read
(variable f : text; str : out string; len : out natural) is --V87
(file f : text; str : out string; len : out natural) is --V93
begin
assert false report "must not be called" severity failure;
end untruncated_text_read;
procedure readline (variable f: in text; l: inout line) --V87
procedure readline (file f: text; l: inout line) --V93
is
variable len, nlen, posn : natural;
variable nl, old_l : line;
variable str : string (1 to 128);
variable is_eol : boolean;
begin
-- LRM93 14.3
-- If parameter L contains a non-null access value at the start of the
-- call, the object designated by that value is deallocated before the
-- new object is created.
if l /= null then
deallocate (l);
end if;
-- We read the input in 128-byte chunks.
-- We keep reading until we reach a newline or there is no more input.
-- The loop invariant is that old_l is allocated and contains the
-- previous chunks read, and posn = old_l.all'length.
posn := 0;
loop
untruncated_text_read (f, str, len);
exit when len = 0;
if str (len) = LF or str (len) = CR then
-- LRM 14.3
-- The representation of the line does not contain the representation
-- of the end of the line.
is_eol := true;
len := len - 1;
-- End of line is any of LF/CR/CR+LF/LF+CR.
if len > 0 and (str (len) = LF or str (len) = CR) then
len := len - 1;
end if;
elsif endfile (f) then
is_eol := true;
else
is_eol := false;
end if;
l := new string (1 to posn + len);
if old_l /= null then
l (1 to posn) := old_l (1 to posn);
deallocate (old_l);
end if;
l (posn + 1 to posn + len) := str (1 to len);
exit when is_eol;
posn := posn + len;
old_l := l;
end loop;
end readline;
-- Replaces L with L (LEFT to/downto L'RIGHT)
procedure trim (l : inout line; left : natural)
is
variable nl : line;
begin
if l = null then
return;
end if;
if l'left < l'right then
-- Ascending.
if left > l'right then
nl := new string'("");
else
nl := new string (left to l'right);
-- nl := new string (1 to l'right + 1 - left);
nl.all := l (left to l'right);
end if;
else
-- Descending
if left < l'right then
nl := new string'("");
else
nl := new string (left downto l'right);
-- nl := new string (left - l'right + 1 downto 1);
nl.all := l (left downto l'right);
end if;
end if;
deallocate (l);
l := nl;
end trim;
-- Replaces L with L (LEFT + 1 to L'RIGHT or LEFT - 1 downto L'RIGHT)
procedure trim_next (l : inout line; left : natural)
is
variable nl : line;
begin
if l = null then
return;
end if;
if l'left < l'right then
-- Ascending.
trim (l, left + 1);
else
-- Descending
trim (l, left - 1);
end if;
end trim_next;
function to_lower (c : character) return character is
begin
if c >= 'A' and c <= 'Z' then
return character'val (character'pos (c) + 32);
else
return c;
end if;
end to_lower;
procedure read (l: inout line; value: out character; good: out boolean)
is
variable nl : line;
begin
if l = null or l'length = 0 then
good := false;
else
value := l (l'left);
trim_next (l, l'left);
good := true;
end if;
end read;
procedure read (l: inout line; value: out character)
is
variable res : boolean;
begin
read (l, value, res);
assert res = true
report "character read failure"
severity failure;
end read;
procedure read (l: inout line; value: out bit; good: out boolean)
is
begin
good := false;
for i in l'range loop
case l(i) is
when ' '
| NBSP --V93
| HT =>
null;
when '1' =>
value := '1';
good := true;
trim_next (l, i);
return;
when '0' =>
value := '0';
good := true;
trim_next (l, i);
return;
when others =>
return;
end case;
end loop;
return;
end read;
procedure read (l: inout line; value: out bit)
is
variable res : boolean;
begin
read (l, value, res);
assert res = true
report "bit read failure"
severity failure;
end read;
procedure read (l: inout line; value: out bit_vector; good: out boolean)
is
-- Number of bit to parse.
variable len : natural;
variable pos, last : natural;
variable res : bit_vector (1 to value'length);
-- State of the previous byte:
-- LEADING: blank before the bit vector.
-- FOUND: bit of the vector.
type state_type is (leading, found);
variable state : state_type;
begin
-- Initialization.
len := value'length;
if len = 0 then
-- If VALUE is a nul array, return now.
-- L stay unchanged.
-- FIXME: should blanks be removed ?
good := true;
return;
end if;
good := false;
state := leading;
pos := res'left;
for i in l'range loop
case l(i) is
when ' '
| NBSP --V93
| HT =>
case state is
when leading =>
null;
when found =>
return;
end case;
when '1' | '0' =>
case state is
when leading =>
state := found;
when found =>
null;
end case;
if l(i) = '0' then
res (pos) := '0';
else
res (pos) := '1';
end if;
pos := pos + 1;
len := len - 1;
last := i;
exit when len = 0;
when others =>
return;
end case;
end loop;
if len /= 0 then
-- Not enough bits.
return;
end if;
-- Note: if LEN = 0, then FIRST and LAST have been set.
good := true;
value := res;
trim_next (l, last);
return;
end read;
procedure read (l: inout line; value: out bit_vector)
is
variable res : boolean;
begin
read (l, value, res);
assert res = true
report "bit_vector read failure"
severity failure;
end read;
procedure read (l: inout line; value: out boolean; good: out boolean)
is
-- State:
-- BLANK: space are being scaned.
-- L_TF : T(rue) or F(alse) has been scanned.
-- L_RA : (t)R(ue) or (f)A(lse) has been scanned.
-- L_UL : (tr)U(e) or (fa)L(se) has been scanned.
-- L_ES : (tru)E or (fal)S(e) has been scanned.
type state_type is (blank, l_tf, l_ra, l_ul, l_es);
variable state : state_type;
-- Set to TRUE if T has been scanned, to FALSE if F has been scanned.
variable res : boolean;
begin
-- By default, it is a failure.
good := false;
state := blank;
for i in l'range loop
case state is
when blank =>
if l (i) = ' '
or l (i) = nbsp --V93
or l (i) = HT
then
null;
elsif to_lower (l (i)) = 't' then
res := true;
state := l_tf;
elsif to_lower (l (i)) = 'f' then
res := false;
state := l_tf;
else
return;
end if;
when l_tf =>
if res = true and to_lower (l (i)) = 'r' then
state := l_ra;
elsif res = false and to_lower (l (i)) = 'a' then
state := l_ra;
else
return;
end if;
when l_ra =>
if res = true and to_lower (l (i)) = 'u' then
state := l_ul;
elsif res = false and to_lower (l (i)) = 'l' then
state := l_ul;
else
return;
end if;
when l_ul =>
if res = true and to_lower (l (i)) = 'e' then
trim_next (l, i);
good := true;
value := true;
return;
elsif res = false and to_lower (l (i)) = 's' then
state := l_es;
else
return;
end if;
when l_es =>
if res = false and to_lower (l (i)) = 'e' then
trim_next (l, i);
good := true;
value := false;
return;
else
return;
end if;
end case;
end loop;
return;
end read;
procedure read (l: inout line; value: out boolean)
is
variable res : boolean;
begin
read (l, value, res);
assert res = true
report "boolean read failure"
severity failure;
end read;
function char_to_nat (c : character) return natural
is
begin
return character'pos (c) - character'pos ('0');
end char_to_nat;
procedure read (l: inout line; value: out integer; good: out boolean)
is
variable val : integer;
variable d : natural;
type state_t is (leading, sign, digits);
variable cur_state : state_t := leading;
begin
val := 1;
for i in l'range loop
case cur_state is
when leading =>
case l(i) is
when ' '
| NBSP --V93
| ht =>
null;
when '+' =>
cur_state := sign;
when '-' =>
val := -1;
cur_state := sign;
when '0' to '9' =>
val := char_to_nat (l(i));
cur_state := digits;
when others =>
good := false;
return;
end case;
when sign =>
case l(i) is
when '0' to '9' =>
val := val * char_to_nat (l(i));
cur_state := digits;
when others =>
good := false;
return;
end case;
when digits =>
case l(i) is
when '0' to '9' =>
d := char_to_nat (l(i));
val := val * 10;
if val < 0 then
val := val - d;
else
val := val + d;
end if;
when others =>
trim (l, i);
good := true;
value := val;
return;
end case;
end case;
end loop;
deallocate (l);
l := new string'("");
if cur_state /= leading then
good := true;
value := val;
else
good := false;
end if;
end read;
procedure read (l: inout line; value: out integer)
is
variable res : boolean;
begin
read (l, value, res);
assert res = true
report "integer read failure"
severity failure;
end read;
procedure read (l: inout line; value: out real; good: out boolean)
is
-- The result.
variable val : real;
-- True if the result is negative.
variable val_neg : boolean;
-- Number of digits after the dot.
variable nbr_dec : natural;
-- Value of the exponent.
variable exp : integer;
-- True if the exponent is negative.
variable exp_neg : boolean;
-- The parsing is done with a state machine.
-- LEADING: leading blank suppression.
-- SIGN: a sign has been found.
-- DIGITS: integer parts
-- DECIMALS: digits after the dot.
-- EXPONENT_SIGN: sign after "E"
-- EXPONENT_1: first digit of the exponent.
-- EXPONENT: digits of the exponent.
type state_t is (leading, sign, digits, decimals,
exponent_sign, exponent_1, exponent);
variable cur_state : state_t := leading;
-- Set VALUE to the result, and set GOOD to TRUE.
procedure set_value is
begin
good := true;
if exp_neg then
val := val * 10.0 ** (-exp);
else
val := val * 10.0 ** exp;
end if;
if val_neg then
value := -val;
else
value := val;
end if;
end set_value;
begin
-- Initialization.
val_neg := false;
nbr_dec := 1;
exp := 0;
exp_neg := false;
-- By default, parsing has failed.
good := false;
-- Iterate over all characters of the string.
-- Return immediatly in case of parse error.
-- Trim L and call SET_VALUE and return in case of success.
for i in l'range loop
case cur_state is
when leading =>
case l(i) is
when ' '
| NBSP --V93
| ht =>
null;
when '+' =>
cur_state := sign;
when '-' =>
val_neg := true;
cur_state := sign;
when '0' to '9' =>
val := real (char_to_nat (l(i)));
cur_state := digits;
when others =>
return;
end case;
when sign =>
case l(i) is
when '0' to '9' =>
val := real (char_to_nat (l(i)));
cur_state := digits;
when others =>
return;
end case;
when digits =>
case l(i) is
when '0' to '9' =>
val := val * 10.0 + real (char_to_nat (l(i)));
when '.' =>
cur_state := decimals;
when others =>
-- A "." (dot) is required in the string.
return;
end case;
when decimals =>
case l(i) is
when '0' to '9' =>
val := val + real (char_to_nat (l(i))) / (10.0 ** nbr_dec);
nbr_dec := nbr_dec + 1;
when 'e' | 'E' =>
-- "nnn.E" is erroneous.
if nbr_dec = 1 then
return;
end if;
cur_state := exponent_sign;
when others =>
-- "nnn.XX" is erroneous.
if nbr_dec = 1 then
return;
end if;
trim (l, i);
set_value;
return;
end case;
when exponent_sign =>
case l(i) is
when '+' =>
cur_state := exponent_1;
when '-' =>
exp_neg := true;
cur_state := exponent_1;
when '0' to '9' =>
exp := char_to_nat (l(i));
cur_state := exponent;
when others =>
-- Error.
return;
end case;
when exponent_1 | exponent =>
case l(i) is
when '0' to '9' =>
exp := exp * 10 + char_to_nat (l(i));
cur_state := exponent;
when others =>
trim (l, i);
set_value;
return;
end case;
end case;
end loop;
-- End of string.
case cur_state is
when leading | sign | digits =>
-- Erroneous.
return;
when decimals =>
-- "nnn.XX" is erroneous.
if nbr_dec = 1 then
return;
end if;
when exponent_sign =>
-- Erroneous ("NNN.NNNE")
return;
when exponent_1 =>
-- "NNN.NNNE-"
return;
when exponent =>
null;
end case;
deallocate (l);
l := new string'("");
set_value;
end read;
procedure read (l: inout line; value: out real)
is
variable res : boolean;
begin
read (l, value, res);
assert res = true
report "real read failure"
severity failure;
end read;
procedure read (l: inout line; value: out time; good: out boolean)
is
-- The result.
variable res : time;
-- UNIT is computed from the unit name, the exponent and the number of
-- digits before the dot. UNIT is the weight of the current digit.
variable unit : time;
-- Number of digits before the dot.
variable nbr_digits : integer;
-- True if a unit name has been found. Used temporaly to know the status
-- at the end of the search loop.
variable unit_found : boolean;
-- True if the number is negative.
variable is_neg : boolean;
-- Value of the exponent.
variable exp : integer;
-- True if the exponent is negative.
variable exp_neg : boolean;
-- Unit name extracted from the string.
variable unit_name : string (1 to 3);
-- state is the kind of the previous character parsed.
-- LEADING: leading blanks
-- SIGN: + or - as the first character of the number.
-- DIGITS: digit of the integer part of the number.
-- DOT: dot (.) after the integer part and before the decimal part.
-- DECIMALS: digit of the decimal part.
-- EXPONENT_MARK: e or E.
-- EXPONENT_SIGN: + or - just after the exponent mark (E).
-- EXPONENT: digit of the exponent.
-- UNIT_BLANK: blank after the exponent.
-- UNIT_1, UNIT_2, UNIT_3: first, second, third character of the unit.
type state_type is (leading, sign, digits, dot, decimals,
exponent_mark, exponent_sign, exponent,
unit_blank, unit_1, unit_2, unit_3);
variable state : state_type;
-- Used during the second scan of the string, TRUE is digits is being
-- scaned.
variable has_digits : boolean;
-- Position at the end of the string.
variable pos : integer;
-- Used to compute POS.
variable length : integer;
begin
-- Initialization.
-- Fail by default; therefore, in case of error, a return statement is
-- ok.
good := false;
nbr_digits := 0;
is_neg := false;
exp := 0;
exp_neg := false;
res := 0 fs;
-- Look for exponent and unit name.
-- Parse the string: this loop checks the correctness of the format, and
-- must return (GOOD has been set to FALSE) in case of error.
-- Set: NBR_DIGITS, IS_NEG, EXP, EXP_NEG.
state := leading;
for i in l'range loop
case l (i) is
when ' '
| NBSP --V93
| HT =>
case state is
when leading | unit_blank =>
null;
when sign | dot | exponent_mark | exponent_sign =>
return;
when digits | decimals | exponent =>
state := unit_blank;
when unit_1 | unit_2 =>
exit;
when unit_3 =>
-- Cannot happen, since an exit is performed at unit_3.
assert false report "internal error" severity failure;
end case;
when '+' | '-' =>
case state is
when leading =>
if l(i) = '-' then
is_neg := true;
end if;
state := sign;
when exponent_mark =>
if l(i) = '-' then
exp_neg := true;
end if;
state := exponent_sign;
when others =>
return;
end case;
when '0' to '9' =>
case state is
when exponent_mark | exponent_sign | exponent =>
exp := exp * 10 + char_to_nat (l (i));
state := exponent;
when leading | sign | digits =>
-- Leading "0" are not significant.
if nbr_digits > 0 or l (i) /= '0' then
nbr_digits := nbr_digits + 1;
end if;
state := digits;
when decimals =>
null;
when dot =>
state := decimals;
when others =>
return;
end case;
when 'a' to 'z' | 'A' to 'Z' =>
case state is
when digits | decimals =>
-- "E" has exponent mark.
if l (i) = 'e' or l(i) = 'E' then
state := exponent_mark;
else
return;
end if;
when unit_blank =>
unit_name (1) := to_lower (l(i));
state := unit_1;
when unit_1 =>
unit_name (2) := to_lower (l(i));
state := unit_2;
pos := i;
when unit_2 =>
unit_name (3) := to_lower (l(i));
state := unit_3;
exit;
when others =>
return;
end case;
when '.' =>
case state is
when digits =>
state := decimals;
when others =>
exit;
end case;
when others =>
exit;
end case;
end loop;
-- A unit name (2 or 3 letters) must have been found.
-- The string may end anywhere.
if state /= unit_2 and state /= unit_3 then
return;
end if;
-- Compute EXP with the sign.
if exp_neg then
exp := -exp;
end if;
-- Search the unit name in the list of time names.
unit_found := false;
for i in time_names'range loop
-- The first two characters must match (case insensitive).
-- The third character must match if:
-- * the unit name is a three characters identifier (ie, not a blank).
-- * there is a third character in STR.
if time_names (i).name (1) = unit_name (1)
and time_names (i).name (2) = unit_name (2)
and (time_names (i).name (3) = ' '
or time_names (i).name (3) = unit_name (3))
then
unit := time_names (i).val;
unit_found := true;
-- POS is set to the position of the first invalid character.
if time_names (i).name (3) = ' ' then
length := 1;
else
length := 2;
end if;
if l'left < l'right then
pos := pos + length;
else
pos := pos - length;
end if;
exit;
end if;
end loop;
if not unit_found then
return;
end if;
-- Compute UNIT, the weight of the first non-significant character.
nbr_digits := nbr_digits + exp - 1;
if nbr_digits < 0 then
unit := unit / 10 ** (-nbr_digits);
else
unit := unit * 10 ** nbr_digits;
end if;
-- HAS_DIGITS will be set as soon as a digit is found.
-- No error is expected here (this has been checked during the first
-- pass).
has_digits := false;
for i in l'range loop
case l (i) is
when ' '
| NBSP --V93
| HT =>
if has_digits then
exit;
end if;
when '+' | '-' =>
if not has_digits then
has_digits := true;
else
assert false report "internal error" severity failure;
return;
end if;
when '0' to '9' =>
-- Leading "0" are not significant.
if l (i) /= '0' or res /= 0 fs then
res := res + char_to_nat (l (i)) * unit;
unit := unit / 10;
end if;
has_digits := true;
when 'a' to 'z' | 'A' to 'Z' =>
if has_digits then
exit;
else
assert false report "internal error" severity failure;
return;
end if;
when '.' =>
if not has_digits then
assert false report "internal error" severity failure;
return;
end if;
when others =>
assert false report "internal error" severity failure;
return;
end case;
end loop;
-- Set VALUE.
if is_neg then
value := -res;
else
value := res;
end if;
good := true;
trim (l, pos);
return;
end read;
procedure read (l: inout line; value: out time)
is
variable res : boolean;
begin
read (l, value, res);
assert res = true
report "time read failure"
severity failure;
end read;
procedure read (l: inout line; value: out string; good: out boolean)
is
constant len : natural := value'length;
begin
if l'length < len then
good := false;
return;
end if;
good := true;
if len = 0 then
return;
end if;
if l'left < l'right then
-- Ascending (expected common case).
value := l (l'left to l'left + len - 1);
trim (l, l'left + len);
elsif l'left = l'right then
-- String of 1 character. We don't know the direction and therefore
-- can't use the code below which does a slice.
value := l.all;
deallocate (l);
l := new string'("");
else
-- Descending.
value := l (l'left downto l'left - len + 1);
trim (l, l'left - len);
end if;
end read;
procedure read (l: inout line; value: out string)
is
variable res : boolean;
begin
read (l, value, res);
assert res = true
report "string read failure"
severity failure;
end read;
end textio;
| gpl-3.0 | 38f8ffebf4c2cf893ae9276431f33f5e | 0.560574 | 3.534594 | false | false | false | false |
dcliche/mdsynth | rtl/src/ACIA_Clock.vhd | 1 | 3,727 | --===========================================================================--
-- --
-- ACIA_Clock.vhd - Synthesizable Baud Rate Clock Divider --
-- --
--===========================================================================--
--
-- File name : ACIA_Clock.vhd
--
-- Purpose : Implements a baud rate clock divider for a 6850 compatible
-- Asynchronous Communications Interface Adapter
--
-- Dependencies : ieee.std_logic_1164
-- ieee.std_logic_arith
-- ieee.std_logic_unsigned
-- ieee.numeric_std
-- work.bit_funcs
--
-- Author : John E. Kent
--
-- Email : [email protected]
--
-- Web : http://opencores.org/project,system09
--
-- ACIA_Clock.vhd is baud rate clock divider for a 6850 compatible ACIA core.
--
-- Copyright (C) 2003 - 2010 John Kent
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
--===========================================================================--
-- --
-- Revision History --
-- --
--===========================================================================--
--
-- Revision Name Date Description
-- 0.1 John Kent unknown Initial version
-- 1.0 John Kent 30th May 2010 Added GPL header
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
--library unisim;
-- use unisim.vcomponents.all;
library work;
use work.bit_funcs.all;
entity acia_clock is
generic (
SYS_CLK_FREQ : integer;
ACIA_CLK_FREQ : integer
);
port(
clk : in Std_Logic; -- System Clock input
acia_clk : out Std_Logic -- ACIA Clock output
);
end acia_clock;
-------------------------------------------------------------------------------
-- Architecture for ACIA_Clock
-------------------------------------------------------------------------------
architecture rtl of ACIA_Clock is
constant FULL_CYCLE : integer := (SYS_CLK_FREQ / ACIA_CLK_FREQ);
constant HALF_CYCLE : integer := (FULL_CYCLE / 2);
signal acia_count : Std_Logic_Vector(log2(FULL_CYCLE) downto 0) := (Others => '0');
begin
--
-- Baud Rate Clock Divider
--
-- 25MHz / 27 = 926,000 KHz = 57,870Bd * 16
-- 50MHz / 54 = 926,000 KHz = 57,870Bd * 16
--
my_acia_clock: process( clk )
begin
if(clk'event and clk = '0') then
if( acia_count = (FULL_CYCLE - 1) ) then
acia_clk <= '0';
acia_count <= (others => '0'); --"000000";
else
if( acia_count = (HALF_CYCLE - 1) ) then
acia_clk <='1';
end if;
acia_count <= acia_count + 1;
end if;
end if;
end process;
end rtl;
| gpl-3.0 | 740c2b9482ad0c3c34576e743e7a0b76 | 0.473303 | 4.249715 | false | false | false | false |
pepo27/electronica | arquitectura/EjemplosClase/PruebaVariablesSenales.vhdl | 2 | 1,437 | library ieee;
use ieee.std_logic_1164.all;
entity Prueba is
generic (numeroBits : integer :=20); --cuatro bits
Port(
a: in std_logic_vector (numeroBits-1 downto 0);
b: in std_logic_vector (numeroBits-1 downto 0);
op: in std_logic ;
s: out std_logic_vector (numeroBits-1 downto 0);
cout: out std_logic
);
end Prueba;
--/*
--
--Ecuaciones de sumador con acarreo en cascada
--
--EB(i) = B(i) xor OP
--S(i) = A(i) xor EB(i) xor C(i)*
--C(i+1) = EB(i)C(i) or A(i)C(i) + A(i)EB(i)
--
--*Implica una salida del circuito
--
--Sentencias de repetición en vhdl.
--
-->> Concurrente
-- for-generate -> Se puede ejecutar fuera de un bloque process
-- etiqueta:
-- for [variable] in [rango] generate
-- --codigo vhdl
-- end generate;
-->> Iterativa
-- for-loop -> Se ejecuta dentro de un bloque process
-- etiqueta:
-- for [variable] in [rango] LOOP
-- --codigo vhdl
-- end loop;
--
--*/
architecture A_Prueba of Prueba is
--/*Declaracion de señales*/
--signal eb: std_logic_vector (3 downto 0);
--signal c : std_logic_vector (4 downto 0);
--/*Proceso inicial*/
begin
process(a,b,op)
variable eb: std_logic_vector (numeroBits-1 downto 0);
variable c: std_logic_vector (numeroBits downto 0);
begin
c(0):= '0';
for i in 0 to (numeroBits -1) loop
eb(i) := b(i) xor op;
s(i) <= a(i) xor eb(i) xor c(i);
c(i+1) := (eb(i) and c(i)) or (a(i) and c(i)) or (a(i) and eb(i));
end loop;
end process;
end A_Prueba; | gpl-3.0 | 5597294d09dae9d157d767e4baf04fa6 | 0.633449 | 2.548845 | false | false | false | false |
jairov4/accel-oil | impl/impl_test_single/simulation/behavioral/nfa_accept_samples_generic_hw_top_v1_01_a/sample_iterator_next/_primary.vhd | 1 | 3,055 | library verilog;
use verilog.vl_types.all;
entity sample_iterator_next is
generic(
ap_const_logic_1: vl_logic := Hi1;
ap_const_logic_0: vl_logic := Hi0;
ap_ST_pp0_stg0_fsm_0: vl_logic := Hi0;
ap_const_lv32_1 : integer := 1;
ap_const_lv32_20: integer := 32;
ap_const_lv32_2F: integer := 47;
ap_const_lv17_1FFFF: vl_logic_vector(0 to 16) := (Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1);
ap_const_lv16_1 : vl_logic_vector(0 to 15) := (Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi1);
ap_const_lv16_0 : vl_logic_vector(0 to 15) := (Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0);
ap_const_lv56_0 : vl_logic_vector(0 to 55) := (Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0);
ap_true : vl_logic := Hi1
);
port(
ap_clk : in vl_logic;
ap_rst : in vl_logic;
ap_start : in vl_logic;
ap_done : out vl_logic;
ap_idle : out vl_logic;
ap_ready : out vl_logic;
indices_req_din : out vl_logic;
indices_req_full_n: in vl_logic;
indices_req_write: out vl_logic;
indices_rsp_empty_n: in vl_logic;
indices_rsp_read: out vl_logic;
indices_address : out vl_logic_vector(31 downto 0);
indices_datain : in vl_logic_vector(55 downto 0);
indices_dataout : out vl_logic_vector(55 downto 0);
indices_size : out vl_logic_vector(31 downto 0);
ap_ce : in vl_logic;
i_index : in vl_logic_vector(15 downto 0);
i_sample : in vl_logic_vector(15 downto 0);
ap_return_0 : out vl_logic_vector(15 downto 0);
ap_return_1 : out vl_logic_vector(15 downto 0)
);
attribute mti_svvh_generic_type : integer;
attribute mti_svvh_generic_type of ap_const_logic_1 : constant is 1;
attribute mti_svvh_generic_type of ap_const_logic_0 : constant is 1;
attribute mti_svvh_generic_type of ap_ST_pp0_stg0_fsm_0 : constant is 1;
attribute mti_svvh_generic_type of ap_const_lv32_1 : constant is 1;
attribute mti_svvh_generic_type of ap_const_lv32_20 : constant is 1;
attribute mti_svvh_generic_type of ap_const_lv32_2F : constant is 1;
attribute mti_svvh_generic_type of ap_const_lv17_1FFFF : constant is 1;
attribute mti_svvh_generic_type of ap_const_lv16_1 : constant is 1;
attribute mti_svvh_generic_type of ap_const_lv16_0 : constant is 1;
attribute mti_svvh_generic_type of ap_const_lv56_0 : constant is 1;
attribute mti_svvh_generic_type of ap_true : constant is 1;
end sample_iterator_next;
| lgpl-3.0 | 71199da69c527283564aeaa13701da5c | 0.589198 | 2.730116 | false | false | false | false |
TWW12/lzw | final_project_sim/lzw/lzw.cache/ip/9495202d6046313a/bram_2048_1_sim_netlist.vhdl | 1 | 63,423 | -- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1756540 Mon Jan 23 19:11:23 MST 2017
-- Date : Tue Apr 18 23:15:16 2017
-- Host : DESKTOP-I9J3TQJ running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
-- decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ bram_2048_1_sim_netlist.vhdl
-- Design : bram_2048_1
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7z020clg484-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper_init is
port (
douta : out STD_LOGIC_VECTOR ( 8 downto 0 );
clka : in STD_LOGIC;
ena : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 10 downto 0 );
dina : in STD_LOGIC_VECTOR ( 8 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 )
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper_init;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper_init is
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 15 downto 8 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 15 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 to 1 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute CLOCK_DOMAINS : string;
attribute CLOCK_DOMAINS of \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram\ : label is "COMMON";
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram\: unisim.vcomponents.RAMB18E1
generic map(
DOA_REG => 1,
DOB_REG => 0,
INITP_00 => X"0000000000000000000000000000000080000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_00 => X"403E3C3A38363432302E2C2A28262422201E1C1A18161412100E0C0A08060402",
INIT_01 => X"807E7C7A78767472706E6C6A68666462605E5C5A58565452504E4C4A48464442",
INIT_02 => X"C0BEBCBAB8B6B4B2B0AEACAAA8A6A4A2A09E9C9A98969492908E8C8A88868482",
INIT_03 => X"00FEFCFAF8F6F4F2F0EEECEAE8E6E4E2E0DEDCDAD8D6D4D2D0CECCCAC8C6C4C2",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"00000",
INIT_B => X"00000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "PERFORMANCE",
READ_WIDTH_A => 9,
READ_WIDTH_B => 9,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"00000",
SRVAL_B => X"00000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 9,
WRITE_WIDTH_B => 9
)
port map (
ADDRARDADDR(13 downto 3) => addra(10 downto 0),
ADDRARDADDR(2 downto 0) => B"000",
ADDRBWRADDR(13 downto 0) => B"00000000000000",
CLKARDCLK => clka,
CLKBWRCLK => clka,
DIADI(15 downto 8) => B"00000000",
DIADI(7 downto 0) => dina(7 downto 0),
DIBDI(15 downto 0) => B"0000000000000000",
DIPADIP(1) => '0',
DIPADIP(0) => dina(8),
DIPBDIP(1 downto 0) => B"00",
DOADO(15 downto 8) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_DOADO_UNCONNECTED\(15 downto 8),
DOADO(7 downto 0) => douta(7 downto 0),
DOBDO(15 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_DOBDO_UNCONNECTED\(15 downto 0),
DOPADOP(1) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_DOPADOP_UNCONNECTED\(1),
DOPADOP(0) => douta(8),
DOPBDOP(1 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_DOPBDOP_UNCONNECTED\(1 downto 0),
ENARDEN => ena,
ENBWREN => '0',
REGCEAREGCE => ena,
REGCEB => '0',
RSTRAMARSTRAM => '0',
RSTRAMB => '0',
RSTREGARSTREG => '0',
RSTREGB => '0',
WEA(1) => wea(0),
WEA(0) => wea(0),
WEBWE(3 downto 0) => B"0000"
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper_init__parameterized0\ is
port (
douta : out STD_LOGIC_VECTOR ( 10 downto 0 );
clka : in STD_LOGIC;
ena : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 10 downto 0 );
dina : in STD_LOGIC_VECTOR ( 10 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper_init__parameterized0\ : entity is "blk_mem_gen_prim_wrapper_init";
end \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper_init__parameterized0\;
architecture STRUCTURE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper_init__parameterized0\ is
signal \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_37\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_38\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_39\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_45\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_46\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_87\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_88\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 16 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute CLOCK_DOMAINS : string;
attribute CLOCK_DOMAINS of \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\ : label is "COMMON";
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 1,
DOB_REG => 0,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_40 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_41 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_42 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_43 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_44 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_45 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_46 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_47 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_48 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_49 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_50 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_51 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_52 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_53 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_54 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_55 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_56 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_57 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_58 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_59 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_60 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_61 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_62 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_63 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_64 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_65 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_66 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_67 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_68 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_69 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_70 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_71 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_72 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_73 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_74 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "PERFORMANCE",
READ_WIDTH_A => 18,
READ_WIDTH_B => 18,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 18,
WRITE_WIDTH_B => 18
)
port map (
ADDRARDADDR(15) => '1',
ADDRARDADDR(14 downto 4) => addra(10 downto 0),
ADDRARDADDR(3 downto 0) => B"1111",
ADDRBWRADDR(15 downto 0) => B"0000000000000000",
CASCADEINA => '0',
CASCADEINB => '0',
CASCADEOUTA => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => clka,
CLKBWRCLK => clka,
DBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\,
DIADI(31 downto 13) => B"0000000000000000000",
DIADI(12 downto 8) => dina(10 downto 6),
DIADI(7 downto 6) => B"00",
DIADI(5 downto 0) => dina(5 downto 0),
DIBDI(31 downto 0) => B"00000000000000000000000000000000",
DIPADIP(3 downto 0) => B"0000",
DIPBDIP(3 downto 0) => B"0000",
DOADO(31 downto 16) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\(31 downto 16),
DOADO(15) => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_37\,
DOADO(14) => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_38\,
DOADO(13) => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_39\,
DOADO(12 downto 8) => douta(10 downto 6),
DOADO(7) => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_45\,
DOADO(6) => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_46\,
DOADO(5 downto 0) => douta(5 downto 0),
DOBDO(31 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\(31 downto 0),
DOPADOP(3 downto 2) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\(3 downto 2),
DOPADOP(1) => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_87\,
DOPADOP(0) => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_88\,
DOPBDOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\(3 downto 0),
ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => ena,
ENBWREN => '0',
INJECTDBITERR => '0',
INJECTSBITERR => '0',
RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => ena,
REGCEB => '0',
RSTRAMARSTRAM => '0',
RSTRAMB => '0',
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\,
WEA(3) => wea(0),
WEA(2) => wea(0),
WEA(1) => wea(0),
WEA(0) => wea(0),
WEBWE(7 downto 0) => B"00000000"
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width is
port (
douta : out STD_LOGIC_VECTOR ( 8 downto 0 );
clka : in STD_LOGIC;
ena : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 10 downto 0 );
dina : in STD_LOGIC_VECTOR ( 8 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 )
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width is
begin
\prim_init.ram\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper_init
port map (
addra(10 downto 0) => addra(10 downto 0),
clka => clka,
dina(8 downto 0) => dina(8 downto 0),
douta(8 downto 0) => douta(8 downto 0),
ena => ena,
wea(0) => wea(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized0\ is
port (
douta : out STD_LOGIC_VECTOR ( 10 downto 0 );
clka : in STD_LOGIC;
ena : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 10 downto 0 );
dina : in STD_LOGIC_VECTOR ( 10 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized0\ : entity is "blk_mem_gen_prim_width";
end \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized0\;
architecture STRUCTURE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized0\ is
begin
\prim_init.ram\: entity work.\decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper_init__parameterized0\
port map (
addra(10 downto 0) => addra(10 downto 0),
clka => clka,
dina(10 downto 0) => dina(10 downto 0),
douta(10 downto 0) => douta(10 downto 0),
ena => ena,
wea(0) => wea(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_generic_cstr is
port (
douta : out STD_LOGIC_VECTOR ( 19 downto 0 );
clka : in STD_LOGIC;
ena : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 10 downto 0 );
dina : in STD_LOGIC_VECTOR ( 19 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 )
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_generic_cstr;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_generic_cstr is
begin
\ramloop[0].ram.r\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width
port map (
addra(10 downto 0) => addra(10 downto 0),
clka => clka,
dina(8 downto 0) => dina(8 downto 0),
douta(8 downto 0) => douta(8 downto 0),
ena => ena,
wea(0) => wea(0)
);
\ramloop[1].ram.r\: entity work.\decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized0\
port map (
addra(10 downto 0) => addra(10 downto 0),
clka => clka,
dina(10 downto 0) => dina(19 downto 9),
douta(10 downto 0) => douta(19 downto 9),
ena => ena,
wea(0) => wea(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_top is
port (
douta : out STD_LOGIC_VECTOR ( 19 downto 0 );
clka : in STD_LOGIC;
ena : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 10 downto 0 );
dina : in STD_LOGIC_VECTOR ( 19 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 )
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_top;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_top is
begin
\valid.cstr\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_generic_cstr
port map (
addra(10 downto 0) => addra(10 downto 0),
clka => clka,
dina(19 downto 0) => dina(19 downto 0),
douta(19 downto 0) => douta(19 downto 0),
ena => ena,
wea(0) => wea(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5_synth is
port (
douta : out STD_LOGIC_VECTOR ( 19 downto 0 );
clka : in STD_LOGIC;
ena : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 10 downto 0 );
dina : in STD_LOGIC_VECTOR ( 19 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 )
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5_synth;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5_synth is
begin
\gnbram.gnativebmg.native_blk_mem_gen\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_top
port map (
addra(10 downto 0) => addra(10 downto 0),
clka => clka,
dina(19 downto 0) => dina(19 downto 0),
douta(19 downto 0) => douta(19 downto 0),
ena => ena,
wea(0) => wea(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 is
port (
clka : in STD_LOGIC;
rsta : in STD_LOGIC;
ena : in STD_LOGIC;
regcea : in STD_LOGIC;
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
addra : in STD_LOGIC_VECTOR ( 10 downto 0 );
dina : in STD_LOGIC_VECTOR ( 19 downto 0 );
douta : out STD_LOGIC_VECTOR ( 19 downto 0 );
clkb : in STD_LOGIC;
rstb : in STD_LOGIC;
enb : in STD_LOGIC;
regceb : in STD_LOGIC;
web : in STD_LOGIC_VECTOR ( 0 to 0 );
addrb : in STD_LOGIC_VECTOR ( 10 downto 0 );
dinb : in STD_LOGIC_VECTOR ( 19 downto 0 );
doutb : out STD_LOGIC_VECTOR ( 19 downto 0 );
injectsbiterr : in STD_LOGIC;
injectdbiterr : in STD_LOGIC;
eccpipece : in STD_LOGIC;
sbiterr : out STD_LOGIC;
dbiterr : out STD_LOGIC;
rdaddrecc : out STD_LOGIC_VECTOR ( 10 downto 0 );
sleep : in STD_LOGIC;
deepsleep : in STD_LOGIC;
shutdown : in STD_LOGIC;
rsta_busy : out STD_LOGIC;
rstb_busy : out STD_LOGIC;
s_aclk : in STD_LOGIC;
s_aresetn : in STD_LOGIC;
s_axi_awid : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_awready : out STD_LOGIC;
s_axi_wdata : in STD_LOGIC_VECTOR ( 19 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_wlast : in STD_LOGIC;
s_axi_wvalid : in STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_bid : out STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_bvalid : out STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_arid : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arvalid : in STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_rid : out STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_rdata : out STD_LOGIC_VECTOR ( 19 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rlast : out STD_LOGIC;
s_axi_rvalid : out STD_LOGIC;
s_axi_rready : in STD_LOGIC;
s_axi_injectsbiterr : in STD_LOGIC;
s_axi_injectdbiterr : in STD_LOGIC;
s_axi_sbiterr : out STD_LOGIC;
s_axi_dbiterr : out STD_LOGIC;
s_axi_rdaddrecc : out STD_LOGIC_VECTOR ( 10 downto 0 )
);
attribute C_ADDRA_WIDTH : integer;
attribute C_ADDRA_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is 11;
attribute C_ADDRB_WIDTH : integer;
attribute C_ADDRB_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is 11;
attribute C_ALGORITHM : integer;
attribute C_ALGORITHM of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is 1;
attribute C_AXI_ID_WIDTH : integer;
attribute C_AXI_ID_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is 4;
attribute C_AXI_SLAVE_TYPE : integer;
attribute C_AXI_SLAVE_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_AXI_TYPE : integer;
attribute C_AXI_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is 1;
attribute C_BYTE_SIZE : integer;
attribute C_BYTE_SIZE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is 9;
attribute C_COMMON_CLK : integer;
attribute C_COMMON_CLK of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_COUNT_18K_BRAM : string;
attribute C_COUNT_18K_BRAM of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is "1";
attribute C_COUNT_36K_BRAM : string;
attribute C_COUNT_36K_BRAM of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is "1";
attribute C_CTRL_ECC_ALGO : string;
attribute C_CTRL_ECC_ALGO of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is "NONE";
attribute C_DEFAULT_DATA : string;
attribute C_DEFAULT_DATA of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is "0";
attribute C_DISABLE_WARN_BHV_COLL : integer;
attribute C_DISABLE_WARN_BHV_COLL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_DISABLE_WARN_BHV_RANGE : integer;
attribute C_DISABLE_WARN_BHV_RANGE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_ELABORATION_DIR : string;
attribute C_ELABORATION_DIR of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is "./";
attribute C_ENABLE_32BIT_ADDRESS : integer;
attribute C_ENABLE_32BIT_ADDRESS of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_EN_DEEPSLEEP_PIN : integer;
attribute C_EN_DEEPSLEEP_PIN of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_EN_ECC_PIPE : integer;
attribute C_EN_ECC_PIPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_EN_RDADDRA_CHG : integer;
attribute C_EN_RDADDRA_CHG of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_EN_RDADDRB_CHG : integer;
attribute C_EN_RDADDRB_CHG of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_EN_SAFETY_CKT : integer;
attribute C_EN_SAFETY_CKT of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_EN_SHUTDOWN_PIN : integer;
attribute C_EN_SHUTDOWN_PIN of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_EN_SLEEP_PIN : integer;
attribute C_EN_SLEEP_PIN of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_EST_POWER_SUMMARY : string;
attribute C_EST_POWER_SUMMARY of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is "Estimated Power for IP : 3.9373 mW";
attribute C_FAMILY : string;
attribute C_FAMILY of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is "zynq";
attribute C_HAS_AXI_ID : integer;
attribute C_HAS_AXI_ID of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_HAS_ENA : integer;
attribute C_HAS_ENA of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is 1;
attribute C_HAS_ENB : integer;
attribute C_HAS_ENB of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_HAS_INJECTERR : integer;
attribute C_HAS_INJECTERR of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_HAS_MEM_OUTPUT_REGS_A : integer;
attribute C_HAS_MEM_OUTPUT_REGS_A of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is 1;
attribute C_HAS_MEM_OUTPUT_REGS_B : integer;
attribute C_HAS_MEM_OUTPUT_REGS_B of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_HAS_MUX_OUTPUT_REGS_A : integer;
attribute C_HAS_MUX_OUTPUT_REGS_A of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_HAS_MUX_OUTPUT_REGS_B : integer;
attribute C_HAS_MUX_OUTPUT_REGS_B of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_HAS_REGCEA : integer;
attribute C_HAS_REGCEA of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_HAS_REGCEB : integer;
attribute C_HAS_REGCEB of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_HAS_RSTA : integer;
attribute C_HAS_RSTA of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_HAS_RSTB : integer;
attribute C_HAS_RSTB of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_HAS_SOFTECC_INPUT_REGS_A : integer;
attribute C_HAS_SOFTECC_INPUT_REGS_A of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_HAS_SOFTECC_OUTPUT_REGS_B : integer;
attribute C_HAS_SOFTECC_OUTPUT_REGS_B of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_INITA_VAL : string;
attribute C_INITA_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is "0";
attribute C_INITB_VAL : string;
attribute C_INITB_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is "0";
attribute C_INIT_FILE : string;
attribute C_INIT_FILE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is "bram_2048_1.mem";
attribute C_INIT_FILE_NAME : string;
attribute C_INIT_FILE_NAME of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is "bram_2048_1.mif";
attribute C_INTERFACE_TYPE : integer;
attribute C_INTERFACE_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_LOAD_INIT_FILE : integer;
attribute C_LOAD_INIT_FILE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is 1;
attribute C_MEM_TYPE : integer;
attribute C_MEM_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_MUX_PIPELINE_STAGES : integer;
attribute C_MUX_PIPELINE_STAGES of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_PRIM_TYPE : integer;
attribute C_PRIM_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is 1;
attribute C_READ_DEPTH_A : integer;
attribute C_READ_DEPTH_A of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is 2048;
attribute C_READ_DEPTH_B : integer;
attribute C_READ_DEPTH_B of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is 2048;
attribute C_READ_WIDTH_A : integer;
attribute C_READ_WIDTH_A of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is 20;
attribute C_READ_WIDTH_B : integer;
attribute C_READ_WIDTH_B of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is 20;
attribute C_RSTRAM_A : integer;
attribute C_RSTRAM_A of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_RSTRAM_B : integer;
attribute C_RSTRAM_B of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_RST_PRIORITY_A : string;
attribute C_RST_PRIORITY_A of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is "CE";
attribute C_RST_PRIORITY_B : string;
attribute C_RST_PRIORITY_B of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is "CE";
attribute C_SIM_COLLISION_CHECK : string;
attribute C_SIM_COLLISION_CHECK of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is "ALL";
attribute C_USE_BRAM_BLOCK : integer;
attribute C_USE_BRAM_BLOCK of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_USE_BYTE_WEA : integer;
attribute C_USE_BYTE_WEA of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_USE_BYTE_WEB : integer;
attribute C_USE_BYTE_WEB of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_USE_DEFAULT_DATA : integer;
attribute C_USE_DEFAULT_DATA of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_USE_ECC : integer;
attribute C_USE_ECC of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_USE_SOFTECC : integer;
attribute C_USE_SOFTECC of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_USE_URAM : integer;
attribute C_USE_URAM of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_WEA_WIDTH : integer;
attribute C_WEA_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is 1;
attribute C_WEB_WIDTH : integer;
attribute C_WEB_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is 1;
attribute C_WRITE_DEPTH_A : integer;
attribute C_WRITE_DEPTH_A of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is 2048;
attribute C_WRITE_DEPTH_B : integer;
attribute C_WRITE_DEPTH_B of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is 2048;
attribute C_WRITE_MODE_A : string;
attribute C_WRITE_MODE_A of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is "WRITE_FIRST";
attribute C_WRITE_MODE_B : string;
attribute C_WRITE_MODE_B of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is "WRITE_FIRST";
attribute C_WRITE_WIDTH_A : integer;
attribute C_WRITE_WIDTH_A of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is 20;
attribute C_WRITE_WIDTH_B : integer;
attribute C_WRITE_WIDTH_B of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is 20;
attribute C_XDEVICEFAMILY : string;
attribute C_XDEVICEFAMILY of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is "zynq";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is "yes";
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 is
signal \<const0>\ : STD_LOGIC;
begin
dbiterr <= \<const0>\;
doutb(19) <= \<const0>\;
doutb(18) <= \<const0>\;
doutb(17) <= \<const0>\;
doutb(16) <= \<const0>\;
doutb(15) <= \<const0>\;
doutb(14) <= \<const0>\;
doutb(13) <= \<const0>\;
doutb(12) <= \<const0>\;
doutb(11) <= \<const0>\;
doutb(10) <= \<const0>\;
doutb(9) <= \<const0>\;
doutb(8) <= \<const0>\;
doutb(7) <= \<const0>\;
doutb(6) <= \<const0>\;
doutb(5) <= \<const0>\;
doutb(4) <= \<const0>\;
doutb(3) <= \<const0>\;
doutb(2) <= \<const0>\;
doutb(1) <= \<const0>\;
doutb(0) <= \<const0>\;
rdaddrecc(10) <= \<const0>\;
rdaddrecc(9) <= \<const0>\;
rdaddrecc(8) <= \<const0>\;
rdaddrecc(7) <= \<const0>\;
rdaddrecc(6) <= \<const0>\;
rdaddrecc(5) <= \<const0>\;
rdaddrecc(4) <= \<const0>\;
rdaddrecc(3) <= \<const0>\;
rdaddrecc(2) <= \<const0>\;
rdaddrecc(1) <= \<const0>\;
rdaddrecc(0) <= \<const0>\;
rsta_busy <= \<const0>\;
rstb_busy <= \<const0>\;
s_axi_arready <= \<const0>\;
s_axi_awready <= \<const0>\;
s_axi_bid(3) <= \<const0>\;
s_axi_bid(2) <= \<const0>\;
s_axi_bid(1) <= \<const0>\;
s_axi_bid(0) <= \<const0>\;
s_axi_bresp(1) <= \<const0>\;
s_axi_bresp(0) <= \<const0>\;
s_axi_bvalid <= \<const0>\;
s_axi_dbiterr <= \<const0>\;
s_axi_rdaddrecc(10) <= \<const0>\;
s_axi_rdaddrecc(9) <= \<const0>\;
s_axi_rdaddrecc(8) <= \<const0>\;
s_axi_rdaddrecc(7) <= \<const0>\;
s_axi_rdaddrecc(6) <= \<const0>\;
s_axi_rdaddrecc(5) <= \<const0>\;
s_axi_rdaddrecc(4) <= \<const0>\;
s_axi_rdaddrecc(3) <= \<const0>\;
s_axi_rdaddrecc(2) <= \<const0>\;
s_axi_rdaddrecc(1) <= \<const0>\;
s_axi_rdaddrecc(0) <= \<const0>\;
s_axi_rdata(19) <= \<const0>\;
s_axi_rdata(18) <= \<const0>\;
s_axi_rdata(17) <= \<const0>\;
s_axi_rdata(16) <= \<const0>\;
s_axi_rdata(15) <= \<const0>\;
s_axi_rdata(14) <= \<const0>\;
s_axi_rdata(13) <= \<const0>\;
s_axi_rdata(12) <= \<const0>\;
s_axi_rdata(11) <= \<const0>\;
s_axi_rdata(10) <= \<const0>\;
s_axi_rdata(9) <= \<const0>\;
s_axi_rdata(8) <= \<const0>\;
s_axi_rdata(7) <= \<const0>\;
s_axi_rdata(6) <= \<const0>\;
s_axi_rdata(5) <= \<const0>\;
s_axi_rdata(4) <= \<const0>\;
s_axi_rdata(3) <= \<const0>\;
s_axi_rdata(2) <= \<const0>\;
s_axi_rdata(1) <= \<const0>\;
s_axi_rdata(0) <= \<const0>\;
s_axi_rid(3) <= \<const0>\;
s_axi_rid(2) <= \<const0>\;
s_axi_rid(1) <= \<const0>\;
s_axi_rid(0) <= \<const0>\;
s_axi_rlast <= \<const0>\;
s_axi_rresp(1) <= \<const0>\;
s_axi_rresp(0) <= \<const0>\;
s_axi_rvalid <= \<const0>\;
s_axi_sbiterr <= \<const0>\;
s_axi_wready <= \<const0>\;
sbiterr <= \<const0>\;
GND: unisim.vcomponents.GND
port map (
G => \<const0>\
);
inst_blk_mem_gen: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5_synth
port map (
addra(10 downto 0) => addra(10 downto 0),
clka => clka,
dina(19 downto 0) => dina(19 downto 0),
douta(19 downto 0) => douta(19 downto 0),
ena => ena,
wea(0) => wea(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
port (
clka : in STD_LOGIC;
ena : in STD_LOGIC;
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
addra : in STD_LOGIC_VECTOR ( 10 downto 0 );
dina : in STD_LOGIC_VECTOR ( 19 downto 0 );
douta : out STD_LOGIC_VECTOR ( 19 downto 0 )
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is true;
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "bram_2048_1,blk_mem_gen_v8_3_5,{}";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "yes";
attribute x_core_info : string;
attribute x_core_info of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "blk_mem_gen_v8_3_5,Vivado 2016.4";
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
signal NLW_U0_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_rsta_busy_UNCONNECTED : STD_LOGIC;
signal NLW_U0_rstb_busy_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_arready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_awready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_bvalid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_rlast_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_rvalid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_wready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_doutb_UNCONNECTED : STD_LOGIC_VECTOR ( 19 downto 0 );
signal NLW_U0_rdaddrecc_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
signal NLW_U0_s_axi_bid_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_s_axi_bresp_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_U0_s_axi_rdaddrecc_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
signal NLW_U0_s_axi_rdata_UNCONNECTED : STD_LOGIC_VECTOR ( 19 downto 0 );
signal NLW_U0_s_axi_rid_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_s_axi_rresp_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute C_ADDRA_WIDTH : integer;
attribute C_ADDRA_WIDTH of U0 : label is 11;
attribute C_ADDRB_WIDTH : integer;
attribute C_ADDRB_WIDTH of U0 : label is 11;
attribute C_ALGORITHM : integer;
attribute C_ALGORITHM of U0 : label is 1;
attribute C_AXI_ID_WIDTH : integer;
attribute C_AXI_ID_WIDTH of U0 : label is 4;
attribute C_AXI_SLAVE_TYPE : integer;
attribute C_AXI_SLAVE_TYPE of U0 : label is 0;
attribute C_AXI_TYPE : integer;
attribute C_AXI_TYPE of U0 : label is 1;
attribute C_BYTE_SIZE : integer;
attribute C_BYTE_SIZE of U0 : label is 9;
attribute C_COMMON_CLK : integer;
attribute C_COMMON_CLK of U0 : label is 0;
attribute C_COUNT_18K_BRAM : string;
attribute C_COUNT_18K_BRAM of U0 : label is "1";
attribute C_COUNT_36K_BRAM : string;
attribute C_COUNT_36K_BRAM of U0 : label is "1";
attribute C_CTRL_ECC_ALGO : string;
attribute C_CTRL_ECC_ALGO of U0 : label is "NONE";
attribute C_DEFAULT_DATA : string;
attribute C_DEFAULT_DATA of U0 : label is "0";
attribute C_DISABLE_WARN_BHV_COLL : integer;
attribute C_DISABLE_WARN_BHV_COLL of U0 : label is 0;
attribute C_DISABLE_WARN_BHV_RANGE : integer;
attribute C_DISABLE_WARN_BHV_RANGE of U0 : label is 0;
attribute C_ELABORATION_DIR : string;
attribute C_ELABORATION_DIR of U0 : label is "./";
attribute C_ENABLE_32BIT_ADDRESS : integer;
attribute C_ENABLE_32BIT_ADDRESS of U0 : label is 0;
attribute C_EN_DEEPSLEEP_PIN : integer;
attribute C_EN_DEEPSLEEP_PIN of U0 : label is 0;
attribute C_EN_ECC_PIPE : integer;
attribute C_EN_ECC_PIPE of U0 : label is 0;
attribute C_EN_RDADDRA_CHG : integer;
attribute C_EN_RDADDRA_CHG of U0 : label is 0;
attribute C_EN_RDADDRB_CHG : integer;
attribute C_EN_RDADDRB_CHG of U0 : label is 0;
attribute C_EN_SAFETY_CKT : integer;
attribute C_EN_SAFETY_CKT of U0 : label is 0;
attribute C_EN_SHUTDOWN_PIN : integer;
attribute C_EN_SHUTDOWN_PIN of U0 : label is 0;
attribute C_EN_SLEEP_PIN : integer;
attribute C_EN_SLEEP_PIN of U0 : label is 0;
attribute C_EST_POWER_SUMMARY : string;
attribute C_EST_POWER_SUMMARY of U0 : label is "Estimated Power for IP : 3.9373 mW";
attribute C_FAMILY : string;
attribute C_FAMILY of U0 : label is "zynq";
attribute C_HAS_AXI_ID : integer;
attribute C_HAS_AXI_ID of U0 : label is 0;
attribute C_HAS_ENA : integer;
attribute C_HAS_ENA of U0 : label is 1;
attribute C_HAS_ENB : integer;
attribute C_HAS_ENB of U0 : label is 0;
attribute C_HAS_INJECTERR : integer;
attribute C_HAS_INJECTERR of U0 : label is 0;
attribute C_HAS_MEM_OUTPUT_REGS_A : integer;
attribute C_HAS_MEM_OUTPUT_REGS_A of U0 : label is 1;
attribute C_HAS_MEM_OUTPUT_REGS_B : integer;
attribute C_HAS_MEM_OUTPUT_REGS_B of U0 : label is 0;
attribute C_HAS_MUX_OUTPUT_REGS_A : integer;
attribute C_HAS_MUX_OUTPUT_REGS_A of U0 : label is 0;
attribute C_HAS_MUX_OUTPUT_REGS_B : integer;
attribute C_HAS_MUX_OUTPUT_REGS_B of U0 : label is 0;
attribute C_HAS_REGCEA : integer;
attribute C_HAS_REGCEA of U0 : label is 0;
attribute C_HAS_REGCEB : integer;
attribute C_HAS_REGCEB of U0 : label is 0;
attribute C_HAS_RSTA : integer;
attribute C_HAS_RSTA of U0 : label is 0;
attribute C_HAS_RSTB : integer;
attribute C_HAS_RSTB of U0 : label is 0;
attribute C_HAS_SOFTECC_INPUT_REGS_A : integer;
attribute C_HAS_SOFTECC_INPUT_REGS_A of U0 : label is 0;
attribute C_HAS_SOFTECC_OUTPUT_REGS_B : integer;
attribute C_HAS_SOFTECC_OUTPUT_REGS_B of U0 : label is 0;
attribute C_INITA_VAL : string;
attribute C_INITA_VAL of U0 : label is "0";
attribute C_INITB_VAL : string;
attribute C_INITB_VAL of U0 : label is "0";
attribute C_INIT_FILE : string;
attribute C_INIT_FILE of U0 : label is "bram_2048_1.mem";
attribute C_INIT_FILE_NAME : string;
attribute C_INIT_FILE_NAME of U0 : label is "bram_2048_1.mif";
attribute C_INTERFACE_TYPE : integer;
attribute C_INTERFACE_TYPE of U0 : label is 0;
attribute C_LOAD_INIT_FILE : integer;
attribute C_LOAD_INIT_FILE of U0 : label is 1;
attribute C_MEM_TYPE : integer;
attribute C_MEM_TYPE of U0 : label is 0;
attribute C_MUX_PIPELINE_STAGES : integer;
attribute C_MUX_PIPELINE_STAGES of U0 : label is 0;
attribute C_PRIM_TYPE : integer;
attribute C_PRIM_TYPE of U0 : label is 1;
attribute C_READ_DEPTH_A : integer;
attribute C_READ_DEPTH_A of U0 : label is 2048;
attribute C_READ_DEPTH_B : integer;
attribute C_READ_DEPTH_B of U0 : label is 2048;
attribute C_READ_WIDTH_A : integer;
attribute C_READ_WIDTH_A of U0 : label is 20;
attribute C_READ_WIDTH_B : integer;
attribute C_READ_WIDTH_B of U0 : label is 20;
attribute C_RSTRAM_A : integer;
attribute C_RSTRAM_A of U0 : label is 0;
attribute C_RSTRAM_B : integer;
attribute C_RSTRAM_B of U0 : label is 0;
attribute C_RST_PRIORITY_A : string;
attribute C_RST_PRIORITY_A of U0 : label is "CE";
attribute C_RST_PRIORITY_B : string;
attribute C_RST_PRIORITY_B of U0 : label is "CE";
attribute C_SIM_COLLISION_CHECK : string;
attribute C_SIM_COLLISION_CHECK of U0 : label is "ALL";
attribute C_USE_BRAM_BLOCK : integer;
attribute C_USE_BRAM_BLOCK of U0 : label is 0;
attribute C_USE_BYTE_WEA : integer;
attribute C_USE_BYTE_WEA of U0 : label is 0;
attribute C_USE_BYTE_WEB : integer;
attribute C_USE_BYTE_WEB of U0 : label is 0;
attribute C_USE_DEFAULT_DATA : integer;
attribute C_USE_DEFAULT_DATA of U0 : label is 0;
attribute C_USE_ECC : integer;
attribute C_USE_ECC of U0 : label is 0;
attribute C_USE_SOFTECC : integer;
attribute C_USE_SOFTECC of U0 : label is 0;
attribute C_USE_URAM : integer;
attribute C_USE_URAM of U0 : label is 0;
attribute C_WEA_WIDTH : integer;
attribute C_WEA_WIDTH of U0 : label is 1;
attribute C_WEB_WIDTH : integer;
attribute C_WEB_WIDTH of U0 : label is 1;
attribute C_WRITE_DEPTH_A : integer;
attribute C_WRITE_DEPTH_A of U0 : label is 2048;
attribute C_WRITE_DEPTH_B : integer;
attribute C_WRITE_DEPTH_B of U0 : label is 2048;
attribute C_WRITE_MODE_A : string;
attribute C_WRITE_MODE_A of U0 : label is "WRITE_FIRST";
attribute C_WRITE_MODE_B : string;
attribute C_WRITE_MODE_B of U0 : label is "WRITE_FIRST";
attribute C_WRITE_WIDTH_A : integer;
attribute C_WRITE_WIDTH_A of U0 : label is 20;
attribute C_WRITE_WIDTH_B : integer;
attribute C_WRITE_WIDTH_B of U0 : label is 20;
attribute C_XDEVICEFAMILY : string;
attribute C_XDEVICEFAMILY of U0 : label is "zynq";
attribute downgradeipidentifiedwarnings of U0 : label is "yes";
begin
U0: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5
port map (
addra(10 downto 0) => addra(10 downto 0),
addrb(10 downto 0) => B"00000000000",
clka => clka,
clkb => '0',
dbiterr => NLW_U0_dbiterr_UNCONNECTED,
deepsleep => '0',
dina(19 downto 0) => dina(19 downto 0),
dinb(19 downto 0) => B"00000000000000000000",
douta(19 downto 0) => douta(19 downto 0),
doutb(19 downto 0) => NLW_U0_doutb_UNCONNECTED(19 downto 0),
eccpipece => '0',
ena => ena,
enb => '0',
injectdbiterr => '0',
injectsbiterr => '0',
rdaddrecc(10 downto 0) => NLW_U0_rdaddrecc_UNCONNECTED(10 downto 0),
regcea => '0',
regceb => '0',
rsta => '0',
rsta_busy => NLW_U0_rsta_busy_UNCONNECTED,
rstb => '0',
rstb_busy => NLW_U0_rstb_busy_UNCONNECTED,
s_aclk => '0',
s_aresetn => '0',
s_axi_araddr(31 downto 0) => B"00000000000000000000000000000000",
s_axi_arburst(1 downto 0) => B"00",
s_axi_arid(3 downto 0) => B"0000",
s_axi_arlen(7 downto 0) => B"00000000",
s_axi_arready => NLW_U0_s_axi_arready_UNCONNECTED,
s_axi_arsize(2 downto 0) => B"000",
s_axi_arvalid => '0',
s_axi_awaddr(31 downto 0) => B"00000000000000000000000000000000",
s_axi_awburst(1 downto 0) => B"00",
s_axi_awid(3 downto 0) => B"0000",
s_axi_awlen(7 downto 0) => B"00000000",
s_axi_awready => NLW_U0_s_axi_awready_UNCONNECTED,
s_axi_awsize(2 downto 0) => B"000",
s_axi_awvalid => '0',
s_axi_bid(3 downto 0) => NLW_U0_s_axi_bid_UNCONNECTED(3 downto 0),
s_axi_bready => '0',
s_axi_bresp(1 downto 0) => NLW_U0_s_axi_bresp_UNCONNECTED(1 downto 0),
s_axi_bvalid => NLW_U0_s_axi_bvalid_UNCONNECTED,
s_axi_dbiterr => NLW_U0_s_axi_dbiterr_UNCONNECTED,
s_axi_injectdbiterr => '0',
s_axi_injectsbiterr => '0',
s_axi_rdaddrecc(10 downto 0) => NLW_U0_s_axi_rdaddrecc_UNCONNECTED(10 downto 0),
s_axi_rdata(19 downto 0) => NLW_U0_s_axi_rdata_UNCONNECTED(19 downto 0),
s_axi_rid(3 downto 0) => NLW_U0_s_axi_rid_UNCONNECTED(3 downto 0),
s_axi_rlast => NLW_U0_s_axi_rlast_UNCONNECTED,
s_axi_rready => '0',
s_axi_rresp(1 downto 0) => NLW_U0_s_axi_rresp_UNCONNECTED(1 downto 0),
s_axi_rvalid => NLW_U0_s_axi_rvalid_UNCONNECTED,
s_axi_sbiterr => NLW_U0_s_axi_sbiterr_UNCONNECTED,
s_axi_wdata(19 downto 0) => B"00000000000000000000",
s_axi_wlast => '0',
s_axi_wready => NLW_U0_s_axi_wready_UNCONNECTED,
s_axi_wstrb(0) => '0',
s_axi_wvalid => '0',
sbiterr => NLW_U0_sbiterr_UNCONNECTED,
shutdown => '0',
sleep => '0',
wea(0) => wea(0),
web(0) => '0'
);
end STRUCTURE;
| unlicense | 21beac5587374d5801d0b71d9a7fe17d | 0.713669 | 3.665222 | false | false | false | false |
wsoltys/AtomFpga | src/AtomGodilVideo/src/SID/sid_components.vhd | 1 | 2,504 | -------------------------------------------------------------------------------
--
-- SID 6581 (voice)
--
-- This piece of VHDL code describes a single SID voice (sound channel)
--
-------------------------------------------------------------------------------
-- to do: - better resolution of result signal voice, this is now only 10bits,
-- but it could be 20 !! Problem, it does not fit the PWM-dac
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
use IEEE.numeric_std.all;
-------------------------------------------------------------------------------
--
-- Delta-Sigma DAC
--
-- Refer to Xilinx Application Note XAPP154.
--
-- This DAC requires an external RC low-pass filter:
--
-- dac_o 0---XXXXX---+---0 analog audio
-- 3k3 |
-- === 4n7
-- |
-- GND
--
-------------------------------------------------------------------------------
--Implementation Digital to Analog converter
entity pwm_sddac is
generic (
msbi_g : integer := 9
);
port (
clk_i : in std_logic;
reset : in std_logic;
dac_i : in std_logic_vector(msbi_g downto 0);
dac_o : out std_logic
);
end pwm_sddac;
architecture rtl of pwm_sddac is
signal sig_in : unsigned(msbi_g+2 downto 0) := (others => '0');
begin
seq: process (clk_i, reset)
begin
if reset = '1' then
sig_in <= to_unsigned(2**(msbi_g+1), sig_in'length);
dac_o <= '0';
elsif rising_edge(clk_i) then
sig_in <= sig_in + unsigned(sig_in(msbi_g+2) & sig_in(msbi_g+2) & dac_i);
dac_o <= sig_in(msbi_g+2);
end if;
end process seq;
end rtl;
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
use IEEE.numeric_std.all;
entity pwm_sdadc is
port (
clk : in std_logic; -- main clock signal (the higher the better)
reset : in std_logic; --
ADC_out : out std_logic_vector(7 downto 0); -- binary input of signal to be converted
ADC_in : in std_logic -- "analog" paddle input pin
);
end pwm_sdadc;
-- Dummy implementation (no real A/D conversion performed)
architecture rtl of pwm_sdadc is
begin
process (clk, ADC_in)
begin
if ADC_in = '1' then
ADC_out <= (others => '1');
else
ADC_out <= (others => '0');
end if;
end process;
end rtl;
| apache-2.0 | 684910303201b65fb99da0b219ef8b4d | 0.483626 | 3.551773 | false | false | false | false |
jairov4/accel-oil | impl/impl_test_single/hdl/system_lmb_bram_wrapper.vhd | 1 | 2,902 | -------------------------------------------------------------------------------
-- system_lmb_bram_wrapper.vhd
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
library lmb_bram_elaborate_v1_00_a;
use lmb_bram_elaborate_v1_00_a.all;
entity system_lmb_bram_wrapper is
port (
BRAM_Rst_A : in std_logic;
BRAM_Clk_A : in std_logic;
BRAM_EN_A : in std_logic;
BRAM_WEN_A : in std_logic_vector(0 to 3);
BRAM_Addr_A : in std_logic_vector(0 to 31);
BRAM_Din_A : out std_logic_vector(0 to 31);
BRAM_Dout_A : in std_logic_vector(0 to 31);
BRAM_Rst_B : in std_logic;
BRAM_Clk_B : in std_logic;
BRAM_EN_B : in std_logic;
BRAM_WEN_B : in std_logic_vector(0 to 3);
BRAM_Addr_B : in std_logic_vector(0 to 31);
BRAM_Din_B : out std_logic_vector(0 to 31);
BRAM_Dout_B : in std_logic_vector(0 to 31)
);
attribute x_core_info : STRING;
attribute keep_hierarchy : STRING;
attribute x_core_info of system_lmb_bram_wrapper : entity is "lmb_bram_elaborate_v1_00_a";
attribute keep_hierarchy of system_lmb_bram_wrapper : entity is "yes";
end system_lmb_bram_wrapper;
architecture STRUCTURE of system_lmb_bram_wrapper is
component lmb_bram_elaborate is
generic (
C_MEMSIZE : integer;
C_PORT_DWIDTH : integer;
C_PORT_AWIDTH : integer;
C_NUM_WE : integer;
C_FAMILY : string
);
port (
BRAM_Rst_A : in std_logic;
BRAM_Clk_A : in std_logic;
BRAM_EN_A : in std_logic;
BRAM_WEN_A : in std_logic_vector(0 to C_NUM_WE-1);
BRAM_Addr_A : in std_logic_vector(0 to C_PORT_AWIDTH-1);
BRAM_Din_A : out std_logic_vector(0 to C_PORT_DWIDTH-1);
BRAM_Dout_A : in std_logic_vector(0 to C_PORT_DWIDTH-1);
BRAM_Rst_B : in std_logic;
BRAM_Clk_B : in std_logic;
BRAM_EN_B : in std_logic;
BRAM_WEN_B : in std_logic_vector(0 to C_NUM_WE-1);
BRAM_Addr_B : in std_logic_vector(0 to C_PORT_AWIDTH-1);
BRAM_Din_B : out std_logic_vector(0 to C_PORT_DWIDTH-1);
BRAM_Dout_B : in std_logic_vector(0 to C_PORT_DWIDTH-1)
);
end component;
begin
lmb_bram : lmb_bram_elaborate
generic map (
C_MEMSIZE => 16#4000#,
C_PORT_DWIDTH => 32,
C_PORT_AWIDTH => 32,
C_NUM_WE => 4,
C_FAMILY => "virtex5"
)
port map (
BRAM_Rst_A => BRAM_Rst_A,
BRAM_Clk_A => BRAM_Clk_A,
BRAM_EN_A => BRAM_EN_A,
BRAM_WEN_A => BRAM_WEN_A,
BRAM_Addr_A => BRAM_Addr_A,
BRAM_Din_A => BRAM_Din_A,
BRAM_Dout_A => BRAM_Dout_A,
BRAM_Rst_B => BRAM_Rst_B,
BRAM_Clk_B => BRAM_Clk_B,
BRAM_EN_B => BRAM_EN_B,
BRAM_WEN_B => BRAM_WEN_B,
BRAM_Addr_B => BRAM_Addr_B,
BRAM_Din_B => BRAM_Din_B,
BRAM_Dout_B => BRAM_Dout_B
);
end architecture STRUCTURE;
| lgpl-3.0 | 83a535cc058c8e2982f1d93fe0bc279a | 0.573398 | 2.946193 | false | false | false | false |
takeshineshiro/fpga_fibre_scan | HUCB2P0_150701/HUCB2P0_TOP.vhd | 1 | 41,194 | --*****************************************************************************
-- @Copyright 2013 by SIAT_HFUS_TEAM, All rights reserved.
-- Module name : HUCB2P0_TOP
-- Call by :
-- Description : this module is the top module of HUCB2P0.
-- IC : 5CGXFC7D7F31C8N
-- Version : A
-- Note: :
-- Author : Peitian Mu
-- Date : 2013.09.12
-- Update :
--*****************************************************************************
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
library work;
entity HUCB2P0_TOP is
port
(
I_reset : in std_logic; -- 复位，低有效--
I_ref_clk : in std_logic; -- 20M时钟
DDR3_A0 : out std_logic; -- not used
DDR3_A1 : out std_logic; -- not used
DDR3_A2 : out std_logic; -- not used
DDR3_A3 : out std_logic; -- not used
DDR3_A4 : out std_logic; -- not used
DDR3_A5 : out std_logic; -- not used
DDR3_A6 : out std_logic; -- not used
DDR3_A7 : out std_logic; -- not used
DDR3_A8 : out std_logic; -- not used
DDR3_A9 : out std_logic; -- not used
DDR3_A10 : out std_logic; -- not used
DDR3_A11 : out std_logic; -- not used
DDR3_A12 : out std_logic; -- not used
DDR3_A13 : out std_logic; -- not used
DDR3_D0 : inout std_logic; -- not used
DDR3_D1 : inout std_logic; -- not used
DDR3_D2 : inout std_logic; -- not used
DDR3_D3 : inout std_logic; -- not used
DDR3_D4 : inout std_logic; -- not used
DDR3_D5 : inout std_logic; -- not used
DDR3_D6 : inout std_logic; -- not used
DDR3_D7 : inout std_logic; -- not used
DDR3_D8 : inout std_logic; -- not used
DDR3_D9 : inout std_logic; -- not used
DDR3_D10 : inout std_logic; -- not used
DDR3_D11 : inout std_logic; -- not used
DDR3_D12 : inout std_logic; -- not used
DDR3_D13 : inout std_logic; -- not used
DDR3_D14 : inout std_logic; -- not used
DDR3_D15 : inout std_logic; -- not used
DDR3_BA0 : out std_logic; -- not used
DDR3_BA1 : out std_logic; -- not used
DDR3_BA2 : out std_logic; -- not used
DDR3_CAS : out std_logic_vector(0 downto 0); -- not used
DDR3_RAS : out std_logic_vector(0 downto 0); -- not used
DDR3_WE : out std_logic_vector(0 downto 0); -- not used
DDR3_CLK : out std_logic_vector(0 downto 0); -- not used
DDR3_CLK_n : out std_logic_vector(0 downto 0); -- not used
DDR3_DQS0 : inout std_logic; --not used
DDR3_DQS0_n : inout std_logic; --not used
DDR3_DQS1 : inout std_logic; --not used
DDR3_DQS1_n : inout std_logic; --not used
DDR3_ODT : out std_logic_vector(0 downto 0); --not used
DDR3_DML : out std_logic; --not used
DDR3_CKE : out std_logic_vector(0 downto 0); --not used
DDR3_DMU : out std_logic; --not used
DDR3_CS : out std_logic_vector(0 downto 0); --not used
DDR3_RST : out std_logic; --not used
--ADC ADS58C48
O_adca_sen : out std_logic; -- 此ADC未使用
I_adca_sd : in std_logic;
O_adca_sdata : out std_logic;
O_adca_sclk : out std_logic;
O_adca_rst : out std_logic;
O_adca_pdn : out std_logic;
O_adca_snrb0 : out std_logic;
O_adca_snrb1 : out std_logic;
I_adca_oclk : in std_logic;
I_adca_d : in std_logic_vector(5 downto 0);
I_adcb_d : in std_logic_vector(5 downto 0);
I_adcc_d : in std_logic_vector(5 downto 0);
I_adcd_d : in std_logic_vector(5 downto 0);
--ADC AD9634
I_adce_clk : in std_logic; -- 此ADC未使用
I_adce_d : in std_logic_vector(5 downto 0);
I_adce_or : in std_logic;
O_adce_csb : out std_logic;
O_adce_sdio : out std_logic;
O_adce_sclk : out std_logic;
--ADC AD9230
I_adcf_clk : in std_logic; -- 此ADC用于本项目数据采集 --240M
I_adcf_d : in std_logic_vector(11 downto 0);
I_adcf_or : in std_logic;
O_adcf_pwdn : out std_logic;
O_adcf_csb : out std_logic;
O_adcf_sclk : out std_logic;
O_adcf_sdio : out std_logic;
O_adcf_reset : out std_logic;
--ADC AD9235
I_m_adc_d : in std_logic_vector(11 downto 0); -- 此ADC未使用
O_m_adc_clk : out std_logic;
I_m_adc_otr : in std_logic;
O_m_adc_pdwn : out std_logic;
O_pulse : out std_logic_vector(3 downto 0); -- 未使用
O_pulse_0pd : out std_logic; -- 未使用
O_pulse_1pd : out std_logic; -- 未使用
O_pulse_2pd : out std_logic; -- 未使用
O_pulse_3pd : out std_logic; -- 未使用
O_8220pulse : out std_logic_vector(3 downto 0); -- 发射通道
O_8020islpulse : out std_logic_vector(3 downto 0); -- 未使用
O_8020mdpulse : out std_logic_vector(7 downto 0); -- 未使用
----------pll configuration
O_pll_rst : out std_logic; -- 此PLL用于ADC时钟配置，使用方法可参考AD9518的datasheet。
O_pll_sync : out std_logic;
O_pll_sdio : out std_logic;
O_pll_pd : out std_logic;
O_pll_cs : out std_logic;
O_pll_sclk : out std_logic;
I_pll_refmon : in std_logic; --not used
I_pll_ld : in std_logic; --not used
I_pll_status : in std_logic; --not used
I_pll_sdo : in std_logic; --not used
I_iotrig : in std_logic; -- X10 I/O -- not used
I_ioenable : in std_logic; -- X2 I/O -- not used
BEEP : in std_logic; -- 蜂鸣器未使用 -- not used
DA_SYNC : out std_logic; -- AD5300，是ADI公司的DAC，用于输出sine给功放驱动电磁铁。
DA_SCLK : out std_logic; -- AD5300
DA_DIN : out std_logic; -- AD5300
FPGA_IO0 : in std_logic; -- 未使用 --not used
FPGA_IO1 : in std_logic; -- 未使用 --not used
SRAM_WE : in std_logic; -- 未使用 --not used
SRAM_OE : in std_logic; --not used
SRAM_CLK : in std_logic; --not used
SRAM_ADV : in std_logic; --not used
SRAM_CRE : in std_logic; --not used
SRAM_LB : in std_logic; --not used
SRAM_UB : in std_logic; --not used
O_swi_dir : out std_logic; -- 电压转换芯片74LVC4245APW
O_swi_oe : out std_logic; -- 电压转换芯片74LVC4245APW
I_swi0 : in std_logic; --not used
I_swi1 : in std_logic; --not used
I_swi2 : in std_logic; --not used
I_swi3 : in std_logic; --not used
I_swi4 : in std_logic; --not used
PCIE_SMCLK : in std_logic; --not used
PCIE_SMDAT : in std_logic; --not used
PCIE_WAKE : in std_logic; --not used
PCIE_PERST : in std_logic; --not used
DAC_SLEEP : in std_logic; --not used
DAC_GD0 : in std_logic; --not used
DAC_GD1 : in std_logic; --not used
DAC_GD2 : in std_logic; --not used
DAC_GD3 : in std_logic; --not used
DAC_GD4 : in std_logic; --not used
DAC_GD5 : in std_logic; --not used
DAC_GD6 : in std_logic; --not used
DAC_GD7 : in std_logic; --not used
SRAM_D0 : in std_logic; --not used
SRAM_D1 : in std_logic; --not used
SRAM_D2 : in std_logic; --not used
SRAM_D3 : in std_logic; --not used
SRAM_D4 : in std_logic; --not used
SRAM_D5 : in std_logic; --not used
SRAM_D6 : in std_logic; --not used
SRAM_D7 : in std_logic; --not used
SRAM_D8 : in std_logic; --not used
SRAM_D9 : in std_logic; --not used
SRAM_D10 : in std_logic; --not used
SRAM_D11 : in std_logic; --not used
SRAM_D12 : in std_logic; --not used
SRAM_D13 : in std_logic; --not used
SRAM_D14 : in std_logic; --not used
SRAM_D15 : in std_logic; --not used
SRAM_A0 : in std_logic; --not used
SRAM_A1 : in std_logic; --not used
SRAM_A2 : in std_logic; --not used
SRAM_A3 : in std_logic; --not used
SRAM_A4 : in std_logic; --not used
SRAM_A5 : in std_logic; --not used
SRAM_A6 : in std_logic; --not used
SRAM_A7 : in std_logic; --not used
SRAM_A8 : in std_logic; --not used
SRAM_A9 : in std_logic; --not used
SRAM_A10 : in std_logic; --not used
SRAM_A11 : in std_logic; --not used
SRAM_A12 : in std_logic; --not used
SRAM_A13 : in std_logic; --not used
SRAM_A14 : in std_logic; --not used
SRAM_A15 : in std_logic; --not used
SRAM_A16 : in std_logic; --not used
SRAM_A17 : in std_logic; --not used
SRAM_A18 : in std_logic; --not used
SRAM_A19 : in std_logic; --not used
SRAM_A20 : in std_logic; --not used
SRAM_A21 : in std_logic; --not used
SRAM_WAIT : in std_logic; --not used
SRAM_CE : in std_logic; --not used
----------USB
O_usb_pclk : out std_logic; --CTL[0] SLCS#
--CTL[1] SLWR#
I_usb_flga : in std_logic := '0'; --CTL[2] SLOE#
I_usb_flgb : in std_logic := '0'; --CTL[3] SLRD#
--CTL[4] FLAGA
O_usb_cs : out std_logic; --CTL[5] FLAGB
O_usb_wr : out std_logic; --CTL[7] PKTEND#
O_usb_rd : out std_logic; --CTL[11] A1
O_usb_oe : out std_logic; --CTL[12] A0
O_usb_a0 : out std_logic;
O_usb_a1 : out std_logic;
O_usb_pkt : out std_logic;
O_usb_int : out std_logic;
O_usb_reset : out std_logic;
IO_usb_dq : inout std_logic_vector(31 downto 0);
O_usb_uart_rxd : out std_logic;
I_usb_uart_rts : in std_logic; --not used
I_usb_uart_txd : in std_logic;
O_usb_uart_cts : out std_logic; --not used
----------USB unused
USB_CTL6 : in std_logic; --not used
USB_CTL8 : in std_logic; --not used
USB_CTL9 : in std_logic; --not used
USB_CTL10 : in std_logic; --not used
O_usb_clk : out std_logic;
O_usb_i2s : out std_logic_vector(3 downto 0); --not used
O_usb_gpio : out std_logic_vector(5 downto 0); --not used
-- PCIE_RX_0 : in std_logic;
-- PCIE_RX_1 : in std_logic;
-- PCIE_RX_2 : in std_logic;
-- PCIE_RX_3 : in std_logic;
-- PCIE_TX_0 : out std_logic;
-- PCIE_TX_1 : out std_logic;
-- PCIE_TX_2 : out std_logic;
-- PCIE_TX_3 : out std_logic;
-- PCIE_RCLK : in std_logic;
USB_CLKIN : in std_logic; --not used
-- FPGA_CLK : in std_logic;--LVDS
DAC_GCLK : in std_logic; -- 未使用 --not used
KEYIN0 : in std_logic; -- button
O_led : out std_logic_vector(3 downto 0) -- LED
);
end HUCB2P0_TOP;
architecture arc_HUCB2P0_TOP of HUCB2P0_TOP is
component pll_conf -- PLL AD9518
port
(
I_clk : in std_logic;
I_reset_n : in std_logic;
O_ADC_ready : out std_logic;
O_FPGA_ADC_d : out std_logic;
O_FPGA_ADC_clk : out std_logic;
O_FPGA_ADC_en : out std_logic;
O_FPGA_ADC_reset : out std_logic
);
end component;
component LED_HANDLE -- 未使用
port
(
I_26M_clk : in std_logic;
I_reset_n : in std_logic;
I_led_dis : in std_logic_vector(3 downto 0);
I_adc_dis : in std_logic;
I_fifo_full : in std_logic;
O_fpga_led0 : out std_logic;
O_fpga_led1 : out std_logic;
O_fpga_led2 : out std_logic;
O_fpga_led3 : out std_logic
);
end component;
component frontend -- 重要，数据采集时序。
port
(
I_reset_n : in std_logic;
I_sys_clk : in std_logic;
I_scan_trig : in std_logic; --scan triger
I_reg_csr : in std_logic_vector(31 downto 0);
--ADC
I_adc_d : in std_logic_vector(11 downto 0);
I_adc_or : in std_logic;
I_f2pc_full : in std_logic;
O_pixel_symbol : out std_logic;
O_pixel_en : out std_logic;
O_pixel_data : out std_logic_vector(15 downto 0);
O_pulse_trig : out std_logic;
O_shake_start : out std_logic
);
end component;
component Interface -- 采集时序和USB3.0时序之间的连接
port
(
I_reset_n : in std_logic;
I_sys_clk : in std_logic;
--work control
O_register : out std_logic_vector(31 downto 0);
--image data output
I_data_en : in std_logic;
I_data_symbol : in std_logic;
I_data : in std_logic_vector(15 downto 0);
---usb FIFO
O_wfifo_reset : out std_logic;
O_usb_wrreq : out std_logic;
O_usb_din : out std_logic_vector(15 downto 0);
O_usb_rdreq : out std_logic;
I_usb_dout : in std_logic_vector(31 downto 0);
I_usb_rdempty : in std_logic
);
end component;
component usb_121pll -- USB逻辑时钟倍频 20->60
port
(
refclk : in std_logic := '0'; -- refclk.clk
rst : in std_logic := '0'; -- reset.reset
outclk_0 : out std_logic; -- outclk0.clk
outclk_1 : out std_logic; -- outclk0.clk
locked : out std_logic -- locked.export
);
end component;
component adc_pll -- ADC时钟分频，240->60
port
(
refclk : in std_logic := '0'; -- refclk.clk
rst : in std_logic := '0'; -- reset.reset
outclk_0 : out std_logic; -- outclk0.clk
outclk_1 : out std_logic -- locked.export
);
end component;
component pulse -- 超声发射
port
(
I_clk : in std_logic;
I_reset_n : in std_logic;
I_pulse_trig : in std_logic;
O_pulse : out std_logic_vector(3 downto 0)
);
end component;
component AD9634 -- 未使用
port
(
I_adce_clk : in std_logic;
I_adce_d : in std_logic_vector(5 downto 0);
I_adce_or : in std_logic;--LVDS
O_adce_csb : out std_logic;
O_adce_sdio : out std_logic;
O_adce_sclk : out std_logic;
O_adce_data : out std_logic_vector(11 downto 0)
);
end component;
component AD9235 -- 未使用
port
(
I_m_adc_d : in std_logic_vector(11 downto 0);
O_m_adc_clk : out std_logic;
I_m_adc_otr : in std_logic;
O_m_adc_pdwn : out std_logic
);
end component;
component ADS58C48 -- 未使用
port
(
O_adca_sen : out std_logic;
I_adca_sd : in std_logic;
O_adca_sdata : out std_logic;
O_adca_sclk : out std_logic;
O_adca_rst : out std_logic;
O_adca_pdn : out std_logic;
O_adca_snrb0 : out std_logic;
O_adca_snrb1 : out std_logic;
I_adca_oclk : in std_logic;
I_adca_d : in std_logic_vector(5 downto 0);
I_adcb_d : in std_logic_vector(5 downto 0);
I_adcc_d : in std_logic_vector(5 downto 0);
I_adcd_d : in std_logic_vector(5 downto 0);
O_adca_data : out std_logic_vector(11 downto 0);
O_adcb_data : out std_logic_vector(11 downto 0);
O_adcc_data : out std_logic_vector(11 downto 0);
O_adcd_data : out std_logic_vector(11 downto 0)
);
end component;
component p2s_dac -- AD5300，DAC时序，串行控制。
port(
a,clk,clr : in std_logic;
datain1 : in std_logic_vector(15 downto 0);
ld,s_data : out std_logic);
end component;
component sine_rom -- 正弦波查找表
PORT
(
address : IN STD_LOGIC_VECTOR (6 DOWNTO 0);
clock : IN STD_LOGIC := '1';
q : OUT STD_LOGIC_VECTOR (7 DOWNTO 0)
);
END component;
COMPONENT usb_top -- 新版本USB3.0时序，对用户来说就是操作FIFO。
PORT
(
I_sys_clk : IN STD_LOGIC := '1';
I_usb_clk : IN STD_LOGIC;
I_sys_rst : IN STD_LOGIC ;
I_usb_rst : IN STD_LOGIC;
I_usb_wfifo_aclr : IN STD_LOGIC;
I_usb_wrreq : IN STD_LOGIC;
I_usb_din : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
O_usb_wrfull : OUT STD_LOGIC;
O_usb_wruesdw : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
I_usb_rdreq : IN STD_LOGIC;
O_usb_dout : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
O_usb_rdempty : OUT STD_LOGIC;
I_usb_uart_tx_req : IN STD_LOGIC;
I_usb_uart_tx_data : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
O_usb_uart_tx_full : OUT STD_LOGIC;
I_usb_uart_rx_req : IN STD_LOGIC;
O_usb_uart_rx_data : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
O_usb_uart_rx_empty : OUT STD_LOGIC;
O_usb_pclk : OUT STD_LOGIC;
O_usb_clk : OUT STD_LOGIC;
I_usb_flga : IN STD_LOGIC;
I_usb_flgb : IN STD_LOGIC;
O_usb_cs : OUT STD_LOGIC;
O_usb_wr : OUT STD_LOGIC;
O_usb_rd : OUT STD_LOGIC;
O_usb_oe : OUT STD_LOGIC;
O_usb_a0 : OUT STD_LOGIC;
O_usb_a1 : OUT STD_LOGIC;
O_usb_pkt : OUT STD_LOGIC;
O_usb_reset : OUT STD_LOGIC;
IO_usb_dq : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0);
O_usb_uart_txd : OUT STD_LOGIC;
I_usb_uart_rxd : IN STD_LOGIC;
I_usb_dir : IN STD_LOGIC
);
END COMPONENT;
COMPONENT register_ctrl_top -- USB桥接芯片的串口通信部分，主要功能是接收上位机控制命令。
PORT
(
I_sys_clk : IN STD_LOGIC := '1';
I_sys_rst : IN STD_LOGIC := '1';
O_usb_uart_tx_req : OUT STD_LOGIC;
O_usb_uart_tx_data : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
I_usb_uart_tx_full : IN STD_LOGIC := '0';
O_usb_uart_rx_req : OUT STD_LOGIC;
I_usb_uart_rx_data : IN STD_LOGIC_VECTOR(7 DOWNTO 0) := "00000000";
I_usb_uart_rx_empty : IN STD_LOGIC := '0';
O_usb_dir : OUT STD_LOGIC;
O_motor_start : OUT STD_LOGIC;
tp : OUT STD_LOGIC;
I_key_start : IN STD_LOGIC := '1'
);
END COMPONENT;
signal S_usb_wrfull : std_logic:= '0';
signal S_pulse : std_logic_vector (3 downto 0);
signal s_trig_pulse : std_logic;
constant c_speed_test : integer := 40000;
signal s_reset : std_logic := '0';
signal s_scan_trig : std_logic;
signal s_scan_trig_buf : std_logic;
signal s_pll_reset : std_logic;
signal S_pll_ready : std_logic;
signal S_usb_wrreq : std_logic;
signal S_usb_din : std_logic_vector(15 downto 0);
signal S_usb_wrusedw : std_logic_vector(15 downto 0):="0000000000000000";
signal S_usb_rdreq : std_logic;
signal S_usb_dout : std_logic_vector(31 downto 0);
signal S_usb_rdempty : std_logic;
signal S_usb_rdusedw : std_logic_vector(4 downto 0);
------------usb write state-------------
signal S_usb_wr_state : std_logic_vector(1 downto 0);
signal S_usb_wr_cnt : std_logic_vector(9 downto 0);
------------usb read state--------------
signal S_usb_pulse_state: std_logic_vector(1 downto 0);
signal s_usb_clk : std_logic;
signal s_pll_locked : std_logic;
-------constant for reset and logic judgement------------------
constant C_RST_ON : std_logic := '0'; --reset signal the system is low reset
constant C_ACT_ON : std_logic := '1'; --logic judgement signal
constant C_ACT_OFF : std_logic := '0';
signal S_case_test : std_logic_vector(1 downto 0);
signal S_case_work : std_logic_vector(1 downto 0);
signal S_ad_buf : std_logic_vector(11 downto 0);
signal S_ad_1buf : std_logic_vector(15 downto 0);
signal S_register : std_logic_vector(31 downto 0):="00000000000000000000000000000000";
signal s_test_cn : std_logic_vector(19 downto 0);
signal s_work_cn : std_logic_vector(19 downto 0);
signal s_line_no : std_logic_vector(15 downto 0);
signal s_line_comb : std_logic_vector(15 downto 0);
signal s_pixel_data : std_logic_vector(15 downto 0);
signal S_pixel_symbol : std_logic;
signal S_pixel_en : std_logic;
signal s_sys_clk : std_logic;
signal s_sys_reset : std_logic;
signal s_pll_lock : std_logic;
signal S_pulse_trig : std_logic;
signal S_swi4 : std_logic;
signal S_key_start_dcnt : std_logic_vector (15 downto 0):="0000000000000000";
signal S_key_start_dclk : std_logic;
signal S_adce_data : std_logic_vector(11 downto 0);
signal S_adca_data : std_logic_vector(11 downto 0);
signal S_adcb_data : std_logic_vector(11 downto 0);
signal S_adcc_data : std_logic_vector(11 downto 0);
signal S_adcd_data : std_logic_vector(11 downto 0);
signal s_clk_60m : std_logic;
signal s_clk_60m_st : std_logic;
signal S_DA_SYNC : std_logic;
signal S_DA_cnt : std_logic_vector(4 downto 0):="00000";
signal S_DA_a : std_logic;
signal S_DA_addr : std_logic_vector(7 downto 0);
signal S_DA_rom_q : std_logic_vector(7 downto 0);
signal S_KEYIN0 : std_logic;
signal S_clk_4883_cnt : std_logic_vector(7 downto 0);
signal S_clk_4883 : std_logic:='0';
signal S_key0_cnt : std_logic_vector(24 downto 0);
signal S_key0_dclk : std_logic;
signal S_usb_uart_tx_req : std_logic;
signal S_usb_uart_tx_data : std_logic_vector(7 downto 0);
signal S_usb_uart_tx_full : std_logic;
signal S_usb_uart_rx_req : std_logic;
signal S_usb_uart_rx_data : std_logic_vector(7 downto 0);
signal S_usb_uart_rx_empty : std_logic;
signal S_usb_dir : std_logic;
signal S_motor_start : std_logic;
signal s_usb_clk_180 : std_logic;
signal S_motor_start_delay : std_logic;
signal S_shake_start : std_logic:='0';
signal S_key_start_temp1 : std_logic;
signal S_key_start_temp2 : std_logic;
signal S_key_start : std_logic;
begin
--s_sys_clk <= I_adcf_clk;
O_pll_pd <= '1'; --Chip Power Down, Active Low
O_pll_sync <= '1'; --Manual Synchronizations and Manual Holdover, Active Low
O_pll_rst <= not s_pll_reset;
O_adcf_pwdn <= '0';
O_adcf_csb <= '1';
O_adcf_sclk <= '1';
O_adcf_sdio <= '1';
O_adcf_reset <= '1';
--------------------------------
--pulse
--------------------------------
--O_pulse_0pd <= '0'; --1 power down
--O_pulse_1pd <= '0';
--O_pulse_2pd <= '0';
--O_pulse_3pd <= '0';
--O_pulse <= S_pulse;
--O_8020islpulse <= S_pulse;
--O_8020mdpulse(7 downto 6) <= S_pulse(1 downto 0);
O_8220pulse(3 downto 0) <= S_pulse(3 downto 0);
U0 : pll_conf -- 用于片外PLL配置ADC时钟，也可以不看。
port map
(
I_clk => I_ref_clk, --20M
I_reset_n => s_pll_lock ,
O_ADC_ready => S_pll_ready,
O_FPGA_ADC_d => O_pll_sdio,
O_FPGA_ADC_clk => O_pll_sclk,
O_FPGA_ADC_en => O_pll_cs,
O_FPGA_ADC_reset => s_pll_reset
);
U1_LED_HANDLE : LED_HANDLE
port map
(
I_26M_clk => I_ref_clk ,
I_reset_n => s_pll_lock ,
I_led_dis => "0100" ,
I_adc_dis => '0' ,
I_fifo_full => S_usb_wrfull ,
O_fpga_led0 => open,--O_led(0) ,
O_fpga_led1 => open,--O_led(1) ,
O_fpga_led2 => open,--O_led(2) ,
O_fpga_led3 => open--O_led(3)
);
U0_pulse : pulse -- 5M发射，60M时钟，类似于分频实现，可参考TC8220的发射时序。
port map
(
I_clk => s_clk_60m,--s_sys_clk,
I_reset_n => s_pll_lock,
I_pulse_trig => S_pulse_trig,--s_trig_pulse,
O_pulse => S_pulse
);
--------------------------------
--pulse
--------------------------------
O_pulse_0pd <= '0'; --1 power down
O_pulse_1pd <= '0';
O_pulse_2pd <= '1';
O_pulse_3pd <= '1';
s_sys_reset <= not I_reset;
U4_usb_pll : usb_121pll -- USB逻辑时钟
port map
(
refclk => I_ref_clk, --20M--
rst => s_sys_reset,
outclk_0 => s_usb_clk, --60M--
outclk_1 => s_usb_clk_180, --60M--
locked => s_pll_lock ----
);
U5_adc_pll : adc_pll -- ADC随路时钟分频得到的60M，用于数据采集。
port map
(
refclk => I_adcf_clk, --240M
rst => s_sys_reset,
outclk_0 => s_clk_60m,
outclk_1 => s_clk_60m_st
);
U0_frontend : frontend -- 重要，数据采集时序。
port map
(
I_reset_n => s_pll_lock ,
I_sys_clk => s_clk_60m ,
I_scan_trig => S_motor_start_delay, --motor start--
I_reg_csr => s_register, -- not used --
--ADC
I_adc_d => I_adcf_d,
I_adc_or => I_adcf_or ,
I_f2pc_full => S_usb_wrfull , --not used--
O_pixel_symbol => S_pixel_symbol, --receive valid--
O_pixel_en => S_pixel_en, --18000 period valid --
O_pixel_data => S_pixel_data, --receive data --
O_pulse_trig => S_pulse_trig, --trans valid --
O_shake_start => S_shake_start -- shake valid --
);
U4_interface : Interface -- 采集时序和USB3.0时序之间的连接
port map
(
I_reset_n => s_pll_lock,
I_sys_clk => s_clk_60m,
--work control
O_register => s_register, -- output not used--
--image data output
I_data_en => S_pixel_en, --18000 period valid--
I_data_symbol => S_pixel_symbol, --receive valid--
I_data => S_pixel_data, --receive data --
---usb FIFO
O_wfifo_reset => s_reset, --output for usb_top--
O_usb_wrreq => S_usb_wrreq, --output for usb_top--
O_usb_din => S_usb_din, --output for usb_top--
O_usb_rdreq => S_usb_rdreq, --output for usb_top--
I_usb_dout => S_usb_dout, --input from usb_top--
I_usb_rdempty => S_usb_rdempty --input from usb_top--
);
U33_usbcore : usb_top -- USB3.0
port map
(
I_sys_clk => s_clk_60m, --60M--
I_usb_clk => s_usb_clk, --60M--
I_sys_rst => not s_pll_lock,
I_usb_rst => not s_pll_lock,
I_usb_wfifo_aclr => s_reset, --input
I_usb_wrreq => S_usb_wrreq, --input
I_usb_din => S_usb_din, --input
O_usb_wrfull => S_usb_wrfull, --output-- not used--
O_usb_wruesdw => S_usb_wrusedw, --output-- not used--
I_usb_rdreq => S_usb_rdreq, --input--
O_usb_dout => S_usb_dout, --output--
O_usb_rdempty => S_usb_rdempty, --output--
I_usb_uart_tx_req => S_usb_uart_tx_req, --input--
I_usb_uart_tx_data => S_usb_uart_tx_data,--input--
O_usb_uart_tx_full => S_usb_uart_tx_full,--output--
I_usb_uart_rx_req => S_usb_uart_rx_req, --input--
O_usb_uart_rx_data => S_usb_uart_rx_data,--output--
O_usb_uart_rx_empty => S_usb_uart_rx_empty,--output--
O_usb_pclk => open, --O_usb_pclk,
O_usb_clk => open,
I_usb_flga => I_usb_flga, --input--
I_usb_flgb => I_usb_flgb, --input--
O_usb_cs => O_usb_cs, --output--
O_usb_wr => O_usb_wr, --output--
O_usb_rd => O_usb_rd, --output--
O_usb_oe => O_usb_oe, --output--
O_usb_a0 => O_usb_a0, --output--
O_usb_a1 => O_usb_a1, --output--
O_usb_pkt => O_usb_pkt, --output-- not used --
O_usb_reset => O_usb_reset, --output-- not used--
IO_usb_dq => IO_usb_dq, --inout--
O_usb_uart_txd => O_usb_uart_rxd, --output--
I_usb_uart_rxd => I_usb_uart_txd, --input--
I_usb_dir => S_usb_dir --input--
);
O_usb_pclk <= s_usb_clk_180;
U44_register_ctrl_top : register_ctrl_top
port map
(
I_sys_clk => s_clk_60m,
I_sys_rst => not s_pll_lock,
O_usb_uart_tx_req => S_usb_uart_tx_req,
O_usb_uart_tx_data => S_usb_uart_tx_data,
I_usb_uart_tx_full => S_usb_uart_tx_full,
O_usb_uart_rx_req => S_usb_uart_rx_req,
I_usb_uart_rx_data => S_usb_uart_rx_data,
I_usb_uart_rx_empty => S_usb_uart_rx_empty,
O_usb_dir => S_usb_dir,
O_motor_start => S_motor_start,
tp => open,
I_key_start => S_key_start
);
U5_AD9634 : AD9634 -- 未使用
port map
(
I_adce_clk => I_adce_clk,
I_adce_d => I_adce_d,
I_adce_or => I_adce_or,
O_adce_csb => O_adce_csb,
O_adce_sdio => O_adce_sdio,
O_adce_sclk => O_adce_sclk,
O_adce_data => S_adce_data
);
U6_AD9235 : AD9235 -- 未使用
port map
(
I_m_adc_d => I_m_adc_d,
O_m_adc_clk => O_m_adc_clk,
I_m_adc_otr => I_m_adc_otr,
O_m_adc_pdwn => O_m_adc_pdwn
);
U7_ADS58C48 : ADS58C48 -- 未使用
port map
(
O_adca_sen => O_adca_sen,
I_adca_sd => I_adca_sd,
O_adca_sdata => O_adca_sdata,
O_adca_sclk => O_adca_sclk,
O_adca_rst => O_adca_rst,
O_adca_pdn => O_adca_pdn,
O_adca_snrb0 => O_adca_snrb0,
O_adca_snrb1 => O_adca_snrb1,
I_adca_oclk => I_adca_oclk,
I_adca_d => I_adca_d,
I_adcb_d => I_adcb_d,
I_adcc_d => I_adcc_d,
I_adcd_d => I_adcd_d,
O_adca_data => S_adca_data,
O_adcb_data => S_adcb_data,
O_adcc_data => S_adcc_data,
O_adcd_data => S_adcd_data
);
U8_p2s_dac : p2s_dac -- AD5300，DAC时序，串行控制。
port map(
a => S_DA_a,
clk => S_clk_4883,
clr => not s_pll_lock,
datain1 => "0000000" & S_DA_rom_q(7 downto 3) & "0000",
ld => S_DA_SYNC,
s_data => DA_DIN);
DA_SYNC <= not S_DA_SYNC;
DA_SCLK <= not S_clk_4883;
process(I_ref_clk, s_pll_lock) -- 20M时钟分频，最终实现100Hz正弦，20M/128（查找表）/32（串行数据长度）/100（设计频率）=48
begin
if s_pll_lock = '0' then
S_clk_4883_cnt <= (others=>'0');
S_clk_4883 <= '0';
elsif rising_edge(I_ref_clk) then
if (S_clk_4883_cnt /= 24)then -- 24翻转一次电平，实现48分频。
S_clk_4883_cnt <= S_clk_4883_cnt + 1;
else
S_clk_4883 <= not S_clk_4883;
S_clk_4883_cnt <= (others=>'0');
end if;
end if;
end process;
process(S_clk_4883)
begin
if rising_edge(S_clk_4883) then -- 分频后的时钟用作串行时钟，此处生成16个高电平用于串行DAC时序。
S_DA_cnt <= S_DA_cnt + 1;
if S_DA_cnt >= "00001" and S_DA_cnt <= "10001" then
S_DA_a <= '1'; --valid--
else
S_DA_a <= '0';
end if;
end if;
end process;
O_led(0) <= S_motor_start_delay; -- 软件界面点开始之后，灯会灭一下，其他时间常亮，用于工作指示
O_led(1) <= S_motor_start_delay;
O_led(2) <= S_motor_start_delay;
O_led(3) <= S_motor_start_delay;
process(s_clk_60m_st, s_pll_lock,S_motor_start) -- 将上位机通过USB串口发送的开始信号的边沿转变成持续一段时间的电平，作为采集时序的开始使能。
begin
if s_pll_lock = '0' then
S_key0_cnt <= (others=>'0');
elsif rising_edge(s_clk_60m_st) then
if(S_motor_start='1') then
S_motor_start_delay <= '1';
S_key0_cnt <= "0000000000000000000000001";
elsif((S_key0_cnt>"0000000000000000000000000") and (S_key0_cnt<"1000000000000000000000000")) then
S_key0_cnt <= S_key0_cnt + 1;
else
S_motor_start_delay <= '0';
S_key0_cnt <= "0000000000000000000000000"; -- dian deng !--
end if;
end if;
end process;
process(S_DA_a,S_shake_start)--,s_register)--S_KEYIN0)
begin
-- if s_register(0) = '1' then
if S_shake_start = '0' then
S_DA_addr <= "00000000";
elsif rising_edge(S_DA_a) then -- 每发射一组串行数据，地址+1，直到128完成一次正弦波查找表。
S_DA_addr <= S_DA_addr + 1;
if S_DA_addr > "01111111" then
S_DA_addr <= "10000000";
end if;
end if;
-- else
-- S_DA_addr <= "00000000";
-- end if;
end process;
U9_sine_rom : sine_rom -- 正弦波查找表
PORT map
(
address => S_DA_addr(6 downto 0),
clock => S_DA_a,
q => S_DA_rom_q
);
O_swi_dir <= '1'; -- 电压转换芯片的方向
O_swi_oe <= '0'; -- 电压转换芯片的使能
process(I_ref_clk, s_pll_lock)
begin
if s_pll_lock = '0' then
S_key_start_dcnt <= (others=>'0');
S_key_start_dclk <= '0';
elsif rising_edge(I_ref_clk) then
S_key_start_dcnt <= S_key_start_dcnt + 1;
if (S_key_start_dcnt = 0)then
S_key_start_dclk <= not S_key_start_dclk; -- 20*10^6/2^16/2 clk period --
end if;
end if;
end process;
process(S_key_start_dclk)
begin
if rising_edge(S_key_start_dclk) then
S_key_start_temp1 <= KEYIN0;
end if;
end process;
process(s_clk_60m,S_key_start_temp1)
begin
if rising_edge(s_clk_60m) then
S_key_start_temp2 <= S_key_start_temp1;
if S_key_start_temp2 = '0' and S_key_start_temp1 = '1' then --rise--
S_key_start <= '1';
else
S_key_start <= '0';
end if;
end if;
end process;
end arc_HUCB2P0_TOP;
| apache-2.0 | 32f369ad76aa0409e01d5a77cb370de6 | 0.428949 | 3.104771 | false | false | false | false |
jairov4/accel-oil | solution_spartan6/impl/vhdl/sample_iterator_next.vhd | 1 | 31,609 | -- ==============================================================
-- RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2013.4
-- Copyright (C) 2013 Xilinx Inc. All rights reserved.
--
-- ===========================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity sample_iterator_next is
port (
ap_clk : IN STD_LOGIC;
ap_rst : IN STD_LOGIC;
ap_start : IN STD_LOGIC;
ap_done : OUT STD_LOGIC;
ap_idle : OUT STD_LOGIC;
ap_ready : OUT STD_LOGIC;
indices_samples_req_din : OUT STD_LOGIC;
indices_samples_req_full_n : IN STD_LOGIC;
indices_samples_req_write : OUT STD_LOGIC;
indices_samples_rsp_empty_n : IN STD_LOGIC;
indices_samples_rsp_read : OUT STD_LOGIC;
indices_samples_address : OUT STD_LOGIC_VECTOR (31 downto 0);
indices_samples_datain : IN STD_LOGIC_VECTOR (15 downto 0);
indices_samples_dataout : OUT STD_LOGIC_VECTOR (15 downto 0);
indices_samples_size : OUT STD_LOGIC_VECTOR (31 downto 0);
ap_ce : IN STD_LOGIC;
indices_begin_req_din : OUT STD_LOGIC;
indices_begin_req_full_n : IN STD_LOGIC;
indices_begin_req_write : OUT STD_LOGIC;
indices_begin_rsp_empty_n : IN STD_LOGIC;
indices_begin_rsp_read : OUT STD_LOGIC;
indices_begin_address : OUT STD_LOGIC_VECTOR (31 downto 0);
indices_begin_datain : IN STD_LOGIC_VECTOR (31 downto 0);
indices_begin_dataout : OUT STD_LOGIC_VECTOR (31 downto 0);
indices_begin_size : OUT STD_LOGIC_VECTOR (31 downto 0);
indices_stride_req_din : OUT STD_LOGIC;
indices_stride_req_full_n : IN STD_LOGIC;
indices_stride_req_write : OUT STD_LOGIC;
indices_stride_rsp_empty_n : IN STD_LOGIC;
indices_stride_rsp_read : OUT STD_LOGIC;
indices_stride_address : OUT STD_LOGIC_VECTOR (31 downto 0);
indices_stride_datain : IN STD_LOGIC_VECTOR (7 downto 0);
indices_stride_dataout : OUT STD_LOGIC_VECTOR (7 downto 0);
indices_stride_size : OUT STD_LOGIC_VECTOR (31 downto 0);
i_index : IN STD_LOGIC_VECTOR (15 downto 0);
i_sample : IN STD_LOGIC_VECTOR (15 downto 0);
ap_return_0 : OUT STD_LOGIC_VECTOR (15 downto 0);
ap_return_1 : OUT STD_LOGIC_VECTOR (15 downto 0) );
end;
architecture behav of sample_iterator_next is
constant ap_const_logic_1 : STD_LOGIC := '1';
constant ap_const_logic_0 : STD_LOGIC := '0';
constant ap_ST_pp0_stg0_fsm_0 : STD_LOGIC_VECTOR (0 downto 0) := "0";
constant ap_const_lv32_0 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000000";
constant ap_const_lv32_1 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000001";
constant ap_const_lv17_1FFFF : STD_LOGIC_VECTOR (16 downto 0) := "11111111111111111";
constant ap_const_lv16_1 : STD_LOGIC_VECTOR (15 downto 0) := "0000000000000001";
constant ap_const_lv16_0 : STD_LOGIC_VECTOR (15 downto 0) := "0000000000000000";
constant ap_const_lv8_0 : STD_LOGIC_VECTOR (7 downto 0) := "00000000";
signal ap_CS_fsm : STD_LOGIC_VECTOR (0 downto 0) := "0";
signal ap_reg_ppiten_pp0_it0 : STD_LOGIC;
signal ap_reg_ppiten_pp0_it1 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it2 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it3 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it4 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it5 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it6 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it7 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it8 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it9 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it10 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it11 : STD_LOGIC := '0';
signal i_sample_read_reg_128 : STD_LOGIC_VECTOR (15 downto 0);
signal ap_reg_ppstg_i_sample_read_reg_128_pp0_it1 : STD_LOGIC_VECTOR (15 downto 0);
signal ap_reg_ppstg_i_sample_read_reg_128_pp0_it2 : STD_LOGIC_VECTOR (15 downto 0);
signal ap_reg_ppstg_i_sample_read_reg_128_pp0_it3 : STD_LOGIC_VECTOR (15 downto 0);
signal ap_reg_ppstg_i_sample_read_reg_128_pp0_it4 : STD_LOGIC_VECTOR (15 downto 0);
signal ap_reg_ppstg_i_sample_read_reg_128_pp0_it5 : STD_LOGIC_VECTOR (15 downto 0);
signal ap_reg_ppstg_i_sample_read_reg_128_pp0_it6 : STD_LOGIC_VECTOR (15 downto 0);
signal ap_reg_ppstg_i_sample_read_reg_128_pp0_it7 : STD_LOGIC_VECTOR (15 downto 0);
signal ap_reg_ppstg_i_sample_read_reg_128_pp0_it8 : STD_LOGIC_VECTOR (15 downto 0);
signal ap_reg_ppstg_i_sample_read_reg_128_pp0_it9 : STD_LOGIC_VECTOR (15 downto 0);
signal i_index_read_reg_134 : STD_LOGIC_VECTOR (15 downto 0);
signal ap_reg_ppstg_i_index_read_reg_134_pp0_it1 : STD_LOGIC_VECTOR (15 downto 0);
signal ap_reg_ppstg_i_index_read_reg_134_pp0_it2 : STD_LOGIC_VECTOR (15 downto 0);
signal ap_reg_ppstg_i_index_read_reg_134_pp0_it3 : STD_LOGIC_VECTOR (15 downto 0);
signal ap_reg_ppstg_i_index_read_reg_134_pp0_it4 : STD_LOGIC_VECTOR (15 downto 0);
signal ap_reg_ppstg_i_index_read_reg_134_pp0_it5 : STD_LOGIC_VECTOR (15 downto 0);
signal ap_reg_ppstg_i_index_read_reg_134_pp0_it6 : STD_LOGIC_VECTOR (15 downto 0);
signal ap_reg_ppstg_i_index_read_reg_134_pp0_it7 : STD_LOGIC_VECTOR (15 downto 0);
signal ap_reg_ppstg_i_index_read_reg_134_pp0_it8 : STD_LOGIC_VECTOR (15 downto 0);
signal ap_reg_ppstg_i_index_read_reg_134_pp0_it9 : STD_LOGIC_VECTOR (15 downto 0);
signal ap_reg_ppstg_i_index_read_reg_134_pp0_it10 : STD_LOGIC_VECTOR (15 downto 0);
signal indices_samples_addr_read_reg_146 : STD_LOGIC_VECTOR (15 downto 0);
signal grp_fu_77_p2 : STD_LOGIC_VECTOR (16 downto 0);
signal tmp_6_reg_156 : STD_LOGIC_VECTOR (16 downto 0);
signal tmp_7_fu_99_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_7_reg_161 : STD_LOGIC_VECTOR (0 downto 0);
signal grp_fu_83_p2 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_8_reg_167 : STD_LOGIC_VECTOR (15 downto 0);
signal grp_fu_88_p2 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_9_reg_172 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_s_fu_63_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal grp_fu_77_p0 : STD_LOGIC_VECTOR (16 downto 0);
signal grp_fu_77_p1 : STD_LOGIC_VECTOR (16 downto 0);
signal grp_fu_83_p0 : STD_LOGIC_VECTOR (15 downto 0);
signal grp_fu_83_p1 : STD_LOGIC_VECTOR (15 downto 0);
signal grp_fu_88_p0 : STD_LOGIC_VECTOR (15 downto 0);
signal grp_fu_88_p1 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_cast_fu_93_p1 : STD_LOGIC_VECTOR (17 downto 0);
signal tmp_7_fu_99_p1 : STD_LOGIC_VECTOR (17 downto 0);
signal tmp_6_reg_156_temp: signed (17-1 downto 0);
signal agg_result_index_write_assign_fu_111_p3 : STD_LOGIC_VECTOR (15 downto 0);
signal agg_result_sample_write_assign_fu_105_p3 : STD_LOGIC_VECTOR (15 downto 0);
signal grp_fu_77_ce : STD_LOGIC;
signal grp_fu_83_ce : STD_LOGIC;
signal grp_fu_88_ce : STD_LOGIC;
signal ap_NS_fsm : STD_LOGIC_VECTOR (0 downto 0);
signal ap_sig_pprstidle_pp0 : STD_LOGIC;
component nfa_accept_samples_generic_hw_add_17ns_17s_17_4 IS
generic (
ID : INTEGER;
NUM_STAGE : INTEGER;
din0_WIDTH : INTEGER;
din1_WIDTH : INTEGER;
dout_WIDTH : INTEGER );
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
din0 : IN STD_LOGIC_VECTOR (16 downto 0);
din1 : IN STD_LOGIC_VECTOR (16 downto 0);
ce : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR (16 downto 0) );
end component;
component nfa_accept_samples_generic_hw_add_16ns_16ns_16_4 IS
generic (
ID : INTEGER;
NUM_STAGE : INTEGER;
din0_WIDTH : INTEGER;
din1_WIDTH : INTEGER;
dout_WIDTH : INTEGER );
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
din0 : IN STD_LOGIC_VECTOR (15 downto 0);
din1 : IN STD_LOGIC_VECTOR (15 downto 0);
ce : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR (15 downto 0) );
end component;
begin
nfa_accept_samples_generic_hw_add_17ns_17s_17_4_U30 : component nfa_accept_samples_generic_hw_add_17ns_17s_17_4
generic map (
ID => 30,
NUM_STAGE => 4,
din0_WIDTH => 17,
din1_WIDTH => 17,
dout_WIDTH => 17)
port map (
clk => ap_clk,
reset => ap_rst,
din0 => grp_fu_77_p0,
din1 => grp_fu_77_p1,
ce => grp_fu_77_ce,
dout => grp_fu_77_p2);
nfa_accept_samples_generic_hw_add_16ns_16ns_16_4_U31 : component nfa_accept_samples_generic_hw_add_16ns_16ns_16_4
generic map (
ID => 31,
NUM_STAGE => 4,
din0_WIDTH => 16,
din1_WIDTH => 16,
dout_WIDTH => 16)
port map (
clk => ap_clk,
reset => ap_rst,
din0 => grp_fu_83_p0,
din1 => grp_fu_83_p1,
ce => grp_fu_83_ce,
dout => grp_fu_83_p2);
nfa_accept_samples_generic_hw_add_16ns_16ns_16_4_U32 : component nfa_accept_samples_generic_hw_add_16ns_16ns_16_4
generic map (
ID => 32,
NUM_STAGE => 4,
din0_WIDTH => 16,
din1_WIDTH => 16,
dout_WIDTH => 16)
port map (
clk => ap_clk,
reset => ap_rst,
din0 => grp_fu_88_p0,
din1 => grp_fu_88_p1,
ce => grp_fu_88_ce,
dout => grp_fu_88_p2);
-- the current state (ap_CS_fsm) of the state machine. --
ap_CS_fsm_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_CS_fsm <= ap_ST_pp0_stg0_fsm_0;
else
ap_CS_fsm <= ap_NS_fsm;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it1 assign process. --
ap_reg_ppiten_pp0_it1_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_reg_ppiten_pp0_it1 <= ap_const_logic_0;
else
if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it5) and (indices_samples_rsp_empty_n = ap_const_logic_0)) or not((ap_const_logic_1 = ap_ce)))))) then
ap_reg_ppiten_pp0_it1 <= ap_reg_ppiten_pp0_it0;
end if;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it10 assign process. --
ap_reg_ppiten_pp0_it10_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_reg_ppiten_pp0_it10 <= ap_const_logic_0;
else
if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it5) and (indices_samples_rsp_empty_n = ap_const_logic_0)) or not((ap_const_logic_1 = ap_ce)))))) then
ap_reg_ppiten_pp0_it10 <= ap_reg_ppiten_pp0_it9;
end if;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it11 assign process. --
ap_reg_ppiten_pp0_it11_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_reg_ppiten_pp0_it11 <= ap_const_logic_0;
else
if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it5) and (indices_samples_rsp_empty_n = ap_const_logic_0)) or not((ap_const_logic_1 = ap_ce)))))) then
ap_reg_ppiten_pp0_it11 <= ap_reg_ppiten_pp0_it10;
end if;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it2 assign process. --
ap_reg_ppiten_pp0_it2_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_reg_ppiten_pp0_it2 <= ap_const_logic_0;
else
if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it5) and (indices_samples_rsp_empty_n = ap_const_logic_0)) or not((ap_const_logic_1 = ap_ce)))))) then
ap_reg_ppiten_pp0_it2 <= ap_reg_ppiten_pp0_it1;
end if;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it3 assign process. --
ap_reg_ppiten_pp0_it3_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_reg_ppiten_pp0_it3 <= ap_const_logic_0;
else
if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it5) and (indices_samples_rsp_empty_n = ap_const_logic_0)) or not((ap_const_logic_1 = ap_ce)))))) then
ap_reg_ppiten_pp0_it3 <= ap_reg_ppiten_pp0_it2;
end if;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it4 assign process. --
ap_reg_ppiten_pp0_it4_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_reg_ppiten_pp0_it4 <= ap_const_logic_0;
else
if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it5) and (indices_samples_rsp_empty_n = ap_const_logic_0)) or not((ap_const_logic_1 = ap_ce)))))) then
ap_reg_ppiten_pp0_it4 <= ap_reg_ppiten_pp0_it3;
end if;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it5 assign process. --
ap_reg_ppiten_pp0_it5_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_reg_ppiten_pp0_it5 <= ap_const_logic_0;
else
if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it5) and (indices_samples_rsp_empty_n = ap_const_logic_0)) or not((ap_const_logic_1 = ap_ce)))))) then
ap_reg_ppiten_pp0_it5 <= ap_reg_ppiten_pp0_it4;
end if;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it6 assign process. --
ap_reg_ppiten_pp0_it6_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_reg_ppiten_pp0_it6 <= ap_const_logic_0;
else
if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it5) and (indices_samples_rsp_empty_n = ap_const_logic_0)) or not((ap_const_logic_1 = ap_ce)))))) then
ap_reg_ppiten_pp0_it6 <= ap_reg_ppiten_pp0_it5;
end if;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it7 assign process. --
ap_reg_ppiten_pp0_it7_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_reg_ppiten_pp0_it7 <= ap_const_logic_0;
else
if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it5) and (indices_samples_rsp_empty_n = ap_const_logic_0)) or not((ap_const_logic_1 = ap_ce)))))) then
ap_reg_ppiten_pp0_it7 <= ap_reg_ppiten_pp0_it6;
end if;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it8 assign process. --
ap_reg_ppiten_pp0_it8_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_reg_ppiten_pp0_it8 <= ap_const_logic_0;
else
if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it5) and (indices_samples_rsp_empty_n = ap_const_logic_0)) or not((ap_const_logic_1 = ap_ce)))))) then
ap_reg_ppiten_pp0_it8 <= ap_reg_ppiten_pp0_it7;
end if;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it9 assign process. --
ap_reg_ppiten_pp0_it9_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_reg_ppiten_pp0_it9 <= ap_const_logic_0;
else
if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it5) and (indices_samples_rsp_empty_n = ap_const_logic_0)) or not((ap_const_logic_1 = ap_ce)))))) then
ap_reg_ppiten_pp0_it9 <= ap_reg_ppiten_pp0_it8;
end if;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it5) and (indices_samples_rsp_empty_n = ap_const_logic_0)))) and (ap_const_logic_1 = ap_ce))) then
ap_reg_ppstg_i_index_read_reg_134_pp0_it1 <= i_index_read_reg_134;
ap_reg_ppstg_i_index_read_reg_134_pp0_it10 <= ap_reg_ppstg_i_index_read_reg_134_pp0_it9;
ap_reg_ppstg_i_index_read_reg_134_pp0_it2 <= ap_reg_ppstg_i_index_read_reg_134_pp0_it1;
ap_reg_ppstg_i_index_read_reg_134_pp0_it3 <= ap_reg_ppstg_i_index_read_reg_134_pp0_it2;
ap_reg_ppstg_i_index_read_reg_134_pp0_it4 <= ap_reg_ppstg_i_index_read_reg_134_pp0_it3;
ap_reg_ppstg_i_index_read_reg_134_pp0_it5 <= ap_reg_ppstg_i_index_read_reg_134_pp0_it4;
ap_reg_ppstg_i_index_read_reg_134_pp0_it6 <= ap_reg_ppstg_i_index_read_reg_134_pp0_it5;
ap_reg_ppstg_i_index_read_reg_134_pp0_it7 <= ap_reg_ppstg_i_index_read_reg_134_pp0_it6;
ap_reg_ppstg_i_index_read_reg_134_pp0_it8 <= ap_reg_ppstg_i_index_read_reg_134_pp0_it7;
ap_reg_ppstg_i_index_read_reg_134_pp0_it9 <= ap_reg_ppstg_i_index_read_reg_134_pp0_it8;
ap_reg_ppstg_i_sample_read_reg_128_pp0_it1 <= i_sample_read_reg_128;
ap_reg_ppstg_i_sample_read_reg_128_pp0_it2 <= ap_reg_ppstg_i_sample_read_reg_128_pp0_it1;
ap_reg_ppstg_i_sample_read_reg_128_pp0_it3 <= ap_reg_ppstg_i_sample_read_reg_128_pp0_it2;
ap_reg_ppstg_i_sample_read_reg_128_pp0_it4 <= ap_reg_ppstg_i_sample_read_reg_128_pp0_it3;
ap_reg_ppstg_i_sample_read_reg_128_pp0_it5 <= ap_reg_ppstg_i_sample_read_reg_128_pp0_it4;
ap_reg_ppstg_i_sample_read_reg_128_pp0_it6 <= ap_reg_ppstg_i_sample_read_reg_128_pp0_it5;
ap_reg_ppstg_i_sample_read_reg_128_pp0_it7 <= ap_reg_ppstg_i_sample_read_reg_128_pp0_it6;
ap_reg_ppstg_i_sample_read_reg_128_pp0_it8 <= ap_reg_ppstg_i_sample_read_reg_128_pp0_it7;
ap_reg_ppstg_i_sample_read_reg_128_pp0_it9 <= ap_reg_ppstg_i_sample_read_reg_128_pp0_it8;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it5) and (indices_samples_rsp_empty_n = ap_const_logic_0)))) and (ap_const_logic_1 = ap_ce))) then
i_index_read_reg_134 <= i_index;
i_sample_read_reg_128 <= i_sample;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it5) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it5) and (indices_samples_rsp_empty_n = ap_const_logic_0)))) and (ap_const_logic_1 = ap_ce))) then
indices_samples_addr_read_reg_146 <= indices_samples_datain;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it9) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it5) and (indices_samples_rsp_empty_n = ap_const_logic_0)))) and (ap_const_logic_1 = ap_ce))) then
tmp_6_reg_156 <= grp_fu_77_p2;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it10) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it5) and (indices_samples_rsp_empty_n = ap_const_logic_0)))) and (ap_const_logic_1 = ap_ce))) then
tmp_7_reg_161 <= tmp_7_fu_99_p2;
tmp_8_reg_167 <= grp_fu_83_p2;
tmp_9_reg_172 <= grp_fu_88_p2;
end if;
end if;
end process;
-- the next state (ap_NS_fsm) of the state machine. --
ap_NS_fsm_assign_proc : process (ap_start , ap_CS_fsm , ap_reg_ppiten_pp0_it0 , ap_reg_ppiten_pp0_it5 , indices_samples_rsp_empty_n , ap_ce , ap_sig_pprstidle_pp0)
begin
case ap_CS_fsm is
when ap_ST_pp0_stg0_fsm_0 =>
ap_NS_fsm <= ap_ST_pp0_stg0_fsm_0;
when others =>
ap_NS_fsm <= "X";
end case;
end process;
agg_result_index_write_assign_fu_111_p3 <=
ap_reg_ppstg_i_index_read_reg_134_pp0_it10 when (tmp_7_reg_161(0) = '1') else
tmp_8_reg_167;
agg_result_sample_write_assign_fu_105_p3 <=
tmp_9_reg_172 when (tmp_7_reg_161(0) = '1') else
ap_const_lv16_0;
-- ap_done assign process. --
ap_done_assign_proc : process(ap_start, ap_CS_fsm, ap_reg_ppiten_pp0_it0, ap_reg_ppiten_pp0_it5, ap_reg_ppiten_pp0_it11, indices_samples_rsp_empty_n, ap_ce)
begin
if (((not((ap_const_logic_1 = ap_start)) and (ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it0)) or ((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it11) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it5) and (indices_samples_rsp_empty_n = ap_const_logic_0)))) and (ap_const_logic_1 = ap_ce)))) then
ap_done <= ap_const_logic_1;
else
ap_done <= ap_const_logic_0;
end if;
end process;
-- ap_idle assign process. --
ap_idle_assign_proc : process(ap_start, ap_CS_fsm, ap_reg_ppiten_pp0_it0, ap_reg_ppiten_pp0_it1, ap_reg_ppiten_pp0_it2, ap_reg_ppiten_pp0_it3, ap_reg_ppiten_pp0_it4, ap_reg_ppiten_pp0_it5, ap_reg_ppiten_pp0_it6, ap_reg_ppiten_pp0_it7, ap_reg_ppiten_pp0_it8, ap_reg_ppiten_pp0_it9, ap_reg_ppiten_pp0_it10, ap_reg_ppiten_pp0_it11)
begin
if ((not((ap_const_logic_1 = ap_start)) and (ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it0) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it1) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it2) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it3) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it4) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it5) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it6) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it7) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it8) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it9) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it10) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it11))) then
ap_idle <= ap_const_logic_1;
else
ap_idle <= ap_const_logic_0;
end if;
end process;
-- ap_ready assign process. --
ap_ready_assign_proc : process(ap_start, ap_CS_fsm, ap_reg_ppiten_pp0_it0, ap_reg_ppiten_pp0_it5, indices_samples_rsp_empty_n, ap_ce)
begin
if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it5) and (indices_samples_rsp_empty_n = ap_const_logic_0)))) and (ap_const_logic_1 = ap_ce))) then
ap_ready <= ap_const_logic_1;
else
ap_ready <= ap_const_logic_0;
end if;
end process;
ap_reg_ppiten_pp0_it0 <= ap_start;
ap_return_0 <= agg_result_index_write_assign_fu_111_p3;
ap_return_1 <= agg_result_sample_write_assign_fu_105_p3;
-- ap_sig_pprstidle_pp0 assign process. --
ap_sig_pprstidle_pp0_assign_proc : process(ap_start, ap_reg_ppiten_pp0_it0, ap_reg_ppiten_pp0_it1, ap_reg_ppiten_pp0_it2, ap_reg_ppiten_pp0_it3, ap_reg_ppiten_pp0_it4, ap_reg_ppiten_pp0_it5, ap_reg_ppiten_pp0_it6, ap_reg_ppiten_pp0_it7, ap_reg_ppiten_pp0_it8, ap_reg_ppiten_pp0_it9, ap_reg_ppiten_pp0_it10)
begin
if (((ap_const_logic_0 = ap_reg_ppiten_pp0_it0) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it1) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it2) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it3) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it4) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it5) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it6) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it7) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it8) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it9) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it10) and (ap_const_logic_0 = ap_start))) then
ap_sig_pprstidle_pp0 <= ap_const_logic_1;
else
ap_sig_pprstidle_pp0 <= ap_const_logic_0;
end if;
end process;
-- grp_fu_77_ce assign process. --
grp_fu_77_ce_assign_proc : process(ap_start, ap_CS_fsm, ap_reg_ppiten_pp0_it0, ap_reg_ppiten_pp0_it5, indices_samples_rsp_empty_n, ap_ce)
begin
if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it5) and (indices_samples_rsp_empty_n = ap_const_logic_0)))) and (ap_const_logic_1 = ap_ce))) then
grp_fu_77_ce <= ap_const_logic_1;
else
grp_fu_77_ce <= ap_const_logic_0;
end if;
end process;
grp_fu_77_p0 <= std_logic_vector(resize(unsigned(indices_samples_addr_read_reg_146),17));
grp_fu_77_p1 <= ap_const_lv17_1FFFF;
-- grp_fu_83_ce assign process. --
grp_fu_83_ce_assign_proc : process(ap_start, ap_CS_fsm, ap_reg_ppiten_pp0_it0, ap_reg_ppiten_pp0_it5, indices_samples_rsp_empty_n, ap_ce)
begin
if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it5) and (indices_samples_rsp_empty_n = ap_const_logic_0)))) and (ap_const_logic_1 = ap_ce))) then
grp_fu_83_ce <= ap_const_logic_1;
else
grp_fu_83_ce <= ap_const_logic_0;
end if;
end process;
grp_fu_83_p0 <= ap_reg_ppstg_i_index_read_reg_134_pp0_it6;
grp_fu_83_p1 <= ap_const_lv16_1;
-- grp_fu_88_ce assign process. --
grp_fu_88_ce_assign_proc : process(ap_start, ap_CS_fsm, ap_reg_ppiten_pp0_it0, ap_reg_ppiten_pp0_it5, indices_samples_rsp_empty_n, ap_ce)
begin
if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it5) and (indices_samples_rsp_empty_n = ap_const_logic_0)))) and (ap_const_logic_1 = ap_ce))) then
grp_fu_88_ce <= ap_const_logic_1;
else
grp_fu_88_ce <= ap_const_logic_0;
end if;
end process;
grp_fu_88_p0 <= ap_reg_ppstg_i_sample_read_reg_128_pp0_it6;
grp_fu_88_p1 <= ap_const_lv16_1;
indices_begin_address <= ap_const_lv32_0;
indices_begin_dataout <= ap_const_lv32_0;
indices_begin_req_din <= ap_const_logic_0;
indices_begin_req_write <= ap_const_logic_0;
indices_begin_rsp_read <= ap_const_logic_0;
indices_begin_size <= ap_const_lv32_0;
indices_samples_address <= tmp_s_fu_63_p1(32 - 1 downto 0);
indices_samples_dataout <= ap_const_lv16_0;
indices_samples_req_din <= ap_const_logic_0;
-- indices_samples_req_write assign process. --
indices_samples_req_write_assign_proc : process(ap_start, ap_CS_fsm, ap_reg_ppiten_pp0_it0, ap_reg_ppiten_pp0_it5, indices_samples_rsp_empty_n, ap_ce)
begin
if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it5) and (indices_samples_rsp_empty_n = ap_const_logic_0)))) and (ap_const_logic_1 = ap_ce))) then
indices_samples_req_write <= ap_const_logic_1;
else
indices_samples_req_write <= ap_const_logic_0;
end if;
end process;
-- indices_samples_rsp_read assign process. --
indices_samples_rsp_read_assign_proc : process(ap_start, ap_CS_fsm, ap_reg_ppiten_pp0_it0, ap_reg_ppiten_pp0_it5, indices_samples_rsp_empty_n, ap_ce)
begin
if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it5) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it5) and (indices_samples_rsp_empty_n = ap_const_logic_0)))) and (ap_const_logic_1 = ap_ce))) then
indices_samples_rsp_read <= ap_const_logic_1;
else
indices_samples_rsp_read <= ap_const_logic_0;
end if;
end process;
indices_samples_size <= ap_const_lv32_1;
indices_stride_address <= ap_const_lv32_0;
indices_stride_dataout <= ap_const_lv8_0;
indices_stride_req_din <= ap_const_logic_0;
indices_stride_req_write <= ap_const_logic_0;
indices_stride_rsp_read <= ap_const_logic_0;
indices_stride_size <= ap_const_lv32_0;
tmp_6_reg_156_temp <= signed(tmp_6_reg_156);
tmp_7_fu_99_p1 <= std_logic_vector(resize(tmp_6_reg_156_temp,18));
tmp_7_fu_99_p2 <= "1" when (signed(tmp_cast_fu_93_p1) < signed(tmp_7_fu_99_p1)) else "0";
tmp_cast_fu_93_p1 <= std_logic_vector(resize(unsigned(ap_reg_ppstg_i_sample_read_reg_128_pp0_it9),18));
tmp_s_fu_63_p1 <= std_logic_vector(resize(unsigned(i_index),64));
end behav;
| lgpl-3.0 | dfa3bff55fa62e36c19c24ccbeb3b452 | 0.600019 | 2.715783 | false | false | false | false |
jairov4/accel-oil | solution_kintex7/sim/vhdl/nfa_accept_sample.vhd | 1 | 58,607 | -- ==============================================================
-- RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2013.4
-- Copyright (C) 2013 Xilinx Inc. All rights reserved.
--
-- ===========================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity nfa_accept_sample is
port (
ap_clk : IN STD_LOGIC;
ap_rst : IN STD_LOGIC;
ap_start : IN STD_LOGIC;
ap_done : OUT STD_LOGIC;
ap_idle : OUT STD_LOGIC;
ap_ready : OUT STD_LOGIC;
nfa_initials_buckets_req_din : OUT STD_LOGIC;
nfa_initials_buckets_req_full_n : IN STD_LOGIC;
nfa_initials_buckets_req_write : OUT STD_LOGIC;
nfa_initials_buckets_rsp_empty_n : IN STD_LOGIC;
nfa_initials_buckets_rsp_read : OUT STD_LOGIC;
nfa_initials_buckets_address : OUT STD_LOGIC_VECTOR (31 downto 0);
nfa_initials_buckets_datain : IN STD_LOGIC_VECTOR (31 downto 0);
nfa_initials_buckets_dataout : OUT STD_LOGIC_VECTOR (31 downto 0);
nfa_initials_buckets_size : OUT STD_LOGIC_VECTOR (31 downto 0);
nfa_finals_buckets_req_din : OUT STD_LOGIC;
nfa_finals_buckets_req_full_n : IN STD_LOGIC;
nfa_finals_buckets_req_write : OUT STD_LOGIC;
nfa_finals_buckets_rsp_empty_n : IN STD_LOGIC;
nfa_finals_buckets_rsp_read : OUT STD_LOGIC;
nfa_finals_buckets_address : OUT STD_LOGIC_VECTOR (31 downto 0);
nfa_finals_buckets_datain : IN STD_LOGIC_VECTOR (31 downto 0);
nfa_finals_buckets_dataout : OUT STD_LOGIC_VECTOR (31 downto 0);
nfa_finals_buckets_size : OUT STD_LOGIC_VECTOR (31 downto 0);
nfa_forward_buckets_req_din : OUT STD_LOGIC;
nfa_forward_buckets_req_full_n : IN STD_LOGIC;
nfa_forward_buckets_req_write : OUT STD_LOGIC;
nfa_forward_buckets_rsp_empty_n : IN STD_LOGIC;
nfa_forward_buckets_rsp_read : OUT STD_LOGIC;
nfa_forward_buckets_address : OUT STD_LOGIC_VECTOR (31 downto 0);
nfa_forward_buckets_datain : IN STD_LOGIC_VECTOR (31 downto 0);
nfa_forward_buckets_dataout : OUT STD_LOGIC_VECTOR (31 downto 0);
nfa_forward_buckets_size : OUT STD_LOGIC_VECTOR (31 downto 0);
nfa_symbols : IN STD_LOGIC_VECTOR (7 downto 0);
sample_req_din : OUT STD_LOGIC;
sample_req_full_n : IN STD_LOGIC;
sample_req_write : OUT STD_LOGIC;
sample_rsp_empty_n : IN STD_LOGIC;
sample_rsp_read : OUT STD_LOGIC;
sample_address : OUT STD_LOGIC_VECTOR (31 downto 0);
sample_datain : IN STD_LOGIC_VECTOR (7 downto 0);
sample_dataout : OUT STD_LOGIC_VECTOR (7 downto 0);
sample_size : OUT STD_LOGIC_VECTOR (31 downto 0);
tmp_14 : IN STD_LOGIC_VECTOR (31 downto 0);
length_r : IN STD_LOGIC_VECTOR (15 downto 0);
ap_return : OUT STD_LOGIC_VECTOR (0 downto 0) );
end;
architecture behav of nfa_accept_sample is
constant ap_const_logic_1 : STD_LOGIC := '1';
constant ap_const_logic_0 : STD_LOGIC := '0';
constant ap_ST_st1_fsm_0 : STD_LOGIC_VECTOR (5 downto 0) := "000000";
constant ap_ST_st2_fsm_1 : STD_LOGIC_VECTOR (5 downto 0) := "000001";
constant ap_ST_st3_fsm_2 : STD_LOGIC_VECTOR (5 downto 0) := "000010";
constant ap_ST_st4_fsm_3 : STD_LOGIC_VECTOR (5 downto 0) := "000011";
constant ap_ST_st5_fsm_4 : STD_LOGIC_VECTOR (5 downto 0) := "000100";
constant ap_ST_st6_fsm_5 : STD_LOGIC_VECTOR (5 downto 0) := "000101";
constant ap_ST_st7_fsm_6 : STD_LOGIC_VECTOR (5 downto 0) := "000110";
constant ap_ST_st8_fsm_7 : STD_LOGIC_VECTOR (5 downto 0) := "000111";
constant ap_ST_st9_fsm_8 : STD_LOGIC_VECTOR (5 downto 0) := "001000";
constant ap_ST_st10_fsm_9 : STD_LOGIC_VECTOR (5 downto 0) := "001001";
constant ap_ST_st11_fsm_10 : STD_LOGIC_VECTOR (5 downto 0) := "001010";
constant ap_ST_st12_fsm_11 : STD_LOGIC_VECTOR (5 downto 0) := "001011";
constant ap_ST_st13_fsm_12 : STD_LOGIC_VECTOR (5 downto 0) := "001100";
constant ap_ST_st14_fsm_13 : STD_LOGIC_VECTOR (5 downto 0) := "001101";
constant ap_ST_st15_fsm_14 : STD_LOGIC_VECTOR (5 downto 0) := "001110";
constant ap_ST_st16_fsm_15 : STD_LOGIC_VECTOR (5 downto 0) := "001111";
constant ap_ST_st17_fsm_16 : STD_LOGIC_VECTOR (5 downto 0) := "010000";
constant ap_ST_st18_fsm_17 : STD_LOGIC_VECTOR (5 downto 0) := "010001";
constant ap_ST_st19_fsm_18 : STD_LOGIC_VECTOR (5 downto 0) := "010010";
constant ap_ST_st20_fsm_19 : STD_LOGIC_VECTOR (5 downto 0) := "010011";
constant ap_ST_st21_fsm_20 : STD_LOGIC_VECTOR (5 downto 0) := "010100";
constant ap_ST_st22_fsm_21 : STD_LOGIC_VECTOR (5 downto 0) := "010101";
constant ap_ST_st23_fsm_22 : STD_LOGIC_VECTOR (5 downto 0) := "010110";
constant ap_ST_st24_fsm_23 : STD_LOGIC_VECTOR (5 downto 0) := "010111";
constant ap_ST_st25_fsm_24 : STD_LOGIC_VECTOR (5 downto 0) := "011000";
constant ap_ST_st26_fsm_25 : STD_LOGIC_VECTOR (5 downto 0) := "011001";
constant ap_ST_st27_fsm_26 : STD_LOGIC_VECTOR (5 downto 0) := "011010";
constant ap_ST_st28_fsm_27 : STD_LOGIC_VECTOR (5 downto 0) := "011011";
constant ap_ST_st29_fsm_28 : STD_LOGIC_VECTOR (5 downto 0) := "011100";
constant ap_ST_st30_fsm_29 : STD_LOGIC_VECTOR (5 downto 0) := "011101";
constant ap_ST_st31_fsm_30 : STD_LOGIC_VECTOR (5 downto 0) := "011110";
constant ap_ST_st32_fsm_31 : STD_LOGIC_VECTOR (5 downto 0) := "011111";
constant ap_ST_st33_fsm_32 : STD_LOGIC_VECTOR (5 downto 0) := "100000";
constant ap_ST_st34_fsm_33 : STD_LOGIC_VECTOR (5 downto 0) := "100001";
constant ap_ST_st35_fsm_34 : STD_LOGIC_VECTOR (5 downto 0) := "100010";
constant ap_ST_st36_fsm_35 : STD_LOGIC_VECTOR (5 downto 0) := "100011";
constant ap_ST_st37_fsm_36 : STD_LOGIC_VECTOR (5 downto 0) := "100100";
constant ap_ST_st38_fsm_37 : STD_LOGIC_VECTOR (5 downto 0) := "100101";
constant ap_ST_st39_fsm_38 : STD_LOGIC_VECTOR (5 downto 0) := "100110";
constant ap_ST_st40_fsm_39 : STD_LOGIC_VECTOR (5 downto 0) := "100111";
constant ap_ST_st41_fsm_40 : STD_LOGIC_VECTOR (5 downto 0) := "101000";
constant ap_ST_st42_fsm_41 : STD_LOGIC_VECTOR (5 downto 0) := "101001";
constant ap_ST_st43_fsm_42 : STD_LOGIC_VECTOR (5 downto 0) := "101010";
constant ap_const_lv1_0 : STD_LOGIC_VECTOR (0 downto 0) := "0";
constant ap_const_lv16_0 : STD_LOGIC_VECTOR (15 downto 0) := "0000000000000000";
constant ap_const_lv64_0 : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000";
constant ap_const_lv1_1 : STD_LOGIC_VECTOR (0 downto 0) := "1";
constant ap_const_lv32_0 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000000";
constant ap_const_lv2_2 : STD_LOGIC_VECTOR (1 downto 0) := "10";
constant ap_const_lv32_1 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000001";
constant ap_const_lv16_1 : STD_LOGIC_VECTOR (15 downto 0) := "0000000000000001";
constant ap_const_lv64_1 : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000000000000000000000000000000000000000000000001";
constant ap_const_lv5_0 : STD_LOGIC_VECTOR (4 downto 0) := "00000";
constant ap_const_lv8_0 : STD_LOGIC_VECTOR (7 downto 0) := "00000000";
signal ap_CS_fsm : STD_LOGIC_VECTOR (5 downto 0) := "000000";
signal reg_377 : STD_LOGIC_VECTOR (31 downto 0);
signal current_buckets_0_reg_587 : STD_LOGIC_VECTOR (31 downto 0);
signal current_buckets_1_reg_592 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_14_cast_fu_389_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_14_cast_reg_602 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_s_fu_404_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_s_reg_607 : STD_LOGIC_VECTOR (0 downto 0);
signal i_1_fu_409_p2 : STD_LOGIC_VECTOR (15 downto 0);
signal i_1_reg_611 : STD_LOGIC_VECTOR (15 downto 0);
signal sample_addr_1_reg_616 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_421_p2 : STD_LOGIC_VECTOR (63 downto 0);
signal p_rec_reg_622 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_19_i_fu_427_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_19_i_reg_627 : STD_LOGIC_VECTOR (0 downto 0);
signal sym_reg_631 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_19_1_i_fu_433_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_19_1_i_reg_636 : STD_LOGIC_VECTOR (0 downto 0);
signal agg_result_bucket_index_0_lcssa4_i_cast_cast_fu_439_p1 : STD_LOGIC_VECTOR (1 downto 0);
signal grp_p_bsf32_hw_fu_371_ap_return : STD_LOGIC_VECTOR (4 downto 0);
signal j_bucket_index1_ph_cast_fu_443_p1 : STD_LOGIC_VECTOR (7 downto 0);
signal j_bit1_ph_cast_fu_447_p1 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_7_i_cast_fu_451_p1 : STD_LOGIC_VECTOR (13 downto 0);
signal tmp_7_i_cast_reg_660 : STD_LOGIC_VECTOR (13 downto 0);
signal state_fu_470_p2 : STD_LOGIC_VECTOR (5 downto 0);
signal state_reg_665 : STD_LOGIC_VECTOR (5 downto 0);
signal j_end_phi_fu_315_p4 : STD_LOGIC_VECTOR (0 downto 0);
signal j_bit_reg_680 : STD_LOGIC_VECTOR (7 downto 0);
signal j_bucket_index_reg_685 : STD_LOGIC_VECTOR (7 downto 0);
signal j_bucket_reg_690 : STD_LOGIC_VECTOR (31 downto 0);
signal p_s_reg_695 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_8_i_fu_505_p2 : STD_LOGIC_VECTOR (13 downto 0);
signal tmp_8_i_reg_700 : STD_LOGIC_VECTOR (13 downto 0);
signal next_buckets_0_1_fu_546_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal next_buckets_0_1_reg_718 : STD_LOGIC_VECTOR (31 downto 0);
signal next_buckets_1_1_fu_552_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_buckets_0_reg_728 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_buckets_1_reg_733 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_1_fu_576_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_1_reg_738 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_2_fu_582_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_2_reg_743 : STD_LOGIC_VECTOR (0 downto 0);
signal grp_bitset_next_fu_347_p_read : STD_LOGIC_VECTOR (31 downto 0);
signal grp_bitset_next_fu_347_r_bit : STD_LOGIC_VECTOR (7 downto 0);
signal grp_bitset_next_fu_347_r_bucket_index : STD_LOGIC_VECTOR (7 downto 0);
signal grp_bitset_next_fu_347_r_bucket : STD_LOGIC_VECTOR (31 downto 0);
signal grp_bitset_next_fu_347_ap_return_0 : STD_LOGIC_VECTOR (7 downto 0);
signal grp_bitset_next_fu_347_ap_return_1 : STD_LOGIC_VECTOR (7 downto 0);
signal grp_bitset_next_fu_347_ap_return_2 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_bitset_next_fu_347_ap_return_3 : STD_LOGIC_VECTOR (0 downto 0);
signal grp_bitset_next_fu_347_ap_ce : STD_LOGIC;
signal grp_nfa_get_initials_fu_359_ap_start : STD_LOGIC;
signal grp_nfa_get_initials_fu_359_ap_done : STD_LOGIC;
signal grp_nfa_get_initials_fu_359_ap_idle : STD_LOGIC;
signal grp_nfa_get_initials_fu_359_ap_ready : STD_LOGIC;
signal grp_nfa_get_initials_fu_359_nfa_initials_buckets_req_din : STD_LOGIC;
signal grp_nfa_get_initials_fu_359_nfa_initials_buckets_req_full_n : STD_LOGIC;
signal grp_nfa_get_initials_fu_359_nfa_initials_buckets_req_write : STD_LOGIC;
signal grp_nfa_get_initials_fu_359_nfa_initials_buckets_rsp_empty_n : STD_LOGIC;
signal grp_nfa_get_initials_fu_359_nfa_initials_buckets_rsp_read : STD_LOGIC;
signal grp_nfa_get_initials_fu_359_nfa_initials_buckets_address : STD_LOGIC_VECTOR (31 downto 0);
signal grp_nfa_get_initials_fu_359_nfa_initials_buckets_datain : STD_LOGIC_VECTOR (31 downto 0);
signal grp_nfa_get_initials_fu_359_nfa_initials_buckets_dataout : STD_LOGIC_VECTOR (31 downto 0);
signal grp_nfa_get_initials_fu_359_nfa_initials_buckets_size : STD_LOGIC_VECTOR (31 downto 0);
signal grp_nfa_get_initials_fu_359_ap_ce : STD_LOGIC;
signal grp_nfa_get_initials_fu_359_ap_return_0 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_nfa_get_initials_fu_359_ap_return_1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_nfa_get_finals_fu_365_ap_start : STD_LOGIC;
signal grp_nfa_get_finals_fu_365_ap_done : STD_LOGIC;
signal grp_nfa_get_finals_fu_365_ap_idle : STD_LOGIC;
signal grp_nfa_get_finals_fu_365_ap_ready : STD_LOGIC;
signal grp_nfa_get_finals_fu_365_nfa_finals_buckets_req_din : STD_LOGIC;
signal grp_nfa_get_finals_fu_365_nfa_finals_buckets_req_full_n : STD_LOGIC;
signal grp_nfa_get_finals_fu_365_nfa_finals_buckets_req_write : STD_LOGIC;
signal grp_nfa_get_finals_fu_365_nfa_finals_buckets_rsp_empty_n : STD_LOGIC;
signal grp_nfa_get_finals_fu_365_nfa_finals_buckets_rsp_read : STD_LOGIC;
signal grp_nfa_get_finals_fu_365_nfa_finals_buckets_address : STD_LOGIC_VECTOR (31 downto 0);
signal grp_nfa_get_finals_fu_365_nfa_finals_buckets_datain : STD_LOGIC_VECTOR (31 downto 0);
signal grp_nfa_get_finals_fu_365_nfa_finals_buckets_dataout : STD_LOGIC_VECTOR (31 downto 0);
signal grp_nfa_get_finals_fu_365_nfa_finals_buckets_size : STD_LOGIC_VECTOR (31 downto 0);
signal grp_nfa_get_finals_fu_365_ap_ce : STD_LOGIC;
signal grp_nfa_get_finals_fu_365_ap_return_0 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_nfa_get_finals_fu_365_ap_return_1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_p_bsf32_hw_fu_371_bus_r : STD_LOGIC_VECTOR (31 downto 0);
signal grp_p_bsf32_hw_fu_371_ap_ce : STD_LOGIC;
signal i_reg_138 : STD_LOGIC_VECTOR (15 downto 0);
signal any_phi_fu_327_p4 : STD_LOGIC_VECTOR (0 downto 0);
signal p_01_rec_reg_149 : STD_LOGIC_VECTOR (63 downto 0);
signal next_buckets_1_reg_161 : STD_LOGIC_VECTOR (31 downto 0);
signal next_buckets_0_reg_171 : STD_LOGIC_VECTOR (31 downto 0);
signal bus_assign_reg_181 : STD_LOGIC_VECTOR (31 downto 0);
signal agg_result_bucket_index_0_lcssa4_i_reg_193 : STD_LOGIC_VECTOR (0 downto 0);
signal j_bucket1_ph_reg_206 : STD_LOGIC_VECTOR (31 downto 0);
signal j_bucket_index1_ph_reg_219 : STD_LOGIC_VECTOR (1 downto 0);
signal j_bit1_ph_reg_230 : STD_LOGIC_VECTOR (4 downto 0);
signal j_end_ph_reg_241 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_buckets_1_3_reg_255 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_buckets_0_3_reg_268 : STD_LOGIC_VECTOR (31 downto 0);
signal j_bucket1_reg_281 : STD_LOGIC_VECTOR (31 downto 0);
signal j_bucket_index1_reg_292 : STD_LOGIC_VECTOR (7 downto 0);
signal j_bit1_reg_302 : STD_LOGIC_VECTOR (7 downto 0);
signal j_end_reg_312 : STD_LOGIC_VECTOR (0 downto 0);
signal any_reg_322 : STD_LOGIC_VECTOR (0 downto 0);
signal p_0_reg_335 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_NS_fsm : STD_LOGIC_VECTOR (5 downto 0);
signal grp_nfa_get_finals_fu_365_ap_start_ap_start_reg : STD_LOGIC := '0';
signal grp_fu_399_p2 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_4_i_cast_fu_517_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_9_i_cast_fu_535_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal grp_fu_399_p0 : STD_LOGIC_VECTOR (63 downto 0);
signal grp_fu_399_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal grp_fu_421_p0 : STD_LOGIC_VECTOR (63 downto 0);
signal grp_fu_421_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_31_fu_454_p1 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_i_fu_458_p3 : STD_LOGIC_VECTOR (5 downto 0);
signal tmp_32_fu_466_p1 : STD_LOGIC_VECTOR (5 downto 0);
signal grp_fu_483_p0 : STD_LOGIC_VECTOR (7 downto 0);
signal grp_fu_483_p1 : STD_LOGIC_VECTOR (5 downto 0);
signal grp_fu_483_p2 : STD_LOGIC_VECTOR (13 downto 0);
signal tmp_4_i_fu_510_p3 : STD_LOGIC_VECTOR (14 downto 0);
signal tmp_9_i_fu_528_p3 : STD_LOGIC_VECTOR (14 downto 0);
signal current_buckets_1_1_fu_571_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal current_buckets_0_1_fu_566_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_399_ce : STD_LOGIC;
signal grp_fu_421_ce : STD_LOGIC;
signal grp_fu_483_ce : STD_LOGIC;
signal ap_return_preg : STD_LOGIC_VECTOR (0 downto 0) := "0";
signal grp_fu_483_p00 : STD_LOGIC_VECTOR (13 downto 0);
signal grp_fu_483_p10 : STD_LOGIC_VECTOR (13 downto 0);
component bitset_next IS
port (
ap_clk : IN STD_LOGIC;
ap_rst : IN STD_LOGIC;
p_read : IN STD_LOGIC_VECTOR (31 downto 0);
r_bit : IN STD_LOGIC_VECTOR (7 downto 0);
r_bucket_index : IN STD_LOGIC_VECTOR (7 downto 0);
r_bucket : IN STD_LOGIC_VECTOR (31 downto 0);
ap_return_0 : OUT STD_LOGIC_VECTOR (7 downto 0);
ap_return_1 : OUT STD_LOGIC_VECTOR (7 downto 0);
ap_return_2 : OUT STD_LOGIC_VECTOR (31 downto 0);
ap_return_3 : OUT STD_LOGIC_VECTOR (0 downto 0);
ap_ce : IN STD_LOGIC );
end component;
component nfa_get_initials IS
port (
ap_clk : IN STD_LOGIC;
ap_rst : IN STD_LOGIC;
ap_start : IN STD_LOGIC;
ap_done : OUT STD_LOGIC;
ap_idle : OUT STD_LOGIC;
ap_ready : OUT STD_LOGIC;
nfa_initials_buckets_req_din : OUT STD_LOGIC;
nfa_initials_buckets_req_full_n : IN STD_LOGIC;
nfa_initials_buckets_req_write : OUT STD_LOGIC;
nfa_initials_buckets_rsp_empty_n : IN STD_LOGIC;
nfa_initials_buckets_rsp_read : OUT STD_LOGIC;
nfa_initials_buckets_address : OUT STD_LOGIC_VECTOR (31 downto 0);
nfa_initials_buckets_datain : IN STD_LOGIC_VECTOR (31 downto 0);
nfa_initials_buckets_dataout : OUT STD_LOGIC_VECTOR (31 downto 0);
nfa_initials_buckets_size : OUT STD_LOGIC_VECTOR (31 downto 0);
ap_ce : IN STD_LOGIC;
ap_return_0 : OUT STD_LOGIC_VECTOR (31 downto 0);
ap_return_1 : OUT STD_LOGIC_VECTOR (31 downto 0) );
end component;
component nfa_get_finals IS
port (
ap_clk : IN STD_LOGIC;
ap_rst : IN STD_LOGIC;
ap_start : IN STD_LOGIC;
ap_done : OUT STD_LOGIC;
ap_idle : OUT STD_LOGIC;
ap_ready : OUT STD_LOGIC;
nfa_finals_buckets_req_din : OUT STD_LOGIC;
nfa_finals_buckets_req_full_n : IN STD_LOGIC;
nfa_finals_buckets_req_write : OUT STD_LOGIC;
nfa_finals_buckets_rsp_empty_n : IN STD_LOGIC;
nfa_finals_buckets_rsp_read : OUT STD_LOGIC;
nfa_finals_buckets_address : OUT STD_LOGIC_VECTOR (31 downto 0);
nfa_finals_buckets_datain : IN STD_LOGIC_VECTOR (31 downto 0);
nfa_finals_buckets_dataout : OUT STD_LOGIC_VECTOR (31 downto 0);
nfa_finals_buckets_size : OUT STD_LOGIC_VECTOR (31 downto 0);
ap_ce : IN STD_LOGIC;
ap_return_0 : OUT STD_LOGIC_VECTOR (31 downto 0);
ap_return_1 : OUT STD_LOGIC_VECTOR (31 downto 0) );
end component;
component p_bsf32_hw IS
port (
ap_clk : IN STD_LOGIC;
ap_rst : IN STD_LOGIC;
bus_r : IN STD_LOGIC_VECTOR (31 downto 0);
ap_return : OUT STD_LOGIC_VECTOR (4 downto 0);
ap_ce : IN STD_LOGIC );
end component;
component nfa_accept_samples_generic_hw_add_64ns_64ns_64_2 IS
generic (
ID : INTEGER;
NUM_STAGE : INTEGER;
din0_WIDTH : INTEGER;
din1_WIDTH : INTEGER;
dout_WIDTH : INTEGER );
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
din0 : IN STD_LOGIC_VECTOR (63 downto 0);
din1 : IN STD_LOGIC_VECTOR (63 downto 0);
ce : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR (63 downto 0) );
end component;
component nfa_accept_samples_generic_hw_mul_8ns_6ns_14_4 IS
generic (
ID : INTEGER;
NUM_STAGE : INTEGER;
din0_WIDTH : INTEGER;
din1_WIDTH : INTEGER;
dout_WIDTH : INTEGER );
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
din0 : IN STD_LOGIC_VECTOR (7 downto 0);
din1 : IN STD_LOGIC_VECTOR (5 downto 0);
ce : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR (13 downto 0) );
end component;
begin
grp_bitset_next_fu_347 : component bitset_next
port map (
ap_clk => ap_clk,
ap_rst => ap_rst,
p_read => grp_bitset_next_fu_347_p_read,
r_bit => grp_bitset_next_fu_347_r_bit,
r_bucket_index => grp_bitset_next_fu_347_r_bucket_index,
r_bucket => grp_bitset_next_fu_347_r_bucket,
ap_return_0 => grp_bitset_next_fu_347_ap_return_0,
ap_return_1 => grp_bitset_next_fu_347_ap_return_1,
ap_return_2 => grp_bitset_next_fu_347_ap_return_2,
ap_return_3 => grp_bitset_next_fu_347_ap_return_3,
ap_ce => grp_bitset_next_fu_347_ap_ce);
grp_nfa_get_initials_fu_359 : component nfa_get_initials
port map (
ap_clk => ap_clk,
ap_rst => ap_rst,
ap_start => grp_nfa_get_initials_fu_359_ap_start,
ap_done => grp_nfa_get_initials_fu_359_ap_done,
ap_idle => grp_nfa_get_initials_fu_359_ap_idle,
ap_ready => grp_nfa_get_initials_fu_359_ap_ready,
nfa_initials_buckets_req_din => grp_nfa_get_initials_fu_359_nfa_initials_buckets_req_din,
nfa_initials_buckets_req_full_n => grp_nfa_get_initials_fu_359_nfa_initials_buckets_req_full_n,
nfa_initials_buckets_req_write => grp_nfa_get_initials_fu_359_nfa_initials_buckets_req_write,
nfa_initials_buckets_rsp_empty_n => grp_nfa_get_initials_fu_359_nfa_initials_buckets_rsp_empty_n,
nfa_initials_buckets_rsp_read => grp_nfa_get_initials_fu_359_nfa_initials_buckets_rsp_read,
nfa_initials_buckets_address => grp_nfa_get_initials_fu_359_nfa_initials_buckets_address,
nfa_initials_buckets_datain => grp_nfa_get_initials_fu_359_nfa_initials_buckets_datain,
nfa_initials_buckets_dataout => grp_nfa_get_initials_fu_359_nfa_initials_buckets_dataout,
nfa_initials_buckets_size => grp_nfa_get_initials_fu_359_nfa_initials_buckets_size,
ap_ce => grp_nfa_get_initials_fu_359_ap_ce,
ap_return_0 => grp_nfa_get_initials_fu_359_ap_return_0,
ap_return_1 => grp_nfa_get_initials_fu_359_ap_return_1);
grp_nfa_get_finals_fu_365 : component nfa_get_finals
port map (
ap_clk => ap_clk,
ap_rst => ap_rst,
ap_start => grp_nfa_get_finals_fu_365_ap_start,
ap_done => grp_nfa_get_finals_fu_365_ap_done,
ap_idle => grp_nfa_get_finals_fu_365_ap_idle,
ap_ready => grp_nfa_get_finals_fu_365_ap_ready,
nfa_finals_buckets_req_din => grp_nfa_get_finals_fu_365_nfa_finals_buckets_req_din,
nfa_finals_buckets_req_full_n => grp_nfa_get_finals_fu_365_nfa_finals_buckets_req_full_n,
nfa_finals_buckets_req_write => grp_nfa_get_finals_fu_365_nfa_finals_buckets_req_write,
nfa_finals_buckets_rsp_empty_n => grp_nfa_get_finals_fu_365_nfa_finals_buckets_rsp_empty_n,
nfa_finals_buckets_rsp_read => grp_nfa_get_finals_fu_365_nfa_finals_buckets_rsp_read,
nfa_finals_buckets_address => grp_nfa_get_finals_fu_365_nfa_finals_buckets_address,
nfa_finals_buckets_datain => grp_nfa_get_finals_fu_365_nfa_finals_buckets_datain,
nfa_finals_buckets_dataout => grp_nfa_get_finals_fu_365_nfa_finals_buckets_dataout,
nfa_finals_buckets_size => grp_nfa_get_finals_fu_365_nfa_finals_buckets_size,
ap_ce => grp_nfa_get_finals_fu_365_ap_ce,
ap_return_0 => grp_nfa_get_finals_fu_365_ap_return_0,
ap_return_1 => grp_nfa_get_finals_fu_365_ap_return_1);
grp_p_bsf32_hw_fu_371 : component p_bsf32_hw
port map (
ap_clk => ap_clk,
ap_rst => ap_rst,
bus_r => grp_p_bsf32_hw_fu_371_bus_r,
ap_return => grp_p_bsf32_hw_fu_371_ap_return,
ap_ce => grp_p_bsf32_hw_fu_371_ap_ce);
nfa_accept_samples_generic_hw_add_64ns_64ns_64_2_U15 : component nfa_accept_samples_generic_hw_add_64ns_64ns_64_2
generic map (
ID => 15,
NUM_STAGE => 2,
din0_WIDTH => 64,
din1_WIDTH => 64,
dout_WIDTH => 64)
port map (
clk => ap_clk,
reset => ap_rst,
din0 => grp_fu_399_p0,
din1 => grp_fu_399_p1,
ce => grp_fu_399_ce,
dout => grp_fu_399_p2);
nfa_accept_samples_generic_hw_add_64ns_64ns_64_2_U16 : component nfa_accept_samples_generic_hw_add_64ns_64ns_64_2
generic map (
ID => 16,
NUM_STAGE => 2,
din0_WIDTH => 64,
din1_WIDTH => 64,
dout_WIDTH => 64)
port map (
clk => ap_clk,
reset => ap_rst,
din0 => grp_fu_421_p0,
din1 => grp_fu_421_p1,
ce => grp_fu_421_ce,
dout => grp_fu_421_p2);
nfa_accept_samples_generic_hw_mul_8ns_6ns_14_4_U17 : component nfa_accept_samples_generic_hw_mul_8ns_6ns_14_4
generic map (
ID => 17,
NUM_STAGE => 4,
din0_WIDTH => 8,
din1_WIDTH => 6,
dout_WIDTH => 14)
port map (
clk => ap_clk,
reset => ap_rst,
din0 => grp_fu_483_p0,
din1 => grp_fu_483_p1,
ce => grp_fu_483_ce,
dout => grp_fu_483_p2);
-- the current state (ap_CS_fsm) of the state machine. --
ap_CS_fsm_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_CS_fsm <= ap_ST_st1_fsm_0;
else
ap_CS_fsm <= ap_NS_fsm;
end if;
end if;
end process;
-- ap_return_preg assign process. --
ap_return_preg_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_return_preg <= ap_const_lv1_0;
else
if ((ap_ST_st43_fsm_42 = ap_CS_fsm)) then
ap_return_preg <= p_0_reg_335;
end if;
end if;
end if;
end process;
-- grp_nfa_get_finals_fu_365_ap_start_ap_start_reg assign process. --
grp_nfa_get_finals_fu_365_ap_start_ap_start_reg_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
grp_nfa_get_finals_fu_365_ap_start_ap_start_reg <= ap_const_logic_0;
else
if (((ap_ST_st9_fsm_8 = ap_CS_fsm) and (ap_ST_st10_fsm_9 = ap_NS_fsm) and (tmp_s_fu_404_p2 = ap_const_lv1_0))) then
grp_nfa_get_finals_fu_365_ap_start_ap_start_reg <= ap_const_logic_1;
elsif ((ap_const_logic_1 = grp_nfa_get_finals_fu_365_ap_ready)) then
grp_nfa_get_finals_fu_365_ap_start_ap_start_reg <= ap_const_logic_0;
end if;
end if;
end if;
end process;
-- agg_result_bucket_index_0_lcssa4_i_reg_193 assign process. --
agg_result_bucket_index_0_lcssa4_i_reg_193_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ST_st17_fsm_16 = ap_CS_fsm) and (tmp_19_1_i_reg_636 = ap_const_lv1_0))) then
agg_result_bucket_index_0_lcssa4_i_reg_193 <= ap_const_lv1_1;
elsif (((ap_ST_st16_fsm_15 = ap_CS_fsm) and not((sample_rsp_empty_n = ap_const_logic_0)) and (tmp_19_i_reg_627 = ap_const_lv1_0))) then
agg_result_bucket_index_0_lcssa4_i_reg_193 <= ap_const_lv1_0;
end if;
end if;
end process;
-- any_reg_322 assign process. --
any_reg_322_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_ST_st20_fsm_19 = ap_CS_fsm)) then
any_reg_322 <= ap_const_lv1_0;
elsif ((ap_ST_st33_fsm_32 = ap_CS_fsm)) then
any_reg_322 <= ap_const_lv1_1;
end if;
end if;
end process;
-- bus_assign_reg_181 assign process. --
bus_assign_reg_181_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ST_st17_fsm_16 = ap_CS_fsm) and (tmp_19_1_i_reg_636 = ap_const_lv1_0))) then
bus_assign_reg_181 <= next_buckets_1_reg_161;
elsif (((ap_ST_st16_fsm_15 = ap_CS_fsm) and not((sample_rsp_empty_n = ap_const_logic_0)) and (tmp_19_i_reg_627 = ap_const_lv1_0))) then
bus_assign_reg_181 <= next_buckets_0_reg_171;
end if;
end if;
end process;
-- i_reg_138 assign process. --
i_reg_138_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ST_st21_fsm_20 = ap_CS_fsm) and not((ap_const_lv1_0 = j_end_phi_fu_315_p4)) and not((ap_const_lv1_0 = any_phi_fu_327_p4)))) then
i_reg_138 <= i_1_reg_611;
elsif ((ap_ST_st8_fsm_7 = ap_CS_fsm)) then
i_reg_138 <= ap_const_lv16_0;
end if;
end if;
end process;
-- j_bit1_reg_302 assign process. --
j_bit1_reg_302_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_ST_st20_fsm_19 = ap_CS_fsm)) then
j_bit1_reg_302 <= j_bit1_ph_cast_fu_447_p1;
elsif ((ap_ST_st33_fsm_32 = ap_CS_fsm)) then
j_bit1_reg_302 <= j_bit_reg_680;
end if;
end if;
end process;
-- j_bucket1_ph_reg_206 assign process. --
j_bucket1_ph_reg_206_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_ST_st19_fsm_18 = ap_CS_fsm)) then
j_bucket1_ph_reg_206 <= bus_assign_reg_181;
elsif (((ap_ST_st17_fsm_16 = ap_CS_fsm) and not((tmp_19_1_i_reg_636 = ap_const_lv1_0)))) then
j_bucket1_ph_reg_206 <= ap_const_lv32_0;
end if;
end if;
end process;
-- j_bucket1_reg_281 assign process. --
j_bucket1_reg_281_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_ST_st20_fsm_19 = ap_CS_fsm)) then
j_bucket1_reg_281 <= j_bucket1_ph_reg_206;
elsif ((ap_ST_st33_fsm_32 = ap_CS_fsm)) then
j_bucket1_reg_281 <= j_bucket_reg_690;
end if;
end if;
end process;
-- j_bucket_index1_ph_reg_219 assign process. --
j_bucket_index1_ph_reg_219_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_ST_st19_fsm_18 = ap_CS_fsm)) then
j_bucket_index1_ph_reg_219 <= agg_result_bucket_index_0_lcssa4_i_cast_cast_fu_439_p1;
elsif (((ap_ST_st17_fsm_16 = ap_CS_fsm) and not((tmp_19_1_i_reg_636 = ap_const_lv1_0)))) then
j_bucket_index1_ph_reg_219 <= ap_const_lv2_2;
end if;
end if;
end process;
-- j_bucket_index1_reg_292 assign process. --
j_bucket_index1_reg_292_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_ST_st20_fsm_19 = ap_CS_fsm)) then
j_bucket_index1_reg_292 <= j_bucket_index1_ph_cast_fu_443_p1;
elsif ((ap_ST_st33_fsm_32 = ap_CS_fsm)) then
j_bucket_index1_reg_292 <= j_bucket_index_reg_685;
end if;
end if;
end process;
-- j_end_ph_reg_241 assign process. --
j_end_ph_reg_241_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_ST_st19_fsm_18 = ap_CS_fsm)) then
j_end_ph_reg_241 <= ap_const_lv1_0;
elsif (((ap_ST_st17_fsm_16 = ap_CS_fsm) and not((tmp_19_1_i_reg_636 = ap_const_lv1_0)))) then
j_end_ph_reg_241 <= ap_const_lv1_1;
end if;
end if;
end process;
-- j_end_reg_312 assign process. --
j_end_reg_312_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_ST_st20_fsm_19 = ap_CS_fsm)) then
j_end_reg_312 <= j_end_ph_reg_241;
elsif ((ap_ST_st33_fsm_32 = ap_CS_fsm)) then
j_end_reg_312 <= p_s_reg_695;
end if;
end if;
end process;
-- next_buckets_0_reg_171 assign process. --
next_buckets_0_reg_171_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ST_st21_fsm_20 = ap_CS_fsm) and not((ap_const_lv1_0 = j_end_phi_fu_315_p4)) and not((ap_const_lv1_0 = any_phi_fu_327_p4)))) then
next_buckets_0_reg_171 <= tmp_buckets_0_3_reg_268;
elsif ((ap_ST_st8_fsm_7 = ap_CS_fsm)) then
next_buckets_0_reg_171 <= current_buckets_0_reg_587;
end if;
end if;
end process;
-- next_buckets_1_reg_161 assign process. --
next_buckets_1_reg_161_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ST_st21_fsm_20 = ap_CS_fsm) and not((ap_const_lv1_0 = j_end_phi_fu_315_p4)) and not((ap_const_lv1_0 = any_phi_fu_327_p4)))) then
next_buckets_1_reg_161 <= tmp_buckets_1_3_reg_255;
elsif ((ap_ST_st8_fsm_7 = ap_CS_fsm)) then
next_buckets_1_reg_161 <= current_buckets_1_reg_592;
end if;
end if;
end process;
-- p_01_rec_reg_149 assign process. --
p_01_rec_reg_149_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ST_st21_fsm_20 = ap_CS_fsm) and not((ap_const_lv1_0 = j_end_phi_fu_315_p4)) and not((ap_const_lv1_0 = any_phi_fu_327_p4)))) then
p_01_rec_reg_149 <= p_rec_reg_622;
elsif ((ap_ST_st8_fsm_7 = ap_CS_fsm)) then
p_01_rec_reg_149 <= ap_const_lv64_0;
end if;
end if;
end process;
-- p_0_reg_335 assign process. --
p_0_reg_335_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ST_st21_fsm_20 = ap_CS_fsm) and not((ap_const_lv1_0 = j_end_phi_fu_315_p4)) and (ap_const_lv1_0 = any_phi_fu_327_p4))) then
p_0_reg_335 <= ap_const_lv1_0;
elsif ((ap_ST_st42_fsm_41 = ap_CS_fsm)) then
p_0_reg_335 <= tmp_2_reg_743;
end if;
end if;
end process;
-- tmp_buckets_0_3_reg_268 assign process. --
tmp_buckets_0_3_reg_268_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_ST_st20_fsm_19 = ap_CS_fsm)) then
tmp_buckets_0_3_reg_268 <= ap_const_lv32_0;
elsif ((ap_ST_st33_fsm_32 = ap_CS_fsm)) then
tmp_buckets_0_3_reg_268 <= next_buckets_0_1_reg_718;
end if;
end if;
end process;
-- tmp_buckets_1_3_reg_255 assign process. --
tmp_buckets_1_3_reg_255_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_ST_st20_fsm_19 = ap_CS_fsm)) then
tmp_buckets_1_3_reg_255 <= ap_const_lv32_0;
elsif ((ap_ST_st33_fsm_32 = ap_CS_fsm)) then
tmp_buckets_1_3_reg_255 <= next_buckets_1_1_fu_552_p2;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_ST_st7_fsm_6 = ap_CS_fsm)) then
current_buckets_0_reg_587 <= grp_nfa_get_initials_fu_359_ap_return_0;
current_buckets_1_reg_592 <= grp_nfa_get_initials_fu_359_ap_return_1;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_ST_st9_fsm_8 = ap_CS_fsm)) then
i_1_reg_611 <= i_1_fu_409_p2;
tmp_s_reg_607 <= tmp_s_fu_404_p2;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_ST_st19_fsm_18 = ap_CS_fsm)) then
j_bit1_ph_reg_230 <= grp_p_bsf32_hw_fu_371_ap_return;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_ST_st24_fsm_23 = ap_CS_fsm)) then
j_bit_reg_680 <= grp_bitset_next_fu_347_ap_return_0;
j_bucket_index_reg_685 <= grp_bitset_next_fu_347_ap_return_1;
j_bucket_reg_690 <= grp_bitset_next_fu_347_ap_return_2;
p_s_reg_695 <= grp_bitset_next_fu_347_ap_return_3;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((not((nfa_forward_buckets_rsp_empty_n = ap_const_logic_0)) and (ap_ST_st32_fsm_31 = ap_CS_fsm))) then
next_buckets_0_1_reg_718 <= next_buckets_0_1_fu_546_p2;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_ST_st11_fsm_10 = ap_CS_fsm)) then
p_rec_reg_622 <= grp_fu_421_p2;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((((ap_ST_st31_fsm_30 = ap_CS_fsm) and not((nfa_forward_buckets_rsp_empty_n = ap_const_logic_0))) or (not((nfa_forward_buckets_rsp_empty_n = ap_const_logic_0)) and (ap_ST_st32_fsm_31 = ap_CS_fsm)))) then
reg_377 <= nfa_forward_buckets_datain;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_ST_st10_fsm_9 = ap_CS_fsm)) then
sample_addr_1_reg_616 <= grp_fu_399_p2(32 - 1 downto 0);
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ST_st21_fsm_20 = ap_CS_fsm) and (ap_const_lv1_0 = j_end_phi_fu_315_p4))) then
state_reg_665 <= state_fu_470_p2;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ST_st16_fsm_15 = ap_CS_fsm) and not((sample_rsp_empty_n = ap_const_logic_0)))) then
sym_reg_631 <= sample_datain;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_ST_st8_fsm_7 = ap_CS_fsm)) then
tmp_14_cast_reg_602(0) <= tmp_14_cast_fu_389_p1(0);
tmp_14_cast_reg_602(1) <= tmp_14_cast_fu_389_p1(1);
tmp_14_cast_reg_602(2) <= tmp_14_cast_fu_389_p1(2);
tmp_14_cast_reg_602(3) <= tmp_14_cast_fu_389_p1(3);
tmp_14_cast_reg_602(4) <= tmp_14_cast_fu_389_p1(4);
tmp_14_cast_reg_602(5) <= tmp_14_cast_fu_389_p1(5);
tmp_14_cast_reg_602(6) <= tmp_14_cast_fu_389_p1(6);
tmp_14_cast_reg_602(7) <= tmp_14_cast_fu_389_p1(7);
tmp_14_cast_reg_602(8) <= tmp_14_cast_fu_389_p1(8);
tmp_14_cast_reg_602(9) <= tmp_14_cast_fu_389_p1(9);
tmp_14_cast_reg_602(10) <= tmp_14_cast_fu_389_p1(10);
tmp_14_cast_reg_602(11) <= tmp_14_cast_fu_389_p1(11);
tmp_14_cast_reg_602(12) <= tmp_14_cast_fu_389_p1(12);
tmp_14_cast_reg_602(13) <= tmp_14_cast_fu_389_p1(13);
tmp_14_cast_reg_602(14) <= tmp_14_cast_fu_389_p1(14);
tmp_14_cast_reg_602(15) <= tmp_14_cast_fu_389_p1(15);
tmp_14_cast_reg_602(16) <= tmp_14_cast_fu_389_p1(16);
tmp_14_cast_reg_602(17) <= tmp_14_cast_fu_389_p1(17);
tmp_14_cast_reg_602(18) <= tmp_14_cast_fu_389_p1(18);
tmp_14_cast_reg_602(19) <= tmp_14_cast_fu_389_p1(19);
tmp_14_cast_reg_602(20) <= tmp_14_cast_fu_389_p1(20);
tmp_14_cast_reg_602(21) <= tmp_14_cast_fu_389_p1(21);
tmp_14_cast_reg_602(22) <= tmp_14_cast_fu_389_p1(22);
tmp_14_cast_reg_602(23) <= tmp_14_cast_fu_389_p1(23);
tmp_14_cast_reg_602(24) <= tmp_14_cast_fu_389_p1(24);
tmp_14_cast_reg_602(25) <= tmp_14_cast_fu_389_p1(25);
tmp_14_cast_reg_602(26) <= tmp_14_cast_fu_389_p1(26);
tmp_14_cast_reg_602(27) <= tmp_14_cast_fu_389_p1(27);
tmp_14_cast_reg_602(28) <= tmp_14_cast_fu_389_p1(28);
tmp_14_cast_reg_602(29) <= tmp_14_cast_fu_389_p1(29);
tmp_14_cast_reg_602(30) <= tmp_14_cast_fu_389_p1(30);
tmp_14_cast_reg_602(31) <= tmp_14_cast_fu_389_p1(31);
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ST_st16_fsm_15 = ap_CS_fsm) and not((sample_rsp_empty_n = ap_const_logic_0)) and not((tmp_19_i_reg_627 = ap_const_lv1_0)))) then
tmp_19_1_i_reg_636 <= tmp_19_1_i_fu_433_p2;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_ST_st15_fsm_14 = ap_CS_fsm)) then
tmp_19_i_reg_627 <= tmp_19_i_fu_427_p2;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_ST_st40_fsm_39 = ap_CS_fsm)) then
tmp_1_reg_738 <= tmp_1_fu_576_p2;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_ST_st41_fsm_40 = ap_CS_fsm)) then
tmp_2_reg_743 <= tmp_2_fu_582_p2;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_ST_st20_fsm_19 = ap_CS_fsm)) then
tmp_7_i_cast_reg_660(0) <= tmp_7_i_cast_fu_451_p1(0);
tmp_7_i_cast_reg_660(1) <= tmp_7_i_cast_fu_451_p1(1);
tmp_7_i_cast_reg_660(2) <= tmp_7_i_cast_fu_451_p1(2);
tmp_7_i_cast_reg_660(3) <= tmp_7_i_cast_fu_451_p1(3);
tmp_7_i_cast_reg_660(4) <= tmp_7_i_cast_fu_451_p1(4);
tmp_7_i_cast_reg_660(5) <= tmp_7_i_cast_fu_451_p1(5);
tmp_7_i_cast_reg_660(6) <= tmp_7_i_cast_fu_451_p1(6);
tmp_7_i_cast_reg_660(7) <= tmp_7_i_cast_fu_451_p1(7);
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_ST_st25_fsm_24 = ap_CS_fsm)) then
tmp_8_i_reg_700 <= tmp_8_i_fu_505_p2;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_ST_st39_fsm_38 = ap_CS_fsm)) then
tmp_buckets_0_reg_728 <= grp_nfa_get_finals_fu_365_ap_return_0;
tmp_buckets_1_reg_733 <= grp_nfa_get_finals_fu_365_ap_return_1;
end if;
end if;
end process;
tmp_14_cast_reg_602(63 downto 32) <= "00000000000000000000000000000000";
tmp_7_i_cast_reg_660(13 downto 8) <= "000000";
-- the next state (ap_NS_fsm) of the state machine. --
ap_NS_fsm_assign_proc : process (ap_start , ap_CS_fsm , nfa_forward_buckets_rsp_empty_n , sample_rsp_empty_n , tmp_s_reg_607 , tmp_19_i_reg_627 , tmp_19_1_i_reg_636 , j_end_phi_fu_315_p4 , any_phi_fu_327_p4)
begin
case ap_CS_fsm is
when ap_ST_st1_fsm_0 =>
if (not((ap_start = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st2_fsm_1;
else
ap_NS_fsm <= ap_ST_st1_fsm_0;
end if;
when ap_ST_st2_fsm_1 =>
ap_NS_fsm <= ap_ST_st3_fsm_2;
when ap_ST_st3_fsm_2 =>
ap_NS_fsm <= ap_ST_st4_fsm_3;
when ap_ST_st4_fsm_3 =>
ap_NS_fsm <= ap_ST_st5_fsm_4;
when ap_ST_st5_fsm_4 =>
ap_NS_fsm <= ap_ST_st6_fsm_5;
when ap_ST_st6_fsm_5 =>
ap_NS_fsm <= ap_ST_st7_fsm_6;
when ap_ST_st7_fsm_6 =>
ap_NS_fsm <= ap_ST_st8_fsm_7;
when ap_ST_st8_fsm_7 =>
ap_NS_fsm <= ap_ST_st9_fsm_8;
when ap_ST_st9_fsm_8 =>
ap_NS_fsm <= ap_ST_st10_fsm_9;
when ap_ST_st10_fsm_9 =>
if ((tmp_s_reg_607 = ap_const_lv1_0)) then
ap_NS_fsm <= ap_ST_st34_fsm_33;
else
ap_NS_fsm <= ap_ST_st11_fsm_10;
end if;
when ap_ST_st11_fsm_10 =>
ap_NS_fsm <= ap_ST_st12_fsm_11;
when ap_ST_st12_fsm_11 =>
ap_NS_fsm <= ap_ST_st13_fsm_12;
when ap_ST_st13_fsm_12 =>
ap_NS_fsm <= ap_ST_st14_fsm_13;
when ap_ST_st14_fsm_13 =>
ap_NS_fsm <= ap_ST_st15_fsm_14;
when ap_ST_st15_fsm_14 =>
ap_NS_fsm <= ap_ST_st16_fsm_15;
when ap_ST_st16_fsm_15 =>
if ((not((sample_rsp_empty_n = ap_const_logic_0)) and (tmp_19_i_reg_627 = ap_const_lv1_0))) then
ap_NS_fsm <= ap_ST_st18_fsm_17;
elsif ((not((sample_rsp_empty_n = ap_const_logic_0)) and not((tmp_19_i_reg_627 = ap_const_lv1_0)))) then
ap_NS_fsm <= ap_ST_st17_fsm_16;
else
ap_NS_fsm <= ap_ST_st16_fsm_15;
end if;
when ap_ST_st17_fsm_16 =>
if (not((tmp_19_1_i_reg_636 = ap_const_lv1_0))) then
ap_NS_fsm <= ap_ST_st20_fsm_19;
else
ap_NS_fsm <= ap_ST_st18_fsm_17;
end if;
when ap_ST_st18_fsm_17 =>
ap_NS_fsm <= ap_ST_st19_fsm_18;
when ap_ST_st19_fsm_18 =>
ap_NS_fsm <= ap_ST_st20_fsm_19;
when ap_ST_st20_fsm_19 =>
ap_NS_fsm <= ap_ST_st21_fsm_20;
when ap_ST_st21_fsm_20 =>
if ((not((ap_const_lv1_0 = j_end_phi_fu_315_p4)) and not((ap_const_lv1_0 = any_phi_fu_327_p4)))) then
ap_NS_fsm <= ap_ST_st9_fsm_8;
elsif ((not((ap_const_lv1_0 = j_end_phi_fu_315_p4)) and (ap_const_lv1_0 = any_phi_fu_327_p4))) then
ap_NS_fsm <= ap_ST_st43_fsm_42;
else
ap_NS_fsm <= ap_ST_st22_fsm_21;
end if;
when ap_ST_st22_fsm_21 =>
ap_NS_fsm <= ap_ST_st23_fsm_22;
when ap_ST_st23_fsm_22 =>
ap_NS_fsm <= ap_ST_st24_fsm_23;
when ap_ST_st24_fsm_23 =>
ap_NS_fsm <= ap_ST_st25_fsm_24;
when ap_ST_st25_fsm_24 =>
ap_NS_fsm <= ap_ST_st26_fsm_25;
when ap_ST_st26_fsm_25 =>
ap_NS_fsm <= ap_ST_st27_fsm_26;
when ap_ST_st27_fsm_26 =>
ap_NS_fsm <= ap_ST_st28_fsm_27;
when ap_ST_st28_fsm_27 =>
ap_NS_fsm <= ap_ST_st29_fsm_28;
when ap_ST_st29_fsm_28 =>
ap_NS_fsm <= ap_ST_st30_fsm_29;
when ap_ST_st30_fsm_29 =>
ap_NS_fsm <= ap_ST_st31_fsm_30;
when ap_ST_st31_fsm_30 =>
if (not((nfa_forward_buckets_rsp_empty_n = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st32_fsm_31;
else
ap_NS_fsm <= ap_ST_st31_fsm_30;
end if;
when ap_ST_st32_fsm_31 =>
if (not((nfa_forward_buckets_rsp_empty_n = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st33_fsm_32;
else
ap_NS_fsm <= ap_ST_st32_fsm_31;
end if;
when ap_ST_st33_fsm_32 =>
ap_NS_fsm <= ap_ST_st21_fsm_20;
when ap_ST_st34_fsm_33 =>
ap_NS_fsm <= ap_ST_st35_fsm_34;
when ap_ST_st35_fsm_34 =>
ap_NS_fsm <= ap_ST_st36_fsm_35;
when ap_ST_st36_fsm_35 =>
ap_NS_fsm <= ap_ST_st37_fsm_36;
when ap_ST_st37_fsm_36 =>
ap_NS_fsm <= ap_ST_st38_fsm_37;
when ap_ST_st38_fsm_37 =>
ap_NS_fsm <= ap_ST_st39_fsm_38;
when ap_ST_st39_fsm_38 =>
ap_NS_fsm <= ap_ST_st40_fsm_39;
when ap_ST_st40_fsm_39 =>
ap_NS_fsm <= ap_ST_st41_fsm_40;
when ap_ST_st41_fsm_40 =>
ap_NS_fsm <= ap_ST_st42_fsm_41;
when ap_ST_st42_fsm_41 =>
ap_NS_fsm <= ap_ST_st43_fsm_42;
when ap_ST_st43_fsm_42 =>
ap_NS_fsm <= ap_ST_st1_fsm_0;
when others =>
ap_NS_fsm <= "XXXXXX";
end case;
end process;
agg_result_bucket_index_0_lcssa4_i_cast_cast_fu_439_p1 <= std_logic_vector(resize(unsigned(agg_result_bucket_index_0_lcssa4_i_reg_193),2));
any_phi_fu_327_p4 <= any_reg_322;
-- ap_done assign process. --
ap_done_assign_proc : process(ap_start, ap_CS_fsm)
begin
if (((not((ap_const_logic_1 = ap_start)) and (ap_ST_st1_fsm_0 = ap_CS_fsm)) or (ap_ST_st43_fsm_42 = ap_CS_fsm))) then
ap_done <= ap_const_logic_1;
else
ap_done <= ap_const_logic_0;
end if;
end process;
-- ap_idle assign process. --
ap_idle_assign_proc : process(ap_start, ap_CS_fsm)
begin
if ((not((ap_const_logic_1 = ap_start)) and (ap_ST_st1_fsm_0 = ap_CS_fsm))) then
ap_idle <= ap_const_logic_1;
else
ap_idle <= ap_const_logic_0;
end if;
end process;
-- ap_ready assign process. --
ap_ready_assign_proc : process(ap_CS_fsm)
begin
if ((ap_ST_st43_fsm_42 = ap_CS_fsm)) then
ap_ready <= ap_const_logic_1;
else
ap_ready <= ap_const_logic_0;
end if;
end process;
-- ap_return assign process. --
ap_return_assign_proc : process(ap_CS_fsm, p_0_reg_335, ap_return_preg)
begin
if ((ap_ST_st43_fsm_42 = ap_CS_fsm)) then
ap_return <= p_0_reg_335;
else
ap_return <= ap_return_preg;
end if;
end process;
current_buckets_0_1_fu_566_p2 <= (next_buckets_0_reg_171 and tmp_buckets_0_reg_728);
current_buckets_1_1_fu_571_p2 <= (next_buckets_1_reg_161 and tmp_buckets_1_reg_733);
-- grp_bitset_next_fu_347_ap_ce assign process. --
grp_bitset_next_fu_347_ap_ce_assign_proc : process(ap_CS_fsm, j_end_phi_fu_315_p4)
begin
if ((((ap_ST_st21_fsm_20 = ap_CS_fsm) and (ap_const_lv1_0 = j_end_phi_fu_315_p4)) or (ap_ST_st22_fsm_21 = ap_CS_fsm) or (ap_ST_st24_fsm_23 = ap_CS_fsm) or (ap_ST_st23_fsm_22 = ap_CS_fsm))) then
grp_bitset_next_fu_347_ap_ce <= ap_const_logic_1;
else
grp_bitset_next_fu_347_ap_ce <= ap_const_logic_0;
end if;
end process;
grp_bitset_next_fu_347_p_read <= next_buckets_1_reg_161;
grp_bitset_next_fu_347_r_bit <= j_bit1_reg_302;
grp_bitset_next_fu_347_r_bucket <= j_bucket1_reg_281;
grp_bitset_next_fu_347_r_bucket_index <= j_bucket_index1_reg_292;
grp_fu_399_ce <= ap_const_logic_1;
grp_fu_399_p0 <= p_01_rec_reg_149;
grp_fu_399_p1 <= tmp_14_cast_reg_602;
grp_fu_421_ce <= ap_const_logic_1;
grp_fu_421_p0 <= p_01_rec_reg_149;
grp_fu_421_p1 <= ap_const_lv64_1;
grp_fu_483_ce <= ap_const_logic_1;
grp_fu_483_p0 <= grp_fu_483_p00(8 - 1 downto 0);
grp_fu_483_p00 <= std_logic_vector(resize(unsigned(nfa_symbols),14));
grp_fu_483_p1 <= grp_fu_483_p10(6 - 1 downto 0);
grp_fu_483_p10 <= std_logic_vector(resize(unsigned(state_reg_665),14));
grp_nfa_get_finals_fu_365_ap_ce <= ap_const_logic_1;
grp_nfa_get_finals_fu_365_ap_start <= grp_nfa_get_finals_fu_365_ap_start_ap_start_reg;
grp_nfa_get_finals_fu_365_nfa_finals_buckets_datain <= nfa_finals_buckets_datain;
grp_nfa_get_finals_fu_365_nfa_finals_buckets_req_full_n <= nfa_finals_buckets_req_full_n;
grp_nfa_get_finals_fu_365_nfa_finals_buckets_rsp_empty_n <= nfa_finals_buckets_rsp_empty_n;
grp_nfa_get_initials_fu_359_ap_ce <= ap_const_logic_1;
-- grp_nfa_get_initials_fu_359_ap_start assign process. --
grp_nfa_get_initials_fu_359_ap_start_assign_proc : process(ap_start, ap_CS_fsm)
begin
if (((ap_ST_st1_fsm_0 = ap_CS_fsm) and not((ap_start = ap_const_logic_0)))) then
grp_nfa_get_initials_fu_359_ap_start <= ap_const_logic_1;
else
grp_nfa_get_initials_fu_359_ap_start <= ap_const_logic_0;
end if;
end process;
grp_nfa_get_initials_fu_359_nfa_initials_buckets_datain <= nfa_initials_buckets_datain;
grp_nfa_get_initials_fu_359_nfa_initials_buckets_req_full_n <= nfa_initials_buckets_req_full_n;
grp_nfa_get_initials_fu_359_nfa_initials_buckets_rsp_empty_n <= nfa_initials_buckets_rsp_empty_n;
-- grp_p_bsf32_hw_fu_371_ap_ce assign process. --
grp_p_bsf32_hw_fu_371_ap_ce_assign_proc : process(ap_CS_fsm)
begin
if (((ap_ST_st19_fsm_18 = ap_CS_fsm) or (ap_ST_st18_fsm_17 = ap_CS_fsm))) then
grp_p_bsf32_hw_fu_371_ap_ce <= ap_const_logic_1;
else
grp_p_bsf32_hw_fu_371_ap_ce <= ap_const_logic_0;
end if;
end process;
grp_p_bsf32_hw_fu_371_bus_r <= bus_assign_reg_181;
i_1_fu_409_p2 <= std_logic_vector(unsigned(i_reg_138) + unsigned(ap_const_lv16_1));
j_bit1_ph_cast_fu_447_p1 <= std_logic_vector(resize(unsigned(j_bit1_ph_reg_230),8));
j_bucket_index1_ph_cast_fu_443_p1 <= std_logic_vector(resize(unsigned(j_bucket_index1_ph_reg_219),8));
j_end_phi_fu_315_p4 <= j_end_reg_312;
next_buckets_0_1_fu_546_p2 <= (tmp_buckets_0_3_reg_268 or reg_377);
next_buckets_1_1_fu_552_p2 <= (tmp_buckets_1_3_reg_255 or reg_377);
nfa_finals_buckets_address <= grp_nfa_get_finals_fu_365_nfa_finals_buckets_address;
nfa_finals_buckets_dataout <= grp_nfa_get_finals_fu_365_nfa_finals_buckets_dataout;
nfa_finals_buckets_req_din <= grp_nfa_get_finals_fu_365_nfa_finals_buckets_req_din;
nfa_finals_buckets_req_write <= grp_nfa_get_finals_fu_365_nfa_finals_buckets_req_write;
nfa_finals_buckets_rsp_read <= grp_nfa_get_finals_fu_365_nfa_finals_buckets_rsp_read;
nfa_finals_buckets_size <= grp_nfa_get_finals_fu_365_nfa_finals_buckets_size;
-- nfa_forward_buckets_address assign process. --
nfa_forward_buckets_address_assign_proc : process(ap_CS_fsm, tmp_4_i_cast_fu_517_p1, tmp_9_i_cast_fu_535_p1)
begin
if ((ap_ST_st27_fsm_26 = ap_CS_fsm)) then
nfa_forward_buckets_address <= tmp_9_i_cast_fu_535_p1(32 - 1 downto 0);
elsif ((ap_ST_st26_fsm_25 = ap_CS_fsm)) then
nfa_forward_buckets_address <= tmp_4_i_cast_fu_517_p1(32 - 1 downto 0);
else
nfa_forward_buckets_address <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
nfa_forward_buckets_dataout <= ap_const_lv32_0;
nfa_forward_buckets_req_din <= ap_const_logic_0;
-- nfa_forward_buckets_req_write assign process. --
nfa_forward_buckets_req_write_assign_proc : process(ap_CS_fsm)
begin
if (((ap_ST_st26_fsm_25 = ap_CS_fsm) or (ap_ST_st27_fsm_26 = ap_CS_fsm))) then
nfa_forward_buckets_req_write <= ap_const_logic_1;
else
nfa_forward_buckets_req_write <= ap_const_logic_0;
end if;
end process;
-- nfa_forward_buckets_rsp_read assign process. --
nfa_forward_buckets_rsp_read_assign_proc : process(ap_CS_fsm, nfa_forward_buckets_rsp_empty_n)
begin
if ((((ap_ST_st31_fsm_30 = ap_CS_fsm) and not((nfa_forward_buckets_rsp_empty_n = ap_const_logic_0))) or (not((nfa_forward_buckets_rsp_empty_n = ap_const_logic_0)) and (ap_ST_st32_fsm_31 = ap_CS_fsm)))) then
nfa_forward_buckets_rsp_read <= ap_const_logic_1;
else
nfa_forward_buckets_rsp_read <= ap_const_logic_0;
end if;
end process;
nfa_forward_buckets_size <= ap_const_lv32_1;
nfa_initials_buckets_address <= grp_nfa_get_initials_fu_359_nfa_initials_buckets_address;
nfa_initials_buckets_dataout <= grp_nfa_get_initials_fu_359_nfa_initials_buckets_dataout;
nfa_initials_buckets_req_din <= grp_nfa_get_initials_fu_359_nfa_initials_buckets_req_din;
nfa_initials_buckets_req_write <= grp_nfa_get_initials_fu_359_nfa_initials_buckets_req_write;
nfa_initials_buckets_rsp_read <= grp_nfa_get_initials_fu_359_nfa_initials_buckets_rsp_read;
nfa_initials_buckets_size <= grp_nfa_get_initials_fu_359_nfa_initials_buckets_size;
sample_address <= sample_addr_1_reg_616;
sample_dataout <= ap_const_lv8_0;
sample_req_din <= ap_const_logic_0;
-- sample_req_write assign process. --
sample_req_write_assign_proc : process(ap_CS_fsm)
begin
if ((ap_ST_st11_fsm_10 = ap_CS_fsm)) then
sample_req_write <= ap_const_logic_1;
else
sample_req_write <= ap_const_logic_0;
end if;
end process;
-- sample_rsp_read assign process. --
sample_rsp_read_assign_proc : process(ap_CS_fsm, sample_rsp_empty_n)
begin
if (((ap_ST_st16_fsm_15 = ap_CS_fsm) and not((sample_rsp_empty_n = ap_const_logic_0)))) then
sample_rsp_read <= ap_const_logic_1;
else
sample_rsp_read <= ap_const_logic_0;
end if;
end process;
sample_size <= ap_const_lv32_1;
state_fu_470_p2 <= std_logic_vector(unsigned(tmp_i_fu_458_p3) + unsigned(tmp_32_fu_466_p1));
tmp_14_cast_fu_389_p1 <= std_logic_vector(resize(unsigned(tmp_14),64));
tmp_19_1_i_fu_433_p2 <= "1" when (next_buckets_1_reg_161 = ap_const_lv32_0) else "0";
tmp_19_i_fu_427_p2 <= "1" when (next_buckets_0_reg_171 = ap_const_lv32_0) else "0";
tmp_1_fu_576_p2 <= (current_buckets_1_1_fu_571_p2 or current_buckets_0_1_fu_566_p2);
tmp_2_fu_582_p2 <= "0" when (tmp_1_reg_738 = ap_const_lv32_0) else "1";
tmp_31_fu_454_p1 <= j_bucket_index1_reg_292(1 - 1 downto 0);
tmp_32_fu_466_p1 <= j_bit1_reg_302(6 - 1 downto 0);
tmp_4_i_cast_fu_517_p1 <= std_logic_vector(resize(unsigned(tmp_4_i_fu_510_p3),64));
tmp_4_i_fu_510_p3 <= (tmp_8_i_reg_700 & ap_const_lv1_0);
tmp_7_i_cast_fu_451_p1 <= std_logic_vector(resize(unsigned(sym_reg_631),14));
tmp_8_i_fu_505_p2 <= std_logic_vector(unsigned(grp_fu_483_p2) + unsigned(tmp_7_i_cast_reg_660));
tmp_9_i_cast_fu_535_p1 <= std_logic_vector(resize(unsigned(tmp_9_i_fu_528_p3),64));
tmp_9_i_fu_528_p3 <= (tmp_8_i_reg_700 & ap_const_lv1_1);
tmp_i_fu_458_p3 <= (tmp_31_fu_454_p1 & ap_const_lv5_0);
tmp_s_fu_404_p2 <= "1" when (unsigned(i_reg_138) < unsigned(length_r)) else "0";
end behav;
| lgpl-3.0 | 608f883e6872c1436d688f1696f90873 | 0.583582 | 2.727683 | false | false | false | false |
MilosSubotic/huffman_coding | RTL/src/rtl/reg.vhd | 1 | 743 | -- @license MIT
-- @brief D flip-flop based register.
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
entity reg is
generic(
WIDTH : positive := 1;
RST_INIT : integer := 0
);
port(
i_clk : in std_logic;
in_rst : in std_logic;
i_d : in std_logic_vector(WIDTH-1 downto 0);
o_q : out std_logic_vector(WIDTH-1 downto 0)
);
end entity reg;
architecture arch_reg of reg is
signal r_q : std_logic_vector(WIDTH-1 downto 0);
begin
process(i_clk, in_rst)
begin
if in_rst = '0' then
r_q <= conv_std_logic_vector(RST_INIT, WIDTH);
elsif rising_edge(i_clk) then
r_q <= i_d;
end if;
end process;
o_q <= r_q;
end architecture arch_reg;
| mit | f8a49cd493e3166e50b29ed731c11220 | 0.601615 | 2.616197 | false | false | false | false |
jairov4/accel-oil | solution_kintex7/sim/vhdl/nfa_accept_samples_generic_hw.vhd | 1 | 75,453 | -- ==============================================================
-- RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2013.4
-- Copyright (C) 2013 Xilinx Inc. All rights reserved.
--
-- ===========================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity nfa_accept_samples_generic_hw is
port (
ap_clk : IN STD_LOGIC;
ap_rst : IN STD_LOGIC;
ap_start : IN STD_LOGIC;
ap_done : OUT STD_LOGIC;
ap_idle : OUT STD_LOGIC;
ap_ready : OUT STD_LOGIC;
nfa_initials_buckets_req_din : OUT STD_LOGIC;
nfa_initials_buckets_req_full_n : IN STD_LOGIC;
nfa_initials_buckets_req_write : OUT STD_LOGIC;
nfa_initials_buckets_rsp_empty_n : IN STD_LOGIC;
nfa_initials_buckets_rsp_read : OUT STD_LOGIC;
nfa_initials_buckets_address : OUT STD_LOGIC_VECTOR (31 downto 0);
nfa_initials_buckets_datain : IN STD_LOGIC_VECTOR (31 downto 0);
nfa_initials_buckets_dataout : OUT STD_LOGIC_VECTOR (31 downto 0);
nfa_initials_buckets_size : OUT STD_LOGIC_VECTOR (31 downto 0);
nfa_finals_buckets_req_din : OUT STD_LOGIC;
nfa_finals_buckets_req_full_n : IN STD_LOGIC;
nfa_finals_buckets_req_write : OUT STD_LOGIC;
nfa_finals_buckets_rsp_empty_n : IN STD_LOGIC;
nfa_finals_buckets_rsp_read : OUT STD_LOGIC;
nfa_finals_buckets_address : OUT STD_LOGIC_VECTOR (31 downto 0);
nfa_finals_buckets_datain : IN STD_LOGIC_VECTOR (31 downto 0);
nfa_finals_buckets_dataout : OUT STD_LOGIC_VECTOR (31 downto 0);
nfa_finals_buckets_size : OUT STD_LOGIC_VECTOR (31 downto 0);
nfa_forward_buckets_req_din : OUT STD_LOGIC;
nfa_forward_buckets_req_full_n : IN STD_LOGIC;
nfa_forward_buckets_req_write : OUT STD_LOGIC;
nfa_forward_buckets_rsp_empty_n : IN STD_LOGIC;
nfa_forward_buckets_rsp_read : OUT STD_LOGIC;
nfa_forward_buckets_address : OUT STD_LOGIC_VECTOR (31 downto 0);
nfa_forward_buckets_datain : IN STD_LOGIC_VECTOR (31 downto 0);
nfa_forward_buckets_dataout : OUT STD_LOGIC_VECTOR (31 downto 0);
nfa_forward_buckets_size : OUT STD_LOGIC_VECTOR (31 downto 0);
nfa_symbols : IN STD_LOGIC_VECTOR (7 downto 0);
sample_buffer_req_din : OUT STD_LOGIC;
sample_buffer_req_full_n : IN STD_LOGIC;
sample_buffer_req_write : OUT STD_LOGIC;
sample_buffer_rsp_empty_n : IN STD_LOGIC;
sample_buffer_rsp_read : OUT STD_LOGIC;
sample_buffer_address : OUT STD_LOGIC_VECTOR (31 downto 0);
sample_buffer_datain : IN STD_LOGIC_VECTOR (7 downto 0);
sample_buffer_dataout : OUT STD_LOGIC_VECTOR (7 downto 0);
sample_buffer_size : OUT STD_LOGIC_VECTOR (31 downto 0);
sample_buffer_length : IN STD_LOGIC_VECTOR (31 downto 0);
sample_length : IN STD_LOGIC_VECTOR (15 downto 0);
indices_begin_req_din : OUT STD_LOGIC;
indices_begin_req_full_n : IN STD_LOGIC;
indices_begin_req_write : OUT STD_LOGIC;
indices_begin_rsp_empty_n : IN STD_LOGIC;
indices_begin_rsp_read : OUT STD_LOGIC;
indices_begin_address : OUT STD_LOGIC_VECTOR (31 downto 0);
indices_begin_datain : IN STD_LOGIC_VECTOR (31 downto 0);
indices_begin_dataout : OUT STD_LOGIC_VECTOR (31 downto 0);
indices_begin_size : OUT STD_LOGIC_VECTOR (31 downto 0);
indices_samples_req_din : OUT STD_LOGIC;
indices_samples_req_full_n : IN STD_LOGIC;
indices_samples_req_write : OUT STD_LOGIC;
indices_samples_rsp_empty_n : IN STD_LOGIC;
indices_samples_rsp_read : OUT STD_LOGIC;
indices_samples_address : OUT STD_LOGIC_VECTOR (31 downto 0);
indices_samples_datain : IN STD_LOGIC_VECTOR (15 downto 0);
indices_samples_dataout : OUT STD_LOGIC_VECTOR (15 downto 0);
indices_samples_size : OUT STD_LOGIC_VECTOR (31 downto 0);
indices_stride_req_din : OUT STD_LOGIC;
indices_stride_req_full_n : IN STD_LOGIC;
indices_stride_req_write : OUT STD_LOGIC;
indices_stride_rsp_empty_n : IN STD_LOGIC;
indices_stride_rsp_read : OUT STD_LOGIC;
indices_stride_address : OUT STD_LOGIC_VECTOR (31 downto 0);
indices_stride_datain : IN STD_LOGIC_VECTOR (7 downto 0);
indices_stride_dataout : OUT STD_LOGIC_VECTOR (7 downto 0);
indices_stride_size : OUT STD_LOGIC_VECTOR (31 downto 0);
i_size : IN STD_LOGIC_VECTOR (15 downto 0);
begin_index : IN STD_LOGIC_VECTOR (15 downto 0);
begin_sample : IN STD_LOGIC_VECTOR (15 downto 0);
end_index : IN STD_LOGIC_VECTOR (15 downto 0);
end_sample : IN STD_LOGIC_VECTOR (15 downto 0);
stop_on_first : IN STD_LOGIC_VECTOR (0 downto 0);
accept : IN STD_LOGIC_VECTOR (0 downto 0);
ap_return : OUT STD_LOGIC_VECTOR (31 downto 0) );
end;
architecture behav of nfa_accept_samples_generic_hw is
attribute CORE_GENERATION_INFO : STRING;
attribute CORE_GENERATION_INFO of behav : architecture is
"nfa_accept_samples_generic_hw,hls_ip_2013_4,{HLS_INPUT_TYPE=c,HLS_INPUT_FLOAT=0,HLS_INPUT_FIXED=0,HLS_INPUT_PART=xc7k325tffg676-3,HLS_INPUT_CLOCK=2.000000,HLS_INPUT_ARCH=others,HLS_SYN_CLOCK=1.750000,HLS_SYN_LAT=78934009,HLS_SYN_TPT=none,HLS_SYN_MEM=0,HLS_SYN_DSP=0,HLS_SYN_FF=0,HLS_SYN_LUT=0}";
constant ap_const_logic_1 : STD_LOGIC := '1';
constant ap_const_logic_0 : STD_LOGIC := '0';
constant ap_ST_st1_fsm_0 : STD_LOGIC_VECTOR (4 downto 0) := "00000";
constant ap_ST_st2_fsm_1 : STD_LOGIC_VECTOR (4 downto 0) := "00001";
constant ap_ST_st3_fsm_2 : STD_LOGIC_VECTOR (4 downto 0) := "00010";
constant ap_ST_st4_fsm_3 : STD_LOGIC_VECTOR (4 downto 0) := "00011";
constant ap_ST_st5_fsm_4 : STD_LOGIC_VECTOR (4 downto 0) := "00100";
constant ap_ST_st6_fsm_5 : STD_LOGIC_VECTOR (4 downto 0) := "00101";
constant ap_ST_st7_fsm_6 : STD_LOGIC_VECTOR (4 downto 0) := "00110";
constant ap_ST_st8_fsm_7 : STD_LOGIC_VECTOR (4 downto 0) := "00111";
constant ap_ST_st9_fsm_8 : STD_LOGIC_VECTOR (4 downto 0) := "01000";
constant ap_ST_st10_fsm_9 : STD_LOGIC_VECTOR (4 downto 0) := "01001";
constant ap_ST_st11_fsm_10 : STD_LOGIC_VECTOR (4 downto 0) := "01010";
constant ap_ST_st12_fsm_11 : STD_LOGIC_VECTOR (4 downto 0) := "01011";
constant ap_ST_st13_fsm_12 : STD_LOGIC_VECTOR (4 downto 0) := "01100";
constant ap_ST_st14_fsm_13 : STD_LOGIC_VECTOR (4 downto 0) := "01101";
constant ap_ST_st15_fsm_14 : STD_LOGIC_VECTOR (4 downto 0) := "01110";
constant ap_ST_st16_fsm_15 : STD_LOGIC_VECTOR (4 downto 0) := "01111";
constant ap_ST_st17_fsm_16 : STD_LOGIC_VECTOR (4 downto 0) := "10000";
constant ap_ST_st18_fsm_17 : STD_LOGIC_VECTOR (4 downto 0) := "10001";
constant ap_ST_st19_fsm_18 : STD_LOGIC_VECTOR (4 downto 0) := "10010";
constant ap_ST_st20_fsm_19 : STD_LOGIC_VECTOR (4 downto 0) := "10011";
constant ap_ST_st21_fsm_20 : STD_LOGIC_VECTOR (4 downto 0) := "10100";
constant ap_ST_st22_fsm_21 : STD_LOGIC_VECTOR (4 downto 0) := "10101";
constant ap_ST_st23_fsm_22 : STD_LOGIC_VECTOR (4 downto 0) := "10110";
constant ap_ST_st24_fsm_23 : STD_LOGIC_VECTOR (4 downto 0) := "10111";
constant ap_const_lv1_0 : STD_LOGIC_VECTOR (0 downto 0) := "0";
constant ap_const_lv32_1 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000001";
constant ap_const_lv32_0 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000000";
signal ap_CS_fsm : STD_LOGIC_VECTOR (4 downto 0) := "00000";
signal stop_on_first_read_read_fu_104_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_i_fu_230_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_i_reg_316 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_i_10_fu_235_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_i_10_reg_321 : STD_LOGIC_VECTOR (0 downto 0);
signal c_load_reg_326 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_sample_iterator_get_offset_fu_208_ap_return : STD_LOGIC_VECTOR (31 downto 0);
signal offset_reg_335 : STD_LOGIC_VECTOR (31 downto 0);
signal or_cond_fu_247_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal or_cond_reg_340 : STD_LOGIC_VECTOR (0 downto 0);
signal grp_nfa_accept_sample_fu_178_ap_done : STD_LOGIC;
signal c_1_fu_252_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal c_1_reg_344 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_nfa_accept_sample_fu_178_ap_start : STD_LOGIC;
signal grp_nfa_accept_sample_fu_178_ap_idle : STD_LOGIC;
signal grp_nfa_accept_sample_fu_178_ap_ready : STD_LOGIC;
signal grp_nfa_accept_sample_fu_178_nfa_initials_buckets_req_din : STD_LOGIC;
signal grp_nfa_accept_sample_fu_178_nfa_initials_buckets_req_full_n : STD_LOGIC;
signal grp_nfa_accept_sample_fu_178_nfa_initials_buckets_req_write : STD_LOGIC;
signal grp_nfa_accept_sample_fu_178_nfa_initials_buckets_rsp_empty_n : STD_LOGIC;
signal grp_nfa_accept_sample_fu_178_nfa_initials_buckets_rsp_read : STD_LOGIC;
signal grp_nfa_accept_sample_fu_178_nfa_initials_buckets_address : STD_LOGIC_VECTOR (31 downto 0);
signal grp_nfa_accept_sample_fu_178_nfa_initials_buckets_datain : STD_LOGIC_VECTOR (31 downto 0);
signal grp_nfa_accept_sample_fu_178_nfa_initials_buckets_dataout : STD_LOGIC_VECTOR (31 downto 0);
signal grp_nfa_accept_sample_fu_178_nfa_initials_buckets_size : STD_LOGIC_VECTOR (31 downto 0);
signal grp_nfa_accept_sample_fu_178_nfa_finals_buckets_req_din : STD_LOGIC;
signal grp_nfa_accept_sample_fu_178_nfa_finals_buckets_req_full_n : STD_LOGIC;
signal grp_nfa_accept_sample_fu_178_nfa_finals_buckets_req_write : STD_LOGIC;
signal grp_nfa_accept_sample_fu_178_nfa_finals_buckets_rsp_empty_n : STD_LOGIC;
signal grp_nfa_accept_sample_fu_178_nfa_finals_buckets_rsp_read : STD_LOGIC;
signal grp_nfa_accept_sample_fu_178_nfa_finals_buckets_address : STD_LOGIC_VECTOR (31 downto 0);
signal grp_nfa_accept_sample_fu_178_nfa_finals_buckets_datain : STD_LOGIC_VECTOR (31 downto 0);
signal grp_nfa_accept_sample_fu_178_nfa_finals_buckets_dataout : STD_LOGIC_VECTOR (31 downto 0);
signal grp_nfa_accept_sample_fu_178_nfa_finals_buckets_size : STD_LOGIC_VECTOR (31 downto 0);
signal grp_nfa_accept_sample_fu_178_nfa_forward_buckets_req_din : STD_LOGIC;
signal grp_nfa_accept_sample_fu_178_nfa_forward_buckets_req_full_n : STD_LOGIC;
signal grp_nfa_accept_sample_fu_178_nfa_forward_buckets_req_write : STD_LOGIC;
signal grp_nfa_accept_sample_fu_178_nfa_forward_buckets_rsp_empty_n : STD_LOGIC;
signal grp_nfa_accept_sample_fu_178_nfa_forward_buckets_rsp_read : STD_LOGIC;
signal grp_nfa_accept_sample_fu_178_nfa_forward_buckets_address : STD_LOGIC_VECTOR (31 downto 0);
signal grp_nfa_accept_sample_fu_178_nfa_forward_buckets_datain : STD_LOGIC_VECTOR (31 downto 0);
signal grp_nfa_accept_sample_fu_178_nfa_forward_buckets_dataout : STD_LOGIC_VECTOR (31 downto 0);
signal grp_nfa_accept_sample_fu_178_nfa_forward_buckets_size : STD_LOGIC_VECTOR (31 downto 0);
signal grp_nfa_accept_sample_fu_178_nfa_symbols : STD_LOGIC_VECTOR (7 downto 0);
signal grp_nfa_accept_sample_fu_178_sample_req_din : STD_LOGIC;
signal grp_nfa_accept_sample_fu_178_sample_req_full_n : STD_LOGIC;
signal grp_nfa_accept_sample_fu_178_sample_req_write : STD_LOGIC;
signal grp_nfa_accept_sample_fu_178_sample_rsp_empty_n : STD_LOGIC;
signal grp_nfa_accept_sample_fu_178_sample_rsp_read : STD_LOGIC;
signal grp_nfa_accept_sample_fu_178_sample_address : STD_LOGIC_VECTOR (31 downto 0);
signal grp_nfa_accept_sample_fu_178_sample_datain : STD_LOGIC_VECTOR (7 downto 0);
signal grp_nfa_accept_sample_fu_178_sample_dataout : STD_LOGIC_VECTOR (7 downto 0);
signal grp_nfa_accept_sample_fu_178_sample_size : STD_LOGIC_VECTOR (31 downto 0);
signal grp_nfa_accept_sample_fu_178_tmp_14 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_nfa_accept_sample_fu_178_length_r : STD_LOGIC_VECTOR (15 downto 0);
signal grp_nfa_accept_sample_fu_178_ap_return : STD_LOGIC_VECTOR (0 downto 0);
signal grp_sample_iterator_next_fu_194_ap_start : STD_LOGIC;
signal grp_sample_iterator_next_fu_194_ap_done : STD_LOGIC;
signal grp_sample_iterator_next_fu_194_ap_idle : STD_LOGIC;
signal grp_sample_iterator_next_fu_194_ap_ready : STD_LOGIC;
signal grp_sample_iterator_next_fu_194_indices_samples_req_din : STD_LOGIC;
signal grp_sample_iterator_next_fu_194_indices_samples_req_full_n : STD_LOGIC;
signal grp_sample_iterator_next_fu_194_indices_samples_req_write : STD_LOGIC;
signal grp_sample_iterator_next_fu_194_indices_samples_rsp_empty_n : STD_LOGIC;
signal grp_sample_iterator_next_fu_194_indices_samples_rsp_read : STD_LOGIC;
signal grp_sample_iterator_next_fu_194_indices_samples_address : STD_LOGIC_VECTOR (31 downto 0);
signal grp_sample_iterator_next_fu_194_indices_samples_datain : STD_LOGIC_VECTOR (15 downto 0);
signal grp_sample_iterator_next_fu_194_indices_samples_dataout : STD_LOGIC_VECTOR (15 downto 0);
signal grp_sample_iterator_next_fu_194_indices_samples_size : STD_LOGIC_VECTOR (31 downto 0);
signal grp_sample_iterator_next_fu_194_ap_ce : STD_LOGIC;
signal grp_sample_iterator_next_fu_194_indices_begin_req_din : STD_LOGIC;
signal grp_sample_iterator_next_fu_194_indices_begin_req_full_n : STD_LOGIC;
signal grp_sample_iterator_next_fu_194_indices_begin_req_write : STD_LOGIC;
signal grp_sample_iterator_next_fu_194_indices_begin_rsp_empty_n : STD_LOGIC;
signal grp_sample_iterator_next_fu_194_indices_begin_rsp_read : STD_LOGIC;
signal grp_sample_iterator_next_fu_194_indices_begin_address : STD_LOGIC_VECTOR (31 downto 0);
signal grp_sample_iterator_next_fu_194_indices_begin_datain : STD_LOGIC_VECTOR (31 downto 0);
signal grp_sample_iterator_next_fu_194_indices_begin_dataout : STD_LOGIC_VECTOR (31 downto 0);
signal grp_sample_iterator_next_fu_194_indices_begin_size : STD_LOGIC_VECTOR (31 downto 0);
signal grp_sample_iterator_next_fu_194_indices_stride_req_din : STD_LOGIC;
signal grp_sample_iterator_next_fu_194_indices_stride_req_full_n : STD_LOGIC;
signal grp_sample_iterator_next_fu_194_indices_stride_req_write : STD_LOGIC;
signal grp_sample_iterator_next_fu_194_indices_stride_rsp_empty_n : STD_LOGIC;
signal grp_sample_iterator_next_fu_194_indices_stride_rsp_read : STD_LOGIC;
signal grp_sample_iterator_next_fu_194_indices_stride_address : STD_LOGIC_VECTOR (31 downto 0);
signal grp_sample_iterator_next_fu_194_indices_stride_datain : STD_LOGIC_VECTOR (7 downto 0);
signal grp_sample_iterator_next_fu_194_indices_stride_dataout : STD_LOGIC_VECTOR (7 downto 0);
signal grp_sample_iterator_next_fu_194_indices_stride_size : STD_LOGIC_VECTOR (31 downto 0);
signal grp_sample_iterator_next_fu_194_i_index : STD_LOGIC_VECTOR (15 downto 0);
signal grp_sample_iterator_next_fu_194_i_sample : STD_LOGIC_VECTOR (15 downto 0);
signal grp_sample_iterator_next_fu_194_ap_return_0 : STD_LOGIC_VECTOR (15 downto 0);
signal grp_sample_iterator_next_fu_194_ap_return_1 : STD_LOGIC_VECTOR (15 downto 0);
signal grp_sample_iterator_get_offset_fu_208_ap_start : STD_LOGIC;
signal grp_sample_iterator_get_offset_fu_208_ap_done : STD_LOGIC;
signal grp_sample_iterator_get_offset_fu_208_ap_idle : STD_LOGIC;
signal grp_sample_iterator_get_offset_fu_208_ap_ready : STD_LOGIC;
signal grp_sample_iterator_get_offset_fu_208_indices_stride_req_din : STD_LOGIC;
signal grp_sample_iterator_get_offset_fu_208_indices_stride_req_full_n : STD_LOGIC;
signal grp_sample_iterator_get_offset_fu_208_indices_stride_req_write : STD_LOGIC;
signal grp_sample_iterator_get_offset_fu_208_indices_stride_rsp_empty_n : STD_LOGIC;
signal grp_sample_iterator_get_offset_fu_208_indices_stride_rsp_read : STD_LOGIC;
signal grp_sample_iterator_get_offset_fu_208_indices_stride_address : STD_LOGIC_VECTOR (31 downto 0);
signal grp_sample_iterator_get_offset_fu_208_indices_stride_datain : STD_LOGIC_VECTOR (7 downto 0);
signal grp_sample_iterator_get_offset_fu_208_indices_stride_dataout : STD_LOGIC_VECTOR (7 downto 0);
signal grp_sample_iterator_get_offset_fu_208_indices_stride_size : STD_LOGIC_VECTOR (31 downto 0);
signal grp_sample_iterator_get_offset_fu_208_indices_begin_req_din : STD_LOGIC;
signal grp_sample_iterator_get_offset_fu_208_indices_begin_req_full_n : STD_LOGIC;
signal grp_sample_iterator_get_offset_fu_208_indices_begin_req_write : STD_LOGIC;
signal grp_sample_iterator_get_offset_fu_208_indices_begin_rsp_empty_n : STD_LOGIC;
signal grp_sample_iterator_get_offset_fu_208_indices_begin_rsp_read : STD_LOGIC;
signal grp_sample_iterator_get_offset_fu_208_indices_begin_address : STD_LOGIC_VECTOR (31 downto 0);
signal grp_sample_iterator_get_offset_fu_208_indices_begin_datain : STD_LOGIC_VECTOR (31 downto 0);
signal grp_sample_iterator_get_offset_fu_208_indices_begin_dataout : STD_LOGIC_VECTOR (31 downto 0);
signal grp_sample_iterator_get_offset_fu_208_indices_begin_size : STD_LOGIC_VECTOR (31 downto 0);
signal grp_sample_iterator_get_offset_fu_208_ap_ce : STD_LOGIC;
signal grp_sample_iterator_get_offset_fu_208_i_index : STD_LOGIC_VECTOR (15 downto 0);
signal grp_sample_iterator_get_offset_fu_208_i_sample : STD_LOGIC_VECTOR (15 downto 0);
signal grp_sample_iterator_get_offset_fu_208_indices_samples_req_din : STD_LOGIC;
signal grp_sample_iterator_get_offset_fu_208_indices_samples_req_full_n : STD_LOGIC;
signal grp_sample_iterator_get_offset_fu_208_indices_samples_req_write : STD_LOGIC;
signal grp_sample_iterator_get_offset_fu_208_indices_samples_rsp_empty_n : STD_LOGIC;
signal grp_sample_iterator_get_offset_fu_208_indices_samples_rsp_read : STD_LOGIC;
signal grp_sample_iterator_get_offset_fu_208_indices_samples_address : STD_LOGIC_VECTOR (31 downto 0);
signal grp_sample_iterator_get_offset_fu_208_indices_samples_datain : STD_LOGIC_VECTOR (15 downto 0);
signal grp_sample_iterator_get_offset_fu_208_indices_samples_dataout : STD_LOGIC_VECTOR (15 downto 0);
signal grp_sample_iterator_get_offset_fu_208_indices_samples_size : STD_LOGIC_VECTOR (31 downto 0);
signal grp_sample_iterator_get_offset_fu_208_sample_buffer_size : STD_LOGIC_VECTOR (31 downto 0);
signal grp_sample_iterator_get_offset_fu_208_sample_length : STD_LOGIC_VECTOR (15 downto 0);
signal i_index_reg_146 : STD_LOGIC_VECTOR (15 downto 0);
signal i_sample_reg_156 : STD_LOGIC_VECTOR (15 downto 0);
signal p_0_reg_166 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_i_11_fu_243_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal grp_nfa_accept_sample_fu_178_ap_start_ap_start_reg : STD_LOGIC := '0';
signal grp_sample_iterator_next_fu_194_ap_start_ap_start_reg : STD_LOGIC := '0';
signal ap_NS_fsm : STD_LOGIC_VECTOR (4 downto 0);
signal grp_sample_iterator_get_offset_fu_208_ap_start_ap_start_reg : STD_LOGIC := '0';
signal c_fu_94 : STD_LOGIC_VECTOR (31 downto 0);
component nfa_accept_sample IS
port (
ap_clk : IN STD_LOGIC;
ap_rst : IN STD_LOGIC;
ap_start : IN STD_LOGIC;
ap_done : OUT STD_LOGIC;
ap_idle : OUT STD_LOGIC;
ap_ready : OUT STD_LOGIC;
nfa_initials_buckets_req_din : OUT STD_LOGIC;
nfa_initials_buckets_req_full_n : IN STD_LOGIC;
nfa_initials_buckets_req_write : OUT STD_LOGIC;
nfa_initials_buckets_rsp_empty_n : IN STD_LOGIC;
nfa_initials_buckets_rsp_read : OUT STD_LOGIC;
nfa_initials_buckets_address : OUT STD_LOGIC_VECTOR (31 downto 0);
nfa_initials_buckets_datain : IN STD_LOGIC_VECTOR (31 downto 0);
nfa_initials_buckets_dataout : OUT STD_LOGIC_VECTOR (31 downto 0);
nfa_initials_buckets_size : OUT STD_LOGIC_VECTOR (31 downto 0);
nfa_finals_buckets_req_din : OUT STD_LOGIC;
nfa_finals_buckets_req_full_n : IN STD_LOGIC;
nfa_finals_buckets_req_write : OUT STD_LOGIC;
nfa_finals_buckets_rsp_empty_n : IN STD_LOGIC;
nfa_finals_buckets_rsp_read : OUT STD_LOGIC;
nfa_finals_buckets_address : OUT STD_LOGIC_VECTOR (31 downto 0);
nfa_finals_buckets_datain : IN STD_LOGIC_VECTOR (31 downto 0);
nfa_finals_buckets_dataout : OUT STD_LOGIC_VECTOR (31 downto 0);
nfa_finals_buckets_size : OUT STD_LOGIC_VECTOR (31 downto 0);
nfa_forward_buckets_req_din : OUT STD_LOGIC;
nfa_forward_buckets_req_full_n : IN STD_LOGIC;
nfa_forward_buckets_req_write : OUT STD_LOGIC;
nfa_forward_buckets_rsp_empty_n : IN STD_LOGIC;
nfa_forward_buckets_rsp_read : OUT STD_LOGIC;
nfa_forward_buckets_address : OUT STD_LOGIC_VECTOR (31 downto 0);
nfa_forward_buckets_datain : IN STD_LOGIC_VECTOR (31 downto 0);
nfa_forward_buckets_dataout : OUT STD_LOGIC_VECTOR (31 downto 0);
nfa_forward_buckets_size : OUT STD_LOGIC_VECTOR (31 downto 0);
nfa_symbols : IN STD_LOGIC_VECTOR (7 downto 0);
sample_req_din : OUT STD_LOGIC;
sample_req_full_n : IN STD_LOGIC;
sample_req_write : OUT STD_LOGIC;
sample_rsp_empty_n : IN STD_LOGIC;
sample_rsp_read : OUT STD_LOGIC;
sample_address : OUT STD_LOGIC_VECTOR (31 downto 0);
sample_datain : IN STD_LOGIC_VECTOR (7 downto 0);
sample_dataout : OUT STD_LOGIC_VECTOR (7 downto 0);
sample_size : OUT STD_LOGIC_VECTOR (31 downto 0);
tmp_14 : IN STD_LOGIC_VECTOR (31 downto 0);
length_r : IN STD_LOGIC_VECTOR (15 downto 0);
ap_return : OUT STD_LOGIC_VECTOR (0 downto 0) );
end component;
component sample_iterator_next IS
port (
ap_clk : IN STD_LOGIC;
ap_rst : IN STD_LOGIC;
ap_start : IN STD_LOGIC;
ap_done : OUT STD_LOGIC;
ap_idle : OUT STD_LOGIC;
ap_ready : OUT STD_LOGIC;
indices_samples_req_din : OUT STD_LOGIC;
indices_samples_req_full_n : IN STD_LOGIC;
indices_samples_req_write : OUT STD_LOGIC;
indices_samples_rsp_empty_n : IN STD_LOGIC;
indices_samples_rsp_read : OUT STD_LOGIC;
indices_samples_address : OUT STD_LOGIC_VECTOR (31 downto 0);
indices_samples_datain : IN STD_LOGIC_VECTOR (15 downto 0);
indices_samples_dataout : OUT STD_LOGIC_VECTOR (15 downto 0);
indices_samples_size : OUT STD_LOGIC_VECTOR (31 downto 0);
ap_ce : IN STD_LOGIC;
indices_begin_req_din : OUT STD_LOGIC;
indices_begin_req_full_n : IN STD_LOGIC;
indices_begin_req_write : OUT STD_LOGIC;
indices_begin_rsp_empty_n : IN STD_LOGIC;
indices_begin_rsp_read : OUT STD_LOGIC;
indices_begin_address : OUT STD_LOGIC_VECTOR (31 downto 0);
indices_begin_datain : IN STD_LOGIC_VECTOR (31 downto 0);
indices_begin_dataout : OUT STD_LOGIC_VECTOR (31 downto 0);
indices_begin_size : OUT STD_LOGIC_VECTOR (31 downto 0);
indices_stride_req_din : OUT STD_LOGIC;
indices_stride_req_full_n : IN STD_LOGIC;
indices_stride_req_write : OUT STD_LOGIC;
indices_stride_rsp_empty_n : IN STD_LOGIC;
indices_stride_rsp_read : OUT STD_LOGIC;
indices_stride_address : OUT STD_LOGIC_VECTOR (31 downto 0);
indices_stride_datain : IN STD_LOGIC_VECTOR (7 downto 0);
indices_stride_dataout : OUT STD_LOGIC_VECTOR (7 downto 0);
indices_stride_size : OUT STD_LOGIC_VECTOR (31 downto 0);
i_index : IN STD_LOGIC_VECTOR (15 downto 0);
i_sample : IN STD_LOGIC_VECTOR (15 downto 0);
ap_return_0 : OUT STD_LOGIC_VECTOR (15 downto 0);
ap_return_1 : OUT STD_LOGIC_VECTOR (15 downto 0) );
end component;
component sample_iterator_get_offset IS
port (
ap_clk : IN STD_LOGIC;
ap_rst : IN STD_LOGIC;
ap_start : IN STD_LOGIC;
ap_done : OUT STD_LOGIC;
ap_idle : OUT STD_LOGIC;
ap_ready : OUT STD_LOGIC;
indices_stride_req_din : OUT STD_LOGIC;
indices_stride_req_full_n : IN STD_LOGIC;
indices_stride_req_write : OUT STD_LOGIC;
indices_stride_rsp_empty_n : IN STD_LOGIC;
indices_stride_rsp_read : OUT STD_LOGIC;
indices_stride_address : OUT STD_LOGIC_VECTOR (31 downto 0);
indices_stride_datain : IN STD_LOGIC_VECTOR (7 downto 0);
indices_stride_dataout : OUT STD_LOGIC_VECTOR (7 downto 0);
indices_stride_size : OUT STD_LOGIC_VECTOR (31 downto 0);
indices_begin_req_din : OUT STD_LOGIC;
indices_begin_req_full_n : IN STD_LOGIC;
indices_begin_req_write : OUT STD_LOGIC;
indices_begin_rsp_empty_n : IN STD_LOGIC;
indices_begin_rsp_read : OUT STD_LOGIC;
indices_begin_address : OUT STD_LOGIC_VECTOR (31 downto 0);
indices_begin_datain : IN STD_LOGIC_VECTOR (31 downto 0);
indices_begin_dataout : OUT STD_LOGIC_VECTOR (31 downto 0);
indices_begin_size : OUT STD_LOGIC_VECTOR (31 downto 0);
ap_ce : IN STD_LOGIC;
i_index : IN STD_LOGIC_VECTOR (15 downto 0);
i_sample : IN STD_LOGIC_VECTOR (15 downto 0);
indices_samples_req_din : OUT STD_LOGIC;
indices_samples_req_full_n : IN STD_LOGIC;
indices_samples_req_write : OUT STD_LOGIC;
indices_samples_rsp_empty_n : IN STD_LOGIC;
indices_samples_rsp_read : OUT STD_LOGIC;
indices_samples_address : OUT STD_LOGIC_VECTOR (31 downto 0);
indices_samples_datain : IN STD_LOGIC_VECTOR (15 downto 0);
indices_samples_dataout : OUT STD_LOGIC_VECTOR (15 downto 0);
indices_samples_size : OUT STD_LOGIC_VECTOR (31 downto 0);
sample_buffer_size : IN STD_LOGIC_VECTOR (31 downto 0);
sample_length : IN STD_LOGIC_VECTOR (15 downto 0);
ap_return : OUT STD_LOGIC_VECTOR (31 downto 0) );
end component;
begin
grp_nfa_accept_sample_fu_178 : component nfa_accept_sample
port map (
ap_clk => ap_clk,
ap_rst => ap_rst,
ap_start => grp_nfa_accept_sample_fu_178_ap_start,
ap_done => grp_nfa_accept_sample_fu_178_ap_done,
ap_idle => grp_nfa_accept_sample_fu_178_ap_idle,
ap_ready => grp_nfa_accept_sample_fu_178_ap_ready,
nfa_initials_buckets_req_din => grp_nfa_accept_sample_fu_178_nfa_initials_buckets_req_din,
nfa_initials_buckets_req_full_n => grp_nfa_accept_sample_fu_178_nfa_initials_buckets_req_full_n,
nfa_initials_buckets_req_write => grp_nfa_accept_sample_fu_178_nfa_initials_buckets_req_write,
nfa_initials_buckets_rsp_empty_n => grp_nfa_accept_sample_fu_178_nfa_initials_buckets_rsp_empty_n,
nfa_initials_buckets_rsp_read => grp_nfa_accept_sample_fu_178_nfa_initials_buckets_rsp_read,
nfa_initials_buckets_address => grp_nfa_accept_sample_fu_178_nfa_initials_buckets_address,
nfa_initials_buckets_datain => grp_nfa_accept_sample_fu_178_nfa_initials_buckets_datain,
nfa_initials_buckets_dataout => grp_nfa_accept_sample_fu_178_nfa_initials_buckets_dataout,
nfa_initials_buckets_size => grp_nfa_accept_sample_fu_178_nfa_initials_buckets_size,
nfa_finals_buckets_req_din => grp_nfa_accept_sample_fu_178_nfa_finals_buckets_req_din,
nfa_finals_buckets_req_full_n => grp_nfa_accept_sample_fu_178_nfa_finals_buckets_req_full_n,
nfa_finals_buckets_req_write => grp_nfa_accept_sample_fu_178_nfa_finals_buckets_req_write,
nfa_finals_buckets_rsp_empty_n => grp_nfa_accept_sample_fu_178_nfa_finals_buckets_rsp_empty_n,
nfa_finals_buckets_rsp_read => grp_nfa_accept_sample_fu_178_nfa_finals_buckets_rsp_read,
nfa_finals_buckets_address => grp_nfa_accept_sample_fu_178_nfa_finals_buckets_address,
nfa_finals_buckets_datain => grp_nfa_accept_sample_fu_178_nfa_finals_buckets_datain,
nfa_finals_buckets_dataout => grp_nfa_accept_sample_fu_178_nfa_finals_buckets_dataout,
nfa_finals_buckets_size => grp_nfa_accept_sample_fu_178_nfa_finals_buckets_size,
nfa_forward_buckets_req_din => grp_nfa_accept_sample_fu_178_nfa_forward_buckets_req_din,
nfa_forward_buckets_req_full_n => grp_nfa_accept_sample_fu_178_nfa_forward_buckets_req_full_n,
nfa_forward_buckets_req_write => grp_nfa_accept_sample_fu_178_nfa_forward_buckets_req_write,
nfa_forward_buckets_rsp_empty_n => grp_nfa_accept_sample_fu_178_nfa_forward_buckets_rsp_empty_n,
nfa_forward_buckets_rsp_read => grp_nfa_accept_sample_fu_178_nfa_forward_buckets_rsp_read,
nfa_forward_buckets_address => grp_nfa_accept_sample_fu_178_nfa_forward_buckets_address,
nfa_forward_buckets_datain => grp_nfa_accept_sample_fu_178_nfa_forward_buckets_datain,
nfa_forward_buckets_dataout => grp_nfa_accept_sample_fu_178_nfa_forward_buckets_dataout,
nfa_forward_buckets_size => grp_nfa_accept_sample_fu_178_nfa_forward_buckets_size,
nfa_symbols => grp_nfa_accept_sample_fu_178_nfa_symbols,
sample_req_din => grp_nfa_accept_sample_fu_178_sample_req_din,
sample_req_full_n => grp_nfa_accept_sample_fu_178_sample_req_full_n,
sample_req_write => grp_nfa_accept_sample_fu_178_sample_req_write,
sample_rsp_empty_n => grp_nfa_accept_sample_fu_178_sample_rsp_empty_n,
sample_rsp_read => grp_nfa_accept_sample_fu_178_sample_rsp_read,
sample_address => grp_nfa_accept_sample_fu_178_sample_address,
sample_datain => grp_nfa_accept_sample_fu_178_sample_datain,
sample_dataout => grp_nfa_accept_sample_fu_178_sample_dataout,
sample_size => grp_nfa_accept_sample_fu_178_sample_size,
tmp_14 => grp_nfa_accept_sample_fu_178_tmp_14,
length_r => grp_nfa_accept_sample_fu_178_length_r,
ap_return => grp_nfa_accept_sample_fu_178_ap_return);
grp_sample_iterator_next_fu_194 : component sample_iterator_next
port map (
ap_clk => ap_clk,
ap_rst => ap_rst,
ap_start => grp_sample_iterator_next_fu_194_ap_start,
ap_done => grp_sample_iterator_next_fu_194_ap_done,
ap_idle => grp_sample_iterator_next_fu_194_ap_idle,
ap_ready => grp_sample_iterator_next_fu_194_ap_ready,
indices_samples_req_din => grp_sample_iterator_next_fu_194_indices_samples_req_din,
indices_samples_req_full_n => grp_sample_iterator_next_fu_194_indices_samples_req_full_n,
indices_samples_req_write => grp_sample_iterator_next_fu_194_indices_samples_req_write,
indices_samples_rsp_empty_n => grp_sample_iterator_next_fu_194_indices_samples_rsp_empty_n,
indices_samples_rsp_read => grp_sample_iterator_next_fu_194_indices_samples_rsp_read,
indices_samples_address => grp_sample_iterator_next_fu_194_indices_samples_address,
indices_samples_datain => grp_sample_iterator_next_fu_194_indices_samples_datain,
indices_samples_dataout => grp_sample_iterator_next_fu_194_indices_samples_dataout,
indices_samples_size => grp_sample_iterator_next_fu_194_indices_samples_size,
ap_ce => grp_sample_iterator_next_fu_194_ap_ce,
indices_begin_req_din => grp_sample_iterator_next_fu_194_indices_begin_req_din,
indices_begin_req_full_n => grp_sample_iterator_next_fu_194_indices_begin_req_full_n,
indices_begin_req_write => grp_sample_iterator_next_fu_194_indices_begin_req_write,
indices_begin_rsp_empty_n => grp_sample_iterator_next_fu_194_indices_begin_rsp_empty_n,
indices_begin_rsp_read => grp_sample_iterator_next_fu_194_indices_begin_rsp_read,
indices_begin_address => grp_sample_iterator_next_fu_194_indices_begin_address,
indices_begin_datain => grp_sample_iterator_next_fu_194_indices_begin_datain,
indices_begin_dataout => grp_sample_iterator_next_fu_194_indices_begin_dataout,
indices_begin_size => grp_sample_iterator_next_fu_194_indices_begin_size,
indices_stride_req_din => grp_sample_iterator_next_fu_194_indices_stride_req_din,
indices_stride_req_full_n => grp_sample_iterator_next_fu_194_indices_stride_req_full_n,
indices_stride_req_write => grp_sample_iterator_next_fu_194_indices_stride_req_write,
indices_stride_rsp_empty_n => grp_sample_iterator_next_fu_194_indices_stride_rsp_empty_n,
indices_stride_rsp_read => grp_sample_iterator_next_fu_194_indices_stride_rsp_read,
indices_stride_address => grp_sample_iterator_next_fu_194_indices_stride_address,
indices_stride_datain => grp_sample_iterator_next_fu_194_indices_stride_datain,
indices_stride_dataout => grp_sample_iterator_next_fu_194_indices_stride_dataout,
indices_stride_size => grp_sample_iterator_next_fu_194_indices_stride_size,
i_index => grp_sample_iterator_next_fu_194_i_index,
i_sample => grp_sample_iterator_next_fu_194_i_sample,
ap_return_0 => grp_sample_iterator_next_fu_194_ap_return_0,
ap_return_1 => grp_sample_iterator_next_fu_194_ap_return_1);
grp_sample_iterator_get_offset_fu_208 : component sample_iterator_get_offset
port map (
ap_clk => ap_clk,
ap_rst => ap_rst,
ap_start => grp_sample_iterator_get_offset_fu_208_ap_start,
ap_done => grp_sample_iterator_get_offset_fu_208_ap_done,
ap_idle => grp_sample_iterator_get_offset_fu_208_ap_idle,
ap_ready => grp_sample_iterator_get_offset_fu_208_ap_ready,
indices_stride_req_din => grp_sample_iterator_get_offset_fu_208_indices_stride_req_din,
indices_stride_req_full_n => grp_sample_iterator_get_offset_fu_208_indices_stride_req_full_n,
indices_stride_req_write => grp_sample_iterator_get_offset_fu_208_indices_stride_req_write,
indices_stride_rsp_empty_n => grp_sample_iterator_get_offset_fu_208_indices_stride_rsp_empty_n,
indices_stride_rsp_read => grp_sample_iterator_get_offset_fu_208_indices_stride_rsp_read,
indices_stride_address => grp_sample_iterator_get_offset_fu_208_indices_stride_address,
indices_stride_datain => grp_sample_iterator_get_offset_fu_208_indices_stride_datain,
indices_stride_dataout => grp_sample_iterator_get_offset_fu_208_indices_stride_dataout,
indices_stride_size => grp_sample_iterator_get_offset_fu_208_indices_stride_size,
indices_begin_req_din => grp_sample_iterator_get_offset_fu_208_indices_begin_req_din,
indices_begin_req_full_n => grp_sample_iterator_get_offset_fu_208_indices_begin_req_full_n,
indices_begin_req_write => grp_sample_iterator_get_offset_fu_208_indices_begin_req_write,
indices_begin_rsp_empty_n => grp_sample_iterator_get_offset_fu_208_indices_begin_rsp_empty_n,
indices_begin_rsp_read => grp_sample_iterator_get_offset_fu_208_indices_begin_rsp_read,
indices_begin_address => grp_sample_iterator_get_offset_fu_208_indices_begin_address,
indices_begin_datain => grp_sample_iterator_get_offset_fu_208_indices_begin_datain,
indices_begin_dataout => grp_sample_iterator_get_offset_fu_208_indices_begin_dataout,
indices_begin_size => grp_sample_iterator_get_offset_fu_208_indices_begin_size,
ap_ce => grp_sample_iterator_get_offset_fu_208_ap_ce,
i_index => grp_sample_iterator_get_offset_fu_208_i_index,
i_sample => grp_sample_iterator_get_offset_fu_208_i_sample,
indices_samples_req_din => grp_sample_iterator_get_offset_fu_208_indices_samples_req_din,
indices_samples_req_full_n => grp_sample_iterator_get_offset_fu_208_indices_samples_req_full_n,
indices_samples_req_write => grp_sample_iterator_get_offset_fu_208_indices_samples_req_write,
indices_samples_rsp_empty_n => grp_sample_iterator_get_offset_fu_208_indices_samples_rsp_empty_n,
indices_samples_rsp_read => grp_sample_iterator_get_offset_fu_208_indices_samples_rsp_read,
indices_samples_address => grp_sample_iterator_get_offset_fu_208_indices_samples_address,
indices_samples_datain => grp_sample_iterator_get_offset_fu_208_indices_samples_datain,
indices_samples_dataout => grp_sample_iterator_get_offset_fu_208_indices_samples_dataout,
indices_samples_size => grp_sample_iterator_get_offset_fu_208_indices_samples_size,
sample_buffer_size => grp_sample_iterator_get_offset_fu_208_sample_buffer_size,
sample_length => grp_sample_iterator_get_offset_fu_208_sample_length,
ap_return => grp_sample_iterator_get_offset_fu_208_ap_return);
-- the current state (ap_CS_fsm) of the state machine. --
ap_CS_fsm_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_CS_fsm <= ap_ST_st1_fsm_0;
else
ap_CS_fsm <= ap_NS_fsm;
end if;
end if;
end process;
-- grp_nfa_accept_sample_fu_178_ap_start_ap_start_reg assign process. --
grp_nfa_accept_sample_fu_178_ap_start_ap_start_reg_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
grp_nfa_accept_sample_fu_178_ap_start_ap_start_reg <= ap_const_logic_0;
else
if ((ap_ST_st13_fsm_12 = ap_CS_fsm)) then
grp_nfa_accept_sample_fu_178_ap_start_ap_start_reg <= ap_const_logic_1;
elsif ((ap_const_logic_1 = grp_nfa_accept_sample_fu_178_ap_ready)) then
grp_nfa_accept_sample_fu_178_ap_start_ap_start_reg <= ap_const_logic_0;
end if;
end if;
end if;
end process;
-- grp_sample_iterator_get_offset_fu_208_ap_start_ap_start_reg assign process. --
grp_sample_iterator_get_offset_fu_208_ap_start_ap_start_reg_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
grp_sample_iterator_get_offset_fu_208_ap_start_ap_start_reg <= ap_const_logic_0;
else
if (((ap_ST_st3_fsm_2 = ap_CS_fsm) and (ap_ST_st4_fsm_3 = ap_NS_fsm))) then
grp_sample_iterator_get_offset_fu_208_ap_start_ap_start_reg <= ap_const_logic_1;
elsif ((ap_const_logic_1 = grp_sample_iterator_get_offset_fu_208_ap_ready)) then
grp_sample_iterator_get_offset_fu_208_ap_start_ap_start_reg <= ap_const_logic_0;
end if;
end if;
end if;
end process;
-- grp_sample_iterator_next_fu_194_ap_start_ap_start_reg assign process. --
grp_sample_iterator_next_fu_194_ap_start_ap_start_reg_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
grp_sample_iterator_next_fu_194_ap_start_ap_start_reg <= ap_const_logic_0;
else
if (((ap_ST_st14_fsm_13 = ap_CS_fsm) and (ap_ST_st15_fsm_14 = ap_NS_fsm))) then
grp_sample_iterator_next_fu_194_ap_start_ap_start_reg <= ap_const_logic_1;
elsif ((ap_const_logic_1 = grp_sample_iterator_next_fu_194_ap_ready)) then
grp_sample_iterator_next_fu_194_ap_start_ap_start_reg <= ap_const_logic_0;
end if;
end if;
end if;
end process;
-- c_fu_94 assign process. --
c_fu_94_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ST_st15_fsm_14 = ap_CS_fsm) and (or_cond_reg_340 = ap_const_lv1_0))) then
c_fu_94 <= c_1_reg_344;
elsif (((ap_ST_st1_fsm_0 = ap_CS_fsm) and not((ap_start = ap_const_logic_0)))) then
c_fu_94 <= ap_const_lv32_0;
end if;
end if;
end process;
-- i_index_reg_146 assign process. --
i_index_reg_146_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_ST_st23_fsm_22 = ap_CS_fsm)) then
i_index_reg_146 <= grp_sample_iterator_next_fu_194_ap_return_0;
elsif (((ap_ST_st1_fsm_0 = ap_CS_fsm) and not((ap_start = ap_const_logic_0)))) then
i_index_reg_146 <= begin_index;
end if;
end if;
end process;
-- i_sample_reg_156 assign process. --
i_sample_reg_156_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_ST_st23_fsm_22 = ap_CS_fsm)) then
i_sample_reg_156 <= grp_sample_iterator_next_fu_194_ap_return_1;
elsif (((ap_ST_st1_fsm_0 = ap_CS_fsm) and not((ap_start = ap_const_logic_0)))) then
i_sample_reg_156 <= begin_sample;
end if;
end if;
end process;
-- p_0_reg_166 assign process. --
p_0_reg_166_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ST_st14_fsm_13 = ap_CS_fsm) and not((ap_const_logic_0 = grp_nfa_accept_sample_fu_178_ap_done)) and (or_cond_fu_247_p2 = ap_const_lv1_0) and not((stop_on_first_read_read_fu_104_p2 = ap_const_lv1_0)))) then
p_0_reg_166 <= ap_const_lv32_1;
elsif (((ap_ST_st3_fsm_2 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_i_11_fu_243_p2)))) then
p_0_reg_166 <= c_fu_94;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ST_st14_fsm_13 = ap_CS_fsm) and not((ap_const_logic_0 = grp_nfa_accept_sample_fu_178_ap_done)) and (or_cond_fu_247_p2 = ap_const_lv1_0) and (stop_on_first_read_read_fu_104_p2 = ap_const_lv1_0))) then
c_1_reg_344 <= c_1_fu_252_p2;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_ST_st3_fsm_2 = ap_CS_fsm)) then
c_load_reg_326 <= c_fu_94;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_ST_st13_fsm_12 = ap_CS_fsm)) then
offset_reg_335 <= grp_sample_iterator_get_offset_fu_208_ap_return;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ST_st14_fsm_13 = ap_CS_fsm) and not((ap_const_logic_0 = grp_nfa_accept_sample_fu_178_ap_done)))) then
or_cond_reg_340 <= or_cond_fu_247_p2;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_ST_st2_fsm_1 = ap_CS_fsm)) then
tmp_i_10_reg_321 <= tmp_i_10_fu_235_p2;
tmp_i_reg_316 <= tmp_i_fu_230_p2;
end if;
end if;
end process;
-- the next state (ap_NS_fsm) of the state machine. --
ap_NS_fsm_assign_proc : process (ap_start , ap_CS_fsm , stop_on_first_read_read_fu_104_p2 , or_cond_fu_247_p2 , grp_nfa_accept_sample_fu_178_ap_done , tmp_i_11_fu_243_p2)
begin
case ap_CS_fsm is
when ap_ST_st1_fsm_0 =>
if (not((ap_start = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st2_fsm_1;
else
ap_NS_fsm <= ap_ST_st1_fsm_0;
end if;
when ap_ST_st2_fsm_1 =>
ap_NS_fsm <= ap_ST_st3_fsm_2;
when ap_ST_st3_fsm_2 =>
if (not((ap_const_lv1_0 = tmp_i_11_fu_243_p2))) then
ap_NS_fsm <= ap_ST_st24_fsm_23;
else
ap_NS_fsm <= ap_ST_st4_fsm_3;
end if;
when ap_ST_st4_fsm_3 =>
ap_NS_fsm <= ap_ST_st5_fsm_4;
when ap_ST_st5_fsm_4 =>
ap_NS_fsm <= ap_ST_st6_fsm_5;
when ap_ST_st6_fsm_5 =>
ap_NS_fsm <= ap_ST_st7_fsm_6;
when ap_ST_st7_fsm_6 =>
ap_NS_fsm <= ap_ST_st8_fsm_7;
when ap_ST_st8_fsm_7 =>
ap_NS_fsm <= ap_ST_st9_fsm_8;
when ap_ST_st9_fsm_8 =>
ap_NS_fsm <= ap_ST_st10_fsm_9;
when ap_ST_st10_fsm_9 =>
ap_NS_fsm <= ap_ST_st11_fsm_10;
when ap_ST_st11_fsm_10 =>
ap_NS_fsm <= ap_ST_st12_fsm_11;
when ap_ST_st12_fsm_11 =>
ap_NS_fsm <= ap_ST_st13_fsm_12;
when ap_ST_st13_fsm_12 =>
ap_NS_fsm <= ap_ST_st14_fsm_13;
when ap_ST_st14_fsm_13 =>
if ((not((ap_const_logic_0 = grp_nfa_accept_sample_fu_178_ap_done)) and (or_cond_fu_247_p2 = ap_const_lv1_0) and not((stop_on_first_read_read_fu_104_p2 = ap_const_lv1_0)))) then
ap_NS_fsm <= ap_ST_st24_fsm_23;
elsif ((not((ap_const_logic_0 = grp_nfa_accept_sample_fu_178_ap_done)) and ((stop_on_first_read_read_fu_104_p2 = ap_const_lv1_0) or not((or_cond_fu_247_p2 = ap_const_lv1_0))))) then
ap_NS_fsm <= ap_ST_st15_fsm_14;
else
ap_NS_fsm <= ap_ST_st14_fsm_13;
end if;
when ap_ST_st15_fsm_14 =>
ap_NS_fsm <= ap_ST_st16_fsm_15;
when ap_ST_st16_fsm_15 =>
ap_NS_fsm <= ap_ST_st17_fsm_16;
when ap_ST_st17_fsm_16 =>
ap_NS_fsm <= ap_ST_st18_fsm_17;
when ap_ST_st18_fsm_17 =>
ap_NS_fsm <= ap_ST_st19_fsm_18;
when ap_ST_st19_fsm_18 =>
ap_NS_fsm <= ap_ST_st20_fsm_19;
when ap_ST_st20_fsm_19 =>
ap_NS_fsm <= ap_ST_st21_fsm_20;
when ap_ST_st21_fsm_20 =>
ap_NS_fsm <= ap_ST_st22_fsm_21;
when ap_ST_st22_fsm_21 =>
ap_NS_fsm <= ap_ST_st23_fsm_22;
when ap_ST_st23_fsm_22 =>
ap_NS_fsm <= ap_ST_st2_fsm_1;
when ap_ST_st24_fsm_23 =>
ap_NS_fsm <= ap_ST_st1_fsm_0;
when others =>
ap_NS_fsm <= "XXXXX";
end case;
end process;
-- ap_done assign process. --
ap_done_assign_proc : process(ap_CS_fsm)
begin
if ((ap_ST_st24_fsm_23 = ap_CS_fsm)) then
ap_done <= ap_const_logic_1;
else
ap_done <= ap_const_logic_0;
end if;
end process;
-- ap_idle assign process. --
ap_idle_assign_proc : process(ap_start, ap_CS_fsm)
begin
if ((not((ap_const_logic_1 = ap_start)) and (ap_ST_st1_fsm_0 = ap_CS_fsm))) then
ap_idle <= ap_const_logic_1;
else
ap_idle <= ap_const_logic_0;
end if;
end process;
-- ap_ready assign process. --
ap_ready_assign_proc : process(ap_CS_fsm)
begin
if ((ap_ST_st24_fsm_23 = ap_CS_fsm)) then
ap_ready <= ap_const_logic_1;
else
ap_ready <= ap_const_logic_0;
end if;
end process;
ap_return <= p_0_reg_166;
c_1_fu_252_p2 <= std_logic_vector(unsigned(c_load_reg_326) + unsigned(ap_const_lv32_1));
grp_nfa_accept_sample_fu_178_ap_start <= grp_nfa_accept_sample_fu_178_ap_start_ap_start_reg;
grp_nfa_accept_sample_fu_178_length_r <= sample_length;
grp_nfa_accept_sample_fu_178_nfa_finals_buckets_datain <= nfa_finals_buckets_datain;
grp_nfa_accept_sample_fu_178_nfa_finals_buckets_req_full_n <= nfa_finals_buckets_req_full_n;
grp_nfa_accept_sample_fu_178_nfa_finals_buckets_rsp_empty_n <= nfa_finals_buckets_rsp_empty_n;
grp_nfa_accept_sample_fu_178_nfa_forward_buckets_datain <= nfa_forward_buckets_datain;
grp_nfa_accept_sample_fu_178_nfa_forward_buckets_req_full_n <= nfa_forward_buckets_req_full_n;
grp_nfa_accept_sample_fu_178_nfa_forward_buckets_rsp_empty_n <= nfa_forward_buckets_rsp_empty_n;
grp_nfa_accept_sample_fu_178_nfa_initials_buckets_datain <= nfa_initials_buckets_datain;
grp_nfa_accept_sample_fu_178_nfa_initials_buckets_req_full_n <= nfa_initials_buckets_req_full_n;
grp_nfa_accept_sample_fu_178_nfa_initials_buckets_rsp_empty_n <= nfa_initials_buckets_rsp_empty_n;
grp_nfa_accept_sample_fu_178_nfa_symbols <= nfa_symbols;
grp_nfa_accept_sample_fu_178_sample_datain <= sample_buffer_datain;
grp_nfa_accept_sample_fu_178_sample_req_full_n <= sample_buffer_req_full_n;
grp_nfa_accept_sample_fu_178_sample_rsp_empty_n <= sample_buffer_rsp_empty_n;
grp_nfa_accept_sample_fu_178_tmp_14 <= offset_reg_335;
grp_sample_iterator_get_offset_fu_208_ap_ce <= ap_const_logic_1;
grp_sample_iterator_get_offset_fu_208_ap_start <= grp_sample_iterator_get_offset_fu_208_ap_start_ap_start_reg;
grp_sample_iterator_get_offset_fu_208_i_index <= i_index_reg_146;
grp_sample_iterator_get_offset_fu_208_i_sample <= i_sample_reg_156;
grp_sample_iterator_get_offset_fu_208_indices_begin_datain <= indices_begin_datain;
grp_sample_iterator_get_offset_fu_208_indices_begin_req_full_n <= indices_begin_req_full_n;
grp_sample_iterator_get_offset_fu_208_indices_begin_rsp_empty_n <= indices_begin_rsp_empty_n;
grp_sample_iterator_get_offset_fu_208_indices_samples_datain <= indices_samples_datain;
grp_sample_iterator_get_offset_fu_208_indices_samples_req_full_n <= indices_samples_req_full_n;
grp_sample_iterator_get_offset_fu_208_indices_samples_rsp_empty_n <= indices_samples_rsp_empty_n;
grp_sample_iterator_get_offset_fu_208_indices_stride_datain <= indices_stride_datain;
grp_sample_iterator_get_offset_fu_208_indices_stride_req_full_n <= indices_stride_req_full_n;
grp_sample_iterator_get_offset_fu_208_indices_stride_rsp_empty_n <= indices_stride_rsp_empty_n;
grp_sample_iterator_get_offset_fu_208_sample_buffer_size <= sample_buffer_length;
grp_sample_iterator_get_offset_fu_208_sample_length <= sample_length;
grp_sample_iterator_next_fu_194_ap_ce <= ap_const_logic_1;
grp_sample_iterator_next_fu_194_ap_start <= grp_sample_iterator_next_fu_194_ap_start_ap_start_reg;
grp_sample_iterator_next_fu_194_i_index <= i_index_reg_146;
grp_sample_iterator_next_fu_194_i_sample <= i_sample_reg_156;
grp_sample_iterator_next_fu_194_indices_begin_datain <= indices_begin_datain;
grp_sample_iterator_next_fu_194_indices_begin_req_full_n <= indices_begin_req_full_n;
grp_sample_iterator_next_fu_194_indices_begin_rsp_empty_n <= indices_begin_rsp_empty_n;
grp_sample_iterator_next_fu_194_indices_samples_datain <= indices_samples_datain;
grp_sample_iterator_next_fu_194_indices_samples_req_full_n <= indices_samples_req_full_n;
grp_sample_iterator_next_fu_194_indices_samples_rsp_empty_n <= indices_samples_rsp_empty_n;
grp_sample_iterator_next_fu_194_indices_stride_datain <= indices_stride_datain;
grp_sample_iterator_next_fu_194_indices_stride_req_full_n <= indices_stride_req_full_n;
grp_sample_iterator_next_fu_194_indices_stride_rsp_empty_n <= indices_stride_rsp_empty_n;
-- indices_begin_address assign process. --
indices_begin_address_assign_proc : process(ap_CS_fsm, grp_sample_iterator_next_fu_194_indices_begin_address, grp_sample_iterator_get_offset_fu_208_indices_begin_address)
begin
if (((ap_ST_st13_fsm_12 = ap_CS_fsm) or (ap_ST_st4_fsm_3 = ap_CS_fsm) or (ap_ST_st5_fsm_4 = ap_CS_fsm) or (ap_ST_st6_fsm_5 = ap_CS_fsm) or (ap_ST_st7_fsm_6 = ap_CS_fsm) or (ap_ST_st8_fsm_7 = ap_CS_fsm) or (ap_ST_st9_fsm_8 = ap_CS_fsm) or (ap_ST_st10_fsm_9 = ap_CS_fsm) or (ap_ST_st11_fsm_10 = ap_CS_fsm) or (ap_ST_st12_fsm_11 = ap_CS_fsm))) then
indices_begin_address <= grp_sample_iterator_get_offset_fu_208_indices_begin_address;
elsif (((ap_ST_st23_fsm_22 = ap_CS_fsm) or (ap_ST_st15_fsm_14 = ap_CS_fsm) or (ap_ST_st16_fsm_15 = ap_CS_fsm) or (ap_ST_st17_fsm_16 = ap_CS_fsm) or (ap_ST_st18_fsm_17 = ap_CS_fsm) or (ap_ST_st19_fsm_18 = ap_CS_fsm) or (ap_ST_st20_fsm_19 = ap_CS_fsm) or (ap_ST_st21_fsm_20 = ap_CS_fsm) or (ap_ST_st22_fsm_21 = ap_CS_fsm))) then
indices_begin_address <= grp_sample_iterator_next_fu_194_indices_begin_address;
else
indices_begin_address <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
-- indices_begin_dataout assign process. --
indices_begin_dataout_assign_proc : process(ap_CS_fsm, grp_sample_iterator_next_fu_194_indices_begin_dataout, grp_sample_iterator_get_offset_fu_208_indices_begin_dataout)
begin
if (((ap_ST_st13_fsm_12 = ap_CS_fsm) or (ap_ST_st4_fsm_3 = ap_CS_fsm) or (ap_ST_st5_fsm_4 = ap_CS_fsm) or (ap_ST_st6_fsm_5 = ap_CS_fsm) or (ap_ST_st7_fsm_6 = ap_CS_fsm) or (ap_ST_st8_fsm_7 = ap_CS_fsm) or (ap_ST_st9_fsm_8 = ap_CS_fsm) or (ap_ST_st10_fsm_9 = ap_CS_fsm) or (ap_ST_st11_fsm_10 = ap_CS_fsm) or (ap_ST_st12_fsm_11 = ap_CS_fsm))) then
indices_begin_dataout <= grp_sample_iterator_get_offset_fu_208_indices_begin_dataout;
elsif (((ap_ST_st23_fsm_22 = ap_CS_fsm) or (ap_ST_st15_fsm_14 = ap_CS_fsm) or (ap_ST_st16_fsm_15 = ap_CS_fsm) or (ap_ST_st17_fsm_16 = ap_CS_fsm) or (ap_ST_st18_fsm_17 = ap_CS_fsm) or (ap_ST_st19_fsm_18 = ap_CS_fsm) or (ap_ST_st20_fsm_19 = ap_CS_fsm) or (ap_ST_st21_fsm_20 = ap_CS_fsm) or (ap_ST_st22_fsm_21 = ap_CS_fsm))) then
indices_begin_dataout <= grp_sample_iterator_next_fu_194_indices_begin_dataout;
else
indices_begin_dataout <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
-- indices_begin_req_din assign process. --
indices_begin_req_din_assign_proc : process(ap_CS_fsm, grp_sample_iterator_next_fu_194_indices_begin_req_din, grp_sample_iterator_get_offset_fu_208_indices_begin_req_din)
begin
if (((ap_ST_st13_fsm_12 = ap_CS_fsm) or (ap_ST_st4_fsm_3 = ap_CS_fsm) or (ap_ST_st5_fsm_4 = ap_CS_fsm) or (ap_ST_st6_fsm_5 = ap_CS_fsm) or (ap_ST_st7_fsm_6 = ap_CS_fsm) or (ap_ST_st8_fsm_7 = ap_CS_fsm) or (ap_ST_st9_fsm_8 = ap_CS_fsm) or (ap_ST_st10_fsm_9 = ap_CS_fsm) or (ap_ST_st11_fsm_10 = ap_CS_fsm) or (ap_ST_st12_fsm_11 = ap_CS_fsm))) then
indices_begin_req_din <= grp_sample_iterator_get_offset_fu_208_indices_begin_req_din;
elsif (((ap_ST_st23_fsm_22 = ap_CS_fsm) or (ap_ST_st15_fsm_14 = ap_CS_fsm) or (ap_ST_st16_fsm_15 = ap_CS_fsm) or (ap_ST_st17_fsm_16 = ap_CS_fsm) or (ap_ST_st18_fsm_17 = ap_CS_fsm) or (ap_ST_st19_fsm_18 = ap_CS_fsm) or (ap_ST_st20_fsm_19 = ap_CS_fsm) or (ap_ST_st21_fsm_20 = ap_CS_fsm) or (ap_ST_st22_fsm_21 = ap_CS_fsm))) then
indices_begin_req_din <= grp_sample_iterator_next_fu_194_indices_begin_req_din;
else
indices_begin_req_din <= 'X';
end if;
end process;
-- indices_begin_req_write assign process. --
indices_begin_req_write_assign_proc : process(ap_CS_fsm, grp_sample_iterator_next_fu_194_indices_begin_req_write, grp_sample_iterator_get_offset_fu_208_indices_begin_req_write)
begin
if (((ap_ST_st13_fsm_12 = ap_CS_fsm) or (ap_ST_st4_fsm_3 = ap_CS_fsm) or (ap_ST_st5_fsm_4 = ap_CS_fsm) or (ap_ST_st6_fsm_5 = ap_CS_fsm) or (ap_ST_st7_fsm_6 = ap_CS_fsm) or (ap_ST_st8_fsm_7 = ap_CS_fsm) or (ap_ST_st9_fsm_8 = ap_CS_fsm) or (ap_ST_st10_fsm_9 = ap_CS_fsm) or (ap_ST_st11_fsm_10 = ap_CS_fsm) or (ap_ST_st12_fsm_11 = ap_CS_fsm))) then
indices_begin_req_write <= grp_sample_iterator_get_offset_fu_208_indices_begin_req_write;
elsif (((ap_ST_st23_fsm_22 = ap_CS_fsm) or (ap_ST_st15_fsm_14 = ap_CS_fsm) or (ap_ST_st16_fsm_15 = ap_CS_fsm) or (ap_ST_st17_fsm_16 = ap_CS_fsm) or (ap_ST_st18_fsm_17 = ap_CS_fsm) or (ap_ST_st19_fsm_18 = ap_CS_fsm) or (ap_ST_st20_fsm_19 = ap_CS_fsm) or (ap_ST_st21_fsm_20 = ap_CS_fsm) or (ap_ST_st22_fsm_21 = ap_CS_fsm))) then
indices_begin_req_write <= grp_sample_iterator_next_fu_194_indices_begin_req_write;
else
indices_begin_req_write <= 'X';
end if;
end process;
-- indices_begin_rsp_read assign process. --
indices_begin_rsp_read_assign_proc : process(ap_CS_fsm, grp_sample_iterator_next_fu_194_indices_begin_rsp_read, grp_sample_iterator_get_offset_fu_208_indices_begin_rsp_read)
begin
if (((ap_ST_st13_fsm_12 = ap_CS_fsm) or (ap_ST_st4_fsm_3 = ap_CS_fsm) or (ap_ST_st5_fsm_4 = ap_CS_fsm) or (ap_ST_st6_fsm_5 = ap_CS_fsm) or (ap_ST_st7_fsm_6 = ap_CS_fsm) or (ap_ST_st8_fsm_7 = ap_CS_fsm) or (ap_ST_st9_fsm_8 = ap_CS_fsm) or (ap_ST_st10_fsm_9 = ap_CS_fsm) or (ap_ST_st11_fsm_10 = ap_CS_fsm) or (ap_ST_st12_fsm_11 = ap_CS_fsm))) then
indices_begin_rsp_read <= grp_sample_iterator_get_offset_fu_208_indices_begin_rsp_read;
elsif (((ap_ST_st23_fsm_22 = ap_CS_fsm) or (ap_ST_st15_fsm_14 = ap_CS_fsm) or (ap_ST_st16_fsm_15 = ap_CS_fsm) or (ap_ST_st17_fsm_16 = ap_CS_fsm) or (ap_ST_st18_fsm_17 = ap_CS_fsm) or (ap_ST_st19_fsm_18 = ap_CS_fsm) or (ap_ST_st20_fsm_19 = ap_CS_fsm) or (ap_ST_st21_fsm_20 = ap_CS_fsm) or (ap_ST_st22_fsm_21 = ap_CS_fsm))) then
indices_begin_rsp_read <= grp_sample_iterator_next_fu_194_indices_begin_rsp_read;
else
indices_begin_rsp_read <= 'X';
end if;
end process;
-- indices_begin_size assign process. --
indices_begin_size_assign_proc : process(ap_CS_fsm, grp_sample_iterator_next_fu_194_indices_begin_size, grp_sample_iterator_get_offset_fu_208_indices_begin_size)
begin
if (((ap_ST_st13_fsm_12 = ap_CS_fsm) or (ap_ST_st4_fsm_3 = ap_CS_fsm) or (ap_ST_st5_fsm_4 = ap_CS_fsm) or (ap_ST_st6_fsm_5 = ap_CS_fsm) or (ap_ST_st7_fsm_6 = ap_CS_fsm) or (ap_ST_st8_fsm_7 = ap_CS_fsm) or (ap_ST_st9_fsm_8 = ap_CS_fsm) or (ap_ST_st10_fsm_9 = ap_CS_fsm) or (ap_ST_st11_fsm_10 = ap_CS_fsm) or (ap_ST_st12_fsm_11 = ap_CS_fsm))) then
indices_begin_size <= grp_sample_iterator_get_offset_fu_208_indices_begin_size;
elsif (((ap_ST_st23_fsm_22 = ap_CS_fsm) or (ap_ST_st15_fsm_14 = ap_CS_fsm) or (ap_ST_st16_fsm_15 = ap_CS_fsm) or (ap_ST_st17_fsm_16 = ap_CS_fsm) or (ap_ST_st18_fsm_17 = ap_CS_fsm) or (ap_ST_st19_fsm_18 = ap_CS_fsm) or (ap_ST_st20_fsm_19 = ap_CS_fsm) or (ap_ST_st21_fsm_20 = ap_CS_fsm) or (ap_ST_st22_fsm_21 = ap_CS_fsm))) then
indices_begin_size <= grp_sample_iterator_next_fu_194_indices_begin_size;
else
indices_begin_size <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
-- indices_samples_address assign process. --
indices_samples_address_assign_proc : process(ap_CS_fsm, grp_sample_iterator_next_fu_194_indices_samples_address, grp_sample_iterator_get_offset_fu_208_indices_samples_address)
begin
if (((ap_ST_st13_fsm_12 = ap_CS_fsm) or (ap_ST_st4_fsm_3 = ap_CS_fsm) or (ap_ST_st5_fsm_4 = ap_CS_fsm) or (ap_ST_st6_fsm_5 = ap_CS_fsm) or (ap_ST_st7_fsm_6 = ap_CS_fsm) or (ap_ST_st8_fsm_7 = ap_CS_fsm) or (ap_ST_st9_fsm_8 = ap_CS_fsm) or (ap_ST_st10_fsm_9 = ap_CS_fsm) or (ap_ST_st11_fsm_10 = ap_CS_fsm) or (ap_ST_st12_fsm_11 = ap_CS_fsm))) then
indices_samples_address <= grp_sample_iterator_get_offset_fu_208_indices_samples_address;
elsif (((ap_ST_st23_fsm_22 = ap_CS_fsm) or (ap_ST_st15_fsm_14 = ap_CS_fsm) or (ap_ST_st16_fsm_15 = ap_CS_fsm) or (ap_ST_st17_fsm_16 = ap_CS_fsm) or (ap_ST_st18_fsm_17 = ap_CS_fsm) or (ap_ST_st19_fsm_18 = ap_CS_fsm) or (ap_ST_st20_fsm_19 = ap_CS_fsm) or (ap_ST_st21_fsm_20 = ap_CS_fsm) or (ap_ST_st22_fsm_21 = ap_CS_fsm))) then
indices_samples_address <= grp_sample_iterator_next_fu_194_indices_samples_address;
else
indices_samples_address <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
-- indices_samples_dataout assign process. --
indices_samples_dataout_assign_proc : process(ap_CS_fsm, grp_sample_iterator_next_fu_194_indices_samples_dataout, grp_sample_iterator_get_offset_fu_208_indices_samples_dataout)
begin
if (((ap_ST_st13_fsm_12 = ap_CS_fsm) or (ap_ST_st4_fsm_3 = ap_CS_fsm) or (ap_ST_st5_fsm_4 = ap_CS_fsm) or (ap_ST_st6_fsm_5 = ap_CS_fsm) or (ap_ST_st7_fsm_6 = ap_CS_fsm) or (ap_ST_st8_fsm_7 = ap_CS_fsm) or (ap_ST_st9_fsm_8 = ap_CS_fsm) or (ap_ST_st10_fsm_9 = ap_CS_fsm) or (ap_ST_st11_fsm_10 = ap_CS_fsm) or (ap_ST_st12_fsm_11 = ap_CS_fsm))) then
indices_samples_dataout <= grp_sample_iterator_get_offset_fu_208_indices_samples_dataout;
elsif (((ap_ST_st23_fsm_22 = ap_CS_fsm) or (ap_ST_st15_fsm_14 = ap_CS_fsm) or (ap_ST_st16_fsm_15 = ap_CS_fsm) or (ap_ST_st17_fsm_16 = ap_CS_fsm) or (ap_ST_st18_fsm_17 = ap_CS_fsm) or (ap_ST_st19_fsm_18 = ap_CS_fsm) or (ap_ST_st20_fsm_19 = ap_CS_fsm) or (ap_ST_st21_fsm_20 = ap_CS_fsm) or (ap_ST_st22_fsm_21 = ap_CS_fsm))) then
indices_samples_dataout <= grp_sample_iterator_next_fu_194_indices_samples_dataout;
else
indices_samples_dataout <= "XXXXXXXXXXXXXXXX";
end if;
end process;
-- indices_samples_req_din assign process. --
indices_samples_req_din_assign_proc : process(ap_CS_fsm, grp_sample_iterator_next_fu_194_indices_samples_req_din, grp_sample_iterator_get_offset_fu_208_indices_samples_req_din)
begin
if (((ap_ST_st13_fsm_12 = ap_CS_fsm) or (ap_ST_st4_fsm_3 = ap_CS_fsm) or (ap_ST_st5_fsm_4 = ap_CS_fsm) or (ap_ST_st6_fsm_5 = ap_CS_fsm) or (ap_ST_st7_fsm_6 = ap_CS_fsm) or (ap_ST_st8_fsm_7 = ap_CS_fsm) or (ap_ST_st9_fsm_8 = ap_CS_fsm) or (ap_ST_st10_fsm_9 = ap_CS_fsm) or (ap_ST_st11_fsm_10 = ap_CS_fsm) or (ap_ST_st12_fsm_11 = ap_CS_fsm))) then
indices_samples_req_din <= grp_sample_iterator_get_offset_fu_208_indices_samples_req_din;
elsif (((ap_ST_st23_fsm_22 = ap_CS_fsm) or (ap_ST_st15_fsm_14 = ap_CS_fsm) or (ap_ST_st16_fsm_15 = ap_CS_fsm) or (ap_ST_st17_fsm_16 = ap_CS_fsm) or (ap_ST_st18_fsm_17 = ap_CS_fsm) or (ap_ST_st19_fsm_18 = ap_CS_fsm) or (ap_ST_st20_fsm_19 = ap_CS_fsm) or (ap_ST_st21_fsm_20 = ap_CS_fsm) or (ap_ST_st22_fsm_21 = ap_CS_fsm))) then
indices_samples_req_din <= grp_sample_iterator_next_fu_194_indices_samples_req_din;
else
indices_samples_req_din <= 'X';
end if;
end process;
-- indices_samples_req_write assign process. --
indices_samples_req_write_assign_proc : process(ap_CS_fsm, grp_sample_iterator_next_fu_194_indices_samples_req_write, grp_sample_iterator_get_offset_fu_208_indices_samples_req_write)
begin
if (((ap_ST_st13_fsm_12 = ap_CS_fsm) or (ap_ST_st4_fsm_3 = ap_CS_fsm) or (ap_ST_st5_fsm_4 = ap_CS_fsm) or (ap_ST_st6_fsm_5 = ap_CS_fsm) or (ap_ST_st7_fsm_6 = ap_CS_fsm) or (ap_ST_st8_fsm_7 = ap_CS_fsm) or (ap_ST_st9_fsm_8 = ap_CS_fsm) or (ap_ST_st10_fsm_9 = ap_CS_fsm) or (ap_ST_st11_fsm_10 = ap_CS_fsm) or (ap_ST_st12_fsm_11 = ap_CS_fsm))) then
indices_samples_req_write <= grp_sample_iterator_get_offset_fu_208_indices_samples_req_write;
elsif (((ap_ST_st23_fsm_22 = ap_CS_fsm) or (ap_ST_st15_fsm_14 = ap_CS_fsm) or (ap_ST_st16_fsm_15 = ap_CS_fsm) or (ap_ST_st17_fsm_16 = ap_CS_fsm) or (ap_ST_st18_fsm_17 = ap_CS_fsm) or (ap_ST_st19_fsm_18 = ap_CS_fsm) or (ap_ST_st20_fsm_19 = ap_CS_fsm) or (ap_ST_st21_fsm_20 = ap_CS_fsm) or (ap_ST_st22_fsm_21 = ap_CS_fsm))) then
indices_samples_req_write <= grp_sample_iterator_next_fu_194_indices_samples_req_write;
else
indices_samples_req_write <= 'X';
end if;
end process;
-- indices_samples_rsp_read assign process. --
indices_samples_rsp_read_assign_proc : process(ap_CS_fsm, grp_sample_iterator_next_fu_194_indices_samples_rsp_read, grp_sample_iterator_get_offset_fu_208_indices_samples_rsp_read)
begin
if (((ap_ST_st13_fsm_12 = ap_CS_fsm) or (ap_ST_st4_fsm_3 = ap_CS_fsm) or (ap_ST_st5_fsm_4 = ap_CS_fsm) or (ap_ST_st6_fsm_5 = ap_CS_fsm) or (ap_ST_st7_fsm_6 = ap_CS_fsm) or (ap_ST_st8_fsm_7 = ap_CS_fsm) or (ap_ST_st9_fsm_8 = ap_CS_fsm) or (ap_ST_st10_fsm_9 = ap_CS_fsm) or (ap_ST_st11_fsm_10 = ap_CS_fsm) or (ap_ST_st12_fsm_11 = ap_CS_fsm))) then
indices_samples_rsp_read <= grp_sample_iterator_get_offset_fu_208_indices_samples_rsp_read;
elsif (((ap_ST_st23_fsm_22 = ap_CS_fsm) or (ap_ST_st15_fsm_14 = ap_CS_fsm) or (ap_ST_st16_fsm_15 = ap_CS_fsm) or (ap_ST_st17_fsm_16 = ap_CS_fsm) or (ap_ST_st18_fsm_17 = ap_CS_fsm) or (ap_ST_st19_fsm_18 = ap_CS_fsm) or (ap_ST_st20_fsm_19 = ap_CS_fsm) or (ap_ST_st21_fsm_20 = ap_CS_fsm) or (ap_ST_st22_fsm_21 = ap_CS_fsm))) then
indices_samples_rsp_read <= grp_sample_iterator_next_fu_194_indices_samples_rsp_read;
else
indices_samples_rsp_read <= 'X';
end if;
end process;
-- indices_samples_size assign process. --
indices_samples_size_assign_proc : process(ap_CS_fsm, grp_sample_iterator_next_fu_194_indices_samples_size, grp_sample_iterator_get_offset_fu_208_indices_samples_size)
begin
if (((ap_ST_st13_fsm_12 = ap_CS_fsm) or (ap_ST_st4_fsm_3 = ap_CS_fsm) or (ap_ST_st5_fsm_4 = ap_CS_fsm) or (ap_ST_st6_fsm_5 = ap_CS_fsm) or (ap_ST_st7_fsm_6 = ap_CS_fsm) or (ap_ST_st8_fsm_7 = ap_CS_fsm) or (ap_ST_st9_fsm_8 = ap_CS_fsm) or (ap_ST_st10_fsm_9 = ap_CS_fsm) or (ap_ST_st11_fsm_10 = ap_CS_fsm) or (ap_ST_st12_fsm_11 = ap_CS_fsm))) then
indices_samples_size <= grp_sample_iterator_get_offset_fu_208_indices_samples_size;
elsif (((ap_ST_st23_fsm_22 = ap_CS_fsm) or (ap_ST_st15_fsm_14 = ap_CS_fsm) or (ap_ST_st16_fsm_15 = ap_CS_fsm) or (ap_ST_st17_fsm_16 = ap_CS_fsm) or (ap_ST_st18_fsm_17 = ap_CS_fsm) or (ap_ST_st19_fsm_18 = ap_CS_fsm) or (ap_ST_st20_fsm_19 = ap_CS_fsm) or (ap_ST_st21_fsm_20 = ap_CS_fsm) or (ap_ST_st22_fsm_21 = ap_CS_fsm))) then
indices_samples_size <= grp_sample_iterator_next_fu_194_indices_samples_size;
else
indices_samples_size <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
-- indices_stride_address assign process. --
indices_stride_address_assign_proc : process(ap_CS_fsm, grp_sample_iterator_next_fu_194_indices_stride_address, grp_sample_iterator_get_offset_fu_208_indices_stride_address)
begin
if (((ap_ST_st13_fsm_12 = ap_CS_fsm) or (ap_ST_st4_fsm_3 = ap_CS_fsm) or (ap_ST_st5_fsm_4 = ap_CS_fsm) or (ap_ST_st6_fsm_5 = ap_CS_fsm) or (ap_ST_st7_fsm_6 = ap_CS_fsm) or (ap_ST_st8_fsm_7 = ap_CS_fsm) or (ap_ST_st9_fsm_8 = ap_CS_fsm) or (ap_ST_st10_fsm_9 = ap_CS_fsm) or (ap_ST_st11_fsm_10 = ap_CS_fsm) or (ap_ST_st12_fsm_11 = ap_CS_fsm))) then
indices_stride_address <= grp_sample_iterator_get_offset_fu_208_indices_stride_address;
elsif (((ap_ST_st23_fsm_22 = ap_CS_fsm) or (ap_ST_st15_fsm_14 = ap_CS_fsm) or (ap_ST_st16_fsm_15 = ap_CS_fsm) or (ap_ST_st17_fsm_16 = ap_CS_fsm) or (ap_ST_st18_fsm_17 = ap_CS_fsm) or (ap_ST_st19_fsm_18 = ap_CS_fsm) or (ap_ST_st20_fsm_19 = ap_CS_fsm) or (ap_ST_st21_fsm_20 = ap_CS_fsm) or (ap_ST_st22_fsm_21 = ap_CS_fsm))) then
indices_stride_address <= grp_sample_iterator_next_fu_194_indices_stride_address;
else
indices_stride_address <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
-- indices_stride_dataout assign process. --
indices_stride_dataout_assign_proc : process(ap_CS_fsm, grp_sample_iterator_next_fu_194_indices_stride_dataout, grp_sample_iterator_get_offset_fu_208_indices_stride_dataout)
begin
if (((ap_ST_st13_fsm_12 = ap_CS_fsm) or (ap_ST_st4_fsm_3 = ap_CS_fsm) or (ap_ST_st5_fsm_4 = ap_CS_fsm) or (ap_ST_st6_fsm_5 = ap_CS_fsm) or (ap_ST_st7_fsm_6 = ap_CS_fsm) or (ap_ST_st8_fsm_7 = ap_CS_fsm) or (ap_ST_st9_fsm_8 = ap_CS_fsm) or (ap_ST_st10_fsm_9 = ap_CS_fsm) or (ap_ST_st11_fsm_10 = ap_CS_fsm) or (ap_ST_st12_fsm_11 = ap_CS_fsm))) then
indices_stride_dataout <= grp_sample_iterator_get_offset_fu_208_indices_stride_dataout;
elsif (((ap_ST_st23_fsm_22 = ap_CS_fsm) or (ap_ST_st15_fsm_14 = ap_CS_fsm) or (ap_ST_st16_fsm_15 = ap_CS_fsm) or (ap_ST_st17_fsm_16 = ap_CS_fsm) or (ap_ST_st18_fsm_17 = ap_CS_fsm) or (ap_ST_st19_fsm_18 = ap_CS_fsm) or (ap_ST_st20_fsm_19 = ap_CS_fsm) or (ap_ST_st21_fsm_20 = ap_CS_fsm) or (ap_ST_st22_fsm_21 = ap_CS_fsm))) then
indices_stride_dataout <= grp_sample_iterator_next_fu_194_indices_stride_dataout;
else
indices_stride_dataout <= "XXXXXXXX";
end if;
end process;
-- indices_stride_req_din assign process. --
indices_stride_req_din_assign_proc : process(ap_CS_fsm, grp_sample_iterator_next_fu_194_indices_stride_req_din, grp_sample_iterator_get_offset_fu_208_indices_stride_req_din)
begin
if (((ap_ST_st13_fsm_12 = ap_CS_fsm) or (ap_ST_st4_fsm_3 = ap_CS_fsm) or (ap_ST_st5_fsm_4 = ap_CS_fsm) or (ap_ST_st6_fsm_5 = ap_CS_fsm) or (ap_ST_st7_fsm_6 = ap_CS_fsm) or (ap_ST_st8_fsm_7 = ap_CS_fsm) or (ap_ST_st9_fsm_8 = ap_CS_fsm) or (ap_ST_st10_fsm_9 = ap_CS_fsm) or (ap_ST_st11_fsm_10 = ap_CS_fsm) or (ap_ST_st12_fsm_11 = ap_CS_fsm))) then
indices_stride_req_din <= grp_sample_iterator_get_offset_fu_208_indices_stride_req_din;
elsif (((ap_ST_st23_fsm_22 = ap_CS_fsm) or (ap_ST_st15_fsm_14 = ap_CS_fsm) or (ap_ST_st16_fsm_15 = ap_CS_fsm) or (ap_ST_st17_fsm_16 = ap_CS_fsm) or (ap_ST_st18_fsm_17 = ap_CS_fsm) or (ap_ST_st19_fsm_18 = ap_CS_fsm) or (ap_ST_st20_fsm_19 = ap_CS_fsm) or (ap_ST_st21_fsm_20 = ap_CS_fsm) or (ap_ST_st22_fsm_21 = ap_CS_fsm))) then
indices_stride_req_din <= grp_sample_iterator_next_fu_194_indices_stride_req_din;
else
indices_stride_req_din <= 'X';
end if;
end process;
-- indices_stride_req_write assign process. --
indices_stride_req_write_assign_proc : process(ap_CS_fsm, grp_sample_iterator_next_fu_194_indices_stride_req_write, grp_sample_iterator_get_offset_fu_208_indices_stride_req_write)
begin
if (((ap_ST_st13_fsm_12 = ap_CS_fsm) or (ap_ST_st4_fsm_3 = ap_CS_fsm) or (ap_ST_st5_fsm_4 = ap_CS_fsm) or (ap_ST_st6_fsm_5 = ap_CS_fsm) or (ap_ST_st7_fsm_6 = ap_CS_fsm) or (ap_ST_st8_fsm_7 = ap_CS_fsm) or (ap_ST_st9_fsm_8 = ap_CS_fsm) or (ap_ST_st10_fsm_9 = ap_CS_fsm) or (ap_ST_st11_fsm_10 = ap_CS_fsm) or (ap_ST_st12_fsm_11 = ap_CS_fsm))) then
indices_stride_req_write <= grp_sample_iterator_get_offset_fu_208_indices_stride_req_write;
elsif (((ap_ST_st23_fsm_22 = ap_CS_fsm) or (ap_ST_st15_fsm_14 = ap_CS_fsm) or (ap_ST_st16_fsm_15 = ap_CS_fsm) or (ap_ST_st17_fsm_16 = ap_CS_fsm) or (ap_ST_st18_fsm_17 = ap_CS_fsm) or (ap_ST_st19_fsm_18 = ap_CS_fsm) or (ap_ST_st20_fsm_19 = ap_CS_fsm) or (ap_ST_st21_fsm_20 = ap_CS_fsm) or (ap_ST_st22_fsm_21 = ap_CS_fsm))) then
indices_stride_req_write <= grp_sample_iterator_next_fu_194_indices_stride_req_write;
else
indices_stride_req_write <= 'X';
end if;
end process;
-- indices_stride_rsp_read assign process. --
indices_stride_rsp_read_assign_proc : process(ap_CS_fsm, grp_sample_iterator_next_fu_194_indices_stride_rsp_read, grp_sample_iterator_get_offset_fu_208_indices_stride_rsp_read)
begin
if (((ap_ST_st13_fsm_12 = ap_CS_fsm) or (ap_ST_st4_fsm_3 = ap_CS_fsm) or (ap_ST_st5_fsm_4 = ap_CS_fsm) or (ap_ST_st6_fsm_5 = ap_CS_fsm) or (ap_ST_st7_fsm_6 = ap_CS_fsm) or (ap_ST_st8_fsm_7 = ap_CS_fsm) or (ap_ST_st9_fsm_8 = ap_CS_fsm) or (ap_ST_st10_fsm_9 = ap_CS_fsm) or (ap_ST_st11_fsm_10 = ap_CS_fsm) or (ap_ST_st12_fsm_11 = ap_CS_fsm))) then
indices_stride_rsp_read <= grp_sample_iterator_get_offset_fu_208_indices_stride_rsp_read;
elsif (((ap_ST_st23_fsm_22 = ap_CS_fsm) or (ap_ST_st15_fsm_14 = ap_CS_fsm) or (ap_ST_st16_fsm_15 = ap_CS_fsm) or (ap_ST_st17_fsm_16 = ap_CS_fsm) or (ap_ST_st18_fsm_17 = ap_CS_fsm) or (ap_ST_st19_fsm_18 = ap_CS_fsm) or (ap_ST_st20_fsm_19 = ap_CS_fsm) or (ap_ST_st21_fsm_20 = ap_CS_fsm) or (ap_ST_st22_fsm_21 = ap_CS_fsm))) then
indices_stride_rsp_read <= grp_sample_iterator_next_fu_194_indices_stride_rsp_read;
else
indices_stride_rsp_read <= 'X';
end if;
end process;
-- indices_stride_size assign process. --
indices_stride_size_assign_proc : process(ap_CS_fsm, grp_sample_iterator_next_fu_194_indices_stride_size, grp_sample_iterator_get_offset_fu_208_indices_stride_size)
begin
if (((ap_ST_st13_fsm_12 = ap_CS_fsm) or (ap_ST_st4_fsm_3 = ap_CS_fsm) or (ap_ST_st5_fsm_4 = ap_CS_fsm) or (ap_ST_st6_fsm_5 = ap_CS_fsm) or (ap_ST_st7_fsm_6 = ap_CS_fsm) or (ap_ST_st8_fsm_7 = ap_CS_fsm) or (ap_ST_st9_fsm_8 = ap_CS_fsm) or (ap_ST_st10_fsm_9 = ap_CS_fsm) or (ap_ST_st11_fsm_10 = ap_CS_fsm) or (ap_ST_st12_fsm_11 = ap_CS_fsm))) then
indices_stride_size <= grp_sample_iterator_get_offset_fu_208_indices_stride_size;
elsif (((ap_ST_st23_fsm_22 = ap_CS_fsm) or (ap_ST_st15_fsm_14 = ap_CS_fsm) or (ap_ST_st16_fsm_15 = ap_CS_fsm) or (ap_ST_st17_fsm_16 = ap_CS_fsm) or (ap_ST_st18_fsm_17 = ap_CS_fsm) or (ap_ST_st19_fsm_18 = ap_CS_fsm) or (ap_ST_st20_fsm_19 = ap_CS_fsm) or (ap_ST_st21_fsm_20 = ap_CS_fsm) or (ap_ST_st22_fsm_21 = ap_CS_fsm))) then
indices_stride_size <= grp_sample_iterator_next_fu_194_indices_stride_size;
else
indices_stride_size <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
nfa_finals_buckets_address <= grp_nfa_accept_sample_fu_178_nfa_finals_buckets_address;
nfa_finals_buckets_dataout <= grp_nfa_accept_sample_fu_178_nfa_finals_buckets_dataout;
nfa_finals_buckets_req_din <= grp_nfa_accept_sample_fu_178_nfa_finals_buckets_req_din;
nfa_finals_buckets_req_write <= grp_nfa_accept_sample_fu_178_nfa_finals_buckets_req_write;
nfa_finals_buckets_rsp_read <= grp_nfa_accept_sample_fu_178_nfa_finals_buckets_rsp_read;
nfa_finals_buckets_size <= grp_nfa_accept_sample_fu_178_nfa_finals_buckets_size;
nfa_forward_buckets_address <= grp_nfa_accept_sample_fu_178_nfa_forward_buckets_address;
nfa_forward_buckets_dataout <= grp_nfa_accept_sample_fu_178_nfa_forward_buckets_dataout;
nfa_forward_buckets_req_din <= grp_nfa_accept_sample_fu_178_nfa_forward_buckets_req_din;
nfa_forward_buckets_req_write <= grp_nfa_accept_sample_fu_178_nfa_forward_buckets_req_write;
nfa_forward_buckets_rsp_read <= grp_nfa_accept_sample_fu_178_nfa_forward_buckets_rsp_read;
nfa_forward_buckets_size <= grp_nfa_accept_sample_fu_178_nfa_forward_buckets_size;
nfa_initials_buckets_address <= grp_nfa_accept_sample_fu_178_nfa_initials_buckets_address;
nfa_initials_buckets_dataout <= grp_nfa_accept_sample_fu_178_nfa_initials_buckets_dataout;
nfa_initials_buckets_req_din <= grp_nfa_accept_sample_fu_178_nfa_initials_buckets_req_din;
nfa_initials_buckets_req_write <= grp_nfa_accept_sample_fu_178_nfa_initials_buckets_req_write;
nfa_initials_buckets_rsp_read <= grp_nfa_accept_sample_fu_178_nfa_initials_buckets_rsp_read;
nfa_initials_buckets_size <= grp_nfa_accept_sample_fu_178_nfa_initials_buckets_size;
or_cond_fu_247_p2 <= (grp_nfa_accept_sample_fu_178_ap_return xor accept);
sample_buffer_address <= grp_nfa_accept_sample_fu_178_sample_address;
sample_buffer_dataout <= grp_nfa_accept_sample_fu_178_sample_dataout;
sample_buffer_req_din <= grp_nfa_accept_sample_fu_178_sample_req_din;
sample_buffer_req_write <= grp_nfa_accept_sample_fu_178_sample_req_write;
sample_buffer_rsp_read <= grp_nfa_accept_sample_fu_178_sample_rsp_read;
sample_buffer_size <= grp_nfa_accept_sample_fu_178_sample_size;
stop_on_first_read_read_fu_104_p2 <= stop_on_first;
tmp_i_10_fu_235_p2 <= "1" when (i_index_reg_146 = end_index) else "0";
tmp_i_11_fu_243_p2 <= (tmp_i_reg_316 and tmp_i_10_reg_321);
tmp_i_fu_230_p2 <= "1" when (i_sample_reg_156 = end_sample) else "0";
end behav;
| lgpl-3.0 | c6845a180a0ea664709b7c0a95b670a8 | 0.651266 | 2.730836 | false | false | false | false |
grwlf/vsim | vhdl_ct/ct00151.vhd | 1 | 16,749 | -- NEED RESULT: ARCH00151.P1: Multi inertial transactions occurred on signal asg with selected name on LHS passed
-- NEED RESULT: ARCH00151.P2: Multi inertial transactions occurred on signal asg with selected name on LHS failed
-- NEED RESULT: ARCH00151.P3: Multi inertial transactions occurred on signal asg with selected name on LHS failed
-- NEED RESULT: ARCH00151: One inertial transaction occurred on signal asg with selected name on LHS passed
-- NEED RESULT: ARCH00151: One inertial transaction occurred on signal asg with selected name on LHS failed
-- NEED RESULT: ARCH00151: One inertial transaction occurred on signal asg with selected name on LHS failed
-- NEED RESULT: ARCH00151: Old transactions were removed on signal asg with selected name on LHS failed
-- NEED RESULT: ARCH00151: Old transactions were removed on signal asg with selected name on LHS failed
-- NEED RESULT: ARCH00151: One inertial transaction occurred on signal asg with selected name on LHS failed
-- NEED RESULT: ARCH00151: One inertial transaction occurred on signal asg with selected name on LHS failed
-- NEED RESULT: ARCH00151: Inertial semantics check on a signal asg with selected name on LHS failed
-- NEED RESULT: ARCH00151: Inertial semantics check on a signal asg with selected name on LHS failed
-- NEED RESULT: ARCH00151: Inertial semantics check on a signal asg with selected name on LHS failed
-- NEED RESULT: ARCH00151: Inertial semantics check on a signal asg with selected name on LHS failed
-- NEED RESULT: ARCH00151: Inertial semantics check on a signal asg with selected name on LHS failed
-- NEED RESULT: ARCH00151: Inertial semantics check on a signal asg with selected name on LHS failed
-- NEED RESULT: ARCH00151: Old transactions were removed on signal asg with selected name on LHS passed
-- NEED RESULT: ARCH00151: One inertial transaction occurred on signal asg with selected name on LHS passed
-- NEED RESULT: ARCH00151: Inertial semantics check on a signal asg with selected name on LHS passed
-- NEED RESULT: P3: Inertial transactions entirely completed failed
-- NEED RESULT: P2: Inertial transactions entirely completed failed
-- NEED RESULT: P1: Inertial transactions entirely completed passed
-------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
-------------------------------------------------------------------------------
--
-- TEST NAME:
--
-- CT00151
--
-- AUTHOR:
--
-- G. Tominovich
--
-- TEST OBJECTIVES:
--
-- 8.3 (1)
-- 8.3 (2)
-- 8.3 (4)
-- 8.3 (5)
-- 8.3.1 (4)
--
-- DESIGN UNIT ORDERING:
--
-- ENT00151(ARCH00151)
-- ENT00151_Test_Bench(ARCH00151_Test_Bench)
--
-- REVISION HISTORY:
--
-- 08-JUL-1987 - initial revision
--
-- NOTES:
--
-- self-checking
-- automatically generated
--
use WORK.STANDARD_TYPES.all ;
entity ENT00151 is
subtype chk_sig_type is integer range -1 to 100 ;
signal chk_st_rec1 : chk_sig_type := -1 ;
signal chk_st_rec2 : chk_sig_type := -1 ;
signal chk_st_rec3 : chk_sig_type := -1 ;
--
procedure Proc1 (
signal s_st_rec1 : inout st_rec1 ;
variable counter : inout integer ;
variable correct : inout boolean ;
variable savtime : inout time ;
signal chk_st_rec1 : out chk_sig_type
)
is
begin
case counter is
when 0
=> s_st_rec1.f2 <=
c_st_rec1_2.f2 after 10 ns,
c_st_rec1_1.f2 after 20 ns ;
--
when 1
=> correct :=
s_st_rec1.f2 = c_st_rec1_2.f2 and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_rec1.f2 = c_st_rec1_1.f2 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00151.P1" ,
"Multi inertial transactions occurred on signal " &
"asg with selected name on LHS",
correct ) ;
s_st_rec1.f2 <=
c_st_rec1_2.f2 after 10 ns ,
c_st_rec1_1.f2 after 20 ns ,
c_st_rec1_2.f2 after 30 ns ,
c_st_rec1_1.f2 after 40 ns ;
--
when 3
=> correct :=
s_st_rec1.f2 = c_st_rec1_2.f2 and
(savtime + 10 ns) = Std.Standard.Now ;
s_st_rec1.f2 <= c_st_rec1_1.f2 after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_rec1.f2 = c_st_rec1_1.f2 and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00151" ,
"One inertial transaction occurred on signal " &
"asg with selected name on LHS",
correct ) ;
s_st_rec1.f2 <= transport
c_st_rec1_1.f2 after 100 ns ;
--
when 5
=> correct :=
s_st_rec1.f2 = c_st_rec1_1.f2 and
(savtime + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00151" ,
"Old transactions were removed on signal " &
"asg with selected name on LHS",
correct ) ;
s_st_rec1.f2 <=
c_st_rec1_2.f2 after 10 ns ,
c_st_rec1_1.f2 after 20 ns ,
c_st_rec1_2.f2 after 30 ns ,
c_st_rec1_1.f2 after 40 ns ;
--
when 6
=> correct :=
s_st_rec1.f2 = c_st_rec1_2.f2 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00151" ,
"One inertial transaction occurred on signal " &
"asg with selected name on LHS",
correct ) ;
s_st_rec1.f2 <= -- Last transaction above is marked
c_st_rec1_1.f2 after 40 ns ;
--
when 7
=> correct :=
s_st_rec1.f2 = c_st_rec1_1.f2 and
(savtime + 30 ns) = Std.Standard.Now ;
--
when 8
=> correct := correct and
s_st_rec1.f2 = c_st_rec1_1.f2 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00151" ,
"Inertial semantics check on a signal " &
"asg with selected name on LHS",
correct ) ;
--
when others
=>
test_report ( "ARCH00151" ,
"Inertial semantics check on a signal " &
"asg with selected name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_st_rec1 <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
end Proc1 ;
--
procedure Proc2 (
signal s_st_rec2 : inout st_rec2 ;
variable counter : inout integer ;
variable correct : inout boolean ;
variable savtime : inout time ;
signal chk_st_rec2 : out chk_sig_type
)
is
begin
case counter is
when 0
=> s_st_rec2.f2 <=
c_st_rec2_2.f2 after 10 ns,
c_st_rec2_1.f2 after 20 ns ;
--
when 1
=> correct :=
s_st_rec2.f2 = c_st_rec2_2.f2 and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_rec2.f2 = c_st_rec2_1.f2 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00151.P2" ,
"Multi inertial transactions occurred on signal " &
"asg with selected name on LHS",
correct ) ;
s_st_rec2.f2 <=
c_st_rec2_2.f2 after 10 ns ,
c_st_rec2_1.f2 after 20 ns ,
c_st_rec2_2.f2 after 30 ns ,
c_st_rec2_1.f2 after 40 ns ;
--
when 3
=> correct :=
s_st_rec2.f2 = c_st_rec2_2.f2 and
(savtime + 10 ns) = Std.Standard.Now ;
s_st_rec2.f2 <= c_st_rec2_1.f2 after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_rec2.f2 = c_st_rec2_1.f2 and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00151" ,
"One inertial transaction occurred on signal " &
"asg with selected name on LHS",
correct ) ;
s_st_rec2.f2 <= transport
c_st_rec2_1.f2 after 100 ns ;
--
when 5
=> correct :=
s_st_rec2.f2 = c_st_rec2_1.f2 and
(savtime + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00151" ,
"Old transactions were removed on signal " &
"asg with selected name on LHS",
correct ) ;
s_st_rec2.f2 <=
c_st_rec2_2.f2 after 10 ns ,
c_st_rec2_1.f2 after 20 ns ,
c_st_rec2_2.f2 after 30 ns ,
c_st_rec2_1.f2 after 40 ns ;
--
when 6
=> correct :=
s_st_rec2.f2 = c_st_rec2_2.f2 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00151" ,
"One inertial transaction occurred on signal " &
"asg with selected name on LHS",
correct ) ;
s_st_rec2.f2 <= -- Last transaction above is marked
c_st_rec2_1.f2 after 40 ns ;
--
when 7
=> correct :=
s_st_rec2.f2 = c_st_rec2_1.f2 and
(savtime + 30 ns) = Std.Standard.Now ;
--
when 8
=> correct := correct and
s_st_rec2.f2 = c_st_rec2_1.f2 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00151" ,
"Inertial semantics check on a signal " &
"asg with selected name on LHS",
correct ) ;
--
when others
=>
test_report ( "ARCH00151" ,
"Inertial semantics check on a signal " &
"asg with selected name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_st_rec2 <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
end Proc2 ;
--
procedure Proc3 (
signal s_st_rec3 : inout st_rec3 ;
variable counter : inout integer ;
variable correct : inout boolean ;
variable savtime : inout time ;
signal chk_st_rec3 : out chk_sig_type
)
is
begin
case counter is
when 0
=> s_st_rec3.f2 <=
c_st_rec3_2.f2 after 10 ns,
c_st_rec3_1.f2 after 20 ns ;
--
when 1
=> correct :=
s_st_rec3.f2 = c_st_rec3_2.f2 and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_rec3.f2 = c_st_rec3_1.f2 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00151.P3" ,
"Multi inertial transactions occurred on signal " &
"asg with selected name on LHS",
correct ) ;
s_st_rec3.f2 <=
c_st_rec3_2.f2 after 10 ns ,
c_st_rec3_1.f2 after 20 ns ,
c_st_rec3_2.f2 after 30 ns ,
c_st_rec3_1.f2 after 40 ns ;
--
when 3
=> correct :=
s_st_rec3.f2 = c_st_rec3_2.f2 and
(savtime + 10 ns) = Std.Standard.Now ;
s_st_rec3.f2 <= c_st_rec3_1.f2 after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_rec3.f2 = c_st_rec3_1.f2 and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00151" ,
"One inertial transaction occurred on signal " &
"asg with selected name on LHS",
correct ) ;
s_st_rec3.f2 <= transport
c_st_rec3_1.f2 after 100 ns ;
--
when 5
=> correct :=
s_st_rec3.f2 = c_st_rec3_1.f2 and
(savtime + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00151" ,
"Old transactions were removed on signal " &
"asg with selected name on LHS",
correct ) ;
s_st_rec3.f2 <=
c_st_rec3_2.f2 after 10 ns ,
c_st_rec3_1.f2 after 20 ns ,
c_st_rec3_2.f2 after 30 ns ,
c_st_rec3_1.f2 after 40 ns ;
--
when 6
=> correct :=
s_st_rec3.f2 = c_st_rec3_2.f2 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00151" ,
"One inertial transaction occurred on signal " &
"asg with selected name on LHS",
correct ) ;
s_st_rec3.f2 <= -- Last transaction above is marked
c_st_rec3_1.f2 after 40 ns ;
--
when 7
=> correct :=
s_st_rec3.f2 = c_st_rec3_1.f2 and
(savtime + 30 ns) = Std.Standard.Now ;
--
when 8
=> correct := correct and
s_st_rec3.f2 = c_st_rec3_1.f2 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00151" ,
"Inertial semantics check on a signal " &
"asg with selected name on LHS",
correct ) ;
--
when others
=>
test_report ( "ARCH00151" ,
"Inertial semantics check on a signal " &
"asg with selected name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_st_rec3 <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
end Proc3 ;
--
--
end ENT00151 ;
--
architecture ARCH00151 of ENT00151 is
signal s_st_rec1 : st_rec1
:= c_st_rec1_1 ;
signal s_st_rec2 : st_rec2
:= c_st_rec2_1 ;
signal s_st_rec3 : st_rec3
:= c_st_rec3_1 ;
--
begin
P1 :
process
variable counter : integer := 0 ;
variable correct : boolean ;
variable savtime : time ;
begin
Proc1 (
s_st_rec1,
counter,
correct,
savtime,
chk_st_rec1
) ;
wait until (not s_st_rec1'Quiet) and
(savtime /= Std.Standard.Now) ;
--
end process P1 ;
--
PGEN_CHKP_1 :
process ( chk_st_rec1 )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P1" ,
"Inertial transactions entirely completed",
chk_st_rec1 = 8 ) ;
end if ;
end process PGEN_CHKP_1 ;
--
P2 :
process
variable counter : integer := 0 ;
variable correct : boolean ;
variable savtime : time ;
begin
Proc2 (
s_st_rec2,
counter,
correct,
savtime,
chk_st_rec2
) ;
wait until (not s_st_rec2'Quiet) and
(savtime /= Std.Standard.Now) ;
--
end process P2 ;
--
PGEN_CHKP_2 :
process ( chk_st_rec2 )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P2" ,
"Inertial transactions entirely completed",
chk_st_rec2 = 8 ) ;
end if ;
end process PGEN_CHKP_2 ;
--
P3 :
process
variable counter : integer := 0 ;
variable correct : boolean ;
variable savtime : time ;
begin
Proc3 (
s_st_rec3,
counter,
correct,
savtime,
chk_st_rec3
) ;
wait until (not s_st_rec3'Quiet) and
(savtime /= Std.Standard.Now) ;
--
end process P3 ;
--
PGEN_CHKP_3 :
process ( chk_st_rec3 )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P3" ,
"Inertial transactions entirely completed",
chk_st_rec3 = 8 ) ;
end if ;
end process PGEN_CHKP_3 ;
--
--
end ARCH00151 ;
--
entity ENT00151_Test_Bench is
end ENT00151_Test_Bench ;
--
architecture ARCH00151_Test_Bench of ENT00151_Test_Bench is
begin
L1:
block
component UUT
end component ;
for CIS1 : UUT use entity WORK.ENT00151 ( ARCH00151 ) ;
begin
CIS1 : UUT ;
end block L1 ;
end ARCH00151_Test_Bench ;
| gpl-3.0 | 28a4b0cd5213f207ae88c364c01eb494 | 0.499015 | 3.638714 | false | true | false | false |
grwlf/vsim | vhdl/function1.vhd | 1 | 721 | entity test is
end entity test;
architecture test of test is
constant c : integer := 0;
type arr01 is array (0 to 1) of integer;
procedure p1(constant i:integer) is
begin
end;
procedure p2(constant i:integer) is
begin
return;
end;
function f1(a1 : arr01) return integer is
begin
return a1(c);
end function;
begin
main: process
variable i : arr01 := (others => 33);
variable x : integer := 10;
begin
p1(c);
p2(c);
x := f1( i );
report integer'image(x);
assert false report "end of simulation" severity failure;
end process;
end architecture test;
| gpl-3.0 | cfc22220fb2177cd1e44f18a9a4ce3ed | 0.552011 | 3.983425 | false | true | false | false |
jairov4/accel-oil | solution_virtex5_plb/impl/vhdl/nfa_accept_samples_generic_hw_mul_16ns_8ns_24_2.vhd | 1 | 2,575 | -- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2014.1
-- Copyright (C) 2014 Xilinx Inc. All rights reserved.
--
-- ==============================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity nfa_accept_samples_generic_hw_mul_16ns_8ns_24_2_MAC2S_0 is
port (
clk: in std_logic;
ce: in std_logic;
a: in std_logic_vector(16 - 1 downto 0);
b: in std_logic_vector(8 - 1 downto 0);
p: out std_logic_vector(24 - 1 downto 0));
end entity;
architecture behav of nfa_accept_samples_generic_hw_mul_16ns_8ns_24_2_MAC2S_0 is
signal tmp_product : std_logic_vector(24 - 1 downto 0);
signal a_i : std_logic_vector(16 - 1 downto 0);
signal b_i : std_logic_vector(8 - 1 downto 0);
signal p_tmp : std_logic_vector(24 - 1 downto 0);
attribute keep : string;
attribute keep of a_i : signal is "true";
attribute keep of b_i : signal is "true";
begin
a_i <= a;
b_i <= b;
p <= p_tmp;
tmp_product <= std_logic_vector(resize(unsigned(a_i) * unsigned(b_i), 24));
process(clk)
begin
if (clk'event and clk = '1') then
if (ce = '1') then
p_tmp <= tmp_product;
end if;
end if;
end process;
end architecture;
Library IEEE;
use IEEE.std_logic_1164.all;
entity nfa_accept_samples_generic_hw_mul_16ns_8ns_24_2 is
generic (
ID : INTEGER;
NUM_STAGE : INTEGER;
din0_WIDTH : INTEGER;
din1_WIDTH : INTEGER;
dout_WIDTH : INTEGER);
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
ce : IN STD_LOGIC;
din0 : IN STD_LOGIC_VECTOR(din0_WIDTH - 1 DOWNTO 0);
din1 : IN STD_LOGIC_VECTOR(din1_WIDTH - 1 DOWNTO 0);
dout : OUT STD_LOGIC_VECTOR(dout_WIDTH - 1 DOWNTO 0));
end entity;
architecture arch of nfa_accept_samples_generic_hw_mul_16ns_8ns_24_2 is
component nfa_accept_samples_generic_hw_mul_16ns_8ns_24_2_MAC2S_0 is
port (
clk : IN STD_LOGIC;
ce : IN STD_LOGIC;
a : IN STD_LOGIC_VECTOR;
b : IN STD_LOGIC_VECTOR;
p : OUT STD_LOGIC_VECTOR);
end component;
begin
nfa_accept_samples_generic_hw_mul_16ns_8ns_24_2_MAC2S_0_U : component nfa_accept_samples_generic_hw_mul_16ns_8ns_24_2_MAC2S_0
port map (
clk => clk,
ce => ce,
a => din0,
b => din1,
p => dout);
end architecture;
| lgpl-3.0 | 6abe8d26032e440e8037d425857e2bb0 | 0.565437 | 3.182942 | false | false | false | false |
TWW12/lzw | final_project_sim/lzw/lzw.srcs/sources_1/ip/bram_1024_0/bram_1024_0_sim_netlist.vhdl | 1 | 50,604 | -- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1756540 Mon Jan 23 19:11:23 MST 2017
-- Date : Tue Apr 18 23:18:55 2017
-- Host : DESKTOP-I9J3TQJ running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode funcsim
-- X:/final_project_sim/lzw/lzw.srcs/sources_1/ip/bram_1024_0/bram_1024_0_sim_netlist.vhdl
-- Design : bram_1024_0
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7z020clg484-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity bram_1024_0_blk_mem_gen_prim_wrapper_init is
port (
douta : out STD_LOGIC_VECTOR ( 19 downto 0 );
clka : in STD_LOGIC;
ena : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 9 downto 0 );
dina : in STD_LOGIC_VECTOR ( 19 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of bram_1024_0_blk_mem_gen_prim_wrapper_init : entity is "blk_mem_gen_prim_wrapper_init";
end bram_1024_0_blk_mem_gen_prim_wrapper_init;
architecture STRUCTURE of bram_1024_0_blk_mem_gen_prim_wrapper_init is
signal \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_21\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_22\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_23\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_29\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_30\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_31\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_37\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_38\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_39\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_45\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_46\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_47\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_85\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_86\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_87\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_88\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute CLOCK_DOMAINS : string;
attribute CLOCK_DOMAINS of \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\ : label is "COMMON";
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 1,
DOB_REG => 0,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_00 => X"0000001D0000001900000015000000110000000D000000090000000500000001",
INIT_01 => X"0000011D0000011900000115000001110000010D000001090000010500000101",
INIT_02 => X"0000021D0000021900000215000002110000020D000002090000020500000201",
INIT_03 => X"0000031D0000031900000315000003110000030D000003090000030500000301",
INIT_04 => X"0000041D0000041900000415000004110000040D000004090000040500000401",
INIT_05 => X"0000051D0000051900000515000005110000050D000005090000050500000501",
INIT_06 => X"0000061D0000061900000615000006110000060D000006090000060500000601",
INIT_07 => X"0000071D0000071900000715000007110000070D000007090000070500000701",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_40 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_41 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_42 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_43 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_44 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_45 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_46 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_47 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_48 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_49 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_50 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_51 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_52 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_53 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_54 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_55 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_56 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_57 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_58 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_59 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_60 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_61 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_62 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_63 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_64 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_65 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_66 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_67 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_68 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_69 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_70 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_71 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_72 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_73 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_74 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "PERFORMANCE",
READ_WIDTH_A => 36,
READ_WIDTH_B => 36,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 36,
WRITE_WIDTH_B => 36
)
port map (
ADDRARDADDR(15) => '1',
ADDRARDADDR(14 downto 5) => addra(9 downto 0),
ADDRARDADDR(4 downto 0) => B"11111",
ADDRBWRADDR(15 downto 0) => B"0000000000000000",
CASCADEINA => '0',
CASCADEINB => '0',
CASCADEOUTA => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => clka,
CLKBWRCLK => clka,
DBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\,
DIADI(31 downto 29) => B"000",
DIADI(28 downto 24) => dina(19 downto 15),
DIADI(23 downto 21) => B"000",
DIADI(20 downto 16) => dina(14 downto 10),
DIADI(15 downto 13) => B"000",
DIADI(12 downto 8) => dina(9 downto 5),
DIADI(7 downto 5) => B"000",
DIADI(4 downto 0) => dina(4 downto 0),
DIBDI(31 downto 0) => B"00000000000000000000000000000000",
DIPADIP(3 downto 0) => B"0000",
DIPBDIP(3 downto 0) => B"0000",
DOADO(31) => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_21\,
DOADO(30) => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_22\,
DOADO(29) => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_23\,
DOADO(28 downto 24) => douta(19 downto 15),
DOADO(23) => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_29\,
DOADO(22) => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_30\,
DOADO(21) => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_31\,
DOADO(20 downto 16) => douta(14 downto 10),
DOADO(15) => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_37\,
DOADO(14) => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_38\,
DOADO(13) => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_39\,
DOADO(12 downto 8) => douta(9 downto 5),
DOADO(7) => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_45\,
DOADO(6) => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_46\,
DOADO(5) => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_47\,
DOADO(4 downto 0) => douta(4 downto 0),
DOBDO(31 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\(31 downto 0),
DOPADOP(3) => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_85\,
DOPADOP(2) => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_86\,
DOPADOP(1) => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_87\,
DOPADOP(0) => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_88\,
DOPBDOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\(3 downto 0),
ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => ena,
ENBWREN => '0',
INJECTDBITERR => '0',
INJECTSBITERR => '0',
RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => ena,
REGCEB => '0',
RSTRAMARSTRAM => '0',
RSTRAMB => '0',
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\,
WEA(3) => wea(0),
WEA(2) => wea(0),
WEA(1) => wea(0),
WEA(0) => wea(0),
WEBWE(7 downto 0) => B"00000000"
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity bram_1024_0_blk_mem_gen_prim_width is
port (
douta : out STD_LOGIC_VECTOR ( 19 downto 0 );
clka : in STD_LOGIC;
ena : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 9 downto 0 );
dina : in STD_LOGIC_VECTOR ( 19 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of bram_1024_0_blk_mem_gen_prim_width : entity is "blk_mem_gen_prim_width";
end bram_1024_0_blk_mem_gen_prim_width;
architecture STRUCTURE of bram_1024_0_blk_mem_gen_prim_width is
begin
\prim_init.ram\: entity work.bram_1024_0_blk_mem_gen_prim_wrapper_init
port map (
addra(9 downto 0) => addra(9 downto 0),
clka => clka,
dina(19 downto 0) => dina(19 downto 0),
douta(19 downto 0) => douta(19 downto 0),
ena => ena,
wea(0) => wea(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity bram_1024_0_blk_mem_gen_generic_cstr is
port (
douta : out STD_LOGIC_VECTOR ( 19 downto 0 );
clka : in STD_LOGIC;
ena : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 9 downto 0 );
dina : in STD_LOGIC_VECTOR ( 19 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of bram_1024_0_blk_mem_gen_generic_cstr : entity is "blk_mem_gen_generic_cstr";
end bram_1024_0_blk_mem_gen_generic_cstr;
architecture STRUCTURE of bram_1024_0_blk_mem_gen_generic_cstr is
begin
\ramloop[0].ram.r\: entity work.bram_1024_0_blk_mem_gen_prim_width
port map (
addra(9 downto 0) => addra(9 downto 0),
clka => clka,
dina(19 downto 0) => dina(19 downto 0),
douta(19 downto 0) => douta(19 downto 0),
ena => ena,
wea(0) => wea(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity bram_1024_0_blk_mem_gen_top is
port (
douta : out STD_LOGIC_VECTOR ( 19 downto 0 );
clka : in STD_LOGIC;
ena : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 9 downto 0 );
dina : in STD_LOGIC_VECTOR ( 19 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of bram_1024_0_blk_mem_gen_top : entity is "blk_mem_gen_top";
end bram_1024_0_blk_mem_gen_top;
architecture STRUCTURE of bram_1024_0_blk_mem_gen_top is
begin
\valid.cstr\: entity work.bram_1024_0_blk_mem_gen_generic_cstr
port map (
addra(9 downto 0) => addra(9 downto 0),
clka => clka,
dina(19 downto 0) => dina(19 downto 0),
douta(19 downto 0) => douta(19 downto 0),
ena => ena,
wea(0) => wea(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity bram_1024_0_blk_mem_gen_v8_3_5_synth is
port (
douta : out STD_LOGIC_VECTOR ( 19 downto 0 );
clka : in STD_LOGIC;
ena : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 9 downto 0 );
dina : in STD_LOGIC_VECTOR ( 19 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of bram_1024_0_blk_mem_gen_v8_3_5_synth : entity is "blk_mem_gen_v8_3_5_synth";
end bram_1024_0_blk_mem_gen_v8_3_5_synth;
architecture STRUCTURE of bram_1024_0_blk_mem_gen_v8_3_5_synth is
begin
\gnbram.gnativebmg.native_blk_mem_gen\: entity work.bram_1024_0_blk_mem_gen_top
port map (
addra(9 downto 0) => addra(9 downto 0),
clka => clka,
dina(19 downto 0) => dina(19 downto 0),
douta(19 downto 0) => douta(19 downto 0),
ena => ena,
wea(0) => wea(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity bram_1024_0_blk_mem_gen_v8_3_5 is
port (
clka : in STD_LOGIC;
rsta : in STD_LOGIC;
ena : in STD_LOGIC;
regcea : in STD_LOGIC;
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
addra : in STD_LOGIC_VECTOR ( 9 downto 0 );
dina : in STD_LOGIC_VECTOR ( 19 downto 0 );
douta : out STD_LOGIC_VECTOR ( 19 downto 0 );
clkb : in STD_LOGIC;
rstb : in STD_LOGIC;
enb : in STD_LOGIC;
regceb : in STD_LOGIC;
web : in STD_LOGIC_VECTOR ( 0 to 0 );
addrb : in STD_LOGIC_VECTOR ( 9 downto 0 );
dinb : in STD_LOGIC_VECTOR ( 19 downto 0 );
doutb : out STD_LOGIC_VECTOR ( 19 downto 0 );
injectsbiterr : in STD_LOGIC;
injectdbiterr : in STD_LOGIC;
eccpipece : in STD_LOGIC;
sbiterr : out STD_LOGIC;
dbiterr : out STD_LOGIC;
rdaddrecc : out STD_LOGIC_VECTOR ( 9 downto 0 );
sleep : in STD_LOGIC;
deepsleep : in STD_LOGIC;
shutdown : in STD_LOGIC;
rsta_busy : out STD_LOGIC;
rstb_busy : out STD_LOGIC;
s_aclk : in STD_LOGIC;
s_aresetn : in STD_LOGIC;
s_axi_awid : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_awready : out STD_LOGIC;
s_axi_wdata : in STD_LOGIC_VECTOR ( 19 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_wlast : in STD_LOGIC;
s_axi_wvalid : in STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_bid : out STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_bvalid : out STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_arid : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arvalid : in STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_rid : out STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_rdata : out STD_LOGIC_VECTOR ( 19 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rlast : out STD_LOGIC;
s_axi_rvalid : out STD_LOGIC;
s_axi_rready : in STD_LOGIC;
s_axi_injectsbiterr : in STD_LOGIC;
s_axi_injectdbiterr : in STD_LOGIC;
s_axi_sbiterr : out STD_LOGIC;
s_axi_dbiterr : out STD_LOGIC;
s_axi_rdaddrecc : out STD_LOGIC_VECTOR ( 9 downto 0 )
);
attribute C_ADDRA_WIDTH : integer;
attribute C_ADDRA_WIDTH of bram_1024_0_blk_mem_gen_v8_3_5 : entity is 10;
attribute C_ADDRB_WIDTH : integer;
attribute C_ADDRB_WIDTH of bram_1024_0_blk_mem_gen_v8_3_5 : entity is 10;
attribute C_ALGORITHM : integer;
attribute C_ALGORITHM of bram_1024_0_blk_mem_gen_v8_3_5 : entity is 1;
attribute C_AXI_ID_WIDTH : integer;
attribute C_AXI_ID_WIDTH of bram_1024_0_blk_mem_gen_v8_3_5 : entity is 4;
attribute C_AXI_SLAVE_TYPE : integer;
attribute C_AXI_SLAVE_TYPE of bram_1024_0_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_AXI_TYPE : integer;
attribute C_AXI_TYPE of bram_1024_0_blk_mem_gen_v8_3_5 : entity is 1;
attribute C_BYTE_SIZE : integer;
attribute C_BYTE_SIZE of bram_1024_0_blk_mem_gen_v8_3_5 : entity is 9;
attribute C_COMMON_CLK : integer;
attribute C_COMMON_CLK of bram_1024_0_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_COUNT_18K_BRAM : string;
attribute C_COUNT_18K_BRAM of bram_1024_0_blk_mem_gen_v8_3_5 : entity is "0";
attribute C_COUNT_36K_BRAM : string;
attribute C_COUNT_36K_BRAM of bram_1024_0_blk_mem_gen_v8_3_5 : entity is "1";
attribute C_CTRL_ECC_ALGO : string;
attribute C_CTRL_ECC_ALGO of bram_1024_0_blk_mem_gen_v8_3_5 : entity is "NONE";
attribute C_DEFAULT_DATA : string;
attribute C_DEFAULT_DATA of bram_1024_0_blk_mem_gen_v8_3_5 : entity is "0";
attribute C_DISABLE_WARN_BHV_COLL : integer;
attribute C_DISABLE_WARN_BHV_COLL of bram_1024_0_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_DISABLE_WARN_BHV_RANGE : integer;
attribute C_DISABLE_WARN_BHV_RANGE of bram_1024_0_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_ELABORATION_DIR : string;
attribute C_ELABORATION_DIR of bram_1024_0_blk_mem_gen_v8_3_5 : entity is "./";
attribute C_ENABLE_32BIT_ADDRESS : integer;
attribute C_ENABLE_32BIT_ADDRESS of bram_1024_0_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_EN_DEEPSLEEP_PIN : integer;
attribute C_EN_DEEPSLEEP_PIN of bram_1024_0_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_EN_ECC_PIPE : integer;
attribute C_EN_ECC_PIPE of bram_1024_0_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_EN_RDADDRA_CHG : integer;
attribute C_EN_RDADDRA_CHG of bram_1024_0_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_EN_RDADDRB_CHG : integer;
attribute C_EN_RDADDRB_CHG of bram_1024_0_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_EN_SAFETY_CKT : integer;
attribute C_EN_SAFETY_CKT of bram_1024_0_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_EN_SHUTDOWN_PIN : integer;
attribute C_EN_SHUTDOWN_PIN of bram_1024_0_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_EN_SLEEP_PIN : integer;
attribute C_EN_SLEEP_PIN of bram_1024_0_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_EST_POWER_SUMMARY : string;
attribute C_EST_POWER_SUMMARY of bram_1024_0_blk_mem_gen_v8_3_5 : entity is "Estimated Power for IP : 2.74095 mW";
attribute C_FAMILY : string;
attribute C_FAMILY of bram_1024_0_blk_mem_gen_v8_3_5 : entity is "zynq";
attribute C_HAS_AXI_ID : integer;
attribute C_HAS_AXI_ID of bram_1024_0_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_HAS_ENA : integer;
attribute C_HAS_ENA of bram_1024_0_blk_mem_gen_v8_3_5 : entity is 1;
attribute C_HAS_ENB : integer;
attribute C_HAS_ENB of bram_1024_0_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_HAS_INJECTERR : integer;
attribute C_HAS_INJECTERR of bram_1024_0_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_HAS_MEM_OUTPUT_REGS_A : integer;
attribute C_HAS_MEM_OUTPUT_REGS_A of bram_1024_0_blk_mem_gen_v8_3_5 : entity is 1;
attribute C_HAS_MEM_OUTPUT_REGS_B : integer;
attribute C_HAS_MEM_OUTPUT_REGS_B of bram_1024_0_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_HAS_MUX_OUTPUT_REGS_A : integer;
attribute C_HAS_MUX_OUTPUT_REGS_A of bram_1024_0_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_HAS_MUX_OUTPUT_REGS_B : integer;
attribute C_HAS_MUX_OUTPUT_REGS_B of bram_1024_0_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_HAS_REGCEA : integer;
attribute C_HAS_REGCEA of bram_1024_0_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_HAS_REGCEB : integer;
attribute C_HAS_REGCEB of bram_1024_0_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_HAS_RSTA : integer;
attribute C_HAS_RSTA of bram_1024_0_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_HAS_RSTB : integer;
attribute C_HAS_RSTB of bram_1024_0_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_HAS_SOFTECC_INPUT_REGS_A : integer;
attribute C_HAS_SOFTECC_INPUT_REGS_A of bram_1024_0_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_HAS_SOFTECC_OUTPUT_REGS_B : integer;
attribute C_HAS_SOFTECC_OUTPUT_REGS_B of bram_1024_0_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_INITA_VAL : string;
attribute C_INITA_VAL of bram_1024_0_blk_mem_gen_v8_3_5 : entity is "0";
attribute C_INITB_VAL : string;
attribute C_INITB_VAL of bram_1024_0_blk_mem_gen_v8_3_5 : entity is "0";
attribute C_INIT_FILE : string;
attribute C_INIT_FILE of bram_1024_0_blk_mem_gen_v8_3_5 : entity is "bram_1024_0.mem";
attribute C_INIT_FILE_NAME : string;
attribute C_INIT_FILE_NAME of bram_1024_0_blk_mem_gen_v8_3_5 : entity is "bram_1024_0.mif";
attribute C_INTERFACE_TYPE : integer;
attribute C_INTERFACE_TYPE of bram_1024_0_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_LOAD_INIT_FILE : integer;
attribute C_LOAD_INIT_FILE of bram_1024_0_blk_mem_gen_v8_3_5 : entity is 1;
attribute C_MEM_TYPE : integer;
attribute C_MEM_TYPE of bram_1024_0_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_MUX_PIPELINE_STAGES : integer;
attribute C_MUX_PIPELINE_STAGES of bram_1024_0_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_PRIM_TYPE : integer;
attribute C_PRIM_TYPE of bram_1024_0_blk_mem_gen_v8_3_5 : entity is 1;
attribute C_READ_DEPTH_A : integer;
attribute C_READ_DEPTH_A of bram_1024_0_blk_mem_gen_v8_3_5 : entity is 1024;
attribute C_READ_DEPTH_B : integer;
attribute C_READ_DEPTH_B of bram_1024_0_blk_mem_gen_v8_3_5 : entity is 1024;
attribute C_READ_WIDTH_A : integer;
attribute C_READ_WIDTH_A of bram_1024_0_blk_mem_gen_v8_3_5 : entity is 20;
attribute C_READ_WIDTH_B : integer;
attribute C_READ_WIDTH_B of bram_1024_0_blk_mem_gen_v8_3_5 : entity is 20;
attribute C_RSTRAM_A : integer;
attribute C_RSTRAM_A of bram_1024_0_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_RSTRAM_B : integer;
attribute C_RSTRAM_B of bram_1024_0_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_RST_PRIORITY_A : string;
attribute C_RST_PRIORITY_A of bram_1024_0_blk_mem_gen_v8_3_5 : entity is "CE";
attribute C_RST_PRIORITY_B : string;
attribute C_RST_PRIORITY_B of bram_1024_0_blk_mem_gen_v8_3_5 : entity is "CE";
attribute C_SIM_COLLISION_CHECK : string;
attribute C_SIM_COLLISION_CHECK of bram_1024_0_blk_mem_gen_v8_3_5 : entity is "ALL";
attribute C_USE_BRAM_BLOCK : integer;
attribute C_USE_BRAM_BLOCK of bram_1024_0_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_USE_BYTE_WEA : integer;
attribute C_USE_BYTE_WEA of bram_1024_0_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_USE_BYTE_WEB : integer;
attribute C_USE_BYTE_WEB of bram_1024_0_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_USE_DEFAULT_DATA : integer;
attribute C_USE_DEFAULT_DATA of bram_1024_0_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_USE_ECC : integer;
attribute C_USE_ECC of bram_1024_0_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_USE_SOFTECC : integer;
attribute C_USE_SOFTECC of bram_1024_0_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_USE_URAM : integer;
attribute C_USE_URAM of bram_1024_0_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_WEA_WIDTH : integer;
attribute C_WEA_WIDTH of bram_1024_0_blk_mem_gen_v8_3_5 : entity is 1;
attribute C_WEB_WIDTH : integer;
attribute C_WEB_WIDTH of bram_1024_0_blk_mem_gen_v8_3_5 : entity is 1;
attribute C_WRITE_DEPTH_A : integer;
attribute C_WRITE_DEPTH_A of bram_1024_0_blk_mem_gen_v8_3_5 : entity is 1024;
attribute C_WRITE_DEPTH_B : integer;
attribute C_WRITE_DEPTH_B of bram_1024_0_blk_mem_gen_v8_3_5 : entity is 1024;
attribute C_WRITE_MODE_A : string;
attribute C_WRITE_MODE_A of bram_1024_0_blk_mem_gen_v8_3_5 : entity is "WRITE_FIRST";
attribute C_WRITE_MODE_B : string;
attribute C_WRITE_MODE_B of bram_1024_0_blk_mem_gen_v8_3_5 : entity is "WRITE_FIRST";
attribute C_WRITE_WIDTH_A : integer;
attribute C_WRITE_WIDTH_A of bram_1024_0_blk_mem_gen_v8_3_5 : entity is 20;
attribute C_WRITE_WIDTH_B : integer;
attribute C_WRITE_WIDTH_B of bram_1024_0_blk_mem_gen_v8_3_5 : entity is 20;
attribute C_XDEVICEFAMILY : string;
attribute C_XDEVICEFAMILY of bram_1024_0_blk_mem_gen_v8_3_5 : entity is "zynq";
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of bram_1024_0_blk_mem_gen_v8_3_5 : entity is "blk_mem_gen_v8_3_5";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of bram_1024_0_blk_mem_gen_v8_3_5 : entity is "yes";
end bram_1024_0_blk_mem_gen_v8_3_5;
architecture STRUCTURE of bram_1024_0_blk_mem_gen_v8_3_5 is
signal \<const0>\ : STD_LOGIC;
begin
dbiterr <= \<const0>\;
doutb(19) <= \<const0>\;
doutb(18) <= \<const0>\;
doutb(17) <= \<const0>\;
doutb(16) <= \<const0>\;
doutb(15) <= \<const0>\;
doutb(14) <= \<const0>\;
doutb(13) <= \<const0>\;
doutb(12) <= \<const0>\;
doutb(11) <= \<const0>\;
doutb(10) <= \<const0>\;
doutb(9) <= \<const0>\;
doutb(8) <= \<const0>\;
doutb(7) <= \<const0>\;
doutb(6) <= \<const0>\;
doutb(5) <= \<const0>\;
doutb(4) <= \<const0>\;
doutb(3) <= \<const0>\;
doutb(2) <= \<const0>\;
doutb(1) <= \<const0>\;
doutb(0) <= \<const0>\;
rdaddrecc(9) <= \<const0>\;
rdaddrecc(8) <= \<const0>\;
rdaddrecc(7) <= \<const0>\;
rdaddrecc(6) <= \<const0>\;
rdaddrecc(5) <= \<const0>\;
rdaddrecc(4) <= \<const0>\;
rdaddrecc(3) <= \<const0>\;
rdaddrecc(2) <= \<const0>\;
rdaddrecc(1) <= \<const0>\;
rdaddrecc(0) <= \<const0>\;
rsta_busy <= \<const0>\;
rstb_busy <= \<const0>\;
s_axi_arready <= \<const0>\;
s_axi_awready <= \<const0>\;
s_axi_bid(3) <= \<const0>\;
s_axi_bid(2) <= \<const0>\;
s_axi_bid(1) <= \<const0>\;
s_axi_bid(0) <= \<const0>\;
s_axi_bresp(1) <= \<const0>\;
s_axi_bresp(0) <= \<const0>\;
s_axi_bvalid <= \<const0>\;
s_axi_dbiterr <= \<const0>\;
s_axi_rdaddrecc(9) <= \<const0>\;
s_axi_rdaddrecc(8) <= \<const0>\;
s_axi_rdaddrecc(7) <= \<const0>\;
s_axi_rdaddrecc(6) <= \<const0>\;
s_axi_rdaddrecc(5) <= \<const0>\;
s_axi_rdaddrecc(4) <= \<const0>\;
s_axi_rdaddrecc(3) <= \<const0>\;
s_axi_rdaddrecc(2) <= \<const0>\;
s_axi_rdaddrecc(1) <= \<const0>\;
s_axi_rdaddrecc(0) <= \<const0>\;
s_axi_rdata(19) <= \<const0>\;
s_axi_rdata(18) <= \<const0>\;
s_axi_rdata(17) <= \<const0>\;
s_axi_rdata(16) <= \<const0>\;
s_axi_rdata(15) <= \<const0>\;
s_axi_rdata(14) <= \<const0>\;
s_axi_rdata(13) <= \<const0>\;
s_axi_rdata(12) <= \<const0>\;
s_axi_rdata(11) <= \<const0>\;
s_axi_rdata(10) <= \<const0>\;
s_axi_rdata(9) <= \<const0>\;
s_axi_rdata(8) <= \<const0>\;
s_axi_rdata(7) <= \<const0>\;
s_axi_rdata(6) <= \<const0>\;
s_axi_rdata(5) <= \<const0>\;
s_axi_rdata(4) <= \<const0>\;
s_axi_rdata(3) <= \<const0>\;
s_axi_rdata(2) <= \<const0>\;
s_axi_rdata(1) <= \<const0>\;
s_axi_rdata(0) <= \<const0>\;
s_axi_rid(3) <= \<const0>\;
s_axi_rid(2) <= \<const0>\;
s_axi_rid(1) <= \<const0>\;
s_axi_rid(0) <= \<const0>\;
s_axi_rlast <= \<const0>\;
s_axi_rresp(1) <= \<const0>\;
s_axi_rresp(0) <= \<const0>\;
s_axi_rvalid <= \<const0>\;
s_axi_sbiterr <= \<const0>\;
s_axi_wready <= \<const0>\;
sbiterr <= \<const0>\;
GND: unisim.vcomponents.GND
port map (
G => \<const0>\
);
inst_blk_mem_gen: entity work.bram_1024_0_blk_mem_gen_v8_3_5_synth
port map (
addra(9 downto 0) => addra(9 downto 0),
clka => clka,
dina(19 downto 0) => dina(19 downto 0),
douta(19 downto 0) => douta(19 downto 0),
ena => ena,
wea(0) => wea(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity bram_1024_0 is
port (
clka : in STD_LOGIC;
ena : in STD_LOGIC;
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
addra : in STD_LOGIC_VECTOR ( 9 downto 0 );
dina : in STD_LOGIC_VECTOR ( 19 downto 0 );
douta : out STD_LOGIC_VECTOR ( 19 downto 0 )
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of bram_1024_0 : entity is true;
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of bram_1024_0 : entity is "bram_1024_0,blk_mem_gen_v8_3_5,{}";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of bram_1024_0 : entity is "yes";
attribute x_core_info : string;
attribute x_core_info of bram_1024_0 : entity is "blk_mem_gen_v8_3_5,Vivado 2016.4";
end bram_1024_0;
architecture STRUCTURE of bram_1024_0 is
signal NLW_U0_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_rsta_busy_UNCONNECTED : STD_LOGIC;
signal NLW_U0_rstb_busy_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_arready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_awready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_bvalid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_rlast_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_rvalid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_wready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_doutb_UNCONNECTED : STD_LOGIC_VECTOR ( 19 downto 0 );
signal NLW_U0_rdaddrecc_UNCONNECTED : STD_LOGIC_VECTOR ( 9 downto 0 );
signal NLW_U0_s_axi_bid_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_s_axi_bresp_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_U0_s_axi_rdaddrecc_UNCONNECTED : STD_LOGIC_VECTOR ( 9 downto 0 );
signal NLW_U0_s_axi_rdata_UNCONNECTED : STD_LOGIC_VECTOR ( 19 downto 0 );
signal NLW_U0_s_axi_rid_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_s_axi_rresp_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute C_ADDRA_WIDTH : integer;
attribute C_ADDRA_WIDTH of U0 : label is 10;
attribute C_ADDRB_WIDTH : integer;
attribute C_ADDRB_WIDTH of U0 : label is 10;
attribute C_ALGORITHM : integer;
attribute C_ALGORITHM of U0 : label is 1;
attribute C_AXI_ID_WIDTH : integer;
attribute C_AXI_ID_WIDTH of U0 : label is 4;
attribute C_AXI_SLAVE_TYPE : integer;
attribute C_AXI_SLAVE_TYPE of U0 : label is 0;
attribute C_AXI_TYPE : integer;
attribute C_AXI_TYPE of U0 : label is 1;
attribute C_BYTE_SIZE : integer;
attribute C_BYTE_SIZE of U0 : label is 9;
attribute C_COMMON_CLK : integer;
attribute C_COMMON_CLK of U0 : label is 0;
attribute C_COUNT_18K_BRAM : string;
attribute C_COUNT_18K_BRAM of U0 : label is "0";
attribute C_COUNT_36K_BRAM : string;
attribute C_COUNT_36K_BRAM of U0 : label is "1";
attribute C_CTRL_ECC_ALGO : string;
attribute C_CTRL_ECC_ALGO of U0 : label is "NONE";
attribute C_DEFAULT_DATA : string;
attribute C_DEFAULT_DATA of U0 : label is "0";
attribute C_DISABLE_WARN_BHV_COLL : integer;
attribute C_DISABLE_WARN_BHV_COLL of U0 : label is 0;
attribute C_DISABLE_WARN_BHV_RANGE : integer;
attribute C_DISABLE_WARN_BHV_RANGE of U0 : label is 0;
attribute C_ELABORATION_DIR : string;
attribute C_ELABORATION_DIR of U0 : label is "./";
attribute C_ENABLE_32BIT_ADDRESS : integer;
attribute C_ENABLE_32BIT_ADDRESS of U0 : label is 0;
attribute C_EN_DEEPSLEEP_PIN : integer;
attribute C_EN_DEEPSLEEP_PIN of U0 : label is 0;
attribute C_EN_ECC_PIPE : integer;
attribute C_EN_ECC_PIPE of U0 : label is 0;
attribute C_EN_RDADDRA_CHG : integer;
attribute C_EN_RDADDRA_CHG of U0 : label is 0;
attribute C_EN_RDADDRB_CHG : integer;
attribute C_EN_RDADDRB_CHG of U0 : label is 0;
attribute C_EN_SAFETY_CKT : integer;
attribute C_EN_SAFETY_CKT of U0 : label is 0;
attribute C_EN_SHUTDOWN_PIN : integer;
attribute C_EN_SHUTDOWN_PIN of U0 : label is 0;
attribute C_EN_SLEEP_PIN : integer;
attribute C_EN_SLEEP_PIN of U0 : label is 0;
attribute C_EST_POWER_SUMMARY : string;
attribute C_EST_POWER_SUMMARY of U0 : label is "Estimated Power for IP : 2.74095 mW";
attribute C_FAMILY : string;
attribute C_FAMILY of U0 : label is "zynq";
attribute C_HAS_AXI_ID : integer;
attribute C_HAS_AXI_ID of U0 : label is 0;
attribute C_HAS_ENA : integer;
attribute C_HAS_ENA of U0 : label is 1;
attribute C_HAS_ENB : integer;
attribute C_HAS_ENB of U0 : label is 0;
attribute C_HAS_INJECTERR : integer;
attribute C_HAS_INJECTERR of U0 : label is 0;
attribute C_HAS_MEM_OUTPUT_REGS_A : integer;
attribute C_HAS_MEM_OUTPUT_REGS_A of U0 : label is 1;
attribute C_HAS_MEM_OUTPUT_REGS_B : integer;
attribute C_HAS_MEM_OUTPUT_REGS_B of U0 : label is 0;
attribute C_HAS_MUX_OUTPUT_REGS_A : integer;
attribute C_HAS_MUX_OUTPUT_REGS_A of U0 : label is 0;
attribute C_HAS_MUX_OUTPUT_REGS_B : integer;
attribute C_HAS_MUX_OUTPUT_REGS_B of U0 : label is 0;
attribute C_HAS_REGCEA : integer;
attribute C_HAS_REGCEA of U0 : label is 0;
attribute C_HAS_REGCEB : integer;
attribute C_HAS_REGCEB of U0 : label is 0;
attribute C_HAS_RSTA : integer;
attribute C_HAS_RSTA of U0 : label is 0;
attribute C_HAS_RSTB : integer;
attribute C_HAS_RSTB of U0 : label is 0;
attribute C_HAS_SOFTECC_INPUT_REGS_A : integer;
attribute C_HAS_SOFTECC_INPUT_REGS_A of U0 : label is 0;
attribute C_HAS_SOFTECC_OUTPUT_REGS_B : integer;
attribute C_HAS_SOFTECC_OUTPUT_REGS_B of U0 : label is 0;
attribute C_INITA_VAL : string;
attribute C_INITA_VAL of U0 : label is "0";
attribute C_INITB_VAL : string;
attribute C_INITB_VAL of U0 : label is "0";
attribute C_INIT_FILE : string;
attribute C_INIT_FILE of U0 : label is "bram_1024_0.mem";
attribute C_INIT_FILE_NAME : string;
attribute C_INIT_FILE_NAME of U0 : label is "bram_1024_0.mif";
attribute C_INTERFACE_TYPE : integer;
attribute C_INTERFACE_TYPE of U0 : label is 0;
attribute C_LOAD_INIT_FILE : integer;
attribute C_LOAD_INIT_FILE of U0 : label is 1;
attribute C_MEM_TYPE : integer;
attribute C_MEM_TYPE of U0 : label is 0;
attribute C_MUX_PIPELINE_STAGES : integer;
attribute C_MUX_PIPELINE_STAGES of U0 : label is 0;
attribute C_PRIM_TYPE : integer;
attribute C_PRIM_TYPE of U0 : label is 1;
attribute C_READ_DEPTH_A : integer;
attribute C_READ_DEPTH_A of U0 : label is 1024;
attribute C_READ_DEPTH_B : integer;
attribute C_READ_DEPTH_B of U0 : label is 1024;
attribute C_READ_WIDTH_A : integer;
attribute C_READ_WIDTH_A of U0 : label is 20;
attribute C_READ_WIDTH_B : integer;
attribute C_READ_WIDTH_B of U0 : label is 20;
attribute C_RSTRAM_A : integer;
attribute C_RSTRAM_A of U0 : label is 0;
attribute C_RSTRAM_B : integer;
attribute C_RSTRAM_B of U0 : label is 0;
attribute C_RST_PRIORITY_A : string;
attribute C_RST_PRIORITY_A of U0 : label is "CE";
attribute C_RST_PRIORITY_B : string;
attribute C_RST_PRIORITY_B of U0 : label is "CE";
attribute C_SIM_COLLISION_CHECK : string;
attribute C_SIM_COLLISION_CHECK of U0 : label is "ALL";
attribute C_USE_BRAM_BLOCK : integer;
attribute C_USE_BRAM_BLOCK of U0 : label is 0;
attribute C_USE_BYTE_WEA : integer;
attribute C_USE_BYTE_WEA of U0 : label is 0;
attribute C_USE_BYTE_WEB : integer;
attribute C_USE_BYTE_WEB of U0 : label is 0;
attribute C_USE_DEFAULT_DATA : integer;
attribute C_USE_DEFAULT_DATA of U0 : label is 0;
attribute C_USE_ECC : integer;
attribute C_USE_ECC of U0 : label is 0;
attribute C_USE_SOFTECC : integer;
attribute C_USE_SOFTECC of U0 : label is 0;
attribute C_USE_URAM : integer;
attribute C_USE_URAM of U0 : label is 0;
attribute C_WEA_WIDTH : integer;
attribute C_WEA_WIDTH of U0 : label is 1;
attribute C_WEB_WIDTH : integer;
attribute C_WEB_WIDTH of U0 : label is 1;
attribute C_WRITE_DEPTH_A : integer;
attribute C_WRITE_DEPTH_A of U0 : label is 1024;
attribute C_WRITE_DEPTH_B : integer;
attribute C_WRITE_DEPTH_B of U0 : label is 1024;
attribute C_WRITE_MODE_A : string;
attribute C_WRITE_MODE_A of U0 : label is "WRITE_FIRST";
attribute C_WRITE_MODE_B : string;
attribute C_WRITE_MODE_B of U0 : label is "WRITE_FIRST";
attribute C_WRITE_WIDTH_A : integer;
attribute C_WRITE_WIDTH_A of U0 : label is 20;
attribute C_WRITE_WIDTH_B : integer;
attribute C_WRITE_WIDTH_B of U0 : label is 20;
attribute C_XDEVICEFAMILY : string;
attribute C_XDEVICEFAMILY of U0 : label is "zynq";
attribute downgradeipidentifiedwarnings of U0 : label is "yes";
begin
U0: entity work.bram_1024_0_blk_mem_gen_v8_3_5
port map (
addra(9 downto 0) => addra(9 downto 0),
addrb(9 downto 0) => B"0000000000",
clka => clka,
clkb => '0',
dbiterr => NLW_U0_dbiterr_UNCONNECTED,
deepsleep => '0',
dina(19 downto 0) => dina(19 downto 0),
dinb(19 downto 0) => B"00000000000000000000",
douta(19 downto 0) => douta(19 downto 0),
doutb(19 downto 0) => NLW_U0_doutb_UNCONNECTED(19 downto 0),
eccpipece => '0',
ena => ena,
enb => '0',
injectdbiterr => '0',
injectsbiterr => '0',
rdaddrecc(9 downto 0) => NLW_U0_rdaddrecc_UNCONNECTED(9 downto 0),
regcea => '0',
regceb => '0',
rsta => '0',
rsta_busy => NLW_U0_rsta_busy_UNCONNECTED,
rstb => '0',
rstb_busy => NLW_U0_rstb_busy_UNCONNECTED,
s_aclk => '0',
s_aresetn => '0',
s_axi_araddr(31 downto 0) => B"00000000000000000000000000000000",
s_axi_arburst(1 downto 0) => B"00",
s_axi_arid(3 downto 0) => B"0000",
s_axi_arlen(7 downto 0) => B"00000000",
s_axi_arready => NLW_U0_s_axi_arready_UNCONNECTED,
s_axi_arsize(2 downto 0) => B"000",
s_axi_arvalid => '0',
s_axi_awaddr(31 downto 0) => B"00000000000000000000000000000000",
s_axi_awburst(1 downto 0) => B"00",
s_axi_awid(3 downto 0) => B"0000",
s_axi_awlen(7 downto 0) => B"00000000",
s_axi_awready => NLW_U0_s_axi_awready_UNCONNECTED,
s_axi_awsize(2 downto 0) => B"000",
s_axi_awvalid => '0',
s_axi_bid(3 downto 0) => NLW_U0_s_axi_bid_UNCONNECTED(3 downto 0),
s_axi_bready => '0',
s_axi_bresp(1 downto 0) => NLW_U0_s_axi_bresp_UNCONNECTED(1 downto 0),
s_axi_bvalid => NLW_U0_s_axi_bvalid_UNCONNECTED,
s_axi_dbiterr => NLW_U0_s_axi_dbiterr_UNCONNECTED,
s_axi_injectdbiterr => '0',
s_axi_injectsbiterr => '0',
s_axi_rdaddrecc(9 downto 0) => NLW_U0_s_axi_rdaddrecc_UNCONNECTED(9 downto 0),
s_axi_rdata(19 downto 0) => NLW_U0_s_axi_rdata_UNCONNECTED(19 downto 0),
s_axi_rid(3 downto 0) => NLW_U0_s_axi_rid_UNCONNECTED(3 downto 0),
s_axi_rlast => NLW_U0_s_axi_rlast_UNCONNECTED,
s_axi_rready => '0',
s_axi_rresp(1 downto 0) => NLW_U0_s_axi_rresp_UNCONNECTED(1 downto 0),
s_axi_rvalid => NLW_U0_s_axi_rvalid_UNCONNECTED,
s_axi_sbiterr => NLW_U0_s_axi_sbiterr_UNCONNECTED,
s_axi_wdata(19 downto 0) => B"00000000000000000000",
s_axi_wlast => '0',
s_axi_wready => NLW_U0_s_axi_wready_UNCONNECTED,
s_axi_wstrb(0) => '0',
s_axi_wvalid => '0',
sbiterr => NLW_U0_sbiterr_UNCONNECTED,
shutdown => '0',
sleep => '0',
wea(0) => wea(0),
web(0) => '0'
);
end STRUCTURE;
| unlicense | 37b7cea7b47d5d4de93c3811a1d51d4c | 0.698719 | 3.463418 | false | false | false | false |
grwlf/vsim | vhdl_ct/ct00290.vhd | 1 | 2,626 | -- NEED RESULT: ARCH00290: Physical types passed
-------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
-------------------------------------------------------------------------------
--
-- TEST NAME:
--
-- CT00290
--
-- AUTHOR:
--
-- D. Hyman
--
-- TEST OBJECTIVES:
--
-- 3.1.3 (1)
-- 3.1.3 (2)
-- 3.1.3 (3)
-- 3.1.3 (4)
-- 3.1.3 (5)
-- 3.1.3 (6)
-- 3.1.3 (7)
--
-- DESIGN UNIT ORDERING:
--
-- E00000(ARCH00290)
-- ENT00290_Test_Bench(ARCH00290_Test_Bench)
--
-- REVISION HISTORY:
--
-- 22-JUL-1987 - initial revision
--
-- NOTES:
--
-- self-checking
--
--
use WORK.STANDARD_TYPES.all ;
architecture ARCH00290 of E00000 is
-- this tests 3.1.3 (1), 3.1.3 (4), and 3.1.3 (6)
type physical_integer is range -2147483647 to +2147483647
units
physical_one ;
end units ;
-- this tests 3.1.3 (2), 3.1.3 (5), and 3.1.3 (7)
type backward_integer is range +2147483647 downto -2147483647
units
one ;
ten = 10 one ;
another_ten = ten ;
ten_tens = 10 ten ;
hundred = 100 one ;
five_tens = 5 ten ;
fifty = 50 one ;
another_fifty = 5 another_ten ;
end units ;
-- these will test 3.1.3 (5)
type signed_byte is range -128 to +127 ;
type signed_nibble is range -8 to +7 ;
type something is range signed_nibble'left to signed_byte'right
units
some_one ;
some_ten = 10 some_one ;
end units ;
begin
P :
process
begin
test_report ( "ARCH00290" ,
"Physical types" ,
(physical_integer'pos(physical_one) = 1) and
(physical_integer'val(5) = 5 physical_one) and
(fifty + another_fifty = hundred) and
(2 five_tens = ten_tens) and
(some_ten / 5 = 2 some_one)
) ;
wait ;
end process P ;
end ARCH00290 ;
entity ENT00290_Test_Bench is
end ENT00290_Test_Bench ;
architecture ARCH00290_Test_Bench of ENT00290_Test_Bench is
begin
L1:
block
component UUT
end component ;
for CIS1 : UUT use entity WORK.E00000 ( ARCH00290 ) ;
begin
CIS1 : UUT ;
end block L1 ;
end ARCH00290_Test_Bench ;
| gpl-3.0 | ea505e2a52452054d6eece3a811df8ac | 0.454303 | 3.506008 | false | true | false | false |
grwlf/vsim | vhdl_ct/ct00396.vhd | 1 | 19,997 | -- NEED RESULT: ARCH00396.P1: Multi inertial transactions occurred on concurrent signal asg passed
-- NEED RESULT: ARCH00396.P2: Multi inertial transactions occurred on concurrent signal asg passed
-- NEED RESULT: ARCH00396.P3: Multi inertial transactions occurred on concurrent signal asg passed
-- NEED RESULT: ARCH00396: One inertial transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00396: One inertial transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00396: One inertial transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00396: Old transactions were removed on a concurrent signal asg passed
-- NEED RESULT: ARCH00396: Old transactions were removed on a concurrent signal asg passed
-- NEED RESULT: ARCH00396: Old transactions were removed on a concurrent signal asg passed
-- NEED RESULT: ARCH00396: One inertial transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00396: One inertial transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00396: One inertial transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00396: Inertial semantics check on a concurrent signal asg passed
-- NEED RESULT: ARCH00396: Inertial semantics check on a concurrent signal asg passed
-- NEED RESULT: ARCH00396: Inertial semantics check on a concurrent signal asg passed
-- NEED RESULT: P3: Inertial transactions completed entirely passed
-- NEED RESULT: P2: Inertial transactions completed entirely passed
-- NEED RESULT: P1: Inertial transactions completed entirely passed
-------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
-------------------------------------------------------------------------------
--
-- TEST NAME:
--
-- CT00396
--
-- AUTHOR:
--
-- G. Tominovich
--
-- TEST OBJECTIVES:
--
-- 9.5 (3)
-- 9.5.1 (1)
-- 9.5.1 (2)
--
-- DESIGN UNIT ORDERING:
--
-- ENT00396(ARCH00396)
-- ENT00396_Test_Bench(ARCH00396_Test_Bench)
--
-- REVISION HISTORY:
--
-- 30-JUL-1987 - initial revision
--
-- NOTES:
--
-- self-checking
-- automatically generated
--
use WORK.STANDARD_TYPES.all ;
entity ENT00396 is
port (
s_st_rec1 : inout st_rec1
; s_st_rec2 : inout st_rec2
; s_st_rec3 : inout st_rec3
) ;
subtype chk_sig_type is integer range -1 to 100 ;
signal chk_st_rec1 : chk_sig_type := -1 ;
signal chk_st_rec2 : chk_sig_type := -1 ;
signal chk_st_rec3 : chk_sig_type := -1 ;
--
end ENT00396 ;
--
--
architecture ARCH00396 of ENT00396 is
subtype chk_time_type is Time ;
signal s_st_rec1_savt : chk_time_type := 0 ns ;
signal s_st_rec2_savt : chk_time_type := 0 ns ;
signal s_st_rec3_savt : chk_time_type := 0 ns ;
--
subtype chk_cnt_type is Integer ;
signal s_st_rec1_cnt : chk_cnt_type := 0 ;
signal s_st_rec2_cnt : chk_cnt_type := 0 ;
signal s_st_rec3_cnt : chk_cnt_type := 0 ;
--
type select_type is range 1 to 6 ;
signal st_rec1_select : select_type := 1 ;
signal st_rec2_select : select_type := 1 ;
signal st_rec3_select : select_type := 1 ;
--
begin
CHG1 :
process
variable correct : boolean ;
begin
case s_st_rec1_cnt is
when 0
=> null ;
-- s_st_rec1.f2 <=
-- c_st_rec1_2.f2 after 10 ns,
-- c_st_rec1_1.f2 after 20 ns ;
--
when 1
=> correct :=
s_st_rec1.f2 =
c_st_rec1_2.f2 and
(s_st_rec1_savt + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_rec1.f2 =
c_st_rec1_1.f2 and
(s_st_rec1_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00396.P1" ,
"Multi inertial transactions occurred on " &
"concurrent signal asg",
correct ) ;
--
st_rec1_select <= transport 2 ;
-- s_st_rec1.f2 <=
-- c_st_rec1_2.f2 after 10 ns ,
-- c_st_rec1_1.f2 after 20 ns ,
-- c_st_rec1_2.f2 after 30 ns ,
-- c_st_rec1_1.f2 after 40 ns ;
--
when 3
=> correct :=
s_st_rec1.f2 =
c_st_rec1_2.f2 and
(s_st_rec1_savt + 10 ns) = Std.Standard.Now ;
st_rec1_select <= transport 3 ;
-- s_st_rec1.f2 <=
-- c_st_rec1_1.f2 after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_rec1.f2 =
c_st_rec1_1.f2 and
(s_st_rec1_savt + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00396" ,
"One inertial transaction occurred on a " &
"concurrent signal asg",
correct ) ;
st_rec1_select <= transport 4 ;
-- s_st_rec1.f2 <=
-- c_st_rec1_1.f2 after 100 ns ;
--
when 5
=> correct :=
correct and
s_st_rec1.f2 =
c_st_rec1_1.f2 and
(s_st_rec1_savt + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00396" ,
"Old transactions were removed on a " &
"concurrent signal asg",
correct ) ;
st_rec1_select <= transport 5 ;
-- s_st_rec1.f2 <=
-- c_st_rec1_2.f2 after 10 ns ,
-- c_st_rec1_1.f2 after 20 ns ,
-- c_st_rec1_2.f2 after 30 ns ,
-- c_st_rec1_1.f2 after 40 ns ;
--
when 6
=> correct :=
correct and
s_st_rec1.f2 =
c_st_rec1_2.f2 and
(s_st_rec1_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00396" ,
"One inertial transaction occurred on a " &
"concurrent signal asg",
correct ) ;
st_rec1_select <= transport 6 ;
-- Last transaction above is marked
-- s_st_rec1.f2 <=
-- c_st_rec1_1.f2 after 40 ns ;
--
when 7
=> correct :=
correct and
s_st_rec1.f2 =
c_st_rec1_1.f2 and
(s_st_rec1_savt + 30 ns) = Std.Standard.Now ;
--
when 8
=> correct :=
correct and
s_st_rec1.f2 =
c_st_rec1_1.f2 and
(s_st_rec1_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00396" ,
"Inertial semantics check on a concurrent " &
"signal asg",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00396" ,
"Inertial semantics check on a concurrent " &
"signal asg",
false ) ;
--
end case ;
--
s_st_rec1_savt <= transport Std.Standard.Now ;
chk_st_rec1 <= transport s_st_rec1_cnt
after (1 us - Std.Standard.Now) ;
s_st_rec1_cnt <= transport s_st_rec1_cnt + 1 ;
wait until (not s_st_rec1.f2'Quiet) and
(s_st_rec1_savt /= Std.Standard.Now) ;
--
end process CHG1 ;
--
PGEN_CHKP_1 :
process ( chk_st_rec1 )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P1" ,
"Inertial transactions completed entirely",
chk_st_rec1 = 8 ) ;
end if ;
end process PGEN_CHKP_1 ;
--
--
s_st_rec1.f2 <=
c_st_rec1_2.f2 after 10 ns,
c_st_rec1_1.f2 after 20 ns
when st_rec1_select = 1 else
--
c_st_rec1_2.f2 after 10 ns ,
c_st_rec1_1.f2 after 20 ns ,
c_st_rec1_2.f2 after 30 ns ,
c_st_rec1_1.f2 after 40 ns
when st_rec1_select = 2 else
--
c_st_rec1_1.f2 after 5 ns
when st_rec1_select = 3 else
--
c_st_rec1_1.f2 after 100 ns
when st_rec1_select = 4 else
--
c_st_rec1_2.f2 after 10 ns ,
c_st_rec1_1.f2 after 20 ns ,
c_st_rec1_2.f2 after 30 ns ,
c_st_rec1_1.f2 after 40 ns
when st_rec1_select = 5 else
--
-- Last transaction above is marked
c_st_rec1_1.f2 after 40 ns ;
--
CHG2 :
process
variable correct : boolean ;
begin
case s_st_rec2_cnt is
when 0
=> null ;
-- s_st_rec2.f2 <=
-- c_st_rec2_2.f2 after 10 ns,
-- c_st_rec2_1.f2 after 20 ns ;
--
when 1
=> correct :=
s_st_rec2.f2 =
c_st_rec2_2.f2 and
(s_st_rec2_savt + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_rec2.f2 =
c_st_rec2_1.f2 and
(s_st_rec2_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00396.P2" ,
"Multi inertial transactions occurred on " &
"concurrent signal asg",
correct ) ;
--
st_rec2_select <= transport 2 ;
-- s_st_rec2.f2 <=
-- c_st_rec2_2.f2 after 10 ns ,
-- c_st_rec2_1.f2 after 20 ns ,
-- c_st_rec2_2.f2 after 30 ns ,
-- c_st_rec2_1.f2 after 40 ns ;
--
when 3
=> correct :=
s_st_rec2.f2 =
c_st_rec2_2.f2 and
(s_st_rec2_savt + 10 ns) = Std.Standard.Now ;
st_rec2_select <= transport 3 ;
-- s_st_rec2.f2 <=
-- c_st_rec2_1.f2 after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_rec2.f2 =
c_st_rec2_1.f2 and
(s_st_rec2_savt + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00396" ,
"One inertial transaction occurred on a " &
"concurrent signal asg",
correct ) ;
st_rec2_select <= transport 4 ;
-- s_st_rec2.f2 <=
-- c_st_rec2_1.f2 after 100 ns ;
--
when 5
=> correct :=
correct and
s_st_rec2.f2 =
c_st_rec2_1.f2 and
(s_st_rec2_savt + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00396" ,
"Old transactions were removed on a " &
"concurrent signal asg",
correct ) ;
st_rec2_select <= transport 5 ;
-- s_st_rec2.f2 <=
-- c_st_rec2_2.f2 after 10 ns ,
-- c_st_rec2_1.f2 after 20 ns ,
-- c_st_rec2_2.f2 after 30 ns ,
-- c_st_rec2_1.f2 after 40 ns ;
--
when 6
=> correct :=
correct and
s_st_rec2.f2 =
c_st_rec2_2.f2 and
(s_st_rec2_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00396" ,
"One inertial transaction occurred on a " &
"concurrent signal asg",
correct ) ;
st_rec2_select <= transport 6 ;
-- Last transaction above is marked
-- s_st_rec2.f2 <=
-- c_st_rec2_1.f2 after 40 ns ;
--
when 7
=> correct :=
correct and
s_st_rec2.f2 =
c_st_rec2_1.f2 and
(s_st_rec2_savt + 30 ns) = Std.Standard.Now ;
--
when 8
=> correct :=
correct and
s_st_rec2.f2 =
c_st_rec2_1.f2 and
(s_st_rec2_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00396" ,
"Inertial semantics check on a concurrent " &
"signal asg",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00396" ,
"Inertial semantics check on a concurrent " &
"signal asg",
false ) ;
--
end case ;
--
s_st_rec2_savt <= transport Std.Standard.Now ;
chk_st_rec2 <= transport s_st_rec2_cnt
after (1 us - Std.Standard.Now) ;
s_st_rec2_cnt <= transport s_st_rec2_cnt + 1 ;
wait until (not s_st_rec2.f2'Quiet) and
(s_st_rec2_savt /= Std.Standard.Now) ;
--
end process CHG2 ;
--
PGEN_CHKP_2 :
process ( chk_st_rec2 )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P2" ,
"Inertial transactions completed entirely",
chk_st_rec2 = 8 ) ;
end if ;
end process PGEN_CHKP_2 ;
--
--
s_st_rec2.f2 <=
c_st_rec2_2.f2 after 10 ns,
c_st_rec2_1.f2 after 20 ns
when st_rec2_select = 1 else
--
c_st_rec2_2.f2 after 10 ns ,
c_st_rec2_1.f2 after 20 ns ,
c_st_rec2_2.f2 after 30 ns ,
c_st_rec2_1.f2 after 40 ns
when st_rec2_select = 2 else
--
c_st_rec2_1.f2 after 5 ns
when st_rec2_select = 3 else
--
c_st_rec2_1.f2 after 100 ns
when st_rec2_select = 4 else
--
c_st_rec2_2.f2 after 10 ns ,
c_st_rec2_1.f2 after 20 ns ,
c_st_rec2_2.f2 after 30 ns ,
c_st_rec2_1.f2 after 40 ns
when st_rec2_select = 5 else
--
-- Last transaction above is marked
c_st_rec2_1.f2 after 40 ns ;
--
CHG3 :
process
variable correct : boolean ;
begin
case s_st_rec3_cnt is
when 0
=> null ;
-- s_st_rec3.f2 <=
-- c_st_rec3_2.f2 after 10 ns,
-- c_st_rec3_1.f2 after 20 ns ;
--
when 1
=> correct :=
s_st_rec3.f2 =
c_st_rec3_2.f2 and
(s_st_rec3_savt + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_rec3.f2 =
c_st_rec3_1.f2 and
(s_st_rec3_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00396.P3" ,
"Multi inertial transactions occurred on " &
"concurrent signal asg",
correct ) ;
--
st_rec3_select <= transport 2 ;
-- s_st_rec3.f2 <=
-- c_st_rec3_2.f2 after 10 ns ,
-- c_st_rec3_1.f2 after 20 ns ,
-- c_st_rec3_2.f2 after 30 ns ,
-- c_st_rec3_1.f2 after 40 ns ;
--
when 3
=> correct :=
s_st_rec3.f2 =
c_st_rec3_2.f2 and
(s_st_rec3_savt + 10 ns) = Std.Standard.Now ;
st_rec3_select <= transport 3 ;
-- s_st_rec3.f2 <=
-- c_st_rec3_1.f2 after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_rec3.f2 =
c_st_rec3_1.f2 and
(s_st_rec3_savt + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00396" ,
"One inertial transaction occurred on a " &
"concurrent signal asg",
correct ) ;
st_rec3_select <= transport 4 ;
-- s_st_rec3.f2 <=
-- c_st_rec3_1.f2 after 100 ns ;
--
when 5
=> correct :=
correct and
s_st_rec3.f2 =
c_st_rec3_1.f2 and
(s_st_rec3_savt + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00396" ,
"Old transactions were removed on a " &
"concurrent signal asg",
correct ) ;
st_rec3_select <= transport 5 ;
-- s_st_rec3.f2 <=
-- c_st_rec3_2.f2 after 10 ns ,
-- c_st_rec3_1.f2 after 20 ns ,
-- c_st_rec3_2.f2 after 30 ns ,
-- c_st_rec3_1.f2 after 40 ns ;
--
when 6
=> correct :=
correct and
s_st_rec3.f2 =
c_st_rec3_2.f2 and
(s_st_rec3_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00396" ,
"One inertial transaction occurred on a " &
"concurrent signal asg",
correct ) ;
st_rec3_select <= transport 6 ;
-- Last transaction above is marked
-- s_st_rec3.f2 <=
-- c_st_rec3_1.f2 after 40 ns ;
--
when 7
=> correct :=
correct and
s_st_rec3.f2 =
c_st_rec3_1.f2 and
(s_st_rec3_savt + 30 ns) = Std.Standard.Now ;
--
when 8
=> correct :=
correct and
s_st_rec3.f2 =
c_st_rec3_1.f2 and
(s_st_rec3_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00396" ,
"Inertial semantics check on a concurrent " &
"signal asg",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00396" ,
"Inertial semantics check on a concurrent " &
"signal asg",
false ) ;
--
end case ;
--
s_st_rec3_savt <= transport Std.Standard.Now ;
chk_st_rec3 <= transport s_st_rec3_cnt
after (1 us - Std.Standard.Now) ;
s_st_rec3_cnt <= transport s_st_rec3_cnt + 1 ;
wait until (not s_st_rec3.f2'Quiet) and
(s_st_rec3_savt /= Std.Standard.Now) ;
--
end process CHG3 ;
--
PGEN_CHKP_3 :
process ( chk_st_rec3 )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P3" ,
"Inertial transactions completed entirely",
chk_st_rec3 = 8 ) ;
end if ;
end process PGEN_CHKP_3 ;
--
--
s_st_rec3.f2 <=
c_st_rec3_2.f2 after 10 ns,
c_st_rec3_1.f2 after 20 ns
when st_rec3_select = 1 else
--
c_st_rec3_2.f2 after 10 ns ,
c_st_rec3_1.f2 after 20 ns ,
c_st_rec3_2.f2 after 30 ns ,
c_st_rec3_1.f2 after 40 ns
when st_rec3_select = 2 else
--
c_st_rec3_1.f2 after 5 ns
when st_rec3_select = 3 else
--
c_st_rec3_1.f2 after 100 ns
when st_rec3_select = 4 else
--
c_st_rec3_2.f2 after 10 ns ,
c_st_rec3_1.f2 after 20 ns ,
c_st_rec3_2.f2 after 30 ns ,
c_st_rec3_1.f2 after 40 ns
when st_rec3_select = 5 else
--
-- Last transaction above is marked
c_st_rec3_1.f2 after 40 ns ;
--
end ARCH00396 ;
--
--
use WORK.STANDARD_TYPES.all ;
entity ENT00396_Test_Bench is
signal s_st_rec1 : st_rec1
:= c_st_rec1_1 ;
signal s_st_rec2 : st_rec2
:= c_st_rec2_1 ;
signal s_st_rec3 : st_rec3
:= c_st_rec3_1 ;
--
end ENT00396_Test_Bench ;
--
--
architecture ARCH00396_Test_Bench of ENT00396_Test_Bench is
begin
L1:
block
component UUT
port (
s_st_rec1 : inout st_rec1
; s_st_rec2 : inout st_rec2
; s_st_rec3 : inout st_rec3
) ;
end component ;
--
for CIS1 : UUT use entity WORK.ENT00396 ( ARCH00396 ) ;
begin
CIS1 : UUT
port map (
s_st_rec1
, s_st_rec2
, s_st_rec3
)
;
end block L1 ;
end ARCH00396_Test_Bench ;
| gpl-3.0 | f01a12e49029e5d6023ad7aba336b403 | 0.46962 | 3.337283 | false | false | false | false |
jairov4/accel-oil | impl/impl_test_single/hdl/system_ilmb_cntlr_wrapper.vhd | 1 | 18,461 | -------------------------------------------------------------------------------
-- system_ilmb_cntlr_wrapper.vhd
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
library lmb_bram_if_cntlr_v3_10_c;
use lmb_bram_if_cntlr_v3_10_c.all;
entity system_ilmb_cntlr_wrapper is
port (
LMB_Clk : in std_logic;
LMB_Rst : in std_logic;
LMB_ABus : in std_logic_vector(0 to 31);
LMB_WriteDBus : in std_logic_vector(0 to 31);
LMB_AddrStrobe : in std_logic;
LMB_ReadStrobe : in std_logic;
LMB_WriteStrobe : in std_logic;
LMB_BE : in std_logic_vector(0 to 3);
Sl_DBus : out std_logic_vector(0 to 31);
Sl_Ready : out std_logic;
Sl_Wait : out std_logic;
Sl_UE : out std_logic;
Sl_CE : out std_logic;
LMB1_ABus : in std_logic_vector(0 to 31);
LMB1_WriteDBus : in std_logic_vector(0 to 31);
LMB1_AddrStrobe : in std_logic;
LMB1_ReadStrobe : in std_logic;
LMB1_WriteStrobe : in std_logic;
LMB1_BE : in std_logic_vector(0 to 3);
Sl1_DBus : out std_logic_vector(0 to 31);
Sl1_Ready : out std_logic;
Sl1_Wait : out std_logic;
Sl1_UE : out std_logic;
Sl1_CE : out std_logic;
LMB2_ABus : in std_logic_vector(0 to 31);
LMB2_WriteDBus : in std_logic_vector(0 to 31);
LMB2_AddrStrobe : in std_logic;
LMB2_ReadStrobe : in std_logic;
LMB2_WriteStrobe : in std_logic;
LMB2_BE : in std_logic_vector(0 to 3);
Sl2_DBus : out std_logic_vector(0 to 31);
Sl2_Ready : out std_logic;
Sl2_Wait : out std_logic;
Sl2_UE : out std_logic;
Sl2_CE : out std_logic;
LMB3_ABus : in std_logic_vector(0 to 31);
LMB3_WriteDBus : in std_logic_vector(0 to 31);
LMB3_AddrStrobe : in std_logic;
LMB3_ReadStrobe : in std_logic;
LMB3_WriteStrobe : in std_logic;
LMB3_BE : in std_logic_vector(0 to 3);
Sl3_DBus : out std_logic_vector(0 to 31);
Sl3_Ready : out std_logic;
Sl3_Wait : out std_logic;
Sl3_UE : out std_logic;
Sl3_CE : out std_logic;
BRAM_Rst_A : out std_logic;
BRAM_Clk_A : out std_logic;
BRAM_EN_A : out std_logic;
BRAM_WEN_A : out std_logic_vector(0 to 3);
BRAM_Addr_A : out std_logic_vector(0 to 31);
BRAM_Din_A : in std_logic_vector(0 to 31);
BRAM_Dout_A : out std_logic_vector(0 to 31);
Interrupt : out std_logic;
UE : out std_logic;
CE : out std_logic;
SPLB_CTRL_PLB_ABus : in std_logic_vector(0 to 31);
SPLB_CTRL_PLB_PAValid : in std_logic;
SPLB_CTRL_PLB_masterID : in std_logic_vector(0 to 0);
SPLB_CTRL_PLB_RNW : in std_logic;
SPLB_CTRL_PLB_BE : in std_logic_vector(0 to 3);
SPLB_CTRL_PLB_size : in std_logic_vector(0 to 3);
SPLB_CTRL_PLB_type : in std_logic_vector(0 to 2);
SPLB_CTRL_PLB_wrDBus : in std_logic_vector(0 to 31);
SPLB_CTRL_Sl_addrAck : out std_logic;
SPLB_CTRL_Sl_SSize : out std_logic_vector(0 to 1);
SPLB_CTRL_Sl_wait : out std_logic;
SPLB_CTRL_Sl_rearbitrate : out std_logic;
SPLB_CTRL_Sl_wrDAck : out std_logic;
SPLB_CTRL_Sl_wrComp : out std_logic;
SPLB_CTRL_Sl_rdDBus : out std_logic_vector(0 to 31);
SPLB_CTRL_Sl_rdDAck : out std_logic;
SPLB_CTRL_Sl_rdComp : out std_logic;
SPLB_CTRL_Sl_MBusy : out std_logic_vector(0 to 0);
SPLB_CTRL_Sl_MWrErr : out std_logic_vector(0 to 0);
SPLB_CTRL_Sl_MRdErr : out std_logic_vector(0 to 0);
SPLB_CTRL_PLB_UABus : in std_logic_vector(0 to 31);
SPLB_CTRL_PLB_SAValid : in std_logic;
SPLB_CTRL_PLB_rdPrim : in std_logic;
SPLB_CTRL_PLB_wrPrim : in std_logic;
SPLB_CTRL_PLB_abort : in std_logic;
SPLB_CTRL_PLB_busLock : in std_logic;
SPLB_CTRL_PLB_MSize : in std_logic_vector(0 to 1);
SPLB_CTRL_PLB_lockErr : in std_logic;
SPLB_CTRL_PLB_wrBurst : in std_logic;
SPLB_CTRL_PLB_rdBurst : in std_logic;
SPLB_CTRL_PLB_wrPendReq : in std_logic;
SPLB_CTRL_PLB_rdPendReq : in std_logic;
SPLB_CTRL_PLB_wrPendPri : in std_logic_vector(0 to 1);
SPLB_CTRL_PLB_rdPendPri : in std_logic_vector(0 to 1);
SPLB_CTRL_PLB_reqPri : in std_logic_vector(0 to 1);
SPLB_CTRL_PLB_TAttribute : in std_logic_vector(0 to 15);
SPLB_CTRL_Sl_wrBTerm : out std_logic;
SPLB_CTRL_Sl_rdWdAddr : out std_logic_vector(0 to 3);
SPLB_CTRL_Sl_rdBTerm : out std_logic;
SPLB_CTRL_Sl_MIRQ : out std_logic_vector(0 to 0);
S_AXI_CTRL_ACLK : in std_logic;
S_AXI_CTRL_ARESETN : in std_logic;
S_AXI_CTRL_AWADDR : in std_logic_vector(31 downto 0);
S_AXI_CTRL_AWVALID : in std_logic;
S_AXI_CTRL_AWREADY : out std_logic;
S_AXI_CTRL_WDATA : in std_logic_vector(31 downto 0);
S_AXI_CTRL_WSTRB : in std_logic_vector(3 downto 0);
S_AXI_CTRL_WVALID : in std_logic;
S_AXI_CTRL_WREADY : out std_logic;
S_AXI_CTRL_BRESP : out std_logic_vector(1 downto 0);
S_AXI_CTRL_BVALID : out std_logic;
S_AXI_CTRL_BREADY : in std_logic;
S_AXI_CTRL_ARADDR : in std_logic_vector(31 downto 0);
S_AXI_CTRL_ARVALID : in std_logic;
S_AXI_CTRL_ARREADY : out std_logic;
S_AXI_CTRL_RDATA : out std_logic_vector(31 downto 0);
S_AXI_CTRL_RRESP : out std_logic_vector(1 downto 0);
S_AXI_CTRL_RVALID : out std_logic;
S_AXI_CTRL_RREADY : in std_logic
);
attribute x_core_info : STRING;
attribute x_core_info of system_ilmb_cntlr_wrapper : entity is "lmb_bram_if_cntlr_v3_10_c";
end system_ilmb_cntlr_wrapper;
architecture STRUCTURE of system_ilmb_cntlr_wrapper is
component lmb_bram_if_cntlr is
generic (
C_BASEADDR : std_logic_vector(0 to 31);
C_HIGHADDR : std_logic_vector(0 to 31);
C_FAMILY : string;
C_MASK : std_logic_vector(0 to 31);
C_MASK1 : std_logic_vector(0 to 31);
C_MASK2 : std_logic_vector(0 to 31);
C_MASK3 : std_logic_vector(0 to 31);
C_LMB_AWIDTH : integer;
C_LMB_DWIDTH : integer;
C_ECC : integer;
C_INTERCONNECT : integer;
C_FAULT_INJECT : integer;
C_CE_FAILING_REGISTERS : integer;
C_UE_FAILING_REGISTERS : integer;
C_ECC_STATUS_REGISTERS : integer;
C_ECC_ONOFF_REGISTER : integer;
C_ECC_ONOFF_RESET_VALUE : integer;
C_CE_COUNTER_WIDTH : integer;
C_WRITE_ACCESS : integer;
C_NUM_LMB : integer;
C_SPLB_CTRL_BASEADDR : std_logic_vector;
C_SPLB_CTRL_HIGHADDR : std_logic_vector;
C_SPLB_CTRL_AWIDTH : INTEGER;
C_SPLB_CTRL_DWIDTH : INTEGER;
C_SPLB_CTRL_P2P : INTEGER;
C_SPLB_CTRL_MID_WIDTH : INTEGER;
C_SPLB_CTRL_NUM_MASTERS : INTEGER;
C_SPLB_CTRL_SUPPORT_BURSTS : INTEGER;
C_SPLB_CTRL_NATIVE_DWIDTH : INTEGER;
C_S_AXI_CTRL_BASEADDR : std_logic_vector(31 downto 0);
C_S_AXI_CTRL_HIGHADDR : std_logic_vector(31 downto 0);
C_S_AXI_CTRL_ADDR_WIDTH : INTEGER;
C_S_AXI_CTRL_DATA_WIDTH : INTEGER
);
port (
LMB_Clk : in std_logic;
LMB_Rst : in std_logic;
LMB_ABus : in std_logic_vector(0 to C_LMB_AWIDTH-1);
LMB_WriteDBus : in std_logic_vector(0 to C_LMB_DWIDTH-1);
LMB_AddrStrobe : in std_logic;
LMB_ReadStrobe : in std_logic;
LMB_WriteStrobe : in std_logic;
LMB_BE : in std_logic_vector(0 to C_LMB_DWIDTH/8-1);
Sl_DBus : out std_logic_vector(0 to C_LMB_DWIDTH-1);
Sl_Ready : out std_logic;
Sl_Wait : out std_logic;
Sl_UE : out std_logic;
Sl_CE : out std_logic;
LMB1_ABus : in std_logic_vector(0 to C_LMB_AWIDTH-1);
LMB1_WriteDBus : in std_logic_vector(0 to C_LMB_DWIDTH-1);
LMB1_AddrStrobe : in std_logic;
LMB1_ReadStrobe : in std_logic;
LMB1_WriteStrobe : in std_logic;
LMB1_BE : in std_logic_vector(0 to C_LMB_DWIDTH/8-1);
Sl1_DBus : out std_logic_vector(0 to C_LMB_DWIDTH-1);
Sl1_Ready : out std_logic;
Sl1_Wait : out std_logic;
Sl1_UE : out std_logic;
Sl1_CE : out std_logic;
LMB2_ABus : in std_logic_vector(0 to C_LMB_AWIDTH-1);
LMB2_WriteDBus : in std_logic_vector(0 to C_LMB_DWIDTH-1);
LMB2_AddrStrobe : in std_logic;
LMB2_ReadStrobe : in std_logic;
LMB2_WriteStrobe : in std_logic;
LMB2_BE : in std_logic_vector(0 to C_LMB_DWIDTH/8-1);
Sl2_DBus : out std_logic_vector(0 to C_LMB_DWIDTH-1);
Sl2_Ready : out std_logic;
Sl2_Wait : out std_logic;
Sl2_UE : out std_logic;
Sl2_CE : out std_logic;
LMB3_ABus : in std_logic_vector(0 to C_LMB_AWIDTH-1);
LMB3_WriteDBus : in std_logic_vector(0 to C_LMB_DWIDTH-1);
LMB3_AddrStrobe : in std_logic;
LMB3_ReadStrobe : in std_logic;
LMB3_WriteStrobe : in std_logic;
LMB3_BE : in std_logic_vector(0 to C_LMB_DWIDTH/8-1);
Sl3_DBus : out std_logic_vector(0 to C_LMB_DWIDTH-1);
Sl3_Ready : out std_logic;
Sl3_Wait : out std_logic;
Sl3_UE : out std_logic;
Sl3_CE : out std_logic;
BRAM_Rst_A : out std_logic;
BRAM_Clk_A : out std_logic;
BRAM_EN_A : out std_logic;
BRAM_WEN_A : out std_logic_vector(0 to ((C_LMB_DWIDTH+8*C_ECC)/8)-1);
BRAM_Addr_A : out std_logic_vector(0 to C_LMB_AWIDTH-1);
BRAM_Din_A : in std_logic_vector(0 to C_LMB_DWIDTH-1+8*C_ECC);
BRAM_Dout_A : out std_logic_vector(0 to C_LMB_DWIDTH-1+8*C_ECC);
Interrupt : out std_logic;
UE : out std_logic;
CE : out std_logic;
SPLB_CTRL_PLB_ABus : in std_logic_vector(0 to 31);
SPLB_CTRL_PLB_PAValid : in std_logic;
SPLB_CTRL_PLB_masterID : in std_logic_vector(0 to (C_SPLB_CTRL_MID_WIDTH-1));
SPLB_CTRL_PLB_RNW : in std_logic;
SPLB_CTRL_PLB_BE : in std_logic_vector(0 to ((C_SPLB_CTRL_DWIDTH/8)-1));
SPLB_CTRL_PLB_size : in std_logic_vector(0 to 3);
SPLB_CTRL_PLB_type : in std_logic_vector(0 to 2);
SPLB_CTRL_PLB_wrDBus : in std_logic_vector(0 to (C_SPLB_CTRL_DWIDTH-1));
SPLB_CTRL_Sl_addrAck : out std_logic;
SPLB_CTRL_Sl_SSize : out std_logic_vector(0 to 1);
SPLB_CTRL_Sl_wait : out std_logic;
SPLB_CTRL_Sl_rearbitrate : out std_logic;
SPLB_CTRL_Sl_wrDAck : out std_logic;
SPLB_CTRL_Sl_wrComp : out std_logic;
SPLB_CTRL_Sl_rdDBus : out std_logic_vector(0 to (C_SPLB_CTRL_DWIDTH-1));
SPLB_CTRL_Sl_rdDAck : out std_logic;
SPLB_CTRL_Sl_rdComp : out std_logic;
SPLB_CTRL_Sl_MBusy : out std_logic_vector(0 to (C_SPLB_CTRL_NUM_MASTERS-1));
SPLB_CTRL_Sl_MWrErr : out std_logic_vector(0 to (C_SPLB_CTRL_NUM_MASTERS-1));
SPLB_CTRL_Sl_MRdErr : out std_logic_vector(0 to (C_SPLB_CTRL_NUM_MASTERS-1));
SPLB_CTRL_PLB_UABus : in std_logic_vector(0 to 31);
SPLB_CTRL_PLB_SAValid : in std_logic;
SPLB_CTRL_PLB_rdPrim : in std_logic;
SPLB_CTRL_PLB_wrPrim : in std_logic;
SPLB_CTRL_PLB_abort : in std_logic;
SPLB_CTRL_PLB_busLock : in std_logic;
SPLB_CTRL_PLB_MSize : in std_logic_vector(0 to 1);
SPLB_CTRL_PLB_lockErr : in std_logic;
SPLB_CTRL_PLB_wrBurst : in std_logic;
SPLB_CTRL_PLB_rdBurst : in std_logic;
SPLB_CTRL_PLB_wrPendReq : in std_logic;
SPLB_CTRL_PLB_rdPendReq : in std_logic;
SPLB_CTRL_PLB_wrPendPri : in std_logic_vector(0 to 1);
SPLB_CTRL_PLB_rdPendPri : in std_logic_vector(0 to 1);
SPLB_CTRL_PLB_reqPri : in std_logic_vector(0 to 1);
SPLB_CTRL_PLB_TAttribute : in std_logic_vector(0 to 15);
SPLB_CTRL_Sl_wrBTerm : out std_logic;
SPLB_CTRL_Sl_rdWdAddr : out std_logic_vector(0 to 3);
SPLB_CTRL_Sl_rdBTerm : out std_logic;
SPLB_CTRL_Sl_MIRQ : out std_logic_vector(0 to (C_SPLB_CTRL_NUM_MASTERS-1));
S_AXI_CTRL_ACLK : in std_logic;
S_AXI_CTRL_ARESETN : in std_logic;
S_AXI_CTRL_AWADDR : in std_logic_vector((C_S_AXI_CTRL_ADDR_WIDTH-1) downto 0);
S_AXI_CTRL_AWVALID : in std_logic;
S_AXI_CTRL_AWREADY : out std_logic;
S_AXI_CTRL_WDATA : in std_logic_vector((C_S_AXI_CTRL_DATA_WIDTH-1) downto 0);
S_AXI_CTRL_WSTRB : in std_logic_vector(((C_S_AXI_CTRL_DATA_WIDTH/8)-1) downto 0);
S_AXI_CTRL_WVALID : in std_logic;
S_AXI_CTRL_WREADY : out std_logic;
S_AXI_CTRL_BRESP : out std_logic_vector(1 downto 0);
S_AXI_CTRL_BVALID : out std_logic;
S_AXI_CTRL_BREADY : in std_logic;
S_AXI_CTRL_ARADDR : in std_logic_vector((C_S_AXI_CTRL_ADDR_WIDTH-1) downto 0);
S_AXI_CTRL_ARVALID : in std_logic;
S_AXI_CTRL_ARREADY : out std_logic;
S_AXI_CTRL_RDATA : out std_logic_vector((C_S_AXI_CTRL_DATA_WIDTH-1) downto 0);
S_AXI_CTRL_RRESP : out std_logic_vector(1 downto 0);
S_AXI_CTRL_RVALID : out std_logic;
S_AXI_CTRL_RREADY : in std_logic
);
end component;
begin
ilmb_cntlr : lmb_bram_if_cntlr
generic map (
C_BASEADDR => X"00000000",
C_HIGHADDR => X"00003FFF",
C_FAMILY => "virtex5",
C_MASK => X"80000000",
C_MASK1 => X"00800000",
C_MASK2 => X"00800000",
C_MASK3 => X"00800000",
C_LMB_AWIDTH => 32,
C_LMB_DWIDTH => 32,
C_ECC => 0,
C_INTERCONNECT => 0,
C_FAULT_INJECT => 0,
C_CE_FAILING_REGISTERS => 0,
C_UE_FAILING_REGISTERS => 0,
C_ECC_STATUS_REGISTERS => 0,
C_ECC_ONOFF_REGISTER => 0,
C_ECC_ONOFF_RESET_VALUE => 1,
C_CE_COUNTER_WIDTH => 0,
C_WRITE_ACCESS => 2,
C_NUM_LMB => 1,
C_SPLB_CTRL_BASEADDR => X"FFFFFFFF",
C_SPLB_CTRL_HIGHADDR => X"00000000",
C_SPLB_CTRL_AWIDTH => 32,
C_SPLB_CTRL_DWIDTH => 32,
C_SPLB_CTRL_P2P => 0,
C_SPLB_CTRL_MID_WIDTH => 1,
C_SPLB_CTRL_NUM_MASTERS => 1,
C_SPLB_CTRL_SUPPORT_BURSTS => 0,
C_SPLB_CTRL_NATIVE_DWIDTH => 32,
C_S_AXI_CTRL_BASEADDR => X"FFFFFFFF",
C_S_AXI_CTRL_HIGHADDR => X"00000000",
C_S_AXI_CTRL_ADDR_WIDTH => 32,
C_S_AXI_CTRL_DATA_WIDTH => 32
)
port map (
LMB_Clk => LMB_Clk,
LMB_Rst => LMB_Rst,
LMB_ABus => LMB_ABus,
LMB_WriteDBus => LMB_WriteDBus,
LMB_AddrStrobe => LMB_AddrStrobe,
LMB_ReadStrobe => LMB_ReadStrobe,
LMB_WriteStrobe => LMB_WriteStrobe,
LMB_BE => LMB_BE,
Sl_DBus => Sl_DBus,
Sl_Ready => Sl_Ready,
Sl_Wait => Sl_Wait,
Sl_UE => Sl_UE,
Sl_CE => Sl_CE,
LMB1_ABus => LMB1_ABus,
LMB1_WriteDBus => LMB1_WriteDBus,
LMB1_AddrStrobe => LMB1_AddrStrobe,
LMB1_ReadStrobe => LMB1_ReadStrobe,
LMB1_WriteStrobe => LMB1_WriteStrobe,
LMB1_BE => LMB1_BE,
Sl1_DBus => Sl1_DBus,
Sl1_Ready => Sl1_Ready,
Sl1_Wait => Sl1_Wait,
Sl1_UE => Sl1_UE,
Sl1_CE => Sl1_CE,
LMB2_ABus => LMB2_ABus,
LMB2_WriteDBus => LMB2_WriteDBus,
LMB2_AddrStrobe => LMB2_AddrStrobe,
LMB2_ReadStrobe => LMB2_ReadStrobe,
LMB2_WriteStrobe => LMB2_WriteStrobe,
LMB2_BE => LMB2_BE,
Sl2_DBus => Sl2_DBus,
Sl2_Ready => Sl2_Ready,
Sl2_Wait => Sl2_Wait,
Sl2_UE => Sl2_UE,
Sl2_CE => Sl2_CE,
LMB3_ABus => LMB3_ABus,
LMB3_WriteDBus => LMB3_WriteDBus,
LMB3_AddrStrobe => LMB3_AddrStrobe,
LMB3_ReadStrobe => LMB3_ReadStrobe,
LMB3_WriteStrobe => LMB3_WriteStrobe,
LMB3_BE => LMB3_BE,
Sl3_DBus => Sl3_DBus,
Sl3_Ready => Sl3_Ready,
Sl3_Wait => Sl3_Wait,
Sl3_UE => Sl3_UE,
Sl3_CE => Sl3_CE,
BRAM_Rst_A => BRAM_Rst_A,
BRAM_Clk_A => BRAM_Clk_A,
BRAM_EN_A => BRAM_EN_A,
BRAM_WEN_A => BRAM_WEN_A,
BRAM_Addr_A => BRAM_Addr_A,
BRAM_Din_A => BRAM_Din_A,
BRAM_Dout_A => BRAM_Dout_A,
Interrupt => Interrupt,
UE => UE,
CE => CE,
SPLB_CTRL_PLB_ABus => SPLB_CTRL_PLB_ABus,
SPLB_CTRL_PLB_PAValid => SPLB_CTRL_PLB_PAValid,
SPLB_CTRL_PLB_masterID => SPLB_CTRL_PLB_masterID,
SPLB_CTRL_PLB_RNW => SPLB_CTRL_PLB_RNW,
SPLB_CTRL_PLB_BE => SPLB_CTRL_PLB_BE,
SPLB_CTRL_PLB_size => SPLB_CTRL_PLB_size,
SPLB_CTRL_PLB_type => SPLB_CTRL_PLB_type,
SPLB_CTRL_PLB_wrDBus => SPLB_CTRL_PLB_wrDBus,
SPLB_CTRL_Sl_addrAck => SPLB_CTRL_Sl_addrAck,
SPLB_CTRL_Sl_SSize => SPLB_CTRL_Sl_SSize,
SPLB_CTRL_Sl_wait => SPLB_CTRL_Sl_wait,
SPLB_CTRL_Sl_rearbitrate => SPLB_CTRL_Sl_rearbitrate,
SPLB_CTRL_Sl_wrDAck => SPLB_CTRL_Sl_wrDAck,
SPLB_CTRL_Sl_wrComp => SPLB_CTRL_Sl_wrComp,
SPLB_CTRL_Sl_rdDBus => SPLB_CTRL_Sl_rdDBus,
SPLB_CTRL_Sl_rdDAck => SPLB_CTRL_Sl_rdDAck,
SPLB_CTRL_Sl_rdComp => SPLB_CTRL_Sl_rdComp,
SPLB_CTRL_Sl_MBusy => SPLB_CTRL_Sl_MBusy,
SPLB_CTRL_Sl_MWrErr => SPLB_CTRL_Sl_MWrErr,
SPLB_CTRL_Sl_MRdErr => SPLB_CTRL_Sl_MRdErr,
SPLB_CTRL_PLB_UABus => SPLB_CTRL_PLB_UABus,
SPLB_CTRL_PLB_SAValid => SPLB_CTRL_PLB_SAValid,
SPLB_CTRL_PLB_rdPrim => SPLB_CTRL_PLB_rdPrim,
SPLB_CTRL_PLB_wrPrim => SPLB_CTRL_PLB_wrPrim,
SPLB_CTRL_PLB_abort => SPLB_CTRL_PLB_abort,
SPLB_CTRL_PLB_busLock => SPLB_CTRL_PLB_busLock,
SPLB_CTRL_PLB_MSize => SPLB_CTRL_PLB_MSize,
SPLB_CTRL_PLB_lockErr => SPLB_CTRL_PLB_lockErr,
SPLB_CTRL_PLB_wrBurst => SPLB_CTRL_PLB_wrBurst,
SPLB_CTRL_PLB_rdBurst => SPLB_CTRL_PLB_rdBurst,
SPLB_CTRL_PLB_wrPendReq => SPLB_CTRL_PLB_wrPendReq,
SPLB_CTRL_PLB_rdPendReq => SPLB_CTRL_PLB_rdPendReq,
SPLB_CTRL_PLB_wrPendPri => SPLB_CTRL_PLB_wrPendPri,
SPLB_CTRL_PLB_rdPendPri => SPLB_CTRL_PLB_rdPendPri,
SPLB_CTRL_PLB_reqPri => SPLB_CTRL_PLB_reqPri,
SPLB_CTRL_PLB_TAttribute => SPLB_CTRL_PLB_TAttribute,
SPLB_CTRL_Sl_wrBTerm => SPLB_CTRL_Sl_wrBTerm,
SPLB_CTRL_Sl_rdWdAddr => SPLB_CTRL_Sl_rdWdAddr,
SPLB_CTRL_Sl_rdBTerm => SPLB_CTRL_Sl_rdBTerm,
SPLB_CTRL_Sl_MIRQ => SPLB_CTRL_Sl_MIRQ,
S_AXI_CTRL_ACLK => S_AXI_CTRL_ACLK,
S_AXI_CTRL_ARESETN => S_AXI_CTRL_ARESETN,
S_AXI_CTRL_AWADDR => S_AXI_CTRL_AWADDR,
S_AXI_CTRL_AWVALID => S_AXI_CTRL_AWVALID,
S_AXI_CTRL_AWREADY => S_AXI_CTRL_AWREADY,
S_AXI_CTRL_WDATA => S_AXI_CTRL_WDATA,
S_AXI_CTRL_WSTRB => S_AXI_CTRL_WSTRB,
S_AXI_CTRL_WVALID => S_AXI_CTRL_WVALID,
S_AXI_CTRL_WREADY => S_AXI_CTRL_WREADY,
S_AXI_CTRL_BRESP => S_AXI_CTRL_BRESP,
S_AXI_CTRL_BVALID => S_AXI_CTRL_BVALID,
S_AXI_CTRL_BREADY => S_AXI_CTRL_BREADY,
S_AXI_CTRL_ARADDR => S_AXI_CTRL_ARADDR,
S_AXI_CTRL_ARVALID => S_AXI_CTRL_ARVALID,
S_AXI_CTRL_ARREADY => S_AXI_CTRL_ARREADY,
S_AXI_CTRL_RDATA => S_AXI_CTRL_RDATA,
S_AXI_CTRL_RRESP => S_AXI_CTRL_RRESP,
S_AXI_CTRL_RVALID => S_AXI_CTRL_RVALID,
S_AXI_CTRL_RREADY => S_AXI_CTRL_RREADY
);
end architecture STRUCTURE;
| lgpl-3.0 | 09dd2b0dc35f11a7bfd4dd664a6258fa | 0.615785 | 2.932645 | false | false | false | false |
grwlf/vsim | vhdl/IEEE/math_complex-body.vhdl | 2 | 12,489 | ---------------------------------------------------------------
--
-- This source file may be used and distributed without restriction.
-- No declarations or definitions shall be included in this package.
-- This package cannot be sold or distributed for profit.
--
-- ****************************************************************
-- * *
-- * W A R N I N G *
-- * *
-- * This DRAFT version IS NOT endorsed or approved by IEEE *
-- * *
-- ****************************************************************
--
-- Title: PACKAGE BODY MATH_COMPLEX
--
-- Purpose: VHDL declarations for mathematical package MATH_COMPLEX
-- which contains common complex constants and basic complex
-- functions and operations.
--
-- Author: IEEE VHDL Math Package Study Group
--
-- Notes:
-- The package body uses package IEEE.MATH_REAL
--
-- The package body shall be considered the formal definition of
-- the semantics of this package. Tool developers may choose to implement
-- the package body in the most efficient manner available to them.
--
-- Source code for this package body comes from the following
-- following sources:
-- IEEE VHDL Math Package Study Group participants,
-- U. of Mississippi, Mentor Graphics, Synopsys,
-- Viewlogic/Vantage, Communications of the ACM (June 1988, Vol
-- 31, Number 6, pp. 747, Pierre L'Ecuyer, Efficient and Portable
-- Random Number Generators, Handbook of Mathematical Functions
-- by Milton Abramowitz and Irene A. Stegun (Dover).
--
-- History:
-- Version 0.1 Jose A. Torres 4/23/93 First draft
-- Version 0.2 Jose A. Torres 5/28/93 Fixed potentially illegal code
--
-------------------------------------------------------------
Library IEEE;
Use IEEE.MATH_REAL.all; -- real trascendental operations
Package body MATH_COMPLEX is
function CABS(Z: in complex ) return real is
-- returns absolute value (magnitude) of Z
variable ztemp : complex_polar;
begin
ztemp := COMPLEX_TO_POLAR(Z);
return ztemp.mag;
end CABS;
function CARG(Z: in complex ) return real is
-- returns argument (angle) in radians of a complex number
variable ztemp : complex_polar;
begin
ztemp := COMPLEX_TO_POLAR(Z);
return ztemp.arg;
end CARG;
function CMPLX(X: in real; Y: in real := 0.0 ) return complex is
-- returns complex number X + iY
begin
return COMPLEX'(X, Y);
end CMPLX;
function "-" (Z: in complex ) return complex is
-- unary minus; returns -x -jy for z= x + jy
begin
return COMPLEX'(-z.Re, -z.Im);
end "-";
function "-" (Z: in complex_polar ) return complex_polar is
-- unary minus; returns (z.mag, z.arg + MATH_PI)
begin
return COMPLEX_POLAR'(z.mag, z.arg + MATH_PI);
end "-";
function CONJ (Z: in complex) return complex is
-- returns complex conjugate (x-jy for z = x+ jy)
begin
return COMPLEX'(z.Re, -z.Im);
end CONJ;
function CONJ (Z: in complex_polar) return complex_polar is
-- returns complex conjugate (z.mag, -z.arg)
begin
return COMPLEX_POLAR'(z.mag, -z.arg);
end CONJ;
function CSQRT(Z: in complex ) return complex_vector is
-- returns square root of Z; 2 values
variable ztemp : complex_polar;
variable zout : complex_vector (0 to 1);
variable temp : real;
begin
ztemp := COMPLEX_TO_POLAR(Z);
temp := SQRT(ztemp.mag);
zout(0).re := temp*COS(ztemp.arg/2.0);
zout(0).im := temp*SIN(ztemp.arg/2.0);
zout(1).re := temp*COS(ztemp.arg/2.0 + MATH_PI);
zout(1).im := temp*SIN(ztemp.arg/2.0 + MATH_PI);
return zout;
end CSQRT;
function CEXP(Z: in complex ) return complex is
-- returns e**Z
begin
return COMPLEX'(EXP(Z.re)*COS(Z.im), EXP(Z.re)*SIN(Z.im));
end CEXP;
function COMPLEX_TO_POLAR(Z: in complex ) return complex_polar is
-- converts complex to complex_polar
begin
return COMPLEX_POLAR'(sqrt(z.re**2 + z.im**2),atan2(z.re,z.im));
end COMPLEX_TO_POLAR;
function POLAR_TO_COMPLEX(Z: in complex_polar ) return complex is
-- converts complex_polar to complex
begin
return COMPLEX'( z.mag*cos(z.arg), z.mag*sin(z.arg) );
end POLAR_TO_COMPLEX;
--
-- arithmetic operators
--
function "+" ( L: in complex; R: in complex ) return complex is
begin
return COMPLEX'(L.Re + R.Re, L.Im + R.Im);
end "+";
function "+" (L: in complex_polar; R: in complex_polar) return complex is
variable zL, zR : complex;
begin
zL := POLAR_TO_COMPLEX( L );
zR := POLAR_TO_COMPLEX( R );
return COMPLEX'(zL.Re + zR.Re, zL.Im + zR.Im);
end "+";
function "+" ( L: in complex_polar; R: in complex ) return complex is
variable zL : complex;
begin
zL := POLAR_TO_COMPLEX( L );
return COMPLEX'(zL.Re + R.Re, zL.Im + R.Im);
end "+";
function "+" ( L: in complex; R: in complex_polar) return complex is
variable zR : complex;
begin
zR := POLAR_TO_COMPLEX( R );
return COMPLEX'(L.Re + zR.Re, L.Im + zR.Im);
end "+";
function "+" ( L: in real; R: in complex ) return complex is
begin
return COMPLEX'(L + R.Re, R.Im);
end "+";
function "+" ( L: in complex; R: in real ) return complex is
begin
return COMPLEX'(L.Re + R, L.Im);
end "+";
function "+" ( L: in real; R: in complex_polar) return complex is
variable zR : complex;
begin
zR := POLAR_TO_COMPLEX( R );
return COMPLEX'(L + zR.Re, zR.Im);
end "+";
function "+" ( L: in complex_polar; R: in real) return complex is
variable zL : complex;
begin
zL := POLAR_TO_COMPLEX( L );
return COMPLEX'(zL.Re + R, zL.Im);
end "+";
function "-" ( L: in complex; R: in complex ) return complex is
begin
return COMPLEX'(L.Re - R.Re, L.Im - R.Im);
end "-";
function "-" ( L: in complex_polar; R: in complex_polar) return complex is
variable zL, zR : complex;
begin
zL := POLAR_TO_COMPLEX( L );
zR := POLAR_TO_COMPLEX( R );
return COMPLEX'(zL.Re - zR.Re, zL.Im - zR.Im);
end "-";
function "-" ( L: in complex_polar; R: in complex ) return complex is
variable zL : complex;
begin
zL := POLAR_TO_COMPLEX( L );
return COMPLEX'(zL.Re - R.Re, zL.Im - R.Im);
end "-";
function "-" ( L: in complex; R: in complex_polar) return complex is
variable zR : complex;
begin
zR := POLAR_TO_COMPLEX( R );
return COMPLEX'(L.Re - zR.Re, L.Im - zR.Im);
end "-";
function "-" ( L: in real; R: in complex ) return complex is
begin
return COMPLEX'(L - R.Re, -1.0 * R.Im);
end "-";
function "-" ( L: in complex; R: in real ) return complex is
begin
return COMPLEX'(L.Re - R, L.Im);
end "-";
function "-" ( L: in real; R: in complex_polar) return complex is
variable zR : complex;
begin
zR := POLAR_TO_COMPLEX( R );
return COMPLEX'(L - zR.Re, -1.0*zR.Im);
end "-";
function "-" ( L: in complex_polar; R: in real) return complex is
variable zL : complex;
begin
zL := POLAR_TO_COMPLEX( L );
return COMPLEX'(zL.Re - R, zL.Im);
end "-";
function "*" ( L: in complex; R: in complex ) return complex is
begin
return COMPLEX'(L.Re * R.Re - L.Im * R.Im, L.Re * R.Im + L.Im * R.Re);
end "*";
function "*" ( L: in complex_polar; R: in complex_polar) return complex is
variable zout : complex_polar;
begin
zout.mag := L.mag * R.mag;
zout.arg := L.arg + R.arg;
return POLAR_TO_COMPLEX(zout);
end "*";
function "*" ( L: in complex_polar; R: in complex ) return complex is
variable zL : complex;
begin
zL := POLAR_TO_COMPLEX( L );
return COMPLEX'(zL.Re*R.Re - zL.Im * R.Im, zL.Re * R.Im + zL.Im*R.Re);
end "*";
function "*" ( L: in complex; R: in complex_polar) return complex is
variable zR : complex;
begin
zR := POLAR_TO_COMPLEX( R );
return COMPLEX'(L.Re*zR.Re - L.Im * zR.Im, L.Re * zR.Im + L.Im*zR.Re);
end "*";
function "*" ( L: in real; R: in complex ) return complex is
begin
return COMPLEX'(L * R.Re, L * R.Im);
end "*";
function "*" ( L: in complex; R: in real ) return complex is
begin
return COMPLEX'(L.Re * R, L.Im * R);
end "*";
function "*" ( L: in real; R: in complex_polar) return complex is
variable zR : complex;
begin
zR := POLAR_TO_COMPLEX( R );
return COMPLEX'(L * zR.Re, L * zR.Im);
end "*";
function "*" ( L: in complex_polar; R: in real) return complex is
variable zL : complex;
begin
zL := POLAR_TO_COMPLEX( L );
return COMPLEX'(zL.Re * R, zL.Im * R);
end "*";
function "/" ( L: in complex; R: in complex ) return complex is
variable magrsq : REAL := R.Re ** 2 + R.Im ** 2;
begin
if (magrsq = 0.0) then
assert FALSE report "Attempt to divide by (0,0)"
severity ERROR;
return COMPLEX'(REAL'RIGHT, REAL'RIGHT);
else
return COMPLEX'( (L.Re * R.Re + L.Im * R.Im) / magrsq,
(L.Im * R.Re - L.Re * R.Im) / magrsq);
end if;
end "/";
function "/" ( L: in complex_polar; R: in complex_polar) return complex is
variable zout : complex_polar;
begin
if (R.mag = 0.0) then
assert FALSE report "Attempt to divide by (0,0)"
severity ERROR;
return COMPLEX'(REAL'RIGHT, REAL'RIGHT);
else
zout.mag := L.mag/R.mag;
zout.arg := L.arg - R.arg;
return POLAR_TO_COMPLEX(zout);
end if;
end "/";
function "/" ( L: in complex_polar; R: in complex ) return complex is
variable zL : complex;
variable temp : REAL := R.Re ** 2 + R.Im ** 2;
begin
if (temp = 0.0) then
assert FALSE report "Attempt to divide by (0.0,0.0)"
severity ERROR;
return COMPLEX'(REAL'RIGHT, REAL'RIGHT);
else
zL := POLAR_TO_COMPLEX( L );
return COMPLEX'( (zL.Re * R.Re + zL.Im * R.Im) / temp,
(zL.Im * R.Re - zL.Re * R.Im) / temp);
end if;
end "/";
function "/" ( L: in complex; R: in complex_polar) return complex is
variable zR : complex := POLAR_TO_COMPLEX( R );
variable temp : REAL := zR.Re ** 2 + zR.Im ** 2;
begin
if (R.mag = 0.0) or (temp = 0.0) then
assert FALSE report "Attempt to divide by (0.0,0.0)"
severity ERROR;
return COMPLEX'(REAL'RIGHT, REAL'RIGHT);
else
return COMPLEX'( (L.Re * zR.Re + L.Im * zR.Im) / temp,
(L.Im * zR.Re - L.Re * zR.Im) / temp);
end if;
end "/";
function "/" ( L: in real; R: in complex ) return complex is
variable temp : REAL := R.Re ** 2 + R.Im ** 2;
begin
if (temp = 0.0) then
assert FALSE report "Attempt to divide by (0.0,0.0)"
severity ERROR;
return COMPLEX'(REAL'RIGHT, REAL'RIGHT);
else
temp := L / temp;
return COMPLEX'( temp * R.Re, -temp * R.Im );
end if;
end "/";
function "/" ( L: in complex; R: in real ) return complex is
begin
if (R = 0.0) then
assert FALSE report "Attempt to divide by (0.0,0.0)"
severity ERROR;
return COMPLEX'(REAL'RIGHT, REAL'RIGHT);
else
return COMPLEX'(L.Re / R, L.Im / R);
end if;
end "/";
function "/" ( L: in real; R: in complex_polar) return complex is
variable zR : complex := POLAR_TO_COMPLEX( R );
variable temp : REAL := zR.Re ** 2 + zR.Im ** 2;
begin
if (R.mag = 0.0) or (temp = 0.0) then
assert FALSE report "Attempt to divide by (0.0,0.0)"
severity ERROR;
return COMPLEX'(REAL'RIGHT, REAL'RIGHT);
else
temp := L / temp;
return COMPLEX'( temp * zR.Re, -temp * zR.Im );
end if;
end "/";
function "/" ( L: in complex_polar; R: in real) return complex is
variable zL : complex := POLAR_TO_COMPLEX( L );
begin
if (R = 0.0) then
assert FALSE report "Attempt to divide by (0.0,0.0)"
severity ERROR;
return COMPLEX'(REAL'RIGHT, REAL'RIGHT);
else
return COMPLEX'(zL.Re / R, zL.Im / R);
end if;
end "/";
end MATH_COMPLEX;
| gpl-3.0 | 285f6705027e5865c6d075c3737f0d1f | 0.556169 | 3.358161 | false | false | false | false |
rauenzi/VHDL-Communications | i2c_master.vhd | 1 | 14,232 | --------------------------------------------------------------------------------
--
-- FileName: i2c_master.vhd
-- Dependencies: none
-- Design Software: Quartus II 64-bit Version 13.1 Build 162 SJ Full Version
--
-- HDL CODE IS PROVIDED "AS IS." DIGI-KEY EXPRESSLY DISCLAIMS ANY
-- WARRANTY OF ANY KIND, WHETHER EXPRESS OR IMPLIED, INCLUDING BUT NOT
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A
-- PARTICULAR PURPOSE, OR NON-INFRINGEMENT. IN NO EVENT SHALL DIGI-KEY
-- BE LIABLE FOR ANY INCIDENTAL, SPECIAL, INDIRECT OR CONSEQUENTIAL
-- DAMAGES, LOST PROFITS OR LOST DATA, HARM TO YOUR EQUIPMENT, COST OF
-- PROCUREMENT OF SUBSTITUTE GOODS, TECHNOLOGY OR SERVICES, ANY CLAIMS
-- BY THIRD PARTIES (INCLUDING BUT NOT LIMITED TO ANY DEFENSE THEREOF),
-- ANY CLAIMS FOR INDEMNITY OR CONTRIBUTION, OR OTHER SIMILAR COSTS.
--
-- Version History
-- Version 1.0 11/1/2012 Scott Larson
-- Initial Public Release
-- Version 2.0 06/20/2014 Scott Larson
-- Added ability to interface with different slaves in the same transaction
-- Corrected ack_error bug where ack_error went 'Z' instead of '1' on error
-- Corrected timing of when ack_error signal clears
-- Version 2.1 10/21/2014 Scott Larson
-- Replaced gated clock with clock enable
-- Adjusted timing of SCL during start and stop conditions
--
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
ENTITY i2c_master IS
GENERIC(
input_clk : INTEGER := 100_000_000; --input clock speed from user logic in Hz
bus_clk : INTEGER := 400_000); --speed the i2c bus (scl) will run at in Hz
PORT(
clk : IN STD_LOGIC; --system clock
reset_n : IN STD_LOGIC; --active low reset
ena : IN STD_LOGIC; --latch in command
addr : IN STD_LOGIC_VECTOR(6 DOWNTO 0); --address of target slave
rw : IN STD_LOGIC; --'0' is write, '1' is read
data_wr : IN STD_LOGIC_VECTOR(7 DOWNTO 0); --data to write to slave
busy : OUT STD_LOGIC; --indicates transaction in progress
data_rd : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); --data read from slave
ack_error : BUFFER STD_LOGIC; --flag if improper acknowledge from slave
sda : INOUT STD_LOGIC; --serial data output of i2c bus
scl : INOUT STD_LOGIC); --serial clock output of i2c bus
END i2c_master;
ARCHITECTURE logic OF i2c_master IS
CONSTANT divider : INTEGER := (input_clk/bus_clk)/4; --number of clocks in 1/4 cycle of scl
TYPE machine IS(ready, start, command, slv_ack1, wr, rd, slv_ack2, mstr_ack, stop); --needed states
SIGNAL state : machine; --state machine
SIGNAL data_clk : STD_LOGIC; --data clock for sda
SIGNAL data_clk_prev : STD_LOGIC; --data clock during previous system clock
SIGNAL scl_clk : STD_LOGIC; --constantly running internal scl
SIGNAL scl_ena : STD_LOGIC := '0'; --enables internal scl to output
SIGNAL sda_int : STD_LOGIC := '1'; --internal sda
SIGNAL sda_ena_n : STD_LOGIC; --enables internal sda to output
SIGNAL addr_rw : STD_LOGIC_VECTOR(7 DOWNTO 0); --latched in address and read/write
SIGNAL data_tx : STD_LOGIC_VECTOR(7 DOWNTO 0); --latched in data to write to slave
SIGNAL data_rx : STD_LOGIC_VECTOR(7 DOWNTO 0); --data received from slave
SIGNAL bit_cnt : INTEGER RANGE 0 TO 7 := 7; --tracks bit number in transaction
SIGNAL stretch : STD_LOGIC := '0'; --identifies if slave is stretching scl
signal data_clk_m : std_logic;
BEGIN
--generate the timing for the bus clock (scl_clk) and the data clock (data_clk)
PROCESS(clk, reset_n)
VARIABLE count : INTEGER RANGE 0 TO divider*4; --timing for clock generation
BEGIN
IF(reset_n = '0') THEN --reset asserted
stretch <= '0';
count := 0;
ELSIF(clk'EVENT AND clk = '1') THEN
data_clk_prev <= data_clk; --store previous value of data clock
IF(count = divider*4-1) THEN --end of timing cycle
count := 0; --reset timer
ELSIF(stretch = '0') THEN --clock stretching from slave not detected
count := count + 1; --continue clock generation timing
END IF;
CASE count IS
WHEN 0 TO divider-1 => --first 1/4 cycle of clocking
scl_clk <= '0';
data_clk <= '0';
WHEN divider TO divider*2-1 => --second 1/4 cycle of clocking
scl_clk <= '0';
data_clk <= '1';
WHEN divider*2 TO divider*3-1 => --third 1/4 cycle of clocking
scl_clk <= '1'; --release scl
IF(scl = '0') THEN --detect if slave is stretching clock
stretch <= '1';
ELSE
stretch <= '0';
END IF;
data_clk <= '1';
WHEN OTHERS => --last 1/4 cycle of clocking
scl_clk <= '1';
data_clk <= '0';
END CASE;
END IF;
END PROCESS;
--state machine and writing to sda during scl low (data_clk rising edge)
PROCESS(clk, reset_n)
BEGIN
IF(reset_n = '0') THEN --reset asserted
state <= ready; --return to initial state
busy <= '1'; --indicate not available
scl_ena <= '0'; --sets scl high impedance
sda_int <= '1'; --sets sda high impedance
ack_error <= '0'; --clear acknowledge error flag
bit_cnt <= 7; --restarts data bit counter
data_rd <= "00000000"; --clear data read port
ELSIF(clk'EVENT AND clk = '1') THEN
IF(data_clk = '1' AND data_clk_prev = '0') THEN --data clock rising edge
CASE state IS
WHEN ready => --idle state
IF(ena = '1') THEN --transaction requested
busy <= '1'; --flag busy
addr_rw <= addr & rw; --collect requested slave address and command
data_tx <= data_wr; --collect requested data to write
state <= start; --go to start bit
ELSE --remain idle
busy <= '0'; --unflag busy
state <= ready; --remain idle
END IF;
WHEN start => --start bit of transaction
busy <= '1'; --resume busy if continuous mode
sda_int <= addr_rw(bit_cnt); --set first address bit to bus
state <= command; --go to command
WHEN command => --address and command byte of transaction
IF(bit_cnt = 0) THEN --command transmit finished
sda_int <= '1'; --release sda for slave acknowledge
bit_cnt <= 7; --reset bit counter for "byte" states
state <= slv_ack1; --go to slave acknowledge (command)
ELSE --next clock cycle of command state
bit_cnt <= bit_cnt - 1; --keep track of transaction bits
sda_int <= addr_rw(bit_cnt-1); --write address/command bit to bus
state <= command; --continue with command
END IF;
WHEN slv_ack1 => --slave acknowledge bit (command)
IF(addr_rw(0) = '0') THEN --write command
sda_int <= data_tx(bit_cnt); --write first bit of data
state <= wr; --go to write byte
ELSE --read command
sda_int <= '1'; --release sda from incoming data
state <= rd; --go to read byte
END IF;
WHEN wr => --write byte of transaction
busy <= '1'; --resume busy if continuous mode
IF(bit_cnt = 0) THEN --write byte transmit finished
sda_int <= '1'; --release sda for slave acknowledge
bit_cnt <= 7; --reset bit counter for "byte" states
busy<='0'; --modified
state <= slv_ack2; --go to slave acknowledge (write)
ELSE --next clock cycle of write state
bit_cnt <= bit_cnt - 1; --keep track of transaction bits
sda_int <= data_tx(bit_cnt-1); --write next bit to bus
state <= wr; --continue writing
END IF;
WHEN rd => --read byte of transaction
busy <= '1'; --resume busy if continuous mode
IF(bit_cnt = 0) THEN --read byte receive finished
IF(ena = '1' AND addr_rw = addr & rw) THEN --continuing with another read at same address
sda_int <= '0'; --acknowledge the byte has been received
ELSE --stopping or continuing with a write
sda_int <= '1'; --send a no-acknowledge (before stop or repeated start)
END IF;
bit_cnt <= 7; --reset bit counter for "byte" states
data_rd <= data_rx; --output received data
state <= mstr_ack; --go to master acknowledge
ELSE --next clock cycle of read state
bit_cnt <= bit_cnt - 1; --keep track of transaction bits
state <= rd; --continue reading
END IF;
WHEN slv_ack2 => --slave acknowledge bit (write)
IF(ena = '1') THEN --continue transaction
-- busy <= '0'; --continue is accepted
addr_rw <= addr & rw; --collect requested slave address and command
data_tx <= data_wr; --collect requested data to write
IF(addr_rw = addr & rw) THEN --continue transaction with another write
busy <= '1';
sda_int <= data_wr(bit_cnt); --write first bit of data
state <= wr; --go to write byte
ELSE --continue transaction with a read or new slave
state <= start; --go to repeated start
END IF;
ELSE --complete transaction
state <= stop; --go to stop bit
END IF;
WHEN mstr_ack => --master acknowledge bit after a read
IF(ena = '1') THEN --continue transaction
busy <= '0'; --continue is accepted and data received is available on bus
addr_rw <= addr & rw; --collect requested slave address and command
data_tx <= data_wr; --collect requested data to write
IF(addr_rw = addr & rw) THEN --continue transaction with another read
sda_int <= '1'; --release sda from incoming data
state <= rd; --go to read byte
ELSE --continue transaction with a write or new slave
state <= start; --repeated start
END IF;
ELSE --complete transaction
state <= stop; --go to stop bit
END IF;
WHEN stop => --stop bit of transaction
busy <= '0'; --unflag busy
state <= ready; --go to idle state
END CASE;
ELSIF(data_clk = '0' AND data_clk_prev = '1') THEN --data clock falling edge
CASE state IS
WHEN start =>
IF(scl_ena = '0') THEN --starting new transaction
scl_ena <= '1'; --enable scl output
ack_error <= '0'; --reset acknowledge error output
END IF;
WHEN slv_ack1 => --receiving slave acknowledge (command)
IF(sda /= '0' OR ack_error = '1') THEN --no-acknowledge or previous no-acknowledge
ack_error <= '1'; --set error output if no-acknowledge
END IF;
WHEN rd => --receiving slave data
data_rx(bit_cnt) <= sda; --receive current slave data bit
WHEN slv_ack2 => --receiving slave acknowledge (write)
IF(sda /= '0' OR ack_error = '1') THEN --no-acknowledge or previous no-acknowledge
ack_error <= '1'; --set error output if no-acknowledge
END IF;
WHEN stop =>
scl_ena <= '0'; --disable scl
WHEN OTHERS =>
NULL;
END CASE;
END IF;
END IF;
END PROCESS;
--set sda output
data_clk_m<=data_clk_prev and data_clk;
WITH state SELECT
sda_ena_n <= data_clk WHEN start, --generate start condition
NOT data_clk_m WHEN stop, --generate stop condition
sda_int WHEN OTHERS; --set to internal sda signal
--set scl and sda outputs
scl <= '0' WHEN (scl_ena = '1' AND scl_clk = '0') ELSE 'Z';
sda <= '0' WHEN sda_ena_n = '0' ELSE 'Z';
END logic; | apache-2.0 | 79eea5d5879130fb20ade2d493819b97 | 0.488547 | 4.657068 | false | false | false | false |
jairov4/accel-oil | impl/impl_test_pcie/hdl/system_xps_central_dma_1_wrapper.vhd | 1 | 10,336 | -------------------------------------------------------------------------------
-- system_xps_central_dma_1_wrapper.vhd
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
library xps_central_dma_v2_03_a;
use xps_central_dma_v2_03_a.all;
entity system_xps_central_dma_1_wrapper is
port (
SPLB_Clk : in std_logic;
SPLB_Rst : in std_logic;
MPLB_Clk : in std_logic;
MPLB_Rst : in std_logic;
SPLB_ABus : in std_logic_vector(0 to 31);
SPLB_BE : in std_logic_vector(0 to 7);
SPLB_UABus : in std_logic_vector(0 to 31);
SPLB_PAValid : in std_logic;
SPLB_SAValid : in std_logic;
SPLB_rdPrim : in std_logic;
SPLB_wrPrim : in std_logic;
SPLB_masterID : in std_logic_vector(0 to 2);
SPLB_abort : in std_logic;
SPLB_busLock : in std_logic;
SPLB_RNW : in std_logic;
SPLB_MSize : in std_logic_vector(0 to 1);
SPLB_size : in std_logic_vector(0 to 3);
SPLB_type : in std_logic_vector(0 to 2);
SPLB_lockErr : in std_logic;
SPLB_wrDBus : in std_logic_vector(0 to 63);
SPLB_wrBurst : in std_logic;
SPLB_rdBurst : in std_logic;
SPLB_wrPendReq : in std_logic;
SPLB_rdPendReq : in std_logic;
SPLB_wrPendPri : in std_logic_vector(0 to 1);
SPLB_rdPendPri : in std_logic_vector(0 to 1);
SPLB_reqPri : in std_logic_vector(0 to 1);
SPLB_TAttribute : in std_logic_vector(0 to 15);
Sl_addrAck : out std_logic;
Sl_SSize : out std_logic_vector(0 to 1);
Sl_wait : out std_logic;
Sl_rearbitrate : out std_logic;
Sl_wrDAck : out std_logic;
Sl_wrComp : out std_logic;
Sl_wrBTerm : out std_logic;
Sl_rdDBus : out std_logic_vector(0 to 63);
Sl_rdWdAddr : out std_logic_vector(0 to 3);
Sl_rdDAck : out std_logic;
Sl_rdComp : out std_logic;
Sl_rdBTerm : out std_logic;
Sl_MBusy : out std_logic_vector(0 to 5);
Sl_MWrErr : out std_logic_vector(0 to 5);
Sl_MRdErr : out std_logic_vector(0 to 5);
Sl_MIRQ : out std_logic_vector(0 to 5);
IP2INTC_Irpt : out std_logic;
MPLB_MAddrAck : in std_logic;
MPLB_MSSize : in std_logic_vector(0 to 1);
MPLB_MRearbitrate : in std_logic;
MPLB_MTimeout : in std_logic;
MPLB_MBusy : in std_logic;
MPLB_MRdErr : in std_logic;
MPLB_MWrErr : in std_logic;
MPLB_MIRQ : in std_logic;
MPLB_MRdDBus : in std_logic_vector(0 to 63);
MPLB_MRdWdAddr : in std_logic_vector(0 to 3);
MPLB_MRdDAck : in std_logic;
MPLB_MRdBTerm : in std_logic;
MPLB_MWrDAck : in std_logic;
MPLB_MWrBTerm : in std_logic;
M_request : out std_logic;
M_priority : out std_logic_vector(0 to 1);
M_busLock : out std_logic;
M_RNW : out std_logic;
M_BE : out std_logic_vector(0 to 7);
M_MSize : out std_logic_vector(0 to 1);
M_size : out std_logic_vector(0 to 3);
M_type : out std_logic_vector(0 to 2);
M_TAttribute : out std_logic_vector(0 to 15);
M_lockErr : out std_logic;
M_abort : out std_logic;
M_UABus : out std_logic_vector(0 to 31);
M_ABus : out std_logic_vector(0 to 31);
M_wrDBus : out std_logic_vector(0 to 63);
M_wrBurst : out std_logic;
M_rdBurst : out std_logic
);
attribute x_core_info : STRING;
attribute x_core_info of system_xps_central_dma_1_wrapper : entity is "xps_central_dma_v2_03_a";
end system_xps_central_dma_1_wrapper;
architecture STRUCTURE of system_xps_central_dma_1_wrapper is
component xps_central_dma is
generic (
C_FIFO_DEPTH : INTEGER;
C_RD_BURST_SIZE : INTEGER;
C_WR_BURST_SIZE : INTEGER;
C_BASEADDR : std_logic_vector;
C_HIGHADDR : std_logic_vector;
C_SPLB_DWIDTH : INTEGER;
C_SPLB_AWIDTH : INTEGER;
C_SPLB_NUM_MASTERS : INTEGER;
C_SPLB_MID_WIDTH : INTEGER;
C_SPLB_P2P : INTEGER;
C_SPLB_NATIVE_DWIDTH : INTEGER;
C_MPLB_NATIVE_DWIDTH : INTEGER;
C_SPLB_SUPPORT_BURSTS : INTEGER;
C_MPLB_AWIDTH : INTEGER;
C_MPLB_DWIDTH : INTEGER;
C_FAMILY : STRING
);
port (
SPLB_Clk : in std_logic;
SPLB_Rst : in std_logic;
MPLB_Clk : in std_logic;
MPLB_Rst : in std_logic;
SPLB_ABus : in std_logic_vector(0 to (C_SPLB_AWIDTH-1));
SPLB_BE : in std_logic_vector(0 to ((C_SPLB_DWIDTH/8)-1));
SPLB_UABus : in std_logic_vector(0 to 31);
SPLB_PAValid : in std_logic;
SPLB_SAValid : in std_logic;
SPLB_rdPrim : in std_logic;
SPLB_wrPrim : in std_logic;
SPLB_masterID : in std_logic_vector(0 to (C_SPLB_MID_WIDTH-1));
SPLB_abort : in std_logic;
SPLB_busLock : in std_logic;
SPLB_RNW : in std_logic;
SPLB_MSize : in std_logic_vector(0 to 1);
SPLB_size : in std_logic_vector(0 to 3);
SPLB_type : in std_logic_vector(0 to 2);
SPLB_lockErr : in std_logic;
SPLB_wrDBus : in std_logic_vector(0 to (C_SPLB_DWIDTH-1));
SPLB_wrBurst : in std_logic;
SPLB_rdBurst : in std_logic;
SPLB_wrPendReq : in std_logic;
SPLB_rdPendReq : in std_logic;
SPLB_wrPendPri : in std_logic_vector(0 to 1);
SPLB_rdPendPri : in std_logic_vector(0 to 1);
SPLB_reqPri : in std_logic_vector(0 to 1);
SPLB_TAttribute : in std_logic_vector(0 to 15);
Sl_addrAck : out std_logic;
Sl_SSize : out std_logic_vector(0 to 1);
Sl_wait : out std_logic;
Sl_rearbitrate : out std_logic;
Sl_wrDAck : out std_logic;
Sl_wrComp : out std_logic;
Sl_wrBTerm : out std_logic;
Sl_rdDBus : out std_logic_vector(0 to (C_SPLB_DWIDTH-1));
Sl_rdWdAddr : out std_logic_vector(0 to 3);
Sl_rdDAck : out std_logic;
Sl_rdComp : out std_logic;
Sl_rdBTerm : out std_logic;
Sl_MBusy : out std_logic_vector(0 to (C_SPLB_NUM_MASTERS-1));
Sl_MWrErr : out std_logic_vector(0 to (C_SPLB_NUM_MASTERS-1));
Sl_MRdErr : out std_logic_vector(0 to (C_SPLB_NUM_MASTERS-1));
Sl_MIRQ : out std_logic_vector(0 to (C_SPLB_NUM_MASTERS-1));
IP2INTC_Irpt : out std_logic;
MPLB_MAddrAck : in std_logic;
MPLB_MSSize : in std_logic_vector(0 to 1);
MPLB_MRearbitrate : in std_logic;
MPLB_MTimeout : in std_logic;
MPLB_MBusy : in std_logic;
MPLB_MRdErr : in std_logic;
MPLB_MWrErr : in std_logic;
MPLB_MIRQ : in std_logic;
MPLB_MRdDBus : in std_logic_vector(0 to (C_MPLB_DWIDTH-1));
MPLB_MRdWdAddr : in std_logic_vector(0 to 3);
MPLB_MRdDAck : in std_logic;
MPLB_MRdBTerm : in std_logic;
MPLB_MWrDAck : in std_logic;
MPLB_MWrBTerm : in std_logic;
M_request : out std_logic;
M_priority : out std_logic_vector(0 to 1);
M_busLock : out std_logic;
M_RNW : out std_logic;
M_BE : out std_logic_vector(0 to ((C_MPLB_DWIDTH/8)-1));
M_MSize : out std_logic_vector(0 to 1);
M_size : out std_logic_vector(0 to 3);
M_type : out std_logic_vector(0 to 2);
M_TAttribute : out std_logic_vector(0 to 15);
M_lockErr : out std_logic;
M_abort : out std_logic;
M_UABus : out std_logic_vector(0 to 31);
M_ABus : out std_logic_vector(0 to (C_MPLB_AWIDTH-1));
M_wrDBus : out std_logic_vector(0 to (C_MPLB_DWIDTH-1));
M_wrBurst : out std_logic;
M_rdBurst : out std_logic
);
end component;
begin
xps_central_dma_1 : xps_central_dma
generic map (
C_FIFO_DEPTH => 8,
C_RD_BURST_SIZE => 8,
C_WR_BURST_SIZE => 8,
C_BASEADDR => X"80200000",
C_HIGHADDR => X"8020ffff",
C_SPLB_DWIDTH => 64,
C_SPLB_AWIDTH => 32,
C_SPLB_NUM_MASTERS => 6,
C_SPLB_MID_WIDTH => 3,
C_SPLB_P2P => 0,
C_SPLB_NATIVE_DWIDTH => 32,
C_MPLB_NATIVE_DWIDTH => 32,
C_SPLB_SUPPORT_BURSTS => 0,
C_MPLB_AWIDTH => 32,
C_MPLB_DWIDTH => 64,
C_FAMILY => "virtex5"
)
port map (
SPLB_Clk => SPLB_Clk,
SPLB_Rst => SPLB_Rst,
MPLB_Clk => MPLB_Clk,
MPLB_Rst => MPLB_Rst,
SPLB_ABus => SPLB_ABus,
SPLB_BE => SPLB_BE,
SPLB_UABus => SPLB_UABus,
SPLB_PAValid => SPLB_PAValid,
SPLB_SAValid => SPLB_SAValid,
SPLB_rdPrim => SPLB_rdPrim,
SPLB_wrPrim => SPLB_wrPrim,
SPLB_masterID => SPLB_masterID,
SPLB_abort => SPLB_abort,
SPLB_busLock => SPLB_busLock,
SPLB_RNW => SPLB_RNW,
SPLB_MSize => SPLB_MSize,
SPLB_size => SPLB_size,
SPLB_type => SPLB_type,
SPLB_lockErr => SPLB_lockErr,
SPLB_wrDBus => SPLB_wrDBus,
SPLB_wrBurst => SPLB_wrBurst,
SPLB_rdBurst => SPLB_rdBurst,
SPLB_wrPendReq => SPLB_wrPendReq,
SPLB_rdPendReq => SPLB_rdPendReq,
SPLB_wrPendPri => SPLB_wrPendPri,
SPLB_rdPendPri => SPLB_rdPendPri,
SPLB_reqPri => SPLB_reqPri,
SPLB_TAttribute => SPLB_TAttribute,
Sl_addrAck => Sl_addrAck,
Sl_SSize => Sl_SSize,
Sl_wait => Sl_wait,
Sl_rearbitrate => Sl_rearbitrate,
Sl_wrDAck => Sl_wrDAck,
Sl_wrComp => Sl_wrComp,
Sl_wrBTerm => Sl_wrBTerm,
Sl_rdDBus => Sl_rdDBus,
Sl_rdWdAddr => Sl_rdWdAddr,
Sl_rdDAck => Sl_rdDAck,
Sl_rdComp => Sl_rdComp,
Sl_rdBTerm => Sl_rdBTerm,
Sl_MBusy => Sl_MBusy,
Sl_MWrErr => Sl_MWrErr,
Sl_MRdErr => Sl_MRdErr,
Sl_MIRQ => Sl_MIRQ,
IP2INTC_Irpt => IP2INTC_Irpt,
MPLB_MAddrAck => MPLB_MAddrAck,
MPLB_MSSize => MPLB_MSSize,
MPLB_MRearbitrate => MPLB_MRearbitrate,
MPLB_MTimeout => MPLB_MTimeout,
MPLB_MBusy => MPLB_MBusy,
MPLB_MRdErr => MPLB_MRdErr,
MPLB_MWrErr => MPLB_MWrErr,
MPLB_MIRQ => MPLB_MIRQ,
MPLB_MRdDBus => MPLB_MRdDBus,
MPLB_MRdWdAddr => MPLB_MRdWdAddr,
MPLB_MRdDAck => MPLB_MRdDAck,
MPLB_MRdBTerm => MPLB_MRdBTerm,
MPLB_MWrDAck => MPLB_MWrDAck,
MPLB_MWrBTerm => MPLB_MWrBTerm,
M_request => M_request,
M_priority => M_priority,
M_busLock => M_busLock,
M_RNW => M_RNW,
M_BE => M_BE,
M_MSize => M_MSize,
M_size => M_size,
M_type => M_type,
M_TAttribute => M_TAttribute,
M_lockErr => M_lockErr,
M_abort => M_abort,
M_UABus => M_UABus,
M_ABus => M_ABus,
M_wrDBus => M_wrDBus,
M_wrBurst => M_wrBurst,
M_rdBurst => M_rdBurst
);
end architecture STRUCTURE;
| lgpl-3.0 | 41ad11b22d85fb42e12fe7771db4373b | 0.593266 | 3.21393 | false | false | false | false |
jairov4/accel-oil | impl/impl_test_single/simulation/behavioral/system_mdm_0_wrapper.vhd | 1 | 38,992 | -------------------------------------------------------------------------------
-- system_mdm_0_wrapper.vhd
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
library mdm_v2_10_a;
use mdm_v2_10_a.all;
entity system_mdm_0_wrapper is
port (
Interrupt : out std_logic;
Debug_SYS_Rst : out std_logic;
Ext_BRK : out std_logic;
Ext_NM_BRK : out std_logic;
S_AXI_ACLK : in std_logic;
S_AXI_ARESETN : in std_logic;
S_AXI_AWADDR : in std_logic_vector(31 downto 0);
S_AXI_AWVALID : in std_logic;
S_AXI_AWREADY : out std_logic;
S_AXI_WDATA : in std_logic_vector(31 downto 0);
S_AXI_WSTRB : in std_logic_vector(3 downto 0);
S_AXI_WVALID : in std_logic;
S_AXI_WREADY : out std_logic;
S_AXI_BRESP : out std_logic_vector(1 downto 0);
S_AXI_BVALID : out std_logic;
S_AXI_BREADY : in std_logic;
S_AXI_ARADDR : in std_logic_vector(31 downto 0);
S_AXI_ARVALID : in std_logic;
S_AXI_ARREADY : out std_logic;
S_AXI_RDATA : out std_logic_vector(31 downto 0);
S_AXI_RRESP : out std_logic_vector(1 downto 0);
S_AXI_RVALID : out std_logic;
S_AXI_RREADY : in std_logic;
SPLB_Clk : in std_logic;
SPLB_Rst : in std_logic;
PLB_ABus : in std_logic_vector(0 to 31);
PLB_UABus : in std_logic_vector(0 to 31);
PLB_PAValid : in std_logic;
PLB_SAValid : in std_logic;
PLB_rdPrim : in std_logic;
PLB_wrPrim : in std_logic;
PLB_masterID : in std_logic_vector(0 to 2);
PLB_abort : in std_logic;
PLB_busLock : in std_logic;
PLB_RNW : in std_logic;
PLB_BE : in std_logic_vector(0 to 7);
PLB_MSize : in std_logic_vector(0 to 1);
PLB_size : in std_logic_vector(0 to 3);
PLB_type : in std_logic_vector(0 to 2);
PLB_lockErr : in std_logic;
PLB_wrDBus : in std_logic_vector(0 to 63);
PLB_wrBurst : in std_logic;
PLB_rdBurst : in std_logic;
PLB_wrPendReq : in std_logic;
PLB_rdPendReq : in std_logic;
PLB_wrPendPri : in std_logic_vector(0 to 1);
PLB_rdPendPri : in std_logic_vector(0 to 1);
PLB_reqPri : in std_logic_vector(0 to 1);
PLB_TAttribute : in std_logic_vector(0 to 15);
Sl_addrAck : out std_logic;
Sl_SSize : out std_logic_vector(0 to 1);
Sl_wait : out std_logic;
Sl_rearbitrate : out std_logic;
Sl_wrDAck : out std_logic;
Sl_wrComp : out std_logic;
Sl_wrBTerm : out std_logic;
Sl_rdDBus : out std_logic_vector(0 to 63);
Sl_rdWdAddr : out std_logic_vector(0 to 3);
Sl_rdDAck : out std_logic;
Sl_rdComp : out std_logic;
Sl_rdBTerm : out std_logic;
Sl_MBusy : out std_logic_vector(0 to 6);
Sl_MWrErr : out std_logic_vector(0 to 6);
Sl_MRdErr : out std_logic_vector(0 to 6);
Sl_MIRQ : out std_logic_vector(0 to 6);
Dbg_Clk_0 : out std_logic;
Dbg_TDI_0 : out std_logic;
Dbg_TDO_0 : in std_logic;
Dbg_Reg_En_0 : out std_logic_vector(0 to 7);
Dbg_Capture_0 : out std_logic;
Dbg_Shift_0 : out std_logic;
Dbg_Update_0 : out std_logic;
Dbg_Rst_0 : out std_logic;
Dbg_Clk_1 : out std_logic;
Dbg_TDI_1 : out std_logic;
Dbg_TDO_1 : in std_logic;
Dbg_Reg_En_1 : out std_logic_vector(0 to 7);
Dbg_Capture_1 : out std_logic;
Dbg_Shift_1 : out std_logic;
Dbg_Update_1 : out std_logic;
Dbg_Rst_1 : out std_logic;
Dbg_Clk_2 : out std_logic;
Dbg_TDI_2 : out std_logic;
Dbg_TDO_2 : in std_logic;
Dbg_Reg_En_2 : out std_logic_vector(0 to 7);
Dbg_Capture_2 : out std_logic;
Dbg_Shift_2 : out std_logic;
Dbg_Update_2 : out std_logic;
Dbg_Rst_2 : out std_logic;
Dbg_Clk_3 : out std_logic;
Dbg_TDI_3 : out std_logic;
Dbg_TDO_3 : in std_logic;
Dbg_Reg_En_3 : out std_logic_vector(0 to 7);
Dbg_Capture_3 : out std_logic;
Dbg_Shift_3 : out std_logic;
Dbg_Update_3 : out std_logic;
Dbg_Rst_3 : out std_logic;
Dbg_Clk_4 : out std_logic;
Dbg_TDI_4 : out std_logic;
Dbg_TDO_4 : in std_logic;
Dbg_Reg_En_4 : out std_logic_vector(0 to 7);
Dbg_Capture_4 : out std_logic;
Dbg_Shift_4 : out std_logic;
Dbg_Update_4 : out std_logic;
Dbg_Rst_4 : out std_logic;
Dbg_Clk_5 : out std_logic;
Dbg_TDI_5 : out std_logic;
Dbg_TDO_5 : in std_logic;
Dbg_Reg_En_5 : out std_logic_vector(0 to 7);
Dbg_Capture_5 : out std_logic;
Dbg_Shift_5 : out std_logic;
Dbg_Update_5 : out std_logic;
Dbg_Rst_5 : out std_logic;
Dbg_Clk_6 : out std_logic;
Dbg_TDI_6 : out std_logic;
Dbg_TDO_6 : in std_logic;
Dbg_Reg_En_6 : out std_logic_vector(0 to 7);
Dbg_Capture_6 : out std_logic;
Dbg_Shift_6 : out std_logic;
Dbg_Update_6 : out std_logic;
Dbg_Rst_6 : out std_logic;
Dbg_Clk_7 : out std_logic;
Dbg_TDI_7 : out std_logic;
Dbg_TDO_7 : in std_logic;
Dbg_Reg_En_7 : out std_logic_vector(0 to 7);
Dbg_Capture_7 : out std_logic;
Dbg_Shift_7 : out std_logic;
Dbg_Update_7 : out std_logic;
Dbg_Rst_7 : out std_logic;
Dbg_Clk_8 : out std_logic;
Dbg_TDI_8 : out std_logic;
Dbg_TDO_8 : in std_logic;
Dbg_Reg_En_8 : out std_logic_vector(0 to 7);
Dbg_Capture_8 : out std_logic;
Dbg_Shift_8 : out std_logic;
Dbg_Update_8 : out std_logic;
Dbg_Rst_8 : out std_logic;
Dbg_Clk_9 : out std_logic;
Dbg_TDI_9 : out std_logic;
Dbg_TDO_9 : in std_logic;
Dbg_Reg_En_9 : out std_logic_vector(0 to 7);
Dbg_Capture_9 : out std_logic;
Dbg_Shift_9 : out std_logic;
Dbg_Update_9 : out std_logic;
Dbg_Rst_9 : out std_logic;
Dbg_Clk_10 : out std_logic;
Dbg_TDI_10 : out std_logic;
Dbg_TDO_10 : in std_logic;
Dbg_Reg_En_10 : out std_logic_vector(0 to 7);
Dbg_Capture_10 : out std_logic;
Dbg_Shift_10 : out std_logic;
Dbg_Update_10 : out std_logic;
Dbg_Rst_10 : out std_logic;
Dbg_Clk_11 : out std_logic;
Dbg_TDI_11 : out std_logic;
Dbg_TDO_11 : in std_logic;
Dbg_Reg_En_11 : out std_logic_vector(0 to 7);
Dbg_Capture_11 : out std_logic;
Dbg_Shift_11 : out std_logic;
Dbg_Update_11 : out std_logic;
Dbg_Rst_11 : out std_logic;
Dbg_Clk_12 : out std_logic;
Dbg_TDI_12 : out std_logic;
Dbg_TDO_12 : in std_logic;
Dbg_Reg_En_12 : out std_logic_vector(0 to 7);
Dbg_Capture_12 : out std_logic;
Dbg_Shift_12 : out std_logic;
Dbg_Update_12 : out std_logic;
Dbg_Rst_12 : out std_logic;
Dbg_Clk_13 : out std_logic;
Dbg_TDI_13 : out std_logic;
Dbg_TDO_13 : in std_logic;
Dbg_Reg_En_13 : out std_logic_vector(0 to 7);
Dbg_Capture_13 : out std_logic;
Dbg_Shift_13 : out std_logic;
Dbg_Update_13 : out std_logic;
Dbg_Rst_13 : out std_logic;
Dbg_Clk_14 : out std_logic;
Dbg_TDI_14 : out std_logic;
Dbg_TDO_14 : in std_logic;
Dbg_Reg_En_14 : out std_logic_vector(0 to 7);
Dbg_Capture_14 : out std_logic;
Dbg_Shift_14 : out std_logic;
Dbg_Update_14 : out std_logic;
Dbg_Rst_14 : out std_logic;
Dbg_Clk_15 : out std_logic;
Dbg_TDI_15 : out std_logic;
Dbg_TDO_15 : in std_logic;
Dbg_Reg_En_15 : out std_logic_vector(0 to 7);
Dbg_Capture_15 : out std_logic;
Dbg_Shift_15 : out std_logic;
Dbg_Update_15 : out std_logic;
Dbg_Rst_15 : out std_logic;
Dbg_Clk_16 : out std_logic;
Dbg_TDI_16 : out std_logic;
Dbg_TDO_16 : in std_logic;
Dbg_Reg_En_16 : out std_logic_vector(0 to 7);
Dbg_Capture_16 : out std_logic;
Dbg_Shift_16 : out std_logic;
Dbg_Update_16 : out std_logic;
Dbg_Rst_16 : out std_logic;
Dbg_Clk_17 : out std_logic;
Dbg_TDI_17 : out std_logic;
Dbg_TDO_17 : in std_logic;
Dbg_Reg_En_17 : out std_logic_vector(0 to 7);
Dbg_Capture_17 : out std_logic;
Dbg_Shift_17 : out std_logic;
Dbg_Update_17 : out std_logic;
Dbg_Rst_17 : out std_logic;
Dbg_Clk_18 : out std_logic;
Dbg_TDI_18 : out std_logic;
Dbg_TDO_18 : in std_logic;
Dbg_Reg_En_18 : out std_logic_vector(0 to 7);
Dbg_Capture_18 : out std_logic;
Dbg_Shift_18 : out std_logic;
Dbg_Update_18 : out std_logic;
Dbg_Rst_18 : out std_logic;
Dbg_Clk_19 : out std_logic;
Dbg_TDI_19 : out std_logic;
Dbg_TDO_19 : in std_logic;
Dbg_Reg_En_19 : out std_logic_vector(0 to 7);
Dbg_Capture_19 : out std_logic;
Dbg_Shift_19 : out std_logic;
Dbg_Update_19 : out std_logic;
Dbg_Rst_19 : out std_logic;
Dbg_Clk_20 : out std_logic;
Dbg_TDI_20 : out std_logic;
Dbg_TDO_20 : in std_logic;
Dbg_Reg_En_20 : out std_logic_vector(0 to 7);
Dbg_Capture_20 : out std_logic;
Dbg_Shift_20 : out std_logic;
Dbg_Update_20 : out std_logic;
Dbg_Rst_20 : out std_logic;
Dbg_Clk_21 : out std_logic;
Dbg_TDI_21 : out std_logic;
Dbg_TDO_21 : in std_logic;
Dbg_Reg_En_21 : out std_logic_vector(0 to 7);
Dbg_Capture_21 : out std_logic;
Dbg_Shift_21 : out std_logic;
Dbg_Update_21 : out std_logic;
Dbg_Rst_21 : out std_logic;
Dbg_Clk_22 : out std_logic;
Dbg_TDI_22 : out std_logic;
Dbg_TDO_22 : in std_logic;
Dbg_Reg_En_22 : out std_logic_vector(0 to 7);
Dbg_Capture_22 : out std_logic;
Dbg_Shift_22 : out std_logic;
Dbg_Update_22 : out std_logic;
Dbg_Rst_22 : out std_logic;
Dbg_Clk_23 : out std_logic;
Dbg_TDI_23 : out std_logic;
Dbg_TDO_23 : in std_logic;
Dbg_Reg_En_23 : out std_logic_vector(0 to 7);
Dbg_Capture_23 : out std_logic;
Dbg_Shift_23 : out std_logic;
Dbg_Update_23 : out std_logic;
Dbg_Rst_23 : out std_logic;
Dbg_Clk_24 : out std_logic;
Dbg_TDI_24 : out std_logic;
Dbg_TDO_24 : in std_logic;
Dbg_Reg_En_24 : out std_logic_vector(0 to 7);
Dbg_Capture_24 : out std_logic;
Dbg_Shift_24 : out std_logic;
Dbg_Update_24 : out std_logic;
Dbg_Rst_24 : out std_logic;
Dbg_Clk_25 : out std_logic;
Dbg_TDI_25 : out std_logic;
Dbg_TDO_25 : in std_logic;
Dbg_Reg_En_25 : out std_logic_vector(0 to 7);
Dbg_Capture_25 : out std_logic;
Dbg_Shift_25 : out std_logic;
Dbg_Update_25 : out std_logic;
Dbg_Rst_25 : out std_logic;
Dbg_Clk_26 : out std_logic;
Dbg_TDI_26 : out std_logic;
Dbg_TDO_26 : in std_logic;
Dbg_Reg_En_26 : out std_logic_vector(0 to 7);
Dbg_Capture_26 : out std_logic;
Dbg_Shift_26 : out std_logic;
Dbg_Update_26 : out std_logic;
Dbg_Rst_26 : out std_logic;
Dbg_Clk_27 : out std_logic;
Dbg_TDI_27 : out std_logic;
Dbg_TDO_27 : in std_logic;
Dbg_Reg_En_27 : out std_logic_vector(0 to 7);
Dbg_Capture_27 : out std_logic;
Dbg_Shift_27 : out std_logic;
Dbg_Update_27 : out std_logic;
Dbg_Rst_27 : out std_logic;
Dbg_Clk_28 : out std_logic;
Dbg_TDI_28 : out std_logic;
Dbg_TDO_28 : in std_logic;
Dbg_Reg_En_28 : out std_logic_vector(0 to 7);
Dbg_Capture_28 : out std_logic;
Dbg_Shift_28 : out std_logic;
Dbg_Update_28 : out std_logic;
Dbg_Rst_28 : out std_logic;
Dbg_Clk_29 : out std_logic;
Dbg_TDI_29 : out std_logic;
Dbg_TDO_29 : in std_logic;
Dbg_Reg_En_29 : out std_logic_vector(0 to 7);
Dbg_Capture_29 : out std_logic;
Dbg_Shift_29 : out std_logic;
Dbg_Update_29 : out std_logic;
Dbg_Rst_29 : out std_logic;
Dbg_Clk_30 : out std_logic;
Dbg_TDI_30 : out std_logic;
Dbg_TDO_30 : in std_logic;
Dbg_Reg_En_30 : out std_logic_vector(0 to 7);
Dbg_Capture_30 : out std_logic;
Dbg_Shift_30 : out std_logic;
Dbg_Update_30 : out std_logic;
Dbg_Rst_30 : out std_logic;
Dbg_Clk_31 : out std_logic;
Dbg_TDI_31 : out std_logic;
Dbg_TDO_31 : in std_logic;
Dbg_Reg_En_31 : out std_logic_vector(0 to 7);
Dbg_Capture_31 : out std_logic;
Dbg_Shift_31 : out std_logic;
Dbg_Update_31 : out std_logic;
Dbg_Rst_31 : out std_logic;
bscan_tdi : out std_logic;
bscan_reset : out std_logic;
bscan_shift : out std_logic;
bscan_update : out std_logic;
bscan_capture : out std_logic;
bscan_sel1 : out std_logic;
bscan_drck1 : out std_logic;
bscan_tdo1 : in std_logic;
bscan_ext_tdi : in std_logic;
bscan_ext_reset : in std_logic;
bscan_ext_shift : in std_logic;
bscan_ext_update : in std_logic;
bscan_ext_capture : in std_logic;
bscan_ext_sel : in std_logic;
bscan_ext_drck : in std_logic;
bscan_ext_tdo : out std_logic;
Ext_JTAG_DRCK : out std_logic;
Ext_JTAG_RESET : out std_logic;
Ext_JTAG_SEL : out std_logic;
Ext_JTAG_CAPTURE : out std_logic;
Ext_JTAG_SHIFT : out std_logic;
Ext_JTAG_UPDATE : out std_logic;
Ext_JTAG_TDI : out std_logic;
Ext_JTAG_TDO : in std_logic
);
end system_mdm_0_wrapper;
architecture STRUCTURE of system_mdm_0_wrapper is
component mdm is
generic (
C_FAMILY : STRING;
C_JTAG_CHAIN : INTEGER;
C_INTERCONNECT : INTEGER;
C_BASEADDR : STD_LOGIC_VECTOR;
C_HIGHADDR : STD_LOGIC_VECTOR;
C_SPLB_AWIDTH : INTEGER;
C_SPLB_DWIDTH : INTEGER;
C_SPLB_P2P : INTEGER;
C_SPLB_MID_WIDTH : INTEGER;
C_SPLB_NUM_MASTERS : INTEGER;
C_SPLB_NATIVE_DWIDTH : INTEGER;
C_SPLB_SUPPORT_BURSTS : INTEGER;
C_MB_DBG_PORTS : INTEGER;
C_USE_UART : INTEGER;
C_USE_BSCAN : integer;
C_S_AXI_ADDR_WIDTH : INTEGER;
C_S_AXI_DATA_WIDTH : INTEGER
);
port (
Interrupt : out std_logic;
Debug_SYS_Rst : out std_logic;
Ext_BRK : out std_logic;
Ext_NM_BRK : out std_logic;
S_AXI_ACLK : in std_logic;
S_AXI_ARESETN : in std_logic;
S_AXI_AWADDR : in std_logic_vector((C_S_AXI_ADDR_WIDTH-1) downto 0);
S_AXI_AWVALID : in std_logic;
S_AXI_AWREADY : out std_logic;
S_AXI_WDATA : in std_logic_vector((C_S_AXI_DATA_WIDTH-1) downto 0);
S_AXI_WSTRB : in std_logic_vector((C_S_AXI_DATA_WIDTH/8-1) downto 0);
S_AXI_WVALID : in std_logic;
S_AXI_WREADY : out std_logic;
S_AXI_BRESP : out std_logic_vector(1 downto 0);
S_AXI_BVALID : out std_logic;
S_AXI_BREADY : in std_logic;
S_AXI_ARADDR : in std_logic_vector((C_S_AXI_ADDR_WIDTH-1) downto 0);
S_AXI_ARVALID : in std_logic;
S_AXI_ARREADY : out std_logic;
S_AXI_RDATA : out std_logic_vector((C_S_AXI_DATA_WIDTH-1) downto 0);
S_AXI_RRESP : out std_logic_vector(1 downto 0);
S_AXI_RVALID : out std_logic;
S_AXI_RREADY : in std_logic;
SPLB_Clk : in std_logic;
SPLB_Rst : in std_logic;
PLB_ABus : in std_logic_vector(0 to 31);
PLB_UABus : in std_logic_vector(0 to 31);
PLB_PAValid : in std_logic;
PLB_SAValid : in std_logic;
PLB_rdPrim : in std_logic;
PLB_wrPrim : in std_logic;
PLB_masterID : in std_logic_vector(0 to (C_SPLB_MID_WIDTH-1));
PLB_abort : in std_logic;
PLB_busLock : in std_logic;
PLB_RNW : in std_logic;
PLB_BE : in std_logic_vector(0 to ((C_SPLB_DWIDTH/8)-1));
PLB_MSize : in std_logic_vector(0 to 1);
PLB_size : in std_logic_vector(0 to 3);
PLB_type : in std_logic_vector(0 to 2);
PLB_lockErr : in std_logic;
PLB_wrDBus : in std_logic_vector(0 to (C_SPLB_DWIDTH-1));
PLB_wrBurst : in std_logic;
PLB_rdBurst : in std_logic;
PLB_wrPendReq : in std_logic;
PLB_rdPendReq : in std_logic;
PLB_wrPendPri : in std_logic_vector(0 to 1);
PLB_rdPendPri : in std_logic_vector(0 to 1);
PLB_reqPri : in std_logic_vector(0 to 1);
PLB_TAttribute : in std_logic_vector(0 to 15);
Sl_addrAck : out std_logic;
Sl_SSize : out std_logic_vector(0 to 1);
Sl_wait : out std_logic;
Sl_rearbitrate : out std_logic;
Sl_wrDAck : out std_logic;
Sl_wrComp : out std_logic;
Sl_wrBTerm : out std_logic;
Sl_rdDBus : out std_logic_vector(0 to (C_SPLB_DWIDTH-1));
Sl_rdWdAddr : out std_logic_vector(0 to 3);
Sl_rdDAck : out std_logic;
Sl_rdComp : out std_logic;
Sl_rdBTerm : out std_logic;
Sl_MBusy : out std_logic_vector(0 to (C_SPLB_NUM_MASTERS-1));
Sl_MWrErr : out std_logic_vector(0 to (C_SPLB_NUM_MASTERS-1));
Sl_MRdErr : out std_logic_vector(0 to (C_SPLB_NUM_MASTERS-1));
Sl_MIRQ : out std_logic_vector(0 to (C_SPLB_NUM_MASTERS-1));
Dbg_Clk_0 : out std_logic;
Dbg_TDI_0 : out std_logic;
Dbg_TDO_0 : in std_logic;
Dbg_Reg_En_0 : out std_logic_vector(0 to 7);
Dbg_Capture_0 : out std_logic;
Dbg_Shift_0 : out std_logic;
Dbg_Update_0 : out std_logic;
Dbg_Rst_0 : out std_logic;
Dbg_Clk_1 : out std_logic;
Dbg_TDI_1 : out std_logic;
Dbg_TDO_1 : in std_logic;
Dbg_Reg_En_1 : out std_logic_vector(0 to 7);
Dbg_Capture_1 : out std_logic;
Dbg_Shift_1 : out std_logic;
Dbg_Update_1 : out std_logic;
Dbg_Rst_1 : out std_logic;
Dbg_Clk_2 : out std_logic;
Dbg_TDI_2 : out std_logic;
Dbg_TDO_2 : in std_logic;
Dbg_Reg_En_2 : out std_logic_vector(0 to 7);
Dbg_Capture_2 : out std_logic;
Dbg_Shift_2 : out std_logic;
Dbg_Update_2 : out std_logic;
Dbg_Rst_2 : out std_logic;
Dbg_Clk_3 : out std_logic;
Dbg_TDI_3 : out std_logic;
Dbg_TDO_3 : in std_logic;
Dbg_Reg_En_3 : out std_logic_vector(0 to 7);
Dbg_Capture_3 : out std_logic;
Dbg_Shift_3 : out std_logic;
Dbg_Update_3 : out std_logic;
Dbg_Rst_3 : out std_logic;
Dbg_Clk_4 : out std_logic;
Dbg_TDI_4 : out std_logic;
Dbg_TDO_4 : in std_logic;
Dbg_Reg_En_4 : out std_logic_vector(0 to 7);
Dbg_Capture_4 : out std_logic;
Dbg_Shift_4 : out std_logic;
Dbg_Update_4 : out std_logic;
Dbg_Rst_4 : out std_logic;
Dbg_Clk_5 : out std_logic;
Dbg_TDI_5 : out std_logic;
Dbg_TDO_5 : in std_logic;
Dbg_Reg_En_5 : out std_logic_vector(0 to 7);
Dbg_Capture_5 : out std_logic;
Dbg_Shift_5 : out std_logic;
Dbg_Update_5 : out std_logic;
Dbg_Rst_5 : out std_logic;
Dbg_Clk_6 : out std_logic;
Dbg_TDI_6 : out std_logic;
Dbg_TDO_6 : in std_logic;
Dbg_Reg_En_6 : out std_logic_vector(0 to 7);
Dbg_Capture_6 : out std_logic;
Dbg_Shift_6 : out std_logic;
Dbg_Update_6 : out std_logic;
Dbg_Rst_6 : out std_logic;
Dbg_Clk_7 : out std_logic;
Dbg_TDI_7 : out std_logic;
Dbg_TDO_7 : in std_logic;
Dbg_Reg_En_7 : out std_logic_vector(0 to 7);
Dbg_Capture_7 : out std_logic;
Dbg_Shift_7 : out std_logic;
Dbg_Update_7 : out std_logic;
Dbg_Rst_7 : out std_logic;
Dbg_Clk_8 : out std_logic;
Dbg_TDI_8 : out std_logic;
Dbg_TDO_8 : in std_logic;
Dbg_Reg_En_8 : out std_logic_vector(0 to 7);
Dbg_Capture_8 : out std_logic;
Dbg_Shift_8 : out std_logic;
Dbg_Update_8 : out std_logic;
Dbg_Rst_8 : out std_logic;
Dbg_Clk_9 : out std_logic;
Dbg_TDI_9 : out std_logic;
Dbg_TDO_9 : in std_logic;
Dbg_Reg_En_9 : out std_logic_vector(0 to 7);
Dbg_Capture_9 : out std_logic;
Dbg_Shift_9 : out std_logic;
Dbg_Update_9 : out std_logic;
Dbg_Rst_9 : out std_logic;
Dbg_Clk_10 : out std_logic;
Dbg_TDI_10 : out std_logic;
Dbg_TDO_10 : in std_logic;
Dbg_Reg_En_10 : out std_logic_vector(0 to 7);
Dbg_Capture_10 : out std_logic;
Dbg_Shift_10 : out std_logic;
Dbg_Update_10 : out std_logic;
Dbg_Rst_10 : out std_logic;
Dbg_Clk_11 : out std_logic;
Dbg_TDI_11 : out std_logic;
Dbg_TDO_11 : in std_logic;
Dbg_Reg_En_11 : out std_logic_vector(0 to 7);
Dbg_Capture_11 : out std_logic;
Dbg_Shift_11 : out std_logic;
Dbg_Update_11 : out std_logic;
Dbg_Rst_11 : out std_logic;
Dbg_Clk_12 : out std_logic;
Dbg_TDI_12 : out std_logic;
Dbg_TDO_12 : in std_logic;
Dbg_Reg_En_12 : out std_logic_vector(0 to 7);
Dbg_Capture_12 : out std_logic;
Dbg_Shift_12 : out std_logic;
Dbg_Update_12 : out std_logic;
Dbg_Rst_12 : out std_logic;
Dbg_Clk_13 : out std_logic;
Dbg_TDI_13 : out std_logic;
Dbg_TDO_13 : in std_logic;
Dbg_Reg_En_13 : out std_logic_vector(0 to 7);
Dbg_Capture_13 : out std_logic;
Dbg_Shift_13 : out std_logic;
Dbg_Update_13 : out std_logic;
Dbg_Rst_13 : out std_logic;
Dbg_Clk_14 : out std_logic;
Dbg_TDI_14 : out std_logic;
Dbg_TDO_14 : in std_logic;
Dbg_Reg_En_14 : out std_logic_vector(0 to 7);
Dbg_Capture_14 : out std_logic;
Dbg_Shift_14 : out std_logic;
Dbg_Update_14 : out std_logic;
Dbg_Rst_14 : out std_logic;
Dbg_Clk_15 : out std_logic;
Dbg_TDI_15 : out std_logic;
Dbg_TDO_15 : in std_logic;
Dbg_Reg_En_15 : out std_logic_vector(0 to 7);
Dbg_Capture_15 : out std_logic;
Dbg_Shift_15 : out std_logic;
Dbg_Update_15 : out std_logic;
Dbg_Rst_15 : out std_logic;
Dbg_Clk_16 : out std_logic;
Dbg_TDI_16 : out std_logic;
Dbg_TDO_16 : in std_logic;
Dbg_Reg_En_16 : out std_logic_vector(0 to 7);
Dbg_Capture_16 : out std_logic;
Dbg_Shift_16 : out std_logic;
Dbg_Update_16 : out std_logic;
Dbg_Rst_16 : out std_logic;
Dbg_Clk_17 : out std_logic;
Dbg_TDI_17 : out std_logic;
Dbg_TDO_17 : in std_logic;
Dbg_Reg_En_17 : out std_logic_vector(0 to 7);
Dbg_Capture_17 : out std_logic;
Dbg_Shift_17 : out std_logic;
Dbg_Update_17 : out std_logic;
Dbg_Rst_17 : out std_logic;
Dbg_Clk_18 : out std_logic;
Dbg_TDI_18 : out std_logic;
Dbg_TDO_18 : in std_logic;
Dbg_Reg_En_18 : out std_logic_vector(0 to 7);
Dbg_Capture_18 : out std_logic;
Dbg_Shift_18 : out std_logic;
Dbg_Update_18 : out std_logic;
Dbg_Rst_18 : out std_logic;
Dbg_Clk_19 : out std_logic;
Dbg_TDI_19 : out std_logic;
Dbg_TDO_19 : in std_logic;
Dbg_Reg_En_19 : out std_logic_vector(0 to 7);
Dbg_Capture_19 : out std_logic;
Dbg_Shift_19 : out std_logic;
Dbg_Update_19 : out std_logic;
Dbg_Rst_19 : out std_logic;
Dbg_Clk_20 : out std_logic;
Dbg_TDI_20 : out std_logic;
Dbg_TDO_20 : in std_logic;
Dbg_Reg_En_20 : out std_logic_vector(0 to 7);
Dbg_Capture_20 : out std_logic;
Dbg_Shift_20 : out std_logic;
Dbg_Update_20 : out std_logic;
Dbg_Rst_20 : out std_logic;
Dbg_Clk_21 : out std_logic;
Dbg_TDI_21 : out std_logic;
Dbg_TDO_21 : in std_logic;
Dbg_Reg_En_21 : out std_logic_vector(0 to 7);
Dbg_Capture_21 : out std_logic;
Dbg_Shift_21 : out std_logic;
Dbg_Update_21 : out std_logic;
Dbg_Rst_21 : out std_logic;
Dbg_Clk_22 : out std_logic;
Dbg_TDI_22 : out std_logic;
Dbg_TDO_22 : in std_logic;
Dbg_Reg_En_22 : out std_logic_vector(0 to 7);
Dbg_Capture_22 : out std_logic;
Dbg_Shift_22 : out std_logic;
Dbg_Update_22 : out std_logic;
Dbg_Rst_22 : out std_logic;
Dbg_Clk_23 : out std_logic;
Dbg_TDI_23 : out std_logic;
Dbg_TDO_23 : in std_logic;
Dbg_Reg_En_23 : out std_logic_vector(0 to 7);
Dbg_Capture_23 : out std_logic;
Dbg_Shift_23 : out std_logic;
Dbg_Update_23 : out std_logic;
Dbg_Rst_23 : out std_logic;
Dbg_Clk_24 : out std_logic;
Dbg_TDI_24 : out std_logic;
Dbg_TDO_24 : in std_logic;
Dbg_Reg_En_24 : out std_logic_vector(0 to 7);
Dbg_Capture_24 : out std_logic;
Dbg_Shift_24 : out std_logic;
Dbg_Update_24 : out std_logic;
Dbg_Rst_24 : out std_logic;
Dbg_Clk_25 : out std_logic;
Dbg_TDI_25 : out std_logic;
Dbg_TDO_25 : in std_logic;
Dbg_Reg_En_25 : out std_logic_vector(0 to 7);
Dbg_Capture_25 : out std_logic;
Dbg_Shift_25 : out std_logic;
Dbg_Update_25 : out std_logic;
Dbg_Rst_25 : out std_logic;
Dbg_Clk_26 : out std_logic;
Dbg_TDI_26 : out std_logic;
Dbg_TDO_26 : in std_logic;
Dbg_Reg_En_26 : out std_logic_vector(0 to 7);
Dbg_Capture_26 : out std_logic;
Dbg_Shift_26 : out std_logic;
Dbg_Update_26 : out std_logic;
Dbg_Rst_26 : out std_logic;
Dbg_Clk_27 : out std_logic;
Dbg_TDI_27 : out std_logic;
Dbg_TDO_27 : in std_logic;
Dbg_Reg_En_27 : out std_logic_vector(0 to 7);
Dbg_Capture_27 : out std_logic;
Dbg_Shift_27 : out std_logic;
Dbg_Update_27 : out std_logic;
Dbg_Rst_27 : out std_logic;
Dbg_Clk_28 : out std_logic;
Dbg_TDI_28 : out std_logic;
Dbg_TDO_28 : in std_logic;
Dbg_Reg_En_28 : out std_logic_vector(0 to 7);
Dbg_Capture_28 : out std_logic;
Dbg_Shift_28 : out std_logic;
Dbg_Update_28 : out std_logic;
Dbg_Rst_28 : out std_logic;
Dbg_Clk_29 : out std_logic;
Dbg_TDI_29 : out std_logic;
Dbg_TDO_29 : in std_logic;
Dbg_Reg_En_29 : out std_logic_vector(0 to 7);
Dbg_Capture_29 : out std_logic;
Dbg_Shift_29 : out std_logic;
Dbg_Update_29 : out std_logic;
Dbg_Rst_29 : out std_logic;
Dbg_Clk_30 : out std_logic;
Dbg_TDI_30 : out std_logic;
Dbg_TDO_30 : in std_logic;
Dbg_Reg_En_30 : out std_logic_vector(0 to 7);
Dbg_Capture_30 : out std_logic;
Dbg_Shift_30 : out std_logic;
Dbg_Update_30 : out std_logic;
Dbg_Rst_30 : out std_logic;
Dbg_Clk_31 : out std_logic;
Dbg_TDI_31 : out std_logic;
Dbg_TDO_31 : in std_logic;
Dbg_Reg_En_31 : out std_logic_vector(0 to 7);
Dbg_Capture_31 : out std_logic;
Dbg_Shift_31 : out std_logic;
Dbg_Update_31 : out std_logic;
Dbg_Rst_31 : out std_logic;
bscan_tdi : out std_logic;
bscan_reset : out std_logic;
bscan_shift : out std_logic;
bscan_update : out std_logic;
bscan_capture : out std_logic;
bscan_sel1 : out std_logic;
bscan_drck1 : out std_logic;
bscan_tdo1 : in std_logic;
bscan_ext_tdi : in std_logic;
bscan_ext_reset : in std_logic;
bscan_ext_shift : in std_logic;
bscan_ext_update : in std_logic;
bscan_ext_capture : in std_logic;
bscan_ext_sel : in std_logic;
bscan_ext_drck : in std_logic;
bscan_ext_tdo : out std_logic;
Ext_JTAG_DRCK : out std_logic;
Ext_JTAG_RESET : out std_logic;
Ext_JTAG_SEL : out std_logic;
Ext_JTAG_CAPTURE : out std_logic;
Ext_JTAG_SHIFT : out std_logic;
Ext_JTAG_UPDATE : out std_logic;
Ext_JTAG_TDI : out std_logic;
Ext_JTAG_TDO : in std_logic
);
end component;
begin
mdm_0 : mdm
generic map (
C_FAMILY => "virtex5",
C_JTAG_CHAIN => 2,
C_INTERCONNECT => 1,
C_BASEADDR => X"84400000",
C_HIGHADDR => X"8440ffff",
C_SPLB_AWIDTH => 32,
C_SPLB_DWIDTH => 64,
C_SPLB_P2P => 0,
C_SPLB_MID_WIDTH => 3,
C_SPLB_NUM_MASTERS => 7,
C_SPLB_NATIVE_DWIDTH => 32,
C_SPLB_SUPPORT_BURSTS => 1,
C_MB_DBG_PORTS => 1,
C_USE_UART => 1,
C_USE_BSCAN => 0,
C_S_AXI_ADDR_WIDTH => 32,
C_S_AXI_DATA_WIDTH => 32
)
port map (
Interrupt => Interrupt,
Debug_SYS_Rst => Debug_SYS_Rst,
Ext_BRK => Ext_BRK,
Ext_NM_BRK => Ext_NM_BRK,
S_AXI_ACLK => S_AXI_ACLK,
S_AXI_ARESETN => S_AXI_ARESETN,
S_AXI_AWADDR => S_AXI_AWADDR,
S_AXI_AWVALID => S_AXI_AWVALID,
S_AXI_AWREADY => S_AXI_AWREADY,
S_AXI_WDATA => S_AXI_WDATA,
S_AXI_WSTRB => S_AXI_WSTRB,
S_AXI_WVALID => S_AXI_WVALID,
S_AXI_WREADY => S_AXI_WREADY,
S_AXI_BRESP => S_AXI_BRESP,
S_AXI_BVALID => S_AXI_BVALID,
S_AXI_BREADY => S_AXI_BREADY,
S_AXI_ARADDR => S_AXI_ARADDR,
S_AXI_ARVALID => S_AXI_ARVALID,
S_AXI_ARREADY => S_AXI_ARREADY,
S_AXI_RDATA => S_AXI_RDATA,
S_AXI_RRESP => S_AXI_RRESP,
S_AXI_RVALID => S_AXI_RVALID,
S_AXI_RREADY => S_AXI_RREADY,
SPLB_Clk => SPLB_Clk,
SPLB_Rst => SPLB_Rst,
PLB_ABus => PLB_ABus,
PLB_UABus => PLB_UABus,
PLB_PAValid => PLB_PAValid,
PLB_SAValid => PLB_SAValid,
PLB_rdPrim => PLB_rdPrim,
PLB_wrPrim => PLB_wrPrim,
PLB_masterID => PLB_masterID,
PLB_abort => PLB_abort,
PLB_busLock => PLB_busLock,
PLB_RNW => PLB_RNW,
PLB_BE => PLB_BE,
PLB_MSize => PLB_MSize,
PLB_size => PLB_size,
PLB_type => PLB_type,
PLB_lockErr => PLB_lockErr,
PLB_wrDBus => PLB_wrDBus,
PLB_wrBurst => PLB_wrBurst,
PLB_rdBurst => PLB_rdBurst,
PLB_wrPendReq => PLB_wrPendReq,
PLB_rdPendReq => PLB_rdPendReq,
PLB_wrPendPri => PLB_wrPendPri,
PLB_rdPendPri => PLB_rdPendPri,
PLB_reqPri => PLB_reqPri,
PLB_TAttribute => PLB_TAttribute,
Sl_addrAck => Sl_addrAck,
Sl_SSize => Sl_SSize,
Sl_wait => Sl_wait,
Sl_rearbitrate => Sl_rearbitrate,
Sl_wrDAck => Sl_wrDAck,
Sl_wrComp => Sl_wrComp,
Sl_wrBTerm => Sl_wrBTerm,
Sl_rdDBus => Sl_rdDBus,
Sl_rdWdAddr => Sl_rdWdAddr,
Sl_rdDAck => Sl_rdDAck,
Sl_rdComp => Sl_rdComp,
Sl_rdBTerm => Sl_rdBTerm,
Sl_MBusy => Sl_MBusy,
Sl_MWrErr => Sl_MWrErr,
Sl_MRdErr => Sl_MRdErr,
Sl_MIRQ => Sl_MIRQ,
Dbg_Clk_0 => Dbg_Clk_0,
Dbg_TDI_0 => Dbg_TDI_0,
Dbg_TDO_0 => Dbg_TDO_0,
Dbg_Reg_En_0 => Dbg_Reg_En_0,
Dbg_Capture_0 => Dbg_Capture_0,
Dbg_Shift_0 => Dbg_Shift_0,
Dbg_Update_0 => Dbg_Update_0,
Dbg_Rst_0 => Dbg_Rst_0,
Dbg_Clk_1 => Dbg_Clk_1,
Dbg_TDI_1 => Dbg_TDI_1,
Dbg_TDO_1 => Dbg_TDO_1,
Dbg_Reg_En_1 => Dbg_Reg_En_1,
Dbg_Capture_1 => Dbg_Capture_1,
Dbg_Shift_1 => Dbg_Shift_1,
Dbg_Update_1 => Dbg_Update_1,
Dbg_Rst_1 => Dbg_Rst_1,
Dbg_Clk_2 => Dbg_Clk_2,
Dbg_TDI_2 => Dbg_TDI_2,
Dbg_TDO_2 => Dbg_TDO_2,
Dbg_Reg_En_2 => Dbg_Reg_En_2,
Dbg_Capture_2 => Dbg_Capture_2,
Dbg_Shift_2 => Dbg_Shift_2,
Dbg_Update_2 => Dbg_Update_2,
Dbg_Rst_2 => Dbg_Rst_2,
Dbg_Clk_3 => Dbg_Clk_3,
Dbg_TDI_3 => Dbg_TDI_3,
Dbg_TDO_3 => Dbg_TDO_3,
Dbg_Reg_En_3 => Dbg_Reg_En_3,
Dbg_Capture_3 => Dbg_Capture_3,
Dbg_Shift_3 => Dbg_Shift_3,
Dbg_Update_3 => Dbg_Update_3,
Dbg_Rst_3 => Dbg_Rst_3,
Dbg_Clk_4 => Dbg_Clk_4,
Dbg_TDI_4 => Dbg_TDI_4,
Dbg_TDO_4 => Dbg_TDO_4,
Dbg_Reg_En_4 => Dbg_Reg_En_4,
Dbg_Capture_4 => Dbg_Capture_4,
Dbg_Shift_4 => Dbg_Shift_4,
Dbg_Update_4 => Dbg_Update_4,
Dbg_Rst_4 => Dbg_Rst_4,
Dbg_Clk_5 => Dbg_Clk_5,
Dbg_TDI_5 => Dbg_TDI_5,
Dbg_TDO_5 => Dbg_TDO_5,
Dbg_Reg_En_5 => Dbg_Reg_En_5,
Dbg_Capture_5 => Dbg_Capture_5,
Dbg_Shift_5 => Dbg_Shift_5,
Dbg_Update_5 => Dbg_Update_5,
Dbg_Rst_5 => Dbg_Rst_5,
Dbg_Clk_6 => Dbg_Clk_6,
Dbg_TDI_6 => Dbg_TDI_6,
Dbg_TDO_6 => Dbg_TDO_6,
Dbg_Reg_En_6 => Dbg_Reg_En_6,
Dbg_Capture_6 => Dbg_Capture_6,
Dbg_Shift_6 => Dbg_Shift_6,
Dbg_Update_6 => Dbg_Update_6,
Dbg_Rst_6 => Dbg_Rst_6,
Dbg_Clk_7 => Dbg_Clk_7,
Dbg_TDI_7 => Dbg_TDI_7,
Dbg_TDO_7 => Dbg_TDO_7,
Dbg_Reg_En_7 => Dbg_Reg_En_7,
Dbg_Capture_7 => Dbg_Capture_7,
Dbg_Shift_7 => Dbg_Shift_7,
Dbg_Update_7 => Dbg_Update_7,
Dbg_Rst_7 => Dbg_Rst_7,
Dbg_Clk_8 => Dbg_Clk_8,
Dbg_TDI_8 => Dbg_TDI_8,
Dbg_TDO_8 => Dbg_TDO_8,
Dbg_Reg_En_8 => Dbg_Reg_En_8,
Dbg_Capture_8 => Dbg_Capture_8,
Dbg_Shift_8 => Dbg_Shift_8,
Dbg_Update_8 => Dbg_Update_8,
Dbg_Rst_8 => Dbg_Rst_8,
Dbg_Clk_9 => Dbg_Clk_9,
Dbg_TDI_9 => Dbg_TDI_9,
Dbg_TDO_9 => Dbg_TDO_9,
Dbg_Reg_En_9 => Dbg_Reg_En_9,
Dbg_Capture_9 => Dbg_Capture_9,
Dbg_Shift_9 => Dbg_Shift_9,
Dbg_Update_9 => Dbg_Update_9,
Dbg_Rst_9 => Dbg_Rst_9,
Dbg_Clk_10 => Dbg_Clk_10,
Dbg_TDI_10 => Dbg_TDI_10,
Dbg_TDO_10 => Dbg_TDO_10,
Dbg_Reg_En_10 => Dbg_Reg_En_10,
Dbg_Capture_10 => Dbg_Capture_10,
Dbg_Shift_10 => Dbg_Shift_10,
Dbg_Update_10 => Dbg_Update_10,
Dbg_Rst_10 => Dbg_Rst_10,
Dbg_Clk_11 => Dbg_Clk_11,
Dbg_TDI_11 => Dbg_TDI_11,
Dbg_TDO_11 => Dbg_TDO_11,
Dbg_Reg_En_11 => Dbg_Reg_En_11,
Dbg_Capture_11 => Dbg_Capture_11,
Dbg_Shift_11 => Dbg_Shift_11,
Dbg_Update_11 => Dbg_Update_11,
Dbg_Rst_11 => Dbg_Rst_11,
Dbg_Clk_12 => Dbg_Clk_12,
Dbg_TDI_12 => Dbg_TDI_12,
Dbg_TDO_12 => Dbg_TDO_12,
Dbg_Reg_En_12 => Dbg_Reg_En_12,
Dbg_Capture_12 => Dbg_Capture_12,
Dbg_Shift_12 => Dbg_Shift_12,
Dbg_Update_12 => Dbg_Update_12,
Dbg_Rst_12 => Dbg_Rst_12,
Dbg_Clk_13 => Dbg_Clk_13,
Dbg_TDI_13 => Dbg_TDI_13,
Dbg_TDO_13 => Dbg_TDO_13,
Dbg_Reg_En_13 => Dbg_Reg_En_13,
Dbg_Capture_13 => Dbg_Capture_13,
Dbg_Shift_13 => Dbg_Shift_13,
Dbg_Update_13 => Dbg_Update_13,
Dbg_Rst_13 => Dbg_Rst_13,
Dbg_Clk_14 => Dbg_Clk_14,
Dbg_TDI_14 => Dbg_TDI_14,
Dbg_TDO_14 => Dbg_TDO_14,
Dbg_Reg_En_14 => Dbg_Reg_En_14,
Dbg_Capture_14 => Dbg_Capture_14,
Dbg_Shift_14 => Dbg_Shift_14,
Dbg_Update_14 => Dbg_Update_14,
Dbg_Rst_14 => Dbg_Rst_14,
Dbg_Clk_15 => Dbg_Clk_15,
Dbg_TDI_15 => Dbg_TDI_15,
Dbg_TDO_15 => Dbg_TDO_15,
Dbg_Reg_En_15 => Dbg_Reg_En_15,
Dbg_Capture_15 => Dbg_Capture_15,
Dbg_Shift_15 => Dbg_Shift_15,
Dbg_Update_15 => Dbg_Update_15,
Dbg_Rst_15 => Dbg_Rst_15,
Dbg_Clk_16 => Dbg_Clk_16,
Dbg_TDI_16 => Dbg_TDI_16,
Dbg_TDO_16 => Dbg_TDO_16,
Dbg_Reg_En_16 => Dbg_Reg_En_16,
Dbg_Capture_16 => Dbg_Capture_16,
Dbg_Shift_16 => Dbg_Shift_16,
Dbg_Update_16 => Dbg_Update_16,
Dbg_Rst_16 => Dbg_Rst_16,
Dbg_Clk_17 => Dbg_Clk_17,
Dbg_TDI_17 => Dbg_TDI_17,
Dbg_TDO_17 => Dbg_TDO_17,
Dbg_Reg_En_17 => Dbg_Reg_En_17,
Dbg_Capture_17 => Dbg_Capture_17,
Dbg_Shift_17 => Dbg_Shift_17,
Dbg_Update_17 => Dbg_Update_17,
Dbg_Rst_17 => Dbg_Rst_17,
Dbg_Clk_18 => Dbg_Clk_18,
Dbg_TDI_18 => Dbg_TDI_18,
Dbg_TDO_18 => Dbg_TDO_18,
Dbg_Reg_En_18 => Dbg_Reg_En_18,
Dbg_Capture_18 => Dbg_Capture_18,
Dbg_Shift_18 => Dbg_Shift_18,
Dbg_Update_18 => Dbg_Update_18,
Dbg_Rst_18 => Dbg_Rst_18,
Dbg_Clk_19 => Dbg_Clk_19,
Dbg_TDI_19 => Dbg_TDI_19,
Dbg_TDO_19 => Dbg_TDO_19,
Dbg_Reg_En_19 => Dbg_Reg_En_19,
Dbg_Capture_19 => Dbg_Capture_19,
Dbg_Shift_19 => Dbg_Shift_19,
Dbg_Update_19 => Dbg_Update_19,
Dbg_Rst_19 => Dbg_Rst_19,
Dbg_Clk_20 => Dbg_Clk_20,
Dbg_TDI_20 => Dbg_TDI_20,
Dbg_TDO_20 => Dbg_TDO_20,
Dbg_Reg_En_20 => Dbg_Reg_En_20,
Dbg_Capture_20 => Dbg_Capture_20,
Dbg_Shift_20 => Dbg_Shift_20,
Dbg_Update_20 => Dbg_Update_20,
Dbg_Rst_20 => Dbg_Rst_20,
Dbg_Clk_21 => Dbg_Clk_21,
Dbg_TDI_21 => Dbg_TDI_21,
Dbg_TDO_21 => Dbg_TDO_21,
Dbg_Reg_En_21 => Dbg_Reg_En_21,
Dbg_Capture_21 => Dbg_Capture_21,
Dbg_Shift_21 => Dbg_Shift_21,
Dbg_Update_21 => Dbg_Update_21,
Dbg_Rst_21 => Dbg_Rst_21,
Dbg_Clk_22 => Dbg_Clk_22,
Dbg_TDI_22 => Dbg_TDI_22,
Dbg_TDO_22 => Dbg_TDO_22,
Dbg_Reg_En_22 => Dbg_Reg_En_22,
Dbg_Capture_22 => Dbg_Capture_22,
Dbg_Shift_22 => Dbg_Shift_22,
Dbg_Update_22 => Dbg_Update_22,
Dbg_Rst_22 => Dbg_Rst_22,
Dbg_Clk_23 => Dbg_Clk_23,
Dbg_TDI_23 => Dbg_TDI_23,
Dbg_TDO_23 => Dbg_TDO_23,
Dbg_Reg_En_23 => Dbg_Reg_En_23,
Dbg_Capture_23 => Dbg_Capture_23,
Dbg_Shift_23 => Dbg_Shift_23,
Dbg_Update_23 => Dbg_Update_23,
Dbg_Rst_23 => Dbg_Rst_23,
Dbg_Clk_24 => Dbg_Clk_24,
Dbg_TDI_24 => Dbg_TDI_24,
Dbg_TDO_24 => Dbg_TDO_24,
Dbg_Reg_En_24 => Dbg_Reg_En_24,
Dbg_Capture_24 => Dbg_Capture_24,
Dbg_Shift_24 => Dbg_Shift_24,
Dbg_Update_24 => Dbg_Update_24,
Dbg_Rst_24 => Dbg_Rst_24,
Dbg_Clk_25 => Dbg_Clk_25,
Dbg_TDI_25 => Dbg_TDI_25,
Dbg_TDO_25 => Dbg_TDO_25,
Dbg_Reg_En_25 => Dbg_Reg_En_25,
Dbg_Capture_25 => Dbg_Capture_25,
Dbg_Shift_25 => Dbg_Shift_25,
Dbg_Update_25 => Dbg_Update_25,
Dbg_Rst_25 => Dbg_Rst_25,
Dbg_Clk_26 => Dbg_Clk_26,
Dbg_TDI_26 => Dbg_TDI_26,
Dbg_TDO_26 => Dbg_TDO_26,
Dbg_Reg_En_26 => Dbg_Reg_En_26,
Dbg_Capture_26 => Dbg_Capture_26,
Dbg_Shift_26 => Dbg_Shift_26,
Dbg_Update_26 => Dbg_Update_26,
Dbg_Rst_26 => Dbg_Rst_26,
Dbg_Clk_27 => Dbg_Clk_27,
Dbg_TDI_27 => Dbg_TDI_27,
Dbg_TDO_27 => Dbg_TDO_27,
Dbg_Reg_En_27 => Dbg_Reg_En_27,
Dbg_Capture_27 => Dbg_Capture_27,
Dbg_Shift_27 => Dbg_Shift_27,
Dbg_Update_27 => Dbg_Update_27,
Dbg_Rst_27 => Dbg_Rst_27,
Dbg_Clk_28 => Dbg_Clk_28,
Dbg_TDI_28 => Dbg_TDI_28,
Dbg_TDO_28 => Dbg_TDO_28,
Dbg_Reg_En_28 => Dbg_Reg_En_28,
Dbg_Capture_28 => Dbg_Capture_28,
Dbg_Shift_28 => Dbg_Shift_28,
Dbg_Update_28 => Dbg_Update_28,
Dbg_Rst_28 => Dbg_Rst_28,
Dbg_Clk_29 => Dbg_Clk_29,
Dbg_TDI_29 => Dbg_TDI_29,
Dbg_TDO_29 => Dbg_TDO_29,
Dbg_Reg_En_29 => Dbg_Reg_En_29,
Dbg_Capture_29 => Dbg_Capture_29,
Dbg_Shift_29 => Dbg_Shift_29,
Dbg_Update_29 => Dbg_Update_29,
Dbg_Rst_29 => Dbg_Rst_29,
Dbg_Clk_30 => Dbg_Clk_30,
Dbg_TDI_30 => Dbg_TDI_30,
Dbg_TDO_30 => Dbg_TDO_30,
Dbg_Reg_En_30 => Dbg_Reg_En_30,
Dbg_Capture_30 => Dbg_Capture_30,
Dbg_Shift_30 => Dbg_Shift_30,
Dbg_Update_30 => Dbg_Update_30,
Dbg_Rst_30 => Dbg_Rst_30,
Dbg_Clk_31 => Dbg_Clk_31,
Dbg_TDI_31 => Dbg_TDI_31,
Dbg_TDO_31 => Dbg_TDO_31,
Dbg_Reg_En_31 => Dbg_Reg_En_31,
Dbg_Capture_31 => Dbg_Capture_31,
Dbg_Shift_31 => Dbg_Shift_31,
Dbg_Update_31 => Dbg_Update_31,
Dbg_Rst_31 => Dbg_Rst_31,
bscan_tdi => bscan_tdi,
bscan_reset => bscan_reset,
bscan_shift => bscan_shift,
bscan_update => bscan_update,
bscan_capture => bscan_capture,
bscan_sel1 => bscan_sel1,
bscan_drck1 => bscan_drck1,
bscan_tdo1 => bscan_tdo1,
bscan_ext_tdi => bscan_ext_tdi,
bscan_ext_reset => bscan_ext_reset,
bscan_ext_shift => bscan_ext_shift,
bscan_ext_update => bscan_ext_update,
bscan_ext_capture => bscan_ext_capture,
bscan_ext_sel => bscan_ext_sel,
bscan_ext_drck => bscan_ext_drck,
bscan_ext_tdo => bscan_ext_tdo,
Ext_JTAG_DRCK => Ext_JTAG_DRCK,
Ext_JTAG_RESET => Ext_JTAG_RESET,
Ext_JTAG_SEL => Ext_JTAG_SEL,
Ext_JTAG_CAPTURE => Ext_JTAG_CAPTURE,
Ext_JTAG_SHIFT => Ext_JTAG_SHIFT,
Ext_JTAG_UPDATE => Ext_JTAG_UPDATE,
Ext_JTAG_TDI => Ext_JTAG_TDI,
Ext_JTAG_TDO => Ext_JTAG_TDO
);
end architecture STRUCTURE;
| lgpl-3.0 | 3587792ec98dbc56c8a953735644ffb3 | 0.575528 | 2.800144 | false | false | false | false |
grwlf/vsim | vhdl_ct/ct00195.vhd | 1 | 4,269 | -- NEED RESULT: ARCH00195.P2: Transaction occurred on signal asg with no time expression -- 0 ns assumed passed
-- NEED RESULT: ARCH00195.P1: Transaction occurred on signal asg with no time expression -- 0 ns assumed passed
-- NEED RESULT: P2: Transport transactions entirely completed passed
-- NEED RESULT: P1: Transport transactions entirely completed passed
-------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
-------------------------------------------------------------------------------
--
-- TEST NAME:
--
-- CT00195
--
-- AUTHOR:
--
-- G. Tominovich
--
-- TEST OBJECTIVES:
--
-- 8.3.1 (1)
-- 8.3.1 (6)
--
-- DESIGN UNIT ORDERING:
--
-- E00000(ARCH00195)
-- ENT00195_Test_Bench(ARCH00195_Test_Bench)
--
-- REVISION HISTORY:
--
-- 09-JUL-1987 - initial revision
--
-- NOTES:
--
-- self-checking
-- automatically generated
--
use WORK.STANDARD_TYPES.all ;
architecture ARCH00195 of E00000 is
subtype chk_sig_type is integer range -1 to 100 ;
signal chk_real : chk_sig_type := -1 ;
signal chk_st_real1 : chk_sig_type := -1 ;
--
signal s_real : real
:= c_real_1 ;
signal s_st_real1 : st_real1
:= c_st_real1_1 ;
--
begin
PGEN_CHKP_1 :
process ( chk_real )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P1" ,
"Transport transactions entirely completed",
chk_real = 1 ) ;
end if ;
end process PGEN_CHKP_1 ;
--
P1 :
process ( s_real )
variable correct : boolean ;
variable counter : integer := 0 ;
variable savtime : time ;
begin
case counter is
when 0
=> s_real <= Transport
50.0 ;
--
when 1
=> correct :=
s_real = 50.0 and
savtime = Std.Standard.Now ;
test_report ( "ARCH00195.P1" ,
"Transaction occurred on signal asg with no " &
" time expression -- 0 ns assumed",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00195.P1" ,
"Transaction occurred on signal asg with no " &
" time expression -- 0 ns assumed",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_real <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
end process P1 ;
--
PGEN_CHKP_2 :
process ( chk_st_real1 )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P2" ,
"Transport transactions entirely completed",
chk_st_real1 = 1 ) ;
end if ;
end process PGEN_CHKP_2 ;
--
P2 :
process ( s_st_real1 )
variable correct : boolean ;
variable counter : integer := 0 ;
variable savtime : time ;
begin
case counter is
when 0
=> s_st_real1 <= Transport
50.0 ;
--
when 1
=> correct :=
s_st_real1 = 50.0 and
savtime = Std.Standard.Now ;
test_report ( "ARCH00195.P2" ,
"Transaction occurred on signal asg with no " &
" time expression -- 0 ns assumed",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00195.P2" ,
"Transaction occurred on signal asg with no " &
" time expression -- 0 ns assumed",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_st_real1 <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
end process P2 ;
--
--
end ARCH00195 ;
--
entity ENT00195_Test_Bench is
end ENT00195_Test_Bench ;
--
architecture ARCH00195_Test_Bench of ENT00195_Test_Bench is
begin
L1:
block
component UUT
end component ;
for CIS1 : UUT use entity WORK.E00000 ( ARCH00195 ) ;
begin
CIS1 : UUT ;
end block L1 ;
end ARCH00195_Test_Bench ;
| gpl-3.0 | fbe6081e83f983c786a5fc75e28af9d8 | 0.513235 | 3.771201 | false | true | false | false |
grwlf/vsim | vhdl_ct/ct00439.vhd | 1 | 4,859 | -------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
-------------------------------------------------------------------------------
--
-- TEST NAME:
--
-- CT00439
--
-- AUTHOR:
--
-- A. Wilmot
--
-- TEST OBJECTIVES:
--
-- 7.2.4 (1)
-- 7.2.4 (4)
-- 7.2.4 (11)
-- 7.2.4 (12)
-- 7.2.4 (13)
--
-- DESIGN UNIT ORDERING:
--
-- ENT00439(ARCH00439)
-- ENT00439_Test_Bench(ARCH00439_Test_Bench)
--
-- REVISION HISTORY:
--
-- 29-JUL-1987 - initial revision
-- 6-JUN-1988 - JTH
--
-- NOTES:
--
-- self-checking
--
use WORK.STANDARD_TYPES.test_report, WORK.STANDARD_TYPES.print ;
use WORK.ARITHMETIC.ALL ;
entity ENT00439 is
generic (
i_int_1 : integer := c_int_1 ;
i_int_2 : integer := c_int_2 ;
i_t_int_1 : t_int := c_t_int_1 ;
i_t_int_2 : t_int := c_t_int_2 ;
i_st_int_1 : st_int := c_st_int_1 ;
i_st_int_2 : st_int := c_st_int_2
) ;
port ( locally_static_correct : out boolean ;
globally_static_correct : out boolean ;
dynamic_correct : out boolean ) ;
end ENT00439 ;
architecture ARCH00439 of ENT00439 is
constant c2_int_1 : integer :=
(-10) mod i_int_1 + i_int_1 mod i_int_2 + i_int_1 mod (i_int_1 - 1)
- i_int_2 mod (c_int_2 + 1) ;
constant c2_t_int_1 : t_int :=
(1) mod i_t_int_1 + (i_t_int_1) mod i_t_int_2 + (-i_t_int_1) mod 2 -
c_t_int_2 mod (i_t_int_2 - 1) ;
constant c2_st_int_1 : st_int :=
(-0) mod i_st_int_2 + i_t_int_1 mod (i_st_int_1) +
(i_st_int_1 mod i_t_int_2) - (c_st_int_2) mod i_t_int_2 ;
begin
process
variable bool : boolean := true ;
variable cons_correct, gen_correct, dyn_correct : boolean := true ;
--
variable v_int_1, v2_int_1 : integer := i_int_1 ;
variable v_int_2, v2_int_2 : integer := i_int_2 ;
variable v_t_int_1, v2_t_int_1 : t_int := i_t_int_1 ;
variable v_t_int_2, v2_t_int_2 : t_int := i_t_int_2 ;
variable v_st_int_1, v2_st_int_1 : st_int := i_st_int_1 ;
variable v_st_int_2, v2_st_int_2 : st_int := i_st_int_2 ;
--
begin
-- static expression
case bool is
when (
(-10) mod c_int_1 + c_int_1 mod c_int_2 + c_int_1 mod (c_int_1 - 1)
- c_int_2 mod (c_int_2 + 1) = -2 and
(1) mod c_t_int_1 + (c_t_int_1) mod c_t_int_2 + (-c_t_int_1) mod 2 -
c_t_int_2 mod (c_t_int_2 - 1) = 3 and
(-0) mod c_st_int_2 + c_t_int_1 mod (c_st_int_1) +
(c_st_int_1 mod c_t_int_2) - (c_st_int_2) mod c_t_int_2 = 0
) =>
null ;
when others =>
cons_correct := false ;
end case ;
-- generic expression
gen_correct := c2_int_1 = -2 and
c2_t_int_1 = 3 and
c2_st_int_1 = 0 ;
-- dynamic expression
v2_int_1 :=
(-10) mod v_int_1 + v_int_1 mod v_int_2 + v_int_1 mod (v_int_1 - 1)
- v_int_2 mod (i_int_2 + 1) ;
v2_t_int_1 :=
(1) mod v_t_int_1 + (v_t_int_1) mod v_t_int_2 + (-v_t_int_1) mod 2 -
c_t_int_2 mod (v_t_int_2 - 1) ;
v2_st_int_1 :=
(-0) mod v_st_int_2 + v_t_int_1 mod (v_st_int_1) +
(v_st_int_1 mod v_t_int_2) - (i_st_int_2) mod v_t_int_2 ;
dyn_correct := v2_int_1 = -2 and
v2_t_int_1 = 3 and
v2_st_int_1 = 0 ;
locally_static_correct <= cons_correct ;
globally_static_correct <= gen_correct ;
dynamic_correct <= dyn_correct ;
wait ;
end process ;
end ARCH00439 ;
use WORK.STANDARD_TYPES.test_report, WORK.STANDARD_TYPES.print ;
use WORK.ARITHMETIC.ALL ;
entity ENT00439_Test_Bench is
end ENT00439_Test_Bench ;
architecture ARCH00439_Test_Bench of ENT00439_Test_Bench is
begin
L1:
block
signal locally_static_correct, globally_static_correct,
dynamic_correct : boolean := false ;
component UUT
port ( locally_static_correct : inout boolean ;
globally_static_correct : inout boolean ;
dynamic_correct : inout boolean ) ;
end component ;
for CIS1 : UUT use entity WORK.ENT00439 ( ARCH00439 ) ;
begin
CIS1 : UUT
port map ( locally_static_correct,
globally_static_correct,
dynamic_correct ) ;
process ( locally_static_correct, globally_static_correct,
dynamic_correct )
begin
if locally_static_correct and globally_static_correct and
dynamic_correct then
test_report ( "ARCH00439" ,
"mod predefined for integer types" ,
true ) ;
end if ;
end process ;
end block L1 ;
end ARCH00439_Test_Bench ;
| gpl-3.0 | 7207976deec61e4775b3762acc3efe38 | 0.504219 | 2.846514 | false | true | false | false |
grwlf/vsim | vhdl_ct/ct00105.vhd | 1 | 5,784 | -- NEED RESULT: ARCH00105.P1: Multi transport transactions occurred on signal asg with slice name prefixed by an indexed name on LHS passed
-- NEED RESULT: ARCH00105: One transport transaction occurred on signal asg with slice name prefixed by an indexed name on LHS passed
-- NEED RESULT: ARCH00105: Old transactions were removed on signal asg with slice name prefixed by an indexed name on LHS passed
-- NEED RESULT: P1: Transport transactions entirely completed passed
-------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
-------------------------------------------------------------------------------
--
-- TEST NAME:
--
-- CT00105
--
-- AUTHOR:
--
-- G. Tominovich
--
-- TEST OBJECTIVES:
--
-- 8.3 (2)
-- 8.3 (3)
-- 8.3 (5)
-- 8.3.1 (3)
--
-- DESIGN UNIT ORDERING:
--
-- ENT00105(ARCH00105)
-- ENT00105_Test_Bench(ARCH00105_Test_Bench)
--
-- REVISION HISTORY:
--
-- 07-JUL-1987 - initial revision
--
-- NOTES:
--
-- self-checking
-- automatically generated
--
use WORK.STANDARD_TYPES.all ;
entity ENT00105 is
port (
s_st_arr1_vector : inout st_arr1_vector
) ;
subtype chk_sig_type is integer range -1 to 100 ;
signal chk_st_arr1_vector : chk_sig_type := -1 ;
--
end ENT00105 ;
--
architecture ARCH00105 of ENT00105 is
begin
PGEN_CHKP_1 :
process ( chk_st_arr1_vector )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P1" ,
"Transport transactions entirely completed",
chk_st_arr1_vector = 4 ) ;
end if ;
end process PGEN_CHKP_1 ;
--
P1 :
process ( s_st_arr1_vector )
variable correct : boolean ;
variable counter : integer := 0 ;
variable savtime : time ;
--
procedure Proc1 is
begin
case counter is
when 0
=> s_st_arr1_vector(lowb) (lowb+1 to highb-1) <= transport
c_st_arr1_vector_2(highb)
(lowb+1 to highb-1) after 10 ns,
c_st_arr1_vector_1(highb)
(lowb+1 to highb-1) after 20 ns ;
--
when 1
=> correct :=
s_st_arr1_vector(lowb) (lowb+1 to highb-1) =
c_st_arr1_vector_2(highb) (lowb+1 to highb-1) and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_arr1_vector(lowb) (lowb+1 to highb-1) =
c_st_arr1_vector_1(highb) (lowb+1 to highb-1) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00105.P1" ,
"Multi transport transactions occurred on signal " &
"asg with slice name prefixed by an indexed name on LHS",
correct ) ;
s_st_arr1_vector(lowb) (lowb+1 to highb-1) <= transport
c_st_arr1_vector_2(highb)
(lowb+1 to highb-1) after 10 ns ,
c_st_arr1_vector_1(highb)
(lowb+1 to highb-1) after 20 ns ,
c_st_arr1_vector_2(highb)
(lowb+1 to highb-1) after 30 ns ,
c_st_arr1_vector_1(highb)
(lowb+1 to highb-1) after 40 ns ;
--
when 3
=> correct :=
s_st_arr1_vector(lowb) (lowb+1 to highb-1) =
c_st_arr1_vector_2(highb) (lowb+1 to highb-1) and
(savtime + 10 ns) = Std.Standard.Now ;
s_st_arr1_vector(lowb) (lowb+1 to highb-1) <= transport
c_st_arr1_vector_1(highb)
(lowb+1 to highb-1) after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_arr1_vector(lowb) (lowb+1 to highb-1) =
c_st_arr1_vector_1(highb) (lowb+1 to highb-1) and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00105" ,
"One transport transaction occurred on signal " &
"asg with slice name prefixed by an indexed name on LHS",
correct ) ;
test_report ( "ARCH00105" ,
"Old transactions were removed on signal " &
"asg with slice name prefixed by an indexed name on LHS",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00105" ,
"Old transactions were removed on signal " &
"asg with slice name prefixed by an indexed name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_st_arr1_vector <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
end Proc1 ;
--
begin
Proc1 ;
end process P1 ;
--
--
end ARCH00105 ;
--
use WORK.STANDARD_TYPES.all ;
entity ENT00105_Test_Bench is
signal s_st_arr1_vector : st_arr1_vector
:= c_st_arr1_vector_1 ;
--
end ENT00105_Test_Bench ;
--
architecture ARCH00105_Test_Bench of ENT00105_Test_Bench is
begin
L1:
block
component UUT
port (
s_st_arr1_vector : inout st_arr1_vector
) ;
end component ;
--
for CIS1 : UUT use entity WORK.ENT00105 ( ARCH00105 ) ;
begin
CIS1 : UUT
port map (
s_st_arr1_vector
) ;
end block L1 ;
end ARCH00105_Test_Bench ;
| gpl-3.0 | 337625d8a0e7d1803a0a5318922ba676 | 0.496715 | 3.583643 | false | true | false | false |
takeshineshiro/fpga_fibre_scan | HUCB2P0_150701/adc_pll.vhd | 1 | 18,077 | -- megafunction wizard: %Altera PLL v14.0%
-- GENERATION: XML
-- adc_pll.vhd
-- Generated using ACDS version 14.0 200 at 2015.06.18.16:00:31
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity adc_pll is
port (
refclk : in std_logic := '0'; -- refclk.clk
rst : in std_logic := '0'; -- reset.reset
outclk_0 : out std_logic; -- outclk0.clk
outclk_1 : out std_logic -- outclk1.clk
);
end entity adc_pll;
architecture rtl of adc_pll is
component adc_pll_0002 is
port (
refclk : in std_logic := 'X'; -- clk
rst : in std_logic := 'X'; -- reset
outclk_0 : out std_logic; -- clk
outclk_1 : out std_logic; -- clk
locked : out std_logic -- export
);
end component adc_pll_0002;
begin
adc_pll_inst : component adc_pll_0002
port map (
refclk => refclk, -- refclk.clk
rst => rst, -- reset.reset
outclk_0 => outclk_0, -- outclk0.clk
outclk_1 => outclk_1, -- outclk1.clk
locked => open -- (terminated)
);
end architecture rtl; -- of adc_pll
-- Retrieval info: <?xml version="1.0"?>
--<!--
-- Generated by Altera MegaWizard Launcher Utility version 1.0
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
-- ************************************************************
-- Copyright (C) 1991-2015 Altera Corporation
-- Any megafunction design, and related net list (encrypted or decrypted),
-- support information, device programming or simulation file, and any other
-- associated documentation or information provided by Altera or a partner
-- under Altera's Megafunction Partnership Program may be used only to
-- program PLD devices (but not masked PLD devices) from Altera. Any other
-- use of such megafunction design, net list, support information, device
-- programming or simulation file, or any other related documentation or
-- information is prohibited for any other purpose, including, but not
-- limited to modification, reverse engineering, de-compiling, or use with
-- any other silicon devices, unless such use is explicitly licensed under
-- a separate agreement with Altera or a megafunction partner. Title to
-- the intellectual property, including patents, copyrights, trademarks,
-- trade secrets, or maskworks, embodied in any such megafunction design,
-- net list, support information, device programming or simulation file, or
-- any other related documentation or information provided by Altera or a
-- megafunction partner, remains with Altera, the megafunction partner, or
-- their respective licensors. No other licenses, including any licenses
-- needed under any third party's intellectual property, are provided herein.
---->
-- Retrieval info: <instance entity-name="altera_pll" version="14.0" >
-- Retrieval info: <generic name="debug_print_output" value="false" />
-- Retrieval info: <generic name="debug_use_rbc_taf_method" value="false" />
-- Retrieval info: <generic name="device_family" value="Cyclone V" />
-- Retrieval info: <generic name="device" value="Unknown" />
-- Retrieval info: <generic name="gui_device_speed_grade" value="8" />
-- Retrieval info: <generic name="gui_pll_mode" value="Integer-N PLL" />
-- Retrieval info: <generic name="gui_reference_clock_frequency" value="240.0" />
-- Retrieval info: <generic name="gui_channel_spacing" value="0.0" />
-- Retrieval info: <generic name="gui_operation_mode" value="normal" />
-- Retrieval info: <generic name="gui_feedback_clock" value="Global Clock" />
-- Retrieval info: <generic name="gui_fractional_cout" value="32" />
-- Retrieval info: <generic name="gui_dsm_out_sel" value="1st_order" />
-- Retrieval info: <generic name="gui_use_locked" value="false" />
-- Retrieval info: <generic name="gui_en_adv_params" value="false" />
-- Retrieval info: <generic name="gui_number_of_clocks" value="2" />
-- Retrieval info: <generic name="gui_multiply_factor" value="1" />
-- Retrieval info: <generic name="gui_frac_multiply_factor" value="1" />
-- Retrieval info: <generic name="gui_divide_factor_n" value="1" />
-- Retrieval info: <generic name="gui_cascade_counter0" value="false" />
-- Retrieval info: <generic name="gui_output_clock_frequency0" value="60.0" />
-- Retrieval info: <generic name="gui_divide_factor_c0" value="1" />
-- Retrieval info: <generic name="gui_actual_output_clock_frequency0" value="0 MHz" />
-- Retrieval info: <generic name="gui_ps_units0" value="degrees" />
-- Retrieval info: <generic name="gui_phase_shift0" value="0" />
-- Retrieval info: <generic name="gui_phase_shift_deg0" value="50.0" />
-- Retrieval info: <generic name="gui_actual_phase_shift0" value="0" />
-- Retrieval info: <generic name="gui_duty_cycle0" value="50" />
-- Retrieval info: <generic name="gui_cascade_counter1" value="false" />
-- Retrieval info: <generic name="gui_output_clock_frequency1" value="60.0" />
-- Retrieval info: <generic name="gui_divide_factor_c1" value="1" />
-- Retrieval info: <generic name="gui_actual_output_clock_frequency1" value="0 MHz" />
-- Retrieval info: <generic name="gui_ps_units1" value="degrees" />
-- Retrieval info: <generic name="gui_phase_shift1" value="0" />
-- Retrieval info: <generic name="gui_phase_shift_deg1" value="50.0" />
-- Retrieval info: <generic name="gui_actual_phase_shift1" value="0" />
-- Retrieval info: <generic name="gui_duty_cycle1" value="50" />
-- Retrieval info: <generic name="gui_cascade_counter2" value="false" />
-- Retrieval info: <generic name="gui_output_clock_frequency2" value="100.0" />
-- Retrieval info: <generic name="gui_divide_factor_c2" value="1" />
-- Retrieval info: <generic name="gui_actual_output_clock_frequency2" value="0 MHz" />
-- Retrieval info: <generic name="gui_ps_units2" value="ps" />
-- Retrieval info: <generic name="gui_phase_shift2" value="0" />
-- Retrieval info: <generic name="gui_phase_shift_deg2" value="0.0" />
-- Retrieval info: <generic name="gui_actual_phase_shift2" value="0" />
-- Retrieval info: <generic name="gui_duty_cycle2" value="50" />
-- Retrieval info: <generic name="gui_cascade_counter3" value="false" />
-- Retrieval info: <generic name="gui_output_clock_frequency3" value="100.0" />
-- Retrieval info: <generic name="gui_divide_factor_c3" value="1" />
-- Retrieval info: <generic name="gui_actual_output_clock_frequency3" value="0 MHz" />
-- Retrieval info: <generic name="gui_ps_units3" value="ps" />
-- Retrieval info: <generic name="gui_phase_shift3" value="0" />
-- Retrieval info: <generic name="gui_phase_shift_deg3" value="0.0" />
-- Retrieval info: <generic name="gui_actual_phase_shift3" value="0" />
-- Retrieval info: <generic name="gui_duty_cycle3" value="50" />
-- Retrieval info: <generic name="gui_cascade_counter4" value="false" />
-- Retrieval info: <generic name="gui_output_clock_frequency4" value="100.0" />
-- Retrieval info: <generic name="gui_divide_factor_c4" value="1" />
-- Retrieval info: <generic name="gui_actual_output_clock_frequency4" value="0 MHz" />
-- Retrieval info: <generic name="gui_ps_units4" value="ps" />
-- Retrieval info: <generic name="gui_phase_shift4" value="0" />
-- Retrieval info: <generic name="gui_phase_shift_deg4" value="0.0" />
-- Retrieval info: <generic name="gui_actual_phase_shift4" value="0" />
-- Retrieval info: <generic name="gui_duty_cycle4" value="50" />
-- Retrieval info: <generic name="gui_cascade_counter5" value="false" />
-- Retrieval info: <generic name="gui_output_clock_frequency5" value="100.0" />
-- Retrieval info: <generic name="gui_divide_factor_c5" value="1" />
-- Retrieval info: <generic name="gui_actual_output_clock_frequency5" value="0 MHz" />
-- Retrieval info: <generic name="gui_ps_units5" value="ps" />
-- Retrieval info: <generic name="gui_phase_shift5" value="0" />
-- Retrieval info: <generic name="gui_phase_shift_deg5" value="0.0" />
-- Retrieval info: <generic name="gui_actual_phase_shift5" value="0" />
-- Retrieval info: <generic name="gui_duty_cycle5" value="50" />
-- Retrieval info: <generic name="gui_cascade_counter6" value="false" />
-- Retrieval info: <generic name="gui_output_clock_frequency6" value="100.0" />
-- Retrieval info: <generic name="gui_divide_factor_c6" value="1" />
-- Retrieval info: <generic name="gui_actual_output_clock_frequency6" value="0 MHz" />
-- Retrieval info: <generic name="gui_ps_units6" value="ps" />
-- Retrieval info: <generic name="gui_phase_shift6" value="0" />
-- Retrieval info: <generic name="gui_phase_shift_deg6" value="0.0" />
-- Retrieval info: <generic name="gui_actual_phase_shift6" value="0" />
-- Retrieval info: <generic name="gui_duty_cycle6" value="50" />
-- Retrieval info: <generic name="gui_cascade_counter7" value="false" />
-- Retrieval info: <generic name="gui_output_clock_frequency7" value="100.0" />
-- Retrieval info: <generic name="gui_divide_factor_c7" value="1" />
-- Retrieval info: <generic name="gui_actual_output_clock_frequency7" value="0 MHz" />
-- Retrieval info: <generic name="gui_ps_units7" value="ps" />
-- Retrieval info: <generic name="gui_phase_shift7" value="0" />
-- Retrieval info: <generic name="gui_phase_shift_deg7" value="0.0" />
-- Retrieval info: <generic name="gui_actual_phase_shift7" value="0" />
-- Retrieval info: <generic name="gui_duty_cycle7" value="50" />
-- Retrieval info: <generic name="gui_cascade_counter8" value="false" />
-- Retrieval info: <generic name="gui_output_clock_frequency8" value="100.0" />
-- Retrieval info: <generic name="gui_divide_factor_c8" value="1" />
-- Retrieval info: <generic name="gui_actual_output_clock_frequency8" value="0 MHz" />
-- Retrieval info: <generic name="gui_ps_units8" value="ps" />
-- Retrieval info: <generic name="gui_phase_shift8" value="0" />
-- Retrieval info: <generic name="gui_phase_shift_deg8" value="0.0" />
-- Retrieval info: <generic name="gui_actual_phase_shift8" value="0" />
-- Retrieval info: <generic name="gui_duty_cycle8" value="50" />
-- Retrieval info: <generic name="gui_cascade_counter9" value="false" />
-- Retrieval info: <generic name="gui_output_clock_frequency9" value="100.0" />
-- Retrieval info: <generic name="gui_divide_factor_c9" value="1" />
-- Retrieval info: <generic name="gui_actual_output_clock_frequency9" value="0 MHz" />
-- Retrieval info: <generic name="gui_ps_units9" value="ps" />
-- Retrieval info: <generic name="gui_phase_shift9" value="0" />
-- Retrieval info: <generic name="gui_phase_shift_deg9" value="0.0" />
-- Retrieval info: <generic name="gui_actual_phase_shift9" value="0" />
-- Retrieval info: <generic name="gui_duty_cycle9" value="50" />
-- Retrieval info: <generic name="gui_cascade_counter10" value="false" />
-- Retrieval info: <generic name="gui_output_clock_frequency10" value="100.0" />
-- Retrieval info: <generic name="gui_divide_factor_c10" value="1" />
-- Retrieval info: <generic name="gui_actual_output_clock_frequency10" value="0 MHz" />
-- Retrieval info: <generic name="gui_ps_units10" value="ps" />
-- Retrieval info: <generic name="gui_phase_shift10" value="0" />
-- Retrieval info: <generic name="gui_phase_shift_deg10" value="0.0" />
-- Retrieval info: <generic name="gui_actual_phase_shift10" value="0" />
-- Retrieval info: <generic name="gui_duty_cycle10" value="50" />
-- Retrieval info: <generic name="gui_cascade_counter11" value="false" />
-- Retrieval info: <generic name="gui_output_clock_frequency11" value="100.0" />
-- Retrieval info: <generic name="gui_divide_factor_c11" value="1" />
-- Retrieval info: <generic name="gui_actual_output_clock_frequency11" value="0 MHz" />
-- Retrieval info: <generic name="gui_ps_units11" value="ps" />
-- Retrieval info: <generic name="gui_phase_shift11" value="0" />
-- Retrieval info: <generic name="gui_phase_shift_deg11" value="0.0" />
-- Retrieval info: <generic name="gui_actual_phase_shift11" value="0" />
-- Retrieval info: <generic name="gui_duty_cycle11" value="50" />
-- Retrieval info: <generic name="gui_cascade_counter12" value="false" />
-- Retrieval info: <generic name="gui_output_clock_frequency12" value="100.0" />
-- Retrieval info: <generic name="gui_divide_factor_c12" value="1" />
-- Retrieval info: <generic name="gui_actual_output_clock_frequency12" value="0 MHz" />
-- Retrieval info: <generic name="gui_ps_units12" value="ps" />
-- Retrieval info: <generic name="gui_phase_shift12" value="0" />
-- Retrieval info: <generic name="gui_phase_shift_deg12" value="0.0" />
-- Retrieval info: <generic name="gui_actual_phase_shift12" value="0" />
-- Retrieval info: <generic name="gui_duty_cycle12" value="50" />
-- Retrieval info: <generic name="gui_cascade_counter13" value="false" />
-- Retrieval info: <generic name="gui_output_clock_frequency13" value="100.0" />
-- Retrieval info: <generic name="gui_divide_factor_c13" value="1" />
-- Retrieval info: <generic name="gui_actual_output_clock_frequency13" value="0 MHz" />
-- Retrieval info: <generic name="gui_ps_units13" value="ps" />
-- Retrieval info: <generic name="gui_phase_shift13" value="0" />
-- Retrieval info: <generic name="gui_phase_shift_deg13" value="0.0" />
-- Retrieval info: <generic name="gui_actual_phase_shift13" value="0" />
-- Retrieval info: <generic name="gui_duty_cycle13" value="50" />
-- Retrieval info: <generic name="gui_cascade_counter14" value="false" />
-- Retrieval info: <generic name="gui_output_clock_frequency14" value="100.0" />
-- Retrieval info: <generic name="gui_divide_factor_c14" value="1" />
-- Retrieval info: <generic name="gui_actual_output_clock_frequency14" value="0 MHz" />
-- Retrieval info: <generic name="gui_ps_units14" value="ps" />
-- Retrieval info: <generic name="gui_phase_shift14" value="0" />
-- Retrieval info: <generic name="gui_phase_shift_deg14" value="0.0" />
-- Retrieval info: <generic name="gui_actual_phase_shift14" value="0" />
-- Retrieval info: <generic name="gui_duty_cycle14" value="50" />
-- Retrieval info: <generic name="gui_cascade_counter15" value="false" />
-- Retrieval info: <generic name="gui_output_clock_frequency15" value="100.0" />
-- Retrieval info: <generic name="gui_divide_factor_c15" value="1" />
-- Retrieval info: <generic name="gui_actual_output_clock_frequency15" value="0 MHz" />
-- Retrieval info: <generic name="gui_ps_units15" value="ps" />
-- Retrieval info: <generic name="gui_phase_shift15" value="0" />
-- Retrieval info: <generic name="gui_phase_shift_deg15" value="0.0" />
-- Retrieval info: <generic name="gui_actual_phase_shift15" value="0" />
-- Retrieval info: <generic name="gui_duty_cycle15" value="50" />
-- Retrieval info: <generic name="gui_cascade_counter16" value="false" />
-- Retrieval info: <generic name="gui_output_clock_frequency16" value="100.0" />
-- Retrieval info: <generic name="gui_divide_factor_c16" value="1" />
-- Retrieval info: <generic name="gui_actual_output_clock_frequency16" value="0 MHz" />
-- Retrieval info: <generic name="gui_ps_units16" value="ps" />
-- Retrieval info: <generic name="gui_phase_shift16" value="0" />
-- Retrieval info: <generic name="gui_phase_shift_deg16" value="0.0" />
-- Retrieval info: <generic name="gui_actual_phase_shift16" value="0" />
-- Retrieval info: <generic name="gui_duty_cycle16" value="50" />
-- Retrieval info: <generic name="gui_cascade_counter17" value="false" />
-- Retrieval info: <generic name="gui_output_clock_frequency17" value="100.0" />
-- Retrieval info: <generic name="gui_divide_factor_c17" value="1" />
-- Retrieval info: <generic name="gui_actual_output_clock_frequency17" value="0 MHz" />
-- Retrieval info: <generic name="gui_ps_units17" value="ps" />
-- Retrieval info: <generic name="gui_phase_shift17" value="0" />
-- Retrieval info: <generic name="gui_phase_shift_deg17" value="0.0" />
-- Retrieval info: <generic name="gui_actual_phase_shift17" value="0" />
-- Retrieval info: <generic name="gui_duty_cycle17" value="50" />
-- Retrieval info: <generic name="gui_pll_auto_reset" value="Off" />
-- Retrieval info: <generic name="gui_pll_bandwidth_preset" value="Auto" />
-- Retrieval info: <generic name="gui_en_reconf" value="false" />
-- Retrieval info: <generic name="gui_en_dps_ports" value="false" />
-- Retrieval info: <generic name="gui_en_phout_ports" value="false" />
-- Retrieval info: <generic name="gui_phout_division" value="1" />
-- Retrieval info: <generic name="gui_en_lvds_ports" value="false" />
-- Retrieval info: <generic name="gui_mif_generate" value="false" />
-- Retrieval info: <generic name="gui_enable_mif_dps" value="false" />
-- Retrieval info: <generic name="gui_dps_cntr" value="C0" />
-- Retrieval info: <generic name="gui_dps_num" value="1" />
-- Retrieval info: <generic name="gui_dps_dir" value="Positive" />
-- Retrieval info: <generic name="gui_refclk_switch" value="false" />
-- Retrieval info: <generic name="gui_refclk1_frequency" value="100.0" />
-- Retrieval info: <generic name="gui_switchover_mode" value="Automatic Switchover" />
-- Retrieval info: <generic name="gui_switchover_delay" value="0" />
-- Retrieval info: <generic name="gui_active_clk" value="false" />
-- Retrieval info: <generic name="gui_clk_bad" value="false" />
-- Retrieval info: <generic name="gui_enable_cascade_out" value="false" />
-- Retrieval info: <generic name="gui_cascade_outclk_index" value="0" />
-- Retrieval info: <generic name="gui_enable_cascade_in" value="false" />
-- Retrieval info: <generic name="gui_pll_cascading_mode" value="Create an adjpllin signal to connect with an upstream PLL" />
-- Retrieval info: <generic name="AUTO_REFCLK_CLOCK_RATE" value="-1" />
-- Retrieval info: </instance>
-- IPFS_FILES : adc_pll.vho
-- RELATED_FILES: adc_pll.vhd, adc_pll_0002.v
| apache-2.0 | 9424f18586bc8ad0e7375a1b28f7b52c | 0.672623 | 3.002824 | false | false | false | false |
jairov4/accel-oil | solution_virtex5_plb/syn/vhdl/nfa_get_initials_1.vhd | 1 | 13,390 | -- ==============================================================
-- RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2014.1
-- Copyright (C) 2014 Xilinx Inc. All rights reserved.
--
-- ===========================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity nfa_get_initials_1 is
port (
ap_clk : IN STD_LOGIC;
ap_rst : IN STD_LOGIC;
ap_start : IN STD_LOGIC;
ap_done : OUT STD_LOGIC;
ap_idle : OUT STD_LOGIC;
ap_ready : OUT STD_LOGIC;
nfa_initials_buckets_req_din : OUT STD_LOGIC;
nfa_initials_buckets_req_full_n : IN STD_LOGIC;
nfa_initials_buckets_req_write : OUT STD_LOGIC;
nfa_initials_buckets_rsp_empty_n : IN STD_LOGIC;
nfa_initials_buckets_rsp_read : OUT STD_LOGIC;
nfa_initials_buckets_address : OUT STD_LOGIC_VECTOR (31 downto 0);
nfa_initials_buckets_datain : IN STD_LOGIC_VECTOR (63 downto 0);
nfa_initials_buckets_dataout : OUT STD_LOGIC_VECTOR (63 downto 0);
nfa_initials_buckets_size : OUT STD_LOGIC_VECTOR (31 downto 0);
ap_ce : IN STD_LOGIC;
initials_buckets_address0 : OUT STD_LOGIC_VECTOR (3 downto 0);
initials_buckets_ce0 : OUT STD_LOGIC;
initials_buckets_we0 : OUT STD_LOGIC;
initials_buckets_d0 : OUT STD_LOGIC_VECTOR (63 downto 0);
tmp_s : IN STD_LOGIC_VECTOR (4 downto 0) );
end;
architecture behav of nfa_get_initials_1 is
constant ap_const_logic_1 : STD_LOGIC := '1';
constant ap_const_logic_0 : STD_LOGIC := '0';
constant ap_ST_pp0_stg0_fsm_0 : STD_LOGIC_VECTOR (0 downto 0) := "0";
constant ap_const_lv32_0 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000000";
constant ap_const_lv32_1 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000001";
constant ap_const_lv64_0 : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000";
signal ap_CS_fsm : STD_LOGIC_VECTOR (0 downto 0) := "0";
signal ap_reg_ppiten_pp0_it0 : STD_LOGIC;
signal ap_reg_ppiten_pp0_it1 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it2 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it3 : STD_LOGIC := '0';
signal tmp_read_reg_67 : STD_LOGIC_VECTOR (4 downto 0);
signal ap_reg_ppstg_tmp_read_reg_67_pp0_it1 : STD_LOGIC_VECTOR (4 downto 0);
signal ap_reg_ppstg_tmp_read_reg_67_pp0_it2 : STD_LOGIC_VECTOR (4 downto 0);
signal nfa_initials_buckets_read_reg_72 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_cast_fu_63_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal ap_NS_fsm : STD_LOGIC_VECTOR (0 downto 0);
signal ap_sig_pprstidle_pp0 : STD_LOGIC;
begin
-- the current state (ap_CS_fsm) of the state machine. --
ap_CS_fsm_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_CS_fsm <= ap_ST_pp0_stg0_fsm_0;
else
ap_CS_fsm <= ap_NS_fsm;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it1 assign process. --
ap_reg_ppiten_pp0_it1_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_reg_ppiten_pp0_it1 <= ap_const_logic_0;
else
if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it2) and (nfa_initials_buckets_rsp_empty_n = ap_const_logic_0)) or not((ap_const_logic_1 = ap_ce)))))) then
ap_reg_ppiten_pp0_it1 <= ap_reg_ppiten_pp0_it0;
end if;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it2 assign process. --
ap_reg_ppiten_pp0_it2_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_reg_ppiten_pp0_it2 <= ap_const_logic_0;
else
if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it2) and (nfa_initials_buckets_rsp_empty_n = ap_const_logic_0)) or not((ap_const_logic_1 = ap_ce)))))) then
ap_reg_ppiten_pp0_it2 <= ap_reg_ppiten_pp0_it1;
end if;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it3 assign process. --
ap_reg_ppiten_pp0_it3_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_reg_ppiten_pp0_it3 <= ap_const_logic_0;
else
if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it2) and (nfa_initials_buckets_rsp_empty_n = ap_const_logic_0)) or not((ap_const_logic_1 = ap_ce)))))) then
ap_reg_ppiten_pp0_it3 <= ap_reg_ppiten_pp0_it2;
end if;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it2) and (nfa_initials_buckets_rsp_empty_n = ap_const_logic_0)))) and (ap_const_logic_1 = ap_ce))) then
ap_reg_ppstg_tmp_read_reg_67_pp0_it1 <= tmp_read_reg_67;
ap_reg_ppstg_tmp_read_reg_67_pp0_it2 <= ap_reg_ppstg_tmp_read_reg_67_pp0_it1;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it2) and (nfa_initials_buckets_rsp_empty_n = ap_const_logic_0)))) and (ap_const_logic_1 = ap_ce))) then
nfa_initials_buckets_read_reg_72 <= nfa_initials_buckets_datain;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it2) and (nfa_initials_buckets_rsp_empty_n = ap_const_logic_0)))) and (ap_const_logic_1 = ap_ce))) then
tmp_read_reg_67 <= tmp_s;
end if;
end if;
end process;
-- the next state (ap_NS_fsm) of the state machine. --
ap_NS_fsm_assign_proc : process (ap_start , ap_CS_fsm , ap_reg_ppiten_pp0_it0 , ap_reg_ppiten_pp0_it2 , nfa_initials_buckets_rsp_empty_n , ap_ce , ap_sig_pprstidle_pp0)
begin
case ap_CS_fsm is
when ap_ST_pp0_stg0_fsm_0 =>
ap_NS_fsm <= ap_ST_pp0_stg0_fsm_0;
when others =>
ap_NS_fsm <= "X";
end case;
end process;
-- ap_done assign process. --
ap_done_assign_proc : process(ap_start, ap_CS_fsm, ap_reg_ppiten_pp0_it0, ap_reg_ppiten_pp0_it2, ap_reg_ppiten_pp0_it3, nfa_initials_buckets_rsp_empty_n, ap_ce)
begin
if (((not((ap_const_logic_1 = ap_start)) and (ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it0)) or ((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it3) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it2) and (nfa_initials_buckets_rsp_empty_n = ap_const_logic_0)))) and (ap_const_logic_1 = ap_ce)))) then
ap_done <= ap_const_logic_1;
else
ap_done <= ap_const_logic_0;
end if;
end process;
-- ap_idle assign process. --
ap_idle_assign_proc : process(ap_start, ap_CS_fsm, ap_reg_ppiten_pp0_it0, ap_reg_ppiten_pp0_it1, ap_reg_ppiten_pp0_it2, ap_reg_ppiten_pp0_it3)
begin
if ((not((ap_const_logic_1 = ap_start)) and (ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it0) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it1) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it2) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it3))) then
ap_idle <= ap_const_logic_1;
else
ap_idle <= ap_const_logic_0;
end if;
end process;
-- ap_ready assign process. --
ap_ready_assign_proc : process(ap_start, ap_CS_fsm, ap_reg_ppiten_pp0_it0, ap_reg_ppiten_pp0_it2, nfa_initials_buckets_rsp_empty_n, ap_ce)
begin
if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it2) and (nfa_initials_buckets_rsp_empty_n = ap_const_logic_0)))) and (ap_const_logic_1 = ap_ce))) then
ap_ready <= ap_const_logic_1;
else
ap_ready <= ap_const_logic_0;
end if;
end process;
ap_reg_ppiten_pp0_it0 <= ap_start;
-- ap_sig_pprstidle_pp0 assign process. --
ap_sig_pprstidle_pp0_assign_proc : process(ap_start, ap_reg_ppiten_pp0_it0, ap_reg_ppiten_pp0_it1, ap_reg_ppiten_pp0_it2)
begin
if (((ap_const_logic_0 = ap_reg_ppiten_pp0_it0) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it1) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it2) and (ap_const_logic_0 = ap_start))) then
ap_sig_pprstidle_pp0 <= ap_const_logic_1;
else
ap_sig_pprstidle_pp0 <= ap_const_logic_0;
end if;
end process;
initials_buckets_address0 <= tmp_cast_fu_63_p1(4 - 1 downto 0);
-- initials_buckets_ce0 assign process. --
initials_buckets_ce0_assign_proc : process(ap_start, ap_CS_fsm, ap_reg_ppiten_pp0_it0, ap_reg_ppiten_pp0_it2, ap_reg_ppiten_pp0_it3, nfa_initials_buckets_rsp_empty_n, ap_ce)
begin
if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it3) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it2) and (nfa_initials_buckets_rsp_empty_n = ap_const_logic_0)))) and (ap_const_logic_1 = ap_ce))) then
initials_buckets_ce0 <= ap_const_logic_1;
else
initials_buckets_ce0 <= ap_const_logic_0;
end if;
end process;
initials_buckets_d0 <= nfa_initials_buckets_read_reg_72;
-- initials_buckets_we0 assign process. --
initials_buckets_we0_assign_proc : process(ap_start, ap_CS_fsm, ap_reg_ppiten_pp0_it0, ap_reg_ppiten_pp0_it2, ap_reg_ppiten_pp0_it3, nfa_initials_buckets_rsp_empty_n, ap_ce)
begin
if ((((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it3) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it2) and (nfa_initials_buckets_rsp_empty_n = ap_const_logic_0)))) and (ap_const_logic_1 = ap_ce)))) then
initials_buckets_we0 <= ap_const_logic_1;
else
initials_buckets_we0 <= ap_const_logic_0;
end if;
end process;
nfa_initials_buckets_address <= ap_const_lv32_0;
nfa_initials_buckets_dataout <= ap_const_lv64_0;
nfa_initials_buckets_req_din <= ap_const_logic_0;
-- nfa_initials_buckets_req_write assign process. --
nfa_initials_buckets_req_write_assign_proc : process(ap_start, ap_CS_fsm, ap_reg_ppiten_pp0_it0, ap_reg_ppiten_pp0_it2, nfa_initials_buckets_rsp_empty_n, ap_ce)
begin
if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it2) and (nfa_initials_buckets_rsp_empty_n = ap_const_logic_0)))) and (ap_const_logic_1 = ap_ce))) then
nfa_initials_buckets_req_write <= ap_const_logic_1;
else
nfa_initials_buckets_req_write <= ap_const_logic_0;
end if;
end process;
-- nfa_initials_buckets_rsp_read assign process. --
nfa_initials_buckets_rsp_read_assign_proc : process(ap_start, ap_CS_fsm, ap_reg_ppiten_pp0_it0, ap_reg_ppiten_pp0_it2, nfa_initials_buckets_rsp_empty_n, ap_ce)
begin
if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it2) and (nfa_initials_buckets_rsp_empty_n = ap_const_logic_0)))) and (ap_const_logic_1 = ap_ce))) then
nfa_initials_buckets_rsp_read <= ap_const_logic_1;
else
nfa_initials_buckets_rsp_read <= ap_const_logic_0;
end if;
end process;
nfa_initials_buckets_size <= ap_const_lv32_1;
tmp_cast_fu_63_p1 <= std_logic_vector(resize(unsigned(ap_reg_ppstg_tmp_read_reg_67_pp0_it2),64));
end behav;
| lgpl-3.0 | 76ce178f7394c159fe10592b9d628dab | 0.608588 | 2.69254 | false | false | false | false |
wsoltys/AtomFpga | src/Atomic_top_hoglet.vhd | 1 | 15,570 | --------------------------------------------------------------------------------
-- Copyright (c) 2014 David Banks
--
-- based on work by Alan Daly. Copyright(c) 2009. All rights reserved.
--------------------------------------------------------------------------------
-- ____ ____
-- / /\/ /
-- /___/ \ /
-- \ \ \/
-- \ \
-- / / Filename : Atomic_top_hoglet.vhf
-- /___/ /\ Timestamp : 03/04/2014 19:27:00
-- \ \ / \
-- \___\/\___\
--
--Design Name: Atomic_top_hoglet
--Device: spartan3E
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
entity Atomic_top_hoglet is
port (clk_32M00 : in std_logic;
ps2_clk : in std_logic;
ps2_data : in std_logic;
ps2_mouse_clk : inout std_logic;
ps2_mouse_data : inout std_logic;
ERSTn : in std_logic;
red : out std_logic_vector (2 downto 2);
green : out std_logic_vector (2 downto 1);
blue : out std_logic_vector (2 downto 2);
vsync : out std_logic;
hsync : out std_logic;
audiol : out std_logic;
audioR : out std_logic;
RAMOEn : out std_logic;
RAMWRn : out std_logic;
ROMOEn : out std_logic;
ROMWRn : out std_logic;
ExternA : out std_logic_vector (16 downto 0);
ExternD : inout std_logic_vector (7 downto 0);
SDMISO : in std_logic;
SDSS : out std_logic;
SDCLK : out std_logic;
SDMOSI : out std_logic;
RxD : in std_logic;
TxD : out std_logic;
LED1 : out std_logic;
LED2 : out std_logic
);
end Atomic_top_hoglet;
architecture behavioral of Atomic_top_hoglet is
component dcm4
port (
CLKIN_IN : in std_logic;
CLK0_OUT : out std_logic;
CLK0_OUT1 : out std_logic;
CLK2X_OUT : out std_logic
);
end component;
component dcm5
port (
CLKIN_IN : in std_logic;
CLK0_OUT : out std_logic;
CLK0_OUT1 : out std_logic;
CLK2X_OUT : out std_logic
);
end component;
component Atomic_core
generic (
CImplSDDOS : boolean;
CImplGraphicsExt : boolean;
CImplSoftChar : boolean;
CImplSID : boolean;
CImplVGA80x40 : boolean;
CImplHWScrolling : boolean;
CImplMouse : boolean;
CImplUart : boolean;
MainClockSpeed : integer;
DefaultBaud : integer
);
port (
clk_vga : in std_logic;
clk_16M00 : in std_logic;
clk_32M00 : in std_logic;
ps2_clk : in std_logic;
ps2_data : in std_logic;
ps2_mouse_clk : inout std_logic;
ps2_mouse_data : inout std_logic;
ERSTn : in std_logic;
IRSTn : out std_logic;
SDMISO : in std_logic;
red : out std_logic_vector(2 downto 0);
green : out std_logic_vector(2 downto 0);
blue : out std_logic_vector(2 downto 0);
vsync : out std_logic;
hsync : out std_logic;
RamCE : out std_logic;
RomCE : out std_logic;
Phi2 : out std_logic;
ExternWE : out std_logic;
ExternA : out std_logic_vector (16 downto 0);
ExternDin : out std_logic_vector (7 downto 0);
ExternDout: in std_logic_vector (7 downto 0);
audiol : out std_logic;
audioR : out std_logic;
SDSS : out std_logic;
SDCLK : out std_logic;
SDMOSI : out std_logic;
uart_RxD : in std_logic;
uart_TxD : out std_logic;
LED1 : out std_logic;
LED2 : out std_logic
);
end component;
component AtomPL8
port (
clk : in std_logic;
enable : in std_logic;
nRST : in std_logic;
RW : in std_logic;
Addr : in std_logic_vector(2 downto 0);
DataIn : in std_logic_vector(7 downto 0);
nARD : in std_logic;
nAWR : in std_logic;
AVRA0 : in std_logic;
AVRDataIn : in std_logic_vector(7 downto 0);
AVRDataOut : OUT std_logic_vector(7 downto 0);
DataOut : OUT std_logic_vector(7 downto 0);
AVRINTOut : OUT std_logic;
AtomIORDOut : out std_logic;
AtomIOWROut : out std_logic
);
end component;
component AVR8
port(
clk16M : in std_logic;
nrst : in std_logic;
portain : in std_logic_vector(7 downto 0);
portaout : out std_logic_vector(7 downto 0);
portbin : in std_logic_vector(7 downto 0);
portbout : out std_logic_vector(7 downto 0);
portc : inout std_logic_vector(7 downto 0);
portdin : in std_logic_vector(7 downto 0);
portdout : out std_logic_vector(7 downto 0);
porte : inout std_logic_vector(7 downto 0);
portf : inout std_logic_vector(7 downto 0);
spi_mosio : out std_logic;
spi_scko : out std_logic;
spi_cs_n : out std_logic;
spi_misoi : in std_logic;
rxd : in std_logic;
txd : out std_logic
);
end component;
signal clk_vga : std_logic;
signal clk_16M00 : std_logic;
signal IRSTn : std_logic;
signal Phi2 : std_logic;
signal RamCE : std_logic;
signal RomCE : std_logic;
signal ExternWE : std_logic;
signal ExternDin : std_logic_vector (7 downto 0);
signal ExternDout: std_logic_vector (7 downto 0);
signal nARD : std_logic;
signal nAWR : std_logic;
signal AVRA0 : std_logic;
signal AVRInt : std_logic;
signal AVRDataIn : std_logic_vector (7 downto 0);
signal AVRDataOut : std_logic_vector (7 downto 0);
signal Addr : std_logic_vector (16 downto 0);
signal PL8Data : std_logic_vector (7 downto 0);
signal PL8Enable: std_logic;
signal cpuclken : std_logic;
signal BFFE_Enable : std_logic;
signal BFFF_Enable : std_logic;
signal RomJumpers : std_logic_vector (7 downto 0);
signal RomLatch : std_logic_vector (7 downto 0);
signal ExtRAMEN1 : std_logic; -- SwitchLatch[0] on Phill's board
signal ExtRAMEN2 : std_logic; -- SwitchLatch[1] on Phill's board
signal DskRAMEN : std_logic; -- SwitchLatch[1] on Phill's board, not currently used in AtomFPGA
signal DskROMEN : std_logic; -- SwitchLatch[2] on Phill's board
signal BeebMode : std_logic; -- SwitchLatch[3] on Phill's board
signal Addr6000RAM : std_logic;
signal Addr6000ROM : std_logic;
signal Addr7000RAM : std_logic;
signal Addr7000ROM : std_logic;
signal AddrA000RAM : std_logic;
signal AddrA000ROM : std_logic;
signal avr_TxR : std_logic;
signal uart_RxD : std_logic;
signal uart_TxD : std_logic;
begin
inst_dcm4 : dcm4 port map(
CLKIN_IN => clk_32M00,
CLK0_OUT => clk_vga,
CLK0_OUT1 => open,
CLK2X_OUT => open);
inst_dcm5 : dcm5 port map(
CLKIN_IN => clk_32M00,
CLK0_OUT => clk_16M00,
CLK0_OUT1 => open,
CLK2X_OUT => open);
inst_Atomic_core : Atomic_core
generic map (
CImplSDDOS => false,
CImplGraphicsExt => true,
CImplSoftChar => true,
CImplSID => true,
CImplVGA80x40 => true,
CImplHWScrolling => true,
CImplMouse => true,
CImplUart => true,
MainClockSpeed => 16000000,
DefaultBaud => 115200
)
port map(
clk_vga => clk_vga,
clk_16M00 => clk_16M00,
clk_32M00 => clk_32M00,
ps2_clk => ps2_clk,
ps2_data => ps2_data,
ps2_mouse_clk => ps2_mouse_clk,
ps2_mouse_data => ps2_mouse_data,
ERSTn => ERSTn,
IRSTn => IRSTn,
red(2) => red(2),
red(1 downto 0) => open,
green(2 downto 1) => green(2 downto 1),
green(0) => open,
blue(2) => blue(2),
blue(1 downto 0) => open,
vsync => vsync,
hsync => hsync,
RamCE => open,
RomCE => open,
Phi2 => Phi2,
ExternWE => ExternWE,
ExternA => Addr,
ExternDin => ExternDin,
ExternDout=> ExternDout,
audiol => audiol,
audioR => audioR,
SDMISO => '0',
SDSS => open,
SDCLK => open,
SDMOSI => open,
uart_RxD => uart_RxD,
uart_TxD => uart_TxD,
LED1 => open,
LED2 => open
);
Inst_AVR8: AVR8 PORT MAP(
clk16M => clk_16M00,
nrst => IRSTn,
portain => AVRDataOut,
portaout => AVRDataIn,
portbin(0) => '0',
portbin(1) => '0',
portbin(2) => '0',
portbin(3) => '0',
portbin(4) => AVRInt,
portbin(5) => '0',
portbin(6) => '0',
portbin(7) => '0',
portbout(0) => nARD,
portbout(1) => nAWR,
portbout(2) => open,
portbout(3) => AVRA0,
portbout(4) => open,
portbout(5) => open,
portbout(6) => LED1,
portbout(7) => LED2,
portdin => (others => '0'),
portdout(0) => open,
portdout(1) => open,
portdout(2) => open,
portdout(3) => open,
portdout(4) => SDSS,
portdout(5) => open,
portdout(6) => open,
portdout(7) => open,
spi_mosio => SDMOSI,
spi_scko => SDCLK,
spi_misoi => SDMISO,
rxd => RxD,
txd => avr_TxR
);
Inst_AtomPL8: AtomPL8 port map(
clk => clk_16M00,
enable => PL8Enable,
nRST => IRSTn,
RW => not ExternWE,
Addr => Addr(2 downto 0),
DataIn => ExternDin,
DataOut => PL8Data,
AVRDataIn => AVRDataIn,
AVRDataOut => AVRDataOut,
nARD => nARD,
nAWR => nAWR,
AVRA0 => AVRA0,
AVRINTOut => AVRInt,
AtomIORDOut => open,
AtomIOWROut => open
);
Addr6000ROM <= '1' when Addr(15 downto 12) = "0110" and (BeebMode = '1' and (RomLatch(4 downto 0) /= "00000" or ExtRAMEN1 = '0'))
else '0';
Addr6000RAM <= '1' when Addr(15 downto 12) = "0110" and (BeebMode = '0' or (RomLatch(4 downto 0) = "00000" and ExtRAMEN1 = '1'))
else '0';
Addr7000ROM <= '1' when Addr(15 downto 12) = "0111" and (BeebMode = '1' and ExtRAMEN2 = '0')
else '0';
Addr7000RAM <= '1' when Addr(15 downto 12) = "0111" and (BeebMode = '0' or ExtRAMEN2 = '1')
else '0';
AddrA000ROM <= '1' when Addr(15 downto 12) = "1010" and (BeebMode = '1' or RomLatch(4 downto 0) /= "00000" or ExtRAMEN1 = '0')
else '0';
AddrA000RAM <= '1' when Addr(15 downto 12) = "1010" and (BeebMode = '0' and RomLatch(4 downto 0) = "00000" and ExtRAMEN1 = '1')
else '0';
RamCE <= '1' when Addr(15 downto 12) < "0110" or Addr6000RAM = '1' or Addr7000RAM = '1' or AddrA000RAM = '1'
else '0';
RomCE <= '1' when Addr(15 downto 14) = "11" or Addr6000ROM = '1' or Addr7000ROM = '1' or AddrA000ROM = '1'
else '0';
RAMWRn <= not (ExternWE and RamCE and Phi2);
RAMOEn <= not ((not ExternWE) and RamCE);
ROMWRn <= not (ExternWE and RomCE and Phi2);
ROMOEn <= not ((not ExternWE) and RomCE);
ExternD <= ExternDin when ExternWE = '1' else "ZZZZZZZZ";
PL8Enable <= '1' when Addr(15 downto 8) = "10110100" else '0';
ExternDout <= PL8Data when PL8Enable = '1' else
RomJumpers when BFFE_Enable = '1' else
RomLatch when BFFF_Enable = '1' else
ExternD;
-------------------------------------------------
-- External address decoding
-------------------------------------------------
ExternA <=
-- 0x6000 comes from ROM address 0x08000-0x0F000 in Beeb Mode (Ext ROM 1)
( "01" & RomLatch(2 downto 0) & Addr(11 downto 0)) when Addr6000ROM = '1' else
-- 0x6000 is 4K remappable RAM bank mapped to 0x6000
(ExtRAMEN1 & Addr(15 downto 0)) when Addr6000RAM = '1' else
-- 0x7000 comes from ROM address 0x19000 in Beeb Mode (Ext ROM 2)
( "11001" & Addr(11 downto 0)) when Addr7000ROM = '1' else
-- 0x7000 is 4K remappable RAM bank mapped to 0x7000
(ExtRAMEN2 & Addr(15 downto 0)) when Addr7000RAM = '1' else
-- 0xA000 remappable RAM bank at 0x7000 re-mapped to 0xA000
( "00111" & Addr(11 downto 0)) when AddrA000RAM = '1' else
-- 0xA000 is bank switched by ROM Latch in Atom Mode
-- 5 bits of RomLatch are used here, to allow any of the 32 pages of FLASH to A000 for in system programming
( RomLatch(4 downto 0) & Addr(11 downto 0)) when AddrA000ROM = '1' and BeebMode = '0' else
-- 0xA000 comes from ROM address 0x0A000 in Beeb Mode
( "11010" & Addr(11 downto 0)) when AddrA000ROM = '1' and BeebMode = '1' else
-- 0xC000-0xFFFF comes from ROM address 0x1C000-0x1FFFF in Beeb Mode
( "1" & Addr(15 downto 0)) when Addr(15 downto 14) = "11" and BeebMode = '1' else
-- 0xC000-0xFFFF comes from ROM address 0x10000-0x17FFF in Atom Mode (2x 16K banks selected SwitchLatch[2])
( "10" & DskROMEN & Addr(13 downto 0)) when Addr(15 downto 14) = "11" and BeebMode = '0' else
-- RAM
Addr;
-------------------------------------------------
-- ROM Latch and Jumpers
-------------------------------------------------
BFFE_Enable <= '1' when Addr(15 downto 0) = "1011111111111110" else '0';
BFFF_Enable <= '1' when Addr(15 downto 0) = "1011111111111111" else '0';
ExtRAMEN1 <= RomJumpers(0);
ExtRAMEN2 <= RomJumpers(1);
DskRAMEN <= RomJumpers(1); -- currently unused
DskROMEN <= RomJumpers(2);
BeebMode <= RomJumpers(3);
RomLatchProcess : process (ERSTn, IRSTn, clk_16M00)
begin
if ERSTn = '0' then
RomJumpers <= "00000000";
RomLatch <= "00000000";
elsif rising_edge(clk_16M00) then
if BFFE_Enable = '1' and ExternWE = '1' then
RomJumpers <= ExternDin;
end if;
if BFFF_Enable = '1' and ExternWE = '1' then
RomLatch <= ExternDin;
end if;
end if;
end process;
uart_RxD <= RxD;
-- Idle state is high, logically OR the active low signals
TxD <= uart_TxD and avr_TxR;
end behavioral;
| apache-2.0 | d7bce2c6a26e773a8bc59a287b7e8180 | 0.494926 | 3.584254 | false | false | false | false |
wsoltys/AtomFpga | src/AtomGodilVideo/src/AtomGodilVideo.vhd | 1 | 39,701 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date:
-- Design Name:
-- Module Name:
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.all;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
use IEEE.NUMERIC_STD.all;
use IEEE.STD_LOGIC_UNSIGNED.all;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity AtomGodilVideo is
generic (
CImplGraphicsExt : boolean;
CImplSoftChar : boolean;
CImplSID : boolean;
CImplVGA80x40 : boolean;
CImplHWScrolling : boolean;
CImplMouse : boolean;
CImplUart : boolean;
MainClockSpeed : integer;
DefaultBaud : integer
);
port (
-- clock_vga is a full speed VGA clock (25MHz ish)
clock_vga : in std_logic;
-- clock_main is the main clock
clock_main : in std_logic;
-- A fixed 32MHz clock for the SID
clock_sid_32MHz : in std_logic;
-- As fast a clock as possible for the SID DAC
clock_sid_dac : in std_logic;
-- Reset signal (active high)
reset : in std_logic;
-- Reset signal to 6847 (active high), not currently used
reset_vid : in std_logic;
-- Main Address / Data Bus signals
din : in std_logic_vector (7 downto 0);
dout : out std_logic_vector (7 downto 0);
addr : in std_logic_vector (12 downto 0);
-- 6847 signals
CSS : in std_logic;
AG : in std_logic;
GM : in std_logic_vector (2 downto 0);
nFS : out std_logic;
-- RAM signals
ram_we : in std_logic;
-- SID signals
reg_cs : in std_logic;
reg_we : in std_logic;
-- SID signals
sid_cs : in std_logic;
sid_we : in std_logic;
sid_audio : out std_logic;
-- PS/2 Mouse signals
PS2_CLK : inout std_logic;
PS2_DATA : inout std_logic;
-- UART signals
uart_cs : in std_logic;
uart_we : in std_logic;
uart_RxD : in std_logic;
uart_TxD : out std_logic;
uart_escape : out std_logic;
uart_break : out std_logic;
-- VGA Signals
final_red : out std_logic;
final_green1 : out std_logic;
final_green0 : out std_logic;
final_blue : out std_logic;
final_vsync : out std_logic;
final_hsync : out std_logic
);
end AtomGodilVideo;
architecture BEHAVIORAL of AtomGodilVideo is
constant MAJOR_VERSION : std_logic_vector(3 downto 0) := "0001";
constant MINOR_VERSION : std_logic_vector(3 downto 0) := "0001";
-- Set this to 0 if you want dark green/dark orange background on text
-- Set this to 1 if you want black background on text (authentic Atom)
constant BLACK_BACKGND : std_logic := '1';
signal clock_vga_en : std_logic;
-- Internal 1MHz clocks for SID
signal div32 : std_logic_vector (4 downto 0);
signal clock_sid_1MHz : std_logic;
-- VGA colour signals out of mc6847, only top 2 bits are used
signal vga_red : std_logic_vector (7 downto 0);
signal vga_green : std_logic_vector (7 downto 0);
signal vga_blue : std_logic_vector (7 downto 0);
signal vga_vsync : std_logic;
signal vga_hsync : std_logic;
-- 8Kx8 Dual port video RAM signals
-- Port A connects to Atom and is read/write
-- Port B connects to MC6847 and is read only
signal douta : std_logic_vector (7 downto 0);
signal addrb : std_logic_vector (12 downto 0);
signal doutb : std_logic_vector (7 downto 0);
-- Masked (by nRST) version of the mode control signals
signal mask : std_logic;
signal gm_masked : std_logic_vector (2 downto 0);
signal ag_masked : std_logic;
signal css_masked : std_logic;
-- SID signals
signal sid_do : std_logic_vector (7 downto 0);
-- Atom extension register signals
signal reg_addr : std_logic_vector (4 downto 0);
signal reg_do : std_logic_vector (7 downto 0);
signal extensions : std_logic_vector (7 downto 0);
signal char_addr : std_logic_vector (7 downto 0);
signal ocrx : std_logic_vector (7 downto 0);
signal ocry : std_logic_vector (7 downto 0);
signal octl : std_logic_vector (7 downto 0);
signal octl2 : std_logic_vector (7 downto 0);
signal char_we : std_logic;
signal char_reg : std_logic_vector (7 downto 0);
signal mc6847_an_s : std_logic;
signal mc6847_intn_ext : std_logic;
signal mc6847_inv : std_logic;
signal mc6847_css : std_logic;
signal mc6847_d_final : std_logic_vector (7 downto 0);
signal mc6847_d : std_logic_vector (7 downto 0);
signal mc6847_d_with_pointer : std_logic_vector (7 downto 0);
signal mc6847_char_a : std_logic_vector (10 downto 0);
signal mc6847_addrb : std_logic_vector (12 downto 0);
signal mc6847_addrb_hw : std_logic_vector (12 downto 0);
signal char_d_o : std_logic_vector (7 downto 0);
signal pointer_nr : std_logic_vector (7 downto 0);
signal pointer_nr_rd : std_logic_vector (7 downto 0);
signal pointer_x : std_logic_vector (7 downto 0);
signal pointer_y : std_logic_vector (7 downto 0);
signal pointer_y_inv : std_logic_vector (7 downto 0);
signal pointer_left : std_logic;
signal pointer_middle : std_logic;
signal pointer_right : std_logic;
signal hwscrollmode : std_logic;
signal scroll_left : std_logic_vector (7 downto 0);
signal scroll_right : std_logic_vector (7 downto 0);
signal scroll_h : std_logic_vector (7 downto 0);
signal scroll_top : std_logic_vector (7 downto 0);
signal scroll_bottom : std_logic_vector (7 downto 0);
signal scroll_v : std_logic_vector (7 downto 0);
signal width32 : std_logic;
signal lines : std_logic_vector (7 downto 0);
signal vga80x40mode : std_logic;
signal final_char_a : std_logic_vector (10 downto 0);
signal vga80_R : std_logic;
signal vga80_G : std_logic;
signal vga80_B : std_logic;
signal vga80_vsync : std_logic;
signal vga80_hsync : std_logic;
signal vga80_invert : std_logic;
signal vga80_char_a : std_logic_vector (10 downto 0);
signal vga80_char_d : std_logic_vector (7 downto 0);
signal vga80_addrb : std_logic_vector (12 downto 0);
signal vga80_addrb_hw: std_logic_vector (12 downto 0);
signal uart_do : std_logic_vector (7 downto 0);
Component vga80x40
port(
reset : IN std_logic;
clk25MHz : IN std_logic;
TEXT_D : IN std_logic_vector(7 downto 0);
FONT_D : IN std_logic_vector(7 downto 0);
ocrx : IN std_logic_vector(7 downto 0);
ocry : IN std_logic_vector(7 downto 0);
octl : IN std_logic_vector(7 downto 0);
octl2 : IN std_logic_vector(7 downto 0);
TEXT_A : OUT std_logic_vector(12 downto 0);
FONT_A : OUT std_logic_vector(11 downto 0);
R : OUT std_logic;
G : OUT std_logic;
B : OUT std_logic;
hsync : OUT std_logic;
vsync : OUT std_logic
);
end component;
component mc6847
port(
clk : in std_logic;
clk_ena : in std_logic;
reset : in std_logic;
dd : in std_logic_vector(7 downto 0);
an_g : in std_logic;
an_s : in std_logic;
intn_ext : in std_logic;
gm : in std_logic_vector(2 downto 0);
css : in std_logic;
inv : in std_logic;
artifact_en : in std_logic;
artifact_set : in std_logic;
artifact_phase : in std_logic;
da0 : out std_logic;
videoaddr : out std_logic_vector(12 downto 0);
hs_n : out std_logic;
fs_n : out std_logic;
red : out std_logic_vector(7 downto 0);
green : out std_logic_vector(7 downto 0);
blue : out std_logic_vector(7 downto 0);
hsync : out std_logic;
vsync : out std_logic;
hblank : out std_logic;
vblank : out std_logic;
cvbs : out std_logic_vector(7 downto 0);
black_backgnd : in std_logic;
char_a : out std_logic_vector(10 downto 0);
char_d_o : in std_logic_vector(7 downto 0)
);
end component;
component VideoRam
port (
clka : in std_logic;
wea : in std_logic;
addra : in std_logic_vector(12 downto 0);
dina : in std_logic_vector(7 downto 0);
douta : out std_logic_vector(7 downto 0);
clkb : in std_logic;
web : in std_logic;
addrb : in std_logic_vector(12 downto 0);
dinb : in std_logic_vector(7 downto 0);
doutb : out std_logic_vector(7 downto 0)
);
end component;
component sid6581
port(
clk_1MHz : in std_logic;
clk32 : in std_logic;
clk_DAC : in std_logic;
reset : in std_logic;
cs : in std_logic;
we : in std_logic;
addr : in std_logic_vector(4 downto 0);
di : in std_logic_vector(7 downto 0);
pot_x : in std_logic;
pot_y : in std_logic;
do : out std_logic_vector(7 downto 0);
audio_out : out std_logic;
audio_data : out std_logic_vector(17 downto 0)
);
end component;
component MouseRefComp
generic (
MainClockSpeed : integer
);
port(
CLK : IN std_logic;
RESOLUTION : IN std_logic;
RST : IN std_logic;
SWITCH : IN std_logic;
PS2_CLK : INOUT std_logic;
PS2_DATA : INOUT std_logic;
LEFT : OUT std_logic;
MIDDLE : OUT std_logic;
NEW_EVENT : OUT std_logic;
RIGHT : OUT std_logic;
XPOS : OUT std_logic_vector(9 downto 0);
YPOS : OUT std_logic_vector(9 downto 0);
ZPOS : OUT std_logic_vector(3 downto 0)
);
end component;
component Pointer is
port (
CLK : in std_logic;
PO : in std_logic;
PS : in std_logic_vector (4 downto 0);
X : in std_logic_vector (7 downto 0);
Y : in std_logic_vector (7 downto 0);
ADDR : in std_logic_vector (12 downto 0);
DIN : in std_logic_vector (7 downto 0);
DOUT : out std_logic_vector (7 downto 0)
);
end component;
component miniuart
generic (
MainClockSpeed : integer;
DefaultBaud : integer
);
port(
wb_clk_i : in std_logic;
wb_rst_i : in std_logic;
wb_adr_i : in std_logic_vector(1 downto 0);
wb_dat_i : in std_logic_vector(7 downto 0);
wb_we_i : in std_logic;
wb_stb_i : in std_logic;
br_clk_i : in std_logic;
rxd_pad_i : in std_logic;
wb_dat_o : out std_logic_vector(7 downto 0);
wb_ack_o : out std_logic;
inttx_o : out std_logic;
intrx_o : out std_logic;
txd_pad_o : out std_logic;
esc_o : out std_logic;
break_o : out std_logic
);
end component;
function modulo5 (x : std_logic_vector(7 downto 0))
return std_logic_vector is
variable tmp1 : std_logic_vector(4 downto 0);
variable tmp2 : std_logic_vector(3 downto 0);
begin
-- uses some tricks from here:
-- http://homepage.cs.uiowa.edu/~jones/bcd/mod.shtml
-- calculate modulo 15
tmp1 := ('0' & X(7 downto 4)) + ('0' & X(3 downto 0));
if (tmp1 = 30) then
tmp1 := "00000";
elsif (tmp1 >= 15) then
tmp1 := tmp1 - 15;
end if;
-- calculate modulo 5
tmp2 := tmp1(3 downto 0);
if (tmp2 >= 10) then
tmp2 := tmp2 - 5;
end if;
if (tmp2 >= 5) then
tmp2 := tmp2 - 5;
end if;
return tmp2(2 downto 0);
end modulo5;
begin
-----------------------------------------------------------------------------
-- Core
-----------------------------------------------------------------------------
-- Motorola MC6847
-- Original version: https://svn.pacedev.net/repos/pace/sw/src/component/video/mc6847.vhd
-- Updated by AlanD for his Atom FPGA: http://stardot.org.uk/forums/viewtopic.php?f=3&t=6313
-- A further few bugs fixed by myself
Inst_mc6847 : mc6847
port map (
clk => clock_vga,
clk_ena => clock_vga_en,
reset => reset_vid,
da0 => open,
videoaddr => mc6847_addrb,
dd => mc6847_d_final,
hs_n => open,
fs_n => nFS,
an_g => ag_masked,
an_s => mc6847_an_s,
intn_ext => mc6847_intn_ext,
gm => gm_masked,
css => mc6847_css,
inv => mc6847_inv,
red => vga_red,
green => vga_green,
blue => vga_blue,
hsync => vga_hsync,
vsync => vga_vsync,
artifact_en => '0',
artifact_set => '0',
artifact_phase => '0',
hblank => open,
vblank => open,
cvbs => open,
black_backgnd => BLACK_BACKGND,
char_a => mc6847_char_a,
char_d_o => char_d_o
);
mc6847_d_final <= mc6847_d_with_pointer when CImplMouse else mc6847_d;
-- 8Kx8 Dual port video RAM
-- Port A connects to Atom and is read/write
-- Port B connects to MC6847 and is read only
Inst_VideoRam : VideoRam
port map (
clka => clock_main,
wea => ram_we,
addra => addr,
dina => din,
douta => douta,
clkb => clock_vga,
web => '0',
addrb => addrb,
dinb => (others => '0'),
doutb => doutb
);
hwscrollmode <= extensions(6) when CImplHWScrolling else '0';
addrb <= mc6847_addrb when vga80x40mode = '0' and hwscrollmode = '0' else
mc6847_addrb_hw when vga80x40mode = '0' and hwscrollmode = '1' else
vga80_addrb when hwscrollmode = '0' else
vga80_addrb_hw;
-- VGA Multiplexing between two controllers
vga80x40mode <= extensions(7) when CImplVGA80x40 else '0';
final_red <= vga_red(7) when vga80x40mode = '0' else vga80_R;
final_green1 <= vga_green(7) when vga80x40mode = '0' else vga80_G;
final_green0 <= vga_green(6) when vga80x40mode = '0' else vga80_G;
final_blue <= vga_blue(7) when vga80x40mode = '0' else vga80_B;
final_vsync <= vga_vsync when vga80x40mode = '0' else vga80_vsync;
final_hsync <= vga_hsync when vga80x40mode = '0' else vga80_hsync;
final_char_a <= mc6847_char_a when vga80x40mode = '0' else vga80_char_a;
-- Hold internal reset low for two frames after nRST released
-- This avoids any diaplay glitches
process (clock_vga)
variable state : std_logic_vector(2 downto 0);
begin
if rising_edge(clock_vga) then
if (reset = '1') then
state := "000";
elsif (state = "000" and vga_vsync = '0') then
state := "001";
elsif (state = "001" and vga_vsync = '1') then
state := "010";
elsif (state = "010" and vga_vsync = '0') then
state := "011";
elsif (state = "011" and vga_vsync = '1') then
state := "100";
end if;
mask <= state(2);
end if;
end process;
process (clock_vga)
begin
if rising_edge(clock_vga) then
clock_vga_en <= not clock_vga_en;
end if;
end process;
-- During reset, force the 6847 mode select inputs low
-- (this is necessary to stop the mode changing during reset, as the GODIL has 1.5K pullups)
gm_masked <= GM(2 downto 0) when mask = '1' else (others => '0');
ag_masked <= AG when mask = '1' else '0';
css_masked <= CSS when mask = '1' else '0';
reg_addr <= addr(4 downto 0);
reg_do <= extensions when reg_addr = "00000" and (CImplGraphicsExt or CImplVGA80x40 or CImplHWScrolling) else
char_addr when reg_addr = "00001" and CImplSoftChar else
ocrx when reg_addr = "00010" and CImplVGA80x40 else
ocry when reg_addr = "00011" and CImplVGA80x40 else
octl when reg_addr = "00100" and CImplVGA80x40 else
octl2 when reg_addr = "00101" and CImplVGA80x40 else
scroll_h when reg_addr = "00110" and CImplHWScrolling else
scroll_v when reg_addr = "00111" and CImplHWScrolling else
pointer_x when reg_addr = "01000" and CImplMouse else
pointer_y_inv when reg_addr = "01001" and CImplMouse else
pointer_nr_rd when reg_addr = "01010" and CImplMouse else
scroll_left when reg_addr = "01011" and CImplHWScrolling else
scroll_right when reg_addr = "01100" and CImplHWScrolling else
scroll_top when reg_addr = "01101" and CImplHWScrolling else
scroll_bottom when reg_addr = "01110" and CImplHWScrolling else
MAJOR_VERSION & MINOR_VERSION when reg_addr = "01111" else
char_reg when CImplSoftChar else
x"f1";
dout <= sid_do when sid_cs = '1' and CimplSID else
uart_do when uart_cs = '1' and CimplUart else
reg_do when reg_cs = '1' else
douta;
-----------------------------------------------------------------------------
-- Optional Soft Character Set
-----------------------------------------------------------------------------
Optional_SoftChar: if CImplSoftChar generate
-- A register to control extra 6847 features
process (clock_main)
begin
if rising_edge(clock_main) then
if (reset = '1') then
char_addr <= (others => '0');
elsif (reg_cs = '1' and reg_we = '1') then
case reg_addr is
-- char_addr register
when "00001" =>
char_addr <= din;
when others =>
end case;
end if;
end if;
end process;
char_we <= '1' when reg_cs = '1' and reg_we = '1' and char_addr(7) = '1' and reg_addr(4) = '1' else '0';
---- ram for char generator
charrom_inst : entity work.CharRam
port map(
clka => clock_main,
wea => char_we,
addra(10 downto 4) => char_addr(6 downto 0),
addra(3 downto 0) => addr(3 downto 0),
dina => din,
douta => char_reg,
clkb => clock_vga,
web => '0',
addrb => final_char_a,
dinb => (others => '0'),
doutb => char_d_o
);
end generate;
Optional_Not_SoftChar: if not CImplSoftChar generate
---- ram for char generator
charrom_inst : entity work.CharRom
port map(
CLK => clock_vga,
ADDR => final_char_a,
DATA => char_d_o
);
end generate;
-----------------------------------------------------------------------------
-- Graphics Extension Register
-- shared by several optional functions
-----------------------------------------------------------------------------
Optional_GraphicsExtReg: if CImplGraphicsExt or CImplVGA80x40 or CImplHWScrolling generate
-- A register to control extra 6847 features
process (clock_main)
begin
if rising_edge(clock_main) then
if (reset = '1') then
extensions <= (others => '0');
elsif (reg_cs = '1' and reg_we = '1') then
case reg_addr is
-- extensions register
when "00000" =>
extensions <= din;
when others =>
end case;
end if;
end if;
end process;
end generate;
-----------------------------------------------------------------------------
-- Optional Graphics Modes
-----------------------------------------------------------------------------
Optional_GraphicsExt: if CImplGraphicsExt generate
-- Adjust the inputs to the 6847 based on the extensions register
process (extensions, doutb, css_masked, ag_masked)
begin
case extensions(2 downto 0) is
-- Text plus 8 Colour Semigraphics 4
when "001" =>
mc6847_an_s <= doutb(6);
mc6847_intn_ext <= '0';
mc6847_inv <= doutb(7);
-- Replace the 64-127 and 192-255 blocks with Semigraphics 4
-- Only tweak the data bus when actually displaying semigraphics
if (ag_masked = '0' and doutb(6) = '1') then
mc6847_d <= '0' & doutb(7) & doutb(5 downto 0);
else
mc6847_d <= doutb;
end if;
mc6847_css <= css_masked;
-- 2 Colour Text Only
when "010" =>
mc6847_an_s <= '0';
mc6847_intn_ext <= '0';
mc6847_inv <= doutb(7);
if (ag_masked = '0' and doutb(6) = '1') then
mc6847_d <= "00" & doutb(5 downto 0);
else
mc6847_d <= doutb;
end if;
mc6847_css <= doutb(6) xor css_masked;
-- 4 Colour Semigraphics 6 Only
when "011" =>
mc6847_an_s <= '1';
mc6847_intn_ext <= '1';
mc6847_inv <= doutb(7);
mc6847_d <= doutb;
mc6847_css <= css_masked;
-- Extended character set, lower case replaces Red Semigraphics
-- 00-3F - Normal Upper Case
-- 40-7F - Yellow Semigraphics 6
-- 80-BF - Inverse Upper Case
-- C0-FF - Normal Lower Case
when "100" =>
mc6847_an_s <= doutb(6) and not doutb(7);
mc6847_intn_ext <= doutb(6);
mc6847_inv <= not doutb(6) and doutb(7);
mc6847_d <= doutb;
mc6847_css <= css_masked;
-- Extended character set, lower case replaces Red and Yello Semigraphics
-- 00-3F - Normal Upper Case
-- 40-7F - Normal Lower Case
-- 80-BF - Inverse Upper Case
-- C0-FF - Inverse Lower Case
when "101" =>
mc6847_an_s <= '0';
mc6847_intn_ext <= '0';
mc6847_inv <= doutb(7);
mc6847_d <= doutb;
mc6847_css <= css_masked;
-- Extended character set, lower case replaces inverse
-- 00-3F - Normal Upper Case
-- 40-7F - Yellow Semigraphics 6 -- Blue
-- 80-BF - Normal Lower Case
-- C0-FF - Red Semigraphics 6
when "110" =>
mc6847_an_s <= doutb(6);
mc6847_intn_ext <= doutb(6);
mc6847_inv <= '0';
if (ag_masked = '0' and doutb(7 downto 6) = "10") then
mc6847_d <= "01" & doutb(5 downto 0);
else
mc6847_d <= doutb;
end if;
mc6847_css <= css_masked;
-- Just replace inverse upper case (32 chars) with lower case
-- 00-3F - Normal Upper Case
-- 40-7F - Yellow Semigraphics 6
-- 80-BF - Lower Case/Inverse Upper Case
-- C0-FF - Red Semigraphics 6
when "111" =>
mc6847_an_s <= doutb(6);
mc6847_intn_ext <= doutb(6);
mc6847_inv <= doutb(7) and doutb(5);
if (ag_masked = '0' and doutb(7 downto 5) = "100") then
mc6847_d <= "01" & doutb(5 downto 0);
else
mc6847_d <= doutb;
end if;
mc6847_css <= css_masked;
-- Default Atom Behaviour
-- 00-3F - Normal Upper Case
-- 40-7F - Yellow Semigraphics 6
-- 80-BF - Inverse Upper Case
-- C0-FF - Red Semigraphics 6
when others =>
mc6847_an_s <= doutb(6);
mc6847_intn_ext <= doutb(6);
mc6847_inv <= doutb(7);
mc6847_d <= doutb;
mc6847_css <= css_masked;
end case;
end process;
end generate;
Optional_Not_GraphicsExt: if not CImplGraphicsExt generate
mc6847_an_s <= doutb(6);
mc6847_intn_ext <= doutb(6);
mc6847_inv <= doutb(7);
mc6847_d <= doutb;
mc6847_css <= css_masked;
end generate;
-----------------------------------------------------------------------------
-- Optional SID
-----------------------------------------------------------------------------
Optional_SID: if CImplSID generate
Inst_sid6581: sid6581
port map (
clk_1MHz => clock_sid_1MHz,
clk32 => clock_sid_32MHz,
clk_DAC => clock_sid_dac,
reset => reset,
cs => sid_cs,
we => sid_we,
addr => reg_addr,
di => din,
do => sid_do,
pot_x => '0',
pot_y => '0',
audio_out => sid_audio,
audio_data => open
);
-- Clock_Sid_1MHz is derived by dividing down thw 32MHz clock
process (clock_sid_32MHz)
begin
if rising_edge(clock_sid_32MHz) then
div32 <= div32 + 1;
end if;
end process;
clock_sid_1MHz <= div32(4);
end generate;
-----------------------------------------------------------------------------
-- Optional VGA80x40 Mode
-----------------------------------------------------------------------------
Optional_VGA80x40: if CImplVGA80x40 generate
-- A register to control extra 6847 features
process (clock_main)
begin
if rising_edge(clock_main) then
if (reset = '1') then
ocrx <= (others => '0');
ocry <= (others => '0');
-- Default to Green Foreground
octl <= "10000010";
-- Default to Black Background
octl2 <= "00000000";
elsif (reg_cs = '1' and reg_we = '1') then
case reg_addr is
when "00010" =>
ocrx <= din;
when "00011" =>
ocry <= din;
when "00100" =>
octl <= din;
when "00101" =>
octl2 <= din;
when others =>
end case;
end if;
end if;
end process;
Inst_vga80x40: vga80x40 PORT MAP(
reset => reset_vid,
clk25MHz => clock_vga,
TEXT_A => vga80_addrb,
TEXT_D => mc6847_d,
FONT_A(10 downto 0) => vga80_char_a,
FONT_A(11) => vga80_invert,
FONT_D => vga80_char_d,
ocrx => ocrx,
ocry => ocry,
octl => octl,
octl2 => octl2,
R => vga80_R,
G => vga80_G,
B => vga80_B,
hsync => vga80_hsync,
vsync => vga80_vsync
);
vga80_char_d <= char_d_o when vga80_invert='0' else char_d_o xor "11111111";
end generate;
-----------------------------------------------------------------------------
-- Optional HW Scrolling of Atom Modes
-----------------------------------------------------------------------------
Optional_HWScrolling_Atom: if CImplHWScrolling generate
-- A register to control extra 6847 features
process (clock_main)
begin
if rising_edge(clock_main) then
if (reset = '1') then
scroll_h <= (others => '0');
scroll_left <= (others => '0');
scroll_right <= (others => '0');
scroll_v <= (others => '0');
scroll_top <= (others => '0');
scroll_bottom <= (others => '0');
elsif (reg_cs = '1' and reg_we = '1') then
case reg_addr is
when "00110" =>
scroll_h <= din;
when "00111" =>
scroll_v <= din;
when "01011" =>
scroll_left <= din;
when "01100" =>
scroll_right <= din;
when "01101" =>
scroll_top <= din;
when "01110" =>
scroll_bottom <= din;
when others =>
end case;
end if;
end if;
end process;
-- 32 bytes wide in Modes 0, 2a, 3a, 4a, 4
-- 16 bytes wide in Modes 1a, 1, 2, 3
width32 <= '1' when ag_masked = '0' or
gm_masked = "010" or gm_masked = "100" or
gm_masked = "110" or gm_masked = "111" else '0';
lines <= "00010000" when ag_masked = '0' else
"01000000" when gm_masked = "000" or gm_masked = "001" or gm_masked = "010" else
"01100000" when gm_masked = "011" or gm_masked = "100" else
"11000000";
-- Hardware Scrolling of atom modes
-- mc6847_addrb -> mc6847_addrb_hw
process (lines, width32, scroll_left, scroll_right, scroll_h, scroll_top, scroll_bottom, scroll_v, mc6847_addrb)
variable x : std_logic_vector(7 downto 0);
variable y : std_logic_vector(8 downto 0);
variable scroll_h_min : std_logic_vector(7 downto 0);
variable scroll_h_max : std_logic_vector(7 downto 0);
variable scroll_v_min : std_logic_vector(7 downto 0);
variable scroll_v_max : std_logic_vector(7 downto 0);
begin
scroll_h_min := scroll_left;
scroll_v_min := scroll_top;
scroll_v_max := lines - scroll_bottom;
if (width32 = '0') then
x := "0000" & mc6847_addrb(3 downto 0);
y := "0" & mc6847_addrb(11 downto 4);
scroll_h_max := 16 - scroll_right;
else
x := "000" & mc6847_addrb(4 downto 0);
y := "0" & mc6847_addrb(12 downto 5);
scroll_h_max := 32 - scroll_right;
end if;
if (x >= scroll_h_min and x < scroll_h_max) and (y >= scroll_v_min and y < scroll_v_max) then
x := x + scroll_h;
if (x >= scroll_h_max) then
x := x - (scroll_h_max - scroll_h_min);
end if;
y := y + scroll_v;
if (y >= scroll_v_max) then
y := y - (scroll_v_max - scroll_v_min);
end if;
end if;
if (width32 = '0') then
mc6847_addrb_hw(3 downto 0) <= x(3 downto 0);
mc6847_addrb_hw(12 downto 4) <= y;
else
mc6847_addrb_hw(4 downto 0) <= x(4 downto 0);
mc6847_addrb_hw(12 downto 5) <= y(7 downto 0);
end if;
end process;
end generate;
-----------------------------------------------------------------------------
-- Optional HW Scrolling of VGA80x40 Modes
-----------------------------------------------------------------------------
Optional_HWScrolling_VGA80x40: if CImplHWScrolling and CImplVGA80x40 generate
-- Hardware Scrolling of vga80x40 mode
-- vga80_addrb -> vga80_addrb_hw
process (scroll_h, scroll_v, vga80_addrb)
variable addr1 : std_logic_vector(11 downto 0);
variable addr2 : std_logic_vector(13 downto 0);
variable attr : std_logic;
variable display_start : std_logic_vector(11 downto 0);
variable x1 : std_logic_vector(6 downto 0);
variable x2 : std_logic_vector(7 downto 0);
begin
-- determine if this is an attribute access or not
if (vga80_addrb < 3200) then
attr := '0';
else
attr := '1';
end if;
-- calculate an address in the range 0..3199 regardless of whether char or attr being accessed
if (attr = '0') then
addr1 := vga80_addrb(11 downto 0);
else
addr1 := vga80_addrb(11 downto 0) - 3200;
end if;
-- calculate x from the address modulo 80
x1 := modulo5(addr1(11 downto 4)) & addr1(3 downto 0);
-- calculate the new x after the scroll_h has been added, modulo 80
x2 := ('0' & x1) + scroll_h;
if (x2 >= 80) then
x2 := x2 - 80;
end if;
-- calculate the display start as 80 * scroll_v
display_start := (scroll_v(5 downto 0) & "000000") + ("00" & scroll_v(5 downto 0) & "0000");
-- calculate the new screen start address, extending the precision by one bit
addr2 := ('0' & vga80_addrb) + ("00" & display_start) - ("0000000" & x1) + ("0000000" & x2(6 downto 0));
-- detect wrapping in wrapping in the character and attributevregions
if ((attr = '0' and addr2 >= 3200) or addr2 >= 6400) then
vga80_addrb_hw <= addr2(12 downto 0) - 3200;
else
vga80_addrb_hw <= addr2(12 downto 0);
end if;
end process;
end generate;
-----------------------------------------------------------------------------
-- Optional Mouse
-----------------------------------------------------------------------------
Optional_Mouse: if CImplMouse generate
Inst_Pointer: Pointer PORT MAP (
CLK => clock_vga,
PO => not pointer_nr(7),
PS => pointer_nr(4 downto 0),
X => pointer_x,
Y => pointer_y,
ADDR => mc6847_addrb,
DIN => mc6847_d,
DOUT => mc6847_d_with_pointer
);
Inst_MouseRefComp: MouseRefComp
generic map (
MainClockSpeed => MainClockSpeed
)
PORT MAP (
CLK => clock_main,
RESOLUTION => '1', -- select 256x192 resolution
RST => reset,
SWITCH => '0',
LEFT => pointer_left,
MIDDLE => pointer_middle,
NEW_EVENT => open,
RIGHT => pointer_right,
XPOS(7 downto 0) => pointer_x,
XPOS(9 downto 8) => open,
YPOS(7 downto 0) => pointer_y,
YPOS(9 downto 8) => open,
ZPOS => open,
PS2_CLK => PS2_CLK,
PS2_DATA => PS2_DATA
);
pointer_nr_rd <= pointer_nr(7) & "1111" & not pointer_middle & not pointer_right & not pointer_left;
pointer_y_inv <= pointer_y xor "11111111";
process (clock_main)
begin
if rising_edge(clock_main) then
if (reset = '1') then
pointer_nr <= "10000000";
elsif (reg_cs = '1' and reg_we = '1') then
case reg_addr is
when "01010" =>
pointer_nr <= din;
when others =>
end case;
end if;
end if;
end process;
end generate;
-----------------------------------------------------------------------------
-- Optional Mouse
-----------------------------------------------------------------------------
Optional_Uart: if CImplUart generate
inst_miniuart: miniuart
generic map (
MainClockSpeed => MainClockSpeed,
DefaultBaud => DefaultBaud
)
port map (
wb_clk_i => clock_main,
wb_rst_i => reset,
wb_adr_i => addr(1 downto 0),
wb_dat_i => din,
wb_dat_o => uart_do,
wb_we_i => uart_we,
wb_stb_i => uart_cs,
wb_ack_o => open,
inttx_o => open,
intrx_o => open,
br_clk_i => clock_main,
txd_pad_o => uart_TxD,
rxd_pad_i => uart_RxD,
esc_o => uart_escape,
break_o => uart_break
);
end generate;
Optional_Not_Uart: if not CImplUart generate
uart_TxD <= '1';
uart_escape <= '1';
uart_break <= '1';
end generate;
end BEHAVIORAL;
| apache-2.0 | dbf56099b892794cd6429860a6259515 | 0.458024 | 4.139833 | false | false | false | false |
grwlf/vsim | vhdl_ct/ct00509.vhd | 1 | 2,431 | -- NEED RESULT: ARCH00509: Default initialization for drivers of subtype T is T'Left passed
-------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
-------------------------------------------------------------------------------
--
-- TEST NAME:
--
-- CT00509
--
-- AUTHOR:
--
-- G. Tominovich
--
-- TEST OBJECTIVES:
--
-- 5.2 (4)
--
-- DESIGN UNIT ORDERING:
--
-- E00000(ARCH00509)
-- ENT00509_Test_Bench(ARCH00509_Test_Bench)
--
-- REVISION HISTORY:
--
-- 10-AUG-1987 - initial revision
--
-- NOTES:
--
-- self-checking
--
--
use WORK.STANDARD_TYPES.all ;
architecture ARCH00509 of E00000 is
subtype sml is integer range 1 to 10 ;
type rec is record
f1 : boolean ;
f2 : sml ;
end record ;
type T1 is array ( Integer range <> ) of rec ;
subtype ST1 is T1 ( 1 to 3 ) ;
type rec2 is record
f1 : ST1 ;
f2 : Real ;
end record ;
signal S1 : rec ;
signal S2 : ST1 ;
signal S3 : rec2 ;
signal S4 : boolean ;
signal S5 : integer ;
signal S6 : Real ;
begin
process
begin
test_report ( "ARCH00509" ,
"Default initialization for drivers of subtype T "&
"is T'Left",
(s1.f1 = boolean'Left) and (s1.f2 = 1) and
(s2(1).f1 = boolean'Left) and (s2(1).f2 = 1) and
(s2(2).f1 = boolean'Left) and (s2(2).f2 = 1) and
(s2(3).f1 = boolean'Left) and (s2(3).f2 = 1) and
(s3.f1(1).f1 = boolean'Left) and (s3.f1(1).f2 = 1) and
(s3.f1(2).f1 = boolean'Left) and (s3.f1(2).f2 = 1) and
(s3.f1(3).f1 = boolean'Left) and (s3.f1(3).f2 = 1) and
(s3.f2 = Real'Left) and
(s4 = boolean'Left) and
(s5 = integer'Left) and
(s6 = Real'Left) );
wait ;
end process ;
end ARCH00509 ;
entity ENT00509_Test_Bench is
end ENT00509_Test_Bench ;
architecture ARCH00509_Test_Bench of ENT00509_Test_Bench is
begin
L1:
block
component UUT
end component ;
for CIS1 : UUT use entity WORK.E00000 ( ARCH00509 ) ;
begin
CIS1 : UUT ;
end block L1 ;
end ARCH00509_Test_Bench ;
| gpl-3.0 | c45d6e11973a2db014a52f06818f2102 | 0.477581 | 3.211361 | false | true | false | false |
grwlf/vsim | vhdl_ct/ct00486.vhd | 1 | 6,374 | -- NEED RESULT: ARCH00486: The expression in an attribute specification may be globally static passed
-------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
-------------------------------------------------------------------------------
--
-- TEST NAME:
--
-- CT00486
--
-- AUTHOR:
--
-- G. Tominovich
--
-- TEST OBJECTIVES:
--
-- 5.1 (9)
--
-- DESIGN UNIT ORDERING:
--
-- ENT00486(ARCH00486)
-- ENT00486_Test_Bench(ARCH00486_Test_Bench)
--
-- REVISION HISTORY:
--
-- 07-AUG-1987 - initial revision
--
-- NOTES:
--
-- self-checking
-- automatically generated
--
use WORK.STANDARD_TYPES.all ;
entity ENT00486 is
generic (
g_boolean_1 : in boolean
; g_bit_1 : in bit
; g_severity_level_1 : in severity_level
; g_character_1 : in character
; g_st_enum1_1 : in st_enum1
; g_integer_1 : in integer
; g_st_int1_1 : in st_int1
; g_time_1 : in time
; g_st_phys1_1 : in st_phys1
; g_real_1 : in real
; g_st_real1_1 : in st_real1
; g_st_rec1_1 : in st_rec1
; g_st_rec2_1 : in st_rec2
; g_st_rec3_1 : in st_rec3
; g_st_arr1_1 : in st_arr1
; g_st_arr2_1 : in st_arr2
; g_st_arr3_1 : in st_arr3
);
end ENT00486;
--
--
architecture ARCH00486 of ENT00486 is
signal S : Integer := 0 ;
attribute A_boolean : boolean ;
attribute A_boolean of S : signal is g_boolean_1 ;
--
attribute A_bit : bit ;
attribute A_bit of S : signal is g_bit_1 ;
--
attribute A_severity_level : severity_level ;
attribute A_severity_level of S : signal is g_severity_level_1 ;
--
attribute A_character : character ;
attribute A_character of S : signal is g_character_1 ;
--
attribute A_st_enum1 : st_enum1 ;
attribute A_st_enum1 of S : signal is g_st_enum1_1 ;
--
attribute A_integer : integer ;
attribute A_integer of S : signal is g_integer_1 ;
--
attribute A_st_int1 : st_int1 ;
attribute A_st_int1 of S : signal is g_st_int1_1 ;
--
attribute A_time : time ;
attribute A_time of S : signal is g_time_1 ;
--
attribute A_st_phys1 : st_phys1 ;
attribute A_st_phys1 of S : signal is g_st_phys1_1 ;
--
attribute A_real : real ;
attribute A_real of S : signal is g_real_1 ;
--
attribute A_st_real1 : st_real1 ;
attribute A_st_real1 of S : signal is g_st_real1_1 ;
--
attribute A_st_rec1 : st_rec1 ;
attribute A_st_rec1 of S : signal is g_st_rec1_1 ;
--
attribute A_st_rec2 : st_rec2 ;
attribute A_st_rec2 of S : signal is g_st_rec2_1 ;
--
attribute A_st_rec3 : st_rec3 ;
attribute A_st_rec3 of S : signal is g_st_rec3_1 ;
--
attribute A_st_arr1 : st_arr1 ;
attribute A_st_arr1 of S : signal is g_st_arr1_1 ;
--
attribute A_st_arr2 : st_arr2 ;
attribute A_st_arr2 of S : signal is g_st_arr2_1 ;
--
attribute A_st_arr3 : st_arr3 ;
attribute A_st_arr3 of S : signal is g_st_arr3_1 ;
--
--
begin
process
variable correct : boolean := true;
begin
correct := correct and
(S'A_boolean = c_boolean_1) ;
correct := correct and
(S'A_bit = c_bit_1) ;
correct := correct and
(S'A_severity_level = c_severity_level_1) ;
correct := correct and
(S'A_character = c_character_1) ;
correct := correct and
(S'A_st_enum1 = c_st_enum1_1) ;
correct := correct and
(S'A_integer = c_integer_1) ;
correct := correct and
(S'A_st_int1 = c_st_int1_1) ;
correct := correct and
(S'A_time = c_time_1) ;
correct := correct and
(S'A_st_phys1 = c_st_phys1_1) ;
correct := correct and
(S'A_real = c_real_1) ;
correct := correct and
(S'A_st_real1 = c_st_real1_1) ;
correct := correct and
(S'A_st_rec1 = c_st_rec1_1) ;
correct := correct and
(S'A_st_rec2 = c_st_rec2_1) ;
correct := correct and
(S'A_st_rec3 = c_st_rec3_1) ;
correct := correct and
(S'A_st_arr1 = c_st_arr1_1) ;
correct := correct and
(S'A_st_arr2 = c_st_arr2_1) ;
correct := correct and
(S'A_st_arr3 = c_st_arr3_1) ;
test_report ( "ARCH00486" ,
"The expression in an attribute specification "&
"may be globally static" ,
correct );
wait ;
end process ;
end ARCH00486 ;
--
--
entity ENT00486_Test_Bench is
end ENT00486_Test_Bench ;
--
use WORK.STANDARD_TYPES.all ;
architecture ARCH00486_Test_Bench of ENT00486_Test_Bench is
begin
L1:
block
component UUT
generic (
g_boolean_1 : in boolean
; g_bit_1 : in bit
; g_severity_level_1 : in severity_level
; g_character_1 : in character
; g_st_enum1_1 : in st_enum1
; g_integer_1 : in integer
; g_st_int1_1 : in st_int1
; g_time_1 : in time
; g_st_phys1_1 : in st_phys1
; g_real_1 : in real
; g_st_real1_1 : in st_real1
; g_st_rec1_1 : in st_rec1
; g_st_rec2_1 : in st_rec2
; g_st_rec3_1 : in st_rec3
; g_st_arr1_1 : in st_arr1
; g_st_arr2_1 : in st_arr2
; g_st_arr3_1 : in st_arr3
) ;
end component ;
for CIS1 : UUT use entity WORK.ENT00486 ( ARCH00486 ) ;
begin
CIS1 : UUT
generic map (
c_boolean_1
, c_bit_1
, c_severity_level_1
, c_character_1
, c_st_enum1_1
, c_integer_1
, c_st_int1_1
, c_time_1
, c_st_phys1_1
, c_real_1
, c_st_real1_1
, c_st_rec1_1
, c_st_rec2_1
, c_st_rec3_1
, c_st_arr1_1
, c_st_arr2_1
, c_st_arr3_1
)
;
end block L1 ;
end ARCH00486_Test_Bench ;
| gpl-3.0 | 3f6e115c80e354efda0ef9977ace1254 | 0.492469 | 3.076255 | false | false | false | false |
grwlf/vsim | vhdl_ct/ct00387.vhd | 1 | 70,938 | -- NEED RESULT: ARCH00387.P1: Multi inertial transactions occurred on concurrent signal asg passed
-- NEED RESULT: ARCH00387.P2: Multi inertial transactions occurred on concurrent signal asg passed
-- NEED RESULT: ARCH00387.P3: Multi inertial transactions occurred on concurrent signal asg passed
-- NEED RESULT: ARCH00387.P4: Multi inertial transactions occurred on concurrent signal asg passed
-- NEED RESULT: ARCH00387.P5: Multi inertial transactions occurred on concurrent signal asg passed
-- NEED RESULT: ARCH00387.P6: Multi inertial transactions occurred on concurrent signal asg passed
-- NEED RESULT: ARCH00387.P7: Multi inertial transactions occurred on concurrent signal asg passed
-- NEED RESULT: ARCH00387.P8: Multi inertial transactions occurred on concurrent signal asg passed
-- NEED RESULT: ARCH00387.P9: Multi inertial transactions occurred on concurrent signal asg passed
-- NEED RESULT: ARCH00387.P10: Multi inertial transactions occurred on concurrent signal asg passed
-- NEED RESULT: ARCH00387: One inertial transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00387: One inertial transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00387: One inertial transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00387: One inertial transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00387: One inertial transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00387: One inertial transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00387: One inertial transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00387: One inertial transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00387: One inertial transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00387: One inertial transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00387: Old transactions were removed on a concurrent signal asg passed
-- NEED RESULT: ARCH00387: Old transactions were removed on a concurrent signal asg passed
-- NEED RESULT: ARCH00387: Old transactions were removed on a concurrent signal asg passed
-- NEED RESULT: ARCH00387: Old transactions were removed on a concurrent signal asg passed
-- NEED RESULT: ARCH00387: Old transactions were removed on a concurrent signal asg passed
-- NEED RESULT: ARCH00387: Old transactions were removed on a concurrent signal asg passed
-- NEED RESULT: ARCH00387: Old transactions were removed on a concurrent signal asg passed
-- NEED RESULT: ARCH00387: Old transactions were removed on a concurrent signal asg passed
-- NEED RESULT: ARCH00387: Old transactions were removed on a concurrent signal asg passed
-- NEED RESULT: ARCH00387: Old transactions were removed on a concurrent signal asg passed
-- NEED RESULT: ARCH00387: One inertial transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00387: One inertial transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00387: One inertial transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00387: One inertial transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00387: One inertial transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00387: One inertial transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00387: One inertial transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00387: One inertial transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00387: One inertial transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00387: One inertial transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00387: Inertial semantics check on a concurrent signal asg passed
-- NEED RESULT: ARCH00387: Inertial semantics check on a concurrent signal asg passed
-- NEED RESULT: ARCH00387: Inertial semantics check on a concurrent signal asg passed
-- NEED RESULT: ARCH00387: Inertial semantics check on a concurrent signal asg passed
-- NEED RESULT: ARCH00387: Inertial semantics check on a concurrent signal asg passed
-- NEED RESULT: ARCH00387: Inertial semantics check on a concurrent signal asg passed
-- NEED RESULT: ARCH00387: Inertial semantics check on a concurrent signal asg passed
-- NEED RESULT: ARCH00387: Inertial semantics check on a concurrent signal asg passed
-- NEED RESULT: ARCH00387: Inertial semantics check on a concurrent signal asg passed
-- NEED RESULT: ARCH00387: Inertial semantics check on a concurrent signal asg passed
-- NEED RESULT: P10: Inertial transactions completed entirely passed
-- NEED RESULT: P9: Inertial transactions completed entirely passed
-- NEED RESULT: P8: Inertial transactions completed entirely passed
-- NEED RESULT: P7: Inertial transactions completed entirely passed
-- NEED RESULT: P6: Inertial transactions completed entirely passed
-- NEED RESULT: P5: Inertial transactions completed entirely passed
-- NEED RESULT: P4: Inertial transactions completed entirely passed
-- NEED RESULT: P3: Inertial transactions completed entirely passed
-- NEED RESULT: P2: Inertial transactions completed entirely passed
-- NEED RESULT: P1: Inertial transactions completed entirely passed
-------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
-------------------------------------------------------------------------------
--
-- TEST NAME:
--
-- CT00387
--
-- AUTHOR:
--
-- G. Tominovich
--
-- TEST OBJECTIVES:
--
-- 9.5 (3)
-- 9.5.2 (1)
--
-- DESIGN UNIT ORDERING:
--
-- ENT00387(ARCH00387)
-- ENT00387_Test_Bench(ARCH00387_Test_Bench)
--
-- REVISION HISTORY:
--
-- 30-JUL-1987 - initial revision
--
-- NOTES:
--
-- self-checking
-- automatically generated
--
use WORK.STANDARD_TYPES.all ;
entity ENT00387 is
port (
s_st_boolean_vector : inout st_boolean_vector
; s_st_severity_level_vector : inout st_severity_level_vector
; s_st_string : inout st_string
; s_st_enum1_vector : inout st_enum1_vector
; s_st_integer_vector : inout st_integer_vector
; s_st_time_vector : inout st_time_vector
; s_st_real_vector : inout st_real_vector
; s_st_rec1_vector : inout st_rec1_vector
; s_st_arr2_vector : inout st_arr2_vector
; s_st_arr2 : inout st_arr2
) ;
subtype chk_sig_type is integer range -1 to 100 ;
signal chk_st_boolean_vector : chk_sig_type := -1 ;
signal chk_st_severity_level_vector : chk_sig_type := -1 ;
signal chk_st_string : chk_sig_type := -1 ;
signal chk_st_enum1_vector : chk_sig_type := -1 ;
signal chk_st_integer_vector : chk_sig_type := -1 ;
signal chk_st_time_vector : chk_sig_type := -1 ;
signal chk_st_real_vector : chk_sig_type := -1 ;
signal chk_st_rec1_vector : chk_sig_type := -1 ;
signal chk_st_arr2_vector : chk_sig_type := -1 ;
signal chk_st_arr2 : chk_sig_type := -1 ;
--
end ENT00387 ;
--
--
architecture ARCH00387 of ENT00387 is
subtype chk_time_type is Time ;
signal s_st_boolean_vector_savt : chk_time_type := 0 ns ;
signal s_st_severity_level_vector_savt : chk_time_type := 0 ns ;
signal s_st_string_savt : chk_time_type := 0 ns ;
signal s_st_enum1_vector_savt : chk_time_type := 0 ns ;
signal s_st_integer_vector_savt : chk_time_type := 0 ns ;
signal s_st_time_vector_savt : chk_time_type := 0 ns ;
signal s_st_real_vector_savt : chk_time_type := 0 ns ;
signal s_st_rec1_vector_savt : chk_time_type := 0 ns ;
signal s_st_arr2_vector_savt : chk_time_type := 0 ns ;
signal s_st_arr2_savt : chk_time_type := 0 ns ;
--
subtype chk_cnt_type is Integer ;
signal s_st_boolean_vector_cnt : chk_cnt_type := 0 ;
signal s_st_severity_level_vector_cnt : chk_cnt_type := 0 ;
signal s_st_string_cnt : chk_cnt_type := 0 ;
signal s_st_enum1_vector_cnt : chk_cnt_type := 0 ;
signal s_st_integer_vector_cnt : chk_cnt_type := 0 ;
signal s_st_time_vector_cnt : chk_cnt_type := 0 ;
signal s_st_real_vector_cnt : chk_cnt_type := 0 ;
signal s_st_rec1_vector_cnt : chk_cnt_type := 0 ;
signal s_st_arr2_vector_cnt : chk_cnt_type := 0 ;
signal s_st_arr2_cnt : chk_cnt_type := 0 ;
--
type select_type is range 1 to 6 ;
signal st_boolean_vector_select : select_type := 1 ;
signal st_severity_level_vector_select : select_type := 1 ;
signal st_string_select : select_type := 1 ;
signal st_enum1_vector_select : select_type := 1 ;
signal st_integer_vector_select : select_type := 1 ;
signal st_time_vector_select : select_type := 1 ;
signal st_real_vector_select : select_type := 1 ;
signal st_rec1_vector_select : select_type := 1 ;
signal st_arr2_vector_select : select_type := 1 ;
signal st_arr2_select : select_type := 1 ;
--
begin
CHG1 :
process
variable correct : boolean ;
begin
case s_st_boolean_vector_cnt is
when 0
=> null ;
-- s_st_boolean_vector(lowb) <=
-- c_st_boolean_vector_2(lowb) after 10 ns,
-- c_st_boolean_vector_1(lowb) after 20 ns ;
--
when 1
=> correct :=
s_st_boolean_vector(lowb) =
c_st_boolean_vector_2(lowb) and
(s_st_boolean_vector_savt + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_boolean_vector(lowb) =
c_st_boolean_vector_1(lowb) and
(s_st_boolean_vector_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00387.P1" ,
"Multi inertial transactions occurred on " &
"concurrent signal asg",
correct ) ;
--
st_boolean_vector_select <= transport 2 ;
-- s_st_boolean_vector(lowb) <=
-- c_st_boolean_vector_2(lowb) after 10 ns ,
-- c_st_boolean_vector_1(lowb) after 20 ns ,
-- c_st_boolean_vector_2(lowb) after 30 ns ,
-- c_st_boolean_vector_1(lowb) after 40 ns ;
--
when 3
=> correct :=
s_st_boolean_vector(lowb) =
c_st_boolean_vector_2(lowb) and
(s_st_boolean_vector_savt + 10 ns) = Std.Standard.Now ;
st_boolean_vector_select <= transport 3 ;
-- s_st_boolean_vector(lowb) <=
-- c_st_boolean_vector_1(lowb) after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_boolean_vector(lowb) =
c_st_boolean_vector_1(lowb) and
(s_st_boolean_vector_savt + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00387" ,
"One inertial transaction occurred on a " &
"concurrent signal asg",
correct ) ;
st_boolean_vector_select <= transport 4 ;
-- s_st_boolean_vector(lowb) <=
-- c_st_boolean_vector_1(lowb) after 100 ns ;
--
when 5
=> correct :=
correct and
s_st_boolean_vector(lowb) =
c_st_boolean_vector_1(lowb) and
(s_st_boolean_vector_savt + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00387" ,
"Old transactions were removed on a " &
"concurrent signal asg",
correct ) ;
st_boolean_vector_select <= transport 5 ;
-- s_st_boolean_vector(lowb) <=
-- c_st_boolean_vector_2(lowb) after 10 ns ,
-- c_st_boolean_vector_1(lowb) after 20 ns ,
-- c_st_boolean_vector_2(lowb) after 30 ns ,
-- c_st_boolean_vector_1(lowb) after 40 ns ;
--
when 6
=> correct :=
correct and
s_st_boolean_vector(lowb) =
c_st_boolean_vector_2(lowb) and
(s_st_boolean_vector_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00387" ,
"One inertial transaction occurred on a " &
"concurrent signal asg",
correct ) ;
st_boolean_vector_select <= transport 6 ;
-- Last transaction above is marked
-- s_st_boolean_vector(lowb) <=
-- c_st_boolean_vector_1(lowb) after 40 ns ;
--
when 7
=> correct :=
correct and
s_st_boolean_vector(lowb) =
c_st_boolean_vector_1(lowb) and
(s_st_boolean_vector_savt + 30 ns) = Std.Standard.Now ;
--
when 8
=> correct :=
correct and
s_st_boolean_vector(lowb) =
c_st_boolean_vector_1(lowb) and
(s_st_boolean_vector_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00387" ,
"Inertial semantics check on a concurrent " &
"signal asg",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00387" ,
"Inertial semantics check on a concurrent " &
"signal asg",
false ) ;
--
end case ;
--
s_st_boolean_vector_savt <= transport Std.Standard.Now ;
chk_st_boolean_vector <= transport s_st_boolean_vector_cnt
after (1 us - Std.Standard.Now) ;
s_st_boolean_vector_cnt <= transport s_st_boolean_vector_cnt + 1 ;
wait until (not s_st_boolean_vector(lowb)'Quiet) and
(s_st_boolean_vector_savt /= Std.Standard.Now) ;
--
end process CHG1 ;
--
PGEN_CHKP_1 :
process ( chk_st_boolean_vector )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P1" ,
"Inertial transactions completed entirely",
chk_st_boolean_vector = 8 ) ;
end if ;
end process PGEN_CHKP_1 ;
--
--
with st_boolean_vector_select select
s_st_boolean_vector(lowb) <=
c_st_boolean_vector_2(lowb) after 10 ns,
c_st_boolean_vector_1(lowb) after 20 ns
when 1,
--
c_st_boolean_vector_2(lowb) after 10 ns ,
c_st_boolean_vector_1(lowb) after 20 ns ,
c_st_boolean_vector_2(lowb) after 30 ns ,
c_st_boolean_vector_1(lowb) after 40 ns
when 2,
--
c_st_boolean_vector_1(lowb) after 5 ns
when 3,
--
c_st_boolean_vector_1(lowb) after 100 ns
when 4,
--
c_st_boolean_vector_2(lowb) after 10 ns ,
c_st_boolean_vector_1(lowb) after 20 ns ,
c_st_boolean_vector_2(lowb) after 30 ns ,
c_st_boolean_vector_1(lowb) after 40 ns
when 5,
--
-- Last transaction above is marked
c_st_boolean_vector_1(lowb) after 40 ns when 6 ;
--
CHG2 :
process
variable correct : boolean ;
begin
case s_st_severity_level_vector_cnt is
when 0
=> null ;
-- s_st_severity_level_vector(lowb) <=
-- c_st_severity_level_vector_2(lowb) after 10 ns,
-- c_st_severity_level_vector_1(lowb) after 20 ns ;
--
when 1
=> correct :=
s_st_severity_level_vector(lowb) =
c_st_severity_level_vector_2(lowb) and
(s_st_severity_level_vector_savt + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_severity_level_vector(lowb) =
c_st_severity_level_vector_1(lowb) and
(s_st_severity_level_vector_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00387.P2" ,
"Multi inertial transactions occurred on " &
"concurrent signal asg",
correct ) ;
--
st_severity_level_vector_select <= transport 2 ;
-- s_st_severity_level_vector(lowb) <=
-- c_st_severity_level_vector_2(lowb) after 10 ns ,
-- c_st_severity_level_vector_1(lowb) after 20 ns ,
-- c_st_severity_level_vector_2(lowb) after 30 ns ,
-- c_st_severity_level_vector_1(lowb) after 40 ns ;
--
when 3
=> correct :=
s_st_severity_level_vector(lowb) =
c_st_severity_level_vector_2(lowb) and
(s_st_severity_level_vector_savt + 10 ns) = Std.Standard.Now ;
st_severity_level_vector_select <= transport 3 ;
-- s_st_severity_level_vector(lowb) <=
-- c_st_severity_level_vector_1(lowb) after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_severity_level_vector(lowb) =
c_st_severity_level_vector_1(lowb) and
(s_st_severity_level_vector_savt + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00387" ,
"One inertial transaction occurred on a " &
"concurrent signal asg",
correct ) ;
st_severity_level_vector_select <= transport 4 ;
-- s_st_severity_level_vector(lowb) <=
-- c_st_severity_level_vector_1(lowb) after 100 ns ;
--
when 5
=> correct :=
correct and
s_st_severity_level_vector(lowb) =
c_st_severity_level_vector_1(lowb) and
(s_st_severity_level_vector_savt + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00387" ,
"Old transactions were removed on a " &
"concurrent signal asg",
correct ) ;
st_severity_level_vector_select <= transport 5 ;
-- s_st_severity_level_vector(lowb) <=
-- c_st_severity_level_vector_2(lowb) after 10 ns ,
-- c_st_severity_level_vector_1(lowb) after 20 ns ,
-- c_st_severity_level_vector_2(lowb) after 30 ns ,
-- c_st_severity_level_vector_1(lowb) after 40 ns ;
--
when 6
=> correct :=
correct and
s_st_severity_level_vector(lowb) =
c_st_severity_level_vector_2(lowb) and
(s_st_severity_level_vector_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00387" ,
"One inertial transaction occurred on a " &
"concurrent signal asg",
correct ) ;
st_severity_level_vector_select <= transport 6 ;
-- Last transaction above is marked
-- s_st_severity_level_vector(lowb) <=
-- c_st_severity_level_vector_1(lowb) after 40 ns ;
--
when 7
=> correct :=
correct and
s_st_severity_level_vector(lowb) =
c_st_severity_level_vector_1(lowb) and
(s_st_severity_level_vector_savt + 30 ns) = Std.Standard.Now ;
--
when 8
=> correct :=
correct and
s_st_severity_level_vector(lowb) =
c_st_severity_level_vector_1(lowb) and
(s_st_severity_level_vector_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00387" ,
"Inertial semantics check on a concurrent " &
"signal asg",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00387" ,
"Inertial semantics check on a concurrent " &
"signal asg",
false ) ;
--
end case ;
--
s_st_severity_level_vector_savt <= transport Std.Standard.Now ;
chk_st_severity_level_vector <= transport s_st_severity_level_vector_cnt
after (1 us - Std.Standard.Now) ;
s_st_severity_level_vector_cnt <= transport s_st_severity_level_vector_cnt
+ 1 ;
wait until (not s_st_severity_level_vector(lowb)'Quiet) and
(s_st_severity_level_vector_savt /= Std.Standard.Now) ;
--
end process CHG2 ;
--
PGEN_CHKP_2 :
process ( chk_st_severity_level_vector )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P2" ,
"Inertial transactions completed entirely",
chk_st_severity_level_vector = 8 ) ;
end if ;
end process PGEN_CHKP_2 ;
--
--
with st_severity_level_vector_select select
s_st_severity_level_vector(lowb) <=
c_st_severity_level_vector_2(lowb) after 10 ns,
c_st_severity_level_vector_1(lowb) after 20 ns
when 1,
--
c_st_severity_level_vector_2(lowb) after 10 ns ,
c_st_severity_level_vector_1(lowb) after 20 ns ,
c_st_severity_level_vector_2(lowb) after 30 ns ,
c_st_severity_level_vector_1(lowb) after 40 ns
when 2,
--
c_st_severity_level_vector_1(lowb) after 5 ns
when 3,
--
c_st_severity_level_vector_1(lowb) after 100 ns
when 4,
--
c_st_severity_level_vector_2(lowb) after 10 ns ,
c_st_severity_level_vector_1(lowb) after 20 ns ,
c_st_severity_level_vector_2(lowb) after 30 ns ,
c_st_severity_level_vector_1(lowb) after 40 ns
when 5,
--
-- Last transaction above is marked
c_st_severity_level_vector_1(lowb) after 40 ns when 6 ;
--
CHG3 :
process
variable correct : boolean ;
begin
case s_st_string_cnt is
when 0
=> null ;
-- s_st_string(highb) <=
-- c_st_string_2(highb) after 10 ns,
-- c_st_string_1(highb) after 20 ns ;
--
when 1
=> correct :=
s_st_string(highb) =
c_st_string_2(highb) and
(s_st_string_savt + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_string(highb) =
c_st_string_1(highb) and
(s_st_string_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00387.P3" ,
"Multi inertial transactions occurred on " &
"concurrent signal asg",
correct ) ;
--
st_string_select <= transport 2 ;
-- s_st_string(highb) <=
-- c_st_string_2(highb) after 10 ns ,
-- c_st_string_1(highb) after 20 ns ,
-- c_st_string_2(highb) after 30 ns ,
-- c_st_string_1(highb) after 40 ns ;
--
when 3
=> correct :=
s_st_string(highb) =
c_st_string_2(highb) and
(s_st_string_savt + 10 ns) = Std.Standard.Now ;
st_string_select <= transport 3 ;
-- s_st_string(highb) <=
-- c_st_string_1(highb) after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_string(highb) =
c_st_string_1(highb) and
(s_st_string_savt + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00387" ,
"One inertial transaction occurred on a " &
"concurrent signal asg",
correct ) ;
st_string_select <= transport 4 ;
-- s_st_string(highb) <=
-- c_st_string_1(highb) after 100 ns ;
--
when 5
=> correct :=
correct and
s_st_string(highb) =
c_st_string_1(highb) and
(s_st_string_savt + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00387" ,
"Old transactions were removed on a " &
"concurrent signal asg",
correct ) ;
st_string_select <= transport 5 ;
-- s_st_string(highb) <=
-- c_st_string_2(highb) after 10 ns ,
-- c_st_string_1(highb) after 20 ns ,
-- c_st_string_2(highb) after 30 ns ,
-- c_st_string_1(highb) after 40 ns ;
--
when 6
=> correct :=
correct and
s_st_string(highb) =
c_st_string_2(highb) and
(s_st_string_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00387" ,
"One inertial transaction occurred on a " &
"concurrent signal asg",
correct ) ;
st_string_select <= transport 6 ;
-- Last transaction above is marked
-- s_st_string(highb) <=
-- c_st_string_1(highb) after 40 ns ;
--
when 7
=> correct :=
correct and
s_st_string(highb) =
c_st_string_1(highb) and
(s_st_string_savt + 30 ns) = Std.Standard.Now ;
--
when 8
=> correct :=
correct and
s_st_string(highb) =
c_st_string_1(highb) and
(s_st_string_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00387" ,
"Inertial semantics check on a concurrent " &
"signal asg",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00387" ,
"Inertial semantics check on a concurrent " &
"signal asg",
false ) ;
--
end case ;
--
s_st_string_savt <= transport Std.Standard.Now ;
chk_st_string <= transport s_st_string_cnt
after (1 us - Std.Standard.Now) ;
s_st_string_cnt <= transport s_st_string_cnt + 1 ;
wait until (not s_st_string(highb)'Quiet) and
(s_st_string_savt /= Std.Standard.Now) ;
--
end process CHG3 ;
--
PGEN_CHKP_3 :
process ( chk_st_string )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P3" ,
"Inertial transactions completed entirely",
chk_st_string = 8 ) ;
end if ;
end process PGEN_CHKP_3 ;
--
--
with st_string_select select
s_st_string(highb) <=
c_st_string_2(highb) after 10 ns,
c_st_string_1(highb) after 20 ns
when 1,
--
c_st_string_2(highb) after 10 ns ,
c_st_string_1(highb) after 20 ns ,
c_st_string_2(highb) after 30 ns ,
c_st_string_1(highb) after 40 ns
when 2,
--
c_st_string_1(highb) after 5 ns
when 3,
--
c_st_string_1(highb) after 100 ns
when 4,
--
c_st_string_2(highb) after 10 ns ,
c_st_string_1(highb) after 20 ns ,
c_st_string_2(highb) after 30 ns ,
c_st_string_1(highb) after 40 ns
when 5,
--
-- Last transaction above is marked
c_st_string_1(highb) after 40 ns when 6 ;
--
CHG4 :
process
variable correct : boolean ;
begin
case s_st_enum1_vector_cnt is
when 0
=> null ;
-- s_st_enum1_vector(highb) <=
-- c_st_enum1_vector_2(highb) after 10 ns,
-- c_st_enum1_vector_1(highb) after 20 ns ;
--
when 1
=> correct :=
s_st_enum1_vector(highb) =
c_st_enum1_vector_2(highb) and
(s_st_enum1_vector_savt + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_enum1_vector(highb) =
c_st_enum1_vector_1(highb) and
(s_st_enum1_vector_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00387.P4" ,
"Multi inertial transactions occurred on " &
"concurrent signal asg",
correct ) ;
--
st_enum1_vector_select <= transport 2 ;
-- s_st_enum1_vector(highb) <=
-- c_st_enum1_vector_2(highb) after 10 ns ,
-- c_st_enum1_vector_1(highb) after 20 ns ,
-- c_st_enum1_vector_2(highb) after 30 ns ,
-- c_st_enum1_vector_1(highb) after 40 ns ;
--
when 3
=> correct :=
s_st_enum1_vector(highb) =
c_st_enum1_vector_2(highb) and
(s_st_enum1_vector_savt + 10 ns) = Std.Standard.Now ;
st_enum1_vector_select <= transport 3 ;
-- s_st_enum1_vector(highb) <=
-- c_st_enum1_vector_1(highb) after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_enum1_vector(highb) =
c_st_enum1_vector_1(highb) and
(s_st_enum1_vector_savt + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00387" ,
"One inertial transaction occurred on a " &
"concurrent signal asg",
correct ) ;
st_enum1_vector_select <= transport 4 ;
-- s_st_enum1_vector(highb) <=
-- c_st_enum1_vector_1(highb) after 100 ns ;
--
when 5
=> correct :=
correct and
s_st_enum1_vector(highb) =
c_st_enum1_vector_1(highb) and
(s_st_enum1_vector_savt + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00387" ,
"Old transactions were removed on a " &
"concurrent signal asg",
correct ) ;
st_enum1_vector_select <= transport 5 ;
-- s_st_enum1_vector(highb) <=
-- c_st_enum1_vector_2(highb) after 10 ns ,
-- c_st_enum1_vector_1(highb) after 20 ns ,
-- c_st_enum1_vector_2(highb) after 30 ns ,
-- c_st_enum1_vector_1(highb) after 40 ns ;
--
when 6
=> correct :=
correct and
s_st_enum1_vector(highb) =
c_st_enum1_vector_2(highb) and
(s_st_enum1_vector_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00387" ,
"One inertial transaction occurred on a " &
"concurrent signal asg",
correct ) ;
st_enum1_vector_select <= transport 6 ;
-- Last transaction above is marked
-- s_st_enum1_vector(highb) <=
-- c_st_enum1_vector_1(highb) after 40 ns ;
--
when 7
=> correct :=
correct and
s_st_enum1_vector(highb) =
c_st_enum1_vector_1(highb) and
(s_st_enum1_vector_savt + 30 ns) = Std.Standard.Now ;
--
when 8
=> correct :=
correct and
s_st_enum1_vector(highb) =
c_st_enum1_vector_1(highb) and
(s_st_enum1_vector_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00387" ,
"Inertial semantics check on a concurrent " &
"signal asg",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00387" ,
"Inertial semantics check on a concurrent " &
"signal asg",
false ) ;
--
end case ;
--
s_st_enum1_vector_savt <= transport Std.Standard.Now ;
chk_st_enum1_vector <= transport s_st_enum1_vector_cnt
after (1 us - Std.Standard.Now) ;
s_st_enum1_vector_cnt <= transport s_st_enum1_vector_cnt + 1 ;
wait until (not s_st_enum1_vector(highb)'Quiet) and
(s_st_enum1_vector_savt /= Std.Standard.Now) ;
--
end process CHG4 ;
--
PGEN_CHKP_4 :
process ( chk_st_enum1_vector )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P4" ,
"Inertial transactions completed entirely",
chk_st_enum1_vector = 8 ) ;
end if ;
end process PGEN_CHKP_4 ;
--
--
with st_enum1_vector_select select
s_st_enum1_vector(highb) <=
c_st_enum1_vector_2(highb) after 10 ns,
c_st_enum1_vector_1(highb) after 20 ns
when 1,
--
c_st_enum1_vector_2(highb) after 10 ns ,
c_st_enum1_vector_1(highb) after 20 ns ,
c_st_enum1_vector_2(highb) after 30 ns ,
c_st_enum1_vector_1(highb) after 40 ns
when 2,
--
c_st_enum1_vector_1(highb) after 5 ns
when 3,
--
c_st_enum1_vector_1(highb) after 100 ns
when 4,
--
c_st_enum1_vector_2(highb) after 10 ns ,
c_st_enum1_vector_1(highb) after 20 ns ,
c_st_enum1_vector_2(highb) after 30 ns ,
c_st_enum1_vector_1(highb) after 40 ns
when 5,
--
-- Last transaction above is marked
c_st_enum1_vector_1(highb) after 40 ns when 6 ;
--
CHG5 :
process
variable correct : boolean ;
begin
case s_st_integer_vector_cnt is
when 0
=> null ;
-- s_st_integer_vector(lowb) <=
-- c_st_integer_vector_2(lowb) after 10 ns,
-- c_st_integer_vector_1(lowb) after 20 ns ;
--
when 1
=> correct :=
s_st_integer_vector(lowb) =
c_st_integer_vector_2(lowb) and
(s_st_integer_vector_savt + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_integer_vector(lowb) =
c_st_integer_vector_1(lowb) and
(s_st_integer_vector_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00387.P5" ,
"Multi inertial transactions occurred on " &
"concurrent signal asg",
correct ) ;
--
st_integer_vector_select <= transport 2 ;
-- s_st_integer_vector(lowb) <=
-- c_st_integer_vector_2(lowb) after 10 ns ,
-- c_st_integer_vector_1(lowb) after 20 ns ,
-- c_st_integer_vector_2(lowb) after 30 ns ,
-- c_st_integer_vector_1(lowb) after 40 ns ;
--
when 3
=> correct :=
s_st_integer_vector(lowb) =
c_st_integer_vector_2(lowb) and
(s_st_integer_vector_savt + 10 ns) = Std.Standard.Now ;
st_integer_vector_select <= transport 3 ;
-- s_st_integer_vector(lowb) <=
-- c_st_integer_vector_1(lowb) after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_integer_vector(lowb) =
c_st_integer_vector_1(lowb) and
(s_st_integer_vector_savt + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00387" ,
"One inertial transaction occurred on a " &
"concurrent signal asg",
correct ) ;
st_integer_vector_select <= transport 4 ;
-- s_st_integer_vector(lowb) <=
-- c_st_integer_vector_1(lowb) after 100 ns ;
--
when 5
=> correct :=
correct and
s_st_integer_vector(lowb) =
c_st_integer_vector_1(lowb) and
(s_st_integer_vector_savt + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00387" ,
"Old transactions were removed on a " &
"concurrent signal asg",
correct ) ;
st_integer_vector_select <= transport 5 ;
-- s_st_integer_vector(lowb) <=
-- c_st_integer_vector_2(lowb) after 10 ns ,
-- c_st_integer_vector_1(lowb) after 20 ns ,
-- c_st_integer_vector_2(lowb) after 30 ns ,
-- c_st_integer_vector_1(lowb) after 40 ns ;
--
when 6
=> correct :=
correct and
s_st_integer_vector(lowb) =
c_st_integer_vector_2(lowb) and
(s_st_integer_vector_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00387" ,
"One inertial transaction occurred on a " &
"concurrent signal asg",
correct ) ;
st_integer_vector_select <= transport 6 ;
-- Last transaction above is marked
-- s_st_integer_vector(lowb) <=
-- c_st_integer_vector_1(lowb) after 40 ns ;
--
when 7
=> correct :=
correct and
s_st_integer_vector(lowb) =
c_st_integer_vector_1(lowb) and
(s_st_integer_vector_savt + 30 ns) = Std.Standard.Now ;
--
when 8
=> correct :=
correct and
s_st_integer_vector(lowb) =
c_st_integer_vector_1(lowb) and
(s_st_integer_vector_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00387" ,
"Inertial semantics check on a concurrent " &
"signal asg",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00387" ,
"Inertial semantics check on a concurrent " &
"signal asg",
false ) ;
--
end case ;
--
s_st_integer_vector_savt <= transport Std.Standard.Now ;
chk_st_integer_vector <= transport s_st_integer_vector_cnt
after (1 us - Std.Standard.Now) ;
s_st_integer_vector_cnt <= transport s_st_integer_vector_cnt + 1 ;
wait until (not s_st_integer_vector(lowb)'Quiet) and
(s_st_integer_vector_savt /= Std.Standard.Now) ;
--
end process CHG5 ;
--
PGEN_CHKP_5 :
process ( chk_st_integer_vector )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P5" ,
"Inertial transactions completed entirely",
chk_st_integer_vector = 8 ) ;
end if ;
end process PGEN_CHKP_5 ;
--
--
with st_integer_vector_select select
s_st_integer_vector(lowb) <=
c_st_integer_vector_2(lowb) after 10 ns,
c_st_integer_vector_1(lowb) after 20 ns
when 1,
--
c_st_integer_vector_2(lowb) after 10 ns ,
c_st_integer_vector_1(lowb) after 20 ns ,
c_st_integer_vector_2(lowb) after 30 ns ,
c_st_integer_vector_1(lowb) after 40 ns
when 2,
--
c_st_integer_vector_1(lowb) after 5 ns
when 3,
--
c_st_integer_vector_1(lowb) after 100 ns
when 4,
--
c_st_integer_vector_2(lowb) after 10 ns ,
c_st_integer_vector_1(lowb) after 20 ns ,
c_st_integer_vector_2(lowb) after 30 ns ,
c_st_integer_vector_1(lowb) after 40 ns
when 5,
--
-- Last transaction above is marked
c_st_integer_vector_1(lowb) after 40 ns when 6 ;
--
CHG6 :
process
variable correct : boolean ;
begin
case s_st_time_vector_cnt is
when 0
=> null ;
-- s_st_time_vector(lowb) <=
-- c_st_time_vector_2(lowb) after 10 ns,
-- c_st_time_vector_1(lowb) after 20 ns ;
--
when 1
=> correct :=
s_st_time_vector(lowb) =
c_st_time_vector_2(lowb) and
(s_st_time_vector_savt + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_time_vector(lowb) =
c_st_time_vector_1(lowb) and
(s_st_time_vector_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00387.P6" ,
"Multi inertial transactions occurred on " &
"concurrent signal asg",
correct ) ;
--
st_time_vector_select <= transport 2 ;
-- s_st_time_vector(lowb) <=
-- c_st_time_vector_2(lowb) after 10 ns ,
-- c_st_time_vector_1(lowb) after 20 ns ,
-- c_st_time_vector_2(lowb) after 30 ns ,
-- c_st_time_vector_1(lowb) after 40 ns ;
--
when 3
=> correct :=
s_st_time_vector(lowb) =
c_st_time_vector_2(lowb) and
(s_st_time_vector_savt + 10 ns) = Std.Standard.Now ;
st_time_vector_select <= transport 3 ;
-- s_st_time_vector(lowb) <=
-- c_st_time_vector_1(lowb) after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_time_vector(lowb) =
c_st_time_vector_1(lowb) and
(s_st_time_vector_savt + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00387" ,
"One inertial transaction occurred on a " &
"concurrent signal asg",
correct ) ;
st_time_vector_select <= transport 4 ;
-- s_st_time_vector(lowb) <=
-- c_st_time_vector_1(lowb) after 100 ns ;
--
when 5
=> correct :=
correct and
s_st_time_vector(lowb) =
c_st_time_vector_1(lowb) and
(s_st_time_vector_savt + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00387" ,
"Old transactions were removed on a " &
"concurrent signal asg",
correct ) ;
st_time_vector_select <= transport 5 ;
-- s_st_time_vector(lowb) <=
-- c_st_time_vector_2(lowb) after 10 ns ,
-- c_st_time_vector_1(lowb) after 20 ns ,
-- c_st_time_vector_2(lowb) after 30 ns ,
-- c_st_time_vector_1(lowb) after 40 ns ;
--
when 6
=> correct :=
correct and
s_st_time_vector(lowb) =
c_st_time_vector_2(lowb) and
(s_st_time_vector_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00387" ,
"One inertial transaction occurred on a " &
"concurrent signal asg",
correct ) ;
st_time_vector_select <= transport 6 ;
-- Last transaction above is marked
-- s_st_time_vector(lowb) <=
-- c_st_time_vector_1(lowb) after 40 ns ;
--
when 7
=> correct :=
correct and
s_st_time_vector(lowb) =
c_st_time_vector_1(lowb) and
(s_st_time_vector_savt + 30 ns) = Std.Standard.Now ;
--
when 8
=> correct :=
correct and
s_st_time_vector(lowb) =
c_st_time_vector_1(lowb) and
(s_st_time_vector_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00387" ,
"Inertial semantics check on a concurrent " &
"signal asg",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00387" ,
"Inertial semantics check on a concurrent " &
"signal asg",
false ) ;
--
end case ;
--
s_st_time_vector_savt <= transport Std.Standard.Now ;
chk_st_time_vector <= transport s_st_time_vector_cnt
after (1 us - Std.Standard.Now) ;
s_st_time_vector_cnt <= transport s_st_time_vector_cnt + 1 ;
wait until (not s_st_time_vector(lowb)'Quiet) and
(s_st_time_vector_savt /= Std.Standard.Now) ;
--
end process CHG6 ;
--
PGEN_CHKP_6 :
process ( chk_st_time_vector )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P6" ,
"Inertial transactions completed entirely",
chk_st_time_vector = 8 ) ;
end if ;
end process PGEN_CHKP_6 ;
--
--
with st_time_vector_select select
s_st_time_vector(lowb) <=
c_st_time_vector_2(lowb) after 10 ns,
c_st_time_vector_1(lowb) after 20 ns
when 1,
--
c_st_time_vector_2(lowb) after 10 ns ,
c_st_time_vector_1(lowb) after 20 ns ,
c_st_time_vector_2(lowb) after 30 ns ,
c_st_time_vector_1(lowb) after 40 ns
when 2,
--
c_st_time_vector_1(lowb) after 5 ns
when 3,
--
c_st_time_vector_1(lowb) after 100 ns
when 4,
--
c_st_time_vector_2(lowb) after 10 ns ,
c_st_time_vector_1(lowb) after 20 ns ,
c_st_time_vector_2(lowb) after 30 ns ,
c_st_time_vector_1(lowb) after 40 ns
when 5,
--
-- Last transaction above is marked
c_st_time_vector_1(lowb) after 40 ns when 6 ;
--
CHG7 :
process
variable correct : boolean ;
begin
case s_st_real_vector_cnt is
when 0
=> null ;
-- s_st_real_vector(highb) <=
-- c_st_real_vector_2(highb) after 10 ns,
-- c_st_real_vector_1(highb) after 20 ns ;
--
when 1
=> correct :=
s_st_real_vector(highb) =
c_st_real_vector_2(highb) and
(s_st_real_vector_savt + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_real_vector(highb) =
c_st_real_vector_1(highb) and
(s_st_real_vector_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00387.P7" ,
"Multi inertial transactions occurred on " &
"concurrent signal asg",
correct ) ;
--
st_real_vector_select <= transport 2 ;
-- s_st_real_vector(highb) <=
-- c_st_real_vector_2(highb) after 10 ns ,
-- c_st_real_vector_1(highb) after 20 ns ,
-- c_st_real_vector_2(highb) after 30 ns ,
-- c_st_real_vector_1(highb) after 40 ns ;
--
when 3
=> correct :=
s_st_real_vector(highb) =
c_st_real_vector_2(highb) and
(s_st_real_vector_savt + 10 ns) = Std.Standard.Now ;
st_real_vector_select <= transport 3 ;
-- s_st_real_vector(highb) <=
-- c_st_real_vector_1(highb) after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_real_vector(highb) =
c_st_real_vector_1(highb) and
(s_st_real_vector_savt + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00387" ,
"One inertial transaction occurred on a " &
"concurrent signal asg",
correct ) ;
st_real_vector_select <= transport 4 ;
-- s_st_real_vector(highb) <=
-- c_st_real_vector_1(highb) after 100 ns ;
--
when 5
=> correct :=
correct and
s_st_real_vector(highb) =
c_st_real_vector_1(highb) and
(s_st_real_vector_savt + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00387" ,
"Old transactions were removed on a " &
"concurrent signal asg",
correct ) ;
st_real_vector_select <= transport 5 ;
-- s_st_real_vector(highb) <=
-- c_st_real_vector_2(highb) after 10 ns ,
-- c_st_real_vector_1(highb) after 20 ns ,
-- c_st_real_vector_2(highb) after 30 ns ,
-- c_st_real_vector_1(highb) after 40 ns ;
--
when 6
=> correct :=
correct and
s_st_real_vector(highb) =
c_st_real_vector_2(highb) and
(s_st_real_vector_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00387" ,
"One inertial transaction occurred on a " &
"concurrent signal asg",
correct ) ;
st_real_vector_select <= transport 6 ;
-- Last transaction above is marked
-- s_st_real_vector(highb) <=
-- c_st_real_vector_1(highb) after 40 ns ;
--
when 7
=> correct :=
correct and
s_st_real_vector(highb) =
c_st_real_vector_1(highb) and
(s_st_real_vector_savt + 30 ns) = Std.Standard.Now ;
--
when 8
=> correct :=
correct and
s_st_real_vector(highb) =
c_st_real_vector_1(highb) and
(s_st_real_vector_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00387" ,
"Inertial semantics check on a concurrent " &
"signal asg",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00387" ,
"Inertial semantics check on a concurrent " &
"signal asg",
false ) ;
--
end case ;
--
s_st_real_vector_savt <= transport Std.Standard.Now ;
chk_st_real_vector <= transport s_st_real_vector_cnt
after (1 us - Std.Standard.Now) ;
s_st_real_vector_cnt <= transport s_st_real_vector_cnt + 1 ;
wait until (not s_st_real_vector(highb)'Quiet) and
(s_st_real_vector_savt /= Std.Standard.Now) ;
--
end process CHG7 ;
--
PGEN_CHKP_7 :
process ( chk_st_real_vector )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P7" ,
"Inertial transactions completed entirely",
chk_st_real_vector = 8 ) ;
end if ;
end process PGEN_CHKP_7 ;
--
--
with st_real_vector_select select
s_st_real_vector(highb) <=
c_st_real_vector_2(highb) after 10 ns,
c_st_real_vector_1(highb) after 20 ns
when 1,
--
c_st_real_vector_2(highb) after 10 ns ,
c_st_real_vector_1(highb) after 20 ns ,
c_st_real_vector_2(highb) after 30 ns ,
c_st_real_vector_1(highb) after 40 ns
when 2,
--
c_st_real_vector_1(highb) after 5 ns
when 3,
--
c_st_real_vector_1(highb) after 100 ns
when 4,
--
c_st_real_vector_2(highb) after 10 ns ,
c_st_real_vector_1(highb) after 20 ns ,
c_st_real_vector_2(highb) after 30 ns ,
c_st_real_vector_1(highb) after 40 ns
when 5,
--
-- Last transaction above is marked
c_st_real_vector_1(highb) after 40 ns when 6 ;
--
CHG8 :
process
variable correct : boolean ;
begin
case s_st_rec1_vector_cnt is
when 0
=> null ;
-- s_st_rec1_vector(highb) <=
-- c_st_rec1_vector_2(highb) after 10 ns,
-- c_st_rec1_vector_1(highb) after 20 ns ;
--
when 1
=> correct :=
s_st_rec1_vector(highb) =
c_st_rec1_vector_2(highb) and
(s_st_rec1_vector_savt + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_rec1_vector(highb) =
c_st_rec1_vector_1(highb) and
(s_st_rec1_vector_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00387.P8" ,
"Multi inertial transactions occurred on " &
"concurrent signal asg",
correct ) ;
--
st_rec1_vector_select <= transport 2 ;
-- s_st_rec1_vector(highb) <=
-- c_st_rec1_vector_2(highb) after 10 ns ,
-- c_st_rec1_vector_1(highb) after 20 ns ,
-- c_st_rec1_vector_2(highb) after 30 ns ,
-- c_st_rec1_vector_1(highb) after 40 ns ;
--
when 3
=> correct :=
s_st_rec1_vector(highb) =
c_st_rec1_vector_2(highb) and
(s_st_rec1_vector_savt + 10 ns) = Std.Standard.Now ;
st_rec1_vector_select <= transport 3 ;
-- s_st_rec1_vector(highb) <=
-- c_st_rec1_vector_1(highb) after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_rec1_vector(highb) =
c_st_rec1_vector_1(highb) and
(s_st_rec1_vector_savt + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00387" ,
"One inertial transaction occurred on a " &
"concurrent signal asg",
correct ) ;
st_rec1_vector_select <= transport 4 ;
-- s_st_rec1_vector(highb) <=
-- c_st_rec1_vector_1(highb) after 100 ns ;
--
when 5
=> correct :=
correct and
s_st_rec1_vector(highb) =
c_st_rec1_vector_1(highb) and
(s_st_rec1_vector_savt + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00387" ,
"Old transactions were removed on a " &
"concurrent signal asg",
correct ) ;
st_rec1_vector_select <= transport 5 ;
-- s_st_rec1_vector(highb) <=
-- c_st_rec1_vector_2(highb) after 10 ns ,
-- c_st_rec1_vector_1(highb) after 20 ns ,
-- c_st_rec1_vector_2(highb) after 30 ns ,
-- c_st_rec1_vector_1(highb) after 40 ns ;
--
when 6
=> correct :=
correct and
s_st_rec1_vector(highb) =
c_st_rec1_vector_2(highb) and
(s_st_rec1_vector_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00387" ,
"One inertial transaction occurred on a " &
"concurrent signal asg",
correct ) ;
st_rec1_vector_select <= transport 6 ;
-- Last transaction above is marked
-- s_st_rec1_vector(highb) <=
-- c_st_rec1_vector_1(highb) after 40 ns ;
--
when 7
=> correct :=
correct and
s_st_rec1_vector(highb) =
c_st_rec1_vector_1(highb) and
(s_st_rec1_vector_savt + 30 ns) = Std.Standard.Now ;
--
when 8
=> correct :=
correct and
s_st_rec1_vector(highb) =
c_st_rec1_vector_1(highb) and
(s_st_rec1_vector_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00387" ,
"Inertial semantics check on a concurrent " &
"signal asg",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00387" ,
"Inertial semantics check on a concurrent " &
"signal asg",
false ) ;
--
end case ;
--
s_st_rec1_vector_savt <= transport Std.Standard.Now ;
chk_st_rec1_vector <= transport s_st_rec1_vector_cnt
after (1 us - Std.Standard.Now) ;
s_st_rec1_vector_cnt <= transport s_st_rec1_vector_cnt + 1 ;
wait until (not s_st_rec1_vector(highb)'Quiet) and
(s_st_rec1_vector_savt /= Std.Standard.Now) ;
--
end process CHG8 ;
--
PGEN_CHKP_8 :
process ( chk_st_rec1_vector )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P8" ,
"Inertial transactions completed entirely",
chk_st_rec1_vector = 8 ) ;
end if ;
end process PGEN_CHKP_8 ;
--
--
with st_rec1_vector_select select
s_st_rec1_vector(highb) <=
c_st_rec1_vector_2(highb) after 10 ns,
c_st_rec1_vector_1(highb) after 20 ns
when 1,
--
c_st_rec1_vector_2(highb) after 10 ns ,
c_st_rec1_vector_1(highb) after 20 ns ,
c_st_rec1_vector_2(highb) after 30 ns ,
c_st_rec1_vector_1(highb) after 40 ns
when 2,
--
c_st_rec1_vector_1(highb) after 5 ns
when 3,
--
c_st_rec1_vector_1(highb) after 100 ns
when 4,
--
c_st_rec1_vector_2(highb) after 10 ns ,
c_st_rec1_vector_1(highb) after 20 ns ,
c_st_rec1_vector_2(highb) after 30 ns ,
c_st_rec1_vector_1(highb) after 40 ns
when 5,
--
-- Last transaction above is marked
c_st_rec1_vector_1(highb) after 40 ns when 6 ;
--
CHG9 :
process
variable correct : boolean ;
begin
case s_st_arr2_vector_cnt is
when 0
=> null ;
-- s_st_arr2_vector(lowb) <=
-- c_st_arr2_vector_2(lowb) after 10 ns,
-- c_st_arr2_vector_1(lowb) after 20 ns ;
--
when 1
=> correct :=
s_st_arr2_vector(lowb) =
c_st_arr2_vector_2(lowb) and
(s_st_arr2_vector_savt + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_arr2_vector(lowb) =
c_st_arr2_vector_1(lowb) and
(s_st_arr2_vector_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00387.P9" ,
"Multi inertial transactions occurred on " &
"concurrent signal asg",
correct ) ;
--
st_arr2_vector_select <= transport 2 ;
-- s_st_arr2_vector(lowb) <=
-- c_st_arr2_vector_2(lowb) after 10 ns ,
-- c_st_arr2_vector_1(lowb) after 20 ns ,
-- c_st_arr2_vector_2(lowb) after 30 ns ,
-- c_st_arr2_vector_1(lowb) after 40 ns ;
--
when 3
=> correct :=
s_st_arr2_vector(lowb) =
c_st_arr2_vector_2(lowb) and
(s_st_arr2_vector_savt + 10 ns) = Std.Standard.Now ;
st_arr2_vector_select <= transport 3 ;
-- s_st_arr2_vector(lowb) <=
-- c_st_arr2_vector_1(lowb) after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_arr2_vector(lowb) =
c_st_arr2_vector_1(lowb) and
(s_st_arr2_vector_savt + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00387" ,
"One inertial transaction occurred on a " &
"concurrent signal asg",
correct ) ;
st_arr2_vector_select <= transport 4 ;
-- s_st_arr2_vector(lowb) <=
-- c_st_arr2_vector_1(lowb) after 100 ns ;
--
when 5
=> correct :=
correct and
s_st_arr2_vector(lowb) =
c_st_arr2_vector_1(lowb) and
(s_st_arr2_vector_savt + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00387" ,
"Old transactions were removed on a " &
"concurrent signal asg",
correct ) ;
st_arr2_vector_select <= transport 5 ;
-- s_st_arr2_vector(lowb) <=
-- c_st_arr2_vector_2(lowb) after 10 ns ,
-- c_st_arr2_vector_1(lowb) after 20 ns ,
-- c_st_arr2_vector_2(lowb) after 30 ns ,
-- c_st_arr2_vector_1(lowb) after 40 ns ;
--
when 6
=> correct :=
correct and
s_st_arr2_vector(lowb) =
c_st_arr2_vector_2(lowb) and
(s_st_arr2_vector_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00387" ,
"One inertial transaction occurred on a " &
"concurrent signal asg",
correct ) ;
st_arr2_vector_select <= transport 6 ;
-- Last transaction above is marked
-- s_st_arr2_vector(lowb) <=
-- c_st_arr2_vector_1(lowb) after 40 ns ;
--
when 7
=> correct :=
correct and
s_st_arr2_vector(lowb) =
c_st_arr2_vector_1(lowb) and
(s_st_arr2_vector_savt + 30 ns) = Std.Standard.Now ;
--
when 8
=> correct :=
correct and
s_st_arr2_vector(lowb) =
c_st_arr2_vector_1(lowb) and
(s_st_arr2_vector_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00387" ,
"Inertial semantics check on a concurrent " &
"signal asg",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00387" ,
"Inertial semantics check on a concurrent " &
"signal asg",
false ) ;
--
end case ;
--
s_st_arr2_vector_savt <= transport Std.Standard.Now ;
chk_st_arr2_vector <= transport s_st_arr2_vector_cnt
after (1 us - Std.Standard.Now) ;
s_st_arr2_vector_cnt <= transport s_st_arr2_vector_cnt + 1 ;
wait until (not s_st_arr2_vector(lowb)'Quiet) and
(s_st_arr2_vector_savt /= Std.Standard.Now) ;
--
end process CHG9 ;
--
PGEN_CHKP_9 :
process ( chk_st_arr2_vector )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P9" ,
"Inertial transactions completed entirely",
chk_st_arr2_vector = 8 ) ;
end if ;
end process PGEN_CHKP_9 ;
--
--
with st_arr2_vector_select select
s_st_arr2_vector(lowb) <=
c_st_arr2_vector_2(lowb) after 10 ns,
c_st_arr2_vector_1(lowb) after 20 ns
when 1,
--
c_st_arr2_vector_2(lowb) after 10 ns ,
c_st_arr2_vector_1(lowb) after 20 ns ,
c_st_arr2_vector_2(lowb) after 30 ns ,
c_st_arr2_vector_1(lowb) after 40 ns
when 2,
--
c_st_arr2_vector_1(lowb) after 5 ns
when 3,
--
c_st_arr2_vector_1(lowb) after 100 ns
when 4,
--
c_st_arr2_vector_2(lowb) after 10 ns ,
c_st_arr2_vector_1(lowb) after 20 ns ,
c_st_arr2_vector_2(lowb) after 30 ns ,
c_st_arr2_vector_1(lowb) after 40 ns
when 5,
--
-- Last transaction above is marked
c_st_arr2_vector_1(lowb) after 40 ns when 6 ;
--
CHG10 :
process
variable correct : boolean ;
begin
case s_st_arr2_cnt is
when 0
=> null ;
-- s_st_arr2(highb,false) <=
-- c_st_arr2_2(highb,false) after 10 ns,
-- c_st_arr2_1(highb,false) after 20 ns ;
--
when 1
=> correct :=
s_st_arr2(highb,false) =
c_st_arr2_2(highb,false) and
(s_st_arr2_savt + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_arr2(highb,false) =
c_st_arr2_1(highb,false) and
(s_st_arr2_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00387.P10" ,
"Multi inertial transactions occurred on " &
"concurrent signal asg",
correct ) ;
--
st_arr2_select <= transport 2 ;
-- s_st_arr2(highb,false) <=
-- c_st_arr2_2(highb,false) after 10 ns ,
-- c_st_arr2_1(highb,false) after 20 ns ,
-- c_st_arr2_2(highb,false) after 30 ns ,
-- c_st_arr2_1(highb,false) after 40 ns ;
--
when 3
=> correct :=
s_st_arr2(highb,false) =
c_st_arr2_2(highb,false) and
(s_st_arr2_savt + 10 ns) = Std.Standard.Now ;
st_arr2_select <= transport 3 ;
-- s_st_arr2(highb,false) <=
-- c_st_arr2_1(highb,false) after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_arr2(highb,false) =
c_st_arr2_1(highb,false) and
(s_st_arr2_savt + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00387" ,
"One inertial transaction occurred on a " &
"concurrent signal asg",
correct ) ;
st_arr2_select <= transport 4 ;
-- s_st_arr2(highb,false) <=
-- c_st_arr2_1(highb,false) after 100 ns ;
--
when 5
=> correct :=
correct and
s_st_arr2(highb,false) =
c_st_arr2_1(highb,false) and
(s_st_arr2_savt + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00387" ,
"Old transactions were removed on a " &
"concurrent signal asg",
correct ) ;
st_arr2_select <= transport 5 ;
-- s_st_arr2(highb,false) <=
-- c_st_arr2_2(highb,false) after 10 ns ,
-- c_st_arr2_1(highb,false) after 20 ns ,
-- c_st_arr2_2(highb,false) after 30 ns ,
-- c_st_arr2_1(highb,false) after 40 ns ;
--
when 6
=> correct :=
correct and
s_st_arr2(highb,false) =
c_st_arr2_2(highb,false) and
(s_st_arr2_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00387" ,
"One inertial transaction occurred on a " &
"concurrent signal asg",
correct ) ;
st_arr2_select <= transport 6 ;
-- Last transaction above is marked
-- s_st_arr2(highb,false) <=
-- c_st_arr2_1(highb,false) after 40 ns ;
--
when 7
=> correct :=
correct and
s_st_arr2(highb,false) =
c_st_arr2_1(highb,false) and
(s_st_arr2_savt + 30 ns) = Std.Standard.Now ;
--
when 8
=> correct :=
correct and
s_st_arr2(highb,false) =
c_st_arr2_1(highb,false) and
(s_st_arr2_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00387" ,
"Inertial semantics check on a concurrent " &
"signal asg",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00387" ,
"Inertial semantics check on a concurrent " &
"signal asg",
false ) ;
--
end case ;
--
s_st_arr2_savt <= transport Std.Standard.Now ;
chk_st_arr2 <= transport s_st_arr2_cnt
after (1 us - Std.Standard.Now) ;
s_st_arr2_cnt <= transport s_st_arr2_cnt + 1 ;
wait until (not s_st_arr2(highb,false)'Quiet) and
(s_st_arr2_savt /= Std.Standard.Now) ;
--
end process CHG10 ;
--
PGEN_CHKP_10 :
process ( chk_st_arr2 )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P10" ,
"Inertial transactions completed entirely",
chk_st_arr2 = 8 ) ;
end if ;
end process PGEN_CHKP_10 ;
--
--
with st_arr2_select select
s_st_arr2(highb,false) <=
c_st_arr2_2(highb,false) after 10 ns,
c_st_arr2_1(highb,false) after 20 ns
when 1,
--
c_st_arr2_2(highb,false) after 10 ns ,
c_st_arr2_1(highb,false) after 20 ns ,
c_st_arr2_2(highb,false) after 30 ns ,
c_st_arr2_1(highb,false) after 40 ns
when 2,
--
c_st_arr2_1(highb,false) after 5 ns
when 3,
--
c_st_arr2_1(highb,false) after 100 ns
when 4,
--
c_st_arr2_2(highb,false) after 10 ns ,
c_st_arr2_1(highb,false) after 20 ns ,
c_st_arr2_2(highb,false) after 30 ns ,
c_st_arr2_1(highb,false) after 40 ns
when 5,
--
-- Last transaction above is marked
c_st_arr2_1(highb,false) after 40 ns when 6 ;
--
end ARCH00387 ;
--
--
use WORK.STANDARD_TYPES.all ;
entity ENT00387_Test_Bench is
signal s_st_boolean_vector : st_boolean_vector
:= c_st_boolean_vector_1 ;
signal s_st_severity_level_vector : st_severity_level_vector
:= c_st_severity_level_vector_1 ;
signal s_st_string : st_string
:= c_st_string_1 ;
signal s_st_enum1_vector : st_enum1_vector
:= c_st_enum1_vector_1 ;
signal s_st_integer_vector : st_integer_vector
:= c_st_integer_vector_1 ;
signal s_st_time_vector : st_time_vector
:= c_st_time_vector_1 ;
signal s_st_real_vector : st_real_vector
:= c_st_real_vector_1 ;
signal s_st_rec1_vector : st_rec1_vector
:= c_st_rec1_vector_1 ;
signal s_st_arr2_vector : st_arr2_vector
:= c_st_arr2_vector_1 ;
signal s_st_arr2 : st_arr2
:= c_st_arr2_1 ;
--
end ENT00387_Test_Bench ;
--
--
architecture ARCH00387_Test_Bench of ENT00387_Test_Bench is
begin
L1:
block
component UUT
port (
s_st_boolean_vector : inout st_boolean_vector
; s_st_severity_level_vector : inout st_severity_level_vector
; s_st_string : inout st_string
; s_st_enum1_vector : inout st_enum1_vector
; s_st_integer_vector : inout st_integer_vector
; s_st_time_vector : inout st_time_vector
; s_st_real_vector : inout st_real_vector
; s_st_rec1_vector : inout st_rec1_vector
; s_st_arr2_vector : inout st_arr2_vector
; s_st_arr2 : inout st_arr2
) ;
end component ;
--
for CIS1 : UUT use entity WORK.ENT00387 ( ARCH00387 ) ;
begin
CIS1 : UUT
port map (
s_st_boolean_vector
, s_st_severity_level_vector
, s_st_string
, s_st_enum1_vector
, s_st_integer_vector
, s_st_time_vector
, s_st_real_vector
, s_st_rec1_vector
, s_st_arr2_vector
, s_st_arr2
)
;
end block L1 ;
end ARCH00387_Test_Bench ;
| gpl-3.0 | bf9fa80201a54dc693fcba5345bbad7a | 0.510474 | 3.526797 | false | false | false | false |
EpicFailv2/open-source-repo | Embedded Systems/witFreqSwitching.vhd | 1 | 2,363 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity IESigGen is
Port (
CLOCK_50 : IN STD_LOGIC;
SW : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
KEY : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
HEX0 : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
HEX1 : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
HEX2 : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
HEX3 : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
LEDG : OUT STD_LOGIC_VECTOR(9 downto 0);
GPIO_0 : OUT STD_LOGIC_VECTOR(2 DOWNTO 0)
);
end IESigGen;
architecture Whatever of IESigGen is
constant timer_max : INTEGER := 50000000;
signal timer_count : INTEGER := 0;
signal led_state : STD_LOGIC := '0';
signal counter : INTEGER := 0;
SIGNAL FREQUENCY : INTEGER := 0;
signal INTERVAL : INTEGER := 0;
begin
WITH FREQUENCY mod 10 SELECT HEX0 <=
"11000000" WHEN 0,
"11111001" WHEN 1,
"10100100" WHEN 2,
"10110000" WHEN 3,
"10011001" WHEN 4,
"10010010" WHEN 5,
"10000010" WHEN 6,
"11111000" WHEN 7,
"10000000" WHEN 8,
"10010000" WHEN 9,
"01111111" WHEN OTHERS;
WITH (FREQUENCY / 10) mod 10 SELECT HEX1 <=
"11000000" WHEN 0,
"11111001" WHEN 1,
"10100100" WHEN 2,
"10110000" WHEN 3,
"10011001" WHEN 4,
"10010010" WHEN 5,
"10000010" WHEN 6,
"11111000" WHEN 7,
"10000000" WHEN 8,
"10010000" WHEN 9,
"01111111" WHEN OTHERS;
WITH (FREQUENCY / 100) mod 10 SELECT HEX2 <=
"01000000" WHEN 0,
"01111001" WHEN 1,
"00100100" WHEN 2,
"00110000" WHEN 3,
"00011001" WHEN 4,
"00010010" WHEN 5,
"00000010" WHEN 6,
"01111000" WHEN 7,
"00000000" WHEN 8,
"00010000" WHEN 9,
"01111111" WHEN OTHERS;
WITH (FREQUENCY / 1000) mod 10 SELECT HEX3 <=
"11000000" WHEN 0,
"11111001" WHEN 1,
"10100100" WHEN 2,
"10110000" WHEN 3,
"10011001" WHEN 4,
"10010010" WHEN 5,
"10000010" WHEN 6,
"11111000" WHEN 7,
"10000000" WHEN 8,
"10010000" WHEN 9,
"01111111" WHEN OTHERS;
WITH COUNTER MOD 2 SELECT GPIO_0 <=
"001" WHEN 0,
"000" WHEN OTHERS;
process(CLOCK_50)
begin
if rising_edge(CLOCK_50) then
timer_count <= timer_count + 1;
if (timer_count >= INTERVAL) then
led_state <= not led_state;
counter <= counter + 1;
timer_count <= 0;
end if;
INTERVAL <= TO_INTEGER(UNSIGNED(SW));
FREQUENCY <= 5000/((INTERVAL+1)*2);
end if;
end process;
LEDG(0) <= led_state;
LEDG(1) <= KEY(1);
end Whatever;
| mit | fcb94f4f290a6f98d8a75a10afdd090a | 0.636902 | 2.813095 | false | false | false | false |
grwlf/vsim | vhdl/IEEE/old/numeric_bit.vhd | 1 | 87,293 | -- -----------------------------------------------------------------------------
--
-- Copyright 1995 by IEEE. All rights reserved.
--
-- This source file is considered by the IEEE to be an essential part of the use
-- of the standard 1076.3 and as such may be distributed without change, except
-- as permitted by the standard. This source file may not be sold or distributed
-- for profit. This package may be modified to include additional data required
-- by tools, but must in no way change the external interfaces or simulation
-- behaviour of the description. It is permissible to add comments and/or
-- attributes to the package declarations, but not to change or delete any
-- original lines of the approved package declaration. The package body may be
-- changed only in accordance with the terms of clauses 7.1 and 7.2 of the
-- standard.
--
-- Title : Standard VHDL Synthesis Package (1076.3, NUMERIC_BIT)
--
-- Library : This package shall be compiled into a library symbolically
-- : named IEEE.
--
-- Developers : IEEE DASC Synthesis Working Group, PAR 1076.3
--
-- Purpose : This package defines numeric types and arithmetic functions
-- : for use with synthesis tools. Two numeric types are defined:
-- : -- > UNSIGNED: represents an UNSIGNED number in vector form
-- : -- > SIGNED: represents a SIGNED number in vector form
-- : The base element type is type BIT.
-- : The leftmost bit is treated as the most significant bit.
-- : Signed vectors are represented in two's complement form.
-- : This package contains overloaded arithmetic operators on
-- : the SIGNED and UNSIGNED types. The package also contains
-- : useful type conversions functions, clock detection
-- : functions, and other utility functions.
-- :
-- : If any argument to a function is a null array, a null array is
-- : returned (exceptions, if any, are noted individually).
--
-- Limitation :
--
-- Note : No declarations or definitions shall be included in,
-- : or excluded from this package. The "package declaration"
-- : defines the types, subtypes and declarations of
-- : NUMERIC_BIT. The NUMERIC_BIT package body shall be
-- : considered the formal definition of the semantics of
-- : this package. Tool developers may choose to implement
-- : the package body in the most efficient manner available
-- : to them.
-- :
-- -----------------------------------------------------------------------------
-- Version : 2.4
-- Date : 12 April 1995
-- -----------------------------------------------------------------------------
package NUMERIC_BIT is
constant CopyRightNotice: STRING
:= "Copyright 1995 IEEE. All rights reserved.";
--============================================================================
-- Numeric array type definitions
--============================================================================
type UNSIGNED is array (NATURAL range <> ) of BIT;
type SIGNED is array (NATURAL range <> ) of BIT;
--============================================================================
-- Arithmetic Operators:
--============================================================================
-- Id: A.1
function "abs" (ARG: SIGNED) return SIGNED;
-- Result subtype: SIGNED(ARG'LENGTH-1 downto 0).
-- Result: Returns the absolute value of a SIGNED vector ARG.
-- Id: A.2
function "-" (ARG: SIGNED) return SIGNED;
-- Result subtype: SIGNED(ARG'LENGTH-1 downto 0).
-- Result: Returns the value of the unary minus operation on a
-- SIGNED vector ARG.
--============================================================================
-- Id: A.3
function "+" (L, R: UNSIGNED) return UNSIGNED;
-- Result subtype: UNSIGNED(MAX(L'LENGTH, R'LENGTH)-1 downto 0).
-- Result: Adds two UNSIGNED vectors that may be of different lengths.
-- Id: A.4
function "+" (L, R: SIGNED) return SIGNED;
-- Result subtype: SIGNED(MAX(L'LENGTH, R'LENGTH)-1 downto 0).
-- Result: Adds two SIGNED vectors that may be of different lengths.
-- Id: A.5
function "+" (L: UNSIGNED; R: NATURAL) return UNSIGNED;
-- Result subtype: UNSIGNED(L'LENGTH-1 downto 0).
-- Result: Adds an UNSIGNED vector, L, with a non-negative INTEGER, R.
-- Id: A.6
function "+" (L: NATURAL; R: UNSIGNED) return UNSIGNED;
-- Result subtype: UNSIGNED(R'LENGTH-1 downto 0).
-- Result: Adds a non-negative INTEGER, L, with an UNSIGNED vector, R.
-- Id: A.7
function "+" (L: INTEGER; R: SIGNED) return SIGNED;
-- Result subtype: SIGNED(R'LENGTH-1 downto 0).
-- Result: Adds an INTEGER, L(may be positive or negative), to a SIGNED
-- vector, R.
-- Id: A.8
function "+" (L: SIGNED; R: INTEGER) return SIGNED;
-- Result subtype: SIGNED(L'LENGTH-1 downto 0).
-- Result: Adds a SIGNED vector, L, to an INTEGER, R.
--============================================================================
-- Id: A.9
function "-" (L, R: UNSIGNED) return UNSIGNED;
-- Result subtype: UNSIGNED(MAX(L'LENGTH, R'LENGTH)-1 downto 0).
-- Result: Subtracts two UNSIGNED vectors that may be of different lengths.
-- Id: A.10
function "-" (L, R: SIGNED) return SIGNED;
-- Result subtype: SIGNED(MAX(L'LENGTH, R'LENGTH)-1 downto 0).
-- Result: Subtracts a SIGNED vector, R, from another SIGNED vector, L,
-- that may possibly be of different lengths.
-- Id: A.11
function "-" (L: UNSIGNED; R: NATURAL) return UNSIGNED;
-- Result subtype: UNSIGNED(L'LENGTH-1 downto 0).
-- Result: Subtracts a non-negative INTEGER, R, from an UNSIGNED vector, L.
-- Id: A.12
function "-" (L: NATURAL; R: UNSIGNED) return UNSIGNED;
-- Result subtype: UNSIGNED(R'LENGTH-1 downto 0).
-- Result: Subtracts an UNSIGNED vector, R, from a non-negative INTEGER, L.
-- Id: A.13
function "-" (L: SIGNED; R: INTEGER) return SIGNED;
-- Result subtype: SIGNED(L'LENGTH-1 downto 0).
-- Result: Subtracts an INTEGER, R, from a SIGNED vector, L.
-- Id: A.14
function "-" (L: INTEGER; R: SIGNED) return SIGNED;
-- Result subtype: SIGNED(R'LENGTH-1 downto 0).
-- Result: Subtracts a SIGNED vector, R, from an INTEGER, L.
--============================================================================
-- Id: A.15
function "*" (L, R: UNSIGNED) return UNSIGNED;
-- Result subtype: UNSIGNED((L'LENGTH+R'LENGTH-1) downto 0).
-- Result: Performs the multiplication operation on two UNSIGNED vectors
-- that may possibly be of different lengths.
-- Id: A.16
function "*" (L, R: SIGNED) return SIGNED;
-- Result subtype: SIGNED((L'LENGTH+R'LENGTH-1) downto 0)
-- Result: Multiplies two SIGNED vectors that may possibly be of
-- different lengths.
-- Id: A.17
function "*" (L: UNSIGNED; R: NATURAL) return UNSIGNED;
-- Result subtype: UNSIGNED((L'LENGTH+L'LENGTH-1) downto 0).
-- Result: Multiplies an UNSIGNED vector, L, with a non-negative
-- INTEGER, R. R is converted to an UNSIGNED vector of
-- size L'LENGTH before multiplication.
-- Id: A.18
function "*" (L: NATURAL; R: UNSIGNED) return UNSIGNED;
-- Result subtype: UNSIGNED((R'LENGTH+R'LENGTH-1) downto 0).
-- Result: Multiplies an UNSIGNED vector, R, with a non-negative
-- INTEGER, L. L is converted to an UNSIGNED vector of
-- size R'LENGTH before multiplication.
-- Id: A.19
function "*" (L: SIGNED; R: INTEGER) return SIGNED;
-- Result subtype: SIGNED((L'LENGTH+L'LENGTH-1) downto 0)
-- Result: Multiplies a SIGNED vector, L, with an INTEGER, R. R is
-- converted to a SIGNED vector of size L'LENGTH before
-- multiplication.
-- Id: A.20
function "*" (L: INTEGER; R: SIGNED) return SIGNED;
-- Result subtype: SIGNED((R'LENGTH+R'LENGTH-1) downto 0)
-- Result: Multiplies a SIGNED vector, R, with an INTEGER, L. L is
-- converted to a SIGNED vector of size R'LENGTH before
-- multiplication.
--============================================================================
--
-- NOTE: If second argument is zero for "/" operator, a severity level
-- of ERROR is issued.
-- Id: A.21
function "/" (L, R: UNSIGNED) return UNSIGNED;
-- Result subtype: UNSIGNED(L'LENGTH-1 downto 0)
-- Result: Divides an UNSIGNED vector, L, by another UNSIGNED vector, R.
-- Id: A.22
function "/" (L, R: SIGNED) return SIGNED;
-- Result subtype: SIGNED(L'LENGTH-1 downto 0)
-- Result: Divides an SIGNED vector, L, by another SIGNED vector, R.
-- Id: A.23
function "/" (L: UNSIGNED; R: NATURAL) return UNSIGNED;
-- Result subtype: UNSIGNED(L'LENGTH-1 downto 0)
-- Result: Divides an UNSIGNED vector, L, by a non-negative INTEGER, R.
-- If NO_OF_BITS(R) > L'LENGTH, result is truncated to L'LENGTH.
-- Id: A.24
function "/" (L: NATURAL; R: UNSIGNED) return UNSIGNED;
-- Result subtype: UNSIGNED(R'LENGTH-1 downto 0)
-- Result: Divides a non-negative INTEGER, L, by an UNSIGNED vector, R.
-- If NO_OF_BITS(L) > R'LENGTH, result is truncated to R'LENGTH.
-- Id: A.25
function "/" (L: SIGNED; R: INTEGER) return SIGNED;
-- Result subtype: SIGNED(L'LENGTH-1 downto 0)
-- Result: Divides a SIGNED vector, L, by an INTEGER, R.
-- If NO_OF_BITS(R) > L'LENGTH, result is truncated to L'LENGTH.
-- Id: A.26
function "/" (L: INTEGER; R: SIGNED) return SIGNED;
-- Result subtype: SIGNED(R'LENGTH-1 downto 0)
-- Result: Divides an INTEGER, L, by a SIGNED vector, R.
-- If NO_OF_BITS(L) > R'LENGTH, result is truncated to R'LENGTH.
--============================================================================
--
-- NOTE: If second argument is zero for "rem" operator, a severity level
-- of ERROR is issued.
-- Id: A.27
function "rem" (L, R: UNSIGNED) return UNSIGNED;
-- Result subtype: UNSIGNED(R'LENGTH-1 downto 0)
-- Result: Computes "L rem R" where L and R are UNSIGNED vectors.
-- Id: A.28
function "rem" (L, R: SIGNED) return SIGNED;
-- Result subtype: SIGNED(R'LENGTH-1 downto 0)
-- Result: Computes "L rem R" where L and R are SIGNED vectors.
-- Id: A.29
function "rem" (L: UNSIGNED; R: NATURAL) return UNSIGNED;
-- Result subtype: UNSIGNED(L'LENGTH-1 downto 0)
-- Result: Computes "L rem R" where L is an UNSIGNED vector and R is a
-- non-negative INTEGER.
-- If NO_OF_BITS(R) > L'LENGTH, result is truncated to L'LENGTH.
-- Id: A.30
function "rem" (L: NATURAL; R: UNSIGNED) return UNSIGNED;
-- Result subtype: UNSIGNED(R'LENGTH-1 downto 0)
-- Result: Computes "L rem R" where R is an UNSIGNED vector and L is a
-- non-negative INTEGER.
-- If NO_OF_BITS(L) > R'LENGTH, result is truncated to R'LENGTH.
-- Id: A.31
function "rem" (L: SIGNED; R: INTEGER) return SIGNED;
-- Result subtype: SIGNED(L'LENGTH-1 downto 0)
-- Result: Computes "L rem R" where L is SIGNED vector and R is an INTEGER.
-- If NO_OF_BITS(R) > L'LENGTH, result is truncated to L'LENGTH.
-- Id: A.32
function "rem" (L: INTEGER; R: SIGNED) return SIGNED;
-- Result subtype: SIGNED(R'LENGTH-1 downto 0)
-- Result: Computes "L rem R" where R is SIGNED vector and L is an INTEGER.
-- If NO_OF_BITS(L) > R'LENGTH, result is truncated to R'LENGTH.
--============================================================================
--
-- NOTE: If second argument is zero for "mod" operator, a severity level
-- of ERROR is issued.
-- Id: A.33
function "mod" (L, R: UNSIGNED) return UNSIGNED;
-- Result subtype: UNSIGNED(R'LENGTH-1 downto 0)
-- Result: Computes "L mod R" where L and R are UNSIGNED vectors.
-- Id: A.34
function "mod" (L, R: SIGNED) return SIGNED;
-- Result subtype: SIGNED(R'LENGTH-1 downto 0)
-- Result: Computes "L mod R" where L and R are SIGNED vectors.
-- Id: A.35
function "mod" (L: UNSIGNED; R: NATURAL) return UNSIGNED;
-- Result subtype: UNSIGNED(L'LENGTH-1 downto 0)
-- Result: Computes "L mod R" where L is an UNSIGNED vector and R
-- is a non-negative INTEGER.
-- If NO_OF_BITS(R) > L'LENGTH, result is truncated to L'LENGTH.
-- Id: A.36
function "mod" (L: NATURAL; R: UNSIGNED) return UNSIGNED;
-- Result subtype: UNSIGNED(R'LENGTH-1 downto 0)
-- Result: Computes "L mod R" where R is an UNSIGNED vector and L
-- is a non-negative INTEGER.
-- If NO_OF_BITS(L) > R'LENGTH, result is truncated to R'LENGTH.
-- Id: A.37
function "mod" (L: SIGNED; R: INTEGER) return SIGNED;
-- Result subtype: SIGNED(L'LENGTH-1 downto 0)
-- Result: Computes "L mod R" where L is a SIGNED vector and
-- R is an INTEGER.
-- If NO_OF_BITS(R) > L'LENGTH, result is truncated to L'LENGTH.
-- Id: A.38
function "mod" (L: INTEGER; R: SIGNED) return SIGNED;
-- Result subtype: SIGNED(R'LENGTH-1 downto 0)
-- Result: Computes "L mod R" where L is an INTEGER and
-- R is a SIGNED vector.
-- If NO_OF_BITS(L) > R'LENGTH, result is truncated to R'LENGTH.
--============================================================================
-- Comparison Operators
--============================================================================
-- Id: C.1
function ">" (L, R: UNSIGNED) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L > R" where L and R are UNSIGNED vectors possibly
-- of different lengths.
-- Id: C.2
function ">" (L, R: SIGNED) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L > R" where L and R are SIGNED vectors possibly
-- of different lengths.
-- Id: C.3
function ">" (L: NATURAL; R: UNSIGNED) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L > R" where L is a non-negative INTEGER and
-- R is an UNSIGNED vector.
-- Id: C.4
function ">" (L: INTEGER; R: SIGNED) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L > R" where L is a INTEGER and
-- R is a SIGNED vector.
-- Id: C.5
function ">" (L: UNSIGNED; R: NATURAL) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L > R" where L is an UNSIGNED vector and
-- R is a non-negative INTEGER.
-- Id: C.6
function ">" (L: SIGNED; R: INTEGER) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L > R" where L is a SIGNED vector and
-- R is a INTEGER.
--============================================================================
-- Id: C.7
function "<" (L, R: UNSIGNED) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L < R" where L and R are UNSIGNED vectors possibly
-- of different lengths.
-- Id: C.8
function "<" (L, R: SIGNED) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L < R" where L and R are SIGNED vectors possibly
-- of different lengths.
-- Id: C.9
function "<" (L: NATURAL; R: UNSIGNED) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L < R" where L is a non-negative INTEGER and
-- R is an UNSIGNED vector.
-- Id: C.10
function "<" (L: INTEGER; R: SIGNED) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L < R" where L is an INTEGER and
-- R is a SIGNED vector.
-- Id: C.11
function "<" (L: UNSIGNED; R: NATURAL) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L < R" where L is an UNSIGNED vector and
-- R is a non-negative INTEGER.
-- Id: C.12
function "<" (L: SIGNED; R: INTEGER) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L < R" where L is a SIGNED vector and
-- R is an INTEGER.
--============================================================================
-- Id: C.13
function "<=" (L, R: UNSIGNED) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L <= R" where L and R are UNSIGNED vectors possibly
-- of different lengths.
-- Id: C.14
function "<=" (L, R: SIGNED) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L <= R" where L and R are SIGNED vectors possibly
-- of different lengths.
-- Id: C.15
function "<=" (L: NATURAL; R: UNSIGNED) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L <= R" where L is a non-negative INTEGER and
-- R is an UNSIGNED vector.
-- Id: C.16
function "<=" (L: INTEGER; R: SIGNED) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L <= R" where L is an INTEGER and
-- R is a SIGNED vector.
-- Id: C.17
function "<=" (L: UNSIGNED; R: NATURAL) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L <= R" where L is an UNSIGNED vector and
-- R is a non-negative INTEGER.
-- Id: C.18
function "<=" (L: SIGNED; R: INTEGER) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L <= R" where L is a SIGNED vector and
-- R is an INTEGER.
--============================================================================
-- Id: C.19
function ">=" (L, R: UNSIGNED) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L >= R" where L and R are UNSIGNED vectors possibly
-- of different lengths.
-- Id: C.20
function ">=" (L, R: SIGNED) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L >= R" where L and R are SIGNED vectors possibly
-- of different lengths.
-- Id: C.21
function ">=" (L: NATURAL; R: UNSIGNED) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L >= R" where L is a non-negative INTEGER and
-- R is an UNSIGNED vector.
-- Id: C.22
function ">=" (L: INTEGER; R: SIGNED) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L >= R" where L is an INTEGER and
-- R is a SIGNED vector.
-- Id: C.23
function ">=" (L: UNSIGNED; R: NATURAL) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L >= R" where L is an UNSIGNED vector and
-- R is a non-negative INTEGER.
-- Id: C.24
function ">=" (L: SIGNED; R: INTEGER) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L >= R" where L is a SIGNED vector and
-- R is an INTEGER.
--============================================================================
-- Id: C.25
function "=" (L, R: UNSIGNED) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L = R" where L and R are UNSIGNED vectors possibly
-- of different lengths.
-- Id: C.26
function "=" (L, R: SIGNED) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L = R" where L and R are SIGNED vectors possibly
-- of different lengths.
-- Id: C.27
function "=" (L: NATURAL; R: UNSIGNED) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L = R" where L is a non-negative INTEGER and
-- R is an UNSIGNED vector.
-- Id: C.28
function "=" (L: INTEGER; R: SIGNED) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L = R" where L is an INTEGER and
-- R is a SIGNED vector.
-- Id: C.29
function "=" (L: UNSIGNED; R: NATURAL) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L = R" where L is an UNSIGNED vector and
-- R is a non-negative INTEGER.
-- Id: C.30
function "=" (L: SIGNED; R: INTEGER) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L = R" where L is a SIGNED vector and
-- R is an INTEGER.
--============================================================================
-- Id: C.31
function "/=" (L, R: UNSIGNED) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L /= R" where L and R are UNSIGNED vectors possibly
-- of different lengths.
-- Id: C.32
function "/=" (L, R: SIGNED) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L /= R" where L and R are SIGNED vectors possibly
-- of different lengths.
-- Id: C.33
function "/=" (L: NATURAL; R: UNSIGNED) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L /= R" where L is a non-negative INTEGER and
-- R is an UNSIGNED vector.
-- Id: C.34
function "/=" (L: INTEGER; R: SIGNED) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L /= R" where L is an INTEGER and
-- R is a SIGNED vector.
-- Id: C.35
function "/=" (L: UNSIGNED; R: NATURAL) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L /= R" where L is an UNSIGNED vector and
-- R is a non-negative INTEGER.
-- Id: C.36
function "/=" (L: SIGNED; R: INTEGER) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L /= R" where L is a SIGNED vector and
-- R is an INTEGER.
--============================================================================
-- Shift and Rotate Functions
--============================================================================
-- Id: S.1
function SHIFT_LEFT (ARG: UNSIGNED; COUNT: NATURAL) return UNSIGNED;
-- Result subtype: UNSIGNED(ARG'LENGTH-1 downto 0)
-- Result: Performs a shift-left on an UNSIGNED vector COUNT times.
-- The vacated positions are filled with Bit '0'.
-- The COUNT leftmost bits are lost.
-- Id: S.2
function SHIFT_RIGHT (ARG: UNSIGNED; COUNT: NATURAL) return UNSIGNED;
-- Result subtype: UNSIGNED(ARG'LENGTH-1 downto 0)
-- Result: Performs a shift-right on an UNSIGNED vector COUNT times.
-- The vacated positions are filled with Bit '0'.
-- The COUNT rightmost bits are lost.
-- Id: S.3
function SHIFT_LEFT (ARG: SIGNED; COUNT: NATURAL) return SIGNED;
-- Result subtype: SIGNED(ARG'LENGTH-1 downto 0)
-- Result: Performs a shift-left on a SIGNED vector COUNT times.
-- The vacated positions are filled with Bit '0'.
-- The COUNT leftmost bits, except ARG'LEFT, are lost.
-- Id: S.4
function SHIFT_RIGHT (ARG: SIGNED; COUNT: NATURAL) return SIGNED;
-- Result subtype: SIGNED(ARG'LENGTH-1 downto 0)
-- Result: Performs a shift-right on a SIGNED vector COUNT times.
-- The vacated positions are filled with the leftmost bit, ARG'LEFT.
-- The COUNT rightmost bits are lost.
--============================================================================
-- Id: S.5
function ROTATE_LEFT (ARG: UNSIGNED; COUNT: NATURAL) return UNSIGNED;
-- Result subtype: UNSIGNED(ARG'LENGTH-1 downto 0)
-- Result: Performs a rotate-left of an UNSIGNED vector COUNT times.
-- Id: S.6
function ROTATE_RIGHT (ARG: UNSIGNED; COUNT: NATURAL) return UNSIGNED;
-- Result subtype: UNSIGNED(ARG'LENGTH-1 downto 0)
-- Result: Performs a rotate-right of an UNSIGNED vector COUNT times.
-- Id: S.7
function ROTATE_LEFT (ARG: SIGNED; COUNT: NATURAL) return SIGNED;
-- Result subtype: SIGNED(ARG'LENGTH-1 downto 0)
-- Result: Performs a logical rotate-left of a SIGNED vector COUNT times.
-- Id: S.8
function ROTATE_RIGHT (ARG: SIGNED; COUNT: NATURAL) return SIGNED;
-- Result subtype: SIGNED(ARG'LENGTH-1 downto 0)
-- Result: Performs a logical rotate-right of a SIGNED vector COUNT times.
--============================================================================
------------------------------------------------------------------------------
-- Note : Function S.9 is not compatible with VHDL 1076-1987. Comment
-- out the function (declaration and body) for VHDL 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: S.9
function "sll" (ARG: UNSIGNED; COUNT: INTEGER) return UNSIGNED;
-- Result subtype: UNSIGNED(ARG'LENGTH-1 downto 0)
-- Result: SHIFT_LEFT(ARG, COUNT)
------------------------------------------------------------------------------
-- Note : Function S.10 is not compatible with VHDL 1076-1987. Comment
-- out the function (declaration and body) for VHDL 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: S.10
function "sll" (ARG: SIGNED; COUNT: INTEGER) return SIGNED;
-- Result subtype: SIGNED(ARG'LENGTH-1 downto 0)
-- Result: SHIFT_LEFT(ARG, COUNT)
------------------------------------------------------------------------------
-- Note : Function S.11 is not compatible with VHDL 1076-1987. Comment
-- out the function (declaration and body) for VHDL 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: S.11
function "srl" (ARG: UNSIGNED; COUNT: INTEGER) return UNSIGNED;
-- Result subtype: UNSIGNED(ARG'LENGTH-1 downto 0)
-- Result: SHIFT_RIGHT(ARG, COUNT)
------------------------------------------------------------------------------
-- Note : Function S.12 is not compatible with VHDL 1076-1987. Comment
-- out the function (declaration and body) for VHDL 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: S.12
function "srl" (ARG: SIGNED; COUNT: INTEGER) return SIGNED;
-- Result subtype: SIGNED(ARG'LENGTH-1 downto 0)
-- Result: SIGNED(SHIFT_RIGHT(UNSIGNED(ARG), COUNT))
------------------------------------------------------------------------------
-- Note : Function S.13 is not compatible with VHDL 1076-1987. Comment
-- out the function (declaration and body) for VHDL 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: S.13
function "rol" (ARG: UNSIGNED; COUNT: INTEGER) return UNSIGNED;
-- Result subtype: UNSIGNED(ARG'LENGTH-1 downto 0)
-- Result: ROTATE_LEFT(ARG, COUNT)
------------------------------------------------------------------------------
-- Note : Function S.14 is not compatible with VHDL 1076-1987. Comment
-- out the function (declaration and body) for VHDL 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: S.14
function "rol" (ARG: SIGNED; COUNT: INTEGER) return SIGNED;
-- Result subtype: SIGNED(ARG'LENGTH-1 downto 0)
-- Result: ROTATE_LEFT(ARG, COUNT)
------------------------------------------------------------------------------
-- Note : Function S.15 is not compatible with VHDL 1076-1987. Comment
-- out the function (declaration and body) for VHDL 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: S.15
function "ror" (ARG: UNSIGNED; COUNT: INTEGER) return UNSIGNED;
-- Result subtype: UNSIGNED(ARG'LENGTH-1 downto 0)
-- Result: ROTATE_RIGHT(ARG, COUNT)
------------------------------------------------------------------------------
-- Note : Function S.16 is not compatible with VHDL 1076-1987. Comment
-- out the function (declaration and body) for VHDL 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: S.16
function "ror" (ARG: SIGNED; COUNT: INTEGER) return SIGNED;
-- Result subtype: SIGNED(ARG'LENGTH-1 downto 0)
-- Result: ROTATE_RIGHT(ARG, COUNT)
--============================================================================
-- RESIZE Functions
--============================================================================
-- Id: R.1
function RESIZE (ARG: SIGNED; NEW_SIZE: NATURAL) return SIGNED;
-- Result subtype: SIGNED(NEW_SIZE-1 downto 0)
-- Result: Resizes the SIGNED vector ARG to the specified size.
-- To create a larger vector, the new [leftmost] bit positions
-- are filled with the sign bit (ARG'LEFT). When truncating,
-- the sign bit is retained along with the rightmost part.
-- Id: R.2
function RESIZE (ARG: UNSIGNED; NEW_SIZE: NATURAL) return UNSIGNED;
-- Result subtype: UNSIGNED(NEW_SIZE-1 downto 0)
-- Result: Resizes the UNSIGNED vector ARG to the specified size.
-- To create a larger vector, the new [leftmost] bit positions
-- are filled with '0'. When truncating, the leftmost bits
-- are dropped.
--============================================================================
-- Conversion Functions
--============================================================================
-- Id: D.1
function TO_INTEGER (ARG: UNSIGNED) return NATURAL;
-- Result subtype: NATURAL. Value cannot be negative since parameter is an
-- UNSIGNED vector.
-- Result: Converts the UNSIGNED vector to an INTEGER.
-- Id: D.2
function TO_INTEGER (ARG: SIGNED) return INTEGER;
-- Result subtype: INTEGER
-- Result: Converts a SIGNED vector to an INTEGER.
-- Id: D.3
function TO_UNSIGNED (ARG, SIZE: NATURAL) return UNSIGNED;
-- Result subtype: UNSIGNED(SIZE-1 downto 0)
-- Result: Converts a non-negative INTEGER to an UNSIGNED vector with
-- the specified size.
-- Id: D.4
function TO_SIGNED (ARG: INTEGER; SIZE: NATURAL) return SIGNED;
-- Result subtype: SIGNED(SIZE-1 downto 0)
-- Result: Converts an INTEGER to a SIGNED vector of the specified size.
--============================================================================
-- Logical Operators
--============================================================================
-- Id: L.1
function "not" (L: UNSIGNED) return UNSIGNED;
-- Result subtype: UNSIGNED(L'LENGTH-1 downto 0)
-- Result: Termwise inversion
-- Id: L.2
function "and" (L, R: UNSIGNED) return UNSIGNED;
-- Result subtype: UNSIGNED(L'LENGTH-1 downto 0)
-- Result: Vector AND operation
-- Id: L.3
function "or" (L, R: UNSIGNED) return UNSIGNED;
-- Result subtype: UNSIGNED(L'LENGTH-1 downto 0)
-- Result: Vector OR operation
-- Id: L.4
function "nand" (L, R: UNSIGNED) return UNSIGNED;
-- Result subtype: UNSIGNED(L'LENGTH-1 downto 0)
-- Result: Vector NAND operation
-- Id: L.5
function "nor" (L, R: UNSIGNED) return UNSIGNED;
-- Result subtype: UNSIGNED(L'LENGTH-1 downto 0)
-- Result: Vector NOR operation
-- Id: L.6
function "xor" (L, R: UNSIGNED) return UNSIGNED;
-- Result subtype: UNSIGNED(L'LENGTH-1 downto 0)
-- Result: Vector XOR operation
------------------------------------------------------------------------------
-- Note : Function L.7 is not compatible with VHDL 1076-1987. Comment
-- out the function (declaration and body) for VHDL 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: L.7
function "xnor" (L, R: UNSIGNED) return UNSIGNED;
-- Result subtype: UNSIGNED(L'LENGTH-1 downto 0)
-- Result: Vector XNOR operation
-- Id: L.8
function "not" (L: SIGNED) return SIGNED;
-- Result subtype: SIGNED(L'LENGTH-1 downto 0)
-- Result: Termwise inversion
-- Id: L.9
function "and" (L, R: SIGNED) return SIGNED;
-- Result subtype: SIGNED(L'LENGTH-1 downto 0)
-- Result: Vector AND operation
-- Id: L.10
function "or" (L, R: SIGNED) return SIGNED;
-- Result subtype: SIGNED(L'LENGTH-1 downto 0)
-- Result: Vector OR operation
-- Id: L.11
function "nand" (L, R: SIGNED) return SIGNED;
-- Result subtype: SIGNED(L'LENGTH-1 downto 0)
-- Result: Vector NAND operation
-- Id: L.12
function "nor" (L, R: SIGNED) return SIGNED;
-- Result subtype: SIGNED(L'LENGTH-1 downto 0)
-- Result: Vector NOR operation
-- Id: L.13
function "xor" (L, R: SIGNED) return SIGNED;
-- Result subtype: SIGNED(L'LENGTH-1 downto 0)
-- Result: Vector XOR operation
------------------------------------------------------------------------------
-- Note : Function L.14 is not compatible with VHDL 1076-1987. Comment
-- out the function (declaration and body) for VHDL 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: L.14
function "xnor" (L, R: SIGNED) return SIGNED;
-- Result subtype: SIGNED(L'LENGTH-1 downto 0)
-- Result: Vector XNOR operation
--============================================================================
-- Edge Detection Functions
--============================================================================
-- Id: E.1
function RISING_EDGE (signal S: BIT) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Returns TRUE if an event is detected on signal S and the
-- value changed from a '0' to a '1'.
-- Id: E.2
function FALLING_EDGE (signal S: BIT) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Returns TRUE if an event is detected on signal S and the
-- value changed from a '1' to a '0'.
end NUMERIC_BIT;
--==============================================================================
--======================= Package Body =========================================
--==============================================================================
package body NUMERIC_BIT is
-- null range array constants
constant NAU: UNSIGNED(0 downto 1) := (others => '0');
constant NAS: SIGNED(0 downto 1) := (others => '0');
-- implementation controls
constant NO_WARNING: BOOLEAN := FALSE; -- default to emit warnings
--=========================Local Subprograms =================================
function MAX (LEFT, RIGHT: INTEGER) return INTEGER is
begin
if LEFT > RIGHT then return LEFT;
else return RIGHT;
end if;
end MAX;
function MIN (LEFT, RIGHT: INTEGER) return INTEGER is
begin
if LEFT < RIGHT then return LEFT;
else return RIGHT;
end if;
end MIN;
function SIGNED_NUM_BITS (ARG: INTEGER) return NATURAL is
variable NBITS: NATURAL;
variable N: NATURAL;
begin
if ARG >= 0 then
N := ARG;
else
N := -(ARG+1);
end if;
NBITS := 1;
while N > 0 loop
NBITS := NBITS+1;
N := N / 2;
end loop;
return NBITS;
end SIGNED_NUM_BITS;
function UNSIGNED_NUM_BITS (ARG: NATURAL) return NATURAL is
variable NBITS: NATURAL;
variable N: NATURAL;
begin
N := ARG;
NBITS := 1;
while N > 1 loop
NBITS := NBITS+1;
N := N / 2;
end loop;
return NBITS;
end UNSIGNED_NUM_BITS;
------------------------------------------------------------------------------
-- this internal function computes the addition of two UNSIGNED
-- with input carry
-- * the two arguments are of the same length
function ADD_UNSIGNED (L, R: UNSIGNED; C: BIT) return UNSIGNED is
constant L_LEFT: INTEGER := L'LENGTH-1;
alias XL: UNSIGNED(L_LEFT downto 0) is L;
alias XR: UNSIGNED(L_LEFT downto 0) is R;
variable RESULT: UNSIGNED(L_LEFT downto 0);
variable CBIT: BIT := C;
begin
for I in 0 to L_LEFT loop
RESULT(I) := CBIT xor XL(I) xor XR(I);
CBIT := (CBIT and XL(I)) or (CBIT and XR(I)) or (XL(I) and XR(I));
end loop;
return RESULT;
end ADD_UNSIGNED;
-- this internal function computes the addition of two SIGNED
-- with input carry
-- * the two arguments are of the same length
function ADD_SIGNED (L, R: SIGNED; C: BIT) return SIGNED is
constant L_LEFT: INTEGER := L'LENGTH-1;
alias XL: SIGNED(L_LEFT downto 0) is L;
alias XR: SIGNED(L_LEFT downto 0) is R;
variable RESULT: SIGNED(L_LEFT downto 0);
variable CBIT: BIT := C;
begin
for I in 0 to L_LEFT loop
RESULT(I) := CBIT xor XL(I) xor XR(I);
CBIT := (CBIT and XL(I)) or (CBIT and XR(I)) or (XL(I) and XR(I));
end loop;
return RESULT;
end ADD_SIGNED;
------------------------------------------------------------------------------
-- this internal procedure computes UNSIGNED division
-- giving the quotient and remainder.
procedure DIVMOD (NUM, XDENOM: UNSIGNED; XQUOT, XREMAIN: out UNSIGNED) is
variable TEMP: UNSIGNED(NUM'LENGTH downto 0);
variable QUOT: UNSIGNED(MAX(NUM'LENGTH, XDENOM'LENGTH)-1 downto 0);
alias DENOM: UNSIGNED(XDENOM'LENGTH-1 downto 0) is XDENOM;
variable TOPBIT: INTEGER;
variable TOPBIT_assigned : boolean := false;
begin
TEMP := "0"&NUM;
QUOT := (others => '0');
TOPBIT := -1;
for J in DENOM'RANGE loop
if DENOM(J)='1' and not TOPBIT_assigned then
TOPBIT := J;
TOPBIT_assigned := true;
end if;
-- оригинальный код с не поддержанным пока exit
-- if DENOM(J)='1' then
-- TOPBIT := J;
-- exit;
-- end if;
end loop;
assert TOPBIT >= 0 report "DIV, MOD, or REM by zero" severity ERROR;
for J in NUM'LENGTH-(TOPBIT+1) downto 0 loop
if TEMP(TOPBIT+J+1 downto J) >= "0"&DENOM(TOPBIT downto 0) then
TEMP(TOPBIT+J+1 downto J) := (TEMP(TOPBIT+J+1 downto J))
-("0"&DENOM(TOPBIT downto 0));
QUOT(J) := '1';
end if;
assert TEMP(TOPBIT+J+1)='0'
report "internal error in the division algorithm"
severity ERROR;
end loop;
XQUOT := RESIZE(QUOT, XQUOT'LENGTH);
XREMAIN := RESIZE(TEMP, XREMAIN'LENGTH);
end DIVMOD;
-----------------Local Subprograms - shift/rotate ops-------------------------
function XSLL (ARG: BIT_VECTOR; COUNT: NATURAL) return BIT_VECTOR is
constant ARG_L: INTEGER := ARG'LENGTH-1;
alias XARG: BIT_VECTOR(ARG_L downto 0) is ARG;
variable RESULT: BIT_VECTOR(ARG_L downto 0) := (others => '0');
begin
if COUNT <= ARG_L then
RESULT(ARG_L downto COUNT) := XARG(ARG_L-COUNT downto 0);
end if;
return RESULT;
end XSLL;
function XSRL (ARG: BIT_VECTOR; COUNT: NATURAL) return BIT_VECTOR is
constant ARG_L: INTEGER := ARG'LENGTH-1;
alias XARG: BIT_VECTOR(ARG_L downto 0) is ARG;
variable RESULT: BIT_VECTOR(ARG_L downto 0) := (others => '0');
begin
if COUNT <= ARG_L then
RESULT(ARG_L-COUNT downto 0) := XARG(ARG_L downto COUNT);
end if;
return RESULT;
end XSRL;
function XSRA (ARG: BIT_VECTOR; COUNT: NATURAL) return BIT_VECTOR is
constant ARG_L: INTEGER := ARG'LENGTH-1;
alias XARG: BIT_VECTOR(ARG_L downto 0) is ARG;
variable RESULT: BIT_VECTOR(ARG_L downto 0);
variable XCOUNT: NATURAL := COUNT;
begin
if ((ARG'LENGTH <= 1) or (XCOUNT = 0)) then return ARG;
else
if (XCOUNT > ARG_L) then XCOUNT := ARG_L;
end if;
RESULT(ARG_L-XCOUNT downto 0) := XARG(ARG_L downto XCOUNT);
RESULT(ARG_L downto (ARG_L - XCOUNT + 1)) := (others => XARG(ARG_L));
end if;
return RESULT;
end XSRA;
function XROL (ARG: BIT_VECTOR; COUNT: NATURAL) return BIT_VECTOR is
constant ARG_L: INTEGER := ARG'LENGTH-1;
alias XARG: BIT_VECTOR(ARG_L downto 0) is ARG;
variable RESULT: BIT_VECTOR(ARG_L downto 0) := XARG;
variable COUNTM: INTEGER;
begin
COUNTM := COUNT mod (ARG_L + 1);
if COUNTM /= 0 then
RESULT(ARG_L downto COUNTM) := XARG(ARG_L-COUNTM downto 0);
RESULT(COUNTM-1 downto 0) := XARG(ARG_L downto ARG_L-COUNTM+1);
end if;
return RESULT;
end XROL;
function XROR (ARG: BIT_VECTOR; COUNT: NATURAL) return BIT_VECTOR is
constant ARG_L: INTEGER := ARG'LENGTH-1;
alias XARG: BIT_VECTOR(ARG_L downto 0) is ARG;
variable RESULT: BIT_VECTOR(ARG_L downto 0) := XARG;
variable COUNTM: INTEGER;
begin
COUNTM := COUNT mod (ARG_L + 1);
if COUNTM /= 0 then
RESULT(ARG_L-COUNTM downto 0) := XARG(ARG_L downto COUNTM);
RESULT(ARG_L downto ARG_L-COUNTM+1) := XARG(COUNTM-1 downto 0);
end if;
return RESULT;
end XROR;
---------------- Local Subprograms - Relational Operators --------------------
-- General "=" for UNSIGNED vectors, same length
--
function UNSIGNED_EQUAL (L, R: UNSIGNED) return BOOLEAN is
begin
return BIT_VECTOR(L) = BIT_VECTOR(R);
end UNSIGNED_EQUAL;
--
-- General "=" for SIGNED vectors, same length
--
function SIGNED_EQUAL (L, R: SIGNED) return BOOLEAN is
begin
return BIT_VECTOR(L) = BIT_VECTOR(R);
end SIGNED_EQUAL;
--
-- General "<" for UNSIGNED vectors, same length
--
function UNSIGNED_LESS (L, R: UNSIGNED) return BOOLEAN is
begin
return BIT_VECTOR(L) < BIT_VECTOR(R);
end UNSIGNED_LESS;
--
-- General "<" function for SIGNED vectors, same length
--
function SIGNED_LESS (L, R: SIGNED) return BOOLEAN is
-- Need aliases to assure index direction
variable INTERN_L: SIGNED(0 to L'LENGTH-1);
variable INTERN_R: SIGNED(0 to R'LENGTH-1);
begin
INTERN_L := L;
INTERN_R := R;
INTERN_L(0) := not INTERN_L(0);
INTERN_R(0) := not INTERN_R(0);
return BIT_VECTOR(INTERN_L) < BIT_VECTOR(INTERN_R);
end SIGNED_LESS;
--
-- General "<=" function for UNSIGNED vectors, same length
--
function UNSIGNED_LESS_OR_EQUAL (L, R: UNSIGNED) return BOOLEAN is
begin
return BIT_VECTOR(L) <= BIT_VECTOR(R);
end UNSIGNED_LESS_OR_EQUAL;
--
-- General "<=" function for SIGNED vectors, same length
--
function SIGNED_LESS_OR_EQUAL (L, R: SIGNED) return BOOLEAN is
-- Need aliases to assure index direction
variable INTERN_L: SIGNED(0 to L'LENGTH-1);
variable INTERN_R: SIGNED(0 to R'LENGTH-1);
begin
INTERN_L := L;
INTERN_R := R;
INTERN_L(0) := not INTERN_L(0);
INTERN_R(0) := not INTERN_R(0);
return BIT_VECTOR(INTERN_L) <= BIT_VECTOR(INTERN_R);
end SIGNED_LESS_OR_EQUAL;
--====================== Exported Functions ==================================
-- Id: A.1
function "abs" (ARG: SIGNED) return SIGNED is
constant ARG_LEFT: INTEGER := ARG'LENGTH-1;
variable RESULT: SIGNED(ARG_LEFT downto 0);
begin
if ARG'LENGTH < 1 then return NAS;
end if;
RESULT := ARG;
if RESULT(RESULT'LEFT) = '1' then
RESULT := -RESULT;
end if;
return RESULT;
end "abs";
-- Id: A.2
function "-" (ARG: SIGNED) return SIGNED is
constant ARG_LEFT: INTEGER := ARG'LENGTH-1;
alias XARG: SIGNED(ARG_LEFT downto 0) is ARG;
variable RESULT: SIGNED(ARG_LEFT downto 0);
variable CBIT: BIT := '1';
begin
if ARG'LENGTH < 1 then return NAS;
end if;
for I in 0 to RESULT'LEFT loop
RESULT(I) := not(XARG(I)) xor CBIT;
CBIT := CBIT and not(XARG(I));
end loop;
return RESULT;
end "-";
--============================================================================
-- Id: A.3
function "+" (L, R: UNSIGNED) return UNSIGNED is
constant L_LEFT: INTEGER := L'LENGTH-1;
constant R_LEFT: INTEGER := R'LENGTH-1;
constant SIZE: NATURAL := MAX(L'LENGTH, R'LENGTH);
begin
if ((L'LENGTH < 1) or (R'LENGTH < 1)) then return NAU;
end if;
return ADD_UNSIGNED(RESIZE(L, SIZE), RESIZE(R, SIZE), bit' ('0') );
end "+";
-- Id: A.4
function "+" (L, R: SIGNED) return SIGNED is
constant L_LEFT: INTEGER := L'LENGTH-1;
constant R_LEFT: INTEGER := R'LENGTH-1;
constant SIZE: NATURAL := MAX(L'LENGTH, R'LENGTH);
begin
if ((L'LENGTH < 1) or (R'LENGTH < 1)) then return NAS;
end if;
return ADD_SIGNED(RESIZE(L, SIZE), RESIZE(R, SIZE), bit' ('0'));
end "+";
-- Id: A.5
function "+" (L: UNSIGNED; R: NATURAL) return UNSIGNED is
begin
return L + TO_UNSIGNED(R, L'LENGTH);
end "+";
-- Id: A.6
function "+" (L: NATURAL; R: UNSIGNED) return UNSIGNED is
begin
return TO_UNSIGNED(L, R'LENGTH) + R;
end "+";
-- Id: A.7
function "+" (L: SIGNED; R: INTEGER) return SIGNED is
begin
return L + TO_SIGNED(R, L'LENGTH);
end "+";
-- Id: A.8
function "+" (L: INTEGER; R: SIGNED) return SIGNED is
begin
return TO_SIGNED(L, R'LENGTH) + R;
end "+";
--============================================================================
-- Id: A.9
function "-" (L, R: UNSIGNED) return UNSIGNED is
constant L_LEFT: INTEGER := L'LENGTH-1;
constant R_LEFT: INTEGER := R'LENGTH-1;
constant SIZE: NATURAL := MAX(L'LENGTH, R'LENGTH);
begin
if ((L'LENGTH < 1) or (R'LENGTH < 1)) then return NAU;
end if;
return ADD_UNSIGNED(RESIZE(L, SIZE),
not(RESIZE(R, SIZE)),
bit' ('1'));
end "-";
-- Id: A.10
function "-" (L, R: SIGNED) return SIGNED is
constant L_LEFT: INTEGER := L'LENGTH-1;
constant R_LEFT: INTEGER := R'LENGTH-1;
constant SIZE: NATURAL := MAX(L'LENGTH, R'LENGTH);
begin
if ((L'LENGTH < 1) or (R'LENGTH < 1)) then return NAS;
end if;
return ADD_SIGNED(RESIZE(L, SIZE),
not(RESIZE(R, SIZE)),
bit' ('1'));
end "-";
-- Id: A.11
function "-" (L: UNSIGNED; R: NATURAL) return UNSIGNED is
begin
return L - TO_UNSIGNED(R, L'LENGTH);
end "-";
-- Id: A.12
function "-" (L: NATURAL; R: UNSIGNED) return UNSIGNED is
begin
return TO_UNSIGNED(L, R'LENGTH) - R;
end "-";
-- Id: A.13
function "-" (L: SIGNED; R: INTEGER) return SIGNED is
begin
return L - TO_SIGNED(R, L'LENGTH);
end "-";
-- Id: A.14
function "-" (L: INTEGER; R: SIGNED) return SIGNED is
begin
return TO_SIGNED(L, R'LENGTH) - R;
end "-";
--============================================================================
-- Id: A.15
function "*" (L, R: UNSIGNED) return UNSIGNED is
constant L_LEFT: INTEGER := L'LENGTH-1;
constant R_LEFT: INTEGER := R'LENGTH-1;
alias XL: UNSIGNED(L_LEFT downto 0) is L;
alias XR: UNSIGNED(R_LEFT downto 0) is R;
variable RESULT: UNSIGNED((L'LENGTH+R'LENGTH-1) downto 0) := (others => '0');
variable ADVAL: UNSIGNED((L'LENGTH+R'LENGTH-1) downto 0);
begin
if ((L'LENGTH < 1) or (R'LENGTH < 1)) then return NAU;
end if;
ADVAL := RESIZE(XR, RESULT'LENGTH);
for I in 0 to L_LEFT loop
if XL(I)='1' then RESULT := RESULT + ADVAL;
end if;
ADVAL := SHIFT_LEFT(ADVAL, 1);
end loop;
return RESULT;
end "*";
-- Id: A.16
function "*" (L, R: SIGNED) return SIGNED is
constant L_LEFT: INTEGER := L'LENGTH-1;
constant R_LEFT: INTEGER := R'LENGTH-1;
variable XL: SIGNED(L_LEFT downto 0);
variable XR: SIGNED(R_LEFT downto 0);
variable RESULT: SIGNED((L_LEFT+R_LEFT+1) downto 0) := (others => '0');
variable ADVAL: SIGNED((L_LEFT+R_LEFT+1) downto 0);
begin
if ((L_LEFT < 0) or (R_LEFT < 0)) then return NAS;
end if;
XL := L;
XR := R;
ADVAL := RESIZE(XR, RESULT'LENGTH);
for I in 0 to L_LEFT-1 loop
if XL(I)='1' then RESULT := RESULT + ADVAL;
end if;
ADVAL := SHIFT_LEFT(ADVAL, 1);
end loop;
if XL(L_LEFT)='1' then
RESULT := RESULT - ADVAL;
end if;
return RESULT;
end "*";
-- Id: A.17
function "*" (L: UNSIGNED; R: NATURAL) return UNSIGNED is
begin
return L * TO_UNSIGNED(R, L'LENGTH);
end "*";
-- Id: A.18
function "*" (L: NATURAL; R: UNSIGNED) return UNSIGNED is
begin
return TO_UNSIGNED(L, R'LENGTH) * R;
end "*";
-- Id: A.19
function "*" (L: SIGNED; R: INTEGER) return SIGNED is
begin
return L * TO_SIGNED(R, L'LENGTH);
end "*";
-- Id: A.20
function "*" (L: INTEGER; R: SIGNED) return SIGNED is
begin
return TO_SIGNED(L, R'LENGTH) * R;
end "*";
--============================================================================
-- Id: A.21
function "/" (L, R: UNSIGNED) return UNSIGNED is
variable FQUOT: UNSIGNED(L'LENGTH-1 downto 0);
variable FREMAIN: UNSIGNED(R'LENGTH-1 downto 0);
begin
if ((L'LENGTH < 1) or (R'LENGTH < 1)) then return NAU;
end if;
DIVMOD(L, R, FQUOT, FREMAIN);
return FQUOT;
end "/";
-- Id: A.22
function "/" (L, R: SIGNED) return SIGNED is
variable FQUOT: UNSIGNED(L'LENGTH-1 downto 0);
variable FREMAIN: UNSIGNED(R'LENGTH-1 downto 0);
variable XNUM: UNSIGNED(L'LENGTH-1 downto 0);
variable XDENOM: UNSIGNED(R'LENGTH-1 downto 0);
variable QNEG: BOOLEAN := FALSE;
begin
if ((L'LENGTH < 1) or (R'LENGTH < 1)) then return NAS;
end if;
if L(L'LEFT)='1' then
XNUM := UNSIGNED(-L);
QNEG := TRUE;
else
XNUM := UNSIGNED(L);
end if;
if R(R'LEFT)='1' then
XDENOM := UNSIGNED(-R);
QNEG := not QNEG;
else
XDENOM := UNSIGNED(R);
end if;
DIVMOD(XNUM, XDENOM, FQUOT, FREMAIN);
if QNEG then FQUOT := "0"-FQUOT;
end if;
return SIGNED(FQUOT);
end "/";
-- Id: A.23
function "/" (L: UNSIGNED; R: NATURAL) return UNSIGNED is
constant R_LENGTH: NATURAL := MAX(L'LENGTH, UNSIGNED_NUM_BITS(R));
variable XR, QUOT: UNSIGNED(R_LENGTH-1 downto 0);
begin
if (L'LENGTH < 1) then return NAU;
end if;
if (R_LENGTH > L'LENGTH) then
QUOT := (others => '0');
return RESIZE(QUOT, L'LENGTH);
end if;
XR := TO_UNSIGNED(R, R_LENGTH);
QUOT := RESIZE((L / XR), QUOT'LENGTH);
return RESIZE(QUOT, L'LENGTH);
end "/";
-- Id: A.24
function "/" (L: NATURAL; R: UNSIGNED) return UNSIGNED is
constant L_LENGTH: NATURAL := MAX(UNSIGNED_NUM_BITS(L), R'LENGTH);
variable XL, QUOT: UNSIGNED(L_LENGTH-1 downto 0);
begin
if (R'LENGTH < 1) then return NAU;
end if;
XL := TO_UNSIGNED(L, L_LENGTH);
QUOT := RESIZE((XL / R), QUOT'LENGTH);
if L_LENGTH > R'LENGTH
and QUOT(L_LENGTH-1 downto R'LENGTH)
/= (L_LENGTH-1 downto R'LENGTH => '0')
then
assert NO_WARNING report "NUMERIC_BIT.""/"": Quotient Truncated"
severity WARNING;
end if;
return RESIZE(QUOT, R'LENGTH);
end "/";
-- Id: A.25
function "/" (L: SIGNED; R: INTEGER) return SIGNED is
constant R_LENGTH: NATURAL := MAX(L'LENGTH, SIGNED_NUM_BITS(R));
variable XR, QUOT: SIGNED(R_LENGTH-1 downto 0);
begin
if (L'LENGTH < 1) then return NAS;
end if;
if (R_LENGTH > L'LENGTH) then
QUOT := (others => '0');
return RESIZE(QUOT, L'LENGTH);
end if;
XR := TO_SIGNED(R, R_LENGTH);
QUOT := RESIZE((L / XR), QUOT'LENGTH);
return RESIZE(QUOT, L'LENGTH);
end "/";
-- Id: A.26
function "/" (L: INTEGER; R: SIGNED) return SIGNED is
constant L_LENGTH: NATURAL := MAX(SIGNED_NUM_BITS(L), R'LENGTH);
variable XL, QUOT: SIGNED(L_LENGTH-1 downto 0);
begin
if (R'LENGTH < 1) then return NAS;
end if;
XL := TO_SIGNED(L, L_LENGTH);
QUOT := RESIZE((XL / R), QUOT'LENGTH);
if L_LENGTH > R'LENGTH and QUOT(L_LENGTH-1 downto R'LENGTH)
/= (L_LENGTH-1 downto R'LENGTH => QUOT(R'LENGTH-1))
then
assert NO_WARNING report "NUMERIC_BIT.""/"": Quotient Truncated"
severity WARNING;
end if;
return RESIZE(QUOT, R'LENGTH);
end "/";
--============================================================================
-- Id: A.27
function "rem" (L, R: UNSIGNED) return UNSIGNED is
variable FQUOT: UNSIGNED(L'LENGTH-1 downto 0);
variable FREMAIN: UNSIGNED(R'LENGTH-1 downto 0);
begin
if ((L'LENGTH < 1) or (R'LENGTH < 1)) then return NAU;
end if;
DIVMOD(L, R, FQUOT, FREMAIN);
return FREMAIN;
end "rem";
-- Id: A.28
function "rem" (L, R: SIGNED) return SIGNED is
variable FQUOT: UNSIGNED(L'LENGTH-1 downto 0);
variable FREMAIN: UNSIGNED(R'LENGTH-1 downto 0);
variable XNUM: UNSIGNED(L'LENGTH-1 downto 0);
variable XDENOM: UNSIGNED(R'LENGTH-1 downto 0);
variable RNEG: BOOLEAN := FALSE;
begin
if ((L'LENGTH < 1) or (R'LENGTH < 1)) then return NAS;
end if;
if L(L'LEFT)='1' then
XNUM := UNSIGNED(-L);
RNEG := TRUE;
else
XNUM := UNSIGNED(L);
end if;
if R(R'LEFT)='1' then
XDENOM := UNSIGNED(-R);
else
XDENOM := UNSIGNED(R);
end if;
DIVMOD(XNUM, XDENOM, FQUOT, FREMAIN);
if RNEG then
FREMAIN := "0"-FREMAIN;
end if;
return SIGNED(FREMAIN);
end "rem";
-- Id: A.29
function "rem" (L: UNSIGNED; R: NATURAL) return UNSIGNED is
constant R_LENGTH: NATURAL := MAX(L'LENGTH, UNSIGNED_NUM_BITS(R));
variable XR, XREM: UNSIGNED(R_LENGTH-1 downto 0);
begin
if (L'LENGTH < 1) then return NAU;
end if;
XR := TO_UNSIGNED(R, R_LENGTH);
XREM := RESIZE((L rem XR), XREM'LENGTH);
if R_LENGTH > L'LENGTH and XREM(R_LENGTH-1 downto L'LENGTH)
/= (R_LENGTH-1 downto L'LENGTH => '0')
then
assert NO_WARNING report "NUMERIC_BIT.""rem"": Remainder Truncated"
severity WARNING;
end if;
return RESIZE(XREM, L'LENGTH);
end "rem";
-- Id: A.30
function "rem" (L: NATURAL; R: UNSIGNED) return UNSIGNED is
constant L_LENGTH: NATURAL := MAX(UNSIGNED_NUM_BITS(L), R'LENGTH);
variable XL, XREM: UNSIGNED(L_LENGTH-1 downto 0);
begin
if (R'LENGTH < 1) then return NAU;
end if;
XL := TO_UNSIGNED(L, L_LENGTH);
XREM := RESIZE((XL rem R), XREM'LENGTH);
if L_LENGTH > R'LENGTH and XREM(L_LENGTH-1 downto R'LENGTH)
/= (L_LENGTH-1 downto R'LENGTH => '0')
then
assert NO_WARNING report "NUMERIC_BIT.""rem"": Remainder Truncated"
severity WARNING;
end if;
return RESIZE(XREM, R'LENGTH);
end "rem";
-- Id: A.31
function "rem" (L: SIGNED; R: INTEGER) return SIGNED is
constant R_LENGTH: NATURAL := MAX(L'LENGTH, SIGNED_NUM_BITS(R));
variable XR, XREM: SIGNED(R_LENGTH-1 downto 0);
begin
if (L'LENGTH < 1) then return NAS;
end if;
XR := TO_SIGNED(R, R_LENGTH);
XREM := RESIZE((L rem XR), XREM'LENGTH);
if R_LENGTH > L'LENGTH and XREM(R_LENGTH-1 downto L'LENGTH)
/= (R_LENGTH-1 downto L'LENGTH => XREM(L'LENGTH-1))
then
assert NO_WARNING report "NUMERIC_BIT.""rem"": Remainder Truncated"
severity WARNING;
end if;
return RESIZE(XREM, L'LENGTH);
end "rem";
-- Id: A.32
function "rem" (L: INTEGER; R: SIGNED) return SIGNED is
constant L_LENGTH: NATURAL := MAX(SIGNED_NUM_BITS(L), R'LENGTH);
variable XL, XREM: SIGNED(L_LENGTH-1 downto 0);
begin
if (R'LENGTH < 1) then return NAS;
end if;
XL := TO_SIGNED(L, L_LENGTH);
XREM := RESIZE((XL rem R), XREM'LENGTH);
if L_LENGTH > R'LENGTH and XREM(L_LENGTH-1 downto R'LENGTH)
/= (L_LENGTH-1 downto R'LENGTH => XREM(R'LENGTH-1))
then
assert NO_WARNING report "NUMERIC_BIT.""rem"": Remainder Truncated"
severity WARNING;
end if;
return RESIZE(XREM, R'LENGTH);
end "rem";
--============================================================================
-- Id: A.33
function "mod" (L, R: UNSIGNED) return UNSIGNED is
variable FQUOT: UNSIGNED(L'LENGTH-1 downto 0);
variable FREMAIN: UNSIGNED(R'LENGTH-1 downto 0);
begin
if ((L'LENGTH < 1) or (R'LENGTH < 1)) then return NAU;
end if;
DIVMOD(L, R, FQUOT, FREMAIN);
return FREMAIN;
end "mod";
-- Id: A.34
function "mod" (L, R: SIGNED) return SIGNED is
variable FQUOT: UNSIGNED(L'LENGTH-1 downto 0);
variable FREMAIN: UNSIGNED(R'LENGTH-1 downto 0);
variable XNUM: UNSIGNED(L'LENGTH-1 downto 0);
variable XDENOM: UNSIGNED(R'LENGTH-1 downto 0);
variable RNEG: BOOLEAN := FALSE;
begin
if ((L'LENGTH < 1) or (R'LENGTH < 1)) then return NAS;
end if;
if L(L'LEFT)='1' then
XNUM := UNSIGNED(-L);
else
XNUM := UNSIGNED(L);
end if;
if R(R'LEFT)='1' then
XDENOM := UNSIGNED(-R);
RNEG := TRUE;
else
XDENOM := UNSIGNED(R);
end if;
DIVMOD(XNUM, XDENOM, FQUOT, FREMAIN);
if RNEG and L(L'LEFT)='1' then
FREMAIN := "0"-FREMAIN;
elsif RNEG and FREMAIN/="0" then
FREMAIN := FREMAIN-XDENOM;
elsif L(L'LEFT)='1' and FREMAIN/="0" then
FREMAIN := XDENOM-FREMAIN;
end if;
return SIGNED(FREMAIN);
end "mod";
-- Id: A.35
function "mod" (L: UNSIGNED; R: NATURAL) return UNSIGNED is
constant R_LENGTH: NATURAL := MAX(L'LENGTH, UNSIGNED_NUM_BITS(R));
variable XR, XREM: UNSIGNED(R_LENGTH-1 downto 0);
begin
if (L'LENGTH < 1) then return NAU;
end if;
XR := TO_UNSIGNED(R, R_LENGTH);
XREM := RESIZE((L mod XR), XREM'LENGTH);
if R_LENGTH > L'LENGTH and XREM(R_LENGTH-1 downto L'LENGTH)
/= (R_LENGTH-1 downto L'LENGTH => '0')
then
assert NO_WARNING report "NUMERIC_BIT.""mod"": modulus Truncated"
severity WARNING;
end if;
return RESIZE(XREM, L'LENGTH);
end "mod";
-- Id: A.36
function "mod" (L: NATURAL; R: UNSIGNED) return UNSIGNED is
constant L_LENGTH: NATURAL := MAX(UNSIGNED_NUM_BITS(L), R'LENGTH);
variable XL, XREM: UNSIGNED(L_LENGTH-1 downto 0);
begin
if (R'LENGTH < 1) then return NAU;
end if;
XL := TO_UNSIGNED(L, L_LENGTH);
XREM := RESIZE((XL mod R), XREM'LENGTH);
if L_LENGTH > R'LENGTH and XREM(L_LENGTH-1 downto R'LENGTH)
/= (L_LENGTH-1 downto R'LENGTH => '0')
then
assert NO_WARNING report "NUMERIC_BIT.""mod"": modulus Truncated"
severity WARNING;
end if;
return RESIZE(XREM, R'LENGTH);
end "mod";
-- Id: A.37
function "mod" (L: SIGNED; R: INTEGER) return SIGNED is
constant R_LENGTH: NATURAL := MAX(L'LENGTH, SIGNED_NUM_BITS(R));
variable XR, XREM: SIGNED(R_LENGTH-1 downto 0);
begin
if (L'LENGTH < 1) then return NAS;
end if;
XR := TO_SIGNED(R, R_LENGTH);
XREM := RESIZE((L mod XR), XREM'LENGTH);
if R_LENGTH > L'LENGTH and XREM(R_LENGTH-1 downto L'LENGTH)
/= (R_LENGTH-1 downto L'LENGTH => XREM(L'LENGTH-1))
then
assert NO_WARNING report "NUMERIC_BIT.""mod"": modulus Truncated"
severity WARNING;
end if;
return RESIZE(XREM, L'LENGTH);
end "mod";
-- Id: A.38
function "mod" (L: INTEGER; R: SIGNED) return SIGNED is
constant L_LENGTH: NATURAL := MAX(SIGNED_NUM_BITS(L), R'LENGTH);
variable XL, XREM: SIGNED(L_LENGTH-1 downto 0);
begin
if (R'LENGTH < 1) then return NAS;
end if;
XL := TO_SIGNED(L, L_LENGTH);
XREM := RESIZE((XL mod R), XREM'LENGTH);
if L_LENGTH > R'LENGTH and XREM(L_LENGTH-1 downto R'LENGTH)
/= (L_LENGTH-1 downto R'LENGTH => XREM(R'LENGTH-1))
then
assert NO_WARNING report "NUMERIC_BIT.""mod"": modulus Truncated"
severity WARNING;
end if;
return RESIZE(XREM, R'LENGTH);
end "mod";
--============================================================================
-- Id: C.1
function ">" (L, R: UNSIGNED) return BOOLEAN is
variable SIZE: NATURAL := MAX(L'LENGTH, R'LENGTH);
begin
if ((L'LENGTH < 1) or (R'LENGTH < 1)) then
assert NO_WARNING
report "NUMERIC_BIT."">"": null argument detected, returning FALSE"
severity WARNING;
return FALSE;
end if;
return not UNSIGNED_LESS_OR_EQUAL(RESIZE(L, SIZE), RESIZE(R, SIZE));
end ">";
-- Id: C.2
function ">" (L, R: SIGNED) return BOOLEAN is
variable SIZE: NATURAL := MAX(L'LENGTH, R'LENGTH);
begin
if ((L'LENGTH < 1) or (R'LENGTH < 1)) then
assert NO_WARNING
report "NUMERIC_BIT."">"": null argument detected, returning FALSE"
severity WARNING;
return FALSE;
end if;
return not SIGNED_LESS_OR_EQUAL(RESIZE(L, SIZE), RESIZE(R, SIZE));
end ">";
-- Id: C.3
function ">" (L: NATURAL; R: UNSIGNED) return BOOLEAN is
begin
if (R'LENGTH < 1) then
assert NO_WARNING
report "NUMERIC_BIT."">"": null argument detected, returning FALSE"
severity WARNING;
return FALSE;
end if;
if UNSIGNED_NUM_BITS(L) > R'LENGTH then return TRUE;
end if;
return not UNSIGNED_LESS_OR_EQUAL(TO_UNSIGNED(L, R'LENGTH), R);
end ">";
-- Id: C.4
function ">" (L: INTEGER; R: SIGNED) return BOOLEAN is
begin
if (R'LENGTH < 1) then
assert NO_WARNING
report "NUMERIC_BIT."">"": null argument detected, returning FALSE"
severity WARNING;
return FALSE;
end if;
if SIGNED_NUM_BITS(L) > R'LENGTH then return L > 0;
end if;
return not SIGNED_LESS_OR_EQUAL(TO_SIGNED(L, R'LENGTH), R);
end ">";
-- Id: C.5
function ">" (L: UNSIGNED; R: NATURAL) return BOOLEAN is
begin
if (L'LENGTH < 1) then
assert NO_WARNING
report "NUMERIC_BIT."">"": null argument detected, returning FALSE"
severity WARNING;
return FALSE;
end if;
if UNSIGNED_NUM_BITS(R) > L'LENGTH then return FALSE;
end if;
return not UNSIGNED_LESS_OR_EQUAL(L, TO_UNSIGNED(R, L'LENGTH));
end ">";
-- Id: C.6
function ">" (L: SIGNED; R: INTEGER) return BOOLEAN is
begin
if (L'LENGTH < 1) then
assert NO_WARNING
report "NUMERIC_BIT."">"": null argument detected, returning FALSE"
severity WARNING;
return FALSE;
end if;
if SIGNED_NUM_BITS(R) > L'LENGTH then return 0 > R;
end if;
return not SIGNED_LESS_OR_EQUAL(L, TO_SIGNED(R, L'LENGTH));
end ">";
--============================================================================
-- Id: C.7
function "<" (L, R: UNSIGNED) return BOOLEAN is
variable SIZE: NATURAL := MAX(L'LENGTH, R'LENGTH);
begin
if ((L'LENGTH < 1) or (R'LENGTH < 1)) then
assert NO_WARNING
report "NUMERIC_BIT.""<"": null argument detected, returning FALSE"
severity WARNING;
return FALSE;
end if;
return UNSIGNED_LESS(RESIZE(L, SIZE), RESIZE(R, SIZE));
end "<";
-- Id: C.8
function "<" (L, R: SIGNED) return BOOLEAN is
variable SIZE: NATURAL := MAX(L'LENGTH, R'LENGTH);
begin
if ((L'LENGTH < 1) or (R'LENGTH < 1)) then
assert NO_WARNING
report "NUMERIC_BIT.""<"": null argument detected, returning FALSE"
severity WARNING;
return FALSE;
end if;
return SIGNED_LESS(RESIZE(L, SIZE), RESIZE(R, SIZE));
end "<";
-- Id: C.9
function "<" (L: NATURAL; R: UNSIGNED) return BOOLEAN is
begin
if (R'LENGTH < 1) then
assert NO_WARNING
report "NUMERIC_BIT.""<"": null argument detected, returning FALSE"
severity WARNING;
return FALSE;
end if;
if UNSIGNED_NUM_BITS(L) > R'LENGTH then return L < 0;
end if;
return UNSIGNED_LESS(TO_UNSIGNED(L, R'LENGTH), R);
end "<";
-- Id: C.10
function "<" (L: INTEGER; R: SIGNED) return BOOLEAN is
begin
if (R'LENGTH < 1) then
assert NO_WARNING
report "NUMERIC_BIT.""<"": null argument detected, returning FALSE"
severity WARNING;
return FALSE;
end if;
if SIGNED_NUM_BITS(L) > R'LENGTH then return L < 0;
end if;
return SIGNED_LESS(TO_SIGNED(L, R'LENGTH), R);
end "<";
-- Id: C.11
function "<" (L: UNSIGNED; R: NATURAL) return BOOLEAN is
begin
if (L'LENGTH < 1) then
assert NO_WARNING
report "NUMERIC_BIT.""<"": null argument detected, returning FALSE"
severity WARNING;
return FALSE;
end if;
if UNSIGNED_NUM_BITS(R) > L'LENGTH then return 0 < R;
end if;
return UNSIGNED_LESS(L, TO_UNSIGNED(R, L'LENGTH));
end "<";
-- Id: C.12
function "<" (L: SIGNED; R: INTEGER) return BOOLEAN is
begin
if (L'LENGTH < 1) then
assert NO_WARNING
report "NUMERIC_BIT.""<"": null argument detected, returning FALSE"
severity WARNING;
return FALSE;
end if;
if SIGNED_NUM_BITS(R) > L'LENGTH then return 0 < R;
end if;
return SIGNED_LESS(L, TO_SIGNED(R, L'LENGTH));
end "<";
--============================================================================
-- Id: C.13
function "<=" (L, R: UNSIGNED) return BOOLEAN is
variable SIZE: NATURAL := MAX(L'LENGTH, R'LENGTH);
begin
if ((L'LENGTH < 1) or (R'LENGTH < 1)) then
assert NO_WARNING
report "NUMERIC_BIT.""<="": null argument detected, returning FALSE"
severity WARNING;
return FALSE;
end if;
return UNSIGNED_LESS_OR_EQUAL(RESIZE(L, SIZE), RESIZE(R, SIZE));
end "<=";
-- Id: C.14
function "<=" (L, R: SIGNED) return BOOLEAN is
variable SIZE: NATURAL := MAX(L'LENGTH, R'LENGTH);
begin
if ((L'LENGTH < 1) or (R'LENGTH < 1)) then
assert NO_WARNING
report "NUMERIC_BIT.""<="": null argument detected, returning FALSE"
severity WARNING;
return FALSE;
end if;
return SIGNED_LESS_OR_EQUAL(RESIZE(L, SIZE), RESIZE(R, SIZE));
end "<=";
-- Id: C.15
function "<=" (L: NATURAL; R: UNSIGNED) return BOOLEAN is
begin
if (R'LENGTH < 1) then
assert NO_WARNING
report "NUMERIC_BIT.""<="": null argument detected, returning FALSE"
severity WARNING;
return FALSE;
end if;
if UNSIGNED_NUM_BITS(L) > R'LENGTH then return L < 0;
end if;
return UNSIGNED_LESS_OR_EQUAL(TO_UNSIGNED(L, R'LENGTH), R);
end "<=";
-- Id: C.16
function "<=" (L: INTEGER; R: SIGNED) return BOOLEAN is
begin
if (R'LENGTH < 1) then
assert NO_WARNING
report "NUMERIC_BIT.""<="": null argument detected, returning FALSE"
severity WARNING;
return FALSE;
end if;
if SIGNED_NUM_BITS(L) > R'LENGTH then return L < 0;
end if;
return SIGNED_LESS_OR_EQUAL(TO_SIGNED(L, R'LENGTH), R);
end "<=";
-- Id: C.17
function "<=" (L: UNSIGNED; R: NATURAL) return BOOLEAN is
begin
if (L'LENGTH < 1) then
assert NO_WARNING
report "NUMERIC_BIT.""<="": null argument detected, returning FALSE"
severity WARNING;
return FALSE;
end if;
if UNSIGNED_NUM_BITS(R) > L'LENGTH then return 0 < R;
end if;
return UNSIGNED_LESS_OR_EQUAL(L, TO_UNSIGNED(R, L'LENGTH));
end "<=";
-- Id: C.18
function "<=" (L: SIGNED; R: INTEGER) return BOOLEAN is
begin
if (L'LENGTH < 1) then
assert NO_WARNING
report "NUMERIC_BIT.""<="": null argument detected, returning FALSE"
severity WARNING;
return FALSE;
end if;
if SIGNED_NUM_BITS(R) > L'LENGTH then return 0 < R;
end if;
return SIGNED_LESS_OR_EQUAL(L, TO_SIGNED(R, L'LENGTH));
end "<=";
--============================================================================
-- Id: C.19
function ">=" (L, R: UNSIGNED) return BOOLEAN is
variable SIZE: NATURAL := MAX(L'LENGTH, R'LENGTH);
begin
if ((L'LENGTH < 1) or (R'LENGTH < 1)) then
assert NO_WARNING
report "NUMERIC_BIT."">="": null argument detected, returning FALSE"
severity WARNING;
return FALSE;
end if;
return not UNSIGNED_LESS(RESIZE(L, SIZE), RESIZE(R, SIZE));
end ">=";
-- Id: C.20
function ">=" (L, R: SIGNED) return BOOLEAN is
variable SIZE: NATURAL := MAX(L'LENGTH, R'LENGTH);
begin
if ((L'LENGTH < 1) or (R'LENGTH < 1)) then
assert NO_WARNING
report "NUMERIC_BIT."">="": null argument detected, returning FALSE"
severity WARNING;
return FALSE;
end if;
return not SIGNED_LESS(RESIZE(L, SIZE), RESIZE(R, SIZE));
end ">=";
-- Id: C.21
function ">=" (L: NATURAL; R: UNSIGNED) return BOOLEAN is
begin
if (R'LENGTH < 1) then
assert NO_WARNING
report "NUMERIC_BIT."">="": null argument detected, returning FALSE"
severity WARNING;
return FALSE;
end if;
if UNSIGNED_NUM_BITS(L) > R'LENGTH then return L > 0;
end if;
return not UNSIGNED_LESS(TO_UNSIGNED(L, R'LENGTH), R);
end ">=";
-- Id: C.22
function ">=" (L: INTEGER; R: SIGNED) return BOOLEAN is
begin
if (R'LENGTH < 1) then
assert NO_WARNING
report "NUMERIC_BIT."">="": null argument detected, returning FALSE"
severity WARNING;
return FALSE;
end if;
if SIGNED_NUM_BITS(L) > R'LENGTH then return L > 0;
end if;
return not SIGNED_LESS(TO_SIGNED(L, R'LENGTH), R);
end ">=";
-- Id: C.23
function ">=" (L: UNSIGNED; R: NATURAL) return BOOLEAN is
begin
if (L'LENGTH < 1) then
assert NO_WARNING
report "NUMERIC_BIT."">="": null argument detected, returning FALSE"
severity WARNING;
return FALSE;
end if;
if UNSIGNED_NUM_BITS(R) > L'LENGTH then return 0 > R;
end if;
return not UNSIGNED_LESS(L, TO_UNSIGNED(R, L'LENGTH));
end ">=";
-- Id: C.24
function ">=" (L: SIGNED; R: INTEGER) return BOOLEAN is
begin
if (L'LENGTH < 1) then
assert NO_WARNING
report "NUMERIC_BIT."">="": null argument detected, returning FALSE"
severity WARNING;
return FALSE;
end if;
if SIGNED_NUM_BITS(R) > L'LENGTH then return 0 > R;
end if;
return not SIGNED_LESS(L, TO_SIGNED(R, L'LENGTH));
end ">=";
--============================================================================
-- Id: C.25
function "=" (L, R: UNSIGNED) return BOOLEAN is
variable SIZE: NATURAL := MAX(L'LENGTH, R'LENGTH);
begin
if ((L'LENGTH < 1) or (R'LENGTH < 1)) then
assert NO_WARNING
report "NUMERIC_BIT.""="": null argument detected, returning FALSE"
severity WARNING;
return FALSE;
end if;
return UNSIGNED_EQUAL(RESIZE(L, SIZE), RESIZE(R, SIZE));
end "=";
-- Id: C.26
function "=" (L, R: SIGNED) return BOOLEAN is
variable SIZE: NATURAL := MAX(L'LENGTH, R'LENGTH);
begin
if ((L'LENGTH < 1) or (R'LENGTH < 1)) then
assert NO_WARNING
report "NUMERIC_BIT.""="": null argument detected, returning FALSE"
severity WARNING;
return FALSE;
end if;
return SIGNED_EQUAL(RESIZE(L, SIZE), RESIZE(R, SIZE));
end "=";
-- Id: C.27
function "=" (L: NATURAL; R: UNSIGNED) return BOOLEAN is
begin
if (R'LENGTH < 1) then
assert NO_WARNING
report "NUMERIC_BIT.""="": null argument detected, returning FALSE"
severity WARNING;
return FALSE;
end if;
if UNSIGNED_NUM_BITS(L) > R'LENGTH then return FALSE;
end if;
return UNSIGNED_EQUAL(TO_UNSIGNED(L, R'LENGTH), R);
end "=";
-- Id: C.28
function "=" (L: INTEGER; R: SIGNED) return BOOLEAN is
begin
if (R'LENGTH < 1) then
assert NO_WARNING
report "NUMERIC_BIT.""="": null argument detected, returning FALSE"
severity WARNING;
return FALSE;
end if;
if SIGNED_NUM_BITS(L) > R'LENGTH then return FALSE;
end if;
return SIGNED_EQUAL(TO_SIGNED(L, R'LENGTH), R);
end "=";
-- Id: C.29
function "=" (L: UNSIGNED; R: NATURAL) return BOOLEAN is
begin
if (L'LENGTH < 1) then
assert NO_WARNING
report "NUMERIC_BIT.""="": null argument detected, returning FALSE"
severity WARNING;
return FALSE;
end if;
if UNSIGNED_NUM_BITS(R) > L'LENGTH then return FALSE;
end if;
return UNSIGNED_EQUAL(L, TO_UNSIGNED(R, L'LENGTH));
end "=";
-- Id: C.30
function "=" (L: SIGNED; R: INTEGER) return BOOLEAN is
begin
if (L'LENGTH < 1) then
assert NO_WARNING
report "NUMERIC_BIT.""="": null argument detected, returning FALSE"
severity WARNING;
return FALSE;
end if;
if SIGNED_NUM_BITS(R) > L'LENGTH then return FALSE;
end if;
return SIGNED_EQUAL(L, TO_SIGNED(R, L'LENGTH));
end "=";
--============================================================================
-- Id: C.31
function "/=" (L, R: UNSIGNED) return BOOLEAN is
variable SIZE: NATURAL := MAX(L'LENGTH, R'LENGTH);
begin
if ((L'LENGTH < 1) or (R'LENGTH < 1)) then
assert NO_WARNING
report "NUMERIC_BIT.""/="": null argument detected, returning TRUE"
severity WARNING;
return TRUE;
end if;
return not(UNSIGNED_EQUAL(RESIZE(L, SIZE), RESIZE(R, SIZE)));
end "/=";
-- Id: C.32
function "/=" (L, R: SIGNED) return BOOLEAN is
variable SIZE: NATURAL := MAX(L'LENGTH, R'LENGTH);
begin
if ((L'LENGTH < 1) or (R'LENGTH < 1)) then
assert NO_WARNING
report "NUMERIC_BIT.""/="": null argument detected, returning TRUE"
severity WARNING;
return TRUE;
end if;
return not(SIGNED_EQUAL(RESIZE(L, SIZE), RESIZE(R, SIZE)));
end "/=";
-- Id: C.33
function "/=" (L: NATURAL; R: UNSIGNED) return BOOLEAN is
begin
if (R'LENGTH < 1) then
assert NO_WARNING
report "NUMERIC_BIT.""/="": null argument detected, returning TRUE"
severity WARNING;
return TRUE;
end if;
if UNSIGNED_NUM_BITS(L) > R'LENGTH then return TRUE;
end if;
return not(UNSIGNED_EQUAL(TO_UNSIGNED(L, R'LENGTH), R));
end "/=";
-- Id: C.34
function "/=" (L: INTEGER; R: SIGNED) return BOOLEAN is
begin
if (R'LENGTH < 1) then
assert NO_WARNING
report "NUMERIC_BIT.""/="": null argument detected, returning TRUE"
severity WARNING;
return TRUE;
end if;
if SIGNED_NUM_BITS(L) > R'LENGTH then return TRUE;
end if;
return not(SIGNED_EQUAL(TO_SIGNED(L, R'LENGTH), R));
end "/=";
-- Id: C.35
function "/=" (L: UNSIGNED; R: NATURAL) return BOOLEAN is
begin
if (L'LENGTH < 1) then
assert NO_WARNING
report "NUMERIC_BIT.""/="": null argument detected, returning TRUE"
severity WARNING;
return TRUE;
end if;
if UNSIGNED_NUM_BITS(R) > L'LENGTH then return TRUE;
end if;
return not(UNSIGNED_EQUAL(L, TO_UNSIGNED(R, L'LENGTH)));
end "/=";
-- Id: C.36
function "/=" (L: SIGNED; R: INTEGER) return BOOLEAN is
begin
if (L'LENGTH < 1) then
assert NO_WARNING
report "NUMERIC_BIT.""/="": null argument detected, returning TRUE"
severity WARNING;
return TRUE;
end if;
if SIGNED_NUM_BITS(R) > L'LENGTH then return TRUE;
end if;
return not(SIGNED_EQUAL(L, TO_SIGNED(R, L'LENGTH)));
end "/=";
--============================================================================
-- Id: S.1
function SHIFT_LEFT (ARG: UNSIGNED; COUNT: NATURAL) return UNSIGNED is
begin
if (ARG'LENGTH < 1) then return NAU;
end if;
return UNSIGNED(XSLL(BIT_VECTOR(ARG), COUNT));
end SHIFT_LEFT;
-- Id: S.2
function SHIFT_RIGHT (ARG: UNSIGNED; COUNT: NATURAL) return UNSIGNED is
begin
if (ARG'LENGTH < 1) then return NAU;
end if;
return UNSIGNED(XSRL(BIT_VECTOR(ARG), COUNT));
end SHIFT_RIGHT;
-- Id: S.3
function SHIFT_LEFT (ARG: SIGNED; COUNT: NATURAL) return SIGNED is
begin
if (ARG'LENGTH < 1) then return NAS;
end if;
return SIGNED(XSLL(BIT_VECTOR(ARG), COUNT));
end SHIFT_LEFT;
-- Id: S.4
function SHIFT_RIGHT (ARG: SIGNED; COUNT: NATURAL) return SIGNED is
begin
if (ARG'LENGTH < 1) then return NAS;
end if;
return SIGNED(XSRA(BIT_VECTOR(ARG), COUNT));
end SHIFT_RIGHT;
--============================================================================
-- Id: S.5
function ROTATE_LEFT (ARG: UNSIGNED; COUNT: NATURAL) return UNSIGNED is
begin
if (ARG'LENGTH < 1) then return NAU;
end if;
return UNSIGNED(XROL(BIT_VECTOR(ARG), COUNT));
end ROTATE_LEFT;
-- Id: S.6
function ROTATE_RIGHT (ARG: UNSIGNED; COUNT: NATURAL) return UNSIGNED is
begin
if (ARG'LENGTH < 1) then return NAU;
end if;
return UNSIGNED(XROR(BIT_VECTOR(ARG), COUNT));
end ROTATE_RIGHT;
-- Id: S.7
function ROTATE_LEFT (ARG: SIGNED; COUNT: NATURAL) return SIGNED is
begin
if (ARG'LENGTH < 1) then return NAS;
end if;
return SIGNED(XROL(BIT_VECTOR(ARG), COUNT));
end ROTATE_LEFT;
-- Id: S.8
function ROTATE_RIGHT (ARG: SIGNED; COUNT: NATURAL) return SIGNED is
begin
if (ARG'LENGTH < 1) then return NAS;
end if;
return SIGNED(XROR(BIT_VECTOR(ARG), COUNT));
end ROTATE_RIGHT;
--============================================================================
------------------------------------------------------------------------------
-- Note : Function S.9 is not compatible with VHDL 1076-1987. Comment
-- out the function (declaration and body) for VHDL 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: S.9
function "sll" (ARG: UNSIGNED; COUNT: INTEGER) return UNSIGNED is
begin
if (COUNT >= 0) then
return SHIFT_LEFT(ARG, COUNT);
else
return SHIFT_RIGHT(ARG, -COUNT);
end if;
end "sll";
------------------------------------------------------------------------------
-- Note : Function S.10 is not compatible with VHDL 1076-1987. Comment
-- out the function (declaration and body) for VHDL 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: S.10
function "sll" (ARG: SIGNED; COUNT: INTEGER) return SIGNED is
begin
if (COUNT >= 0) then
return SHIFT_LEFT(ARG, COUNT);
else
return SIGNED(SHIFT_RIGHT(UNSIGNED(ARG), -COUNT));
end if;
end "sll";
------------------------------------------------------------------------------
-- Note : Function S.11 is not compatible with VHDL 1076-1987. Comment
-- out the function (declaration and body) for VHDL 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: S.11
function "srl" (ARG: UNSIGNED; COUNT: INTEGER) return UNSIGNED is
begin
if (COUNT >= 0) then
return SHIFT_RIGHT(ARG, COUNT);
else
return SHIFT_LEFT(ARG, -COUNT);
end if;
end "srl";
------------------------------------------------------------------------------
-- Note : Function S.12 is not compatible with VHDL 1076-1987. Comment
-- out the function (declaration and body) for VHDL 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: S.12
function "srl" (ARG: SIGNED; COUNT: INTEGER) return SIGNED is
begin
if (COUNT >= 0) then
return SIGNED(SHIFT_RIGHT(UNSIGNED(ARG), COUNT));
else
return SHIFT_LEFT(ARG, -COUNT);
end if;
end "srl";
------------------------------------------------------------------------------
-- Note : Function S.13 is not compatible with VHDL 1076-1987. Comment
-- out the function (declaration and body) for VHDL 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: S.13
function "rol" (ARG: UNSIGNED; COUNT: INTEGER) return UNSIGNED is
begin
if (COUNT >= 0) then
return ROTATE_LEFT(ARG, COUNT);
else
return ROTATE_RIGHT(ARG, -COUNT);
end if;
end "rol";
------------------------------------------------------------------------------
-- Note : Function S.14 is not compatible with VHDL 1076-1987. Comment
-- out the function (declaration and body) for VHDL 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: S.14
function "rol" (ARG: SIGNED; COUNT: INTEGER) return SIGNED is
begin
if (COUNT >= 0) then
return ROTATE_LEFT(ARG, COUNT);
else
return ROTATE_RIGHT(ARG, -COUNT);
end if;
end "rol";
------------------------------------------------------------------------------
-- Note : Function S.15 is not compatible with VHDL 1076-1987. Comment
-- out the function (declaration and body) for VHDL 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: S.15
function "ror" (ARG: UNSIGNED; COUNT: INTEGER) return UNSIGNED is
begin
if (COUNT >= 0) then
return ROTATE_RIGHT(ARG, COUNT);
else
return ROTATE_LEFT(ARG, -COUNT);
end if;
end "ror";
------------------------------------------------------------------------------
-- Note : Function S.16 is not compatible with VHDL 1076-1987. Comment
-- out the function (declaration and body) for VHDL 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: S.16
function "ror" (ARG: SIGNED; COUNT: INTEGER) return SIGNED is
begin
if (COUNT >= 0) then
return ROTATE_RIGHT(ARG, COUNT);
else
return ROTATE_LEFT(ARG, -COUNT);
end if;
end "ror";
--============================================================================
-- Id: D.1
function TO_INTEGER (ARG: UNSIGNED) return NATURAL is
constant ARG_LEFT: INTEGER := ARG'LENGTH-1;
alias XARG: UNSIGNED(ARG_LEFT downto 0) is ARG;
variable RESULT: NATURAL := 0;
begin
if (ARG'LENGTH < 1) then
assert NO_WARNING
report "NUMERIC_BIT.TO_INTEGER: null detected, returning 0"
severity WARNING;
return 0;
end if;
for I in XARG'RANGE loop
RESULT := RESULT+RESULT;
if XARG(I) = '1' then
RESULT := RESULT + 1;
end if;
end loop;
return RESULT;
end TO_INTEGER;
-- Id: D.2
function TO_INTEGER (ARG: SIGNED) return INTEGER is
begin
if (ARG'LENGTH < 1) then
assert NO_WARNING
report "NUMERIC_BIT.TO_INTEGER: null detected, returning 0"
severity WARNING;
return 0;
end if;
if ARG(ARG'LEFT) = '0' then
return TO_INTEGER(UNSIGNED(ARG));
else
return (- (TO_INTEGER(UNSIGNED(- (ARG + 1)))) -1);
end if;
end TO_INTEGER;
-- Id: D.3
function TO_UNSIGNED (ARG, SIZE: NATURAL) return UNSIGNED is
variable RESULT: UNSIGNED(SIZE-1 downto 0);
variable I_VAL: NATURAL := ARG;
begin
if (SIZE < 1) then return NAU;
end if;
for I in 0 to RESULT'LEFT loop
if (I_VAL mod 2) = 0 then
RESULT(I) := '0';
else RESULT(I) := '1';
end if;
I_VAL := I_VAL/2;
end loop;
if not(I_VAL =0) then
assert NO_WARNING
report "NUMERIC_BIT.TO_UNSIGNED: vector truncated"
severity WARNING;
end if;
return RESULT;
end TO_UNSIGNED;
-- Id: D.4
function TO_SIGNED (ARG: INTEGER;
SIZE: NATURAL) return SIGNED is
variable RESULT: SIGNED(SIZE-1 downto 0);
variable B_VAL: BIT := '0';
variable I_VAL: INTEGER := ARG;
begin
if (SIZE < 1) then return NAS;
end if;
if (ARG < 0) then
B_VAL := '1';
I_VAL := -(ARG+1);
end if;
for I in 0 to RESULT'LEFT loop
if (I_VAL mod 2) = 0 then
RESULT(I) := B_VAL;
else
RESULT(I) := not B_VAL;
end if;
I_VAL := I_VAL/2;
end loop;
if ((I_VAL/=0) or (B_VAL/=RESULT(RESULT'LEFT))) then
assert NO_WARNING
report "NUMERIC_BIT.TO_SIGNED: vector truncated"
severity WARNING;
end if;
return RESULT;
end TO_SIGNED;
--============================================================================
-- Id: R.1
function RESIZE (ARG: SIGNED; NEW_SIZE: NATURAL) return SIGNED is
alias INVEC: SIGNED(ARG'LENGTH-1 downto 0) is ARG;
variable RESULT: SIGNED(NEW_SIZE-1 downto 0) := (others => '0');
constant BOUND: INTEGER := MIN(ARG'LENGTH, RESULT'LENGTH)-2;
begin
if (NEW_SIZE < 1) then return NAS;
end if;
if (ARG'LENGTH = 0) then return RESULT;
end if;
RESULT := (others => ARG(ARG'LEFT));
if BOUND >= 0 then
RESULT(BOUND downto 0) := INVEC(BOUND downto 0);
end if;
return RESULT;
end RESIZE;
-- Id: R.2
function RESIZE (ARG: UNSIGNED; NEW_SIZE: NATURAL) return UNSIGNED is
constant ARG_LEFT: INTEGER := ARG'LENGTH-1;
alias XARG: UNSIGNED(ARG_LEFT downto 0) is ARG;
variable RESULT: UNSIGNED(NEW_SIZE-1 downto 0) := (others => '0');
begin
if (NEW_SIZE < 1) then return NAU;
end if;
if XARG'LENGTH =0 then return RESULT;
end if;
if (RESULT'LENGTH < ARG'LENGTH) then
RESULT(RESULT'LEFT downto 0) := XARG(RESULT'LEFT downto 0);
else
RESULT(RESULT'LEFT downto XARG'LEFT+1) := (others => '0');
RESULT(XARG'LEFT downto 0) := XARG;
end if;
return RESULT;
end RESIZE;
--============================================================================
-- Id: L.1
function "not" (L: UNSIGNED) return UNSIGNED is
variable RESULT: UNSIGNED(L'LENGTH-1 downto 0);
begin
RESULT := UNSIGNED(not(BIT_VECTOR(L)));
return RESULT;
end "not";
-- Id: L.2
function "and" (L, R: UNSIGNED) return UNSIGNED is
variable RESULT: UNSIGNED(L'LENGTH-1 downto 0);
begin
RESULT := UNSIGNED(BIT_VECTOR(L) and BIT_VECTOR(R));
return RESULT;
end "and";
-- Id: L.3
function "or" (L, R: UNSIGNED) return UNSIGNED is
variable RESULT: UNSIGNED(L'LENGTH-1 downto 0);
begin
RESULT := UNSIGNED(BIT_VECTOR(L) or BIT_VECTOR(R));
return RESULT;
end "or";
-- Id: L.4
function "nand" (L, R: UNSIGNED) return UNSIGNED is
variable RESULT: UNSIGNED(L'LENGTH-1 downto 0);
begin
RESULT := UNSIGNED(BIT_VECTOR(L) nand BIT_VECTOR(R));
return RESULT;
end "nand";
-- Id: L.5
function "nor" (L, R: UNSIGNED) return UNSIGNED is
variable RESULT: UNSIGNED(L'LENGTH-1 downto 0);
begin
RESULT := UNSIGNED(BIT_VECTOR(L) nor BIT_VECTOR(R));
return RESULT;
end "nor";
-- Id: L.6
function "xor" (L, R: UNSIGNED) return UNSIGNED is
variable RESULT: UNSIGNED(L'LENGTH-1 downto 0);
begin
RESULT := UNSIGNED(BIT_VECTOR(L) xor BIT_VECTOR(R));
return RESULT;
end "xor";
------------------------------------------------------------------------------
-- Note : Function L.7 is not compatible with VHDL 1076-1987. Comment
-- out the function (declaration and body) for VHDL 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: L.7
function "xnor" (L, R: UNSIGNED) return UNSIGNED is
variable RESULT: UNSIGNED(L'LENGTH-1 downto 0);
begin
RESULT := UNSIGNED(BIT_VECTOR(L) xnor BIT_VECTOR(R));
return RESULT;
end "xnor";
-- Id: L.8
function "not" (L: SIGNED) return SIGNED is
variable RESULT: SIGNED(L'LENGTH-1 downto 0);
begin
RESULT := SIGNED(not(BIT_VECTOR(L)));
return RESULT;
end "not";
-- Id: L.9
function "and" (L, R: SIGNED) return SIGNED is
variable RESULT: SIGNED(L'LENGTH-1 downto 0);
begin
RESULT := SIGNED(BIT_VECTOR(L) and BIT_VECTOR(R));
return RESULT;
end "and";
-- Id: L.10
function "or" (L, R: SIGNED) return SIGNED is
variable RESULT: SIGNED(L'LENGTH-1 downto 0);
begin
RESULT := SIGNED(BIT_VECTOR(L) or BIT_VECTOR(R));
return RESULT;
end "or";
-- Id: L.11
function "nand" (L, R: SIGNED) return SIGNED is
variable RESULT: SIGNED(L'LENGTH-1 downto 0);
begin
RESULT := SIGNED(BIT_VECTOR(L) nand BIT_VECTOR(R));
return RESULT;
end "nand";
-- Id: L.12
function "nor" (L, R: SIGNED) return SIGNED is
variable RESULT: SIGNED(L'LENGTH-1 downto 0);
begin
RESULT := SIGNED(BIT_VECTOR(L) nor BIT_VECTOR(R));
return RESULT;
end "nor";
-- Id: L.13
function "xor" (L, R: SIGNED) return SIGNED is
variable RESULT: SIGNED(L'LENGTH-1 downto 0);
begin
RESULT := SIGNED(BIT_VECTOR(L) xor BIT_VECTOR(R));
return RESULT;
end "xor";
------------------------------------------------------------------------------
-- Note : Function L.14 is not compatible with VHDL 1076-1987. Comment
-- out the function (declaration and body) for VHDL 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: L.14
function "xnor" (L, R: SIGNED) return SIGNED is
variable RESULT: SIGNED(L'LENGTH-1 downto 0);
begin
RESULT := SIGNED(BIT_VECTOR(L) xnor BIT_VECTOR(R));
return RESULT;
end "xnor";
--============================================================================
-- Id: E.1
function RISING_EDGE (signal S: BIT) return BOOLEAN is
begin
return S'EVENT and S = '1';
end RISING_EDGE;
-- Id: E.2
function FALLING_EDGE (signal S: BIT) return BOOLEAN is
begin
return S'EVENT and S = '0';
end FALLING_EDGE;
--============================================================================
end NUMERIC_BIT;
| gpl-3.0 | 9fd386f5773888af3d6110630b630f81 | 0.565455 | 3.901762 | false | false | false | false |
SamuelLBau/Pool-Shot-Tracking-using-FPGA | examples/array_sum/solution1/syn/vhdl/array_sum.vhd | 1 | 65,541 | -- ==============================================================
-- RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2015.4
-- Copyright (C) 2015 Xilinx Inc. All rights reserved.
--
-- ===========================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity array_sum is
port (
ap_clk : IN STD_LOGIC;
ap_rst : IN STD_LOGIC;
ap_start : IN STD_LOGIC;
ap_done : OUT STD_LOGIC;
ap_idle : OUT STD_LOGIC;
ap_ready : OUT STD_LOGIC;
array_r_address0 : OUT STD_LOGIC_VECTOR (5 downto 0);
array_r_ce0 : OUT STD_LOGIC;
array_r_q0 : IN STD_LOGIC_VECTOR (31 downto 0);
array_r_address1 : OUT STD_LOGIC_VECTOR (5 downto 0);
array_r_ce1 : OUT STD_LOGIC;
array_r_q1 : IN STD_LOGIC_VECTOR (31 downto 0);
length_r : IN STD_LOGIC_VECTOR (31 downto 0);
ap_return : OUT STD_LOGIC_VECTOR (31 downto 0) );
end;
architecture behav of array_sum is
attribute CORE_GENERATION_INFO : STRING;
attribute CORE_GENERATION_INFO of behav : architecture is
"array_sum,hls_ip_2015_4,{HLS_INPUT_TYPE=c,HLS_INPUT_FLOAT=0,HLS_INPUT_FIXED=0,HLS_INPUT_PART=xc7vx690tffg1761-2,HLS_INPUT_CLOCK=10.000000,HLS_INPUT_ARCH=others,HLS_SYN_CLOCK=7.820000,HLS_SYN_LAT=33,HLS_SYN_TPT=none,HLS_SYN_MEM=0,HLS_SYN_DSP=0,HLS_SYN_FF=386,HLS_SYN_LUT=372}";
constant ap_const_logic_1 : STD_LOGIC := '1';
constant ap_const_logic_0 : STD_LOGIC := '0';
constant ap_ST_st1_fsm_0 : STD_LOGIC_VECTOR (33 downto 0) := "0000000000000000000000000000000001";
constant ap_ST_st2_fsm_1 : STD_LOGIC_VECTOR (33 downto 0) := "0000000000000000000000000000000010";
constant ap_ST_st3_fsm_2 : STD_LOGIC_VECTOR (33 downto 0) := "0000000000000000000000000000000100";
constant ap_ST_st4_fsm_3 : STD_LOGIC_VECTOR (33 downto 0) := "0000000000000000000000000000001000";
constant ap_ST_st5_fsm_4 : STD_LOGIC_VECTOR (33 downto 0) := "0000000000000000000000000000010000";
constant ap_ST_st6_fsm_5 : STD_LOGIC_VECTOR (33 downto 0) := "0000000000000000000000000000100000";
constant ap_ST_st7_fsm_6 : STD_LOGIC_VECTOR (33 downto 0) := "0000000000000000000000000001000000";
constant ap_ST_st8_fsm_7 : STD_LOGIC_VECTOR (33 downto 0) := "0000000000000000000000000010000000";
constant ap_ST_st9_fsm_8 : STD_LOGIC_VECTOR (33 downto 0) := "0000000000000000000000000100000000";
constant ap_ST_st10_fsm_9 : STD_LOGIC_VECTOR (33 downto 0) := "0000000000000000000000001000000000";
constant ap_ST_st11_fsm_10 : STD_LOGIC_VECTOR (33 downto 0) := "0000000000000000000000010000000000";
constant ap_ST_st12_fsm_11 : STD_LOGIC_VECTOR (33 downto 0) := "0000000000000000000000100000000000";
constant ap_ST_st13_fsm_12 : STD_LOGIC_VECTOR (33 downto 0) := "0000000000000000000001000000000000";
constant ap_ST_st14_fsm_13 : STD_LOGIC_VECTOR (33 downto 0) := "0000000000000000000010000000000000";
constant ap_ST_st15_fsm_14 : STD_LOGIC_VECTOR (33 downto 0) := "0000000000000000000100000000000000";
constant ap_ST_st16_fsm_15 : STD_LOGIC_VECTOR (33 downto 0) := "0000000000000000001000000000000000";
constant ap_ST_st17_fsm_16 : STD_LOGIC_VECTOR (33 downto 0) := "0000000000000000010000000000000000";
constant ap_ST_st18_fsm_17 : STD_LOGIC_VECTOR (33 downto 0) := "0000000000000000100000000000000000";
constant ap_ST_st19_fsm_18 : STD_LOGIC_VECTOR (33 downto 0) := "0000000000000001000000000000000000";
constant ap_ST_st20_fsm_19 : STD_LOGIC_VECTOR (33 downto 0) := "0000000000000010000000000000000000";
constant ap_ST_st21_fsm_20 : STD_LOGIC_VECTOR (33 downto 0) := "0000000000000100000000000000000000";
constant ap_ST_st22_fsm_21 : STD_LOGIC_VECTOR (33 downto 0) := "0000000000001000000000000000000000";
constant ap_ST_st23_fsm_22 : STD_LOGIC_VECTOR (33 downto 0) := "0000000000010000000000000000000000";
constant ap_ST_st24_fsm_23 : STD_LOGIC_VECTOR (33 downto 0) := "0000000000100000000000000000000000";
constant ap_ST_st25_fsm_24 : STD_LOGIC_VECTOR (33 downto 0) := "0000000001000000000000000000000000";
constant ap_ST_st26_fsm_25 : STD_LOGIC_VECTOR (33 downto 0) := "0000000010000000000000000000000000";
constant ap_ST_st27_fsm_26 : STD_LOGIC_VECTOR (33 downto 0) := "0000000100000000000000000000000000";
constant ap_ST_st28_fsm_27 : STD_LOGIC_VECTOR (33 downto 0) := "0000001000000000000000000000000000";
constant ap_ST_st29_fsm_28 : STD_LOGIC_VECTOR (33 downto 0) := "0000010000000000000000000000000000";
constant ap_ST_st30_fsm_29 : STD_LOGIC_VECTOR (33 downto 0) := "0000100000000000000000000000000000";
constant ap_ST_st31_fsm_30 : STD_LOGIC_VECTOR (33 downto 0) := "0001000000000000000000000000000000";
constant ap_ST_st32_fsm_31 : STD_LOGIC_VECTOR (33 downto 0) := "0010000000000000000000000000000000";
constant ap_ST_st33_fsm_32 : STD_LOGIC_VECTOR (33 downto 0) := "0100000000000000000000000000000000";
constant ap_ST_st34_fsm_33 : STD_LOGIC_VECTOR (33 downto 0) := "1000000000000000000000000000000000";
constant ap_const_lv32_0 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000000";
constant ap_const_lv1_1 : STD_LOGIC_VECTOR (0 downto 0) := "1";
constant ap_const_lv32_1 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000001";
constant ap_const_lv32_3 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000011";
constant ap_const_lv32_7 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000111";
constant ap_const_lv32_9 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001001";
constant ap_const_lv32_B : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001011";
constant ap_const_lv32_F : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001111";
constant ap_const_lv32_13 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000010011";
constant ap_const_lv32_17 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000010111";
constant ap_const_lv32_19 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000011001";
constant ap_const_lv32_1B : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000011011";
constant ap_const_lv32_1F : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000011111";
constant ap_const_lv32_5 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000101";
constant ap_const_lv32_D : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001101";
constant ap_const_lv32_11 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000010001";
constant ap_const_lv32_15 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000010101";
constant ap_const_lv32_1D : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000011101";
constant ap_const_lv32_6 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000110";
constant ap_const_lv32_E : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001110";
constant ap_const_lv32_12 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000010010";
constant ap_const_lv32_16 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000010110";
constant ap_const_lv32_1E : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000011110";
constant ap_const_lv32_2 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000010";
constant ap_const_lv32_A : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001010";
constant ap_const_lv32_1A : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000011010";
constant ap_const_lv32_4 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000100";
constant ap_const_lv32_C : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001100";
constant ap_const_lv32_1C : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000011100";
constant ap_const_lv32_8 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001000";
constant ap_const_lv32_10 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000010000";
constant ap_const_lv32_14 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000010100";
constant ap_const_lv32_18 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000011000";
constant ap_const_lv32_20 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000100000";
constant ap_const_lv64_0 : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000";
constant ap_const_lv64_1 : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000000000000000000000000000000000000000000000001";
constant ap_const_lv64_2 : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000000000000000000000000000000000000000000000010";
constant ap_const_lv64_3 : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000000000000000000000000000000000000000000000011";
constant ap_const_lv64_4 : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000000000000000000000000000000000000000000000100";
constant ap_const_lv64_5 : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000000000000000000000000000000000000000000000101";
constant ap_const_lv64_6 : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000000000000000000000000000000000000000000000110";
constant ap_const_lv64_7 : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000000000000000000000000000000000000000000000111";
constant ap_const_lv64_8 : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000000000000000000000000000000000000000000001000";
constant ap_const_lv64_9 : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000000000000000000000000000000000000000000001001";
constant ap_const_lv64_A : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000000000000000000000000000000000000000000001010";
constant ap_const_lv64_B : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000000000000000000000000000000000000000000001011";
constant ap_const_lv64_C : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000000000000000000000000000000000000000000001100";
constant ap_const_lv64_D : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000000000000000000000000000000000000000000001101";
constant ap_const_lv64_E : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000000000000000000000000000000000000000000001110";
constant ap_const_lv64_F : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000000000000000000000000000000000000000000001111";
constant ap_const_lv64_10 : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000000000000000000000000000000000000000000010000";
constant ap_const_lv64_11 : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000000000000000000000000000000000000000000010001";
constant ap_const_lv64_12 : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000000000000000000000000000000000000000000010010";
constant ap_const_lv64_13 : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000000000000000000000000000000000000000000010011";
constant ap_const_lv64_14 : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000000000000000000000000000000000000000000010100";
constant ap_const_lv64_15 : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000000000000000000000000000000000000000000010101";
constant ap_const_lv64_16 : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000000000000000000000000000000000000000000010110";
constant ap_const_lv64_17 : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000000000000000000000000000000000000000000010111";
constant ap_const_lv64_18 : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000000000000000000000000000000000000000000011000";
constant ap_const_lv64_19 : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000000000000000000000000000000000000000000011001";
constant ap_const_lv64_1A : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000000000000000000000000000000000000000000011010";
constant ap_const_lv64_1B : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000000000000000000000000000000000000000000011011";
constant ap_const_lv64_1C : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000000000000000000000000000000000000000000011100";
constant ap_const_lv64_1D : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000000000000000000000000000000000000000000011101";
constant ap_const_lv64_1E : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000000000000000000000000000000000000000000011110";
constant ap_const_lv64_1F : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000000000000000000000000000000000000000000011111";
constant ap_const_lv64_20 : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000000000000000000000000000000000000000000100000";
constant ap_const_lv64_21 : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000000000000000000000000000000000000000000100001";
constant ap_const_lv64_22 : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000000000000000000000000000000000000000000100010";
constant ap_const_lv64_23 : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000000000000000000000000000000000000000000100011";
constant ap_const_lv64_24 : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000000000000000000000000000000000000000000100100";
constant ap_const_lv64_25 : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000000000000000000000000000000000000000000100101";
constant ap_const_lv64_26 : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000000000000000000000000000000000000000000100110";
constant ap_const_lv64_27 : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000000000000000000000000000000000000000000100111";
constant ap_const_lv64_28 : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000000000000000000000000000000000000000000101000";
constant ap_const_lv64_29 : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000000000000000000000000000000000000000000101001";
constant ap_const_lv64_2A : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000000000000000000000000000000000000000000101010";
constant ap_const_lv64_2B : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000000000000000000000000000000000000000000101011";
constant ap_const_lv64_2C : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000000000000000000000000000000000000000000101100";
constant ap_const_lv64_2D : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000000000000000000000000000000000000000000101101";
constant ap_const_lv64_2E : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000000000000000000000000000000000000000000101110";
constant ap_const_lv64_2F : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000000000000000000000000000000000000000000101111";
constant ap_const_lv64_30 : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000000000000000000000000000000000000000000110000";
constant ap_const_lv64_31 : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000000000000000000000000000000000000000000110001";
constant ap_const_lv64_32 : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000000000000000000000000000000000000000000110010";
constant ap_const_lv64_33 : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000000000000000000000000000000000000000000110011";
constant ap_const_lv64_34 : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000000000000000000000000000000000000000000110100";
constant ap_const_lv64_35 : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000000000000000000000000000000000000000000110101";
constant ap_const_lv64_36 : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000000000000000000000000000000000000000000110110";
constant ap_const_lv64_37 : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000000000000000000000000000000000000000000110111";
constant ap_const_lv64_38 : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000000000000000000000000000000000000000000111000";
constant ap_const_lv64_39 : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000000000000000000000000000000000000000000111001";
constant ap_const_lv64_3A : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000000000000000000000000000000000000000000111010";
constant ap_const_lv64_3B : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000000000000000000000000000000000000000000111011";
constant ap_const_lv64_3C : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000000000000000000000000000000000000000000111100";
constant ap_const_lv64_3D : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000000000000000000000000000000000000000000111101";
constant ap_const_lv64_3E : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000000000000000000000000000000000000000000111110";
constant ap_const_lv64_3F : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000000000000000000000000000000000000000000111111";
constant ap_const_lv32_21 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000100001";
signal ap_CS_fsm : STD_LOGIC_VECTOR (33 downto 0) := "0000000000000000000000000000000001";
attribute fsm_encoding : string;
attribute fsm_encoding of ap_CS_fsm : signal is "none";
signal ap_sig_cseq_ST_st1_fsm_0 : STD_LOGIC;
signal ap_sig_bdd_50 : BOOLEAN;
signal reg_729 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_sig_cseq_ST_st2_fsm_1 : STD_LOGIC;
signal ap_sig_bdd_74 : BOOLEAN;
signal ap_sig_cseq_ST_st4_fsm_3 : STD_LOGIC;
signal ap_sig_bdd_81 : BOOLEAN;
signal ap_sig_cseq_ST_st8_fsm_7 : STD_LOGIC;
signal ap_sig_bdd_89 : BOOLEAN;
signal ap_sig_cseq_ST_st10_fsm_9 : STD_LOGIC;
signal ap_sig_bdd_97 : BOOLEAN;
signal ap_sig_cseq_ST_st12_fsm_11 : STD_LOGIC;
signal ap_sig_bdd_105 : BOOLEAN;
signal ap_sig_cseq_ST_st16_fsm_15 : STD_LOGIC;
signal ap_sig_bdd_113 : BOOLEAN;
signal ap_sig_cseq_ST_st20_fsm_19 : STD_LOGIC;
signal ap_sig_bdd_121 : BOOLEAN;
signal ap_sig_cseq_ST_st24_fsm_23 : STD_LOGIC;
signal ap_sig_bdd_129 : BOOLEAN;
signal ap_sig_cseq_ST_st26_fsm_25 : STD_LOGIC;
signal ap_sig_bdd_137 : BOOLEAN;
signal ap_sig_cseq_ST_st28_fsm_27 : STD_LOGIC;
signal ap_sig_bdd_145 : BOOLEAN;
signal ap_sig_cseq_ST_st32_fsm_31 : STD_LOGIC;
signal ap_sig_bdd_153 : BOOLEAN;
signal reg_733 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_723_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal reg_737 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_sig_cseq_ST_st6_fsm_5 : STD_LOGIC;
signal ap_sig_bdd_164 : BOOLEAN;
signal ap_sig_cseq_ST_st14_fsm_13 : STD_LOGIC;
signal ap_sig_bdd_171 : BOOLEAN;
signal ap_sig_cseq_ST_st18_fsm_17 : STD_LOGIC;
signal ap_sig_bdd_179 : BOOLEAN;
signal ap_sig_cseq_ST_st22_fsm_21 : STD_LOGIC;
signal ap_sig_bdd_187 : BOOLEAN;
signal ap_sig_cseq_ST_st30_fsm_29 : STD_LOGIC;
signal ap_sig_bdd_195 : BOOLEAN;
signal reg_741 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_sig_cseq_ST_st7_fsm_6 : STD_LOGIC;
signal ap_sig_bdd_204 : BOOLEAN;
signal ap_sig_cseq_ST_st15_fsm_14 : STD_LOGIC;
signal ap_sig_bdd_211 : BOOLEAN;
signal ap_sig_cseq_ST_st19_fsm_18 : STD_LOGIC;
signal ap_sig_bdd_219 : BOOLEAN;
signal ap_sig_cseq_ST_st23_fsm_22 : STD_LOGIC;
signal ap_sig_bdd_227 : BOOLEAN;
signal ap_sig_cseq_ST_st31_fsm_30 : STD_LOGIC;
signal ap_sig_bdd_235 : BOOLEAN;
signal grp_fu_751_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal reg_769 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_sig_cseq_ST_st3_fsm_2 : STD_LOGIC;
signal ap_sig_bdd_245 : BOOLEAN;
signal ap_sig_cseq_ST_st11_fsm_10 : STD_LOGIC;
signal ap_sig_bdd_252 : BOOLEAN;
signal ap_sig_cseq_ST_st27_fsm_26 : STD_LOGIC;
signal ap_sig_bdd_260 : BOOLEAN;
signal reg_773 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_sig_cseq_ST_st5_fsm_4 : STD_LOGIC;
signal ap_sig_bdd_269 : BOOLEAN;
signal ap_sig_cseq_ST_st13_fsm_12 : STD_LOGIC;
signal ap_sig_bdd_276 : BOOLEAN;
signal ap_sig_cseq_ST_st29_fsm_28 : STD_LOGIC;
signal ap_sig_bdd_284 : BOOLEAN;
signal ap_sig_cseq_ST_st9_fsm_8 : STD_LOGIC;
signal ap_sig_bdd_329 : BOOLEAN;
signal grp_fu_783_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp1_reg_898 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_sig_cseq_ST_st17_fsm_16 : STD_LOGIC;
signal ap_sig_bdd_370 : BOOLEAN;
signal tmp16_reg_983 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_sig_cseq_ST_st21_fsm_20 : STD_LOGIC;
signal ap_sig_bdd_394 : BOOLEAN;
signal grp_fu_763_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp33_reg_1028 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_sig_cseq_ST_st25_fsm_24 : STD_LOGIC;
signal ap_sig_bdd_419 : BOOLEAN;
signal tmp40_reg_1073 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp47_reg_1148 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_sig_cseq_ST_st33_fsm_32 : STD_LOGIC;
signal ap_sig_bdd_458 : BOOLEAN;
signal grp_fu_745_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_757_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_777_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_sig_cseq_ST_st34_fsm_33 : STD_LOGIC;
signal ap_sig_bdd_613 : BOOLEAN;
signal tmp32_fu_793_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp31_fu_797_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_fu_789_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_NS_fsm : STD_LOGIC_VECTOR (33 downto 0);
begin
-- the current state (ap_CS_fsm) of the state machine. --
ap_CS_fsm_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_CS_fsm <= ap_ST_st1_fsm_0;
else
ap_CS_fsm <= ap_NS_fsm;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st2_fsm_1) or (ap_const_logic_1 = ap_sig_cseq_ST_st4_fsm_3) or (ap_const_logic_1 = ap_sig_cseq_ST_st8_fsm_7) or (ap_const_logic_1 = ap_sig_cseq_ST_st10_fsm_9) or (ap_const_logic_1 = ap_sig_cseq_ST_st12_fsm_11) or (ap_const_logic_1 = ap_sig_cseq_ST_st16_fsm_15) or (ap_const_logic_1 = ap_sig_cseq_ST_st20_fsm_19) or (ap_const_logic_1 = ap_sig_cseq_ST_st24_fsm_23) or (ap_const_logic_1 = ap_sig_cseq_ST_st26_fsm_25) or (ap_const_logic_1 = ap_sig_cseq_ST_st28_fsm_27) or (ap_const_logic_1 = ap_sig_cseq_ST_st32_fsm_31))) then
reg_729 <= array_r_q0;
reg_733 <= array_r_q1;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st6_fsm_5) or (ap_const_logic_1 = ap_sig_cseq_ST_st14_fsm_13) or (ap_const_logic_1 = ap_sig_cseq_ST_st18_fsm_17) or (ap_const_logic_1 = ap_sig_cseq_ST_st22_fsm_21) or (ap_const_logic_1 = ap_sig_cseq_ST_st30_fsm_29))) then
reg_737 <= grp_fu_723_p2;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st7_fsm_6) or (ap_const_logic_1 = ap_sig_cseq_ST_st15_fsm_14) or (ap_const_logic_1 = ap_sig_cseq_ST_st19_fsm_18) or (ap_const_logic_1 = ap_sig_cseq_ST_st23_fsm_22) or (ap_const_logic_1 = ap_sig_cseq_ST_st31_fsm_30))) then
reg_741 <= grp_fu_723_p2;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st3_fsm_2) or (ap_const_logic_1 = ap_sig_cseq_ST_st11_fsm_10) or (ap_const_logic_1 = ap_sig_cseq_ST_st27_fsm_26))) then
reg_769 <= grp_fu_751_p2;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st5_fsm_4) or (ap_const_logic_1 = ap_sig_cseq_ST_st13_fsm_12) or (ap_const_logic_1 = ap_sig_cseq_ST_st29_fsm_28))) then
reg_773 <= grp_fu_751_p2;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_sig_cseq_ST_st17_fsm_16)) then
tmp16_reg_983 <= grp_fu_783_p2;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_sig_cseq_ST_st9_fsm_8)) then
tmp1_reg_898 <= grp_fu_783_p2;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_sig_cseq_ST_st21_fsm_20)) then
tmp33_reg_1028 <= grp_fu_763_p2;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_sig_cseq_ST_st25_fsm_24)) then
tmp40_reg_1073 <= grp_fu_763_p2;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_sig_cseq_ST_st33_fsm_32)) then
tmp47_reg_1148 <= grp_fu_783_p2;
end if;
end if;
end process;
-- the next state (ap_NS_fsm) of the state machine. --
ap_NS_fsm_assign_proc : process (ap_start, ap_CS_fsm)
begin
case ap_CS_fsm is
when ap_ST_st1_fsm_0 =>
if (not((ap_start = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st2_fsm_1;
else
ap_NS_fsm <= ap_ST_st1_fsm_0;
end if;
when ap_ST_st2_fsm_1 =>
ap_NS_fsm <= ap_ST_st3_fsm_2;
when ap_ST_st3_fsm_2 =>
ap_NS_fsm <= ap_ST_st4_fsm_3;
when ap_ST_st4_fsm_3 =>
ap_NS_fsm <= ap_ST_st5_fsm_4;
when ap_ST_st5_fsm_4 =>
ap_NS_fsm <= ap_ST_st6_fsm_5;
when ap_ST_st6_fsm_5 =>
ap_NS_fsm <= ap_ST_st7_fsm_6;
when ap_ST_st7_fsm_6 =>
ap_NS_fsm <= ap_ST_st8_fsm_7;
when ap_ST_st8_fsm_7 =>
ap_NS_fsm <= ap_ST_st9_fsm_8;
when ap_ST_st9_fsm_8 =>
ap_NS_fsm <= ap_ST_st10_fsm_9;
when ap_ST_st10_fsm_9 =>
ap_NS_fsm <= ap_ST_st11_fsm_10;
when ap_ST_st11_fsm_10 =>
ap_NS_fsm <= ap_ST_st12_fsm_11;
when ap_ST_st12_fsm_11 =>
ap_NS_fsm <= ap_ST_st13_fsm_12;
when ap_ST_st13_fsm_12 =>
ap_NS_fsm <= ap_ST_st14_fsm_13;
when ap_ST_st14_fsm_13 =>
ap_NS_fsm <= ap_ST_st15_fsm_14;
when ap_ST_st15_fsm_14 =>
ap_NS_fsm <= ap_ST_st16_fsm_15;
when ap_ST_st16_fsm_15 =>
ap_NS_fsm <= ap_ST_st17_fsm_16;
when ap_ST_st17_fsm_16 =>
ap_NS_fsm <= ap_ST_st18_fsm_17;
when ap_ST_st18_fsm_17 =>
ap_NS_fsm <= ap_ST_st19_fsm_18;
when ap_ST_st19_fsm_18 =>
ap_NS_fsm <= ap_ST_st20_fsm_19;
when ap_ST_st20_fsm_19 =>
ap_NS_fsm <= ap_ST_st21_fsm_20;
when ap_ST_st21_fsm_20 =>
ap_NS_fsm <= ap_ST_st22_fsm_21;
when ap_ST_st22_fsm_21 =>
ap_NS_fsm <= ap_ST_st23_fsm_22;
when ap_ST_st23_fsm_22 =>
ap_NS_fsm <= ap_ST_st24_fsm_23;
when ap_ST_st24_fsm_23 =>
ap_NS_fsm <= ap_ST_st25_fsm_24;
when ap_ST_st25_fsm_24 =>
ap_NS_fsm <= ap_ST_st26_fsm_25;
when ap_ST_st26_fsm_25 =>
ap_NS_fsm <= ap_ST_st27_fsm_26;
when ap_ST_st27_fsm_26 =>
ap_NS_fsm <= ap_ST_st28_fsm_27;
when ap_ST_st28_fsm_27 =>
ap_NS_fsm <= ap_ST_st29_fsm_28;
when ap_ST_st29_fsm_28 =>
ap_NS_fsm <= ap_ST_st30_fsm_29;
when ap_ST_st30_fsm_29 =>
ap_NS_fsm <= ap_ST_st31_fsm_30;
when ap_ST_st31_fsm_30 =>
ap_NS_fsm <= ap_ST_st32_fsm_31;
when ap_ST_st32_fsm_31 =>
ap_NS_fsm <= ap_ST_st33_fsm_32;
when ap_ST_st33_fsm_32 =>
ap_NS_fsm <= ap_ST_st34_fsm_33;
when ap_ST_st34_fsm_33 =>
ap_NS_fsm <= ap_ST_st1_fsm_0;
when others =>
ap_NS_fsm <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end case;
end process;
-- ap_done assign process. --
ap_done_assign_proc : process(ap_sig_cseq_ST_st34_fsm_33)
begin
if ((ap_const_logic_1 = ap_sig_cseq_ST_st34_fsm_33)) then
ap_done <= ap_const_logic_1;
else
ap_done <= ap_const_logic_0;
end if;
end process;
-- ap_idle assign process. --
ap_idle_assign_proc : process(ap_start, ap_sig_cseq_ST_st1_fsm_0)
begin
if ((not((ap_const_logic_1 = ap_start)) and (ap_const_logic_1 = ap_sig_cseq_ST_st1_fsm_0))) then
ap_idle <= ap_const_logic_1;
else
ap_idle <= ap_const_logic_0;
end if;
end process;
-- ap_ready assign process. --
ap_ready_assign_proc : process(ap_sig_cseq_ST_st34_fsm_33)
begin
if ((ap_const_logic_1 = ap_sig_cseq_ST_st34_fsm_33)) then
ap_ready <= ap_const_logic_1;
else
ap_ready <= ap_const_logic_0;
end if;
end process;
ap_return <= std_logic_vector(unsigned(tmp31_fu_797_p2) + unsigned(tmp_fu_789_p2));
-- ap_sig_bdd_105 assign process. --
ap_sig_bdd_105_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_105 <= (ap_const_lv1_1 = ap_CS_fsm(11 downto 11));
end process;
-- ap_sig_bdd_113 assign process. --
ap_sig_bdd_113_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_113 <= (ap_const_lv1_1 = ap_CS_fsm(15 downto 15));
end process;
-- ap_sig_bdd_121 assign process. --
ap_sig_bdd_121_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_121 <= (ap_const_lv1_1 = ap_CS_fsm(19 downto 19));
end process;
-- ap_sig_bdd_129 assign process. --
ap_sig_bdd_129_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_129 <= (ap_const_lv1_1 = ap_CS_fsm(23 downto 23));
end process;
-- ap_sig_bdd_137 assign process. --
ap_sig_bdd_137_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_137 <= (ap_const_lv1_1 = ap_CS_fsm(25 downto 25));
end process;
-- ap_sig_bdd_145 assign process. --
ap_sig_bdd_145_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_145 <= (ap_const_lv1_1 = ap_CS_fsm(27 downto 27));
end process;
-- ap_sig_bdd_153 assign process. --
ap_sig_bdd_153_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_153 <= (ap_const_lv1_1 = ap_CS_fsm(31 downto 31));
end process;
-- ap_sig_bdd_164 assign process. --
ap_sig_bdd_164_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_164 <= (ap_const_lv1_1 = ap_CS_fsm(5 downto 5));
end process;
-- ap_sig_bdd_171 assign process. --
ap_sig_bdd_171_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_171 <= (ap_const_lv1_1 = ap_CS_fsm(13 downto 13));
end process;
-- ap_sig_bdd_179 assign process. --
ap_sig_bdd_179_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_179 <= (ap_const_lv1_1 = ap_CS_fsm(17 downto 17));
end process;
-- ap_sig_bdd_187 assign process. --
ap_sig_bdd_187_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_187 <= (ap_const_lv1_1 = ap_CS_fsm(21 downto 21));
end process;
-- ap_sig_bdd_195 assign process. --
ap_sig_bdd_195_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_195 <= (ap_const_lv1_1 = ap_CS_fsm(29 downto 29));
end process;
-- ap_sig_bdd_204 assign process. --
ap_sig_bdd_204_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_204 <= (ap_const_lv1_1 = ap_CS_fsm(6 downto 6));
end process;
-- ap_sig_bdd_211 assign process. --
ap_sig_bdd_211_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_211 <= (ap_const_lv1_1 = ap_CS_fsm(14 downto 14));
end process;
-- ap_sig_bdd_219 assign process. --
ap_sig_bdd_219_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_219 <= (ap_const_lv1_1 = ap_CS_fsm(18 downto 18));
end process;
-- ap_sig_bdd_227 assign process. --
ap_sig_bdd_227_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_227 <= (ap_const_lv1_1 = ap_CS_fsm(22 downto 22));
end process;
-- ap_sig_bdd_235 assign process. --
ap_sig_bdd_235_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_235 <= (ap_const_lv1_1 = ap_CS_fsm(30 downto 30));
end process;
-- ap_sig_bdd_245 assign process. --
ap_sig_bdd_245_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_245 <= (ap_const_lv1_1 = ap_CS_fsm(2 downto 2));
end process;
-- ap_sig_bdd_252 assign process. --
ap_sig_bdd_252_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_252 <= (ap_const_lv1_1 = ap_CS_fsm(10 downto 10));
end process;
-- ap_sig_bdd_260 assign process. --
ap_sig_bdd_260_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_260 <= (ap_const_lv1_1 = ap_CS_fsm(26 downto 26));
end process;
-- ap_sig_bdd_269 assign process. --
ap_sig_bdd_269_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_269 <= (ap_const_lv1_1 = ap_CS_fsm(4 downto 4));
end process;
-- ap_sig_bdd_276 assign process. --
ap_sig_bdd_276_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_276 <= (ap_const_lv1_1 = ap_CS_fsm(12 downto 12));
end process;
-- ap_sig_bdd_284 assign process. --
ap_sig_bdd_284_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_284 <= (ap_const_lv1_1 = ap_CS_fsm(28 downto 28));
end process;
-- ap_sig_bdd_329 assign process. --
ap_sig_bdd_329_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_329 <= (ap_const_lv1_1 = ap_CS_fsm(8 downto 8));
end process;
-- ap_sig_bdd_370 assign process. --
ap_sig_bdd_370_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_370 <= (ap_const_lv1_1 = ap_CS_fsm(16 downto 16));
end process;
-- ap_sig_bdd_394 assign process. --
ap_sig_bdd_394_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_394 <= (ap_const_lv1_1 = ap_CS_fsm(20 downto 20));
end process;
-- ap_sig_bdd_419 assign process. --
ap_sig_bdd_419_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_419 <= (ap_const_lv1_1 = ap_CS_fsm(24 downto 24));
end process;
-- ap_sig_bdd_458 assign process. --
ap_sig_bdd_458_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_458 <= (ap_const_lv1_1 = ap_CS_fsm(32 downto 32));
end process;
-- ap_sig_bdd_50 assign process. --
ap_sig_bdd_50_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_50 <= (ap_CS_fsm(0 downto 0) = ap_const_lv1_1);
end process;
-- ap_sig_bdd_613 assign process. --
ap_sig_bdd_613_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_613 <= (ap_const_lv1_1 = ap_CS_fsm(33 downto 33));
end process;
-- ap_sig_bdd_74 assign process. --
ap_sig_bdd_74_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_74 <= (ap_const_lv1_1 = ap_CS_fsm(1 downto 1));
end process;
-- ap_sig_bdd_81 assign process. --
ap_sig_bdd_81_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_81 <= (ap_const_lv1_1 = ap_CS_fsm(3 downto 3));
end process;
-- ap_sig_bdd_89 assign process. --
ap_sig_bdd_89_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_89 <= (ap_const_lv1_1 = ap_CS_fsm(7 downto 7));
end process;
-- ap_sig_bdd_97 assign process. --
ap_sig_bdd_97_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_97 <= (ap_const_lv1_1 = ap_CS_fsm(9 downto 9));
end process;
-- ap_sig_cseq_ST_st10_fsm_9 assign process. --
ap_sig_cseq_ST_st10_fsm_9_assign_proc : process(ap_sig_bdd_97)
begin
if (ap_sig_bdd_97) then
ap_sig_cseq_ST_st10_fsm_9 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st10_fsm_9 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st11_fsm_10 assign process. --
ap_sig_cseq_ST_st11_fsm_10_assign_proc : process(ap_sig_bdd_252)
begin
if (ap_sig_bdd_252) then
ap_sig_cseq_ST_st11_fsm_10 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st11_fsm_10 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st12_fsm_11 assign process. --
ap_sig_cseq_ST_st12_fsm_11_assign_proc : process(ap_sig_bdd_105)
begin
if (ap_sig_bdd_105) then
ap_sig_cseq_ST_st12_fsm_11 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st12_fsm_11 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st13_fsm_12 assign process. --
ap_sig_cseq_ST_st13_fsm_12_assign_proc : process(ap_sig_bdd_276)
begin
if (ap_sig_bdd_276) then
ap_sig_cseq_ST_st13_fsm_12 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st13_fsm_12 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st14_fsm_13 assign process. --
ap_sig_cseq_ST_st14_fsm_13_assign_proc : process(ap_sig_bdd_171)
begin
if (ap_sig_bdd_171) then
ap_sig_cseq_ST_st14_fsm_13 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st14_fsm_13 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st15_fsm_14 assign process. --
ap_sig_cseq_ST_st15_fsm_14_assign_proc : process(ap_sig_bdd_211)
begin
if (ap_sig_bdd_211) then
ap_sig_cseq_ST_st15_fsm_14 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st15_fsm_14 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st16_fsm_15 assign process. --
ap_sig_cseq_ST_st16_fsm_15_assign_proc : process(ap_sig_bdd_113)
begin
if (ap_sig_bdd_113) then
ap_sig_cseq_ST_st16_fsm_15 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st16_fsm_15 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st17_fsm_16 assign process. --
ap_sig_cseq_ST_st17_fsm_16_assign_proc : process(ap_sig_bdd_370)
begin
if (ap_sig_bdd_370) then
ap_sig_cseq_ST_st17_fsm_16 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st17_fsm_16 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st18_fsm_17 assign process. --
ap_sig_cseq_ST_st18_fsm_17_assign_proc : process(ap_sig_bdd_179)
begin
if (ap_sig_bdd_179) then
ap_sig_cseq_ST_st18_fsm_17 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st18_fsm_17 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st19_fsm_18 assign process. --
ap_sig_cseq_ST_st19_fsm_18_assign_proc : process(ap_sig_bdd_219)
begin
if (ap_sig_bdd_219) then
ap_sig_cseq_ST_st19_fsm_18 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st19_fsm_18 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st1_fsm_0 assign process. --
ap_sig_cseq_ST_st1_fsm_0_assign_proc : process(ap_sig_bdd_50)
begin
if (ap_sig_bdd_50) then
ap_sig_cseq_ST_st1_fsm_0 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st1_fsm_0 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st20_fsm_19 assign process. --
ap_sig_cseq_ST_st20_fsm_19_assign_proc : process(ap_sig_bdd_121)
begin
if (ap_sig_bdd_121) then
ap_sig_cseq_ST_st20_fsm_19 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st20_fsm_19 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st21_fsm_20 assign process. --
ap_sig_cseq_ST_st21_fsm_20_assign_proc : process(ap_sig_bdd_394)
begin
if (ap_sig_bdd_394) then
ap_sig_cseq_ST_st21_fsm_20 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st21_fsm_20 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st22_fsm_21 assign process. --
ap_sig_cseq_ST_st22_fsm_21_assign_proc : process(ap_sig_bdd_187)
begin
if (ap_sig_bdd_187) then
ap_sig_cseq_ST_st22_fsm_21 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st22_fsm_21 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st23_fsm_22 assign process. --
ap_sig_cseq_ST_st23_fsm_22_assign_proc : process(ap_sig_bdd_227)
begin
if (ap_sig_bdd_227) then
ap_sig_cseq_ST_st23_fsm_22 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st23_fsm_22 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st24_fsm_23 assign process. --
ap_sig_cseq_ST_st24_fsm_23_assign_proc : process(ap_sig_bdd_129)
begin
if (ap_sig_bdd_129) then
ap_sig_cseq_ST_st24_fsm_23 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st24_fsm_23 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st25_fsm_24 assign process. --
ap_sig_cseq_ST_st25_fsm_24_assign_proc : process(ap_sig_bdd_419)
begin
if (ap_sig_bdd_419) then
ap_sig_cseq_ST_st25_fsm_24 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st25_fsm_24 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st26_fsm_25 assign process. --
ap_sig_cseq_ST_st26_fsm_25_assign_proc : process(ap_sig_bdd_137)
begin
if (ap_sig_bdd_137) then
ap_sig_cseq_ST_st26_fsm_25 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st26_fsm_25 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st27_fsm_26 assign process. --
ap_sig_cseq_ST_st27_fsm_26_assign_proc : process(ap_sig_bdd_260)
begin
if (ap_sig_bdd_260) then
ap_sig_cseq_ST_st27_fsm_26 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st27_fsm_26 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st28_fsm_27 assign process. --
ap_sig_cseq_ST_st28_fsm_27_assign_proc : process(ap_sig_bdd_145)
begin
if (ap_sig_bdd_145) then
ap_sig_cseq_ST_st28_fsm_27 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st28_fsm_27 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st29_fsm_28 assign process. --
ap_sig_cseq_ST_st29_fsm_28_assign_proc : process(ap_sig_bdd_284)
begin
if (ap_sig_bdd_284) then
ap_sig_cseq_ST_st29_fsm_28 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st29_fsm_28 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st2_fsm_1 assign process. --
ap_sig_cseq_ST_st2_fsm_1_assign_proc : process(ap_sig_bdd_74)
begin
if (ap_sig_bdd_74) then
ap_sig_cseq_ST_st2_fsm_1 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st2_fsm_1 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st30_fsm_29 assign process. --
ap_sig_cseq_ST_st30_fsm_29_assign_proc : process(ap_sig_bdd_195)
begin
if (ap_sig_bdd_195) then
ap_sig_cseq_ST_st30_fsm_29 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st30_fsm_29 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st31_fsm_30 assign process. --
ap_sig_cseq_ST_st31_fsm_30_assign_proc : process(ap_sig_bdd_235)
begin
if (ap_sig_bdd_235) then
ap_sig_cseq_ST_st31_fsm_30 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st31_fsm_30 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st32_fsm_31 assign process. --
ap_sig_cseq_ST_st32_fsm_31_assign_proc : process(ap_sig_bdd_153)
begin
if (ap_sig_bdd_153) then
ap_sig_cseq_ST_st32_fsm_31 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st32_fsm_31 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st33_fsm_32 assign process. --
ap_sig_cseq_ST_st33_fsm_32_assign_proc : process(ap_sig_bdd_458)
begin
if (ap_sig_bdd_458) then
ap_sig_cseq_ST_st33_fsm_32 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st33_fsm_32 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st34_fsm_33 assign process. --
ap_sig_cseq_ST_st34_fsm_33_assign_proc : process(ap_sig_bdd_613)
begin
if (ap_sig_bdd_613) then
ap_sig_cseq_ST_st34_fsm_33 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st34_fsm_33 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st3_fsm_2 assign process. --
ap_sig_cseq_ST_st3_fsm_2_assign_proc : process(ap_sig_bdd_245)
begin
if (ap_sig_bdd_245) then
ap_sig_cseq_ST_st3_fsm_2 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st3_fsm_2 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st4_fsm_3 assign process. --
ap_sig_cseq_ST_st4_fsm_3_assign_proc : process(ap_sig_bdd_81)
begin
if (ap_sig_bdd_81) then
ap_sig_cseq_ST_st4_fsm_3 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st4_fsm_3 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st5_fsm_4 assign process. --
ap_sig_cseq_ST_st5_fsm_4_assign_proc : process(ap_sig_bdd_269)
begin
if (ap_sig_bdd_269) then
ap_sig_cseq_ST_st5_fsm_4 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st5_fsm_4 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st6_fsm_5 assign process. --
ap_sig_cseq_ST_st6_fsm_5_assign_proc : process(ap_sig_bdd_164)
begin
if (ap_sig_bdd_164) then
ap_sig_cseq_ST_st6_fsm_5 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st6_fsm_5 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st7_fsm_6 assign process. --
ap_sig_cseq_ST_st7_fsm_6_assign_proc : process(ap_sig_bdd_204)
begin
if (ap_sig_bdd_204) then
ap_sig_cseq_ST_st7_fsm_6 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st7_fsm_6 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st8_fsm_7 assign process. --
ap_sig_cseq_ST_st8_fsm_7_assign_proc : process(ap_sig_bdd_89)
begin
if (ap_sig_bdd_89) then
ap_sig_cseq_ST_st8_fsm_7 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st8_fsm_7 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st9_fsm_8 assign process. --
ap_sig_cseq_ST_st9_fsm_8_assign_proc : process(ap_sig_bdd_329)
begin
if (ap_sig_bdd_329) then
ap_sig_cseq_ST_st9_fsm_8 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st9_fsm_8 <= ap_const_logic_0;
end if;
end process;
-- array_r_address0 assign process. --
array_r_address0_assign_proc : process(ap_sig_cseq_ST_st1_fsm_0, ap_sig_cseq_ST_st2_fsm_1, ap_sig_cseq_ST_st4_fsm_3, ap_sig_cseq_ST_st8_fsm_7, ap_sig_cseq_ST_st10_fsm_9, ap_sig_cseq_ST_st12_fsm_11, ap_sig_cseq_ST_st16_fsm_15, ap_sig_cseq_ST_st20_fsm_19, ap_sig_cseq_ST_st24_fsm_23, ap_sig_cseq_ST_st26_fsm_25, ap_sig_cseq_ST_st28_fsm_27, ap_sig_cseq_ST_st32_fsm_31, ap_sig_cseq_ST_st6_fsm_5, ap_sig_cseq_ST_st14_fsm_13, ap_sig_cseq_ST_st18_fsm_17, ap_sig_cseq_ST_st22_fsm_21, ap_sig_cseq_ST_st30_fsm_29, ap_sig_cseq_ST_st7_fsm_6, ap_sig_cseq_ST_st15_fsm_14, ap_sig_cseq_ST_st19_fsm_18, ap_sig_cseq_ST_st23_fsm_22, ap_sig_cseq_ST_st31_fsm_30, ap_sig_cseq_ST_st3_fsm_2, ap_sig_cseq_ST_st11_fsm_10, ap_sig_cseq_ST_st27_fsm_26, ap_sig_cseq_ST_st5_fsm_4, ap_sig_cseq_ST_st13_fsm_12, ap_sig_cseq_ST_st29_fsm_28, ap_sig_cseq_ST_st9_fsm_8, ap_sig_cseq_ST_st17_fsm_16, ap_sig_cseq_ST_st21_fsm_20, ap_sig_cseq_ST_st25_fsm_24)
begin
if ((ap_const_logic_1 = ap_sig_cseq_ST_st32_fsm_31)) then
array_r_address0 <= ap_const_lv64_3E(6 - 1 downto 0);
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st31_fsm_30)) then
array_r_address0 <= ap_const_lv64_3C(6 - 1 downto 0);
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st30_fsm_29)) then
array_r_address0 <= ap_const_lv64_3A(6 - 1 downto 0);
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st29_fsm_28)) then
array_r_address0 <= ap_const_lv64_38(6 - 1 downto 0);
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st28_fsm_27)) then
array_r_address0 <= ap_const_lv64_36(6 - 1 downto 0);
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st27_fsm_26)) then
array_r_address0 <= ap_const_lv64_34(6 - 1 downto 0);
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st26_fsm_25)) then
array_r_address0 <= ap_const_lv64_32(6 - 1 downto 0);
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st25_fsm_24)) then
array_r_address0 <= ap_const_lv64_30(6 - 1 downto 0);
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st24_fsm_23)) then
array_r_address0 <= ap_const_lv64_2E(6 - 1 downto 0);
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st23_fsm_22)) then
array_r_address0 <= ap_const_lv64_2C(6 - 1 downto 0);
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st22_fsm_21)) then
array_r_address0 <= ap_const_lv64_2A(6 - 1 downto 0);
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st21_fsm_20)) then
array_r_address0 <= ap_const_lv64_28(6 - 1 downto 0);
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st20_fsm_19)) then
array_r_address0 <= ap_const_lv64_26(6 - 1 downto 0);
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st19_fsm_18)) then
array_r_address0 <= ap_const_lv64_24(6 - 1 downto 0);
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st18_fsm_17)) then
array_r_address0 <= ap_const_lv64_22(6 - 1 downto 0);
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st17_fsm_16)) then
array_r_address0 <= ap_const_lv64_20(6 - 1 downto 0);
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st16_fsm_15)) then
array_r_address0 <= ap_const_lv64_1E(6 - 1 downto 0);
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st15_fsm_14)) then
array_r_address0 <= ap_const_lv64_1C(6 - 1 downto 0);
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st14_fsm_13)) then
array_r_address0 <= ap_const_lv64_1A(6 - 1 downto 0);
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st13_fsm_12)) then
array_r_address0 <= ap_const_lv64_18(6 - 1 downto 0);
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st12_fsm_11)) then
array_r_address0 <= ap_const_lv64_16(6 - 1 downto 0);
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st11_fsm_10)) then
array_r_address0 <= ap_const_lv64_14(6 - 1 downto 0);
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st10_fsm_9)) then
array_r_address0 <= ap_const_lv64_12(6 - 1 downto 0);
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st9_fsm_8)) then
array_r_address0 <= ap_const_lv64_10(6 - 1 downto 0);
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st8_fsm_7)) then
array_r_address0 <= ap_const_lv64_E(6 - 1 downto 0);
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st7_fsm_6)) then
array_r_address0 <= ap_const_lv64_C(6 - 1 downto 0);
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st6_fsm_5)) then
array_r_address0 <= ap_const_lv64_A(6 - 1 downto 0);
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st5_fsm_4)) then
array_r_address0 <= ap_const_lv64_8(6 - 1 downto 0);
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st4_fsm_3)) then
array_r_address0 <= ap_const_lv64_6(6 - 1 downto 0);
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st3_fsm_2)) then
array_r_address0 <= ap_const_lv64_4(6 - 1 downto 0);
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st2_fsm_1)) then
array_r_address0 <= ap_const_lv64_2(6 - 1 downto 0);
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st1_fsm_0)) then
array_r_address0 <= ap_const_lv64_0(6 - 1 downto 0);
else
array_r_address0 <= "XXXXXX";
end if;
end process;
-- array_r_address1 assign process. --
array_r_address1_assign_proc : process(ap_sig_cseq_ST_st1_fsm_0, ap_sig_cseq_ST_st2_fsm_1, ap_sig_cseq_ST_st4_fsm_3, ap_sig_cseq_ST_st8_fsm_7, ap_sig_cseq_ST_st10_fsm_9, ap_sig_cseq_ST_st12_fsm_11, ap_sig_cseq_ST_st16_fsm_15, ap_sig_cseq_ST_st20_fsm_19, ap_sig_cseq_ST_st24_fsm_23, ap_sig_cseq_ST_st26_fsm_25, ap_sig_cseq_ST_st28_fsm_27, ap_sig_cseq_ST_st32_fsm_31, ap_sig_cseq_ST_st6_fsm_5, ap_sig_cseq_ST_st14_fsm_13, ap_sig_cseq_ST_st18_fsm_17, ap_sig_cseq_ST_st22_fsm_21, ap_sig_cseq_ST_st30_fsm_29, ap_sig_cseq_ST_st7_fsm_6, ap_sig_cseq_ST_st15_fsm_14, ap_sig_cseq_ST_st19_fsm_18, ap_sig_cseq_ST_st23_fsm_22, ap_sig_cseq_ST_st31_fsm_30, ap_sig_cseq_ST_st3_fsm_2, ap_sig_cseq_ST_st11_fsm_10, ap_sig_cseq_ST_st27_fsm_26, ap_sig_cseq_ST_st5_fsm_4, ap_sig_cseq_ST_st13_fsm_12, ap_sig_cseq_ST_st29_fsm_28, ap_sig_cseq_ST_st9_fsm_8, ap_sig_cseq_ST_st17_fsm_16, ap_sig_cseq_ST_st21_fsm_20, ap_sig_cseq_ST_st25_fsm_24)
begin
if ((ap_const_logic_1 = ap_sig_cseq_ST_st32_fsm_31)) then
array_r_address1 <= ap_const_lv64_3F(6 - 1 downto 0);
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st31_fsm_30)) then
array_r_address1 <= ap_const_lv64_3D(6 - 1 downto 0);
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st30_fsm_29)) then
array_r_address1 <= ap_const_lv64_3B(6 - 1 downto 0);
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st29_fsm_28)) then
array_r_address1 <= ap_const_lv64_39(6 - 1 downto 0);
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st28_fsm_27)) then
array_r_address1 <= ap_const_lv64_37(6 - 1 downto 0);
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st27_fsm_26)) then
array_r_address1 <= ap_const_lv64_35(6 - 1 downto 0);
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st26_fsm_25)) then
array_r_address1 <= ap_const_lv64_33(6 - 1 downto 0);
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st25_fsm_24)) then
array_r_address1 <= ap_const_lv64_31(6 - 1 downto 0);
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st24_fsm_23)) then
array_r_address1 <= ap_const_lv64_2F(6 - 1 downto 0);
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st23_fsm_22)) then
array_r_address1 <= ap_const_lv64_2D(6 - 1 downto 0);
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st22_fsm_21)) then
array_r_address1 <= ap_const_lv64_2B(6 - 1 downto 0);
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st21_fsm_20)) then
array_r_address1 <= ap_const_lv64_29(6 - 1 downto 0);
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st20_fsm_19)) then
array_r_address1 <= ap_const_lv64_27(6 - 1 downto 0);
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st19_fsm_18)) then
array_r_address1 <= ap_const_lv64_25(6 - 1 downto 0);
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st18_fsm_17)) then
array_r_address1 <= ap_const_lv64_23(6 - 1 downto 0);
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st17_fsm_16)) then
array_r_address1 <= ap_const_lv64_21(6 - 1 downto 0);
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st16_fsm_15)) then
array_r_address1 <= ap_const_lv64_1F(6 - 1 downto 0);
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st15_fsm_14)) then
array_r_address1 <= ap_const_lv64_1D(6 - 1 downto 0);
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st14_fsm_13)) then
array_r_address1 <= ap_const_lv64_1B(6 - 1 downto 0);
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st13_fsm_12)) then
array_r_address1 <= ap_const_lv64_19(6 - 1 downto 0);
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st12_fsm_11)) then
array_r_address1 <= ap_const_lv64_17(6 - 1 downto 0);
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st11_fsm_10)) then
array_r_address1 <= ap_const_lv64_15(6 - 1 downto 0);
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st10_fsm_9)) then
array_r_address1 <= ap_const_lv64_13(6 - 1 downto 0);
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st9_fsm_8)) then
array_r_address1 <= ap_const_lv64_11(6 - 1 downto 0);
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st8_fsm_7)) then
array_r_address1 <= ap_const_lv64_F(6 - 1 downto 0);
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st7_fsm_6)) then
array_r_address1 <= ap_const_lv64_D(6 - 1 downto 0);
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st6_fsm_5)) then
array_r_address1 <= ap_const_lv64_B(6 - 1 downto 0);
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st5_fsm_4)) then
array_r_address1 <= ap_const_lv64_9(6 - 1 downto 0);
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st4_fsm_3)) then
array_r_address1 <= ap_const_lv64_7(6 - 1 downto 0);
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st3_fsm_2)) then
array_r_address1 <= ap_const_lv64_5(6 - 1 downto 0);
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st2_fsm_1)) then
array_r_address1 <= ap_const_lv64_3(6 - 1 downto 0);
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st1_fsm_0)) then
array_r_address1 <= ap_const_lv64_1(6 - 1 downto 0);
else
array_r_address1 <= "XXXXXX";
end if;
end process;
-- array_r_ce0 assign process. --
array_r_ce0_assign_proc : process(ap_start, ap_sig_cseq_ST_st1_fsm_0, ap_sig_cseq_ST_st2_fsm_1, ap_sig_cseq_ST_st4_fsm_3, ap_sig_cseq_ST_st8_fsm_7, ap_sig_cseq_ST_st10_fsm_9, ap_sig_cseq_ST_st12_fsm_11, ap_sig_cseq_ST_st16_fsm_15, ap_sig_cseq_ST_st20_fsm_19, ap_sig_cseq_ST_st24_fsm_23, ap_sig_cseq_ST_st26_fsm_25, ap_sig_cseq_ST_st28_fsm_27, ap_sig_cseq_ST_st32_fsm_31, ap_sig_cseq_ST_st6_fsm_5, ap_sig_cseq_ST_st14_fsm_13, ap_sig_cseq_ST_st18_fsm_17, ap_sig_cseq_ST_st22_fsm_21, ap_sig_cseq_ST_st30_fsm_29, ap_sig_cseq_ST_st7_fsm_6, ap_sig_cseq_ST_st15_fsm_14, ap_sig_cseq_ST_st19_fsm_18, ap_sig_cseq_ST_st23_fsm_22, ap_sig_cseq_ST_st31_fsm_30, ap_sig_cseq_ST_st3_fsm_2, ap_sig_cseq_ST_st11_fsm_10, ap_sig_cseq_ST_st27_fsm_26, ap_sig_cseq_ST_st5_fsm_4, ap_sig_cseq_ST_st13_fsm_12, ap_sig_cseq_ST_st29_fsm_28, ap_sig_cseq_ST_st9_fsm_8, ap_sig_cseq_ST_st17_fsm_16, ap_sig_cseq_ST_st21_fsm_20, ap_sig_cseq_ST_st25_fsm_24)
begin
if (((ap_const_logic_1 = ap_sig_cseq_ST_st2_fsm_1) or (ap_const_logic_1 = ap_sig_cseq_ST_st4_fsm_3) or (ap_const_logic_1 = ap_sig_cseq_ST_st8_fsm_7) or (ap_const_logic_1 = ap_sig_cseq_ST_st10_fsm_9) or (ap_const_logic_1 = ap_sig_cseq_ST_st12_fsm_11) or (ap_const_logic_1 = ap_sig_cseq_ST_st16_fsm_15) or (ap_const_logic_1 = ap_sig_cseq_ST_st20_fsm_19) or (ap_const_logic_1 = ap_sig_cseq_ST_st24_fsm_23) or (ap_const_logic_1 = ap_sig_cseq_ST_st26_fsm_25) or (ap_const_logic_1 = ap_sig_cseq_ST_st28_fsm_27) or (ap_const_logic_1 = ap_sig_cseq_ST_st32_fsm_31) or (ap_const_logic_1 = ap_sig_cseq_ST_st6_fsm_5) or (ap_const_logic_1 = ap_sig_cseq_ST_st14_fsm_13) or (ap_const_logic_1 = ap_sig_cseq_ST_st18_fsm_17) or (ap_const_logic_1 = ap_sig_cseq_ST_st22_fsm_21) or (ap_const_logic_1 = ap_sig_cseq_ST_st30_fsm_29) or (ap_const_logic_1 = ap_sig_cseq_ST_st7_fsm_6) or (ap_const_logic_1 = ap_sig_cseq_ST_st15_fsm_14) or (ap_const_logic_1 = ap_sig_cseq_ST_st19_fsm_18) or (ap_const_logic_1 = ap_sig_cseq_ST_st23_fsm_22) or (ap_const_logic_1 = ap_sig_cseq_ST_st31_fsm_30) or (ap_const_logic_1 = ap_sig_cseq_ST_st3_fsm_2) or (ap_const_logic_1 = ap_sig_cseq_ST_st11_fsm_10) or (ap_const_logic_1 = ap_sig_cseq_ST_st27_fsm_26) or (ap_const_logic_1 = ap_sig_cseq_ST_st5_fsm_4) or (ap_const_logic_1 = ap_sig_cseq_ST_st13_fsm_12) or (ap_const_logic_1 = ap_sig_cseq_ST_st29_fsm_28) or ((ap_const_logic_1 = ap_sig_cseq_ST_st1_fsm_0) and not((ap_start = ap_const_logic_0))) or (ap_const_logic_1 = ap_sig_cseq_ST_st9_fsm_8) or (ap_const_logic_1 = ap_sig_cseq_ST_st17_fsm_16) or (ap_const_logic_1 = ap_sig_cseq_ST_st21_fsm_20) or (ap_const_logic_1 = ap_sig_cseq_ST_st25_fsm_24))) then
array_r_ce0 <= ap_const_logic_1;
else
array_r_ce0 <= ap_const_logic_0;
end if;
end process;
-- array_r_ce1 assign process. --
array_r_ce1_assign_proc : process(ap_start, ap_sig_cseq_ST_st1_fsm_0, ap_sig_cseq_ST_st2_fsm_1, ap_sig_cseq_ST_st4_fsm_3, ap_sig_cseq_ST_st8_fsm_7, ap_sig_cseq_ST_st10_fsm_9, ap_sig_cseq_ST_st12_fsm_11, ap_sig_cseq_ST_st16_fsm_15, ap_sig_cseq_ST_st20_fsm_19, ap_sig_cseq_ST_st24_fsm_23, ap_sig_cseq_ST_st26_fsm_25, ap_sig_cseq_ST_st28_fsm_27, ap_sig_cseq_ST_st32_fsm_31, ap_sig_cseq_ST_st6_fsm_5, ap_sig_cseq_ST_st14_fsm_13, ap_sig_cseq_ST_st18_fsm_17, ap_sig_cseq_ST_st22_fsm_21, ap_sig_cseq_ST_st30_fsm_29, ap_sig_cseq_ST_st7_fsm_6, ap_sig_cseq_ST_st15_fsm_14, ap_sig_cseq_ST_st19_fsm_18, ap_sig_cseq_ST_st23_fsm_22, ap_sig_cseq_ST_st31_fsm_30, ap_sig_cseq_ST_st3_fsm_2, ap_sig_cseq_ST_st11_fsm_10, ap_sig_cseq_ST_st27_fsm_26, ap_sig_cseq_ST_st5_fsm_4, ap_sig_cseq_ST_st13_fsm_12, ap_sig_cseq_ST_st29_fsm_28, ap_sig_cseq_ST_st9_fsm_8, ap_sig_cseq_ST_st17_fsm_16, ap_sig_cseq_ST_st21_fsm_20, ap_sig_cseq_ST_st25_fsm_24)
begin
if (((ap_const_logic_1 = ap_sig_cseq_ST_st2_fsm_1) or (ap_const_logic_1 = ap_sig_cseq_ST_st4_fsm_3) or (ap_const_logic_1 = ap_sig_cseq_ST_st8_fsm_7) or (ap_const_logic_1 = ap_sig_cseq_ST_st10_fsm_9) or (ap_const_logic_1 = ap_sig_cseq_ST_st12_fsm_11) or (ap_const_logic_1 = ap_sig_cseq_ST_st16_fsm_15) or (ap_const_logic_1 = ap_sig_cseq_ST_st20_fsm_19) or (ap_const_logic_1 = ap_sig_cseq_ST_st24_fsm_23) or (ap_const_logic_1 = ap_sig_cseq_ST_st26_fsm_25) or (ap_const_logic_1 = ap_sig_cseq_ST_st28_fsm_27) or (ap_const_logic_1 = ap_sig_cseq_ST_st32_fsm_31) or (ap_const_logic_1 = ap_sig_cseq_ST_st6_fsm_5) or (ap_const_logic_1 = ap_sig_cseq_ST_st14_fsm_13) or (ap_const_logic_1 = ap_sig_cseq_ST_st18_fsm_17) or (ap_const_logic_1 = ap_sig_cseq_ST_st22_fsm_21) or (ap_const_logic_1 = ap_sig_cseq_ST_st30_fsm_29) or (ap_const_logic_1 = ap_sig_cseq_ST_st7_fsm_6) or (ap_const_logic_1 = ap_sig_cseq_ST_st15_fsm_14) or (ap_const_logic_1 = ap_sig_cseq_ST_st19_fsm_18) or (ap_const_logic_1 = ap_sig_cseq_ST_st23_fsm_22) or (ap_const_logic_1 = ap_sig_cseq_ST_st31_fsm_30) or (ap_const_logic_1 = ap_sig_cseq_ST_st3_fsm_2) or (ap_const_logic_1 = ap_sig_cseq_ST_st11_fsm_10) or (ap_const_logic_1 = ap_sig_cseq_ST_st27_fsm_26) or (ap_const_logic_1 = ap_sig_cseq_ST_st5_fsm_4) or (ap_const_logic_1 = ap_sig_cseq_ST_st13_fsm_12) or (ap_const_logic_1 = ap_sig_cseq_ST_st29_fsm_28) or ((ap_const_logic_1 = ap_sig_cseq_ST_st1_fsm_0) and not((ap_start = ap_const_logic_0))) or (ap_const_logic_1 = ap_sig_cseq_ST_st9_fsm_8) or (ap_const_logic_1 = ap_sig_cseq_ST_st17_fsm_16) or (ap_const_logic_1 = ap_sig_cseq_ST_st21_fsm_20) or (ap_const_logic_1 = ap_sig_cseq_ST_st25_fsm_24))) then
array_r_ce1 <= ap_const_logic_1;
else
array_r_ce1 <= ap_const_logic_0;
end if;
end process;
grp_fu_723_p2 <= std_logic_vector(unsigned(array_r_q0) + unsigned(array_r_q1));
grp_fu_745_p2 <= std_logic_vector(unsigned(reg_729) + unsigned(reg_733));
grp_fu_751_p2 <= std_logic_vector(unsigned(grp_fu_723_p2) + unsigned(grp_fu_745_p2));
grp_fu_757_p2 <= std_logic_vector(unsigned(reg_741) + unsigned(reg_737));
grp_fu_763_p2 <= std_logic_vector(unsigned(grp_fu_751_p2) + unsigned(grp_fu_757_p2));
grp_fu_777_p2 <= std_logic_vector(unsigned(reg_773) + unsigned(reg_769));
grp_fu_783_p2 <= std_logic_vector(unsigned(grp_fu_763_p2) + unsigned(grp_fu_777_p2));
tmp31_fu_797_p2 <= std_logic_vector(unsigned(tmp47_reg_1148) + unsigned(tmp32_fu_793_p2));
tmp32_fu_793_p2 <= std_logic_vector(unsigned(tmp40_reg_1073) + unsigned(tmp33_reg_1028));
tmp_fu_789_p2 <= std_logic_vector(unsigned(tmp16_reg_983) + unsigned(tmp1_reg_898));
end behav;
| gpl-3.0 | 80478f9360a4413cb114bc9cbdca262d | 0.627073 | 2.911251 | false | false | false | false |
jairov4/accel-oil | solution_spartan6/syn/vhdl/nfa_accept_sample.vhd | 1 | 61,740 | -- ==============================================================
-- RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2013.4
-- Copyright (C) 2013 Xilinx Inc. All rights reserved.
--
-- ===========================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity nfa_accept_sample is
port (
ap_clk : IN STD_LOGIC;
ap_rst : IN STD_LOGIC;
ap_start : IN STD_LOGIC;
ap_done : OUT STD_LOGIC;
ap_idle : OUT STD_LOGIC;
ap_ready : OUT STD_LOGIC;
nfa_initials_buckets_req_din : OUT STD_LOGIC;
nfa_initials_buckets_req_full_n : IN STD_LOGIC;
nfa_initials_buckets_req_write : OUT STD_LOGIC;
nfa_initials_buckets_rsp_empty_n : IN STD_LOGIC;
nfa_initials_buckets_rsp_read : OUT STD_LOGIC;
nfa_initials_buckets_address : OUT STD_LOGIC_VECTOR (31 downto 0);
nfa_initials_buckets_datain : IN STD_LOGIC_VECTOR (31 downto 0);
nfa_initials_buckets_dataout : OUT STD_LOGIC_VECTOR (31 downto 0);
nfa_initials_buckets_size : OUT STD_LOGIC_VECTOR (31 downto 0);
nfa_finals_buckets_req_din : OUT STD_LOGIC;
nfa_finals_buckets_req_full_n : IN STD_LOGIC;
nfa_finals_buckets_req_write : OUT STD_LOGIC;
nfa_finals_buckets_rsp_empty_n : IN STD_LOGIC;
nfa_finals_buckets_rsp_read : OUT STD_LOGIC;
nfa_finals_buckets_address : OUT STD_LOGIC_VECTOR (31 downto 0);
nfa_finals_buckets_datain : IN STD_LOGIC_VECTOR (31 downto 0);
nfa_finals_buckets_dataout : OUT STD_LOGIC_VECTOR (31 downto 0);
nfa_finals_buckets_size : OUT STD_LOGIC_VECTOR (31 downto 0);
nfa_forward_buckets_req_din : OUT STD_LOGIC;
nfa_forward_buckets_req_full_n : IN STD_LOGIC;
nfa_forward_buckets_req_write : OUT STD_LOGIC;
nfa_forward_buckets_rsp_empty_n : IN STD_LOGIC;
nfa_forward_buckets_rsp_read : OUT STD_LOGIC;
nfa_forward_buckets_address : OUT STD_LOGIC_VECTOR (31 downto 0);
nfa_forward_buckets_datain : IN STD_LOGIC_VECTOR (31 downto 0);
nfa_forward_buckets_dataout : OUT STD_LOGIC_VECTOR (31 downto 0);
nfa_forward_buckets_size : OUT STD_LOGIC_VECTOR (31 downto 0);
nfa_symbols : IN STD_LOGIC_VECTOR (7 downto 0);
sample_req_din : OUT STD_LOGIC;
sample_req_full_n : IN STD_LOGIC;
sample_req_write : OUT STD_LOGIC;
sample_rsp_empty_n : IN STD_LOGIC;
sample_rsp_read : OUT STD_LOGIC;
sample_address : OUT STD_LOGIC_VECTOR (31 downto 0);
sample_datain : IN STD_LOGIC_VECTOR (7 downto 0);
sample_dataout : OUT STD_LOGIC_VECTOR (7 downto 0);
sample_size : OUT STD_LOGIC_VECTOR (31 downto 0);
empty : IN STD_LOGIC_VECTOR (31 downto 0);
length_r : IN STD_LOGIC_VECTOR (15 downto 0);
ap_return : OUT STD_LOGIC_VECTOR (0 downto 0) );
end;
architecture behav of nfa_accept_sample is
constant ap_const_logic_1 : STD_LOGIC := '1';
constant ap_const_logic_0 : STD_LOGIC := '0';
constant ap_ST_st1_fsm_0 : STD_LOGIC_VECTOR (5 downto 0) := "000000";
constant ap_ST_st2_fsm_1 : STD_LOGIC_VECTOR (5 downto 0) := "000001";
constant ap_ST_st3_fsm_2 : STD_LOGIC_VECTOR (5 downto 0) := "000010";
constant ap_ST_st4_fsm_3 : STD_LOGIC_VECTOR (5 downto 0) := "000011";
constant ap_ST_st5_fsm_4 : STD_LOGIC_VECTOR (5 downto 0) := "000100";
constant ap_ST_st6_fsm_5 : STD_LOGIC_VECTOR (5 downto 0) := "000101";
constant ap_ST_st7_fsm_6 : STD_LOGIC_VECTOR (5 downto 0) := "000110";
constant ap_ST_st8_fsm_7 : STD_LOGIC_VECTOR (5 downto 0) := "000111";
constant ap_ST_st9_fsm_8 : STD_LOGIC_VECTOR (5 downto 0) := "001000";
constant ap_ST_st10_fsm_9 : STD_LOGIC_VECTOR (5 downto 0) := "001001";
constant ap_ST_st11_fsm_10 : STD_LOGIC_VECTOR (5 downto 0) := "001010";
constant ap_ST_st12_fsm_11 : STD_LOGIC_VECTOR (5 downto 0) := "001011";
constant ap_ST_st13_fsm_12 : STD_LOGIC_VECTOR (5 downto 0) := "001100";
constant ap_ST_st14_fsm_13 : STD_LOGIC_VECTOR (5 downto 0) := "001101";
constant ap_ST_st15_fsm_14 : STD_LOGIC_VECTOR (5 downto 0) := "001110";
constant ap_ST_st16_fsm_15 : STD_LOGIC_VECTOR (5 downto 0) := "001111";
constant ap_ST_st17_fsm_16 : STD_LOGIC_VECTOR (5 downto 0) := "010000";
constant ap_ST_st18_fsm_17 : STD_LOGIC_VECTOR (5 downto 0) := "010001";
constant ap_ST_st19_fsm_18 : STD_LOGIC_VECTOR (5 downto 0) := "010010";
constant ap_ST_st20_fsm_19 : STD_LOGIC_VECTOR (5 downto 0) := "010011";
constant ap_ST_st21_fsm_20 : STD_LOGIC_VECTOR (5 downto 0) := "010100";
constant ap_ST_st22_fsm_21 : STD_LOGIC_VECTOR (5 downto 0) := "010101";
constant ap_ST_st23_fsm_22 : STD_LOGIC_VECTOR (5 downto 0) := "010110";
constant ap_ST_st24_fsm_23 : STD_LOGIC_VECTOR (5 downto 0) := "010111";
constant ap_ST_st25_fsm_24 : STD_LOGIC_VECTOR (5 downto 0) := "011000";
constant ap_ST_st26_fsm_25 : STD_LOGIC_VECTOR (5 downto 0) := "011001";
constant ap_ST_st27_fsm_26 : STD_LOGIC_VECTOR (5 downto 0) := "011010";
constant ap_ST_st28_fsm_27 : STD_LOGIC_VECTOR (5 downto 0) := "011011";
constant ap_ST_st29_fsm_28 : STD_LOGIC_VECTOR (5 downto 0) := "011100";
constant ap_ST_st30_fsm_29 : STD_LOGIC_VECTOR (5 downto 0) := "011101";
constant ap_ST_st31_fsm_30 : STD_LOGIC_VECTOR (5 downto 0) := "011110";
constant ap_ST_st32_fsm_31 : STD_LOGIC_VECTOR (5 downto 0) := "011111";
constant ap_ST_st33_fsm_32 : STD_LOGIC_VECTOR (5 downto 0) := "100000";
constant ap_ST_st34_fsm_33 : STD_LOGIC_VECTOR (5 downto 0) := "100001";
constant ap_ST_st35_fsm_34 : STD_LOGIC_VECTOR (5 downto 0) := "100010";
constant ap_ST_st36_fsm_35 : STD_LOGIC_VECTOR (5 downto 0) := "100011";
constant ap_ST_st37_fsm_36 : STD_LOGIC_VECTOR (5 downto 0) := "100100";
constant ap_ST_st38_fsm_37 : STD_LOGIC_VECTOR (5 downto 0) := "100101";
constant ap_ST_st39_fsm_38 : STD_LOGIC_VECTOR (5 downto 0) := "100110";
constant ap_ST_st40_fsm_39 : STD_LOGIC_VECTOR (5 downto 0) := "100111";
constant ap_ST_st41_fsm_40 : STD_LOGIC_VECTOR (5 downto 0) := "101000";
constant ap_ST_st42_fsm_41 : STD_LOGIC_VECTOR (5 downto 0) := "101001";
constant ap_ST_st43_fsm_42 : STD_LOGIC_VECTOR (5 downto 0) := "101010";
constant ap_ST_st44_fsm_43 : STD_LOGIC_VECTOR (5 downto 0) := "101011";
constant ap_ST_st45_fsm_44 : STD_LOGIC_VECTOR (5 downto 0) := "101100";
constant ap_const_lv1_0 : STD_LOGIC_VECTOR (0 downto 0) := "0";
constant ap_const_lv16_0 : STD_LOGIC_VECTOR (15 downto 0) := "0000000000000000";
constant ap_const_lv32_0 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000000";
constant ap_const_lv1_1 : STD_LOGIC_VECTOR (0 downto 0) := "1";
constant ap_const_lv2_2 : STD_LOGIC_VECTOR (1 downto 0) := "10";
constant ap_const_lv32_1 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000001";
constant ap_const_lv16_1 : STD_LOGIC_VECTOR (15 downto 0) := "0000000000000001";
constant ap_const_lv5_0 : STD_LOGIC_VECTOR (4 downto 0) := "00000";
constant ap_const_lv8_0 : STD_LOGIC_VECTOR (7 downto 0) := "00000000";
signal ap_CS_fsm : STD_LOGIC_VECTOR (5 downto 0) := "000000";
signal reg_374 : STD_LOGIC_VECTOR (31 downto 0);
signal current_buckets_0_reg_577 : STD_LOGIC_VECTOR (31 downto 0);
signal current_buckets_1_reg_582 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_s_fu_397_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_s_reg_597 : STD_LOGIC_VECTOR (0 downto 0);
signal grp_fu_402_p2 : STD_LOGIC_VECTOR (15 downto 0);
signal i_1_reg_601 : STD_LOGIC_VECTOR (15 downto 0);
signal sample_addr_1_reg_606 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_2_i_fu_420_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_2_i_reg_612 : STD_LOGIC_VECTOR (0 downto 0);
signal grp_fu_414_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal p_rec_reg_616 : STD_LOGIC_VECTOR (31 downto 0);
signal sym_reg_621 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_2_1_i_fu_426_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_2_1_i_reg_626 : STD_LOGIC_VECTOR (0 downto 0);
signal grp_p_bsf32_hw_fu_368_ap_return : STD_LOGIC_VECTOR (4 downto 0);
signal r_bit_reg_630 : STD_LOGIC_VECTOR (4 downto 0);
signal agg_result_bucket_index_0_lcssa4_i_cast_cast_fu_432_p1 : STD_LOGIC_VECTOR (1 downto 0);
signal j_bucket_index1_ph_cast_fu_436_p1 : STD_LOGIC_VECTOR (7 downto 0);
signal j_bit1_ph_cast_fu_440_p1 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_18_i_cast_fu_444_p1 : STD_LOGIC_VECTOR (13 downto 0);
signal tmp_18_i_cast_reg_650 : STD_LOGIC_VECTOR (13 downto 0);
signal j_end_phi_fu_312_p4 : STD_LOGIC_VECTOR (0 downto 0);
signal grp_fu_463_p2 : STD_LOGIC_VECTOR (5 downto 0);
signal state_reg_665 : STD_LOGIC_VECTOR (5 downto 0);
signal grp_fu_476_p2 : STD_LOGIC_VECTOR (13 downto 0);
signal tmp_17_i_reg_680 : STD_LOGIC_VECTOR (13 downto 0);
signal grp_fu_482_p2 : STD_LOGIC_VECTOR (13 downto 0);
signal offset_i_reg_685 : STD_LOGIC_VECTOR (13 downto 0);
signal j_bit_reg_701 : STD_LOGIC_VECTOR (7 downto 0);
signal j_bucket_index_reg_706 : STD_LOGIC_VECTOR (7 downto 0);
signal j_bucket_reg_711 : STD_LOGIC_VECTOR (31 downto 0);
signal p_s_reg_716 : STD_LOGIC_VECTOR (0 downto 0);
signal next_buckets_0_1_fu_538_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal next_buckets_0_1_reg_721 : STD_LOGIC_VECTOR (31 downto 0);
signal next_buckets_1_1_fu_544_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_buckets_0_reg_731 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_buckets_1_reg_736 : STD_LOGIC_VECTOR (31 downto 0);
signal current_buckets_0_1_fu_558_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal current_buckets_0_1_reg_741 : STD_LOGIC_VECTOR (31 downto 0);
signal current_buckets_1_1_fu_563_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal current_buckets_1_1_reg_746 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_1_fu_568_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_1_reg_751 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_2_fu_572_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_2_reg_756 : STD_LOGIC_VECTOR (0 downto 0);
signal grp_bitset_next_fu_344_p_read : STD_LOGIC_VECTOR (31 downto 0);
signal grp_bitset_next_fu_344_r_bit : STD_LOGIC_VECTOR (7 downto 0);
signal grp_bitset_next_fu_344_r_bucket_index : STD_LOGIC_VECTOR (7 downto 0);
signal grp_bitset_next_fu_344_r_bucket : STD_LOGIC_VECTOR (31 downto 0);
signal grp_bitset_next_fu_344_ap_return_0 : STD_LOGIC_VECTOR (7 downto 0);
signal grp_bitset_next_fu_344_ap_return_1 : STD_LOGIC_VECTOR (7 downto 0);
signal grp_bitset_next_fu_344_ap_return_2 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_bitset_next_fu_344_ap_return_3 : STD_LOGIC_VECTOR (0 downto 0);
signal grp_bitset_next_fu_344_ap_ce : STD_LOGIC;
signal grp_nfa_get_initials_fu_356_ap_start : STD_LOGIC;
signal grp_nfa_get_initials_fu_356_ap_done : STD_LOGIC;
signal grp_nfa_get_initials_fu_356_ap_idle : STD_LOGIC;
signal grp_nfa_get_initials_fu_356_ap_ready : STD_LOGIC;
signal grp_nfa_get_initials_fu_356_nfa_initials_buckets_req_din : STD_LOGIC;
signal grp_nfa_get_initials_fu_356_nfa_initials_buckets_req_full_n : STD_LOGIC;
signal grp_nfa_get_initials_fu_356_nfa_initials_buckets_req_write : STD_LOGIC;
signal grp_nfa_get_initials_fu_356_nfa_initials_buckets_rsp_empty_n : STD_LOGIC;
signal grp_nfa_get_initials_fu_356_nfa_initials_buckets_rsp_read : STD_LOGIC;
signal grp_nfa_get_initials_fu_356_nfa_initials_buckets_address : STD_LOGIC_VECTOR (31 downto 0);
signal grp_nfa_get_initials_fu_356_nfa_initials_buckets_datain : STD_LOGIC_VECTOR (31 downto 0);
signal grp_nfa_get_initials_fu_356_nfa_initials_buckets_dataout : STD_LOGIC_VECTOR (31 downto 0);
signal grp_nfa_get_initials_fu_356_nfa_initials_buckets_size : STD_LOGIC_VECTOR (31 downto 0);
signal grp_nfa_get_initials_fu_356_ap_ce : STD_LOGIC;
signal grp_nfa_get_initials_fu_356_ap_return_0 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_nfa_get_initials_fu_356_ap_return_1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_nfa_get_finals_fu_362_ap_start : STD_LOGIC;
signal grp_nfa_get_finals_fu_362_ap_done : STD_LOGIC;
signal grp_nfa_get_finals_fu_362_ap_idle : STD_LOGIC;
signal grp_nfa_get_finals_fu_362_ap_ready : STD_LOGIC;
signal grp_nfa_get_finals_fu_362_nfa_finals_buckets_req_din : STD_LOGIC;
signal grp_nfa_get_finals_fu_362_nfa_finals_buckets_req_full_n : STD_LOGIC;
signal grp_nfa_get_finals_fu_362_nfa_finals_buckets_req_write : STD_LOGIC;
signal grp_nfa_get_finals_fu_362_nfa_finals_buckets_rsp_empty_n : STD_LOGIC;
signal grp_nfa_get_finals_fu_362_nfa_finals_buckets_rsp_read : STD_LOGIC;
signal grp_nfa_get_finals_fu_362_nfa_finals_buckets_address : STD_LOGIC_VECTOR (31 downto 0);
signal grp_nfa_get_finals_fu_362_nfa_finals_buckets_datain : STD_LOGIC_VECTOR (31 downto 0);
signal grp_nfa_get_finals_fu_362_nfa_finals_buckets_dataout : STD_LOGIC_VECTOR (31 downto 0);
signal grp_nfa_get_finals_fu_362_nfa_finals_buckets_size : STD_LOGIC_VECTOR (31 downto 0);
signal grp_nfa_get_finals_fu_362_ap_ce : STD_LOGIC;
signal grp_nfa_get_finals_fu_362_ap_return_0 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_nfa_get_finals_fu_362_ap_return_1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_p_bsf32_hw_fu_368_bus_r : STD_LOGIC_VECTOR (31 downto 0);
signal grp_p_bsf32_hw_fu_368_ap_ce : STD_LOGIC;
signal i_reg_134 : STD_LOGIC_VECTOR (15 downto 0);
signal any_phi_fu_324_p4 : STD_LOGIC_VECTOR (0 downto 0);
signal p_01_rec_reg_146 : STD_LOGIC_VECTOR (31 downto 0);
signal next_buckets_1_reg_158 : STD_LOGIC_VECTOR (31 downto 0);
signal next_buckets_0_reg_168 : STD_LOGIC_VECTOR (31 downto 0);
signal bus_assign_reg_178 : STD_LOGIC_VECTOR (31 downto 0);
signal agg_result_bucket_index_0_lcssa4_i_reg_190 : STD_LOGIC_VECTOR (0 downto 0);
signal j_bucket1_ph_reg_203 : STD_LOGIC_VECTOR (31 downto 0);
signal j_bucket_index1_ph_reg_216 : STD_LOGIC_VECTOR (1 downto 0);
signal j_bit1_ph_reg_227 : STD_LOGIC_VECTOR (4 downto 0);
signal j_end_ph_reg_238 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_buckets_1_3_reg_252 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_buckets_0_3_reg_265 : STD_LOGIC_VECTOR (31 downto 0);
signal j_bucket1_reg_278 : STD_LOGIC_VECTOR (31 downto 0);
signal j_bucket_index1_reg_289 : STD_LOGIC_VECTOR (7 downto 0);
signal j_bit1_reg_299 : STD_LOGIC_VECTOR (7 downto 0);
signal j_end_reg_309 : STD_LOGIC_VECTOR (0 downto 0);
signal any_reg_319 : STD_LOGIC_VECTOR (0 downto 0);
signal p_0_reg_332 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_NS_fsm : STD_LOGIC_VECTOR (5 downto 0);
signal grp_nfa_get_finals_fu_362_ap_start_ap_start_reg : STD_LOGIC := '0';
signal grp_fu_392_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_5_i_cast_fu_493_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_6_i_cast_fu_511_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_392_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_392_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_402_p0 : STD_LOGIC_VECTOR (15 downto 0);
signal grp_fu_402_p1 : STD_LOGIC_VECTOR (15 downto 0);
signal grp_fu_414_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_414_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_5_fu_447_p1 : STD_LOGIC_VECTOR (0 downto 0);
signal grp_fu_463_p0 : STD_LOGIC_VECTOR (5 downto 0);
signal grp_fu_463_p1 : STD_LOGIC_VECTOR (5 downto 0);
signal grp_fu_476_p0 : STD_LOGIC_VECTOR (7 downto 0);
signal grp_fu_476_p1 : STD_LOGIC_VECTOR (5 downto 0);
signal grp_fu_482_p0 : STD_LOGIC_VECTOR (13 downto 0);
signal grp_fu_482_p1 : STD_LOGIC_VECTOR (13 downto 0);
signal tmp_5_i_fu_486_p3 : STD_LOGIC_VECTOR (14 downto 0);
signal tmp_6_i_fu_504_p3 : STD_LOGIC_VECTOR (14 downto 0);
signal grp_fu_392_ce : STD_LOGIC;
signal grp_fu_402_ce : STD_LOGIC;
signal grp_fu_414_ce : STD_LOGIC;
signal grp_fu_463_ce : STD_LOGIC;
signal grp_fu_476_ce : STD_LOGIC;
signal grp_fu_482_ce : STD_LOGIC;
signal ap_return_preg : STD_LOGIC_VECTOR (0 downto 0) := "0";
signal grp_fu_476_p00 : STD_LOGIC_VECTOR (13 downto 0);
signal grp_fu_476_p10 : STD_LOGIC_VECTOR (13 downto 0);
component bitset_next IS
port (
ap_clk : IN STD_LOGIC;
ap_rst : IN STD_LOGIC;
p_read : IN STD_LOGIC_VECTOR (31 downto 0);
r_bit : IN STD_LOGIC_VECTOR (7 downto 0);
r_bucket_index : IN STD_LOGIC_VECTOR (7 downto 0);
r_bucket : IN STD_LOGIC_VECTOR (31 downto 0);
ap_return_0 : OUT STD_LOGIC_VECTOR (7 downto 0);
ap_return_1 : OUT STD_LOGIC_VECTOR (7 downto 0);
ap_return_2 : OUT STD_LOGIC_VECTOR (31 downto 0);
ap_return_3 : OUT STD_LOGIC_VECTOR (0 downto 0);
ap_ce : IN STD_LOGIC );
end component;
component nfa_get_initials IS
port (
ap_clk : IN STD_LOGIC;
ap_rst : IN STD_LOGIC;
ap_start : IN STD_LOGIC;
ap_done : OUT STD_LOGIC;
ap_idle : OUT STD_LOGIC;
ap_ready : OUT STD_LOGIC;
nfa_initials_buckets_req_din : OUT STD_LOGIC;
nfa_initials_buckets_req_full_n : IN STD_LOGIC;
nfa_initials_buckets_req_write : OUT STD_LOGIC;
nfa_initials_buckets_rsp_empty_n : IN STD_LOGIC;
nfa_initials_buckets_rsp_read : OUT STD_LOGIC;
nfa_initials_buckets_address : OUT STD_LOGIC_VECTOR (31 downto 0);
nfa_initials_buckets_datain : IN STD_LOGIC_VECTOR (31 downto 0);
nfa_initials_buckets_dataout : OUT STD_LOGIC_VECTOR (31 downto 0);
nfa_initials_buckets_size : OUT STD_LOGIC_VECTOR (31 downto 0);
ap_ce : IN STD_LOGIC;
ap_return_0 : OUT STD_LOGIC_VECTOR (31 downto 0);
ap_return_1 : OUT STD_LOGIC_VECTOR (31 downto 0) );
end component;
component nfa_get_finals IS
port (
ap_clk : IN STD_LOGIC;
ap_rst : IN STD_LOGIC;
ap_start : IN STD_LOGIC;
ap_done : OUT STD_LOGIC;
ap_idle : OUT STD_LOGIC;
ap_ready : OUT STD_LOGIC;
nfa_finals_buckets_req_din : OUT STD_LOGIC;
nfa_finals_buckets_req_full_n : IN STD_LOGIC;
nfa_finals_buckets_req_write : OUT STD_LOGIC;
nfa_finals_buckets_rsp_empty_n : IN STD_LOGIC;
nfa_finals_buckets_rsp_read : OUT STD_LOGIC;
nfa_finals_buckets_address : OUT STD_LOGIC_VECTOR (31 downto 0);
nfa_finals_buckets_datain : IN STD_LOGIC_VECTOR (31 downto 0);
nfa_finals_buckets_dataout : OUT STD_LOGIC_VECTOR (31 downto 0);
nfa_finals_buckets_size : OUT STD_LOGIC_VECTOR (31 downto 0);
ap_ce : IN STD_LOGIC;
ap_return_0 : OUT STD_LOGIC_VECTOR (31 downto 0);
ap_return_1 : OUT STD_LOGIC_VECTOR (31 downto 0) );
end component;
component p_bsf32_hw IS
port (
ap_clk : IN STD_LOGIC;
ap_rst : IN STD_LOGIC;
bus_r : IN STD_LOGIC_VECTOR (31 downto 0);
ap_return : OUT STD_LOGIC_VECTOR (4 downto 0);
ap_ce : IN STD_LOGIC );
end component;
component nfa_accept_samples_generic_hw_add_32ns_32ns_32_8 IS
generic (
ID : INTEGER;
NUM_STAGE : INTEGER;
din0_WIDTH : INTEGER;
din1_WIDTH : INTEGER;
dout_WIDTH : INTEGER );
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
din0 : IN STD_LOGIC_VECTOR (31 downto 0);
din1 : IN STD_LOGIC_VECTOR (31 downto 0);
ce : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR (31 downto 0) );
end component;
component nfa_accept_samples_generic_hw_add_16ns_16ns_16_4 IS
generic (
ID : INTEGER;
NUM_STAGE : INTEGER;
din0_WIDTH : INTEGER;
din1_WIDTH : INTEGER;
dout_WIDTH : INTEGER );
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
din0 : IN STD_LOGIC_VECTOR (15 downto 0);
din1 : IN STD_LOGIC_VECTOR (15 downto 0);
ce : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR (15 downto 0) );
end component;
component nfa_accept_samples_generic_hw_add_6ns_6ns_6_2 IS
generic (
ID : INTEGER;
NUM_STAGE : INTEGER;
din0_WIDTH : INTEGER;
din1_WIDTH : INTEGER;
dout_WIDTH : INTEGER );
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
din0 : IN STD_LOGIC_VECTOR (5 downto 0);
din1 : IN STD_LOGIC_VECTOR (5 downto 0);
ce : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR (5 downto 0) );
end component;
component nfa_accept_samples_generic_hw_mul_8ns_6ns_14_4 IS
generic (
ID : INTEGER;
NUM_STAGE : INTEGER;
din0_WIDTH : INTEGER;
din1_WIDTH : INTEGER;
dout_WIDTH : INTEGER );
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
din0 : IN STD_LOGIC_VECTOR (7 downto 0);
din1 : IN STD_LOGIC_VECTOR (5 downto 0);
ce : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR (13 downto 0) );
end component;
component nfa_accept_samples_generic_hw_add_14ns_14ns_14_4 IS
generic (
ID : INTEGER;
NUM_STAGE : INTEGER;
din0_WIDTH : INTEGER;
din1_WIDTH : INTEGER;
dout_WIDTH : INTEGER );
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
din0 : IN STD_LOGIC_VECTOR (13 downto 0);
din1 : IN STD_LOGIC_VECTOR (13 downto 0);
ce : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR (13 downto 0) );
end component;
begin
grp_bitset_next_fu_344 : component bitset_next
port map (
ap_clk => ap_clk,
ap_rst => ap_rst,
p_read => grp_bitset_next_fu_344_p_read,
r_bit => grp_bitset_next_fu_344_r_bit,
r_bucket_index => grp_bitset_next_fu_344_r_bucket_index,
r_bucket => grp_bitset_next_fu_344_r_bucket,
ap_return_0 => grp_bitset_next_fu_344_ap_return_0,
ap_return_1 => grp_bitset_next_fu_344_ap_return_1,
ap_return_2 => grp_bitset_next_fu_344_ap_return_2,
ap_return_3 => grp_bitset_next_fu_344_ap_return_3,
ap_ce => grp_bitset_next_fu_344_ap_ce);
grp_nfa_get_initials_fu_356 : component nfa_get_initials
port map (
ap_clk => ap_clk,
ap_rst => ap_rst,
ap_start => grp_nfa_get_initials_fu_356_ap_start,
ap_done => grp_nfa_get_initials_fu_356_ap_done,
ap_idle => grp_nfa_get_initials_fu_356_ap_idle,
ap_ready => grp_nfa_get_initials_fu_356_ap_ready,
nfa_initials_buckets_req_din => grp_nfa_get_initials_fu_356_nfa_initials_buckets_req_din,
nfa_initials_buckets_req_full_n => grp_nfa_get_initials_fu_356_nfa_initials_buckets_req_full_n,
nfa_initials_buckets_req_write => grp_nfa_get_initials_fu_356_nfa_initials_buckets_req_write,
nfa_initials_buckets_rsp_empty_n => grp_nfa_get_initials_fu_356_nfa_initials_buckets_rsp_empty_n,
nfa_initials_buckets_rsp_read => grp_nfa_get_initials_fu_356_nfa_initials_buckets_rsp_read,
nfa_initials_buckets_address => grp_nfa_get_initials_fu_356_nfa_initials_buckets_address,
nfa_initials_buckets_datain => grp_nfa_get_initials_fu_356_nfa_initials_buckets_datain,
nfa_initials_buckets_dataout => grp_nfa_get_initials_fu_356_nfa_initials_buckets_dataout,
nfa_initials_buckets_size => grp_nfa_get_initials_fu_356_nfa_initials_buckets_size,
ap_ce => grp_nfa_get_initials_fu_356_ap_ce,
ap_return_0 => grp_nfa_get_initials_fu_356_ap_return_0,
ap_return_1 => grp_nfa_get_initials_fu_356_ap_return_1);
grp_nfa_get_finals_fu_362 : component nfa_get_finals
port map (
ap_clk => ap_clk,
ap_rst => ap_rst,
ap_start => grp_nfa_get_finals_fu_362_ap_start,
ap_done => grp_nfa_get_finals_fu_362_ap_done,
ap_idle => grp_nfa_get_finals_fu_362_ap_idle,
ap_ready => grp_nfa_get_finals_fu_362_ap_ready,
nfa_finals_buckets_req_din => grp_nfa_get_finals_fu_362_nfa_finals_buckets_req_din,
nfa_finals_buckets_req_full_n => grp_nfa_get_finals_fu_362_nfa_finals_buckets_req_full_n,
nfa_finals_buckets_req_write => grp_nfa_get_finals_fu_362_nfa_finals_buckets_req_write,
nfa_finals_buckets_rsp_empty_n => grp_nfa_get_finals_fu_362_nfa_finals_buckets_rsp_empty_n,
nfa_finals_buckets_rsp_read => grp_nfa_get_finals_fu_362_nfa_finals_buckets_rsp_read,
nfa_finals_buckets_address => grp_nfa_get_finals_fu_362_nfa_finals_buckets_address,
nfa_finals_buckets_datain => grp_nfa_get_finals_fu_362_nfa_finals_buckets_datain,
nfa_finals_buckets_dataout => grp_nfa_get_finals_fu_362_nfa_finals_buckets_dataout,
nfa_finals_buckets_size => grp_nfa_get_finals_fu_362_nfa_finals_buckets_size,
ap_ce => grp_nfa_get_finals_fu_362_ap_ce,
ap_return_0 => grp_nfa_get_finals_fu_362_ap_return_0,
ap_return_1 => grp_nfa_get_finals_fu_362_ap_return_1);
grp_p_bsf32_hw_fu_368 : component p_bsf32_hw
port map (
ap_clk => ap_clk,
ap_rst => ap_rst,
bus_r => grp_p_bsf32_hw_fu_368_bus_r,
ap_return => grp_p_bsf32_hw_fu_368_ap_return,
ap_ce => grp_p_bsf32_hw_fu_368_ap_ce);
nfa_accept_samples_generic_hw_add_32ns_32ns_32_8_U17 : component nfa_accept_samples_generic_hw_add_32ns_32ns_32_8
generic map (
ID => 17,
NUM_STAGE => 8,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst,
din0 => grp_fu_392_p0,
din1 => grp_fu_392_p1,
ce => grp_fu_392_ce,
dout => grp_fu_392_p2);
nfa_accept_samples_generic_hw_add_16ns_16ns_16_4_U18 : component nfa_accept_samples_generic_hw_add_16ns_16ns_16_4
generic map (
ID => 18,
NUM_STAGE => 4,
din0_WIDTH => 16,
din1_WIDTH => 16,
dout_WIDTH => 16)
port map (
clk => ap_clk,
reset => ap_rst,
din0 => grp_fu_402_p0,
din1 => grp_fu_402_p1,
ce => grp_fu_402_ce,
dout => grp_fu_402_p2);
nfa_accept_samples_generic_hw_add_32ns_32ns_32_8_U19 : component nfa_accept_samples_generic_hw_add_32ns_32ns_32_8
generic map (
ID => 19,
NUM_STAGE => 8,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst,
din0 => grp_fu_414_p0,
din1 => grp_fu_414_p1,
ce => grp_fu_414_ce,
dout => grp_fu_414_p2);
nfa_accept_samples_generic_hw_add_6ns_6ns_6_2_U20 : component nfa_accept_samples_generic_hw_add_6ns_6ns_6_2
generic map (
ID => 20,
NUM_STAGE => 2,
din0_WIDTH => 6,
din1_WIDTH => 6,
dout_WIDTH => 6)
port map (
clk => ap_clk,
reset => ap_rst,
din0 => grp_fu_463_p0,
din1 => grp_fu_463_p1,
ce => grp_fu_463_ce,
dout => grp_fu_463_p2);
nfa_accept_samples_generic_hw_mul_8ns_6ns_14_4_U21 : component nfa_accept_samples_generic_hw_mul_8ns_6ns_14_4
generic map (
ID => 21,
NUM_STAGE => 4,
din0_WIDTH => 8,
din1_WIDTH => 6,
dout_WIDTH => 14)
port map (
clk => ap_clk,
reset => ap_rst,
din0 => grp_fu_476_p0,
din1 => grp_fu_476_p1,
ce => grp_fu_476_ce,
dout => grp_fu_476_p2);
nfa_accept_samples_generic_hw_add_14ns_14ns_14_4_U22 : component nfa_accept_samples_generic_hw_add_14ns_14ns_14_4
generic map (
ID => 22,
NUM_STAGE => 4,
din0_WIDTH => 14,
din1_WIDTH => 14,
dout_WIDTH => 14)
port map (
clk => ap_clk,
reset => ap_rst,
din0 => grp_fu_482_p0,
din1 => grp_fu_482_p1,
ce => grp_fu_482_ce,
dout => grp_fu_482_p2);
-- the current state (ap_CS_fsm) of the state machine. --
ap_CS_fsm_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_CS_fsm <= ap_ST_st1_fsm_0;
else
ap_CS_fsm <= ap_NS_fsm;
end if;
end if;
end process;
-- ap_return_preg assign process. --
ap_return_preg_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_return_preg <= ap_const_lv1_0;
else
if ((ap_ST_st45_fsm_44 = ap_CS_fsm)) then
ap_return_preg <= p_0_reg_332;
end if;
end if;
end if;
end process;
-- grp_nfa_get_finals_fu_362_ap_start_ap_start_reg assign process. --
grp_nfa_get_finals_fu_362_ap_start_ap_start_reg_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
grp_nfa_get_finals_fu_362_ap_start_ap_start_reg <= ap_const_logic_0;
else
if (((ap_ST_st12_fsm_11 = ap_NS_fsm) and (ap_ST_st11_fsm_10 = ap_CS_fsm) and (tmp_s_reg_597 = ap_const_lv1_0))) then
grp_nfa_get_finals_fu_362_ap_start_ap_start_reg <= ap_const_logic_1;
elsif ((ap_const_logic_1 = grp_nfa_get_finals_fu_362_ap_ready)) then
grp_nfa_get_finals_fu_362_ap_start_ap_start_reg <= ap_const_logic_0;
end if;
end if;
end if;
end process;
-- agg_result_bucket_index_0_lcssa4_i_reg_190 assign process. --
agg_result_bucket_index_0_lcssa4_i_reg_190_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ST_st20_fsm_19 = ap_CS_fsm) and (tmp_2_1_i_reg_626 = ap_const_lv1_0))) then
agg_result_bucket_index_0_lcssa4_i_reg_190 <= ap_const_lv1_1;
elsif (((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((sample_rsp_empty_n = ap_const_logic_0)) and (tmp_2_i_reg_612 = ap_const_lv1_0))) then
agg_result_bucket_index_0_lcssa4_i_reg_190 <= ap_const_lv1_0;
end if;
end if;
end process;
-- any_reg_319 assign process. --
any_reg_319_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_ST_st24_fsm_23 = ap_CS_fsm)) then
any_reg_319 <= ap_const_lv1_0;
elsif ((ap_ST_st38_fsm_37 = ap_CS_fsm)) then
any_reg_319 <= ap_const_lv1_1;
end if;
end if;
end process;
-- bus_assign_reg_178 assign process. --
bus_assign_reg_178_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ST_st20_fsm_19 = ap_CS_fsm) and (tmp_2_1_i_reg_626 = ap_const_lv1_0))) then
bus_assign_reg_178 <= next_buckets_1_reg_158;
elsif (((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((sample_rsp_empty_n = ap_const_logic_0)) and (tmp_2_i_reg_612 = ap_const_lv1_0))) then
bus_assign_reg_178 <= next_buckets_0_reg_168;
end if;
end if;
end process;
-- i_reg_134 assign process. --
i_reg_134_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ST_st25_fsm_24 = ap_CS_fsm) and not((ap_const_lv1_0 = j_end_phi_fu_312_p4)) and not((ap_const_lv1_0 = any_phi_fu_324_p4)))) then
i_reg_134 <= i_1_reg_601;
elsif ((ap_ST_st4_fsm_3 = ap_CS_fsm)) then
i_reg_134 <= ap_const_lv16_0;
end if;
end if;
end process;
-- j_bit1_reg_299 assign process. --
j_bit1_reg_299_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_ST_st24_fsm_23 = ap_CS_fsm)) then
j_bit1_reg_299 <= j_bit1_ph_cast_fu_440_p1;
elsif ((ap_ST_st38_fsm_37 = ap_CS_fsm)) then
j_bit1_reg_299 <= j_bit_reg_701;
end if;
end if;
end process;
-- j_bucket1_ph_reg_203 assign process. --
j_bucket1_ph_reg_203_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_ST_st23_fsm_22 = ap_CS_fsm)) then
j_bucket1_ph_reg_203 <= bus_assign_reg_178;
elsif (((ap_ST_st20_fsm_19 = ap_CS_fsm) and not((tmp_2_1_i_reg_626 = ap_const_lv1_0)))) then
j_bucket1_ph_reg_203 <= ap_const_lv32_0;
end if;
end if;
end process;
-- j_bucket1_reg_278 assign process. --
j_bucket1_reg_278_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_ST_st24_fsm_23 = ap_CS_fsm)) then
j_bucket1_reg_278 <= j_bucket1_ph_reg_203;
elsif ((ap_ST_st38_fsm_37 = ap_CS_fsm)) then
j_bucket1_reg_278 <= j_bucket_reg_711;
end if;
end if;
end process;
-- j_bucket_index1_ph_reg_216 assign process. --
j_bucket_index1_ph_reg_216_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_ST_st23_fsm_22 = ap_CS_fsm)) then
j_bucket_index1_ph_reg_216 <= agg_result_bucket_index_0_lcssa4_i_cast_cast_fu_432_p1;
elsif (((ap_ST_st20_fsm_19 = ap_CS_fsm) and not((tmp_2_1_i_reg_626 = ap_const_lv1_0)))) then
j_bucket_index1_ph_reg_216 <= ap_const_lv2_2;
end if;
end if;
end process;
-- j_bucket_index1_reg_289 assign process. --
j_bucket_index1_reg_289_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_ST_st24_fsm_23 = ap_CS_fsm)) then
j_bucket_index1_reg_289 <= j_bucket_index1_ph_cast_fu_436_p1;
elsif ((ap_ST_st38_fsm_37 = ap_CS_fsm)) then
j_bucket_index1_reg_289 <= j_bucket_index_reg_706;
end if;
end if;
end process;
-- j_end_ph_reg_238 assign process. --
j_end_ph_reg_238_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_ST_st23_fsm_22 = ap_CS_fsm)) then
j_end_ph_reg_238 <= ap_const_lv1_0;
elsif (((ap_ST_st20_fsm_19 = ap_CS_fsm) and not((tmp_2_1_i_reg_626 = ap_const_lv1_0)))) then
j_end_ph_reg_238 <= ap_const_lv1_1;
end if;
end if;
end process;
-- j_end_reg_309 assign process. --
j_end_reg_309_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_ST_st24_fsm_23 = ap_CS_fsm)) then
j_end_reg_309 <= j_end_ph_reg_238;
elsif ((ap_ST_st38_fsm_37 = ap_CS_fsm)) then
j_end_reg_309 <= p_s_reg_716;
end if;
end if;
end process;
-- next_buckets_0_reg_168 assign process. --
next_buckets_0_reg_168_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ST_st25_fsm_24 = ap_CS_fsm) and not((ap_const_lv1_0 = j_end_phi_fu_312_p4)) and not((ap_const_lv1_0 = any_phi_fu_324_p4)))) then
next_buckets_0_reg_168 <= tmp_buckets_0_3_reg_265;
elsif ((ap_ST_st4_fsm_3 = ap_CS_fsm)) then
next_buckets_0_reg_168 <= current_buckets_0_reg_577;
end if;
end if;
end process;
-- next_buckets_1_reg_158 assign process. --
next_buckets_1_reg_158_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ST_st25_fsm_24 = ap_CS_fsm) and not((ap_const_lv1_0 = j_end_phi_fu_312_p4)) and not((ap_const_lv1_0 = any_phi_fu_324_p4)))) then
next_buckets_1_reg_158 <= tmp_buckets_1_3_reg_252;
elsif ((ap_ST_st4_fsm_3 = ap_CS_fsm)) then
next_buckets_1_reg_158 <= current_buckets_1_reg_582;
end if;
end if;
end process;
-- p_01_rec_reg_146 assign process. --
p_01_rec_reg_146_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ST_st25_fsm_24 = ap_CS_fsm) and not((ap_const_lv1_0 = j_end_phi_fu_312_p4)) and not((ap_const_lv1_0 = any_phi_fu_324_p4)))) then
p_01_rec_reg_146 <= p_rec_reg_616;
elsif ((ap_ST_st4_fsm_3 = ap_CS_fsm)) then
p_01_rec_reg_146 <= ap_const_lv32_0;
end if;
end if;
end process;
-- p_0_reg_332 assign process. --
p_0_reg_332_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ST_st25_fsm_24 = ap_CS_fsm) and not((ap_const_lv1_0 = j_end_phi_fu_312_p4)) and (ap_const_lv1_0 = any_phi_fu_324_p4))) then
p_0_reg_332 <= ap_const_lv1_0;
elsif ((ap_ST_st44_fsm_43 = ap_CS_fsm)) then
p_0_reg_332 <= tmp_2_reg_756;
end if;
end if;
end process;
-- tmp_buckets_0_3_reg_265 assign process. --
tmp_buckets_0_3_reg_265_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_ST_st24_fsm_23 = ap_CS_fsm)) then
tmp_buckets_0_3_reg_265 <= ap_const_lv32_0;
elsif ((ap_ST_st38_fsm_37 = ap_CS_fsm)) then
tmp_buckets_0_3_reg_265 <= next_buckets_0_1_reg_721;
end if;
end if;
end process;
-- tmp_buckets_1_3_reg_252 assign process. --
tmp_buckets_1_3_reg_252_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_ST_st24_fsm_23 = ap_CS_fsm)) then
tmp_buckets_1_3_reg_252 <= ap_const_lv32_0;
elsif ((ap_ST_st38_fsm_37 = ap_CS_fsm)) then
tmp_buckets_1_3_reg_252 <= next_buckets_1_1_fu_544_p2;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_ST_st41_fsm_40 = ap_CS_fsm)) then
current_buckets_0_1_reg_741 <= current_buckets_0_1_fu_558_p2;
current_buckets_1_1_reg_746 <= current_buckets_1_1_fu_563_p2;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_ST_st3_fsm_2 = ap_CS_fsm)) then
current_buckets_0_reg_577 <= grp_nfa_get_initials_fu_356_ap_return_0;
current_buckets_1_reg_582 <= grp_nfa_get_initials_fu_356_ap_return_1;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_ST_st8_fsm_7 = ap_CS_fsm)) then
i_1_reg_601 <= grp_fu_402_p2;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_ST_st23_fsm_22 = ap_CS_fsm)) then
j_bit1_ph_reg_227 <= r_bit_reg_630;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ST_st36_fsm_35 = ap_CS_fsm) and not((nfa_forward_buckets_rsp_empty_n = ap_const_logic_0)))) then
j_bit_reg_701 <= grp_bitset_next_fu_344_ap_return_0;
j_bucket_index_reg_706 <= grp_bitset_next_fu_344_ap_return_1;
j_bucket_reg_711 <= grp_bitset_next_fu_344_ap_return_2;
p_s_reg_716 <= grp_bitset_next_fu_344_ap_return_3;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((not((nfa_forward_buckets_rsp_empty_n = ap_const_logic_0)) and (ap_ST_st37_fsm_36 = ap_CS_fsm))) then
next_buckets_0_1_reg_721 <= next_buckets_0_1_fu_538_p2;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_ST_st34_fsm_33 = ap_CS_fsm)) then
offset_i_reg_685 <= grp_fu_482_p2;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((sample_rsp_empty_n = ap_const_logic_0)))) then
p_rec_reg_616 <= grp_fu_414_p2;
sym_reg_621 <= sample_datain;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_ST_st22_fsm_21 = ap_CS_fsm)) then
r_bit_reg_630 <= grp_p_bsf32_hw_fu_368_ap_return;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((((ap_ST_st36_fsm_35 = ap_CS_fsm) and not((nfa_forward_buckets_rsp_empty_n = ap_const_logic_0))) or (not((nfa_forward_buckets_rsp_empty_n = ap_const_logic_0)) and (ap_ST_st37_fsm_36 = ap_CS_fsm)))) then
reg_374 <= nfa_forward_buckets_datain;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_ST_st12_fsm_11 = ap_CS_fsm)) then
sample_addr_1_reg_606 <= grp_fu_392_p2;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_ST_st26_fsm_25 = ap_CS_fsm)) then
state_reg_665 <= grp_fu_463_p2;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_ST_st30_fsm_29 = ap_CS_fsm)) then
tmp_17_i_reg_680 <= grp_fu_476_p2;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_ST_st24_fsm_23 = ap_CS_fsm)) then
tmp_18_i_cast_reg_650(0) <= tmp_18_i_cast_fu_444_p1(0);
tmp_18_i_cast_reg_650(1) <= tmp_18_i_cast_fu_444_p1(1);
tmp_18_i_cast_reg_650(2) <= tmp_18_i_cast_fu_444_p1(2);
tmp_18_i_cast_reg_650(3) <= tmp_18_i_cast_fu_444_p1(3);
tmp_18_i_cast_reg_650(4) <= tmp_18_i_cast_fu_444_p1(4);
tmp_18_i_cast_reg_650(5) <= tmp_18_i_cast_fu_444_p1(5);
tmp_18_i_cast_reg_650(6) <= tmp_18_i_cast_fu_444_p1(6);
tmp_18_i_cast_reg_650(7) <= tmp_18_i_cast_fu_444_p1(7);
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_ST_st42_fsm_41 = ap_CS_fsm)) then
tmp_1_reg_751 <= tmp_1_fu_568_p2;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((sample_rsp_empty_n = ap_const_logic_0)) and not((tmp_2_i_reg_612 = ap_const_lv1_0)))) then
tmp_2_1_i_reg_626 <= tmp_2_1_i_fu_426_p2;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_ST_st18_fsm_17 = ap_CS_fsm)) then
tmp_2_i_reg_612 <= tmp_2_i_fu_420_p2;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_ST_st43_fsm_42 = ap_CS_fsm)) then
tmp_2_reg_756 <= tmp_2_fu_572_p2;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_ST_st40_fsm_39 = ap_CS_fsm)) then
tmp_buckets_0_reg_731 <= grp_nfa_get_finals_fu_362_ap_return_0;
tmp_buckets_1_reg_736 <= grp_nfa_get_finals_fu_362_ap_return_1;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_ST_st5_fsm_4 = ap_CS_fsm)) then
tmp_s_reg_597 <= tmp_s_fu_397_p2;
end if;
end if;
end process;
tmp_18_i_cast_reg_650(13 downto 8) <= "000000";
-- the next state (ap_NS_fsm) of the state machine. --
ap_NS_fsm_assign_proc : process (ap_start , ap_CS_fsm , nfa_forward_buckets_rsp_empty_n , sample_rsp_empty_n , tmp_s_reg_597 , tmp_2_i_reg_612 , tmp_2_1_i_reg_626 , j_end_phi_fu_312_p4 , any_phi_fu_324_p4)
begin
case ap_CS_fsm is
when ap_ST_st1_fsm_0 =>
if (not((ap_start = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st2_fsm_1;
else
ap_NS_fsm <= ap_ST_st1_fsm_0;
end if;
when ap_ST_st2_fsm_1 =>
ap_NS_fsm <= ap_ST_st3_fsm_2;
when ap_ST_st3_fsm_2 =>
ap_NS_fsm <= ap_ST_st4_fsm_3;
when ap_ST_st4_fsm_3 =>
ap_NS_fsm <= ap_ST_st5_fsm_4;
when ap_ST_st5_fsm_4 =>
ap_NS_fsm <= ap_ST_st6_fsm_5;
when ap_ST_st6_fsm_5 =>
ap_NS_fsm <= ap_ST_st7_fsm_6;
when ap_ST_st7_fsm_6 =>
ap_NS_fsm <= ap_ST_st8_fsm_7;
when ap_ST_st8_fsm_7 =>
ap_NS_fsm <= ap_ST_st9_fsm_8;
when ap_ST_st9_fsm_8 =>
ap_NS_fsm <= ap_ST_st10_fsm_9;
when ap_ST_st10_fsm_9 =>
ap_NS_fsm <= ap_ST_st11_fsm_10;
when ap_ST_st11_fsm_10 =>
ap_NS_fsm <= ap_ST_st12_fsm_11;
when ap_ST_st12_fsm_11 =>
if ((tmp_s_reg_597 = ap_const_lv1_0)) then
ap_NS_fsm <= ap_ST_st39_fsm_38;
else
ap_NS_fsm <= ap_ST_st13_fsm_12;
end if;
when ap_ST_st13_fsm_12 =>
ap_NS_fsm <= ap_ST_st14_fsm_13;
when ap_ST_st14_fsm_13 =>
ap_NS_fsm <= ap_ST_st15_fsm_14;
when ap_ST_st15_fsm_14 =>
ap_NS_fsm <= ap_ST_st16_fsm_15;
when ap_ST_st16_fsm_15 =>
ap_NS_fsm <= ap_ST_st17_fsm_16;
when ap_ST_st17_fsm_16 =>
ap_NS_fsm <= ap_ST_st18_fsm_17;
when ap_ST_st18_fsm_17 =>
ap_NS_fsm <= ap_ST_st19_fsm_18;
when ap_ST_st19_fsm_18 =>
if ((not((sample_rsp_empty_n = ap_const_logic_0)) and (tmp_2_i_reg_612 = ap_const_lv1_0))) then
ap_NS_fsm <= ap_ST_st21_fsm_20;
elsif ((not((sample_rsp_empty_n = ap_const_logic_0)) and not((tmp_2_i_reg_612 = ap_const_lv1_0)))) then
ap_NS_fsm <= ap_ST_st20_fsm_19;
else
ap_NS_fsm <= ap_ST_st19_fsm_18;
end if;
when ap_ST_st20_fsm_19 =>
if (not((tmp_2_1_i_reg_626 = ap_const_lv1_0))) then
ap_NS_fsm <= ap_ST_st24_fsm_23;
else
ap_NS_fsm <= ap_ST_st21_fsm_20;
end if;
when ap_ST_st21_fsm_20 =>
ap_NS_fsm <= ap_ST_st22_fsm_21;
when ap_ST_st22_fsm_21 =>
ap_NS_fsm <= ap_ST_st23_fsm_22;
when ap_ST_st23_fsm_22 =>
ap_NS_fsm <= ap_ST_st24_fsm_23;
when ap_ST_st24_fsm_23 =>
ap_NS_fsm <= ap_ST_st25_fsm_24;
when ap_ST_st25_fsm_24 =>
if ((not((ap_const_lv1_0 = j_end_phi_fu_312_p4)) and not((ap_const_lv1_0 = any_phi_fu_324_p4)))) then
ap_NS_fsm <= ap_ST_st5_fsm_4;
elsif ((not((ap_const_lv1_0 = j_end_phi_fu_312_p4)) and (ap_const_lv1_0 = any_phi_fu_324_p4))) then
ap_NS_fsm <= ap_ST_st45_fsm_44;
else
ap_NS_fsm <= ap_ST_st26_fsm_25;
end if;
when ap_ST_st26_fsm_25 =>
ap_NS_fsm <= ap_ST_st27_fsm_26;
when ap_ST_st27_fsm_26 =>
ap_NS_fsm <= ap_ST_st28_fsm_27;
when ap_ST_st28_fsm_27 =>
ap_NS_fsm <= ap_ST_st29_fsm_28;
when ap_ST_st29_fsm_28 =>
ap_NS_fsm <= ap_ST_st30_fsm_29;
when ap_ST_st30_fsm_29 =>
ap_NS_fsm <= ap_ST_st31_fsm_30;
when ap_ST_st31_fsm_30 =>
ap_NS_fsm <= ap_ST_st32_fsm_31;
when ap_ST_st32_fsm_31 =>
ap_NS_fsm <= ap_ST_st33_fsm_32;
when ap_ST_st33_fsm_32 =>
ap_NS_fsm <= ap_ST_st34_fsm_33;
when ap_ST_st34_fsm_33 =>
ap_NS_fsm <= ap_ST_st35_fsm_34;
when ap_ST_st35_fsm_34 =>
ap_NS_fsm <= ap_ST_st36_fsm_35;
when ap_ST_st36_fsm_35 =>
if (not((nfa_forward_buckets_rsp_empty_n = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st37_fsm_36;
else
ap_NS_fsm <= ap_ST_st36_fsm_35;
end if;
when ap_ST_st37_fsm_36 =>
if (not((nfa_forward_buckets_rsp_empty_n = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st38_fsm_37;
else
ap_NS_fsm <= ap_ST_st37_fsm_36;
end if;
when ap_ST_st38_fsm_37 =>
ap_NS_fsm <= ap_ST_st25_fsm_24;
when ap_ST_st39_fsm_38 =>
ap_NS_fsm <= ap_ST_st40_fsm_39;
when ap_ST_st40_fsm_39 =>
ap_NS_fsm <= ap_ST_st41_fsm_40;
when ap_ST_st41_fsm_40 =>
ap_NS_fsm <= ap_ST_st42_fsm_41;
when ap_ST_st42_fsm_41 =>
ap_NS_fsm <= ap_ST_st43_fsm_42;
when ap_ST_st43_fsm_42 =>
ap_NS_fsm <= ap_ST_st44_fsm_43;
when ap_ST_st44_fsm_43 =>
ap_NS_fsm <= ap_ST_st45_fsm_44;
when ap_ST_st45_fsm_44 =>
ap_NS_fsm <= ap_ST_st1_fsm_0;
when others =>
ap_NS_fsm <= "XXXXXX";
end case;
end process;
agg_result_bucket_index_0_lcssa4_i_cast_cast_fu_432_p1 <= std_logic_vector(resize(unsigned(agg_result_bucket_index_0_lcssa4_i_reg_190),2));
any_phi_fu_324_p4 <= any_reg_319;
-- ap_done assign process. --
ap_done_assign_proc : process(ap_start, ap_CS_fsm)
begin
if (((not((ap_const_logic_1 = ap_start)) and (ap_ST_st1_fsm_0 = ap_CS_fsm)) or (ap_ST_st45_fsm_44 = ap_CS_fsm))) then
ap_done <= ap_const_logic_1;
else
ap_done <= ap_const_logic_0;
end if;
end process;
-- ap_idle assign process. --
ap_idle_assign_proc : process(ap_start, ap_CS_fsm)
begin
if ((not((ap_const_logic_1 = ap_start)) and (ap_ST_st1_fsm_0 = ap_CS_fsm))) then
ap_idle <= ap_const_logic_1;
else
ap_idle <= ap_const_logic_0;
end if;
end process;
-- ap_ready assign process. --
ap_ready_assign_proc : process(ap_CS_fsm)
begin
if ((ap_ST_st45_fsm_44 = ap_CS_fsm)) then
ap_ready <= ap_const_logic_1;
else
ap_ready <= ap_const_logic_0;
end if;
end process;
-- ap_return assign process. --
ap_return_assign_proc : process(ap_CS_fsm, p_0_reg_332, ap_return_preg)
begin
if ((ap_ST_st45_fsm_44 = ap_CS_fsm)) then
ap_return <= p_0_reg_332;
else
ap_return <= ap_return_preg;
end if;
end process;
current_buckets_0_1_fu_558_p2 <= (next_buckets_0_reg_168 and tmp_buckets_0_reg_731);
current_buckets_1_1_fu_563_p2 <= (next_buckets_1_reg_158 and tmp_buckets_1_reg_736);
-- grp_bitset_next_fu_344_ap_ce assign process. --
grp_bitset_next_fu_344_ap_ce_assign_proc : process(ap_CS_fsm, nfa_forward_buckets_rsp_empty_n, j_end_phi_fu_312_p4)
begin
if ((((ap_ST_st36_fsm_35 = ap_CS_fsm) and not((nfa_forward_buckets_rsp_empty_n = ap_const_logic_0))) or ((ap_ST_st25_fsm_24 = ap_CS_fsm) and (ap_const_lv1_0 = j_end_phi_fu_312_p4)) or (ap_ST_st26_fsm_25 = ap_CS_fsm) or (ap_ST_st27_fsm_26 = ap_CS_fsm) or (ap_ST_st30_fsm_29 = ap_CS_fsm) or (ap_ST_st34_fsm_33 = ap_CS_fsm) or (ap_ST_st35_fsm_34 = ap_CS_fsm) or (ap_ST_st28_fsm_27 = ap_CS_fsm) or (ap_ST_st29_fsm_28 = ap_CS_fsm) or (ap_ST_st31_fsm_30 = ap_CS_fsm) or (ap_ST_st32_fsm_31 = ap_CS_fsm) or (ap_ST_st33_fsm_32 = ap_CS_fsm))) then
grp_bitset_next_fu_344_ap_ce <= ap_const_logic_1;
else
grp_bitset_next_fu_344_ap_ce <= ap_const_logic_0;
end if;
end process;
grp_bitset_next_fu_344_p_read <= next_buckets_1_reg_158;
grp_bitset_next_fu_344_r_bit <= j_bit1_reg_299;
grp_bitset_next_fu_344_r_bucket <= j_bucket1_reg_278;
grp_bitset_next_fu_344_r_bucket_index <= j_bucket_index1_reg_289;
grp_fu_392_ce <= ap_const_logic_1;
grp_fu_392_p0 <= p_01_rec_reg_146;
grp_fu_392_p1 <= empty;
grp_fu_402_ce <= ap_const_logic_1;
grp_fu_402_p0 <= i_reg_134;
grp_fu_402_p1 <= ap_const_lv16_1;
-- grp_fu_414_ce assign process. --
grp_fu_414_ce_assign_proc : process(ap_CS_fsm, sample_rsp_empty_n, tmp_s_reg_597)
begin
if (((ap_ST_st18_fsm_17 = ap_CS_fsm) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((sample_rsp_empty_n = ap_const_logic_0))) or ((ap_ST_st12_fsm_11 = ap_CS_fsm) and not((tmp_s_reg_597 = ap_const_lv1_0))) or (ap_ST_st13_fsm_12 = ap_CS_fsm) or (ap_ST_st14_fsm_13 = ap_CS_fsm) or (ap_ST_st15_fsm_14 = ap_CS_fsm) or (ap_ST_st16_fsm_15 = ap_CS_fsm) or (ap_ST_st17_fsm_16 = ap_CS_fsm))) then
grp_fu_414_ce <= ap_const_logic_1;
else
grp_fu_414_ce <= ap_const_logic_0;
end if;
end process;
grp_fu_414_p0 <= p_01_rec_reg_146;
grp_fu_414_p1 <= ap_const_lv32_1;
grp_fu_463_ce <= ap_const_logic_1;
grp_fu_463_p0 <= (tmp_5_fu_447_p1 & ap_const_lv5_0);
grp_fu_463_p1 <= j_bit1_reg_299(6 - 1 downto 0);
grp_fu_476_ce <= ap_const_logic_1;
grp_fu_476_p0 <= grp_fu_476_p00(8 - 1 downto 0);
grp_fu_476_p00 <= std_logic_vector(resize(unsigned(nfa_symbols),14));
grp_fu_476_p1 <= grp_fu_476_p10(6 - 1 downto 0);
grp_fu_476_p10 <= std_logic_vector(resize(unsigned(state_reg_665),14));
grp_fu_482_ce <= ap_const_logic_1;
grp_fu_482_p0 <= tmp_17_i_reg_680;
grp_fu_482_p1 <= tmp_18_i_cast_reg_650;
grp_nfa_get_finals_fu_362_ap_ce <= ap_const_logic_1;
grp_nfa_get_finals_fu_362_ap_start <= grp_nfa_get_finals_fu_362_ap_start_ap_start_reg;
grp_nfa_get_finals_fu_362_nfa_finals_buckets_datain <= nfa_finals_buckets_datain;
grp_nfa_get_finals_fu_362_nfa_finals_buckets_req_full_n <= nfa_finals_buckets_req_full_n;
grp_nfa_get_finals_fu_362_nfa_finals_buckets_rsp_empty_n <= nfa_finals_buckets_rsp_empty_n;
grp_nfa_get_initials_fu_356_ap_ce <= ap_const_logic_1;
-- grp_nfa_get_initials_fu_356_ap_start assign process. --
grp_nfa_get_initials_fu_356_ap_start_assign_proc : process(ap_start, ap_CS_fsm)
begin
if (((ap_ST_st1_fsm_0 = ap_CS_fsm) and not((ap_start = ap_const_logic_0)))) then
grp_nfa_get_initials_fu_356_ap_start <= ap_const_logic_1;
else
grp_nfa_get_initials_fu_356_ap_start <= ap_const_logic_0;
end if;
end process;
grp_nfa_get_initials_fu_356_nfa_initials_buckets_datain <= nfa_initials_buckets_datain;
grp_nfa_get_initials_fu_356_nfa_initials_buckets_req_full_n <= nfa_initials_buckets_req_full_n;
grp_nfa_get_initials_fu_356_nfa_initials_buckets_rsp_empty_n <= nfa_initials_buckets_rsp_empty_n;
-- grp_p_bsf32_hw_fu_368_ap_ce assign process. --
grp_p_bsf32_hw_fu_368_ap_ce_assign_proc : process(ap_CS_fsm)
begin
if (((ap_ST_st22_fsm_21 = ap_CS_fsm) or (ap_ST_st21_fsm_20 = ap_CS_fsm))) then
grp_p_bsf32_hw_fu_368_ap_ce <= ap_const_logic_1;
else
grp_p_bsf32_hw_fu_368_ap_ce <= ap_const_logic_0;
end if;
end process;
grp_p_bsf32_hw_fu_368_bus_r <= bus_assign_reg_178;
j_bit1_ph_cast_fu_440_p1 <= std_logic_vector(resize(unsigned(j_bit1_ph_reg_227),8));
j_bucket_index1_ph_cast_fu_436_p1 <= std_logic_vector(resize(unsigned(j_bucket_index1_ph_reg_216),8));
j_end_phi_fu_312_p4 <= j_end_reg_309;
next_buckets_0_1_fu_538_p2 <= (tmp_buckets_0_3_reg_265 or reg_374);
next_buckets_1_1_fu_544_p2 <= (tmp_buckets_1_3_reg_252 or reg_374);
nfa_finals_buckets_address <= grp_nfa_get_finals_fu_362_nfa_finals_buckets_address;
nfa_finals_buckets_dataout <= grp_nfa_get_finals_fu_362_nfa_finals_buckets_dataout;
nfa_finals_buckets_req_din <= grp_nfa_get_finals_fu_362_nfa_finals_buckets_req_din;
nfa_finals_buckets_req_write <= grp_nfa_get_finals_fu_362_nfa_finals_buckets_req_write;
nfa_finals_buckets_rsp_read <= grp_nfa_get_finals_fu_362_nfa_finals_buckets_rsp_read;
nfa_finals_buckets_size <= grp_nfa_get_finals_fu_362_nfa_finals_buckets_size;
-- nfa_forward_buckets_address assign process. --
nfa_forward_buckets_address_assign_proc : process(ap_CS_fsm, nfa_forward_buckets_rsp_empty_n, tmp_5_i_cast_fu_493_p1, tmp_6_i_cast_fu_511_p1)
begin
if (((ap_ST_st36_fsm_35 = ap_CS_fsm) and not((nfa_forward_buckets_rsp_empty_n = ap_const_logic_0)))) then
nfa_forward_buckets_address <= tmp_6_i_cast_fu_511_p1;
elsif ((ap_ST_st35_fsm_34 = ap_CS_fsm)) then
nfa_forward_buckets_address <= tmp_5_i_cast_fu_493_p1;
else
nfa_forward_buckets_address <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
nfa_forward_buckets_dataout <= ap_const_lv32_0;
nfa_forward_buckets_req_din <= ap_const_logic_0;
-- nfa_forward_buckets_req_write assign process. --
nfa_forward_buckets_req_write_assign_proc : process(ap_CS_fsm, nfa_forward_buckets_rsp_empty_n)
begin
if ((((ap_ST_st36_fsm_35 = ap_CS_fsm) and not((nfa_forward_buckets_rsp_empty_n = ap_const_logic_0))) or (ap_ST_st35_fsm_34 = ap_CS_fsm))) then
nfa_forward_buckets_req_write <= ap_const_logic_1;
else
nfa_forward_buckets_req_write <= ap_const_logic_0;
end if;
end process;
-- nfa_forward_buckets_rsp_read assign process. --
nfa_forward_buckets_rsp_read_assign_proc : process(ap_CS_fsm, nfa_forward_buckets_rsp_empty_n)
begin
if ((((ap_ST_st36_fsm_35 = ap_CS_fsm) and not((nfa_forward_buckets_rsp_empty_n = ap_const_logic_0))) or (not((nfa_forward_buckets_rsp_empty_n = ap_const_logic_0)) and (ap_ST_st37_fsm_36 = ap_CS_fsm)))) then
nfa_forward_buckets_rsp_read <= ap_const_logic_1;
else
nfa_forward_buckets_rsp_read <= ap_const_logic_0;
end if;
end process;
nfa_forward_buckets_size <= ap_const_lv32_1;
nfa_initials_buckets_address <= grp_nfa_get_initials_fu_356_nfa_initials_buckets_address;
nfa_initials_buckets_dataout <= grp_nfa_get_initials_fu_356_nfa_initials_buckets_dataout;
nfa_initials_buckets_req_din <= grp_nfa_get_initials_fu_356_nfa_initials_buckets_req_din;
nfa_initials_buckets_req_write <= grp_nfa_get_initials_fu_356_nfa_initials_buckets_req_write;
nfa_initials_buckets_rsp_read <= grp_nfa_get_initials_fu_356_nfa_initials_buckets_rsp_read;
nfa_initials_buckets_size <= grp_nfa_get_initials_fu_356_nfa_initials_buckets_size;
sample_address <= sample_addr_1_reg_606;
sample_dataout <= ap_const_lv8_0;
sample_req_din <= ap_const_logic_0;
-- sample_req_write assign process. --
sample_req_write_assign_proc : process(ap_CS_fsm)
begin
if ((ap_ST_st18_fsm_17 = ap_CS_fsm)) then
sample_req_write <= ap_const_logic_1;
else
sample_req_write <= ap_const_logic_0;
end if;
end process;
-- sample_rsp_read assign process. --
sample_rsp_read_assign_proc : process(ap_CS_fsm, sample_rsp_empty_n)
begin
if (((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((sample_rsp_empty_n = ap_const_logic_0)))) then
sample_rsp_read <= ap_const_logic_1;
else
sample_rsp_read <= ap_const_logic_0;
end if;
end process;
sample_size <= ap_const_lv32_1;
tmp_18_i_cast_fu_444_p1 <= std_logic_vector(resize(unsigned(sym_reg_621),14));
tmp_1_fu_568_p2 <= (current_buckets_1_1_reg_746 or current_buckets_0_1_reg_741);
tmp_2_1_i_fu_426_p2 <= "1" when (next_buckets_1_reg_158 = ap_const_lv32_0) else "0";
tmp_2_fu_572_p2 <= "0" when (tmp_1_reg_751 = ap_const_lv32_0) else "1";
tmp_2_i_fu_420_p2 <= "1" when (next_buckets_0_reg_168 = ap_const_lv32_0) else "0";
tmp_5_fu_447_p1 <= j_bucket_index1_reg_289(1 - 1 downto 0);
tmp_5_i_cast_fu_493_p1 <= std_logic_vector(resize(unsigned(tmp_5_i_fu_486_p3),32));
tmp_5_i_fu_486_p3 <= (offset_i_reg_685 & ap_const_lv1_0);
tmp_6_i_cast_fu_511_p1 <= std_logic_vector(resize(unsigned(tmp_6_i_fu_504_p3),32));
tmp_6_i_fu_504_p3 <= (offset_i_reg_685 & ap_const_lv1_1);
tmp_s_fu_397_p2 <= "1" when (unsigned(i_reg_134) < unsigned(length_r)) else "0";
end behav;
| lgpl-3.0 | 587ab8b1d3d2674e0d5937b4148584bc | 0.579495 | 2.764148 | false | false | false | false |
jairov4/accel-oil | solution_virtex5_plb/impl/pcores/nfa_accept_samples_generic_hw_top_v1_01_a/synhdl/vhdl/indices_if.vhd | 4 | 27,784 | -- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2014.1
-- Copyright (C) 2014 Xilinx Inc. All rights reserved.
--
-- ==============================================================
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity indices_if is
generic
(
C_PLB_AWIDTH : integer := 32;
C_PLB_DWIDTH : integer := 64;
PLB_ADDR_SHIFT : integer := 3;
USER_DATA_WIDTH : integer := 56;
USER_DATA_WIDTH_2N : integer := 64;
USER_ADDR_SHIFT : integer := 3; -- log2(byte_count_of_data_width)
REMOTE_DESTINATION_ADDRESS : std_logic_vector(0 to 31):= X"00000000"
);
port
(
-- Bus protocol ports, do not add to or delete
MPLB_Clk : in std_logic;
MPLB_Rst : in std_logic;
M_request : out std_logic;
M_priority : out std_logic_vector(0 to 1);
M_busLock : out std_logic;
M_RNW : out std_logic;
M_BE : out std_logic_vector(0 to C_PLB_DWIDTH/8-1);
M_MSize : out std_logic_vector(0 to 1);
M_size : out std_logic_vector(0 to 3);
M_type : out std_logic_vector(0 to 2);
M_TAttribute : out std_logic_vector(0 to 15);
M_lockErr : out std_logic;
M_abort : out std_logic;
M_ABus : out std_logic_vector(0 to C_PLB_AWIDTH-1);
M_UABus : out std_logic_vector(0 to 31);
M_wrDBus : out std_logic_vector(0 to C_PLB_DWIDTH-1);
M_wrBurst : out std_logic;
M_rdBurst : out std_logic;
PLB_MAddrAck : in std_logic;
PLB_MSSize : in std_logic_vector(0 to 1);
PLB_MRearbitrate : in std_logic;
PLB_MTimeout : in std_logic;
PLB_MBusy : in std_logic;
PLB_MRdErr : in std_logic;
PLB_MWrErr : in std_logic;
PLB_MIRQ : in std_logic;
PLB_MRdDBus : in std_logic_vector(0 to (C_PLB_DWIDTH-1));
PLB_MRdWdAddr : in std_logic_vector(0 to 3);
PLB_MRdDAck : in std_logic;
PLB_MRdBTerm : in std_logic;
PLB_MWrDAck : in std_logic;
PLB_MWrBTerm : in std_logic;
-- signals from user logic
USER_RdData : out std_logic_vector(USER_DATA_WIDTH - 1 downto 0); -- Bus read return data to user_logic
USER_WrData : in std_logic_vector(USER_DATA_WIDTH - 1 downto 0); -- Bus write data
USER_address : in std_logic_vector(31 downto 0); -- word offset from BASE_ADDRESS
USER_size : in std_logic_vector(31 downto 0); -- burst size of word
USER_req_nRW : in std_logic; -- req type 0: Read, 1: write
USER_req_full_n : out std_logic; -- req Fifo full
USER_req_push : in std_logic; -- req Fifo push (new request in)
USER_rsp_empty_n : out std_logic; -- return data FIFO empty
USER_rsp_pop : in std_logic -- return data FIFO pop
);
attribute SIGIS : string;
attribute SIGIS of MPLB_Clk : signal is "Clk";
attribute SIGIS of MPLB_Rst : signal is "Rst";
end entity;
------------------------------------------------------------------------------
-- Architecture section
------------------------------------------------------------------------------
architecture IMP of indices_if is
component indices_if_ap_fifo is
generic (
DATA_WIDTH : integer := 32;
ADDR_WIDTH : integer := 4;
DEPTH : integer := 16);
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
if_empty_n : OUT STD_LOGIC;
if_read : IN STD_LOGIC;
if_dout : OUT STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0);
if_full_n : OUT STD_LOGIC;
if_write : IN STD_LOGIC;
if_din : IN STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0) );
end component;
component indices_if_plb_master_if is
generic (
C_PLB_AWIDTH : integer := 32;
C_PLB_DWIDTH : integer := 64;
PLB_ADDR_SHIFT : integer := 3);
port (
-- Bus protocol ports, do not add to or delete
PLB_Clk : in std_logic;
PLB_Rst : in std_logic;
M_abort : out std_logic;
M_ABus : out std_logic_vector(0 to C_PLB_AWIDTH-1);
M_BE : out std_logic_vector(0 to C_PLB_DWIDTH/8-1);
M_busLock : out std_logic;
M_lockErr : out std_logic;
M_MSize : out std_logic_vector(0 to 1);
M_priority : out std_logic_vector(0 to 1);
M_rdBurst : out std_logic;
M_request : out std_logic;
M_RNW : out std_logic;
M_size : out std_logic_vector(0 to 3);
M_type : out std_logic_vector(0 to 2);
M_wrBurst : out std_logic;
M_wrDBus : out std_logic_vector(0 to C_PLB_DWIDTH-1);
PLB_MBusy : in std_logic;
PLB_MWrBTerm : in std_logic;
PLB_MWrDAck : in std_logic;
PLB_MAddrAck : in std_logic;
PLB_MRdBTerm : in std_logic;
PLB_MRdDAck : in std_logic;
PLB_MRdDBus : in std_logic_vector(0 to (C_PLB_DWIDTH-1));
PLB_MRdWdAddr : in std_logic_vector(0 to 3);
PLB_MRearbitrate : in std_logic;
PLB_MSSize : in std_logic_vector(0 to 1);
-- signals from user logic
BUS_RdData : out std_logic_vector(C_PLB_DWIDTH-1 downto 0); -- Bus read return data to user_logic
BUS_WrData : in std_logic_vector(C_PLB_DWIDTH-1 downto 0); -- Bus write data
BUS_address : in std_logic_vector(31 downto 0); -- word offset from BASE_ADDRESS
BUS_size : in std_logic_vector(31 downto 0); -- burst size of word
BUS_req_nRW : in std_logic; -- req type 0: Read, 1: write
BUS_req_BE : in std_logic_vector(C_PLB_DWIDTH/8 -1 downto 0); -- Bus write data byte enable
BUS_req_full_n : out std_logic; -- req Fifo full
BUS_req_push : in std_logic; -- req Fifo push (new request in)
BUS_rsp_nRW : out std_logic; -- return data FIFO rsp type
BUS_rsp_empty_n : out std_logic; -- return data FIFO empty
BUS_rsp_pop : in std_logic -- return data FIFO pop
);
end component;
-- type state_type is (IDLE, );
-- signal cs, ns : st_type;
constant PLB_BW : integer := C_PLB_DWIDTH;
constant PLB_BYTE_COUNT : integer := C_PLB_DWIDTH/8;
constant USER_DATA_BYTE_COUNT : integer := USER_DATA_WIDTH_2N/8;
constant REQ_FIFO_DATA_WIDTH : integer := 1 + 32 + 32 + USER_DATA_WIDTH_2N; -- nRW + addr + size + wr_data
constant REQ_FIFO_ADDR_WIDTH : integer := 5;
constant REQ_FIFO_DEPTH : integer := 32;
constant ALIGN_DATA_WIDTH : integer := USER_DATA_WIDTH_2N + PLB_BW;
constant ALIGN_DATA_BE_WIDTH : integer := (USER_DATA_WIDTH_2N + PLB_BW)/8;
signal user_phy_address : STD_LOGIC_VECTOR(31 downto 0);
-- request FIFO
signal req_fifo_empty_n : STD_LOGIC;
signal req_fifo_pop : STD_LOGIC;
signal req_fifo_dout : STD_LOGIC_VECTOR(REQ_FIFO_DATA_WIDTH - 1 downto 0);
signal req_fifo_full_n : STD_LOGIC;
signal req_fifo_push : STD_LOGIC;
signal req_fifo_din : STD_LOGIC_VECTOR(REQ_FIFO_DATA_WIDTH - 1 downto 0);
signal user_WrData_2N : STD_LOGIC_VECTOR(USER_DATA_WIDTH_2N-1 downto 0);
signal req_fifo_dout_req_nRW : STD_LOGIC;
signal req_fifo_dout_req_address : STD_LOGIC_VECTOR(31 downto 0);
signal req_fifo_dout_req_size, req_fifo_dout_req_size_normalize : STD_LOGIC_VECTOR(31 downto 0);
-- internal request information
signal req_nRW : STD_LOGIC;
signal req_address : STD_LOGIC_VECTOR(31 downto 0);
signal req_size, burst_size : STD_LOGIC_VECTOR(31 downto 0);
signal req_size_user : STD_LOGIC_VECTOR(31 downto 0);
signal req_BE : STD_LOGIC_VECTOR(PLB_BYTE_COUNT-1 downto 0);
signal req_WrData : STD_LOGIC_VECTOR(ALIGN_DATA_WIDTH -1 downto 0);
signal req_WrData_BE : STD_LOGIC_VECTOR(ALIGN_DATA_BE_WIDTH -1 downto 0);
signal req_WrData_byte_p : STD_LOGIC_VECTOR(PLB_ADDR_SHIFT-1 downto 0);
signal req_valid, req_SOP, req_EOP_user, req_EOP : STD_LOGIC;
signal req_burst_write_counter : STD_LOGIC_VECTOR(31 downto 0);
signal req_burst_mode, req_last_burst: STD_LOGIC;
-- interface to PLB_master_if module
signal PLB_master_if_req_full_n : STD_LOGIC;
signal PLB_master_if_req_push : STD_LOGIC;
signal PLB_master_if_dataout : STD_LOGIC_VECTOR(PLB_BW-1 downto 0);
signal PLB_master_if_rsp_nRW : STD_LOGIC;
signal PLB_master_if_rsp_empty_n : STD_LOGIC;
signal PLB_master_if_rsp_pop : STD_LOGIC;
signal USER_size_local: STD_LOGIC_VECTOR(31 downto 0);
-- rsp FIFO
constant RSP_FIFO_DATA_WIDTH : integer := PLB_ADDR_SHIFT + 32; -- addr + size
constant RSP_FIFO_ADDR_WIDTH : integer := 6;
constant RSP_FIFO_DEPTH : integer := 64;
signal rsp_fifo_empty_n : STD_LOGIC;
signal rsp_fifo_pop : STD_LOGIC;
signal rsp_fifo_dout : STD_LOGIC_VECTOR(RSP_FIFO_DATA_WIDTH -1 downto 0);
signal rsp_fifo_full_n : STD_LOGIC;
signal rsp_fifo_push : STD_LOGIC;
signal rsp_fifo_din : STD_LOGIC_VECTOR(RSP_FIFO_DATA_WIDTH -1 downto 0);
signal rsp_valid, rsp_SOP : STD_LOGIC;
signal rsp_addr : STD_LOGIC_VECTOR(PLB_ADDR_SHIFT-1 downto 0);
signal rsp_size : STD_LOGIC_VECTOR(31 downto 0);
signal rsp_rd_data : STD_LOGIC_VECTOR(ALIGN_DATA_WIDTH -1 downto 0);
signal rsp_rd_data_byte_count : STD_LOGIC_VECTOR(4 downto 0);
-- rd data user FIFO
signal rd_data_user_fifo_empty_n : STD_LOGIC;
signal rd_data_user_fifo_pop : STD_LOGIC;
signal rd_data_user_fifo_dout : STD_LOGIC_VECTOR(USER_DATA_WIDTH -1 downto 0);
signal rd_data_user_fifo_full_n : STD_LOGIC;
signal rd_data_user_fifo_push : STD_LOGIC;
signal rd_data_user_fifo_din : STD_LOGIC_VECTOR(USER_DATA_WIDTH -1 downto 0);
signal rd_data_user_fifo_din_2N : STD_LOGIC_VECTOR(USER_DATA_WIDTH_2N -1 downto 0);
signal BE_ALL_ONE : STD_LOGIC_VECTOR(PLB_BYTE_COUNT -1 downto 0);
begin
BE_ALL_ONE <= (others => '1');
M_UABus <= (others => '0');
M_TAttribute <= (others => '0');
-- interface to user logic
user_phy_address(31 downto USER_ADDR_SHIFT) <= REMOTE_DESTINATION_ADDRESS(0 to C_PLB_AWIDTH - USER_ADDR_SHIFT -1) + USER_address(31 -USER_ADDR_SHIFT downto 0);
user_phy_address(USER_ADDR_SHIFT-1 downto 0) <= REMOTE_DESTINATION_ADDRESS(C_PLB_AWIDTH - USER_ADDR_SHIFT to C_PLB_AWIDTH -1);
USER_size_local <= X"00000001" when conv_integer(USER_size(31 downto 1)) = 0 else USER_size;
USER_req_full_n <= req_fifo_full_n;
process(USER_WrData)
variable i: integer;
begin
user_WrData_2N <= (others=> '0');
for i in 0 to USER_WrData'length -1 loop
user_WrData_2N (USER_DATA_WIDTH_2N-1 -i) <= USER_WrData(i);
end loop;
end process;
req_fifo_din(REQ_FIFO_DATA_WIDTH-1) <= USER_req_nRW;
req_fifo_din(REQ_FIFO_DATA_WIDTH-1-1 downto REQ_FIFO_DATA_WIDTH -1-32) <= user_phy_address;
req_fifo_din(REQ_FIFO_DATA_WIDTH-1-32-1 downto REQ_FIFO_DATA_WIDTH -1-32-32) <= USER_size_local;
req_fifo_din(USER_DATA_WIDTH_2N -1 downto 0) <= user_WrData_2N(USER_DATA_WIDTH_2N-1 downto 0);
req_fifo_push <= USER_req_push;
U_indices_if_req_fifo: component indices_if_ap_fifo
generic map(
DATA_WIDTH => REQ_FIFO_DATA_WIDTH,
ADDR_WIDTH => REQ_FIFO_ADDR_WIDTH,
DEPTH => REQ_FIFO_DEPTH)
port map(
clk => MPLB_Clk,
reset => MPLB_Rst,
if_empty_n => req_fifo_empty_n,
if_read => req_fifo_pop,
if_dout => req_fifo_dout,
if_full_n => req_fifo_full_n,
if_write => req_fifo_push,
if_din => req_fifo_din
);
req_fifo_dout_req_nRW <= req_fifo_dout(REQ_FIFO_DATA_WIDTH -1);
req_fifo_dout_req_size <= req_fifo_dout(REQ_FIFO_DATA_WIDTH-1-32-1 downto REQ_FIFO_DATA_WIDTH -1-32-32);
req_fifo_dout_req_address <= req_fifo_dout(REQ_FIFO_DATA_WIDTH-1-1 downto REQ_FIFO_DATA_WIDTH -1-32);
req_fifo_dout_req_size_normalize(31 downto USER_ADDR_SHIFT) <= req_fifo_dout_req_size(31-USER_ADDR_SHIFT downto 0);
req_fifo_dout_req_size_normalize(USER_ADDR_SHIFT-1 downto 0) <= (others => '0');
process(req_fifo_empty_n, req_valid)
begin
req_fifo_pop <= '0';
if (req_fifo_empty_n = '1' and req_valid = '0') then -- lunch next request
req_fifo_pop <= '1';
end if;
end process;
process (MPLB_Clk, MPLB_Rst)
variable offset: integer;
begin
if (MPLB_Rst = '1') then
req_nRW <= '0';
burst_size <= (others => '0');
req_size_user <= (others => '0');
req_address <= (others => '0');
req_WrData <= (others => '0'); -- set possible MSB to ZERO
req_WrData_BE <= (others => '0'); -- set possible MSB to ZERO
req_WrData_byte_p <= (others => '0'); -- set possible MSB to ZERO
req_valid <= '0';
req_EOP <= '0';
req_burst_write_counter <= (others => '0');
req_burst_mode <= '0';
elsif (MPLB_Clk'event and MPLB_Clk = '1') then
if (req_fifo_pop = '1') then -- lunch next request
req_valid <= '1';
if (req_burst_mode = '0') then
if (req_fifo_dout_req_nRW = '0') then
if (req_fifo_dout_req_size_normalize(PLB_ADDR_SHIFT-1 downto 0) = CONV_STD_LOGIC_VECTOR(0,PLB_ADDR_SHIFT) and
req_fifo_dout_req_address(PLB_ADDR_SHIFT-1 downto 0) = CONV_STD_LOGIC_VECTOR(0,PLB_ADDR_SHIFT)) then
burst_size(31-PLB_ADDR_SHIFT downto 0) <= req_fifo_dout_req_size_normalize(31 downto PLB_ADDR_SHIFT);
elsif (('0'&req_fifo_dout_req_size_normalize(PLB_ADDR_SHIFT-1 downto 0)) +
('0'&req_fifo_dout_req_address(PLB_ADDR_SHIFT-1 downto 0)) <= PLB_BYTE_COUNT) then
burst_size(31-PLB_ADDR_SHIFT downto 0) <= req_fifo_dout_req_size_normalize(31 downto PLB_ADDR_SHIFT) + 1;
else
burst_size(31-PLB_ADDR_SHIFT downto 0) <= req_fifo_dout_req_size_normalize(31 downto PLB_ADDR_SHIFT) + 2;
end if;
else
burst_size <= X"00000001"; -- single by default
if (req_fifo_dout_req_size_normalize(31 downto PLB_ADDR_SHIFT+1) /= CONV_STD_LOGIC_VECTOR(0,31-PLB_ADDR_SHIFT)) then -- may burst
burst_size(31 downto 32-PLB_ADDR_SHIFT) <= (others=>'0'); -- burst_size for write operation
if (req_fifo_dout_req_address(PLB_ADDR_SHIFT-1 downto 0) = CONV_STD_LOGIC_VECTOR(0, PLB_ADDR_SHIFT)) or
(conv_integer(req_fifo_dout_req_address(PLB_ADDR_SHIFT-1 downto 0)) + conv_integer(req_fifo_dout_req_size_normalize(PLB_ADDR_SHIFT-1 downto 0)) >= PLB_BYTE_COUNT) then
burst_size(31-PLB_ADDR_SHIFT downto 0) <= req_fifo_dout_req_size_normalize(31 downto PLB_ADDR_SHIFT);
else
burst_size(31-PLB_ADDR_SHIFT downto 0) <= req_fifo_dout_req_size_normalize(31 downto PLB_ADDR_SHIFT)-1;
end if;
end if;
end if;
offset := conv_integer(req_fifo_dout_req_address(PLB_ADDR_SHIFT-1 downto 0));
if (req_fifo_dout_req_nRW = '1') then
req_WrData(USER_DATA_WIDTH_2N +offset*8 -1 downto offset*8) <= req_fifo_dout(USER_DATA_WIDTH_2N -1 downto 0);
req_WrData_BE(USER_DATA_BYTE_COUNT+offset-1 downto offset) <= (others => '1');
end if;
req_size_user <= req_fifo_dout_req_size; -- for read operation
req_nRW <= req_fifo_dout_req_nRW;
req_EOP <= '1';
req_address <= req_fifo_dout_req_address;
req_burst_write_counter <= req_fifo_dout_req_size;
req_WrData_byte_p <= req_fifo_dout_req_address(PLB_ADDR_SHIFT-1 downto 0) + USER_DATA_BYTE_COUNT;
if (req_fifo_dout_req_nRW = '1' and req_fifo_dout_req_size(31 downto 1) /= "0000000000000000000000000000000") then
req_burst_mode <= '1';
req_EOP <= '0';
end if;
else -- in a burst write process
req_burst_write_counter <= req_burst_write_counter -1;
offset := conv_integer(req_WrData_byte_p);
req_WrData(USER_DATA_WIDTH_2N +offset*8 -1 downto offset*8) <= req_fifo_dout(USER_DATA_WIDTH_2N -1 downto 0);
req_WrData_BE(USER_DATA_BYTE_COUNT+offset-1 downto offset) <= (others => '1');
req_WrData_byte_p <= req_WrData_byte_p + USER_DATA_BYTE_COUNT;
if (req_last_burst = '1') then
req_burst_mode <= '0';
req_EOP <= '1';
end if;
end if;
elsif (req_valid = '1') then
if (req_nRW = '0' and PLB_master_if_req_push = '1') then
req_valid <= '0';
elsif (req_nRW = '1') then
if (req_EOP = '1' and PLB_master_if_req_push = '1') then -- last burst request
if (req_WrData_BE(ALIGN_DATA_BE_WIDTH-1 downto PLB_BYTE_COUNT) = CONV_STD_LOGIC_VECTOR(0, ALIGN_DATA_BE_WIDTH-PLB_BYTE_COUNT)) then
req_valid <= '0';
req_EOP <= '0';
req_WrData <= (others=>'0');
req_WrData_BE <= (others => '0');
else
req_WrData(USER_DATA_WIDTH_2N + PLB_BW -1 downto USER_DATA_WIDTH_2N) <= (others => '0');
req_WrData(USER_DATA_WIDTH_2N -1 downto 0) <= req_WrData(USER_DATA_WIDTH_2N +PLB_BW -1 downto PLB_BW);
req_WrData_BE(ALIGN_DATA_BE_WIDTH -1 downto ALIGN_DATA_BE_WIDTH-PLB_BYTE_COUNT) <= (others => '0');
req_WrData_BE(ALIGN_DATA_BE_WIDTH -PLB_BYTE_COUNT-1 downto 0) <= req_WrData_BE(ALIGN_DATA_BE_WIDTH -1 downto PLB_BYTE_COUNT);
req_address(31 downto PLB_ADDR_SHIFT) <= req_address(31 downto PLB_ADDR_SHIFT) +1;
req_address(PLB_ADDR_SHIFT-1 downto 0) <= (others=>'0');
end if;
elsif (req_EOP = '0') then
if (req_WrData_BE(PLB_BYTE_COUNT-1) = '0') then
req_valid <= '0';
elsif (req_WrData_BE(PLB_BYTE_COUNT-1) = '1' and PLB_master_if_req_push = '1') then
req_WrData(USER_DATA_WIDTH_2N + PLB_BW -1 downto USER_DATA_WIDTH_2N) <= (others => '0');
req_WrData(USER_DATA_WIDTH_2N -1 downto 0) <= req_WrData(USER_DATA_WIDTH_2N +PLB_BW -1 downto PLB_BW);
req_WrData_BE(ALIGN_DATA_BE_WIDTH -1 downto ALIGN_DATA_BE_WIDTH-PLB_BYTE_COUNT) <= (others => '0');
req_WrData_BE(ALIGN_DATA_BE_WIDTH-PLB_BYTE_COUNT-1 downto 0) <= req_WrData_BE(ALIGN_DATA_BE_WIDTH -1 downto PLB_BYTE_COUNT);
req_address(31 downto PLB_ADDR_SHIFT) <= req_address(31 downto PLB_ADDR_SHIFT) +1;
req_address(PLB_ADDR_SHIFT-1 downto 0) <= (others=>'0');
end if;
end if;
end if;
end if;
end if;
end process;
req_last_burst <= '1' when (req_burst_mode = '1' and req_burst_write_counter(31 downto 0) = X"00000002") else '0';
process(req_nRW, req_WrData_BE, burst_size)
begin
req_size <= (others => '0');
if (req_nRW = '0') then
req_size <= burst_size;
elsif (req_WrData_BE(PLB_BYTE_COUNT-1 downto 0) = BE_ALL_ONE) then
req_size <= burst_size;
else
req_size <= X"00000001";
end if;
end process;
process(req_valid, PLB_master_if_req_full_n, req_nRW, req_WrData_BE)
begin
PLB_master_if_req_push <= '0';
if (req_valid = '1' and PLB_master_if_req_full_n = '1') then
if (req_nRW = '0') then
PLB_master_if_req_push <= '1'; -- only push when the last byte been push
elsif (req_WrData_BE(PLB_BYTE_COUNT-1) = '1' or (req_EOP = '1' and req_WrData_BE(PLB_BYTE_COUNT-1 downto 0) /= CONV_STD_LOGIC_VECTOR(0, PLB_BYTE_COUNT))) then
PLB_master_if_req_push <= '1'; -- only push when the last byte been push
end if;
end if;
end process;
req_BE <= req_WrData_BE(PLB_BYTE_COUNT-1 downto 0) when req_nRW = '1' else (others => '1');
U_indices_if_plb_master_if: component indices_if_plb_master_if
generic map(
C_PLB_AWIDTH => C_PLB_AWIDTH,
C_PLB_DWIDTH => C_PLB_DWIDTH,
PLB_ADDR_SHIFT => PLB_ADDR_SHIFT)
port map (
-- Bus protocol ports, do not add to or delete
PLB_Clk => MPLB_Clk,
PLB_Rst => MPLB_Rst,
M_abort => M_abort,
M_ABus => M_ABus,
M_BE => M_BE,
M_busLock => M_busLock,
M_lockErr => M_lockErr,
M_MSize => M_MSize,
M_priority => M_priority,
M_rdBurst => M_rdBurst,
M_request => M_request,
M_RNW => M_RNW,
M_size => M_size,
M_type => M_type,
M_wrBurst => M_wrBurst,
M_wrDBus => M_wrDBus,
PLB_MBusy => PLB_MBusy,
PLB_MWrBTerm => PLB_MWrBTerm,
PLB_MWrDAck => PLB_MWrDAck,
PLB_MAddrAck => PLB_MAddrAck,
PLB_MRdBTerm => PLB_MRdBTerm,
PLB_MRdDAck => PLB_MRdDAck,
PLB_MRdDBus => PLB_MRdDBus,
PLB_MRdWdAddr => PLB_MRdWdAddr,
PLB_MRearbitrate => PLB_MRearbitrate,
PLB_MSSize => PLB_MSSize,
-- signals from user logic
BUS_RdData => PLB_master_if_dataout,
BUS_WrData => req_WrData(PLB_BW-1 downto 0),
BUS_address => req_address,
BUS_size => req_size,
BUS_req_nRW => req_nRW,
BUS_req_BE => req_BE,
BUS_req_full_n => PLB_master_if_req_full_n,
BUS_req_push => PLB_master_if_req_push,
BUS_rsp_nRW => PLB_master_if_rsp_nRW,
BUS_rsp_empty_n => PLB_master_if_rsp_empty_n,
BUS_rsp_pop => PLB_master_if_rsp_pop
);
-- below is the response (bus read data) part
U_indices_if_rsp_fifo: component indices_if_ap_fifo
generic map(
DATA_WIDTH => RSP_FIFO_DATA_WIDTH,
ADDR_WIDTH => RSP_FIFO_ADDR_WIDTH,
DEPTH => RSP_FIFO_DEPTH)
port map(
clk => MPLB_Clk,
reset => MPLB_Rst,
if_empty_n => rsp_fifo_empty_n,
if_read => rsp_fifo_pop,
if_dout => rsp_fifo_dout,
if_full_n => rsp_fifo_full_n,
if_write => rsp_fifo_push,
if_din => rsp_fifo_din
);
rsp_fifo_din(32+PLB_ADDR_SHIFT-1 downto 32) <= req_address(PLB_ADDR_SHIFT-1 downto 0);
rsp_fifo_din(31 downto 0) <= req_size_user;
rsp_fifo_push <= PLB_master_if_req_push and (not req_nRW);
process (rsp_valid, PLB_master_if_rsp_empty_n, rsp_rd_data_byte_count)
begin
PLB_master_if_rsp_pop <= '0';
-- fetch data to rsp_rd_data until enough bytes
if (rsp_valid = '1' and PLB_master_if_rsp_empty_n = '1' and CONV_INTEGER(rsp_rd_data_byte_count) < USER_DATA_BYTE_COUNT) then
PLB_master_if_rsp_pop <= '1';
end if;
end process;
process (MPLB_Clk, MPLB_Rst)
begin
if (MPLB_Rst = '1') then
rsp_valid <= '0';
rsp_addr <= (others=> '0');
rsp_size <= (others=> '0');
rsp_SOP <= '1';
rsp_rd_data_byte_count <= (others => '0');
rsp_rd_data <= (others=>'0');
rsp_fifo_pop <= '0';
elsif (MPLB_Clk'event and MPLB_Clk = '1') then
rsp_fifo_pop <= '0';
if (rsp_valid = '0' and rsp_fifo_empty_n = '1') then
rsp_valid <= '1';
rsp_addr <= rsp_fifo_dout(32+PLB_ADDR_SHIFT-1 downto 32);
rsp_size <= rsp_fifo_dout(31 downto 0);
rsp_fifo_pop <= '1';
rsp_rd_data_byte_count <= (others=>'0');
rsp_SOP <= '1';
end if;
-- fetch data to rsp_rd_data until enough bytes
if (PLB_master_if_rsp_pop = '1') then
rsp_rd_data(USER_DATA_WIDTH_2N-1 downto 0) <= rsp_rd_data(USER_DATA_WIDTH_2N + PLB_BW -1 downto PLB_BW);
rsp_rd_data(USER_DATA_WIDTH_2N +PLB_BW -1 downto USER_DATA_WIDTH_2N) <= PLB_master_if_dataout;
if (rsp_SOP = '1') then
rsp_rd_data_byte_count <= rsp_rd_data_byte_count + PLB_BYTE_COUNT - rsp_addr;
rsp_SOP <= '0';
else
rsp_rd_data_byte_count <= rsp_rd_data_byte_count + PLB_BYTE_COUNT;
end if;
end if;
-- write one unit of data to USER LOGIC
if (rd_data_user_fifo_push = '1') then
rsp_size <= rsp_size -1;
rsp_rd_data_byte_count <= rsp_rd_data_byte_count - USER_DATA_BYTE_COUNT;
rsp_addr <= rsp_addr + USER_DATA_BYTE_COUNT;
if (rsp_size = X"00000001") then
rsp_valid <= '0';
end if;
end if;
end if;
end process;
process(rsp_addr, rsp_rd_data,rsp_valid, rd_data_user_fifo_full_n, rsp_rd_data_byte_count, rd_data_user_fifo_din_2N)
variable i: integer;
begin
case CONV_INTEGER(rsp_addr) is
when 0 => rd_data_user_fifo_din_2N <= rsp_rd_data(USER_DATA_WIDTH_2N +64 -1 downto 64);
when 1 => rd_data_user_fifo_din_2N <= rsp_rd_data(USER_DATA_WIDTH_2N +8 -1 downto 8);
when 2 => rd_data_user_fifo_din_2N <= rsp_rd_data(USER_DATA_WIDTH_2N +16 -1 downto 16);
when 3 => rd_data_user_fifo_din_2N <= rsp_rd_data(USER_DATA_WIDTH_2N +24 -1 downto 24);
when 4 => rd_data_user_fifo_din_2N <= rsp_rd_data(USER_DATA_WIDTH_2N +32 -1 downto 32);
when 5 => rd_data_user_fifo_din_2N <= rsp_rd_data(USER_DATA_WIDTH_2N +40 -1 downto 40);
when 6 => rd_data_user_fifo_din_2N <= rsp_rd_data(USER_DATA_WIDTH_2N +48 -1 downto 48);
when 7 => rd_data_user_fifo_din_2N <= rsp_rd_data(USER_DATA_WIDTH_2N +56 -1 downto 56);
when others => null;
end case;
for i in 0 to USER_DATA_WIDTH -1 loop
rd_data_user_fifo_din(i) <= rd_data_user_fifo_din_2N(USER_DATA_WIDTH_2N-1-i);
end loop;
rd_data_user_fifo_push <= '0';
if (rsp_valid = '1' and rd_data_user_fifo_full_n = '1' and
CONV_INTEGER(rsp_rd_data_byte_count)>= USER_DATA_BYTE_COUNT) then
rd_data_user_fifo_push <= '1';
end if;
end process;
U_indices_if_rd_data_user_fifo: component indices_if_ap_fifo
generic map(
DATA_WIDTH => USER_DATA_WIDTH,
ADDR_WIDTH => 5,
DEPTH => 32)
port map(
clk => MPLB_Clk,
reset => MPLB_Rst,
if_empty_n => rd_data_user_fifo_empty_n,
if_read => USER_rsp_pop,
if_dout => rd_data_user_fifo_dout,
if_full_n => rd_data_user_fifo_full_n,
if_write => rd_data_user_fifo_push,
if_din => rd_data_user_fifo_din
);
USER_RdData <= rd_data_user_fifo_dout;
USER_rsp_empty_n <= rd_data_user_fifo_empty_n;
end IMP;
| lgpl-3.0 | 5c32f61533210fdda0f1903e25b2c758 | 0.550713 | 3.272941 | false | false | false | false |
takeshineshiro/fpga_fibre_scan | HUCB2P0_150701/frontend/analytic_filter_h_a1.vhd | 1 | 3,644 | -- Implementation of Filter H_a1(z)
--
-- This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License
-- as published by the Free Software Foundation; either version 3 of the License, or (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied
-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License along with this program;
-- if not, see <http://www.gnu.org/licenses/>.
-- Package Definition
library ieee;
use ieee.std_logic_1164.all;
use IEEE.STD_LOGIC_arith.all;
package analytic_filter_h_a1_pkg is
component analytic_filter_h_a1
generic(
input_data_width : integer;
output_data_width : integer;
filter_delay_in_clks : integer --delay of hilbert filter
);
port(
clk_i : in std_logic;
rst_i : in std_logic;
data_str_i : in std_logic;
data_i : in std_logic_vector(input_data_width-1 downto 0);
data_i_o : out std_logic_vector(output_data_width-1 downto 0);
data_q_o : out std_logic_vector(output_data_width-1 downto 0);
data_str_o : out std_logic
);
end component;
end analytic_filter_h_a1_pkg;
package body analytic_filter_h_a1_pkg is
end analytic_filter_h_a1_pkg;
-- Entity Definition
library ieee;
use ieee.std_logic_1164.all;
use IEEE.STD_LOGIC_arith.all;
use work.const_delay_pkg.all;
use work.hilbert_filter_pkg.all;
entity analytic_filter_h_a1 is
generic(
input_data_width : integer := 16;
output_data_width : integer := 16;
filter_delay_in_clks : integer := 7 --delay of hilbert filter (including pipeline delay)
);
port(
clk_i : in std_logic;
rst_i : in std_logic;
data_str_i : in std_logic;
data_i : in std_logic_vector(input_data_width-1 downto 0);
data_i_o : out std_logic_vector(output_data_width-1 downto 0);
data_q_o : out std_logic_vector(output_data_width-1 downto 0);
data_str_o : out std_logic -- delay 7 clock than data_str_i
);
end analytic_filter_h_a1;
architecture analytic_filter_h_a1_arch of analytic_filter_h_a1 is
function maximum_int(
x1 : integer;
x2 : integer
) return integer is
begin
if x1 > x2 then
return x1;
else
return x2;
end if;
end maximum_int;
constant max_data_width : integer := maximum_int(input_data_width,output_data_width);
signal const_delay_data_i, const_delay_data_o : std_logic_vector(max_data_width-1 downto 0);
begin
const_delay_data_i(max_data_width-1 downto max_data_width-input_data_width) <= data_i;
zero_pad: if max_data_width-input_data_width > 0 generate
const_delay_data_i(max_data_width-input_data_width-1 downto 0) <= (others => '0');
end generate;
data_i_o <= const_delay_data_o(max_data_width-1 downto max_data_width-output_data_width);
in_phase_channel : const_delay
generic map(
data_width => max_data_width,
delay_in_clks => filter_delay_in_clks
)
port map(
clk_i => clk_i,
rst_i => rst_i,
data_i => const_delay_data_i,
data_str_i => data_str_i,
data_o => const_delay_data_o,
data_str_o => data_str_o
);
quadrature_phase_channel : hilbert_filter
generic map(
input_data_width => input_data_width,
output_data_width => output_data_width,
internal_data_width => max_data_width
)
port map(
clk => clk_i,
clk_enable => data_str_i,
reset => rst_i,
filter_in => data_i,
filter_out => data_q_o
);
end analytic_filter_h_a1_arch; | apache-2.0 | c114e668631d202b07594e63cd9bdf75 | 0.682492 | 3.01157 | false | false | false | false |
grwlf/vsim | vhdl_ct/ct00091.vhd | 1 | 11,576 | -- NEED RESULT: ARCH00091.P1: Multi transport transactions occurred on signal asg with selected name on LHS passed
-- NEED RESULT: ARCH00091.P2: Multi transport transactions occurred on signal asg with selected name on LHS failed
-- NEED RESULT: ARCH00091.P3: Multi transport transactions occurred on signal asg with selected name on LHS failed
-- NEED RESULT: ARCH00091: One transport transaction occurred on signal asg with selected name on LHS passed
-- NEED RESULT: ARCH00091: Old transactions were removed on signal asg with selected name on LHS passed
-- NEED RESULT: ARCH00091: One transport transaction occurred on signal asg with selected name on LHS failed
-- NEED RESULT: ARCH00091: Old transactions were removed on signal asg with selected name on LHS failed
-- NEED RESULT: ARCH00091: One transport transaction occurred on signal asg with selected name on LHS failed
-- NEED RESULT: ARCH00091: Old transactions were removed on signal asg with selected name on LHS failed
-- NEED RESULT: P3: Transport transactions entirely completed passed
-- NEED RESULT: P2: Transport transactions entirely completed passed
-- NEED RESULT: P1: Transport transactions entirely completed passed
-------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
-------------------------------------------------------------------------------
--
-- TEST NAME:
--
-- CT00091
--
-- AUTHOR:
--
-- G. Tominovich
--
-- TEST OBJECTIVES:
--
-- 8.3 (2)
-- 8.3 (3)
-- 8.3 (5)
-- 8.3.1 (3)
--
-- DESIGN UNIT ORDERING:
--
-- ENT00091(ARCH00091)
-- ENT00091_Test_Bench(ARCH00091_Test_Bench)
--
-- REVISION HISTORY:
--
-- 07-JUL-1987 - initial revision
--
-- NOTES:
--
-- self-checking
-- automatically generated
--
use WORK.STANDARD_TYPES.all ;
entity ENT00091 is
subtype chk_sig_type is integer range -1 to 100 ;
signal chk_st_rec1 : chk_sig_type := -1 ;
signal chk_st_rec2 : chk_sig_type := -1 ;
signal chk_st_rec3 : chk_sig_type := -1 ;
--
procedure Proc1 (
signal s_st_rec1 : inout st_rec1 ;
variable counter : inout integer ;
variable correct : inout boolean ;
variable savtime : inout time ;
signal chk_st_rec1 : out chk_sig_type
)
is
begin
case counter is
when 0
=> s_st_rec1.f2 <= transport
c_st_rec1_2.f2 after 10 ns,
c_st_rec1_1.f2 after 20 ns ;
--
when 1
=> correct :=
s_st_rec1.f2 = c_st_rec1_2.f2 and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_rec1.f2 = c_st_rec1_1.f2 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00091.P1" ,
"Multi transport transactions occurred on signal " &
"asg with selected name on LHS",
correct ) ;
s_st_rec1.f2 <= transport
c_st_rec1_2.f2 after 10 ns ,
c_st_rec1_1.f2 after 20 ns ,
c_st_rec1_2.f2 after 30 ns ,
c_st_rec1_1.f2 after 40 ns ;
--
when 3
=> correct :=
s_st_rec1.f2 = c_st_rec1_2.f2 and
(savtime + 10 ns) = Std.Standard.Now ;
s_st_rec1.f2 <= transport c_st_rec1_1.f2 after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_rec1.f2 = c_st_rec1_1.f2 and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00091" ,
"One transport transaction occurred on signal " &
"asg with selected name on LHS",
correct ) ;
test_report ( "ARCH00091" ,
"Old transactions were removed on signal " &
"asg with selected name on LHS",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00091" ,
"Old transactions were removed on signal " &
"asg with selected name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_st_rec1 <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
end Proc1 ;
--
procedure Proc2 (
signal s_st_rec2 : inout st_rec2 ;
variable counter : inout integer ;
variable correct : inout boolean ;
variable savtime : inout time ;
signal chk_st_rec2 : out chk_sig_type
)
is
begin
case counter is
when 0
=> s_st_rec2.f2 <= transport
c_st_rec2_2.f2 after 10 ns,
c_st_rec2_1.f2 after 20 ns ;
--
when 1
=> correct :=
s_st_rec2.f2 = c_st_rec2_2.f2 and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_rec2.f2 = c_st_rec2_1.f2 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00091.P2" ,
"Multi transport transactions occurred on signal " &
"asg with selected name on LHS",
correct ) ;
s_st_rec2.f2 <= transport
c_st_rec2_2.f2 after 10 ns ,
c_st_rec2_1.f2 after 20 ns ,
c_st_rec2_2.f2 after 30 ns ,
c_st_rec2_1.f2 after 40 ns ;
--
when 3
=> correct :=
s_st_rec2.f2 = c_st_rec2_2.f2 and
(savtime + 10 ns) = Std.Standard.Now ;
s_st_rec2.f2 <= transport c_st_rec2_1.f2 after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_rec2.f2 = c_st_rec2_1.f2 and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00091" ,
"One transport transaction occurred on signal " &
"asg with selected name on LHS",
correct ) ;
test_report ( "ARCH00091" ,
"Old transactions were removed on signal " &
"asg with selected name on LHS",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00091" ,
"Old transactions were removed on signal " &
"asg with selected name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_st_rec2 <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
end Proc2 ;
--
procedure Proc3 (
signal s_st_rec3 : inout st_rec3 ;
variable counter : inout integer ;
variable correct : inout boolean ;
variable savtime : inout time ;
signal chk_st_rec3 : out chk_sig_type
)
is
begin
case counter is
when 0
=> s_st_rec3.f2 <= transport
c_st_rec3_2.f2 after 10 ns,
c_st_rec3_1.f2 after 20 ns ;
--
when 1
=> correct :=
s_st_rec3.f2 = c_st_rec3_2.f2 and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_rec3.f2 = c_st_rec3_1.f2 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00091.P3" ,
"Multi transport transactions occurred on signal " &
"asg with selected name on LHS",
correct ) ;
s_st_rec3.f2 <= transport
c_st_rec3_2.f2 after 10 ns ,
c_st_rec3_1.f2 after 20 ns ,
c_st_rec3_2.f2 after 30 ns ,
c_st_rec3_1.f2 after 40 ns ;
--
when 3
=> correct :=
s_st_rec3.f2 = c_st_rec3_2.f2 and
(savtime + 10 ns) = Std.Standard.Now ;
s_st_rec3.f2 <= transport c_st_rec3_1.f2 after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_rec3.f2 = c_st_rec3_1.f2 and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00091" ,
"One transport transaction occurred on signal " &
"asg with selected name on LHS",
correct ) ;
test_report ( "ARCH00091" ,
"Old transactions were removed on signal " &
"asg with selected name on LHS",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00091" ,
"Old transactions were removed on signal " &
"asg with selected name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_st_rec3 <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
end Proc3 ;
--
--
end ENT00091 ;
--
architecture ARCH00091 of ENT00091 is
signal s_st_rec1 : st_rec1
:= c_st_rec1_1 ;
signal s_st_rec2 : st_rec2
:= c_st_rec2_1 ;
signal s_st_rec3 : st_rec3
:= c_st_rec3_1 ;
--
begin
PGEN_CHKP_1 :
process ( chk_st_rec1 )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P1" ,
"Transport transactions entirely completed",
chk_st_rec1 = 4 ) ;
end if ;
end process PGEN_CHKP_1 ;
--
P1 :
process ( s_st_rec1 )
variable counter : integer := 0 ;
variable correct : boolean ;
variable savtime : time ;
begin
Proc1 (
s_st_rec1,
counter,
correct,
savtime,
chk_st_rec1
) ;
end process P1 ;
--
PGEN_CHKP_2 :
process ( chk_st_rec2 )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P2" ,
"Transport transactions entirely completed",
chk_st_rec2 = 4 ) ;
end if ;
end process PGEN_CHKP_2 ;
--
P2 :
process ( s_st_rec2 )
variable counter : integer := 0 ;
variable correct : boolean ;
variable savtime : time ;
begin
Proc2 (
s_st_rec2,
counter,
correct,
savtime,
chk_st_rec2
) ;
end process P2 ;
--
PGEN_CHKP_3 :
process ( chk_st_rec3 )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P3" ,
"Transport transactions entirely completed",
chk_st_rec3 = 4 ) ;
end if ;
end process PGEN_CHKP_3 ;
--
P3 :
process ( s_st_rec3 )
variable counter : integer := 0 ;
variable correct : boolean ;
variable savtime : time ;
begin
Proc3 (
s_st_rec3,
counter,
correct,
savtime,
chk_st_rec3
) ;
end process P3 ;
--
--
end ARCH00091 ;
--
entity ENT00091_Test_Bench is
end ENT00091_Test_Bench ;
--
architecture ARCH00091_Test_Bench of ENT00091_Test_Bench is
begin
L1:
block
component UUT
end component ;
for CIS1 : UUT use entity WORK.ENT00091 ( ARCH00091 ) ;
begin
CIS1 : UUT ;
end block L1 ;
end ARCH00091_Test_Bench ;
| gpl-3.0 | f8b13c27124f8bb5ed86a66f6e64e118 | 0.504665 | 3.705506 | false | true | false | false |
grwlf/vsim | vhdl_ct/ct00201.vhd | 1 | 5,199 | -- NEED RESULT: ENT00201: Wait statement longest static prefix check passed
-- NEED RESULT: ENT00201: Wait statement longest static prefix check passed
-- NEED RESULT: ENT00201: Wait statement longest static prefix check passed
-- NEED RESULT: ENT00201: Wait statement longest static prefix check passed
-- NEED RESULT: P1: Wait longest static prefix test completed passed
-------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
-------------------------------------------------------------------------------
--
-- TEST NAME:
--
-- CT00201
--
-- AUTHOR:
--
-- G. Tominovich
--
-- TEST OBJECTIVES:
--
-- 8.1 (5)
--
-- DESIGN UNIT ORDERING:
--
-- ENT00201(ARCH00201)
-- ENT00201_Test_Bench(ARCH00201_Test_Bench)
--
-- REVISION HISTORY:
--
-- 10-JUL-1987 - initial revision
--
-- NOTES:
--
-- self-checking
-- automatically generated
--
use WORK.STANDARD_TYPES.all ;
entity ENT00201 is
generic (G : integer) ;
port (
s_st_int1_vector : inout st_int1_vector
) ;
--
constant CG : integer := G+1;
attribute attr : integer ;
attribute attr of CG : constant is CG+1;
--
end ENT00201 ;
--
--
architecture ARCH00201 of ENT00201 is
subtype chk_sig_type is integer range -1 to 100 ;
signal chk_st_int1_vector : chk_sig_type := -1 ;
--
begin
P1 :
process
variable counter : integer := 0 ;
variable correct : boolean ;
variable savtime : time := 0 ns ;
begin
case counter is
when 0
=>
s_st_int1_vector(1) <= transport
c_st_int1_vector_2(1) ;
s_st_int1_vector(2) <= transport
c_st_int1_vector_2(2) after 10 ns ;
wait until s_st_int1_vector(2) =
c_st_int1_vector_2(2) ;
Test_Report (
"ENT00201",
"Wait statement longest static prefix check",
((savtime + 10 ns) = Std.Standard.Now) and
(s_st_int1_vector(2) =
c_st_int1_vector_2(2) )) ;
--
when 1
=>
s_st_int1_vector(1) <= transport
c_st_int1_vector_1(1) ;
s_st_int1_vector(G) <= transport
c_st_int1_vector_2(G) after 10 ns ;
wait until s_st_int1_vector(G) =
c_st_int1_vector_2(G) ;
Test_Report (
"ENT00201",
"Wait statement longest static prefix check",
((savtime + 10 ns) = Std.Standard.Now) and
(s_st_int1_vector(G) =
c_st_int1_vector_2(G) )) ;
--
when 2
=>
s_st_int1_vector(1) <= transport
c_st_int1_vector_2(1) ;
s_st_int1_vector(CG) <= transport
c_st_int1_vector_2(CG) after 10 ns ;
wait until s_st_int1_vector(CG) =
c_st_int1_vector_2(CG) ;
Test_Report (
"ENT00201",
"Wait statement longest static prefix check",
((savtime + 10 ns) = Std.Standard.Now) and
(s_st_int1_vector(CG) =
c_st_int1_vector_2(CG) )) ;
--
when 3
=>
s_st_int1_vector(1) <= transport
c_st_int1_vector_1(1) ;
s_st_int1_vector(CG'Attr) <= transport
c_st_int1_vector_2(CG'Attr) after 10 ns ;
wait until s_st_int1_vector(CG'Attr) =
c_st_int1_vector_2(CG'Attr) ;
Test_Report (
"ENT00201",
"Wait statement longest static prefix check",
((savtime + 10 ns) = Std.Standard.Now) and
(s_st_int1_vector(CG'Attr) =
c_st_int1_vector_2(CG'Attr) )) ;
--
when others
=> wait ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_st_int1_vector <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
end process P1 ;
--
PGEN_CHKP_1 :
process ( chk_st_int1_vector )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P1" ,
"Wait longest static prefix test completed",
chk_st_int1_vector = 3 ) ;
end if ;
end process PGEN_CHKP_1 ;
--
--
end ARCH00201 ;
--
--
use WORK.STANDARD_TYPES.all ;
entity ENT00201_Test_Bench is
end ENT00201_Test_Bench ;
--
--
architecture ARCH00201_Test_Bench of ENT00201_Test_Bench is
begin
L1:
block
signal s_st_int1_vector : st_int1_vector
:= c_st_int1_vector_1 ;
--
component UUT
generic (G : integer) ;
port (
s_st_int1_vector : inout st_int1_vector
) ;
end component ;
--
for CIS1 : UUT use entity WORK.ENT00201 ( ARCH00201 ) ;
begin
CIS1 : UUT
generic map (lowb+2)
port map (
s_st_int1_vector
)
;
end block L1 ;
end ARCH00201_Test_Bench ;
| gpl-3.0 | 8860cbcb93aeeffb2c2a24ac51d81e9d | 0.490287 | 3.503369 | false | true | false | false |
SamuelLBau/Pool-Shot-Tracking-using-FPGA | examples/sparse_mm/solution1/syn/vhdl/sparse_mm_mul_32s_32s_32_3.vhd | 1 | 2,705 | -- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2015.4
-- Copyright (C) 2015 Xilinx Inc. All rights reserved.
--
-- ==============================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity sparse_mm_mul_32s_32s_32_3_Mul3S_0 is
port (
clk: in std_logic;
ce: in std_logic;
a: in std_logic_vector(32 - 1 downto 0);
b: in std_logic_vector(32 - 1 downto 0);
p: out std_logic_vector(32 - 1 downto 0));
end entity;
architecture behav of sparse_mm_mul_32s_32s_32_3_Mul3S_0 is
signal tmp_product : std_logic_vector(32 - 1 downto 0);
signal a_i : std_logic_vector(32 - 1 downto 0);
signal b_i : std_logic_vector(32 - 1 downto 0);
signal p_tmp : std_logic_vector(32 - 1 downto 0);
signal a_reg0 : std_logic_vector(32 - 1 downto 0);
signal b_reg0 : std_logic_vector(32 - 1 downto 0);
attribute keep : string;
attribute keep of a_i : signal is "true";
attribute keep of b_i : signal is "true";
signal buff0 : std_logic_vector(32 - 1 downto 0);
begin
a_i <= a;
b_i <= b;
p <= p_tmp;
p_tmp <= buff0;
tmp_product <= std_logic_vector(resize(unsigned(std_logic_vector(signed(a_reg0) * signed(b_reg0))), 32));
process(clk)
begin
if (clk'event and clk = '1') then
if (ce = '1') then
a_reg0 <= a_i;
b_reg0 <= b_i;
buff0 <= tmp_product;
end if;
end if;
end process;
end architecture;
Library IEEE;
use IEEE.std_logic_1164.all;
entity sparse_mm_mul_32s_32s_32_3 is
generic (
ID : INTEGER;
NUM_STAGE : INTEGER;
din0_WIDTH : INTEGER;
din1_WIDTH : INTEGER;
dout_WIDTH : INTEGER);
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
ce : IN STD_LOGIC;
din0 : IN STD_LOGIC_VECTOR(din0_WIDTH - 1 DOWNTO 0);
din1 : IN STD_LOGIC_VECTOR(din1_WIDTH - 1 DOWNTO 0);
dout : OUT STD_LOGIC_VECTOR(dout_WIDTH - 1 DOWNTO 0));
end entity;
architecture arch of sparse_mm_mul_32s_32s_32_3 is
component sparse_mm_mul_32s_32s_32_3_Mul3S_0 is
port (
clk : IN STD_LOGIC;
ce : IN STD_LOGIC;
a : IN STD_LOGIC_VECTOR;
b : IN STD_LOGIC_VECTOR;
p : OUT STD_LOGIC_VECTOR);
end component;
begin
sparse_mm_mul_32s_32s_32_3_Mul3S_0_U : component sparse_mm_mul_32s_32s_32_3_Mul3S_0
port map (
clk => clk,
ce => ce,
a => din0,
b => din1,
p => dout);
end architecture;
| gpl-3.0 | a32ebcffc885615ec7c0a71729374d48 | 0.548983 | 3.178613 | false | false | false | false |
Given-Jiang/Binarization | tb_Binarization/db/alt_dspbuilder_delay.vhd | 1 | 3,978 | -- This file is not intended for synthesis, is is present so that simulators
-- see a complete view of the system.
-- You may use the entity declaration from this file as the basis for a
-- component declaration in a VHDL file instantiating this entity.
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.NUMERIC_STD.all;
entity alt_dspbuilder_delay is
generic (
CLOCKPHASE : string := "1";
DELAY : positive := 1;
USE_INIT : natural := 0;
BITPATTERN : string := "00000001";
WIDTH : positive := 8
);
port (
input : in std_logic_vector(width-1 downto 0) := (others=>'0');
clock : in std_logic := '0';
sclr : in std_logic := '0';
aclr : in std_logic := '0';
output : out std_logic_vector(width-1 downto 0);
ena : in std_logic := '0'
);
end entity alt_dspbuilder_delay;
architecture rtl of alt_dspbuilder_delay is
component alt_dspbuilder_delay_GNUECIBFDH is
generic (
CLOCKPHASE : string := "1";
DELAY : positive := 1;
USE_INIT : natural := 1;
BITPATTERN : string := "0";
WIDTH : positive := 1
);
port (
aclr : in std_logic := '0';
clock : in std_logic := '0';
ena : in std_logic := '0';
input : in std_logic_vector(1-1 downto 0) := (others=>'0');
output : out std_logic_vector(1-1 downto 0);
sclr : in std_logic := '0'
);
end component alt_dspbuilder_delay_GNUECIBFDH;
component alt_dspbuilder_delay_GNVTJPHWYT is
generic (
CLOCKPHASE : string := "1";
DELAY : positive := 1;
USE_INIT : natural := 1;
BITPATTERN : string := "01111111";
WIDTH : positive := 8
);
port (
aclr : in std_logic := '0';
clock : in std_logic := '0';
ena : in std_logic := '0';
input : in std_logic_vector(8-1 downto 0) := (others=>'0');
output : out std_logic_vector(8-1 downto 0);
sclr : in std_logic := '0'
);
end component alt_dspbuilder_delay_GNVTJPHWYT;
component alt_dspbuilder_delay_GNHYCSAEGT is
generic (
CLOCKPHASE : string := "1";
DELAY : positive := 1;
USE_INIT : natural := 0;
BITPATTERN : string := "0";
WIDTH : positive := 1
);
port (
aclr : in std_logic := '0';
clock : in std_logic := '0';
ena : in std_logic := '0';
input : in std_logic_vector(1-1 downto 0) := (others=>'0');
output : out std_logic_vector(1-1 downto 0);
sclr : in std_logic := '0'
);
end component alt_dspbuilder_delay_GNHYCSAEGT;
begin
alt_dspbuilder_delay_GNUECIBFDH_0: if ((CLOCKPHASE = "1") and (DELAY = 1) and (USE_INIT = 1) and (BITPATTERN = "0") and (WIDTH = 1)) generate
inst_alt_dspbuilder_delay_GNUECIBFDH_0: alt_dspbuilder_delay_GNUECIBFDH
generic map(CLOCKPHASE => "1", DELAY => 1, USE_INIT => 1, BITPATTERN => "0", WIDTH => 1)
port map(aclr => aclr, clock => clock, ena => ena, input => input, output => output, sclr => sclr);
end generate;
alt_dspbuilder_delay_GNVTJPHWYT_1: if ((CLOCKPHASE = "1") and (DELAY = 1) and (USE_INIT = 1) and (BITPATTERN = "01111111") and (WIDTH = 8)) generate
inst_alt_dspbuilder_delay_GNVTJPHWYT_1: alt_dspbuilder_delay_GNVTJPHWYT
generic map(CLOCKPHASE => "1", DELAY => 1, USE_INIT => 1, BITPATTERN => "01111111", WIDTH => 8)
port map(aclr => aclr, clock => clock, ena => ena, input => input, output => output, sclr => sclr);
end generate;
alt_dspbuilder_delay_GNHYCSAEGT_2: if ((CLOCKPHASE = "1") and (DELAY = 1) and (USE_INIT = 0) and (BITPATTERN = "0") and (WIDTH = 1)) generate
inst_alt_dspbuilder_delay_GNHYCSAEGT_2: alt_dspbuilder_delay_GNHYCSAEGT
generic map(CLOCKPHASE => "1", DELAY => 1, USE_INIT => 0, BITPATTERN => "0", WIDTH => 1)
port map(aclr => aclr, clock => clock, ena => ena, input => input, output => output, sclr => sclr);
end generate;
assert not (((CLOCKPHASE = "1") and (DELAY = 1) and (USE_INIT = 1) and (BITPATTERN = "0") and (WIDTH = 1)) or ((CLOCKPHASE = "1") and (DELAY = 1) and (USE_INIT = 1) and (BITPATTERN = "01111111") and (WIDTH = 8)) or ((CLOCKPHASE = "1") and (DELAY = 1) and (USE_INIT = 0) and (BITPATTERN = "0") and (WIDTH = 1)))
report "Please run generate again" severity error;
end architecture rtl;
| mit | 79f503e8c0c91f3d43867d3c41c18782 | 0.643539 | 3.124902 | false | false | false | false |
grwlf/vsim | vhdl_ct/ct00042.vhd | 1 | 9,180 | -- NEED RESULT: ARCH00042.P1: Target of a variable assignment may be a slice prefixed by an indexed name passed
-- NEED RESULT: ARCH00042.P2: Target of a variable assignment may be a slice prefixed by an indexed name passed
-- NEED RESULT: ARCH00042.P3: Target of a variable assignment may be a slice prefixed by an indexed name passed
-- NEED RESULT: ARCH00042.P4: Target of a variable assignment may be a slice prefixed by an indexed name passed
-------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
-------------------------------------------------------------------------------
--
-- TEST NAME:
--
-- CT00042
--
-- AUTHOR:
--
-- G. Tominovich
--
-- TEST OBJECTIVES:
--
-- 8.4 (1)
-- 8.4 (3)
--
-- DESIGN UNIT ORDERING:
--
-- E00000(ARCH00042)
-- ENT00042_Test_Bench(ARCH00042_Test_Bench)
--
-- REVISION HISTORY:
--
-- 29-JUN-1987 - initial revision
--
-- NOTES:
--
-- self-checking
-- automatically generated
--
use WORK.STANDARD_TYPES.all ;
architecture ARCH00042 of E00000 is
signal Dummy : Boolean := false ;
--
begin
P1 :
process ( Dummy )
variable v_st_rec3_vector : st_rec3_vector :=
c_st_rec3_vector_1 ;
variable v_st_arr1_vector : st_arr1_vector :=
c_st_arr1_vector_1 ;
variable v_st_arr2_vector : st_arr2_vector :=
c_st_arr2_vector_1 ;
--
variable correct : boolean := true ;
begin
v_st_rec3_vector(lowb).f3(st_arr2'Left(1),st_arr2'Left(2))
(lowb+1 to highb-1)
:= c_st_rec3_vector_2(lowb).f3(st_arr2'Right(1),st_arr2'Right(2))
(lowb+1 to highb-1) ;
--
v_st_arr1_vector(lowb)(lowb+1 to highb-1)
:= c_st_arr1_vector_2(lowb)(lowb+1 to highb-1) ;
--
v_st_arr2_vector(lowb)(st_arr2'Left(1),st_arr2'Left(2))
(lowb+1 to highb-1)
:= c_st_arr2_vector_2(lowb)(st_arr2'Right(1),st_arr2'Right(2))
(lowb+1 to highb-1) ;
--
--
correct :=
correct and
v_st_rec3_vector(lowb).f3(st_arr2'Left(1),st_arr2'Left(2))
(lowb+1 to highb-1) =
c_st_rec3_vector_2(lowb).f3(st_arr2'Right(1),st_arr2'Right(2))
(lowb+1 to highb-1) ;
--
correct :=
correct and
v_st_arr1_vector(lowb)(lowb+1 to highb-1) =
c_st_arr1_vector_2(lowb)(lowb+1 to highb-1) ;
--
correct :=
correct and
v_st_arr2_vector(lowb)(st_arr2'Left(1),st_arr2'Left(2))
(lowb+1 to highb-1) =
c_st_arr2_vector_2(lowb)(st_arr2'Right(1),st_arr2'Right(2))
(lowb+1 to highb-1) ;
--
--
test_report ( "ARCH00042.P1" ,
"Target of a variable assignment may be a " &
"slice prefixed by an indexed name" ,
correct) ;
end process P1 ;
--
P2 :
process ( Dummy )
variable correct : boolean := true ;
--
procedure Proc1 is
variable v_st_rec3_vector : st_rec3_vector :=
c_st_rec3_vector_1 ;
variable v_st_arr1_vector : st_arr1_vector :=
c_st_arr1_vector_1 ;
variable v_st_arr2_vector : st_arr2_vector :=
c_st_arr2_vector_1 ;
--
begin
v_st_rec3_vector(lowb).f3(st_arr2'Left(1),st_arr2'Left(2))
(lowb+1 to highb-1)
:= c_st_rec3_vector_2(lowb).f3(st_arr2'Right(1),st_arr2'Right(2))
(lowb+1 to highb-1) ;
--
v_st_arr1_vector(lowb)(lowb+1 to highb-1)
:= c_st_arr1_vector_2(lowb)(lowb+1 to highb-1) ;
--
v_st_arr2_vector(lowb)(st_arr2'Left(1),st_arr2'Left(2))
(lowb+1 to highb-1)
:= c_st_arr2_vector_2(lowb)(st_arr2'Right(1),st_arr2'Right(2))
(lowb+1 to highb-1) ;
--
--
correct :=
correct and
v_st_rec3_vector(lowb).f3(st_arr2'Left(1),st_arr2'Left(2))
(lowb+1 to highb-1) =
c_st_rec3_vector_2(lowb).f3(st_arr2'Right(1),st_arr2'Right(2))
(lowb+1 to highb-1) ;
--
correct :=
correct and
v_st_arr1_vector(lowb)(lowb+1 to highb-1) =
c_st_arr1_vector_2(lowb)(lowb+1 to highb-1) ;
--
correct :=
correct and
v_st_arr2_vector(lowb)(st_arr2'Left(1),st_arr2'Left(2))
(lowb+1 to highb-1) =
c_st_arr2_vector_2(lowb)(st_arr2'Right(1),st_arr2'Right(2))
(lowb+1 to highb-1) ;
--
--
end Proc1 ;
begin
Proc1 ;
test_report ( "ARCH00042.P2" ,
"Target of a variable assignment may be a " &
"slice prefixed by an indexed name" ,
correct) ;
end process P2 ;
--
P3 :
process ( Dummy )
variable v_st_rec3_vector : st_rec3_vector :=
c_st_rec3_vector_1 ;
variable v_st_arr1_vector : st_arr1_vector :=
c_st_arr1_vector_1 ;
variable v_st_arr2_vector : st_arr2_vector :=
c_st_arr2_vector_1 ;
--
variable correct : boolean := true ;
--
procedure Proc1 is
begin
v_st_rec3_vector(lowb).f3(st_arr2'Left(1),st_arr2'Left(2))
(lowb+1 to highb-1)
:= c_st_rec3_vector_2(lowb).f3(st_arr2'Right(1),st_arr2'Right(2))
(lowb+1 to highb-1) ;
--
v_st_arr1_vector(lowb)(lowb+1 to highb-1)
:= c_st_arr1_vector_2(lowb)(lowb+1 to highb-1) ;
--
v_st_arr2_vector(lowb)(st_arr2'Left(1),st_arr2'Left(2))
(lowb+1 to highb-1)
:= c_st_arr2_vector_2(lowb)(st_arr2'Right(1),st_arr2'Right(2))
(lowb+1 to highb-1) ;
--
--
end Proc1 ;
begin
Proc1 ;
correct :=
correct and
v_st_rec3_vector(lowb).f3(st_arr2'Left(1),st_arr2'Left(2))
(lowb+1 to highb-1) =
c_st_rec3_vector_2(lowb).f3(st_arr2'Right(1),st_arr2'Right(2))
(lowb+1 to highb-1) ;
--
correct :=
correct and
v_st_arr1_vector(lowb)(lowb+1 to highb-1) =
c_st_arr1_vector_2(lowb)(lowb+1 to highb-1) ;
--
correct :=
correct and
v_st_arr2_vector(lowb)(st_arr2'Left(1),st_arr2'Left(2))
(lowb+1 to highb-1) =
c_st_arr2_vector_2(lowb)(st_arr2'Right(1),st_arr2'Right(2))
(lowb+1 to highb-1) ;
--
--
test_report ( "ARCH00042.P3" ,
"Target of a variable assignment may be a " &
"slice prefixed by an indexed name" ,
correct) ;
end process P3 ;
--
P4 :
process ( Dummy )
variable v_st_rec3_vector : st_rec3_vector :=
c_st_rec3_vector_1 ;
variable v_st_arr1_vector : st_arr1_vector :=
c_st_arr1_vector_1 ;
variable v_st_arr2_vector : st_arr2_vector :=
c_st_arr2_vector_1 ;
--
variable correct : boolean := true ;
--
procedure Proc1 (
v_st_rec3_vector : inout st_rec3_vector
; v_st_arr1_vector : inout st_arr1_vector
; v_st_arr2_vector : inout st_arr2_vector
)
is
begin
v_st_rec3_vector(lowb).f3(st_arr2'Left(1),st_arr2'Left(2))
(lowb+1 to highb-1)
:= c_st_rec3_vector_2(lowb).f3(st_arr2'Right(1),st_arr2'Right(2))
(lowb+1 to highb-1) ;
--
v_st_arr1_vector(lowb)(lowb+1 to highb-1)
:= c_st_arr1_vector_2(lowb)(lowb+1 to highb-1) ;
--
v_st_arr2_vector(lowb)(st_arr2'Left(1),st_arr2'Left(2))
(lowb+1 to highb-1)
:= c_st_arr2_vector_2(lowb)(st_arr2'Right(1),st_arr2'Right(2))
(lowb+1 to highb-1) ;
--
--
end Proc1 ;
begin
Proc1 (
v_st_rec3_vector
, v_st_arr1_vector
, v_st_arr2_vector
) ;
correct :=
correct and
v_st_rec3_vector(lowb).f3(st_arr2'Left(1),st_arr2'Left(2))
(lowb+1 to highb-1) =
c_st_rec3_vector_2(lowb).f3(st_arr2'Right(1),st_arr2'Right(2))
(lowb+1 to highb-1) ;
--
correct :=
correct and
v_st_arr1_vector(lowb)(lowb+1 to highb-1) =
c_st_arr1_vector_2(lowb)(lowb+1 to highb-1) ;
--
correct :=
correct and
v_st_arr2_vector(lowb)(st_arr2'Left(1),st_arr2'Left(2))
(lowb+1 to highb-1) =
c_st_arr2_vector_2(lowb)(st_arr2'Right(1),st_arr2'Right(2))
(lowb+1 to highb-1) ;
--
--
test_report ( "ARCH00042.P4" ,
"Target of a variable assignment may be a " &
"slice prefixed by an indexed name" ,
correct) ;
end process P4 ;
--
end ARCH00042 ;
--
entity ENT00042_Test_Bench is
end ENT00042_Test_Bench ;
--
architecture ARCH00042_Test_Bench of ENT00042_Test_Bench is
begin
L1:
block
component UUT
end component ;
for CIS1 : UUT use entity WORK.E00000 ( ARCH00042 ) ;
begin
CIS1 : UUT ;
end block L1 ;
end ARCH00042_Test_Bench ;
| gpl-3.0 | 7c9df03f0de5bfde7796af00fdd3c553 | 0.514161 | 2.830712 | false | false | false | false |
grwlf/vsim | vhdl_ct/ct00570.vhd | 1 | 27,090 | -- NEED RESULT: ARCH00570: Attribute declarations - composite generic subtypes with composite initial values passed
-------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
-------------------------------------------------------------------------------
--
-- TEST NAME:
--
-- CT00570
--
-- AUTHOR:
--
-- A. Wilmot
--
-- TEST OBJECTIVES:
--
-- 4.4 (1)
-- 4.4 (8)
--
-- DESIGN UNIT ORDERING:
--
-- E00000(ARCH00570)
-- ENT00570_Test_Bench(ARCH00570_Test_Bench)
--
-- REVISION HISTORY:
--
-- 19-AUG-1987 - initial revision
--
-- NOTES:
--
-- self-checking
-- automatically generated
--
use WORK.STANDARD_TYPES.test_report ;
--
architecture ARCH00570 of E00000 is
begin
B1 :
block
procedure p2 (
constant lowb : integer := 1 ;
constant highb : integer := 10 ;
constant lowb_i2 : integer := 0 ;
constant highb_i2 : integer := 1000 ;
constant lowb_p : integer := -100 ;
constant highb_p : integer := 1000 ;
constant lowb_r : real := 0.0 ;
constant highb_r : real := 1000.0 ;
constant lowb_r2 : real := 8.0 ;
constant highb_r2 : real := 80.0
--
) is
--
-- assertion: c_xxxxx_2 >= c_xxxxx_1
-- enumeration types
-- predefined
-- boolean
constant c_boolean_1 : boolean := false ;
constant c_boolean_2 : boolean := true ;
--
type boolean_vector is array (integer range <>) of boolean ;
subtype boolean_vector_range1 is integer range lowb to highb ;
subtype st_boolean_vector is boolean_vector (boolean_vector_range1) ;
constant c_st_boolean_vector_1 : st_boolean_vector :=
(others => c_boolean_1) ;
constant c_st_boolean_vector_2 : st_boolean_vector :=
(others => c_boolean_2) ;
--
-- bit
constant c_bit_1 : bit := '0' ;
constant c_bit_2 : bit := '1' ;
--
constant c_bit_vector_1 : bit_vector := B"0000" ;
constant c_bit_vector_2 : bit_vector := B"1111" ;
subtype bit_vector_range1 is integer range lowb to highb ;
subtype st_bit_vector is bit_vector (bit_vector_range1) ;
constant c_st_bit_vector_1 : st_bit_vector :=
(others => c_bit_1) ;
constant c_st_bit_vector_2 : st_bit_vector :=
(others => c_bit_2) ;
-- severity_level
constant c_severity_level_1 : severity_level := NOTE ;
constant c_severity_level_2 : severity_level := WARNING ;
--
type severity_level_vector is array (integer range <>) of severity_level ;
subtype severity_level_vector_range1 is integer range lowb to highb ;
subtype st_severity_level_vector is
severity_level_vector (severity_level_vector_range1) ;
constant c_st_severity_level_vector_1 : st_severity_level_vector :=
(others => c_severity_level_1) ;
constant c_st_severity_level_vector_2 : st_severity_level_vector :=
(others => c_severity_level_2) ;
--
-- character
constant c_character_1 : character := 'A' ;
constant c_character_2 : character := 'a' ;
--
constant c_string_1 : string := "ABC0000" ;
constant c_string_2 : string := "ABC1111" ;
subtype string_range1 is integer range lowb to highb ;
subtype st_string is string (string_range1) ;
constant c_st_string_1 : st_string :=
(others => c_character_1) ;
constant c_st_string_2 : st_string :=
(others => c_character_2) ;
-- user defined enumeration
type t_enum1 is (en1, en2, en3, en4) ;
constant c_t_enum1_1 : t_enum1 := en1 ;
constant c_t_enum1_2 : t_enum1 := en2 ;
subtype st_enum1 is t_enum1 range en4 downto en1 ;
constant c_st_enum1_1 : st_enum1 := en1 ;
constant c_st_enum1_2 : st_enum1 := en2 ;
--
type enum1_vector is array (integer range <>) of st_enum1 ;
subtype enum1_vector_range1 is integer range lowb to highb ;
subtype st_enum1_vector is enum1_vector (enum1_vector_range1) ;
constant c_st_enum1_vector_1 : st_enum1_vector :=
(others => c_st_enum1_1) ;
constant c_st_enum1_vector_2 : st_enum1_vector :=
(others => c_st_enum1_2) ;
-- integer types
-- predefined
constant c_integer_1 : integer := lowb ;
constant c_integer_2 : integer := highb ;
--
type integer_vector is array (integer range <>) of integer ;
subtype integer_vector_range1 is integer range lowb to highb ;
subtype st_integer_vector is integer_vector (integer_vector_range1) ;
constant c_st_integer_vector_1 : st_integer_vector :=
(others => c_integer_1) ;
constant c_st_integer_vector_2 : st_integer_vector :=
(others => c_integer_2) ;
--
-- user defined integer type
type t_int1 is range 0 to 100 ;
constant c_t_int1_1 : t_int1 := 0 ;
constant c_t_int1_2 : t_int1 := 10 ;
subtype st_int1 is t_int1 range 8 to 60 ;
constant c_st_int1_1 : st_int1 := 8 ;
constant c_st_int1_2 : st_int1 := 9 ;
--
type int1_vector is array (integer range <>) of st_int1 ;
subtype int1_vector_range1 is integer range lowb to highb ;
subtype st_int1_vector is int1_vector (int1_vector_range1) ;
constant c_st_int1_vector_1 : st_int1_vector :=
(others => c_st_int1_1) ;
constant c_st_int1_vector_2 : st_int1_vector :=
(others => c_st_int1_2) ;
--
-- physical types
-- predefined
constant c_time_1 : time := 1 ns ;
constant c_time_2 : time := 2 ns ;
--
type time_vector is array (integer range <>) of time ;
subtype time_vector_range1 is integer range lowb to highb ;
subtype st_time_vector is time_vector (time_vector_range1) ;
constant c_st_time_vector_1 : st_time_vector :=
(others => c_time_1) ;
constant c_st_time_vector_2 : st_time_vector :=
(others => c_time_2) ;
--
-- user defined physical type
type t_phys1 is range -100 to 1000
units
phys1_1 ;
phys1_2 = 10 phys1_1 ;
phys1_3 = 10 phys1_2 ;
phys1_4 = 10 phys1_3 ;
phys1_5 = 10 phys1_4 ;
end units ;
--
constant c_t_phys1_1 : t_phys1 := phys1_1 ;
constant c_t_phys1_2 : t_phys1 := phys1_2 ;
subtype st_phys1 is t_phys1 range phys1_2 to phys1_4 ;
constant c_st_phys1_1 : st_phys1 := phys1_2 ;
constant c_st_phys1_2 : st_phys1 := phys1_3 ;
--
type phys1_vector is array (integer range <>) of st_phys1 ;
subtype phys1_vector_range1 is integer range lowb to highb ;
subtype st_phys1_vector is phys1_vector (phys1_vector_range1) ;
constant c_st_phys1_vector_1 : st_phys1_vector :=
(others => c_st_phys1_1) ;
constant c_st_phys1_vector_2 : st_phys1_vector :=
(others => c_st_phys1_2) ;
--
--
-- floating point types
-- predefined
constant c_real_1 : real := 0.0 ;
constant c_real_2 : real := 1.0 ;
--
type real_vector is array (integer range <>) of real ;
subtype real_vector_range1 is integer range lowb to highb ;
subtype st_real_vector is real_vector (real_vector_range1) ;
constant c_st_real_vector_1 : st_real_vector :=
(others => c_real_1) ;
constant c_st_real_vector_2 : st_real_vector :=
(others => c_real_2) ;
--
-- user defined floating type
type t_real1 is range 0.0 to 1000.0 ;
constant c_t_real1_1 : t_real1 := 0.0 ;
constant c_t_real1_2 : t_real1 := 1.0 ;
subtype st_real1 is t_real1 range 8.0 to 80.0 ;
constant c_st_real1_1 : st_real1 := 8.0 ;
constant c_st_real1_2 : st_real1 := 9.0 ;
--
type real1_vector is array (integer range <>) of st_real1 ;
subtype real1_vector_range1 is integer range lowb to highb ;
subtype st_real1_vector is real1_vector (real1_vector_range1) ;
constant c_st_real1_vector_1 : st_real1_vector :=
(others => c_st_real1_1) ;
constant c_st_real1_vector_2 : st_real1_vector :=
(others => c_st_real1_2) ;
-- composite types
--
-- simple record
type t_rec1 is record
f1 : integer range lowb_i2 to highb_i2 ;
f2 : time ;
f3 : boolean ;
f4 : real ;
end record ;
constant c_t_rec1_1 : t_rec1 :=
(c_integer_1, c_time_1, c_boolean_1, c_real_1) ;
constant c_t_rec1_2 : t_rec1 :=
(c_integer_2, c_time_2, c_boolean_2, c_real_2) ;
subtype st_rec1 is t_rec1 ;
constant c_st_rec1_1 : st_rec1 := c_t_rec1_1 ;
constant c_st_rec1_2 : st_rec1 := c_t_rec1_2 ;
--
type rec1_vector is array (integer range <>) of st_rec1 ;
subtype rec1_vector_range1 is integer range lowb to highb ;
subtype st_rec1_vector is rec1_vector (rec1_vector_range1) ;
constant c_st_rec1_vector_1 : st_rec1_vector :=
(others => c_st_rec1_1) ;
constant c_st_rec1_vector_2 : st_rec1_vector :=
(others => c_st_rec1_2) ;
--
--
-- more complex record
type t_rec2 is record
f1 : boolean ;
f2 : st_rec1 ;
f3 : time ;
end record ;
constant c_t_rec2_1 : t_rec2 :=
(c_boolean_1, c_st_rec1_1, c_time_1) ;
constant c_t_rec2_2 : t_rec2 :=
(c_boolean_2, c_st_rec1_2, c_time_2) ;
subtype st_rec2 is t_rec2 ;
constant c_st_rec2_1 : st_rec2 := c_t_rec2_1 ;
constant c_st_rec2_2 : st_rec2 := c_t_rec2_2 ;
--
type rec2_vector is array (integer range <>) of st_rec2 ;
subtype rec2_vector_range1 is integer range lowb to highb ;
subtype st_rec2_vector is rec2_vector (rec2_vector_range1) ;
constant c_st_rec2_vector_1 : st_rec2_vector :=
(others => c_st_rec2_1) ;
constant c_st_rec2_vector_2 : st_rec2_vector :=
(others => c_st_rec2_2) ;
--
-- simple array
type t_arr1 is array (integer range <>) of st_int1 ;
subtype t_arr1_range1 is integer range lowb to highb ;
subtype st_arr1 is t_arr1 (t_arr1_range1) ;
constant c_st_arr1_1 : st_arr1 := (others => c_st_int1_1) ;
constant c_st_arr1_2 : st_arr1 := (others => c_st_int1_2) ;
constant c_t_arr1_1 : st_arr1 := c_st_arr1_1 ;
constant c_t_arr1_2 : st_arr1 := c_st_arr1_2 ;
--
type arr1_vector is array (integer range <>) of st_arr1 ;
subtype arr1_vector_range1 is integer range lowb to highb ;
subtype st_arr1_vector is arr1_vector (arr1_vector_range1) ;
constant c_st_arr1_vector_1 : st_arr1_vector :=
(others => c_st_arr1_1) ;
constant c_st_arr1_vector_2 : st_arr1_vector :=
(others => c_st_arr1_2) ;
-- more complex array
type t_arr2 is array (integer range <>, boolean range <>) of st_arr1 ;
subtype t_arr2_range1 is integer range lowb to highb ;
subtype t_arr2_range2 is boolean range false to true ;
subtype st_arr2 is t_arr2 (t_arr2_range1, t_arr2_range2);
constant c_st_arr2_1 : st_arr2 := (others => (others => c_st_arr1_1)) ;
constant c_st_arr2_2 : st_arr2 := (others => (others => c_st_arr1_2)) ;
constant c_t_arr2_1 : st_arr2 := c_st_arr2_1 ;
constant c_t_arr2_2 : st_arr2 := c_st_arr2_2 ;
--
type arr2_vector is array (integer range <>) of st_arr2 ;
subtype arr2_vector_range1 is integer range lowb to highb ;
subtype st_arr2_vector is arr2_vector (arr2_vector_range1) ;
constant c_st_arr2_vector_1 : st_arr2_vector :=
(others => c_st_arr2_1) ;
constant c_st_arr2_vector_2 : st_arr2_vector :=
(others => c_st_arr2_2) ;
--
--
-- most complex record
type t_rec3 is record
f1 : boolean ;
f2 : st_rec2 ;
f3 : st_arr2 ;
end record ;
constant c_t_rec3_1 : t_rec3 :=
(c_boolean_1, c_st_rec2_1, c_st_arr2_1) ;
constant c_t_rec3_2 : t_rec3 :=
(c_boolean_2, c_st_rec2_2, c_st_arr2_2) ;
subtype st_rec3 is t_rec3 ;
constant c_st_rec3_1 : st_rec3 := c_t_rec3_1 ;
constant c_st_rec3_2 : st_rec3 := c_t_rec3_2 ;
--
type rec3_vector is array (integer range <>) of st_rec3 ;
subtype rec3_vector_range1 is integer range lowb to highb ;
subtype st_rec3_vector is rec3_vector (rec3_vector_range1) ;
constant c_st_rec3_vector_1 : st_rec3_vector :=
(others => c_st_rec3_1) ;
constant c_st_rec3_vector_2 : st_rec3_vector :=
(others => c_st_rec3_2) ;
--
-- most complex array
type t_arr3 is array (integer range <>, boolean range <>) of st_rec3 ;
subtype t_arr3_range1 is integer range lowb to highb ;
subtype t_arr3_range2 is boolean range true downto false ;
subtype st_arr3 is t_arr3 (t_arr3_range1, t_arr3_range2) ;
constant c_st_arr3_1 : st_arr3 := (others => (others => c_st_rec3_1)) ;
constant c_st_arr3_2 : st_arr3 := (others => (others => c_st_rec3_2)) ;
constant c_t_arr3_1 : st_arr3 := c_st_arr3_1 ;
constant c_t_arr3_2 : st_arr3 := c_st_arr3_2 ;
--
type arr3_vector is array (integer range <>) of st_arr3 ;
subtype arr3_vector_range1 is integer range lowb to highb ;
subtype st_arr3_vector is arr3_vector (arr3_vector_range1) ;
constant c_st_arr3_vector_1 : st_arr3_vector :=
(others => c_st_arr3_1) ;
constant c_st_arr3_vector_2 : st_arr3_vector :=
(others => c_st_arr3_2) ;
--
-- enumeration types
-- predefined
-- boolean
function bf_boolean(to_resolve : boolean_vector) return boolean is
variable sum : integer := 0 ;
begin
if to_resolve'length = 0 then
return boolean'left ;
else
for i in to_resolve'range loop
sum := sum + boolean'pos(to_resolve(i)) ;
end loop ;
return boolean'val(integer'pos(sum) mod
(boolean'pos(boolean'high) + 1)) ;
end if ;
end bf_boolean ;
--
--
-- bit
function bf_bit(to_resolve : bit_vector) return bit is
variable sum : integer := 0 ;
begin
if to_resolve'length = 0 then
return bit'left ;
else
for i in to_resolve'range loop
sum := sum + bit'pos(to_resolve(i)) ;
end loop ;
return bit'val(integer'pos(sum) mod
(bit'pos(bit'high) + 1)) ;
end if ;
end bf_bit ;
--
-- severity_level
function bf_severity_level(to_resolve : severity_level_vector)
return severity_level is
variable sum : integer := 0 ;
begin
if to_resolve'length = 0 then
return severity_level'left ;
else
for i in to_resolve'range loop
sum := sum + severity_level'pos(to_resolve(i)) ;
end loop ;
return severity_level'val(integer'pos(sum) mod
(severity_level'pos(severity_level'high) + 1)) ;
end if ;
end bf_severity_level ;
--
-- character
function bf_character(to_resolve : string) return character is
variable sum : integer := 0 ;
begin
if to_resolve'length = 0 then
return character'left ;
else
for i in to_resolve'range loop
sum := sum + character'pos(to_resolve(i)) ;
end loop ;
return character'val(integer'pos(sum) mod
(character'pos(character'high) + 1)) ;
end if ;
end bf_character ;
--
--
-- user defined enumeration
function bf_enum1(to_resolve : enum1_vector) return st_enum1 is
variable sum : integer := 0 ;
begin
if to_resolve'length = 0 then
return st_enum1'left ;
else
for i in to_resolve'range loop
sum := sum + t_enum1'pos(to_resolve(i)) ;
end loop ;
return t_enum1'val(integer'pos(sum) mod
(t_enum1'pos(t_enum1'high) + 1)) ;
end if ;
end bf_enum1 ;
--
--
-- integer types
-- predefined
function bf_integer(to_resolve : integer_vector) return integer is
variable sum : integer := 0 ;
begin
if to_resolve'length = 0 then
return integer'left ;
else
for i in to_resolve'range loop
sum := sum + integer'pos(to_resolve(i)) ;
end loop ;
return sum ;
end if ;
end bf_integer ;
--
--
-- user defined integer type
function bf_int1(to_resolve : int1_vector) return st_int1 is
variable sum : integer := 0 ;
begin
if to_resolve'length = 0 then
return st_int1'left ;
else
for i in to_resolve'range loop
sum := sum + t_int1'pos(to_resolve(i)) ;
end loop ;
return t_int1'val(integer'pos(sum) mod
(t_int1'pos(t_int1'high) + 1)) ;
end if ;
end bf_int1 ;
--
--
-- physical types
-- predefined
function bf_time(to_resolve : time_vector) return time is
variable sum : time := 0 fs;
begin
if to_resolve'length = 0 then
return time'left ;
else
for i in to_resolve'range loop
sum := sum + to_resolve(i) ;
end loop ;
return sum ;
end if ;
end bf_time ;
--
--
-- user defined physical type
function bf_phys1(to_resolve : phys1_vector) return st_phys1 is
variable sum : integer := 0 ;
begin
if to_resolve'length = 0 then
return c_st_phys1_1 ;
else
for i in to_resolve'range loop
sum := sum + t_phys1'pos(to_resolve(i)) ;
end loop ;
return t_phys1'val(integer'pos(sum) mod
(t_phys1'pos(t_phys1'high) + 1)) ;
end if ;
end bf_phys1 ;
--
--
-- floating point types
-- predefined
function bf_real(to_resolve : real_vector) return real is
variable sum : real := 0.0 ;
begin
if to_resolve'length = 0 then
return real'left ;
else
for i in to_resolve'range loop
sum := sum + to_resolve(i) ;
end loop ;
return sum ;
end if ;
end bf_real ;
--
--
-- user defined floating type
function bf_real1(to_resolve : real1_vector) return st_real1 is
variable sum : t_real1 := 0.0 ;
begin
if to_resolve'length = 0 then
return c_st_real1_1 ;
else
for i in to_resolve'range loop
sum := sum + to_resolve(i) ;
end loop ;
return sum ;
end if ;
end bf_real1 ;
--
--
-- composite types
--
-- simple record
function bf_rec1(to_resolve : rec1_vector) return st_rec1 is
variable f1array : integer_vector (to_resolve'range) ;
variable f2array : time_vector (to_resolve'range) ;
variable f3array : boolean_vector (to_resolve'range) ;
variable f4array : real_vector (to_resolve'range) ;
variable result : st_rec1 ;
begin
if to_resolve'length = 0 then
return c_st_rec1_1 ;
else
for i in to_resolve'range loop
f1array(i) := to_resolve(i).f1 ;
f2array(i) := to_resolve(i).f2 ;
f3array(i) := to_resolve(i).f3 ;
f4array(i) := to_resolve(i).f4 ;
end loop ;
result.f1 := bf_integer(f1array) ;
result.f2 := bf_time(f2array) ;
result.f3 := bf_boolean(f3array) ;
result.f4 := bf_real(f4array) ;
return result ;
end if ;
end bf_rec1 ;
--
--
-- more complex record
function bf_rec2(to_resolve : rec2_vector) return st_rec2 is
variable f1array : boolean_vector (to_resolve'range) ;
variable f2array : rec1_vector (to_resolve'range) ;
variable f3array : time_vector (to_resolve'range) ;
variable result : st_rec2 ;
begin
if to_resolve'length = 0 then
return c_st_rec2_1 ;
else
for i in to_resolve'range loop
f1array(i) := to_resolve(i).f1 ;
f2array(i) := to_resolve(i).f2 ;
f3array(i) := to_resolve(i).f3 ;
end loop ;
result.f1 := bf_boolean(f1array) ;
result.f2 := bf_rec1(f2array) ;
result.f3 := bf_time(f3array) ;
return result ;
end if ;
end bf_rec2 ;
--
--
-- simple array
function bf_arr1(to_resolve : arr1_vector) return st_arr1 is
variable temp : int1_vector (to_resolve'range) ;
variable result : st_arr1 ;
begin
if to_resolve'length = 0 then
return c_st_arr1_1 ;
else
for i in st_arr1'range loop
for j in to_resolve'range(1) loop
temp(j) := to_resolve(j)(i) ;
end loop;
result(i) := bf_int1(temp) ;
end loop ;
return result ;
end if ;
end bf_arr1 ;
--
--
-- more complex array
function bf_arr2(to_resolve : arr2_vector) return st_arr2 is
variable temp : arr1_vector (to_resolve'range) ;
variable result : st_arr2 ;
begin
if to_resolve'length = 0 then
return c_st_arr2_1 ;
else
for i in st_arr2'range(1) loop
for j in st_arr2'range(2) loop
for k in to_resolve'range loop
temp(k) := to_resolve(k)(i,j) ;
end loop ;
result(i, j) := bf_arr1(temp) ;
end loop ;
end loop ;
return result ;
end if ;
end bf_arr2 ;
--
--
-- most complex record
function bf_rec3(to_resolve : rec3_vector) return st_rec3 is
variable f1array : boolean_vector (to_resolve'range) ;
variable f2array : rec2_vector (to_resolve'range) ;
variable f3array : arr2_vector (to_resolve'range) ;
variable result : st_rec3 ;
begin
if to_resolve'length = 0 then
return c_st_rec3_1 ;
else
for i in to_resolve'range loop
f1array(i) := to_resolve(i).f1 ;
f2array(i) := to_resolve(i).f2 ;
f3array(i) := to_resolve(i).f3 ;
end loop ;
result.f1 := bf_boolean(f1array) ;
result.f2 := bf_rec2(f2array) ;
result.f3 := bf_arr2(f3array) ;
return result ;
end if ;
end bf_rec3 ;
--
--
-- most complex array
function bf_arr3(to_resolve : arr3_vector) return st_arr3 is
variable temp : rec3_vector (to_resolve'range) ;
variable result : st_arr3 ;
begin
if to_resolve'length = 0 then
return c_st_arr3_1 ;
else
for i in st_arr3'range(1) loop
for j in st_arr3'range(2) loop
for k in to_resolve'range loop
temp(k) := to_resolve(k)(i,j) ;
end loop ;
result(i, j) := bf_rec3(temp) ;
end loop ;
end loop ;
return result ;
end if ;
end bf_arr3 ;
--
attribute at_bit_vector_1 : bit_vector ;
attribute at_string_1 : string ;
attribute at_t_rec1_1 : t_rec1 ;
attribute at_st_rec1_1 : st_rec1 ;
attribute at_t_rec2_1 : t_rec2 ;
attribute at_st_rec2_1 : st_rec2 ;
attribute at_t_rec3_1 : t_rec3 ;
attribute at_st_rec3_1 : st_rec3 ;
attribute at_t_arr1_1 : t_arr1 ;
attribute at_st_arr1_1 : st_arr1 ;
attribute at_t_arr2_1 : t_arr2 ;
attribute at_st_arr2_1 : st_arr2 ;
attribute at_t_arr3_1 : t_arr3 ;
attribute at_st_arr3_1 : st_arr3 ;
procedure p1 ;
attribute at_bit_vector_1 of p1 : procedure is
c_st_bit_vector_1 ;
attribute at_string_1 of p1 : procedure is
c_st_string_1 ;
attribute at_t_rec1_1 of p1 : procedure is
c_st_rec1_1 ;
attribute at_st_rec1_1 of p1 : procedure is
c_st_rec1_1 ;
attribute at_t_rec2_1 of p1 : procedure is
c_st_rec2_1 ;
attribute at_st_rec2_1 of p1 : procedure is
c_st_rec2_1 ;
attribute at_t_rec3_1 of p1 : procedure is
c_st_rec3_1 ;
attribute at_st_rec3_1 of p1 : procedure is
c_st_rec3_1 ;
attribute at_t_arr1_1 of p1 : procedure is
c_st_arr1_1 ;
attribute at_st_arr1_1 of p1 : procedure is
c_st_arr1_1 ;
attribute at_t_arr2_1 of p1 : procedure is
c_st_arr2_1 ;
attribute at_st_arr2_1 of p1 : procedure is
c_st_arr2_1 ;
attribute at_t_arr3_1 of p1 : procedure is
c_st_arr3_1 ;
attribute at_st_arr3_1 of p1 : procedure is
c_st_arr3_1 ;
procedure p1 is
variable correct : boolean := true ;
begin
correct := correct and p1'at_bit_vector_1
= c_st_bit_vector_1 ;
correct := correct and p1'at_string_1
= c_st_string_1 ;
correct := correct and p1'at_t_rec1_1
= c_st_rec1_1 ;
correct := correct and p1'at_st_rec1_1
= c_st_rec1_1 ;
correct := correct and p1'at_t_rec2_1
= c_st_rec2_1 ;
correct := correct and p1'at_st_rec2_1
= c_st_rec2_1 ;
correct := correct and p1'at_t_rec3_1
= c_st_rec3_1 ;
correct := correct and p1'at_st_rec3_1
= c_st_rec3_1 ;
correct := correct and p1'at_t_arr1_1
= c_st_arr1_1 ;
correct := correct and p1'at_st_arr1_1
= c_st_arr1_1 ;
correct := correct and p1'at_t_arr2_1
= c_st_arr2_1 ;
correct := correct and p1'at_st_arr2_1
= c_st_arr2_1 ;
correct := correct and p1'at_t_arr3_1
= c_st_arr3_1 ;
correct := correct and p1'at_st_arr3_1
= c_st_arr3_1 ;
test_report ( "ARCH00570" ,
"Attribute declarations - composite generic subtypes"
& " with composite initial values" ,
correct) ;
end p1 ;
begin
p1 ;
end p2 ;
begin
process
begin
p2 ;
wait ;
end process ;
end block B1 ;
end ARCH00570 ;
--
entity ENT00570_Test_Bench is
end ENT00570_Test_Bench ;
--
architecture ARCH00570_Test_Bench of ENT00570_Test_Bench is
begin
L1:
block
component UUT
end component ;
for CIS1 : UUT use entity WORK.E00000 ( ARCH00570 ) ;
begin
CIS1 : UUT ;
end block L1 ;
end ARCH00570_Test_Bench ;
| gpl-3.0 | d5e34c349f19ef74218a032eb0cdc33b | 0.540162 | 3.232697 | false | false | false | false |
grwlf/vsim | vhdl_ct/ct00411.vhd | 1 | 8,126 | -- NEED RESULT: ARCH00411.P1: Multi inertial transactions occurred on concurrent signal asg passed
-- NEED RESULT: ARCH00411: One inertial transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00411: Old transactions were removed on a concurrent signal asg passed
-- NEED RESULT: ARCH00411: One inertial transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00411: Inertial semantics check on a concurrent signal asg passed
-- NEED RESULT: P1: Inertial transactions completed entirely passed
-------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
-------------------------------------------------------------------------------
--
-- TEST NAME:
--
-- CT00411
--
-- AUTHOR:
--
-- G. Tominovich
--
-- TEST OBJECTIVES:
--
-- 9.5 (3)
-- 9.5.2 (1)
--
-- DESIGN UNIT ORDERING:
--
-- ENT00411(ARCH00411)
-- ENT00411_Test_Bench(ARCH00411_Test_Bench)
--
-- REVISION HISTORY:
--
-- 30-JUL-1987 - initial revision
--
-- NOTES:
--
-- self-checking
-- automatically generated
--
use WORK.STANDARD_TYPES.all ;
entity ENT00411 is
port (
s_st_rec3 : inout st_rec3
) ;
subtype chk_sig_type is integer range -1 to 100 ;
signal chk_st_rec3 : chk_sig_type := -1 ;
--
end ENT00411 ;
--
--
architecture ARCH00411 of ENT00411 is
subtype chk_time_type is Time ;
signal s_st_rec3_savt : chk_time_type := 0 ns ;
--
subtype chk_cnt_type is Integer ;
signal s_st_rec3_cnt : chk_cnt_type := 0 ;
--
type select_type is range 1 to 6 ;
signal st_rec3_select : select_type := 1 ;
--
begin
CHG1 :
process
variable correct : boolean ;
begin
case s_st_rec3_cnt is
when 0
=> null ;
-- s_st_rec3.f3(lowb,true) <=
-- c_st_rec3_2.f3(lowb,true) after 10 ns,
-- c_st_rec3_1.f3(lowb,true) after 20 ns ;
--
when 1
=> correct :=
s_st_rec3.f3(lowb,true) =
c_st_rec3_2.f3(lowb,true) and
(s_st_rec3_savt + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_rec3.f3(lowb,true) =
c_st_rec3_1.f3(lowb,true) and
(s_st_rec3_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00411.P1" ,
"Multi inertial transactions occurred on " &
"concurrent signal asg",
correct ) ;
--
st_rec3_select <= transport 2 ;
-- s_st_rec3.f3(lowb,true) <=
-- c_st_rec3_2.f3(lowb,true) after 10 ns ,
-- c_st_rec3_1.f3(lowb,true) after 20 ns ,
-- c_st_rec3_2.f3(lowb,true) after 30 ns ,
-- c_st_rec3_1.f3(lowb,true) after 40 ns ;
--
when 3
=> correct :=
s_st_rec3.f3(lowb,true) =
c_st_rec3_2.f3(lowb,true) and
(s_st_rec3_savt + 10 ns) = Std.Standard.Now ;
st_rec3_select <= transport 3 ;
-- s_st_rec3.f3(lowb,true) <=
-- c_st_rec3_1.f3(lowb,true) after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_rec3.f3(lowb,true) =
c_st_rec3_1.f3(lowb,true) and
(s_st_rec3_savt + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00411" ,
"One inertial transaction occurred on a " &
"concurrent signal asg",
correct ) ;
st_rec3_select <= transport 4 ;
-- s_st_rec3.f3(lowb,true) <=
-- c_st_rec3_1.f3(lowb,true) after 100 ns ;
--
when 5
=> correct :=
correct and
s_st_rec3.f3(lowb,true) =
c_st_rec3_1.f3(lowb,true) and
(s_st_rec3_savt + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00411" ,
"Old transactions were removed on a " &
"concurrent signal asg",
correct ) ;
st_rec3_select <= transport 5 ;
-- s_st_rec3.f3(lowb,true) <=
-- c_st_rec3_2.f3(lowb,true) after 10 ns ,
-- c_st_rec3_1.f3(lowb,true) after 20 ns ,
-- c_st_rec3_2.f3(lowb,true) after 30 ns ,
-- c_st_rec3_1.f3(lowb,true) after 40 ns ;
--
when 6
=> correct :=
correct and
s_st_rec3.f3(lowb,true) =
c_st_rec3_2.f3(lowb,true) and
(s_st_rec3_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00411" ,
"One inertial transaction occurred on a " &
"concurrent signal asg",
correct ) ;
st_rec3_select <= transport 6 ;
-- Last transaction above is marked
-- s_st_rec3.f3(lowb,true) <=
-- c_st_rec3_1.f3(lowb,true) after 40 ns ;
--
when 7
=> correct :=
correct and
s_st_rec3.f3(lowb,true) =
c_st_rec3_1.f3(lowb,true) and
(s_st_rec3_savt + 30 ns) = Std.Standard.Now ;
--
when 8
=> correct :=
correct and
s_st_rec3.f3(lowb,true) =
c_st_rec3_1.f3(lowb,true) and
(s_st_rec3_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00411" ,
"Inertial semantics check on a concurrent " &
"signal asg",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00411" ,
"Inertial semantics check on a concurrent " &
"signal asg",
false ) ;
--
end case ;
--
s_st_rec3_savt <= transport Std.Standard.Now ;
chk_st_rec3 <= transport s_st_rec3_cnt
after (1 us - Std.Standard.Now) ;
s_st_rec3_cnt <= transport s_st_rec3_cnt + 1 ;
wait until (not s_st_rec3.f3(lowb,true)'Quiet) and
(s_st_rec3_savt /= Std.Standard.Now) ;
--
end process CHG1 ;
--
PGEN_CHKP_1 :
process ( chk_st_rec3 )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P1" ,
"Inertial transactions completed entirely",
chk_st_rec3 = 8 ) ;
end if ;
end process PGEN_CHKP_1 ;
--
--
with st_rec3_select select
s_st_rec3.f3(lowb,true) <=
c_st_rec3_2.f3(lowb,true) after 10 ns,
c_st_rec3_1.f3(lowb,true) after 20 ns
when 1,
--
c_st_rec3_2.f3(lowb,true) after 10 ns ,
c_st_rec3_1.f3(lowb,true) after 20 ns ,
c_st_rec3_2.f3(lowb,true) after 30 ns ,
c_st_rec3_1.f3(lowb,true) after 40 ns
when 2,
--
c_st_rec3_1.f3(lowb,true) after 5 ns
when 3,
--
c_st_rec3_1.f3(lowb,true) after 100 ns
when 4,
--
c_st_rec3_2.f3(lowb,true) after 10 ns ,
c_st_rec3_1.f3(lowb,true) after 20 ns ,
c_st_rec3_2.f3(lowb,true) after 30 ns ,
c_st_rec3_1.f3(lowb,true) after 40 ns
when 5,
--
-- Last transaction above is marked
c_st_rec3_1.f3(lowb,true) after 40 ns when 6 ;
--
end ARCH00411 ;
--
--
use WORK.STANDARD_TYPES.all ;
entity ENT00411_Test_Bench is
signal s_st_rec3 : st_rec3
:= c_st_rec3_1 ;
--
end ENT00411_Test_Bench ;
--
--
architecture ARCH00411_Test_Bench of ENT00411_Test_Bench is
begin
L1:
block
component UUT
port (
s_st_rec3 : inout st_rec3
) ;
end component ;
--
for CIS1 : UUT use entity WORK.ENT00411 ( ARCH00411 ) ;
begin
CIS1 : UUT
port map (
s_st_rec3
)
;
end block L1 ;
end ARCH00411_Test_Bench ;
| gpl-3.0 | a74c8c7396e3ad711a50ccc719573e6a | 0.48634 | 3.189168 | false | true | false | false |
dcliche/mdsynth | rtl/src/vdu8.vhd | 1 | 23,325 | --===========================================================================--
-- --
-- vdu8.vhd - Synthesizable Colour Video Display Unit for System09 --
-- --
--===========================================================================--
--
-- File name : vdu8.vhd
--
-- Purpose : Implements a text based Colour Video Display Unit for System09
-- Supports 2KByte Text buffer and 2KByte Attribute memory
-- Displays 80 characters across by 25 character rows
-- Characters are 8 pixels across x 16 lines down.
-- Character attribute bita for foreground and backgrond colour
-- 1 bit for each Blue Green and Red signal
-- Supports 2 x 8 chunky graphics character mode.
-- Uses Generic arguments for setting the video synchronization timing.
--
-- Dependencies : ieee.std_logic_1164
-- ieee.numeric_std
--
-- Uses : ram_2k (ram2k_b16.vhd) 2KByte Character & Attribute buffer
-- char_rom (char_rom2k_b16.vhd) 2KByte Character Generator ROM
--
-- Author : John E. Kent
--
-- Email : [email protected]
--
-- Web : http://opencores.org/project,system09
--
-- Description : Display Timing:
-- 800 pixels / line
-- 446 lines / frame
-- None interlaced
-- 25MHz pixel clock implies
-- 31.25 KHz line rate
-- 70.067 Hz frame rate
-- Timing settable by generics.
--
-- Display Size:
-- 80 characters across
-- 25 characters down.
--
-- Character Size:
-- 8 horizontal pixels across
-- 16 vertical scan lines down (2 scan lines/row)
--
-- Registers:
-- Base + 0 ASCII character register
-- Writing to this register writes an 8 bit byte
-- into the text buffer at the specified cursor position
-- Text Mode: ASCII Character (0 to 127)
-- Chunky Graphics Mode: B0 B1 (0 to 255)
-- B2 B3
-- B4 B5
-- B6 B7
-- Base + 1 Attibute bit (0 to 255)
-- Writing to the register writes an 8 bit byte
-- into the attribute buffer at the specified cursor position
-- B7 - 0 => Text Mode / 1 => Chunky Graphics Mode
-- B6 - 1 => Character Background Blue
-- B5 - 1 => Character Background Green
-- B4 - 1 => Character Background Red
-- B3 - 1 => Character Background & Foreground Alternates
-- B2 - 1 => Character Foreground Blue
-- B1 - 1 => Character Foreground Green
-- B0 - 1 => Character Foreground Red
-- Base + 2 Cursor Horizontal Position (0 to 79)
-- Base + 3 Cusror Vertical Position (0 to 24)
-- Base + 4 Vertical Scroll Offset (0 to 24)
-- Scrolls the display up by the specified number of character rows
-- Base + 5 Cursor Attribute
-- B7 downto B1 - N/A
-- B0 - 0 => Invisible / 1 => Visible
--
-- Video Timing :
--
-- Horizontal 800 Pixels/ 25MHz Pixel Clock = 32usec Line period = 31.25 KHz Line Frequency
-- /--------------------------\_____________/---------------\______________/
-- 640 Pixels Display 16 Pixel FP 96 Pixel HS 48 Pixel BP
--
-- VGA_CLK_FREQ : integer := 25000000; -- HZ
-- VGA_HOR_FRONT_PORCH : integer := 16; -- PIXELS 0.64us (0.94us)
-- VGA_HOR_SYNC : integer := 96; -- PIXELS 3.84us (3.77us)
-- VGA_HOR_BACK_PORCH : integer := 48; -- PIXELS 1.92us (1.89us)
-- VGA_PIX_PER_CHAR : integer := 8; -- PIXELS 0.32us
-- VGA_HOR_CHARS : integer := 80; -- CHARACTERS 25.6us
--
-- Vertical 446 Lines * 32 usec Line rate = 14.272ms Frame Period = 70.07Hz Frame frequency
-- /---------------------------\____________/---------------\______________/
-- 400 Line Display 10 Line FP 2 Line VS 34 Line BP
--
-- VGA_VER_FRONT_PORCH : integer := 10; -- LINES 0.320ms
-- VGA_VER_SYNC : integer := 2; -- LINES 0.064ms
-- VGA_VER_BACK_PORCH : integer := 34; -- LINES 1.088ms
-- VGA_LIN_PER_CHAR : integer := 16; -- LINES 0.512ms
-- VGA_VER_CHARS : integer := 25; -- CHARACTERS 12.8ms
--
-- Copyright (C) 2003 - 2010 John Kent
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
--===========================================================================--
-- --
-- Revision History --
-- --
--===========================================================================--
--
-- Version Author Date Changes
--
-- 0.1 John Kent 2004-09-03 Initial release
--
-- 0.2 Bert Cuzeau 2007-01-16 Modified by for compliance and code cleanliness
-- The effort is not over.
-- There are still signal initialized, which is BAD.
--
-- 0.3 John Kent 2007-02-07 Added generics for VGA Timing
--
-- 0.4 John Kent 2010-07-03 Added GPL notice.
-- Updated description.
-- Rearranged Video Timing
--
Library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
--Library unisim;
-- use unisim.vcomponents.all;
Entity vdu8 is
generic(
VGA_CLK_FREQ : integer := 25000000; -- HZ
VGA_HOR_CHARS : integer := 80; -- CHARACTERS 25.6us
VGA_HOR_CHAR_PIXELS : integer := 8; -- PIXELS 0.32us
VGA_HOR_FRONT_PORCH : integer := 16; -- PIXELS 0.64us
VGA_HOR_SYNC : integer := 96; -- PIXELS 3.84us
VGA_HOR_BACK_PORCH : integer := 48; -- PIXELS 1.92us
VGA_VER_CHARS : integer := 25; -- CHARACTERS 12.8ms
VGA_VER_CHAR_LINES : integer := 16; -- LINES 0.512ms
VGA_VER_FRONT_PORCH : integer := 10; -- LINES 0.320ms
VGA_VER_SYNC : integer := 2; -- LINES 0.064ms
VGA_VER_BACK_PORCH : integer := 34 -- LINES 1.088ms
);
port(
-- control register interface
vdu_clk : in std_logic; -- 12.5/25 MHz CPU Clock
vdu_rst : in std_logic;
vdu_cs : in std_logic;
vdu_rw : in std_logic;
vdu_addr : in std_logic_vector(2 downto 0);
vdu_data_in : in std_logic_vector(7 downto 0);
vdu_data_out : out std_logic_vector(7 downto 0);
-- vga port connections
vga_clk : in std_logic; -- 25MHz clock
vga_red_o : out std_logic;
vga_green_o : out std_logic;
vga_blue_o : out std_logic;
vga_hsync_o : out std_logic;
vga_vsync_o : out std_logic
);
end vdu8;
Architecture RTL of vdu8 is
--
-- Synchronisation constants
--
-- Displayed Characters per row
constant HOR_DISP_CHR : integer := VGA_HOR_CHARS;
-- Last horizontal pixel displayed
constant HOR_DISP_END : integer := (HOR_DISP_CHR * VGA_HOR_CHAR_PIXELS) - 1;
-- Start of horizontal synch pulse
constant HOR_SYNC_BEG : integer := HOR_DISP_END + VGA_HOR_FRONT_PORCH;
-- End of Horizontal Synch pulse
constant HOR_SYNC_END : integer := HOR_SYNC_BEG + VGA_HOR_SYNC;
-- Last pixel in scan line
constant HOR_SCAN_END : integer := HOR_SYNC_END + VGA_HOR_BACK_PORCH;
-- Displayed Characters per Column
constant VER_DISP_CHR : integer := VGA_VER_CHARS;
-- last row displayed
constant VER_DISP_END : integer := (VER_DISP_CHR * VGA_VER_CHAR_LINES) - 1;
-- start of vertical synch pulse
constant VER_SYNC_BEG : integer := VER_DISP_END + VGA_VER_FRONT_PORCH;
-- end of vertical synch pulse
constant VER_SYNC_END : integer := VER_SYNC_BEG + VGA_VER_SYNC;
-- Last scan row in the frame
constant VER_SCAN_END : integer := VER_SYNC_END + VGA_VER_BACK_PORCH;
signal horiz_sync : std_logic := '1';
signal vert_sync : std_logic := '1';
signal cursor_on_v : std_logic;
signal cursor_on_h : std_logic;
signal video_on_v : std_logic := '0';
signal video_on_h : std_logic := '0';
signal h_count : std_logic_vector(9 downto 0) := (others=>'0');
signal v_count : std_logic_vector(8 downto 0) := (others=>'0'); -- 0 to VER_SCAN_END
signal blink_count : std_logic_vector(22 downto 0):= (others=>'1');
--
-- Character generator ROM
--
signal char_addr : std_logic_vector(10 downto 0);
signal char_data_out : std_logic_vector(7 downto 0);
--
-- Control Registers
--
signal reg_character : std_logic_vector(7 downto 0);
signal reg_colour : std_logic_vector(7 downto 0);
signal reg_hcursor : std_logic_vector(6 downto 0); -- 80 columns
signal reg_vcursor : std_logic_vector(4 downto 0); -- 25 rows
signal reg_voffset : std_logic_vector(4 downto 0); -- 25 rows
signal reg_cursor_visible: std_logic;
--
-- Video Shift register
--
signal vga_shift : std_logic_vector(7 downto 0);
signal vga_fg_colour : std_logic_vector(2 downto 0);
signal vga_bg_colour : std_logic_vector(2 downto 0);
signal cursor_on : std_logic;
signal cursor_on1 : std_logic;
signal video_on : std_logic := '0';
signal video_on1 : std_logic := '0';
signal video_on2 : std_logic := '0';
--
-- vga character ram access bus
--
signal col_addr : std_logic_vector(6 downto 0) := (others=>'0'); -- 0 to 79
signal row_addr : unsigned(5 downto 0) := (others=>'0'); -- 0 to 49 (25 * 2 -1)
signal col1_addr : std_logic_vector(6 downto 0) := (others=>'0'); -- 0 to 79
signal row1_addr : unsigned(5 downto 0) := (others=>'0'); -- 0 to 49 (25 * 2 - 1)
signal hor_addr : std_logic_vector(6 downto 0) := (others=>'0'); -- 0 to 79
signal ver_addr : std_logic_vector(6 downto 0) := (others=>'0'); -- 0 to 124
signal vga0_cs : std_logic;
signal vga0_rw : std_logic;
signal vga1_cs : std_logic;
signal vga1_rw : std_logic;
signal vga2_cs : std_logic;
signal vga2_rw : std_logic;
signal vga_cs : std_logic;
signal vga_rw : std_logic;
signal vga_addr : std_logic_vector(10 downto 0) := (others=>'0'); -- 2K byte character buffer
signal vga_data_out : std_logic_vector(7 downto 0);
signal attr_data_out : std_logic_vector(7 downto 0);
--
-- Character write handshake signals
--
signal req_write : std_logic; -- request character write
signal ack_write : std_logic;
--
-- Block Ram Character gen
--
component char_rom
port (
clk : in std_logic;
rst : in std_logic;
cs : in std_logic;
rw : in std_logic;
addr : in std_logic_vector (10 downto 0);
data_in : in std_logic_vector (7 downto 0);
data_out : out std_logic_vector (7 downto 0)
);
end component;
component ram_2k
port (
clk : in std_logic;
rst : in std_logic;
cs : in std_logic;
rw : in std_logic;
addr : in std_logic_vector (10 downto 0);
data_in : in std_logic_vector (7 downto 0);
data_out : out std_logic_vector (7 downto 0)
);
end component;
begin
--
-- instantiate Character generator ROM
--
vdu_char_rom : char_rom port map(
clk => vga_clk,
rst => vdu_rst,
cs => '1',
rw => '1',
addr => char_addr,
data_in => "00000000",
data_out => char_data_out
);
--
-- Character buffer RAM
--
char_buff_ram : ram_2k port map(
clk => vga_clk,
rst => vdu_rst,
cs => vga_cs,
rw => vga_rw,
addr => vga_addr,
data_in => reg_character,
data_out => vga_data_out
);
--
-- Attribute buffer RAM
--
attr_buff_ram : ram_2k port map(
clk => vga_clk,
rst => vdu_rst,
cs => vga_cs,
rw => vga_rw,
addr => vga_addr,
data_in => reg_colour,
data_out => attr_data_out
);
--
-- CPU Write interface
--
vga_cpu_write : process(vdu_clk, vdu_rst)
begin
if vdu_rst = '1' then
reg_character <= "00000000";
reg_colour <= "00000111";
reg_cursor_visible <= '1';
reg_hcursor <= "0000000";
reg_vcursor <= "00000";
reg_voffset <= "00000";
req_write <= '0';
elsif vdu_clk'event and vdu_clk = '0' then
if (vdu_cs = '1') and (vdu_rw = '0') then
case vdu_addr is
when "000" =>
reg_character <= vdu_data_in;
req_write <= '1';
when "001" =>
reg_colour <= vdu_data_in;
when "010" =>
reg_hcursor <= vdu_data_in(6 downto 0);
when "011" =>
reg_vcursor <= vdu_data_in(4 downto 0);
when "100" =>
reg_voffset <= vdu_data_in(4 downto 0);
when others =>
reg_cursor_visible <= vdu_data_in(0);
end case;
else
if (req_write = '1') and (ack_write = '1') then
req_write <= '0';
else
req_write <= req_write;
end if;
end if;
end if;
end process;
--
-- CPU Read interface
--
vga_cpu_read : process(vdu_addr, vdu_cs,
reg_character, reg_colour,
reg_hcursor, reg_vcursor, reg_voffset)
begin
case vdu_addr is
when "000" =>
vdu_data_out <= reg_character;
when "001" =>
vdu_data_out <= reg_colour;
when "010" =>
vdu_data_out <= "0" & reg_hcursor;
when "011" =>
vdu_data_out <= "000" & reg_vcursor;
when "100" =>
vdu_data_out <= "000" & reg_voffset;
when others =>
vdu_data_out <= "0000000" & reg_cursor_visible;
end case;
end process;
--
-- Video memory access
--
vga_addr_proc : process(vga_clk, vdu_rst)
begin
if vdu_rst = '1' then
vga0_cs <= '0';
vga0_rw <= '1';
row_addr <= "000000";
col_addr <= "0000000";
--
vga1_cs <= '0';
vga1_rw <= '1';
row1_addr <= "000000";
col1_addr <= "0000000";
--
vga2_cs <= '0';
vga2_rw <= '1';
ver_addr <= "0000000";
hor_addr <= "0000000";
--
vga_cs <= '0';
vga_rw <= '1';
vga_addr <= "00000000000";
elsif vga_clk'event and vga_clk = '0' then
--
-- on h_count = 0 initiate character write.
-- all other cycles are reads.
--
case h_count(2 downto 0) is
when "000" => -- pipeline character write
vga0_cs <= req_write;
vga0_rw <= '0';
col_addr <= reg_hcursor(6 downto 0);
row_addr <= unsigned("0" & reg_vcursor(4 downto 0)) + unsigned("0" & reg_voffset(4 downto 0));
when others => -- other 6 cycles free
vga0_cs <= '1';
vga0_rw <= '1';
col_addr <= h_count(9 downto 3);
row_addr <= unsigned("0" & v_count(8 downto 4)) + unsigned("0" & reg_voffset(4 downto 0));
end case;
--
-- on vga_clk + 1 round off row address
--
vga1_cs <= vga0_cs;
vga1_rw <= vga0_rw;
if row_addr < VER_DISP_CHR then
row1_addr <= row_addr;
else
row1_addr <= row_addr - VER_DISP_CHR;
end if;
col1_addr <= col_addr;
--
-- on vga_clk + 2 calculate vertical address
--
vga2_cs <= vga1_cs;
vga2_rw <= vga1_rw;
ver_addr <= std_logic_vector(unsigned("00" & row1_addr(4 downto 0)) + unsigned(row1_addr(4 downto 0) & "00"));
hor_addr <= col1_addr;
--
-- on vga_clk + 3 calculate memory address
--
vga_cs <= vga2_cs;
vga_rw <= vga2_rw;
vga_addr <= std_logic_vector(unsigned("0000" & hor_addr) + unsigned(ver_addr & "0000"));
end if;
end process;
--
-- Video shift register
--
vga_shift_proc : process( vga_clk, vdu_rst)
begin
if vdu_rst = '1' then
ack_write <= '0';
video_on2 <= '0';
video_on <= '0';
cursor_on <= '0';
vga_bg_colour <= "000";
vga_fg_colour <= "111";
vga_shift <= "00000000";
vga_red_o <= '0';
vga_green_o <= '0';
vga_blue_o <= '0';
-- Put all video signals through DFFs to elminate any delays that cause a blurry image
elsif vga_clk'event and vga_clk = '0' then
-- Character Data valid on 1 count
if h_count(2 downto 0) = "000" then
if (req_write = '1') and (ack_write = '0') then
ack_write <= '1';
elsif (req_write = '0') and (ack_write = '1') then
ack_write <= '0';
else
ack_write <= ack_write;
end if;
video_on2 <= video_on1;
video_on <= video_on2;
cursor_on <= (cursor_on1 or attr_data_out(3)) and blink_count(22) and reg_cursor_visible;
vga_fg_colour <= attr_data_out(2 downto 0);
vga_bg_colour <= attr_data_out(6 downto 4);
if attr_data_out(7) = '0' then
vga_shift <= char_data_out;
else
case v_count(3 downto 2) is
when "00" =>
vga_shift(7 downto 4) <= vga_data_out(0) & vga_data_out(0) & vga_data_out(0) & vga_data_out(0);
vga_shift(3 downto 0) <= vga_data_out(1) & vga_data_out(1) & vga_data_out(1) & vga_data_out(1);
when "01" =>
vga_shift(7 downto 4) <= vga_data_out(2) & vga_data_out(2) & vga_data_out(2) & vga_data_out(2);
vga_shift(3 downto 0) <= vga_data_out(3) & vga_data_out(3) & vga_data_out(3) & vga_data_out(3);
when "10" =>
vga_shift(7 downto 4) <= vga_data_out(4) & vga_data_out(4) & vga_data_out(4) & vga_data_out(4);
vga_shift(3 downto 0) <= vga_data_out(5) & vga_data_out(5) & vga_data_out(5) & vga_data_out(5);
when others =>
vga_shift(7 downto 4) <= vga_data_out(6) & vga_data_out(6) & vga_data_out(6) & vga_data_out(6);
vga_shift(3 downto 0) <= vga_data_out(7) & vga_data_out(7) & vga_data_out(7) & vga_data_out(7);
end case;
end if;
else
vga_shift <= vga_shift(6 downto 0) & '0';
end if;
--
-- Colour mask is
-- 7 6 5 4 3 2 1 0
-- X BG BB BR X FG FB FR
--
if vga_shift(7) = (not cursor_on) then
vga_red_o <= video_on and vga_fg_colour(0);
vga_green_o <= video_on and vga_fg_colour(1);
vga_blue_o <= video_on and vga_fg_colour(2);
else
vga_red_o <= video_on and vga_bg_colour(0);
vga_green_o <= video_on and vga_bg_colour(1);
vga_blue_o <= video_on and vga_bg_colour(2);
end if;
end if;
end process;
--
-- Sync generator & timing process
-- Generate Horizontal and Vertical Timing Signals for Video Signal
--
vga_sync : process(vga_clk)
begin
if vga_clk'event and vga_clk = '0' then
--
-- H_count counts pixels (640 + extra time for sync signals)
--
-- Horiz_sync -----------------------------__________--------
-- H_count 0 640 659 755 799
--
if unsigned(h_count) = HOR_SCAN_END then
h_count <= (others=>'0');
else
h_count <= std_logic_vector(unsigned(h_count) + 1);
end if;
--
-- Generate Horizontal Sync Signal using H_count
--
if unsigned(h_count) = HOR_SYNC_BEG then
horiz_sync <= '0';
elsif unsigned(h_count) = HOR_SYNC_END then
horiz_sync <= '1';
else
horiz_sync <= horiz_sync;
end if;
--
-- V_count counts rows of pixels
-- 400 lines + extra time for sync signals
-- 25 rows * 16 scan lines
--
-- Vert_sync ---------------------------------_______------------
-- V_count 0 400 413 414 444
--
if (unsigned(v_count) = VER_SCAN_END) and (unsigned(h_count) = HOR_SCAN_END) then
v_count <= "000000000";
elsif unsigned(h_count) = HOR_SYNC_END then
v_count <= std_logic_vector(unsigned(v_count) + 1);
end if;
--
-- Generate Vertical Sync Signal using V_count
--
if unsigned(v_count) = VER_SYNC_BEG then
vert_sync <= '0';
elsif unsigned(v_count) = VER_SYNC_END then
vert_sync <= '1';
else
vert_sync <= vert_sync;
end if;
-- Generate Video on Screen Signals for Pixel Data
if unsigned(h_count) = HOR_SCAN_END then
video_on_h <= '1';
elsif unsigned(h_count) = HOR_DISP_END then
video_on_h <= '0';
else
video_on_h <= video_on_h;
end if;
if unsigned(v_count) = VER_SCAN_END then
video_on_v <= '1';
elsif unsigned(v_count) = VER_DISP_END then
video_on_v <= '0';
else
video_on_v <= video_on_v;
end if;
if h_count(9 downto 3) = reg_hcursor(6 downto 0) then
cursor_on_h <= '1';
else
cursor_on_h <= '0';
end if;
if (v_count(8 downto 4) = reg_vcursor(4 downto 0)) then
cursor_on_v <= '1';
else
cursor_on_v <= '0';
end if;
-- cursor_on is only active when on selected character
blink_count <= std_logic_vector(unsigned(blink_count) + 1);
end if;
end process;
-- video_on is high only when RGB data is displayed
vga_hsync_o <= horiz_sync;
vga_vsync_o <= vert_sync;
video_on1 <= video_on_H and video_on_V;
cursor_on1 <= cursor_on_h and cursor_on_v;
--
-- Here to look up character ROM
-- This will take one clock cycle
-- and should be performed on h_count = "111"
--
char_addr(10 downto 4) <= vga_data_out(6 downto 0);
char_addr(3 downto 0) <= v_count(3 downto 0);
end RTL;
| gpl-3.0 | ee0e402af98662ca01fba517e82db9c6 | 0.507867 | 3.490199 | false | false | false | false |
grwlf/vsim | vhdl_ct/ct00562.vhd | 1 | 18,827 | -- NEED RESULT: ARCH00562: Aliasing - scalar generic subtypes passed
-------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
-------------------------------------------------------------------------------
--
-- TEST NAME:
--
-- CT00562
--
-- AUTHOR:
--
-- A. Wilmot
--
-- TEST OBJECTIVES:
--
-- 4.3.4 (1)
-- 4.3.4 (2)
-- 4.3.4 (11)
--
-- DESIGN UNIT ORDERING:
--
-- GENERIC_STANDARD_TYPES(ARCH00562)
-- ENT00562_Test_Bench(ARCH00562_Test_Bench)
--
-- REVISION HISTORY:
--
-- 19-AUG-1987 - initial revision
--
-- NOTES:
--
-- self-checking
-- automatically generated
--
use WORK.STANDARD_TYPES.all ;
architecture ARCH00562 of GENERIC_STANDARD_TYPES is
constant co_boolean_1 : boolean
:= c_boolean_1 ;
constant co_bit_1 : bit
:= c_bit_1 ;
constant co_severity_level_1 : severity_level
:= c_severity_level_1 ;
constant co_character_1 : character
:= c_character_1 ;
constant co_t_enum1_1 : t_enum1
:= c_t_enum1_1 ;
constant co_st_enum1_1 : st_enum1
:= c_st_enum1_1 ;
constant co_integer_1 : integer
:= c_integer_1 ;
constant co_t_int1_1 : t_int1
:= c_t_int1_1 ;
constant co_st_int1_1 : st_int1
:= c_st_int1_1 ;
constant co_time_1 : time
:= c_time_1 ;
constant co_t_phys1_1 : t_phys1
:= c_t_phys1_1 ;
constant co_st_phys1_1 : st_phys1
:= c_st_phys1_1 ;
constant co_real_1 : real
:= c_real_1 ;
constant co_t_real1_1 : t_real1
:= c_t_real1_1 ;
constant co_st_real1_1 : st_real1
:= c_st_real1_1 ;
signal si_boolean_1 : boolean
:= c_boolean_1 ;
signal si_bit_1 : bit
:= c_bit_1 ;
signal si_severity_level_1 : severity_level
:= c_severity_level_1 ;
signal si_character_1 : character
:= c_character_1 ;
signal si_t_enum1_1 : t_enum1
:= c_t_enum1_1 ;
signal si_st_enum1_1 : st_enum1
:= c_st_enum1_1 ;
signal si_integer_1 : integer
:= c_integer_1 ;
signal si_t_int1_1 : t_int1
:= c_t_int1_1 ;
signal si_st_int1_1 : st_int1
:= c_st_int1_1 ;
signal si_time_1 : time
:= c_time_1 ;
signal si_t_phys1_1 : t_phys1
:= c_t_phys1_1 ;
signal si_st_phys1_1 : st_phys1
:= c_st_phys1_1 ;
signal si_real_1 : real
:= c_real_1 ;
signal si_t_real1_1 : t_real1
:= c_t_real1_1 ;
signal si_st_real1_1 : st_real1
:= c_st_real1_1 ;
alias as_boolean_1 : boolean
is si_boolean_1 ;
alias as_bit_1 : bit
is si_bit_1 ;
alias as_severity_level_1 : severity_level
is si_severity_level_1 ;
alias as_character_1 : character
is si_character_1 ;
alias as_t_enum1_1 : t_enum1
is si_t_enum1_1 ;
alias as_st_enum1_1 : st_enum1
is si_st_enum1_1 ;
alias as_integer_1 : integer
is si_integer_1 ;
alias as_t_int1_1 : t_int1
is si_t_int1_1 ;
alias as_st_int1_1 : st_int1
is si_st_int1_1 ;
alias as_time_1 : time
is si_time_1 ;
alias as_t_phys1_1 : t_phys1
is si_t_phys1_1 ;
alias as_st_phys1_1 : st_phys1
is si_st_phys1_1 ;
alias as_real_1 : real
is si_real_1 ;
alias as_t_real1_1 : t_real1
is si_t_real1_1 ;
alias as_st_real1_1 : st_real1
is si_st_real1_1 ;
type test is (initial, intermediate, final) ;
signal synch : test := initial ;
signal s_correct1 : boolean ;
signal s_correct2 : boolean ;
begin
process
variable correct : boolean := true ;
begin
if synch = initial then
correct := correct and as_boolean_1 = c_boolean_1 ;
correct := correct and as_bit_1 = c_bit_1 ;
correct := correct and as_severity_level_1 = c_severity_level_1 ;
correct := correct and as_character_1 = c_character_1 ;
correct := correct and as_t_enum1_1 = c_t_enum1_1 ;
correct := correct and as_st_enum1_1 = c_st_enum1_1 ;
correct := correct and as_integer_1 = c_integer_1 ;
correct := correct and as_t_int1_1 = c_t_int1_1 ;
correct := correct and as_st_int1_1 = c_st_int1_1 ;
correct := correct and as_time_1 = c_time_1 ;
correct := correct and as_t_phys1_1 = c_t_phys1_1 ;
correct := correct and as_st_phys1_1 = c_st_phys1_1 ;
correct := correct and as_real_1 = c_real_1 ;
correct := correct and as_t_real1_1 = c_t_real1_1 ;
correct := correct and as_st_real1_1 = c_st_real1_1 ;
si_boolean_1 <= c_boolean_2 ;
si_bit_1 <= c_bit_2 ;
si_severity_level_1 <= c_severity_level_2 ;
si_character_1 <= c_character_2 ;
si_t_enum1_1 <= c_t_enum1_2 ;
si_st_enum1_1 <= c_st_enum1_2 ;
si_integer_1 <= c_integer_2 ;
si_t_int1_1 <= c_t_int1_2 ;
si_st_int1_1 <= c_st_int1_2 ;
si_time_1 <= c_time_2 ;
si_t_phys1_1 <= c_t_phys1_2 ;
si_st_phys1_1 <= c_st_phys1_2 ;
si_real_1 <= c_real_2 ;
si_t_real1_1 <= c_t_real1_2 ;
si_st_real1_1 <= c_st_real1_2 ;
synch <= intermediate ;
as_boolean_1 <= transport c_boolean_1 after 1 ns ;
as_bit_1 <= transport c_bit_1 after 1 ns ;
as_severity_level_1 <= transport c_severity_level_1 after 1 ns ;
as_character_1 <= transport c_character_1 after 1 ns ;
as_t_enum1_1 <= transport c_t_enum1_1 after 1 ns ;
as_st_enum1_1 <= transport c_st_enum1_1 after 1 ns ;
as_integer_1 <= transport c_integer_1 after 1 ns ;
as_t_int1_1 <= transport c_t_int1_1 after 1 ns ;
as_st_int1_1 <= transport c_st_int1_1 after 1 ns ;
as_time_1 <= transport c_time_1 after 1 ns ;
as_t_phys1_1 <= transport c_t_phys1_1 after 1 ns ;
as_st_phys1_1 <= transport c_st_phys1_1 after 1 ns ;
as_real_1 <= transport c_real_1 after 1 ns ;
as_t_real1_1 <= transport c_t_real1_1 after 1 ns ;
as_st_real1_1 <= transport c_st_real1_1 after 1 ns ;
synch <= transport final after 1 ns ;
s_correct1 <= correct ;
end if ;
wait ;
end process ;
process (synch)
procedure p1 is
variable correct : boolean ;
variable va_boolean_1 : boolean
:= c_boolean_1 ;
variable va_bit_1 : bit
:= c_bit_1 ;
variable va_severity_level_1 : severity_level
:= c_severity_level_1 ;
variable va_character_1 : character
:= c_character_1 ;
variable va_t_enum1_1 : t_enum1
:= c_t_enum1_1 ;
variable va_st_enum1_1 : st_enum1
:= c_st_enum1_1 ;
variable va_integer_1 : integer
:= c_integer_1 ;
variable va_t_int1_1 : t_int1
:= c_t_int1_1 ;
variable va_st_int1_1 : st_int1
:= c_st_int1_1 ;
variable va_time_1 : time
:= c_time_1 ;
variable va_t_phys1_1 : t_phys1
:= c_t_phys1_1 ;
variable va_st_phys1_1 : st_phys1
:= c_st_phys1_1 ;
variable va_real_1 : real
:= c_real_1 ;
variable va_t_real1_1 : t_real1
:= c_t_real1_1 ;
variable va_st_real1_1 : st_real1
:= c_st_real1_1 ;
alias ac_boolean_1 : boolean
is co_boolean_1 ;
alias ac_bit_1 : bit
is co_bit_1 ;
alias ac_severity_level_1 : severity_level
is co_severity_level_1 ;
alias ac_character_1 : character
is co_character_1 ;
alias ac_t_enum1_1 : t_enum1
is co_t_enum1_1 ;
alias ac_st_enum1_1 : st_enum1
is co_st_enum1_1 ;
alias ac_integer_1 : integer
is co_integer_1 ;
alias ac_t_int1_1 : t_int1
is co_t_int1_1 ;
alias ac_st_int1_1 : st_int1
is co_st_int1_1 ;
alias ac_time_1 : time
is co_time_1 ;
alias ac_t_phys1_1 : t_phys1
is co_t_phys1_1 ;
alias ac_st_phys1_1 : st_phys1
is co_st_phys1_1 ;
alias ac_real_1 : real
is co_real_1 ;
alias ac_t_real1_1 : t_real1
is co_t_real1_1 ;
alias ac_st_real1_1 : st_real1
is co_st_real1_1 ;
alias av_boolean_1 : boolean
is va_boolean_1 ;
alias av_bit_1 : bit
is va_bit_1 ;
alias av_severity_level_1 : severity_level
is va_severity_level_1 ;
alias av_character_1 : character
is va_character_1 ;
alias av_t_enum1_1 : t_enum1
is va_t_enum1_1 ;
alias av_st_enum1_1 : st_enum1
is va_st_enum1_1 ;
alias av_integer_1 : integer
is va_integer_1 ;
alias av_t_int1_1 : t_int1
is va_t_int1_1 ;
alias av_st_int1_1 : st_int1
is va_st_int1_1 ;
alias av_time_1 : time
is va_time_1 ;
alias av_t_phys1_1 : t_phys1
is va_t_phys1_1 ;
alias av_st_phys1_1 : st_phys1
is va_st_phys1_1 ;
alias av_real_1 : real
is va_real_1 ;
alias av_t_real1_1 : t_real1
is va_t_real1_1 ;
alias av_st_real1_1 : st_real1
is va_st_real1_1 ;
begin
correct := s_correct1 ;
if synch = intermediate then
-- test that variables denote same object
correct := correct and av_boolean_1 = c_boolean_1 ;
correct := correct and av_bit_1 = c_bit_1 ;
correct := correct and av_severity_level_1 = c_severity_level_1 ;
correct := correct and av_character_1 = c_character_1 ;
correct := correct and av_t_enum1_1 = c_t_enum1_1 ;
correct := correct and av_st_enum1_1 = c_st_enum1_1 ;
correct := correct and av_integer_1 = c_integer_1 ;
correct := correct and av_t_int1_1 = c_t_int1_1 ;
correct := correct and av_st_int1_1 = c_st_int1_1 ;
correct := correct and av_time_1 = c_time_1 ;
correct := correct and av_t_phys1_1 = c_t_phys1_1 ;
correct := correct and av_st_phys1_1 = c_st_phys1_1 ;
correct := correct and av_real_1 = c_real_1 ;
correct := correct and av_t_real1_1 = c_t_real1_1 ;
correct := correct and av_st_real1_1 = c_st_real1_1 ;
va_boolean_1 := c_boolean_2 ;
va_bit_1 := c_bit_2 ;
va_severity_level_1 := c_severity_level_2 ;
va_character_1 := c_character_2 ;
va_t_enum1_1 := c_t_enum1_2 ;
va_st_enum1_1 := c_st_enum1_2 ;
va_integer_1 := c_integer_2 ;
va_t_int1_1 := c_t_int1_2 ;
va_st_int1_1 := c_st_int1_2 ;
va_time_1 := c_time_2 ;
va_t_phys1_1 := c_t_phys1_2 ;
va_st_phys1_1 := c_st_phys1_2 ;
va_real_1 := c_real_2 ;
va_t_real1_1 := c_t_real1_2 ;
va_st_real1_1 := c_st_real1_2 ;
correct := correct and av_boolean_1 = c_boolean_2 ;
correct := correct and av_bit_1 = c_bit_2 ;
correct := correct and av_severity_level_1 = c_severity_level_2 ;
correct := correct and av_character_1 = c_character_2 ;
correct := correct and av_t_enum1_1 = c_t_enum1_2 ;
correct := correct and av_st_enum1_1 = c_st_enum1_2 ;
correct := correct and av_integer_1 = c_integer_2 ;
correct := correct and av_t_int1_1 = c_t_int1_2 ;
correct := correct and av_st_int1_1 = c_st_int1_2 ;
correct := correct and av_time_1 = c_time_2 ;
correct := correct and av_t_phys1_1 = c_t_phys1_2 ;
correct := correct and av_st_phys1_1 = c_st_phys1_2 ;
correct := correct and av_real_1 = c_real_2 ;
correct := correct and av_t_real1_1 = c_t_real1_2 ;
correct := correct and av_st_real1_1 = c_st_real1_2 ;
av_boolean_1 := c_boolean_1 ;
av_bit_1 := c_bit_1 ;
av_severity_level_1 := c_severity_level_1 ;
av_character_1 := c_character_1 ;
av_t_enum1_1 := c_t_enum1_1 ;
av_st_enum1_1 := c_st_enum1_1 ;
av_integer_1 := c_integer_1 ;
av_t_int1_1 := c_t_int1_1 ;
av_st_int1_1 := c_st_int1_1 ;
av_time_1 := c_time_1 ;
av_t_phys1_1 := c_t_phys1_1 ;
av_st_phys1_1 := c_st_phys1_1 ;
av_real_1 := c_real_1 ;
av_t_real1_1 := c_t_real1_1 ;
av_st_real1_1 := c_st_real1_1 ;
correct := correct and va_boolean_1 = c_boolean_1 ;
correct := correct and va_bit_1 = c_bit_1 ;
correct := correct and va_severity_level_1 = c_severity_level_1 ;
correct := correct and va_character_1 = c_character_1 ;
correct := correct and va_t_enum1_1 = c_t_enum1_1 ;
correct := correct and va_st_enum1_1 = c_st_enum1_1 ;
correct := correct and va_integer_1 = c_integer_1 ;
correct := correct and va_t_int1_1 = c_t_int1_1 ;
correct := correct and va_st_int1_1 = c_st_int1_1 ;
correct := correct and va_time_1 = c_time_1 ;
correct := correct and va_t_phys1_1 = c_t_phys1_1 ;
correct := correct and va_st_phys1_1 = c_st_phys1_1 ;
correct := correct and va_real_1 = c_real_1 ;
correct := correct and va_t_real1_1 = c_t_real1_1 ;
correct := correct and va_st_real1_1 = c_st_real1_1 ;
-- test that signals denote same object
correct := correct and as_boolean_1 = c_boolean_2 ;
correct := correct and as_bit_1 = c_bit_2 ;
correct := correct and as_severity_level_1 = c_severity_level_2 ;
correct := correct and as_character_1 = c_character_2 ;
correct := correct and as_t_enum1_1 = c_t_enum1_2 ;
correct := correct and as_st_enum1_1 = c_st_enum1_2 ;
correct := correct and as_integer_1 = c_integer_2 ;
correct := correct and as_t_int1_1 = c_t_int1_2 ;
correct := correct and as_st_int1_1 = c_st_int1_2 ;
correct := correct and as_time_1 = c_time_2 ;
correct := correct and as_t_phys1_1 = c_t_phys1_2 ;
correct := correct and as_st_phys1_1 = c_st_phys1_2 ;
correct := correct and as_real_1 = c_real_2 ;
correct := correct and as_t_real1_1 = c_t_real1_2 ;
correct := correct and as_st_real1_1 = c_st_real1_2 ;
correct := correct and si_boolean_1 = c_boolean_2 ;
correct := correct and si_bit_1 = c_bit_2 ;
correct := correct and si_severity_level_1 = c_severity_level_2 ;
correct := correct and si_character_1 = c_character_2 ;
correct := correct and si_t_enum1_1 = c_t_enum1_2 ;
correct := correct and si_st_enum1_1 = c_st_enum1_2 ;
correct := correct and si_integer_1 = c_integer_2 ;
correct := correct and si_t_int1_1 = c_t_int1_2 ;
correct := correct and si_st_int1_1 = c_st_int1_2 ;
correct := correct and si_time_1 = c_time_2 ;
correct := correct and si_t_phys1_1 = c_t_phys1_2 ;
correct := correct and si_st_phys1_1 = c_st_phys1_2 ;
correct := correct and si_real_1 = c_real_2 ;
correct := correct and si_t_real1_1 = c_t_real1_2 ;
correct := correct and si_st_real1_1 = c_st_real1_2 ;
-- test that constants denote same object
correct := correct and ac_boolean_1 = c_boolean_1 ;
correct := correct and ac_bit_1 = c_bit_1 ;
correct := correct and ac_severity_level_1 = c_severity_level_1 ;
correct := correct and ac_character_1 = c_character_1 ;
correct := correct and ac_t_enum1_1 = c_t_enum1_1 ;
correct := correct and ac_st_enum1_1 = c_st_enum1_1 ;
correct := correct and ac_integer_1 = c_integer_1 ;
correct := correct and ac_t_int1_1 = c_t_int1_1 ;
correct := correct and ac_st_int1_1 = c_st_int1_1 ;
correct := correct and ac_time_1 = c_time_1 ;
correct := correct and ac_t_phys1_1 = c_t_phys1_1 ;
correct := correct and ac_st_phys1_1 = c_st_phys1_1 ;
correct := correct and ac_real_1 = c_real_1 ;
correct := correct and ac_t_real1_1 = c_t_real1_1 ;
correct := correct and ac_st_real1_1 = c_st_real1_1 ;
s_correct2 <= correct ;
end if ;
end p1 ;
begin
p1 ;
end process ;
--
process (synch)
variable correct : boolean ;
begin
if synch = final then
correct := s_correct2 ;
correct := correct and si_boolean_1 = c_boolean_1 ;
correct := correct and si_bit_1 = c_bit_1 ;
correct := correct and si_severity_level_1 = c_severity_level_1 ;
correct := correct and si_character_1 = c_character_1 ;
correct := correct and si_t_enum1_1 = c_t_enum1_1 ;
correct := correct and si_st_enum1_1 = c_st_enum1_1 ;
correct := correct and si_integer_1 = c_integer_1 ;
correct := correct and si_t_int1_1 = c_t_int1_1 ;
correct := correct and si_st_int1_1 = c_st_int1_1 ;
correct := correct and si_time_1 = c_time_1 ;
correct := correct and si_t_phys1_1 = c_t_phys1_1 ;
correct := correct and si_st_phys1_1 = c_st_phys1_1 ;
correct := correct and si_real_1 = c_real_1 ;
correct := correct and si_t_real1_1 = c_t_real1_1 ;
correct := correct and si_st_real1_1 = c_st_real1_1 ;
test_report ( "ARCH00562" ,
"Aliasing - scalar generic subtypes" ,
correct) ;
end if ;
end process ;
end ARCH00562 ;
--
entity ENT00562_Test_Bench is
end ENT00562_Test_Bench ;
--
architecture ARCH00562_Test_Bench of ENT00562_Test_Bench is
begin
L1:
block
component UUT
end component ;
for CIS1 : UUT use entity WORK.GENERIC_STANDARD_TYPES ( ARCH00562 ) ;
begin
CIS1 : UUT ;
end block L1 ;
end ARCH00562_Test_Bench ;
| gpl-3.0 | ae5ab0b76f697b81c271a09df276666a | 0.512296 | 3.054348 | false | false | false | false |
grwlf/vsim | vhdl_ct/ct00390.vhd | 1 | 69,202 | -- NEED RESULT: ARCH00390.P1: Multi inertial transactions occurred on concurrent signal asg passed
-- NEED RESULT: ARCH00390.P2: Multi inertial transactions occurred on concurrent signal asg passed
-- NEED RESULT: ARCH00390.P3: Multi inertial transactions occurred on concurrent signal asg passed
-- NEED RESULT: ARCH00390.P4: Multi inertial transactions occurred on concurrent signal asg passed
-- NEED RESULT: ARCH00390.P5: Multi inertial transactions occurred on concurrent signal asg passed
-- NEED RESULT: ARCH00390.P6: Multi inertial transactions occurred on concurrent signal asg passed
-- NEED RESULT: ARCH00390.P7: Multi inertial transactions occurred on concurrent signal asg passed
-- NEED RESULT: ARCH00390.P8: Multi inertial transactions occurred on concurrent signal asg passed
-- NEED RESULT: ARCH00390.P9: Multi inertial transactions occurred on concurrent signal asg passed
-- NEED RESULT: ARCH00390: One inertial transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00390: One inertial transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00390: One inertial transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00390: One inertial transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00390: One inertial transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00390: One inertial transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00390: One inertial transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00390: One inertial transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00390: One inertial transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00390: Old transactions were removed on a concurrent signal asg passed
-- NEED RESULT: ARCH00390: Old transactions were removed on a concurrent signal asg passed
-- NEED RESULT: ARCH00390: Old transactions were removed on a concurrent signal asg passed
-- NEED RESULT: ARCH00390: Old transactions were removed on a concurrent signal asg passed
-- NEED RESULT: ARCH00390: Old transactions were removed on a concurrent signal asg passed
-- NEED RESULT: ARCH00390: Old transactions were removed on a concurrent signal asg passed
-- NEED RESULT: ARCH00390: Old transactions were removed on a concurrent signal asg passed
-- NEED RESULT: ARCH00390: Old transactions were removed on a concurrent signal asg passed
-- NEED RESULT: ARCH00390: Old transactions were removed on a concurrent signal asg passed
-- NEED RESULT: ARCH00390: One inertial transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00390: One inertial transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00390: One inertial transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00390: One inertial transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00390: One inertial transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00390: One inertial transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00390: One inertial transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00390: One inertial transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00390: One inertial transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00390: Inertial semantics check on a concurrent signal asg passed
-- NEED RESULT: ARCH00390: Inertial semantics check on a concurrent signal asg passed
-- NEED RESULT: ARCH00390: Inertial semantics check on a concurrent signal asg passed
-- NEED RESULT: ARCH00390: Inertial semantics check on a concurrent signal asg passed
-- NEED RESULT: ARCH00390: Inertial semantics check on a concurrent signal asg passed
-- NEED RESULT: ARCH00390: Inertial semantics check on a concurrent signal asg passed
-- NEED RESULT: ARCH00390: Inertial semantics check on a concurrent signal asg passed
-- NEED RESULT: ARCH00390: Inertial semantics check on a concurrent signal asg passed
-- NEED RESULT: ARCH00390: Inertial semantics check on a concurrent signal asg passed
-- NEED RESULT: P9: Inertial transactions completed entirely passed
-- NEED RESULT: P8: Inertial transactions completed entirely passed
-- NEED RESULT: P7: Inertial transactions completed entirely passed
-- NEED RESULT: P6: Inertial transactions completed entirely passed
-- NEED RESULT: P5: Inertial transactions completed entirely passed
-- NEED RESULT: P4: Inertial transactions completed entirely passed
-- NEED RESULT: P3: Inertial transactions completed entirely passed
-- NEED RESULT: P2: Inertial transactions completed entirely passed
-- NEED RESULT: P1: Inertial transactions completed entirely passed
-------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
-------------------------------------------------------------------------------
--
-- TEST NAME:
--
-- CT00390
--
-- AUTHOR:
--
-- G. Tominovich
--
-- TEST OBJECTIVES:
--
-- 9.5 (3)
-- 9.5.1 (1)
-- 9.5.1 (2)
--
-- DESIGN UNIT ORDERING:
--
-- ENT00390(ARCH00390)
-- ENT00390_Test_Bench(ARCH00390_Test_Bench)
--
-- REVISION HISTORY:
--
-- 30-JUL-1987 - initial revision
--
-- NOTES:
--
-- self-checking
-- automatically generated
--
use WORK.STANDARD_TYPES.all ;
entity ENT00390 is
end ENT00390 ;
--
--
architecture ARCH00390 of ENT00390 is
subtype chk_sig_type is integer range -1 to 100 ;
signal chk_st_boolean_vector : chk_sig_type := -1 ;
signal chk_st_severity_level_vector : chk_sig_type := -1 ;
signal chk_st_string : chk_sig_type := -1 ;
signal chk_st_enum1_vector : chk_sig_type := -1 ;
signal chk_st_integer_vector : chk_sig_type := -1 ;
signal chk_st_time_vector : chk_sig_type := -1 ;
signal chk_st_real_vector : chk_sig_type := -1 ;
signal chk_st_rec1_vector : chk_sig_type := -1 ;
signal chk_st_arr2_vector : chk_sig_type := -1 ;
--
subtype chk_time_type is Time ;
signal s_st_boolean_vector_savt : chk_time_type := 0 ns ;
signal s_st_severity_level_vector_savt : chk_time_type := 0 ns ;
signal s_st_string_savt : chk_time_type := 0 ns ;
signal s_st_enum1_vector_savt : chk_time_type := 0 ns ;
signal s_st_integer_vector_savt : chk_time_type := 0 ns ;
signal s_st_time_vector_savt : chk_time_type := 0 ns ;
signal s_st_real_vector_savt : chk_time_type := 0 ns ;
signal s_st_rec1_vector_savt : chk_time_type := 0 ns ;
signal s_st_arr2_vector_savt : chk_time_type := 0 ns ;
--
subtype chk_cnt_type is Integer ;
signal s_st_boolean_vector_cnt : chk_cnt_type := 0 ;
signal s_st_severity_level_vector_cnt : chk_cnt_type := 0 ;
signal s_st_string_cnt : chk_cnt_type := 0 ;
signal s_st_enum1_vector_cnt : chk_cnt_type := 0 ;
signal s_st_integer_vector_cnt : chk_cnt_type := 0 ;
signal s_st_time_vector_cnt : chk_cnt_type := 0 ;
signal s_st_real_vector_cnt : chk_cnt_type := 0 ;
signal s_st_rec1_vector_cnt : chk_cnt_type := 0 ;
signal s_st_arr2_vector_cnt : chk_cnt_type := 0 ;
--
type select_type is range 1 to 6 ;
signal st_boolean_vector_select : select_type := 1 ;
signal st_severity_level_vector_select : select_type := 1 ;
signal st_string_select : select_type := 1 ;
signal st_enum1_vector_select : select_type := 1 ;
signal st_integer_vector_select : select_type := 1 ;
signal st_time_vector_select : select_type := 1 ;
signal st_real_vector_select : select_type := 1 ;
signal st_rec1_vector_select : select_type := 1 ;
signal st_arr2_vector_select : select_type := 1 ;
--
signal s_st_boolean_vector : st_boolean_vector
:= c_st_boolean_vector_1 ;
signal s_st_severity_level_vector : st_severity_level_vector
:= c_st_severity_level_vector_1 ;
signal s_st_string : st_string
:= c_st_string_1 ;
signal s_st_enum1_vector : st_enum1_vector
:= c_st_enum1_vector_1 ;
signal s_st_integer_vector : st_integer_vector
:= c_st_integer_vector_1 ;
signal s_st_time_vector : st_time_vector
:= c_st_time_vector_1 ;
signal s_st_real_vector : st_real_vector
:= c_st_real_vector_1 ;
signal s_st_rec1_vector : st_rec1_vector
:= c_st_rec1_vector_1 ;
signal s_st_arr2_vector : st_arr2_vector
:= c_st_arr2_vector_1 ;
--
begin
CHG1 :
process
variable correct : boolean ;
begin
case s_st_boolean_vector_cnt is
when 0
=> null ;
-- s_st_boolean_vector(lowb to highb-1) <=
-- c_st_boolean_vector_2(lowb to highb-1) after 10 ns,
-- c_st_boolean_vector_1(lowb to highb-1) after 20 ns ;
--
when 1
=> correct :=
s_st_boolean_vector(lowb to highb-1) =
c_st_boolean_vector_2(lowb to highb-1) and
(s_st_boolean_vector_savt + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_boolean_vector(lowb to highb-1) =
c_st_boolean_vector_1(lowb to highb-1) and
(s_st_boolean_vector_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00390.P1" ,
"Multi inertial transactions occurred on " &
"concurrent signal asg",
correct ) ;
--
st_boolean_vector_select <= transport 2 ;
-- s_st_boolean_vector(lowb to highb-1) <=
-- c_st_boolean_vector_2(lowb to highb-1) after 10 ns ,
-- c_st_boolean_vector_1(lowb to highb-1) after 20 ns ,
-- c_st_boolean_vector_2(lowb to highb-1) after 30 ns ,
-- c_st_boolean_vector_1(lowb to highb-1) after 40 ns ;
--
when 3
=> correct :=
s_st_boolean_vector(lowb to highb-1) =
c_st_boolean_vector_2(lowb to highb-1) and
(s_st_boolean_vector_savt + 10 ns) = Std.Standard.Now ;
st_boolean_vector_select <= transport 3 ;
-- s_st_boolean_vector(lowb to highb-1) <=
-- c_st_boolean_vector_1(lowb to highb-1) after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_boolean_vector(lowb to highb-1) =
c_st_boolean_vector_1(lowb to highb-1) and
(s_st_boolean_vector_savt + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00390" ,
"One inertial transaction occurred on a " &
"concurrent signal asg",
correct ) ;
st_boolean_vector_select <= transport 4 ;
-- s_st_boolean_vector(lowb to highb-1) <=
-- c_st_boolean_vector_1(lowb to highb-1) after 100 ns ;
--
when 5
=> correct :=
correct and
s_st_boolean_vector(lowb to highb-1) =
c_st_boolean_vector_1(lowb to highb-1) and
(s_st_boolean_vector_savt + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00390" ,
"Old transactions were removed on a " &
"concurrent signal asg",
correct ) ;
st_boolean_vector_select <= transport 5 ;
-- s_st_boolean_vector(lowb to highb-1) <=
-- c_st_boolean_vector_2(lowb to highb-1) after 10 ns ,
-- c_st_boolean_vector_1(lowb to highb-1) after 20 ns ,
-- c_st_boolean_vector_2(lowb to highb-1) after 30 ns ,
-- c_st_boolean_vector_1(lowb to highb-1) after 40 ns ;
--
when 6
=> correct :=
correct and
s_st_boolean_vector(lowb to highb-1) =
c_st_boolean_vector_2(lowb to highb-1) and
(s_st_boolean_vector_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00390" ,
"One inertial transaction occurred on a " &
"concurrent signal asg",
correct ) ;
st_boolean_vector_select <= transport 6 ;
-- Last transaction above is marked
-- s_st_boolean_vector(lowb to highb-1) <=
-- c_st_boolean_vector_1(lowb to highb-1) after 40 ns ;
--
when 7
=> correct :=
correct and
s_st_boolean_vector(lowb to highb-1) =
c_st_boolean_vector_1(lowb to highb-1) and
(s_st_boolean_vector_savt + 30 ns) = Std.Standard.Now ;
--
when 8
=> correct :=
correct and
s_st_boolean_vector(lowb to highb-1) =
c_st_boolean_vector_1(lowb to highb-1) and
(s_st_boolean_vector_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00390" ,
"Inertial semantics check on a concurrent " &
"signal asg",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00390" ,
"Inertial semantics check on a concurrent " &
"signal asg",
false ) ;
--
end case ;
--
s_st_boolean_vector_savt <= transport Std.Standard.Now ;
chk_st_boolean_vector <= transport s_st_boolean_vector_cnt
after (1 us - Std.Standard.Now) ;
s_st_boolean_vector_cnt <= transport s_st_boolean_vector_cnt + 1 ;
wait until (not s_st_boolean_vector(lowb to highb-1)'Quiet) and
(s_st_boolean_vector_savt /= Std.Standard.Now) ;
--
end process CHG1 ;
--
PGEN_CHKP_1 :
process ( chk_st_boolean_vector )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P1" ,
"Inertial transactions completed entirely",
chk_st_boolean_vector = 8 ) ;
end if ;
end process PGEN_CHKP_1 ;
--
--
s_st_boolean_vector(lowb to highb-1) <=
c_st_boolean_vector_2(lowb to highb-1) after 10 ns,
c_st_boolean_vector_1(lowb to highb-1) after 20 ns
when st_boolean_vector_select = 1 else
--
c_st_boolean_vector_2(lowb to highb-1) after 10 ns ,
c_st_boolean_vector_1(lowb to highb-1) after 20 ns ,
c_st_boolean_vector_2(lowb to highb-1) after 30 ns ,
c_st_boolean_vector_1(lowb to highb-1) after 40 ns
when st_boolean_vector_select = 2 else
--
c_st_boolean_vector_1(lowb to highb-1) after 5 ns
when st_boolean_vector_select = 3 else
--
c_st_boolean_vector_1(lowb to highb-1) after 100 ns
when st_boolean_vector_select = 4 else
--
c_st_boolean_vector_2(lowb to highb-1) after 10 ns ,
c_st_boolean_vector_1(lowb to highb-1) after 20 ns ,
c_st_boolean_vector_2(lowb to highb-1) after 30 ns ,
c_st_boolean_vector_1(lowb to highb-1) after 40 ns
when st_boolean_vector_select = 5 else
--
-- Last transaction above is marked
c_st_boolean_vector_1(lowb to highb-1) after 40 ns ;
--
CHG2 :
process
variable correct : boolean ;
begin
case s_st_severity_level_vector_cnt is
when 0
=> null ;
-- s_st_severity_level_vector(lowb to highb-1) <=
-- c_st_severity_level_vector_2(lowb to highb-1) after 10 ns,
-- c_st_severity_level_vector_1(lowb to highb-1) after 20 ns ;
--
when 1
=> correct :=
s_st_severity_level_vector(lowb to highb-1) =
c_st_severity_level_vector_2(lowb to highb-1) and
(s_st_severity_level_vector_savt + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_severity_level_vector(lowb to highb-1) =
c_st_severity_level_vector_1(lowb to highb-1) and
(s_st_severity_level_vector_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00390.P2" ,
"Multi inertial transactions occurred on " &
"concurrent signal asg",
correct ) ;
--
st_severity_level_vector_select <= transport 2 ;
-- s_st_severity_level_vector(lowb to highb-1) <=
-- c_st_severity_level_vector_2(lowb to highb-1) after 10 ns ,
-- c_st_severity_level_vector_1(lowb to highb-1) after 20 ns ,
-- c_st_severity_level_vector_2(lowb to highb-1) after 30 ns ,
-- c_st_severity_level_vector_1(lowb to highb-1) after 40 ns ;
--
when 3
=> correct :=
s_st_severity_level_vector(lowb to highb-1) =
c_st_severity_level_vector_2(lowb to highb-1) and
(s_st_severity_level_vector_savt + 10 ns) = Std.Standard.Now ;
st_severity_level_vector_select <= transport 3 ;
-- s_st_severity_level_vector(lowb to highb-1) <=
-- c_st_severity_level_vector_1(lowb to highb-1) after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_severity_level_vector(lowb to highb-1) =
c_st_severity_level_vector_1(lowb to highb-1) and
(s_st_severity_level_vector_savt + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00390" ,
"One inertial transaction occurred on a " &
"concurrent signal asg",
correct ) ;
st_severity_level_vector_select <= transport 4 ;
-- s_st_severity_level_vector(lowb to highb-1) <=
-- c_st_severity_level_vector_1(lowb to highb-1) after 100 ns ;
--
when 5
=> correct :=
correct and
s_st_severity_level_vector(lowb to highb-1) =
c_st_severity_level_vector_1(lowb to highb-1) and
(s_st_severity_level_vector_savt + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00390" ,
"Old transactions were removed on a " &
"concurrent signal asg",
correct ) ;
st_severity_level_vector_select <= transport 5 ;
-- s_st_severity_level_vector(lowb to highb-1) <=
-- c_st_severity_level_vector_2(lowb to highb-1) after 10 ns ,
-- c_st_severity_level_vector_1(lowb to highb-1) after 20 ns ,
-- c_st_severity_level_vector_2(lowb to highb-1) after 30 ns ,
-- c_st_severity_level_vector_1(lowb to highb-1) after 40 ns ;
--
when 6
=> correct :=
correct and
s_st_severity_level_vector(lowb to highb-1) =
c_st_severity_level_vector_2(lowb to highb-1) and
(s_st_severity_level_vector_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00390" ,
"One inertial transaction occurred on a " &
"concurrent signal asg",
correct ) ;
st_severity_level_vector_select <= transport 6 ;
-- Last transaction above is marked
-- s_st_severity_level_vector(lowb to highb-1) <=
-- c_st_severity_level_vector_1(lowb to highb-1) after 40 ns ;
--
when 7
=> correct :=
correct and
s_st_severity_level_vector(lowb to highb-1) =
c_st_severity_level_vector_1(lowb to highb-1) and
(s_st_severity_level_vector_savt + 30 ns) = Std.Standard.Now ;
--
when 8
=> correct :=
correct and
s_st_severity_level_vector(lowb to highb-1) =
c_st_severity_level_vector_1(lowb to highb-1) and
(s_st_severity_level_vector_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00390" ,
"Inertial semantics check on a concurrent " &
"signal asg",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00390" ,
"Inertial semantics check on a concurrent " &
"signal asg",
false ) ;
--
end case ;
--
s_st_severity_level_vector_savt <= transport Std.Standard.Now ;
chk_st_severity_level_vector <= transport s_st_severity_level_vector_cnt
after (1 us - Std.Standard.Now) ;
s_st_severity_level_vector_cnt <= transport s_st_severity_level_vector_cnt
+ 1 ;
wait until (not s_st_severity_level_vector(lowb to highb-1)'Quiet) and
(s_st_severity_level_vector_savt /= Std.Standard.Now) ;
--
end process CHG2 ;
--
PGEN_CHKP_2 :
process ( chk_st_severity_level_vector )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P2" ,
"Inertial transactions completed entirely",
chk_st_severity_level_vector = 8 ) ;
end if ;
end process PGEN_CHKP_2 ;
--
--
s_st_severity_level_vector(lowb to highb-1) <=
c_st_severity_level_vector_2(lowb to highb-1) after 10 ns,
c_st_severity_level_vector_1(lowb to highb-1) after 20 ns
when st_severity_level_vector_select = 1 else
--
c_st_severity_level_vector_2(lowb to highb-1) after 10 ns ,
c_st_severity_level_vector_1(lowb to highb-1) after 20 ns ,
c_st_severity_level_vector_2(lowb to highb-1) after 30 ns ,
c_st_severity_level_vector_1(lowb to highb-1) after 40 ns
when st_severity_level_vector_select = 2 else
--
c_st_severity_level_vector_1(lowb to highb-1) after 5 ns
when st_severity_level_vector_select = 3 else
--
c_st_severity_level_vector_1(lowb to highb-1) after 100 ns
when st_severity_level_vector_select = 4 else
--
c_st_severity_level_vector_2(lowb to highb-1) after 10 ns ,
c_st_severity_level_vector_1(lowb to highb-1) after 20 ns ,
c_st_severity_level_vector_2(lowb to highb-1) after 30 ns ,
c_st_severity_level_vector_1(lowb to highb-1) after 40 ns
when st_severity_level_vector_select = 5 else
--
-- Last transaction above is marked
c_st_severity_level_vector_1(lowb to highb-1) after 40 ns ;
--
CHG3 :
process
variable correct : boolean ;
begin
case s_st_string_cnt is
when 0
=> null ;
-- s_st_string(highb-1 to highb-1) <=
-- c_st_string_2(highb-1 to highb-1) after 10 ns,
-- c_st_string_1(highb-1 to highb-1) after 20 ns ;
--
when 1
=> correct :=
s_st_string(highb-1 to highb-1) =
c_st_string_2(highb-1 to highb-1) and
(s_st_string_savt + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_string(highb-1 to highb-1) =
c_st_string_1(highb-1 to highb-1) and
(s_st_string_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00390.P3" ,
"Multi inertial transactions occurred on " &
"concurrent signal asg",
correct ) ;
--
st_string_select <= transport 2 ;
-- s_st_string(highb-1 to highb-1) <=
-- c_st_string_2(highb-1 to highb-1) after 10 ns ,
-- c_st_string_1(highb-1 to highb-1) after 20 ns ,
-- c_st_string_2(highb-1 to highb-1) after 30 ns ,
-- c_st_string_1(highb-1 to highb-1) after 40 ns ;
--
when 3
=> correct :=
s_st_string(highb-1 to highb-1) =
c_st_string_2(highb-1 to highb-1) and
(s_st_string_savt + 10 ns) = Std.Standard.Now ;
st_string_select <= transport 3 ;
-- s_st_string(highb-1 to highb-1) <=
-- c_st_string_1(highb-1 to highb-1) after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_string(highb-1 to highb-1) =
c_st_string_1(highb-1 to highb-1) and
(s_st_string_savt + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00390" ,
"One inertial transaction occurred on a " &
"concurrent signal asg",
correct ) ;
st_string_select <= transport 4 ;
-- s_st_string(highb-1 to highb-1) <=
-- c_st_string_1(highb-1 to highb-1) after 100 ns ;
--
when 5
=> correct :=
correct and
s_st_string(highb-1 to highb-1) =
c_st_string_1(highb-1 to highb-1) and
(s_st_string_savt + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00390" ,
"Old transactions were removed on a " &
"concurrent signal asg",
correct ) ;
st_string_select <= transport 5 ;
-- s_st_string(highb-1 to highb-1) <=
-- c_st_string_2(highb-1 to highb-1) after 10 ns ,
-- c_st_string_1(highb-1 to highb-1) after 20 ns ,
-- c_st_string_2(highb-1 to highb-1) after 30 ns ,
-- c_st_string_1(highb-1 to highb-1) after 40 ns ;
--
when 6
=> correct :=
correct and
s_st_string(highb-1 to highb-1) =
c_st_string_2(highb-1 to highb-1) and
(s_st_string_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00390" ,
"One inertial transaction occurred on a " &
"concurrent signal asg",
correct ) ;
st_string_select <= transport 6 ;
-- Last transaction above is marked
-- s_st_string(highb-1 to highb-1) <=
-- c_st_string_1(highb-1 to highb-1) after 40 ns ;
--
when 7
=> correct :=
correct and
s_st_string(highb-1 to highb-1) =
c_st_string_1(highb-1 to highb-1) and
(s_st_string_savt + 30 ns) = Std.Standard.Now ;
--
when 8
=> correct :=
correct and
s_st_string(highb-1 to highb-1) =
c_st_string_1(highb-1 to highb-1) and
(s_st_string_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00390" ,
"Inertial semantics check on a concurrent " &
"signal asg",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00390" ,
"Inertial semantics check on a concurrent " &
"signal asg",
false ) ;
--
end case ;
--
s_st_string_savt <= transport Std.Standard.Now ;
chk_st_string <= transport s_st_string_cnt
after (1 us - Std.Standard.Now) ;
s_st_string_cnt <= transport s_st_string_cnt + 1 ;
wait until (not s_st_string(highb-1 to highb-1)'Quiet) and
(s_st_string_savt /= Std.Standard.Now) ;
--
end process CHG3 ;
--
PGEN_CHKP_3 :
process ( chk_st_string )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P3" ,
"Inertial transactions completed entirely",
chk_st_string = 8 ) ;
end if ;
end process PGEN_CHKP_3 ;
--
--
s_st_string(highb-1 to highb-1) <=
c_st_string_2(highb-1 to highb-1) after 10 ns,
c_st_string_1(highb-1 to highb-1) after 20 ns
when st_string_select = 1 else
--
c_st_string_2(highb-1 to highb-1) after 10 ns ,
c_st_string_1(highb-1 to highb-1) after 20 ns ,
c_st_string_2(highb-1 to highb-1) after 30 ns ,
c_st_string_1(highb-1 to highb-1) after 40 ns
when st_string_select = 2 else
--
c_st_string_1(highb-1 to highb-1) after 5 ns
when st_string_select = 3 else
--
c_st_string_1(highb-1 to highb-1) after 100 ns
when st_string_select = 4 else
--
c_st_string_2(highb-1 to highb-1) after 10 ns ,
c_st_string_1(highb-1 to highb-1) after 20 ns ,
c_st_string_2(highb-1 to highb-1) after 30 ns ,
c_st_string_1(highb-1 to highb-1) after 40 ns
when st_string_select = 5 else
--
-- Last transaction above is marked
c_st_string_1(highb-1 to highb-1) after 40 ns ;
--
CHG4 :
process
variable correct : boolean ;
begin
case s_st_enum1_vector_cnt is
when 0
=> null ;
-- s_st_enum1_vector(highb-1 to highb-1) <=
-- c_st_enum1_vector_2(highb-1 to highb-1) after 10 ns,
-- c_st_enum1_vector_1(highb-1 to highb-1) after 20 ns ;
--
when 1
=> correct :=
s_st_enum1_vector(highb-1 to highb-1) =
c_st_enum1_vector_2(highb-1 to highb-1) and
(s_st_enum1_vector_savt + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_enum1_vector(highb-1 to highb-1) =
c_st_enum1_vector_1(highb-1 to highb-1) and
(s_st_enum1_vector_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00390.P4" ,
"Multi inertial transactions occurred on " &
"concurrent signal asg",
correct ) ;
--
st_enum1_vector_select <= transport 2 ;
-- s_st_enum1_vector(highb-1 to highb-1) <=
-- c_st_enum1_vector_2(highb-1 to highb-1) after 10 ns ,
-- c_st_enum1_vector_1(highb-1 to highb-1) after 20 ns ,
-- c_st_enum1_vector_2(highb-1 to highb-1) after 30 ns ,
-- c_st_enum1_vector_1(highb-1 to highb-1) after 40 ns ;
--
when 3
=> correct :=
s_st_enum1_vector(highb-1 to highb-1) =
c_st_enum1_vector_2(highb-1 to highb-1) and
(s_st_enum1_vector_savt + 10 ns) = Std.Standard.Now ;
st_enum1_vector_select <= transport 3 ;
-- s_st_enum1_vector(highb-1 to highb-1) <=
-- c_st_enum1_vector_1(highb-1 to highb-1) after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_enum1_vector(highb-1 to highb-1) =
c_st_enum1_vector_1(highb-1 to highb-1) and
(s_st_enum1_vector_savt + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00390" ,
"One inertial transaction occurred on a " &
"concurrent signal asg",
correct ) ;
st_enum1_vector_select <= transport 4 ;
-- s_st_enum1_vector(highb-1 to highb-1) <=
-- c_st_enum1_vector_1(highb-1 to highb-1) after 100 ns ;
--
when 5
=> correct :=
correct and
s_st_enum1_vector(highb-1 to highb-1) =
c_st_enum1_vector_1(highb-1 to highb-1) and
(s_st_enum1_vector_savt + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00390" ,
"Old transactions were removed on a " &
"concurrent signal asg",
correct ) ;
st_enum1_vector_select <= transport 5 ;
-- s_st_enum1_vector(highb-1 to highb-1) <=
-- c_st_enum1_vector_2(highb-1 to highb-1) after 10 ns ,
-- c_st_enum1_vector_1(highb-1 to highb-1) after 20 ns ,
-- c_st_enum1_vector_2(highb-1 to highb-1) after 30 ns ,
-- c_st_enum1_vector_1(highb-1 to highb-1) after 40 ns ;
--
when 6
=> correct :=
correct and
s_st_enum1_vector(highb-1 to highb-1) =
c_st_enum1_vector_2(highb-1 to highb-1) and
(s_st_enum1_vector_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00390" ,
"One inertial transaction occurred on a " &
"concurrent signal asg",
correct ) ;
st_enum1_vector_select <= transport 6 ;
-- Last transaction above is marked
-- s_st_enum1_vector(highb-1 to highb-1) <=
-- c_st_enum1_vector_1(highb-1 to highb-1) after 40 ns ;
--
when 7
=> correct :=
correct and
s_st_enum1_vector(highb-1 to highb-1) =
c_st_enum1_vector_1(highb-1 to highb-1) and
(s_st_enum1_vector_savt + 30 ns) = Std.Standard.Now ;
--
when 8
=> correct :=
correct and
s_st_enum1_vector(highb-1 to highb-1) =
c_st_enum1_vector_1(highb-1 to highb-1) and
(s_st_enum1_vector_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00390" ,
"Inertial semantics check on a concurrent " &
"signal asg",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00390" ,
"Inertial semantics check on a concurrent " &
"signal asg",
false ) ;
--
end case ;
--
s_st_enum1_vector_savt <= transport Std.Standard.Now ;
chk_st_enum1_vector <= transport s_st_enum1_vector_cnt
after (1 us - Std.Standard.Now) ;
s_st_enum1_vector_cnt <= transport s_st_enum1_vector_cnt + 1 ;
wait until (not s_st_enum1_vector(highb-1 to highb-1)'Quiet) and
(s_st_enum1_vector_savt /= Std.Standard.Now) ;
--
end process CHG4 ;
--
PGEN_CHKP_4 :
process ( chk_st_enum1_vector )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P4" ,
"Inertial transactions completed entirely",
chk_st_enum1_vector = 8 ) ;
end if ;
end process PGEN_CHKP_4 ;
--
--
s_st_enum1_vector(highb-1 to highb-1) <=
c_st_enum1_vector_2(highb-1 to highb-1) after 10 ns,
c_st_enum1_vector_1(highb-1 to highb-1) after 20 ns
when st_enum1_vector_select = 1 else
--
c_st_enum1_vector_2(highb-1 to highb-1) after 10 ns ,
c_st_enum1_vector_1(highb-1 to highb-1) after 20 ns ,
c_st_enum1_vector_2(highb-1 to highb-1) after 30 ns ,
c_st_enum1_vector_1(highb-1 to highb-1) after 40 ns
when st_enum1_vector_select = 2 else
--
c_st_enum1_vector_1(highb-1 to highb-1) after 5 ns
when st_enum1_vector_select = 3 else
--
c_st_enum1_vector_1(highb-1 to highb-1) after 100 ns
when st_enum1_vector_select = 4 else
--
c_st_enum1_vector_2(highb-1 to highb-1) after 10 ns ,
c_st_enum1_vector_1(highb-1 to highb-1) after 20 ns ,
c_st_enum1_vector_2(highb-1 to highb-1) after 30 ns ,
c_st_enum1_vector_1(highb-1 to highb-1) after 40 ns
when st_enum1_vector_select = 5 else
--
-- Last transaction above is marked
c_st_enum1_vector_1(highb-1 to highb-1) after 40 ns ;
--
CHG5 :
process
variable correct : boolean ;
begin
case s_st_integer_vector_cnt is
when 0
=> null ;
-- s_st_integer_vector(lowb to highb-1) <=
-- c_st_integer_vector_2(lowb to highb-1) after 10 ns,
-- c_st_integer_vector_1(lowb to highb-1) after 20 ns ;
--
when 1
=> correct :=
s_st_integer_vector(lowb to highb-1) =
c_st_integer_vector_2(lowb to highb-1) and
(s_st_integer_vector_savt + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_integer_vector(lowb to highb-1) =
c_st_integer_vector_1(lowb to highb-1) and
(s_st_integer_vector_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00390.P5" ,
"Multi inertial transactions occurred on " &
"concurrent signal asg",
correct ) ;
--
st_integer_vector_select <= transport 2 ;
-- s_st_integer_vector(lowb to highb-1) <=
-- c_st_integer_vector_2(lowb to highb-1) after 10 ns ,
-- c_st_integer_vector_1(lowb to highb-1) after 20 ns ,
-- c_st_integer_vector_2(lowb to highb-1) after 30 ns ,
-- c_st_integer_vector_1(lowb to highb-1) after 40 ns ;
--
when 3
=> correct :=
s_st_integer_vector(lowb to highb-1) =
c_st_integer_vector_2(lowb to highb-1) and
(s_st_integer_vector_savt + 10 ns) = Std.Standard.Now ;
st_integer_vector_select <= transport 3 ;
-- s_st_integer_vector(lowb to highb-1) <=
-- c_st_integer_vector_1(lowb to highb-1) after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_integer_vector(lowb to highb-1) =
c_st_integer_vector_1(lowb to highb-1) and
(s_st_integer_vector_savt + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00390" ,
"One inertial transaction occurred on a " &
"concurrent signal asg",
correct ) ;
st_integer_vector_select <= transport 4 ;
-- s_st_integer_vector(lowb to highb-1) <=
-- c_st_integer_vector_1(lowb to highb-1) after 100 ns ;
--
when 5
=> correct :=
correct and
s_st_integer_vector(lowb to highb-1) =
c_st_integer_vector_1(lowb to highb-1) and
(s_st_integer_vector_savt + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00390" ,
"Old transactions were removed on a " &
"concurrent signal asg",
correct ) ;
st_integer_vector_select <= transport 5 ;
-- s_st_integer_vector(lowb to highb-1) <=
-- c_st_integer_vector_2(lowb to highb-1) after 10 ns ,
-- c_st_integer_vector_1(lowb to highb-1) after 20 ns ,
-- c_st_integer_vector_2(lowb to highb-1) after 30 ns ,
-- c_st_integer_vector_1(lowb to highb-1) after 40 ns ;
--
when 6
=> correct :=
correct and
s_st_integer_vector(lowb to highb-1) =
c_st_integer_vector_2(lowb to highb-1) and
(s_st_integer_vector_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00390" ,
"One inertial transaction occurred on a " &
"concurrent signal asg",
correct ) ;
st_integer_vector_select <= transport 6 ;
-- Last transaction above is marked
-- s_st_integer_vector(lowb to highb-1) <=
-- c_st_integer_vector_1(lowb to highb-1) after 40 ns ;
--
when 7
=> correct :=
correct and
s_st_integer_vector(lowb to highb-1) =
c_st_integer_vector_1(lowb to highb-1) and
(s_st_integer_vector_savt + 30 ns) = Std.Standard.Now ;
--
when 8
=> correct :=
correct and
s_st_integer_vector(lowb to highb-1) =
c_st_integer_vector_1(lowb to highb-1) and
(s_st_integer_vector_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00390" ,
"Inertial semantics check on a concurrent " &
"signal asg",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00390" ,
"Inertial semantics check on a concurrent " &
"signal asg",
false ) ;
--
end case ;
--
s_st_integer_vector_savt <= transport Std.Standard.Now ;
chk_st_integer_vector <= transport s_st_integer_vector_cnt
after (1 us - Std.Standard.Now) ;
s_st_integer_vector_cnt <= transport s_st_integer_vector_cnt + 1 ;
wait until (not s_st_integer_vector(lowb to highb-1)'Quiet) and
(s_st_integer_vector_savt /= Std.Standard.Now) ;
--
end process CHG5 ;
--
PGEN_CHKP_5 :
process ( chk_st_integer_vector )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P5" ,
"Inertial transactions completed entirely",
chk_st_integer_vector = 8 ) ;
end if ;
end process PGEN_CHKP_5 ;
--
--
s_st_integer_vector(lowb to highb-1) <=
c_st_integer_vector_2(lowb to highb-1) after 10 ns,
c_st_integer_vector_1(lowb to highb-1) after 20 ns
when st_integer_vector_select = 1 else
--
c_st_integer_vector_2(lowb to highb-1) after 10 ns ,
c_st_integer_vector_1(lowb to highb-1) after 20 ns ,
c_st_integer_vector_2(lowb to highb-1) after 30 ns ,
c_st_integer_vector_1(lowb to highb-1) after 40 ns
when st_integer_vector_select = 2 else
--
c_st_integer_vector_1(lowb to highb-1) after 5 ns
when st_integer_vector_select = 3 else
--
c_st_integer_vector_1(lowb to highb-1) after 100 ns
when st_integer_vector_select = 4 else
--
c_st_integer_vector_2(lowb to highb-1) after 10 ns ,
c_st_integer_vector_1(lowb to highb-1) after 20 ns ,
c_st_integer_vector_2(lowb to highb-1) after 30 ns ,
c_st_integer_vector_1(lowb to highb-1) after 40 ns
when st_integer_vector_select = 5 else
--
-- Last transaction above is marked
c_st_integer_vector_1(lowb to highb-1) after 40 ns ;
--
CHG6 :
process
variable correct : boolean ;
begin
case s_st_time_vector_cnt is
when 0
=> null ;
-- s_st_time_vector(lowb to highb-1) <=
-- c_st_time_vector_2(lowb to highb-1) after 10 ns,
-- c_st_time_vector_1(lowb to highb-1) after 20 ns ;
--
when 1
=> correct :=
s_st_time_vector(lowb to highb-1) =
c_st_time_vector_2(lowb to highb-1) and
(s_st_time_vector_savt + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_time_vector(lowb to highb-1) =
c_st_time_vector_1(lowb to highb-1) and
(s_st_time_vector_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00390.P6" ,
"Multi inertial transactions occurred on " &
"concurrent signal asg",
correct ) ;
--
st_time_vector_select <= transport 2 ;
-- s_st_time_vector(lowb to highb-1) <=
-- c_st_time_vector_2(lowb to highb-1) after 10 ns ,
-- c_st_time_vector_1(lowb to highb-1) after 20 ns ,
-- c_st_time_vector_2(lowb to highb-1) after 30 ns ,
-- c_st_time_vector_1(lowb to highb-1) after 40 ns ;
--
when 3
=> correct :=
s_st_time_vector(lowb to highb-1) =
c_st_time_vector_2(lowb to highb-1) and
(s_st_time_vector_savt + 10 ns) = Std.Standard.Now ;
st_time_vector_select <= transport 3 ;
-- s_st_time_vector(lowb to highb-1) <=
-- c_st_time_vector_1(lowb to highb-1) after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_time_vector(lowb to highb-1) =
c_st_time_vector_1(lowb to highb-1) and
(s_st_time_vector_savt + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00390" ,
"One inertial transaction occurred on a " &
"concurrent signal asg",
correct ) ;
st_time_vector_select <= transport 4 ;
-- s_st_time_vector(lowb to highb-1) <=
-- c_st_time_vector_1(lowb to highb-1) after 100 ns ;
--
when 5
=> correct :=
correct and
s_st_time_vector(lowb to highb-1) =
c_st_time_vector_1(lowb to highb-1) and
(s_st_time_vector_savt + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00390" ,
"Old transactions were removed on a " &
"concurrent signal asg",
correct ) ;
st_time_vector_select <= transport 5 ;
-- s_st_time_vector(lowb to highb-1) <=
-- c_st_time_vector_2(lowb to highb-1) after 10 ns ,
-- c_st_time_vector_1(lowb to highb-1) after 20 ns ,
-- c_st_time_vector_2(lowb to highb-1) after 30 ns ,
-- c_st_time_vector_1(lowb to highb-1) after 40 ns ;
--
when 6
=> correct :=
correct and
s_st_time_vector(lowb to highb-1) =
c_st_time_vector_2(lowb to highb-1) and
(s_st_time_vector_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00390" ,
"One inertial transaction occurred on a " &
"concurrent signal asg",
correct ) ;
st_time_vector_select <= transport 6 ;
-- Last transaction above is marked
-- s_st_time_vector(lowb to highb-1) <=
-- c_st_time_vector_1(lowb to highb-1) after 40 ns ;
--
when 7
=> correct :=
correct and
s_st_time_vector(lowb to highb-1) =
c_st_time_vector_1(lowb to highb-1) and
(s_st_time_vector_savt + 30 ns) = Std.Standard.Now ;
--
when 8
=> correct :=
correct and
s_st_time_vector(lowb to highb-1) =
c_st_time_vector_1(lowb to highb-1) and
(s_st_time_vector_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00390" ,
"Inertial semantics check on a concurrent " &
"signal asg",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00390" ,
"Inertial semantics check on a concurrent " &
"signal asg",
false ) ;
--
end case ;
--
s_st_time_vector_savt <= transport Std.Standard.Now ;
chk_st_time_vector <= transport s_st_time_vector_cnt
after (1 us - Std.Standard.Now) ;
s_st_time_vector_cnt <= transport s_st_time_vector_cnt + 1 ;
wait until (not s_st_time_vector(lowb to highb-1)'Quiet) and
(s_st_time_vector_savt /= Std.Standard.Now) ;
--
end process CHG6 ;
--
PGEN_CHKP_6 :
process ( chk_st_time_vector )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P6" ,
"Inertial transactions completed entirely",
chk_st_time_vector = 8 ) ;
end if ;
end process PGEN_CHKP_6 ;
--
--
s_st_time_vector(lowb to highb-1) <=
c_st_time_vector_2(lowb to highb-1) after 10 ns,
c_st_time_vector_1(lowb to highb-1) after 20 ns
when st_time_vector_select = 1 else
--
c_st_time_vector_2(lowb to highb-1) after 10 ns ,
c_st_time_vector_1(lowb to highb-1) after 20 ns ,
c_st_time_vector_2(lowb to highb-1) after 30 ns ,
c_st_time_vector_1(lowb to highb-1) after 40 ns
when st_time_vector_select = 2 else
--
c_st_time_vector_1(lowb to highb-1) after 5 ns
when st_time_vector_select = 3 else
--
c_st_time_vector_1(lowb to highb-1) after 100 ns
when st_time_vector_select = 4 else
--
c_st_time_vector_2(lowb to highb-1) after 10 ns ,
c_st_time_vector_1(lowb to highb-1) after 20 ns ,
c_st_time_vector_2(lowb to highb-1) after 30 ns ,
c_st_time_vector_1(lowb to highb-1) after 40 ns
when st_time_vector_select = 5 else
--
-- Last transaction above is marked
c_st_time_vector_1(lowb to highb-1) after 40 ns ;
--
CHG7 :
process
variable correct : boolean ;
begin
case s_st_real_vector_cnt is
when 0
=> null ;
-- s_st_real_vector(highb-1 to highb-1) <=
-- c_st_real_vector_2(highb-1 to highb-1) after 10 ns,
-- c_st_real_vector_1(highb-1 to highb-1) after 20 ns ;
--
when 1
=> correct :=
s_st_real_vector(highb-1 to highb-1) =
c_st_real_vector_2(highb-1 to highb-1) and
(s_st_real_vector_savt + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_real_vector(highb-1 to highb-1) =
c_st_real_vector_1(highb-1 to highb-1) and
(s_st_real_vector_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00390.P7" ,
"Multi inertial transactions occurred on " &
"concurrent signal asg",
correct ) ;
--
st_real_vector_select <= transport 2 ;
-- s_st_real_vector(highb-1 to highb-1) <=
-- c_st_real_vector_2(highb-1 to highb-1) after 10 ns ,
-- c_st_real_vector_1(highb-1 to highb-1) after 20 ns ,
-- c_st_real_vector_2(highb-1 to highb-1) after 30 ns ,
-- c_st_real_vector_1(highb-1 to highb-1) after 40 ns ;
--
when 3
=> correct :=
s_st_real_vector(highb-1 to highb-1) =
c_st_real_vector_2(highb-1 to highb-1) and
(s_st_real_vector_savt + 10 ns) = Std.Standard.Now ;
st_real_vector_select <= transport 3 ;
-- s_st_real_vector(highb-1 to highb-1) <=
-- c_st_real_vector_1(highb-1 to highb-1) after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_real_vector(highb-1 to highb-1) =
c_st_real_vector_1(highb-1 to highb-1) and
(s_st_real_vector_savt + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00390" ,
"One inertial transaction occurred on a " &
"concurrent signal asg",
correct ) ;
st_real_vector_select <= transport 4 ;
-- s_st_real_vector(highb-1 to highb-1) <=
-- c_st_real_vector_1(highb-1 to highb-1) after 100 ns ;
--
when 5
=> correct :=
correct and
s_st_real_vector(highb-1 to highb-1) =
c_st_real_vector_1(highb-1 to highb-1) and
(s_st_real_vector_savt + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00390" ,
"Old transactions were removed on a " &
"concurrent signal asg",
correct ) ;
st_real_vector_select <= transport 5 ;
-- s_st_real_vector(highb-1 to highb-1) <=
-- c_st_real_vector_2(highb-1 to highb-1) after 10 ns ,
-- c_st_real_vector_1(highb-1 to highb-1) after 20 ns ,
-- c_st_real_vector_2(highb-1 to highb-1) after 30 ns ,
-- c_st_real_vector_1(highb-1 to highb-1) after 40 ns ;
--
when 6
=> correct :=
correct and
s_st_real_vector(highb-1 to highb-1) =
c_st_real_vector_2(highb-1 to highb-1) and
(s_st_real_vector_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00390" ,
"One inertial transaction occurred on a " &
"concurrent signal asg",
correct ) ;
st_real_vector_select <= transport 6 ;
-- Last transaction above is marked
-- s_st_real_vector(highb-1 to highb-1) <=
-- c_st_real_vector_1(highb-1 to highb-1) after 40 ns ;
--
when 7
=> correct :=
correct and
s_st_real_vector(highb-1 to highb-1) =
c_st_real_vector_1(highb-1 to highb-1) and
(s_st_real_vector_savt + 30 ns) = Std.Standard.Now ;
--
when 8
=> correct :=
correct and
s_st_real_vector(highb-1 to highb-1) =
c_st_real_vector_1(highb-1 to highb-1) and
(s_st_real_vector_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00390" ,
"Inertial semantics check on a concurrent " &
"signal asg",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00390" ,
"Inertial semantics check on a concurrent " &
"signal asg",
false ) ;
--
end case ;
--
s_st_real_vector_savt <= transport Std.Standard.Now ;
chk_st_real_vector <= transport s_st_real_vector_cnt
after (1 us - Std.Standard.Now) ;
s_st_real_vector_cnt <= transport s_st_real_vector_cnt + 1 ;
wait until (not s_st_real_vector(highb-1 to highb-1)'Quiet) and
(s_st_real_vector_savt /= Std.Standard.Now) ;
--
end process CHG7 ;
--
PGEN_CHKP_7 :
process ( chk_st_real_vector )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P7" ,
"Inertial transactions completed entirely",
chk_st_real_vector = 8 ) ;
end if ;
end process PGEN_CHKP_7 ;
--
--
s_st_real_vector(highb-1 to highb-1) <=
c_st_real_vector_2(highb-1 to highb-1) after 10 ns,
c_st_real_vector_1(highb-1 to highb-1) after 20 ns
when st_real_vector_select = 1 else
--
c_st_real_vector_2(highb-1 to highb-1) after 10 ns ,
c_st_real_vector_1(highb-1 to highb-1) after 20 ns ,
c_st_real_vector_2(highb-1 to highb-1) after 30 ns ,
c_st_real_vector_1(highb-1 to highb-1) after 40 ns
when st_real_vector_select = 2 else
--
c_st_real_vector_1(highb-1 to highb-1) after 5 ns
when st_real_vector_select = 3 else
--
c_st_real_vector_1(highb-1 to highb-1) after 100 ns
when st_real_vector_select = 4 else
--
c_st_real_vector_2(highb-1 to highb-1) after 10 ns ,
c_st_real_vector_1(highb-1 to highb-1) after 20 ns ,
c_st_real_vector_2(highb-1 to highb-1) after 30 ns ,
c_st_real_vector_1(highb-1 to highb-1) after 40 ns
when st_real_vector_select = 5 else
--
-- Last transaction above is marked
c_st_real_vector_1(highb-1 to highb-1) after 40 ns ;
--
CHG8 :
process
variable correct : boolean ;
begin
case s_st_rec1_vector_cnt is
when 0
=> null ;
-- s_st_rec1_vector(highb-1 to highb-1) <=
-- c_st_rec1_vector_2(highb-1 to highb-1) after 10 ns,
-- c_st_rec1_vector_1(highb-1 to highb-1) after 20 ns ;
--
when 1
=> correct :=
s_st_rec1_vector(highb-1 to highb-1) =
c_st_rec1_vector_2(highb-1 to highb-1) and
(s_st_rec1_vector_savt + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_rec1_vector(highb-1 to highb-1) =
c_st_rec1_vector_1(highb-1 to highb-1) and
(s_st_rec1_vector_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00390.P8" ,
"Multi inertial transactions occurred on " &
"concurrent signal asg",
correct ) ;
--
st_rec1_vector_select <= transport 2 ;
-- s_st_rec1_vector(highb-1 to highb-1) <=
-- c_st_rec1_vector_2(highb-1 to highb-1) after 10 ns ,
-- c_st_rec1_vector_1(highb-1 to highb-1) after 20 ns ,
-- c_st_rec1_vector_2(highb-1 to highb-1) after 30 ns ,
-- c_st_rec1_vector_1(highb-1 to highb-1) after 40 ns ;
--
when 3
=> correct :=
s_st_rec1_vector(highb-1 to highb-1) =
c_st_rec1_vector_2(highb-1 to highb-1) and
(s_st_rec1_vector_savt + 10 ns) = Std.Standard.Now ;
st_rec1_vector_select <= transport 3 ;
-- s_st_rec1_vector(highb-1 to highb-1) <=
-- c_st_rec1_vector_1(highb-1 to highb-1) after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_rec1_vector(highb-1 to highb-1) =
c_st_rec1_vector_1(highb-1 to highb-1) and
(s_st_rec1_vector_savt + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00390" ,
"One inertial transaction occurred on a " &
"concurrent signal asg",
correct ) ;
st_rec1_vector_select <= transport 4 ;
-- s_st_rec1_vector(highb-1 to highb-1) <=
-- c_st_rec1_vector_1(highb-1 to highb-1) after 100 ns ;
--
when 5
=> correct :=
correct and
s_st_rec1_vector(highb-1 to highb-1) =
c_st_rec1_vector_1(highb-1 to highb-1) and
(s_st_rec1_vector_savt + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00390" ,
"Old transactions were removed on a " &
"concurrent signal asg",
correct ) ;
st_rec1_vector_select <= transport 5 ;
-- s_st_rec1_vector(highb-1 to highb-1) <=
-- c_st_rec1_vector_2(highb-1 to highb-1) after 10 ns ,
-- c_st_rec1_vector_1(highb-1 to highb-1) after 20 ns ,
-- c_st_rec1_vector_2(highb-1 to highb-1) after 30 ns ,
-- c_st_rec1_vector_1(highb-1 to highb-1) after 40 ns ;
--
when 6
=> correct :=
correct and
s_st_rec1_vector(highb-1 to highb-1) =
c_st_rec1_vector_2(highb-1 to highb-1) and
(s_st_rec1_vector_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00390" ,
"One inertial transaction occurred on a " &
"concurrent signal asg",
correct ) ;
st_rec1_vector_select <= transport 6 ;
-- Last transaction above is marked
-- s_st_rec1_vector(highb-1 to highb-1) <=
-- c_st_rec1_vector_1(highb-1 to highb-1) after 40 ns ;
--
when 7
=> correct :=
correct and
s_st_rec1_vector(highb-1 to highb-1) =
c_st_rec1_vector_1(highb-1 to highb-1) and
(s_st_rec1_vector_savt + 30 ns) = Std.Standard.Now ;
--
when 8
=> correct :=
correct and
s_st_rec1_vector(highb-1 to highb-1) =
c_st_rec1_vector_1(highb-1 to highb-1) and
(s_st_rec1_vector_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00390" ,
"Inertial semantics check on a concurrent " &
"signal asg",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00390" ,
"Inertial semantics check on a concurrent " &
"signal asg",
false ) ;
--
end case ;
--
s_st_rec1_vector_savt <= transport Std.Standard.Now ;
chk_st_rec1_vector <= transport s_st_rec1_vector_cnt
after (1 us - Std.Standard.Now) ;
s_st_rec1_vector_cnt <= transport s_st_rec1_vector_cnt + 1 ;
wait until (not s_st_rec1_vector(highb-1 to highb-1)'Quiet) and
(s_st_rec1_vector_savt /= Std.Standard.Now) ;
--
end process CHG8 ;
--
PGEN_CHKP_8 :
process ( chk_st_rec1_vector )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P8" ,
"Inertial transactions completed entirely",
chk_st_rec1_vector = 8 ) ;
end if ;
end process PGEN_CHKP_8 ;
--
--
s_st_rec1_vector(highb-1 to highb-1) <=
c_st_rec1_vector_2(highb-1 to highb-1) after 10 ns,
c_st_rec1_vector_1(highb-1 to highb-1) after 20 ns
when st_rec1_vector_select = 1 else
--
c_st_rec1_vector_2(highb-1 to highb-1) after 10 ns ,
c_st_rec1_vector_1(highb-1 to highb-1) after 20 ns ,
c_st_rec1_vector_2(highb-1 to highb-1) after 30 ns ,
c_st_rec1_vector_1(highb-1 to highb-1) after 40 ns
when st_rec1_vector_select = 2 else
--
c_st_rec1_vector_1(highb-1 to highb-1) after 5 ns
when st_rec1_vector_select = 3 else
--
c_st_rec1_vector_1(highb-1 to highb-1) after 100 ns
when st_rec1_vector_select = 4 else
--
c_st_rec1_vector_2(highb-1 to highb-1) after 10 ns ,
c_st_rec1_vector_1(highb-1 to highb-1) after 20 ns ,
c_st_rec1_vector_2(highb-1 to highb-1) after 30 ns ,
c_st_rec1_vector_1(highb-1 to highb-1) after 40 ns
when st_rec1_vector_select = 5 else
--
-- Last transaction above is marked
c_st_rec1_vector_1(highb-1 to highb-1) after 40 ns ;
--
CHG9 :
process
variable correct : boolean ;
begin
case s_st_arr2_vector_cnt is
when 0
=> null ;
-- s_st_arr2_vector(lowb to highb-1) <=
-- c_st_arr2_vector_2(lowb to highb-1) after 10 ns,
-- c_st_arr2_vector_1(lowb to highb-1) after 20 ns ;
--
when 1
=> correct :=
s_st_arr2_vector(lowb to highb-1) =
c_st_arr2_vector_2(lowb to highb-1) and
(s_st_arr2_vector_savt + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_arr2_vector(lowb to highb-1) =
c_st_arr2_vector_1(lowb to highb-1) and
(s_st_arr2_vector_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00390.P9" ,
"Multi inertial transactions occurred on " &
"concurrent signal asg",
correct ) ;
--
st_arr2_vector_select <= transport 2 ;
-- s_st_arr2_vector(lowb to highb-1) <=
-- c_st_arr2_vector_2(lowb to highb-1) after 10 ns ,
-- c_st_arr2_vector_1(lowb to highb-1) after 20 ns ,
-- c_st_arr2_vector_2(lowb to highb-1) after 30 ns ,
-- c_st_arr2_vector_1(lowb to highb-1) after 40 ns ;
--
when 3
=> correct :=
s_st_arr2_vector(lowb to highb-1) =
c_st_arr2_vector_2(lowb to highb-1) and
(s_st_arr2_vector_savt + 10 ns) = Std.Standard.Now ;
st_arr2_vector_select <= transport 3 ;
-- s_st_arr2_vector(lowb to highb-1) <=
-- c_st_arr2_vector_1(lowb to highb-1) after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_arr2_vector(lowb to highb-1) =
c_st_arr2_vector_1(lowb to highb-1) and
(s_st_arr2_vector_savt + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00390" ,
"One inertial transaction occurred on a " &
"concurrent signal asg",
correct ) ;
st_arr2_vector_select <= transport 4 ;
-- s_st_arr2_vector(lowb to highb-1) <=
-- c_st_arr2_vector_1(lowb to highb-1) after 100 ns ;
--
when 5
=> correct :=
correct and
s_st_arr2_vector(lowb to highb-1) =
c_st_arr2_vector_1(lowb to highb-1) and
(s_st_arr2_vector_savt + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00390" ,
"Old transactions were removed on a " &
"concurrent signal asg",
correct ) ;
st_arr2_vector_select <= transport 5 ;
-- s_st_arr2_vector(lowb to highb-1) <=
-- c_st_arr2_vector_2(lowb to highb-1) after 10 ns ,
-- c_st_arr2_vector_1(lowb to highb-1) after 20 ns ,
-- c_st_arr2_vector_2(lowb to highb-1) after 30 ns ,
-- c_st_arr2_vector_1(lowb to highb-1) after 40 ns ;
--
when 6
=> correct :=
correct and
s_st_arr2_vector(lowb to highb-1) =
c_st_arr2_vector_2(lowb to highb-1) and
(s_st_arr2_vector_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00390" ,
"One inertial transaction occurred on a " &
"concurrent signal asg",
correct ) ;
st_arr2_vector_select <= transport 6 ;
-- Last transaction above is marked
-- s_st_arr2_vector(lowb to highb-1) <=
-- c_st_arr2_vector_1(lowb to highb-1) after 40 ns ;
--
when 7
=> correct :=
correct and
s_st_arr2_vector(lowb to highb-1) =
c_st_arr2_vector_1(lowb to highb-1) and
(s_st_arr2_vector_savt + 30 ns) = Std.Standard.Now ;
--
when 8
=> correct :=
correct and
s_st_arr2_vector(lowb to highb-1) =
c_st_arr2_vector_1(lowb to highb-1) and
(s_st_arr2_vector_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00390" ,
"Inertial semantics check on a concurrent " &
"signal asg",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00390" ,
"Inertial semantics check on a concurrent " &
"signal asg",
false ) ;
--
end case ;
--
s_st_arr2_vector_savt <= transport Std.Standard.Now ;
chk_st_arr2_vector <= transport s_st_arr2_vector_cnt
after (1 us - Std.Standard.Now) ;
s_st_arr2_vector_cnt <= transport s_st_arr2_vector_cnt + 1 ;
wait until (not s_st_arr2_vector(lowb to highb-1)'Quiet) and
(s_st_arr2_vector_savt /= Std.Standard.Now) ;
--
end process CHG9 ;
--
PGEN_CHKP_9 :
process ( chk_st_arr2_vector )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P9" ,
"Inertial transactions completed entirely",
chk_st_arr2_vector = 8 ) ;
end if ;
end process PGEN_CHKP_9 ;
--
--
s_st_arr2_vector(lowb to highb-1) <=
c_st_arr2_vector_2(lowb to highb-1) after 10 ns,
c_st_arr2_vector_1(lowb to highb-1) after 20 ns
when st_arr2_vector_select = 1 else
--
c_st_arr2_vector_2(lowb to highb-1) after 10 ns ,
c_st_arr2_vector_1(lowb to highb-1) after 20 ns ,
c_st_arr2_vector_2(lowb to highb-1) after 30 ns ,
c_st_arr2_vector_1(lowb to highb-1) after 40 ns
when st_arr2_vector_select = 2 else
--
c_st_arr2_vector_1(lowb to highb-1) after 5 ns
when st_arr2_vector_select = 3 else
--
c_st_arr2_vector_1(lowb to highb-1) after 100 ns
when st_arr2_vector_select = 4 else
--
c_st_arr2_vector_2(lowb to highb-1) after 10 ns ,
c_st_arr2_vector_1(lowb to highb-1) after 20 ns ,
c_st_arr2_vector_2(lowb to highb-1) after 30 ns ,
c_st_arr2_vector_1(lowb to highb-1) after 40 ns
when st_arr2_vector_select = 5 else
--
-- Last transaction above is marked
c_st_arr2_vector_1(lowb to highb-1) after 40 ns ;
--
end ARCH00390 ;
--
--
use WORK.STANDARD_TYPES.all ;
entity ENT00390_Test_Bench is
end ENT00390_Test_Bench ;
--
--
architecture ARCH00390_Test_Bench of ENT00390_Test_Bench is
begin
L1:
block
component UUT
end component ;
--
for CIS1 : UUT use entity WORK.ENT00390 ( ARCH00390 ) ;
begin
CIS1 : UUT
;
end block L1 ;
end ARCH00390_Test_Bench ;
| gpl-3.0 | 21ddc9a7ee75996ac058ee6ccad0ebeb | 0.531473 | 3.40176 | false | false | false | false |
grwlf/vsim | vhdl_ct/ct00298.vhd | 1 | 8,181 | -- NEED RESULT: ARCH00298: Dynamic boolean short circuiting results passed
-------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
-------------------------------------------------------------------------------
--
-- TEST NAME:
--
-- CT00298
--
-- AUTHOR:
--
-- A. Wilmot
--
-- TEST OBJECTIVES:
--
-- 7.2.1 (6)
-- 7.2.1 (7)
--
-- DESIGN UNIT ORDERING:
--
-- E00000(ARCH00298)
-- ENT00298_Test_Bench(ARCH00298_Test_Bench)
--
-- REVISION HISTORY:
--
-- 24-JUL-1987 - initial revision
--
-- NOTES:
--
-- self-checking
--
use WORK.STANDARD_TYPES.all ;
architecture ARCH00298 of E00000 is
begin
P00298 :
process
variable vboolean, boolean0, boolean1 : boolean ;
variable bool : boolean := true ;
function do_not_evaluate return boolean is
begin
test_report ( "ARCH00298" ,
"Dynamic boolean short circuiting correct" ,
false ) ;
return false ;
end do_not_evaluate ;
begin
boolean0 := false ;
boolean1 := true ;
vboolean := boolean0 and (do_not_evaluate and do_not_evaluate) ;
bool := bool and vboolean = false ;
vboolean := (boolean0 and do_not_evaluate) and do_not_evaluate ;
bool := bool and vboolean = false ;
vboolean := boolean1 and (boolean0 and do_not_evaluate) ;
bool := bool and vboolean = false ;
vboolean := (boolean1 and boolean0) and do_not_evaluate ;
bool := bool and vboolean = false ;
vboolean := boolean1 and (boolean1 and boolean0) ;
bool := bool and vboolean = false ;
vboolean := (boolean1 and boolean1) and boolean0 ;
bool := bool and vboolean = false ;
vboolean := boolean1 and (boolean1 and boolean1) ;
bool := bool and vboolean = true ;
vboolean := (boolean1 and boolean1) and boolean1 ;
bool := bool and vboolean = true ;
vboolean := boolean0 or (boolean0 or boolean0) ;
bool := bool and vboolean = false ;
vboolean := (boolean0 or boolean0) or boolean0 ;
bool := bool and vboolean = false ;
vboolean := boolean0 or (boolean0 or boolean1) ;
bool := bool and vboolean = true ;
vboolean := (boolean0 or boolean0) or boolean1 ;
bool := bool and vboolean = true ;
vboolean := boolean0 or (boolean1 or do_not_evaluate) ;
bool := bool and vboolean = true ;
vboolean := (boolean0 or boolean1) or do_not_evaluate ;
bool := bool and vboolean = true ;
vboolean := boolean1 or (do_not_evaluate or do_not_evaluate) ;
bool := bool and vboolean = true ;
vboolean := (boolean1 or do_not_evaluate) or do_not_evaluate ;
bool := bool and vboolean = true ;
vboolean := boolean0 or (boolean0 and do_not_evaluate) ;
bool := bool and vboolean = false ;
vboolean := (boolean0 or boolean0) and do_not_evaluate ;
bool := bool and vboolean = false ;
vboolean := boolean0 or (boolean1 and boolean0) ;
bool := bool and vboolean = false ;
vboolean := (boolean0 or boolean1) and boolean0 ;
bool := bool and vboolean = false ;
vboolean := boolean0 or (boolean1 and boolean1) ;
bool := bool and vboolean = true ;
vboolean := (boolean0 or boolean1) and boolean1 ;
bool := bool and vboolean = true ;
vboolean := boolean1 or (do_not_evaluate and do_not_evaluate) ;
bool := bool and vboolean = true ;
vboolean := (boolean1 or do_not_evaluate) and boolean0 ;
bool := bool and vboolean = false ;
vboolean := (boolean1 or do_not_evaluate) and boolean1 ;
bool := bool and vboolean = true ;
vboolean := boolean0 and (do_not_evaluate or do_not_evaluate) ;
bool := bool and vboolean = false ;
vboolean := (boolean0 and do_not_evaluate) or boolean0 ;
bool := bool and vboolean = false ;
vboolean := (boolean0 and do_not_evaluate) or boolean1 ;
bool := bool and vboolean = true ;
vboolean := boolean1 and (boolean0 or boolean0) ;
bool := bool and vboolean = false ;
vboolean := (boolean1 and boolean0) or boolean0 ;
bool := bool and vboolean = false ;
vboolean := boolean1 and (boolean0 or boolean1) ;
bool := bool and vboolean = true ;
vboolean := (boolean1 and boolean0) or boolean1 ;
bool := bool and vboolean = true ;
vboolean := boolean1 and (boolean1 or do_not_evaluate) ;
bool := bool and vboolean = true ;
vboolean := (boolean1 and boolean1) or do_not_evaluate ;
bool := bool and vboolean = true ;
vboolean := boolean0 nand (do_not_evaluate nand do_not_evaluate) ;
bool := bool and vboolean = true ;
vboolean := boolean1 nand (boolean0 nand do_not_evaluate) ;
bool := bool and vboolean = false ;
vboolean := boolean1 nand (boolean1 nand boolean0) ;
bool := bool and vboolean = false ;
vboolean := (boolean1 nand boolean1) nand boolean0 ;
bool := bool and vboolean = true ;
vboolean := boolean1 nand (boolean1 nand boolean1) ;
bool := bool and vboolean = true ;
vboolean := (boolean1 nand boolean1) nand boolean1 ;
bool := bool and vboolean = true ;
vboolean := boolean0 nor (boolean0 nor boolean0) ;
bool := bool and vboolean = false ;
vboolean := (boolean0 nor boolean0) nor boolean0 ;
bool := bool and vboolean = false ;
vboolean := boolean0 nor (boolean0 nor boolean1) ;
bool := bool and vboolean = true ;
vboolean := (boolean0 nor boolean0) nor boolean1 ;
bool := bool and vboolean = false ;
vboolean := boolean0 nor (boolean1 nor do_not_evaluate) ;
bool := bool and vboolean = true ;
vboolean := boolean0 nor (boolean0 nand do_not_evaluate) ;
bool := bool and vboolean = false ;
vboolean := boolean0 nor (boolean1 nand boolean0) ;
bool := bool and vboolean = false ;
vboolean := (boolean0 nor boolean1) nand boolean0 ;
bool := bool and vboolean = true ;
vboolean := boolean0 nor (boolean1 nand boolean1) ;
bool := bool and vboolean = true ;
vboolean := (boolean0 nor boolean1) nand boolean1 ;
bool := bool and vboolean = true ;
vboolean := boolean1 nor (do_not_evaluate nand do_not_evaluate) ;
bool := bool and vboolean = false ;
vboolean := (boolean1 nor do_not_evaluate) nand boolean0 ;
bool := bool and vboolean = true ;
vboolean := (boolean1 nor do_not_evaluate) nand boolean1 ;
bool := bool and vboolean = true ;
vboolean := boolean0 nand (do_not_evaluate nor do_not_evaluate) ;
bool := bool and vboolean = true ;
vboolean := (boolean0 nand do_not_evaluate) nor boolean0 ;
bool := bool and vboolean = false ;
vboolean := (boolean0 nand do_not_evaluate) nor boolean1 ;
bool := bool and vboolean = false ;
vboolean := boolean1 nand (boolean0 nor boolean0) ;
bool := bool and vboolean = false ;
vboolean := (boolean1 nand boolean0) nor boolean0 ;
bool := bool and vboolean = false ;
vboolean := boolean1 nand (boolean0 nor boolean1) ;
bool := bool and vboolean = true ;
vboolean := (boolean1 nand boolean0) nor boolean1 ;
bool := bool and vboolean = false ;
vboolean := boolean1 nand (boolean1 nor do_not_evaluate) ;
bool := bool and vboolean = true ;
test_report ( "ARCH00298" ,
"Dynamic boolean short circuiting results" ,
bool ) ;
wait ;
end process P00298 ;
end ARCH00298 ;
entity ENT00298_Test_Bench is
end ENT00298_Test_Bench ;
architecture ARCH00298_Test_Bench of ENT00298_Test_Bench is
begin
L1:
block
component UUT
end component ;
for CIS1 : UUT use entity WORK.E00000 ( ARCH00298 ) ;
begin
CIS1 : UUT ;
end block L1 ;
end ARCH00298_Test_Bench ;
| gpl-3.0 | f3da17865985532ccf16b9c9760a3951 | 0.588437 | 3.899428 | false | false | false | false |
TWW12/lzw | final_project_sim/lzw/lzw.srcs/sources_1/ip/bram_2048_0/bram_2048_0_sim_netlist.vhdl | 1 | 60,755 | -- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1756540 Mon Jan 23 19:11:23 MST 2017
-- Date : Tue Apr 18 23:15:18 2017
-- Host : DESKTOP-I9J3TQJ running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode funcsim
-- X:/final_project_sim/lzw/lzw.srcs/sources_1/ip/bram_2048_0/bram_2048_0_sim_netlist.vhdl
-- Design : bram_2048_0
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7z020clg484-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity bram_2048_0_blk_mem_gen_prim_wrapper_init is
port (
douta : out STD_LOGIC_VECTOR ( 8 downto 0 );
clka : in STD_LOGIC;
ena : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 10 downto 0 );
dina : in STD_LOGIC_VECTOR ( 8 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of bram_2048_0_blk_mem_gen_prim_wrapper_init : entity is "blk_mem_gen_prim_wrapper_init";
end bram_2048_0_blk_mem_gen_prim_wrapper_init;
architecture STRUCTURE of bram_2048_0_blk_mem_gen_prim_wrapper_init is
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 15 downto 8 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 15 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 to 1 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute CLOCK_DOMAINS : string;
attribute CLOCK_DOMAINS of \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram\ : label is "COMMON";
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram\: unisim.vcomponents.RAMB18E1
generic map(
DOA_REG => 1,
DOB_REG => 0,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_00 => X"3F3D3B39373533312F2D2B29272523211F1D1B19171513110F0D0B0907050301",
INIT_01 => X"7F7D7B79777573716F6D6B69676563615F5D5B59575553514F4D4B4947454341",
INIT_02 => X"BFBDBBB9B7B5B3B1AFADABA9A7A5A3A19F9D9B99979593918F8D8B8987858381",
INIT_03 => X"FFFDFBF9F7F5F3F1EFEDEBE9E7E5E3E1DFDDDBD9D7D5D3D1CFCDCBC9C7C5C3C1",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"00000",
INIT_B => X"00000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "PERFORMANCE",
READ_WIDTH_A => 9,
READ_WIDTH_B => 9,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"00000",
SRVAL_B => X"00000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 9,
WRITE_WIDTH_B => 9
)
port map (
ADDRARDADDR(13 downto 3) => addra(10 downto 0),
ADDRARDADDR(2 downto 0) => B"000",
ADDRBWRADDR(13 downto 0) => B"00000000000000",
CLKARDCLK => clka,
CLKBWRCLK => clka,
DIADI(15 downto 8) => B"00000000",
DIADI(7 downto 0) => dina(7 downto 0),
DIBDI(15 downto 0) => B"0000000000000000",
DIPADIP(1) => '0',
DIPADIP(0) => dina(8),
DIPBDIP(1 downto 0) => B"00",
DOADO(15 downto 8) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_DOADO_UNCONNECTED\(15 downto 8),
DOADO(7 downto 0) => douta(7 downto 0),
DOBDO(15 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_DOBDO_UNCONNECTED\(15 downto 0),
DOPADOP(1) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_DOPADOP_UNCONNECTED\(1),
DOPADOP(0) => douta(8),
DOPBDOP(1 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_DOPBDOP_UNCONNECTED\(1 downto 0),
ENARDEN => ena,
ENBWREN => '0',
REGCEAREGCE => ena,
REGCEB => '0',
RSTRAMARSTRAM => '0',
RSTRAMB => '0',
RSTREGARSTREG => '0',
RSTREGB => '0',
WEA(1) => wea(0),
WEA(0) => wea(0),
WEBWE(3 downto 0) => B"0000"
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \bram_2048_0_blk_mem_gen_prim_wrapper_init__parameterized0\ is
port (
douta : out STD_LOGIC_VECTOR ( 10 downto 0 );
clka : in STD_LOGIC;
ena : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 10 downto 0 );
dina : in STD_LOGIC_VECTOR ( 10 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \bram_2048_0_blk_mem_gen_prim_wrapper_init__parameterized0\ : entity is "blk_mem_gen_prim_wrapper_init";
end \bram_2048_0_blk_mem_gen_prim_wrapper_init__parameterized0\;
architecture STRUCTURE of \bram_2048_0_blk_mem_gen_prim_wrapper_init__parameterized0\ is
signal \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_37\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_38\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_39\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_45\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_46\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_87\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_88\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 16 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute CLOCK_DOMAINS : string;
attribute CLOCK_DOMAINS of \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\ : label is "COMMON";
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 1,
DOB_REG => 0,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_40 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_41 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_42 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_43 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_44 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_45 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_46 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_47 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_48 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_49 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_50 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_51 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_52 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_53 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_54 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_55 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_56 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_57 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_58 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_59 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_60 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_61 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_62 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_63 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_64 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_65 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_66 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_67 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_68 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_69 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_70 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_71 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_72 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_73 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_74 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "PERFORMANCE",
READ_WIDTH_A => 18,
READ_WIDTH_B => 18,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 18,
WRITE_WIDTH_B => 18
)
port map (
ADDRARDADDR(15) => '1',
ADDRARDADDR(14 downto 4) => addra(10 downto 0),
ADDRARDADDR(3 downto 0) => B"1111",
ADDRBWRADDR(15 downto 0) => B"0000000000000000",
CASCADEINA => '0',
CASCADEINB => '0',
CASCADEOUTA => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => clka,
CLKBWRCLK => clka,
DBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\,
DIADI(31 downto 13) => B"0000000000000000000",
DIADI(12 downto 8) => dina(10 downto 6),
DIADI(7 downto 6) => B"00",
DIADI(5 downto 0) => dina(5 downto 0),
DIBDI(31 downto 0) => B"00000000000000000000000000000000",
DIPADIP(3 downto 0) => B"0000",
DIPBDIP(3 downto 0) => B"0000",
DOADO(31 downto 16) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\(31 downto 16),
DOADO(15) => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_37\,
DOADO(14) => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_38\,
DOADO(13) => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_39\,
DOADO(12 downto 8) => douta(10 downto 6),
DOADO(7) => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_45\,
DOADO(6) => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_46\,
DOADO(5 downto 0) => douta(5 downto 0),
DOBDO(31 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\(31 downto 0),
DOPADOP(3 downto 2) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\(3 downto 2),
DOPADOP(1) => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_87\,
DOPADOP(0) => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_88\,
DOPBDOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\(3 downto 0),
ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => ena,
ENBWREN => '0',
INJECTDBITERR => '0',
INJECTSBITERR => '0',
RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => ena,
REGCEB => '0',
RSTRAMARSTRAM => '0',
RSTRAMB => '0',
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\,
WEA(3) => wea(0),
WEA(2) => wea(0),
WEA(1) => wea(0),
WEA(0) => wea(0),
WEBWE(7 downto 0) => B"00000000"
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity bram_2048_0_blk_mem_gen_prim_width is
port (
douta : out STD_LOGIC_VECTOR ( 8 downto 0 );
clka : in STD_LOGIC;
ena : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 10 downto 0 );
dina : in STD_LOGIC_VECTOR ( 8 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of bram_2048_0_blk_mem_gen_prim_width : entity is "blk_mem_gen_prim_width";
end bram_2048_0_blk_mem_gen_prim_width;
architecture STRUCTURE of bram_2048_0_blk_mem_gen_prim_width is
begin
\prim_init.ram\: entity work.bram_2048_0_blk_mem_gen_prim_wrapper_init
port map (
addra(10 downto 0) => addra(10 downto 0),
clka => clka,
dina(8 downto 0) => dina(8 downto 0),
douta(8 downto 0) => douta(8 downto 0),
ena => ena,
wea(0) => wea(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \bram_2048_0_blk_mem_gen_prim_width__parameterized0\ is
port (
douta : out STD_LOGIC_VECTOR ( 10 downto 0 );
clka : in STD_LOGIC;
ena : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 10 downto 0 );
dina : in STD_LOGIC_VECTOR ( 10 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \bram_2048_0_blk_mem_gen_prim_width__parameterized0\ : entity is "blk_mem_gen_prim_width";
end \bram_2048_0_blk_mem_gen_prim_width__parameterized0\;
architecture STRUCTURE of \bram_2048_0_blk_mem_gen_prim_width__parameterized0\ is
begin
\prim_init.ram\: entity work.\bram_2048_0_blk_mem_gen_prim_wrapper_init__parameterized0\
port map (
addra(10 downto 0) => addra(10 downto 0),
clka => clka,
dina(10 downto 0) => dina(10 downto 0),
douta(10 downto 0) => douta(10 downto 0),
ena => ena,
wea(0) => wea(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity bram_2048_0_blk_mem_gen_generic_cstr is
port (
douta : out STD_LOGIC_VECTOR ( 19 downto 0 );
clka : in STD_LOGIC;
ena : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 10 downto 0 );
dina : in STD_LOGIC_VECTOR ( 19 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of bram_2048_0_blk_mem_gen_generic_cstr : entity is "blk_mem_gen_generic_cstr";
end bram_2048_0_blk_mem_gen_generic_cstr;
architecture STRUCTURE of bram_2048_0_blk_mem_gen_generic_cstr is
begin
\ramloop[0].ram.r\: entity work.bram_2048_0_blk_mem_gen_prim_width
port map (
addra(10 downto 0) => addra(10 downto 0),
clka => clka,
dina(8 downto 0) => dina(8 downto 0),
douta(8 downto 0) => douta(8 downto 0),
ena => ena,
wea(0) => wea(0)
);
\ramloop[1].ram.r\: entity work.\bram_2048_0_blk_mem_gen_prim_width__parameterized0\
port map (
addra(10 downto 0) => addra(10 downto 0),
clka => clka,
dina(10 downto 0) => dina(19 downto 9),
douta(10 downto 0) => douta(19 downto 9),
ena => ena,
wea(0) => wea(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity bram_2048_0_blk_mem_gen_top is
port (
douta : out STD_LOGIC_VECTOR ( 19 downto 0 );
clka : in STD_LOGIC;
ena : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 10 downto 0 );
dina : in STD_LOGIC_VECTOR ( 19 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of bram_2048_0_blk_mem_gen_top : entity is "blk_mem_gen_top";
end bram_2048_0_blk_mem_gen_top;
architecture STRUCTURE of bram_2048_0_blk_mem_gen_top is
begin
\valid.cstr\: entity work.bram_2048_0_blk_mem_gen_generic_cstr
port map (
addra(10 downto 0) => addra(10 downto 0),
clka => clka,
dina(19 downto 0) => dina(19 downto 0),
douta(19 downto 0) => douta(19 downto 0),
ena => ena,
wea(0) => wea(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity bram_2048_0_blk_mem_gen_v8_3_5_synth is
port (
douta : out STD_LOGIC_VECTOR ( 19 downto 0 );
clka : in STD_LOGIC;
ena : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 10 downto 0 );
dina : in STD_LOGIC_VECTOR ( 19 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of bram_2048_0_blk_mem_gen_v8_3_5_synth : entity is "blk_mem_gen_v8_3_5_synth";
end bram_2048_0_blk_mem_gen_v8_3_5_synth;
architecture STRUCTURE of bram_2048_0_blk_mem_gen_v8_3_5_synth is
begin
\gnbram.gnativebmg.native_blk_mem_gen\: entity work.bram_2048_0_blk_mem_gen_top
port map (
addra(10 downto 0) => addra(10 downto 0),
clka => clka,
dina(19 downto 0) => dina(19 downto 0),
douta(19 downto 0) => douta(19 downto 0),
ena => ena,
wea(0) => wea(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity bram_2048_0_blk_mem_gen_v8_3_5 is
port (
clka : in STD_LOGIC;
rsta : in STD_LOGIC;
ena : in STD_LOGIC;
regcea : in STD_LOGIC;
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
addra : in STD_LOGIC_VECTOR ( 10 downto 0 );
dina : in STD_LOGIC_VECTOR ( 19 downto 0 );
douta : out STD_LOGIC_VECTOR ( 19 downto 0 );
clkb : in STD_LOGIC;
rstb : in STD_LOGIC;
enb : in STD_LOGIC;
regceb : in STD_LOGIC;
web : in STD_LOGIC_VECTOR ( 0 to 0 );
addrb : in STD_LOGIC_VECTOR ( 10 downto 0 );
dinb : in STD_LOGIC_VECTOR ( 19 downto 0 );
doutb : out STD_LOGIC_VECTOR ( 19 downto 0 );
injectsbiterr : in STD_LOGIC;
injectdbiterr : in STD_LOGIC;
eccpipece : in STD_LOGIC;
sbiterr : out STD_LOGIC;
dbiterr : out STD_LOGIC;
rdaddrecc : out STD_LOGIC_VECTOR ( 10 downto 0 );
sleep : in STD_LOGIC;
deepsleep : in STD_LOGIC;
shutdown : in STD_LOGIC;
rsta_busy : out STD_LOGIC;
rstb_busy : out STD_LOGIC;
s_aclk : in STD_LOGIC;
s_aresetn : in STD_LOGIC;
s_axi_awid : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_awready : out STD_LOGIC;
s_axi_wdata : in STD_LOGIC_VECTOR ( 19 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_wlast : in STD_LOGIC;
s_axi_wvalid : in STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_bid : out STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_bvalid : out STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_arid : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arvalid : in STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_rid : out STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_rdata : out STD_LOGIC_VECTOR ( 19 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rlast : out STD_LOGIC;
s_axi_rvalid : out STD_LOGIC;
s_axi_rready : in STD_LOGIC;
s_axi_injectsbiterr : in STD_LOGIC;
s_axi_injectdbiterr : in STD_LOGIC;
s_axi_sbiterr : out STD_LOGIC;
s_axi_dbiterr : out STD_LOGIC;
s_axi_rdaddrecc : out STD_LOGIC_VECTOR ( 10 downto 0 )
);
attribute C_ADDRA_WIDTH : integer;
attribute C_ADDRA_WIDTH of bram_2048_0_blk_mem_gen_v8_3_5 : entity is 11;
attribute C_ADDRB_WIDTH : integer;
attribute C_ADDRB_WIDTH of bram_2048_0_blk_mem_gen_v8_3_5 : entity is 11;
attribute C_ALGORITHM : integer;
attribute C_ALGORITHM of bram_2048_0_blk_mem_gen_v8_3_5 : entity is 1;
attribute C_AXI_ID_WIDTH : integer;
attribute C_AXI_ID_WIDTH of bram_2048_0_blk_mem_gen_v8_3_5 : entity is 4;
attribute C_AXI_SLAVE_TYPE : integer;
attribute C_AXI_SLAVE_TYPE of bram_2048_0_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_AXI_TYPE : integer;
attribute C_AXI_TYPE of bram_2048_0_blk_mem_gen_v8_3_5 : entity is 1;
attribute C_BYTE_SIZE : integer;
attribute C_BYTE_SIZE of bram_2048_0_blk_mem_gen_v8_3_5 : entity is 9;
attribute C_COMMON_CLK : integer;
attribute C_COMMON_CLK of bram_2048_0_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_COUNT_18K_BRAM : string;
attribute C_COUNT_18K_BRAM of bram_2048_0_blk_mem_gen_v8_3_5 : entity is "1";
attribute C_COUNT_36K_BRAM : string;
attribute C_COUNT_36K_BRAM of bram_2048_0_blk_mem_gen_v8_3_5 : entity is "1";
attribute C_CTRL_ECC_ALGO : string;
attribute C_CTRL_ECC_ALGO of bram_2048_0_blk_mem_gen_v8_3_5 : entity is "NONE";
attribute C_DEFAULT_DATA : string;
attribute C_DEFAULT_DATA of bram_2048_0_blk_mem_gen_v8_3_5 : entity is "0";
attribute C_DISABLE_WARN_BHV_COLL : integer;
attribute C_DISABLE_WARN_BHV_COLL of bram_2048_0_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_DISABLE_WARN_BHV_RANGE : integer;
attribute C_DISABLE_WARN_BHV_RANGE of bram_2048_0_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_ELABORATION_DIR : string;
attribute C_ELABORATION_DIR of bram_2048_0_blk_mem_gen_v8_3_5 : entity is "./";
attribute C_ENABLE_32BIT_ADDRESS : integer;
attribute C_ENABLE_32BIT_ADDRESS of bram_2048_0_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_EN_DEEPSLEEP_PIN : integer;
attribute C_EN_DEEPSLEEP_PIN of bram_2048_0_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_EN_ECC_PIPE : integer;
attribute C_EN_ECC_PIPE of bram_2048_0_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_EN_RDADDRA_CHG : integer;
attribute C_EN_RDADDRA_CHG of bram_2048_0_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_EN_RDADDRB_CHG : integer;
attribute C_EN_RDADDRB_CHG of bram_2048_0_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_EN_SAFETY_CKT : integer;
attribute C_EN_SAFETY_CKT of bram_2048_0_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_EN_SHUTDOWN_PIN : integer;
attribute C_EN_SHUTDOWN_PIN of bram_2048_0_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_EN_SLEEP_PIN : integer;
attribute C_EN_SLEEP_PIN of bram_2048_0_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_EST_POWER_SUMMARY : string;
attribute C_EST_POWER_SUMMARY of bram_2048_0_blk_mem_gen_v8_3_5 : entity is "Estimated Power for IP : 3.9373 mW";
attribute C_FAMILY : string;
attribute C_FAMILY of bram_2048_0_blk_mem_gen_v8_3_5 : entity is "zynq";
attribute C_HAS_AXI_ID : integer;
attribute C_HAS_AXI_ID of bram_2048_0_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_HAS_ENA : integer;
attribute C_HAS_ENA of bram_2048_0_blk_mem_gen_v8_3_5 : entity is 1;
attribute C_HAS_ENB : integer;
attribute C_HAS_ENB of bram_2048_0_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_HAS_INJECTERR : integer;
attribute C_HAS_INJECTERR of bram_2048_0_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_HAS_MEM_OUTPUT_REGS_A : integer;
attribute C_HAS_MEM_OUTPUT_REGS_A of bram_2048_0_blk_mem_gen_v8_3_5 : entity is 1;
attribute C_HAS_MEM_OUTPUT_REGS_B : integer;
attribute C_HAS_MEM_OUTPUT_REGS_B of bram_2048_0_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_HAS_MUX_OUTPUT_REGS_A : integer;
attribute C_HAS_MUX_OUTPUT_REGS_A of bram_2048_0_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_HAS_MUX_OUTPUT_REGS_B : integer;
attribute C_HAS_MUX_OUTPUT_REGS_B of bram_2048_0_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_HAS_REGCEA : integer;
attribute C_HAS_REGCEA of bram_2048_0_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_HAS_REGCEB : integer;
attribute C_HAS_REGCEB of bram_2048_0_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_HAS_RSTA : integer;
attribute C_HAS_RSTA of bram_2048_0_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_HAS_RSTB : integer;
attribute C_HAS_RSTB of bram_2048_0_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_HAS_SOFTECC_INPUT_REGS_A : integer;
attribute C_HAS_SOFTECC_INPUT_REGS_A of bram_2048_0_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_HAS_SOFTECC_OUTPUT_REGS_B : integer;
attribute C_HAS_SOFTECC_OUTPUT_REGS_B of bram_2048_0_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_INITA_VAL : string;
attribute C_INITA_VAL of bram_2048_0_blk_mem_gen_v8_3_5 : entity is "0";
attribute C_INITB_VAL : string;
attribute C_INITB_VAL of bram_2048_0_blk_mem_gen_v8_3_5 : entity is "0";
attribute C_INIT_FILE : string;
attribute C_INIT_FILE of bram_2048_0_blk_mem_gen_v8_3_5 : entity is "bram_2048_0.mem";
attribute C_INIT_FILE_NAME : string;
attribute C_INIT_FILE_NAME of bram_2048_0_blk_mem_gen_v8_3_5 : entity is "bram_2048_0.mif";
attribute C_INTERFACE_TYPE : integer;
attribute C_INTERFACE_TYPE of bram_2048_0_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_LOAD_INIT_FILE : integer;
attribute C_LOAD_INIT_FILE of bram_2048_0_blk_mem_gen_v8_3_5 : entity is 1;
attribute C_MEM_TYPE : integer;
attribute C_MEM_TYPE of bram_2048_0_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_MUX_PIPELINE_STAGES : integer;
attribute C_MUX_PIPELINE_STAGES of bram_2048_0_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_PRIM_TYPE : integer;
attribute C_PRIM_TYPE of bram_2048_0_blk_mem_gen_v8_3_5 : entity is 1;
attribute C_READ_DEPTH_A : integer;
attribute C_READ_DEPTH_A of bram_2048_0_blk_mem_gen_v8_3_5 : entity is 2048;
attribute C_READ_DEPTH_B : integer;
attribute C_READ_DEPTH_B of bram_2048_0_blk_mem_gen_v8_3_5 : entity is 2048;
attribute C_READ_WIDTH_A : integer;
attribute C_READ_WIDTH_A of bram_2048_0_blk_mem_gen_v8_3_5 : entity is 20;
attribute C_READ_WIDTH_B : integer;
attribute C_READ_WIDTH_B of bram_2048_0_blk_mem_gen_v8_3_5 : entity is 20;
attribute C_RSTRAM_A : integer;
attribute C_RSTRAM_A of bram_2048_0_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_RSTRAM_B : integer;
attribute C_RSTRAM_B of bram_2048_0_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_RST_PRIORITY_A : string;
attribute C_RST_PRIORITY_A of bram_2048_0_blk_mem_gen_v8_3_5 : entity is "CE";
attribute C_RST_PRIORITY_B : string;
attribute C_RST_PRIORITY_B of bram_2048_0_blk_mem_gen_v8_3_5 : entity is "CE";
attribute C_SIM_COLLISION_CHECK : string;
attribute C_SIM_COLLISION_CHECK of bram_2048_0_blk_mem_gen_v8_3_5 : entity is "ALL";
attribute C_USE_BRAM_BLOCK : integer;
attribute C_USE_BRAM_BLOCK of bram_2048_0_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_USE_BYTE_WEA : integer;
attribute C_USE_BYTE_WEA of bram_2048_0_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_USE_BYTE_WEB : integer;
attribute C_USE_BYTE_WEB of bram_2048_0_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_USE_DEFAULT_DATA : integer;
attribute C_USE_DEFAULT_DATA of bram_2048_0_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_USE_ECC : integer;
attribute C_USE_ECC of bram_2048_0_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_USE_SOFTECC : integer;
attribute C_USE_SOFTECC of bram_2048_0_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_USE_URAM : integer;
attribute C_USE_URAM of bram_2048_0_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_WEA_WIDTH : integer;
attribute C_WEA_WIDTH of bram_2048_0_blk_mem_gen_v8_3_5 : entity is 1;
attribute C_WEB_WIDTH : integer;
attribute C_WEB_WIDTH of bram_2048_0_blk_mem_gen_v8_3_5 : entity is 1;
attribute C_WRITE_DEPTH_A : integer;
attribute C_WRITE_DEPTH_A of bram_2048_0_blk_mem_gen_v8_3_5 : entity is 2048;
attribute C_WRITE_DEPTH_B : integer;
attribute C_WRITE_DEPTH_B of bram_2048_0_blk_mem_gen_v8_3_5 : entity is 2048;
attribute C_WRITE_MODE_A : string;
attribute C_WRITE_MODE_A of bram_2048_0_blk_mem_gen_v8_3_5 : entity is "WRITE_FIRST";
attribute C_WRITE_MODE_B : string;
attribute C_WRITE_MODE_B of bram_2048_0_blk_mem_gen_v8_3_5 : entity is "WRITE_FIRST";
attribute C_WRITE_WIDTH_A : integer;
attribute C_WRITE_WIDTH_A of bram_2048_0_blk_mem_gen_v8_3_5 : entity is 20;
attribute C_WRITE_WIDTH_B : integer;
attribute C_WRITE_WIDTH_B of bram_2048_0_blk_mem_gen_v8_3_5 : entity is 20;
attribute C_XDEVICEFAMILY : string;
attribute C_XDEVICEFAMILY of bram_2048_0_blk_mem_gen_v8_3_5 : entity is "zynq";
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of bram_2048_0_blk_mem_gen_v8_3_5 : entity is "blk_mem_gen_v8_3_5";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of bram_2048_0_blk_mem_gen_v8_3_5 : entity is "yes";
end bram_2048_0_blk_mem_gen_v8_3_5;
architecture STRUCTURE of bram_2048_0_blk_mem_gen_v8_3_5 is
signal \<const0>\ : STD_LOGIC;
begin
dbiterr <= \<const0>\;
doutb(19) <= \<const0>\;
doutb(18) <= \<const0>\;
doutb(17) <= \<const0>\;
doutb(16) <= \<const0>\;
doutb(15) <= \<const0>\;
doutb(14) <= \<const0>\;
doutb(13) <= \<const0>\;
doutb(12) <= \<const0>\;
doutb(11) <= \<const0>\;
doutb(10) <= \<const0>\;
doutb(9) <= \<const0>\;
doutb(8) <= \<const0>\;
doutb(7) <= \<const0>\;
doutb(6) <= \<const0>\;
doutb(5) <= \<const0>\;
doutb(4) <= \<const0>\;
doutb(3) <= \<const0>\;
doutb(2) <= \<const0>\;
doutb(1) <= \<const0>\;
doutb(0) <= \<const0>\;
rdaddrecc(10) <= \<const0>\;
rdaddrecc(9) <= \<const0>\;
rdaddrecc(8) <= \<const0>\;
rdaddrecc(7) <= \<const0>\;
rdaddrecc(6) <= \<const0>\;
rdaddrecc(5) <= \<const0>\;
rdaddrecc(4) <= \<const0>\;
rdaddrecc(3) <= \<const0>\;
rdaddrecc(2) <= \<const0>\;
rdaddrecc(1) <= \<const0>\;
rdaddrecc(0) <= \<const0>\;
rsta_busy <= \<const0>\;
rstb_busy <= \<const0>\;
s_axi_arready <= \<const0>\;
s_axi_awready <= \<const0>\;
s_axi_bid(3) <= \<const0>\;
s_axi_bid(2) <= \<const0>\;
s_axi_bid(1) <= \<const0>\;
s_axi_bid(0) <= \<const0>\;
s_axi_bresp(1) <= \<const0>\;
s_axi_bresp(0) <= \<const0>\;
s_axi_bvalid <= \<const0>\;
s_axi_dbiterr <= \<const0>\;
s_axi_rdaddrecc(10) <= \<const0>\;
s_axi_rdaddrecc(9) <= \<const0>\;
s_axi_rdaddrecc(8) <= \<const0>\;
s_axi_rdaddrecc(7) <= \<const0>\;
s_axi_rdaddrecc(6) <= \<const0>\;
s_axi_rdaddrecc(5) <= \<const0>\;
s_axi_rdaddrecc(4) <= \<const0>\;
s_axi_rdaddrecc(3) <= \<const0>\;
s_axi_rdaddrecc(2) <= \<const0>\;
s_axi_rdaddrecc(1) <= \<const0>\;
s_axi_rdaddrecc(0) <= \<const0>\;
s_axi_rdata(19) <= \<const0>\;
s_axi_rdata(18) <= \<const0>\;
s_axi_rdata(17) <= \<const0>\;
s_axi_rdata(16) <= \<const0>\;
s_axi_rdata(15) <= \<const0>\;
s_axi_rdata(14) <= \<const0>\;
s_axi_rdata(13) <= \<const0>\;
s_axi_rdata(12) <= \<const0>\;
s_axi_rdata(11) <= \<const0>\;
s_axi_rdata(10) <= \<const0>\;
s_axi_rdata(9) <= \<const0>\;
s_axi_rdata(8) <= \<const0>\;
s_axi_rdata(7) <= \<const0>\;
s_axi_rdata(6) <= \<const0>\;
s_axi_rdata(5) <= \<const0>\;
s_axi_rdata(4) <= \<const0>\;
s_axi_rdata(3) <= \<const0>\;
s_axi_rdata(2) <= \<const0>\;
s_axi_rdata(1) <= \<const0>\;
s_axi_rdata(0) <= \<const0>\;
s_axi_rid(3) <= \<const0>\;
s_axi_rid(2) <= \<const0>\;
s_axi_rid(1) <= \<const0>\;
s_axi_rid(0) <= \<const0>\;
s_axi_rlast <= \<const0>\;
s_axi_rresp(1) <= \<const0>\;
s_axi_rresp(0) <= \<const0>\;
s_axi_rvalid <= \<const0>\;
s_axi_sbiterr <= \<const0>\;
s_axi_wready <= \<const0>\;
sbiterr <= \<const0>\;
GND: unisim.vcomponents.GND
port map (
G => \<const0>\
);
inst_blk_mem_gen: entity work.bram_2048_0_blk_mem_gen_v8_3_5_synth
port map (
addra(10 downto 0) => addra(10 downto 0),
clka => clka,
dina(19 downto 0) => dina(19 downto 0),
douta(19 downto 0) => douta(19 downto 0),
ena => ena,
wea(0) => wea(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity bram_2048_0 is
port (
clka : in STD_LOGIC;
ena : in STD_LOGIC;
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
addra : in STD_LOGIC_VECTOR ( 10 downto 0 );
dina : in STD_LOGIC_VECTOR ( 19 downto 0 );
douta : out STD_LOGIC_VECTOR ( 19 downto 0 )
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of bram_2048_0 : entity is true;
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of bram_2048_0 : entity is "bram_2048_0,blk_mem_gen_v8_3_5,{}";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of bram_2048_0 : entity is "yes";
attribute x_core_info : string;
attribute x_core_info of bram_2048_0 : entity is "blk_mem_gen_v8_3_5,Vivado 2016.4";
end bram_2048_0;
architecture STRUCTURE of bram_2048_0 is
signal NLW_U0_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_rsta_busy_UNCONNECTED : STD_LOGIC;
signal NLW_U0_rstb_busy_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_arready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_awready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_bvalid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_rlast_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_rvalid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_wready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_doutb_UNCONNECTED : STD_LOGIC_VECTOR ( 19 downto 0 );
signal NLW_U0_rdaddrecc_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
signal NLW_U0_s_axi_bid_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_s_axi_bresp_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_U0_s_axi_rdaddrecc_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
signal NLW_U0_s_axi_rdata_UNCONNECTED : STD_LOGIC_VECTOR ( 19 downto 0 );
signal NLW_U0_s_axi_rid_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_s_axi_rresp_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute C_ADDRA_WIDTH : integer;
attribute C_ADDRA_WIDTH of U0 : label is 11;
attribute C_ADDRB_WIDTH : integer;
attribute C_ADDRB_WIDTH of U0 : label is 11;
attribute C_ALGORITHM : integer;
attribute C_ALGORITHM of U0 : label is 1;
attribute C_AXI_ID_WIDTH : integer;
attribute C_AXI_ID_WIDTH of U0 : label is 4;
attribute C_AXI_SLAVE_TYPE : integer;
attribute C_AXI_SLAVE_TYPE of U0 : label is 0;
attribute C_AXI_TYPE : integer;
attribute C_AXI_TYPE of U0 : label is 1;
attribute C_BYTE_SIZE : integer;
attribute C_BYTE_SIZE of U0 : label is 9;
attribute C_COMMON_CLK : integer;
attribute C_COMMON_CLK of U0 : label is 0;
attribute C_COUNT_18K_BRAM : string;
attribute C_COUNT_18K_BRAM of U0 : label is "1";
attribute C_COUNT_36K_BRAM : string;
attribute C_COUNT_36K_BRAM of U0 : label is "1";
attribute C_CTRL_ECC_ALGO : string;
attribute C_CTRL_ECC_ALGO of U0 : label is "NONE";
attribute C_DEFAULT_DATA : string;
attribute C_DEFAULT_DATA of U0 : label is "0";
attribute C_DISABLE_WARN_BHV_COLL : integer;
attribute C_DISABLE_WARN_BHV_COLL of U0 : label is 0;
attribute C_DISABLE_WARN_BHV_RANGE : integer;
attribute C_DISABLE_WARN_BHV_RANGE of U0 : label is 0;
attribute C_ELABORATION_DIR : string;
attribute C_ELABORATION_DIR of U0 : label is "./";
attribute C_ENABLE_32BIT_ADDRESS : integer;
attribute C_ENABLE_32BIT_ADDRESS of U0 : label is 0;
attribute C_EN_DEEPSLEEP_PIN : integer;
attribute C_EN_DEEPSLEEP_PIN of U0 : label is 0;
attribute C_EN_ECC_PIPE : integer;
attribute C_EN_ECC_PIPE of U0 : label is 0;
attribute C_EN_RDADDRA_CHG : integer;
attribute C_EN_RDADDRA_CHG of U0 : label is 0;
attribute C_EN_RDADDRB_CHG : integer;
attribute C_EN_RDADDRB_CHG of U0 : label is 0;
attribute C_EN_SAFETY_CKT : integer;
attribute C_EN_SAFETY_CKT of U0 : label is 0;
attribute C_EN_SHUTDOWN_PIN : integer;
attribute C_EN_SHUTDOWN_PIN of U0 : label is 0;
attribute C_EN_SLEEP_PIN : integer;
attribute C_EN_SLEEP_PIN of U0 : label is 0;
attribute C_EST_POWER_SUMMARY : string;
attribute C_EST_POWER_SUMMARY of U0 : label is "Estimated Power for IP : 3.9373 mW";
attribute C_FAMILY : string;
attribute C_FAMILY of U0 : label is "zynq";
attribute C_HAS_AXI_ID : integer;
attribute C_HAS_AXI_ID of U0 : label is 0;
attribute C_HAS_ENA : integer;
attribute C_HAS_ENA of U0 : label is 1;
attribute C_HAS_ENB : integer;
attribute C_HAS_ENB of U0 : label is 0;
attribute C_HAS_INJECTERR : integer;
attribute C_HAS_INJECTERR of U0 : label is 0;
attribute C_HAS_MEM_OUTPUT_REGS_A : integer;
attribute C_HAS_MEM_OUTPUT_REGS_A of U0 : label is 1;
attribute C_HAS_MEM_OUTPUT_REGS_B : integer;
attribute C_HAS_MEM_OUTPUT_REGS_B of U0 : label is 0;
attribute C_HAS_MUX_OUTPUT_REGS_A : integer;
attribute C_HAS_MUX_OUTPUT_REGS_A of U0 : label is 0;
attribute C_HAS_MUX_OUTPUT_REGS_B : integer;
attribute C_HAS_MUX_OUTPUT_REGS_B of U0 : label is 0;
attribute C_HAS_REGCEA : integer;
attribute C_HAS_REGCEA of U0 : label is 0;
attribute C_HAS_REGCEB : integer;
attribute C_HAS_REGCEB of U0 : label is 0;
attribute C_HAS_RSTA : integer;
attribute C_HAS_RSTA of U0 : label is 0;
attribute C_HAS_RSTB : integer;
attribute C_HAS_RSTB of U0 : label is 0;
attribute C_HAS_SOFTECC_INPUT_REGS_A : integer;
attribute C_HAS_SOFTECC_INPUT_REGS_A of U0 : label is 0;
attribute C_HAS_SOFTECC_OUTPUT_REGS_B : integer;
attribute C_HAS_SOFTECC_OUTPUT_REGS_B of U0 : label is 0;
attribute C_INITA_VAL : string;
attribute C_INITA_VAL of U0 : label is "0";
attribute C_INITB_VAL : string;
attribute C_INITB_VAL of U0 : label is "0";
attribute C_INIT_FILE : string;
attribute C_INIT_FILE of U0 : label is "bram_2048_0.mem";
attribute C_INIT_FILE_NAME : string;
attribute C_INIT_FILE_NAME of U0 : label is "bram_2048_0.mif";
attribute C_INTERFACE_TYPE : integer;
attribute C_INTERFACE_TYPE of U0 : label is 0;
attribute C_LOAD_INIT_FILE : integer;
attribute C_LOAD_INIT_FILE of U0 : label is 1;
attribute C_MEM_TYPE : integer;
attribute C_MEM_TYPE of U0 : label is 0;
attribute C_MUX_PIPELINE_STAGES : integer;
attribute C_MUX_PIPELINE_STAGES of U0 : label is 0;
attribute C_PRIM_TYPE : integer;
attribute C_PRIM_TYPE of U0 : label is 1;
attribute C_READ_DEPTH_A : integer;
attribute C_READ_DEPTH_A of U0 : label is 2048;
attribute C_READ_DEPTH_B : integer;
attribute C_READ_DEPTH_B of U0 : label is 2048;
attribute C_READ_WIDTH_A : integer;
attribute C_READ_WIDTH_A of U0 : label is 20;
attribute C_READ_WIDTH_B : integer;
attribute C_READ_WIDTH_B of U0 : label is 20;
attribute C_RSTRAM_A : integer;
attribute C_RSTRAM_A of U0 : label is 0;
attribute C_RSTRAM_B : integer;
attribute C_RSTRAM_B of U0 : label is 0;
attribute C_RST_PRIORITY_A : string;
attribute C_RST_PRIORITY_A of U0 : label is "CE";
attribute C_RST_PRIORITY_B : string;
attribute C_RST_PRIORITY_B of U0 : label is "CE";
attribute C_SIM_COLLISION_CHECK : string;
attribute C_SIM_COLLISION_CHECK of U0 : label is "ALL";
attribute C_USE_BRAM_BLOCK : integer;
attribute C_USE_BRAM_BLOCK of U0 : label is 0;
attribute C_USE_BYTE_WEA : integer;
attribute C_USE_BYTE_WEA of U0 : label is 0;
attribute C_USE_BYTE_WEB : integer;
attribute C_USE_BYTE_WEB of U0 : label is 0;
attribute C_USE_DEFAULT_DATA : integer;
attribute C_USE_DEFAULT_DATA of U0 : label is 0;
attribute C_USE_ECC : integer;
attribute C_USE_ECC of U0 : label is 0;
attribute C_USE_SOFTECC : integer;
attribute C_USE_SOFTECC of U0 : label is 0;
attribute C_USE_URAM : integer;
attribute C_USE_URAM of U0 : label is 0;
attribute C_WEA_WIDTH : integer;
attribute C_WEA_WIDTH of U0 : label is 1;
attribute C_WEB_WIDTH : integer;
attribute C_WEB_WIDTH of U0 : label is 1;
attribute C_WRITE_DEPTH_A : integer;
attribute C_WRITE_DEPTH_A of U0 : label is 2048;
attribute C_WRITE_DEPTH_B : integer;
attribute C_WRITE_DEPTH_B of U0 : label is 2048;
attribute C_WRITE_MODE_A : string;
attribute C_WRITE_MODE_A of U0 : label is "WRITE_FIRST";
attribute C_WRITE_MODE_B : string;
attribute C_WRITE_MODE_B of U0 : label is "WRITE_FIRST";
attribute C_WRITE_WIDTH_A : integer;
attribute C_WRITE_WIDTH_A of U0 : label is 20;
attribute C_WRITE_WIDTH_B : integer;
attribute C_WRITE_WIDTH_B of U0 : label is 20;
attribute C_XDEVICEFAMILY : string;
attribute C_XDEVICEFAMILY of U0 : label is "zynq";
attribute downgradeipidentifiedwarnings of U0 : label is "yes";
begin
U0: entity work.bram_2048_0_blk_mem_gen_v8_3_5
port map (
addra(10 downto 0) => addra(10 downto 0),
addrb(10 downto 0) => B"00000000000",
clka => clka,
clkb => '0',
dbiterr => NLW_U0_dbiterr_UNCONNECTED,
deepsleep => '0',
dina(19 downto 0) => dina(19 downto 0),
dinb(19 downto 0) => B"00000000000000000000",
douta(19 downto 0) => douta(19 downto 0),
doutb(19 downto 0) => NLW_U0_doutb_UNCONNECTED(19 downto 0),
eccpipece => '0',
ena => ena,
enb => '0',
injectdbiterr => '0',
injectsbiterr => '0',
rdaddrecc(10 downto 0) => NLW_U0_rdaddrecc_UNCONNECTED(10 downto 0),
regcea => '0',
regceb => '0',
rsta => '0',
rsta_busy => NLW_U0_rsta_busy_UNCONNECTED,
rstb => '0',
rstb_busy => NLW_U0_rstb_busy_UNCONNECTED,
s_aclk => '0',
s_aresetn => '0',
s_axi_araddr(31 downto 0) => B"00000000000000000000000000000000",
s_axi_arburst(1 downto 0) => B"00",
s_axi_arid(3 downto 0) => B"0000",
s_axi_arlen(7 downto 0) => B"00000000",
s_axi_arready => NLW_U0_s_axi_arready_UNCONNECTED,
s_axi_arsize(2 downto 0) => B"000",
s_axi_arvalid => '0',
s_axi_awaddr(31 downto 0) => B"00000000000000000000000000000000",
s_axi_awburst(1 downto 0) => B"00",
s_axi_awid(3 downto 0) => B"0000",
s_axi_awlen(7 downto 0) => B"00000000",
s_axi_awready => NLW_U0_s_axi_awready_UNCONNECTED,
s_axi_awsize(2 downto 0) => B"000",
s_axi_awvalid => '0',
s_axi_bid(3 downto 0) => NLW_U0_s_axi_bid_UNCONNECTED(3 downto 0),
s_axi_bready => '0',
s_axi_bresp(1 downto 0) => NLW_U0_s_axi_bresp_UNCONNECTED(1 downto 0),
s_axi_bvalid => NLW_U0_s_axi_bvalid_UNCONNECTED,
s_axi_dbiterr => NLW_U0_s_axi_dbiterr_UNCONNECTED,
s_axi_injectdbiterr => '0',
s_axi_injectsbiterr => '0',
s_axi_rdaddrecc(10 downto 0) => NLW_U0_s_axi_rdaddrecc_UNCONNECTED(10 downto 0),
s_axi_rdata(19 downto 0) => NLW_U0_s_axi_rdata_UNCONNECTED(19 downto 0),
s_axi_rid(3 downto 0) => NLW_U0_s_axi_rid_UNCONNECTED(3 downto 0),
s_axi_rlast => NLW_U0_s_axi_rlast_UNCONNECTED,
s_axi_rready => '0',
s_axi_rresp(1 downto 0) => NLW_U0_s_axi_rresp_UNCONNECTED(1 downto 0),
s_axi_rvalid => NLW_U0_s_axi_rvalid_UNCONNECTED,
s_axi_sbiterr => NLW_U0_s_axi_sbiterr_UNCONNECTED,
s_axi_wdata(19 downto 0) => B"00000000000000000000",
s_axi_wlast => '0',
s_axi_wready => NLW_U0_s_axi_wready_UNCONNECTED,
s_axi_wstrb(0) => '0',
s_axi_wvalid => '0',
sbiterr => NLW_U0_sbiterr_UNCONNECTED,
shutdown => '0',
sleep => '0',
wea(0) => wea(0),
web(0) => '0'
);
end STRUCTURE;
| unlicense | 16fef9351fe2096764324d3431e3625b | 0.706938 | 3.696234 | false | false | false | false |
wsoltys/AtomFpga | src/AtomGodilVideo/src/mouse/MouseRefComp.vhd | 1 | 5,692 | ----------------------------------------------------------------------------------
-- Company: Digilent RO
-- Engineer: Mircea Dabacan
--
-- Create Date: 12:57:12 03/01/2008
-- Design Name:
-- Module Name: MouseRefComp - Structural
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description: This is the structural VHDL code of the
-- Digilent Mouse Reference Component.
-- It instantiates three components:
-- - ps2interface
-- - mouse_controller
-- - resolution_mouse_informer
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.ALL;
use ieee.numeric_std.ALL;
library UNISIM;
--use UNISIM.Vcomponents.ALL;
entity MouseRefComp is
generic (
MainClockSpeed : integer
);
port (
CLK : in std_logic;
RESOLUTION : in std_logic;
RST : in std_logic;
SWITCH : in std_logic;
LEFT : out std_logic;
MIDDLE : out std_logic;
NEW_EVENT : out std_logic;
RIGHT : out std_logic;
XPOS : out std_logic_vector (9 downto 0);
YPOS : out std_logic_vector (9 downto 0);
ZPOS : out std_logic_vector (3 downto 0);
PS2_CLK : inout std_logic;
PS2_DATA : inout std_logic);
end MouseRefComp;
architecture Structural of MouseRefComp is
signal TX_DATA : std_logic_vector (7 downto 0);
signal bitSetMaxX : std_logic;
signal vecValue : std_logic_vector (9 downto 0);
signal bitRead : std_logic;
signal bitWrite : std_logic;
signal bitErr : std_logic;
signal bitSetX : std_logic;
signal bitSetY : std_logic;
signal bitSetMaxY : std_logic;
signal vecRxData : std_logic_vector (7 downto 0);
component mouse_controller
port ( clk : in std_logic;
rst : in std_logic;
read : in std_logic;
write : out std_logic;
err : in std_logic;
setx : in std_logic;
sety : in std_logic;
setmax_x : in std_logic;
setmax_y : in std_logic;
value : in std_logic_vector (9 downto 0);
rx_data : in std_logic_vector (7 downto 0);
tx_data : out std_logic_vector (7 downto 0);
left : out std_logic;
middle : out std_logic;
right : out std_logic;
xpos : out std_logic_vector (9 downto 0);
ypos : out std_logic_vector (9 downto 0);
zpos : out std_logic_vector (3 downto 0);
new_event : out std_logic);
end component;
component resolution_mouse_informer
port ( clk : in std_logic;
rst : in std_logic;
resolution : in std_logic;
switch : in std_logic;
setx : out std_logic;
sety : out std_logic;
setmax_x : out std_logic;
setmax_y : out std_logic;
value : out std_logic_vector (9 downto 0));
end component;
component ps2interface
generic (
MainClockSpeed : integer
);
port ( clk : in std_logic;
rst : in std_logic;
read : out std_logic;
write : in std_logic;
rx_data : out std_logic_vector (7 downto 0);
tx_data : in std_logic_vector (7 downto 0);
busy : out std_logic;
err : out std_logic;
ps2_clk : inout std_logic;
ps2_data : inout std_logic);
end component;
begin
MouseCtrlInst : mouse_controller
port map (clk=>CLK,
rst=>RST,
read=>bitRead,
write=>bitWrite,
err=>bitErr,
setmax_x=>bitSetMaxX,
setmax_y=>bitSetMaxY,
setx=>bitSetX,
sety=>bitSetY,
value(9 downto 0)=>vecValue(9 downto 0),
rx_data(7 downto 0)=>vecRxData(7 downto 0),
tx_data(7 downto 0)=>TX_DATA(7 downto 0),
left=>LEFT,
middle=>MIDDLE,
right=>RIGHT,
xpos(9 downto 0)=>XPOS(9 downto 0),
ypos(9 downto 0)=>YPOS(9 downto 0),
zpos(3 downto 0)=>ZPOS(3 downto 0),
new_event=>NEW_EVENT);
ResMouseInfInst : resolution_mouse_informer
port map (clk=>CLK,
resolution=>RESOLUTION,
rst=>RST,
switch=>SWITCH,
setmax_x=>bitSetMaxX,
setmax_y=>bitSetMaxY,
setx=>bitSetX,
sety=>bitSetY,
value(9 downto 0)=>vecValue(9 downto 0));
Pss2Inst : ps2interface
generic map (MainClockSpeed => MainClockSpeed)
port map (clk=>CLK,
rst=>RST,
tx_data(7 downto 0)=>TX_DATA(7 downto 0),
read=>bitRead,
write=>bitWrite,
busy=>open,
err=>bitErr,
rx_data(7 downto 0)=>vecRxData(7 downto 0),
ps2_clk=>PS2_CLK,
ps2_data=>PS2_DATA);
end Structural; | apache-2.0 | ed14a5fc9047f0c6648b07dd0959bf85 | 0.469079 | 4.106782 | false | false | false | false |
jairov4/accel-oil | impl/impl_test_pcie/simulation/behavioral/system_ac1_mb_bridge_wrapper.vhd | 1 | 10,910 | -------------------------------------------------------------------------------
-- system_ac1_mb_bridge_wrapper.vhd
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
library plbv46_plbv46_bridge_v1_04_a;
use plbv46_plbv46_bridge_v1_04_a.all;
entity system_ac1_mb_bridge_wrapper is
port (
SPLB_Clk : in std_logic;
SPLB_Rst : in std_logic;
IP2INTC_Irpt : out std_logic;
PLB_ABus : in std_logic_vector(0 to 31);
PLB_UABus : in std_logic_vector(0 to 31);
PLB_PAValid : in std_logic;
PLB_SAValid : in std_logic;
PLB_rdPrim : in std_logic;
PLB_wrPrim : in std_logic;
PLB_masterID : in std_logic_vector(0 to 3);
PLB_abort : in std_logic;
PLB_busLock : in std_logic;
PLB_RNW : in std_logic;
PLB_BE : in std_logic_vector(0 to 7);
PLB_MSize : in std_logic_vector(0 to 1);
PLB_size : in std_logic_vector(0 to 3);
PLB_type : in std_logic_vector(0 to 2);
PLB_lockErr : in std_logic;
PLB_wrDBus : in std_logic_vector(0 to 63);
PLB_wrBurst : in std_logic;
PLB_rdBurst : in std_logic;
PLB_wrPendReq : in std_logic;
PLB_rdPendReq : in std_logic;
PLB_wrPendPri : in std_logic_vector(0 to 1);
PLB_rdPendPri : in std_logic_vector(0 to 1);
PLB_reqPri : in std_logic_vector(0 to 1);
PLB_TAttribute : in std_logic_vector(0 to 15);
Sl_addrAck : out std_logic;
Sl_SSize : out std_logic_vector(0 to 1);
Sl_wait : out std_logic;
Sl_rearbitrate : out std_logic;
Sl_wrDAck : out std_logic;
Sl_wrComp : out std_logic;
Sl_wrBTerm : out std_logic;
Sl_rdDBus : out std_logic_vector(0 to 63);
Sl_rdWdAddr : out std_logic_vector(0 to 3);
Sl_rdDAck : out std_logic;
Sl_rdComp : out std_logic;
Sl_rdBTerm : out std_logic;
Sl_MBusy : out std_logic_vector(0 to 14);
Sl_MWrErr : out std_logic_vector(0 to 14);
Sl_MRdErr : out std_logic_vector(0 to 14);
Sl_MIRQ : out std_logic_vector(0 to 14);
MPLB_Clk : in std_logic;
MPLB_Rst : in std_logic;
M_request : out std_logic;
M_priority : out std_logic_vector(0 to 1);
M_busLock : out std_logic;
M_RNW : out std_logic;
M_BE : out std_logic_vector(0 to 7);
M_MSize : out std_logic_vector(0 to 1);
M_size : out std_logic_vector(0 to 3);
M_type : out std_logic_vector(0 to 2);
M_ABus : out std_logic_vector(0 to 31);
M_wrBurst : out std_logic;
M_rdBurst : out std_logic;
M_wrDBus : out std_logic_vector(0 to 63);
PLB_MAddrAck : in std_logic;
PLB_MSSize : in std_logic_vector(0 to 1);
PLB_MRearbitrate : in std_logic;
PLB_MTimeout : in std_logic;
PLB_MRdErr : in std_logic;
PLB_MWrErr : in std_logic;
PLB_MRdDBus : in std_logic_vector(0 to 63);
PLB_MRdDAck : in std_logic;
PLB_MRdBTerm : in std_logic;
PLB_MWrDAck : in std_logic;
PLB_MWrBTerm : in std_logic;
M_TAttribute : out std_logic_vector(0 to 15);
M_lockErr : out std_logic;
M_abort : out std_logic;
M_UABus : out std_logic_vector(0 to 31);
PLB_MBusy : in std_logic;
PLB_MIRQ : in std_logic;
PLB_MRdWdAddr : in std_logic_vector(0 to 3)
);
end system_ac1_mb_bridge_wrapper;
architecture STRUCTURE of system_ac1_mb_bridge_wrapper is
component plbv46_plbv46_bridge is
generic (
C_NUM_ADDR_RNG : INTEGER;
C_BRIDGE_BASEADDR : std_logic_vector;
C_BRIDGE_HIGHADDR : std_logic_vector;
C_RNG0_BASEADDR : std_logic_vector;
C_RNG0_HIGHADDR : std_logic_vector;
C_RNG1_BASEADDR : std_logic_vector;
C_RNG1_HIGHADDR : std_logic_vector;
C_RNG2_BASEADDR : std_logic_vector;
C_RNG2_HIGHADDR : std_logic_vector;
C_RNG3_BASEADDR : std_logic_vector;
C_RNG3_HIGHADDR : std_logic_vector;
C_SPLB_P2P : INTEGER;
C_SPLB_MID_WIDTH : INTEGER;
C_SPLB_NUM_MASTERS : INTEGER;
C_SPLB_SMALLEST_MASTER : INTEGER;
C_SPLB_BIGGEST_MASTER : INTEGER;
C_SPLB_AWIDTH : INTEGER;
C_SPLB_DWIDTH : INTEGER;
C_MPLB_AWIDTH : INTEGER;
C_MPLB_DWIDTH : INTEGER;
C_SPLB_NATIVE_DWIDTH : INTEGER;
C_MPLB_NATIVE_DWIDTH : INTEGER;
C_MPLB_SMALLEST_SLAVE : INTEGER;
C_BUS_CLOCK_RATIO : INTEGER;
C_PREFETCH_TIMEOUT : INTEGER;
C_FAMILY : STRING
);
port (
SPLB_Clk : in std_logic;
SPLB_Rst : in std_logic;
IP2INTC_Irpt : out std_logic;
PLB_ABus : in std_logic_vector(0 to C_SPLB_AWIDTH-1);
PLB_UABus : in std_logic_vector(0 to C_SPLB_AWIDTH-1);
PLB_PAValid : in std_logic;
PLB_SAValid : in std_logic;
PLB_rdPrim : in std_logic;
PLB_wrPrim : in std_logic;
PLB_masterID : in std_logic_vector(0 to (C_SPLB_MID_WIDTH-1));
PLB_abort : in std_logic;
PLB_busLock : in std_logic;
PLB_RNW : in std_logic;
PLB_BE : in std_logic_vector(0 to ((C_SPLB_DWIDTH/8)-1));
PLB_MSize : in std_logic_vector(0 to 1);
PLB_size : in std_logic_vector(0 to 3);
PLB_type : in std_logic_vector(0 to 2);
PLB_lockErr : in std_logic;
PLB_wrDBus : in std_logic_vector(0 to (C_SPLB_DWIDTH-1));
PLB_wrBurst : in std_logic;
PLB_rdBurst : in std_logic;
PLB_wrPendReq : in std_logic;
PLB_rdPendReq : in std_logic;
PLB_wrPendPri : in std_logic_vector(0 to 1);
PLB_rdPendPri : in std_logic_vector(0 to 1);
PLB_reqPri : in std_logic_vector(0 to 1);
PLB_TAttribute : in std_logic_vector(0 to 15);
Sl_addrAck : out std_logic;
Sl_SSize : out std_logic_vector(0 to 1);
Sl_wait : out std_logic;
Sl_rearbitrate : out std_logic;
Sl_wrDAck : out std_logic;
Sl_wrComp : out std_logic;
Sl_wrBTerm : out std_logic;
Sl_rdDBus : out std_logic_vector(0 to (C_SPLB_DWIDTH-1));
Sl_rdWdAddr : out std_logic_vector(0 to 3);
Sl_rdDAck : out std_logic;
Sl_rdComp : out std_logic;
Sl_rdBTerm : out std_logic;
Sl_MBusy : out std_logic_vector(0 to (C_SPLB_NUM_MASTERS-1));
Sl_MWrErr : out std_logic_vector(0 to (C_SPLB_NUM_MASTERS-1));
Sl_MRdErr : out std_logic_vector(0 to (C_SPLB_NUM_MASTERS-1));
Sl_MIRQ : out std_logic_vector(0 to (C_SPLB_NUM_MASTERS-1));
MPLB_Clk : in std_logic;
MPLB_Rst : in std_logic;
M_request : out std_logic;
M_priority : out std_logic_vector(0 to 1);
M_busLock : out std_logic;
M_RNW : out std_logic;
M_BE : out std_logic_vector(0 to ((C_MPLB_DWIDTH/8)-1));
M_MSize : out std_logic_vector(0 to 1);
M_size : out std_logic_vector(0 to 3);
M_type : out std_logic_vector(0 to 2);
M_ABus : out std_logic_vector(0 to C_MPLB_AWIDTH-1);
M_wrBurst : out std_logic;
M_rdBurst : out std_logic;
M_wrDBus : out std_logic_vector(0 to (C_MPLB_DWIDTH-1));
PLB_MAddrAck : in std_logic;
PLB_MSSize : in std_logic_vector(0 to 1);
PLB_MRearbitrate : in std_logic;
PLB_MTimeout : in std_logic;
PLB_MRdErr : in std_logic;
PLB_MWrErr : in std_logic;
PLB_MRdDBus : in std_logic_vector(0 to (C_MPLB_DWIDTH-1));
PLB_MRdDAck : in std_logic;
PLB_MRdBTerm : in std_logic;
PLB_MWrDAck : in std_logic;
PLB_MWrBTerm : in std_logic;
M_TAttribute : out std_logic_vector(0 to 15);
M_lockErr : out std_logic;
M_abort : out std_logic;
M_UABus : out std_logic_vector(0 to C_MPLB_AWIDTH-1);
PLB_MBusy : in std_logic;
PLB_MIRQ : in std_logic;
PLB_MRdWdAddr : in std_logic_vector(0 to 3)
);
end component;
begin
ac1_mb_bridge : plbv46_plbv46_bridge
generic map (
C_NUM_ADDR_RNG => 1,
C_BRIDGE_BASEADDR => X"00000000",
C_BRIDGE_HIGHADDR => X"FFFFFFFF",
C_RNG0_BASEADDR => X"00000000",
C_RNG0_HIGHADDR => X"FFFFFFFF",
C_RNG1_BASEADDR => X"ffffffff",
C_RNG1_HIGHADDR => X"00000000",
C_RNG2_BASEADDR => X"ffffffff",
C_RNG2_HIGHADDR => X"00000000",
C_RNG3_BASEADDR => X"ffffffff",
C_RNG3_HIGHADDR => X"00000000",
C_SPLB_P2P => 0,
C_SPLB_MID_WIDTH => 4,
C_SPLB_NUM_MASTERS => 15,
C_SPLB_SMALLEST_MASTER => 64,
C_SPLB_BIGGEST_MASTER => 32,
C_SPLB_AWIDTH => 32,
C_SPLB_DWIDTH => 64,
C_MPLB_AWIDTH => 32,
C_MPLB_DWIDTH => 64,
C_SPLB_NATIVE_DWIDTH => 32,
C_MPLB_NATIVE_DWIDTH => 32,
C_MPLB_SMALLEST_SLAVE => 32,
C_BUS_CLOCK_RATIO => 1,
C_PREFETCH_TIMEOUT => 10,
C_FAMILY => "virtex5"
)
port map (
SPLB_Clk => SPLB_Clk,
SPLB_Rst => SPLB_Rst,
IP2INTC_Irpt => IP2INTC_Irpt,
PLB_ABus => PLB_ABus,
PLB_UABus => PLB_UABus,
PLB_PAValid => PLB_PAValid,
PLB_SAValid => PLB_SAValid,
PLB_rdPrim => PLB_rdPrim,
PLB_wrPrim => PLB_wrPrim,
PLB_masterID => PLB_masterID,
PLB_abort => PLB_abort,
PLB_busLock => PLB_busLock,
PLB_RNW => PLB_RNW,
PLB_BE => PLB_BE,
PLB_MSize => PLB_MSize,
PLB_size => PLB_size,
PLB_type => PLB_type,
PLB_lockErr => PLB_lockErr,
PLB_wrDBus => PLB_wrDBus,
PLB_wrBurst => PLB_wrBurst,
PLB_rdBurst => PLB_rdBurst,
PLB_wrPendReq => PLB_wrPendReq,
PLB_rdPendReq => PLB_rdPendReq,
PLB_wrPendPri => PLB_wrPendPri,
PLB_rdPendPri => PLB_rdPendPri,
PLB_reqPri => PLB_reqPri,
PLB_TAttribute => PLB_TAttribute,
Sl_addrAck => Sl_addrAck,
Sl_SSize => Sl_SSize,
Sl_wait => Sl_wait,
Sl_rearbitrate => Sl_rearbitrate,
Sl_wrDAck => Sl_wrDAck,
Sl_wrComp => Sl_wrComp,
Sl_wrBTerm => Sl_wrBTerm,
Sl_rdDBus => Sl_rdDBus,
Sl_rdWdAddr => Sl_rdWdAddr,
Sl_rdDAck => Sl_rdDAck,
Sl_rdComp => Sl_rdComp,
Sl_rdBTerm => Sl_rdBTerm,
Sl_MBusy => Sl_MBusy,
Sl_MWrErr => Sl_MWrErr,
Sl_MRdErr => Sl_MRdErr,
Sl_MIRQ => Sl_MIRQ,
MPLB_Clk => MPLB_Clk,
MPLB_Rst => MPLB_Rst,
M_request => M_request,
M_priority => M_priority,
M_busLock => M_busLock,
M_RNW => M_RNW,
M_BE => M_BE,
M_MSize => M_MSize,
M_size => M_size,
M_type => M_type,
M_ABus => M_ABus,
M_wrBurst => M_wrBurst,
M_rdBurst => M_rdBurst,
M_wrDBus => M_wrDBus,
PLB_MAddrAck => PLB_MAddrAck,
PLB_MSSize => PLB_MSSize,
PLB_MRearbitrate => PLB_MRearbitrate,
PLB_MTimeout => PLB_MTimeout,
PLB_MRdErr => PLB_MRdErr,
PLB_MWrErr => PLB_MWrErr,
PLB_MRdDBus => PLB_MRdDBus,
PLB_MRdDAck => PLB_MRdDAck,
PLB_MRdBTerm => PLB_MRdBTerm,
PLB_MWrDAck => PLB_MWrDAck,
PLB_MWrBTerm => PLB_MWrBTerm,
M_TAttribute => M_TAttribute,
M_lockErr => M_lockErr,
M_abort => M_abort,
M_UABus => M_UABus,
PLB_MBusy => PLB_MBusy,
PLB_MIRQ => PLB_MIRQ,
PLB_MRdWdAddr => PLB_MRdWdAddr
);
end architecture STRUCTURE;
| lgpl-3.0 | 82b6c37959a54a88d9163510882bd4f6 | 0.590009 | 3.16599 | false | false | false | false |
jairov4/accel-oil | impl/impl_test_pcie/hdl/system_ilmb_cntlr_wrapper.vhd | 1 | 18,461 | -------------------------------------------------------------------------------
-- system_ilmb_cntlr_wrapper.vhd
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
library lmb_bram_if_cntlr_v3_10_c;
use lmb_bram_if_cntlr_v3_10_c.all;
entity system_ilmb_cntlr_wrapper is
port (
LMB_Clk : in std_logic;
LMB_Rst : in std_logic;
LMB_ABus : in std_logic_vector(0 to 31);
LMB_WriteDBus : in std_logic_vector(0 to 31);
LMB_AddrStrobe : in std_logic;
LMB_ReadStrobe : in std_logic;
LMB_WriteStrobe : in std_logic;
LMB_BE : in std_logic_vector(0 to 3);
Sl_DBus : out std_logic_vector(0 to 31);
Sl_Ready : out std_logic;
Sl_Wait : out std_logic;
Sl_UE : out std_logic;
Sl_CE : out std_logic;
LMB1_ABus : in std_logic_vector(0 to 31);
LMB1_WriteDBus : in std_logic_vector(0 to 31);
LMB1_AddrStrobe : in std_logic;
LMB1_ReadStrobe : in std_logic;
LMB1_WriteStrobe : in std_logic;
LMB1_BE : in std_logic_vector(0 to 3);
Sl1_DBus : out std_logic_vector(0 to 31);
Sl1_Ready : out std_logic;
Sl1_Wait : out std_logic;
Sl1_UE : out std_logic;
Sl1_CE : out std_logic;
LMB2_ABus : in std_logic_vector(0 to 31);
LMB2_WriteDBus : in std_logic_vector(0 to 31);
LMB2_AddrStrobe : in std_logic;
LMB2_ReadStrobe : in std_logic;
LMB2_WriteStrobe : in std_logic;
LMB2_BE : in std_logic_vector(0 to 3);
Sl2_DBus : out std_logic_vector(0 to 31);
Sl2_Ready : out std_logic;
Sl2_Wait : out std_logic;
Sl2_UE : out std_logic;
Sl2_CE : out std_logic;
LMB3_ABus : in std_logic_vector(0 to 31);
LMB3_WriteDBus : in std_logic_vector(0 to 31);
LMB3_AddrStrobe : in std_logic;
LMB3_ReadStrobe : in std_logic;
LMB3_WriteStrobe : in std_logic;
LMB3_BE : in std_logic_vector(0 to 3);
Sl3_DBus : out std_logic_vector(0 to 31);
Sl3_Ready : out std_logic;
Sl3_Wait : out std_logic;
Sl3_UE : out std_logic;
Sl3_CE : out std_logic;
BRAM_Rst_A : out std_logic;
BRAM_Clk_A : out std_logic;
BRAM_EN_A : out std_logic;
BRAM_WEN_A : out std_logic_vector(0 to 3);
BRAM_Addr_A : out std_logic_vector(0 to 31);
BRAM_Din_A : in std_logic_vector(0 to 31);
BRAM_Dout_A : out std_logic_vector(0 to 31);
Interrupt : out std_logic;
UE : out std_logic;
CE : out std_logic;
SPLB_CTRL_PLB_ABus : in std_logic_vector(0 to 31);
SPLB_CTRL_PLB_PAValid : in std_logic;
SPLB_CTRL_PLB_masterID : in std_logic_vector(0 to 0);
SPLB_CTRL_PLB_RNW : in std_logic;
SPLB_CTRL_PLB_BE : in std_logic_vector(0 to 3);
SPLB_CTRL_PLB_size : in std_logic_vector(0 to 3);
SPLB_CTRL_PLB_type : in std_logic_vector(0 to 2);
SPLB_CTRL_PLB_wrDBus : in std_logic_vector(0 to 31);
SPLB_CTRL_Sl_addrAck : out std_logic;
SPLB_CTRL_Sl_SSize : out std_logic_vector(0 to 1);
SPLB_CTRL_Sl_wait : out std_logic;
SPLB_CTRL_Sl_rearbitrate : out std_logic;
SPLB_CTRL_Sl_wrDAck : out std_logic;
SPLB_CTRL_Sl_wrComp : out std_logic;
SPLB_CTRL_Sl_rdDBus : out std_logic_vector(0 to 31);
SPLB_CTRL_Sl_rdDAck : out std_logic;
SPLB_CTRL_Sl_rdComp : out std_logic;
SPLB_CTRL_Sl_MBusy : out std_logic_vector(0 to 0);
SPLB_CTRL_Sl_MWrErr : out std_logic_vector(0 to 0);
SPLB_CTRL_Sl_MRdErr : out std_logic_vector(0 to 0);
SPLB_CTRL_PLB_UABus : in std_logic_vector(0 to 31);
SPLB_CTRL_PLB_SAValid : in std_logic;
SPLB_CTRL_PLB_rdPrim : in std_logic;
SPLB_CTRL_PLB_wrPrim : in std_logic;
SPLB_CTRL_PLB_abort : in std_logic;
SPLB_CTRL_PLB_busLock : in std_logic;
SPLB_CTRL_PLB_MSize : in std_logic_vector(0 to 1);
SPLB_CTRL_PLB_lockErr : in std_logic;
SPLB_CTRL_PLB_wrBurst : in std_logic;
SPLB_CTRL_PLB_rdBurst : in std_logic;
SPLB_CTRL_PLB_wrPendReq : in std_logic;
SPLB_CTRL_PLB_rdPendReq : in std_logic;
SPLB_CTRL_PLB_wrPendPri : in std_logic_vector(0 to 1);
SPLB_CTRL_PLB_rdPendPri : in std_logic_vector(0 to 1);
SPLB_CTRL_PLB_reqPri : in std_logic_vector(0 to 1);
SPLB_CTRL_PLB_TAttribute : in std_logic_vector(0 to 15);
SPLB_CTRL_Sl_wrBTerm : out std_logic;
SPLB_CTRL_Sl_rdWdAddr : out std_logic_vector(0 to 3);
SPLB_CTRL_Sl_rdBTerm : out std_logic;
SPLB_CTRL_Sl_MIRQ : out std_logic_vector(0 to 0);
S_AXI_CTRL_ACLK : in std_logic;
S_AXI_CTRL_ARESETN : in std_logic;
S_AXI_CTRL_AWADDR : in std_logic_vector(31 downto 0);
S_AXI_CTRL_AWVALID : in std_logic;
S_AXI_CTRL_AWREADY : out std_logic;
S_AXI_CTRL_WDATA : in std_logic_vector(31 downto 0);
S_AXI_CTRL_WSTRB : in std_logic_vector(3 downto 0);
S_AXI_CTRL_WVALID : in std_logic;
S_AXI_CTRL_WREADY : out std_logic;
S_AXI_CTRL_BRESP : out std_logic_vector(1 downto 0);
S_AXI_CTRL_BVALID : out std_logic;
S_AXI_CTRL_BREADY : in std_logic;
S_AXI_CTRL_ARADDR : in std_logic_vector(31 downto 0);
S_AXI_CTRL_ARVALID : in std_logic;
S_AXI_CTRL_ARREADY : out std_logic;
S_AXI_CTRL_RDATA : out std_logic_vector(31 downto 0);
S_AXI_CTRL_RRESP : out std_logic_vector(1 downto 0);
S_AXI_CTRL_RVALID : out std_logic;
S_AXI_CTRL_RREADY : in std_logic
);
attribute x_core_info : STRING;
attribute x_core_info of system_ilmb_cntlr_wrapper : entity is "lmb_bram_if_cntlr_v3_10_c";
end system_ilmb_cntlr_wrapper;
architecture STRUCTURE of system_ilmb_cntlr_wrapper is
component lmb_bram_if_cntlr is
generic (
C_BASEADDR : std_logic_vector(0 to 31);
C_HIGHADDR : std_logic_vector(0 to 31);
C_FAMILY : string;
C_MASK : std_logic_vector(0 to 31);
C_MASK1 : std_logic_vector(0 to 31);
C_MASK2 : std_logic_vector(0 to 31);
C_MASK3 : std_logic_vector(0 to 31);
C_LMB_AWIDTH : integer;
C_LMB_DWIDTH : integer;
C_ECC : integer;
C_INTERCONNECT : integer;
C_FAULT_INJECT : integer;
C_CE_FAILING_REGISTERS : integer;
C_UE_FAILING_REGISTERS : integer;
C_ECC_STATUS_REGISTERS : integer;
C_ECC_ONOFF_REGISTER : integer;
C_ECC_ONOFF_RESET_VALUE : integer;
C_CE_COUNTER_WIDTH : integer;
C_WRITE_ACCESS : integer;
C_NUM_LMB : integer;
C_SPLB_CTRL_BASEADDR : std_logic_vector;
C_SPLB_CTRL_HIGHADDR : std_logic_vector;
C_SPLB_CTRL_AWIDTH : INTEGER;
C_SPLB_CTRL_DWIDTH : INTEGER;
C_SPLB_CTRL_P2P : INTEGER;
C_SPLB_CTRL_MID_WIDTH : INTEGER;
C_SPLB_CTRL_NUM_MASTERS : INTEGER;
C_SPLB_CTRL_SUPPORT_BURSTS : INTEGER;
C_SPLB_CTRL_NATIVE_DWIDTH : INTEGER;
C_S_AXI_CTRL_BASEADDR : std_logic_vector(31 downto 0);
C_S_AXI_CTRL_HIGHADDR : std_logic_vector(31 downto 0);
C_S_AXI_CTRL_ADDR_WIDTH : INTEGER;
C_S_AXI_CTRL_DATA_WIDTH : INTEGER
);
port (
LMB_Clk : in std_logic;
LMB_Rst : in std_logic;
LMB_ABus : in std_logic_vector(0 to C_LMB_AWIDTH-1);
LMB_WriteDBus : in std_logic_vector(0 to C_LMB_DWIDTH-1);
LMB_AddrStrobe : in std_logic;
LMB_ReadStrobe : in std_logic;
LMB_WriteStrobe : in std_logic;
LMB_BE : in std_logic_vector(0 to C_LMB_DWIDTH/8-1);
Sl_DBus : out std_logic_vector(0 to C_LMB_DWIDTH-1);
Sl_Ready : out std_logic;
Sl_Wait : out std_logic;
Sl_UE : out std_logic;
Sl_CE : out std_logic;
LMB1_ABus : in std_logic_vector(0 to C_LMB_AWIDTH-1);
LMB1_WriteDBus : in std_logic_vector(0 to C_LMB_DWIDTH-1);
LMB1_AddrStrobe : in std_logic;
LMB1_ReadStrobe : in std_logic;
LMB1_WriteStrobe : in std_logic;
LMB1_BE : in std_logic_vector(0 to C_LMB_DWIDTH/8-1);
Sl1_DBus : out std_logic_vector(0 to C_LMB_DWIDTH-1);
Sl1_Ready : out std_logic;
Sl1_Wait : out std_logic;
Sl1_UE : out std_logic;
Sl1_CE : out std_logic;
LMB2_ABus : in std_logic_vector(0 to C_LMB_AWIDTH-1);
LMB2_WriteDBus : in std_logic_vector(0 to C_LMB_DWIDTH-1);
LMB2_AddrStrobe : in std_logic;
LMB2_ReadStrobe : in std_logic;
LMB2_WriteStrobe : in std_logic;
LMB2_BE : in std_logic_vector(0 to C_LMB_DWIDTH/8-1);
Sl2_DBus : out std_logic_vector(0 to C_LMB_DWIDTH-1);
Sl2_Ready : out std_logic;
Sl2_Wait : out std_logic;
Sl2_UE : out std_logic;
Sl2_CE : out std_logic;
LMB3_ABus : in std_logic_vector(0 to C_LMB_AWIDTH-1);
LMB3_WriteDBus : in std_logic_vector(0 to C_LMB_DWIDTH-1);
LMB3_AddrStrobe : in std_logic;
LMB3_ReadStrobe : in std_logic;
LMB3_WriteStrobe : in std_logic;
LMB3_BE : in std_logic_vector(0 to C_LMB_DWIDTH/8-1);
Sl3_DBus : out std_logic_vector(0 to C_LMB_DWIDTH-1);
Sl3_Ready : out std_logic;
Sl3_Wait : out std_logic;
Sl3_UE : out std_logic;
Sl3_CE : out std_logic;
BRAM_Rst_A : out std_logic;
BRAM_Clk_A : out std_logic;
BRAM_EN_A : out std_logic;
BRAM_WEN_A : out std_logic_vector(0 to ((C_LMB_DWIDTH+8*C_ECC)/8)-1);
BRAM_Addr_A : out std_logic_vector(0 to C_LMB_AWIDTH-1);
BRAM_Din_A : in std_logic_vector(0 to C_LMB_DWIDTH-1+8*C_ECC);
BRAM_Dout_A : out std_logic_vector(0 to C_LMB_DWIDTH-1+8*C_ECC);
Interrupt : out std_logic;
UE : out std_logic;
CE : out std_logic;
SPLB_CTRL_PLB_ABus : in std_logic_vector(0 to 31);
SPLB_CTRL_PLB_PAValid : in std_logic;
SPLB_CTRL_PLB_masterID : in std_logic_vector(0 to (C_SPLB_CTRL_MID_WIDTH-1));
SPLB_CTRL_PLB_RNW : in std_logic;
SPLB_CTRL_PLB_BE : in std_logic_vector(0 to ((C_SPLB_CTRL_DWIDTH/8)-1));
SPLB_CTRL_PLB_size : in std_logic_vector(0 to 3);
SPLB_CTRL_PLB_type : in std_logic_vector(0 to 2);
SPLB_CTRL_PLB_wrDBus : in std_logic_vector(0 to (C_SPLB_CTRL_DWIDTH-1));
SPLB_CTRL_Sl_addrAck : out std_logic;
SPLB_CTRL_Sl_SSize : out std_logic_vector(0 to 1);
SPLB_CTRL_Sl_wait : out std_logic;
SPLB_CTRL_Sl_rearbitrate : out std_logic;
SPLB_CTRL_Sl_wrDAck : out std_logic;
SPLB_CTRL_Sl_wrComp : out std_logic;
SPLB_CTRL_Sl_rdDBus : out std_logic_vector(0 to (C_SPLB_CTRL_DWIDTH-1));
SPLB_CTRL_Sl_rdDAck : out std_logic;
SPLB_CTRL_Sl_rdComp : out std_logic;
SPLB_CTRL_Sl_MBusy : out std_logic_vector(0 to (C_SPLB_CTRL_NUM_MASTERS-1));
SPLB_CTRL_Sl_MWrErr : out std_logic_vector(0 to (C_SPLB_CTRL_NUM_MASTERS-1));
SPLB_CTRL_Sl_MRdErr : out std_logic_vector(0 to (C_SPLB_CTRL_NUM_MASTERS-1));
SPLB_CTRL_PLB_UABus : in std_logic_vector(0 to 31);
SPLB_CTRL_PLB_SAValid : in std_logic;
SPLB_CTRL_PLB_rdPrim : in std_logic;
SPLB_CTRL_PLB_wrPrim : in std_logic;
SPLB_CTRL_PLB_abort : in std_logic;
SPLB_CTRL_PLB_busLock : in std_logic;
SPLB_CTRL_PLB_MSize : in std_logic_vector(0 to 1);
SPLB_CTRL_PLB_lockErr : in std_logic;
SPLB_CTRL_PLB_wrBurst : in std_logic;
SPLB_CTRL_PLB_rdBurst : in std_logic;
SPLB_CTRL_PLB_wrPendReq : in std_logic;
SPLB_CTRL_PLB_rdPendReq : in std_logic;
SPLB_CTRL_PLB_wrPendPri : in std_logic_vector(0 to 1);
SPLB_CTRL_PLB_rdPendPri : in std_logic_vector(0 to 1);
SPLB_CTRL_PLB_reqPri : in std_logic_vector(0 to 1);
SPLB_CTRL_PLB_TAttribute : in std_logic_vector(0 to 15);
SPLB_CTRL_Sl_wrBTerm : out std_logic;
SPLB_CTRL_Sl_rdWdAddr : out std_logic_vector(0 to 3);
SPLB_CTRL_Sl_rdBTerm : out std_logic;
SPLB_CTRL_Sl_MIRQ : out std_logic_vector(0 to (C_SPLB_CTRL_NUM_MASTERS-1));
S_AXI_CTRL_ACLK : in std_logic;
S_AXI_CTRL_ARESETN : in std_logic;
S_AXI_CTRL_AWADDR : in std_logic_vector((C_S_AXI_CTRL_ADDR_WIDTH-1) downto 0);
S_AXI_CTRL_AWVALID : in std_logic;
S_AXI_CTRL_AWREADY : out std_logic;
S_AXI_CTRL_WDATA : in std_logic_vector((C_S_AXI_CTRL_DATA_WIDTH-1) downto 0);
S_AXI_CTRL_WSTRB : in std_logic_vector(((C_S_AXI_CTRL_DATA_WIDTH/8)-1) downto 0);
S_AXI_CTRL_WVALID : in std_logic;
S_AXI_CTRL_WREADY : out std_logic;
S_AXI_CTRL_BRESP : out std_logic_vector(1 downto 0);
S_AXI_CTRL_BVALID : out std_logic;
S_AXI_CTRL_BREADY : in std_logic;
S_AXI_CTRL_ARADDR : in std_logic_vector((C_S_AXI_CTRL_ADDR_WIDTH-1) downto 0);
S_AXI_CTRL_ARVALID : in std_logic;
S_AXI_CTRL_ARREADY : out std_logic;
S_AXI_CTRL_RDATA : out std_logic_vector((C_S_AXI_CTRL_DATA_WIDTH-1) downto 0);
S_AXI_CTRL_RRESP : out std_logic_vector(1 downto 0);
S_AXI_CTRL_RVALID : out std_logic;
S_AXI_CTRL_RREADY : in std_logic
);
end component;
begin
ilmb_cntlr : lmb_bram_if_cntlr
generic map (
C_BASEADDR => X"00000000",
C_HIGHADDR => X"00000fff",
C_FAMILY => "virtex5",
C_MASK => X"80000000",
C_MASK1 => X"00800000",
C_MASK2 => X"00800000",
C_MASK3 => X"00800000",
C_LMB_AWIDTH => 32,
C_LMB_DWIDTH => 32,
C_ECC => 0,
C_INTERCONNECT => 0,
C_FAULT_INJECT => 0,
C_CE_FAILING_REGISTERS => 0,
C_UE_FAILING_REGISTERS => 0,
C_ECC_STATUS_REGISTERS => 0,
C_ECC_ONOFF_REGISTER => 0,
C_ECC_ONOFF_RESET_VALUE => 1,
C_CE_COUNTER_WIDTH => 0,
C_WRITE_ACCESS => 2,
C_NUM_LMB => 1,
C_SPLB_CTRL_BASEADDR => X"FFFFFFFF",
C_SPLB_CTRL_HIGHADDR => X"00000000",
C_SPLB_CTRL_AWIDTH => 32,
C_SPLB_CTRL_DWIDTH => 32,
C_SPLB_CTRL_P2P => 0,
C_SPLB_CTRL_MID_WIDTH => 1,
C_SPLB_CTRL_NUM_MASTERS => 1,
C_SPLB_CTRL_SUPPORT_BURSTS => 0,
C_SPLB_CTRL_NATIVE_DWIDTH => 32,
C_S_AXI_CTRL_BASEADDR => X"FFFFFFFF",
C_S_AXI_CTRL_HIGHADDR => X"00000000",
C_S_AXI_CTRL_ADDR_WIDTH => 32,
C_S_AXI_CTRL_DATA_WIDTH => 32
)
port map (
LMB_Clk => LMB_Clk,
LMB_Rst => LMB_Rst,
LMB_ABus => LMB_ABus,
LMB_WriteDBus => LMB_WriteDBus,
LMB_AddrStrobe => LMB_AddrStrobe,
LMB_ReadStrobe => LMB_ReadStrobe,
LMB_WriteStrobe => LMB_WriteStrobe,
LMB_BE => LMB_BE,
Sl_DBus => Sl_DBus,
Sl_Ready => Sl_Ready,
Sl_Wait => Sl_Wait,
Sl_UE => Sl_UE,
Sl_CE => Sl_CE,
LMB1_ABus => LMB1_ABus,
LMB1_WriteDBus => LMB1_WriteDBus,
LMB1_AddrStrobe => LMB1_AddrStrobe,
LMB1_ReadStrobe => LMB1_ReadStrobe,
LMB1_WriteStrobe => LMB1_WriteStrobe,
LMB1_BE => LMB1_BE,
Sl1_DBus => Sl1_DBus,
Sl1_Ready => Sl1_Ready,
Sl1_Wait => Sl1_Wait,
Sl1_UE => Sl1_UE,
Sl1_CE => Sl1_CE,
LMB2_ABus => LMB2_ABus,
LMB2_WriteDBus => LMB2_WriteDBus,
LMB2_AddrStrobe => LMB2_AddrStrobe,
LMB2_ReadStrobe => LMB2_ReadStrobe,
LMB2_WriteStrobe => LMB2_WriteStrobe,
LMB2_BE => LMB2_BE,
Sl2_DBus => Sl2_DBus,
Sl2_Ready => Sl2_Ready,
Sl2_Wait => Sl2_Wait,
Sl2_UE => Sl2_UE,
Sl2_CE => Sl2_CE,
LMB3_ABus => LMB3_ABus,
LMB3_WriteDBus => LMB3_WriteDBus,
LMB3_AddrStrobe => LMB3_AddrStrobe,
LMB3_ReadStrobe => LMB3_ReadStrobe,
LMB3_WriteStrobe => LMB3_WriteStrobe,
LMB3_BE => LMB3_BE,
Sl3_DBus => Sl3_DBus,
Sl3_Ready => Sl3_Ready,
Sl3_Wait => Sl3_Wait,
Sl3_UE => Sl3_UE,
Sl3_CE => Sl3_CE,
BRAM_Rst_A => BRAM_Rst_A,
BRAM_Clk_A => BRAM_Clk_A,
BRAM_EN_A => BRAM_EN_A,
BRAM_WEN_A => BRAM_WEN_A,
BRAM_Addr_A => BRAM_Addr_A,
BRAM_Din_A => BRAM_Din_A,
BRAM_Dout_A => BRAM_Dout_A,
Interrupt => Interrupt,
UE => UE,
CE => CE,
SPLB_CTRL_PLB_ABus => SPLB_CTRL_PLB_ABus,
SPLB_CTRL_PLB_PAValid => SPLB_CTRL_PLB_PAValid,
SPLB_CTRL_PLB_masterID => SPLB_CTRL_PLB_masterID,
SPLB_CTRL_PLB_RNW => SPLB_CTRL_PLB_RNW,
SPLB_CTRL_PLB_BE => SPLB_CTRL_PLB_BE,
SPLB_CTRL_PLB_size => SPLB_CTRL_PLB_size,
SPLB_CTRL_PLB_type => SPLB_CTRL_PLB_type,
SPLB_CTRL_PLB_wrDBus => SPLB_CTRL_PLB_wrDBus,
SPLB_CTRL_Sl_addrAck => SPLB_CTRL_Sl_addrAck,
SPLB_CTRL_Sl_SSize => SPLB_CTRL_Sl_SSize,
SPLB_CTRL_Sl_wait => SPLB_CTRL_Sl_wait,
SPLB_CTRL_Sl_rearbitrate => SPLB_CTRL_Sl_rearbitrate,
SPLB_CTRL_Sl_wrDAck => SPLB_CTRL_Sl_wrDAck,
SPLB_CTRL_Sl_wrComp => SPLB_CTRL_Sl_wrComp,
SPLB_CTRL_Sl_rdDBus => SPLB_CTRL_Sl_rdDBus,
SPLB_CTRL_Sl_rdDAck => SPLB_CTRL_Sl_rdDAck,
SPLB_CTRL_Sl_rdComp => SPLB_CTRL_Sl_rdComp,
SPLB_CTRL_Sl_MBusy => SPLB_CTRL_Sl_MBusy,
SPLB_CTRL_Sl_MWrErr => SPLB_CTRL_Sl_MWrErr,
SPLB_CTRL_Sl_MRdErr => SPLB_CTRL_Sl_MRdErr,
SPLB_CTRL_PLB_UABus => SPLB_CTRL_PLB_UABus,
SPLB_CTRL_PLB_SAValid => SPLB_CTRL_PLB_SAValid,
SPLB_CTRL_PLB_rdPrim => SPLB_CTRL_PLB_rdPrim,
SPLB_CTRL_PLB_wrPrim => SPLB_CTRL_PLB_wrPrim,
SPLB_CTRL_PLB_abort => SPLB_CTRL_PLB_abort,
SPLB_CTRL_PLB_busLock => SPLB_CTRL_PLB_busLock,
SPLB_CTRL_PLB_MSize => SPLB_CTRL_PLB_MSize,
SPLB_CTRL_PLB_lockErr => SPLB_CTRL_PLB_lockErr,
SPLB_CTRL_PLB_wrBurst => SPLB_CTRL_PLB_wrBurst,
SPLB_CTRL_PLB_rdBurst => SPLB_CTRL_PLB_rdBurst,
SPLB_CTRL_PLB_wrPendReq => SPLB_CTRL_PLB_wrPendReq,
SPLB_CTRL_PLB_rdPendReq => SPLB_CTRL_PLB_rdPendReq,
SPLB_CTRL_PLB_wrPendPri => SPLB_CTRL_PLB_wrPendPri,
SPLB_CTRL_PLB_rdPendPri => SPLB_CTRL_PLB_rdPendPri,
SPLB_CTRL_PLB_reqPri => SPLB_CTRL_PLB_reqPri,
SPLB_CTRL_PLB_TAttribute => SPLB_CTRL_PLB_TAttribute,
SPLB_CTRL_Sl_wrBTerm => SPLB_CTRL_Sl_wrBTerm,
SPLB_CTRL_Sl_rdWdAddr => SPLB_CTRL_Sl_rdWdAddr,
SPLB_CTRL_Sl_rdBTerm => SPLB_CTRL_Sl_rdBTerm,
SPLB_CTRL_Sl_MIRQ => SPLB_CTRL_Sl_MIRQ,
S_AXI_CTRL_ACLK => S_AXI_CTRL_ACLK,
S_AXI_CTRL_ARESETN => S_AXI_CTRL_ARESETN,
S_AXI_CTRL_AWADDR => S_AXI_CTRL_AWADDR,
S_AXI_CTRL_AWVALID => S_AXI_CTRL_AWVALID,
S_AXI_CTRL_AWREADY => S_AXI_CTRL_AWREADY,
S_AXI_CTRL_WDATA => S_AXI_CTRL_WDATA,
S_AXI_CTRL_WSTRB => S_AXI_CTRL_WSTRB,
S_AXI_CTRL_WVALID => S_AXI_CTRL_WVALID,
S_AXI_CTRL_WREADY => S_AXI_CTRL_WREADY,
S_AXI_CTRL_BRESP => S_AXI_CTRL_BRESP,
S_AXI_CTRL_BVALID => S_AXI_CTRL_BVALID,
S_AXI_CTRL_BREADY => S_AXI_CTRL_BREADY,
S_AXI_CTRL_ARADDR => S_AXI_CTRL_ARADDR,
S_AXI_CTRL_ARVALID => S_AXI_CTRL_ARVALID,
S_AXI_CTRL_ARREADY => S_AXI_CTRL_ARREADY,
S_AXI_CTRL_RDATA => S_AXI_CTRL_RDATA,
S_AXI_CTRL_RRESP => S_AXI_CTRL_RRESP,
S_AXI_CTRL_RVALID => S_AXI_CTRL_RVALID,
S_AXI_CTRL_RREADY => S_AXI_CTRL_RREADY
);
end architecture STRUCTURE;
| lgpl-3.0 | 7a416e37f7f51cd14633bc225761cf34 | 0.615785 | 2.932645 | false | false | false | false |
grwlf/vsim | vhdl_ct/ct00174.vhd | 1 | 8,695 | -- NEED RESULT: ARCH00174.P1: Multi inertial transactions occurred on signal asg with indexed name prefixed by a selected name on LHS passed
-- NEED RESULT: ARCH00174: One inertial transaction occurred on signal asg with indexed name prefixed by a selected name on LHS passed
-- NEED RESULT: P1: Inertial transactions entirely completed failed
-------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
-------------------------------------------------------------------------------
--
-- TEST NAME:
--
-- CT00174
--
-- AUTHOR:
--
-- G. Tominovich
--
-- TEST OBJECTIVES:
--
-- 8.3 (1)
-- 8.3 (2)
-- 8.3 (4)
-- 8.3 (5)
-- 8.3.1 (4)
--
-- DESIGN UNIT ORDERING:
--
-- E00000(ARCH00174)
-- ENT00174_Test_Bench(ARCH00174_Test_Bench)
--
-- REVISION HISTORY:
--
-- 08-JUL-1987 - initial revision
--
-- NOTES:
--
-- self-checking
-- automatically generated
--
use WORK.STANDARD_TYPES.all ;
architecture ARCH00174 of E00000 is
subtype chk_sig_type is integer range -1 to 100 ;
signal chk_st_rec3 : chk_sig_type := -1 ;
--
signal s_st_rec3 : st_rec3
:= c_st_rec3_1 ;
--
begin
P1 :
process
variable correct : boolean ;
variable counter : integer := 0 ;
variable savtime : time ;
--
procedure Proc1 is
begin
case counter is
when 0 =>
s_st_rec3.f3 (
s_st_rec3.f3'Left(1),s_st_rec3.f3'Left(2)) <=
c_st_rec3_2.f3 (
s_st_rec3.f3'Right(1),s_st_rec3.f3'Right(2)) after 10 ns,
c_st_rec3_1.f3 (
s_st_rec3.f3'Right(1),s_st_rec3.f3'Right(2)) after 20 ns ;
--
when 1 =>
correct :=
s_st_rec3.f3 (
s_st_rec3.f3'Left(1),s_st_rec3.f3'Left(2)) =
c_st_rec3_2.f3 (
s_st_rec3.f3'Right(1),s_st_rec3.f3'Right(2)) and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2 =>
correct :=
correct and
s_st_rec3.f3 (
s_st_rec3.f3'Left(1),s_st_rec3.f3'Left(2)) =
c_st_rec3_1.f3 (
s_st_rec3.f3'Right(1),s_st_rec3.f3'Right(2)) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00174.P1" ,
"Multi inertial transactions occurred on signal " &
"asg with indexed name prefixed by a selected name on LHS",
correct ) ;
s_st_rec3.f3 (
s_st_rec3.f3'Left(1),s_st_rec3.f3'Left(2)) <=
c_st_rec3_2.f3 (
s_st_rec3.f3'Right(1),s_st_rec3.f3'Right(2)) after 10 ns,
c_st_rec3_1.f3 (
s_st_rec3.f3'Right(1),s_st_rec3.f3'Right(2)) after 20 ns,
c_st_rec3_2.f3 (
s_st_rec3.f3'Right(1),s_st_rec3.f3'Right(2)) after 30 ns,
c_st_rec3_1.f3 (
s_st_rec3.f3'Right(1),s_st_rec3.f3'Right(2)) after 40 ns ;
--
when 3 =>
correct :=
s_st_rec3.f3 (
s_st_rec3.f3'Left(1),s_st_rec3.f3'Left(2)) =
c_st_rec3_2.f3 (
s_st_rec3.f3'Right(1),s_st_rec3.f3'Right(2)) and
(savtime + 10 ns) = Std.Standard.Now ;
s_st_rec3.f3 (
s_st_rec3.f3'Left(1),s_st_rec3.f3'Left(2)) <=
c_st_rec3_1.f3 (
s_st_rec3.f3'Right(1),s_st_rec3.f3'Right(2)) after 5 ns;
--
when 4 =>
correct :=
correct and
s_st_rec3.f3 (
s_st_rec3.f3'Left(1),s_st_rec3.f3'Left(2)) =
c_st_rec3_1.f3 (
s_st_rec3.f3'Right(1),s_st_rec3.f3'Right(2)) and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00174" ,
"One inertial transaction occurred on signal " &
"asg with indexed name prefixed by a selected name on LHS",
correct ) ;
s_st_rec3.f3 (
s_st_rec3.f3'Left(1),s_st_rec3.f3'Left(2)) <= transport
c_st_rec3_1.f3 (
s_st_rec3.f3'Right(1),s_st_rec3.f3'Right(2)) after 100 ns;
--
when 5 =>
correct :=
s_st_rec3.f3 (
s_st_rec3.f3'Left(1),s_st_rec3.f3'Left(2)) =
c_st_rec3_1.f3 (
s_st_rec3.f3'Right(1),s_st_rec3.f3'Right(2)) and
(savtime + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00174" ,
"Old transactions were removed on signal " &
"asg with indexed name prefixed by a selected name on LHS",
correct ) ;
s_st_rec3.f3 (
s_st_rec3.f3'Left(1),s_st_rec3.f3'Left(2)) <=
c_st_rec3_2.f3 (
s_st_rec3.f3'Right(1),s_st_rec3.f3'Right(2)) after 10 ns,
c_st_rec3_1.f3 (
s_st_rec3.f3'Right(1),s_st_rec3.f3'Right(2)) after 20 ns,
c_st_rec3_2.f3 (
s_st_rec3.f3'Right(1),s_st_rec3.f3'Right(2)) after 30 ns,
c_st_rec3_1.f3 (
s_st_rec3.f3'Right(1),s_st_rec3.f3'Right(2)) after 40 ns ;
--
when 6 =>
correct :=
s_st_rec3.f3 (
s_st_rec3.f3'Left(1),s_st_rec3.f3'Left(2)) =
c_st_rec3_2.f3 (
s_st_rec3.f3'Right(1),s_st_rec3.f3'Right(2)) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00174" ,
"One inertial transaction occurred on signal " &
"asg with indexed name prefixed by a selected name on LHS",
correct ) ;
-- The following will mark last transaction above
s_st_rec3.f3 (
s_st_rec3.f3'Left(1),s_st_rec3.f3'Left(2)) <=
c_st_rec3_1.f3 (
s_st_rec3.f3'Right(1),s_st_rec3.f3'Right(2)) after 40 ns;
--
when 7 =>
correct :=
s_st_rec3.f3 (
s_st_rec3.f3'Left(1),s_st_rec3.f3'Left(2)) =
c_st_rec3_1.f3 (
s_st_rec3.f3'Right(1),s_st_rec3.f3'Right(2)) and
(savtime + 30 ns) = Std.Standard.Now ;
--
when 8 =>
correct :=
correct and
s_st_rec3.f3 (
s_st_rec3.f3'Left(1),s_st_rec3.f3'Left(2)) =
c_st_rec3_1.f3 (
s_st_rec3.f3'Right(1),s_st_rec3.f3'Right(2)) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00174" ,
"Inertial semantics check on a signal " &
"asg with indexed name prefixed by a selected name on LHS",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00174" ,
"Inertial semantics check on a signal " &
"asg with indexed name prefixed by a selected name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_st_rec3 <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
end Proc1 ;
--
begin
Proc1 ;
wait until (not s_st_rec3'Quiet) and
(savtime /= Std.Standard.Now) ;
--
end process P1 ;
--
PGEN_CHKP_1 :
process ( chk_st_rec3 )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P1" ,
"Inertial transactions entirely completed",
chk_st_rec3 = 8 ) ;
end if ;
end process PGEN_CHKP_1 ;
--
--
--
end ARCH00174 ;
--
entity ENT00174_Test_Bench is
end ENT00174_Test_Bench ;
--
architecture ARCH00174_Test_Bench of ENT00174_Test_Bench is
begin
L1:
block
component UUT
end component ;
for CIS1 : UUT use entity WORK.E00000 ( ARCH00174 ) ;
begin
CIS1 : UUT ;
end block L1 ;
end ARCH00174_Test_Bench ;
| gpl-3.0 | c92b1248f471924780cfe5e5e77a7750 | 0.446463 | 3.184982 | false | true | false | false |
grwlf/vsim | vhdl_ct/ct00037.vhd | 1 | 11,762 | -------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
-------------------------------------------------------------------------------
--
-- TEST NAME:
--
-- CT00037
--
-- AUTHOR:
--
-- G. Tominovich
--
-- TEST OBJECTIVES:
--
-- 8.4 (1)
-- 8.4 (3)
--
-- DESIGN UNIT ORDERING:
--
-- E00000(ARCH00037)
-- ENT00037_Test_Bench(ARCH00037_Test_Bench)
--
-- REVISION HISTORY:
--
-- 29-JUN-1987 - initial revision
--
-- NOTES:
--
-- self-checking
-- automatically generated
--
use WORK.STANDARD_TYPES.all ;
architecture ARCH00037 of E00000 is
signal Dummy : Boolean := false ;
--
begin
P1 :
process ( Dummy )
type arr_time is
array (integer range -1 downto - 3 ) of
time ;
type arr_st_rec1 is
array (integer range -1 downto - 3 ) of
st_rec1 ;
type arr_st_rec2 is
array (integer range -1 downto - 3 ) of
st_rec2 ;
--
variable v_st_rec1_1 : st_rec1 :=
c_st_rec1_1 ;
variable v_st_rec2_1 : st_rec2 :=
c_st_rec2_1 ;
variable v_st_rec3_1 : st_rec3 :=
c_st_rec3_1 ;
--
variable v_st_rec1_2 : st_rec1 :=
c_st_rec1_1 ;
variable v_st_rec2_2 : st_rec2 :=
c_st_rec2_1 ;
variable v_st_rec3_2 : st_rec3 :=
c_st_rec3_1 ;
--
variable v_st_rec1_3 : st_rec1 :=
c_st_rec1_1 ;
variable v_st_rec2_3 : st_rec2 :=
c_st_rec2_1 ;
variable v_st_rec3_3 : st_rec3 :=
c_st_rec3_1 ;
--
variable correct : boolean := true ;
begin
(
v_st_rec1_1.f2
, v_st_rec1_2.f2
, v_st_rec1_3.f2
) :=
arr_time ' (
(others => c_st_rec1_2.f2)) ;
--
(
v_st_rec2_1.f2
, v_st_rec2_2.f2
, v_st_rec2_3.f2
) :=
arr_st_rec1 ' (
(others => c_st_rec2_2.f2)) ;
--
(
v_st_rec3_1.f2
, v_st_rec3_2.f2
, v_st_rec3_3.f2
) :=
arr_st_rec2 ' (
(others => c_st_rec3_2.f2)) ;
--
--
correct := correct and
v_st_rec1_1.f2 =
c_st_rec1_2.f2 ;
correct := correct and
v_st_rec2_1.f2 =
c_st_rec2_2.f2 ;
correct := correct and
v_st_rec3_1.f2 =
c_st_rec3_2.f2 ;
--
correct := correct and
v_st_rec1_2.f2 =
c_st_rec1_2.f2 ;
correct := correct and
v_st_rec2_2.f2 =
c_st_rec2_2.f2 ;
correct := correct and
v_st_rec3_2.f2 =
c_st_rec3_2.f2 ;
--
correct := correct and
v_st_rec1_3.f2 =
c_st_rec1_2.f2 ;
correct := correct and
v_st_rec2_3.f2 =
c_st_rec2_2.f2 ;
correct := correct and
v_st_rec3_3.f2 =
c_st_rec3_2.f2 ;
--
test_report ( "ARCH00037.P1" ,
"Target of a variable assignment may be a " &
"aggregate of selected namess" ,
correct) ;
end process P1 ;
--
P2 :
process ( Dummy )
variable correct : boolean := true ;
--
procedure Proc1 is
type arr_time is
array (integer range -1 downto - 3 ) of
time ;
type arr_st_rec1 is
array (integer range -1 downto - 3 ) of
st_rec1 ;
type arr_st_rec2 is
array (integer range -1 downto - 3 ) of
st_rec2 ;
--
variable v_st_rec1_1 : st_rec1 :=
c_st_rec1_1 ;
variable v_st_rec2_1 : st_rec2 :=
c_st_rec2_1 ;
variable v_st_rec3_1 : st_rec3 :=
c_st_rec3_1 ;
--
variable v_st_rec1_2 : st_rec1 :=
c_st_rec1_1 ;
variable v_st_rec2_2 : st_rec2 :=
c_st_rec2_1 ;
variable v_st_rec3_2 : st_rec3 :=
c_st_rec3_1 ;
--
variable v_st_rec1_3 : st_rec1 :=
c_st_rec1_1 ;
variable v_st_rec2_3 : st_rec2 :=
c_st_rec2_1 ;
variable v_st_rec3_3 : st_rec3 :=
c_st_rec3_1 ;
--
begin
(
v_st_rec1_1.f2
, v_st_rec1_2.f2
, v_st_rec1_3.f2
) :=
arr_time ' (
(others => c_st_rec1_2.f2)) ;
--
(
v_st_rec2_1.f2
, v_st_rec2_2.f2
, v_st_rec2_3.f2
) :=
arr_st_rec1 ' (
(others => c_st_rec2_2.f2)) ;
--
(
v_st_rec3_1.f2
, v_st_rec3_2.f2
, v_st_rec3_3.f2
) :=
arr_st_rec2 ' (
(others => c_st_rec3_2.f2)) ;
--
--
correct := correct and
v_st_rec1_1.f2 =
c_st_rec1_2.f2 ;
correct := correct and
v_st_rec2_1.f2 =
c_st_rec2_2.f2 ;
correct := correct and
v_st_rec3_1.f2 =
c_st_rec3_2.f2 ;
--
correct := correct and
v_st_rec1_2.f2 =
c_st_rec1_2.f2 ;
correct := correct and
v_st_rec2_2.f2 =
c_st_rec2_2.f2 ;
correct := correct and
v_st_rec3_2.f2 =
c_st_rec3_2.f2 ;
--
correct := correct and
v_st_rec1_3.f2 =
c_st_rec1_2.f2 ;
correct := correct and
v_st_rec2_3.f2 =
c_st_rec2_2.f2 ;
correct := correct and
v_st_rec3_3.f2 =
c_st_rec3_2.f2 ;
--
end Proc1 ;
begin
Proc1 ;
test_report ( "ARCH00037.P2" ,
"Target of a variable assignment may be a " &
"aggregate of selected namess" ,
correct) ;
end process P2 ;
--
P3 :
process ( Dummy )
type arr_time is
array (integer range -1 downto - 3 ) of
time ;
type arr_st_rec1 is
array (integer range -1 downto - 3 ) of
st_rec1 ;
type arr_st_rec2 is
array (integer range -1 downto - 3 ) of
st_rec2 ;
--
variable v_st_rec1_1 : st_rec1 :=
c_st_rec1_1 ;
variable v_st_rec2_1 : st_rec2 :=
c_st_rec2_1 ;
variable v_st_rec3_1 : st_rec3 :=
c_st_rec3_1 ;
--
variable v_st_rec1_2 : st_rec1 :=
c_st_rec1_1 ;
variable v_st_rec2_2 : st_rec2 :=
c_st_rec2_1 ;
variable v_st_rec3_2 : st_rec3 :=
c_st_rec3_1 ;
--
variable v_st_rec1_3 : st_rec1 :=
c_st_rec1_1 ;
variable v_st_rec2_3 : st_rec2 :=
c_st_rec2_1 ;
variable v_st_rec3_3 : st_rec3 :=
c_st_rec3_1 ;
--
variable correct : boolean := true ;
--
procedure Proc1 is
begin
(
v_st_rec1_1.f2
, v_st_rec1_2.f2
, v_st_rec1_3.f2
) :=
arr_time ' (
(others => c_st_rec1_2.f2)) ;
--
(
v_st_rec2_1.f2
, v_st_rec2_2.f2
, v_st_rec2_3.f2
) :=
arr_st_rec1 ' (
(others => c_st_rec2_2.f2)) ;
--
(
v_st_rec3_1.f2
, v_st_rec3_2.f2
, v_st_rec3_3.f2
) :=
arr_st_rec2 ' (
(others => c_st_rec3_2.f2)) ;
--
--
end Proc1 ;
begin
Proc1 ;
correct := correct and
v_st_rec1_1.f2 =
c_st_rec1_2.f2 ;
correct := correct and
v_st_rec2_1.f2 =
c_st_rec2_2.f2 ;
correct := correct and
v_st_rec3_1.f2 =
c_st_rec3_2.f2 ;
--
correct := correct and
v_st_rec1_2.f2 =
c_st_rec1_2.f2 ;
correct := correct and
v_st_rec2_2.f2 =
c_st_rec2_2.f2 ;
correct := correct and
v_st_rec3_2.f2 =
c_st_rec3_2.f2 ;
--
correct := correct and
v_st_rec1_3.f2 =
c_st_rec1_2.f2 ;
correct := correct and
v_st_rec2_3.f2 =
c_st_rec2_2.f2 ;
correct := correct and
v_st_rec3_3.f2 =
c_st_rec3_2.f2 ;
--
test_report ( "ARCH00037.P3" ,
"Target of a variable assignment may be a " &
"aggregate of selected namess" ,
correct) ;
end process P3 ;
--
P4 :
process ( Dummy )
type arr_time is
array (integer range -1 downto - 3 ) of
time ;
type arr_st_rec1 is
array (integer range -1 downto - 3 ) of
st_rec1 ;
type arr_st_rec2 is
array (integer range -1 downto - 3 ) of
st_rec2 ;
--
variable v_st_rec1_1 : st_rec1 :=
c_st_rec1_1 ;
variable v_st_rec2_1 : st_rec2 :=
c_st_rec2_1 ;
variable v_st_rec3_1 : st_rec3 :=
c_st_rec3_1 ;
--
variable v_st_rec1_2 : st_rec1 :=
c_st_rec1_1 ;
variable v_st_rec2_2 : st_rec2 :=
c_st_rec2_1 ;
variable v_st_rec3_2 : st_rec3 :=
c_st_rec3_1 ;
--
variable v_st_rec1_3 : st_rec1 :=
c_st_rec1_1 ;
variable v_st_rec2_3 : st_rec2 :=
c_st_rec2_1 ;
variable v_st_rec3_3 : st_rec3 :=
c_st_rec3_1 ;
--
variable correct : boolean := true ;
--
procedure Proc1 (
v_st_rec1_2 : inout st_rec1
; v_st_rec2_2 : inout st_rec2
; v_st_rec3_2 : inout st_rec3
)
is
begin
(
v_st_rec1_1.f2
, v_st_rec1_2.f2
, v_st_rec1_3.f2
) :=
arr_time ' (
(others => c_st_rec1_2.f2)) ;
--
(
v_st_rec2_1.f2
, v_st_rec2_2.f2
, v_st_rec2_3.f2
) :=
arr_st_rec1 ' (
(others => c_st_rec2_2.f2)) ;
--
(
v_st_rec3_1.f2
, v_st_rec3_2.f2
, v_st_rec3_3.f2
) :=
arr_st_rec2 ' (
(others => c_st_rec3_2.f2)) ;
--
--
end Proc1 ;
begin
Proc1 (
v_st_rec1_2
, v_st_rec2_2
, v_st_rec3_2
) ;
correct := correct and
v_st_rec1_1.f2 =
c_st_rec1_2.f2 ;
correct := correct and
v_st_rec2_1.f2 =
c_st_rec2_2.f2 ;
correct := correct and
v_st_rec3_1.f2 =
c_st_rec3_2.f2 ;
--
correct := correct and
v_st_rec1_2.f2 =
c_st_rec1_2.f2 ;
correct := correct and
v_st_rec2_2.f2 =
c_st_rec2_2.f2 ;
correct := correct and
v_st_rec3_2.f2 =
c_st_rec3_2.f2 ;
--
correct := correct and
v_st_rec1_3.f2 =
c_st_rec1_2.f2 ;
correct := correct and
v_st_rec2_3.f2 =
c_st_rec2_2.f2 ;
correct := correct and
v_st_rec3_3.f2 =
c_st_rec3_2.f2 ;
--
test_report ( "ARCH00037.P4" ,
"Target of a variable assignment may be a " &
"aggregate of selected namess" ,
correct) ;
end process P4 ;
--
end ARCH00037 ;
--
entity ENT00037_Test_Bench is
end ENT00037_Test_Bench ;
--
architecture ARCH00037_Test_Bench of ENT00037_Test_Bench is
begin
L1:
block
component UUT
end component ;
for CIS1 : UUT use entity WORK.E00000 ( ARCH00037 ) ;
begin
CIS1 : UUT ;
end block L1 ;
end ARCH00037_Test_Bench ;
| gpl-3.0 | 2b70250363042232e338377862cdd1fd | 0.419316 | 2.971703 | false | false | false | false |
TWW12/lzw | ip_repo/axi_compression_1.0/src/output_fifo/synth/output_fifo.vhd | 2 | 38,780 | -- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:fifo_generator:13.1
-- IP Revision: 3
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY fifo_generator_v13_1_3;
USE fifo_generator_v13_1_3.fifo_generator_v13_1_3;
ENTITY output_fifo IS
PORT (
clk : IN STD_LOGIC;
srst : IN STD_LOGIC;
din : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
wr_en : IN STD_LOGIC;
rd_en : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
full : OUT STD_LOGIC;
empty : OUT STD_LOGIC
);
END output_fifo;
ARCHITECTURE output_fifo_arch OF output_fifo IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF output_fifo_arch: ARCHITECTURE IS "yes";
COMPONENT fifo_generator_v13_1_3 IS
GENERIC (
C_COMMON_CLOCK : INTEGER;
C_SELECT_XPM : INTEGER;
C_COUNT_TYPE : INTEGER;
C_DATA_COUNT_WIDTH : INTEGER;
C_DEFAULT_VALUE : STRING;
C_DIN_WIDTH : INTEGER;
C_DOUT_RST_VAL : STRING;
C_DOUT_WIDTH : INTEGER;
C_ENABLE_RLOCS : INTEGER;
C_FAMILY : STRING;
C_FULL_FLAGS_RST_VAL : INTEGER;
C_HAS_ALMOST_EMPTY : INTEGER;
C_HAS_ALMOST_FULL : INTEGER;
C_HAS_BACKUP : INTEGER;
C_HAS_DATA_COUNT : INTEGER;
C_HAS_INT_CLK : INTEGER;
C_HAS_MEMINIT_FILE : INTEGER;
C_HAS_OVERFLOW : INTEGER;
C_HAS_RD_DATA_COUNT : INTEGER;
C_HAS_RD_RST : INTEGER;
C_HAS_RST : INTEGER;
C_HAS_SRST : INTEGER;
C_HAS_UNDERFLOW : INTEGER;
C_HAS_VALID : INTEGER;
C_HAS_WR_ACK : INTEGER;
C_HAS_WR_DATA_COUNT : INTEGER;
C_HAS_WR_RST : INTEGER;
C_IMPLEMENTATION_TYPE : INTEGER;
C_INIT_WR_PNTR_VAL : INTEGER;
C_MEMORY_TYPE : INTEGER;
C_MIF_FILE_NAME : STRING;
C_OPTIMIZATION_MODE : INTEGER;
C_OVERFLOW_LOW : INTEGER;
C_PRELOAD_LATENCY : INTEGER;
C_PRELOAD_REGS : INTEGER;
C_PRIM_FIFO_TYPE : STRING;
C_PROG_EMPTY_THRESH_ASSERT_VAL : INTEGER;
C_PROG_EMPTY_THRESH_NEGATE_VAL : INTEGER;
C_PROG_EMPTY_TYPE : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL : INTEGER;
C_PROG_FULL_THRESH_NEGATE_VAL : INTEGER;
C_PROG_FULL_TYPE : INTEGER;
C_RD_DATA_COUNT_WIDTH : INTEGER;
C_RD_DEPTH : INTEGER;
C_RD_FREQ : INTEGER;
C_RD_PNTR_WIDTH : INTEGER;
C_UNDERFLOW_LOW : INTEGER;
C_USE_DOUT_RST : INTEGER;
C_USE_ECC : INTEGER;
C_USE_EMBEDDED_REG : INTEGER;
C_USE_PIPELINE_REG : INTEGER;
C_POWER_SAVING_MODE : INTEGER;
C_USE_FIFO16_FLAGS : INTEGER;
C_USE_FWFT_DATA_COUNT : INTEGER;
C_VALID_LOW : INTEGER;
C_WR_ACK_LOW : INTEGER;
C_WR_DATA_COUNT_WIDTH : INTEGER;
C_WR_DEPTH : INTEGER;
C_WR_FREQ : INTEGER;
C_WR_PNTR_WIDTH : INTEGER;
C_WR_RESPONSE_LATENCY : INTEGER;
C_MSGON_VAL : INTEGER;
C_ENABLE_RST_SYNC : INTEGER;
C_EN_SAFETY_CKT : INTEGER;
C_ERROR_INJECTION_TYPE : INTEGER;
C_SYNCHRONIZER_STAGE : INTEGER;
C_INTERFACE_TYPE : INTEGER;
C_AXI_TYPE : INTEGER;
C_HAS_AXI_WR_CHANNEL : INTEGER;
C_HAS_AXI_RD_CHANNEL : INTEGER;
C_HAS_SLAVE_CE : INTEGER;
C_HAS_MASTER_CE : INTEGER;
C_ADD_NGC_CONSTRAINT : INTEGER;
C_USE_COMMON_OVERFLOW : INTEGER;
C_USE_COMMON_UNDERFLOW : INTEGER;
C_USE_DEFAULT_SETTINGS : INTEGER;
C_AXI_ID_WIDTH : INTEGER;
C_AXI_ADDR_WIDTH : INTEGER;
C_AXI_DATA_WIDTH : INTEGER;
C_AXI_LEN_WIDTH : INTEGER;
C_AXI_LOCK_WIDTH : INTEGER;
C_HAS_AXI_ID : INTEGER;
C_HAS_AXI_AWUSER : INTEGER;
C_HAS_AXI_WUSER : INTEGER;
C_HAS_AXI_BUSER : INTEGER;
C_HAS_AXI_ARUSER : INTEGER;
C_HAS_AXI_RUSER : INTEGER;
C_AXI_ARUSER_WIDTH : INTEGER;
C_AXI_AWUSER_WIDTH : INTEGER;
C_AXI_WUSER_WIDTH : INTEGER;
C_AXI_BUSER_WIDTH : INTEGER;
C_AXI_RUSER_WIDTH : INTEGER;
C_HAS_AXIS_TDATA : INTEGER;
C_HAS_AXIS_TID : INTEGER;
C_HAS_AXIS_TDEST : INTEGER;
C_HAS_AXIS_TUSER : INTEGER;
C_HAS_AXIS_TREADY : INTEGER;
C_HAS_AXIS_TLAST : INTEGER;
C_HAS_AXIS_TSTRB : INTEGER;
C_HAS_AXIS_TKEEP : INTEGER;
C_AXIS_TDATA_WIDTH : INTEGER;
C_AXIS_TID_WIDTH : INTEGER;
C_AXIS_TDEST_WIDTH : INTEGER;
C_AXIS_TUSER_WIDTH : INTEGER;
C_AXIS_TSTRB_WIDTH : INTEGER;
C_AXIS_TKEEP_WIDTH : INTEGER;
C_WACH_TYPE : INTEGER;
C_WDCH_TYPE : INTEGER;
C_WRCH_TYPE : INTEGER;
C_RACH_TYPE : INTEGER;
C_RDCH_TYPE : INTEGER;
C_AXIS_TYPE : INTEGER;
C_IMPLEMENTATION_TYPE_WACH : INTEGER;
C_IMPLEMENTATION_TYPE_WDCH : INTEGER;
C_IMPLEMENTATION_TYPE_WRCH : INTEGER;
C_IMPLEMENTATION_TYPE_RACH : INTEGER;
C_IMPLEMENTATION_TYPE_RDCH : INTEGER;
C_IMPLEMENTATION_TYPE_AXIS : INTEGER;
C_APPLICATION_TYPE_WACH : INTEGER;
C_APPLICATION_TYPE_WDCH : INTEGER;
C_APPLICATION_TYPE_WRCH : INTEGER;
C_APPLICATION_TYPE_RACH : INTEGER;
C_APPLICATION_TYPE_RDCH : INTEGER;
C_APPLICATION_TYPE_AXIS : INTEGER;
C_PRIM_FIFO_TYPE_WACH : STRING;
C_PRIM_FIFO_TYPE_WDCH : STRING;
C_PRIM_FIFO_TYPE_WRCH : STRING;
C_PRIM_FIFO_TYPE_RACH : STRING;
C_PRIM_FIFO_TYPE_RDCH : STRING;
C_PRIM_FIFO_TYPE_AXIS : STRING;
C_USE_ECC_WACH : INTEGER;
C_USE_ECC_WDCH : INTEGER;
C_USE_ECC_WRCH : INTEGER;
C_USE_ECC_RACH : INTEGER;
C_USE_ECC_RDCH : INTEGER;
C_USE_ECC_AXIS : INTEGER;
C_ERROR_INJECTION_TYPE_WACH : INTEGER;
C_ERROR_INJECTION_TYPE_WDCH : INTEGER;
C_ERROR_INJECTION_TYPE_WRCH : INTEGER;
C_ERROR_INJECTION_TYPE_RACH : INTEGER;
C_ERROR_INJECTION_TYPE_RDCH : INTEGER;
C_ERROR_INJECTION_TYPE_AXIS : INTEGER;
C_DIN_WIDTH_WACH : INTEGER;
C_DIN_WIDTH_WDCH : INTEGER;
C_DIN_WIDTH_WRCH : INTEGER;
C_DIN_WIDTH_RACH : INTEGER;
C_DIN_WIDTH_RDCH : INTEGER;
C_DIN_WIDTH_AXIS : INTEGER;
C_WR_DEPTH_WACH : INTEGER;
C_WR_DEPTH_WDCH : INTEGER;
C_WR_DEPTH_WRCH : INTEGER;
C_WR_DEPTH_RACH : INTEGER;
C_WR_DEPTH_RDCH : INTEGER;
C_WR_DEPTH_AXIS : INTEGER;
C_WR_PNTR_WIDTH_WACH : INTEGER;
C_WR_PNTR_WIDTH_WDCH : INTEGER;
C_WR_PNTR_WIDTH_WRCH : INTEGER;
C_WR_PNTR_WIDTH_RACH : INTEGER;
C_WR_PNTR_WIDTH_RDCH : INTEGER;
C_WR_PNTR_WIDTH_AXIS : INTEGER;
C_HAS_DATA_COUNTS_WACH : INTEGER;
C_HAS_DATA_COUNTS_WDCH : INTEGER;
C_HAS_DATA_COUNTS_WRCH : INTEGER;
C_HAS_DATA_COUNTS_RACH : INTEGER;
C_HAS_DATA_COUNTS_RDCH : INTEGER;
C_HAS_DATA_COUNTS_AXIS : INTEGER;
C_HAS_PROG_FLAGS_WACH : INTEGER;
C_HAS_PROG_FLAGS_WDCH : INTEGER;
C_HAS_PROG_FLAGS_WRCH : INTEGER;
C_HAS_PROG_FLAGS_RACH : INTEGER;
C_HAS_PROG_FLAGS_RDCH : INTEGER;
C_HAS_PROG_FLAGS_AXIS : INTEGER;
C_PROG_FULL_TYPE_WACH : INTEGER;
C_PROG_FULL_TYPE_WDCH : INTEGER;
C_PROG_FULL_TYPE_WRCH : INTEGER;
C_PROG_FULL_TYPE_RACH : INTEGER;
C_PROG_FULL_TYPE_RDCH : INTEGER;
C_PROG_FULL_TYPE_AXIS : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL_WACH : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL_WDCH : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL_WRCH : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL_RACH : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL_RDCH : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL_AXIS : INTEGER;
C_PROG_EMPTY_TYPE_WACH : INTEGER;
C_PROG_EMPTY_TYPE_WDCH : INTEGER;
C_PROG_EMPTY_TYPE_WRCH : INTEGER;
C_PROG_EMPTY_TYPE_RACH : INTEGER;
C_PROG_EMPTY_TYPE_RDCH : INTEGER;
C_PROG_EMPTY_TYPE_AXIS : INTEGER;
C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH : INTEGER;
C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH : INTEGER;
C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH : INTEGER;
C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH : INTEGER;
C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH : INTEGER;
C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS : INTEGER;
C_REG_SLICE_MODE_WACH : INTEGER;
C_REG_SLICE_MODE_WDCH : INTEGER;
C_REG_SLICE_MODE_WRCH : INTEGER;
C_REG_SLICE_MODE_RACH : INTEGER;
C_REG_SLICE_MODE_RDCH : INTEGER;
C_REG_SLICE_MODE_AXIS : INTEGER
);
PORT (
backup : IN STD_LOGIC;
backup_marker : IN STD_LOGIC;
clk : IN STD_LOGIC;
rst : IN STD_LOGIC;
srst : IN STD_LOGIC;
wr_clk : IN STD_LOGIC;
wr_rst : IN STD_LOGIC;
rd_clk : IN STD_LOGIC;
rd_rst : IN STD_LOGIC;
din : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
wr_en : IN STD_LOGIC;
rd_en : IN STD_LOGIC;
prog_empty_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
prog_empty_thresh_assert : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
prog_empty_thresh_negate : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
prog_full_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
prog_full_thresh_assert : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
prog_full_thresh_negate : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
int_clk : IN STD_LOGIC;
injectdbiterr : IN STD_LOGIC;
injectsbiterr : IN STD_LOGIC;
sleep : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
full : OUT STD_LOGIC;
almost_full : OUT STD_LOGIC;
wr_ack : OUT STD_LOGIC;
overflow : OUT STD_LOGIC;
empty : OUT STD_LOGIC;
almost_empty : OUT STD_LOGIC;
valid : OUT STD_LOGIC;
underflow : OUT STD_LOGIC;
data_count : OUT STD_LOGIC_VECTOR(9 DOWNTO 0);
rd_data_count : OUT STD_LOGIC_VECTOR(9 DOWNTO 0);
wr_data_count : OUT STD_LOGIC_VECTOR(9 DOWNTO 0);
prog_full : OUT STD_LOGIC;
prog_empty : OUT STD_LOGIC;
sbiterr : OUT STD_LOGIC;
dbiterr : OUT STD_LOGIC;
wr_rst_busy : OUT STD_LOGIC;
rd_rst_busy : OUT STD_LOGIC;
m_aclk : IN STD_LOGIC;
s_aclk : IN STD_LOGIC;
s_aresetn : IN STD_LOGIC;
m_aclk_en : IN STD_LOGIC;
s_aclk_en : IN STD_LOGIC;
s_axi_awid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_awaddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_awlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_awsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_awburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_awlock : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_awcache : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_awprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_awqos : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_awregion : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_awuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_wdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_wlast : IN STD_LOGIC;
s_axi_wuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_buser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
m_axi_awid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_awaddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_awlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axi_awsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_awburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_awlock : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_awcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_awprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_awqos : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_awregion : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_awuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_awvalid : OUT STD_LOGIC;
m_axi_awready : IN STD_LOGIC;
m_axi_wid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_wdata : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
m_axi_wstrb : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axi_wlast : OUT STD_LOGIC;
m_axi_wuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_wvalid : OUT STD_LOGIC;
m_axi_wready : IN STD_LOGIC;
m_axi_bid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_bresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_buser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_bvalid : IN STD_LOGIC;
m_axi_bready : OUT STD_LOGIC;
s_axi_arid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_araddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_arlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_arsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_arburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_arlock : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_arcache : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_arprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_arqos : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_arregion : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_aruser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_rdata : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rlast : OUT STD_LOGIC;
s_axi_ruser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
m_axi_arid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_araddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_arlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axi_arsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_arburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_arlock : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_arcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_arprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_arqos : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_arregion : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_aruser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_arvalid : OUT STD_LOGIC;
m_axi_arready : IN STD_LOGIC;
m_axi_rid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_rdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
m_axi_rresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_rlast : IN STD_LOGIC;
m_axi_ruser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_rvalid : IN STD_LOGIC;
m_axi_rready : OUT STD_LOGIC;
s_axis_tvalid : IN STD_LOGIC;
s_axis_tready : OUT STD_LOGIC;
s_axis_tdata : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axis_tstrb : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_tkeep : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_tlast : IN STD_LOGIC;
s_axis_tid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_tdest : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_tuser : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axis_tvalid : OUT STD_LOGIC;
m_axis_tready : IN STD_LOGIC;
m_axis_tdata : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axis_tstrb : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_tkeep : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_tlast : OUT STD_LOGIC;
m_axis_tid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_tdest : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_tuser : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_aw_injectsbiterr : IN STD_LOGIC;
axi_aw_injectdbiterr : IN STD_LOGIC;
axi_aw_prog_full_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_aw_prog_empty_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_aw_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_aw_wr_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_aw_rd_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_aw_sbiterr : OUT STD_LOGIC;
axi_aw_dbiterr : OUT STD_LOGIC;
axi_aw_overflow : OUT STD_LOGIC;
axi_aw_underflow : OUT STD_LOGIC;
axi_aw_prog_full : OUT STD_LOGIC;
axi_aw_prog_empty : OUT STD_LOGIC;
axi_w_injectsbiterr : IN STD_LOGIC;
axi_w_injectdbiterr : IN STD_LOGIC;
axi_w_prog_full_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
axi_w_prog_empty_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
axi_w_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axi_w_wr_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axi_w_rd_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axi_w_sbiterr : OUT STD_LOGIC;
axi_w_dbiterr : OUT STD_LOGIC;
axi_w_overflow : OUT STD_LOGIC;
axi_w_underflow : OUT STD_LOGIC;
axi_w_prog_full : OUT STD_LOGIC;
axi_w_prog_empty : OUT STD_LOGIC;
axi_b_injectsbiterr : IN STD_LOGIC;
axi_b_injectdbiterr : IN STD_LOGIC;
axi_b_prog_full_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_b_prog_empty_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_b_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_b_wr_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_b_rd_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_b_sbiterr : OUT STD_LOGIC;
axi_b_dbiterr : OUT STD_LOGIC;
axi_b_overflow : OUT STD_LOGIC;
axi_b_underflow : OUT STD_LOGIC;
axi_b_prog_full : OUT STD_LOGIC;
axi_b_prog_empty : OUT STD_LOGIC;
axi_ar_injectsbiterr : IN STD_LOGIC;
axi_ar_injectdbiterr : IN STD_LOGIC;
axi_ar_prog_full_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_ar_prog_empty_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_ar_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_ar_wr_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_ar_rd_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_ar_sbiterr : OUT STD_LOGIC;
axi_ar_dbiterr : OUT STD_LOGIC;
axi_ar_overflow : OUT STD_LOGIC;
axi_ar_underflow : OUT STD_LOGIC;
axi_ar_prog_full : OUT STD_LOGIC;
axi_ar_prog_empty : OUT STD_LOGIC;
axi_r_injectsbiterr : IN STD_LOGIC;
axi_r_injectdbiterr : IN STD_LOGIC;
axi_r_prog_full_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
axi_r_prog_empty_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
axi_r_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axi_r_wr_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axi_r_rd_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axi_r_sbiterr : OUT STD_LOGIC;
axi_r_dbiterr : OUT STD_LOGIC;
axi_r_overflow : OUT STD_LOGIC;
axi_r_underflow : OUT STD_LOGIC;
axi_r_prog_full : OUT STD_LOGIC;
axi_r_prog_empty : OUT STD_LOGIC;
axis_injectsbiterr : IN STD_LOGIC;
axis_injectdbiterr : IN STD_LOGIC;
axis_prog_full_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
axis_prog_empty_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
axis_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axis_wr_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axis_rd_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axis_sbiterr : OUT STD_LOGIC;
axis_dbiterr : OUT STD_LOGIC;
axis_overflow : OUT STD_LOGIC;
axis_underflow : OUT STD_LOGIC;
axis_prog_full : OUT STD_LOGIC;
axis_prog_empty : OUT STD_LOGIC
);
END COMPONENT fifo_generator_v13_1_3;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF output_fifo_arch: ARCHITECTURE IS "fifo_generator_v13_1_3,Vivado 2016.4";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF output_fifo_arch : ARCHITECTURE IS "output_fifo,fifo_generator_v13_1_3,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF output_fifo_arch: ARCHITECTURE IS "output_fifo,fifo_generator_v13_1_3,{x_ipProduct=Vivado 2016.4,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=fifo_generator,x_ipVersion=13.1,x_ipCoreRevision=3,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,C_COMMON_CLOCK=1,C_SELECT_XPM=0,C_COUNT_TYPE=0,C_DATA_COUNT_WIDTH=10,C_DEFAULT_VALUE=BlankString,C_DIN_WIDTH=12,C_DOUT_RST_VAL=0,C_DOUT_WIDTH=12,C_ENABLE_RLOCS=0,C_FAMILY=zynq,C_FULL_FLAGS_RST_VAL=0,C_HAS_ALMOST_EMPTY=0,C_HAS_ALMOST_FULL=0,C_HAS_BACKUP=0,C_HAS_DATA_COUNT=0,C_HAS_INT_CLK=0,C_HAS_MEMIN" &
"IT_FILE=0,C_HAS_OVERFLOW=0,C_HAS_RD_DATA_COUNT=0,C_HAS_RD_RST=0,C_HAS_RST=0,C_HAS_SRST=1,C_HAS_UNDERFLOW=0,C_HAS_VALID=0,C_HAS_WR_ACK=0,C_HAS_WR_DATA_COUNT=0,C_HAS_WR_RST=0,C_IMPLEMENTATION_TYPE=0,C_INIT_WR_PNTR_VAL=0,C_MEMORY_TYPE=1,C_MIF_FILE_NAME=BlankString,C_OPTIMIZATION_MODE=0,C_OVERFLOW_LOW=0,C_PRELOAD_LATENCY=2,C_PRELOAD_REGS=1,C_PRIM_FIFO_TYPE=1kx18,C_PROG_EMPTY_THRESH_ASSERT_VAL=2,C_PROG_EMPTY_THRESH_NEGATE_VAL=3,C_PROG_EMPTY_TYPE=0,C_PROG_FULL_THRESH_ASSERT_VAL=1022,C_PROG_FULL_THRESH" &
"_NEGATE_VAL=1021,C_PROG_FULL_TYPE=0,C_RD_DATA_COUNT_WIDTH=10,C_RD_DEPTH=1024,C_RD_FREQ=1,C_RD_PNTR_WIDTH=10,C_UNDERFLOW_LOW=0,C_USE_DOUT_RST=1,C_USE_ECC=0,C_USE_EMBEDDED_REG=1,C_USE_PIPELINE_REG=0,C_POWER_SAVING_MODE=0,C_USE_FIFO16_FLAGS=0,C_USE_FWFT_DATA_COUNT=0,C_VALID_LOW=0,C_WR_ACK_LOW=0,C_WR_DATA_COUNT_WIDTH=10,C_WR_DEPTH=1024,C_WR_FREQ=1,C_WR_PNTR_WIDTH=10,C_WR_RESPONSE_LATENCY=1,C_MSGON_VAL=1,C_ENABLE_RST_SYNC=1,C_EN_SAFETY_CKT=0,C_ERROR_INJECTION_TYPE=0,C_SYNCHRONIZER_STAGE=2,C_INTERFACE" &
"_TYPE=0,C_AXI_TYPE=1,C_HAS_AXI_WR_CHANNEL=1,C_HAS_AXI_RD_CHANNEL=1,C_HAS_SLAVE_CE=0,C_HAS_MASTER_CE=0,C_ADD_NGC_CONSTRAINT=0,C_USE_COMMON_OVERFLOW=0,C_USE_COMMON_UNDERFLOW=0,C_USE_DEFAULT_SETTINGS=0,C_AXI_ID_WIDTH=1,C_AXI_ADDR_WIDTH=32,C_AXI_DATA_WIDTH=64,C_AXI_LEN_WIDTH=8,C_AXI_LOCK_WIDTH=1,C_HAS_AXI_ID=0,C_HAS_AXI_AWUSER=0,C_HAS_AXI_WUSER=0,C_HAS_AXI_BUSER=0,C_HAS_AXI_ARUSER=0,C_HAS_AXI_RUSER=0,C_AXI_ARUSER_WIDTH=1,C_AXI_AWUSER_WIDTH=1,C_AXI_WUSER_WIDTH=1,C_AXI_BUSER_WIDTH=1,C_AXI_RUSER_WIDTH=" &
"1,C_HAS_AXIS_TDATA=1,C_HAS_AXIS_TID=0,C_HAS_AXIS_TDEST=0,C_HAS_AXIS_TUSER=1,C_HAS_AXIS_TREADY=1,C_HAS_AXIS_TLAST=0,C_HAS_AXIS_TSTRB=0,C_HAS_AXIS_TKEEP=0,C_AXIS_TDATA_WIDTH=8,C_AXIS_TID_WIDTH=1,C_AXIS_TDEST_WIDTH=1,C_AXIS_TUSER_WIDTH=4,C_AXIS_TSTRB_WIDTH=1,C_AXIS_TKEEP_WIDTH=1,C_WACH_TYPE=0,C_WDCH_TYPE=0,C_WRCH_TYPE=0,C_RACH_TYPE=0,C_RDCH_TYPE=0,C_AXIS_TYPE=0,C_IMPLEMENTATION_TYPE_WACH=1,C_IMPLEMENTATION_TYPE_WDCH=1,C_IMPLEMENTATION_TYPE_WRCH=1,C_IMPLEMENTATION_TYPE_RACH=1,C_IMPLEMENTATION_TYPE_R" &
"DCH=1,C_IMPLEMENTATION_TYPE_AXIS=1,C_APPLICATION_TYPE_WACH=0,C_APPLICATION_TYPE_WDCH=0,C_APPLICATION_TYPE_WRCH=0,C_APPLICATION_TYPE_RACH=0,C_APPLICATION_TYPE_RDCH=0,C_APPLICATION_TYPE_AXIS=0,C_PRIM_FIFO_TYPE_WACH=512x36,C_PRIM_FIFO_TYPE_WDCH=1kx36,C_PRIM_FIFO_TYPE_WRCH=512x36,C_PRIM_FIFO_TYPE_RACH=512x36,C_PRIM_FIFO_TYPE_RDCH=1kx36,C_PRIM_FIFO_TYPE_AXIS=1kx18,C_USE_ECC_WACH=0,C_USE_ECC_WDCH=0,C_USE_ECC_WRCH=0,C_USE_ECC_RACH=0,C_USE_ECC_RDCH=0,C_USE_ECC_AXIS=0,C_ERROR_INJECTION_TYPE_WACH=0,C_ERRO" &
"R_INJECTION_TYPE_WDCH=0,C_ERROR_INJECTION_TYPE_WRCH=0,C_ERROR_INJECTION_TYPE_RACH=0,C_ERROR_INJECTION_TYPE_RDCH=0,C_ERROR_INJECTION_TYPE_AXIS=0,C_DIN_WIDTH_WACH=1,C_DIN_WIDTH_WDCH=64,C_DIN_WIDTH_WRCH=2,C_DIN_WIDTH_RACH=32,C_DIN_WIDTH_RDCH=64,C_DIN_WIDTH_AXIS=1,C_WR_DEPTH_WACH=16,C_WR_DEPTH_WDCH=1024,C_WR_DEPTH_WRCH=16,C_WR_DEPTH_RACH=16,C_WR_DEPTH_RDCH=1024,C_WR_DEPTH_AXIS=1024,C_WR_PNTR_WIDTH_WACH=4,C_WR_PNTR_WIDTH_WDCH=10,C_WR_PNTR_WIDTH_WRCH=4,C_WR_PNTR_WIDTH_RACH=4,C_WR_PNTR_WIDTH_RDCH=10,C_" &
"WR_PNTR_WIDTH_AXIS=10,C_HAS_DATA_COUNTS_WACH=0,C_HAS_DATA_COUNTS_WDCH=0,C_HAS_DATA_COUNTS_WRCH=0,C_HAS_DATA_COUNTS_RACH=0,C_HAS_DATA_COUNTS_RDCH=0,C_HAS_DATA_COUNTS_AXIS=0,C_HAS_PROG_FLAGS_WACH=0,C_HAS_PROG_FLAGS_WDCH=0,C_HAS_PROG_FLAGS_WRCH=0,C_HAS_PROG_FLAGS_RACH=0,C_HAS_PROG_FLAGS_RDCH=0,C_HAS_PROG_FLAGS_AXIS=0,C_PROG_FULL_TYPE_WACH=0,C_PROG_FULL_TYPE_WDCH=0,C_PROG_FULL_TYPE_WRCH=0,C_PROG_FULL_TYPE_RACH=0,C_PROG_FULL_TYPE_RDCH=0,C_PROG_FULL_TYPE_AXIS=0,C_PROG_FULL_THRESH_ASSERT_VAL_WACH=1023," &
"C_PROG_FULL_THRESH_ASSERT_VAL_WDCH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_WRCH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_RACH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_RDCH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_AXIS=1023,C_PROG_EMPTY_TYPE_WACH=0,C_PROG_EMPTY_TYPE_WDCH=0,C_PROG_EMPTY_TYPE_WRCH=0,C_PROG_EMPTY_TYPE_RACH=0,C_PROG_EMPTY_TYPE_RDCH=0,C_PROG_EMPTY_TYPE_AXIS=0,C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH=1022,C_PROG_EMPTY_THRESH_ASSERT_" &
"VAL_RACH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS=1022,C_REG_SLICE_MODE_WACH=0,C_REG_SLICE_MODE_WDCH=0,C_REG_SLICE_MODE_WRCH=0,C_REG_SLICE_MODE_RACH=0,C_REG_SLICE_MODE_RDCH=0,C_REG_SLICE_MODE_AXIS=0}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF clk: SIGNAL IS "xilinx.com:signal:clock:1.0 core_clk CLK";
ATTRIBUTE X_INTERFACE_INFO OF din: SIGNAL IS "xilinx.com:interface:fifo_write:1.0 FIFO_WRITE WR_DATA";
ATTRIBUTE X_INTERFACE_INFO OF wr_en: SIGNAL IS "xilinx.com:interface:fifo_write:1.0 FIFO_WRITE WR_EN";
ATTRIBUTE X_INTERFACE_INFO OF rd_en: SIGNAL IS "xilinx.com:interface:fifo_read:1.0 FIFO_READ RD_EN";
ATTRIBUTE X_INTERFACE_INFO OF dout: SIGNAL IS "xilinx.com:interface:fifo_read:1.0 FIFO_READ RD_DATA";
ATTRIBUTE X_INTERFACE_INFO OF full: SIGNAL IS "xilinx.com:interface:fifo_write:1.0 FIFO_WRITE FULL";
ATTRIBUTE X_INTERFACE_INFO OF empty: SIGNAL IS "xilinx.com:interface:fifo_read:1.0 FIFO_READ EMPTY";
BEGIN
U0 : fifo_generator_v13_1_3
GENERIC MAP (
C_COMMON_CLOCK => 1,
C_SELECT_XPM => 0,
C_COUNT_TYPE => 0,
C_DATA_COUNT_WIDTH => 10,
C_DEFAULT_VALUE => "BlankString",
C_DIN_WIDTH => 12,
C_DOUT_RST_VAL => "0",
C_DOUT_WIDTH => 12,
C_ENABLE_RLOCS => 0,
C_FAMILY => "zynq",
C_FULL_FLAGS_RST_VAL => 0,
C_HAS_ALMOST_EMPTY => 0,
C_HAS_ALMOST_FULL => 0,
C_HAS_BACKUP => 0,
C_HAS_DATA_COUNT => 0,
C_HAS_INT_CLK => 0,
C_HAS_MEMINIT_FILE => 0,
C_HAS_OVERFLOW => 0,
C_HAS_RD_DATA_COUNT => 0,
C_HAS_RD_RST => 0,
C_HAS_RST => 0,
C_HAS_SRST => 1,
C_HAS_UNDERFLOW => 0,
C_HAS_VALID => 0,
C_HAS_WR_ACK => 0,
C_HAS_WR_DATA_COUNT => 0,
C_HAS_WR_RST => 0,
C_IMPLEMENTATION_TYPE => 0,
C_INIT_WR_PNTR_VAL => 0,
C_MEMORY_TYPE => 1,
C_MIF_FILE_NAME => "BlankString",
C_OPTIMIZATION_MODE => 0,
C_OVERFLOW_LOW => 0,
C_PRELOAD_LATENCY => 2,
C_PRELOAD_REGS => 1,
C_PRIM_FIFO_TYPE => "1kx18",
C_PROG_EMPTY_THRESH_ASSERT_VAL => 2,
C_PROG_EMPTY_THRESH_NEGATE_VAL => 3,
C_PROG_EMPTY_TYPE => 0,
C_PROG_FULL_THRESH_ASSERT_VAL => 1022,
C_PROG_FULL_THRESH_NEGATE_VAL => 1021,
C_PROG_FULL_TYPE => 0,
C_RD_DATA_COUNT_WIDTH => 10,
C_RD_DEPTH => 1024,
C_RD_FREQ => 1,
C_RD_PNTR_WIDTH => 10,
C_UNDERFLOW_LOW => 0,
C_USE_DOUT_RST => 1,
C_USE_ECC => 0,
C_USE_EMBEDDED_REG => 1,
C_USE_PIPELINE_REG => 0,
C_POWER_SAVING_MODE => 0,
C_USE_FIFO16_FLAGS => 0,
C_USE_FWFT_DATA_COUNT => 0,
C_VALID_LOW => 0,
C_WR_ACK_LOW => 0,
C_WR_DATA_COUNT_WIDTH => 10,
C_WR_DEPTH => 1024,
C_WR_FREQ => 1,
C_WR_PNTR_WIDTH => 10,
C_WR_RESPONSE_LATENCY => 1,
C_MSGON_VAL => 1,
C_ENABLE_RST_SYNC => 1,
C_EN_SAFETY_CKT => 0,
C_ERROR_INJECTION_TYPE => 0,
C_SYNCHRONIZER_STAGE => 2,
C_INTERFACE_TYPE => 0,
C_AXI_TYPE => 1,
C_HAS_AXI_WR_CHANNEL => 1,
C_HAS_AXI_RD_CHANNEL => 1,
C_HAS_SLAVE_CE => 0,
C_HAS_MASTER_CE => 0,
C_ADD_NGC_CONSTRAINT => 0,
C_USE_COMMON_OVERFLOW => 0,
C_USE_COMMON_UNDERFLOW => 0,
C_USE_DEFAULT_SETTINGS => 0,
C_AXI_ID_WIDTH => 1,
C_AXI_ADDR_WIDTH => 32,
C_AXI_DATA_WIDTH => 64,
C_AXI_LEN_WIDTH => 8,
C_AXI_LOCK_WIDTH => 1,
C_HAS_AXI_ID => 0,
C_HAS_AXI_AWUSER => 0,
C_HAS_AXI_WUSER => 0,
C_HAS_AXI_BUSER => 0,
C_HAS_AXI_ARUSER => 0,
C_HAS_AXI_RUSER => 0,
C_AXI_ARUSER_WIDTH => 1,
C_AXI_AWUSER_WIDTH => 1,
C_AXI_WUSER_WIDTH => 1,
C_AXI_BUSER_WIDTH => 1,
C_AXI_RUSER_WIDTH => 1,
C_HAS_AXIS_TDATA => 1,
C_HAS_AXIS_TID => 0,
C_HAS_AXIS_TDEST => 0,
C_HAS_AXIS_TUSER => 1,
C_HAS_AXIS_TREADY => 1,
C_HAS_AXIS_TLAST => 0,
C_HAS_AXIS_TSTRB => 0,
C_HAS_AXIS_TKEEP => 0,
C_AXIS_TDATA_WIDTH => 8,
C_AXIS_TID_WIDTH => 1,
C_AXIS_TDEST_WIDTH => 1,
C_AXIS_TUSER_WIDTH => 4,
C_AXIS_TSTRB_WIDTH => 1,
C_AXIS_TKEEP_WIDTH => 1,
C_WACH_TYPE => 0,
C_WDCH_TYPE => 0,
C_WRCH_TYPE => 0,
C_RACH_TYPE => 0,
C_RDCH_TYPE => 0,
C_AXIS_TYPE => 0,
C_IMPLEMENTATION_TYPE_WACH => 1,
C_IMPLEMENTATION_TYPE_WDCH => 1,
C_IMPLEMENTATION_TYPE_WRCH => 1,
C_IMPLEMENTATION_TYPE_RACH => 1,
C_IMPLEMENTATION_TYPE_RDCH => 1,
C_IMPLEMENTATION_TYPE_AXIS => 1,
C_APPLICATION_TYPE_WACH => 0,
C_APPLICATION_TYPE_WDCH => 0,
C_APPLICATION_TYPE_WRCH => 0,
C_APPLICATION_TYPE_RACH => 0,
C_APPLICATION_TYPE_RDCH => 0,
C_APPLICATION_TYPE_AXIS => 0,
C_PRIM_FIFO_TYPE_WACH => "512x36",
C_PRIM_FIFO_TYPE_WDCH => "1kx36",
C_PRIM_FIFO_TYPE_WRCH => "512x36",
C_PRIM_FIFO_TYPE_RACH => "512x36",
C_PRIM_FIFO_TYPE_RDCH => "1kx36",
C_PRIM_FIFO_TYPE_AXIS => "1kx18",
C_USE_ECC_WACH => 0,
C_USE_ECC_WDCH => 0,
C_USE_ECC_WRCH => 0,
C_USE_ECC_RACH => 0,
C_USE_ECC_RDCH => 0,
C_USE_ECC_AXIS => 0,
C_ERROR_INJECTION_TYPE_WACH => 0,
C_ERROR_INJECTION_TYPE_WDCH => 0,
C_ERROR_INJECTION_TYPE_WRCH => 0,
C_ERROR_INJECTION_TYPE_RACH => 0,
C_ERROR_INJECTION_TYPE_RDCH => 0,
C_ERROR_INJECTION_TYPE_AXIS => 0,
C_DIN_WIDTH_WACH => 1,
C_DIN_WIDTH_WDCH => 64,
C_DIN_WIDTH_WRCH => 2,
C_DIN_WIDTH_RACH => 32,
C_DIN_WIDTH_RDCH => 64,
C_DIN_WIDTH_AXIS => 1,
C_WR_DEPTH_WACH => 16,
C_WR_DEPTH_WDCH => 1024,
C_WR_DEPTH_WRCH => 16,
C_WR_DEPTH_RACH => 16,
C_WR_DEPTH_RDCH => 1024,
C_WR_DEPTH_AXIS => 1024,
C_WR_PNTR_WIDTH_WACH => 4,
C_WR_PNTR_WIDTH_WDCH => 10,
C_WR_PNTR_WIDTH_WRCH => 4,
C_WR_PNTR_WIDTH_RACH => 4,
C_WR_PNTR_WIDTH_RDCH => 10,
C_WR_PNTR_WIDTH_AXIS => 10,
C_HAS_DATA_COUNTS_WACH => 0,
C_HAS_DATA_COUNTS_WDCH => 0,
C_HAS_DATA_COUNTS_WRCH => 0,
C_HAS_DATA_COUNTS_RACH => 0,
C_HAS_DATA_COUNTS_RDCH => 0,
C_HAS_DATA_COUNTS_AXIS => 0,
C_HAS_PROG_FLAGS_WACH => 0,
C_HAS_PROG_FLAGS_WDCH => 0,
C_HAS_PROG_FLAGS_WRCH => 0,
C_HAS_PROG_FLAGS_RACH => 0,
C_HAS_PROG_FLAGS_RDCH => 0,
C_HAS_PROG_FLAGS_AXIS => 0,
C_PROG_FULL_TYPE_WACH => 0,
C_PROG_FULL_TYPE_WDCH => 0,
C_PROG_FULL_TYPE_WRCH => 0,
C_PROG_FULL_TYPE_RACH => 0,
C_PROG_FULL_TYPE_RDCH => 0,
C_PROG_FULL_TYPE_AXIS => 0,
C_PROG_FULL_THRESH_ASSERT_VAL_WACH => 1023,
C_PROG_FULL_THRESH_ASSERT_VAL_WDCH => 1023,
C_PROG_FULL_THRESH_ASSERT_VAL_WRCH => 1023,
C_PROG_FULL_THRESH_ASSERT_VAL_RACH => 1023,
C_PROG_FULL_THRESH_ASSERT_VAL_RDCH => 1023,
C_PROG_FULL_THRESH_ASSERT_VAL_AXIS => 1023,
C_PROG_EMPTY_TYPE_WACH => 0,
C_PROG_EMPTY_TYPE_WDCH => 0,
C_PROG_EMPTY_TYPE_WRCH => 0,
C_PROG_EMPTY_TYPE_RACH => 0,
C_PROG_EMPTY_TYPE_RDCH => 0,
C_PROG_EMPTY_TYPE_AXIS => 0,
C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH => 1022,
C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH => 1022,
C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH => 1022,
C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH => 1022,
C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH => 1022,
C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS => 1022,
C_REG_SLICE_MODE_WACH => 0,
C_REG_SLICE_MODE_WDCH => 0,
C_REG_SLICE_MODE_WRCH => 0,
C_REG_SLICE_MODE_RACH => 0,
C_REG_SLICE_MODE_RDCH => 0,
C_REG_SLICE_MODE_AXIS => 0
)
PORT MAP (
backup => '0',
backup_marker => '0',
clk => clk,
rst => '0',
srst => srst,
wr_clk => '0',
wr_rst => '0',
rd_clk => '0',
rd_rst => '0',
din => din,
wr_en => wr_en,
rd_en => rd_en,
prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
prog_empty_thresh_assert => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
prog_empty_thresh_negate => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
prog_full_thresh_assert => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
prog_full_thresh_negate => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
int_clk => '0',
injectdbiterr => '0',
injectsbiterr => '0',
sleep => '0',
dout => dout,
full => full,
empty => empty,
m_aclk => '0',
s_aclk => '0',
s_aresetn => '0',
m_aclk_en => '0',
s_aclk_en => '0',
s_axi_awid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_awaddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_awlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_awsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_awburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_awlock => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_awcache => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_awprot => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_awqos => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_awregion => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_awuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_awvalid => '0',
s_axi_wid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_wdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 64)),
s_axi_wstrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_wlast => '0',
s_axi_wuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_wvalid => '0',
s_axi_bready => '0',
m_axi_awready => '0',
m_axi_wready => '0',
m_axi_bid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
m_axi_bresp => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
m_axi_buser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
m_axi_bvalid => '0',
s_axi_arid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_araddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_arlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_arsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_arburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_arlock => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_arcache => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_arprot => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_arqos => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_arregion => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_aruser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_arvalid => '0',
s_axi_rready => '0',
m_axi_arready => '0',
m_axi_rid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
m_axi_rdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 64)),
m_axi_rresp => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
m_axi_rlast => '0',
m_axi_ruser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
m_axi_rvalid => '0',
s_axis_tvalid => '0',
s_axis_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axis_tstrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_tkeep => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_tlast => '0',
s_axis_tid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_tdest => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
m_axis_tready => '0',
axi_aw_injectsbiterr => '0',
axi_aw_injectdbiterr => '0',
axi_aw_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_aw_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_w_injectsbiterr => '0',
axi_w_injectdbiterr => '0',
axi_w_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
axi_w_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
axi_b_injectsbiterr => '0',
axi_b_injectdbiterr => '0',
axi_b_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_b_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_ar_injectsbiterr => '0',
axi_ar_injectdbiterr => '0',
axi_ar_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_ar_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_r_injectsbiterr => '0',
axi_r_injectdbiterr => '0',
axi_r_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
axi_r_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
axis_injectsbiterr => '0',
axis_injectdbiterr => '0',
axis_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
axis_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10))
);
END output_fifo_arch;
| unlicense | db38d68fb7970b779c3271244d006e53 | 0.627231 | 2.911849 | false | false | false | false |
grwlf/vsim | vhdl_ct/pro000014.vhd | 1 | 3,943 | -- Prosoft VHDL tests.
--
-- Copyright (C) 2011 Prosoft.
--
-- Author: Zefirov, Karavaev.
--
-- This is a set of simplest tests for isolated tests of VHDL features.
--
-- Nothing more than standard package should be required.
--
-- Categories: entity, architecture, process, after, if-then-else, enumerations, array, record, case, for-loop, signals-attributes.
use work.std_logic_1164_for_tst.all;
entity ENT00011_Test_Bench is
end ENT00011_Test_Bench;
architecture ARCH00011_Test_Bench of ENT00011_Test_Bench is
type std_array_array is array (0 to 3, 1 to 4) of std_ulogic;
signal I_saa : std_array_array := (others => x"B");
subtype byte is bit_vector(7 downto 0);
subtype byte2 is bit_vector(0 to 7);
signal b1 : byte := x"00";
signal b2 : byte2 := x"00";
type bit_array_array is array (0 to 3, 4 downto 1) of bit;
signal I_baa : bit_array_array := (others => x"A");
type NatArray is array (natural range <>) of natural;
type std_array is array (0 to 7) of std_logic;
signal I_sa : std_array := "10101010";
type enum is (a_v, b_v, c_v, d_v, e_v, f_v);
type enum_array is array (integer range <>) of enum;
type rec is record
f1 : integer;
f2 : boolean;
f3 : bit;
f4 : enum;
f5 : enum_array(0 to 3);
f6 : NatArray(7 downto 0);
f7 : bit_vector(7 downto 0);
end record;
type rec_array is array (integer range <>) of rec;
signal e : enum := a_v;
signal ea : enum_array(0 to 3) := (others => a_v);
signal r : rec := (
f1 => 10
, f2 => true
, f3 => '1'
, f4 => a_v
, f5 => (others => a_v)
, f6 => (0 => 10, 7 => 3, others => 0)
, f7 => x"33"
);
signal ra : rec_array(0 to 3) := (others => (
f1 => 10
, f2 => true
, f3 => '1'
, f4 => a_v
, f5 => (others => a_v)
, f6 => (0 => 10, 7 => 3, others => 0)
, f7 => x"33"
)
);
signal bv : bit_vector(15 downto 0) := x"CCCC";
signal clk : std_ulogic := '0';
signal clk2 : std_ulogic := '0';
type BoolVector is array (integer range <>) of boolean;
signal bool : BoolVector(1 to 60);
begin
bool(37) <= bv'Active;
bool(38) <= ra'Active;
bool(39) <= r'Active;
bool(40) <= ea'Active;
bool(41) <= e'Active;
bool(42) <= I_sa'Active;
bool(43) <= I_baa'Active;
bool(44) <= I_saa'Active;
bool(45) <= b1'Active;
bool(46) <= b2'Active;
bool(47) <= clk'Active;
bool(48) <= clk2'Active;
clk <= not clk after 1 us;
clk2 <= not clk2 after 3 us;
process (clk)
begin
if clk'event and clk = '1' then
b1 <= b1(6 downto 0) & not b1(7);
case e is
when a_v => e <= b_v;
when b_v => e <= c_v;
when c_v => e <= d_v;
when d_v => e <= e_v;
when e_v => e <= f_v;
when f_v => e <= a_v;
end case;
ea(0) <= e;
ea_loop: for i in 1 to ea'length-1 loop
ea(i) <= ea(i-1);
end loop ea_loop;
elsif falling_edge(clk) then
bv <= bv(bv'left-1 downto bv'low) & bv(bv'high);
r.f1 <= r.f1 + 1;
r.f2 <= not r.f2;
r.f3 <= not r.f3;
r.f4 <= e;
r.f5 <= ea;
r_f6_loop: for i in r.f6'low to r.f6'high loop
r.f6(i) <= r.f6(i) + 1;
end loop r_f6_loop;
r.f7 <= r.f7(6 downto 0) & r.f7(7);
ra(ra'high) <= r;
ra_loop: for i in ra'high-1 downto 0 loop
ra(i) <= ra(i+1);
end loop;
end if;
end process;
process (clk2)
begin
if rising_edge(clk2) then
I_sa <= I_sa(I_sa'length-1) & I_sa(0 to I_sa'length-2);
elsif clk2'event and clk2 = '0' then
I_saa_loop_1: for i in 0 to 3 loop
I_saa_loop_2: for j in 1 to 4 loop
I_saa(i,j) <= I_sa(i+j);
end loop I_saa_loop_2;
end loop I_saa_loop_1;
I_baa_loop_1: for i in 0 to 3 loop
I_baa_loop_2: for j in 1 to 4 loop
I_baa(i,j) <= bv(i*j);
end loop I_baa_loop_2;
end loop I_baa_loop_1;
end if;
end process;
end ARCH00011_Test_Bench ; | gpl-3.0 | c5bcf7737d86ef2a6ebc23d5bc555b83 | 0.544763 | 2.473651 | false | false | false | false |
ntb-ch/pathos | FPGA/EIMBusToggle/src/pintoggler.vhd | 1 | 2,049 | library ieee;
use ieee.std_logic_1164.all;
entity pintoggler is
port (
clk_50 : in std_logic;
data : out std_logic_vector(15 downto 0);
addr : out std_logic_vector(15 downto 0);
div : out std_logic_vector(15 downto 0)
);
end entity;
architecture rtl of pintoggler is
signal counter : integer := 0;
signal toggler : std_logic_vector(15 downto 0) := (others => '0');
constant clk_ticks : integer := 5000000;
begin
data <= toggler;
addr <= toggler;
count: process (clk_50)
begin
if (rising_edge(clk_50)) then
if ((counter mod clk_ticks) = 0) then toggler(0) <= not toggler(0); end if;
if ((counter mod (clk_ticks/2)) = 0) then toggler(1) <= not toggler(1); end if;
if ((counter mod (clk_ticks/4)) = 0) then toggler(2) <= not toggler(2); end if;
if ((counter mod (clk_ticks/8)) = 0) then toggler(3) <= not toggler(3); end if;
if ((counter mod (clk_ticks/16)) = 0) then toggler(4) <= not toggler(4); end if;
if ((counter mod (clk_ticks/32)) = 0) then toggler(5) <= not toggler(5); end if;
if ((counter mod (clk_ticks/64)) = 0) then toggler(6) <= not toggler(6); end if;
if ((counter mod (clk_ticks/128)) = 0) then toggler(7) <= not toggler(7); end if;
if ((counter mod (clk_ticks/256)) = 0) then toggler(8) <= not toggler(8); end if;
if ((counter mod (clk_ticks/512)) = 0) then toggler(9) <= not toggler(9); end if;
if ((counter mod (clk_ticks/256)) = 0) then toggler(10) <= not toggler(10); end if;
if ((counter mod (clk_ticks/128)) = 0) then toggler(11) <= not toggler(11); end if;
if ((counter mod (clk_ticks/64)) = 0) then toggler(12) <= not toggler(12); end if;
if ((counter mod (clk_ticks/32)) = 0) then toggler(13) <= not toggler(13); end if;
if ((counter mod (clk_ticks/16)) = 0) then toggler(14) <= not toggler(14); end if;
if ((counter mod (clk_ticks/8)) = 0) then toggler(15) <= not toggler(15); end if;
if (counter > clk_ticks) then
counter <= 0;
else
counter <= (counter + 1);
end if;
end if;
end process;
end architecture;
| apache-2.0 | 935672e3d9f42e0c830c185d2d3e0e2d | 0.620303 | 2.643871 | false | false | false | false |
grwlf/vsim | vhdl_ct/ct00035.vhd | 1 | 77,244 | -- NEED RESULT: ARCH00035.P1: Target of a variable assignment may be a aggregate of slices passed
-- NEED RESULT: ARCH00035.P2: Target of a variable assignment may be a aggregate of slices passed
-- NEED RESULT: ARCH00035.P3: Target of a variable assignment may be a aggregate of slices passed
-- NEED RESULT: ARCH00035.P4: Target of a variable assignment may be a aggregate of slices passed
-------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
-------------------------------------------------------------------------------
--
-- TEST NAME:
--
-- CT00035
--
-- AUTHOR:
--
-- G. Tominovich
--
-- TEST OBJECTIVES:
--
-- 8.4 (1)
-- 8.4 (3)
--
-- DESIGN UNIT ORDERING:
--
-- E00000(ARCH00035)
-- ENT00035_Test_Bench(ARCH00035_Test_Bench)
--
-- REVISION HISTORY:
--
-- 29-JUN-1987 - initial revision
--
-- NOTES:
--
-- self-checking
-- automatically generated
--
use WORK.STANDARD_TYPES.all ;
architecture ARCH00035 of E00000 is
signal Dummy : Boolean := false ;
--
begin
P1 :
process ( Dummy )
type arr_st_boolean_vector is
array (integer range -1 downto - 3 ) of
st_boolean_vector ;
type arr_st_bit_vector is
array (integer range -1 downto - 3 ) of
st_bit_vector ;
type arr_st_severity_level_vector is
array (integer range -1 downto - 3 ) of
st_severity_level_vector ;
type arr_st_string is
array (integer range -1 downto - 3 ) of
st_string ;
type arr_st_enum1_vector is
array (integer range -1 downto - 3 ) of
st_enum1_vector ;
type arr_st_integer_vector is
array (integer range -1 downto - 3 ) of
st_integer_vector ;
type arr_st_int1_vector is
array (integer range -1 downto - 3 ) of
st_int1_vector ;
type arr_st_time_vector is
array (integer range -1 downto - 3 ) of
st_time_vector ;
type arr_st_phys1_vector is
array (integer range -1 downto - 3 ) of
st_phys1_vector ;
type arr_st_real_vector is
array (integer range -1 downto - 3 ) of
st_real_vector ;
type arr_st_real1_vector is
array (integer range -1 downto - 3 ) of
st_real1_vector ;
type arr_st_rec1_vector is
array (integer range -1 downto - 3 ) of
st_rec1_vector ;
type arr_st_rec2_vector is
array (integer range -1 downto - 3 ) of
st_rec2_vector ;
type arr_st_rec3_vector is
array (integer range -1 downto - 3 ) of
st_rec3_vector ;
type arr_st_arr1_vector is
array (integer range -1 downto - 3 ) of
st_arr1_vector ;
type arr_st_arr2_vector is
array (integer range -1 downto - 3 ) of
st_arr2_vector ;
type arr_st_arr3_vector is
array (integer range -1 downto - 3 ) of
st_arr3_vector ;
--
variable v_st_boolean_vector_1 : st_boolean_vector :=
c_st_boolean_vector_1 ;
variable v_st_bit_vector_1 : st_bit_vector :=
c_st_bit_vector_1 ;
variable v_st_severity_level_vector_1 : st_severity_level_vector :=
c_st_severity_level_vector_1 ;
variable v_st_string_1 : st_string :=
c_st_string_1 ;
variable v_st_enum1_vector_1 : st_enum1_vector :=
c_st_enum1_vector_1 ;
variable v_st_integer_vector_1 : st_integer_vector :=
c_st_integer_vector_1 ;
variable v_st_int1_vector_1 : st_int1_vector :=
c_st_int1_vector_1 ;
variable v_st_time_vector_1 : st_time_vector :=
c_st_time_vector_1 ;
variable v_st_phys1_vector_1 : st_phys1_vector :=
c_st_phys1_vector_1 ;
variable v_st_real_vector_1 : st_real_vector :=
c_st_real_vector_1 ;
variable v_st_real1_vector_1 : st_real1_vector :=
c_st_real1_vector_1 ;
variable v_st_rec1_vector_1 : st_rec1_vector :=
c_st_rec1_vector_1 ;
variable v_st_rec2_vector_1 : st_rec2_vector :=
c_st_rec2_vector_1 ;
variable v_st_rec3_vector_1 : st_rec3_vector :=
c_st_rec3_vector_1 ;
variable v_st_arr1_vector_1 : st_arr1_vector :=
c_st_arr1_vector_1 ;
variable v_st_arr2_vector_1 : st_arr2_vector :=
c_st_arr2_vector_1 ;
variable v_st_arr3_vector_1 : st_arr3_vector :=
c_st_arr3_vector_1 ;
--
variable v_st_boolean_vector_2 : st_boolean_vector :=
c_st_boolean_vector_1 ;
variable v_st_bit_vector_2 : st_bit_vector :=
c_st_bit_vector_1 ;
variable v_st_severity_level_vector_2 : st_severity_level_vector :=
c_st_severity_level_vector_1 ;
variable v_st_string_2 : st_string :=
c_st_string_1 ;
variable v_st_enum1_vector_2 : st_enum1_vector :=
c_st_enum1_vector_1 ;
variable v_st_integer_vector_2 : st_integer_vector :=
c_st_integer_vector_1 ;
variable v_st_int1_vector_2 : st_int1_vector :=
c_st_int1_vector_1 ;
variable v_st_time_vector_2 : st_time_vector :=
c_st_time_vector_1 ;
variable v_st_phys1_vector_2 : st_phys1_vector :=
c_st_phys1_vector_1 ;
variable v_st_real_vector_2 : st_real_vector :=
c_st_real_vector_1 ;
variable v_st_real1_vector_2 : st_real1_vector :=
c_st_real1_vector_1 ;
variable v_st_rec1_vector_2 : st_rec1_vector :=
c_st_rec1_vector_1 ;
variable v_st_rec2_vector_2 : st_rec2_vector :=
c_st_rec2_vector_1 ;
variable v_st_rec3_vector_2 : st_rec3_vector :=
c_st_rec3_vector_1 ;
variable v_st_arr1_vector_2 : st_arr1_vector :=
c_st_arr1_vector_1 ;
variable v_st_arr2_vector_2 : st_arr2_vector :=
c_st_arr2_vector_1 ;
variable v_st_arr3_vector_2 : st_arr3_vector :=
c_st_arr3_vector_1 ;
--
variable v_st_boolean_vector_3 : st_boolean_vector :=
c_st_boolean_vector_1 ;
variable v_st_bit_vector_3 : st_bit_vector :=
c_st_bit_vector_1 ;
variable v_st_severity_level_vector_3 : st_severity_level_vector :=
c_st_severity_level_vector_1 ;
variable v_st_string_3 : st_string :=
c_st_string_1 ;
variable v_st_enum1_vector_3 : st_enum1_vector :=
c_st_enum1_vector_1 ;
variable v_st_integer_vector_3 : st_integer_vector :=
c_st_integer_vector_1 ;
variable v_st_int1_vector_3 : st_int1_vector :=
c_st_int1_vector_1 ;
variable v_st_time_vector_3 : st_time_vector :=
c_st_time_vector_1 ;
variable v_st_phys1_vector_3 : st_phys1_vector :=
c_st_phys1_vector_1 ;
variable v_st_real_vector_3 : st_real_vector :=
c_st_real_vector_1 ;
variable v_st_real1_vector_3 : st_real1_vector :=
c_st_real1_vector_1 ;
variable v_st_rec1_vector_3 : st_rec1_vector :=
c_st_rec1_vector_1 ;
variable v_st_rec2_vector_3 : st_rec2_vector :=
c_st_rec2_vector_1 ;
variable v_st_rec3_vector_3 : st_rec3_vector :=
c_st_rec3_vector_1 ;
variable v_st_arr1_vector_3 : st_arr1_vector :=
c_st_arr1_vector_1 ;
variable v_st_arr2_vector_3 : st_arr2_vector :=
c_st_arr2_vector_1 ;
variable v_st_arr3_vector_3 : st_arr3_vector :=
c_st_arr3_vector_1 ;
--
variable correct : boolean := true ;
begin
(
v_st_boolean_vector_1(lowb to highb)
, v_st_boolean_vector_2(lowb to highb)
, v_st_boolean_vector_3(lowb to highb)
) :=
arr_st_boolean_vector ' (
(others => c_st_boolean_vector_2(lowb to highb))) ;
--
(
v_st_bit_vector_1(lowb to highb)
, v_st_bit_vector_2(lowb to highb)
, v_st_bit_vector_3(lowb to highb)
) :=
arr_st_bit_vector ' (
(others => c_st_bit_vector_2(lowb to highb))) ;
--
(
v_st_severity_level_vector_1(lowb to highb)
, v_st_severity_level_vector_2(lowb to highb)
, v_st_severity_level_vector_3(lowb to highb)
) :=
arr_st_severity_level_vector ' (
(others => c_st_severity_level_vector_2(lowb to highb))) ;
--
(
v_st_string_1(lowb to highb)
, v_st_string_2(lowb to highb)
, v_st_string_3(lowb to highb)
) :=
arr_st_string ' (
(others => c_st_string_2(lowb to highb))) ;
--
(
v_st_enum1_vector_1(lowb to highb)
, v_st_enum1_vector_2(lowb to highb)
, v_st_enum1_vector_3(lowb to highb)
) :=
arr_st_enum1_vector ' (
(others => c_st_enum1_vector_2(lowb to highb))) ;
--
(
v_st_integer_vector_1(lowb to highb)
, v_st_integer_vector_2(lowb to highb)
, v_st_integer_vector_3(lowb to highb)
) :=
arr_st_integer_vector ' (
(others => c_st_integer_vector_2(lowb to highb))) ;
--
(
v_st_int1_vector_1(lowb to highb)
, v_st_int1_vector_2(lowb to highb)
, v_st_int1_vector_3(lowb to highb)
) :=
arr_st_int1_vector ' (
(others => c_st_int1_vector_2(lowb to highb))) ;
--
(
v_st_time_vector_1(lowb to highb)
, v_st_time_vector_2(lowb to highb)
, v_st_time_vector_3(lowb to highb)
) :=
arr_st_time_vector ' (
(others => c_st_time_vector_2(lowb to highb))) ;
--
(
v_st_phys1_vector_1(lowb to highb)
, v_st_phys1_vector_2(lowb to highb)
, v_st_phys1_vector_3(lowb to highb)
) :=
arr_st_phys1_vector ' (
(others => c_st_phys1_vector_2(lowb to highb))) ;
--
(
v_st_real_vector_1(lowb to highb)
, v_st_real_vector_2(lowb to highb)
, v_st_real_vector_3(lowb to highb)
) :=
arr_st_real_vector ' (
(others => c_st_real_vector_2(lowb to highb))) ;
--
(
v_st_real1_vector_1(lowb to highb)
, v_st_real1_vector_2(lowb to highb)
, v_st_real1_vector_3(lowb to highb)
) :=
arr_st_real1_vector ' (
(others => c_st_real1_vector_2(lowb to highb))) ;
--
(
v_st_rec1_vector_1(lowb to highb)
, v_st_rec1_vector_2(lowb to highb)
, v_st_rec1_vector_3(lowb to highb)
) :=
arr_st_rec1_vector ' (
(others => c_st_rec1_vector_2(lowb to highb))) ;
--
(
v_st_rec2_vector_1(lowb to highb)
, v_st_rec2_vector_2(lowb to highb)
, v_st_rec2_vector_3(lowb to highb)
) :=
arr_st_rec2_vector ' (
(others => c_st_rec2_vector_2(lowb to highb))) ;
--
(
v_st_rec3_vector_1(lowb to highb)
, v_st_rec3_vector_2(lowb to highb)
, v_st_rec3_vector_3(lowb to highb)
) :=
arr_st_rec3_vector ' (
(others => c_st_rec3_vector_2(lowb to highb))) ;
--
(
v_st_arr1_vector_1(lowb to highb)
, v_st_arr1_vector_2(lowb to highb)
, v_st_arr1_vector_3(lowb to highb)
) :=
arr_st_arr1_vector ' (
(others => c_st_arr1_vector_2(lowb to highb))) ;
--
(
v_st_arr2_vector_1(lowb to highb)
, v_st_arr2_vector_2(lowb to highb)
, v_st_arr2_vector_3(lowb to highb)
) :=
arr_st_arr2_vector ' (
(others => c_st_arr2_vector_2(lowb to highb))) ;
--
(
v_st_arr3_vector_1(lowb to highb)
, v_st_arr3_vector_2(lowb to highb)
, v_st_arr3_vector_3(lowb to highb)
) :=
arr_st_arr3_vector ' (
(others => c_st_arr3_vector_2(lowb to highb))) ;
--
--
correct := correct and
v_st_boolean_vector_1(lowb to highb) =
c_st_boolean_vector_2(lowb to highb) ;
correct := correct and
v_st_bit_vector_1(lowb to highb) =
c_st_bit_vector_2(lowb to highb) ;
correct := correct and
v_st_severity_level_vector_1(lowb to highb) =
c_st_severity_level_vector_2(lowb to highb) ;
correct := correct and
v_st_string_1(lowb to highb) =
c_st_string_2(lowb to highb) ;
correct := correct and
v_st_enum1_vector_1(lowb to highb) =
c_st_enum1_vector_2(lowb to highb) ;
correct := correct and
v_st_integer_vector_1(lowb to highb) =
c_st_integer_vector_2(lowb to highb) ;
correct := correct and
v_st_int1_vector_1(lowb to highb) =
c_st_int1_vector_2(lowb to highb) ;
correct := correct and
v_st_time_vector_1(lowb to highb) =
c_st_time_vector_2(lowb to highb) ;
correct := correct and
v_st_phys1_vector_1(lowb to highb) =
c_st_phys1_vector_2(lowb to highb) ;
correct := correct and
v_st_real_vector_1(lowb to highb) =
c_st_real_vector_2(lowb to highb) ;
correct := correct and
v_st_real1_vector_1(lowb to highb) =
c_st_real1_vector_2(lowb to highb) ;
correct := correct and
v_st_rec1_vector_1(lowb to highb) =
c_st_rec1_vector_2(lowb to highb) ;
correct := correct and
v_st_rec2_vector_1(lowb to highb) =
c_st_rec2_vector_2(lowb to highb) ;
correct := correct and
v_st_rec3_vector_1(lowb to highb) =
c_st_rec3_vector_2(lowb to highb) ;
correct := correct and
v_st_arr1_vector_1(lowb to highb) =
c_st_arr1_vector_2(lowb to highb) ;
correct := correct and
v_st_arr2_vector_1(lowb to highb) =
c_st_arr2_vector_2(lowb to highb) ;
correct := correct and
v_st_arr3_vector_1(lowb to highb) =
c_st_arr3_vector_2(lowb to highb) ;
--
correct := correct and
v_st_boolean_vector_2(lowb to highb) =
c_st_boolean_vector_2(lowb to highb) ;
correct := correct and
v_st_bit_vector_2(lowb to highb) =
c_st_bit_vector_2(lowb to highb) ;
correct := correct and
v_st_severity_level_vector_2(lowb to highb) =
c_st_severity_level_vector_2(lowb to highb) ;
correct := correct and
v_st_string_2(lowb to highb) =
c_st_string_2(lowb to highb) ;
correct := correct and
v_st_enum1_vector_2(lowb to highb) =
c_st_enum1_vector_2(lowb to highb) ;
correct := correct and
v_st_integer_vector_2(lowb to highb) =
c_st_integer_vector_2(lowb to highb) ;
correct := correct and
v_st_int1_vector_2(lowb to highb) =
c_st_int1_vector_2(lowb to highb) ;
correct := correct and
v_st_time_vector_2(lowb to highb) =
c_st_time_vector_2(lowb to highb) ;
correct := correct and
v_st_phys1_vector_2(lowb to highb) =
c_st_phys1_vector_2(lowb to highb) ;
correct := correct and
v_st_real_vector_2(lowb to highb) =
c_st_real_vector_2(lowb to highb) ;
correct := correct and
v_st_real1_vector_2(lowb to highb) =
c_st_real1_vector_2(lowb to highb) ;
correct := correct and
v_st_rec1_vector_2(lowb to highb) =
c_st_rec1_vector_2(lowb to highb) ;
correct := correct and
v_st_rec2_vector_2(lowb to highb) =
c_st_rec2_vector_2(lowb to highb) ;
correct := correct and
v_st_rec3_vector_2(lowb to highb) =
c_st_rec3_vector_2(lowb to highb) ;
correct := correct and
v_st_arr1_vector_2(lowb to highb) =
c_st_arr1_vector_2(lowb to highb) ;
correct := correct and
v_st_arr2_vector_2(lowb to highb) =
c_st_arr2_vector_2(lowb to highb) ;
correct := correct and
v_st_arr3_vector_2(lowb to highb) =
c_st_arr3_vector_2(lowb to highb) ;
--
correct := correct and
v_st_boolean_vector_3(lowb to highb) =
c_st_boolean_vector_2(lowb to highb) ;
correct := correct and
v_st_bit_vector_3(lowb to highb) =
c_st_bit_vector_2(lowb to highb) ;
correct := correct and
v_st_severity_level_vector_3(lowb to highb) =
c_st_severity_level_vector_2(lowb to highb) ;
correct := correct and
v_st_string_3(lowb to highb) =
c_st_string_2(lowb to highb) ;
correct := correct and
v_st_enum1_vector_3(lowb to highb) =
c_st_enum1_vector_2(lowb to highb) ;
correct := correct and
v_st_integer_vector_3(lowb to highb) =
c_st_integer_vector_2(lowb to highb) ;
correct := correct and
v_st_int1_vector_3(lowb to highb) =
c_st_int1_vector_2(lowb to highb) ;
correct := correct and
v_st_time_vector_3(lowb to highb) =
c_st_time_vector_2(lowb to highb) ;
correct := correct and
v_st_phys1_vector_3(lowb to highb) =
c_st_phys1_vector_2(lowb to highb) ;
correct := correct and
v_st_real_vector_3(lowb to highb) =
c_st_real_vector_2(lowb to highb) ;
correct := correct and
v_st_real1_vector_3(lowb to highb) =
c_st_real1_vector_2(lowb to highb) ;
correct := correct and
v_st_rec1_vector_3(lowb to highb) =
c_st_rec1_vector_2(lowb to highb) ;
correct := correct and
v_st_rec2_vector_3(lowb to highb) =
c_st_rec2_vector_2(lowb to highb) ;
correct := correct and
v_st_rec3_vector_3(lowb to highb) =
c_st_rec3_vector_2(lowb to highb) ;
correct := correct and
v_st_arr1_vector_3(lowb to highb) =
c_st_arr1_vector_2(lowb to highb) ;
correct := correct and
v_st_arr2_vector_3(lowb to highb) =
c_st_arr2_vector_2(lowb to highb) ;
correct := correct and
v_st_arr3_vector_3(lowb to highb) =
c_st_arr3_vector_2(lowb to highb) ;
--
test_report ( "ARCH00035.P1" ,
"Target of a variable assignment may be a " &
"aggregate of slices" ,
correct) ;
end process P1 ;
--
P2 :
process ( Dummy )
variable correct : boolean := true ;
--
procedure Proc1 is
type arr_st_boolean_vector is
array (integer range -1 downto - 3 ) of
st_boolean_vector ;
type arr_st_bit_vector is
array (integer range -1 downto - 3 ) of
st_bit_vector ;
type arr_st_severity_level_vector is
array (integer range -1 downto - 3 ) of
st_severity_level_vector ;
type arr_st_string is
array (integer range -1 downto - 3 ) of
st_string ;
type arr_st_enum1_vector is
array (integer range -1 downto - 3 ) of
st_enum1_vector ;
type arr_st_integer_vector is
array (integer range -1 downto - 3 ) of
st_integer_vector ;
type arr_st_int1_vector is
array (integer range -1 downto - 3 ) of
st_int1_vector ;
type arr_st_time_vector is
array (integer range -1 downto - 3 ) of
st_time_vector ;
type arr_st_phys1_vector is
array (integer range -1 downto - 3 ) of
st_phys1_vector ;
type arr_st_real_vector is
array (integer range -1 downto - 3 ) of
st_real_vector ;
type arr_st_real1_vector is
array (integer range -1 downto - 3 ) of
st_real1_vector ;
type arr_st_rec1_vector is
array (integer range -1 downto - 3 ) of
st_rec1_vector ;
type arr_st_rec2_vector is
array (integer range -1 downto - 3 ) of
st_rec2_vector ;
type arr_st_rec3_vector is
array (integer range -1 downto - 3 ) of
st_rec3_vector ;
type arr_st_arr1_vector is
array (integer range -1 downto - 3 ) of
st_arr1_vector ;
type arr_st_arr2_vector is
array (integer range -1 downto - 3 ) of
st_arr2_vector ;
type arr_st_arr3_vector is
array (integer range -1 downto - 3 ) of
st_arr3_vector ;
--
variable v_st_boolean_vector_1 : st_boolean_vector :=
c_st_boolean_vector_1 ;
variable v_st_bit_vector_1 : st_bit_vector :=
c_st_bit_vector_1 ;
variable v_st_severity_level_vector_1 : st_severity_level_vector :=
c_st_severity_level_vector_1 ;
variable v_st_string_1 : st_string :=
c_st_string_1 ;
variable v_st_enum1_vector_1 : st_enum1_vector :=
c_st_enum1_vector_1 ;
variable v_st_integer_vector_1 : st_integer_vector :=
c_st_integer_vector_1 ;
variable v_st_int1_vector_1 : st_int1_vector :=
c_st_int1_vector_1 ;
variable v_st_time_vector_1 : st_time_vector :=
c_st_time_vector_1 ;
variable v_st_phys1_vector_1 : st_phys1_vector :=
c_st_phys1_vector_1 ;
variable v_st_real_vector_1 : st_real_vector :=
c_st_real_vector_1 ;
variable v_st_real1_vector_1 : st_real1_vector :=
c_st_real1_vector_1 ;
variable v_st_rec1_vector_1 : st_rec1_vector :=
c_st_rec1_vector_1 ;
variable v_st_rec2_vector_1 : st_rec2_vector :=
c_st_rec2_vector_1 ;
variable v_st_rec3_vector_1 : st_rec3_vector :=
c_st_rec3_vector_1 ;
variable v_st_arr1_vector_1 : st_arr1_vector :=
c_st_arr1_vector_1 ;
variable v_st_arr2_vector_1 : st_arr2_vector :=
c_st_arr2_vector_1 ;
variable v_st_arr3_vector_1 : st_arr3_vector :=
c_st_arr3_vector_1 ;
--
variable v_st_boolean_vector_2 : st_boolean_vector :=
c_st_boolean_vector_1 ;
variable v_st_bit_vector_2 : st_bit_vector :=
c_st_bit_vector_1 ;
variable v_st_severity_level_vector_2 : st_severity_level_vector :=
c_st_severity_level_vector_1 ;
variable v_st_string_2 : st_string :=
c_st_string_1 ;
variable v_st_enum1_vector_2 : st_enum1_vector :=
c_st_enum1_vector_1 ;
variable v_st_integer_vector_2 : st_integer_vector :=
c_st_integer_vector_1 ;
variable v_st_int1_vector_2 : st_int1_vector :=
c_st_int1_vector_1 ;
variable v_st_time_vector_2 : st_time_vector :=
c_st_time_vector_1 ;
variable v_st_phys1_vector_2 : st_phys1_vector :=
c_st_phys1_vector_1 ;
variable v_st_real_vector_2 : st_real_vector :=
c_st_real_vector_1 ;
variable v_st_real1_vector_2 : st_real1_vector :=
c_st_real1_vector_1 ;
variable v_st_rec1_vector_2 : st_rec1_vector :=
c_st_rec1_vector_1 ;
variable v_st_rec2_vector_2 : st_rec2_vector :=
c_st_rec2_vector_1 ;
variable v_st_rec3_vector_2 : st_rec3_vector :=
c_st_rec3_vector_1 ;
variable v_st_arr1_vector_2 : st_arr1_vector :=
c_st_arr1_vector_1 ;
variable v_st_arr2_vector_2 : st_arr2_vector :=
c_st_arr2_vector_1 ;
variable v_st_arr3_vector_2 : st_arr3_vector :=
c_st_arr3_vector_1 ;
--
variable v_st_boolean_vector_3 : st_boolean_vector :=
c_st_boolean_vector_1 ;
variable v_st_bit_vector_3 : st_bit_vector :=
c_st_bit_vector_1 ;
variable v_st_severity_level_vector_3 : st_severity_level_vector :=
c_st_severity_level_vector_1 ;
variable v_st_string_3 : st_string :=
c_st_string_1 ;
variable v_st_enum1_vector_3 : st_enum1_vector :=
c_st_enum1_vector_1 ;
variable v_st_integer_vector_3 : st_integer_vector :=
c_st_integer_vector_1 ;
variable v_st_int1_vector_3 : st_int1_vector :=
c_st_int1_vector_1 ;
variable v_st_time_vector_3 : st_time_vector :=
c_st_time_vector_1 ;
variable v_st_phys1_vector_3 : st_phys1_vector :=
c_st_phys1_vector_1 ;
variable v_st_real_vector_3 : st_real_vector :=
c_st_real_vector_1 ;
variable v_st_real1_vector_3 : st_real1_vector :=
c_st_real1_vector_1 ;
variable v_st_rec1_vector_3 : st_rec1_vector :=
c_st_rec1_vector_1 ;
variable v_st_rec2_vector_3 : st_rec2_vector :=
c_st_rec2_vector_1 ;
variable v_st_rec3_vector_3 : st_rec3_vector :=
c_st_rec3_vector_1 ;
variable v_st_arr1_vector_3 : st_arr1_vector :=
c_st_arr1_vector_1 ;
variable v_st_arr2_vector_3 : st_arr2_vector :=
c_st_arr2_vector_1 ;
variable v_st_arr3_vector_3 : st_arr3_vector :=
c_st_arr3_vector_1 ;
--
begin
(
v_st_boolean_vector_1(lowb to highb)
, v_st_boolean_vector_2(lowb to highb)
, v_st_boolean_vector_3(lowb to highb)
) :=
arr_st_boolean_vector ' (
(others => c_st_boolean_vector_2(lowb to highb))) ;
--
(
v_st_bit_vector_1(lowb to highb)
, v_st_bit_vector_2(lowb to highb)
, v_st_bit_vector_3(lowb to highb)
) :=
arr_st_bit_vector ' (
(others => c_st_bit_vector_2(lowb to highb))) ;
--
(
v_st_severity_level_vector_1(lowb to highb)
, v_st_severity_level_vector_2(lowb to highb)
, v_st_severity_level_vector_3(lowb to highb)
) :=
arr_st_severity_level_vector ' (
(others => c_st_severity_level_vector_2(lowb to highb))) ;
--
(
v_st_string_1(lowb to highb)
, v_st_string_2(lowb to highb)
, v_st_string_3(lowb to highb)
) :=
arr_st_string ' (
(others => c_st_string_2(lowb to highb))) ;
--
(
v_st_enum1_vector_1(lowb to highb)
, v_st_enum1_vector_2(lowb to highb)
, v_st_enum1_vector_3(lowb to highb)
) :=
arr_st_enum1_vector ' (
(others => c_st_enum1_vector_2(lowb to highb))) ;
--
(
v_st_integer_vector_1(lowb to highb)
, v_st_integer_vector_2(lowb to highb)
, v_st_integer_vector_3(lowb to highb)
) :=
arr_st_integer_vector ' (
(others => c_st_integer_vector_2(lowb to highb))) ;
--
(
v_st_int1_vector_1(lowb to highb)
, v_st_int1_vector_2(lowb to highb)
, v_st_int1_vector_3(lowb to highb)
) :=
arr_st_int1_vector ' (
(others => c_st_int1_vector_2(lowb to highb))) ;
--
(
v_st_time_vector_1(lowb to highb)
, v_st_time_vector_2(lowb to highb)
, v_st_time_vector_3(lowb to highb)
) :=
arr_st_time_vector ' (
(others => c_st_time_vector_2(lowb to highb))) ;
--
(
v_st_phys1_vector_1(lowb to highb)
, v_st_phys1_vector_2(lowb to highb)
, v_st_phys1_vector_3(lowb to highb)
) :=
arr_st_phys1_vector ' (
(others => c_st_phys1_vector_2(lowb to highb))) ;
--
(
v_st_real_vector_1(lowb to highb)
, v_st_real_vector_2(lowb to highb)
, v_st_real_vector_3(lowb to highb)
) :=
arr_st_real_vector ' (
(others => c_st_real_vector_2(lowb to highb))) ;
--
(
v_st_real1_vector_1(lowb to highb)
, v_st_real1_vector_2(lowb to highb)
, v_st_real1_vector_3(lowb to highb)
) :=
arr_st_real1_vector ' (
(others => c_st_real1_vector_2(lowb to highb))) ;
--
(
v_st_rec1_vector_1(lowb to highb)
, v_st_rec1_vector_2(lowb to highb)
, v_st_rec1_vector_3(lowb to highb)
) :=
arr_st_rec1_vector ' (
(others => c_st_rec1_vector_2(lowb to highb))) ;
--
(
v_st_rec2_vector_1(lowb to highb)
, v_st_rec2_vector_2(lowb to highb)
, v_st_rec2_vector_3(lowb to highb)
) :=
arr_st_rec2_vector ' (
(others => c_st_rec2_vector_2(lowb to highb))) ;
--
(
v_st_rec3_vector_1(lowb to highb)
, v_st_rec3_vector_2(lowb to highb)
, v_st_rec3_vector_3(lowb to highb)
) :=
arr_st_rec3_vector ' (
(others => c_st_rec3_vector_2(lowb to highb))) ;
--
(
v_st_arr1_vector_1(lowb to highb)
, v_st_arr1_vector_2(lowb to highb)
, v_st_arr1_vector_3(lowb to highb)
) :=
arr_st_arr1_vector ' (
(others => c_st_arr1_vector_2(lowb to highb))) ;
--
(
v_st_arr2_vector_1(lowb to highb)
, v_st_arr2_vector_2(lowb to highb)
, v_st_arr2_vector_3(lowb to highb)
) :=
arr_st_arr2_vector ' (
(others => c_st_arr2_vector_2(lowb to highb))) ;
--
(
v_st_arr3_vector_1(lowb to highb)
, v_st_arr3_vector_2(lowb to highb)
, v_st_arr3_vector_3(lowb to highb)
) :=
arr_st_arr3_vector ' (
(others => c_st_arr3_vector_2(lowb to highb))) ;
--
--
correct := correct and
v_st_boolean_vector_1(lowb to highb) =
c_st_boolean_vector_2(lowb to highb) ;
correct := correct and
v_st_bit_vector_1(lowb to highb) =
c_st_bit_vector_2(lowb to highb) ;
correct := correct and
v_st_severity_level_vector_1(lowb to highb) =
c_st_severity_level_vector_2(lowb to highb) ;
correct := correct and
v_st_string_1(lowb to highb) =
c_st_string_2(lowb to highb) ;
correct := correct and
v_st_enum1_vector_1(lowb to highb) =
c_st_enum1_vector_2(lowb to highb) ;
correct := correct and
v_st_integer_vector_1(lowb to highb) =
c_st_integer_vector_2(lowb to highb) ;
correct := correct and
v_st_int1_vector_1(lowb to highb) =
c_st_int1_vector_2(lowb to highb) ;
correct := correct and
v_st_time_vector_1(lowb to highb) =
c_st_time_vector_2(lowb to highb) ;
correct := correct and
v_st_phys1_vector_1(lowb to highb) =
c_st_phys1_vector_2(lowb to highb) ;
correct := correct and
v_st_real_vector_1(lowb to highb) =
c_st_real_vector_2(lowb to highb) ;
correct := correct and
v_st_real1_vector_1(lowb to highb) =
c_st_real1_vector_2(lowb to highb) ;
correct := correct and
v_st_rec1_vector_1(lowb to highb) =
c_st_rec1_vector_2(lowb to highb) ;
correct := correct and
v_st_rec2_vector_1(lowb to highb) =
c_st_rec2_vector_2(lowb to highb) ;
correct := correct and
v_st_rec3_vector_1(lowb to highb) =
c_st_rec3_vector_2(lowb to highb) ;
correct := correct and
v_st_arr1_vector_1(lowb to highb) =
c_st_arr1_vector_2(lowb to highb) ;
correct := correct and
v_st_arr2_vector_1(lowb to highb) =
c_st_arr2_vector_2(lowb to highb) ;
correct := correct and
v_st_arr3_vector_1(lowb to highb) =
c_st_arr3_vector_2(lowb to highb) ;
--
correct := correct and
v_st_boolean_vector_2(lowb to highb) =
c_st_boolean_vector_2(lowb to highb) ;
correct := correct and
v_st_bit_vector_2(lowb to highb) =
c_st_bit_vector_2(lowb to highb) ;
correct := correct and
v_st_severity_level_vector_2(lowb to highb) =
c_st_severity_level_vector_2(lowb to highb) ;
correct := correct and
v_st_string_2(lowb to highb) =
c_st_string_2(lowb to highb) ;
correct := correct and
v_st_enum1_vector_2(lowb to highb) =
c_st_enum1_vector_2(lowb to highb) ;
correct := correct and
v_st_integer_vector_2(lowb to highb) =
c_st_integer_vector_2(lowb to highb) ;
correct := correct and
v_st_int1_vector_2(lowb to highb) =
c_st_int1_vector_2(lowb to highb) ;
correct := correct and
v_st_time_vector_2(lowb to highb) =
c_st_time_vector_2(lowb to highb) ;
correct := correct and
v_st_phys1_vector_2(lowb to highb) =
c_st_phys1_vector_2(lowb to highb) ;
correct := correct and
v_st_real_vector_2(lowb to highb) =
c_st_real_vector_2(lowb to highb) ;
correct := correct and
v_st_real1_vector_2(lowb to highb) =
c_st_real1_vector_2(lowb to highb) ;
correct := correct and
v_st_rec1_vector_2(lowb to highb) =
c_st_rec1_vector_2(lowb to highb) ;
correct := correct and
v_st_rec2_vector_2(lowb to highb) =
c_st_rec2_vector_2(lowb to highb) ;
correct := correct and
v_st_rec3_vector_2(lowb to highb) =
c_st_rec3_vector_2(lowb to highb) ;
correct := correct and
v_st_arr1_vector_2(lowb to highb) =
c_st_arr1_vector_2(lowb to highb) ;
correct := correct and
v_st_arr2_vector_2(lowb to highb) =
c_st_arr2_vector_2(lowb to highb) ;
correct := correct and
v_st_arr3_vector_2(lowb to highb) =
c_st_arr3_vector_2(lowb to highb) ;
--
correct := correct and
v_st_boolean_vector_3(lowb to highb) =
c_st_boolean_vector_2(lowb to highb) ;
correct := correct and
v_st_bit_vector_3(lowb to highb) =
c_st_bit_vector_2(lowb to highb) ;
correct := correct and
v_st_severity_level_vector_3(lowb to highb) =
c_st_severity_level_vector_2(lowb to highb) ;
correct := correct and
v_st_string_3(lowb to highb) =
c_st_string_2(lowb to highb) ;
correct := correct and
v_st_enum1_vector_3(lowb to highb) =
c_st_enum1_vector_2(lowb to highb) ;
correct := correct and
v_st_integer_vector_3(lowb to highb) =
c_st_integer_vector_2(lowb to highb) ;
correct := correct and
v_st_int1_vector_3(lowb to highb) =
c_st_int1_vector_2(lowb to highb) ;
correct := correct and
v_st_time_vector_3(lowb to highb) =
c_st_time_vector_2(lowb to highb) ;
correct := correct and
v_st_phys1_vector_3(lowb to highb) =
c_st_phys1_vector_2(lowb to highb) ;
correct := correct and
v_st_real_vector_3(lowb to highb) =
c_st_real_vector_2(lowb to highb) ;
correct := correct and
v_st_real1_vector_3(lowb to highb) =
c_st_real1_vector_2(lowb to highb) ;
correct := correct and
v_st_rec1_vector_3(lowb to highb) =
c_st_rec1_vector_2(lowb to highb) ;
correct := correct and
v_st_rec2_vector_3(lowb to highb) =
c_st_rec2_vector_2(lowb to highb) ;
correct := correct and
v_st_rec3_vector_3(lowb to highb) =
c_st_rec3_vector_2(lowb to highb) ;
correct := correct and
v_st_arr1_vector_3(lowb to highb) =
c_st_arr1_vector_2(lowb to highb) ;
correct := correct and
v_st_arr2_vector_3(lowb to highb) =
c_st_arr2_vector_2(lowb to highb) ;
correct := correct and
v_st_arr3_vector_3(lowb to highb) =
c_st_arr3_vector_2(lowb to highb) ;
--
end Proc1 ;
begin
Proc1 ;
test_report ( "ARCH00035.P2" ,
"Target of a variable assignment may be a " &
"aggregate of slices" ,
correct) ;
end process P2 ;
--
P3 :
process ( Dummy )
type arr_st_boolean_vector is
array (integer range -1 downto - 3 ) of
st_boolean_vector ;
type arr_st_bit_vector is
array (integer range -1 downto - 3 ) of
st_bit_vector ;
type arr_st_severity_level_vector is
array (integer range -1 downto - 3 ) of
st_severity_level_vector ;
type arr_st_string is
array (integer range -1 downto - 3 ) of
st_string ;
type arr_st_enum1_vector is
array (integer range -1 downto - 3 ) of
st_enum1_vector ;
type arr_st_integer_vector is
array (integer range -1 downto - 3 ) of
st_integer_vector ;
type arr_st_int1_vector is
array (integer range -1 downto - 3 ) of
st_int1_vector ;
type arr_st_time_vector is
array (integer range -1 downto - 3 ) of
st_time_vector ;
type arr_st_phys1_vector is
array (integer range -1 downto - 3 ) of
st_phys1_vector ;
type arr_st_real_vector is
array (integer range -1 downto - 3 ) of
st_real_vector ;
type arr_st_real1_vector is
array (integer range -1 downto - 3 ) of
st_real1_vector ;
type arr_st_rec1_vector is
array (integer range -1 downto - 3 ) of
st_rec1_vector ;
type arr_st_rec2_vector is
array (integer range -1 downto - 3 ) of
st_rec2_vector ;
type arr_st_rec3_vector is
array (integer range -1 downto - 3 ) of
st_rec3_vector ;
type arr_st_arr1_vector is
array (integer range -1 downto - 3 ) of
st_arr1_vector ;
type arr_st_arr2_vector is
array (integer range -1 downto - 3 ) of
st_arr2_vector ;
type arr_st_arr3_vector is
array (integer range -1 downto - 3 ) of
st_arr3_vector ;
--
variable v_st_boolean_vector_1 : st_boolean_vector :=
c_st_boolean_vector_1 ;
variable v_st_bit_vector_1 : st_bit_vector :=
c_st_bit_vector_1 ;
variable v_st_severity_level_vector_1 : st_severity_level_vector :=
c_st_severity_level_vector_1 ;
variable v_st_string_1 : st_string :=
c_st_string_1 ;
variable v_st_enum1_vector_1 : st_enum1_vector :=
c_st_enum1_vector_1 ;
variable v_st_integer_vector_1 : st_integer_vector :=
c_st_integer_vector_1 ;
variable v_st_int1_vector_1 : st_int1_vector :=
c_st_int1_vector_1 ;
variable v_st_time_vector_1 : st_time_vector :=
c_st_time_vector_1 ;
variable v_st_phys1_vector_1 : st_phys1_vector :=
c_st_phys1_vector_1 ;
variable v_st_real_vector_1 : st_real_vector :=
c_st_real_vector_1 ;
variable v_st_real1_vector_1 : st_real1_vector :=
c_st_real1_vector_1 ;
variable v_st_rec1_vector_1 : st_rec1_vector :=
c_st_rec1_vector_1 ;
variable v_st_rec2_vector_1 : st_rec2_vector :=
c_st_rec2_vector_1 ;
variable v_st_rec3_vector_1 : st_rec3_vector :=
c_st_rec3_vector_1 ;
variable v_st_arr1_vector_1 : st_arr1_vector :=
c_st_arr1_vector_1 ;
variable v_st_arr2_vector_1 : st_arr2_vector :=
c_st_arr2_vector_1 ;
variable v_st_arr3_vector_1 : st_arr3_vector :=
c_st_arr3_vector_1 ;
--
variable v_st_boolean_vector_2 : st_boolean_vector :=
c_st_boolean_vector_1 ;
variable v_st_bit_vector_2 : st_bit_vector :=
c_st_bit_vector_1 ;
variable v_st_severity_level_vector_2 : st_severity_level_vector :=
c_st_severity_level_vector_1 ;
variable v_st_string_2 : st_string :=
c_st_string_1 ;
variable v_st_enum1_vector_2 : st_enum1_vector :=
c_st_enum1_vector_1 ;
variable v_st_integer_vector_2 : st_integer_vector :=
c_st_integer_vector_1 ;
variable v_st_int1_vector_2 : st_int1_vector :=
c_st_int1_vector_1 ;
variable v_st_time_vector_2 : st_time_vector :=
c_st_time_vector_1 ;
variable v_st_phys1_vector_2 : st_phys1_vector :=
c_st_phys1_vector_1 ;
variable v_st_real_vector_2 : st_real_vector :=
c_st_real_vector_1 ;
variable v_st_real1_vector_2 : st_real1_vector :=
c_st_real1_vector_1 ;
variable v_st_rec1_vector_2 : st_rec1_vector :=
c_st_rec1_vector_1 ;
variable v_st_rec2_vector_2 : st_rec2_vector :=
c_st_rec2_vector_1 ;
variable v_st_rec3_vector_2 : st_rec3_vector :=
c_st_rec3_vector_1 ;
variable v_st_arr1_vector_2 : st_arr1_vector :=
c_st_arr1_vector_1 ;
variable v_st_arr2_vector_2 : st_arr2_vector :=
c_st_arr2_vector_1 ;
variable v_st_arr3_vector_2 : st_arr3_vector :=
c_st_arr3_vector_1 ;
--
variable v_st_boolean_vector_3 : st_boolean_vector :=
c_st_boolean_vector_1 ;
variable v_st_bit_vector_3 : st_bit_vector :=
c_st_bit_vector_1 ;
variable v_st_severity_level_vector_3 : st_severity_level_vector :=
c_st_severity_level_vector_1 ;
variable v_st_string_3 : st_string :=
c_st_string_1 ;
variable v_st_enum1_vector_3 : st_enum1_vector :=
c_st_enum1_vector_1 ;
variable v_st_integer_vector_3 : st_integer_vector :=
c_st_integer_vector_1 ;
variable v_st_int1_vector_3 : st_int1_vector :=
c_st_int1_vector_1 ;
variable v_st_time_vector_3 : st_time_vector :=
c_st_time_vector_1 ;
variable v_st_phys1_vector_3 : st_phys1_vector :=
c_st_phys1_vector_1 ;
variable v_st_real_vector_3 : st_real_vector :=
c_st_real_vector_1 ;
variable v_st_real1_vector_3 : st_real1_vector :=
c_st_real1_vector_1 ;
variable v_st_rec1_vector_3 : st_rec1_vector :=
c_st_rec1_vector_1 ;
variable v_st_rec2_vector_3 : st_rec2_vector :=
c_st_rec2_vector_1 ;
variable v_st_rec3_vector_3 : st_rec3_vector :=
c_st_rec3_vector_1 ;
variable v_st_arr1_vector_3 : st_arr1_vector :=
c_st_arr1_vector_1 ;
variable v_st_arr2_vector_3 : st_arr2_vector :=
c_st_arr2_vector_1 ;
variable v_st_arr3_vector_3 : st_arr3_vector :=
c_st_arr3_vector_1 ;
--
variable correct : boolean := true ;
--
procedure Proc1 is
begin
(
v_st_boolean_vector_1(lowb to highb)
, v_st_boolean_vector_2(lowb to highb)
, v_st_boolean_vector_3(lowb to highb)
) :=
arr_st_boolean_vector ' (
(others => c_st_boolean_vector_2(lowb to highb))) ;
--
(
v_st_bit_vector_1(lowb to highb)
, v_st_bit_vector_2(lowb to highb)
, v_st_bit_vector_3(lowb to highb)
) :=
arr_st_bit_vector ' (
(others => c_st_bit_vector_2(lowb to highb))) ;
--
(
v_st_severity_level_vector_1(lowb to highb)
, v_st_severity_level_vector_2(lowb to highb)
, v_st_severity_level_vector_3(lowb to highb)
) :=
arr_st_severity_level_vector ' (
(others => c_st_severity_level_vector_2(lowb to highb))) ;
--
(
v_st_string_1(lowb to highb)
, v_st_string_2(lowb to highb)
, v_st_string_3(lowb to highb)
) :=
arr_st_string ' (
(others => c_st_string_2(lowb to highb))) ;
--
(
v_st_enum1_vector_1(lowb to highb)
, v_st_enum1_vector_2(lowb to highb)
, v_st_enum1_vector_3(lowb to highb)
) :=
arr_st_enum1_vector ' (
(others => c_st_enum1_vector_2(lowb to highb))) ;
--
(
v_st_integer_vector_1(lowb to highb)
, v_st_integer_vector_2(lowb to highb)
, v_st_integer_vector_3(lowb to highb)
) :=
arr_st_integer_vector ' (
(others => c_st_integer_vector_2(lowb to highb))) ;
--
(
v_st_int1_vector_1(lowb to highb)
, v_st_int1_vector_2(lowb to highb)
, v_st_int1_vector_3(lowb to highb)
) :=
arr_st_int1_vector ' (
(others => c_st_int1_vector_2(lowb to highb))) ;
--
(
v_st_time_vector_1(lowb to highb)
, v_st_time_vector_2(lowb to highb)
, v_st_time_vector_3(lowb to highb)
) :=
arr_st_time_vector ' (
(others => c_st_time_vector_2(lowb to highb))) ;
--
(
v_st_phys1_vector_1(lowb to highb)
, v_st_phys1_vector_2(lowb to highb)
, v_st_phys1_vector_3(lowb to highb)
) :=
arr_st_phys1_vector ' (
(others => c_st_phys1_vector_2(lowb to highb))) ;
--
(
v_st_real_vector_1(lowb to highb)
, v_st_real_vector_2(lowb to highb)
, v_st_real_vector_3(lowb to highb)
) :=
arr_st_real_vector ' (
(others => c_st_real_vector_2(lowb to highb))) ;
--
(
v_st_real1_vector_1(lowb to highb)
, v_st_real1_vector_2(lowb to highb)
, v_st_real1_vector_3(lowb to highb)
) :=
arr_st_real1_vector ' (
(others => c_st_real1_vector_2(lowb to highb))) ;
--
(
v_st_rec1_vector_1(lowb to highb)
, v_st_rec1_vector_2(lowb to highb)
, v_st_rec1_vector_3(lowb to highb)
) :=
arr_st_rec1_vector ' (
(others => c_st_rec1_vector_2(lowb to highb))) ;
--
(
v_st_rec2_vector_1(lowb to highb)
, v_st_rec2_vector_2(lowb to highb)
, v_st_rec2_vector_3(lowb to highb)
) :=
arr_st_rec2_vector ' (
(others => c_st_rec2_vector_2(lowb to highb))) ;
--
(
v_st_rec3_vector_1(lowb to highb)
, v_st_rec3_vector_2(lowb to highb)
, v_st_rec3_vector_3(lowb to highb)
) :=
arr_st_rec3_vector ' (
(others => c_st_rec3_vector_2(lowb to highb))) ;
--
(
v_st_arr1_vector_1(lowb to highb)
, v_st_arr1_vector_2(lowb to highb)
, v_st_arr1_vector_3(lowb to highb)
) :=
arr_st_arr1_vector ' (
(others => c_st_arr1_vector_2(lowb to highb))) ;
--
(
v_st_arr2_vector_1(lowb to highb)
, v_st_arr2_vector_2(lowb to highb)
, v_st_arr2_vector_3(lowb to highb)
) :=
arr_st_arr2_vector ' (
(others => c_st_arr2_vector_2(lowb to highb))) ;
--
(
v_st_arr3_vector_1(lowb to highb)
, v_st_arr3_vector_2(lowb to highb)
, v_st_arr3_vector_3(lowb to highb)
) :=
arr_st_arr3_vector ' (
(others => c_st_arr3_vector_2(lowb to highb))) ;
--
--
end Proc1 ;
begin
Proc1 ;
correct := correct and
v_st_boolean_vector_1(lowb to highb) =
c_st_boolean_vector_2(lowb to highb) ;
correct := correct and
v_st_bit_vector_1(lowb to highb) =
c_st_bit_vector_2(lowb to highb) ;
correct := correct and
v_st_severity_level_vector_1(lowb to highb) =
c_st_severity_level_vector_2(lowb to highb) ;
correct := correct and
v_st_string_1(lowb to highb) =
c_st_string_2(lowb to highb) ;
correct := correct and
v_st_enum1_vector_1(lowb to highb) =
c_st_enum1_vector_2(lowb to highb) ;
correct := correct and
v_st_integer_vector_1(lowb to highb) =
c_st_integer_vector_2(lowb to highb) ;
correct := correct and
v_st_int1_vector_1(lowb to highb) =
c_st_int1_vector_2(lowb to highb) ;
correct := correct and
v_st_time_vector_1(lowb to highb) =
c_st_time_vector_2(lowb to highb) ;
correct := correct and
v_st_phys1_vector_1(lowb to highb) =
c_st_phys1_vector_2(lowb to highb) ;
correct := correct and
v_st_real_vector_1(lowb to highb) =
c_st_real_vector_2(lowb to highb) ;
correct := correct and
v_st_real1_vector_1(lowb to highb) =
c_st_real1_vector_2(lowb to highb) ;
correct := correct and
v_st_rec1_vector_1(lowb to highb) =
c_st_rec1_vector_2(lowb to highb) ;
correct := correct and
v_st_rec2_vector_1(lowb to highb) =
c_st_rec2_vector_2(lowb to highb) ;
correct := correct and
v_st_rec3_vector_1(lowb to highb) =
c_st_rec3_vector_2(lowb to highb) ;
correct := correct and
v_st_arr1_vector_1(lowb to highb) =
c_st_arr1_vector_2(lowb to highb) ;
correct := correct and
v_st_arr2_vector_1(lowb to highb) =
c_st_arr2_vector_2(lowb to highb) ;
correct := correct and
v_st_arr3_vector_1(lowb to highb) =
c_st_arr3_vector_2(lowb to highb) ;
--
correct := correct and
v_st_boolean_vector_2(lowb to highb) =
c_st_boolean_vector_2(lowb to highb) ;
correct := correct and
v_st_bit_vector_2(lowb to highb) =
c_st_bit_vector_2(lowb to highb) ;
correct := correct and
v_st_severity_level_vector_2(lowb to highb) =
c_st_severity_level_vector_2(lowb to highb) ;
correct := correct and
v_st_string_2(lowb to highb) =
c_st_string_2(lowb to highb) ;
correct := correct and
v_st_enum1_vector_2(lowb to highb) =
c_st_enum1_vector_2(lowb to highb) ;
correct := correct and
v_st_integer_vector_2(lowb to highb) =
c_st_integer_vector_2(lowb to highb) ;
correct := correct and
v_st_int1_vector_2(lowb to highb) =
c_st_int1_vector_2(lowb to highb) ;
correct := correct and
v_st_time_vector_2(lowb to highb) =
c_st_time_vector_2(lowb to highb) ;
correct := correct and
v_st_phys1_vector_2(lowb to highb) =
c_st_phys1_vector_2(lowb to highb) ;
correct := correct and
v_st_real_vector_2(lowb to highb) =
c_st_real_vector_2(lowb to highb) ;
correct := correct and
v_st_real1_vector_2(lowb to highb) =
c_st_real1_vector_2(lowb to highb) ;
correct := correct and
v_st_rec1_vector_2(lowb to highb) =
c_st_rec1_vector_2(lowb to highb) ;
correct := correct and
v_st_rec2_vector_2(lowb to highb) =
c_st_rec2_vector_2(lowb to highb) ;
correct := correct and
v_st_rec3_vector_2(lowb to highb) =
c_st_rec3_vector_2(lowb to highb) ;
correct := correct and
v_st_arr1_vector_2(lowb to highb) =
c_st_arr1_vector_2(lowb to highb) ;
correct := correct and
v_st_arr2_vector_2(lowb to highb) =
c_st_arr2_vector_2(lowb to highb) ;
correct := correct and
v_st_arr3_vector_2(lowb to highb) =
c_st_arr3_vector_2(lowb to highb) ;
--
correct := correct and
v_st_boolean_vector_3(lowb to highb) =
c_st_boolean_vector_2(lowb to highb) ;
correct := correct and
v_st_bit_vector_3(lowb to highb) =
c_st_bit_vector_2(lowb to highb) ;
correct := correct and
v_st_severity_level_vector_3(lowb to highb) =
c_st_severity_level_vector_2(lowb to highb) ;
correct := correct and
v_st_string_3(lowb to highb) =
c_st_string_2(lowb to highb) ;
correct := correct and
v_st_enum1_vector_3(lowb to highb) =
c_st_enum1_vector_2(lowb to highb) ;
correct := correct and
v_st_integer_vector_3(lowb to highb) =
c_st_integer_vector_2(lowb to highb) ;
correct := correct and
v_st_int1_vector_3(lowb to highb) =
c_st_int1_vector_2(lowb to highb) ;
correct := correct and
v_st_time_vector_3(lowb to highb) =
c_st_time_vector_2(lowb to highb) ;
correct := correct and
v_st_phys1_vector_3(lowb to highb) =
c_st_phys1_vector_2(lowb to highb) ;
correct := correct and
v_st_real_vector_3(lowb to highb) =
c_st_real_vector_2(lowb to highb) ;
correct := correct and
v_st_real1_vector_3(lowb to highb) =
c_st_real1_vector_2(lowb to highb) ;
correct := correct and
v_st_rec1_vector_3(lowb to highb) =
c_st_rec1_vector_2(lowb to highb) ;
correct := correct and
v_st_rec2_vector_3(lowb to highb) =
c_st_rec2_vector_2(lowb to highb) ;
correct := correct and
v_st_rec3_vector_3(lowb to highb) =
c_st_rec3_vector_2(lowb to highb) ;
correct := correct and
v_st_arr1_vector_3(lowb to highb) =
c_st_arr1_vector_2(lowb to highb) ;
correct := correct and
v_st_arr2_vector_3(lowb to highb) =
c_st_arr2_vector_2(lowb to highb) ;
correct := correct and
v_st_arr3_vector_3(lowb to highb) =
c_st_arr3_vector_2(lowb to highb) ;
--
test_report ( "ARCH00035.P3" ,
"Target of a variable assignment may be a " &
"aggregate of slices" ,
correct) ;
end process P3 ;
--
P4 :
process ( Dummy )
type arr_st_boolean_vector is
array (integer range -1 downto - 3 ) of
st_boolean_vector ;
type arr_st_bit_vector is
array (integer range -1 downto - 3 ) of
st_bit_vector ;
type arr_st_severity_level_vector is
array (integer range -1 downto - 3 ) of
st_severity_level_vector ;
type arr_st_string is
array (integer range -1 downto - 3 ) of
st_string ;
type arr_st_enum1_vector is
array (integer range -1 downto - 3 ) of
st_enum1_vector ;
type arr_st_integer_vector is
array (integer range -1 downto - 3 ) of
st_integer_vector ;
type arr_st_int1_vector is
array (integer range -1 downto - 3 ) of
st_int1_vector ;
type arr_st_time_vector is
array (integer range -1 downto - 3 ) of
st_time_vector ;
type arr_st_phys1_vector is
array (integer range -1 downto - 3 ) of
st_phys1_vector ;
type arr_st_real_vector is
array (integer range -1 downto - 3 ) of
st_real_vector ;
type arr_st_real1_vector is
array (integer range -1 downto - 3 ) of
st_real1_vector ;
type arr_st_rec1_vector is
array (integer range -1 downto - 3 ) of
st_rec1_vector ;
type arr_st_rec2_vector is
array (integer range -1 downto - 3 ) of
st_rec2_vector ;
type arr_st_rec3_vector is
array (integer range -1 downto - 3 ) of
st_rec3_vector ;
type arr_st_arr1_vector is
array (integer range -1 downto - 3 ) of
st_arr1_vector ;
type arr_st_arr2_vector is
array (integer range -1 downto - 3 ) of
st_arr2_vector ;
type arr_st_arr3_vector is
array (integer range -1 downto - 3 ) of
st_arr3_vector ;
--
variable v_st_boolean_vector_1 : st_boolean_vector :=
c_st_boolean_vector_1 ;
variable v_st_bit_vector_1 : st_bit_vector :=
c_st_bit_vector_1 ;
variable v_st_severity_level_vector_1 : st_severity_level_vector :=
c_st_severity_level_vector_1 ;
variable v_st_string_1 : st_string :=
c_st_string_1 ;
variable v_st_enum1_vector_1 : st_enum1_vector :=
c_st_enum1_vector_1 ;
variable v_st_integer_vector_1 : st_integer_vector :=
c_st_integer_vector_1 ;
variable v_st_int1_vector_1 : st_int1_vector :=
c_st_int1_vector_1 ;
variable v_st_time_vector_1 : st_time_vector :=
c_st_time_vector_1 ;
variable v_st_phys1_vector_1 : st_phys1_vector :=
c_st_phys1_vector_1 ;
variable v_st_real_vector_1 : st_real_vector :=
c_st_real_vector_1 ;
variable v_st_real1_vector_1 : st_real1_vector :=
c_st_real1_vector_1 ;
variable v_st_rec1_vector_1 : st_rec1_vector :=
c_st_rec1_vector_1 ;
variable v_st_rec2_vector_1 : st_rec2_vector :=
c_st_rec2_vector_1 ;
variable v_st_rec3_vector_1 : st_rec3_vector :=
c_st_rec3_vector_1 ;
variable v_st_arr1_vector_1 : st_arr1_vector :=
c_st_arr1_vector_1 ;
variable v_st_arr2_vector_1 : st_arr2_vector :=
c_st_arr2_vector_1 ;
variable v_st_arr3_vector_1 : st_arr3_vector :=
c_st_arr3_vector_1 ;
--
variable v_st_boolean_vector_2 : st_boolean_vector :=
c_st_boolean_vector_1 ;
variable v_st_bit_vector_2 : st_bit_vector :=
c_st_bit_vector_1 ;
variable v_st_severity_level_vector_2 : st_severity_level_vector :=
c_st_severity_level_vector_1 ;
variable v_st_string_2 : st_string :=
c_st_string_1 ;
variable v_st_enum1_vector_2 : st_enum1_vector :=
c_st_enum1_vector_1 ;
variable v_st_integer_vector_2 : st_integer_vector :=
c_st_integer_vector_1 ;
variable v_st_int1_vector_2 : st_int1_vector :=
c_st_int1_vector_1 ;
variable v_st_time_vector_2 : st_time_vector :=
c_st_time_vector_1 ;
variable v_st_phys1_vector_2 : st_phys1_vector :=
c_st_phys1_vector_1 ;
variable v_st_real_vector_2 : st_real_vector :=
c_st_real_vector_1 ;
variable v_st_real1_vector_2 : st_real1_vector :=
c_st_real1_vector_1 ;
variable v_st_rec1_vector_2 : st_rec1_vector :=
c_st_rec1_vector_1 ;
variable v_st_rec2_vector_2 : st_rec2_vector :=
c_st_rec2_vector_1 ;
variable v_st_rec3_vector_2 : st_rec3_vector :=
c_st_rec3_vector_1 ;
variable v_st_arr1_vector_2 : st_arr1_vector :=
c_st_arr1_vector_1 ;
variable v_st_arr2_vector_2 : st_arr2_vector :=
c_st_arr2_vector_1 ;
variable v_st_arr3_vector_2 : st_arr3_vector :=
c_st_arr3_vector_1 ;
--
variable v_st_boolean_vector_3 : st_boolean_vector :=
c_st_boolean_vector_1 ;
variable v_st_bit_vector_3 : st_bit_vector :=
c_st_bit_vector_1 ;
variable v_st_severity_level_vector_3 : st_severity_level_vector :=
c_st_severity_level_vector_1 ;
variable v_st_string_3 : st_string :=
c_st_string_1 ;
variable v_st_enum1_vector_3 : st_enum1_vector :=
c_st_enum1_vector_1 ;
variable v_st_integer_vector_3 : st_integer_vector :=
c_st_integer_vector_1 ;
variable v_st_int1_vector_3 : st_int1_vector :=
c_st_int1_vector_1 ;
variable v_st_time_vector_3 : st_time_vector :=
c_st_time_vector_1 ;
variable v_st_phys1_vector_3 : st_phys1_vector :=
c_st_phys1_vector_1 ;
variable v_st_real_vector_3 : st_real_vector :=
c_st_real_vector_1 ;
variable v_st_real1_vector_3 : st_real1_vector :=
c_st_real1_vector_1 ;
variable v_st_rec1_vector_3 : st_rec1_vector :=
c_st_rec1_vector_1 ;
variable v_st_rec2_vector_3 : st_rec2_vector :=
c_st_rec2_vector_1 ;
variable v_st_rec3_vector_3 : st_rec3_vector :=
c_st_rec3_vector_1 ;
variable v_st_arr1_vector_3 : st_arr1_vector :=
c_st_arr1_vector_1 ;
variable v_st_arr2_vector_3 : st_arr2_vector :=
c_st_arr2_vector_1 ;
variable v_st_arr3_vector_3 : st_arr3_vector :=
c_st_arr3_vector_1 ;
--
variable correct : boolean := true ;
--
procedure Proc1 (
v_st_boolean_vector_2 : inout st_boolean_vector
; v_st_bit_vector_2 : inout st_bit_vector
; v_st_severity_level_vector_2 : inout st_severity_level_vector
; v_st_string_2 : inout st_string
; v_st_enum1_vector_2 : inout st_enum1_vector
; v_st_integer_vector_2 : inout st_integer_vector
; v_st_int1_vector_2 : inout st_int1_vector
; v_st_time_vector_2 : inout st_time_vector
; v_st_phys1_vector_2 : inout st_phys1_vector
; v_st_real_vector_2 : inout st_real_vector
; v_st_real1_vector_2 : inout st_real1_vector
; v_st_rec1_vector_2 : inout st_rec1_vector
; v_st_rec2_vector_2 : inout st_rec2_vector
; v_st_rec3_vector_2 : inout st_rec3_vector
; v_st_arr1_vector_2 : inout st_arr1_vector
; v_st_arr2_vector_2 : inout st_arr2_vector
; v_st_arr3_vector_2 : inout st_arr3_vector
)
is
begin
(
v_st_boolean_vector_1(lowb to highb)
, v_st_boolean_vector_2(lowb to highb)
, v_st_boolean_vector_3(lowb to highb)
) :=
arr_st_boolean_vector ' (
(others => c_st_boolean_vector_2(lowb to highb))) ;
--
(
v_st_bit_vector_1(lowb to highb)
, v_st_bit_vector_2(lowb to highb)
, v_st_bit_vector_3(lowb to highb)
) :=
arr_st_bit_vector ' (
(others => c_st_bit_vector_2(lowb to highb))) ;
--
(
v_st_severity_level_vector_1(lowb to highb)
, v_st_severity_level_vector_2(lowb to highb)
, v_st_severity_level_vector_3(lowb to highb)
) :=
arr_st_severity_level_vector ' (
(others => c_st_severity_level_vector_2(lowb to highb))) ;
--
(
v_st_string_1(lowb to highb)
, v_st_string_2(lowb to highb)
, v_st_string_3(lowb to highb)
) :=
arr_st_string ' (
(others => c_st_string_2(lowb to highb))) ;
--
(
v_st_enum1_vector_1(lowb to highb)
, v_st_enum1_vector_2(lowb to highb)
, v_st_enum1_vector_3(lowb to highb)
) :=
arr_st_enum1_vector ' (
(others => c_st_enum1_vector_2(lowb to highb))) ;
--
(
v_st_integer_vector_1(lowb to highb)
, v_st_integer_vector_2(lowb to highb)
, v_st_integer_vector_3(lowb to highb)
) :=
arr_st_integer_vector ' (
(others => c_st_integer_vector_2(lowb to highb))) ;
--
(
v_st_int1_vector_1(lowb to highb)
, v_st_int1_vector_2(lowb to highb)
, v_st_int1_vector_3(lowb to highb)
) :=
arr_st_int1_vector ' (
(others => c_st_int1_vector_2(lowb to highb))) ;
--
(
v_st_time_vector_1(lowb to highb)
, v_st_time_vector_2(lowb to highb)
, v_st_time_vector_3(lowb to highb)
) :=
arr_st_time_vector ' (
(others => c_st_time_vector_2(lowb to highb))) ;
--
(
v_st_phys1_vector_1(lowb to highb)
, v_st_phys1_vector_2(lowb to highb)
, v_st_phys1_vector_3(lowb to highb)
) :=
arr_st_phys1_vector ' (
(others => c_st_phys1_vector_2(lowb to highb))) ;
--
(
v_st_real_vector_1(lowb to highb)
, v_st_real_vector_2(lowb to highb)
, v_st_real_vector_3(lowb to highb)
) :=
arr_st_real_vector ' (
(others => c_st_real_vector_2(lowb to highb))) ;
--
(
v_st_real1_vector_1(lowb to highb)
, v_st_real1_vector_2(lowb to highb)
, v_st_real1_vector_3(lowb to highb)
) :=
arr_st_real1_vector ' (
(others => c_st_real1_vector_2(lowb to highb))) ;
--
(
v_st_rec1_vector_1(lowb to highb)
, v_st_rec1_vector_2(lowb to highb)
, v_st_rec1_vector_3(lowb to highb)
) :=
arr_st_rec1_vector ' (
(others => c_st_rec1_vector_2(lowb to highb))) ;
--
(
v_st_rec2_vector_1(lowb to highb)
, v_st_rec2_vector_2(lowb to highb)
, v_st_rec2_vector_3(lowb to highb)
) :=
arr_st_rec2_vector ' (
(others => c_st_rec2_vector_2(lowb to highb))) ;
--
(
v_st_rec3_vector_1(lowb to highb)
, v_st_rec3_vector_2(lowb to highb)
, v_st_rec3_vector_3(lowb to highb)
) :=
arr_st_rec3_vector ' (
(others => c_st_rec3_vector_2(lowb to highb))) ;
--
(
v_st_arr1_vector_1(lowb to highb)
, v_st_arr1_vector_2(lowb to highb)
, v_st_arr1_vector_3(lowb to highb)
) :=
arr_st_arr1_vector ' (
(others => c_st_arr1_vector_2(lowb to highb))) ;
--
(
v_st_arr2_vector_1(lowb to highb)
, v_st_arr2_vector_2(lowb to highb)
, v_st_arr2_vector_3(lowb to highb)
) :=
arr_st_arr2_vector ' (
(others => c_st_arr2_vector_2(lowb to highb))) ;
--
(
v_st_arr3_vector_1(lowb to highb)
, v_st_arr3_vector_2(lowb to highb)
, v_st_arr3_vector_3(lowb to highb)
) :=
arr_st_arr3_vector ' (
(others => c_st_arr3_vector_2(lowb to highb))) ;
--
--
end Proc1 ;
begin
Proc1 (
v_st_boolean_vector_2
, v_st_bit_vector_2
, v_st_severity_level_vector_2
, v_st_string_2
, v_st_enum1_vector_2
, v_st_integer_vector_2
, v_st_int1_vector_2
, v_st_time_vector_2
, v_st_phys1_vector_2
, v_st_real_vector_2
, v_st_real1_vector_2
, v_st_rec1_vector_2
, v_st_rec2_vector_2
, v_st_rec3_vector_2
, v_st_arr1_vector_2
, v_st_arr2_vector_2
, v_st_arr3_vector_2
) ;
correct := correct and
v_st_boolean_vector_1(lowb to highb) =
c_st_boolean_vector_2(lowb to highb) ;
correct := correct and
v_st_bit_vector_1(lowb to highb) =
c_st_bit_vector_2(lowb to highb) ;
correct := correct and
v_st_severity_level_vector_1(lowb to highb) =
c_st_severity_level_vector_2(lowb to highb) ;
correct := correct and
v_st_string_1(lowb to highb) =
c_st_string_2(lowb to highb) ;
correct := correct and
v_st_enum1_vector_1(lowb to highb) =
c_st_enum1_vector_2(lowb to highb) ;
correct := correct and
v_st_integer_vector_1(lowb to highb) =
c_st_integer_vector_2(lowb to highb) ;
correct := correct and
v_st_int1_vector_1(lowb to highb) =
c_st_int1_vector_2(lowb to highb) ;
correct := correct and
v_st_time_vector_1(lowb to highb) =
c_st_time_vector_2(lowb to highb) ;
correct := correct and
v_st_phys1_vector_1(lowb to highb) =
c_st_phys1_vector_2(lowb to highb) ;
correct := correct and
v_st_real_vector_1(lowb to highb) =
c_st_real_vector_2(lowb to highb) ;
correct := correct and
v_st_real1_vector_1(lowb to highb) =
c_st_real1_vector_2(lowb to highb) ;
correct := correct and
v_st_rec1_vector_1(lowb to highb) =
c_st_rec1_vector_2(lowb to highb) ;
correct := correct and
v_st_rec2_vector_1(lowb to highb) =
c_st_rec2_vector_2(lowb to highb) ;
correct := correct and
v_st_rec3_vector_1(lowb to highb) =
c_st_rec3_vector_2(lowb to highb) ;
correct := correct and
v_st_arr1_vector_1(lowb to highb) =
c_st_arr1_vector_2(lowb to highb) ;
correct := correct and
v_st_arr2_vector_1(lowb to highb) =
c_st_arr2_vector_2(lowb to highb) ;
correct := correct and
v_st_arr3_vector_1(lowb to highb) =
c_st_arr3_vector_2(lowb to highb) ;
--
correct := correct and
v_st_boolean_vector_2(lowb to highb) =
c_st_boolean_vector_2(lowb to highb) ;
correct := correct and
v_st_bit_vector_2(lowb to highb) =
c_st_bit_vector_2(lowb to highb) ;
correct := correct and
v_st_severity_level_vector_2(lowb to highb) =
c_st_severity_level_vector_2(lowb to highb) ;
correct := correct and
v_st_string_2(lowb to highb) =
c_st_string_2(lowb to highb) ;
correct := correct and
v_st_enum1_vector_2(lowb to highb) =
c_st_enum1_vector_2(lowb to highb) ;
correct := correct and
v_st_integer_vector_2(lowb to highb) =
c_st_integer_vector_2(lowb to highb) ;
correct := correct and
v_st_int1_vector_2(lowb to highb) =
c_st_int1_vector_2(lowb to highb) ;
correct := correct and
v_st_time_vector_2(lowb to highb) =
c_st_time_vector_2(lowb to highb) ;
correct := correct and
v_st_phys1_vector_2(lowb to highb) =
c_st_phys1_vector_2(lowb to highb) ;
correct := correct and
v_st_real_vector_2(lowb to highb) =
c_st_real_vector_2(lowb to highb) ;
correct := correct and
v_st_real1_vector_2(lowb to highb) =
c_st_real1_vector_2(lowb to highb) ;
correct := correct and
v_st_rec1_vector_2(lowb to highb) =
c_st_rec1_vector_2(lowb to highb) ;
correct := correct and
v_st_rec2_vector_2(lowb to highb) =
c_st_rec2_vector_2(lowb to highb) ;
correct := correct and
v_st_rec3_vector_2(lowb to highb) =
c_st_rec3_vector_2(lowb to highb) ;
correct := correct and
v_st_arr1_vector_2(lowb to highb) =
c_st_arr1_vector_2(lowb to highb) ;
correct := correct and
v_st_arr2_vector_2(lowb to highb) =
c_st_arr2_vector_2(lowb to highb) ;
correct := correct and
v_st_arr3_vector_2(lowb to highb) =
c_st_arr3_vector_2(lowb to highb) ;
--
correct := correct and
v_st_boolean_vector_3(lowb to highb) =
c_st_boolean_vector_2(lowb to highb) ;
correct := correct and
v_st_bit_vector_3(lowb to highb) =
c_st_bit_vector_2(lowb to highb) ;
correct := correct and
v_st_severity_level_vector_3(lowb to highb) =
c_st_severity_level_vector_2(lowb to highb) ;
correct := correct and
v_st_string_3(lowb to highb) =
c_st_string_2(lowb to highb) ;
correct := correct and
v_st_enum1_vector_3(lowb to highb) =
c_st_enum1_vector_2(lowb to highb) ;
correct := correct and
v_st_integer_vector_3(lowb to highb) =
c_st_integer_vector_2(lowb to highb) ;
correct := correct and
v_st_int1_vector_3(lowb to highb) =
c_st_int1_vector_2(lowb to highb) ;
correct := correct and
v_st_time_vector_3(lowb to highb) =
c_st_time_vector_2(lowb to highb) ;
correct := correct and
v_st_phys1_vector_3(lowb to highb) =
c_st_phys1_vector_2(lowb to highb) ;
correct := correct and
v_st_real_vector_3(lowb to highb) =
c_st_real_vector_2(lowb to highb) ;
correct := correct and
v_st_real1_vector_3(lowb to highb) =
c_st_real1_vector_2(lowb to highb) ;
correct := correct and
v_st_rec1_vector_3(lowb to highb) =
c_st_rec1_vector_2(lowb to highb) ;
correct := correct and
v_st_rec2_vector_3(lowb to highb) =
c_st_rec2_vector_2(lowb to highb) ;
correct := correct and
v_st_rec3_vector_3(lowb to highb) =
c_st_rec3_vector_2(lowb to highb) ;
correct := correct and
v_st_arr1_vector_3(lowb to highb) =
c_st_arr1_vector_2(lowb to highb) ;
correct := correct and
v_st_arr2_vector_3(lowb to highb) =
c_st_arr2_vector_2(lowb to highb) ;
correct := correct and
v_st_arr3_vector_3(lowb to highb) =
c_st_arr3_vector_2(lowb to highb) ;
--
test_report ( "ARCH00035.P4" ,
"Target of a variable assignment may be a " &
"aggregate of slices" ,
correct) ;
end process P4 ;
--
end ARCH00035 ;
--
entity ENT00035_Test_Bench is
end ENT00035_Test_Bench ;
--
architecture ARCH00035_Test_Bench of ENT00035_Test_Bench is
begin
L1:
block
component UUT
end component ;
for CIS1 : UUT use entity WORK.E00000 ( ARCH00035 ) ;
begin
CIS1 : UUT ;
end block L1 ;
end ARCH00035_Test_Bench ;
| gpl-3.0 | 93f3cee7c79313c4cc2e99513d0ccf40 | 0.507729 | 3.207008 | false | false | false | false |
grwlf/vsim | vhdl_ct/ct00651.vhd | 1 | 12,392 | -- NEED RESULT: ARCH00651: The value and predefined attributes of an interface object (generic) of mode 'in' for an entity may be read failed
-- NEED RESULT: ARCH00651: The value and predefined attributes of an interface object (port) of mode 'in' for an entity may be read failed
-- NEED RESULT: ARCH00651: The value and predefined attributes of an interface object (generic) of mode 'in' for a block may be read failed
-- NEED RESULT: ARCH00651: The value and predefined attributes of an interface object (port) of mode 'in' for a block may be read failed
-- NEED RESULT: ARCH00651: The value and predefined signal attributes of an interface object (port) of mode 'in' for an entity may be read passed
-- NEED RESULT: ARCH00651.Proc1: The value and predefined attributes of an interface object (constant parameter) of mode 'in' for a subp may be read failed
-- NEED RESULT: ARCH00651.Proc2: The value and predefined attributes of an interface object (variable parameter) of mode 'in' for a subp may be read failed
-- NEED RESULT: ARCH00651: The value and predefined attributes of an interface object (signal parameter) of mode 'in' for a subp may be read failed
-- NEED RESULT: ARCH00651: The value and predefined signal attributes of an interface object (signal parameter) of mode 'in' for a subp may be read (except DELAYED, STABLE, and QUIET) passed
-- NEED RESULT: ARCH00651: The value and predefined signal attributes of an interface object (port) of mode 'in' for a block may be read passed
-------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
-------------------------------------------------------------------------------
--
-- TEST NAME:
--
-- CT00651
--
-- AUTHOR:
--
-- G. Tominovich
--
-- TEST OBJECTIVES:
--
-- 4.3.3 (13)
--
-- DESIGN UNIT ORDERING:
--
-- ENT00651(ARCH00651)
-- ENT00651_Test_Bench(ARCH00651_Test_Bench)
--
-- REVISION HISTORY:
--
-- 26-AUG-1987 - initial revision
--
-- NOTES:
--
-- self-checking
--
--
use WORK.STANDARD_TYPES.all ;
entity ENT00651 is
generic ( G : Bit_Vector ) ;
port ( Pt1 : in Bit_Vector ;
Pt2 : in Integer ) ;
end ENT00651 ;
--
architecture ARCH00651 of ENT00651 is
function To_Real ( P : Integer ) return Real is
begin
if P = -1 then
return -1.0 ;
else
return -2.0 ;
end if ;
end To_Real ;
procedure Proc1 ( constant G : in Bit_Vector ) is
subtype ST_Up is integer range G'RANGE ;
subtype ST_Down is integer range G'REVERSE_RANGE(1) ;
begin
test_report ( "ARCH00651.Proc1" ,
"The value and predefined attributes of an interface "&
"object (constant parameter) of mode 'in' for a subp may be read" ,
(G = B"10101010101") and
(G'LEFT = 10) and
(G'RIGHT(1) = 20) and
(G'HIGH(1) = 20) and
(G'LOW = 10) and
(G'LENGTH = 11) and
(ST_Up'LEFT = 10) and
(ST_Up'RIGHT = 20) and
(ST_Down'LEFT = 20) and
(ST_Down'RIGHT = 10) ) ;
end Proc1 ;
procedure Proc2 ( variable G : inout Bit_Vector ) is
subtype ST_Up is integer range G'RANGE ;
subtype ST_Down is integer range G'REVERSE_RANGE(1) ;
begin
test_report ( "ARCH00651.Proc2" ,
"The value and predefined attributes of an interface "&
"object (variable parameter) of mode 'in' for a subp may be read" ,
(G = B"10101010101") and
(G'LEFT = 10) and
(G'RIGHT(1) = 20) and
(G'HIGH(1) = 20) and
(G'LOW = 10) and
(G'LENGTH = 11) and
(ST_Up'LEFT = 10) and
(ST_Up'RIGHT = 20) and
(ST_Down'LEFT = 20) and
(ST_Down'RIGHT = 10) ) ;
end Proc2 ;
function Func1 ( signal Pt1 : in Bit_Vector ) return boolean is
subtype ST_Up is integer range Pt1'RANGE ;
subtype ST_Down is integer range Pt1'REVERSE_RANGE(1) ;
begin
return (Pt1 = B"10101010101") and
(Pt1'LEFT = 10) and
(Pt1'RIGHT(1) = 20) and
(Pt1'HIGH(1) = 20) and
(Pt1'LOW = 10) and
(Pt1'LENGTH = 11) and
(ST_Up'LEFT = 10) and
(ST_Up'RIGHT = 20) and
(ST_Down'LEFT = 20) and
(ST_Down'RIGHT = 10)
;
end Func1 ;
function Func2 ( signal Pt2 : in Integer ) return boolean is
begin
return (Pt2 = -1) and
(Pt2'EVENT) and
(Pt2'ACTIVE) and
(STD.STANDARD.NOW - Pt2'LAST_EVENT = 10 ns) and
(STD.STANDARD.NOW - Pt2'LAST_ACTIVE = 10 ns) and
(Pt2'LAST_VALUE = -2)
;
end Func2 ;
begin
P1 :
process -- Check formal generic on entity
subtype ST_Up is integer range G'RANGE ;
subtype ST_Down is integer range G'REVERSE_RANGE(1) ;
begin
test_report ( "ARCH00651" ,
"The value and predefined attributes of an interface "&
"object (generic) of mode 'in' for an entity may be read" ,
(G = B"10101010101") and
(G'LEFT = 10) and
(G'RIGHT(1) = 20) and
(G'HIGH(1) = 20) and
(G'LOW = 10) and
(G'LENGTH = 11) and
(ST_Up'LEFT = 10) and
(ST_Up'RIGHT = 20) and
(ST_Down'LEFT = 20) and
(ST_Down'RIGHT = 10) ) ;
wait ;
end process P1 ;
P2 :
process -- Check formal port on entity (no signal attributes)
subtype ST_Up is integer range Pt1'RANGE ;
subtype ST_Down is integer range Pt1'REVERSE_RANGE(1) ;
begin
test_report ( "ARCH00651" ,
"The value and predefined attributes of an interface "&
"object (port) of mode 'in' for an entity may be read" ,
(Pt1 = B"10101010101") and
(Pt1'LEFT = 10) and
(Pt1'RIGHT(1) = 20) and
(Pt1'HIGH(1) = 20) and
(Pt1'LOW = 10) and
(Pt1'LENGTH = 11) and
(ST_Up'LEFT = 10) and
(ST_Up'RIGHT = 20) and
(ST_Down'LEFT = 20) and
(ST_Down'RIGHT = 10)
) ;
wait ;
end process P2 ;
P3 :
process ( Pt2 ) -- Check formal port on entity (signal attributes)
variable First_Time : boolean := True ;
begin
if First_Time then
First_Time := false ;
else
test_report ( "ARCH00651" ,
"The value and predefined signal attributes of an interface "&
"object (port) of mode 'in' for an entity may be read" ,
(Pt2 = -1) and
(Pt2'DELAYED(10 ns) = -2) and
(Not Pt2'STABLE(10 ns)) and
(Not Pt2'QUIET(10 ns)) and
(Pt2'EVENT) and
(Pt2'ACTIVE) and
(STD.STANDARD.NOW - Pt2'LAST_EVENT = 10 ns) and
(STD.STANDARD.NOW - Pt2'LAST_ACTIVE = 10 ns) and
(Pt2'LAST_VALUE = -2)
) ;
end if ;
end process P3 ;
P4 :
process ( Pt2 ) -- Check formal parameters in a subprogram
variable V : Bit_Vector (G'Range) := G ;
variable First_Time : boolean := True ;
begin
if First_Time then
First_Time := false ;
else
Proc1 (G => G) ;
Proc2 (G => V) ;
test_report ( "ARCH00651" ,
"The value and predefined attributes of an interface "&
"object (signal parameter) of mode 'in' for a subp "&
"may be read" ,
Func1 (Pt1 => Pt1)
) ;
test_report ( "ARCH00651" ,
"The value and predefined signal attributes of an interface "&
"object (signal parameter) of mode 'in' for a subp "&
"may be read (except DELAYED, STABLE, and QUIET)" ,
Func2 (Pt2 => Pt2)
) ;
end if ;
end process P4 ;
L1 : -- Check block ports/generics
block
generic ( G : in Bit_Vector ) ;
generic map ( G => G ) ;
port ( Pt1 : in Bit_Vector ;
Pt2 : in Real ) ;
port map ( Pt1 => Pt1, Pt2 => To_Real(Pt2) ) ;
begin
BP1 :
process -- Check formal generic on block
subtype ST_Up is integer range G'RANGE ;
subtype ST_Down is integer range G'REVERSE_RANGE(1) ;
begin
test_report ( "ARCH00651" ,
"The value and predefined attributes of an interface "&
"object (generic) of mode 'in' for a block may be read" ,
(G = B"10101010101") and
(G'LEFT = 10) and
(G'RIGHT(1) = 20) and
(G'HIGH(1) = 20) and
(G'LOW = 10) and
(G'LENGTH = 11) and
(ST_Up'LEFT = 10) and
(ST_Up'RIGHT = 20) and
(ST_Down'LEFT = 20) and
(ST_Down'RIGHT = 10) ) ;
wait ;
end process BP1 ;
BP2 :
process -- Check formal port on block (no signal attributes)
subtype ST_Up is integer range Pt1'RANGE ;
subtype ST_Down is integer range Pt1'REVERSE_RANGE(1) ;
begin
test_report ( "ARCH00651" ,
"The value and predefined attributes of an interface "&
"object (port) of mode 'in' for a block may be read" ,
(Pt1 = B"10101010101") and
(Pt1'LEFT = 10) and
(Pt1'RIGHT(1) = 20) and
(Pt1'HIGH(1) = 20) and
(Pt1'LOW = 10) and
(Pt1'LENGTH = 11) and
(ST_Up'LEFT = 10) and
(ST_Up'RIGHT = 20) and
(ST_Down'LEFT = 20) and
(ST_Down'RIGHT = 10)
) ;
wait ;
end process BP2 ;
BP3 :
process ( Pt2 ) -- Check formal port on a block (signal attributes)
variable First_Time : boolean := True ;
begin
if First_Time then
First_Time := false ;
else
test_report ( "ARCH00651" ,
"The value and predefined signal attributes of an interface "&
"object (port) of mode 'in' for a block may be read" ,
(Pt2 = -1.0) and
(Pt2'DELAYED(10 ns) = -2.0) and
(Not Pt2'STABLE(10 ns)) and
(Not Pt2'QUIET(10 ns)) and
(Pt2'EVENT) and
(Pt2'ACTIVE) and
(STD.STANDARD.NOW - Pt2'LAST_EVENT = 10 ns) and
(STD.STANDARD.NOW - Pt2'LAST_ACTIVE = 10 ns) and
(Pt2'LAST_VALUE = -2.0)
) ;
end if ;
end process BP3 ;
end block L1 ;
end ARCH00651 ;
--
entity ENT00651_Test_Bench is
end ENT00651_Test_Bench ;
architecture ARCH00651_Test_Bench of ENT00651_Test_Bench is
begin
L1:
block
component UUT
end component ;
subtype ST is Bit_Vector ( 10 to 20 ) ;
constant C : ST := B"10101010101" ;
signal S1 : ST := C ;
signal S2 : Integer := -2 ;
for CIS1 : UUT use entity WORK.ENT00651 ( ARCH00651 )
generic map ( G => C )
port map ( S1, S2 ) ;
begin
SigA : S2 <= transport -1 after 10 ns ;
CIS1 : UUT ;
end block L1 ;
end ARCH00651_Test_Bench ;
--
| gpl-3.0 | ec0d991394ec3da7e7bb411bfd3e21b2 | 0.484264 | 3.930225 | false | true | false | false |
grwlf/vsim | vhdl_ct/ct00436.vhd | 1 | 6,335 | -- NEED RESULT: ARCH00436.Chk_s3: Guarded assignment controlled by implicit guard passed
-- NEED RESULT: ARCH00436.Chk_s2: Guarded assignment controlled by implicit guard passed
-- NEED RESULT: ARCH00436.Chk_s1: Guarded assignment controlled by implicit guard passed
-- NEED RESULT: ARCH00436.Chk_s1: Guarded assignment controlled by implicit guard passed
-- NEED RESULT: ARCH00436.Chk_s2: Guarded assignment controlled by implicit guard passed
-- NEED RESULT: ARCH00436.Chk_s3: Guarded assignment controlled by implicit guard passed
-- NEED RESULT: ARCH00436.Chk_gs3: Guarded assignment controlled by explicit guard passed
-- NEED RESULT: ARCH00436.Chk_gs2: Guarded assignment controlled by explicit guard passed
-- NEED RESULT: ARCH00436.Chk_gs1: Guarded assignment controlled by explicit guard passed
-------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
-------------------------------------------------------------------------------
--
-- TEST NAME:
--
-- ct00436
--
-- AUTHOR:
--
-- G. Tominovich
--
-- TEST OBJECTIVES:
--
-- 9.5 (4)
-- 9.5 (5)
-- 9.5 (9)
--
-- DESIGN UNIT ORDERING:
--
-- E00000(ARCH00436)
-- ENT00436_Test_Bench(ARCH00436_Test_Bench)
--
-- REVISION HISTORY:
--
-- 4-AUG-1987 - initial revision
--
-- NOTES:
--
-- self-checking
--
--
use WORK.STANDARD_TYPES.all ;
architecture ARCH00436 of E00000 is
function rfunc ( to_resolve : boolean_vector ) return boolean ;
subtype rboolean is rfunc boolean ;
signal Control : boolean := false ;
signal s1, s2, s3 : rboolean ;
alias gs1 : rboolean is s1 ;
alias gs2 : rboolean is s2 ;
alias gs3 : rboolean is s3 ;
signal Guard : boolean := false ;
function rfunc ( to_resolve : boolean_vector ) return boolean is
variable result : boolean := false ;
begin
for i in to_resolve'range loop
result := result or to_resolve (i) ;
end loop ;
return result ;
end rfunc ;
begin
B1 :
block ( Control ) -- Implicit Guard Signal
begin
s1 <= guarded transport Not s1 after 5 ns, s1 after 10 ns ;
s2 <= guarded transport False after 5 ns, True after 10 ns when s2 else
True after 5 ns, False after 10 ns ;
with s3 select
s3 <= guarded transport False after 5 ns, True after 10 ns when True,
True after 5 ns, False after 10 ns when others ;
end block B1 ;
Control <= transport True after 10 ns, False after 11 ns ;
Chk_s1 :
process ( s1 )
variable SavTime : Time ;
variable counter : Integer := 0 ;
begin
case counter is
when 0 =>
SavTime := Std.Standard.Now ;
when 1 =>
test_report ( "ARCH00436.Chk_s1" ,
"Guarded assignment controlled by implicit guard" ,
s1 and ((SavTime+15 ns) = Std.Standard.Now) ) ;
when 2 =>
test_report ( "ARCH00436.Chk_s1" ,
"Guarded assignment controlled by implicit guard" ,
(Not s1) and ((SavTime+20 ns) = Std.Standard.Now) ) ;
when 3 =>
test_report ( "ARCH00436.Chk_gs1" ,
"Guarded assignment controlled by explicit guard" ,
gs1 and ((SavTime+105 ns) = Std.Standard.Now) ) ;
when others =>
test_report ( "ARCH00436.Chk_s1" ,
"Guarded assignment controlled by implicit guard" ,
False ) ;
end case ;
counter := counter + 1;
end process Chk_s1 ;
Chk_s2 :
process ( s2 )
variable SavTime : Time ;
variable counter : Integer := 0 ;
begin
case counter is
when 0 =>
SavTime := Std.Standard.Now ;
when 1 =>
test_report ( "ARCH00436.Chk_s2" ,
"Guarded assignment controlled by implicit guard" ,
s2 and ((SavTime+15 ns) = Std.Standard.Now) ) ;
when 2 =>
test_report ( "ARCH00436.Chk_s2" ,
"Guarded assignment controlled by implicit guard" ,
(Not s2) and ((SavTime+20 ns) = Std.Standard.Now) ) ;
when 3 =>
test_report ( "ARCH00436.Chk_gs2" ,
"Guarded assignment controlled by explicit guard" ,
gs2 and ((SavTime+105 ns) = Std.Standard.Now) ) ;
when others =>
test_report ( "ARCH00436.Chk_s2" ,
"Guarded assignment controlled by implicit guard" ,
False ) ;
end case ;
counter := counter + 1;
end process Chk_s2 ;
Chk_s3 :
process ( s3 )
variable SavTime : Time ;
variable counter : Integer := 0 ;
begin
case counter is
when 0 =>
SavTime := Std.Standard.Now ;
when 1 =>
test_report ( "ARCH00436.Chk_s3" ,
"Guarded assignment controlled by implicit guard" ,
s3 and ((SavTime+15 ns) = Std.Standard.Now) ) ;
when 2 =>
test_report ( "ARCH00436.Chk_s3" ,
"Guarded assignment controlled by implicit guard" ,
(Not s3) and ((SavTime+20 ns) = Std.Standard.Now) ) ;
when 3 =>
test_report ( "ARCH00436.Chk_gs3" ,
"Guarded assignment controlled by explicit guard" ,
gs3 and ((SavTime+105 ns) = Std.Standard.Now) ) ;
when others =>
test_report ( "ARCH00436.Chk_s3" ,
"Guarded assignment controlled by implicit guard" ,
False ) ;
end case ;
counter := counter + 1;
end process Chk_s3 ;
-- The following depend on the explicit signal Guard
gs1 <= guarded transport Not gs1 after 5 ns ;
gs2 <= guarded transport False after 5 ns when gs2 else
True after 5 ns ;
with gs3 select
gs3 <= guarded transport False after 5 ns when True,
True after 5 ns when others ;
Guard <= transport True after 100 ns, False after 101 ns ;
end ARCH00436 ;
entity ENT00436_Test_Bench is
end ENT00436_Test_Bench ;
architecture ARCH00436_Test_Bench of ENT00436_Test_Bench is
begin
L1:
block
component UUT
end component ;
for CIS1 : UUT use entity WORK.E00000 ( ARCH00436 ) ;
begin
CIS1 : UUT ;
end block L1 ;
end ARCH00436_Test_Bench ;
| gpl-3.0 | 7e3ac46ab6aa8349eccc60b250847aaf | 0.578374 | 3.793413 | false | true | false | false |
grwlf/vsim | vhdl_ct/ct00420.vhd | 1 | 7,809 | -- NEED RESULT: ARCH00420.P1: Multi inertial transactions occurred on concurrent signal asg passed
-- NEED RESULT: ARCH00420: One inertial transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00420: Old transactions were removed on a concurrent signal asg passed
-- NEED RESULT: ARCH00420: One inertial transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00420: Inertial semantics check on a concurrent signal asg passed
-- NEED RESULT: P1: Inertial transactions completed entirely passed
-------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
-------------------------------------------------------------------------------
--
-- TEST NAME:
--
-- CT00420
--
-- AUTHOR:
--
-- G. Tominovich
--
-- TEST OBJECTIVES:
--
-- 9.5 (3)
-- 9.5.1 (1)
-- 9.5.1 (2)
--
-- DESIGN UNIT ORDERING:
--
-- ENT00420(ARCH00420)
-- ENT00420_Test_Bench(ARCH00420_Test_Bench)
--
-- REVISION HISTORY:
--
-- 30-JUL-1987 - initial revision
--
-- NOTES:
--
-- self-checking
-- automatically generated
--
use WORK.STANDARD_TYPES.all ;
entity ENT00420 is
port (
s_st_rec3 : inout st_rec3
) ;
subtype chk_sig_type is integer range -1 to 100 ;
signal chk_st_rec3 : chk_sig_type := -1 ;
--
end ENT00420 ;
--
--
architecture ARCH00420 of ENT00420 is
subtype chk_time_type is Time ;
signal s_st_rec3_savt : chk_time_type := 0 ns ;
--
subtype chk_cnt_type is Integer ;
signal s_st_rec3_cnt : chk_cnt_type := 0 ;
--
type select_type is range 1 to 6 ;
signal st_rec3_select : select_type := 1 ;
--
begin
CHG1 :
process
variable correct : boolean ;
begin
case s_st_rec3_cnt is
when 0
=> null ;
-- s_st_rec3.f2.f2 <=
-- c_st_rec3_2.f2.f2 after 10 ns,
-- c_st_rec3_1.f2.f2 after 20 ns ;
--
when 1
=> correct :=
s_st_rec3.f2.f2 =
c_st_rec3_2.f2.f2 and
(s_st_rec3_savt + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_rec3.f2.f2 =
c_st_rec3_1.f2.f2 and
(s_st_rec3_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00420.P1" ,
"Multi inertial transactions occurred on " &
"concurrent signal asg",
correct ) ;
--
st_rec3_select <= transport 2 ;
-- s_st_rec3.f2.f2 <=
-- c_st_rec3_2.f2.f2 after 10 ns ,
-- c_st_rec3_1.f2.f2 after 20 ns ,
-- c_st_rec3_2.f2.f2 after 30 ns ,
-- c_st_rec3_1.f2.f2 after 40 ns ;
--
when 3
=> correct :=
s_st_rec3.f2.f2 =
c_st_rec3_2.f2.f2 and
(s_st_rec3_savt + 10 ns) = Std.Standard.Now ;
st_rec3_select <= transport 3 ;
-- s_st_rec3.f2.f2 <=
-- c_st_rec3_1.f2.f2 after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_rec3.f2.f2 =
c_st_rec3_1.f2.f2 and
(s_st_rec3_savt + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00420" ,
"One inertial transaction occurred on a " &
"concurrent signal asg",
correct ) ;
st_rec3_select <= transport 4 ;
-- s_st_rec3.f2.f2 <=
-- c_st_rec3_1.f2.f2 after 100 ns ;
--
when 5
=> correct :=
correct and
s_st_rec3.f2.f2 =
c_st_rec3_1.f2.f2 and
(s_st_rec3_savt + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00420" ,
"Old transactions were removed on a " &
"concurrent signal asg",
correct ) ;
st_rec3_select <= transport 5 ;
-- s_st_rec3.f2.f2 <=
-- c_st_rec3_2.f2.f2 after 10 ns ,
-- c_st_rec3_1.f2.f2 after 20 ns ,
-- c_st_rec3_2.f2.f2 after 30 ns ,
-- c_st_rec3_1.f2.f2 after 40 ns ;
--
when 6
=> correct :=
correct and
s_st_rec3.f2.f2 =
c_st_rec3_2.f2.f2 and
(s_st_rec3_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00420" ,
"One inertial transaction occurred on a " &
"concurrent signal asg",
correct ) ;
st_rec3_select <= transport 6 ;
-- Last transaction above is marked
-- s_st_rec3.f2.f2 <=
-- c_st_rec3_1.f2.f2 after 40 ns ;
--
when 7
=> correct :=
correct and
s_st_rec3.f2.f2 =
c_st_rec3_1.f2.f2 and
(s_st_rec3_savt + 30 ns) = Std.Standard.Now ;
--
when 8
=> correct :=
correct and
s_st_rec3.f2.f2 =
c_st_rec3_1.f2.f2 and
(s_st_rec3_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00420" ,
"Inertial semantics check on a concurrent " &
"signal asg",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00420" ,
"Inertial semantics check on a concurrent " &
"signal asg",
false ) ;
--
end case ;
--
s_st_rec3_savt <= transport Std.Standard.Now ;
chk_st_rec3 <= transport s_st_rec3_cnt
after (1 us - Std.Standard.Now) ;
s_st_rec3_cnt <= transport s_st_rec3_cnt + 1 ;
wait until (not s_st_rec3.f2.f2'Quiet) and
(s_st_rec3_savt /= Std.Standard.Now) ;
--
end process CHG1 ;
--
PGEN_CHKP_1 :
process ( chk_st_rec3 )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P1" ,
"Inertial transactions completed entirely",
chk_st_rec3 = 8 ) ;
end if ;
end process PGEN_CHKP_1 ;
--
--
s_st_rec3.f2.f2 <=
c_st_rec3_2.f2.f2 after 10 ns,
c_st_rec3_1.f2.f2 after 20 ns
when st_rec3_select = 1 else
--
c_st_rec3_2.f2.f2 after 10 ns ,
c_st_rec3_1.f2.f2 after 20 ns ,
c_st_rec3_2.f2.f2 after 30 ns ,
c_st_rec3_1.f2.f2 after 40 ns
when st_rec3_select = 2 else
--
c_st_rec3_1.f2.f2 after 5 ns
when st_rec3_select = 3 else
--
c_st_rec3_1.f2.f2 after 100 ns
when st_rec3_select = 4 else
--
c_st_rec3_2.f2.f2 after 10 ns ,
c_st_rec3_1.f2.f2 after 20 ns ,
c_st_rec3_2.f2.f2 after 30 ns ,
c_st_rec3_1.f2.f2 after 40 ns
when st_rec3_select = 5 else
--
-- Last transaction above is marked
c_st_rec3_1.f2.f2 after 40 ns ;
--
end ARCH00420 ;
--
--
use WORK.STANDARD_TYPES.all ;
entity ENT00420_Test_Bench is
signal s_st_rec3 : st_rec3
:= c_st_rec3_1 ;
--
end ENT00420_Test_Bench ;
--
--
architecture ARCH00420_Test_Bench of ENT00420_Test_Bench is
begin
L1:
block
component UUT
port (
s_st_rec3 : inout st_rec3
) ;
end component ;
--
for CIS1 : UUT use entity WORK.ENT00420 ( ARCH00420 ) ;
begin
CIS1 : UUT
port map (
s_st_rec3
)
;
end block L1 ;
end ARCH00420_Test_Bench ;
| gpl-3.0 | ba761df7dbaa07285f7be480758ad92f | 0.474965 | 3.171812 | false | true | false | false |
grwlf/vsim | vhdl_ct/ct00229.vhd | 1 | 9,414 | -------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
-------------------------------------------------------------------------------
--
-- TEST NAME:
--
-- CT00229
--
-- AUTHOR:
--
-- A. Wilmot
--
-- TEST OBJECTIVES:
--
-- 1.1.1.2 (6)
--
-- DESIGN UNIT ORDERING:
--
-- GENERIC_STANDARD_TYPES(ARCH00229)
-- ENT00229_Test_Bench(ARCH00229_Test_Bench)
--
-- REVISION HISTORY:
--
-- 15-JUN-1987 - initial revision
--
-- NOTES:
--
-- self-checking
-- automatically generated
--
use WORK.STANDARD_TYPES ;
use STANDARD_TYPES.test_report, STANDARD_TYPES.switch,
STANDARD_TYPES.up, STANDARD_TYPES.down, STANDARD_TYPES.toggle,
STANDARD_TYPES."=" ;
architecture ARCH00229 of GENERIC_STANDARD_TYPES is
signal i_boolean_1, i_boolean_2 : boolean
:= c_boolean_1 ;
signal i_bit_1, i_bit_2 : bit
:= c_bit_1 ;
signal i_severity_level_1, i_severity_level_2 : severity_level
:= c_severity_level_1 ;
signal i_character_1, i_character_2 : character
:= c_character_1 ;
signal i_t_enum1_1, i_t_enum1_2 : t_enum1
:= c_t_enum1_1 ;
signal i_st_enum1_1, i_st_enum1_2 : st_enum1
:= c_st_enum1_1 ;
signal i_integer_1, i_integer_2 : integer
:= c_integer_1 ;
signal i_t_int1_1, i_t_int1_2 : t_int1
:= c_t_int1_1 ;
signal i_st_int1_1, i_st_int1_2 : st_int1
:= c_st_int1_1 ;
signal i_time_1, i_time_2 : time
:= c_time_1 ;
signal i_t_phys1_1, i_t_phys1_2 : t_phys1
:= c_t_phys1_1 ;
signal i_st_phys1_1, i_st_phys1_2 : st_phys1
:= c_st_phys1_1 ;
signal i_real_1, i_real_2 : real
:= c_real_1 ;
signal i_t_real1_1, i_t_real1_2 : t_real1
:= c_t_real1_1 ;
signal i_st_real1_1, i_st_real1_2 : st_real1
:= c_st_real1_1 ;
--
begin
L1:
block
port (
toggle : inout switch := down;
i_boolean_1, i_boolean_2 : inout boolean
:= c_boolean_1
;
i_bit_1, i_bit_2 : inout bit
:= c_bit_1
;
i_severity_level_1, i_severity_level_2 : inout severity_level
:= c_severity_level_1
;
i_character_1, i_character_2 : inout character
:= c_character_1
;
i_t_enum1_1, i_t_enum1_2 : inout t_enum1
:= c_t_enum1_1
;
i_st_enum1_1, i_st_enum1_2 : inout st_enum1
:= c_st_enum1_1
;
i_integer_1, i_integer_2 : inout integer
:= c_integer_1
;
i_t_int1_1, i_t_int1_2 : inout t_int1
:= c_t_int1_1
;
i_st_int1_1, i_st_int1_2 : inout st_int1
:= c_st_int1_1
;
i_time_1, i_time_2 : inout time
:= c_time_1
;
i_t_phys1_1, i_t_phys1_2 : inout t_phys1
:= c_t_phys1_1
;
i_st_phys1_1, i_st_phys1_2 : inout st_phys1
:= c_st_phys1_1
;
i_real_1, i_real_2 : inout real
:= c_real_1
;
i_t_real1_1, i_t_real1_2 : inout t_real1
:= c_t_real1_1
;
i_st_real1_1, i_st_real1_2 : inout st_real1
:= c_st_real1_1
) ;
port map (
toggle ,
i_boolean_1, i_boolean_2,
i_bit_1, i_bit_2,
i_severity_level_1, i_severity_level_2,
i_character_1, i_character_2,
i_t_enum1_1, i_t_enum1_2,
i_st_enum1_1, i_st_enum1_2,
i_integer_1, i_integer_2,
i_t_int1_1, i_t_int1_2,
i_st_int1_1, i_st_int1_2,
i_time_1, i_time_2,
i_t_phys1_1, i_t_phys1_2,
i_st_phys1_1, i_st_phys1_2,
i_real_1, i_real_2,
i_t_real1_1, i_t_real1_2,
i_st_real1_1, i_st_real1_2
) ;
--
begin
process
variable correct : boolean := true ;
begin
correct := correct and i_boolean_1 = c_boolean_1
and i_boolean_2 = c_boolean_1 ;
correct := correct and i_bit_1 = c_bit_1
and i_bit_2 = c_bit_1 ;
correct := correct and i_severity_level_1 = c_severity_level_1
and i_severity_level_2 = c_severity_level_1 ;
correct := correct and i_character_1 = c_character_1
and i_character_2 = c_character_1 ;
correct := correct and i_t_enum1_1 = c_t_enum1_1
and i_t_enum1_2 = c_t_enum1_1 ;
correct := correct and i_st_enum1_1 = c_st_enum1_1
and i_st_enum1_2 = c_st_enum1_1 ;
correct := correct and i_integer_1 = c_integer_1
and i_integer_2 = c_integer_1 ;
correct := correct and i_t_int1_1 = c_t_int1_1
and i_t_int1_2 = c_t_int1_1 ;
correct := correct and i_st_int1_1 = c_st_int1_1
and i_st_int1_2 = c_st_int1_1 ;
correct := correct and i_time_1 = c_time_1
and i_time_2 = c_time_1 ;
correct := correct and i_t_phys1_1 = c_t_phys1_1
and i_t_phys1_2 = c_t_phys1_1 ;
correct := correct and i_st_phys1_1 = c_st_phys1_1
and i_st_phys1_2 = c_st_phys1_1 ;
correct := correct and i_real_1 = c_real_1
and i_real_2 = c_real_1 ;
correct := correct and i_t_real1_1 = c_t_real1_1
and i_t_real1_2 = c_t_real1_1 ;
correct := correct and i_st_real1_1 = c_st_real1_1
and i_st_real1_2 = c_st_real1_1 ;
--
test_report ( "ENT00229" ,
"Associated scalar inout ports with generic subtypes" ,
correct) ;
--
toggle <= up ;
i_boolean_1 <= c_boolean_2 ;
i_boolean_2 <= c_boolean_2 ;
i_bit_1 <= c_bit_2 ;
i_bit_2 <= c_bit_2 ;
i_severity_level_1 <= c_severity_level_2 ;
i_severity_level_2 <= c_severity_level_2 ;
i_character_1 <= c_character_2 ;
i_character_2 <= c_character_2 ;
i_t_enum1_1 <= c_t_enum1_2 ;
i_t_enum1_2 <= c_t_enum1_2 ;
i_st_enum1_1 <= c_st_enum1_2 ;
i_st_enum1_2 <= c_st_enum1_2 ;
i_integer_1 <= c_integer_2 ;
i_integer_2 <= c_integer_2 ;
i_t_int1_1 <= c_t_int1_2 ;
i_t_int1_2 <= c_t_int1_2 ;
i_st_int1_1 <= c_st_int1_2 ;
i_st_int1_2 <= c_st_int1_2 ;
i_time_1 <= c_time_2 ;
i_time_2 <= c_time_2 ;
i_t_phys1_1 <= c_t_phys1_2 ;
i_t_phys1_2 <= c_t_phys1_2 ;
i_st_phys1_1 <= c_st_phys1_2 ;
i_st_phys1_2 <= c_st_phys1_2 ;
i_real_1 <= c_real_2 ;
i_real_2 <= c_real_2 ;
i_t_real1_1 <= c_t_real1_2 ;
i_t_real1_2 <= c_t_real1_2 ;
i_st_real1_1 <= c_st_real1_2 ;
i_st_real1_2 <= c_st_real1_2 ;
wait ;
end process ;
end block L1 ;
P00229 :
process ( toggle )
variable correct : boolean := true ;
begin
if toggle = up then
correct := correct and i_boolean_1 = c_boolean_2
and i_boolean_2 = c_boolean_2 ;
correct := correct and i_bit_1 = c_bit_2
and i_bit_2 = c_bit_2 ;
correct := correct and i_severity_level_1 = c_severity_level_2
and i_severity_level_2 = c_severity_level_2 ;
correct := correct and i_character_1 = c_character_2
and i_character_2 = c_character_2 ;
correct := correct and i_t_enum1_1 = c_t_enum1_2
and i_t_enum1_2 = c_t_enum1_2 ;
correct := correct and i_st_enum1_1 = c_st_enum1_2
and i_st_enum1_2 = c_st_enum1_2 ;
correct := correct and i_integer_1 = c_integer_2
and i_integer_2 = c_integer_2 ;
correct := correct and i_t_int1_1 = c_t_int1_2
and i_t_int1_2 = c_t_int1_2 ;
correct := correct and i_st_int1_1 = c_st_int1_2
and i_st_int1_2 = c_st_int1_2 ;
correct := correct and i_time_1 = c_time_2
and i_time_2 = c_time_2 ;
correct := correct and i_t_phys1_1 = c_t_phys1_2
and i_t_phys1_2 = c_t_phys1_2 ;
correct := correct and i_st_phys1_1 = c_st_phys1_2
and i_st_phys1_2 = c_st_phys1_2 ;
correct := correct and i_real_1 = c_real_2
and i_real_2 = c_real_2 ;
correct := correct and i_t_real1_1 = c_t_real1_2
and i_t_real1_2 = c_t_real1_2 ;
correct := correct and i_st_real1_1 = c_st_real1_2
and i_st_real1_2 = c_st_real1_2 ;
end if ;
--
test_report ( "ENT00229.P00229" ,
"Associated scalar inout ports with generic subtypes",
correct) ;
end process P00229 ;
end ARCH00229 ;
--
entity ENT00229_Test_Bench is
end ENT00229_Test_Bench ;
--
architecture ARCH00229_Test_Bench of ENT00229_Test_Bench is
begin
L1:
block
component UUT
end component ;
--
for CIS1 : UUT use entity WORK.GENERIC_STANDARD_TYPES ( ARCH00229 ) ;
begin
CIS1 : UUT ;
end block L1 ;
end ARCH00229_Test_Bench ;
| gpl-3.0 | 5c2cd20c55c13d31ff78bfa3f60a815a | 0.480455 | 2.896615 | false | false | false | false |
grwlf/vsim | vhdl_ct/ct00041.vhd | 1 | 9,137 | -- NEED RESULT: ARCH00041.P1: Target of a variable assignment may be a indexed name prefixed by an indexed name passed
-- NEED RESULT: ARCH00041.P2: Target of a variable assignment may be a indexed name prefixed by an indexed name passed
-- NEED RESULT: ARCH00041.P3: Target of a variable assignment may be a indexed name prefixed by an indexed name passed
-- NEED RESULT: ARCH00041.P4: Target of a variable assignment may be a indexed name prefixed by an indexed name passed
-------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
-------------------------------------------------------------------------------
--
-- TEST NAME:
--
-- CT00041
--
-- AUTHOR:
--
-- G. Tominovich
--
-- TEST OBJECTIVES:
--
-- 8.4 (1)
-- 8.4 (3)
--
-- DESIGN UNIT ORDERING:
--
-- E00000(ARCH00041)
-- ENT00041_Test_Bench(ARCH00041_Test_Bench)
--
-- REVISION HISTORY:
--
-- 29-JUN-1987 - initial revision
--
-- NOTES:
--
-- self-checking
-- automatically generated
--
use WORK.STANDARD_TYPES.all ;
architecture ARCH00041 of E00000 is
signal Dummy : Boolean := false ;
--
begin
P1 :
process ( Dummy )
variable v_st_rec3_vector : st_rec3_vector :=
c_st_rec3_vector_1 ;
variable v_st_arr1_vector : st_arr1_vector :=
c_st_arr1_vector_1 ;
variable v_st_arr2_vector : st_arr2_vector :=
c_st_arr2_vector_1 ;
variable v_st_arr3_vector : st_arr3_vector :=
c_st_arr3_vector_1 ;
--
variable correct : boolean := true ;
begin
v_st_rec3_vector(lowb).f3(st_arr2'Left(1),st_arr2'Left(2)) :=
c_st_rec3_vector_2(lowb).f3(st_arr2'Right(1),st_arr2'Right(2)) ;
v_st_arr1_vector(lowb)(st_arr1'Left) :=
c_st_arr1_vector_2(lowb)(st_arr1'Right) ;
v_st_arr2_vector(lowb)(st_arr2'Left(1),st_arr2'Left(2)) :=
c_st_arr2_vector_2(lowb)(st_arr2'Right(1),st_arr2'Right(2)) ;
v_st_arr3_vector(lowb)(st_arr3'Left(1),st_arr3'Left(2)) :=
c_st_arr3_vector_2(lowb)(st_arr3'Right(1),st_arr3'Right(2)) ;
--
correct :=
correct and
v_st_rec3_vector(lowb).f3(st_arr2'Left(1),st_arr2'Left(2)) =
c_st_arr1_2 ;
--
correct :=
correct and
v_st_arr1_vector(lowb)(st_arr1'Left) =
c_st_int1_2 ;
--
correct :=
correct and
v_st_arr2_vector(lowb)(st_arr2'Left(1),st_arr2'Left(2)) =
c_st_arr1_2 ;
--
correct :=
correct and
v_st_arr3_vector(lowb)(st_arr3'Left(1),st_arr3'Left(2)) =
c_st_rec3_2 ;
--
--
test_report ( "ARCH00041.P1" ,
"Target of a variable assignment may be a " &
"indexed name prefixed by an indexed name" ,
correct) ;
end process P1 ;
--
P2 :
process ( Dummy )
variable correct : boolean := true ;
--
procedure Proc1 is
variable v_st_rec3_vector : st_rec3_vector :=
c_st_rec3_vector_1 ;
variable v_st_arr1_vector : st_arr1_vector :=
c_st_arr1_vector_1 ;
variable v_st_arr2_vector : st_arr2_vector :=
c_st_arr2_vector_1 ;
variable v_st_arr3_vector : st_arr3_vector :=
c_st_arr3_vector_1 ;
--
begin
v_st_rec3_vector(lowb).f3(st_arr2'Left(1),st_arr2'Left(2)) :=
c_st_rec3_vector_2(lowb).f3(st_arr2'Right(1),st_arr2'Right(2)) ;
v_st_arr1_vector(lowb)(st_arr1'Left) :=
c_st_arr1_vector_2(lowb)(st_arr1'Right) ;
v_st_arr2_vector(lowb)(st_arr2'Left(1),st_arr2'Left(2)) :=
c_st_arr2_vector_2(lowb)(st_arr2'Right(1),st_arr2'Right(2)) ;
v_st_arr3_vector(lowb)(st_arr3'Left(1),st_arr3'Left(2)) :=
c_st_arr3_vector_2(lowb)(st_arr3'Right(1),st_arr3'Right(2)) ;
--
correct :=
correct and
v_st_rec3_vector(lowb).f3(st_arr2'Left(1),st_arr2'Left(2)) =
c_st_arr1_2 ;
--
correct :=
correct and
v_st_arr1_vector(lowb)(st_arr1'Left) =
c_st_int1_2 ;
--
correct :=
correct and
v_st_arr2_vector(lowb)(st_arr2'Left(1),st_arr2'Left(2)) =
c_st_arr1_2 ;
--
correct :=
correct and
v_st_arr3_vector(lowb)(st_arr3'Left(1),st_arr3'Left(2)) =
c_st_rec3_2 ;
--
--
end Proc1 ;
begin
Proc1 ;
test_report ( "ARCH00041.P2" ,
"Target of a variable assignment may be a " &
"indexed name prefixed by an indexed name" ,
correct) ;
end process P2 ;
--
P3 :
process ( Dummy )
variable v_st_rec3_vector : st_rec3_vector :=
c_st_rec3_vector_1 ;
variable v_st_arr1_vector : st_arr1_vector :=
c_st_arr1_vector_1 ;
variable v_st_arr2_vector : st_arr2_vector :=
c_st_arr2_vector_1 ;
variable v_st_arr3_vector : st_arr3_vector :=
c_st_arr3_vector_1 ;
--
variable correct : boolean := true ;
--
procedure Proc1 is
begin
v_st_rec3_vector(lowb).f3(st_arr2'Left(1),st_arr2'Left(2)) :=
c_st_rec3_vector_2(lowb).f3(st_arr2'Right(1),st_arr2'Right(2)) ;
v_st_arr1_vector(lowb)(st_arr1'Left) :=
c_st_arr1_vector_2(lowb)(st_arr1'Right) ;
v_st_arr2_vector(lowb)(st_arr2'Left(1),st_arr2'Left(2)) :=
c_st_arr2_vector_2(lowb)(st_arr2'Right(1),st_arr2'Right(2)) ;
v_st_arr3_vector(lowb)(st_arr3'Left(1),st_arr3'Left(2)) :=
c_st_arr3_vector_2(lowb)(st_arr3'Right(1),st_arr3'Right(2)) ;
--
end Proc1 ;
begin
Proc1 ;
correct :=
correct and
v_st_rec3_vector(lowb).f3(st_arr2'Left(1),st_arr2'Left(2)) =
c_st_arr1_2 ;
--
correct :=
correct and
v_st_arr1_vector(lowb)(st_arr1'Left) =
c_st_int1_2 ;
--
correct :=
correct and
v_st_arr2_vector(lowb)(st_arr2'Left(1),st_arr2'Left(2)) =
c_st_arr1_2 ;
--
correct :=
correct and
v_st_arr3_vector(lowb)(st_arr3'Left(1),st_arr3'Left(2)) =
c_st_rec3_2 ;
--
--
test_report ( "ARCH00041.P3" ,
"Target of a variable assignment may be a " &
"indexed name prefixed by an indexed name" ,
correct) ;
end process P3 ;
--
P4 :
process ( Dummy )
variable v_st_rec3_vector : st_rec3_vector :=
c_st_rec3_vector_1 ;
variable v_st_arr1_vector : st_arr1_vector :=
c_st_arr1_vector_1 ;
variable v_st_arr2_vector : st_arr2_vector :=
c_st_arr2_vector_1 ;
variable v_st_arr3_vector : st_arr3_vector :=
c_st_arr3_vector_1 ;
--
variable correct : boolean := true ;
--
procedure Proc1 (
v_st_rec3_vector : inout st_rec3_vector
; v_st_arr1_vector : inout st_arr1_vector
; v_st_arr2_vector : inout st_arr2_vector
; v_st_arr3_vector : inout st_arr3_vector
)
is
begin
v_st_rec3_vector(lowb).f3(st_arr2'Left(1),st_arr2'Left(2)) :=
c_st_rec3_vector_2(lowb).f3(st_arr2'Right(1),st_arr2'Right(2)) ;
v_st_arr1_vector(lowb)(st_arr1'Left) :=
c_st_arr1_vector_2(lowb)(st_arr1'Right) ;
v_st_arr2_vector(lowb)(st_arr2'Left(1),st_arr2'Left(2)) :=
c_st_arr2_vector_2(lowb)(st_arr2'Right(1),st_arr2'Right(2)) ;
v_st_arr3_vector(lowb)(st_arr3'Left(1),st_arr3'Left(2)) :=
c_st_arr3_vector_2(lowb)(st_arr3'Right(1),st_arr3'Right(2)) ;
--
end Proc1 ;
begin
Proc1 (
v_st_rec3_vector
, v_st_arr1_vector
, v_st_arr2_vector
, v_st_arr3_vector
) ;
correct :=
correct and
v_st_rec3_vector(lowb).f3(st_arr2'Left(1),st_arr2'Left(2)) =
c_st_arr1_2 ;
--
correct :=
correct and
v_st_arr1_vector(lowb)(st_arr1'Left) =
c_st_int1_2 ;
--
correct :=
correct and
v_st_arr2_vector(lowb)(st_arr2'Left(1),st_arr2'Left(2)) =
c_st_arr1_2 ;
--
correct :=
correct and
v_st_arr3_vector(lowb)(st_arr3'Left(1),st_arr3'Left(2)) =
c_st_rec3_2 ;
--
--
test_report ( "ARCH00041.P4" ,
"Target of a variable assignment may be a " &
"indexed name prefixed by an indexed name" ,
correct) ;
end process P4 ;
--
end ARCH00041 ;
--
entity ENT00041_Test_Bench is
end ENT00041_Test_Bench ;
--
architecture ARCH00041_Test_Bench of ENT00041_Test_Bench is
begin
L1:
block
component UUT
end component ;
for CIS1 : UUT use entity WORK.E00000 ( ARCH00041 ) ;
begin
CIS1 : UUT ;
end block L1 ;
end ARCH00041_Test_Bench ;
| gpl-3.0 | 7faa59e803a1697f2c73335e5cc00c84 | 0.520849 | 2.863366 | false | false | false | false |
grwlf/vsim | vhdl_ct/ct00389.vhd | 1 | 68,291 | -- NEED RESULT: ARCH00389.P1: Multi inertial transactions occurred on concurrent signal asg passed
-- NEED RESULT: ARCH00389.P2: Multi inertial transactions occurred on concurrent signal asg passed
-- NEED RESULT: ARCH00389.P3: Multi inertial transactions occurred on concurrent signal asg passed
-- NEED RESULT: ARCH00389.P4: Multi inertial transactions occurred on concurrent signal asg passed
-- NEED RESULT: ARCH00389.P5: Multi inertial transactions occurred on concurrent signal asg passed
-- NEED RESULT: ARCH00389.P6: Multi inertial transactions occurred on concurrent signal asg passed
-- NEED RESULT: ARCH00389.P7: Multi inertial transactions occurred on concurrent signal asg passed
-- NEED RESULT: ARCH00389.P8: Multi inertial transactions occurred on concurrent signal asg passed
-- NEED RESULT: ARCH00389.P9: Multi inertial transactions occurred on concurrent signal asg passed
-- NEED RESULT: ARCH00389: One inertial transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00389: One inertial transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00389: One inertial transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00389: One inertial transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00389: One inertial transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00389: One inertial transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00389: One inertial transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00389: One inertial transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00389: One inertial transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00389: Old transactions were removed on a concurrent signal asg passed
-- NEED RESULT: ARCH00389: Old transactions were removed on a concurrent signal asg passed
-- NEED RESULT: ARCH00389: Old transactions were removed on a concurrent signal asg passed
-- NEED RESULT: ARCH00389: Old transactions were removed on a concurrent signal asg passed
-- NEED RESULT: ARCH00389: Old transactions were removed on a concurrent signal asg passed
-- NEED RESULT: ARCH00389: Old transactions were removed on a concurrent signal asg passed
-- NEED RESULT: ARCH00389: Old transactions were removed on a concurrent signal asg passed
-- NEED RESULT: ARCH00389: Old transactions were removed on a concurrent signal asg passed
-- NEED RESULT: ARCH00389: Old transactions were removed on a concurrent signal asg passed
-- NEED RESULT: ARCH00389: One inertial transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00389: One inertial transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00389: One inertial transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00389: One inertial transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00389: One inertial transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00389: One inertial transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00389: One inertial transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00389: One inertial transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00389: One inertial transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00389: Inertial semantics check on a concurrent signal asg passed
-- NEED RESULT: ARCH00389: Inertial semantics check on a concurrent signal asg passed
-- NEED RESULT: ARCH00389: Inertial semantics check on a concurrent signal asg passed
-- NEED RESULT: ARCH00389: Inertial semantics check on a concurrent signal asg passed
-- NEED RESULT: ARCH00389: Inertial semantics check on a concurrent signal asg passed
-- NEED RESULT: ARCH00389: Inertial semantics check on a concurrent signal asg passed
-- NEED RESULT: ARCH00389: Inertial semantics check on a concurrent signal asg passed
-- NEED RESULT: ARCH00389: Inertial semantics check on a concurrent signal asg passed
-- NEED RESULT: ARCH00389: Inertial semantics check on a concurrent signal asg passed
-- NEED RESULT: P9: Inertial transactions completed entirely passed
-- NEED RESULT: P8: Inertial transactions completed entirely passed
-- NEED RESULT: P7: Inertial transactions completed entirely passed
-- NEED RESULT: P6: Inertial transactions completed entirely passed
-- NEED RESULT: P5: Inertial transactions completed entirely passed
-- NEED RESULT: P4: Inertial transactions completed entirely passed
-- NEED RESULT: P3: Inertial transactions completed entirely passed
-- NEED RESULT: P2: Inertial transactions completed entirely passed
-- NEED RESULT: P1: Inertial transactions completed entirely passed
-------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
-------------------------------------------------------------------------------
--
-- TEST NAME:
--
-- CT00389
--
-- AUTHOR:
--
-- G. Tominovich
--
-- TEST OBJECTIVES:
--
-- 9.5 (3)
-- 9.5.2 (1)
--
-- DESIGN UNIT ORDERING:
--
-- ENT00389(ARCH00389)
-- ENT00389_Test_Bench(ARCH00389_Test_Bench)
--
-- REVISION HISTORY:
--
-- 30-JUL-1987 - initial revision
--
-- NOTES:
--
-- self-checking
-- automatically generated
--
use WORK.STANDARD_TYPES.all ;
entity ENT00389 is
end ENT00389 ;
--
--
architecture ARCH00389 of ENT00389 is
subtype chk_sig_type is integer range -1 to 100 ;
signal chk_st_boolean_vector : chk_sig_type := -1 ;
signal chk_st_severity_level_vector : chk_sig_type := -1 ;
signal chk_st_string : chk_sig_type := -1 ;
signal chk_st_enum1_vector : chk_sig_type := -1 ;
signal chk_st_integer_vector : chk_sig_type := -1 ;
signal chk_st_time_vector : chk_sig_type := -1 ;
signal chk_st_real_vector : chk_sig_type := -1 ;
signal chk_st_rec1_vector : chk_sig_type := -1 ;
signal chk_st_arr2_vector : chk_sig_type := -1 ;
--
subtype chk_time_type is Time ;
signal s_st_boolean_vector_savt : chk_time_type := 0 ns ;
signal s_st_severity_level_vector_savt : chk_time_type := 0 ns ;
signal s_st_string_savt : chk_time_type := 0 ns ;
signal s_st_enum1_vector_savt : chk_time_type := 0 ns ;
signal s_st_integer_vector_savt : chk_time_type := 0 ns ;
signal s_st_time_vector_savt : chk_time_type := 0 ns ;
signal s_st_real_vector_savt : chk_time_type := 0 ns ;
signal s_st_rec1_vector_savt : chk_time_type := 0 ns ;
signal s_st_arr2_vector_savt : chk_time_type := 0 ns ;
--
subtype chk_cnt_type is Integer ;
signal s_st_boolean_vector_cnt : chk_cnt_type := 0 ;
signal s_st_severity_level_vector_cnt : chk_cnt_type := 0 ;
signal s_st_string_cnt : chk_cnt_type := 0 ;
signal s_st_enum1_vector_cnt : chk_cnt_type := 0 ;
signal s_st_integer_vector_cnt : chk_cnt_type := 0 ;
signal s_st_time_vector_cnt : chk_cnt_type := 0 ;
signal s_st_real_vector_cnt : chk_cnt_type := 0 ;
signal s_st_rec1_vector_cnt : chk_cnt_type := 0 ;
signal s_st_arr2_vector_cnt : chk_cnt_type := 0 ;
--
type select_type is range 1 to 6 ;
signal st_boolean_vector_select : select_type := 1 ;
signal st_severity_level_vector_select : select_type := 1 ;
signal st_string_select : select_type := 1 ;
signal st_enum1_vector_select : select_type := 1 ;
signal st_integer_vector_select : select_type := 1 ;
signal st_time_vector_select : select_type := 1 ;
signal st_real_vector_select : select_type := 1 ;
signal st_rec1_vector_select : select_type := 1 ;
signal st_arr2_vector_select : select_type := 1 ;
--
signal s_st_boolean_vector : st_boolean_vector
:= c_st_boolean_vector_1 ;
signal s_st_severity_level_vector : st_severity_level_vector
:= c_st_severity_level_vector_1 ;
signal s_st_string : st_string
:= c_st_string_1 ;
signal s_st_enum1_vector : st_enum1_vector
:= c_st_enum1_vector_1 ;
signal s_st_integer_vector : st_integer_vector
:= c_st_integer_vector_1 ;
signal s_st_time_vector : st_time_vector
:= c_st_time_vector_1 ;
signal s_st_real_vector : st_real_vector
:= c_st_real_vector_1 ;
signal s_st_rec1_vector : st_rec1_vector
:= c_st_rec1_vector_1 ;
signal s_st_arr2_vector : st_arr2_vector
:= c_st_arr2_vector_1 ;
--
begin
CHG1 :
process
variable correct : boolean ;
begin
case s_st_boolean_vector_cnt is
when 0
=> null ;
-- s_st_boolean_vector(lowb to highb-1) <=
-- c_st_boolean_vector_2(lowb to highb-1) after 10 ns,
-- c_st_boolean_vector_1(lowb to highb-1) after 20 ns ;
--
when 1
=> correct :=
s_st_boolean_vector(lowb to highb-1) =
c_st_boolean_vector_2(lowb to highb-1) and
(s_st_boolean_vector_savt + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_boolean_vector(lowb to highb-1) =
c_st_boolean_vector_1(lowb to highb-1) and
(s_st_boolean_vector_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00389.P1" ,
"Multi inertial transactions occurred on " &
"concurrent signal asg",
correct ) ;
--
st_boolean_vector_select <= transport 2 ;
-- s_st_boolean_vector(lowb to highb-1) <=
-- c_st_boolean_vector_2(lowb to highb-1) after 10 ns ,
-- c_st_boolean_vector_1(lowb to highb-1) after 20 ns ,
-- c_st_boolean_vector_2(lowb to highb-1) after 30 ns ,
-- c_st_boolean_vector_1(lowb to highb-1) after 40 ns ;
--
when 3
=> correct :=
s_st_boolean_vector(lowb to highb-1) =
c_st_boolean_vector_2(lowb to highb-1) and
(s_st_boolean_vector_savt + 10 ns) = Std.Standard.Now ;
st_boolean_vector_select <= transport 3 ;
-- s_st_boolean_vector(lowb to highb-1) <=
-- c_st_boolean_vector_1(lowb to highb-1) after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_boolean_vector(lowb to highb-1) =
c_st_boolean_vector_1(lowb to highb-1) and
(s_st_boolean_vector_savt + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00389" ,
"One inertial transaction occurred on a " &
"concurrent signal asg",
correct ) ;
st_boolean_vector_select <= transport 4 ;
-- s_st_boolean_vector(lowb to highb-1) <=
-- c_st_boolean_vector_1(lowb to highb-1) after 100 ns ;
--
when 5
=> correct :=
correct and
s_st_boolean_vector(lowb to highb-1) =
c_st_boolean_vector_1(lowb to highb-1) and
(s_st_boolean_vector_savt + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00389" ,
"Old transactions were removed on a " &
"concurrent signal asg",
correct ) ;
st_boolean_vector_select <= transport 5 ;
-- s_st_boolean_vector(lowb to highb-1) <=
-- c_st_boolean_vector_2(lowb to highb-1) after 10 ns ,
-- c_st_boolean_vector_1(lowb to highb-1) after 20 ns ,
-- c_st_boolean_vector_2(lowb to highb-1) after 30 ns ,
-- c_st_boolean_vector_1(lowb to highb-1) after 40 ns ;
--
when 6
=> correct :=
correct and
s_st_boolean_vector(lowb to highb-1) =
c_st_boolean_vector_2(lowb to highb-1) and
(s_st_boolean_vector_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00389" ,
"One inertial transaction occurred on a " &
"concurrent signal asg",
correct ) ;
st_boolean_vector_select <= transport 6 ;
-- Last transaction above is marked
-- s_st_boolean_vector(lowb to highb-1) <=
-- c_st_boolean_vector_1(lowb to highb-1) after 40 ns ;
--
when 7
=> correct :=
correct and
s_st_boolean_vector(lowb to highb-1) =
c_st_boolean_vector_1(lowb to highb-1) and
(s_st_boolean_vector_savt + 30 ns) = Std.Standard.Now ;
--
when 8
=> correct :=
correct and
s_st_boolean_vector(lowb to highb-1) =
c_st_boolean_vector_1(lowb to highb-1) and
(s_st_boolean_vector_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00389" ,
"Inertial semantics check on a concurrent " &
"signal asg",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00389" ,
"Inertial semantics check on a concurrent " &
"signal asg",
false ) ;
--
end case ;
--
s_st_boolean_vector_savt <= transport Std.Standard.Now ;
chk_st_boolean_vector <= transport s_st_boolean_vector_cnt
after (1 us - Std.Standard.Now) ;
s_st_boolean_vector_cnt <= transport s_st_boolean_vector_cnt + 1 ;
wait until (not s_st_boolean_vector(lowb to highb-1)'Quiet) and
(s_st_boolean_vector_savt /= Std.Standard.Now) ;
--
end process CHG1 ;
--
PGEN_CHKP_1 :
process ( chk_st_boolean_vector )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P1" ,
"Inertial transactions completed entirely",
chk_st_boolean_vector = 8 ) ;
end if ;
end process PGEN_CHKP_1 ;
--
--
with st_boolean_vector_select select
s_st_boolean_vector(lowb to highb-1) <=
c_st_boolean_vector_2(lowb to highb-1) after 10 ns,
c_st_boolean_vector_1(lowb to highb-1) after 20 ns
when 1,
--
c_st_boolean_vector_2(lowb to highb-1) after 10 ns ,
c_st_boolean_vector_1(lowb to highb-1) after 20 ns ,
c_st_boolean_vector_2(lowb to highb-1) after 30 ns ,
c_st_boolean_vector_1(lowb to highb-1) after 40 ns
when 2,
--
c_st_boolean_vector_1(lowb to highb-1) after 5 ns
when 3,
--
c_st_boolean_vector_1(lowb to highb-1) after 100 ns
when 4,
--
c_st_boolean_vector_2(lowb to highb-1) after 10 ns ,
c_st_boolean_vector_1(lowb to highb-1) after 20 ns ,
c_st_boolean_vector_2(lowb to highb-1) after 30 ns ,
c_st_boolean_vector_1(lowb to highb-1) after 40 ns
when 5,
--
-- Last transaction above is marked
c_st_boolean_vector_1(lowb to highb-1) after 40 ns when 6 ;
--
CHG2 :
process
variable correct : boolean ;
begin
case s_st_severity_level_vector_cnt is
when 0
=> null ;
-- s_st_severity_level_vector(lowb to highb-1) <=
-- c_st_severity_level_vector_2(lowb to highb-1) after 10 ns,
-- c_st_severity_level_vector_1(lowb to highb-1) after 20 ns ;
--
when 1
=> correct :=
s_st_severity_level_vector(lowb to highb-1) =
c_st_severity_level_vector_2(lowb to highb-1) and
(s_st_severity_level_vector_savt + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_severity_level_vector(lowb to highb-1) =
c_st_severity_level_vector_1(lowb to highb-1) and
(s_st_severity_level_vector_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00389.P2" ,
"Multi inertial transactions occurred on " &
"concurrent signal asg",
correct ) ;
--
st_severity_level_vector_select <= transport 2 ;
-- s_st_severity_level_vector(lowb to highb-1) <=
-- c_st_severity_level_vector_2(lowb to highb-1) after 10 ns ,
-- c_st_severity_level_vector_1(lowb to highb-1) after 20 ns ,
-- c_st_severity_level_vector_2(lowb to highb-1) after 30 ns ,
-- c_st_severity_level_vector_1(lowb to highb-1) after 40 ns ;
--
when 3
=> correct :=
s_st_severity_level_vector(lowb to highb-1) =
c_st_severity_level_vector_2(lowb to highb-1) and
(s_st_severity_level_vector_savt + 10 ns) = Std.Standard.Now ;
st_severity_level_vector_select <= transport 3 ;
-- s_st_severity_level_vector(lowb to highb-1) <=
-- c_st_severity_level_vector_1(lowb to highb-1) after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_severity_level_vector(lowb to highb-1) =
c_st_severity_level_vector_1(lowb to highb-1) and
(s_st_severity_level_vector_savt + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00389" ,
"One inertial transaction occurred on a " &
"concurrent signal asg",
correct ) ;
st_severity_level_vector_select <= transport 4 ;
-- s_st_severity_level_vector(lowb to highb-1) <=
-- c_st_severity_level_vector_1(lowb to highb-1) after 100 ns ;
--
when 5
=> correct :=
correct and
s_st_severity_level_vector(lowb to highb-1) =
c_st_severity_level_vector_1(lowb to highb-1) and
(s_st_severity_level_vector_savt + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00389" ,
"Old transactions were removed on a " &
"concurrent signal asg",
correct ) ;
st_severity_level_vector_select <= transport 5 ;
-- s_st_severity_level_vector(lowb to highb-1) <=
-- c_st_severity_level_vector_2(lowb to highb-1) after 10 ns ,
-- c_st_severity_level_vector_1(lowb to highb-1) after 20 ns ,
-- c_st_severity_level_vector_2(lowb to highb-1) after 30 ns ,
-- c_st_severity_level_vector_1(lowb to highb-1) after 40 ns ;
--
when 6
=> correct :=
correct and
s_st_severity_level_vector(lowb to highb-1) =
c_st_severity_level_vector_2(lowb to highb-1) and
(s_st_severity_level_vector_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00389" ,
"One inertial transaction occurred on a " &
"concurrent signal asg",
correct ) ;
st_severity_level_vector_select <= transport 6 ;
-- Last transaction above is marked
-- s_st_severity_level_vector(lowb to highb-1) <=
-- c_st_severity_level_vector_1(lowb to highb-1) after 40 ns ;
--
when 7
=> correct :=
correct and
s_st_severity_level_vector(lowb to highb-1) =
c_st_severity_level_vector_1(lowb to highb-1) and
(s_st_severity_level_vector_savt + 30 ns) = Std.Standard.Now ;
--
when 8
=> correct :=
correct and
s_st_severity_level_vector(lowb to highb-1) =
c_st_severity_level_vector_1(lowb to highb-1) and
(s_st_severity_level_vector_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00389" ,
"Inertial semantics check on a concurrent " &
"signal asg",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00389" ,
"Inertial semantics check on a concurrent " &
"signal asg",
false ) ;
--
end case ;
--
s_st_severity_level_vector_savt <= transport Std.Standard.Now ;
chk_st_severity_level_vector <= transport s_st_severity_level_vector_cnt
after (1 us - Std.Standard.Now) ;
s_st_severity_level_vector_cnt <= transport s_st_severity_level_vector_cnt
+ 1 ;
wait until (not s_st_severity_level_vector(lowb to highb-1)'Quiet) and
(s_st_severity_level_vector_savt /= Std.Standard.Now) ;
--
end process CHG2 ;
--
PGEN_CHKP_2 :
process ( chk_st_severity_level_vector )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P2" ,
"Inertial transactions completed entirely",
chk_st_severity_level_vector = 8 ) ;
end if ;
end process PGEN_CHKP_2 ;
--
--
with st_severity_level_vector_select select
s_st_severity_level_vector(lowb to highb-1) <=
c_st_severity_level_vector_2(lowb to highb-1) after 10 ns,
c_st_severity_level_vector_1(lowb to highb-1) after 20 ns
when 1,
--
c_st_severity_level_vector_2(lowb to highb-1) after 10 ns ,
c_st_severity_level_vector_1(lowb to highb-1) after 20 ns ,
c_st_severity_level_vector_2(lowb to highb-1) after 30 ns ,
c_st_severity_level_vector_1(lowb to highb-1) after 40 ns
when 2,
--
c_st_severity_level_vector_1(lowb to highb-1) after 5 ns
when 3,
--
c_st_severity_level_vector_1(lowb to highb-1) after 100 ns
when 4,
--
c_st_severity_level_vector_2(lowb to highb-1) after 10 ns ,
c_st_severity_level_vector_1(lowb to highb-1) after 20 ns ,
c_st_severity_level_vector_2(lowb to highb-1) after 30 ns ,
c_st_severity_level_vector_1(lowb to highb-1) after 40 ns
when 5,
--
-- Last transaction above is marked
c_st_severity_level_vector_1(lowb to highb-1) after 40 ns when 6 ;
--
CHG3 :
process
variable correct : boolean ;
begin
case s_st_string_cnt is
when 0
=> null ;
-- s_st_string(highb-1 to highb-1) <=
-- c_st_string_2(highb-1 to highb-1) after 10 ns,
-- c_st_string_1(highb-1 to highb-1) after 20 ns ;
--
when 1
=> correct :=
s_st_string(highb-1 to highb-1) =
c_st_string_2(highb-1 to highb-1) and
(s_st_string_savt + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_string(highb-1 to highb-1) =
c_st_string_1(highb-1 to highb-1) and
(s_st_string_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00389.P3" ,
"Multi inertial transactions occurred on " &
"concurrent signal asg",
correct ) ;
--
st_string_select <= transport 2 ;
-- s_st_string(highb-1 to highb-1) <=
-- c_st_string_2(highb-1 to highb-1) after 10 ns ,
-- c_st_string_1(highb-1 to highb-1) after 20 ns ,
-- c_st_string_2(highb-1 to highb-1) after 30 ns ,
-- c_st_string_1(highb-1 to highb-1) after 40 ns ;
--
when 3
=> correct :=
s_st_string(highb-1 to highb-1) =
c_st_string_2(highb-1 to highb-1) and
(s_st_string_savt + 10 ns) = Std.Standard.Now ;
st_string_select <= transport 3 ;
-- s_st_string(highb-1 to highb-1) <=
-- c_st_string_1(highb-1 to highb-1) after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_string(highb-1 to highb-1) =
c_st_string_1(highb-1 to highb-1) and
(s_st_string_savt + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00389" ,
"One inertial transaction occurred on a " &
"concurrent signal asg",
correct ) ;
st_string_select <= transport 4 ;
-- s_st_string(highb-1 to highb-1) <=
-- c_st_string_1(highb-1 to highb-1) after 100 ns ;
--
when 5
=> correct :=
correct and
s_st_string(highb-1 to highb-1) =
c_st_string_1(highb-1 to highb-1) and
(s_st_string_savt + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00389" ,
"Old transactions were removed on a " &
"concurrent signal asg",
correct ) ;
st_string_select <= transport 5 ;
-- s_st_string(highb-1 to highb-1) <=
-- c_st_string_2(highb-1 to highb-1) after 10 ns ,
-- c_st_string_1(highb-1 to highb-1) after 20 ns ,
-- c_st_string_2(highb-1 to highb-1) after 30 ns ,
-- c_st_string_1(highb-1 to highb-1) after 40 ns ;
--
when 6
=> correct :=
correct and
s_st_string(highb-1 to highb-1) =
c_st_string_2(highb-1 to highb-1) and
(s_st_string_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00389" ,
"One inertial transaction occurred on a " &
"concurrent signal asg",
correct ) ;
st_string_select <= transport 6 ;
-- Last transaction above is marked
-- s_st_string(highb-1 to highb-1) <=
-- c_st_string_1(highb-1 to highb-1) after 40 ns ;
--
when 7
=> correct :=
correct and
s_st_string(highb-1 to highb-1) =
c_st_string_1(highb-1 to highb-1) and
(s_st_string_savt + 30 ns) = Std.Standard.Now ;
--
when 8
=> correct :=
correct and
s_st_string(highb-1 to highb-1) =
c_st_string_1(highb-1 to highb-1) and
(s_st_string_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00389" ,
"Inertial semantics check on a concurrent " &
"signal asg",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00389" ,
"Inertial semantics check on a concurrent " &
"signal asg",
false ) ;
--
end case ;
--
s_st_string_savt <= transport Std.Standard.Now ;
chk_st_string <= transport s_st_string_cnt
after (1 us - Std.Standard.Now) ;
s_st_string_cnt <= transport s_st_string_cnt + 1 ;
wait until (not s_st_string(highb-1 to highb-1)'Quiet) and
(s_st_string_savt /= Std.Standard.Now) ;
--
end process CHG3 ;
--
PGEN_CHKP_3 :
process ( chk_st_string )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P3" ,
"Inertial transactions completed entirely",
chk_st_string = 8 ) ;
end if ;
end process PGEN_CHKP_3 ;
--
--
with st_string_select select
s_st_string(highb-1 to highb-1) <=
c_st_string_2(highb-1 to highb-1) after 10 ns,
c_st_string_1(highb-1 to highb-1) after 20 ns
when 1,
--
c_st_string_2(highb-1 to highb-1) after 10 ns ,
c_st_string_1(highb-1 to highb-1) after 20 ns ,
c_st_string_2(highb-1 to highb-1) after 30 ns ,
c_st_string_1(highb-1 to highb-1) after 40 ns
when 2,
--
c_st_string_1(highb-1 to highb-1) after 5 ns
when 3,
--
c_st_string_1(highb-1 to highb-1) after 100 ns
when 4,
--
c_st_string_2(highb-1 to highb-1) after 10 ns ,
c_st_string_1(highb-1 to highb-1) after 20 ns ,
c_st_string_2(highb-1 to highb-1) after 30 ns ,
c_st_string_1(highb-1 to highb-1) after 40 ns
when 5,
--
-- Last transaction above is marked
c_st_string_1(highb-1 to highb-1) after 40 ns when 6 ;
--
CHG4 :
process
variable correct : boolean ;
begin
case s_st_enum1_vector_cnt is
when 0
=> null ;
-- s_st_enum1_vector(highb-1 to highb-1) <=
-- c_st_enum1_vector_2(highb-1 to highb-1) after 10 ns,
-- c_st_enum1_vector_1(highb-1 to highb-1) after 20 ns ;
--
when 1
=> correct :=
s_st_enum1_vector(highb-1 to highb-1) =
c_st_enum1_vector_2(highb-1 to highb-1) and
(s_st_enum1_vector_savt + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_enum1_vector(highb-1 to highb-1) =
c_st_enum1_vector_1(highb-1 to highb-1) and
(s_st_enum1_vector_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00389.P4" ,
"Multi inertial transactions occurred on " &
"concurrent signal asg",
correct ) ;
--
st_enum1_vector_select <= transport 2 ;
-- s_st_enum1_vector(highb-1 to highb-1) <=
-- c_st_enum1_vector_2(highb-1 to highb-1) after 10 ns ,
-- c_st_enum1_vector_1(highb-1 to highb-1) after 20 ns ,
-- c_st_enum1_vector_2(highb-1 to highb-1) after 30 ns ,
-- c_st_enum1_vector_1(highb-1 to highb-1) after 40 ns ;
--
when 3
=> correct :=
s_st_enum1_vector(highb-1 to highb-1) =
c_st_enum1_vector_2(highb-1 to highb-1) and
(s_st_enum1_vector_savt + 10 ns) = Std.Standard.Now ;
st_enum1_vector_select <= transport 3 ;
-- s_st_enum1_vector(highb-1 to highb-1) <=
-- c_st_enum1_vector_1(highb-1 to highb-1) after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_enum1_vector(highb-1 to highb-1) =
c_st_enum1_vector_1(highb-1 to highb-1) and
(s_st_enum1_vector_savt + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00389" ,
"One inertial transaction occurred on a " &
"concurrent signal asg",
correct ) ;
st_enum1_vector_select <= transport 4 ;
-- s_st_enum1_vector(highb-1 to highb-1) <=
-- c_st_enum1_vector_1(highb-1 to highb-1) after 100 ns ;
--
when 5
=> correct :=
correct and
s_st_enum1_vector(highb-1 to highb-1) =
c_st_enum1_vector_1(highb-1 to highb-1) and
(s_st_enum1_vector_savt + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00389" ,
"Old transactions were removed on a " &
"concurrent signal asg",
correct ) ;
st_enum1_vector_select <= transport 5 ;
-- s_st_enum1_vector(highb-1 to highb-1) <=
-- c_st_enum1_vector_2(highb-1 to highb-1) after 10 ns ,
-- c_st_enum1_vector_1(highb-1 to highb-1) after 20 ns ,
-- c_st_enum1_vector_2(highb-1 to highb-1) after 30 ns ,
-- c_st_enum1_vector_1(highb-1 to highb-1) after 40 ns ;
--
when 6
=> correct :=
correct and
s_st_enum1_vector(highb-1 to highb-1) =
c_st_enum1_vector_2(highb-1 to highb-1) and
(s_st_enum1_vector_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00389" ,
"One inertial transaction occurred on a " &
"concurrent signal asg",
correct ) ;
st_enum1_vector_select <= transport 6 ;
-- Last transaction above is marked
-- s_st_enum1_vector(highb-1 to highb-1) <=
-- c_st_enum1_vector_1(highb-1 to highb-1) after 40 ns ;
--
when 7
=> correct :=
correct and
s_st_enum1_vector(highb-1 to highb-1) =
c_st_enum1_vector_1(highb-1 to highb-1) and
(s_st_enum1_vector_savt + 30 ns) = Std.Standard.Now ;
--
when 8
=> correct :=
correct and
s_st_enum1_vector(highb-1 to highb-1) =
c_st_enum1_vector_1(highb-1 to highb-1) and
(s_st_enum1_vector_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00389" ,
"Inertial semantics check on a concurrent " &
"signal asg",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00389" ,
"Inertial semantics check on a concurrent " &
"signal asg",
false ) ;
--
end case ;
--
s_st_enum1_vector_savt <= transport Std.Standard.Now ;
chk_st_enum1_vector <= transport s_st_enum1_vector_cnt
after (1 us - Std.Standard.Now) ;
s_st_enum1_vector_cnt <= transport s_st_enum1_vector_cnt + 1 ;
wait until (not s_st_enum1_vector(highb-1 to highb-1)'Quiet) and
(s_st_enum1_vector_savt /= Std.Standard.Now) ;
--
end process CHG4 ;
--
PGEN_CHKP_4 :
process ( chk_st_enum1_vector )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P4" ,
"Inertial transactions completed entirely",
chk_st_enum1_vector = 8 ) ;
end if ;
end process PGEN_CHKP_4 ;
--
--
with st_enum1_vector_select select
s_st_enum1_vector(highb-1 to highb-1) <=
c_st_enum1_vector_2(highb-1 to highb-1) after 10 ns,
c_st_enum1_vector_1(highb-1 to highb-1) after 20 ns
when 1,
--
c_st_enum1_vector_2(highb-1 to highb-1) after 10 ns ,
c_st_enum1_vector_1(highb-1 to highb-1) after 20 ns ,
c_st_enum1_vector_2(highb-1 to highb-1) after 30 ns ,
c_st_enum1_vector_1(highb-1 to highb-1) after 40 ns
when 2,
--
c_st_enum1_vector_1(highb-1 to highb-1) after 5 ns
when 3,
--
c_st_enum1_vector_1(highb-1 to highb-1) after 100 ns
when 4,
--
c_st_enum1_vector_2(highb-1 to highb-1) after 10 ns ,
c_st_enum1_vector_1(highb-1 to highb-1) after 20 ns ,
c_st_enum1_vector_2(highb-1 to highb-1) after 30 ns ,
c_st_enum1_vector_1(highb-1 to highb-1) after 40 ns
when 5,
--
-- Last transaction above is marked
c_st_enum1_vector_1(highb-1 to highb-1) after 40 ns when 6 ;
--
CHG5 :
process
variable correct : boolean ;
begin
case s_st_integer_vector_cnt is
when 0
=> null ;
-- s_st_integer_vector(lowb to highb-1) <=
-- c_st_integer_vector_2(lowb to highb-1) after 10 ns,
-- c_st_integer_vector_1(lowb to highb-1) after 20 ns ;
--
when 1
=> correct :=
s_st_integer_vector(lowb to highb-1) =
c_st_integer_vector_2(lowb to highb-1) and
(s_st_integer_vector_savt + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_integer_vector(lowb to highb-1) =
c_st_integer_vector_1(lowb to highb-1) and
(s_st_integer_vector_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00389.P5" ,
"Multi inertial transactions occurred on " &
"concurrent signal asg",
correct ) ;
--
st_integer_vector_select <= transport 2 ;
-- s_st_integer_vector(lowb to highb-1) <=
-- c_st_integer_vector_2(lowb to highb-1) after 10 ns ,
-- c_st_integer_vector_1(lowb to highb-1) after 20 ns ,
-- c_st_integer_vector_2(lowb to highb-1) after 30 ns ,
-- c_st_integer_vector_1(lowb to highb-1) after 40 ns ;
--
when 3
=> correct :=
s_st_integer_vector(lowb to highb-1) =
c_st_integer_vector_2(lowb to highb-1) and
(s_st_integer_vector_savt + 10 ns) = Std.Standard.Now ;
st_integer_vector_select <= transport 3 ;
-- s_st_integer_vector(lowb to highb-1) <=
-- c_st_integer_vector_1(lowb to highb-1) after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_integer_vector(lowb to highb-1) =
c_st_integer_vector_1(lowb to highb-1) and
(s_st_integer_vector_savt + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00389" ,
"One inertial transaction occurred on a " &
"concurrent signal asg",
correct ) ;
st_integer_vector_select <= transport 4 ;
-- s_st_integer_vector(lowb to highb-1) <=
-- c_st_integer_vector_1(lowb to highb-1) after 100 ns ;
--
when 5
=> correct :=
correct and
s_st_integer_vector(lowb to highb-1) =
c_st_integer_vector_1(lowb to highb-1) and
(s_st_integer_vector_savt + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00389" ,
"Old transactions were removed on a " &
"concurrent signal asg",
correct ) ;
st_integer_vector_select <= transport 5 ;
-- s_st_integer_vector(lowb to highb-1) <=
-- c_st_integer_vector_2(lowb to highb-1) after 10 ns ,
-- c_st_integer_vector_1(lowb to highb-1) after 20 ns ,
-- c_st_integer_vector_2(lowb to highb-1) after 30 ns ,
-- c_st_integer_vector_1(lowb to highb-1) after 40 ns ;
--
when 6
=> correct :=
correct and
s_st_integer_vector(lowb to highb-1) =
c_st_integer_vector_2(lowb to highb-1) and
(s_st_integer_vector_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00389" ,
"One inertial transaction occurred on a " &
"concurrent signal asg",
correct ) ;
st_integer_vector_select <= transport 6 ;
-- Last transaction above is marked
-- s_st_integer_vector(lowb to highb-1) <=
-- c_st_integer_vector_1(lowb to highb-1) after 40 ns ;
--
when 7
=> correct :=
correct and
s_st_integer_vector(lowb to highb-1) =
c_st_integer_vector_1(lowb to highb-1) and
(s_st_integer_vector_savt + 30 ns) = Std.Standard.Now ;
--
when 8
=> correct :=
correct and
s_st_integer_vector(lowb to highb-1) =
c_st_integer_vector_1(lowb to highb-1) and
(s_st_integer_vector_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00389" ,
"Inertial semantics check on a concurrent " &
"signal asg",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00389" ,
"Inertial semantics check on a concurrent " &
"signal asg",
false ) ;
--
end case ;
--
s_st_integer_vector_savt <= transport Std.Standard.Now ;
chk_st_integer_vector <= transport s_st_integer_vector_cnt
after (1 us - Std.Standard.Now) ;
s_st_integer_vector_cnt <= transport s_st_integer_vector_cnt + 1 ;
wait until (not s_st_integer_vector(lowb to highb-1)'Quiet) and
(s_st_integer_vector_savt /= Std.Standard.Now) ;
--
end process CHG5 ;
--
PGEN_CHKP_5 :
process ( chk_st_integer_vector )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P5" ,
"Inertial transactions completed entirely",
chk_st_integer_vector = 8 ) ;
end if ;
end process PGEN_CHKP_5 ;
--
--
with st_integer_vector_select select
s_st_integer_vector(lowb to highb-1) <=
c_st_integer_vector_2(lowb to highb-1) after 10 ns,
c_st_integer_vector_1(lowb to highb-1) after 20 ns
when 1,
--
c_st_integer_vector_2(lowb to highb-1) after 10 ns ,
c_st_integer_vector_1(lowb to highb-1) after 20 ns ,
c_st_integer_vector_2(lowb to highb-1) after 30 ns ,
c_st_integer_vector_1(lowb to highb-1) after 40 ns
when 2,
--
c_st_integer_vector_1(lowb to highb-1) after 5 ns
when 3,
--
c_st_integer_vector_1(lowb to highb-1) after 100 ns
when 4,
--
c_st_integer_vector_2(lowb to highb-1) after 10 ns ,
c_st_integer_vector_1(lowb to highb-1) after 20 ns ,
c_st_integer_vector_2(lowb to highb-1) after 30 ns ,
c_st_integer_vector_1(lowb to highb-1) after 40 ns
when 5,
--
-- Last transaction above is marked
c_st_integer_vector_1(lowb to highb-1) after 40 ns when 6 ;
--
CHG6 :
process
variable correct : boolean ;
begin
case s_st_time_vector_cnt is
when 0
=> null ;
-- s_st_time_vector(lowb to highb-1) <=
-- c_st_time_vector_2(lowb to highb-1) after 10 ns,
-- c_st_time_vector_1(lowb to highb-1) after 20 ns ;
--
when 1
=> correct :=
s_st_time_vector(lowb to highb-1) =
c_st_time_vector_2(lowb to highb-1) and
(s_st_time_vector_savt + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_time_vector(lowb to highb-1) =
c_st_time_vector_1(lowb to highb-1) and
(s_st_time_vector_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00389.P6" ,
"Multi inertial transactions occurred on " &
"concurrent signal asg",
correct ) ;
--
st_time_vector_select <= transport 2 ;
-- s_st_time_vector(lowb to highb-1) <=
-- c_st_time_vector_2(lowb to highb-1) after 10 ns ,
-- c_st_time_vector_1(lowb to highb-1) after 20 ns ,
-- c_st_time_vector_2(lowb to highb-1) after 30 ns ,
-- c_st_time_vector_1(lowb to highb-1) after 40 ns ;
--
when 3
=> correct :=
s_st_time_vector(lowb to highb-1) =
c_st_time_vector_2(lowb to highb-1) and
(s_st_time_vector_savt + 10 ns) = Std.Standard.Now ;
st_time_vector_select <= transport 3 ;
-- s_st_time_vector(lowb to highb-1) <=
-- c_st_time_vector_1(lowb to highb-1) after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_time_vector(lowb to highb-1) =
c_st_time_vector_1(lowb to highb-1) and
(s_st_time_vector_savt + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00389" ,
"One inertial transaction occurred on a " &
"concurrent signal asg",
correct ) ;
st_time_vector_select <= transport 4 ;
-- s_st_time_vector(lowb to highb-1) <=
-- c_st_time_vector_1(lowb to highb-1) after 100 ns ;
--
when 5
=> correct :=
correct and
s_st_time_vector(lowb to highb-1) =
c_st_time_vector_1(lowb to highb-1) and
(s_st_time_vector_savt + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00389" ,
"Old transactions were removed on a " &
"concurrent signal asg",
correct ) ;
st_time_vector_select <= transport 5 ;
-- s_st_time_vector(lowb to highb-1) <=
-- c_st_time_vector_2(lowb to highb-1) after 10 ns ,
-- c_st_time_vector_1(lowb to highb-1) after 20 ns ,
-- c_st_time_vector_2(lowb to highb-1) after 30 ns ,
-- c_st_time_vector_1(lowb to highb-1) after 40 ns ;
--
when 6
=> correct :=
correct and
s_st_time_vector(lowb to highb-1) =
c_st_time_vector_2(lowb to highb-1) and
(s_st_time_vector_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00389" ,
"One inertial transaction occurred on a " &
"concurrent signal asg",
correct ) ;
st_time_vector_select <= transport 6 ;
-- Last transaction above is marked
-- s_st_time_vector(lowb to highb-1) <=
-- c_st_time_vector_1(lowb to highb-1) after 40 ns ;
--
when 7
=> correct :=
correct and
s_st_time_vector(lowb to highb-1) =
c_st_time_vector_1(lowb to highb-1) and
(s_st_time_vector_savt + 30 ns) = Std.Standard.Now ;
--
when 8
=> correct :=
correct and
s_st_time_vector(lowb to highb-1) =
c_st_time_vector_1(lowb to highb-1) and
(s_st_time_vector_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00389" ,
"Inertial semantics check on a concurrent " &
"signal asg",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00389" ,
"Inertial semantics check on a concurrent " &
"signal asg",
false ) ;
--
end case ;
--
s_st_time_vector_savt <= transport Std.Standard.Now ;
chk_st_time_vector <= transport s_st_time_vector_cnt
after (1 us - Std.Standard.Now) ;
s_st_time_vector_cnt <= transport s_st_time_vector_cnt + 1 ;
wait until (not s_st_time_vector(lowb to highb-1)'Quiet) and
(s_st_time_vector_savt /= Std.Standard.Now) ;
--
end process CHG6 ;
--
PGEN_CHKP_6 :
process ( chk_st_time_vector )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P6" ,
"Inertial transactions completed entirely",
chk_st_time_vector = 8 ) ;
end if ;
end process PGEN_CHKP_6 ;
--
--
with st_time_vector_select select
s_st_time_vector(lowb to highb-1) <=
c_st_time_vector_2(lowb to highb-1) after 10 ns,
c_st_time_vector_1(lowb to highb-1) after 20 ns
when 1,
--
c_st_time_vector_2(lowb to highb-1) after 10 ns ,
c_st_time_vector_1(lowb to highb-1) after 20 ns ,
c_st_time_vector_2(lowb to highb-1) after 30 ns ,
c_st_time_vector_1(lowb to highb-1) after 40 ns
when 2,
--
c_st_time_vector_1(lowb to highb-1) after 5 ns
when 3,
--
c_st_time_vector_1(lowb to highb-1) after 100 ns
when 4,
--
c_st_time_vector_2(lowb to highb-1) after 10 ns ,
c_st_time_vector_1(lowb to highb-1) after 20 ns ,
c_st_time_vector_2(lowb to highb-1) after 30 ns ,
c_st_time_vector_1(lowb to highb-1) after 40 ns
when 5,
--
-- Last transaction above is marked
c_st_time_vector_1(lowb to highb-1) after 40 ns when 6 ;
--
CHG7 :
process
variable correct : boolean ;
begin
case s_st_real_vector_cnt is
when 0
=> null ;
-- s_st_real_vector(highb-1 to highb-1) <=
-- c_st_real_vector_2(highb-1 to highb-1) after 10 ns,
-- c_st_real_vector_1(highb-1 to highb-1) after 20 ns ;
--
when 1
=> correct :=
s_st_real_vector(highb-1 to highb-1) =
c_st_real_vector_2(highb-1 to highb-1) and
(s_st_real_vector_savt + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_real_vector(highb-1 to highb-1) =
c_st_real_vector_1(highb-1 to highb-1) and
(s_st_real_vector_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00389.P7" ,
"Multi inertial transactions occurred on " &
"concurrent signal asg",
correct ) ;
--
st_real_vector_select <= transport 2 ;
-- s_st_real_vector(highb-1 to highb-1) <=
-- c_st_real_vector_2(highb-1 to highb-1) after 10 ns ,
-- c_st_real_vector_1(highb-1 to highb-1) after 20 ns ,
-- c_st_real_vector_2(highb-1 to highb-1) after 30 ns ,
-- c_st_real_vector_1(highb-1 to highb-1) after 40 ns ;
--
when 3
=> correct :=
s_st_real_vector(highb-1 to highb-1) =
c_st_real_vector_2(highb-1 to highb-1) and
(s_st_real_vector_savt + 10 ns) = Std.Standard.Now ;
st_real_vector_select <= transport 3 ;
-- s_st_real_vector(highb-1 to highb-1) <=
-- c_st_real_vector_1(highb-1 to highb-1) after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_real_vector(highb-1 to highb-1) =
c_st_real_vector_1(highb-1 to highb-1) and
(s_st_real_vector_savt + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00389" ,
"One inertial transaction occurred on a " &
"concurrent signal asg",
correct ) ;
st_real_vector_select <= transport 4 ;
-- s_st_real_vector(highb-1 to highb-1) <=
-- c_st_real_vector_1(highb-1 to highb-1) after 100 ns ;
--
when 5
=> correct :=
correct and
s_st_real_vector(highb-1 to highb-1) =
c_st_real_vector_1(highb-1 to highb-1) and
(s_st_real_vector_savt + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00389" ,
"Old transactions were removed on a " &
"concurrent signal asg",
correct ) ;
st_real_vector_select <= transport 5 ;
-- s_st_real_vector(highb-1 to highb-1) <=
-- c_st_real_vector_2(highb-1 to highb-1) after 10 ns ,
-- c_st_real_vector_1(highb-1 to highb-1) after 20 ns ,
-- c_st_real_vector_2(highb-1 to highb-1) after 30 ns ,
-- c_st_real_vector_1(highb-1 to highb-1) after 40 ns ;
--
when 6
=> correct :=
correct and
s_st_real_vector(highb-1 to highb-1) =
c_st_real_vector_2(highb-1 to highb-1) and
(s_st_real_vector_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00389" ,
"One inertial transaction occurred on a " &
"concurrent signal asg",
correct ) ;
st_real_vector_select <= transport 6 ;
-- Last transaction above is marked
-- s_st_real_vector(highb-1 to highb-1) <=
-- c_st_real_vector_1(highb-1 to highb-1) after 40 ns ;
--
when 7
=> correct :=
correct and
s_st_real_vector(highb-1 to highb-1) =
c_st_real_vector_1(highb-1 to highb-1) and
(s_st_real_vector_savt + 30 ns) = Std.Standard.Now ;
--
when 8
=> correct :=
correct and
s_st_real_vector(highb-1 to highb-1) =
c_st_real_vector_1(highb-1 to highb-1) and
(s_st_real_vector_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00389" ,
"Inertial semantics check on a concurrent " &
"signal asg",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00389" ,
"Inertial semantics check on a concurrent " &
"signal asg",
false ) ;
--
end case ;
--
s_st_real_vector_savt <= transport Std.Standard.Now ;
chk_st_real_vector <= transport s_st_real_vector_cnt
after (1 us - Std.Standard.Now) ;
s_st_real_vector_cnt <= transport s_st_real_vector_cnt + 1 ;
wait until (not s_st_real_vector(highb-1 to highb-1)'Quiet) and
(s_st_real_vector_savt /= Std.Standard.Now) ;
--
end process CHG7 ;
--
PGEN_CHKP_7 :
process ( chk_st_real_vector )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P7" ,
"Inertial transactions completed entirely",
chk_st_real_vector = 8 ) ;
end if ;
end process PGEN_CHKP_7 ;
--
--
with st_real_vector_select select
s_st_real_vector(highb-1 to highb-1) <=
c_st_real_vector_2(highb-1 to highb-1) after 10 ns,
c_st_real_vector_1(highb-1 to highb-1) after 20 ns
when 1,
--
c_st_real_vector_2(highb-1 to highb-1) after 10 ns ,
c_st_real_vector_1(highb-1 to highb-1) after 20 ns ,
c_st_real_vector_2(highb-1 to highb-1) after 30 ns ,
c_st_real_vector_1(highb-1 to highb-1) after 40 ns
when 2,
--
c_st_real_vector_1(highb-1 to highb-1) after 5 ns
when 3,
--
c_st_real_vector_1(highb-1 to highb-1) after 100 ns
when 4,
--
c_st_real_vector_2(highb-1 to highb-1) after 10 ns ,
c_st_real_vector_1(highb-1 to highb-1) after 20 ns ,
c_st_real_vector_2(highb-1 to highb-1) after 30 ns ,
c_st_real_vector_1(highb-1 to highb-1) after 40 ns
when 5,
--
-- Last transaction above is marked
c_st_real_vector_1(highb-1 to highb-1) after 40 ns when 6 ;
--
CHG8 :
process
variable correct : boolean ;
begin
case s_st_rec1_vector_cnt is
when 0
=> null ;
-- s_st_rec1_vector(highb-1 to highb-1) <=
-- c_st_rec1_vector_2(highb-1 to highb-1) after 10 ns,
-- c_st_rec1_vector_1(highb-1 to highb-1) after 20 ns ;
--
when 1
=> correct :=
s_st_rec1_vector(highb-1 to highb-1) =
c_st_rec1_vector_2(highb-1 to highb-1) and
(s_st_rec1_vector_savt + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_rec1_vector(highb-1 to highb-1) =
c_st_rec1_vector_1(highb-1 to highb-1) and
(s_st_rec1_vector_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00389.P8" ,
"Multi inertial transactions occurred on " &
"concurrent signal asg",
correct ) ;
--
st_rec1_vector_select <= transport 2 ;
-- s_st_rec1_vector(highb-1 to highb-1) <=
-- c_st_rec1_vector_2(highb-1 to highb-1) after 10 ns ,
-- c_st_rec1_vector_1(highb-1 to highb-1) after 20 ns ,
-- c_st_rec1_vector_2(highb-1 to highb-1) after 30 ns ,
-- c_st_rec1_vector_1(highb-1 to highb-1) after 40 ns ;
--
when 3
=> correct :=
s_st_rec1_vector(highb-1 to highb-1) =
c_st_rec1_vector_2(highb-1 to highb-1) and
(s_st_rec1_vector_savt + 10 ns) = Std.Standard.Now ;
st_rec1_vector_select <= transport 3 ;
-- s_st_rec1_vector(highb-1 to highb-1) <=
-- c_st_rec1_vector_1(highb-1 to highb-1) after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_rec1_vector(highb-1 to highb-1) =
c_st_rec1_vector_1(highb-1 to highb-1) and
(s_st_rec1_vector_savt + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00389" ,
"One inertial transaction occurred on a " &
"concurrent signal asg",
correct ) ;
st_rec1_vector_select <= transport 4 ;
-- s_st_rec1_vector(highb-1 to highb-1) <=
-- c_st_rec1_vector_1(highb-1 to highb-1) after 100 ns ;
--
when 5
=> correct :=
correct and
s_st_rec1_vector(highb-1 to highb-1) =
c_st_rec1_vector_1(highb-1 to highb-1) and
(s_st_rec1_vector_savt + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00389" ,
"Old transactions were removed on a " &
"concurrent signal asg",
correct ) ;
st_rec1_vector_select <= transport 5 ;
-- s_st_rec1_vector(highb-1 to highb-1) <=
-- c_st_rec1_vector_2(highb-1 to highb-1) after 10 ns ,
-- c_st_rec1_vector_1(highb-1 to highb-1) after 20 ns ,
-- c_st_rec1_vector_2(highb-1 to highb-1) after 30 ns ,
-- c_st_rec1_vector_1(highb-1 to highb-1) after 40 ns ;
--
when 6
=> correct :=
correct and
s_st_rec1_vector(highb-1 to highb-1) =
c_st_rec1_vector_2(highb-1 to highb-1) and
(s_st_rec1_vector_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00389" ,
"One inertial transaction occurred on a " &
"concurrent signal asg",
correct ) ;
st_rec1_vector_select <= transport 6 ;
-- Last transaction above is marked
-- s_st_rec1_vector(highb-1 to highb-1) <=
-- c_st_rec1_vector_1(highb-1 to highb-1) after 40 ns ;
--
when 7
=> correct :=
correct and
s_st_rec1_vector(highb-1 to highb-1) =
c_st_rec1_vector_1(highb-1 to highb-1) and
(s_st_rec1_vector_savt + 30 ns) = Std.Standard.Now ;
--
when 8
=> correct :=
correct and
s_st_rec1_vector(highb-1 to highb-1) =
c_st_rec1_vector_1(highb-1 to highb-1) and
(s_st_rec1_vector_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00389" ,
"Inertial semantics check on a concurrent " &
"signal asg",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00389" ,
"Inertial semantics check on a concurrent " &
"signal asg",
false ) ;
--
end case ;
--
s_st_rec1_vector_savt <= transport Std.Standard.Now ;
chk_st_rec1_vector <= transport s_st_rec1_vector_cnt
after (1 us - Std.Standard.Now) ;
s_st_rec1_vector_cnt <= transport s_st_rec1_vector_cnt + 1 ;
wait until (not s_st_rec1_vector(highb-1 to highb-1)'Quiet) and
(s_st_rec1_vector_savt /= Std.Standard.Now) ;
--
end process CHG8 ;
--
PGEN_CHKP_8 :
process ( chk_st_rec1_vector )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P8" ,
"Inertial transactions completed entirely",
chk_st_rec1_vector = 8 ) ;
end if ;
end process PGEN_CHKP_8 ;
--
--
with st_rec1_vector_select select
s_st_rec1_vector(highb-1 to highb-1) <=
c_st_rec1_vector_2(highb-1 to highb-1) after 10 ns,
c_st_rec1_vector_1(highb-1 to highb-1) after 20 ns
when 1,
--
c_st_rec1_vector_2(highb-1 to highb-1) after 10 ns ,
c_st_rec1_vector_1(highb-1 to highb-1) after 20 ns ,
c_st_rec1_vector_2(highb-1 to highb-1) after 30 ns ,
c_st_rec1_vector_1(highb-1 to highb-1) after 40 ns
when 2,
--
c_st_rec1_vector_1(highb-1 to highb-1) after 5 ns
when 3,
--
c_st_rec1_vector_1(highb-1 to highb-1) after 100 ns
when 4,
--
c_st_rec1_vector_2(highb-1 to highb-1) after 10 ns ,
c_st_rec1_vector_1(highb-1 to highb-1) after 20 ns ,
c_st_rec1_vector_2(highb-1 to highb-1) after 30 ns ,
c_st_rec1_vector_1(highb-1 to highb-1) after 40 ns
when 5,
--
-- Last transaction above is marked
c_st_rec1_vector_1(highb-1 to highb-1) after 40 ns when 6 ;
--
CHG9 :
process
variable correct : boolean ;
begin
case s_st_arr2_vector_cnt is
when 0
=> null ;
-- s_st_arr2_vector(lowb to highb-1) <=
-- c_st_arr2_vector_2(lowb to highb-1) after 10 ns,
-- c_st_arr2_vector_1(lowb to highb-1) after 20 ns ;
--
when 1
=> correct :=
s_st_arr2_vector(lowb to highb-1) =
c_st_arr2_vector_2(lowb to highb-1) and
(s_st_arr2_vector_savt + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_arr2_vector(lowb to highb-1) =
c_st_arr2_vector_1(lowb to highb-1) and
(s_st_arr2_vector_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00389.P9" ,
"Multi inertial transactions occurred on " &
"concurrent signal asg",
correct ) ;
--
st_arr2_vector_select <= transport 2 ;
-- s_st_arr2_vector(lowb to highb-1) <=
-- c_st_arr2_vector_2(lowb to highb-1) after 10 ns ,
-- c_st_arr2_vector_1(lowb to highb-1) after 20 ns ,
-- c_st_arr2_vector_2(lowb to highb-1) after 30 ns ,
-- c_st_arr2_vector_1(lowb to highb-1) after 40 ns ;
--
when 3
=> correct :=
s_st_arr2_vector(lowb to highb-1) =
c_st_arr2_vector_2(lowb to highb-1) and
(s_st_arr2_vector_savt + 10 ns) = Std.Standard.Now ;
st_arr2_vector_select <= transport 3 ;
-- s_st_arr2_vector(lowb to highb-1) <=
-- c_st_arr2_vector_1(lowb to highb-1) after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_arr2_vector(lowb to highb-1) =
c_st_arr2_vector_1(lowb to highb-1) and
(s_st_arr2_vector_savt + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00389" ,
"One inertial transaction occurred on a " &
"concurrent signal asg",
correct ) ;
st_arr2_vector_select <= transport 4 ;
-- s_st_arr2_vector(lowb to highb-1) <=
-- c_st_arr2_vector_1(lowb to highb-1) after 100 ns ;
--
when 5
=> correct :=
correct and
s_st_arr2_vector(lowb to highb-1) =
c_st_arr2_vector_1(lowb to highb-1) and
(s_st_arr2_vector_savt + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00389" ,
"Old transactions were removed on a " &
"concurrent signal asg",
correct ) ;
st_arr2_vector_select <= transport 5 ;
-- s_st_arr2_vector(lowb to highb-1) <=
-- c_st_arr2_vector_2(lowb to highb-1) after 10 ns ,
-- c_st_arr2_vector_1(lowb to highb-1) after 20 ns ,
-- c_st_arr2_vector_2(lowb to highb-1) after 30 ns ,
-- c_st_arr2_vector_1(lowb to highb-1) after 40 ns ;
--
when 6
=> correct :=
correct and
s_st_arr2_vector(lowb to highb-1) =
c_st_arr2_vector_2(lowb to highb-1) and
(s_st_arr2_vector_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00389" ,
"One inertial transaction occurred on a " &
"concurrent signal asg",
correct ) ;
st_arr2_vector_select <= transport 6 ;
-- Last transaction above is marked
-- s_st_arr2_vector(lowb to highb-1) <=
-- c_st_arr2_vector_1(lowb to highb-1) after 40 ns ;
--
when 7
=> correct :=
correct and
s_st_arr2_vector(lowb to highb-1) =
c_st_arr2_vector_1(lowb to highb-1) and
(s_st_arr2_vector_savt + 30 ns) = Std.Standard.Now ;
--
when 8
=> correct :=
correct and
s_st_arr2_vector(lowb to highb-1) =
c_st_arr2_vector_1(lowb to highb-1) and
(s_st_arr2_vector_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00389" ,
"Inertial semantics check on a concurrent " &
"signal asg",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00389" ,
"Inertial semantics check on a concurrent " &
"signal asg",
false ) ;
--
end case ;
--
s_st_arr2_vector_savt <= transport Std.Standard.Now ;
chk_st_arr2_vector <= transport s_st_arr2_vector_cnt
after (1 us - Std.Standard.Now) ;
s_st_arr2_vector_cnt <= transport s_st_arr2_vector_cnt + 1 ;
wait until (not s_st_arr2_vector(lowb to highb-1)'Quiet) and
(s_st_arr2_vector_savt /= Std.Standard.Now) ;
--
end process CHG9 ;
--
PGEN_CHKP_9 :
process ( chk_st_arr2_vector )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P9" ,
"Inertial transactions completed entirely",
chk_st_arr2_vector = 8 ) ;
end if ;
end process PGEN_CHKP_9 ;
--
--
with st_arr2_vector_select select
s_st_arr2_vector(lowb to highb-1) <=
c_st_arr2_vector_2(lowb to highb-1) after 10 ns,
c_st_arr2_vector_1(lowb to highb-1) after 20 ns
when 1,
--
c_st_arr2_vector_2(lowb to highb-1) after 10 ns ,
c_st_arr2_vector_1(lowb to highb-1) after 20 ns ,
c_st_arr2_vector_2(lowb to highb-1) after 30 ns ,
c_st_arr2_vector_1(lowb to highb-1) after 40 ns
when 2,
--
c_st_arr2_vector_1(lowb to highb-1) after 5 ns
when 3,
--
c_st_arr2_vector_1(lowb to highb-1) after 100 ns
when 4,
--
c_st_arr2_vector_2(lowb to highb-1) after 10 ns ,
c_st_arr2_vector_1(lowb to highb-1) after 20 ns ,
c_st_arr2_vector_2(lowb to highb-1) after 30 ns ,
c_st_arr2_vector_1(lowb to highb-1) after 40 ns
when 5,
--
-- Last transaction above is marked
c_st_arr2_vector_1(lowb to highb-1) after 40 ns when 6 ;
--
end ARCH00389 ;
--
--
use WORK.STANDARD_TYPES.all ;
entity ENT00389_Test_Bench is
end ENT00389_Test_Bench ;
--
--
architecture ARCH00389_Test_Bench of ENT00389_Test_Bench is
begin
L1:
block
component UUT
end component ;
--
for CIS1 : UUT use entity WORK.ENT00389 ( ARCH00389 ) ;
begin
CIS1 : UUT
;
end block L1 ;
end ARCH00389_Test_Bench ;
| gpl-3.0 | c0bf359cdf17cb220366a81707c0cbca | 0.527654 | 3.401624 | false | false | false | false |
grwlf/vsim | vhdl_ct/ct00315.vhd | 1 | 3,863 | -- NEED RESULT: ARCH00315: Process with Sens List and End Label passed
-- NEED RESULT: ARCH00315: Process has no process declarative items in itsdeclarative part passed
-- NEED RESULT: ARCH00315: Process with Sens List and No End Label passed
-- NEED RESULT: ARCH00315: Process has no process declarative items in itsdeclarative part passed
-- NEED RESULT: ARCH00315: Process with No Sens List and End Label passed
-- NEED RESULT: ARCH00315: Process has no process declarative items in itsdeclarative part passed
-- NEED RESULT: ARCH00315: Process with No Sens List and No End Label passed
-- NEED RESULT: ARCH00315: Process has no process declarative items in itsdeclarative part passed
-- NEED RESULT: ARCH00315: Test completed successfully passed
-------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
-------------------------------------------------------------------------------
--
-- TEST NAME:
--
-- CT00315
--
-- AUTHOR:
--
-- G. Tominovich
--
-- TEST OBJECTIVES:
--
-- 9.2 (1)
-- 9.2 (2)
-- 9.2 (4)
--
-- DESIGN UNIT ORDERING:
--
-- E00000(ARCH00315)
-- ENT00315_Test_Bench(ARCH00315_Test_Bench)
--
-- REVISION HISTORY:
--
-- 29-JUL-1987 - initial revision
--
-- NOTES:
--
-- self-checking
--
--
use WORK.STANDARD_TYPES.all ;
architecture ARCH00315 of E00000 is
signal s1, s2 : boolean := True ;
signal chk1, chk2, chk3, chk4, Complete : boolean := False ;
begin
P1 : -- Sensitivity List and End Label
process ( s1 )
begin
test_report ( "ARCH00315" ,
"Process with Sens List and End Label" ,
True ) ;
test_report ( "ARCH00315" ,
"Process has no process declarative items in its" &
"declarative part" ,
True ) ;
chk1 <= transport True ;
end process P1 ;
P2 : -- Sensitivity List and No End Label
process ( s2 )
begin
test_report ( "ARCH00315" ,
"Process with Sens List and No End Label" ,
True ) ;
test_report ( "ARCH00315" ,
"Process has no process declarative items in its" &
"declarative part" ,
True ) ;
chk2 <= transport True ;
end process ;
P3 : -- No Sensitivity List and End Label
process
begin
test_report ( "ARCH00315" ,
"Process with No Sens List and End Label" ,
True ) ;
test_report ( "ARCH00315" ,
"Process has no process declarative items in its" &
"declarative part" ,
True ) ;
chk3 <= transport True ;
wait ;
end process P3 ;
P4 : -- No Sensitivity List and No End Label
process
begin
test_report ( "ARCH00315" ,
"Process with No Sens List and No End Label" ,
True ) ;
test_report ( "ARCH00315" ,
"Process has no process declarative items in its" &
"declarative part" ,
True ) ;
chk4 <= transport True ;
wait ;
end process ;
complete <= transport True after 100 ns ;
Completion_Test :
process ( complete )
variable First_Time : boolean := True ;
begin
if First_Time then
First_Time := False ;
else
test_report ( "ARCH00315" ,
"Test completed successfully" ,
(chk1 and chk2 and chk3 and chk4) ) ;
end if ;
end process Completion_Test ;
end ARCH00315 ;
entity ENT00315_Test_Bench is
end ENT00315_Test_Bench ;
architecture ARCH00315_Test_Bench of ENT00315_Test_Bench is
begin
L1:
block
component UUT
end component ;
for CIS1 : UUT use entity WORK.E00000 ( ARCH00315 ) ;
begin
CIS1 : UUT ;
end block L1 ;
end ARCH00315_Test_Bench ;
| gpl-3.0 | 69afa51259f9f938b80bc4f89afe6d47 | 0.574683 | 3.83996 | false | true | false | false |
jairov4/accel-oil | impl/impl_test_pcie/hdl/elaborate/lmb_bram_elaborate_v1_00_a/hdl/vhdl/lmb_bram_elaborate.vhd | 1 | 4,691 | -------------------------------------------------------------------------------
-- lmb_bram_elaborate.vhd
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity lmb_bram_elaborate is
generic (
C_MEMSIZE : integer;
C_PORT_DWIDTH : integer;
C_PORT_AWIDTH : integer;
C_NUM_WE : integer;
C_FAMILY : string
);
port (
BRAM_Rst_A : in std_logic;
BRAM_Clk_A : in std_logic;
BRAM_EN_A : in std_logic;
BRAM_WEN_A : in std_logic_vector(0 to C_NUM_WE-1);
BRAM_Addr_A : in std_logic_vector(0 to C_PORT_AWIDTH-1);
BRAM_Din_A : out std_logic_vector(0 to C_PORT_DWIDTH-1);
BRAM_Dout_A : in std_logic_vector(0 to C_PORT_DWIDTH-1);
BRAM_Rst_B : in std_logic;
BRAM_Clk_B : in std_logic;
BRAM_EN_B : in std_logic;
BRAM_WEN_B : in std_logic_vector(0 to C_NUM_WE-1);
BRAM_Addr_B : in std_logic_vector(0 to C_PORT_AWIDTH-1);
BRAM_Din_B : out std_logic_vector(0 to C_PORT_DWIDTH-1);
BRAM_Dout_B : in std_logic_vector(0 to C_PORT_DWIDTH-1)
);
attribute keep_hierarchy : STRING;
attribute keep_hierarchy of lmb_bram_elaborate : entity is "yes";
end lmb_bram_elaborate;
architecture STRUCTURE of lmb_bram_elaborate is
component RAMB36 is
generic (
WRITE_MODE_A : string;
WRITE_MODE_B : string;
INIT_FILE : string;
READ_WIDTH_A : integer;
READ_WIDTH_B : integer;
WRITE_WIDTH_A : integer;
WRITE_WIDTH_B : integer;
RAM_EXTENSION_A : string;
RAM_EXTENSION_B : string
);
port (
ADDRA : in std_logic_vector(15 downto 0);
CASCADEINLATA : in std_logic;
CASCADEINREGA : in std_logic;
CASCADEOUTLATA : out std_logic;
CASCADEOUTREGA : out std_logic;
CLKA : in std_logic;
DIA : in std_logic_vector(31 downto 0);
DIPA : in std_logic_vector(3 downto 0);
DOA : out std_logic_vector(31 downto 0);
DOPA : out std_logic_vector(3 downto 0);
ENA : in std_logic;
REGCEA : in std_logic;
SSRA : in std_logic;
WEA : in std_logic_vector(3 downto 0);
ADDRB : in std_logic_vector(15 downto 0);
CASCADEINLATB : in std_logic;
CASCADEINREGB : in std_logic;
CASCADEOUTLATB : out std_logic;
CASCADEOUTREGB : out std_logic;
CLKB : in std_logic;
DIB : in std_logic_vector(31 downto 0);
DIPB : in std_logic_vector(3 downto 0);
DOB : out std_logic_vector(31 downto 0);
DOPB : out std_logic_vector(3 downto 0);
ENB : in std_logic;
REGCEB : in std_logic;
SSRB : in std_logic;
WEB : in std_logic_vector(3 downto 0)
);
end component;
attribute BMM_INFO : STRING;
attribute BMM_INFO of ramb36_0: label is " ";
-- Internal signals
signal net_gnd0 : std_logic;
signal net_gnd4 : std_logic_vector(3 downto 0);
signal pgassign1 : std_logic_vector(0 to 0);
signal pgassign2 : std_logic_vector(0 to 4);
signal pgassign3 : std_logic_vector(15 downto 0);
signal pgassign4 : std_logic_vector(15 downto 0);
begin
-- Internal assignments
pgassign1(0 to 0) <= B"1";
pgassign2(0 to 4) <= B"00000";
pgassign3(15 downto 15) <= B"1";
pgassign3(14 downto 5) <= BRAM_Addr_A(20 to 29);
pgassign3(4 downto 0) <= B"00000";
pgassign4(15 downto 15) <= B"1";
pgassign4(14 downto 5) <= BRAM_Addr_B(20 to 29);
pgassign4(4 downto 0) <= B"00000";
net_gnd0 <= '0';
net_gnd4(3 downto 0) <= B"0000";
ramb36_0 : RAMB36
generic map (
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
INIT_FILE => "lmb_bram_combined_0.mem",
READ_WIDTH_A => 36,
READ_WIDTH_B => 36,
WRITE_WIDTH_A => 36,
WRITE_WIDTH_B => 36,
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE"
)
port map (
ADDRA => pgassign3,
CASCADEINLATA => net_gnd0,
CASCADEINREGA => net_gnd0,
CASCADEOUTLATA => open,
CASCADEOUTREGA => open,
CLKA => BRAM_Clk_A,
DIA => BRAM_Dout_A(0 to 31),
DIPA => net_gnd4,
DOA => BRAM_Din_A(0 to 31),
DOPA => open,
ENA => BRAM_EN_A,
REGCEA => net_gnd0,
SSRA => BRAM_Rst_A,
WEA => BRAM_WEN_A(0 to 3),
ADDRB => pgassign4,
CASCADEINLATB => net_gnd0,
CASCADEINREGB => net_gnd0,
CASCADEOUTLATB => open,
CASCADEOUTREGB => open,
CLKB => BRAM_Clk_B,
DIB => BRAM_Dout_B(0 to 31),
DIPB => net_gnd4,
DOB => BRAM_Din_B(0 to 31),
DOPB => open,
ENB => BRAM_EN_B,
REGCEB => net_gnd0,
SSRB => BRAM_Rst_B,
WEB => BRAM_WEN_B(0 to 3)
);
end architecture STRUCTURE;
| lgpl-3.0 | a582d2fdc5d57ed668c85adb159fe811 | 0.578768 | 3.29193 | false | false | false | false |
jairov4/accel-oil | solution_spartan3/syn/vhdl/sample_iterator_get_offset.vhd | 1 | 48,361 | -- ==============================================================
-- RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2013.4
-- Copyright (C) 2013 Xilinx Inc. All rights reserved.
--
-- ===========================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity sample_iterator_get_offset is
port (
ap_clk : IN STD_LOGIC;
ap_rst : IN STD_LOGIC;
ap_start : IN STD_LOGIC;
ap_done : OUT STD_LOGIC;
ap_idle : OUT STD_LOGIC;
ap_ready : OUT STD_LOGIC;
indices_stride_req_din : OUT STD_LOGIC;
indices_stride_req_full_n : IN STD_LOGIC;
indices_stride_req_write : OUT STD_LOGIC;
indices_stride_rsp_empty_n : IN STD_LOGIC;
indices_stride_rsp_read : OUT STD_LOGIC;
indices_stride_address : OUT STD_LOGIC_VECTOR (31 downto 0);
indices_stride_datain : IN STD_LOGIC_VECTOR (7 downto 0);
indices_stride_dataout : OUT STD_LOGIC_VECTOR (7 downto 0);
indices_stride_size : OUT STD_LOGIC_VECTOR (31 downto 0);
indices_begin_req_din : OUT STD_LOGIC;
indices_begin_req_full_n : IN STD_LOGIC;
indices_begin_req_write : OUT STD_LOGIC;
indices_begin_rsp_empty_n : IN STD_LOGIC;
indices_begin_rsp_read : OUT STD_LOGIC;
indices_begin_address : OUT STD_LOGIC_VECTOR (31 downto 0);
indices_begin_datain : IN STD_LOGIC_VECTOR (31 downto 0);
indices_begin_dataout : OUT STD_LOGIC_VECTOR (31 downto 0);
indices_begin_size : OUT STD_LOGIC_VECTOR (31 downto 0);
ap_ce : IN STD_LOGIC;
i_index : IN STD_LOGIC_VECTOR (15 downto 0);
i_sample : IN STD_LOGIC_VECTOR (15 downto 0);
indices_samples_req_din : OUT STD_LOGIC;
indices_samples_req_full_n : IN STD_LOGIC;
indices_samples_req_write : OUT STD_LOGIC;
indices_samples_rsp_empty_n : IN STD_LOGIC;
indices_samples_rsp_read : OUT STD_LOGIC;
indices_samples_address : OUT STD_LOGIC_VECTOR (31 downto 0);
indices_samples_datain : IN STD_LOGIC_VECTOR (15 downto 0);
indices_samples_dataout : OUT STD_LOGIC_VECTOR (15 downto 0);
indices_samples_size : OUT STD_LOGIC_VECTOR (31 downto 0);
sample_buffer_size : IN STD_LOGIC_VECTOR (31 downto 0);
sample_length : IN STD_LOGIC_VECTOR (15 downto 0);
ap_return : OUT STD_LOGIC_VECTOR (31 downto 0) );
end;
architecture behav of sample_iterator_get_offset is
constant ap_const_logic_1 : STD_LOGIC := '1';
constant ap_const_logic_0 : STD_LOGIC := '0';
constant ap_ST_pp0_stg0_fsm_0 : STD_LOGIC_VECTOR (0 downto 0) := "0";
constant ap_const_lv32_0 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000000";
constant ap_const_lv32_1 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000001";
constant ap_const_lv8_0 : STD_LOGIC_VECTOR (7 downto 0) := "00000000";
constant ap_const_lv16_0 : STD_LOGIC_VECTOR (15 downto 0) := "0000000000000000";
signal ap_CS_fsm : STD_LOGIC_VECTOR (0 downto 0) := "0";
signal ap_reg_ppiten_pp0_it0 : STD_LOGIC;
signal ap_reg_ppiten_pp0_it1 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it2 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it3 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it4 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it5 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it6 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it7 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it8 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it9 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it10 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it11 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it12 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it13 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it14 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it15 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it16 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it17 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it18 : STD_LOGIC := '0';
signal i_sample_read_reg_130 : STD_LOGIC_VECTOR (15 downto 0);
signal ap_reg_ppstg_i_sample_read_reg_130_pp0_it1 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_fu_93_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_reg_135 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_tmp_reg_135_pp0_it1 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_tmp_reg_135_pp0_it2 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_tmp_reg_135_pp0_it3 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_tmp_reg_135_pp0_it4 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_tmp_reg_135_pp0_it5 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_tmp_reg_135_pp0_it6 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_tmp_reg_135_pp0_it7 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_tmp_reg_135_pp0_it8 : STD_LOGIC_VECTOR (31 downto 0);
signal indices_stride_addr_read_reg_145 : STD_LOGIC_VECTOR (7 downto 0);
signal indices_begin_addr_read_reg_165 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_110_p2 : STD_LOGIC_VECTOR (23 downto 0);
signal tmp_7_reg_170 : STD_LOGIC_VECTOR (23 downto 0);
signal grp_fu_110_p0 : STD_LOGIC_VECTOR (15 downto 0);
signal grp_fu_110_p1 : STD_LOGIC_VECTOR (7 downto 0);
signal grp_fu_125_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_125_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_110_ce : STD_LOGIC;
signal grp_fu_125_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_125_ce : STD_LOGIC;
signal ap_NS_fsm : STD_LOGIC_VECTOR (0 downto 0);
signal ap_sig_pprstidle_pp0 : STD_LOGIC;
signal grp_fu_110_p00 : STD_LOGIC_VECTOR (23 downto 0);
signal grp_fu_110_p10 : STD_LOGIC_VECTOR (23 downto 0);
component nfa_accept_samples_generic_hw_mul_16ns_8ns_24_9 IS
generic (
ID : INTEGER;
NUM_STAGE : INTEGER;
din0_WIDTH : INTEGER;
din1_WIDTH : INTEGER;
dout_WIDTH : INTEGER );
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
din0 : IN STD_LOGIC_VECTOR (15 downto 0);
din1 : IN STD_LOGIC_VECTOR (7 downto 0);
ce : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR (23 downto 0) );
end component;
component nfa_accept_samples_generic_hw_add_32ns_32ns_32_8 IS
generic (
ID : INTEGER;
NUM_STAGE : INTEGER;
din0_WIDTH : INTEGER;
din1_WIDTH : INTEGER;
dout_WIDTH : INTEGER );
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
din0 : IN STD_LOGIC_VECTOR (31 downto 0);
din1 : IN STD_LOGIC_VECTOR (31 downto 0);
ce : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR (31 downto 0) );
end component;
begin
nfa_accept_samples_generic_hw_mul_16ns_8ns_24_9_U0 : component nfa_accept_samples_generic_hw_mul_16ns_8ns_24_9
generic map (
ID => 0,
NUM_STAGE => 9,
din0_WIDTH => 16,
din1_WIDTH => 8,
dout_WIDTH => 24)
port map (
clk => ap_clk,
reset => ap_rst,
din0 => grp_fu_110_p0,
din1 => grp_fu_110_p1,
ce => grp_fu_110_ce,
dout => grp_fu_110_p2);
nfa_accept_samples_generic_hw_add_32ns_32ns_32_8_U1 : component nfa_accept_samples_generic_hw_add_32ns_32ns_32_8
generic map (
ID => 1,
NUM_STAGE => 8,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst,
din0 => grp_fu_125_p0,
din1 => grp_fu_125_p1,
ce => grp_fu_125_ce,
dout => grp_fu_125_p2);
-- the current state (ap_CS_fsm) of the state machine. --
ap_CS_fsm_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_CS_fsm <= ap_ST_pp0_stg0_fsm_0;
else
ap_CS_fsm <= ap_NS_fsm;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it1 assign process. --
ap_reg_ppiten_pp0_it1_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_reg_ppiten_pp0_it1 <= ap_const_logic_0;
else
if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and (indices_stride_rsp_empty_n = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it10) and (indices_begin_rsp_empty_n = ap_const_logic_0)) or not((ap_const_logic_1 = ap_ce)))))) then
ap_reg_ppiten_pp0_it1 <= ap_reg_ppiten_pp0_it0;
end if;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it10 assign process. --
ap_reg_ppiten_pp0_it10_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_reg_ppiten_pp0_it10 <= ap_const_logic_0;
else
if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and (indices_stride_rsp_empty_n = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it10) and (indices_begin_rsp_empty_n = ap_const_logic_0)) or not((ap_const_logic_1 = ap_ce)))))) then
ap_reg_ppiten_pp0_it10 <= ap_reg_ppiten_pp0_it9;
end if;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it11 assign process. --
ap_reg_ppiten_pp0_it11_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_reg_ppiten_pp0_it11 <= ap_const_logic_0;
else
if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and (indices_stride_rsp_empty_n = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it10) and (indices_begin_rsp_empty_n = ap_const_logic_0)) or not((ap_const_logic_1 = ap_ce)))))) then
ap_reg_ppiten_pp0_it11 <= ap_reg_ppiten_pp0_it10;
end if;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it12 assign process. --
ap_reg_ppiten_pp0_it12_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_reg_ppiten_pp0_it12 <= ap_const_logic_0;
else
if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and (indices_stride_rsp_empty_n = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it10) and (indices_begin_rsp_empty_n = ap_const_logic_0)) or not((ap_const_logic_1 = ap_ce)))))) then
ap_reg_ppiten_pp0_it12 <= ap_reg_ppiten_pp0_it11;
end if;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it13 assign process. --
ap_reg_ppiten_pp0_it13_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_reg_ppiten_pp0_it13 <= ap_const_logic_0;
else
if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and (indices_stride_rsp_empty_n = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it10) and (indices_begin_rsp_empty_n = ap_const_logic_0)) or not((ap_const_logic_1 = ap_ce)))))) then
ap_reg_ppiten_pp0_it13 <= ap_reg_ppiten_pp0_it12;
end if;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it14 assign process. --
ap_reg_ppiten_pp0_it14_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_reg_ppiten_pp0_it14 <= ap_const_logic_0;
else
if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and (indices_stride_rsp_empty_n = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it10) and (indices_begin_rsp_empty_n = ap_const_logic_0)) or not((ap_const_logic_1 = ap_ce)))))) then
ap_reg_ppiten_pp0_it14 <= ap_reg_ppiten_pp0_it13;
end if;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it15 assign process. --
ap_reg_ppiten_pp0_it15_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_reg_ppiten_pp0_it15 <= ap_const_logic_0;
else
if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and (indices_stride_rsp_empty_n = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it10) and (indices_begin_rsp_empty_n = ap_const_logic_0)) or not((ap_const_logic_1 = ap_ce)))))) then
ap_reg_ppiten_pp0_it15 <= ap_reg_ppiten_pp0_it14;
end if;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it16 assign process. --
ap_reg_ppiten_pp0_it16_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_reg_ppiten_pp0_it16 <= ap_const_logic_0;
else
if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and (indices_stride_rsp_empty_n = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it10) and (indices_begin_rsp_empty_n = ap_const_logic_0)) or not((ap_const_logic_1 = ap_ce)))))) then
ap_reg_ppiten_pp0_it16 <= ap_reg_ppiten_pp0_it15;
end if;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it17 assign process. --
ap_reg_ppiten_pp0_it17_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_reg_ppiten_pp0_it17 <= ap_const_logic_0;
else
if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and (indices_stride_rsp_empty_n = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it10) and (indices_begin_rsp_empty_n = ap_const_logic_0)) or not((ap_const_logic_1 = ap_ce)))))) then
ap_reg_ppiten_pp0_it17 <= ap_reg_ppiten_pp0_it16;
end if;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it18 assign process. --
ap_reg_ppiten_pp0_it18_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_reg_ppiten_pp0_it18 <= ap_const_logic_0;
else
if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and (indices_stride_rsp_empty_n = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it10) and (indices_begin_rsp_empty_n = ap_const_logic_0)) or not((ap_const_logic_1 = ap_ce)))))) then
ap_reg_ppiten_pp0_it18 <= ap_reg_ppiten_pp0_it17;
end if;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it2 assign process. --
ap_reg_ppiten_pp0_it2_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_reg_ppiten_pp0_it2 <= ap_const_logic_0;
else
if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and (indices_stride_rsp_empty_n = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it10) and (indices_begin_rsp_empty_n = ap_const_logic_0)) or not((ap_const_logic_1 = ap_ce)))))) then
ap_reg_ppiten_pp0_it2 <= ap_reg_ppiten_pp0_it1;
end if;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it3 assign process. --
ap_reg_ppiten_pp0_it3_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_reg_ppiten_pp0_it3 <= ap_const_logic_0;
else
if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and (indices_stride_rsp_empty_n = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it10) and (indices_begin_rsp_empty_n = ap_const_logic_0)) or not((ap_const_logic_1 = ap_ce)))))) then
ap_reg_ppiten_pp0_it3 <= ap_reg_ppiten_pp0_it2;
end if;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it4 assign process. --
ap_reg_ppiten_pp0_it4_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_reg_ppiten_pp0_it4 <= ap_const_logic_0;
else
if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and (indices_stride_rsp_empty_n = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it10) and (indices_begin_rsp_empty_n = ap_const_logic_0)) or not((ap_const_logic_1 = ap_ce)))))) then
ap_reg_ppiten_pp0_it4 <= ap_reg_ppiten_pp0_it3;
end if;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it5 assign process. --
ap_reg_ppiten_pp0_it5_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_reg_ppiten_pp0_it5 <= ap_const_logic_0;
else
if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and (indices_stride_rsp_empty_n = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it10) and (indices_begin_rsp_empty_n = ap_const_logic_0)) or not((ap_const_logic_1 = ap_ce)))))) then
ap_reg_ppiten_pp0_it5 <= ap_reg_ppiten_pp0_it4;
end if;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it6 assign process. --
ap_reg_ppiten_pp0_it6_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_reg_ppiten_pp0_it6 <= ap_const_logic_0;
else
if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and (indices_stride_rsp_empty_n = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it10) and (indices_begin_rsp_empty_n = ap_const_logic_0)) or not((ap_const_logic_1 = ap_ce)))))) then
ap_reg_ppiten_pp0_it6 <= ap_reg_ppiten_pp0_it5;
end if;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it7 assign process. --
ap_reg_ppiten_pp0_it7_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_reg_ppiten_pp0_it7 <= ap_const_logic_0;
else
if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and (indices_stride_rsp_empty_n = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it10) and (indices_begin_rsp_empty_n = ap_const_logic_0)) or not((ap_const_logic_1 = ap_ce)))))) then
ap_reg_ppiten_pp0_it7 <= ap_reg_ppiten_pp0_it6;
end if;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it8 assign process. --
ap_reg_ppiten_pp0_it8_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_reg_ppiten_pp0_it8 <= ap_const_logic_0;
else
if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and (indices_stride_rsp_empty_n = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it10) and (indices_begin_rsp_empty_n = ap_const_logic_0)) or not((ap_const_logic_1 = ap_ce)))))) then
ap_reg_ppiten_pp0_it8 <= ap_reg_ppiten_pp0_it7;
end if;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it9 assign process. --
ap_reg_ppiten_pp0_it9_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_reg_ppiten_pp0_it9 <= ap_const_logic_0;
else
if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and (indices_stride_rsp_empty_n = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it10) and (indices_begin_rsp_empty_n = ap_const_logic_0)) or not((ap_const_logic_1 = ap_ce)))))) then
ap_reg_ppiten_pp0_it9 <= ap_reg_ppiten_pp0_it8;
end if;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and (indices_stride_rsp_empty_n = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it10) and (indices_begin_rsp_empty_n = ap_const_logic_0)))) and (ap_const_logic_1 = ap_ce))) then
ap_reg_ppstg_i_sample_read_reg_130_pp0_it1 <= i_sample_read_reg_130;
ap_reg_ppstg_tmp_reg_135_pp0_it1(0) <= tmp_reg_135(0);
ap_reg_ppstg_tmp_reg_135_pp0_it1(1) <= tmp_reg_135(1);
ap_reg_ppstg_tmp_reg_135_pp0_it1(2) <= tmp_reg_135(2);
ap_reg_ppstg_tmp_reg_135_pp0_it1(3) <= tmp_reg_135(3);
ap_reg_ppstg_tmp_reg_135_pp0_it1(4) <= tmp_reg_135(4);
ap_reg_ppstg_tmp_reg_135_pp0_it1(5) <= tmp_reg_135(5);
ap_reg_ppstg_tmp_reg_135_pp0_it1(6) <= tmp_reg_135(6);
ap_reg_ppstg_tmp_reg_135_pp0_it1(7) <= tmp_reg_135(7);
ap_reg_ppstg_tmp_reg_135_pp0_it1(8) <= tmp_reg_135(8);
ap_reg_ppstg_tmp_reg_135_pp0_it1(9) <= tmp_reg_135(9);
ap_reg_ppstg_tmp_reg_135_pp0_it1(10) <= tmp_reg_135(10);
ap_reg_ppstg_tmp_reg_135_pp0_it1(11) <= tmp_reg_135(11);
ap_reg_ppstg_tmp_reg_135_pp0_it1(12) <= tmp_reg_135(12);
ap_reg_ppstg_tmp_reg_135_pp0_it1(13) <= tmp_reg_135(13);
ap_reg_ppstg_tmp_reg_135_pp0_it1(14) <= tmp_reg_135(14);
ap_reg_ppstg_tmp_reg_135_pp0_it1(15) <= tmp_reg_135(15);
ap_reg_ppstg_tmp_reg_135_pp0_it2(0) <= ap_reg_ppstg_tmp_reg_135_pp0_it1(0);
ap_reg_ppstg_tmp_reg_135_pp0_it2(1) <= ap_reg_ppstg_tmp_reg_135_pp0_it1(1);
ap_reg_ppstg_tmp_reg_135_pp0_it2(2) <= ap_reg_ppstg_tmp_reg_135_pp0_it1(2);
ap_reg_ppstg_tmp_reg_135_pp0_it2(3) <= ap_reg_ppstg_tmp_reg_135_pp0_it1(3);
ap_reg_ppstg_tmp_reg_135_pp0_it2(4) <= ap_reg_ppstg_tmp_reg_135_pp0_it1(4);
ap_reg_ppstg_tmp_reg_135_pp0_it2(5) <= ap_reg_ppstg_tmp_reg_135_pp0_it1(5);
ap_reg_ppstg_tmp_reg_135_pp0_it2(6) <= ap_reg_ppstg_tmp_reg_135_pp0_it1(6);
ap_reg_ppstg_tmp_reg_135_pp0_it2(7) <= ap_reg_ppstg_tmp_reg_135_pp0_it1(7);
ap_reg_ppstg_tmp_reg_135_pp0_it2(8) <= ap_reg_ppstg_tmp_reg_135_pp0_it1(8);
ap_reg_ppstg_tmp_reg_135_pp0_it2(9) <= ap_reg_ppstg_tmp_reg_135_pp0_it1(9);
ap_reg_ppstg_tmp_reg_135_pp0_it2(10) <= ap_reg_ppstg_tmp_reg_135_pp0_it1(10);
ap_reg_ppstg_tmp_reg_135_pp0_it2(11) <= ap_reg_ppstg_tmp_reg_135_pp0_it1(11);
ap_reg_ppstg_tmp_reg_135_pp0_it2(12) <= ap_reg_ppstg_tmp_reg_135_pp0_it1(12);
ap_reg_ppstg_tmp_reg_135_pp0_it2(13) <= ap_reg_ppstg_tmp_reg_135_pp0_it1(13);
ap_reg_ppstg_tmp_reg_135_pp0_it2(14) <= ap_reg_ppstg_tmp_reg_135_pp0_it1(14);
ap_reg_ppstg_tmp_reg_135_pp0_it2(15) <= ap_reg_ppstg_tmp_reg_135_pp0_it1(15);
ap_reg_ppstg_tmp_reg_135_pp0_it3(0) <= ap_reg_ppstg_tmp_reg_135_pp0_it2(0);
ap_reg_ppstg_tmp_reg_135_pp0_it3(1) <= ap_reg_ppstg_tmp_reg_135_pp0_it2(1);
ap_reg_ppstg_tmp_reg_135_pp0_it3(2) <= ap_reg_ppstg_tmp_reg_135_pp0_it2(2);
ap_reg_ppstg_tmp_reg_135_pp0_it3(3) <= ap_reg_ppstg_tmp_reg_135_pp0_it2(3);
ap_reg_ppstg_tmp_reg_135_pp0_it3(4) <= ap_reg_ppstg_tmp_reg_135_pp0_it2(4);
ap_reg_ppstg_tmp_reg_135_pp0_it3(5) <= ap_reg_ppstg_tmp_reg_135_pp0_it2(5);
ap_reg_ppstg_tmp_reg_135_pp0_it3(6) <= ap_reg_ppstg_tmp_reg_135_pp0_it2(6);
ap_reg_ppstg_tmp_reg_135_pp0_it3(7) <= ap_reg_ppstg_tmp_reg_135_pp0_it2(7);
ap_reg_ppstg_tmp_reg_135_pp0_it3(8) <= ap_reg_ppstg_tmp_reg_135_pp0_it2(8);
ap_reg_ppstg_tmp_reg_135_pp0_it3(9) <= ap_reg_ppstg_tmp_reg_135_pp0_it2(9);
ap_reg_ppstg_tmp_reg_135_pp0_it3(10) <= ap_reg_ppstg_tmp_reg_135_pp0_it2(10);
ap_reg_ppstg_tmp_reg_135_pp0_it3(11) <= ap_reg_ppstg_tmp_reg_135_pp0_it2(11);
ap_reg_ppstg_tmp_reg_135_pp0_it3(12) <= ap_reg_ppstg_tmp_reg_135_pp0_it2(12);
ap_reg_ppstg_tmp_reg_135_pp0_it3(13) <= ap_reg_ppstg_tmp_reg_135_pp0_it2(13);
ap_reg_ppstg_tmp_reg_135_pp0_it3(14) <= ap_reg_ppstg_tmp_reg_135_pp0_it2(14);
ap_reg_ppstg_tmp_reg_135_pp0_it3(15) <= ap_reg_ppstg_tmp_reg_135_pp0_it2(15);
ap_reg_ppstg_tmp_reg_135_pp0_it4(0) <= ap_reg_ppstg_tmp_reg_135_pp0_it3(0);
ap_reg_ppstg_tmp_reg_135_pp0_it4(1) <= ap_reg_ppstg_tmp_reg_135_pp0_it3(1);
ap_reg_ppstg_tmp_reg_135_pp0_it4(2) <= ap_reg_ppstg_tmp_reg_135_pp0_it3(2);
ap_reg_ppstg_tmp_reg_135_pp0_it4(3) <= ap_reg_ppstg_tmp_reg_135_pp0_it3(3);
ap_reg_ppstg_tmp_reg_135_pp0_it4(4) <= ap_reg_ppstg_tmp_reg_135_pp0_it3(4);
ap_reg_ppstg_tmp_reg_135_pp0_it4(5) <= ap_reg_ppstg_tmp_reg_135_pp0_it3(5);
ap_reg_ppstg_tmp_reg_135_pp0_it4(6) <= ap_reg_ppstg_tmp_reg_135_pp0_it3(6);
ap_reg_ppstg_tmp_reg_135_pp0_it4(7) <= ap_reg_ppstg_tmp_reg_135_pp0_it3(7);
ap_reg_ppstg_tmp_reg_135_pp0_it4(8) <= ap_reg_ppstg_tmp_reg_135_pp0_it3(8);
ap_reg_ppstg_tmp_reg_135_pp0_it4(9) <= ap_reg_ppstg_tmp_reg_135_pp0_it3(9);
ap_reg_ppstg_tmp_reg_135_pp0_it4(10) <= ap_reg_ppstg_tmp_reg_135_pp0_it3(10);
ap_reg_ppstg_tmp_reg_135_pp0_it4(11) <= ap_reg_ppstg_tmp_reg_135_pp0_it3(11);
ap_reg_ppstg_tmp_reg_135_pp0_it4(12) <= ap_reg_ppstg_tmp_reg_135_pp0_it3(12);
ap_reg_ppstg_tmp_reg_135_pp0_it4(13) <= ap_reg_ppstg_tmp_reg_135_pp0_it3(13);
ap_reg_ppstg_tmp_reg_135_pp0_it4(14) <= ap_reg_ppstg_tmp_reg_135_pp0_it3(14);
ap_reg_ppstg_tmp_reg_135_pp0_it4(15) <= ap_reg_ppstg_tmp_reg_135_pp0_it3(15);
ap_reg_ppstg_tmp_reg_135_pp0_it5(0) <= ap_reg_ppstg_tmp_reg_135_pp0_it4(0);
ap_reg_ppstg_tmp_reg_135_pp0_it5(1) <= ap_reg_ppstg_tmp_reg_135_pp0_it4(1);
ap_reg_ppstg_tmp_reg_135_pp0_it5(2) <= ap_reg_ppstg_tmp_reg_135_pp0_it4(2);
ap_reg_ppstg_tmp_reg_135_pp0_it5(3) <= ap_reg_ppstg_tmp_reg_135_pp0_it4(3);
ap_reg_ppstg_tmp_reg_135_pp0_it5(4) <= ap_reg_ppstg_tmp_reg_135_pp0_it4(4);
ap_reg_ppstg_tmp_reg_135_pp0_it5(5) <= ap_reg_ppstg_tmp_reg_135_pp0_it4(5);
ap_reg_ppstg_tmp_reg_135_pp0_it5(6) <= ap_reg_ppstg_tmp_reg_135_pp0_it4(6);
ap_reg_ppstg_tmp_reg_135_pp0_it5(7) <= ap_reg_ppstg_tmp_reg_135_pp0_it4(7);
ap_reg_ppstg_tmp_reg_135_pp0_it5(8) <= ap_reg_ppstg_tmp_reg_135_pp0_it4(8);
ap_reg_ppstg_tmp_reg_135_pp0_it5(9) <= ap_reg_ppstg_tmp_reg_135_pp0_it4(9);
ap_reg_ppstg_tmp_reg_135_pp0_it5(10) <= ap_reg_ppstg_tmp_reg_135_pp0_it4(10);
ap_reg_ppstg_tmp_reg_135_pp0_it5(11) <= ap_reg_ppstg_tmp_reg_135_pp0_it4(11);
ap_reg_ppstg_tmp_reg_135_pp0_it5(12) <= ap_reg_ppstg_tmp_reg_135_pp0_it4(12);
ap_reg_ppstg_tmp_reg_135_pp0_it5(13) <= ap_reg_ppstg_tmp_reg_135_pp0_it4(13);
ap_reg_ppstg_tmp_reg_135_pp0_it5(14) <= ap_reg_ppstg_tmp_reg_135_pp0_it4(14);
ap_reg_ppstg_tmp_reg_135_pp0_it5(15) <= ap_reg_ppstg_tmp_reg_135_pp0_it4(15);
ap_reg_ppstg_tmp_reg_135_pp0_it6(0) <= ap_reg_ppstg_tmp_reg_135_pp0_it5(0);
ap_reg_ppstg_tmp_reg_135_pp0_it6(1) <= ap_reg_ppstg_tmp_reg_135_pp0_it5(1);
ap_reg_ppstg_tmp_reg_135_pp0_it6(2) <= ap_reg_ppstg_tmp_reg_135_pp0_it5(2);
ap_reg_ppstg_tmp_reg_135_pp0_it6(3) <= ap_reg_ppstg_tmp_reg_135_pp0_it5(3);
ap_reg_ppstg_tmp_reg_135_pp0_it6(4) <= ap_reg_ppstg_tmp_reg_135_pp0_it5(4);
ap_reg_ppstg_tmp_reg_135_pp0_it6(5) <= ap_reg_ppstg_tmp_reg_135_pp0_it5(5);
ap_reg_ppstg_tmp_reg_135_pp0_it6(6) <= ap_reg_ppstg_tmp_reg_135_pp0_it5(6);
ap_reg_ppstg_tmp_reg_135_pp0_it6(7) <= ap_reg_ppstg_tmp_reg_135_pp0_it5(7);
ap_reg_ppstg_tmp_reg_135_pp0_it6(8) <= ap_reg_ppstg_tmp_reg_135_pp0_it5(8);
ap_reg_ppstg_tmp_reg_135_pp0_it6(9) <= ap_reg_ppstg_tmp_reg_135_pp0_it5(9);
ap_reg_ppstg_tmp_reg_135_pp0_it6(10) <= ap_reg_ppstg_tmp_reg_135_pp0_it5(10);
ap_reg_ppstg_tmp_reg_135_pp0_it6(11) <= ap_reg_ppstg_tmp_reg_135_pp0_it5(11);
ap_reg_ppstg_tmp_reg_135_pp0_it6(12) <= ap_reg_ppstg_tmp_reg_135_pp0_it5(12);
ap_reg_ppstg_tmp_reg_135_pp0_it6(13) <= ap_reg_ppstg_tmp_reg_135_pp0_it5(13);
ap_reg_ppstg_tmp_reg_135_pp0_it6(14) <= ap_reg_ppstg_tmp_reg_135_pp0_it5(14);
ap_reg_ppstg_tmp_reg_135_pp0_it6(15) <= ap_reg_ppstg_tmp_reg_135_pp0_it5(15);
ap_reg_ppstg_tmp_reg_135_pp0_it7(0) <= ap_reg_ppstg_tmp_reg_135_pp0_it6(0);
ap_reg_ppstg_tmp_reg_135_pp0_it7(1) <= ap_reg_ppstg_tmp_reg_135_pp0_it6(1);
ap_reg_ppstg_tmp_reg_135_pp0_it7(2) <= ap_reg_ppstg_tmp_reg_135_pp0_it6(2);
ap_reg_ppstg_tmp_reg_135_pp0_it7(3) <= ap_reg_ppstg_tmp_reg_135_pp0_it6(3);
ap_reg_ppstg_tmp_reg_135_pp0_it7(4) <= ap_reg_ppstg_tmp_reg_135_pp0_it6(4);
ap_reg_ppstg_tmp_reg_135_pp0_it7(5) <= ap_reg_ppstg_tmp_reg_135_pp0_it6(5);
ap_reg_ppstg_tmp_reg_135_pp0_it7(6) <= ap_reg_ppstg_tmp_reg_135_pp0_it6(6);
ap_reg_ppstg_tmp_reg_135_pp0_it7(7) <= ap_reg_ppstg_tmp_reg_135_pp0_it6(7);
ap_reg_ppstg_tmp_reg_135_pp0_it7(8) <= ap_reg_ppstg_tmp_reg_135_pp0_it6(8);
ap_reg_ppstg_tmp_reg_135_pp0_it7(9) <= ap_reg_ppstg_tmp_reg_135_pp0_it6(9);
ap_reg_ppstg_tmp_reg_135_pp0_it7(10) <= ap_reg_ppstg_tmp_reg_135_pp0_it6(10);
ap_reg_ppstg_tmp_reg_135_pp0_it7(11) <= ap_reg_ppstg_tmp_reg_135_pp0_it6(11);
ap_reg_ppstg_tmp_reg_135_pp0_it7(12) <= ap_reg_ppstg_tmp_reg_135_pp0_it6(12);
ap_reg_ppstg_tmp_reg_135_pp0_it7(13) <= ap_reg_ppstg_tmp_reg_135_pp0_it6(13);
ap_reg_ppstg_tmp_reg_135_pp0_it7(14) <= ap_reg_ppstg_tmp_reg_135_pp0_it6(14);
ap_reg_ppstg_tmp_reg_135_pp0_it7(15) <= ap_reg_ppstg_tmp_reg_135_pp0_it6(15);
ap_reg_ppstg_tmp_reg_135_pp0_it8(0) <= ap_reg_ppstg_tmp_reg_135_pp0_it7(0);
ap_reg_ppstg_tmp_reg_135_pp0_it8(1) <= ap_reg_ppstg_tmp_reg_135_pp0_it7(1);
ap_reg_ppstg_tmp_reg_135_pp0_it8(2) <= ap_reg_ppstg_tmp_reg_135_pp0_it7(2);
ap_reg_ppstg_tmp_reg_135_pp0_it8(3) <= ap_reg_ppstg_tmp_reg_135_pp0_it7(3);
ap_reg_ppstg_tmp_reg_135_pp0_it8(4) <= ap_reg_ppstg_tmp_reg_135_pp0_it7(4);
ap_reg_ppstg_tmp_reg_135_pp0_it8(5) <= ap_reg_ppstg_tmp_reg_135_pp0_it7(5);
ap_reg_ppstg_tmp_reg_135_pp0_it8(6) <= ap_reg_ppstg_tmp_reg_135_pp0_it7(6);
ap_reg_ppstg_tmp_reg_135_pp0_it8(7) <= ap_reg_ppstg_tmp_reg_135_pp0_it7(7);
ap_reg_ppstg_tmp_reg_135_pp0_it8(8) <= ap_reg_ppstg_tmp_reg_135_pp0_it7(8);
ap_reg_ppstg_tmp_reg_135_pp0_it8(9) <= ap_reg_ppstg_tmp_reg_135_pp0_it7(9);
ap_reg_ppstg_tmp_reg_135_pp0_it8(10) <= ap_reg_ppstg_tmp_reg_135_pp0_it7(10);
ap_reg_ppstg_tmp_reg_135_pp0_it8(11) <= ap_reg_ppstg_tmp_reg_135_pp0_it7(11);
ap_reg_ppstg_tmp_reg_135_pp0_it8(12) <= ap_reg_ppstg_tmp_reg_135_pp0_it7(12);
ap_reg_ppstg_tmp_reg_135_pp0_it8(13) <= ap_reg_ppstg_tmp_reg_135_pp0_it7(13);
ap_reg_ppstg_tmp_reg_135_pp0_it8(14) <= ap_reg_ppstg_tmp_reg_135_pp0_it7(14);
ap_reg_ppstg_tmp_reg_135_pp0_it8(15) <= ap_reg_ppstg_tmp_reg_135_pp0_it7(15);
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and (indices_stride_rsp_empty_n = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it10) and (indices_begin_rsp_empty_n = ap_const_logic_0)))) and (ap_const_logic_1 = ap_ce))) then
i_sample_read_reg_130 <= i_sample;
tmp_reg_135(0) <= tmp_fu_93_p1(0);
tmp_reg_135(1) <= tmp_fu_93_p1(1);
tmp_reg_135(2) <= tmp_fu_93_p1(2);
tmp_reg_135(3) <= tmp_fu_93_p1(3);
tmp_reg_135(4) <= tmp_fu_93_p1(4);
tmp_reg_135(5) <= tmp_fu_93_p1(5);
tmp_reg_135(6) <= tmp_fu_93_p1(6);
tmp_reg_135(7) <= tmp_fu_93_p1(7);
tmp_reg_135(8) <= tmp_fu_93_p1(8);
tmp_reg_135(9) <= tmp_fu_93_p1(9);
tmp_reg_135(10) <= tmp_fu_93_p1(10);
tmp_reg_135(11) <= tmp_fu_93_p1(11);
tmp_reg_135(12) <= tmp_fu_93_p1(12);
tmp_reg_135(13) <= tmp_fu_93_p1(13);
tmp_reg_135(14) <= tmp_fu_93_p1(14);
tmp_reg_135(15) <= tmp_fu_93_p1(15);
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it10) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and (indices_stride_rsp_empty_n = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it10) and (indices_begin_rsp_empty_n = ap_const_logic_0)))) and (ap_const_logic_1 = ap_ce))) then
indices_begin_addr_read_reg_165 <= indices_begin_datain;
tmp_7_reg_170 <= grp_fu_110_p2;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and (indices_stride_rsp_empty_n = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it10) and (indices_begin_rsp_empty_n = ap_const_logic_0)))) and (ap_const_logic_1 = ap_ce))) then
indices_stride_addr_read_reg_145 <= indices_stride_datain;
end if;
end if;
end process;
tmp_reg_135(31 downto 16) <= "0000000000000000";
ap_reg_ppstg_tmp_reg_135_pp0_it1(31 downto 16) <= "0000000000000000";
ap_reg_ppstg_tmp_reg_135_pp0_it2(31 downto 16) <= "0000000000000000";
ap_reg_ppstg_tmp_reg_135_pp0_it3(31 downto 16) <= "0000000000000000";
ap_reg_ppstg_tmp_reg_135_pp0_it4(31 downto 16) <= "0000000000000000";
ap_reg_ppstg_tmp_reg_135_pp0_it5(31 downto 16) <= "0000000000000000";
ap_reg_ppstg_tmp_reg_135_pp0_it6(31 downto 16) <= "0000000000000000";
ap_reg_ppstg_tmp_reg_135_pp0_it7(31 downto 16) <= "0000000000000000";
ap_reg_ppstg_tmp_reg_135_pp0_it8(31 downto 16) <= "0000000000000000";
-- the next state (ap_NS_fsm) of the state machine. --
ap_NS_fsm_assign_proc : process (ap_start , ap_CS_fsm , ap_reg_ppiten_pp0_it0 , ap_reg_ppiten_pp0_it1 , ap_reg_ppiten_pp0_it10 , indices_stride_rsp_empty_n , indices_begin_rsp_empty_n , ap_ce , ap_sig_pprstidle_pp0)
begin
case ap_CS_fsm is
when ap_ST_pp0_stg0_fsm_0 =>
ap_NS_fsm <= ap_ST_pp0_stg0_fsm_0;
when others =>
ap_NS_fsm <= "X";
end case;
end process;
-- ap_done assign process. --
ap_done_assign_proc : process(ap_start, ap_CS_fsm, ap_reg_ppiten_pp0_it0, ap_reg_ppiten_pp0_it1, ap_reg_ppiten_pp0_it10, ap_reg_ppiten_pp0_it18, indices_stride_rsp_empty_n, indices_begin_rsp_empty_n, ap_ce)
begin
if (((not((ap_const_logic_1 = ap_start)) and (ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it0)) or ((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it18) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and (indices_stride_rsp_empty_n = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it10) and (indices_begin_rsp_empty_n = ap_const_logic_0)))) and (ap_const_logic_1 = ap_ce)))) then
ap_done <= ap_const_logic_1;
else
ap_done <= ap_const_logic_0;
end if;
end process;
-- ap_idle assign process. --
ap_idle_assign_proc : process(ap_start, ap_CS_fsm, ap_reg_ppiten_pp0_it0, ap_reg_ppiten_pp0_it1, ap_reg_ppiten_pp0_it2, ap_reg_ppiten_pp0_it3, ap_reg_ppiten_pp0_it4, ap_reg_ppiten_pp0_it5, ap_reg_ppiten_pp0_it6, ap_reg_ppiten_pp0_it7, ap_reg_ppiten_pp0_it8, ap_reg_ppiten_pp0_it9, ap_reg_ppiten_pp0_it10, ap_reg_ppiten_pp0_it11, ap_reg_ppiten_pp0_it12, ap_reg_ppiten_pp0_it13, ap_reg_ppiten_pp0_it14, ap_reg_ppiten_pp0_it15, ap_reg_ppiten_pp0_it16, ap_reg_ppiten_pp0_it17, ap_reg_ppiten_pp0_it18)
begin
if ((not((ap_const_logic_1 = ap_start)) and (ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it0) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it1) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it2) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it3) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it4) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it5) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it6) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it7) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it8) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it9) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it10) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it11) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it12) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it13) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it14) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it15) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it16) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it17) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it18))) then
ap_idle <= ap_const_logic_1;
else
ap_idle <= ap_const_logic_0;
end if;
end process;
-- ap_ready assign process. --
ap_ready_assign_proc : process(ap_start, ap_CS_fsm, ap_reg_ppiten_pp0_it0, ap_reg_ppiten_pp0_it1, ap_reg_ppiten_pp0_it10, indices_stride_rsp_empty_n, indices_begin_rsp_empty_n, ap_ce)
begin
if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and (indices_stride_rsp_empty_n = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it10) and (indices_begin_rsp_empty_n = ap_const_logic_0)))) and (ap_const_logic_1 = ap_ce))) then
ap_ready <= ap_const_logic_1;
else
ap_ready <= ap_const_logic_0;
end if;
end process;
ap_reg_ppiten_pp0_it0 <= ap_start;
ap_return <= grp_fu_125_p2;
-- ap_sig_pprstidle_pp0 assign process. --
ap_sig_pprstidle_pp0_assign_proc : process(ap_start, ap_reg_ppiten_pp0_it0, ap_reg_ppiten_pp0_it1, ap_reg_ppiten_pp0_it2, ap_reg_ppiten_pp0_it3, ap_reg_ppiten_pp0_it4, ap_reg_ppiten_pp0_it5, ap_reg_ppiten_pp0_it6, ap_reg_ppiten_pp0_it7, ap_reg_ppiten_pp0_it8, ap_reg_ppiten_pp0_it9, ap_reg_ppiten_pp0_it10, ap_reg_ppiten_pp0_it11, ap_reg_ppiten_pp0_it12, ap_reg_ppiten_pp0_it13, ap_reg_ppiten_pp0_it14, ap_reg_ppiten_pp0_it15, ap_reg_ppiten_pp0_it16, ap_reg_ppiten_pp0_it17)
begin
if (((ap_const_logic_0 = ap_reg_ppiten_pp0_it0) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it1) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it2) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it3) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it4) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it5) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it6) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it7) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it8) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it9) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it10) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it11) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it12) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it13) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it14) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it15) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it16) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it17) and (ap_const_logic_0 = ap_start))) then
ap_sig_pprstidle_pp0 <= ap_const_logic_1;
else
ap_sig_pprstidle_pp0 <= ap_const_logic_0;
end if;
end process;
-- grp_fu_110_ce assign process. --
grp_fu_110_ce_assign_proc : process(ap_start, ap_CS_fsm, ap_reg_ppiten_pp0_it0, ap_reg_ppiten_pp0_it1, ap_reg_ppiten_pp0_it10, indices_stride_rsp_empty_n, indices_begin_rsp_empty_n, ap_ce)
begin
if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and (indices_stride_rsp_empty_n = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it10) and (indices_begin_rsp_empty_n = ap_const_logic_0)))) and (ap_const_logic_1 = ap_ce))) then
grp_fu_110_ce <= ap_const_logic_1;
else
grp_fu_110_ce <= ap_const_logic_0;
end if;
end process;
grp_fu_110_p0 <= grp_fu_110_p00(16 - 1 downto 0);
grp_fu_110_p00 <= std_logic_vector(resize(unsigned(ap_reg_ppstg_i_sample_read_reg_130_pp0_it1),24));
grp_fu_110_p1 <= grp_fu_110_p10(8 - 1 downto 0);
grp_fu_110_p10 <= std_logic_vector(resize(unsigned(indices_stride_addr_read_reg_145),24));
-- grp_fu_125_ce assign process. --
grp_fu_125_ce_assign_proc : process(ap_start, ap_CS_fsm, ap_reg_ppiten_pp0_it0, ap_reg_ppiten_pp0_it1, ap_reg_ppiten_pp0_it10, indices_stride_rsp_empty_n, indices_begin_rsp_empty_n, ap_ce)
begin
if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and (indices_stride_rsp_empty_n = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it10) and (indices_begin_rsp_empty_n = ap_const_logic_0)))) and (ap_const_logic_1 = ap_ce))) then
grp_fu_125_ce <= ap_const_logic_1;
else
grp_fu_125_ce <= ap_const_logic_0;
end if;
end process;
grp_fu_125_p0 <= std_logic_vector(resize(unsigned(tmp_7_reg_170),32));
grp_fu_125_p1 <= indices_begin_addr_read_reg_165;
indices_begin_address <= ap_reg_ppstg_tmp_reg_135_pp0_it8;
indices_begin_dataout <= ap_const_lv32_0;
indices_begin_req_din <= ap_const_logic_0;
-- indices_begin_req_write assign process. --
indices_begin_req_write_assign_proc : process(ap_start, ap_CS_fsm, ap_reg_ppiten_pp0_it0, ap_reg_ppiten_pp0_it1, ap_reg_ppiten_pp0_it9, ap_reg_ppiten_pp0_it10, indices_stride_rsp_empty_n, indices_begin_rsp_empty_n, ap_ce)
begin
if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it9) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and (indices_stride_rsp_empty_n = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it10) and (indices_begin_rsp_empty_n = ap_const_logic_0)))) and (ap_const_logic_1 = ap_ce))) then
indices_begin_req_write <= ap_const_logic_1;
else
indices_begin_req_write <= ap_const_logic_0;
end if;
end process;
-- indices_begin_rsp_read assign process. --
indices_begin_rsp_read_assign_proc : process(ap_start, ap_CS_fsm, ap_reg_ppiten_pp0_it0, ap_reg_ppiten_pp0_it1, ap_reg_ppiten_pp0_it10, indices_stride_rsp_empty_n, indices_begin_rsp_empty_n, ap_ce)
begin
if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it10) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and (indices_stride_rsp_empty_n = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it10) and (indices_begin_rsp_empty_n = ap_const_logic_0)))) and (ap_const_logic_1 = ap_ce))) then
indices_begin_rsp_read <= ap_const_logic_1;
else
indices_begin_rsp_read <= ap_const_logic_0;
end if;
end process;
indices_begin_size <= ap_const_lv32_1;
indices_samples_address <= ap_const_lv32_0;
indices_samples_dataout <= ap_const_lv16_0;
indices_samples_req_din <= ap_const_logic_0;
indices_samples_req_write <= ap_const_logic_0;
indices_samples_rsp_read <= ap_const_logic_0;
indices_samples_size <= ap_const_lv32_0;
indices_stride_address <= tmp_fu_93_p1;
indices_stride_dataout <= ap_const_lv8_0;
indices_stride_req_din <= ap_const_logic_0;
-- indices_stride_req_write assign process. --
indices_stride_req_write_assign_proc : process(ap_start, ap_CS_fsm, ap_reg_ppiten_pp0_it0, ap_reg_ppiten_pp0_it1, ap_reg_ppiten_pp0_it10, indices_stride_rsp_empty_n, indices_begin_rsp_empty_n, ap_ce)
begin
if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and (indices_stride_rsp_empty_n = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it10) and (indices_begin_rsp_empty_n = ap_const_logic_0)))) and (ap_const_logic_1 = ap_ce))) then
indices_stride_req_write <= ap_const_logic_1;
else
indices_stride_req_write <= ap_const_logic_0;
end if;
end process;
-- indices_stride_rsp_read assign process. --
indices_stride_rsp_read_assign_proc : process(ap_start, ap_CS_fsm, ap_reg_ppiten_pp0_it0, ap_reg_ppiten_pp0_it1, ap_reg_ppiten_pp0_it10, indices_stride_rsp_empty_n, indices_begin_rsp_empty_n, ap_ce)
begin
if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and (indices_stride_rsp_empty_n = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it10) and (indices_begin_rsp_empty_n = ap_const_logic_0)))) and (ap_const_logic_1 = ap_ce))) then
indices_stride_rsp_read <= ap_const_logic_1;
else
indices_stride_rsp_read <= ap_const_logic_0;
end if;
end process;
indices_stride_size <= ap_const_lv32_1;
tmp_fu_93_p1 <= std_logic_vector(resize(unsigned(i_index),32));
end behav;
| lgpl-3.0 | 5fd6495aa13371182b47a7203fdd8574 | 0.611981 | 2.491808 | false | false | false | false |
grwlf/vsim | vhdl_ct/ct00431.vhd | 1 | 6,268 | -- NEED RESULT: ARCH00431: & correctly predefined for 2 scalar operands passed
-------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
-------------------------------------------------------------------------------
--
-- TEST NAME:
--
-- CT00431
--
-- AUTHOR:
--
-- A. Wilmot
--
-- TEST OBJECTIVES:
--
-- 7.2.3 (7)
-- 7.2.3 (9)
-- 7.2.3 (10)
-- 7.2.3 (11)
--
-- DESIGN UNIT ORDERING:
--
-- PKG00431
-- ENT00431(ARCH00431)
-- ENT00431_Test_Bench(ARCH00431_Test_Bench)
--
-- REVISION HISTORY:
--
-- 30-JUL-1987 - initial revision
--
-- NOTES:
--
-- self-checking
--
package PKG00431 is
type complex1 is record
fl : integer ;
f2 : integer ;
end record ;
type complex is array ( positive range <> ) of complex1 ;
constant c_complex1_1 : complex1 := (others => 5) ;
constant c_complex1_2 : complex1 := (others => 57) ;
subtype st_complex2 is complex ( 1 to 2 ) ;
subtype st_complex3 is complex ( 1 to 3 ) ;
subtype st_bit_vector2 is bit_vector ( 0 to 1 ) ;
subtype st_bit_vector3 is bit_vector ( 0 to 2 ) ;
subtype st_string2 is string ( 1 to 2 ) ;
subtype st_string3 is string ( 1 to 3 ) ;
constant c_complex_1 : st_complex3 := (others => c_complex1_1) ;
constant c_complex_2 : st_complex2 := ( 1 => c_complex1_1,
others => c_complex1_2 ) ;
constant c_complex_3 : st_complex2 := ( 1 => c_complex1_2,
others => c_complex1_1 ) ;
end PKG00431 ;
use WORK.PKG00431.all ;
entity ENT00431 is
generic (
i_bit_1 : bit := '1' ;
i_bit_2 : bit := '0' ;
i_character_1 : character := 'e' ;
i_character_2 : character := 'a' ;
i_complex1_1 : complex1 := c_complex1_1 ;
i_complex1_2 : complex1 := c_complex1_2
) ;
port ( locally_static_correct : out boolean ;
globally_static_correct : out boolean ;
dynamic_correct : out boolean ) ;
end ENT00431 ;
architecture ARCH00431 of ENT00431 is
begin
process
variable bool : boolean := true ;
variable cons_correct, gen_correct, dyn_correct : boolean := true ;
--
variable v_bit_vector_1 : st_bit_vector3 ;
variable v_bit_vector_2 : st_bit_vector2 ;
variable v_bit_1 : bit := i_bit_1 ;
variable v_bit_2 : bit := i_bit_2 ;
variable v_string_1 : st_string3 ;
variable v_string_2 : st_string2 ;
variable v_character_1 : character := i_character_1 ;
variable v_character_2 : character := i_character_2 ;
variable v_complex_1 : st_complex3 ;
variable v_complex_2 : st_complex2 ;
variable v_complex1_1 : complex1 := c_complex1_1 ;
variable v_complex1_2 : complex1 := c_complex1_2 ;
constant c2_bit_vector_1 : st_bit_vector3 :=
i_bit_1 & '1' & i_bit_1 ;
constant c2_bit_vector_2 : st_bit_vector2 :=
i_bit_1 & i_bit_2 ;
constant c2_bit_vector_3 : st_bit_vector2 :=
i_bit_2 & i_bit_1 ;
constant c2_string_1 : st_string3 :=
i_character_1 & 'e' & i_character_1 ;
constant c2_string_2 : st_string2 :=
i_character_1 & i_character_2 ;
constant c2_string_3 : st_string2 :=
i_character_2 & i_character_1 ;
constant c2_complex_1 : st_complex3 :=
i_complex1_1 & i_complex1_1 & i_complex1_1 ;
constant c2_complex_2 : st_complex2 :=
i_complex1_1 & i_complex1_2 ;
constant c2_complex_3 : st_complex2 :=
i_complex1_2 & i_complex1_1 ;
begin
gen_correct := c2_bit_vector_1 = B"111" and
c2_bit_vector_2 = B"10" and
c2_bit_vector_3 = B"01" and
c2_string_1 = "eee" and
c2_string_2 = "ea" and
c2_string_3 = "ae" and
c2_complex_1 = c_complex_1 and
c2_complex_2 = c_complex_2 and
c2_complex_3 = c_complex_3 ;
locally_static_correct <= cons_correct ;
globally_static_correct <= gen_correct ;
dyn_correct :=
st_bit_vector3' (v_bit_1 & '1' & i_bit_1) = B"111" and
st_bit_vector2' (v_bit_1 & v_bit_2) = B"10" and
st_bit_vector2' (v_bit_2 & v_bit_1) = B"01" and
st_string3' (v_character_1 & 'e' & i_character_1) = "eee" and
st_string2' (v_character_1 & v_character_2) = "ea" and
st_string2' (v_character_2 & v_character_1) = "ae" and
st_complex3' (st_complex2'(v_complex1_1 & i_complex1_1)
& i_complex1_1) = c_complex_1 and
st_complex2' (v_complex1_1 & v_complex1_2) = c_complex_2 and
st_complex2' (v_complex1_2 & v_complex1_1) = c_complex_3 ;
dynamic_correct <= dyn_correct ;
wait ;
end process ;
end ARCH00431 ;
use WORK.STANDARD_TYPES.all ;
entity ENT00431_Test_Bench is
end ENT00431_Test_Bench ;
architecture ARCH00431_Test_Bench of ENT00431_Test_Bench is
begin
L1:
block
signal locally_static_correct, globally_static_correct,
dynamic_correct : boolean := false ;
component UUT
port ( locally_static_correct : out boolean := false ;
globally_static_correct : out boolean := false ;
dynamic_correct : out boolean := false ) ;
end component ;
for CIS1 : UUT use entity WORK.ENT00431 ( ARCH00431 ) ;
begin
CIS1 : UUT
port map ( locally_static_correct,
globally_static_correct,
dynamic_correct ) ;
process ( locally_static_correct, globally_static_correct,
dynamic_correct )
begin
if locally_static_correct and globally_static_correct and
dynamic_correct then
test_report ( "ARCH00431" ,
"& correctly predefined for 2 scalar operands"
,
true ) ;
end if ;
end process ;
end block L1 ;
end ARCH00431_Test_Bench ;
| gpl-3.0 | a5681d25be30a88cc51197ea5a8a3ece | 0.527122 | 3.360858 | false | true | false | false |
grwlf/vsim | vhdl_ct/ct00128.vhd | 1 | 11,852 | -------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
-------------------------------------------------------------------------------
--
-- TEST NAME:
--
-- CT00128
--
-- AUTHOR:
--
-- G. Tominovich
--
-- TEST OBJECTIVES:
--
-- 8.3 (2)
-- 8.3 (3)
-- 8.3 (5)
-- 8.3.1 (3)
--
-- DESIGN UNIT ORDERING:
--
-- PKG00128
-- PKG00128/BODY
-- ENT00128(ARCH00128)
-- ENT00128_Test_Bench(ARCH00128_Test_Bench)
--
-- REVISION HISTORY:
--
-- 07-JUL-1987 - initial revision
--
-- NOTES:
--
-- self-checking
-- automatically generated
--
use WORK.STANDARD_TYPES.all ;
package PKG00128 is
type r_st_rec1 is record
f1 : integer ;
f2 : st_rec1 ;
end record ;
function c_r_st_rec1_1 return r_st_rec1 ;
-- (c_integer_1, c_st_rec1_1) ;
function c_r_st_rec1_2 return r_st_rec1 ;
-- (c_integer_2, c_st_rec1_2) ;
--
type r_st_rec2 is record
f1 : integer ;
f2 : st_rec2 ;
end record ;
function c_r_st_rec2_1 return r_st_rec2 ;
-- (c_integer_1, c_st_rec2_1) ;
function c_r_st_rec2_2 return r_st_rec2 ;
-- (c_integer_2, c_st_rec2_2) ;
--
type r_st_rec3 is record
f1 : integer ;
f2 : st_rec3 ;
end record ;
function c_r_st_rec3_1 return r_st_rec3 ;
-- (c_integer_1, c_st_rec3_1) ;
function c_r_st_rec3_2 return r_st_rec3 ;
-- (c_integer_2, c_st_rec3_2) ;
--
--
end PKG00128 ;
--
package body PKG00128 is
function c_r_st_rec1_1 return r_st_rec1
is begin
return (c_integer_1, c_st_rec1_1) ;
end c_r_st_rec1_1 ;
--
function c_r_st_rec1_2 return r_st_rec1
is begin
return (c_integer_2, c_st_rec1_2) ;
end c_r_st_rec1_2 ;
--
--
function c_r_st_rec2_1 return r_st_rec2
is begin
return (c_integer_1, c_st_rec2_1) ;
end c_r_st_rec2_1 ;
--
function c_r_st_rec2_2 return r_st_rec2
is begin
return (c_integer_2, c_st_rec2_2) ;
end c_r_st_rec2_2 ;
--
--
function c_r_st_rec3_1 return r_st_rec3
is begin
return (c_integer_1, c_st_rec3_1) ;
end c_r_st_rec3_1 ;
--
function c_r_st_rec3_2 return r_st_rec3
is begin
return (c_integer_2, c_st_rec3_2) ;
end c_r_st_rec3_2 ;
--
--
--
end PKG00128 ;
--
use WORK.STANDARD_TYPES.all ;
use WORK.PKG00128.all ;
entity ENT00128 is
port (
s_r_st_rec1 : inout r_st_rec1
; s_r_st_rec2 : inout r_st_rec2
; s_r_st_rec3 : inout r_st_rec3
) ;
subtype chk_sig_type is integer range -1 to 100 ;
signal chk_r_st_rec1 : chk_sig_type := -1 ;
signal chk_r_st_rec2 : chk_sig_type := -1 ;
signal chk_r_st_rec3 : chk_sig_type := -1 ;
--
end ENT00128 ;
--
architecture ARCH00128 of ENT00128 is
begin
PGEN_CHKP_1 :
process ( chk_r_st_rec1 )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P1" ,
"Transport transactions entirely completed",
chk_r_st_rec1 = 4 ) ;
end if ;
end process PGEN_CHKP_1 ;
--
P1 :
process ( s_r_st_rec1 )
variable correct : boolean ;
variable counter : integer := 0 ;
variable savtime : time ;
begin
case counter is
when 0
=> s_r_st_rec1.f2.f2 <= transport
c_r_st_rec1_2.f2.f2 after 10 ns,
c_r_st_rec1_1.f2.f2 after 20 ns ;
--
when 1
=> correct :=
s_r_st_rec1.f2.f2 =
c_r_st_rec1_2.f2.f2 and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_r_st_rec1.f2.f2 =
c_r_st_rec1_1.f2.f2 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00128.P1" ,
"Multi transport transactions occurred on signal " &
"asg with selected name prefixed by a selected name on LHS",
correct ) ;
s_r_st_rec1.f2.f2 <= transport
c_r_st_rec1_2.f2.f2 after 10 ns ,
c_r_st_rec1_1.f2.f2 after 20 ns ,
c_r_st_rec1_2.f2.f2 after 30 ns ,
c_r_st_rec1_1.f2.f2 after 40 ns ;
--
when 3
=> correct :=
s_r_st_rec1.f2.f2 =
c_r_st_rec1_2.f2.f2 and
(savtime + 10 ns) = Std.Standard.Now ;
s_r_st_rec1.f2.f2 <= transport
c_r_st_rec1_1.f2.f2 after 5 ns ;
--
when 4
=> correct :=
correct and
s_r_st_rec1.f2.f2 =
c_r_st_rec1_1.f2.f2 and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00128" ,
"One transport transaction occurred on signal " &
"asg with selected name prefixed by a selected name on LHS",
correct ) ;
test_report ( "ARCH00128" ,
"Old transactions were removed on signal " &
"asg with selected name prefixed by a selected name on LHS",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00128" ,
"Old transactions were removed on signal " &
"asg with selected name prefixed by a selected name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_r_st_rec1 <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
end process P1 ;
--
PGEN_CHKP_2 :
process ( chk_r_st_rec2 )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P2" ,
"Transport transactions entirely completed",
chk_r_st_rec2 = 4 ) ;
end if ;
end process PGEN_CHKP_2 ;
--
P2 :
process ( s_r_st_rec2 )
variable correct : boolean ;
variable counter : integer := 0 ;
variable savtime : time ;
begin
case counter is
when 0
=> s_r_st_rec2.f2.f2 <= transport
c_r_st_rec2_2.f2.f2 after 10 ns,
c_r_st_rec2_1.f2.f2 after 20 ns ;
--
when 1
=> correct :=
s_r_st_rec2.f2.f2 =
c_r_st_rec2_2.f2.f2 and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_r_st_rec2.f2.f2 =
c_r_st_rec2_1.f2.f2 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00128.P2" ,
"Multi transport transactions occurred on signal " &
"asg with selected name prefixed by a selected name on LHS",
correct ) ;
s_r_st_rec2.f2.f2 <= transport
c_r_st_rec2_2.f2.f2 after 10 ns ,
c_r_st_rec2_1.f2.f2 after 20 ns ,
c_r_st_rec2_2.f2.f2 after 30 ns ,
c_r_st_rec2_1.f2.f2 after 40 ns ;
--
when 3
=> correct :=
s_r_st_rec2.f2.f2 =
c_r_st_rec2_2.f2.f2 and
(savtime + 10 ns) = Std.Standard.Now ;
s_r_st_rec2.f2.f2 <= transport
c_r_st_rec2_1.f2.f2 after 5 ns ;
--
when 4
=> correct :=
correct and
s_r_st_rec2.f2.f2 =
c_r_st_rec2_1.f2.f2 and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00128" ,
"One transport transaction occurred on signal " &
"asg with selected name prefixed by a selected name on LHS",
correct ) ;
test_report ( "ARCH00128" ,
"Old transactions were removed on signal " &
"asg with selected name prefixed by a selected name on LHS",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00128" ,
"Old transactions were removed on signal " &
"asg with selected name prefixed by a selected name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_r_st_rec2 <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
end process P2 ;
--
PGEN_CHKP_3 :
process ( chk_r_st_rec3 )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P3" ,
"Transport transactions entirely completed",
chk_r_st_rec3 = 4 ) ;
end if ;
end process PGEN_CHKP_3 ;
--
P3 :
process ( s_r_st_rec3 )
variable correct : boolean ;
variable counter : integer := 0 ;
variable savtime : time ;
begin
case counter is
when 0
=> s_r_st_rec3.f2.f2 <= transport
c_r_st_rec3_2.f2.f2 after 10 ns,
c_r_st_rec3_1.f2.f2 after 20 ns ;
--
when 1
=> correct :=
s_r_st_rec3.f2.f2 =
c_r_st_rec3_2.f2.f2 and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_r_st_rec3.f2.f2 =
c_r_st_rec3_1.f2.f2 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00128.P3" ,
"Multi transport transactions occurred on signal " &
"asg with selected name prefixed by a selected name on LHS",
correct ) ;
s_r_st_rec3.f2.f2 <= transport
c_r_st_rec3_2.f2.f2 after 10 ns ,
c_r_st_rec3_1.f2.f2 after 20 ns ,
c_r_st_rec3_2.f2.f2 after 30 ns ,
c_r_st_rec3_1.f2.f2 after 40 ns ;
--
when 3
=> correct :=
s_r_st_rec3.f2.f2 =
c_r_st_rec3_2.f2.f2 and
(savtime + 10 ns) = Std.Standard.Now ;
s_r_st_rec3.f2.f2 <= transport
c_r_st_rec3_1.f2.f2 after 5 ns ;
--
when 4
=> correct :=
correct and
s_r_st_rec3.f2.f2 =
c_r_st_rec3_1.f2.f2 and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00128" ,
"One transport transaction occurred on signal " &
"asg with selected name prefixed by a selected name on LHS",
correct ) ;
test_report ( "ARCH00128" ,
"Old transactions were removed on signal " &
"asg with selected name prefixed by a selected name on LHS",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00128" ,
"Old transactions were removed on signal " &
"asg with selected name prefixed by a selected name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_r_st_rec3 <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
end process P3 ;
--
--
end ARCH00128 ;
--
use WORK.STANDARD_TYPES.all ;
use WORK.PKG00128.all ;
entity ENT00128_Test_Bench is
signal s_r_st_rec1 : r_st_rec1
:= c_r_st_rec1_1 ;
signal s_r_st_rec2 : r_st_rec2
:= c_r_st_rec2_1 ;
signal s_r_st_rec3 : r_st_rec3
:= c_r_st_rec3_1 ;
--
end ENT00128_Test_Bench ;
--
architecture ARCH00128_Test_Bench of ENT00128_Test_Bench is
begin
L1:
block
component UUT
port (
s_r_st_rec1 : inout r_st_rec1
; s_r_st_rec2 : inout r_st_rec2
; s_r_st_rec3 : inout r_st_rec3
) ;
end component ;
--
for CIS1 : UUT use entity WORK.ENT00128 ( ARCH00128 ) ;
begin
CIS1 : UUT
port map (
s_r_st_rec1
, s_r_st_rec2
, s_r_st_rec3
) ;
end block L1 ;
end ARCH00128_Test_Bench ;
| gpl-3.0 | f6e547a8cda497a1497f81288672f723 | 0.498734 | 3.122234 | false | true | false | false |
grwlf/vsim | vhdl_ct/ct00328.vhd | 1 | 2,147 | -- NEED RESULT: *** 10 assertion messages should follow
-- NEED RESULT: Assertion # 1
-- NEED RESULT: Assertion # 2
-- NEED RESULT: Assertion # 3
-- NEED RESULT: Assertion # 4
-- NEED RESULT: Assertion # 5
-- NEED RESULT: Assertion # 6
-- NEED RESULT: Assertion # 7
-- NEED RESULT: Assertion # 8
-- NEED RESULT: Assertion # 9
-- NEED RESULT: Assertion #10
-------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
-------------------------------------------------------------------------------
--
-- TEST NAME:
--
-- CT00328
--
-- AUTHOR:
--
-- G. Tominovich
--
-- TEST OBJECTIVES:
--
-- 9.4 (8)
--
-- DESIGN UNIT ORDERING:
--
-- ENT00328_Test_Bench(ARCH00328_Test_Bench)
--
-- REVISION HISTORY:
--
-- 29-JUL-1987 - initial revision
--
-- NOTES:
--
-- Verify that assertion messages match comment messages output
--
--
use WORK.STANDARD_TYPES.all ;
entity ENT00328_Test_Bench is
end ENT00328_Test_Bench ;
architecture ARCH00328_Test_Bench of ENT00328_Test_Bench is
subtype ST is String ( 1 to 2 ) ;
signal S : ST := " 1";
begin
process
begin
print ( "*** 10 assertion messages should follow" ) ;
wait ;
end process ;
assert S /= S
report "Assertion #" & S (1 to 2)
severity Note ;
P1 :
process ( S )
variable count : integer := 1 ;
begin
case count is
when 1 =>
S(2) <= transport '2' after 10 ns ;
when 2 =>
S(2 to 2) <= transport "3" after 10 ns ;
when 3 =>
S(2) <= transport '4' after 10 ns ;
when 4 =>
S(2) <= transport '5' after 10 ns ;
when 5 =>
S(2) <= transport '6' after 10 ns ;
when 6 =>
S(2) <= transport '7' after 10 ns ;
when 7 =>
S(2) <= transport '8' after 10 ns ;
when 8 =>
S(2) <= transport '9' after 10 ns ;
when 9 =>
S <= transport "10" after 10 ns ;
when others =>
null;
end case ;
count := count + 1 ;
end process P1 ;
end ARCH00328_Test_Bench ;
| gpl-3.0 | f026eedb080c248c0c4f5316cfcd67f7 | 0.510014 | 3.429712 | false | true | false | false |
grwlf/vsim | vhdl_ct/ct00157.vhd | 1 | 24,466 | -- NEED RESULT: ARCH00157.P1: Multi inertial transactions occurred on signal asg with indexed name prefixed by an indexed name on LHS passed
-- NEED RESULT: ARCH00157.P2: Multi inertial transactions occurred on signal asg with indexed name prefixed by an indexed name on LHS passed
-- NEED RESULT: ARCH00157.P3: Multi inertial transactions occurred on signal asg with indexed name prefixed by an indexed name on LHS passed
-- NEED RESULT: ARCH00157: One inertial transaction occurred on signal asg with indexed name prefixed by an indexed name on LHS passed
-- NEED RESULT: ARCH00157: One inertial transaction occurred on signal asg with indexed name prefixed by an indexed name on LHS passed
-- NEED RESULT: ARCH00157: One inertial transaction occurred on signal asg with indexed name prefixed by an indexed name on LHS passed
-- NEED RESULT: ARCH00157: Old transactions were removed on signal asg with indexed name prefixed by an indexed name on LHS passed
-- NEED RESULT: ARCH00157: Old transactions were removed on signal asg with indexed name prefixed by an indexed name on LHS passed
-- NEED RESULT: ARCH00157: Old transactions were removed on signal asg with indexed name prefixed by an indexed name on LHS passed
-- NEED RESULT: ARCH00157: One inertial transaction occurred on signal asg with indexed name prefixed by an indexed name on LHS passed
-- NEED RESULT: ARCH00157: One inertial transaction occurred on signal asg with indexed name prefixed by an indexed name on LHS passed
-- NEED RESULT: ARCH00157: One inertial transaction occurred on signal asg with indexed name prefixed by an indexed name on LHS passed
-- NEED RESULT: ARCH00157: Inertial semantics check on a signal asg with indexed name prefixed by an indexed name on LHS passed
-- NEED RESULT: ARCH00157: Inertial semantics check on a signal asg with indexed name prefixed by an indexed name on LHS passed
-- NEED RESULT: ARCH00157: Inertial semantics check on a signal asg with indexed name prefixed by an indexed name on LHS passed
-- NEED RESULT: P3: Inertial transactions entirely completed passed
-- NEED RESULT: P2: Inertial transactions entirely completed passed
-- NEED RESULT: P1: Inertial transactions entirely completed passed
-------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
-------------------------------------------------------------------------------
--
-- TEST NAME:
--
-- CT00157
--
-- AUTHOR:
--
-- G. Tominovich
--
-- TEST OBJECTIVES:
--
-- 8.3 (1)
-- 8.3 (2)
-- 8.3 (4)
-- 8.3 (5)
-- 8.3.1 (4)
--
-- DESIGN UNIT ORDERING:
--
-- ENT00157(ARCH00157)
-- ENT00157_Test_Bench(ARCH00157_Test_Bench)
--
-- REVISION HISTORY:
--
-- 08-JUL-1987 - initial revision
--
-- NOTES:
--
-- self-checking
-- automatically generated
--
use WORK.STANDARD_TYPES.all ;
entity ENT00157 is
subtype chk_sig_type is integer range -1 to 100 ;
signal chk_st_arr1_vector : chk_sig_type := -1 ;
signal chk_st_arr2_vector : chk_sig_type := -1 ;
signal chk_st_arr3_vector : chk_sig_type := -1 ;
--
procedure Proc1 (
signal s_st_arr1_vector : inout st_arr1_vector ;
variable counter : inout integer ;
variable correct : inout boolean ;
variable savtime : inout time ;
signal chk_st_arr1_vector : out chk_sig_type
)
is
begin
case counter is
when 0 =>
s_st_arr1_vector(lowb) (
st_arr1'Left) <=
c_st_arr1_vector_2(highb) (
st_arr1'Right) after 10 ns,
c_st_arr1_vector_1(highb) (
st_arr1'Right) after 20 ns ;
--
when 1 =>
correct :=
s_st_arr1_vector(lowb) (
st_arr1'Left) =
c_st_arr1_vector_2(highb) (
st_arr1'Right) and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2 =>
correct :=
correct and
s_st_arr1_vector(lowb) (
st_arr1'Left) =
c_st_arr1_vector_1(highb) (
st_arr1'Right) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00157.P1" ,
"Multi inertial transactions occurred on signal " &
"asg with indexed name prefixed by an indexed name on LHS",
correct ) ;
s_st_arr1_vector(lowb) (
st_arr1'Left) <=
c_st_arr1_vector_2(highb) (
st_arr1'Right) after 10 ns,
c_st_arr1_vector_1(highb) (
st_arr1'Right) after 20 ns,
c_st_arr1_vector_2(highb) (
st_arr1'Right) after 30 ns,
c_st_arr1_vector_1(highb) (
st_arr1'Right) after 40 ns ;
--
when 3 =>
correct :=
s_st_arr1_vector(lowb) (
st_arr1'Left) =
c_st_arr1_vector_2(highb) (
st_arr1'Right) and
(savtime + 10 ns) = Std.Standard.Now ;
s_st_arr1_vector(lowb) (
st_arr1'Left) <=
c_st_arr1_vector_1(highb) (
st_arr1'Right) after 5 ns;
--
when 4 =>
correct :=
correct and
s_st_arr1_vector(lowb) (
st_arr1'Left) =
c_st_arr1_vector_1(highb) (
st_arr1'Right) and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00157" ,
"One inertial transaction occurred on signal " &
"asg with indexed name prefixed by an indexed name on LHS",
correct ) ;
s_st_arr1_vector(lowb) (
st_arr1'Left) <= transport
c_st_arr1_vector_1(highb) (
st_arr1'Right) after 100 ns;
--
when 5 =>
correct :=
s_st_arr1_vector(lowb) (
st_arr1'Left) =
c_st_arr1_vector_1(highb) (
st_arr1'Right) and
(savtime + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00157" ,
"Old transactions were removed on signal " &
"asg with indexed name prefixed by an indexed name on LHS",
correct ) ;
s_st_arr1_vector(lowb) (
st_arr1'Left) <=
c_st_arr1_vector_2(highb) (
st_arr1'Right) after 10 ns,
c_st_arr1_vector_1(highb) (
st_arr1'Right) after 20 ns,
c_st_arr1_vector_2(highb) (
st_arr1'Right) after 30 ns,
c_st_arr1_vector_1(highb) (
st_arr1'Right) after 40 ns ;
--
when 6 =>
correct :=
s_st_arr1_vector(lowb) (
st_arr1'Left) =
c_st_arr1_vector_2(highb) (
st_arr1'Right) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00157" ,
"One inertial transaction occurred on signal " &
"asg with indexed name prefixed by an indexed name on LHS",
correct ) ;
-- The following will mark last transaction above
s_st_arr1_vector(lowb) (
st_arr1'Left) <=
c_st_arr1_vector_1(highb) (
st_arr1'Right) after 40 ns;
--
when 7 =>
correct :=
s_st_arr1_vector(lowb) (
st_arr1'Left) =
c_st_arr1_vector_1(highb) (
st_arr1'Right) and
(savtime + 30 ns) = Std.Standard.Now ;
--
when 8 =>
correct :=
correct and
s_st_arr1_vector(lowb) (
st_arr1'Left) =
c_st_arr1_vector_1(highb) (
st_arr1'Right) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00157" ,
"Inertial semantics check on a signal " &
"asg with indexed name prefixed by an indexed name on LHS",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00157" ,
"Inertial semantics check on a signal " &
"asg with indexed name prefixed by an indexed name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_st_arr1_vector <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
end Proc1 ;
--
procedure Proc2 (
signal s_st_arr2_vector : inout st_arr2_vector ;
variable counter : inout integer ;
variable correct : inout boolean ;
variable savtime : inout time ;
signal chk_st_arr2_vector : out chk_sig_type
)
is
begin
case counter is
when 0 =>
s_st_arr2_vector(lowb) (
st_arr2'Left(1),st_arr2'Left(2)) <=
c_st_arr2_vector_2(highb) (
st_arr2'Right(1),st_arr2'Right(2)) after 10 ns,
c_st_arr2_vector_1(highb) (
st_arr2'Right(1),st_arr2'Right(2)) after 20 ns ;
--
when 1 =>
correct :=
s_st_arr2_vector(lowb) (
st_arr2'Left(1),st_arr2'Left(2)) =
c_st_arr2_vector_2(highb) (
st_arr2'Right(1),st_arr2'Right(2)) and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2 =>
correct :=
correct and
s_st_arr2_vector(lowb) (
st_arr2'Left(1),st_arr2'Left(2)) =
c_st_arr2_vector_1(highb) (
st_arr2'Right(1),st_arr2'Right(2)) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00157.P2" ,
"Multi inertial transactions occurred on signal " &
"asg with indexed name prefixed by an indexed name on LHS",
correct ) ;
s_st_arr2_vector(lowb) (
st_arr2'Left(1),st_arr2'Left(2)) <=
c_st_arr2_vector_2(highb) (
st_arr2'Right(1),st_arr2'Right(2)) after 10 ns,
c_st_arr2_vector_1(highb) (
st_arr2'Right(1),st_arr2'Right(2)) after 20 ns,
c_st_arr2_vector_2(highb) (
st_arr2'Right(1),st_arr2'Right(2)) after 30 ns,
c_st_arr2_vector_1(highb) (
st_arr2'Right(1),st_arr2'Right(2)) after 40 ns ;
--
when 3 =>
correct :=
s_st_arr2_vector(lowb) (
st_arr2'Left(1),st_arr2'Left(2)) =
c_st_arr2_vector_2(highb) (
st_arr2'Right(1),st_arr2'Right(2)) and
(savtime + 10 ns) = Std.Standard.Now ;
s_st_arr2_vector(lowb) (
st_arr2'Left(1),st_arr2'Left(2)) <=
c_st_arr2_vector_1(highb) (
st_arr2'Right(1),st_arr2'Right(2)) after 5 ns;
--
when 4 =>
correct :=
correct and
s_st_arr2_vector(lowb) (
st_arr2'Left(1),st_arr2'Left(2)) =
c_st_arr2_vector_1(highb) (
st_arr2'Right(1),st_arr2'Right(2)) and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00157" ,
"One inertial transaction occurred on signal " &
"asg with indexed name prefixed by an indexed name on LHS",
correct ) ;
s_st_arr2_vector(lowb) (
st_arr2'Left(1),st_arr2'Left(2)) <= transport
c_st_arr2_vector_1(highb) (
st_arr2'Right(1),st_arr2'Right(2)) after 100 ns;
--
when 5 =>
correct :=
s_st_arr2_vector(lowb) (
st_arr2'Left(1),st_arr2'Left(2)) =
c_st_arr2_vector_1(highb) (
st_arr2'Right(1),st_arr2'Right(2)) and
(savtime + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00157" ,
"Old transactions were removed on signal " &
"asg with indexed name prefixed by an indexed name on LHS",
correct ) ;
s_st_arr2_vector(lowb) (
st_arr2'Left(1),st_arr2'Left(2)) <=
c_st_arr2_vector_2(highb) (
st_arr2'Right(1),st_arr2'Right(2)) after 10 ns,
c_st_arr2_vector_1(highb) (
st_arr2'Right(1),st_arr2'Right(2)) after 20 ns,
c_st_arr2_vector_2(highb) (
st_arr2'Right(1),st_arr2'Right(2)) after 30 ns,
c_st_arr2_vector_1(highb) (
st_arr2'Right(1),st_arr2'Right(2)) after 40 ns ;
--
when 6 =>
correct :=
s_st_arr2_vector(lowb) (
st_arr2'Left(1),st_arr2'Left(2)) =
c_st_arr2_vector_2(highb) (
st_arr2'Right(1),st_arr2'Right(2)) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00157" ,
"One inertial transaction occurred on signal " &
"asg with indexed name prefixed by an indexed name on LHS",
correct ) ;
-- The following will mark last transaction above
s_st_arr2_vector(lowb) (
st_arr2'Left(1),st_arr2'Left(2)) <=
c_st_arr2_vector_1(highb) (
st_arr2'Right(1),st_arr2'Right(2)) after 40 ns;
--
when 7 =>
correct :=
s_st_arr2_vector(lowb) (
st_arr2'Left(1),st_arr2'Left(2)) =
c_st_arr2_vector_1(highb) (
st_arr2'Right(1),st_arr2'Right(2)) and
(savtime + 30 ns) = Std.Standard.Now ;
--
when 8 =>
correct :=
correct and
s_st_arr2_vector(lowb) (
st_arr2'Left(1),st_arr2'Left(2)) =
c_st_arr2_vector_1(highb) (
st_arr2'Right(1),st_arr2'Right(2)) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00157" ,
"Inertial semantics check on a signal " &
"asg with indexed name prefixed by an indexed name on LHS",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00157" ,
"Inertial semantics check on a signal " &
"asg with indexed name prefixed by an indexed name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_st_arr2_vector <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
end Proc2 ;
--
procedure Proc3 (
signal s_st_arr3_vector : inout st_arr3_vector ;
variable counter : inout integer ;
variable correct : inout boolean ;
variable savtime : inout time ;
signal chk_st_arr3_vector : out chk_sig_type
)
is
begin
case counter is
when 0 =>
s_st_arr3_vector(lowb) (
st_arr3'Left(1),st_arr3'Left(2)) <=
c_st_arr3_vector_2(highb) (
st_arr3'Right(1),st_arr3'Right(2)) after 10 ns,
c_st_arr3_vector_1(highb) (
st_arr3'Right(1),st_arr3'Right(2)) after 20 ns ;
--
when 1 =>
correct :=
s_st_arr3_vector(lowb) (
st_arr3'Left(1),st_arr3'Left(2)) =
c_st_arr3_vector_2(highb) (
st_arr3'Right(1),st_arr3'Right(2)) and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2 =>
correct :=
correct and
s_st_arr3_vector(lowb) (
st_arr3'Left(1),st_arr3'Left(2)) =
c_st_arr3_vector_1(highb) (
st_arr3'Right(1),st_arr3'Right(2)) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00157.P3" ,
"Multi inertial transactions occurred on signal " &
"asg with indexed name prefixed by an indexed name on LHS",
correct ) ;
s_st_arr3_vector(lowb) (
st_arr3'Left(1),st_arr3'Left(2)) <=
c_st_arr3_vector_2(highb) (
st_arr3'Right(1),st_arr3'Right(2)) after 10 ns,
c_st_arr3_vector_1(highb) (
st_arr3'Right(1),st_arr3'Right(2)) after 20 ns,
c_st_arr3_vector_2(highb) (
st_arr3'Right(1),st_arr3'Right(2)) after 30 ns,
c_st_arr3_vector_1(highb) (
st_arr3'Right(1),st_arr3'Right(2)) after 40 ns ;
--
when 3 =>
correct :=
s_st_arr3_vector(lowb) (
st_arr3'Left(1),st_arr3'Left(2)) =
c_st_arr3_vector_2(highb) (
st_arr3'Right(1),st_arr3'Right(2)) and
(savtime + 10 ns) = Std.Standard.Now ;
s_st_arr3_vector(lowb) (
st_arr3'Left(1),st_arr3'Left(2)) <=
c_st_arr3_vector_1(highb) (
st_arr3'Right(1),st_arr3'Right(2)) after 5 ns;
--
when 4 =>
correct :=
correct and
s_st_arr3_vector(lowb) (
st_arr3'Left(1),st_arr3'Left(2)) =
c_st_arr3_vector_1(highb) (
st_arr3'Right(1),st_arr3'Right(2)) and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00157" ,
"One inertial transaction occurred on signal " &
"asg with indexed name prefixed by an indexed name on LHS",
correct ) ;
s_st_arr3_vector(lowb) (
st_arr3'Left(1),st_arr3'Left(2)) <= transport
c_st_arr3_vector_1(highb) (
st_arr3'Right(1),st_arr3'Right(2)) after 100 ns;
--
when 5 =>
correct :=
s_st_arr3_vector(lowb) (
st_arr3'Left(1),st_arr3'Left(2)) =
c_st_arr3_vector_1(highb) (
st_arr3'Right(1),st_arr3'Right(2)) and
(savtime + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00157" ,
"Old transactions were removed on signal " &
"asg with indexed name prefixed by an indexed name on LHS",
correct ) ;
s_st_arr3_vector(lowb) (
st_arr3'Left(1),st_arr3'Left(2)) <=
c_st_arr3_vector_2(highb) (
st_arr3'Right(1),st_arr3'Right(2)) after 10 ns,
c_st_arr3_vector_1(highb) (
st_arr3'Right(1),st_arr3'Right(2)) after 20 ns,
c_st_arr3_vector_2(highb) (
st_arr3'Right(1),st_arr3'Right(2)) after 30 ns,
c_st_arr3_vector_1(highb) (
st_arr3'Right(1),st_arr3'Right(2)) after 40 ns ;
--
when 6 =>
correct :=
s_st_arr3_vector(lowb) (
st_arr3'Left(1),st_arr3'Left(2)) =
c_st_arr3_vector_2(highb) (
st_arr3'Right(1),st_arr3'Right(2)) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00157" ,
"One inertial transaction occurred on signal " &
"asg with indexed name prefixed by an indexed name on LHS",
correct ) ;
-- The following will mark last transaction above
s_st_arr3_vector(lowb) (
st_arr3'Left(1),st_arr3'Left(2)) <=
c_st_arr3_vector_1(highb) (
st_arr3'Right(1),st_arr3'Right(2)) after 40 ns;
--
when 7 =>
correct :=
s_st_arr3_vector(lowb) (
st_arr3'Left(1),st_arr3'Left(2)) =
c_st_arr3_vector_1(highb) (
st_arr3'Right(1),st_arr3'Right(2)) and
(savtime + 30 ns) = Std.Standard.Now ;
--
when 8 =>
correct :=
correct and
s_st_arr3_vector(lowb) (
st_arr3'Left(1),st_arr3'Left(2)) =
c_st_arr3_vector_1(highb) (
st_arr3'Right(1),st_arr3'Right(2)) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00157" ,
"Inertial semantics check on a signal " &
"asg with indexed name prefixed by an indexed name on LHS",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00157" ,
"Inertial semantics check on a signal " &
"asg with indexed name prefixed by an indexed name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_st_arr3_vector <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
end Proc3 ;
--
--
end ENT00157 ;
--
architecture ARCH00157 of ENT00157 is
signal s_st_arr1_vector : st_arr1_vector
:= c_st_arr1_vector_1 ;
signal s_st_arr2_vector : st_arr2_vector
:= c_st_arr2_vector_1 ;
signal s_st_arr3_vector : st_arr3_vector
:= c_st_arr3_vector_1 ;
--
begin
P1 :
process
variable counter : integer := 0 ;
variable correct : boolean ;
variable savtime : time ;
begin
Proc1 (
s_st_arr1_vector,
counter,
correct,
savtime,
chk_st_arr1_vector
) ;
wait until (not s_st_arr1_vector'Quiet) and
(savtime /= Std.Standard.Now) ;
--
end process P1 ;
--
PGEN_CHKP_1 :
process ( chk_st_arr1_vector )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P1" ,
"Inertial transactions entirely completed",
chk_st_arr1_vector = 8 ) ;
end if ;
end process PGEN_CHKP_1 ;
--
--
P2 :
process
variable counter : integer := 0 ;
variable correct : boolean ;
variable savtime : time ;
begin
Proc2 (
s_st_arr2_vector,
counter,
correct,
savtime,
chk_st_arr2_vector
) ;
wait until (not s_st_arr2_vector'Quiet) and
(savtime /= Std.Standard.Now) ;
--
end process P2 ;
--
PGEN_CHKP_2 :
process ( chk_st_arr2_vector )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P2" ,
"Inertial transactions entirely completed",
chk_st_arr2_vector = 8 ) ;
end if ;
end process PGEN_CHKP_2 ;
--
--
P3 :
process
variable counter : integer := 0 ;
variable correct : boolean ;
variable savtime : time ;
begin
Proc3 (
s_st_arr3_vector,
counter,
correct,
savtime,
chk_st_arr3_vector
) ;
wait until (not s_st_arr3_vector'Quiet) and
(savtime /= Std.Standard.Now) ;
--
end process P3 ;
--
PGEN_CHKP_3 :
process ( chk_st_arr3_vector )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P3" ,
"Inertial transactions entirely completed",
chk_st_arr3_vector = 8 ) ;
end if ;
end process PGEN_CHKP_3 ;
--
--
--
end ARCH00157 ;
--
entity ENT00157_Test_Bench is
end ENT00157_Test_Bench ;
--
architecture ARCH00157_Test_Bench of ENT00157_Test_Bench is
begin
L1:
block
component UUT
end component ;
for CIS1 : UUT use entity WORK.ENT00157 ( ARCH00157 ) ;
begin
CIS1 : UUT ;
end block L1 ;
end ARCH00157_Test_Bench ;
| gpl-3.0 | f795260742572f80519d635790e7db02 | 0.492112 | 3.573766 | false | false | false | false |
jairov4/accel-oil | solution_virtex5_plb/syn/vhdl/nfa_accept_samples_generic_hw.vhd | 1 | 59,043 | -- ==============================================================
-- RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2014.1
-- Copyright (C) 2014 Xilinx Inc. All rights reserved.
--
-- ===========================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity nfa_accept_samples_generic_hw is
port (
ap_clk : IN STD_LOGIC;
ap_rst : IN STD_LOGIC;
ap_start : IN STD_LOGIC;
ap_done : OUT STD_LOGIC;
ap_idle : OUT STD_LOGIC;
ap_ready : OUT STD_LOGIC;
nfa_initials_buckets_req_din : OUT STD_LOGIC;
nfa_initials_buckets_req_full_n : IN STD_LOGIC;
nfa_initials_buckets_req_write : OUT STD_LOGIC;
nfa_initials_buckets_rsp_empty_n : IN STD_LOGIC;
nfa_initials_buckets_rsp_read : OUT STD_LOGIC;
nfa_initials_buckets_address : OUT STD_LOGIC_VECTOR (31 downto 0);
nfa_initials_buckets_datain : IN STD_LOGIC_VECTOR (63 downto 0);
nfa_initials_buckets_dataout : OUT STD_LOGIC_VECTOR (63 downto 0);
nfa_initials_buckets_size : OUT STD_LOGIC_VECTOR (31 downto 0);
nfa_finals_buckets_req_din : OUT STD_LOGIC;
nfa_finals_buckets_req_full_n : IN STD_LOGIC;
nfa_finals_buckets_req_write : OUT STD_LOGIC;
nfa_finals_buckets_rsp_empty_n : IN STD_LOGIC;
nfa_finals_buckets_rsp_read : OUT STD_LOGIC;
nfa_finals_buckets_address : OUT STD_LOGIC_VECTOR (31 downto 0);
nfa_finals_buckets_datain : IN STD_LOGIC_VECTOR (63 downto 0);
nfa_finals_buckets_dataout : OUT STD_LOGIC_VECTOR (63 downto 0);
nfa_finals_buckets_size : OUT STD_LOGIC_VECTOR (31 downto 0);
nfa_forward_buckets_req_din : OUT STD_LOGIC;
nfa_forward_buckets_req_full_n : IN STD_LOGIC;
nfa_forward_buckets_req_write : OUT STD_LOGIC;
nfa_forward_buckets_rsp_empty_n : IN STD_LOGIC;
nfa_forward_buckets_rsp_read : OUT STD_LOGIC;
nfa_forward_buckets_address : OUT STD_LOGIC_VECTOR (31 downto 0);
nfa_forward_buckets_datain : IN STD_LOGIC_VECTOR (31 downto 0);
nfa_forward_buckets_dataout : OUT STD_LOGIC_VECTOR (31 downto 0);
nfa_forward_buckets_size : OUT STD_LOGIC_VECTOR (31 downto 0);
nfa_symbols : IN STD_LOGIC_VECTOR (7 downto 0);
sample_buffer_req_din : OUT STD_LOGIC;
sample_buffer_req_full_n : IN STD_LOGIC;
sample_buffer_req_write : OUT STD_LOGIC;
sample_buffer_rsp_empty_n : IN STD_LOGIC;
sample_buffer_rsp_read : OUT STD_LOGIC;
sample_buffer_address : OUT STD_LOGIC_VECTOR (31 downto 0);
sample_buffer_datain : IN STD_LOGIC_VECTOR (7 downto 0);
sample_buffer_dataout : OUT STD_LOGIC_VECTOR (7 downto 0);
sample_buffer_size : OUT STD_LOGIC_VECTOR (31 downto 0);
sample_buffer_length : IN STD_LOGIC_VECTOR (31 downto 0);
sample_length : IN STD_LOGIC_VECTOR (15 downto 0);
indices_req_din : OUT STD_LOGIC;
indices_req_full_n : IN STD_LOGIC;
indices_req_write : OUT STD_LOGIC;
indices_rsp_empty_n : IN STD_LOGIC;
indices_rsp_read : OUT STD_LOGIC;
indices_address : OUT STD_LOGIC_VECTOR (31 downto 0);
indices_datain : IN STD_LOGIC_VECTOR (55 downto 0);
indices_dataout : OUT STD_LOGIC_VECTOR (55 downto 0);
indices_size : OUT STD_LOGIC_VECTOR (31 downto 0);
i_size : IN STD_LOGIC_VECTOR (15 downto 0);
begin_index : IN STD_LOGIC_VECTOR (15 downto 0);
begin_sample : IN STD_LOGIC_VECTOR (15 downto 0);
end_index : IN STD_LOGIC_VECTOR (15 downto 0);
end_sample : IN STD_LOGIC_VECTOR (15 downto 0);
stop_on_first : IN STD_LOGIC_VECTOR (0 downto 0);
accept : IN STD_LOGIC_VECTOR (0 downto 0);
ap_return : OUT STD_LOGIC_VECTOR (31 downto 0) );
end;
architecture behav of nfa_accept_samples_generic_hw is
attribute CORE_GENERATION_INFO : STRING;
attribute CORE_GENERATION_INFO of behav : architecture is
"nfa_accept_samples_generic_hw,hls_ip_2014_1,{HLS_INPUT_TYPE=c,HLS_INPUT_FLOAT=0,HLS_INPUT_FIXED=0,HLS_INPUT_PART=xc5vlx50tff1136-3,HLS_INPUT_CLOCK=10.000000,HLS_INPUT_ARCH=others,HLS_SYN_CLOCK=7.000000,HLS_SYN_LAT=-1,HLS_SYN_TPT=none,HLS_SYN_MEM=0,HLS_SYN_DSP=0,HLS_SYN_FF=0,HLS_SYN_LUT=0}";
constant ap_const_logic_1 : STD_LOGIC := '1';
constant ap_const_logic_0 : STD_LOGIC := '0';
constant ap_ST_st1_fsm_0 : STD_LOGIC_VECTOR (3 downto 0) := "0000";
constant ap_ST_st2_fsm_1 : STD_LOGIC_VECTOR (3 downto 0) := "0001";
constant ap_ST_st3_fsm_2 : STD_LOGIC_VECTOR (3 downto 0) := "0010";
constant ap_ST_st4_fsm_3 : STD_LOGIC_VECTOR (3 downto 0) := "0011";
constant ap_ST_st5_fsm_4 : STD_LOGIC_VECTOR (3 downto 0) := "0100";
constant ap_ST_st6_fsm_5 : STD_LOGIC_VECTOR (3 downto 0) := "0101";
constant ap_ST_st7_fsm_6 : STD_LOGIC_VECTOR (3 downto 0) := "0110";
constant ap_ST_st8_fsm_7 : STD_LOGIC_VECTOR (3 downto 0) := "0111";
constant ap_ST_st9_fsm_8 : STD_LOGIC_VECTOR (3 downto 0) := "1000";
constant ap_ST_st10_fsm_9 : STD_LOGIC_VECTOR (3 downto 0) := "1001";
constant ap_const_lv1_0 : STD_LOGIC_VECTOR (0 downto 0) := "0";
constant ap_const_lv5_0 : STD_LOGIC_VECTOR (4 downto 0) := "00000";
constant ap_const_lv16_1 : STD_LOGIC_VECTOR (15 downto 0) := "0000000000000001";
constant ap_const_lv16_0 : STD_LOGIC_VECTOR (15 downto 0) := "0000000000000000";
constant ap_const_lv32_4 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000100";
constant ap_const_lv5_1 : STD_LOGIC_VECTOR (4 downto 0) := "00001";
signal ap_CS_fsm : STD_LOGIC_VECTOR (3 downto 0) := "0000";
signal units_fu_334_p2 : STD_LOGIC_VECTOR (4 downto 0);
signal units_reg_499 : STD_LOGIC_VECTOR (4 downto 0);
signal i_index_load_reg_504 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_3_fu_326_p3 : STD_LOGIC_VECTOR (0 downto 0);
signal i_sample_load_reg_510 : STD_LOGIC_VECTOR (15 downto 0);
signal finished_3_fu_358_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal grp_nfa_accept_sample_multi_fu_268_ap_return : STD_LOGIC_VECTOR (0 downto 0);
signal stop_on_first_meet_reg_521 : STD_LOGIC_VECTOR (0 downto 0);
signal grp_nfa_accept_sample_multi_fu_268_ap_done : STD_LOGIC;
signal k_2_fu_398_p2 : STD_LOGIC_VECTOR (4 downto 0);
signal k_2_reg_532 : STD_LOGIC_VECTOR (4 downto 0);
signal exitcond_fu_392_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_5_fu_412_p3 : STD_LOGIC_VECTOR (15 downto 0);
signal finished_2_reg_233 : STD_LOGIC_VECTOR (0 downto 0);
signal result_address0 : STD_LOGIC_VECTOR (3 downto 0);
signal result_ce0 : STD_LOGIC;
signal result_we0 : STD_LOGIC;
signal result_d0 : STD_LOGIC_VECTOR (0 downto 0);
signal result_q0 : STD_LOGIC_VECTOR (0 downto 0);
signal start_indices_address0 : STD_LOGIC_VECTOR (3 downto 0);
signal start_indices_ce0 : STD_LOGIC;
signal start_indices_we0 : STD_LOGIC;
signal start_indices_d0 : STD_LOGIC_VECTOR (31 downto 0);
signal start_indices_q0 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_nfa_accept_sample_multi_fu_268_ap_start : STD_LOGIC;
signal grp_nfa_accept_sample_multi_fu_268_ap_idle : STD_LOGIC;
signal grp_nfa_accept_sample_multi_fu_268_ap_ready : STD_LOGIC;
signal grp_nfa_accept_sample_multi_fu_268_nfa_initials_buckets_req_din : STD_LOGIC;
signal grp_nfa_accept_sample_multi_fu_268_nfa_initials_buckets_req_full_n : STD_LOGIC;
signal grp_nfa_accept_sample_multi_fu_268_nfa_initials_buckets_req_write : STD_LOGIC;
signal grp_nfa_accept_sample_multi_fu_268_nfa_initials_buckets_rsp_empty_n : STD_LOGIC;
signal grp_nfa_accept_sample_multi_fu_268_nfa_initials_buckets_rsp_read : STD_LOGIC;
signal grp_nfa_accept_sample_multi_fu_268_nfa_initials_buckets_address : STD_LOGIC_VECTOR (31 downto 0);
signal grp_nfa_accept_sample_multi_fu_268_nfa_initials_buckets_datain : STD_LOGIC_VECTOR (63 downto 0);
signal grp_nfa_accept_sample_multi_fu_268_nfa_initials_buckets_dataout : STD_LOGIC_VECTOR (63 downto 0);
signal grp_nfa_accept_sample_multi_fu_268_nfa_initials_buckets_size : STD_LOGIC_VECTOR (31 downto 0);
signal grp_nfa_accept_sample_multi_fu_268_nfa_finals_buckets_req_din : STD_LOGIC;
signal grp_nfa_accept_sample_multi_fu_268_nfa_finals_buckets_req_full_n : STD_LOGIC;
signal grp_nfa_accept_sample_multi_fu_268_nfa_finals_buckets_req_write : STD_LOGIC;
signal grp_nfa_accept_sample_multi_fu_268_nfa_finals_buckets_rsp_empty_n : STD_LOGIC;
signal grp_nfa_accept_sample_multi_fu_268_nfa_finals_buckets_rsp_read : STD_LOGIC;
signal grp_nfa_accept_sample_multi_fu_268_nfa_finals_buckets_address : STD_LOGIC_VECTOR (31 downto 0);
signal grp_nfa_accept_sample_multi_fu_268_nfa_finals_buckets_datain : STD_LOGIC_VECTOR (63 downto 0);
signal grp_nfa_accept_sample_multi_fu_268_nfa_finals_buckets_dataout : STD_LOGIC_VECTOR (63 downto 0);
signal grp_nfa_accept_sample_multi_fu_268_nfa_finals_buckets_size : STD_LOGIC_VECTOR (31 downto 0);
signal grp_nfa_accept_sample_multi_fu_268_nfa_forward_buckets_req_din : STD_LOGIC;
signal grp_nfa_accept_sample_multi_fu_268_nfa_forward_buckets_req_full_n : STD_LOGIC;
signal grp_nfa_accept_sample_multi_fu_268_nfa_forward_buckets_req_write : STD_LOGIC;
signal grp_nfa_accept_sample_multi_fu_268_nfa_forward_buckets_rsp_empty_n : STD_LOGIC;
signal grp_nfa_accept_sample_multi_fu_268_nfa_forward_buckets_rsp_read : STD_LOGIC;
signal grp_nfa_accept_sample_multi_fu_268_nfa_forward_buckets_address : STD_LOGIC_VECTOR (31 downto 0);
signal grp_nfa_accept_sample_multi_fu_268_nfa_forward_buckets_datain : STD_LOGIC_VECTOR (31 downto 0);
signal grp_nfa_accept_sample_multi_fu_268_nfa_forward_buckets_dataout : STD_LOGIC_VECTOR (31 downto 0);
signal grp_nfa_accept_sample_multi_fu_268_nfa_forward_buckets_size : STD_LOGIC_VECTOR (31 downto 0);
signal grp_nfa_accept_sample_multi_fu_268_nfa_symbols : STD_LOGIC_VECTOR (7 downto 0);
signal grp_nfa_accept_sample_multi_fu_268_sample_req_din : STD_LOGIC;
signal grp_nfa_accept_sample_multi_fu_268_sample_req_full_n : STD_LOGIC;
signal grp_nfa_accept_sample_multi_fu_268_sample_req_write : STD_LOGIC;
signal grp_nfa_accept_sample_multi_fu_268_sample_rsp_empty_n : STD_LOGIC;
signal grp_nfa_accept_sample_multi_fu_268_sample_rsp_read : STD_LOGIC;
signal grp_nfa_accept_sample_multi_fu_268_sample_address : STD_LOGIC_VECTOR (31 downto 0);
signal grp_nfa_accept_sample_multi_fu_268_sample_datain : STD_LOGIC_VECTOR (7 downto 0);
signal grp_nfa_accept_sample_multi_fu_268_sample_dataout : STD_LOGIC_VECTOR (7 downto 0);
signal grp_nfa_accept_sample_multi_fu_268_sample_size : STD_LOGIC_VECTOR (31 downto 0);
signal grp_nfa_accept_sample_multi_fu_268_length_r : STD_LOGIC_VECTOR (15 downto 0);
signal grp_nfa_accept_sample_multi_fu_268_start_indices_address0 : STD_LOGIC_VECTOR (3 downto 0);
signal grp_nfa_accept_sample_multi_fu_268_start_indices_ce0 : STD_LOGIC;
signal grp_nfa_accept_sample_multi_fu_268_start_indices_q0 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_nfa_accept_sample_multi_fu_268_stop_on_first : STD_LOGIC_VECTOR (0 downto 0);
signal grp_nfa_accept_sample_multi_fu_268_accept : STD_LOGIC_VECTOR (0 downto 0);
signal grp_nfa_accept_sample_multi_fu_268_units : STD_LOGIC_VECTOR (4 downto 0);
signal grp_nfa_accept_sample_multi_fu_268_result_address0 : STD_LOGIC_VECTOR (3 downto 0);
signal grp_nfa_accept_sample_multi_fu_268_result_ce0 : STD_LOGIC;
signal grp_nfa_accept_sample_multi_fu_268_result_we0 : STD_LOGIC;
signal grp_nfa_accept_sample_multi_fu_268_result_d0 : STD_LOGIC_VECTOR (0 downto 0);
signal grp_nfa_accept_sample_multi_fu_268_result_q0 : STD_LOGIC_VECTOR (0 downto 0);
signal grp_sample_iterator_next_fu_289_ap_start : STD_LOGIC;
signal grp_sample_iterator_next_fu_289_ap_done : STD_LOGIC;
signal grp_sample_iterator_next_fu_289_ap_idle : STD_LOGIC;
signal grp_sample_iterator_next_fu_289_ap_ready : STD_LOGIC;
signal grp_sample_iterator_next_fu_289_indices_req_din : STD_LOGIC;
signal grp_sample_iterator_next_fu_289_indices_req_full_n : STD_LOGIC;
signal grp_sample_iterator_next_fu_289_indices_req_write : STD_LOGIC;
signal grp_sample_iterator_next_fu_289_indices_rsp_empty_n : STD_LOGIC;
signal grp_sample_iterator_next_fu_289_indices_rsp_read : STD_LOGIC;
signal grp_sample_iterator_next_fu_289_indices_address : STD_LOGIC_VECTOR (31 downto 0);
signal grp_sample_iterator_next_fu_289_indices_datain : STD_LOGIC_VECTOR (55 downto 0);
signal grp_sample_iterator_next_fu_289_indices_dataout : STD_LOGIC_VECTOR (55 downto 0);
signal grp_sample_iterator_next_fu_289_indices_size : STD_LOGIC_VECTOR (31 downto 0);
signal grp_sample_iterator_next_fu_289_i_index : STD_LOGIC_VECTOR (15 downto 0);
signal grp_sample_iterator_next_fu_289_i_sample : STD_LOGIC_VECTOR (15 downto 0);
signal grp_sample_iterator_next_fu_289_ap_return_0 : STD_LOGIC_VECTOR (15 downto 0);
signal grp_sample_iterator_next_fu_289_ap_return_1 : STD_LOGIC_VECTOR (15 downto 0);
signal grp_sample_iterator_get_offset_fu_297_ap_start : STD_LOGIC;
signal grp_sample_iterator_get_offset_fu_297_ap_done : STD_LOGIC;
signal grp_sample_iterator_get_offset_fu_297_ap_idle : STD_LOGIC;
signal grp_sample_iterator_get_offset_fu_297_ap_ready : STD_LOGIC;
signal grp_sample_iterator_get_offset_fu_297_i_index : STD_LOGIC_VECTOR (15 downto 0);
signal grp_sample_iterator_get_offset_fu_297_i_sample : STD_LOGIC_VECTOR (15 downto 0);
signal grp_sample_iterator_get_offset_fu_297_indices_req_din : STD_LOGIC;
signal grp_sample_iterator_get_offset_fu_297_indices_req_full_n : STD_LOGIC;
signal grp_sample_iterator_get_offset_fu_297_indices_req_write : STD_LOGIC;
signal grp_sample_iterator_get_offset_fu_297_indices_rsp_empty_n : STD_LOGIC;
signal grp_sample_iterator_get_offset_fu_297_indices_rsp_read : STD_LOGIC;
signal grp_sample_iterator_get_offset_fu_297_indices_address : STD_LOGIC_VECTOR (31 downto 0);
signal grp_sample_iterator_get_offset_fu_297_indices_datain : STD_LOGIC_VECTOR (55 downto 0);
signal grp_sample_iterator_get_offset_fu_297_indices_dataout : STD_LOGIC_VECTOR (55 downto 0);
signal grp_sample_iterator_get_offset_fu_297_indices_size : STD_LOGIC_VECTOR (31 downto 0);
signal grp_sample_iterator_get_offset_fu_297_sample_buffer_size : STD_LOGIC_VECTOR (31 downto 0);
signal grp_sample_iterator_get_offset_fu_297_sample_length : STD_LOGIC_VECTOR (15 downto 0);
signal grp_sample_iterator_get_offset_fu_297_ap_return : STD_LOGIC_VECTOR (31 downto 0);
signal finished_reg_196 : STD_LOGIC_VECTOR (0 downto 0);
signal indvars_iv_reg_208 : STD_LOGIC_VECTOR (4 downto 0);
signal finished_1_reg_220 : STD_LOGIC_VECTOR (0 downto 0);
signal k_1_reg_245 : STD_LOGIC_VECTOR (4 downto 0);
signal brmerge_demorgan_fu_387_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal p_0_reg_256 : STD_LOGIC_VECTOR (15 downto 0);
signal grp_nfa_accept_sample_multi_fu_268_ap_start_ap_start_reg : STD_LOGIC := '0';
signal grp_sample_iterator_next_fu_289_ap_start_ap_start_reg : STD_LOGIC := '0';
signal grp_sample_iterator_get_offset_fu_297_ap_start_ap_start_reg : STD_LOGIC := '0';
signal tmp_1_fu_364_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_2_fu_404_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal c_fu_106 : STD_LOGIC_VECTOR (15 downto 0);
signal p_c_1_fu_425_p3 : STD_LOGIC_VECTOR (15 downto 0);
signal i_index_fu_110 : STD_LOGIC_VECTOR (15 downto 0);
signal i_sample_fu_114 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_i_fu_348_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_i_16_fu_353_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_3_cast_fu_409_p1 : STD_LOGIC_VECTOR (15 downto 0);
signal c_1_fu_419_p2 : STD_LOGIC_VECTOR (15 downto 0);
signal ap_NS_fsm : STD_LOGIC_VECTOR (3 downto 0);
signal ap_sig_bdd_287 : BOOLEAN;
component nfa_accept_sample_multi IS
port (
ap_clk : IN STD_LOGIC;
ap_rst : IN STD_LOGIC;
ap_start : IN STD_LOGIC;
ap_done : OUT STD_LOGIC;
ap_idle : OUT STD_LOGIC;
ap_ready : OUT STD_LOGIC;
nfa_initials_buckets_req_din : OUT STD_LOGIC;
nfa_initials_buckets_req_full_n : IN STD_LOGIC;
nfa_initials_buckets_req_write : OUT STD_LOGIC;
nfa_initials_buckets_rsp_empty_n : IN STD_LOGIC;
nfa_initials_buckets_rsp_read : OUT STD_LOGIC;
nfa_initials_buckets_address : OUT STD_LOGIC_VECTOR (31 downto 0);
nfa_initials_buckets_datain : IN STD_LOGIC_VECTOR (63 downto 0);
nfa_initials_buckets_dataout : OUT STD_LOGIC_VECTOR (63 downto 0);
nfa_initials_buckets_size : OUT STD_LOGIC_VECTOR (31 downto 0);
nfa_finals_buckets_req_din : OUT STD_LOGIC;
nfa_finals_buckets_req_full_n : IN STD_LOGIC;
nfa_finals_buckets_req_write : OUT STD_LOGIC;
nfa_finals_buckets_rsp_empty_n : IN STD_LOGIC;
nfa_finals_buckets_rsp_read : OUT STD_LOGIC;
nfa_finals_buckets_address : OUT STD_LOGIC_VECTOR (31 downto 0);
nfa_finals_buckets_datain : IN STD_LOGIC_VECTOR (63 downto 0);
nfa_finals_buckets_dataout : OUT STD_LOGIC_VECTOR (63 downto 0);
nfa_finals_buckets_size : OUT STD_LOGIC_VECTOR (31 downto 0);
nfa_forward_buckets_req_din : OUT STD_LOGIC;
nfa_forward_buckets_req_full_n : IN STD_LOGIC;
nfa_forward_buckets_req_write : OUT STD_LOGIC;
nfa_forward_buckets_rsp_empty_n : IN STD_LOGIC;
nfa_forward_buckets_rsp_read : OUT STD_LOGIC;
nfa_forward_buckets_address : OUT STD_LOGIC_VECTOR (31 downto 0);
nfa_forward_buckets_datain : IN STD_LOGIC_VECTOR (31 downto 0);
nfa_forward_buckets_dataout : OUT STD_LOGIC_VECTOR (31 downto 0);
nfa_forward_buckets_size : OUT STD_LOGIC_VECTOR (31 downto 0);
nfa_symbols : IN STD_LOGIC_VECTOR (7 downto 0);
sample_req_din : OUT STD_LOGIC;
sample_req_full_n : IN STD_LOGIC;
sample_req_write : OUT STD_LOGIC;
sample_rsp_empty_n : IN STD_LOGIC;
sample_rsp_read : OUT STD_LOGIC;
sample_address : OUT STD_LOGIC_VECTOR (31 downto 0);
sample_datain : IN STD_LOGIC_VECTOR (7 downto 0);
sample_dataout : OUT STD_LOGIC_VECTOR (7 downto 0);
sample_size : OUT STD_LOGIC_VECTOR (31 downto 0);
length_r : IN STD_LOGIC_VECTOR (15 downto 0);
start_indices_address0 : OUT STD_LOGIC_VECTOR (3 downto 0);
start_indices_ce0 : OUT STD_LOGIC;
start_indices_q0 : IN STD_LOGIC_VECTOR (31 downto 0);
stop_on_first : IN STD_LOGIC_VECTOR (0 downto 0);
accept : IN STD_LOGIC_VECTOR (0 downto 0);
units : IN STD_LOGIC_VECTOR (4 downto 0);
result_address0 : OUT STD_LOGIC_VECTOR (3 downto 0);
result_ce0 : OUT STD_LOGIC;
result_we0 : OUT STD_LOGIC;
result_d0 : OUT STD_LOGIC_VECTOR (0 downto 0);
result_q0 : IN STD_LOGIC_VECTOR (0 downto 0);
ap_return : OUT STD_LOGIC_VECTOR (0 downto 0) );
end component;
component sample_iterator_next IS
port (
ap_clk : IN STD_LOGIC;
ap_rst : IN STD_LOGIC;
ap_start : IN STD_LOGIC;
ap_done : OUT STD_LOGIC;
ap_idle : OUT STD_LOGIC;
ap_ready : OUT STD_LOGIC;
indices_req_din : OUT STD_LOGIC;
indices_req_full_n : IN STD_LOGIC;
indices_req_write : OUT STD_LOGIC;
indices_rsp_empty_n : IN STD_LOGIC;
indices_rsp_read : OUT STD_LOGIC;
indices_address : OUT STD_LOGIC_VECTOR (31 downto 0);
indices_datain : IN STD_LOGIC_VECTOR (55 downto 0);
indices_dataout : OUT STD_LOGIC_VECTOR (55 downto 0);
indices_size : OUT STD_LOGIC_VECTOR (31 downto 0);
i_index : IN STD_LOGIC_VECTOR (15 downto 0);
i_sample : IN STD_LOGIC_VECTOR (15 downto 0);
ap_return_0 : OUT STD_LOGIC_VECTOR (15 downto 0);
ap_return_1 : OUT STD_LOGIC_VECTOR (15 downto 0) );
end component;
component sample_iterator_get_offset IS
port (
ap_clk : IN STD_LOGIC;
ap_rst : IN STD_LOGIC;
ap_start : IN STD_LOGIC;
ap_done : OUT STD_LOGIC;
ap_idle : OUT STD_LOGIC;
ap_ready : OUT STD_LOGIC;
i_index : IN STD_LOGIC_VECTOR (15 downto 0);
i_sample : IN STD_LOGIC_VECTOR (15 downto 0);
indices_req_din : OUT STD_LOGIC;
indices_req_full_n : IN STD_LOGIC;
indices_req_write : OUT STD_LOGIC;
indices_rsp_empty_n : IN STD_LOGIC;
indices_rsp_read : OUT STD_LOGIC;
indices_address : OUT STD_LOGIC_VECTOR (31 downto 0);
indices_datain : IN STD_LOGIC_VECTOR (55 downto 0);
indices_dataout : OUT STD_LOGIC_VECTOR (55 downto 0);
indices_size : OUT STD_LOGIC_VECTOR (31 downto 0);
sample_buffer_size : IN STD_LOGIC_VECTOR (31 downto 0);
sample_length : IN STD_LOGIC_VECTOR (15 downto 0);
ap_return : OUT STD_LOGIC_VECTOR (31 downto 0) );
end component;
component nfa_accept_samples_generic_hw_result IS
generic (
DataWidth : INTEGER;
AddressRange : INTEGER;
AddressWidth : INTEGER );
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
address0 : IN STD_LOGIC_VECTOR (3 downto 0);
ce0 : IN STD_LOGIC;
we0 : IN STD_LOGIC;
d0 : IN STD_LOGIC_VECTOR (0 downto 0);
q0 : OUT STD_LOGIC_VECTOR (0 downto 0) );
end component;
component nfa_accept_samples_generic_hw_start_indices IS
generic (
DataWidth : INTEGER;
AddressRange : INTEGER;
AddressWidth : INTEGER );
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
address0 : IN STD_LOGIC_VECTOR (3 downto 0);
ce0 : IN STD_LOGIC;
we0 : IN STD_LOGIC;
d0 : IN STD_LOGIC_VECTOR (31 downto 0);
q0 : OUT STD_LOGIC_VECTOR (31 downto 0) );
end component;
begin
result_U : component nfa_accept_samples_generic_hw_result
generic map (
DataWidth => 1,
AddressRange => 16,
AddressWidth => 4)
port map (
clk => ap_clk,
reset => ap_rst,
address0 => result_address0,
ce0 => result_ce0,
we0 => result_we0,
d0 => result_d0,
q0 => result_q0);
start_indices_U : component nfa_accept_samples_generic_hw_start_indices
generic map (
DataWidth => 32,
AddressRange => 16,
AddressWidth => 4)
port map (
clk => ap_clk,
reset => ap_rst,
address0 => start_indices_address0,
ce0 => start_indices_ce0,
we0 => start_indices_we0,
d0 => start_indices_d0,
q0 => start_indices_q0);
grp_nfa_accept_sample_multi_fu_268 : component nfa_accept_sample_multi
port map (
ap_clk => ap_clk,
ap_rst => ap_rst,
ap_start => grp_nfa_accept_sample_multi_fu_268_ap_start,
ap_done => grp_nfa_accept_sample_multi_fu_268_ap_done,
ap_idle => grp_nfa_accept_sample_multi_fu_268_ap_idle,
ap_ready => grp_nfa_accept_sample_multi_fu_268_ap_ready,
nfa_initials_buckets_req_din => grp_nfa_accept_sample_multi_fu_268_nfa_initials_buckets_req_din,
nfa_initials_buckets_req_full_n => grp_nfa_accept_sample_multi_fu_268_nfa_initials_buckets_req_full_n,
nfa_initials_buckets_req_write => grp_nfa_accept_sample_multi_fu_268_nfa_initials_buckets_req_write,
nfa_initials_buckets_rsp_empty_n => grp_nfa_accept_sample_multi_fu_268_nfa_initials_buckets_rsp_empty_n,
nfa_initials_buckets_rsp_read => grp_nfa_accept_sample_multi_fu_268_nfa_initials_buckets_rsp_read,
nfa_initials_buckets_address => grp_nfa_accept_sample_multi_fu_268_nfa_initials_buckets_address,
nfa_initials_buckets_datain => grp_nfa_accept_sample_multi_fu_268_nfa_initials_buckets_datain,
nfa_initials_buckets_dataout => grp_nfa_accept_sample_multi_fu_268_nfa_initials_buckets_dataout,
nfa_initials_buckets_size => grp_nfa_accept_sample_multi_fu_268_nfa_initials_buckets_size,
nfa_finals_buckets_req_din => grp_nfa_accept_sample_multi_fu_268_nfa_finals_buckets_req_din,
nfa_finals_buckets_req_full_n => grp_nfa_accept_sample_multi_fu_268_nfa_finals_buckets_req_full_n,
nfa_finals_buckets_req_write => grp_nfa_accept_sample_multi_fu_268_nfa_finals_buckets_req_write,
nfa_finals_buckets_rsp_empty_n => grp_nfa_accept_sample_multi_fu_268_nfa_finals_buckets_rsp_empty_n,
nfa_finals_buckets_rsp_read => grp_nfa_accept_sample_multi_fu_268_nfa_finals_buckets_rsp_read,
nfa_finals_buckets_address => grp_nfa_accept_sample_multi_fu_268_nfa_finals_buckets_address,
nfa_finals_buckets_datain => grp_nfa_accept_sample_multi_fu_268_nfa_finals_buckets_datain,
nfa_finals_buckets_dataout => grp_nfa_accept_sample_multi_fu_268_nfa_finals_buckets_dataout,
nfa_finals_buckets_size => grp_nfa_accept_sample_multi_fu_268_nfa_finals_buckets_size,
nfa_forward_buckets_req_din => grp_nfa_accept_sample_multi_fu_268_nfa_forward_buckets_req_din,
nfa_forward_buckets_req_full_n => grp_nfa_accept_sample_multi_fu_268_nfa_forward_buckets_req_full_n,
nfa_forward_buckets_req_write => grp_nfa_accept_sample_multi_fu_268_nfa_forward_buckets_req_write,
nfa_forward_buckets_rsp_empty_n => grp_nfa_accept_sample_multi_fu_268_nfa_forward_buckets_rsp_empty_n,
nfa_forward_buckets_rsp_read => grp_nfa_accept_sample_multi_fu_268_nfa_forward_buckets_rsp_read,
nfa_forward_buckets_address => grp_nfa_accept_sample_multi_fu_268_nfa_forward_buckets_address,
nfa_forward_buckets_datain => grp_nfa_accept_sample_multi_fu_268_nfa_forward_buckets_datain,
nfa_forward_buckets_dataout => grp_nfa_accept_sample_multi_fu_268_nfa_forward_buckets_dataout,
nfa_forward_buckets_size => grp_nfa_accept_sample_multi_fu_268_nfa_forward_buckets_size,
nfa_symbols => grp_nfa_accept_sample_multi_fu_268_nfa_symbols,
sample_req_din => grp_nfa_accept_sample_multi_fu_268_sample_req_din,
sample_req_full_n => grp_nfa_accept_sample_multi_fu_268_sample_req_full_n,
sample_req_write => grp_nfa_accept_sample_multi_fu_268_sample_req_write,
sample_rsp_empty_n => grp_nfa_accept_sample_multi_fu_268_sample_rsp_empty_n,
sample_rsp_read => grp_nfa_accept_sample_multi_fu_268_sample_rsp_read,
sample_address => grp_nfa_accept_sample_multi_fu_268_sample_address,
sample_datain => grp_nfa_accept_sample_multi_fu_268_sample_datain,
sample_dataout => grp_nfa_accept_sample_multi_fu_268_sample_dataout,
sample_size => grp_nfa_accept_sample_multi_fu_268_sample_size,
length_r => grp_nfa_accept_sample_multi_fu_268_length_r,
start_indices_address0 => grp_nfa_accept_sample_multi_fu_268_start_indices_address0,
start_indices_ce0 => grp_nfa_accept_sample_multi_fu_268_start_indices_ce0,
start_indices_q0 => grp_nfa_accept_sample_multi_fu_268_start_indices_q0,
stop_on_first => grp_nfa_accept_sample_multi_fu_268_stop_on_first,
accept => grp_nfa_accept_sample_multi_fu_268_accept,
units => grp_nfa_accept_sample_multi_fu_268_units,
result_address0 => grp_nfa_accept_sample_multi_fu_268_result_address0,
result_ce0 => grp_nfa_accept_sample_multi_fu_268_result_ce0,
result_we0 => grp_nfa_accept_sample_multi_fu_268_result_we0,
result_d0 => grp_nfa_accept_sample_multi_fu_268_result_d0,
result_q0 => grp_nfa_accept_sample_multi_fu_268_result_q0,
ap_return => grp_nfa_accept_sample_multi_fu_268_ap_return);
grp_sample_iterator_next_fu_289 : component sample_iterator_next
port map (
ap_clk => ap_clk,
ap_rst => ap_rst,
ap_start => grp_sample_iterator_next_fu_289_ap_start,
ap_done => grp_sample_iterator_next_fu_289_ap_done,
ap_idle => grp_sample_iterator_next_fu_289_ap_idle,
ap_ready => grp_sample_iterator_next_fu_289_ap_ready,
indices_req_din => grp_sample_iterator_next_fu_289_indices_req_din,
indices_req_full_n => grp_sample_iterator_next_fu_289_indices_req_full_n,
indices_req_write => grp_sample_iterator_next_fu_289_indices_req_write,
indices_rsp_empty_n => grp_sample_iterator_next_fu_289_indices_rsp_empty_n,
indices_rsp_read => grp_sample_iterator_next_fu_289_indices_rsp_read,
indices_address => grp_sample_iterator_next_fu_289_indices_address,
indices_datain => grp_sample_iterator_next_fu_289_indices_datain,
indices_dataout => grp_sample_iterator_next_fu_289_indices_dataout,
indices_size => grp_sample_iterator_next_fu_289_indices_size,
i_index => grp_sample_iterator_next_fu_289_i_index,
i_sample => grp_sample_iterator_next_fu_289_i_sample,
ap_return_0 => grp_sample_iterator_next_fu_289_ap_return_0,
ap_return_1 => grp_sample_iterator_next_fu_289_ap_return_1);
grp_sample_iterator_get_offset_fu_297 : component sample_iterator_get_offset
port map (
ap_clk => ap_clk,
ap_rst => ap_rst,
ap_start => grp_sample_iterator_get_offset_fu_297_ap_start,
ap_done => grp_sample_iterator_get_offset_fu_297_ap_done,
ap_idle => grp_sample_iterator_get_offset_fu_297_ap_idle,
ap_ready => grp_sample_iterator_get_offset_fu_297_ap_ready,
i_index => grp_sample_iterator_get_offset_fu_297_i_index,
i_sample => grp_sample_iterator_get_offset_fu_297_i_sample,
indices_req_din => grp_sample_iterator_get_offset_fu_297_indices_req_din,
indices_req_full_n => grp_sample_iterator_get_offset_fu_297_indices_req_full_n,
indices_req_write => grp_sample_iterator_get_offset_fu_297_indices_req_write,
indices_rsp_empty_n => grp_sample_iterator_get_offset_fu_297_indices_rsp_empty_n,
indices_rsp_read => grp_sample_iterator_get_offset_fu_297_indices_rsp_read,
indices_address => grp_sample_iterator_get_offset_fu_297_indices_address,
indices_datain => grp_sample_iterator_get_offset_fu_297_indices_datain,
indices_dataout => grp_sample_iterator_get_offset_fu_297_indices_dataout,
indices_size => grp_sample_iterator_get_offset_fu_297_indices_size,
sample_buffer_size => grp_sample_iterator_get_offset_fu_297_sample_buffer_size,
sample_length => grp_sample_iterator_get_offset_fu_297_sample_length,
ap_return => grp_sample_iterator_get_offset_fu_297_ap_return);
-- the current state (ap_CS_fsm) of the state machine. --
ap_CS_fsm_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_CS_fsm <= ap_ST_st1_fsm_0;
else
ap_CS_fsm <= ap_NS_fsm;
end if;
end if;
end process;
-- grp_nfa_accept_sample_multi_fu_268_ap_start_ap_start_reg assign process. --
grp_nfa_accept_sample_multi_fu_268_ap_start_ap_start_reg_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
grp_nfa_accept_sample_multi_fu_268_ap_start_ap_start_reg <= ap_const_logic_0;
else
if (((ap_ST_st3_fsm_2 = ap_CS_fsm) and (not((tmp_3_fu_326_p3 = ap_const_lv1_0)) or not((ap_const_lv1_0 = finished_3_fu_358_p2))))) then
grp_nfa_accept_sample_multi_fu_268_ap_start_ap_start_reg <= ap_const_logic_1;
elsif ((ap_const_logic_1 = grp_nfa_accept_sample_multi_fu_268_ap_ready)) then
grp_nfa_accept_sample_multi_fu_268_ap_start_ap_start_reg <= ap_const_logic_0;
end if;
end if;
end if;
end process;
-- grp_sample_iterator_get_offset_fu_297_ap_start_ap_start_reg assign process. --
grp_sample_iterator_get_offset_fu_297_ap_start_ap_start_reg_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
grp_sample_iterator_get_offset_fu_297_ap_start_ap_start_reg <= ap_const_logic_0;
else
if (((ap_ST_st3_fsm_2 = ap_CS_fsm) and (tmp_3_fu_326_p3 = ap_const_lv1_0) and (ap_const_lv1_0 = finished_3_fu_358_p2))) then
grp_sample_iterator_get_offset_fu_297_ap_start_ap_start_reg <= ap_const_logic_1;
elsif ((ap_const_logic_1 = grp_sample_iterator_get_offset_fu_297_ap_ready)) then
grp_sample_iterator_get_offset_fu_297_ap_start_ap_start_reg <= ap_const_logic_0;
end if;
end if;
end if;
end process;
-- grp_sample_iterator_next_fu_289_ap_start_ap_start_reg assign process. --
grp_sample_iterator_next_fu_289_ap_start_ap_start_reg_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
grp_sample_iterator_next_fu_289_ap_start_ap_start_reg <= ap_const_logic_0;
else
if ((ap_ST_st5_fsm_4 = ap_CS_fsm)) then
grp_sample_iterator_next_fu_289_ap_start_ap_start_reg <= ap_const_logic_1;
elsif ((ap_const_logic_1 = grp_sample_iterator_next_fu_289_ap_ready)) then
grp_sample_iterator_next_fu_289_ap_start_ap_start_reg <= ap_const_logic_0;
end if;
end if;
end if;
end process;
-- c_fu_106 assign process. --
c_fu_106_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_ST_st9_fsm_8 = ap_CS_fsm)) then
c_fu_106 <= p_c_1_fu_425_p3;
elsif (((ap_ST_st1_fsm_0 = ap_CS_fsm) and not((ap_start = ap_const_logic_0)))) then
c_fu_106 <= ap_const_lv16_0;
end if;
end if;
end process;
-- finished_1_reg_220 assign process. --
finished_1_reg_220_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ST_st6_fsm_5 = ap_CS_fsm) and not((ap_const_logic_0 = grp_sample_iterator_next_fu_289_ap_done)))) then
finished_1_reg_220 <= ap_const_lv1_0;
elsif ((ap_ST_st2_fsm_1 = ap_CS_fsm)) then
finished_1_reg_220 <= finished_reg_196;
end if;
end if;
end process;
-- finished_2_reg_233 assign process. --
finished_2_reg_233_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_ST_st3_fsm_2 = ap_CS_fsm)) then
if (ap_sig_bdd_287) then
finished_2_reg_233 <= finished_3_fu_358_p2;
elsif (not((tmp_3_fu_326_p3 = ap_const_lv1_0))) then
finished_2_reg_233 <= finished_1_reg_220;
end if;
end if;
end if;
end process;
-- finished_reg_196 assign process. --
finished_reg_196_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ST_st8_fsm_7 = ap_CS_fsm) and not((ap_const_lv1_0 = exitcond_fu_392_p2)) and (ap_const_lv1_0 = finished_2_reg_233))) then
finished_reg_196 <= finished_2_reg_233;
elsif (((ap_ST_st1_fsm_0 = ap_CS_fsm) and not((ap_start = ap_const_logic_0)))) then
finished_reg_196 <= ap_const_lv1_0;
end if;
end if;
end process;
-- i_index_fu_110 assign process. --
i_index_fu_110_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ST_st6_fsm_5 = ap_CS_fsm) and not((ap_const_logic_0 = grp_sample_iterator_next_fu_289_ap_done)))) then
i_index_fu_110 <= grp_sample_iterator_next_fu_289_ap_return_0;
elsif (((ap_ST_st1_fsm_0 = ap_CS_fsm) and not((ap_start = ap_const_logic_0)))) then
i_index_fu_110 <= begin_index;
end if;
end if;
end process;
-- i_sample_fu_114 assign process. --
i_sample_fu_114_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ST_st6_fsm_5 = ap_CS_fsm) and not((ap_const_logic_0 = grp_sample_iterator_next_fu_289_ap_done)))) then
i_sample_fu_114 <= grp_sample_iterator_next_fu_289_ap_return_1;
elsif (((ap_ST_st1_fsm_0 = ap_CS_fsm) and not((ap_start = ap_const_logic_0)))) then
i_sample_fu_114 <= begin_sample;
end if;
end if;
end process;
-- indvars_iv_reg_208 assign process. --
indvars_iv_reg_208_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ST_st6_fsm_5 = ap_CS_fsm) and not((ap_const_logic_0 = grp_sample_iterator_next_fu_289_ap_done)))) then
indvars_iv_reg_208 <= units_reg_499;
elsif ((ap_ST_st2_fsm_1 = ap_CS_fsm)) then
indvars_iv_reg_208 <= ap_const_lv5_0;
end if;
end if;
end process;
-- k_1_reg_245 assign process. --
k_1_reg_245_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ST_st7_fsm_6 = ap_CS_fsm) and not((ap_const_logic_0 = grp_nfa_accept_sample_multi_fu_268_ap_done)) and (ap_const_lv1_0 = brmerge_demorgan_fu_387_p2))) then
k_1_reg_245 <= ap_const_lv5_0;
elsif ((ap_ST_st9_fsm_8 = ap_CS_fsm)) then
k_1_reg_245 <= k_2_reg_532;
end if;
end if;
end process;
-- p_0_reg_256 assign process. --
p_0_reg_256_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ST_st7_fsm_6 = ap_CS_fsm) and not((ap_const_logic_0 = grp_nfa_accept_sample_multi_fu_268_ap_done)) and not((ap_const_lv1_0 = brmerge_demorgan_fu_387_p2)))) then
p_0_reg_256 <= ap_const_lv16_1;
elsif (((ap_ST_st8_fsm_7 = ap_CS_fsm) and not((ap_const_lv1_0 = exitcond_fu_392_p2)) and not((ap_const_lv1_0 = finished_2_reg_233)))) then
p_0_reg_256 <= tmp_5_fu_412_p3;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ST_st3_fsm_2 = ap_CS_fsm) and (tmp_3_fu_326_p3 = ap_const_lv1_0))) then
i_index_load_reg_504 <= i_index_fu_110;
i_sample_load_reg_510 <= i_sample_fu_114;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_ST_st8_fsm_7 = ap_CS_fsm)) then
k_2_reg_532 <= k_2_fu_398_p2;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ST_st7_fsm_6 = ap_CS_fsm) and not((ap_const_logic_0 = grp_nfa_accept_sample_multi_fu_268_ap_done)))) then
stop_on_first_meet_reg_521 <= grp_nfa_accept_sample_multi_fu_268_ap_return;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_ST_st3_fsm_2 = ap_CS_fsm)) then
units_reg_499 <= units_fu_334_p2;
end if;
end if;
end process;
-- the next state (ap_NS_fsm) of the state machine. --
ap_NS_fsm_assign_proc : process (ap_start , ap_CS_fsm , tmp_3_fu_326_p3 , finished_3_fu_358_p2 , grp_nfa_accept_sample_multi_fu_268_ap_done , exitcond_fu_392_p2 , finished_2_reg_233 , grp_sample_iterator_next_fu_289_ap_done , grp_sample_iterator_get_offset_fu_297_ap_done , brmerge_demorgan_fu_387_p2)
begin
case ap_CS_fsm is
when ap_ST_st1_fsm_0 =>
if (not((ap_start = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st2_fsm_1;
else
ap_NS_fsm <= ap_ST_st1_fsm_0;
end if;
when ap_ST_st2_fsm_1 =>
ap_NS_fsm <= ap_ST_st3_fsm_2;
when ap_ST_st3_fsm_2 =>
if (((tmp_3_fu_326_p3 = ap_const_lv1_0) and (ap_const_lv1_0 = finished_3_fu_358_p2))) then
ap_NS_fsm <= ap_ST_st4_fsm_3;
else
ap_NS_fsm <= ap_ST_st7_fsm_6;
end if;
when ap_ST_st4_fsm_3 =>
if (not((ap_const_logic_0 = grp_sample_iterator_get_offset_fu_297_ap_done))) then
ap_NS_fsm <= ap_ST_st5_fsm_4;
else
ap_NS_fsm <= ap_ST_st4_fsm_3;
end if;
when ap_ST_st5_fsm_4 =>
ap_NS_fsm <= ap_ST_st6_fsm_5;
when ap_ST_st6_fsm_5 =>
if (not((ap_const_logic_0 = grp_sample_iterator_next_fu_289_ap_done))) then
ap_NS_fsm <= ap_ST_st3_fsm_2;
else
ap_NS_fsm <= ap_ST_st6_fsm_5;
end if;
when ap_ST_st7_fsm_6 =>
if ((not((ap_const_logic_0 = grp_nfa_accept_sample_multi_fu_268_ap_done)) and not((ap_const_lv1_0 = brmerge_demorgan_fu_387_p2)))) then
ap_NS_fsm <= ap_ST_st10_fsm_9;
elsif ((not((ap_const_logic_0 = grp_nfa_accept_sample_multi_fu_268_ap_done)) and (ap_const_lv1_0 = brmerge_demorgan_fu_387_p2))) then
ap_NS_fsm <= ap_ST_st8_fsm_7;
else
ap_NS_fsm <= ap_ST_st7_fsm_6;
end if;
when ap_ST_st8_fsm_7 =>
if ((not((ap_const_lv1_0 = exitcond_fu_392_p2)) and not((ap_const_lv1_0 = finished_2_reg_233)))) then
ap_NS_fsm <= ap_ST_st10_fsm_9;
elsif ((not((ap_const_lv1_0 = exitcond_fu_392_p2)) and (ap_const_lv1_0 = finished_2_reg_233))) then
ap_NS_fsm <= ap_ST_st2_fsm_1;
else
ap_NS_fsm <= ap_ST_st9_fsm_8;
end if;
when ap_ST_st9_fsm_8 =>
ap_NS_fsm <= ap_ST_st8_fsm_7;
when ap_ST_st10_fsm_9 =>
ap_NS_fsm <= ap_ST_st1_fsm_0;
when others =>
ap_NS_fsm <= "XXXX";
end case;
end process;
-- ap_done assign process. --
ap_done_assign_proc : process(ap_CS_fsm)
begin
if ((ap_ST_st10_fsm_9 = ap_CS_fsm)) then
ap_done <= ap_const_logic_1;
else
ap_done <= ap_const_logic_0;
end if;
end process;
-- ap_idle assign process. --
ap_idle_assign_proc : process(ap_start, ap_CS_fsm)
begin
if ((not((ap_const_logic_1 = ap_start)) and (ap_ST_st1_fsm_0 = ap_CS_fsm))) then
ap_idle <= ap_const_logic_1;
else
ap_idle <= ap_const_logic_0;
end if;
end process;
-- ap_ready assign process. --
ap_ready_assign_proc : process(ap_CS_fsm)
begin
if ((ap_ST_st10_fsm_9 = ap_CS_fsm)) then
ap_ready <= ap_const_logic_1;
else
ap_ready <= ap_const_logic_0;
end if;
end process;
ap_return <= std_logic_vector(resize(unsigned(p_0_reg_256),32));
-- ap_sig_bdd_287 assign process. --
ap_sig_bdd_287_assign_proc : process(tmp_3_fu_326_p3, finished_3_fu_358_p2)
begin
ap_sig_bdd_287 <= ((tmp_3_fu_326_p3 = ap_const_lv1_0) and not((ap_const_lv1_0 = finished_3_fu_358_p2)));
end process;
brmerge_demorgan_fu_387_p2 <= (grp_nfa_accept_sample_multi_fu_268_ap_return and stop_on_first);
c_1_fu_419_p2 <= std_logic_vector(unsigned(c_fu_106) + unsigned(ap_const_lv16_1));
exitcond_fu_392_p2 <= "1" when (k_1_reg_245 = indvars_iv_reg_208) else "0";
finished_3_fu_358_p2 <= (tmp_i_fu_348_p2 and tmp_i_16_fu_353_p2);
grp_nfa_accept_sample_multi_fu_268_accept <= accept;
grp_nfa_accept_sample_multi_fu_268_ap_start <= grp_nfa_accept_sample_multi_fu_268_ap_start_ap_start_reg;
grp_nfa_accept_sample_multi_fu_268_length_r <= sample_length;
grp_nfa_accept_sample_multi_fu_268_nfa_finals_buckets_datain <= nfa_finals_buckets_datain;
grp_nfa_accept_sample_multi_fu_268_nfa_finals_buckets_req_full_n <= nfa_finals_buckets_req_full_n;
grp_nfa_accept_sample_multi_fu_268_nfa_finals_buckets_rsp_empty_n <= nfa_finals_buckets_rsp_empty_n;
grp_nfa_accept_sample_multi_fu_268_nfa_forward_buckets_datain <= nfa_forward_buckets_datain;
grp_nfa_accept_sample_multi_fu_268_nfa_forward_buckets_req_full_n <= nfa_forward_buckets_req_full_n;
grp_nfa_accept_sample_multi_fu_268_nfa_forward_buckets_rsp_empty_n <= nfa_forward_buckets_rsp_empty_n;
grp_nfa_accept_sample_multi_fu_268_nfa_initials_buckets_datain <= nfa_initials_buckets_datain;
grp_nfa_accept_sample_multi_fu_268_nfa_initials_buckets_req_full_n <= nfa_initials_buckets_req_full_n;
grp_nfa_accept_sample_multi_fu_268_nfa_initials_buckets_rsp_empty_n <= nfa_initials_buckets_rsp_empty_n;
grp_nfa_accept_sample_multi_fu_268_nfa_symbols <= nfa_symbols;
grp_nfa_accept_sample_multi_fu_268_result_q0 <= result_q0;
grp_nfa_accept_sample_multi_fu_268_sample_datain <= sample_buffer_datain;
grp_nfa_accept_sample_multi_fu_268_sample_req_full_n <= sample_buffer_req_full_n;
grp_nfa_accept_sample_multi_fu_268_sample_rsp_empty_n <= sample_buffer_rsp_empty_n;
grp_nfa_accept_sample_multi_fu_268_start_indices_q0 <= start_indices_q0;
grp_nfa_accept_sample_multi_fu_268_stop_on_first <= stop_on_first;
grp_nfa_accept_sample_multi_fu_268_units <= indvars_iv_reg_208;
grp_sample_iterator_get_offset_fu_297_ap_start <= grp_sample_iterator_get_offset_fu_297_ap_start_ap_start_reg;
grp_sample_iterator_get_offset_fu_297_i_index <= i_index_load_reg_504;
grp_sample_iterator_get_offset_fu_297_i_sample <= i_sample_load_reg_510;
grp_sample_iterator_get_offset_fu_297_indices_datain <= indices_datain;
grp_sample_iterator_get_offset_fu_297_indices_req_full_n <= indices_req_full_n;
grp_sample_iterator_get_offset_fu_297_indices_rsp_empty_n <= indices_rsp_empty_n;
grp_sample_iterator_get_offset_fu_297_sample_buffer_size <= sample_buffer_length;
grp_sample_iterator_get_offset_fu_297_sample_length <= sample_length;
grp_sample_iterator_next_fu_289_ap_start <= grp_sample_iterator_next_fu_289_ap_start_ap_start_reg;
grp_sample_iterator_next_fu_289_i_index <= i_index_load_reg_504;
grp_sample_iterator_next_fu_289_i_sample <= i_sample_load_reg_510;
grp_sample_iterator_next_fu_289_indices_datain <= indices_datain;
grp_sample_iterator_next_fu_289_indices_req_full_n <= indices_req_full_n;
grp_sample_iterator_next_fu_289_indices_rsp_empty_n <= indices_rsp_empty_n;
-- indices_address assign process. --
indices_address_assign_proc : process(ap_CS_fsm, tmp_3_fu_326_p3, finished_3_fu_358_p2, grp_sample_iterator_next_fu_289_ap_idle, grp_sample_iterator_next_fu_289_indices_address, grp_sample_iterator_get_offset_fu_297_ap_idle, grp_sample_iterator_get_offset_fu_297_indices_address)
begin
if ((((ap_ST_st3_fsm_2 = ap_CS_fsm) and (tmp_3_fu_326_p3 = ap_const_lv1_0) and (ap_const_lv1_0 = finished_3_fu_358_p2)) or ((ap_ST_st4_fsm_3 = ap_CS_fsm) and (ap_const_logic_0 = grp_sample_iterator_get_offset_fu_297_ap_idle)))) then
indices_address <= grp_sample_iterator_get_offset_fu_297_indices_address;
elsif (((ap_ST_st5_fsm_4 = ap_CS_fsm) or ((ap_ST_st6_fsm_5 = ap_CS_fsm) and (ap_const_logic_0 = grp_sample_iterator_next_fu_289_ap_idle)))) then
indices_address <= grp_sample_iterator_next_fu_289_indices_address;
else
indices_address <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
-- indices_dataout assign process. --
indices_dataout_assign_proc : process(ap_CS_fsm, tmp_3_fu_326_p3, finished_3_fu_358_p2, grp_sample_iterator_next_fu_289_ap_idle, grp_sample_iterator_next_fu_289_indices_dataout, grp_sample_iterator_get_offset_fu_297_ap_idle, grp_sample_iterator_get_offset_fu_297_indices_dataout)
begin
if ((((ap_ST_st3_fsm_2 = ap_CS_fsm) and (tmp_3_fu_326_p3 = ap_const_lv1_0) and (ap_const_lv1_0 = finished_3_fu_358_p2)) or ((ap_ST_st4_fsm_3 = ap_CS_fsm) and (ap_const_logic_0 = grp_sample_iterator_get_offset_fu_297_ap_idle)))) then
indices_dataout <= grp_sample_iterator_get_offset_fu_297_indices_dataout;
elsif (((ap_ST_st5_fsm_4 = ap_CS_fsm) or ((ap_ST_st6_fsm_5 = ap_CS_fsm) and (ap_const_logic_0 = grp_sample_iterator_next_fu_289_ap_idle)))) then
indices_dataout <= grp_sample_iterator_next_fu_289_indices_dataout;
else
indices_dataout <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
-- indices_req_din assign process. --
indices_req_din_assign_proc : process(ap_CS_fsm, tmp_3_fu_326_p3, finished_3_fu_358_p2, grp_sample_iterator_next_fu_289_ap_idle, grp_sample_iterator_next_fu_289_indices_req_din, grp_sample_iterator_get_offset_fu_297_ap_idle, grp_sample_iterator_get_offset_fu_297_indices_req_din)
begin
if ((((ap_ST_st3_fsm_2 = ap_CS_fsm) and (tmp_3_fu_326_p3 = ap_const_lv1_0) and (ap_const_lv1_0 = finished_3_fu_358_p2)) or ((ap_ST_st4_fsm_3 = ap_CS_fsm) and (ap_const_logic_0 = grp_sample_iterator_get_offset_fu_297_ap_idle)))) then
indices_req_din <= grp_sample_iterator_get_offset_fu_297_indices_req_din;
elsif (((ap_ST_st5_fsm_4 = ap_CS_fsm) or ((ap_ST_st6_fsm_5 = ap_CS_fsm) and (ap_const_logic_0 = grp_sample_iterator_next_fu_289_ap_idle)))) then
indices_req_din <= grp_sample_iterator_next_fu_289_indices_req_din;
else
indices_req_din <= 'X';
end if;
end process;
-- indices_req_write assign process. --
indices_req_write_assign_proc : process(ap_CS_fsm, tmp_3_fu_326_p3, finished_3_fu_358_p2, grp_sample_iterator_next_fu_289_ap_idle, grp_sample_iterator_next_fu_289_indices_req_write, grp_sample_iterator_get_offset_fu_297_ap_idle, grp_sample_iterator_get_offset_fu_297_indices_req_write)
begin
if ((((ap_ST_st3_fsm_2 = ap_CS_fsm) and (tmp_3_fu_326_p3 = ap_const_lv1_0) and (ap_const_lv1_0 = finished_3_fu_358_p2)) or ((ap_ST_st4_fsm_3 = ap_CS_fsm) and (ap_const_logic_0 = grp_sample_iterator_get_offset_fu_297_ap_idle)))) then
indices_req_write <= grp_sample_iterator_get_offset_fu_297_indices_req_write;
elsif (((ap_ST_st5_fsm_4 = ap_CS_fsm) or ((ap_ST_st6_fsm_5 = ap_CS_fsm) and (ap_const_logic_0 = grp_sample_iterator_next_fu_289_ap_idle)))) then
indices_req_write <= grp_sample_iterator_next_fu_289_indices_req_write;
else
indices_req_write <= 'X';
end if;
end process;
-- indices_rsp_read assign process. --
indices_rsp_read_assign_proc : process(ap_CS_fsm, tmp_3_fu_326_p3, finished_3_fu_358_p2, grp_sample_iterator_next_fu_289_ap_idle, grp_sample_iterator_next_fu_289_indices_rsp_read, grp_sample_iterator_get_offset_fu_297_ap_idle, grp_sample_iterator_get_offset_fu_297_indices_rsp_read)
begin
if ((((ap_ST_st3_fsm_2 = ap_CS_fsm) and (tmp_3_fu_326_p3 = ap_const_lv1_0) and (ap_const_lv1_0 = finished_3_fu_358_p2)) or ((ap_ST_st4_fsm_3 = ap_CS_fsm) and (ap_const_logic_0 = grp_sample_iterator_get_offset_fu_297_ap_idle)))) then
indices_rsp_read <= grp_sample_iterator_get_offset_fu_297_indices_rsp_read;
elsif (((ap_ST_st5_fsm_4 = ap_CS_fsm) or ((ap_ST_st6_fsm_5 = ap_CS_fsm) and (ap_const_logic_0 = grp_sample_iterator_next_fu_289_ap_idle)))) then
indices_rsp_read <= grp_sample_iterator_next_fu_289_indices_rsp_read;
else
indices_rsp_read <= 'X';
end if;
end process;
-- indices_size assign process. --
indices_size_assign_proc : process(ap_CS_fsm, tmp_3_fu_326_p3, finished_3_fu_358_p2, grp_sample_iterator_next_fu_289_ap_idle, grp_sample_iterator_next_fu_289_indices_size, grp_sample_iterator_get_offset_fu_297_ap_idle, grp_sample_iterator_get_offset_fu_297_indices_size)
begin
if ((((ap_ST_st3_fsm_2 = ap_CS_fsm) and (tmp_3_fu_326_p3 = ap_const_lv1_0) and (ap_const_lv1_0 = finished_3_fu_358_p2)) or ((ap_ST_st4_fsm_3 = ap_CS_fsm) and (ap_const_logic_0 = grp_sample_iterator_get_offset_fu_297_ap_idle)))) then
indices_size <= grp_sample_iterator_get_offset_fu_297_indices_size;
elsif (((ap_ST_st5_fsm_4 = ap_CS_fsm) or ((ap_ST_st6_fsm_5 = ap_CS_fsm) and (ap_const_logic_0 = grp_sample_iterator_next_fu_289_ap_idle)))) then
indices_size <= grp_sample_iterator_next_fu_289_indices_size;
else
indices_size <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
k_2_fu_398_p2 <= std_logic_vector(unsigned(k_1_reg_245) + unsigned(ap_const_lv5_1));
nfa_finals_buckets_address <= grp_nfa_accept_sample_multi_fu_268_nfa_finals_buckets_address;
nfa_finals_buckets_dataout <= grp_nfa_accept_sample_multi_fu_268_nfa_finals_buckets_dataout;
nfa_finals_buckets_req_din <= grp_nfa_accept_sample_multi_fu_268_nfa_finals_buckets_req_din;
nfa_finals_buckets_req_write <= grp_nfa_accept_sample_multi_fu_268_nfa_finals_buckets_req_write;
nfa_finals_buckets_rsp_read <= grp_nfa_accept_sample_multi_fu_268_nfa_finals_buckets_rsp_read;
nfa_finals_buckets_size <= grp_nfa_accept_sample_multi_fu_268_nfa_finals_buckets_size;
nfa_forward_buckets_address <= grp_nfa_accept_sample_multi_fu_268_nfa_forward_buckets_address;
nfa_forward_buckets_dataout <= grp_nfa_accept_sample_multi_fu_268_nfa_forward_buckets_dataout;
nfa_forward_buckets_req_din <= grp_nfa_accept_sample_multi_fu_268_nfa_forward_buckets_req_din;
nfa_forward_buckets_req_write <= grp_nfa_accept_sample_multi_fu_268_nfa_forward_buckets_req_write;
nfa_forward_buckets_rsp_read <= grp_nfa_accept_sample_multi_fu_268_nfa_forward_buckets_rsp_read;
nfa_forward_buckets_size <= grp_nfa_accept_sample_multi_fu_268_nfa_forward_buckets_size;
nfa_initials_buckets_address <= grp_nfa_accept_sample_multi_fu_268_nfa_initials_buckets_address;
nfa_initials_buckets_dataout <= grp_nfa_accept_sample_multi_fu_268_nfa_initials_buckets_dataout;
nfa_initials_buckets_req_din <= grp_nfa_accept_sample_multi_fu_268_nfa_initials_buckets_req_din;
nfa_initials_buckets_req_write <= grp_nfa_accept_sample_multi_fu_268_nfa_initials_buckets_req_write;
nfa_initials_buckets_rsp_read <= grp_nfa_accept_sample_multi_fu_268_nfa_initials_buckets_rsp_read;
nfa_initials_buckets_size <= grp_nfa_accept_sample_multi_fu_268_nfa_initials_buckets_size;
p_c_1_fu_425_p3 <=
c_1_fu_419_p2 when (result_q0(0) = '1') else
c_fu_106;
-- result_address0 assign process. --
result_address0_assign_proc : process(ap_CS_fsm, grp_nfa_accept_sample_multi_fu_268_result_address0, tmp_2_fu_404_p1)
begin
if ((ap_ST_st8_fsm_7 = ap_CS_fsm)) then
result_address0 <= tmp_2_fu_404_p1(4 - 1 downto 0);
elsif ((ap_ST_st7_fsm_6 = ap_CS_fsm)) then
result_address0 <= grp_nfa_accept_sample_multi_fu_268_result_address0;
else
result_address0 <= "XXXX";
end if;
end process;
-- result_ce0 assign process. --
result_ce0_assign_proc : process(ap_CS_fsm, grp_nfa_accept_sample_multi_fu_268_result_ce0)
begin
if ((ap_ST_st8_fsm_7 = ap_CS_fsm)) then
result_ce0 <= ap_const_logic_1;
elsif ((ap_ST_st7_fsm_6 = ap_CS_fsm)) then
result_ce0 <= grp_nfa_accept_sample_multi_fu_268_result_ce0;
else
result_ce0 <= ap_const_logic_0;
end if;
end process;
result_d0 <= grp_nfa_accept_sample_multi_fu_268_result_d0;
-- result_we0 assign process. --
result_we0_assign_proc : process(ap_CS_fsm, grp_nfa_accept_sample_multi_fu_268_result_we0)
begin
if ((ap_ST_st7_fsm_6 = ap_CS_fsm)) then
result_we0 <= grp_nfa_accept_sample_multi_fu_268_result_we0;
else
result_we0 <= ap_const_logic_0;
end if;
end process;
sample_buffer_address <= grp_nfa_accept_sample_multi_fu_268_sample_address;
sample_buffer_dataout <= grp_nfa_accept_sample_multi_fu_268_sample_dataout;
sample_buffer_req_din <= grp_nfa_accept_sample_multi_fu_268_sample_req_din;
sample_buffer_req_write <= grp_nfa_accept_sample_multi_fu_268_sample_req_write;
sample_buffer_rsp_read <= grp_nfa_accept_sample_multi_fu_268_sample_rsp_read;
sample_buffer_size <= grp_nfa_accept_sample_multi_fu_268_sample_size;
-- start_indices_address0 assign process. --
start_indices_address0_assign_proc : process(ap_CS_fsm, grp_nfa_accept_sample_multi_fu_268_start_indices_address0, tmp_1_fu_364_p1)
begin
if ((ap_ST_st4_fsm_3 = ap_CS_fsm)) then
start_indices_address0 <= tmp_1_fu_364_p1(4 - 1 downto 0);
elsif ((ap_ST_st7_fsm_6 = ap_CS_fsm)) then
start_indices_address0 <= grp_nfa_accept_sample_multi_fu_268_start_indices_address0;
else
start_indices_address0 <= "XXXX";
end if;
end process;
-- start_indices_ce0 assign process. --
start_indices_ce0_assign_proc : process(ap_CS_fsm, grp_nfa_accept_sample_multi_fu_268_start_indices_ce0, grp_sample_iterator_get_offset_fu_297_ap_done)
begin
if (((ap_ST_st4_fsm_3 = ap_CS_fsm) and not((ap_const_logic_0 = grp_sample_iterator_get_offset_fu_297_ap_done)))) then
start_indices_ce0 <= ap_const_logic_1;
elsif ((ap_ST_st7_fsm_6 = ap_CS_fsm)) then
start_indices_ce0 <= grp_nfa_accept_sample_multi_fu_268_start_indices_ce0;
else
start_indices_ce0 <= ap_const_logic_0;
end if;
end process;
start_indices_d0 <= grp_sample_iterator_get_offset_fu_297_ap_return;
-- start_indices_we0 assign process. --
start_indices_we0_assign_proc : process(ap_CS_fsm, grp_sample_iterator_get_offset_fu_297_ap_done)
begin
if ((((ap_ST_st4_fsm_3 = ap_CS_fsm) and not((ap_const_logic_0 = grp_sample_iterator_get_offset_fu_297_ap_done))))) then
start_indices_we0 <= ap_const_logic_1;
else
start_indices_we0 <= ap_const_logic_0;
end if;
end process;
tmp_1_fu_364_p1 <= std_logic_vector(resize(unsigned(indvars_iv_reg_208),64));
tmp_2_fu_404_p1 <= std_logic_vector(resize(unsigned(k_1_reg_245),64));
tmp_3_cast_fu_409_p1 <= std_logic_vector(resize(unsigned(stop_on_first_meet_reg_521),16));
tmp_3_fu_326_p3 <= indvars_iv_reg_208(4 downto 4);
tmp_5_fu_412_p3 <=
tmp_3_cast_fu_409_p1 when (stop_on_first(0) = '1') else
c_fu_106;
tmp_i_16_fu_353_p2 <= "1" when (i_index_fu_110 = end_index) else "0";
tmp_i_fu_348_p2 <= "1" when (i_sample_fu_114 = end_sample) else "0";
units_fu_334_p2 <= std_logic_vector(unsigned(indvars_iv_reg_208) + unsigned(ap_const_lv5_1));
end behav;
| lgpl-3.0 | 51ada4958aa6d8e7638dd9c578d0eb04 | 0.639907 | 2.870624 | false | false | false | false |
rauenzi/VHDL-Communications | BoardDisplay.vhd | 1 | 2,591 | ----------------------------------------------------------------------------------
--Code by: Zachary Rauen
--Date: 10/6/14
--Last Modified: 10/16/14
--
--Description: This is a 7 segment display that takes in
-- a 16 bit number and displays it across 4 7 segment displays
--
--Version: 2.3
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity BoardDisplay is
Generic (RefreshRate : integer := 1000;
ClockSpeed : integer := 100000000);
Port ( ClockState : in std_logic;
Data : in std_logic_vector(15 downto 0);
DisplayVector : out std_logic_vector(7 downto 0);
SegmentVector : out std_logic_vector(7 downto 0));
end BoardDisplay;
architecture Behavioral of BoardDisplay is
signal vectorSection : std_logic_vector(3 downto 0);
signal segCnt : integer := 0;
signal segCntMax : integer := 3;
signal dispCarry : std_logic_vector(7 downto 0);
signal SegmentEnable : std_logic;
signal clkEnableMax : integer := ClockSpeed/RefreshRate;
signal clkEnCnt : integer := 0;
begin
Refresh: process(ClockState)
begin
if rising_edge(ClockState) then
if clkEnCnt = clkEnableMax then
SegmentEnable <= '1';
clkEnCnt <= 0;
else
clkEnCnt<=clkEnCnt+1;
SegmentEnable <= '0';
end if;
end if;
if rising_edge(ClockState) AND SegmentEnable = '1' then
if segCnt = segCntMax then
segCnt <= 0;
else
segCnt <= segCnt + 1;
end if;
end if;
end process Refresh;
Display: process(ClockState,Data)
begin
case segCnt is
when 0 =>
SegmentVector <="11111110";
vectorSection <=Data(3 downto 0);
when 1 =>
SegmentVector <="11111101";
vectorSection <=Data(7 downto 4);
when 2 =>
SegmentVector <="11111011";
vectorSection <=Data(11 downto 8);
when 3 =>
SegmentVector <="11110111";
vectorSection <=Data(15 downto 12);
when others =>
SegmentVector <="11111111";
vectorSection <="1111";
end case;
end process Display;
with vectorSection select dispCarry <=
"11111100" when "0000",
"01100000" when "0001",
"11011010" when "0010",
"11110010" when "0011",
"01100110" when "0100",
"10110110" when "0101",
"10111110" when "0110",
"11100000" when "0111",
"11111110" when "1000",
"11110110" when "1001",
"11101110" when "1010",
"00111110" when "1011",
"10011100" when "1100",
"01111010" when "1101",
"10011110" when "1110",
"10001110" when "1111";
DisplayVector<= NOT dispCarry;
end Behavioral;
| apache-2.0 | 1b01baa547e842a26cbb75957228db61 | 0.60633 | 3.855655 | false | false | false | false |
grwlf/vsim | vhdl_ct/ct00336.vhd | 1 | 63,583 | -- NEED RESULT: ARCH00336.P1: Multi transport transactions occurred on concurrent signal asg passed
-- NEED RESULT: ARCH00336.P2: Multi transport transactions occurred on concurrent signal asg passed
-- NEED RESULT: ARCH00336.P3: Multi transport transactions occurred on concurrent signal asg passed
-- NEED RESULT: ARCH00336.P4: Multi transport transactions occurred on concurrent signal asg passed
-- NEED RESULT: ARCH00336.P5: Multi transport transactions occurred on concurrent signal asg passed
-- NEED RESULT: ARCH00336.P6: Multi transport transactions occurred on concurrent signal asg passed
-- NEED RESULT: ARCH00336.P7: Multi transport transactions occurred on concurrent signal asg passed
-- NEED RESULT: ARCH00336.P8: Multi transport transactions occurred on concurrent signal asg passed
-- NEED RESULT: ARCH00336.P9: Multi transport transactions occurred on concurrent signal asg passed
-- NEED RESULT: ARCH00336.P10: Multi transport transactions occurred on concurrent signal asg passed
-- NEED RESULT: ARCH00336.P11: Multi transport transactions occurred on concurrent signal asg passed
-- NEED RESULT: ARCH00336.P12: Multi transport transactions occurred on concurrent signal asg passed
-- NEED RESULT: ARCH00336.P13: Multi transport transactions occurred on concurrent signal asg passed
-- NEED RESULT: ARCH00336.P14: Multi transport transactions occurred on concurrent signal asg passed
-- NEED RESULT: ARCH00336.P15: Multi transport transactions occurred on concurrent signal asg passed
-- NEED RESULT: ARCH00336.P16: Multi transport transactions occurred on concurrent signal asg passed
-- NEED RESULT: ARCH00336.P17: Multi transport transactions occurred on concurrent signal asg passed
-- NEED RESULT: ARCH00336: One transport transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00336: Old transactions were removed on a concurrent signal asg passed
-- NEED RESULT: ARCH00336: One transport transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00336: Old transactions were removed on a concurrent signal asg passed
-- NEED RESULT: ARCH00336: One transport transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00336: Old transactions were removed on a concurrent signal asg passed
-- NEED RESULT: ARCH00336: One transport transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00336: Old transactions were removed on a concurrent signal asg passed
-- NEED RESULT: ARCH00336: One transport transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00336: Old transactions were removed on a concurrent signal asg passed
-- NEED RESULT: ARCH00336: One transport transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00336: Old transactions were removed on a concurrent signal asg passed
-- NEED RESULT: ARCH00336: One transport transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00336: Old transactions were removed on a concurrent signal asg passed
-- NEED RESULT: ARCH00336: One transport transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00336: Old transactions were removed on a concurrent signal asg passed
-- NEED RESULT: ARCH00336: One transport transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00336: Old transactions were removed on a concurrent signal asg passed
-- NEED RESULT: ARCH00336: One transport transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00336: Old transactions were removed on a concurrent signal asg passed
-- NEED RESULT: ARCH00336: One transport transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00336: Old transactions were removed on a concurrent signal asg passed
-- NEED RESULT: ARCH00336: One transport transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00336: Old transactions were removed on a concurrent signal asg passed
-- NEED RESULT: ARCH00336: One transport transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00336: Old transactions were removed on a concurrent signal asg passed
-- NEED RESULT: ARCH00336: One transport transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00336: Old transactions were removed on a concurrent signal asg passed
-- NEED RESULT: ARCH00336: One transport transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00336: Old transactions were removed on a concurrent signal asg passed
-- NEED RESULT: ARCH00336: One transport transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00336: Old transactions were removed on a concurrent signal asg passed
-- NEED RESULT: ARCH00336: One transport transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00336: Old transactions were removed on a concurrent signal asg passed
-- NEED RESULT: P17: Transport transactions completed entirely passed
-- NEED RESULT: P16: Transport transactions completed entirely passed
-- NEED RESULT: P15: Transport transactions completed entirely passed
-- NEED RESULT: P14: Transport transactions completed entirely passed
-- NEED RESULT: P13: Transport transactions completed entirely passed
-- NEED RESULT: P12: Transport transactions completed entirely passed
-- NEED RESULT: P11: Transport transactions completed entirely passed
-- NEED RESULT: P10: Transport transactions completed entirely passed
-- NEED RESULT: P9: Transport transactions completed entirely passed
-- NEED RESULT: P8: Transport transactions completed entirely passed
-- NEED RESULT: P7: Transport transactions completed entirely passed
-- NEED RESULT: P6: Transport transactions completed entirely passed
-- NEED RESULT: P5: Transport transactions completed entirely passed
-- NEED RESULT: P4: Transport transactions completed entirely passed
-- NEED RESULT: P3: Transport transactions completed entirely passed
-- NEED RESULT: P2: Transport transactions completed entirely passed
-- NEED RESULT: P1: Transport transactions completed entirely passed
-------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
-------------------------------------------------------------------------------
--
-- TEST NAME:
--
-- CT00336
--
-- AUTHOR:
--
-- G. Tominovich
--
-- TEST OBJECTIVES:
--
-- 9.5 (2)
-- 9.5.2 (1)
--
-- DESIGN UNIT ORDERING:
--
-- ENT00336(ARCH00336)
-- ENT00336_Test_Bench(ARCH00336_Test_Bench)
--
-- REVISION HISTORY:
--
-- 30-JUL-1987 - initial revision
--
-- NOTES:
--
-- self-checking
-- automatically generated
--
use WORK.STANDARD_TYPES.all ;
entity ENT00336 is
end ENT00336 ;
--
--
architecture ARCH00336 of ENT00336 is
subtype chk_sig_type is integer range -1 to 100 ;
signal chk_boolean : chk_sig_type := -1 ;
signal chk_bit : chk_sig_type := -1 ;
signal chk_severity_level : chk_sig_type := -1 ;
signal chk_character : chk_sig_type := -1 ;
signal chk_st_enum1 : chk_sig_type := -1 ;
signal chk_integer : chk_sig_type := -1 ;
signal chk_st_int1 : chk_sig_type := -1 ;
signal chk_time : chk_sig_type := -1 ;
signal chk_st_phys1 : chk_sig_type := -1 ;
signal chk_real : chk_sig_type := -1 ;
signal chk_st_real1 : chk_sig_type := -1 ;
signal chk_st_rec1 : chk_sig_type := -1 ;
signal chk_st_rec2 : chk_sig_type := -1 ;
signal chk_st_rec3 : chk_sig_type := -1 ;
signal chk_st_arr1 : chk_sig_type := -1 ;
signal chk_st_arr2 : chk_sig_type := -1 ;
signal chk_st_arr3 : chk_sig_type := -1 ;
--
subtype chk_time_type is Time ;
signal s_boolean_savt : chk_time_type := 0 ns ;
signal s_bit_savt : chk_time_type := 0 ns ;
signal s_severity_level_savt : chk_time_type := 0 ns ;
signal s_character_savt : chk_time_type := 0 ns ;
signal s_st_enum1_savt : chk_time_type := 0 ns ;
signal s_integer_savt : chk_time_type := 0 ns ;
signal s_st_int1_savt : chk_time_type := 0 ns ;
signal s_time_savt : chk_time_type := 0 ns ;
signal s_st_phys1_savt : chk_time_type := 0 ns ;
signal s_real_savt : chk_time_type := 0 ns ;
signal s_st_real1_savt : chk_time_type := 0 ns ;
signal s_st_rec1_savt : chk_time_type := 0 ns ;
signal s_st_rec2_savt : chk_time_type := 0 ns ;
signal s_st_rec3_savt : chk_time_type := 0 ns ;
signal s_st_arr1_savt : chk_time_type := 0 ns ;
signal s_st_arr2_savt : chk_time_type := 0 ns ;
signal s_st_arr3_savt : chk_time_type := 0 ns ;
--
subtype chk_cnt_type is Integer ;
signal s_boolean_cnt : chk_cnt_type := 0 ;
signal s_bit_cnt : chk_cnt_type := 0 ;
signal s_severity_level_cnt : chk_cnt_type := 0 ;
signal s_character_cnt : chk_cnt_type := 0 ;
signal s_st_enum1_cnt : chk_cnt_type := 0 ;
signal s_integer_cnt : chk_cnt_type := 0 ;
signal s_st_int1_cnt : chk_cnt_type := 0 ;
signal s_time_cnt : chk_cnt_type := 0 ;
signal s_st_phys1_cnt : chk_cnt_type := 0 ;
signal s_real_cnt : chk_cnt_type := 0 ;
signal s_st_real1_cnt : chk_cnt_type := 0 ;
signal s_st_rec1_cnt : chk_cnt_type := 0 ;
signal s_st_rec2_cnt : chk_cnt_type := 0 ;
signal s_st_rec3_cnt : chk_cnt_type := 0 ;
signal s_st_arr1_cnt : chk_cnt_type := 0 ;
signal s_st_arr2_cnt : chk_cnt_type := 0 ;
signal s_st_arr3_cnt : chk_cnt_type := 0 ;
--
type select_type is range 1 to 3 ;
signal boolean_select : select_type := 1 ;
signal bit_select : select_type := 1 ;
signal severity_level_select : select_type := 1 ;
signal character_select : select_type := 1 ;
signal st_enum1_select : select_type := 1 ;
signal integer_select : select_type := 1 ;
signal st_int1_select : select_type := 1 ;
signal time_select : select_type := 1 ;
signal st_phys1_select : select_type := 1 ;
signal real_select : select_type := 1 ;
signal st_real1_select : select_type := 1 ;
signal st_rec1_select : select_type := 1 ;
signal st_rec2_select : select_type := 1 ;
signal st_rec3_select : select_type := 1 ;
signal st_arr1_select : select_type := 1 ;
signal st_arr2_select : select_type := 1 ;
signal st_arr3_select : select_type := 1 ;
--
signal s_boolean : boolean
:= c_boolean_1 ;
signal s_bit : bit
:= c_bit_1 ;
signal s_severity_level : severity_level
:= c_severity_level_1 ;
signal s_character : character
:= c_character_1 ;
signal s_st_enum1 : st_enum1
:= c_st_enum1_1 ;
signal s_integer : integer
:= c_integer_1 ;
signal s_st_int1 : st_int1
:= c_st_int1_1 ;
signal s_time : time
:= c_time_1 ;
signal s_st_phys1 : st_phys1
:= c_st_phys1_1 ;
signal s_real : real
:= c_real_1 ;
signal s_st_real1 : st_real1
:= c_st_real1_1 ;
signal s_st_rec1 : st_rec1
:= c_st_rec1_1 ;
signal s_st_rec2 : st_rec2
:= c_st_rec2_1 ;
signal s_st_rec3 : st_rec3
:= c_st_rec3_1 ;
signal s_st_arr1 : st_arr1
:= c_st_arr1_1 ;
signal s_st_arr2 : st_arr2
:= c_st_arr2_1 ;
signal s_st_arr3 : st_arr3
:= c_st_arr3_1 ;
--
begin
CHG1 :
process ( s_boolean )
variable correct : boolean ;
begin
case s_boolean_cnt is
when 0
=> null ;
-- s_boolean <= transport
-- c_boolean_2 after 10 ns,
-- c_boolean_1 after 20 ns ;
--
when 1
=> correct :=
s_boolean =
c_boolean_2 and
(s_boolean_savt + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_boolean =
c_boolean_1 and
(s_boolean_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00336.P1" ,
"Multi transport transactions occurred on " &
"concurrent signal asg",
correct ) ;
--
boolean_select <= transport 2 ;
-- s_boolean <= transport
-- c_boolean_2 after 10 ns ,
-- c_boolean_1 after 20 ns ,
-- c_boolean_2 after 30 ns ,
-- c_boolean_1 after 40 ns ;
--
when 3
=> correct :=
s_boolean =
c_boolean_2 and
(s_boolean_savt + 10 ns) = Std.Standard.Now ;
boolean_select <= transport 3 ;
-- s_boolean <= transport
-- c_boolean_1 after 5 ns ;
--
when 4
=> correct :=
correct and
s_boolean =
c_boolean_1 and
(s_boolean_savt + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00336" ,
"One transport transaction occurred on a " &
"concurrent signal asg",
correct ) ;
test_report ( "ARCH00336" ,
"Old transactions were removed on a " &
"concurrent signal asg",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00336" ,
"Old transactions were removed on a " &
"concurrent signal asg",
false ) ;
--
end case ;
--
s_boolean_savt <= transport Std.Standard.Now ;
chk_boolean <= transport s_boolean_cnt
after (1 us - Std.Standard.Now) ;
s_boolean_cnt <= transport s_boolean_cnt + 1 ;
--
end process CHG1 ;
--
PGEN_CHKP_1 :
process ( chk_boolean )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P1" ,
"Transport transactions completed entirely",
chk_boolean = 4 ) ;
end if ;
end process PGEN_CHKP_1 ;
--
--
with boolean_select select
s_boolean <= transport
c_boolean_2 after 10 ns,
c_boolean_1 after 20 ns
when 1,
--
c_boolean_2 after 10 ns ,
c_boolean_1 after 20 ns ,
c_boolean_2 after 30 ns ,
c_boolean_1 after 40 ns
when 2,
--
c_boolean_1 after 5 ns when 3 ;
--
CHG2 :
process ( s_bit )
variable correct : boolean ;
begin
case s_bit_cnt is
when 0
=> null ;
-- s_bit <= transport
-- c_bit_2 after 10 ns,
-- c_bit_1 after 20 ns ;
--
when 1
=> correct :=
s_bit =
c_bit_2 and
(s_bit_savt + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_bit =
c_bit_1 and
(s_bit_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00336.P2" ,
"Multi transport transactions occurred on " &
"concurrent signal asg",
correct ) ;
--
bit_select <= transport 2 ;
-- s_bit <= transport
-- c_bit_2 after 10 ns ,
-- c_bit_1 after 20 ns ,
-- c_bit_2 after 30 ns ,
-- c_bit_1 after 40 ns ;
--
when 3
=> correct :=
s_bit =
c_bit_2 and
(s_bit_savt + 10 ns) = Std.Standard.Now ;
bit_select <= transport 3 ;
-- s_bit <= transport
-- c_bit_1 after 5 ns ;
--
when 4
=> correct :=
correct and
s_bit =
c_bit_1 and
(s_bit_savt + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00336" ,
"One transport transaction occurred on a " &
"concurrent signal asg",
correct ) ;
test_report ( "ARCH00336" ,
"Old transactions were removed on a " &
"concurrent signal asg",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00336" ,
"Old transactions were removed on a " &
"concurrent signal asg",
false ) ;
--
end case ;
--
s_bit_savt <= transport Std.Standard.Now ;
chk_bit <= transport s_bit_cnt
after (1 us - Std.Standard.Now) ;
s_bit_cnt <= transport s_bit_cnt + 1 ;
--
end process CHG2 ;
--
PGEN_CHKP_2 :
process ( chk_bit )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P2" ,
"Transport transactions completed entirely",
chk_bit = 4 ) ;
end if ;
end process PGEN_CHKP_2 ;
--
--
with bit_select select
s_bit <= transport
c_bit_2 after 10 ns,
c_bit_1 after 20 ns
when 1,
--
c_bit_2 after 10 ns ,
c_bit_1 after 20 ns ,
c_bit_2 after 30 ns ,
c_bit_1 after 40 ns
when 2,
--
c_bit_1 after 5 ns when 3 ;
--
CHG3 :
process ( s_severity_level )
variable correct : boolean ;
begin
case s_severity_level_cnt is
when 0
=> null ;
-- s_severity_level <= transport
-- c_severity_level_2 after 10 ns,
-- c_severity_level_1 after 20 ns ;
--
when 1
=> correct :=
s_severity_level =
c_severity_level_2 and
(s_severity_level_savt + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_severity_level =
c_severity_level_1 and
(s_severity_level_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00336.P3" ,
"Multi transport transactions occurred on " &
"concurrent signal asg",
correct ) ;
--
severity_level_select <= transport 2 ;
-- s_severity_level <= transport
-- c_severity_level_2 after 10 ns ,
-- c_severity_level_1 after 20 ns ,
-- c_severity_level_2 after 30 ns ,
-- c_severity_level_1 after 40 ns ;
--
when 3
=> correct :=
s_severity_level =
c_severity_level_2 and
(s_severity_level_savt + 10 ns) = Std.Standard.Now ;
severity_level_select <= transport 3 ;
-- s_severity_level <= transport
-- c_severity_level_1 after 5 ns ;
--
when 4
=> correct :=
correct and
s_severity_level =
c_severity_level_1 and
(s_severity_level_savt + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00336" ,
"One transport transaction occurred on a " &
"concurrent signal asg",
correct ) ;
test_report ( "ARCH00336" ,
"Old transactions were removed on a " &
"concurrent signal asg",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00336" ,
"Old transactions were removed on a " &
"concurrent signal asg",
false ) ;
--
end case ;
--
s_severity_level_savt <= transport Std.Standard.Now ;
chk_severity_level <= transport s_severity_level_cnt
after (1 us - Std.Standard.Now) ;
s_severity_level_cnt <= transport s_severity_level_cnt + 1 ;
--
end process CHG3 ;
--
PGEN_CHKP_3 :
process ( chk_severity_level )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P3" ,
"Transport transactions completed entirely",
chk_severity_level = 4 ) ;
end if ;
end process PGEN_CHKP_3 ;
--
--
with severity_level_select select
s_severity_level <= transport
c_severity_level_2 after 10 ns,
c_severity_level_1 after 20 ns
when 1,
--
c_severity_level_2 after 10 ns ,
c_severity_level_1 after 20 ns ,
c_severity_level_2 after 30 ns ,
c_severity_level_1 after 40 ns
when 2,
--
c_severity_level_1 after 5 ns when 3 ;
--
CHG4 :
process ( s_character )
variable correct : boolean ;
begin
case s_character_cnt is
when 0
=> null ;
-- s_character <= transport
-- c_character_2 after 10 ns,
-- c_character_1 after 20 ns ;
--
when 1
=> correct :=
s_character =
c_character_2 and
(s_character_savt + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_character =
c_character_1 and
(s_character_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00336.P4" ,
"Multi transport transactions occurred on " &
"concurrent signal asg",
correct ) ;
--
character_select <= transport 2 ;
-- s_character <= transport
-- c_character_2 after 10 ns ,
-- c_character_1 after 20 ns ,
-- c_character_2 after 30 ns ,
-- c_character_1 after 40 ns ;
--
when 3
=> correct :=
s_character =
c_character_2 and
(s_character_savt + 10 ns) = Std.Standard.Now ;
character_select <= transport 3 ;
-- s_character <= transport
-- c_character_1 after 5 ns ;
--
when 4
=> correct :=
correct and
s_character =
c_character_1 and
(s_character_savt + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00336" ,
"One transport transaction occurred on a " &
"concurrent signal asg",
correct ) ;
test_report ( "ARCH00336" ,
"Old transactions were removed on a " &
"concurrent signal asg",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00336" ,
"Old transactions were removed on a " &
"concurrent signal asg",
false ) ;
--
end case ;
--
s_character_savt <= transport Std.Standard.Now ;
chk_character <= transport s_character_cnt
after (1 us - Std.Standard.Now) ;
s_character_cnt <= transport s_character_cnt + 1 ;
--
end process CHG4 ;
--
PGEN_CHKP_4 :
process ( chk_character )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P4" ,
"Transport transactions completed entirely",
chk_character = 4 ) ;
end if ;
end process PGEN_CHKP_4 ;
--
--
with character_select select
s_character <= transport
c_character_2 after 10 ns,
c_character_1 after 20 ns
when 1,
--
c_character_2 after 10 ns ,
c_character_1 after 20 ns ,
c_character_2 after 30 ns ,
c_character_1 after 40 ns
when 2,
--
c_character_1 after 5 ns when 3 ;
--
CHG5 :
process ( s_st_enum1 )
variable correct : boolean ;
begin
case s_st_enum1_cnt is
when 0
=> null ;
-- s_st_enum1 <= transport
-- c_st_enum1_2 after 10 ns,
-- c_st_enum1_1 after 20 ns ;
--
when 1
=> correct :=
s_st_enum1 =
c_st_enum1_2 and
(s_st_enum1_savt + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_enum1 =
c_st_enum1_1 and
(s_st_enum1_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00336.P5" ,
"Multi transport transactions occurred on " &
"concurrent signal asg",
correct ) ;
--
st_enum1_select <= transport 2 ;
-- s_st_enum1 <= transport
-- c_st_enum1_2 after 10 ns ,
-- c_st_enum1_1 after 20 ns ,
-- c_st_enum1_2 after 30 ns ,
-- c_st_enum1_1 after 40 ns ;
--
when 3
=> correct :=
s_st_enum1 =
c_st_enum1_2 and
(s_st_enum1_savt + 10 ns) = Std.Standard.Now ;
st_enum1_select <= transport 3 ;
-- s_st_enum1 <= transport
-- c_st_enum1_1 after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_enum1 =
c_st_enum1_1 and
(s_st_enum1_savt + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00336" ,
"One transport transaction occurred on a " &
"concurrent signal asg",
correct ) ;
test_report ( "ARCH00336" ,
"Old transactions were removed on a " &
"concurrent signal asg",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00336" ,
"Old transactions were removed on a " &
"concurrent signal asg",
false ) ;
--
end case ;
--
s_st_enum1_savt <= transport Std.Standard.Now ;
chk_st_enum1 <= transport s_st_enum1_cnt
after (1 us - Std.Standard.Now) ;
s_st_enum1_cnt <= transport s_st_enum1_cnt + 1 ;
--
end process CHG5 ;
--
PGEN_CHKP_5 :
process ( chk_st_enum1 )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P5" ,
"Transport transactions completed entirely",
chk_st_enum1 = 4 ) ;
end if ;
end process PGEN_CHKP_5 ;
--
--
with st_enum1_select select
s_st_enum1 <= transport
c_st_enum1_2 after 10 ns,
c_st_enum1_1 after 20 ns
when 1,
--
c_st_enum1_2 after 10 ns ,
c_st_enum1_1 after 20 ns ,
c_st_enum1_2 after 30 ns ,
c_st_enum1_1 after 40 ns
when 2,
--
c_st_enum1_1 after 5 ns when 3 ;
--
CHG6 :
process ( s_integer )
variable correct : boolean ;
begin
case s_integer_cnt is
when 0
=> null ;
-- s_integer <= transport
-- c_integer_2 after 10 ns,
-- c_integer_1 after 20 ns ;
--
when 1
=> correct :=
s_integer =
c_integer_2 and
(s_integer_savt + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_integer =
c_integer_1 and
(s_integer_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00336.P6" ,
"Multi transport transactions occurred on " &
"concurrent signal asg",
correct ) ;
--
integer_select <= transport 2 ;
-- s_integer <= transport
-- c_integer_2 after 10 ns ,
-- c_integer_1 after 20 ns ,
-- c_integer_2 after 30 ns ,
-- c_integer_1 after 40 ns ;
--
when 3
=> correct :=
s_integer =
c_integer_2 and
(s_integer_savt + 10 ns) = Std.Standard.Now ;
integer_select <= transport 3 ;
-- s_integer <= transport
-- c_integer_1 after 5 ns ;
--
when 4
=> correct :=
correct and
s_integer =
c_integer_1 and
(s_integer_savt + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00336" ,
"One transport transaction occurred on a " &
"concurrent signal asg",
correct ) ;
test_report ( "ARCH00336" ,
"Old transactions were removed on a " &
"concurrent signal asg",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00336" ,
"Old transactions were removed on a " &
"concurrent signal asg",
false ) ;
--
end case ;
--
s_integer_savt <= transport Std.Standard.Now ;
chk_integer <= transport s_integer_cnt
after (1 us - Std.Standard.Now) ;
s_integer_cnt <= transport s_integer_cnt + 1 ;
--
end process CHG6 ;
--
PGEN_CHKP_6 :
process ( chk_integer )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P6" ,
"Transport transactions completed entirely",
chk_integer = 4 ) ;
end if ;
end process PGEN_CHKP_6 ;
--
--
with integer_select select
s_integer <= transport
c_integer_2 after 10 ns,
c_integer_1 after 20 ns
when 1,
--
c_integer_2 after 10 ns ,
c_integer_1 after 20 ns ,
c_integer_2 after 30 ns ,
c_integer_1 after 40 ns
when 2,
--
c_integer_1 after 5 ns when 3 ;
--
CHG7 :
process ( s_st_int1 )
variable correct : boolean ;
begin
case s_st_int1_cnt is
when 0
=> null ;
-- s_st_int1 <= transport
-- c_st_int1_2 after 10 ns,
-- c_st_int1_1 after 20 ns ;
--
when 1
=> correct :=
s_st_int1 =
c_st_int1_2 and
(s_st_int1_savt + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_int1 =
c_st_int1_1 and
(s_st_int1_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00336.P7" ,
"Multi transport transactions occurred on " &
"concurrent signal asg",
correct ) ;
--
st_int1_select <= transport 2 ;
-- s_st_int1 <= transport
-- c_st_int1_2 after 10 ns ,
-- c_st_int1_1 after 20 ns ,
-- c_st_int1_2 after 30 ns ,
-- c_st_int1_1 after 40 ns ;
--
when 3
=> correct :=
s_st_int1 =
c_st_int1_2 and
(s_st_int1_savt + 10 ns) = Std.Standard.Now ;
st_int1_select <= transport 3 ;
-- s_st_int1 <= transport
-- c_st_int1_1 after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_int1 =
c_st_int1_1 and
(s_st_int1_savt + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00336" ,
"One transport transaction occurred on a " &
"concurrent signal asg",
correct ) ;
test_report ( "ARCH00336" ,
"Old transactions were removed on a " &
"concurrent signal asg",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00336" ,
"Old transactions were removed on a " &
"concurrent signal asg",
false ) ;
--
end case ;
--
s_st_int1_savt <= transport Std.Standard.Now ;
chk_st_int1 <= transport s_st_int1_cnt
after (1 us - Std.Standard.Now) ;
s_st_int1_cnt <= transport s_st_int1_cnt + 1 ;
--
end process CHG7 ;
--
PGEN_CHKP_7 :
process ( chk_st_int1 )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P7" ,
"Transport transactions completed entirely",
chk_st_int1 = 4 ) ;
end if ;
end process PGEN_CHKP_7 ;
--
--
with st_int1_select select
s_st_int1 <= transport
c_st_int1_2 after 10 ns,
c_st_int1_1 after 20 ns
when 1,
--
c_st_int1_2 after 10 ns ,
c_st_int1_1 after 20 ns ,
c_st_int1_2 after 30 ns ,
c_st_int1_1 after 40 ns
when 2,
--
c_st_int1_1 after 5 ns when 3 ;
--
CHG8 :
process ( s_time )
variable correct : boolean ;
begin
case s_time_cnt is
when 0
=> null ;
-- s_time <= transport
-- c_time_2 after 10 ns,
-- c_time_1 after 20 ns ;
--
when 1
=> correct :=
s_time =
c_time_2 and
(s_time_savt + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_time =
c_time_1 and
(s_time_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00336.P8" ,
"Multi transport transactions occurred on " &
"concurrent signal asg",
correct ) ;
--
time_select <= transport 2 ;
-- s_time <= transport
-- c_time_2 after 10 ns ,
-- c_time_1 after 20 ns ,
-- c_time_2 after 30 ns ,
-- c_time_1 after 40 ns ;
--
when 3
=> correct :=
s_time =
c_time_2 and
(s_time_savt + 10 ns) = Std.Standard.Now ;
time_select <= transport 3 ;
-- s_time <= transport
-- c_time_1 after 5 ns ;
--
when 4
=> correct :=
correct and
s_time =
c_time_1 and
(s_time_savt + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00336" ,
"One transport transaction occurred on a " &
"concurrent signal asg",
correct ) ;
test_report ( "ARCH00336" ,
"Old transactions were removed on a " &
"concurrent signal asg",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00336" ,
"Old transactions were removed on a " &
"concurrent signal asg",
false ) ;
--
end case ;
--
s_time_savt <= transport Std.Standard.Now ;
chk_time <= transport s_time_cnt
after (1 us - Std.Standard.Now) ;
s_time_cnt <= transport s_time_cnt + 1 ;
--
end process CHG8 ;
--
PGEN_CHKP_8 :
process ( chk_time )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P8" ,
"Transport transactions completed entirely",
chk_time = 4 ) ;
end if ;
end process PGEN_CHKP_8 ;
--
--
with time_select select
s_time <= transport
c_time_2 after 10 ns,
c_time_1 after 20 ns
when 1,
--
c_time_2 after 10 ns ,
c_time_1 after 20 ns ,
c_time_2 after 30 ns ,
c_time_1 after 40 ns
when 2,
--
c_time_1 after 5 ns when 3 ;
--
CHG9 :
process ( s_st_phys1 )
variable correct : boolean ;
begin
case s_st_phys1_cnt is
when 0
=> null ;
-- s_st_phys1 <= transport
-- c_st_phys1_2 after 10 ns,
-- c_st_phys1_1 after 20 ns ;
--
when 1
=> correct :=
s_st_phys1 =
c_st_phys1_2 and
(s_st_phys1_savt + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_phys1 =
c_st_phys1_1 and
(s_st_phys1_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00336.P9" ,
"Multi transport transactions occurred on " &
"concurrent signal asg",
correct ) ;
--
st_phys1_select <= transport 2 ;
-- s_st_phys1 <= transport
-- c_st_phys1_2 after 10 ns ,
-- c_st_phys1_1 after 20 ns ,
-- c_st_phys1_2 after 30 ns ,
-- c_st_phys1_1 after 40 ns ;
--
when 3
=> correct :=
s_st_phys1 =
c_st_phys1_2 and
(s_st_phys1_savt + 10 ns) = Std.Standard.Now ;
st_phys1_select <= transport 3 ;
-- s_st_phys1 <= transport
-- c_st_phys1_1 after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_phys1 =
c_st_phys1_1 and
(s_st_phys1_savt + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00336" ,
"One transport transaction occurred on a " &
"concurrent signal asg",
correct ) ;
test_report ( "ARCH00336" ,
"Old transactions were removed on a " &
"concurrent signal asg",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00336" ,
"Old transactions were removed on a " &
"concurrent signal asg",
false ) ;
--
end case ;
--
s_st_phys1_savt <= transport Std.Standard.Now ;
chk_st_phys1 <= transport s_st_phys1_cnt
after (1 us - Std.Standard.Now) ;
s_st_phys1_cnt <= transport s_st_phys1_cnt + 1 ;
--
end process CHG9 ;
--
PGEN_CHKP_9 :
process ( chk_st_phys1 )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P9" ,
"Transport transactions completed entirely",
chk_st_phys1 = 4 ) ;
end if ;
end process PGEN_CHKP_9 ;
--
--
with st_phys1_select select
s_st_phys1 <= transport
c_st_phys1_2 after 10 ns,
c_st_phys1_1 after 20 ns
when 1,
--
c_st_phys1_2 after 10 ns ,
c_st_phys1_1 after 20 ns ,
c_st_phys1_2 after 30 ns ,
c_st_phys1_1 after 40 ns
when 2,
--
c_st_phys1_1 after 5 ns when 3 ;
--
CHG10 :
process ( s_real )
variable correct : boolean ;
begin
case s_real_cnt is
when 0
=> null ;
-- s_real <= transport
-- c_real_2 after 10 ns,
-- c_real_1 after 20 ns ;
--
when 1
=> correct :=
s_real =
c_real_2 and
(s_real_savt + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_real =
c_real_1 and
(s_real_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00336.P10" ,
"Multi transport transactions occurred on " &
"concurrent signal asg",
correct ) ;
--
real_select <= transport 2 ;
-- s_real <= transport
-- c_real_2 after 10 ns ,
-- c_real_1 after 20 ns ,
-- c_real_2 after 30 ns ,
-- c_real_1 after 40 ns ;
--
when 3
=> correct :=
s_real =
c_real_2 and
(s_real_savt + 10 ns) = Std.Standard.Now ;
real_select <= transport 3 ;
-- s_real <= transport
-- c_real_1 after 5 ns ;
--
when 4
=> correct :=
correct and
s_real =
c_real_1 and
(s_real_savt + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00336" ,
"One transport transaction occurred on a " &
"concurrent signal asg",
correct ) ;
test_report ( "ARCH00336" ,
"Old transactions were removed on a " &
"concurrent signal asg",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00336" ,
"Old transactions were removed on a " &
"concurrent signal asg",
false ) ;
--
end case ;
--
s_real_savt <= transport Std.Standard.Now ;
chk_real <= transport s_real_cnt
after (1 us - Std.Standard.Now) ;
s_real_cnt <= transport s_real_cnt + 1 ;
--
end process CHG10 ;
--
PGEN_CHKP_10 :
process ( chk_real )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P10" ,
"Transport transactions completed entirely",
chk_real = 4 ) ;
end if ;
end process PGEN_CHKP_10 ;
--
--
with real_select select
s_real <= transport
c_real_2 after 10 ns,
c_real_1 after 20 ns
when 1,
--
c_real_2 after 10 ns ,
c_real_1 after 20 ns ,
c_real_2 after 30 ns ,
c_real_1 after 40 ns
when 2,
--
c_real_1 after 5 ns when 3 ;
--
CHG11 :
process ( s_st_real1 )
variable correct : boolean ;
begin
case s_st_real1_cnt is
when 0
=> null ;
-- s_st_real1 <= transport
-- c_st_real1_2 after 10 ns,
-- c_st_real1_1 after 20 ns ;
--
when 1
=> correct :=
s_st_real1 =
c_st_real1_2 and
(s_st_real1_savt + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_real1 =
c_st_real1_1 and
(s_st_real1_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00336.P11" ,
"Multi transport transactions occurred on " &
"concurrent signal asg",
correct ) ;
--
st_real1_select <= transport 2 ;
-- s_st_real1 <= transport
-- c_st_real1_2 after 10 ns ,
-- c_st_real1_1 after 20 ns ,
-- c_st_real1_2 after 30 ns ,
-- c_st_real1_1 after 40 ns ;
--
when 3
=> correct :=
s_st_real1 =
c_st_real1_2 and
(s_st_real1_savt + 10 ns) = Std.Standard.Now ;
st_real1_select <= transport 3 ;
-- s_st_real1 <= transport
-- c_st_real1_1 after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_real1 =
c_st_real1_1 and
(s_st_real1_savt + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00336" ,
"One transport transaction occurred on a " &
"concurrent signal asg",
correct ) ;
test_report ( "ARCH00336" ,
"Old transactions were removed on a " &
"concurrent signal asg",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00336" ,
"Old transactions were removed on a " &
"concurrent signal asg",
false ) ;
--
end case ;
--
s_st_real1_savt <= transport Std.Standard.Now ;
chk_st_real1 <= transport s_st_real1_cnt
after (1 us - Std.Standard.Now) ;
s_st_real1_cnt <= transport s_st_real1_cnt + 1 ;
--
end process CHG11 ;
--
PGEN_CHKP_11 :
process ( chk_st_real1 )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P11" ,
"Transport transactions completed entirely",
chk_st_real1 = 4 ) ;
end if ;
end process PGEN_CHKP_11 ;
--
--
with st_real1_select select
s_st_real1 <= transport
c_st_real1_2 after 10 ns,
c_st_real1_1 after 20 ns
when 1,
--
c_st_real1_2 after 10 ns ,
c_st_real1_1 after 20 ns ,
c_st_real1_2 after 30 ns ,
c_st_real1_1 after 40 ns
when 2,
--
c_st_real1_1 after 5 ns when 3 ;
--
CHG12 :
process ( s_st_rec1 )
variable correct : boolean ;
begin
case s_st_rec1_cnt is
when 0
=> null ;
-- s_st_rec1 <= transport
-- c_st_rec1_2 after 10 ns,
-- c_st_rec1_1 after 20 ns ;
--
when 1
=> correct :=
s_st_rec1 =
c_st_rec1_2 and
(s_st_rec1_savt + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_rec1 =
c_st_rec1_1 and
(s_st_rec1_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00336.P12" ,
"Multi transport transactions occurred on " &
"concurrent signal asg",
correct ) ;
--
st_rec1_select <= transport 2 ;
-- s_st_rec1 <= transport
-- c_st_rec1_2 after 10 ns ,
-- c_st_rec1_1 after 20 ns ,
-- c_st_rec1_2 after 30 ns ,
-- c_st_rec1_1 after 40 ns ;
--
when 3
=> correct :=
s_st_rec1 =
c_st_rec1_2 and
(s_st_rec1_savt + 10 ns) = Std.Standard.Now ;
st_rec1_select <= transport 3 ;
-- s_st_rec1 <= transport
-- c_st_rec1_1 after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_rec1 =
c_st_rec1_1 and
(s_st_rec1_savt + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00336" ,
"One transport transaction occurred on a " &
"concurrent signal asg",
correct ) ;
test_report ( "ARCH00336" ,
"Old transactions were removed on a " &
"concurrent signal asg",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00336" ,
"Old transactions were removed on a " &
"concurrent signal asg",
false ) ;
--
end case ;
--
s_st_rec1_savt <= transport Std.Standard.Now ;
chk_st_rec1 <= transport s_st_rec1_cnt
after (1 us - Std.Standard.Now) ;
s_st_rec1_cnt <= transport s_st_rec1_cnt + 1 ;
--
end process CHG12 ;
--
PGEN_CHKP_12 :
process ( chk_st_rec1 )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P12" ,
"Transport transactions completed entirely",
chk_st_rec1 = 4 ) ;
end if ;
end process PGEN_CHKP_12 ;
--
--
with st_rec1_select select
s_st_rec1 <= transport
c_st_rec1_2 after 10 ns,
c_st_rec1_1 after 20 ns
when 1,
--
c_st_rec1_2 after 10 ns ,
c_st_rec1_1 after 20 ns ,
c_st_rec1_2 after 30 ns ,
c_st_rec1_1 after 40 ns
when 2,
--
c_st_rec1_1 after 5 ns when 3 ;
--
CHG13 :
process ( s_st_rec2 )
variable correct : boolean ;
begin
case s_st_rec2_cnt is
when 0
=> null ;
-- s_st_rec2 <= transport
-- c_st_rec2_2 after 10 ns,
-- c_st_rec2_1 after 20 ns ;
--
when 1
=> correct :=
s_st_rec2 =
c_st_rec2_2 and
(s_st_rec2_savt + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_rec2 =
c_st_rec2_1 and
(s_st_rec2_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00336.P13" ,
"Multi transport transactions occurred on " &
"concurrent signal asg",
correct ) ;
--
st_rec2_select <= transport 2 ;
-- s_st_rec2 <= transport
-- c_st_rec2_2 after 10 ns ,
-- c_st_rec2_1 after 20 ns ,
-- c_st_rec2_2 after 30 ns ,
-- c_st_rec2_1 after 40 ns ;
--
when 3
=> correct :=
s_st_rec2 =
c_st_rec2_2 and
(s_st_rec2_savt + 10 ns) = Std.Standard.Now ;
st_rec2_select <= transport 3 ;
-- s_st_rec2 <= transport
-- c_st_rec2_1 after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_rec2 =
c_st_rec2_1 and
(s_st_rec2_savt + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00336" ,
"One transport transaction occurred on a " &
"concurrent signal asg",
correct ) ;
test_report ( "ARCH00336" ,
"Old transactions were removed on a " &
"concurrent signal asg",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00336" ,
"Old transactions were removed on a " &
"concurrent signal asg",
false ) ;
--
end case ;
--
s_st_rec2_savt <= transport Std.Standard.Now ;
chk_st_rec2 <= transport s_st_rec2_cnt
after (1 us - Std.Standard.Now) ;
s_st_rec2_cnt <= transport s_st_rec2_cnt + 1 ;
--
end process CHG13 ;
--
PGEN_CHKP_13 :
process ( chk_st_rec2 )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P13" ,
"Transport transactions completed entirely",
chk_st_rec2 = 4 ) ;
end if ;
end process PGEN_CHKP_13 ;
--
--
with st_rec2_select select
s_st_rec2 <= transport
c_st_rec2_2 after 10 ns,
c_st_rec2_1 after 20 ns
when 1,
--
c_st_rec2_2 after 10 ns ,
c_st_rec2_1 after 20 ns ,
c_st_rec2_2 after 30 ns ,
c_st_rec2_1 after 40 ns
when 2,
--
c_st_rec2_1 after 5 ns when 3 ;
--
CHG14 :
process ( s_st_rec3 )
variable correct : boolean ;
begin
case s_st_rec3_cnt is
when 0
=> null ;
-- s_st_rec3 <= transport
-- c_st_rec3_2 after 10 ns,
-- c_st_rec3_1 after 20 ns ;
--
when 1
=> correct :=
s_st_rec3 =
c_st_rec3_2 and
(s_st_rec3_savt + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_rec3 =
c_st_rec3_1 and
(s_st_rec3_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00336.P14" ,
"Multi transport transactions occurred on " &
"concurrent signal asg",
correct ) ;
--
st_rec3_select <= transport 2 ;
-- s_st_rec3 <= transport
-- c_st_rec3_2 after 10 ns ,
-- c_st_rec3_1 after 20 ns ,
-- c_st_rec3_2 after 30 ns ,
-- c_st_rec3_1 after 40 ns ;
--
when 3
=> correct :=
s_st_rec3 =
c_st_rec3_2 and
(s_st_rec3_savt + 10 ns) = Std.Standard.Now ;
st_rec3_select <= transport 3 ;
-- s_st_rec3 <= transport
-- c_st_rec3_1 after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_rec3 =
c_st_rec3_1 and
(s_st_rec3_savt + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00336" ,
"One transport transaction occurred on a " &
"concurrent signal asg",
correct ) ;
test_report ( "ARCH00336" ,
"Old transactions were removed on a " &
"concurrent signal asg",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00336" ,
"Old transactions were removed on a " &
"concurrent signal asg",
false ) ;
--
end case ;
--
s_st_rec3_savt <= transport Std.Standard.Now ;
chk_st_rec3 <= transport s_st_rec3_cnt
after (1 us - Std.Standard.Now) ;
s_st_rec3_cnt <= transport s_st_rec3_cnt + 1 ;
--
end process CHG14 ;
--
PGEN_CHKP_14 :
process ( chk_st_rec3 )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P14" ,
"Transport transactions completed entirely",
chk_st_rec3 = 4 ) ;
end if ;
end process PGEN_CHKP_14 ;
--
--
with st_rec3_select select
s_st_rec3 <= transport
c_st_rec3_2 after 10 ns,
c_st_rec3_1 after 20 ns
when 1,
--
c_st_rec3_2 after 10 ns ,
c_st_rec3_1 after 20 ns ,
c_st_rec3_2 after 30 ns ,
c_st_rec3_1 after 40 ns
when 2,
--
c_st_rec3_1 after 5 ns when 3 ;
--
CHG15 :
process ( s_st_arr1 )
variable correct : boolean ;
begin
case s_st_arr1_cnt is
when 0
=> null ;
-- s_st_arr1 <= transport
-- c_st_arr1_2 after 10 ns,
-- c_st_arr1_1 after 20 ns ;
--
when 1
=> correct :=
s_st_arr1 =
c_st_arr1_2 and
(s_st_arr1_savt + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_arr1 =
c_st_arr1_1 and
(s_st_arr1_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00336.P15" ,
"Multi transport transactions occurred on " &
"concurrent signal asg",
correct ) ;
--
st_arr1_select <= transport 2 ;
-- s_st_arr1 <= transport
-- c_st_arr1_2 after 10 ns ,
-- c_st_arr1_1 after 20 ns ,
-- c_st_arr1_2 after 30 ns ,
-- c_st_arr1_1 after 40 ns ;
--
when 3
=> correct :=
s_st_arr1 =
c_st_arr1_2 and
(s_st_arr1_savt + 10 ns) = Std.Standard.Now ;
st_arr1_select <= transport 3 ;
-- s_st_arr1 <= transport
-- c_st_arr1_1 after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_arr1 =
c_st_arr1_1 and
(s_st_arr1_savt + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00336" ,
"One transport transaction occurred on a " &
"concurrent signal asg",
correct ) ;
test_report ( "ARCH00336" ,
"Old transactions were removed on a " &
"concurrent signal asg",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00336" ,
"Old transactions were removed on a " &
"concurrent signal asg",
false ) ;
--
end case ;
--
s_st_arr1_savt <= transport Std.Standard.Now ;
chk_st_arr1 <= transport s_st_arr1_cnt
after (1 us - Std.Standard.Now) ;
s_st_arr1_cnt <= transport s_st_arr1_cnt + 1 ;
--
end process CHG15 ;
--
PGEN_CHKP_15 :
process ( chk_st_arr1 )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P15" ,
"Transport transactions completed entirely",
chk_st_arr1 = 4 ) ;
end if ;
end process PGEN_CHKP_15 ;
--
--
with st_arr1_select select
s_st_arr1 <= transport
c_st_arr1_2 after 10 ns,
c_st_arr1_1 after 20 ns
when 1,
--
c_st_arr1_2 after 10 ns ,
c_st_arr1_1 after 20 ns ,
c_st_arr1_2 after 30 ns ,
c_st_arr1_1 after 40 ns
when 2,
--
c_st_arr1_1 after 5 ns when 3 ;
--
CHG16 :
process ( s_st_arr2 )
variable correct : boolean ;
begin
case s_st_arr2_cnt is
when 0
=> null ;
-- s_st_arr2 <= transport
-- c_st_arr2_2 after 10 ns,
-- c_st_arr2_1 after 20 ns ;
--
when 1
=> correct :=
s_st_arr2 =
c_st_arr2_2 and
(s_st_arr2_savt + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_arr2 =
c_st_arr2_1 and
(s_st_arr2_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00336.P16" ,
"Multi transport transactions occurred on " &
"concurrent signal asg",
correct ) ;
--
st_arr2_select <= transport 2 ;
-- s_st_arr2 <= transport
-- c_st_arr2_2 after 10 ns ,
-- c_st_arr2_1 after 20 ns ,
-- c_st_arr2_2 after 30 ns ,
-- c_st_arr2_1 after 40 ns ;
--
when 3
=> correct :=
s_st_arr2 =
c_st_arr2_2 and
(s_st_arr2_savt + 10 ns) = Std.Standard.Now ;
st_arr2_select <= transport 3 ;
-- s_st_arr2 <= transport
-- c_st_arr2_1 after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_arr2 =
c_st_arr2_1 and
(s_st_arr2_savt + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00336" ,
"One transport transaction occurred on a " &
"concurrent signal asg",
correct ) ;
test_report ( "ARCH00336" ,
"Old transactions were removed on a " &
"concurrent signal asg",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00336" ,
"Old transactions were removed on a " &
"concurrent signal asg",
false ) ;
--
end case ;
--
s_st_arr2_savt <= transport Std.Standard.Now ;
chk_st_arr2 <= transport s_st_arr2_cnt
after (1 us - Std.Standard.Now) ;
s_st_arr2_cnt <= transport s_st_arr2_cnt + 1 ;
--
end process CHG16 ;
--
PGEN_CHKP_16 :
process ( chk_st_arr2 )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P16" ,
"Transport transactions completed entirely",
chk_st_arr2 = 4 ) ;
end if ;
end process PGEN_CHKP_16 ;
--
--
with st_arr2_select select
s_st_arr2 <= transport
c_st_arr2_2 after 10 ns,
c_st_arr2_1 after 20 ns
when 1,
--
c_st_arr2_2 after 10 ns ,
c_st_arr2_1 after 20 ns ,
c_st_arr2_2 after 30 ns ,
c_st_arr2_1 after 40 ns
when 2,
--
c_st_arr2_1 after 5 ns when 3 ;
--
CHG17 :
process ( s_st_arr3 )
variable correct : boolean ;
begin
case s_st_arr3_cnt is
when 0
=> null ;
-- s_st_arr3 <= transport
-- c_st_arr3_2 after 10 ns,
-- c_st_arr3_1 after 20 ns ;
--
when 1
=> correct :=
s_st_arr3 =
c_st_arr3_2 and
(s_st_arr3_savt + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_arr3 =
c_st_arr3_1 and
(s_st_arr3_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00336.P17" ,
"Multi transport transactions occurred on " &
"concurrent signal asg",
correct ) ;
--
st_arr3_select <= transport 2 ;
-- s_st_arr3 <= transport
-- c_st_arr3_2 after 10 ns ,
-- c_st_arr3_1 after 20 ns ,
-- c_st_arr3_2 after 30 ns ,
-- c_st_arr3_1 after 40 ns ;
--
when 3
=> correct :=
s_st_arr3 =
c_st_arr3_2 and
(s_st_arr3_savt + 10 ns) = Std.Standard.Now ;
st_arr3_select <= transport 3 ;
-- s_st_arr3 <= transport
-- c_st_arr3_1 after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_arr3 =
c_st_arr3_1 and
(s_st_arr3_savt + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00336" ,
"One transport transaction occurred on a " &
"concurrent signal asg",
correct ) ;
test_report ( "ARCH00336" ,
"Old transactions were removed on a " &
"concurrent signal asg",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00336" ,
"Old transactions were removed on a " &
"concurrent signal asg",
false ) ;
--
end case ;
--
s_st_arr3_savt <= transport Std.Standard.Now ;
chk_st_arr3 <= transport s_st_arr3_cnt
after (1 us - Std.Standard.Now) ;
s_st_arr3_cnt <= transport s_st_arr3_cnt + 1 ;
--
end process CHG17 ;
--
PGEN_CHKP_17 :
process ( chk_st_arr3 )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P17" ,
"Transport transactions completed entirely",
chk_st_arr3 = 4 ) ;
end if ;
end process PGEN_CHKP_17 ;
--
--
with st_arr3_select select
s_st_arr3 <= transport
c_st_arr3_2 after 10 ns,
c_st_arr3_1 after 20 ns
when 1,
--
c_st_arr3_2 after 10 ns ,
c_st_arr3_1 after 20 ns ,
c_st_arr3_2 after 30 ns ,
c_st_arr3_1 after 40 ns
when 2,
--
c_st_arr3_1 after 5 ns when 3 ;
--
end ARCH00336 ;
--
--
use WORK.STANDARD_TYPES.all ;
entity ENT00336_Test_Bench is
end ENT00336_Test_Bench ;
--
--
architecture ARCH00336_Test_Bench of ENT00336_Test_Bench is
begin
L1:
block
component UUT
end component ;
--
for CIS1 : UUT use entity WORK.ENT00336 ( ARCH00336 ) ;
begin
CIS1 : UUT
;
end block L1 ;
end ARCH00336_Test_Bench ;
| gpl-3.0 | 6cff74cbef33cd99c02053b6cbae80ab | 0.488999 | 3.734904 | false | false | false | false |
grwlf/vsim | vhdl_ct/ct00019.vhd | 1 | 12,523 | -- NEED RESULT: ARCH00019: Wait in P1_1 did resume passed
-- NEED RESULT: ARCH00019: Wait in P1_2 did resume passed
-- NEED RESULT: ARCH00019: Wait in P2_1 did resume passed
-- NEED RESULT: ARCH00019: Wait in P2_2 did resume passed
-- NEED RESULT: ARCH00019: Wait in P3_1 did resume passed
-- NEED RESULT: ARCH00019: Wait in P3_2 did resume passed
-- NEED RESULT: ARCH00019: Wait in R1_1 did resume passed
-- NEED RESULT: ARCH00019: Wait in R1_2 did resume passed
-- NEED RESULT: ARCH00019: Wait in PROC1_1 did resume passed
-- NEED RESULT: ARCH00019: Wait in PROC1_2 did resume passed
-- NEED RESULT: ARCH00019: Wait in PROC2_1 did resume passed
-- NEED RESULT: ARCH00019: Wait in PROC2_2 did resume passed
-- NEED RESULT: ARCH00019: Wait in PROC3_1 did resume passed
-- NEED RESULT: ARCH00019: Wait in PROC3_2 did resume passed
-- NEED RESULT: ARCH00019: Wait in PROC4_1 did resume passed
-- NEED RESULT: ARCH00019: Wait in PROC4_2 did resume passed
-------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
-------------------------------------------------------------------------------
--
-- TEST NAME:
--
-- CT00019
--
-- AUTHOR:
--
-- G. Tominovich
--
-- TEST OBJECTIVES:
--
-- 8.1 (9)
--
-- DESIGN UNIT ORDERING:
--
-- ENT00019(ARCH00019)
-- ENT00019_Test_Bench(ARCH00019_Test_Bench)
--
-- REVISION HISTORY:
--
-- 26-JUN-1987 - initial revision
--
-- NOTES:
--
-- self-checking
--
use WORK.STANDARD_TYPES.all ;
entity ENT00019 is
generic ( G1 : Time := 10 ns ) ;
port ( P1 : in Time := 10 ns ) ;
end ENT00019 ;
architecture ARCH00019 of ENT00019 is
signal Pulse1, Pulse2, Pulse3 : Boolean := false ;
signal TestIt : Boolean := false;
signal P1_1_Did_Resume, P1_2_Did_Resume : Boolean := false ;
signal P2_1_Did_Resume, P2_2_Did_Resume : Boolean := false ;
signal P3_1_Did_Resume, P3_2_Did_Resume : Boolean := false ;
signal R1_1_Did_Resume, R1_2_Did_Resume : Boolean := false ;
signal PROC1_1_Did_Resume, PROC1_2_Did_Resume : Boolean := false ;
signal PROC2_1_Did_Resume, PROC2_2_Did_Resume : Boolean := false ;
signal PROC3_1_Did_Resume, PROC3_2_Did_Resume : Boolean := false ;
signal PROC4_1_Did_Resume, PROC4_2_Did_Resume : Boolean := false ;
constant Time_To_Wait : Time := 10 ns ;
procedure PROC1_1 ( Signal Resume_Chk : inout boolean ) is
begin
wait on Pulse1,Pulse2,Pulse3 until (Pulse1 and Pulse2 and Pulse3)
for Time_To_Wait ;
if Pulse1 and Pulse2 and Pulse3 then
Resume_Chk <= transport True ;
else
test_report ( "ARCH00019" ,
"Wait in PROC1_1 resumed when condition was false" ,
false ) ;
end if ;
end PROC1_1 ;
procedure PROC1_2 ( Signal Resume_Chk : inout boolean ) is
begin
wait until (Pulse1 and Pulse2 and Pulse3) for Time_To_Wait ;
if Pulse1 and Pulse2 and Pulse3 then
Resume_Chk <= transport True ;
else
test_report ( "ARCH00019" ,
"Wait in PROC1_2 resumed when condition was false" ,
false ) ;
end if ;
end PROC1_2 ;
procedure PROC2_1 ( Signal Resume_Chk : inout boolean ) is
begin
wait on Pulse1,Pulse2,Pulse3 until (Pulse1 and Pulse2 and Pulse3)
for G1 ;
if Pulse1 and Pulse2 and Pulse3 then
Resume_Chk <= transport True ;
else
test_report ( "ARCH00019" ,
"Wait in PROC2_1 resumed when condition was false" ,
false ) ;
end if ;
end PROC2_1 ;
procedure PROC2_2 ( Signal Resume_Chk : inout boolean ) is
begin
wait until (Pulse1 and Pulse2 and Pulse3) for G1 ;
if Pulse1 and Pulse2 and Pulse3 then
Resume_Chk <= transport True ;
else
test_report ( "ARCH00019" ,
"Wait in PROC2_2 resumed when condition was false" ,
false ) ;
end if ;
end PROC2_2 ;
procedure PROC3_1 ( Signal Resume_Chk : inout boolean ) is
begin
wait on Pulse1,Pulse2,Pulse3 until (Pulse1 and Pulse2 and Pulse3)
for P1 ;
if Pulse1 and Pulse2 and Pulse3 then
Resume_Chk <= transport True ;
else
test_report ( "ARCH00019" ,
"Wait in PROC3_1 resumed when condition was false" ,
false ) ;
end if ;
end PROC3_1 ;
procedure PROC3_2 ( Signal Resume_Chk : inout boolean ) is
begin
wait until (Pulse1 and Pulse2 and Pulse3) for P1 ;
if Pulse1 and Pulse2 and Pulse3 then
Resume_Chk <= transport True ;
else
test_report ( "ARCH00019" ,
"Wait in PROC3_2 resumed when condition was false" ,
false ) ;
end if ;
end PROC3_2 ;
procedure PROC4_1 (Time_To_Wait : Time ;
signal Pulse1, Pulse2, Pulse3 : Boolean ;
signal Resume_Chk : inout boolean) is
begin
wait on Pulse1,Pulse2,Pulse3 until (Pulse1 and Pulse2 and Pulse3)
for Time_To_Wait ;
if Pulse1 and Pulse2 and Pulse3 then
Resume_Chk <= transport True ;
else
test_report ( "ARCH00019" ,
"Wait in PROC4_1 resumed when condition was false" ,
false ) ;
end if ;
end PROC4_1 ;
procedure PROC4_2 (Time_To_Wait : Time;
signal Pulse1, Pulse2, Pulse3 : Boolean ;
signal Resume_Chk : inout boolean) is
begin
wait until (Pulse1 and Pulse2 and Pulse3) for Time_To_Wait ;
if Pulse1 and Pulse2 and Pulse3 then
Resume_Chk <= transport True ;
else
test_report ( "ARCH00019" ,
"Wait in PROC4_2 resumed when condition was false" ,
false ) ;
end if ;
end PROC4_2 ;
begin
Test_Control :
process ( Pulse1, Pulse2, Pulse3, TestIt)
begin
if not Pulse1 then
Pulse1 <= transport not Pulse1 after 1 ns ;
elsif not Pulse2 then
Pulse2 <= transport not Pulse2 after 1 ns ;
elsif not Pulse3 then
Pulse3 <= transport not Pulse3 after 1 ns ;
TestIt <= transport TRUE after 2 ns;
elsif TestIt then
-- Verify that in fact, all of the wait statements resumed
test_report ( "ARCH00019" ,
"Wait in P1_1 did resume" ,
P1_1_Did_Resume ) ;
test_report ( "ARCH00019" ,
"Wait in P1_2 did resume" ,
P1_2_Did_Resume ) ;
test_report ( "ARCH00019" ,
"Wait in P2_1 did resume" ,
P2_1_Did_Resume ) ;
test_report ( "ARCH00019" ,
"Wait in P2_2 did resume" ,
P2_2_Did_Resume ) ;
test_report ( "ARCH00019" ,
"Wait in P3_1 did resume" ,
P3_1_Did_Resume ) ;
test_report ( "ARCH00019" ,
"Wait in P3_2 did resume" ,
P3_2_Did_Resume ) ;
test_report ( "ARCH00019" ,
"Wait in R1_1 did resume" ,
R1_1_Did_Resume ) ;
test_report ( "ARCH00019" ,
"Wait in R1_2 did resume" ,
R1_2_Did_Resume ) ;
test_report ( "ARCH00019" ,
"Wait in PROC1_1 did resume" ,
PROC1_1_Did_Resume ) ;
test_report ( "ARCH00019" ,
"Wait in PROC1_2 did resume" ,
PROC1_2_Did_Resume ) ;
test_report ( "ARCH00019" ,
"Wait in PROC2_1 did resume" ,
PROC2_1_Did_Resume ) ;
test_report ( "ARCH00019" ,
"Wait in PROC2_2 did resume" ,
PROC2_2_Did_Resume ) ;
test_report ( "ARCH00019" ,
"Wait in PROC3_1 did resume" ,
PROC3_1_Did_Resume ) ;
test_report ( "ARCH00019" ,
"Wait in PROC3_2 did resume" ,
PROC3_2_Did_Resume ) ;
test_report ( "ARCH00019" ,
"Wait in PROC4_1 did resume" ,
PROC4_1_Did_Resume ) ;
test_report ( "ARCH00019" ,
"Wait in PROC4_2 did resume" ,
PROC4_2_Did_Resume ) ;
end if ;
end process Test_Control ;
P1_1 :
process
begin
wait on Pulse1,Pulse2,Pulse3 until (Pulse1 and Pulse2 and Pulse3)
for Time_To_Wait ;
if Pulse1 and Pulse2 and Pulse3 then
P1_1_Did_Resume <= transport True ;
else
test_report ( "ARCH00019" ,
"Wait in P1_1 resumed when condition was false" ,
false ) ;
end if ;
wait;
end process P1_1 ;
P1_2 :
process
begin
wait until (Pulse1 and Pulse2 and Pulse3) for Time_To_Wait ;
if Pulse1 and Pulse2 and Pulse3 then
P1_2_Did_Resume <= transport True ;
else
test_report ( "ARCH00019" ,
"Wait in P1_2 resumed when condition was false" ,
false ) ;
end if ;
wait;
end process P1_2 ;
P2_1 :
process
begin
wait on Pulse1,Pulse2,Pulse3 until (Pulse1 and Pulse2 and Pulse3)
for G1 ;
if Pulse1 and Pulse2 and Pulse3 then
P2_1_Did_Resume <= transport True ;
else
test_report ( "ARCH00019" ,
"Wait in P2_1 resumed when condition was false" ,
false ) ;
end if ;
wait;
end process P2_1 ;
P2_2 :
process
begin
wait until (Pulse1 and Pulse2 and Pulse3) for G1 ;
if Pulse1 and Pulse2 and Pulse3 then
P2_2_Did_Resume <= transport True ;
else
test_report ( "ARCH00019" ,
"Wait in P2_2 resumed when condition was false" ,
false ) ;
end if ;
wait;
end process P2_2 ;
P3_1 :
process
begin
wait on Pulse1,Pulse2,Pulse3 until (Pulse1 and Pulse2 and Pulse3)
for P1 ;
if Pulse1 and Pulse2 and Pulse3 then
P3_1_Did_Resume <= transport True ;
else
test_report ( "ARCH00019" ,
"Wait in P3_1 resumed when condition was false" ,
false ) ;
end if ;
wait;
end process P3_1 ;
P3_2 :
process
begin
wait until (Pulse1 and Pulse2 and Pulse3) for P1 ;
if Pulse1 and Pulse2 and Pulse3 then
P3_2_Did_Resume <= transport True ;
else
test_report ( "ARCH00019" ,
"Wait in P3_2 resumed when condition was false" ,
false ) ;
end if ;
wait;
end process P3_2 ;
Q1_1 :
process
begin
PROC1_1 (PROC1_1_Did_Resume) ;
wait;
end process Q1_1 ;
Q1_2 :
process
begin
PROC1_2 (PROC1_2_Did_Resume) ;
wait;
end process Q1_2 ;
Q2_1 :
process
begin
PROC2_1 (PROC2_1_Did_Resume) ;
wait;
end process Q2_1 ;
Q2_2 :
process
begin
PROC2_2 (PROC2_2_Did_Resume) ;
wait;
end process Q2_2 ;
Q3_1 :
process
begin
PROC3_1 (PROC3_1_Did_Resume) ;
wait;
end process Q3_1 ;
Q3_2 :
process
begin
PROC3_2 (PROC3_2_Did_Resume) ;
wait;
end process Q3_2 ;
Q4_1 :
process
begin
PROC4_1 (Time_To_Wait, Pulse1, Pulse2, Pulse3, PROC4_1_Did_Resume) ;
wait;
end process Q4_1 ;
Q4_2 :
process
begin
PROC4_2 (P1, Pulse1, Pulse2, Pulse3, PROC4_2_Did_Resume) ;
wait;
end process Q4_2 ;
R1_1 :
process
begin
wait on Pulse1,Pulse2,Pulse3 until (Pulse1 and Pulse2 and Pulse3) ;
if Pulse1 and Pulse2 and Pulse3 then
R1_1_Did_Resume <= transport True ;
else
test_report ( "ARCH00019" ,
"Wait in R1_1 resumed when condition was false" ,
false ) ;
end if ;
wait;
end process R1_1 ;
R1_2 :
process
begin
wait until (Pulse1 and Pulse2 and Pulse3) ;
if Pulse1 and Pulse2 and Pulse3 then
R1_2_Did_Resume <= transport True ;
else
test_report ( "ARCH00019" ,
"Wait in R1_2 resumed when condition was false" ,
false ) ;
end if ;
wait;
end process R1_2 ;
end ARCH00019 ;
entity ENT00019_Test_Bench is
end ENT00019_Test_Bench ;
architecture ARCH00019_Test_Bench of ENT00019_Test_Bench is
begin
L1:
block
component UUT
end component ;
for CIS1 : UUT use entity WORK.ENT00019 ( ARCH00019 ) ;
begin
CIS1 : UUT ;
end block L1 ;
end ARCH00019_Test_Bench ;
| gpl-3.0 | ba5b0f2399c7179dccdd4c2d3d41bd5d | 0.555458 | 3.537571 | false | true | false | false |
grwlf/vsim | vhdl_ct/ct00610.vhd | 1 | 1,915 | --
-- TEST NAME:
--
-- CT00610
--
-- AUTHOR:
--
-- G. Tominovich
--
-- TEST OBJECTIVES:
--
-- 9.3 (1)
-- 9.3 (2)
--
-- DESIGN UNIT ORDERING:
--
-- PKG00610
-- PKG00610/BODY
-- ENT00610_Test_Bench(ARCH00610_Test_Bench)
--
-- REVISION HISTORY:
--
-- 24-AUG-1987 - initial revision
--
-- NOTES:
--
-- self-Checking
--
--
use WORK.all ;
use STANDARD_TYPES.all ;
package PKG00610 is
signal Check1, Check2 : Integer := 0 ;
procedure PROC ( signal called : out integer;
constant P : in integer );
end PKG00610 ;
--
use WORK.all;
package body PKG00610 is
procedure PROC ( signal called : out integer;
constant P : in integer ) is
begin
called <= P + 1 after 0ns ;
end PROC ;
end PKG00610 ;
--
use WORK.all ;
use WORK.PKG00610.all ;
use WORK.STANDARD_TYPES.all ;
entity ENT00610_Test_Bench is
end ENT00610_Test_Bench ;
use WORK.all;
architecture ARCH00610_Test_Bench of ENT00610_Test_Bench is
begin
L1:
block
begin
ALab: PROC (Check1, Check1) ;
process ( Check1 )
variable First_Time : boolean := True ;
begin
if First_Time then
First_Time := false ;
else
test_report ( "ARCH00610" ,
"Concurrent procedure call with no in/inout signal "&
"parameters has an implicit wait statement with no "&
"sens list" ,
Check1 = 1 ) ;
end if ;
end process ;
PROC (Check2, Check2) ;
process ( Check2 )
variable First_Time : boolean := True ;
begin
if First_Time then
First_Time := false ;
else
test_report ( "ARCH00610" ,
"Concurrent procedure call with no label",
Check2 = 1 ) ;
end if ;
end process ;
end block L1 ;
end ARCH00610_Test_Bench ;
--
| gpl-3.0 | 1138e78bab860a8fe24121a16f78c564 | 0.547781 | 3.546296 | false | true | false | false |
grwlf/vsim | vhdl_ct/ct00568.vhd | 1 | 7,873 | -- NEED RESULT: ARCH00568: Attribute declarations - composite static subtypes with static initial values passed
-- NEED RESULT: ARCH00568: Attribute declarations - scalar static subtypes with generic initial values failed
-------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
-------------------------------------------------------------------------------
--
-- TEST NAME:
--
-- CT00568
--
-- AUTHOR:
--
-- A. Wilmot
--
-- TEST OBJECTIVES:
--
-- 4.4 (1)
-- 4.4 (4)
-- 4.4 (6)
--
-- DESIGN UNIT ORDERING:
--
-- ENT00568(ARCH00568)
-- ENT00568_Test_Bench(ARCH00568_Test_Bench)
--
-- REVISION HISTORY:
--
-- 19-AUG-1987 - initial revision
--
-- NOTES:
--
-- self-checking
-- automatically generated
--
use WORK.STANDARD_TYPES.all ;
--
entity ENT00568 is
generic (
i_bit_vector_1, i_bit_vector_2 : bit_vector
:= c_st_bit_vector_1 ;
i_string_1, i_string_2 : string
:= c_st_string_1 ;
i_t_rec1_1, i_t_rec1_2 : t_rec1
:= c_st_rec1_1 ;
i_st_rec1_1, i_st_rec1_2 : st_rec1
:= c_st_rec1_1 ;
i_t_rec2_1, i_t_rec2_2 : t_rec2
:= c_st_rec2_1 ;
i_st_rec2_1, i_st_rec2_2 : st_rec2
:= c_st_rec2_1 ;
i_t_rec3_1, i_t_rec3_2 : t_rec3
:= c_st_rec3_1 ;
i_st_rec3_1, i_st_rec3_2 : st_rec3
:= c_st_rec3_1 ;
i_t_arr1_1, i_t_arr1_2 : t_arr1
:= c_st_arr1_1 ;
i_st_arr1_1, i_st_arr1_2 : st_arr1
:= c_st_arr1_1 ;
i_t_arr2_1, i_t_arr2_2 : t_arr2
:= c_st_arr2_1 ;
i_st_arr2_1, i_st_arr2_2 : st_arr2
:= c_st_arr2_1 ;
i_t_arr3_1, i_t_arr3_2 : t_arr3
:= c_st_arr3_1 ;
i_st_arr3_1, i_st_arr3_2 : st_arr3
:= c_st_arr3_1
) ;
attribute at_bit_vector_1 : bit_vector ;
attribute at_string_1 : string ;
attribute at_t_rec1_1 : t_rec1 ;
attribute at_st_rec1_1 : st_rec1 ;
attribute at_t_rec2_1 : t_rec2 ;
attribute at_st_rec2_1 : st_rec2 ;
attribute at_t_rec3_1 : t_rec3 ;
attribute at_st_rec3_1 : st_rec3 ;
attribute at_t_arr1_1 : t_arr1 ;
attribute at_st_arr1_1 : st_arr1 ;
attribute at_t_arr2_1 : t_arr2 ;
attribute at_st_arr2_1 : st_arr2 ;
attribute at_t_arr3_1 : t_arr3 ;
attribute at_st_arr3_1 : st_arr3 ;
end ENT00568 ;
architecture ARCH00568 of ENT00568 is
begin
process
variable correct : boolean := true ;
procedure p1 ;
attribute at_bit_vector_1 of p1 : procedure is
c_st_bit_vector_1 ;
attribute at_string_1 of p1 : procedure is
c_st_string_1 ;
attribute at_t_rec1_1 of p1 : procedure is
c_st_rec1_1 ;
attribute at_st_rec1_1 of p1 : procedure is
c_st_rec1_1 ;
attribute at_t_rec2_1 of p1 : procedure is
c_st_rec2_1 ;
attribute at_st_rec2_1 of p1 : procedure is
c_st_rec2_1 ;
attribute at_t_rec3_1 of p1 : procedure is
c_st_rec3_1 ;
attribute at_st_rec3_1 of p1 : procedure is
c_st_rec3_1 ;
attribute at_t_arr1_1 of p1 : procedure is
c_st_arr1_1 ;
attribute at_st_arr1_1 of p1 : procedure is
c_st_arr1_1 ;
attribute at_t_arr2_1 of p1 : procedure is
c_st_arr2_1 ;
attribute at_st_arr2_1 of p1 : procedure is
c_st_arr2_1 ;
attribute at_t_arr3_1 of p1 : procedure is
c_st_arr3_1 ;
attribute at_st_arr3_1 of p1 : procedure is
c_st_arr3_1 ;
procedure p1 is
begin
correct := correct and p1'at_bit_vector_1
= c_st_bit_vector_1 ;
correct := correct and p1'at_string_1
= c_st_string_1 ;
correct := correct and p1'at_t_rec1_1
= c_st_rec1_1 ;
correct := correct and p1'at_st_rec1_1
= c_st_rec1_1 ;
correct := correct and p1'at_t_rec2_1
= c_st_rec2_1 ;
correct := correct and p1'at_st_rec2_1
= c_st_rec2_1 ;
correct := correct and p1'at_t_rec3_1
= c_st_rec3_1 ;
correct := correct and p1'at_st_rec3_1
= c_st_rec3_1 ;
correct := correct and p1'at_t_arr1_1
= c_st_arr1_1 ;
correct := correct and p1'at_st_arr1_1
= c_st_arr1_1 ;
correct := correct and p1'at_t_arr2_1
= c_st_arr2_1 ;
correct := correct and p1'at_st_arr2_1
= c_st_arr2_1 ;
correct := correct and p1'at_t_arr3_1
= c_st_arr3_1 ;
correct := correct and p1'at_st_arr3_1
= c_st_arr3_1 ;
test_report ( "ARCH00568" ,
"Attribute declarations - composite static subtypes"
& " with static initial values" ,
correct) ;
end p1 ;
begin
p1 ;
wait ;
end process ;
process
variable correct : boolean := true ;
procedure p1 ;
attribute at_bit_vector_1 of p1 : procedure is
i_bit_vector_1 ;
attribute at_string_1 of p1 : procedure is
i_string_1 ;
attribute at_t_rec1_1 of p1 : procedure is
i_t_rec1_1 ;
attribute at_st_rec1_1 of p1 : procedure is
i_st_rec1_1 ;
attribute at_t_rec2_1 of p1 : procedure is
i_t_rec2_1 ;
attribute at_st_rec2_1 of p1 : procedure is
i_st_rec2_1 ;
attribute at_t_rec3_1 of p1 : procedure is
i_t_rec3_1 ;
attribute at_st_rec3_1 of p1 : procedure is
i_st_rec3_1 ;
attribute at_t_arr1_1 of p1 : procedure is
i_t_arr1_1 ;
attribute at_st_arr1_1 of p1 : procedure is
i_st_arr1_1 ;
attribute at_t_arr2_1 of p1 : procedure is
i_t_arr2_1 ;
attribute at_st_arr2_1 of p1 : procedure is
i_st_arr2_1 ;
attribute at_t_arr3_1 of p1 : procedure is
i_t_arr3_1 ;
attribute at_st_arr3_1 of p1 : procedure is
i_st_arr3_1 ;
procedure p1 is
begin
correct := correct and p1'at_bit_vector_1
= c_st_bit_vector_1 ;
correct := correct and p1'at_string_1
= c_st_string_1 ;
correct := correct and p1'at_t_rec1_1
= c_st_rec1_1 ;
correct := correct and p1'at_st_rec1_1
= c_st_rec1_1 ;
correct := correct and p1'at_t_rec2_1
= c_st_rec2_1 ;
correct := correct and p1'at_st_rec2_1
= c_st_rec2_1 ;
correct := correct and p1'at_t_rec3_1
= c_st_rec3_1 ;
correct := correct and p1'at_st_rec3_1
= c_st_rec3_1 ;
correct := correct and p1'at_t_arr1_1
= c_st_arr1_1 ;
correct := correct and p1'at_st_arr1_1
= c_st_arr1_1 ;
correct := correct and p1'at_t_arr2_1
= c_st_arr2_1 ;
correct := correct and p1'at_st_arr2_1
= c_st_arr2_1 ;
correct := correct and p1'at_t_arr3_1
= c_st_arr3_1 ;
correct := correct and p1'at_st_arr3_1
= c_st_arr3_1 ;
test_report ( "ARCH00568" ,
"Attribute declarations - scalar static subtypes"
& " with generic initial values" ,
correct) ;
end p1 ;
begin
p1 ;
wait ;
end process ;
end ARCH00568 ;
--
entity ENT00568_Test_Bench is
end ENT00568_Test_Bench ;
--
architecture ARCH00568_Test_Bench of ENT00568_Test_Bench is
begin
L1:
block
component UUT
end component ;
for CIS1 : UUT use entity WORK.ENT00568 ( ARCH00568 ) ;
begin
CIS1 : UUT ;
end block L1 ;
end ARCH00568_Test_Bench ;
| gpl-3.0 | 15d2e5c6bb80c2b276a8c2b72058fb6a | 0.510733 | 2.934402 | false | false | false | false |
grwlf/vsim | vhdl_ct/ct00550.vhd | 1 | 3,171 | -- NEED RESULT: ARCH00550: Constant declarations - composite globally static subtypes passed
-------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
-------------------------------------------------------------------------------
--
-- TEST NAME:
--
-- CT00550
--
-- AUTHOR:
--
-- A. Wilmot
--
-- TEST OBJECTIVES:
--
-- 4.3.1.1 (6)
--
-- DESIGN UNIT ORDERING:
--
-- GENERIC_STANDARD_TYPES(ARCH00550)
-- ENT00550_Test_Bench(ARCH00550_Test_Bench)
--
-- REVISION HISTORY:
--
-- 19-AUG-1987 - initial revision
--
-- NOTES:
--
-- self-checking
--
use WORK.STANDARD_TYPES.all ;
architecture ARCH00550 of GENERIC_STANDARD_TYPES is
begin
process
variable correct : boolean := true ;
constant co_bit_vector_1 : bit_vector
:= c_st_bit_vector_1 ;
constant co_string_1 : string
:= c_st_string_1 ;
constant co_t_rec1_1 : t_rec1
:= c_st_rec1_1 ;
constant co_st_rec1_1 : st_rec1
:= c_st_rec1_1 ;
constant co_t_rec2_1 : t_rec2
:= c_st_rec2_1 ;
constant co_st_rec2_1 : st_rec2
:= c_st_rec2_1 ;
constant co_t_rec3_1 : t_rec3
:= c_st_rec3_1 ;
constant co_st_rec3_1 : st_rec3
:= c_st_rec3_1 ;
constant co_t_arr1_1 : t_arr1
:= c_st_arr1_1 ;
constant co_st_arr1_1 : st_arr1
:= c_st_arr1_1 ;
constant co_t_arr2_1 : t_arr2
:= c_st_arr2_1 ;
constant co_st_arr2_1 : st_arr2
:= c_st_arr2_1 ;
constant co_t_arr3_1 : t_arr3
:= c_st_arr3_1 ;
constant co_st_arr3_1 : st_arr3
:= c_st_arr3_1 ;
begin
correct := correct and co_bit_vector_1 = c_st_bit_vector_1 ;
correct := correct and co_string_1 = c_st_string_1 ;
correct := correct and co_t_rec1_1 = c_t_rec1_1 ;
correct := correct and co_st_rec1_1 = c_st_rec1_1 ;
correct := correct and co_t_rec2_1 = c_t_rec2_1 ;
correct := correct and co_st_rec2_1 = c_st_rec2_1 ;
correct := correct and co_t_rec3_1 = c_t_rec3_1 ;
correct := correct and co_st_rec3_1 = c_st_rec3_1 ;
correct := correct and co_t_arr1_1 = c_t_arr1_1 ;
correct := correct and co_st_arr1_1 = c_st_arr1_1 ;
correct := correct and co_t_arr2_1 = c_t_arr2_1 ;
correct := correct and co_st_arr2_1 = c_st_arr2_1 ;
correct := correct and co_t_arr3_1 = c_t_arr3_1 ;
correct := correct and co_st_arr3_1 = c_st_arr3_1 ;
test_report ( "ARCH00550" ,
"Constant declarations - composite globally static subtypes" ,
correct) ;
wait ;
end process ;
end ARCH00550 ;
--
entity ENT00550_Test_Bench is
end ENT00550_Test_Bench ;
--
architecture ARCH00550_Test_Bench of ENT00550_Test_Bench is
begin
L1:
block
component UUT
end component ;
for CIS1 : UUT use entity WORK.GENERIC_STANDARD_TYPES ( ARCH00550 ) ;
begin
CIS1 : UUT ;
end block L1 ;
end ARCH00550_Test_Bench ;
| gpl-3.0 | a59c0c6e8f0eed945204238712ee614b | 0.523179 | 2.98869 | false | true | false | false |
jairov4/accel-oil | solution_spartan6/syn/vhdl/nfa_accept_samples_generic_hw_add_16ns_16ns_16_4.vhd | 3 | 9,512 | -- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2013.4
-- Copyright (C) 2013 Xilinx Inc. All rights reserved.
--
-- ==============================================================
library IEEE;
use IEEE.std_logic_1164.all;
use ieee.std_logic_arith.all;
entity nfa_accept_samples_generic_hw_add_16ns_16ns_16_4_AddSubnS_2 is
port (
clk: in std_logic;
reset: in std_logic;
ce: in std_logic;
a: in std_logic_vector(15 downto 0);
b: in std_logic_vector(15 downto 0);
s: out std_logic_vector(15 downto 0));
end entity;
architecture behav of nfa_accept_samples_generic_hw_add_16ns_16ns_16_4_AddSubnS_2 is
component nfa_accept_samples_generic_hw_add_16ns_16ns_16_4_AddSubnS_2_fadder is
port (
faa : IN STD_LOGIC_VECTOR (4-1 downto 0);
fab : IN STD_LOGIC_VECTOR (4-1 downto 0);
facin : IN STD_LOGIC_VECTOR (0 downto 0);
fas : OUT STD_LOGIC_VECTOR (4-1 downto 0);
facout : OUT STD_LOGIC_VECTOR (0 downto 0));
end component;
component nfa_accept_samples_generic_hw_add_16ns_16ns_16_4_AddSubnS_2_fadder_f is
port (
faa : IN STD_LOGIC_VECTOR (4-1 downto 0);
fab : IN STD_LOGIC_VECTOR (4-1 downto 0);
facin : IN STD_LOGIC_VECTOR (0 downto 0);
fas : OUT STD_LOGIC_VECTOR (4-1 downto 0);
facout : OUT STD_LOGIC_VECTOR (0 downto 0));
end component;
-- ---- register and wire type variables list here ----
-- wire for the primary inputs
signal a_reg : std_logic_vector(15 downto 0);
signal b_reg : std_logic_vector(15 downto 0);
-- wires for each small adder
signal a0_cb : std_logic_vector(3 downto 0);
signal b0_cb : std_logic_vector(3 downto 0);
signal a1_cb : std_logic_vector(7 downto 4);
signal b1_cb : std_logic_vector(7 downto 4);
signal a2_cb : std_logic_vector(11 downto 8);
signal b2_cb : std_logic_vector(11 downto 8);
signal a3_cb : std_logic_vector(15 downto 12);
signal b3_cb : std_logic_vector(15 downto 12);
-- registers for input register array
type ramtypei0 is array (0 downto 0) of std_logic_vector(3 downto 0);
signal a1_cb_regi1 : ramtypei0;
signal b1_cb_regi1 : ramtypei0;
type ramtypei1 is array (1 downto 0) of std_logic_vector(3 downto 0);
signal a2_cb_regi2 : ramtypei1;
signal b2_cb_regi2 : ramtypei1;
type ramtypei2 is array (2 downto 0) of std_logic_vector(3 downto 0);
signal a3_cb_regi3 : ramtypei2;
signal b3_cb_regi3 : ramtypei2;
-- wires for each full adder sum
signal fas : std_logic_vector(15 downto 0);
-- wires and register for carry out bit
signal faccout_ini : std_logic_vector (0 downto 0);
signal faccout0_co0 : std_logic_vector (0 downto 0);
signal faccout1_co1 : std_logic_vector (0 downto 0);
signal faccout2_co2 : std_logic_vector (0 downto 0);
signal faccout3_co3 : std_logic_vector (0 downto 0);
signal faccout0_co0_reg : std_logic_vector (0 downto 0);
signal faccout1_co1_reg : std_logic_vector (0 downto 0);
signal faccout2_co2_reg : std_logic_vector (0 downto 0);
-- registers for output register array
type ramtypeo2 is array (2 downto 0) of std_logic_vector(3 downto 0);
signal s0_ca_rego0 : ramtypeo2;
type ramtypeo1 is array (1 downto 0) of std_logic_vector(3 downto 0);
signal s1_ca_rego1 : ramtypeo1;
type ramtypeo0 is array (0 downto 0) of std_logic_vector(3 downto 0);
signal s2_ca_rego2 : ramtypeo0;
-- wire for the temporary output
signal s_tmp : std_logic_vector(15 downto 0);
-- ---- RTL code for assignment statements/always blocks/module instantiations here ----
begin
a_reg <= a;
b_reg <= b;
-- small adder input assigments
a0_cb <= a_reg(3 downto 0);
b0_cb <= b_reg(3 downto 0);
a1_cb <= a_reg(7 downto 4);
b1_cb <= b_reg(7 downto 4);
a2_cb <= a_reg(11 downto 8);
b2_cb <= b_reg(11 downto 8);
a3_cb <= a_reg(15 downto 12);
b3_cb <= b_reg(15 downto 12);
-- input register array
process (clk)
begin
if (clk'event and clk='1') then
if (ce='1') then
a1_cb_regi1 (0) <= a1_cb;
b1_cb_regi1 (0) <= b1_cb;
a2_cb_regi2 (0) <= a2_cb;
b2_cb_regi2 (0) <= b2_cb;
a3_cb_regi3 (0) <= a3_cb;
b3_cb_regi3 (0) <= b3_cb;
a2_cb_regi2 (1) <= a2_cb_regi2 (0);
b2_cb_regi2 (1) <= b2_cb_regi2 (0);
a3_cb_regi3 (1) <= a3_cb_regi3 (0);
b3_cb_regi3 (1) <= b3_cb_regi3 (0);
a3_cb_regi3 (2) <= a3_cb_regi3 (1);
b3_cb_regi3 (2) <= b3_cb_regi3 (1);
end if;
end if;
end process;
-- carry out bit processing
process (clk)
begin
if (clk'event and clk='1') then
if (ce='1') then
faccout0_co0_reg <= faccout0_co0;
faccout1_co1_reg <= faccout1_co1;
faccout2_co2_reg <= faccout2_co2;
end if;
end if;
end process;
-- small adder generation
u0 : nfa_accept_samples_generic_hw_add_16ns_16ns_16_4_AddSubnS_2_fadder
port map
(faa => a0_cb,
fab => b0_cb,
facin => faccout_ini,
fas => fas(3 downto 0),
facout => faccout0_co0);
u1 : nfa_accept_samples_generic_hw_add_16ns_16ns_16_4_AddSubnS_2_fadder
port map
(faa => a1_cb_regi1(0),
fab => b1_cb_regi1(0),
facin => faccout0_co0_reg,
fas => fas(7 downto 4),
facout => faccout1_co1);
u2 : nfa_accept_samples_generic_hw_add_16ns_16ns_16_4_AddSubnS_2_fadder
port map
(faa => a2_cb_regi2(1),
fab => b2_cb_regi2(1),
facin => faccout1_co1_reg,
fas => fas(11 downto 8),
facout => faccout2_co2);
u3 : nfa_accept_samples_generic_hw_add_16ns_16ns_16_4_AddSubnS_2_fadder_f
port map
(faa => a3_cb_regi3(2),
fab => b3_cb_regi3(2),
facin => faccout2_co2_reg,
fas => fas(15 downto 12),
facout => faccout3_co3);
faccout_ini <= "0";
-- output register array
process (clk)
begin
if (clk'event and clk='1') then
if (ce='1') then
s0_ca_rego0 (0) <= fas(3 downto 0);
s1_ca_rego1 (0) <= fas(7 downto 4);
s2_ca_rego2 (0) <= fas(11 downto 8);
s0_ca_rego0 (1) <= s0_ca_rego0 (0);
s0_ca_rego0 (2) <= s0_ca_rego0 (1);
s1_ca_rego1 (1) <= s1_ca_rego1 (0);
end if;
end if;
end process;
-- get the s_tmp, assign it to the primary output
s_tmp(3 downto 0) <= s0_ca_rego0(2);
s_tmp(7 downto 4) <= s1_ca_rego1(1);
s_tmp(11 downto 8) <= s2_ca_rego2(0);
s_tmp(15 downto 12) <= fas(15 downto 12);
s <= s_tmp;
end architecture;
-- short adder
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity nfa_accept_samples_generic_hw_add_16ns_16ns_16_4_AddSubnS_2_fadder is
generic(N : natural :=4);
port (
faa : IN STD_LOGIC_VECTOR (N-1 downto 0);
fab : IN STD_LOGIC_VECTOR (N-1 downto 0);
facin : IN STD_LOGIC_VECTOR (0 downto 0);
fas : OUT STD_LOGIC_VECTOR (N-1 downto 0);
facout : OUT STD_LOGIC_VECTOR (0 downto 0));
end;
architecture behav of nfa_accept_samples_generic_hw_add_16ns_16ns_16_4_AddSubnS_2_fadder is
signal tmp : STD_LOGIC_VECTOR (N downto 0);
begin
tmp <= std_logic_vector(unsigned(std_logic_vector(unsigned(std_logic_vector(resize(unsigned(faa),N+1))) + unsigned(fab))) + unsigned(facin));
fas <= tmp(N-1 downto 0 );
facout <= tmp(N downto N);
end behav;
-- the final stage short adder
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity nfa_accept_samples_generic_hw_add_16ns_16ns_16_4_AddSubnS_2_fadder_f is
generic(N : natural :=4);
port (
faa : IN STD_LOGIC_VECTOR (N-1 downto 0);
fab : IN STD_LOGIC_VECTOR (N-1 downto 0);
facin : IN STD_LOGIC_VECTOR (0 downto 0);
fas : OUT STD_LOGIC_VECTOR (N-1 downto 0);
facout : OUT STD_LOGIC_VECTOR (0 downto 0));
end;
architecture behav of nfa_accept_samples_generic_hw_add_16ns_16ns_16_4_AddSubnS_2_fadder_f is
signal tmp : STD_LOGIC_VECTOR (N downto 0);
begin
tmp <= std_logic_vector(unsigned(std_logic_vector(unsigned(std_logic_vector(resize(unsigned(faa),N+1))) + unsigned(fab))) + unsigned(facin));
fas <= tmp(N-1 downto 0 );
facout <= tmp(N downto N);
end behav;
Library IEEE;
use IEEE.std_logic_1164.all;
entity nfa_accept_samples_generic_hw_add_16ns_16ns_16_4 is
generic (
ID : INTEGER;
NUM_STAGE : INTEGER;
din0_WIDTH : INTEGER;
din1_WIDTH : INTEGER;
dout_WIDTH : INTEGER);
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
ce : IN STD_LOGIC;
din0 : IN STD_LOGIC_VECTOR(din0_WIDTH - 1 DOWNTO 0);
din1 : IN STD_LOGIC_VECTOR(din1_WIDTH - 1 DOWNTO 0);
dout : OUT STD_LOGIC_VECTOR(dout_WIDTH - 1 DOWNTO 0));
end entity;
architecture arch of nfa_accept_samples_generic_hw_add_16ns_16ns_16_4 is
component nfa_accept_samples_generic_hw_add_16ns_16ns_16_4_AddSubnS_2 is
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
ce : IN STD_LOGIC;
a : IN STD_LOGIC_VECTOR;
b : IN STD_LOGIC_VECTOR;
s : OUT STD_LOGIC_VECTOR);
end component;
begin
nfa_accept_samples_generic_hw_add_16ns_16ns_16_4_AddSubnS_2_U : component nfa_accept_samples_generic_hw_add_16ns_16ns_16_4_AddSubnS_2
port map (
clk => clk,
reset => reset,
ce => ce,
a => din0,
b => din1,
s => dout);
end architecture;
| lgpl-3.0 | 80d1b3d3c8664df0cadb21d3ee21eb9c | 0.608705 | 2.867651 | false | false | false | false |
grwlf/vsim | vhdl_ct/ct00120.vhd | 1 | 30,831 | -- NEED RESULT: ARCH00120.P1: Multi transport transactions occurred on signal asg with slice name prefixed by a selected name on LHS passed
-- NEED RESULT: ARCH00120.P2: Multi transport transactions occurred on signal asg with slice name prefixed by a selected name on LHS passed
-- NEED RESULT: ARCH00120.P3: Multi transport transactions occurred on signal asg with slice name prefixed by a selected name on LHS passed
-- NEED RESULT: ARCH00120.P4: Multi transport transactions occurred on signal asg with slice name prefixed by a selected name on LHS passed
-- NEED RESULT: ARCH00120.P5: Multi transport transactions occurred on signal asg with slice name prefixed by a selected name on LHS passed
-- NEED RESULT: ARCH00120.P6: Multi transport transactions occurred on signal asg with slice name prefixed by a selected name on LHS passed
-- NEED RESULT: ARCH00120: One transport transaction occurred on signal asg with slice name prefixed by a selected name on LHS passed
-- NEED RESULT: ARCH00120: Old transactions were removed on signal asg with slice name prefixed by a selected name on LHS passed
-- NEED RESULT: ARCH00120: One transport transaction occurred on signal asg with slice name prefixed by a selected name on LHS passed
-- NEED RESULT: ARCH00120: Old transactions were removed on signal asg with slice name prefixed by a selected name on LHS passed
-- NEED RESULT: ARCH00120: One transport transaction occurred on signal asg with slice name prefixed by a selected name on LHS passed
-- NEED RESULT: ARCH00120: Old transactions were removed on signal asg with slice name prefixed by a selected name on LHS passed
-- NEED RESULT: ARCH00120: One transport transaction occurred on signal asg with slice name prefixed by a selected name on LHS passed
-- NEED RESULT: ARCH00120: Old transactions were removed on signal asg with slice name prefixed by a selected name on LHS passed
-- NEED RESULT: ARCH00120: One transport transaction occurred on signal asg with slice name prefixed by a selected name on LHS passed
-- NEED RESULT: ARCH00120: Old transactions were removed on signal asg with slice name prefixed by a selected name on LHS passed
-- NEED RESULT: ARCH00120: One transport transaction occurred on signal asg with slice name prefixed by a selected name on LHS passed
-- NEED RESULT: ARCH00120: Old transactions were removed on signal asg with slice name prefixed by a selected name on LHS passed
-- NEED RESULT: P6: Transport transactions entirely completed passed
-- NEED RESULT: P5: Transport transactions entirely completed passed
-- NEED RESULT: P4: Transport transactions entirely completed passed
-- NEED RESULT: P3: Transport transactions entirely completed passed
-- NEED RESULT: P2: Transport transactions entirely completed passed
-- NEED RESULT: P1: Transport transactions entirely completed passed
-------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
-------------------------------------------------------------------------------
--
-- TEST NAME:
--
-- CT00120
--
-- AUTHOR:
--
-- G. Tominovich
--
-- TEST OBJECTIVES:
--
-- 8.3 (2)
-- 8.3 (3)
-- 8.3 (5)
-- 8.3.1 (3)
--
-- DESIGN UNIT ORDERING:
--
-- PKG00120
-- PKG00120/BODY
-- E00000(ARCH00120)
-- ENT00120_Test_Bench(ARCH00120_Test_Bench)
--
-- REVISION HISTORY:
--
-- 07-JUL-1987 - initial revision
--
-- NOTES:
--
-- self-checking
-- automatically generated
--
use WORK.STANDARD_TYPES.all ;
package PKG00120 is
type r_st_arr1_vector is record
f1 : integer ;
f2 : st_arr1_vector ;
end record ;
function c_r_st_arr1_vector_1 return r_st_arr1_vector ;
-- (c_integer_1, c_st_arr1_vector_1) ;
function c_r_st_arr1_vector_2 return r_st_arr1_vector ;
-- (c_integer_2, c_st_arr1_vector_2) ;
--
type r_st_arr2_vector is record
f1 : integer ;
f2 : st_arr2_vector ;
end record ;
function c_r_st_arr2_vector_1 return r_st_arr2_vector ;
-- (c_integer_1, c_st_arr2_vector_1) ;
function c_r_st_arr2_vector_2 return r_st_arr2_vector ;
-- (c_integer_2, c_st_arr2_vector_2) ;
--
type r_st_arr3_vector is record
f1 : integer ;
f2 : st_arr3_vector ;
end record ;
function c_r_st_arr3_vector_1 return r_st_arr3_vector ;
-- (c_integer_1, c_st_arr3_vector_1) ;
function c_r_st_arr3_vector_2 return r_st_arr3_vector ;
-- (c_integer_2, c_st_arr3_vector_2) ;
--
type r_st_rec1_vector is record
f1 : integer ;
f2 : st_rec1_vector ;
end record ;
function c_r_st_rec1_vector_1 return r_st_rec1_vector ;
-- (c_integer_1, c_st_rec1_vector_1) ;
function c_r_st_rec1_vector_2 return r_st_rec1_vector ;
-- (c_integer_2, c_st_rec1_vector_2) ;
--
type r_st_rec2_vector is record
f1 : integer ;
f2 : st_rec2_vector ;
end record ;
function c_r_st_rec2_vector_1 return r_st_rec2_vector ;
-- (c_integer_1, c_st_rec2_vector_1) ;
function c_r_st_rec2_vector_2 return r_st_rec2_vector ;
-- (c_integer_2, c_st_rec2_vector_2) ;
--
type r_st_rec3_vector is record
f1 : integer ;
f2 : st_rec3_vector ;
end record ;
function c_r_st_rec3_vector_1 return r_st_rec3_vector ;
-- (c_integer_1, c_st_rec3_vector_1) ;
function c_r_st_rec3_vector_2 return r_st_rec3_vector ;
-- (c_integer_2, c_st_rec3_vector_2) ;
--
--
end PKG00120 ;
--
package body PKG00120 is
function c_r_st_arr1_vector_1 return r_st_arr1_vector
is begin
return (c_integer_1, c_st_arr1_vector_1) ;
end c_r_st_arr1_vector_1 ;
--
function c_r_st_arr1_vector_2 return r_st_arr1_vector
is begin
return (c_integer_2, c_st_arr1_vector_2) ;
end c_r_st_arr1_vector_2 ;
--
--
function c_r_st_arr2_vector_1 return r_st_arr2_vector
is begin
return (c_integer_1, c_st_arr2_vector_1) ;
end c_r_st_arr2_vector_1 ;
--
function c_r_st_arr2_vector_2 return r_st_arr2_vector
is begin
return (c_integer_2, c_st_arr2_vector_2) ;
end c_r_st_arr2_vector_2 ;
--
--
function c_r_st_arr3_vector_1 return r_st_arr3_vector
is begin
return (c_integer_1, c_st_arr3_vector_1) ;
end c_r_st_arr3_vector_1 ;
--
function c_r_st_arr3_vector_2 return r_st_arr3_vector
is begin
return (c_integer_2, c_st_arr3_vector_2) ;
end c_r_st_arr3_vector_2 ;
--
--
function c_r_st_rec1_vector_1 return r_st_rec1_vector
is begin
return (c_integer_1, c_st_rec1_vector_1) ;
end c_r_st_rec1_vector_1 ;
--
function c_r_st_rec1_vector_2 return r_st_rec1_vector
is begin
return (c_integer_2, c_st_rec1_vector_2) ;
end c_r_st_rec1_vector_2 ;
--
--
function c_r_st_rec2_vector_1 return r_st_rec2_vector
is begin
return (c_integer_1, c_st_rec2_vector_1) ;
end c_r_st_rec2_vector_1 ;
--
function c_r_st_rec2_vector_2 return r_st_rec2_vector
is begin
return (c_integer_2, c_st_rec2_vector_2) ;
end c_r_st_rec2_vector_2 ;
--
--
function c_r_st_rec3_vector_1 return r_st_rec3_vector
is begin
return (c_integer_1, c_st_rec3_vector_1) ;
end c_r_st_rec3_vector_1 ;
--
function c_r_st_rec3_vector_2 return r_st_rec3_vector
is begin
return (c_integer_2, c_st_rec3_vector_2) ;
end c_r_st_rec3_vector_2 ;
--
--
--
end PKG00120 ;
--
use WORK.STANDARD_TYPES.all ;
use WORK.PKG00120.all ;
architecture ARCH00120 of E00000 is
subtype chk_sig_type is integer range -1 to 100 ;
signal chk_r_st_arr1_vector : chk_sig_type := -1 ;
signal chk_r_st_arr2_vector : chk_sig_type := -1 ;
signal chk_r_st_arr3_vector : chk_sig_type := -1 ;
signal chk_r_st_rec1_vector : chk_sig_type := -1 ;
signal chk_r_st_rec2_vector : chk_sig_type := -1 ;
signal chk_r_st_rec3_vector : chk_sig_type := -1 ;
--
signal s_r_st_arr1_vector : r_st_arr1_vector
:= c_r_st_arr1_vector_1 ;
signal s_r_st_arr2_vector : r_st_arr2_vector
:= c_r_st_arr2_vector_1 ;
signal s_r_st_arr3_vector : r_st_arr3_vector
:= c_r_st_arr3_vector_1 ;
signal s_r_st_rec1_vector : r_st_rec1_vector
:= c_r_st_rec1_vector_1 ;
signal s_r_st_rec2_vector : r_st_rec2_vector
:= c_r_st_rec2_vector_1 ;
signal s_r_st_rec3_vector : r_st_rec3_vector
:= c_r_st_rec3_vector_1 ;
--
begin
PGEN_CHKP_1 :
process ( chk_r_st_arr1_vector )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P1" ,
"Transport transactions entirely completed",
chk_r_st_arr1_vector = 4 ) ;
end if ;
end process PGEN_CHKP_1 ;
--
P1 :
process ( s_r_st_arr1_vector )
variable correct : boolean ;
variable counter : integer := 0 ;
variable savtime : time ;
--
procedure Proc1 is
begin
case counter is
when 0
=> s_r_st_arr1_vector.f2 (lowb+1 to highb-1) <= transport
c_r_st_arr1_vector_2.f2
(lowb+1 to highb-1) after 10 ns,
c_r_st_arr1_vector_1.f2
(lowb+1 to highb-1) after 20 ns ;
--
when 1
=> correct :=
s_r_st_arr1_vector.f2 (lowb+1 to highb-1) =
c_r_st_arr1_vector_2.f2 (lowb+1 to highb-1) and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_r_st_arr1_vector.f2 (lowb+1 to highb-1) =
c_r_st_arr1_vector_1.f2 (lowb+1 to highb-1) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00120.P1" ,
"Multi transport transactions occurred on signal " &
"asg with slice name prefixed by a selected name on LHS",
correct ) ;
s_r_st_arr1_vector.f2 (lowb+1 to highb-1) <= transport
c_r_st_arr1_vector_2.f2
(lowb+1 to highb-1) after 10 ns ,
c_r_st_arr1_vector_1.f2
(lowb+1 to highb-1) after 20 ns ,
c_r_st_arr1_vector_2.f2
(lowb+1 to highb-1) after 30 ns ,
c_r_st_arr1_vector_1.f2
(lowb+1 to highb-1) after 40 ns ;
--
when 3
=> correct :=
s_r_st_arr1_vector.f2 (lowb+1 to highb-1) =
c_r_st_arr1_vector_2.f2 (lowb+1 to highb-1) and
(savtime + 10 ns) = Std.Standard.Now ;
s_r_st_arr1_vector.f2 (lowb+1 to highb-1) <= transport
c_r_st_arr1_vector_1.f2
(lowb+1 to highb-1) after 5 ns ;
--
when 4
=> correct :=
correct and
s_r_st_arr1_vector.f2 (lowb+1 to highb-1) =
c_r_st_arr1_vector_1.f2 (lowb+1 to highb-1) and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00120" ,
"One transport transaction occurred on signal " &
"asg with slice name prefixed by a selected name on LHS",
correct ) ;
test_report ( "ARCH00120" ,
"Old transactions were removed on signal " &
"asg with slice name prefixed by a selected name on LHS",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00120" ,
"Old transactions were removed on signal " &
"asg with slice name prefixed by a selected name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_r_st_arr1_vector <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
end Proc1 ;
--
begin
Proc1 ;
end process P1 ;
--
PGEN_CHKP_2 :
process ( chk_r_st_arr2_vector )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P2" ,
"Transport transactions entirely completed",
chk_r_st_arr2_vector = 4 ) ;
end if ;
end process PGEN_CHKP_2 ;
--
P2 :
process ( s_r_st_arr2_vector )
variable correct : boolean ;
variable counter : integer := 0 ;
variable savtime : time ;
--
procedure Proc1 is
begin
case counter is
when 0
=> s_r_st_arr2_vector.f2 (lowb+1 to highb-1) <= transport
c_r_st_arr2_vector_2.f2
(lowb+1 to highb-1) after 10 ns,
c_r_st_arr2_vector_1.f2
(lowb+1 to highb-1) after 20 ns ;
--
when 1
=> correct :=
s_r_st_arr2_vector.f2 (lowb+1 to highb-1) =
c_r_st_arr2_vector_2.f2 (lowb+1 to highb-1) and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_r_st_arr2_vector.f2 (lowb+1 to highb-1) =
c_r_st_arr2_vector_1.f2 (lowb+1 to highb-1) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00120.P2" ,
"Multi transport transactions occurred on signal " &
"asg with slice name prefixed by a selected name on LHS",
correct ) ;
s_r_st_arr2_vector.f2 (lowb+1 to highb-1) <= transport
c_r_st_arr2_vector_2.f2
(lowb+1 to highb-1) after 10 ns ,
c_r_st_arr2_vector_1.f2
(lowb+1 to highb-1) after 20 ns ,
c_r_st_arr2_vector_2.f2
(lowb+1 to highb-1) after 30 ns ,
c_r_st_arr2_vector_1.f2
(lowb+1 to highb-1) after 40 ns ;
--
when 3
=> correct :=
s_r_st_arr2_vector.f2 (lowb+1 to highb-1) =
c_r_st_arr2_vector_2.f2 (lowb+1 to highb-1) and
(savtime + 10 ns) = Std.Standard.Now ;
s_r_st_arr2_vector.f2 (lowb+1 to highb-1) <= transport
c_r_st_arr2_vector_1.f2
(lowb+1 to highb-1) after 5 ns ;
--
when 4
=> correct :=
correct and
s_r_st_arr2_vector.f2 (lowb+1 to highb-1) =
c_r_st_arr2_vector_1.f2 (lowb+1 to highb-1) and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00120" ,
"One transport transaction occurred on signal " &
"asg with slice name prefixed by a selected name on LHS",
correct ) ;
test_report ( "ARCH00120" ,
"Old transactions were removed on signal " &
"asg with slice name prefixed by a selected name on LHS",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00120" ,
"Old transactions were removed on signal " &
"asg with slice name prefixed by a selected name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_r_st_arr2_vector <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
end Proc1 ;
--
begin
Proc1 ;
end process P2 ;
--
PGEN_CHKP_3 :
process ( chk_r_st_arr3_vector )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P3" ,
"Transport transactions entirely completed",
chk_r_st_arr3_vector = 4 ) ;
end if ;
end process PGEN_CHKP_3 ;
--
P3 :
process ( s_r_st_arr3_vector )
variable correct : boolean ;
variable counter : integer := 0 ;
variable savtime : time ;
--
procedure Proc1 is
begin
case counter is
when 0
=> s_r_st_arr3_vector.f2 (lowb+1 to highb-1) <= transport
c_r_st_arr3_vector_2.f2
(lowb+1 to highb-1) after 10 ns,
c_r_st_arr3_vector_1.f2
(lowb+1 to highb-1) after 20 ns ;
--
when 1
=> correct :=
s_r_st_arr3_vector.f2 (lowb+1 to highb-1) =
c_r_st_arr3_vector_2.f2 (lowb+1 to highb-1) and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_r_st_arr3_vector.f2 (lowb+1 to highb-1) =
c_r_st_arr3_vector_1.f2 (lowb+1 to highb-1) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00120.P3" ,
"Multi transport transactions occurred on signal " &
"asg with slice name prefixed by a selected name on LHS",
correct ) ;
s_r_st_arr3_vector.f2 (lowb+1 to highb-1) <= transport
c_r_st_arr3_vector_2.f2
(lowb+1 to highb-1) after 10 ns ,
c_r_st_arr3_vector_1.f2
(lowb+1 to highb-1) after 20 ns ,
c_r_st_arr3_vector_2.f2
(lowb+1 to highb-1) after 30 ns ,
c_r_st_arr3_vector_1.f2
(lowb+1 to highb-1) after 40 ns ;
--
when 3
=> correct :=
s_r_st_arr3_vector.f2 (lowb+1 to highb-1) =
c_r_st_arr3_vector_2.f2 (lowb+1 to highb-1) and
(savtime + 10 ns) = Std.Standard.Now ;
s_r_st_arr3_vector.f2 (lowb+1 to highb-1) <= transport
c_r_st_arr3_vector_1.f2
(lowb+1 to highb-1) after 5 ns ;
--
when 4
=> correct :=
correct and
s_r_st_arr3_vector.f2 (lowb+1 to highb-1) =
c_r_st_arr3_vector_1.f2 (lowb+1 to highb-1) and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00120" ,
"One transport transaction occurred on signal " &
"asg with slice name prefixed by a selected name on LHS",
correct ) ;
test_report ( "ARCH00120" ,
"Old transactions were removed on signal " &
"asg with slice name prefixed by a selected name on LHS",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00120" ,
"Old transactions were removed on signal " &
"asg with slice name prefixed by a selected name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_r_st_arr3_vector <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
end Proc1 ;
--
begin
Proc1 ;
end process P3 ;
--
PGEN_CHKP_4 :
process ( chk_r_st_rec1_vector )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P4" ,
"Transport transactions entirely completed",
chk_r_st_rec1_vector = 4 ) ;
end if ;
end process PGEN_CHKP_4 ;
--
P4 :
process ( s_r_st_rec1_vector )
variable correct : boolean ;
variable counter : integer := 0 ;
variable savtime : time ;
--
procedure Proc1 is
begin
case counter is
when 0
=> s_r_st_rec1_vector.f2 (lowb+1 to highb-1) <= transport
c_r_st_rec1_vector_2.f2
(lowb+1 to highb-1) after 10 ns,
c_r_st_rec1_vector_1.f2
(lowb+1 to highb-1) after 20 ns ;
--
when 1
=> correct :=
s_r_st_rec1_vector.f2 (lowb+1 to highb-1) =
c_r_st_rec1_vector_2.f2 (lowb+1 to highb-1) and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_r_st_rec1_vector.f2 (lowb+1 to highb-1) =
c_r_st_rec1_vector_1.f2 (lowb+1 to highb-1) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00120.P4" ,
"Multi transport transactions occurred on signal " &
"asg with slice name prefixed by a selected name on LHS",
correct ) ;
s_r_st_rec1_vector.f2 (lowb+1 to highb-1) <= transport
c_r_st_rec1_vector_2.f2
(lowb+1 to highb-1) after 10 ns ,
c_r_st_rec1_vector_1.f2
(lowb+1 to highb-1) after 20 ns ,
c_r_st_rec1_vector_2.f2
(lowb+1 to highb-1) after 30 ns ,
c_r_st_rec1_vector_1.f2
(lowb+1 to highb-1) after 40 ns ;
--
when 3
=> correct :=
s_r_st_rec1_vector.f2 (lowb+1 to highb-1) =
c_r_st_rec1_vector_2.f2 (lowb+1 to highb-1) and
(savtime + 10 ns) = Std.Standard.Now ;
s_r_st_rec1_vector.f2 (lowb+1 to highb-1) <= transport
c_r_st_rec1_vector_1.f2
(lowb+1 to highb-1) after 5 ns ;
--
when 4
=> correct :=
correct and
s_r_st_rec1_vector.f2 (lowb+1 to highb-1) =
c_r_st_rec1_vector_1.f2 (lowb+1 to highb-1) and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00120" ,
"One transport transaction occurred on signal " &
"asg with slice name prefixed by a selected name on LHS",
correct ) ;
test_report ( "ARCH00120" ,
"Old transactions were removed on signal " &
"asg with slice name prefixed by a selected name on LHS",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00120" ,
"Old transactions were removed on signal " &
"asg with slice name prefixed by a selected name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_r_st_rec1_vector <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
end Proc1 ;
--
begin
Proc1 ;
end process P4 ;
--
PGEN_CHKP_5 :
process ( chk_r_st_rec2_vector )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P5" ,
"Transport transactions entirely completed",
chk_r_st_rec2_vector = 4 ) ;
end if ;
end process PGEN_CHKP_5 ;
--
P5 :
process ( s_r_st_rec2_vector )
variable correct : boolean ;
variable counter : integer := 0 ;
variable savtime : time ;
--
procedure Proc1 is
begin
case counter is
when 0
=> s_r_st_rec2_vector.f2 (lowb+1 to highb-1) <= transport
c_r_st_rec2_vector_2.f2
(lowb+1 to highb-1) after 10 ns,
c_r_st_rec2_vector_1.f2
(lowb+1 to highb-1) after 20 ns ;
--
when 1
=> correct :=
s_r_st_rec2_vector.f2 (lowb+1 to highb-1) =
c_r_st_rec2_vector_2.f2 (lowb+1 to highb-1) and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_r_st_rec2_vector.f2 (lowb+1 to highb-1) =
c_r_st_rec2_vector_1.f2 (lowb+1 to highb-1) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00120.P5" ,
"Multi transport transactions occurred on signal " &
"asg with slice name prefixed by a selected name on LHS",
correct ) ;
s_r_st_rec2_vector.f2 (lowb+1 to highb-1) <= transport
c_r_st_rec2_vector_2.f2
(lowb+1 to highb-1) after 10 ns ,
c_r_st_rec2_vector_1.f2
(lowb+1 to highb-1) after 20 ns ,
c_r_st_rec2_vector_2.f2
(lowb+1 to highb-1) after 30 ns ,
c_r_st_rec2_vector_1.f2
(lowb+1 to highb-1) after 40 ns ;
--
when 3
=> correct :=
s_r_st_rec2_vector.f2 (lowb+1 to highb-1) =
c_r_st_rec2_vector_2.f2 (lowb+1 to highb-1) and
(savtime + 10 ns) = Std.Standard.Now ;
s_r_st_rec2_vector.f2 (lowb+1 to highb-1) <= transport
c_r_st_rec2_vector_1.f2
(lowb+1 to highb-1) after 5 ns ;
--
when 4
=> correct :=
correct and
s_r_st_rec2_vector.f2 (lowb+1 to highb-1) =
c_r_st_rec2_vector_1.f2 (lowb+1 to highb-1) and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00120" ,
"One transport transaction occurred on signal " &
"asg with slice name prefixed by a selected name on LHS",
correct ) ;
test_report ( "ARCH00120" ,
"Old transactions were removed on signal " &
"asg with slice name prefixed by a selected name on LHS",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00120" ,
"Old transactions were removed on signal " &
"asg with slice name prefixed by a selected name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_r_st_rec2_vector <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
end Proc1 ;
--
begin
Proc1 ;
end process P5 ;
--
PGEN_CHKP_6 :
process ( chk_r_st_rec3_vector )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P6" ,
"Transport transactions entirely completed",
chk_r_st_rec3_vector = 4 ) ;
end if ;
end process PGEN_CHKP_6 ;
--
P6 :
process ( s_r_st_rec3_vector )
variable correct : boolean ;
variable counter : integer := 0 ;
variable savtime : time ;
--
procedure Proc1 is
begin
case counter is
when 0
=> s_r_st_rec3_vector.f2 (lowb+1 to highb-1) <= transport
c_r_st_rec3_vector_2.f2
(lowb+1 to highb-1) after 10 ns,
c_r_st_rec3_vector_1.f2
(lowb+1 to highb-1) after 20 ns ;
--
when 1
=> correct :=
s_r_st_rec3_vector.f2 (lowb+1 to highb-1) =
c_r_st_rec3_vector_2.f2 (lowb+1 to highb-1) and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_r_st_rec3_vector.f2 (lowb+1 to highb-1) =
c_r_st_rec3_vector_1.f2 (lowb+1 to highb-1) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00120.P6" ,
"Multi transport transactions occurred on signal " &
"asg with slice name prefixed by a selected name on LHS",
correct ) ;
s_r_st_rec3_vector.f2 (lowb+1 to highb-1) <= transport
c_r_st_rec3_vector_2.f2
(lowb+1 to highb-1) after 10 ns ,
c_r_st_rec3_vector_1.f2
(lowb+1 to highb-1) after 20 ns ,
c_r_st_rec3_vector_2.f2
(lowb+1 to highb-1) after 30 ns ,
c_r_st_rec3_vector_1.f2
(lowb+1 to highb-1) after 40 ns ;
--
when 3
=> correct :=
s_r_st_rec3_vector.f2 (lowb+1 to highb-1) =
c_r_st_rec3_vector_2.f2 (lowb+1 to highb-1) and
(savtime + 10 ns) = Std.Standard.Now ;
s_r_st_rec3_vector.f2 (lowb+1 to highb-1) <= transport
c_r_st_rec3_vector_1.f2
(lowb+1 to highb-1) after 5 ns ;
--
when 4
=> correct :=
correct and
s_r_st_rec3_vector.f2 (lowb+1 to highb-1) =
c_r_st_rec3_vector_1.f2 (lowb+1 to highb-1) and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00120" ,
"One transport transaction occurred on signal " &
"asg with slice name prefixed by a selected name on LHS",
correct ) ;
test_report ( "ARCH00120" ,
"Old transactions were removed on signal " &
"asg with slice name prefixed by a selected name on LHS",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00120" ,
"Old transactions were removed on signal " &
"asg with slice name prefixed by a selected name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_r_st_rec3_vector <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
end Proc1 ;
--
begin
Proc1 ;
end process P6 ;
--
--
end ARCH00120 ;
--
entity ENT00120_Test_Bench is
end ENT00120_Test_Bench ;
--
architecture ARCH00120_Test_Bench of ENT00120_Test_Bench is
begin
L1:
block
component UUT
end component ;
for CIS1 : UUT use entity WORK.E00000 ( ARCH00120 ) ;
begin
CIS1 : UUT ;
end block L1 ;
end ARCH00120_Test_Bench ;
| gpl-3.0 | c6bd29bae9017680ba95a026b67e0657 | 0.511595 | 3.446345 | false | false | false | false |
grwlf/vsim | vhdl_ct/ct00494.vhd | 1 | 8,927 | -------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
-------------------------------------------------------------------------------
--
-- TEST NAME:
--
-- CT00494
--
-- AUTHOR:
--
-- A. Wilmot
--
-- TEST OBJECTIVES:
--
-- 7.3.2.2 (5)
-- 7.3.2.2 (11)
--
-- DESIGN UNIT ORDERING:
--
-- ENT00494(ARCH00494)
-- ENT00494_Test_Bench(ARCH00494_Test_Bench)
--
-- REVISION HISTORY:
--
-- 10-AUG-1987 - initial revision
--
-- NOTES:
--
-- self-checking
-- automatically generated
--
use WORK.STANDARD_TYPES.all ;
entity ENT00494 is
generic (
constant g_a11 : boolean := false ;
constant g_a12 : boolean := true ;
constant g_a21 : integer := 1 ;
constant g_a22 : integer := 5 ;
constant g_b11 : integer := 0 ;
constant g_b12 : integer := 0 ;
constant g_b21 : integer := -5 ;
constant g_b22 : integer := -3 ;
constant g_c1 : integer := 0 ;
constant g_c2 : integer := 4 ;
constant g_d1 : integer := 3 ;
constant g_d2 : integer := 5 ;
constant g_r1 : integer := 1
) ;
constant r1 : integer := 1 ;
--
type rec_arr is array ( integer range <> ) of boolean ;
type rec_1 is record
f1 : integer range - g_r1 to g_r1 ;
-- f2 : rec_arr (-g_r1 to g_r1) ;
f3, f4 : integer ;
end record ;
-- constant c_rec_arr : rec_arr (-g_r1 to g_r1) :=
-- (true, false, false) ;
-- constant c_rec_1_1 : rec_1 := (1, (true, false, false), 1, 0) ;
-- constant c_rec_1_2 : rec_1 := (0, (true, false, false), 0, 1) ;
constant c_rec_1_1 : rec_1 := (1, 1, 0) ;
constant c_rec_1_2 : rec_1 := (0, 0, 1) ;
--
type arr_1 is array ( boolean range <> , integer range <> )
of rec_1 ;
type time_matrix is array ( integer range <> , integer range <> )
of time ;
--
--
subtype arange1 is boolean range g_a11 to g_a12 ;
subtype arange2 is integer range g_a21 to g_a22 ;
subtype brange1 is integer range g_b11 to g_b12 ;
subtype brange2 is integer range g_b21 to g_b22 ;
subtype crange is integer range g_c1 to g_c2 ;
subtype drange is integer range g_d1 to g_d2 ;
--
subtype st_arr_1 is arr_1 ( arange1 , arange2 ) ;
subtype st_time_matrix is time_matrix ( brange1 , brange2 ) ;
subtype st_bit_vector is bit_vector ( crange ) ;
subtype st_string is string ( drange ) ;
--
--
end ENT00494 ;
--
architecture ARCH00494 of ENT00494 is
begin
B1 :
block
--
function f_arr_1 return st_arr_1 is
begin
return ( others => (others => c_rec_1_1) ) ;
end f_arr_1 ;
function f_time_matrix return st_time_matrix is
begin
return
(others => (others => 15ms) ) ;
end f_time_matrix ;
function f_bit_vector return st_bit_vector is
begin
return
( others => '0' ) ;
end f_bit_vector ;
function f_string return st_string is
begin
return
( others => 'a' ) ;
end f_string ;
function f_rec_1 return rec_1 is
begin
return
-- ( f2 => (others => false), others => 0) ;
( others => 0) ;
end f_rec_1 ;
procedure p1 (
constant d_a11 : boolean := false ;
constant d_a12 : boolean := true ;
constant d_a21 : integer := 1 ;
constant d_a22 : integer := 5 ;
constant d_b11 : integer := 0 ;
constant d_b12 : integer := 0 ;
constant d_b21 : integer := -5 ;
constant d_b22 : integer := -3 ;
constant d_c1 : integer := 0 ;
constant d_c2 : integer := 4 ;
constant d_d1 : integer := 3 ;
constant d_d2 : integer := 5 ;
constant d_r1 : integer := 1
) is
--
type rec_arr is array ( integer range <> ) of boolean ;
type rec_1 is record
f1 : integer range - d_r1 to d_r1 ;
-- f2 : rec_arr (-d_r1 to d_r1) ;
f3, f4 : integer ;
end record ;
-- constant c_rec_arr : rec_arr (-d_r1 to d_r1) :=
-- (true, false, false) ;
-- constant c_rec_1_1 : rec_1 := (1, (true, false, false), 1, 0) ;
-- constant c_rec_1_2 : rec_1 := (0, (true, false, false), 0, 1) ;
constant c_rec_1_1 : rec_1 := (1, 1, 0) ;
constant c_rec_1_2 : rec_1 := (0, 0, 1) ;
--
type arr_1 is array ( boolean range <> , integer range <> )
of rec_1 ;
type time_matrix is array ( integer range <> , integer range <> )
of time ;
--
--
subtype arange1 is boolean range d_a11 to d_a12 ;
subtype arange2 is integer range d_a21 to d_a22 ;
subtype brange1 is integer range d_b11 to d_b12 ;
subtype brange2 is integer range d_b21 to d_b22 ;
subtype crange is integer range d_c1 to d_c2 ;
subtype drange is integer range d_d1 to d_d2 ;
--
subtype st_arr_1 is arr_1 ( arange1 , arange2 ) ;
subtype st_time_matrix is time_matrix ( brange1 , brange2 ) ;
subtype st_bit_vector is bit_vector ( crange ) ;
subtype st_string is string ( drange ) ;
--
variable bool : boolean := true ;
function f_arr_1 return st_arr_1 is
begin
return ( others => (others => c_rec_1_1) ) ;
end f_arr_1 ;
function f_time_matrix return st_time_matrix is
begin
return
(others => (others => 15ms) ) ;
end f_time_matrix ;
function f_bit_vector return st_bit_vector is
begin
return
( others => '0' ) ;
end f_bit_vector ;
function f_string return st_string is
begin
return
( others => 'a' ) ;
end f_string ;
function f_rec_1 return rec_1 is
begin
return
-- ( f2 => (others => false), others => 0) ;
( others => 0) ;
end f_rec_1 ;
begin
for i in 1 to 5 loop
bool := bool and p1.f_arr_1(false, i) = c_rec_1_1 ;
end loop ;
for i in 1 to 5 loop
bool := bool and p1.f_arr_1(true, i) = c_rec_1_1 ;
end loop ;
--
for i in integer'(-5) to -3 loop
bool := bool and p1.f_time_matrix(0, i) = 15 ms ;
end loop ;
--
bool := bool and p1.f_bit_vector = B"00000" ;
--
bool := bool and p1.f_string = "aaa" ;
--
bool := bool and p1.f_rec_1.f1 = 0 and p1.f_rec_1.f4 = 0
and p1.f_rec_1.f3 = 0 ;
-- bool := bool and p1.f_rec_1.f2(1) = false
-- and p1.f_rec_1.f2(0) = false and
-- p1.f_rec_1.f2(-1) = false ;
--
--
test_report ( "ARCH00494" ,
"Aggregates with others choice associated with function"
& " return (dynamic static)" ,
bool ) ;
end p1 ;
begin
process
variable bool : boolean := true ;
begin
for i in 1 to 5 loop
bool := bool and f_arr_1(false, i) = c_rec_1_1 ;
end loop ;
for i in 1 to 5 loop
bool := bool and f_arr_1(true, i) = c_rec_1_1 ;
end loop ;
--
for i in integer'(-5) to -3 loop
bool := bool and f_time_matrix(0, i) = 15 ms ;
end loop ;
--
bool := bool and f_bit_vector = B"00000" ;
--
bool := bool and f_string = "aaa" ;
--
bool := bool and f_rec_1.f1 = 0 and f_rec_1.f4 = 0
and f_rec_1.f3 = 0 ;
-- bool := bool and f_rec_1.f2(1) = false
-- and f_rec_1.f2(0) = false and
-- f_rec_1.f2(-1) = false ;
--
--
test_report ( "ARCH00494" ,
"Aggregates with others choice associated with function"
& " return (globally static)" ,
bool ) ;
p1 ( open, open, open, open,
open, open, open, open,
open, open, open, open, open ) ;
wait ;
end process ;
end block B1 ;
end ARCH00494 ;
--
entity ENT00494_Test_Bench is
end ENT00494_Test_Bench ;
--
architecture ARCH00494_Test_Bench of ENT00494_Test_Bench is
begin
L1:
block
component UUT
end component ;
--
for CIS1 : UUT use entity WORK.ENT00494 ( ARCH00494 ) ;
begin
CIS1 : UUT ;
end block L1 ;
end ARCH00494_Test_Bench ;
| gpl-3.0 | f0ac36dfa10f4d9b1ca941accdda897e | 0.472835 | 3.476246 | false | false | false | false |
jairov4/accel-oil | solution_virtex5/syn/vhdl/sample_iterator_get_offset.vhd | 2 | 12,688 | -- ==============================================================
-- RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2014.1
-- Copyright (C) 2014 Xilinx Inc. All rights reserved.
--
-- ===========================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity sample_iterator_get_offset is
port (
ap_clk : IN STD_LOGIC;
ap_rst : IN STD_LOGIC;
ap_start : IN STD_LOGIC;
ap_done : OUT STD_LOGIC;
ap_idle : OUT STD_LOGIC;
ap_ready : OUT STD_LOGIC;
indices_req_din : OUT STD_LOGIC;
indices_req_full_n : IN STD_LOGIC;
indices_req_write : OUT STD_LOGIC;
indices_rsp_empty_n : IN STD_LOGIC;
indices_rsp_read : OUT STD_LOGIC;
indices_address : OUT STD_LOGIC_VECTOR (31 downto 0);
indices_datain : IN STD_LOGIC_VECTOR (55 downto 0);
indices_dataout : OUT STD_LOGIC_VECTOR (55 downto 0);
indices_size : OUT STD_LOGIC_VECTOR (31 downto 0);
ap_ce : IN STD_LOGIC;
i_index : IN STD_LOGIC_VECTOR (15 downto 0);
i_sample : IN STD_LOGIC_VECTOR (15 downto 0);
sample_buffer_size : IN STD_LOGIC_VECTOR (31 downto 0);
sample_length : IN STD_LOGIC_VECTOR (15 downto 0);
ap_return : OUT STD_LOGIC_VECTOR (31 downto 0) );
end;
architecture behav of sample_iterator_get_offset is
constant ap_const_logic_1 : STD_LOGIC := '1';
constant ap_const_logic_0 : STD_LOGIC := '0';
constant ap_ST_pp0_stg0_fsm_0 : STD_LOGIC_VECTOR (0 downto 0) := "0";
constant ap_const_lv32_1 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000001";
constant ap_const_lv32_30 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000110000";
constant ap_const_lv32_37 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000110111";
constant ap_const_lv56_0 : STD_LOGIC_VECTOR (55 downto 0) := "00000000000000000000000000000000000000000000000000000000";
signal ap_CS_fsm : STD_LOGIC_VECTOR (0 downto 0) := "0";
signal ap_reg_ppiten_pp0_it0 : STD_LOGIC;
signal ap_reg_ppiten_pp0_it1 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it2 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it3 : STD_LOGIC := '0';
signal i_sample_read_reg_127 : STD_LOGIC_VECTOR (15 downto 0);
signal ap_reg_ppstg_i_sample_read_reg_127_pp0_it1 : STD_LOGIC_VECTOR (15 downto 0);
signal ap_reg_ppstg_i_sample_read_reg_127_pp0_it2 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_9_fu_92_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_9_reg_138 : STD_LOGIC_VECTOR (31 downto 0);
signal indices_stride_load_new_reg_143 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_fu_81_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_6_fu_112_p0 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_6_fu_112_p1 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_6_fu_112_p2 : STD_LOGIC_VECTOR (23 downto 0);
signal tmp_6_cast_fu_118_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_NS_fsm : STD_LOGIC_VECTOR (0 downto 0);
signal ap_sig_pprstidle_pp0 : STD_LOGIC;
signal tmp_6_fu_112_p00 : STD_LOGIC_VECTOR (23 downto 0);
signal tmp_6_fu_112_p10 : STD_LOGIC_VECTOR (23 downto 0);
begin
-- the current state (ap_CS_fsm) of the state machine. --
ap_CS_fsm_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_CS_fsm <= ap_ST_pp0_stg0_fsm_0;
else
ap_CS_fsm <= ap_NS_fsm;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it1 assign process. --
ap_reg_ppiten_pp0_it1_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_reg_ppiten_pp0_it1 <= ap_const_logic_0;
else
if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it2) and (indices_rsp_empty_n = ap_const_logic_0)) or not((ap_const_logic_1 = ap_ce)))))) then
ap_reg_ppiten_pp0_it1 <= ap_reg_ppiten_pp0_it0;
end if;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it2 assign process. --
ap_reg_ppiten_pp0_it2_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_reg_ppiten_pp0_it2 <= ap_const_logic_0;
else
if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it2) and (indices_rsp_empty_n = ap_const_logic_0)) or not((ap_const_logic_1 = ap_ce)))))) then
ap_reg_ppiten_pp0_it2 <= ap_reg_ppiten_pp0_it1;
end if;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it3 assign process. --
ap_reg_ppiten_pp0_it3_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_reg_ppiten_pp0_it3 <= ap_const_logic_0;
else
if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it2) and (indices_rsp_empty_n = ap_const_logic_0)) or not((ap_const_logic_1 = ap_ce)))))) then
ap_reg_ppiten_pp0_it3 <= ap_reg_ppiten_pp0_it2;
end if;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it2) and (indices_rsp_empty_n = ap_const_logic_0)))) and (ap_const_logic_1 = ap_ce))) then
ap_reg_ppstg_i_sample_read_reg_127_pp0_it1 <= i_sample_read_reg_127;
ap_reg_ppstg_i_sample_read_reg_127_pp0_it2 <= ap_reg_ppstg_i_sample_read_reg_127_pp0_it1;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it2) and (indices_rsp_empty_n = ap_const_logic_0)))) and (ap_const_logic_1 = ap_ce))) then
i_sample_read_reg_127 <= i_sample;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it2) and (indices_rsp_empty_n = ap_const_logic_0)))) and (ap_const_logic_1 = ap_ce))) then
indices_stride_load_new_reg_143 <= indices_datain(55 downto 48);
tmp_9_reg_138 <= tmp_9_fu_92_p1;
end if;
end if;
end process;
-- the next state (ap_NS_fsm) of the state machine. --
ap_NS_fsm_assign_proc : process (ap_start , ap_CS_fsm , ap_reg_ppiten_pp0_it0 , ap_reg_ppiten_pp0_it2 , indices_rsp_empty_n , ap_ce , ap_sig_pprstidle_pp0)
begin
case ap_CS_fsm is
when ap_ST_pp0_stg0_fsm_0 =>
ap_NS_fsm <= ap_ST_pp0_stg0_fsm_0;
when others =>
ap_NS_fsm <= "X";
end case;
end process;
-- ap_done assign process. --
ap_done_assign_proc : process(ap_start, ap_CS_fsm, ap_reg_ppiten_pp0_it0, ap_reg_ppiten_pp0_it2, ap_reg_ppiten_pp0_it3, indices_rsp_empty_n, ap_ce)
begin
if (((not((ap_const_logic_1 = ap_start)) and (ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it0)) or ((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it3) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it2) and (indices_rsp_empty_n = ap_const_logic_0)))) and (ap_const_logic_1 = ap_ce)))) then
ap_done <= ap_const_logic_1;
else
ap_done <= ap_const_logic_0;
end if;
end process;
-- ap_idle assign process. --
ap_idle_assign_proc : process(ap_start, ap_CS_fsm, ap_reg_ppiten_pp0_it0, ap_reg_ppiten_pp0_it1, ap_reg_ppiten_pp0_it2, ap_reg_ppiten_pp0_it3)
begin
if ((not((ap_const_logic_1 = ap_start)) and (ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it0) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it1) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it2) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it3))) then
ap_idle <= ap_const_logic_1;
else
ap_idle <= ap_const_logic_0;
end if;
end process;
-- ap_ready assign process. --
ap_ready_assign_proc : process(ap_start, ap_CS_fsm, ap_reg_ppiten_pp0_it0, ap_reg_ppiten_pp0_it2, indices_rsp_empty_n, ap_ce)
begin
if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it2) and (indices_rsp_empty_n = ap_const_logic_0)))) and (ap_const_logic_1 = ap_ce))) then
ap_ready <= ap_const_logic_1;
else
ap_ready <= ap_const_logic_0;
end if;
end process;
ap_reg_ppiten_pp0_it0 <= ap_start;
ap_return <= std_logic_vector(unsigned(tmp_6_cast_fu_118_p1) + unsigned(tmp_9_reg_138));
-- ap_sig_pprstidle_pp0 assign process. --
ap_sig_pprstidle_pp0_assign_proc : process(ap_start, ap_reg_ppiten_pp0_it0, ap_reg_ppiten_pp0_it1, ap_reg_ppiten_pp0_it2)
begin
if (((ap_const_logic_0 = ap_reg_ppiten_pp0_it0) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it1) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it2) and (ap_const_logic_0 = ap_start))) then
ap_sig_pprstidle_pp0 <= ap_const_logic_1;
else
ap_sig_pprstidle_pp0 <= ap_const_logic_0;
end if;
end process;
indices_address <= tmp_fu_81_p1(32 - 1 downto 0);
indices_dataout <= ap_const_lv56_0;
indices_req_din <= ap_const_logic_0;
-- indices_req_write assign process. --
indices_req_write_assign_proc : process(ap_start, ap_CS_fsm, ap_reg_ppiten_pp0_it0, ap_reg_ppiten_pp0_it2, indices_rsp_empty_n, ap_ce)
begin
if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it2) and (indices_rsp_empty_n = ap_const_logic_0)))) and (ap_const_logic_1 = ap_ce))) then
indices_req_write <= ap_const_logic_1;
else
indices_req_write <= ap_const_logic_0;
end if;
end process;
-- indices_rsp_read assign process. --
indices_rsp_read_assign_proc : process(ap_start, ap_CS_fsm, ap_reg_ppiten_pp0_it0, ap_reg_ppiten_pp0_it2, indices_rsp_empty_n, ap_ce)
begin
if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it2) and (indices_rsp_empty_n = ap_const_logic_0)))) and (ap_const_logic_1 = ap_ce))) then
indices_rsp_read <= ap_const_logic_1;
else
indices_rsp_read <= ap_const_logic_0;
end if;
end process;
indices_size <= ap_const_lv32_1;
tmp_6_cast_fu_118_p1 <= std_logic_vector(resize(unsigned(tmp_6_fu_112_p2),32));
tmp_6_fu_112_p0 <= tmp_6_fu_112_p00(16 - 1 downto 0);
tmp_6_fu_112_p00 <= std_logic_vector(resize(unsigned(ap_reg_ppstg_i_sample_read_reg_127_pp0_it2),24));
tmp_6_fu_112_p1 <= tmp_6_fu_112_p10(8 - 1 downto 0);
tmp_6_fu_112_p10 <= std_logic_vector(resize(unsigned(indices_stride_load_new_reg_143),24));
tmp_6_fu_112_p2 <= std_logic_vector(resize(unsigned(tmp_6_fu_112_p0) * unsigned(tmp_6_fu_112_p1), 24));
tmp_9_fu_92_p1 <= indices_datain(32 - 1 downto 0);
tmp_fu_81_p1 <= std_logic_vector(resize(unsigned(i_index),64));
end behav;
| lgpl-3.0 | 671c7fc36a3a8ababa8dbd3efced56da | 0.600095 | 2.761863 | false | false | false | false |
wsoltys/AtomFpga | src/AVR8/CommonPacks/SynthCtrlPack.vhd | 1 | 1,290 | -- *****************************************************************************************
-- AVR synthesis control package
-- Version 1.32 (Special version for the JTAG OCD)
-- Modified 14.07.2005
-- Designed by Ruslan Lepetenok
-- *****************************************************************************************
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
package SynthCtrlPack is
-- Please note: Do not change these settings, this is not quite ready yet. Jack Gassett
-- Control the size of Program and Data memory.
constant CDATAMEMSIZE : integer := 11; --2^(x+1)=Data SRAM Memory Size (10=2048) (Default 11=4096) (12=8192)
constant CPROGMEMSIZE : integer := 12; --(2^(x+1))*2)=Program Memory Size (10=4096) (11=8192) (Default 12=16384)
-- Calculate at Wolfram Alpha (http://www.wolframalpha.com/input/?i=%282^%28x%2B1%29%29*2%29%2Cx%3D12)
-- Reset generator
constant CSecondClockUsed : boolean := FALSE;
constant CImplClockSw : boolean := FALSE;
-- Only for ASICs
constant CSynchLatchUsed : boolean := FALSE;
-- Register file
constant CResetRegFile : boolean := TRUE;
-- External multiplexer size
constant CExtMuxInSize : positive := 16;
end SynthCtrlPack;
| apache-2.0 | aedf7131e8b5986699e567b15532649d | 0.583721 | 3.563536 | false | false | false | false |
jairov4/accel-oil | solution_kintex7/sim/vhdl/AESL_autobus_nfa_finals_buckets.vhd | 1 | 28,967 | library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
use IEEE.numeric_std.all;
use ieee.std_logic_textio.all;
use std.textio.all;
library work;
use work.all;
entity AESL_autobus_nfa_finals_buckets is
generic (
constant TV_IN : STRING (1 to 79) := "../tv/cdatafile/c.nfa_accept_samples_generic_hw.autotvin_nfa_finals_buckets.dat";
constant TV_OUT : STRING (1 to 84) := "../tv/rtldatafile/rtl.nfa_accept_samples_generic_hw.autotvout_nfa_finals_buckets.dat";
constant DATA_WIDTH : INTEGER := 32;
constant ADDR_WIDTH : INTEGER := 32;
constant DEPTH : INTEGER := 2;
constant FIFO_DEPTH : INTEGER := 32;
constant FIFO_DEPTH_ADDR_WIDTH : INTEGER := 32
);
port (
clk : IN STD_LOGIC;
rst : IN STD_LOGIC;
bus_req_RW : IN STD_LOGIC;
bus_req_full_n : OUT STD_LOGIC;
bus_req_RW_en : IN STD_LOGIC;
bus_rsp_empty_n : OUT STD_LOGIC;
bus_rsp_read : IN STD_LOGIC;
bus_address : IN STD_LOGIC_VECTOR (ADDR_WIDTH - 1 downto 0);
bus_din : IN STD_LOGIC_VECTOR (DATA_WIDTH - 1 downto 0);
bus_dout : OUT STD_LOGIC_VECTOR (DATA_WIDTH - 1 downto 0);
bus_size : IN STD_LOGIC_VECTOR ( 31 downto 0);
ready : IN STD_LOGIC;
done : IN STD_LOGIC
);
end AESL_autobus_nfa_finals_buckets;
architecture behav of AESL_autobus_nfa_finals_buckets is
-- Inner signals
signal FIFO_req_ptr_r : STD_LOGIC_VECTOR (FIFO_DEPTH_ADDR_WIDTH - 1 downto 0) := (others => '0');
signal FIFO_req_ptr_w : STD_LOGIC_VECTOR (FIFO_DEPTH_ADDR_WIDTH - 1 downto 0) := (others => '0');
signal FIFO_req_flag : STD_LOGIC := '0'; -- 0: empty hint, 1: full hint
signal FIFO_req_empty : STD_LOGIC := '0';
signal FIFO_req_full : STD_LOGIC := '0';
signal FIFO_req_read : STD_LOGIC := '0';
signal FIFO_req_burst_flag:STD_LOGIC := '0';
signal FIFO_rsp_ptr_r : STD_LOGIC_VECTOR (ADDR_WIDTH - 1 downto 0) := (others => '0');
signal FIFO_rsp_ptr_w : STD_LOGIC_VECTOR (ADDR_WIDTH - 1 downto 0) := (others => '0');
signal FIFO_rsp_flag : STD_LOGIC := '0';
signal FIFO_rsp_empty : STD_LOGIC;
signal FIFO_rsp_full : STD_LOGIC;
signal FIFO_rsp_write : STD_LOGIC;
signal FIFO_req_temp_state : STD_LOGIC_VECTOR(1 downto 0) := "00";
type arr_fifo_req_RW is array(0 to FIFO_DEPTH - 1) of STD_LOGIC;
type arr_fifo_req_addr is array(0 to FIFO_DEPTH - 1) of STD_LOGIC_VECTOR(ADDR_WIDTH - 1 downto 0);
type arr_fifo_req_din is array(0 to FIFO_DEPTH - 1) of STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0);
type arr_fifo_req_size is array(0 to FIFO_DEPTH - 1) of STD_LOGIC_VECTOR(31 downto 0);
type arr_mem is array(0 to DEPTH - 1) of STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0);
shared variable FIFO_req_RW : arr_fifo_req_RW;
shared variable FIFO_req_address: arr_fifo_req_addr;
shared variable FIFO_req_din : arr_fifo_req_din;
shared variable FIFO_req_size : arr_fifo_req_size;
shared variable mem : arr_mem := (others => (others => '0'));
shared variable FIFO_rsp_mem : arr_mem := (others => (others => '0'));
procedure esl_read_token (file textfile: TEXT; textline: inout LINE; token: out STRING; token_len: out INTEGER) is
variable whitespace : CHARACTER;
variable i : INTEGER;
variable ok: BOOLEAN;
variable buff: STRING(1 to token'length);
begin
ok := false;
i := 1;
loop_main: while not endfile(textfile) loop
if textline = null or textline'length = 0 then
readline(textfile, textline);
end if;
loop_remove_whitespace: while textline'length > 0 loop
if textline(textline'left) = ' ' or
textline(textline'left) = HT or
textline(textline'left) = CR or
textline(textline'left) = LF then
read(textline, whitespace);
else
exit loop_remove_whitespace;
end if;
end loop;
loop_aesl_read_token: while textline'length > 0 and i <= buff'length loop
if textline(textline'left) = ' ' or
textline(textline'left) = HT or
textline(textline'left) = CR or
textline(textline'left) = LF then
exit loop_aesl_read_token;
else
read(textline, buff(i));
i := i + 1;
end if;
ok := true;
end loop;
if ok = true then
exit loop_main;
end if;
end loop;
buff(i) := ' ';
token := buff;
token_len:= i-1;
end procedure esl_read_token;
procedure esl_read_token (file textfile: TEXT;
textline: inout LINE;
token: out STRING) is
variable i : INTEGER;
begin
esl_read_token (textfile, textline, token, i);
end procedure esl_read_token;
function esl_add(v1, v2 : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
variable res : unsigned(v1'length-1 downto 0);
begin
res := unsigned(v1) + unsigned(v2);
return std_logic_vector(res);
end function;
function esl_sub(v1, v2 : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
variable res : unsigned(v1'length-1 downto 0);
begin
res := unsigned(v1) - unsigned(v2);
return std_logic_vector(res);
end function;
function esl_str2lv_hex (RHS : STRING; data_width : INTEGER) return STD_LOGIC_VECTOR is
variable ret : STD_LOGIC_VECTOR(data_width - 1 downto 0);
variable idx : integer := 3;
begin
ret := (others => '0');
if(RHS(1) /= '0' and (RHS(2) /= 'x' or RHS(2) /= 'X')) then
report "Error! The format of hex number is not initialed by 0x";
end if;
while true loop
if (data_width > 4) then
case RHS(idx) is
when '0' => ret := ret(data_width - 5 downto 0) & "0000";
when '1' => ret := ret(data_width - 5 downto 0) & "0001";
when '2' => ret := ret(data_width - 5 downto 0) & "0010";
when '3' => ret := ret(data_width - 5 downto 0) & "0011";
when '4' => ret := ret(data_width - 5 downto 0) & "0100";
when '5' => ret := ret(data_width - 5 downto 0) & "0101";
when '6' => ret := ret(data_width - 5 downto 0) & "0110";
when '7' => ret := ret(data_width - 5 downto 0) & "0111";
when '8' => ret := ret(data_width - 5 downto 0) & "1000";
when '9' => ret := ret(data_width - 5 downto 0) & "1001";
when 'a' | 'A' => ret := ret(data_width - 5 downto 0) & "1010";
when 'b' | 'B' => ret := ret(data_width - 5 downto 0) & "1011";
when 'c' | 'C' => ret := ret(data_width - 5 downto 0) & "1100";
when 'd' | 'D' => ret := ret(data_width - 5 downto 0) & "1101";
when 'e' | 'E' => ret := ret(data_width - 5 downto 0) & "1110";
when 'f' | 'F' => ret := ret(data_width - 5 downto 0) & "1111";
when ' ' => return ret;
when others => report "Wrong hex char " & RHS(idx); return ret;
end case;
elsif (data_width = 4) then
case RHS(idx) is
when '0' => ret := "0000";
when '1' => ret := "0001";
when '2' => ret := "0010";
when '3' => ret := "0011";
when '4' => ret := "0100";
when '5' => ret := "0101";
when '6' => ret := "0110";
when '7' => ret := "0111";
when '8' => ret := "1000";
when '9' => ret := "1001";
when 'a' | 'A' => ret := "1010";
when 'b' | 'B' => ret := "1011";
when 'c' | 'C' => ret := "1100";
when 'd' | 'D' => ret := "1101";
when 'e' | 'E' => ret := "1110";
when 'f' | 'F' => ret := "1111";
when ' ' => return ret;
when others => report "Wrong hex char " & RHS(idx); return ret;
end case;
elsif (data_width = 3) then
case RHS(idx) is
when '0' => ret := "000";
when '1' => ret := "001";
when '2' => ret := "010";
when '3' => ret := "011";
when '4' => ret := "100";
when '5' => ret := "101";
when '6' => ret := "110";
when '7' => ret := "111";
when ' ' => return ret;
when others => report "Wrong hex char " & RHS(idx); return ret;
end case;
elsif (data_width = 2) then
case RHS(idx) is
when '0' => ret := "00";
when '1' => ret := "01";
when '2' => ret := "10";
when '3' => ret := "11";
when ' ' => return ret;
when others => report "Wrong hex char " & RHS(idx); return ret;
end case;
elsif (data_width = 1) then
case RHS(idx) is
when '0' => ret := "0";
when '1' => ret := "1";
when ' ' => return ret;
when others => report "Wrong hex char " & RHS(idx); return ret;
end case;
else
report string'("Wrong data_width.");
return ret;
end if;
idx := idx + 1;
end loop;
return ret;
end function;
function esl_conv_string_hex (lv : STD_LOGIC_VECTOR) return STRING is
constant str_len : integer := (lv'length + 3)/4;
variable ret : STRING (1 to str_len);
variable i, tmp: INTEGER;
variable normal_lv : STD_LOGIC_VECTOR(lv'length - 1 downto 0);
variable tmp_lv : STD_LOGIC_VECTOR(3 downto 0);
begin
normal_lv := lv;
for i in 1 to str_len loop
if(i = 1) then
if((lv'length mod 4) = 3) then
tmp_lv(2 downto 0) := normal_lv(lv'length - 1 downto lv'length - 3);
case tmp_lv(2 downto 0) is
when "000" => ret(i) := '0';
when "001" => ret(i) := '1';
when "010" => ret(i) := '2';
when "011" => ret(i) := '3';
when "100" => ret(i) := '4';
when "101" => ret(i) := '5';
when "110" => ret(i) := '6';
when "111" => ret(i) := '7';
when others => ret(i) := '0';
end case;
elsif((lv'length mod 4) = 2) then
tmp_lv(1 downto 0) := normal_lv(lv'length - 1 downto lv'length - 2);
case tmp_lv(1 downto 0) is
when "00" => ret(i) := '0';
when "01" => ret(i) := '1';
when "10" => ret(i) := '2';
when "11" => ret(i) := '3';
when others => ret(i) := '0';
end case;
elsif((lv'length mod 4) = 1) then
tmp_lv(0 downto 0) := normal_lv(lv'length - 1 downto lv'length - 1);
case tmp_lv(0 downto 0) is
when "0" => ret(i) := '0';
when "1" => ret(i) := '1';
when others=> ret(i) := '0';
end case;
elsif((lv'length mod 4) = 0) then
tmp_lv(3 downto 0) := normal_lv(lv'length - 1 downto lv'length - 4);
case tmp_lv(3 downto 0) is
when "0000" => ret(i) := '0';
when "0001" => ret(i) := '1';
when "0010" => ret(i) := '2';
when "0011" => ret(i) := '3';
when "0100" => ret(i) := '4';
when "0101" => ret(i) := '5';
when "0110" => ret(i) := '6';
when "0111" => ret(i) := '7';
when "1000" => ret(i) := '8';
when "1001" => ret(i) := '9';
when "1010" => ret(i) := 'a';
when "1011" => ret(i) := 'b';
when "1100" => ret(i) := 'c';
when "1101" => ret(i) := 'd';
when "1110" => ret(i) := 'e';
when "1111" => ret(i) := 'f';
when others => ret(i) := '0';
end case;
end if;
else
tmp_lv(3 downto 0) := normal_lv((str_len - i) * 4 + 3 downto (str_len - i) * 4);
case tmp_lv(3 downto 0) is
when "0000" => ret(i) := '0';
when "0001" => ret(i) := '1';
when "0010" => ret(i) := '2';
when "0011" => ret(i) := '3';
when "0100" => ret(i) := '4';
when "0101" => ret(i) := '5';
when "0110" => ret(i) := '6';
when "0111" => ret(i) := '7';
when "1000" => ret(i) := '8';
when "1001" => ret(i) := '9';
when "1010" => ret(i) := 'a';
when "1011" => ret(i) := 'b';
when "1100" => ret(i) := 'c';
when "1101" => ret(i) := 'd';
when "1110" => ret(i) := 'e';
when "1111" => ret(i) := 'f';
when others => ret(i) := '0';
end case;
end if;
end loop;
return ret;
end function;
begin
-------------- Assignment for output port -------------------
assign_proc : process
begin
wait until (clk'event and clk = '1');
wait for 0.4 ns;
bus_dout <= FIFO_rsp_mem(CONV_INTEGER(FIFO_rsp_ptr_r));
end process;
bus_rsp_proc : process(FIFO_rsp_empty)
begin
bus_rsp_empty_n <= not FIFO_rsp_empty;
end process;
bus_req_full_n_proc : process(FIFO_req_full)
begin
bus_req_full_n <= not FIFO_req_full;
end process;
FIFO_req_empty_full_proc : process(FIFO_req_ptr_r, FIFO_req_ptr_w, FIFO_req_flag)
begin
if(FIFO_req_ptr_r = FIFO_req_ptr_w) then
if(FIFO_req_flag = '1') then
FIFO_req_full <= '1';
FIFO_req_empty <= '0';
else
FIFO_req_full <= '0';
FIFO_req_empty <= '1';
end if;
else
FIFO_req_full <= '0';
FIFO_req_empty <= '0';
end if;
end process;
FIFO_rsp_empty_full_proc : process(FIFO_rsp_ptr_r, FIFO_rsp_ptr_w, FIFO_rsp_flag)
begin
if(FIFO_rsp_ptr_r = FIFO_rsp_ptr_w) then
if(FIFO_rsp_flag = '1') then
FIFO_rsp_full <= '1';
FIFO_rsp_empty <= '0';
else
FIFO_rsp_full <= '0';
FIFO_rsp_empty <= '1';
end if;
else
FIFO_rsp_full <= '0';
FIFO_rsp_empty <= '0';
end if;
end process;
-- Push RTL's req into FIFO_req
FIFO_req_write_proc : process(clk, rst)
begin
if(rst = '1') then
FIFO_req_ptr_w <= (others => '0');
elsif (clk'event and clk = '1') then
if(bus_req_RW_en = '1' and FIFO_req_full = '0') then
FIFO_req_RW(CONV_INTEGER(FIFO_req_ptr_w)) := bus_req_RW;
FIFO_req_address(CONV_INTEGER(FIFO_req_ptr_w)) := bus_address;
FIFO_req_din(CONV_INTEGER(FIFO_req_ptr_w)) := bus_din;
FIFO_req_size(CONV_INTEGER(FIFO_req_ptr_w)) := bus_size;
if(CONV_INTEGER(FIFO_req_ptr_w) /= FIFO_DEPTH - 1) then
FIFO_req_ptr_w <= esl_add(FIFO_req_ptr_w,"1");
else
FIFO_req_ptr_w <= (others => '0');
end if;
end if;
end if;
end process;
FIFO_req_read_proc : process(clk, rst)
variable FIFO_req_RW_temp : STD_LOGIC;
variable FIFO_req_address_temp : STD_LOGIC_VECTOR(ADDR_WIDTH - 1 downto 0);
variable FIFO_req_din_temp : STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0);
variable FIFO_req_size_temp : STD_LOGIC_VECTOR(31 downto 0);
constant IDLE_STATE : STD_LOGIC_VECTOR(1 downto 0) := "00";
constant READ_BURST_STATE : STD_LOGIC_VECTOR(1 downto 0) := "01";
constant WRITE_BURST_STATE : STD_LOGIC_VECTOR(1 downto 0) := "10";
begin
if(rst = '1') then
FIFO_req_temp_state <= IDLE_STATE;
FIFO_req_read <= '0';
FIFO_rsp_write <= '0';
elsif (clk'event and clk = '1') then
case FIFO_req_temp_state is
when IDLE_STATE =>
if(FIFO_req_empty = '0' and FIFO_rsp_full = '0') then
FIFO_req_read <= '1';
if(CONV_INTEGER(FIFO_req_ptr_r) /= FIFO_DEPTH - 1) then
FIFO_req_ptr_r <= esl_add(FIFO_req_ptr_r, "1");
else
FIFO_req_ptr_r <= (others => '0');
end if;
FIFO_req_RW_temp:= FIFO_req_RW(CONV_INTEGER(FIFO_req_ptr_r));
FIFO_req_address_temp := FIFO_req_address(CONV_INTEGER(FIFO_req_ptr_r));
FIFO_req_din_temp := FIFO_req_din(CONV_INTEGER(FIFO_req_ptr_r));
FIFO_req_size_temp := FIFO_req_size(CONV_INTEGER(FIFO_req_ptr_r));
-- Read request
if(FIFO_req_RW_temp = '0') then
FIFO_rsp_write <= '1'; -- Indicate the output is valid
FIFO_rsp_mem(CONV_INTEGER(FIFO_rsp_ptr_w)) := mem(CONV_INTEGER(FIFO_req_address_temp));
if(FIFO_rsp_ptr_w /= DEPTH - 1) then
FIFO_rsp_ptr_w <= esl_add(FIFO_rsp_ptr_w,"1");
else
FIFO_rsp_ptr_w <= (others => '0');
end if;
if(CONV_INTEGER(FIFO_req_size_temp) /= 0 and CONV_INTEGER(FIFO_req_size_temp) /= 1) then -- Read burst request
FIFO_req_temp_state <= READ_BURST_STATE; -- To deal with the rest data
end if;
else
FIFO_rsp_write <= '0'; -- Indicate the output is not valid
if(CONV_INTEGER(FIFO_req_size_temp) = 0 or CONV_INTEGER(FIFO_req_size_temp) = 1) then -- Write single request
mem(CONV_INTEGER(FIFO_req_address_temp)) := FIFO_req_din_temp;
else -- Write burst request
mem(CONV_INTEGER(FIFO_req_address_temp)) := FIFO_req_din_temp; -- Input the first data
FIFO_req_temp_state <= WRITE_BURST_STATE; -- To deal with the rest data
end if;
end if;
else -- There is no request in the FIFO_req
FIFO_req_read <= '0';
FIFO_rsp_write <= '0';
end if;
when READ_BURST_STATE =>
FIFO_req_read <= '0'; -- Stop reading the next request
FIFO_req_size_temp := esl_sub(FIFO_req_size_temp, "1");
if(CONV_INTEGER(FIFO_req_address_temp) /= DEPTH - 1) then
FIFO_req_address_temp := esl_add(FIFO_req_address_temp, "1");
else
report "Burst read out of size!";
end if;
FIFO_rsp_mem(CONV_INTEGER(FIFO_rsp_ptr_w)) := mem(CONV_INTEGER(FIFO_req_address_temp));
if(CONV_INTEGER(FIFO_rsp_ptr_w) /= DEPTH - 1) then
FIFO_rsp_ptr_w <= esl_add(FIFO_rsp_ptr_w, "1");
else
FIFO_rsp_ptr_w <= (others => '0');
end if;
if(CONV_INTEGER(FIFO_req_size_temp) = 1) then -- The last one is done
FIFO_req_temp_state <= IDLE_STATE;
end if;
when WRITE_BURST_STATE =>
if(FIFO_req_empty = '0') then
FIFO_req_read <= '1'; -- Keep reading the next data(The data is storaged in FIFO_req but it is not a request)
if(CONV_INTEGER(FIFO_req_ptr_r) /= FIFO_DEPTH - 1) then
FIFO_req_ptr_r <= esl_add(FIFO_req_ptr_r, "1");
else
FIFO_req_ptr_r <= (others => '0');
end if;
FIFO_req_size_temp := esl_sub(FIFO_req_size_temp, "1");
if(CONV_INTEGER(FIFO_req_address_temp) /= DEPTH - 1) then
FIFO_req_address_temp := esl_add(FIFO_req_address_temp, "1");
else
report "Burst write out of size!";
end if;
mem(CONV_INTEGER(FIFO_req_address_temp)) := FIFO_req_din(CONV_INTEGER(FIFO_req_ptr_r));
if(CONV_INTEGER(FIFO_req_size_temp) = 1) then -- The last one is done
FIFO_req_temp_state <= IDLE_STATE;
end if;
end if;
when OTHERS =>
FIFO_req_temp_state <= IDLE_STATE;
end case;
end if;
end process;
-- Generate "FIFO_req_flag"
FIFO_req_flag_proc : process
begin
wait until clk'event and clk = '1';
if(rst = '1') then
FIFO_req_flag <= '0';
else
if((bus_req_RW_en = '1' and FIFO_req_full /= '1') and CONV_INTEGER(FIFO_req_ptr_w) = FIFO_DEPTH - 1) then
FIFO_req_flag <= '1';
end if;
wait for 0.4 ns;
if((FIFO_req_read = '1' and FIFO_req_empty /= '1') and CONV_INTEGER(FIFO_req_ptr_r) = 0) then
FIFO_req_flag <= '0';
end if;
end if;
end process;
-- Generate "FIFO_rsp_flag"
FIFO_rsp_flag_proc : process
begin
wait until clk'event and clk = '1';
if(rst = '1') then
FIFO_rsp_flag <= '0';
else
if((bus_rsp_read = '1' and FIFO_rsp_empty /= '1') and CONV_INTEGER(FIFO_rsp_ptr_r) = DEPTH - 1) then
FIFO_rsp_flag <= '0';
end if;
wait for 0.4 ns;
if((FIFO_rsp_write = '1' and FIFO_rsp_full /= '1') and CONV_INTEGER(FIFO_rsp_ptr_w) = 0) then
FIFO_rsp_flag <= '1';
end if;
end if;
end process;
-- Pop data from FIFO_rsp
FIFO_rsp_ptr_r_proc : process(clk, rst)
begin
if(rst = '1') then
FIFO_rsp_ptr_r <= (others => '0');
elsif (clk'event and clk = '1') then
if(bus_rsp_read = '1' and FIFO_rsp_empty /= '1') then
if(CONV_INTEGER(FIFO_rsp_ptr_r) /= DEPTH - 1) then
FIFO_rsp_ptr_r <= esl_add(FIFO_rsp_ptr_r, "1");
else
FIFO_rsp_ptr_r <= (others => '0');
end if;
end if;
end if;
end process;
----------------------------Read file-------------------
-- Read data from file
read_file_proc : process
file fp : TEXT;
variable fstatus : FILE_OPEN_STATUS;
variable token_line : LINE;
variable token : STRING(1 to 128 );
variable token_len : INTEGER;
variable token_int : INTEGER;
variable idx : INTEGER;
--variable mem_var : arr2D;
begin
file_open(fstatus, fp, TV_IN, READ_MODE);
if(fstatus /= OPEN_OK) then
assert false report "Open file " & TV_IN & " failed!!!" severity failure;
end if;
esl_read_token(fp, token_line, token);
if(token(1 to 13) /= "[[[runtime]]]") then
report "The token is " & token;
assert false report "Illegal format of [[[runtime]]] part in " & TV_IN severity failure;
end if;
esl_read_token(fp, token_line, token);
while(token(1 to 14) /= "[[[/runtime]]]") loop
if(token(1 to 15) /= "[[transaction]]") then
report "The token is " & token;
assert false report "Illegal format of [[transaction]] part in " & TV_IN severity failure;
end if;
esl_read_token(fp, token_line, token); -- Skip transaction number
-- Start to read data for every transaction round
wait until clk'event and clk = '1';
wait for 0.2 ns;
while(ready /= '1') loop
wait until clk'event and clk = '1';
wait for 0.2 ns;
end loop;
for i in 0 to DEPTH - 1 loop
esl_read_token(fp, token_line, token);
mem(i) := esl_str2lv_hex(token, DATA_WIDTH);
end loop;
esl_read_token(fp, token_line, token);
if(token(1 to 16) /= "[[/transaction]]") then
report "The token is " & token;
assert false report "Illegal format of [[/transaction]] part in " & TV_IN severity failure;
end if;
esl_read_token(fp, token_line, token);
end loop;
file_close(fp);
wait;
end process;
----------------------------Write file-------------------
-- Write data to file
write_file_proc : process
file fp : TEXT;
variable fstatus : FILE_OPEN_STATUS;
variable token_line : LINE;
variable token : STRING(1 to 128 );
variable transaction_idx : INTEGER;
begin
wait until (rst = '0');
transaction_idx := 0;
while(true) loop
wait until clk'event and clk = '1';
while(done /= '1') loop
wait until clk'event and clk = '1';
end loop;
wait for 0.1 ns;
file_open(fstatus, fp, TV_OUT, APPEND_MODE);
if(fstatus /= OPEN_OK) then
assert false report "Open file " & TV_OUT & " failed!!!" severity failure;
end if;
write(token_line, "[[transaction]] " & integer'image(transaction_idx));
writeline(fp, token_line);
for i in 0 to DEPTH - 1 loop
write(token_line, "0x" & esl_conv_string_hex(mem(i)));
writeline(fp, token_line);
end loop;
write(token_line, string'("[[/transaction]]"));
writeline(fp, token_line);
transaction_idx := transaction_idx + 1;
file_close(fp);
end loop;
wait;
end process;
end behav;
| lgpl-3.0 | e61d234643e57d0c976bb8bd5782ef32 | 0.431629 | 3.793975 | false | false | false | false |
wsoltys/AtomFpga | src/ROM/InternalROM.vhd | 1 | 2,896 | library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
library UNISIM;
--use UNISIM.Vcomponents.all;
entity InternalROM is
port (
CLK : in std_logic;
ADDR : in std_logic_vector(16 downto 0);
DATA : out std_logic_vector(7 downto 0)
);
end;
architecture BEHAVIORAL of InternalROM is
component SDROM is
port (
CLK : in std_logic;
ADDR : in std_logic_vector(11 downto 0);
DATA : out std_logic_vector(7 downto 0));
end component;
component atombasic
port (
CLK : in std_logic;
ADDR : in std_logic_vector(11 downto 0);
DATA : out std_logic_vector(7 downto 0));
end component;
component atomfloat
port (
CLK : in std_logic;
ADDR : in std_logic_vector(11 downto 0);
DATA : out std_logic_vector(7 downto 0));
end component;
component atomkernal
port (
CLK : in std_logic;
ADDR : in std_logic_vector(11 downto 0);
DATA : out std_logic_vector(7 downto 0));
end component;
signal basic_rom_enable : std_logic;
signal kernal_rom_enable : std_logic;
signal float_rom_enable : std_logic;
signal sddos_rom_enable : std_logic;
signal kernal_data : std_logic_vector(7 downto 0);
signal basic_data : std_logic_vector(7 downto 0);
signal float_data : std_logic_vector(7 downto 0);
signal sddos_data : std_logic_vector(7 downto 0);
begin
romc000 : atombasic port map(
CLK => CLK,
ADDR => ADDR(11 downto 0),
DATA => basic_data);
romd000 : atomfloat port map(
CLK => CLK,
ADDR => ADDR(11 downto 0),
DATA => float_data);
rome000 : SDROM port map(
CLK => CLK,
ADDR => ADDR(11 downto 0),
DATA => sddos_data);
romf000 : atomkernal port map(
CLK => CLK,
ADDR => ADDR(11 downto 0),
DATA => kernal_data);
process(ADDR)
begin
-- All regions normally de-selected
sddos_rom_enable <= '0';
basic_rom_enable <= '0';
kernal_rom_enable <= '0';
float_rom_enable <= '0';
case ADDR(15 downto 12) is
when x"C" => basic_rom_enable <= '1';
when x"D" => float_rom_enable <= '1';
when x"E" => sddos_rom_enable <= '1';
when x"F" => kernal_rom_enable <= '1';
when others => null;
end case;
end process;
DATA <=
basic_data when basic_rom_enable = '1' else
float_data when float_rom_enable = '1' else
sddos_data when sddos_rom_enable = '1' else
kernal_data when kernal_rom_enable = '1' else
x"f1"; -- un-decoded locations
end BEHAVIORAL;
| apache-2.0 | 9a115246f4d2b45a6866c3ff3d19efc8 | 0.54489 | 3.510303 | false | false | false | false |
takeshineshiro/fpga_fibre_scan | HUCB2P0_150701/frontend/r2p_post.vhd | 1 | 3,419 | --
-- post.vhd
--
-- Cordic post-processing block
--
-- Compensate cordic algorithm K-factor; divide Radius by 1.6467, or multiply by 0.60725.
-- Approximation: Ra = Ri/2 + Ri/8 - Ri/64 - Ri/512
-- Radius = Ra - Ra/4096 = Ri * 0.60727. This is a 0.0034% error.
-- Implementation: Ra = (Ri/2 + Ri/8) - (Ri/64 + Ri/512)
-- Radius = Ra - Ra/4096
-- Position calculated angle in correct quadrant.
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
entity r2p_post is
port(
clk : in std_logic;
ena : in std_logic;
Ai : in signed(19 downto 0);
Ri : in unsigned(19 downto 0);
Q : in std_logic_vector(2 downto 0);
Ao : out signed(19 downto 0);
Ro : out unsigned(19 downto 0));
end entity r2p_post;
architecture dataflow of r2p_post is
begin
radius: block
signal RadA, RadB, RadC : unsigned(19 downto 0);
begin
process(clk)
begin
if (clk'event and clk = '1') then
if (ena = '1') then
RadA <= ('0' & Ri(19 downto 1)) + ("000" & Ri(19 downto 3));
RadB <= ("000000" & Ri(19 downto 6)) + ("000000000" & Ri(19 downto 9));
RadC <= RadA - RadB;
Ro <= RadC - RadC(19 downto 12);
end if;
end if;
end process;
end block radius;
angle: block
constant const_PI2 : signed(19 downto 0) := conv_signed(16#40000#, 20); -- PI / 2
constant const_PI : signed(19 downto 0) := conv_signed(16#80000#, 20); -- PI
constant const_2PI : signed(19 downto 0) := (others => '0'); -- 2PI
signal dQ : std_logic_vector(2 downto 1);
signal ddQ : std_logic;
signal AngStep1 : signed(19 downto 0);
signal AngStep2 : signed(19 downto 0);
begin
angle_step1: process(clk, Ai, Q)
variable overflow : std_logic;
variable AngA, AngB, Ang : signed(19 downto 0);
begin
-- check if angle is negative, if so set it to zero
overflow := Ai(19); --and Ai(18);
if (overflow = '1') then
AngA := (others => '0');
else
AngA := Ai;
end if;
-- step 1: Xabs and Yabs are swapped
-- Calculated angle is the angle between vector and Y-axis.
-- ActualAngle = PI/2 - CalculatedAngle
AngB := const_PI2 - AngA;
if (Q(0) = '1') then
Ang := AngB;
else
Ang := AngA;
end if;
if (clk'event and clk = '1') then
if (ena = '1') then
AngStep1 <= Ang;
dQ <= q(2 downto 1);
end if;
end if;
end process angle_step1;
angle_step2: process(clk, AngStep1, dQ)
variable AngA, AngB, Ang : signed(19 downto 0);
begin
AngA := AngStep1;
-- step 2: Xvalue is negative
-- Actual angle is in the second or third quadrant
-- ActualAngle = PI - CalculatedAngle
AngB := const_PI - AngA;
if (dQ(1) = '1') then
Ang := AngB;
else
Ang := AngA;
end if;
if (clk'event and clk = '1') then
if (ena = '1') then
AngStep2 <= Ang;
ddQ <= dQ(2);
end if;
end if;
end process angle_step2;
angle_step3: process(clk, AngStep2, ddQ)
variable AngA, AngB, Ang : signed(19 downto 0);
begin
AngA := AngStep2;
-- step 3: Yvalue is negative
-- Actual angle is in the third or fourth quadrant
-- ActualAngle = 2PI - CalculatedAngle
AngB := const_2PI - AngA;
if (ddQ = '1') then
Ang := AngB;
else
Ang := AngA;
end if;
if (clk'event and clk = '1') then
if (ena = '1') then
Ao <= Ang;
end if;
end if;
end process angle_step3;
end block angle;
end;
| apache-2.0 | e9e34be79d91f3d2aadd7af244470c4c | 0.592571 | 2.772912 | false | false | false | false |
grwlf/vsim | vhdl_ct/ct00584.vhd | 1 | 26,772 | -- NEED RESULT: ARCH00584: Attribute declarations - composite static subtypes with dynamic initial values passed
-------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
-------------------------------------------------------------------------------
--
-- TEST NAME:
--
-- CT00584
--
-- AUTHOR:
--
-- A. Wilmot
--
-- TEST OBJECTIVES:
--
-- 4.4 (1)
-- 4.4 (3)
-- 4.4 (6)
--
-- DESIGN UNIT ORDERING:
--
-- E00000(ARCH00584)
-- ENT00584_Test_Bench(ARCH00584_Test_Bench)
--
-- REVISION HISTORY:
--
-- 19-AUG-1987 - initial revision
--
-- NOTES:
--
-- self-checking
-- automatically generated
--
use WORK.STANDARD_TYPES.all ;
architecture ARCH00584 of E00000 is
procedure p2 (
constant lowb : integer := 1 ;
constant highb : integer := 10 ;
constant lowb_i2 : integer := 0 ;
constant highb_i2 : integer := 1000 ;
constant lowb_p : integer := -100 ;
constant highb_p : integer := 1000 ;
constant lowb_r : real := 0.0 ;
constant highb_r : real := 1000.0 ;
constant lowb_r2 : real := 8.0 ;
constant highb_r2 : real := 80.0
--
) is
--
-- assertion: c_xxxxx_2 >= c_xxxxx_1
-- enumeration types
-- predefined
-- boolean
constant c_boolean_1 : boolean := false ;
constant c_boolean_2 : boolean := true ;
--
type boolean_vector is array (integer range <>) of boolean ;
subtype boolean_vector_range1 is integer range lowb to highb ;
subtype st_boolean_vector is boolean_vector (boolean_vector_range1) ;
constant c_st_boolean_vector_1 : st_boolean_vector :=
(others => c_boolean_1) ;
constant c_st_boolean_vector_2 : st_boolean_vector :=
(others => c_boolean_2) ;
--
-- bit
constant c_bit_1 : bit := '0' ;
constant c_bit_2 : bit := '1' ;
--
constant c_bit_vector_1 : bit_vector := B"0000" ;
constant c_bit_vector_2 : bit_vector := B"1111" ;
subtype bit_vector_range1 is integer range lowb to highb ;
subtype st_bit_vector is bit_vector (bit_vector_range1) ;
constant c_st_bit_vector_1 : st_bit_vector :=
(others => c_bit_1) ;
constant c_st_bit_vector_2 : st_bit_vector :=
(others => c_bit_2) ;
-- severity_level
constant c_severity_level_1 : severity_level := NOTE ;
constant c_severity_level_2 : severity_level := WARNING ;
--
type severity_level_vector is array (integer range <>) of severity_level ;
subtype severity_level_vector_range1 is integer range lowb to highb ;
subtype st_severity_level_vector is
severity_level_vector (severity_level_vector_range1) ;
constant c_st_severity_level_vector_1 : st_severity_level_vector :=
(others => c_severity_level_1) ;
constant c_st_severity_level_vector_2 : st_severity_level_vector :=
(others => c_severity_level_2) ;
--
-- character
constant c_character_1 : character := 'A' ;
constant c_character_2 : character := 'a' ;
--
constant c_string_1 : string := "ABC0000" ;
constant c_string_2 : string := "ABC1111" ;
subtype string_range1 is integer range lowb to highb ;
subtype st_string is string (string_range1) ;
constant c_st_string_1 : st_string :=
(others => c_character_1) ;
constant c_st_string_2 : st_string :=
(others => c_character_2) ;
-- user defined enumeration
type t_enum1 is (en1, en2, en3, en4) ;
constant c_t_enum1_1 : t_enum1 := en1 ;
constant c_t_enum1_2 : t_enum1 := en2 ;
subtype st_enum1 is t_enum1 range en4 downto en1 ;
constant c_st_enum1_1 : st_enum1 := en1 ;
constant c_st_enum1_2 : st_enum1 := en2 ;
--
type enum1_vector is array (integer range <>) of st_enum1 ;
subtype enum1_vector_range1 is integer range lowb to highb ;
subtype st_enum1_vector is enum1_vector (enum1_vector_range1) ;
constant c_st_enum1_vector_1 : st_enum1_vector :=
(others => c_st_enum1_1) ;
constant c_st_enum1_vector_2 : st_enum1_vector :=
(others => c_st_enum1_2) ;
-- integer types
-- predefined
constant c_integer_1 : integer := lowb ;
constant c_integer_2 : integer := highb ;
--
type integer_vector is array (integer range <>) of integer ;
subtype integer_vector_range1 is integer range lowb to highb ;
subtype st_integer_vector is integer_vector (integer_vector_range1) ;
constant c_st_integer_vector_1 : st_integer_vector :=
(others => c_integer_1) ;
constant c_st_integer_vector_2 : st_integer_vector :=
(others => c_integer_2) ;
--
-- user defined integer type
type t_int1 is range 0 to 100 ;
constant c_t_int1_1 : t_int1 := 0 ;
constant c_t_int1_2 : t_int1 := 10 ;
subtype st_int1 is t_int1 range 8 to 60 ;
constant c_st_int1_1 : st_int1 := 8 ;
constant c_st_int1_2 : st_int1 := 9 ;
--
type int1_vector is array (integer range <>) of st_int1 ;
subtype int1_vector_range1 is integer range lowb to highb ;
subtype st_int1_vector is int1_vector (int1_vector_range1) ;
constant c_st_int1_vector_1 : st_int1_vector :=
(others => c_st_int1_1) ;
constant c_st_int1_vector_2 : st_int1_vector :=
(others => c_st_int1_2) ;
--
-- physical types
-- predefined
constant c_time_1 : time := 1 ns ;
constant c_time_2 : time := 2 ns ;
--
type time_vector is array (integer range <>) of time ;
subtype time_vector_range1 is integer range lowb to highb ;
subtype st_time_vector is time_vector (time_vector_range1) ;
constant c_st_time_vector_1 : st_time_vector :=
(others => c_time_1) ;
constant c_st_time_vector_2 : st_time_vector :=
(others => c_time_2) ;
--
-- user defined physical type
type t_phys1 is range -100 to 1000
units
phys1_1 ;
phys1_2 = 10 phys1_1 ;
phys1_3 = 10 phys1_2 ;
phys1_4 = 10 phys1_3 ;
phys1_5 = 10 phys1_4 ;
end units ;
--
constant c_t_phys1_1 : t_phys1 := phys1_1 ;
constant c_t_phys1_2 : t_phys1 := phys1_2 ;
subtype st_phys1 is t_phys1 range phys1_2 to phys1_4 ;
constant c_st_phys1_1 : st_phys1 := phys1_2 ;
constant c_st_phys1_2 : st_phys1 := phys1_3 ;
--
type phys1_vector is array (integer range <>) of st_phys1 ;
subtype phys1_vector_range1 is integer range lowb to highb ;
subtype st_phys1_vector is phys1_vector (phys1_vector_range1) ;
constant c_st_phys1_vector_1 : st_phys1_vector :=
(others => c_st_phys1_1) ;
constant c_st_phys1_vector_2 : st_phys1_vector :=
(others => c_st_phys1_2) ;
--
--
-- floating point types
-- predefined
constant c_real_1 : real := 0.0 ;
constant c_real_2 : real := 1.0 ;
--
type real_vector is array (integer range <>) of real ;
subtype real_vector_range1 is integer range lowb to highb ;
subtype st_real_vector is real_vector (real_vector_range1) ;
constant c_st_real_vector_1 : st_real_vector :=
(others => c_real_1) ;
constant c_st_real_vector_2 : st_real_vector :=
(others => c_real_2) ;
--
-- user defined floating type
type t_real1 is range 0.0 to 1000.0 ;
constant c_t_real1_1 : t_real1 := 0.0 ;
constant c_t_real1_2 : t_real1 := 1.0 ;
subtype st_real1 is t_real1 range 8.0 to 80.0 ;
constant c_st_real1_1 : st_real1 := 8.0 ;
constant c_st_real1_2 : st_real1 := 9.0 ;
--
type real1_vector is array (integer range <>) of st_real1 ;
subtype real1_vector_range1 is integer range lowb to highb ;
subtype st_real1_vector is real1_vector (real1_vector_range1) ;
constant c_st_real1_vector_1 : st_real1_vector :=
(others => c_st_real1_1) ;
constant c_st_real1_vector_2 : st_real1_vector :=
(others => c_st_real1_2) ;
-- composite types
--
-- simple record
type t_rec1 is record
f1 : integer range lowb_i2 to highb_i2 ;
f2 : time ;
f3 : boolean ;
f4 : real ;
end record ;
constant c_t_rec1_1 : t_rec1 :=
(c_integer_1, c_time_1, c_boolean_1, c_real_1) ;
constant c_t_rec1_2 : t_rec1 :=
(c_integer_2, c_time_2, c_boolean_2, c_real_2) ;
subtype st_rec1 is t_rec1 ;
constant c_st_rec1_1 : st_rec1 := c_t_rec1_1 ;
constant c_st_rec1_2 : st_rec1 := c_t_rec1_2 ;
--
type rec1_vector is array (integer range <>) of st_rec1 ;
subtype rec1_vector_range1 is integer range lowb to highb ;
subtype st_rec1_vector is rec1_vector (rec1_vector_range1) ;
constant c_st_rec1_vector_1 : st_rec1_vector :=
(others => c_st_rec1_1) ;
constant c_st_rec1_vector_2 : st_rec1_vector :=
(others => c_st_rec1_2) ;
--
--
-- more complex record
type t_rec2 is record
f1 : boolean ;
f2 : st_rec1 ;
f3 : time ;
end record ;
constant c_t_rec2_1 : t_rec2 :=
(c_boolean_1, c_st_rec1_1, c_time_1) ;
constant c_t_rec2_2 : t_rec2 :=
(c_boolean_2, c_st_rec1_2, c_time_2) ;
subtype st_rec2 is t_rec2 ;
constant c_st_rec2_1 : st_rec2 := c_t_rec2_1 ;
constant c_st_rec2_2 : st_rec2 := c_t_rec2_2 ;
--
type rec2_vector is array (integer range <>) of st_rec2 ;
subtype rec2_vector_range1 is integer range lowb to highb ;
subtype st_rec2_vector is rec2_vector (rec2_vector_range1) ;
constant c_st_rec2_vector_1 : st_rec2_vector :=
(others => c_st_rec2_1) ;
constant c_st_rec2_vector_2 : st_rec2_vector :=
(others => c_st_rec2_2) ;
--
-- simple array
type t_arr1 is array (integer range <>) of st_int1 ;
subtype t_arr1_range1 is integer range lowb to highb ;
subtype st_arr1 is t_arr1 (t_arr1_range1) ;
constant c_st_arr1_1 : st_arr1 := (others => c_st_int1_1) ;
constant c_st_arr1_2 : st_arr1 := (others => c_st_int1_2) ;
constant c_t_arr1_1 : st_arr1 := c_st_arr1_1 ;
constant c_t_arr1_2 : st_arr1 := c_st_arr1_2 ;
--
type arr1_vector is array (integer range <>) of st_arr1 ;
subtype arr1_vector_range1 is integer range lowb to highb ;
subtype st_arr1_vector is arr1_vector (arr1_vector_range1) ;
constant c_st_arr1_vector_1 : st_arr1_vector :=
(others => c_st_arr1_1) ;
constant c_st_arr1_vector_2 : st_arr1_vector :=
(others => c_st_arr1_2) ;
-- more complex array
type t_arr2 is array (integer range <>, boolean range <>) of st_arr1 ;
subtype t_arr2_range1 is integer range lowb to highb ;
subtype t_arr2_range2 is boolean range false to true ;
subtype st_arr2 is t_arr2 (t_arr2_range1, t_arr2_range2);
constant c_st_arr2_1 : st_arr2 := (others => (others => c_st_arr1_1)) ;
constant c_st_arr2_2 : st_arr2 := (others => (others => c_st_arr1_2)) ;
constant c_t_arr2_1 : st_arr2 := c_st_arr2_1 ;
constant c_t_arr2_2 : st_arr2 := c_st_arr2_2 ;
--
type arr2_vector is array (integer range <>) of st_arr2 ;
subtype arr2_vector_range1 is integer range lowb to highb ;
subtype st_arr2_vector is arr2_vector (arr2_vector_range1) ;
constant c_st_arr2_vector_1 : st_arr2_vector :=
(others => c_st_arr2_1) ;
constant c_st_arr2_vector_2 : st_arr2_vector :=
(others => c_st_arr2_2) ;
--
--
-- most complex record
type t_rec3 is record
f1 : boolean ;
f2 : st_rec2 ;
f3 : st_arr2 ;
end record ;
constant c_t_rec3_1 : t_rec3 :=
(c_boolean_1, c_st_rec2_1, c_st_arr2_1) ;
constant c_t_rec3_2 : t_rec3 :=
(c_boolean_2, c_st_rec2_2, c_st_arr2_2) ;
subtype st_rec3 is t_rec3 ;
constant c_st_rec3_1 : st_rec3 := c_t_rec3_1 ;
constant c_st_rec3_2 : st_rec3 := c_t_rec3_2 ;
--
type rec3_vector is array (integer range <>) of st_rec3 ;
subtype rec3_vector_range1 is integer range lowb to highb ;
subtype st_rec3_vector is rec3_vector (rec3_vector_range1) ;
constant c_st_rec3_vector_1 : st_rec3_vector :=
(others => c_st_rec3_1) ;
constant c_st_rec3_vector_2 : st_rec3_vector :=
(others => c_st_rec3_2) ;
--
-- most complex array
type t_arr3 is array (integer range <>, boolean range <>) of st_rec3 ;
subtype t_arr3_range1 is integer range lowb to highb ;
subtype t_arr3_range2 is boolean range true downto false ;
subtype st_arr3 is t_arr3 (t_arr3_range1, t_arr3_range2) ;
constant c_st_arr3_1 : st_arr3 := (others => (others => c_st_rec3_1)) ;
constant c_st_arr3_2 : st_arr3 := (others => (others => c_st_rec3_2)) ;
constant c_t_arr3_1 : st_arr3 := c_st_arr3_1 ;
constant c_t_arr3_2 : st_arr3 := c_st_arr3_2 ;
--
type arr3_vector is array (integer range <>) of st_arr3 ;
subtype arr3_vector_range1 is integer range lowb to highb ;
subtype st_arr3_vector is arr3_vector (arr3_vector_range1) ;
constant c_st_arr3_vector_1 : st_arr3_vector :=
(others => c_st_arr3_1) ;
constant c_st_arr3_vector_2 : st_arr3_vector :=
(others => c_st_arr3_2) ;
--
-- enumeration types
-- predefined
-- boolean
function bf_boolean(to_resolve : boolean_vector) return boolean is
variable sum : integer := 0 ;
begin
if to_resolve'length = 0 then
return boolean'left ;
else
for i in to_resolve'range loop
sum := sum + boolean'pos(to_resolve(i)) ;
end loop ;
return boolean'val(integer'pos(sum) mod
(boolean'pos(boolean'high) + 1)) ;
end if ;
end bf_boolean ;
--
--
-- bit
function bf_bit(to_resolve : bit_vector) return bit is
variable sum : integer := 0 ;
begin
if to_resolve'length = 0 then
return bit'left ;
else
for i in to_resolve'range loop
sum := sum + bit'pos(to_resolve(i)) ;
end loop ;
return bit'val(integer'pos(sum) mod
(bit'pos(bit'high) + 1)) ;
end if ;
end bf_bit ;
--
-- severity_level
function bf_severity_level(to_resolve : severity_level_vector)
return severity_level is
variable sum : integer := 0 ;
begin
if to_resolve'length = 0 then
return severity_level'left ;
else
for i in to_resolve'range loop
sum := sum + severity_level'pos(to_resolve(i)) ;
end loop ;
return severity_level'val(integer'pos(sum) mod
(severity_level'pos(severity_level'high) + 1)) ;
end if ;
end bf_severity_level ;
--
-- character
function bf_character(to_resolve : string) return character is
variable sum : integer := 0 ;
begin
if to_resolve'length = 0 then
return character'left ;
else
for i in to_resolve'range loop
sum := sum + character'pos(to_resolve(i)) ;
end loop ;
return character'val(integer'pos(sum) mod
(character'pos(character'high) + 1)) ;
end if ;
end bf_character ;
--
--
-- user defined enumeration
function bf_enum1(to_resolve : enum1_vector) return st_enum1 is
variable sum : integer := 0 ;
begin
if to_resolve'length = 0 then
return st_enum1'left ;
else
for i in to_resolve'range loop
sum := sum + t_enum1'pos(to_resolve(i)) ;
end loop ;
return t_enum1'val(integer'pos(sum) mod
(t_enum1'pos(t_enum1'high) + 1)) ;
end if ;
end bf_enum1 ;
--
--
-- integer types
-- predefined
function bf_integer(to_resolve : integer_vector) return integer is
variable sum : integer := 0 ;
begin
if to_resolve'length = 0 then
return integer'left ;
else
for i in to_resolve'range loop
sum := sum + integer'pos(to_resolve(i)) ;
end loop ;
return sum ;
end if ;
end bf_integer ;
--
--
-- user defined integer type
function bf_int1(to_resolve : int1_vector) return st_int1 is
variable sum : integer := 0 ;
begin
if to_resolve'length = 0 then
return st_int1'left ;
else
for i in to_resolve'range loop
sum := sum + t_int1'pos(to_resolve(i)) ;
end loop ;
return t_int1'val(integer'pos(sum) mod
(t_int1'pos(t_int1'high) + 1)) ;
end if ;
end bf_int1 ;
--
--
-- physical types
-- predefined
function bf_time(to_resolve : time_vector) return time is
variable sum : time := 0 fs;
begin
if to_resolve'length = 0 then
return time'left ;
else
for i in to_resolve'range loop
sum := sum + to_resolve(i) ;
end loop ;
return sum ;
end if ;
end bf_time ;
--
--
-- user defined physical type
function bf_phys1(to_resolve : phys1_vector) return st_phys1 is
variable sum : integer := 0 ;
begin
if to_resolve'length = 0 then
return c_st_phys1_1 ;
else
for i in to_resolve'range loop
sum := sum + t_phys1'pos(to_resolve(i)) ;
end loop ;
return t_phys1'val(integer'pos(sum) mod
(t_phys1'pos(t_phys1'high) + 1)) ;
end if ;
end bf_phys1 ;
--
--
-- floating point types
-- predefined
function bf_real(to_resolve : real_vector) return real is
variable sum : real := 0.0 ;
begin
if to_resolve'length = 0 then
return real'left ;
else
for i in to_resolve'range loop
sum := sum + to_resolve(i) ;
end loop ;
return sum ;
end if ;
end bf_real ;
--
--
-- user defined floating type
function bf_real1(to_resolve : real1_vector) return st_real1 is
variable sum : t_real1 := 0.0 ;
begin
if to_resolve'length = 0 then
return c_st_real1_1 ;
else
for i in to_resolve'range loop
sum := sum + to_resolve(i) ;
end loop ;
return sum ;
end if ;
end bf_real1 ;
--
--
-- composite types
--
-- simple record
function bf_rec1(to_resolve : rec1_vector) return st_rec1 is
variable f1array : integer_vector (to_resolve'range) ;
variable f2array : time_vector (to_resolve'range) ;
variable f3array : boolean_vector (to_resolve'range) ;
variable f4array : real_vector (to_resolve'range) ;
variable result : st_rec1 ;
begin
if to_resolve'length = 0 then
return c_st_rec1_1 ;
else
for i in to_resolve'range loop
f1array(i) := to_resolve(i).f1 ;
f2array(i) := to_resolve(i).f2 ;
f3array(i) := to_resolve(i).f3 ;
f4array(i) := to_resolve(i).f4 ;
end loop ;
result.f1 := bf_integer(f1array) ;
result.f2 := bf_time(f2array) ;
result.f3 := bf_boolean(f3array) ;
result.f4 := bf_real(f4array) ;
return result ;
end if ;
end bf_rec1 ;
--
--
-- more complex record
function bf_rec2(to_resolve : rec2_vector) return st_rec2 is
variable f1array : boolean_vector (to_resolve'range) ;
variable f2array : rec1_vector (to_resolve'range) ;
variable f3array : time_vector (to_resolve'range) ;
variable result : st_rec2 ;
begin
if to_resolve'length = 0 then
return c_st_rec2_1 ;
else
for i in to_resolve'range loop
f1array(i) := to_resolve(i).f1 ;
f2array(i) := to_resolve(i).f2 ;
f3array(i) := to_resolve(i).f3 ;
end loop ;
result.f1 := bf_boolean(f1array) ;
result.f2 := bf_rec1(f2array) ;
result.f3 := bf_time(f3array) ;
return result ;
end if ;
end bf_rec2 ;
--
--
-- simple array
function bf_arr1(to_resolve : arr1_vector) return st_arr1 is
variable temp : int1_vector (to_resolve'range) ;
variable result : st_arr1 ;
begin
if to_resolve'length = 0 then
return c_st_arr1_1 ;
else
for i in st_arr1'range loop
for j in to_resolve'range(1) loop
temp(j) := to_resolve(j)(i) ;
end loop;
result(i) := bf_int1(temp) ;
end loop ;
return result ;
end if ;
end bf_arr1 ;
--
--
-- more complex array
function bf_arr2(to_resolve : arr2_vector) return st_arr2 is
variable temp : arr1_vector (to_resolve'range) ;
variable result : st_arr2 ;
begin
if to_resolve'length = 0 then
return c_st_arr2_1 ;
else
for i in st_arr2'range(1) loop
for j in st_arr2'range(2) loop
for k in to_resolve'range loop
temp(k) := to_resolve(k)(i,j) ;
end loop ;
result(i, j) := bf_arr1(temp) ;
end loop ;
end loop ;
return result ;
end if ;
end bf_arr2 ;
--
--
-- most complex record
function bf_rec3(to_resolve : rec3_vector) return st_rec3 is
variable f1array : boolean_vector (to_resolve'range) ;
variable f2array : rec2_vector (to_resolve'range) ;
variable f3array : arr2_vector (to_resolve'range) ;
variable result : st_rec3 ;
begin
if to_resolve'length = 0 then
return c_st_rec3_1 ;
else
for i in to_resolve'range loop
f1array(i) := to_resolve(i).f1 ;
f2array(i) := to_resolve(i).f2 ;
f3array(i) := to_resolve(i).f3 ;
end loop ;
result.f1 := bf_boolean(f1array) ;
result.f2 := bf_rec2(f2array) ;
result.f3 := bf_arr2(f3array) ;
return result ;
end if ;
end bf_rec3 ;
--
--
-- most complex array
function bf_arr3(to_resolve : arr3_vector) return st_arr3 is
variable temp : rec3_vector (to_resolve'range) ;
variable result : st_arr3 ;
begin
if to_resolve'length = 0 then
return c_st_arr3_1 ;
else
for i in st_arr3'range(1) loop
for j in st_arr3'range(2) loop
for k in to_resolve'range loop
temp(k) := to_resolve(k)(i,j) ;
end loop ;
result(i, j) := bf_rec3(temp) ;
end loop ;
end loop ;
return result ;
end if ;
end bf_arr3 ;
--
attribute at_bit_vector_1 : bit_vector ;
attribute at_string_1 : string ;
attribute at_t_rec1_1 : t_rec1 ;
attribute at_st_rec1_1 : st_rec1 ;
attribute at_t_rec2_1 : t_rec2 ;
attribute at_st_rec2_1 : st_rec2 ;
attribute at_t_rec3_1 : t_rec3 ;
attribute at_st_rec3_1 : st_rec3 ;
attribute at_t_arr1_1 : t_arr1 ;
attribute at_st_arr1_1 : st_arr1 ;
attribute at_t_arr2_1 : t_arr2 ;
attribute at_st_arr2_1 : st_arr2 ;
attribute at_t_arr3_1 : t_arr3 ;
attribute at_st_arr3_1 : st_arr3 ;
procedure p1 ;
attribute at_bit_vector_1 of p1 : procedure is
c_st_bit_vector_1 ;
attribute at_string_1 of p1 : procedure is
c_st_string_1 ;
attribute at_t_rec1_1 of p1 : procedure is
c_st_rec1_1 ;
attribute at_st_rec1_1 of p1 : procedure is
c_st_rec1_1 ;
attribute at_t_rec2_1 of p1 : procedure is
c_st_rec2_1 ;
attribute at_st_rec2_1 of p1 : procedure is
c_st_rec2_1 ;
attribute at_t_rec3_1 of p1 : procedure is
c_st_rec3_1 ;
attribute at_st_rec3_1 of p1 : procedure is
c_st_rec3_1 ;
attribute at_t_arr1_1 of p1 : procedure is
c_st_arr1_1 ;
attribute at_st_arr1_1 of p1 : procedure is
c_st_arr1_1 ;
attribute at_t_arr2_1 of p1 : procedure is
c_st_arr2_1 ;
attribute at_st_arr2_1 of p1 : procedure is
c_st_arr2_1 ;
attribute at_t_arr3_1 of p1 : procedure is
c_st_arr3_1 ;
attribute at_st_arr3_1 of p1 : procedure is
c_st_arr3_1 ;
procedure p1 is
variable correct : boolean := true ;
begin
correct := correct and p1'at_bit_vector_1
= c_st_bit_vector_1 ;
correct := correct and p1'at_string_1
= c_st_string_1 ;
correct := correct and p1'at_t_rec1_1
= c_st_rec1_1 ;
correct := correct and p1'at_st_rec1_1
= c_st_rec1_1 ;
correct := correct and p1'at_t_rec2_1
= c_st_rec2_1 ;
correct := correct and p1'at_st_rec2_1
= c_st_rec2_1 ;
correct := correct and p1'at_t_rec3_1
= c_st_rec3_1 ;
correct := correct and p1'at_st_rec3_1
= c_st_rec3_1 ;
correct := correct and p1'at_t_arr1_1
= c_st_arr1_1 ;
correct := correct and p1'at_st_arr1_1
= c_st_arr1_1 ;
correct := correct and p1'at_t_arr2_1
= c_st_arr2_1 ;
correct := correct and p1'at_st_arr2_1
= c_st_arr2_1 ;
correct := correct and p1'at_t_arr3_1
= c_st_arr3_1 ;
correct := correct and p1'at_st_arr3_1
= c_st_arr3_1 ;
test_report ( "ARCH00584" ,
"Attribute declarations - composite static subtypes"
& " with dynamic initial values" ,
correct) ;
end p1 ;
begin
p1 ;
end p2 ;
begin
process
begin
p2 ;
wait ;
end process ;
end ARCH00584 ;
--
entity ENT00584_Test_Bench is
end ENT00584_Test_Bench ;
--
architecture ARCH00584_Test_Bench of ENT00584_Test_Bench is
begin
L1:
block
component UUT
end component ;
for CIS1 : UUT use entity WORK.E00000 ( ARCH00584 ) ;
begin
CIS1 : UUT ;
end block L1 ;
end ARCH00584_Test_Bench ;
| gpl-3.0 | d237282cd5767eb2d9adfcff05fac6d2 | 0.545383 | 3.192844 | false | false | false | false |
jairov4/accel-oil | solution_virtex5_plb/impl/pcores/nfa_accept_samples_generic_hw_top_v1_01_a/synhdl/vhdl/nfa_initials_buckets_if.vhd | 2 | 27,940 | -- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2014.1
-- Copyright (C) 2014 Xilinx Inc. All rights reserved.
--
-- ==============================================================
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity nfa_initials_buckets_if is
generic
(
C_PLB_AWIDTH : integer := 32;
C_PLB_DWIDTH : integer := 64;
PLB_ADDR_SHIFT : integer := 3;
USER_DATA_WIDTH : integer := 32;
USER_DATA_WIDTH_2N : integer := 32;
USER_ADDR_SHIFT : integer := 2; -- log2(byte_count_of_data_width)
REMOTE_DESTINATION_ADDRESS : std_logic_vector(0 to 31):= X"00000000"
);
port
(
-- Bus protocol ports, do not add to or delete
MPLB_Clk : in std_logic;
MPLB_Rst : in std_logic;
M_request : out std_logic;
M_priority : out std_logic_vector(0 to 1);
M_busLock : out std_logic;
M_RNW : out std_logic;
M_BE : out std_logic_vector(0 to C_PLB_DWIDTH/8-1);
M_MSize : out std_logic_vector(0 to 1);
M_size : out std_logic_vector(0 to 3);
M_type : out std_logic_vector(0 to 2);
M_TAttribute : out std_logic_vector(0 to 15);
M_lockErr : out std_logic;
M_abort : out std_logic;
M_ABus : out std_logic_vector(0 to C_PLB_AWIDTH-1);
M_UABus : out std_logic_vector(0 to 31);
M_wrDBus : out std_logic_vector(0 to C_PLB_DWIDTH-1);
M_wrBurst : out std_logic;
M_rdBurst : out std_logic;
PLB_MAddrAck : in std_logic;
PLB_MSSize : in std_logic_vector(0 to 1);
PLB_MRearbitrate : in std_logic;
PLB_MTimeout : in std_logic;
PLB_MBusy : in std_logic;
PLB_MRdErr : in std_logic;
PLB_MWrErr : in std_logic;
PLB_MIRQ : in std_logic;
PLB_MRdDBus : in std_logic_vector(0 to (C_PLB_DWIDTH-1));
PLB_MRdWdAddr : in std_logic_vector(0 to 3);
PLB_MRdDAck : in std_logic;
PLB_MRdBTerm : in std_logic;
PLB_MWrDAck : in std_logic;
PLB_MWrBTerm : in std_logic;
-- signals from user logic
USER_RdData : out std_logic_vector(USER_DATA_WIDTH - 1 downto 0); -- Bus read return data to user_logic
USER_WrData : in std_logic_vector(USER_DATA_WIDTH - 1 downto 0); -- Bus write data
USER_address : in std_logic_vector(31 downto 0); -- word offset from BASE_ADDRESS
USER_size : in std_logic_vector(31 downto 0); -- burst size of word
USER_req_nRW : in std_logic; -- req type 0: Read, 1: write
USER_req_full_n : out std_logic; -- req Fifo full
USER_req_push : in std_logic; -- req Fifo push (new request in)
USER_rsp_empty_n : out std_logic; -- return data FIFO empty
USER_rsp_pop : in std_logic -- return data FIFO pop
);
attribute SIGIS : string;
attribute SIGIS of MPLB_Clk : signal is "Clk";
attribute SIGIS of MPLB_Rst : signal is "Rst";
end entity;
------------------------------------------------------------------------------
-- Architecture section
------------------------------------------------------------------------------
architecture IMP of nfa_initials_buckets_if is
component nfa_initials_buckets_if_ap_fifo is
generic (
DATA_WIDTH : integer := 32;
ADDR_WIDTH : integer := 4;
DEPTH : integer := 16);
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
if_empty_n : OUT STD_LOGIC;
if_read : IN STD_LOGIC;
if_dout : OUT STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0);
if_full_n : OUT STD_LOGIC;
if_write : IN STD_LOGIC;
if_din : IN STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0) );
end component;
component nfa_initials_buckets_if_plb_master_if is
generic (
C_PLB_AWIDTH : integer := 32;
C_PLB_DWIDTH : integer := 64;
PLB_ADDR_SHIFT : integer := 3);
port (
-- Bus protocol ports, do not add to or delete
PLB_Clk : in std_logic;
PLB_Rst : in std_logic;
M_abort : out std_logic;
M_ABus : out std_logic_vector(0 to C_PLB_AWIDTH-1);
M_BE : out std_logic_vector(0 to C_PLB_DWIDTH/8-1);
M_busLock : out std_logic;
M_lockErr : out std_logic;
M_MSize : out std_logic_vector(0 to 1);
M_priority : out std_logic_vector(0 to 1);
M_rdBurst : out std_logic;
M_request : out std_logic;
M_RNW : out std_logic;
M_size : out std_logic_vector(0 to 3);
M_type : out std_logic_vector(0 to 2);
M_wrBurst : out std_logic;
M_wrDBus : out std_logic_vector(0 to C_PLB_DWIDTH-1);
PLB_MBusy : in std_logic;
PLB_MWrBTerm : in std_logic;
PLB_MWrDAck : in std_logic;
PLB_MAddrAck : in std_logic;
PLB_MRdBTerm : in std_logic;
PLB_MRdDAck : in std_logic;
PLB_MRdDBus : in std_logic_vector(0 to (C_PLB_DWIDTH-1));
PLB_MRdWdAddr : in std_logic_vector(0 to 3);
PLB_MRearbitrate : in std_logic;
PLB_MSSize : in std_logic_vector(0 to 1);
-- signals from user logic
BUS_RdData : out std_logic_vector(C_PLB_DWIDTH-1 downto 0); -- Bus read return data to user_logic
BUS_WrData : in std_logic_vector(C_PLB_DWIDTH-1 downto 0); -- Bus write data
BUS_address : in std_logic_vector(31 downto 0); -- word offset from BASE_ADDRESS
BUS_size : in std_logic_vector(31 downto 0); -- burst size of word
BUS_req_nRW : in std_logic; -- req type 0: Read, 1: write
BUS_req_BE : in std_logic_vector(C_PLB_DWIDTH/8 -1 downto 0); -- Bus write data byte enable
BUS_req_full_n : out std_logic; -- req Fifo full
BUS_req_push : in std_logic; -- req Fifo push (new request in)
BUS_rsp_nRW : out std_logic; -- return data FIFO rsp type
BUS_rsp_empty_n : out std_logic; -- return data FIFO empty
BUS_rsp_pop : in std_logic -- return data FIFO pop
);
end component;
-- type state_type is (IDLE, );
-- signal cs, ns : st_type;
constant PLB_BW : integer := C_PLB_DWIDTH;
constant PLB_BYTE_COUNT : integer := C_PLB_DWIDTH/8;
constant USER_DATA_BYTE_COUNT : integer := USER_DATA_WIDTH_2N/8;
constant REQ_FIFO_DATA_WIDTH : integer := 1 + 32 + 32 + USER_DATA_WIDTH_2N; -- nRW + addr + size + wr_data
constant REQ_FIFO_ADDR_WIDTH : integer := 5;
constant REQ_FIFO_DEPTH : integer := 32;
constant ALIGN_DATA_WIDTH : integer := USER_DATA_WIDTH_2N + PLB_BW;
constant ALIGN_DATA_BE_WIDTH : integer := (USER_DATA_WIDTH_2N + PLB_BW)/8;
signal user_phy_address : STD_LOGIC_VECTOR(31 downto 0);
-- request FIFO
signal req_fifo_empty_n : STD_LOGIC;
signal req_fifo_pop : STD_LOGIC;
signal req_fifo_dout : STD_LOGIC_VECTOR(REQ_FIFO_DATA_WIDTH - 1 downto 0);
signal req_fifo_full_n : STD_LOGIC;
signal req_fifo_push : STD_LOGIC;
signal req_fifo_din : STD_LOGIC_VECTOR(REQ_FIFO_DATA_WIDTH - 1 downto 0);
signal user_WrData_2N : STD_LOGIC_VECTOR(USER_DATA_WIDTH_2N-1 downto 0);
signal req_fifo_dout_req_nRW : STD_LOGIC;
signal req_fifo_dout_req_address : STD_LOGIC_VECTOR(31 downto 0);
signal req_fifo_dout_req_size, req_fifo_dout_req_size_normalize : STD_LOGIC_VECTOR(31 downto 0);
-- internal request information
signal req_nRW : STD_LOGIC;
signal req_address : STD_LOGIC_VECTOR(31 downto 0);
signal req_size, burst_size : STD_LOGIC_VECTOR(31 downto 0);
signal req_size_user : STD_LOGIC_VECTOR(31 downto 0);
signal req_BE : STD_LOGIC_VECTOR(PLB_BYTE_COUNT-1 downto 0);
signal req_WrData : STD_LOGIC_VECTOR(ALIGN_DATA_WIDTH -1 downto 0);
signal req_WrData_BE : STD_LOGIC_VECTOR(ALIGN_DATA_BE_WIDTH -1 downto 0);
signal req_WrData_byte_p : STD_LOGIC_VECTOR(PLB_ADDR_SHIFT-1 downto 0);
signal req_valid, req_SOP, req_EOP_user, req_EOP : STD_LOGIC;
signal req_burst_write_counter : STD_LOGIC_VECTOR(31 downto 0);
signal req_burst_mode, req_last_burst: STD_LOGIC;
-- interface to PLB_master_if module
signal PLB_master_if_req_full_n : STD_LOGIC;
signal PLB_master_if_req_push : STD_LOGIC;
signal PLB_master_if_dataout : STD_LOGIC_VECTOR(PLB_BW-1 downto 0);
signal PLB_master_if_rsp_nRW : STD_LOGIC;
signal PLB_master_if_rsp_empty_n : STD_LOGIC;
signal PLB_master_if_rsp_pop : STD_LOGIC;
signal USER_size_local: STD_LOGIC_VECTOR(31 downto 0);
-- rsp FIFO
constant RSP_FIFO_DATA_WIDTH : integer := PLB_ADDR_SHIFT + 32; -- addr + size
constant RSP_FIFO_ADDR_WIDTH : integer := 6;
constant RSP_FIFO_DEPTH : integer := 64;
signal rsp_fifo_empty_n : STD_LOGIC;
signal rsp_fifo_pop : STD_LOGIC;
signal rsp_fifo_dout : STD_LOGIC_VECTOR(RSP_FIFO_DATA_WIDTH -1 downto 0);
signal rsp_fifo_full_n : STD_LOGIC;
signal rsp_fifo_push : STD_LOGIC;
signal rsp_fifo_din : STD_LOGIC_VECTOR(RSP_FIFO_DATA_WIDTH -1 downto 0);
signal rsp_valid, rsp_SOP : STD_LOGIC;
signal rsp_addr : STD_LOGIC_VECTOR(PLB_ADDR_SHIFT-1 downto 0);
signal rsp_size : STD_LOGIC_VECTOR(31 downto 0);
signal rsp_rd_data : STD_LOGIC_VECTOR(ALIGN_DATA_WIDTH -1 downto 0);
signal rsp_rd_data_byte_count : STD_LOGIC_VECTOR(4 downto 0);
-- rd data user FIFO
signal rd_data_user_fifo_empty_n : STD_LOGIC;
signal rd_data_user_fifo_pop : STD_LOGIC;
signal rd_data_user_fifo_dout : STD_LOGIC_VECTOR(USER_DATA_WIDTH -1 downto 0);
signal rd_data_user_fifo_full_n : STD_LOGIC;
signal rd_data_user_fifo_push : STD_LOGIC;
signal rd_data_user_fifo_din : STD_LOGIC_VECTOR(USER_DATA_WIDTH -1 downto 0);
signal rd_data_user_fifo_din_2N : STD_LOGIC_VECTOR(USER_DATA_WIDTH_2N -1 downto 0);
signal BE_ALL_ONE : STD_LOGIC_VECTOR(PLB_BYTE_COUNT -1 downto 0);
begin
BE_ALL_ONE <= (others => '1');
M_UABus <= (others => '0');
M_TAttribute <= (others => '0');
-- interface to user logic
user_phy_address(31 downto USER_ADDR_SHIFT) <= REMOTE_DESTINATION_ADDRESS(0 to C_PLB_AWIDTH - USER_ADDR_SHIFT -1) + USER_address(31 -USER_ADDR_SHIFT downto 0);
user_phy_address(USER_ADDR_SHIFT-1 downto 0) <= REMOTE_DESTINATION_ADDRESS(C_PLB_AWIDTH - USER_ADDR_SHIFT to C_PLB_AWIDTH -1);
USER_size_local <= X"00000001" when conv_integer(USER_size(31 downto 1)) = 0 else USER_size;
USER_req_full_n <= req_fifo_full_n;
process(USER_WrData)
variable i: integer;
begin
user_WrData_2N <= (others=> '0');
for i in 0 to USER_WrData'length -1 loop
user_WrData_2N (USER_DATA_WIDTH_2N-1 -i) <= USER_WrData(i);
end loop;
end process;
req_fifo_din(REQ_FIFO_DATA_WIDTH-1) <= USER_req_nRW;
req_fifo_din(REQ_FIFO_DATA_WIDTH-1-1 downto REQ_FIFO_DATA_WIDTH -1-32) <= user_phy_address;
req_fifo_din(REQ_FIFO_DATA_WIDTH-1-32-1 downto REQ_FIFO_DATA_WIDTH -1-32-32) <= USER_size_local;
req_fifo_din(USER_DATA_WIDTH_2N -1 downto 0) <= user_WrData_2N(USER_DATA_WIDTH_2N-1 downto 0);
req_fifo_push <= USER_req_push;
U_nfa_initials_buckets_if_req_fifo: component nfa_initials_buckets_if_ap_fifo
generic map(
DATA_WIDTH => REQ_FIFO_DATA_WIDTH,
ADDR_WIDTH => REQ_FIFO_ADDR_WIDTH,
DEPTH => REQ_FIFO_DEPTH)
port map(
clk => MPLB_Clk,
reset => MPLB_Rst,
if_empty_n => req_fifo_empty_n,
if_read => req_fifo_pop,
if_dout => req_fifo_dout,
if_full_n => req_fifo_full_n,
if_write => req_fifo_push,
if_din => req_fifo_din
);
req_fifo_dout_req_nRW <= req_fifo_dout(REQ_FIFO_DATA_WIDTH -1);
req_fifo_dout_req_size <= req_fifo_dout(REQ_FIFO_DATA_WIDTH-1-32-1 downto REQ_FIFO_DATA_WIDTH -1-32-32);
req_fifo_dout_req_address <= req_fifo_dout(REQ_FIFO_DATA_WIDTH-1-1 downto REQ_FIFO_DATA_WIDTH -1-32);
req_fifo_dout_req_size_normalize(31 downto USER_ADDR_SHIFT) <= req_fifo_dout_req_size(31-USER_ADDR_SHIFT downto 0);
req_fifo_dout_req_size_normalize(USER_ADDR_SHIFT-1 downto 0) <= (others => '0');
process(req_fifo_empty_n, req_valid)
begin
req_fifo_pop <= '0';
if (req_fifo_empty_n = '1' and req_valid = '0') then -- lunch next request
req_fifo_pop <= '1';
end if;
end process;
process (MPLB_Clk, MPLB_Rst)
variable offset: integer;
begin
if (MPLB_Rst = '1') then
req_nRW <= '0';
burst_size <= (others => '0');
req_size_user <= (others => '0');
req_address <= (others => '0');
req_WrData <= (others => '0'); -- set possible MSB to ZERO
req_WrData_BE <= (others => '0'); -- set possible MSB to ZERO
req_WrData_byte_p <= (others => '0'); -- set possible MSB to ZERO
req_valid <= '0';
req_EOP <= '0';
req_burst_write_counter <= (others => '0');
req_burst_mode <= '0';
elsif (MPLB_Clk'event and MPLB_Clk = '1') then
if (req_fifo_pop = '1') then -- lunch next request
req_valid <= '1';
if (req_burst_mode = '0') then
if (req_fifo_dout_req_nRW = '0') then
if (req_fifo_dout_req_size_normalize(PLB_ADDR_SHIFT-1 downto 0) = CONV_STD_LOGIC_VECTOR(0,PLB_ADDR_SHIFT) and
req_fifo_dout_req_address(PLB_ADDR_SHIFT-1 downto 0) = CONV_STD_LOGIC_VECTOR(0,PLB_ADDR_SHIFT)) then
burst_size(31-PLB_ADDR_SHIFT downto 0) <= req_fifo_dout_req_size_normalize(31 downto PLB_ADDR_SHIFT);
elsif (('0'&req_fifo_dout_req_size_normalize(PLB_ADDR_SHIFT-1 downto 0)) +
('0'&req_fifo_dout_req_address(PLB_ADDR_SHIFT-1 downto 0)) <= PLB_BYTE_COUNT) then
burst_size(31-PLB_ADDR_SHIFT downto 0) <= req_fifo_dout_req_size_normalize(31 downto PLB_ADDR_SHIFT) + 1;
else
burst_size(31-PLB_ADDR_SHIFT downto 0) <= req_fifo_dout_req_size_normalize(31 downto PLB_ADDR_SHIFT) + 2;
end if;
else
burst_size <= X"00000001"; -- single by default
if (req_fifo_dout_req_size_normalize(31 downto PLB_ADDR_SHIFT+1) /= CONV_STD_LOGIC_VECTOR(0,31-PLB_ADDR_SHIFT)) then -- may burst
burst_size(31 downto 32-PLB_ADDR_SHIFT) <= (others=>'0'); -- burst_size for write operation
if (req_fifo_dout_req_address(PLB_ADDR_SHIFT-1 downto 0) = CONV_STD_LOGIC_VECTOR(0, PLB_ADDR_SHIFT)) or
(conv_integer(req_fifo_dout_req_address(PLB_ADDR_SHIFT-1 downto 0)) + conv_integer(req_fifo_dout_req_size_normalize(PLB_ADDR_SHIFT-1 downto 0)) >= PLB_BYTE_COUNT) then
burst_size(31-PLB_ADDR_SHIFT downto 0) <= req_fifo_dout_req_size_normalize(31 downto PLB_ADDR_SHIFT);
else
burst_size(31-PLB_ADDR_SHIFT downto 0) <= req_fifo_dout_req_size_normalize(31 downto PLB_ADDR_SHIFT)-1;
end if;
end if;
end if;
offset := conv_integer(req_fifo_dout_req_address(PLB_ADDR_SHIFT-1 downto 0));
if (req_fifo_dout_req_nRW = '1') then
req_WrData(USER_DATA_WIDTH_2N +offset*8 -1 downto offset*8) <= req_fifo_dout(USER_DATA_WIDTH_2N -1 downto 0);
req_WrData_BE(USER_DATA_BYTE_COUNT+offset-1 downto offset) <= (others => '1');
end if;
req_size_user <= req_fifo_dout_req_size; -- for read operation
req_nRW <= req_fifo_dout_req_nRW;
req_EOP <= '1';
req_address <= req_fifo_dout_req_address;
req_burst_write_counter <= req_fifo_dout_req_size;
req_WrData_byte_p <= req_fifo_dout_req_address(PLB_ADDR_SHIFT-1 downto 0) + USER_DATA_BYTE_COUNT;
if (req_fifo_dout_req_nRW = '1' and req_fifo_dout_req_size(31 downto 1) /= "0000000000000000000000000000000") then
req_burst_mode <= '1';
req_EOP <= '0';
end if;
else -- in a burst write process
req_burst_write_counter <= req_burst_write_counter -1;
offset := conv_integer(req_WrData_byte_p);
req_WrData(USER_DATA_WIDTH_2N +offset*8 -1 downto offset*8) <= req_fifo_dout(USER_DATA_WIDTH_2N -1 downto 0);
req_WrData_BE(USER_DATA_BYTE_COUNT+offset-1 downto offset) <= (others => '1');
req_WrData_byte_p <= req_WrData_byte_p + USER_DATA_BYTE_COUNT;
if (req_last_burst = '1') then
req_burst_mode <= '0';
req_EOP <= '1';
end if;
end if;
elsif (req_valid = '1') then
if (req_nRW = '0' and PLB_master_if_req_push = '1') then
req_valid <= '0';
elsif (req_nRW = '1') then
if (req_EOP = '1' and PLB_master_if_req_push = '1') then -- last burst request
if (req_WrData_BE(ALIGN_DATA_BE_WIDTH-1 downto PLB_BYTE_COUNT) = CONV_STD_LOGIC_VECTOR(0, ALIGN_DATA_BE_WIDTH-PLB_BYTE_COUNT)) then
req_valid <= '0';
req_EOP <= '0';
req_WrData <= (others=>'0');
req_WrData_BE <= (others => '0');
else
req_WrData(USER_DATA_WIDTH_2N + PLB_BW -1 downto USER_DATA_WIDTH_2N) <= (others => '0');
req_WrData(USER_DATA_WIDTH_2N -1 downto 0) <= req_WrData(USER_DATA_WIDTH_2N +PLB_BW -1 downto PLB_BW);
req_WrData_BE(ALIGN_DATA_BE_WIDTH -1 downto ALIGN_DATA_BE_WIDTH-PLB_BYTE_COUNT) <= (others => '0');
req_WrData_BE(ALIGN_DATA_BE_WIDTH -PLB_BYTE_COUNT-1 downto 0) <= req_WrData_BE(ALIGN_DATA_BE_WIDTH -1 downto PLB_BYTE_COUNT);
req_address(31 downto PLB_ADDR_SHIFT) <= req_address(31 downto PLB_ADDR_SHIFT) +1;
req_address(PLB_ADDR_SHIFT-1 downto 0) <= (others=>'0');
end if;
elsif (req_EOP = '0') then
if (req_WrData_BE(PLB_BYTE_COUNT-1) = '0') then
req_valid <= '0';
elsif (req_WrData_BE(PLB_BYTE_COUNT-1) = '1' and PLB_master_if_req_push = '1') then
req_WrData(USER_DATA_WIDTH_2N + PLB_BW -1 downto USER_DATA_WIDTH_2N) <= (others => '0');
req_WrData(USER_DATA_WIDTH_2N -1 downto 0) <= req_WrData(USER_DATA_WIDTH_2N +PLB_BW -1 downto PLB_BW);
req_WrData_BE(ALIGN_DATA_BE_WIDTH -1 downto ALIGN_DATA_BE_WIDTH-PLB_BYTE_COUNT) <= (others => '0');
req_WrData_BE(ALIGN_DATA_BE_WIDTH-PLB_BYTE_COUNT-1 downto 0) <= req_WrData_BE(ALIGN_DATA_BE_WIDTH -1 downto PLB_BYTE_COUNT);
req_address(31 downto PLB_ADDR_SHIFT) <= req_address(31 downto PLB_ADDR_SHIFT) +1;
req_address(PLB_ADDR_SHIFT-1 downto 0) <= (others=>'0');
end if;
end if;
end if;
end if;
end if;
end process;
req_last_burst <= '1' when (req_burst_mode = '1' and req_burst_write_counter(31 downto 0) = X"00000002") else '0';
process(req_nRW, req_WrData_BE, burst_size)
begin
req_size <= (others => '0');
if (req_nRW = '0') then
req_size <= burst_size;
elsif (req_WrData_BE(PLB_BYTE_COUNT-1 downto 0) = BE_ALL_ONE) then
req_size <= burst_size;
else
req_size <= X"00000001";
end if;
end process;
process(req_valid, PLB_master_if_req_full_n, req_nRW, req_WrData_BE)
begin
PLB_master_if_req_push <= '0';
if (req_valid = '1' and PLB_master_if_req_full_n = '1') then
if (req_nRW = '0') then
PLB_master_if_req_push <= '1'; -- only push when the last byte been push
elsif (req_WrData_BE(PLB_BYTE_COUNT-1) = '1' or (req_EOP = '1' and req_WrData_BE(PLB_BYTE_COUNT-1 downto 0) /= CONV_STD_LOGIC_VECTOR(0, PLB_BYTE_COUNT))) then
PLB_master_if_req_push <= '1'; -- only push when the last byte been push
end if;
end if;
end process;
req_BE <= req_WrData_BE(PLB_BYTE_COUNT-1 downto 0) when req_nRW = '1' else (others => '1');
U_nfa_initials_buckets_if_plb_master_if: component nfa_initials_buckets_if_plb_master_if
generic map(
C_PLB_AWIDTH => C_PLB_AWIDTH,
C_PLB_DWIDTH => C_PLB_DWIDTH,
PLB_ADDR_SHIFT => PLB_ADDR_SHIFT)
port map (
-- Bus protocol ports, do not add to or delete
PLB_Clk => MPLB_Clk,
PLB_Rst => MPLB_Rst,
M_abort => M_abort,
M_ABus => M_ABus,
M_BE => M_BE,
M_busLock => M_busLock,
M_lockErr => M_lockErr,
M_MSize => M_MSize,
M_priority => M_priority,
M_rdBurst => M_rdBurst,
M_request => M_request,
M_RNW => M_RNW,
M_size => M_size,
M_type => M_type,
M_wrBurst => M_wrBurst,
M_wrDBus => M_wrDBus,
PLB_MBusy => PLB_MBusy,
PLB_MWrBTerm => PLB_MWrBTerm,
PLB_MWrDAck => PLB_MWrDAck,
PLB_MAddrAck => PLB_MAddrAck,
PLB_MRdBTerm => PLB_MRdBTerm,
PLB_MRdDAck => PLB_MRdDAck,
PLB_MRdDBus => PLB_MRdDBus,
PLB_MRdWdAddr => PLB_MRdWdAddr,
PLB_MRearbitrate => PLB_MRearbitrate,
PLB_MSSize => PLB_MSSize,
-- signals from user logic
BUS_RdData => PLB_master_if_dataout,
BUS_WrData => req_WrData(PLB_BW-1 downto 0),
BUS_address => req_address,
BUS_size => req_size,
BUS_req_nRW => req_nRW,
BUS_req_BE => req_BE,
BUS_req_full_n => PLB_master_if_req_full_n,
BUS_req_push => PLB_master_if_req_push,
BUS_rsp_nRW => PLB_master_if_rsp_nRW,
BUS_rsp_empty_n => PLB_master_if_rsp_empty_n,
BUS_rsp_pop => PLB_master_if_rsp_pop
);
-- below is the response (bus read data) part
U_nfa_initials_buckets_if_rsp_fifo: component nfa_initials_buckets_if_ap_fifo
generic map(
DATA_WIDTH => RSP_FIFO_DATA_WIDTH,
ADDR_WIDTH => RSP_FIFO_ADDR_WIDTH,
DEPTH => RSP_FIFO_DEPTH)
port map(
clk => MPLB_Clk,
reset => MPLB_Rst,
if_empty_n => rsp_fifo_empty_n,
if_read => rsp_fifo_pop,
if_dout => rsp_fifo_dout,
if_full_n => rsp_fifo_full_n,
if_write => rsp_fifo_push,
if_din => rsp_fifo_din
);
rsp_fifo_din(32+PLB_ADDR_SHIFT-1 downto 32) <= req_address(PLB_ADDR_SHIFT-1 downto 0);
rsp_fifo_din(31 downto 0) <= req_size_user;
rsp_fifo_push <= PLB_master_if_req_push and (not req_nRW);
process (rsp_valid, PLB_master_if_rsp_empty_n, rsp_rd_data_byte_count)
begin
PLB_master_if_rsp_pop <= '0';
-- fetch data to rsp_rd_data until enough bytes
if (rsp_valid = '1' and PLB_master_if_rsp_empty_n = '1' and CONV_INTEGER(rsp_rd_data_byte_count) < USER_DATA_BYTE_COUNT) then
PLB_master_if_rsp_pop <= '1';
end if;
end process;
process (MPLB_Clk, MPLB_Rst)
begin
if (MPLB_Rst = '1') then
rsp_valid <= '0';
rsp_addr <= (others=> '0');
rsp_size <= (others=> '0');
rsp_SOP <= '1';
rsp_rd_data_byte_count <= (others => '0');
rsp_rd_data <= (others=>'0');
rsp_fifo_pop <= '0';
elsif (MPLB_Clk'event and MPLB_Clk = '1') then
rsp_fifo_pop <= '0';
if (rsp_valid = '0' and rsp_fifo_empty_n = '1') then
rsp_valid <= '1';
rsp_addr <= rsp_fifo_dout(32+PLB_ADDR_SHIFT-1 downto 32);
rsp_size <= rsp_fifo_dout(31 downto 0);
rsp_fifo_pop <= '1';
rsp_rd_data_byte_count <= (others=>'0');
rsp_SOP <= '1';
end if;
-- fetch data to rsp_rd_data until enough bytes
if (PLB_master_if_rsp_pop = '1') then
rsp_rd_data(USER_DATA_WIDTH_2N-1 downto 0) <= rsp_rd_data(USER_DATA_WIDTH_2N + PLB_BW -1 downto PLB_BW);
rsp_rd_data(USER_DATA_WIDTH_2N +PLB_BW -1 downto USER_DATA_WIDTH_2N) <= PLB_master_if_dataout;
if (rsp_SOP = '1') then
rsp_rd_data_byte_count <= rsp_rd_data_byte_count + PLB_BYTE_COUNT - rsp_addr;
rsp_SOP <= '0';
else
rsp_rd_data_byte_count <= rsp_rd_data_byte_count + PLB_BYTE_COUNT;
end if;
end if;
-- write one unit of data to USER LOGIC
if (rd_data_user_fifo_push = '1') then
rsp_size <= rsp_size -1;
rsp_rd_data_byte_count <= rsp_rd_data_byte_count - USER_DATA_BYTE_COUNT;
rsp_addr <= rsp_addr + USER_DATA_BYTE_COUNT;
if (rsp_size = X"00000001") then
rsp_valid <= '0';
end if;
end if;
end if;
end process;
process(rsp_addr, rsp_rd_data,rsp_valid, rd_data_user_fifo_full_n, rsp_rd_data_byte_count, rd_data_user_fifo_din_2N)
variable i: integer;
begin
case CONV_INTEGER(rsp_addr) is
when 0 => rd_data_user_fifo_din_2N <= rsp_rd_data(USER_DATA_WIDTH_2N +32 -1 downto 32);
when 1 => rd_data_user_fifo_din_2N <= rsp_rd_data(USER_DATA_WIDTH_2N +40 -1 downto 40);
when 2 => rd_data_user_fifo_din_2N <= rsp_rd_data(USER_DATA_WIDTH_2N +48 -1 downto 48);
when 3 => rd_data_user_fifo_din_2N <= rsp_rd_data(USER_DATA_WIDTH_2N +56 -1 downto 56);
when 4 => rd_data_user_fifo_din_2N <= rsp_rd_data(USER_DATA_WIDTH_2N +64 -1 downto 64);
when 5 => rd_data_user_fifo_din_2N <= rsp_rd_data(USER_DATA_WIDTH_2N +8 -1 downto 8);
when 6 => rd_data_user_fifo_din_2N <= rsp_rd_data(USER_DATA_WIDTH_2N +16 -1 downto 16);
when 7 => rd_data_user_fifo_din_2N <= rsp_rd_data(USER_DATA_WIDTH_2N +24 -1 downto 24);
when others => null;
end case;
for i in 0 to USER_DATA_WIDTH -1 loop
rd_data_user_fifo_din(i) <= rd_data_user_fifo_din_2N(USER_DATA_WIDTH_2N-1-i);
end loop;
rd_data_user_fifo_push <= '0';
if (rsp_valid = '1' and rd_data_user_fifo_full_n = '1' and
CONV_INTEGER(rsp_rd_data_byte_count)>= USER_DATA_BYTE_COUNT) then
rd_data_user_fifo_push <= '1';
end if;
end process;
U_nfa_initials_buckets_if_rd_data_user_fifo: component nfa_initials_buckets_if_ap_fifo
generic map(
DATA_WIDTH => USER_DATA_WIDTH,
ADDR_WIDTH => 5,
DEPTH => 32)
port map(
clk => MPLB_Clk,
reset => MPLB_Rst,
if_empty_n => rd_data_user_fifo_empty_n,
if_read => USER_rsp_pop,
if_dout => rd_data_user_fifo_dout,
if_full_n => rd_data_user_fifo_full_n,
if_write => rd_data_user_fifo_push,
if_din => rd_data_user_fifo_din
);
USER_RdData <= rd_data_user_fifo_dout;
USER_rsp_empty_n <= rd_data_user_fifo_empty_n;
end IMP;
| lgpl-3.0 | aee93c2db4dbd9330c49f73662dd00a4 | 0.552362 | 3.259069 | false | false | false | false |
grwlf/vsim | vhdl_ct/ct00182.vhd | 1 | 42,226 | -- NEED RESULT: ARCH00182.P1: Multi inertial transactions occurred on signal asg with slice name prefixed by a selected name on LHS passed
-- NEED RESULT: ARCH00182.P2: Multi inertial transactions occurred on signal asg with slice name prefixed by a selected name on LHS passed
-- NEED RESULT: ARCH00182.P3: Multi inertial transactions occurred on signal asg with slice name prefixed by a selected name on LHS passed
-- NEED RESULT: ARCH00182.P4: Multi inertial transactions occurred on signal asg with slice name prefixed by a selected name on LHS passed
-- NEED RESULT: ARCH00182.P5: Multi inertial transactions occurred on signal asg with slice name prefixed by a selected name on LHS passed
-- NEED RESULT: ARCH00182.P6: Multi inertial transactions occurred on signal asg with slice name prefixed by a selected name on LHS passed
-- NEED RESULT: ARCH00182: One inertial transaction occurred on signal asg with slice name prefixed by an selected name on LHS passed
-- NEED RESULT: ARCH00182: One inertial transaction occurred on signal asg with slice name prefixed by an selected name on LHS passed
-- NEED RESULT: ARCH00182: One inertial transaction occurred on signal asg with slice name prefixed by an selected name on LHS passed
-- NEED RESULT: ARCH00182: One inertial transaction occurred on signal asg with slice name prefixed by an selected name on LHS passed
-- NEED RESULT: ARCH00182: One inertial transaction occurred on signal asg with slice name prefixed by an selected name on LHS passed
-- NEED RESULT: ARCH00182: One inertial transaction occurred on signal asg with slice name prefixed by an selected name on LHS passed
-- NEED RESULT: P6: Inertial transactions entirely completed failed
-- NEED RESULT: P5: Inertial transactions entirely completed failed
-- NEED RESULT: P4: Inertial transactions entirely completed failed
-- NEED RESULT: P3: Inertial transactions entirely completed failed
-- NEED RESULT: P2: Inertial transactions entirely completed failed
-- NEED RESULT: P1: Inertial transactions entirely completed failed
-------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
-------------------------------------------------------------------------------
--
-- TEST NAME:
--
-- CT00182
--
-- AUTHOR:
--
-- G. Tominovich
--
-- TEST OBJECTIVES:
--
-- 8.3 (1)
-- 8.3 (2)
-- 8.3 (4)
-- 8.3 (5)
-- 8.3.1 (4)
--
-- DESIGN UNIT ORDERING:
--
-- PKG00182
-- PKG00182/BODY
-- ENT00182(ARCH00182)
-- ENT00182_Test_Bench(ARCH00182_Test_Bench)
--
-- REVISION HISTORY:
--
-- 08-JUL-1987 - initial revision
--
-- NOTES:
--
-- self-checking
-- automatically generated
--
use WORK.STANDARD_TYPES.all ;
package PKG00182 is
type r_st_arr1_vector is record
f1 : integer ;
f2 : st_arr1_vector ;
end record ;
function c_r_st_arr1_vector_1 return r_st_arr1_vector ;
-- (c_integer_1, c_st_arr1_vector_1) ;
function c_r_st_arr1_vector_2 return r_st_arr1_vector ;
-- (c_integer_2, c_st_arr1_vector_2) ;
--
type r_st_arr2_vector is record
f1 : integer ;
f2 : st_arr2_vector ;
end record ;
function c_r_st_arr2_vector_1 return r_st_arr2_vector ;
-- (c_integer_1, c_st_arr2_vector_1) ;
function c_r_st_arr2_vector_2 return r_st_arr2_vector ;
-- (c_integer_2, c_st_arr2_vector_2) ;
--
type r_st_arr3_vector is record
f1 : integer ;
f2 : st_arr3_vector ;
end record ;
function c_r_st_arr3_vector_1 return r_st_arr3_vector ;
-- (c_integer_1, c_st_arr3_vector_1) ;
function c_r_st_arr3_vector_2 return r_st_arr3_vector ;
-- (c_integer_2, c_st_arr3_vector_2) ;
--
type r_st_rec1_vector is record
f1 : integer ;
f2 : st_rec1_vector ;
end record ;
function c_r_st_rec1_vector_1 return r_st_rec1_vector ;
-- (c_integer_1, c_st_rec1_vector_1) ;
function c_r_st_rec1_vector_2 return r_st_rec1_vector ;
-- (c_integer_2, c_st_rec1_vector_2) ;
--
type r_st_rec2_vector is record
f1 : integer ;
f2 : st_rec2_vector ;
end record ;
function c_r_st_rec2_vector_1 return r_st_rec2_vector ;
-- (c_integer_1, c_st_rec2_vector_1) ;
function c_r_st_rec2_vector_2 return r_st_rec2_vector ;
-- (c_integer_2, c_st_rec2_vector_2) ;
--
type r_st_rec3_vector is record
f1 : integer ;
f2 : st_rec3_vector ;
end record ;
function c_r_st_rec3_vector_1 return r_st_rec3_vector ;
-- (c_integer_1, c_st_rec3_vector_1) ;
function c_r_st_rec3_vector_2 return r_st_rec3_vector ;
-- (c_integer_2, c_st_rec3_vector_2) ;
--
--
end PKG00182 ;
--
package body PKG00182 is
function c_r_st_arr1_vector_1 return r_st_arr1_vector
is begin
return (c_integer_1, c_st_arr1_vector_1) ;
end c_r_st_arr1_vector_1 ;
--
function c_r_st_arr1_vector_2 return r_st_arr1_vector
is begin
return (c_integer_2, c_st_arr1_vector_2) ;
end c_r_st_arr1_vector_2 ;
--
--
function c_r_st_arr2_vector_1 return r_st_arr2_vector
is begin
return (c_integer_1, c_st_arr2_vector_1) ;
end c_r_st_arr2_vector_1 ;
--
function c_r_st_arr2_vector_2 return r_st_arr2_vector
is begin
return (c_integer_2, c_st_arr2_vector_2) ;
end c_r_st_arr2_vector_2 ;
--
--
function c_r_st_arr3_vector_1 return r_st_arr3_vector
is begin
return (c_integer_1, c_st_arr3_vector_1) ;
end c_r_st_arr3_vector_1 ;
--
function c_r_st_arr3_vector_2 return r_st_arr3_vector
is begin
return (c_integer_2, c_st_arr3_vector_2) ;
end c_r_st_arr3_vector_2 ;
--
--
function c_r_st_rec1_vector_1 return r_st_rec1_vector
is begin
return (c_integer_1, c_st_rec1_vector_1) ;
end c_r_st_rec1_vector_1 ;
--
function c_r_st_rec1_vector_2 return r_st_rec1_vector
is begin
return (c_integer_2, c_st_rec1_vector_2) ;
end c_r_st_rec1_vector_2 ;
--
--
function c_r_st_rec2_vector_1 return r_st_rec2_vector
is begin
return (c_integer_1, c_st_rec2_vector_1) ;
end c_r_st_rec2_vector_1 ;
--
function c_r_st_rec2_vector_2 return r_st_rec2_vector
is begin
return (c_integer_2, c_st_rec2_vector_2) ;
end c_r_st_rec2_vector_2 ;
--
--
function c_r_st_rec3_vector_1 return r_st_rec3_vector
is begin
return (c_integer_1, c_st_rec3_vector_1) ;
end c_r_st_rec3_vector_1 ;
--
function c_r_st_rec3_vector_2 return r_st_rec3_vector
is begin
return (c_integer_2, c_st_rec3_vector_2) ;
end c_r_st_rec3_vector_2 ;
--
--
--
end PKG00182 ;
--
use WORK.STANDARD_TYPES.all ;
use WORK.PKG00182.all ;
entity ENT00182 is
port (
s_r_st_arr1_vector : inout r_st_arr1_vector
; s_r_st_arr2_vector : inout r_st_arr2_vector
; s_r_st_arr3_vector : inout r_st_arr3_vector
; s_r_st_rec1_vector : inout r_st_rec1_vector
; s_r_st_rec2_vector : inout r_st_rec2_vector
; s_r_st_rec3_vector : inout r_st_rec3_vector
) ;
subtype chk_sig_type is integer range -1 to 100 ;
signal chk_r_st_arr1_vector : chk_sig_type := -1 ;
signal chk_r_st_arr2_vector : chk_sig_type := -1 ;
signal chk_r_st_arr3_vector : chk_sig_type := -1 ;
signal chk_r_st_rec1_vector : chk_sig_type := -1 ;
signal chk_r_st_rec2_vector : chk_sig_type := -1 ;
signal chk_r_st_rec3_vector : chk_sig_type := -1 ;
--
end ENT00182 ;
--
architecture ARCH00182 of ENT00182 is
begin
P1 :
process
variable correct : boolean ;
variable counter : integer := 0 ;
variable savtime : time ;
begin
case counter is
when 0
=> s_r_st_arr1_vector.f2 (lowb+1 to highb-1) <=
c_r_st_arr1_vector_2.f2
(lowb+1 to highb-1) after 10 ns,
c_r_st_arr1_vector_1.f2
(lowb+1 to highb-1) after 20 ns ;
--
when 1
=> correct :=
s_r_st_arr1_vector.f2 (lowb+1 to highb-1) =
c_r_st_arr1_vector_2.f2 (lowb+1 to highb-1) and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_r_st_arr1_vector.f2 (lowb+1 to highb-1) =
c_r_st_arr1_vector_1.f2 (lowb+1 to highb-1) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00182.P1" ,
"Multi inertial transactions occurred on signal " &
"asg with slice name prefixed by a selected name on LHS",
correct ) ;
s_r_st_arr1_vector.f2 (lowb+1 to highb-1) <=
c_r_st_arr1_vector_2.f2
(lowb+1 to highb-1) after 10 ns ,
c_r_st_arr1_vector_1.f2
(lowb+1 to highb-1) after 20 ns ,
c_r_st_arr1_vector_2.f2
(lowb+1 to highb-1) after 30 ns ,
c_r_st_arr1_vector_1.f2
(lowb+1 to highb-1) after 40 ns ;
--
when 3
=> correct :=
s_r_st_arr1_vector.f2 (lowb+1 to highb-1) =
c_r_st_arr1_vector_2.f2 (lowb+1 to highb-1) and
(savtime + 10 ns) = Std.Standard.Now ;
s_r_st_arr1_vector.f2 (lowb+1 to highb-1) <=
c_r_st_arr1_vector_1.f2
(lowb+1 to highb-1) after 5 ns ;
--
when 4
=> correct :=
correct and
s_r_st_arr1_vector.f2 (lowb+1 to highb-1) =
c_r_st_arr1_vector_1.f2 (lowb+1 to highb-1) and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00182" ,
"One inertial transaction occurred on signal " &
"asg with slice name prefixed by an selected name on LHS",
correct ) ;
s_r_st_arr1_vector.f2 (lowb+1 to highb-1) <= transport
c_r_st_arr1_vector_1.f2
(lowb+1 to highb-1) after 100 ns ;
--
when 5
=> correct :=
s_r_st_arr1_vector.f2 (lowb+1 to highb-1) =
c_r_st_arr1_vector_1.f2 (lowb+1 to highb-1) and
(savtime + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00182" ,
"Old transactions were removed on signal " &
"asg with slice name prefixed by an selected name on LHS",
correct ) ;
s_r_st_arr1_vector.f2 (lowb+1 to highb-1) <=
c_r_st_arr1_vector_2.f2
(lowb+1 to highb-1) after 10 ns ,
c_r_st_arr1_vector_1.f2
(lowb+1 to highb-1) after 20 ns ,
c_r_st_arr1_vector_2.f2
(lowb+1 to highb-1) after 30 ns ,
c_r_st_arr1_vector_1.f2
(lowb+1 to highb-1) after 40 ns ;
--
when 6
=> correct :=
s_r_st_arr1_vector.f2 (lowb+1 to highb-1) =
c_r_st_arr1_vector_2.f2 (lowb+1 to highb-1) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00182" ,
"One inertial transaction occurred on signal " &
"asg with slice name prefixed by an selected name on LHS",
correct ) ;
-- Last transaction above is marked
s_r_st_arr1_vector.f2 (lowb+1 to highb-1) <=
c_r_st_arr1_vector_1.f2
(lowb+1 to highb-1) after 40 ns ;
--
when 7
=> correct :=
s_r_st_arr1_vector.f2 (lowb+1 to highb-1) =
c_r_st_arr1_vector_1.f2 (lowb+1 to highb-1) and
(savtime + 30 ns) = Std.Standard.Now ;
--
when 8
=> correct := correct and
s_r_st_arr1_vector.f2 (lowb+1 to highb-1) =
c_r_st_arr1_vector_1.f2 (lowb+1 to highb-1) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00182" ,
"Inertial semantics check on a signal " &
"asg with slice name prefixed by an selected name on LHS",
correct ) ;
--
when others
=>
test_report ( "ARCH00182" ,
"Inertial semantics check on a signal " &
"asg with slice name prefixed by an selected name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_r_st_arr1_vector <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
wait until (not s_r_st_arr1_vector'Quiet) and
(savtime /= Std.Standard.Now) ;
--
end process P1 ;
--
PGEN_CHKP_1 :
process ( chk_r_st_arr1_vector )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P1" ,
"Inertial transactions entirely completed",
chk_r_st_arr1_vector = 8 ) ;
end if ;
end process PGEN_CHKP_1 ;
--
--
P2 :
process
variable correct : boolean ;
variable counter : integer := 0 ;
variable savtime : time ;
begin
case counter is
when 0
=> s_r_st_arr2_vector.f2 (lowb+1 to highb-1) <=
c_r_st_arr2_vector_2.f2
(lowb+1 to highb-1) after 10 ns,
c_r_st_arr2_vector_1.f2
(lowb+1 to highb-1) after 20 ns ;
--
when 1
=> correct :=
s_r_st_arr2_vector.f2 (lowb+1 to highb-1) =
c_r_st_arr2_vector_2.f2 (lowb+1 to highb-1) and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_r_st_arr2_vector.f2 (lowb+1 to highb-1) =
c_r_st_arr2_vector_1.f2 (lowb+1 to highb-1) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00182.P2" ,
"Multi inertial transactions occurred on signal " &
"asg with slice name prefixed by a selected name on LHS",
correct ) ;
s_r_st_arr2_vector.f2 (lowb+1 to highb-1) <=
c_r_st_arr2_vector_2.f2
(lowb+1 to highb-1) after 10 ns ,
c_r_st_arr2_vector_1.f2
(lowb+1 to highb-1) after 20 ns ,
c_r_st_arr2_vector_2.f2
(lowb+1 to highb-1) after 30 ns ,
c_r_st_arr2_vector_1.f2
(lowb+1 to highb-1) after 40 ns ;
--
when 3
=> correct :=
s_r_st_arr2_vector.f2 (lowb+1 to highb-1) =
c_r_st_arr2_vector_2.f2 (lowb+1 to highb-1) and
(savtime + 10 ns) = Std.Standard.Now ;
s_r_st_arr2_vector.f2 (lowb+1 to highb-1) <=
c_r_st_arr2_vector_1.f2
(lowb+1 to highb-1) after 5 ns ;
--
when 4
=> correct :=
correct and
s_r_st_arr2_vector.f2 (lowb+1 to highb-1) =
c_r_st_arr2_vector_1.f2 (lowb+1 to highb-1) and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00182" ,
"One inertial transaction occurred on signal " &
"asg with slice name prefixed by an selected name on LHS",
correct ) ;
s_r_st_arr2_vector.f2 (lowb+1 to highb-1) <= transport
c_r_st_arr2_vector_1.f2
(lowb+1 to highb-1) after 100 ns ;
--
when 5
=> correct :=
s_r_st_arr2_vector.f2 (lowb+1 to highb-1) =
c_r_st_arr2_vector_1.f2 (lowb+1 to highb-1) and
(savtime + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00182" ,
"Old transactions were removed on signal " &
"asg with slice name prefixed by an selected name on LHS",
correct ) ;
s_r_st_arr2_vector.f2 (lowb+1 to highb-1) <=
c_r_st_arr2_vector_2.f2
(lowb+1 to highb-1) after 10 ns ,
c_r_st_arr2_vector_1.f2
(lowb+1 to highb-1) after 20 ns ,
c_r_st_arr2_vector_2.f2
(lowb+1 to highb-1) after 30 ns ,
c_r_st_arr2_vector_1.f2
(lowb+1 to highb-1) after 40 ns ;
--
when 6
=> correct :=
s_r_st_arr2_vector.f2 (lowb+1 to highb-1) =
c_r_st_arr2_vector_2.f2 (lowb+1 to highb-1) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00182" ,
"One inertial transaction occurred on signal " &
"asg with slice name prefixed by an selected name on LHS",
correct ) ;
-- Last transaction above is marked
s_r_st_arr2_vector.f2 (lowb+1 to highb-1) <=
c_r_st_arr2_vector_1.f2
(lowb+1 to highb-1) after 40 ns ;
--
when 7
=> correct :=
s_r_st_arr2_vector.f2 (lowb+1 to highb-1) =
c_r_st_arr2_vector_1.f2 (lowb+1 to highb-1) and
(savtime + 30 ns) = Std.Standard.Now ;
--
when 8
=> correct := correct and
s_r_st_arr2_vector.f2 (lowb+1 to highb-1) =
c_r_st_arr2_vector_1.f2 (lowb+1 to highb-1) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00182" ,
"Inertial semantics check on a signal " &
"asg with slice name prefixed by an selected name on LHS",
correct ) ;
--
when others
=>
test_report ( "ARCH00182" ,
"Inertial semantics check on a signal " &
"asg with slice name prefixed by an selected name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_r_st_arr2_vector <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
wait until (not s_r_st_arr2_vector'Quiet) and
(savtime /= Std.Standard.Now) ;
--
end process P2 ;
--
PGEN_CHKP_2 :
process ( chk_r_st_arr2_vector )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P2" ,
"Inertial transactions entirely completed",
chk_r_st_arr2_vector = 8 ) ;
end if ;
end process PGEN_CHKP_2 ;
--
--
P3 :
process
variable correct : boolean ;
variable counter : integer := 0 ;
variable savtime : time ;
begin
case counter is
when 0
=> s_r_st_arr3_vector.f2 (lowb+1 to highb-1) <=
c_r_st_arr3_vector_2.f2
(lowb+1 to highb-1) after 10 ns,
c_r_st_arr3_vector_1.f2
(lowb+1 to highb-1) after 20 ns ;
--
when 1
=> correct :=
s_r_st_arr3_vector.f2 (lowb+1 to highb-1) =
c_r_st_arr3_vector_2.f2 (lowb+1 to highb-1) and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_r_st_arr3_vector.f2 (lowb+1 to highb-1) =
c_r_st_arr3_vector_1.f2 (lowb+1 to highb-1) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00182.P3" ,
"Multi inertial transactions occurred on signal " &
"asg with slice name prefixed by a selected name on LHS",
correct ) ;
s_r_st_arr3_vector.f2 (lowb+1 to highb-1) <=
c_r_st_arr3_vector_2.f2
(lowb+1 to highb-1) after 10 ns ,
c_r_st_arr3_vector_1.f2
(lowb+1 to highb-1) after 20 ns ,
c_r_st_arr3_vector_2.f2
(lowb+1 to highb-1) after 30 ns ,
c_r_st_arr3_vector_1.f2
(lowb+1 to highb-1) after 40 ns ;
--
when 3
=> correct :=
s_r_st_arr3_vector.f2 (lowb+1 to highb-1) =
c_r_st_arr3_vector_2.f2 (lowb+1 to highb-1) and
(savtime + 10 ns) = Std.Standard.Now ;
s_r_st_arr3_vector.f2 (lowb+1 to highb-1) <=
c_r_st_arr3_vector_1.f2
(lowb+1 to highb-1) after 5 ns ;
--
when 4
=> correct :=
correct and
s_r_st_arr3_vector.f2 (lowb+1 to highb-1) =
c_r_st_arr3_vector_1.f2 (lowb+1 to highb-1) and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00182" ,
"One inertial transaction occurred on signal " &
"asg with slice name prefixed by an selected name on LHS",
correct ) ;
s_r_st_arr3_vector.f2 (lowb+1 to highb-1) <= transport
c_r_st_arr3_vector_1.f2
(lowb+1 to highb-1) after 100 ns ;
--
when 5
=> correct :=
s_r_st_arr3_vector.f2 (lowb+1 to highb-1) =
c_r_st_arr3_vector_1.f2 (lowb+1 to highb-1) and
(savtime + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00182" ,
"Old transactions were removed on signal " &
"asg with slice name prefixed by an selected name on LHS",
correct ) ;
s_r_st_arr3_vector.f2 (lowb+1 to highb-1) <=
c_r_st_arr3_vector_2.f2
(lowb+1 to highb-1) after 10 ns ,
c_r_st_arr3_vector_1.f2
(lowb+1 to highb-1) after 20 ns ,
c_r_st_arr3_vector_2.f2
(lowb+1 to highb-1) after 30 ns ,
c_r_st_arr3_vector_1.f2
(lowb+1 to highb-1) after 40 ns ;
--
when 6
=> correct :=
s_r_st_arr3_vector.f2 (lowb+1 to highb-1) =
c_r_st_arr3_vector_2.f2 (lowb+1 to highb-1) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00182" ,
"One inertial transaction occurred on signal " &
"asg with slice name prefixed by an selected name on LHS",
correct ) ;
-- Last transaction above is marked
s_r_st_arr3_vector.f2 (lowb+1 to highb-1) <=
c_r_st_arr3_vector_1.f2
(lowb+1 to highb-1) after 40 ns ;
--
when 7
=> correct :=
s_r_st_arr3_vector.f2 (lowb+1 to highb-1) =
c_r_st_arr3_vector_1.f2 (lowb+1 to highb-1) and
(savtime + 30 ns) = Std.Standard.Now ;
--
when 8
=> correct := correct and
s_r_st_arr3_vector.f2 (lowb+1 to highb-1) =
c_r_st_arr3_vector_1.f2 (lowb+1 to highb-1) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00182" ,
"Inertial semantics check on a signal " &
"asg with slice name prefixed by an selected name on LHS",
correct ) ;
--
when others
=>
test_report ( "ARCH00182" ,
"Inertial semantics check on a signal " &
"asg with slice name prefixed by an selected name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_r_st_arr3_vector <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
wait until (not s_r_st_arr3_vector'Quiet) and
(savtime /= Std.Standard.Now) ;
--
end process P3 ;
--
PGEN_CHKP_3 :
process ( chk_r_st_arr3_vector )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P3" ,
"Inertial transactions entirely completed",
chk_r_st_arr3_vector = 8 ) ;
end if ;
end process PGEN_CHKP_3 ;
--
--
P4 :
process
variable correct : boolean ;
variable counter : integer := 0 ;
variable savtime : time ;
begin
case counter is
when 0
=> s_r_st_rec1_vector.f2 (lowb+1 to highb-1) <=
c_r_st_rec1_vector_2.f2
(lowb+1 to highb-1) after 10 ns,
c_r_st_rec1_vector_1.f2
(lowb+1 to highb-1) after 20 ns ;
--
when 1
=> correct :=
s_r_st_rec1_vector.f2 (lowb+1 to highb-1) =
c_r_st_rec1_vector_2.f2 (lowb+1 to highb-1) and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_r_st_rec1_vector.f2 (lowb+1 to highb-1) =
c_r_st_rec1_vector_1.f2 (lowb+1 to highb-1) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00182.P4" ,
"Multi inertial transactions occurred on signal " &
"asg with slice name prefixed by a selected name on LHS",
correct ) ;
s_r_st_rec1_vector.f2 (lowb+1 to highb-1) <=
c_r_st_rec1_vector_2.f2
(lowb+1 to highb-1) after 10 ns ,
c_r_st_rec1_vector_1.f2
(lowb+1 to highb-1) after 20 ns ,
c_r_st_rec1_vector_2.f2
(lowb+1 to highb-1) after 30 ns ,
c_r_st_rec1_vector_1.f2
(lowb+1 to highb-1) after 40 ns ;
--
when 3
=> correct :=
s_r_st_rec1_vector.f2 (lowb+1 to highb-1) =
c_r_st_rec1_vector_2.f2 (lowb+1 to highb-1) and
(savtime + 10 ns) = Std.Standard.Now ;
s_r_st_rec1_vector.f2 (lowb+1 to highb-1) <=
c_r_st_rec1_vector_1.f2
(lowb+1 to highb-1) after 5 ns ;
--
when 4
=> correct :=
correct and
s_r_st_rec1_vector.f2 (lowb+1 to highb-1) =
c_r_st_rec1_vector_1.f2 (lowb+1 to highb-1) and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00182" ,
"One inertial transaction occurred on signal " &
"asg with slice name prefixed by an selected name on LHS",
correct ) ;
s_r_st_rec1_vector.f2 (lowb+1 to highb-1) <= transport
c_r_st_rec1_vector_1.f2
(lowb+1 to highb-1) after 100 ns ;
--
when 5
=> correct :=
s_r_st_rec1_vector.f2 (lowb+1 to highb-1) =
c_r_st_rec1_vector_1.f2 (lowb+1 to highb-1) and
(savtime + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00182" ,
"Old transactions were removed on signal " &
"asg with slice name prefixed by an selected name on LHS",
correct ) ;
s_r_st_rec1_vector.f2 (lowb+1 to highb-1) <=
c_r_st_rec1_vector_2.f2
(lowb+1 to highb-1) after 10 ns ,
c_r_st_rec1_vector_1.f2
(lowb+1 to highb-1) after 20 ns ,
c_r_st_rec1_vector_2.f2
(lowb+1 to highb-1) after 30 ns ,
c_r_st_rec1_vector_1.f2
(lowb+1 to highb-1) after 40 ns ;
--
when 6
=> correct :=
s_r_st_rec1_vector.f2 (lowb+1 to highb-1) =
c_r_st_rec1_vector_2.f2 (lowb+1 to highb-1) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00182" ,
"One inertial transaction occurred on signal " &
"asg with slice name prefixed by an selected name on LHS",
correct ) ;
-- Last transaction above is marked
s_r_st_rec1_vector.f2 (lowb+1 to highb-1) <=
c_r_st_rec1_vector_1.f2
(lowb+1 to highb-1) after 40 ns ;
--
when 7
=> correct :=
s_r_st_rec1_vector.f2 (lowb+1 to highb-1) =
c_r_st_rec1_vector_1.f2 (lowb+1 to highb-1) and
(savtime + 30 ns) = Std.Standard.Now ;
--
when 8
=> correct := correct and
s_r_st_rec1_vector.f2 (lowb+1 to highb-1) =
c_r_st_rec1_vector_1.f2 (lowb+1 to highb-1) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00182" ,
"Inertial semantics check on a signal " &
"asg with slice name prefixed by an selected name on LHS",
correct ) ;
--
when others
=>
test_report ( "ARCH00182" ,
"Inertial semantics check on a signal " &
"asg with slice name prefixed by an selected name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_r_st_rec1_vector <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
wait until (not s_r_st_rec1_vector'Quiet) and
(savtime /= Std.Standard.Now) ;
--
end process P4 ;
--
PGEN_CHKP_4 :
process ( chk_r_st_rec1_vector )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P4" ,
"Inertial transactions entirely completed",
chk_r_st_rec1_vector = 8 ) ;
end if ;
end process PGEN_CHKP_4 ;
--
--
P5 :
process
variable correct : boolean ;
variable counter : integer := 0 ;
variable savtime : time ;
begin
case counter is
when 0
=> s_r_st_rec2_vector.f2 (lowb+1 to highb-1) <=
c_r_st_rec2_vector_2.f2
(lowb+1 to highb-1) after 10 ns,
c_r_st_rec2_vector_1.f2
(lowb+1 to highb-1) after 20 ns ;
--
when 1
=> correct :=
s_r_st_rec2_vector.f2 (lowb+1 to highb-1) =
c_r_st_rec2_vector_2.f2 (lowb+1 to highb-1) and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_r_st_rec2_vector.f2 (lowb+1 to highb-1) =
c_r_st_rec2_vector_1.f2 (lowb+1 to highb-1) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00182.P5" ,
"Multi inertial transactions occurred on signal " &
"asg with slice name prefixed by a selected name on LHS",
correct ) ;
s_r_st_rec2_vector.f2 (lowb+1 to highb-1) <=
c_r_st_rec2_vector_2.f2
(lowb+1 to highb-1) after 10 ns ,
c_r_st_rec2_vector_1.f2
(lowb+1 to highb-1) after 20 ns ,
c_r_st_rec2_vector_2.f2
(lowb+1 to highb-1) after 30 ns ,
c_r_st_rec2_vector_1.f2
(lowb+1 to highb-1) after 40 ns ;
--
when 3
=> correct :=
s_r_st_rec2_vector.f2 (lowb+1 to highb-1) =
c_r_st_rec2_vector_2.f2 (lowb+1 to highb-1) and
(savtime + 10 ns) = Std.Standard.Now ;
s_r_st_rec2_vector.f2 (lowb+1 to highb-1) <=
c_r_st_rec2_vector_1.f2
(lowb+1 to highb-1) after 5 ns ;
--
when 4
=> correct :=
correct and
s_r_st_rec2_vector.f2 (lowb+1 to highb-1) =
c_r_st_rec2_vector_1.f2 (lowb+1 to highb-1) and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00182" ,
"One inertial transaction occurred on signal " &
"asg with slice name prefixed by an selected name on LHS",
correct ) ;
s_r_st_rec2_vector.f2 (lowb+1 to highb-1) <= transport
c_r_st_rec2_vector_1.f2
(lowb+1 to highb-1) after 100 ns ;
--
when 5
=> correct :=
s_r_st_rec2_vector.f2 (lowb+1 to highb-1) =
c_r_st_rec2_vector_1.f2 (lowb+1 to highb-1) and
(savtime + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00182" ,
"Old transactions were removed on signal " &
"asg with slice name prefixed by an selected name on LHS",
correct ) ;
s_r_st_rec2_vector.f2 (lowb+1 to highb-1) <=
c_r_st_rec2_vector_2.f2
(lowb+1 to highb-1) after 10 ns ,
c_r_st_rec2_vector_1.f2
(lowb+1 to highb-1) after 20 ns ,
c_r_st_rec2_vector_2.f2
(lowb+1 to highb-1) after 30 ns ,
c_r_st_rec2_vector_1.f2
(lowb+1 to highb-1) after 40 ns ;
--
when 6
=> correct :=
s_r_st_rec2_vector.f2 (lowb+1 to highb-1) =
c_r_st_rec2_vector_2.f2 (lowb+1 to highb-1) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00182" ,
"One inertial transaction occurred on signal " &
"asg with slice name prefixed by an selected name on LHS",
correct ) ;
-- Last transaction above is marked
s_r_st_rec2_vector.f2 (lowb+1 to highb-1) <=
c_r_st_rec2_vector_1.f2
(lowb+1 to highb-1) after 40 ns ;
--
when 7
=> correct :=
s_r_st_rec2_vector.f2 (lowb+1 to highb-1) =
c_r_st_rec2_vector_1.f2 (lowb+1 to highb-1) and
(savtime + 30 ns) = Std.Standard.Now ;
--
when 8
=> correct := correct and
s_r_st_rec2_vector.f2 (lowb+1 to highb-1) =
c_r_st_rec2_vector_1.f2 (lowb+1 to highb-1) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00182" ,
"Inertial semantics check on a signal " &
"asg with slice name prefixed by an selected name on LHS",
correct ) ;
--
when others
=>
test_report ( "ARCH00182" ,
"Inertial semantics check on a signal " &
"asg with slice name prefixed by an selected name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_r_st_rec2_vector <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
wait until (not s_r_st_rec2_vector'Quiet) and
(savtime /= Std.Standard.Now) ;
--
end process P5 ;
--
PGEN_CHKP_5 :
process ( chk_r_st_rec2_vector )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P5" ,
"Inertial transactions entirely completed",
chk_r_st_rec2_vector = 8 ) ;
end if ;
end process PGEN_CHKP_5 ;
--
--
P6 :
process
variable correct : boolean ;
variable counter : integer := 0 ;
variable savtime : time ;
begin
case counter is
when 0
=> s_r_st_rec3_vector.f2 (lowb+1 to highb-1) <=
c_r_st_rec3_vector_2.f2
(lowb+1 to highb-1) after 10 ns,
c_r_st_rec3_vector_1.f2
(lowb+1 to highb-1) after 20 ns ;
--
when 1
=> correct :=
s_r_st_rec3_vector.f2 (lowb+1 to highb-1) =
c_r_st_rec3_vector_2.f2 (lowb+1 to highb-1) and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_r_st_rec3_vector.f2 (lowb+1 to highb-1) =
c_r_st_rec3_vector_1.f2 (lowb+1 to highb-1) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00182.P6" ,
"Multi inertial transactions occurred on signal " &
"asg with slice name prefixed by a selected name on LHS",
correct ) ;
s_r_st_rec3_vector.f2 (lowb+1 to highb-1) <=
c_r_st_rec3_vector_2.f2
(lowb+1 to highb-1) after 10 ns ,
c_r_st_rec3_vector_1.f2
(lowb+1 to highb-1) after 20 ns ,
c_r_st_rec3_vector_2.f2
(lowb+1 to highb-1) after 30 ns ,
c_r_st_rec3_vector_1.f2
(lowb+1 to highb-1) after 40 ns ;
--
when 3
=> correct :=
s_r_st_rec3_vector.f2 (lowb+1 to highb-1) =
c_r_st_rec3_vector_2.f2 (lowb+1 to highb-1) and
(savtime + 10 ns) = Std.Standard.Now ;
s_r_st_rec3_vector.f2 (lowb+1 to highb-1) <=
c_r_st_rec3_vector_1.f2
(lowb+1 to highb-1) after 5 ns ;
--
when 4
=> correct :=
correct and
s_r_st_rec3_vector.f2 (lowb+1 to highb-1) =
c_r_st_rec3_vector_1.f2 (lowb+1 to highb-1) and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00182" ,
"One inertial transaction occurred on signal " &
"asg with slice name prefixed by an selected name on LHS",
correct ) ;
s_r_st_rec3_vector.f2 (lowb+1 to highb-1) <= transport
c_r_st_rec3_vector_1.f2
(lowb+1 to highb-1) after 100 ns ;
--
when 5
=> correct :=
s_r_st_rec3_vector.f2 (lowb+1 to highb-1) =
c_r_st_rec3_vector_1.f2 (lowb+1 to highb-1) and
(savtime + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00182" ,
"Old transactions were removed on signal " &
"asg with slice name prefixed by an selected name on LHS",
correct ) ;
s_r_st_rec3_vector.f2 (lowb+1 to highb-1) <=
c_r_st_rec3_vector_2.f2
(lowb+1 to highb-1) after 10 ns ,
c_r_st_rec3_vector_1.f2
(lowb+1 to highb-1) after 20 ns ,
c_r_st_rec3_vector_2.f2
(lowb+1 to highb-1) after 30 ns ,
c_r_st_rec3_vector_1.f2
(lowb+1 to highb-1) after 40 ns ;
--
when 6
=> correct :=
s_r_st_rec3_vector.f2 (lowb+1 to highb-1) =
c_r_st_rec3_vector_2.f2 (lowb+1 to highb-1) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00182" ,
"One inertial transaction occurred on signal " &
"asg with slice name prefixed by an selected name on LHS",
correct ) ;
-- Last transaction above is marked
s_r_st_rec3_vector.f2 (lowb+1 to highb-1) <=
c_r_st_rec3_vector_1.f2
(lowb+1 to highb-1) after 40 ns ;
--
when 7
=> correct :=
s_r_st_rec3_vector.f2 (lowb+1 to highb-1) =
c_r_st_rec3_vector_1.f2 (lowb+1 to highb-1) and
(savtime + 30 ns) = Std.Standard.Now ;
--
when 8
=> correct := correct and
s_r_st_rec3_vector.f2 (lowb+1 to highb-1) =
c_r_st_rec3_vector_1.f2 (lowb+1 to highb-1) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00182" ,
"Inertial semantics check on a signal " &
"asg with slice name prefixed by an selected name on LHS",
correct ) ;
--
when others
=>
test_report ( "ARCH00182" ,
"Inertial semantics check on a signal " &
"asg with slice name prefixed by an selected name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_r_st_rec3_vector <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
wait until (not s_r_st_rec3_vector'Quiet) and
(savtime /= Std.Standard.Now) ;
--
end process P6 ;
--
PGEN_CHKP_6 :
process ( chk_r_st_rec3_vector )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P6" ,
"Inertial transactions entirely completed",
chk_r_st_rec3_vector = 8 ) ;
end if ;
end process PGEN_CHKP_6 ;
--
--
--
end ARCH00182 ;
--
use WORK.STANDARD_TYPES.all ;
use WORK.PKG00182.all ;
entity ENT00182_Test_Bench is
signal s_r_st_arr1_vector : r_st_arr1_vector
:= c_r_st_arr1_vector_1 ;
signal s_r_st_arr2_vector : r_st_arr2_vector
:= c_r_st_arr2_vector_1 ;
signal s_r_st_arr3_vector : r_st_arr3_vector
:= c_r_st_arr3_vector_1 ;
signal s_r_st_rec1_vector : r_st_rec1_vector
:= c_r_st_rec1_vector_1 ;
signal s_r_st_rec2_vector : r_st_rec2_vector
:= c_r_st_rec2_vector_1 ;
signal s_r_st_rec3_vector : r_st_rec3_vector
:= c_r_st_rec3_vector_1 ;
--
end ENT00182_Test_Bench ;
--
architecture ARCH00182_Test_Bench of ENT00182_Test_Bench is
begin
L1:
block
component UUT
port (
s_r_st_arr1_vector : inout r_st_arr1_vector
; s_r_st_arr2_vector : inout r_st_arr2_vector
; s_r_st_arr3_vector : inout r_st_arr3_vector
; s_r_st_rec1_vector : inout r_st_rec1_vector
; s_r_st_rec2_vector : inout r_st_rec2_vector
; s_r_st_rec3_vector : inout r_st_rec3_vector
) ;
end component ;
--
for CIS1 : UUT use entity WORK.ENT00182 ( ARCH00182 ) ;
begin
CIS1 : UUT
port map (
s_r_st_arr1_vector
, s_r_st_arr2_vector
, s_r_st_arr3_vector
, s_r_st_rec1_vector
, s_r_st_rec2_vector
, s_r_st_rec3_vector
) ;
end block L1 ;
end ARCH00182_Test_Bench ;
| gpl-3.0 | 331719f427cc6450fd7e26d653b8bae4 | 0.502321 | 3.227301 | false | false | false | false |
Subsets and Splits
No community queries yet
The top public SQL queries from the community will appear here once available.