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TWW12/lzw | final_project_sim/lzw/lzw.cache/ip/5423d0f67720863f/bram_4096_sim_netlist.vhdl | 1 | 86,708 | -- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1756540 Mon Jan 23 19:11:23 MST 2017
-- Date : Tue Apr 18 23:15:19 2017
-- Host : DESKTOP-I9J3TQJ running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
-- decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ bram_4096_sim_netlist.vhdl
-- Design : bram_4096
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7z020clg484-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper_init is
port (
DOADO : out STD_LOGIC_VECTOR ( 3 downto 0 );
clka : in STD_LOGIC;
ena : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 11 downto 0 );
dina : in STD_LOGIC_VECTOR ( 3 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 )
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper_init;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper_init is
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 15 downto 4 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 15 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute CLOCK_DOMAINS : string;
attribute CLOCK_DOMAINS of \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram\ : label is "COMMON";
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram\: unisim.vcomponents.RAMB18E1
generic map(
DOA_REG => 1,
DOB_REG => 0,
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INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"00000",
INIT_B => X"00000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "PERFORMANCE",
READ_WIDTH_A => 4,
READ_WIDTH_B => 4,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"00000",
SRVAL_B => X"00000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 4,
WRITE_WIDTH_B => 4
)
port map (
ADDRARDADDR(13 downto 2) => addra(11 downto 0),
ADDRARDADDR(1 downto 0) => B"00",
ADDRBWRADDR(13 downto 0) => B"00000000000000",
CLKARDCLK => clka,
CLKBWRCLK => clka,
DIADI(15 downto 4) => B"000000000000",
DIADI(3 downto 0) => dina(3 downto 0),
DIBDI(15 downto 0) => B"0000000000000000",
DIPADIP(1 downto 0) => B"00",
DIPBDIP(1 downto 0) => B"00",
DOADO(15 downto 4) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_DOADO_UNCONNECTED\(15 downto 4),
DOADO(3 downto 0) => DOADO(3 downto 0),
DOBDO(15 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_DOBDO_UNCONNECTED\(15 downto 0),
DOPADOP(1 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_DOPADOP_UNCONNECTED\(1 downto 0),
DOPBDOP(1 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_DOPBDOP_UNCONNECTED\(1 downto 0),
ENARDEN => ena,
ENBWREN => '0',
REGCEAREGCE => ena,
REGCEB => '0',
RSTRAMARSTRAM => '0',
RSTRAMB => '0',
RSTREGARSTREG => '0',
RSTREGB => '0',
WEA(1) => wea(0),
WEA(0) => wea(0),
WEBWE(3 downto 0) => B"0000"
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper_init__parameterized0\ is
port (
douta_array : out STD_LOGIC_VECTOR ( 8 downto 0 );
clka : in STD_LOGIC;
ena : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 11 downto 0 );
dina : in STD_LOGIC_VECTOR ( 8 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper_init__parameterized0\ : entity is "blk_mem_gen_prim_wrapper_init";
end \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper_init__parameterized0\;
architecture STRUCTURE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper_init__parameterized0\ is
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 8 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute CLOCK_DOMAINS : string;
attribute CLOCK_DOMAINS of \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\ : label is "COMMON";
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 1,
DOB_REG => 0,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
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INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_02 => X"0605050505050505050505050505050505040404040404040404040404040404",
INIT_03 => X"0807070707070707070707070707070707060606060606060606060606060606",
INIT_04 => X"0A09090909090909090909090909090909080808080808080808080808080808",
INIT_05 => X"0C0B0B0B0B0B0B0B0B0B0B0B0B0B0B0B0B0A0A0A0A0A0A0A0A0A0A0A0A0A0A0A",
INIT_06 => X"0E0D0D0D0D0D0D0D0D0D0D0D0D0D0D0D0D0C0C0C0C0C0C0C0C0C0C0C0C0C0C0C",
INIT_07 => X"000F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E",
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INIT_4D => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_52 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_5B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_60 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_61 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_62 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_63 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_64 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_65 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_66 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_67 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_68 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_69 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_70 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_71 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_72 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_73 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_74 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "PERFORMANCE",
READ_WIDTH_A => 9,
READ_WIDTH_B => 9,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 9,
WRITE_WIDTH_B => 9
)
port map (
ADDRARDADDR(15) => '1',
ADDRARDADDR(14 downto 3) => addra(11 downto 0),
ADDRARDADDR(2 downto 0) => B"111",
ADDRBWRADDR(15 downto 0) => B"0000000000000000",
CASCADEINA => '0',
CASCADEINB => '0',
CASCADEOUTA => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => clka,
CLKBWRCLK => clka,
DBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\,
DIADI(31 downto 8) => B"000000000000000000000000",
DIADI(7 downto 0) => dina(7 downto 0),
DIBDI(31 downto 0) => B"00000000000000000000000000000000",
DIPADIP(3 downto 1) => B"000",
DIPADIP(0) => dina(8),
DIPBDIP(3 downto 0) => B"0000",
DOADO(31 downto 8) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\(31 downto 8),
DOADO(7 downto 0) => douta_array(7 downto 0),
DOBDO(31 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\(31 downto 0),
DOPADOP(3 downto 1) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\(3 downto 1),
DOPADOP(0) => douta_array(8),
DOPBDOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\(3 downto 0),
ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => ena,
ENBWREN => '0',
INJECTDBITERR => '0',
INJECTSBITERR => '0',
RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => ena,
REGCEB => '0',
RSTRAMARSTRAM => '0',
RSTRAMB => '0',
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\,
WEA(3) => wea(0),
WEA(2) => wea(0),
WEA(1) => wea(0),
WEA(0) => wea(0),
WEBWE(7 downto 0) => B"00000000"
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper_init__parameterized1\ is
port (
DOADO : out STD_LOGIC_VECTOR ( 6 downto 0 );
clka : in STD_LOGIC;
ena : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 11 downto 0 );
dina : in STD_LOGIC_VECTOR ( 6 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper_init__parameterized1\ : entity is "blk_mem_gen_prim_wrapper_init";
end \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper_init__parameterized1\;
architecture STRUCTURE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper_init__parameterized1\ is
signal \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_45\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_88\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 8 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute CLOCK_DOMAINS : string;
attribute CLOCK_DOMAINS of \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\ : label is "COMMON";
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 1,
DOB_REG => 0,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_56 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_57 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_58 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_59 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5F => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_61 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_62 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_63 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_65 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_66 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_67 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_68 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_69 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6F => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_71 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_72 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_73 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_74 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "PERFORMANCE",
READ_WIDTH_A => 9,
READ_WIDTH_B => 9,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 9,
WRITE_WIDTH_B => 9
)
port map (
ADDRARDADDR(15) => '1',
ADDRARDADDR(14 downto 3) => addra(11 downto 0),
ADDRARDADDR(2 downto 0) => B"111",
ADDRBWRADDR(15 downto 0) => B"0000000000000000",
CASCADEINA => '0',
CASCADEINB => '0',
CASCADEOUTA => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => clka,
CLKBWRCLK => clka,
DBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\,
DIADI(31 downto 7) => B"0000000000000000000000000",
DIADI(6 downto 0) => dina(6 downto 0),
DIBDI(31 downto 0) => B"00000000000000000000000000000000",
DIPADIP(3 downto 0) => B"0000",
DIPBDIP(3 downto 0) => B"0000",
DOADO(31 downto 8) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\(31 downto 8),
DOADO(7) => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_45\,
DOADO(6 downto 0) => DOADO(6 downto 0),
DOBDO(31 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\(31 downto 0),
DOPADOP(3 downto 1) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\(3 downto 1),
DOPADOP(0) => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_88\,
DOPBDOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\(3 downto 0),
ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => ena,
ENBWREN => '0',
INJECTDBITERR => '0',
INJECTSBITERR => '0',
RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => ena,
REGCEB => '0',
RSTRAMARSTRAM => '0',
RSTRAMB => '0',
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\,
WEA(3) => wea(0),
WEA(2) => wea(0),
WEA(1) => wea(0),
WEA(0) => wea(0),
WEBWE(7 downto 0) => B"00000000"
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width is
port (
DOADO : out STD_LOGIC_VECTOR ( 3 downto 0 );
clka : in STD_LOGIC;
ena : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 11 downto 0 );
dina : in STD_LOGIC_VECTOR ( 3 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 )
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width is
begin
\prim_init.ram\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper_init
port map (
DOADO(3 downto 0) => DOADO(3 downto 0),
addra(11 downto 0) => addra(11 downto 0),
clka => clka,
dina(3 downto 0) => dina(3 downto 0),
ena => ena,
wea(0) => wea(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized0\ is
port (
douta_array : out STD_LOGIC_VECTOR ( 8 downto 0 );
clka : in STD_LOGIC;
ena : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 11 downto 0 );
dina : in STD_LOGIC_VECTOR ( 8 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized0\ : entity is "blk_mem_gen_prim_width";
end \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized0\;
architecture STRUCTURE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized0\ is
begin
\prim_init.ram\: entity work.\decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper_init__parameterized0\
port map (
addra(11 downto 0) => addra(11 downto 0),
clka => clka,
dina(8 downto 0) => dina(8 downto 0),
douta_array(8 downto 0) => douta_array(8 downto 0),
ena => ena,
wea(0) => wea(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized1\ is
port (
DOADO : out STD_LOGIC_VECTOR ( 6 downto 0 );
clka : in STD_LOGIC;
ena : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 11 downto 0 );
dina : in STD_LOGIC_VECTOR ( 6 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized1\ : entity is "blk_mem_gen_prim_width";
end \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized1\;
architecture STRUCTURE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized1\ is
begin
\prim_init.ram\: entity work.\decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper_init__parameterized1\
port map (
DOADO(6 downto 0) => DOADO(6 downto 0),
addra(11 downto 0) => addra(11 downto 0),
clka => clka,
dina(6 downto 0) => dina(6 downto 0),
ena => ena,
wea(0) => wea(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_generic_cstr is
port (
douta : out STD_LOGIC_VECTOR ( 19 downto 0 );
clka : in STD_LOGIC;
ena : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 11 downto 0 );
dina : in STD_LOGIC_VECTOR ( 19 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 )
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_generic_cstr;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_generic_cstr is
signal douta_array : STD_LOGIC_VECTOR ( 19 downto 0 );
begin
\mux_a_wire.mux_reg.ce_pri.douta_i_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clka,
CE => ena,
D => douta_array(0),
Q => douta(0),
R => '0'
);
\mux_a_wire.mux_reg.ce_pri.douta_i_reg[10]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clka,
CE => ena,
D => douta_array(10),
Q => douta(10),
R => '0'
);
\mux_a_wire.mux_reg.ce_pri.douta_i_reg[11]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clka,
CE => ena,
D => douta_array(11),
Q => douta(11),
R => '0'
);
\mux_a_wire.mux_reg.ce_pri.douta_i_reg[12]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clka,
CE => ena,
D => douta_array(12),
Q => douta(12),
R => '0'
);
\mux_a_wire.mux_reg.ce_pri.douta_i_reg[13]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clka,
CE => ena,
D => douta_array(13),
Q => douta(13),
R => '0'
);
\mux_a_wire.mux_reg.ce_pri.douta_i_reg[14]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clka,
CE => ena,
D => douta_array(14),
Q => douta(14),
R => '0'
);
\mux_a_wire.mux_reg.ce_pri.douta_i_reg[15]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clka,
CE => ena,
D => douta_array(15),
Q => douta(15),
R => '0'
);
\mux_a_wire.mux_reg.ce_pri.douta_i_reg[16]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clka,
CE => ena,
D => douta_array(16),
Q => douta(16),
R => '0'
);
\mux_a_wire.mux_reg.ce_pri.douta_i_reg[17]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clka,
CE => ena,
D => douta_array(17),
Q => douta(17),
R => '0'
);
\mux_a_wire.mux_reg.ce_pri.douta_i_reg[18]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clka,
CE => ena,
D => douta_array(18),
Q => douta(18),
R => '0'
);
\mux_a_wire.mux_reg.ce_pri.douta_i_reg[19]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clka,
CE => ena,
D => douta_array(19),
Q => douta(19),
R => '0'
);
\mux_a_wire.mux_reg.ce_pri.douta_i_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clka,
CE => ena,
D => douta_array(1),
Q => douta(1),
R => '0'
);
\mux_a_wire.mux_reg.ce_pri.douta_i_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clka,
CE => ena,
D => douta_array(2),
Q => douta(2),
R => '0'
);
\mux_a_wire.mux_reg.ce_pri.douta_i_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clka,
CE => ena,
D => douta_array(3),
Q => douta(3),
R => '0'
);
\mux_a_wire.mux_reg.ce_pri.douta_i_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clka,
CE => ena,
D => douta_array(4),
Q => douta(4),
R => '0'
);
\mux_a_wire.mux_reg.ce_pri.douta_i_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clka,
CE => ena,
D => douta_array(5),
Q => douta(5),
R => '0'
);
\mux_a_wire.mux_reg.ce_pri.douta_i_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clka,
CE => ena,
D => douta_array(6),
Q => douta(6),
R => '0'
);
\mux_a_wire.mux_reg.ce_pri.douta_i_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clka,
CE => ena,
D => douta_array(7),
Q => douta(7),
R => '0'
);
\mux_a_wire.mux_reg.ce_pri.douta_i_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clka,
CE => ena,
D => douta_array(8),
Q => douta(8),
R => '0'
);
\mux_a_wire.mux_reg.ce_pri.douta_i_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clka,
CE => ena,
D => douta_array(9),
Q => douta(9),
R => '0'
);
\ramloop[0].ram.r\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width
port map (
DOADO(3 downto 0) => douta_array(3 downto 0),
addra(11 downto 0) => addra(11 downto 0),
clka => clka,
dina(3 downto 0) => dina(3 downto 0),
ena => ena,
wea(0) => wea(0)
);
\ramloop[1].ram.r\: entity work.\decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized0\
port map (
addra(11 downto 0) => addra(11 downto 0),
clka => clka,
dina(8 downto 0) => dina(12 downto 4),
douta_array(8 downto 0) => douta_array(12 downto 4),
ena => ena,
wea(0) => wea(0)
);
\ramloop[2].ram.r\: entity work.\decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized1\
port map (
DOADO(6 downto 0) => douta_array(19 downto 13),
addra(11 downto 0) => addra(11 downto 0),
clka => clka,
dina(6 downto 0) => dina(19 downto 13),
ena => ena,
wea(0) => wea(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_top is
port (
douta : out STD_LOGIC_VECTOR ( 19 downto 0 );
clka : in STD_LOGIC;
ena : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 11 downto 0 );
dina : in STD_LOGIC_VECTOR ( 19 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 )
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_top;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_top is
begin
\valid.cstr\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_generic_cstr
port map (
addra(11 downto 0) => addra(11 downto 0),
clka => clka,
dina(19 downto 0) => dina(19 downto 0),
douta(19 downto 0) => douta(19 downto 0),
ena => ena,
wea(0) => wea(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5_synth is
port (
douta : out STD_LOGIC_VECTOR ( 19 downto 0 );
clka : in STD_LOGIC;
ena : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 11 downto 0 );
dina : in STD_LOGIC_VECTOR ( 19 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 )
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5_synth;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5_synth is
begin
\gnbram.gnativebmg.native_blk_mem_gen\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_top
port map (
addra(11 downto 0) => addra(11 downto 0),
clka => clka,
dina(19 downto 0) => dina(19 downto 0),
douta(19 downto 0) => douta(19 downto 0),
ena => ena,
wea(0) => wea(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 is
port (
clka : in STD_LOGIC;
rsta : in STD_LOGIC;
ena : in STD_LOGIC;
regcea : in STD_LOGIC;
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
addra : in STD_LOGIC_VECTOR ( 11 downto 0 );
dina : in STD_LOGIC_VECTOR ( 19 downto 0 );
douta : out STD_LOGIC_VECTOR ( 19 downto 0 );
clkb : in STD_LOGIC;
rstb : in STD_LOGIC;
enb : in STD_LOGIC;
regceb : in STD_LOGIC;
web : in STD_LOGIC_VECTOR ( 0 to 0 );
addrb : in STD_LOGIC_VECTOR ( 11 downto 0 );
dinb : in STD_LOGIC_VECTOR ( 19 downto 0 );
doutb : out STD_LOGIC_VECTOR ( 19 downto 0 );
injectsbiterr : in STD_LOGIC;
injectdbiterr : in STD_LOGIC;
eccpipece : in STD_LOGIC;
sbiterr : out STD_LOGIC;
dbiterr : out STD_LOGIC;
rdaddrecc : out STD_LOGIC_VECTOR ( 11 downto 0 );
sleep : in STD_LOGIC;
deepsleep : in STD_LOGIC;
shutdown : in STD_LOGIC;
rsta_busy : out STD_LOGIC;
rstb_busy : out STD_LOGIC;
s_aclk : in STD_LOGIC;
s_aresetn : in STD_LOGIC;
s_axi_awid : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_awready : out STD_LOGIC;
s_axi_wdata : in STD_LOGIC_VECTOR ( 19 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_wlast : in STD_LOGIC;
s_axi_wvalid : in STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_bid : out STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_bvalid : out STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_arid : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arvalid : in STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_rid : out STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_rdata : out STD_LOGIC_VECTOR ( 19 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rlast : out STD_LOGIC;
s_axi_rvalid : out STD_LOGIC;
s_axi_rready : in STD_LOGIC;
s_axi_injectsbiterr : in STD_LOGIC;
s_axi_injectdbiterr : in STD_LOGIC;
s_axi_sbiterr : out STD_LOGIC;
s_axi_dbiterr : out STD_LOGIC;
s_axi_rdaddrecc : out STD_LOGIC_VECTOR ( 11 downto 0 )
);
attribute C_ADDRA_WIDTH : integer;
attribute C_ADDRA_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is 12;
attribute C_ADDRB_WIDTH : integer;
attribute C_ADDRB_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is 12;
attribute C_ALGORITHM : integer;
attribute C_ALGORITHM of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is 1;
attribute C_AXI_ID_WIDTH : integer;
attribute C_AXI_ID_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is 4;
attribute C_AXI_SLAVE_TYPE : integer;
attribute C_AXI_SLAVE_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_AXI_TYPE : integer;
attribute C_AXI_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is 1;
attribute C_BYTE_SIZE : integer;
attribute C_BYTE_SIZE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is 9;
attribute C_COMMON_CLK : integer;
attribute C_COMMON_CLK of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_COUNT_18K_BRAM : string;
attribute C_COUNT_18K_BRAM of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is "1";
attribute C_COUNT_36K_BRAM : string;
attribute C_COUNT_36K_BRAM of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is "2";
attribute C_CTRL_ECC_ALGO : string;
attribute C_CTRL_ECC_ALGO of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is "NONE";
attribute C_DEFAULT_DATA : string;
attribute C_DEFAULT_DATA of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is "0";
attribute C_DISABLE_WARN_BHV_COLL : integer;
attribute C_DISABLE_WARN_BHV_COLL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_DISABLE_WARN_BHV_RANGE : integer;
attribute C_DISABLE_WARN_BHV_RANGE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_ELABORATION_DIR : string;
attribute C_ELABORATION_DIR of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is "./";
attribute C_ENABLE_32BIT_ADDRESS : integer;
attribute C_ENABLE_32BIT_ADDRESS of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_EN_DEEPSLEEP_PIN : integer;
attribute C_EN_DEEPSLEEP_PIN of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_EN_ECC_PIPE : integer;
attribute C_EN_ECC_PIPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_EN_RDADDRA_CHG : integer;
attribute C_EN_RDADDRA_CHG of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_EN_RDADDRB_CHG : integer;
attribute C_EN_RDADDRB_CHG of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_EN_SAFETY_CKT : integer;
attribute C_EN_SAFETY_CKT of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_EN_SHUTDOWN_PIN : integer;
attribute C_EN_SHUTDOWN_PIN of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_EN_SLEEP_PIN : integer;
attribute C_EN_SLEEP_PIN of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_EST_POWER_SUMMARY : string;
attribute C_EST_POWER_SUMMARY of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is "Estimated Power for IP : 6.3587 mW";
attribute C_FAMILY : string;
attribute C_FAMILY of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is "zynq";
attribute C_HAS_AXI_ID : integer;
attribute C_HAS_AXI_ID of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_HAS_ENA : integer;
attribute C_HAS_ENA of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is 1;
attribute C_HAS_ENB : integer;
attribute C_HAS_ENB of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_HAS_INJECTERR : integer;
attribute C_HAS_INJECTERR of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_HAS_MEM_OUTPUT_REGS_A : integer;
attribute C_HAS_MEM_OUTPUT_REGS_A of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is 1;
attribute C_HAS_MEM_OUTPUT_REGS_B : integer;
attribute C_HAS_MEM_OUTPUT_REGS_B of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_HAS_MUX_OUTPUT_REGS_A : integer;
attribute C_HAS_MUX_OUTPUT_REGS_A of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is 1;
attribute C_HAS_MUX_OUTPUT_REGS_B : integer;
attribute C_HAS_MUX_OUTPUT_REGS_B of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_HAS_REGCEA : integer;
attribute C_HAS_REGCEA of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_HAS_REGCEB : integer;
attribute C_HAS_REGCEB of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_HAS_RSTA : integer;
attribute C_HAS_RSTA of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_HAS_RSTB : integer;
attribute C_HAS_RSTB of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_HAS_SOFTECC_INPUT_REGS_A : integer;
attribute C_HAS_SOFTECC_INPUT_REGS_A of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_HAS_SOFTECC_OUTPUT_REGS_B : integer;
attribute C_HAS_SOFTECC_OUTPUT_REGS_B of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_INITA_VAL : string;
attribute C_INITA_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is "0";
attribute C_INITB_VAL : string;
attribute C_INITB_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is "0";
attribute C_INIT_FILE : string;
attribute C_INIT_FILE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is "bram_4096.mem";
attribute C_INIT_FILE_NAME : string;
attribute C_INIT_FILE_NAME of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is "bram_4096.mif";
attribute C_INTERFACE_TYPE : integer;
attribute C_INTERFACE_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_LOAD_INIT_FILE : integer;
attribute C_LOAD_INIT_FILE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is 1;
attribute C_MEM_TYPE : integer;
attribute C_MEM_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_MUX_PIPELINE_STAGES : integer;
attribute C_MUX_PIPELINE_STAGES of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_PRIM_TYPE : integer;
attribute C_PRIM_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is 1;
attribute C_READ_DEPTH_A : integer;
attribute C_READ_DEPTH_A of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is 4096;
attribute C_READ_DEPTH_B : integer;
attribute C_READ_DEPTH_B of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is 4096;
attribute C_READ_WIDTH_A : integer;
attribute C_READ_WIDTH_A of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is 20;
attribute C_READ_WIDTH_B : integer;
attribute C_READ_WIDTH_B of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is 20;
attribute C_RSTRAM_A : integer;
attribute C_RSTRAM_A of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_RSTRAM_B : integer;
attribute C_RSTRAM_B of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_RST_PRIORITY_A : string;
attribute C_RST_PRIORITY_A of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is "CE";
attribute C_RST_PRIORITY_B : string;
attribute C_RST_PRIORITY_B of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is "CE";
attribute C_SIM_COLLISION_CHECK : string;
attribute C_SIM_COLLISION_CHECK of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is "ALL";
attribute C_USE_BRAM_BLOCK : integer;
attribute C_USE_BRAM_BLOCK of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_USE_BYTE_WEA : integer;
attribute C_USE_BYTE_WEA of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_USE_BYTE_WEB : integer;
attribute C_USE_BYTE_WEB of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_USE_DEFAULT_DATA : integer;
attribute C_USE_DEFAULT_DATA of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is 1;
attribute C_USE_ECC : integer;
attribute C_USE_ECC of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_USE_SOFTECC : integer;
attribute C_USE_SOFTECC of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_USE_URAM : integer;
attribute C_USE_URAM of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_WEA_WIDTH : integer;
attribute C_WEA_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is 1;
attribute C_WEB_WIDTH : integer;
attribute C_WEB_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is 1;
attribute C_WRITE_DEPTH_A : integer;
attribute C_WRITE_DEPTH_A of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is 4096;
attribute C_WRITE_DEPTH_B : integer;
attribute C_WRITE_DEPTH_B of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is 4096;
attribute C_WRITE_MODE_A : string;
attribute C_WRITE_MODE_A of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is "WRITE_FIRST";
attribute C_WRITE_MODE_B : string;
attribute C_WRITE_MODE_B of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is "WRITE_FIRST";
attribute C_WRITE_WIDTH_A : integer;
attribute C_WRITE_WIDTH_A of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is 20;
attribute C_WRITE_WIDTH_B : integer;
attribute C_WRITE_WIDTH_B of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is 20;
attribute C_XDEVICEFAMILY : string;
attribute C_XDEVICEFAMILY of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is "zynq";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is "yes";
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 is
signal \<const0>\ : STD_LOGIC;
begin
dbiterr <= \<const0>\;
doutb(19) <= \<const0>\;
doutb(18) <= \<const0>\;
doutb(17) <= \<const0>\;
doutb(16) <= \<const0>\;
doutb(15) <= \<const0>\;
doutb(14) <= \<const0>\;
doutb(13) <= \<const0>\;
doutb(12) <= \<const0>\;
doutb(11) <= \<const0>\;
doutb(10) <= \<const0>\;
doutb(9) <= \<const0>\;
doutb(8) <= \<const0>\;
doutb(7) <= \<const0>\;
doutb(6) <= \<const0>\;
doutb(5) <= \<const0>\;
doutb(4) <= \<const0>\;
doutb(3) <= \<const0>\;
doutb(2) <= \<const0>\;
doutb(1) <= \<const0>\;
doutb(0) <= \<const0>\;
rdaddrecc(11) <= \<const0>\;
rdaddrecc(10) <= \<const0>\;
rdaddrecc(9) <= \<const0>\;
rdaddrecc(8) <= \<const0>\;
rdaddrecc(7) <= \<const0>\;
rdaddrecc(6) <= \<const0>\;
rdaddrecc(5) <= \<const0>\;
rdaddrecc(4) <= \<const0>\;
rdaddrecc(3) <= \<const0>\;
rdaddrecc(2) <= \<const0>\;
rdaddrecc(1) <= \<const0>\;
rdaddrecc(0) <= \<const0>\;
rsta_busy <= \<const0>\;
rstb_busy <= \<const0>\;
s_axi_arready <= \<const0>\;
s_axi_awready <= \<const0>\;
s_axi_bid(3) <= \<const0>\;
s_axi_bid(2) <= \<const0>\;
s_axi_bid(1) <= \<const0>\;
s_axi_bid(0) <= \<const0>\;
s_axi_bresp(1) <= \<const0>\;
s_axi_bresp(0) <= \<const0>\;
s_axi_bvalid <= \<const0>\;
s_axi_dbiterr <= \<const0>\;
s_axi_rdaddrecc(11) <= \<const0>\;
s_axi_rdaddrecc(10) <= \<const0>\;
s_axi_rdaddrecc(9) <= \<const0>\;
s_axi_rdaddrecc(8) <= \<const0>\;
s_axi_rdaddrecc(7) <= \<const0>\;
s_axi_rdaddrecc(6) <= \<const0>\;
s_axi_rdaddrecc(5) <= \<const0>\;
s_axi_rdaddrecc(4) <= \<const0>\;
s_axi_rdaddrecc(3) <= \<const0>\;
s_axi_rdaddrecc(2) <= \<const0>\;
s_axi_rdaddrecc(1) <= \<const0>\;
s_axi_rdaddrecc(0) <= \<const0>\;
s_axi_rdata(19) <= \<const0>\;
s_axi_rdata(18) <= \<const0>\;
s_axi_rdata(17) <= \<const0>\;
s_axi_rdata(16) <= \<const0>\;
s_axi_rdata(15) <= \<const0>\;
s_axi_rdata(14) <= \<const0>\;
s_axi_rdata(13) <= \<const0>\;
s_axi_rdata(12) <= \<const0>\;
s_axi_rdata(11) <= \<const0>\;
s_axi_rdata(10) <= \<const0>\;
s_axi_rdata(9) <= \<const0>\;
s_axi_rdata(8) <= \<const0>\;
s_axi_rdata(7) <= \<const0>\;
s_axi_rdata(6) <= \<const0>\;
s_axi_rdata(5) <= \<const0>\;
s_axi_rdata(4) <= \<const0>\;
s_axi_rdata(3) <= \<const0>\;
s_axi_rdata(2) <= \<const0>\;
s_axi_rdata(1) <= \<const0>\;
s_axi_rdata(0) <= \<const0>\;
s_axi_rid(3) <= \<const0>\;
s_axi_rid(2) <= \<const0>\;
s_axi_rid(1) <= \<const0>\;
s_axi_rid(0) <= \<const0>\;
s_axi_rlast <= \<const0>\;
s_axi_rresp(1) <= \<const0>\;
s_axi_rresp(0) <= \<const0>\;
s_axi_rvalid <= \<const0>\;
s_axi_sbiterr <= \<const0>\;
s_axi_wready <= \<const0>\;
sbiterr <= \<const0>\;
GND: unisim.vcomponents.GND
port map (
G => \<const0>\
);
inst_blk_mem_gen: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5_synth
port map (
addra(11 downto 0) => addra(11 downto 0),
clka => clka,
dina(19 downto 0) => dina(19 downto 0),
douta(19 downto 0) => douta(19 downto 0),
ena => ena,
wea(0) => wea(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
port (
clka : in STD_LOGIC;
ena : in STD_LOGIC;
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
addra : in STD_LOGIC_VECTOR ( 11 downto 0 );
dina : in STD_LOGIC_VECTOR ( 19 downto 0 );
douta : out STD_LOGIC_VECTOR ( 19 downto 0 )
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is true;
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "bram_4096,blk_mem_gen_v8_3_5,{}";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "yes";
attribute x_core_info : string;
attribute x_core_info of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "blk_mem_gen_v8_3_5,Vivado 2016.4";
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
signal NLW_U0_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_rsta_busy_UNCONNECTED : STD_LOGIC;
signal NLW_U0_rstb_busy_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_arready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_awready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_bvalid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_rlast_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_rvalid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_wready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_doutb_UNCONNECTED : STD_LOGIC_VECTOR ( 19 downto 0 );
signal NLW_U0_rdaddrecc_UNCONNECTED : STD_LOGIC_VECTOR ( 11 downto 0 );
signal NLW_U0_s_axi_bid_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_s_axi_bresp_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_U0_s_axi_rdaddrecc_UNCONNECTED : STD_LOGIC_VECTOR ( 11 downto 0 );
signal NLW_U0_s_axi_rdata_UNCONNECTED : STD_LOGIC_VECTOR ( 19 downto 0 );
signal NLW_U0_s_axi_rid_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_s_axi_rresp_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute C_ADDRA_WIDTH : integer;
attribute C_ADDRA_WIDTH of U0 : label is 12;
attribute C_ADDRB_WIDTH : integer;
attribute C_ADDRB_WIDTH of U0 : label is 12;
attribute C_ALGORITHM : integer;
attribute C_ALGORITHM of U0 : label is 1;
attribute C_AXI_ID_WIDTH : integer;
attribute C_AXI_ID_WIDTH of U0 : label is 4;
attribute C_AXI_SLAVE_TYPE : integer;
attribute C_AXI_SLAVE_TYPE of U0 : label is 0;
attribute C_AXI_TYPE : integer;
attribute C_AXI_TYPE of U0 : label is 1;
attribute C_BYTE_SIZE : integer;
attribute C_BYTE_SIZE of U0 : label is 9;
attribute C_COMMON_CLK : integer;
attribute C_COMMON_CLK of U0 : label is 0;
attribute C_COUNT_18K_BRAM : string;
attribute C_COUNT_18K_BRAM of U0 : label is "1";
attribute C_COUNT_36K_BRAM : string;
attribute C_COUNT_36K_BRAM of U0 : label is "2";
attribute C_CTRL_ECC_ALGO : string;
attribute C_CTRL_ECC_ALGO of U0 : label is "NONE";
attribute C_DEFAULT_DATA : string;
attribute C_DEFAULT_DATA of U0 : label is "0";
attribute C_DISABLE_WARN_BHV_COLL : integer;
attribute C_DISABLE_WARN_BHV_COLL of U0 : label is 0;
attribute C_DISABLE_WARN_BHV_RANGE : integer;
attribute C_DISABLE_WARN_BHV_RANGE of U0 : label is 0;
attribute C_ELABORATION_DIR : string;
attribute C_ELABORATION_DIR of U0 : label is "./";
attribute C_ENABLE_32BIT_ADDRESS : integer;
attribute C_ENABLE_32BIT_ADDRESS of U0 : label is 0;
attribute C_EN_DEEPSLEEP_PIN : integer;
attribute C_EN_DEEPSLEEP_PIN of U0 : label is 0;
attribute C_EN_ECC_PIPE : integer;
attribute C_EN_ECC_PIPE of U0 : label is 0;
attribute C_EN_RDADDRA_CHG : integer;
attribute C_EN_RDADDRA_CHG of U0 : label is 0;
attribute C_EN_RDADDRB_CHG : integer;
attribute C_EN_RDADDRB_CHG of U0 : label is 0;
attribute C_EN_SAFETY_CKT : integer;
attribute C_EN_SAFETY_CKT of U0 : label is 0;
attribute C_EN_SHUTDOWN_PIN : integer;
attribute C_EN_SHUTDOWN_PIN of U0 : label is 0;
attribute C_EN_SLEEP_PIN : integer;
attribute C_EN_SLEEP_PIN of U0 : label is 0;
attribute C_EST_POWER_SUMMARY : string;
attribute C_EST_POWER_SUMMARY of U0 : label is "Estimated Power for IP : 6.3587 mW";
attribute C_FAMILY : string;
attribute C_FAMILY of U0 : label is "zynq";
attribute C_HAS_AXI_ID : integer;
attribute C_HAS_AXI_ID of U0 : label is 0;
attribute C_HAS_ENA : integer;
attribute C_HAS_ENA of U0 : label is 1;
attribute C_HAS_ENB : integer;
attribute C_HAS_ENB of U0 : label is 0;
attribute C_HAS_INJECTERR : integer;
attribute C_HAS_INJECTERR of U0 : label is 0;
attribute C_HAS_MEM_OUTPUT_REGS_A : integer;
attribute C_HAS_MEM_OUTPUT_REGS_A of U0 : label is 1;
attribute C_HAS_MEM_OUTPUT_REGS_B : integer;
attribute C_HAS_MEM_OUTPUT_REGS_B of U0 : label is 0;
attribute C_HAS_MUX_OUTPUT_REGS_A : integer;
attribute C_HAS_MUX_OUTPUT_REGS_A of U0 : label is 1;
attribute C_HAS_MUX_OUTPUT_REGS_B : integer;
attribute C_HAS_MUX_OUTPUT_REGS_B of U0 : label is 0;
attribute C_HAS_REGCEA : integer;
attribute C_HAS_REGCEA of U0 : label is 0;
attribute C_HAS_REGCEB : integer;
attribute C_HAS_REGCEB of U0 : label is 0;
attribute C_HAS_RSTA : integer;
attribute C_HAS_RSTA of U0 : label is 0;
attribute C_HAS_RSTB : integer;
attribute C_HAS_RSTB of U0 : label is 0;
attribute C_HAS_SOFTECC_INPUT_REGS_A : integer;
attribute C_HAS_SOFTECC_INPUT_REGS_A of U0 : label is 0;
attribute C_HAS_SOFTECC_OUTPUT_REGS_B : integer;
attribute C_HAS_SOFTECC_OUTPUT_REGS_B of U0 : label is 0;
attribute C_INITA_VAL : string;
attribute C_INITA_VAL of U0 : label is "0";
attribute C_INITB_VAL : string;
attribute C_INITB_VAL of U0 : label is "0";
attribute C_INIT_FILE : string;
attribute C_INIT_FILE of U0 : label is "bram_4096.mem";
attribute C_INIT_FILE_NAME : string;
attribute C_INIT_FILE_NAME of U0 : label is "bram_4096.mif";
attribute C_INTERFACE_TYPE : integer;
attribute C_INTERFACE_TYPE of U0 : label is 0;
attribute C_LOAD_INIT_FILE : integer;
attribute C_LOAD_INIT_FILE of U0 : label is 1;
attribute C_MEM_TYPE : integer;
attribute C_MEM_TYPE of U0 : label is 0;
attribute C_MUX_PIPELINE_STAGES : integer;
attribute C_MUX_PIPELINE_STAGES of U0 : label is 0;
attribute C_PRIM_TYPE : integer;
attribute C_PRIM_TYPE of U0 : label is 1;
attribute C_READ_DEPTH_A : integer;
attribute C_READ_DEPTH_A of U0 : label is 4096;
attribute C_READ_DEPTH_B : integer;
attribute C_READ_DEPTH_B of U0 : label is 4096;
attribute C_READ_WIDTH_A : integer;
attribute C_READ_WIDTH_A of U0 : label is 20;
attribute C_READ_WIDTH_B : integer;
attribute C_READ_WIDTH_B of U0 : label is 20;
attribute C_RSTRAM_A : integer;
attribute C_RSTRAM_A of U0 : label is 0;
attribute C_RSTRAM_B : integer;
attribute C_RSTRAM_B of U0 : label is 0;
attribute C_RST_PRIORITY_A : string;
attribute C_RST_PRIORITY_A of U0 : label is "CE";
attribute C_RST_PRIORITY_B : string;
attribute C_RST_PRIORITY_B of U0 : label is "CE";
attribute C_SIM_COLLISION_CHECK : string;
attribute C_SIM_COLLISION_CHECK of U0 : label is "ALL";
attribute C_USE_BRAM_BLOCK : integer;
attribute C_USE_BRAM_BLOCK of U0 : label is 0;
attribute C_USE_BYTE_WEA : integer;
attribute C_USE_BYTE_WEA of U0 : label is 0;
attribute C_USE_BYTE_WEB : integer;
attribute C_USE_BYTE_WEB of U0 : label is 0;
attribute C_USE_DEFAULT_DATA : integer;
attribute C_USE_DEFAULT_DATA of U0 : label is 1;
attribute C_USE_ECC : integer;
attribute C_USE_ECC of U0 : label is 0;
attribute C_USE_SOFTECC : integer;
attribute C_USE_SOFTECC of U0 : label is 0;
attribute C_USE_URAM : integer;
attribute C_USE_URAM of U0 : label is 0;
attribute C_WEA_WIDTH : integer;
attribute C_WEA_WIDTH of U0 : label is 1;
attribute C_WEB_WIDTH : integer;
attribute C_WEB_WIDTH of U0 : label is 1;
attribute C_WRITE_DEPTH_A : integer;
attribute C_WRITE_DEPTH_A of U0 : label is 4096;
attribute C_WRITE_DEPTH_B : integer;
attribute C_WRITE_DEPTH_B of U0 : label is 4096;
attribute C_WRITE_MODE_A : string;
attribute C_WRITE_MODE_A of U0 : label is "WRITE_FIRST";
attribute C_WRITE_MODE_B : string;
attribute C_WRITE_MODE_B of U0 : label is "WRITE_FIRST";
attribute C_WRITE_WIDTH_A : integer;
attribute C_WRITE_WIDTH_A of U0 : label is 20;
attribute C_WRITE_WIDTH_B : integer;
attribute C_WRITE_WIDTH_B of U0 : label is 20;
attribute C_XDEVICEFAMILY : string;
attribute C_XDEVICEFAMILY of U0 : label is "zynq";
attribute downgradeipidentifiedwarnings of U0 : label is "yes";
begin
U0: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5
port map (
addra(11 downto 0) => addra(11 downto 0),
addrb(11 downto 0) => B"000000000000",
clka => clka,
clkb => '0',
dbiterr => NLW_U0_dbiterr_UNCONNECTED,
deepsleep => '0',
dina(19 downto 0) => dina(19 downto 0),
dinb(19 downto 0) => B"00000000000000000000",
douta(19 downto 0) => douta(19 downto 0),
doutb(19 downto 0) => NLW_U0_doutb_UNCONNECTED(19 downto 0),
eccpipece => '0',
ena => ena,
enb => '0',
injectdbiterr => '0',
injectsbiterr => '0',
rdaddrecc(11 downto 0) => NLW_U0_rdaddrecc_UNCONNECTED(11 downto 0),
regcea => '0',
regceb => '0',
rsta => '0',
rsta_busy => NLW_U0_rsta_busy_UNCONNECTED,
rstb => '0',
rstb_busy => NLW_U0_rstb_busy_UNCONNECTED,
s_aclk => '0',
s_aresetn => '0',
s_axi_araddr(31 downto 0) => B"00000000000000000000000000000000",
s_axi_arburst(1 downto 0) => B"00",
s_axi_arid(3 downto 0) => B"0000",
s_axi_arlen(7 downto 0) => B"00000000",
s_axi_arready => NLW_U0_s_axi_arready_UNCONNECTED,
s_axi_arsize(2 downto 0) => B"000",
s_axi_arvalid => '0',
s_axi_awaddr(31 downto 0) => B"00000000000000000000000000000000",
s_axi_awburst(1 downto 0) => B"00",
s_axi_awid(3 downto 0) => B"0000",
s_axi_awlen(7 downto 0) => B"00000000",
s_axi_awready => NLW_U0_s_axi_awready_UNCONNECTED,
s_axi_awsize(2 downto 0) => B"000",
s_axi_awvalid => '0',
s_axi_bid(3 downto 0) => NLW_U0_s_axi_bid_UNCONNECTED(3 downto 0),
s_axi_bready => '0',
s_axi_bresp(1 downto 0) => NLW_U0_s_axi_bresp_UNCONNECTED(1 downto 0),
s_axi_bvalid => NLW_U0_s_axi_bvalid_UNCONNECTED,
s_axi_dbiterr => NLW_U0_s_axi_dbiterr_UNCONNECTED,
s_axi_injectdbiterr => '0',
s_axi_injectsbiterr => '0',
s_axi_rdaddrecc(11 downto 0) => NLW_U0_s_axi_rdaddrecc_UNCONNECTED(11 downto 0),
s_axi_rdata(19 downto 0) => NLW_U0_s_axi_rdata_UNCONNECTED(19 downto 0),
s_axi_rid(3 downto 0) => NLW_U0_s_axi_rid_UNCONNECTED(3 downto 0),
s_axi_rlast => NLW_U0_s_axi_rlast_UNCONNECTED,
s_axi_rready => '0',
s_axi_rresp(1 downto 0) => NLW_U0_s_axi_rresp_UNCONNECTED(1 downto 0),
s_axi_rvalid => NLW_U0_s_axi_rvalid_UNCONNECTED,
s_axi_sbiterr => NLW_U0_s_axi_sbiterr_UNCONNECTED,
s_axi_wdata(19 downto 0) => B"00000000000000000000",
s_axi_wlast => '0',
s_axi_wready => NLW_U0_s_axi_wready_UNCONNECTED,
s_axi_wstrb(0) => '0',
s_axi_wvalid => '0',
sbiterr => NLW_U0_sbiterr_UNCONNECTED,
shutdown => '0',
sleep => '0',
wea(0) => wea(0),
web(0) => '0'
);
end STRUCTURE;
| unlicense | 76c90f67703a6a077860e88e9f06f70d | 0.711353 | 3.899618 | false | false | false | false |
KaskMartin/Digiloogika_ALU | ALU_FPGA/mux.vhdl | 2 | 1,315 | ------------------------------------------------------------------------------
-- File: mux.vhd
------------------------------------------------------------------------------
--Multiplexer design
--The output is chosen based on 2 bit control signal from 4 signals with length 4 bits
--If control signal is '00' then input F1_in is chosen to the output m_o
--If '01' then input F2_in is chosen to the output m_o
--If '10' then input F3_in is chosen to the output m_o
--If '11' then input F4_in is chosen to the output m_o
library IEEE;
use IEEE.std_logic_1164.all;
--Multiplexer entity
entity Mux is
port ( m_op : in STD_LOGIC_VECTOR (1 downto 0);
F1_in : in STD_LOGIC_VECTOR (3 downto 0);
F2_in : in STD_LOGIC_VECTOR (3 downto 0);
F3_in : in STD_LOGIC_VECTOR (3 downto 0);
F4_in : in STD_LOGIC_VECTOR (3 downto 0);
m_o : out STD_LOGIC_VECTOR (3 downto 0));
end Mux;
--Architecture of the multiplexer
architecture RTL of Mux is
begin
--Behavioural process DISP_MUX
DISP_MUX: process ( F1_in, F2_in, F3_in, F4_in, m_op ) --sensitivity list
begin
case m_op is
when "00" => m_o <= F1_in;
when "01" => m_o <= F2_in;
when "10" => m_o <= F3_in;
when "11" => m_o <= F4_in;
when others => m_o <= F1_in;
end case;
end process DISP_MUX;
end RTL; | mit | d27f1a154aba6f15a15729aa3a6c383f | 0.558935 | 3.079625 | false | false | false | false |
jairov4/accel-oil | impl/impl_test_pcie/simulation/behavioral/system_ac0_plb_wrapper.vhd | 1 | 14,574 | -------------------------------------------------------------------------------
-- system_ac0_plb_wrapper.vhd
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
library plb_v46_v1_05_a;
use plb_v46_v1_05_a.all;
entity system_ac0_plb_wrapper is
port (
PLB_Clk : in std_logic;
SYS_Rst : in std_logic;
PLB_Rst : out std_logic;
SPLB_Rst : out std_logic_vector(0 to 0);
MPLB_Rst : out std_logic_vector(0 to 14);
PLB_dcrAck : out std_logic;
PLB_dcrDBus : out std_logic_vector(0 to 31);
DCR_ABus : in std_logic_vector(0 to 9);
DCR_DBus : in std_logic_vector(0 to 31);
DCR_Read : in std_logic;
DCR_Write : in std_logic;
M_ABus : in std_logic_vector(0 to 479);
M_UABus : in std_logic_vector(0 to 479);
M_BE : in std_logic_vector(0 to 119);
M_RNW : in std_logic_vector(0 to 14);
M_abort : in std_logic_vector(0 to 14);
M_busLock : in std_logic_vector(0 to 14);
M_TAttribute : in std_logic_vector(0 to 239);
M_lockErr : in std_logic_vector(0 to 14);
M_MSize : in std_logic_vector(0 to 29);
M_priority : in std_logic_vector(0 to 29);
M_rdBurst : in std_logic_vector(0 to 14);
M_request : in std_logic_vector(0 to 14);
M_size : in std_logic_vector(0 to 59);
M_type : in std_logic_vector(0 to 44);
M_wrBurst : in std_logic_vector(0 to 14);
M_wrDBus : in std_logic_vector(0 to 959);
Sl_addrAck : in std_logic_vector(0 to 0);
Sl_MRdErr : in std_logic_vector(0 to 14);
Sl_MWrErr : in std_logic_vector(0 to 14);
Sl_MBusy : in std_logic_vector(0 to 14);
Sl_rdBTerm : in std_logic_vector(0 to 0);
Sl_rdComp : in std_logic_vector(0 to 0);
Sl_rdDAck : in std_logic_vector(0 to 0);
Sl_rdDBus : in std_logic_vector(0 to 63);
Sl_rdWdAddr : in std_logic_vector(0 to 3);
Sl_rearbitrate : in std_logic_vector(0 to 0);
Sl_SSize : in std_logic_vector(0 to 1);
Sl_wait : in std_logic_vector(0 to 0);
Sl_wrBTerm : in std_logic_vector(0 to 0);
Sl_wrComp : in std_logic_vector(0 to 0);
Sl_wrDAck : in std_logic_vector(0 to 0);
Sl_MIRQ : in std_logic_vector(0 to 14);
PLB_MIRQ : out std_logic_vector(0 to 14);
PLB_ABus : out std_logic_vector(0 to 31);
PLB_UABus : out std_logic_vector(0 to 31);
PLB_BE : out std_logic_vector(0 to 7);
PLB_MAddrAck : out std_logic_vector(0 to 14);
PLB_MTimeout : out std_logic_vector(0 to 14);
PLB_MBusy : out std_logic_vector(0 to 14);
PLB_MRdErr : out std_logic_vector(0 to 14);
PLB_MWrErr : out std_logic_vector(0 to 14);
PLB_MRdBTerm : out std_logic_vector(0 to 14);
PLB_MRdDAck : out std_logic_vector(0 to 14);
PLB_MRdDBus : out std_logic_vector(0 to 959);
PLB_MRdWdAddr : out std_logic_vector(0 to 59);
PLB_MRearbitrate : out std_logic_vector(0 to 14);
PLB_MWrBTerm : out std_logic_vector(0 to 14);
PLB_MWrDAck : out std_logic_vector(0 to 14);
PLB_MSSize : out std_logic_vector(0 to 29);
PLB_PAValid : out std_logic;
PLB_RNW : out std_logic;
PLB_SAValid : out std_logic;
PLB_abort : out std_logic;
PLB_busLock : out std_logic;
PLB_TAttribute : out std_logic_vector(0 to 15);
PLB_lockErr : out std_logic;
PLB_masterID : out std_logic_vector(0 to 3);
PLB_MSize : out std_logic_vector(0 to 1);
PLB_rdPendPri : out std_logic_vector(0 to 1);
PLB_wrPendPri : out std_logic_vector(0 to 1);
PLB_rdPendReq : out std_logic;
PLB_wrPendReq : out std_logic;
PLB_rdBurst : out std_logic;
PLB_rdPrim : out std_logic_vector(0 to 0);
PLB_reqPri : out std_logic_vector(0 to 1);
PLB_size : out std_logic_vector(0 to 3);
PLB_type : out std_logic_vector(0 to 2);
PLB_wrBurst : out std_logic;
PLB_wrDBus : out std_logic_vector(0 to 63);
PLB_wrPrim : out std_logic_vector(0 to 0);
PLB_SaddrAck : out std_logic;
PLB_SMRdErr : out std_logic_vector(0 to 14);
PLB_SMWrErr : out std_logic_vector(0 to 14);
PLB_SMBusy : out std_logic_vector(0 to 14);
PLB_SrdBTerm : out std_logic;
PLB_SrdComp : out std_logic;
PLB_SrdDAck : out std_logic;
PLB_SrdDBus : out std_logic_vector(0 to 63);
PLB_SrdWdAddr : out std_logic_vector(0 to 3);
PLB_Srearbitrate : out std_logic;
PLB_Sssize : out std_logic_vector(0 to 1);
PLB_Swait : out std_logic;
PLB_SwrBTerm : out std_logic;
PLB_SwrComp : out std_logic;
PLB_SwrDAck : out std_logic;
Bus_Error_Det : out std_logic
);
end system_ac0_plb_wrapper;
architecture STRUCTURE of system_ac0_plb_wrapper is
component plb_v46 is
generic (
C_PLBV46_NUM_MASTERS : integer;
C_PLBV46_NUM_SLAVES : integer;
C_PLBV46_MID_WIDTH : integer;
C_PLBV46_AWIDTH : integer;
C_PLBV46_DWIDTH : integer;
C_DCR_INTFCE : integer;
C_BASEADDR : std_logic_vector;
C_HIGHADDR : std_logic_vector;
C_DCR_AWIDTH : integer;
C_DCR_DWIDTH : integer;
C_EXT_RESET_HIGH : integer;
C_IRQ_ACTIVE : std_logic;
C_ADDR_PIPELINING_TYPE : integer;
C_FAMILY : string;
C_P2P : integer;
C_ARB_TYPE : integer
);
port (
PLB_Clk : in std_logic;
SYS_Rst : in std_logic;
PLB_Rst : out std_logic;
SPLB_Rst : out std_logic_vector(0 to C_PLBV46_NUM_SLAVES-1);
MPLB_Rst : out std_logic_vector(0 to C_PLBV46_NUM_MASTERS-1);
PLB_dcrAck : out std_logic;
PLB_dcrDBus : out std_logic_vector(0 to C_DCR_DWIDTH-1);
DCR_ABus : in std_logic_vector(0 to C_DCR_AWIDTH-1);
DCR_DBus : in std_logic_vector(0 to C_DCR_DWIDTH-1);
DCR_Read : in std_logic;
DCR_Write : in std_logic;
M_ABus : in std_logic_vector(0 to (C_PLBV46_NUM_MASTERS*32)-1);
M_UABus : in std_logic_vector(0 to (C_PLBV46_NUM_MASTERS*32)-1);
M_BE : in std_logic_vector(0 to (C_PLBV46_NUM_MASTERS*(C_PLBV46_DWIDTH/8))-1);
M_RNW : in std_logic_vector(0 to C_PLBV46_NUM_MASTERS-1);
M_abort : in std_logic_vector(0 to C_PLBV46_NUM_MASTERS-1);
M_busLock : in std_logic_vector(0 to C_PLBV46_NUM_MASTERS-1);
M_TAttribute : in std_logic_vector(0 to (C_PLBV46_NUM_MASTERS*16)-1);
M_lockErr : in std_logic_vector(0 to C_PLBV46_NUM_MASTERS-1);
M_MSize : in std_logic_vector(0 to (C_PLBV46_NUM_MASTERS*2)-1);
M_priority : in std_logic_vector(0 to (C_PLBV46_NUM_MASTERS*2)-1);
M_rdBurst : in std_logic_vector(0 to C_PLBV46_NUM_MASTERS-1);
M_request : in std_logic_vector(0 to C_PLBV46_NUM_MASTERS-1);
M_size : in std_logic_vector(0 to (C_PLBV46_NUM_MASTERS*4)-1);
M_type : in std_logic_vector(0 to (C_PLBV46_NUM_MASTERS*3)-1);
M_wrBurst : in std_logic_vector(0 to C_PLBV46_NUM_MASTERS-1);
M_wrDBus : in std_logic_vector(0 to (C_PLBV46_NUM_MASTERS*C_PLBV46_DWIDTH)-1);
Sl_addrAck : in std_logic_vector(0 to C_PLBV46_NUM_SLAVES-1);
Sl_MRdErr : in std_logic_vector(0 to (C_PLBV46_NUM_SLAVES*C_PLBV46_NUM_MASTERS)-1);
Sl_MWrErr : in std_logic_vector(0 to (C_PLBV46_NUM_SLAVES*C_PLBV46_NUM_MASTERS)-1);
Sl_MBusy : in std_logic_vector(0 to C_PLBV46_NUM_SLAVES*C_PLBV46_NUM_MASTERS - 1 );
Sl_rdBTerm : in std_logic_vector(0 to C_PLBV46_NUM_SLAVES-1);
Sl_rdComp : in std_logic_vector(0 to C_PLBV46_NUM_SLAVES-1);
Sl_rdDAck : in std_logic_vector(0 to C_PLBV46_NUM_SLAVES-1);
Sl_rdDBus : in std_logic_vector(0 to C_PLBV46_NUM_SLAVES*C_PLBV46_DWIDTH-1);
Sl_rdWdAddr : in std_logic_vector(0 to C_PLBV46_NUM_SLAVES*4-1);
Sl_rearbitrate : in std_logic_vector(0 to C_PLBV46_NUM_SLAVES-1);
Sl_SSize : in std_logic_vector(0 to C_PLBV46_NUM_SLAVES*2-1);
Sl_wait : in std_logic_vector(0 to C_PLBV46_NUM_SLAVES-1);
Sl_wrBTerm : in std_logic_vector(0 to C_PLBV46_NUM_SLAVES-1);
Sl_wrComp : in std_logic_vector(0 to C_PLBV46_NUM_SLAVES-1);
Sl_wrDAck : in std_logic_vector(0 to C_PLBV46_NUM_SLAVES-1);
Sl_MIRQ : in std_logic_vector(0 to C_PLBV46_NUM_SLAVES*C_PLBV46_NUM_MASTERS-1);
PLB_MIRQ : out std_logic_vector(0 to C_PLBV46_NUM_MASTERS-1);
PLB_ABus : out std_logic_vector(0 to 31);
PLB_UABus : out std_logic_vector(0 to 31);
PLB_BE : out std_logic_vector(0 to (C_PLBV46_DWIDTH/8)-1);
PLB_MAddrAck : out std_logic_vector(0 to C_PLBV46_NUM_MASTERS-1);
PLB_MTimeout : out std_logic_vector(0 to C_PLBV46_NUM_MASTERS-1);
PLB_MBusy : out std_logic_vector(0 to C_PLBV46_NUM_MASTERS-1);
PLB_MRdErr : out std_logic_vector(0 to C_PLBV46_NUM_MASTERS-1);
PLB_MWrErr : out std_logic_vector(0 to C_PLBV46_NUM_MASTERS-1);
PLB_MRdBTerm : out std_logic_vector(0 to C_PLBV46_NUM_MASTERS-1);
PLB_MRdDAck : out std_logic_vector(0 to C_PLBV46_NUM_MASTERS-1);
PLB_MRdDBus : out std_logic_vector(0 to (C_PLBV46_NUM_MASTERS*C_PLBV46_DWIDTH)-1);
PLB_MRdWdAddr : out std_logic_vector(0 to (C_PLBV46_NUM_MASTERS*4)-1);
PLB_MRearbitrate : out std_logic_vector(0 to C_PLBV46_NUM_MASTERS-1);
PLB_MWrBTerm : out std_logic_vector(0 to C_PLBV46_NUM_MASTERS-1);
PLB_MWrDAck : out std_logic_vector(0 to C_PLBV46_NUM_MASTERS-1);
PLB_MSSize : out std_logic_vector(0 to (C_PLBV46_NUM_MASTERS*2)-1);
PLB_PAValid : out std_logic;
PLB_RNW : out std_logic;
PLB_SAValid : out std_logic;
PLB_abort : out std_logic;
PLB_busLock : out std_logic;
PLB_TAttribute : out std_logic_vector(0 to 15);
PLB_lockErr : out std_logic;
PLB_masterID : out std_logic_vector(0 to C_PLBV46_MID_WIDTH-1);
PLB_MSize : out std_logic_vector(0 to 1);
PLB_rdPendPri : out std_logic_vector(0 to 1);
PLB_wrPendPri : out std_logic_vector(0 to 1);
PLB_rdPendReq : out std_logic;
PLB_wrPendReq : out std_logic;
PLB_rdBurst : out std_logic;
PLB_rdPrim : out std_logic_vector(0 to C_PLBV46_NUM_SLAVES-1);
PLB_reqPri : out std_logic_vector(0 to 1);
PLB_size : out std_logic_vector(0 to 3);
PLB_type : out std_logic_vector(0 to 2);
PLB_wrBurst : out std_logic;
PLB_wrDBus : out std_logic_vector(0 to C_PLBV46_DWIDTH-1);
PLB_wrPrim : out std_logic_vector(0 to C_PLBV46_NUM_SLAVES-1);
PLB_SaddrAck : out std_logic;
PLB_SMRdErr : out std_logic_vector(0 to C_PLBV46_NUM_MASTERS-1);
PLB_SMWrErr : out std_logic_vector(0 to C_PLBV46_NUM_MASTERS-1);
PLB_SMBusy : out std_logic_vector(0 to C_PLBV46_NUM_MASTERS-1);
PLB_SrdBTerm : out std_logic;
PLB_SrdComp : out std_logic;
PLB_SrdDAck : out std_logic;
PLB_SrdDBus : out std_logic_vector(0 to C_PLBV46_DWIDTH-1);
PLB_SrdWdAddr : out std_logic_vector(0 to 3);
PLB_Srearbitrate : out std_logic;
PLB_Sssize : out std_logic_vector(0 to 1);
PLB_Swait : out std_logic;
PLB_SwrBTerm : out std_logic;
PLB_SwrComp : out std_logic;
PLB_SwrDAck : out std_logic;
Bus_Error_Det : out std_logic
);
end component;
begin
ac0_plb : plb_v46
generic map (
C_PLBV46_NUM_MASTERS => 15,
C_PLBV46_NUM_SLAVES => 1,
C_PLBV46_MID_WIDTH => 4,
C_PLBV46_AWIDTH => 32,
C_PLBV46_DWIDTH => 64,
C_DCR_INTFCE => 0,
C_BASEADDR => B"1111111111",
C_HIGHADDR => B"0000000000",
C_DCR_AWIDTH => 10,
C_DCR_DWIDTH => 32,
C_EXT_RESET_HIGH => 1,
C_IRQ_ACTIVE => '1',
C_ADDR_PIPELINING_TYPE => 1,
C_FAMILY => "virtex5",
C_P2P => 0,
C_ARB_TYPE => 0
)
port map (
PLB_Clk => PLB_Clk,
SYS_Rst => SYS_Rst,
PLB_Rst => PLB_Rst,
SPLB_Rst => SPLB_Rst,
MPLB_Rst => MPLB_Rst,
PLB_dcrAck => PLB_dcrAck,
PLB_dcrDBus => PLB_dcrDBus,
DCR_ABus => DCR_ABus,
DCR_DBus => DCR_DBus,
DCR_Read => DCR_Read,
DCR_Write => DCR_Write,
M_ABus => M_ABus,
M_UABus => M_UABus,
M_BE => M_BE,
M_RNW => M_RNW,
M_abort => M_abort,
M_busLock => M_busLock,
M_TAttribute => M_TAttribute,
M_lockErr => M_lockErr,
M_MSize => M_MSize,
M_priority => M_priority,
M_rdBurst => M_rdBurst,
M_request => M_request,
M_size => M_size,
M_type => M_type,
M_wrBurst => M_wrBurst,
M_wrDBus => M_wrDBus,
Sl_addrAck => Sl_addrAck,
Sl_MRdErr => Sl_MRdErr,
Sl_MWrErr => Sl_MWrErr,
Sl_MBusy => Sl_MBusy,
Sl_rdBTerm => Sl_rdBTerm,
Sl_rdComp => Sl_rdComp,
Sl_rdDAck => Sl_rdDAck,
Sl_rdDBus => Sl_rdDBus,
Sl_rdWdAddr => Sl_rdWdAddr,
Sl_rearbitrate => Sl_rearbitrate,
Sl_SSize => Sl_SSize,
Sl_wait => Sl_wait,
Sl_wrBTerm => Sl_wrBTerm,
Sl_wrComp => Sl_wrComp,
Sl_wrDAck => Sl_wrDAck,
Sl_MIRQ => Sl_MIRQ,
PLB_MIRQ => PLB_MIRQ,
PLB_ABus => PLB_ABus,
PLB_UABus => PLB_UABus,
PLB_BE => PLB_BE,
PLB_MAddrAck => PLB_MAddrAck,
PLB_MTimeout => PLB_MTimeout,
PLB_MBusy => PLB_MBusy,
PLB_MRdErr => PLB_MRdErr,
PLB_MWrErr => PLB_MWrErr,
PLB_MRdBTerm => PLB_MRdBTerm,
PLB_MRdDAck => PLB_MRdDAck,
PLB_MRdDBus => PLB_MRdDBus,
PLB_MRdWdAddr => PLB_MRdWdAddr,
PLB_MRearbitrate => PLB_MRearbitrate,
PLB_MWrBTerm => PLB_MWrBTerm,
PLB_MWrDAck => PLB_MWrDAck,
PLB_MSSize => PLB_MSSize,
PLB_PAValid => PLB_PAValid,
PLB_RNW => PLB_RNW,
PLB_SAValid => PLB_SAValid,
PLB_abort => PLB_abort,
PLB_busLock => PLB_busLock,
PLB_TAttribute => PLB_TAttribute,
PLB_lockErr => PLB_lockErr,
PLB_masterID => PLB_masterID,
PLB_MSize => PLB_MSize,
PLB_rdPendPri => PLB_rdPendPri,
PLB_wrPendPri => PLB_wrPendPri,
PLB_rdPendReq => PLB_rdPendReq,
PLB_wrPendReq => PLB_wrPendReq,
PLB_rdBurst => PLB_rdBurst,
PLB_rdPrim => PLB_rdPrim,
PLB_reqPri => PLB_reqPri,
PLB_size => PLB_size,
PLB_type => PLB_type,
PLB_wrBurst => PLB_wrBurst,
PLB_wrDBus => PLB_wrDBus,
PLB_wrPrim => PLB_wrPrim,
PLB_SaddrAck => PLB_SaddrAck,
PLB_SMRdErr => PLB_SMRdErr,
PLB_SMWrErr => PLB_SMWrErr,
PLB_SMBusy => PLB_SMBusy,
PLB_SrdBTerm => PLB_SrdBTerm,
PLB_SrdComp => PLB_SrdComp,
PLB_SrdDAck => PLB_SrdDAck,
PLB_SrdDBus => PLB_SrdDBus,
PLB_SrdWdAddr => PLB_SrdWdAddr,
PLB_Srearbitrate => PLB_Srearbitrate,
PLB_Sssize => PLB_Sssize,
PLB_Swait => PLB_Swait,
PLB_SwrBTerm => PLB_SwrBTerm,
PLB_SwrComp => PLB_SwrComp,
PLB_SwrDAck => PLB_SwrDAck,
Bus_Error_Det => Bus_Error_Det
);
end architecture STRUCTURE;
| lgpl-3.0 | 60066927f221e324e0b7db1f14181efa | 0.611157 | 3.041954 | false | false | false | false |
jairov4/accel-oil | solution_spartan3/syn/vhdl/sample_iterator_next.vhd | 2 | 26,409 | -- ==============================================================
-- RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2013.4
-- Copyright (C) 2013 Xilinx Inc. All rights reserved.
--
-- ===========================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity sample_iterator_next is
port (
ap_clk : IN STD_LOGIC;
ap_rst : IN STD_LOGIC;
ap_start : IN STD_LOGIC;
ap_done : OUT STD_LOGIC;
ap_idle : OUT STD_LOGIC;
ap_ready : OUT STD_LOGIC;
indices_samples_req_din : OUT STD_LOGIC;
indices_samples_req_full_n : IN STD_LOGIC;
indices_samples_req_write : OUT STD_LOGIC;
indices_samples_rsp_empty_n : IN STD_LOGIC;
indices_samples_rsp_read : OUT STD_LOGIC;
indices_samples_address : OUT STD_LOGIC_VECTOR (31 downto 0);
indices_samples_datain : IN STD_LOGIC_VECTOR (15 downto 0);
indices_samples_dataout : OUT STD_LOGIC_VECTOR (15 downto 0);
indices_samples_size : OUT STD_LOGIC_VECTOR (31 downto 0);
ap_ce : IN STD_LOGIC;
indices_begin_req_din : OUT STD_LOGIC;
indices_begin_req_full_n : IN STD_LOGIC;
indices_begin_req_write : OUT STD_LOGIC;
indices_begin_rsp_empty_n : IN STD_LOGIC;
indices_begin_rsp_read : OUT STD_LOGIC;
indices_begin_address : OUT STD_LOGIC_VECTOR (31 downto 0);
indices_begin_datain : IN STD_LOGIC_VECTOR (31 downto 0);
indices_begin_dataout : OUT STD_LOGIC_VECTOR (31 downto 0);
indices_begin_size : OUT STD_LOGIC_VECTOR (31 downto 0);
indices_stride_req_din : OUT STD_LOGIC;
indices_stride_req_full_n : IN STD_LOGIC;
indices_stride_req_write : OUT STD_LOGIC;
indices_stride_rsp_empty_n : IN STD_LOGIC;
indices_stride_rsp_read : OUT STD_LOGIC;
indices_stride_address : OUT STD_LOGIC_VECTOR (31 downto 0);
indices_stride_datain : IN STD_LOGIC_VECTOR (7 downto 0);
indices_stride_dataout : OUT STD_LOGIC_VECTOR (7 downto 0);
indices_stride_size : OUT STD_LOGIC_VECTOR (31 downto 0);
i_index : IN STD_LOGIC_VECTOR (15 downto 0);
i_sample : IN STD_LOGIC_VECTOR (15 downto 0);
ap_return_0 : OUT STD_LOGIC_VECTOR (15 downto 0);
ap_return_1 : OUT STD_LOGIC_VECTOR (15 downto 0) );
end;
architecture behav of sample_iterator_next is
constant ap_const_logic_1 : STD_LOGIC := '1';
constant ap_const_logic_0 : STD_LOGIC := '0';
constant ap_ST_pp0_stg0_fsm_0 : STD_LOGIC_VECTOR (0 downto 0) := "0";
constant ap_const_lv32_0 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000000";
constant ap_const_lv32_1 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000001";
constant ap_const_lv17_1FFFF : STD_LOGIC_VECTOR (16 downto 0) := "11111111111111111";
constant ap_const_lv16_1 : STD_LOGIC_VECTOR (15 downto 0) := "0000000000000001";
constant ap_const_lv16_0 : STD_LOGIC_VECTOR (15 downto 0) := "0000000000000000";
constant ap_const_lv8_0 : STD_LOGIC_VECTOR (7 downto 0) := "00000000";
signal ap_CS_fsm : STD_LOGIC_VECTOR (0 downto 0) := "0";
signal ap_reg_ppiten_pp0_it0 : STD_LOGIC;
signal ap_reg_ppiten_pp0_it1 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it2 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it3 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it4 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it5 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it6 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it7 : STD_LOGIC := '0';
signal i_sample_read_reg_128 : STD_LOGIC_VECTOR (15 downto 0);
signal ap_reg_ppstg_i_sample_read_reg_128_pp0_it1 : STD_LOGIC_VECTOR (15 downto 0);
signal ap_reg_ppstg_i_sample_read_reg_128_pp0_it2 : STD_LOGIC_VECTOR (15 downto 0);
signal ap_reg_ppstg_i_sample_read_reg_128_pp0_it3 : STD_LOGIC_VECTOR (15 downto 0);
signal ap_reg_ppstg_i_sample_read_reg_128_pp0_it4 : STD_LOGIC_VECTOR (15 downto 0);
signal ap_reg_ppstg_i_sample_read_reg_128_pp0_it5 : STD_LOGIC_VECTOR (15 downto 0);
signal i_index_read_reg_134 : STD_LOGIC_VECTOR (15 downto 0);
signal ap_reg_ppstg_i_index_read_reg_134_pp0_it1 : STD_LOGIC_VECTOR (15 downto 0);
signal ap_reg_ppstg_i_index_read_reg_134_pp0_it2 : STD_LOGIC_VECTOR (15 downto 0);
signal ap_reg_ppstg_i_index_read_reg_134_pp0_it3 : STD_LOGIC_VECTOR (15 downto 0);
signal ap_reg_ppstg_i_index_read_reg_134_pp0_it4 : STD_LOGIC_VECTOR (15 downto 0);
signal ap_reg_ppstg_i_index_read_reg_134_pp0_it5 : STD_LOGIC_VECTOR (15 downto 0);
signal ap_reg_ppstg_i_index_read_reg_134_pp0_it6 : STD_LOGIC_VECTOR (15 downto 0);
signal indices_samples_addr_read_reg_145 : STD_LOGIC_VECTOR (15 downto 0);
signal grp_fu_77_p2 : STD_LOGIC_VECTOR (16 downto 0);
signal tmp_s_reg_155 : STD_LOGIC_VECTOR (16 downto 0);
signal tmp_1_fu_99_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_1_reg_160 : STD_LOGIC_VECTOR (0 downto 0);
signal grp_fu_83_p2 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_3_reg_166 : STD_LOGIC_VECTOR (15 downto 0);
signal grp_fu_88_p2 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_2_reg_171 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_8_fu_63_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_77_p0 : STD_LOGIC_VECTOR (16 downto 0);
signal grp_fu_77_p1 : STD_LOGIC_VECTOR (16 downto 0);
signal grp_fu_83_p0 : STD_LOGIC_VECTOR (15 downto 0);
signal grp_fu_83_p1 : STD_LOGIC_VECTOR (15 downto 0);
signal grp_fu_88_p0 : STD_LOGIC_VECTOR (15 downto 0);
signal grp_fu_88_p1 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_cast_fu_93_p1 : STD_LOGIC_VECTOR (17 downto 0);
signal tmp_1_fu_99_p1 : STD_LOGIC_VECTOR (17 downto 0);
signal tmp_s_reg_155_temp: signed (17-1 downto 0);
signal agg_result_index_write_assign_fu_111_p3 : STD_LOGIC_VECTOR (15 downto 0);
signal agg_result_sample_write_assign_fu_105_p3 : STD_LOGIC_VECTOR (15 downto 0);
signal grp_fu_77_ce : STD_LOGIC;
signal grp_fu_83_ce : STD_LOGIC;
signal grp_fu_88_ce : STD_LOGIC;
signal ap_NS_fsm : STD_LOGIC_VECTOR (0 downto 0);
signal ap_sig_pprstidle_pp0 : STD_LOGIC;
component nfa_accept_samples_generic_hw_add_17ns_17s_17_4 IS
generic (
ID : INTEGER;
NUM_STAGE : INTEGER;
din0_WIDTH : INTEGER;
din1_WIDTH : INTEGER;
dout_WIDTH : INTEGER );
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
din0 : IN STD_LOGIC_VECTOR (16 downto 0);
din1 : IN STD_LOGIC_VECTOR (16 downto 0);
ce : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR (16 downto 0) );
end component;
component nfa_accept_samples_generic_hw_add_16ns_16ns_16_4 IS
generic (
ID : INTEGER;
NUM_STAGE : INTEGER;
din0_WIDTH : INTEGER;
din1_WIDTH : INTEGER;
dout_WIDTH : INTEGER );
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
din0 : IN STD_LOGIC_VECTOR (15 downto 0);
din1 : IN STD_LOGIC_VECTOR (15 downto 0);
ce : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR (15 downto 0) );
end component;
begin
nfa_accept_samples_generic_hw_add_17ns_17s_17_4_U30 : component nfa_accept_samples_generic_hw_add_17ns_17s_17_4
generic map (
ID => 30,
NUM_STAGE => 4,
din0_WIDTH => 17,
din1_WIDTH => 17,
dout_WIDTH => 17)
port map (
clk => ap_clk,
reset => ap_rst,
din0 => grp_fu_77_p0,
din1 => grp_fu_77_p1,
ce => grp_fu_77_ce,
dout => grp_fu_77_p2);
nfa_accept_samples_generic_hw_add_16ns_16ns_16_4_U31 : component nfa_accept_samples_generic_hw_add_16ns_16ns_16_4
generic map (
ID => 31,
NUM_STAGE => 4,
din0_WIDTH => 16,
din1_WIDTH => 16,
dout_WIDTH => 16)
port map (
clk => ap_clk,
reset => ap_rst,
din0 => grp_fu_83_p0,
din1 => grp_fu_83_p1,
ce => grp_fu_83_ce,
dout => grp_fu_83_p2);
nfa_accept_samples_generic_hw_add_16ns_16ns_16_4_U32 : component nfa_accept_samples_generic_hw_add_16ns_16ns_16_4
generic map (
ID => 32,
NUM_STAGE => 4,
din0_WIDTH => 16,
din1_WIDTH => 16,
dout_WIDTH => 16)
port map (
clk => ap_clk,
reset => ap_rst,
din0 => grp_fu_88_p0,
din1 => grp_fu_88_p1,
ce => grp_fu_88_ce,
dout => grp_fu_88_p2);
-- the current state (ap_CS_fsm) of the state machine. --
ap_CS_fsm_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_CS_fsm <= ap_ST_pp0_stg0_fsm_0;
else
ap_CS_fsm <= ap_NS_fsm;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it1 assign process. --
ap_reg_ppiten_pp0_it1_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_reg_ppiten_pp0_it1 <= ap_const_logic_0;
else
if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and (indices_samples_rsp_empty_n = ap_const_logic_0)) or not((ap_const_logic_1 = ap_ce)))))) then
ap_reg_ppiten_pp0_it1 <= ap_reg_ppiten_pp0_it0;
end if;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it2 assign process. --
ap_reg_ppiten_pp0_it2_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_reg_ppiten_pp0_it2 <= ap_const_logic_0;
else
if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and (indices_samples_rsp_empty_n = ap_const_logic_0)) or not((ap_const_logic_1 = ap_ce)))))) then
ap_reg_ppiten_pp0_it2 <= ap_reg_ppiten_pp0_it1;
end if;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it3 assign process. --
ap_reg_ppiten_pp0_it3_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_reg_ppiten_pp0_it3 <= ap_const_logic_0;
else
if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and (indices_samples_rsp_empty_n = ap_const_logic_0)) or not((ap_const_logic_1 = ap_ce)))))) then
ap_reg_ppiten_pp0_it3 <= ap_reg_ppiten_pp0_it2;
end if;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it4 assign process. --
ap_reg_ppiten_pp0_it4_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_reg_ppiten_pp0_it4 <= ap_const_logic_0;
else
if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and (indices_samples_rsp_empty_n = ap_const_logic_0)) or not((ap_const_logic_1 = ap_ce)))))) then
ap_reg_ppiten_pp0_it4 <= ap_reg_ppiten_pp0_it3;
end if;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it5 assign process. --
ap_reg_ppiten_pp0_it5_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_reg_ppiten_pp0_it5 <= ap_const_logic_0;
else
if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and (indices_samples_rsp_empty_n = ap_const_logic_0)) or not((ap_const_logic_1 = ap_ce)))))) then
ap_reg_ppiten_pp0_it5 <= ap_reg_ppiten_pp0_it4;
end if;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it6 assign process. --
ap_reg_ppiten_pp0_it6_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_reg_ppiten_pp0_it6 <= ap_const_logic_0;
else
if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and (indices_samples_rsp_empty_n = ap_const_logic_0)) or not((ap_const_logic_1 = ap_ce)))))) then
ap_reg_ppiten_pp0_it6 <= ap_reg_ppiten_pp0_it5;
end if;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it7 assign process. --
ap_reg_ppiten_pp0_it7_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_reg_ppiten_pp0_it7 <= ap_const_logic_0;
else
if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and (indices_samples_rsp_empty_n = ap_const_logic_0)) or not((ap_const_logic_1 = ap_ce)))))) then
ap_reg_ppiten_pp0_it7 <= ap_reg_ppiten_pp0_it6;
end if;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and (indices_samples_rsp_empty_n = ap_const_logic_0)))) and (ap_const_logic_1 = ap_ce))) then
ap_reg_ppstg_i_index_read_reg_134_pp0_it1 <= i_index_read_reg_134;
ap_reg_ppstg_i_index_read_reg_134_pp0_it2 <= ap_reg_ppstg_i_index_read_reg_134_pp0_it1;
ap_reg_ppstg_i_index_read_reg_134_pp0_it3 <= ap_reg_ppstg_i_index_read_reg_134_pp0_it2;
ap_reg_ppstg_i_index_read_reg_134_pp0_it4 <= ap_reg_ppstg_i_index_read_reg_134_pp0_it3;
ap_reg_ppstg_i_index_read_reg_134_pp0_it5 <= ap_reg_ppstg_i_index_read_reg_134_pp0_it4;
ap_reg_ppstg_i_index_read_reg_134_pp0_it6 <= ap_reg_ppstg_i_index_read_reg_134_pp0_it5;
ap_reg_ppstg_i_sample_read_reg_128_pp0_it1 <= i_sample_read_reg_128;
ap_reg_ppstg_i_sample_read_reg_128_pp0_it2 <= ap_reg_ppstg_i_sample_read_reg_128_pp0_it1;
ap_reg_ppstg_i_sample_read_reg_128_pp0_it3 <= ap_reg_ppstg_i_sample_read_reg_128_pp0_it2;
ap_reg_ppstg_i_sample_read_reg_128_pp0_it4 <= ap_reg_ppstg_i_sample_read_reg_128_pp0_it3;
ap_reg_ppstg_i_sample_read_reg_128_pp0_it5 <= ap_reg_ppstg_i_sample_read_reg_128_pp0_it4;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and (indices_samples_rsp_empty_n = ap_const_logic_0)))) and (ap_const_logic_1 = ap_ce))) then
i_index_read_reg_134 <= i_index;
i_sample_read_reg_128 <= i_sample;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and (indices_samples_rsp_empty_n = ap_const_logic_0)))) and (ap_const_logic_1 = ap_ce))) then
indices_samples_addr_read_reg_145 <= indices_samples_datain;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it6) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and (indices_samples_rsp_empty_n = ap_const_logic_0)))) and (ap_const_logic_1 = ap_ce))) then
tmp_1_reg_160 <= tmp_1_fu_99_p2;
tmp_2_reg_171 <= grp_fu_88_p2;
tmp_3_reg_166 <= grp_fu_83_p2;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it5) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and (indices_samples_rsp_empty_n = ap_const_logic_0)))) and (ap_const_logic_1 = ap_ce))) then
tmp_s_reg_155 <= grp_fu_77_p2;
end if;
end if;
end process;
-- the next state (ap_NS_fsm) of the state machine. --
ap_NS_fsm_assign_proc : process (ap_start , ap_CS_fsm , ap_reg_ppiten_pp0_it0 , ap_reg_ppiten_pp0_it1 , indices_samples_rsp_empty_n , ap_ce , ap_sig_pprstidle_pp0)
begin
case ap_CS_fsm is
when ap_ST_pp0_stg0_fsm_0 =>
ap_NS_fsm <= ap_ST_pp0_stg0_fsm_0;
when others =>
ap_NS_fsm <= "X";
end case;
end process;
agg_result_index_write_assign_fu_111_p3 <=
ap_reg_ppstg_i_index_read_reg_134_pp0_it6 when (tmp_1_reg_160(0) = '1') else
tmp_3_reg_166;
agg_result_sample_write_assign_fu_105_p3 <=
tmp_2_reg_171 when (tmp_1_reg_160(0) = '1') else
ap_const_lv16_0;
-- ap_done assign process. --
ap_done_assign_proc : process(ap_start, ap_CS_fsm, ap_reg_ppiten_pp0_it0, ap_reg_ppiten_pp0_it1, ap_reg_ppiten_pp0_it7, indices_samples_rsp_empty_n, ap_ce)
begin
if (((not((ap_const_logic_1 = ap_start)) and (ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it0)) or ((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it7) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and (indices_samples_rsp_empty_n = ap_const_logic_0)))) and (ap_const_logic_1 = ap_ce)))) then
ap_done <= ap_const_logic_1;
else
ap_done <= ap_const_logic_0;
end if;
end process;
-- ap_idle assign process. --
ap_idle_assign_proc : process(ap_start, ap_CS_fsm, ap_reg_ppiten_pp0_it0, ap_reg_ppiten_pp0_it1, ap_reg_ppiten_pp0_it2, ap_reg_ppiten_pp0_it3, ap_reg_ppiten_pp0_it4, ap_reg_ppiten_pp0_it5, ap_reg_ppiten_pp0_it6, ap_reg_ppiten_pp0_it7)
begin
if ((not((ap_const_logic_1 = ap_start)) and (ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it0) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it1) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it2) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it3) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it4) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it5) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it6) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it7))) then
ap_idle <= ap_const_logic_1;
else
ap_idle <= ap_const_logic_0;
end if;
end process;
-- ap_ready assign process. --
ap_ready_assign_proc : process(ap_start, ap_CS_fsm, ap_reg_ppiten_pp0_it0, ap_reg_ppiten_pp0_it1, indices_samples_rsp_empty_n, ap_ce)
begin
if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and (indices_samples_rsp_empty_n = ap_const_logic_0)))) and (ap_const_logic_1 = ap_ce))) then
ap_ready <= ap_const_logic_1;
else
ap_ready <= ap_const_logic_0;
end if;
end process;
ap_reg_ppiten_pp0_it0 <= ap_start;
ap_return_0 <= agg_result_index_write_assign_fu_111_p3;
ap_return_1 <= agg_result_sample_write_assign_fu_105_p3;
-- ap_sig_pprstidle_pp0 assign process. --
ap_sig_pprstidle_pp0_assign_proc : process(ap_start, ap_reg_ppiten_pp0_it0, ap_reg_ppiten_pp0_it1, ap_reg_ppiten_pp0_it2, ap_reg_ppiten_pp0_it3, ap_reg_ppiten_pp0_it4, ap_reg_ppiten_pp0_it5, ap_reg_ppiten_pp0_it6)
begin
if (((ap_const_logic_0 = ap_reg_ppiten_pp0_it0) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it1) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it2) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it3) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it4) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it5) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it6) and (ap_const_logic_0 = ap_start))) then
ap_sig_pprstidle_pp0 <= ap_const_logic_1;
else
ap_sig_pprstidle_pp0 <= ap_const_logic_0;
end if;
end process;
-- grp_fu_77_ce assign process. --
grp_fu_77_ce_assign_proc : process(ap_start, ap_CS_fsm, ap_reg_ppiten_pp0_it0, ap_reg_ppiten_pp0_it1, indices_samples_rsp_empty_n, ap_ce)
begin
if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and (indices_samples_rsp_empty_n = ap_const_logic_0)))) and (ap_const_logic_1 = ap_ce))) then
grp_fu_77_ce <= ap_const_logic_1;
else
grp_fu_77_ce <= ap_const_logic_0;
end if;
end process;
grp_fu_77_p0 <= std_logic_vector(resize(unsigned(indices_samples_addr_read_reg_145),17));
grp_fu_77_p1 <= ap_const_lv17_1FFFF;
-- grp_fu_83_ce assign process. --
grp_fu_83_ce_assign_proc : process(ap_start, ap_CS_fsm, ap_reg_ppiten_pp0_it0, ap_reg_ppiten_pp0_it1, indices_samples_rsp_empty_n, ap_ce)
begin
if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and (indices_samples_rsp_empty_n = ap_const_logic_0)))) and (ap_const_logic_1 = ap_ce))) then
grp_fu_83_ce <= ap_const_logic_1;
else
grp_fu_83_ce <= ap_const_logic_0;
end if;
end process;
grp_fu_83_p0 <= ap_reg_ppstg_i_index_read_reg_134_pp0_it2;
grp_fu_83_p1 <= ap_const_lv16_1;
-- grp_fu_88_ce assign process. --
grp_fu_88_ce_assign_proc : process(ap_start, ap_CS_fsm, ap_reg_ppiten_pp0_it0, ap_reg_ppiten_pp0_it1, indices_samples_rsp_empty_n, ap_ce)
begin
if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and (indices_samples_rsp_empty_n = ap_const_logic_0)))) and (ap_const_logic_1 = ap_ce))) then
grp_fu_88_ce <= ap_const_logic_1;
else
grp_fu_88_ce <= ap_const_logic_0;
end if;
end process;
grp_fu_88_p0 <= ap_reg_ppstg_i_sample_read_reg_128_pp0_it2;
grp_fu_88_p1 <= ap_const_lv16_1;
indices_begin_address <= ap_const_lv32_0;
indices_begin_dataout <= ap_const_lv32_0;
indices_begin_req_din <= ap_const_logic_0;
indices_begin_req_write <= ap_const_logic_0;
indices_begin_rsp_read <= ap_const_logic_0;
indices_begin_size <= ap_const_lv32_0;
indices_samples_address <= tmp_8_fu_63_p1;
indices_samples_dataout <= ap_const_lv16_0;
indices_samples_req_din <= ap_const_logic_0;
-- indices_samples_req_write assign process. --
indices_samples_req_write_assign_proc : process(ap_start, ap_CS_fsm, ap_reg_ppiten_pp0_it0, ap_reg_ppiten_pp0_it1, indices_samples_rsp_empty_n, ap_ce)
begin
if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and (indices_samples_rsp_empty_n = ap_const_logic_0)))) and (ap_const_logic_1 = ap_ce))) then
indices_samples_req_write <= ap_const_logic_1;
else
indices_samples_req_write <= ap_const_logic_0;
end if;
end process;
-- indices_samples_rsp_read assign process. --
indices_samples_rsp_read_assign_proc : process(ap_start, ap_CS_fsm, ap_reg_ppiten_pp0_it0, ap_reg_ppiten_pp0_it1, indices_samples_rsp_empty_n, ap_ce)
begin
if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and (indices_samples_rsp_empty_n = ap_const_logic_0)))) and (ap_const_logic_1 = ap_ce))) then
indices_samples_rsp_read <= ap_const_logic_1;
else
indices_samples_rsp_read <= ap_const_logic_0;
end if;
end process;
indices_samples_size <= ap_const_lv32_1;
indices_stride_address <= ap_const_lv32_0;
indices_stride_dataout <= ap_const_lv8_0;
indices_stride_req_din <= ap_const_logic_0;
indices_stride_req_write <= ap_const_logic_0;
indices_stride_rsp_read <= ap_const_logic_0;
indices_stride_size <= ap_const_lv32_0;
tmp_s_reg_155_temp <= signed(tmp_s_reg_155);
tmp_1_fu_99_p1 <= std_logic_vector(resize(tmp_s_reg_155_temp,18));
tmp_1_fu_99_p2 <= "1" when (signed(tmp_cast_fu_93_p1) < signed(tmp_1_fu_99_p1)) else "0";
tmp_8_fu_63_p1 <= std_logic_vector(resize(unsigned(i_index),32));
tmp_cast_fu_93_p1 <= std_logic_vector(resize(unsigned(ap_reg_ppstg_i_sample_read_reg_128_pp0_it5),18));
end behav;
| lgpl-3.0 | 182537e888cdaa97d49c188d30f92578 | 0.600439 | 2.741514 | false | false | false | false |
jairov4/accel-oil | solution_kintex7/sim/vhdl/nfa_accept_samples_generic_hw.autotb.vhd | 1 | 99,901 | -- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2013.4
-- Copyright (C) 2013 Xilinx Inc. All rights reserved.
--
-- ==============================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
use IEEE.numeric_std.all;
use ieee.std_logic_textio.all;
use std.textio.all;
library work;
use work.all;
entity apatb_nfa_accept_samples_generic_hw_top is
generic (
AUTOTB_CLOCK_PERIOD : TIME := 2.000000 ns;
AUTOTB_TVIN_nfa_initials_buckets : STRING := "../tv/cdatafile/c.nfa_accept_samples_generic_hw.autotvin_nfa_initials_buckets.dat";
AUTOTB_TVIN_nfa_finals_buckets : STRING := "../tv/cdatafile/c.nfa_accept_samples_generic_hw.autotvin_nfa_finals_buckets.dat";
AUTOTB_TVIN_nfa_forward_buckets : STRING := "../tv/cdatafile/c.nfa_accept_samples_generic_hw.autotvin_nfa_forward_buckets.dat";
AUTOTB_TVIN_nfa_symbols : STRING := "../tv/cdatafile/c.nfa_accept_samples_generic_hw.autotvin_nfa_symbols.dat";
AUTOTB_TVIN_sample_buffer : STRING := "../tv/cdatafile/c.nfa_accept_samples_generic_hw.autotvin_sample_buffer.dat";
AUTOTB_TVIN_sample_buffer_length : STRING := "../tv/cdatafile/c.nfa_accept_samples_generic_hw.autotvin_sample_buffer_length.dat";
AUTOTB_TVIN_sample_length : STRING := "../tv/cdatafile/c.nfa_accept_samples_generic_hw.autotvin_sample_length.dat";
AUTOTB_TVIN_indices_begin : STRING := "../tv/cdatafile/c.nfa_accept_samples_generic_hw.autotvin_indices_begin.dat";
AUTOTB_TVIN_indices_samples : STRING := "../tv/cdatafile/c.nfa_accept_samples_generic_hw.autotvin_indices_samples.dat";
AUTOTB_TVIN_indices_stride : STRING := "../tv/cdatafile/c.nfa_accept_samples_generic_hw.autotvin_indices_stride.dat";
AUTOTB_TVIN_begin_index : STRING := "../tv/cdatafile/c.nfa_accept_samples_generic_hw.autotvin_begin_index.dat";
AUTOTB_TVIN_begin_sample : STRING := "../tv/cdatafile/c.nfa_accept_samples_generic_hw.autotvin_begin_sample.dat";
AUTOTB_TVIN_end_index : STRING := "../tv/cdatafile/c.nfa_accept_samples_generic_hw.autotvin_end_index.dat";
AUTOTB_TVIN_end_sample : STRING := "../tv/cdatafile/c.nfa_accept_samples_generic_hw.autotvin_end_sample.dat";
AUTOTB_TVIN_stop_on_first : STRING := "../tv/cdatafile/c.nfa_accept_samples_generic_hw.autotvin_stop_on_first.dat";
AUTOTB_TVIN_accept : STRING := "../tv/cdatafile/c.nfa_accept_samples_generic_hw.autotvin_accept.dat";
AUTOTB_TVIN_nfa_initials_buckets_out_wrapc : STRING := "../tv/rtldatafile/rtl.nfa_accept_samples_generic_hw.autotvin_nfa_initials_buckets.dat";
AUTOTB_TVIN_nfa_finals_buckets_out_wrapc : STRING := "../tv/rtldatafile/rtl.nfa_accept_samples_generic_hw.autotvin_nfa_finals_buckets.dat";
AUTOTB_TVIN_nfa_forward_buckets_out_wrapc : STRING := "../tv/rtldatafile/rtl.nfa_accept_samples_generic_hw.autotvin_nfa_forward_buckets.dat";
AUTOTB_TVIN_nfa_symbols_out_wrapc : STRING := "../tv/rtldatafile/rtl.nfa_accept_samples_generic_hw.autotvin_nfa_symbols.dat";
AUTOTB_TVIN_sample_buffer_out_wrapc : STRING := "../tv/rtldatafile/rtl.nfa_accept_samples_generic_hw.autotvin_sample_buffer.dat";
AUTOTB_TVIN_sample_buffer_length_out_wrapc : STRING := "../tv/rtldatafile/rtl.nfa_accept_samples_generic_hw.autotvin_sample_buffer_length.dat";
AUTOTB_TVIN_sample_length_out_wrapc : STRING := "../tv/rtldatafile/rtl.nfa_accept_samples_generic_hw.autotvin_sample_length.dat";
AUTOTB_TVIN_indices_begin_out_wrapc : STRING := "../tv/rtldatafile/rtl.nfa_accept_samples_generic_hw.autotvin_indices_begin.dat";
AUTOTB_TVIN_indices_samples_out_wrapc : STRING := "../tv/rtldatafile/rtl.nfa_accept_samples_generic_hw.autotvin_indices_samples.dat";
AUTOTB_TVIN_indices_stride_out_wrapc : STRING := "../tv/rtldatafile/rtl.nfa_accept_samples_generic_hw.autotvin_indices_stride.dat";
AUTOTB_TVIN_begin_index_out_wrapc : STRING := "../tv/rtldatafile/rtl.nfa_accept_samples_generic_hw.autotvin_begin_index.dat";
AUTOTB_TVIN_begin_sample_out_wrapc : STRING := "../tv/rtldatafile/rtl.nfa_accept_samples_generic_hw.autotvin_begin_sample.dat";
AUTOTB_TVIN_end_index_out_wrapc : STRING := "../tv/rtldatafile/rtl.nfa_accept_samples_generic_hw.autotvin_end_index.dat";
AUTOTB_TVIN_end_sample_out_wrapc : STRING := "../tv/rtldatafile/rtl.nfa_accept_samples_generic_hw.autotvin_end_sample.dat";
AUTOTB_TVIN_stop_on_first_out_wrapc : STRING := "../tv/rtldatafile/rtl.nfa_accept_samples_generic_hw.autotvin_stop_on_first.dat";
AUTOTB_TVIN_accept_out_wrapc : STRING := "../tv/rtldatafile/rtl.nfa_accept_samples_generic_hw.autotvin_accept.dat";
AUTOTB_TVOUT_ap_return : STRING := "../tv/cdatafile/c.nfa_accept_samples_generic_hw.autotvout_ap_return.dat";
AUTOTB_TVOUT_ap_return_out_wrapc : STRING := "../tv/rtldatafile/rtl.nfa_accept_samples_generic_hw.autotvout_ap_return.dat";
AUTOTB_LAT_RESULT_FILE : STRING := "nfa_accept_samples_generic_hw.result.lat.rb";
AUTOTB_PER_RESULT_TRANS_FILE : STRING := "nfa_accept_samples_generic_hw.performance.result.transaction.xml";
LENGTH_nfa_initials_buckets : INTEGER := 2;
LENGTH_nfa_finals_buckets : INTEGER := 2;
LENGTH_nfa_forward_buckets : INTEGER := 10;
LENGTH_nfa_symbols : INTEGER := 1;
LENGTH_sample_buffer : INTEGER := 10;
LENGTH_sample_buffer_length : INTEGER := 1;
LENGTH_sample_length : INTEGER := 1;
LENGTH_indices_begin : INTEGER := 10;
LENGTH_indices_samples : INTEGER := 10;
LENGTH_indices_stride : INTEGER := 10;
LENGTH_begin_index : INTEGER := 1;
LENGTH_begin_sample : INTEGER := 1;
LENGTH_end_index : INTEGER := 1;
LENGTH_end_sample : INTEGER := 1;
LENGTH_stop_on_first : INTEGER := 1;
LENGTH_accept : INTEGER := 1;
LENGTH_ap_return : INTEGER := 1;
AUTOTB_TRANSACTION_NUM : INTEGER := 4
);
end apatb_nfa_accept_samples_generic_hw_top;
architecture behav of apatb_nfa_accept_samples_generic_hw_top is
signal AESL_clock : STD_LOGIC := '0';
signal rst : STD_LOGIC;
signal start : STD_LOGIC := '0';
signal ce : STD_LOGIC;
signal continue : STD_LOGIC := '0';
signal AESL_reset : STD_LOGIC := '0';
signal AESL_start : STD_LOGIC := '0';
signal AESL_ce : STD_LOGIC := '0';
signal AESL_continue : STD_LOGIC := '0';
signal AESL_ready : STD_LOGIC := '0';
signal AESL_idle : STD_LOGIC := '0';
signal AESL_done : STD_LOGIC := '0';
signal AESL_done_delay : STD_LOGIC := '0';
signal AESL_done_delay2 : STD_LOGIC := '0';
signal AESL_ready_delay : STD_LOGIC := '0';
signal ready : STD_LOGIC := '0';
signal ready_wire : STD_LOGIC := '0';
signal ap_clk : STD_LOGIC;
signal ap_rst : STD_LOGIC;
signal ap_start : STD_LOGIC;
signal ap_done : STD_LOGIC;
signal ap_idle : STD_LOGIC;
signal ap_ready : STD_LOGIC;
signal nfa_initials_buckets_req_din : STD_LOGIC;
signal nfa_initials_buckets_req_full_n : STD_LOGIC;
signal nfa_initials_buckets_req_write : STD_LOGIC;
signal nfa_initials_buckets_rsp_empty_n : STD_LOGIC;
signal nfa_initials_buckets_rsp_read : STD_LOGIC;
signal nfa_initials_buckets_address : STD_LOGIC_VECTOR (31 DOWNTO 0);
signal nfa_initials_buckets_datain : STD_LOGIC_VECTOR (31 DOWNTO 0);
signal nfa_initials_buckets_dataout : STD_LOGIC_VECTOR (31 DOWNTO 0);
signal nfa_initials_buckets_size : STD_LOGIC_VECTOR (31 DOWNTO 0);
signal nfa_finals_buckets_req_din : STD_LOGIC;
signal nfa_finals_buckets_req_full_n : STD_LOGIC;
signal nfa_finals_buckets_req_write : STD_LOGIC;
signal nfa_finals_buckets_rsp_empty_n : STD_LOGIC;
signal nfa_finals_buckets_rsp_read : STD_LOGIC;
signal nfa_finals_buckets_address : STD_LOGIC_VECTOR (31 DOWNTO 0);
signal nfa_finals_buckets_datain : STD_LOGIC_VECTOR (31 DOWNTO 0);
signal nfa_finals_buckets_dataout : STD_LOGIC_VECTOR (31 DOWNTO 0);
signal nfa_finals_buckets_size : STD_LOGIC_VECTOR (31 DOWNTO 0);
signal nfa_forward_buckets_req_din : STD_LOGIC;
signal nfa_forward_buckets_req_full_n : STD_LOGIC;
signal nfa_forward_buckets_req_write : STD_LOGIC;
signal nfa_forward_buckets_rsp_empty_n : STD_LOGIC;
signal nfa_forward_buckets_rsp_read : STD_LOGIC;
signal nfa_forward_buckets_address : STD_LOGIC_VECTOR (31 DOWNTO 0);
signal nfa_forward_buckets_datain : STD_LOGIC_VECTOR (31 DOWNTO 0);
signal nfa_forward_buckets_dataout : STD_LOGIC_VECTOR (31 DOWNTO 0);
signal nfa_forward_buckets_size : STD_LOGIC_VECTOR (31 DOWNTO 0);
signal nfa_symbols : STD_LOGIC_VECTOR (7 DOWNTO 0);
signal sample_buffer_req_din : STD_LOGIC;
signal sample_buffer_req_full_n : STD_LOGIC;
signal sample_buffer_req_write : STD_LOGIC;
signal sample_buffer_rsp_empty_n : STD_LOGIC;
signal sample_buffer_rsp_read : STD_LOGIC;
signal sample_buffer_address : STD_LOGIC_VECTOR (31 DOWNTO 0);
signal sample_buffer_datain : STD_LOGIC_VECTOR (7 DOWNTO 0);
signal sample_buffer_dataout : STD_LOGIC_VECTOR (7 DOWNTO 0);
signal sample_buffer_size : STD_LOGIC_VECTOR (31 DOWNTO 0);
signal sample_buffer_length : STD_LOGIC_VECTOR (31 DOWNTO 0);
signal sample_length : STD_LOGIC_VECTOR (15 DOWNTO 0);
signal indices_begin_req_din : STD_LOGIC;
signal indices_begin_req_full_n : STD_LOGIC;
signal indices_begin_req_write : STD_LOGIC;
signal indices_begin_rsp_empty_n : STD_LOGIC;
signal indices_begin_rsp_read : STD_LOGIC;
signal indices_begin_address : STD_LOGIC_VECTOR (31 DOWNTO 0);
signal indices_begin_datain : STD_LOGIC_VECTOR (31 DOWNTO 0);
signal indices_begin_dataout : STD_LOGIC_VECTOR (31 DOWNTO 0);
signal indices_begin_size : STD_LOGIC_VECTOR (31 DOWNTO 0);
signal indices_samples_req_din : STD_LOGIC;
signal indices_samples_req_full_n : STD_LOGIC;
signal indices_samples_req_write : STD_LOGIC;
signal indices_samples_rsp_empty_n : STD_LOGIC;
signal indices_samples_rsp_read : STD_LOGIC;
signal indices_samples_address : STD_LOGIC_VECTOR (31 DOWNTO 0);
signal indices_samples_datain : STD_LOGIC_VECTOR (15 DOWNTO 0);
signal indices_samples_dataout : STD_LOGIC_VECTOR (15 DOWNTO 0);
signal indices_samples_size : STD_LOGIC_VECTOR (31 DOWNTO 0);
signal indices_stride_req_din : STD_LOGIC;
signal indices_stride_req_full_n : STD_LOGIC;
signal indices_stride_req_write : STD_LOGIC;
signal indices_stride_rsp_empty_n : STD_LOGIC;
signal indices_stride_rsp_read : STD_LOGIC;
signal indices_stride_address : STD_LOGIC_VECTOR (31 DOWNTO 0);
signal indices_stride_datain : STD_LOGIC_VECTOR (7 DOWNTO 0);
signal indices_stride_dataout : STD_LOGIC_VECTOR (7 DOWNTO 0);
signal indices_stride_size : STD_LOGIC_VECTOR (31 DOWNTO 0);
signal i_size : STD_LOGIC_VECTOR (15 DOWNTO 0);
signal begin_index : STD_LOGIC_VECTOR (15 DOWNTO 0);
signal begin_sample : STD_LOGIC_VECTOR (15 DOWNTO 0);
signal end_index : STD_LOGIC_VECTOR (15 DOWNTO 0);
signal end_sample : STD_LOGIC_VECTOR (15 DOWNTO 0);
signal stop_on_first : STD_LOGIC_VECTOR (0 DOWNTO 0);
signal accept : STD_LOGIC_VECTOR (0 DOWNTO 0);
signal ap_return : STD_LOGIC_VECTOR (31 DOWNTO 0);
shared variable AESL_ready_cnt : INTEGER := 0;
shared variable ready_cnt : INTEGER := 0;
shared variable done_cnt : INTEGER := 0;
signal ready_initial : STD_LOGIC;
signal ready_initial_n : STD_LOGIC;
signal ready_last_n : STD_LOGIC;
signal ready_delay_last_n : STD_LOGIC;
signal done_delay_last_n : STD_LOGIC;
signal interface_done : STD_LOGIC := '0';
-- Subtype for random state number, to prevent confusing it with true integers
-- Top of range should be (2**31)-1 but this literal calculation causes overflow on 32-bit machines
subtype T_RANDINT is integer range 1 to integer'high;
type latency_record is array(0 to AUTOTB_TRANSACTION_NUM + 1) of INTEGER;
shared variable AESL_mLatCnterIn : latency_record;
shared variable AESL_mLatCnterOut : latency_record;
shared variable AESL_mLatCnterIn_addr : INTEGER;
shared variable AESL_mLatCnterOut_addr : INTEGER;
shared variable AESL_clk_counter : INTEGER;
component nfa_accept_samples_generic_hw is
port (
ap_clk : IN STD_LOGIC;
ap_rst : IN STD_LOGIC;
ap_start : IN STD_LOGIC;
ap_done : OUT STD_LOGIC;
ap_idle : OUT STD_LOGIC;
ap_ready : OUT STD_LOGIC;
nfa_initials_buckets_req_din : OUT STD_LOGIC;
nfa_initials_buckets_req_full_n : IN STD_LOGIC;
nfa_initials_buckets_req_write : OUT STD_LOGIC;
nfa_initials_buckets_rsp_empty_n : IN STD_LOGIC;
nfa_initials_buckets_rsp_read : OUT STD_LOGIC;
nfa_initials_buckets_address : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
nfa_initials_buckets_datain : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
nfa_initials_buckets_dataout : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
nfa_initials_buckets_size : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
nfa_finals_buckets_req_din : OUT STD_LOGIC;
nfa_finals_buckets_req_full_n : IN STD_LOGIC;
nfa_finals_buckets_req_write : OUT STD_LOGIC;
nfa_finals_buckets_rsp_empty_n : IN STD_LOGIC;
nfa_finals_buckets_rsp_read : OUT STD_LOGIC;
nfa_finals_buckets_address : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
nfa_finals_buckets_datain : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
nfa_finals_buckets_dataout : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
nfa_finals_buckets_size : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
nfa_forward_buckets_req_din : OUT STD_LOGIC;
nfa_forward_buckets_req_full_n : IN STD_LOGIC;
nfa_forward_buckets_req_write : OUT STD_LOGIC;
nfa_forward_buckets_rsp_empty_n : IN STD_LOGIC;
nfa_forward_buckets_rsp_read : OUT STD_LOGIC;
nfa_forward_buckets_address : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
nfa_forward_buckets_datain : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
nfa_forward_buckets_dataout : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
nfa_forward_buckets_size : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
nfa_symbols : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
sample_buffer_req_din : OUT STD_LOGIC;
sample_buffer_req_full_n : IN STD_LOGIC;
sample_buffer_req_write : OUT STD_LOGIC;
sample_buffer_rsp_empty_n : IN STD_LOGIC;
sample_buffer_rsp_read : OUT STD_LOGIC;
sample_buffer_address : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
sample_buffer_datain : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
sample_buffer_dataout : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
sample_buffer_size : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
sample_buffer_length : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
sample_length : IN STD_LOGIC_VECTOR (15 DOWNTO 0);
indices_begin_req_din : OUT STD_LOGIC;
indices_begin_req_full_n : IN STD_LOGIC;
indices_begin_req_write : OUT STD_LOGIC;
indices_begin_rsp_empty_n : IN STD_LOGIC;
indices_begin_rsp_read : OUT STD_LOGIC;
indices_begin_address : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
indices_begin_datain : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
indices_begin_dataout : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
indices_begin_size : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
indices_samples_req_din : OUT STD_LOGIC;
indices_samples_req_full_n : IN STD_LOGIC;
indices_samples_req_write : OUT STD_LOGIC;
indices_samples_rsp_empty_n : IN STD_LOGIC;
indices_samples_rsp_read : OUT STD_LOGIC;
indices_samples_address : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
indices_samples_datain : IN STD_LOGIC_VECTOR (15 DOWNTO 0);
indices_samples_dataout : OUT STD_LOGIC_VECTOR (15 DOWNTO 0);
indices_samples_size : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
indices_stride_req_din : OUT STD_LOGIC;
indices_stride_req_full_n : IN STD_LOGIC;
indices_stride_req_write : OUT STD_LOGIC;
indices_stride_rsp_empty_n : IN STD_LOGIC;
indices_stride_rsp_read : OUT STD_LOGIC;
indices_stride_address : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
indices_stride_datain : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
indices_stride_dataout : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
indices_stride_size : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
i_size : IN STD_LOGIC_VECTOR (15 DOWNTO 0);
begin_index : IN STD_LOGIC_VECTOR (15 DOWNTO 0);
begin_sample : IN STD_LOGIC_VECTOR (15 DOWNTO 0);
end_index : IN STD_LOGIC_VECTOR (15 DOWNTO 0);
end_sample : IN STD_LOGIC_VECTOR (15 DOWNTO 0);
stop_on_first : IN STD_LOGIC_VECTOR (0 DOWNTO 0);
accept : IN STD_LOGIC_VECTOR (0 DOWNTO 0);
ap_return : OUT STD_LOGIC_VECTOR (31 DOWNTO 0));
end component;
signal bus_nfa_initials_buckets_req_RW : STD_LOGIC;
signal bus_nfa_initials_buckets_req_full_n : STD_LOGIC;
signal reg_bus_nfa_initials_buckets_req_full_n : STD_LOGIC;
signal bus_nfa_initials_buckets_req_RW_en : STD_LOGIC;
signal bus_nfa_initials_buckets_rsp_empty_n : STD_LOGIC;
signal reg_bus_nfa_initials_buckets_rsp_empty_n : STD_LOGIC;
signal bus_nfa_initials_buckets_rsp_read : STD_LOGIC;
signal bus_nfa_initials_buckets_address : STD_LOGIC_VECTOR(31 downto 0);
signal bus_nfa_initials_buckets_din : STD_LOGIC_VECTOR(31 downto 0);
signal bus_nfa_initials_buckets_dout : STD_LOGIC_VECTOR(31 downto 0);
signal bus_nfa_initials_buckets_size : STD_LOGIC_VECTOR(31 downto 0);
signal bus_nfa_initials_buckets_ready : STD_LOGIC;
signal bus_nfa_initials_buckets_done : STD_LOGIC;
component AESL_autobus_nfa_initials_buckets is
port(
clk : IN STD_LOGIC;
rst : IN STD_LOGIC;
bus_req_RW : IN STD_LOGIC;
bus_req_full_n : OUT STD_LOGIC;
bus_req_RW_en : IN STD_LOGIC;
bus_rsp_empty_n : OUT STD_LOGIC;
bus_rsp_read : IN STD_LOGIC;
bus_address : IN STD_LOGIC_VECTOR;
bus_din : IN STD_LOGIC_VECTOR;
bus_dout : OUT STD_LOGIC_VECTOR;
bus_size : IN STD_LOGIC_VECTOR;
ready : IN STD_LOGIC;
done : IN STD_LOGIC
);
end component;
signal bus_nfa_finals_buckets_req_RW : STD_LOGIC;
signal bus_nfa_finals_buckets_req_full_n : STD_LOGIC;
signal reg_bus_nfa_finals_buckets_req_full_n : STD_LOGIC;
signal bus_nfa_finals_buckets_req_RW_en : STD_LOGIC;
signal bus_nfa_finals_buckets_rsp_empty_n : STD_LOGIC;
signal reg_bus_nfa_finals_buckets_rsp_empty_n : STD_LOGIC;
signal bus_nfa_finals_buckets_rsp_read : STD_LOGIC;
signal bus_nfa_finals_buckets_address : STD_LOGIC_VECTOR(31 downto 0);
signal bus_nfa_finals_buckets_din : STD_LOGIC_VECTOR(31 downto 0);
signal bus_nfa_finals_buckets_dout : STD_LOGIC_VECTOR(31 downto 0);
signal bus_nfa_finals_buckets_size : STD_LOGIC_VECTOR(31 downto 0);
signal bus_nfa_finals_buckets_ready : STD_LOGIC;
signal bus_nfa_finals_buckets_done : STD_LOGIC;
component AESL_autobus_nfa_finals_buckets is
port(
clk : IN STD_LOGIC;
rst : IN STD_LOGIC;
bus_req_RW : IN STD_LOGIC;
bus_req_full_n : OUT STD_LOGIC;
bus_req_RW_en : IN STD_LOGIC;
bus_rsp_empty_n : OUT STD_LOGIC;
bus_rsp_read : IN STD_LOGIC;
bus_address : IN STD_LOGIC_VECTOR;
bus_din : IN STD_LOGIC_VECTOR;
bus_dout : OUT STD_LOGIC_VECTOR;
bus_size : IN STD_LOGIC_VECTOR;
ready : IN STD_LOGIC;
done : IN STD_LOGIC
);
end component;
signal bus_nfa_forward_buckets_req_RW : STD_LOGIC;
signal bus_nfa_forward_buckets_req_full_n : STD_LOGIC;
signal reg_bus_nfa_forward_buckets_req_full_n : STD_LOGIC;
signal bus_nfa_forward_buckets_req_RW_en : STD_LOGIC;
signal bus_nfa_forward_buckets_rsp_empty_n : STD_LOGIC;
signal reg_bus_nfa_forward_buckets_rsp_empty_n : STD_LOGIC;
signal bus_nfa_forward_buckets_rsp_read : STD_LOGIC;
signal bus_nfa_forward_buckets_address : STD_LOGIC_VECTOR(31 downto 0);
signal bus_nfa_forward_buckets_din : STD_LOGIC_VECTOR(31 downto 0);
signal bus_nfa_forward_buckets_dout : STD_LOGIC_VECTOR(31 downto 0);
signal bus_nfa_forward_buckets_size : STD_LOGIC_VECTOR(31 downto 0);
signal bus_nfa_forward_buckets_ready : STD_LOGIC;
signal bus_nfa_forward_buckets_done : STD_LOGIC;
component AESL_autobus_nfa_forward_buckets is
port(
clk : IN STD_LOGIC;
rst : IN STD_LOGIC;
bus_req_RW : IN STD_LOGIC;
bus_req_full_n : OUT STD_LOGIC;
bus_req_RW_en : IN STD_LOGIC;
bus_rsp_empty_n : OUT STD_LOGIC;
bus_rsp_read : IN STD_LOGIC;
bus_address : IN STD_LOGIC_VECTOR;
bus_din : IN STD_LOGIC_VECTOR;
bus_dout : OUT STD_LOGIC_VECTOR;
bus_size : IN STD_LOGIC_VECTOR;
ready : IN STD_LOGIC;
done : IN STD_LOGIC
);
end component;
signal arraynfa_backward_buckets_ce0, arraynfa_backward_buckets_ce1 : STD_LOGIC;
signal arraynfa_backward_buckets_we0, arraynfa_backward_buckets_we1 : STD_LOGIC;
signal arraynfa_backward_buckets_address0, arraynfa_backward_buckets_address1 : STD_LOGIC_VECTOR(14 downto 0);
signal arraynfa_backward_buckets_din0, arraynfa_backward_buckets_din1 : STD_LOGIC_VECTOR(31 downto 0);
signal arraynfa_backward_buckets_dout0, arraynfa_backward_buckets_dout1 : STD_LOGIC_VECTOR(31 downto 0);
signal arraynfa_backward_buckets_ready : STD_LOGIC;
signal arraynfa_backward_buckets_done : STD_LOGIC;
component AESL_automem_nfa_backward_buckets is
port(
clk : IN STD_LOGIC;
rst : IN STD_LOGIC;
ce0 : IN STD_LOGIC;
we0 : IN STD_LOGIC;
address0 : IN STD_LOGIC_VECTOR;
din0 : IN STD_LOGIC_VECTOR;
dout0 : OUT STD_LOGIC_VECTOR;
ce1 : IN STD_LOGIC;
we1 : IN STD_LOGIC;
address1 : IN STD_LOGIC_VECTOR;
din1 : IN STD_LOGIC_VECTOR;
dout1 : OUT STD_LOGIC_VECTOR;
ready : IN STD_LOGIC;
done : IN STD_LOGIC
);
end component;
-- The signal of port nfa_symbols
shared variable AESL_REG_nfa_symbols : STD_LOGIC_VECTOR(7 downto 0) := (others => '0');
signal bus_sample_buffer_req_RW : STD_LOGIC;
signal bus_sample_buffer_req_full_n : STD_LOGIC;
signal reg_bus_sample_buffer_req_full_n : STD_LOGIC;
signal bus_sample_buffer_req_RW_en : STD_LOGIC;
signal bus_sample_buffer_rsp_empty_n : STD_LOGIC;
signal reg_bus_sample_buffer_rsp_empty_n : STD_LOGIC;
signal bus_sample_buffer_rsp_read : STD_LOGIC;
signal bus_sample_buffer_address : STD_LOGIC_VECTOR(31 downto 0);
signal bus_sample_buffer_din : STD_LOGIC_VECTOR(7 downto 0);
signal bus_sample_buffer_dout : STD_LOGIC_VECTOR(7 downto 0);
signal bus_sample_buffer_size : STD_LOGIC_VECTOR(31 downto 0);
signal bus_sample_buffer_ready : STD_LOGIC;
signal bus_sample_buffer_done : STD_LOGIC;
component AESL_autobus_sample_buffer is
port(
clk : IN STD_LOGIC;
rst : IN STD_LOGIC;
bus_req_RW : IN STD_LOGIC;
bus_req_full_n : OUT STD_LOGIC;
bus_req_RW_en : IN STD_LOGIC;
bus_rsp_empty_n : OUT STD_LOGIC;
bus_rsp_read : IN STD_LOGIC;
bus_address : IN STD_LOGIC_VECTOR;
bus_din : IN STD_LOGIC_VECTOR;
bus_dout : OUT STD_LOGIC_VECTOR;
bus_size : IN STD_LOGIC_VECTOR;
ready : IN STD_LOGIC;
done : IN STD_LOGIC
);
end component;
-- The signal of port sample_buffer_length
shared variable AESL_REG_sample_buffer_length : STD_LOGIC_VECTOR(31 downto 0) := (others => '0');
-- The signal of port sample_length
shared variable AESL_REG_sample_length : STD_LOGIC_VECTOR(15 downto 0) := (others => '0');
signal bus_indices_begin_req_RW : STD_LOGIC;
signal bus_indices_begin_req_full_n : STD_LOGIC;
signal reg_bus_indices_begin_req_full_n : STD_LOGIC;
signal bus_indices_begin_req_RW_en : STD_LOGIC;
signal bus_indices_begin_rsp_empty_n : STD_LOGIC;
signal reg_bus_indices_begin_rsp_empty_n : STD_LOGIC;
signal bus_indices_begin_rsp_read : STD_LOGIC;
signal bus_indices_begin_address : STD_LOGIC_VECTOR(31 downto 0);
signal bus_indices_begin_din : STD_LOGIC_VECTOR(31 downto 0);
signal bus_indices_begin_dout : STD_LOGIC_VECTOR(31 downto 0);
signal bus_indices_begin_size : STD_LOGIC_VECTOR(31 downto 0);
signal bus_indices_begin_ready : STD_LOGIC;
signal bus_indices_begin_done : STD_LOGIC;
component AESL_autobus_indices_begin is
port(
clk : IN STD_LOGIC;
rst : IN STD_LOGIC;
bus_req_RW : IN STD_LOGIC;
bus_req_full_n : OUT STD_LOGIC;
bus_req_RW_en : IN STD_LOGIC;
bus_rsp_empty_n : OUT STD_LOGIC;
bus_rsp_read : IN STD_LOGIC;
bus_address : IN STD_LOGIC_VECTOR;
bus_din : IN STD_LOGIC_VECTOR;
bus_dout : OUT STD_LOGIC_VECTOR;
bus_size : IN STD_LOGIC_VECTOR;
ready : IN STD_LOGIC;
done : IN STD_LOGIC
);
end component;
signal bus_indices_samples_req_RW : STD_LOGIC;
signal bus_indices_samples_req_full_n : STD_LOGIC;
signal reg_bus_indices_samples_req_full_n : STD_LOGIC;
signal bus_indices_samples_req_RW_en : STD_LOGIC;
signal bus_indices_samples_rsp_empty_n : STD_LOGIC;
signal reg_bus_indices_samples_rsp_empty_n : STD_LOGIC;
signal bus_indices_samples_rsp_read : STD_LOGIC;
signal bus_indices_samples_address : STD_LOGIC_VECTOR(31 downto 0);
signal bus_indices_samples_din : STD_LOGIC_VECTOR(15 downto 0);
signal bus_indices_samples_dout : STD_LOGIC_VECTOR(15 downto 0);
signal bus_indices_samples_size : STD_LOGIC_VECTOR(31 downto 0);
signal bus_indices_samples_ready : STD_LOGIC;
signal bus_indices_samples_done : STD_LOGIC;
component AESL_autobus_indices_samples is
port(
clk : IN STD_LOGIC;
rst : IN STD_LOGIC;
bus_req_RW : IN STD_LOGIC;
bus_req_full_n : OUT STD_LOGIC;
bus_req_RW_en : IN STD_LOGIC;
bus_rsp_empty_n : OUT STD_LOGIC;
bus_rsp_read : IN STD_LOGIC;
bus_address : IN STD_LOGIC_VECTOR;
bus_din : IN STD_LOGIC_VECTOR;
bus_dout : OUT STD_LOGIC_VECTOR;
bus_size : IN STD_LOGIC_VECTOR;
ready : IN STD_LOGIC;
done : IN STD_LOGIC
);
end component;
signal bus_indices_stride_req_RW : STD_LOGIC;
signal bus_indices_stride_req_full_n : STD_LOGIC;
signal reg_bus_indices_stride_req_full_n : STD_LOGIC;
signal bus_indices_stride_req_RW_en : STD_LOGIC;
signal bus_indices_stride_rsp_empty_n : STD_LOGIC;
signal reg_bus_indices_stride_rsp_empty_n : STD_LOGIC;
signal bus_indices_stride_rsp_read : STD_LOGIC;
signal bus_indices_stride_address : STD_LOGIC_VECTOR(31 downto 0);
signal bus_indices_stride_din : STD_LOGIC_VECTOR(7 downto 0);
signal bus_indices_stride_dout : STD_LOGIC_VECTOR(7 downto 0);
signal bus_indices_stride_size : STD_LOGIC_VECTOR(31 downto 0);
signal bus_indices_stride_ready : STD_LOGIC;
signal bus_indices_stride_done : STD_LOGIC;
component AESL_autobus_indices_stride is
port(
clk : IN STD_LOGIC;
rst : IN STD_LOGIC;
bus_req_RW : IN STD_LOGIC;
bus_req_full_n : OUT STD_LOGIC;
bus_req_RW_en : IN STD_LOGIC;
bus_rsp_empty_n : OUT STD_LOGIC;
bus_rsp_read : IN STD_LOGIC;
bus_address : IN STD_LOGIC_VECTOR;
bus_din : IN STD_LOGIC_VECTOR;
bus_dout : OUT STD_LOGIC_VECTOR;
bus_size : IN STD_LOGIC_VECTOR;
ready : IN STD_LOGIC;
done : IN STD_LOGIC
);
end component;
-- The signal of port i_size
shared variable AESL_REG_i_size : STD_LOGIC_VECTOR(15 downto 0) := (others => '0');
-- The signal of port begin_index
shared variable AESL_REG_begin_index : STD_LOGIC_VECTOR(15 downto 0) := (others => '0');
-- The signal of port begin_sample
shared variable AESL_REG_begin_sample : STD_LOGIC_VECTOR(15 downto 0) := (others => '0');
-- The signal of port end_index
shared variable AESL_REG_end_index : STD_LOGIC_VECTOR(15 downto 0) := (others => '0');
-- The signal of port end_sample
shared variable AESL_REG_end_sample : STD_LOGIC_VECTOR(15 downto 0) := (others => '0');
-- The signal of port stop_on_first
shared variable AESL_REG_stop_on_first : STD_LOGIC_VECTOR(0 downto 0) := (others => '0');
-- The signal of port accept
shared variable AESL_REG_accept : STD_LOGIC_VECTOR(0 downto 0) := (others => '0');
procedure esl_read_token (file textfile: TEXT; textline: inout LINE; token: out STRING; token_len: out INTEGER) is
variable whitespace : CHARACTER;
variable i : INTEGER;
variable ok: BOOLEAN;
variable buff: STRING(1 to token'length);
begin
ok := false;
i := 1;
loop_main: while not endfile(textfile) loop
if textline = null or textline'length = 0 then
readline(textfile, textline);
end if;
loop_remove_whitespace: while textline'length > 0 loop
if textline(textline'left) = ' ' or
textline(textline'left) = HT or
textline(textline'left) = CR or
textline(textline'left) = LF then
read(textline, whitespace);
else
exit loop_remove_whitespace;
end if;
end loop;
loop_aesl_read_token: while textline'length > 0 and i <= buff'length loop
if textline(textline'left) = ' ' or
textline(textline'left) = HT or
textline(textline'left) = CR or
textline(textline'left) = LF then
exit loop_aesl_read_token;
else
read(textline, buff(i));
i := i + 1;
end if;
ok := true;
end loop;
if ok = true then
exit loop_main;
end if;
end loop;
buff(i) := ' ';
token := buff;
token_len:= i-1;
end procedure esl_read_token;
procedure esl_read_token (file textfile: TEXT;
textline: inout LINE;
token: out STRING) is
variable i : INTEGER;
begin
esl_read_token (textfile, textline, token, i);
end procedure esl_read_token;
function esl_str2lv_hex (RHS : STRING; data_width : INTEGER) return STD_LOGIC_VECTOR is
variable ret : STD_LOGIC_VECTOR(data_width - 1 downto 0);
variable idx : integer := 3;
begin
ret := (others => '0');
if(RHS(1) /= '0' and (RHS(2) /= 'x' or RHS(2) /= 'X')) then
report "Error! The format of hex number is not initialed by 0x";
end if;
while true loop
if (data_width > 4) then
case RHS(idx) is
when '0' => ret := ret(data_width - 5 downto 0) & "0000";
when '1' => ret := ret(data_width - 5 downto 0) & "0001";
when '2' => ret := ret(data_width - 5 downto 0) & "0010";
when '3' => ret := ret(data_width - 5 downto 0) & "0011";
when '4' => ret := ret(data_width - 5 downto 0) & "0100";
when '5' => ret := ret(data_width - 5 downto 0) & "0101";
when '6' => ret := ret(data_width - 5 downto 0) & "0110";
when '7' => ret := ret(data_width - 5 downto 0) & "0111";
when '8' => ret := ret(data_width - 5 downto 0) & "1000";
when '9' => ret := ret(data_width - 5 downto 0) & "1001";
when 'a' | 'A' => ret := ret(data_width - 5 downto 0) & "1010";
when 'b' | 'B' => ret := ret(data_width - 5 downto 0) & "1011";
when 'c' | 'C' => ret := ret(data_width - 5 downto 0) & "1100";
when 'd' | 'D' => ret := ret(data_width - 5 downto 0) & "1101";
when 'e' | 'E' => ret := ret(data_width - 5 downto 0) & "1110";
when 'f' | 'F' => ret := ret(data_width - 5 downto 0) & "1111";
when ' ' => return ret;
when others => report "Wrong hex char " & RHS(idx); return ret;
end case;
elsif (data_width = 4) then
case RHS(idx) is
when '0' => ret := "0000";
when '1' => ret := "0001";
when '2' => ret := "0010";
when '3' => ret := "0011";
when '4' => ret := "0100";
when '5' => ret := "0101";
when '6' => ret := "0110";
when '7' => ret := "0111";
when '8' => ret := "1000";
when '9' => ret := "1001";
when 'a' | 'A' => ret := "1010";
when 'b' | 'B' => ret := "1011";
when 'c' | 'C' => ret := "1100";
when 'd' | 'D' => ret := "1101";
when 'e' | 'E' => ret := "1110";
when 'f' | 'F' => ret := "1111";
when ' ' => return ret;
when others => report "Wrong hex char " & RHS(idx); return ret;
end case;
elsif (data_width = 3) then
case RHS(idx) is
when '0' => ret := "000";
when '1' => ret := "001";
when '2' => ret := "010";
when '3' => ret := "011";
when '4' => ret := "100";
when '5' => ret := "101";
when '6' => ret := "110";
when '7' => ret := "111";
when ' ' => return ret;
when others => report "Wrong hex char " & RHS(idx); return ret;
end case;
elsif (data_width = 2) then
case RHS(idx) is
when '0' => ret := "00";
when '1' => ret := "01";
when '2' => ret := "10";
when '3' => ret := "11";
when ' ' => return ret;
when others => report "Wrong hex char " & RHS(idx); return ret;
end case;
elsif (data_width = 1) then
case RHS(idx) is
when '0' => ret := "0";
when '1' => ret := "1";
when ' ' => return ret;
when others => report "Wrong hex char " & RHS(idx); return ret;
end case;
else
report string'("Wrong data_width.");
return ret;
end if;
idx := idx + 1;
end loop;
return ret;
end function;
function esl_str_dec2int (RHS : STRING) return INTEGER is
variable ret : integer;
variable idx : integer := 1;
begin
ret := 0;
while true loop
case RHS(idx) is
when '0' => ret := ret * 10 + 0;
when '1' => ret := ret * 10 + 1;
when '2' => ret := ret * 10 + 2;
when '3' => ret := ret * 10 + 3;
when '4' => ret := ret * 10 + 4;
when '5' => ret := ret * 10 + 5;
when '6' => ret := ret * 10 + 6;
when '7' => ret := ret * 10 + 7;
when '8' => ret := ret * 10 + 8;
when '9' => ret := ret * 10 + 9;
when ' ' => return ret;
when others => report "Wrong dec char " & RHS(idx); return ret;
end case;
idx := idx + 1;
end loop;
return ret;
end function;
function esl_conv_string_hex (lv : STD_LOGIC_VECTOR) return STRING is
constant str_len : integer := (lv'length + 3)/4;
variable ret : STRING (1 to str_len);
variable i, tmp: INTEGER;
variable normal_lv : STD_LOGIC_VECTOR(lv'length - 1 downto 0);
variable tmp_lv : STD_LOGIC_VECTOR(3 downto 0);
begin
normal_lv := lv;
for i in 1 to str_len loop
if(i = 1) then
if((lv'length mod 4) = 3) then
tmp_lv(2 downto 0) := normal_lv(lv'length - 1 downto lv'length - 3);
case tmp_lv(2 downto 0) is
when "000" => ret(i) := '0';
when "001" => ret(i) := '1';
when "010" => ret(i) := '2';
when "011" => ret(i) := '3';
when "100" => ret(i) := '4';
when "101" => ret(i) := '5';
when "110" => ret(i) := '6';
when "111" => ret(i) := '7';
when others => ret(i) := '0';
end case;
elsif((lv'length mod 4) = 2) then
tmp_lv(1 downto 0) := normal_lv(lv'length - 1 downto lv'length - 2);
case tmp_lv(1 downto 0) is
when "00" => ret(i) := '0';
when "01" => ret(i) := '1';
when "10" => ret(i) := '2';
when "11" => ret(i) := '3';
when others => ret(i) := '0';
end case;
elsif((lv'length mod 4) = 1) then
tmp_lv(0 downto 0) := normal_lv(lv'length - 1 downto lv'length - 1);
case tmp_lv(0 downto 0) is
when "0" => ret(i) := '0';
when "1" => ret(i) := '1';
when others=> ret(i) := '0';
end case;
elsif((lv'length mod 4) = 0) then
tmp_lv(3 downto 0) := normal_lv(lv'length - 1 downto lv'length - 4);
case tmp_lv(3 downto 0) is
when "0000" => ret(i) := '0';
when "0001" => ret(i) := '1';
when "0010" => ret(i) := '2';
when "0011" => ret(i) := '3';
when "0100" => ret(i) := '4';
when "0101" => ret(i) := '5';
when "0110" => ret(i) := '6';
when "0111" => ret(i) := '7';
when "1000" => ret(i) := '8';
when "1001" => ret(i) := '9';
when "1010" => ret(i) := 'a';
when "1011" => ret(i) := 'b';
when "1100" => ret(i) := 'c';
when "1101" => ret(i) := 'd';
when "1110" => ret(i) := 'e';
when "1111" => ret(i) := 'f';
when others => ret(i) := '0';
end case;
end if;
else
tmp_lv(3 downto 0) := normal_lv((str_len - i) * 4 + 3 downto (str_len - i) * 4);
case tmp_lv(3 downto 0) is
when "0000" => ret(i) := '0';
when "0001" => ret(i) := '1';
when "0010" => ret(i) := '2';
when "0011" => ret(i) := '3';
when "0100" => ret(i) := '4';
when "0101" => ret(i) := '5';
when "0110" => ret(i) := '6';
when "0111" => ret(i) := '7';
when "1000" => ret(i) := '8';
when "1001" => ret(i) := '9';
when "1010" => ret(i) := 'a';
when "1011" => ret(i) := 'b';
when "1100" => ret(i) := 'c';
when "1101" => ret(i) := 'd';
when "1110" => ret(i) := 'e';
when "1111" => ret(i) := 'f';
when others => ret(i) := '0';
end case;
end if;
end loop;
return ret;
end function;
-- purpose: initialise the random state variable based on an integer seed
function init_rand(seed : integer) return T_RANDINT is
variable result : T_RANDINT;
begin
-- If the seed is smaller than the minimum value of the random state variable, use the minimum value
if seed < T_RANDINT'low then
result := T_RANDINT'low;
-- If the seed is larger than the maximum value of the random state variable, use the maximum value
elsif seed > T_RANDINT'high then
result := T_RANDINT'high;
-- If the seed is within the range of the random state variable, just use the seed
else
result := seed;
end if;
-- Return the result
return result;
end init_rand;
-- purpose: generate a random integer between min and max limits
procedure rand_int(variable rand : inout T_RANDINT;
constant minval : in integer;
constant maxval : in integer;
variable result : out integer
) is
variable k, q : integer;
variable real_rand : real;
variable res : integer;
begin
-- Create a new random integer in the range 1 to 2**31-1 and put it back into rand VARIABLE
-- Based on an example from Numerical Recipes in C, 2nd Edition, page 279
k := rand/127773;
q := 16807*(rand-k*127773)-2836*k;
if q < 0 then
q := q + 2147483647;
end if;
rand := init_rand(q);
-- Convert this integer to a real number in the range 0 to 1
real_rand := (real(rand - T_RANDINT'low)) / real(T_RANDINT'high - T_RANDINT'low);
-- Convert this real number to an integer in the range minval to maxval
-- The +1 and -0.5 are to get equal probability of minval and maxval as other values
res := integer((real_rand * real(maxval+1-minval)) - 0.5) + minval;
-- VHDL real to integer conversion doesn't define what happens for x.5 so deal with this
if res < minval then
res := minval;
elsif res > maxval then
res := maxval;
end if;
-- assign output
result := res;
end rand_int;
begin
AESL_inst_nfa_accept_samples_generic_hw : nfa_accept_samples_generic_hw port map (
ap_clk => ap_clk,
ap_rst => ap_rst,
ap_start => ap_start,
ap_done => ap_done,
ap_idle => ap_idle,
ap_ready => ap_ready,
nfa_initials_buckets_req_din => nfa_initials_buckets_req_din,
nfa_initials_buckets_req_full_n => nfa_initials_buckets_req_full_n,
nfa_initials_buckets_req_write => nfa_initials_buckets_req_write,
nfa_initials_buckets_rsp_empty_n => nfa_initials_buckets_rsp_empty_n,
nfa_initials_buckets_rsp_read => nfa_initials_buckets_rsp_read,
nfa_initials_buckets_address => nfa_initials_buckets_address,
nfa_initials_buckets_datain => nfa_initials_buckets_datain,
nfa_initials_buckets_dataout => nfa_initials_buckets_dataout,
nfa_initials_buckets_size => nfa_initials_buckets_size,
nfa_finals_buckets_req_din => nfa_finals_buckets_req_din,
nfa_finals_buckets_req_full_n => nfa_finals_buckets_req_full_n,
nfa_finals_buckets_req_write => nfa_finals_buckets_req_write,
nfa_finals_buckets_rsp_empty_n => nfa_finals_buckets_rsp_empty_n,
nfa_finals_buckets_rsp_read => nfa_finals_buckets_rsp_read,
nfa_finals_buckets_address => nfa_finals_buckets_address,
nfa_finals_buckets_datain => nfa_finals_buckets_datain,
nfa_finals_buckets_dataout => nfa_finals_buckets_dataout,
nfa_finals_buckets_size => nfa_finals_buckets_size,
nfa_forward_buckets_req_din => nfa_forward_buckets_req_din,
nfa_forward_buckets_req_full_n => nfa_forward_buckets_req_full_n,
nfa_forward_buckets_req_write => nfa_forward_buckets_req_write,
nfa_forward_buckets_rsp_empty_n => nfa_forward_buckets_rsp_empty_n,
nfa_forward_buckets_rsp_read => nfa_forward_buckets_rsp_read,
nfa_forward_buckets_address => nfa_forward_buckets_address,
nfa_forward_buckets_datain => nfa_forward_buckets_datain,
nfa_forward_buckets_dataout => nfa_forward_buckets_dataout,
nfa_forward_buckets_size => nfa_forward_buckets_size,
nfa_symbols => nfa_symbols,
sample_buffer_req_din => sample_buffer_req_din,
sample_buffer_req_full_n => sample_buffer_req_full_n,
sample_buffer_req_write => sample_buffer_req_write,
sample_buffer_rsp_empty_n => sample_buffer_rsp_empty_n,
sample_buffer_rsp_read => sample_buffer_rsp_read,
sample_buffer_address => sample_buffer_address,
sample_buffer_datain => sample_buffer_datain,
sample_buffer_dataout => sample_buffer_dataout,
sample_buffer_size => sample_buffer_size,
sample_buffer_length => sample_buffer_length,
sample_length => sample_length,
indices_begin_req_din => indices_begin_req_din,
indices_begin_req_full_n => indices_begin_req_full_n,
indices_begin_req_write => indices_begin_req_write,
indices_begin_rsp_empty_n => indices_begin_rsp_empty_n,
indices_begin_rsp_read => indices_begin_rsp_read,
indices_begin_address => indices_begin_address,
indices_begin_datain => indices_begin_datain,
indices_begin_dataout => indices_begin_dataout,
indices_begin_size => indices_begin_size,
indices_samples_req_din => indices_samples_req_din,
indices_samples_req_full_n => indices_samples_req_full_n,
indices_samples_req_write => indices_samples_req_write,
indices_samples_rsp_empty_n => indices_samples_rsp_empty_n,
indices_samples_rsp_read => indices_samples_rsp_read,
indices_samples_address => indices_samples_address,
indices_samples_datain => indices_samples_datain,
indices_samples_dataout => indices_samples_dataout,
indices_samples_size => indices_samples_size,
indices_stride_req_din => indices_stride_req_din,
indices_stride_req_full_n => indices_stride_req_full_n,
indices_stride_req_write => indices_stride_req_write,
indices_stride_rsp_empty_n => indices_stride_rsp_empty_n,
indices_stride_rsp_read => indices_stride_rsp_read,
indices_stride_address => indices_stride_address,
indices_stride_datain => indices_stride_datain,
indices_stride_dataout => indices_stride_dataout,
indices_stride_size => indices_stride_size,
i_size => i_size,
begin_index => begin_index,
begin_sample => begin_sample,
end_index => end_index,
end_sample => end_sample,
stop_on_first => stop_on_first,
accept => accept,
ap_return => ap_return
);
-- Assignment for control signal
ap_clk <= AESL_clock;
ap_rst <= AESL_reset;
AESL_reset <= rst;
ap_start <= AESL_start;
AESL_start <= start;
AESL_done <= ap_done;
AESL_idle <= ap_idle;
AESL_ready <= ap_ready;
AESL_ce <= ce;
AESL_continue <= continue;
AESL_inst_nfa_initials_buckets : AESL_autobus_nfa_initials_buckets port map (
clk => AESL_clock,
rst => AESL_reset,
bus_req_RW => bus_nfa_initials_buckets_req_RW,
bus_req_full_n => bus_nfa_initials_buckets_req_full_n,
bus_req_RW_en => bus_nfa_initials_buckets_req_RW_en,
bus_rsp_empty_n => bus_nfa_initials_buckets_rsp_empty_n,
bus_rsp_read => bus_nfa_initials_buckets_rsp_read,
bus_address => bus_nfa_initials_buckets_address,
bus_din => bus_nfa_initials_buckets_din,
bus_dout => bus_nfa_initials_buckets_dout,
bus_size => bus_nfa_initials_buckets_size,
ready => bus_nfa_initials_buckets_ready,
done => bus_nfa_initials_buckets_done
);
-- Assignment between dut and bus nfa_initials_buckets
-- Assign input of bus nfa_initials_buckets
bus_nfa_initials_buckets_req_RW <= nfa_initials_buckets_req_din;
bus_nfa_initials_buckets_req_RW_en <= nfa_initials_buckets_req_write and nfa_initials_buckets_req_full_n;
bus_nfa_initials_buckets_rsp_read <= nfa_initials_buckets_rsp_read and nfa_initials_buckets_rsp_empty_n;
bus_nfa_initials_buckets_address <= nfa_initials_buckets_address;
bus_nfa_initials_buckets_din <= nfa_initials_buckets_dataout;
bus_nfa_initials_buckets_size <= nfa_initials_buckets_size;
bus_nfa_initials_buckets_ready <= ready;
-- Assign input of dut
nfa_initials_buckets_datain <= bus_nfa_initials_buckets_dout;
gen_reg_bus_nfa_initials_buckets_req_full_n_proc : process
variable rand : T_RANDINT := init_rand(0);
variable rint : INTEGER;
begin
reg_bus_nfa_initials_buckets_req_full_n <= '0';
while(true) loop
wait until bus_nfa_initials_buckets_req_full_n'event;
if(bus_nfa_initials_buckets_req_full_n = '1') then
end if;
reg_bus_nfa_initials_buckets_req_full_n <= bus_nfa_initials_buckets_req_full_n;
end loop;
end process;
nfa_initials_buckets_req_full_n <= reg_bus_nfa_initials_buckets_req_full_n;
gen_reg_bus_nfa_initials_buckets_rsp_empty_n_proc : process
variable rand : T_RANDINT := init_rand(0);
variable rint : INTEGER;
begin
reg_bus_nfa_initials_buckets_rsp_empty_n <= '0';
while(true) loop
wait until bus_nfa_initials_buckets_rsp_empty_n'event;
if(bus_nfa_initials_buckets_rsp_empty_n = '1') then
end if;
reg_bus_nfa_initials_buckets_rsp_empty_n <= bus_nfa_initials_buckets_rsp_empty_n;
end loop;
end process;
nfa_initials_buckets_rsp_empty_n <= reg_bus_nfa_initials_buckets_rsp_empty_n;
AESL_inst_nfa_finals_buckets : AESL_autobus_nfa_finals_buckets port map (
clk => AESL_clock,
rst => AESL_reset,
bus_req_RW => bus_nfa_finals_buckets_req_RW,
bus_req_full_n => bus_nfa_finals_buckets_req_full_n,
bus_req_RW_en => bus_nfa_finals_buckets_req_RW_en,
bus_rsp_empty_n => bus_nfa_finals_buckets_rsp_empty_n,
bus_rsp_read => bus_nfa_finals_buckets_rsp_read,
bus_address => bus_nfa_finals_buckets_address,
bus_din => bus_nfa_finals_buckets_din,
bus_dout => bus_nfa_finals_buckets_dout,
bus_size => bus_nfa_finals_buckets_size,
ready => bus_nfa_finals_buckets_ready,
done => bus_nfa_finals_buckets_done
);
-- Assignment between dut and bus nfa_finals_buckets
-- Assign input of bus nfa_finals_buckets
bus_nfa_finals_buckets_req_RW <= nfa_finals_buckets_req_din;
bus_nfa_finals_buckets_req_RW_en <= nfa_finals_buckets_req_write and nfa_finals_buckets_req_full_n;
bus_nfa_finals_buckets_rsp_read <= nfa_finals_buckets_rsp_read and nfa_finals_buckets_rsp_empty_n;
bus_nfa_finals_buckets_address <= nfa_finals_buckets_address;
bus_nfa_finals_buckets_din <= nfa_finals_buckets_dataout;
bus_nfa_finals_buckets_size <= nfa_finals_buckets_size;
bus_nfa_finals_buckets_ready <= ready;
-- Assign input of dut
nfa_finals_buckets_datain <= bus_nfa_finals_buckets_dout;
gen_reg_bus_nfa_finals_buckets_req_full_n_proc : process
variable rand : T_RANDINT := init_rand(0);
variable rint : INTEGER;
begin
reg_bus_nfa_finals_buckets_req_full_n <= '0';
while(true) loop
wait until bus_nfa_finals_buckets_req_full_n'event;
if(bus_nfa_finals_buckets_req_full_n = '1') then
end if;
reg_bus_nfa_finals_buckets_req_full_n <= bus_nfa_finals_buckets_req_full_n;
end loop;
end process;
nfa_finals_buckets_req_full_n <= reg_bus_nfa_finals_buckets_req_full_n;
gen_reg_bus_nfa_finals_buckets_rsp_empty_n_proc : process
variable rand : T_RANDINT := init_rand(0);
variable rint : INTEGER;
begin
reg_bus_nfa_finals_buckets_rsp_empty_n <= '0';
while(true) loop
wait until bus_nfa_finals_buckets_rsp_empty_n'event;
if(bus_nfa_finals_buckets_rsp_empty_n = '1') then
end if;
reg_bus_nfa_finals_buckets_rsp_empty_n <= bus_nfa_finals_buckets_rsp_empty_n;
end loop;
end process;
nfa_finals_buckets_rsp_empty_n <= reg_bus_nfa_finals_buckets_rsp_empty_n;
AESL_inst_nfa_forward_buckets : AESL_autobus_nfa_forward_buckets port map (
clk => AESL_clock,
rst => AESL_reset,
bus_req_RW => bus_nfa_forward_buckets_req_RW,
bus_req_full_n => bus_nfa_forward_buckets_req_full_n,
bus_req_RW_en => bus_nfa_forward_buckets_req_RW_en,
bus_rsp_empty_n => bus_nfa_forward_buckets_rsp_empty_n,
bus_rsp_read => bus_nfa_forward_buckets_rsp_read,
bus_address => bus_nfa_forward_buckets_address,
bus_din => bus_nfa_forward_buckets_din,
bus_dout => bus_nfa_forward_buckets_dout,
bus_size => bus_nfa_forward_buckets_size,
ready => bus_nfa_forward_buckets_ready,
done => bus_nfa_forward_buckets_done
);
-- Assignment between dut and bus nfa_forward_buckets
-- Assign input of bus nfa_forward_buckets
bus_nfa_forward_buckets_req_RW <= nfa_forward_buckets_req_din;
bus_nfa_forward_buckets_req_RW_en <= nfa_forward_buckets_req_write and nfa_forward_buckets_req_full_n;
bus_nfa_forward_buckets_rsp_read <= nfa_forward_buckets_rsp_read and nfa_forward_buckets_rsp_empty_n;
bus_nfa_forward_buckets_address <= nfa_forward_buckets_address;
bus_nfa_forward_buckets_din <= nfa_forward_buckets_dataout;
bus_nfa_forward_buckets_size <= nfa_forward_buckets_size;
bus_nfa_forward_buckets_ready <= ready;
-- Assign input of dut
nfa_forward_buckets_datain <= bus_nfa_forward_buckets_dout;
gen_reg_bus_nfa_forward_buckets_req_full_n_proc : process
variable rand : T_RANDINT := init_rand(0);
variable rint : INTEGER;
begin
reg_bus_nfa_forward_buckets_req_full_n <= '0';
while(true) loop
wait until bus_nfa_forward_buckets_req_full_n'event;
if(bus_nfa_forward_buckets_req_full_n = '1') then
end if;
reg_bus_nfa_forward_buckets_req_full_n <= bus_nfa_forward_buckets_req_full_n;
end loop;
end process;
nfa_forward_buckets_req_full_n <= reg_bus_nfa_forward_buckets_req_full_n;
gen_reg_bus_nfa_forward_buckets_rsp_empty_n_proc : process
variable rand : T_RANDINT := init_rand(0);
variable rint : INTEGER;
begin
reg_bus_nfa_forward_buckets_rsp_empty_n <= '0';
while(true) loop
wait until bus_nfa_forward_buckets_rsp_empty_n'event;
if(bus_nfa_forward_buckets_rsp_empty_n = '1') then
end if;
reg_bus_nfa_forward_buckets_rsp_empty_n <= bus_nfa_forward_buckets_rsp_empty_n;
end loop;
end process;
nfa_forward_buckets_rsp_empty_n <= reg_bus_nfa_forward_buckets_rsp_empty_n;
-- Assignment between dut and arraynfa_backward_buckets
arraynfa_backward_buckets_done <= '0';
gen_assign_nfa_symbols_proc : process
begin
wait until (AESL_clock'event and AESL_clock = '1');
wait for 0.45 ns;
nfa_symbols <= AESL_REG_nfa_symbols;
end process;
read_file_process_nfa_symbols : process
file fp : TEXT;
variable fstatus : FILE_OPEN_STATUS;
variable token_line : LINE;
variable token : STRING(1 to 280);
variable i : INTEGER;
variable transaction_finish : INTEGER;
variable rand : T_RANDINT := init_rand(0);
variable rint : INTEGER;
begin
wait until AESL_reset = '0';
file_open(fstatus, fp, AUTOTB_TVIN_nfa_symbols, READ_MODE);
if(fstatus /= OPEN_OK) then
assert false report "Open file " & AUTOTB_TVIN_nfa_symbols & " failed!!!" severity note;
assert false report "ERROR: Simulation using HLS TB failed." severity failure;
end if;
esl_read_token(fp, token_line, token);
if(token(1 to 13) /= "[[[runtime]]]") then
report "The token is " & token;
assert false report "Illegal format of [[[runtime]]] part in " & AUTOTB_TVIN_nfa_symbols severity note;
assert false report "ERROR: Simulation using HLS TB failed." severity failure;
end if;
esl_read_token(fp, token_line, token);
while(token(1 to 14) /= "[[[/runtime]]]") loop
if(token(1 to 15) /= "[[transaction]]") then
report "The token is " & token;
assert false report "Illegal format of [[transaction]] part in " & AUTOTB_TVIN_nfa_symbols severity note;
assert false report "ERROR: Simulation using HLS TB failed." severity failure;
end if;
esl_read_token(fp, token_line, token); -- Skip transaction number
esl_read_token(fp, token_line, token);
wait until AESL_clock'event and AESL_clock = '1';
wait for 0.2 ns;
while(ready_wire /= '1') loop
wait until AESL_clock'event and AESL_clock = '1';
wait for 0.2 ns;
end loop;
if(token(1 to 16) /= "[[/transaction]]") then
AESL_REG_nfa_symbols := esl_str2lv_hex(token, 8 );
esl_read_token(fp, token_line, token);
end if;
esl_read_token(fp, token_line, token);
end loop;
file_close(fp);
wait;
end process;
AESL_inst_sample_buffer : AESL_autobus_sample_buffer port map (
clk => AESL_clock,
rst => AESL_reset,
bus_req_RW => bus_sample_buffer_req_RW,
bus_req_full_n => bus_sample_buffer_req_full_n,
bus_req_RW_en => bus_sample_buffer_req_RW_en,
bus_rsp_empty_n => bus_sample_buffer_rsp_empty_n,
bus_rsp_read => bus_sample_buffer_rsp_read,
bus_address => bus_sample_buffer_address,
bus_din => bus_sample_buffer_din,
bus_dout => bus_sample_buffer_dout,
bus_size => bus_sample_buffer_size,
ready => bus_sample_buffer_ready,
done => bus_sample_buffer_done
);
-- Assignment between dut and bus sample_buffer
-- Assign input of bus sample_buffer
bus_sample_buffer_req_RW <= sample_buffer_req_din;
bus_sample_buffer_req_RW_en <= sample_buffer_req_write and sample_buffer_req_full_n;
bus_sample_buffer_rsp_read <= sample_buffer_rsp_read and sample_buffer_rsp_empty_n;
bus_sample_buffer_address <= sample_buffer_address;
bus_sample_buffer_din <= sample_buffer_dataout;
bus_sample_buffer_size <= sample_buffer_size;
bus_sample_buffer_ready <= ready;
-- Assign input of dut
sample_buffer_datain <= bus_sample_buffer_dout;
gen_reg_bus_sample_buffer_req_full_n_proc : process
variable rand : T_RANDINT := init_rand(0);
variable rint : INTEGER;
begin
reg_bus_sample_buffer_req_full_n <= '0';
while(true) loop
wait until bus_sample_buffer_req_full_n'event;
if(bus_sample_buffer_req_full_n = '1') then
end if;
reg_bus_sample_buffer_req_full_n <= bus_sample_buffer_req_full_n;
end loop;
end process;
sample_buffer_req_full_n <= reg_bus_sample_buffer_req_full_n;
gen_reg_bus_sample_buffer_rsp_empty_n_proc : process
variable rand : T_RANDINT := init_rand(0);
variable rint : INTEGER;
begin
reg_bus_sample_buffer_rsp_empty_n <= '0';
while(true) loop
wait until bus_sample_buffer_rsp_empty_n'event;
if(bus_sample_buffer_rsp_empty_n = '1') then
end if;
reg_bus_sample_buffer_rsp_empty_n <= bus_sample_buffer_rsp_empty_n;
end loop;
end process;
sample_buffer_rsp_empty_n <= reg_bus_sample_buffer_rsp_empty_n;
gen_assign_sample_buffer_length_proc : process
begin
wait until (AESL_clock'event and AESL_clock = '1');
wait for 0.45 ns;
sample_buffer_length <= AESL_REG_sample_buffer_length;
end process;
read_file_process_sample_buffer_length : process
file fp : TEXT;
variable fstatus : FILE_OPEN_STATUS;
variable token_line : LINE;
variable token : STRING(1 to 280);
variable i : INTEGER;
variable transaction_finish : INTEGER;
variable rand : T_RANDINT := init_rand(0);
variable rint : INTEGER;
begin
wait until AESL_reset = '0';
file_open(fstatus, fp, AUTOTB_TVIN_sample_buffer_length, READ_MODE);
if(fstatus /= OPEN_OK) then
assert false report "Open file " & AUTOTB_TVIN_sample_buffer_length & " failed!!!" severity note;
assert false report "ERROR: Simulation using HLS TB failed." severity failure;
end if;
esl_read_token(fp, token_line, token);
if(token(1 to 13) /= "[[[runtime]]]") then
report "The token is " & token;
assert false report "Illegal format of [[[runtime]]] part in " & AUTOTB_TVIN_sample_buffer_length severity note;
assert false report "ERROR: Simulation using HLS TB failed." severity failure;
end if;
esl_read_token(fp, token_line, token);
while(token(1 to 14) /= "[[[/runtime]]]") loop
if(token(1 to 15) /= "[[transaction]]") then
report "The token is " & token;
assert false report "Illegal format of [[transaction]] part in " & AUTOTB_TVIN_sample_buffer_length severity note;
assert false report "ERROR: Simulation using HLS TB failed." severity failure;
end if;
esl_read_token(fp, token_line, token); -- Skip transaction number
esl_read_token(fp, token_line, token);
wait until AESL_clock'event and AESL_clock = '1';
wait for 0.2 ns;
while(ready_wire /= '1') loop
wait until AESL_clock'event and AESL_clock = '1';
wait for 0.2 ns;
end loop;
if(token(1 to 16) /= "[[/transaction]]") then
AESL_REG_sample_buffer_length := esl_str2lv_hex(token, 32 );
esl_read_token(fp, token_line, token);
end if;
esl_read_token(fp, token_line, token);
end loop;
file_close(fp);
wait;
end process;
gen_assign_sample_length_proc : process
begin
wait until (AESL_clock'event and AESL_clock = '1');
wait for 0.45 ns;
sample_length <= AESL_REG_sample_length;
end process;
read_file_process_sample_length : process
file fp : TEXT;
variable fstatus : FILE_OPEN_STATUS;
variable token_line : LINE;
variable token : STRING(1 to 280);
variable i : INTEGER;
variable transaction_finish : INTEGER;
variable rand : T_RANDINT := init_rand(0);
variable rint : INTEGER;
begin
wait until AESL_reset = '0';
file_open(fstatus, fp, AUTOTB_TVIN_sample_length, READ_MODE);
if(fstatus /= OPEN_OK) then
assert false report "Open file " & AUTOTB_TVIN_sample_length & " failed!!!" severity note;
assert false report "ERROR: Simulation using HLS TB failed." severity failure;
end if;
esl_read_token(fp, token_line, token);
if(token(1 to 13) /= "[[[runtime]]]") then
report "The token is " & token;
assert false report "Illegal format of [[[runtime]]] part in " & AUTOTB_TVIN_sample_length severity note;
assert false report "ERROR: Simulation using HLS TB failed." severity failure;
end if;
esl_read_token(fp, token_line, token);
while(token(1 to 14) /= "[[[/runtime]]]") loop
if(token(1 to 15) /= "[[transaction]]") then
report "The token is " & token;
assert false report "Illegal format of [[transaction]] part in " & AUTOTB_TVIN_sample_length severity note;
assert false report "ERROR: Simulation using HLS TB failed." severity failure;
end if;
esl_read_token(fp, token_line, token); -- Skip transaction number
esl_read_token(fp, token_line, token);
wait until AESL_clock'event and AESL_clock = '1';
wait for 0.2 ns;
while(ready_wire /= '1') loop
wait until AESL_clock'event and AESL_clock = '1';
wait for 0.2 ns;
end loop;
if(token(1 to 16) /= "[[/transaction]]") then
AESL_REG_sample_length := esl_str2lv_hex(token, 16 );
esl_read_token(fp, token_line, token);
end if;
esl_read_token(fp, token_line, token);
end loop;
file_close(fp);
wait;
end process;
AESL_inst_indices_begin : AESL_autobus_indices_begin port map (
clk => AESL_clock,
rst => AESL_reset,
bus_req_RW => bus_indices_begin_req_RW,
bus_req_full_n => bus_indices_begin_req_full_n,
bus_req_RW_en => bus_indices_begin_req_RW_en,
bus_rsp_empty_n => bus_indices_begin_rsp_empty_n,
bus_rsp_read => bus_indices_begin_rsp_read,
bus_address => bus_indices_begin_address,
bus_din => bus_indices_begin_din,
bus_dout => bus_indices_begin_dout,
bus_size => bus_indices_begin_size,
ready => bus_indices_begin_ready,
done => bus_indices_begin_done
);
-- Assignment between dut and bus indices_begin
-- Assign input of bus indices_begin
bus_indices_begin_req_RW <= indices_begin_req_din;
bus_indices_begin_req_RW_en <= indices_begin_req_write and indices_begin_req_full_n;
bus_indices_begin_rsp_read <= indices_begin_rsp_read and indices_begin_rsp_empty_n;
bus_indices_begin_address <= indices_begin_address;
bus_indices_begin_din <= indices_begin_dataout;
bus_indices_begin_size <= indices_begin_size;
bus_indices_begin_ready <= ready;
-- Assign input of dut
indices_begin_datain <= bus_indices_begin_dout;
gen_reg_bus_indices_begin_req_full_n_proc : process
variable rand : T_RANDINT := init_rand(0);
variable rint : INTEGER;
begin
reg_bus_indices_begin_req_full_n <= '0';
while(true) loop
wait until bus_indices_begin_req_full_n'event;
if(bus_indices_begin_req_full_n = '1') then
end if;
reg_bus_indices_begin_req_full_n <= bus_indices_begin_req_full_n;
end loop;
end process;
indices_begin_req_full_n <= reg_bus_indices_begin_req_full_n;
gen_reg_bus_indices_begin_rsp_empty_n_proc : process
variable rand : T_RANDINT := init_rand(0);
variable rint : INTEGER;
begin
reg_bus_indices_begin_rsp_empty_n <= '0';
while(true) loop
wait until bus_indices_begin_rsp_empty_n'event;
if(bus_indices_begin_rsp_empty_n = '1') then
end if;
reg_bus_indices_begin_rsp_empty_n <= bus_indices_begin_rsp_empty_n;
end loop;
end process;
indices_begin_rsp_empty_n <= reg_bus_indices_begin_rsp_empty_n;
AESL_inst_indices_samples : AESL_autobus_indices_samples port map (
clk => AESL_clock,
rst => AESL_reset,
bus_req_RW => bus_indices_samples_req_RW,
bus_req_full_n => bus_indices_samples_req_full_n,
bus_req_RW_en => bus_indices_samples_req_RW_en,
bus_rsp_empty_n => bus_indices_samples_rsp_empty_n,
bus_rsp_read => bus_indices_samples_rsp_read,
bus_address => bus_indices_samples_address,
bus_din => bus_indices_samples_din,
bus_dout => bus_indices_samples_dout,
bus_size => bus_indices_samples_size,
ready => bus_indices_samples_ready,
done => bus_indices_samples_done
);
-- Assignment between dut and bus indices_samples
-- Assign input of bus indices_samples
bus_indices_samples_req_RW <= indices_samples_req_din;
bus_indices_samples_req_RW_en <= indices_samples_req_write and indices_samples_req_full_n;
bus_indices_samples_rsp_read <= indices_samples_rsp_read and indices_samples_rsp_empty_n;
bus_indices_samples_address <= indices_samples_address;
bus_indices_samples_din <= indices_samples_dataout;
bus_indices_samples_size <= indices_samples_size;
bus_indices_samples_ready <= ready;
-- Assign input of dut
indices_samples_datain <= bus_indices_samples_dout;
gen_reg_bus_indices_samples_req_full_n_proc : process
variable rand : T_RANDINT := init_rand(0);
variable rint : INTEGER;
begin
reg_bus_indices_samples_req_full_n <= '0';
while(true) loop
wait until bus_indices_samples_req_full_n'event;
if(bus_indices_samples_req_full_n = '1') then
end if;
reg_bus_indices_samples_req_full_n <= bus_indices_samples_req_full_n;
end loop;
end process;
indices_samples_req_full_n <= reg_bus_indices_samples_req_full_n;
gen_reg_bus_indices_samples_rsp_empty_n_proc : process
variable rand : T_RANDINT := init_rand(0);
variable rint : INTEGER;
begin
reg_bus_indices_samples_rsp_empty_n <= '0';
while(true) loop
wait until bus_indices_samples_rsp_empty_n'event;
if(bus_indices_samples_rsp_empty_n = '1') then
end if;
reg_bus_indices_samples_rsp_empty_n <= bus_indices_samples_rsp_empty_n;
end loop;
end process;
indices_samples_rsp_empty_n <= reg_bus_indices_samples_rsp_empty_n;
AESL_inst_indices_stride : AESL_autobus_indices_stride port map (
clk => AESL_clock,
rst => AESL_reset,
bus_req_RW => bus_indices_stride_req_RW,
bus_req_full_n => bus_indices_stride_req_full_n,
bus_req_RW_en => bus_indices_stride_req_RW_en,
bus_rsp_empty_n => bus_indices_stride_rsp_empty_n,
bus_rsp_read => bus_indices_stride_rsp_read,
bus_address => bus_indices_stride_address,
bus_din => bus_indices_stride_din,
bus_dout => bus_indices_stride_dout,
bus_size => bus_indices_stride_size,
ready => bus_indices_stride_ready,
done => bus_indices_stride_done
);
-- Assignment between dut and bus indices_stride
-- Assign input of bus indices_stride
bus_indices_stride_req_RW <= indices_stride_req_din;
bus_indices_stride_req_RW_en <= indices_stride_req_write and indices_stride_req_full_n;
bus_indices_stride_rsp_read <= indices_stride_rsp_read and indices_stride_rsp_empty_n;
bus_indices_stride_address <= indices_stride_address;
bus_indices_stride_din <= indices_stride_dataout;
bus_indices_stride_size <= indices_stride_size;
bus_indices_stride_ready <= ready;
-- Assign input of dut
indices_stride_datain <= bus_indices_stride_dout;
gen_reg_bus_indices_stride_req_full_n_proc : process
variable rand : T_RANDINT := init_rand(0);
variable rint : INTEGER;
begin
reg_bus_indices_stride_req_full_n <= '0';
while(true) loop
wait until bus_indices_stride_req_full_n'event;
if(bus_indices_stride_req_full_n = '1') then
end if;
reg_bus_indices_stride_req_full_n <= bus_indices_stride_req_full_n;
end loop;
end process;
indices_stride_req_full_n <= reg_bus_indices_stride_req_full_n;
gen_reg_bus_indices_stride_rsp_empty_n_proc : process
variable rand : T_RANDINT := init_rand(0);
variable rint : INTEGER;
begin
reg_bus_indices_stride_rsp_empty_n <= '0';
while(true) loop
wait until bus_indices_stride_rsp_empty_n'event;
if(bus_indices_stride_rsp_empty_n = '1') then
end if;
reg_bus_indices_stride_rsp_empty_n <= bus_indices_stride_rsp_empty_n;
end loop;
end process;
indices_stride_rsp_empty_n <= reg_bus_indices_stride_rsp_empty_n;
gen_assign_i_size_proc : process
begin
wait until (AESL_clock'event and AESL_clock = '1');
wait for 0.45 ns;
i_size <= AESL_REG_i_size;
end process;
gen_assign_begin_index_proc : process
begin
wait until (AESL_clock'event and AESL_clock = '1');
wait for 0.45 ns;
begin_index <= AESL_REG_begin_index;
end process;
read_file_process_begin_index : process
file fp : TEXT;
variable fstatus : FILE_OPEN_STATUS;
variable token_line : LINE;
variable token : STRING(1 to 280);
variable i : INTEGER;
variable transaction_finish : INTEGER;
variable rand : T_RANDINT := init_rand(0);
variable rint : INTEGER;
begin
wait until AESL_reset = '0';
file_open(fstatus, fp, AUTOTB_TVIN_begin_index, READ_MODE);
if(fstatus /= OPEN_OK) then
assert false report "Open file " & AUTOTB_TVIN_begin_index & " failed!!!" severity note;
assert false report "ERROR: Simulation using HLS TB failed." severity failure;
end if;
esl_read_token(fp, token_line, token);
if(token(1 to 13) /= "[[[runtime]]]") then
report "The token is " & token;
assert false report "Illegal format of [[[runtime]]] part in " & AUTOTB_TVIN_begin_index severity note;
assert false report "ERROR: Simulation using HLS TB failed." severity failure;
end if;
esl_read_token(fp, token_line, token);
while(token(1 to 14) /= "[[[/runtime]]]") loop
if(token(1 to 15) /= "[[transaction]]") then
report "The token is " & token;
assert false report "Illegal format of [[transaction]] part in " & AUTOTB_TVIN_begin_index severity note;
assert false report "ERROR: Simulation using HLS TB failed." severity failure;
end if;
esl_read_token(fp, token_line, token); -- Skip transaction number
esl_read_token(fp, token_line, token);
wait until AESL_clock'event and AESL_clock = '1';
wait for 0.2 ns;
while(ready_wire /= '1') loop
wait until AESL_clock'event and AESL_clock = '1';
wait for 0.2 ns;
end loop;
if(token(1 to 16) /= "[[/transaction]]") then
AESL_REG_begin_index := esl_str2lv_hex(token, 16 );
esl_read_token(fp, token_line, token);
end if;
esl_read_token(fp, token_line, token);
end loop;
file_close(fp);
wait;
end process;
gen_assign_begin_sample_proc : process
begin
wait until (AESL_clock'event and AESL_clock = '1');
wait for 0.45 ns;
begin_sample <= AESL_REG_begin_sample;
end process;
read_file_process_begin_sample : process
file fp : TEXT;
variable fstatus : FILE_OPEN_STATUS;
variable token_line : LINE;
variable token : STRING(1 to 280);
variable i : INTEGER;
variable transaction_finish : INTEGER;
variable rand : T_RANDINT := init_rand(0);
variable rint : INTEGER;
begin
wait until AESL_reset = '0';
file_open(fstatus, fp, AUTOTB_TVIN_begin_sample, READ_MODE);
if(fstatus /= OPEN_OK) then
assert false report "Open file " & AUTOTB_TVIN_begin_sample & " failed!!!" severity note;
assert false report "ERROR: Simulation using HLS TB failed." severity failure;
end if;
esl_read_token(fp, token_line, token);
if(token(1 to 13) /= "[[[runtime]]]") then
report "The token is " & token;
assert false report "Illegal format of [[[runtime]]] part in " & AUTOTB_TVIN_begin_sample severity note;
assert false report "ERROR: Simulation using HLS TB failed." severity failure;
end if;
esl_read_token(fp, token_line, token);
while(token(1 to 14) /= "[[[/runtime]]]") loop
if(token(1 to 15) /= "[[transaction]]") then
report "The token is " & token;
assert false report "Illegal format of [[transaction]] part in " & AUTOTB_TVIN_begin_sample severity note;
assert false report "ERROR: Simulation using HLS TB failed." severity failure;
end if;
esl_read_token(fp, token_line, token); -- Skip transaction number
esl_read_token(fp, token_line, token);
wait until AESL_clock'event and AESL_clock = '1';
wait for 0.2 ns;
while(ready_wire /= '1') loop
wait until AESL_clock'event and AESL_clock = '1';
wait for 0.2 ns;
end loop;
if(token(1 to 16) /= "[[/transaction]]") then
AESL_REG_begin_sample := esl_str2lv_hex(token, 16 );
esl_read_token(fp, token_line, token);
end if;
esl_read_token(fp, token_line, token);
end loop;
file_close(fp);
wait;
end process;
gen_assign_end_index_proc : process
begin
wait until (AESL_clock'event and AESL_clock = '1');
wait for 0.45 ns;
end_index <= AESL_REG_end_index;
end process;
read_file_process_end_index : process
file fp : TEXT;
variable fstatus : FILE_OPEN_STATUS;
variable token_line : LINE;
variable token : STRING(1 to 280);
variable i : INTEGER;
variable transaction_finish : INTEGER;
variable rand : T_RANDINT := init_rand(0);
variable rint : INTEGER;
begin
wait until AESL_reset = '0';
file_open(fstatus, fp, AUTOTB_TVIN_end_index, READ_MODE);
if(fstatus /= OPEN_OK) then
assert false report "Open file " & AUTOTB_TVIN_end_index & " failed!!!" severity note;
assert false report "ERROR: Simulation using HLS TB failed." severity failure;
end if;
esl_read_token(fp, token_line, token);
if(token(1 to 13) /= "[[[runtime]]]") then
report "The token is " & token;
assert false report "Illegal format of [[[runtime]]] part in " & AUTOTB_TVIN_end_index severity note;
assert false report "ERROR: Simulation using HLS TB failed." severity failure;
end if;
esl_read_token(fp, token_line, token);
while(token(1 to 14) /= "[[[/runtime]]]") loop
if(token(1 to 15) /= "[[transaction]]") then
report "The token is " & token;
assert false report "Illegal format of [[transaction]] part in " & AUTOTB_TVIN_end_index severity note;
assert false report "ERROR: Simulation using HLS TB failed." severity failure;
end if;
esl_read_token(fp, token_line, token); -- Skip transaction number
esl_read_token(fp, token_line, token);
wait until AESL_clock'event and AESL_clock = '1';
wait for 0.2 ns;
while(ready_wire /= '1') loop
wait until AESL_clock'event and AESL_clock = '1';
wait for 0.2 ns;
end loop;
if(token(1 to 16) /= "[[/transaction]]") then
AESL_REG_end_index := esl_str2lv_hex(token, 16 );
esl_read_token(fp, token_line, token);
end if;
esl_read_token(fp, token_line, token);
end loop;
file_close(fp);
wait;
end process;
gen_assign_end_sample_proc : process
begin
wait until (AESL_clock'event and AESL_clock = '1');
wait for 0.45 ns;
end_sample <= AESL_REG_end_sample;
end process;
read_file_process_end_sample : process
file fp : TEXT;
variable fstatus : FILE_OPEN_STATUS;
variable token_line : LINE;
variable token : STRING(1 to 280);
variable i : INTEGER;
variable transaction_finish : INTEGER;
variable rand : T_RANDINT := init_rand(0);
variable rint : INTEGER;
begin
wait until AESL_reset = '0';
file_open(fstatus, fp, AUTOTB_TVIN_end_sample, READ_MODE);
if(fstatus /= OPEN_OK) then
assert false report "Open file " & AUTOTB_TVIN_end_sample & " failed!!!" severity note;
assert false report "ERROR: Simulation using HLS TB failed." severity failure;
end if;
esl_read_token(fp, token_line, token);
if(token(1 to 13) /= "[[[runtime]]]") then
report "The token is " & token;
assert false report "Illegal format of [[[runtime]]] part in " & AUTOTB_TVIN_end_sample severity note;
assert false report "ERROR: Simulation using HLS TB failed." severity failure;
end if;
esl_read_token(fp, token_line, token);
while(token(1 to 14) /= "[[[/runtime]]]") loop
if(token(1 to 15) /= "[[transaction]]") then
report "The token is " & token;
assert false report "Illegal format of [[transaction]] part in " & AUTOTB_TVIN_end_sample severity note;
assert false report "ERROR: Simulation using HLS TB failed." severity failure;
end if;
esl_read_token(fp, token_line, token); -- Skip transaction number
esl_read_token(fp, token_line, token);
wait until AESL_clock'event and AESL_clock = '1';
wait for 0.2 ns;
while(ready_wire /= '1') loop
wait until AESL_clock'event and AESL_clock = '1';
wait for 0.2 ns;
end loop;
if(token(1 to 16) /= "[[/transaction]]") then
AESL_REG_end_sample := esl_str2lv_hex(token, 16 );
esl_read_token(fp, token_line, token);
end if;
esl_read_token(fp, token_line, token);
end loop;
file_close(fp);
wait;
end process;
gen_assign_stop_on_first_proc : process
begin
wait until (AESL_clock'event and AESL_clock = '1');
wait for 0.45 ns;
stop_on_first <= AESL_REG_stop_on_first;
end process;
read_file_process_stop_on_first : process
file fp : TEXT;
variable fstatus : FILE_OPEN_STATUS;
variable token_line : LINE;
variable token : STRING(1 to 280);
variable i : INTEGER;
variable transaction_finish : INTEGER;
variable rand : T_RANDINT := init_rand(0);
variable rint : INTEGER;
begin
wait until AESL_reset = '0';
file_open(fstatus, fp, AUTOTB_TVIN_stop_on_first, READ_MODE);
if(fstatus /= OPEN_OK) then
assert false report "Open file " & AUTOTB_TVIN_stop_on_first & " failed!!!" severity note;
assert false report "ERROR: Simulation using HLS TB failed." severity failure;
end if;
esl_read_token(fp, token_line, token);
if(token(1 to 13) /= "[[[runtime]]]") then
report "The token is " & token;
assert false report "Illegal format of [[[runtime]]] part in " & AUTOTB_TVIN_stop_on_first severity note;
assert false report "ERROR: Simulation using HLS TB failed." severity failure;
end if;
esl_read_token(fp, token_line, token);
while(token(1 to 14) /= "[[[/runtime]]]") loop
if(token(1 to 15) /= "[[transaction]]") then
report "The token is " & token;
assert false report "Illegal format of [[transaction]] part in " & AUTOTB_TVIN_stop_on_first severity note;
assert false report "ERROR: Simulation using HLS TB failed." severity failure;
end if;
esl_read_token(fp, token_line, token); -- Skip transaction number
esl_read_token(fp, token_line, token);
wait until AESL_clock'event and AESL_clock = '1';
wait for 0.2 ns;
while(ready_wire /= '1') loop
wait until AESL_clock'event and AESL_clock = '1';
wait for 0.2 ns;
end loop;
if(token(1 to 16) /= "[[/transaction]]") then
AESL_REG_stop_on_first := esl_str2lv_hex(token, 1 );
esl_read_token(fp, token_line, token);
end if;
esl_read_token(fp, token_line, token);
end loop;
file_close(fp);
wait;
end process;
gen_assign_accept_proc : process
begin
wait until (AESL_clock'event and AESL_clock = '1');
wait for 0.45 ns;
accept <= AESL_REG_accept;
end process;
read_file_process_accept : process
file fp : TEXT;
variable fstatus : FILE_OPEN_STATUS;
variable token_line : LINE;
variable token : STRING(1 to 280);
variable i : INTEGER;
variable transaction_finish : INTEGER;
variable rand : T_RANDINT := init_rand(0);
variable rint : INTEGER;
begin
wait until AESL_reset = '0';
file_open(fstatus, fp, AUTOTB_TVIN_accept, READ_MODE);
if(fstatus /= OPEN_OK) then
assert false report "Open file " & AUTOTB_TVIN_accept & " failed!!!" severity note;
assert false report "ERROR: Simulation using HLS TB failed." severity failure;
end if;
esl_read_token(fp, token_line, token);
if(token(1 to 13) /= "[[[runtime]]]") then
report "The token is " & token;
assert false report "Illegal format of [[[runtime]]] part in " & AUTOTB_TVIN_accept severity note;
assert false report "ERROR: Simulation using HLS TB failed." severity failure;
end if;
esl_read_token(fp, token_line, token);
while(token(1 to 14) /= "[[[/runtime]]]") loop
if(token(1 to 15) /= "[[transaction]]") then
report "The token is " & token;
assert false report "Illegal format of [[transaction]] part in " & AUTOTB_TVIN_accept severity note;
assert false report "ERROR: Simulation using HLS TB failed." severity failure;
end if;
esl_read_token(fp, token_line, token); -- Skip transaction number
esl_read_token(fp, token_line, token);
wait until AESL_clock'event and AESL_clock = '1';
wait for 0.2 ns;
while(ready_wire /= '1') loop
wait until AESL_clock'event and AESL_clock = '1';
wait for 0.2 ns;
end loop;
if(token(1 to 16) /= "[[/transaction]]") then
AESL_REG_accept := esl_str2lv_hex(token, 1 );
esl_read_token(fp, token_line, token);
end if;
esl_read_token(fp, token_line, token);
end loop;
file_close(fp);
wait;
end process;
write_file_process_ap_return : process
file fp : TEXT;
file fp_size : TEXT;
variable fstatus : FILE_OPEN_STATUS;
variable token_line : LINE;
variable token : STRING(1 to 280);
variable transaction_idx : INTEGER;
variable ap_return_count : INTEGER;
variable hls_stream_size : INTEGER;
variable i : INTEGER;
variable rand : T_RANDINT := init_rand(0);
variable rint : INTEGER;
begin
wait until AESL_reset = '0';
file_open(fstatus, fp, AUTOTB_TVOUT_ap_return_out_wrapc, WRITE_MODE);
if(fstatus /= OPEN_OK) then
assert false report "Open file " & AUTOTB_TVOUT_ap_return_out_wrapc & " failed!!!" severity note;
assert false report "ERROR: Simulation using HLS TB failed." severity failure;
end if;
write(token_line, string'("[[[runtime]]]"));
writeline(fp, token_line);
transaction_idx := 0;
while (transaction_idx /= AUTOTB_TRANSACTION_NUM) loop
write(token_line, string'("[[transaction]] ") & integer'image(transaction_idx));
writeline(fp, token_line);
wait until AESL_clock'event and AESL_clock = '1';
while(AESL_done /= '1') loop
wait until AESL_clock'event and AESL_clock = '1';
end loop;
write(token_line, "0x" & esl_conv_string_hex(ap_return));
writeline(fp, token_line);
transaction_idx := transaction_idx + 1;
write(token_line, string'("[[/transaction]]"));
writeline(fp, token_line);
end loop;
write(token_line, string'("[[[/runtime]]]"));
writeline(fp, token_line);
file_close(fp);
wait;
end process;
generate_AESL_ready_cnt_proc : process
begin
AESL_ready_cnt := 0;
wait until AESL_reset = '0';
while(AESL_ready_cnt /= AUTOTB_TRANSACTION_NUM) loop
while(AESL_ready /= '1') loop
wait until AESL_clock'event and AESL_clock = '1';
wait for 0.4 ns;
end loop;
wait until AESL_clock'event and AESL_clock = '0';
AESL_ready_cnt := AESL_ready_cnt + 1;
wait until AESL_clock'event and AESL_clock = '1';
wait for 0.4 ns;
end loop;
end process;
generate_ready_cnt_proc : process
begin
ready_cnt := 0;
wait until AESL_reset = '0';
while(ready_cnt /= AUTOTB_TRANSACTION_NUM) loop
while(ready /= '1') loop
wait until AESL_clock'event and AESL_clock = '1';
wait for 0.4 ns;
end loop;
wait until AESL_clock'event and AESL_clock = '0';
ready_cnt := ready_cnt + 1;
wait until AESL_clock'event and AESL_clock = '1';
wait for 0.4 ns;
end loop;
wait;
end process;
generate_done_cnt_proc : process
begin
done_cnt := 0;
wait until AESL_reset = '0';
while(done_cnt /= AUTOTB_TRANSACTION_NUM) loop
while(AESL_done /= '1') loop
wait until AESL_clock'event and AESL_clock = '1';
wait for 0.4 ns;
end loop;
wait until AESL_clock'event and AESL_clock = '0';
done_cnt := done_cnt + 1;
wait until AESL_clock'event and AESL_clock = '1';
wait for 0.4 ns;
end loop;
wait until AESL_clock'event and AESL_clock = '1';
wait for 0.4 ns;
assert false report "simulation done!" severity note;
assert false report "NORMAL EXIT (note: failure is to force the simulator to stop)" severity failure;
wait;
end process;
gen_clock_proc : process
begin
AESL_clock <= '0';
while(true) loop
wait for (AUTOTB_CLOCK_PERIOD/2.0);
AESL_clock <= not AESL_clock;
end loop;
wait;
end process;
gen_reset_proc : process
variable rand : T_RANDINT := init_rand(0);
variable rint : INTEGER;
begin
rst <= '1';
wait for 100 ns;
for i in 1 to 3 loop
wait until AESL_clock'event and AESL_clock = '1';
end loop;
rst <= '0';
wait;
end process;
gen_start_proc : process
variable rand : T_RANDINT := init_rand(0);
variable rint : INTEGER;
begin
start <= '0';
ce <= '1';
wait until AESL_reset = '0';
wait until (AESL_clock'event and AESL_clock = '1');
start <= '1';
while(ready_cnt /= AUTOTB_TRANSACTION_NUM + 1) loop
wait until (AESL_clock'event and AESL_clock = '1');
if(AESL_ready = '1') then
start <= '0';
start <= '1';
end if;
end loop;
start <= '0';
wait;
end process;
gen_continue_proc : process(AESL_done)
begin
continue <= AESL_done;
end process;
gen_ready_initial_proc : process
begin
ready_initial <= '0';
wait until AESL_start = '1';
ready_initial <= '1';
wait until AESL_clock'event and AESL_clock = '1';
ready_initial <= '0';
wait;
end process;
gen_AESL_ready_delay_proc : process(AESL_clock)
begin
if (AESL_clock'event and AESL_clock = '1') then
if(AESL_reset = '1') then
AESL_ready_delay <= '0';
else
AESL_ready_delay <= AESL_ready;
end if;
end if;
end process;
ready_last_n_proc : process
begin
ready_last_n <= '1';
while(ready_cnt /= AUTOTB_TRANSACTION_NUM) loop
wait until AESL_clock'event and AESL_clock = '1';
end loop;
ready_last_n <= '0';
wait;
end process;
gen_ready_delay_n_last_proc : process(AESL_clock)
begin
if (AESL_clock'event and AESL_clock = '1') then
if(AESL_reset = '1') then
ready_delay_last_n <= '0';
else
ready_delay_last_n <= ready_last_n;
end if;
end if;
end process;
ready <= (ready_initial or AESL_ready_delay);
ready_wire <= ready_initial or AESL_ready_delay;
gen_done_delay_last_n_proc : process
begin
done_delay_last_n <= '1';
while(done_cnt /= AUTOTB_TRANSACTION_NUM) loop
wait until (AESL_clock'event and AESL_clock = '1');
end loop;
done_delay_last_n <= '0';
wait;
end process;
gen_done_delay_proc : process(AESL_clock)
begin
if (AESL_clock'event and AESL_clock = '1') then
if(AESL_reset = '1') then
AESL_done_delay <= '0';
AESL_done_delay2 <= '0';
else
AESL_done_delay <= AESL_done and done_delay_last_n;
AESL_done_delay2 <= AESL_done_delay;
end if;
end if;
end process;
gen_interface_done : process(ready, AESL_done_delay)
begin
if(ready_cnt > 0 and ready_cnt < AUTOTB_TRANSACTION_NUM) then
interface_done <= ready;
elsif(ready_cnt = AUTOTB_TRANSACTION_NUM) then
interface_done <= AESL_done_delay;
else
interface_done <= '0';
end if;
end process;
gen_clock_counter_proc : process(AESL_clock)
begin
if (AESL_clock'event and AESL_clock = '1') then
if(AESL_reset = '1') then
AESL_clk_counter := 0;
else
AESL_clk_counter := AESL_clk_counter + 1;
end if;
end if;
end process;
gen_mLatcnterout_proc : process(AESL_clock)
begin
if (AESL_clock'event and AESL_clock = '1') then
if(AESL_reset = '1') then
AESL_mLatCnterOut_addr := 0;
AESL_mLatCnterOut(AESL_mLatCnterOut_addr) := AESL_clk_counter + 1 ;
else
if (AESL_done = '1' and AESL_mLatCnterOut_addr < AUTOTB_TRANSACTION_NUM + 1) then
AESL_mLatCnterOut(AESL_mLatCnterOut_addr) := AESL_clk_counter;
AESL_mLatCnterOut_addr := AESL_mLatCnterOut_addr + 1;
end if;
end if;
end if;
end process;
gen_mLatcnterin_proc : process(AESL_clock)
begin
if (AESL_clock'event and AESL_clock = '1') then
if(AESL_reset = '1') then
AESL_mLatCnterIn_addr := 0;
else
if (AESL_start = '1' and AESL_mLatCnterIn_addr = 0) then
AESL_mLatCnterIn(AESL_mLatCnterIn_addr) := AESL_clk_counter;
AESL_mLatCnterIn_addr := AESL_mLatCnterIn_addr + 1;
end if;
if (AESL_ready = '1' and AESL_mLatCnterIn_addr < AUTOTB_TRANSACTION_NUM + 1 ) then
AESL_mLatCnterIn(AESL_mLatCnterIn_addr) := AESL_clk_counter;
AESL_mLatCnterIn_addr := AESL_mLatCnterIn_addr + 1;
end if;
end if;
end if;
end process;
gen_performance_check_proc : process
variable transaction_counter : INTEGER;
variable i : INTEGER;
file fp : TEXT;
variable fstatus : FILE_OPEN_STATUS;
variable token_line : LINE;
variable token : STRING(1 to 1024);
variable latthistime : INTEGER;
variable lattotal : INTEGER;
variable latmax : INTEGER;
variable latmin : INTEGER;
variable thrthistime : INTEGER;
variable thrtotal : INTEGER;
variable thrmax : INTEGER;
variable thrmin : INTEGER;
variable lataver : INTEGER;
variable thraver : INTEGER;
type latency_record is array(0 to AUTOTB_TRANSACTION_NUM + 1) of INTEGER;
variable lat_array : latency_record;
variable thr_array : latency_record;
begin
i := 0;
lattotal := 0;
latmax := 0;
latmin := 16#7fffffff#;
lataver := 0;
thrtotal := 0;
thrmax := 0;
thrmin := 16#7fffffff#;
thraver := 0;
wait until (AESL_clock'event and AESL_clock = '1');
wait until (AESL_reset = '0');
while (done_cnt /= AUTOTB_TRANSACTION_NUM) loop
wait until (AESL_clock'event and AESL_clock = '1');
end loop;
wait for 0.001 ns;
if (AESL_mLatCnterIn_addr = 1 or AESL_mLatCnterIn_addr = 0 ) then
latmax := 0;
latmin := 0;
lataver := 0;
thrmax := 0;
thrmin := 0;
thraver := 0;
lat_array(0) := 0;
thr_array(0) := 0;
elsif (AESL_mLatCnterOut_addr = 1 or AESL_mLatCnterOut_addr = 0 ) then
latmax := AESL_mLatCnterOut(0) - AESL_mLatCnterIn(0);
latmin := AESL_mLatCnterOut(0) - AESL_mLatCnterIn(0);
lataver := AESL_mLatCnterOut(0) - AESL_mLatCnterIn(0);
thrmax := AESL_mLatCnterIn(1) - AESL_mLatCnterIn(0) + 1;
thrmin := AESL_mLatCnterIn(1) - AESL_mLatCnterIn(0) + 1;
thraver := AESL_mLatCnterIn(1) - AESL_mLatCnterIn(0) + 1;
lat_array(0) := lataver;
thr_array(0) := thraver;
else
-- LATENCY
for i in 0 to AESL_mLatCnterOut_addr - 1 loop
latthistime := AESL_mLatCnterOut(i) - AESL_mLatCnterIn(i) ;
if ( i > 0 ) then
if (latthistime - 1 < 0) then
latthistime := 0;
else
latthistime := latthistime - 1;
end if;
end if;
lattotal := lattotal + latthistime;
lat_array(i) := latthistime;
if (latthistime > latmax) then
latmax := latthistime;
end if;
if (latthistime < latmin) then
latmin := latthistime;
end if;
end loop;
-- II
for i in 0 to AESL_mLatCnterIn_addr - 2 loop
thrthistime := AESL_mLatCnterIn(i + 1) - AESL_mLatCnterIn(i);
if ( i = 0 ) then
thrthistime := thrthistime + 1;
end if;
thrtotal := thrtotal + thrthistime;
thr_array(i) := thrthistime;
if (thrthistime > thrmax) then
thrmax := thrthistime;
end if;
if (thrthistime < thrmin) then
thrmin := thrthistime;
end if;
end loop;
thr_array(AESL_mLatCnterIn_addr - 1) := 0;
lataver := lattotal / ( AESL_mLatCnterOut_addr);
thraver := thrtotal / ( AESL_mLatCnterIn_addr - 1 );
end if;
file_open(fstatus, fp, AUTOTB_LAT_RESULT_FILE, WRITE_MODE);
if(fstatus /= OPEN_OK) then
assert false report "Open file " & AUTOTB_LAT_RESULT_FILE & " failed!!!" severity note;
assert false report "ERROR: Simulation using HLS TB failed." severity failure;
end if;
write(token_line, "$MAX_LATENCY = " & '"' & integer'image(latmax) & '"');
writeline(fp, token_line);
write(token_line, "$MIN_LATENCY = " & '"' & integer'image(latmin) & '"');
writeline(fp, token_line);
write(token_line, "$AVER_LATENCY = " & '"' & integer'image(lataver) & '"');
writeline(fp, token_line);
write(token_line, "$MAX_THROUGHPUT = " & '"' & integer'image(thrmax) & '"');
writeline(fp, token_line);
write(token_line, "$MIN_THROUGHPUT = " & '"' & integer'image(thrmin) & '"');
writeline(fp, token_line);
write(token_line, "$AVER_THROUGHPUT = " & '"' & integer'image(thraver) & '"');
writeline(fp, token_line);
file_close(fp);
file_open(fstatus, fp, AUTOTB_PER_RESULT_TRANS_FILE, WRITE_MODE);
if(fstatus /= OPEN_OK) then
assert false report "Open file " & AUTOTB_PER_RESULT_TRANS_FILE & " failed!!!" severity note;
assert false report "ERROR: Simulation using HLS TB failed." severity failure;
end if;
write(token_line,string'(" latency interval"));
writeline(fp, token_line);
for i in 0 to AESL_mLatCnterOut_addr - 1 loop
write(token_line,"transaction " & integer'image(i) & " " & integer'image(lat_array(i) ) & " " & integer'image(thr_array(i) ) );
writeline(fp, token_line);
end loop;
file_close(fp);
wait;
end process;
end behav;
| lgpl-3.0 | 47703e8213cd1ac00727ec32ddacee69 | 0.594328 | 3.314455 | false | false | false | false |
wsoltys/AtomFpga | src/AtomGodilVideo/src/VGA80x40/vga80x40.vhd | 1 | 13,255 | -- Hi Emacs, this is -*- mode: vhdl; -*-
----------------------------------------------------------------------------------------------------
--
-- Monocrome Text Mode Video Controller VHDL Macro
-- 80x40 characters. Pixel resolution is 640x480/60Hz
--
-- Copyright (c) 2007 Javier Valcarce Garca, [email protected]
-- $Id$
--
----------------------------------------------------------------------------------------------------
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU Lesser General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU Lesser General Public License for more details.
--
-- You should have received a copy of the GNU Lesser General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
----------------------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity vga80x40 is
port (
reset : in std_logic;
clk25MHz : in std_logic;
TEXT_A : out std_logic_vector(12 downto 0); -- text buffer
TEXT_D : in std_logic_vector(07 downto 0);
FONT_A : out std_logic_vector(11 downto 0); -- font buffer
FONT_D : in std_logic_vector(07 downto 0);
--
ocrx : in std_logic_vector(07 downto 0); -- OUTPUT regs
ocry : in std_logic_vector(07 downto 0);
octl : in std_logic_vector(07 downto 0);
octl2 : in std_logic_vector(07 downto 0);
--
R : out std_logic;
G : out std_logic;
B : out std_logic;
hsync : out std_logic;
vsync : out std_logic
);
end vga80x40;
architecture rtl of vga80x40 is
signal R_int : std_logic;
signal G_int : std_logic;
signal B_int : std_logic;
signal hsync_int : std_logic;
signal vsync_int : std_logic;
signal blank : std_logic;
signal hctr : integer range 799 downto 0;
signal vctr : integer range 525 downto 0;
-- character/pixel position on the screen
signal scry : integer range 039 downto 0; -- chr row < 40 (6 bits)
signal scry_r: integer range 039 downto 0; -- chr row < 40 (6 bits)
signal scrx : integer range 079 downto 0; -- chr col < 80 (7 bits)
signal scrx_r: integer range 079 downto 0; -- chr col < 80 (7 bits)
signal chry : integer range 011 downto 0; -- chr high < 12 (4 bits)
signal chry_r: integer range 011 downto 0; -- chr high < 12 (4 bits)
signal chrx : integer range 007 downto 0; -- chr width < 08 (3 bits)
signal losr_ce : std_logic;
signal losr_ld : std_logic;
signal losr_do : std_logic;
signal y : std_logic; -- character luminance pixel value (0 or 1)
signal ys : std_logic; -- character luminance pixel value (0 or 1) after semigraphic attribute
signal yu : std_logic; -- character luminance pixel value (0 or 1) after underline attribute
signal ya : std_logic; -- character luminance pixel value (0 or 1) after all attrributes
-- Data byte for the current character (before the font mapping) used for semi graphics
signal data : std_logic_vector(7 downto 0);
-- Colour attributes byte for the current character
signal attrtmp : std_logic_vector(7 downto 0);
signal attr : std_logic_vector(7 downto 0);
-- control io register
signal ctl : std_logic_vector(7 downto 0);
signal vga_en : std_logic;
signal cur_en : std_logic;
signal cur_mode : std_logic;
signal cur_blink : std_logic;
signal ctl_r : std_logic;
signal ctl_g : std_logic;
signal ctl_b : std_logic;
signal ctl_r_bg : std_logic;
signal ctl_g_bg : std_logic;
signal ctl_b_bg : std_logic;
signal ctl_attr : std_logic;
component ctrm
generic (
M : integer := 08);
port (
reset : in std_logic; -- asyncronous reset
clk : in std_logic;
ce : in std_logic; -- enable counting
rs : in std_logic; -- syncronous reset
do : out integer range (M-1) downto 0
);
end component;
component losr
generic (
N : integer := 04);
port (
reset : in std_logic;
clk : in std_logic;
load : in std_logic;
ce : in std_logic;
do : out std_logic;
di : in std_logic_vector(N-1 downto 0));
end component;
begin
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- hsync generator, initialized with '1'
process (reset, clk25MHz)
begin
if reset = '1' then
hsync_int <= '1';
elsif rising_edge(clk25MHz) then
if (hctr > 663) and (hctr < 757) then
hsync_int <= '0';
else
hsync_int <= '1';
end if;
end if;
end process;
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- vsync generator, initialized with '1'
process (reset, clk25MHz)
begin
if reset = '1' then
vsync_int <= '1';
elsif rising_edge(clk25MHz) then
if (vctr > 499) and (vctr < 502) then
vsync_int <= '0';
else
vsync_int <= '1';
end if;
end if;
end process;
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Blank signal, 0 = no draw, 1 = visible/draw zone
-- Proboscide99 31/08/08
-- blank <= '0' when (hctr > 639) or (vctr > 479) else '1';
blank <= '0' when (hctr < 8) or (hctr > 647) or (vctr > 479) else '1';
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- flip-flips for sync of R, G y B signal, initialized with '0'
process (reset, clk25MHz)
begin
if reset = '1' then
R <= '0';
G <= '0';
B <= '0';
elsif rising_edge(clk25MHz) then
R <= R_int;
G <= G_int;
B <= B_int;
end if;
end process;
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Control register. Individual control signal
cur_mode <= octl(4);
cur_blink <= octl(5);
cur_en <= octl(6);
vga_en <= octl(7);
ctl_attr <= octl(3);
ctl_r <= octl(2);
ctl_g <= octl(1);
ctl_b <= octl(0);
ctl_r_bg <= octl2(2);
ctl_g_bg <= octl2(1);
ctl_b_bg <= octl2(0);
-- counters, hctr, vctr, srcx, srcy, chrx, chry
-- TODO: OPTIMIZE THIS
counters : block
signal hctr_ce : std_logic;
signal hctr_rs : std_logic;
signal vctr_ce : std_logic;
signal vctr_rs : std_logic;
signal chrx_ce : std_logic;
signal chrx_rs : std_logic;
signal chry_ce : std_logic;
signal chry_rs : std_logic;
signal scrx_ce : std_logic;
signal scrx_rs : std_logic;
signal scry_ce : std_logic;
signal scry_rs : std_logic;
signal hctr_639 : std_logic;
signal vctr_479 : std_logic;
signal chrx_007 : std_logic;
signal chry_011 : std_logic;
signal scrx_079 : std_logic;
signal read_attr : std_logic;
-- RAM read, ROM read
signal ram_tmp : integer range 6400 downto 0; --13 bits
signal rom_tmp : integer range 3070 downto 0;
begin
U_HCTR : ctrm generic map (M => 800) port map (
reset =>reset, clk=>clk25MHz, ce =>hctr_ce, rs =>hctr_rs, do => hctr);
U_VCTR : ctrm generic map (M => 526) port map (reset, clk25MHz, vctr_ce, vctr_rs, vctr);
hctr_ce <= '1';
hctr_rs <= '1' when hctr = 799 else '0';
vctr_ce <= '1' when hctr = 663 else '0';
vctr_rs <= '1' when vctr = 525 else '0';
U_CHRX: ctrm generic map (M => 008) port map (reset, clk25MHz, chrx_ce, chrx_rs, chrx);
U_CHRY: ctrm generic map (M => 012) port map (reset, clk25MHz, chry_ce, chry_rs, chry);
U_SCRX: ctrm generic map (M => 080) port map (reset, clk25MHz, scrx_ce, scrx_rs, scrx);
U_SCRY: ctrm generic map (M => 040) port map (reset, clk25MHz, scry_ce, scry_rs, scry);
hctr_639 <= '1' when hctr = 639 else '0';
vctr_479 <= '1' when vctr = 479 else '0';
chrx_007 <= '1' when chrx = 007 else '0';
chry_011 <= '1' when chry = 011 else '0';
scrx_079 <= '1' when scrx = 079 else '0';
chrx_rs <= chrx_007 or hctr_639;
chrx_ce <= '1' and blank;
chry_rs <= chry_011 or vctr_479;
chry_ce <= hctr_639 and blank;
scrx_ce <= chrx_007;
scrx_rs <= hctr_639;
scry_ce <= chry_011 and hctr_639;
scry_rs <= vctr_479;
-- Proboscide99 31/08/08
-- ram_tmp <= scry * 80 + scrx + 1 when ((scrx_079 = '0')) else
-- scry * 80 when ((chry_011 = '0') and (scrx_079 = '1')) else
-- 0 when ((chry_011 = '1') and (scrx_079 = '1'));
read_attr <= '1' when chrx = 000 or chrx = 001 or chrx = 002 or chrx = 003 else '0';
ram_tmp <= scry * 80 + scrx + 3200 when read_attr = '1' else scry * 80 + scrx;
TEXT_A <= std_logic_vector(TO_UNSIGNED(ram_tmp, 13));
rom_tmp <= TO_INTEGER(unsigned(TEXT_D)) * 16 + chry;
FONT_A <= std_logic_vector(TO_UNSIGNED(rom_tmp, 12));
end block;
process (clk25MHz)
begin
if rising_edge(clk25MHz) then
if (chrx = 003) then
attrtmp <= TEXT_D;
end if;
if (chrx = 007) then
attr <= attrtmp;
data <= TEXT_D;
end if;
if (losr_ld = '1') then
scrx_r <= scrx;
scry_r <= scry;
chry_r <= chry;
end if;
end if;
end process;
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
U_LOSR : losr generic map (N => 8)
port map (reset, clk25MHz, losr_ld, losr_ce, losr_do, FONT_D);
losr_ce <= blank;
losr_ld <= '1' when (chrx = 007) else '0';
-- Apply the underline attriute to the luminance
yu <= not y when ((attr(3) = '1') and (chry_r = 0010)) else y;
-- Generate the semigraphic pixel data
ys <= '1' when
(data(0) = '1' and (chrx >= 004) and (chry_r >= 008)) or
(data(1) = '1' and (chrx < 004) and (chry_r >= 008)) or
(data(2) = '1' and (chrx >= 004) and (chry_r >= 004) and (chry_r < 008)) or
(data(3) = '1' and (chrx < 004) and (chry_r >= 004) and (chry_r < 008)) or
(data(4) = '1' and (chrx >= 004) and (chry_r < 004)) or
(data(5) = '1' and (chrx < 004) and (chry_r < 004)) else '0';
ya <= ys when (attr(7) = '1') else yu;
-- video out, vga_en control signal enable/disable vga signal
R_int <= (((not ctl_attr) and ((y and ctl_r) or ((not y) and ctl_r_bg))) or
(ctl_attr and ((ya and attr(2)) or ((not ya) and attr(6))))) and blank;
G_int <= (((not ctl_attr) and ((y and ctl_g) or ((not y) and ctl_g_bg))) or
(ctl_attr and ((ya and attr(1)) or ((not ya) and attr(5))))) and blank;
B_int <= (((not ctl_attr) and ((y and ctl_b) or ((not y) and ctl_b_bg))) or
(ctl_attr and ((ya and attr(0)) or ((not ya) and attr(4))))) and blank;
hsync <= hsync_int and vga_en;
vsync <= vsync_int and vga_en;
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Hardware Cursor
hw_cursor : block
signal small : std_logic;
signal curen2 : std_logic;
signal slowclk : std_logic;
signal curpos : std_logic;
signal yint : std_logic;
signal crx_tmp : integer range 079 downto 0;
signal cry_tmp : integer range 039 downto 0;
signal crx : integer range 079 downto 0;
signal cry : integer range 039 downto 0;
signal counter : unsigned(22 downto 0);
begin
-- slowclk for blink hardware cursor
counter <= counter + 1 when rising_edge(clk25MHz);
slowclk <= counter(22); --2.98Hz
crx <= TO_INTEGER(unsigned(ocrx(6 downto 0)));
cry <= TO_INTEGER(unsigned(ocry(5 downto 0)));
--
curpos <= '1' when (scry_r = cry) and (scrx_r = crx) else '0';
small <= '1' when (chry_r > 8) else '0';
curen2 <= (slowclk or (not cur_blink)) and cur_en;
yint <= '1' when cur_mode = '0' else small;
y <= (yint and curpos and curen2) xor losr_do;
end block;
end rtl;
| apache-2.0 | 68bc2e28f149132122e309b0f3a8ae4f | 0.501471 | 3.468987 | false | false | false | false |
grwlf/vsim | vhdl_ct/ct00381.vhd | 1 | 101,079 | -- NEED RESULT: ARCH00381.P1: Multi inertial transactions occurred on concurrent signal asg passed
-- NEED RESULT: ARCH00381.P2: Multi inertial transactions occurred on concurrent signal asg passed
-- NEED RESULT: ARCH00381.P3: Multi inertial transactions occurred on concurrent signal asg passed
-- NEED RESULT: ARCH00381.P4: Multi inertial transactions occurred on concurrent signal asg passed
-- NEED RESULT: ARCH00381.P5: Multi inertial transactions occurred on concurrent signal asg passed
-- NEED RESULT: ARCH00381.P6: Multi inertial transactions occurred on concurrent signal asg passed
-- NEED RESULT: ARCH00381.P7: Multi inertial transactions occurred on concurrent signal asg passed
-- NEED RESULT: ARCH00381.P8: Multi inertial transactions occurred on concurrent signal asg passed
-- NEED RESULT: ARCH00381.P9: Multi inertial transactions occurred on concurrent signal asg passed
-- NEED RESULT: ARCH00381.P10: Multi inertial transactions occurred on concurrent signal asg passed
-- NEED RESULT: ARCH00381.P11: Multi inertial transactions occurred on concurrent signal asg passed
-- NEED RESULT: ARCH00381.P12: Multi inertial transactions occurred on concurrent signal asg passed
-- NEED RESULT: ARCH00381.P13: Multi inertial transactions occurred on concurrent signal asg passed
-- NEED RESULT: ARCH00381.P14: Multi inertial transactions occurred on concurrent signal asg passed
-- NEED RESULT: ARCH00381.P15: Multi inertial transactions occurred on concurrent signal asg passed
-- NEED RESULT: ARCH00381.P16: Multi inertial transactions occurred on concurrent signal asg passed
-- NEED RESULT: ARCH00381.P17: Multi inertial transactions occurred on concurrent signal asg passed
-- NEED RESULT: ARCH00381: One inertial transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00381: One inertial transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00381: One inertial transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00381: One inertial transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00381: One inertial transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00381: One inertial transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00381: One inertial transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00381: One inertial transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00381: One inertial transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00381: One inertial transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00381: One inertial transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00381: One inertial transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00381: One inertial transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00381: One inertial transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00381: One inertial transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00381: One inertial transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00381: One inertial transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00381: Old transactions were removed on a concurrent signal asg passed
-- NEED RESULT: ARCH00381: Old transactions were removed on a concurrent signal asg passed
-- NEED RESULT: ARCH00381: Old transactions were removed on a concurrent signal asg passed
-- NEED RESULT: ARCH00381: Old transactions were removed on a concurrent signal asg passed
-- NEED RESULT: ARCH00381: Old transactions were removed on a concurrent signal asg passed
-- NEED RESULT: ARCH00381: Old transactions were removed on a concurrent signal asg passed
-- NEED RESULT: ARCH00381: Old transactions were removed on a concurrent signal asg passed
-- NEED RESULT: ARCH00381: Old transactions were removed on a concurrent signal asg passed
-- NEED RESULT: ARCH00381: Old transactions were removed on a concurrent signal asg passed
-- NEED RESULT: ARCH00381: Old transactions were removed on a concurrent signal asg passed
-- NEED RESULT: ARCH00381: Old transactions were removed on a concurrent signal asg passed
-- NEED RESULT: ARCH00381: Old transactions were removed on a concurrent signal asg passed
-- NEED RESULT: ARCH00381: Old transactions were removed on a concurrent signal asg passed
-- NEED RESULT: ARCH00381: Old transactions were removed on a concurrent signal asg passed
-- NEED RESULT: ARCH00381: Old transactions were removed on a concurrent signal asg passed
-- NEED RESULT: ARCH00381: Old transactions were removed on a concurrent signal asg passed
-- NEED RESULT: ARCH00381: Old transactions were removed on a concurrent signal asg passed
-- NEED RESULT: ARCH00381: One inertial transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00381: One inertial transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00381: One inertial transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00381: One inertial transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00381: One inertial transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00381: One inertial transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00381: One inertial transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00381: One inertial transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00381: One inertial transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00381: One inertial transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00381: One inertial transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00381: One inertial transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00381: One inertial transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00381: One inertial transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00381: One inertial transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00381: One inertial transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00381: One inertial transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00381: Inertial semantics check on a concurrent signal asg passed
-- NEED RESULT: ARCH00381: Inertial semantics check on a concurrent signal asg passed
-- NEED RESULT: ARCH00381: Inertial semantics check on a concurrent signal asg passed
-- NEED RESULT: ARCH00381: Inertial semantics check on a concurrent signal asg passed
-- NEED RESULT: ARCH00381: Inertial semantics check on a concurrent signal asg passed
-- NEED RESULT: ARCH00381: Inertial semantics check on a concurrent signal asg passed
-- NEED RESULT: ARCH00381: Inertial semantics check on a concurrent signal asg passed
-- NEED RESULT: ARCH00381: Inertial semantics check on a concurrent signal asg passed
-- NEED RESULT: ARCH00381: Inertial semantics check on a concurrent signal asg passed
-- NEED RESULT: ARCH00381: Inertial semantics check on a concurrent signal asg passed
-- NEED RESULT: ARCH00381: Inertial semantics check on a concurrent signal asg passed
-- NEED RESULT: ARCH00381: Inertial semantics check on a concurrent signal asg passed
-- NEED RESULT: ARCH00381: Inertial semantics check on a concurrent signal asg passed
-- NEED RESULT: ARCH00381: Inertial semantics check on a concurrent signal asg passed
-- NEED RESULT: ARCH00381: Inertial semantics check on a concurrent signal asg passed
-- NEED RESULT: ARCH00381: Inertial semantics check on a concurrent signal asg passed
-- NEED RESULT: ARCH00381: Inertial semantics check on a concurrent signal asg passed
-- NEED RESULT: P17: Inertial transactions completed entirely passed
-- NEED RESULT: P16: Inertial transactions completed entirely passed
-- NEED RESULT: P15: Inertial transactions completed entirely passed
-- NEED RESULT: P14: Inertial transactions completed entirely passed
-- NEED RESULT: P13: Inertial transactions completed entirely passed
-- NEED RESULT: P12: Inertial transactions completed entirely passed
-- NEED RESULT: P11: Inertial transactions completed entirely passed
-- NEED RESULT: P10: Inertial transactions completed entirely passed
-- NEED RESULT: P9: Inertial transactions completed entirely passed
-- NEED RESULT: P8: Inertial transactions completed entirely passed
-- NEED RESULT: P7: Inertial transactions completed entirely passed
-- NEED RESULT: P6: Inertial transactions completed entirely passed
-- NEED RESULT: P5: Inertial transactions completed entirely passed
-- NEED RESULT: P4: Inertial transactions completed entirely passed
-- NEED RESULT: P3: Inertial transactions completed entirely passed
-- NEED RESULT: P2: Inertial transactions completed entirely passed
-- NEED RESULT: P1: Inertial transactions completed entirely passed
-------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
-------------------------------------------------------------------------------
--
-- TEST NAME:
--
-- CT00381
--
-- AUTHOR:
--
-- G. Tominovich
--
-- TEST OBJECTIVES:
--
-- 9.5 (3)
-- 9.5.2 (1)
--
-- DESIGN UNIT ORDERING:
--
-- ENT00381(ARCH00381)
-- ENT00381_Test_Bench(ARCH00381_Test_Bench)
--
-- REVISION HISTORY:
--
-- 30-JUL-1987 - initial revision
--
-- NOTES:
--
-- self-checking
-- automatically generated
--
use WORK.STANDARD_TYPES.all ;
entity ENT00381 is
end ENT00381 ;
--
--
architecture ARCH00381 of ENT00381 is
subtype chk_sig_type is integer range -1 to 100 ;
signal chk_boolean : chk_sig_type := -1 ;
signal chk_bit : chk_sig_type := -1 ;
signal chk_severity_level : chk_sig_type := -1 ;
signal chk_character : chk_sig_type := -1 ;
signal chk_st_enum1 : chk_sig_type := -1 ;
signal chk_integer : chk_sig_type := -1 ;
signal chk_st_int1 : chk_sig_type := -1 ;
signal chk_time : chk_sig_type := -1 ;
signal chk_st_phys1 : chk_sig_type := -1 ;
signal chk_real : chk_sig_type := -1 ;
signal chk_st_real1 : chk_sig_type := -1 ;
signal chk_st_rec1 : chk_sig_type := -1 ;
signal chk_st_rec2 : chk_sig_type := -1 ;
signal chk_st_rec3 : chk_sig_type := -1 ;
signal chk_st_arr1 : chk_sig_type := -1 ;
signal chk_st_arr2 : chk_sig_type := -1 ;
signal chk_st_arr3 : chk_sig_type := -1 ;
--
subtype chk_time_type is Time ;
signal s_boolean_savt : chk_time_type := 0 ns ;
signal s_bit_savt : chk_time_type := 0 ns ;
signal s_severity_level_savt : chk_time_type := 0 ns ;
signal s_character_savt : chk_time_type := 0 ns ;
signal s_st_enum1_savt : chk_time_type := 0 ns ;
signal s_integer_savt : chk_time_type := 0 ns ;
signal s_st_int1_savt : chk_time_type := 0 ns ;
signal s_time_savt : chk_time_type := 0 ns ;
signal s_st_phys1_savt : chk_time_type := 0 ns ;
signal s_real_savt : chk_time_type := 0 ns ;
signal s_st_real1_savt : chk_time_type := 0 ns ;
signal s_st_rec1_savt : chk_time_type := 0 ns ;
signal s_st_rec2_savt : chk_time_type := 0 ns ;
signal s_st_rec3_savt : chk_time_type := 0 ns ;
signal s_st_arr1_savt : chk_time_type := 0 ns ;
signal s_st_arr2_savt : chk_time_type := 0 ns ;
signal s_st_arr3_savt : chk_time_type := 0 ns ;
--
subtype chk_cnt_type is Integer ;
signal s_boolean_cnt : chk_cnt_type := 0 ;
signal s_bit_cnt : chk_cnt_type := 0 ;
signal s_severity_level_cnt : chk_cnt_type := 0 ;
signal s_character_cnt : chk_cnt_type := 0 ;
signal s_st_enum1_cnt : chk_cnt_type := 0 ;
signal s_integer_cnt : chk_cnt_type := 0 ;
signal s_st_int1_cnt : chk_cnt_type := 0 ;
signal s_time_cnt : chk_cnt_type := 0 ;
signal s_st_phys1_cnt : chk_cnt_type := 0 ;
signal s_real_cnt : chk_cnt_type := 0 ;
signal s_st_real1_cnt : chk_cnt_type := 0 ;
signal s_st_rec1_cnt : chk_cnt_type := 0 ;
signal s_st_rec2_cnt : chk_cnt_type := 0 ;
signal s_st_rec3_cnt : chk_cnt_type := 0 ;
signal s_st_arr1_cnt : chk_cnt_type := 0 ;
signal s_st_arr2_cnt : chk_cnt_type := 0 ;
signal s_st_arr3_cnt : chk_cnt_type := 0 ;
--
type select_type is range 1 to 6 ;
signal boolean_select : select_type := 1 ;
signal bit_select : select_type := 1 ;
signal severity_level_select : select_type := 1 ;
signal character_select : select_type := 1 ;
signal st_enum1_select : select_type := 1 ;
signal integer_select : select_type := 1 ;
signal st_int1_select : select_type := 1 ;
signal time_select : select_type := 1 ;
signal st_phys1_select : select_type := 1 ;
signal real_select : select_type := 1 ;
signal st_real1_select : select_type := 1 ;
signal st_rec1_select : select_type := 1 ;
signal st_rec2_select : select_type := 1 ;
signal st_rec3_select : select_type := 1 ;
signal st_arr1_select : select_type := 1 ;
signal st_arr2_select : select_type := 1 ;
signal st_arr3_select : select_type := 1 ;
--
signal s_boolean : boolean
:= c_boolean_1 ;
signal s_bit : bit
:= c_bit_1 ;
signal s_severity_level : severity_level
:= c_severity_level_1 ;
signal s_character : character
:= c_character_1 ;
signal s_st_enum1 : st_enum1
:= c_st_enum1_1 ;
signal s_integer : integer
:= c_integer_1 ;
signal s_st_int1 : st_int1
:= c_st_int1_1 ;
signal s_time : time
:= c_time_1 ;
signal s_st_phys1 : st_phys1
:= c_st_phys1_1 ;
signal s_real : real
:= c_real_1 ;
signal s_st_real1 : st_real1
:= c_st_real1_1 ;
signal s_st_rec1 : st_rec1
:= c_st_rec1_1 ;
signal s_st_rec2 : st_rec2
:= c_st_rec2_1 ;
signal s_st_rec3 : st_rec3
:= c_st_rec3_1 ;
signal s_st_arr1 : st_arr1
:= c_st_arr1_1 ;
signal s_st_arr2 : st_arr2
:= c_st_arr2_1 ;
signal s_st_arr3 : st_arr3
:= c_st_arr3_1 ;
--
begin
CHG1 :
process
variable correct : boolean ;
begin
case s_boolean_cnt is
when 0
=> null ;
-- s_boolean <=
-- c_boolean_2 after 10 ns,
-- c_boolean_1 after 20 ns ;
--
when 1
=> correct :=
s_boolean =
c_boolean_2 and
(s_boolean_savt + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_boolean =
c_boolean_1 and
(s_boolean_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00381.P1" ,
"Multi inertial transactions occurred on " &
"concurrent signal asg",
correct ) ;
--
boolean_select <= transport 2 ;
-- s_boolean <=
-- c_boolean_2 after 10 ns ,
-- c_boolean_1 after 20 ns ,
-- c_boolean_2 after 30 ns ,
-- c_boolean_1 after 40 ns ;
--
when 3
=> correct :=
s_boolean =
c_boolean_2 and
(s_boolean_savt + 10 ns) = Std.Standard.Now ;
boolean_select <= transport 3 ;
-- s_boolean <=
-- c_boolean_1 after 5 ns ;
--
when 4
=> correct :=
correct and
s_boolean =
c_boolean_1 and
(s_boolean_savt + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00381" ,
"One inertial transaction occurred on a " &
"concurrent signal asg",
correct ) ;
boolean_select <= transport 4 ;
-- s_boolean <=
-- c_boolean_1 after 100 ns ;
--
when 5
=> correct :=
correct and
s_boolean =
c_boolean_1 and
(s_boolean_savt + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00381" ,
"Old transactions were removed on a " &
"concurrent signal asg",
correct ) ;
boolean_select <= transport 5 ;
-- s_boolean <=
-- c_boolean_2 after 10 ns ,
-- c_boolean_1 after 20 ns ,
-- c_boolean_2 after 30 ns ,
-- c_boolean_1 after 40 ns ;
--
when 6
=> correct :=
correct and
s_boolean =
c_boolean_2 and
(s_boolean_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00381" ,
"One inertial transaction occurred on a " &
"concurrent signal asg",
correct ) ;
boolean_select <= transport 6 ;
-- Last transaction above is marked
-- s_boolean <=
-- c_boolean_1 after 40 ns ;
--
when 7
=> correct :=
correct and
s_boolean =
c_boolean_1 and
(s_boolean_savt + 30 ns) = Std.Standard.Now ;
--
when 8
=> correct :=
correct and
s_boolean =
c_boolean_1 and
(s_boolean_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00381" ,
"Inertial semantics check on a concurrent " &
"signal asg",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00381" ,
"Inertial semantics check on a concurrent " &
"signal asg",
false ) ;
--
end case ;
--
s_boolean_savt <= transport Std.Standard.Now ;
chk_boolean <= transport s_boolean_cnt
after (1 us - Std.Standard.Now) ;
s_boolean_cnt <= transport s_boolean_cnt + 1 ;
wait until (not s_boolean'Quiet) and
(s_boolean_savt /= Std.Standard.Now) ;
--
end process CHG1 ;
--
PGEN_CHKP_1 :
process ( chk_boolean )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P1" ,
"Inertial transactions completed entirely",
chk_boolean = 8 ) ;
end if ;
end process PGEN_CHKP_1 ;
--
--
with boolean_select select
s_boolean <=
c_boolean_2 after 10 ns,
c_boolean_1 after 20 ns
when 1,
--
c_boolean_2 after 10 ns ,
c_boolean_1 after 20 ns ,
c_boolean_2 after 30 ns ,
c_boolean_1 after 40 ns
when 2,
--
c_boolean_1 after 5 ns
when 3,
--
c_boolean_1 after 100 ns
when 4,
--
c_boolean_2 after 10 ns ,
c_boolean_1 after 20 ns ,
c_boolean_2 after 30 ns ,
c_boolean_1 after 40 ns
when 5,
--
-- Last transaction above is marked
c_boolean_1 after 40 ns when 6 ;
--
CHG2 :
process
variable correct : boolean ;
begin
case s_bit_cnt is
when 0
=> null ;
-- s_bit <=
-- c_bit_2 after 10 ns,
-- c_bit_1 after 20 ns ;
--
when 1
=> correct :=
s_bit =
c_bit_2 and
(s_bit_savt + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_bit =
c_bit_1 and
(s_bit_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00381.P2" ,
"Multi inertial transactions occurred on " &
"concurrent signal asg",
correct ) ;
--
bit_select <= transport 2 ;
-- s_bit <=
-- c_bit_2 after 10 ns ,
-- c_bit_1 after 20 ns ,
-- c_bit_2 after 30 ns ,
-- c_bit_1 after 40 ns ;
--
when 3
=> correct :=
s_bit =
c_bit_2 and
(s_bit_savt + 10 ns) = Std.Standard.Now ;
bit_select <= transport 3 ;
-- s_bit <=
-- c_bit_1 after 5 ns ;
--
when 4
=> correct :=
correct and
s_bit =
c_bit_1 and
(s_bit_savt + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00381" ,
"One inertial transaction occurred on a " &
"concurrent signal asg",
correct ) ;
bit_select <= transport 4 ;
-- s_bit <=
-- c_bit_1 after 100 ns ;
--
when 5
=> correct :=
correct and
s_bit =
c_bit_1 and
(s_bit_savt + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00381" ,
"Old transactions were removed on a " &
"concurrent signal asg",
correct ) ;
bit_select <= transport 5 ;
-- s_bit <=
-- c_bit_2 after 10 ns ,
-- c_bit_1 after 20 ns ,
-- c_bit_2 after 30 ns ,
-- c_bit_1 after 40 ns ;
--
when 6
=> correct :=
correct and
s_bit =
c_bit_2 and
(s_bit_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00381" ,
"One inertial transaction occurred on a " &
"concurrent signal asg",
correct ) ;
bit_select <= transport 6 ;
-- Last transaction above is marked
-- s_bit <=
-- c_bit_1 after 40 ns ;
--
when 7
=> correct :=
correct and
s_bit =
c_bit_1 and
(s_bit_savt + 30 ns) = Std.Standard.Now ;
--
when 8
=> correct :=
correct and
s_bit =
c_bit_1 and
(s_bit_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00381" ,
"Inertial semantics check on a concurrent " &
"signal asg",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00381" ,
"Inertial semantics check on a concurrent " &
"signal asg",
false ) ;
--
end case ;
--
s_bit_savt <= transport Std.Standard.Now ;
chk_bit <= transport s_bit_cnt
after (1 us - Std.Standard.Now) ;
s_bit_cnt <= transport s_bit_cnt + 1 ;
wait until (not s_bit'Quiet) and
(s_bit_savt /= Std.Standard.Now) ;
--
end process CHG2 ;
--
PGEN_CHKP_2 :
process ( chk_bit )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P2" ,
"Inertial transactions completed entirely",
chk_bit = 8 ) ;
end if ;
end process PGEN_CHKP_2 ;
--
--
with bit_select select
s_bit <=
c_bit_2 after 10 ns,
c_bit_1 after 20 ns
when 1,
--
c_bit_2 after 10 ns ,
c_bit_1 after 20 ns ,
c_bit_2 after 30 ns ,
c_bit_1 after 40 ns
when 2,
--
c_bit_1 after 5 ns
when 3,
--
c_bit_1 after 100 ns
when 4,
--
c_bit_2 after 10 ns ,
c_bit_1 after 20 ns ,
c_bit_2 after 30 ns ,
c_bit_1 after 40 ns
when 5,
--
-- Last transaction above is marked
c_bit_1 after 40 ns when 6 ;
--
CHG3 :
process
variable correct : boolean ;
begin
case s_severity_level_cnt is
when 0
=> null ;
-- s_severity_level <=
-- c_severity_level_2 after 10 ns,
-- c_severity_level_1 after 20 ns ;
--
when 1
=> correct :=
s_severity_level =
c_severity_level_2 and
(s_severity_level_savt + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_severity_level =
c_severity_level_1 and
(s_severity_level_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00381.P3" ,
"Multi inertial transactions occurred on " &
"concurrent signal asg",
correct ) ;
--
severity_level_select <= transport 2 ;
-- s_severity_level <=
-- c_severity_level_2 after 10 ns ,
-- c_severity_level_1 after 20 ns ,
-- c_severity_level_2 after 30 ns ,
-- c_severity_level_1 after 40 ns ;
--
when 3
=> correct :=
s_severity_level =
c_severity_level_2 and
(s_severity_level_savt + 10 ns) = Std.Standard.Now ;
severity_level_select <= transport 3 ;
-- s_severity_level <=
-- c_severity_level_1 after 5 ns ;
--
when 4
=> correct :=
correct and
s_severity_level =
c_severity_level_1 and
(s_severity_level_savt + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00381" ,
"One inertial transaction occurred on a " &
"concurrent signal asg",
correct ) ;
severity_level_select <= transport 4 ;
-- s_severity_level <=
-- c_severity_level_1 after 100 ns ;
--
when 5
=> correct :=
correct and
s_severity_level =
c_severity_level_1 and
(s_severity_level_savt + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00381" ,
"Old transactions were removed on a " &
"concurrent signal asg",
correct ) ;
severity_level_select <= transport 5 ;
-- s_severity_level <=
-- c_severity_level_2 after 10 ns ,
-- c_severity_level_1 after 20 ns ,
-- c_severity_level_2 after 30 ns ,
-- c_severity_level_1 after 40 ns ;
--
when 6
=> correct :=
correct and
s_severity_level =
c_severity_level_2 and
(s_severity_level_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00381" ,
"One inertial transaction occurred on a " &
"concurrent signal asg",
correct ) ;
severity_level_select <= transport 6 ;
-- Last transaction above is marked
-- s_severity_level <=
-- c_severity_level_1 after 40 ns ;
--
when 7
=> correct :=
correct and
s_severity_level =
c_severity_level_1 and
(s_severity_level_savt + 30 ns) = Std.Standard.Now ;
--
when 8
=> correct :=
correct and
s_severity_level =
c_severity_level_1 and
(s_severity_level_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00381" ,
"Inertial semantics check on a concurrent " &
"signal asg",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00381" ,
"Inertial semantics check on a concurrent " &
"signal asg",
false ) ;
--
end case ;
--
s_severity_level_savt <= transport Std.Standard.Now ;
chk_severity_level <= transport s_severity_level_cnt
after (1 us - Std.Standard.Now) ;
s_severity_level_cnt <= transport s_severity_level_cnt + 1 ;
wait until (not s_severity_level'Quiet) and
(s_severity_level_savt /= Std.Standard.Now) ;
--
end process CHG3 ;
--
PGEN_CHKP_3 :
process ( chk_severity_level )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P3" ,
"Inertial transactions completed entirely",
chk_severity_level = 8 ) ;
end if ;
end process PGEN_CHKP_3 ;
--
--
with severity_level_select select
s_severity_level <=
c_severity_level_2 after 10 ns,
c_severity_level_1 after 20 ns
when 1,
--
c_severity_level_2 after 10 ns ,
c_severity_level_1 after 20 ns ,
c_severity_level_2 after 30 ns ,
c_severity_level_1 after 40 ns
when 2,
--
c_severity_level_1 after 5 ns
when 3,
--
c_severity_level_1 after 100 ns
when 4,
--
c_severity_level_2 after 10 ns ,
c_severity_level_1 after 20 ns ,
c_severity_level_2 after 30 ns ,
c_severity_level_1 after 40 ns
when 5,
--
-- Last transaction above is marked
c_severity_level_1 after 40 ns when 6 ;
--
CHG4 :
process
variable correct : boolean ;
begin
case s_character_cnt is
when 0
=> null ;
-- s_character <=
-- c_character_2 after 10 ns,
-- c_character_1 after 20 ns ;
--
when 1
=> correct :=
s_character =
c_character_2 and
(s_character_savt + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_character =
c_character_1 and
(s_character_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00381.P4" ,
"Multi inertial transactions occurred on " &
"concurrent signal asg",
correct ) ;
--
character_select <= transport 2 ;
-- s_character <=
-- c_character_2 after 10 ns ,
-- c_character_1 after 20 ns ,
-- c_character_2 after 30 ns ,
-- c_character_1 after 40 ns ;
--
when 3
=> correct :=
s_character =
c_character_2 and
(s_character_savt + 10 ns) = Std.Standard.Now ;
character_select <= transport 3 ;
-- s_character <=
-- c_character_1 after 5 ns ;
--
when 4
=> correct :=
correct and
s_character =
c_character_1 and
(s_character_savt + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00381" ,
"One inertial transaction occurred on a " &
"concurrent signal asg",
correct ) ;
character_select <= transport 4 ;
-- s_character <=
-- c_character_1 after 100 ns ;
--
when 5
=> correct :=
correct and
s_character =
c_character_1 and
(s_character_savt + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00381" ,
"Old transactions were removed on a " &
"concurrent signal asg",
correct ) ;
character_select <= transport 5 ;
-- s_character <=
-- c_character_2 after 10 ns ,
-- c_character_1 after 20 ns ,
-- c_character_2 after 30 ns ,
-- c_character_1 after 40 ns ;
--
when 6
=> correct :=
correct and
s_character =
c_character_2 and
(s_character_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00381" ,
"One inertial transaction occurred on a " &
"concurrent signal asg",
correct ) ;
character_select <= transport 6 ;
-- Last transaction above is marked
-- s_character <=
-- c_character_1 after 40 ns ;
--
when 7
=> correct :=
correct and
s_character =
c_character_1 and
(s_character_savt + 30 ns) = Std.Standard.Now ;
--
when 8
=> correct :=
correct and
s_character =
c_character_1 and
(s_character_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00381" ,
"Inertial semantics check on a concurrent " &
"signal asg",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00381" ,
"Inertial semantics check on a concurrent " &
"signal asg",
false ) ;
--
end case ;
--
s_character_savt <= transport Std.Standard.Now ;
chk_character <= transport s_character_cnt
after (1 us - Std.Standard.Now) ;
s_character_cnt <= transport s_character_cnt + 1 ;
wait until (not s_character'Quiet) and
(s_character_savt /= Std.Standard.Now) ;
--
end process CHG4 ;
--
PGEN_CHKP_4 :
process ( chk_character )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P4" ,
"Inertial transactions completed entirely",
chk_character = 8 ) ;
end if ;
end process PGEN_CHKP_4 ;
--
--
with character_select select
s_character <=
c_character_2 after 10 ns,
c_character_1 after 20 ns
when 1,
--
c_character_2 after 10 ns ,
c_character_1 after 20 ns ,
c_character_2 after 30 ns ,
c_character_1 after 40 ns
when 2,
--
c_character_1 after 5 ns
when 3,
--
c_character_1 after 100 ns
when 4,
--
c_character_2 after 10 ns ,
c_character_1 after 20 ns ,
c_character_2 after 30 ns ,
c_character_1 after 40 ns
when 5,
--
-- Last transaction above is marked
c_character_1 after 40 ns when 6 ;
--
CHG5 :
process
variable correct : boolean ;
begin
case s_st_enum1_cnt is
when 0
=> null ;
-- s_st_enum1 <=
-- c_st_enum1_2 after 10 ns,
-- c_st_enum1_1 after 20 ns ;
--
when 1
=> correct :=
s_st_enum1 =
c_st_enum1_2 and
(s_st_enum1_savt + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_enum1 =
c_st_enum1_1 and
(s_st_enum1_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00381.P5" ,
"Multi inertial transactions occurred on " &
"concurrent signal asg",
correct ) ;
--
st_enum1_select <= transport 2 ;
-- s_st_enum1 <=
-- c_st_enum1_2 after 10 ns ,
-- c_st_enum1_1 after 20 ns ,
-- c_st_enum1_2 after 30 ns ,
-- c_st_enum1_1 after 40 ns ;
--
when 3
=> correct :=
s_st_enum1 =
c_st_enum1_2 and
(s_st_enum1_savt + 10 ns) = Std.Standard.Now ;
st_enum1_select <= transport 3 ;
-- s_st_enum1 <=
-- c_st_enum1_1 after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_enum1 =
c_st_enum1_1 and
(s_st_enum1_savt + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00381" ,
"One inertial transaction occurred on a " &
"concurrent signal asg",
correct ) ;
st_enum1_select <= transport 4 ;
-- s_st_enum1 <=
-- c_st_enum1_1 after 100 ns ;
--
when 5
=> correct :=
correct and
s_st_enum1 =
c_st_enum1_1 and
(s_st_enum1_savt + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00381" ,
"Old transactions were removed on a " &
"concurrent signal asg",
correct ) ;
st_enum1_select <= transport 5 ;
-- s_st_enum1 <=
-- c_st_enum1_2 after 10 ns ,
-- c_st_enum1_1 after 20 ns ,
-- c_st_enum1_2 after 30 ns ,
-- c_st_enum1_1 after 40 ns ;
--
when 6
=> correct :=
correct and
s_st_enum1 =
c_st_enum1_2 and
(s_st_enum1_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00381" ,
"One inertial transaction occurred on a " &
"concurrent signal asg",
correct ) ;
st_enum1_select <= transport 6 ;
-- Last transaction above is marked
-- s_st_enum1 <=
-- c_st_enum1_1 after 40 ns ;
--
when 7
=> correct :=
correct and
s_st_enum1 =
c_st_enum1_1 and
(s_st_enum1_savt + 30 ns) = Std.Standard.Now ;
--
when 8
=> correct :=
correct and
s_st_enum1 =
c_st_enum1_1 and
(s_st_enum1_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00381" ,
"Inertial semantics check on a concurrent " &
"signal asg",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00381" ,
"Inertial semantics check on a concurrent " &
"signal asg",
false ) ;
--
end case ;
--
s_st_enum1_savt <= transport Std.Standard.Now ;
chk_st_enum1 <= transport s_st_enum1_cnt
after (1 us - Std.Standard.Now) ;
s_st_enum1_cnt <= transport s_st_enum1_cnt + 1 ;
wait until (not s_st_enum1'Quiet) and
(s_st_enum1_savt /= Std.Standard.Now) ;
--
end process CHG5 ;
--
PGEN_CHKP_5 :
process ( chk_st_enum1 )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P5" ,
"Inertial transactions completed entirely",
chk_st_enum1 = 8 ) ;
end if ;
end process PGEN_CHKP_5 ;
--
--
with st_enum1_select select
s_st_enum1 <=
c_st_enum1_2 after 10 ns,
c_st_enum1_1 after 20 ns
when 1,
--
c_st_enum1_2 after 10 ns ,
c_st_enum1_1 after 20 ns ,
c_st_enum1_2 after 30 ns ,
c_st_enum1_1 after 40 ns
when 2,
--
c_st_enum1_1 after 5 ns
when 3,
--
c_st_enum1_1 after 100 ns
when 4,
--
c_st_enum1_2 after 10 ns ,
c_st_enum1_1 after 20 ns ,
c_st_enum1_2 after 30 ns ,
c_st_enum1_1 after 40 ns
when 5,
--
-- Last transaction above is marked
c_st_enum1_1 after 40 ns when 6 ;
--
CHG6 :
process
variable correct : boolean ;
begin
case s_integer_cnt is
when 0
=> null ;
-- s_integer <=
-- c_integer_2 after 10 ns,
-- c_integer_1 after 20 ns ;
--
when 1
=> correct :=
s_integer =
c_integer_2 and
(s_integer_savt + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_integer =
c_integer_1 and
(s_integer_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00381.P6" ,
"Multi inertial transactions occurred on " &
"concurrent signal asg",
correct ) ;
--
integer_select <= transport 2 ;
-- s_integer <=
-- c_integer_2 after 10 ns ,
-- c_integer_1 after 20 ns ,
-- c_integer_2 after 30 ns ,
-- c_integer_1 after 40 ns ;
--
when 3
=> correct :=
s_integer =
c_integer_2 and
(s_integer_savt + 10 ns) = Std.Standard.Now ;
integer_select <= transport 3 ;
-- s_integer <=
-- c_integer_1 after 5 ns ;
--
when 4
=> correct :=
correct and
s_integer =
c_integer_1 and
(s_integer_savt + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00381" ,
"One inertial transaction occurred on a " &
"concurrent signal asg",
correct ) ;
integer_select <= transport 4 ;
-- s_integer <=
-- c_integer_1 after 100 ns ;
--
when 5
=> correct :=
correct and
s_integer =
c_integer_1 and
(s_integer_savt + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00381" ,
"Old transactions were removed on a " &
"concurrent signal asg",
correct ) ;
integer_select <= transport 5 ;
-- s_integer <=
-- c_integer_2 after 10 ns ,
-- c_integer_1 after 20 ns ,
-- c_integer_2 after 30 ns ,
-- c_integer_1 after 40 ns ;
--
when 6
=> correct :=
correct and
s_integer =
c_integer_2 and
(s_integer_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00381" ,
"One inertial transaction occurred on a " &
"concurrent signal asg",
correct ) ;
integer_select <= transport 6 ;
-- Last transaction above is marked
-- s_integer <=
-- c_integer_1 after 40 ns ;
--
when 7
=> correct :=
correct and
s_integer =
c_integer_1 and
(s_integer_savt + 30 ns) = Std.Standard.Now ;
--
when 8
=> correct :=
correct and
s_integer =
c_integer_1 and
(s_integer_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00381" ,
"Inertial semantics check on a concurrent " &
"signal asg",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00381" ,
"Inertial semantics check on a concurrent " &
"signal asg",
false ) ;
--
end case ;
--
s_integer_savt <= transport Std.Standard.Now ;
chk_integer <= transport s_integer_cnt
after (1 us - Std.Standard.Now) ;
s_integer_cnt <= transport s_integer_cnt + 1 ;
wait until (not s_integer'Quiet) and
(s_integer_savt /= Std.Standard.Now) ;
--
end process CHG6 ;
--
PGEN_CHKP_6 :
process ( chk_integer )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P6" ,
"Inertial transactions completed entirely",
chk_integer = 8 ) ;
end if ;
end process PGEN_CHKP_6 ;
--
--
with integer_select select
s_integer <=
c_integer_2 after 10 ns,
c_integer_1 after 20 ns
when 1,
--
c_integer_2 after 10 ns ,
c_integer_1 after 20 ns ,
c_integer_2 after 30 ns ,
c_integer_1 after 40 ns
when 2,
--
c_integer_1 after 5 ns
when 3,
--
c_integer_1 after 100 ns
when 4,
--
c_integer_2 after 10 ns ,
c_integer_1 after 20 ns ,
c_integer_2 after 30 ns ,
c_integer_1 after 40 ns
when 5,
--
-- Last transaction above is marked
c_integer_1 after 40 ns when 6 ;
--
CHG7 :
process
variable correct : boolean ;
begin
case s_st_int1_cnt is
when 0
=> null ;
-- s_st_int1 <=
-- c_st_int1_2 after 10 ns,
-- c_st_int1_1 after 20 ns ;
--
when 1
=> correct :=
s_st_int1 =
c_st_int1_2 and
(s_st_int1_savt + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_int1 =
c_st_int1_1 and
(s_st_int1_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00381.P7" ,
"Multi inertial transactions occurred on " &
"concurrent signal asg",
correct ) ;
--
st_int1_select <= transport 2 ;
-- s_st_int1 <=
-- c_st_int1_2 after 10 ns ,
-- c_st_int1_1 after 20 ns ,
-- c_st_int1_2 after 30 ns ,
-- c_st_int1_1 after 40 ns ;
--
when 3
=> correct :=
s_st_int1 =
c_st_int1_2 and
(s_st_int1_savt + 10 ns) = Std.Standard.Now ;
st_int1_select <= transport 3 ;
-- s_st_int1 <=
-- c_st_int1_1 after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_int1 =
c_st_int1_1 and
(s_st_int1_savt + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00381" ,
"One inertial transaction occurred on a " &
"concurrent signal asg",
correct ) ;
st_int1_select <= transport 4 ;
-- s_st_int1 <=
-- c_st_int1_1 after 100 ns ;
--
when 5
=> correct :=
correct and
s_st_int1 =
c_st_int1_1 and
(s_st_int1_savt + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00381" ,
"Old transactions were removed on a " &
"concurrent signal asg",
correct ) ;
st_int1_select <= transport 5 ;
-- s_st_int1 <=
-- c_st_int1_2 after 10 ns ,
-- c_st_int1_1 after 20 ns ,
-- c_st_int1_2 after 30 ns ,
-- c_st_int1_1 after 40 ns ;
--
when 6
=> correct :=
correct and
s_st_int1 =
c_st_int1_2 and
(s_st_int1_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00381" ,
"One inertial transaction occurred on a " &
"concurrent signal asg",
correct ) ;
st_int1_select <= transport 6 ;
-- Last transaction above is marked
-- s_st_int1 <=
-- c_st_int1_1 after 40 ns ;
--
when 7
=> correct :=
correct and
s_st_int1 =
c_st_int1_1 and
(s_st_int1_savt + 30 ns) = Std.Standard.Now ;
--
when 8
=> correct :=
correct and
s_st_int1 =
c_st_int1_1 and
(s_st_int1_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00381" ,
"Inertial semantics check on a concurrent " &
"signal asg",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00381" ,
"Inertial semantics check on a concurrent " &
"signal asg",
false ) ;
--
end case ;
--
s_st_int1_savt <= transport Std.Standard.Now ;
chk_st_int1 <= transport s_st_int1_cnt
after (1 us - Std.Standard.Now) ;
s_st_int1_cnt <= transport s_st_int1_cnt + 1 ;
wait until (not s_st_int1'Quiet) and
(s_st_int1_savt /= Std.Standard.Now) ;
--
end process CHG7 ;
--
PGEN_CHKP_7 :
process ( chk_st_int1 )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P7" ,
"Inertial transactions completed entirely",
chk_st_int1 = 8 ) ;
end if ;
end process PGEN_CHKP_7 ;
--
--
with st_int1_select select
s_st_int1 <=
c_st_int1_2 after 10 ns,
c_st_int1_1 after 20 ns
when 1,
--
c_st_int1_2 after 10 ns ,
c_st_int1_1 after 20 ns ,
c_st_int1_2 after 30 ns ,
c_st_int1_1 after 40 ns
when 2,
--
c_st_int1_1 after 5 ns
when 3,
--
c_st_int1_1 after 100 ns
when 4,
--
c_st_int1_2 after 10 ns ,
c_st_int1_1 after 20 ns ,
c_st_int1_2 after 30 ns ,
c_st_int1_1 after 40 ns
when 5,
--
-- Last transaction above is marked
c_st_int1_1 after 40 ns when 6 ;
--
CHG8 :
process
variable correct : boolean ;
begin
case s_time_cnt is
when 0
=> null ;
-- s_time <=
-- c_time_2 after 10 ns,
-- c_time_1 after 20 ns ;
--
when 1
=> correct :=
s_time =
c_time_2 and
(s_time_savt + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_time =
c_time_1 and
(s_time_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00381.P8" ,
"Multi inertial transactions occurred on " &
"concurrent signal asg",
correct ) ;
--
time_select <= transport 2 ;
-- s_time <=
-- c_time_2 after 10 ns ,
-- c_time_1 after 20 ns ,
-- c_time_2 after 30 ns ,
-- c_time_1 after 40 ns ;
--
when 3
=> correct :=
s_time =
c_time_2 and
(s_time_savt + 10 ns) = Std.Standard.Now ;
time_select <= transport 3 ;
-- s_time <=
-- c_time_1 after 5 ns ;
--
when 4
=> correct :=
correct and
s_time =
c_time_1 and
(s_time_savt + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00381" ,
"One inertial transaction occurred on a " &
"concurrent signal asg",
correct ) ;
time_select <= transport 4 ;
-- s_time <=
-- c_time_1 after 100 ns ;
--
when 5
=> correct :=
correct and
s_time =
c_time_1 and
(s_time_savt + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00381" ,
"Old transactions were removed on a " &
"concurrent signal asg",
correct ) ;
time_select <= transport 5 ;
-- s_time <=
-- c_time_2 after 10 ns ,
-- c_time_1 after 20 ns ,
-- c_time_2 after 30 ns ,
-- c_time_1 after 40 ns ;
--
when 6
=> correct :=
correct and
s_time =
c_time_2 and
(s_time_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00381" ,
"One inertial transaction occurred on a " &
"concurrent signal asg",
correct ) ;
time_select <= transport 6 ;
-- Last transaction above is marked
-- s_time <=
-- c_time_1 after 40 ns ;
--
when 7
=> correct :=
correct and
s_time =
c_time_1 and
(s_time_savt + 30 ns) = Std.Standard.Now ;
--
when 8
=> correct :=
correct and
s_time =
c_time_1 and
(s_time_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00381" ,
"Inertial semantics check on a concurrent " &
"signal asg",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00381" ,
"Inertial semantics check on a concurrent " &
"signal asg",
false ) ;
--
end case ;
--
s_time_savt <= transport Std.Standard.Now ;
chk_time <= transport s_time_cnt
after (1 us - Std.Standard.Now) ;
s_time_cnt <= transport s_time_cnt + 1 ;
wait until (not s_time'Quiet) and
(s_time_savt /= Std.Standard.Now) ;
--
end process CHG8 ;
--
PGEN_CHKP_8 :
process ( chk_time )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P8" ,
"Inertial transactions completed entirely",
chk_time = 8 ) ;
end if ;
end process PGEN_CHKP_8 ;
--
--
with time_select select
s_time <=
c_time_2 after 10 ns,
c_time_1 after 20 ns
when 1,
--
c_time_2 after 10 ns ,
c_time_1 after 20 ns ,
c_time_2 after 30 ns ,
c_time_1 after 40 ns
when 2,
--
c_time_1 after 5 ns
when 3,
--
c_time_1 after 100 ns
when 4,
--
c_time_2 after 10 ns ,
c_time_1 after 20 ns ,
c_time_2 after 30 ns ,
c_time_1 after 40 ns
when 5,
--
-- Last transaction above is marked
c_time_1 after 40 ns when 6 ;
--
CHG9 :
process
variable correct : boolean ;
begin
case s_st_phys1_cnt is
when 0
=> null ;
-- s_st_phys1 <=
-- c_st_phys1_2 after 10 ns,
-- c_st_phys1_1 after 20 ns ;
--
when 1
=> correct :=
s_st_phys1 =
c_st_phys1_2 and
(s_st_phys1_savt + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_phys1 =
c_st_phys1_1 and
(s_st_phys1_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00381.P9" ,
"Multi inertial transactions occurred on " &
"concurrent signal asg",
correct ) ;
--
st_phys1_select <= transport 2 ;
-- s_st_phys1 <=
-- c_st_phys1_2 after 10 ns ,
-- c_st_phys1_1 after 20 ns ,
-- c_st_phys1_2 after 30 ns ,
-- c_st_phys1_1 after 40 ns ;
--
when 3
=> correct :=
s_st_phys1 =
c_st_phys1_2 and
(s_st_phys1_savt + 10 ns) = Std.Standard.Now ;
st_phys1_select <= transport 3 ;
-- s_st_phys1 <=
-- c_st_phys1_1 after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_phys1 =
c_st_phys1_1 and
(s_st_phys1_savt + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00381" ,
"One inertial transaction occurred on a " &
"concurrent signal asg",
correct ) ;
st_phys1_select <= transport 4 ;
-- s_st_phys1 <=
-- c_st_phys1_1 after 100 ns ;
--
when 5
=> correct :=
correct and
s_st_phys1 =
c_st_phys1_1 and
(s_st_phys1_savt + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00381" ,
"Old transactions were removed on a " &
"concurrent signal asg",
correct ) ;
st_phys1_select <= transport 5 ;
-- s_st_phys1 <=
-- c_st_phys1_2 after 10 ns ,
-- c_st_phys1_1 after 20 ns ,
-- c_st_phys1_2 after 30 ns ,
-- c_st_phys1_1 after 40 ns ;
--
when 6
=> correct :=
correct and
s_st_phys1 =
c_st_phys1_2 and
(s_st_phys1_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00381" ,
"One inertial transaction occurred on a " &
"concurrent signal asg",
correct ) ;
st_phys1_select <= transport 6 ;
-- Last transaction above is marked
-- s_st_phys1 <=
-- c_st_phys1_1 after 40 ns ;
--
when 7
=> correct :=
correct and
s_st_phys1 =
c_st_phys1_1 and
(s_st_phys1_savt + 30 ns) = Std.Standard.Now ;
--
when 8
=> correct :=
correct and
s_st_phys1 =
c_st_phys1_1 and
(s_st_phys1_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00381" ,
"Inertial semantics check on a concurrent " &
"signal asg",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00381" ,
"Inertial semantics check on a concurrent " &
"signal asg",
false ) ;
--
end case ;
--
s_st_phys1_savt <= transport Std.Standard.Now ;
chk_st_phys1 <= transport s_st_phys1_cnt
after (1 us - Std.Standard.Now) ;
s_st_phys1_cnt <= transport s_st_phys1_cnt + 1 ;
wait until (not s_st_phys1'Quiet) and
(s_st_phys1_savt /= Std.Standard.Now) ;
--
end process CHG9 ;
--
PGEN_CHKP_9 :
process ( chk_st_phys1 )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P9" ,
"Inertial transactions completed entirely",
chk_st_phys1 = 8 ) ;
end if ;
end process PGEN_CHKP_9 ;
--
--
with st_phys1_select select
s_st_phys1 <=
c_st_phys1_2 after 10 ns,
c_st_phys1_1 after 20 ns
when 1,
--
c_st_phys1_2 after 10 ns ,
c_st_phys1_1 after 20 ns ,
c_st_phys1_2 after 30 ns ,
c_st_phys1_1 after 40 ns
when 2,
--
c_st_phys1_1 after 5 ns
when 3,
--
c_st_phys1_1 after 100 ns
when 4,
--
c_st_phys1_2 after 10 ns ,
c_st_phys1_1 after 20 ns ,
c_st_phys1_2 after 30 ns ,
c_st_phys1_1 after 40 ns
when 5,
--
-- Last transaction above is marked
c_st_phys1_1 after 40 ns when 6 ;
--
CHG10 :
process
variable correct : boolean ;
begin
case s_real_cnt is
when 0
=> null ;
-- s_real <=
-- c_real_2 after 10 ns,
-- c_real_1 after 20 ns ;
--
when 1
=> correct :=
s_real =
c_real_2 and
(s_real_savt + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_real =
c_real_1 and
(s_real_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00381.P10" ,
"Multi inertial transactions occurred on " &
"concurrent signal asg",
correct ) ;
--
real_select <= transport 2 ;
-- s_real <=
-- c_real_2 after 10 ns ,
-- c_real_1 after 20 ns ,
-- c_real_2 after 30 ns ,
-- c_real_1 after 40 ns ;
--
when 3
=> correct :=
s_real =
c_real_2 and
(s_real_savt + 10 ns) = Std.Standard.Now ;
real_select <= transport 3 ;
-- s_real <=
-- c_real_1 after 5 ns ;
--
when 4
=> correct :=
correct and
s_real =
c_real_1 and
(s_real_savt + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00381" ,
"One inertial transaction occurred on a " &
"concurrent signal asg",
correct ) ;
real_select <= transport 4 ;
-- s_real <=
-- c_real_1 after 100 ns ;
--
when 5
=> correct :=
correct and
s_real =
c_real_1 and
(s_real_savt + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00381" ,
"Old transactions were removed on a " &
"concurrent signal asg",
correct ) ;
real_select <= transport 5 ;
-- s_real <=
-- c_real_2 after 10 ns ,
-- c_real_1 after 20 ns ,
-- c_real_2 after 30 ns ,
-- c_real_1 after 40 ns ;
--
when 6
=> correct :=
correct and
s_real =
c_real_2 and
(s_real_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00381" ,
"One inertial transaction occurred on a " &
"concurrent signal asg",
correct ) ;
real_select <= transport 6 ;
-- Last transaction above is marked
-- s_real <=
-- c_real_1 after 40 ns ;
--
when 7
=> correct :=
correct and
s_real =
c_real_1 and
(s_real_savt + 30 ns) = Std.Standard.Now ;
--
when 8
=> correct :=
correct and
s_real =
c_real_1 and
(s_real_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00381" ,
"Inertial semantics check on a concurrent " &
"signal asg",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00381" ,
"Inertial semantics check on a concurrent " &
"signal asg",
false ) ;
--
end case ;
--
s_real_savt <= transport Std.Standard.Now ;
chk_real <= transport s_real_cnt
after (1 us - Std.Standard.Now) ;
s_real_cnt <= transport s_real_cnt + 1 ;
wait until (not s_real'Quiet) and
(s_real_savt /= Std.Standard.Now) ;
--
end process CHG10 ;
--
PGEN_CHKP_10 :
process ( chk_real )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P10" ,
"Inertial transactions completed entirely",
chk_real = 8 ) ;
end if ;
end process PGEN_CHKP_10 ;
--
--
with real_select select
s_real <=
c_real_2 after 10 ns,
c_real_1 after 20 ns
when 1,
--
c_real_2 after 10 ns ,
c_real_1 after 20 ns ,
c_real_2 after 30 ns ,
c_real_1 after 40 ns
when 2,
--
c_real_1 after 5 ns
when 3,
--
c_real_1 after 100 ns
when 4,
--
c_real_2 after 10 ns ,
c_real_1 after 20 ns ,
c_real_2 after 30 ns ,
c_real_1 after 40 ns
when 5,
--
-- Last transaction above is marked
c_real_1 after 40 ns when 6 ;
--
CHG11 :
process
variable correct : boolean ;
begin
case s_st_real1_cnt is
when 0
=> null ;
-- s_st_real1 <=
-- c_st_real1_2 after 10 ns,
-- c_st_real1_1 after 20 ns ;
--
when 1
=> correct :=
s_st_real1 =
c_st_real1_2 and
(s_st_real1_savt + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_real1 =
c_st_real1_1 and
(s_st_real1_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00381.P11" ,
"Multi inertial transactions occurred on " &
"concurrent signal asg",
correct ) ;
--
st_real1_select <= transport 2 ;
-- s_st_real1 <=
-- c_st_real1_2 after 10 ns ,
-- c_st_real1_1 after 20 ns ,
-- c_st_real1_2 after 30 ns ,
-- c_st_real1_1 after 40 ns ;
--
when 3
=> correct :=
s_st_real1 =
c_st_real1_2 and
(s_st_real1_savt + 10 ns) = Std.Standard.Now ;
st_real1_select <= transport 3 ;
-- s_st_real1 <=
-- c_st_real1_1 after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_real1 =
c_st_real1_1 and
(s_st_real1_savt + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00381" ,
"One inertial transaction occurred on a " &
"concurrent signal asg",
correct ) ;
st_real1_select <= transport 4 ;
-- s_st_real1 <=
-- c_st_real1_1 after 100 ns ;
--
when 5
=> correct :=
correct and
s_st_real1 =
c_st_real1_1 and
(s_st_real1_savt + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00381" ,
"Old transactions were removed on a " &
"concurrent signal asg",
correct ) ;
st_real1_select <= transport 5 ;
-- s_st_real1 <=
-- c_st_real1_2 after 10 ns ,
-- c_st_real1_1 after 20 ns ,
-- c_st_real1_2 after 30 ns ,
-- c_st_real1_1 after 40 ns ;
--
when 6
=> correct :=
correct and
s_st_real1 =
c_st_real1_2 and
(s_st_real1_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00381" ,
"One inertial transaction occurred on a " &
"concurrent signal asg",
correct ) ;
st_real1_select <= transport 6 ;
-- Last transaction above is marked
-- s_st_real1 <=
-- c_st_real1_1 after 40 ns ;
--
when 7
=> correct :=
correct and
s_st_real1 =
c_st_real1_1 and
(s_st_real1_savt + 30 ns) = Std.Standard.Now ;
--
when 8
=> correct :=
correct and
s_st_real1 =
c_st_real1_1 and
(s_st_real1_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00381" ,
"Inertial semantics check on a concurrent " &
"signal asg",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00381" ,
"Inertial semantics check on a concurrent " &
"signal asg",
false ) ;
--
end case ;
--
s_st_real1_savt <= transport Std.Standard.Now ;
chk_st_real1 <= transport s_st_real1_cnt
after (1 us - Std.Standard.Now) ;
s_st_real1_cnt <= transport s_st_real1_cnt + 1 ;
wait until (not s_st_real1'Quiet) and
(s_st_real1_savt /= Std.Standard.Now) ;
--
end process CHG11 ;
--
PGEN_CHKP_11 :
process ( chk_st_real1 )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P11" ,
"Inertial transactions completed entirely",
chk_st_real1 = 8 ) ;
end if ;
end process PGEN_CHKP_11 ;
--
--
with st_real1_select select
s_st_real1 <=
c_st_real1_2 after 10 ns,
c_st_real1_1 after 20 ns
when 1,
--
c_st_real1_2 after 10 ns ,
c_st_real1_1 after 20 ns ,
c_st_real1_2 after 30 ns ,
c_st_real1_1 after 40 ns
when 2,
--
c_st_real1_1 after 5 ns
when 3,
--
c_st_real1_1 after 100 ns
when 4,
--
c_st_real1_2 after 10 ns ,
c_st_real1_1 after 20 ns ,
c_st_real1_2 after 30 ns ,
c_st_real1_1 after 40 ns
when 5,
--
-- Last transaction above is marked
c_st_real1_1 after 40 ns when 6 ;
--
CHG12 :
process
variable correct : boolean ;
begin
case s_st_rec1_cnt is
when 0
=> null ;
-- s_st_rec1 <=
-- c_st_rec1_2 after 10 ns,
-- c_st_rec1_1 after 20 ns ;
--
when 1
=> correct :=
s_st_rec1 =
c_st_rec1_2 and
(s_st_rec1_savt + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_rec1 =
c_st_rec1_1 and
(s_st_rec1_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00381.P12" ,
"Multi inertial transactions occurred on " &
"concurrent signal asg",
correct ) ;
--
st_rec1_select <= transport 2 ;
-- s_st_rec1 <=
-- c_st_rec1_2 after 10 ns ,
-- c_st_rec1_1 after 20 ns ,
-- c_st_rec1_2 after 30 ns ,
-- c_st_rec1_1 after 40 ns ;
--
when 3
=> correct :=
s_st_rec1 =
c_st_rec1_2 and
(s_st_rec1_savt + 10 ns) = Std.Standard.Now ;
st_rec1_select <= transport 3 ;
-- s_st_rec1 <=
-- c_st_rec1_1 after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_rec1 =
c_st_rec1_1 and
(s_st_rec1_savt + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00381" ,
"One inertial transaction occurred on a " &
"concurrent signal asg",
correct ) ;
st_rec1_select <= transport 4 ;
-- s_st_rec1 <=
-- c_st_rec1_1 after 100 ns ;
--
when 5
=> correct :=
correct and
s_st_rec1 =
c_st_rec1_1 and
(s_st_rec1_savt + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00381" ,
"Old transactions were removed on a " &
"concurrent signal asg",
correct ) ;
st_rec1_select <= transport 5 ;
-- s_st_rec1 <=
-- c_st_rec1_2 after 10 ns ,
-- c_st_rec1_1 after 20 ns ,
-- c_st_rec1_2 after 30 ns ,
-- c_st_rec1_1 after 40 ns ;
--
when 6
=> correct :=
correct and
s_st_rec1 =
c_st_rec1_2 and
(s_st_rec1_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00381" ,
"One inertial transaction occurred on a " &
"concurrent signal asg",
correct ) ;
st_rec1_select <= transport 6 ;
-- Last transaction above is marked
-- s_st_rec1 <=
-- c_st_rec1_1 after 40 ns ;
--
when 7
=> correct :=
correct and
s_st_rec1 =
c_st_rec1_1 and
(s_st_rec1_savt + 30 ns) = Std.Standard.Now ;
--
when 8
=> correct :=
correct and
s_st_rec1 =
c_st_rec1_1 and
(s_st_rec1_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00381" ,
"Inertial semantics check on a concurrent " &
"signal asg",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00381" ,
"Inertial semantics check on a concurrent " &
"signal asg",
false ) ;
--
end case ;
--
s_st_rec1_savt <= transport Std.Standard.Now ;
chk_st_rec1 <= transport s_st_rec1_cnt
after (1 us - Std.Standard.Now) ;
s_st_rec1_cnt <= transport s_st_rec1_cnt + 1 ;
wait until (not s_st_rec1'Quiet) and
(s_st_rec1_savt /= Std.Standard.Now) ;
--
end process CHG12 ;
--
PGEN_CHKP_12 :
process ( chk_st_rec1 )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P12" ,
"Inertial transactions completed entirely",
chk_st_rec1 = 8 ) ;
end if ;
end process PGEN_CHKP_12 ;
--
--
with st_rec1_select select
s_st_rec1 <=
c_st_rec1_2 after 10 ns,
c_st_rec1_1 after 20 ns
when 1,
--
c_st_rec1_2 after 10 ns ,
c_st_rec1_1 after 20 ns ,
c_st_rec1_2 after 30 ns ,
c_st_rec1_1 after 40 ns
when 2,
--
c_st_rec1_1 after 5 ns
when 3,
--
c_st_rec1_1 after 100 ns
when 4,
--
c_st_rec1_2 after 10 ns ,
c_st_rec1_1 after 20 ns ,
c_st_rec1_2 after 30 ns ,
c_st_rec1_1 after 40 ns
when 5,
--
-- Last transaction above is marked
c_st_rec1_1 after 40 ns when 6 ;
--
CHG13 :
process
variable correct : boolean ;
begin
case s_st_rec2_cnt is
when 0
=> null ;
-- s_st_rec2 <=
-- c_st_rec2_2 after 10 ns,
-- c_st_rec2_1 after 20 ns ;
--
when 1
=> correct :=
s_st_rec2 =
c_st_rec2_2 and
(s_st_rec2_savt + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_rec2 =
c_st_rec2_1 and
(s_st_rec2_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00381.P13" ,
"Multi inertial transactions occurred on " &
"concurrent signal asg",
correct ) ;
--
st_rec2_select <= transport 2 ;
-- s_st_rec2 <=
-- c_st_rec2_2 after 10 ns ,
-- c_st_rec2_1 after 20 ns ,
-- c_st_rec2_2 after 30 ns ,
-- c_st_rec2_1 after 40 ns ;
--
when 3
=> correct :=
s_st_rec2 =
c_st_rec2_2 and
(s_st_rec2_savt + 10 ns) = Std.Standard.Now ;
st_rec2_select <= transport 3 ;
-- s_st_rec2 <=
-- c_st_rec2_1 after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_rec2 =
c_st_rec2_1 and
(s_st_rec2_savt + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00381" ,
"One inertial transaction occurred on a " &
"concurrent signal asg",
correct ) ;
st_rec2_select <= transport 4 ;
-- s_st_rec2 <=
-- c_st_rec2_1 after 100 ns ;
--
when 5
=> correct :=
correct and
s_st_rec2 =
c_st_rec2_1 and
(s_st_rec2_savt + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00381" ,
"Old transactions were removed on a " &
"concurrent signal asg",
correct ) ;
st_rec2_select <= transport 5 ;
-- s_st_rec2 <=
-- c_st_rec2_2 after 10 ns ,
-- c_st_rec2_1 after 20 ns ,
-- c_st_rec2_2 after 30 ns ,
-- c_st_rec2_1 after 40 ns ;
--
when 6
=> correct :=
correct and
s_st_rec2 =
c_st_rec2_2 and
(s_st_rec2_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00381" ,
"One inertial transaction occurred on a " &
"concurrent signal asg",
correct ) ;
st_rec2_select <= transport 6 ;
-- Last transaction above is marked
-- s_st_rec2 <=
-- c_st_rec2_1 after 40 ns ;
--
when 7
=> correct :=
correct and
s_st_rec2 =
c_st_rec2_1 and
(s_st_rec2_savt + 30 ns) = Std.Standard.Now ;
--
when 8
=> correct :=
correct and
s_st_rec2 =
c_st_rec2_1 and
(s_st_rec2_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00381" ,
"Inertial semantics check on a concurrent " &
"signal asg",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00381" ,
"Inertial semantics check on a concurrent " &
"signal asg",
false ) ;
--
end case ;
--
s_st_rec2_savt <= transport Std.Standard.Now ;
chk_st_rec2 <= transport s_st_rec2_cnt
after (1 us - Std.Standard.Now) ;
s_st_rec2_cnt <= transport s_st_rec2_cnt + 1 ;
wait until (not s_st_rec2'Quiet) and
(s_st_rec2_savt /= Std.Standard.Now) ;
--
end process CHG13 ;
--
PGEN_CHKP_13 :
process ( chk_st_rec2 )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P13" ,
"Inertial transactions completed entirely",
chk_st_rec2 = 8 ) ;
end if ;
end process PGEN_CHKP_13 ;
--
--
with st_rec2_select select
s_st_rec2 <=
c_st_rec2_2 after 10 ns,
c_st_rec2_1 after 20 ns
when 1,
--
c_st_rec2_2 after 10 ns ,
c_st_rec2_1 after 20 ns ,
c_st_rec2_2 after 30 ns ,
c_st_rec2_1 after 40 ns
when 2,
--
c_st_rec2_1 after 5 ns
when 3,
--
c_st_rec2_1 after 100 ns
when 4,
--
c_st_rec2_2 after 10 ns ,
c_st_rec2_1 after 20 ns ,
c_st_rec2_2 after 30 ns ,
c_st_rec2_1 after 40 ns
when 5,
--
-- Last transaction above is marked
c_st_rec2_1 after 40 ns when 6 ;
--
CHG14 :
process
variable correct : boolean ;
begin
case s_st_rec3_cnt is
when 0
=> null ;
-- s_st_rec3 <=
-- c_st_rec3_2 after 10 ns,
-- c_st_rec3_1 after 20 ns ;
--
when 1
=> correct :=
s_st_rec3 =
c_st_rec3_2 and
(s_st_rec3_savt + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_rec3 =
c_st_rec3_1 and
(s_st_rec3_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00381.P14" ,
"Multi inertial transactions occurred on " &
"concurrent signal asg",
correct ) ;
--
st_rec3_select <= transport 2 ;
-- s_st_rec3 <=
-- c_st_rec3_2 after 10 ns ,
-- c_st_rec3_1 after 20 ns ,
-- c_st_rec3_2 after 30 ns ,
-- c_st_rec3_1 after 40 ns ;
--
when 3
=> correct :=
s_st_rec3 =
c_st_rec3_2 and
(s_st_rec3_savt + 10 ns) = Std.Standard.Now ;
st_rec3_select <= transport 3 ;
-- s_st_rec3 <=
-- c_st_rec3_1 after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_rec3 =
c_st_rec3_1 and
(s_st_rec3_savt + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00381" ,
"One inertial transaction occurred on a " &
"concurrent signal asg",
correct ) ;
st_rec3_select <= transport 4 ;
-- s_st_rec3 <=
-- c_st_rec3_1 after 100 ns ;
--
when 5
=> correct :=
correct and
s_st_rec3 =
c_st_rec3_1 and
(s_st_rec3_savt + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00381" ,
"Old transactions were removed on a " &
"concurrent signal asg",
correct ) ;
st_rec3_select <= transport 5 ;
-- s_st_rec3 <=
-- c_st_rec3_2 after 10 ns ,
-- c_st_rec3_1 after 20 ns ,
-- c_st_rec3_2 after 30 ns ,
-- c_st_rec3_1 after 40 ns ;
--
when 6
=> correct :=
correct and
s_st_rec3 =
c_st_rec3_2 and
(s_st_rec3_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00381" ,
"One inertial transaction occurred on a " &
"concurrent signal asg",
correct ) ;
st_rec3_select <= transport 6 ;
-- Last transaction above is marked
-- s_st_rec3 <=
-- c_st_rec3_1 after 40 ns ;
--
when 7
=> correct :=
correct and
s_st_rec3 =
c_st_rec3_1 and
(s_st_rec3_savt + 30 ns) = Std.Standard.Now ;
--
when 8
=> correct :=
correct and
s_st_rec3 =
c_st_rec3_1 and
(s_st_rec3_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00381" ,
"Inertial semantics check on a concurrent " &
"signal asg",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00381" ,
"Inertial semantics check on a concurrent " &
"signal asg",
false ) ;
--
end case ;
--
s_st_rec3_savt <= transport Std.Standard.Now ;
chk_st_rec3 <= transport s_st_rec3_cnt
after (1 us - Std.Standard.Now) ;
s_st_rec3_cnt <= transport s_st_rec3_cnt + 1 ;
wait until (not s_st_rec3'Quiet) and
(s_st_rec3_savt /= Std.Standard.Now) ;
--
end process CHG14 ;
--
PGEN_CHKP_14 :
process ( chk_st_rec3 )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P14" ,
"Inertial transactions completed entirely",
chk_st_rec3 = 8 ) ;
end if ;
end process PGEN_CHKP_14 ;
--
--
with st_rec3_select select
s_st_rec3 <=
c_st_rec3_2 after 10 ns,
c_st_rec3_1 after 20 ns
when 1,
--
c_st_rec3_2 after 10 ns ,
c_st_rec3_1 after 20 ns ,
c_st_rec3_2 after 30 ns ,
c_st_rec3_1 after 40 ns
when 2,
--
c_st_rec3_1 after 5 ns
when 3,
--
c_st_rec3_1 after 100 ns
when 4,
--
c_st_rec3_2 after 10 ns ,
c_st_rec3_1 after 20 ns ,
c_st_rec3_2 after 30 ns ,
c_st_rec3_1 after 40 ns
when 5,
--
-- Last transaction above is marked
c_st_rec3_1 after 40 ns when 6 ;
--
CHG15 :
process
variable correct : boolean ;
begin
case s_st_arr1_cnt is
when 0
=> null ;
-- s_st_arr1 <=
-- c_st_arr1_2 after 10 ns,
-- c_st_arr1_1 after 20 ns ;
--
when 1
=> correct :=
s_st_arr1 =
c_st_arr1_2 and
(s_st_arr1_savt + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_arr1 =
c_st_arr1_1 and
(s_st_arr1_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00381.P15" ,
"Multi inertial transactions occurred on " &
"concurrent signal asg",
correct ) ;
--
st_arr1_select <= transport 2 ;
-- s_st_arr1 <=
-- c_st_arr1_2 after 10 ns ,
-- c_st_arr1_1 after 20 ns ,
-- c_st_arr1_2 after 30 ns ,
-- c_st_arr1_1 after 40 ns ;
--
when 3
=> correct :=
s_st_arr1 =
c_st_arr1_2 and
(s_st_arr1_savt + 10 ns) = Std.Standard.Now ;
st_arr1_select <= transport 3 ;
-- s_st_arr1 <=
-- c_st_arr1_1 after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_arr1 =
c_st_arr1_1 and
(s_st_arr1_savt + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00381" ,
"One inertial transaction occurred on a " &
"concurrent signal asg",
correct ) ;
st_arr1_select <= transport 4 ;
-- s_st_arr1 <=
-- c_st_arr1_1 after 100 ns ;
--
when 5
=> correct :=
correct and
s_st_arr1 =
c_st_arr1_1 and
(s_st_arr1_savt + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00381" ,
"Old transactions were removed on a " &
"concurrent signal asg",
correct ) ;
st_arr1_select <= transport 5 ;
-- s_st_arr1 <=
-- c_st_arr1_2 after 10 ns ,
-- c_st_arr1_1 after 20 ns ,
-- c_st_arr1_2 after 30 ns ,
-- c_st_arr1_1 after 40 ns ;
--
when 6
=> correct :=
correct and
s_st_arr1 =
c_st_arr1_2 and
(s_st_arr1_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00381" ,
"One inertial transaction occurred on a " &
"concurrent signal asg",
correct ) ;
st_arr1_select <= transport 6 ;
-- Last transaction above is marked
-- s_st_arr1 <=
-- c_st_arr1_1 after 40 ns ;
--
when 7
=> correct :=
correct and
s_st_arr1 =
c_st_arr1_1 and
(s_st_arr1_savt + 30 ns) = Std.Standard.Now ;
--
when 8
=> correct :=
correct and
s_st_arr1 =
c_st_arr1_1 and
(s_st_arr1_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00381" ,
"Inertial semantics check on a concurrent " &
"signal asg",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00381" ,
"Inertial semantics check on a concurrent " &
"signal asg",
false ) ;
--
end case ;
--
s_st_arr1_savt <= transport Std.Standard.Now ;
chk_st_arr1 <= transport s_st_arr1_cnt
after (1 us - Std.Standard.Now) ;
s_st_arr1_cnt <= transport s_st_arr1_cnt + 1 ;
wait until (not s_st_arr1'Quiet) and
(s_st_arr1_savt /= Std.Standard.Now) ;
--
end process CHG15 ;
--
PGEN_CHKP_15 :
process ( chk_st_arr1 )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P15" ,
"Inertial transactions completed entirely",
chk_st_arr1 = 8 ) ;
end if ;
end process PGEN_CHKP_15 ;
--
--
with st_arr1_select select
s_st_arr1 <=
c_st_arr1_2 after 10 ns,
c_st_arr1_1 after 20 ns
when 1,
--
c_st_arr1_2 after 10 ns ,
c_st_arr1_1 after 20 ns ,
c_st_arr1_2 after 30 ns ,
c_st_arr1_1 after 40 ns
when 2,
--
c_st_arr1_1 after 5 ns
when 3,
--
c_st_arr1_1 after 100 ns
when 4,
--
c_st_arr1_2 after 10 ns ,
c_st_arr1_1 after 20 ns ,
c_st_arr1_2 after 30 ns ,
c_st_arr1_1 after 40 ns
when 5,
--
-- Last transaction above is marked
c_st_arr1_1 after 40 ns when 6 ;
--
CHG16 :
process
variable correct : boolean ;
begin
case s_st_arr2_cnt is
when 0
=> null ;
-- s_st_arr2 <=
-- c_st_arr2_2 after 10 ns,
-- c_st_arr2_1 after 20 ns ;
--
when 1
=> correct :=
s_st_arr2 =
c_st_arr2_2 and
(s_st_arr2_savt + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_arr2 =
c_st_arr2_1 and
(s_st_arr2_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00381.P16" ,
"Multi inertial transactions occurred on " &
"concurrent signal asg",
correct ) ;
--
st_arr2_select <= transport 2 ;
-- s_st_arr2 <=
-- c_st_arr2_2 after 10 ns ,
-- c_st_arr2_1 after 20 ns ,
-- c_st_arr2_2 after 30 ns ,
-- c_st_arr2_1 after 40 ns ;
--
when 3
=> correct :=
s_st_arr2 =
c_st_arr2_2 and
(s_st_arr2_savt + 10 ns) = Std.Standard.Now ;
st_arr2_select <= transport 3 ;
-- s_st_arr2 <=
-- c_st_arr2_1 after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_arr2 =
c_st_arr2_1 and
(s_st_arr2_savt + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00381" ,
"One inertial transaction occurred on a " &
"concurrent signal asg",
correct ) ;
st_arr2_select <= transport 4 ;
-- s_st_arr2 <=
-- c_st_arr2_1 after 100 ns ;
--
when 5
=> correct :=
correct and
s_st_arr2 =
c_st_arr2_1 and
(s_st_arr2_savt + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00381" ,
"Old transactions were removed on a " &
"concurrent signal asg",
correct ) ;
st_arr2_select <= transport 5 ;
-- s_st_arr2 <=
-- c_st_arr2_2 after 10 ns ,
-- c_st_arr2_1 after 20 ns ,
-- c_st_arr2_2 after 30 ns ,
-- c_st_arr2_1 after 40 ns ;
--
when 6
=> correct :=
correct and
s_st_arr2 =
c_st_arr2_2 and
(s_st_arr2_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00381" ,
"One inertial transaction occurred on a " &
"concurrent signal asg",
correct ) ;
st_arr2_select <= transport 6 ;
-- Last transaction above is marked
-- s_st_arr2 <=
-- c_st_arr2_1 after 40 ns ;
--
when 7
=> correct :=
correct and
s_st_arr2 =
c_st_arr2_1 and
(s_st_arr2_savt + 30 ns) = Std.Standard.Now ;
--
when 8
=> correct :=
correct and
s_st_arr2 =
c_st_arr2_1 and
(s_st_arr2_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00381" ,
"Inertial semantics check on a concurrent " &
"signal asg",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00381" ,
"Inertial semantics check on a concurrent " &
"signal asg",
false ) ;
--
end case ;
--
s_st_arr2_savt <= transport Std.Standard.Now ;
chk_st_arr2 <= transport s_st_arr2_cnt
after (1 us - Std.Standard.Now) ;
s_st_arr2_cnt <= transport s_st_arr2_cnt + 1 ;
wait until (not s_st_arr2'Quiet) and
(s_st_arr2_savt /= Std.Standard.Now) ;
--
end process CHG16 ;
--
PGEN_CHKP_16 :
process ( chk_st_arr2 )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P16" ,
"Inertial transactions completed entirely",
chk_st_arr2 = 8 ) ;
end if ;
end process PGEN_CHKP_16 ;
--
--
with st_arr2_select select
s_st_arr2 <=
c_st_arr2_2 after 10 ns,
c_st_arr2_1 after 20 ns
when 1,
--
c_st_arr2_2 after 10 ns ,
c_st_arr2_1 after 20 ns ,
c_st_arr2_2 after 30 ns ,
c_st_arr2_1 after 40 ns
when 2,
--
c_st_arr2_1 after 5 ns
when 3,
--
c_st_arr2_1 after 100 ns
when 4,
--
c_st_arr2_2 after 10 ns ,
c_st_arr2_1 after 20 ns ,
c_st_arr2_2 after 30 ns ,
c_st_arr2_1 after 40 ns
when 5,
--
-- Last transaction above is marked
c_st_arr2_1 after 40 ns when 6 ;
--
CHG17 :
process
variable correct : boolean ;
begin
case s_st_arr3_cnt is
when 0
=> null ;
-- s_st_arr3 <=
-- c_st_arr3_2 after 10 ns,
-- c_st_arr3_1 after 20 ns ;
--
when 1
=> correct :=
s_st_arr3 =
c_st_arr3_2 and
(s_st_arr3_savt + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_arr3 =
c_st_arr3_1 and
(s_st_arr3_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00381.P17" ,
"Multi inertial transactions occurred on " &
"concurrent signal asg",
correct ) ;
--
st_arr3_select <= transport 2 ;
-- s_st_arr3 <=
-- c_st_arr3_2 after 10 ns ,
-- c_st_arr3_1 after 20 ns ,
-- c_st_arr3_2 after 30 ns ,
-- c_st_arr3_1 after 40 ns ;
--
when 3
=> correct :=
s_st_arr3 =
c_st_arr3_2 and
(s_st_arr3_savt + 10 ns) = Std.Standard.Now ;
st_arr3_select <= transport 3 ;
-- s_st_arr3 <=
-- c_st_arr3_1 after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_arr3 =
c_st_arr3_1 and
(s_st_arr3_savt + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00381" ,
"One inertial transaction occurred on a " &
"concurrent signal asg",
correct ) ;
st_arr3_select <= transport 4 ;
-- s_st_arr3 <=
-- c_st_arr3_1 after 100 ns ;
--
when 5
=> correct :=
correct and
s_st_arr3 =
c_st_arr3_1 and
(s_st_arr3_savt + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00381" ,
"Old transactions were removed on a " &
"concurrent signal asg",
correct ) ;
st_arr3_select <= transport 5 ;
-- s_st_arr3 <=
-- c_st_arr3_2 after 10 ns ,
-- c_st_arr3_1 after 20 ns ,
-- c_st_arr3_2 after 30 ns ,
-- c_st_arr3_1 after 40 ns ;
--
when 6
=> correct :=
correct and
s_st_arr3 =
c_st_arr3_2 and
(s_st_arr3_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00381" ,
"One inertial transaction occurred on a " &
"concurrent signal asg",
correct ) ;
st_arr3_select <= transport 6 ;
-- Last transaction above is marked
-- s_st_arr3 <=
-- c_st_arr3_1 after 40 ns ;
--
when 7
=> correct :=
correct and
s_st_arr3 =
c_st_arr3_1 and
(s_st_arr3_savt + 30 ns) = Std.Standard.Now ;
--
when 8
=> correct :=
correct and
s_st_arr3 =
c_st_arr3_1 and
(s_st_arr3_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00381" ,
"Inertial semantics check on a concurrent " &
"signal asg",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00381" ,
"Inertial semantics check on a concurrent " &
"signal asg",
false ) ;
--
end case ;
--
s_st_arr3_savt <= transport Std.Standard.Now ;
chk_st_arr3 <= transport s_st_arr3_cnt
after (1 us - Std.Standard.Now) ;
s_st_arr3_cnt <= transport s_st_arr3_cnt + 1 ;
wait until (not s_st_arr3'Quiet) and
(s_st_arr3_savt /= Std.Standard.Now) ;
--
end process CHG17 ;
--
PGEN_CHKP_17 :
process ( chk_st_arr3 )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P17" ,
"Inertial transactions completed entirely",
chk_st_arr3 = 8 ) ;
end if ;
end process PGEN_CHKP_17 ;
--
--
with st_arr3_select select
s_st_arr3 <=
c_st_arr3_2 after 10 ns,
c_st_arr3_1 after 20 ns
when 1,
--
c_st_arr3_2 after 10 ns ,
c_st_arr3_1 after 20 ns ,
c_st_arr3_2 after 30 ns ,
c_st_arr3_1 after 40 ns
when 2,
--
c_st_arr3_1 after 5 ns
when 3,
--
c_st_arr3_1 after 100 ns
when 4,
--
c_st_arr3_2 after 10 ns ,
c_st_arr3_1 after 20 ns ,
c_st_arr3_2 after 30 ns ,
c_st_arr3_1 after 40 ns
when 5,
--
-- Last transaction above is marked
c_st_arr3_1 after 40 ns when 6 ;
--
end ARCH00381 ;
--
--
use WORK.STANDARD_TYPES.all ;
entity ENT00381_Test_Bench is
end ENT00381_Test_Bench ;
--
--
architecture ARCH00381_Test_Bench of ENT00381_Test_Bench is
begin
L1:
block
component UUT
end component ;
--
for CIS1 : UUT use entity WORK.ENT00381 ( ARCH00381 ) ;
begin
CIS1 : UUT
;
end block L1 ;
end ARCH00381_Test_Bench ;
| gpl-3.0 | 6b7eb592c8fa483341da373c0db98e1f | 0.46714 | 3.821801 | false | false | false | false |
dcliche/mdsynth | rtl/src/sound/envelope.vhd | 1 | 3,955 | -- MDSynth Sound Chip
--
-- Copyright (c) 2016, Meldora Inc.
-- All rights reserved.
--
-- Redistribution and use in source and binary forms, with or without modification, are permitted provided that the
-- following conditions are met:
--
-- * Redistributions of source code must retain the above copyright notice, this list of conditions and the
-- following disclaimer.
-- * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the
-- following disclaimer in the documentation and/or other materials provided with the distribution.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
-- INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-- DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
-- SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-- SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
-- WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
-- USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
-- ASDR Envelope
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity envelope is
port ( clk: in std_logic;
reset: in std_logic;
note_on: in std_logic;
attack_rate: in unsigned(3 downto 0);
release_rate: in unsigned(3 downto 0);
gain: out unsigned(5 downto 0);
phase: out std_logic_vector(1 downto 0));
end envelope;
architecture envelope_arch of envelope is
type phase_type is (
wait_phase,
attack_phase,
sustain_phase,
release_phase);
signal current_phase: phase_type := wait_phase;
signal current_gain: unsigned(25 downto 0); -- current_gain(25) is carry
begin
process (clk, reset)
begin
if (reset = '1') then
current_phase <= wait_phase;
current_gain <= to_unsigned(0, 26);
elsif (rising_edge(clk)) then
gain <= current_gain(24 downto 19);
case current_phase is
when wait_phase =>
phase <= "00";
if (note_on = '1') then
current_phase <= attack_phase;
end if;
when attack_phase =>
phase <= "01";
if (note_on = '1') then
if (current_gain(25) = '1') then
current_gain <= to_unsigned(33554431, 26);
current_phase <= sustain_phase;
else
current_gain <= current_gain + attack_rate;
end if;
else
current_phase <= release_phase;
end if;
when sustain_phase =>
phase <= "10";
if (note_on = '0') then
current_phase <= release_phase;
end if;
when release_phase =>
phase <= "11";
-- release
if (note_on = '1') then
-- We have a note on during release phase
-- Start a new attack phase
current_gain <= to_unsigned(0, 26);
current_phase <= attack_phase;
else
if (current_gain(25) = '1') then
current_gain <= to_unsigned(0, 26);
current_phase <= wait_phase;
else
current_gain <= current_gain - release_rate;
end if;
end if;
end case;
end if;
end process;
end envelope_arch;
| gpl-3.0 | 612998a4816d74677c2d90a234deace3 | 0.569659 | 4.540758 | false | false | false | false |
wsoltys/AtomFpga | src/T6502/T65_ALU.vhd | 1 | 8,848 | -- ****
-- T65(b) core. In an effort to merge and maintain bug fixes ....
--
--
-- Ver 300 Bugfixes by ehenciak added
-- MikeJ March 2005
-- Latest version from www.fpgaarcade.com (original www.opencores.org)
--
-- ****
--
-- 6502 compatible microprocessor core
--
-- Version : 0245
--
-- Copyright (c) 2002 Daniel Wallner ([email protected])
--
-- All rights reserved
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--
-- Redistributions in synthesized form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- Neither the name of the author nor the names of other contributors may
-- be used to endorse or promote products derived from this software without
-- specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- Please report bugs to the author, but before you do so, please
-- make sure that this is not a derivative work and that
-- you have the latest version of this file.
--
-- The latest version of this file can be found at:
-- http://www.opencores.org/cvsweb.shtml/t65/
--
-- Limitations :
--
-- File history :
--
-- 0245 : First version
--
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.T65_Pack.all;
entity T65_ALU is
port(
Mode : in std_logic_vector(1 downto 0); -- "00" => 6502, "01" => 65C02, "10" => 65816
Op : in std_logic_vector(3 downto 0);
BusA : in std_logic_vector(7 downto 0);
BusB : in std_logic_vector(7 downto 0);
P_In : in std_logic_vector(7 downto 0);
P_Out : out std_logic_vector(7 downto 0);
Q : out std_logic_vector(7 downto 0)
);
end T65_ALU;
architecture rtl of T65_ALU is
-- AddSub variables (temporary signals)
signal ADC_Z : std_logic;
signal ADC_C : std_logic;
signal ADC_V : std_logic;
signal ADC_N : std_logic;
signal ADC_Q : std_logic_vector(7 downto 0);
signal SBC_Z : std_logic;
signal SBC_C : std_logic;
signal SBC_V : std_logic;
signal SBC_N : std_logic;
signal SBC_Q : std_logic_vector(7 downto 0);
begin
process (P_In, BusA, BusB)
variable AL : unsigned(6 downto 0);
variable AH : unsigned(6 downto 0);
variable C : std_logic;
begin
AL := resize(unsigned(BusA(3 downto 0) & P_In(Flag_C)), 7) + resize(unsigned(BusB(3 downto 0) & "1"), 7);
AH := resize(unsigned(BusA(7 downto 4) & AL(5)), 7) + resize(unsigned(BusB(7 downto 4) & "1"), 7);
-- pragma translate_off
if is_x(std_logic_vector(AL)) then AL := "0000000"; end if;
if is_x(std_logic_vector(AH)) then AH := "0000000"; end if;
-- pragma translate_on
if AL(4 downto 1) = 0 and AH(4 downto 1) = 0 then
ADC_Z <= '1';
else
ADC_Z <= '0';
end if;
if AL(5 downto 1) > 9 and P_In(Flag_D) = '1' then
AL(6 downto 1) := AL(6 downto 1) + 6;
end if;
C := AL(6) or AL(5);
AH := resize(unsigned(BusA(7 downto 4) & C), 7) + resize(unsigned(BusB(7 downto 4) & "1"), 7);
ADC_N <= AH(4);
ADC_V <= (AH(4) xor BusA(7)) and not (BusA(7) xor BusB(7));
-- pragma translate_off
if is_x(std_logic_vector(AH)) then AH := "0000000"; end if;
-- pragma translate_on
if AH(5 downto 1) > 9 and P_In(Flag_D) = '1' then
AH(6 downto 1) := AH(6 downto 1) + 6;
end if;
ADC_C <= AH(6) or AH(5);
ADC_Q <= std_logic_vector(AH(4 downto 1) & AL(4 downto 1));
end process;
process (Op, P_In, BusA, BusB)
variable AL : unsigned(6 downto 0);
variable AH : unsigned(5 downto 0);
variable C : std_logic;
begin
C := P_In(Flag_C) or not Op(0);
AL := resize(unsigned(BusA(3 downto 0) & C), 7) - resize(unsigned(BusB(3 downto 0) & "1"), 6);
AH := resize(unsigned(BusA(7 downto 4) & "0"), 6) - resize(unsigned(BusB(7 downto 4) & AL(5)), 6);
-- pragma translate_off
if is_x(std_logic_vector(AL)) then AL := "0000000"; end if;
if is_x(std_logic_vector(AH)) then AH := "000000"; end if;
-- pragma translate_on
if AL(4 downto 1) = 0 and AH(4 downto 1) = 0 then
SBC_Z <= '1';
else
SBC_Z <= '0';
end if;
SBC_C <= not AH(5);
SBC_V <= (AH(4) xor BusA(7)) and (BusA(7) xor BusB(7));
SBC_N <= AH(4);
if P_In(Flag_D) = '1' then
if AL(5) = '1' then
AL(5 downto 1) := AL(5 downto 1) - 6;
end if;
AH := resize(unsigned(BusA(7 downto 4) & "0"), 6) - resize(unsigned(BusB(7 downto 4) & AL(6)), 6);
if AH(5) = '1' then
AH(5 downto 1) := AH(5 downto 1) - 6;
end if;
end if;
SBC_Q <= std_logic_vector(AH(4 downto 1) & AL(4 downto 1));
end process;
process (Op, P_In, BusA, BusB,
ADC_Z, ADC_C, ADC_V, ADC_N, ADC_Q,
SBC_Z, SBC_C, SBC_V, SBC_N, SBC_Q)
variable Q_t : std_logic_vector(7 downto 0);
begin
-- ORA, AND, EOR, ADC, NOP, LD, CMP, SBC
-- ASL, ROL, LSR, ROR, BIT, LD, DEC, INC
P_Out <= P_In;
Q_t := BusA;
case Op(3 downto 0) is
when "0000" =>
-- ORA
Q_t := BusA or BusB;
when "0001" =>
-- AND
Q_t := BusA and BusB;
when "0010" =>
-- EOR
Q_t := BusA xor BusB;
when "0011" =>
-- ADC
P_Out(Flag_V) <= ADC_V;
P_Out(Flag_C) <= ADC_C;
Q_t := ADC_Q;
when "0101" | "1101" =>
-- LDA
when "0110" =>
-- CMP
P_Out(Flag_C) <= SBC_C;
when "0111" =>
-- SBC
P_Out(Flag_V) <= SBC_V;
P_Out(Flag_C) <= SBC_C;
Q_t := SBC_Q;
when "1000" =>
-- ASL
Q_t := BusA(6 downto 0) & "0";
P_Out(Flag_C) <= BusA(7);
when "1001" =>
-- ROL
Q_t := BusA(6 downto 0) & P_In(Flag_C);
P_Out(Flag_C) <= BusA(7);
when "1010" =>
-- LSR
Q_t := "0" & BusA(7 downto 1);
P_Out(Flag_C) <= BusA(0);
when "1011" =>
-- ROR
Q_t := P_In(Flag_C) & BusA(7 downto 1);
P_Out(Flag_C) <= BusA(0);
when "1100" =>
-- BIT
P_Out(Flag_V) <= BusB(6);
when "1110" =>
-- DEC
Q_t := std_logic_vector(unsigned(BusA) - 1);
when "1111" =>
-- INC
Q_t := std_logic_vector(unsigned(BusA) + 1);
when others =>
end case;
case Op(3 downto 0) is
when "0011" =>
P_Out(Flag_N) <= ADC_N;
P_Out(Flag_Z) <= ADC_Z;
when "0110" | "0111" =>
P_Out(Flag_N) <= SBC_N;
P_Out(Flag_Z) <= SBC_Z;
when "0100" =>
when "1100" =>
P_Out(Flag_N) <= BusB(7);
if (BusA and BusB) = "00000000" then
P_Out(Flag_Z) <= '1';
else
P_Out(Flag_Z) <= '0';
end if;
when others =>
P_Out(Flag_N) <= Q_t(7);
if Q_t = "00000000" then
P_Out(Flag_Z) <= '1';
else
P_Out(Flag_Z) <= '0';
end if;
end case;
Q <= Q_t;
end process;
end;
| apache-2.0 | 3dc3aead7b0698bbdc57da26de4951f4 | 0.510511 | 3.493091 | false | false | false | false |
wsoltys/AtomFpga | src/AtomGodilVideo/src/MC6847/mc6847.vhd | 1 | 30,331 | library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
entity mc6847 is
generic
(
T1_VARIANT : boolean := false;
CVBS_NOT_VGA : boolean := false);
port
(
clk : in std_logic;
clk_ena : in std_logic;
reset : in std_logic;
da0 : out std_logic;
videoaddr : out std_logic_vector (12 downto 0);
dd : in std_logic_vector(7 downto 0);
hs_n : out std_logic;
fs_n : out std_logic;
an_g : in std_logic;
an_s : in std_logic;
intn_ext : in std_logic;
gm : in std_logic_vector(2 downto 0);
css : in std_logic;
inv : in std_logic;
red : out std_logic_vector(7 downto 0);
green : out std_logic_vector(7 downto 0);
blue : out std_logic_vector(7 downto 0);
hsync : out std_logic;
vsync : out std_logic;
hblank : out std_logic;
vblank : out std_logic;
artifact_en : in std_logic;
artifact_set : in std_logic;
artifact_phase : in std_logic;
cvbs : out std_logic_vector(7 downto 0);
black_backgnd : in std_logic;
char_a : out std_logic_vector(10 downto 0);
char_d_o : in std_logic_vector(7 downto 0)
);
end mc6847;
architecture SYN of mc6847 is
constant BUILD_DEBUG : boolean := false;
constant DEBUG_AN_G : std_logic := '1';
constant DEBUG_AN_S : std_logic := '1';
constant DEBUG_INTN_EXT : std_logic := '1';
constant DEBUG_GM : std_logic_vector(2 downto 0) := "111";
constant DEBUG_CSS : std_logic := '1';
constant DEBUG_INV : std_logic := '0';
-- H_TOTAL_PER_LINE must be divisible by 16
-- so that sys_count is the same on each line when
-- the video comes out of hblank
-- so the phase relationship between char_d_o from the 6847 and character timing is maintained
-- 14.31818 MHz : 256 X 384 == 25 * 4 / 7 approx
-- constant H_FRONT_PORCH : integer := 11-1 ; --11-1+1;
-- constant H_HORIZ_SYNC : integer := H_FRONT_PORCH + 35+2;
-- constant H_BACK_PORCH : integer := H_HORIZ_SYNC + 34+1;
-- constant H_LEFT_BORDER : integer := H_BACK_PORCH + 61+1;--+3; -- adjust for hblank de-assert @sys_count=6
-- constant H_LEFT_RSTADDR : integer := H_LEFT_BORDER -16;
-- constant H_VIDEO : integer := H_LEFT_BORDER + 256;
-- -- constant H_RIGHT_BORDER : integer := H_VIDEO + 61+1;---3; -- "
-- constant H_RIGHT_BORDER : integer := H_VIDEO + 54;---3; -- tweak to get to 60hz exactly
-- constant H_TOTAL_PER_LINE : integer := H_RIGHT_BORDER;
-- 12.5714 MHz = 32 * 11 / 28
constant H_FRONT_PORCH : integer := 8;
constant H_HORIZ_SYNC : integer := H_FRONT_PORCH + 48;
constant H_BACK_PORCH : integer := H_HORIZ_SYNC + 24;
constant H_LEFT_BORDER : integer := H_BACK_PORCH + 32; -- adjust for hblank de-assert @sys_count=6
constant H_LEFT_RSTADDR : integer := H_LEFT_BORDER - 16;
constant H_VIDEO : integer := H_LEFT_BORDER + 256;
constant H_RIGHT_BORDER : integer := H_VIDEO + 31; -- "
constant H_TOTAL_PER_LINE : integer := H_RIGHT_BORDER;
constant V2_FRONT_PORCH : integer := 2;
constant V2_VERTICAL_SYNC : integer := V2_FRONT_PORCH + 2;
constant V2_BACK_PORCH : integer := V2_VERTICAL_SYNC + 12;
constant V2_TOP_BORDER : integer := V2_BACK_PORCH + 27; -- + 25; -- +25 for PAL
constant V2_VIDEO : integer := V2_TOP_BORDER + 192;
constant V2_BOTTOM_BORDER : integer := V2_VIDEO + 27; -- + 25; -- +25 for PAL
constant V2_TOTAL_PER_FIELD : integer := V2_BOTTOM_BORDER;
-- internal version of control ports
signal an_g_s : std_logic;
signal an_s_s : std_logic;
signal intn_ext_s : std_logic;
signal gm_s : std_logic_vector(2 downto 0);
signal css_s : std_logic;
signal inv_s : std_logic;
-- VGA signals
signal vga_hsync : std_logic;
signal vga_vsync : std_logic;
signal vga_hblank : std_logic;
signal vga_vblank : std_logic;
signal vga_linebuf_addr : std_logic_vector(8 downto 0);
signal vga_char_d_o : std_logic_vector(7 downto 0);
signal vga_hborder : std_logic;
signal vga_vborder : std_logic;
-- CVBS signals
signal cvbs_clk_ena : std_logic; -- PAL/NTSC*2
signal cvbs_hsync : std_logic;
signal cvbs_vsync : std_logic;
signal cvbs_hblank : std_logic;
signal cvbs_vblank : std_logic;
signal cvbs_hborder : std_logic;
signal cvbs_vborder : std_logic;
signal cvbs_linebuf_we : std_logic;
signal cvbs_linebuf_addr : std_logic_vector(8 downto 0);
signal active_h_start : std_logic := '0';
signal an_s_r : std_logic;
signal inv_r : std_logic;
signal intn_ext_r : std_logic;
signal dd_r : std_logic_vector(7 downto 0);
signal pixel_char_d_o : std_logic_vector(7 downto 0);
signal cvbs_char_d_o : std_logic_vector(7 downto 0); -- CVBS char_d_o out
alias hs_int : std_logic is cvbs_hblank;
alias fs_int : std_logic is cvbs_vblank;
signal da0_int : std_logic_vector(4 downto 0);
-- character rom signals
signal cvbs_linebuf_we_r : std_logic;
signal cvbs_linebuf_addr_r : std_logic_vector(8 downto 0);
signal cvbs_linebuf_we_rr : std_logic;
signal cvbs_linebuf_addr_rr : std_logic_vector(8 downto 0);
signal lookup : std_logic_vector(5 downto 0);
signal tripletaddr : std_logic_vector(7 downto 0);
signal tripletcnt : std_logic_vector(3 downto 0);
-----------------------------------------------------------------------
type vram_type is array (511 downto 0) of std_logic_vector (7 downto 0);
signal VRAM : vram_type := (511 downto 0 => X"FF");
attribute RAM_STYLE : string;
attribute RAM_STYLE of VRAM : signal is "BLOCK";
------------------------------------------------------------------------
-- used by both CVBS and VGA
shared variable v_count : std_logic_vector(8 downto 0);
shared variable row_v : std_logic_vector(3 downto 0);
procedure map_palette (vga_char_d_o : in std_logic_vector(7 downto 0);
r : out std_logic_vector(7 downto 0);
g : out std_logic_vector(7 downto 0);
b : out std_logic_vector(7 downto 0)) is
type pal_entry_t is array (0 to 2) of std_logic_vector(1 downto 0);
type pal_a is array (0 to 7) of pal_entry_t;
constant pal : pal_a :=
(
0 => (0 => "00", 1 => "11", 2=>"00"), -- green
1 => (0 => "11", 1 => "11", 2=>"00"), -- yellow
2 => (0 => "00", 1 => "00", 2=>"11"), -- blue
3 => (0 => "11", 1 => "00", 2=>"00"), -- red
4 => (0 => "11", 1 => "11", 2=>"11"), -- white
5 => (0 => "00", 1 => "11", 2=>"11"), -- cyan
6 => (0 => "11", 1 => "00", 2=>"11"), -- magenta
7 => (0 => "11", 1 => "10", 2=>"00") -- orange
--others => (others => (others => '0'))
);
alias css_v : std_logic is vga_char_d_o(6);
alias an_g_v : std_logic is vga_char_d_o(5);
alias an_s_v : std_logic is vga_char_d_o(4);
alias luma : std_logic is vga_char_d_o(3);
alias chroma : std_logic_vector(2 downto 0) is vga_char_d_o(2 downto 0);
begin
if luma = '1' then
r := pal(to_integer(unsigned(chroma)))(0) & "000000";
g := pal(to_integer(unsigned(chroma)))(1) & "000000";
b := pal(to_integer(unsigned(chroma)))(2) & "000000";
else
-- not quite black in alpha mode
if black_backgnd = '0' and an_g_v = '0' and an_s_v = '0' then
-- dark green/orange
r := '0' & css_v & "000000";
g := "01000000";
else
r := (others => '0');
g := (others => '0');
end if;
b := (others => '0');
end if;
end procedure;
begin
-- assign control inputs for debug/release build
an_g_s <= DEBUG_AN_G when BUILD_DEBUG else an_g;
an_s_s <= DEBUG_AN_S when BUILD_DEBUG else an_s;
intn_ext_s <= DEBUG_INTN_EXT when BUILD_DEBUG else intn_ext;
gm_s <= DEBUG_GM when BUILD_DEBUG else gm;
css_s <= DEBUG_CSS when BUILD_DEBUG else css;
inv_s <= DEBUG_INV when BUILD_DEBUG else inv;
-- generate the clocks
PROC_CLOCKS : process (clk, reset)
variable toggle : std_logic := '0';
begin
if reset = '1' then
toggle := '0';
cvbs_clk_ena <= '0';
elsif rising_edge(clk) then
cvbs_clk_ena <= '0'; -- default
if clk_ena = '1' then
cvbs_clk_ena <= toggle;
toggle := not toggle;
end if;
end if;
end process PROC_CLOCKS;
-- generate horizontal timing for VGA
-- generate line buffer address for reading VGA char_d_o
PROC_VGA : process (clk, reset)
variable h_count : integer range 0 to H_TOTAL_PER_LINE;
variable active_h_count : std_logic_vector(7 downto 0);
variable vga_vblank_r : std_logic;
begin
if reset = '1' then
h_count := 0;
vga_hsync <= '1';
vga_vsync <= '1';
vga_hblank <= '0';
elsif rising_edge (clk) and clk_ena = '1' then
-- start hsync when cvbs comes out of vblank
if vga_vblank_r = '1' and vga_vblank = '0' then
h_count := 0;
else
if h_count = H_TOTAL_PER_LINE then
h_count := 0;
vga_hborder <= '0';
else
h_count := h_count + 1;
end if;
if h_count = H_FRONT_PORCH then
vga_hsync <= '0';
elsif h_count = H_HORIZ_SYNC then
vga_hsync <= '1';
elsif h_count = H_BACK_PORCH then
vga_hborder <= '1';
elsif h_count = H_LEFT_BORDER+1 then
vga_hblank <= '0';
elsif h_count = H_VIDEO+1 then
vga_hblank <= '1';
elsif h_count = H_RIGHT_BORDER then
vga_hborder <= '0';
end if;
if h_count = H_LEFT_BORDER then
active_h_count := (others => '1');
else
active_h_count := std_logic_vector(unsigned(active_h_count) + 1);
end if;
end if;
-- vertical syncs, blanks are the same
vga_vsync <= cvbs_vsync;
-- generate linebuffer address
-- - alternate every 2nd line
vga_linebuf_addr <= (not v_count(0)) & active_h_count;
vga_vblank_r := vga_vblank;
end if;
end process;
-- generate horizontal timing for CVBS
-- generate line buffer address for writing CVBS char_d_o
PROC_CVBS : process (clk, reset)
variable h_count : integer range 0 to H_TOTAL_PER_LINE;
variable active_h_count : std_logic_vector(7 downto 0);
variable cvbs_hblank_r : std_logic := '0';
--variable row_v : std_logic_vector(3 downto 0);
-- for debug only
variable active_v_count : std_logic_vector(v_count'range);
begin
if reset = '1' then
h_count := H_TOTAL_PER_LINE;
v_count := std_logic_vector(to_unsigned(V2_TOTAL_PER_FIELD, v_count'length));
active_h_count := (others => '0');
active_h_start <= '0';
cvbs_hsync <= '1';
cvbs_vsync <= '1';
cvbs_hblank <= '0';
cvbs_vblank <= '1';
vga_vblank <= '1';
da0_int <= (others => '0');
cvbs_hblank_r := '0';
row_v := (others => '0');
elsif rising_edge (clk) and cvbs_clk_ena = '1' then
active_h_start <= '0';
if h_count = H_TOTAL_PER_LINE then
h_count := 0;
if v_count = V2_TOTAL_PER_FIELD then
v_count := (others => '0');
else
v_count := v_count + 1;
end if;
-- VGA vblank is 1 line behind CVBS
-- - because we need to fill the line buffer
vga_vblank <= cvbs_vblank;
if v_count = V2_FRONT_PORCH then
cvbs_vsync <= '0';
elsif v_count = V2_VERTICAL_SYNC then
cvbs_vsync <= '1';
elsif v_count = V2_BACK_PORCH then
cvbs_vborder <= '1';
elsif v_count = V2_TOP_BORDER then
cvbs_vblank <= '0';
row_v := (others => '0');
active_v_count := (others => '0');
tripletaddr <= (others => '0');
tripletcnt <= (others => '0');
elsif v_count = V2_VIDEO then
cvbs_vblank <= '1';
elsif v_count = V2_BOTTOM_BORDER then
cvbs_vborder <= '0';
else
if row_v = 11 then
row_v := (others => '0');
if an_g_s = '0' then
active_v_count := active_v_count + 5; -- step for alphas
else
active_v_count := active_v_count + 1; -- mode 4,4a
end if;
else
row_v := row_v + 1;
active_v_count := active_v_count + 1;
end if;
if tripletcnt = 2 then -- mode 1,1a,2a
tripletcnt <= (others => '0');
tripletaddr <= tripletaddr + 1;
else
tripletcnt <= tripletcnt + 1;
end if;
end if;
else
h_count := h_count + 1;
if h_count = H_FRONT_PORCH then
cvbs_hsync <= '0';
elsif h_count = H_HORIZ_SYNC then
cvbs_hsync <= '1';
elsif h_count = H_BACK_PORCH then
elsif h_count = H_LEFT_RSTADDR then
active_h_count := (others => '0');
elsif h_count = H_LEFT_BORDER then
cvbs_hblank <= '0';
active_h_start <= '1';
elsif h_count = H_VIDEO then
cvbs_hblank <= '1';
active_h_count := active_h_count + 1;
elsif h_count = H_RIGHT_BORDER then
null;
else
active_h_count := active_h_count + 1;
end if;
end if;
-- generate character rom address
char_a <= dd(6 downto 0) & row_v(3 downto 0);
-- DA0 high during FS
if cvbs_vblank = '1' then
da0_int <= (others => '1');
elsif cvbs_hblank = '1' then
da0_int <= (others => '0');
elsif cvbs_hblank_r = '1' and cvbs_hblank = '0' then
da0_int <= "01000";
else
da0_int <= da0_int + 1;
end if;
cvbs_linebuf_addr <= v_count(0) & active_h_count;
-- pipeline writes to linebuf because char_d_o is delayed 1 clock as well!
cvbs_linebuf_we_r <= cvbs_linebuf_we;
cvbs_linebuf_addr_r <= cvbs_linebuf_addr;
cvbs_linebuf_we_rr <= cvbs_linebuf_we_r;
cvbs_linebuf_addr_rr <= cvbs_linebuf_addr_r;
cvbs_hblank_r := cvbs_hblank;
if an_g_s = '0' then
lookup(4 downto 0) <= active_h_count(7 downto 3) + 1;
videoaddr <= "000" & active_v_count(8 downto 4) & lookup(4 downto 0);
else
case gm is --lookupaddr
when "000" =>
lookup(3 downto 0) <= active_h_count(7 downto 4) + 1;
videoaddr <= "0" & tripletaddr(7 downto 0) & lookup(3 downto 0);
when "001" =>
lookup(3 downto 0) <= active_h_count(7 downto 4) + 1;
videoaddr <= "0" & tripletaddr(7 downto 0) & lookup(3 downto 0);
when "010" =>
lookup(4 downto 0) <= active_h_count(7 downto 3) + 1;
videoaddr <= tripletaddr(7 downto 0) & lookup(4 downto 0);
when "011" =>
lookup(3 downto 0) <= active_h_count(7 downto 4) + 1;
videoaddr <= "00" &active_v_count(7 downto 1) & lookup(3 downto 0);
when "100" =>
lookup(4 downto 0) <= active_h_count(7 downto 3) + 1;
videoaddr <= "0" & active_v_count(7 downto 1) & lookup(4 downto 0);
when "101" =>
lookup(3 downto 0) <= active_h_count(7 downto 4) + 1;
videoaddr <= "0" &active_v_count(7 downto 0) & lookup(3 downto 0);
when "110" =>
lookup(4 downto 0) <= active_h_count(7 downto 3) + 1;
videoaddr <= active_v_count(7 downto 0) & lookup(4 downto 0);
when "111" =>
lookup(4 downto 0) <= active_h_count(7 downto 3) + 1;
videoaddr <= active_v_count(7 downto 0) & lookup(4 downto 0);
when others =>
null;
end case;
end if;
end if; -- cvbs_clk_ena
end process;
-- handle latching & shifting of character, graphics char_d_o
process (clk, reset)
variable count : std_logic_vector(3 downto 0) := (others => '0');
begin
if reset = '1' then
count := (others => '0');
elsif rising_edge(clk) and cvbs_clk_ena = '1' then
if active_h_start = '1' then
count := (others => '0');
end if;
if an_g_s = '0' then
-- alpha-semi modes
if count(2 downto 0) = 0 then
-- handle alpha-semi latching
an_s_r <= an_s_s;
inv_r <= inv_s;
intn_ext_r <= intn_ext_s;
if an_s_s = '0' then
dd_r <= char_d_o; -- alpha mode
else
-- store luma,chroma(2..0),luma,chroma(2..0)
if intn_ext_s = '0' then -- semi-4
if row_v < 6 then
dd_r <= dd(3) & dd(6) & dd(5) & dd(4) &
dd(2) & dd(6) & dd(5) & dd(4);
else
dd_r <= dd(1) & dd(6) & dd(5) & dd(4) &
dd(0) & dd(6) & dd(5) & dd(4);
end if;
else -- semi-6
if row_v < 4 then
dd_r <= dd(5) & css_s & dd(7) & dd(6) &
dd(4) & css_s & dd(7) & dd(6);
elsif row_v < 8 then
dd_r <= dd(3) & css_s & dd(7) & dd(6) &
dd(2) & css_s & dd(7) & dd(6);
else
dd_r <= dd(1) & css_s & dd(7) & dd(6) &
dd(0) & css_s & dd(7) & dd(6);
end if;
end if;
end if;
else
-- handle alpha-semi shifting
if an_s_r = '0' then
dd_r <= dd_r(dd_r'left-1 downto 0) & '0'; -- alpha mode
else
if count(1 downto 0) = 0 then
dd_r <= dd_r(dd_r'left-4 downto 0) & "0000"; -- semi mode
end if;
end if;
end if;
else
-- graphics modes
--if IN_SIMULATION then
an_s_r <= '0';
--end if;
case gm_s is
when "000" | "001" | "011" | "101" => -- CG1/RG1/RG2/RG3
if count(3 downto 0) = 0 then
-- handle graphics latching
dd_r <= dd;
else
-- handle graphics shifting
if gm_s = "000" then
if count(1 downto 0) = 0 then
dd_r <= dd_r(dd_r'left-2 downto 0) & "00"; -- CG1
end if;
else
if count(0) = '0' then
dd_r <= dd_r(dd_r'left-1 downto 0) & '0'; -- RG1/RG2/RG3
end if;
end if;
end if;
when others => -- CG2/CG3/CG6/RG6
if count(2 downto 0) = 0 then
-- handle graphics latching
dd_r <= dd;
else
-- handle graphics shifting
if gm_s = "111" then
dd_r <= dd_r(dd_r'left-1 downto 0) & '0'; -- RG6
else
if count(0) = '0' then
dd_r <= dd_r(dd_r'left-2 downto 0) & "00"; -- CG2/CG3/CG6
end if;
end if;
end if;
end case;
end if;
count := count + 1;
end if;
end process;
-- generate pixel char_d_o
process (clk, reset)
variable luma : std_logic;
variable chroma : std_logic_vector(2 downto 0);
begin
if reset = '1' then
elsif rising_edge(clk) and cvbs_clk_ena = '1' then
-- alpha/graphics mode
if an_g_s = '0' then
-- alphanumeric & semi-graphics mode
luma := dd_r(dd_r'left);
if an_s_r = '0' then
-- alphanumeric
if intn_ext_r = '0' then
-- internal rom
chroma := (others => css_s);
if inv_r = '1' then
luma := not luma;
end if; -- normal/inverse
else
-- external ROM?!?
end if; -- internal/external
else
chroma := dd_r(dd_r'left-1 downto dd_r'left-3);
end if; -- alphanumeric/semi-graphics
else
-- graphics mode
case gm_s is
when "000" => -- CG1 64x64x4
luma := '1';
chroma := css_s & dd_r(dd_r'left downto dd_r'left-1);
when "001" | "011" | "101" => -- RG1/2/3 128x64/96/192x2
luma := dd_r(dd_r'left);
chroma := css_s & "00"; -- green/buff
when "010" | "100" | "110" => -- CG2/3/6 128x64/96/192x4
luma := '1';
chroma := css_s & dd_r(dd_r'left downto dd_r'left-1);
when others => -- RG6 256x192x2
luma := dd_r(dd_r'left);
chroma := css_s & "00"; -- green/buff
end case;
end if; -- alpha/graphics mode
-- pack source char_d_o into line buffer
-- - palette lookup on output
pixel_char_d_o <= '0' & css_s & an_g_s & an_s_r & luma & chroma;
end if;
end process;
-- only write to the linebuffer during active display
cvbs_linebuf_we <= not (cvbs_vblank or cvbs_hblank);
cvbs <= '0' & cvbs_vsync & "000000" when cvbs_vblank = '1' else
'0' & cvbs_hsync & "000000" when cvbs_hblank = '1' else
cvbs_char_d_o;
-- assign outputs
hs_n <= not hs_int;
fs_n <= not fs_int;
da0 <= da0_int(4) when (gm_s = "001" or gm_s = "011" or gm_s = "101") else
da0_int(3);
-- map the palette to the pixel char_d_o
-- - we do that at the output so we can use a
-- higher colour-resolution palette
-- without using memory in the line buffer
PROC_OUTPUT : process (clk)
variable r : std_logic_vector(red'range);
variable g : std_logic_vector(green'range);
variable b : std_logic_vector(blue'range);
-- for artifacting testing only
variable p_in : std_logic_vector(vga_char_d_o'range);
variable p_out : std_logic_vector(vga_char_d_o'range);
variable count : std_logic := '0';
begin
if reset = '1' then
count := '0';
elsif rising_edge(clk) then
if CVBS_NOT_VGA then
if cvbs_clk_ena = '1' then
if cvbs_hblank = '0' and cvbs_vblank = '0' then
map_palette (vga_char_d_o, r, g, b);
else
r := (others => '0');
g := (others => '0');
b := (others => '0');
end if;
end if;
else
if clk_ena = '1' then
if vga_hblank = '1' then
count := '0';
p_in := (others => '0');
end if;
if vga_hblank = '0' and vga_vblank = '0' then
-- artifacting test only --
if artifact_en = '1' and an_g_s = '1' and gm_s = "111" then
if count /= '0' then
p_out(p_out'left downto 4) := vga_char_d_o(p_out'left downto 4);
if p_in(3) = '0' and vga_char_d_o(3) = '0' then
p_out(3 downto 0) := "0000";
elsif p_in(3) = '1' and vga_char_d_o(3) = '1' then
p_out(3 downto 0) := "1100";
elsif p_in(3) = '0' and vga_char_d_o(3) = '1' then
p_out(3 downto 0) := "1011"; -- red
--p_out(3 downto 0) := "1101"; -- cyan
else
p_out(3 downto 0) := "1010"; -- blue
--p_out(3 downto 0) := "1111"; -- orange
end if;
end if;
map_palette (p_out, r, g, b);
p_in := vga_char_d_o;
else
map_palette (vga_char_d_o, r, g, b);
end if;
count := not count;
elsif an_g_s = '1' and vga_hborder = '1' and cvbs_vborder = '1' then
-- graphics mode, either green or buff (white)
map_palette ("00001" & css_s & "00", r, g, b);
else
r := (others => '0');
g := (others => '0');
b := (others => '0');
end if;
end if;
end if; -- CVBS_NOT_VGA
red <= r; green <= g; blue <= b;
end if; -- rising_edge(clk)
if CVBS_NOT_VGA then
hsync <= cvbs_hsync;
vsync <= cvbs_vsync;
hblank <= cvbs_hblank;
vblank <= cvbs_vblank;
else
hsync <= vga_hsync;
vsync <= vga_vsync;
hblank <= not vga_hborder;
vblank <= not cvbs_vborder;
end if;
end process PROC_OUTPUT;
-- line buffer for scan doubler gives us vga monitor compatible output
process (clk)
begin
if rising_edge(clk) then
if cvbs_clk_ena = '1' then
if (cvbs_linebuf_we_rr = '1') then
VRAM(conv_integer(cvbs_linebuf_addr_rr(8 downto 0))) <= pixel_char_d_o;
end if;
end if;
if clk_ena = '1' then
vga_char_d_o <= VRAM(conv_integer(vga_linebuf_addr(8 downto 0)));
end if;
end if;
end process;
---- rom for char generator
-- charrom_inst : entity work.mc6847t1_ntsc_plus_keith
-- port map(
-- CLK => clk,
-- ADDR => char_a,
-- DATA => char_d_o
-- );
end SYN;
| apache-2.0 | 1e33b86722aefb6365323d9ca30663d8 | 0.420329 | 3.865299 | false | false | false | false |
jairov4/accel-oil | impl/impl_test_single/hdl/system_ilmb_wrapper.vhd | 2 | 3,835 | -------------------------------------------------------------------------------
-- system_ilmb_wrapper.vhd
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
library lmb_v10_v2_00_b;
use lmb_v10_v2_00_b.all;
entity system_ilmb_wrapper is
port (
LMB_Clk : in std_logic;
SYS_Rst : in std_logic;
LMB_Rst : out std_logic;
M_ABus : in std_logic_vector(0 to 31);
M_ReadStrobe : in std_logic;
M_WriteStrobe : in std_logic;
M_AddrStrobe : in std_logic;
M_DBus : in std_logic_vector(0 to 31);
M_BE : in std_logic_vector(0 to 3);
Sl_DBus : in std_logic_vector(0 to 31);
Sl_Ready : in std_logic_vector(0 to 0);
Sl_Wait : in std_logic_vector(0 to 0);
Sl_UE : in std_logic_vector(0 to 0);
Sl_CE : in std_logic_vector(0 to 0);
LMB_ABus : out std_logic_vector(0 to 31);
LMB_ReadStrobe : out std_logic;
LMB_WriteStrobe : out std_logic;
LMB_AddrStrobe : out std_logic;
LMB_ReadDBus : out std_logic_vector(0 to 31);
LMB_WriteDBus : out std_logic_vector(0 to 31);
LMB_Ready : out std_logic;
LMB_Wait : out std_logic;
LMB_UE : out std_logic;
LMB_CE : out std_logic;
LMB_BE : out std_logic_vector(0 to 3)
);
attribute x_core_info : STRING;
attribute x_core_info of system_ilmb_wrapper : entity is "lmb_v10_v2_00_b";
end system_ilmb_wrapper;
architecture STRUCTURE of system_ilmb_wrapper is
component lmb_v10 is
generic (
C_LMB_NUM_SLAVES : integer;
C_LMB_AWIDTH : integer;
C_LMB_DWIDTH : integer;
C_EXT_RESET_HIGH : integer
);
port (
LMB_Clk : in std_logic;
SYS_Rst : in std_logic;
LMB_Rst : out std_logic;
M_ABus : in std_logic_vector(0 to C_LMB_AWIDTH-1);
M_ReadStrobe : in std_logic;
M_WriteStrobe : in std_logic;
M_AddrStrobe : in std_logic;
M_DBus : in std_logic_vector(0 to C_LMB_DWIDTH-1);
M_BE : in std_logic_vector(0 to (C_LMB_DWIDTH+7)/8-1);
Sl_DBus : in std_logic_vector(0 to (C_LMB_DWIDTH*C_LMB_NUM_SLAVES)-1);
Sl_Ready : in std_logic_vector(0 to C_LMB_NUM_SLAVES-1);
Sl_Wait : in std_logic_vector(0 to C_LMB_NUM_SLAVES-1);
Sl_UE : in std_logic_vector(0 to C_LMB_NUM_SLAVES-1);
Sl_CE : in std_logic_vector(0 to C_LMB_NUM_SLAVES-1);
LMB_ABus : out std_logic_vector(0 to C_LMB_AWIDTH-1);
LMB_ReadStrobe : out std_logic;
LMB_WriteStrobe : out std_logic;
LMB_AddrStrobe : out std_logic;
LMB_ReadDBus : out std_logic_vector(0 to C_LMB_DWIDTH-1);
LMB_WriteDBus : out std_logic_vector(0 to C_LMB_DWIDTH-1);
LMB_Ready : out std_logic;
LMB_Wait : out std_logic;
LMB_UE : out std_logic;
LMB_CE : out std_logic;
LMB_BE : out std_logic_vector(0 to (C_LMB_DWIDTH+7)/8-1)
);
end component;
begin
ilmb : lmb_v10
generic map (
C_LMB_NUM_SLAVES => 1,
C_LMB_AWIDTH => 32,
C_LMB_DWIDTH => 32,
C_EXT_RESET_HIGH => 1
)
port map (
LMB_Clk => LMB_Clk,
SYS_Rst => SYS_Rst,
LMB_Rst => LMB_Rst,
M_ABus => M_ABus,
M_ReadStrobe => M_ReadStrobe,
M_WriteStrobe => M_WriteStrobe,
M_AddrStrobe => M_AddrStrobe,
M_DBus => M_DBus,
M_BE => M_BE,
Sl_DBus => Sl_DBus,
Sl_Ready => Sl_Ready,
Sl_Wait => Sl_Wait,
Sl_UE => Sl_UE,
Sl_CE => Sl_CE,
LMB_ABus => LMB_ABus,
LMB_ReadStrobe => LMB_ReadStrobe,
LMB_WriteStrobe => LMB_WriteStrobe,
LMB_AddrStrobe => LMB_AddrStrobe,
LMB_ReadDBus => LMB_ReadDBus,
LMB_WriteDBus => LMB_WriteDBus,
LMB_Ready => LMB_Ready,
LMB_Wait => LMB_Wait,
LMB_UE => LMB_UE,
LMB_CE => LMB_CE,
LMB_BE => LMB_BE
);
end architecture STRUCTURE;
| lgpl-3.0 | fd8038b9e6e237448fcb939d792ca1eb | 0.574707 | 3.092742 | false | true | false | false |
grwlf/vsim | vhdl_ct/ct00236.vhd | 1 | 11,136 | -- NEED RESULT: ENT00236.P00236: Associated composite buffer ports with static subtypes passed
-- NEED RESULT: ENT00236: Associated composite buffer ports with static subtypes passed
-- NEED RESULT: ENT00236.P00236: Associated composite buffer ports with static subtypes passed
-------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
-------------------------------------------------------------------------------
--
-- TEST NAME:
--
-- CT00236
--
-- AUTHOR:
--
-- A. Wilmot
--
-- TEST OBJECTIVES:
--
-- 1.1.1.2 (4)
-- 1.1.1.2 (7)
--
-- DESIGN UNIT ORDERING:
--
-- ENT00236(ARCH00236)
-- ENT00236_Test_Bench(ARCH00236_Test_Bench)
--
-- REVISION HISTORY:
--
-- 25-JUN-1987 - initial revision
--
-- NOTES:
--
-- self-checking
-- automatically generated
--
use WORK.STANDARD_TYPES.all ;
entity ENT00236 is
port (
toggle : buffer switch := down;
i_bit_vector_1, i_bit_vector_2 : buffer bit_vector
:= c_st_bit_vector_1
;
i_string_1, i_string_2 : buffer string
:= c_st_string_1
;
i_t_rec1_1, i_t_rec1_2 : buffer t_rec1
:= c_st_rec1_1
;
i_st_rec1_1, i_st_rec1_2 : buffer st_rec1
:= c_st_rec1_1
;
i_t_rec2_1, i_t_rec2_2 : buffer t_rec2
:= c_st_rec2_1
;
i_st_rec2_1, i_st_rec2_2 : buffer st_rec2
:= c_st_rec2_1
;
i_t_rec3_1, i_t_rec3_2 : buffer t_rec3
:= c_st_rec3_1
;
i_st_rec3_1, i_st_rec3_2 : buffer st_rec3
:= c_st_rec3_1
;
i_t_arr1_1, i_t_arr1_2 : buffer t_arr1
:= c_st_arr1_1
;
i_st_arr1_1, i_st_arr1_2 : buffer st_arr1
:= c_st_arr1_1
;
i_t_arr2_1, i_t_arr2_2 : buffer t_arr2
:= c_st_arr2_1
;
i_st_arr2_1, i_st_arr2_2 : buffer st_arr2
:= c_st_arr2_1
;
i_t_arr3_1, i_t_arr3_2 : buffer t_arr3
:= c_st_arr3_1
;
i_st_arr3_1, i_st_arr3_2 : buffer st_arr3
:= c_st_arr3_1
) ;
begin
end ENT00236 ;
--
architecture ARCH00236 of ENT00236 is
begin
process
variable correct : boolean := true ;
begin
correct := correct and i_bit_vector_1 = c_st_bit_vector_1
and i_bit_vector_2 = c_st_bit_vector_1 ;
correct := correct and i_string_1 = c_st_string_1
and i_string_2 = c_st_string_1 ;
correct := correct and i_t_rec1_1 = c_st_rec1_1
and i_t_rec1_2 = c_st_rec1_1 ;
correct := correct and i_st_rec1_1 = c_st_rec1_1
and i_st_rec1_2 = c_st_rec1_1 ;
correct := correct and i_t_rec2_1 = c_st_rec2_1
and i_t_rec2_2 = c_st_rec2_1 ;
correct := correct and i_st_rec2_1 = c_st_rec2_1
and i_st_rec2_2 = c_st_rec2_1 ;
correct := correct and i_t_rec3_1 = c_st_rec3_1
and i_t_rec3_2 = c_st_rec3_1 ;
correct := correct and i_st_rec3_1 = c_st_rec3_1
and i_st_rec3_2 = c_st_rec3_1 ;
correct := correct and i_t_arr1_1 = c_st_arr1_1
and i_t_arr1_2 = c_st_arr1_1 ;
correct := correct and i_st_arr1_1 = c_st_arr1_1
and i_st_arr1_2 = c_st_arr1_1 ;
correct := correct and i_t_arr2_1 = c_st_arr2_1
and i_t_arr2_2 = c_st_arr2_1 ;
correct := correct and i_st_arr2_1 = c_st_arr2_1
and i_st_arr2_2 = c_st_arr2_1 ;
correct := correct and i_t_arr3_1 = c_st_arr3_1
and i_t_arr3_2 = c_st_arr3_1 ;
correct := correct and i_st_arr3_1 = c_st_arr3_1
and i_st_arr3_2 = c_st_arr3_1 ;
--
test_report ( "ENT00236" ,
"Associated composite buffer ports with static subtypes" ,
correct) ;
--
toggle <= up ;
i_bit_vector_1 <= c_st_bit_vector_2 ;
i_bit_vector_2 <= c_st_bit_vector_2 ;
i_string_1 <= c_st_string_2 ;
i_string_2 <= c_st_string_2 ;
i_t_rec1_1 <= c_st_rec1_2 ;
i_t_rec1_2 <= c_st_rec1_2 ;
i_st_rec1_1 <= c_st_rec1_2 ;
i_st_rec1_2 <= c_st_rec1_2 ;
i_t_rec2_1 <= c_st_rec2_2 ;
i_t_rec2_2 <= c_st_rec2_2 ;
i_st_rec2_1 <= c_st_rec2_2 ;
i_st_rec2_2 <= c_st_rec2_2 ;
i_t_rec3_1 <= c_st_rec3_2 ;
i_t_rec3_2 <= c_st_rec3_2 ;
i_st_rec3_1 <= c_st_rec3_2 ;
i_st_rec3_2 <= c_st_rec3_2 ;
i_t_arr1_1 <= c_st_arr1_2 ;
i_t_arr1_2 <= c_st_arr1_2 ;
i_st_arr1_1 <= c_st_arr1_2 ;
i_st_arr1_2 <= c_st_arr1_2 ;
i_t_arr2_1 <= c_st_arr2_2 ;
i_t_arr2_2 <= c_st_arr2_2 ;
i_st_arr2_1 <= c_st_arr2_2 ;
i_st_arr2_2 <= c_st_arr2_2 ;
i_t_arr3_1 <= c_st_arr3_2 ;
i_t_arr3_2 <= c_st_arr3_2 ;
i_st_arr3_1 <= c_st_arr3_2 ;
i_st_arr3_2 <= c_st_arr3_2 ;
wait ;
end process ;
end ARCH00236 ;
--
use WORK.STANDARD_TYPES.all ;
entity ENT00236_Test_Bench is
end ENT00236_Test_Bench ;
--
architecture ARCH00236_Test_Bench of ENT00236_Test_Bench is
begin
L1:
block
signal i_bit_vector_1, i_bit_vector_2 : st_bit_vector
:= c_st_bit_vector_1 ;
signal i_string_1, i_string_2 : st_string
:= c_st_string_1 ;
signal i_t_rec1_1, i_t_rec1_2 : st_rec1
:= c_st_rec1_1 ;
signal i_st_rec1_1, i_st_rec1_2 : st_rec1
:= c_st_rec1_1 ;
signal i_t_rec2_1, i_t_rec2_2 : st_rec2
:= c_st_rec2_1 ;
signal i_st_rec2_1, i_st_rec2_2 : st_rec2
:= c_st_rec2_1 ;
signal i_t_rec3_1, i_t_rec3_2 : st_rec3
:= c_st_rec3_1 ;
signal i_st_rec3_1, i_st_rec3_2 : st_rec3
:= c_st_rec3_1 ;
signal i_t_arr1_1, i_t_arr1_2 : st_arr1
:= c_st_arr1_1 ;
signal i_st_arr1_1, i_st_arr1_2 : st_arr1
:= c_st_arr1_1 ;
signal i_t_arr2_1, i_t_arr2_2 : st_arr2
:= c_st_arr2_1 ;
signal i_st_arr2_1, i_st_arr2_2 : st_arr2
:= c_st_arr2_1 ;
signal i_t_arr3_1, i_t_arr3_2 : st_arr3
:= c_st_arr3_1 ;
signal i_st_arr3_1, i_st_arr3_2 : st_arr3
:= c_st_arr3_1 ;
--
component UUT
port (
toggle : buffer switch ;
i_bit_vector_1, i_bit_vector_2 : buffer bit_vector
:= c_st_bit_vector_1
;
i_string_1, i_string_2 : buffer string
:= c_st_string_1
;
i_t_rec1_1, i_t_rec1_2 : buffer t_rec1
:= c_st_rec1_1
;
i_st_rec1_1, i_st_rec1_2 : buffer st_rec1
:= c_st_rec1_1
;
i_t_rec2_1, i_t_rec2_2 : buffer t_rec2
:= c_st_rec2_1
;
i_st_rec2_1, i_st_rec2_2 : buffer st_rec2
:= c_st_rec2_1
;
i_t_rec3_1, i_t_rec3_2 : buffer t_rec3
:= c_st_rec3_1
;
i_st_rec3_1, i_st_rec3_2 : buffer st_rec3
:= c_st_rec3_1
;
i_t_arr1_1, i_t_arr1_2 : buffer t_arr1
:= c_st_arr1_1
;
i_st_arr1_1, i_st_arr1_2 : buffer st_arr1
:= c_st_arr1_1
;
i_t_arr2_1, i_t_arr2_2 : buffer t_arr2
:= c_st_arr2_1
;
i_st_arr2_1, i_st_arr2_2 : buffer st_arr2
:= c_st_arr2_1
;
i_t_arr3_1, i_t_arr3_2 : buffer t_arr3
:= c_st_arr3_1
;
i_st_arr3_1, i_st_arr3_2 : buffer st_arr3
:= c_st_arr3_1
) ;
end component ;
--
for CIS1 : UUT use entity WORK.ENT00236 ( ARCH00236 ) ;
--
begin
CIS1 : UUT
port map (
toggle ,
i_bit_vector_1, i_bit_vector_2,
i_string_1, i_string_2,
i_t_rec1_1, i_t_rec1_2,
i_st_rec1_1, i_st_rec1_2,
i_t_rec2_1, i_t_rec2_2,
i_st_rec2_1, i_st_rec2_2,
i_t_rec3_1, i_t_rec3_2,
i_st_rec3_1, i_st_rec3_2,
i_t_arr1_1, i_t_arr1_2,
i_st_arr1_1, i_st_arr1_2,
i_t_arr2_1, i_t_arr2_2,
i_st_arr2_1, i_st_arr2_2,
i_t_arr3_1, i_t_arr3_2,
i_st_arr3_1, i_st_arr3_2
) ;
P00236 :
process ( toggle )
variable correct : boolean := true ;
begin
if toggle = up then
correct := correct and i_bit_vector_1 = c_st_bit_vector_2
and i_bit_vector_2 = c_st_bit_vector_2 ;
correct := correct and i_string_1 = c_st_string_2
and i_string_2 = c_st_string_2 ;
correct := correct and i_t_rec1_1 = c_st_rec1_2
and i_t_rec1_2 = c_st_rec1_2 ;
correct := correct and i_st_rec1_1 = c_st_rec1_2
and i_st_rec1_2 = c_st_rec1_2 ;
correct := correct and i_t_rec2_1 = c_st_rec2_2
and i_t_rec2_2 = c_st_rec2_2 ;
correct := correct and i_st_rec2_1 = c_st_rec2_2
and i_st_rec2_2 = c_st_rec2_2 ;
correct := correct and i_t_rec3_1 = c_st_rec3_2
and i_t_rec3_2 = c_st_rec3_2 ;
correct := correct and i_st_rec3_1 = c_st_rec3_2
and i_st_rec3_2 = c_st_rec3_2 ;
correct := correct and i_t_arr1_1 = c_st_arr1_2
and i_t_arr1_2 = c_st_arr1_2 ;
correct := correct and i_st_arr1_1 = c_st_arr1_2
and i_st_arr1_2 = c_st_arr1_2 ;
correct := correct and i_t_arr2_1 = c_st_arr2_2
and i_t_arr2_2 = c_st_arr2_2 ;
correct := correct and i_st_arr2_1 = c_st_arr2_2
and i_st_arr2_2 = c_st_arr2_2 ;
correct := correct and i_t_arr3_1 = c_st_arr3_2
and i_t_arr3_2 = c_st_arr3_2 ;
correct := correct and i_st_arr3_1 = c_st_arr3_2
and i_st_arr3_2 = c_st_arr3_2 ;
end if ;
--
test_report ( "ENT00236.P00236" ,
"Associated composite buffer ports with static subtypes",
correct) ;
end process P00236 ;
end block L1 ;
end ARCH00236_Test_Bench ;
| gpl-3.0 | 06688e11424fb8aeb528eba3a4150d6a | 0.434537 | 2.773599 | false | false | false | false |
dcliche/mdsynth | rtl/src/ram2k_b16.vhd | 1 | 8,726 | --===========================================================================--
-- --
-- Synthesizable 2K RAM using Xilinx RAMB16_S9 Block RAM --
-- --
--===========================================================================--
--
-- File name : ram2k_b16.vhd
--
-- Entity name : ram_2k
--
-- Purpose : Implements 2KBytes of RAM using one Xilinx RAMB16_S9 Block RAM
-- Essentially a wrapper for a 2KByte RAM block for different
-- technology FPGAs. Used in vdu8.vhd for the System09 SoC as a
-- character buffer and attribute RAM. Initiatized with rubbish
-- so that the VDU displays random characters on start up to
-- indicate it is working correctly.
--
-- Dependencies : ieee.std_logic_1164
-- ieee.std_logic_arith
--
-- Uses : RAMB16_S9 (Xilinx 16KBit Block RAM)
--
-- Author : John E. Kent
--
-- Email : [email protected]
--
-- Web : http://opencores.org/project,system09
--
-- Description : Block RAM instatiation
--
-- Copyright (C) 2010 John Kent
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
--===========================================================================--
-- --
-- Revision History --
-- --
--===========================================================================--
--
-- Version Date Author Changes
--
-- 0.1 2010-06-17 John Kent Added GPL and header
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
library unisim;
use unisim.vcomponents.all;
entity ram_2k is
Port (
clk : in std_logic;
rst : in std_logic;
cs : in std_logic;
addr : in std_logic_vector (10 downto 0);
rw : in std_logic;
data_in : in std_logic_vector (7 downto 0);
data_out : out std_logic_vector (7 downto 0)
);
end ram_2k;
architecture rtl of ram_2k is
signal we : std_logic;
signal dp : std_logic;
begin
ROM : RAMB16_S9
generic map (
INIT_00 => x"00FF00FF00FF00FF00FF00FF00FF00FF00FF00FF00FF00FF00FF00FF00FF00FF",
INIT_01 => x"00FF00FF00FF00FF00FF00FF00FF00FF00FF00FF00FF00FF00FF00FF00FF00FF",
INIT_02 => x"00FF00FF00FF00FF00FF00FF00FF00FF00FF00FF00FF00FF00FF00FF00FF00FF",
INIT_03 => x"00FF00FF00FF00FF00FF00FF00FF00FF00FF00FF00FF00FF00FF00FF00FF00FF",
INIT_04 => x"00FF00FF00FF00FF00FF00FF00FF00FF00FF00FF00FF00FF00FF00FF00FF00FF",
INIT_05 => x"00FF00FF00FF00FF00FF00FF00FF00FF00FF00FF00FF00FF00FF00FF00FF00FF",
INIT_06 => x"00FF00FF00FF00FF00FF00FF00FF00FF00FF00FF00FF00FF00FF00FF00FF00FF",
INIT_07 => x"00FF00FF00FF00FF00FF00FF00FF00FF00FF00FF00FF00FF00FF00FF00FF00FF",
INIT_08 => x"00FF00FF00FF00FF00FF00FF00FF00FF00FF00FF00FF00FF00FF00FF00FF00FF",
INIT_09 => x"00FF00FF00FF00FF00FF00FF00FF00FF00FF00FF00FF00FF00FF00FF00FF00FF",
INIT_0A => x"00FF00FF00FF00FF00FF00FF00FF00FF00FF00FF00FF00FF00FF00FF00FF00FF",
INIT_0B => x"00FF00FF00FF00FF00FF00FF00FF00FF00FF00FF00FF00FF00FF00FF00FF00FF",
INIT_0C => x"00FF00FF00FF00FF00FF00FF00FF00FF00FF00FF00FF00FF00FF00FF00FF00FF",
INIT_0D => x"00FF00FF00FF00FF00FF00FF00FF00FF00FF00FF00FF00FF00FF00FF00FF00FF",
INIT_0E => x"00FF00FF00FF00FF00FF00FF00FF00FF00FF00FF00FF00FF00FF00FF00FF00FF",
INIT_0F => x"00FF00FF00FF00FF00FF00FF00FF00FF00FF00FF00FF00FF00FF00FF00FF00FF",
INIT_10 => x"00FF00FF00FF00FF00FF00FF00FF00FF00FF00FF00FF00FF00FF00FF00FF00FF",
INIT_11 => x"00FF00FF00FF00FF00FF00FF00FF00FF00FF00FF00FF00FF00FF00FF00FF00FF",
INIT_12 => x"00FF00FF00FF00FF00FF00FF00FF00FF00FF00FF00FF00FF00FF00FF00FF00FF",
INIT_13 => x"00FF00FF00FF00FF00FF00FF00FF00FF00FF00FF00FF00FF00FF00FF00FF00FF",
INIT_14 => x"00FF00FF00FF00FF00FF00FF00FF00FF00FF00FF00FF00FF00FF00FF00FF00FF",
INIT_15 => x"00FF00FF00FF00FF00FF00FF00FF00FF00FF00FF00FF00FF00FF00FF00FF00FF",
INIT_16 => x"00FF00FF00FF00FF00FF00FF00FF00FF00FF00FF00FF00FF00FF00FF00FF00FF",
INIT_17 => x"00FF00FF00FF00FF00FF00FF00FF00FF00FF00FF00FF00FF00FF00FF00FF00FF",
INIT_18 => x"00FF00FF00FF00FF00FF00FF00FF00FF00FF00FF00FF00FF00FF00FF00FF00FF",
INIT_19 => x"00FF00FF00FF00FF00FF00FF00FF00FF00FF00FF00FF00FF00FF00FF00FF00FF",
INIT_1A => x"00FF00FF00FF00FF00FF00FF00FF00FF00FF00FF00FF00FF00FF00FF00FF00FF",
INIT_1B => x"00FF00FF00FF00FF00FF00FF00FF00FF00FF00FF00FF00FF00FF00FF00FF00FF",
INIT_1C => x"00FF00FF00FF00FF00FF00FF00FF00FF00FF00FF00FF00FF00FF00FF00FF00FF",
INIT_1D => x"00FF00FF00FF00FF00FF00FF00FF00FF00FF00FF00FF00FF00FF00FF00FF00FF",
INIT_1E => x"00FF00FF00FF00FF00FF00FF00FF00FF00FF00FF00FF00FF00FF00FF00FF00FF",
INIT_1F => x"00FF00FF00FF00FF00FF00FF00FF00FF00FF00FF00FF00FF00FF00FF00FF00FF",
INIT_20 => x"00FF00FF00FF00FF00FF00FF00FF00FF00FF00FF00FF00FF00FF00FF00FF00FF",
INIT_21 => x"00FF00FF00FF00FF00FF00FF00FF00FF00FF00FF00FF00FF00FF00FF00FF00FF",
INIT_22 => x"00FF00FF00FF00FF00FF00FF00FF00FF00FF00FF00FF00FF00FF00FF00FF00FF",
INIT_23 => x"00FF00FF00FF00FF00FF00FF00FF00FF00FF00FF00FF00FF00FF00FF00FF00FF",
INIT_24 => x"00FF00FF00FF00FF00FF00FF00FF00FF00FF00FF00FF00FF00FF00FF00FF00FF",
INIT_25 => x"00FF00FF00FF00FF00FF00FF00FF00FF00FF00FF00FF00FF00FF00FF00FF00FF",
INIT_26 => x"00FF00FF00FF00FF00FF00FF00FF00FF00FF00FF00FF00FF00FF00FF00FF00FF",
INIT_27 => x"00FF00FF00FF00FF00FF00FF00FF00FF00FF00FF00FF00FF00FF00FF00FF00FF",
INIT_28 => x"00FF00FF00FF00FF00FF00FF00FF00FF00FF00FF00FF00FF00FF00FF00FF00FF",
INIT_29 => x"00FF00FF00FF00FF00FF00FF00FF00FF00FF00FF00FF00FF00FF00FF00FF00FF",
INIT_2A => x"00FF00FF00FF00FF00FF00FF00FF00FF00FF00FF00FF00FF00FF00FF00FF00FF",
INIT_2B => x"00FF00FF00FF00FF00FF00FF00FF00FF00FF00FF00FF00FF00FF00FF00FF00FF",
INIT_2C => x"00FF00FF00FF00FF00FF00FF00FF00FF00FF00FF00FF00FF00FF00FF00FF00FF",
INIT_2D => x"00FF00FF00FF00FF00FF00FF00FF00FF00FF00FF00FF00FF00FF00FF00FF00FF",
INIT_2E => x"00FF00FF00FF00FF00FF00FF00FF00FF00FF00FF00FF00FF00FF00FF00FF00FF",
INIT_2F => x"00FF00FF00FF00FF00FF00FF00FF00FF00FF00FF00FF00FF00FF00FF00FF00FF",
INIT_30 => x"00FF00FF00FF00FF00FF00FF00FF00FF00FF00FF00FF00FF00FF00FF00FF00FF",
INIT_31 => x"00FF00FF00FF00FF00FF00FF00FF00FF00FF00FF00FF00FF00FF00FF00FF00FF",
INIT_32 => x"00FF00FF00FF00FF00FF00FF00FF00FF00FF00FF00FF00FF00FF00FF00FF00FF",
INIT_33 => x"00FF00FF00FF00FF00FF00FF00FF00FF00FF00FF00FF00FF00FF00FF00FF00FF",
INIT_34 => x"00FF00FF00FF00FF00FF00FF00FF00FF00FF00FF00FF00FF00FF00FF00FF00FF",
INIT_35 => x"00FF00FF00FF00FF00FF00FF00FF00FF00FF00FF00FF00FF00FF00FF00FF00FF",
INIT_36 => x"00FF00FF00FF00FF00FF00FF00FF00FF00FF00FF00FF00FF00FF00FF00FF00FF",
INIT_37 => x"00FF00FF00FF00FF00FF00FF00FF00FF00FF00FF00FF00FF00FF00FF00FF00FF",
INIT_38 => x"00FF00FF00FF00FF00FF00FF00FF00FF00FF00FF00FF00FF00FF00FF00FF00FF",
INIT_39 => x"00FF00FF00FF00FF00FF00FF00FF00FF00FF00FF00FF00FF00FF00FF00FF00FF",
INIT_3A => x"00FF00FF00FF00FF00FF00FF00FF00FF00FF00FF00FF00FF00FF00FF00FF00FF",
INIT_3B => x"00FF00FF00FF00FF00FF00FF00FF00FF00FF00FF00FF00FF00FF00FF00FF00FF",
INIT_3C => x"00FF00FF00FF00FF00FF00FF00FF00FF00FF00FF00FF00FF00FF00FF00FF00FF",
INIT_3D => x"00FF00FF00FF00FF00FF00FF00FF00FF00FF00FF00FF00FF00FF00FF00FF00FF",
INIT_3E => x"00FF00FF00FF00FF00FF00FF00FF00FF00FF00FF00FF00FF00FF00FF00FF00FF",
INIT_3F => x"00FF00FF00FF00FF00FF00FF00FF00FF00FF00FF00FF00FF00FF00FF00FF00FF"
)
port map (
do => data_out,
dop(0) => dp,
addr => addr,
clk => clk,
di => data_in,
dip(0) => dp,
en => cs,
ssr => rst,
we => we
);
my_ram_2k : process ( rw )
begin
we <= not rw;
end process;
end architecture rtl;
| gpl-3.0 | 5c63c3519d712fa2cc0a2737fc98d31a | 0.702613 | 2.587015 | false | false | false | false |
jairov4/accel-oil | impl/impl_test_pcie/hdl/system_pcie_bridge_wrapper.vhd | 1 | 14,632 | -------------------------------------------------------------------------------
-- system_pcie_bridge_wrapper.vhd
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
library plbv46_pcie_v4_07_a;
use plbv46_pcie_v4_07_a.all;
entity system_pcie_bridge_wrapper is
port (
MPLB_Clk : in std_logic;
MPLB_Rst : in std_logic;
PLB_MTimeout : in std_logic;
PLB_MIRQ : in std_logic;
PLB_MAddrAck : in std_logic;
PLB_MSSize : in std_logic_vector(0 to 1);
PLB_MRearbitrate : in std_logic;
PLB_MBusy : in std_logic;
PLB_MRdErr : in std_logic;
PLB_MWrErr : in std_logic;
PLB_MWrDAck : in std_logic;
PLB_MRdDBus : in std_logic_vector(0 to 63);
PLB_MRdWdAddr : in std_logic_vector(0 to 3);
PLB_MRdDAck : in std_logic;
PLB_MRdBTerm : in std_logic;
PLB_MWrBTerm : in std_logic;
M_request : out std_logic;
M_priority : out std_logic_vector(0 to 1);
M_buslock : out std_logic;
M_RNW : out std_logic;
M_BE : out std_logic_vector(0 to 7);
M_MSize : out std_logic_vector(0 to 1);
M_size : out std_logic_vector(0 to 3);
M_type : out std_logic_vector(0 to 2);
M_lockErr : out std_logic;
M_abort : out std_logic;
M_TAttribute : out std_logic_vector(0 to 15);
M_UABus : out std_logic_vector(0 to 31);
M_ABus : out std_logic_vector(0 to 31);
M_wrDBus : out std_logic_vector(0 to 63);
M_wrBurst : out std_logic;
M_rdBurst : out std_logic;
SPLB_Clk : in std_logic;
SPLB_Rst : in std_logic;
PLB_ABus : in std_logic_vector(0 to 31);
PLB_UABus : in std_logic_vector(0 to 31);
PLB_PAValid : in std_logic;
PLB_SAValid : in std_logic;
PLB_rdPrim : in std_logic;
PLB_wrPrim : in std_logic;
PLB_masterID : in std_logic_vector(0 to 2);
PLB_abort : in std_logic;
PLB_busLock : in std_logic;
PLB_RNW : in std_logic;
PLB_BE : in std_logic_vector(0 to 7);
PLB_MSize : in std_logic_vector(0 to 1);
PLB_size : in std_logic_vector(0 to 3);
PLB_type : in std_logic_vector(0 to 2);
PLB_lockErr : in std_logic;
PLB_wrDBus : in std_logic_vector(0 to 63);
PLB_wrBurst : in std_logic;
PLB_rdBurst : in std_logic;
PLB_wrPendReq : in std_logic;
PLB_rdPendReq : in std_logic;
PLB_wrPendPri : in std_logic_vector(0 to 1);
PLB_rdPendPri : in std_logic_vector(0 to 1);
PLB_reqPri : in std_logic_vector(0 to 1);
PLB_TAttribute : in std_logic_vector(0 to 15);
Sl_addrAck : out std_logic;
Sl_SSize : out std_logic_vector(0 to 1);
Sl_wait : out std_logic;
Sl_rearbitrate : out std_logic;
Sl_wrDAck : out std_logic;
Sl_wrComp : out std_logic;
Sl_wrBTerm : out std_logic;
Sl_rdDBus : out std_logic_vector(0 to 63);
Sl_rdWdAddr : out std_logic_vector(0 to 3);
Sl_rdDAck : out std_logic;
Sl_rdComp : out std_logic;
Sl_rdBTerm : out std_logic;
Sl_MBusy : out std_logic_vector(0 to 5);
Sl_MWrErr : out std_logic_vector(0 to 5);
Sl_MRdErr : out std_logic_vector(0 to 5);
Sl_MIRQ : out std_logic_vector(0 to 5);
REFCLK : in std_logic;
Bridge_Clk : out std_logic;
RXN : in std_logic_vector(0 to 0);
RXP : in std_logic_vector(0 to 0);
TXN : out std_logic_vector(0 to 0);
TXP : out std_logic_vector(0 to 0);
IP2INTC_Irpt : out std_logic;
MSI_request : in std_logic
);
attribute x_core_info : STRING;
attribute x_core_info of system_pcie_bridge_wrapper : entity is "plbv46_pcie_v4_07_a";
end system_pcie_bridge_wrapper;
architecture STRUCTURE of system_pcie_bridge_wrapper is
component plbv46_pcie is
generic (
C_FAMILY : STRING;
C_SUBFAMILY : STRING;
C_IPIFBAR_NUM : INTEGER;
C_INCLUDE_BAROFFSET_REG : INTEGER;
C_PCIBAR_NUM : INTEGER;
C_NO_OF_LANES : INTEGER;
C_DEVICE_ID : std_logic_vector;
C_VENDOR_ID : std_logic_vector;
C_CLASS_CODE : std_logic_vector;
C_REF_CLK_FREQ : integer;
C_REV_ID : std_logic_vector;
C_SUBSYSTEM_ID : std_logic_vector;
C_SUBSYSTEM_VENDOR_ID : std_logic_vector;
C_COMP_TIMEOUT : INTEGER;
C_INCLUDE_RC : INTEGER;
C_MPLB_AWIDTH : INTEGER;
C_MPLB_DWIDTH : INTEGER;
C_MPLB_SMALLEST_SLAVE : INTEGER;
C_MPLB_NATIVE_DWIDTH : INTEGER;
C_SPLB_MID_WIDTH : INTEGER;
C_SPLB_NUM_MASTERS : INTEGER;
C_SPLB_SMALLEST_MASTER : INTEGER;
C_SPLB_AWIDTH : INTEGER;
C_BASEADDR : std_logic_vector;
C_HIGHADDR : std_logic_vector;
C_SPLB_DWIDTH : INTEGER;
C_SPLB_NATIVE_DWIDTH : INTEGER;
C_IPIFBAR_0 : std_logic_vector;
C_IPIFBAR_1 : std_logic_vector;
C_IPIFBAR_2 : std_logic_vector;
C_IPIFBAR_3 : std_logic_vector;
C_IPIFBAR_4 : std_logic_vector;
C_IPIFBAR_5 : std_logic_vector;
C_IPIFBAR_HIGHADDR_0 : std_logic_vector;
C_IPIFBAR_HIGHADDR_1 : std_logic_vector;
C_IPIFBAR_HIGHADDR_2 : std_logic_vector;
C_IPIFBAR_HIGHADDR_3 : std_logic_vector;
C_IPIFBAR_HIGHADDR_4 : std_logic_vector;
C_IPIFBAR_HIGHADDR_5 : std_logic_vector;
C_IPIFBAR2PCIBAR_0 : std_logic_vector;
C_IPIFBAR2PCIBAR_1 : std_logic_vector;
C_IPIFBAR2PCIBAR_2 : std_logic_vector;
C_IPIFBAR2PCIBAR_3 : std_logic_vector;
C_IPIFBAR2PCIBAR_4 : std_logic_vector;
C_IPIFBAR2PCIBAR_5 : std_logic_vector;
C_IPIFBAR_AS_0 : INTEGER;
C_IPIFBAR_AS_1 : INTEGER;
C_IPIFBAR_AS_2 : INTEGER;
C_IPIFBAR_AS_3 : INTEGER;
C_IPIFBAR_AS_4 : INTEGER;
C_IPIFBAR_AS_5 : INTEGER;
C_IPIFBAR_SPACE_TYPE_0 : INTEGER;
C_IPIFBAR_SPACE_TYPE_1 : INTEGER;
C_IPIFBAR_SPACE_TYPE_2 : INTEGER;
C_IPIFBAR_SPACE_TYPE_3 : INTEGER;
C_IPIFBAR_SPACE_TYPE_4 : INTEGER;
C_IPIFBAR_SPACE_TYPE_5 : INTEGER;
C_ECAM_BASEADDR : std_logic_vector;
C_ECAM_HIGHADDR : std_logic_vector;
C_PCIBAR2IPIFBAR_0 : std_logic_vector;
C_PCIBAR2IPIFBAR_1 : std_logic_vector;
C_PCIBAR2IPIFBAR_2 : std_logic_vector;
C_PCIBAR_LEN_0 : INTEGER;
C_PCIBAR_LEN_1 : INTEGER;
C_PCIBAR_LEN_2 : INTEGER;
C_PCIBAR_AS : INTEGER;
C_PCIE_CAP_SLOT_IMPLEMENTED : INTEGER
);
port (
MPLB_Clk : in std_logic;
MPLB_Rst : in std_logic;
PLB_MTimeout : in std_logic;
PLB_MIRQ : in std_logic;
PLB_MAddrAck : in std_logic;
PLB_MSSize : in std_logic_vector(0 to 1);
PLB_MRearbitrate : in std_logic;
PLB_MBusy : in std_logic;
PLB_MRdErr : in std_logic;
PLB_MWrErr : in std_logic;
PLB_MWrDAck : in std_logic;
PLB_MRdDBus : in std_logic_vector(0 to (C_MPLB_DWIDTH-1));
PLB_MRdWdAddr : in std_logic_vector(0 to 3);
PLB_MRdDAck : in std_logic;
PLB_MRdBTerm : in std_logic;
PLB_MWrBTerm : in std_logic;
M_request : out std_logic;
M_priority : out std_logic_vector(0 to 1);
M_buslock : out std_logic;
M_RNW : out std_logic;
M_BE : out std_logic_vector(0 to ((C_MPLB_DWIDTH/8)-1));
M_MSize : out std_logic_vector(0 to 1);
M_size : out std_logic_vector(0 to 3);
M_type : out std_logic_vector(0 to 2);
M_lockErr : out std_logic;
M_abort : out std_logic;
M_TAttribute : out std_logic_vector(0 to 15);
M_UABus : out std_logic_vector(0 to 31);
M_ABus : out std_logic_vector(0 to (C_MPLB_AWIDTH-1));
M_wrDBus : out std_logic_vector(0 to (C_MPLB_DWIDTH-1));
M_wrBurst : out std_logic;
M_rdBurst : out std_logic;
SPLB_Clk : in std_logic;
SPLB_Rst : in std_logic;
PLB_ABus : in std_logic_vector(0 to 31);
PLB_UABus : in std_logic_vector(0 to 31);
PLB_PAValid : in std_logic;
PLB_SAValid : in std_logic;
PLB_rdPrim : in std_logic;
PLB_wrPrim : in std_logic;
PLB_masterID : in std_logic_vector(0 to (C_SPLB_MID_WIDTH-1));
PLB_abort : in std_logic;
PLB_busLock : in std_logic;
PLB_RNW : in std_logic;
PLB_BE : in std_logic_vector(0 to ((C_SPLB_DWIDTH/8)-1));
PLB_MSize : in std_logic_vector(0 to 1);
PLB_size : in std_logic_vector(0 to 3);
PLB_type : in std_logic_vector(0 to 2);
PLB_lockErr : in std_logic;
PLB_wrDBus : in std_logic_vector(0 to (C_SPLB_DWIDTH-1));
PLB_wrBurst : in std_logic;
PLB_rdBurst : in std_logic;
PLB_wrPendReq : in std_logic;
PLB_rdPendReq : in std_logic;
PLB_wrPendPri : in std_logic_vector(0 to 1);
PLB_rdPendPri : in std_logic_vector(0 to 1);
PLB_reqPri : in std_logic_vector(0 to 1);
PLB_TAttribute : in std_logic_vector(0 to 15);
Sl_addrAck : out std_logic;
Sl_SSize : out std_logic_vector(0 to 1);
Sl_wait : out std_logic;
Sl_rearbitrate : out std_logic;
Sl_wrDAck : out std_logic;
Sl_wrComp : out std_logic;
Sl_wrBTerm : out std_logic;
Sl_rdDBus : out std_logic_vector(0 to (C_SPLB_DWIDTH-1));
Sl_rdWdAddr : out std_logic_vector(0 to 3);
Sl_rdDAck : out std_logic;
Sl_rdComp : out std_logic;
Sl_rdBTerm : out std_logic;
Sl_MBusy : out std_logic_vector(0 to (C_SPLB_NUM_MASTERS-1));
Sl_MWrErr : out std_logic_vector(0 to (C_SPLB_NUM_MASTERS-1));
Sl_MRdErr : out std_logic_vector(0 to (C_SPLB_NUM_MASTERS-1));
Sl_MIRQ : out std_logic_vector(0 to (C_SPLB_NUM_MASTERS-1));
REFCLK : in std_logic;
Bridge_Clk : out std_logic;
RXN : in std_logic_vector((C_NO_OF_LANES-1) to 0);
RXP : in std_logic_vector((C_NO_OF_LANES-1) to 0);
TXN : out std_logic_vector((C_NO_OF_LANES-1) to 0);
TXP : out std_logic_vector((C_NO_OF_LANES-1) to 0);
IP2INTC_Irpt : out std_logic;
MSI_request : in std_logic
);
end component;
begin
PCIe_Bridge : plbv46_pcie
generic map (
C_FAMILY => "virtex5",
C_SUBFAMILY => "lx",
C_IPIFBAR_NUM => 2,
C_INCLUDE_BAROFFSET_REG => 0,
C_PCIBAR_NUM => 1,
C_NO_OF_LANES => 1,
C_DEVICE_ID => X"0505",
C_VENDOR_ID => X"10EE",
C_CLASS_CODE => X"058000",
C_REF_CLK_FREQ => 0,
C_REV_ID => X"00",
C_SUBSYSTEM_ID => X"0000",
C_SUBSYSTEM_VENDOR_ID => X"0000",
C_COMP_TIMEOUT => 1,
C_INCLUDE_RC => 0,
C_MPLB_AWIDTH => 32,
C_MPLB_DWIDTH => 64,
C_MPLB_SMALLEST_SLAVE => 32,
C_MPLB_NATIVE_DWIDTH => 64,
C_SPLB_MID_WIDTH => 3,
C_SPLB_NUM_MASTERS => 6,
C_SPLB_SMALLEST_MASTER => 32,
C_SPLB_AWIDTH => 32,
C_BASEADDR => X"85c00000",
C_HIGHADDR => X"85c0ffff",
C_SPLB_DWIDTH => 64,
C_SPLB_NATIVE_DWIDTH => 64,
C_IPIFBAR_0 => X"E0000000",
C_IPIFBAR_1 => X"b0000000",
C_IPIFBAR_2 => X"FFFFFFFF",
C_IPIFBAR_3 => X"FFFFFFFF",
C_IPIFBAR_4 => X"FFFFFFFF",
C_IPIFBAR_5 => X"FFFFFFFF",
C_IPIFBAR_HIGHADDR_0 => X"FFFFFFFF",
C_IPIFBAR_HIGHADDR_1 => X"bfffffff",
C_IPIFBAR_HIGHADDR_2 => X"00000000",
C_IPIFBAR_HIGHADDR_3 => X"00000000",
C_IPIFBAR_HIGHADDR_4 => X"00000000",
C_IPIFBAR_HIGHADDR_5 => X"00000000",
C_IPIFBAR2PCIBAR_0 => X"00000000",
C_IPIFBAR2PCIBAR_1 => X"00000000",
C_IPIFBAR2PCIBAR_2 => X"FFFFFFFF",
C_IPIFBAR2PCIBAR_3 => X"FFFFFFFF",
C_IPIFBAR2PCIBAR_4 => X"FFFFFFFF",
C_IPIFBAR2PCIBAR_5 => X"FFFFFFFF",
C_IPIFBAR_AS_0 => 0,
C_IPIFBAR_AS_1 => 0,
C_IPIFBAR_AS_2 => 0,
C_IPIFBAR_AS_3 => 0,
C_IPIFBAR_AS_4 => 0,
C_IPIFBAR_AS_5 => 0,
C_IPIFBAR_SPACE_TYPE_0 => 1,
C_IPIFBAR_SPACE_TYPE_1 => 1,
C_IPIFBAR_SPACE_TYPE_2 => 1,
C_IPIFBAR_SPACE_TYPE_3 => 1,
C_IPIFBAR_SPACE_TYPE_4 => 1,
C_IPIFBAR_SPACE_TYPE_5 => 1,
C_ECAM_BASEADDR => X"FFFFFFFF",
C_ECAM_HIGHADDR => X"00000000",
C_PCIBAR2IPIFBAR_0 => X"c0000000",
C_PCIBAR2IPIFBAR_1 => X"00000000",
C_PCIBAR2IPIFBAR_2 => X"FFFFFFFF",
C_PCIBAR_LEN_0 => 28,
C_PCIBAR_LEN_1 => 28,
C_PCIBAR_LEN_2 => 16,
C_PCIBAR_AS => 1,
C_PCIE_CAP_SLOT_IMPLEMENTED => 1
)
port map (
MPLB_Clk => MPLB_Clk,
MPLB_Rst => MPLB_Rst,
PLB_MTimeout => PLB_MTimeout,
PLB_MIRQ => PLB_MIRQ,
PLB_MAddrAck => PLB_MAddrAck,
PLB_MSSize => PLB_MSSize,
PLB_MRearbitrate => PLB_MRearbitrate,
PLB_MBusy => PLB_MBusy,
PLB_MRdErr => PLB_MRdErr,
PLB_MWrErr => PLB_MWrErr,
PLB_MWrDAck => PLB_MWrDAck,
PLB_MRdDBus => PLB_MRdDBus,
PLB_MRdWdAddr => PLB_MRdWdAddr,
PLB_MRdDAck => PLB_MRdDAck,
PLB_MRdBTerm => PLB_MRdBTerm,
PLB_MWrBTerm => PLB_MWrBTerm,
M_request => M_request,
M_priority => M_priority,
M_buslock => M_buslock,
M_RNW => M_RNW,
M_BE => M_BE,
M_MSize => M_MSize,
M_size => M_size,
M_type => M_type,
M_lockErr => M_lockErr,
M_abort => M_abort,
M_TAttribute => M_TAttribute,
M_UABus => M_UABus,
M_ABus => M_ABus,
M_wrDBus => M_wrDBus,
M_wrBurst => M_wrBurst,
M_rdBurst => M_rdBurst,
SPLB_Clk => SPLB_Clk,
SPLB_Rst => SPLB_Rst,
PLB_ABus => PLB_ABus,
PLB_UABus => PLB_UABus,
PLB_PAValid => PLB_PAValid,
PLB_SAValid => PLB_SAValid,
PLB_rdPrim => PLB_rdPrim,
PLB_wrPrim => PLB_wrPrim,
PLB_masterID => PLB_masterID,
PLB_abort => PLB_abort,
PLB_busLock => PLB_busLock,
PLB_RNW => PLB_RNW,
PLB_BE => PLB_BE,
PLB_MSize => PLB_MSize,
PLB_size => PLB_size,
PLB_type => PLB_type,
PLB_lockErr => PLB_lockErr,
PLB_wrDBus => PLB_wrDBus,
PLB_wrBurst => PLB_wrBurst,
PLB_rdBurst => PLB_rdBurst,
PLB_wrPendReq => PLB_wrPendReq,
PLB_rdPendReq => PLB_rdPendReq,
PLB_wrPendPri => PLB_wrPendPri,
PLB_rdPendPri => PLB_rdPendPri,
PLB_reqPri => PLB_reqPri,
PLB_TAttribute => PLB_TAttribute,
Sl_addrAck => Sl_addrAck,
Sl_SSize => Sl_SSize,
Sl_wait => Sl_wait,
Sl_rearbitrate => Sl_rearbitrate,
Sl_wrDAck => Sl_wrDAck,
Sl_wrComp => Sl_wrComp,
Sl_wrBTerm => Sl_wrBTerm,
Sl_rdDBus => Sl_rdDBus,
Sl_rdWdAddr => Sl_rdWdAddr,
Sl_rdDAck => Sl_rdDAck,
Sl_rdComp => Sl_rdComp,
Sl_rdBTerm => Sl_rdBTerm,
Sl_MBusy => Sl_MBusy,
Sl_MWrErr => Sl_MWrErr,
Sl_MRdErr => Sl_MRdErr,
Sl_MIRQ => Sl_MIRQ,
REFCLK => REFCLK,
Bridge_Clk => Bridge_Clk,
RXN => RXN,
RXP => RXP,
TXN => TXN,
TXP => TXP,
IP2INTC_Irpt => IP2INTC_Irpt,
MSI_request => MSI_request
);
end architecture STRUCTURE;
| lgpl-3.0 | a46ed1c7e27e9557ca3f8c732a8783af | 0.585634 | 3.052149 | false | false | false | false |
grwlf/vsim | vhdl_ct/ct00023.vhd | 1 | 4,613 | -- NEED RESULT: ARCH00023: Unassociated composite ports with globally static subtype take on default expression passed
-------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
-------------------------------------------------------------------------------
--
-- TEST NAME:
--
-- CT00023
--
-- AUTHOR:
--
-- A. Wilmot
--
-- TEST OBJECTIVES:
--
-- 1.1.1.2 (2)
--
-- DESIGN UNIT ORDERING:
--
-- GENERIC_STANDARD_TYPES(ARCH00023)
-- ENT00023_Test_Bench(ARCH00023_Test_Bench)
--
-- REVISION HISTORY:
--
-- 26-JUN-1987 - initial revision
--
-- NOTES:
--
-- self-checking
-- automatically generated
--
use WORK.STANDARD_TYPES.all ;
architecture ARCH00023 of GENERIC_STANDARD_TYPES is
begin
L1 :
block
port (
i_bit_vector_1, i_bit_vector_2 : bit_vector
:= c_st_bit_vector_1 ;
i_string_1, i_string_2 : string
:= c_st_string_1 ;
i_t_rec1_1, i_t_rec1_2 : t_rec1
:= c_st_rec1_1 ;
i_st_rec1_1, i_st_rec1_2 : st_rec1
:= c_st_rec1_1 ;
i_t_rec2_1, i_t_rec2_2 : t_rec2
:= c_st_rec2_1 ;
i_st_rec2_1, i_st_rec2_2 : st_rec2
:= c_st_rec2_1 ;
i_t_rec3_1, i_t_rec3_2 : t_rec3
:= c_st_rec3_1 ;
i_st_rec3_1, i_st_rec3_2 : st_rec3
:= c_st_rec3_1 ;
i_t_arr1_1, i_t_arr1_2 : t_arr1
:= c_st_arr1_1 ;
i_st_arr1_1, i_st_arr1_2 : st_arr1
:= c_st_arr1_1 ;
i_t_arr2_1, i_t_arr2_2 : t_arr2
:= c_st_arr2_1 ;
i_st_arr2_1, i_st_arr2_2 : st_arr2
:= c_st_arr2_1 ;
i_t_arr3_1, i_t_arr3_2 : t_arr3
:= c_st_arr3_1 ;
i_st_arr3_1, i_st_arr3_2 : st_arr3
:= c_st_arr3_1
) ;
port map (
open, open,
open, open,
open, open,
open, open,
open, open,
open, open,
open, open,
open, open,
open, open,
open, open,
open, open,
open, open,
open, open,
open, open
) ;
begin
process
variable correct : boolean := true ;
begin
correct := correct and i_bit_vector_1 = c_st_bit_vector_1
and i_bit_vector_2 = c_st_bit_vector_1 ;
correct := correct and i_string_1 = c_st_string_1
and i_string_2 = c_st_string_1 ;
correct := correct and i_t_rec1_1 = c_st_rec1_1
and i_t_rec1_2 = c_st_rec1_1 ;
correct := correct and i_st_rec1_1 = c_st_rec1_1
and i_st_rec1_2 = c_st_rec1_1 ;
correct := correct and i_t_rec2_1 = c_st_rec2_1
and i_t_rec2_2 = c_st_rec2_1 ;
correct := correct and i_st_rec2_1 = c_st_rec2_1
and i_st_rec2_2 = c_st_rec2_1 ;
correct := correct and i_t_rec3_1 = c_st_rec3_1
and i_t_rec3_2 = c_st_rec3_1 ;
correct := correct and i_st_rec3_1 = c_st_rec3_1
and i_st_rec3_2 = c_st_rec3_1 ;
correct := correct and i_t_arr1_1 = c_st_arr1_1
and i_t_arr1_2 = c_st_arr1_1 ;
correct := correct and i_st_arr1_1 = c_st_arr1_1
and i_st_arr1_2 = c_st_arr1_1 ;
correct := correct and i_t_arr2_1 = c_st_arr2_1
and i_t_arr2_2 = c_st_arr2_1 ;
correct := correct and i_st_arr2_1 = c_st_arr2_1
and i_st_arr2_2 = c_st_arr2_1 ;
correct := correct and i_t_arr3_1 = c_st_arr3_1
and i_t_arr3_2 = c_st_arr3_1 ;
correct := correct and i_st_arr3_1 = c_st_arr3_1
and i_st_arr3_2 = c_st_arr3_1 ;
test_report ( "ARCH00023" ,
"Unassociated composite ports with globally static subtype"
& " take on default expression" ,
correct) ;
wait ;
end process ;
end block L1 ;
end ARCH00023 ;
--
entity ENT00023_Test_Bench is
end ENT00023_Test_Bench ;
--
architecture ARCH00023_Test_Bench of ENT00023_Test_Bench is
begin
L1:
block
component UUT
end component ;
for CIS1 : UUT use entity WORK.GENERIC_STANDARD_TYPES ( ARCH00023 ) ;
begin
CIS1 : UUT ;
end block L1 ;
end ARCH00023_Test_Bench ;
| gpl-3.0 | 178ea1e23df7471029e01d087b4087a4 | 0.45892 | 2.983829 | false | true | false | false |
jairov4/accel-oil | impl/impl_test_single/simulation/behavioral/system_proc_sys_reset_0_wrapper.vhd | 2 | 4,081 | -------------------------------------------------------------------------------
-- system_proc_sys_reset_0_wrapper.vhd
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
library proc_sys_reset_v3_00_a;
use proc_sys_reset_v3_00_a.all;
entity system_proc_sys_reset_0_wrapper is
port (
Slowest_sync_clk : in std_logic;
Ext_Reset_In : in std_logic;
Aux_Reset_In : in std_logic;
MB_Debug_Sys_Rst : in std_logic;
Core_Reset_Req_0 : in std_logic;
Chip_Reset_Req_0 : in std_logic;
System_Reset_Req_0 : in std_logic;
Core_Reset_Req_1 : in std_logic;
Chip_Reset_Req_1 : in std_logic;
System_Reset_Req_1 : in std_logic;
Dcm_locked : in std_logic;
RstcPPCresetcore_0 : out std_logic;
RstcPPCresetchip_0 : out std_logic;
RstcPPCresetsys_0 : out std_logic;
RstcPPCresetcore_1 : out std_logic;
RstcPPCresetchip_1 : out std_logic;
RstcPPCresetsys_1 : out std_logic;
MB_Reset : out std_logic;
Bus_Struct_Reset : out std_logic_vector(0 to 0);
Peripheral_Reset : out std_logic_vector(0 to 0);
Interconnect_aresetn : out std_logic_vector(0 to 0);
Peripheral_aresetn : out std_logic_vector(0 to 0)
);
end system_proc_sys_reset_0_wrapper;
architecture STRUCTURE of system_proc_sys_reset_0_wrapper is
component proc_sys_reset is
generic (
C_EXT_RST_WIDTH : integer;
C_AUX_RST_WIDTH : integer;
C_EXT_RESET_HIGH : std_logic;
C_AUX_RESET_HIGH : std_logic;
C_NUM_BUS_RST : integer;
C_NUM_PERP_RST : integer;
C_NUM_INTERCONNECT_ARESETN : integer;
C_NUM_PERP_ARESETN : integer
);
port (
Slowest_sync_clk : in std_logic;
Ext_Reset_In : in std_logic;
Aux_Reset_In : in std_logic;
MB_Debug_Sys_Rst : in std_logic;
Core_Reset_Req_0 : in std_logic;
Chip_Reset_Req_0 : in std_logic;
System_Reset_Req_0 : in std_logic;
Core_Reset_Req_1 : in std_logic;
Chip_Reset_Req_1 : in std_logic;
System_Reset_Req_1 : in std_logic;
Dcm_locked : in std_logic;
RstcPPCresetcore_0 : out std_logic;
RstcPPCresetchip_0 : out std_logic;
RstcPPCresetsys_0 : out std_logic;
RstcPPCresetcore_1 : out std_logic;
RstcPPCresetchip_1 : out std_logic;
RstcPPCresetsys_1 : out std_logic;
MB_Reset : out std_logic;
Bus_Struct_Reset : out std_logic_vector(0 to C_NUM_BUS_RST-1);
Peripheral_Reset : out std_logic_vector(0 to C_NUM_PERP_RST-1);
Interconnect_aresetn : out std_logic_vector(0 to C_NUM_INTERCONNECT_ARESETN-1);
Peripheral_aresetn : out std_logic_vector(0 to C_NUM_PERP_ARESETN-1)
);
end component;
begin
proc_sys_reset_0 : proc_sys_reset
generic map (
C_EXT_RST_WIDTH => 4,
C_AUX_RST_WIDTH => 4,
C_EXT_RESET_HIGH => '0',
C_AUX_RESET_HIGH => '1',
C_NUM_BUS_RST => 1,
C_NUM_PERP_RST => 1,
C_NUM_INTERCONNECT_ARESETN => 1,
C_NUM_PERP_ARESETN => 1
)
port map (
Slowest_sync_clk => Slowest_sync_clk,
Ext_Reset_In => Ext_Reset_In,
Aux_Reset_In => Aux_Reset_In,
MB_Debug_Sys_Rst => MB_Debug_Sys_Rst,
Core_Reset_Req_0 => Core_Reset_Req_0,
Chip_Reset_Req_0 => Chip_Reset_Req_0,
System_Reset_Req_0 => System_Reset_Req_0,
Core_Reset_Req_1 => Core_Reset_Req_1,
Chip_Reset_Req_1 => Chip_Reset_Req_1,
System_Reset_Req_1 => System_Reset_Req_1,
Dcm_locked => Dcm_locked,
RstcPPCresetcore_0 => RstcPPCresetcore_0,
RstcPPCresetchip_0 => RstcPPCresetchip_0,
RstcPPCresetsys_0 => RstcPPCresetsys_0,
RstcPPCresetcore_1 => RstcPPCresetcore_1,
RstcPPCresetchip_1 => RstcPPCresetchip_1,
RstcPPCresetsys_1 => RstcPPCresetsys_1,
MB_Reset => MB_Reset,
Bus_Struct_Reset => Bus_Struct_Reset,
Peripheral_Reset => Peripheral_Reset,
Interconnect_aresetn => Interconnect_aresetn,
Peripheral_aresetn => Peripheral_aresetn
);
end architecture STRUCTURE;
| lgpl-3.0 | 13614512fedfbd55091826d44875066c | 0.61382 | 3.317886 | false | false | false | false |
Given-Jiang/Binarization | tb_Binarization/hdl/Binarization_GN_Binarization_Binarization_Module.vhd | 2 | 30,670 | -- Binarization_GN_Binarization_Binarization_Module.vhd
-- Generated using ACDS version 13.1 162 at 2015.02.12.09:18:23
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity Binarization_GN_Binarization_Binarization_Module is
port (
sop : in std_logic := '0'; -- sop.wire
writedata : in std_logic_vector(31 downto 0) := (others => '0'); -- writedata.wire
eop : in std_logic := '0'; -- eop.wire
addr : in std_logic_vector(1 downto 0) := (others => '0'); -- addr.wire
write : in std_logic := '0'; -- write.wire
Clock : in std_logic := '0'; -- Clock.clk
aclr : in std_logic := '0'; -- .reset
data_out : out std_logic_vector(23 downto 0); -- data_out.wire
data_in : in std_logic_vector(23 downto 0) := (others => '0') -- data_in.wire
);
end entity Binarization_GN_Binarization_Binarization_Module;
architecture rtl of Binarization_GN_Binarization_Binarization_Module is
component alt_dspbuilder_clock_GNQFU4PUDH is
port (
aclr : in std_logic := 'X'; -- reset
aclr_n : in std_logic := 'X'; -- reset_n
aclr_out : out std_logic; -- reset
clock : in std_logic := 'X'; -- clk
clock_out : out std_logic -- clk
);
end component alt_dspbuilder_clock_GNQFU4PUDH;
component alt_dspbuilder_cast_GNKXX25S2S is
generic (
round : natural := 0;
saturate : natural := 0
);
port (
input : in std_logic_vector(23 downto 0) := (others => 'X'); -- wire
output : out std_logic_vector(7 downto 0) -- wire
);
end component alt_dspbuilder_cast_GNKXX25S2S;
component alt_dspbuilder_port_GNEPKLLZKY is
port (
input : in std_logic_vector(31 downto 0) := (others => 'X'); -- wire
output : out std_logic_vector(31 downto 0) -- wire
);
end component alt_dspbuilder_port_GNEPKLLZKY;
component alt_dspbuilder_multiplexer_GNCALBUTDR is
generic (
HDLTYPE : string := "STD_LOGIC_VECTOR";
use_one_hot_select_bus : natural := 0;
width : positive := 8;
pipeline : natural := 0;
number_inputs : natural := 4
);
port (
clock : in std_logic := 'X'; -- clk
aclr : in std_logic := 'X'; -- reset
sel : in std_logic_vector(0 downto 0) := (others => 'X'); -- wire
result : out std_logic_vector(23 downto 0); -- wire
ena : in std_logic := 'X'; -- wire
user_aclr : in std_logic := 'X'; -- wire
in0 : in std_logic_vector(23 downto 0) := (others => 'X'); -- wire
in1 : in std_logic_vector(23 downto 0) := (others => 'X') -- wire
);
end component alt_dspbuilder_multiplexer_GNCALBUTDR;
component alt_dspbuilder_gnd_GN is
port (
output : out std_logic -- wire
);
end component alt_dspbuilder_gnd_GN;
component alt_dspbuilder_vcc_GN is
port (
output : out std_logic -- wire
);
end component alt_dspbuilder_vcc_GN;
component alt_dspbuilder_constant_GNZEH3JAKA is
generic (
HDLTYPE : string := "STD_LOGIC_VECTOR";
BitPattern : string := "0000";
width : natural := 4
);
port (
output : out std_logic_vector(23 downto 0) -- wire
);
end component alt_dspbuilder_constant_GNZEH3JAKA;
component alt_dspbuilder_port_GN6TDLHAW6 is
port (
input : in std_logic_vector(1 downto 0) := (others => 'X'); -- wire
output : out std_logic_vector(1 downto 0) -- wire
);
end component alt_dspbuilder_port_GN6TDLHAW6;
component alt_dspbuilder_constant_GNNKZSYI73 is
generic (
HDLTYPE : string := "STD_LOGIC_VECTOR";
BitPattern : string := "0000";
width : natural := 4
);
port (
output : out std_logic_vector(23 downto 0) -- wire
);
end component alt_dspbuilder_constant_GNNKZSYI73;
component alt_dspbuilder_constant_GNLMV7GZFA is
generic (
HDLTYPE : string := "STD_LOGIC_VECTOR";
BitPattern : string := "0000";
width : natural := 4
);
port (
output : out std_logic_vector(23 downto 0) -- wire
);
end component alt_dspbuilder_constant_GNLMV7GZFA;
component alt_dspbuilder_if_statement_GNYT6HZJI5 is
generic (
use_else_output : natural := 0;
bwr : natural := 0;
use_else_input : natural := 0;
signed : natural := 1;
HDLTYPE : string := "STD_LOGIC_VECTOR";
if_expression : string := "a";
number_inputs : integer := 1;
width : natural := 8
);
port (
true : out std_logic; -- wire
a : in std_logic_vector(7 downto 0) := (others => 'X'); -- wire
b : in std_logic_vector(7 downto 0) := (others => 'X') -- wire
);
end component alt_dspbuilder_if_statement_GNYT6HZJI5;
component alt_dspbuilder_delay_GNUECIBFDH is
generic (
ClockPhase : string := "1";
delay : positive := 1;
use_init : natural := 0;
BitPattern : string := "00000001";
width : positive := 8
);
port (
aclr : in std_logic := 'X'; -- clk
clock : in std_logic := 'X'; -- clk
ena : in std_logic := 'X'; -- wire
input : in std_logic_vector(width-1 downto 0) := (others => 'X'); -- wire
output : out std_logic_vector(width-1 downto 0); -- wire
sclr : in std_logic := 'X' -- wire
);
end component alt_dspbuilder_delay_GNUECIBFDH;
component alt_dspbuilder_port_GN37ALZBS4 is
port (
input : in std_logic := 'X'; -- wire
output : out std_logic -- wire
);
end component alt_dspbuilder_port_GN37ALZBS4;
component alt_dspbuilder_logical_bit_op_GNA5ZFEL7V is
generic (
LogicalOp : string := "AltAND";
number_inputs : positive := 2
);
port (
result : out std_logic; -- wire
data0 : in std_logic := 'X'; -- wire
data1 : in std_logic := 'X' -- wire
);
end component alt_dspbuilder_logical_bit_op_GNA5ZFEL7V;
component alt_dspbuilder_decoder_GNSCEXJCJK is
generic (
decode : string := "00000000";
pipeline : natural := 0;
width : natural := 8
);
port (
aclr : in std_logic := 'X'; -- clk
clock : in std_logic := 'X'; -- clk
data : in std_logic_vector(width-1 downto 0) := (others => 'X'); -- wire
dec : out std_logic; -- wire
ena : in std_logic := 'X'; -- wire
sclr : in std_logic := 'X' -- wire
);
end component alt_dspbuilder_decoder_GNSCEXJCJK;
component alt_dspbuilder_delay_GNVTJPHWYT is
generic (
ClockPhase : string := "1";
delay : positive := 1;
use_init : natural := 0;
BitPattern : string := "00000001";
width : positive := 8
);
port (
aclr : in std_logic := 'X'; -- clk
clock : in std_logic := 'X'; -- clk
ena : in std_logic := 'X'; -- wire
input : in std_logic_vector(width-1 downto 0) := (others => 'X'); -- wire
output : out std_logic_vector(width-1 downto 0); -- wire
sclr : in std_logic := 'X' -- wire
);
end component alt_dspbuilder_delay_GNVTJPHWYT;
component alt_dspbuilder_if_statement_GN7VA7SRUP is
generic (
use_else_output : natural := 0;
bwr : natural := 0;
use_else_input : natural := 0;
signed : natural := 1;
HDLTYPE : string := "STD_LOGIC_VECTOR";
if_expression : string := "a";
number_inputs : integer := 1;
width : natural := 8
);
port (
true : out std_logic; -- wire
a : in std_logic_vector(23 downto 0) := (others => 'X'); -- wire
b : in std_logic_vector(23 downto 0) := (others => 'X'); -- wire
c : in std_logic_vector(23 downto 0) := (others => 'X') -- wire
);
end component alt_dspbuilder_if_statement_GN7VA7SRUP;
component alt_dspbuilder_delay_GNHYCSAEGT is
generic (
ClockPhase : string := "1";
delay : positive := 1;
use_init : natural := 0;
BitPattern : string := "00000001";
width : positive := 8
);
port (
aclr : in std_logic := 'X'; -- clk
clock : in std_logic := 'X'; -- clk
ena : in std_logic := 'X'; -- wire
input : in std_logic_vector(width-1 downto 0) := (others => 'X'); -- wire
output : out std_logic_vector(width-1 downto 0); -- wire
sclr : in std_logic := 'X' -- wire
);
end component alt_dspbuilder_delay_GNHYCSAEGT;
component alt_dspbuilder_port_GNOC3SGKQJ is
port (
input : in std_logic_vector(23 downto 0) := (others => 'X'); -- wire
output : out std_logic_vector(23 downto 0) -- wire
);
end component alt_dspbuilder_port_GNOC3SGKQJ;
component alt_dspbuilder_decoder_GNM4LOIHXZ is
generic (
decode : string := "00000000";
pipeline : natural := 0;
width : natural := 8
);
port (
aclr : in std_logic := 'X'; -- clk
clock : in std_logic := 'X'; -- clk
data : in std_logic_vector(width-1 downto 0) := (others => 'X'); -- wire
dec : out std_logic; -- wire
ena : in std_logic := 'X'; -- wire
sclr : in std_logic := 'X' -- wire
);
end component alt_dspbuilder_decoder_GNM4LOIHXZ;
component alt_dspbuilder_cast_GN7PRGDOVA is
generic (
round : natural := 0;
saturate : natural := 0
);
port (
input : in std_logic_vector(31 downto 0) := (others => 'X'); -- wire
output : out std_logic_vector(23 downto 0) -- wire
);
end component alt_dspbuilder_cast_GN7PRGDOVA;
component alt_dspbuilder_cast_GNSB3OXIQS is
generic (
round : natural := 0;
saturate : natural := 0
);
port (
input : in std_logic_vector(0 downto 0) := (others => 'X'); -- wire
output : out std_logic -- wire
);
end component alt_dspbuilder_cast_GNSB3OXIQS;
component alt_dspbuilder_cast_GN46N4UJ5S is
generic (
round : natural := 0;
saturate : natural := 0
);
port (
input : in std_logic := 'X'; -- wire
output : out std_logic_vector(0 downto 0) -- wire
);
end component alt_dspbuilder_cast_GN46N4UJ5S;
signal multiplexeruser_aclrgnd_output_wire : std_logic; -- Multiplexeruser_aclrGND:output -> Multiplexer:user_aclr
signal multiplexerenavcc_output_wire : std_logic; -- MultiplexerenaVCC:output -> Multiplexer:ena
signal decoder1sclrgnd_output_wire : std_logic; -- Decoder1sclrGND:output -> Decoder1:sclr
signal decoder1enavcc_output_wire : std_logic; -- Decoder1enaVCC:output -> Decoder1:ena
signal delay3sclrgnd_output_wire : std_logic; -- Delay3sclrGND:output -> Delay3:sclr
signal multiplexer1user_aclrgnd_output_wire : std_logic; -- Multiplexer1user_aclrGND:output -> Multiplexer1:user_aclr
signal multiplexer1enavcc_output_wire : std_logic; -- Multiplexer1enaVCC:output -> Multiplexer1:ena
signal delay1sclrgnd_output_wire : std_logic; -- Delay1sclrGND:output -> Delay1:sclr
signal delay1enavcc_output_wire : std_logic; -- Delay1enaVCC:output -> Delay1:ena
signal delay2sclrgnd_output_wire : std_logic; -- Delay2sclrGND:output -> Delay2:sclr
signal decodersclrgnd_output_wire : std_logic; -- DecodersclrGND:output -> Decoder:sclr
signal decoderenavcc_output_wire : std_logic; -- DecoderenaVCC:output -> Decoder:ena
signal addr_0_output_wire : std_logic_vector(1 downto 0); -- addr_0:output -> Decoder:data
signal bus_conversion1_output_wire : std_logic_vector(7 downto 0); -- Bus_Conversion1:output -> Delay2:input
signal delay2_output_wire : std_logic_vector(7 downto 0); -- Delay2:output -> Delay3:input
signal data_in_0_output_wire : std_logic_vector(23 downto 0); -- data_in_0:output -> [Bus_Conversion:input, Decoder1:data, If_Statement1:a, Multiplexer:in0]
signal bus_conversion_output_wire : std_logic_vector(7 downto 0); -- Bus_Conversion:output -> If_Statement:a
signal delay3_output_wire : std_logic_vector(7 downto 0); -- Delay3:output -> If_Statement:b
signal constant3_output_wire : std_logic_vector(23 downto 0); -- Constant3:output -> If_Statement1:b
signal constant4_output_wire : std_logic_vector(23 downto 0); -- Constant4:output -> If_Statement1:c
signal if_statement1_true_wire : std_logic; -- If_Statement1:true -> Logical_Bit_Operator:data0
signal sop_0_output_wire : std_logic; -- sop_0:output -> [Logical_Bit_Operator3:data0, Logical_Bit_Operator:data1]
signal logical_bit_operator_result_wire : std_logic; -- Logical_Bit_Operator:result -> [Delay:ena, cast2:input]
signal eop_0_output_wire : std_logic; -- eop_0:output -> Logical_Bit_Operator1:data0
signal decoder_dec_wire : std_logic; -- Decoder:dec -> Logical_Bit_Operator2:data0
signal write_0_output_wire : std_logic; -- write_0:output -> Logical_Bit_Operator2:data1
signal logical_bit_operator2_result_wire : std_logic; -- Logical_Bit_Operator2:result -> Delay2:ena
signal decoder1_dec_wire : std_logic; -- Decoder1:dec -> Logical_Bit_Operator3:data1
signal logical_bit_operator3_result_wire : std_logic; -- Logical_Bit_Operator3:result -> Delay3:ena
signal delay_output_wire : std_logic_vector(0 downto 0); -- Delay:output -> [Multiplexer:sel, cast3:input]
signal constant1_output_wire : std_logic_vector(23 downto 0); -- Constant1:output -> Multiplexer1:in0
signal constant2_output_wire : std_logic_vector(23 downto 0); -- Constant2:output -> Multiplexer1:in1
signal multiplexer1_result_wire : std_logic_vector(23 downto 0); -- Multiplexer1:result -> Multiplexer:in1
signal multiplexer_result_wire : std_logic_vector(23 downto 0); -- Multiplexer:result -> data_out_0:input
signal writedata_0_output_wire : std_logic_vector(31 downto 0); -- writedata_0:output -> cast0:input
signal cast0_output_wire : std_logic_vector(23 downto 0); -- cast0:output -> Bus_Conversion1:input
signal delay1_output_wire : std_logic_vector(0 downto 0); -- Delay1:output -> cast1:input
signal cast1_output_wire : std_logic; -- cast1:output -> Delay:sclr
signal cast2_output_wire : std_logic_vector(0 downto 0); -- cast2:output -> Delay:input
signal cast3_output_wire : std_logic; -- cast3:output -> Logical_Bit_Operator1:data1
signal logical_bit_operator1_result_wire : std_logic; -- Logical_Bit_Operator1:result -> cast4:input
signal cast4_output_wire : std_logic_vector(0 downto 0); -- cast4:output -> Delay1:input
signal if_statement_true_wire : std_logic; -- If_Statement:true -> cast5:input
signal cast5_output_wire : std_logic_vector(0 downto 0); -- cast5:output -> Multiplexer1:sel
signal clock_0_clock_output_reset : std_logic; -- Clock_0:aclr_out -> [Decoder1:aclr, Decoder:aclr, Delay1:aclr, Delay2:aclr, Delay3:aclr, Delay:aclr, Multiplexer1:aclr, Multiplexer:aclr]
signal clock_0_clock_output_clk : std_logic; -- Clock_0:clock_out -> [Decoder1:clock, Decoder:clock, Delay1:clock, Delay2:clock, Delay3:clock, Delay:clock, Multiplexer1:clock, Multiplexer:clock]
begin
clock_0 : component alt_dspbuilder_clock_GNQFU4PUDH
port map (
clock_out => clock_0_clock_output_clk, -- clock_output.clk
aclr_out => clock_0_clock_output_reset, -- .reset
clock => Clock, -- clock.clk
aclr => aclr -- .reset
);
bus_conversion1 : component alt_dspbuilder_cast_GNKXX25S2S
generic map (
round => 0,
saturate => 0
)
port map (
input => cast0_output_wire, -- input.wire
output => bus_conversion1_output_wire -- output.wire
);
writedata_0 : component alt_dspbuilder_port_GNEPKLLZKY
port map (
input => writedata, -- input.wire
output => writedata_0_output_wire -- output.wire
);
multiplexer : component alt_dspbuilder_multiplexer_GNCALBUTDR
generic map (
HDLTYPE => "STD_LOGIC_VECTOR",
use_one_hot_select_bus => 0,
width => 24,
pipeline => 0,
number_inputs => 2
)
port map (
clock => clock_0_clock_output_clk, -- clock_aclr.clk
aclr => clock_0_clock_output_reset, -- .reset
sel => delay_output_wire, -- sel.wire
result => multiplexer_result_wire, -- result.wire
ena => multiplexerenavcc_output_wire, -- ena.wire
user_aclr => multiplexeruser_aclrgnd_output_wire, -- user_aclr.wire
in0 => data_in_0_output_wire, -- in0.wire
in1 => multiplexer1_result_wire -- in1.wire
);
multiplexeruser_aclrgnd : component alt_dspbuilder_gnd_GN
port map (
output => multiplexeruser_aclrgnd_output_wire -- output.wire
);
multiplexerenavcc : component alt_dspbuilder_vcc_GN
port map (
output => multiplexerenavcc_output_wire -- output.wire
);
bus_conversion : component alt_dspbuilder_cast_GNKXX25S2S
generic map (
round => 0,
saturate => 0
)
port map (
input => data_in_0_output_wire, -- input.wire
output => bus_conversion_output_wire -- output.wire
);
constant4 : component alt_dspbuilder_constant_GNZEH3JAKA
generic map (
HDLTYPE => "STD_LOGIC_VECTOR",
BitPattern => "000000000000000000001111",
width => 24
)
port map (
output => constant4_output_wire -- output.wire
);
addr_0 : component alt_dspbuilder_port_GN6TDLHAW6
port map (
input => addr, -- input.wire
output => addr_0_output_wire -- output.wire
);
constant3 : component alt_dspbuilder_constant_GNNKZSYI73
generic map (
HDLTYPE => "STD_LOGIC_VECTOR",
BitPattern => "000000000000000000000000",
width => 24
)
port map (
output => constant3_output_wire -- output.wire
);
constant2 : component alt_dspbuilder_constant_GNLMV7GZFA
generic map (
HDLTYPE => "STD_LOGIC_VECTOR",
BitPattern => "111111111111111111111111",
width => 24
)
port map (
output => constant2_output_wire -- output.wire
);
if_statement : component alt_dspbuilder_if_statement_GNYT6HZJI5
generic map (
use_else_output => 0,
bwr => 0,
use_else_input => 0,
signed => 0,
HDLTYPE => "STD_LOGIC_VECTOR",
if_expression => "a>b",
number_inputs => 2,
width => 8
)
port map (
true => if_statement_true_wire, -- true.wire
a => bus_conversion_output_wire, -- a.wire
b => delay3_output_wire -- b.wire
);
constant1 : component alt_dspbuilder_constant_GNNKZSYI73
generic map (
HDLTYPE => "STD_LOGIC_VECTOR",
BitPattern => "000000000000000000000000",
width => 24
)
port map (
output => constant1_output_wire -- output.wire
);
delay : component alt_dspbuilder_delay_GNUECIBFDH
generic map (
ClockPhase => "1",
delay => 1,
use_init => 1,
BitPattern => "0",
width => 1
)
port map (
input => cast2_output_wire, -- input.wire
clock => clock_0_clock_output_clk, -- clock_aclr.clk
aclr => clock_0_clock_output_reset, -- .reset
output => delay_output_wire, -- output.wire
sclr => cast1_output_wire, -- sclr.wire
ena => logical_bit_operator_result_wire -- ena.wire
);
write_0 : component alt_dspbuilder_port_GN37ALZBS4
port map (
input => write, -- input.wire
output => write_0_output_wire -- output.wire
);
logical_bit_operator3 : component alt_dspbuilder_logical_bit_op_GNA5ZFEL7V
generic map (
LogicalOp => "AltAND",
number_inputs => 2
)
port map (
result => logical_bit_operator3_result_wire, -- result.wire
data0 => sop_0_output_wire, -- data0.wire
data1 => decoder1_dec_wire -- data1.wire
);
eop_0 : component alt_dspbuilder_port_GN37ALZBS4
port map (
input => eop, -- input.wire
output => eop_0_output_wire -- output.wire
);
logical_bit_operator2 : component alt_dspbuilder_logical_bit_op_GNA5ZFEL7V
generic map (
LogicalOp => "AltAND",
number_inputs => 2
)
port map (
result => logical_bit_operator2_result_wire, -- result.wire
data0 => decoder_dec_wire, -- data0.wire
data1 => write_0_output_wire -- data1.wire
);
logical_bit_operator1 : component alt_dspbuilder_logical_bit_op_GNA5ZFEL7V
generic map (
LogicalOp => "AltAND",
number_inputs => 2
)
port map (
result => logical_bit_operator1_result_wire, -- result.wire
data0 => eop_0_output_wire, -- data0.wire
data1 => cast3_output_wire -- data1.wire
);
decoder1 : component alt_dspbuilder_decoder_GNSCEXJCJK
generic map (
decode => "000000000000000000001111",
pipeline => 0,
width => 24
)
port map (
clock => clock_0_clock_output_clk, -- clock_aclr.clk
aclr => clock_0_clock_output_reset, -- .reset
data => data_in_0_output_wire, -- data.wire
dec => decoder1_dec_wire, -- dec.wire
sclr => decoder1sclrgnd_output_wire, -- sclr.wire
ena => decoder1enavcc_output_wire -- ena.wire
);
decoder1sclrgnd : component alt_dspbuilder_gnd_GN
port map (
output => decoder1sclrgnd_output_wire -- output.wire
);
decoder1enavcc : component alt_dspbuilder_vcc_GN
port map (
output => decoder1enavcc_output_wire -- output.wire
);
logical_bit_operator : component alt_dspbuilder_logical_bit_op_GNA5ZFEL7V
generic map (
LogicalOp => "AltAND",
number_inputs => 2
)
port map (
result => logical_bit_operator_result_wire, -- result.wire
data0 => if_statement1_true_wire, -- data0.wire
data1 => sop_0_output_wire -- data1.wire
);
delay3 : component alt_dspbuilder_delay_GNVTJPHWYT
generic map (
ClockPhase => "1",
delay => 1,
use_init => 1,
BitPattern => "01111111",
width => 8
)
port map (
input => delay2_output_wire, -- input.wire
clock => clock_0_clock_output_clk, -- clock_aclr.clk
aclr => clock_0_clock_output_reset, -- .reset
output => delay3_output_wire, -- output.wire
sclr => delay3sclrgnd_output_wire, -- sclr.wire
ena => logical_bit_operator3_result_wire -- ena.wire
);
delay3sclrgnd : component alt_dspbuilder_gnd_GN
port map (
output => delay3sclrgnd_output_wire -- output.wire
);
if_statement1 : component alt_dspbuilder_if_statement_GN7VA7SRUP
generic map (
use_else_output => 0,
bwr => 0,
use_else_input => 0,
signed => 0,
HDLTYPE => "STD_LOGIC_VECTOR",
if_expression => "(a=b) and (a /= c)",
number_inputs => 3,
width => 24
)
port map (
true => if_statement1_true_wire, -- true.wire
a => data_in_0_output_wire, -- a.wire
b => constant3_output_wire, -- b.wire
c => constant4_output_wire -- c.wire
);
sop_0 : component alt_dspbuilder_port_GN37ALZBS4
port map (
input => sop, -- input.wire
output => sop_0_output_wire -- output.wire
);
multiplexer1 : component alt_dspbuilder_multiplexer_GNCALBUTDR
generic map (
HDLTYPE => "STD_LOGIC_VECTOR",
use_one_hot_select_bus => 0,
width => 24,
pipeline => 0,
number_inputs => 2
)
port map (
clock => clock_0_clock_output_clk, -- clock_aclr.clk
aclr => clock_0_clock_output_reset, -- .reset
sel => cast5_output_wire, -- sel.wire
result => multiplexer1_result_wire, -- result.wire
ena => multiplexer1enavcc_output_wire, -- ena.wire
user_aclr => multiplexer1user_aclrgnd_output_wire, -- user_aclr.wire
in0 => constant1_output_wire, -- in0.wire
in1 => constant2_output_wire -- in1.wire
);
multiplexer1user_aclrgnd : component alt_dspbuilder_gnd_GN
port map (
output => multiplexer1user_aclrgnd_output_wire -- output.wire
);
multiplexer1enavcc : component alt_dspbuilder_vcc_GN
port map (
output => multiplexer1enavcc_output_wire -- output.wire
);
delay1 : component alt_dspbuilder_delay_GNHYCSAEGT
generic map (
ClockPhase => "1",
delay => 1,
use_init => 0,
BitPattern => "0",
width => 1
)
port map (
input => cast4_output_wire, -- input.wire
clock => clock_0_clock_output_clk, -- clock_aclr.clk
aclr => clock_0_clock_output_reset, -- .reset
output => delay1_output_wire, -- output.wire
sclr => delay1sclrgnd_output_wire, -- sclr.wire
ena => delay1enavcc_output_wire -- ena.wire
);
delay1sclrgnd : component alt_dspbuilder_gnd_GN
port map (
output => delay1sclrgnd_output_wire -- output.wire
);
delay1enavcc : component alt_dspbuilder_vcc_GN
port map (
output => delay1enavcc_output_wire -- output.wire
);
delay2 : component alt_dspbuilder_delay_GNVTJPHWYT
generic map (
ClockPhase => "1",
delay => 1,
use_init => 1,
BitPattern => "01111111",
width => 8
)
port map (
input => bus_conversion1_output_wire, -- input.wire
clock => clock_0_clock_output_clk, -- clock_aclr.clk
aclr => clock_0_clock_output_reset, -- .reset
output => delay2_output_wire, -- output.wire
sclr => delay2sclrgnd_output_wire, -- sclr.wire
ena => logical_bit_operator2_result_wire -- ena.wire
);
delay2sclrgnd : component alt_dspbuilder_gnd_GN
port map (
output => delay2sclrgnd_output_wire -- output.wire
);
data_out_0 : component alt_dspbuilder_port_GNOC3SGKQJ
port map (
input => multiplexer_result_wire, -- input.wire
output => data_out -- output.wire
);
data_in_0 : component alt_dspbuilder_port_GNOC3SGKQJ
port map (
input => data_in, -- input.wire
output => data_in_0_output_wire -- output.wire
);
decoder : component alt_dspbuilder_decoder_GNM4LOIHXZ
generic map (
decode => "01",
pipeline => 1,
width => 2
)
port map (
clock => clock_0_clock_output_clk, -- clock_aclr.clk
aclr => clock_0_clock_output_reset, -- .reset
data => addr_0_output_wire, -- data.wire
dec => decoder_dec_wire, -- dec.wire
sclr => decodersclrgnd_output_wire, -- sclr.wire
ena => decoderenavcc_output_wire -- ena.wire
);
decodersclrgnd : component alt_dspbuilder_gnd_GN
port map (
output => decodersclrgnd_output_wire -- output.wire
);
decoderenavcc : component alt_dspbuilder_vcc_GN
port map (
output => decoderenavcc_output_wire -- output.wire
);
cast0 : component alt_dspbuilder_cast_GN7PRGDOVA
generic map (
round => 0,
saturate => 0
)
port map (
input => writedata_0_output_wire, -- input.wire
output => cast0_output_wire -- output.wire
);
cast1 : component alt_dspbuilder_cast_GNSB3OXIQS
generic map (
round => 0,
saturate => 0
)
port map (
input => delay1_output_wire, -- input.wire
output => cast1_output_wire -- output.wire
);
cast2 : component alt_dspbuilder_cast_GN46N4UJ5S
generic map (
round => 0,
saturate => 0
)
port map (
input => logical_bit_operator_result_wire, -- input.wire
output => cast2_output_wire -- output.wire
);
cast3 : component alt_dspbuilder_cast_GNSB3OXIQS
generic map (
round => 0,
saturate => 0
)
port map (
input => delay_output_wire, -- input.wire
output => cast3_output_wire -- output.wire
);
cast4 : component alt_dspbuilder_cast_GN46N4UJ5S
generic map (
round => 0,
saturate => 0
)
port map (
input => logical_bit_operator1_result_wire, -- input.wire
output => cast4_output_wire -- output.wire
);
cast5 : component alt_dspbuilder_cast_GN46N4UJ5S
generic map (
round => 0,
saturate => 0
)
port map (
input => if_statement_true_wire, -- input.wire
output => cast5_output_wire -- output.wire
);
end architecture rtl; -- of Binarization_GN_Binarization_Binarization_Module
| mit | 5ebe8f65b5541cd5150e44425faf5013 | 0.558885 | 3.397961 | false | false | false | false |
grwlf/vsim | vhdl_ct/ct00003.vhd | 1 | 4,669 | -- NEED RESULT: ARCH00003.P1: Wait statement causes suspension of a process statement passed
-- NEED RESULT: ARCH00003.Glb_Proc1: Wait statement causes suspension of a procedure passed
-- NEED RESULT: ARCH00003.P2: Wait statement causes suspension of a process statement passed
-- NEED RESULT: ARCH00003.Glb_Proc2: Wait statement causes suspension of a procedure passed
-- NEED RESULT: ARCH00003.P3: Wait statement causes suspension of a process statement passed
-- NEED RESULT: ARCH00003.P4.Loc_Proc1: Wait statement causes suspension of a procedure passed
-- NEED RESULT: ARCH00003.P4: Wait statement causes suspension of a process statement passed
-- NEED RESULT: ARCH00003.P5.Loc_Proc2: Wait statement causes suspension of a procedure passed
-- NEED RESULT: ARCH00003.P5: Wait statement causes suspension of a process statement passed
-------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
-------------------------------------------------------------------------------
--
-- TEST NAME:
--
-- CT00003
--
-- AUTHOR:
--
-- G. Tominovich
--
-- TEST OBJECTIVES:
--
-- 8.1 (1)
--
-- DESIGN UNIT ORDERING:
--
-- E00000(ARCH00003)
-- ENT00003_Test_Bench(ARCH00003_Test_Bench)
--
-- REVISION HISTORY:
--
-- 25-JUN-1987 - initial revision
--
-- NOTES:
--
-- self-checking
--
use WORK.STANDARD_TYPES.all ;
architecture ARCH00003 of E00000 is -- Check with simple names
signal Pulse : Boolean := c_boolean_1 ;
procedure Glb_Proc1 is
variable Save : Boolean ;
begin
Save := Pulse ;
wait on Pulse ;
test_report ( "ARCH00003.Glb_Proc1" ,
"Wait statement causes suspension of a procedure" ,
Save /= Pulse ) ;
end Glb_Proc1 ;
procedure Glb_Proc2 ( signal InParm : in Boolean ) is
variable Save : Boolean ;
begin
Save := InParm ;
wait on InParm ;
test_report ( "ARCH00003.Glb_Proc2" ,
"Wait statement causes suspension of a procedure" ,
Save /= InParm ) ;
end Glb_Proc2 ;
begin
Change_Pulse :
process (Pulse)
begin
if Pulse /= c_boolean_2 then
Pulse <= transport c_boolean_2 after 1 ns ;
end if ;
end process Change_Pulse ;
P1 :
process
variable Save : Boolean ;
begin
Save := Pulse ;
wait on Pulse ;
test_report ( "ARCH00003.P1" ,
"Wait statement causes suspension of a process statement" ,
Save /= Pulse ) ;
end process P1 ;
P2 :
process
variable Save : Boolean ;
begin
Save := Pulse ;
Glb_Proc1 ;
test_report ( "ARCH00003.P2" ,
"Wait statement causes suspension of a process statement" ,
Save /= Pulse ) ;
end process P2 ;
P3 :
process
variable Save : Boolean ;
begin
Save := Pulse ;
Glb_Proc2 ( Pulse ) ;
test_report ( "ARCH00003.P3" ,
"Wait statement causes suspension of a process statement" ,
Save /= Pulse ) ;
end process P3 ;
P4 :
process
variable Save : Boolean ;
procedure Loc_Proc1 is
variable Save : Boolean ;
begin
Save := Pulse ;
wait on Pulse ;
test_report ( "ARCH00003.P4.Loc_Proc1" ,
"Wait statement causes suspension of a procedure" ,
Save /= Pulse ) ;
end Loc_Proc1 ;
begin
Save := Pulse ;
Loc_Proc1 ;
test_report ( "ARCH00003.P4" ,
"Wait statement causes suspension of a process statement" ,
Save /= Pulse ) ;
end process P4 ;
P5 :
process
variable Save : Boolean ;
procedure Loc_Proc2 ( signal InParm : in Boolean ) is
variable Save : Boolean ;
begin
Save := InParm ;
wait on InParm ;
test_report ( "ARCH00003.P5.Loc_Proc2" ,
"Wait statement causes suspension of a procedure" ,
Save /= InParm ) ;
end Loc_Proc2 ;
begin
Save := Pulse ;
Loc_Proc2 ( Pulse ) ;
test_report ( "ARCH00003.P5" ,
"Wait statement causes suspension of a process statement" ,
Save /= Pulse ) ;
end process P5 ;
end ARCH00003 ;
entity ENT00003_Test_Bench is
end ENT00003_Test_Bench ;
architecture ARCH00003_Test_Bench of ENT00003_Test_Bench is
begin
L1:
block
component UUT
end component ;
for CIS1 : UUT use entity WORK.E00000 ( ARCH00003 ) ;
begin
CIS1 : UUT ;
end block L1 ;
end ARCH00003_Test_Bench ;
| gpl-3.0 | c967cfadcc511f004090b9d5fd87528f | 0.578496 | 3.881131 | false | true | false | false |
grwlf/vsim | vhdl_ct/ct00395.vhd | 1 | 19,782 | -- NEED RESULT: ARCH00395.P1: Multi inertial transactions occurred on concurrent signal asg passed
-- NEED RESULT: ARCH00395.P2: Multi inertial transactions occurred on concurrent signal asg passed
-- NEED RESULT: ARCH00395.P3: Multi inertial transactions occurred on concurrent signal asg passed
-- NEED RESULT: ARCH00395: One inertial transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00395: One inertial transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00395: One inertial transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00395: Old transactions were removed on a concurrent signal asg passed
-- NEED RESULT: ARCH00395: Old transactions were removed on a concurrent signal asg passed
-- NEED RESULT: ARCH00395: Old transactions were removed on a concurrent signal asg passed
-- NEED RESULT: ARCH00395: One inertial transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00395: One inertial transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00395: One inertial transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00395: Inertial semantics check on a concurrent signal asg passed
-- NEED RESULT: ARCH00395: Inertial semantics check on a concurrent signal asg passed
-- NEED RESULT: ARCH00395: Inertial semantics check on a concurrent signal asg passed
-- NEED RESULT: P3: Inertial transactions completed entirely passed
-- NEED RESULT: P2: Inertial transactions completed entirely passed
-- NEED RESULT: P1: Inertial transactions completed entirely passed
-------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
-------------------------------------------------------------------------------
--
-- TEST NAME:
--
-- CT00395
--
-- AUTHOR:
--
-- G. Tominovich
--
-- TEST OBJECTIVES:
--
-- 9.5 (3)
-- 9.5.2 (1)
--
-- DESIGN UNIT ORDERING:
--
-- ENT00395(ARCH00395)
-- ENT00395_Test_Bench(ARCH00395_Test_Bench)
--
-- REVISION HISTORY:
--
-- 30-JUL-1987 - initial revision
--
-- NOTES:
--
-- self-checking
-- automatically generated
--
use WORK.STANDARD_TYPES.all ;
entity ENT00395 is
port (
s_st_rec1 : inout st_rec1
; s_st_rec2 : inout st_rec2
; s_st_rec3 : inout st_rec3
) ;
subtype chk_sig_type is integer range -1 to 100 ;
signal chk_st_rec1 : chk_sig_type := -1 ;
signal chk_st_rec2 : chk_sig_type := -1 ;
signal chk_st_rec3 : chk_sig_type := -1 ;
--
end ENT00395 ;
--
--
architecture ARCH00395 of ENT00395 is
subtype chk_time_type is Time ;
signal s_st_rec1_savt : chk_time_type := 0 ns ;
signal s_st_rec2_savt : chk_time_type := 0 ns ;
signal s_st_rec3_savt : chk_time_type := 0 ns ;
--
subtype chk_cnt_type is Integer ;
signal s_st_rec1_cnt : chk_cnt_type := 0 ;
signal s_st_rec2_cnt : chk_cnt_type := 0 ;
signal s_st_rec3_cnt : chk_cnt_type := 0 ;
--
type select_type is range 1 to 6 ;
signal st_rec1_select : select_type := 1 ;
signal st_rec2_select : select_type := 1 ;
signal st_rec3_select : select_type := 1 ;
--
begin
CHG1 :
process
variable correct : boolean ;
begin
case s_st_rec1_cnt is
when 0
=> null ;
-- s_st_rec1.f2 <=
-- c_st_rec1_2.f2 after 10 ns,
-- c_st_rec1_1.f2 after 20 ns ;
--
when 1
=> correct :=
s_st_rec1.f2 =
c_st_rec1_2.f2 and
(s_st_rec1_savt + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_rec1.f2 =
c_st_rec1_1.f2 and
(s_st_rec1_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00395.P1" ,
"Multi inertial transactions occurred on " &
"concurrent signal asg",
correct ) ;
--
st_rec1_select <= transport 2 ;
-- s_st_rec1.f2 <=
-- c_st_rec1_2.f2 after 10 ns ,
-- c_st_rec1_1.f2 after 20 ns ,
-- c_st_rec1_2.f2 after 30 ns ,
-- c_st_rec1_1.f2 after 40 ns ;
--
when 3
=> correct :=
s_st_rec1.f2 =
c_st_rec1_2.f2 and
(s_st_rec1_savt + 10 ns) = Std.Standard.Now ;
st_rec1_select <= transport 3 ;
-- s_st_rec1.f2 <=
-- c_st_rec1_1.f2 after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_rec1.f2 =
c_st_rec1_1.f2 and
(s_st_rec1_savt + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00395" ,
"One inertial transaction occurred on a " &
"concurrent signal asg",
correct ) ;
st_rec1_select <= transport 4 ;
-- s_st_rec1.f2 <=
-- c_st_rec1_1.f2 after 100 ns ;
--
when 5
=> correct :=
correct and
s_st_rec1.f2 =
c_st_rec1_1.f2 and
(s_st_rec1_savt + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00395" ,
"Old transactions were removed on a " &
"concurrent signal asg",
correct ) ;
st_rec1_select <= transport 5 ;
-- s_st_rec1.f2 <=
-- c_st_rec1_2.f2 after 10 ns ,
-- c_st_rec1_1.f2 after 20 ns ,
-- c_st_rec1_2.f2 after 30 ns ,
-- c_st_rec1_1.f2 after 40 ns ;
--
when 6
=> correct :=
correct and
s_st_rec1.f2 =
c_st_rec1_2.f2 and
(s_st_rec1_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00395" ,
"One inertial transaction occurred on a " &
"concurrent signal asg",
correct ) ;
st_rec1_select <= transport 6 ;
-- Last transaction above is marked
-- s_st_rec1.f2 <=
-- c_st_rec1_1.f2 after 40 ns ;
--
when 7
=> correct :=
correct and
s_st_rec1.f2 =
c_st_rec1_1.f2 and
(s_st_rec1_savt + 30 ns) = Std.Standard.Now ;
--
when 8
=> correct :=
correct and
s_st_rec1.f2 =
c_st_rec1_1.f2 and
(s_st_rec1_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00395" ,
"Inertial semantics check on a concurrent " &
"signal asg",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00395" ,
"Inertial semantics check on a concurrent " &
"signal asg",
false ) ;
--
end case ;
--
s_st_rec1_savt <= transport Std.Standard.Now ;
chk_st_rec1 <= transport s_st_rec1_cnt
after (1 us - Std.Standard.Now) ;
s_st_rec1_cnt <= transport s_st_rec1_cnt + 1 ;
wait until (not s_st_rec1.f2'Quiet) and
(s_st_rec1_savt /= Std.Standard.Now) ;
--
end process CHG1 ;
--
PGEN_CHKP_1 :
process ( chk_st_rec1 )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P1" ,
"Inertial transactions completed entirely",
chk_st_rec1 = 8 ) ;
end if ;
end process PGEN_CHKP_1 ;
--
--
with st_rec1_select select
s_st_rec1.f2 <=
c_st_rec1_2.f2 after 10 ns,
c_st_rec1_1.f2 after 20 ns
when 1,
--
c_st_rec1_2.f2 after 10 ns ,
c_st_rec1_1.f2 after 20 ns ,
c_st_rec1_2.f2 after 30 ns ,
c_st_rec1_1.f2 after 40 ns
when 2,
--
c_st_rec1_1.f2 after 5 ns
when 3,
--
c_st_rec1_1.f2 after 100 ns
when 4,
--
c_st_rec1_2.f2 after 10 ns ,
c_st_rec1_1.f2 after 20 ns ,
c_st_rec1_2.f2 after 30 ns ,
c_st_rec1_1.f2 after 40 ns
when 5,
--
-- Last transaction above is marked
c_st_rec1_1.f2 after 40 ns when 6 ;
--
CHG2 :
process
variable correct : boolean ;
begin
case s_st_rec2_cnt is
when 0
=> null ;
-- s_st_rec2.f2 <=
-- c_st_rec2_2.f2 after 10 ns,
-- c_st_rec2_1.f2 after 20 ns ;
--
when 1
=> correct :=
s_st_rec2.f2 =
c_st_rec2_2.f2 and
(s_st_rec2_savt + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_rec2.f2 =
c_st_rec2_1.f2 and
(s_st_rec2_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00395.P2" ,
"Multi inertial transactions occurred on " &
"concurrent signal asg",
correct ) ;
--
st_rec2_select <= transport 2 ;
-- s_st_rec2.f2 <=
-- c_st_rec2_2.f2 after 10 ns ,
-- c_st_rec2_1.f2 after 20 ns ,
-- c_st_rec2_2.f2 after 30 ns ,
-- c_st_rec2_1.f2 after 40 ns ;
--
when 3
=> correct :=
s_st_rec2.f2 =
c_st_rec2_2.f2 and
(s_st_rec2_savt + 10 ns) = Std.Standard.Now ;
st_rec2_select <= transport 3 ;
-- s_st_rec2.f2 <=
-- c_st_rec2_1.f2 after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_rec2.f2 =
c_st_rec2_1.f2 and
(s_st_rec2_savt + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00395" ,
"One inertial transaction occurred on a " &
"concurrent signal asg",
correct ) ;
st_rec2_select <= transport 4 ;
-- s_st_rec2.f2 <=
-- c_st_rec2_1.f2 after 100 ns ;
--
when 5
=> correct :=
correct and
s_st_rec2.f2 =
c_st_rec2_1.f2 and
(s_st_rec2_savt + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00395" ,
"Old transactions were removed on a " &
"concurrent signal asg",
correct ) ;
st_rec2_select <= transport 5 ;
-- s_st_rec2.f2 <=
-- c_st_rec2_2.f2 after 10 ns ,
-- c_st_rec2_1.f2 after 20 ns ,
-- c_st_rec2_2.f2 after 30 ns ,
-- c_st_rec2_1.f2 after 40 ns ;
--
when 6
=> correct :=
correct and
s_st_rec2.f2 =
c_st_rec2_2.f2 and
(s_st_rec2_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00395" ,
"One inertial transaction occurred on a " &
"concurrent signal asg",
correct ) ;
st_rec2_select <= transport 6 ;
-- Last transaction above is marked
-- s_st_rec2.f2 <=
-- c_st_rec2_1.f2 after 40 ns ;
--
when 7
=> correct :=
correct and
s_st_rec2.f2 =
c_st_rec2_1.f2 and
(s_st_rec2_savt + 30 ns) = Std.Standard.Now ;
--
when 8
=> correct :=
correct and
s_st_rec2.f2 =
c_st_rec2_1.f2 and
(s_st_rec2_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00395" ,
"Inertial semantics check on a concurrent " &
"signal asg",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00395" ,
"Inertial semantics check on a concurrent " &
"signal asg",
false ) ;
--
end case ;
--
s_st_rec2_savt <= transport Std.Standard.Now ;
chk_st_rec2 <= transport s_st_rec2_cnt
after (1 us - Std.Standard.Now) ;
s_st_rec2_cnt <= transport s_st_rec2_cnt + 1 ;
wait until (not s_st_rec2.f2'Quiet) and
(s_st_rec2_savt /= Std.Standard.Now) ;
--
end process CHG2 ;
--
PGEN_CHKP_2 :
process ( chk_st_rec2 )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P2" ,
"Inertial transactions completed entirely",
chk_st_rec2 = 8 ) ;
end if ;
end process PGEN_CHKP_2 ;
--
--
with st_rec2_select select
s_st_rec2.f2 <=
c_st_rec2_2.f2 after 10 ns,
c_st_rec2_1.f2 after 20 ns
when 1,
--
c_st_rec2_2.f2 after 10 ns ,
c_st_rec2_1.f2 after 20 ns ,
c_st_rec2_2.f2 after 30 ns ,
c_st_rec2_1.f2 after 40 ns
when 2,
--
c_st_rec2_1.f2 after 5 ns
when 3,
--
c_st_rec2_1.f2 after 100 ns
when 4,
--
c_st_rec2_2.f2 after 10 ns ,
c_st_rec2_1.f2 after 20 ns ,
c_st_rec2_2.f2 after 30 ns ,
c_st_rec2_1.f2 after 40 ns
when 5,
--
-- Last transaction above is marked
c_st_rec2_1.f2 after 40 ns when 6 ;
--
CHG3 :
process
variable correct : boolean ;
begin
case s_st_rec3_cnt is
when 0
=> null ;
-- s_st_rec3.f2 <=
-- c_st_rec3_2.f2 after 10 ns,
-- c_st_rec3_1.f2 after 20 ns ;
--
when 1
=> correct :=
s_st_rec3.f2 =
c_st_rec3_2.f2 and
(s_st_rec3_savt + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_rec3.f2 =
c_st_rec3_1.f2 and
(s_st_rec3_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00395.P3" ,
"Multi inertial transactions occurred on " &
"concurrent signal asg",
correct ) ;
--
st_rec3_select <= transport 2 ;
-- s_st_rec3.f2 <=
-- c_st_rec3_2.f2 after 10 ns ,
-- c_st_rec3_1.f2 after 20 ns ,
-- c_st_rec3_2.f2 after 30 ns ,
-- c_st_rec3_1.f2 after 40 ns ;
--
when 3
=> correct :=
s_st_rec3.f2 =
c_st_rec3_2.f2 and
(s_st_rec3_savt + 10 ns) = Std.Standard.Now ;
st_rec3_select <= transport 3 ;
-- s_st_rec3.f2 <=
-- c_st_rec3_1.f2 after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_rec3.f2 =
c_st_rec3_1.f2 and
(s_st_rec3_savt + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00395" ,
"One inertial transaction occurred on a " &
"concurrent signal asg",
correct ) ;
st_rec3_select <= transport 4 ;
-- s_st_rec3.f2 <=
-- c_st_rec3_1.f2 after 100 ns ;
--
when 5
=> correct :=
correct and
s_st_rec3.f2 =
c_st_rec3_1.f2 and
(s_st_rec3_savt + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00395" ,
"Old transactions were removed on a " &
"concurrent signal asg",
correct ) ;
st_rec3_select <= transport 5 ;
-- s_st_rec3.f2 <=
-- c_st_rec3_2.f2 after 10 ns ,
-- c_st_rec3_1.f2 after 20 ns ,
-- c_st_rec3_2.f2 after 30 ns ,
-- c_st_rec3_1.f2 after 40 ns ;
--
when 6
=> correct :=
correct and
s_st_rec3.f2 =
c_st_rec3_2.f2 and
(s_st_rec3_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00395" ,
"One inertial transaction occurred on a " &
"concurrent signal asg",
correct ) ;
st_rec3_select <= transport 6 ;
-- Last transaction above is marked
-- s_st_rec3.f2 <=
-- c_st_rec3_1.f2 after 40 ns ;
--
when 7
=> correct :=
correct and
s_st_rec3.f2 =
c_st_rec3_1.f2 and
(s_st_rec3_savt + 30 ns) = Std.Standard.Now ;
--
when 8
=> correct :=
correct and
s_st_rec3.f2 =
c_st_rec3_1.f2 and
(s_st_rec3_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00395" ,
"Inertial semantics check on a concurrent " &
"signal asg",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00395" ,
"Inertial semantics check on a concurrent " &
"signal asg",
false ) ;
--
end case ;
--
s_st_rec3_savt <= transport Std.Standard.Now ;
chk_st_rec3 <= transport s_st_rec3_cnt
after (1 us - Std.Standard.Now) ;
s_st_rec3_cnt <= transport s_st_rec3_cnt + 1 ;
wait until (not s_st_rec3.f2'Quiet) and
(s_st_rec3_savt /= Std.Standard.Now) ;
--
end process CHG3 ;
--
PGEN_CHKP_3 :
process ( chk_st_rec3 )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P3" ,
"Inertial transactions completed entirely",
chk_st_rec3 = 8 ) ;
end if ;
end process PGEN_CHKP_3 ;
--
--
with st_rec3_select select
s_st_rec3.f2 <=
c_st_rec3_2.f2 after 10 ns,
c_st_rec3_1.f2 after 20 ns
when 1,
--
c_st_rec3_2.f2 after 10 ns ,
c_st_rec3_1.f2 after 20 ns ,
c_st_rec3_2.f2 after 30 ns ,
c_st_rec3_1.f2 after 40 ns
when 2,
--
c_st_rec3_1.f2 after 5 ns
when 3,
--
c_st_rec3_1.f2 after 100 ns
when 4,
--
c_st_rec3_2.f2 after 10 ns ,
c_st_rec3_1.f2 after 20 ns ,
c_st_rec3_2.f2 after 30 ns ,
c_st_rec3_1.f2 after 40 ns
when 5,
--
-- Last transaction above is marked
c_st_rec3_1.f2 after 40 ns when 6 ;
--
end ARCH00395 ;
--
--
use WORK.STANDARD_TYPES.all ;
entity ENT00395_Test_Bench is
signal s_st_rec1 : st_rec1
:= c_st_rec1_1 ;
signal s_st_rec2 : st_rec2
:= c_st_rec2_1 ;
signal s_st_rec3 : st_rec3
:= c_st_rec3_1 ;
--
end ENT00395_Test_Bench ;
--
--
architecture ARCH00395_Test_Bench of ENT00395_Test_Bench is
begin
L1:
block
component UUT
port (
s_st_rec1 : inout st_rec1
; s_st_rec2 : inout st_rec2
; s_st_rec3 : inout st_rec3
) ;
end component ;
--
for CIS1 : UUT use entity WORK.ENT00395 ( ARCH00395 ) ;
begin
CIS1 : UUT
port map (
s_st_rec1
, s_st_rec2
, s_st_rec3
)
;
end block L1 ;
end ARCH00395_Test_Bench ;
| gpl-3.0 | d45a7c96c0dd64cc4f8ad029fb73392d | 0.466485 | 3.346642 | false | false | false | false |
grwlf/vsim | vhdl_ct/ct00591.vhd | 1 | 29,134 | -- NEED RESULT: ARCH00591: Variable declarations - composite dynamic access subtypes passed
-------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
-------------------------------------------------------------------------------
--
-- TEST NAME:
--
-- CT00591
--
-- AUTHOR:
--
-- A. Wilmot
--
-- TEST OBJECTIVES:
--
-- 4.3.1.3 (12)
--
-- DESIGN UNIT ORDERING:
--
-- E00000(ARCH00591)
-- ENT00591_Test_Bench(ARCH00591_Test_Bench)
--
-- REVISION HISTORY:
--
-- 19-AUG-1987 - initial revision
--
-- NOTES:
--
-- self-checking
-- automatically generated
--
use WORK.STANDARD_TYPES.test_report ;
architecture ARCH00591 of E00000 is
procedure p1 (
constant lowb : integer := 1 ;
constant highb : integer := 10 ;
constant lowb_i2 : integer := 0 ;
constant highb_i2 : integer := 1000 ;
constant lowb_p : integer := -100 ;
constant highb_p : integer := 1000 ;
constant lowb_r : real := 0.0 ;
constant highb_r : real := 1000.0 ;
constant lowb_r2 : real := 8.0 ;
constant highb_r2 : real := 80.0
--
) is
variable correct : boolean := true ;
--
-- assertion: c_xxxxx_2 >= c_xxxxx_1
-- enumeration types
-- predefined
-- boolean
constant c_boolean_1 : boolean := false ;
constant c_boolean_2 : boolean := true ;
--
type boolean_vector is array (integer range <>) of boolean ;
subtype boolean_vector_range1 is integer range lowb to highb ;
subtype st_boolean_vector is boolean_vector (boolean_vector_range1) ;
constant c_st_boolean_vector_1 : st_boolean_vector :=
(others => c_boolean_1) ;
constant c_st_boolean_vector_2 : st_boolean_vector :=
(others => c_boolean_2) ;
--
-- bit
constant c_bit_1 : bit := '0' ;
constant c_bit_2 : bit := '1' ;
--
constant c_bit_vector_1 : bit_vector := B"0000" ;
constant c_bit_vector_2 : bit_vector := B"1111" ;
subtype bit_vector_range1 is integer range lowb to highb ;
subtype st_bit_vector is bit_vector (bit_vector_range1) ;
constant c_st_bit_vector_1 : st_bit_vector :=
(others => c_bit_1) ;
constant c_st_bit_vector_2 : st_bit_vector :=
(others => c_bit_2) ;
-- severity_level
constant c_severity_level_1 : severity_level := NOTE ;
constant c_severity_level_2 : severity_level := WARNING ;
--
type severity_level_vector is array (integer range <>) of severity_level ;
subtype severity_level_vector_range1 is integer range lowb to highb ;
subtype st_severity_level_vector is
severity_level_vector (severity_level_vector_range1) ;
constant c_st_severity_level_vector_1 : st_severity_level_vector :=
(others => c_severity_level_1) ;
constant c_st_severity_level_vector_2 : st_severity_level_vector :=
(others => c_severity_level_2) ;
--
-- character
constant c_character_1 : character := 'A' ;
constant c_character_2 : character := 'a' ;
--
constant c_string_1 : string := "ABC0000" ;
constant c_string_2 : string := "ABC1111" ;
subtype string_range1 is integer range lowb to highb ;
subtype st_string is string (string_range1) ;
constant c_st_string_1 : st_string :=
(others => c_character_1) ;
constant c_st_string_2 : st_string :=
(others => c_character_2) ;
-- user defined enumeration
type t_enum1 is (en1, en2, en3, en4) ;
constant c_t_enum1_1 : t_enum1 := en1 ;
constant c_t_enum1_2 : t_enum1 := en2 ;
subtype st_enum1 is t_enum1 range en4 downto en1 ;
constant c_st_enum1_1 : st_enum1 := en1 ;
constant c_st_enum1_2 : st_enum1 := en2 ;
--
type enum1_vector is array (integer range <>) of st_enum1 ;
subtype enum1_vector_range1 is integer range lowb to highb ;
subtype st_enum1_vector is enum1_vector (enum1_vector_range1) ;
constant c_st_enum1_vector_1 : st_enum1_vector :=
(others => c_st_enum1_1) ;
constant c_st_enum1_vector_2 : st_enum1_vector :=
(others => c_st_enum1_2) ;
-- integer types
-- predefined
constant c_integer_1 : integer := lowb ;
constant c_integer_2 : integer := highb ;
--
type integer_vector is array (integer range <>) of integer ;
subtype integer_vector_range1 is integer range lowb to highb ;
subtype st_integer_vector is integer_vector (integer_vector_range1) ;
constant c_st_integer_vector_1 : st_integer_vector :=
(others => c_integer_1) ;
constant c_st_integer_vector_2 : st_integer_vector :=
(others => c_integer_2) ;
--
-- user defined integer type
type t_int1 is range 0 to 100 ;
constant c_t_int1_1 : t_int1 := 0 ;
constant c_t_int1_2 : t_int1 := 10 ;
subtype st_int1 is t_int1 range 8 to 60 ;
constant c_st_int1_1 : st_int1 := 8 ;
constant c_st_int1_2 : st_int1 := 9 ;
--
type int1_vector is array (integer range <>) of st_int1 ;
subtype int1_vector_range1 is integer range lowb to highb ;
subtype st_int1_vector is int1_vector (int1_vector_range1) ;
constant c_st_int1_vector_1 : st_int1_vector :=
(others => c_st_int1_1) ;
constant c_st_int1_vector_2 : st_int1_vector :=
(others => c_st_int1_2) ;
--
-- physical types
-- predefined
constant c_time_1 : time := 1 ns ;
constant c_time_2 : time := 2 ns ;
--
type time_vector is array (integer range <>) of time ;
subtype time_vector_range1 is integer range lowb to highb ;
subtype st_time_vector is time_vector (time_vector_range1) ;
constant c_st_time_vector_1 : st_time_vector :=
(others => c_time_1) ;
constant c_st_time_vector_2 : st_time_vector :=
(others => c_time_2) ;
--
-- user defined physical type
type t_phys1 is range -100 to 1000
units
phys1_1 ;
phys1_2 = 10 phys1_1 ;
phys1_3 = 10 phys1_2 ;
phys1_4 = 10 phys1_3 ;
phys1_5 = 10 phys1_4 ;
end units ;
--
constant c_t_phys1_1 : t_phys1 := phys1_1 ;
constant c_t_phys1_2 : t_phys1 := phys1_2 ;
subtype st_phys1 is t_phys1 range phys1_2 to phys1_4 ;
constant c_st_phys1_1 : st_phys1 := phys1_2 ;
constant c_st_phys1_2 : st_phys1 := phys1_3 ;
--
type phys1_vector is array (integer range <>) of st_phys1 ;
subtype phys1_vector_range1 is integer range lowb to highb ;
subtype st_phys1_vector is phys1_vector (phys1_vector_range1) ;
constant c_st_phys1_vector_1 : st_phys1_vector :=
(others => c_st_phys1_1) ;
constant c_st_phys1_vector_2 : st_phys1_vector :=
(others => c_st_phys1_2) ;
--
--
-- floating point types
-- predefined
constant c_real_1 : real := 0.0 ;
constant c_real_2 : real := 1.0 ;
--
type real_vector is array (integer range <>) of real ;
subtype real_vector_range1 is integer range lowb to highb ;
subtype st_real_vector is real_vector (real_vector_range1) ;
constant c_st_real_vector_1 : st_real_vector :=
(others => c_real_1) ;
constant c_st_real_vector_2 : st_real_vector :=
(others => c_real_2) ;
--
-- user defined floating type
type t_real1 is range 0.0 to 1000.0 ;
constant c_t_real1_1 : t_real1 := 0.0 ;
constant c_t_real1_2 : t_real1 := 1.0 ;
subtype st_real1 is t_real1 range 8.0 to 80.0 ;
constant c_st_real1_1 : st_real1 := 8.0 ;
constant c_st_real1_2 : st_real1 := 9.0 ;
--
type real1_vector is array (integer range <>) of st_real1 ;
subtype real1_vector_range1 is integer range lowb to highb ;
subtype st_real1_vector is real1_vector (real1_vector_range1) ;
constant c_st_real1_vector_1 : st_real1_vector :=
(others => c_st_real1_1) ;
constant c_st_real1_vector_2 : st_real1_vector :=
(others => c_st_real1_2) ;
-- composite types
--
-- simple record
type t_rec1 is record
f1 : integer range lowb_i2 to highb_i2 ;
f2 : time ;
f3 : boolean ;
f4 : real ;
end record ;
constant c_t_rec1_1 : t_rec1 :=
(c_integer_1, c_time_1, c_boolean_1, c_real_1) ;
constant c_t_rec1_2 : t_rec1 :=
(c_integer_2, c_time_2, c_boolean_2, c_real_2) ;
subtype st_rec1 is t_rec1 ;
constant c_st_rec1_1 : st_rec1 := c_t_rec1_1 ;
constant c_st_rec1_2 : st_rec1 := c_t_rec1_2 ;
--
type rec1_vector is array (integer range <>) of st_rec1 ;
subtype rec1_vector_range1 is integer range lowb to highb ;
subtype st_rec1_vector is rec1_vector (rec1_vector_range1) ;
constant c_st_rec1_vector_1 : st_rec1_vector :=
(others => c_st_rec1_1) ;
constant c_st_rec1_vector_2 : st_rec1_vector :=
(others => c_st_rec1_2) ;
--
--
-- more complex record
type t_rec2 is record
f1 : boolean ;
f2 : st_rec1 ;
f3 : time ;
end record ;
constant c_t_rec2_1 : t_rec2 :=
(c_boolean_1, c_st_rec1_1, c_time_1) ;
constant c_t_rec2_2 : t_rec2 :=
(c_boolean_2, c_st_rec1_2, c_time_2) ;
subtype st_rec2 is t_rec2 ;
constant c_st_rec2_1 : st_rec2 := c_t_rec2_1 ;
constant c_st_rec2_2 : st_rec2 := c_t_rec2_2 ;
--
type rec2_vector is array (integer range <>) of st_rec2 ;
subtype rec2_vector_range1 is integer range lowb to highb ;
subtype st_rec2_vector is rec2_vector (rec2_vector_range1) ;
constant c_st_rec2_vector_1 : st_rec2_vector :=
(others => c_st_rec2_1) ;
constant c_st_rec2_vector_2 : st_rec2_vector :=
(others => c_st_rec2_2) ;
--
-- simple array
type t_arr1 is array (integer range <>) of st_int1 ;
subtype t_arr1_range1 is integer range lowb to highb ;
subtype st_arr1 is t_arr1 (t_arr1_range1) ;
constant c_st_arr1_1 : st_arr1 := (others => c_st_int1_1) ;
constant c_st_arr1_2 : st_arr1 := (others => c_st_int1_2) ;
constant c_t_arr1_1 : st_arr1 := c_st_arr1_1 ;
constant c_t_arr1_2 : st_arr1 := c_st_arr1_2 ;
--
type arr1_vector is array (integer range <>) of st_arr1 ;
subtype arr1_vector_range1 is integer range lowb to highb ;
subtype st_arr1_vector is arr1_vector (arr1_vector_range1) ;
constant c_st_arr1_vector_1 : st_arr1_vector :=
(others => c_st_arr1_1) ;
constant c_st_arr1_vector_2 : st_arr1_vector :=
(others => c_st_arr1_2) ;
-- more complex array
type t_arr2 is array (integer range <>, boolean range <>) of st_arr1 ;
subtype t_arr2_range1 is integer range lowb to highb ;
subtype t_arr2_range2 is boolean range false to true ;
subtype st_arr2 is t_arr2 (t_arr2_range1, t_arr2_range2);
constant c_st_arr2_1 : st_arr2 := (others => (others => c_st_arr1_1)) ;
constant c_st_arr2_2 : st_arr2 := (others => (others => c_st_arr1_2)) ;
constant c_t_arr2_1 : st_arr2 := c_st_arr2_1 ;
constant c_t_arr2_2 : st_arr2 := c_st_arr2_2 ;
--
type arr2_vector is array (integer range <>) of st_arr2 ;
subtype arr2_vector_range1 is integer range lowb to highb ;
subtype st_arr2_vector is arr2_vector (arr2_vector_range1) ;
constant c_st_arr2_vector_1 : st_arr2_vector :=
(others => c_st_arr2_1) ;
constant c_st_arr2_vector_2 : st_arr2_vector :=
(others => c_st_arr2_2) ;
--
--
-- most complex record
type t_rec3 is record
f1 : boolean ;
f2 : st_rec2 ;
f3 : st_arr2 ;
end record ;
constant c_t_rec3_1 : t_rec3 :=
(c_boolean_1, c_st_rec2_1, c_st_arr2_1) ;
constant c_t_rec3_2 : t_rec3 :=
(c_boolean_2, c_st_rec2_2, c_st_arr2_2) ;
subtype st_rec3 is t_rec3 ;
constant c_st_rec3_1 : st_rec3 := c_t_rec3_1 ;
constant c_st_rec3_2 : st_rec3 := c_t_rec3_2 ;
--
type rec3_vector is array (integer range <>) of st_rec3 ;
subtype rec3_vector_range1 is integer range lowb to highb ;
subtype st_rec3_vector is rec3_vector (rec3_vector_range1) ;
constant c_st_rec3_vector_1 : st_rec3_vector :=
(others => c_st_rec3_1) ;
constant c_st_rec3_vector_2 : st_rec3_vector :=
(others => c_st_rec3_2) ;
--
-- most complex array
type t_arr3 is array (integer range <>, boolean range <>) of st_rec3 ;
subtype t_arr3_range1 is integer range lowb to highb ;
subtype t_arr3_range2 is boolean range true downto false ;
subtype st_arr3 is t_arr3 (t_arr3_range1, t_arr3_range2) ;
constant c_st_arr3_1 : st_arr3 := (others => (others => c_st_rec3_1)) ;
constant c_st_arr3_2 : st_arr3 := (others => (others => c_st_rec3_2)) ;
constant c_t_arr3_1 : st_arr3 := c_st_arr3_1 ;
constant c_t_arr3_2 : st_arr3 := c_st_arr3_2 ;
--
type arr3_vector is array (integer range <>) of st_arr3 ;
subtype arr3_vector_range1 is integer range lowb to highb ;
subtype st_arr3_vector is arr3_vector (arr3_vector_range1) ;
constant c_st_arr3_vector_1 : st_arr3_vector :=
(others => c_st_arr3_1) ;
constant c_st_arr3_vector_2 : st_arr3_vector :=
(others => c_st_arr3_2) ;
--
-- enumeration types
-- predefined
-- boolean
function bf_boolean(to_resolve : boolean_vector) return boolean is
variable sum : integer := 0 ;
begin
if to_resolve'length = 0 then
return boolean'left ;
else
for i in to_resolve'range loop
sum := sum + boolean'pos(to_resolve(i)) ;
end loop ;
return boolean'val(integer'pos(sum) mod
(boolean'pos(boolean'high) + 1)) ;
end if ;
end bf_boolean ;
--
--
-- bit
function bf_bit(to_resolve : bit_vector) return bit is
variable sum : integer := 0 ;
begin
if to_resolve'length = 0 then
return bit'left ;
else
for i in to_resolve'range loop
sum := sum + bit'pos(to_resolve(i)) ;
end loop ;
return bit'val(integer'pos(sum) mod
(bit'pos(bit'high) + 1)) ;
end if ;
end bf_bit ;
--
-- severity_level
function bf_severity_level(to_resolve : severity_level_vector)
return severity_level is
variable sum : integer := 0 ;
begin
if to_resolve'length = 0 then
return severity_level'left ;
else
for i in to_resolve'range loop
sum := sum + severity_level'pos(to_resolve(i)) ;
end loop ;
return severity_level'val(integer'pos(sum) mod
(severity_level'pos(severity_level'high) + 1)) ;
end if ;
end bf_severity_level ;
--
-- character
function bf_character(to_resolve : string) return character is
variable sum : integer := 0 ;
begin
if to_resolve'length = 0 then
return character'left ;
else
for i in to_resolve'range loop
sum := sum + character'pos(to_resolve(i)) ;
end loop ;
return character'val(integer'pos(sum) mod
(character'pos(character'high) + 1)) ;
end if ;
end bf_character ;
--
--
-- user defined enumeration
function bf_enum1(to_resolve : enum1_vector) return st_enum1 is
variable sum : integer := 0 ;
begin
if to_resolve'length = 0 then
return st_enum1'left ;
else
for i in to_resolve'range loop
sum := sum + t_enum1'pos(to_resolve(i)) ;
end loop ;
return t_enum1'val(integer'pos(sum) mod
(t_enum1'pos(t_enum1'high) + 1)) ;
end if ;
end bf_enum1 ;
--
--
-- integer types
-- predefined
function bf_integer(to_resolve : integer_vector) return integer is
variable sum : integer := 0 ;
begin
if to_resolve'length = 0 then
return integer'left ;
else
for i in to_resolve'range loop
sum := sum + integer'pos(to_resolve(i)) ;
end loop ;
return sum ;
end if ;
end bf_integer ;
--
--
-- user defined integer type
function bf_int1(to_resolve : int1_vector) return st_int1 is
variable sum : integer := 0 ;
begin
if to_resolve'length = 0 then
return st_int1'left ;
else
for i in to_resolve'range loop
sum := sum + t_int1'pos(to_resolve(i)) ;
end loop ;
return t_int1'val(integer'pos(sum) mod
(t_int1'pos(t_int1'high) + 1)) ;
end if ;
end bf_int1 ;
--
--
-- physical types
-- predefined
function bf_time(to_resolve : time_vector) return time is
variable sum : time := 0 fs;
begin
if to_resolve'length = 0 then
return time'left ;
else
for i in to_resolve'range loop
sum := sum + to_resolve(i) ;
end loop ;
return sum ;
end if ;
end bf_time ;
--
--
-- user defined physical type
function bf_phys1(to_resolve : phys1_vector) return st_phys1 is
variable sum : integer := 0 ;
begin
if to_resolve'length = 0 then
return c_st_phys1_1 ;
else
for i in to_resolve'range loop
sum := sum + t_phys1'pos(to_resolve(i)) ;
end loop ;
return t_phys1'val(integer'pos(sum) mod
(t_phys1'pos(t_phys1'high) + 1)) ;
end if ;
end bf_phys1 ;
--
--
-- floating point types
-- predefined
function bf_real(to_resolve : real_vector) return real is
variable sum : real := 0.0 ;
begin
if to_resolve'length = 0 then
return real'left ;
else
for i in to_resolve'range loop
sum := sum + to_resolve(i) ;
end loop ;
return sum ;
end if ;
end bf_real ;
--
--
-- user defined floating type
function bf_real1(to_resolve : real1_vector) return st_real1 is
variable sum : t_real1 := 0.0 ;
begin
if to_resolve'length = 0 then
return c_st_real1_1 ;
else
for i in to_resolve'range loop
sum := sum + to_resolve(i) ;
end loop ;
return sum ;
end if ;
end bf_real1 ;
--
--
-- composite types
--
-- simple record
function bf_rec1(to_resolve : rec1_vector) return st_rec1 is
variable f1array : integer_vector (to_resolve'range) ;
variable f2array : time_vector (to_resolve'range) ;
variable f3array : boolean_vector (to_resolve'range) ;
variable f4array : real_vector (to_resolve'range) ;
variable result : st_rec1 ;
begin
if to_resolve'length = 0 then
return c_st_rec1_1 ;
else
for i in to_resolve'range loop
f1array(i) := to_resolve(i).f1 ;
f2array(i) := to_resolve(i).f2 ;
f3array(i) := to_resolve(i).f3 ;
f4array(i) := to_resolve(i).f4 ;
end loop ;
result.f1 := bf_integer(f1array) ;
result.f2 := bf_time(f2array) ;
result.f3 := bf_boolean(f3array) ;
result.f4 := bf_real(f4array) ;
return result ;
end if ;
end bf_rec1 ;
--
--
-- more complex record
function bf_rec2(to_resolve : rec2_vector) return st_rec2 is
variable f1array : boolean_vector (to_resolve'range) ;
variable f2array : rec1_vector (to_resolve'range) ;
variable f3array : time_vector (to_resolve'range) ;
variable result : st_rec2 ;
begin
if to_resolve'length = 0 then
return c_st_rec2_1 ;
else
for i in to_resolve'range loop
f1array(i) := to_resolve(i).f1 ;
f2array(i) := to_resolve(i).f2 ;
f3array(i) := to_resolve(i).f3 ;
end loop ;
result.f1 := bf_boolean(f1array) ;
result.f2 := bf_rec1(f2array) ;
result.f3 := bf_time(f3array) ;
return result ;
end if ;
end bf_rec2 ;
--
--
-- simple array
function bf_arr1(to_resolve : arr1_vector) return st_arr1 is
variable temp : int1_vector (to_resolve'range) ;
variable result : st_arr1 ;
begin
if to_resolve'length = 0 then
return c_st_arr1_1 ;
else
for i in st_arr1'range loop
for j in to_resolve'range(1) loop
temp(j) := to_resolve(j)(i) ;
end loop;
result(i) := bf_int1(temp) ;
end loop ;
return result ;
end if ;
end bf_arr1 ;
--
--
-- more complex array
function bf_arr2(to_resolve : arr2_vector) return st_arr2 is
variable temp : arr1_vector (to_resolve'range) ;
variable result : st_arr2 ;
begin
if to_resolve'length = 0 then
return c_st_arr2_1 ;
else
for i in st_arr2'range(1) loop
for j in st_arr2'range(2) loop
for k in to_resolve'range loop
temp(k) := to_resolve(k)(i,j) ;
end loop ;
result(i, j) := bf_arr1(temp) ;
end loop ;
end loop ;
return result ;
end if ;
end bf_arr2 ;
--
--
-- most complex record
function bf_rec3(to_resolve : rec3_vector) return st_rec3 is
variable f1array : boolean_vector (to_resolve'range) ;
variable f2array : rec2_vector (to_resolve'range) ;
variable f3array : arr2_vector (to_resolve'range) ;
variable result : st_rec3 ;
begin
if to_resolve'length = 0 then
return c_st_rec3_1 ;
else
for i in to_resolve'range loop
f1array(i) := to_resolve(i).f1 ;
f2array(i) := to_resolve(i).f2 ;
f3array(i) := to_resolve(i).f3 ;
end loop ;
result.f1 := bf_boolean(f1array) ;
result.f2 := bf_rec2(f2array) ;
result.f3 := bf_arr2(f3array) ;
return result ;
end if ;
end bf_rec3 ;
--
--
-- most complex array
function bf_arr3(to_resolve : arr3_vector) return st_arr3 is
variable temp : rec3_vector (to_resolve'range) ;
variable result : st_arr3 ;
begin
if to_resolve'length = 0 then
return c_st_arr3_1 ;
else
for i in st_arr3'range(1) loop
for j in st_arr3'range(2) loop
for k in to_resolve'range loop
temp(k) := to_resolve(k)(i,j) ;
end loop ;
result(i, j) := bf_rec3(temp) ;
end loop ;
end loop ;
return result ;
end if ;
end bf_arr3 ;
--
type a_bit_vector is access bit_vector ;
variable av_bit_vector_1, av_bit_vector_2 : a_bit_vector
:= new st_bit_vector ;
type a_string is access string ;
variable av_string_1, av_string_2 : a_string
:= new st_string ;
type a_t_rec1 is access t_rec1 ;
variable av_t_rec1_1, av_t_rec1_2 : a_t_rec1
:= new st_rec1 ;
type a_st_rec1 is access st_rec1 ;
variable av_st_rec1_1, av_st_rec1_2 : a_st_rec1
:= new st_rec1 ;
type a_t_rec2 is access t_rec2 ;
variable av_t_rec2_1, av_t_rec2_2 : a_t_rec2
:= new st_rec2 ;
type a_st_rec2 is access st_rec2 ;
variable av_st_rec2_1, av_st_rec2_2 : a_st_rec2
:= new st_rec2 ;
type a_t_rec3 is access t_rec3 ;
variable av_t_rec3_1, av_t_rec3_2 : a_t_rec3
:= new st_rec3 ;
type a_st_rec3 is access st_rec3 ;
variable av_st_rec3_1, av_st_rec3_2 : a_st_rec3
:= new st_rec3 ;
type a_t_arr1 is access t_arr1 ;
variable av_t_arr1_1, av_t_arr1_2 : a_t_arr1
:= new st_arr1 ;
type a_st_arr1 is access st_arr1 ;
variable av_st_arr1_1, av_st_arr1_2 : a_st_arr1
:= new st_arr1 ;
type a_t_arr2 is access t_arr2 ;
variable av_t_arr2_1, av_t_arr2_2 : a_t_arr2
:= new st_arr2 ;
type a_st_arr2 is access st_arr2 ;
variable av_st_arr2_1, av_st_arr2_2 : a_st_arr2
:= new st_arr2 ;
type a_t_arr3 is access t_arr3 ;
variable av_t_arr3_1, av_t_arr3_2 : a_t_arr3
:= new st_arr3 ;
type a_st_arr3 is access st_arr3 ;
variable av_st_arr3_1, av_st_arr3_2 : a_st_arr3
:= new st_arr3 ;
begin
av_bit_vector_1 := new st_bit_vector'(c_st_bit_vector_1) ;
av_string_1 := new st_string'(c_st_string_1) ;
av_t_rec1_1 := new st_rec1'(c_st_rec1_1) ;
av_st_rec1_1 := new st_rec1'(c_st_rec1_1) ;
av_t_rec2_1 := new st_rec2'(c_st_rec2_1) ;
av_st_rec2_1 := new st_rec2'(c_st_rec2_1) ;
av_t_rec3_1 := new st_rec3'(c_st_rec3_1) ;
av_st_rec3_1 := new st_rec3'(c_st_rec3_1) ;
av_t_arr1_1 := new st_arr1'(c_st_arr1_1) ;
av_st_arr1_1 := new st_arr1'(c_st_arr1_1) ;
av_t_arr2_1 := new st_arr2'(c_st_arr2_1) ;
av_st_arr2_1 := new st_arr2'(c_st_arr2_1) ;
av_t_arr3_1 := new st_arr3'(c_st_arr3_1) ;
av_st_arr3_1 := new st_arr3'(c_st_arr3_1) ;
correct := correct and av_bit_vector_1.all
= c_st_bit_vector_1 ;
correct := correct and av_string_1.all
= c_st_string_1 ;
correct := correct and av_t_rec1_1.all
= c_st_rec1_1 ;
correct := correct and av_st_rec1_1.all
= c_st_rec1_1 ;
correct := correct and av_t_rec2_1.all
= c_st_rec2_1 ;
correct := correct and av_st_rec2_1.all
= c_st_rec2_1 ;
correct := correct and av_t_rec3_1.all
= c_st_rec3_1 ;
correct := correct and av_st_rec3_1.all
= c_st_rec3_1 ;
correct := correct and av_t_arr1_1.all
= c_st_arr1_1 ;
correct := correct and av_st_arr1_1.all
= c_st_arr1_1 ;
correct := correct and av_t_arr2_1.all
= c_st_arr2_1 ;
correct := correct and av_st_arr2_1.all
= c_st_arr2_1 ;
correct := correct and av_t_arr3_1.all
= c_st_arr3_1 ;
correct := correct and av_st_arr3_1.all
= c_st_arr3_1 ;
av_bit_vector_1.all := c_st_bit_vector_2 ;
av_string_1.all := c_st_string_2 ;
av_t_rec1_1.all := c_st_rec1_2 ;
av_st_rec1_1.all := c_st_rec1_2 ;
av_t_rec2_1.all := c_st_rec2_2 ;
av_st_rec2_1.all := c_st_rec2_2 ;
av_t_rec3_1.all := c_st_rec3_2 ;
av_st_rec3_1.all := c_st_rec3_2 ;
av_t_arr1_1.all := c_st_arr1_2 ;
av_st_arr1_1.all := c_st_arr1_2 ;
av_t_arr2_1.all := c_st_arr2_2 ;
av_st_arr2_1.all := c_st_arr2_2 ;
av_t_arr3_1.all := c_st_arr3_2 ;
av_st_arr3_1.all := c_st_arr3_2 ;
correct := correct and av_bit_vector_1.all
= c_st_bit_vector_2 ;
correct := correct and av_string_1.all
= c_st_string_2 ;
correct := correct and av_t_rec1_1.all
= c_st_rec1_2 ;
correct := correct and av_st_rec1_1.all
= c_st_rec1_2 ;
correct := correct and av_t_rec2_1.all
= c_st_rec2_2 ;
correct := correct and av_st_rec2_1.all
= c_st_rec2_2 ;
correct := correct and av_t_rec3_1.all
= c_st_rec3_2 ;
correct := correct and av_st_rec3_1.all
= c_st_rec3_2 ;
correct := correct and av_t_arr1_1.all
= c_st_arr1_2 ;
correct := correct and av_st_arr1_1.all
= c_st_arr1_2 ;
correct := correct and av_t_arr2_1.all
= c_st_arr2_2 ;
correct := correct and av_st_arr2_1.all
= c_st_arr2_2 ;
correct := correct and av_t_arr3_1.all
= c_st_arr3_2 ;
correct := correct and av_st_arr3_1.all
= c_st_arr3_2 ;
test_report ( "ARCH00591" ,
"Variable declarations - composite dynamic access subtypes" ,
correct) ;
end p1 ;
begin
process
begin
p1 ;
wait ;
end process ;
end ARCH00591 ;
--
entity ENT00591_Test_Bench is
end ENT00591_Test_Bench ;
--
architecture ARCH00591_Test_Bench of ENT00591_Test_Bench is
begin
L1:
block
component UUT
end component ;
for CIS1 : UUT use entity WORK.E00000 ( ARCH00591 ) ;
begin
CIS1 : UUT ;
end block L1 ;
end ARCH00591_Test_Bench ;
| gpl-3.0 | 05eab49ce527d7d5bc566cff6c712f50 | 0.540605 | 3.090813 | false | false | false | false |
grwlf/vsim | vhdl_ct/ct00441.vhd | 1 | 1,909 | -- NEED RESULT: ARCH00441: Allowable replacement of characters passed
-------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
-------------------------------------------------------------------------------
--
-- TEST NAME:
--
-- CT00441
--
-- AUTHOR:
--
-- D. Hyman
--
-- TEST OBJECTIVES:
--
-- 13.10 (1)
-- 13.10 (2)
--
-- DESIGN UNIT ORDERING:
--
-- E00000(ARCH00441)
-- ENT00441_Test_Bench(ARCH00441_Test_Bench)
--
-- REVISION HISTORY:
--
-- 4-AUG-1987 - initial revision
--
-- NOTES:
--
-- self-checking
--
--
use WORK.STANDARD_TYPES.all ;
architecture ARCH00441 of E00000 is
begin
P :
process
variable ch : character := 'B' ;
variable i : integer := 0 ;
constant cstr1 : string := "A" ;
constant cstr2 : string := "abc%xyz" ;
begin
case ch is
when 'a' | 'b' | 'c' =>
i := 200 ;
when 'A' ! 'B' ! 'C' =>
i := 201 ;
when 'w' | 'x' | 'y' | 'z' =>
i := 300 ;
when 'W' ! 'X' ! 'Y' ! 'Z' =>
i := 301 ;
when others =>
i := 400 ;
end case ;
test_report ( "ARCH00441" ,
"Allowable replacement of characters" ,
(i = 201) and
(16:9ABCDEF: = 16#9ABCDEF#) and
(cstr1 = %A%) and
(B"101" = B%101%) and
(cstr2 = %abc%%xyz%)
) ;
wait ;
end process P ;
end ARCH00441 ;
entity ENT00441_Test_Bench is
end ENT00441_Test_Bench ;
architecture ARCH00441_Test_Bench of ENT00441_Test_Bench is
begin
L1:
block
component UUT
end component ;
for CIS1 : UUT use entity WORK.E00000 ( ARCH00441 ) ;
begin
CIS1 : UUT ;
end block L1 ;
end ARCH00441_Test_Bench ;
| gpl-3.0 | 0c08b5e7eb56abd2ee2c47ffcf8ff0db | 0.44945 | 3.274443 | false | true | false | false |
grwlf/vsim | vhdl_ct/ct00454.vhd | 1 | 4,998 | -------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
-------------------------------------------------------------------------------
--
-- TEST NAME:
--
-- CT00454
--
-- AUTHOR:
--
-- A. Wilmot
--
-- TEST OBJECTIVES:
--
-- 7.2.4 (6)
-- 7.2.4 (11)
-- 7.2.4 (12)
-- 7.2.4 (13)
--
-- DESIGN UNIT ORDERING:
--
-- ENT00454(ARCH00454)
-- ENT00454_Test_Bench(ARCH00454_Test_Bench)
--
-- REVISION HISTORY:
--
-- 29-JUL-1987 - initial revision
--
-- NOTES:
--
-- self-checking
--
use WORK.STANDARD_TYPES ;
use WORK.ARITHMETIC.ALL ;
entity ENT00454 is
generic (
i_real_1 : real := c_real_1 ;
i_real_2 : real := c_real_2 ;
i_realt_1 : realt := c_realt_1 ;
i_realt_2 : realt := c_realt_2 ;
i_realst_1 : realst := c_realst_1 ;
i_realst_2 : realst := c_realst_2 ;
i_time_1 : time := c_time_1 ;
i_time_2 : time := c_time_2 ;
i_t_phys_1 : t_phys := c_t_phys_1 ;
i_t_phys_2 : t_phys := c_t_phys_2 ;
i_st_phys_1 : st_phys := c_st_phys_1 ;
i_st_phys_2 : st_phys := c_st_phys_2
) ;
constant c2_time_1 : time :=
i_time_1 * i_realst_1 + i_time_2 * i_real_1 -
i_realst_1 * i_time_1 - i_real_1 * i_time_2 ;
constant c2_t_phys_1 : t_phys :=
i_t_phys_1 * i_realst_1 +
i_t_phys_1 * i_realt_2 + i_t_phys_2 * c_real_2 +
i_realt_1 * c_t_phys_1 + i_realst_2 * i_t_phys_1 +
i_realst_2 * i_t_phys_2 + i_real_2 * i_t_phys_2 ;
constant c2_st_phys_1 : st_phys :=
-( i_st_phys_1 * i_realst_1 +
i_t_phys_1 * i_realt_2 + i_st_phys_2 * c_real_2 +
i_realt_1 * c_t_phys_1 + i_realst_2 * i_t_phys_2 +
c_real_1 * i_st_phys_2 + i_real_2 * i_t_phys_2) ;
end ENT00454 ;
architecture ARCH00454 of ENT00454 is
begin
process
variable bool : boolean := true ;
variable cons_correct, gen_correct, dyn_correct : boolean := true ;
--
variable v_time_1, v2_time_1 : time := i_time_1 ;
variable v_time_2, v2_time_2 : time := i_time_2 ;
variable v_t_phys_1, v2_t_phys_1 : t_phys := i_t_phys_1 ;
variable v_t_phys_2, v2_t_phys_2 : t_phys := i_t_phys_2 ;
variable v_st_phys_1, v2_st_phys_1 : st_phys := i_st_phys_1 ;
variable v_st_phys_2, v2_st_phys_2 : st_phys := i_st_phys_2 ;
variable v_real_1 : real := i_real_1 ;
variable v_real_2 : real := i_real_2 ;
variable v_realt_1 : realt := i_realt_1 ;
variable v_realt_2 : realt := i_realt_2 ;
variable v_realst_1 : realst := i_realst_1 ;
variable v_realst_2 : realst := i_realst_2 ;
--
begin
-- static expression
case bool is
when (
c_time_1 * c_realst_1 + c_time_2 * c_real_1 -
c_realst_1 * c_time_1 - c_real_1 * c_time_2 = 0 ns and --xx and
c_t_phys_1 * c_realst_1 +
c_t_phys_1 * c_realt_2 + c_t_phys_2 * c_real_2 +
c_realt_1 * c_t_phys_1 + c_realst_2 * c_t_phys_1 +
c_realst_2 * c_t_phys_2 + c_real_2 * c_t_phys_2 = 52394 ones and --xx and
-( c_st_phys_1 * c_realst_1 +
c_t_phys_1 * c_realt_2 + c_st_phys_2 * c_real_2 +
c_realt_1 * c_t_phys_1 + c_realst_2 * c_t_phys_2 +
c_real_1 * c_st_phys_2 + c_real_2 * c_t_phys_2 ) = -249374 ones --xx
) =>
null ;
when others =>
cons_correct := false ;
end case ;
-- generic expression
gen_correct := c2_time_1 = 0 ns and --xx and
c2_t_phys_1 = 52394 ones and --xx and
c2_st_phys_1 = -249374 ones ; --xx ;
-- dynamic expression
v2_time_1 :=
v_time_1 * i_realst_1 + v_time_2 * i_real_1 -
v_realst_1 * c_time_1 - v_real_1 * i_time_2 ;
v2_t_phys_1 :=
v_t_phys_1 * v_realst_1 +
v_t_phys_1 * v_realt_2 + v_t_phys_2 * c_real_2 +
v_realt_1 * c_t_phys_1 + v_realst_2 * v_t_phys_1 +
i_realst_2 * v_t_phys_2 + v_real_2 * v_t_phys_2 ;
v2_st_phys_1 :=
-( v_st_phys_1 * v_realst_1 +
v_t_phys_1 * v_realt_2 + v_st_phys_2 * c_real_2 +
v_realt_1 * c_t_phys_1 + v_realst_2 * v_t_phys_2 +
i_real_1 * v_st_phys_2 + v_real_2 * v_t_phys_2) ;
dyn_correct := v2_time_1 = 0 ns and --xx and
v2_t_phys_1 = 52394 ones and --xx and
v2_st_phys_1 = -249374 ones ; --xx ;
STANDARD_TYPES.test_report ( "ARCH00454" ,
"* predefined for physical and real types" ,
dyn_correct and cons_correct and gen_correct ) ;
wait ;
end process ;
end ARCH00454 ;
entity ENT00454_Test_Bench is
end ENT00454_Test_Bench ;
architecture ARCH00454_Test_Bench of ENT00454_Test_Bench is
begin
L1:
block
component UUT
end component ;
for CIS1 : UUT use entity WORK.ENT00454 ( ARCH00454 ) ;
begin
CIS1 : UUT ;
end block L1 ;
end ARCH00454_Test_Bench ;
| gpl-3.0 | 1836933de3417549944b81410ae78ba1 | 0.501 | 2.560451 | false | true | false | false |
grwlf/vsim | vhdl/IEEE/math_real-body.vhdl | 2 | 12,493 | ---------------------------------------------------------------
--
-- This source file may be used and distributed without restriction.
-- No declarations or definitions shall be added to this package.
-- This package cannot be sold or distributed for profit.
--
-- ****************************************************************
-- * *
-- * W A R N I N G *
-- * *
-- * This DRAFT version IS NOT endorsed or approved by IEEE *
-- * *
-- ****************************************************************
--
-- Title: PACKAGE BODY MATH_REAL
--
-- Library: This package shall be compiled into a library
-- symbolically named IEEE.
--
-- Purpose: VHDL declarations for mathematical package MATH_REAL
-- which contains common real constants, common real
-- functions, and real trascendental functions.
--
-- Author: IEEE VHDL Math Package Study Group
--
-- Notes:
-- The package body shall be considered the formal definition of
-- the semantics of this package. Tool developers may choose to implement
-- the package body in the most efficient manner available to them.
--
-- Source code and algorithms for this package body comes from the
-- following sources:
-- IEEE VHDL Math Package Study Group participants,
-- U. of Mississippi, Mentor Graphics, Synopsys,
-- Viewlogic/Vantage, Communications of the ACM (June 1988, Vol
-- 31, Number 6, pp. 747, Pierre L'Ecuyer, Efficient and Portable
-- Random Number Generators), Handbook of Mathematical Functions
-- by Milton Abramowitz and Irene A. Stegun (Dover).
--
-- History:
-- Version 0.1 Jose A. Torres 4/23/93 First draft
-- Version 0.2 Jose A. Torres 5/28/93 Fixed potentially illegal code
--
-- GHDL history
-- 2005-04-07 Initial version.
-- 2005-12-23 I. Curtis : overhaul of log functions to bring in line
-- with ieee standard
-------------------------------------------------------------
Library IEEE;
Package body MATH_REAL is
--
-- non-trascendental functions
--
function SIGN (X: real ) return real is
-- returns 1.0 if X > 0.0; 0.0 if X == 0.0; -1.0 if X < 0.0
begin
assert false severity failure;
end SIGN;
function CEIL (X : real ) return real is
begin
assert false severity failure;
end CEIL;
function FLOOR (X : real ) return real is
begin
assert false severity failure;
end FLOOR;
function ROUND (X : real ) return real is
begin
assert false severity failure;
end ROUND;
function FMAX (X, Y : real ) return real is
begin
assert false severity failure;
end FMAX;
function FMIN (X, Y : real ) return real is
begin
assert false severity failure;
end FMIN;
--
-- Pseudo-random number generators
--
procedure UNIFORM(variable Seed1,Seed2:inout integer;variable X:out real) is
-- returns a pseudo-random number with uniform distribution in the
-- interval (0.0, 1.0).
-- Before the first call to UNIFORM, the seed values (Seed1, Seed2) must
-- be initialized to values in the range [1, 2147483562] and
-- [1, 2147483398] respectively. The seed values are modified after
-- each call to UNIFORM.
-- This random number generator is portable for 32-bit computers, and
-- it has period ~2.30584*(10**18) for each set of seed values.
--
-- For VHDL-1992, the seeds will be global variables, functions to
-- initialize their values (INIT_SEED) will be provided, and the UNIFORM
-- procedure call will be modified accordingly.
variable z, k: integer;
begin
k := Seed1/53668;
Seed1 := 40014 * (Seed1 - k * 53668) - k * 12211;
if Seed1 < 0 then
Seed1 := Seed1 + 2147483563;
end if;
k := Seed2/52774;
Seed2 := 40692 * (Seed2 - k * 52774) - k * 3791;
if Seed2 < 0 then
Seed2 := Seed2 + 2147483399;
end if;
z := Seed1 - Seed2;
if z < 1 then
z := z + 2147483562;
end if;
X := REAL(Z)*4.656613e-10;
end UNIFORM;
function SRAND (seed: in integer ) return integer is
begin
assert false severity failure;
end SRAND;
function RAND return integer is
begin
assert false severity failure;
end RAND;
function GET_RAND_MAX return integer is
-- The value this function returns should be the same as
-- RAND_MAX in /usr/include/stdlib.h
begin
assert false
report "Be sure to update GET_RAND_MAX in mathpack.vhd"
severity note;
return 2147483647; -- i386 linux
end GET_RAND_MAX;
--
-- trascendental and trigonometric functions
--
function c_sqrt (x : real ) return real;
attribute foreign of c_sqrt : function is "VHPIDIRECT sqrt";
function c_sqrt (x : real ) return real is
begin
assert false severity failure;
end c_sqrt;
function SQRT (X : real ) return real is
begin
-- check validity of argument
if ( X < 0.0 ) then
assert false report "X < 0 in SQRT(X)"
severity ERROR;
return (0.0);
end if;
return c_sqrt(X);
end SQRT;
function CBRT (X : real ) return real is
begin
assert false severity failure;
end CBRT;
function "**" (X : integer; Y : real) return real is
-- returns Y power of X ==> X**Y;
-- error if X = 0 and Y <= 0.0
-- error if X < 0 and Y does not have an integer value
begin
-- check validity of argument
if ( X = 0 ) and ( Y <= 0.0 ) then
assert false report "X = 0 and Y <= 0.0 in X**Y"
severity ERROR;
return (0.0);
end if;
if ( X < 0 ) and ( Y /= REAL(INTEGER(Y)) ) then
assert false
report "X < 0 and Y \= integer in X**Y"
severity ERROR;
return (0.0);
end if;
-- compute the result
return EXP (Y * LOG (REAL(X)));
end "**";
function "**" (X : real; Y : real) return real is
-- returns Y power of X ==> X**Y;
-- error if X = 0.0 and Y <= 0.0
-- error if X < 0.0 and Y does not have an integer value
begin
-- check validity of argument
if ( X = 0.0 ) and ( Y <= 0.0 ) then
assert false report "X = 0.0 and Y <= 0.0 in X**Y"
severity ERROR;
return (0.0);
end if;
if ( X < 0.0 ) and ( Y /= REAL(INTEGER(Y)) ) then
assert false report "X < 0.0 and Y \= integer in X**Y"
severity ERROR;
return (0.0);
end if;
-- compute the result
return EXP (Y * LOG (X));
end "**";
function EXP (X : real ) return real is
begin
assert false severity failure;
end EXP;
function c_log (x : real ) return real;
attribute foreign of c_log : function is "VHPIDIRECT log";
function c_log (x : real ) return real is
begin
assert false severity failure;
end c_log;
function LOG (X : real ) return real is
-- returns natural logarithm of X; X > 0
--
-- This function computes the exponential using the following series:
-- log(x) = 2[ (x-1)/(x+1) + (((x-1)/(x+1))**3)/3.0 + ...] ; x > 0
--
begin
-- check validity of argument
if ( x <= 0.0 ) then
assert false report "X <= 0 in LOG(X)"
severity ERROR;
return(REAL'LOW);
end if;
return c_log(x);
end LOG;
function LOG (X : in real; BASE: in real) return real is
-- returns logarithm base BASE of X; X > 0
begin
-- check validity of argument
if ( BASE <= 0.0 ) or ( x <= 0.0 ) then
assert false report "BASE <= 0.0 or X <= 0.0 in LOG(BASE, X)"
severity ERROR;
return(REAL'LOW);
end if;
-- compute the value
return (LOG(X)/LOG(BASE));
end LOG;
function LOG2 (X : in real) return real is
-- returns logarithm BASE 2 of X; X > 0
begin
return LOG(X) / MATH_LOG_OF_2;
end LOG2;
function LOG10 (X : in real) return real is
-- returns logarithm BASE 10 of X; X > 0
begin
return LOG(X) / MATH_LOG_OF_10;
end LOG10;
function SIN (X : real ) return real is
begin
assert false severity failure;
end SIN;
function COS (x : REAL) return REAL is
begin
assert false severity failure;
end COS;
function TAN (x : REAL) return REAL is
begin
assert false severity failure;
end TAN;
function c_asin (x : real ) return real;
attribute foreign of c_asin : function is "VHPIDIRECT asin";
function c_asin (x : real ) return real is
begin
assert false severity failure;
end c_asin;
function ASIN (x : real ) return real is
-- returns -PI/2 < asin X < PI/2; | X | <= 1
begin
if abs x > 1.0 then
assert false
report "Out of range parameter passed to ASIN"
severity ERROR;
return x;
else
return c_asin(x);
end if;
end ASIN;
function c_acos (x : real ) return real;
attribute foreign of c_acos : function is "VHPIDIRECT acos";
function c_acos (x : real ) return real is
begin
assert false severity failure;
end c_acos;
function ACOS (x : REAL) return REAL is
-- returns 0 < acos X < PI; | X | <= 1
begin
if abs x > 1.0 then
assert false
report "Out of range parameter passed to ACOS"
severity ERROR;
return x;
else
return c_acos(x);
end if;
end ACOS;
function ATAN (x : REAL) return REAL is
-- returns -PI/2 < atan X < PI/2
begin
assert false severity failure;
end ATAN;
function c_atan2 (x : real; y : real) return real;
attribute foreign of c_atan2 : function is "VHPIDIRECT atan2";
function c_atan2 (x : real; y: real) return real is
begin
assert false severity failure;
end c_atan2;
function ATAN2 (x : REAL; y : REAL) return REAL is
-- returns atan (X/Y); -PI < atan2(X,Y) < PI; Y /= 0.0
begin
if y = 0.0 and x = 0.0 then
assert false
report "atan2(0.0, 0.0) is undetermined, returned 0,0"
severity NOTE;
return 0.0;
else
return c_atan2(x,y);
end if;
end ATAN2;
function SINH (X : real) return real is
-- hyperbolic sine; returns (e**X - e**(-X))/2
begin
assert false severity failure;
end SINH;
function COSH (X : real) return real is
-- hyperbolic cosine; returns (e**X + e**(-X))/2
begin
assert false severity failure;
end COSH;
function TANH (X : real) return real is
-- hyperbolic tangent; -- returns (e**X - e**(-X))/(e**X + e**(-X))
begin
assert false severity failure;
end TANH;
function ASINH (X : real) return real is
-- returns ln( X + sqrt( X**2 + 1))
begin
assert false severity failure;
end ASINH;
function c_acosh (x : real ) return real;
attribute foreign of c_acosh : function is "VHPIDIRECT acosh";
function c_acosh (x : real ) return real is
begin
assert false severity failure;
end c_acosh;
function ACOSH (X : real) return real is
-- returns ln( X + sqrt( X**2 - 1)); X >= 1
begin
if abs x >= 1.0 then
assert false report "Out of range parameter passed to ACOSH"
severity ERROR;
return x;
end if;
return c_acosh(x);
end ACOSH;
function c_atanh (x : real ) return real;
attribute foreign of c_atanh : function is "VHPIDIRECT atanh";
function c_atanh (x : real ) return real is
begin
assert false severity failure;
end c_atanh;
function ATANH (X : real) return real is
-- returns (ln( (1 + X)/(1 - X)))/2 ; | X | < 1
begin
if abs x < 1.0 then
assert false report "Out of range parameter passed to ATANH"
severity ERROR;
return x;
end if;
return c_atanh(x);
end ATANH;
end MATH_REAL;
| gpl-3.0 | aa4ac1a58a2ab6533f76fb71cacbfd87 | 0.55375 | 3.884639 | false | false | false | false |
dcliche/mdsynth | rtl/src/sound/dac.vhd | 1 | 2,518 | -- MDSynth Sound Chip
--
-- Copyright (c) 2012, Meldora Inc.
-- All rights reserved.
--
-- Redistribution and use in source and binary forms, with or without modification, are permitted provided that the
-- following conditions are met:
--
-- * Redistributions of source code must retain the above copyright notice, this list of conditions and the
-- following disclaimer.
-- * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the
-- following disclaimer in the documentation and/or other materials provided with the distribution.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
-- INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-- DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
-- SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-- SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
-- WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
-- USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-- 10-bits DAC
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity dac is
generic(
MSBI : integer := 9
);
port ( clk: in std_logic;
dac_in: in std_logic_vector(MSBI downto 0);
reset: in std_logic;
dac_out: out std_logic);
end entity dac;
architecture dac_arch of dac is
signal delta_adder : std_logic_vector(MSBI+2 downto 0);
signal sigma_adder : std_logic_vector(MSBI+2 downto 0);
signal sigma_latch : std_logic_vector(MSBI+2 downto 0);
signal delta_b : std_logic_vector(MSBI+2 downto 0);
begin
delta_b(MSBI+2 downto MSBI+1) <= sigma_latch(MSBI+2) & sigma_latch(MSBI+2);
delta_b(MSBI downto 0) <= (others => '0');
delta_adder <= std_logic_vector(unsigned(dac_in) + unsigned(delta_b));
sigma_adder <= std_logic_vector(unsigned(delta_adder) + unsigned(sigma_latch));
process (clk, reset)
begin
if (reset = '1') then
sigma_latch <= ('1', others => '0');
dac_out <= '0';
elsif (rising_edge(clk)) then
sigma_latch <= sigma_adder;
dac_out <= sigma_latch(MSBI+2);
end if;
end process;
end architecture dac_arch;
| gpl-3.0 | 6c976d527ccf529005a08fb01ad930dc | 0.711279 | 3.702941 | false | false | false | false |
TWW12/lzw | ip_repo/axi_compression_1.0/src/dictionary_4.vhd | 4 | 7,518 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;
entity dictionary_4 is
port (
clk : in std_logic;
rst : in std_logic;
start_search : in std_logic;
search_entry : in std_logic_vector(19 downto 0);
--Write enable & entries
wr_en : in std_logic;
wr_entry : in std_logic_vector(19 downto 0);
--Outputs
prefix : out std_logic_vector(11 downto 0);
entry_found : out std_logic;
search_completed : out std_logic;
dictionary_full : out std_logic);
end dictionary_4;
architecture Behavioral of dictionary_4 is
signal wr_addr_shift : std_logic_vector(11 downto 0);
signal search_completed_i : std_logic;
signal full : std_logic;
signal wr_addr : std_logic_vector(11 downto 0);
signal halt_search : std_logic;
signal block0_wr_en : std_logic;
signal block0_prefix : std_logic_vector(9 downto 0);
signal block0_entry_found : std_logic;
signal block0_search_completed : std_logic;
signal block1_wr_en : std_logic;
signal block1_prefix : std_logic_vector(9 downto 0);
signal block1_entry_found : std_logic;
signal block1_search_completed : std_logic;
signal block2_wr_en : std_logic;
signal block2_prefix : std_logic_vector(9 downto 0);
signal block2_entry_found : std_logic;
signal block2_search_completed : std_logic;
signal block3_wr_en : std_logic;
signal block3_prefix : std_logic_vector(9 downto 0);
signal block3_entry_found : std_logic;
signal block3_search_completed : std_logic;
--Registered signals to improve timing
signal r_block0_wr_en : std_logic;
signal r_block1_wr_en : std_logic;
signal r_block2_wr_en : std_logic;
signal r_block3_wr_en : std_logic;
signal r_start_search : std_logic;
signal r_search_entry : std_logic_vector(19 downto 0);
signal r_wr_addr : std_logic_vector(11 downto 0);
signal r_wr_entry : std_logic_vector(19 downto 0);
begin
process(clk,rst)
begin
if rst = '1' then
r_block0_wr_en <= '0';
r_block1_wr_en <= '0';
r_block2_wr_en <= '0';
r_block3_wr_en <= '0';
r_wr_addr <= (others => '0');
r_wr_entry <= (others => '0');
elsif rising_edge(clk) then
r_wr_addr <= wr_addr;
r_wr_entry <= wr_entry;
r_block0_wr_en <= block0_wr_en;
r_block1_wr_en <= block1_wr_en;
r_block2_wr_en <= block2_wr_en;
r_block3_wr_en <= block3_wr_en;
end if;
end process;
wr_addr_shift(11 downto 2) <= wr_addr(9 downto 0);
wr_addr_shift(1 downto 0) <= "00";
--Combines all signals from blocks
search_completed <= search_completed_i;
process(clk,rst)
begin
if rst = '1' then
block1_wr_en <= '0';
block0_wr_en <= '0';
block2_wr_en <= '0';
block3_wr_en <= '0';
search_completed_i <= '0';
entry_found <= '0';
prefix <= x"000";
elsif rising_edge(clk) then
block3_wr_en <= not wr_addr(0) and wr_addr(1) and wr_en;
block0_wr_en <= wr_addr(0) and wr_addr(1) and wr_en;
block1_wr_en <= not wr_addr(0) and not wr_addr(1) and wr_en;
block2_wr_en <= wr_addr(0) and not wr_addr(1) and wr_en;
search_completed_i <= block0_search_completed or block1_search_completed or block2_search_completed or block3_search_completed;
entry_found <= block0_entry_found or block1_entry_found or block2_entry_found or block3_entry_found;
if block0_entry_found = '1' then
if block0_prefix = "0000000000" then
prefix <= x"001";
else
prefix(11 downto 2) <= std_logic_vector(unsigned(block0_prefix)-to_unsigned(1,10));
prefix(1 downto 0) <= "01";
end if;
elsif block1_entry_found = '1' then
prefix(11 downto 2) <= std_logic_vector(unsigned(block1_prefix)-to_unsigned(1,10));
prefix(1 downto 0) <= "10";
elsif block2_entry_found = '1' then
prefix(11 downto 2) <= std_logic_vector(unsigned(block2_prefix)-to_unsigned(1,10));
prefix(1 downto 0) <= "11";
elsif block3_entry_found = '1' then
prefix(11 downto 2) <= block3_prefix;
prefix(1 downto 0) <= "00";
end if;
end if;
end process;
U_BLOCK_0 : entity work.dictionary_block_4
generic map (block_num => 0)
port map(
clk => clk,
rst => rst,
start_search => start_search,
search_entry => search_entry,
halt_search => search_completed_i,
wr_en => r_block0_wr_en,
wr_addr => r_wr_addr(11 downto 2),
wr_entry => r_wr_entry,
prefix => block0_prefix,
entry_found => block0_entry_found,
search_completed => block0_search_completed);
U_BLOCK_1 : entity work.dictionary_block_4
generic map (block_num => 1)
port map(
clk => clk,
rst => rst,
start_search => start_search,
search_entry => search_entry,
wr_en => r_block1_wr_en,
wr_addr => r_wr_addr(11 downto 2),
wr_entry => r_wr_entry,
halt_search => search_completed_i,
prefix => block1_prefix,
entry_found => block1_entry_found,
search_completed => block1_search_completed);
U_BLOCK_2 : entity work.dictionary_block_4
generic map (block_num => 2)
port map(
clk => clk,
rst => rst,
start_search => start_search,
search_entry => search_entry,
wr_en => r_block2_wr_en,
wr_addr => r_wr_addr(11 downto 2),
wr_entry => r_wr_entry,
halt_search => search_completed_i,
prefix => block2_prefix,
entry_found => block2_entry_found,
search_completed => block2_search_completed);
U_BLOCK_3 : entity work.dictionary_block_4
generic map (block_num => 3)
port map(
clk => clk,
rst => rst,
start_search => start_search,
search_entry => search_entry,
wr_en => r_block3_wr_en,
wr_addr => r_wr_addr(11 downto 2),
wr_entry => r_wr_entry,
halt_search => search_completed_i,
prefix => block3_prefix,
entry_found => block3_entry_found,
search_completed => block3_search_completed);
--write proc
dictionary_full <= full;
process(clk,rst)
begin
if rst = '1' then
wr_addr <= std_logic_vector(to_unsigned(254,12));
full <= '0';
elsif rising_edge(clk) then
if wr_en = '1' and full = '0' then
wr_addr <= std_logic_vector(to_unsigned(1,12)+unsigned(wr_addr));
end if;
--last entry written should increment counter to "1000...000"
if wr_addr(11) = '1' then
full <= '1';
end if;
end if;
end process;
end Behavioral;
| unlicense | 8c678fc7c744ae641b90c4f50b7221eb | 0.529928 | 3.581706 | false | false | false | false |
grwlf/vsim | vhdl_ct/ct00536.vhd | 1 | 2,329 | -- NEED RESULT: ARCH00536: Record type visibility test passed
-------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
-------------------------------------------------------------------------------
--
-- TEST NAME:
--
-- CT00536
--
-- AUTHOR:
--
-- G. Tominovich
--
-- TEST OBJECTIVES:
--
-- 10.3 (6)
--
-- DESIGN UNIT ORDERING:
--
-- PKG00536
-- PKG00536/BODY
-- E00000(ARCH00536)
-- ENT00536_Test_Bench(ARCH00536_Test_Bench)
--
-- REVISION HISTORY:
--
-- 18-AUG-1987 - initial revision
--
-- NOTES:
--
-- self-checking
--
--
package PKG00536 is
type RE1 is record
A : INTEGER;
B : BIT;
end record;
type RE2 is record
A : INTEGER;
B : BIT;
end record;
type RE3 is record
A : RE1;
B : RE2;
end record;
function F ( A : RE1; B : RE2) return RE3 ;
end PKG00536 ;
--
package body PKG00536 is
function F ( A : RE1; B : RE2) return RE3 is
variable RETURN_RECORD : RE3;
begin
RETURN_RECORD.A.A := A.A;
RETURN_RECORD.A.B := A.B;
RETURN_RECORD.B.A := B.A;
RETURN_RECORD.B.B := B.B;
return RETURN_RECORD;
end F;
end PKG00536 ;
--
use WORK.STANDARD_TYPES.all, WORK.PKG00536.all ;
architecture ARCH00536 of E00000 is
begin
process
variable A : RE3;
variable B : RE1;
variable C : RE2;
variable D : INTEGER;
begin
A := (A => (A => 3, B => '1') ,
B => (A => 1, B => '0') ) ;
B := A.A;
C := A.B;
D := WORK.PKG00536.F (A => B, B => C) .A.A;
test_report ( "ARCH00536" ,
"Record type visibility test" ,
(B.A = 3) and (B.B = '1') and
(C.A = 1) and (C.B = '0') and
(D = 3) ) ;
wait ;
end process;
end ARCH00536 ;
--
entity ENT00536_Test_Bench is
end ENT00536_Test_Bench ;
architecture ARCH00536_Test_Bench of ENT00536_Test_Bench is
begin
L1:
block
component UUT
end component ;
for CIS1 : UUT use entity WORK.E00000 ( ARCH00536 ) ;
begin
CIS1 : UUT ;
end block L1 ;
end ARCH00536_Test_Bench ;
--
| gpl-3.0 | 5a8101a0f5c151bcf115a4bb787802e4 | 0.474882 | 3.068511 | false | true | false | false |
grwlf/vsim | vhdl_ct/ct00230.vhd | 1 | 8,920 | -------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
-------------------------------------------------------------------------------
--
-- TEST NAME:
--
-- CT00230
--
-- AUTHOR:
--
-- A. Wilmot
--
-- TEST OBJECTIVES:
--
-- 1.1.1.2 (8)
--
-- DESIGN UNIT ORDERING:
--
-- GENERIC_STANDARD_TYPES(ARCH00230)
-- ENT00230_Test_Bench(ARCH00230_Test_Bench)
--
-- REVISION HISTORY:
--
-- 15-JUN-1987 - initial revision
--
-- NOTES:
--
-- self-checking
-- automatically generated
--
use WORK.STANDARD_TYPES ;
use STANDARD_TYPES.test_report, STANDARD_TYPES.switch,
STANDARD_TYPES.up, STANDARD_TYPES.down, STANDARD_TYPES.toggle,
STANDARD_TYPES."=" ;
architecture ARCH00230 of GENERIC_STANDARD_TYPES is
signal i_bit_vector_1, i_bit_vector_2 : st_bit_vector
:= c_st_bit_vector_1 ;
signal i_string_1, i_string_2 : st_string
:= c_st_string_1 ;
signal i_t_rec1_1, i_t_rec1_2 : st_rec1
:= c_st_rec1_1 ;
signal i_st_rec1_1, i_st_rec1_2 : st_rec1
:= c_st_rec1_1 ;
signal i_t_rec2_1, i_t_rec2_2 : st_rec2
:= c_st_rec2_1 ;
signal i_st_rec2_1, i_st_rec2_2 : st_rec2
:= c_st_rec2_1 ;
signal i_t_rec3_1, i_t_rec3_2 : st_rec3
:= c_st_rec3_1 ;
signal i_st_rec3_1, i_st_rec3_2 : st_rec3
:= c_st_rec3_1 ;
signal i_t_arr1_1, i_t_arr1_2 : st_arr1
:= c_st_arr1_1 ;
signal i_st_arr1_1, i_st_arr1_2 : st_arr1
:= c_st_arr1_1 ;
signal i_t_arr2_1, i_t_arr2_2 : st_arr2
:= c_st_arr2_1 ;
signal i_st_arr2_1, i_st_arr2_2 : st_arr2
:= c_st_arr2_1 ;
signal i_t_arr3_1, i_t_arr3_2 : st_arr3
:= c_st_arr3_1 ;
signal i_st_arr3_1, i_st_arr3_2 : st_arr3
:= c_st_arr3_1 ;
--
begin
L1:
block
port (
toggle : inout switch := down;
i_bit_vector_1, i_bit_vector_2 : inout bit_vector
:= c_st_bit_vector_1
;
i_string_1, i_string_2 : inout string
:= c_st_string_1
;
i_t_rec1_1, i_t_rec1_2 : inout t_rec1
:= c_st_rec1_1
;
i_st_rec1_1, i_st_rec1_2 : inout st_rec1
:= c_st_rec1_1
;
i_t_rec2_1, i_t_rec2_2 : inout t_rec2
:= c_st_rec2_1
;
i_st_rec2_1, i_st_rec2_2 : inout st_rec2
:= c_st_rec2_1
;
i_t_rec3_1, i_t_rec3_2 : inout t_rec3
:= c_st_rec3_1
;
i_st_rec3_1, i_st_rec3_2 : inout st_rec3
:= c_st_rec3_1
;
i_t_arr1_1, i_t_arr1_2 : inout t_arr1
:= c_st_arr1_1
;
i_st_arr1_1, i_st_arr1_2 : inout st_arr1
:= c_st_arr1_1
;
i_t_arr2_1, i_t_arr2_2 : inout t_arr2
:= c_st_arr2_1
;
i_st_arr2_1, i_st_arr2_2 : inout st_arr2
:= c_st_arr2_1
;
i_t_arr3_1, i_t_arr3_2 : inout t_arr3
:= c_st_arr3_1
;
i_st_arr3_1, i_st_arr3_2 : inout st_arr3
:= c_st_arr3_1
) ;
port map (
toggle ,
i_bit_vector_1, i_bit_vector_2,
i_string_1, i_string_2,
i_t_rec1_1, i_t_rec1_2,
i_st_rec1_1, i_st_rec1_2,
i_t_rec2_1, i_t_rec2_2,
i_st_rec2_1, i_st_rec2_2,
i_t_rec3_1, i_t_rec3_2,
i_st_rec3_1, i_st_rec3_2,
i_t_arr1_1, i_t_arr1_2,
i_st_arr1_1, i_st_arr1_2,
i_t_arr2_1, i_t_arr2_2,
i_st_arr2_1, i_st_arr2_2,
i_t_arr3_1, i_t_arr3_2,
i_st_arr3_1, i_st_arr3_2
) ;
--
begin
process
variable correct : boolean := true ;
begin
correct := correct and i_bit_vector_1 = c_st_bit_vector_1
and i_bit_vector_2 = c_st_bit_vector_1 ;
correct := correct and i_string_1 = c_st_string_1
and i_string_2 = c_st_string_1 ;
correct := correct and i_t_rec1_1 = c_st_rec1_1
and i_t_rec1_2 = c_st_rec1_1 ;
correct := correct and i_st_rec1_1 = c_st_rec1_1
and i_st_rec1_2 = c_st_rec1_1 ;
correct := correct and i_t_rec2_1 = c_st_rec2_1
and i_t_rec2_2 = c_st_rec2_1 ;
correct := correct and i_st_rec2_1 = c_st_rec2_1
and i_st_rec2_2 = c_st_rec2_1 ;
correct := correct and i_t_rec3_1 = c_st_rec3_1
and i_t_rec3_2 = c_st_rec3_1 ;
correct := correct and i_st_rec3_1 = c_st_rec3_1
and i_st_rec3_2 = c_st_rec3_1 ;
correct := correct and i_t_arr1_1 = c_st_arr1_1
and i_t_arr1_2 = c_st_arr1_1 ;
correct := correct and i_st_arr1_1 = c_st_arr1_1
and i_st_arr1_2 = c_st_arr1_1 ;
correct := correct and i_t_arr2_1 = c_st_arr2_1
and i_t_arr2_2 = c_st_arr2_1 ;
correct := correct and i_st_arr2_1 = c_st_arr2_1
and i_st_arr2_2 = c_st_arr2_1 ;
correct := correct and i_t_arr3_1 = c_st_arr3_1
and i_t_arr3_2 = c_st_arr3_1 ;
correct := correct and i_st_arr3_1 = c_st_arr3_1
and i_st_arr3_2 = c_st_arr3_1 ;
--
test_report ( "ENT00230" ,
"Associated composite inout ports with generic subtypes" ,
correct) ;
--
toggle <= up ;
i_bit_vector_1 <= c_st_bit_vector_2 ;
i_bit_vector_2 <= c_st_bit_vector_2 ;
i_string_1 <= c_st_string_2 ;
i_string_2 <= c_st_string_2 ;
i_t_rec1_1 <= c_st_rec1_2 ;
i_t_rec1_2 <= c_st_rec1_2 ;
i_st_rec1_1 <= c_st_rec1_2 ;
i_st_rec1_2 <= c_st_rec1_2 ;
i_t_rec2_1 <= c_st_rec2_2 ;
i_t_rec2_2 <= c_st_rec2_2 ;
i_st_rec2_1 <= c_st_rec2_2 ;
i_st_rec2_2 <= c_st_rec2_2 ;
i_t_rec3_1 <= c_st_rec3_2 ;
i_t_rec3_2 <= c_st_rec3_2 ;
i_st_rec3_1 <= c_st_rec3_2 ;
i_st_rec3_2 <= c_st_rec3_2 ;
i_t_arr1_1 <= c_st_arr1_2 ;
i_t_arr1_2 <= c_st_arr1_2 ;
i_st_arr1_1 <= c_st_arr1_2 ;
i_st_arr1_2 <= c_st_arr1_2 ;
i_t_arr2_1 <= c_st_arr2_2 ;
i_t_arr2_2 <= c_st_arr2_2 ;
i_st_arr2_1 <= c_st_arr2_2 ;
i_st_arr2_2 <= c_st_arr2_2 ;
i_t_arr3_1 <= c_st_arr3_2 ;
i_t_arr3_2 <= c_st_arr3_2 ;
i_st_arr3_1 <= c_st_arr3_2 ;
i_st_arr3_2 <= c_st_arr3_2 ;
wait ;
end process ;
end block L1 ;
P00230 :
process ( toggle )
variable correct : boolean := true ;
begin
if toggle = up then
correct := correct and i_bit_vector_1 = c_st_bit_vector_2
and i_bit_vector_2 = c_st_bit_vector_2 ;
correct := correct and i_string_1 = c_st_string_2
and i_string_2 = c_st_string_2 ;
correct := correct and i_t_rec1_1 = c_st_rec1_2
and i_t_rec1_2 = c_st_rec1_2 ;
correct := correct and i_st_rec1_1 = c_st_rec1_2
and i_st_rec1_2 = c_st_rec1_2 ;
correct := correct and i_t_rec2_1 = c_st_rec2_2
and i_t_rec2_2 = c_st_rec2_2 ;
correct := correct and i_st_rec2_1 = c_st_rec2_2
and i_st_rec2_2 = c_st_rec2_2 ;
correct := correct and i_t_rec3_1 = c_st_rec3_2
and i_t_rec3_2 = c_st_rec3_2 ;
correct := correct and i_st_rec3_1 = c_st_rec3_2
and i_st_rec3_2 = c_st_rec3_2 ;
correct := correct and i_t_arr1_1 = c_st_arr1_2
and i_t_arr1_2 = c_st_arr1_2 ;
correct := correct and i_st_arr1_1 = c_st_arr1_2
and i_st_arr1_2 = c_st_arr1_2 ;
correct := correct and i_t_arr2_1 = c_st_arr2_2
and i_t_arr2_2 = c_st_arr2_2 ;
correct := correct and i_st_arr2_1 = c_st_arr2_2
and i_st_arr2_2 = c_st_arr2_2 ;
correct := correct and i_t_arr3_1 = c_st_arr3_2
and i_t_arr3_2 = c_st_arr3_2 ;
correct := correct and i_st_arr3_1 = c_st_arr3_2
and i_st_arr3_2 = c_st_arr3_2 ;
end if ;
--
test_report ( "ENT00230.P00230" ,
"Associated composite inout ports with generic subtypes",
correct) ;
end process P00230 ;
end ARCH00230 ;
--
entity ENT00230_Test_Bench is
end ENT00230_Test_Bench ;
--
architecture ARCH00230_Test_Bench of ENT00230_Test_Bench is
begin
L1:
block
component UUT
end component ;
--
for CIS1 : UUT use entity WORK.GENERIC_STANDARD_TYPES ( ARCH00230 ) ;
begin
CIS1 : UUT ;
end block L1 ;
end ARCH00230_Test_Bench ;
| gpl-3.0 | be797d443485f8ee4f3335001107c6d3 | 0.468161 | 2.607425 | false | false | false | false |
jairov4/accel-oil | solution_virtex5/impl/pcores/nfa_accept_samples_generic_hw_top_v1_00_a/synhdl/vhdl/nfa_forward_buckets_if_async_fifo.vhd | 1 | 5,829 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity nfa_forward_buckets_if_async_fifo is
generic (
DATA_WIDTH : integer := 32;
ADDR_WIDTH : integer := 3;
DEPTH : integer := 8);
port (
clk_w : in std_logic;
clk_r : in std_logic;
reset : in std_logic;
if_din : in std_logic_vector(DATA_WIDTH - 1 downto 0);
if_full_n : out std_logic;
if_write_ce: in std_logic;
if_write : in std_logic;
if_dout : out std_logic_vector(DATA_WIDTH - 1 downto 0);
if_empty_n : out std_logic;
if_read_ce : in std_logic;
if_read : in std_logic);
function calc_addr_width(x : integer) return integer is
begin
if (x < 1) then
return 1;
else
return x;
end if;
end function;
end entity;
architecture rtl of nfa_forward_buckets_if_async_fifo is
constant DEPTH_BITS : integer := calc_addr_width(ADDR_WIDTH);
constant REAL_DEPTH : integer := 2 ** DEPTH_BITS;
constant ALL_ONE : unsigned(DEPTH_BITS downto 0) := (others => '1');
constant MASK : std_logic_vector(DEPTH_BITS downto 0) := std_logic_vector(ALL_ONE sll (DEPTH_BITS - 1));
type memtype is array (0 to REAL_DEPTH - 1) of std_logic_vector(DATA_WIDTH - 1 downto 0);
signal mem : memtype;
signal full : std_logic := '0';
signal empty : std_logic := '1';
signal full_next : std_logic;
signal empty_next : std_logic;
signal wraddr_bin : std_logic_vector(DEPTH_BITS downto 0) := (others => '0');
signal rdaddr_bin : std_logic_vector(DEPTH_BITS downto 0) := (others => '0');
signal wraddr : std_logic_vector(DEPTH_BITS - 1 downto 0);
signal rdaddr : std_logic_vector(DEPTH_BITS - 1 downto 0);
signal wraddr_bin_next : std_logic_vector(DEPTH_BITS downto 0);
signal rdaddr_bin_next : std_logic_vector(DEPTH_BITS downto 0);
signal wraddr_gray_next : std_logic_vector(DEPTH_BITS downto 0);
signal rdaddr_gray_next : std_logic_vector(DEPTH_BITS downto 0);
signal wraddr_gray_sync0 : std_logic_vector(DEPTH_BITS downto 0) := (others => '0');
signal rdaddr_gray_sync0 : std_logic_vector(DEPTH_BITS downto 0) := (others => '0');
signal wraddr_gray_sync1 : std_logic_vector(DEPTH_BITS downto 0) := (others => '0');
signal rdaddr_gray_sync1 : std_logic_vector(DEPTH_BITS downto 0) := (others => '0');
signal wraddr_gray_sync2 : std_logic_vector(DEPTH_BITS downto 0) := (others => '0');
signal rdaddr_gray_sync2 : std_logic_vector(DEPTH_BITS downto 0) := (others => '0');
signal dout_buf : std_logic_vector(DATA_WIDTH - 1 downto 0) := (others => '0');
attribute ram_style : string;
attribute ram_style of mem : signal is "block";
begin
if_full_n <= not full;
if_empty_n <= not empty;
if_dout <= dout_buf;
full_next <= '1' when (wraddr_gray_next = (rdaddr_gray_sync2 xor MASK)) else '0';
empty_next <= '1' when (rdaddr_gray_next = wraddr_gray_sync2) else '0';
wraddr <= wraddr_bin(DEPTH_BITS - 1 downto 0);
rdaddr <= rdaddr_bin_next(DEPTH_BITS - 1 downto 0);
wraddr_bin_next <= std_logic_vector(unsigned(wraddr_bin) + 1) when (full = '0' and if_write = '1') else wraddr_bin;
rdaddr_bin_next <= std_logic_vector(unsigned(rdaddr_bin) + 1) when (empty = '0' and if_read = '1') else rdaddr_bin;
wraddr_gray_next <= wraddr_bin_next xor std_logic_vector(unsigned(wraddr_bin_next) srl 1);
rdaddr_gray_next <= rdaddr_bin_next xor std_logic_vector(unsigned(rdaddr_bin_next) srl 1);
-- full, wraddr_bin, wraddr_gray_sync0, rdaddr_gray_sync1, rdaddr_gray_sync2
-- @ clk_w domain
process(clk_w, reset) begin
if (reset = '1') then
full <= '0';
wraddr_bin <= (others => '0');
wraddr_gray_sync0 <= (others => '0');
rdaddr_gray_sync1 <= (others => '0');
rdaddr_gray_sync2 <= (others => '0');
elsif (clk_w'event and clk_w = '1' and if_write_ce = '1') then
full <= full_next;
wraddr_bin <= wraddr_bin_next;
wraddr_gray_sync0 <= wraddr_gray_next;
rdaddr_gray_sync1 <= rdaddr_gray_sync0;
rdaddr_gray_sync2 <= rdaddr_gray_sync1;
end if;
end process;
-- empty, rdaddr_bin, rdaddr_gray_sync0, wraddr_gray_sync1, wraddr_gray_sync2
-- @ clk_r domain
process(clk_r, reset) begin
if (reset = '1') then
empty <= '1';
rdaddr_bin <= (others => '0');
rdaddr_gray_sync0 <= (others => '0');
wraddr_gray_sync1 <= (others => '0');
wraddr_gray_sync2 <= (others => '0');
elsif (clk_r'event and clk_r = '1' and if_read_ce = '1') then
empty <= empty_next;
rdaddr_bin <= rdaddr_bin_next;
rdaddr_gray_sync0 <= rdaddr_gray_next;
wraddr_gray_sync1 <= wraddr_gray_sync0;
wraddr_gray_sync2 <= wraddr_gray_sync1;
end if;
end process;
-- write mem
process(clk_w) begin
if (clk_w'event and clk_w = '1' and if_write_ce = '1') then
if (full = '0' and if_write = '1') then
mem(to_integer(unsigned(wraddr))) <= if_din;
end if;
end if;
end process;
-- read mem
process(clk_r) begin
if (clk_r'event and clk_r = '1' and if_read_ce = '1') then
dout_buf <= mem(to_integer(unsigned(rdaddr)));
end if;
end process;
end architecture;
| lgpl-3.0 | 2917b319d0de0ee935ba176b48d73b25 | 0.554297 | 3.408772 | false | false | false | false |
jairov4/accel-oil | solution_virtex5_plb/impl/pcores/nfa_accept_samples_generic_hw_top_v1_01_a/synhdl/vhdl/indices_if_plb_master_if.vhd | 4 | 36,869 | -- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2014.1
-- Copyright (C) 2014 Xilinx Inc. All rights reserved.
--
-- ==============================================================
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity indices_if_ap_fifo_uw is
generic (
DATA_WIDTH : integer := 32;
ADDR_WIDTH : integer := 4;
DEPTH : integer := 16);
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
if_empty_n : OUT STD_LOGIC;
if_read : IN STD_LOGIC;
if_dout : OUT STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0);
if_full_n : OUT STD_LOGIC;
if_write : IN STD_LOGIC;
if_din : IN STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0);
use_word: OUT STD_LOGIC_VECTOR(ADDR_WIDTH -1 downto 0));
end entity;
architecture rtl of indices_if_ap_fifo_uw is
type memtype is array (0 to DEPTH - 1) of STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0);
signal mStorage : memtype;
signal mInPtr, mNextInPtr, mOutPtr : UNSIGNED(ADDR_WIDTH - 1 downto 0);
signal internal_empty_n, internal_full_n : STD_LOGIC;
signal internal_use_word : STD_LOGIC_VECTOR(ADDR_WIDTH -1 downto 0);
begin
mNextInPtr <= mInPtr + 1;
if_dout <= mStorage(CONV_INTEGER(mOutPtr));
if_empty_n <= internal_empty_n;
if_full_n <= internal_full_n;
use_word <= internal_use_word;
process (clk, reset)
begin
if reset = '1' then
mInPtr <= (others => '0');
mOutPtr <= (others => '0');
internal_use_word <= (others => '0');
else
if clk'event and clk = '1' then
if if_read = '1' and internal_empty_n = '1' then
mOutPtr <= mOutPtr + 1;
end if;
if if_write = '1' and internal_full_n = '1' then
mStorage(CONV_INTEGER(mInPtr)) <= if_din;
mInPtr <= mNextInPtr;
end if;
if (if_read = '1' and if_write = '0') then
internal_use_word <= internal_use_word - '1';
elsif (if_read = '0' and if_write = '1') then
internal_use_word <= internal_use_word + '1';
end if;
end if;
end if;
end process;
process (mInPtr, mOutPtr, mNextInPtr)
begin
if mInPtr = mOutPtr then
internal_empty_n <= '0';
else
internal_empty_n <= '1';
end if;
if mNextInPtr = mOutPtr then
internal_full_n <= '0';
else
internal_full_n <= '1';
end if;
end process;
end architecture;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity indices_if_plb_master_if is
generic
(
C_PLB_AWIDTH : integer := 32;
C_PLB_DWIDTH : integer := 64;
PLB_ADDR_SHIFT : integer := 3
);
port
(
-- ADD USER PORTS BELOW THIS LINE ------------------
--USER ports added here
-- ADD USER PORTS ABOVE THIS LINE ------------------
-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol ports, do not add to or delete
PLB_Clk : in std_logic;
PLB_Rst : in std_logic;
M_abort : out std_logic;
M_ABus : out std_logic_vector(0 to C_PLB_AWIDTH-1);
M_BE : out std_logic_vector(0 to C_PLB_DWIDTH/8-1);
M_busLock : out std_logic;
M_lockErr : out std_logic;
M_MSize : out std_logic_vector(0 to 1);
M_priority : out std_logic_vector(0 to 1);
M_rdBurst : out std_logic;
M_request : out std_logic;
M_RNW : out std_logic;
M_size : out std_logic_vector(0 to 3);
M_type : out std_logic_vector(0 to 2);
M_wrBurst : out std_logic;
M_wrDBus : out std_logic_vector(0 to C_PLB_DWIDTH-1);
PLB_MBusy : in std_logic;
PLB_MWrBTerm : in std_logic;
PLB_MWrDAck : in std_logic;
PLB_MAddrAck : in std_logic;
PLB_MRdBTerm : in std_logic;
PLB_MRdDAck : in std_logic;
PLB_MRdDBus : in std_logic_vector(0 to (C_PLB_DWIDTH-1));
PLB_MRdWdAddr : in std_logic_vector(0 to 3);
PLB_MRearbitrate : in std_logic;
PLB_MSSize : in std_logic_vector(0 to 1);
-- signals from user logic
BUS_RdData : out std_logic_vector(C_PLB_DWIDTH-1 downto 0); -- Bus read return data to user_logic
BUS_WrData : in std_logic_vector(C_PLB_DWIDTH-1 downto 0); -- Bus write data
BUS_address : in std_logic_vector(31 downto 0); -- physical address
BUS_size : in std_logic_vector(31 downto 0); -- burst size of word
BUS_req_nRW : in std_logic; -- req type 0: Read, 1: write
BUS_req_BE : in std_logic_vector(C_PLB_DWIDTH/8-1 downto 0); -- Bus write data byte enable
BUS_req_full_n : out std_logic; -- req Fifo full
BUS_req_push : in std_logic; -- req Fifo push (new request in)
BUS_rsp_nRW : out std_logic; -- return data FIFO rsp type
BUS_rsp_empty_n: out std_logic; -- return data FIFO empty
BUS_rsp_pop : in std_logic -- return data FIFO pop
);
attribute SIGIS : string;
attribute SIGIS of PLB_Clk : signal is "Clk";
attribute SIGIS of PLB_Rst : signal is "Rst";
end entity;
------------------------------------------------------------------------------
-- Architecture section
------------------------------------------------------------------------------
architecture IMP of indices_if_plb_master_if is
component indices_if_ap_fifo is
generic (
DATA_WIDTH : integer := 32;
ADDR_WIDTH : integer := 4;
DEPTH : integer := 16);
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
if_empty_n : OUT STD_LOGIC;
if_read : IN STD_LOGIC;
if_dout : OUT STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0);
if_full_n : OUT STD_LOGIC;
if_write : IN STD_LOGIC;
if_din : IN STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0));
end component;
component indices_if_ap_fifo_uw is
generic (
DATA_WIDTH : integer := 32;
ADDR_WIDTH : integer := 4;
DEPTH : integer := 16);
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
if_empty_n : OUT STD_LOGIC;
if_read : IN STD_LOGIC;
if_dout : OUT STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0);
if_full_n : OUT STD_LOGIC;
if_write : IN STD_LOGIC;
if_din : IN STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0);
use_word: OUT STD_LOGIC_VECTOR(ADDR_WIDTH -1 downto 0));
end component;
constant PLB_DW : integer := C_PLB_DWIDTH;
constant PLB_BYTE_COUNT : integer := PLB_DW/8;
constant REQ_FIFO_WIDTH : integer := 1 + PLB_BYTE_COUNT + 32 + 32; --nRW + BE + 32 bits phy addr + size
constant FIFO_ADDR_WIDTH : integer := 5;
constant FIFO_DEPTH : integer := 32;
-- request FIFO
signal req_fifo_empty_n : STD_LOGIC;
signal req_fifo_pop : STD_LOGIC;
signal req_fifo_dout : STD_LOGIC_VECTOR(REQ_FIFO_WIDTH - 1 downto 0);
signal req_fifo_full_n : STD_LOGIC;
signal req_fifo_push : STD_LOGIC;
signal req_fifo_din : STD_LOGIC_VECTOR(REQ_FIFO_WIDTH - 1 downto 0);
-- burst write counter (only push burst data in and ignore all burst write request except the first one)
signal req_burst_write: STD_LOGIC; -- whether last request is a burst write
signal req_burst_write_counter: STD_LOGIC_VECTOR(31 downto 0);
-- write data FIFO (for bus write data)
signal wd_fifo_empty_n : STD_LOGIC;
signal wd_fifo_pop : STD_LOGIC;
signal wd_fifo_dout : STD_LOGIC_VECTOR(PLB_DW - 1 downto 0);
signal wd_fifo_dout_mirror : STD_LOGIC_VECTOR(PLB_DW - 1 downto 0);
signal wd_fifo_full_n : STD_LOGIC;
signal wd_fifo_push : STD_LOGIC;
signal wd_fifo_din : STD_LOGIC_VECTOR(PLB_DW - 1 downto 0);
signal wd_fifo_use_word: STD_LOGIC_VECTOR(FIFO_ADDR_WIDTH -1 downto 0);
-- read data FIFO (for bus read returned data)
signal rd_fifo_empty_n : STD_LOGIC;
signal rd_fifo_pop : STD_LOGIC;
signal rd_fifo_dout : STD_LOGIC_VECTOR(PLB_DW - 1 downto 0);
signal rd_fifo_full_n : STD_LOGIC;
signal rd_fifo_push : STD_LOGIC;
signal rd_fifo_din : STD_LOGIC_VECTOR(PLB_DW - 1 downto 0);
signal rd_fifo_use_word: STD_LOGIC_VECTOR(FIFO_ADDR_WIDTH -1 downto 0);
signal req_address : std_logic_vector(0 to C_PLB_AWIDTH -1);-- bus request word address
signal req_fifo_dout_req_size : std_logic_vector(31 downto 0); -- req_size -1
signal req_size : std_logic_vector(0 to 27); -- burst size of 16 word block
signal request, req_nRW: std_logic;
signal req_BE : std_logic_vector(PLB_BYTE_COUNT-1 downto 0);
signal pending_rd_req_burst_mode: std_logic;
signal pending_rd_req_burst_size: std_logic_vector(3 downto 0);
signal pending_wr_req_burst_mode: std_logic;
signal pending_wr_req_burst_size: std_logic_vector(3 downto 0);
signal pending_read, pending_write: std_logic;
signal burst_mode, burst_last : std_logic;
signal burst_size : std_logic_vector(3 downto 0); -- maximum burst 16 words
--signals for write data mirror
signal conv_mode_comb : std_logic_vector(1 downto 0); -- 00: NO conv, 01: 128/32, 10: 64/32, 11: 128/64
signal conv_counter_comb: std_logic_vector(1 downto 0);
signal wr_data_phase : std_logic;
signal dataConv_last: std_logic;
signal dp_dataConv_last: std_logic;
signal dp_dataConv_word_addr: std_logic_vector(1 downto 0);
signal dp_dataConv_wd_conv_mode : std_logic_vector(1 downto 0); -- 00:NO conv, 01:128/32, 10:64/32, 11:128/64
signal dp_dataConv_wd_burst_counter: std_logic_vector(1 downto 0);
signal dp_dataConv_wd_BE: std_logic_vector(PLB_BYTE_COUNT-1 downto 0);
signal dp_PLB_MSSize : std_logic_vector(1 downto 0);
--signals for read data mirror
signal PLB_MRdDAck_reg : std_logic;
signal dp_dataConv_rd_conv_mode : std_logic_vector(1 downto 0);-- 00: NO conv, 01: 128/32, 10: 64/32, 11: 128/64
signal dp_dataConv_rd_burst_counter, dp_dataConv_rd_burst_counter_reg: std_logic_vector(1 downto 0);
signal PLB_MRdDBus_reverse : std_logic_vector(PLB_DW-1 downto 0);
-- signals with dp_ prefix stand for data phase signals
-- signals with req_ prefix stand for request phase signals
begin
-- interface to user logic
BUS_RdData <= rd_fifo_dout;
BUS_req_full_n <= req_fifo_full_n and wd_fifo_full_n;
BUS_rsp_nRW <= '0';
BUS_rsp_empty_n <= rd_fifo_empty_n;
-- interface to PLB
M_abort <= '0';
M_busLock <= '0';
M_lockErr <= '0';
M_MSize <= "01"; -- 00:32b dev, 01:64b, 10:128b, 11:256b
M_size <= "0000" when (burst_mode = '0' or burst_size = "0000") else "1011"; -- single rw or 64 bits burst
M_type <= "000"; -- memory trans
M_priority <= "00";
M_RNW <= not req_nRW;
M_rdBurst <= '1' when pending_rd_req_burst_mode = '1' and
(pending_rd_req_burst_size /= "0000" or dp_dataConv_rd_burst_counter /="00") else '0';
process (PLB_MSSize)
begin
M_wrBurst <= '0';
if (pending_wr_req_burst_mode = '1' and
(pending_wr_req_burst_size /= "0000" or dp_dataConv_wd_burst_counter /="00")) then
M_wrBurst <= '1';
elsif (request = '1' and req_nRW = '1' and pending_write = '0' and
burst_mode = '1' and burst_size /="0000" and wd_fifo_use_word > burst_size) then
M_wrBurst <= '1';
end if;
end process;
-- write data mirror section
process (PLB_MSSize)
begin
if (C_PLB_DWIDTH = 64 and PLB_MSSize = "00") then
conv_mode_comb <= "10"; -- conv 64:32
conv_counter_comb <= "01";
elsif (C_PLB_DWIDTH = 128 and PLB_MSSize = "01") then
conv_mode_comb <= "11"; -- conv 128:64
conv_counter_comb <= "01";
elsif (C_PLB_DWIDTH = 128 and PLB_MSSize = "00") then
conv_mode_comb <= "01"; -- conv 128:32
conv_counter_comb <= "11";
else
conv_mode_comb <= "00"; -- do not need conv
conv_counter_comb <= "00";
end if;
end process;
process (burst_mode, burst_size, conv_mode_comb, req_address, req_BE)
begin
dataConv_last <= '0';
if (burst_mode = '0' or burst_size = "0000") then
if (conv_mode_comb = "00") then -- no conv
dataConv_last <= '1';
elsif (conv_mode_comb = "10") then -- 64:32 conv
if (req_address(29)='1' or req_BE(PLB_BYTE_COUNT-1 downto PLB_BYTE_COUNT/2)=CONV_STD_LOGIC_VECTOR(0,PLB_BYTE_COUNT/2)) then
dataConv_last <= '1';
end if;
elsif (conv_mode_comb = "11") then -- 128:64 conv
if (req_address(28)='1' or req_BE(PLB_BYTE_COUNT-1 downto PLB_BYTE_COUNT/2)=CONV_STD_LOGIC_VECTOR(0,PLB_BYTE_COUNT/2)) then
dataConv_last <= '1';
end if;
elsif (conv_mode_comb = "01") then -- 128:32 conv
if (req_address(28 to 29) = "00" and req_BE(PLB_BYTE_COUNT-1 downto PLB_BYTE_COUNT/4)=CONV_STD_LOGIC_VECTOR(0,PLB_BYTE_COUNT*3/4)) then
dataConv_last <= '1';
elsif (req_address(28 to 29) = "01" and req_BE(PLB_BYTE_COUNT-1 downto PLB_BYTE_COUNT/2)=CONV_STD_LOGIC_VECTOR(0,PLB_BYTE_COUNT/2)) then
dataConv_last <= '1';
elsif (req_address(28 to 29) = "10" and req_BE(PLB_BYTE_COUNT-1 downto PLB_BYTE_COUNT*3/4)=CONV_STD_LOGIC_VECTOR(0,PLB_BYTE_COUNT/4)) then
dataConv_last <= '1';
elsif (req_address(28 to 29) = "11") then
dataConv_last <= '1';
end if;
end if;
end if;
end process;
process (PLB_Clk, PLB_Rst)
begin
if (PLB_Rst = '1') then
dp_dataConv_word_addr <= (others => '0');
dp_dataConv_wd_conv_mode <= (others =>'0');
dp_dataConv_wd_burst_counter <= (others => '0');
dp_dataConv_wd_BE <= (others => '0');
dp_dataConv_last <= '0';
wr_data_phase <= '0';
elsif (PLB_Clk'event and PLB_Clk = '1') then
if (PLB_MAddrAck = '1' and req_nRW = '1') then
dp_dataConv_wd_BE <= req_BE;
dp_dataConv_last <= dataConv_last;
end if;
if (PLB_MAddrAck = '1' and req_nRW = '1' and
(PLB_MWrDAck = '0' or (burst_mode = '1' and burst_size /= "0000"))) then
wr_data_phase <= '1';
end if;
if (PLB_MWrDAck = '1' and wr_data_phase = '1') then
if ((pending_wr_req_burst_size = "0000" and dp_dataConv_wd_burst_counter = "00") or
(pending_wr_req_burst_mode = '0')) then
wr_data_phase <= '0';
end if;
end if;
if (PLB_MAddrAck = '1' and req_nRW = '1' and dp_dataConv_wd_conv_mode = "00") then
if (PLB_MWrDAck = '0') then
-- only AddrAck asserted
dp_dataConv_wd_conv_mode <= conv_mode_comb;
dp_dataConv_word_addr <= req_address(28 to 29);
dp_dataConv_wd_burst_counter <= conv_counter_comb;
else
-- Xilinx PLB v4.6 support assert addrAck & wrDAck at the same cycle
if (dataConv_last = '0') then
dp_dataConv_wd_conv_mode <= conv_mode_comb;
end if;
if (PLB_MSSize = "00") then -- 32 bits slave
dp_dataConv_word_addr <= req_address(28 to 29) +1;
elsif (PLB_MSSize = "01") then -- 64 bits slave
dp_dataConv_word_addr <= req_address(28 to 29) +2;
end if;
if (conv_mode_comb /= "00") then -- need conv
dp_dataConv_wd_burst_counter <= conv_counter_comb -1;
end if;
end if;
end if;
if (wr_data_phase = '1' and PLB_MWrDAck = '1' and
((pending_wr_req_burst_mode = '1' and pending_wr_req_burst_size = "0000" and dp_dataConv_wd_burst_counter = "00") or
(pending_wr_req_burst_mode = '0' and dp_dataConv_last = '1'))) then
dp_dataConv_wd_conv_mode <= "00";
end if;
if (PLB_MWrDAck = '1' and wr_data_phase = '1') then
if (dp_PLB_MSSize = "01") then -- 64 bits slave
dp_dataConv_word_addr <= dp_dataConv_word_addr +2;
else
dp_dataConv_word_addr <= dp_dataConv_word_addr +1;
end if;
if ((pending_wr_req_burst_mode = '1' and pending_wr_req_burst_size /= "0000") or
dp_dataConv_wd_burst_counter /= "00") then
if (dp_dataConv_wd_burst_counter = "00") then
if (dp_dataConv_wd_conv_mode = "01") then -- 128/32
dp_dataConv_wd_burst_counter <= "11";
elsif (dp_dataConv_wd_conv_mode(1) = '1') then -- 64/32 or 128/64
dp_dataConv_wd_burst_counter <= "01";
end if;
else
dp_dataConv_wd_burst_counter <= dp_dataConv_wd_burst_counter -1;
end if;
end if;
end if;
end if;
end process;
process(PLB_MWrDAck, wr_data_phase, dp_dataConv_wd_burst_counter, burst_mode, conv_counter_comb, conv_mode_comb, req_BE)
begin
wd_fifo_pop <= '0';
if (PLB_MWrDAck = '1') then
if (wr_data_phase = '1') then
if ((pending_wr_req_burst_mode = '1' and dp_dataConv_wd_burst_counter = "00") or
(dp_dataConv_wd_conv_mode /= "00" and dp_dataConv_last = '1') or
dp_dataConv_wd_conv_mode = "00" )then
wd_fifo_pop <= '1';
end if;
else
-- got addrAck and wrDAck at the same cycle
if (burst_mode = '1' and burst_size /= "0000" and conv_counter_comb = "00") then
wd_fifo_pop <= '1';
elsif ((burst_mode = '0' or burst_size = "0000") and dataConv_last = '1') then
wd_fifo_pop <= '1';
end if;
end if;
end if;
end process;
process(wd_fifo_dout, wr_data_phase, req_address, dp_dataConv_wd_conv_mode, dp_dataConv_word_addr)
begin
wd_fifo_dout_mirror <= wd_fifo_dout;
if (wr_data_phase = '0') then -- we do not know slave bus width, perform default convert
if (C_PLB_DWIDTH = 32) then
wd_fifo_dout_mirror <= wd_fifo_dout;
elsif (C_PLB_DWIDTH = 64) then
if (req_address(29) = '0') then
wd_fifo_dout_mirror <= wd_fifo_dout;
else
wd_fifo_dout_mirror(PLB_DW/2-1 downto 0) <= wd_fifo_dout(PLB_DW-1 downto PLB_DW/2);
wd_fifo_dout_mirror(PLB_DW-1 downto PLB_DW/2) <= wd_fifo_dout(PLB_DW-1 downto PLB_DW/2);
end if;
elsif (C_PLB_DWIDTH = 128) then
case req_address(28 to 29) is
when "00" =>
wd_fifo_dout_mirror <= wd_fifo_dout;
when "01" =>
wd_fifo_dout_mirror(C_PLB_DWIDTH/4-1 downto 0) <= wd_fifo_dout(C_PLB_DWIDTH/2-1 downto C_PLB_DWIDTH/4);
wd_fifo_dout_mirror(C_PLB_DWIDTH-1 downto C_PLB_DWIDTH/4) <= wd_fifo_dout(C_PLB_DWIDTH-1 downto C_PLB_DWIDTH/4);
when "10" =>
wd_fifo_dout_mirror(C_PLB_DWIDTH/2-1 downto 0) <= wd_fifo_dout(C_PLB_DWIDTH-1 downto C_PLB_DWIDTH/2);
wd_fifo_dout_mirror(C_PLB_DWIDTH-1 downto C_PLB_DWIDTH/2) <= wd_fifo_dout(C_PLB_DWIDTH-1 downto C_PLB_DWIDTH/2);
when "11" =>
wd_fifo_dout_mirror(C_PLB_DWIDTH/4-1 downto 0) <= wd_fifo_dout(C_PLB_DWIDTH-1 downto C_PLB_DWIDTH*3/4);
wd_fifo_dout_mirror(C_PLB_DWIDTH/2-1 downto C_PLB_DWIDTH/4) <= wd_fifo_dout(C_PLB_DWIDTH-1 downto C_PLB_DWIDTH*3/4);
wd_fifo_dout_mirror(C_PLB_DWIDTH*3/4-1 downto C_PLB_DWIDTH/2) <= wd_fifo_dout(C_PLB_DWIDTH-1 downto C_PLB_DWIDTH*3/4);
wd_fifo_dout_mirror(C_PLB_DWIDTH-1 downto C_PLB_DWIDTH*3/4) <= wd_fifo_dout(C_PLB_DWIDTH-1 downto C_PLB_DWIDTH*3/4);
when others => null;
end case;
end if;
else -- in data phase
wd_fifo_dout_mirror <= wd_fifo_dout;
if ((dp_dataConv_wd_conv_mode = "10" and dp_dataConv_word_addr(0) = '1') or
(dp_dataConv_wd_conv_mode = "11" and dp_dataConv_word_addr(1) = '1')) then -- conv 64:32 or 128:64
wd_fifo_dout_mirror(C_PLB_DWIDTH/2-1 downto 0) <= wd_fifo_dout(C_PLB_DWIDTH-1 downto C_PLB_DWIDTH/2);
wd_fifo_dout_mirror(C_PLB_DWIDTH-1 downto C_PLB_DWIDTH/2) <= wd_fifo_dout(C_PLB_DWIDTH-1 downto C_PLB_DWIDTH/2);
elsif (dp_dataConv_wd_conv_mode = "01") then -- conv 128:32
case dp_dataConv_word_addr is
when "00" =>
wd_fifo_dout_mirror <= wd_fifo_dout;
when "01" =>
wd_fifo_dout_mirror(C_PLB_DWIDTH/4-1 downto 0) <= wd_fifo_dout(C_PLB_DWIDTH/2-1 downto C_PLB_DWIDTH/4);
when "10" =>
wd_fifo_dout_mirror(C_PLB_DWIDTH/4-1 downto 0) <= wd_fifo_dout(C_PLB_DWIDTH*3/4-1 downto C_PLB_DWIDTH/2);
when "11" =>
wd_fifo_dout_mirror(C_PLB_DWIDTH/4-1 downto 0) <= wd_fifo_dout(C_PLB_DWIDTH-1 downto C_PLB_DWIDTH*3/4);
when others => null;
end case;
end if;
end if;
end process;
process(wd_fifo_dout_mirror)
variable i: integer;
begin
for i in 0 to C_PLB_DWIDTH-1 loop
M_wrDBus(i) <= wd_fifo_dout_mirror(i);
end loop;
end process;
process (request, req_nRW, pending_read, burst_mode, rd_fifo_full_n, rd_fifo_use_word,
pending_write, wd_fifo_empty_n, wd_fifo_use_word, burst_size)
begin
M_request <= '0';
if (request = '1') then
if (req_nRW = '0' and pending_read = '0') then -- read request
if ((burst_mode = '0' or burst_size = "0000") and rd_fifo_full_n = '1') then
M_request <= '1';
elsif (rd_fifo_use_word(4) = '0') then -- 16 words slots available
M_request <= '1';
end if;
elsif (req_nRW = '1' and pending_write = '0') then -- write request
if ((burst_mode = '0' or burst_size = "0000") and wd_fifo_empty_n = '1') then
M_request <= '1';
elsif (wd_fifo_use_word > burst_size) then
M_request <= '1';
end if;
end if;
end if;
end process;
M_ABus(0 to C_PLB_AWIDTH - 1) <= req_address;
process(req_nRW, burst_mode, burst_size, req_BE)
variable i:integer;
begin
M_BE <= (others => '0');
if (burst_mode = '1') then
if (burst_size = "0000") then
M_BE <= (others => '1'); -- first single,then burst 16
else
M_BE(0 to 3) <= burst_size; -- fixed length burst
end if;
elsif (req_nRW = '0') then
M_BE <= (others => '1');
else
for i in 0 to PLB_BYTE_COUNT-1 loop
M_BE(i) <= req_BE(i);
end loop;
end if;
end process;
-- user req FIFO, for both read request and write request
U_req_indices_if_fifo: component indices_if_ap_fifo
generic map(
DATA_WIDTH => REQ_FIFO_WIDTH,
ADDR_WIDTH => FIFO_ADDR_WIDTH,
DEPTH => FIFO_DEPTH)
port map(
clk => PLB_Clk,
reset => PLB_Rst,
if_empty_n => req_fifo_empty_n,
if_read => req_fifo_pop,
if_dout => req_fifo_dout,
if_full_n => req_fifo_full_n,
if_write => req_fifo_push,
if_din => req_fifo_din
);
req_fifo_push <= BUS_req_push and not req_burst_write;
req_fifo_din <= BUS_req_nRW & BUS_req_BE & BUS_address & BUS_size;
req_fifo_dout_req_size <= req_fifo_dout(31 downto 0) -1;
process (PLB_Clk, PLB_Rst)
begin
if (PLB_Rst = '1') then
req_burst_write <= '0';
req_burst_write_counter <= (others => '0');
elsif (PLB_Clk'event and PLB_Clk = '1') then
if (req_fifo_push = '1' and BUS_req_nRW = '1' and BUS_size(31 downto 1) /= "0000000000000000000000000000000") then
req_burst_write <= '1';
req_burst_write_counter <= BUS_size - 1;
end if;
if (BUS_req_push = '1' and BUS_req_nRW = '1' and req_burst_write = '1') then
req_burst_write_counter <= req_burst_write_counter -1;
end if;
if (BUS_req_push = '1' and BUS_req_nRW = '1' and req_burst_write_counter = X"00000001") then-- last burst write data
req_burst_write <= '0';
end if;
end if;
end process;
process (PLB_Clk, PLB_Rst)
begin
if (PLB_Rst = '1') then
request <= '0';
req_size <= (others => '0');
req_nRW <= '0';
req_address(0 to C_PLB_AWIDTH - 1) <= (others => '0');
burst_mode <= '0';
burst_size <= (others => '0');
req_fifo_pop <= '0';
elsif (PLB_Clk'event and PLB_Clk = '1') then
req_fifo_pop <= '0';
if ((request = '0' and req_fifo_empty_n = '1') or PLB_MAddrAck = '1') then
if (PLB_MAddrAck = '1' and (burst_mode = '0' or burst_size ="0000") and dataConv_last = '0') then
request <= '1';
if (conv_mode_comb(1) = '1') then -- 2:1 conv
req_BE(PLB_BYTE_COUNT/2-1 downto 0) <= (others => '0');
else -- 128:32
if (req_address(28 to 29) = "00") then
req_BE(PLB_BYTE_COUNT/4-1 downto 0) <= (others => '0');
elsif (req_address(28 to 29) = "01") then
req_BE(PLB_BYTE_COUNT/2-1 downto PLB_BYTE_COUNT/4) <= (others => '0');
elsif (req_address(28 to 29) = "10") then
req_BE(PLB_BYTE_COUNT*3/4-1 downto PLB_BYTE_COUNT/2) <= (others => '0');
end if;
end if;
if (PLB_MSSize = "00") then -- 32 bits slave
req_address <= req_address + 4;
elsif (PLB_MSSize = "01") then -- 64 slave
req_address <= req_address + 8;
end if;-- 128 bits slave does not need conversion cycle
elsif (PLB_MAddrAck = '1' and burst_mode = '1' and burst_last = '0') then
request <= '1'; -- req next burst section, this will be pending until previous burst finished
req_size(0 to 27) <= req_size(0 to 27) - 1;
req_address(0 to C_PLB_AWIDTH - PLB_ADDR_SHIFT - 1) <= req_address(0 to C_PLB_AWIDTH -PLB_ADDR_SHIFT -1) + burst_size +1;
req_address(C_PLB_AWIDTH-PLB_ADDR_SHIFT to C_PLB_AWIDTH-1) <= (others => '0');
-- low bits of addr must be reset for possible data_conv modifications of 10 lines above
burst_mode <= '1';
burst_size <= "1111"; -- burst 16 words
else
if (req_fifo_empty_n = '1') then
req_fifo_pop <= '1';
end if;
request <= req_fifo_empty_n; -- fetch next user_req, may be a vaild req or a null req
req_size(0 to 27) <= req_fifo_dout_req_size(31 downto 4); --remaining burst transfer except current one
req_nRW <= req_fifo_dout(REQ_FIFO_WIDTH-1);
req_BE <= req_fifo_dout(REQ_FIFO_WIDTH-2 downto 64);
req_address <= req_fifo_dout(63 downto 32);
if (req_fifo_dout(REQ_FIFO_WIDTH-1) = '0') then -- read request
req_address(C_PLB_AWIDTH-PLB_ADDR_SHIFT to C_PLB_AWIDTH-1) <= (others => '0');
end if;
-- long burst request will be split to 1stReq: 1-16 words, all next req: 16 words
if (req_fifo_dout_req_size /= X"00000000") then -- more than 1 word, burst
burst_mode <= req_fifo_empty_n; -- fetched req may be null req
-- req of burst 17 will be single + burst 16, please check burst_size also
else
burst_mode <= '0';
end if;
burst_size(3 downto 0) <= req_fifo_dout_req_size(3 downto 0);-- 0:single, 1-15: burst 2-16words
end if;
end if;
end if;
end process;
process (PLB_Clk, PLB_Rst)
begin
if (PLB_Rst = '1') then
pending_read <= '0';
pending_write <= '0';
dp_PLB_MSSize <= (others => '0');
elsif (PLB_Clk'event and PLB_Clk = '1') then
if (PLB_MRdDAck = '1' and
((pending_rd_req_burst_mode = '1' and pending_rd_req_burst_size = "0000" and dp_dataConv_rd_burst_counter = "00") or
(pending_rd_req_burst_mode = '0'))) then
pending_read <= '0';
elsif (PLB_MAddrAck = '1' and req_nRW='0') then
pending_read <= '1';
end if;
if (PLB_MWrDAck = '1' and wr_data_phase = '1' and
((pending_wr_req_burst_mode = '1' and pending_wr_req_burst_size = "0000" and dp_dataConv_wd_burst_counter = "00") or
pending_wr_req_burst_mode = '0')) then
pending_write <= '0';
elsif (PLB_MAddrAck = '1' and req_nRW='1' and
(PLB_MWrDAck = '0' or burst_size /= "0000")) then
pending_write <= '1';
end if;
if (PLB_MAddrAck = '1') then
dp_PLB_MSSize <= PLB_MSSize;
end if;
end if;
end process;
process(req_size)
begin
if (req_size(0 to 27) = "000000000000000000000000000") then
burst_last <= '1'; -- one request is ok
else
burst_last <= '0';
end if;
end process;
-- user write data FIFO, for data of bus write request
U_wd_indices_if_fifo: component indices_if_ap_fifo_uw
generic map(
DATA_WIDTH => PLB_DW,
ADDR_WIDTH => FIFO_ADDR_WIDTH,
DEPTH => FIFO_DEPTH)
port map(
clk => PLB_Clk,
reset => PLB_Rst,
if_empty_n => wd_fifo_empty_n,
if_read => wd_fifo_pop,
if_dout => wd_fifo_dout,
if_full_n => wd_fifo_full_n,
if_write => wd_fifo_push,
if_din => wd_fifo_din,
use_word => wd_fifo_use_word
);
wd_fifo_push <= BUS_req_push and BUS_req_nRW;
wd_fifo_din <= BUS_WrData;
-- returned bus read data fifo
U_rd_indices_if_fifo: component indices_if_ap_fifo_uw
generic map(
DATA_WIDTH => PLB_DW,
ADDR_WIDTH => FIFO_ADDR_WIDTH,
DEPTH => FIFO_DEPTH)
port map(
clk => PLB_Clk,
reset => PLB_Rst,
if_empty_n => rd_fifo_empty_n,
if_read => rd_fifo_pop,
if_dout => rd_fifo_dout,
if_full_n => rd_fifo_full_n,
if_write => rd_fifo_push,
if_din => rd_fifo_din,
use_word => rd_fifo_use_word
);
process (PLB_Clk, PLB_Rst)
begin
if (PLB_Rst = '1') then
dp_dataConv_rd_conv_mode <= (others =>'0');
dp_dataConv_rd_burst_counter <= (others => '0');
dp_dataConv_rd_burst_counter_reg <= (others => '0');
PLB_MRdDAck_reg <= '0';
elsif (PLB_Clk'event and PLB_Clk = '1') then
if (PLB_MAddrAck = '1' and req_nRW = '0' and dp_dataConv_rd_conv_mode = "00") then
dp_dataConv_rd_conv_mode <= conv_mode_comb;
dp_dataConv_rd_burst_counter <= conv_counter_comb;
end if;
if (PLB_MRdDAck = '1' and
((pending_rd_req_burst_mode = '1' and (pending_rd_req_burst_size = "0000" and dp_dataConv_rd_burst_counter = "00")) or
(pending_rd_req_burst_mode = '0' and dp_dataConv_rd_burst_counter = "00")))then
dp_dataConv_rd_conv_mode <= "00";
end if;
if (PLB_MRdDAck = '1' and
((pending_rd_req_burst_mode = '1' and (pending_rd_req_burst_size /= "0000" or dp_dataConv_rd_burst_counter /= "00")) or
(pending_rd_req_burst_mode = '0' and dp_dataConv_rd_burst_counter /= "00")))then
if (dp_dataConv_rd_burst_counter = "00") then
if (dp_dataConv_rd_conv_mode = "01") then -- 128/32
dp_dataConv_rd_burst_counter <= "11";
elsif (dp_dataConv_rd_conv_mode(1) = '1') then -- 64/32 or 128/64
dp_dataConv_rd_burst_counter <= "01";
end if;
else
dp_dataConv_rd_burst_counter <= dp_dataConv_rd_burst_counter -1;
end if;
end if;
dp_dataConv_rd_burst_counter_reg <= dp_dataConv_rd_burst_counter;
PLB_MRdDAck_reg <= PLB_MRdDAck;
end if;
end process;
rd_fifo_push <= '1' when PLB_MRdDAck_reg = '1' and dp_dataConv_rd_burst_counter_reg = "00" else '0';
process(PLB_MRdDBus)
variable i: integer;
begin
-- change to little endian
for i in 0 to C_PLB_DWIDTH-1 loop
PLB_MRdDBus_reverse(i) <= PLB_MRdDBus(i);
end loop;
end process;
process(PLB_Clk, PLB_Rst)
begin
if (PLB_Rst = '1') then
rd_fifo_din <= (others => '0');
elsif (PLB_Clk'event and PLB_Clk = '1') then
if (PLB_MRdDAck = '1') then
case dp_dataConv_rd_conv_mode is
when "00" => rd_fifo_din <= PLB_MRdDBus_reverse;
when "10" | "11" =>
if (dp_dataConv_rd_burst_counter = "00") then
rd_fifo_din(PLB_DW-1 downto PLB_DW/2) <= PLB_MRdDBus_reverse(PLB_DW/2-1 downto 0);
else
rd_fifo_din(PLB_DW/2-1 downto 0) <= PLB_MRdDBus_reverse(PLB_DW/2-1 downto 0);
end if;
when "01" =>
case dp_dataConv_rd_burst_counter is
when "00" =>
rd_fifo_din(PLB_DW-1 downto PLB_DW*3/4) <= PLB_MRdDBus_reverse(PLB_DW/4-1 downto 0);
when "01" =>
rd_fifo_din(PLB_DW*3/4-1 downto PLB_DW/2) <= PLB_MRdDBus_reverse(PLB_DW/4-1 downto 0);
when "10" =>
rd_fifo_din(PLB_DW/2-1 downto PLB_DW/4) <= PLB_MRdDBus_reverse(PLB_DW/4-1 downto 0);
when "11" =>
rd_fifo_din(PLB_DW/4-1 downto 0) <= PLB_MRdDBus_reverse(PLB_DW/4-1 downto 0);
when others => null;
end case;
when others => null;
end case;
end if;
end if;
end process;
rd_fifo_pop <= BUS_rsp_pop;
pending_read_req_p: process (PLB_Clk, PLB_Rst)
begin
if (PLB_Rst = '1') then
pending_rd_req_burst_mode <= '0';
pending_rd_req_burst_size <= (others => '0');
elsif (PLB_Clk'event and PLB_Clk = '1') then
if (PLB_MAddrAck = '1' and req_nRW = '0') then
if (burst_mode = '1' and burst_size /= "0000") then
pending_rd_req_burst_mode <= burst_mode;
end if;
pending_rd_req_burst_size <= burst_size;
elsif (PLB_MRdDAck = '1' and pending_rd_req_burst_mode = '1') then
if (dp_dataConv_rd_burst_counter = "00") then
pending_rd_req_burst_size <= pending_rd_req_burst_size - 1;
if (pending_rd_req_burst_size = "0000") then
pending_rd_req_burst_mode <= '0';
end if;
end if;
end if;
end if;
end process;
pending_write_req_p: process (PLB_Clk, PLB_Rst)
begin
if (PLB_Rst = '1') then
pending_wr_req_burst_mode <= '0';
pending_wr_req_burst_size <= (others => '0');
elsif (PLB_Clk'event and PLB_Clk = '1') then
if (PLB_MAddrAck = '1' and req_nRW = '1') then
if (burst_mode = '1' and burst_size /= "0000") then
pending_wr_req_burst_mode <= '1';
end if;
pending_wr_req_burst_size <= burst_size;
if (PLB_MWrDAck = '1') then
if (conv_counter_comb = "00") then
pending_wr_req_burst_size <= burst_size -1;
else
pending_wr_req_burst_size <= burst_size;
end if;
end if;
elsif (PLB_MWrDAck = '1' and pending_wr_req_burst_mode = '1') then
if (dp_dataConv_wd_burst_counter = "00") then
pending_wr_req_burst_size <= pending_wr_req_burst_size - 1;
if (pending_wr_req_burst_size = "0000") then
pending_wr_req_burst_mode <= '0';
end if;
end if;
end if;
end if;
end process;
end IMP;
| lgpl-3.0 | cb36fe7a781b26ae2a7a936430aa4a9a | 0.533836 | 3.320335 | false | false | false | false |
takeshineshiro/fpga_fibre_scan | HUCB2P0_150701/adc/ADC_DDIO.vhd | 1 | 4,079 | -- megafunction wizard: %ALTDDIO_IN%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: ALTDDIO_IN
-- ============================================================
-- File Name: ADC_DDIO.vhd
-- Megafunction Name(s):
-- ALTDDIO_IN
--
-- Simulation Library Files(s):
-- altera_mf
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 12.1 Build 243 01/31/2013 SP 1 SJ Full Version
-- ************************************************************
--Copyright (C) 1991-2012 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY altera_mf;
USE altera_mf.altera_mf_components.all;
ENTITY ADC_DDIO IS
PORT
(
datain : IN STD_LOGIC_VECTOR (5 DOWNTO 0);
inclock : IN STD_LOGIC ;
dataout_h : OUT STD_LOGIC_VECTOR (5 DOWNTO 0);
dataout_l : OUT STD_LOGIC_VECTOR (5 DOWNTO 0)
);
END ADC_DDIO;
ARCHITECTURE SYN OF adc_ddio IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (5 DOWNTO 0);
SIGNAL sub_wire1 : STD_LOGIC_VECTOR (5 DOWNTO 0);
BEGIN
dataout_h <= sub_wire0(5 DOWNTO 0);
dataout_l <= sub_wire1(5 DOWNTO 0);
ALTDDIO_IN_component : ALTDDIO_IN
GENERIC MAP (
intended_device_family => "Cyclone V",
invert_input_clocks => "OFF",
lpm_hint => "UNUSED",
lpm_type => "altddio_in",
power_up_high => "OFF",
width => 6
)
PORT MAP (
datain => datain,
inclock => inclock,
dataout_h => sub_wire0,
dataout_l => sub_wire1
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone V"
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone V"
-- Retrieval info: CONSTANT: INVERT_INPUT_CLOCKS STRING "OFF"
-- Retrieval info: CONSTANT: LPM_HINT STRING "UNUSED"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "altddio_in"
-- Retrieval info: CONSTANT: POWER_UP_HIGH STRING "OFF"
-- Retrieval info: CONSTANT: WIDTH NUMERIC "6"
-- Retrieval info: USED_PORT: datain 0 0 6 0 INPUT NODEFVAL "datain[5..0]"
-- Retrieval info: CONNECT: @datain 0 0 6 0 datain 0 0 6 0
-- Retrieval info: USED_PORT: dataout_h 0 0 6 0 OUTPUT NODEFVAL "dataout_h[5..0]"
-- Retrieval info: CONNECT: dataout_h 0 0 6 0 @dataout_h 0 0 6 0
-- Retrieval info: USED_PORT: dataout_l 0 0 6 0 OUTPUT NODEFVAL "dataout_l[5..0]"
-- Retrieval info: CONNECT: dataout_l 0 0 6 0 @dataout_l 0 0 6 0
-- Retrieval info: USED_PORT: inclock 0 0 0 0 INPUT_CLK_EXT NODEFVAL "inclock"
-- Retrieval info: CONNECT: @inclock 0 0 0 0 inclock 0 0 0 0
-- Retrieval info: GEN_FILE: TYPE_NORMAL ADC_DDIO.vhd TRUE FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL ADC_DDIO.qip TRUE FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL ADC_DDIO.bsf TRUE TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL ADC_DDIO_inst.vhd TRUE TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL ADC_DDIO.inc TRUE TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL ADC_DDIO.cmp TRUE TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL ADC_DDIO.ppf TRUE FALSE
-- Retrieval info: LIB_FILE: altera_mf
| apache-2.0 | 9630f7fe17cbb7e00794f73408f6d49f | 0.631772 | 3.606543 | false | false | false | false |
grwlf/vsim | vhdl_ct/ct00010.vhd | 1 | 4,002 | -- NEED RESULT: ENT00010: Unassociated composite generics with static subtypes take on default expression failed
-------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
-------------------------------------------------------------------------------
--
-- TEST NAME:
--
-- CT00010
--
-- AUTHOR:
--
-- A. Wilmot
--
-- TEST OBJECTIVES:
--
-- 1.1.1.1 (1)
--
-- DESIGN UNIT ORDERING:
--
-- ENT00010(ARCH00010)
-- ENT00010_Test_Bench(ARCH00010_Test_Bench)
--
-- REVISION HISTORY:
--
-- 26-JUN-1987 - initial revision
--
-- NOTES:
--
-- self-checking
-- automatically generated
--
use WORK.STANDARD_TYPES.all ;
entity ENT00010 is
generic (
i_bit_vector_1, i_bit_vector_2 : bit_vector
:= c_st_bit_vector_1 ;
i_string_1, i_string_2 : string
:= c_st_string_1 ;
i_t_rec1_1, i_t_rec1_2 : t_rec1
:= c_st_rec1_1 ;
i_st_rec1_1, i_st_rec1_2 : st_rec1
:= c_st_rec1_1 ;
i_t_rec2_1, i_t_rec2_2 : t_rec2
:= c_st_rec2_1 ;
i_st_rec2_1, i_st_rec2_2 : st_rec2
:= c_st_rec2_1 ;
i_t_rec3_1, i_t_rec3_2 : t_rec3
:= c_st_rec3_1 ;
i_st_rec3_1, i_st_rec3_2 : st_rec3
:= c_st_rec3_1 ;
i_t_arr1_1, i_t_arr1_2 : t_arr1
:= c_st_arr1_1 ;
i_st_arr1_1, i_st_arr1_2 : st_arr1
:= c_st_arr1_1 ;
i_t_arr2_1, i_t_arr2_2 : t_arr2
:= c_st_arr2_1 ;
i_st_arr2_1, i_st_arr2_2 : st_arr2
:= c_st_arr2_1 ;
i_t_arr3_1, i_t_arr3_2 : t_arr3
:= c_st_arr3_1 ;
i_st_arr3_1, i_st_arr3_2 : st_arr3
:= c_st_arr3_1
) ;
begin
end ENT00010 ;
--
architecture ARCH00010 of ENT00010 is
begin
process
variable correct : boolean := true ;
begin
correct := correct and i_bit_vector_1 = c_st_bit_vector_1
and i_bit_vector_2 = c_st_bit_vector_1 ;
correct := correct and i_string_1 = c_st_string_1
and i_string_2 = c_st_string_1 ;
correct := correct and i_t_rec1_1 = c_st_rec1_1
and i_t_rec1_2 = c_st_rec1_1 ;
correct := correct and i_st_rec1_1 = c_st_rec1_1
and i_st_rec1_2 = c_st_rec1_1 ;
correct := correct and i_t_rec2_1 = c_st_rec2_1
and i_t_rec2_2 = c_st_rec2_1 ;
correct := correct and i_st_rec2_1 = c_st_rec2_1
and i_st_rec2_2 = c_st_rec2_1 ;
correct := correct and i_t_rec3_1 = c_st_rec3_1
and i_t_rec3_2 = c_st_rec3_1 ;
correct := correct and i_st_rec3_1 = c_st_rec3_1
and i_st_rec3_2 = c_st_rec3_1 ;
correct := correct and i_t_arr1_1 = c_st_arr1_1
and i_t_arr1_2 = c_st_arr1_1 ;
correct := correct and i_st_arr1_1 = c_st_arr1_1
and i_st_arr1_2 = c_st_arr1_1 ;
correct := correct and i_t_arr2_1 = c_st_arr2_1
and i_t_arr2_2 = c_st_arr2_1 ;
correct := correct and i_st_arr2_1 = c_st_arr2_1
and i_st_arr2_2 = c_st_arr2_1 ;
correct := correct and i_t_arr3_1 = c_st_arr3_1
and i_t_arr3_2 = c_st_arr3_1 ;
correct := correct and i_st_arr3_1 = c_st_arr3_1
and i_st_arr3_2 = c_st_arr3_1 ;
test_report ( "ENT00010" ,
"Unassociated composite generics with static subtypes" &
" take on default expression" ,
correct) ;
wait ;
end process ;
end ARCH00010 ;
--
entity ENT00010_Test_Bench is
end ENT00010_Test_Bench ;
--
architecture ARCH00010_Test_Bench of ENT00010_Test_Bench is
begin
L1:
block
component UUT
end component ;
for CIS1 : UUT use entity WORK.ENT00010 ( ARCH00010 ) ;
begin
CIS1 : UUT ;
end block L1 ;
end ARCH00010_Test_Bench ;
| gpl-3.0 | f4a3b163937edc9226f66e0d6a9ad68b | 0.491004 | 2.735475 | false | true | false | false |
grwlf/vsim | vhdl_ct/ct00511.vhd | 1 | 5,602 | -- NEED RESULT: ARCH00511: The expression in an initialization specification may be globally static passed
-------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
-------------------------------------------------------------------------------
--
-- TEST NAME:
--
-- CT00511
--
-- AUTHOR:
--
-- G. Tominovich
--
-- TEST OBJECTIVES:
--
-- 5.2 (5)
-- 5.2 (6)
-- 5.2 (8)
-- 5.2 (10)
--
-- DESIGN UNIT ORDERING:
--
-- ENT00511(ARCH00511)
-- ENT00511_Test_Bench(ARCH00511_Test_Bench)
--
-- REVISION HISTORY:
--
-- 10-AUG-1987 - initial revision
--
-- NOTES:
--
-- self-checking
--
use WORK.STANDARD_TYPES.all ;
entity ENT00511 is
generic (
g_boolean_1 : in boolean
; g_bit_1 : in bit
; g_severity_level_1 : in severity_level
; g_character_1 : in character
; g_st_enum1_1 : in st_enum1
; g_integer_1 : in integer
; g_st_int1_1 : in st_int1
; g_time_1 : in time
; g_st_phys1_1 : in st_phys1
; g_real_1 : in real
; g_st_real1_1 : in st_real1
; g_st_rec1_1 : in st_rec1
; g_st_rec2_1 : in st_rec2
; g_st_rec3_1 : in st_rec3
; g_st_arr1_1 : in st_arr1
; g_st_arr2_1 : in st_arr2
; g_st_arr3_1 : in st_arr3
);
end ENT00511;
--
--
architecture ARCH00511 of ENT00511 is
signal S_boolean : boolean := g_boolean_1 ;
--
signal S_bit : bit := g_bit_1 ;
--
signal S_severity_level : severity_level := g_severity_level_1 ;
--
signal S_character : character := g_character_1 ;
--
signal S_st_enum1 : st_enum1 := g_st_enum1_1 ;
--
signal S_integer : integer := g_integer_1 ;
--
signal S_st_int1 : st_int1 := g_st_int1_1 ;
--
signal S_time : time := g_time_1 ;
--
signal S_st_phys1 : st_phys1 := g_st_phys1_1 ;
--
signal S_real : real := g_real_1 ;
--
signal S_st_real1 : st_real1 := g_st_real1_1 ;
--
signal S_st_rec1 : st_rec1 := g_st_rec1_1 ;
--
signal S_st_rec2 : st_rec2 := g_st_rec2_1 ;
--
signal S_st_rec3 : st_rec3 := g_st_rec3_1 ;
--
signal S_st_arr1 : st_arr1 := g_st_arr1_1 ;
--
signal S_st_arr2 : st_arr2 := g_st_arr2_1 ;
--
signal S_st_arr3 : st_arr3 := g_st_arr3_1 ;
--
--
begin
process
variable correct : boolean := true;
begin
correct := correct and
(S_boolean = c_boolean_1) ;
correct := correct and
(S_bit = c_bit_1) ;
correct := correct and
(S_severity_level = c_severity_level_1) ;
correct := correct and
(S_character = c_character_1) ;
correct := correct and
(S_st_enum1 = c_st_enum1_1) ;
correct := correct and
(S_integer = c_integer_1) ;
correct := correct and
(S_st_int1 = c_st_int1_1) ;
correct := correct and
(S_time = c_time_1) ;
correct := correct and
(S_st_phys1 = c_st_phys1_1) ;
correct := correct and
(S_real = c_real_1) ;
correct := correct and
(S_st_real1 = c_st_real1_1) ;
correct := correct and
(S_st_rec1 = c_st_rec1_1) ;
correct := correct and
(S_st_rec2 = c_st_rec2_1) ;
correct := correct and
(S_st_rec3 = c_st_rec3_1) ;
correct := correct and
(S_st_arr1 = c_st_arr1_1) ;
correct := correct and
(S_st_arr2 = c_st_arr2_1) ;
correct := correct and
(S_st_arr3 = c_st_arr3_1) ;
test_report ( "ARCH00511" ,
"The expression in an initialization specification "&
"may be globally static" ,
correct );
wait ;
end process ;
end ARCH00511 ;
--
--
entity ENT00511_Test_Bench is
end ENT00511_Test_Bench ;
--
use WORK.STANDARD_TYPES.all ;
architecture ARCH00511_Test_Bench of ENT00511_Test_Bench is
begin
L1:
block
component UUT
generic (
g_boolean_1 : in boolean
; g_bit_1 : in bit
; g_severity_level_1 : in severity_level
; g_character_1 : in character
; g_st_enum1_1 : in st_enum1
; g_integer_1 : in integer
; g_st_int1_1 : in st_int1
; g_time_1 : in time
; g_st_phys1_1 : in st_phys1
; g_real_1 : in real
; g_st_real1_1 : in st_real1
; g_st_rec1_1 : in st_rec1
; g_st_rec2_1 : in st_rec2
; g_st_rec3_1 : in st_rec3
; g_st_arr1_1 : in st_arr1
; g_st_arr2_1 : in st_arr2
; g_st_arr3_1 : in st_arr3
) ;
end component ;
for CIS1 : UUT use entity WORK.ENT00511 ( ARCH00511 ) ;
begin
CIS1 : UUT
generic map (
c_boolean_1
, c_bit_1
, c_severity_level_1
, c_character_1
, c_st_enum1_1
, c_integer_1
, c_st_int1_1
, c_time_1
, c_st_phys1_1
, c_real_1
, c_st_real1_1
, c_st_rec1_1
, c_st_rec2_1
, c_st_rec3_1
, c_st_arr1_1
, c_st_arr2_1
, c_st_arr3_1
)
;
end block L1 ;
end ARCH00511_Test_Bench ;
| gpl-3.0 | 28e3d20479df4e3393ce2de16a99e22e | 0.461799 | 3.018319 | false | true | false | false |
grwlf/vsim | vhdl_ct/ct00520.vhd | 1 | 11,850 | -------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
-------------------------------------------------------------------------------
--
-- TEST NAME:
--
-- CT00520
--
-- AUTHOR:
--
-- A. Wilmot
--
-- TEST OBJECTIVES:
--
-- 7.3.2.2 (12)
-- 7.3.2.2 (15)
-- 7.3.2.2 (16)
--
-- DESIGN UNIT ORDERING:
--
-- PKG00520
-- ENT00520(ARCH00520)
-- ENT00520_Test_Bench(ARCH00520_Test_Bench)
--
-- REVISION HISTORY:
--
-- 12-AUG-1987 - initial revision
-- 11-APR-1988 - JW: Test was really bogus.
--
-- NOTES:
--
-- self-checking
--
package PKG00520 is
type rec_1 is record
f1 : integer ;
f2 : boolean ;
end record ;
subtype brange is integer range 4 downto 0 ;
subtype crange is integer range 1 downto 1 ;
subtype drange is integer range 0 to 2 ;
type arr_1 is array ( boolean range <> , crange range <> )
of rec_1 ;
type time_matrix is array ( drange range <> , brange range <> )
of time ;
type bit_matrix is array ( brange range <> , drange range <> )
of bit ;
type bit_arr_vec is array ( brange range <> ) of bit_vector
( 0 to 2 ) ;
end PKG00520 ;
use WORK.STANDARD_TYPES.all ;
use WORK.PKG00520.all ;
entity ENT00520 is
generic (
g_arr_1 : arr_1 ;
g_time_matrix : time_matrix ;
g_bit_matrix : bit_matrix ;
g_bitarr_vec : bit_arr_vec ;
g_string : string ;
g_bit_vector : bit_vector
) ;
-- JW: Added defaults to ports.
port (
p_arr_1 : arr_1 := ( (1 => (1, true)), (1 => (0, false)) ) ;
p_time_matrix : time_matrix := ( (15 ns, 15ms, 15 ps, 15 fs, 9 ns),
(10 ns, 10ms, 10 ps, 10 fs, 6 ns),
(5 ns, 5ms, 5 ps, 5 fs, 3 ns) ) ;
p_bit_matrix : bit_matrix := ( B"000", B"001", B"010", B"011", B"111" ) ;
p_bitarr_vec : bit_arr_vec := ( B"000", B"001", B"010", B"011", B"111" ) ;
p_string : string := ( "abcDEF" ) ;
p_bit_vector : bit_vector := ( ('1', '0', '0') )
) ;
procedure p1 (
p_arr_1 : arr_1 ;
p_time_matrix : time_matrix ;
p_bit_matrix : bit_matrix ;
p_bitarr_vec : bit_arr_vec ;
p_string : string ;
p_bit_vector : bit_vector
) is
variable correct : boolean := true ;
subtype rg_arr_11 is boolean range g_arr_1'range(1) ;
subtype rg_arr_12 is integer range g_arr_1'range(2) ;
subtype rg_time_matrix1 is integer range g_time_matrix'range(1) ;
subtype rg_time_matrix2 is integer range g_time_matrix'range(2) ;
subtype rg_bit_matrix1 is integer range g_bit_matrix'range(1) ;
subtype rg_bit_matrix2 is integer range g_bit_matrix'range(2) ;
subtype rg_bitarr_vec1 is integer range g_bitarr_vec'range(1) ;
subtype rg_string is integer range g_string'range ;
subtype rg_bit_vector is integer range g_bit_vector'range ;
subtype rp_arr_11 is boolean range p_arr_1'range(1) ;
subtype rp_arr_12 is integer range p_arr_1'range(2) ;
subtype rp_time_matrix1 is integer range p_time_matrix'range(1) ;
subtype rp_time_matrix2 is integer range p_time_matrix'range(2) ;
subtype rp_bit_matrix1 is integer range p_bit_matrix'range(1) ;
subtype rp_bit_matrix2 is integer range p_bit_matrix'range(2) ;
subtype rp_bitarr_vec1 is integer range p_bitarr_vec'range(1) ;
subtype rp_string is integer range p_string'range ;
subtype rp_bit_vector is integer range p_bit_vector'range ;
begin
correct := correct and rg_arr_11'left <= rg_arr_11'right ;
correct := correct and rg_arr_11'left = false and
rg_arr_11'right = true ;
correct := correct and rg_arr_12'right <= rg_arr_12'left ;
correct := correct and rg_arr_12'left = 1 and
rg_arr_12'right = 1 ;
correct := correct and rg_time_matrix1'left <=
rg_time_matrix1'right ;
correct := correct and rg_time_matrix1'left = 0 and
rg_time_matrix1'right = 2 ;
correct := correct and rg_time_matrix2'right <=
rg_time_matrix2'left ;
correct := correct and rg_time_matrix2'left = 4 and
rg_time_matrix2'right = 0 ;
correct := correct and rg_bit_matrix1'right <=
rg_bit_matrix1'left ;
correct := correct and rg_bit_matrix1'left = 4 and
rg_bit_matrix1'right = 0 ;
correct := correct and rg_bit_matrix2'left <=
rg_bit_matrix2'right ;
correct := correct and rg_bit_matrix2'left = 0 and
rg_bit_matrix2'right = 2 ;
correct := correct and rg_bitarr_vec1'right <=
rg_bitarr_vec1'left ;
correct := correct and rg_bitarr_vec1'left = 4 and
rg_bitarr_vec1'right = 0 ;
correct := correct and rg_string'left <=
rg_string'right ;
correct := correct and rg_string'left = 1 and
rg_string'right = 6 ;
correct := correct and rg_bit_vector'left <=
rg_bit_vector'right ;
correct := correct and rg_bit_vector'left = 0 and
rg_bit_vector'right = 2 ;
correct := correct and rp_arr_11'left <= rp_arr_11'right ;
correct := correct and rp_arr_11'left = false and
rp_arr_11'right = true ;
correct := correct and rp_arr_12'right <= rp_arr_12'left ;
correct := correct and rp_arr_12'left = 1 and
rp_arr_12'right = 1 ;
correct := correct and rp_time_matrix1'left <=
rp_time_matrix1'right ;
correct := correct and rp_time_matrix1'left = 0 and
rp_time_matrix1'right = 2 ;
correct := correct and rp_time_matrix2'right <=
rp_time_matrix2'left ;
correct := correct and rp_time_matrix2'left = 4 and
rp_time_matrix2'right = 0 ;
correct := correct and rp_bit_matrix1'right <=
rp_bit_matrix1'left ;
correct := correct and rp_bit_matrix1'left = 4 and
rp_bit_matrix1'right = 0 ;
correct := correct and rp_bit_matrix2'left <=
rp_bit_matrix2'right ;
correct := correct and rp_bit_matrix2'left = 0 and
rp_bit_matrix2'right = 2 ;
correct := correct and rp_bitarr_vec1'right <=
rp_bitarr_vec1'left ;
correct := correct and rp_bitarr_vec1'left = 4 and
rp_bitarr_vec1'right = 0 ;
correct := correct and rp_string'left <=
rp_string'right ;
correct := correct and rp_string'left = 1 and
rp_string'right = 6 ;
correct := correct and rp_bit_vector'left <=
rp_bit_vector'right ;
correct := correct and rp_bit_vector'left = 0 and
rp_bit_vector'right = 2 ;
test_report ( "ARCH00520" ,
"Positional aggregates associated with unconstrained"
& " generics and parameters" ,
correct ) ;
end p1 ;
end ENT00520 ;
architecture ARCH00520 of ENT00520 is
begin
process
variable correct : boolean := true ;
subtype rp_arr_11 is boolean range p_arr_1'range(1) ;
subtype rp_arr_12 is integer range p_arr_1'range(2) ;
subtype rp_time_matrix1 is integer range p_time_matrix'range(1) ;
subtype rp_time_matrix2 is integer range p_time_matrix'range(2) ;
subtype rp_bit_matrix1 is integer range p_bit_matrix'range(1) ;
subtype rp_bit_matrix2 is integer range p_bit_matrix'range(2) ;
subtype rp_bitarr_vec1 is integer range p_bitarr_vec'range(1) ;
subtype rp_string is integer range p_string'range ;
subtype rp_bit_vector is integer range p_bit_vector'range ;
begin
p1 (
( (1 => (1, true)), (1 => (0, false)) ) ,
( (15 ns, 15ms, 15 ps, 15 fs, 9 ns),
(10 ns, 10ms, 10 ps, 10 fs, 6 ns),
(5 ns, 5ms, 5 ps, 5 fs, 3 ns) ) ,
( B"000", B"001", B"010", B"011", B"111" ) ,
( B"000", B"001", B"010", B"011", B"111" ) ,
( "abcDEF" ) ,
( ('1', '0', '0') )
) ;
correct := correct and rp_arr_11'left <= rp_arr_11'right ;
correct := correct and rp_arr_11'left = false and
rp_arr_11'right = true ;
correct := correct and rp_arr_12'right <= rp_arr_12'left ;
correct := correct and rp_arr_12'left = 1 and
rp_arr_12'right = 1 ;
correct := correct and rp_time_matrix1'left <=
rp_time_matrix1'right ;
correct := correct and rp_time_matrix1'left = 0 and
rp_time_matrix1'right = 2 ;
correct := correct and rp_time_matrix2'right <=
rp_time_matrix2'left ;
correct := correct and rp_time_matrix2'left = 4 and
rp_time_matrix2'right = 0 ;
correct := correct and rp_bit_matrix1'right <=
rp_bit_matrix1'left ;
correct := correct and rp_bit_matrix1'left = 4 and
rp_bit_matrix1'right = 0 ;
correct := correct and rp_bit_matrix2'left <=
rp_bit_matrix2'right ;
correct := correct and rp_bit_matrix2'left = 0 and
rp_bit_matrix2'right = 2 ;
correct := correct and rp_bitarr_vec1'right <=
rp_bitarr_vec1'left ;
correct := correct and rp_bitarr_vec1'left = 4 and
rp_bitarr_vec1'right = 0 ;
correct := correct and rp_string'left <=
rp_string'right ;
correct := correct and rp_string'left = 1 and
rp_string'right = 6 ;
correct := correct and rp_bit_vector'left <=
rp_bit_vector'right ;
correct := correct and rp_bit_vector'left = 0 and
rp_bit_vector'right = 2 ;
test_report ( "ARCH00520" ,
"Positional aggregates associated with unconstrained"
& " signals" ,
correct ) ;
wait ;
end process ;
end ARCH00520 ;
use WORK.PKG00520.all ;
entity ENT00520_Test_Bench is
end ENT00520_Test_Bench ;
architecture ARCH00520_Test_Bench of ENT00520_Test_Bench is
begin
L1:
block
component UUT
-- JW: Generic ports were missing here
generic (
g_arr_1 : arr_1 ;
g_time_matrix : time_matrix ;
g_bit_matrix : bit_matrix ;
g_bitarr_vec : bit_arr_vec ;
g_string : string ;
g_bit_vector : bit_vector
) ;
end component ;
for CIS1 : UUT use entity WORK.ENT00520 ( ARCH00520 ) ;
begin
CIS1 : UUT
generic map (
( (1 => (1, true)), (1 => (0, false)) ),
( (15 ns, 15ms, 15 ps, 15 fs, 9 ns),
(10 ns, 10ms, 10 ps, 10 fs, 6 ns),
(5 ns, 5ms, 5 ps, 5 fs, 3 ns) ) ,
( B"000", B"001", B"010", B"011", B"111" ) ,
( B"000", B"001", B"010", B"011", B"111" ) ,
( "abcDEF" ) ,
( ('1', '0', '0') )
);
-- JW: Removed port map which was attempting to associate literals with ports.
end block L1 ;
end ARCH00520_Test_Bench ;
| gpl-3.0 | 3bd5f602d0fca5ffe6a72b494fab4990 | 0.513755 | 3.639435 | false | false | false | false |
TWW12/lzw | ip_repo/axi_compression_1.0/hdl/axi_compression_v1_0_S00_AXI.vhd | 3 | 24,405 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity axi_compression_v1_0_S00_AXI is
generic (
-- Users to add parameters here
-- User parameters ends
-- Do not modify the parameters beyond this line
-- Width of S_AXI data bus
C_S_AXI_DATA_WIDTH : integer := 32;
-- Width of S_AXI address bus
C_S_AXI_ADDR_WIDTH : integer := 6
);
port (
-- Users to add ports here
-- User ports ends
-- Do not modify the ports beyond this line
-- Global Clock Signal
S_AXI_ACLK : in std_logic;
-- Global Reset Signal. This Signal is Active LOW
S_AXI_ARESETN : in std_logic;
-- Write address (issued by master, acceped by Slave)
S_AXI_AWADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
-- Write channel Protection type. This signal indicates the
-- privilege and security level of the transaction, and whether
-- the transaction is a data access or an instruction access.
S_AXI_AWPROT : in std_logic_vector(2 downto 0);
-- Write address valid. This signal indicates that the master signaling
-- valid write address and control information.
S_AXI_AWVALID : in std_logic;
-- Write address ready. This signal indicates that the slave is ready
-- to accept an address and associated control signals.
S_AXI_AWREADY : out std_logic;
-- Write data (issued by master, acceped by Slave)
S_AXI_WDATA : in std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
-- Write strobes. This signal indicates which byte lanes hold
-- valid data. There is one write strobe bit for each eight
-- bits of the write data bus.
S_AXI_WSTRB : in std_logic_vector((C_S_AXI_DATA_WIDTH/8)-1 downto 0);
-- Write valid. This signal indicates that valid write
-- data and strobes are available.
S_AXI_WVALID : in std_logic;
-- Write ready. This signal indicates that the slave
-- can accept the write data.
S_AXI_WREADY : out std_logic;
-- Write response. This signal indicates the status
-- of the write transaction.
S_AXI_BRESP : out std_logic_vector(1 downto 0);
-- Write response valid. This signal indicates that the channel
-- is signaling a valid write response.
S_AXI_BVALID : out std_logic;
-- Response ready. This signal indicates that the master
-- can accept a write response.
S_AXI_BREADY : in std_logic;
-- Read address (issued by master, acceped by Slave)
S_AXI_ARADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
-- Protection type. This signal indicates the privilege
-- and security level of the transaction, and whether the
-- transaction is a data access or an instruction access.
S_AXI_ARPROT : in std_logic_vector(2 downto 0);
-- Read address valid. This signal indicates that the channel
-- is signaling valid read address and control information.
S_AXI_ARVALID : in std_logic;
-- Read address ready. This signal indicates that the slave is
-- ready to accept an address and associated control signals.
S_AXI_ARREADY : out std_logic;
-- Read data (issued by slave)
S_AXI_RDATA : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
-- Read response. This signal indicates the status of the
-- read transfer.
S_AXI_RRESP : out std_logic_vector(1 downto 0);
-- Read valid. This signal indicates that the channel is
-- signaling the required read data.
S_AXI_RVALID : out std_logic;
-- Read ready. This signal indicates that the master can
-- accept the read data and response information.
S_AXI_RREADY : in std_logic
);
end axi_compression_v1_0_S00_AXI;
architecture arch_imp of axi_compression_v1_0_S00_AXI is
signal lzw_rst : std_logic;
signal input_fifo_wr_en : std_logic;
signal input_fifo_rd_en : std_logic;
signal input_fifo_output : std_logic_vector(7 downto 0);
signal input_fifo_full : std_logic_vector(31 downto 0);
signal input_fifo_empty : std_logic;
signal input_fifo_not_empty : std_logic;
signal input_fifo_wr_ack : std_logic_vector(31 downto 0);
signal output_fifo_rd_en : std_logic;
signal output_fifo_wr_en : std_logic;
signal output_fifo_din : std_logic_vector(11 downto 0);
signal output_fifo_dout : std_logic_vector(31 downto 0);
signal output_fifo_full : std_logic_vector(31 downto 0);
signal output_fifo_empty : std_logic_vector(31 downto 0);
signal output_fifo_valid : std_logic_vector(31 downto 0);
signal compression_done : std_logic_vector(31 downto 0);
signal clock_count : std_logic_vector(31 downto 0);
--Input FIFO for compression
COMPONENT input_fifo
PORT (
clk : IN STD_LOGIC;
srst : IN STD_LOGIC;
din : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
wr_en : IN STD_LOGIC;
rd_en : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
full : OUT STD_LOGIC;
empty : OUT STD_LOGIC;
wr_ack : OUT STD_LOGIC
);
END COMPONENT;
--Output FIFO for decompressed results
COMPONENT output_fifo
PORT (
clk : IN STD_LOGIC;
srst : IN STD_LOGIC;
din : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
wr_en : IN STD_LOGIC;
rd_en : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
full : OUT STD_LOGIC;
empty : OUT STD_LOGIC;
valid : OUT STD_LOGIC
);
END COMPONENT;
COMPONENT clock_counter
PORT (
enable : IN STD_LOGIC;
count : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
done : IN STD_LOGIC;
clk : IN STD_LOGIC;
rst : IN STD_LOGIC
);
END COMPONENT;
-- AXI4LITE signals
signal axi_awaddr : std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
signal axi_awready : std_logic;
signal axi_wready : std_logic;
signal axi_bresp : std_logic_vector(1 downto 0);
signal axi_bvalid : std_logic;
signal axi_araddr : std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
signal axi_arready : std_logic;
signal axi_rdata : std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal axi_rresp : std_logic_vector(1 downto 0);
signal axi_rvalid : std_logic;
-- Example-specific design signals
-- local parameter for addressing 32 bit / 64 bit C_S_AXI_DATA_WIDTH
-- ADDR_LSB is used for addressing 32/64 bit registers/memories
-- ADDR_LSB = 2 for 32 bits (n downto 2)
-- ADDR_LSB = 3 for 64 bits (n downto 3)
constant ADDR_LSB : integer := (C_S_AXI_DATA_WIDTH/32)+ 1;
constant OPT_MEM_ADDR_BITS : integer := 3;
------------------------------------------------
---- Signals for user logic register space example
--------------------------------------------------
---- Number of Slave Registers 12
signal slv_reg0 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg1 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg2 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg3 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg4 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg5 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg6 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg7 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg8 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg9 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg10 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg11 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg_rden : std_logic;
signal slv_reg_wren : std_logic;
signal reg_data_out :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal byte_index : integer;
begin
-- I/O Connections assignments
S_AXI_AWREADY <= axi_awready;
S_AXI_WREADY <= axi_wready;
S_AXI_BRESP <= axi_bresp;
S_AXI_BVALID <= axi_bvalid;
S_AXI_ARREADY <= axi_arready;
S_AXI_RDATA <= axi_rdata;
S_AXI_RRESP <= axi_rresp;
S_AXI_RVALID <= axi_rvalid;
-- Implement axi_awready generation
-- axi_awready is asserted for one S_AXI_ACLK clock cycle when both
-- S_AXI_AWVALID and S_AXI_WVALID are asserted. axi_awready is
-- de-asserted when reset is low.
process (S_AXI_ACLK)
begin
if rising_edge(S_AXI_ACLK) then
if S_AXI_ARESETN = '0' then
axi_awready <= '0';
else
if (axi_awready = '0' and S_AXI_AWVALID = '1' and S_AXI_WVALID = '1') then
-- slave is ready to accept write address when
-- there is a valid write address and write data
-- on the write address and data bus. This design
-- expects no outstanding transactions.
axi_awready <= '1';
else
axi_awready <= '0';
end if;
end if;
end if;
end process;
-- Implement axi_awaddr latching
-- This process is used to latch the address when both
-- S_AXI_AWVALID and S_AXI_WVALID are valid.
process (S_AXI_ACLK)
begin
if rising_edge(S_AXI_ACLK) then
if S_AXI_ARESETN = '0' then
axi_awaddr <= (others => '0');
else
if (axi_awready = '0' and S_AXI_AWVALID = '1' and S_AXI_WVALID = '1') then
-- Write Address latching
axi_awaddr <= S_AXI_AWADDR;
end if;
end if;
end if;
end process;
-- Implement axi_wready generation
-- axi_wready is asserted for one S_AXI_ACLK clock cycle when both
-- S_AXI_AWVALID and S_AXI_WVALID are asserted. axi_wready is
-- de-asserted when reset is low.
process (S_AXI_ACLK)
begin
if rising_edge(S_AXI_ACLK) then
if S_AXI_ARESETN = '0' then
axi_wready <= '0';
else
if (axi_wready = '0' and S_AXI_WVALID = '1' and S_AXI_AWVALID = '1') then
-- slave is ready to accept write data when
-- there is a valid write address and write data
-- on the write address and data bus. This design
-- expects no outstanding transactions.
axi_wready <= '1';
else
axi_wready <= '0';
end if;
end if;
end if;
end process;
-- Implement memory mapped register select and write logic generation
-- The write data is accepted and written to memory mapped registers when
-- axi_awready, S_AXI_WVALID, axi_wready and S_AXI_WVALID are asserted. Write strobes are used to
-- select byte enables of slave registers while writing.
-- These registers are cleared when reset (active low) is applied.
-- Slave register write enable is asserted when valid address and data are available
-- and the slave is ready to accept the write address and write data.
slv_reg_wren <= axi_wready and S_AXI_WVALID and axi_awready and S_AXI_AWVALID ;
process (S_AXI_ACLK)
variable loc_addr :std_logic_vector(OPT_MEM_ADDR_BITS downto 0);
begin
if rising_edge(S_AXI_ACLK) then
if S_AXI_ARESETN = '0' then
slv_reg0 <= (others => '0');
slv_reg1 <= (others => '0');
slv_reg2 <= (others => '0');
slv_reg3 <= (others => '0');
slv_reg4 <= (others => '0');
slv_reg5 <= (others => '0');
slv_reg6 <= (others => '0');
slv_reg7 <= (others => '0');
slv_reg8 <= (others => '0');
slv_reg9 <= (others => '0');
slv_reg10 <= (others => '0');
slv_reg11 <= (others => '0');
input_fifo_wr_en <= '0';
output_fifo_rd_en <= '0';
else
input_fifo_wr_en <= '0';
output_fifo_rd_en <= '0';
loc_addr := axi_awaddr(ADDR_LSB + OPT_MEM_ADDR_BITS downto ADDR_LSB);
if (slv_reg_wren = '1') then
case loc_addr is
when b"0000" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
input_fifo_wr_en <= '1';
-- Respective byte enables are asserted as per write strobes
-- slave registor 0
slv_reg0(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"0001" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 1
slv_reg1(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"0010" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 2
slv_reg2(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"0011" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 3
slv_reg3(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"0100" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
output_fifo_rd_en <= '1';
-- Respective byte enables are asserted as per write strobes
-- slave registor 4
slv_reg4(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"0101" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 5
slv_reg5(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"0110" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 6
slv_reg6(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"0111" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 7
slv_reg7(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"1000" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 8
slv_reg8(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"1001" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 9
slv_reg9(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"1010" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 10
slv_reg10(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"1011" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 11
slv_reg11(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when others =>
slv_reg0 <= slv_reg0;
slv_reg1 <= slv_reg1;
slv_reg2 <= slv_reg2;
slv_reg3 <= slv_reg3;
slv_reg4 <= slv_reg4;
slv_reg5 <= slv_reg5;
slv_reg6 <= slv_reg6;
slv_reg7 <= slv_reg7;
slv_reg8 <= slv_reg8;
slv_reg9 <= slv_reg9;
slv_reg10 <= slv_reg10;
slv_reg11 <= slv_reg11;
end case;
end if;
end if;
end if;
end process;
-- Implement write response logic generation
-- The write response and response valid signals are asserted by the slave
-- when axi_wready, S_AXI_WVALID, axi_wready and S_AXI_WVALID are asserted.
-- This marks the acceptance of address and indicates the status of
-- write transaction.
process (S_AXI_ACLK)
begin
if rising_edge(S_AXI_ACLK) then
if S_AXI_ARESETN = '0' then
axi_bvalid <= '0';
axi_bresp <= "00"; --need to work more on the responses
else
if (axi_awready = '1' and S_AXI_AWVALID = '1' and axi_wready = '1' and S_AXI_WVALID = '1' and axi_bvalid = '0' ) then
axi_bvalid <= '1';
axi_bresp <= "00";
elsif (S_AXI_BREADY = '1' and axi_bvalid = '1') then --check if bready is asserted while bvalid is high)
axi_bvalid <= '0'; -- (there is a possibility that bready is always asserted high)
end if;
end if;
end if;
end process;
-- Implement axi_arready generation
-- axi_arready is asserted for one S_AXI_ACLK clock cycle when
-- S_AXI_ARVALID is asserted. axi_awready is
-- de-asserted when reset (active low) is asserted.
-- The read address is also latched when S_AXI_ARVALID is
-- asserted. axi_araddr is reset to zero on reset assertion.
process (S_AXI_ACLK)
begin
if rising_edge(S_AXI_ACLK) then
if S_AXI_ARESETN = '0' then
axi_arready <= '0';
axi_araddr <= (others => '1');
else
if (axi_arready = '0' and S_AXI_ARVALID = '1') then
-- indicates that the slave has acceped the valid read address
axi_arready <= '1';
-- Read Address latching
axi_araddr <= S_AXI_ARADDR;
else
axi_arready <= '0';
end if;
end if;
end if;
end process;
-- Implement axi_arvalid generation
-- axi_rvalid is asserted for one S_AXI_ACLK clock cycle when both
-- S_AXI_ARVALID and axi_arready are asserted. The slave registers
-- data are available on the axi_rdata bus at this instance. The
-- assertion of axi_rvalid marks the validity of read data on the
-- bus and axi_rresp indicates the status of read transaction.axi_rvalid
-- is deasserted on reset (active low). axi_rresp and axi_rdata are
-- cleared to zero on reset (active low).
process (S_AXI_ACLK)
begin
if rising_edge(S_AXI_ACLK) then
if S_AXI_ARESETN = '0' then
axi_rvalid <= '0';
axi_rresp <= "00";
else
if (axi_arready = '1' and S_AXI_ARVALID = '1' and axi_rvalid = '0') then
-- Valid read data is available at the read data bus
axi_rvalid <= '1';
axi_rresp <= "00"; -- 'OKAY' response
elsif (axi_rvalid = '1' and S_AXI_RREADY = '1') then
-- Read data is accepted by the master
axi_rvalid <= '0';
end if;
end if;
end if;
end process;
-- Implement memory mapped register select and read logic generation
-- Slave register read enable is asserted when valid address is available
-- and the slave is ready to accept the read address.
slv_reg_rden <= axi_arready and S_AXI_ARVALID and (not axi_rvalid) ;
process (slv_reg0, slv_reg1, slv_reg2, slv_reg3, slv_reg4, slv_reg5, slv_reg6, slv_reg7, slv_reg8, slv_reg9, slv_reg10, slv_reg11, axi_araddr, S_AXI_ARESETN, slv_reg_rden)
variable loc_addr :std_logic_vector(OPT_MEM_ADDR_BITS downto 0);
begin
-- Address decoding for reading registers
loc_addr := axi_araddr(ADDR_LSB + OPT_MEM_ADDR_BITS downto ADDR_LSB);
case loc_addr is
when b"0000" =>
reg_data_out <= slv_reg0;
when b"0001" =>
reg_data_out <= slv_reg1;
when b"0010" =>
reg_data_out <= input_fifo_full;
when b"0011" =>
reg_data_out <= slv_reg3;
when b"0100" =>
reg_data_out <= slv_reg4;
when b"0101" =>
reg_data_out <= output_fifo_dout;
when b"0110" =>
reg_data_out <= output_fifo_full;
when b"0111" =>
reg_data_out <= output_fifo_empty;
when b"1000" =>
reg_data_out <= compression_done;
when b"1001" =>
reg_data_out <= input_fifo_wr_ack;
when b"1010" =>
reg_data_out <= output_fifo_valid;
when b"1011" =>
reg_data_out <= clock_count;
when others =>
reg_data_out <= (others => '0');
end case;
end process;
-- Output register or memory read data
process( S_AXI_ACLK ) is
begin
if (rising_edge (S_AXI_ACLK)) then
if ( S_AXI_ARESETN = '0' ) then
axi_rdata <= (others => '0');
else
if (slv_reg_rden = '1') then
-- When there is a valid read address (S_AXI_ARVALID) with
-- acceptance of read address by the slave (axi_arready),
-- output the read dada
-- Read address mux
axi_rdata <= reg_data_out; -- register read data
end if;
end if;
end if;
end process;
-- Add user logic here
lzw_rst <= NOT(S_AXI_ARESETN);
fifo0 : input_fifo
port map(
clk => S_AXI_ACLK,
srst => lzw_rst,
din => slv_reg1(7 downto 0),
wr_en => input_fifo_wr_en,
rd_en => input_fifo_rd_en,
dout => input_fifo_output,
full => input_fifo_full(0),
empty => input_fifo_empty,
wr_ack => input_fifo_wr_ack(0)
);
fifo1 : output_fifo
port map(
clk => S_AXI_ACLK,
srst => lzw_rst,
din => output_fifo_din,
wr_en => output_fifo_wr_en,
rd_en => output_fifo_rd_en,
dout => output_fifo_dout(11 downto 0),
full => output_fifo_full(0),
empty => output_fifo_empty(0),
valid => output_fifo_valid(0)
);
input_fifo_not_empty <= NOT(input_fifo_empty);
compression : entity work.lzw
generic map( num_blocks => 4)
port map(
clk => S_AXI_ACLK,
rst => lzw_rst,
char_in => input_fifo_output,
input_valid => input_fifo_not_empty,
file_size => slv_reg3(15 downto 0),
input_rd => input_fifo_rd_en,
prefix_out => output_fifo_din,
output_valid => output_fifo_wr_en,
done => compression_done(0)
);
clk_count : clock_counter
port map(
enable => input_fifo_not_empty,
count => clock_count,
done => compression_done(0),
clk => S_AXI_ACLK,
rst => lzw_rst
);
-- User logic ends
end arch_imp;
| unlicense | cf95ca60e59919da4a6ea673ebdc32a4 | 0.57267 | 3.508986 | false | false | false | false |
grwlf/vsim | vhdl_ct/ct00203.vhd | 1 | 4,965 | -- NEED RESULT: ENT00203: Wait statement longest static prefix check passed
-- NEED RESULT: ENT00203: Wait statement longest static prefix check passed
-- NEED RESULT: ENT00203: Wait statement longest static prefix check passed
-- NEED RESULT: ENT00203: Wait statement longest static prefix check passed
-- NEED RESULT: P1: Wait longest static prefix test completed passed
-------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
-------------------------------------------------------------------------------
--
-- TEST NAME:
--
-- CT00203
--
-- AUTHOR:
--
-- G. Tominovich
--
-- TEST OBJECTIVES:
--
-- 8.1 (5)
--
-- DESIGN UNIT ORDERING:
--
-- ENT00203(ARCH00203)
-- ENT00203_Test_Bench(ARCH00203_Test_Bench)
--
-- REVISION HISTORY:
--
-- 10-JUL-1987 - initial revision
--
-- NOTES:
--
-- self-checking
-- automatically generated
--
use WORK.STANDARD_TYPES.all ;
entity ENT00203 is
generic (G : integer) ;
--
constant CG : integer := G+1;
attribute attr : integer ;
attribute attr of CG : constant is CG+1;
--
end ENT00203 ;
--
--
architecture ARCH00203 of ENT00203 is
signal s_st_int1_vector : st_int1_vector
:= c_st_int1_vector_1 ;
--
subtype chk_sig_type is integer range -1 to 100 ;
signal chk_st_int1_vector : chk_sig_type := -1 ;
--
begin
P1 :
process
variable counter : integer := 0 ;
variable correct : boolean ;
variable savtime : time := 0 ns ;
begin
case counter is
when 0
=>
s_st_int1_vector(1) <= transport
c_st_int1_vector_2(1) ;
s_st_int1_vector(2) <= transport
c_st_int1_vector_2(2) after 10 ns ;
wait until s_st_int1_vector(2) =
c_st_int1_vector_2(2) ;
Test_Report (
"ENT00203",
"Wait statement longest static prefix check",
((savtime + 10 ns) = Std.Standard.Now) and
(s_st_int1_vector(2) =
c_st_int1_vector_2(2) )) ;
--
when 1
=>
s_st_int1_vector(1) <= transport
c_st_int1_vector_1(1) ;
s_st_int1_vector(G) <= transport
c_st_int1_vector_2(G) after 10 ns ;
wait until s_st_int1_vector(G) =
c_st_int1_vector_2(G) ;
Test_Report (
"ENT00203",
"Wait statement longest static prefix check",
((savtime + 10 ns) = Std.Standard.Now) and
(s_st_int1_vector(G) =
c_st_int1_vector_2(G) )) ;
--
when 2
=>
s_st_int1_vector(1) <= transport
c_st_int1_vector_2(1) ;
s_st_int1_vector(CG) <= transport
c_st_int1_vector_2(CG) after 10 ns ;
wait until s_st_int1_vector(CG) =
c_st_int1_vector_2(CG) ;
Test_Report (
"ENT00203",
"Wait statement longest static prefix check",
((savtime + 10 ns) = Std.Standard.Now) and
(s_st_int1_vector(CG) =
c_st_int1_vector_2(CG) )) ;
--
when 3
=>
s_st_int1_vector(1) <= transport
c_st_int1_vector_1(1) ;
s_st_int1_vector(CG'Attr) <= transport
c_st_int1_vector_2(CG'Attr) after 10 ns ;
wait until s_st_int1_vector(CG'Attr) =
c_st_int1_vector_2(CG'Attr) ;
Test_Report (
"ENT00203",
"Wait statement longest static prefix check",
((savtime + 10 ns) = Std.Standard.Now) and
(s_st_int1_vector(CG'Attr) =
c_st_int1_vector_2(CG'Attr) )) ;
--
when others
=> wait ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_st_int1_vector <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
end process P1 ;
--
PGEN_CHKP_1 :
process ( chk_st_int1_vector )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P1" ,
"Wait longest static prefix test completed",
chk_st_int1_vector = 3 ) ;
end if ;
end process PGEN_CHKP_1 ;
--
--
end ARCH00203 ;
--
--
use WORK.STANDARD_TYPES.all ;
entity ENT00203_Test_Bench is
end ENT00203_Test_Bench ;
--
--
architecture ARCH00203_Test_Bench of ENT00203_Test_Bench is
begin
L1:
block
component UUT
generic (G : integer) ;
end component ;
--
for CIS1 : UUT use entity WORK.ENT00203 ( ARCH00203 ) ;
begin
CIS1 : UUT
generic map (lowb+2)
;
end block L1 ;
end ARCH00203_Test_Bench ;
| gpl-3.0 | fca9a9fe7df54684e2cd157c241f5ea4 | 0.49567 | 3.489108 | false | true | false | false |
jairov4/accel-oil | solution_spartan3/syn/vhdl/nfa_accept_samples_generic_hw_mul_8ns_6ns_14_9.vhd | 2 | 3,326 | -- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2013.4
-- Copyright (C) 2013 Xilinx Inc. All rights reserved.
--
-- ==============================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity nfa_accept_samples_generic_hw_mul_8ns_6ns_14_9_MulnS_1 is
port (
clk: in std_logic;
ce: in std_logic;
a: in std_logic_vector(8 - 1 downto 0);
b: in std_logic_vector(6 - 1 downto 0);
p: out std_logic_vector(14 - 1 downto 0));
end entity;
architecture behav of nfa_accept_samples_generic_hw_mul_8ns_6ns_14_9_MulnS_1 is
signal tmp_product : std_logic_vector(14 - 1 downto 0);
signal a_i : std_logic_vector(8 - 1 downto 0);
signal b_i : std_logic_vector(6 - 1 downto 0);
signal p_tmp : std_logic_vector(14 - 1 downto 0);
signal a_reg : std_logic_vector(8 - 1 downto 0);
signal b_reg : std_logic_vector(6 - 1 downto 0);
attribute keep : string;
attribute keep of a_i : signal is "true";
attribute keep of b_i : signal is "true";
signal buff0 : std_logic_vector(14 - 1 downto 0);
signal buff1 : std_logic_vector(14 - 1 downto 0);
signal buff2 : std_logic_vector(14 - 1 downto 0);
signal buff3 : std_logic_vector(14 - 1 downto 0);
signal buff4 : std_logic_vector(14 - 1 downto 0);
signal buff5 : std_logic_vector(14 - 1 downto 0);
signal buff6 : std_logic_vector(14 - 1 downto 0);
begin
a_i <= a;
b_i <= b;
p <= p_tmp;
p_tmp <= buff6;
tmp_product <= std_logic_vector(resize(unsigned(a_reg) * unsigned(b_reg), 14));
process(clk)
begin
if (clk'event and clk = '1') then
if (ce = '1') then
a_reg <= a_i;
b_reg <= b_i;
buff0 <= tmp_product;
buff1 <= buff0;
buff2 <= buff1;
buff3 <= buff2;
buff4 <= buff3;
buff5 <= buff4;
buff6 <= buff5;
end if;
end if;
end process;
end architecture;
Library IEEE;
use IEEE.std_logic_1164.all;
entity nfa_accept_samples_generic_hw_mul_8ns_6ns_14_9 is
generic (
ID : INTEGER;
NUM_STAGE : INTEGER;
din0_WIDTH : INTEGER;
din1_WIDTH : INTEGER;
dout_WIDTH : INTEGER);
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
ce : IN STD_LOGIC;
din0 : IN STD_LOGIC_VECTOR(din0_WIDTH - 1 DOWNTO 0);
din1 : IN STD_LOGIC_VECTOR(din1_WIDTH - 1 DOWNTO 0);
dout : OUT STD_LOGIC_VECTOR(dout_WIDTH - 1 DOWNTO 0));
end entity;
architecture arch of nfa_accept_samples_generic_hw_mul_8ns_6ns_14_9 is
component nfa_accept_samples_generic_hw_mul_8ns_6ns_14_9_MulnS_1 is
port (
clk : IN STD_LOGIC;
ce : IN STD_LOGIC;
a : IN STD_LOGIC_VECTOR;
b : IN STD_LOGIC_VECTOR;
p : OUT STD_LOGIC_VECTOR);
end component;
begin
nfa_accept_samples_generic_hw_mul_8ns_6ns_14_9_MulnS_1_U : component nfa_accept_samples_generic_hw_mul_8ns_6ns_14_9_MulnS_1
port map (
clk => clk,
ce => ce,
a => din0,
b => din1,
p => dout);
end architecture;
| lgpl-3.0 | 44806378fc6933b41246395be346d017 | 0.55442 | 3.260784 | false | false | false | false |
grwlf/vsim | vhdl_ct/ct00088.vhd | 1 | 72,595 | -- NEED RESULT: ARCH00088.P1: Multi transport transactions occurred on signal asg with slice name on LHS failed
-- NEED RESULT: ARCH00088.P2: Multi transport transactions occurred on signal asg with slice name on LHS failed
-- NEED RESULT: ARCH00088.P3: Multi transport transactions occurred on signal asg with slice name on LHS failed
-- NEED RESULT: ARCH00088.P4: Multi transport transactions occurred on signal asg with slice name on LHS failed
-- NEED RESULT: ARCH00088.P5: Multi transport transactions occurred on signal asg with slice name on LHS failed
-- NEED RESULT: ARCH00088.P6: Multi transport transactions occurred on signal asg with slice name on LHS failed
-- NEED RESULT: ARCH00088.P7: Multi transport transactions occurred on signal asg with slice name on LHS failed
-- NEED RESULT: ARCH00088.P8: Multi transport transactions occurred on signal asg with slice name on LHS failed
-- NEED RESULT: ARCH00088.P9: Multi transport transactions occurred on signal asg with slice name on LHS failed
-- NEED RESULT: ARCH00088.P10: Multi transport transactions occurred on signal asg with slice name on LHS failed
-- NEED RESULT: ARCH00088.P11: Multi transport transactions occurred on signal asg with slice name on LHS failed
-- NEED RESULT: ARCH00088.P12: Multi transport transactions occurred on signal asg with slice name on LHS failed
-- NEED RESULT: ARCH00088.P13: Multi transport transactions occurred on signal asg with slice name on LHS failed
-- NEED RESULT: ARCH00088.P14: Multi transport transactions occurred on signal asg with slice name on LHS failed
-- NEED RESULT: ARCH00088.P15: Multi transport transactions occurred on signal asg with slice name on LHS failed
-- NEED RESULT: ARCH00088.P16: Multi transport transactions occurred on signal asg with slice name on LHS failed
-- NEED RESULT: ARCH00088.P17: Multi transport transactions occurred on signal asg with slice name on LHS failed
-- NEED RESULT: ARCH00088: One transport transaction occurred on signal asg with slice name on LHS failed
-- NEED RESULT: ARCH00088: Old transactions were removed on signal asg with slice name on LHS failed
-- NEED RESULT: ARCH00088: One transport transaction occurred on signal asg with slice name on LHS failed
-- NEED RESULT: ARCH00088: Old transactions were removed on signal asg with slice name on LHS failed
-- NEED RESULT: ARCH00088: One transport transaction occurred on signal asg with slice name on LHS failed
-- NEED RESULT: ARCH00088: Old transactions were removed on signal asg with slice name on LHS failed
-- NEED RESULT: ARCH00088: One transport transaction occurred on signal asg with slice name on LHS failed
-- NEED RESULT: ARCH00088: Old transactions were removed on signal asg with slice name on LHS failed
-- NEED RESULT: ARCH00088: One transport transaction occurred on signal asg with slice name on LHS failed
-- NEED RESULT: ARCH00088: Old transactions were removed on signal asg with slice name on LHS failed
-- NEED RESULT: ARCH00088: One transport transaction occurred on signal asg with slice name on LHS failed
-- NEED RESULT: ARCH00088: Old transactions were removed on signal asg with slice name on LHS failed
-- NEED RESULT: ARCH00088: One transport transaction occurred on signal asg with slice name on LHS failed
-- NEED RESULT: ARCH00088: Old transactions were removed on signal asg with slice name on LHS failed
-- NEED RESULT: ARCH00088: One transport transaction occurred on signal asg with slice name on LHS failed
-- NEED RESULT: ARCH00088: Old transactions were removed on signal asg with slice name on LHS failed
-- NEED RESULT: ARCH00088: One transport transaction occurred on signal asg with slice name on LHS failed
-- NEED RESULT: ARCH00088: Old transactions were removed on signal asg with slice name on LHS failed
-- NEED RESULT: ARCH00088: One transport transaction occurred on signal asg with slice name on LHS failed
-- NEED RESULT: ARCH00088: Old transactions were removed on signal asg with slice name on LHS failed
-- NEED RESULT: ARCH00088: One transport transaction occurred on signal asg with slice name on LHS failed
-- NEED RESULT: ARCH00088: Old transactions were removed on signal asg with slice name on LHS failed
-- NEED RESULT: ARCH00088: One transport transaction occurred on signal asg with slice name on LHS failed
-- NEED RESULT: ARCH00088: Old transactions were removed on signal asg with slice name on LHS failed
-- NEED RESULT: ARCH00088: One transport transaction occurred on signal asg with slice name on LHS failed
-- NEED RESULT: ARCH00088: Old transactions were removed on signal asg with slice name on LHS failed
-- NEED RESULT: ARCH00088: One transport transaction occurred on signal asg with slice name on LHS failed
-- NEED RESULT: ARCH00088: Old transactions were removed on signal asg with slice name on LHS failed
-- NEED RESULT: ARCH00088: One transport transaction occurred on signal asg with slice name on LHS failed
-- NEED RESULT: ARCH00088: Old transactions were removed on signal asg with slice name on LHS failed
-- NEED RESULT: ARCH00088: One transport transaction occurred on signal asg with slice name on LHS failed
-- NEED RESULT: ARCH00088: Old transactions were removed on signal asg with slice name on LHS failed
-- NEED RESULT: ARCH00088: One transport transaction occurred on signal asg with slice name on LHS failed
-- NEED RESULT: ARCH00088: Old transactions were removed on signal asg with slice name on LHS failed
-- NEED RESULT: P17: Transport transactions entirely completed passed
-- NEED RESULT: P16: Transport transactions entirely completed passed
-- NEED RESULT: P15: Transport transactions entirely completed passed
-- NEED RESULT: P14: Transport transactions entirely completed passed
-- NEED RESULT: P13: Transport transactions entirely completed passed
-- NEED RESULT: P12: Transport transactions entirely completed passed
-- NEED RESULT: P11: Transport transactions entirely completed passed
-- NEED RESULT: P10: Transport transactions entirely completed passed
-- NEED RESULT: P9: Transport transactions entirely completed passed
-- NEED RESULT: P8: Transport transactions entirely completed passed
-- NEED RESULT: P7: Transport transactions entirely completed passed
-- NEED RESULT: P6: Transport transactions entirely completed passed
-- NEED RESULT: P5: Transport transactions entirely completed passed
-- NEED RESULT: P4: Transport transactions entirely completed passed
-- NEED RESULT: P3: Transport transactions entirely completed passed
-- NEED RESULT: P2: Transport transactions entirely completed passed
-- NEED RESULT: P1: Transport transactions entirely completed passed
-------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
-------------------------------------------------------------------------------
--
-- TEST NAME:
--
-- CT00088
--
-- AUTHOR:
--
-- G. Tominovich
--
-- TEST OBJECTIVES:
--
-- 8.3 (2)
-- 8.3 (3)
-- 8.3 (5)
-- 8.3.1 (3)
--
-- DESIGN UNIT ORDERING:
--
-- ENT00088(ARCH00088)
-- ENT00088_Test_Bench(ARCH00088_Test_Bench)
--
-- REVISION HISTORY:
--
-- 07-JUL-1987 - initial revision
--
-- NOTES:
--
-- self-checking
-- automatically generated
--
use WORK.STANDARD_TYPES.all ;
entity ENT00088 is
port (
s_st_boolean_vector : inout st_boolean_vector
; s_st_bit_vector : inout st_bit_vector
; s_st_severity_level_vector : inout st_severity_level_vector
; s_st_string : inout st_string
; s_st_enum1_vector : inout st_enum1_vector
; s_st_integer_vector : inout st_integer_vector
; s_st_int1_vector : inout st_int1_vector
; s_st_time_vector : inout st_time_vector
; s_st_phys1_vector : inout st_phys1_vector
; s_st_real_vector : inout st_real_vector
; s_st_real1_vector : inout st_real1_vector
; s_st_rec1_vector : inout st_rec1_vector
; s_st_rec2_vector : inout st_rec2_vector
; s_st_rec3_vector : inout st_rec3_vector
; s_st_arr1_vector : inout st_arr1_vector
; s_st_arr2_vector : inout st_arr2_vector
; s_st_arr3_vector : inout st_arr3_vector
) ;
subtype chk_sig_type is integer range -1 to 100 ;
signal chk_st_boolean_vector : chk_sig_type := -1 ;
signal chk_st_bit_vector : chk_sig_type := -1 ;
signal chk_st_severity_level_vector : chk_sig_type := -1 ;
signal chk_st_string : chk_sig_type := -1 ;
signal chk_st_enum1_vector : chk_sig_type := -1 ;
signal chk_st_integer_vector : chk_sig_type := -1 ;
signal chk_st_int1_vector : chk_sig_type := -1 ;
signal chk_st_time_vector : chk_sig_type := -1 ;
signal chk_st_phys1_vector : chk_sig_type := -1 ;
signal chk_st_real_vector : chk_sig_type := -1 ;
signal chk_st_real1_vector : chk_sig_type := -1 ;
signal chk_st_rec1_vector : chk_sig_type := -1 ;
signal chk_st_rec2_vector : chk_sig_type := -1 ;
signal chk_st_rec3_vector : chk_sig_type := -1 ;
signal chk_st_arr1_vector : chk_sig_type := -1 ;
signal chk_st_arr2_vector : chk_sig_type := -1 ;
signal chk_st_arr3_vector : chk_sig_type := -1 ;
--
--
procedure Proc1 (
signal s_st_boolean_vector : inout st_boolean_vector ;
variable counter : inout integer ;
variable correct : inout boolean ;
variable savtime : inout time ;
signal chk_st_boolean_vector : out chk_sig_type
)
is
begin
case counter is
when 0
=> s_st_boolean_vector (lowb+1 to lowb+3) <= transport
c_st_boolean_vector_2 (lowb+1 to lowb+3) after 10 ns,
c_st_boolean_vector_1 (lowb+1 to lowb+3) after 20 ns ;
--
when 1
=> correct :=
s_st_boolean_vector (lowb+1 to lowb+3) =
c_st_boolean_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_boolean_vector (lowb+1 to lowb+3) =
c_st_boolean_vector_1 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00088.P1" ,
"Multi transport transactions occurred on signal " &
"asg with slice name on LHS",
correct ) ;
s_st_boolean_vector (lowb+1 to lowb+3) <= transport
c_st_boolean_vector_2 (lowb+1 to lowb+3) after 10 ns ,
c_st_boolean_vector_1 (lowb+1 to lowb+3) after 20 ns ,
c_st_boolean_vector_2 (lowb+1 to lowb+3) after 30 ns ,
c_st_boolean_vector_1 (lowb+1 to lowb+3) after 40 ns ;
--
when 3
=> correct :=
s_st_boolean_vector (lowb+1 to lowb+3) =
c_st_boolean_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
s_st_boolean_vector (lowb+1 to lowb+3) <= transport
c_st_boolean_vector_1 (lowb+1 to lowb+3) after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_boolean_vector (lowb+1 to lowb+3) =
c_st_boolean_vector_1 (lowb+1 to lowb+3) and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00088" ,
"One transport transaction occurred on signal " &
"asg with slice name on LHS",
correct ) ;
test_report ( "ARCH00088" ,
"Old transactions were removed on signal " &
"asg with slice name on LHS",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00088" ,
"Old transactions were removed on signal " &
"asg with slice name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_st_boolean_vector <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
end Proc1 ;
--
procedure Proc2 (
signal s_st_bit_vector : inout st_bit_vector ;
variable counter : inout integer ;
variable correct : inout boolean ;
variable savtime : inout time ;
signal chk_st_bit_vector : out chk_sig_type
)
is
begin
case counter is
when 0
=> s_st_bit_vector (lowb+1 to lowb+3) <= transport
c_st_bit_vector_2 (lowb+1 to lowb+3) after 10 ns,
c_st_bit_vector_1 (lowb+1 to lowb+3) after 20 ns ;
--
when 1
=> correct :=
s_st_bit_vector (lowb+1 to lowb+3) =
c_st_bit_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_bit_vector (lowb+1 to lowb+3) =
c_st_bit_vector_1 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00088.P2" ,
"Multi transport transactions occurred on signal " &
"asg with slice name on LHS",
correct ) ;
s_st_bit_vector (lowb+1 to lowb+3) <= transport
c_st_bit_vector_2 (lowb+1 to lowb+3) after 10 ns ,
c_st_bit_vector_1 (lowb+1 to lowb+3) after 20 ns ,
c_st_bit_vector_2 (lowb+1 to lowb+3) after 30 ns ,
c_st_bit_vector_1 (lowb+1 to lowb+3) after 40 ns ;
--
when 3
=> correct :=
s_st_bit_vector (lowb+1 to lowb+3) =
c_st_bit_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
s_st_bit_vector (lowb+1 to lowb+3) <= transport
c_st_bit_vector_1 (lowb+1 to lowb+3) after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_bit_vector (lowb+1 to lowb+3) =
c_st_bit_vector_1 (lowb+1 to lowb+3) and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00088" ,
"One transport transaction occurred on signal " &
"asg with slice name on LHS",
correct ) ;
test_report ( "ARCH00088" ,
"Old transactions were removed on signal " &
"asg with slice name on LHS",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00088" ,
"Old transactions were removed on signal " &
"asg with slice name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_st_bit_vector <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
end Proc2 ;
--
procedure Proc3 (
signal s_st_severity_level_vector : inout st_severity_level_vector ;
variable counter : inout integer ;
variable correct : inout boolean ;
variable savtime : inout time ;
signal chk_st_severity_level_vector : out chk_sig_type
)
is
begin
case counter is
when 0
=> s_st_severity_level_vector (lowb+1 to lowb+3) <= transport
c_st_severity_level_vector_2 (lowb+1 to lowb+3) after 10 ns,
c_st_severity_level_vector_1 (lowb+1 to lowb+3) after 20 ns ;
--
when 1
=> correct :=
s_st_severity_level_vector (lowb+1 to lowb+3) =
c_st_severity_level_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_severity_level_vector (lowb+1 to lowb+3) =
c_st_severity_level_vector_1 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00088.P3" ,
"Multi transport transactions occurred on signal " &
"asg with slice name on LHS",
correct ) ;
s_st_severity_level_vector (lowb+1 to lowb+3) <= transport
c_st_severity_level_vector_2 (lowb+1 to lowb+3) after 10 ns ,
c_st_severity_level_vector_1 (lowb+1 to lowb+3) after 20 ns ,
c_st_severity_level_vector_2 (lowb+1 to lowb+3) after 30 ns ,
c_st_severity_level_vector_1 (lowb+1 to lowb+3) after 40 ns ;
--
when 3
=> correct :=
s_st_severity_level_vector (lowb+1 to lowb+3) =
c_st_severity_level_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
s_st_severity_level_vector (lowb+1 to lowb+3) <= transport
c_st_severity_level_vector_1 (lowb+1 to lowb+3) after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_severity_level_vector (lowb+1 to lowb+3) =
c_st_severity_level_vector_1 (lowb+1 to lowb+3) and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00088" ,
"One transport transaction occurred on signal " &
"asg with slice name on LHS",
correct ) ;
test_report ( "ARCH00088" ,
"Old transactions were removed on signal " &
"asg with slice name on LHS",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00088" ,
"Old transactions were removed on signal " &
"asg with slice name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_st_severity_level_vector <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
end Proc3 ;
--
procedure Proc4 (
signal s_st_string : inout st_string ;
variable counter : inout integer ;
variable correct : inout boolean ;
variable savtime : inout time ;
signal chk_st_string : out chk_sig_type
)
is
begin
case counter is
when 0
=> s_st_string (lowb+1 to lowb+3) <= transport
c_st_string_2 (lowb+1 to lowb+3) after 10 ns,
c_st_string_1 (lowb+1 to lowb+3) after 20 ns ;
--
when 1
=> correct :=
s_st_string (lowb+1 to lowb+3) =
c_st_string_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_string (lowb+1 to lowb+3) =
c_st_string_1 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00088.P4" ,
"Multi transport transactions occurred on signal " &
"asg with slice name on LHS",
correct ) ;
s_st_string (lowb+1 to lowb+3) <= transport
c_st_string_2 (lowb+1 to lowb+3) after 10 ns ,
c_st_string_1 (lowb+1 to lowb+3) after 20 ns ,
c_st_string_2 (lowb+1 to lowb+3) after 30 ns ,
c_st_string_1 (lowb+1 to lowb+3) after 40 ns ;
--
when 3
=> correct :=
s_st_string (lowb+1 to lowb+3) =
c_st_string_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
s_st_string (lowb+1 to lowb+3) <= transport
c_st_string_1 (lowb+1 to lowb+3) after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_string (lowb+1 to lowb+3) =
c_st_string_1 (lowb+1 to lowb+3) and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00088" ,
"One transport transaction occurred on signal " &
"asg with slice name on LHS",
correct ) ;
test_report ( "ARCH00088" ,
"Old transactions were removed on signal " &
"asg with slice name on LHS",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00088" ,
"Old transactions were removed on signal " &
"asg with slice name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_st_string <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
end Proc4 ;
--
procedure Proc5 (
signal s_st_enum1_vector : inout st_enum1_vector ;
variable counter : inout integer ;
variable correct : inout boolean ;
variable savtime : inout time ;
signal chk_st_enum1_vector : out chk_sig_type
)
is
begin
case counter is
when 0
=> s_st_enum1_vector (lowb+1 to lowb+3) <= transport
c_st_enum1_vector_2 (lowb+1 to lowb+3) after 10 ns,
c_st_enum1_vector_1 (lowb+1 to lowb+3) after 20 ns ;
--
when 1
=> correct :=
s_st_enum1_vector (lowb+1 to lowb+3) =
c_st_enum1_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_enum1_vector (lowb+1 to lowb+3) =
c_st_enum1_vector_1 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00088.P5" ,
"Multi transport transactions occurred on signal " &
"asg with slice name on LHS",
correct ) ;
s_st_enum1_vector (lowb+1 to lowb+3) <= transport
c_st_enum1_vector_2 (lowb+1 to lowb+3) after 10 ns ,
c_st_enum1_vector_1 (lowb+1 to lowb+3) after 20 ns ,
c_st_enum1_vector_2 (lowb+1 to lowb+3) after 30 ns ,
c_st_enum1_vector_1 (lowb+1 to lowb+3) after 40 ns ;
--
when 3
=> correct :=
s_st_enum1_vector (lowb+1 to lowb+3) =
c_st_enum1_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
s_st_enum1_vector (lowb+1 to lowb+3) <= transport
c_st_enum1_vector_1 (lowb+1 to lowb+3) after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_enum1_vector (lowb+1 to lowb+3) =
c_st_enum1_vector_1 (lowb+1 to lowb+3) and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00088" ,
"One transport transaction occurred on signal " &
"asg with slice name on LHS",
correct ) ;
test_report ( "ARCH00088" ,
"Old transactions were removed on signal " &
"asg with slice name on LHS",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00088" ,
"Old transactions were removed on signal " &
"asg with slice name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_st_enum1_vector <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
end Proc5 ;
--
procedure Proc6 (
signal s_st_integer_vector : inout st_integer_vector ;
variable counter : inout integer ;
variable correct : inout boolean ;
variable savtime : inout time ;
signal chk_st_integer_vector : out chk_sig_type
)
is
begin
case counter is
when 0
=> s_st_integer_vector (lowb+1 to lowb+3) <= transport
c_st_integer_vector_2 (lowb+1 to lowb+3) after 10 ns,
c_st_integer_vector_1 (lowb+1 to lowb+3) after 20 ns ;
--
when 1
=> correct :=
s_st_integer_vector (lowb+1 to lowb+3) =
c_st_integer_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_integer_vector (lowb+1 to lowb+3) =
c_st_integer_vector_1 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00088.P6" ,
"Multi transport transactions occurred on signal " &
"asg with slice name on LHS",
correct ) ;
s_st_integer_vector (lowb+1 to lowb+3) <= transport
c_st_integer_vector_2 (lowb+1 to lowb+3) after 10 ns ,
c_st_integer_vector_1 (lowb+1 to lowb+3) after 20 ns ,
c_st_integer_vector_2 (lowb+1 to lowb+3) after 30 ns ,
c_st_integer_vector_1 (lowb+1 to lowb+3) after 40 ns ;
--
when 3
=> correct :=
s_st_integer_vector (lowb+1 to lowb+3) =
c_st_integer_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
s_st_integer_vector (lowb+1 to lowb+3) <= transport
c_st_integer_vector_1 (lowb+1 to lowb+3) after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_integer_vector (lowb+1 to lowb+3) =
c_st_integer_vector_1 (lowb+1 to lowb+3) and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00088" ,
"One transport transaction occurred on signal " &
"asg with slice name on LHS",
correct ) ;
test_report ( "ARCH00088" ,
"Old transactions were removed on signal " &
"asg with slice name on LHS",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00088" ,
"Old transactions were removed on signal " &
"asg with slice name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_st_integer_vector <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
end Proc6 ;
--
procedure Proc7 (
signal s_st_int1_vector : inout st_int1_vector ;
variable counter : inout integer ;
variable correct : inout boolean ;
variable savtime : inout time ;
signal chk_st_int1_vector : out chk_sig_type
)
is
begin
case counter is
when 0
=> s_st_int1_vector (lowb+1 to lowb+3) <= transport
c_st_int1_vector_2 (lowb+1 to lowb+3) after 10 ns,
c_st_int1_vector_1 (lowb+1 to lowb+3) after 20 ns ;
--
when 1
=> correct :=
s_st_int1_vector (lowb+1 to lowb+3) =
c_st_int1_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_int1_vector (lowb+1 to lowb+3) =
c_st_int1_vector_1 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00088.P7" ,
"Multi transport transactions occurred on signal " &
"asg with slice name on LHS",
correct ) ;
s_st_int1_vector (lowb+1 to lowb+3) <= transport
c_st_int1_vector_2 (lowb+1 to lowb+3) after 10 ns ,
c_st_int1_vector_1 (lowb+1 to lowb+3) after 20 ns ,
c_st_int1_vector_2 (lowb+1 to lowb+3) after 30 ns ,
c_st_int1_vector_1 (lowb+1 to lowb+3) after 40 ns ;
--
when 3
=> correct :=
s_st_int1_vector (lowb+1 to lowb+3) =
c_st_int1_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
s_st_int1_vector (lowb+1 to lowb+3) <= transport
c_st_int1_vector_1 (lowb+1 to lowb+3) after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_int1_vector (lowb+1 to lowb+3) =
c_st_int1_vector_1 (lowb+1 to lowb+3) and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00088" ,
"One transport transaction occurred on signal " &
"asg with slice name on LHS",
correct ) ;
test_report ( "ARCH00088" ,
"Old transactions were removed on signal " &
"asg with slice name on LHS",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00088" ,
"Old transactions were removed on signal " &
"asg with slice name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_st_int1_vector <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
end Proc7 ;
--
procedure Proc8 (
signal s_st_time_vector : inout st_time_vector ;
variable counter : inout integer ;
variable correct : inout boolean ;
variable savtime : inout time ;
signal chk_st_time_vector : out chk_sig_type
)
is
begin
case counter is
when 0
=> s_st_time_vector (lowb+1 to lowb+3) <= transport
c_st_time_vector_2 (lowb+1 to lowb+3) after 10 ns,
c_st_time_vector_1 (lowb+1 to lowb+3) after 20 ns ;
--
when 1
=> correct :=
s_st_time_vector (lowb+1 to lowb+3) =
c_st_time_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_time_vector (lowb+1 to lowb+3) =
c_st_time_vector_1 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00088.P8" ,
"Multi transport transactions occurred on signal " &
"asg with slice name on LHS",
correct ) ;
s_st_time_vector (lowb+1 to lowb+3) <= transport
c_st_time_vector_2 (lowb+1 to lowb+3) after 10 ns ,
c_st_time_vector_1 (lowb+1 to lowb+3) after 20 ns ,
c_st_time_vector_2 (lowb+1 to lowb+3) after 30 ns ,
c_st_time_vector_1 (lowb+1 to lowb+3) after 40 ns ;
--
when 3
=> correct :=
s_st_time_vector (lowb+1 to lowb+3) =
c_st_time_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
s_st_time_vector (lowb+1 to lowb+3) <= transport
c_st_time_vector_1 (lowb+1 to lowb+3) after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_time_vector (lowb+1 to lowb+3) =
c_st_time_vector_1 (lowb+1 to lowb+3) and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00088" ,
"One transport transaction occurred on signal " &
"asg with slice name on LHS",
correct ) ;
test_report ( "ARCH00088" ,
"Old transactions were removed on signal " &
"asg with slice name on LHS",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00088" ,
"Old transactions were removed on signal " &
"asg with slice name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_st_time_vector <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
end Proc8 ;
--
procedure Proc9 (
signal s_st_phys1_vector : inout st_phys1_vector ;
variable counter : inout integer ;
variable correct : inout boolean ;
variable savtime : inout time ;
signal chk_st_phys1_vector : out chk_sig_type
)
is
begin
case counter is
when 0
=> s_st_phys1_vector (lowb+1 to lowb+3) <= transport
c_st_phys1_vector_2 (lowb+1 to lowb+3) after 10 ns,
c_st_phys1_vector_1 (lowb+1 to lowb+3) after 20 ns ;
--
when 1
=> correct :=
s_st_phys1_vector (lowb+1 to lowb+3) =
c_st_phys1_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_phys1_vector (lowb+1 to lowb+3) =
c_st_phys1_vector_1 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00088.P9" ,
"Multi transport transactions occurred on signal " &
"asg with slice name on LHS",
correct ) ;
s_st_phys1_vector (lowb+1 to lowb+3) <= transport
c_st_phys1_vector_2 (lowb+1 to lowb+3) after 10 ns ,
c_st_phys1_vector_1 (lowb+1 to lowb+3) after 20 ns ,
c_st_phys1_vector_2 (lowb+1 to lowb+3) after 30 ns ,
c_st_phys1_vector_1 (lowb+1 to lowb+3) after 40 ns ;
--
when 3
=> correct :=
s_st_phys1_vector (lowb+1 to lowb+3) =
c_st_phys1_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
s_st_phys1_vector (lowb+1 to lowb+3) <= transport
c_st_phys1_vector_1 (lowb+1 to lowb+3) after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_phys1_vector (lowb+1 to lowb+3) =
c_st_phys1_vector_1 (lowb+1 to lowb+3) and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00088" ,
"One transport transaction occurred on signal " &
"asg with slice name on LHS",
correct ) ;
test_report ( "ARCH00088" ,
"Old transactions were removed on signal " &
"asg with slice name on LHS",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00088" ,
"Old transactions were removed on signal " &
"asg with slice name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_st_phys1_vector <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
end Proc9 ;
--
procedure Proc10 (
signal s_st_real_vector : inout st_real_vector ;
variable counter : inout integer ;
variable correct : inout boolean ;
variable savtime : inout time ;
signal chk_st_real_vector : out chk_sig_type
)
is
begin
case counter is
when 0
=> s_st_real_vector (lowb+1 to lowb+3) <= transport
c_st_real_vector_2 (lowb+1 to lowb+3) after 10 ns,
c_st_real_vector_1 (lowb+1 to lowb+3) after 20 ns ;
--
when 1
=> correct :=
s_st_real_vector (lowb+1 to lowb+3) =
c_st_real_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_real_vector (lowb+1 to lowb+3) =
c_st_real_vector_1 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00088.P10" ,
"Multi transport transactions occurred on signal " &
"asg with slice name on LHS",
correct ) ;
s_st_real_vector (lowb+1 to lowb+3) <= transport
c_st_real_vector_2 (lowb+1 to lowb+3) after 10 ns ,
c_st_real_vector_1 (lowb+1 to lowb+3) after 20 ns ,
c_st_real_vector_2 (lowb+1 to lowb+3) after 30 ns ,
c_st_real_vector_1 (lowb+1 to lowb+3) after 40 ns ;
--
when 3
=> correct :=
s_st_real_vector (lowb+1 to lowb+3) =
c_st_real_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
s_st_real_vector (lowb+1 to lowb+3) <= transport
c_st_real_vector_1 (lowb+1 to lowb+3) after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_real_vector (lowb+1 to lowb+3) =
c_st_real_vector_1 (lowb+1 to lowb+3) and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00088" ,
"One transport transaction occurred on signal " &
"asg with slice name on LHS",
correct ) ;
test_report ( "ARCH00088" ,
"Old transactions were removed on signal " &
"asg with slice name on LHS",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00088" ,
"Old transactions were removed on signal " &
"asg with slice name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_st_real_vector <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
end Proc10 ;
--
procedure Proc11 (
signal s_st_real1_vector : inout st_real1_vector ;
variable counter : inout integer ;
variable correct : inout boolean ;
variable savtime : inout time ;
signal chk_st_real1_vector : out chk_sig_type
)
is
begin
case counter is
when 0
=> s_st_real1_vector (lowb+1 to lowb+3) <= transport
c_st_real1_vector_2 (lowb+1 to lowb+3) after 10 ns,
c_st_real1_vector_1 (lowb+1 to lowb+3) after 20 ns ;
--
when 1
=> correct :=
s_st_real1_vector (lowb+1 to lowb+3) =
c_st_real1_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_real1_vector (lowb+1 to lowb+3) =
c_st_real1_vector_1 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00088.P11" ,
"Multi transport transactions occurred on signal " &
"asg with slice name on LHS",
correct ) ;
s_st_real1_vector (lowb+1 to lowb+3) <= transport
c_st_real1_vector_2 (lowb+1 to lowb+3) after 10 ns ,
c_st_real1_vector_1 (lowb+1 to lowb+3) after 20 ns ,
c_st_real1_vector_2 (lowb+1 to lowb+3) after 30 ns ,
c_st_real1_vector_1 (lowb+1 to lowb+3) after 40 ns ;
--
when 3
=> correct :=
s_st_real1_vector (lowb+1 to lowb+3) =
c_st_real1_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
s_st_real1_vector (lowb+1 to lowb+3) <= transport
c_st_real1_vector_1 (lowb+1 to lowb+3) after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_real1_vector (lowb+1 to lowb+3) =
c_st_real1_vector_1 (lowb+1 to lowb+3) and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00088" ,
"One transport transaction occurred on signal " &
"asg with slice name on LHS",
correct ) ;
test_report ( "ARCH00088" ,
"Old transactions were removed on signal " &
"asg with slice name on LHS",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00088" ,
"Old transactions were removed on signal " &
"asg with slice name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_st_real1_vector <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
end Proc11 ;
--
procedure Proc12 (
signal s_st_rec1_vector : inout st_rec1_vector ;
variable counter : inout integer ;
variable correct : inout boolean ;
variable savtime : inout time ;
signal chk_st_rec1_vector : out chk_sig_type
)
is
begin
case counter is
when 0
=> s_st_rec1_vector (lowb+1 to lowb+3) <= transport
c_st_rec1_vector_2 (lowb+1 to lowb+3) after 10 ns,
c_st_rec1_vector_1 (lowb+1 to lowb+3) after 20 ns ;
--
when 1
=> correct :=
s_st_rec1_vector (lowb+1 to lowb+3) =
c_st_rec1_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_rec1_vector (lowb+1 to lowb+3) =
c_st_rec1_vector_1 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00088.P12" ,
"Multi transport transactions occurred on signal " &
"asg with slice name on LHS",
correct ) ;
s_st_rec1_vector (lowb+1 to lowb+3) <= transport
c_st_rec1_vector_2 (lowb+1 to lowb+3) after 10 ns ,
c_st_rec1_vector_1 (lowb+1 to lowb+3) after 20 ns ,
c_st_rec1_vector_2 (lowb+1 to lowb+3) after 30 ns ,
c_st_rec1_vector_1 (lowb+1 to lowb+3) after 40 ns ;
--
when 3
=> correct :=
s_st_rec1_vector (lowb+1 to lowb+3) =
c_st_rec1_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
s_st_rec1_vector (lowb+1 to lowb+3) <= transport
c_st_rec1_vector_1 (lowb+1 to lowb+3) after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_rec1_vector (lowb+1 to lowb+3) =
c_st_rec1_vector_1 (lowb+1 to lowb+3) and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00088" ,
"One transport transaction occurred on signal " &
"asg with slice name on LHS",
correct ) ;
test_report ( "ARCH00088" ,
"Old transactions were removed on signal " &
"asg with slice name on LHS",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00088" ,
"Old transactions were removed on signal " &
"asg with slice name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_st_rec1_vector <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
end Proc12 ;
--
procedure Proc13 (
signal s_st_rec2_vector : inout st_rec2_vector ;
variable counter : inout integer ;
variable correct : inout boolean ;
variable savtime : inout time ;
signal chk_st_rec2_vector : out chk_sig_type
)
is
begin
case counter is
when 0
=> s_st_rec2_vector (lowb+1 to lowb+3) <= transport
c_st_rec2_vector_2 (lowb+1 to lowb+3) after 10 ns,
c_st_rec2_vector_1 (lowb+1 to lowb+3) after 20 ns ;
--
when 1
=> correct :=
s_st_rec2_vector (lowb+1 to lowb+3) =
c_st_rec2_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_rec2_vector (lowb+1 to lowb+3) =
c_st_rec2_vector_1 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00088.P13" ,
"Multi transport transactions occurred on signal " &
"asg with slice name on LHS",
correct ) ;
s_st_rec2_vector (lowb+1 to lowb+3) <= transport
c_st_rec2_vector_2 (lowb+1 to lowb+3) after 10 ns ,
c_st_rec2_vector_1 (lowb+1 to lowb+3) after 20 ns ,
c_st_rec2_vector_2 (lowb+1 to lowb+3) after 30 ns ,
c_st_rec2_vector_1 (lowb+1 to lowb+3) after 40 ns ;
--
when 3
=> correct :=
s_st_rec2_vector (lowb+1 to lowb+3) =
c_st_rec2_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
s_st_rec2_vector (lowb+1 to lowb+3) <= transport
c_st_rec2_vector_1 (lowb+1 to lowb+3) after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_rec2_vector (lowb+1 to lowb+3) =
c_st_rec2_vector_1 (lowb+1 to lowb+3) and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00088" ,
"One transport transaction occurred on signal " &
"asg with slice name on LHS",
correct ) ;
test_report ( "ARCH00088" ,
"Old transactions were removed on signal " &
"asg with slice name on LHS",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00088" ,
"Old transactions were removed on signal " &
"asg with slice name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_st_rec2_vector <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
end Proc13 ;
--
procedure Proc14 (
signal s_st_rec3_vector : inout st_rec3_vector ;
variable counter : inout integer ;
variable correct : inout boolean ;
variable savtime : inout time ;
signal chk_st_rec3_vector : out chk_sig_type
)
is
begin
case counter is
when 0
=> s_st_rec3_vector (lowb+1 to lowb+3) <= transport
c_st_rec3_vector_2 (lowb+1 to lowb+3) after 10 ns,
c_st_rec3_vector_1 (lowb+1 to lowb+3) after 20 ns ;
--
when 1
=> correct :=
s_st_rec3_vector (lowb+1 to lowb+3) =
c_st_rec3_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_rec3_vector (lowb+1 to lowb+3) =
c_st_rec3_vector_1 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00088.P14" ,
"Multi transport transactions occurred on signal " &
"asg with slice name on LHS",
correct ) ;
s_st_rec3_vector (lowb+1 to lowb+3) <= transport
c_st_rec3_vector_2 (lowb+1 to lowb+3) after 10 ns ,
c_st_rec3_vector_1 (lowb+1 to lowb+3) after 20 ns ,
c_st_rec3_vector_2 (lowb+1 to lowb+3) after 30 ns ,
c_st_rec3_vector_1 (lowb+1 to lowb+3) after 40 ns ;
--
when 3
=> correct :=
s_st_rec3_vector (lowb+1 to lowb+3) =
c_st_rec3_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
s_st_rec3_vector (lowb+1 to lowb+3) <= transport
c_st_rec3_vector_1 (lowb+1 to lowb+3) after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_rec3_vector (lowb+1 to lowb+3) =
c_st_rec3_vector_1 (lowb+1 to lowb+3) and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00088" ,
"One transport transaction occurred on signal " &
"asg with slice name on LHS",
correct ) ;
test_report ( "ARCH00088" ,
"Old transactions were removed on signal " &
"asg with slice name on LHS",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00088" ,
"Old transactions were removed on signal " &
"asg with slice name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_st_rec3_vector <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
end Proc14 ;
--
procedure Proc15 (
signal s_st_arr1_vector : inout st_arr1_vector ;
variable counter : inout integer ;
variable correct : inout boolean ;
variable savtime : inout time ;
signal chk_st_arr1_vector : out chk_sig_type
)
is
begin
case counter is
when 0
=> s_st_arr1_vector (lowb+1 to lowb+3) <= transport
c_st_arr1_vector_2 (lowb+1 to lowb+3) after 10 ns,
c_st_arr1_vector_1 (lowb+1 to lowb+3) after 20 ns ;
--
when 1
=> correct :=
s_st_arr1_vector (lowb+1 to lowb+3) =
c_st_arr1_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_arr1_vector (lowb+1 to lowb+3) =
c_st_arr1_vector_1 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00088.P15" ,
"Multi transport transactions occurred on signal " &
"asg with slice name on LHS",
correct ) ;
s_st_arr1_vector (lowb+1 to lowb+3) <= transport
c_st_arr1_vector_2 (lowb+1 to lowb+3) after 10 ns ,
c_st_arr1_vector_1 (lowb+1 to lowb+3) after 20 ns ,
c_st_arr1_vector_2 (lowb+1 to lowb+3) after 30 ns ,
c_st_arr1_vector_1 (lowb+1 to lowb+3) after 40 ns ;
--
when 3
=> correct :=
s_st_arr1_vector (lowb+1 to lowb+3) =
c_st_arr1_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
s_st_arr1_vector (lowb+1 to lowb+3) <= transport
c_st_arr1_vector_1 (lowb+1 to lowb+3) after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_arr1_vector (lowb+1 to lowb+3) =
c_st_arr1_vector_1 (lowb+1 to lowb+3) and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00088" ,
"One transport transaction occurred on signal " &
"asg with slice name on LHS",
correct ) ;
test_report ( "ARCH00088" ,
"Old transactions were removed on signal " &
"asg with slice name on LHS",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00088" ,
"Old transactions were removed on signal " &
"asg with slice name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_st_arr1_vector <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
end Proc15 ;
--
procedure Proc16 (
signal s_st_arr2_vector : inout st_arr2_vector ;
variable counter : inout integer ;
variable correct : inout boolean ;
variable savtime : inout time ;
signal chk_st_arr2_vector : out chk_sig_type
)
is
begin
case counter is
when 0
=> s_st_arr2_vector (lowb+1 to lowb+3) <= transport
c_st_arr2_vector_2 (lowb+1 to lowb+3) after 10 ns,
c_st_arr2_vector_1 (lowb+1 to lowb+3) after 20 ns ;
--
when 1
=> correct :=
s_st_arr2_vector (lowb+1 to lowb+3) =
c_st_arr2_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_arr2_vector (lowb+1 to lowb+3) =
c_st_arr2_vector_1 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00088.P16" ,
"Multi transport transactions occurred on signal " &
"asg with slice name on LHS",
correct ) ;
s_st_arr2_vector (lowb+1 to lowb+3) <= transport
c_st_arr2_vector_2 (lowb+1 to lowb+3) after 10 ns ,
c_st_arr2_vector_1 (lowb+1 to lowb+3) after 20 ns ,
c_st_arr2_vector_2 (lowb+1 to lowb+3) after 30 ns ,
c_st_arr2_vector_1 (lowb+1 to lowb+3) after 40 ns ;
--
when 3
=> correct :=
s_st_arr2_vector (lowb+1 to lowb+3) =
c_st_arr2_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
s_st_arr2_vector (lowb+1 to lowb+3) <= transport
c_st_arr2_vector_1 (lowb+1 to lowb+3) after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_arr2_vector (lowb+1 to lowb+3) =
c_st_arr2_vector_1 (lowb+1 to lowb+3) and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00088" ,
"One transport transaction occurred on signal " &
"asg with slice name on LHS",
correct ) ;
test_report ( "ARCH00088" ,
"Old transactions were removed on signal " &
"asg with slice name on LHS",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00088" ,
"Old transactions were removed on signal " &
"asg with slice name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_st_arr2_vector <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
end Proc16 ;
--
procedure Proc17 (
signal s_st_arr3_vector : inout st_arr3_vector ;
variable counter : inout integer ;
variable correct : inout boolean ;
variable savtime : inout time ;
signal chk_st_arr3_vector : out chk_sig_type
)
is
begin
case counter is
when 0
=> s_st_arr3_vector (lowb+1 to lowb+3) <= transport
c_st_arr3_vector_2 (lowb+1 to lowb+3) after 10 ns,
c_st_arr3_vector_1 (lowb+1 to lowb+3) after 20 ns ;
--
when 1
=> correct :=
s_st_arr3_vector (lowb+1 to lowb+3) =
c_st_arr3_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_arr3_vector (lowb+1 to lowb+3) =
c_st_arr3_vector_1 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00088.P17" ,
"Multi transport transactions occurred on signal " &
"asg with slice name on LHS",
correct ) ;
s_st_arr3_vector (lowb+1 to lowb+3) <= transport
c_st_arr3_vector_2 (lowb+1 to lowb+3) after 10 ns ,
c_st_arr3_vector_1 (lowb+1 to lowb+3) after 20 ns ,
c_st_arr3_vector_2 (lowb+1 to lowb+3) after 30 ns ,
c_st_arr3_vector_1 (lowb+1 to lowb+3) after 40 ns ;
--
when 3
=> correct :=
s_st_arr3_vector (lowb+1 to lowb+3) =
c_st_arr3_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
s_st_arr3_vector (lowb+1 to lowb+3) <= transport
c_st_arr3_vector_1 (lowb+1 to lowb+3) after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_arr3_vector (lowb+1 to lowb+3) =
c_st_arr3_vector_1 (lowb+1 to lowb+3) and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00088" ,
"One transport transaction occurred on signal " &
"asg with slice name on LHS",
correct ) ;
test_report ( "ARCH00088" ,
"Old transactions were removed on signal " &
"asg with slice name on LHS",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00088" ,
"Old transactions were removed on signal " &
"asg with slice name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_st_arr3_vector <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
end Proc17 ;
--
--
end ENT00088 ;
--
architecture ARCH00088 of ENT00088 is
begin
PGEN_CHKP_1 :
process ( chk_st_boolean_vector )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P1" ,
"Transport transactions entirely completed",
chk_st_boolean_vector = 4 ) ;
end if ;
end process PGEN_CHKP_1 ;
--
P1 :
process ( s_st_boolean_vector )
variable counter : integer := 0 ;
variable correct : boolean ;
variable savtime : time ;
begin
Proc1 (
s_st_boolean_vector,
counter,
correct,
savtime,
chk_st_boolean_vector
) ;
end process P1 ;
--
PGEN_CHKP_2 :
process ( chk_st_bit_vector )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P2" ,
"Transport transactions entirely completed",
chk_st_bit_vector = 4 ) ;
end if ;
end process PGEN_CHKP_2 ;
--
P2 :
process ( s_st_bit_vector )
variable counter : integer := 0 ;
variable correct : boolean ;
variable savtime : time ;
begin
Proc2 (
s_st_bit_vector,
counter,
correct,
savtime,
chk_st_bit_vector
) ;
end process P2 ;
--
PGEN_CHKP_3 :
process ( chk_st_severity_level_vector )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P3" ,
"Transport transactions entirely completed",
chk_st_severity_level_vector = 4 ) ;
end if ;
end process PGEN_CHKP_3 ;
--
P3 :
process ( s_st_severity_level_vector )
variable counter : integer := 0 ;
variable correct : boolean ;
variable savtime : time ;
begin
Proc3 (
s_st_severity_level_vector,
counter,
correct,
savtime,
chk_st_severity_level_vector
) ;
end process P3 ;
--
PGEN_CHKP_4 :
process ( chk_st_string )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P4" ,
"Transport transactions entirely completed",
chk_st_string = 4 ) ;
end if ;
end process PGEN_CHKP_4 ;
--
P4 :
process ( s_st_string )
variable counter : integer := 0 ;
variable correct : boolean ;
variable savtime : time ;
begin
Proc4 (
s_st_string,
counter,
correct,
savtime,
chk_st_string
) ;
end process P4 ;
--
PGEN_CHKP_5 :
process ( chk_st_enum1_vector )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P5" ,
"Transport transactions entirely completed",
chk_st_enum1_vector = 4 ) ;
end if ;
end process PGEN_CHKP_5 ;
--
P5 :
process ( s_st_enum1_vector )
variable counter : integer := 0 ;
variable correct : boolean ;
variable savtime : time ;
begin
Proc5 (
s_st_enum1_vector,
counter,
correct,
savtime,
chk_st_enum1_vector
) ;
end process P5 ;
--
PGEN_CHKP_6 :
process ( chk_st_integer_vector )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P6" ,
"Transport transactions entirely completed",
chk_st_integer_vector = 4 ) ;
end if ;
end process PGEN_CHKP_6 ;
--
P6 :
process ( s_st_integer_vector )
variable counter : integer := 0 ;
variable correct : boolean ;
variable savtime : time ;
begin
Proc6 (
s_st_integer_vector,
counter,
correct,
savtime,
chk_st_integer_vector
) ;
end process P6 ;
--
PGEN_CHKP_7 :
process ( chk_st_int1_vector )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P7" ,
"Transport transactions entirely completed",
chk_st_int1_vector = 4 ) ;
end if ;
end process PGEN_CHKP_7 ;
--
P7 :
process ( s_st_int1_vector )
variable counter : integer := 0 ;
variable correct : boolean ;
variable savtime : time ;
begin
Proc7 (
s_st_int1_vector,
counter,
correct,
savtime,
chk_st_int1_vector
) ;
end process P7 ;
--
PGEN_CHKP_8 :
process ( chk_st_time_vector )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P8" ,
"Transport transactions entirely completed",
chk_st_time_vector = 4 ) ;
end if ;
end process PGEN_CHKP_8 ;
--
P8 :
process ( s_st_time_vector )
variable counter : integer := 0 ;
variable correct : boolean ;
variable savtime : time ;
begin
Proc8 (
s_st_time_vector,
counter,
correct,
savtime,
chk_st_time_vector
) ;
end process P8 ;
--
PGEN_CHKP_9 :
process ( chk_st_phys1_vector )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P9" ,
"Transport transactions entirely completed",
chk_st_phys1_vector = 4 ) ;
end if ;
end process PGEN_CHKP_9 ;
--
P9 :
process ( s_st_phys1_vector )
variable counter : integer := 0 ;
variable correct : boolean ;
variable savtime : time ;
begin
Proc9 (
s_st_phys1_vector,
counter,
correct,
savtime,
chk_st_phys1_vector
) ;
end process P9 ;
--
PGEN_CHKP_10 :
process ( chk_st_real_vector )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P10" ,
"Transport transactions entirely completed",
chk_st_real_vector = 4 ) ;
end if ;
end process PGEN_CHKP_10 ;
--
P10 :
process ( s_st_real_vector )
variable counter : integer := 0 ;
variable correct : boolean ;
variable savtime : time ;
begin
Proc10 (
s_st_real_vector,
counter,
correct,
savtime,
chk_st_real_vector
) ;
end process P10 ;
--
PGEN_CHKP_11 :
process ( chk_st_real1_vector )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P11" ,
"Transport transactions entirely completed",
chk_st_real1_vector = 4 ) ;
end if ;
end process PGEN_CHKP_11 ;
--
P11 :
process ( s_st_real1_vector )
variable counter : integer := 0 ;
variable correct : boolean ;
variable savtime : time ;
begin
Proc11 (
s_st_real1_vector,
counter,
correct,
savtime,
chk_st_real1_vector
) ;
end process P11 ;
--
PGEN_CHKP_12 :
process ( chk_st_rec1_vector )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P12" ,
"Transport transactions entirely completed",
chk_st_rec1_vector = 4 ) ;
end if ;
end process PGEN_CHKP_12 ;
--
P12 :
process ( s_st_rec1_vector )
variable counter : integer := 0 ;
variable correct : boolean ;
variable savtime : time ;
begin
Proc12 (
s_st_rec1_vector,
counter,
correct,
savtime,
chk_st_rec1_vector
) ;
end process P12 ;
--
PGEN_CHKP_13 :
process ( chk_st_rec2_vector )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P13" ,
"Transport transactions entirely completed",
chk_st_rec2_vector = 4 ) ;
end if ;
end process PGEN_CHKP_13 ;
--
P13 :
process ( s_st_rec2_vector )
variable counter : integer := 0 ;
variable correct : boolean ;
variable savtime : time ;
begin
Proc13 (
s_st_rec2_vector,
counter,
correct,
savtime,
chk_st_rec2_vector
) ;
end process P13 ;
--
PGEN_CHKP_14 :
process ( chk_st_rec3_vector )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P14" ,
"Transport transactions entirely completed",
chk_st_rec3_vector = 4 ) ;
end if ;
end process PGEN_CHKP_14 ;
--
P14 :
process ( s_st_rec3_vector )
variable counter : integer := 0 ;
variable correct : boolean ;
variable savtime : time ;
begin
Proc14 (
s_st_rec3_vector,
counter,
correct,
savtime,
chk_st_rec3_vector
) ;
end process P14 ;
--
PGEN_CHKP_15 :
process ( chk_st_arr1_vector )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P15" ,
"Transport transactions entirely completed",
chk_st_arr1_vector = 4 ) ;
end if ;
end process PGEN_CHKP_15 ;
--
P15 :
process ( s_st_arr1_vector )
variable counter : integer := 0 ;
variable correct : boolean ;
variable savtime : time ;
begin
Proc15 (
s_st_arr1_vector,
counter,
correct,
savtime,
chk_st_arr1_vector
) ;
end process P15 ;
--
PGEN_CHKP_16 :
process ( chk_st_arr2_vector )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P16" ,
"Transport transactions entirely completed",
chk_st_arr2_vector = 4 ) ;
end if ;
end process PGEN_CHKP_16 ;
--
P16 :
process ( s_st_arr2_vector )
variable counter : integer := 0 ;
variable correct : boolean ;
variable savtime : time ;
begin
Proc16 (
s_st_arr2_vector,
counter,
correct,
savtime,
chk_st_arr2_vector
) ;
end process P16 ;
--
PGEN_CHKP_17 :
process ( chk_st_arr3_vector )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P17" ,
"Transport transactions entirely completed",
chk_st_arr3_vector = 4 ) ;
end if ;
end process PGEN_CHKP_17 ;
--
P17 :
process ( s_st_arr3_vector )
variable counter : integer := 0 ;
variable correct : boolean ;
variable savtime : time ;
begin
Proc17 (
s_st_arr3_vector,
counter,
correct,
savtime,
chk_st_arr3_vector
) ;
end process P17 ;
--
--
end ARCH00088 ;
--
use WORK.STANDARD_TYPES.all ;
entity ENT00088_Test_Bench is
signal s_st_boolean_vector : st_boolean_vector
:= c_st_boolean_vector_1 ;
signal s_st_bit_vector : st_bit_vector
:= c_st_bit_vector_1 ;
signal s_st_severity_level_vector : st_severity_level_vector
:= c_st_severity_level_vector_1 ;
signal s_st_string : st_string
:= c_st_string_1 ;
signal s_st_enum1_vector : st_enum1_vector
:= c_st_enum1_vector_1 ;
signal s_st_integer_vector : st_integer_vector
:= c_st_integer_vector_1 ;
signal s_st_int1_vector : st_int1_vector
:= c_st_int1_vector_1 ;
signal s_st_time_vector : st_time_vector
:= c_st_time_vector_1 ;
signal s_st_phys1_vector : st_phys1_vector
:= c_st_phys1_vector_1 ;
signal s_st_real_vector : st_real_vector
:= c_st_real_vector_1 ;
signal s_st_real1_vector : st_real1_vector
:= c_st_real1_vector_1 ;
signal s_st_rec1_vector : st_rec1_vector
:= c_st_rec1_vector_1 ;
signal s_st_rec2_vector : st_rec2_vector
:= c_st_rec2_vector_1 ;
signal s_st_rec3_vector : st_rec3_vector
:= c_st_rec3_vector_1 ;
signal s_st_arr1_vector : st_arr1_vector
:= c_st_arr1_vector_1 ;
signal s_st_arr2_vector : st_arr2_vector
:= c_st_arr2_vector_1 ;
signal s_st_arr3_vector : st_arr3_vector
:= c_st_arr3_vector_1 ;
--
end ENT00088_Test_Bench ;
--
architecture ARCH00088_Test_Bench of ENT00088_Test_Bench is
begin
L1:
block
component UUT
port (
s_st_boolean_vector : inout st_boolean_vector
; s_st_bit_vector : inout st_bit_vector
; s_st_severity_level_vector : inout st_severity_level_vector
; s_st_string : inout st_string
; s_st_enum1_vector : inout st_enum1_vector
; s_st_integer_vector : inout st_integer_vector
; s_st_int1_vector : inout st_int1_vector
; s_st_time_vector : inout st_time_vector
; s_st_phys1_vector : inout st_phys1_vector
; s_st_real_vector : inout st_real_vector
; s_st_real1_vector : inout st_real1_vector
; s_st_rec1_vector : inout st_rec1_vector
; s_st_rec2_vector : inout st_rec2_vector
; s_st_rec3_vector : inout st_rec3_vector
; s_st_arr1_vector : inout st_arr1_vector
; s_st_arr2_vector : inout st_arr2_vector
; s_st_arr3_vector : inout st_arr3_vector
) ;
end component ;
--
for CIS1 : UUT use entity WORK.ENT00088 ( ARCH00088 ) ;
begin
CIS1 : UUT
port map (
s_st_boolean_vector
, s_st_bit_vector
, s_st_severity_level_vector
, s_st_string
, s_st_enum1_vector
, s_st_integer_vector
, s_st_int1_vector
, s_st_time_vector
, s_st_phys1_vector
, s_st_real_vector
, s_st_real1_vector
, s_st_rec1_vector
, s_st_rec2_vector
, s_st_rec3_vector
, s_st_arr1_vector
, s_st_arr2_vector
, s_st_arr3_vector
) ;
end block L1 ;
end ARCH00088_Test_Bench ;
| gpl-3.0 | e2feff3cd4f9a22458ed17879d604b04 | 0.523066 | 3.683716 | false | false | false | false |
grwlf/vsim | vhdl/array3.vhd | 1 | 532 | -- Aggregate assignments
entity test is
end entity test;
architecture test_arch of test is
type vector is array (0 to 10) of integer;
signal a : vector;
begin
main: process
begin
a <= (0=>0, 1=>1*1, 2=>2*1, others=>33*1) after 1 us,
(0=>0, 1=>1*2, 2=>2*2, others=>33*2) after 2 us,
(0=>0, 1=>1*3, 2=>2*3, others=>33*3) after 3 us;
wait for 10 us;
assert false report "end of simulation" severity failure;
end process;
end architecture test_arch;
| gpl-3.0 | 0c4bf1600794f9ce1a111a01bca06612 | 0.573308 | 3.075145 | false | true | false | false |
jairov4/accel-oil | solution_virtex5/impl/pcores/nfa_accept_samples_generic_hw_top_v1_00_a/simhdl/vhdl/nfa_initials_buckets_if_async_fifo.vhd | 1 | 5,845 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity nfa_initials_buckets_if_async_fifo is
generic (
DATA_WIDTH : integer := 32;
ADDR_WIDTH : integer := 3;
DEPTH : integer := 8);
port (
clk_w : in std_logic;
clk_r : in std_logic;
reset : in std_logic;
if_din : in std_logic_vector(DATA_WIDTH - 1 downto 0);
if_full_n : out std_logic;
if_write_ce: in std_logic := '1';
if_write : in std_logic;
if_dout : out std_logic_vector(DATA_WIDTH - 1 downto 0);
if_empty_n : out std_logic;
if_read_ce : in std_logic := '1';
if_read : in std_logic);
function calc_addr_width(x : integer) return integer is
begin
if (x < 1) then
return 1;
else
return x;
end if;
end function;
end entity;
architecture rtl of nfa_initials_buckets_if_async_fifo is
constant DEPTH_BITS : integer := calc_addr_width(ADDR_WIDTH);
constant REAL_DEPTH : integer := 2 ** DEPTH_BITS;
constant ALL_ONE : unsigned(DEPTH_BITS downto 0) := (others => '1');
constant MASK : std_logic_vector(DEPTH_BITS downto 0) := std_logic_vector(ALL_ONE sll (DEPTH_BITS - 1));
type memtype is array (0 to REAL_DEPTH - 1) of std_logic_vector(DATA_WIDTH - 1 downto 0);
signal mem : memtype;
signal full : std_logic := '0';
signal empty : std_logic := '1';
signal full_next : std_logic;
signal empty_next : std_logic;
signal wraddr_bin : std_logic_vector(DEPTH_BITS downto 0) := (others => '0');
signal rdaddr_bin : std_logic_vector(DEPTH_BITS downto 0) := (others => '0');
signal wraddr : std_logic_vector(DEPTH_BITS - 1 downto 0);
signal rdaddr : std_logic_vector(DEPTH_BITS - 1 downto 0);
signal wraddr_bin_next : std_logic_vector(DEPTH_BITS downto 0);
signal rdaddr_bin_next : std_logic_vector(DEPTH_BITS downto 0);
signal wraddr_gray_next : std_logic_vector(DEPTH_BITS downto 0);
signal rdaddr_gray_next : std_logic_vector(DEPTH_BITS downto 0);
signal wraddr_gray_sync0 : std_logic_vector(DEPTH_BITS downto 0) := (others => '0');
signal rdaddr_gray_sync0 : std_logic_vector(DEPTH_BITS downto 0) := (others => '0');
signal wraddr_gray_sync1 : std_logic_vector(DEPTH_BITS downto 0) := (others => '0');
signal rdaddr_gray_sync1 : std_logic_vector(DEPTH_BITS downto 0) := (others => '0');
signal wraddr_gray_sync2 : std_logic_vector(DEPTH_BITS downto 0) := (others => '0');
signal rdaddr_gray_sync2 : std_logic_vector(DEPTH_BITS downto 0) := (others => '0');
signal dout_buf : std_logic_vector(DATA_WIDTH - 1 downto 0) := (others => '0');
attribute ram_style : string;
attribute ram_style of mem : signal is "block";
begin
if_full_n <= not full;
if_empty_n <= not empty;
if_dout <= dout_buf;
full_next <= '1' when (wraddr_gray_next = (rdaddr_gray_sync2 xor MASK)) else '0';
empty_next <= '1' when (rdaddr_gray_next = wraddr_gray_sync2) else '0';
wraddr <= wraddr_bin(DEPTH_BITS - 1 downto 0);
rdaddr <= rdaddr_bin_next(DEPTH_BITS - 1 downto 0);
wraddr_bin_next <= std_logic_vector(unsigned(wraddr_bin) + 1) when (full = '0' and if_write = '1') else wraddr_bin;
rdaddr_bin_next <= std_logic_vector(unsigned(rdaddr_bin) + 1) when (empty = '0' and if_read = '1') else rdaddr_bin;
wraddr_gray_next <= wraddr_bin_next xor std_logic_vector(unsigned(wraddr_bin_next) srl 1);
rdaddr_gray_next <= rdaddr_bin_next xor std_logic_vector(unsigned(rdaddr_bin_next) srl 1);
-- full, wraddr_bin, wraddr_gray_sync0, rdaddr_gray_sync1, rdaddr_gray_sync2
-- @ clk_w domain
process(clk_w, reset) begin
if (reset = '1') then
full <= '0';
wraddr_bin <= (others => '0');
wraddr_gray_sync0 <= (others => '0');
rdaddr_gray_sync1 <= (others => '0');
rdaddr_gray_sync2 <= (others => '0');
elsif (clk_w'event and clk_w = '1' and if_write_ce = '1') then
full <= full_next;
wraddr_bin <= wraddr_bin_next;
wraddr_gray_sync0 <= wraddr_gray_next;
rdaddr_gray_sync1 <= rdaddr_gray_sync0;
rdaddr_gray_sync2 <= rdaddr_gray_sync1;
end if;
end process;
-- empty, rdaddr_bin, rdaddr_gray_sync0, wraddr_gray_sync1, wraddr_gray_sync2
-- @ clk_r domain
process(clk_r, reset) begin
if (reset = '1') then
empty <= '1';
rdaddr_bin <= (others => '0');
rdaddr_gray_sync0 <= (others => '0');
wraddr_gray_sync1 <= (others => '0');
wraddr_gray_sync2 <= (others => '0');
elsif (clk_r'event and clk_r = '1' and if_read_ce = '1') then
empty <= empty_next;
rdaddr_bin <= rdaddr_bin_next;
rdaddr_gray_sync0 <= rdaddr_gray_next;
wraddr_gray_sync1 <= wraddr_gray_sync0;
wraddr_gray_sync2 <= wraddr_gray_sync1;
end if;
end process;
-- write mem
process(clk_w) begin
if (clk_w'event and clk_w = '1' and if_write_ce = '1') then
if (full = '0' and if_write = '1') then
mem(to_integer(unsigned(wraddr))) <= if_din;
end if;
end if;
end process;
-- read mem
process(clk_r) begin
if (clk_r'event and clk_r = '1' and if_read_ce = '1') then
dout_buf <= mem(to_integer(unsigned(rdaddr)));
end if;
end process;
end architecture;
| lgpl-3.0 | bbc1a26d9cfa54caeaba5c7b1dbe3ce2 | 0.553464 | 3.402212 | false | false | false | false |
wsoltys/AtomFpga | src/T6502/T65_MCode.vhd | 1 | 44,172 | -- ****
-- T65(b) core. In an effort to merge and maintain bug fixes ....
--
--
-- Ver 302 minor timing fixes
-- Ver 301 Jump timing fixed
-- Ver 300 Bugfixes by ehenciak added
-- MikeJ March 2005
-- Latest version from www.fpgaarcade.com (original www.opencores.org)
--
-- ****
--
-- 65xx compatible microprocessor core
--
-- Version : 0246 + fix
--
-- Copyright (c) 2002 Daniel Wallner ([email protected])
--
-- All rights reserved
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--
-- Redistributions in synthesized form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- Neither the name of the author nor the names of other contributors may
-- be used to endorse or promote products derived from this software without
-- specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- Please report bugs to the author, but before you do so, please
-- make sure that this is not a derivative work and that
-- you have the latest version of this file.
--
-- The latest version of this file can be found at:
-- http://www.opencores.org/cvsweb.shtml/t65/
--
-- Limitations :
--
-- 65C02
-- supported : inc, dec, phx, plx, phy, ply
-- missing : bra, ora, lda, cmp, sbc, tsb*2, trb*2, stz*2, bit*2, wai, stp, jmp, bbr*8, bbs*8
--
-- File history :
--
-- 0246 : First release
--
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.T65_Pack.all;
entity T65_MCode is
port(
Mode : in std_logic_vector(1 downto 0); -- "00" => 6502, "01" => 65C02, "10" => 65816
IR : in std_logic_vector(7 downto 0);
MCycle : in std_logic_vector(2 downto 0);
P : in std_logic_vector(7 downto 0);
LCycle : out std_logic_vector(2 downto 0);
ALU_Op : out std_logic_vector(3 downto 0);
Set_BusA_To : out std_logic_vector(2 downto 0); -- DI,A,X,Y,S,P
Set_Addr_To : out std_logic_vector(1 downto 0); -- PC Adder,S,AD,BA
Write_Data : out std_logic_vector(2 downto 0); -- DL,A,X,Y,S,P,PCL,PCH
Jump : out std_logic_vector(1 downto 0); -- PC,++,DIDL,Rel
BAAdd : out std_logic_vector(1 downto 0); -- None,DB Inc,BA Add,BA Adj
BreakAtNA : out std_logic;
ADAdd : out std_logic;
AddY : out std_logic;
PCAdd : out std_logic;
Inc_S : out std_logic;
Dec_S : out std_logic;
LDA : out std_logic;
LDP : out std_logic;
LDX : out std_logic;
LDY : out std_logic;
LDS : out std_logic;
LDDI : out std_logic;
LDALU : out std_logic;
LDAD : out std_logic;
LDBAL : out std_logic;
LDBAH : out std_logic;
SaveP : out std_logic;
Write : out std_logic
);
end T65_MCode;
architecture rtl of T65_MCode is
signal Branch : std_logic;
begin
with IR(7 downto 5) select
Branch <= not P(Flag_N) when "000",
P(Flag_N) when "001",
not P(Flag_V) when "010",
P(Flag_V) when "011",
not P(Flag_C) when "100",
P(Flag_C) when "101",
not P(Flag_Z) when "110",
P(Flag_Z) when others;
process (IR, MCycle, P, Branch, Mode)
begin
LCycle <= "001";
Set_BusA_To <= "001"; -- A
Set_Addr_To <= (others => '0');
Write_Data <= (others => '0');
Jump <= (others => '0');
BAAdd <= "00";
BreakAtNA <= '0';
ADAdd <= '0';
PCAdd <= '0';
Inc_S <= '0';
Dec_S <= '0';
LDA <= '0';
LDP <= '0';
LDX <= '0';
LDY <= '0';
LDS <= '0';
LDDI <= '0';
LDALU <= '0';
LDAD <= '0';
LDBAL <= '0';
LDBAH <= '0';
SaveP <= '0';
Write <= '0';
AddY <= '0';
case IR(7 downto 5) is
when "100" =>
--{{{
case IR(1 downto 0) is
when "00" =>
Set_BusA_To <= "011"; -- Y
Write_Data <= "011"; -- Y
when "10" =>
Set_BusA_To <= "010"; -- X
Write_Data <= "010"; -- X
when others =>
Write_Data <= "001"; -- A
end case;
--}}}
when "101" =>
--{{{
case IR(1 downto 0) is
when "00" =>
if IR(4) /= '1' or IR(2) /= '0' then
LDY <= '1';
end if;
when "10" =>
LDX <= '1';
when others =>
LDA <= '1';
end case;
Set_BusA_To <= "000"; -- DI
--}}}
when "110" =>
--{{{
case IR(1 downto 0) is
when "00" =>
if IR(4) = '0' then
LDY <= '1';
end if;
Set_BusA_To <= "011"; -- Y
when others =>
Set_BusA_To <= "001"; -- A
end case;
--}}}
when "111" =>
--{{{
case IR(1 downto 0) is
when "00" =>
if IR(4) = '0' then
LDX <= '1';
end if;
Set_BusA_To <= "010"; -- X
when others =>
Set_BusA_To <= "001"; -- A
end case;
--}}}
when others =>
end case;
if IR(7 downto 6) /= "10" and IR(1 downto 0) = "10" then
Set_BusA_To <= "000"; -- DI
end if;
case IR(4 downto 0) is
when "00000" | "01000" | "01010" | "11000" | "11010" =>
--{{{
-- Implied
case IR is
when "00000000" =>
-- BRK
LCycle <= "110";
case to_integer(unsigned(MCycle)) is
when 1 =>
Set_Addr_To <= "01"; -- S
Write_Data <= "111"; -- PCH
Write <= '1';
when 2 =>
Dec_S <= '1';
Set_Addr_To <= "01"; -- S
Write_Data <= "110"; -- PCL
Write <= '1';
when 3 =>
Dec_S <= '1';
Set_Addr_To <= "01"; -- S
Write_Data <= "101"; -- P
Write <= '1';
when 4 =>
Dec_S <= '1';
Set_Addr_To <= "11"; -- BA
when 5 =>
LDDI <= '1';
Set_Addr_To <= "11"; -- BA
when 6 =>
Jump <= "10"; -- DIDL
when others =>
end case;
when "00100000" =>
-- JSR
LCycle <= "101";
case to_integer(unsigned(MCycle)) is
when 1 =>
Jump <= "01";
LDDI <= '1';
Set_Addr_To <= "01"; -- S
when 2 =>
Set_Addr_To <= "01"; -- S
Write_Data <= "111"; -- PCH
Write <= '1';
when 3 =>
Dec_S <= '1';
Set_Addr_To <= "01"; -- S
Write_Data <= "110"; -- PCL
Write <= '1';
when 4 =>
Dec_S <= '1';
when 5 =>
Jump <= "10"; -- DIDL
when others =>
end case;
when "01000000" =>
-- RTI
LCycle <= "101";
case to_integer(unsigned(MCycle)) is
when 1 =>
Set_Addr_To <= "01"; -- S
when 2 =>
Inc_S <= '1';
Set_Addr_To <= "01"; -- S
when 3 =>
Inc_S <= '1';
Set_Addr_To <= "01"; -- S
Set_BusA_To <= "000"; -- DI
when 4 =>
LDP <= '1';
Inc_S <= '1';
LDDI <= '1';
Set_Addr_To <= "01"; -- S
when 5 =>
Jump <= "10"; -- DIDL
when others =>
end case;
when "01100000" =>
-- RTS
LCycle <= "101";
case to_integer(unsigned(MCycle)) is
when 1 =>
Set_Addr_To <= "01"; -- S
when 2 =>
Inc_S <= '1';
Set_Addr_To <= "01"; -- S
when 3 =>
Inc_S <= '1';
LDDI <= '1';
Set_Addr_To <= "01"; -- S
when 4 =>
Jump <= "10"; -- DIDL
when 5 =>
Jump <= "01";
when others =>
end case;
when "00001000" | "01001000" | "01011010" | "11011010" =>
-- PHP, PHA, PHY*, PHX*
LCycle <= "010";
if Mode = "00" and IR(1) = '1' then
LCycle <= "001";
end if;
case to_integer(unsigned(MCycle)) is
when 1 =>
case IR(7 downto 4) is
when "0000" =>
Write_Data <= "101"; -- P
when "0100" =>
Write_Data <= "001"; -- A
when "0101" =>
Write_Data <= "011"; -- Y
when "1101" =>
Write_Data <= "010"; -- X
when others =>
end case;
Write <= '1';
Set_Addr_To <= "01"; -- S
when 2 =>
Dec_S <= '1';
when others =>
end case;
when "00101000" | "01101000" | "01111010" | "11111010" =>
-- PLP, PLA, PLY*, PLX*
LCycle <= "011";
if Mode = "00" and IR(1) = '1' then
LCycle <= "001";
end if;
case IR(7 downto 4) is
when "0010" =>
LDP <= '1';
when "0110" =>
LDA <= '1';
when "0111" =>
if Mode /= "00" then
LDY <= '1';
end if;
when "1111" =>
if Mode /= "00" then
LDX <= '1';
end if;
when others =>
end case;
case to_integer(unsigned(MCycle)) is
when 0 =>
SaveP <= '1';
when 1 =>
Set_Addr_To <= "01"; -- S
when 2 =>
Inc_S <= '1';
Set_Addr_To <= "01"; -- S
when 3 =>
Set_BusA_To <= "000"; -- DI
when others =>
end case;
when "10100000" | "11000000" | "11100000" =>
-- LDY, CPY, CPX
-- Immediate
case to_integer(unsigned(MCycle)) is
when 0 =>
when 1 =>
Jump <= "01";
when others =>
end case;
when "10001000" =>
-- DEY
LDY <= '1';
case to_integer(unsigned(MCycle)) is
when 0 =>
when 1 =>
Set_BusA_To <= "011"; -- Y
when others =>
end case;
when "11001010" =>
-- DEX
LDX <= '1';
case to_integer(unsigned(MCycle)) is
when 0 =>
when 1 =>
Set_BusA_To <= "010"; -- X
when others =>
end case;
when "00011010" | "00111010" =>
-- INC*, DEC*
if Mode /= "00" then
LDA <= '1'; -- A
end if;
case to_integer(unsigned(MCycle)) is
when 0 =>
when 1 =>
Set_BusA_To <= "100"; -- S
when others =>
end case;
when "00001010" | "00101010" | "01001010" | "01101010" =>
-- ASL, ROL, LSR, ROR
LDA <= '1'; -- A
Set_BusA_To <= "001"; -- A
case to_integer(unsigned(MCycle)) is
when 0 =>
when 1 =>
when others =>
end case;
when "10001010" | "10011000" =>
-- TYA, TXA
LDA <= '1'; -- A
case to_integer(unsigned(MCycle)) is
when 0 =>
when 1 =>
when others =>
end case;
when "10101010" | "10101000" =>
-- TAX, TAY
case to_integer(unsigned(MCycle)) is
when 0 =>
when 1 =>
Set_BusA_To <= "001"; -- A
when others =>
end case;
when "10011010" =>
-- TXS
case to_integer(unsigned(MCycle)) is
when 0 =>
LDS <= '1';
when 1 =>
when others =>
end case;
when "10111010" =>
-- TSX
LDX <= '1';
case to_integer(unsigned(MCycle)) is
when 0 =>
when 1 =>
Set_BusA_To <= "100"; -- S
when others =>
end case;
-- when "00011000" | "00111000" | "01011000" | "01111000" | "10111000" | "11011000" | "11111000" | "11001000" | "11101000" =>
-- -- CLC, SEC, CLI, SEI, CLV, CLD, SED, INY, INX
-- case to_integer(unsigned(MCycle)) is
-- when 1 =>
-- when others =>
-- end case;
when others =>
case to_integer(unsigned(MCycle)) is
when 0 =>
when others =>
end case;
end case;
--}}}
when "00001" | "00011" =>
--{{{
-- Zero Page Indexed Indirect (d,x)
LCycle <= "101";
if IR(7 downto 6) /= "10" then
LDA <= '1';
end if;
case to_integer(unsigned(MCycle)) is
when 0 =>
when 1 =>
Jump <= "01";
LDAD <= '1';
Set_Addr_To <= "10"; -- AD
when 2 =>
ADAdd <= '1';
Set_Addr_To <= "10"; -- AD
when 3 =>
BAAdd <= "01"; -- DB Inc
LDBAL <= '1';
Set_Addr_To <= "10"; -- AD
when 4 =>
LDBAH <= '1';
if IR(7 downto 5) = "100" then
Write <= '1';
end if;
Set_Addr_To <= "11"; -- BA
when 5 =>
when others =>
end case;
--}}}
when "01001" | "01011" =>
--{{{
-- Immediate
LDA <= '1';
case to_integer(unsigned(MCycle)) is
when 0 =>
when 1 =>
Jump <= "01";
when others =>
end case;
--}}}
when "00010" | "10010" =>
--{{{
-- Immediate, KIL
LDX <= '1';
case to_integer(unsigned(MCycle)) is
when 0 =>
when 1 =>
if IR = "10100010" then
-- LDX
Jump <= "01";
else
-- KIL !!!!!!!!!!!!!!!!!!!!!!!!!!!!!
end if;
when others =>
end case;
--}}}
when "00100" =>
--{{{
-- Zero Page
LCycle <= "010";
case to_integer(unsigned(MCycle)) is
when 0 =>
if IR(7 downto 5) = "001" then
SaveP <= '1';
end if;
when 1 =>
Jump <= "01";
LDAD <= '1';
if IR(7 downto 5) = "100" then
Write <= '1';
end if;
Set_Addr_To <= "10"; -- AD
when 2 =>
when others =>
end case;
--}}}
when "00101" | "00110" | "00111" =>
--{{{
-- Zero Page
if IR(7 downto 6) /= "10" and IR(1 downto 0) = "10" then
-- Read-Modify-Write
LCycle <= "100";
case to_integer(unsigned(MCycle)) is
when 1 =>
Jump <= "01";
LDAD <= '1';
Set_Addr_To <= "10"; -- AD
when 2 =>
LDDI <= '1';
Write <= '1';
Set_Addr_To <= "10"; -- AD
when 3 =>
LDALU <= '1';
SaveP <= '1';
Write <= '1';
Set_Addr_To <= "10"; -- AD
when 4 =>
when others =>
end case;
else
LCycle <= "010";
if IR(7 downto 6) /= "10" then
LDA <= '1';
end if;
case to_integer(unsigned(MCycle)) is
when 0 =>
when 1 =>
Jump <= "01";
LDAD <= '1';
if IR(7 downto 5) = "100" then
Write <= '1';
end if;
Set_Addr_To <= "10"; -- AD
when 2 =>
when others =>
end case;
end if;
--}}}
when "01100" =>
--{{{
-- Absolute
if IR(7 downto 6) = "01" and IR(4 downto 0) = "01100" then
-- JMP
if IR(5) = '0' then
--LCycle <= "011";
LCycle <= "010";
case to_integer(unsigned(MCycle)) is
when 1 =>
Jump <= "01";
LDDI <= '1';
when 2 =>
Jump <= "10"; -- DIDL
when others =>
end case;
else
--LCycle <= "101";
LCycle <= "100"; -- mikej
case to_integer(unsigned(MCycle)) is
when 1 =>
Jump <= "01";
LDDI <= '1';
LDBAL <= '1';
when 2 =>
LDBAH <= '1';
if Mode /= "00" then
Jump <= "10"; -- DIDL
end if;
if Mode = "00" then
Set_Addr_To <= "11"; -- BA
end if;
when 3 =>
LDDI <= '1';
if Mode = "00" then
Set_Addr_To <= "11"; -- BA
BAAdd <= "01"; -- DB Inc
else
Jump <= "01";
end if;
when 4 =>
Jump <= "10"; -- DIDL
when others =>
end case;
end if;
else
LCycle <= "011";
case to_integer(unsigned(MCycle)) is
when 0 =>
if IR(7 downto 5) = "001" then
SaveP <= '1';
end if;
when 1 =>
Jump <= "01";
LDBAL <= '1';
when 2 =>
Jump <= "01";
LDBAH <= '1';
if IR(7 downto 5) = "100" then
Write <= '1';
end if;
Set_Addr_To <= "11"; -- BA
when 3 =>
when others =>
end case;
end if;
--}}}
when "01101" | "01110" | "01111" =>
--{{{
-- Absolute
if IR(7 downto 6) /= "10" and IR(1 downto 0) = "10" then
-- Read-Modify-Write
LCycle <= "101";
case to_integer(unsigned(MCycle)) is
when 1 =>
Jump <= "01";
LDBAL <= '1';
when 2 =>
Jump <= "01";
LDBAH <= '1';
Set_Addr_To <= "11"; -- BA
when 3 =>
LDDI <= '1';
Write <= '1';
Set_Addr_To <= "11"; -- BA
when 4 =>
Write <= '1';
LDALU <= '1';
SaveP <= '1';
Set_Addr_To <= "11"; -- BA
when 5 =>
SaveP <= '0'; -- MIKEJ was 1
when others =>
end case;
else
LCycle <= "011";
if IR(7 downto 6) /= "10" then
LDA <= '1';
end if;
case to_integer(unsigned(MCycle)) is
when 0 =>
when 1 =>
Jump <= "01";
LDBAL <= '1';
when 2 =>
Jump <= "01";
LDBAH <= '1';
if IR(7 downto 5) = "100" then
Write <= '1';
end if;
Set_Addr_To <= "11"; -- BA
when 3 =>
when others =>
end case;
end if;
--}}}
when "10000" =>
--{{{
-- Relative
-- This circuit dictates when the last
-- microcycle occurs for the branch depending on
-- whether or not the branch is taken and if a page
-- is crossed...
if (Branch = '1') then
LCycle <= "011"; -- We're done @ T3 if branching...upper
-- level logic will stop at T2 if no page cross
-- (See the Break signal)
else
LCycle <= "001";
end if;
-- This decodes the current microcycle and takes the
-- proper course of action...
case to_integer(unsigned(MCycle)) is
-- On the T1 microcycle, increment the program counter
-- and instruct the upper level logic to fetch the offset
-- from the Din bus and store it in the data latches. This
-- will be the last microcycle if the branch isn't taken.
when 1 =>
Jump <= "01"; -- Increments the PC by one (PC will now be PC+2)
-- from microcycle T0.
LDDI <= '1'; -- Tells logic in top level (T65.vhd) to route
-- the Din bus to the memory data latch (DL)
-- so that the branch offset is fetched.
-- In microcycle T2, tell the logic in the top level to
-- add the offset. If the most significant byte of the
-- program counter (i.e. the current "page") does not need
-- updating, we are done here...the Break signal at the
-- T65.vhd level takes care of that...
when 2 =>
Jump <= "11"; -- Tell the PC Jump logic to use relative mode.
PCAdd <= '1'; -- This tells the PC adder to update itself with
-- the current offset recently fetched from
-- memory.
-- The following is microcycle T3 :
-- The program counter should be completely updated
-- on this cycle after the page cross is detected.
-- We don't need to do anything here...
when 3 =>
when others => null; -- Do nothing.
end case;
--}}}
when "10001" | "10011" =>
--{{{
-- Zero Page Indirect Indexed (d),y
LCycle <= "101";
if IR(7 downto 6) /= "10" then
LDA <= '1';
end if;
case to_integer(unsigned(MCycle)) is
when 0 =>
when 1 =>
Jump <= "01";
LDAD <= '1';
Set_Addr_To <= "10"; -- AD
when 2 =>
LDBAL <= '1';
BAAdd <= "01"; -- DB Inc
Set_Addr_To <= "10"; -- AD
when 3 =>
Set_BusA_To <= "011"; -- Y
BAAdd <= "10"; -- BA Add
LDBAH <= '1';
Set_Addr_To <= "11"; -- BA
when 4 =>
BAAdd <= "11"; -- BA Adj
if IR(7 downto 5) = "100" then
Write <= '1';
else
BreakAtNA <= '1';
end if;
Set_Addr_To <= "11"; -- BA
when 5 =>
when others =>
end case;
--}}}
when "10100" | "10101" | "10110" | "10111" =>
--{{{
-- Zero Page, X
if IR(7 downto 6) /= "10" and IR(1 downto 0) = "10" then
-- Read-Modify-Write
LCycle <= "101";
case to_integer(unsigned(MCycle)) is
when 1 =>
Jump <= "01";
LDAD <= '1';
Set_Addr_To <= "10"; -- AD
when 2 =>
ADAdd <= '1';
Set_Addr_To <= "10"; -- AD
when 3 =>
LDDI <= '1';
Write <= '1';
Set_Addr_To <= "10"; -- AD
when 4 =>
LDALU <= '1';
SaveP <= '1';
Write <= '1';
Set_Addr_To <= "10"; -- AD
when 5 =>
when others =>
end case;
else
LCycle <= "011";
if IR(7 downto 6) /= "10" then
LDA <= '1';
end if;
case to_integer(unsigned(MCycle)) is
when 0 =>
when 1 =>
Jump <= "01";
LDAD <= '1';
Set_Addr_To <= "10"; -- AD
when 2 =>
ADAdd <= '1';
-- Added this check for Y reg. use...
if (IR(3 downto 0) = "0110") then
AddY <= '1';
end if;
if IR(7 downto 5) = "100" then
Write <= '1';
end if;
Set_Addr_To <= "10"; -- AD
when 3 => null;
when others =>
end case;
end if;
--}}}
when "11001" | "11011" =>
--{{{
-- Absolute Y
LCycle <= "100";
if IR(7 downto 6) /= "10" then
LDA <= '1';
end if;
case to_integer(unsigned(MCycle)) is
when 0 =>
when 1 =>
Jump <= "01";
LDBAL <= '1';
when 2 =>
Jump <= "01";
Set_BusA_To <= "011"; -- Y
BAAdd <= "10"; -- BA Add
LDBAH <= '1';
Set_Addr_To <= "11"; -- BA
when 3 =>
BAAdd <= "11"; -- BA adj
if IR(7 downto 5) = "100" then
Write <= '1';
else
BreakAtNA <= '1';
end if;
Set_Addr_To <= "11"; -- BA
when 4 =>
when others =>
end case;
--}}}
when "11100" | "11101" | "11110" | "11111" =>
--{{{
-- Absolute X
if IR(7 downto 6) /= "10" and IR(1 downto 0) = "10" then
-- Read-Modify-Write
LCycle <= "110";
case to_integer(unsigned(MCycle)) is
when 1 =>
Jump <= "01";
LDBAL <= '1';
when 2 =>
Jump <= "01";
Set_BusA_To <= "010"; -- X
BAAdd <= "10"; -- BA Add
LDBAH <= '1';
Set_Addr_To <= "11"; -- BA
when 3 =>
BAAdd <= "11"; -- BA adj
Set_Addr_To <= "11"; -- BA
when 4 =>
LDDI <= '1';
Write <= '1';
Set_Addr_To <= "11"; -- BA
when 5 =>
LDALU <= '1';
SaveP <= '1';
Write <= '1';
Set_Addr_To <= "11"; -- BA
when 6 =>
when others =>
end case;
else
LCycle <= "100";
if IR(7 downto 6) /= "10" then
LDA <= '1';
end if;
case to_integer(unsigned(MCycle)) is
when 0 =>
when 1 =>
Jump <= "01";
LDBAL <= '1';
when 2 =>
Jump <= "01";
-- mikej
-- special case 0xBE which uses Y reg as index!!
if (IR = "10111110") then
Set_BusA_To <= "011"; -- Y
else
Set_BusA_To <= "010"; -- X
end if;
BAAdd <= "10"; -- BA Add
LDBAH <= '1';
Set_Addr_To <= "11"; -- BA
when 3 =>
BAAdd <= "11"; -- BA adj
if IR(7 downto 5) = "100" then
Write <= '1';
else
BreakAtNA <= '1';
end if;
Set_Addr_To <= "11"; -- BA
when 4 =>
when others =>
end case;
end if;
--}}}
when others =>
end case;
end process;
process (IR, MCycle)
begin
-- ORA, AND, EOR, ADC, NOP, LD, CMP, SBC
-- ASL, ROL, LSR, ROR, BIT, LD, DEC, INC
case IR(1 downto 0) is
when "00" =>
--{{{
case IR(4 downto 2) is
when "000" | "001" | "011" =>
case IR(7 downto 5) is
when "110" | "111" =>
-- CP
ALU_Op <= "0110";
when "101" =>
-- LD
ALU_Op <= "0101";
when "001" =>
-- BIT
ALU_Op <= "1100";
when others =>
-- NOP/ST
ALU_Op <= "0100";
end case;
when "010" =>
case IR(7 downto 5) is
when "111" | "110" =>
-- IN
ALU_Op <= "1111";
when "100" =>
-- DEY
ALU_Op <= "1110";
when others =>
-- LD
ALU_Op <= "1101";
end case;
when "110" =>
case IR(7 downto 5) is
when "100" =>
-- TYA
ALU_Op <= "1101";
when others =>
ALU_Op <= "----";
end case;
when others =>
case IR(7 downto 5) is
when "101" =>
-- LD
ALU_Op <= "1101";
when others =>
ALU_Op <= "0100";
end case;
end case;
--}}}
when "01" => -- OR
--{{{
ALU_Op(3) <= '0';
ALU_Op(2 downto 0) <= IR(7 downto 5);
--}}}
when "10" =>
--{{{
ALU_Op(3) <= '1';
ALU_Op(2 downto 0) <= IR(7 downto 5);
case IR(7 downto 5) is
when "000" =>
if IR(4 downto 2) = "110" then
-- INC
ALU_Op <= "1111";
end if;
when "001" =>
if IR(4 downto 2) = "110" then
-- DEC
ALU_Op <= "1110";
end if;
when "100" =>
if IR(4 downto 2) = "010" then
-- TXA
ALU_Op <= "0101";
else
ALU_Op <= "0100";
end if;
when others =>
end case;
--}}}
when others =>
--{{{
case IR(7 downto 5) is
when "100" =>
ALU_Op <= "0100";
when others =>
if MCycle = "000" then
ALU_Op(3) <= '0';
ALU_Op(2 downto 0) <= IR(7 downto 5);
else
ALU_Op(3) <= '1';
ALU_Op(2 downto 0) <= IR(7 downto 5);
end if;
end case;
--}}}
end case;
end process;
end;
| apache-2.0 | 2623355ae24c6c78e39a82753c81edfa | 0.268315 | 5.643542 | false | false | false | false |
grwlf/vsim | vhdl_ct/ct00103.vhd | 1 | 5,709 | -- NEED RESULT: ARCH00103.P1: Multi transport transactions occurred on signal asg with slice name prefixed by an indexed name on LHS failed
-- NEED RESULT: ARCH00103: One transport transaction occurred on signal asg with slice name prefixed by an indexed name on LHS failed
-- NEED RESULT: ARCH00103: Old transactions were removed on signal asg with slice name prefixed by an indexed name on LHS failed
-- NEED RESULT: P1: Transport transactions entirely completed passed
-------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
-------------------------------------------------------------------------------
--
-- TEST NAME:
--
-- CT00103
--
-- AUTHOR:
--
-- G. Tominovich
--
-- TEST OBJECTIVES:
--
-- 8.3 (2)
-- 8.3 (3)
-- 8.3 (5)
-- 8.3.1 (3)
--
-- DESIGN UNIT ORDERING:
--
-- ENT00103(ARCH00103)
-- ENT00103_Test_Bench(ARCH00103_Test_Bench)
--
-- REVISION HISTORY:
--
-- 07-JUL-1987 - initial revision
--
-- NOTES:
--
-- self-checking
-- automatically generated
--
use WORK.STANDARD_TYPES.all ;
entity ENT00103 is
subtype chk_sig_type is integer range -1 to 100 ;
signal chk_st_arr1_vector : chk_sig_type := -1 ;
--
procedure Proc1 (
signal s_st_arr1_vector : inout st_arr1_vector ;
variable counter : inout integer ;
variable correct : inout boolean ;
variable savtime : inout time ;
signal chk_st_arr1_vector : out chk_sig_type
)
is
begin
case counter is
when 0
=> s_st_arr1_vector(lowb) (lowb+1 to highb-1) <= transport
c_st_arr1_vector_2(highb)
(lowb+1 to highb-1) after 10 ns,
c_st_arr1_vector_1(highb)
(lowb+1 to highb-1) after 20 ns ;
--
when 1
=> correct :=
s_st_arr1_vector(lowb) (lowb+1 to highb-1) =
c_st_arr1_vector_2(highb) (lowb+1 to highb-1) and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_arr1_vector(lowb) (lowb+1 to highb-1) =
c_st_arr1_vector_1(highb) (lowb+1 to highb-1) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00103.P1" ,
"Multi transport transactions occurred on signal " &
"asg with slice name prefixed by an indexed name on LHS",
correct ) ;
s_st_arr1_vector(lowb) (lowb+1 to highb-1) <= transport
c_st_arr1_vector_2(highb)
(lowb+1 to highb-1) after 10 ns ,
c_st_arr1_vector_1(highb)
(lowb+1 to highb-1) after 20 ns ,
c_st_arr1_vector_2(highb)
(lowb+1 to highb-1) after 30 ns ,
c_st_arr1_vector_1(highb)
(lowb+1 to highb-1) after 40 ns ;
--
when 3
=> correct :=
s_st_arr1_vector(lowb) (lowb+1 to highb-1) =
c_st_arr1_vector_2(highb) (lowb+1 to highb-1) and
(savtime + 10 ns) = Std.Standard.Now ;
s_st_arr1_vector(lowb) (lowb+1 to highb-1) <= transport
c_st_arr1_vector_1(highb)
(lowb+1 to highb-1) after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_arr1_vector(lowb) (lowb+1 to highb-1) =
c_st_arr1_vector_1(highb) (lowb+1 to highb-1) and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00103" ,
"One transport transaction occurred on signal " &
"asg with slice name prefixed by an indexed name on LHS",
correct ) ;
test_report ( "ARCH00103" ,
"Old transactions were removed on signal " &
"asg with slice name prefixed by an indexed name on LHS",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00103" ,
"Old transactions were removed on signal " &
"asg with slice name prefixed by an indexed name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_st_arr1_vector <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
end Proc1 ;
--
--
end ENT00103 ;
--
architecture ARCH00103 of ENT00103 is
signal s_st_arr1_vector : st_arr1_vector
:= c_st_arr1_vector_1 ;
--
begin
PGEN_CHKP_1 :
process ( chk_st_arr1_vector )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P1" ,
"Transport transactions entirely completed",
chk_st_arr1_vector = 4 ) ;
end if ;
end process PGEN_CHKP_1 ;
--
P1 :
process ( s_st_arr1_vector )
variable counter : integer := 0 ;
variable correct : boolean ;
variable savtime : time ;
begin
Proc1 (
s_st_arr1_vector,
counter,
correct,
savtime,
chk_st_arr1_vector
) ;
end process P1 ;
--
--
end ARCH00103 ;
--
entity ENT00103_Test_Bench is
end ENT00103_Test_Bench ;
--
architecture ARCH00103_Test_Bench of ENT00103_Test_Bench is
begin
L1:
block
component UUT
end component ;
for CIS1 : UUT use entity WORK.ENT00103 ( ARCH00103 ) ;
begin
CIS1 : UUT ;
end block L1 ;
end ARCH00103_Test_Bench ;
| gpl-3.0 | 2e1ef785c6fabba26b991aa1b4fd50d4 | 0.518304 | 3.543762 | false | true | false | false |
grwlf/vsim | vhdl_ct/ct00134.vhd | 1 | 79,429 | -- NEED RESULT: ARCH00134.P1: Multi inertial transactions occurred on signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00134.P2: Multi inertial transactions occurred on signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00134.P3: Multi inertial transactions occurred on signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00134.P4: Multi inertial transactions occurred on signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00134.P5: Multi inertial transactions occurred on signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00134.P6: Multi inertial transactions occurred on signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00134.P7: Multi inertial transactions occurred on signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00134.P8: Multi inertial transactions occurred on signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00134.P9: Multi inertial transactions occurred on signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00134.P10: Multi inertial transactions occurred on signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00134.P11: Multi inertial transactions occurred on signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00134.P12: Multi inertial transactions occurred on signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00134.P13: Multi inertial transactions occurred on signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00134.P14: Multi inertial transactions occurred on signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00134.P15: Multi inertial transactions occurred on signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00134.P16: Multi inertial transactions occurred on signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00134.P17: Multi inertial transactions occurred on signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00134: One inertial transaction occurred on signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00134: One inertial transaction occurred on signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00134: One inertial transaction occurred on signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00134: One inertial transaction occurred on signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00134: One inertial transaction occurred on signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00134: One inertial transaction occurred on signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00134: One inertial transaction occurred on signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00134: One inertial transaction occurred on signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00134: One inertial transaction occurred on signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00134: One inertial transaction occurred on signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00134: One inertial transaction occurred on signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00134: One inertial transaction occurred on signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00134: One inertial transaction occurred on signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00134: One inertial transaction occurred on signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00134: One inertial transaction occurred on signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00134: One inertial transaction occurred on signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00134: One inertial transaction occurred on signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00134: Old transactions were removed on signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00134: Old transactions were removed on signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00134: Old transactions were removed on signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00134: Old transactions were removed on signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00134: Old transactions were removed on signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00134: Old transactions were removed on signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00134: Old transactions were removed on signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00134: Old transactions were removed on signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00134: Old transactions were removed on signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00134: Old transactions were removed on signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00134: Old transactions were removed on signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00134: Old transactions were removed on signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00134: Old transactions were removed on signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00134: Old transactions were removed on signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00134: Old transactions were removed on signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00134: Old transactions were removed on signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00134: Old transactions were removed on signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00134: One inertial transaction occurred on signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00134: One inertial transaction occurred on signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00134: One inertial transaction occurred on signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00134: One inertial transaction occurred on signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00134: One inertial transaction occurred on signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00134: One inertial transaction occurred on signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00134: One inertial transaction occurred on signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00134: One inertial transaction occurred on signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00134: One inertial transaction occurred on signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00134: One inertial transaction occurred on signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00134: One inertial transaction occurred on signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00134: One inertial transaction occurred on signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00134: One inertial transaction occurred on signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00134: One inertial transaction occurred on signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00134: One inertial transaction occurred on signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00134: One inertial transaction occurred on signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00134: One inertial transaction occurred on signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00134: Inertial semantics check on a signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00134: Inertial semantics check on a signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00134: Inertial semantics check on a signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00134: Inertial semantics check on a signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00134: Inertial semantics check on a signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00134: Inertial semantics check on a signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00134: Inertial semantics check on a signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00134: Inertial semantics check on a signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00134: Inertial semantics check on a signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00134: Inertial semantics check on a signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00134: Inertial semantics check on a signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00134: Inertial semantics check on a signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00134: Inertial semantics check on a signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00134: Inertial semantics check on a signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00134: Inertial semantics check on a signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00134: Inertial semantics check on a signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00134: Inertial semantics check on a signal asg with simple name on LHS passed
-- NEED RESULT: P17: Inertial transactions entirely completed passed
-- NEED RESULT: P16: Inertial transactions entirely completed passed
-- NEED RESULT: P15: Inertial transactions entirely completed passed
-- NEED RESULT: P14: Inertial transactions entirely completed passed
-- NEED RESULT: P13: Inertial transactions entirely completed passed
-- NEED RESULT: P12: Inertial transactions entirely completed passed
-- NEED RESULT: P11: Inertial transactions entirely completed passed
-- NEED RESULT: P10: Inertial transactions entirely completed passed
-- NEED RESULT: P9: Inertial transactions entirely completed passed
-- NEED RESULT: P8: Inertial transactions entirely completed passed
-- NEED RESULT: P7: Inertial transactions entirely completed passed
-- NEED RESULT: P6: Inertial transactions entirely completed passed
-- NEED RESULT: P5: Inertial transactions entirely completed passed
-- NEED RESULT: P4: Inertial transactions entirely completed passed
-- NEED RESULT: P3: Inertial transactions entirely completed passed
-- NEED RESULT: P2: Inertial transactions entirely completed passed
-- NEED RESULT: P1: Inertial transactions entirely completed passed
-------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
-------------------------------------------------------------------------------
--
-- TEST NAME:
--
-- CT00134
--
-- AUTHOR:
--
-- G. Tominovich
--
-- TEST OBJECTIVES:
--
-- 8.3 (1)
-- 8.3 (2)
-- 8.3 (4)
-- 8.3 (5)
-- 8.3.1 (4)
--
-- DESIGN UNIT ORDERING:
--
-- ENT00134(ARCH00134)
-- ENT00134_Test_Bench(ARCH00134_Test_Bench)
--
-- REVISION HISTORY:
--
-- 08-JUL-1987 - initial revision
--
-- NOTES:
--
-- self-checking
-- automatically generated
--
use WORK.STANDARD_TYPES.all ;
entity ENT00134 is
port (
s_boolean : inout boolean
; s_bit : inout bit
; s_severity_level : inout severity_level
; s_character : inout character
; s_st_enum1 : inout st_enum1
; s_integer : inout integer
; s_st_int1 : inout st_int1
; s_time : inout time
; s_st_phys1 : inout st_phys1
; s_real : inout real
; s_st_real1 : inout st_real1
; s_st_rec1 : inout st_rec1
; s_st_rec2 : inout st_rec2
; s_st_rec3 : inout st_rec3
; s_st_arr1 : inout st_arr1
; s_st_arr2 : inout st_arr2
; s_st_arr3 : inout st_arr3
) ;
subtype chk_sig_type is integer range -1 to 100 ;
signal chk_boolean : chk_sig_type := -1 ;
signal chk_bit : chk_sig_type := -1 ;
signal chk_severity_level : chk_sig_type := -1 ;
signal chk_character : chk_sig_type := -1 ;
signal chk_st_enum1 : chk_sig_type := -1 ;
signal chk_integer : chk_sig_type := -1 ;
signal chk_st_int1 : chk_sig_type := -1 ;
signal chk_time : chk_sig_type := -1 ;
signal chk_st_phys1 : chk_sig_type := -1 ;
signal chk_real : chk_sig_type := -1 ;
signal chk_st_real1 : chk_sig_type := -1 ;
signal chk_st_rec1 : chk_sig_type := -1 ;
signal chk_st_rec2 : chk_sig_type := -1 ;
signal chk_st_rec3 : chk_sig_type := -1 ;
signal chk_st_arr1 : chk_sig_type := -1 ;
signal chk_st_arr2 : chk_sig_type := -1 ;
signal chk_st_arr3 : chk_sig_type := -1 ;
--
end ENT00134 ;
--
architecture ARCH00134 of ENT00134 is
begin
P1 :
process
variable correct : boolean ;
variable counter : integer := 0 ;
variable savtime : time ;
begin
case counter is
when 0
=> s_boolean <=
c_boolean_2 after 10 ns,
c_boolean_1 after 20 ns ;
--
when 1
=> correct :=
s_boolean = c_boolean_2 and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_boolean = c_boolean_1 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00134.P1" ,
"Multi inertial transactions occurred on signal " &
"asg with simple name on LHS",
correct ) ;
s_boolean <=
c_boolean_2 after 10 ns ,
c_boolean_1 after 20 ns ,
c_boolean_2 after 30 ns ,
c_boolean_1 after 40 ns ;
--
when 3
=> correct :=
s_boolean = c_boolean_2 and
(savtime + 10 ns) = Std.Standard.Now ;
s_boolean <= c_boolean_1 after 5 ns ;
--
when 4
=> correct :=
correct and
s_boolean = c_boolean_1 and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00134" ,
"One inertial transaction occurred on signal " &
"asg with simple name on LHS",
correct ) ;
s_boolean <= transport
c_boolean_1 after 100 ns ;
--
when 5
=> correct :=
s_boolean = c_boolean_1 and
(savtime + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00134" ,
"Old transactions were removed on signal " &
"asg with simple name on LHS",
correct ) ;
s_boolean <=
c_boolean_2 after 10 ns ,
c_boolean_1 after 20 ns ,
c_boolean_2 after 30 ns ,
c_boolean_1 after 40 ns ;
--
when 6
=> correct :=
s_boolean = c_boolean_2 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00134" ,
"One inertial transaction occurred on signal " &
"asg with simple name on LHS",
correct ) ;
s_boolean <= -- Last transaction above is marked
c_boolean_1 after 40 ns ;
--
when 7
=> correct :=
s_boolean = c_boolean_1 and
(savtime + 30 ns) = Std.Standard.Now ;
--
--
when 8
=> correct := correct and
s_boolean = c_boolean_1 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00134" ,
"Inertial semantics check on a signal " &
"asg with simple name on LHS",
correct ) ;
--
when others
=>
test_report ( "ARCH00134" ,
"Inertial semantics check on a signal " &
"asg with simple name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_boolean <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
wait until (not s_boolean'Quiet) and
(savtime /= Std.Standard.Now) ;
--
end process P1 ;
--
PGEN_CHKP_1 :
process ( chk_boolean )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P1" ,
"Inertial transactions entirely completed",
chk_boolean = 8 ) ;
end if ;
end process PGEN_CHKP_1 ;
--
P2 :
process
variable correct : boolean ;
variable counter : integer := 0 ;
variable savtime : time ;
begin
case counter is
when 0
=> s_bit <=
c_bit_2 after 10 ns,
c_bit_1 after 20 ns ;
--
when 1
=> correct :=
s_bit = c_bit_2 and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_bit = c_bit_1 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00134.P2" ,
"Multi inertial transactions occurred on signal " &
"asg with simple name on LHS",
correct ) ;
s_bit <=
c_bit_2 after 10 ns ,
c_bit_1 after 20 ns ,
c_bit_2 after 30 ns ,
c_bit_1 after 40 ns ;
--
when 3
=> correct :=
s_bit = c_bit_2 and
(savtime + 10 ns) = Std.Standard.Now ;
s_bit <= c_bit_1 after 5 ns ;
--
when 4
=> correct :=
correct and
s_bit = c_bit_1 and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00134" ,
"One inertial transaction occurred on signal " &
"asg with simple name on LHS",
correct ) ;
s_bit <= transport
c_bit_1 after 100 ns ;
--
when 5
=> correct :=
s_bit = c_bit_1 and
(savtime + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00134" ,
"Old transactions were removed on signal " &
"asg with simple name on LHS",
correct ) ;
s_bit <=
c_bit_2 after 10 ns ,
c_bit_1 after 20 ns ,
c_bit_2 after 30 ns ,
c_bit_1 after 40 ns ;
--
when 6
=> correct :=
s_bit = c_bit_2 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00134" ,
"One inertial transaction occurred on signal " &
"asg with simple name on LHS",
correct ) ;
s_bit <= -- Last transaction above is marked
c_bit_1 after 40 ns ;
--
when 7
=> correct :=
s_bit = c_bit_1 and
(savtime + 30 ns) = Std.Standard.Now ;
--
--
when 8
=> correct := correct and
s_bit = c_bit_1 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00134" ,
"Inertial semantics check on a signal " &
"asg with simple name on LHS",
correct ) ;
--
when others
=>
test_report ( "ARCH00134" ,
"Inertial semantics check on a signal " &
"asg with simple name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_bit <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
wait until (not s_bit'Quiet) and
(savtime /= Std.Standard.Now) ;
--
end process P2 ;
--
PGEN_CHKP_2 :
process ( chk_bit )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P2" ,
"Inertial transactions entirely completed",
chk_bit = 8 ) ;
end if ;
end process PGEN_CHKP_2 ;
--
P3 :
process
variable correct : boolean ;
variable counter : integer := 0 ;
variable savtime : time ;
begin
case counter is
when 0
=> s_severity_level <=
c_severity_level_2 after 10 ns,
c_severity_level_1 after 20 ns ;
--
when 1
=> correct :=
s_severity_level = c_severity_level_2 and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_severity_level = c_severity_level_1 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00134.P3" ,
"Multi inertial transactions occurred on signal " &
"asg with simple name on LHS",
correct ) ;
s_severity_level <=
c_severity_level_2 after 10 ns ,
c_severity_level_1 after 20 ns ,
c_severity_level_2 after 30 ns ,
c_severity_level_1 after 40 ns ;
--
when 3
=> correct :=
s_severity_level = c_severity_level_2 and
(savtime + 10 ns) = Std.Standard.Now ;
s_severity_level <= c_severity_level_1 after 5 ns ;
--
when 4
=> correct :=
correct and
s_severity_level = c_severity_level_1 and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00134" ,
"One inertial transaction occurred on signal " &
"asg with simple name on LHS",
correct ) ;
s_severity_level <= transport
c_severity_level_1 after 100 ns ;
--
when 5
=> correct :=
s_severity_level = c_severity_level_1 and
(savtime + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00134" ,
"Old transactions were removed on signal " &
"asg with simple name on LHS",
correct ) ;
s_severity_level <=
c_severity_level_2 after 10 ns ,
c_severity_level_1 after 20 ns ,
c_severity_level_2 after 30 ns ,
c_severity_level_1 after 40 ns ;
--
when 6
=> correct :=
s_severity_level = c_severity_level_2 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00134" ,
"One inertial transaction occurred on signal " &
"asg with simple name on LHS",
correct ) ;
s_severity_level <= -- Last transaction above is marked
c_severity_level_1 after 40 ns ;
--
when 7
=> correct :=
s_severity_level = c_severity_level_1 and
(savtime + 30 ns) = Std.Standard.Now ;
--
--
when 8
=> correct := correct and
s_severity_level = c_severity_level_1 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00134" ,
"Inertial semantics check on a signal " &
"asg with simple name on LHS",
correct ) ;
--
when others
=>
test_report ( "ARCH00134" ,
"Inertial semantics check on a signal " &
"asg with simple name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_severity_level <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
wait until (not s_severity_level'Quiet) and
(savtime /= Std.Standard.Now) ;
--
end process P3 ;
--
PGEN_CHKP_3 :
process ( chk_severity_level )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P3" ,
"Inertial transactions entirely completed",
chk_severity_level = 8 ) ;
end if ;
end process PGEN_CHKP_3 ;
--
P4 :
process
variable correct : boolean ;
variable counter : integer := 0 ;
variable savtime : time ;
begin
case counter is
when 0
=> s_character <=
c_character_2 after 10 ns,
c_character_1 after 20 ns ;
--
when 1
=> correct :=
s_character = c_character_2 and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_character = c_character_1 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00134.P4" ,
"Multi inertial transactions occurred on signal " &
"asg with simple name on LHS",
correct ) ;
s_character <=
c_character_2 after 10 ns ,
c_character_1 after 20 ns ,
c_character_2 after 30 ns ,
c_character_1 after 40 ns ;
--
when 3
=> correct :=
s_character = c_character_2 and
(savtime + 10 ns) = Std.Standard.Now ;
s_character <= c_character_1 after 5 ns ;
--
when 4
=> correct :=
correct and
s_character = c_character_1 and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00134" ,
"One inertial transaction occurred on signal " &
"asg with simple name on LHS",
correct ) ;
s_character <= transport
c_character_1 after 100 ns ;
--
when 5
=> correct :=
s_character = c_character_1 and
(savtime + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00134" ,
"Old transactions were removed on signal " &
"asg with simple name on LHS",
correct ) ;
s_character <=
c_character_2 after 10 ns ,
c_character_1 after 20 ns ,
c_character_2 after 30 ns ,
c_character_1 after 40 ns ;
--
when 6
=> correct :=
s_character = c_character_2 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00134" ,
"One inertial transaction occurred on signal " &
"asg with simple name on LHS",
correct ) ;
s_character <= -- Last transaction above is marked
c_character_1 after 40 ns ;
--
when 7
=> correct :=
s_character = c_character_1 and
(savtime + 30 ns) = Std.Standard.Now ;
--
--
when 8
=> correct := correct and
s_character = c_character_1 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00134" ,
"Inertial semantics check on a signal " &
"asg with simple name on LHS",
correct ) ;
--
when others
=>
test_report ( "ARCH00134" ,
"Inertial semantics check on a signal " &
"asg with simple name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_character <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
wait until (not s_character'Quiet) and
(savtime /= Std.Standard.Now) ;
--
end process P4 ;
--
PGEN_CHKP_4 :
process ( chk_character )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P4" ,
"Inertial transactions entirely completed",
chk_character = 8 ) ;
end if ;
end process PGEN_CHKP_4 ;
--
P5 :
process
variable correct : boolean ;
variable counter : integer := 0 ;
variable savtime : time ;
begin
case counter is
when 0
=> s_st_enum1 <=
c_st_enum1_2 after 10 ns,
c_st_enum1_1 after 20 ns ;
--
when 1
=> correct :=
s_st_enum1 = c_st_enum1_2 and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_enum1 = c_st_enum1_1 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00134.P5" ,
"Multi inertial transactions occurred on signal " &
"asg with simple name on LHS",
correct ) ;
s_st_enum1 <=
c_st_enum1_2 after 10 ns ,
c_st_enum1_1 after 20 ns ,
c_st_enum1_2 after 30 ns ,
c_st_enum1_1 after 40 ns ;
--
when 3
=> correct :=
s_st_enum1 = c_st_enum1_2 and
(savtime + 10 ns) = Std.Standard.Now ;
s_st_enum1 <= c_st_enum1_1 after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_enum1 = c_st_enum1_1 and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00134" ,
"One inertial transaction occurred on signal " &
"asg with simple name on LHS",
correct ) ;
s_st_enum1 <= transport
c_st_enum1_1 after 100 ns ;
--
when 5
=> correct :=
s_st_enum1 = c_st_enum1_1 and
(savtime + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00134" ,
"Old transactions were removed on signal " &
"asg with simple name on LHS",
correct ) ;
s_st_enum1 <=
c_st_enum1_2 after 10 ns ,
c_st_enum1_1 after 20 ns ,
c_st_enum1_2 after 30 ns ,
c_st_enum1_1 after 40 ns ;
--
when 6
=> correct :=
s_st_enum1 = c_st_enum1_2 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00134" ,
"One inertial transaction occurred on signal " &
"asg with simple name on LHS",
correct ) ;
s_st_enum1 <= -- Last transaction above is marked
c_st_enum1_1 after 40 ns ;
--
when 7
=> correct :=
s_st_enum1 = c_st_enum1_1 and
(savtime + 30 ns) = Std.Standard.Now ;
--
--
when 8
=> correct := correct and
s_st_enum1 = c_st_enum1_1 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00134" ,
"Inertial semantics check on a signal " &
"asg with simple name on LHS",
correct ) ;
--
when others
=>
test_report ( "ARCH00134" ,
"Inertial semantics check on a signal " &
"asg with simple name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_st_enum1 <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
wait until (not s_st_enum1'Quiet) and
(savtime /= Std.Standard.Now) ;
--
end process P5 ;
--
PGEN_CHKP_5 :
process ( chk_st_enum1 )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P5" ,
"Inertial transactions entirely completed",
chk_st_enum1 = 8 ) ;
end if ;
end process PGEN_CHKP_5 ;
--
P6 :
process
variable correct : boolean ;
variable counter : integer := 0 ;
variable savtime : time ;
begin
case counter is
when 0
=> s_integer <=
c_integer_2 after 10 ns,
c_integer_1 after 20 ns ;
--
when 1
=> correct :=
s_integer = c_integer_2 and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_integer = c_integer_1 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00134.P6" ,
"Multi inertial transactions occurred on signal " &
"asg with simple name on LHS",
correct ) ;
s_integer <=
c_integer_2 after 10 ns ,
c_integer_1 after 20 ns ,
c_integer_2 after 30 ns ,
c_integer_1 after 40 ns ;
--
when 3
=> correct :=
s_integer = c_integer_2 and
(savtime + 10 ns) = Std.Standard.Now ;
s_integer <= c_integer_1 after 5 ns ;
--
when 4
=> correct :=
correct and
s_integer = c_integer_1 and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00134" ,
"One inertial transaction occurred on signal " &
"asg with simple name on LHS",
correct ) ;
s_integer <= transport
c_integer_1 after 100 ns ;
--
when 5
=> correct :=
s_integer = c_integer_1 and
(savtime + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00134" ,
"Old transactions were removed on signal " &
"asg with simple name on LHS",
correct ) ;
s_integer <=
c_integer_2 after 10 ns ,
c_integer_1 after 20 ns ,
c_integer_2 after 30 ns ,
c_integer_1 after 40 ns ;
--
when 6
=> correct :=
s_integer = c_integer_2 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00134" ,
"One inertial transaction occurred on signal " &
"asg with simple name on LHS",
correct ) ;
s_integer <= -- Last transaction above is marked
c_integer_1 after 40 ns ;
--
when 7
=> correct :=
s_integer = c_integer_1 and
(savtime + 30 ns) = Std.Standard.Now ;
--
--
when 8
=> correct := correct and
s_integer = c_integer_1 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00134" ,
"Inertial semantics check on a signal " &
"asg with simple name on LHS",
correct ) ;
--
when others
=>
test_report ( "ARCH00134" ,
"Inertial semantics check on a signal " &
"asg with simple name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_integer <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
wait until (not s_integer'Quiet) and
(savtime /= Std.Standard.Now) ;
--
end process P6 ;
--
PGEN_CHKP_6 :
process ( chk_integer )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P6" ,
"Inertial transactions entirely completed",
chk_integer = 8 ) ;
end if ;
end process PGEN_CHKP_6 ;
--
P7 :
process
variable correct : boolean ;
variable counter : integer := 0 ;
variable savtime : time ;
begin
case counter is
when 0
=> s_st_int1 <=
c_st_int1_2 after 10 ns,
c_st_int1_1 after 20 ns ;
--
when 1
=> correct :=
s_st_int1 = c_st_int1_2 and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_int1 = c_st_int1_1 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00134.P7" ,
"Multi inertial transactions occurred on signal " &
"asg with simple name on LHS",
correct ) ;
s_st_int1 <=
c_st_int1_2 after 10 ns ,
c_st_int1_1 after 20 ns ,
c_st_int1_2 after 30 ns ,
c_st_int1_1 after 40 ns ;
--
when 3
=> correct :=
s_st_int1 = c_st_int1_2 and
(savtime + 10 ns) = Std.Standard.Now ;
s_st_int1 <= c_st_int1_1 after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_int1 = c_st_int1_1 and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00134" ,
"One inertial transaction occurred on signal " &
"asg with simple name on LHS",
correct ) ;
s_st_int1 <= transport
c_st_int1_1 after 100 ns ;
--
when 5
=> correct :=
s_st_int1 = c_st_int1_1 and
(savtime + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00134" ,
"Old transactions were removed on signal " &
"asg with simple name on LHS",
correct ) ;
s_st_int1 <=
c_st_int1_2 after 10 ns ,
c_st_int1_1 after 20 ns ,
c_st_int1_2 after 30 ns ,
c_st_int1_1 after 40 ns ;
--
when 6
=> correct :=
s_st_int1 = c_st_int1_2 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00134" ,
"One inertial transaction occurred on signal " &
"asg with simple name on LHS",
correct ) ;
s_st_int1 <= -- Last transaction above is marked
c_st_int1_1 after 40 ns ;
--
when 7
=> correct :=
s_st_int1 = c_st_int1_1 and
(savtime + 30 ns) = Std.Standard.Now ;
--
--
when 8
=> correct := correct and
s_st_int1 = c_st_int1_1 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00134" ,
"Inertial semantics check on a signal " &
"asg with simple name on LHS",
correct ) ;
--
when others
=>
test_report ( "ARCH00134" ,
"Inertial semantics check on a signal " &
"asg with simple name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_st_int1 <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
wait until (not s_st_int1'Quiet) and
(savtime /= Std.Standard.Now) ;
--
end process P7 ;
--
PGEN_CHKP_7 :
process ( chk_st_int1 )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P7" ,
"Inertial transactions entirely completed",
chk_st_int1 = 8 ) ;
end if ;
end process PGEN_CHKP_7 ;
--
P8 :
process
variable correct : boolean ;
variable counter : integer := 0 ;
variable savtime : time ;
begin
case counter is
when 0
=> s_time <=
c_time_2 after 10 ns,
c_time_1 after 20 ns ;
--
when 1
=> correct :=
s_time = c_time_2 and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_time = c_time_1 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00134.P8" ,
"Multi inertial transactions occurred on signal " &
"asg with simple name on LHS",
correct ) ;
s_time <=
c_time_2 after 10 ns ,
c_time_1 after 20 ns ,
c_time_2 after 30 ns ,
c_time_1 after 40 ns ;
--
when 3
=> correct :=
s_time = c_time_2 and
(savtime + 10 ns) = Std.Standard.Now ;
s_time <= c_time_1 after 5 ns ;
--
when 4
=> correct :=
correct and
s_time = c_time_1 and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00134" ,
"One inertial transaction occurred on signal " &
"asg with simple name on LHS",
correct ) ;
s_time <= transport
c_time_1 after 100 ns ;
--
when 5
=> correct :=
s_time = c_time_1 and
(savtime + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00134" ,
"Old transactions were removed on signal " &
"asg with simple name on LHS",
correct ) ;
s_time <=
c_time_2 after 10 ns ,
c_time_1 after 20 ns ,
c_time_2 after 30 ns ,
c_time_1 after 40 ns ;
--
when 6
=> correct :=
s_time = c_time_2 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00134" ,
"One inertial transaction occurred on signal " &
"asg with simple name on LHS",
correct ) ;
s_time <= -- Last transaction above is marked
c_time_1 after 40 ns ;
--
when 7
=> correct :=
s_time = c_time_1 and
(savtime + 30 ns) = Std.Standard.Now ;
--
--
when 8
=> correct := correct and
s_time = c_time_1 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00134" ,
"Inertial semantics check on a signal " &
"asg with simple name on LHS",
correct ) ;
--
when others
=>
test_report ( "ARCH00134" ,
"Inertial semantics check on a signal " &
"asg with simple name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_time <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
wait until (not s_time'Quiet) and
(savtime /= Std.Standard.Now) ;
--
end process P8 ;
--
PGEN_CHKP_8 :
process ( chk_time )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P8" ,
"Inertial transactions entirely completed",
chk_time = 8 ) ;
end if ;
end process PGEN_CHKP_8 ;
--
P9 :
process
variable correct : boolean ;
variable counter : integer := 0 ;
variable savtime : time ;
begin
case counter is
when 0
=> s_st_phys1 <=
c_st_phys1_2 after 10 ns,
c_st_phys1_1 after 20 ns ;
--
when 1
=> correct :=
s_st_phys1 = c_st_phys1_2 and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_phys1 = c_st_phys1_1 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00134.P9" ,
"Multi inertial transactions occurred on signal " &
"asg with simple name on LHS",
correct ) ;
s_st_phys1 <=
c_st_phys1_2 after 10 ns ,
c_st_phys1_1 after 20 ns ,
c_st_phys1_2 after 30 ns ,
c_st_phys1_1 after 40 ns ;
--
when 3
=> correct :=
s_st_phys1 = c_st_phys1_2 and
(savtime + 10 ns) = Std.Standard.Now ;
s_st_phys1 <= c_st_phys1_1 after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_phys1 = c_st_phys1_1 and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00134" ,
"One inertial transaction occurred on signal " &
"asg with simple name on LHS",
correct ) ;
s_st_phys1 <= transport
c_st_phys1_1 after 100 ns ;
--
when 5
=> correct :=
s_st_phys1 = c_st_phys1_1 and
(savtime + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00134" ,
"Old transactions were removed on signal " &
"asg with simple name on LHS",
correct ) ;
s_st_phys1 <=
c_st_phys1_2 after 10 ns ,
c_st_phys1_1 after 20 ns ,
c_st_phys1_2 after 30 ns ,
c_st_phys1_1 after 40 ns ;
--
when 6
=> correct :=
s_st_phys1 = c_st_phys1_2 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00134" ,
"One inertial transaction occurred on signal " &
"asg with simple name on LHS",
correct ) ;
s_st_phys1 <= -- Last transaction above is marked
c_st_phys1_1 after 40 ns ;
--
when 7
=> correct :=
s_st_phys1 = c_st_phys1_1 and
(savtime + 30 ns) = Std.Standard.Now ;
--
--
when 8
=> correct := correct and
s_st_phys1 = c_st_phys1_1 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00134" ,
"Inertial semantics check on a signal " &
"asg with simple name on LHS",
correct ) ;
--
when others
=>
test_report ( "ARCH00134" ,
"Inertial semantics check on a signal " &
"asg with simple name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_st_phys1 <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
wait until (not s_st_phys1'Quiet) and
(savtime /= Std.Standard.Now) ;
--
end process P9 ;
--
PGEN_CHKP_9 :
process ( chk_st_phys1 )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P9" ,
"Inertial transactions entirely completed",
chk_st_phys1 = 8 ) ;
end if ;
end process PGEN_CHKP_9 ;
--
P10 :
process
variable correct : boolean ;
variable counter : integer := 0 ;
variable savtime : time ;
begin
case counter is
when 0
=> s_real <=
c_real_2 after 10 ns,
c_real_1 after 20 ns ;
--
when 1
=> correct :=
s_real = c_real_2 and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_real = c_real_1 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00134.P10" ,
"Multi inertial transactions occurred on signal " &
"asg with simple name on LHS",
correct ) ;
s_real <=
c_real_2 after 10 ns ,
c_real_1 after 20 ns ,
c_real_2 after 30 ns ,
c_real_1 after 40 ns ;
--
when 3
=> correct :=
s_real = c_real_2 and
(savtime + 10 ns) = Std.Standard.Now ;
s_real <= c_real_1 after 5 ns ;
--
when 4
=> correct :=
correct and
s_real = c_real_1 and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00134" ,
"One inertial transaction occurred on signal " &
"asg with simple name on LHS",
correct ) ;
s_real <= transport
c_real_1 after 100 ns ;
--
when 5
=> correct :=
s_real = c_real_1 and
(savtime + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00134" ,
"Old transactions were removed on signal " &
"asg with simple name on LHS",
correct ) ;
s_real <=
c_real_2 after 10 ns ,
c_real_1 after 20 ns ,
c_real_2 after 30 ns ,
c_real_1 after 40 ns ;
--
when 6
=> correct :=
s_real = c_real_2 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00134" ,
"One inertial transaction occurred on signal " &
"asg with simple name on LHS",
correct ) ;
s_real <= -- Last transaction above is marked
c_real_1 after 40 ns ;
--
when 7
=> correct :=
s_real = c_real_1 and
(savtime + 30 ns) = Std.Standard.Now ;
--
--
when 8
=> correct := correct and
s_real = c_real_1 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00134" ,
"Inertial semantics check on a signal " &
"asg with simple name on LHS",
correct ) ;
--
when others
=>
test_report ( "ARCH00134" ,
"Inertial semantics check on a signal " &
"asg with simple name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_real <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
wait until (not s_real'Quiet) and
(savtime /= Std.Standard.Now) ;
--
end process P10 ;
--
PGEN_CHKP_10 :
process ( chk_real )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P10" ,
"Inertial transactions entirely completed",
chk_real = 8 ) ;
end if ;
end process PGEN_CHKP_10 ;
--
P11 :
process
variable correct : boolean ;
variable counter : integer := 0 ;
variable savtime : time ;
begin
case counter is
when 0
=> s_st_real1 <=
c_st_real1_2 after 10 ns,
c_st_real1_1 after 20 ns ;
--
when 1
=> correct :=
s_st_real1 = c_st_real1_2 and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_real1 = c_st_real1_1 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00134.P11" ,
"Multi inertial transactions occurred on signal " &
"asg with simple name on LHS",
correct ) ;
s_st_real1 <=
c_st_real1_2 after 10 ns ,
c_st_real1_1 after 20 ns ,
c_st_real1_2 after 30 ns ,
c_st_real1_1 after 40 ns ;
--
when 3
=> correct :=
s_st_real1 = c_st_real1_2 and
(savtime + 10 ns) = Std.Standard.Now ;
s_st_real1 <= c_st_real1_1 after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_real1 = c_st_real1_1 and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00134" ,
"One inertial transaction occurred on signal " &
"asg with simple name on LHS",
correct ) ;
s_st_real1 <= transport
c_st_real1_1 after 100 ns ;
--
when 5
=> correct :=
s_st_real1 = c_st_real1_1 and
(savtime + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00134" ,
"Old transactions were removed on signal " &
"asg with simple name on LHS",
correct ) ;
s_st_real1 <=
c_st_real1_2 after 10 ns ,
c_st_real1_1 after 20 ns ,
c_st_real1_2 after 30 ns ,
c_st_real1_1 after 40 ns ;
--
when 6
=> correct :=
s_st_real1 = c_st_real1_2 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00134" ,
"One inertial transaction occurred on signal " &
"asg with simple name on LHS",
correct ) ;
s_st_real1 <= -- Last transaction above is marked
c_st_real1_1 after 40 ns ;
--
when 7
=> correct :=
s_st_real1 = c_st_real1_1 and
(savtime + 30 ns) = Std.Standard.Now ;
--
--
when 8
=> correct := correct and
s_st_real1 = c_st_real1_1 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00134" ,
"Inertial semantics check on a signal " &
"asg with simple name on LHS",
correct ) ;
--
when others
=>
test_report ( "ARCH00134" ,
"Inertial semantics check on a signal " &
"asg with simple name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_st_real1 <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
wait until (not s_st_real1'Quiet) and
(savtime /= Std.Standard.Now) ;
--
end process P11 ;
--
PGEN_CHKP_11 :
process ( chk_st_real1 )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P11" ,
"Inertial transactions entirely completed",
chk_st_real1 = 8 ) ;
end if ;
end process PGEN_CHKP_11 ;
--
P12 :
process
variable correct : boolean ;
variable counter : integer := 0 ;
variable savtime : time ;
begin
case counter is
when 0
=> s_st_rec1 <=
c_st_rec1_2 after 10 ns,
c_st_rec1_1 after 20 ns ;
--
when 1
=> correct :=
s_st_rec1 = c_st_rec1_2 and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_rec1 = c_st_rec1_1 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00134.P12" ,
"Multi inertial transactions occurred on signal " &
"asg with simple name on LHS",
correct ) ;
s_st_rec1 <=
c_st_rec1_2 after 10 ns ,
c_st_rec1_1 after 20 ns ,
c_st_rec1_2 after 30 ns ,
c_st_rec1_1 after 40 ns ;
--
when 3
=> correct :=
s_st_rec1 = c_st_rec1_2 and
(savtime + 10 ns) = Std.Standard.Now ;
s_st_rec1 <= c_st_rec1_1 after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_rec1 = c_st_rec1_1 and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00134" ,
"One inertial transaction occurred on signal " &
"asg with simple name on LHS",
correct ) ;
s_st_rec1 <= transport
c_st_rec1_1 after 100 ns ;
--
when 5
=> correct :=
s_st_rec1 = c_st_rec1_1 and
(savtime + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00134" ,
"Old transactions were removed on signal " &
"asg with simple name on LHS",
correct ) ;
s_st_rec1 <=
c_st_rec1_2 after 10 ns ,
c_st_rec1_1 after 20 ns ,
c_st_rec1_2 after 30 ns ,
c_st_rec1_1 after 40 ns ;
--
when 6
=> correct :=
s_st_rec1 = c_st_rec1_2 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00134" ,
"One inertial transaction occurred on signal " &
"asg with simple name on LHS",
correct ) ;
s_st_rec1 <= -- Last transaction above is marked
c_st_rec1_1 after 40 ns ;
--
when 7
=> correct :=
s_st_rec1 = c_st_rec1_1 and
(savtime + 30 ns) = Std.Standard.Now ;
--
--
when 8
=> correct := correct and
s_st_rec1 = c_st_rec1_1 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00134" ,
"Inertial semantics check on a signal " &
"asg with simple name on LHS",
correct ) ;
--
when others
=>
test_report ( "ARCH00134" ,
"Inertial semantics check on a signal " &
"asg with simple name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_st_rec1 <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
wait until (not s_st_rec1'Quiet) and
(savtime /= Std.Standard.Now) ;
--
end process P12 ;
--
PGEN_CHKP_12 :
process ( chk_st_rec1 )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P12" ,
"Inertial transactions entirely completed",
chk_st_rec1 = 8 ) ;
end if ;
end process PGEN_CHKP_12 ;
--
P13 :
process
variable correct : boolean ;
variable counter : integer := 0 ;
variable savtime : time ;
begin
case counter is
when 0
=> s_st_rec2 <=
c_st_rec2_2 after 10 ns,
c_st_rec2_1 after 20 ns ;
--
when 1
=> correct :=
s_st_rec2 = c_st_rec2_2 and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_rec2 = c_st_rec2_1 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00134.P13" ,
"Multi inertial transactions occurred on signal " &
"asg with simple name on LHS",
correct ) ;
s_st_rec2 <=
c_st_rec2_2 after 10 ns ,
c_st_rec2_1 after 20 ns ,
c_st_rec2_2 after 30 ns ,
c_st_rec2_1 after 40 ns ;
--
when 3
=> correct :=
s_st_rec2 = c_st_rec2_2 and
(savtime + 10 ns) = Std.Standard.Now ;
s_st_rec2 <= c_st_rec2_1 after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_rec2 = c_st_rec2_1 and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00134" ,
"One inertial transaction occurred on signal " &
"asg with simple name on LHS",
correct ) ;
s_st_rec2 <= transport
c_st_rec2_1 after 100 ns ;
--
when 5
=> correct :=
s_st_rec2 = c_st_rec2_1 and
(savtime + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00134" ,
"Old transactions were removed on signal " &
"asg with simple name on LHS",
correct ) ;
s_st_rec2 <=
c_st_rec2_2 after 10 ns ,
c_st_rec2_1 after 20 ns ,
c_st_rec2_2 after 30 ns ,
c_st_rec2_1 after 40 ns ;
--
when 6
=> correct :=
s_st_rec2 = c_st_rec2_2 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00134" ,
"One inertial transaction occurred on signal " &
"asg with simple name on LHS",
correct ) ;
s_st_rec2 <= -- Last transaction above is marked
c_st_rec2_1 after 40 ns ;
--
when 7
=> correct :=
s_st_rec2 = c_st_rec2_1 and
(savtime + 30 ns) = Std.Standard.Now ;
--
--
when 8
=> correct := correct and
s_st_rec2 = c_st_rec2_1 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00134" ,
"Inertial semantics check on a signal " &
"asg with simple name on LHS",
correct ) ;
--
when others
=>
test_report ( "ARCH00134" ,
"Inertial semantics check on a signal " &
"asg with simple name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_st_rec2 <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
wait until (not s_st_rec2'Quiet) and
(savtime /= Std.Standard.Now) ;
--
end process P13 ;
--
PGEN_CHKP_13 :
process ( chk_st_rec2 )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P13" ,
"Inertial transactions entirely completed",
chk_st_rec2 = 8 ) ;
end if ;
end process PGEN_CHKP_13 ;
--
P14 :
process
variable correct : boolean ;
variable counter : integer := 0 ;
variable savtime : time ;
begin
case counter is
when 0
=> s_st_rec3 <=
c_st_rec3_2 after 10 ns,
c_st_rec3_1 after 20 ns ;
--
when 1
=> correct :=
s_st_rec3 = c_st_rec3_2 and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_rec3 = c_st_rec3_1 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00134.P14" ,
"Multi inertial transactions occurred on signal " &
"asg with simple name on LHS",
correct ) ;
s_st_rec3 <=
c_st_rec3_2 after 10 ns ,
c_st_rec3_1 after 20 ns ,
c_st_rec3_2 after 30 ns ,
c_st_rec3_1 after 40 ns ;
--
when 3
=> correct :=
s_st_rec3 = c_st_rec3_2 and
(savtime + 10 ns) = Std.Standard.Now ;
s_st_rec3 <= c_st_rec3_1 after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_rec3 = c_st_rec3_1 and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00134" ,
"One inertial transaction occurred on signal " &
"asg with simple name on LHS",
correct ) ;
s_st_rec3 <= transport
c_st_rec3_1 after 100 ns ;
--
when 5
=> correct :=
s_st_rec3 = c_st_rec3_1 and
(savtime + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00134" ,
"Old transactions were removed on signal " &
"asg with simple name on LHS",
correct ) ;
s_st_rec3 <=
c_st_rec3_2 after 10 ns ,
c_st_rec3_1 after 20 ns ,
c_st_rec3_2 after 30 ns ,
c_st_rec3_1 after 40 ns ;
--
when 6
=> correct :=
s_st_rec3 = c_st_rec3_2 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00134" ,
"One inertial transaction occurred on signal " &
"asg with simple name on LHS",
correct ) ;
s_st_rec3 <= -- Last transaction above is marked
c_st_rec3_1 after 40 ns ;
--
when 7
=> correct :=
s_st_rec3 = c_st_rec3_1 and
(savtime + 30 ns) = Std.Standard.Now ;
--
--
when 8
=> correct := correct and
s_st_rec3 = c_st_rec3_1 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00134" ,
"Inertial semantics check on a signal " &
"asg with simple name on LHS",
correct ) ;
--
when others
=>
test_report ( "ARCH00134" ,
"Inertial semantics check on a signal " &
"asg with simple name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_st_rec3 <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
wait until (not s_st_rec3'Quiet) and
(savtime /= Std.Standard.Now) ;
--
end process P14 ;
--
PGEN_CHKP_14 :
process ( chk_st_rec3 )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P14" ,
"Inertial transactions entirely completed",
chk_st_rec3 = 8 ) ;
end if ;
end process PGEN_CHKP_14 ;
--
P15 :
process
variable correct : boolean ;
variable counter : integer := 0 ;
variable savtime : time ;
begin
case counter is
when 0
=> s_st_arr1 <=
c_st_arr1_2 after 10 ns,
c_st_arr1_1 after 20 ns ;
--
when 1
=> correct :=
s_st_arr1 = c_st_arr1_2 and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_arr1 = c_st_arr1_1 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00134.P15" ,
"Multi inertial transactions occurred on signal " &
"asg with simple name on LHS",
correct ) ;
s_st_arr1 <=
c_st_arr1_2 after 10 ns ,
c_st_arr1_1 after 20 ns ,
c_st_arr1_2 after 30 ns ,
c_st_arr1_1 after 40 ns ;
--
when 3
=> correct :=
s_st_arr1 = c_st_arr1_2 and
(savtime + 10 ns) = Std.Standard.Now ;
s_st_arr1 <= c_st_arr1_1 after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_arr1 = c_st_arr1_1 and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00134" ,
"One inertial transaction occurred on signal " &
"asg with simple name on LHS",
correct ) ;
s_st_arr1 <= transport
c_st_arr1_1 after 100 ns ;
--
when 5
=> correct :=
s_st_arr1 = c_st_arr1_1 and
(savtime + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00134" ,
"Old transactions were removed on signal " &
"asg with simple name on LHS",
correct ) ;
s_st_arr1 <=
c_st_arr1_2 after 10 ns ,
c_st_arr1_1 after 20 ns ,
c_st_arr1_2 after 30 ns ,
c_st_arr1_1 after 40 ns ;
--
when 6
=> correct :=
s_st_arr1 = c_st_arr1_2 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00134" ,
"One inertial transaction occurred on signal " &
"asg with simple name on LHS",
correct ) ;
s_st_arr1 <= -- Last transaction above is marked
c_st_arr1_1 after 40 ns ;
--
when 7
=> correct :=
s_st_arr1 = c_st_arr1_1 and
(savtime + 30 ns) = Std.Standard.Now ;
--
--
when 8
=> correct := correct and
s_st_arr1 = c_st_arr1_1 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00134" ,
"Inertial semantics check on a signal " &
"asg with simple name on LHS",
correct ) ;
--
when others
=>
test_report ( "ARCH00134" ,
"Inertial semantics check on a signal " &
"asg with simple name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_st_arr1 <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
wait until (not s_st_arr1'Quiet) and
(savtime /= Std.Standard.Now) ;
--
end process P15 ;
--
PGEN_CHKP_15 :
process ( chk_st_arr1 )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P15" ,
"Inertial transactions entirely completed",
chk_st_arr1 = 8 ) ;
end if ;
end process PGEN_CHKP_15 ;
--
P16 :
process
variable correct : boolean ;
variable counter : integer := 0 ;
variable savtime : time ;
begin
case counter is
when 0
=> s_st_arr2 <=
c_st_arr2_2 after 10 ns,
c_st_arr2_1 after 20 ns ;
--
when 1
=> correct :=
s_st_arr2 = c_st_arr2_2 and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_arr2 = c_st_arr2_1 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00134.P16" ,
"Multi inertial transactions occurred on signal " &
"asg with simple name on LHS",
correct ) ;
s_st_arr2 <=
c_st_arr2_2 after 10 ns ,
c_st_arr2_1 after 20 ns ,
c_st_arr2_2 after 30 ns ,
c_st_arr2_1 after 40 ns ;
--
when 3
=> correct :=
s_st_arr2 = c_st_arr2_2 and
(savtime + 10 ns) = Std.Standard.Now ;
s_st_arr2 <= c_st_arr2_1 after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_arr2 = c_st_arr2_1 and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00134" ,
"One inertial transaction occurred on signal " &
"asg with simple name on LHS",
correct ) ;
s_st_arr2 <= transport
c_st_arr2_1 after 100 ns ;
--
when 5
=> correct :=
s_st_arr2 = c_st_arr2_1 and
(savtime + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00134" ,
"Old transactions were removed on signal " &
"asg with simple name on LHS",
correct ) ;
s_st_arr2 <=
c_st_arr2_2 after 10 ns ,
c_st_arr2_1 after 20 ns ,
c_st_arr2_2 after 30 ns ,
c_st_arr2_1 after 40 ns ;
--
when 6
=> correct :=
s_st_arr2 = c_st_arr2_2 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00134" ,
"One inertial transaction occurred on signal " &
"asg with simple name on LHS",
correct ) ;
s_st_arr2 <= -- Last transaction above is marked
c_st_arr2_1 after 40 ns ;
--
when 7
=> correct :=
s_st_arr2 = c_st_arr2_1 and
(savtime + 30 ns) = Std.Standard.Now ;
--
--
when 8
=> correct := correct and
s_st_arr2 = c_st_arr2_1 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00134" ,
"Inertial semantics check on a signal " &
"asg with simple name on LHS",
correct ) ;
--
when others
=>
test_report ( "ARCH00134" ,
"Inertial semantics check on a signal " &
"asg with simple name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_st_arr2 <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
wait until (not s_st_arr2'Quiet) and
(savtime /= Std.Standard.Now) ;
--
end process P16 ;
--
PGEN_CHKP_16 :
process ( chk_st_arr2 )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P16" ,
"Inertial transactions entirely completed",
chk_st_arr2 = 8 ) ;
end if ;
end process PGEN_CHKP_16 ;
--
P17 :
process
variable correct : boolean ;
variable counter : integer := 0 ;
variable savtime : time ;
begin
case counter is
when 0
=> s_st_arr3 <=
c_st_arr3_2 after 10 ns,
c_st_arr3_1 after 20 ns ;
--
when 1
=> correct :=
s_st_arr3 = c_st_arr3_2 and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_arr3 = c_st_arr3_1 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00134.P17" ,
"Multi inertial transactions occurred on signal " &
"asg with simple name on LHS",
correct ) ;
s_st_arr3 <=
c_st_arr3_2 after 10 ns ,
c_st_arr3_1 after 20 ns ,
c_st_arr3_2 after 30 ns ,
c_st_arr3_1 after 40 ns ;
--
when 3
=> correct :=
s_st_arr3 = c_st_arr3_2 and
(savtime + 10 ns) = Std.Standard.Now ;
s_st_arr3 <= c_st_arr3_1 after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_arr3 = c_st_arr3_1 and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00134" ,
"One inertial transaction occurred on signal " &
"asg with simple name on LHS",
correct ) ;
s_st_arr3 <= transport
c_st_arr3_1 after 100 ns ;
--
when 5
=> correct :=
s_st_arr3 = c_st_arr3_1 and
(savtime + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00134" ,
"Old transactions were removed on signal " &
"asg with simple name on LHS",
correct ) ;
s_st_arr3 <=
c_st_arr3_2 after 10 ns ,
c_st_arr3_1 after 20 ns ,
c_st_arr3_2 after 30 ns ,
c_st_arr3_1 after 40 ns ;
--
when 6
=> correct :=
s_st_arr3 = c_st_arr3_2 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00134" ,
"One inertial transaction occurred on signal " &
"asg with simple name on LHS",
correct ) ;
s_st_arr3 <= -- Last transaction above is marked
c_st_arr3_1 after 40 ns ;
--
when 7
=> correct :=
s_st_arr3 = c_st_arr3_1 and
(savtime + 30 ns) = Std.Standard.Now ;
--
--
when 8
=> correct := correct and
s_st_arr3 = c_st_arr3_1 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00134" ,
"Inertial semantics check on a signal " &
"asg with simple name on LHS",
correct ) ;
--
when others
=>
test_report ( "ARCH00134" ,
"Inertial semantics check on a signal " &
"asg with simple name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_st_arr3 <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
wait until (not s_st_arr3'Quiet) and
(savtime /= Std.Standard.Now) ;
--
end process P17 ;
--
PGEN_CHKP_17 :
process ( chk_st_arr3 )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P17" ,
"Inertial transactions entirely completed",
chk_st_arr3 = 8 ) ;
end if ;
end process PGEN_CHKP_17 ;
--
--
end ARCH00134 ;
--
use WORK.STANDARD_TYPES.all ;
entity ENT00134_Test_Bench is
signal s_boolean : boolean
:= c_boolean_1 ;
signal s_bit : bit
:= c_bit_1 ;
signal s_severity_level : severity_level
:= c_severity_level_1 ;
signal s_character : character
:= c_character_1 ;
signal s_st_enum1 : st_enum1
:= c_st_enum1_1 ;
signal s_integer : integer
:= c_integer_1 ;
signal s_st_int1 : st_int1
:= c_st_int1_1 ;
signal s_time : time
:= c_time_1 ;
signal s_st_phys1 : st_phys1
:= c_st_phys1_1 ;
signal s_real : real
:= c_real_1 ;
signal s_st_real1 : st_real1
:= c_st_real1_1 ;
signal s_st_rec1 : st_rec1
:= c_st_rec1_1 ;
signal s_st_rec2 : st_rec2
:= c_st_rec2_1 ;
signal s_st_rec3 : st_rec3
:= c_st_rec3_1 ;
signal s_st_arr1 : st_arr1
:= c_st_arr1_1 ;
signal s_st_arr2 : st_arr2
:= c_st_arr2_1 ;
signal s_st_arr3 : st_arr3
:= c_st_arr3_1 ;
--
end ENT00134_Test_Bench ;
--
architecture ARCH00134_Test_Bench of ENT00134_Test_Bench is
begin
L1:
block
component UUT
port (
s_boolean : inout boolean
; s_bit : inout bit
; s_severity_level : inout severity_level
; s_character : inout character
; s_st_enum1 : inout st_enum1
; s_integer : inout integer
; s_st_int1 : inout st_int1
; s_time : inout time
; s_st_phys1 : inout st_phys1
; s_real : inout real
; s_st_real1 : inout st_real1
; s_st_rec1 : inout st_rec1
; s_st_rec2 : inout st_rec2
; s_st_rec3 : inout st_rec3
; s_st_arr1 : inout st_arr1
; s_st_arr2 : inout st_arr2
; s_st_arr3 : inout st_arr3
) ;
end component ;
--
for CIS1 : UUT use entity WORK.ENT00134 ( ARCH00134 ) ;
begin
CIS1 : UUT
port map (
s_boolean
, s_bit
, s_severity_level
, s_character
, s_st_enum1
, s_integer
, s_st_int1
, s_time
, s_st_phys1
, s_real
, s_st_real1
, s_st_rec1
, s_st_rec2
, s_st_rec3
, s_st_arr1
, s_st_arr2
, s_st_arr3
) ;
end block L1 ;
end ARCH00134_Test_Bench ;
| gpl-3.0 | 53f01394d013dff5ba3e20af03b9eb07 | 0.490224 | 3.995423 | false | true | false | false |
grwlf/vsim | vhdl_ct/ct00595.vhd | 1 | 2,367 | -- NEED RESULT: ARCH00595: The base type of a subtype is the base type of the type or subtype denoted by type mark passed
-- NEED RESULT: ARCH00595: Subtype do not define new types passed
-------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
-------------------------------------------------------------------------------
--
-- TEST NAME:
--
-- CT00595
--
-- AUTHOR:
--
-- A. Wilmot
--
-- TEST OBJECTIVES:
--
-- 4.2 (5)
-- 4.2 (6)
--
-- DESIGN UNIT ORDERING:
--
-- E00000(ARCH00595)
-- ENT00595_Test_Bench(ARCH00595_Test_Bench)
--
-- REVISION HISTORY:
--
-- 26-AUG-1987 - initial revision
--
-- NOTES:
--
-- self-checking
--
use WORK.STANDARD_TYPES.all ;
architecture ARCH00595 of E00000 is
subtype severity_level_1 is severity_level ;
subtype severity_level_2 is severity_level_1 range warning to failure ;
subtype severity_level_3 is severity_level_2 range failure downto error ;
begin
process
subtype severity_level_3 is severity_level_2 range failure downto error ;
variable v_severity_level : severity_level := failure ;
variable v_severity_level_3 : severity_level_3 := failure ;
begin
test_report ( "ARCH00595" ,
"The base type of a subtype is the base type of"
& " the type or subtype denoted by type mark" ,
severity_level'base'left = note and
severity_level'base'right = failure and
severity_level_1'base'left = note and
severity_level_1'base'right = failure and
severity_level_2'base'left = note and
severity_level_2'base'right = failure and
severity_level_3'base'left = note and
severity_level_3'base'right = failure ) ;
test_report ( "ARCH00595" ,
"Subtype do not define new types " ,
v_severity_level_3 = v_severity_level ) ;
wait ;
end process ;
end ARCH00595 ;
--
entity ENT00595_Test_Bench is
end ENT00595_Test_Bench ;
architecture ARCH00595_Test_Bench of ENT00595_Test_Bench is
begin
L1:
block
component UUT
end component ;
for CIS1 : UUT use entity WORK.E00000 ( ARCH00595 ) ;
begin
CIS1 : UUT ;
end block L1 ;
end ARCH00595_Test_Bench ;
--
| gpl-3.0 | b6e8919d3eb310a5f31ea3ad1692a64c | 0.583016 | 3.630368 | false | true | false | false |
grwlf/vsim | vhdl_ct/ct00448.vhd | 1 | 12,711 | -- NEED RESULT: ARCH00448.Chk_s3: In absence of primaries that denote signals, an equivalent process statement for the concurrent sig asg has a wait statement with no sensitivity clause except for maybe the signal 'GUARD' passed
-- NEED RESULT: ARCH00448.Chk_s2: In absence of primaries that denote signals, an equivalent process statement for the concurrent sig asg has a wait statement with no sensitivity clause except for maybe the signal 'GUARD' passed
-- NEED RESULT: ARCH00448.Chk_s1: In absence of primaries that denote signals, an equivalent process statement for the concurrent sig asg has a wait statement with no sensitivity clause except for maybe the signal 'GUARD' passed
-- NEED RESULT: ARCH00448.Chk_s1: In absence of primaries that denote signals, an equivalent process statement for the concurrent sig asg has a wait statement with no sensitivity clause except for maybe the signal 'GUARD' passed
-- NEED RESULT: ARCH00448.Chk_s2: In absence of primaries that denote signals, an equivalent process statement for the concurrent sig asg has a wait statement with no sensitivity clause except for maybe the signal 'GUARD' passed
-- NEED RESULT: ARCH00448.Chk_s3: In absence of primaries that denote signals, an equivalent process statement for the concurrent sig asg has a wait statement with no sensitivity clause except for maybe the signal 'GUARD' passed
-- NEED RESULT: ARCH00448.Chk_gs3: In absence of primaries that denote signals, an equivalent process statement for the concurrent sig asg has a wait statement with no sensitivity clause except for maybe the signal 'GUARD' passed
-- NEED RESULT: ARCH00448.Chk_gs2: In absence of primaries that denote signals, an equivalent process statement for the concurrent sig asg has a wait statement with no sensitivity clause except for maybe the signal 'GUARD' passed
-- NEED RESULT: ARCH00448.Chk_gs1: In absence of primaries that denote signals, an equivalent process statement for the concurrent sig asg has a wait statement with no sensitivity clause except for maybe the signal 'GUARD' passed
-- NEED RESULT: ARCH00448.Chk_gs1: In absence of primaries that denote signals, an equivalent process statement for the concurrent sig asg has a wait statement with no sensitivity clause except for maybe the signal 'GUARD' passed
-- NEED RESULT: ARCH00448.Chk_gs2: In absence of primaries that denote signals, an equivalent process statement for the concurrent sig asg has a wait statement with no sensitivity clause except for maybe the signal 'GUARD' passed
-- NEED RESULT: ARCH00448.Chk_gs3: In absence of primaries that denote signals, an equivalent process statement for the concurrent sig asg has a wait statement with no sensitivity clause except for maybe the signal 'GUARD' passed
-------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
-------------------------------------------------------------------------------
--
-- TEST NAME:
--
-- ct00448
--
-- AUTHOR:
--
-- G. Tominovich
--
-- TEST OBJECTIVES:
--
-- 9.5 (8)
--
-- DESIGN UNIT ORDERING:
--
-- E00000(ARCH00448)
-- ENT00448_Test_Bench(ARCH00448_Test_Bench)
--
-- REVISION HISTORY:
--
-- 4-AUG-1987 - initial revision
--
-- NOTES:
--
-- self-checking
--
--
use WORK.STANDARD_TYPES.all ;
architecture ARCH00448 of E00000 is
function rfunc ( to_resolve : boolean_vector ) return boolean ;
subtype rboolean is rfunc boolean ;
signal Control : boolean := true ;
signal s1, s2, s3 : rboolean ;
alias gs1 : rboolean is s1 ;
alias gs2 : rboolean is s2 ;
alias gs3 : rboolean is s3 ;
signal Guard : boolean := false ;
function rfunc ( to_resolve : boolean_vector ) return boolean is
variable result : boolean := false ;
begin
for i in to_resolve'range loop
result := result or to_resolve (i) ;
end loop ;
return result ;
end rfunc ;
begin
B1 :
block ( Control ) -- Implicit Guard Signal
begin
s1 <= guarded transport Not s1 after 5 ns ;
s2 <= guarded transport False after 5 ns when s2 else
True after 5 ns ;
with s3 select
s3 <= guarded transport False after 5 ns when True,
True after 5 ns when others ;
end block B1 ;
Chk_s1 :
process ( s1 )
variable SavTime : Time ;
variable counter : Integer := 0 ;
begin
case counter is
when 0 =>
SavTime := Std.Standard.Now ;
when 1 =>
test_report ( "ARCH00448.Chk_s1" ,
"In absence of primaries that denote signals, an "&
"equivalent process statement for the concurrent "&
"sig asg has a wait statement with no sensitivity "&
"clause except for maybe the signal 'GUARD'" ,
s1 and ((SavTime+5 ns) = Std.Standard.Now) ) ;
when 2 =>
test_report ( "ARCH00448.Chk_s1" ,
"In absence of primaries that denote signals, an "&
"equivalent process statement for the concurrent "&
"sig asg has a wait statement with no sensitivity "&
"clause except for maybe the signal 'GUARD'" ,
(Not s1) and ((SavTime+10 ns) = Std.Standard.Now) ) ;
when 3 =>
test_report ( "ARCH00448.Chk_gs1" ,
"In absence of primaries that denote signals, an "&
"equivalent process statement for the concurrent "&
"sig asg has a wait statement with no sensitivity "&
"clause except for maybe the signal 'GUARD'" ,
gs1 and ((SavTime+105 ns) = Std.Standard.Now) ) ;
when 4 =>
test_report ( "ARCH00448.Chk_gs1" ,
"In absence of primaries that denote signals, an "&
"equivalent process statement for the concurrent "&
"sig asg has a wait statement with no sensitivity "&
"clause except for maybe the signal 'GUARD'" ,
(Not gs1) and ((SavTime+110 ns) = Std.Standard.Now) ) ;
when others =>
test_report ( "ARCH00448.Chk_s1" ,
"In absence of primaries that denote signals, an "&
"equivalent process statement for the concurrent "&
"sig asg has a wait statement with no sensitivity "&
"clause except for maybe the signal 'GUARD'" ,
False ) ;
end case ;
counter := counter + 1;
end process Chk_s1 ;
Chk_s2 :
process ( s2 )
variable SavTime : Time ;
variable counter : Integer := 0 ;
begin
case counter is
when 0 =>
SavTime := Std.Standard.Now ;
when 1 =>
test_report ( "ARCH00448.Chk_s2" ,
"In absence of primaries that denote signals, an "&
"equivalent process statement for the concurrent "&
"sig asg has a wait statement with no sensitivity "&
"clause except for maybe the signal 'GUARD'" ,
s2 and ((SavTime+5 ns) = Std.Standard.Now) ) ;
when 2 =>
test_report ( "ARCH00448.Chk_s2" ,
"In absence of primaries that denote signals, an "&
"equivalent process statement for the concurrent "&
"sig asg has a wait statement with no sensitivity "&
"clause except for maybe the signal 'GUARD'" ,
(Not s2) and ((SavTime+10 ns) = Std.Standard.Now) ) ;
when 3 =>
test_report ( "ARCH00448.Chk_gs2" ,
"In absence of primaries that denote signals, an "&
"equivalent process statement for the concurrent "&
"sig asg has a wait statement with no sensitivity "&
"clause except for maybe the signal 'GUARD'" ,
gs2 and ((SavTime+105 ns) = Std.Standard.Now) ) ;
when 4 =>
test_report ( "ARCH00448.Chk_gs2" ,
"In absence of primaries that denote signals, an "&
"equivalent process statement for the concurrent "&
"sig asg has a wait statement with no sensitivity "&
"clause except for maybe the signal 'GUARD'" ,
(Not gs2) and ((SavTime+110 ns) = Std.Standard.Now) ) ;
when others =>
test_report ( "ARCH00448.Chk_s2" ,
"In absence of primaries that denote signals, an "&
"equivalent process statement for the concurrent "&
"sig asg has a wait statement with no sensitivity "&
"clause except for maybe the signal 'GUARD'" ,
False ) ;
end case ;
counter := counter + 1;
end process Chk_s2 ;
Chk_s3 :
process ( s3 )
variable SavTime : Time ;
variable counter : Integer := 0 ;
begin
case counter is
when 0 =>
SavTime := Std.Standard.Now ;
when 1 =>
test_report ( "ARCH00448.Chk_s3" ,
"In absence of primaries that denote signals, an "&
"equivalent process statement for the concurrent "&
"sig asg has a wait statement with no sensitivity "&
"clause except for maybe the signal 'GUARD'" ,
s3 and ((SavTime+5 ns) = Std.Standard.Now) ) ;
when 2 =>
test_report ( "ARCH00448.Chk_s3" ,
"In absence of primaries that denote signals, an "&
"equivalent process statement for the concurrent "&
"sig asg has a wait statement with no sensitivity "&
"clause except for maybe the signal 'GUARD'" ,
(Not s3) and ((SavTime+10 ns) = Std.Standard.Now) ) ;
when 3 =>
test_report ( "ARCH00448.Chk_gs3" ,
"In absence of primaries that denote signals, an "&
"equivalent process statement for the concurrent "&
"sig asg has a wait statement with no sensitivity "&
"clause except for maybe the signal 'GUARD'" ,
gs3 and ((SavTime+105 ns) = Std.Standard.Now) ) ;
when 4 =>
test_report ( "ARCH00448.Chk_gs3" ,
"In absence of primaries that denote signals, an "&
"equivalent process statement for the concurrent "&
"sig asg has a wait statement with no sensitivity "&
"clause except for maybe the signal 'GUARD'" ,
(Not gs3) and ((SavTime+110 ns) = Std.Standard.Now) ) ;
when others =>
test_report ( "ARCH00448.Chk_s3" ,
"In absence of primaries that denote signals, an "&
"equivalent process statement for the concurrent "&
"sig asg has a wait statement with no sensitivity "&
"clause except for maybe the signal 'GUARD'" ,
False ) ;
end case ;
counter := counter + 1;
end process Chk_s3 ;
-- The following depend on the explicit signal Guard
gs1 <= guarded transport Not gs1 after 5 ns ;
gs2 <= guarded transport False after 5 ns when gs2 else
True after 5 ns ;
with gs3 select
gs3 <= guarded transport False after 5 ns when True,
True after 5 ns when others ;
-- DD modified this test 26-JUN-88 because the VHDL seemed to be an
-- infinite loop. He did not really understand the test, he just wanted
-- to get it to terminate.
-- The test used to read:
--Guard <= transport True after 100 ns;
-- Now it reads:
Guard <= transport True after 100 ns, False after 110 ns;
Control <= transport False after 10 ns;
end ARCH00448 ;
entity ENT00448_Test_Bench is
end ENT00448_Test_Bench ;
architecture ARCH00448_Test_Bench of ENT00448_Test_Bench is
begin
L1:
block
component UUT
end component ;
for CIS1 : UUT use entity WORK.E00000 ( ARCH00448 ) ;
begin
CIS1 : UUT ;
end block L1 ;
end ARCH00448_Test_Bench ;
| gpl-3.0 | 919c69875835c44d8f7919abe7e27912 | 0.577925 | 4.505849 | false | true | false | false |
grwlf/vsim | vhdl_ct/pro000009.vhd | 1 | 2,138 | -- Prosoft VHDL tests.
--
-- Copyright (C) 2011 Prosoft.
--
-- Author: Zefirov, Karavaev.
--
-- This is a set of simplest tests for isolated tests of VHDL features.
--
-- Nothing more than standard package should be required.
--
-- Categories: entity, architecture, process, after, component, if-then-else, procedure, constant.
entity ENT00006 is
port(
latch : in boolean
);
end entity;
architecture ARCH00006 of ENT00006 is
constant flag_const : boolean := true;
signal flag : boolean := false;
signal cond : boolean;
procedure print_report_valid (cond : in boolean) is
begin
if cond then
report "OK. flag = flag_const" severity NOTE;
else
report "error: flag /= flag_const" severity NOTE;
end if;
end procedure;
type boolVec is array (integer range <>) of boolean;
signal step : boolVec(1 to 3) := (others => false);
signal flag2 : boolean;
begin
flag2 <= flag_const;
process(step)
variable init : boolean := true;
variable v : boolean;
begin
if init then
step(1) <= true;
init := false;
elsif step(1) then
step(1) <= false;
step(2) <= true;
flag <= flag_const;
v := cond;
elsif step(2) then
cond <= flag = flag_const;
step(2) <= false;
step(3) <= true;
v := cond;
elsif step(3) then
v := cond;
print_report_valid(cond);
step(3) <= false;
else
null;
end if;
end process;
end ARCH00006;
entity ENT00006_Test_Bench is
end entity;
architecture ARCH00006_Test_Bench of ENT00006_Test_Bench is
component ENT00006 is
port(
latch : in boolean
);
end component;
signal latch : boolean := false;
begin
latch <= not latch after 1 us;
UUT1: ENT00006
port map (
latch => latch
);
UUT2: ENT00006
port map (
latch => latch
);
end ARCH00006_Test_Bench; | gpl-3.0 | 946716be5e074a11f2ed77f6fd8ca7e0 | 0.54537 | 3.894353 | false | true | false | false |
grwlf/vsim | vhdl_ct/ct00660.vhd | 1 | 4,436 | -- NEED RESULT: ARCH00660: Deferred constant declarations passed
-------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
-------------------------------------------------------------------------------
--
-- TEST NAME:
--
-- CT00660
--
-- AUTHOR:
--
-- A. Wilmot
--
-- TEST OBJECTIVES:
--
-- 4.3.1.1 (1)
--
-- DESIGN UNIT ORDERING:
--
-- PKG00660
-- PKG00660/BODY
-- E00000(ARCH00660)
-- ENT00660_Test_Bench(ARCH00660_Test_Bench)
--
-- REVISION HISTORY:
--
-- 19-AUG-1987 - initial revision
--
-- NOTES:
--
-- self-checking
-- automatically generated
--
use WORK.STANDARD_TYPES.all ;
package PKG00660 is
constant co_boolean_1 : boolean
;
constant co_bit_1 : bit
;
constant co_severity_level_1 : severity_level
;
constant co_character_1 : character
;
constant co_t_enum1_1 : t_enum1
;
constant co_st_enum1_1 : st_enum1
;
constant co_integer_1 : integer
;
constant co_t_int1_1 : t_int1
;
constant co_st_int1_1 : st_int1
;
constant co_time_1 : time
;
constant co_t_phys1_1 : t_phys1
;
constant co_st_phys1_1 : st_phys1
;
constant co_real_1 : real
;
constant co_t_real1_1 : t_real1
;
constant co_st_real1_1 : st_real1
;
end PKG00660 ;
package body PKG00660 is
constant co_boolean_1 : boolean
:= c_boolean_1 ;
constant co_bit_1 : bit
:= c_bit_1 ;
constant co_severity_level_1 : severity_level
:= c_severity_level_1 ;
constant co_character_1 : character
:= c_character_1 ;
constant co_t_enum1_1 : t_enum1
:= c_t_enum1_1 ;
constant co_st_enum1_1 : st_enum1
:= c_st_enum1_1 ;
constant co_integer_1 : integer
:= c_integer_1 ;
constant co_t_int1_1 : t_int1
:= c_t_int1_1 ;
constant co_st_int1_1 : st_int1
:= c_st_int1_1 ;
constant co_time_1 : time
:= c_time_1 ;
constant co_t_phys1_1 : t_phys1
:= c_t_phys1_1 ;
constant co_st_phys1_1 : st_phys1
:= c_st_phys1_1 ;
constant co_real_1 : real
:= c_real_1 ;
constant co_t_real1_1 : t_real1
:= c_t_real1_1 ;
constant co_st_real1_1 : st_real1
:= c_st_real1_1 ;
end PKG00660 ;
use WORK.STANDARD_TYPES.all ;
use WORK.PKG00660.all ;
architecture ARCH00660 of E00000 is
begin
process
variable correct : boolean := true ;
begin
correct := correct and co_boolean_1
= c_boolean_1 ;
correct := correct and co_bit_1
= c_bit_1 ;
correct := correct and co_severity_level_1
= c_severity_level_1 ;
correct := correct and co_character_1
= c_character_1 ;
correct := correct and co_t_enum1_1
= c_t_enum1_1 ;
correct := correct and co_st_enum1_1
= c_st_enum1_1 ;
correct := correct and co_integer_1
= c_integer_1 ;
correct := correct and co_t_int1_1
= c_t_int1_1 ;
correct := correct and co_st_int1_1
= c_st_int1_1 ;
correct := correct and co_time_1
= c_time_1 ;
correct := correct and co_t_phys1_1
= c_t_phys1_1 ;
correct := correct and co_st_phys1_1
= c_st_phys1_1 ;
correct := correct and co_real_1
= c_real_1 ;
correct := correct and co_t_real1_1
= c_t_real1_1 ;
correct := correct and co_st_real1_1
= c_st_real1_1 ;
test_report ( "ARCH00660" ,
"Deferred constant declarations" ,
correct) ;
wait ;
end process ;
end ARCH00660 ;
--
entity ENT00660_Test_Bench is
end ENT00660_Test_Bench ;
--
architecture ARCH00660_Test_Bench of ENT00660_Test_Bench is
begin
L1:
block
component UUT
end component ;
for CIS1 : UUT use entity WORK.E00000 ( ARCH00660 ) ;
begin
CIS1 : UUT ;
end block L1 ;
end ARCH00660_Test_Bench ;
| gpl-3.0 | ae1409831f0ddcedab2d1dc7a1bde011 | 0.490081 | 3.342879 | false | true | false | false |
grwlf/vsim | vhdl_ct/ct00212.vhd | 1 | 3,520 | -------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
-------------------------------------------------------------------------------
--
-- TEST NAME:
--
-- CT00212
--
-- AUTHOR:
--
-- G. Tominovich
--
-- TEST OBJECTIVES:
--
-- 8.1 (5)
--
-- DESIGN UNIT ORDERING:
--
-- ENT00212(ARCH00212)
-- ENT00212_Test_Bench(ARCH00212_Test_Bench)
--
-- REVISION HISTORY:
--
-- 10-JUL-1987 - initial revision
--
-- NOTES:
--
-- self-checking
-- automatically generated
--
use WORK.STANDARD_TYPES.all ;
entity ENT00212 is
generic (G : integer) ;
--
constant CG : integer := G+1;
attribute attr : integer ;
attribute attr of CG : constant is CG+1;
--
end ENT00212 ;
--
--
architecture ARCH00212 of ENT00212 is
signal s_st_rec3 : st_rec3
:= c_st_rec3_1 ;
--
subtype chk_sig_type is integer range -1 to 100 ;
signal chk_st_rec3 : chk_sig_type := -1 ;
--
procedure Proc1 (
signal s_st_rec3 : inout st_rec3
; variable counter : inout integer
; variable correct : inout boolean
; variable savtime : inout time
; signal chk_st_rec3 : out chk_sig_type
)
is
begin
case counter is
when 0
=>
s_st_rec3.f1 <= transport
c_st_rec3_2.f1 ;
s_st_rec3.f2 <= transport
c_st_rec3_2.f2 after 10 ns ;
wait until s_st_rec3.f2 =
c_st_rec3_2.f2 ;
Test_Report (
"ENT00212",
"Wait statement longest static prefix check",
((savtime + 10 ns) = Std.Standard.Now) and
(s_st_rec3.f2 =
c_st_rec3_2.f2 )) ;
--
when 1
=>
s_st_rec3.f1 <= transport
c_st_rec3_1.f1 ;
s_st_rec3.f3 <= transport
c_st_rec3_2.f3 after 10 ns ;
wait until s_st_rec3.f3 =
c_st_rec3_2.f3 ;
Test_Report (
"ENT00212",
"Wait statement longest static prefix check",
((savtime + 10 ns) = Std.Standard.Now) and
(s_st_rec3.f3 =
c_st_rec3_2.f3 )) ;
--
when others
=> wait ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_st_rec3 <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
end Proc1 ;
--
begin
P1 :
process
variable counter : integer := 0 ;
variable correct : boolean ;
variable savtime : time := 0 ns ;
begin
Proc1 (
s_st_rec3
, counter
, correct
, savtime
, chk_st_rec3
) ;
end process P1 ;
--
PGEN_CHKP_1 :
process ( chk_st_rec3 )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P1" ,
"Wait longest static prefix test completed",
chk_st_rec3 = 1 ) ;
end if ;
end process PGEN_CHKP_1 ;
--
--
end ARCH00212 ;
--
--
use WORK.STANDARD_TYPES.all ;
entity ENT00212_Test_Bench is
end ENT00212_Test_Bench ;
--
--
architecture ARCH00212_Test_Bench of ENT00212_Test_Bench is
begin
L1:
block
component UUT
generic (G : integer) ;
end component ;
--
for CIS1 : UUT use entity WORK.ENT00212 ( ARCH00212 ) ;
begin
CIS1 : UUT
generic map (lowb+2)
;
end block L1 ;
end ARCH00212_Test_Bench ;
| gpl-3.0 | ec2bef958912859eaaf700b9fcb63cdc | 0.490341 | 3.52 | false | true | false | false |
grwlf/vsim | vhdl_ct/ct00639.vhd | 1 | 99,755 | -- NEED RESULT: ARCH00639.P1: Multi inertial transactions occurred on signal asg with slice name on LHS passed
-- NEED RESULT: ARCH00639.P2: Multi inertial transactions occurred on signal asg with slice name on LHS passed
-- NEED RESULT: ARCH00639.P3: Multi inertial transactions occurred on signal asg with slice name on LHS passed
-- NEED RESULT: ARCH00639.P4: Multi inertial transactions occurred on signal asg with slice name on LHS passed
-- NEED RESULT: ARCH00639.P5: Multi inertial transactions occurred on signal asg with slice name on LHS passed
-- NEED RESULT: ARCH00639.P6: Multi inertial transactions occurred on signal asg with slice name on LHS passed
-- NEED RESULT: ARCH00639.P7: Multi inertial transactions occurred on signal asg with slice name on LHS passed
-- NEED RESULT: ARCH00639.P8: Multi inertial transactions occurred on signal asg with slice name on LHS passed
-- NEED RESULT: ARCH00639.P9: Multi inertial transactions occurred on signal asg with slice name on LHS passed
-- NEED RESULT: ARCH00639.P10: Multi inertial transactions occurred on signal asg with slice name on LHS passed
-- NEED RESULT: ARCH00639.P11: Multi inertial transactions occurred on signal asg with slice name on LHS passed
-- NEED RESULT: ARCH00639.P12: Multi inertial transactions occurred on signal asg with slice name on LHS passed
-- NEED RESULT: ARCH00639.P13: Multi inertial transactions occurred on signal asg with slice name on LHS passed
-- NEED RESULT: ARCH00639.P14: Multi inertial transactions occurred on signal asg with slice name on LHS passed
-- NEED RESULT: ARCH00639.P15: Multi inertial transactions occurred on signal asg with slice name on LHS passed
-- NEED RESULT: ARCH00639.P16: Multi inertial transactions occurred on signal asg with slice name on LHS passed
-- NEED RESULT: ARCH00639.P17: Multi inertial transactions occurred on signal asg with slice name on LHS passed
-- NEED RESULT: ARCH00639: One inertial transaction occurred on signal asg with slice name on LHS passed
-- NEED RESULT: ARCH00639: One inertial transaction occurred on signal asg with slice name on LHS passed
-- NEED RESULT: ARCH00639: One inertial transaction occurred on signal asg with slice name on LHS passed
-- NEED RESULT: ARCH00639: One inertial transaction occurred on signal asg with slice name on LHS passed
-- NEED RESULT: ARCH00639: One inertial transaction occurred on signal asg with slice name on LHS passed
-- NEED RESULT: ARCH00639: One inertial transaction occurred on signal asg with slice name on LHS passed
-- NEED RESULT: ARCH00639: One inertial transaction occurred on signal asg with slice name on LHS passed
-- NEED RESULT: ARCH00639: One inertial transaction occurred on signal asg with slice name on LHS passed
-- NEED RESULT: ARCH00639: One inertial transaction occurred on signal asg with slice name on LHS passed
-- NEED RESULT: ARCH00639: One inertial transaction occurred on signal asg with slice name on LHS passed
-- NEED RESULT: ARCH00639: One inertial transaction occurred on signal asg with slice name on LHS passed
-- NEED RESULT: ARCH00639: One inertial transaction occurred on signal asg with slice name on LHS passed
-- NEED RESULT: ARCH00639: One inertial transaction occurred on signal asg with slice name on LHS passed
-- NEED RESULT: ARCH00639: One inertial transaction occurred on signal asg with slice name on LHS passed
-- NEED RESULT: ARCH00639: One inertial transaction occurred on signal asg with slice name on LHS passed
-- NEED RESULT: ARCH00639: One inertial transaction occurred on signal asg with slice name on LHS passed
-- NEED RESULT: ARCH00639: One inertial transaction occurred on signal asg with slice name on LHS passed
-- NEED RESULT: P17: Inertial transactions entirely completed failed
-- NEED RESULT: P16: Inertial transactions entirely completed failed
-- NEED RESULT: P15: Inertial transactions entirely completed failed
-- NEED RESULT: P14: Inertial transactions entirely completed failed
-- NEED RESULT: P13: Inertial transactions entirely completed failed
-- NEED RESULT: P12: Inertial transactions entirely completed failed
-- NEED RESULT: P11: Inertial transactions entirely completed failed
-- NEED RESULT: P10: Inertial transactions entirely completed failed
-- NEED RESULT: P9: Inertial transactions entirely completed failed
-- NEED RESULT: P8: Inertial transactions entirely completed failed
-- NEED RESULT: P7: Inertial transactions entirely completed failed
-- NEED RESULT: P6: Inertial transactions entirely completed failed
-- NEED RESULT: P5: Inertial transactions entirely completed failed
-- NEED RESULT: P4: Inertial transactions entirely completed failed
-- NEED RESULT: P3: Inertial transactions entirely completed failed
-- NEED RESULT: P2: Inertial transactions entirely completed failed
-- NEED RESULT: P1: Inertial transactions entirely completed failed
-------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
-------------------------------------------------------------------------------
--
-- TEST NAME:
--
-- CT00639
--
-- AUTHOR:
--
-- G. Tominovich
--
-- TEST OBJECTIVES:
--
-- 8.3 (1)
-- 8.3 (2)
-- 8.3 (4)
-- 8.3 (6)
-- 8.3.1 (4)
--
-- DESIGN UNIT ORDERING:
--
-- E00000(ARCH00639)
-- ENT00639_Test_Bench(ARCH00639_Test_Bench)
--
-- REVISION HISTORY:
--
-- 25-AUG-1987 - initial revision
--
-- NOTES:
--
-- self-checking
-- automatically generated
--
use WORK.STANDARD_TYPES.all ;
architecture ARCH00639 of E00000 is
subtype chk_sig_type is integer range -1 to 100 ;
signal chk_st_boolean_vector : chk_sig_type := -1 ;
signal chk_st_bit_vector : chk_sig_type := -1 ;
signal chk_st_severity_level_vector : chk_sig_type := -1 ;
signal chk_st_string : chk_sig_type := -1 ;
signal chk_st_enum1_vector : chk_sig_type := -1 ;
signal chk_st_integer_vector : chk_sig_type := -1 ;
signal chk_st_int1_vector : chk_sig_type := -1 ;
signal chk_st_time_vector : chk_sig_type := -1 ;
signal chk_st_phys1_vector : chk_sig_type := -1 ;
signal chk_st_real_vector : chk_sig_type := -1 ;
signal chk_st_real1_vector : chk_sig_type := -1 ;
signal chk_st_rec1_vector : chk_sig_type := -1 ;
signal chk_st_rec2_vector : chk_sig_type := -1 ;
signal chk_st_rec3_vector : chk_sig_type := -1 ;
signal chk_st_arr1_vector : chk_sig_type := -1 ;
signal chk_st_arr2_vector : chk_sig_type := -1 ;
signal chk_st_arr3_vector : chk_sig_type := -1 ;
--
signal s_st_boolean_vector : st_boolean_vector
:= c_st_boolean_vector_1 ;
signal s_st_bit_vector : st_bit_vector
:= c_st_bit_vector_1 ;
signal s_st_severity_level_vector : st_severity_level_vector
:= c_st_severity_level_vector_1 ;
signal s_st_string : st_string
:= c_st_string_1 ;
signal s_st_enum1_vector : st_enum1_vector
:= c_st_enum1_vector_1 ;
signal s_st_integer_vector : st_integer_vector
:= c_st_integer_vector_1 ;
signal s_st_int1_vector : st_int1_vector
:= c_st_int1_vector_1 ;
signal s_st_time_vector : st_time_vector
:= c_st_time_vector_1 ;
signal s_st_phys1_vector : st_phys1_vector
:= c_st_phys1_vector_1 ;
signal s_st_real_vector : st_real_vector
:= c_st_real_vector_1 ;
signal s_st_real1_vector : st_real1_vector
:= c_st_real1_vector_1 ;
signal s_st_rec1_vector : st_rec1_vector
:= c_st_rec1_vector_1 ;
signal s_st_rec2_vector : st_rec2_vector
:= c_st_rec2_vector_1 ;
signal s_st_rec3_vector : st_rec3_vector
:= c_st_rec3_vector_1 ;
signal s_st_arr1_vector : st_arr1_vector
:= c_st_arr1_vector_1 ;
signal s_st_arr2_vector : st_arr2_vector
:= c_st_arr2_vector_1 ;
signal s_st_arr3_vector : st_arr3_vector
:= c_st_arr3_vector_1 ;
--
begin
P1 :
process
variable correct : boolean ;
variable counter : integer := 0 ;
variable savtime : time ;
begin
case counter is
when 0
=> (s_st_boolean_vector (lowb+1),
s_st_boolean_vector (lowb+2),
s_st_boolean_vector (lowb+3)) <=
c_st_boolean_vector_2 (lowb+1 to lowb+3) after 10 ns,
c_st_boolean_vector_1 (lowb+1 to lowb+3) after 20 ns ;
--
when 1
=> correct :=
s_st_boolean_vector (lowb+1 to lowb+3) =
c_st_boolean_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_boolean_vector (lowb+1 to lowb+3) =
c_st_boolean_vector_1 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00639.P1" ,
"Multi inertial transactions occurred on signal " &
"asg with slice name on LHS",
correct ) ;
(s_st_boolean_vector (lowb+1),
s_st_boolean_vector (lowb+2),
s_st_boolean_vector (lowb+3)) <=
c_st_boolean_vector_2 (lowb+1 to lowb+3) after 10 ns ,
c_st_boolean_vector_1 (lowb+1 to lowb+3) after 20 ns ,
c_st_boolean_vector_2 (lowb+1 to lowb+3) after 30 ns ,
c_st_boolean_vector_1 (lowb+1 to lowb+3) after 40 ns ;
--
when 3
=> correct :=
s_st_boolean_vector (lowb+1 to lowb+3) =
c_st_boolean_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
(s_st_boolean_vector (lowb+1),
s_st_boolean_vector (lowb+2),
s_st_boolean_vector (lowb+3)) <=
c_st_boolean_vector_1 (lowb+1 to lowb+3) after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_boolean_vector (lowb+1 to lowb+3) =
c_st_boolean_vector_1 (lowb+1 to lowb+3) and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00639" ,
"One inertial transaction occurred on signal " &
"asg with slice name on LHS",
correct ) ;
(s_st_boolean_vector (lowb+1),
s_st_boolean_vector (lowb+2),
s_st_boolean_vector (lowb+3)) <= transport
c_st_boolean_vector_1 (lowb+1 to lowb+3) after 100 ns ;
--
when 5
=> correct :=
s_st_boolean_vector (lowb+1 to lowb+3) =
c_st_boolean_vector_1 (lowb+1 to lowb+3) and
(savtime + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00639" ,
"Old transactions were removed on signal " &
"asg with slice name on LHS",
correct ) ;
(s_st_boolean_vector (lowb+1),
s_st_boolean_vector (lowb+2),
s_st_boolean_vector (lowb+3)) <=
c_st_boolean_vector_2 (lowb+1 to lowb+3) after 10 ns ,
c_st_boolean_vector_1 (lowb+1 to lowb+3) after 20 ns ,
c_st_boolean_vector_2 (lowb+1 to lowb+3) after 30 ns ,
c_st_boolean_vector_1 (lowb+1 to lowb+3) after 40 ns ;
--
when 6
=> correct :=
s_st_boolean_vector (lowb+1 to lowb+3) =
c_st_boolean_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00639" ,
"One inertial transaction occurred on signal " &
"asg with slice name on LHS",
correct ) ;
-- Last transaction above is marked by following
(s_st_boolean_vector (lowb+1),
s_st_boolean_vector (lowb+2),
s_st_boolean_vector (lowb+3)) <=
c_st_boolean_vector_1 (lowb+1 to lowb+3) after 40 ns ;
--
when 7
=> correct :=
s_st_boolean_vector (lowb+1 to lowb+3) =
c_st_boolean_vector_1 (lowb+1 to lowb+3) and
(savtime + 30 ns) = Std.Standard.Now ;
--
when 8
=> correct := correct and
s_st_boolean_vector (lowb+1 to lowb+3) =
c_st_boolean_vector_1 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00639" ,
"Inertial semantics check on a signal " &
"asg with slice name on LHS",
correct ) ;
--
when others
=>
test_report ( "ARCH00639" ,
"Inertial semantics check on a signal " &
"asg with slice name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_st_boolean_vector <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
wait until (not s_st_boolean_vector'Quiet) and
(savtime /= Std.Standard.Now) ;
--
end process P1 ;
--
PGEN_CHKP_1 :
process ( chk_st_boolean_vector )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P1" ,
"Inertial transactions entirely completed",
chk_st_boolean_vector = 8 ) ;
end if ;
end process PGEN_CHKP_1 ;
--
P2 :
process
variable correct : boolean ;
variable counter : integer := 0 ;
variable savtime : time ;
begin
case counter is
when 0
=> (s_st_bit_vector (lowb+1),
s_st_bit_vector (lowb+2),
s_st_bit_vector (lowb+3)) <=
c_st_bit_vector_2 (lowb+1 to lowb+3) after 10 ns,
c_st_bit_vector_1 (lowb+1 to lowb+3) after 20 ns ;
--
when 1
=> correct :=
s_st_bit_vector (lowb+1 to lowb+3) =
c_st_bit_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_bit_vector (lowb+1 to lowb+3) =
c_st_bit_vector_1 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00639.P2" ,
"Multi inertial transactions occurred on signal " &
"asg with slice name on LHS",
correct ) ;
(s_st_bit_vector (lowb+1),
s_st_bit_vector (lowb+2),
s_st_bit_vector (lowb+3)) <=
c_st_bit_vector_2 (lowb+1 to lowb+3) after 10 ns ,
c_st_bit_vector_1 (lowb+1 to lowb+3) after 20 ns ,
c_st_bit_vector_2 (lowb+1 to lowb+3) after 30 ns ,
c_st_bit_vector_1 (lowb+1 to lowb+3) after 40 ns ;
--
when 3
=> correct :=
s_st_bit_vector (lowb+1 to lowb+3) =
c_st_bit_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
(s_st_bit_vector (lowb+1),
s_st_bit_vector (lowb+2),
s_st_bit_vector (lowb+3)) <=
c_st_bit_vector_1 (lowb+1 to lowb+3) after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_bit_vector (lowb+1 to lowb+3) =
c_st_bit_vector_1 (lowb+1 to lowb+3) and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00639" ,
"One inertial transaction occurred on signal " &
"asg with slice name on LHS",
correct ) ;
(s_st_bit_vector (lowb+1),
s_st_bit_vector (lowb+2),
s_st_bit_vector (lowb+3)) <= transport
c_st_bit_vector_1 (lowb+1 to lowb+3) after 100 ns ;
--
when 5
=> correct :=
s_st_bit_vector (lowb+1 to lowb+3) =
c_st_bit_vector_1 (lowb+1 to lowb+3) and
(savtime + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00639" ,
"Old transactions were removed on signal " &
"asg with slice name on LHS",
correct ) ;
(s_st_bit_vector (lowb+1),
s_st_bit_vector (lowb+2),
s_st_bit_vector (lowb+3)) <=
c_st_bit_vector_2 (lowb+1 to lowb+3) after 10 ns ,
c_st_bit_vector_1 (lowb+1 to lowb+3) after 20 ns ,
c_st_bit_vector_2 (lowb+1 to lowb+3) after 30 ns ,
c_st_bit_vector_1 (lowb+1 to lowb+3) after 40 ns ;
--
when 6
=> correct :=
s_st_bit_vector (lowb+1 to lowb+3) =
c_st_bit_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00639" ,
"One inertial transaction occurred on signal " &
"asg with slice name on LHS",
correct ) ;
-- Last transaction above is marked by following
(s_st_bit_vector (lowb+1),
s_st_bit_vector (lowb+2),
s_st_bit_vector (lowb+3)) <=
c_st_bit_vector_1 (lowb+1 to lowb+3) after 40 ns ;
--
when 7
=> correct :=
s_st_bit_vector (lowb+1 to lowb+3) =
c_st_bit_vector_1 (lowb+1 to lowb+3) and
(savtime + 30 ns) = Std.Standard.Now ;
--
when 8
=> correct := correct and
s_st_bit_vector (lowb+1 to lowb+3) =
c_st_bit_vector_1 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00639" ,
"Inertial semantics check on a signal " &
"asg with slice name on LHS",
correct ) ;
--
when others
=>
test_report ( "ARCH00639" ,
"Inertial semantics check on a signal " &
"asg with slice name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_st_bit_vector <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
wait until (not s_st_bit_vector'Quiet) and
(savtime /= Std.Standard.Now) ;
--
end process P2 ;
--
PGEN_CHKP_2 :
process ( chk_st_bit_vector )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P2" ,
"Inertial transactions entirely completed",
chk_st_bit_vector = 8 ) ;
end if ;
end process PGEN_CHKP_2 ;
--
P3 :
process
variable correct : boolean ;
variable counter : integer := 0 ;
variable savtime : time ;
begin
case counter is
when 0
=> (s_st_severity_level_vector (lowb+1),
s_st_severity_level_vector (lowb+2),
s_st_severity_level_vector (lowb+3)) <=
c_st_severity_level_vector_2 (lowb+1 to lowb+3) after 10 ns,
c_st_severity_level_vector_1 (lowb+1 to lowb+3) after 20 ns ;
--
when 1
=> correct :=
s_st_severity_level_vector (lowb+1 to lowb+3) =
c_st_severity_level_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_severity_level_vector (lowb+1 to lowb+3) =
c_st_severity_level_vector_1 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00639.P3" ,
"Multi inertial transactions occurred on signal " &
"asg with slice name on LHS",
correct ) ;
(s_st_severity_level_vector (lowb+1),
s_st_severity_level_vector (lowb+2),
s_st_severity_level_vector (lowb+3)) <=
c_st_severity_level_vector_2 (lowb+1 to lowb+3) after 10 ns ,
c_st_severity_level_vector_1 (lowb+1 to lowb+3) after 20 ns ,
c_st_severity_level_vector_2 (lowb+1 to lowb+3) after 30 ns ,
c_st_severity_level_vector_1 (lowb+1 to lowb+3) after 40 ns ;
--
when 3
=> correct :=
s_st_severity_level_vector (lowb+1 to lowb+3) =
c_st_severity_level_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
(s_st_severity_level_vector (lowb+1),
s_st_severity_level_vector (lowb+2),
s_st_severity_level_vector (lowb+3)) <=
c_st_severity_level_vector_1 (lowb+1 to lowb+3) after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_severity_level_vector (lowb+1 to lowb+3) =
c_st_severity_level_vector_1 (lowb+1 to lowb+3) and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00639" ,
"One inertial transaction occurred on signal " &
"asg with slice name on LHS",
correct ) ;
(s_st_severity_level_vector (lowb+1),
s_st_severity_level_vector (lowb+2),
s_st_severity_level_vector (lowb+3)) <= transport
c_st_severity_level_vector_1 (lowb+1 to lowb+3) after 100 ns ;
--
when 5
=> correct :=
s_st_severity_level_vector (lowb+1 to lowb+3) =
c_st_severity_level_vector_1 (lowb+1 to lowb+3) and
(savtime + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00639" ,
"Old transactions were removed on signal " &
"asg with slice name on LHS",
correct ) ;
(s_st_severity_level_vector (lowb+1),
s_st_severity_level_vector (lowb+2),
s_st_severity_level_vector (lowb+3)) <=
c_st_severity_level_vector_2 (lowb+1 to lowb+3) after 10 ns ,
c_st_severity_level_vector_1 (lowb+1 to lowb+3) after 20 ns ,
c_st_severity_level_vector_2 (lowb+1 to lowb+3) after 30 ns ,
c_st_severity_level_vector_1 (lowb+1 to lowb+3) after 40 ns ;
--
when 6
=> correct :=
s_st_severity_level_vector (lowb+1 to lowb+3) =
c_st_severity_level_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00639" ,
"One inertial transaction occurred on signal " &
"asg with slice name on LHS",
correct ) ;
-- Last transaction above is marked by following
(s_st_severity_level_vector (lowb+1),
s_st_severity_level_vector (lowb+2),
s_st_severity_level_vector (lowb+3)) <=
c_st_severity_level_vector_1 (lowb+1 to lowb+3) after 40 ns ;
--
when 7
=> correct :=
s_st_severity_level_vector (lowb+1 to lowb+3) =
c_st_severity_level_vector_1 (lowb+1 to lowb+3) and
(savtime + 30 ns) = Std.Standard.Now ;
--
when 8
=> correct := correct and
s_st_severity_level_vector (lowb+1 to lowb+3) =
c_st_severity_level_vector_1 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00639" ,
"Inertial semantics check on a signal " &
"asg with slice name on LHS",
correct ) ;
--
when others
=>
test_report ( "ARCH00639" ,
"Inertial semantics check on a signal " &
"asg with slice name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_st_severity_level_vector <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
wait until (not s_st_severity_level_vector'Quiet) and
(savtime /= Std.Standard.Now) ;
--
end process P3 ;
--
PGEN_CHKP_3 :
process ( chk_st_severity_level_vector )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P3" ,
"Inertial transactions entirely completed",
chk_st_severity_level_vector = 8 ) ;
end if ;
end process PGEN_CHKP_3 ;
--
P4 :
process
variable correct : boolean ;
variable counter : integer := 0 ;
variable savtime : time ;
begin
case counter is
when 0
=> (s_st_string (lowb+1),
s_st_string (lowb+2),
s_st_string (lowb+3)) <=
c_st_string_2 (lowb+1 to lowb+3) after 10 ns,
c_st_string_1 (lowb+1 to lowb+3) after 20 ns ;
--
when 1
=> correct :=
s_st_string (lowb+1 to lowb+3) =
c_st_string_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_string (lowb+1 to lowb+3) =
c_st_string_1 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00639.P4" ,
"Multi inertial transactions occurred on signal " &
"asg with slice name on LHS",
correct ) ;
(s_st_string (lowb+1),
s_st_string (lowb+2),
s_st_string (lowb+3)) <=
c_st_string_2 (lowb+1 to lowb+3) after 10 ns ,
c_st_string_1 (lowb+1 to lowb+3) after 20 ns ,
c_st_string_2 (lowb+1 to lowb+3) after 30 ns ,
c_st_string_1 (lowb+1 to lowb+3) after 40 ns ;
--
when 3
=> correct :=
s_st_string (lowb+1 to lowb+3) =
c_st_string_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
(s_st_string (lowb+1),
s_st_string (lowb+2),
s_st_string (lowb+3)) <=
c_st_string_1 (lowb+1 to lowb+3) after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_string (lowb+1 to lowb+3) =
c_st_string_1 (lowb+1 to lowb+3) and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00639" ,
"One inertial transaction occurred on signal " &
"asg with slice name on LHS",
correct ) ;
(s_st_string (lowb+1),
s_st_string (lowb+2),
s_st_string (lowb+3)) <= transport
c_st_string_1 (lowb+1 to lowb+3) after 100 ns ;
--
when 5
=> correct :=
s_st_string (lowb+1 to lowb+3) =
c_st_string_1 (lowb+1 to lowb+3) and
(savtime + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00639" ,
"Old transactions were removed on signal " &
"asg with slice name on LHS",
correct ) ;
(s_st_string (lowb+1),
s_st_string (lowb+2),
s_st_string (lowb+3)) <=
c_st_string_2 (lowb+1 to lowb+3) after 10 ns ,
c_st_string_1 (lowb+1 to lowb+3) after 20 ns ,
c_st_string_2 (lowb+1 to lowb+3) after 30 ns ,
c_st_string_1 (lowb+1 to lowb+3) after 40 ns ;
--
when 6
=> correct :=
s_st_string (lowb+1 to lowb+3) =
c_st_string_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00639" ,
"One inertial transaction occurred on signal " &
"asg with slice name on LHS",
correct ) ;
-- Last transaction above is marked by following
(s_st_string (lowb+1),
s_st_string (lowb+2),
s_st_string (lowb+3)) <=
c_st_string_1 (lowb+1 to lowb+3) after 40 ns ;
--
when 7
=> correct :=
s_st_string (lowb+1 to lowb+3) =
c_st_string_1 (lowb+1 to lowb+3) and
(savtime + 30 ns) = Std.Standard.Now ;
--
when 8
=> correct := correct and
s_st_string (lowb+1 to lowb+3) =
c_st_string_1 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00639" ,
"Inertial semantics check on a signal " &
"asg with slice name on LHS",
correct ) ;
--
when others
=>
test_report ( "ARCH00639" ,
"Inertial semantics check on a signal " &
"asg with slice name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_st_string <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
wait until (not s_st_string'Quiet) and
(savtime /= Std.Standard.Now) ;
--
end process P4 ;
--
PGEN_CHKP_4 :
process ( chk_st_string )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P4" ,
"Inertial transactions entirely completed",
chk_st_string = 8 ) ;
end if ;
end process PGEN_CHKP_4 ;
--
P5 :
process
variable correct : boolean ;
variable counter : integer := 0 ;
variable savtime : time ;
begin
case counter is
when 0
=> (s_st_enum1_vector (lowb+1),
s_st_enum1_vector (lowb+2),
s_st_enum1_vector (lowb+3)) <=
c_st_enum1_vector_2 (lowb+1 to lowb+3) after 10 ns,
c_st_enum1_vector_1 (lowb+1 to lowb+3) after 20 ns ;
--
when 1
=> correct :=
s_st_enum1_vector (lowb+1 to lowb+3) =
c_st_enum1_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_enum1_vector (lowb+1 to lowb+3) =
c_st_enum1_vector_1 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00639.P5" ,
"Multi inertial transactions occurred on signal " &
"asg with slice name on LHS",
correct ) ;
(s_st_enum1_vector (lowb+1),
s_st_enum1_vector (lowb+2),
s_st_enum1_vector (lowb+3)) <=
c_st_enum1_vector_2 (lowb+1 to lowb+3) after 10 ns ,
c_st_enum1_vector_1 (lowb+1 to lowb+3) after 20 ns ,
c_st_enum1_vector_2 (lowb+1 to lowb+3) after 30 ns ,
c_st_enum1_vector_1 (lowb+1 to lowb+3) after 40 ns ;
--
when 3
=> correct :=
s_st_enum1_vector (lowb+1 to lowb+3) =
c_st_enum1_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
(s_st_enum1_vector (lowb+1),
s_st_enum1_vector (lowb+2),
s_st_enum1_vector (lowb+3)) <=
c_st_enum1_vector_1 (lowb+1 to lowb+3) after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_enum1_vector (lowb+1 to lowb+3) =
c_st_enum1_vector_1 (lowb+1 to lowb+3) and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00639" ,
"One inertial transaction occurred on signal " &
"asg with slice name on LHS",
correct ) ;
(s_st_enum1_vector (lowb+1),
s_st_enum1_vector (lowb+2),
s_st_enum1_vector (lowb+3)) <= transport
c_st_enum1_vector_1 (lowb+1 to lowb+3) after 100 ns ;
--
when 5
=> correct :=
s_st_enum1_vector (lowb+1 to lowb+3) =
c_st_enum1_vector_1 (lowb+1 to lowb+3) and
(savtime + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00639" ,
"Old transactions were removed on signal " &
"asg with slice name on LHS",
correct ) ;
(s_st_enum1_vector (lowb+1),
s_st_enum1_vector (lowb+2),
s_st_enum1_vector (lowb+3)) <=
c_st_enum1_vector_2 (lowb+1 to lowb+3) after 10 ns ,
c_st_enum1_vector_1 (lowb+1 to lowb+3) after 20 ns ,
c_st_enum1_vector_2 (lowb+1 to lowb+3) after 30 ns ,
c_st_enum1_vector_1 (lowb+1 to lowb+3) after 40 ns ;
--
when 6
=> correct :=
s_st_enum1_vector (lowb+1 to lowb+3) =
c_st_enum1_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00639" ,
"One inertial transaction occurred on signal " &
"asg with slice name on LHS",
correct ) ;
-- Last transaction above is marked by following
(s_st_enum1_vector (lowb+1),
s_st_enum1_vector (lowb+2),
s_st_enum1_vector (lowb+3)) <=
c_st_enum1_vector_1 (lowb+1 to lowb+3) after 40 ns ;
--
when 7
=> correct :=
s_st_enum1_vector (lowb+1 to lowb+3) =
c_st_enum1_vector_1 (lowb+1 to lowb+3) and
(savtime + 30 ns) = Std.Standard.Now ;
--
when 8
=> correct := correct and
s_st_enum1_vector (lowb+1 to lowb+3) =
c_st_enum1_vector_1 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00639" ,
"Inertial semantics check on a signal " &
"asg with slice name on LHS",
correct ) ;
--
when others
=>
test_report ( "ARCH00639" ,
"Inertial semantics check on a signal " &
"asg with slice name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_st_enum1_vector <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
wait until (not s_st_enum1_vector'Quiet) and
(savtime /= Std.Standard.Now) ;
--
end process P5 ;
--
PGEN_CHKP_5 :
process ( chk_st_enum1_vector )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P5" ,
"Inertial transactions entirely completed",
chk_st_enum1_vector = 8 ) ;
end if ;
end process PGEN_CHKP_5 ;
--
P6 :
process
variable correct : boolean ;
variable counter : integer := 0 ;
variable savtime : time ;
begin
case counter is
when 0
=> (s_st_integer_vector (lowb+1),
s_st_integer_vector (lowb+2),
s_st_integer_vector (lowb+3)) <=
c_st_integer_vector_2 (lowb+1 to lowb+3) after 10 ns,
c_st_integer_vector_1 (lowb+1 to lowb+3) after 20 ns ;
--
when 1
=> correct :=
s_st_integer_vector (lowb+1 to lowb+3) =
c_st_integer_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_integer_vector (lowb+1 to lowb+3) =
c_st_integer_vector_1 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00639.P6" ,
"Multi inertial transactions occurred on signal " &
"asg with slice name on LHS",
correct ) ;
(s_st_integer_vector (lowb+1),
s_st_integer_vector (lowb+2),
s_st_integer_vector (lowb+3)) <=
c_st_integer_vector_2 (lowb+1 to lowb+3) after 10 ns ,
c_st_integer_vector_1 (lowb+1 to lowb+3) after 20 ns ,
c_st_integer_vector_2 (lowb+1 to lowb+3) after 30 ns ,
c_st_integer_vector_1 (lowb+1 to lowb+3) after 40 ns ;
--
when 3
=> correct :=
s_st_integer_vector (lowb+1 to lowb+3) =
c_st_integer_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
(s_st_integer_vector (lowb+1),
s_st_integer_vector (lowb+2),
s_st_integer_vector (lowb+3)) <=
c_st_integer_vector_1 (lowb+1 to lowb+3) after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_integer_vector (lowb+1 to lowb+3) =
c_st_integer_vector_1 (lowb+1 to lowb+3) and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00639" ,
"One inertial transaction occurred on signal " &
"asg with slice name on LHS",
correct ) ;
(s_st_integer_vector (lowb+1),
s_st_integer_vector (lowb+2),
s_st_integer_vector (lowb+3)) <= transport
c_st_integer_vector_1 (lowb+1 to lowb+3) after 100 ns ;
--
when 5
=> correct :=
s_st_integer_vector (lowb+1 to lowb+3) =
c_st_integer_vector_1 (lowb+1 to lowb+3) and
(savtime + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00639" ,
"Old transactions were removed on signal " &
"asg with slice name on LHS",
correct ) ;
(s_st_integer_vector (lowb+1),
s_st_integer_vector (lowb+2),
s_st_integer_vector (lowb+3)) <=
c_st_integer_vector_2 (lowb+1 to lowb+3) after 10 ns ,
c_st_integer_vector_1 (lowb+1 to lowb+3) after 20 ns ,
c_st_integer_vector_2 (lowb+1 to lowb+3) after 30 ns ,
c_st_integer_vector_1 (lowb+1 to lowb+3) after 40 ns ;
--
when 6
=> correct :=
s_st_integer_vector (lowb+1 to lowb+3) =
c_st_integer_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00639" ,
"One inertial transaction occurred on signal " &
"asg with slice name on LHS",
correct ) ;
-- Last transaction above is marked by following
(s_st_integer_vector (lowb+1),
s_st_integer_vector (lowb+2),
s_st_integer_vector (lowb+3)) <=
c_st_integer_vector_1 (lowb+1 to lowb+3) after 40 ns ;
--
when 7
=> correct :=
s_st_integer_vector (lowb+1 to lowb+3) =
c_st_integer_vector_1 (lowb+1 to lowb+3) and
(savtime + 30 ns) = Std.Standard.Now ;
--
when 8
=> correct := correct and
s_st_integer_vector (lowb+1 to lowb+3) =
c_st_integer_vector_1 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00639" ,
"Inertial semantics check on a signal " &
"asg with slice name on LHS",
correct ) ;
--
when others
=>
test_report ( "ARCH00639" ,
"Inertial semantics check on a signal " &
"asg with slice name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_st_integer_vector <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
wait until (not s_st_integer_vector'Quiet) and
(savtime /= Std.Standard.Now) ;
--
end process P6 ;
--
PGEN_CHKP_6 :
process ( chk_st_integer_vector )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P6" ,
"Inertial transactions entirely completed",
chk_st_integer_vector = 8 ) ;
end if ;
end process PGEN_CHKP_6 ;
--
P7 :
process
variable correct : boolean ;
variable counter : integer := 0 ;
variable savtime : time ;
begin
case counter is
when 0
=> (s_st_int1_vector (lowb+1),
s_st_int1_vector (lowb+2),
s_st_int1_vector (lowb+3)) <=
c_st_int1_vector_2 (lowb+1 to lowb+3) after 10 ns,
c_st_int1_vector_1 (lowb+1 to lowb+3) after 20 ns ;
--
when 1
=> correct :=
s_st_int1_vector (lowb+1 to lowb+3) =
c_st_int1_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_int1_vector (lowb+1 to lowb+3) =
c_st_int1_vector_1 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00639.P7" ,
"Multi inertial transactions occurred on signal " &
"asg with slice name on LHS",
correct ) ;
(s_st_int1_vector (lowb+1),
s_st_int1_vector (lowb+2),
s_st_int1_vector (lowb+3)) <=
c_st_int1_vector_2 (lowb+1 to lowb+3) after 10 ns ,
c_st_int1_vector_1 (lowb+1 to lowb+3) after 20 ns ,
c_st_int1_vector_2 (lowb+1 to lowb+3) after 30 ns ,
c_st_int1_vector_1 (lowb+1 to lowb+3) after 40 ns ;
--
when 3
=> correct :=
s_st_int1_vector (lowb+1 to lowb+3) =
c_st_int1_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
(s_st_int1_vector (lowb+1),
s_st_int1_vector (lowb+2),
s_st_int1_vector (lowb+3)) <=
c_st_int1_vector_1 (lowb+1 to lowb+3) after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_int1_vector (lowb+1 to lowb+3) =
c_st_int1_vector_1 (lowb+1 to lowb+3) and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00639" ,
"One inertial transaction occurred on signal " &
"asg with slice name on LHS",
correct ) ;
(s_st_int1_vector (lowb+1),
s_st_int1_vector (lowb+2),
s_st_int1_vector (lowb+3)) <= transport
c_st_int1_vector_1 (lowb+1 to lowb+3) after 100 ns ;
--
when 5
=> correct :=
s_st_int1_vector (lowb+1 to lowb+3) =
c_st_int1_vector_1 (lowb+1 to lowb+3) and
(savtime + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00639" ,
"Old transactions were removed on signal " &
"asg with slice name on LHS",
correct ) ;
(s_st_int1_vector (lowb+1),
s_st_int1_vector (lowb+2),
s_st_int1_vector (lowb+3)) <=
c_st_int1_vector_2 (lowb+1 to lowb+3) after 10 ns ,
c_st_int1_vector_1 (lowb+1 to lowb+3) after 20 ns ,
c_st_int1_vector_2 (lowb+1 to lowb+3) after 30 ns ,
c_st_int1_vector_1 (lowb+1 to lowb+3) after 40 ns ;
--
when 6
=> correct :=
s_st_int1_vector (lowb+1 to lowb+3) =
c_st_int1_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00639" ,
"One inertial transaction occurred on signal " &
"asg with slice name on LHS",
correct ) ;
-- Last transaction above is marked by following
(s_st_int1_vector (lowb+1),
s_st_int1_vector (lowb+2),
s_st_int1_vector (lowb+3)) <=
c_st_int1_vector_1 (lowb+1 to lowb+3) after 40 ns ;
--
when 7
=> correct :=
s_st_int1_vector (lowb+1 to lowb+3) =
c_st_int1_vector_1 (lowb+1 to lowb+3) and
(savtime + 30 ns) = Std.Standard.Now ;
--
when 8
=> correct := correct and
s_st_int1_vector (lowb+1 to lowb+3) =
c_st_int1_vector_1 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00639" ,
"Inertial semantics check on a signal " &
"asg with slice name on LHS",
correct ) ;
--
when others
=>
test_report ( "ARCH00639" ,
"Inertial semantics check on a signal " &
"asg with slice name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_st_int1_vector <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
wait until (not s_st_int1_vector'Quiet) and
(savtime /= Std.Standard.Now) ;
--
end process P7 ;
--
PGEN_CHKP_7 :
process ( chk_st_int1_vector )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P7" ,
"Inertial transactions entirely completed",
chk_st_int1_vector = 8 ) ;
end if ;
end process PGEN_CHKP_7 ;
--
P8 :
process
variable correct : boolean ;
variable counter : integer := 0 ;
variable savtime : time ;
begin
case counter is
when 0
=> (s_st_time_vector (lowb+1),
s_st_time_vector (lowb+2),
s_st_time_vector (lowb+3)) <=
c_st_time_vector_2 (lowb+1 to lowb+3) after 10 ns,
c_st_time_vector_1 (lowb+1 to lowb+3) after 20 ns ;
--
when 1
=> correct :=
s_st_time_vector (lowb+1 to lowb+3) =
c_st_time_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_time_vector (lowb+1 to lowb+3) =
c_st_time_vector_1 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00639.P8" ,
"Multi inertial transactions occurred on signal " &
"asg with slice name on LHS",
correct ) ;
(s_st_time_vector (lowb+1),
s_st_time_vector (lowb+2),
s_st_time_vector (lowb+3)) <=
c_st_time_vector_2 (lowb+1 to lowb+3) after 10 ns ,
c_st_time_vector_1 (lowb+1 to lowb+3) after 20 ns ,
c_st_time_vector_2 (lowb+1 to lowb+3) after 30 ns ,
c_st_time_vector_1 (lowb+1 to lowb+3) after 40 ns ;
--
when 3
=> correct :=
s_st_time_vector (lowb+1 to lowb+3) =
c_st_time_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
(s_st_time_vector (lowb+1),
s_st_time_vector (lowb+2),
s_st_time_vector (lowb+3)) <=
c_st_time_vector_1 (lowb+1 to lowb+3) after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_time_vector (lowb+1 to lowb+3) =
c_st_time_vector_1 (lowb+1 to lowb+3) and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00639" ,
"One inertial transaction occurred on signal " &
"asg with slice name on LHS",
correct ) ;
(s_st_time_vector (lowb+1),
s_st_time_vector (lowb+2),
s_st_time_vector (lowb+3)) <= transport
c_st_time_vector_1 (lowb+1 to lowb+3) after 100 ns ;
--
when 5
=> correct :=
s_st_time_vector (lowb+1 to lowb+3) =
c_st_time_vector_1 (lowb+1 to lowb+3) and
(savtime + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00639" ,
"Old transactions were removed on signal " &
"asg with slice name on LHS",
correct ) ;
(s_st_time_vector (lowb+1),
s_st_time_vector (lowb+2),
s_st_time_vector (lowb+3)) <=
c_st_time_vector_2 (lowb+1 to lowb+3) after 10 ns ,
c_st_time_vector_1 (lowb+1 to lowb+3) after 20 ns ,
c_st_time_vector_2 (lowb+1 to lowb+3) after 30 ns ,
c_st_time_vector_1 (lowb+1 to lowb+3) after 40 ns ;
--
when 6
=> correct :=
s_st_time_vector (lowb+1 to lowb+3) =
c_st_time_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00639" ,
"One inertial transaction occurred on signal " &
"asg with slice name on LHS",
correct ) ;
-- Last transaction above is marked by following
(s_st_time_vector (lowb+1),
s_st_time_vector (lowb+2),
s_st_time_vector (lowb+3)) <=
c_st_time_vector_1 (lowb+1 to lowb+3) after 40 ns ;
--
when 7
=> correct :=
s_st_time_vector (lowb+1 to lowb+3) =
c_st_time_vector_1 (lowb+1 to lowb+3) and
(savtime + 30 ns) = Std.Standard.Now ;
--
when 8
=> correct := correct and
s_st_time_vector (lowb+1 to lowb+3) =
c_st_time_vector_1 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00639" ,
"Inertial semantics check on a signal " &
"asg with slice name on LHS",
correct ) ;
--
when others
=>
test_report ( "ARCH00639" ,
"Inertial semantics check on a signal " &
"asg with slice name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_st_time_vector <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
wait until (not s_st_time_vector'Quiet) and
(savtime /= Std.Standard.Now) ;
--
end process P8 ;
--
PGEN_CHKP_8 :
process ( chk_st_time_vector )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P8" ,
"Inertial transactions entirely completed",
chk_st_time_vector = 8 ) ;
end if ;
end process PGEN_CHKP_8 ;
--
P9 :
process
variable correct : boolean ;
variable counter : integer := 0 ;
variable savtime : time ;
begin
case counter is
when 0
=> (s_st_phys1_vector (lowb+1),
s_st_phys1_vector (lowb+2),
s_st_phys1_vector (lowb+3)) <=
c_st_phys1_vector_2 (lowb+1 to lowb+3) after 10 ns,
c_st_phys1_vector_1 (lowb+1 to lowb+3) after 20 ns ;
--
when 1
=> correct :=
s_st_phys1_vector (lowb+1 to lowb+3) =
c_st_phys1_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_phys1_vector (lowb+1 to lowb+3) =
c_st_phys1_vector_1 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00639.P9" ,
"Multi inertial transactions occurred on signal " &
"asg with slice name on LHS",
correct ) ;
(s_st_phys1_vector (lowb+1),
s_st_phys1_vector (lowb+2),
s_st_phys1_vector (lowb+3)) <=
c_st_phys1_vector_2 (lowb+1 to lowb+3) after 10 ns ,
c_st_phys1_vector_1 (lowb+1 to lowb+3) after 20 ns ,
c_st_phys1_vector_2 (lowb+1 to lowb+3) after 30 ns ,
c_st_phys1_vector_1 (lowb+1 to lowb+3) after 40 ns ;
--
when 3
=> correct :=
s_st_phys1_vector (lowb+1 to lowb+3) =
c_st_phys1_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
(s_st_phys1_vector (lowb+1),
s_st_phys1_vector (lowb+2),
s_st_phys1_vector (lowb+3)) <=
c_st_phys1_vector_1 (lowb+1 to lowb+3) after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_phys1_vector (lowb+1 to lowb+3) =
c_st_phys1_vector_1 (lowb+1 to lowb+3) and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00639" ,
"One inertial transaction occurred on signal " &
"asg with slice name on LHS",
correct ) ;
(s_st_phys1_vector (lowb+1),
s_st_phys1_vector (lowb+2),
s_st_phys1_vector (lowb+3)) <= transport
c_st_phys1_vector_1 (lowb+1 to lowb+3) after 100 ns ;
--
when 5
=> correct :=
s_st_phys1_vector (lowb+1 to lowb+3) =
c_st_phys1_vector_1 (lowb+1 to lowb+3) and
(savtime + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00639" ,
"Old transactions were removed on signal " &
"asg with slice name on LHS",
correct ) ;
(s_st_phys1_vector (lowb+1),
s_st_phys1_vector (lowb+2),
s_st_phys1_vector (lowb+3)) <=
c_st_phys1_vector_2 (lowb+1 to lowb+3) after 10 ns ,
c_st_phys1_vector_1 (lowb+1 to lowb+3) after 20 ns ,
c_st_phys1_vector_2 (lowb+1 to lowb+3) after 30 ns ,
c_st_phys1_vector_1 (lowb+1 to lowb+3) after 40 ns ;
--
when 6
=> correct :=
s_st_phys1_vector (lowb+1 to lowb+3) =
c_st_phys1_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00639" ,
"One inertial transaction occurred on signal " &
"asg with slice name on LHS",
correct ) ;
-- Last transaction above is marked by following
(s_st_phys1_vector (lowb+1),
s_st_phys1_vector (lowb+2),
s_st_phys1_vector (lowb+3)) <=
c_st_phys1_vector_1 (lowb+1 to lowb+3) after 40 ns ;
--
when 7
=> correct :=
s_st_phys1_vector (lowb+1 to lowb+3) =
c_st_phys1_vector_1 (lowb+1 to lowb+3) and
(savtime + 30 ns) = Std.Standard.Now ;
--
when 8
=> correct := correct and
s_st_phys1_vector (lowb+1 to lowb+3) =
c_st_phys1_vector_1 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00639" ,
"Inertial semantics check on a signal " &
"asg with slice name on LHS",
correct ) ;
--
when others
=>
test_report ( "ARCH00639" ,
"Inertial semantics check on a signal " &
"asg with slice name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_st_phys1_vector <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
wait until (not s_st_phys1_vector'Quiet) and
(savtime /= Std.Standard.Now) ;
--
end process P9 ;
--
PGEN_CHKP_9 :
process ( chk_st_phys1_vector )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P9" ,
"Inertial transactions entirely completed",
chk_st_phys1_vector = 8 ) ;
end if ;
end process PGEN_CHKP_9 ;
--
P10 :
process
variable correct : boolean ;
variable counter : integer := 0 ;
variable savtime : time ;
begin
case counter is
when 0
=> (s_st_real_vector (lowb+1),
s_st_real_vector (lowb+2),
s_st_real_vector (lowb+3)) <=
c_st_real_vector_2 (lowb+1 to lowb+3) after 10 ns,
c_st_real_vector_1 (lowb+1 to lowb+3) after 20 ns ;
--
when 1
=> correct :=
s_st_real_vector (lowb+1 to lowb+3) =
c_st_real_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_real_vector (lowb+1 to lowb+3) =
c_st_real_vector_1 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00639.P10" ,
"Multi inertial transactions occurred on signal " &
"asg with slice name on LHS",
correct ) ;
(s_st_real_vector (lowb+1),
s_st_real_vector (lowb+2),
s_st_real_vector (lowb+3)) <=
c_st_real_vector_2 (lowb+1 to lowb+3) after 10 ns ,
c_st_real_vector_1 (lowb+1 to lowb+3) after 20 ns ,
c_st_real_vector_2 (lowb+1 to lowb+3) after 30 ns ,
c_st_real_vector_1 (lowb+1 to lowb+3) after 40 ns ;
--
when 3
=> correct :=
s_st_real_vector (lowb+1 to lowb+3) =
c_st_real_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
(s_st_real_vector (lowb+1),
s_st_real_vector (lowb+2),
s_st_real_vector (lowb+3)) <=
c_st_real_vector_1 (lowb+1 to lowb+3) after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_real_vector (lowb+1 to lowb+3) =
c_st_real_vector_1 (lowb+1 to lowb+3) and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00639" ,
"One inertial transaction occurred on signal " &
"asg with slice name on LHS",
correct ) ;
(s_st_real_vector (lowb+1),
s_st_real_vector (lowb+2),
s_st_real_vector (lowb+3)) <= transport
c_st_real_vector_1 (lowb+1 to lowb+3) after 100 ns ;
--
when 5
=> correct :=
s_st_real_vector (lowb+1 to lowb+3) =
c_st_real_vector_1 (lowb+1 to lowb+3) and
(savtime + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00639" ,
"Old transactions were removed on signal " &
"asg with slice name on LHS",
correct ) ;
(s_st_real_vector (lowb+1),
s_st_real_vector (lowb+2),
s_st_real_vector (lowb+3)) <=
c_st_real_vector_2 (lowb+1 to lowb+3) after 10 ns ,
c_st_real_vector_1 (lowb+1 to lowb+3) after 20 ns ,
c_st_real_vector_2 (lowb+1 to lowb+3) after 30 ns ,
c_st_real_vector_1 (lowb+1 to lowb+3) after 40 ns ;
--
when 6
=> correct :=
s_st_real_vector (lowb+1 to lowb+3) =
c_st_real_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00639" ,
"One inertial transaction occurred on signal " &
"asg with slice name on LHS",
correct ) ;
-- Last transaction above is marked by following
(s_st_real_vector (lowb+1),
s_st_real_vector (lowb+2),
s_st_real_vector (lowb+3)) <=
c_st_real_vector_1 (lowb+1 to lowb+3) after 40 ns ;
--
when 7
=> correct :=
s_st_real_vector (lowb+1 to lowb+3) =
c_st_real_vector_1 (lowb+1 to lowb+3) and
(savtime + 30 ns) = Std.Standard.Now ;
--
when 8
=> correct := correct and
s_st_real_vector (lowb+1 to lowb+3) =
c_st_real_vector_1 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00639" ,
"Inertial semantics check on a signal " &
"asg with slice name on LHS",
correct ) ;
--
when others
=>
test_report ( "ARCH00639" ,
"Inertial semantics check on a signal " &
"asg with slice name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_st_real_vector <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
wait until (not s_st_real_vector'Quiet) and
(savtime /= Std.Standard.Now) ;
--
end process P10 ;
--
PGEN_CHKP_10 :
process ( chk_st_real_vector )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P10" ,
"Inertial transactions entirely completed",
chk_st_real_vector = 8 ) ;
end if ;
end process PGEN_CHKP_10 ;
--
P11 :
process
variable correct : boolean ;
variable counter : integer := 0 ;
variable savtime : time ;
begin
case counter is
when 0
=> (s_st_real1_vector (lowb+1),
s_st_real1_vector (lowb+2),
s_st_real1_vector (lowb+3)) <=
c_st_real1_vector_2 (lowb+1 to lowb+3) after 10 ns,
c_st_real1_vector_1 (lowb+1 to lowb+3) after 20 ns ;
--
when 1
=> correct :=
s_st_real1_vector (lowb+1 to lowb+3) =
c_st_real1_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_real1_vector (lowb+1 to lowb+3) =
c_st_real1_vector_1 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00639.P11" ,
"Multi inertial transactions occurred on signal " &
"asg with slice name on LHS",
correct ) ;
(s_st_real1_vector (lowb+1),
s_st_real1_vector (lowb+2),
s_st_real1_vector (lowb+3)) <=
c_st_real1_vector_2 (lowb+1 to lowb+3) after 10 ns ,
c_st_real1_vector_1 (lowb+1 to lowb+3) after 20 ns ,
c_st_real1_vector_2 (lowb+1 to lowb+3) after 30 ns ,
c_st_real1_vector_1 (lowb+1 to lowb+3) after 40 ns ;
--
when 3
=> correct :=
s_st_real1_vector (lowb+1 to lowb+3) =
c_st_real1_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
(s_st_real1_vector (lowb+1),
s_st_real1_vector (lowb+2),
s_st_real1_vector (lowb+3)) <=
c_st_real1_vector_1 (lowb+1 to lowb+3) after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_real1_vector (lowb+1 to lowb+3) =
c_st_real1_vector_1 (lowb+1 to lowb+3) and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00639" ,
"One inertial transaction occurred on signal " &
"asg with slice name on LHS",
correct ) ;
(s_st_real1_vector (lowb+1),
s_st_real1_vector (lowb+2),
s_st_real1_vector (lowb+3)) <= transport
c_st_real1_vector_1 (lowb+1 to lowb+3) after 100 ns ;
--
when 5
=> correct :=
s_st_real1_vector (lowb+1 to lowb+3) =
c_st_real1_vector_1 (lowb+1 to lowb+3) and
(savtime + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00639" ,
"Old transactions were removed on signal " &
"asg with slice name on LHS",
correct ) ;
(s_st_real1_vector (lowb+1),
s_st_real1_vector (lowb+2),
s_st_real1_vector (lowb+3)) <=
c_st_real1_vector_2 (lowb+1 to lowb+3) after 10 ns ,
c_st_real1_vector_1 (lowb+1 to lowb+3) after 20 ns ,
c_st_real1_vector_2 (lowb+1 to lowb+3) after 30 ns ,
c_st_real1_vector_1 (lowb+1 to lowb+3) after 40 ns ;
--
when 6
=> correct :=
s_st_real1_vector (lowb+1 to lowb+3) =
c_st_real1_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00639" ,
"One inertial transaction occurred on signal " &
"asg with slice name on LHS",
correct ) ;
-- Last transaction above is marked by following
(s_st_real1_vector (lowb+1),
s_st_real1_vector (lowb+2),
s_st_real1_vector (lowb+3)) <=
c_st_real1_vector_1 (lowb+1 to lowb+3) after 40 ns ;
--
when 7
=> correct :=
s_st_real1_vector (lowb+1 to lowb+3) =
c_st_real1_vector_1 (lowb+1 to lowb+3) and
(savtime + 30 ns) = Std.Standard.Now ;
--
when 8
=> correct := correct and
s_st_real1_vector (lowb+1 to lowb+3) =
c_st_real1_vector_1 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00639" ,
"Inertial semantics check on a signal " &
"asg with slice name on LHS",
correct ) ;
--
when others
=>
test_report ( "ARCH00639" ,
"Inertial semantics check on a signal " &
"asg with slice name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_st_real1_vector <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
wait until (not s_st_real1_vector'Quiet) and
(savtime /= Std.Standard.Now) ;
--
end process P11 ;
--
PGEN_CHKP_11 :
process ( chk_st_real1_vector )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P11" ,
"Inertial transactions entirely completed",
chk_st_real1_vector = 8 ) ;
end if ;
end process PGEN_CHKP_11 ;
--
P12 :
process
variable correct : boolean ;
variable counter : integer := 0 ;
variable savtime : time ;
begin
case counter is
when 0
=> (s_st_rec1_vector (lowb+1),
s_st_rec1_vector (lowb+2),
s_st_rec1_vector (lowb+3)) <=
c_st_rec1_vector_2 (lowb+1 to lowb+3) after 10 ns,
c_st_rec1_vector_1 (lowb+1 to lowb+3) after 20 ns ;
--
when 1
=> correct :=
s_st_rec1_vector (lowb+1 to lowb+3) =
c_st_rec1_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_rec1_vector (lowb+1 to lowb+3) =
c_st_rec1_vector_1 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00639.P12" ,
"Multi inertial transactions occurred on signal " &
"asg with slice name on LHS",
correct ) ;
(s_st_rec1_vector (lowb+1),
s_st_rec1_vector (lowb+2),
s_st_rec1_vector (lowb+3)) <=
c_st_rec1_vector_2 (lowb+1 to lowb+3) after 10 ns ,
c_st_rec1_vector_1 (lowb+1 to lowb+3) after 20 ns ,
c_st_rec1_vector_2 (lowb+1 to lowb+3) after 30 ns ,
c_st_rec1_vector_1 (lowb+1 to lowb+3) after 40 ns ;
--
when 3
=> correct :=
s_st_rec1_vector (lowb+1 to lowb+3) =
c_st_rec1_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
(s_st_rec1_vector (lowb+1),
s_st_rec1_vector (lowb+2),
s_st_rec1_vector (lowb+3)) <=
c_st_rec1_vector_1 (lowb+1 to lowb+3) after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_rec1_vector (lowb+1 to lowb+3) =
c_st_rec1_vector_1 (lowb+1 to lowb+3) and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00639" ,
"One inertial transaction occurred on signal " &
"asg with slice name on LHS",
correct ) ;
(s_st_rec1_vector (lowb+1),
s_st_rec1_vector (lowb+2),
s_st_rec1_vector (lowb+3)) <= transport
c_st_rec1_vector_1 (lowb+1 to lowb+3) after 100 ns ;
--
when 5
=> correct :=
s_st_rec1_vector (lowb+1 to lowb+3) =
c_st_rec1_vector_1 (lowb+1 to lowb+3) and
(savtime + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00639" ,
"Old transactions were removed on signal " &
"asg with slice name on LHS",
correct ) ;
(s_st_rec1_vector (lowb+1),
s_st_rec1_vector (lowb+2),
s_st_rec1_vector (lowb+3)) <=
c_st_rec1_vector_2 (lowb+1 to lowb+3) after 10 ns ,
c_st_rec1_vector_1 (lowb+1 to lowb+3) after 20 ns ,
c_st_rec1_vector_2 (lowb+1 to lowb+3) after 30 ns ,
c_st_rec1_vector_1 (lowb+1 to lowb+3) after 40 ns ;
--
when 6
=> correct :=
s_st_rec1_vector (lowb+1 to lowb+3) =
c_st_rec1_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00639" ,
"One inertial transaction occurred on signal " &
"asg with slice name on LHS",
correct ) ;
-- Last transaction above is marked by following
(s_st_rec1_vector (lowb+1),
s_st_rec1_vector (lowb+2),
s_st_rec1_vector (lowb+3)) <=
c_st_rec1_vector_1 (lowb+1 to lowb+3) after 40 ns ;
--
when 7
=> correct :=
s_st_rec1_vector (lowb+1 to lowb+3) =
c_st_rec1_vector_1 (lowb+1 to lowb+3) and
(savtime + 30 ns) = Std.Standard.Now ;
--
when 8
=> correct := correct and
s_st_rec1_vector (lowb+1 to lowb+3) =
c_st_rec1_vector_1 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00639" ,
"Inertial semantics check on a signal " &
"asg with slice name on LHS",
correct ) ;
--
when others
=>
test_report ( "ARCH00639" ,
"Inertial semantics check on a signal " &
"asg with slice name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_st_rec1_vector <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
wait until (not s_st_rec1_vector'Quiet) and
(savtime /= Std.Standard.Now) ;
--
end process P12 ;
--
PGEN_CHKP_12 :
process ( chk_st_rec1_vector )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P12" ,
"Inertial transactions entirely completed",
chk_st_rec1_vector = 8 ) ;
end if ;
end process PGEN_CHKP_12 ;
--
P13 :
process
variable correct : boolean ;
variable counter : integer := 0 ;
variable savtime : time ;
begin
case counter is
when 0
=> (s_st_rec2_vector (lowb+1),
s_st_rec2_vector (lowb+2),
s_st_rec2_vector (lowb+3)) <=
c_st_rec2_vector_2 (lowb+1 to lowb+3) after 10 ns,
c_st_rec2_vector_1 (lowb+1 to lowb+3) after 20 ns ;
--
when 1
=> correct :=
s_st_rec2_vector (lowb+1 to lowb+3) =
c_st_rec2_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_rec2_vector (lowb+1 to lowb+3) =
c_st_rec2_vector_1 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00639.P13" ,
"Multi inertial transactions occurred on signal " &
"asg with slice name on LHS",
correct ) ;
(s_st_rec2_vector (lowb+1),
s_st_rec2_vector (lowb+2),
s_st_rec2_vector (lowb+3)) <=
c_st_rec2_vector_2 (lowb+1 to lowb+3) after 10 ns ,
c_st_rec2_vector_1 (lowb+1 to lowb+3) after 20 ns ,
c_st_rec2_vector_2 (lowb+1 to lowb+3) after 30 ns ,
c_st_rec2_vector_1 (lowb+1 to lowb+3) after 40 ns ;
--
when 3
=> correct :=
s_st_rec2_vector (lowb+1 to lowb+3) =
c_st_rec2_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
(s_st_rec2_vector (lowb+1),
s_st_rec2_vector (lowb+2),
s_st_rec2_vector (lowb+3)) <=
c_st_rec2_vector_1 (lowb+1 to lowb+3) after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_rec2_vector (lowb+1 to lowb+3) =
c_st_rec2_vector_1 (lowb+1 to lowb+3) and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00639" ,
"One inertial transaction occurred on signal " &
"asg with slice name on LHS",
correct ) ;
(s_st_rec2_vector (lowb+1),
s_st_rec2_vector (lowb+2),
s_st_rec2_vector (lowb+3)) <= transport
c_st_rec2_vector_1 (lowb+1 to lowb+3) after 100 ns ;
--
when 5
=> correct :=
s_st_rec2_vector (lowb+1 to lowb+3) =
c_st_rec2_vector_1 (lowb+1 to lowb+3) and
(savtime + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00639" ,
"Old transactions were removed on signal " &
"asg with slice name on LHS",
correct ) ;
(s_st_rec2_vector (lowb+1),
s_st_rec2_vector (lowb+2),
s_st_rec2_vector (lowb+3)) <=
c_st_rec2_vector_2 (lowb+1 to lowb+3) after 10 ns ,
c_st_rec2_vector_1 (lowb+1 to lowb+3) after 20 ns ,
c_st_rec2_vector_2 (lowb+1 to lowb+3) after 30 ns ,
c_st_rec2_vector_1 (lowb+1 to lowb+3) after 40 ns ;
--
when 6
=> correct :=
s_st_rec2_vector (lowb+1 to lowb+3) =
c_st_rec2_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00639" ,
"One inertial transaction occurred on signal " &
"asg with slice name on LHS",
correct ) ;
-- Last transaction above is marked by following
(s_st_rec2_vector (lowb+1),
s_st_rec2_vector (lowb+2),
s_st_rec2_vector (lowb+3)) <=
c_st_rec2_vector_1 (lowb+1 to lowb+3) after 40 ns ;
--
when 7
=> correct :=
s_st_rec2_vector (lowb+1 to lowb+3) =
c_st_rec2_vector_1 (lowb+1 to lowb+3) and
(savtime + 30 ns) = Std.Standard.Now ;
--
when 8
=> correct := correct and
s_st_rec2_vector (lowb+1 to lowb+3) =
c_st_rec2_vector_1 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00639" ,
"Inertial semantics check on a signal " &
"asg with slice name on LHS",
correct ) ;
--
when others
=>
test_report ( "ARCH00639" ,
"Inertial semantics check on a signal " &
"asg with slice name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_st_rec2_vector <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
wait until (not s_st_rec2_vector'Quiet) and
(savtime /= Std.Standard.Now) ;
--
end process P13 ;
--
PGEN_CHKP_13 :
process ( chk_st_rec2_vector )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P13" ,
"Inertial transactions entirely completed",
chk_st_rec2_vector = 8 ) ;
end if ;
end process PGEN_CHKP_13 ;
--
P14 :
process
variable correct : boolean ;
variable counter : integer := 0 ;
variable savtime : time ;
begin
case counter is
when 0
=> (s_st_rec3_vector (lowb+1),
s_st_rec3_vector (lowb+2),
s_st_rec3_vector (lowb+3)) <=
c_st_rec3_vector_2 (lowb+1 to lowb+3) after 10 ns,
c_st_rec3_vector_1 (lowb+1 to lowb+3) after 20 ns ;
--
when 1
=> correct :=
s_st_rec3_vector (lowb+1 to lowb+3) =
c_st_rec3_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_rec3_vector (lowb+1 to lowb+3) =
c_st_rec3_vector_1 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00639.P14" ,
"Multi inertial transactions occurred on signal " &
"asg with slice name on LHS",
correct ) ;
(s_st_rec3_vector (lowb+1),
s_st_rec3_vector (lowb+2),
s_st_rec3_vector (lowb+3)) <=
c_st_rec3_vector_2 (lowb+1 to lowb+3) after 10 ns ,
c_st_rec3_vector_1 (lowb+1 to lowb+3) after 20 ns ,
c_st_rec3_vector_2 (lowb+1 to lowb+3) after 30 ns ,
c_st_rec3_vector_1 (lowb+1 to lowb+3) after 40 ns ;
--
when 3
=> correct :=
s_st_rec3_vector (lowb+1 to lowb+3) =
c_st_rec3_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
(s_st_rec3_vector (lowb+1),
s_st_rec3_vector (lowb+2),
s_st_rec3_vector (lowb+3)) <=
c_st_rec3_vector_1 (lowb+1 to lowb+3) after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_rec3_vector (lowb+1 to lowb+3) =
c_st_rec3_vector_1 (lowb+1 to lowb+3) and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00639" ,
"One inertial transaction occurred on signal " &
"asg with slice name on LHS",
correct ) ;
(s_st_rec3_vector (lowb+1),
s_st_rec3_vector (lowb+2),
s_st_rec3_vector (lowb+3)) <= transport
c_st_rec3_vector_1 (lowb+1 to lowb+3) after 100 ns ;
--
when 5
=> correct :=
s_st_rec3_vector (lowb+1 to lowb+3) =
c_st_rec3_vector_1 (lowb+1 to lowb+3) and
(savtime + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00639" ,
"Old transactions were removed on signal " &
"asg with slice name on LHS",
correct ) ;
(s_st_rec3_vector (lowb+1),
s_st_rec3_vector (lowb+2),
s_st_rec3_vector (lowb+3)) <=
c_st_rec3_vector_2 (lowb+1 to lowb+3) after 10 ns ,
c_st_rec3_vector_1 (lowb+1 to lowb+3) after 20 ns ,
c_st_rec3_vector_2 (lowb+1 to lowb+3) after 30 ns ,
c_st_rec3_vector_1 (lowb+1 to lowb+3) after 40 ns ;
--
when 6
=> correct :=
s_st_rec3_vector (lowb+1 to lowb+3) =
c_st_rec3_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00639" ,
"One inertial transaction occurred on signal " &
"asg with slice name on LHS",
correct ) ;
-- Last transaction above is marked by following
(s_st_rec3_vector (lowb+1),
s_st_rec3_vector (lowb+2),
s_st_rec3_vector (lowb+3)) <=
c_st_rec3_vector_1 (lowb+1 to lowb+3) after 40 ns ;
--
when 7
=> correct :=
s_st_rec3_vector (lowb+1 to lowb+3) =
c_st_rec3_vector_1 (lowb+1 to lowb+3) and
(savtime + 30 ns) = Std.Standard.Now ;
--
when 8
=> correct := correct and
s_st_rec3_vector (lowb+1 to lowb+3) =
c_st_rec3_vector_1 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00639" ,
"Inertial semantics check on a signal " &
"asg with slice name on LHS",
correct ) ;
--
when others
=>
test_report ( "ARCH00639" ,
"Inertial semantics check on a signal " &
"asg with slice name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_st_rec3_vector <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
wait until (not s_st_rec3_vector'Quiet) and
(savtime /= Std.Standard.Now) ;
--
end process P14 ;
--
PGEN_CHKP_14 :
process ( chk_st_rec3_vector )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P14" ,
"Inertial transactions entirely completed",
chk_st_rec3_vector = 8 ) ;
end if ;
end process PGEN_CHKP_14 ;
--
P15 :
process
variable correct : boolean ;
variable counter : integer := 0 ;
variable savtime : time ;
begin
case counter is
when 0
=> (s_st_arr1_vector (lowb+1),
s_st_arr1_vector (lowb+2),
s_st_arr1_vector (lowb+3)) <=
c_st_arr1_vector_2 (lowb+1 to lowb+3) after 10 ns,
c_st_arr1_vector_1 (lowb+1 to lowb+3) after 20 ns ;
--
when 1
=> correct :=
s_st_arr1_vector (lowb+1 to lowb+3) =
c_st_arr1_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_arr1_vector (lowb+1 to lowb+3) =
c_st_arr1_vector_1 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00639.P15" ,
"Multi inertial transactions occurred on signal " &
"asg with slice name on LHS",
correct ) ;
(s_st_arr1_vector (lowb+1),
s_st_arr1_vector (lowb+2),
s_st_arr1_vector (lowb+3)) <=
c_st_arr1_vector_2 (lowb+1 to lowb+3) after 10 ns ,
c_st_arr1_vector_1 (lowb+1 to lowb+3) after 20 ns ,
c_st_arr1_vector_2 (lowb+1 to lowb+3) after 30 ns ,
c_st_arr1_vector_1 (lowb+1 to lowb+3) after 40 ns ;
--
when 3
=> correct :=
s_st_arr1_vector (lowb+1 to lowb+3) =
c_st_arr1_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
(s_st_arr1_vector (lowb+1),
s_st_arr1_vector (lowb+2),
s_st_arr1_vector (lowb+3)) <=
c_st_arr1_vector_1 (lowb+1 to lowb+3) after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_arr1_vector (lowb+1 to lowb+3) =
c_st_arr1_vector_1 (lowb+1 to lowb+3) and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00639" ,
"One inertial transaction occurred on signal " &
"asg with slice name on LHS",
correct ) ;
(s_st_arr1_vector (lowb+1),
s_st_arr1_vector (lowb+2),
s_st_arr1_vector (lowb+3)) <= transport
c_st_arr1_vector_1 (lowb+1 to lowb+3) after 100 ns ;
--
when 5
=> correct :=
s_st_arr1_vector (lowb+1 to lowb+3) =
c_st_arr1_vector_1 (lowb+1 to lowb+3) and
(savtime + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00639" ,
"Old transactions were removed on signal " &
"asg with slice name on LHS",
correct ) ;
(s_st_arr1_vector (lowb+1),
s_st_arr1_vector (lowb+2),
s_st_arr1_vector (lowb+3)) <=
c_st_arr1_vector_2 (lowb+1 to lowb+3) after 10 ns ,
c_st_arr1_vector_1 (lowb+1 to lowb+3) after 20 ns ,
c_st_arr1_vector_2 (lowb+1 to lowb+3) after 30 ns ,
c_st_arr1_vector_1 (lowb+1 to lowb+3) after 40 ns ;
--
when 6
=> correct :=
s_st_arr1_vector (lowb+1 to lowb+3) =
c_st_arr1_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00639" ,
"One inertial transaction occurred on signal " &
"asg with slice name on LHS",
correct ) ;
-- Last transaction above is marked by following
(s_st_arr1_vector (lowb+1),
s_st_arr1_vector (lowb+2),
s_st_arr1_vector (lowb+3)) <=
c_st_arr1_vector_1 (lowb+1 to lowb+3) after 40 ns ;
--
when 7
=> correct :=
s_st_arr1_vector (lowb+1 to lowb+3) =
c_st_arr1_vector_1 (lowb+1 to lowb+3) and
(savtime + 30 ns) = Std.Standard.Now ;
--
when 8
=> correct := correct and
s_st_arr1_vector (lowb+1 to lowb+3) =
c_st_arr1_vector_1 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00639" ,
"Inertial semantics check on a signal " &
"asg with slice name on LHS",
correct ) ;
--
when others
=>
test_report ( "ARCH00639" ,
"Inertial semantics check on a signal " &
"asg with slice name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_st_arr1_vector <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
wait until (not s_st_arr1_vector'Quiet) and
(savtime /= Std.Standard.Now) ;
--
end process P15 ;
--
PGEN_CHKP_15 :
process ( chk_st_arr1_vector )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P15" ,
"Inertial transactions entirely completed",
chk_st_arr1_vector = 8 ) ;
end if ;
end process PGEN_CHKP_15 ;
--
P16 :
process
variable correct : boolean ;
variable counter : integer := 0 ;
variable savtime : time ;
begin
case counter is
when 0
=> (s_st_arr2_vector (lowb+1),
s_st_arr2_vector (lowb+2),
s_st_arr2_vector (lowb+3)) <=
c_st_arr2_vector_2 (lowb+1 to lowb+3) after 10 ns,
c_st_arr2_vector_1 (lowb+1 to lowb+3) after 20 ns ;
--
when 1
=> correct :=
s_st_arr2_vector (lowb+1 to lowb+3) =
c_st_arr2_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_arr2_vector (lowb+1 to lowb+3) =
c_st_arr2_vector_1 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00639.P16" ,
"Multi inertial transactions occurred on signal " &
"asg with slice name on LHS",
correct ) ;
(s_st_arr2_vector (lowb+1),
s_st_arr2_vector (lowb+2),
s_st_arr2_vector (lowb+3)) <=
c_st_arr2_vector_2 (lowb+1 to lowb+3) after 10 ns ,
c_st_arr2_vector_1 (lowb+1 to lowb+3) after 20 ns ,
c_st_arr2_vector_2 (lowb+1 to lowb+3) after 30 ns ,
c_st_arr2_vector_1 (lowb+1 to lowb+3) after 40 ns ;
--
when 3
=> correct :=
s_st_arr2_vector (lowb+1 to lowb+3) =
c_st_arr2_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
(s_st_arr2_vector (lowb+1),
s_st_arr2_vector (lowb+2),
s_st_arr2_vector (lowb+3)) <=
c_st_arr2_vector_1 (lowb+1 to lowb+3) after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_arr2_vector (lowb+1 to lowb+3) =
c_st_arr2_vector_1 (lowb+1 to lowb+3) and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00639" ,
"One inertial transaction occurred on signal " &
"asg with slice name on LHS",
correct ) ;
(s_st_arr2_vector (lowb+1),
s_st_arr2_vector (lowb+2),
s_st_arr2_vector (lowb+3)) <= transport
c_st_arr2_vector_1 (lowb+1 to lowb+3) after 100 ns ;
--
when 5
=> correct :=
s_st_arr2_vector (lowb+1 to lowb+3) =
c_st_arr2_vector_1 (lowb+1 to lowb+3) and
(savtime + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00639" ,
"Old transactions were removed on signal " &
"asg with slice name on LHS",
correct ) ;
(s_st_arr2_vector (lowb+1),
s_st_arr2_vector (lowb+2),
s_st_arr2_vector (lowb+3)) <=
c_st_arr2_vector_2 (lowb+1 to lowb+3) after 10 ns ,
c_st_arr2_vector_1 (lowb+1 to lowb+3) after 20 ns ,
c_st_arr2_vector_2 (lowb+1 to lowb+3) after 30 ns ,
c_st_arr2_vector_1 (lowb+1 to lowb+3) after 40 ns ;
--
when 6
=> correct :=
s_st_arr2_vector (lowb+1 to lowb+3) =
c_st_arr2_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00639" ,
"One inertial transaction occurred on signal " &
"asg with slice name on LHS",
correct ) ;
-- Last transaction above is marked by following
(s_st_arr2_vector (lowb+1),
s_st_arr2_vector (lowb+2),
s_st_arr2_vector (lowb+3)) <=
c_st_arr2_vector_1 (lowb+1 to lowb+3) after 40 ns ;
--
when 7
=> correct :=
s_st_arr2_vector (lowb+1 to lowb+3) =
c_st_arr2_vector_1 (lowb+1 to lowb+3) and
(savtime + 30 ns) = Std.Standard.Now ;
--
when 8
=> correct := correct and
s_st_arr2_vector (lowb+1 to lowb+3) =
c_st_arr2_vector_1 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00639" ,
"Inertial semantics check on a signal " &
"asg with slice name on LHS",
correct ) ;
--
when others
=>
test_report ( "ARCH00639" ,
"Inertial semantics check on a signal " &
"asg with slice name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_st_arr2_vector <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
wait until (not s_st_arr2_vector'Quiet) and
(savtime /= Std.Standard.Now) ;
--
end process P16 ;
--
PGEN_CHKP_16 :
process ( chk_st_arr2_vector )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P16" ,
"Inertial transactions entirely completed",
chk_st_arr2_vector = 8 ) ;
end if ;
end process PGEN_CHKP_16 ;
--
P17 :
process
variable correct : boolean ;
variable counter : integer := 0 ;
variable savtime : time ;
begin
case counter is
when 0
=> (s_st_arr3_vector (lowb+1),
s_st_arr3_vector (lowb+2),
s_st_arr3_vector (lowb+3)) <=
c_st_arr3_vector_2 (lowb+1 to lowb+3) after 10 ns,
c_st_arr3_vector_1 (lowb+1 to lowb+3) after 20 ns ;
--
when 1
=> correct :=
s_st_arr3_vector (lowb+1 to lowb+3) =
c_st_arr3_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_arr3_vector (lowb+1 to lowb+3) =
c_st_arr3_vector_1 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00639.P17" ,
"Multi inertial transactions occurred on signal " &
"asg with slice name on LHS",
correct ) ;
(s_st_arr3_vector (lowb+1),
s_st_arr3_vector (lowb+2),
s_st_arr3_vector (lowb+3)) <=
c_st_arr3_vector_2 (lowb+1 to lowb+3) after 10 ns ,
c_st_arr3_vector_1 (lowb+1 to lowb+3) after 20 ns ,
c_st_arr3_vector_2 (lowb+1 to lowb+3) after 30 ns ,
c_st_arr3_vector_1 (lowb+1 to lowb+3) after 40 ns ;
--
when 3
=> correct :=
s_st_arr3_vector (lowb+1 to lowb+3) =
c_st_arr3_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
(s_st_arr3_vector (lowb+1),
s_st_arr3_vector (lowb+2),
s_st_arr3_vector (lowb+3)) <=
c_st_arr3_vector_1 (lowb+1 to lowb+3) after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_arr3_vector (lowb+1 to lowb+3) =
c_st_arr3_vector_1 (lowb+1 to lowb+3) and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00639" ,
"One inertial transaction occurred on signal " &
"asg with slice name on LHS",
correct ) ;
(s_st_arr3_vector (lowb+1),
s_st_arr3_vector (lowb+2),
s_st_arr3_vector (lowb+3)) <= transport
c_st_arr3_vector_1 (lowb+1 to lowb+3) after 100 ns ;
--
when 5
=> correct :=
s_st_arr3_vector (lowb+1 to lowb+3) =
c_st_arr3_vector_1 (lowb+1 to lowb+3) and
(savtime + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00639" ,
"Old transactions were removed on signal " &
"asg with slice name on LHS",
correct ) ;
(s_st_arr3_vector (lowb+1),
s_st_arr3_vector (lowb+2),
s_st_arr3_vector (lowb+3)) <=
c_st_arr3_vector_2 (lowb+1 to lowb+3) after 10 ns ,
c_st_arr3_vector_1 (lowb+1 to lowb+3) after 20 ns ,
c_st_arr3_vector_2 (lowb+1 to lowb+3) after 30 ns ,
c_st_arr3_vector_1 (lowb+1 to lowb+3) after 40 ns ;
--
when 6
=> correct :=
s_st_arr3_vector (lowb+1 to lowb+3) =
c_st_arr3_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00639" ,
"One inertial transaction occurred on signal " &
"asg with slice name on LHS",
correct ) ;
-- Last transaction above is marked by following
(s_st_arr3_vector (lowb+1),
s_st_arr3_vector (lowb+2),
s_st_arr3_vector (lowb+3)) <=
c_st_arr3_vector_1 (lowb+1 to lowb+3) after 40 ns ;
--
when 7
=> correct :=
s_st_arr3_vector (lowb+1 to lowb+3) =
c_st_arr3_vector_1 (lowb+1 to lowb+3) and
(savtime + 30 ns) = Std.Standard.Now ;
--
when 8
=> correct := correct and
s_st_arr3_vector (lowb+1 to lowb+3) =
c_st_arr3_vector_1 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00639" ,
"Inertial semantics check on a signal " &
"asg with slice name on LHS",
correct ) ;
--
when others
=>
test_report ( "ARCH00639" ,
"Inertial semantics check on a signal " &
"asg with slice name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_st_arr3_vector <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
wait until (not s_st_arr3_vector'Quiet) and
(savtime /= Std.Standard.Now) ;
--
end process P17 ;
--
PGEN_CHKP_17 :
process ( chk_st_arr3_vector )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P17" ,
"Inertial transactions entirely completed",
chk_st_arr3_vector = 8 ) ;
end if ;
end process PGEN_CHKP_17 ;
--
--
end ARCH00639 ;
--
entity ENT00639_Test_Bench is
end ENT00639_Test_Bench ;
--
architecture ARCH00639_Test_Bench of ENT00639_Test_Bench is
begin
L1:
block
component UUT
end component ;
for CIS1 : UUT use entity WORK.E00000 ( ARCH00639 ) ;
begin
CIS1 : UUT ;
end block L1 ;
end ARCH00639_Test_Bench ;
| gpl-3.0 | 95299981d6a20782ce2cfaeabd51b54d | 0.48974 | 3.438523 | false | true | false | false |
jairov4/accel-oil | solution_virtex5_plb/syn/vhdl/nfa_accept_sample_multi.vhd | 1 | 673,159 | -- ==============================================================
-- RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2014.1
-- Copyright (C) 2014 Xilinx Inc. All rights reserved.
--
-- ===========================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity nfa_accept_sample_multi is
port (
ap_clk : IN STD_LOGIC;
ap_rst : IN STD_LOGIC;
ap_start : IN STD_LOGIC;
ap_done : OUT STD_LOGIC;
ap_idle : OUT STD_LOGIC;
ap_ready : OUT STD_LOGIC;
nfa_initials_buckets_req_din : OUT STD_LOGIC;
nfa_initials_buckets_req_full_n : IN STD_LOGIC;
nfa_initials_buckets_req_write : OUT STD_LOGIC;
nfa_initials_buckets_rsp_empty_n : IN STD_LOGIC;
nfa_initials_buckets_rsp_read : OUT STD_LOGIC;
nfa_initials_buckets_address : OUT STD_LOGIC_VECTOR (31 downto 0);
nfa_initials_buckets_datain : IN STD_LOGIC_VECTOR (63 downto 0);
nfa_initials_buckets_dataout : OUT STD_LOGIC_VECTOR (63 downto 0);
nfa_initials_buckets_size : OUT STD_LOGIC_VECTOR (31 downto 0);
nfa_finals_buckets_req_din : OUT STD_LOGIC;
nfa_finals_buckets_req_full_n : IN STD_LOGIC;
nfa_finals_buckets_req_write : OUT STD_LOGIC;
nfa_finals_buckets_rsp_empty_n : IN STD_LOGIC;
nfa_finals_buckets_rsp_read : OUT STD_LOGIC;
nfa_finals_buckets_address : OUT STD_LOGIC_VECTOR (31 downto 0);
nfa_finals_buckets_datain : IN STD_LOGIC_VECTOR (63 downto 0);
nfa_finals_buckets_dataout : OUT STD_LOGIC_VECTOR (63 downto 0);
nfa_finals_buckets_size : OUT STD_LOGIC_VECTOR (31 downto 0);
nfa_forward_buckets_req_din : OUT STD_LOGIC;
nfa_forward_buckets_req_full_n : IN STD_LOGIC;
nfa_forward_buckets_req_write : OUT STD_LOGIC;
nfa_forward_buckets_rsp_empty_n : IN STD_LOGIC;
nfa_forward_buckets_rsp_read : OUT STD_LOGIC;
nfa_forward_buckets_address : OUT STD_LOGIC_VECTOR (31 downto 0);
nfa_forward_buckets_datain : IN STD_LOGIC_VECTOR (31 downto 0);
nfa_forward_buckets_dataout : OUT STD_LOGIC_VECTOR (31 downto 0);
nfa_forward_buckets_size : OUT STD_LOGIC_VECTOR (31 downto 0);
nfa_symbols : IN STD_LOGIC_VECTOR (7 downto 0);
sample_req_din : OUT STD_LOGIC;
sample_req_full_n : IN STD_LOGIC;
sample_req_write : OUT STD_LOGIC;
sample_rsp_empty_n : IN STD_LOGIC;
sample_rsp_read : OUT STD_LOGIC;
sample_address : OUT STD_LOGIC_VECTOR (31 downto 0);
sample_datain : IN STD_LOGIC_VECTOR (7 downto 0);
sample_dataout : OUT STD_LOGIC_VECTOR (7 downto 0);
sample_size : OUT STD_LOGIC_VECTOR (31 downto 0);
length_r : IN STD_LOGIC_VECTOR (15 downto 0);
start_indices_address0 : OUT STD_LOGIC_VECTOR (3 downto 0);
start_indices_ce0 : OUT STD_LOGIC;
start_indices_q0 : IN STD_LOGIC_VECTOR (31 downto 0);
stop_on_first : IN STD_LOGIC_VECTOR (0 downto 0);
accept : IN STD_LOGIC_VECTOR (0 downto 0);
units : IN STD_LOGIC_VECTOR (4 downto 0);
result_address0 : OUT STD_LOGIC_VECTOR (3 downto 0);
result_ce0 : OUT STD_LOGIC;
result_we0 : OUT STD_LOGIC;
result_d0 : OUT STD_LOGIC_VECTOR (0 downto 0);
result_q0 : IN STD_LOGIC_VECTOR (0 downto 0);
ap_return : OUT STD_LOGIC_VECTOR (0 downto 0) );
end;
architecture behav of nfa_accept_sample_multi is
constant ap_const_logic_1 : STD_LOGIC := '1';
constant ap_const_logic_0 : STD_LOGIC := '0';
constant ap_ST_st1_fsm_0 : STD_LOGIC_VECTOR (5 downto 0) := "000000";
constant ap_ST_st2_fsm_1 : STD_LOGIC_VECTOR (5 downto 0) := "000001";
constant ap_ST_st3_fsm_2 : STD_LOGIC_VECTOR (5 downto 0) := "000010";
constant ap_ST_st4_fsm_3 : STD_LOGIC_VECTOR (5 downto 0) := "000011";
constant ap_ST_st5_fsm_4 : STD_LOGIC_VECTOR (5 downto 0) := "000100";
constant ap_ST_st6_fsm_5 : STD_LOGIC_VECTOR (5 downto 0) := "000101";
constant ap_ST_st7_fsm_6 : STD_LOGIC_VECTOR (5 downto 0) := "000110";
constant ap_ST_st8_fsm_7 : STD_LOGIC_VECTOR (5 downto 0) := "000111";
constant ap_ST_st9_fsm_8 : STD_LOGIC_VECTOR (5 downto 0) := "001000";
constant ap_ST_st10_fsm_9 : STD_LOGIC_VECTOR (5 downto 0) := "001001";
constant ap_ST_st11_fsm_10 : STD_LOGIC_VECTOR (5 downto 0) := "001010";
constant ap_ST_st12_fsm_11 : STD_LOGIC_VECTOR (5 downto 0) := "001011";
constant ap_ST_st13_fsm_12 : STD_LOGIC_VECTOR (5 downto 0) := "001100";
constant ap_ST_st14_fsm_13 : STD_LOGIC_VECTOR (5 downto 0) := "001101";
constant ap_ST_st15_fsm_14 : STD_LOGIC_VECTOR (5 downto 0) := "001110";
constant ap_ST_st16_fsm_15 : STD_LOGIC_VECTOR (5 downto 0) := "001111";
constant ap_ST_st17_fsm_16 : STD_LOGIC_VECTOR (5 downto 0) := "010000";
constant ap_ST_st18_fsm_17 : STD_LOGIC_VECTOR (5 downto 0) := "010001";
constant ap_ST_st19_fsm_18 : STD_LOGIC_VECTOR (5 downto 0) := "010010";
constant ap_ST_st20_fsm_19 : STD_LOGIC_VECTOR (5 downto 0) := "010011";
constant ap_ST_st21_fsm_20 : STD_LOGIC_VECTOR (5 downto 0) := "010100";
constant ap_ST_st22_fsm_21 : STD_LOGIC_VECTOR (5 downto 0) := "010101";
constant ap_ST_st23_fsm_22 : STD_LOGIC_VECTOR (5 downto 0) := "010110";
constant ap_ST_st24_fsm_23 : STD_LOGIC_VECTOR (5 downto 0) := "010111";
constant ap_ST_st25_fsm_24 : STD_LOGIC_VECTOR (5 downto 0) := "011000";
constant ap_ST_st26_fsm_25 : STD_LOGIC_VECTOR (5 downto 0) := "011001";
constant ap_ST_st27_fsm_26 : STD_LOGIC_VECTOR (5 downto 0) := "011010";
constant ap_ST_st28_fsm_27 : STD_LOGIC_VECTOR (5 downto 0) := "011011";
constant ap_ST_st29_fsm_28 : STD_LOGIC_VECTOR (5 downto 0) := "011100";
constant ap_ST_st30_fsm_29 : STD_LOGIC_VECTOR (5 downto 0) := "011101";
constant ap_ST_st31_fsm_30 : STD_LOGIC_VECTOR (5 downto 0) := "011110";
constant ap_ST_st32_fsm_31 : STD_LOGIC_VECTOR (5 downto 0) := "011111";
constant ap_ST_st33_fsm_32 : STD_LOGIC_VECTOR (5 downto 0) := "100000";
constant ap_ST_st34_fsm_33 : STD_LOGIC_VECTOR (5 downto 0) := "100001";
constant ap_ST_st35_fsm_34 : STD_LOGIC_VECTOR (5 downto 0) := "100010";
constant ap_ST_st36_fsm_35 : STD_LOGIC_VECTOR (5 downto 0) := "100011";
constant ap_ST_st37_fsm_36 : STD_LOGIC_VECTOR (5 downto 0) := "100100";
constant ap_ST_st38_fsm_37 : STD_LOGIC_VECTOR (5 downto 0) := "100101";
constant ap_ST_st39_fsm_38 : STD_LOGIC_VECTOR (5 downto 0) := "100110";
constant ap_ST_st40_fsm_39 : STD_LOGIC_VECTOR (5 downto 0) := "100111";
constant ap_ST_st41_fsm_40 : STD_LOGIC_VECTOR (5 downto 0) := "101000";
constant ap_ST_st42_fsm_41 : STD_LOGIC_VECTOR (5 downto 0) := "101001";
constant ap_ST_st43_fsm_42 : STD_LOGIC_VECTOR (5 downto 0) := "101010";
constant ap_ST_st44_fsm_43 : STD_LOGIC_VECTOR (5 downto 0) := "101011";
constant ap_ST_st45_fsm_44 : STD_LOGIC_VECTOR (5 downto 0) := "101100";
constant ap_ST_st46_fsm_45 : STD_LOGIC_VECTOR (5 downto 0) := "101101";
constant ap_ST_st47_fsm_46 : STD_LOGIC_VECTOR (5 downto 0) := "101110";
constant ap_ST_st48_fsm_47 : STD_LOGIC_VECTOR (5 downto 0) := "101111";
constant ap_const_lv1_0 : STD_LOGIC_VECTOR (0 downto 0) := "0";
constant ap_const_lv5_0 : STD_LOGIC_VECTOR (4 downto 0) := "00000";
constant ap_const_lv4_E : STD_LOGIC_VECTOR (3 downto 0) := "1110";
constant ap_const_lv4_D : STD_LOGIC_VECTOR (3 downto 0) := "1101";
constant ap_const_lv4_C : STD_LOGIC_VECTOR (3 downto 0) := "1100";
constant ap_const_lv4_B : STD_LOGIC_VECTOR (3 downto 0) := "1011";
constant ap_const_lv4_A : STD_LOGIC_VECTOR (3 downto 0) := "1010";
constant ap_const_lv4_9 : STD_LOGIC_VECTOR (3 downto 0) := "1001";
constant ap_const_lv4_8 : STD_LOGIC_VECTOR (3 downto 0) := "1000";
constant ap_const_lv4_7 : STD_LOGIC_VECTOR (3 downto 0) := "0111";
constant ap_const_lv4_6 : STD_LOGIC_VECTOR (3 downto 0) := "0110";
constant ap_const_lv4_5 : STD_LOGIC_VECTOR (3 downto 0) := "0101";
constant ap_const_lv4_4 : STD_LOGIC_VECTOR (3 downto 0) := "0100";
constant ap_const_lv4_3 : STD_LOGIC_VECTOR (3 downto 0) := "0011";
constant ap_const_lv4_2 : STD_LOGIC_VECTOR (3 downto 0) := "0010";
constant ap_const_lv4_1 : STD_LOGIC_VECTOR (3 downto 0) := "0001";
constant ap_const_lv4_0 : STD_LOGIC_VECTOR (3 downto 0) := "0000";
constant ap_const_lv1_1 : STD_LOGIC_VECTOR (0 downto 0) := "1";
constant ap_const_lv2_2 : STD_LOGIC_VECTOR (1 downto 0) := "10";
constant ap_const_lv32_0 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000000";
constant ap_const_lv32_1 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000001";
constant ap_const_lv64_0 : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000";
constant ap_const_lv32_20 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000100000";
constant ap_const_lv32_3F : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000111111";
constant ap_const_lv5_1 : STD_LOGIC_VECTOR (4 downto 0) := "00001";
constant ap_const_lv16_FFFF : STD_LOGIC_VECTOR (15 downto 0) := "1111111111111111";
constant ap_const_lv16_0 : STD_LOGIC_VECTOR (15 downto 0) := "0000000000000000";
constant ap_const_lv8_5 : STD_LOGIC_VECTOR (7 downto 0) := "00000101";
constant ap_const_lv8_0 : STD_LOGIC_VECTOR (7 downto 0) := "00000000";
constant ap_true : BOOLEAN := true;
signal ap_CS_fsm : STD_LOGIC_VECTOR (5 downto 0) := "000000";
signal k_4_fu_12996_p2 : STD_LOGIC_VECTOR (4 downto 0);
signal k_4_reg_13968 : STD_LOGIC_VECTOR (4 downto 0);
signal i_1_fu_13091_p2 : STD_LOGIC_VECTOR (15 downto 0);
signal i_1_reg_14270 : STD_LOGIC_VECTOR (15 downto 0);
signal j_15_bit_load_reg_14279 : STD_LOGIC_VECTOR (7 downto 0);
signal j_15_bit_1_load_reg_14284 : STD_LOGIC_VECTOR (7 downto 0);
signal j_15_bit_2_load_reg_14289 : STD_LOGIC_VECTOR (7 downto 0);
signal j_15_bit_3_load_reg_14294 : STD_LOGIC_VECTOR (7 downto 0);
signal j_15_bit_4_load_reg_14299 : STD_LOGIC_VECTOR (7 downto 0);
signal j_15_bit_5_load_reg_14304 : STD_LOGIC_VECTOR (7 downto 0);
signal j_15_bit_6_load_reg_14309 : STD_LOGIC_VECTOR (7 downto 0);
signal j_15_bit_7_load_reg_14314 : STD_LOGIC_VECTOR (7 downto 0);
signal j_15_bit_8_load_reg_14319 : STD_LOGIC_VECTOR (7 downto 0);
signal j_15_bit_9_load_reg_14324 : STD_LOGIC_VECTOR (7 downto 0);
signal j_15_bit_10_load_reg_14329 : STD_LOGIC_VECTOR (7 downto 0);
signal j_15_bit_11_load_reg_14334 : STD_LOGIC_VECTOR (7 downto 0);
signal j_15_bit_12_load_reg_14339 : STD_LOGIC_VECTOR (7 downto 0);
signal j_15_bit_13_load_reg_14344 : STD_LOGIC_VECTOR (7 downto 0);
signal j_15_bit_14_load_reg_14349 : STD_LOGIC_VECTOR (7 downto 0);
signal j_15_bit_15_load_reg_14354 : STD_LOGIC_VECTOR (7 downto 0);
signal j_bucket_index_0_load_reg_14359 : STD_LOGIC_VECTOR (7 downto 0);
signal j_bucket_index_1_load_reg_14364 : STD_LOGIC_VECTOR (7 downto 0);
signal j_bucket_index_2_load_reg_14369 : STD_LOGIC_VECTOR (7 downto 0);
signal j_bucket_index_3_load_reg_14374 : STD_LOGIC_VECTOR (7 downto 0);
signal j_bucket_index_4_load_reg_14379 : STD_LOGIC_VECTOR (7 downto 0);
signal j_bucket_index_5_load_reg_14384 : STD_LOGIC_VECTOR (7 downto 0);
signal j_bucket_index_6_load_reg_14389 : STD_LOGIC_VECTOR (7 downto 0);
signal j_bucket_index_7_load_reg_14394 : STD_LOGIC_VECTOR (7 downto 0);
signal j_bucket_index_8_load_reg_14399 : STD_LOGIC_VECTOR (7 downto 0);
signal j_bucket_index_9_load_reg_14404 : STD_LOGIC_VECTOR (7 downto 0);
signal j_bucket_index_10_load_reg_14409 : STD_LOGIC_VECTOR (7 downto 0);
signal j_bucket_index_11_load_reg_14414 : STD_LOGIC_VECTOR (7 downto 0);
signal j_bucket_index_12_load_reg_14419 : STD_LOGIC_VECTOR (7 downto 0);
signal j_bucket_index_13_load_reg_14424 : STD_LOGIC_VECTOR (7 downto 0);
signal j_bucket_index_14_load_reg_14429 : STD_LOGIC_VECTOR (7 downto 0);
signal j_bucket_index_15_load_reg_14434 : STD_LOGIC_VECTOR (7 downto 0);
signal j_15_end_load_reg_14439 : STD_LOGIC_VECTOR (0 downto 0);
signal j_15_end_1_load_reg_14444 : STD_LOGIC_VECTOR (0 downto 0);
signal j_15_end_2_load_reg_14449 : STD_LOGIC_VECTOR (0 downto 0);
signal j_15_end_3_load_reg_14454 : STD_LOGIC_VECTOR (0 downto 0);
signal j_15_end_4_load_reg_14459 : STD_LOGIC_VECTOR (0 downto 0);
signal j_15_end_5_load_reg_14464 : STD_LOGIC_VECTOR (0 downto 0);
signal j_15_end_6_load_reg_14469 : STD_LOGIC_VECTOR (0 downto 0);
signal j_15_end_7_load_reg_14474 : STD_LOGIC_VECTOR (0 downto 0);
signal j_15_end_8_load_reg_14479 : STD_LOGIC_VECTOR (0 downto 0);
signal j_15_end_9_load_reg_14484 : STD_LOGIC_VECTOR (0 downto 0);
signal j_15_end_10_load_reg_14489 : STD_LOGIC_VECTOR (0 downto 0);
signal j_15_end_11_load_reg_14494 : STD_LOGIC_VECTOR (0 downto 0);
signal j_15_end_12_load_reg_14499 : STD_LOGIC_VECTOR (0 downto 0);
signal j_15_end_13_load_reg_14504 : STD_LOGIC_VECTOR (0 downto 0);
signal j_15_end_14_load_reg_14509 : STD_LOGIC_VECTOR (0 downto 0);
signal j_15_end_15_load_reg_14514 : STD_LOGIC_VECTOR (0 downto 0);
signal k_5_fu_13252_p2 : STD_LOGIC_VECTOR (4 downto 0);
signal k_5_reg_14522 : STD_LOGIC_VECTOR (4 downto 0);
signal tmp_8_fu_13258_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_8_reg_14527 : STD_LOGIC_VECTOR (63 downto 0);
signal exitcond2_fu_13247_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_36_fu_13263_p1 : STD_LOGIC_VECTOR (3 downto 0);
signal tmp_36_reg_14538 : STD_LOGIC_VECTOR (3 downto 0);
signal tmp_7_fu_13267_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_7_reg_14542 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_39_fu_13272_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_13_fu_13282_p4 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_11_fu_13276_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal r_1_0_i_lcssa3_cast_fu_13298_p1 : STD_LOGIC_VECTOR (1 downto 0);
signal j_0_bucket_index_cast_fu_13311_p1 : STD_LOGIC_VECTOR (7 downto 0);
signal j_0_bucket_index_cast_reg_14592 : STD_LOGIC_VECTOR (7 downto 0);
signal k_7_fu_13544_p2 : STD_LOGIC_VECTOR (4 downto 0);
signal k_7_reg_14615 : STD_LOGIC_VECTOR (4 downto 0);
signal tmp_5_fu_13550_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_5_reg_14621 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_9_fu_13539_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_37_fu_13557_p1 : STD_LOGIC_VECTOR (3 downto 0);
signal tmp_37_reg_14631 : STD_LOGIC_VECTOR (3 downto 0);
signal next_buckets_addr_3_reg_14635 : STD_LOGIC_VECTOR (3 downto 0);
signal end_0_phi_fu_5844_p32 : STD_LOGIC_VECTOR (0 downto 0);
signal end_string_0_phi_fu_6831_p4 : STD_LOGIC_VECTOR (0 downto 0);
signal current_buckets_addr_1_reg_14640 : STD_LOGIC_VECTOR (3 downto 0);
signal state_0_fu_13574_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal next_buckets_addr_4_reg_14670 : STD_LOGIC_VECTOR (3 downto 0);
signal not_s_fu_13615_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal not_s_reg_14675 : STD_LOGIC_VECTOR (0 downto 0);
signal brmerge_demorgan_fu_13621_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal brmerge_demorgan_reg_14680 : STD_LOGIC_VECTOR (0 downto 0);
signal sym_offset_0_1_25_fu_13631_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal sample_addr_read_reg_14718 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_8_i1_fu_13669_p2 : STD_LOGIC_VECTOR (13 downto 0);
signal tmp_8_i1_reg_14723 : STD_LOGIC_VECTOR (13 downto 0);
signal nfa_forward_buckets_addr_read_reg_14735 : STD_LOGIC_VECTOR (31 downto 0);
signal nfa_forward_buckets_addr_1_read_reg_14746 : STD_LOGIC_VECTOR (31 downto 0);
signal k_6_fu_13723_p2 : STD_LOGIC_VECTOR (4 downto 0);
signal k_6_reg_14754 : STD_LOGIC_VECTOR (4 downto 0);
signal tmp_10_fu_13729_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_10_reg_14775 : STD_LOGIC_VECTOR (63 downto 0);
signal exitcond_fu_13718_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_38_fu_13733_p1 : STD_LOGIC_VECTOR (3 downto 0);
signal tmp_38_reg_14781 : STD_LOGIC_VECTOR (3 downto 0);
signal end_load_phi_phi_fu_12756_p32 : STD_LOGIC_VECTOR (0 downto 0);
signal next_buckets_addr_2_reg_14790 : STD_LOGIC_VECTOR (3 downto 0);
signal next_buckets_address0 : STD_LOGIC_VECTOR (3 downto 0);
signal next_buckets_ce0 : STD_LOGIC;
signal next_buckets_we0 : STD_LOGIC;
signal next_buckets_d0 : STD_LOGIC_VECTOR (63 downto 0);
signal next_buckets_q0 : STD_LOGIC_VECTOR (63 downto 0);
signal current_buckets_address0 : STD_LOGIC_VECTOR (3 downto 0);
signal current_buckets_ce0 : STD_LOGIC;
signal current_buckets_we0 : STD_LOGIC;
signal current_buckets_d0 : STD_LOGIC_VECTOR (63 downto 0);
signal current_buckets_q0 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_buckets_address0 : STD_LOGIC_VECTOR (3 downto 0);
signal tmp_buckets_ce0 : STD_LOGIC;
signal tmp_buckets_we0 : STD_LOGIC;
signal tmp_buckets_d0 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_buckets_q0 : STD_LOGIC_VECTOR (63 downto 0);
signal grp_nfa_get_initials_1_fu_12896_ap_start : STD_LOGIC;
signal grp_nfa_get_initials_1_fu_12896_ap_done : STD_LOGIC;
signal grp_nfa_get_initials_1_fu_12896_ap_idle : STD_LOGIC;
signal grp_nfa_get_initials_1_fu_12896_ap_ready : STD_LOGIC;
signal grp_nfa_get_initials_1_fu_12896_nfa_initials_buckets_req_din : STD_LOGIC;
signal grp_nfa_get_initials_1_fu_12896_nfa_initials_buckets_req_full_n : STD_LOGIC;
signal grp_nfa_get_initials_1_fu_12896_nfa_initials_buckets_req_write : STD_LOGIC;
signal grp_nfa_get_initials_1_fu_12896_nfa_initials_buckets_rsp_empty_n : STD_LOGIC;
signal grp_nfa_get_initials_1_fu_12896_nfa_initials_buckets_rsp_read : STD_LOGIC;
signal grp_nfa_get_initials_1_fu_12896_nfa_initials_buckets_address : STD_LOGIC_VECTOR (31 downto 0);
signal grp_nfa_get_initials_1_fu_12896_nfa_initials_buckets_datain : STD_LOGIC_VECTOR (63 downto 0);
signal grp_nfa_get_initials_1_fu_12896_nfa_initials_buckets_dataout : STD_LOGIC_VECTOR (63 downto 0);
signal grp_nfa_get_initials_1_fu_12896_nfa_initials_buckets_size : STD_LOGIC_VECTOR (31 downto 0);
signal grp_nfa_get_initials_1_fu_12896_ap_ce : STD_LOGIC;
signal grp_nfa_get_initials_1_fu_12896_initials_buckets_address0 : STD_LOGIC_VECTOR (3 downto 0);
signal grp_nfa_get_initials_1_fu_12896_initials_buckets_ce0 : STD_LOGIC;
signal grp_nfa_get_initials_1_fu_12896_initials_buckets_we0 : STD_LOGIC;
signal grp_nfa_get_initials_1_fu_12896_initials_buckets_d0 : STD_LOGIC_VECTOR (63 downto 0);
signal grp_nfa_get_initials_1_fu_12896_tmp_s : STD_LOGIC_VECTOR (4 downto 0);
signal grp_nfa_get_finals_1_fu_12905_ap_start : STD_LOGIC;
signal grp_nfa_get_finals_1_fu_12905_ap_done : STD_LOGIC;
signal grp_nfa_get_finals_1_fu_12905_ap_idle : STD_LOGIC;
signal grp_nfa_get_finals_1_fu_12905_ap_ready : STD_LOGIC;
signal grp_nfa_get_finals_1_fu_12905_nfa_finals_buckets_req_din : STD_LOGIC;
signal grp_nfa_get_finals_1_fu_12905_nfa_finals_buckets_req_full_n : STD_LOGIC;
signal grp_nfa_get_finals_1_fu_12905_nfa_finals_buckets_req_write : STD_LOGIC;
signal grp_nfa_get_finals_1_fu_12905_nfa_finals_buckets_rsp_empty_n : STD_LOGIC;
signal grp_nfa_get_finals_1_fu_12905_nfa_finals_buckets_rsp_read : STD_LOGIC;
signal grp_nfa_get_finals_1_fu_12905_nfa_finals_buckets_address : STD_LOGIC_VECTOR (31 downto 0);
signal grp_nfa_get_finals_1_fu_12905_nfa_finals_buckets_datain : STD_LOGIC_VECTOR (63 downto 0);
signal grp_nfa_get_finals_1_fu_12905_nfa_finals_buckets_dataout : STD_LOGIC_VECTOR (63 downto 0);
signal grp_nfa_get_finals_1_fu_12905_nfa_finals_buckets_size : STD_LOGIC_VECTOR (31 downto 0);
signal grp_nfa_get_finals_1_fu_12905_ap_ce : STD_LOGIC;
signal grp_nfa_get_finals_1_fu_12905_finals_buckets_address0 : STD_LOGIC_VECTOR (3 downto 0);
signal grp_nfa_get_finals_1_fu_12905_finals_buckets_ce0 : STD_LOGIC;
signal grp_nfa_get_finals_1_fu_12905_finals_buckets_we0 : STD_LOGIC;
signal grp_nfa_get_finals_1_fu_12905_finals_buckets_d0 : STD_LOGIC_VECTOR (63 downto 0);
signal grp_nfa_get_finals_1_fu_12905_tmp_28 : STD_LOGIC_VECTOR (4 downto 0);
signal r_bit_p_bsf32_hw_fu_12914_bus_r : STD_LOGIC_VECTOR (31 downto 0);
signal r_bit_p_bsf32_hw_fu_12914_ap_return : STD_LOGIC_VECTOR (5 downto 0);
signal k_reg_612 : STD_LOGIC_VECTOR (4 downto 0);
signal state_15_2_reg_4611 : STD_LOGIC_VECTOR (7 downto 0);
signal state_15_s_reg_624 : STD_LOGIC_VECTOR (7 downto 0);
signal all_end_phi_fu_12651_p36 : STD_LOGIC_VECTOR (0 downto 0);
signal state_14_2_reg_4626 : STD_LOGIC_VECTOR (7 downto 0);
signal state_14_s_reg_636 : STD_LOGIC_VECTOR (7 downto 0);
signal state_13_2_reg_4641 : STD_LOGIC_VECTOR (7 downto 0);
signal state_13_s_reg_648 : STD_LOGIC_VECTOR (7 downto 0);
signal state_12_2_reg_4656 : STD_LOGIC_VECTOR (7 downto 0);
signal state_12_s_reg_660 : STD_LOGIC_VECTOR (7 downto 0);
signal state_11_2_reg_4671 : STD_LOGIC_VECTOR (7 downto 0);
signal state_11_s_reg_672 : STD_LOGIC_VECTOR (7 downto 0);
signal state_10_2_reg_4686 : STD_LOGIC_VECTOR (7 downto 0);
signal state_10_s_reg_684 : STD_LOGIC_VECTOR (7 downto 0);
signal state_9_2_reg_4701 : STD_LOGIC_VECTOR (7 downto 0);
signal state_9_s_reg_696 : STD_LOGIC_VECTOR (7 downto 0);
signal state_8_2_reg_4716 : STD_LOGIC_VECTOR (7 downto 0);
signal state_8_s_reg_708 : STD_LOGIC_VECTOR (7 downto 0);
signal state_7_2_reg_4731 : STD_LOGIC_VECTOR (7 downto 0);
signal state_7_s_reg_720 : STD_LOGIC_VECTOR (7 downto 0);
signal state_6_2_reg_4746 : STD_LOGIC_VECTOR (7 downto 0);
signal state_6_s_reg_732 : STD_LOGIC_VECTOR (7 downto 0);
signal state_5_2_reg_4761 : STD_LOGIC_VECTOR (7 downto 0);
signal state_5_s_reg_744 : STD_LOGIC_VECTOR (7 downto 0);
signal state_4_2_reg_4776 : STD_LOGIC_VECTOR (7 downto 0);
signal state_4_s_reg_756 : STD_LOGIC_VECTOR (7 downto 0);
signal state_3_2_reg_4791 : STD_LOGIC_VECTOR (7 downto 0);
signal state_3_s_reg_768 : STD_LOGIC_VECTOR (7 downto 0);
signal state_2_2_reg_4806 : STD_LOGIC_VECTOR (7 downto 0);
signal state_2_s_reg_780 : STD_LOGIC_VECTOR (7 downto 0);
signal state_1_2_reg_4821 : STD_LOGIC_VECTOR (7 downto 0);
signal state_1_s_reg_792 : STD_LOGIC_VECTOR (7 downto 0);
signal state_0_2_reg_4836 : STD_LOGIC_VECTOR (7 downto 0);
signal state_0_s_reg_804 : STD_LOGIC_VECTOR (7 downto 0);
signal end_15_2_reg_4851 : STD_LOGIC_VECTOR (0 downto 0);
signal end_15_s_reg_816 : STD_LOGIC_VECTOR (0 downto 0);
signal end_14_2_reg_4866 : STD_LOGIC_VECTOR (0 downto 0);
signal end_14_s_reg_828 : STD_LOGIC_VECTOR (0 downto 0);
signal end_13_2_reg_4881 : STD_LOGIC_VECTOR (0 downto 0);
signal end_13_s_reg_840 : STD_LOGIC_VECTOR (0 downto 0);
signal end_12_2_reg_4896 : STD_LOGIC_VECTOR (0 downto 0);
signal end_12_s_reg_852 : STD_LOGIC_VECTOR (0 downto 0);
signal end_11_2_reg_4911 : STD_LOGIC_VECTOR (0 downto 0);
signal end_11_s_reg_864 : STD_LOGIC_VECTOR (0 downto 0);
signal end_10_2_reg_4926 : STD_LOGIC_VECTOR (0 downto 0);
signal end_10_s_reg_876 : STD_LOGIC_VECTOR (0 downto 0);
signal end_9_2_reg_4941 : STD_LOGIC_VECTOR (0 downto 0);
signal end_9_s_reg_888 : STD_LOGIC_VECTOR (0 downto 0);
signal end_8_2_reg_4956 : STD_LOGIC_VECTOR (0 downto 0);
signal end_8_s_reg_900 : STD_LOGIC_VECTOR (0 downto 0);
signal end_7_2_reg_4971 : STD_LOGIC_VECTOR (0 downto 0);
signal end_7_s_reg_912 : STD_LOGIC_VECTOR (0 downto 0);
signal end_6_2_reg_4986 : STD_LOGIC_VECTOR (0 downto 0);
signal end_6_s_reg_924 : STD_LOGIC_VECTOR (0 downto 0);
signal end_5_2_reg_5001 : STD_LOGIC_VECTOR (0 downto 0);
signal end_5_s_reg_936 : STD_LOGIC_VECTOR (0 downto 0);
signal end_4_2_reg_5016 : STD_LOGIC_VECTOR (0 downto 0);
signal end_4_s_reg_948 : STD_LOGIC_VECTOR (0 downto 0);
signal end_3_2_reg_5031 : STD_LOGIC_VECTOR (0 downto 0);
signal end_3_s_reg_960 : STD_LOGIC_VECTOR (0 downto 0);
signal end_2_2_reg_5046 : STD_LOGIC_VECTOR (0 downto 0);
signal end_2_s_reg_972 : STD_LOGIC_VECTOR (0 downto 0);
signal end_1_2_reg_5061 : STD_LOGIC_VECTOR (0 downto 0);
signal end_1_s_reg_984 : STD_LOGIC_VECTOR (0 downto 0);
signal end_0_2_reg_5076 : STD_LOGIC_VECTOR (0 downto 0);
signal end_0_s_reg_996 : STD_LOGIC_VECTOR (0 downto 0);
signal any_state_15_4_reg_5091 : STD_LOGIC_VECTOR (0 downto 0);
signal any_state_s_reg_1008 : STD_LOGIC_VECTOR (0 downto 0);
signal any_state_14_4_reg_5106 : STD_LOGIC_VECTOR (0 downto 0);
signal any_state_14_reg_1020 : STD_LOGIC_VECTOR (0 downto 0);
signal any_state_13_4_reg_5121 : STD_LOGIC_VECTOR (0 downto 0);
signal any_state_13_reg_1032 : STD_LOGIC_VECTOR (0 downto 0);
signal any_state_12_4_reg_5136 : STD_LOGIC_VECTOR (0 downto 0);
signal any_state_12_reg_1044 : STD_LOGIC_VECTOR (0 downto 0);
signal any_state_11_4_reg_5151 : STD_LOGIC_VECTOR (0 downto 0);
signal any_state_11_reg_1056 : STD_LOGIC_VECTOR (0 downto 0);
signal any_state_10_4_reg_5166 : STD_LOGIC_VECTOR (0 downto 0);
signal any_state_10_reg_1068 : STD_LOGIC_VECTOR (0 downto 0);
signal any_state_9_4_reg_5181 : STD_LOGIC_VECTOR (0 downto 0);
signal any_state_9_reg_1080 : STD_LOGIC_VECTOR (0 downto 0);
signal any_state_8_4_reg_5196 : STD_LOGIC_VECTOR (0 downto 0);
signal any_state_8_reg_1092 : STD_LOGIC_VECTOR (0 downto 0);
signal any_state_7_4_reg_5211 : STD_LOGIC_VECTOR (0 downto 0);
signal any_state_7_reg_1104 : STD_LOGIC_VECTOR (0 downto 0);
signal any_state_6_4_reg_5226 : STD_LOGIC_VECTOR (0 downto 0);
signal any_state_6_reg_1116 : STD_LOGIC_VECTOR (0 downto 0);
signal any_state_5_4_reg_5241 : STD_LOGIC_VECTOR (0 downto 0);
signal any_state_5_reg_1128 : STD_LOGIC_VECTOR (0 downto 0);
signal any_state_4_4_reg_5256 : STD_LOGIC_VECTOR (0 downto 0);
signal any_state_4_reg_1140 : STD_LOGIC_VECTOR (0 downto 0);
signal any_state_3_4_reg_5271 : STD_LOGIC_VECTOR (0 downto 0);
signal any_state_3_reg_1152 : STD_LOGIC_VECTOR (0 downto 0);
signal any_state_2_4_reg_5286 : STD_LOGIC_VECTOR (0 downto 0);
signal any_state_2_reg_1164 : STD_LOGIC_VECTOR (0 downto 0);
signal any_state_1_4_reg_5301 : STD_LOGIC_VECTOR (0 downto 0);
signal any_state_1_reg_1176 : STD_LOGIC_VECTOR (0 downto 0);
signal any_state_0_4_reg_5316 : STD_LOGIC_VECTOR (0 downto 0);
signal any_state_reg_1188 : STD_LOGIC_VECTOR (0 downto 0);
signal sym_offset_15_4_reg_5331 : STD_LOGIC_VECTOR (31 downto 0);
signal sym_offset_s_reg_1200 : STD_LOGIC_VECTOR (31 downto 0);
signal sym_offset_14_4_reg_5347 : STD_LOGIC_VECTOR (31 downto 0);
signal sym_offset_14_reg_1212 : STD_LOGIC_VECTOR (31 downto 0);
signal sym_offset_13_4_reg_5363 : STD_LOGIC_VECTOR (31 downto 0);
signal sym_offset_13_reg_1224 : STD_LOGIC_VECTOR (31 downto 0);
signal sym_offset_12_4_reg_5379 : STD_LOGIC_VECTOR (31 downto 0);
signal sym_offset_12_reg_1236 : STD_LOGIC_VECTOR (31 downto 0);
signal sym_offset_11_4_reg_5395 : STD_LOGIC_VECTOR (31 downto 0);
signal sym_offset_11_reg_1248 : STD_LOGIC_VECTOR (31 downto 0);
signal sym_offset_10_4_reg_5411 : STD_LOGIC_VECTOR (31 downto 0);
signal sym_offset_10_reg_1260 : STD_LOGIC_VECTOR (31 downto 0);
signal sym_offset_9_4_reg_5427 : STD_LOGIC_VECTOR (31 downto 0);
signal sym_offset_9_reg_1272 : STD_LOGIC_VECTOR (31 downto 0);
signal sym_offset_8_4_reg_5443 : STD_LOGIC_VECTOR (31 downto 0);
signal sym_offset_8_reg_1284 : STD_LOGIC_VECTOR (31 downto 0);
signal sym_offset_7_4_reg_5459 : STD_LOGIC_VECTOR (31 downto 0);
signal sym_offset_7_reg_1296 : STD_LOGIC_VECTOR (31 downto 0);
signal sym_offset_6_4_reg_5475 : STD_LOGIC_VECTOR (31 downto 0);
signal sym_offset_6_reg_1308 : STD_LOGIC_VECTOR (31 downto 0);
signal sym_offset_5_4_reg_5491 : STD_LOGIC_VECTOR (31 downto 0);
signal sym_offset_5_reg_1320 : STD_LOGIC_VECTOR (31 downto 0);
signal sym_offset_4_4_reg_5507 : STD_LOGIC_VECTOR (31 downto 0);
signal sym_offset_4_reg_1332 : STD_LOGIC_VECTOR (31 downto 0);
signal sym_offset_3_4_reg_5523 : STD_LOGIC_VECTOR (31 downto 0);
signal sym_offset_3_reg_1344 : STD_LOGIC_VECTOR (31 downto 0);
signal sym_offset_2_4_reg_5539 : STD_LOGIC_VECTOR (31 downto 0);
signal sym_offset_2_reg_1356 : STD_LOGIC_VECTOR (31 downto 0);
signal sym_offset_1_4_reg_5555 : STD_LOGIC_VECTOR (31 downto 0);
signal sym_offset_1_reg_1368 : STD_LOGIC_VECTOR (31 downto 0);
signal sym_offset_0_4_reg_5571 : STD_LOGIC_VECTOR (31 downto 0);
signal sym_offset_reg_1380 : STD_LOGIC_VECTOR (31 downto 0);
signal end_string_15_4_reg_5587 : STD_LOGIC_VECTOR (0 downto 0);
signal end_string_15_2_reg_1392 : STD_LOGIC_VECTOR (0 downto 0);
signal exitcond3_fu_12991_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal end_string_14_4_reg_5602 : STD_LOGIC_VECTOR (0 downto 0);
signal end_string_14_2_reg_1402 : STD_LOGIC_VECTOR (0 downto 0);
signal end_string_13_4_reg_5617 : STD_LOGIC_VECTOR (0 downto 0);
signal end_string_13_2_reg_1412 : STD_LOGIC_VECTOR (0 downto 0);
signal end_string_12_4_reg_5632 : STD_LOGIC_VECTOR (0 downto 0);
signal end_string_12_2_reg_1422 : STD_LOGIC_VECTOR (0 downto 0);
signal end_string_11_4_reg_5647 : STD_LOGIC_VECTOR (0 downto 0);
signal end_string_11_2_reg_1432 : STD_LOGIC_VECTOR (0 downto 0);
signal end_string_10_4_reg_5662 : STD_LOGIC_VECTOR (0 downto 0);
signal end_string_10_2_reg_1442 : STD_LOGIC_VECTOR (0 downto 0);
signal end_string_9_4_reg_5677 : STD_LOGIC_VECTOR (0 downto 0);
signal end_string_9_2_reg_1452 : STD_LOGIC_VECTOR (0 downto 0);
signal end_string_8_4_reg_5692 : STD_LOGIC_VECTOR (0 downto 0);
signal end_string_8_2_reg_1462 : STD_LOGIC_VECTOR (0 downto 0);
signal end_string_7_4_reg_5707 : STD_LOGIC_VECTOR (0 downto 0);
signal end_string_7_2_reg_1472 : STD_LOGIC_VECTOR (0 downto 0);
signal end_string_6_4_reg_5722 : STD_LOGIC_VECTOR (0 downto 0);
signal end_string_6_2_reg_1482 : STD_LOGIC_VECTOR (0 downto 0);
signal end_string_5_4_reg_5737 : STD_LOGIC_VECTOR (0 downto 0);
signal end_string_5_2_reg_1492 : STD_LOGIC_VECTOR (0 downto 0);
signal end_string_4_4_reg_5752 : STD_LOGIC_VECTOR (0 downto 0);
signal end_string_4_2_reg_1502 : STD_LOGIC_VECTOR (0 downto 0);
signal end_string_3_4_reg_5767 : STD_LOGIC_VECTOR (0 downto 0);
signal end_string_3_2_reg_1512 : STD_LOGIC_VECTOR (0 downto 0);
signal end_string_2_4_reg_5782 : STD_LOGIC_VECTOR (0 downto 0);
signal end_string_2_2_reg_1522 : STD_LOGIC_VECTOR (0 downto 0);
signal end_string_1_4_reg_5797 : STD_LOGIC_VECTOR (0 downto 0);
signal end_string_1_2_reg_1532 : STD_LOGIC_VECTOR (0 downto 0);
signal end_string_0_4_reg_5812 : STD_LOGIC_VECTOR (0 downto 0);
signal end_string_0_2_reg_1542 : STD_LOGIC_VECTOR (0 downto 0);
signal i_reg_1552 : STD_LOGIC_VECTOR (15 downto 0);
signal any_state_15_1_reg_1561 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_6_fu_13097_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal any_state_15_2_reg_2788 : STD_LOGIC_VECTOR (0 downto 0);
signal any_state_14_1_reg_1572 : STD_LOGIC_VECTOR (0 downto 0);
signal any_state_14_2_reg_2844 : STD_LOGIC_VECTOR (0 downto 0);
signal any_state_13_1_reg_1583 : STD_LOGIC_VECTOR (0 downto 0);
signal any_state_13_2_reg_2900 : STD_LOGIC_VECTOR (0 downto 0);
signal any_state_12_1_reg_1594 : STD_LOGIC_VECTOR (0 downto 0);
signal any_state_12_2_reg_2956 : STD_LOGIC_VECTOR (0 downto 0);
signal any_state_11_1_reg_1605 : STD_LOGIC_VECTOR (0 downto 0);
signal any_state_11_2_reg_3012 : STD_LOGIC_VECTOR (0 downto 0);
signal any_state_10_1_reg_1616 : STD_LOGIC_VECTOR (0 downto 0);
signal any_state_10_2_reg_3068 : STD_LOGIC_VECTOR (0 downto 0);
signal any_state_9_1_reg_1627 : STD_LOGIC_VECTOR (0 downto 0);
signal any_state_9_2_reg_3124 : STD_LOGIC_VECTOR (0 downto 0);
signal any_state_8_1_reg_1638 : STD_LOGIC_VECTOR (0 downto 0);
signal any_state_8_2_reg_3180 : STD_LOGIC_VECTOR (0 downto 0);
signal any_state_7_1_reg_1649 : STD_LOGIC_VECTOR (0 downto 0);
signal any_state_7_2_reg_3236 : STD_LOGIC_VECTOR (0 downto 0);
signal any_state_6_1_reg_1660 : STD_LOGIC_VECTOR (0 downto 0);
signal any_state_6_2_reg_3292 : STD_LOGIC_VECTOR (0 downto 0);
signal any_state_5_1_reg_1671 : STD_LOGIC_VECTOR (0 downto 0);
signal any_state_5_2_reg_3348 : STD_LOGIC_VECTOR (0 downto 0);
signal any_state_4_1_reg_1682 : STD_LOGIC_VECTOR (0 downto 0);
signal any_state_4_2_reg_3404 : STD_LOGIC_VECTOR (0 downto 0);
signal any_state_3_1_reg_1693 : STD_LOGIC_VECTOR (0 downto 0);
signal any_state_3_2_reg_3460 : STD_LOGIC_VECTOR (0 downto 0);
signal any_state_2_1_reg_1704 : STD_LOGIC_VECTOR (0 downto 0);
signal any_state_2_2_reg_3516 : STD_LOGIC_VECTOR (0 downto 0);
signal any_state_1_1_reg_1715 : STD_LOGIC_VECTOR (0 downto 0);
signal any_state_1_2_reg_3572 : STD_LOGIC_VECTOR (0 downto 0);
signal any_state_0_1_reg_1726 : STD_LOGIC_VECTOR (0 downto 0);
signal any_state_0_2_reg_3628 : STD_LOGIC_VECTOR (0 downto 0);
signal sym_offset_15_1_reg_1737 : STD_LOGIC_VECTOR (31 downto 0);
signal sym_offset_15_2_reg_1924 : STD_LOGIC_VECTOR (31 downto 0);
signal sym_offset_14_1_reg_1748 : STD_LOGIC_VECTOR (31 downto 0);
signal sym_offset_14_2_reg_1978 : STD_LOGIC_VECTOR (31 downto 0);
signal sym_offset_13_1_reg_1759 : STD_LOGIC_VECTOR (31 downto 0);
signal sym_offset_13_2_reg_2032 : STD_LOGIC_VECTOR (31 downto 0);
signal sym_offset_12_1_reg_1770 : STD_LOGIC_VECTOR (31 downto 0);
signal sym_offset_12_2_reg_2086 : STD_LOGIC_VECTOR (31 downto 0);
signal sym_offset_11_1_reg_1781 : STD_LOGIC_VECTOR (31 downto 0);
signal sym_offset_11_2_reg_2140 : STD_LOGIC_VECTOR (31 downto 0);
signal sym_offset_10_1_reg_1792 : STD_LOGIC_VECTOR (31 downto 0);
signal sym_offset_10_2_reg_2194 : STD_LOGIC_VECTOR (31 downto 0);
signal sym_offset_9_1_reg_1803 : STD_LOGIC_VECTOR (31 downto 0);
signal sym_offset_9_2_reg_2248 : STD_LOGIC_VECTOR (31 downto 0);
signal sym_offset_8_1_reg_1814 : STD_LOGIC_VECTOR (31 downto 0);
signal sym_offset_8_2_reg_2302 : STD_LOGIC_VECTOR (31 downto 0);
signal sym_offset_7_1_reg_1825 : STD_LOGIC_VECTOR (31 downto 0);
signal sym_offset_7_2_reg_2356 : STD_LOGIC_VECTOR (31 downto 0);
signal sym_offset_6_1_reg_1836 : STD_LOGIC_VECTOR (31 downto 0);
signal sym_offset_6_2_reg_2410 : STD_LOGIC_VECTOR (31 downto 0);
signal sym_offset_5_1_reg_1847 : STD_LOGIC_VECTOR (31 downto 0);
signal sym_offset_5_2_reg_2464 : STD_LOGIC_VECTOR (31 downto 0);
signal sym_offset_4_1_reg_1858 : STD_LOGIC_VECTOR (31 downto 0);
signal sym_offset_4_2_reg_2518 : STD_LOGIC_VECTOR (31 downto 0);
signal sym_offset_3_1_reg_1869 : STD_LOGIC_VECTOR (31 downto 0);
signal sym_offset_3_2_reg_2572 : STD_LOGIC_VECTOR (31 downto 0);
signal sym_offset_2_1_reg_1880 : STD_LOGIC_VECTOR (31 downto 0);
signal sym_offset_2_2_reg_2626 : STD_LOGIC_VECTOR (31 downto 0);
signal sym_offset_1_1_reg_1891 : STD_LOGIC_VECTOR (31 downto 0);
signal sym_offset_1_2_reg_2680 : STD_LOGIC_VECTOR (31 downto 0);
signal sym_offset_0_1_reg_1902 : STD_LOGIC_VECTOR (31 downto 0);
signal sym_offset_0_2_reg_2734 : STD_LOGIC_VECTOR (31 downto 0);
signal k_1_reg_1913 : STD_LOGIC_VECTOR (4 downto 0);
signal bus_assign_reg_3684 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_27_1_fu_13292_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal r_1_0_i_lcssa3_reg_3693 : STD_LOGIC_VECTOR (0 downto 0);
signal j_0_bucket_index_reg_3706 : STD_LOGIC_VECTOR (1 downto 0);
signal j_0_end_reg_3717 : STD_LOGIC_VECTOR (0 downto 0);
signal state_15_1_reg_3731 : STD_LOGIC_VECTOR (7 downto 0);
signal state_14_1_reg_3742 : STD_LOGIC_VECTOR (7 downto 0);
signal state_13_1_reg_3753 : STD_LOGIC_VECTOR (7 downto 0);
signal state_12_1_reg_3764 : STD_LOGIC_VECTOR (7 downto 0);
signal state_11_1_reg_3775 : STD_LOGIC_VECTOR (7 downto 0);
signal state_10_1_reg_3786 : STD_LOGIC_VECTOR (7 downto 0);
signal state_9_1_reg_3797 : STD_LOGIC_VECTOR (7 downto 0);
signal state_8_1_reg_3808 : STD_LOGIC_VECTOR (7 downto 0);
signal state_7_1_reg_3819 : STD_LOGIC_VECTOR (7 downto 0);
signal state_6_1_reg_3830 : STD_LOGIC_VECTOR (7 downto 0);
signal state_5_1_reg_3841 : STD_LOGIC_VECTOR (7 downto 0);
signal state_4_1_reg_3852 : STD_LOGIC_VECTOR (7 downto 0);
signal state_3_1_reg_3863 : STD_LOGIC_VECTOR (7 downto 0);
signal state_2_1_reg_3874 : STD_LOGIC_VECTOR (7 downto 0);
signal state_1_1_reg_3885 : STD_LOGIC_VECTOR (7 downto 0);
signal state_0_1_reg_3896 : STD_LOGIC_VECTOR (7 downto 0);
signal end_15_1_reg_3907 : STD_LOGIC_VECTOR (0 downto 0);
signal end_14_1_reg_3918 : STD_LOGIC_VECTOR (0 downto 0);
signal end_13_1_reg_3929 : STD_LOGIC_VECTOR (0 downto 0);
signal end_12_1_reg_3940 : STD_LOGIC_VECTOR (0 downto 0);
signal end_11_1_reg_3951 : STD_LOGIC_VECTOR (0 downto 0);
signal end_10_1_reg_3962 : STD_LOGIC_VECTOR (0 downto 0);
signal end_9_1_reg_3973 : STD_LOGIC_VECTOR (0 downto 0);
signal end_8_1_reg_3984 : STD_LOGIC_VECTOR (0 downto 0);
signal end_7_1_reg_3995 : STD_LOGIC_VECTOR (0 downto 0);
signal end_6_1_reg_4006 : STD_LOGIC_VECTOR (0 downto 0);
signal end_5_1_reg_4017 : STD_LOGIC_VECTOR (0 downto 0);
signal end_4_1_reg_4028 : STD_LOGIC_VECTOR (0 downto 0);
signal end_3_1_reg_4039 : STD_LOGIC_VECTOR (0 downto 0);
signal end_2_1_reg_4050 : STD_LOGIC_VECTOR (0 downto 0);
signal end_1_1_reg_4061 : STD_LOGIC_VECTOR (0 downto 0);
signal end_0_1_reg_4072 : STD_LOGIC_VECTOR (0 downto 0);
signal any_state_15_3_reg_4083 : STD_LOGIC_VECTOR (0 downto 0);
signal any_state_14_3_reg_4094 : STD_LOGIC_VECTOR (0 downto 0);
signal any_state_13_3_reg_4105 : STD_LOGIC_VECTOR (0 downto 0);
signal any_state_12_3_reg_4116 : STD_LOGIC_VECTOR (0 downto 0);
signal any_state_11_3_reg_4127 : STD_LOGIC_VECTOR (0 downto 0);
signal any_state_10_3_reg_4138 : STD_LOGIC_VECTOR (0 downto 0);
signal any_state_9_3_reg_4149 : STD_LOGIC_VECTOR (0 downto 0);
signal any_state_8_3_reg_4160 : STD_LOGIC_VECTOR (0 downto 0);
signal any_state_7_3_reg_4171 : STD_LOGIC_VECTOR (0 downto 0);
signal any_state_6_3_reg_4182 : STD_LOGIC_VECTOR (0 downto 0);
signal any_state_5_3_reg_4193 : STD_LOGIC_VECTOR (0 downto 0);
signal any_state_4_3_reg_4204 : STD_LOGIC_VECTOR (0 downto 0);
signal any_state_3_3_reg_4215 : STD_LOGIC_VECTOR (0 downto 0);
signal any_state_2_3_reg_4226 : STD_LOGIC_VECTOR (0 downto 0);
signal any_state_1_3_reg_4237 : STD_LOGIC_VECTOR (0 downto 0);
signal any_state_0_3_reg_4248 : STD_LOGIC_VECTOR (0 downto 0);
signal sym_offset_15_3_reg_4259 : STD_LOGIC_VECTOR (31 downto 0);
signal sym_offset_14_3_reg_4270 : STD_LOGIC_VECTOR (31 downto 0);
signal sym_offset_13_3_reg_4281 : STD_LOGIC_VECTOR (31 downto 0);
signal sym_offset_12_3_reg_4292 : STD_LOGIC_VECTOR (31 downto 0);
signal sym_offset_11_3_reg_4303 : STD_LOGIC_VECTOR (31 downto 0);
signal sym_offset_10_3_reg_4314 : STD_LOGIC_VECTOR (31 downto 0);
signal sym_offset_9_3_reg_4325 : STD_LOGIC_VECTOR (31 downto 0);
signal sym_offset_8_3_reg_4336 : STD_LOGIC_VECTOR (31 downto 0);
signal sym_offset_7_3_reg_4347 : STD_LOGIC_VECTOR (31 downto 0);
signal sym_offset_6_3_reg_4358 : STD_LOGIC_VECTOR (31 downto 0);
signal sym_offset_5_3_reg_4369 : STD_LOGIC_VECTOR (31 downto 0);
signal sym_offset_4_3_reg_4380 : STD_LOGIC_VECTOR (31 downto 0);
signal sym_offset_3_3_reg_4391 : STD_LOGIC_VECTOR (31 downto 0);
signal sym_offset_2_3_reg_4402 : STD_LOGIC_VECTOR (31 downto 0);
signal sym_offset_1_3_reg_4413 : STD_LOGIC_VECTOR (31 downto 0);
signal sym_offset_0_3_reg_4424 : STD_LOGIC_VECTOR (31 downto 0);
signal end_string_15_3_reg_4435 : STD_LOGIC_VECTOR (0 downto 0);
signal end_string_14_3_reg_4446 : STD_LOGIC_VECTOR (0 downto 0);
signal end_string_13_3_reg_4457 : STD_LOGIC_VECTOR (0 downto 0);
signal end_string_12_3_reg_4468 : STD_LOGIC_VECTOR (0 downto 0);
signal end_string_11_3_reg_4479 : STD_LOGIC_VECTOR (0 downto 0);
signal end_string_10_3_reg_4490 : STD_LOGIC_VECTOR (0 downto 0);
signal end_string_9_3_reg_4501 : STD_LOGIC_VECTOR (0 downto 0);
signal end_string_8_3_reg_4512 : STD_LOGIC_VECTOR (0 downto 0);
signal end_string_7_3_reg_4523 : STD_LOGIC_VECTOR (0 downto 0);
signal end_string_6_3_reg_4534 : STD_LOGIC_VECTOR (0 downto 0);
signal end_string_5_3_reg_4545 : STD_LOGIC_VECTOR (0 downto 0);
signal end_string_4_3_reg_4556 : STD_LOGIC_VECTOR (0 downto 0);
signal end_string_3_3_reg_4567 : STD_LOGIC_VECTOR (0 downto 0);
signal end_string_2_3_reg_4578 : STD_LOGIC_VECTOR (0 downto 0);
signal end_string_1_3_reg_4589 : STD_LOGIC_VECTOR (0 downto 0);
signal end_string_0_3_reg_4600 : STD_LOGIC_VECTOR (0 downto 0);
signal state_15_4_reg_8712 : STD_LOGIC_VECTOR (7 downto 0);
signal end_load_3_phi_phi_fu_11584_p32 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp1_fu_13626_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal state_14_4_reg_8770 : STD_LOGIC_VECTOR (7 downto 0);
signal state_13_4_reg_8828 : STD_LOGIC_VECTOR (7 downto 0);
signal state_12_4_reg_8886 : STD_LOGIC_VECTOR (7 downto 0);
signal state_11_4_reg_8944 : STD_LOGIC_VECTOR (7 downto 0);
signal state_10_4_reg_9002 : STD_LOGIC_VECTOR (7 downto 0);
signal state_9_4_reg_9060 : STD_LOGIC_VECTOR (7 downto 0);
signal state_8_4_reg_9118 : STD_LOGIC_VECTOR (7 downto 0);
signal state_7_4_reg_9176 : STD_LOGIC_VECTOR (7 downto 0);
signal state_6_4_reg_9234 : STD_LOGIC_VECTOR (7 downto 0);
signal state_5_4_reg_9292 : STD_LOGIC_VECTOR (7 downto 0);
signal state_4_4_reg_9350 : STD_LOGIC_VECTOR (7 downto 0);
signal state_3_4_reg_9408 : STD_LOGIC_VECTOR (7 downto 0);
signal state_2_4_reg_9466 : STD_LOGIC_VECTOR (7 downto 0);
signal state_1_4_reg_9524 : STD_LOGIC_VECTOR (7 downto 0);
signal state_0_4_reg_9582 : STD_LOGIC_VECTOR (7 downto 0);
signal end_15_3_reg_5879 : STD_LOGIC_VECTOR (0 downto 0);
signal end_14_3_reg_5935 : STD_LOGIC_VECTOR (0 downto 0);
signal end_13_3_reg_5991 : STD_LOGIC_VECTOR (0 downto 0);
signal end_12_3_reg_6047 : STD_LOGIC_VECTOR (0 downto 0);
signal end_11_3_reg_6103 : STD_LOGIC_VECTOR (0 downto 0);
signal end_10_3_reg_6159 : STD_LOGIC_VECTOR (0 downto 0);
signal end_9_3_reg_6215 : STD_LOGIC_VECTOR (0 downto 0);
signal end_8_3_reg_6271 : STD_LOGIC_VECTOR (0 downto 0);
signal end_7_3_reg_6327 : STD_LOGIC_VECTOR (0 downto 0);
signal end_6_3_reg_6383 : STD_LOGIC_VECTOR (0 downto 0);
signal end_5_3_reg_6439 : STD_LOGIC_VECTOR (0 downto 0);
signal end_4_3_reg_6495 : STD_LOGIC_VECTOR (0 downto 0);
signal end_3_3_reg_6551 : STD_LOGIC_VECTOR (0 downto 0);
signal end_2_3_reg_6607 : STD_LOGIC_VECTOR (0 downto 0);
signal end_1_3_reg_6663 : STD_LOGIC_VECTOR (0 downto 0);
signal end_0_3_reg_6719 : STD_LOGIC_VECTOR (0 downto 0);
signal any_state_15_6_reg_9640 : STD_LOGIC_VECTOR (0 downto 0);
signal any_state_14_6_reg_9699 : STD_LOGIC_VECTOR (0 downto 0);
signal any_state_13_6_reg_9758 : STD_LOGIC_VECTOR (0 downto 0);
signal any_state_12_6_reg_9817 : STD_LOGIC_VECTOR (0 downto 0);
signal any_state_11_6_reg_9876 : STD_LOGIC_VECTOR (0 downto 0);
signal any_state_10_6_reg_9935 : STD_LOGIC_VECTOR (0 downto 0);
signal any_state_9_6_reg_9994 : STD_LOGIC_VECTOR (0 downto 0);
signal any_state_8_6_reg_10053 : STD_LOGIC_VECTOR (0 downto 0);
signal any_state_7_6_reg_10112 : STD_LOGIC_VECTOR (0 downto 0);
signal any_state_6_6_reg_10171 : STD_LOGIC_VECTOR (0 downto 0);
signal any_state_5_6_reg_10230 : STD_LOGIC_VECTOR (0 downto 0);
signal any_state_4_6_reg_10289 : STD_LOGIC_VECTOR (0 downto 0);
signal any_state_3_6_reg_10348 : STD_LOGIC_VECTOR (0 downto 0);
signal any_state_2_6_reg_10407 : STD_LOGIC_VECTOR (0 downto 0);
signal any_state_1_6_reg_10466 : STD_LOGIC_VECTOR (0 downto 0);
signal any_state_0_6_reg_10525 : STD_LOGIC_VECTOR (0 downto 0);
signal sym_offset_15_5_reg_11687 : STD_LOGIC_VECTOR (31 downto 0);
signal sym_offset_14_5_reg_11741 : STD_LOGIC_VECTOR (31 downto 0);
signal sym_offset_13_5_reg_11795 : STD_LOGIC_VECTOR (31 downto 0);
signal sym_offset_12_5_reg_11849 : STD_LOGIC_VECTOR (31 downto 0);
signal sym_offset_11_5_reg_11903 : STD_LOGIC_VECTOR (31 downto 0);
signal sym_offset_10_5_reg_11957 : STD_LOGIC_VECTOR (31 downto 0);
signal sym_offset_9_5_reg_12011 : STD_LOGIC_VECTOR (31 downto 0);
signal sym_offset_8_5_reg_12065 : STD_LOGIC_VECTOR (31 downto 0);
signal sym_offset_7_5_reg_12119 : STD_LOGIC_VECTOR (31 downto 0);
signal sym_offset_6_5_reg_12173 : STD_LOGIC_VECTOR (31 downto 0);
signal sym_offset_5_5_reg_12227 : STD_LOGIC_VECTOR (31 downto 0);
signal sym_offset_4_5_reg_12281 : STD_LOGIC_VECTOR (31 downto 0);
signal sym_offset_3_5_reg_12335 : STD_LOGIC_VECTOR (31 downto 0);
signal sym_offset_2_5_reg_12389 : STD_LOGIC_VECTOR (31 downto 0);
signal sym_offset_1_5_reg_12443 : STD_LOGIC_VECTOR (31 downto 0);
signal sym_offset_0_5_reg_12497 : STD_LOGIC_VECTOR (31 downto 0);
signal end_string_15_6_reg_10584 : STD_LOGIC_VECTOR (0 downto 0);
signal end_string_14_6_reg_10643 : STD_LOGIC_VECTOR (0 downto 0);
signal end_string_13_6_reg_10702 : STD_LOGIC_VECTOR (0 downto 0);
signal end_string_12_6_reg_10761 : STD_LOGIC_VECTOR (0 downto 0);
signal end_string_11_6_reg_10820 : STD_LOGIC_VECTOR (0 downto 0);
signal end_string_10_6_reg_10879 : STD_LOGIC_VECTOR (0 downto 0);
signal end_string_9_6_reg_10938 : STD_LOGIC_VECTOR (0 downto 0);
signal end_string_8_6_reg_10997 : STD_LOGIC_VECTOR (0 downto 0);
signal end_string_7_6_reg_11056 : STD_LOGIC_VECTOR (0 downto 0);
signal end_string_6_6_reg_11115 : STD_LOGIC_VECTOR (0 downto 0);
signal end_string_5_6_reg_11174 : STD_LOGIC_VECTOR (0 downto 0);
signal end_string_4_6_reg_11233 : STD_LOGIC_VECTOR (0 downto 0);
signal end_string_3_6_reg_11292 : STD_LOGIC_VECTOR (0 downto 0);
signal end_string_2_6_reg_11351 : STD_LOGIC_VECTOR (0 downto 0);
signal end_string_1_6_reg_11410 : STD_LOGIC_VECTOR (0 downto 0);
signal end_string_0_6_reg_11469 : STD_LOGIC_VECTOR (0 downto 0);
signal k_2_reg_5827 : STD_LOGIC_VECTOR (4 downto 0);
signal end_0_reg_5841 : STD_LOGIC_VECTOR (0 downto 0);
signal any_state_load_phi_phi_fu_6778_p32 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_12_fu_13561_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal end_string_0_reg_6828 : STD_LOGIC_VECTOR (0 downto 0);
signal end_string_15_5_reg_6839 : STD_LOGIC_VECTOR (0 downto 0);
signal end_string_14_5_reg_6893 : STD_LOGIC_VECTOR (0 downto 0);
signal end_string_13_5_reg_6947 : STD_LOGIC_VECTOR (0 downto 0);
signal end_string_12_5_reg_7001 : STD_LOGIC_VECTOR (0 downto 0);
signal end_string_11_5_reg_7055 : STD_LOGIC_VECTOR (0 downto 0);
signal end_string_10_5_reg_7109 : STD_LOGIC_VECTOR (0 downto 0);
signal end_string_9_5_reg_7163 : STD_LOGIC_VECTOR (0 downto 0);
signal end_string_8_5_reg_7217 : STD_LOGIC_VECTOR (0 downto 0);
signal end_string_7_5_reg_7271 : STD_LOGIC_VECTOR (0 downto 0);
signal end_string_6_5_reg_7325 : STD_LOGIC_VECTOR (0 downto 0);
signal end_string_5_5_reg_7379 : STD_LOGIC_VECTOR (0 downto 0);
signal end_string_4_5_reg_7433 : STD_LOGIC_VECTOR (0 downto 0);
signal end_string_3_5_reg_7487 : STD_LOGIC_VECTOR (0 downto 0);
signal end_string_2_5_reg_7541 : STD_LOGIC_VECTOR (0 downto 0);
signal end_string_1_5_reg_7595 : STD_LOGIC_VECTOR (0 downto 0);
signal end_string_0_5_reg_7649 : STD_LOGIC_VECTOR (0 downto 0);
signal any_state_load_1_phi_phi_fu_7706_p32 : STD_LOGIC_VECTOR (0 downto 0);
signal any_state_load_1_phi_reg_7703 : STD_LOGIC_VECTOR (0 downto 0);
signal any_state_15_5_reg_7757 : STD_LOGIC_VECTOR (0 downto 0);
signal any_state_14_5_reg_7812 : STD_LOGIC_VECTOR (0 downto 0);
signal any_state_13_5_reg_7867 : STD_LOGIC_VECTOR (0 downto 0);
signal any_state_12_5_reg_7922 : STD_LOGIC_VECTOR (0 downto 0);
signal any_state_11_5_reg_7977 : STD_LOGIC_VECTOR (0 downto 0);
signal any_state_10_5_reg_8032 : STD_LOGIC_VECTOR (0 downto 0);
signal any_state_9_5_reg_8087 : STD_LOGIC_VECTOR (0 downto 0);
signal any_state_8_5_reg_8142 : STD_LOGIC_VECTOR (0 downto 0);
signal any_state_7_5_reg_8197 : STD_LOGIC_VECTOR (0 downto 0);
signal any_state_6_5_reg_8252 : STD_LOGIC_VECTOR (0 downto 0);
signal any_state_5_5_reg_8307 : STD_LOGIC_VECTOR (0 downto 0);
signal any_state_4_5_reg_8362 : STD_LOGIC_VECTOR (0 downto 0);
signal any_state_3_5_reg_8417 : STD_LOGIC_VECTOR (0 downto 0);
signal any_state_2_5_reg_8472 : STD_LOGIC_VECTOR (0 downto 0);
signal any_state_1_5_reg_8527 : STD_LOGIC_VECTOR (0 downto 0);
signal any_state_0_5_reg_8582 : STD_LOGIC_VECTOR (0 downto 0);
signal j_bit_addr12_phi_reg_8637 : STD_LOGIC_VECTOR (7 downto 0);
signal j_bucket_index_addr13_phi_reg_8675 : STD_LOGIC_VECTOR (7 downto 0);
signal end_string_15_6_phi_fu_10589_p34 : STD_LOGIC_VECTOR (0 downto 0);
signal end_string_14_6_phi_fu_10648_p34 : STD_LOGIC_VECTOR (0 downto 0);
signal end_string_13_6_phi_fu_10707_p34 : STD_LOGIC_VECTOR (0 downto 0);
signal end_string_12_6_phi_fu_10766_p34 : STD_LOGIC_VECTOR (0 downto 0);
signal end_string_11_6_phi_fu_10825_p34 : STD_LOGIC_VECTOR (0 downto 0);
signal end_string_10_6_phi_fu_10884_p34 : STD_LOGIC_VECTOR (0 downto 0);
signal end_string_9_6_phi_fu_10943_p34 : STD_LOGIC_VECTOR (0 downto 0);
signal end_string_8_6_phi_fu_11002_p34 : STD_LOGIC_VECTOR (0 downto 0);
signal end_string_7_6_phi_fu_11061_p34 : STD_LOGIC_VECTOR (0 downto 0);
signal end_string_6_6_phi_fu_11120_p34 : STD_LOGIC_VECTOR (0 downto 0);
signal end_string_5_6_phi_fu_11179_p34 : STD_LOGIC_VECTOR (0 downto 0);
signal end_string_4_6_phi_fu_11238_p34 : STD_LOGIC_VECTOR (0 downto 0);
signal end_string_3_6_phi_fu_11297_p34 : STD_LOGIC_VECTOR (0 downto 0);
signal end_string_2_6_phi_fu_11356_p34 : STD_LOGIC_VECTOR (0 downto 0);
signal end_string_1_6_phi_fu_11415_p34 : STD_LOGIC_VECTOR (0 downto 0);
signal end_string_0_6_phi_fu_11474_p34 : STD_LOGIC_VECTOR (0 downto 0);
signal end_string_load_phi_phi_fu_11531_p32 : STD_LOGIC_VECTOR (0 downto 0);
signal offset_reg_11634 : STD_LOGIC_VECTOR (31 downto 0);
signal state_assign_in_reg_12551 : STD_LOGIC_VECTOR (7 downto 0);
signal k_3_reg_12604 : STD_LOGIC_VECTOR (4 downto 0);
signal any_end_reg_12691 : STD_LOGIC_VECTOR (0 downto 0);
signal all_end_reg_12647 : STD_LOGIC_VECTOR (0 downto 0);
signal end_load_phi_reg_12753 : STD_LOGIC_VECTOR (0 downto 0);
signal all_end_1_reg_12807 : STD_LOGIC_VECTOR (0 downto 0);
signal p_0_reg_12882 : STD_LOGIC_VECTOR (0 downto 0);
signal grp_nfa_get_initials_1_fu_12896_ap_start_ap_start_reg : STD_LOGIC := '0';
signal ap_NS_fsm : STD_LOGIC_VECTOR (5 downto 0);
signal grp_nfa_get_finals_1_fu_12905_ap_start_ap_start_reg : STD_LOGIC := '0';
signal tmp_s_fu_13002_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_buckets_addr_1_gep_fu_547_p3 : STD_LOGIC_VECTOR (3 downto 0);
signal result_addr_gep_fu_575_p3 : STD_LOGIC_VECTOR (3 downto 0);
signal tmp_buckets_addr_3_gep_fu_591_p3 : STD_LOGIC_VECTOR (3 downto 0);
signal tmp_15_fu_13637_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_82_i_cast_fu_13682_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_83_i_cast_fu_13700_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal end_string_fu_152 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_35_fu_13007_p1 : STD_LOGIC_VECTOR (3 downto 0);
signal end_string_1_fu_156 : STD_LOGIC_VECTOR (0 downto 0);
signal end_string_2_fu_160 : STD_LOGIC_VECTOR (0 downto 0);
signal end_string_3_fu_164 : STD_LOGIC_VECTOR (0 downto 0);
signal end_string_4_fu_168 : STD_LOGIC_VECTOR (0 downto 0);
signal end_string_5_fu_172 : STD_LOGIC_VECTOR (0 downto 0);
signal end_string_6_fu_176 : STD_LOGIC_VECTOR (0 downto 0);
signal end_string_7_fu_180 : STD_LOGIC_VECTOR (0 downto 0);
signal end_string_8_fu_184 : STD_LOGIC_VECTOR (0 downto 0);
signal end_string_9_fu_188 : STD_LOGIC_VECTOR (0 downto 0);
signal end_string_10_fu_192 : STD_LOGIC_VECTOR (0 downto 0);
signal end_string_11_fu_196 : STD_LOGIC_VECTOR (0 downto 0);
signal end_string_12_fu_200 : STD_LOGIC_VECTOR (0 downto 0);
signal end_string_13_fu_204 : STD_LOGIC_VECTOR (0 downto 0);
signal end_string_14_fu_208 : STD_LOGIC_VECTOR (0 downto 0);
signal end_string_s_fu_212 : STD_LOGIC_VECTOR (0 downto 0);
signal j_15_bit_17_fu_228 : STD_LOGIC_VECTOR (7 downto 0);
signal j_15_bit_16_fu_13302_p1 : STD_LOGIC_VECTOR (7 downto 0);
signal r_bit_p_bsf32_hw_fu_12914_ap_return_temp: signed (6-1 downto 0);
signal j_15_bit_fu_232 : STD_LOGIC_VECTOR (7 downto 0);
signal j_15_bit_1_fu_236 : STD_LOGIC_VECTOR (7 downto 0);
signal j_15_bit_2_fu_240 : STD_LOGIC_VECTOR (7 downto 0);
signal j_15_bit_3_fu_244 : STD_LOGIC_VECTOR (7 downto 0);
signal j_15_bit_4_fu_248 : STD_LOGIC_VECTOR (7 downto 0);
signal j_15_bit_5_fu_252 : STD_LOGIC_VECTOR (7 downto 0);
signal j_15_bit_6_fu_256 : STD_LOGIC_VECTOR (7 downto 0);
signal j_15_bit_7_fu_260 : STD_LOGIC_VECTOR (7 downto 0);
signal j_15_bit_8_fu_264 : STD_LOGIC_VECTOR (7 downto 0);
signal j_15_bit_9_fu_268 : STD_LOGIC_VECTOR (7 downto 0);
signal j_15_bit_10_fu_272 : STD_LOGIC_VECTOR (7 downto 0);
signal j_15_bit_11_fu_276 : STD_LOGIC_VECTOR (7 downto 0);
signal j_15_bit_12_fu_280 : STD_LOGIC_VECTOR (7 downto 0);
signal j_15_bit_13_fu_284 : STD_LOGIC_VECTOR (7 downto 0);
signal j_15_bit_14_fu_288 : STD_LOGIC_VECTOR (7 downto 0);
signal j_15_bit_15_fu_292 : STD_LOGIC_VECTOR (7 downto 0);
signal j_bucket_index_0_s_fu_296 : STD_LOGIC_VECTOR (7 downto 0);
signal j_bucket_index_1_s_fu_300 : STD_LOGIC_VECTOR (7 downto 0);
signal j_bucket_index_2_s_fu_304 : STD_LOGIC_VECTOR (7 downto 0);
signal j_bucket_index_3_s_fu_308 : STD_LOGIC_VECTOR (7 downto 0);
signal j_bucket_index_4_s_fu_312 : STD_LOGIC_VECTOR (7 downto 0);
signal j_bucket_index_5_s_fu_316 : STD_LOGIC_VECTOR (7 downto 0);
signal j_bucket_index_6_s_fu_320 : STD_LOGIC_VECTOR (7 downto 0);
signal j_bucket_index_7_s_fu_324 : STD_LOGIC_VECTOR (7 downto 0);
signal j_bucket_index_8_s_fu_328 : STD_LOGIC_VECTOR (7 downto 0);
signal j_bucket_index_9_s_fu_332 : STD_LOGIC_VECTOR (7 downto 0);
signal j_bucket_index_10_s_fu_336 : STD_LOGIC_VECTOR (7 downto 0);
signal j_bucket_index_11_s_fu_340 : STD_LOGIC_VECTOR (7 downto 0);
signal j_bucket_index_12_s_fu_344 : STD_LOGIC_VECTOR (7 downto 0);
signal j_bucket_index_13_s_fu_348 : STD_LOGIC_VECTOR (7 downto 0);
signal j_bucket_index_14_s_fu_352 : STD_LOGIC_VECTOR (7 downto 0);
signal j_bucket_index_15_s_fu_356 : STD_LOGIC_VECTOR (7 downto 0);
signal j_15_end_fu_360 : STD_LOGIC_VECTOR (0 downto 0);
signal j_15_end_1_fu_364 : STD_LOGIC_VECTOR (0 downto 0);
signal j_15_end_2_fu_368 : STD_LOGIC_VECTOR (0 downto 0);
signal j_15_end_3_fu_372 : STD_LOGIC_VECTOR (0 downto 0);
signal j_15_end_4_fu_376 : STD_LOGIC_VECTOR (0 downto 0);
signal j_15_end_5_fu_380 : STD_LOGIC_VECTOR (0 downto 0);
signal j_15_end_6_fu_384 : STD_LOGIC_VECTOR (0 downto 0);
signal j_15_end_7_fu_388 : STD_LOGIC_VECTOR (0 downto 0);
signal j_15_end_8_fu_392 : STD_LOGIC_VECTOR (0 downto 0);
signal j_15_end_9_fu_396 : STD_LOGIC_VECTOR (0 downto 0);
signal j_15_end_10_fu_400 : STD_LOGIC_VECTOR (0 downto 0);
signal j_15_end_11_fu_404 : STD_LOGIC_VECTOR (0 downto 0);
signal j_15_end_12_fu_408 : STD_LOGIC_VECTOR (0 downto 0);
signal j_15_end_13_fu_412 : STD_LOGIC_VECTOR (0 downto 0);
signal j_15_end_14_fu_416 : STD_LOGIC_VECTOR (0 downto 0);
signal j_15_end_15_fu_420 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_49_i_fu_13600_p3 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_68_i_fu_13757_p3 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_84_i_fu_13711_p3 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_42_fu_13568_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_44_fu_13584_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_43_fu_13580_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_12923_p4 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_12933_p4 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_8_1_i_fu_13594_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_8_i_fu_13588_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_1_fu_13609_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_45_fu_13648_p1 : STD_LOGIC_VECTOR (5 downto 0);
signal tmp_6_i_fu_13660_p0 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_6_i_fu_13660_p1 : STD_LOGIC_VECTOR (5 downto 0);
signal tmp_6_i_fu_13660_p2 : STD_LOGIC_VECTOR (13 downto 0);
signal tmp_7_i_cast_fu_13666_p1 : STD_LOGIC_VECTOR (13 downto 0);
signal tmp_82_i_fu_13675_p3 : STD_LOGIC_VECTOR (14 downto 0);
signal tmp_83_i_fu_13693_p3 : STD_LOGIC_VECTOR (14 downto 0);
signal tmp_41_fu_13741_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_40_fu_13737_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_6_1_i_fu_13751_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_57_i_fu_13745_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_return_preg : STD_LOGIC_VECTOR (0 downto 0) := "0";
signal tmp_6_i_fu_13660_p00 : STD_LOGIC_VECTOR (13 downto 0);
signal tmp_6_i_fu_13660_p10 : STD_LOGIC_VECTOR (13 downto 0);
signal ap_sig_bdd_2953 : BOOLEAN;
signal ap_sig_bdd_2955 : BOOLEAN;
signal ap_sig_bdd_2957 : BOOLEAN;
signal ap_sig_bdd_2959 : BOOLEAN;
signal ap_sig_bdd_2961 : BOOLEAN;
signal ap_sig_bdd_2963 : BOOLEAN;
signal ap_sig_bdd_2965 : BOOLEAN;
signal ap_sig_bdd_2967 : BOOLEAN;
signal ap_sig_bdd_2969 : BOOLEAN;
signal ap_sig_bdd_2971 : BOOLEAN;
signal ap_sig_bdd_2973 : BOOLEAN;
signal ap_sig_bdd_2975 : BOOLEAN;
signal ap_sig_bdd_2977 : BOOLEAN;
signal ap_sig_bdd_2979 : BOOLEAN;
signal ap_sig_bdd_2981 : BOOLEAN;
signal ap_sig_bdd_2983 : BOOLEAN;
signal ap_sig_bdd_1962 : BOOLEAN;
signal ap_sig_bdd_1739 : BOOLEAN;
signal ap_sig_bdd_1202 : BOOLEAN;
signal ap_sig_bdd_327 : BOOLEAN;
signal ap_sig_bdd_2491 : BOOLEAN;
signal ap_sig_bdd_2495 : BOOLEAN;
signal ap_sig_bdd_2499 : BOOLEAN;
signal ap_sig_bdd_2503 : BOOLEAN;
signal ap_sig_bdd_2507 : BOOLEAN;
signal ap_sig_bdd_2511 : BOOLEAN;
signal ap_sig_bdd_2515 : BOOLEAN;
signal ap_sig_bdd_2519 : BOOLEAN;
signal ap_sig_bdd_2523 : BOOLEAN;
signal ap_sig_bdd_2527 : BOOLEAN;
signal ap_sig_bdd_2531 : BOOLEAN;
signal ap_sig_bdd_2535 : BOOLEAN;
signal ap_sig_bdd_2539 : BOOLEAN;
signal ap_sig_bdd_2543 : BOOLEAN;
signal ap_sig_bdd_2547 : BOOLEAN;
signal ap_sig_bdd_2551 : BOOLEAN;
signal ap_sig_bdd_395 : BOOLEAN;
signal ap_sig_bdd_1793 : BOOLEAN;
signal ap_sig_bdd_2557 : BOOLEAN;
signal ap_sig_bdd_2561 : BOOLEAN;
signal ap_sig_bdd_2565 : BOOLEAN;
signal ap_sig_bdd_2569 : BOOLEAN;
signal ap_sig_bdd_2573 : BOOLEAN;
signal ap_sig_bdd_2577 : BOOLEAN;
signal ap_sig_bdd_2581 : BOOLEAN;
signal ap_sig_bdd_2585 : BOOLEAN;
signal ap_sig_bdd_2589 : BOOLEAN;
signal ap_sig_bdd_2593 : BOOLEAN;
signal ap_sig_bdd_2597 : BOOLEAN;
signal ap_sig_bdd_2601 : BOOLEAN;
signal ap_sig_bdd_2605 : BOOLEAN;
signal ap_sig_bdd_2609 : BOOLEAN;
signal ap_sig_bdd_2613 : BOOLEAN;
signal ap_sig_bdd_2617 : BOOLEAN;
signal ap_sig_bdd_369 : BOOLEAN;
component nfa_get_initials_1 IS
port (
ap_clk : IN STD_LOGIC;
ap_rst : IN STD_LOGIC;
ap_start : IN STD_LOGIC;
ap_done : OUT STD_LOGIC;
ap_idle : OUT STD_LOGIC;
ap_ready : OUT STD_LOGIC;
nfa_initials_buckets_req_din : OUT STD_LOGIC;
nfa_initials_buckets_req_full_n : IN STD_LOGIC;
nfa_initials_buckets_req_write : OUT STD_LOGIC;
nfa_initials_buckets_rsp_empty_n : IN STD_LOGIC;
nfa_initials_buckets_rsp_read : OUT STD_LOGIC;
nfa_initials_buckets_address : OUT STD_LOGIC_VECTOR (31 downto 0);
nfa_initials_buckets_datain : IN STD_LOGIC_VECTOR (63 downto 0);
nfa_initials_buckets_dataout : OUT STD_LOGIC_VECTOR (63 downto 0);
nfa_initials_buckets_size : OUT STD_LOGIC_VECTOR (31 downto 0);
ap_ce : IN STD_LOGIC;
initials_buckets_address0 : OUT STD_LOGIC_VECTOR (3 downto 0);
initials_buckets_ce0 : OUT STD_LOGIC;
initials_buckets_we0 : OUT STD_LOGIC;
initials_buckets_d0 : OUT STD_LOGIC_VECTOR (63 downto 0);
tmp_s : IN STD_LOGIC_VECTOR (4 downto 0) );
end component;
component nfa_get_finals_1 IS
port (
ap_clk : IN STD_LOGIC;
ap_rst : IN STD_LOGIC;
ap_start : IN STD_LOGIC;
ap_done : OUT STD_LOGIC;
ap_idle : OUT STD_LOGIC;
ap_ready : OUT STD_LOGIC;
nfa_finals_buckets_req_din : OUT STD_LOGIC;
nfa_finals_buckets_req_full_n : IN STD_LOGIC;
nfa_finals_buckets_req_write : OUT STD_LOGIC;
nfa_finals_buckets_rsp_empty_n : IN STD_LOGIC;
nfa_finals_buckets_rsp_read : OUT STD_LOGIC;
nfa_finals_buckets_address : OUT STD_LOGIC_VECTOR (31 downto 0);
nfa_finals_buckets_datain : IN STD_LOGIC_VECTOR (63 downto 0);
nfa_finals_buckets_dataout : OUT STD_LOGIC_VECTOR (63 downto 0);
nfa_finals_buckets_size : OUT STD_LOGIC_VECTOR (31 downto 0);
ap_ce : IN STD_LOGIC;
finals_buckets_address0 : OUT STD_LOGIC_VECTOR (3 downto 0);
finals_buckets_ce0 : OUT STD_LOGIC;
finals_buckets_we0 : OUT STD_LOGIC;
finals_buckets_d0 : OUT STD_LOGIC_VECTOR (63 downto 0);
tmp_28 : IN STD_LOGIC_VECTOR (4 downto 0) );
end component;
component p_bsf32_hw IS
port (
bus_r : IN STD_LOGIC_VECTOR (31 downto 0);
ap_return : OUT STD_LOGIC_VECTOR (5 downto 0) );
end component;
component nfa_accept_sample_multi_next_buckets IS
generic (
DataWidth : INTEGER;
AddressRange : INTEGER;
AddressWidth : INTEGER );
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
address0 : IN STD_LOGIC_VECTOR (3 downto 0);
ce0 : IN STD_LOGIC;
we0 : IN STD_LOGIC;
d0 : IN STD_LOGIC_VECTOR (63 downto 0);
q0 : OUT STD_LOGIC_VECTOR (63 downto 0) );
end component;
begin
next_buckets_U : component nfa_accept_sample_multi_next_buckets
generic map (
DataWidth => 64,
AddressRange => 16,
AddressWidth => 4)
port map (
clk => ap_clk,
reset => ap_rst,
address0 => next_buckets_address0,
ce0 => next_buckets_ce0,
we0 => next_buckets_we0,
d0 => next_buckets_d0,
q0 => next_buckets_q0);
current_buckets_U : component nfa_accept_sample_multi_next_buckets
generic map (
DataWidth => 64,
AddressRange => 16,
AddressWidth => 4)
port map (
clk => ap_clk,
reset => ap_rst,
address0 => current_buckets_address0,
ce0 => current_buckets_ce0,
we0 => current_buckets_we0,
d0 => current_buckets_d0,
q0 => current_buckets_q0);
tmp_buckets_U : component nfa_accept_sample_multi_next_buckets
generic map (
DataWidth => 64,
AddressRange => 16,
AddressWidth => 4)
port map (
clk => ap_clk,
reset => ap_rst,
address0 => tmp_buckets_address0,
ce0 => tmp_buckets_ce0,
we0 => tmp_buckets_we0,
d0 => tmp_buckets_d0,
q0 => tmp_buckets_q0);
grp_nfa_get_initials_1_fu_12896 : component nfa_get_initials_1
port map (
ap_clk => ap_clk,
ap_rst => ap_rst,
ap_start => grp_nfa_get_initials_1_fu_12896_ap_start,
ap_done => grp_nfa_get_initials_1_fu_12896_ap_done,
ap_idle => grp_nfa_get_initials_1_fu_12896_ap_idle,
ap_ready => grp_nfa_get_initials_1_fu_12896_ap_ready,
nfa_initials_buckets_req_din => grp_nfa_get_initials_1_fu_12896_nfa_initials_buckets_req_din,
nfa_initials_buckets_req_full_n => grp_nfa_get_initials_1_fu_12896_nfa_initials_buckets_req_full_n,
nfa_initials_buckets_req_write => grp_nfa_get_initials_1_fu_12896_nfa_initials_buckets_req_write,
nfa_initials_buckets_rsp_empty_n => grp_nfa_get_initials_1_fu_12896_nfa_initials_buckets_rsp_empty_n,
nfa_initials_buckets_rsp_read => grp_nfa_get_initials_1_fu_12896_nfa_initials_buckets_rsp_read,
nfa_initials_buckets_address => grp_nfa_get_initials_1_fu_12896_nfa_initials_buckets_address,
nfa_initials_buckets_datain => grp_nfa_get_initials_1_fu_12896_nfa_initials_buckets_datain,
nfa_initials_buckets_dataout => grp_nfa_get_initials_1_fu_12896_nfa_initials_buckets_dataout,
nfa_initials_buckets_size => grp_nfa_get_initials_1_fu_12896_nfa_initials_buckets_size,
ap_ce => grp_nfa_get_initials_1_fu_12896_ap_ce,
initials_buckets_address0 => grp_nfa_get_initials_1_fu_12896_initials_buckets_address0,
initials_buckets_ce0 => grp_nfa_get_initials_1_fu_12896_initials_buckets_ce0,
initials_buckets_we0 => grp_nfa_get_initials_1_fu_12896_initials_buckets_we0,
initials_buckets_d0 => grp_nfa_get_initials_1_fu_12896_initials_buckets_d0,
tmp_s => grp_nfa_get_initials_1_fu_12896_tmp_s);
grp_nfa_get_finals_1_fu_12905 : component nfa_get_finals_1
port map (
ap_clk => ap_clk,
ap_rst => ap_rst,
ap_start => grp_nfa_get_finals_1_fu_12905_ap_start,
ap_done => grp_nfa_get_finals_1_fu_12905_ap_done,
ap_idle => grp_nfa_get_finals_1_fu_12905_ap_idle,
ap_ready => grp_nfa_get_finals_1_fu_12905_ap_ready,
nfa_finals_buckets_req_din => grp_nfa_get_finals_1_fu_12905_nfa_finals_buckets_req_din,
nfa_finals_buckets_req_full_n => grp_nfa_get_finals_1_fu_12905_nfa_finals_buckets_req_full_n,
nfa_finals_buckets_req_write => grp_nfa_get_finals_1_fu_12905_nfa_finals_buckets_req_write,
nfa_finals_buckets_rsp_empty_n => grp_nfa_get_finals_1_fu_12905_nfa_finals_buckets_rsp_empty_n,
nfa_finals_buckets_rsp_read => grp_nfa_get_finals_1_fu_12905_nfa_finals_buckets_rsp_read,
nfa_finals_buckets_address => grp_nfa_get_finals_1_fu_12905_nfa_finals_buckets_address,
nfa_finals_buckets_datain => grp_nfa_get_finals_1_fu_12905_nfa_finals_buckets_datain,
nfa_finals_buckets_dataout => grp_nfa_get_finals_1_fu_12905_nfa_finals_buckets_dataout,
nfa_finals_buckets_size => grp_nfa_get_finals_1_fu_12905_nfa_finals_buckets_size,
ap_ce => grp_nfa_get_finals_1_fu_12905_ap_ce,
finals_buckets_address0 => grp_nfa_get_finals_1_fu_12905_finals_buckets_address0,
finals_buckets_ce0 => grp_nfa_get_finals_1_fu_12905_finals_buckets_ce0,
finals_buckets_we0 => grp_nfa_get_finals_1_fu_12905_finals_buckets_we0,
finals_buckets_d0 => grp_nfa_get_finals_1_fu_12905_finals_buckets_d0,
tmp_28 => grp_nfa_get_finals_1_fu_12905_tmp_28);
r_bit_p_bsf32_hw_fu_12914 : component p_bsf32_hw
port map (
bus_r => r_bit_p_bsf32_hw_fu_12914_bus_r,
ap_return => r_bit_p_bsf32_hw_fu_12914_ap_return);
-- the current state (ap_CS_fsm) of the state machine. --
ap_CS_fsm_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_CS_fsm <= ap_ST_st1_fsm_0;
else
ap_CS_fsm <= ap_NS_fsm;
end if;
end if;
end process;
-- ap_return_preg assign process. --
ap_return_preg_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_return_preg <= ap_const_lv1_0;
else
if ((ap_ST_st48_fsm_47 = ap_CS_fsm)) then
ap_return_preg <= p_0_reg_12882;
end if;
end if;
end if;
end process;
-- grp_nfa_get_finals_1_fu_12905_ap_start_ap_start_reg assign process. --
grp_nfa_get_finals_1_fu_12905_ap_start_ap_start_reg_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
grp_nfa_get_finals_1_fu_12905_ap_start_ap_start_reg <= ap_const_logic_0;
else
if (((ap_ST_st19_fsm_18 = ap_CS_fsm) and (ap_ST_st24_fsm_23 = ap_NS_fsm))) then
grp_nfa_get_finals_1_fu_12905_ap_start_ap_start_reg <= ap_const_logic_1;
elsif ((ap_const_logic_1 = grp_nfa_get_finals_1_fu_12905_ap_ready)) then
grp_nfa_get_finals_1_fu_12905_ap_start_ap_start_reg <= ap_const_logic_0;
end if;
end if;
end if;
end process;
-- grp_nfa_get_initials_1_fu_12896_ap_start_ap_start_reg assign process. --
grp_nfa_get_initials_1_fu_12896_ap_start_ap_start_reg_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
grp_nfa_get_initials_1_fu_12896_ap_start_ap_start_reg <= ap_const_logic_0;
else
if (((ap_ST_st2_fsm_1 = ap_CS_fsm) and (ap_ST_st3_fsm_2 = ap_NS_fsm))) then
grp_nfa_get_initials_1_fu_12896_ap_start_ap_start_reg <= ap_const_logic_1;
elsif ((ap_const_logic_1 = grp_nfa_get_initials_1_fu_12896_ap_ready)) then
grp_nfa_get_initials_1_fu_12896_ap_start_ap_start_reg <= ap_const_logic_0;
end if;
end if;
end if;
end process;
-- all_end_1_reg_12807 assign process. --
all_end_1_reg_12807_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_ST_st46_fsm_45 = ap_CS_fsm)) then
if ((ap_const_lv1_0 = all_end_reg_12647)) then
all_end_1_reg_12807 <= ap_const_lv1_0;
elsif (ap_sig_bdd_2983) then
all_end_1_reg_12807 <= end_0_2_reg_5076;
elsif (ap_sig_bdd_2981) then
all_end_1_reg_12807 <= end_15_2_reg_4851;
elsif (ap_sig_bdd_2979) then
all_end_1_reg_12807 <= end_14_2_reg_4866;
elsif (ap_sig_bdd_2977) then
all_end_1_reg_12807 <= end_13_2_reg_4881;
elsif (ap_sig_bdd_2975) then
all_end_1_reg_12807 <= end_12_2_reg_4896;
elsif (ap_sig_bdd_2973) then
all_end_1_reg_12807 <= end_11_2_reg_4911;
elsif (ap_sig_bdd_2971) then
all_end_1_reg_12807 <= end_10_2_reg_4926;
elsif (ap_sig_bdd_2969) then
all_end_1_reg_12807 <= end_9_2_reg_4941;
elsif (ap_sig_bdd_2967) then
all_end_1_reg_12807 <= end_8_2_reg_4956;
elsif (ap_sig_bdd_2965) then
all_end_1_reg_12807 <= end_7_2_reg_4971;
elsif (ap_sig_bdd_2963) then
all_end_1_reg_12807 <= end_6_2_reg_4986;
elsif (ap_sig_bdd_2961) then
all_end_1_reg_12807 <= end_5_2_reg_5001;
elsif (ap_sig_bdd_2959) then
all_end_1_reg_12807 <= end_4_2_reg_5016;
elsif (ap_sig_bdd_2957) then
all_end_1_reg_12807 <= end_3_2_reg_5031;
elsif (ap_sig_bdd_2955) then
all_end_1_reg_12807 <= end_2_2_reg_5046;
elsif (ap_sig_bdd_2953) then
all_end_1_reg_12807 <= end_1_2_reg_5061;
end if;
end if;
end if;
end process;
-- all_end_reg_12647 assign process. --
all_end_reg_12647_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ST_st19_fsm_18 = ap_CS_fsm) and (ap_const_lv1_0 = tmp_9_fu_13539_p2))) then
all_end_reg_12647 <= ap_const_lv1_1;
elsif ((((ap_ST_st47_fsm_46 = ap_CS_fsm) and not((tmp_38_reg_14781 = ap_const_lv4_E)) and not((tmp_38_reg_14781 = ap_const_lv4_D)) and not((tmp_38_reg_14781 = ap_const_lv4_C)) and not((tmp_38_reg_14781 = ap_const_lv4_B)) and not((tmp_38_reg_14781 = ap_const_lv4_A)) and not((tmp_38_reg_14781 = ap_const_lv4_9)) and not((tmp_38_reg_14781 = ap_const_lv4_8)) and not((tmp_38_reg_14781 = ap_const_lv4_7)) and not((tmp_38_reg_14781 = ap_const_lv4_6)) and not((tmp_38_reg_14781 = ap_const_lv4_5)) and not((tmp_38_reg_14781 = ap_const_lv4_4)) and not((tmp_38_reg_14781 = ap_const_lv4_3)) and not((tmp_38_reg_14781 = ap_const_lv4_2)) and not((tmp_38_reg_14781 = ap_const_lv4_1)) and not((tmp_38_reg_14781 = ap_const_lv4_0)) and (ap_const_lv1_0 = any_end_reg_12691)) or ((ap_ST_st47_fsm_46 = ap_CS_fsm) and (tmp_38_reg_14781 = ap_const_lv4_E) and (ap_const_lv1_0 = any_end_reg_12691)) or ((ap_ST_st47_fsm_46 = ap_CS_fsm) and (tmp_38_reg_14781 = ap_const_lv4_D) and (ap_const_lv1_0 = any_end_reg_12691)) or ((ap_ST_st47_fsm_46 = ap_CS_fsm) and (tmp_38_reg_14781 = ap_const_lv4_C) and (ap_const_lv1_0 = any_end_reg_12691)) or ((ap_ST_st47_fsm_46 = ap_CS_fsm) and (tmp_38_reg_14781 = ap_const_lv4_B) and (ap_const_lv1_0 = any_end_reg_12691)) or ((ap_ST_st47_fsm_46 = ap_CS_fsm) and (tmp_38_reg_14781 = ap_const_lv4_A) and (ap_const_lv1_0 = any_end_reg_12691)) or ((ap_ST_st47_fsm_46 = ap_CS_fsm) and (tmp_38_reg_14781 = ap_const_lv4_9) and (ap_const_lv1_0 = any_end_reg_12691)) or ((ap_ST_st47_fsm_46 = ap_CS_fsm) and (tmp_38_reg_14781 = ap_const_lv4_8) and (ap_const_lv1_0 = any_end_reg_12691)) or ((ap_ST_st47_fsm_46 = ap_CS_fsm) and (tmp_38_reg_14781 = ap_const_lv4_7) and (ap_const_lv1_0 = any_end_reg_12691)) or ((ap_ST_st47_fsm_46 = ap_CS_fsm) and (tmp_38_reg_14781 = ap_const_lv4_6) and (ap_const_lv1_0 = any_end_reg_12691)) or ((ap_ST_st47_fsm_46 = ap_CS_fsm) and (tmp_38_reg_14781 = ap_const_lv4_5) and (ap_const_lv1_0 = any_end_reg_12691)) or ((ap_ST_st47_fsm_46 = ap_CS_fsm) and (tmp_38_reg_14781 = ap_const_lv4_4) and (ap_const_lv1_0 = any_end_reg_12691)) or ((ap_ST_st47_fsm_46 = ap_CS_fsm) and (tmp_38_reg_14781 = ap_const_lv4_3) and (ap_const_lv1_0 = any_end_reg_12691)) or ((ap_ST_st47_fsm_46 = ap_CS_fsm) and (tmp_38_reg_14781 = ap_const_lv4_2) and (ap_const_lv1_0 = any_end_reg_12691)) or ((ap_ST_st47_fsm_46 = ap_CS_fsm) and (tmp_38_reg_14781 = ap_const_lv4_1) and (ap_const_lv1_0 = any_end_reg_12691)) or ((ap_ST_st47_fsm_46 = ap_CS_fsm) and (tmp_38_reg_14781 = ap_const_lv4_0) and (ap_const_lv1_0 = any_end_reg_12691)) or ((ap_ST_st47_fsm_46 = ap_CS_fsm) and not((ap_const_lv1_0 = any_end_reg_12691))))) then
all_end_reg_12647 <= all_end_1_reg_12807;
end if;
end if;
end process;
-- any_end_reg_12691 assign process. --
any_end_reg_12691_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ST_st47_fsm_46 = ap_CS_fsm) and not((ap_const_lv1_0 = any_end_reg_12691)))) then
any_end_reg_12691 <= ap_const_lv1_1;
elsif (((ap_ST_st19_fsm_18 = ap_CS_fsm) and (ap_const_lv1_0 = tmp_9_fu_13539_p2))) then
any_end_reg_12691 <= ap_const_lv1_0;
elsif (((ap_ST_st47_fsm_46 = ap_CS_fsm) and (tmp_38_reg_14781 = ap_const_lv4_0) and (ap_const_lv1_0 = any_end_reg_12691))) then
any_end_reg_12691 <= end_0_2_reg_5076;
elsif (((ap_ST_st47_fsm_46 = ap_CS_fsm) and not((tmp_38_reg_14781 = ap_const_lv4_E)) and not((tmp_38_reg_14781 = ap_const_lv4_D)) and not((tmp_38_reg_14781 = ap_const_lv4_C)) and not((tmp_38_reg_14781 = ap_const_lv4_B)) and not((tmp_38_reg_14781 = ap_const_lv4_A)) and not((tmp_38_reg_14781 = ap_const_lv4_9)) and not((tmp_38_reg_14781 = ap_const_lv4_8)) and not((tmp_38_reg_14781 = ap_const_lv4_7)) and not((tmp_38_reg_14781 = ap_const_lv4_6)) and not((tmp_38_reg_14781 = ap_const_lv4_5)) and not((tmp_38_reg_14781 = ap_const_lv4_4)) and not((tmp_38_reg_14781 = ap_const_lv4_3)) and not((tmp_38_reg_14781 = ap_const_lv4_2)) and not((tmp_38_reg_14781 = ap_const_lv4_1)) and not((tmp_38_reg_14781 = ap_const_lv4_0)) and (ap_const_lv1_0 = any_end_reg_12691))) then
any_end_reg_12691 <= end_15_2_reg_4851;
elsif (((ap_ST_st47_fsm_46 = ap_CS_fsm) and (tmp_38_reg_14781 = ap_const_lv4_E) and (ap_const_lv1_0 = any_end_reg_12691))) then
any_end_reg_12691 <= end_14_2_reg_4866;
elsif (((ap_ST_st47_fsm_46 = ap_CS_fsm) and (tmp_38_reg_14781 = ap_const_lv4_D) and (ap_const_lv1_0 = any_end_reg_12691))) then
any_end_reg_12691 <= end_13_2_reg_4881;
elsif (((ap_ST_st47_fsm_46 = ap_CS_fsm) and (tmp_38_reg_14781 = ap_const_lv4_C) and (ap_const_lv1_0 = any_end_reg_12691))) then
any_end_reg_12691 <= end_12_2_reg_4896;
elsif (((ap_ST_st47_fsm_46 = ap_CS_fsm) and (tmp_38_reg_14781 = ap_const_lv4_B) and (ap_const_lv1_0 = any_end_reg_12691))) then
any_end_reg_12691 <= end_11_2_reg_4911;
elsif (((ap_ST_st47_fsm_46 = ap_CS_fsm) and (tmp_38_reg_14781 = ap_const_lv4_A) and (ap_const_lv1_0 = any_end_reg_12691))) then
any_end_reg_12691 <= end_10_2_reg_4926;
elsif (((ap_ST_st47_fsm_46 = ap_CS_fsm) and (tmp_38_reg_14781 = ap_const_lv4_9) and (ap_const_lv1_0 = any_end_reg_12691))) then
any_end_reg_12691 <= end_9_2_reg_4941;
elsif (((ap_ST_st47_fsm_46 = ap_CS_fsm) and (tmp_38_reg_14781 = ap_const_lv4_8) and (ap_const_lv1_0 = any_end_reg_12691))) then
any_end_reg_12691 <= end_8_2_reg_4956;
elsif (((ap_ST_st47_fsm_46 = ap_CS_fsm) and (tmp_38_reg_14781 = ap_const_lv4_7) and (ap_const_lv1_0 = any_end_reg_12691))) then
any_end_reg_12691 <= end_7_2_reg_4971;
elsif (((ap_ST_st47_fsm_46 = ap_CS_fsm) and (tmp_38_reg_14781 = ap_const_lv4_6) and (ap_const_lv1_0 = any_end_reg_12691))) then
any_end_reg_12691 <= end_6_2_reg_4986;
elsif (((ap_ST_st47_fsm_46 = ap_CS_fsm) and (tmp_38_reg_14781 = ap_const_lv4_5) and (ap_const_lv1_0 = any_end_reg_12691))) then
any_end_reg_12691 <= end_5_2_reg_5001;
elsif (((ap_ST_st47_fsm_46 = ap_CS_fsm) and (tmp_38_reg_14781 = ap_const_lv4_4) and (ap_const_lv1_0 = any_end_reg_12691))) then
any_end_reg_12691 <= end_4_2_reg_5016;
elsif (((ap_ST_st47_fsm_46 = ap_CS_fsm) and (tmp_38_reg_14781 = ap_const_lv4_3) and (ap_const_lv1_0 = any_end_reg_12691))) then
any_end_reg_12691 <= end_3_2_reg_5031;
elsif (((ap_ST_st47_fsm_46 = ap_CS_fsm) and (tmp_38_reg_14781 = ap_const_lv4_2) and (ap_const_lv1_0 = any_end_reg_12691))) then
any_end_reg_12691 <= end_2_2_reg_5046;
elsif (((ap_ST_st47_fsm_46 = ap_CS_fsm) and (tmp_38_reg_14781 = ap_const_lv4_1) and (ap_const_lv1_0 = any_end_reg_12691))) then
any_end_reg_12691 <= end_1_2_reg_5061;
end if;
end if;
end process;
-- any_state_0_1_reg_1726 assign process. --
any_state_0_1_reg_1726_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_ST_st17_fsm_16 = ap_CS_fsm)) then
any_state_0_1_reg_1726 <= any_state_0_2_reg_3628;
elsif (((ap_ST_st7_fsm_6 = ap_CS_fsm) and (ap_const_lv1_0 = tmp_6_fu_13097_p2))) then
any_state_0_1_reg_1726 <= any_state_reg_1188;
end if;
end if;
end process;
-- any_state_0_2_reg_3628 assign process. --
any_state_0_2_reg_3628_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((tmp_36_reg_14538 = ap_const_lv4_0) and (ap_ST_st10_fsm_9 = ap_CS_fsm))) then
any_state_0_2_reg_3628 <= ap_const_lv1_0;
elsif (((ap_ST_st10_fsm_9 = ap_CS_fsm) or ((tmp_36_reg_14538 = ap_const_lv4_E) and (ap_ST_st10_fsm_9 = ap_CS_fsm)) or ((tmp_36_reg_14538 = ap_const_lv4_D) and (ap_ST_st10_fsm_9 = ap_CS_fsm)) or ((tmp_36_reg_14538 = ap_const_lv4_C) and (ap_ST_st10_fsm_9 = ap_CS_fsm)) or ((tmp_36_reg_14538 = ap_const_lv4_B) and (ap_ST_st10_fsm_9 = ap_CS_fsm)) or ((tmp_36_reg_14538 = ap_const_lv4_A) and (ap_ST_st10_fsm_9 = ap_CS_fsm)) or ((tmp_36_reg_14538 = ap_const_lv4_9) and (ap_ST_st10_fsm_9 = ap_CS_fsm)) or ((tmp_36_reg_14538 = ap_const_lv4_8) and (ap_ST_st10_fsm_9 = ap_CS_fsm)) or ((tmp_36_reg_14538 = ap_const_lv4_7) and (ap_ST_st10_fsm_9 = ap_CS_fsm)) or ((tmp_36_reg_14538 = ap_const_lv4_6) and (ap_ST_st10_fsm_9 = ap_CS_fsm)) or ((tmp_36_reg_14538 = ap_const_lv4_5) and (ap_ST_st10_fsm_9 = ap_CS_fsm)) or ((tmp_36_reg_14538 = ap_const_lv4_4) and (ap_ST_st10_fsm_9 = ap_CS_fsm)) or ((tmp_36_reg_14538 = ap_const_lv4_3) and (ap_ST_st10_fsm_9 = ap_CS_fsm)) or ((tmp_36_reg_14538 = ap_const_lv4_2) and (ap_ST_st10_fsm_9 = ap_CS_fsm)) or ((tmp_36_reg_14538 = ap_const_lv4_1) and (ap_ST_st10_fsm_9 = ap_CS_fsm)))) then
any_state_0_2_reg_3628 <= any_state_0_1_reg_1726;
end if;
end if;
end process;
-- any_state_0_3_reg_4248 assign process. --
any_state_0_3_reg_4248_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ST_st44_fsm_43 = ap_CS_fsm) and not((ap_const_lv1_0 = exitcond_fu_13718_p2)) and (ap_const_lv1_0 = all_end_phi_fu_12651_p36))) then
any_state_0_3_reg_4248 <= any_state_0_4_reg_5316;
elsif (((ap_ST_st8_fsm_7 = ap_CS_fsm) and not((exitcond2_fu_13247_p2 = ap_const_lv1_0)))) then
any_state_0_3_reg_4248 <= any_state_0_1_reg_1726;
end if;
end if;
end process;
-- any_state_0_4_reg_5316 assign process. --
any_state_0_4_reg_5316_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ST_st43_fsm_42 = ap_CS_fsm) or ((ap_ST_st32_fsm_31 = ap_CS_fsm) and ((not((ap_const_lv1_0 = end_load_3_phi_phi_fu_11584_p32)) and (ap_const_lv1_0 = brmerge_demorgan_reg_14680)) or (not((ap_const_lv1_0 = end_load_3_phi_phi_fu_11584_p32)) and not((ap_const_lv1_0 = tmp1_fu_13626_p2))))))) then
any_state_0_4_reg_5316 <= any_state_0_6_reg_10525;
elsif ((ap_ST_st18_fsm_17 = ap_CS_fsm)) then
any_state_0_4_reg_5316 <= any_state_0_3_reg_4248;
end if;
end if;
end process;
-- any_state_0_5_reg_8582 assign process. --
any_state_0_5_reg_8582_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and (ap_const_lv1_0 = end_0_phi_fu_5844_p32) and (tmp_37_fu_13557_p1 = ap_const_lv4_0))) then
any_state_0_5_reg_8582 <= ap_const_lv1_1;
elsif ((((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and (ap_const_lv1_0 = end_0_phi_fu_5844_p32)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and (ap_const_lv1_0 = end_0_phi_fu_5844_p32) and (tmp_37_fu_13557_p1 = ap_const_lv4_D)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and (ap_const_lv1_0 = end_0_phi_fu_5844_p32) and (tmp_37_fu_13557_p1 = ap_const_lv4_C)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and (ap_const_lv1_0 = end_0_phi_fu_5844_p32) and (tmp_37_fu_13557_p1 = ap_const_lv4_B)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and (ap_const_lv1_0 = end_0_phi_fu_5844_p32) and (tmp_37_fu_13557_p1 = ap_const_lv4_A)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and (ap_const_lv1_0 = end_0_phi_fu_5844_p32) and (tmp_37_fu_13557_p1 = ap_const_lv4_9)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and (ap_const_lv1_0 = end_0_phi_fu_5844_p32) and (tmp_37_fu_13557_p1 = ap_const_lv4_8)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and (ap_const_lv1_0 = end_0_phi_fu_5844_p32) and (tmp_37_fu_13557_p1 = ap_const_lv4_7)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and (ap_const_lv1_0 = end_0_phi_fu_5844_p32) and (tmp_37_fu_13557_p1 = ap_const_lv4_6)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and (ap_const_lv1_0 = end_0_phi_fu_5844_p32) and (tmp_37_fu_13557_p1 = ap_const_lv4_5)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and (ap_const_lv1_0 = end_0_phi_fu_5844_p32) and (tmp_37_fu_13557_p1 = ap_const_lv4_4)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and (ap_const_lv1_0 = end_0_phi_fu_5844_p32) and (tmp_37_fu_13557_p1 = ap_const_lv4_3)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and (ap_const_lv1_0 = end_0_phi_fu_5844_p32) and (tmp_37_fu_13557_p1 = ap_const_lv4_2)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and (ap_const_lv1_0 = end_0_phi_fu_5844_p32) and (tmp_37_fu_13557_p1 = ap_const_lv4_1)))) then
any_state_0_5_reg_8582 <= any_state_0_4_reg_5316;
end if;
end if;
end process;
-- any_state_0_6_reg_10525 assign process. --
any_state_0_6_reg_10525_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ST_st30_fsm_29 = ap_CS_fsm) and not((ap_const_lv1_0 = end_0_reg_5841)))) then
any_state_0_6_reg_10525 <= any_state_0_4_reg_5316;
elsif ((((ap_ST_st22_fsm_21 = ap_CS_fsm) and not((tmp_37_reg_14631 = ap_const_lv4_E)) and not((tmp_37_reg_14631 = ap_const_lv4_D)) and not((tmp_37_reg_14631 = ap_const_lv4_C)) and not((tmp_37_reg_14631 = ap_const_lv4_B)) and not((tmp_37_reg_14631 = ap_const_lv4_A)) and not((tmp_37_reg_14631 = ap_const_lv4_9)) and not((tmp_37_reg_14631 = ap_const_lv4_8)) and not((tmp_37_reg_14631 = ap_const_lv4_7)) and not((tmp_37_reg_14631 = ap_const_lv4_6)) and not((tmp_37_reg_14631 = ap_const_lv4_5)) and not((tmp_37_reg_14631 = ap_const_lv4_4)) and not((tmp_37_reg_14631 = ap_const_lv4_3)) and not((tmp_37_reg_14631 = ap_const_lv4_2)) and not((tmp_37_reg_14631 = ap_const_lv4_1)) and not((tmp_37_reg_14631 = ap_const_lv4_0))) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_E)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_D)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_C)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_B)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_A)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_9)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_8)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_7)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_6)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_5)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_4)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_3)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_2)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_1)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_0)))) then
any_state_0_6_reg_10525 <= any_state_0_5_reg_8582;
end if;
end if;
end process;
-- any_state_10_1_reg_1616 assign process. --
any_state_10_1_reg_1616_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_ST_st17_fsm_16 = ap_CS_fsm)) then
any_state_10_1_reg_1616 <= any_state_10_2_reg_3068;
elsif (((ap_ST_st7_fsm_6 = ap_CS_fsm) and (ap_const_lv1_0 = tmp_6_fu_13097_p2))) then
any_state_10_1_reg_1616 <= any_state_10_reg_1068;
end if;
end if;
end process;
-- any_state_10_2_reg_3068 assign process. --
any_state_10_2_reg_3068_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((tmp_36_reg_14538 = ap_const_lv4_A) and (ap_ST_st10_fsm_9 = ap_CS_fsm))) then
any_state_10_2_reg_3068 <= ap_const_lv1_0;
elsif (((ap_ST_st10_fsm_9 = ap_CS_fsm) or ((tmp_36_reg_14538 = ap_const_lv4_E) and (ap_ST_st10_fsm_9 = ap_CS_fsm)) or ((tmp_36_reg_14538 = ap_const_lv4_D) and (ap_ST_st10_fsm_9 = ap_CS_fsm)) or ((tmp_36_reg_14538 = ap_const_lv4_C) and (ap_ST_st10_fsm_9 = ap_CS_fsm)) or ((tmp_36_reg_14538 = ap_const_lv4_B) and (ap_ST_st10_fsm_9 = ap_CS_fsm)) or ((tmp_36_reg_14538 = ap_const_lv4_9) and (ap_ST_st10_fsm_9 = ap_CS_fsm)) or ((tmp_36_reg_14538 = ap_const_lv4_8) and (ap_ST_st10_fsm_9 = ap_CS_fsm)) or ((tmp_36_reg_14538 = ap_const_lv4_7) and (ap_ST_st10_fsm_9 = ap_CS_fsm)) or ((tmp_36_reg_14538 = ap_const_lv4_6) and (ap_ST_st10_fsm_9 = ap_CS_fsm)) or ((tmp_36_reg_14538 = ap_const_lv4_5) and (ap_ST_st10_fsm_9 = ap_CS_fsm)) or ((tmp_36_reg_14538 = ap_const_lv4_4) and (ap_ST_st10_fsm_9 = ap_CS_fsm)) or ((tmp_36_reg_14538 = ap_const_lv4_3) and (ap_ST_st10_fsm_9 = ap_CS_fsm)) or ((tmp_36_reg_14538 = ap_const_lv4_2) and (ap_ST_st10_fsm_9 = ap_CS_fsm)) or ((tmp_36_reg_14538 = ap_const_lv4_1) and (ap_ST_st10_fsm_9 = ap_CS_fsm)) or ((tmp_36_reg_14538 = ap_const_lv4_0) and (ap_ST_st10_fsm_9 = ap_CS_fsm)))) then
any_state_10_2_reg_3068 <= any_state_10_1_reg_1616;
end if;
end if;
end process;
-- any_state_10_3_reg_4138 assign process. --
any_state_10_3_reg_4138_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ST_st44_fsm_43 = ap_CS_fsm) and not((ap_const_lv1_0 = exitcond_fu_13718_p2)) and (ap_const_lv1_0 = all_end_phi_fu_12651_p36))) then
any_state_10_3_reg_4138 <= any_state_10_4_reg_5166;
elsif (((ap_ST_st8_fsm_7 = ap_CS_fsm) and not((exitcond2_fu_13247_p2 = ap_const_lv1_0)))) then
any_state_10_3_reg_4138 <= any_state_10_1_reg_1616;
end if;
end if;
end process;
-- any_state_10_4_reg_5166 assign process. --
any_state_10_4_reg_5166_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ST_st43_fsm_42 = ap_CS_fsm) or ((ap_ST_st32_fsm_31 = ap_CS_fsm) and ((not((ap_const_lv1_0 = end_load_3_phi_phi_fu_11584_p32)) and (ap_const_lv1_0 = brmerge_demorgan_reg_14680)) or (not((ap_const_lv1_0 = end_load_3_phi_phi_fu_11584_p32)) and not((ap_const_lv1_0 = tmp1_fu_13626_p2))))))) then
any_state_10_4_reg_5166 <= any_state_10_6_reg_9935;
elsif ((ap_ST_st18_fsm_17 = ap_CS_fsm)) then
any_state_10_4_reg_5166 <= any_state_10_3_reg_4138;
end if;
end if;
end process;
-- any_state_10_5_reg_8032 assign process. --
any_state_10_5_reg_8032_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and (ap_const_lv1_0 = end_0_phi_fu_5844_p32) and (tmp_37_fu_13557_p1 = ap_const_lv4_A))) then
any_state_10_5_reg_8032 <= ap_const_lv1_1;
elsif ((((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and (ap_const_lv1_0 = end_0_phi_fu_5844_p32)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and (ap_const_lv1_0 = end_0_phi_fu_5844_p32) and (tmp_37_fu_13557_p1 = ap_const_lv4_D)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and (ap_const_lv1_0 = end_0_phi_fu_5844_p32) and (tmp_37_fu_13557_p1 = ap_const_lv4_C)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and (ap_const_lv1_0 = end_0_phi_fu_5844_p32) and (tmp_37_fu_13557_p1 = ap_const_lv4_B)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and (ap_const_lv1_0 = end_0_phi_fu_5844_p32) and (tmp_37_fu_13557_p1 = ap_const_lv4_9)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and (ap_const_lv1_0 = end_0_phi_fu_5844_p32) and (tmp_37_fu_13557_p1 = ap_const_lv4_8)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and (ap_const_lv1_0 = end_0_phi_fu_5844_p32) and (tmp_37_fu_13557_p1 = ap_const_lv4_7)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and (ap_const_lv1_0 = end_0_phi_fu_5844_p32) and (tmp_37_fu_13557_p1 = ap_const_lv4_6)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and (ap_const_lv1_0 = end_0_phi_fu_5844_p32) and (tmp_37_fu_13557_p1 = ap_const_lv4_5)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and (ap_const_lv1_0 = end_0_phi_fu_5844_p32) and (tmp_37_fu_13557_p1 = ap_const_lv4_4)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and (ap_const_lv1_0 = end_0_phi_fu_5844_p32) and (tmp_37_fu_13557_p1 = ap_const_lv4_3)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and (ap_const_lv1_0 = end_0_phi_fu_5844_p32) and (tmp_37_fu_13557_p1 = ap_const_lv4_2)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and (ap_const_lv1_0 = end_0_phi_fu_5844_p32) and (tmp_37_fu_13557_p1 = ap_const_lv4_1)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and (ap_const_lv1_0 = end_0_phi_fu_5844_p32) and (tmp_37_fu_13557_p1 = ap_const_lv4_0)))) then
any_state_10_5_reg_8032 <= any_state_10_4_reg_5166;
end if;
end if;
end process;
-- any_state_10_6_reg_9935 assign process. --
any_state_10_6_reg_9935_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ST_st30_fsm_29 = ap_CS_fsm) and not((ap_const_lv1_0 = end_0_reg_5841)))) then
any_state_10_6_reg_9935 <= any_state_10_4_reg_5166;
elsif ((((ap_ST_st22_fsm_21 = ap_CS_fsm) and not((tmp_37_reg_14631 = ap_const_lv4_E)) and not((tmp_37_reg_14631 = ap_const_lv4_D)) and not((tmp_37_reg_14631 = ap_const_lv4_C)) and not((tmp_37_reg_14631 = ap_const_lv4_B)) and not((tmp_37_reg_14631 = ap_const_lv4_A)) and not((tmp_37_reg_14631 = ap_const_lv4_9)) and not((tmp_37_reg_14631 = ap_const_lv4_8)) and not((tmp_37_reg_14631 = ap_const_lv4_7)) and not((tmp_37_reg_14631 = ap_const_lv4_6)) and not((tmp_37_reg_14631 = ap_const_lv4_5)) and not((tmp_37_reg_14631 = ap_const_lv4_4)) and not((tmp_37_reg_14631 = ap_const_lv4_3)) and not((tmp_37_reg_14631 = ap_const_lv4_2)) and not((tmp_37_reg_14631 = ap_const_lv4_1)) and not((tmp_37_reg_14631 = ap_const_lv4_0))) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_E)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_D)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_C)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_B)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_A)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_9)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_8)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_7)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_6)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_5)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_4)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_3)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_2)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_1)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_0)))) then
any_state_10_6_reg_9935 <= any_state_10_5_reg_8032;
end if;
end if;
end process;
-- any_state_11_1_reg_1605 assign process. --
any_state_11_1_reg_1605_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_ST_st17_fsm_16 = ap_CS_fsm)) then
any_state_11_1_reg_1605 <= any_state_11_2_reg_3012;
elsif (((ap_ST_st7_fsm_6 = ap_CS_fsm) and (ap_const_lv1_0 = tmp_6_fu_13097_p2))) then
any_state_11_1_reg_1605 <= any_state_11_reg_1056;
end if;
end if;
end process;
-- any_state_11_2_reg_3012 assign process. --
any_state_11_2_reg_3012_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((tmp_36_reg_14538 = ap_const_lv4_B) and (ap_ST_st10_fsm_9 = ap_CS_fsm))) then
any_state_11_2_reg_3012 <= ap_const_lv1_0;
elsif (((ap_ST_st10_fsm_9 = ap_CS_fsm) or ((tmp_36_reg_14538 = ap_const_lv4_E) and (ap_ST_st10_fsm_9 = ap_CS_fsm)) or ((tmp_36_reg_14538 = ap_const_lv4_D) and (ap_ST_st10_fsm_9 = ap_CS_fsm)) or ((tmp_36_reg_14538 = ap_const_lv4_C) and (ap_ST_st10_fsm_9 = ap_CS_fsm)) or ((tmp_36_reg_14538 = ap_const_lv4_A) and (ap_ST_st10_fsm_9 = ap_CS_fsm)) or ((tmp_36_reg_14538 = ap_const_lv4_9) and (ap_ST_st10_fsm_9 = ap_CS_fsm)) or ((tmp_36_reg_14538 = ap_const_lv4_8) and (ap_ST_st10_fsm_9 = ap_CS_fsm)) or ((tmp_36_reg_14538 = ap_const_lv4_7) and (ap_ST_st10_fsm_9 = ap_CS_fsm)) or ((tmp_36_reg_14538 = ap_const_lv4_6) and (ap_ST_st10_fsm_9 = ap_CS_fsm)) or ((tmp_36_reg_14538 = ap_const_lv4_5) and (ap_ST_st10_fsm_9 = ap_CS_fsm)) or ((tmp_36_reg_14538 = ap_const_lv4_4) and (ap_ST_st10_fsm_9 = ap_CS_fsm)) or ((tmp_36_reg_14538 = ap_const_lv4_3) and (ap_ST_st10_fsm_9 = ap_CS_fsm)) or ((tmp_36_reg_14538 = ap_const_lv4_2) and (ap_ST_st10_fsm_9 = ap_CS_fsm)) or ((tmp_36_reg_14538 = ap_const_lv4_1) and (ap_ST_st10_fsm_9 = ap_CS_fsm)) or ((tmp_36_reg_14538 = ap_const_lv4_0) and (ap_ST_st10_fsm_9 = ap_CS_fsm)))) then
any_state_11_2_reg_3012 <= any_state_11_1_reg_1605;
end if;
end if;
end process;
-- any_state_11_3_reg_4127 assign process. --
any_state_11_3_reg_4127_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ST_st44_fsm_43 = ap_CS_fsm) and not((ap_const_lv1_0 = exitcond_fu_13718_p2)) and (ap_const_lv1_0 = all_end_phi_fu_12651_p36))) then
any_state_11_3_reg_4127 <= any_state_11_4_reg_5151;
elsif (((ap_ST_st8_fsm_7 = ap_CS_fsm) and not((exitcond2_fu_13247_p2 = ap_const_lv1_0)))) then
any_state_11_3_reg_4127 <= any_state_11_1_reg_1605;
end if;
end if;
end process;
-- any_state_11_4_reg_5151 assign process. --
any_state_11_4_reg_5151_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ST_st43_fsm_42 = ap_CS_fsm) or ((ap_ST_st32_fsm_31 = ap_CS_fsm) and ((not((ap_const_lv1_0 = end_load_3_phi_phi_fu_11584_p32)) and (ap_const_lv1_0 = brmerge_demorgan_reg_14680)) or (not((ap_const_lv1_0 = end_load_3_phi_phi_fu_11584_p32)) and not((ap_const_lv1_0 = tmp1_fu_13626_p2))))))) then
any_state_11_4_reg_5151 <= any_state_11_6_reg_9876;
elsif ((ap_ST_st18_fsm_17 = ap_CS_fsm)) then
any_state_11_4_reg_5151 <= any_state_11_3_reg_4127;
end if;
end if;
end process;
-- any_state_11_5_reg_7977 assign process. --
any_state_11_5_reg_7977_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and (ap_const_lv1_0 = end_0_phi_fu_5844_p32) and (tmp_37_fu_13557_p1 = ap_const_lv4_B))) then
any_state_11_5_reg_7977 <= ap_const_lv1_1;
elsif ((((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and (ap_const_lv1_0 = end_0_phi_fu_5844_p32)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and (ap_const_lv1_0 = end_0_phi_fu_5844_p32) and (tmp_37_fu_13557_p1 = ap_const_lv4_D)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and (ap_const_lv1_0 = end_0_phi_fu_5844_p32) and (tmp_37_fu_13557_p1 = ap_const_lv4_C)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and (ap_const_lv1_0 = end_0_phi_fu_5844_p32) and (tmp_37_fu_13557_p1 = ap_const_lv4_A)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and (ap_const_lv1_0 = end_0_phi_fu_5844_p32) and (tmp_37_fu_13557_p1 = ap_const_lv4_9)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and (ap_const_lv1_0 = end_0_phi_fu_5844_p32) and (tmp_37_fu_13557_p1 = ap_const_lv4_8)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and (ap_const_lv1_0 = end_0_phi_fu_5844_p32) and (tmp_37_fu_13557_p1 = ap_const_lv4_7)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and (ap_const_lv1_0 = end_0_phi_fu_5844_p32) and (tmp_37_fu_13557_p1 = ap_const_lv4_6)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and (ap_const_lv1_0 = end_0_phi_fu_5844_p32) and (tmp_37_fu_13557_p1 = ap_const_lv4_5)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and (ap_const_lv1_0 = end_0_phi_fu_5844_p32) and (tmp_37_fu_13557_p1 = ap_const_lv4_4)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and (ap_const_lv1_0 = end_0_phi_fu_5844_p32) and (tmp_37_fu_13557_p1 = ap_const_lv4_3)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and (ap_const_lv1_0 = end_0_phi_fu_5844_p32) and (tmp_37_fu_13557_p1 = ap_const_lv4_2)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and (ap_const_lv1_0 = end_0_phi_fu_5844_p32) and (tmp_37_fu_13557_p1 = ap_const_lv4_1)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and (ap_const_lv1_0 = end_0_phi_fu_5844_p32) and (tmp_37_fu_13557_p1 = ap_const_lv4_0)))) then
any_state_11_5_reg_7977 <= any_state_11_4_reg_5151;
end if;
end if;
end process;
-- any_state_11_6_reg_9876 assign process. --
any_state_11_6_reg_9876_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ST_st30_fsm_29 = ap_CS_fsm) and not((ap_const_lv1_0 = end_0_reg_5841)))) then
any_state_11_6_reg_9876 <= any_state_11_4_reg_5151;
elsif ((((ap_ST_st22_fsm_21 = ap_CS_fsm) and not((tmp_37_reg_14631 = ap_const_lv4_E)) and not((tmp_37_reg_14631 = ap_const_lv4_D)) and not((tmp_37_reg_14631 = ap_const_lv4_C)) and not((tmp_37_reg_14631 = ap_const_lv4_B)) and not((tmp_37_reg_14631 = ap_const_lv4_A)) and not((tmp_37_reg_14631 = ap_const_lv4_9)) and not((tmp_37_reg_14631 = ap_const_lv4_8)) and not((tmp_37_reg_14631 = ap_const_lv4_7)) and not((tmp_37_reg_14631 = ap_const_lv4_6)) and not((tmp_37_reg_14631 = ap_const_lv4_5)) and not((tmp_37_reg_14631 = ap_const_lv4_4)) and not((tmp_37_reg_14631 = ap_const_lv4_3)) and not((tmp_37_reg_14631 = ap_const_lv4_2)) and not((tmp_37_reg_14631 = ap_const_lv4_1)) and not((tmp_37_reg_14631 = ap_const_lv4_0))) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_E)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_D)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_C)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_B)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_A)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_9)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_8)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_7)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_6)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_5)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_4)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_3)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_2)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_1)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_0)))) then
any_state_11_6_reg_9876 <= any_state_11_5_reg_7977;
end if;
end if;
end process;
-- any_state_12_1_reg_1594 assign process. --
any_state_12_1_reg_1594_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_ST_st17_fsm_16 = ap_CS_fsm)) then
any_state_12_1_reg_1594 <= any_state_12_2_reg_2956;
elsif (((ap_ST_st7_fsm_6 = ap_CS_fsm) and (ap_const_lv1_0 = tmp_6_fu_13097_p2))) then
any_state_12_1_reg_1594 <= any_state_12_reg_1044;
end if;
end if;
end process;
-- any_state_12_2_reg_2956 assign process. --
any_state_12_2_reg_2956_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((tmp_36_reg_14538 = ap_const_lv4_C) and (ap_ST_st10_fsm_9 = ap_CS_fsm))) then
any_state_12_2_reg_2956 <= ap_const_lv1_0;
elsif (((ap_ST_st10_fsm_9 = ap_CS_fsm) or ((tmp_36_reg_14538 = ap_const_lv4_E) and (ap_ST_st10_fsm_9 = ap_CS_fsm)) or ((tmp_36_reg_14538 = ap_const_lv4_D) and (ap_ST_st10_fsm_9 = ap_CS_fsm)) or ((tmp_36_reg_14538 = ap_const_lv4_B) and (ap_ST_st10_fsm_9 = ap_CS_fsm)) or ((tmp_36_reg_14538 = ap_const_lv4_A) and (ap_ST_st10_fsm_9 = ap_CS_fsm)) or ((tmp_36_reg_14538 = ap_const_lv4_9) and (ap_ST_st10_fsm_9 = ap_CS_fsm)) or ((tmp_36_reg_14538 = ap_const_lv4_8) and (ap_ST_st10_fsm_9 = ap_CS_fsm)) or ((tmp_36_reg_14538 = ap_const_lv4_7) and (ap_ST_st10_fsm_9 = ap_CS_fsm)) or ((tmp_36_reg_14538 = ap_const_lv4_6) and (ap_ST_st10_fsm_9 = ap_CS_fsm)) or ((tmp_36_reg_14538 = ap_const_lv4_5) and (ap_ST_st10_fsm_9 = ap_CS_fsm)) or ((tmp_36_reg_14538 = ap_const_lv4_4) and (ap_ST_st10_fsm_9 = ap_CS_fsm)) or ((tmp_36_reg_14538 = ap_const_lv4_3) and (ap_ST_st10_fsm_9 = ap_CS_fsm)) or ((tmp_36_reg_14538 = ap_const_lv4_2) and (ap_ST_st10_fsm_9 = ap_CS_fsm)) or ((tmp_36_reg_14538 = ap_const_lv4_1) and (ap_ST_st10_fsm_9 = ap_CS_fsm)) or ((tmp_36_reg_14538 = ap_const_lv4_0) and (ap_ST_st10_fsm_9 = ap_CS_fsm)))) then
any_state_12_2_reg_2956 <= any_state_12_1_reg_1594;
end if;
end if;
end process;
-- any_state_12_3_reg_4116 assign process. --
any_state_12_3_reg_4116_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ST_st44_fsm_43 = ap_CS_fsm) and not((ap_const_lv1_0 = exitcond_fu_13718_p2)) and (ap_const_lv1_0 = all_end_phi_fu_12651_p36))) then
any_state_12_3_reg_4116 <= any_state_12_4_reg_5136;
elsif (((ap_ST_st8_fsm_7 = ap_CS_fsm) and not((exitcond2_fu_13247_p2 = ap_const_lv1_0)))) then
any_state_12_3_reg_4116 <= any_state_12_1_reg_1594;
end if;
end if;
end process;
-- any_state_12_4_reg_5136 assign process. --
any_state_12_4_reg_5136_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ST_st43_fsm_42 = ap_CS_fsm) or ((ap_ST_st32_fsm_31 = ap_CS_fsm) and ((not((ap_const_lv1_0 = end_load_3_phi_phi_fu_11584_p32)) and (ap_const_lv1_0 = brmerge_demorgan_reg_14680)) or (not((ap_const_lv1_0 = end_load_3_phi_phi_fu_11584_p32)) and not((ap_const_lv1_0 = tmp1_fu_13626_p2))))))) then
any_state_12_4_reg_5136 <= any_state_12_6_reg_9817;
elsif ((ap_ST_st18_fsm_17 = ap_CS_fsm)) then
any_state_12_4_reg_5136 <= any_state_12_3_reg_4116;
end if;
end if;
end process;
-- any_state_12_5_reg_7922 assign process. --
any_state_12_5_reg_7922_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and (ap_const_lv1_0 = end_0_phi_fu_5844_p32) and (tmp_37_fu_13557_p1 = ap_const_lv4_C))) then
any_state_12_5_reg_7922 <= ap_const_lv1_1;
elsif ((((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and (ap_const_lv1_0 = end_0_phi_fu_5844_p32)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and (ap_const_lv1_0 = end_0_phi_fu_5844_p32) and (tmp_37_fu_13557_p1 = ap_const_lv4_D)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and (ap_const_lv1_0 = end_0_phi_fu_5844_p32) and (tmp_37_fu_13557_p1 = ap_const_lv4_B)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and (ap_const_lv1_0 = end_0_phi_fu_5844_p32) and (tmp_37_fu_13557_p1 = ap_const_lv4_A)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and (ap_const_lv1_0 = end_0_phi_fu_5844_p32) and (tmp_37_fu_13557_p1 = ap_const_lv4_9)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and (ap_const_lv1_0 = end_0_phi_fu_5844_p32) and (tmp_37_fu_13557_p1 = ap_const_lv4_8)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and (ap_const_lv1_0 = end_0_phi_fu_5844_p32) and (tmp_37_fu_13557_p1 = ap_const_lv4_7)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and (ap_const_lv1_0 = end_0_phi_fu_5844_p32) and (tmp_37_fu_13557_p1 = ap_const_lv4_6)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and (ap_const_lv1_0 = end_0_phi_fu_5844_p32) and (tmp_37_fu_13557_p1 = ap_const_lv4_5)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and (ap_const_lv1_0 = end_0_phi_fu_5844_p32) and (tmp_37_fu_13557_p1 = ap_const_lv4_4)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and (ap_const_lv1_0 = end_0_phi_fu_5844_p32) and (tmp_37_fu_13557_p1 = ap_const_lv4_3)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and (ap_const_lv1_0 = end_0_phi_fu_5844_p32) and (tmp_37_fu_13557_p1 = ap_const_lv4_2)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and (ap_const_lv1_0 = end_0_phi_fu_5844_p32) and (tmp_37_fu_13557_p1 = ap_const_lv4_1)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and (ap_const_lv1_0 = end_0_phi_fu_5844_p32) and (tmp_37_fu_13557_p1 = ap_const_lv4_0)))) then
any_state_12_5_reg_7922 <= any_state_12_4_reg_5136;
end if;
end if;
end process;
-- any_state_12_6_reg_9817 assign process. --
any_state_12_6_reg_9817_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ST_st30_fsm_29 = ap_CS_fsm) and not((ap_const_lv1_0 = end_0_reg_5841)))) then
any_state_12_6_reg_9817 <= any_state_12_4_reg_5136;
elsif ((((ap_ST_st22_fsm_21 = ap_CS_fsm) and not((tmp_37_reg_14631 = ap_const_lv4_E)) and not((tmp_37_reg_14631 = ap_const_lv4_D)) and not((tmp_37_reg_14631 = ap_const_lv4_C)) and not((tmp_37_reg_14631 = ap_const_lv4_B)) and not((tmp_37_reg_14631 = ap_const_lv4_A)) and not((tmp_37_reg_14631 = ap_const_lv4_9)) and not((tmp_37_reg_14631 = ap_const_lv4_8)) and not((tmp_37_reg_14631 = ap_const_lv4_7)) and not((tmp_37_reg_14631 = ap_const_lv4_6)) and not((tmp_37_reg_14631 = ap_const_lv4_5)) and not((tmp_37_reg_14631 = ap_const_lv4_4)) and not((tmp_37_reg_14631 = ap_const_lv4_3)) and not((tmp_37_reg_14631 = ap_const_lv4_2)) and not((tmp_37_reg_14631 = ap_const_lv4_1)) and not((tmp_37_reg_14631 = ap_const_lv4_0))) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_E)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_D)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_C)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_B)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_A)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_9)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_8)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_7)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_6)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_5)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_4)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_3)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_2)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_1)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_0)))) then
any_state_12_6_reg_9817 <= any_state_12_5_reg_7922;
end if;
end if;
end process;
-- any_state_13_1_reg_1583 assign process. --
any_state_13_1_reg_1583_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_ST_st17_fsm_16 = ap_CS_fsm)) then
any_state_13_1_reg_1583 <= any_state_13_2_reg_2900;
elsif (((ap_ST_st7_fsm_6 = ap_CS_fsm) and (ap_const_lv1_0 = tmp_6_fu_13097_p2))) then
any_state_13_1_reg_1583 <= any_state_13_reg_1032;
end if;
end if;
end process;
-- any_state_13_2_reg_2900 assign process. --
any_state_13_2_reg_2900_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((tmp_36_reg_14538 = ap_const_lv4_D) and (ap_ST_st10_fsm_9 = ap_CS_fsm))) then
any_state_13_2_reg_2900 <= ap_const_lv1_0;
elsif (((ap_ST_st10_fsm_9 = ap_CS_fsm) or ((tmp_36_reg_14538 = ap_const_lv4_E) and (ap_ST_st10_fsm_9 = ap_CS_fsm)) or ((tmp_36_reg_14538 = ap_const_lv4_C) and (ap_ST_st10_fsm_9 = ap_CS_fsm)) or ((tmp_36_reg_14538 = ap_const_lv4_B) and (ap_ST_st10_fsm_9 = ap_CS_fsm)) or ((tmp_36_reg_14538 = ap_const_lv4_A) and (ap_ST_st10_fsm_9 = ap_CS_fsm)) or ((tmp_36_reg_14538 = ap_const_lv4_9) and (ap_ST_st10_fsm_9 = ap_CS_fsm)) or ((tmp_36_reg_14538 = ap_const_lv4_8) and (ap_ST_st10_fsm_9 = ap_CS_fsm)) or ((tmp_36_reg_14538 = ap_const_lv4_7) and (ap_ST_st10_fsm_9 = ap_CS_fsm)) or ((tmp_36_reg_14538 = ap_const_lv4_6) and (ap_ST_st10_fsm_9 = ap_CS_fsm)) or ((tmp_36_reg_14538 = ap_const_lv4_5) and (ap_ST_st10_fsm_9 = ap_CS_fsm)) or ((tmp_36_reg_14538 = ap_const_lv4_4) and (ap_ST_st10_fsm_9 = ap_CS_fsm)) or ((tmp_36_reg_14538 = ap_const_lv4_3) and (ap_ST_st10_fsm_9 = ap_CS_fsm)) or ((tmp_36_reg_14538 = ap_const_lv4_2) and (ap_ST_st10_fsm_9 = ap_CS_fsm)) or ((tmp_36_reg_14538 = ap_const_lv4_1) and (ap_ST_st10_fsm_9 = ap_CS_fsm)) or ((tmp_36_reg_14538 = ap_const_lv4_0) and (ap_ST_st10_fsm_9 = ap_CS_fsm)))) then
any_state_13_2_reg_2900 <= any_state_13_1_reg_1583;
end if;
end if;
end process;
-- any_state_13_3_reg_4105 assign process. --
any_state_13_3_reg_4105_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ST_st44_fsm_43 = ap_CS_fsm) and not((ap_const_lv1_0 = exitcond_fu_13718_p2)) and (ap_const_lv1_0 = all_end_phi_fu_12651_p36))) then
any_state_13_3_reg_4105 <= any_state_13_4_reg_5121;
elsif (((ap_ST_st8_fsm_7 = ap_CS_fsm) and not((exitcond2_fu_13247_p2 = ap_const_lv1_0)))) then
any_state_13_3_reg_4105 <= any_state_13_1_reg_1583;
end if;
end if;
end process;
-- any_state_13_4_reg_5121 assign process. --
any_state_13_4_reg_5121_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ST_st43_fsm_42 = ap_CS_fsm) or ((ap_ST_st32_fsm_31 = ap_CS_fsm) and ((not((ap_const_lv1_0 = end_load_3_phi_phi_fu_11584_p32)) and (ap_const_lv1_0 = brmerge_demorgan_reg_14680)) or (not((ap_const_lv1_0 = end_load_3_phi_phi_fu_11584_p32)) and not((ap_const_lv1_0 = tmp1_fu_13626_p2))))))) then
any_state_13_4_reg_5121 <= any_state_13_6_reg_9758;
elsif ((ap_ST_st18_fsm_17 = ap_CS_fsm)) then
any_state_13_4_reg_5121 <= any_state_13_3_reg_4105;
end if;
end if;
end process;
-- any_state_13_5_reg_7867 assign process. --
any_state_13_5_reg_7867_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and (ap_const_lv1_0 = end_0_phi_fu_5844_p32) and (tmp_37_fu_13557_p1 = ap_const_lv4_D))) then
any_state_13_5_reg_7867 <= ap_const_lv1_1;
elsif ((((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and (ap_const_lv1_0 = end_0_phi_fu_5844_p32)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and (ap_const_lv1_0 = end_0_phi_fu_5844_p32) and (tmp_37_fu_13557_p1 = ap_const_lv4_C)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and (ap_const_lv1_0 = end_0_phi_fu_5844_p32) and (tmp_37_fu_13557_p1 = ap_const_lv4_B)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and (ap_const_lv1_0 = end_0_phi_fu_5844_p32) and (tmp_37_fu_13557_p1 = ap_const_lv4_A)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and (ap_const_lv1_0 = end_0_phi_fu_5844_p32) and (tmp_37_fu_13557_p1 = ap_const_lv4_9)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and (ap_const_lv1_0 = end_0_phi_fu_5844_p32) and (tmp_37_fu_13557_p1 = ap_const_lv4_8)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and (ap_const_lv1_0 = end_0_phi_fu_5844_p32) and (tmp_37_fu_13557_p1 = ap_const_lv4_7)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and (ap_const_lv1_0 = end_0_phi_fu_5844_p32) and (tmp_37_fu_13557_p1 = ap_const_lv4_6)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and (ap_const_lv1_0 = end_0_phi_fu_5844_p32) and (tmp_37_fu_13557_p1 = ap_const_lv4_5)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and (ap_const_lv1_0 = end_0_phi_fu_5844_p32) and (tmp_37_fu_13557_p1 = ap_const_lv4_4)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and (ap_const_lv1_0 = end_0_phi_fu_5844_p32) and (tmp_37_fu_13557_p1 = ap_const_lv4_3)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and (ap_const_lv1_0 = end_0_phi_fu_5844_p32) and (tmp_37_fu_13557_p1 = ap_const_lv4_2)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and (ap_const_lv1_0 = end_0_phi_fu_5844_p32) and (tmp_37_fu_13557_p1 = ap_const_lv4_1)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and (ap_const_lv1_0 = end_0_phi_fu_5844_p32) and (tmp_37_fu_13557_p1 = ap_const_lv4_0)))) then
any_state_13_5_reg_7867 <= any_state_13_4_reg_5121;
end if;
end if;
end process;
-- any_state_13_6_reg_9758 assign process. --
any_state_13_6_reg_9758_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ST_st30_fsm_29 = ap_CS_fsm) and not((ap_const_lv1_0 = end_0_reg_5841)))) then
any_state_13_6_reg_9758 <= any_state_13_4_reg_5121;
elsif ((((ap_ST_st22_fsm_21 = ap_CS_fsm) and not((tmp_37_reg_14631 = ap_const_lv4_E)) and not((tmp_37_reg_14631 = ap_const_lv4_D)) and not((tmp_37_reg_14631 = ap_const_lv4_C)) and not((tmp_37_reg_14631 = ap_const_lv4_B)) and not((tmp_37_reg_14631 = ap_const_lv4_A)) and not((tmp_37_reg_14631 = ap_const_lv4_9)) and not((tmp_37_reg_14631 = ap_const_lv4_8)) and not((tmp_37_reg_14631 = ap_const_lv4_7)) and not((tmp_37_reg_14631 = ap_const_lv4_6)) and not((tmp_37_reg_14631 = ap_const_lv4_5)) and not((tmp_37_reg_14631 = ap_const_lv4_4)) and not((tmp_37_reg_14631 = ap_const_lv4_3)) and not((tmp_37_reg_14631 = ap_const_lv4_2)) and not((tmp_37_reg_14631 = ap_const_lv4_1)) and not((tmp_37_reg_14631 = ap_const_lv4_0))) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_E)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_D)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_C)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_B)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_A)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_9)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_8)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_7)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_6)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_5)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_4)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_3)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_2)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_1)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_0)))) then
any_state_13_6_reg_9758 <= any_state_13_5_reg_7867;
end if;
end if;
end process;
-- any_state_14_1_reg_1572 assign process. --
any_state_14_1_reg_1572_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_ST_st17_fsm_16 = ap_CS_fsm)) then
any_state_14_1_reg_1572 <= any_state_14_2_reg_2844;
elsif (((ap_ST_st7_fsm_6 = ap_CS_fsm) and (ap_const_lv1_0 = tmp_6_fu_13097_p2))) then
any_state_14_1_reg_1572 <= any_state_14_reg_1020;
end if;
end if;
end process;
-- any_state_14_2_reg_2844 assign process. --
any_state_14_2_reg_2844_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((tmp_36_reg_14538 = ap_const_lv4_E) and (ap_ST_st10_fsm_9 = ap_CS_fsm))) then
any_state_14_2_reg_2844 <= ap_const_lv1_0;
elsif (((ap_ST_st10_fsm_9 = ap_CS_fsm) or ((tmp_36_reg_14538 = ap_const_lv4_D) and (ap_ST_st10_fsm_9 = ap_CS_fsm)) or ((tmp_36_reg_14538 = ap_const_lv4_C) and (ap_ST_st10_fsm_9 = ap_CS_fsm)) or ((tmp_36_reg_14538 = ap_const_lv4_B) and (ap_ST_st10_fsm_9 = ap_CS_fsm)) or ((tmp_36_reg_14538 = ap_const_lv4_A) and (ap_ST_st10_fsm_9 = ap_CS_fsm)) or ((tmp_36_reg_14538 = ap_const_lv4_9) and (ap_ST_st10_fsm_9 = ap_CS_fsm)) or ((tmp_36_reg_14538 = ap_const_lv4_8) and (ap_ST_st10_fsm_9 = ap_CS_fsm)) or ((tmp_36_reg_14538 = ap_const_lv4_7) and (ap_ST_st10_fsm_9 = ap_CS_fsm)) or ((tmp_36_reg_14538 = ap_const_lv4_6) and (ap_ST_st10_fsm_9 = ap_CS_fsm)) or ((tmp_36_reg_14538 = ap_const_lv4_5) and (ap_ST_st10_fsm_9 = ap_CS_fsm)) or ((tmp_36_reg_14538 = ap_const_lv4_4) and (ap_ST_st10_fsm_9 = ap_CS_fsm)) or ((tmp_36_reg_14538 = ap_const_lv4_3) and (ap_ST_st10_fsm_9 = ap_CS_fsm)) or ((tmp_36_reg_14538 = ap_const_lv4_2) and (ap_ST_st10_fsm_9 = ap_CS_fsm)) or ((tmp_36_reg_14538 = ap_const_lv4_1) and (ap_ST_st10_fsm_9 = ap_CS_fsm)) or ((tmp_36_reg_14538 = ap_const_lv4_0) and (ap_ST_st10_fsm_9 = ap_CS_fsm)))) then
any_state_14_2_reg_2844 <= any_state_14_1_reg_1572;
end if;
end if;
end process;
-- any_state_14_3_reg_4094 assign process. --
any_state_14_3_reg_4094_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ST_st44_fsm_43 = ap_CS_fsm) and not((ap_const_lv1_0 = exitcond_fu_13718_p2)) and (ap_const_lv1_0 = all_end_phi_fu_12651_p36))) then
any_state_14_3_reg_4094 <= any_state_14_4_reg_5106;
elsif (((ap_ST_st8_fsm_7 = ap_CS_fsm) and not((exitcond2_fu_13247_p2 = ap_const_lv1_0)))) then
any_state_14_3_reg_4094 <= any_state_14_1_reg_1572;
end if;
end if;
end process;
-- any_state_14_4_reg_5106 assign process. --
any_state_14_4_reg_5106_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ST_st43_fsm_42 = ap_CS_fsm) or ((ap_ST_st32_fsm_31 = ap_CS_fsm) and ((not((ap_const_lv1_0 = end_load_3_phi_phi_fu_11584_p32)) and (ap_const_lv1_0 = brmerge_demorgan_reg_14680)) or (not((ap_const_lv1_0 = end_load_3_phi_phi_fu_11584_p32)) and not((ap_const_lv1_0 = tmp1_fu_13626_p2))))))) then
any_state_14_4_reg_5106 <= any_state_14_6_reg_9699;
elsif ((ap_ST_st18_fsm_17 = ap_CS_fsm)) then
any_state_14_4_reg_5106 <= any_state_14_3_reg_4094;
end if;
end if;
end process;
-- any_state_14_5_reg_7812 assign process. --
any_state_14_5_reg_7812_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and (ap_const_lv1_0 = end_0_phi_fu_5844_p32) and (tmp_37_fu_13557_p1 = ap_const_lv4_E))) then
any_state_14_5_reg_7812 <= ap_const_lv1_1;
elsif ((((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and (ap_const_lv1_0 = end_0_phi_fu_5844_p32)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and (ap_const_lv1_0 = end_0_phi_fu_5844_p32) and (tmp_37_fu_13557_p1 = ap_const_lv4_C)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and (ap_const_lv1_0 = end_0_phi_fu_5844_p32) and (tmp_37_fu_13557_p1 = ap_const_lv4_B)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and (ap_const_lv1_0 = end_0_phi_fu_5844_p32) and (tmp_37_fu_13557_p1 = ap_const_lv4_A)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and (ap_const_lv1_0 = end_0_phi_fu_5844_p32) and (tmp_37_fu_13557_p1 = ap_const_lv4_9)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and (ap_const_lv1_0 = end_0_phi_fu_5844_p32) and (tmp_37_fu_13557_p1 = ap_const_lv4_8)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and (ap_const_lv1_0 = end_0_phi_fu_5844_p32) and (tmp_37_fu_13557_p1 = ap_const_lv4_7)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and (ap_const_lv1_0 = end_0_phi_fu_5844_p32) and (tmp_37_fu_13557_p1 = ap_const_lv4_6)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and (ap_const_lv1_0 = end_0_phi_fu_5844_p32) and (tmp_37_fu_13557_p1 = ap_const_lv4_5)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and (ap_const_lv1_0 = end_0_phi_fu_5844_p32) and (tmp_37_fu_13557_p1 = ap_const_lv4_4)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and (ap_const_lv1_0 = end_0_phi_fu_5844_p32) and (tmp_37_fu_13557_p1 = ap_const_lv4_3)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and (ap_const_lv1_0 = end_0_phi_fu_5844_p32) and (tmp_37_fu_13557_p1 = ap_const_lv4_2)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and (ap_const_lv1_0 = end_0_phi_fu_5844_p32) and (tmp_37_fu_13557_p1 = ap_const_lv4_1)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and (ap_const_lv1_0 = end_0_phi_fu_5844_p32) and (tmp_37_fu_13557_p1 = ap_const_lv4_0)))) then
any_state_14_5_reg_7812 <= any_state_14_4_reg_5106;
end if;
end if;
end process;
-- any_state_14_6_reg_9699 assign process. --
any_state_14_6_reg_9699_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ST_st30_fsm_29 = ap_CS_fsm) and not((ap_const_lv1_0 = end_0_reg_5841)))) then
any_state_14_6_reg_9699 <= any_state_14_4_reg_5106;
elsif ((((ap_ST_st22_fsm_21 = ap_CS_fsm) and not((tmp_37_reg_14631 = ap_const_lv4_E)) and not((tmp_37_reg_14631 = ap_const_lv4_D)) and not((tmp_37_reg_14631 = ap_const_lv4_C)) and not((tmp_37_reg_14631 = ap_const_lv4_B)) and not((tmp_37_reg_14631 = ap_const_lv4_A)) and not((tmp_37_reg_14631 = ap_const_lv4_9)) and not((tmp_37_reg_14631 = ap_const_lv4_8)) and not((tmp_37_reg_14631 = ap_const_lv4_7)) and not((tmp_37_reg_14631 = ap_const_lv4_6)) and not((tmp_37_reg_14631 = ap_const_lv4_5)) and not((tmp_37_reg_14631 = ap_const_lv4_4)) and not((tmp_37_reg_14631 = ap_const_lv4_3)) and not((tmp_37_reg_14631 = ap_const_lv4_2)) and not((tmp_37_reg_14631 = ap_const_lv4_1)) and not((tmp_37_reg_14631 = ap_const_lv4_0))) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_E)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_D)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_C)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_B)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_A)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_9)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_8)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_7)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_6)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_5)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_4)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_3)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_2)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_1)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_0)))) then
any_state_14_6_reg_9699 <= any_state_14_5_reg_7812;
end if;
end if;
end process;
-- any_state_15_1_reg_1561 assign process. --
any_state_15_1_reg_1561_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_ST_st17_fsm_16 = ap_CS_fsm)) then
any_state_15_1_reg_1561 <= any_state_15_2_reg_2788;
elsif (((ap_ST_st7_fsm_6 = ap_CS_fsm) and (ap_const_lv1_0 = tmp_6_fu_13097_p2))) then
any_state_15_1_reg_1561 <= any_state_s_reg_1008;
end if;
end if;
end process;
-- any_state_15_2_reg_2788 assign process. --
any_state_15_2_reg_2788_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((((tmp_36_reg_14538 = ap_const_lv4_E) and (ap_ST_st10_fsm_9 = ap_CS_fsm)) or ((tmp_36_reg_14538 = ap_const_lv4_D) and (ap_ST_st10_fsm_9 = ap_CS_fsm)) or ((tmp_36_reg_14538 = ap_const_lv4_C) and (ap_ST_st10_fsm_9 = ap_CS_fsm)) or ((tmp_36_reg_14538 = ap_const_lv4_B) and (ap_ST_st10_fsm_9 = ap_CS_fsm)) or ((tmp_36_reg_14538 = ap_const_lv4_A) and (ap_ST_st10_fsm_9 = ap_CS_fsm)) or ((tmp_36_reg_14538 = ap_const_lv4_9) and (ap_ST_st10_fsm_9 = ap_CS_fsm)) or ((tmp_36_reg_14538 = ap_const_lv4_8) and (ap_ST_st10_fsm_9 = ap_CS_fsm)) or ((tmp_36_reg_14538 = ap_const_lv4_7) and (ap_ST_st10_fsm_9 = ap_CS_fsm)) or ((tmp_36_reg_14538 = ap_const_lv4_6) and (ap_ST_st10_fsm_9 = ap_CS_fsm)) or ((tmp_36_reg_14538 = ap_const_lv4_5) and (ap_ST_st10_fsm_9 = ap_CS_fsm)) or ((tmp_36_reg_14538 = ap_const_lv4_4) and (ap_ST_st10_fsm_9 = ap_CS_fsm)) or ((tmp_36_reg_14538 = ap_const_lv4_3) and (ap_ST_st10_fsm_9 = ap_CS_fsm)) or ((tmp_36_reg_14538 = ap_const_lv4_2) and (ap_ST_st10_fsm_9 = ap_CS_fsm)) or ((tmp_36_reg_14538 = ap_const_lv4_1) and (ap_ST_st10_fsm_9 = ap_CS_fsm)) or ((tmp_36_reg_14538 = ap_const_lv4_0) and (ap_ST_st10_fsm_9 = ap_CS_fsm)))) then
any_state_15_2_reg_2788 <= any_state_15_1_reg_1561;
elsif ((ap_ST_st10_fsm_9 = ap_CS_fsm)) then
any_state_15_2_reg_2788 <= ap_const_lv1_0;
end if;
end if;
end process;
-- any_state_15_3_reg_4083 assign process. --
any_state_15_3_reg_4083_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ST_st44_fsm_43 = ap_CS_fsm) and not((ap_const_lv1_0 = exitcond_fu_13718_p2)) and (ap_const_lv1_0 = all_end_phi_fu_12651_p36))) then
any_state_15_3_reg_4083 <= any_state_15_4_reg_5091;
elsif (((ap_ST_st8_fsm_7 = ap_CS_fsm) and not((exitcond2_fu_13247_p2 = ap_const_lv1_0)))) then
any_state_15_3_reg_4083 <= any_state_15_1_reg_1561;
end if;
end if;
end process;
-- any_state_15_4_reg_5091 assign process. --
any_state_15_4_reg_5091_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ST_st43_fsm_42 = ap_CS_fsm) or ((ap_ST_st32_fsm_31 = ap_CS_fsm) and ((not((ap_const_lv1_0 = end_load_3_phi_phi_fu_11584_p32)) and (ap_const_lv1_0 = brmerge_demorgan_reg_14680)) or (not((ap_const_lv1_0 = end_load_3_phi_phi_fu_11584_p32)) and not((ap_const_lv1_0 = tmp1_fu_13626_p2))))))) then
any_state_15_4_reg_5091 <= any_state_15_6_reg_9640;
elsif ((ap_ST_st18_fsm_17 = ap_CS_fsm)) then
any_state_15_4_reg_5091 <= any_state_15_3_reg_4083;
end if;
end if;
end process;
-- any_state_15_5_reg_7757 assign process. --
any_state_15_5_reg_7757_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and (ap_const_lv1_0 = end_0_phi_fu_5844_p32) and (tmp_37_fu_13557_p1 = ap_const_lv4_E)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and (ap_const_lv1_0 = end_0_phi_fu_5844_p32) and (tmp_37_fu_13557_p1 = ap_const_lv4_D)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and (ap_const_lv1_0 = end_0_phi_fu_5844_p32) and (tmp_37_fu_13557_p1 = ap_const_lv4_C)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and (ap_const_lv1_0 = end_0_phi_fu_5844_p32) and (tmp_37_fu_13557_p1 = ap_const_lv4_B)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and (ap_const_lv1_0 = end_0_phi_fu_5844_p32) and (tmp_37_fu_13557_p1 = ap_const_lv4_A)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and (ap_const_lv1_0 = end_0_phi_fu_5844_p32) and (tmp_37_fu_13557_p1 = ap_const_lv4_9)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and (ap_const_lv1_0 = end_0_phi_fu_5844_p32) and (tmp_37_fu_13557_p1 = ap_const_lv4_8)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and (ap_const_lv1_0 = end_0_phi_fu_5844_p32) and (tmp_37_fu_13557_p1 = ap_const_lv4_7)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and (ap_const_lv1_0 = end_0_phi_fu_5844_p32) and (tmp_37_fu_13557_p1 = ap_const_lv4_6)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and (ap_const_lv1_0 = end_0_phi_fu_5844_p32) and (tmp_37_fu_13557_p1 = ap_const_lv4_5)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and (ap_const_lv1_0 = end_0_phi_fu_5844_p32) and (tmp_37_fu_13557_p1 = ap_const_lv4_4)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and (ap_const_lv1_0 = end_0_phi_fu_5844_p32) and (tmp_37_fu_13557_p1 = ap_const_lv4_3)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and (ap_const_lv1_0 = end_0_phi_fu_5844_p32) and (tmp_37_fu_13557_p1 = ap_const_lv4_2)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and (ap_const_lv1_0 = end_0_phi_fu_5844_p32) and (tmp_37_fu_13557_p1 = ap_const_lv4_1)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and (ap_const_lv1_0 = end_0_phi_fu_5844_p32) and (tmp_37_fu_13557_p1 = ap_const_lv4_0)))) then
any_state_15_5_reg_7757 <= any_state_15_4_reg_5091;
elsif (((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and (ap_const_lv1_0 = end_0_phi_fu_5844_p32))) then
any_state_15_5_reg_7757 <= ap_const_lv1_1;
end if;
end if;
end process;
-- any_state_15_6_reg_9640 assign process. --
any_state_15_6_reg_9640_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ST_st30_fsm_29 = ap_CS_fsm) and not((ap_const_lv1_0 = end_0_reg_5841)))) then
any_state_15_6_reg_9640 <= any_state_15_4_reg_5091;
elsif ((((ap_ST_st22_fsm_21 = ap_CS_fsm) and not((tmp_37_reg_14631 = ap_const_lv4_E)) and not((tmp_37_reg_14631 = ap_const_lv4_D)) and not((tmp_37_reg_14631 = ap_const_lv4_C)) and not((tmp_37_reg_14631 = ap_const_lv4_B)) and not((tmp_37_reg_14631 = ap_const_lv4_A)) and not((tmp_37_reg_14631 = ap_const_lv4_9)) and not((tmp_37_reg_14631 = ap_const_lv4_8)) and not((tmp_37_reg_14631 = ap_const_lv4_7)) and not((tmp_37_reg_14631 = ap_const_lv4_6)) and not((tmp_37_reg_14631 = ap_const_lv4_5)) and not((tmp_37_reg_14631 = ap_const_lv4_4)) and not((tmp_37_reg_14631 = ap_const_lv4_3)) and not((tmp_37_reg_14631 = ap_const_lv4_2)) and not((tmp_37_reg_14631 = ap_const_lv4_1)) and not((tmp_37_reg_14631 = ap_const_lv4_0))) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_E)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_D)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_C)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_B)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_A)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_9)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_8)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_7)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_6)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_5)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_4)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_3)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_2)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_1)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_0)))) then
any_state_15_6_reg_9640 <= any_state_15_5_reg_7757;
end if;
end if;
end process;
-- any_state_1_1_reg_1715 assign process. --
any_state_1_1_reg_1715_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_ST_st17_fsm_16 = ap_CS_fsm)) then
any_state_1_1_reg_1715 <= any_state_1_2_reg_3572;
elsif (((ap_ST_st7_fsm_6 = ap_CS_fsm) and (ap_const_lv1_0 = tmp_6_fu_13097_p2))) then
any_state_1_1_reg_1715 <= any_state_1_reg_1176;
end if;
end if;
end process;
-- any_state_1_2_reg_3572 assign process. --
any_state_1_2_reg_3572_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((tmp_36_reg_14538 = ap_const_lv4_1) and (ap_ST_st10_fsm_9 = ap_CS_fsm))) then
any_state_1_2_reg_3572 <= ap_const_lv1_0;
elsif (((ap_ST_st10_fsm_9 = ap_CS_fsm) or ((tmp_36_reg_14538 = ap_const_lv4_E) and (ap_ST_st10_fsm_9 = ap_CS_fsm)) or ((tmp_36_reg_14538 = ap_const_lv4_D) and (ap_ST_st10_fsm_9 = ap_CS_fsm)) or ((tmp_36_reg_14538 = ap_const_lv4_C) and (ap_ST_st10_fsm_9 = ap_CS_fsm)) or ((tmp_36_reg_14538 = ap_const_lv4_B) and (ap_ST_st10_fsm_9 = ap_CS_fsm)) or ((tmp_36_reg_14538 = ap_const_lv4_A) and (ap_ST_st10_fsm_9 = ap_CS_fsm)) or ((tmp_36_reg_14538 = ap_const_lv4_9) and (ap_ST_st10_fsm_9 = ap_CS_fsm)) or ((tmp_36_reg_14538 = ap_const_lv4_8) and (ap_ST_st10_fsm_9 = ap_CS_fsm)) or ((tmp_36_reg_14538 = ap_const_lv4_7) and (ap_ST_st10_fsm_9 = ap_CS_fsm)) or ((tmp_36_reg_14538 = ap_const_lv4_6) and (ap_ST_st10_fsm_9 = ap_CS_fsm)) or ((tmp_36_reg_14538 = ap_const_lv4_5) and (ap_ST_st10_fsm_9 = ap_CS_fsm)) or ((tmp_36_reg_14538 = ap_const_lv4_4) and (ap_ST_st10_fsm_9 = ap_CS_fsm)) or ((tmp_36_reg_14538 = ap_const_lv4_3) and (ap_ST_st10_fsm_9 = ap_CS_fsm)) or ((tmp_36_reg_14538 = ap_const_lv4_2) and (ap_ST_st10_fsm_9 = ap_CS_fsm)) or ((tmp_36_reg_14538 = ap_const_lv4_0) and (ap_ST_st10_fsm_9 = ap_CS_fsm)))) then
any_state_1_2_reg_3572 <= any_state_1_1_reg_1715;
end if;
end if;
end process;
-- any_state_1_3_reg_4237 assign process. --
any_state_1_3_reg_4237_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ST_st44_fsm_43 = ap_CS_fsm) and not((ap_const_lv1_0 = exitcond_fu_13718_p2)) and (ap_const_lv1_0 = all_end_phi_fu_12651_p36))) then
any_state_1_3_reg_4237 <= any_state_1_4_reg_5301;
elsif (((ap_ST_st8_fsm_7 = ap_CS_fsm) and not((exitcond2_fu_13247_p2 = ap_const_lv1_0)))) then
any_state_1_3_reg_4237 <= any_state_1_1_reg_1715;
end if;
end if;
end process;
-- any_state_1_4_reg_5301 assign process. --
any_state_1_4_reg_5301_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ST_st43_fsm_42 = ap_CS_fsm) or ((ap_ST_st32_fsm_31 = ap_CS_fsm) and ((not((ap_const_lv1_0 = end_load_3_phi_phi_fu_11584_p32)) and (ap_const_lv1_0 = brmerge_demorgan_reg_14680)) or (not((ap_const_lv1_0 = end_load_3_phi_phi_fu_11584_p32)) and not((ap_const_lv1_0 = tmp1_fu_13626_p2))))))) then
any_state_1_4_reg_5301 <= any_state_1_6_reg_10466;
elsif ((ap_ST_st18_fsm_17 = ap_CS_fsm)) then
any_state_1_4_reg_5301 <= any_state_1_3_reg_4237;
end if;
end if;
end process;
-- any_state_1_5_reg_8527 assign process. --
any_state_1_5_reg_8527_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and (ap_const_lv1_0 = end_0_phi_fu_5844_p32) and (tmp_37_fu_13557_p1 = ap_const_lv4_1))) then
any_state_1_5_reg_8527 <= ap_const_lv1_1;
elsif ((((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and (ap_const_lv1_0 = end_0_phi_fu_5844_p32)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and (ap_const_lv1_0 = end_0_phi_fu_5844_p32) and (tmp_37_fu_13557_p1 = ap_const_lv4_D)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and (ap_const_lv1_0 = end_0_phi_fu_5844_p32) and (tmp_37_fu_13557_p1 = ap_const_lv4_C)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and (ap_const_lv1_0 = end_0_phi_fu_5844_p32) and (tmp_37_fu_13557_p1 = ap_const_lv4_B)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and (ap_const_lv1_0 = end_0_phi_fu_5844_p32) and (tmp_37_fu_13557_p1 = ap_const_lv4_A)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and (ap_const_lv1_0 = end_0_phi_fu_5844_p32) and (tmp_37_fu_13557_p1 = ap_const_lv4_9)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and (ap_const_lv1_0 = end_0_phi_fu_5844_p32) and (tmp_37_fu_13557_p1 = ap_const_lv4_8)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and (ap_const_lv1_0 = end_0_phi_fu_5844_p32) and (tmp_37_fu_13557_p1 = ap_const_lv4_7)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and (ap_const_lv1_0 = end_0_phi_fu_5844_p32) and (tmp_37_fu_13557_p1 = ap_const_lv4_6)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and (ap_const_lv1_0 = end_0_phi_fu_5844_p32) and (tmp_37_fu_13557_p1 = ap_const_lv4_5)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and (ap_const_lv1_0 = end_0_phi_fu_5844_p32) and (tmp_37_fu_13557_p1 = ap_const_lv4_4)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and (ap_const_lv1_0 = end_0_phi_fu_5844_p32) and (tmp_37_fu_13557_p1 = ap_const_lv4_3)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and (ap_const_lv1_0 = end_0_phi_fu_5844_p32) and (tmp_37_fu_13557_p1 = ap_const_lv4_2)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and (ap_const_lv1_0 = end_0_phi_fu_5844_p32) and (tmp_37_fu_13557_p1 = ap_const_lv4_0)))) then
any_state_1_5_reg_8527 <= any_state_1_4_reg_5301;
end if;
end if;
end process;
-- any_state_1_6_reg_10466 assign process. --
any_state_1_6_reg_10466_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ST_st30_fsm_29 = ap_CS_fsm) and not((ap_const_lv1_0 = end_0_reg_5841)))) then
any_state_1_6_reg_10466 <= any_state_1_4_reg_5301;
elsif ((((ap_ST_st22_fsm_21 = ap_CS_fsm) and not((tmp_37_reg_14631 = ap_const_lv4_E)) and not((tmp_37_reg_14631 = ap_const_lv4_D)) and not((tmp_37_reg_14631 = ap_const_lv4_C)) and not((tmp_37_reg_14631 = ap_const_lv4_B)) and not((tmp_37_reg_14631 = ap_const_lv4_A)) and not((tmp_37_reg_14631 = ap_const_lv4_9)) and not((tmp_37_reg_14631 = ap_const_lv4_8)) and not((tmp_37_reg_14631 = ap_const_lv4_7)) and not((tmp_37_reg_14631 = ap_const_lv4_6)) and not((tmp_37_reg_14631 = ap_const_lv4_5)) and not((tmp_37_reg_14631 = ap_const_lv4_4)) and not((tmp_37_reg_14631 = ap_const_lv4_3)) and not((tmp_37_reg_14631 = ap_const_lv4_2)) and not((tmp_37_reg_14631 = ap_const_lv4_1)) and not((tmp_37_reg_14631 = ap_const_lv4_0))) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_E)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_D)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_C)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_B)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_A)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_9)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_8)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_7)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_6)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_5)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_4)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_3)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_2)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_1)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_0)))) then
any_state_1_6_reg_10466 <= any_state_1_5_reg_8527;
end if;
end if;
end process;
-- any_state_2_1_reg_1704 assign process. --
any_state_2_1_reg_1704_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_ST_st17_fsm_16 = ap_CS_fsm)) then
any_state_2_1_reg_1704 <= any_state_2_2_reg_3516;
elsif (((ap_ST_st7_fsm_6 = ap_CS_fsm) and (ap_const_lv1_0 = tmp_6_fu_13097_p2))) then
any_state_2_1_reg_1704 <= any_state_2_reg_1164;
end if;
end if;
end process;
-- any_state_2_2_reg_3516 assign process. --
any_state_2_2_reg_3516_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((tmp_36_reg_14538 = ap_const_lv4_2) and (ap_ST_st10_fsm_9 = ap_CS_fsm))) then
any_state_2_2_reg_3516 <= ap_const_lv1_0;
elsif (((ap_ST_st10_fsm_9 = ap_CS_fsm) or ((tmp_36_reg_14538 = ap_const_lv4_E) and (ap_ST_st10_fsm_9 = ap_CS_fsm)) or ((tmp_36_reg_14538 = ap_const_lv4_D) and (ap_ST_st10_fsm_9 = ap_CS_fsm)) or ((tmp_36_reg_14538 = ap_const_lv4_C) and (ap_ST_st10_fsm_9 = ap_CS_fsm)) or ((tmp_36_reg_14538 = ap_const_lv4_B) and (ap_ST_st10_fsm_9 = ap_CS_fsm)) or ((tmp_36_reg_14538 = ap_const_lv4_A) and (ap_ST_st10_fsm_9 = ap_CS_fsm)) or ((tmp_36_reg_14538 = ap_const_lv4_9) and (ap_ST_st10_fsm_9 = ap_CS_fsm)) or ((tmp_36_reg_14538 = ap_const_lv4_8) and (ap_ST_st10_fsm_9 = ap_CS_fsm)) or ((tmp_36_reg_14538 = ap_const_lv4_7) and (ap_ST_st10_fsm_9 = ap_CS_fsm)) or ((tmp_36_reg_14538 = ap_const_lv4_6) and (ap_ST_st10_fsm_9 = ap_CS_fsm)) or ((tmp_36_reg_14538 = ap_const_lv4_5) and (ap_ST_st10_fsm_9 = ap_CS_fsm)) or ((tmp_36_reg_14538 = ap_const_lv4_4) and (ap_ST_st10_fsm_9 = ap_CS_fsm)) or ((tmp_36_reg_14538 = ap_const_lv4_3) and (ap_ST_st10_fsm_9 = ap_CS_fsm)) or ((tmp_36_reg_14538 = ap_const_lv4_1) and (ap_ST_st10_fsm_9 = ap_CS_fsm)) or ((tmp_36_reg_14538 = ap_const_lv4_0) and (ap_ST_st10_fsm_9 = ap_CS_fsm)))) then
any_state_2_2_reg_3516 <= any_state_2_1_reg_1704;
end if;
end if;
end process;
-- any_state_2_3_reg_4226 assign process. --
any_state_2_3_reg_4226_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ST_st44_fsm_43 = ap_CS_fsm) and not((ap_const_lv1_0 = exitcond_fu_13718_p2)) and (ap_const_lv1_0 = all_end_phi_fu_12651_p36))) then
any_state_2_3_reg_4226 <= any_state_2_4_reg_5286;
elsif (((ap_ST_st8_fsm_7 = ap_CS_fsm) and not((exitcond2_fu_13247_p2 = ap_const_lv1_0)))) then
any_state_2_3_reg_4226 <= any_state_2_1_reg_1704;
end if;
end if;
end process;
-- any_state_2_4_reg_5286 assign process. --
any_state_2_4_reg_5286_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ST_st43_fsm_42 = ap_CS_fsm) or ((ap_ST_st32_fsm_31 = ap_CS_fsm) and ((not((ap_const_lv1_0 = end_load_3_phi_phi_fu_11584_p32)) and (ap_const_lv1_0 = brmerge_demorgan_reg_14680)) or (not((ap_const_lv1_0 = end_load_3_phi_phi_fu_11584_p32)) and not((ap_const_lv1_0 = tmp1_fu_13626_p2))))))) then
any_state_2_4_reg_5286 <= any_state_2_6_reg_10407;
elsif ((ap_ST_st18_fsm_17 = ap_CS_fsm)) then
any_state_2_4_reg_5286 <= any_state_2_3_reg_4226;
end if;
end if;
end process;
-- any_state_2_5_reg_8472 assign process. --
any_state_2_5_reg_8472_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and (ap_const_lv1_0 = end_0_phi_fu_5844_p32) and (tmp_37_fu_13557_p1 = ap_const_lv4_2))) then
any_state_2_5_reg_8472 <= ap_const_lv1_1;
elsif ((((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and (ap_const_lv1_0 = end_0_phi_fu_5844_p32)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and (ap_const_lv1_0 = end_0_phi_fu_5844_p32) and (tmp_37_fu_13557_p1 = ap_const_lv4_D)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and (ap_const_lv1_0 = end_0_phi_fu_5844_p32) and (tmp_37_fu_13557_p1 = ap_const_lv4_C)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and (ap_const_lv1_0 = end_0_phi_fu_5844_p32) and (tmp_37_fu_13557_p1 = ap_const_lv4_B)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and (ap_const_lv1_0 = end_0_phi_fu_5844_p32) and (tmp_37_fu_13557_p1 = ap_const_lv4_A)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and (ap_const_lv1_0 = end_0_phi_fu_5844_p32) and (tmp_37_fu_13557_p1 = ap_const_lv4_9)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and (ap_const_lv1_0 = end_0_phi_fu_5844_p32) and (tmp_37_fu_13557_p1 = ap_const_lv4_8)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and (ap_const_lv1_0 = end_0_phi_fu_5844_p32) and (tmp_37_fu_13557_p1 = ap_const_lv4_7)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and (ap_const_lv1_0 = end_0_phi_fu_5844_p32) and (tmp_37_fu_13557_p1 = ap_const_lv4_6)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and (ap_const_lv1_0 = end_0_phi_fu_5844_p32) and (tmp_37_fu_13557_p1 = ap_const_lv4_5)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and (ap_const_lv1_0 = end_0_phi_fu_5844_p32) and (tmp_37_fu_13557_p1 = ap_const_lv4_4)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and (ap_const_lv1_0 = end_0_phi_fu_5844_p32) and (tmp_37_fu_13557_p1 = ap_const_lv4_3)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and (ap_const_lv1_0 = end_0_phi_fu_5844_p32) and (tmp_37_fu_13557_p1 = ap_const_lv4_1)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and (ap_const_lv1_0 = end_0_phi_fu_5844_p32) and (tmp_37_fu_13557_p1 = ap_const_lv4_0)))) then
any_state_2_5_reg_8472 <= any_state_2_4_reg_5286;
end if;
end if;
end process;
-- any_state_2_6_reg_10407 assign process. --
any_state_2_6_reg_10407_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ST_st30_fsm_29 = ap_CS_fsm) and not((ap_const_lv1_0 = end_0_reg_5841)))) then
any_state_2_6_reg_10407 <= any_state_2_4_reg_5286;
elsif ((((ap_ST_st22_fsm_21 = ap_CS_fsm) and not((tmp_37_reg_14631 = ap_const_lv4_E)) and not((tmp_37_reg_14631 = ap_const_lv4_D)) and not((tmp_37_reg_14631 = ap_const_lv4_C)) and not((tmp_37_reg_14631 = ap_const_lv4_B)) and not((tmp_37_reg_14631 = ap_const_lv4_A)) and not((tmp_37_reg_14631 = ap_const_lv4_9)) and not((tmp_37_reg_14631 = ap_const_lv4_8)) and not((tmp_37_reg_14631 = ap_const_lv4_7)) and not((tmp_37_reg_14631 = ap_const_lv4_6)) and not((tmp_37_reg_14631 = ap_const_lv4_5)) and not((tmp_37_reg_14631 = ap_const_lv4_4)) and not((tmp_37_reg_14631 = ap_const_lv4_3)) and not((tmp_37_reg_14631 = ap_const_lv4_2)) and not((tmp_37_reg_14631 = ap_const_lv4_1)) and not((tmp_37_reg_14631 = ap_const_lv4_0))) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_E)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_D)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_C)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_B)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_A)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_9)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_8)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_7)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_6)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_5)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_4)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_3)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_2)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_1)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_0)))) then
any_state_2_6_reg_10407 <= any_state_2_5_reg_8472;
end if;
end if;
end process;
-- any_state_3_1_reg_1693 assign process. --
any_state_3_1_reg_1693_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_ST_st17_fsm_16 = ap_CS_fsm)) then
any_state_3_1_reg_1693 <= any_state_3_2_reg_3460;
elsif (((ap_ST_st7_fsm_6 = ap_CS_fsm) and (ap_const_lv1_0 = tmp_6_fu_13097_p2))) then
any_state_3_1_reg_1693 <= any_state_3_reg_1152;
end if;
end if;
end process;
-- any_state_3_2_reg_3460 assign process. --
any_state_3_2_reg_3460_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((tmp_36_reg_14538 = ap_const_lv4_3) and (ap_ST_st10_fsm_9 = ap_CS_fsm))) then
any_state_3_2_reg_3460 <= ap_const_lv1_0;
elsif (((ap_ST_st10_fsm_9 = ap_CS_fsm) or ((tmp_36_reg_14538 = ap_const_lv4_E) and (ap_ST_st10_fsm_9 = ap_CS_fsm)) or ((tmp_36_reg_14538 = ap_const_lv4_D) and (ap_ST_st10_fsm_9 = ap_CS_fsm)) or ((tmp_36_reg_14538 = ap_const_lv4_C) and (ap_ST_st10_fsm_9 = ap_CS_fsm)) or ((tmp_36_reg_14538 = ap_const_lv4_B) and (ap_ST_st10_fsm_9 = ap_CS_fsm)) or ((tmp_36_reg_14538 = ap_const_lv4_A) and (ap_ST_st10_fsm_9 = ap_CS_fsm)) or ((tmp_36_reg_14538 = ap_const_lv4_9) and (ap_ST_st10_fsm_9 = ap_CS_fsm)) or ((tmp_36_reg_14538 = ap_const_lv4_8) and (ap_ST_st10_fsm_9 = ap_CS_fsm)) or ((tmp_36_reg_14538 = ap_const_lv4_7) and (ap_ST_st10_fsm_9 = ap_CS_fsm)) or ((tmp_36_reg_14538 = ap_const_lv4_6) and (ap_ST_st10_fsm_9 = ap_CS_fsm)) or ((tmp_36_reg_14538 = ap_const_lv4_5) and (ap_ST_st10_fsm_9 = ap_CS_fsm)) or ((tmp_36_reg_14538 = ap_const_lv4_4) and (ap_ST_st10_fsm_9 = ap_CS_fsm)) or ((tmp_36_reg_14538 = ap_const_lv4_2) and (ap_ST_st10_fsm_9 = ap_CS_fsm)) or ((tmp_36_reg_14538 = ap_const_lv4_1) and (ap_ST_st10_fsm_9 = ap_CS_fsm)) or ((tmp_36_reg_14538 = ap_const_lv4_0) and (ap_ST_st10_fsm_9 = ap_CS_fsm)))) then
any_state_3_2_reg_3460 <= any_state_3_1_reg_1693;
end if;
end if;
end process;
-- any_state_3_3_reg_4215 assign process. --
any_state_3_3_reg_4215_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ST_st44_fsm_43 = ap_CS_fsm) and not((ap_const_lv1_0 = exitcond_fu_13718_p2)) and (ap_const_lv1_0 = all_end_phi_fu_12651_p36))) then
any_state_3_3_reg_4215 <= any_state_3_4_reg_5271;
elsif (((ap_ST_st8_fsm_7 = ap_CS_fsm) and not((exitcond2_fu_13247_p2 = ap_const_lv1_0)))) then
any_state_3_3_reg_4215 <= any_state_3_1_reg_1693;
end if;
end if;
end process;
-- any_state_3_4_reg_5271 assign process. --
any_state_3_4_reg_5271_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ST_st43_fsm_42 = ap_CS_fsm) or ((ap_ST_st32_fsm_31 = ap_CS_fsm) and ((not((ap_const_lv1_0 = end_load_3_phi_phi_fu_11584_p32)) and (ap_const_lv1_0 = brmerge_demorgan_reg_14680)) or (not((ap_const_lv1_0 = end_load_3_phi_phi_fu_11584_p32)) and not((ap_const_lv1_0 = tmp1_fu_13626_p2))))))) then
any_state_3_4_reg_5271 <= any_state_3_6_reg_10348;
elsif ((ap_ST_st18_fsm_17 = ap_CS_fsm)) then
any_state_3_4_reg_5271 <= any_state_3_3_reg_4215;
end if;
end if;
end process;
-- any_state_3_5_reg_8417 assign process. --
any_state_3_5_reg_8417_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and (ap_const_lv1_0 = end_0_phi_fu_5844_p32) and (tmp_37_fu_13557_p1 = ap_const_lv4_3))) then
any_state_3_5_reg_8417 <= ap_const_lv1_1;
elsif ((((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and (ap_const_lv1_0 = end_0_phi_fu_5844_p32)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and (ap_const_lv1_0 = end_0_phi_fu_5844_p32) and (tmp_37_fu_13557_p1 = ap_const_lv4_D)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and (ap_const_lv1_0 = end_0_phi_fu_5844_p32) and (tmp_37_fu_13557_p1 = ap_const_lv4_C)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and (ap_const_lv1_0 = end_0_phi_fu_5844_p32) and (tmp_37_fu_13557_p1 = ap_const_lv4_B)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and (ap_const_lv1_0 = end_0_phi_fu_5844_p32) and (tmp_37_fu_13557_p1 = ap_const_lv4_A)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and (ap_const_lv1_0 = end_0_phi_fu_5844_p32) and (tmp_37_fu_13557_p1 = ap_const_lv4_9)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and (ap_const_lv1_0 = end_0_phi_fu_5844_p32) and (tmp_37_fu_13557_p1 = ap_const_lv4_8)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and (ap_const_lv1_0 = end_0_phi_fu_5844_p32) and (tmp_37_fu_13557_p1 = ap_const_lv4_7)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and (ap_const_lv1_0 = end_0_phi_fu_5844_p32) and (tmp_37_fu_13557_p1 = ap_const_lv4_6)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and (ap_const_lv1_0 = end_0_phi_fu_5844_p32) and (tmp_37_fu_13557_p1 = ap_const_lv4_5)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and (ap_const_lv1_0 = end_0_phi_fu_5844_p32) and (tmp_37_fu_13557_p1 = ap_const_lv4_4)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and (ap_const_lv1_0 = end_0_phi_fu_5844_p32) and (tmp_37_fu_13557_p1 = ap_const_lv4_2)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and (ap_const_lv1_0 = end_0_phi_fu_5844_p32) and (tmp_37_fu_13557_p1 = ap_const_lv4_1)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and (ap_const_lv1_0 = end_0_phi_fu_5844_p32) and (tmp_37_fu_13557_p1 = ap_const_lv4_0)))) then
any_state_3_5_reg_8417 <= any_state_3_4_reg_5271;
end if;
end if;
end process;
-- any_state_3_6_reg_10348 assign process. --
any_state_3_6_reg_10348_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ST_st30_fsm_29 = ap_CS_fsm) and not((ap_const_lv1_0 = end_0_reg_5841)))) then
any_state_3_6_reg_10348 <= any_state_3_4_reg_5271;
elsif ((((ap_ST_st22_fsm_21 = ap_CS_fsm) and not((tmp_37_reg_14631 = ap_const_lv4_E)) and not((tmp_37_reg_14631 = ap_const_lv4_D)) and not((tmp_37_reg_14631 = ap_const_lv4_C)) and not((tmp_37_reg_14631 = ap_const_lv4_B)) and not((tmp_37_reg_14631 = ap_const_lv4_A)) and not((tmp_37_reg_14631 = ap_const_lv4_9)) and not((tmp_37_reg_14631 = ap_const_lv4_8)) and not((tmp_37_reg_14631 = ap_const_lv4_7)) and not((tmp_37_reg_14631 = ap_const_lv4_6)) and not((tmp_37_reg_14631 = ap_const_lv4_5)) and not((tmp_37_reg_14631 = ap_const_lv4_4)) and not((tmp_37_reg_14631 = ap_const_lv4_3)) and not((tmp_37_reg_14631 = ap_const_lv4_2)) and not((tmp_37_reg_14631 = ap_const_lv4_1)) and not((tmp_37_reg_14631 = ap_const_lv4_0))) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_E)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_D)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_C)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_B)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_A)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_9)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_8)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_7)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_6)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_5)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_4)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_3)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_2)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_1)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_0)))) then
any_state_3_6_reg_10348 <= any_state_3_5_reg_8417;
end if;
end if;
end process;
-- any_state_4_1_reg_1682 assign process. --
any_state_4_1_reg_1682_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_ST_st17_fsm_16 = ap_CS_fsm)) then
any_state_4_1_reg_1682 <= any_state_4_2_reg_3404;
elsif (((ap_ST_st7_fsm_6 = ap_CS_fsm) and (ap_const_lv1_0 = tmp_6_fu_13097_p2))) then
any_state_4_1_reg_1682 <= any_state_4_reg_1140;
end if;
end if;
end process;
-- any_state_4_2_reg_3404 assign process. --
any_state_4_2_reg_3404_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((tmp_36_reg_14538 = ap_const_lv4_4) and (ap_ST_st10_fsm_9 = ap_CS_fsm))) then
any_state_4_2_reg_3404 <= ap_const_lv1_0;
elsif (((ap_ST_st10_fsm_9 = ap_CS_fsm) or ((tmp_36_reg_14538 = ap_const_lv4_E) and (ap_ST_st10_fsm_9 = ap_CS_fsm)) or ((tmp_36_reg_14538 = ap_const_lv4_D) and (ap_ST_st10_fsm_9 = ap_CS_fsm)) or ((tmp_36_reg_14538 = ap_const_lv4_C) and (ap_ST_st10_fsm_9 = ap_CS_fsm)) or ((tmp_36_reg_14538 = ap_const_lv4_B) and (ap_ST_st10_fsm_9 = ap_CS_fsm)) or ((tmp_36_reg_14538 = ap_const_lv4_A) and (ap_ST_st10_fsm_9 = ap_CS_fsm)) or ((tmp_36_reg_14538 = ap_const_lv4_9) and (ap_ST_st10_fsm_9 = ap_CS_fsm)) or ((tmp_36_reg_14538 = ap_const_lv4_8) and (ap_ST_st10_fsm_9 = ap_CS_fsm)) or ((tmp_36_reg_14538 = ap_const_lv4_7) and (ap_ST_st10_fsm_9 = ap_CS_fsm)) or ((tmp_36_reg_14538 = ap_const_lv4_6) and (ap_ST_st10_fsm_9 = ap_CS_fsm)) or ((tmp_36_reg_14538 = ap_const_lv4_5) and (ap_ST_st10_fsm_9 = ap_CS_fsm)) or ((tmp_36_reg_14538 = ap_const_lv4_3) and (ap_ST_st10_fsm_9 = ap_CS_fsm)) or ((tmp_36_reg_14538 = ap_const_lv4_2) and (ap_ST_st10_fsm_9 = ap_CS_fsm)) or ((tmp_36_reg_14538 = ap_const_lv4_1) and (ap_ST_st10_fsm_9 = ap_CS_fsm)) or ((tmp_36_reg_14538 = ap_const_lv4_0) and (ap_ST_st10_fsm_9 = ap_CS_fsm)))) then
any_state_4_2_reg_3404 <= any_state_4_1_reg_1682;
end if;
end if;
end process;
-- any_state_4_3_reg_4204 assign process. --
any_state_4_3_reg_4204_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ST_st44_fsm_43 = ap_CS_fsm) and not((ap_const_lv1_0 = exitcond_fu_13718_p2)) and (ap_const_lv1_0 = all_end_phi_fu_12651_p36))) then
any_state_4_3_reg_4204 <= any_state_4_4_reg_5256;
elsif (((ap_ST_st8_fsm_7 = ap_CS_fsm) and not((exitcond2_fu_13247_p2 = ap_const_lv1_0)))) then
any_state_4_3_reg_4204 <= any_state_4_1_reg_1682;
end if;
end if;
end process;
-- any_state_4_4_reg_5256 assign process. --
any_state_4_4_reg_5256_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ST_st43_fsm_42 = ap_CS_fsm) or ((ap_ST_st32_fsm_31 = ap_CS_fsm) and ((not((ap_const_lv1_0 = end_load_3_phi_phi_fu_11584_p32)) and (ap_const_lv1_0 = brmerge_demorgan_reg_14680)) or (not((ap_const_lv1_0 = end_load_3_phi_phi_fu_11584_p32)) and not((ap_const_lv1_0 = tmp1_fu_13626_p2))))))) then
any_state_4_4_reg_5256 <= any_state_4_6_reg_10289;
elsif ((ap_ST_st18_fsm_17 = ap_CS_fsm)) then
any_state_4_4_reg_5256 <= any_state_4_3_reg_4204;
end if;
end if;
end process;
-- any_state_4_5_reg_8362 assign process. --
any_state_4_5_reg_8362_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and (ap_const_lv1_0 = end_0_phi_fu_5844_p32) and (tmp_37_fu_13557_p1 = ap_const_lv4_4))) then
any_state_4_5_reg_8362 <= ap_const_lv1_1;
elsif ((((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and (ap_const_lv1_0 = end_0_phi_fu_5844_p32)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and (ap_const_lv1_0 = end_0_phi_fu_5844_p32) and (tmp_37_fu_13557_p1 = ap_const_lv4_D)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and (ap_const_lv1_0 = end_0_phi_fu_5844_p32) and (tmp_37_fu_13557_p1 = ap_const_lv4_C)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and (ap_const_lv1_0 = end_0_phi_fu_5844_p32) and (tmp_37_fu_13557_p1 = ap_const_lv4_B)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and (ap_const_lv1_0 = end_0_phi_fu_5844_p32) and (tmp_37_fu_13557_p1 = ap_const_lv4_A)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and (ap_const_lv1_0 = end_0_phi_fu_5844_p32) and (tmp_37_fu_13557_p1 = ap_const_lv4_9)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and (ap_const_lv1_0 = end_0_phi_fu_5844_p32) and (tmp_37_fu_13557_p1 = ap_const_lv4_8)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and (ap_const_lv1_0 = end_0_phi_fu_5844_p32) and (tmp_37_fu_13557_p1 = ap_const_lv4_7)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and (ap_const_lv1_0 = end_0_phi_fu_5844_p32) and (tmp_37_fu_13557_p1 = ap_const_lv4_6)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and (ap_const_lv1_0 = end_0_phi_fu_5844_p32) and (tmp_37_fu_13557_p1 = ap_const_lv4_5)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and (ap_const_lv1_0 = end_0_phi_fu_5844_p32) and (tmp_37_fu_13557_p1 = ap_const_lv4_3)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and (ap_const_lv1_0 = end_0_phi_fu_5844_p32) and (tmp_37_fu_13557_p1 = ap_const_lv4_2)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and (ap_const_lv1_0 = end_0_phi_fu_5844_p32) and (tmp_37_fu_13557_p1 = ap_const_lv4_1)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and (ap_const_lv1_0 = end_0_phi_fu_5844_p32) and (tmp_37_fu_13557_p1 = ap_const_lv4_0)))) then
any_state_4_5_reg_8362 <= any_state_4_4_reg_5256;
end if;
end if;
end process;
-- any_state_4_6_reg_10289 assign process. --
any_state_4_6_reg_10289_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ST_st30_fsm_29 = ap_CS_fsm) and not((ap_const_lv1_0 = end_0_reg_5841)))) then
any_state_4_6_reg_10289 <= any_state_4_4_reg_5256;
elsif ((((ap_ST_st22_fsm_21 = ap_CS_fsm) and not((tmp_37_reg_14631 = ap_const_lv4_E)) and not((tmp_37_reg_14631 = ap_const_lv4_D)) and not((tmp_37_reg_14631 = ap_const_lv4_C)) and not((tmp_37_reg_14631 = ap_const_lv4_B)) and not((tmp_37_reg_14631 = ap_const_lv4_A)) and not((tmp_37_reg_14631 = ap_const_lv4_9)) and not((tmp_37_reg_14631 = ap_const_lv4_8)) and not((tmp_37_reg_14631 = ap_const_lv4_7)) and not((tmp_37_reg_14631 = ap_const_lv4_6)) and not((tmp_37_reg_14631 = ap_const_lv4_5)) and not((tmp_37_reg_14631 = ap_const_lv4_4)) and not((tmp_37_reg_14631 = ap_const_lv4_3)) and not((tmp_37_reg_14631 = ap_const_lv4_2)) and not((tmp_37_reg_14631 = ap_const_lv4_1)) and not((tmp_37_reg_14631 = ap_const_lv4_0))) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_E)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_D)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_C)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_B)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_A)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_9)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_8)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_7)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_6)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_5)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_4)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_3)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_2)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_1)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_0)))) then
any_state_4_6_reg_10289 <= any_state_4_5_reg_8362;
end if;
end if;
end process;
-- any_state_5_1_reg_1671 assign process. --
any_state_5_1_reg_1671_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_ST_st17_fsm_16 = ap_CS_fsm)) then
any_state_5_1_reg_1671 <= any_state_5_2_reg_3348;
elsif (((ap_ST_st7_fsm_6 = ap_CS_fsm) and (ap_const_lv1_0 = tmp_6_fu_13097_p2))) then
any_state_5_1_reg_1671 <= any_state_5_reg_1128;
end if;
end if;
end process;
-- any_state_5_2_reg_3348 assign process. --
any_state_5_2_reg_3348_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((tmp_36_reg_14538 = ap_const_lv4_5) and (ap_ST_st10_fsm_9 = ap_CS_fsm))) then
any_state_5_2_reg_3348 <= ap_const_lv1_0;
elsif (((ap_ST_st10_fsm_9 = ap_CS_fsm) or ((tmp_36_reg_14538 = ap_const_lv4_E) and (ap_ST_st10_fsm_9 = ap_CS_fsm)) or ((tmp_36_reg_14538 = ap_const_lv4_D) and (ap_ST_st10_fsm_9 = ap_CS_fsm)) or ((tmp_36_reg_14538 = ap_const_lv4_C) and (ap_ST_st10_fsm_9 = ap_CS_fsm)) or ((tmp_36_reg_14538 = ap_const_lv4_B) and (ap_ST_st10_fsm_9 = ap_CS_fsm)) or ((tmp_36_reg_14538 = ap_const_lv4_A) and (ap_ST_st10_fsm_9 = ap_CS_fsm)) or ((tmp_36_reg_14538 = ap_const_lv4_9) and (ap_ST_st10_fsm_9 = ap_CS_fsm)) or ((tmp_36_reg_14538 = ap_const_lv4_8) and (ap_ST_st10_fsm_9 = ap_CS_fsm)) or ((tmp_36_reg_14538 = ap_const_lv4_7) and (ap_ST_st10_fsm_9 = ap_CS_fsm)) or ((tmp_36_reg_14538 = ap_const_lv4_6) and (ap_ST_st10_fsm_9 = ap_CS_fsm)) or ((tmp_36_reg_14538 = ap_const_lv4_4) and (ap_ST_st10_fsm_9 = ap_CS_fsm)) or ((tmp_36_reg_14538 = ap_const_lv4_3) and (ap_ST_st10_fsm_9 = ap_CS_fsm)) or ((tmp_36_reg_14538 = ap_const_lv4_2) and (ap_ST_st10_fsm_9 = ap_CS_fsm)) or ((tmp_36_reg_14538 = ap_const_lv4_1) and (ap_ST_st10_fsm_9 = ap_CS_fsm)) or ((tmp_36_reg_14538 = ap_const_lv4_0) and (ap_ST_st10_fsm_9 = ap_CS_fsm)))) then
any_state_5_2_reg_3348 <= any_state_5_1_reg_1671;
end if;
end if;
end process;
-- any_state_5_3_reg_4193 assign process. --
any_state_5_3_reg_4193_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ST_st44_fsm_43 = ap_CS_fsm) and not((ap_const_lv1_0 = exitcond_fu_13718_p2)) and (ap_const_lv1_0 = all_end_phi_fu_12651_p36))) then
any_state_5_3_reg_4193 <= any_state_5_4_reg_5241;
elsif (((ap_ST_st8_fsm_7 = ap_CS_fsm) and not((exitcond2_fu_13247_p2 = ap_const_lv1_0)))) then
any_state_5_3_reg_4193 <= any_state_5_1_reg_1671;
end if;
end if;
end process;
-- any_state_5_4_reg_5241 assign process. --
any_state_5_4_reg_5241_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ST_st43_fsm_42 = ap_CS_fsm) or ((ap_ST_st32_fsm_31 = ap_CS_fsm) and ((not((ap_const_lv1_0 = end_load_3_phi_phi_fu_11584_p32)) and (ap_const_lv1_0 = brmerge_demorgan_reg_14680)) or (not((ap_const_lv1_0 = end_load_3_phi_phi_fu_11584_p32)) and not((ap_const_lv1_0 = tmp1_fu_13626_p2))))))) then
any_state_5_4_reg_5241 <= any_state_5_6_reg_10230;
elsif ((ap_ST_st18_fsm_17 = ap_CS_fsm)) then
any_state_5_4_reg_5241 <= any_state_5_3_reg_4193;
end if;
end if;
end process;
-- any_state_5_5_reg_8307 assign process. --
any_state_5_5_reg_8307_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and (ap_const_lv1_0 = end_0_phi_fu_5844_p32) and (tmp_37_fu_13557_p1 = ap_const_lv4_5))) then
any_state_5_5_reg_8307 <= ap_const_lv1_1;
elsif ((((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and (ap_const_lv1_0 = end_0_phi_fu_5844_p32)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and (ap_const_lv1_0 = end_0_phi_fu_5844_p32) and (tmp_37_fu_13557_p1 = ap_const_lv4_D)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and (ap_const_lv1_0 = end_0_phi_fu_5844_p32) and (tmp_37_fu_13557_p1 = ap_const_lv4_C)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and (ap_const_lv1_0 = end_0_phi_fu_5844_p32) and (tmp_37_fu_13557_p1 = ap_const_lv4_B)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and (ap_const_lv1_0 = end_0_phi_fu_5844_p32) and (tmp_37_fu_13557_p1 = ap_const_lv4_A)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and (ap_const_lv1_0 = end_0_phi_fu_5844_p32) and (tmp_37_fu_13557_p1 = ap_const_lv4_9)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and (ap_const_lv1_0 = end_0_phi_fu_5844_p32) and (tmp_37_fu_13557_p1 = ap_const_lv4_8)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and (ap_const_lv1_0 = end_0_phi_fu_5844_p32) and (tmp_37_fu_13557_p1 = ap_const_lv4_7)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and (ap_const_lv1_0 = end_0_phi_fu_5844_p32) and (tmp_37_fu_13557_p1 = ap_const_lv4_6)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and (ap_const_lv1_0 = end_0_phi_fu_5844_p32) and (tmp_37_fu_13557_p1 = ap_const_lv4_4)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and (ap_const_lv1_0 = end_0_phi_fu_5844_p32) and (tmp_37_fu_13557_p1 = ap_const_lv4_3)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and (ap_const_lv1_0 = end_0_phi_fu_5844_p32) and (tmp_37_fu_13557_p1 = ap_const_lv4_2)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and (ap_const_lv1_0 = end_0_phi_fu_5844_p32) and (tmp_37_fu_13557_p1 = ap_const_lv4_1)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and (ap_const_lv1_0 = end_0_phi_fu_5844_p32) and (tmp_37_fu_13557_p1 = ap_const_lv4_0)))) then
any_state_5_5_reg_8307 <= any_state_5_4_reg_5241;
end if;
end if;
end process;
-- any_state_5_6_reg_10230 assign process. --
any_state_5_6_reg_10230_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ST_st30_fsm_29 = ap_CS_fsm) and not((ap_const_lv1_0 = end_0_reg_5841)))) then
any_state_5_6_reg_10230 <= any_state_5_4_reg_5241;
elsif ((((ap_ST_st22_fsm_21 = ap_CS_fsm) and not((tmp_37_reg_14631 = ap_const_lv4_E)) and not((tmp_37_reg_14631 = ap_const_lv4_D)) and not((tmp_37_reg_14631 = ap_const_lv4_C)) and not((tmp_37_reg_14631 = ap_const_lv4_B)) and not((tmp_37_reg_14631 = ap_const_lv4_A)) and not((tmp_37_reg_14631 = ap_const_lv4_9)) and not((tmp_37_reg_14631 = ap_const_lv4_8)) and not((tmp_37_reg_14631 = ap_const_lv4_7)) and not((tmp_37_reg_14631 = ap_const_lv4_6)) and not((tmp_37_reg_14631 = ap_const_lv4_5)) and not((tmp_37_reg_14631 = ap_const_lv4_4)) and not((tmp_37_reg_14631 = ap_const_lv4_3)) and not((tmp_37_reg_14631 = ap_const_lv4_2)) and not((tmp_37_reg_14631 = ap_const_lv4_1)) and not((tmp_37_reg_14631 = ap_const_lv4_0))) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_E)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_D)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_C)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_B)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_A)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_9)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_8)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_7)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_6)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_5)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_4)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_3)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_2)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_1)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_0)))) then
any_state_5_6_reg_10230 <= any_state_5_5_reg_8307;
end if;
end if;
end process;
-- any_state_6_1_reg_1660 assign process. --
any_state_6_1_reg_1660_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_ST_st17_fsm_16 = ap_CS_fsm)) then
any_state_6_1_reg_1660 <= any_state_6_2_reg_3292;
elsif (((ap_ST_st7_fsm_6 = ap_CS_fsm) and (ap_const_lv1_0 = tmp_6_fu_13097_p2))) then
any_state_6_1_reg_1660 <= any_state_6_reg_1116;
end if;
end if;
end process;
-- any_state_6_2_reg_3292 assign process. --
any_state_6_2_reg_3292_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((tmp_36_reg_14538 = ap_const_lv4_6) and (ap_ST_st10_fsm_9 = ap_CS_fsm))) then
any_state_6_2_reg_3292 <= ap_const_lv1_0;
elsif (((ap_ST_st10_fsm_9 = ap_CS_fsm) or ((tmp_36_reg_14538 = ap_const_lv4_E) and (ap_ST_st10_fsm_9 = ap_CS_fsm)) or ((tmp_36_reg_14538 = ap_const_lv4_D) and (ap_ST_st10_fsm_9 = ap_CS_fsm)) or ((tmp_36_reg_14538 = ap_const_lv4_C) and (ap_ST_st10_fsm_9 = ap_CS_fsm)) or ((tmp_36_reg_14538 = ap_const_lv4_B) and (ap_ST_st10_fsm_9 = ap_CS_fsm)) or ((tmp_36_reg_14538 = ap_const_lv4_A) and (ap_ST_st10_fsm_9 = ap_CS_fsm)) or ((tmp_36_reg_14538 = ap_const_lv4_9) and (ap_ST_st10_fsm_9 = ap_CS_fsm)) or ((tmp_36_reg_14538 = ap_const_lv4_8) and (ap_ST_st10_fsm_9 = ap_CS_fsm)) or ((tmp_36_reg_14538 = ap_const_lv4_7) and (ap_ST_st10_fsm_9 = ap_CS_fsm)) or ((tmp_36_reg_14538 = ap_const_lv4_5) and (ap_ST_st10_fsm_9 = ap_CS_fsm)) or ((tmp_36_reg_14538 = ap_const_lv4_4) and (ap_ST_st10_fsm_9 = ap_CS_fsm)) or ((tmp_36_reg_14538 = ap_const_lv4_3) and (ap_ST_st10_fsm_9 = ap_CS_fsm)) or ((tmp_36_reg_14538 = ap_const_lv4_2) and (ap_ST_st10_fsm_9 = ap_CS_fsm)) or ((tmp_36_reg_14538 = ap_const_lv4_1) and (ap_ST_st10_fsm_9 = ap_CS_fsm)) or ((tmp_36_reg_14538 = ap_const_lv4_0) and (ap_ST_st10_fsm_9 = ap_CS_fsm)))) then
any_state_6_2_reg_3292 <= any_state_6_1_reg_1660;
end if;
end if;
end process;
-- any_state_6_3_reg_4182 assign process. --
any_state_6_3_reg_4182_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ST_st44_fsm_43 = ap_CS_fsm) and not((ap_const_lv1_0 = exitcond_fu_13718_p2)) and (ap_const_lv1_0 = all_end_phi_fu_12651_p36))) then
any_state_6_3_reg_4182 <= any_state_6_4_reg_5226;
elsif (((ap_ST_st8_fsm_7 = ap_CS_fsm) and not((exitcond2_fu_13247_p2 = ap_const_lv1_0)))) then
any_state_6_3_reg_4182 <= any_state_6_1_reg_1660;
end if;
end if;
end process;
-- any_state_6_4_reg_5226 assign process. --
any_state_6_4_reg_5226_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ST_st43_fsm_42 = ap_CS_fsm) or ((ap_ST_st32_fsm_31 = ap_CS_fsm) and ((not((ap_const_lv1_0 = end_load_3_phi_phi_fu_11584_p32)) and (ap_const_lv1_0 = brmerge_demorgan_reg_14680)) or (not((ap_const_lv1_0 = end_load_3_phi_phi_fu_11584_p32)) and not((ap_const_lv1_0 = tmp1_fu_13626_p2))))))) then
any_state_6_4_reg_5226 <= any_state_6_6_reg_10171;
elsif ((ap_ST_st18_fsm_17 = ap_CS_fsm)) then
any_state_6_4_reg_5226 <= any_state_6_3_reg_4182;
end if;
end if;
end process;
-- any_state_6_5_reg_8252 assign process. --
any_state_6_5_reg_8252_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and (ap_const_lv1_0 = end_0_phi_fu_5844_p32) and (tmp_37_fu_13557_p1 = ap_const_lv4_6))) then
any_state_6_5_reg_8252 <= ap_const_lv1_1;
elsif ((((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and (ap_const_lv1_0 = end_0_phi_fu_5844_p32)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and (ap_const_lv1_0 = end_0_phi_fu_5844_p32) and (tmp_37_fu_13557_p1 = ap_const_lv4_D)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and (ap_const_lv1_0 = end_0_phi_fu_5844_p32) and (tmp_37_fu_13557_p1 = ap_const_lv4_C)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and (ap_const_lv1_0 = end_0_phi_fu_5844_p32) and (tmp_37_fu_13557_p1 = ap_const_lv4_B)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and (ap_const_lv1_0 = end_0_phi_fu_5844_p32) and (tmp_37_fu_13557_p1 = ap_const_lv4_A)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and (ap_const_lv1_0 = end_0_phi_fu_5844_p32) and (tmp_37_fu_13557_p1 = ap_const_lv4_9)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and (ap_const_lv1_0 = end_0_phi_fu_5844_p32) and (tmp_37_fu_13557_p1 = ap_const_lv4_8)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and (ap_const_lv1_0 = end_0_phi_fu_5844_p32) and (tmp_37_fu_13557_p1 = ap_const_lv4_7)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and (ap_const_lv1_0 = end_0_phi_fu_5844_p32) and (tmp_37_fu_13557_p1 = ap_const_lv4_5)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and (ap_const_lv1_0 = end_0_phi_fu_5844_p32) and (tmp_37_fu_13557_p1 = ap_const_lv4_4)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and (ap_const_lv1_0 = end_0_phi_fu_5844_p32) and (tmp_37_fu_13557_p1 = ap_const_lv4_3)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and (ap_const_lv1_0 = end_0_phi_fu_5844_p32) and (tmp_37_fu_13557_p1 = ap_const_lv4_2)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and (ap_const_lv1_0 = end_0_phi_fu_5844_p32) and (tmp_37_fu_13557_p1 = ap_const_lv4_1)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and (ap_const_lv1_0 = end_0_phi_fu_5844_p32) and (tmp_37_fu_13557_p1 = ap_const_lv4_0)))) then
any_state_6_5_reg_8252 <= any_state_6_4_reg_5226;
end if;
end if;
end process;
-- any_state_6_6_reg_10171 assign process. --
any_state_6_6_reg_10171_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ST_st30_fsm_29 = ap_CS_fsm) and not((ap_const_lv1_0 = end_0_reg_5841)))) then
any_state_6_6_reg_10171 <= any_state_6_4_reg_5226;
elsif ((((ap_ST_st22_fsm_21 = ap_CS_fsm) and not((tmp_37_reg_14631 = ap_const_lv4_E)) and not((tmp_37_reg_14631 = ap_const_lv4_D)) and not((tmp_37_reg_14631 = ap_const_lv4_C)) and not((tmp_37_reg_14631 = ap_const_lv4_B)) and not((tmp_37_reg_14631 = ap_const_lv4_A)) and not((tmp_37_reg_14631 = ap_const_lv4_9)) and not((tmp_37_reg_14631 = ap_const_lv4_8)) and not((tmp_37_reg_14631 = ap_const_lv4_7)) and not((tmp_37_reg_14631 = ap_const_lv4_6)) and not((tmp_37_reg_14631 = ap_const_lv4_5)) and not((tmp_37_reg_14631 = ap_const_lv4_4)) and not((tmp_37_reg_14631 = ap_const_lv4_3)) and not((tmp_37_reg_14631 = ap_const_lv4_2)) and not((tmp_37_reg_14631 = ap_const_lv4_1)) and not((tmp_37_reg_14631 = ap_const_lv4_0))) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_E)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_D)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_C)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_B)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_A)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_9)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_8)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_7)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_6)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_5)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_4)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_3)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_2)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_1)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_0)))) then
any_state_6_6_reg_10171 <= any_state_6_5_reg_8252;
end if;
end if;
end process;
-- any_state_7_1_reg_1649 assign process. --
any_state_7_1_reg_1649_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_ST_st17_fsm_16 = ap_CS_fsm)) then
any_state_7_1_reg_1649 <= any_state_7_2_reg_3236;
elsif (((ap_ST_st7_fsm_6 = ap_CS_fsm) and (ap_const_lv1_0 = tmp_6_fu_13097_p2))) then
any_state_7_1_reg_1649 <= any_state_7_reg_1104;
end if;
end if;
end process;
-- any_state_7_2_reg_3236 assign process. --
any_state_7_2_reg_3236_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((tmp_36_reg_14538 = ap_const_lv4_7) and (ap_ST_st10_fsm_9 = ap_CS_fsm))) then
any_state_7_2_reg_3236 <= ap_const_lv1_0;
elsif (((ap_ST_st10_fsm_9 = ap_CS_fsm) or ((tmp_36_reg_14538 = ap_const_lv4_E) and (ap_ST_st10_fsm_9 = ap_CS_fsm)) or ((tmp_36_reg_14538 = ap_const_lv4_D) and (ap_ST_st10_fsm_9 = ap_CS_fsm)) or ((tmp_36_reg_14538 = ap_const_lv4_C) and (ap_ST_st10_fsm_9 = ap_CS_fsm)) or ((tmp_36_reg_14538 = ap_const_lv4_B) and (ap_ST_st10_fsm_9 = ap_CS_fsm)) or ((tmp_36_reg_14538 = ap_const_lv4_A) and (ap_ST_st10_fsm_9 = ap_CS_fsm)) or ((tmp_36_reg_14538 = ap_const_lv4_9) and (ap_ST_st10_fsm_9 = ap_CS_fsm)) or ((tmp_36_reg_14538 = ap_const_lv4_8) and (ap_ST_st10_fsm_9 = ap_CS_fsm)) or ((tmp_36_reg_14538 = ap_const_lv4_6) and (ap_ST_st10_fsm_9 = ap_CS_fsm)) or ((tmp_36_reg_14538 = ap_const_lv4_5) and (ap_ST_st10_fsm_9 = ap_CS_fsm)) or ((tmp_36_reg_14538 = ap_const_lv4_4) and (ap_ST_st10_fsm_9 = ap_CS_fsm)) or ((tmp_36_reg_14538 = ap_const_lv4_3) and (ap_ST_st10_fsm_9 = ap_CS_fsm)) or ((tmp_36_reg_14538 = ap_const_lv4_2) and (ap_ST_st10_fsm_9 = ap_CS_fsm)) or ((tmp_36_reg_14538 = ap_const_lv4_1) and (ap_ST_st10_fsm_9 = ap_CS_fsm)) or ((tmp_36_reg_14538 = ap_const_lv4_0) and (ap_ST_st10_fsm_9 = ap_CS_fsm)))) then
any_state_7_2_reg_3236 <= any_state_7_1_reg_1649;
end if;
end if;
end process;
-- any_state_7_3_reg_4171 assign process. --
any_state_7_3_reg_4171_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ST_st44_fsm_43 = ap_CS_fsm) and not((ap_const_lv1_0 = exitcond_fu_13718_p2)) and (ap_const_lv1_0 = all_end_phi_fu_12651_p36))) then
any_state_7_3_reg_4171 <= any_state_7_4_reg_5211;
elsif (((ap_ST_st8_fsm_7 = ap_CS_fsm) and not((exitcond2_fu_13247_p2 = ap_const_lv1_0)))) then
any_state_7_3_reg_4171 <= any_state_7_1_reg_1649;
end if;
end if;
end process;
-- any_state_7_4_reg_5211 assign process. --
any_state_7_4_reg_5211_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ST_st43_fsm_42 = ap_CS_fsm) or ((ap_ST_st32_fsm_31 = ap_CS_fsm) and ((not((ap_const_lv1_0 = end_load_3_phi_phi_fu_11584_p32)) and (ap_const_lv1_0 = brmerge_demorgan_reg_14680)) or (not((ap_const_lv1_0 = end_load_3_phi_phi_fu_11584_p32)) and not((ap_const_lv1_0 = tmp1_fu_13626_p2))))))) then
any_state_7_4_reg_5211 <= any_state_7_6_reg_10112;
elsif ((ap_ST_st18_fsm_17 = ap_CS_fsm)) then
any_state_7_4_reg_5211 <= any_state_7_3_reg_4171;
end if;
end if;
end process;
-- any_state_7_5_reg_8197 assign process. --
any_state_7_5_reg_8197_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and (ap_const_lv1_0 = end_0_phi_fu_5844_p32) and (tmp_37_fu_13557_p1 = ap_const_lv4_7))) then
any_state_7_5_reg_8197 <= ap_const_lv1_1;
elsif ((((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and (ap_const_lv1_0 = end_0_phi_fu_5844_p32)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and (ap_const_lv1_0 = end_0_phi_fu_5844_p32) and (tmp_37_fu_13557_p1 = ap_const_lv4_D)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and (ap_const_lv1_0 = end_0_phi_fu_5844_p32) and (tmp_37_fu_13557_p1 = ap_const_lv4_C)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and (ap_const_lv1_0 = end_0_phi_fu_5844_p32) and (tmp_37_fu_13557_p1 = ap_const_lv4_B)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and (ap_const_lv1_0 = end_0_phi_fu_5844_p32) and (tmp_37_fu_13557_p1 = ap_const_lv4_A)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and (ap_const_lv1_0 = end_0_phi_fu_5844_p32) and (tmp_37_fu_13557_p1 = ap_const_lv4_9)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and (ap_const_lv1_0 = end_0_phi_fu_5844_p32) and (tmp_37_fu_13557_p1 = ap_const_lv4_8)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and (ap_const_lv1_0 = end_0_phi_fu_5844_p32) and (tmp_37_fu_13557_p1 = ap_const_lv4_6)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and (ap_const_lv1_0 = end_0_phi_fu_5844_p32) and (tmp_37_fu_13557_p1 = ap_const_lv4_5)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and (ap_const_lv1_0 = end_0_phi_fu_5844_p32) and (tmp_37_fu_13557_p1 = ap_const_lv4_4)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and (ap_const_lv1_0 = end_0_phi_fu_5844_p32) and (tmp_37_fu_13557_p1 = ap_const_lv4_3)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and (ap_const_lv1_0 = end_0_phi_fu_5844_p32) and (tmp_37_fu_13557_p1 = ap_const_lv4_2)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and (ap_const_lv1_0 = end_0_phi_fu_5844_p32) and (tmp_37_fu_13557_p1 = ap_const_lv4_1)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and (ap_const_lv1_0 = end_0_phi_fu_5844_p32) and (tmp_37_fu_13557_p1 = ap_const_lv4_0)))) then
any_state_7_5_reg_8197 <= any_state_7_4_reg_5211;
end if;
end if;
end process;
-- any_state_7_6_reg_10112 assign process. --
any_state_7_6_reg_10112_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ST_st30_fsm_29 = ap_CS_fsm) and not((ap_const_lv1_0 = end_0_reg_5841)))) then
any_state_7_6_reg_10112 <= any_state_7_4_reg_5211;
elsif ((((ap_ST_st22_fsm_21 = ap_CS_fsm) and not((tmp_37_reg_14631 = ap_const_lv4_E)) and not((tmp_37_reg_14631 = ap_const_lv4_D)) and not((tmp_37_reg_14631 = ap_const_lv4_C)) and not((tmp_37_reg_14631 = ap_const_lv4_B)) and not((tmp_37_reg_14631 = ap_const_lv4_A)) and not((tmp_37_reg_14631 = ap_const_lv4_9)) and not((tmp_37_reg_14631 = ap_const_lv4_8)) and not((tmp_37_reg_14631 = ap_const_lv4_7)) and not((tmp_37_reg_14631 = ap_const_lv4_6)) and not((tmp_37_reg_14631 = ap_const_lv4_5)) and not((tmp_37_reg_14631 = ap_const_lv4_4)) and not((tmp_37_reg_14631 = ap_const_lv4_3)) and not((tmp_37_reg_14631 = ap_const_lv4_2)) and not((tmp_37_reg_14631 = ap_const_lv4_1)) and not((tmp_37_reg_14631 = ap_const_lv4_0))) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_E)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_D)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_C)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_B)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_A)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_9)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_8)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_7)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_6)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_5)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_4)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_3)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_2)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_1)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_0)))) then
any_state_7_6_reg_10112 <= any_state_7_5_reg_8197;
end if;
end if;
end process;
-- any_state_8_1_reg_1638 assign process. --
any_state_8_1_reg_1638_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_ST_st17_fsm_16 = ap_CS_fsm)) then
any_state_8_1_reg_1638 <= any_state_8_2_reg_3180;
elsif (((ap_ST_st7_fsm_6 = ap_CS_fsm) and (ap_const_lv1_0 = tmp_6_fu_13097_p2))) then
any_state_8_1_reg_1638 <= any_state_8_reg_1092;
end if;
end if;
end process;
-- any_state_8_2_reg_3180 assign process. --
any_state_8_2_reg_3180_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((tmp_36_reg_14538 = ap_const_lv4_8) and (ap_ST_st10_fsm_9 = ap_CS_fsm))) then
any_state_8_2_reg_3180 <= ap_const_lv1_0;
elsif (((ap_ST_st10_fsm_9 = ap_CS_fsm) or ((tmp_36_reg_14538 = ap_const_lv4_E) and (ap_ST_st10_fsm_9 = ap_CS_fsm)) or ((tmp_36_reg_14538 = ap_const_lv4_D) and (ap_ST_st10_fsm_9 = ap_CS_fsm)) or ((tmp_36_reg_14538 = ap_const_lv4_C) and (ap_ST_st10_fsm_9 = ap_CS_fsm)) or ((tmp_36_reg_14538 = ap_const_lv4_B) and (ap_ST_st10_fsm_9 = ap_CS_fsm)) or ((tmp_36_reg_14538 = ap_const_lv4_A) and (ap_ST_st10_fsm_9 = ap_CS_fsm)) or ((tmp_36_reg_14538 = ap_const_lv4_9) and (ap_ST_st10_fsm_9 = ap_CS_fsm)) or ((tmp_36_reg_14538 = ap_const_lv4_7) and (ap_ST_st10_fsm_9 = ap_CS_fsm)) or ((tmp_36_reg_14538 = ap_const_lv4_6) and (ap_ST_st10_fsm_9 = ap_CS_fsm)) or ((tmp_36_reg_14538 = ap_const_lv4_5) and (ap_ST_st10_fsm_9 = ap_CS_fsm)) or ((tmp_36_reg_14538 = ap_const_lv4_4) and (ap_ST_st10_fsm_9 = ap_CS_fsm)) or ((tmp_36_reg_14538 = ap_const_lv4_3) and (ap_ST_st10_fsm_9 = ap_CS_fsm)) or ((tmp_36_reg_14538 = ap_const_lv4_2) and (ap_ST_st10_fsm_9 = ap_CS_fsm)) or ((tmp_36_reg_14538 = ap_const_lv4_1) and (ap_ST_st10_fsm_9 = ap_CS_fsm)) or ((tmp_36_reg_14538 = ap_const_lv4_0) and (ap_ST_st10_fsm_9 = ap_CS_fsm)))) then
any_state_8_2_reg_3180 <= any_state_8_1_reg_1638;
end if;
end if;
end process;
-- any_state_8_3_reg_4160 assign process. --
any_state_8_3_reg_4160_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ST_st44_fsm_43 = ap_CS_fsm) and not((ap_const_lv1_0 = exitcond_fu_13718_p2)) and (ap_const_lv1_0 = all_end_phi_fu_12651_p36))) then
any_state_8_3_reg_4160 <= any_state_8_4_reg_5196;
elsif (((ap_ST_st8_fsm_7 = ap_CS_fsm) and not((exitcond2_fu_13247_p2 = ap_const_lv1_0)))) then
any_state_8_3_reg_4160 <= any_state_8_1_reg_1638;
end if;
end if;
end process;
-- any_state_8_4_reg_5196 assign process. --
any_state_8_4_reg_5196_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ST_st43_fsm_42 = ap_CS_fsm) or ((ap_ST_st32_fsm_31 = ap_CS_fsm) and ((not((ap_const_lv1_0 = end_load_3_phi_phi_fu_11584_p32)) and (ap_const_lv1_0 = brmerge_demorgan_reg_14680)) or (not((ap_const_lv1_0 = end_load_3_phi_phi_fu_11584_p32)) and not((ap_const_lv1_0 = tmp1_fu_13626_p2))))))) then
any_state_8_4_reg_5196 <= any_state_8_6_reg_10053;
elsif ((ap_ST_st18_fsm_17 = ap_CS_fsm)) then
any_state_8_4_reg_5196 <= any_state_8_3_reg_4160;
end if;
end if;
end process;
-- any_state_8_5_reg_8142 assign process. --
any_state_8_5_reg_8142_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and (ap_const_lv1_0 = end_0_phi_fu_5844_p32) and (tmp_37_fu_13557_p1 = ap_const_lv4_8))) then
any_state_8_5_reg_8142 <= ap_const_lv1_1;
elsif ((((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and (ap_const_lv1_0 = end_0_phi_fu_5844_p32)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and (ap_const_lv1_0 = end_0_phi_fu_5844_p32) and (tmp_37_fu_13557_p1 = ap_const_lv4_D)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and (ap_const_lv1_0 = end_0_phi_fu_5844_p32) and (tmp_37_fu_13557_p1 = ap_const_lv4_C)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and (ap_const_lv1_0 = end_0_phi_fu_5844_p32) and (tmp_37_fu_13557_p1 = ap_const_lv4_B)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and (ap_const_lv1_0 = end_0_phi_fu_5844_p32) and (tmp_37_fu_13557_p1 = ap_const_lv4_A)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and (ap_const_lv1_0 = end_0_phi_fu_5844_p32) and (tmp_37_fu_13557_p1 = ap_const_lv4_9)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and (ap_const_lv1_0 = end_0_phi_fu_5844_p32) and (tmp_37_fu_13557_p1 = ap_const_lv4_7)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and (ap_const_lv1_0 = end_0_phi_fu_5844_p32) and (tmp_37_fu_13557_p1 = ap_const_lv4_6)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and (ap_const_lv1_0 = end_0_phi_fu_5844_p32) and (tmp_37_fu_13557_p1 = ap_const_lv4_5)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and (ap_const_lv1_0 = end_0_phi_fu_5844_p32) and (tmp_37_fu_13557_p1 = ap_const_lv4_4)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and (ap_const_lv1_0 = end_0_phi_fu_5844_p32) and (tmp_37_fu_13557_p1 = ap_const_lv4_3)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and (ap_const_lv1_0 = end_0_phi_fu_5844_p32) and (tmp_37_fu_13557_p1 = ap_const_lv4_2)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and (ap_const_lv1_0 = end_0_phi_fu_5844_p32) and (tmp_37_fu_13557_p1 = ap_const_lv4_1)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and (ap_const_lv1_0 = end_0_phi_fu_5844_p32) and (tmp_37_fu_13557_p1 = ap_const_lv4_0)))) then
any_state_8_5_reg_8142 <= any_state_8_4_reg_5196;
end if;
end if;
end process;
-- any_state_8_6_reg_10053 assign process. --
any_state_8_6_reg_10053_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ST_st30_fsm_29 = ap_CS_fsm) and not((ap_const_lv1_0 = end_0_reg_5841)))) then
any_state_8_6_reg_10053 <= any_state_8_4_reg_5196;
elsif ((((ap_ST_st22_fsm_21 = ap_CS_fsm) and not((tmp_37_reg_14631 = ap_const_lv4_E)) and not((tmp_37_reg_14631 = ap_const_lv4_D)) and not((tmp_37_reg_14631 = ap_const_lv4_C)) and not((tmp_37_reg_14631 = ap_const_lv4_B)) and not((tmp_37_reg_14631 = ap_const_lv4_A)) and not((tmp_37_reg_14631 = ap_const_lv4_9)) and not((tmp_37_reg_14631 = ap_const_lv4_8)) and not((tmp_37_reg_14631 = ap_const_lv4_7)) and not((tmp_37_reg_14631 = ap_const_lv4_6)) and not((tmp_37_reg_14631 = ap_const_lv4_5)) and not((tmp_37_reg_14631 = ap_const_lv4_4)) and not((tmp_37_reg_14631 = ap_const_lv4_3)) and not((tmp_37_reg_14631 = ap_const_lv4_2)) and not((tmp_37_reg_14631 = ap_const_lv4_1)) and not((tmp_37_reg_14631 = ap_const_lv4_0))) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_E)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_D)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_C)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_B)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_A)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_9)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_8)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_7)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_6)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_5)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_4)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_3)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_2)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_1)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_0)))) then
any_state_8_6_reg_10053 <= any_state_8_5_reg_8142;
end if;
end if;
end process;
-- any_state_9_1_reg_1627 assign process. --
any_state_9_1_reg_1627_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_ST_st17_fsm_16 = ap_CS_fsm)) then
any_state_9_1_reg_1627 <= any_state_9_2_reg_3124;
elsif (((ap_ST_st7_fsm_6 = ap_CS_fsm) and (ap_const_lv1_0 = tmp_6_fu_13097_p2))) then
any_state_9_1_reg_1627 <= any_state_9_reg_1080;
end if;
end if;
end process;
-- any_state_9_2_reg_3124 assign process. --
any_state_9_2_reg_3124_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((tmp_36_reg_14538 = ap_const_lv4_9) and (ap_ST_st10_fsm_9 = ap_CS_fsm))) then
any_state_9_2_reg_3124 <= ap_const_lv1_0;
elsif (((ap_ST_st10_fsm_9 = ap_CS_fsm) or ((tmp_36_reg_14538 = ap_const_lv4_E) and (ap_ST_st10_fsm_9 = ap_CS_fsm)) or ((tmp_36_reg_14538 = ap_const_lv4_D) and (ap_ST_st10_fsm_9 = ap_CS_fsm)) or ((tmp_36_reg_14538 = ap_const_lv4_C) and (ap_ST_st10_fsm_9 = ap_CS_fsm)) or ((tmp_36_reg_14538 = ap_const_lv4_B) and (ap_ST_st10_fsm_9 = ap_CS_fsm)) or ((tmp_36_reg_14538 = ap_const_lv4_A) and (ap_ST_st10_fsm_9 = ap_CS_fsm)) or ((tmp_36_reg_14538 = ap_const_lv4_8) and (ap_ST_st10_fsm_9 = ap_CS_fsm)) or ((tmp_36_reg_14538 = ap_const_lv4_7) and (ap_ST_st10_fsm_9 = ap_CS_fsm)) or ((tmp_36_reg_14538 = ap_const_lv4_6) and (ap_ST_st10_fsm_9 = ap_CS_fsm)) or ((tmp_36_reg_14538 = ap_const_lv4_5) and (ap_ST_st10_fsm_9 = ap_CS_fsm)) or ((tmp_36_reg_14538 = ap_const_lv4_4) and (ap_ST_st10_fsm_9 = ap_CS_fsm)) or ((tmp_36_reg_14538 = ap_const_lv4_3) and (ap_ST_st10_fsm_9 = ap_CS_fsm)) or ((tmp_36_reg_14538 = ap_const_lv4_2) and (ap_ST_st10_fsm_9 = ap_CS_fsm)) or ((tmp_36_reg_14538 = ap_const_lv4_1) and (ap_ST_st10_fsm_9 = ap_CS_fsm)) or ((tmp_36_reg_14538 = ap_const_lv4_0) and (ap_ST_st10_fsm_9 = ap_CS_fsm)))) then
any_state_9_2_reg_3124 <= any_state_9_1_reg_1627;
end if;
end if;
end process;
-- any_state_9_3_reg_4149 assign process. --
any_state_9_3_reg_4149_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ST_st44_fsm_43 = ap_CS_fsm) and not((ap_const_lv1_0 = exitcond_fu_13718_p2)) and (ap_const_lv1_0 = all_end_phi_fu_12651_p36))) then
any_state_9_3_reg_4149 <= any_state_9_4_reg_5181;
elsif (((ap_ST_st8_fsm_7 = ap_CS_fsm) and not((exitcond2_fu_13247_p2 = ap_const_lv1_0)))) then
any_state_9_3_reg_4149 <= any_state_9_1_reg_1627;
end if;
end if;
end process;
-- any_state_9_4_reg_5181 assign process. --
any_state_9_4_reg_5181_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ST_st43_fsm_42 = ap_CS_fsm) or ((ap_ST_st32_fsm_31 = ap_CS_fsm) and ((not((ap_const_lv1_0 = end_load_3_phi_phi_fu_11584_p32)) and (ap_const_lv1_0 = brmerge_demorgan_reg_14680)) or (not((ap_const_lv1_0 = end_load_3_phi_phi_fu_11584_p32)) and not((ap_const_lv1_0 = tmp1_fu_13626_p2))))))) then
any_state_9_4_reg_5181 <= any_state_9_6_reg_9994;
elsif ((ap_ST_st18_fsm_17 = ap_CS_fsm)) then
any_state_9_4_reg_5181 <= any_state_9_3_reg_4149;
end if;
end if;
end process;
-- any_state_9_5_reg_8087 assign process. --
any_state_9_5_reg_8087_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and (ap_const_lv1_0 = end_0_phi_fu_5844_p32) and (tmp_37_fu_13557_p1 = ap_const_lv4_9))) then
any_state_9_5_reg_8087 <= ap_const_lv1_1;
elsif ((((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and (ap_const_lv1_0 = end_0_phi_fu_5844_p32)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and (ap_const_lv1_0 = end_0_phi_fu_5844_p32) and (tmp_37_fu_13557_p1 = ap_const_lv4_D)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and (ap_const_lv1_0 = end_0_phi_fu_5844_p32) and (tmp_37_fu_13557_p1 = ap_const_lv4_C)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and (ap_const_lv1_0 = end_0_phi_fu_5844_p32) and (tmp_37_fu_13557_p1 = ap_const_lv4_B)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and (ap_const_lv1_0 = end_0_phi_fu_5844_p32) and (tmp_37_fu_13557_p1 = ap_const_lv4_A)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and (ap_const_lv1_0 = end_0_phi_fu_5844_p32) and (tmp_37_fu_13557_p1 = ap_const_lv4_8)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and (ap_const_lv1_0 = end_0_phi_fu_5844_p32) and (tmp_37_fu_13557_p1 = ap_const_lv4_7)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and (ap_const_lv1_0 = end_0_phi_fu_5844_p32) and (tmp_37_fu_13557_p1 = ap_const_lv4_6)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and (ap_const_lv1_0 = end_0_phi_fu_5844_p32) and (tmp_37_fu_13557_p1 = ap_const_lv4_5)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and (ap_const_lv1_0 = end_0_phi_fu_5844_p32) and (tmp_37_fu_13557_p1 = ap_const_lv4_4)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and (ap_const_lv1_0 = end_0_phi_fu_5844_p32) and (tmp_37_fu_13557_p1 = ap_const_lv4_3)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and (ap_const_lv1_0 = end_0_phi_fu_5844_p32) and (tmp_37_fu_13557_p1 = ap_const_lv4_2)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and (ap_const_lv1_0 = end_0_phi_fu_5844_p32) and (tmp_37_fu_13557_p1 = ap_const_lv4_1)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and (ap_const_lv1_0 = end_0_phi_fu_5844_p32) and (tmp_37_fu_13557_p1 = ap_const_lv4_0)))) then
any_state_9_5_reg_8087 <= any_state_9_4_reg_5181;
end if;
end if;
end process;
-- any_state_9_6_reg_9994 assign process. --
any_state_9_6_reg_9994_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ST_st30_fsm_29 = ap_CS_fsm) and not((ap_const_lv1_0 = end_0_reg_5841)))) then
any_state_9_6_reg_9994 <= any_state_9_4_reg_5181;
elsif ((((ap_ST_st22_fsm_21 = ap_CS_fsm) and not((tmp_37_reg_14631 = ap_const_lv4_E)) and not((tmp_37_reg_14631 = ap_const_lv4_D)) and not((tmp_37_reg_14631 = ap_const_lv4_C)) and not((tmp_37_reg_14631 = ap_const_lv4_B)) and not((tmp_37_reg_14631 = ap_const_lv4_A)) and not((tmp_37_reg_14631 = ap_const_lv4_9)) and not((tmp_37_reg_14631 = ap_const_lv4_8)) and not((tmp_37_reg_14631 = ap_const_lv4_7)) and not((tmp_37_reg_14631 = ap_const_lv4_6)) and not((tmp_37_reg_14631 = ap_const_lv4_5)) and not((tmp_37_reg_14631 = ap_const_lv4_4)) and not((tmp_37_reg_14631 = ap_const_lv4_3)) and not((tmp_37_reg_14631 = ap_const_lv4_2)) and not((tmp_37_reg_14631 = ap_const_lv4_1)) and not((tmp_37_reg_14631 = ap_const_lv4_0))) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_E)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_D)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_C)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_B)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_A)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_9)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_8)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_7)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_6)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_5)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_4)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_3)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_2)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_1)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_0)))) then
any_state_9_6_reg_9994 <= any_state_9_5_reg_8087;
end if;
end if;
end process;
-- any_state_load_1_phi_reg_7703 assign process. --
any_state_load_1_phi_reg_7703_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_sig_bdd_1962) then
if ((tmp_37_fu_13557_p1 = ap_const_lv4_0)) then
any_state_load_1_phi_reg_7703 <= any_state_0_4_reg_5316;
elsif ((tmp_37_fu_13557_p1 = ap_const_lv4_E)) then
any_state_load_1_phi_reg_7703 <= any_state_14_4_reg_5106;
elsif ((tmp_37_fu_13557_p1 = ap_const_lv4_D)) then
any_state_load_1_phi_reg_7703 <= any_state_13_4_reg_5121;
elsif ((tmp_37_fu_13557_p1 = ap_const_lv4_C)) then
any_state_load_1_phi_reg_7703 <= any_state_12_4_reg_5136;
elsif ((tmp_37_fu_13557_p1 = ap_const_lv4_B)) then
any_state_load_1_phi_reg_7703 <= any_state_11_4_reg_5151;
elsif ((tmp_37_fu_13557_p1 = ap_const_lv4_A)) then
any_state_load_1_phi_reg_7703 <= any_state_10_4_reg_5166;
elsif ((tmp_37_fu_13557_p1 = ap_const_lv4_9)) then
any_state_load_1_phi_reg_7703 <= any_state_9_4_reg_5181;
elsif ((tmp_37_fu_13557_p1 = ap_const_lv4_8)) then
any_state_load_1_phi_reg_7703 <= any_state_8_4_reg_5196;
elsif ((tmp_37_fu_13557_p1 = ap_const_lv4_7)) then
any_state_load_1_phi_reg_7703 <= any_state_7_4_reg_5211;
elsif ((tmp_37_fu_13557_p1 = ap_const_lv4_6)) then
any_state_load_1_phi_reg_7703 <= any_state_6_4_reg_5226;
elsif ((tmp_37_fu_13557_p1 = ap_const_lv4_5)) then
any_state_load_1_phi_reg_7703 <= any_state_5_4_reg_5241;
elsif ((tmp_37_fu_13557_p1 = ap_const_lv4_4)) then
any_state_load_1_phi_reg_7703 <= any_state_4_4_reg_5256;
elsif ((tmp_37_fu_13557_p1 = ap_const_lv4_3)) then
any_state_load_1_phi_reg_7703 <= any_state_3_4_reg_5271;
elsif ((tmp_37_fu_13557_p1 = ap_const_lv4_2)) then
any_state_load_1_phi_reg_7703 <= any_state_2_4_reg_5286;
elsif ((tmp_37_fu_13557_p1 = ap_const_lv4_1)) then
any_state_load_1_phi_reg_7703 <= any_state_1_4_reg_5301;
elsif ((ap_true = ap_true)) then
any_state_load_1_phi_reg_7703 <= any_state_15_4_reg_5091;
end if;
end if;
end if;
end process;
-- bus_assign_reg_3684 assign process. --
bus_assign_reg_3684_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_ST_st12_fsm_11 = ap_CS_fsm)) then
if (ap_sig_bdd_1202) then
bus_assign_reg_3684 <= current_buckets_q0(63 downto 32);
elsif ((ap_const_lv1_0 = tmp_11_fu_13276_p2)) then
bus_assign_reg_3684 <= tmp_39_fu_13272_p1;
end if;
end if;
end if;
end process;
-- end_0_1_reg_4072 assign process. --
end_0_1_reg_4072_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ST_st44_fsm_43 = ap_CS_fsm) and not((ap_const_lv1_0 = exitcond_fu_13718_p2)) and (ap_const_lv1_0 = all_end_phi_fu_12651_p36))) then
end_0_1_reg_4072 <= end_0_2_reg_5076;
elsif (((ap_ST_st8_fsm_7 = ap_CS_fsm) and not((exitcond2_fu_13247_p2 = ap_const_lv1_0)))) then
end_0_1_reg_4072 <= end_0_s_reg_996;
end if;
end if;
end process;
-- end_0_2_reg_5076 assign process. --
end_0_2_reg_5076_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ST_st43_fsm_42 = ap_CS_fsm) or ((ap_ST_st32_fsm_31 = ap_CS_fsm) and ((not((ap_const_lv1_0 = end_load_3_phi_phi_fu_11584_p32)) and (ap_const_lv1_0 = brmerge_demorgan_reg_14680)) or (not((ap_const_lv1_0 = end_load_3_phi_phi_fu_11584_p32)) and not((ap_const_lv1_0 = tmp1_fu_13626_p2))))))) then
end_0_2_reg_5076 <= end_0_3_reg_6719;
elsif ((ap_ST_st18_fsm_17 = ap_CS_fsm)) then
end_0_2_reg_5076 <= end_0_1_reg_4072;
end if;
end if;
end process;
-- end_0_3_reg_6719 assign process. --
end_0_3_reg_6719_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and (tmp_37_fu_13557_p1 = ap_const_lv4_0))) then
end_0_3_reg_6719 <= end_0_phi_fu_5844_p32;
elsif ((((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2))) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and (tmp_37_fu_13557_p1 = ap_const_lv4_1)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and (tmp_37_fu_13557_p1 = ap_const_lv4_2)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and (tmp_37_fu_13557_p1 = ap_const_lv4_3)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and (tmp_37_fu_13557_p1 = ap_const_lv4_4)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and (tmp_37_fu_13557_p1 = ap_const_lv4_5)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and (tmp_37_fu_13557_p1 = ap_const_lv4_6)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and (tmp_37_fu_13557_p1 = ap_const_lv4_7)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and (tmp_37_fu_13557_p1 = ap_const_lv4_8)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and (tmp_37_fu_13557_p1 = ap_const_lv4_9)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and (tmp_37_fu_13557_p1 = ap_const_lv4_A)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and (tmp_37_fu_13557_p1 = ap_const_lv4_B)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and (tmp_37_fu_13557_p1 = ap_const_lv4_C)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and (tmp_37_fu_13557_p1 = ap_const_lv4_D)))) then
end_0_3_reg_6719 <= end_0_2_reg_5076;
end if;
end if;
end process;
-- end_0_reg_5841 assign process. --
end_0_reg_5841_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_sig_bdd_327) then
if ((tmp_37_fu_13557_p1 = ap_const_lv4_0)) then
end_0_reg_5841 <= j_15_end_load_reg_14439;
elsif ((tmp_37_fu_13557_p1 = ap_const_lv4_E)) then
end_0_reg_5841 <= j_15_end_14_load_reg_14509;
elsif ((tmp_37_fu_13557_p1 = ap_const_lv4_D)) then
end_0_reg_5841 <= j_15_end_13_load_reg_14504;
elsif ((tmp_37_fu_13557_p1 = ap_const_lv4_C)) then
end_0_reg_5841 <= j_15_end_12_load_reg_14499;
elsif ((tmp_37_fu_13557_p1 = ap_const_lv4_B)) then
end_0_reg_5841 <= j_15_end_11_load_reg_14494;
elsif ((tmp_37_fu_13557_p1 = ap_const_lv4_A)) then
end_0_reg_5841 <= j_15_end_10_load_reg_14489;
elsif ((tmp_37_fu_13557_p1 = ap_const_lv4_9)) then
end_0_reg_5841 <= j_15_end_9_load_reg_14484;
elsif ((tmp_37_fu_13557_p1 = ap_const_lv4_8)) then
end_0_reg_5841 <= j_15_end_8_load_reg_14479;
elsif ((tmp_37_fu_13557_p1 = ap_const_lv4_7)) then
end_0_reg_5841 <= j_15_end_7_load_reg_14474;
elsif ((tmp_37_fu_13557_p1 = ap_const_lv4_6)) then
end_0_reg_5841 <= j_15_end_6_load_reg_14469;
elsif ((tmp_37_fu_13557_p1 = ap_const_lv4_5)) then
end_0_reg_5841 <= j_15_end_5_load_reg_14464;
elsif ((tmp_37_fu_13557_p1 = ap_const_lv4_4)) then
end_0_reg_5841 <= j_15_end_4_load_reg_14459;
elsif ((tmp_37_fu_13557_p1 = ap_const_lv4_3)) then
end_0_reg_5841 <= j_15_end_3_load_reg_14454;
elsif ((tmp_37_fu_13557_p1 = ap_const_lv4_2)) then
end_0_reg_5841 <= j_15_end_2_load_reg_14449;
elsif ((tmp_37_fu_13557_p1 = ap_const_lv4_1)) then
end_0_reg_5841 <= j_15_end_1_load_reg_14444;
elsif ((ap_true = ap_true)) then
end_0_reg_5841 <= j_15_end_15_load_reg_14514;
end if;
end if;
end if;
end process;
-- end_10_1_reg_3962 assign process. --
end_10_1_reg_3962_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ST_st44_fsm_43 = ap_CS_fsm) and not((ap_const_lv1_0 = exitcond_fu_13718_p2)) and (ap_const_lv1_0 = all_end_phi_fu_12651_p36))) then
end_10_1_reg_3962 <= end_10_2_reg_4926;
elsif (((ap_ST_st8_fsm_7 = ap_CS_fsm) and not((exitcond2_fu_13247_p2 = ap_const_lv1_0)))) then
end_10_1_reg_3962 <= end_10_s_reg_876;
end if;
end if;
end process;
-- end_10_2_reg_4926 assign process. --
end_10_2_reg_4926_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ST_st43_fsm_42 = ap_CS_fsm) or ((ap_ST_st32_fsm_31 = ap_CS_fsm) and ((not((ap_const_lv1_0 = end_load_3_phi_phi_fu_11584_p32)) and (ap_const_lv1_0 = brmerge_demorgan_reg_14680)) or (not((ap_const_lv1_0 = end_load_3_phi_phi_fu_11584_p32)) and not((ap_const_lv1_0 = tmp1_fu_13626_p2))))))) then
end_10_2_reg_4926 <= end_10_3_reg_6159;
elsif ((ap_ST_st18_fsm_17 = ap_CS_fsm)) then
end_10_2_reg_4926 <= end_10_1_reg_3962;
end if;
end if;
end process;
-- end_10_3_reg_6159 assign process. --
end_10_3_reg_6159_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and (tmp_37_fu_13557_p1 = ap_const_lv4_A))) then
end_10_3_reg_6159 <= end_0_phi_fu_5844_p32;
elsif ((((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2))) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and (tmp_37_fu_13557_p1 = ap_const_lv4_1)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and (tmp_37_fu_13557_p1 = ap_const_lv4_2)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and (tmp_37_fu_13557_p1 = ap_const_lv4_3)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and (tmp_37_fu_13557_p1 = ap_const_lv4_4)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and (tmp_37_fu_13557_p1 = ap_const_lv4_5)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and (tmp_37_fu_13557_p1 = ap_const_lv4_6)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and (tmp_37_fu_13557_p1 = ap_const_lv4_7)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and (tmp_37_fu_13557_p1 = ap_const_lv4_8)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and (tmp_37_fu_13557_p1 = ap_const_lv4_9)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and (tmp_37_fu_13557_p1 = ap_const_lv4_B)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and (tmp_37_fu_13557_p1 = ap_const_lv4_C)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and (tmp_37_fu_13557_p1 = ap_const_lv4_D)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and (tmp_37_fu_13557_p1 = ap_const_lv4_0)))) then
end_10_3_reg_6159 <= end_10_2_reg_4926;
end if;
end if;
end process;
-- end_11_1_reg_3951 assign process. --
end_11_1_reg_3951_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ST_st44_fsm_43 = ap_CS_fsm) and not((ap_const_lv1_0 = exitcond_fu_13718_p2)) and (ap_const_lv1_0 = all_end_phi_fu_12651_p36))) then
end_11_1_reg_3951 <= end_11_2_reg_4911;
elsif (((ap_ST_st8_fsm_7 = ap_CS_fsm) and not((exitcond2_fu_13247_p2 = ap_const_lv1_0)))) then
end_11_1_reg_3951 <= end_11_s_reg_864;
end if;
end if;
end process;
-- end_11_2_reg_4911 assign process. --
end_11_2_reg_4911_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ST_st43_fsm_42 = ap_CS_fsm) or ((ap_ST_st32_fsm_31 = ap_CS_fsm) and ((not((ap_const_lv1_0 = end_load_3_phi_phi_fu_11584_p32)) and (ap_const_lv1_0 = brmerge_demorgan_reg_14680)) or (not((ap_const_lv1_0 = end_load_3_phi_phi_fu_11584_p32)) and not((ap_const_lv1_0 = tmp1_fu_13626_p2))))))) then
end_11_2_reg_4911 <= end_11_3_reg_6103;
elsif ((ap_ST_st18_fsm_17 = ap_CS_fsm)) then
end_11_2_reg_4911 <= end_11_1_reg_3951;
end if;
end if;
end process;
-- end_11_3_reg_6103 assign process. --
end_11_3_reg_6103_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and (tmp_37_fu_13557_p1 = ap_const_lv4_B))) then
end_11_3_reg_6103 <= end_0_phi_fu_5844_p32;
elsif ((((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2))) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and (tmp_37_fu_13557_p1 = ap_const_lv4_1)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and (tmp_37_fu_13557_p1 = ap_const_lv4_2)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and (tmp_37_fu_13557_p1 = ap_const_lv4_3)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and (tmp_37_fu_13557_p1 = ap_const_lv4_4)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and (tmp_37_fu_13557_p1 = ap_const_lv4_5)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and (tmp_37_fu_13557_p1 = ap_const_lv4_6)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and (tmp_37_fu_13557_p1 = ap_const_lv4_7)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and (tmp_37_fu_13557_p1 = ap_const_lv4_8)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and (tmp_37_fu_13557_p1 = ap_const_lv4_9)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and (tmp_37_fu_13557_p1 = ap_const_lv4_A)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and (tmp_37_fu_13557_p1 = ap_const_lv4_C)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and (tmp_37_fu_13557_p1 = ap_const_lv4_D)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and (tmp_37_fu_13557_p1 = ap_const_lv4_0)))) then
end_11_3_reg_6103 <= end_11_2_reg_4911;
end if;
end if;
end process;
-- end_12_1_reg_3940 assign process. --
end_12_1_reg_3940_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ST_st44_fsm_43 = ap_CS_fsm) and not((ap_const_lv1_0 = exitcond_fu_13718_p2)) and (ap_const_lv1_0 = all_end_phi_fu_12651_p36))) then
end_12_1_reg_3940 <= end_12_2_reg_4896;
elsif (((ap_ST_st8_fsm_7 = ap_CS_fsm) and not((exitcond2_fu_13247_p2 = ap_const_lv1_0)))) then
end_12_1_reg_3940 <= end_12_s_reg_852;
end if;
end if;
end process;
-- end_12_2_reg_4896 assign process. --
end_12_2_reg_4896_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ST_st43_fsm_42 = ap_CS_fsm) or ((ap_ST_st32_fsm_31 = ap_CS_fsm) and ((not((ap_const_lv1_0 = end_load_3_phi_phi_fu_11584_p32)) and (ap_const_lv1_0 = brmerge_demorgan_reg_14680)) or (not((ap_const_lv1_0 = end_load_3_phi_phi_fu_11584_p32)) and not((ap_const_lv1_0 = tmp1_fu_13626_p2))))))) then
end_12_2_reg_4896 <= end_12_3_reg_6047;
elsif ((ap_ST_st18_fsm_17 = ap_CS_fsm)) then
end_12_2_reg_4896 <= end_12_1_reg_3940;
end if;
end if;
end process;
-- end_12_3_reg_6047 assign process. --
end_12_3_reg_6047_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and (tmp_37_fu_13557_p1 = ap_const_lv4_C))) then
end_12_3_reg_6047 <= end_0_phi_fu_5844_p32;
elsif ((((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2))) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and (tmp_37_fu_13557_p1 = ap_const_lv4_1)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and (tmp_37_fu_13557_p1 = ap_const_lv4_2)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and (tmp_37_fu_13557_p1 = ap_const_lv4_3)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and (tmp_37_fu_13557_p1 = ap_const_lv4_4)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and (tmp_37_fu_13557_p1 = ap_const_lv4_5)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and (tmp_37_fu_13557_p1 = ap_const_lv4_6)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and (tmp_37_fu_13557_p1 = ap_const_lv4_7)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and (tmp_37_fu_13557_p1 = ap_const_lv4_8)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and (tmp_37_fu_13557_p1 = ap_const_lv4_9)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and (tmp_37_fu_13557_p1 = ap_const_lv4_A)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and (tmp_37_fu_13557_p1 = ap_const_lv4_B)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and (tmp_37_fu_13557_p1 = ap_const_lv4_D)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and (tmp_37_fu_13557_p1 = ap_const_lv4_0)))) then
end_12_3_reg_6047 <= end_12_2_reg_4896;
end if;
end if;
end process;
-- end_13_1_reg_3929 assign process. --
end_13_1_reg_3929_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ST_st44_fsm_43 = ap_CS_fsm) and not((ap_const_lv1_0 = exitcond_fu_13718_p2)) and (ap_const_lv1_0 = all_end_phi_fu_12651_p36))) then
end_13_1_reg_3929 <= end_13_2_reg_4881;
elsif (((ap_ST_st8_fsm_7 = ap_CS_fsm) and not((exitcond2_fu_13247_p2 = ap_const_lv1_0)))) then
end_13_1_reg_3929 <= end_13_s_reg_840;
end if;
end if;
end process;
-- end_13_2_reg_4881 assign process. --
end_13_2_reg_4881_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ST_st43_fsm_42 = ap_CS_fsm) or ((ap_ST_st32_fsm_31 = ap_CS_fsm) and ((not((ap_const_lv1_0 = end_load_3_phi_phi_fu_11584_p32)) and (ap_const_lv1_0 = brmerge_demorgan_reg_14680)) or (not((ap_const_lv1_0 = end_load_3_phi_phi_fu_11584_p32)) and not((ap_const_lv1_0 = tmp1_fu_13626_p2))))))) then
end_13_2_reg_4881 <= end_13_3_reg_5991;
elsif ((ap_ST_st18_fsm_17 = ap_CS_fsm)) then
end_13_2_reg_4881 <= end_13_1_reg_3929;
end if;
end if;
end process;
-- end_13_3_reg_5991 assign process. --
end_13_3_reg_5991_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and (tmp_37_fu_13557_p1 = ap_const_lv4_D))) then
end_13_3_reg_5991 <= end_0_phi_fu_5844_p32;
elsif ((((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2))) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and (tmp_37_fu_13557_p1 = ap_const_lv4_1)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and (tmp_37_fu_13557_p1 = ap_const_lv4_2)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and (tmp_37_fu_13557_p1 = ap_const_lv4_3)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and (tmp_37_fu_13557_p1 = ap_const_lv4_4)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and (tmp_37_fu_13557_p1 = ap_const_lv4_5)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and (tmp_37_fu_13557_p1 = ap_const_lv4_6)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and (tmp_37_fu_13557_p1 = ap_const_lv4_7)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and (tmp_37_fu_13557_p1 = ap_const_lv4_8)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and (tmp_37_fu_13557_p1 = ap_const_lv4_9)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and (tmp_37_fu_13557_p1 = ap_const_lv4_A)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and (tmp_37_fu_13557_p1 = ap_const_lv4_B)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and (tmp_37_fu_13557_p1 = ap_const_lv4_C)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and (tmp_37_fu_13557_p1 = ap_const_lv4_0)))) then
end_13_3_reg_5991 <= end_13_2_reg_4881;
end if;
end if;
end process;
-- end_14_1_reg_3918 assign process. --
end_14_1_reg_3918_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ST_st44_fsm_43 = ap_CS_fsm) and not((ap_const_lv1_0 = exitcond_fu_13718_p2)) and (ap_const_lv1_0 = all_end_phi_fu_12651_p36))) then
end_14_1_reg_3918 <= end_14_2_reg_4866;
elsif (((ap_ST_st8_fsm_7 = ap_CS_fsm) and not((exitcond2_fu_13247_p2 = ap_const_lv1_0)))) then
end_14_1_reg_3918 <= end_14_s_reg_828;
end if;
end if;
end process;
-- end_14_2_reg_4866 assign process. --
end_14_2_reg_4866_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ST_st43_fsm_42 = ap_CS_fsm) or ((ap_ST_st32_fsm_31 = ap_CS_fsm) and ((not((ap_const_lv1_0 = end_load_3_phi_phi_fu_11584_p32)) and (ap_const_lv1_0 = brmerge_demorgan_reg_14680)) or (not((ap_const_lv1_0 = end_load_3_phi_phi_fu_11584_p32)) and not((ap_const_lv1_0 = tmp1_fu_13626_p2))))))) then
end_14_2_reg_4866 <= end_14_3_reg_5935;
elsif ((ap_ST_st18_fsm_17 = ap_CS_fsm)) then
end_14_2_reg_4866 <= end_14_1_reg_3918;
end if;
end if;
end process;
-- end_14_3_reg_5935 assign process. --
end_14_3_reg_5935_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and (tmp_37_fu_13557_p1 = ap_const_lv4_E))) then
end_14_3_reg_5935 <= end_0_phi_fu_5844_p32;
elsif ((((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2))) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and (tmp_37_fu_13557_p1 = ap_const_lv4_1)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and (tmp_37_fu_13557_p1 = ap_const_lv4_2)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and (tmp_37_fu_13557_p1 = ap_const_lv4_3)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and (tmp_37_fu_13557_p1 = ap_const_lv4_4)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and (tmp_37_fu_13557_p1 = ap_const_lv4_5)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and (tmp_37_fu_13557_p1 = ap_const_lv4_6)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and (tmp_37_fu_13557_p1 = ap_const_lv4_7)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and (tmp_37_fu_13557_p1 = ap_const_lv4_8)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and (tmp_37_fu_13557_p1 = ap_const_lv4_9)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and (tmp_37_fu_13557_p1 = ap_const_lv4_A)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and (tmp_37_fu_13557_p1 = ap_const_lv4_B)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and (tmp_37_fu_13557_p1 = ap_const_lv4_C)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and (tmp_37_fu_13557_p1 = ap_const_lv4_0)))) then
end_14_3_reg_5935 <= end_14_2_reg_4866;
end if;
end if;
end process;
-- end_15_1_reg_3907 assign process. --
end_15_1_reg_3907_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ST_st44_fsm_43 = ap_CS_fsm) and not((ap_const_lv1_0 = exitcond_fu_13718_p2)) and (ap_const_lv1_0 = all_end_phi_fu_12651_p36))) then
end_15_1_reg_3907 <= end_15_2_reg_4851;
elsif (((ap_ST_st8_fsm_7 = ap_CS_fsm) and not((exitcond2_fu_13247_p2 = ap_const_lv1_0)))) then
end_15_1_reg_3907 <= end_15_s_reg_816;
end if;
end if;
end process;
-- end_15_2_reg_4851 assign process. --
end_15_2_reg_4851_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ST_st43_fsm_42 = ap_CS_fsm) or ((ap_ST_st32_fsm_31 = ap_CS_fsm) and ((not((ap_const_lv1_0 = end_load_3_phi_phi_fu_11584_p32)) and (ap_const_lv1_0 = brmerge_demorgan_reg_14680)) or (not((ap_const_lv1_0 = end_load_3_phi_phi_fu_11584_p32)) and not((ap_const_lv1_0 = tmp1_fu_13626_p2))))))) then
end_15_2_reg_4851 <= end_15_3_reg_5879;
elsif ((ap_ST_st18_fsm_17 = ap_CS_fsm)) then
end_15_2_reg_4851 <= end_15_1_reg_3907;
end if;
end if;
end process;
-- end_15_3_reg_5879 assign process. --
end_15_3_reg_5879_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and (tmp_37_fu_13557_p1 = ap_const_lv4_1)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and (tmp_37_fu_13557_p1 = ap_const_lv4_2)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and (tmp_37_fu_13557_p1 = ap_const_lv4_3)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and (tmp_37_fu_13557_p1 = ap_const_lv4_4)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and (tmp_37_fu_13557_p1 = ap_const_lv4_5)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and (tmp_37_fu_13557_p1 = ap_const_lv4_6)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and (tmp_37_fu_13557_p1 = ap_const_lv4_7)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and (tmp_37_fu_13557_p1 = ap_const_lv4_8)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and (tmp_37_fu_13557_p1 = ap_const_lv4_9)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and (tmp_37_fu_13557_p1 = ap_const_lv4_A)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and (tmp_37_fu_13557_p1 = ap_const_lv4_B)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and (tmp_37_fu_13557_p1 = ap_const_lv4_C)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and (tmp_37_fu_13557_p1 = ap_const_lv4_D)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and (tmp_37_fu_13557_p1 = ap_const_lv4_E)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and (tmp_37_fu_13557_p1 = ap_const_lv4_0)))) then
end_15_3_reg_5879 <= end_15_2_reg_4851;
elsif (((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)))) then
end_15_3_reg_5879 <= end_0_phi_fu_5844_p32;
end if;
end if;
end process;
-- end_1_1_reg_4061 assign process. --
end_1_1_reg_4061_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ST_st44_fsm_43 = ap_CS_fsm) and not((ap_const_lv1_0 = exitcond_fu_13718_p2)) and (ap_const_lv1_0 = all_end_phi_fu_12651_p36))) then
end_1_1_reg_4061 <= end_1_2_reg_5061;
elsif (((ap_ST_st8_fsm_7 = ap_CS_fsm) and not((exitcond2_fu_13247_p2 = ap_const_lv1_0)))) then
end_1_1_reg_4061 <= end_1_s_reg_984;
end if;
end if;
end process;
-- end_1_2_reg_5061 assign process. --
end_1_2_reg_5061_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ST_st43_fsm_42 = ap_CS_fsm) or ((ap_ST_st32_fsm_31 = ap_CS_fsm) and ((not((ap_const_lv1_0 = end_load_3_phi_phi_fu_11584_p32)) and (ap_const_lv1_0 = brmerge_demorgan_reg_14680)) or (not((ap_const_lv1_0 = end_load_3_phi_phi_fu_11584_p32)) and not((ap_const_lv1_0 = tmp1_fu_13626_p2))))))) then
end_1_2_reg_5061 <= end_1_3_reg_6663;
elsif ((ap_ST_st18_fsm_17 = ap_CS_fsm)) then
end_1_2_reg_5061 <= end_1_1_reg_4061;
end if;
end if;
end process;
-- end_1_3_reg_6663 assign process. --
end_1_3_reg_6663_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and (tmp_37_fu_13557_p1 = ap_const_lv4_1))) then
end_1_3_reg_6663 <= end_0_phi_fu_5844_p32;
elsif ((((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2))) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and (tmp_37_fu_13557_p1 = ap_const_lv4_2)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and (tmp_37_fu_13557_p1 = ap_const_lv4_3)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and (tmp_37_fu_13557_p1 = ap_const_lv4_4)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and (tmp_37_fu_13557_p1 = ap_const_lv4_5)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and (tmp_37_fu_13557_p1 = ap_const_lv4_6)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and (tmp_37_fu_13557_p1 = ap_const_lv4_7)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and (tmp_37_fu_13557_p1 = ap_const_lv4_8)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and (tmp_37_fu_13557_p1 = ap_const_lv4_9)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and (tmp_37_fu_13557_p1 = ap_const_lv4_A)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and (tmp_37_fu_13557_p1 = ap_const_lv4_B)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and (tmp_37_fu_13557_p1 = ap_const_lv4_C)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and (tmp_37_fu_13557_p1 = ap_const_lv4_D)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and (tmp_37_fu_13557_p1 = ap_const_lv4_0)))) then
end_1_3_reg_6663 <= end_1_2_reg_5061;
end if;
end if;
end process;
-- end_2_1_reg_4050 assign process. --
end_2_1_reg_4050_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ST_st44_fsm_43 = ap_CS_fsm) and not((ap_const_lv1_0 = exitcond_fu_13718_p2)) and (ap_const_lv1_0 = all_end_phi_fu_12651_p36))) then
end_2_1_reg_4050 <= end_2_2_reg_5046;
elsif (((ap_ST_st8_fsm_7 = ap_CS_fsm) and not((exitcond2_fu_13247_p2 = ap_const_lv1_0)))) then
end_2_1_reg_4050 <= end_2_s_reg_972;
end if;
end if;
end process;
-- end_2_2_reg_5046 assign process. --
end_2_2_reg_5046_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ST_st43_fsm_42 = ap_CS_fsm) or ((ap_ST_st32_fsm_31 = ap_CS_fsm) and ((not((ap_const_lv1_0 = end_load_3_phi_phi_fu_11584_p32)) and (ap_const_lv1_0 = brmerge_demorgan_reg_14680)) or (not((ap_const_lv1_0 = end_load_3_phi_phi_fu_11584_p32)) and not((ap_const_lv1_0 = tmp1_fu_13626_p2))))))) then
end_2_2_reg_5046 <= end_2_3_reg_6607;
elsif ((ap_ST_st18_fsm_17 = ap_CS_fsm)) then
end_2_2_reg_5046 <= end_2_1_reg_4050;
end if;
end if;
end process;
-- end_2_3_reg_6607 assign process. --
end_2_3_reg_6607_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and (tmp_37_fu_13557_p1 = ap_const_lv4_2))) then
end_2_3_reg_6607 <= end_0_phi_fu_5844_p32;
elsif ((((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2))) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and (tmp_37_fu_13557_p1 = ap_const_lv4_1)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and (tmp_37_fu_13557_p1 = ap_const_lv4_3)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and (tmp_37_fu_13557_p1 = ap_const_lv4_4)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and (tmp_37_fu_13557_p1 = ap_const_lv4_5)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and (tmp_37_fu_13557_p1 = ap_const_lv4_6)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and (tmp_37_fu_13557_p1 = ap_const_lv4_7)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and (tmp_37_fu_13557_p1 = ap_const_lv4_8)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and (tmp_37_fu_13557_p1 = ap_const_lv4_9)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and (tmp_37_fu_13557_p1 = ap_const_lv4_A)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and (tmp_37_fu_13557_p1 = ap_const_lv4_B)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and (tmp_37_fu_13557_p1 = ap_const_lv4_C)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and (tmp_37_fu_13557_p1 = ap_const_lv4_D)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and (tmp_37_fu_13557_p1 = ap_const_lv4_0)))) then
end_2_3_reg_6607 <= end_2_2_reg_5046;
end if;
end if;
end process;
-- end_3_1_reg_4039 assign process. --
end_3_1_reg_4039_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ST_st44_fsm_43 = ap_CS_fsm) and not((ap_const_lv1_0 = exitcond_fu_13718_p2)) and (ap_const_lv1_0 = all_end_phi_fu_12651_p36))) then
end_3_1_reg_4039 <= end_3_2_reg_5031;
elsif (((ap_ST_st8_fsm_7 = ap_CS_fsm) and not((exitcond2_fu_13247_p2 = ap_const_lv1_0)))) then
end_3_1_reg_4039 <= end_3_s_reg_960;
end if;
end if;
end process;
-- end_3_2_reg_5031 assign process. --
end_3_2_reg_5031_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ST_st43_fsm_42 = ap_CS_fsm) or ((ap_ST_st32_fsm_31 = ap_CS_fsm) and ((not((ap_const_lv1_0 = end_load_3_phi_phi_fu_11584_p32)) and (ap_const_lv1_0 = brmerge_demorgan_reg_14680)) or (not((ap_const_lv1_0 = end_load_3_phi_phi_fu_11584_p32)) and not((ap_const_lv1_0 = tmp1_fu_13626_p2))))))) then
end_3_2_reg_5031 <= end_3_3_reg_6551;
elsif ((ap_ST_st18_fsm_17 = ap_CS_fsm)) then
end_3_2_reg_5031 <= end_3_1_reg_4039;
end if;
end if;
end process;
-- end_3_3_reg_6551 assign process. --
end_3_3_reg_6551_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and (tmp_37_fu_13557_p1 = ap_const_lv4_3))) then
end_3_3_reg_6551 <= end_0_phi_fu_5844_p32;
elsif ((((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2))) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and (tmp_37_fu_13557_p1 = ap_const_lv4_1)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and (tmp_37_fu_13557_p1 = ap_const_lv4_2)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and (tmp_37_fu_13557_p1 = ap_const_lv4_4)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and (tmp_37_fu_13557_p1 = ap_const_lv4_5)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and (tmp_37_fu_13557_p1 = ap_const_lv4_6)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and (tmp_37_fu_13557_p1 = ap_const_lv4_7)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and (tmp_37_fu_13557_p1 = ap_const_lv4_8)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and (tmp_37_fu_13557_p1 = ap_const_lv4_9)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and (tmp_37_fu_13557_p1 = ap_const_lv4_A)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and (tmp_37_fu_13557_p1 = ap_const_lv4_B)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and (tmp_37_fu_13557_p1 = ap_const_lv4_C)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and (tmp_37_fu_13557_p1 = ap_const_lv4_D)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and (tmp_37_fu_13557_p1 = ap_const_lv4_0)))) then
end_3_3_reg_6551 <= end_3_2_reg_5031;
end if;
end if;
end process;
-- end_4_1_reg_4028 assign process. --
end_4_1_reg_4028_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ST_st44_fsm_43 = ap_CS_fsm) and not((ap_const_lv1_0 = exitcond_fu_13718_p2)) and (ap_const_lv1_0 = all_end_phi_fu_12651_p36))) then
end_4_1_reg_4028 <= end_4_2_reg_5016;
elsif (((ap_ST_st8_fsm_7 = ap_CS_fsm) and not((exitcond2_fu_13247_p2 = ap_const_lv1_0)))) then
end_4_1_reg_4028 <= end_4_s_reg_948;
end if;
end if;
end process;
-- end_4_2_reg_5016 assign process. --
end_4_2_reg_5016_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ST_st43_fsm_42 = ap_CS_fsm) or ((ap_ST_st32_fsm_31 = ap_CS_fsm) and ((not((ap_const_lv1_0 = end_load_3_phi_phi_fu_11584_p32)) and (ap_const_lv1_0 = brmerge_demorgan_reg_14680)) or (not((ap_const_lv1_0 = end_load_3_phi_phi_fu_11584_p32)) and not((ap_const_lv1_0 = tmp1_fu_13626_p2))))))) then
end_4_2_reg_5016 <= end_4_3_reg_6495;
elsif ((ap_ST_st18_fsm_17 = ap_CS_fsm)) then
end_4_2_reg_5016 <= end_4_1_reg_4028;
end if;
end if;
end process;
-- end_4_3_reg_6495 assign process. --
end_4_3_reg_6495_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and (tmp_37_fu_13557_p1 = ap_const_lv4_4))) then
end_4_3_reg_6495 <= end_0_phi_fu_5844_p32;
elsif ((((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2))) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and (tmp_37_fu_13557_p1 = ap_const_lv4_1)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and (tmp_37_fu_13557_p1 = ap_const_lv4_2)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and (tmp_37_fu_13557_p1 = ap_const_lv4_3)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and (tmp_37_fu_13557_p1 = ap_const_lv4_5)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and (tmp_37_fu_13557_p1 = ap_const_lv4_6)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and (tmp_37_fu_13557_p1 = ap_const_lv4_7)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and (tmp_37_fu_13557_p1 = ap_const_lv4_8)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and (tmp_37_fu_13557_p1 = ap_const_lv4_9)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and (tmp_37_fu_13557_p1 = ap_const_lv4_A)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and (tmp_37_fu_13557_p1 = ap_const_lv4_B)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and (tmp_37_fu_13557_p1 = ap_const_lv4_C)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and (tmp_37_fu_13557_p1 = ap_const_lv4_D)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and (tmp_37_fu_13557_p1 = ap_const_lv4_0)))) then
end_4_3_reg_6495 <= end_4_2_reg_5016;
end if;
end if;
end process;
-- end_5_1_reg_4017 assign process. --
end_5_1_reg_4017_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ST_st44_fsm_43 = ap_CS_fsm) and not((ap_const_lv1_0 = exitcond_fu_13718_p2)) and (ap_const_lv1_0 = all_end_phi_fu_12651_p36))) then
end_5_1_reg_4017 <= end_5_2_reg_5001;
elsif (((ap_ST_st8_fsm_7 = ap_CS_fsm) and not((exitcond2_fu_13247_p2 = ap_const_lv1_0)))) then
end_5_1_reg_4017 <= end_5_s_reg_936;
end if;
end if;
end process;
-- end_5_2_reg_5001 assign process. --
end_5_2_reg_5001_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ST_st43_fsm_42 = ap_CS_fsm) or ((ap_ST_st32_fsm_31 = ap_CS_fsm) and ((not((ap_const_lv1_0 = end_load_3_phi_phi_fu_11584_p32)) and (ap_const_lv1_0 = brmerge_demorgan_reg_14680)) or (not((ap_const_lv1_0 = end_load_3_phi_phi_fu_11584_p32)) and not((ap_const_lv1_0 = tmp1_fu_13626_p2))))))) then
end_5_2_reg_5001 <= end_5_3_reg_6439;
elsif ((ap_ST_st18_fsm_17 = ap_CS_fsm)) then
end_5_2_reg_5001 <= end_5_1_reg_4017;
end if;
end if;
end process;
-- end_5_3_reg_6439 assign process. --
end_5_3_reg_6439_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and (tmp_37_fu_13557_p1 = ap_const_lv4_5))) then
end_5_3_reg_6439 <= end_0_phi_fu_5844_p32;
elsif ((((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2))) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and (tmp_37_fu_13557_p1 = ap_const_lv4_1)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and (tmp_37_fu_13557_p1 = ap_const_lv4_2)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and (tmp_37_fu_13557_p1 = ap_const_lv4_3)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and (tmp_37_fu_13557_p1 = ap_const_lv4_4)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and (tmp_37_fu_13557_p1 = ap_const_lv4_6)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and (tmp_37_fu_13557_p1 = ap_const_lv4_7)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and (tmp_37_fu_13557_p1 = ap_const_lv4_8)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and (tmp_37_fu_13557_p1 = ap_const_lv4_9)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and (tmp_37_fu_13557_p1 = ap_const_lv4_A)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and (tmp_37_fu_13557_p1 = ap_const_lv4_B)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and (tmp_37_fu_13557_p1 = ap_const_lv4_C)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and (tmp_37_fu_13557_p1 = ap_const_lv4_D)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and (tmp_37_fu_13557_p1 = ap_const_lv4_0)))) then
end_5_3_reg_6439 <= end_5_2_reg_5001;
end if;
end if;
end process;
-- end_6_1_reg_4006 assign process. --
end_6_1_reg_4006_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ST_st44_fsm_43 = ap_CS_fsm) and not((ap_const_lv1_0 = exitcond_fu_13718_p2)) and (ap_const_lv1_0 = all_end_phi_fu_12651_p36))) then
end_6_1_reg_4006 <= end_6_2_reg_4986;
elsif (((ap_ST_st8_fsm_7 = ap_CS_fsm) and not((exitcond2_fu_13247_p2 = ap_const_lv1_0)))) then
end_6_1_reg_4006 <= end_6_s_reg_924;
end if;
end if;
end process;
-- end_6_2_reg_4986 assign process. --
end_6_2_reg_4986_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ST_st43_fsm_42 = ap_CS_fsm) or ((ap_ST_st32_fsm_31 = ap_CS_fsm) and ((not((ap_const_lv1_0 = end_load_3_phi_phi_fu_11584_p32)) and (ap_const_lv1_0 = brmerge_demorgan_reg_14680)) or (not((ap_const_lv1_0 = end_load_3_phi_phi_fu_11584_p32)) and not((ap_const_lv1_0 = tmp1_fu_13626_p2))))))) then
end_6_2_reg_4986 <= end_6_3_reg_6383;
elsif ((ap_ST_st18_fsm_17 = ap_CS_fsm)) then
end_6_2_reg_4986 <= end_6_1_reg_4006;
end if;
end if;
end process;
-- end_6_3_reg_6383 assign process. --
end_6_3_reg_6383_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and (tmp_37_fu_13557_p1 = ap_const_lv4_6))) then
end_6_3_reg_6383 <= end_0_phi_fu_5844_p32;
elsif ((((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2))) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and (tmp_37_fu_13557_p1 = ap_const_lv4_1)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and (tmp_37_fu_13557_p1 = ap_const_lv4_2)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and (tmp_37_fu_13557_p1 = ap_const_lv4_3)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and (tmp_37_fu_13557_p1 = ap_const_lv4_4)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and (tmp_37_fu_13557_p1 = ap_const_lv4_5)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and (tmp_37_fu_13557_p1 = ap_const_lv4_7)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and (tmp_37_fu_13557_p1 = ap_const_lv4_8)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and (tmp_37_fu_13557_p1 = ap_const_lv4_9)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and (tmp_37_fu_13557_p1 = ap_const_lv4_A)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and (tmp_37_fu_13557_p1 = ap_const_lv4_B)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and (tmp_37_fu_13557_p1 = ap_const_lv4_C)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and (tmp_37_fu_13557_p1 = ap_const_lv4_D)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and (tmp_37_fu_13557_p1 = ap_const_lv4_0)))) then
end_6_3_reg_6383 <= end_6_2_reg_4986;
end if;
end if;
end process;
-- end_7_1_reg_3995 assign process. --
end_7_1_reg_3995_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ST_st44_fsm_43 = ap_CS_fsm) and not((ap_const_lv1_0 = exitcond_fu_13718_p2)) and (ap_const_lv1_0 = all_end_phi_fu_12651_p36))) then
end_7_1_reg_3995 <= end_7_2_reg_4971;
elsif (((ap_ST_st8_fsm_7 = ap_CS_fsm) and not((exitcond2_fu_13247_p2 = ap_const_lv1_0)))) then
end_7_1_reg_3995 <= end_7_s_reg_912;
end if;
end if;
end process;
-- end_7_2_reg_4971 assign process. --
end_7_2_reg_4971_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ST_st43_fsm_42 = ap_CS_fsm) or ((ap_ST_st32_fsm_31 = ap_CS_fsm) and ((not((ap_const_lv1_0 = end_load_3_phi_phi_fu_11584_p32)) and (ap_const_lv1_0 = brmerge_demorgan_reg_14680)) or (not((ap_const_lv1_0 = end_load_3_phi_phi_fu_11584_p32)) and not((ap_const_lv1_0 = tmp1_fu_13626_p2))))))) then
end_7_2_reg_4971 <= end_7_3_reg_6327;
elsif ((ap_ST_st18_fsm_17 = ap_CS_fsm)) then
end_7_2_reg_4971 <= end_7_1_reg_3995;
end if;
end if;
end process;
-- end_7_3_reg_6327 assign process. --
end_7_3_reg_6327_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and (tmp_37_fu_13557_p1 = ap_const_lv4_7))) then
end_7_3_reg_6327 <= end_0_phi_fu_5844_p32;
elsif ((((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2))) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and (tmp_37_fu_13557_p1 = ap_const_lv4_1)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and (tmp_37_fu_13557_p1 = ap_const_lv4_2)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and (tmp_37_fu_13557_p1 = ap_const_lv4_3)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and (tmp_37_fu_13557_p1 = ap_const_lv4_4)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and (tmp_37_fu_13557_p1 = ap_const_lv4_5)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and (tmp_37_fu_13557_p1 = ap_const_lv4_6)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and (tmp_37_fu_13557_p1 = ap_const_lv4_8)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and (tmp_37_fu_13557_p1 = ap_const_lv4_9)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and (tmp_37_fu_13557_p1 = ap_const_lv4_A)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and (tmp_37_fu_13557_p1 = ap_const_lv4_B)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and (tmp_37_fu_13557_p1 = ap_const_lv4_C)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and (tmp_37_fu_13557_p1 = ap_const_lv4_D)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and (tmp_37_fu_13557_p1 = ap_const_lv4_0)))) then
end_7_3_reg_6327 <= end_7_2_reg_4971;
end if;
end if;
end process;
-- end_8_1_reg_3984 assign process. --
end_8_1_reg_3984_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ST_st44_fsm_43 = ap_CS_fsm) and not((ap_const_lv1_0 = exitcond_fu_13718_p2)) and (ap_const_lv1_0 = all_end_phi_fu_12651_p36))) then
end_8_1_reg_3984 <= end_8_2_reg_4956;
elsif (((ap_ST_st8_fsm_7 = ap_CS_fsm) and not((exitcond2_fu_13247_p2 = ap_const_lv1_0)))) then
end_8_1_reg_3984 <= end_8_s_reg_900;
end if;
end if;
end process;
-- end_8_2_reg_4956 assign process. --
end_8_2_reg_4956_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ST_st43_fsm_42 = ap_CS_fsm) or ((ap_ST_st32_fsm_31 = ap_CS_fsm) and ((not((ap_const_lv1_0 = end_load_3_phi_phi_fu_11584_p32)) and (ap_const_lv1_0 = brmerge_demorgan_reg_14680)) or (not((ap_const_lv1_0 = end_load_3_phi_phi_fu_11584_p32)) and not((ap_const_lv1_0 = tmp1_fu_13626_p2))))))) then
end_8_2_reg_4956 <= end_8_3_reg_6271;
elsif ((ap_ST_st18_fsm_17 = ap_CS_fsm)) then
end_8_2_reg_4956 <= end_8_1_reg_3984;
end if;
end if;
end process;
-- end_8_3_reg_6271 assign process. --
end_8_3_reg_6271_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and (tmp_37_fu_13557_p1 = ap_const_lv4_8))) then
end_8_3_reg_6271 <= end_0_phi_fu_5844_p32;
elsif ((((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2))) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and (tmp_37_fu_13557_p1 = ap_const_lv4_1)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and (tmp_37_fu_13557_p1 = ap_const_lv4_2)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and (tmp_37_fu_13557_p1 = ap_const_lv4_3)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and (tmp_37_fu_13557_p1 = ap_const_lv4_4)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and (tmp_37_fu_13557_p1 = ap_const_lv4_5)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and (tmp_37_fu_13557_p1 = ap_const_lv4_6)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and (tmp_37_fu_13557_p1 = ap_const_lv4_7)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and (tmp_37_fu_13557_p1 = ap_const_lv4_9)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and (tmp_37_fu_13557_p1 = ap_const_lv4_A)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and (tmp_37_fu_13557_p1 = ap_const_lv4_B)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and (tmp_37_fu_13557_p1 = ap_const_lv4_C)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and (tmp_37_fu_13557_p1 = ap_const_lv4_D)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and (tmp_37_fu_13557_p1 = ap_const_lv4_0)))) then
end_8_3_reg_6271 <= end_8_2_reg_4956;
end if;
end if;
end process;
-- end_9_1_reg_3973 assign process. --
end_9_1_reg_3973_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ST_st44_fsm_43 = ap_CS_fsm) and not((ap_const_lv1_0 = exitcond_fu_13718_p2)) and (ap_const_lv1_0 = all_end_phi_fu_12651_p36))) then
end_9_1_reg_3973 <= end_9_2_reg_4941;
elsif (((ap_ST_st8_fsm_7 = ap_CS_fsm) and not((exitcond2_fu_13247_p2 = ap_const_lv1_0)))) then
end_9_1_reg_3973 <= end_9_s_reg_888;
end if;
end if;
end process;
-- end_9_2_reg_4941 assign process. --
end_9_2_reg_4941_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ST_st43_fsm_42 = ap_CS_fsm) or ((ap_ST_st32_fsm_31 = ap_CS_fsm) and ((not((ap_const_lv1_0 = end_load_3_phi_phi_fu_11584_p32)) and (ap_const_lv1_0 = brmerge_demorgan_reg_14680)) or (not((ap_const_lv1_0 = end_load_3_phi_phi_fu_11584_p32)) and not((ap_const_lv1_0 = tmp1_fu_13626_p2))))))) then
end_9_2_reg_4941 <= end_9_3_reg_6215;
elsif ((ap_ST_st18_fsm_17 = ap_CS_fsm)) then
end_9_2_reg_4941 <= end_9_1_reg_3973;
end if;
end if;
end process;
-- end_9_3_reg_6215 assign process. --
end_9_3_reg_6215_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and (tmp_37_fu_13557_p1 = ap_const_lv4_9))) then
end_9_3_reg_6215 <= end_0_phi_fu_5844_p32;
elsif ((((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2))) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and (tmp_37_fu_13557_p1 = ap_const_lv4_1)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and (tmp_37_fu_13557_p1 = ap_const_lv4_2)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and (tmp_37_fu_13557_p1 = ap_const_lv4_3)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and (tmp_37_fu_13557_p1 = ap_const_lv4_4)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and (tmp_37_fu_13557_p1 = ap_const_lv4_5)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and (tmp_37_fu_13557_p1 = ap_const_lv4_6)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and (tmp_37_fu_13557_p1 = ap_const_lv4_7)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and (tmp_37_fu_13557_p1 = ap_const_lv4_8)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and (tmp_37_fu_13557_p1 = ap_const_lv4_A)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and (tmp_37_fu_13557_p1 = ap_const_lv4_B)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and (tmp_37_fu_13557_p1 = ap_const_lv4_C)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and (tmp_37_fu_13557_p1 = ap_const_lv4_D)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and (tmp_37_fu_13557_p1 = ap_const_lv4_0)))) then
end_9_3_reg_6215 <= end_9_2_reg_4941;
end if;
end if;
end process;
-- end_load_phi_reg_12753 assign process. --
end_load_phi_reg_12753_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_sig_bdd_395) then
if ((tmp_38_fu_13733_p1 = ap_const_lv4_0)) then
end_load_phi_reg_12753 <= end_0_2_reg_5076;
elsif ((tmp_38_fu_13733_p1 = ap_const_lv4_E)) then
end_load_phi_reg_12753 <= end_14_2_reg_4866;
elsif ((tmp_38_fu_13733_p1 = ap_const_lv4_D)) then
end_load_phi_reg_12753 <= end_13_2_reg_4881;
elsif ((tmp_38_fu_13733_p1 = ap_const_lv4_C)) then
end_load_phi_reg_12753 <= end_12_2_reg_4896;
elsif ((tmp_38_fu_13733_p1 = ap_const_lv4_B)) then
end_load_phi_reg_12753 <= end_11_2_reg_4911;
elsif ((tmp_38_fu_13733_p1 = ap_const_lv4_A)) then
end_load_phi_reg_12753 <= end_10_2_reg_4926;
elsif ((tmp_38_fu_13733_p1 = ap_const_lv4_9)) then
end_load_phi_reg_12753 <= end_9_2_reg_4941;
elsif ((tmp_38_fu_13733_p1 = ap_const_lv4_8)) then
end_load_phi_reg_12753 <= end_8_2_reg_4956;
elsif ((tmp_38_fu_13733_p1 = ap_const_lv4_7)) then
end_load_phi_reg_12753 <= end_7_2_reg_4971;
elsif ((tmp_38_fu_13733_p1 = ap_const_lv4_6)) then
end_load_phi_reg_12753 <= end_6_2_reg_4986;
elsif ((tmp_38_fu_13733_p1 = ap_const_lv4_5)) then
end_load_phi_reg_12753 <= end_5_2_reg_5001;
elsif ((tmp_38_fu_13733_p1 = ap_const_lv4_4)) then
end_load_phi_reg_12753 <= end_4_2_reg_5016;
elsif ((tmp_38_fu_13733_p1 = ap_const_lv4_3)) then
end_load_phi_reg_12753 <= end_3_2_reg_5031;
elsif ((tmp_38_fu_13733_p1 = ap_const_lv4_2)) then
end_load_phi_reg_12753 <= end_2_2_reg_5046;
elsif ((tmp_38_fu_13733_p1 = ap_const_lv4_1)) then
end_load_phi_reg_12753 <= end_1_2_reg_5061;
elsif ((ap_true = ap_true)) then
end_load_phi_reg_12753 <= end_15_2_reg_4851;
end if;
end if;
end if;
end process;
-- end_string_0_2_reg_1542 assign process. --
end_string_0_2_reg_1542_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ST_st2_fsm_1 = ap_CS_fsm) and not((ap_const_lv1_0 = exitcond3_fu_12991_p2)))) then
end_string_0_2_reg_1542 <= end_string_fu_152;
elsif (((ap_ST_st44_fsm_43 = ap_CS_fsm) and not((ap_const_lv1_0 = exitcond_fu_13718_p2)) and not((ap_const_lv1_0 = all_end_phi_fu_12651_p36)))) then
end_string_0_2_reg_1542 <= end_string_0_4_reg_5812;
end if;
end if;
end process;
-- end_string_0_3_reg_4600 assign process. --
end_string_0_3_reg_4600_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ST_st44_fsm_43 = ap_CS_fsm) and not((ap_const_lv1_0 = exitcond_fu_13718_p2)) and (ap_const_lv1_0 = all_end_phi_fu_12651_p36))) then
end_string_0_3_reg_4600 <= end_string_0_4_reg_5812;
elsif (((ap_ST_st8_fsm_7 = ap_CS_fsm) and not((exitcond2_fu_13247_p2 = ap_const_lv1_0)))) then
end_string_0_3_reg_4600 <= end_string_0_2_reg_1542;
end if;
end if;
end process;
-- end_string_0_4_reg_5812 assign process. --
end_string_0_4_reg_5812_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ST_st43_fsm_42 = ap_CS_fsm) or ((ap_ST_st32_fsm_31 = ap_CS_fsm) and ((not((ap_const_lv1_0 = end_load_3_phi_phi_fu_11584_p32)) and (ap_const_lv1_0 = brmerge_demorgan_reg_14680)) or (not((ap_const_lv1_0 = end_load_3_phi_phi_fu_11584_p32)) and not((ap_const_lv1_0 = tmp1_fu_13626_p2))))))) then
end_string_0_4_reg_5812 <= end_string_0_6_reg_11469;
elsif ((ap_ST_st18_fsm_17 = ap_CS_fsm)) then
end_string_0_4_reg_5812 <= end_string_0_3_reg_4600;
end if;
end if;
end process;
-- end_string_0_5_reg_7649 assign process. --
end_string_0_5_reg_7649_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and not((ap_const_lv1_0 = end_0_phi_fu_5844_p32)) and (tmp_37_fu_13557_p1 = ap_const_lv4_0))) then
end_string_0_5_reg_7649 <= end_string_0_phi_fu_6831_p4;
elsif ((((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and not((ap_const_lv1_0 = end_0_phi_fu_5844_p32))) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and not((ap_const_lv1_0 = end_0_phi_fu_5844_p32)) and (tmp_37_fu_13557_p1 = ap_const_lv4_D)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and not((ap_const_lv1_0 = end_0_phi_fu_5844_p32)) and (tmp_37_fu_13557_p1 = ap_const_lv4_C)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and not((ap_const_lv1_0 = end_0_phi_fu_5844_p32)) and (tmp_37_fu_13557_p1 = ap_const_lv4_B)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and not((ap_const_lv1_0 = end_0_phi_fu_5844_p32)) and (tmp_37_fu_13557_p1 = ap_const_lv4_A)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and not((ap_const_lv1_0 = end_0_phi_fu_5844_p32)) and (tmp_37_fu_13557_p1 = ap_const_lv4_9)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and not((ap_const_lv1_0 = end_0_phi_fu_5844_p32)) and (tmp_37_fu_13557_p1 = ap_const_lv4_8)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and not((ap_const_lv1_0 = end_0_phi_fu_5844_p32)) and (tmp_37_fu_13557_p1 = ap_const_lv4_7)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and not((ap_const_lv1_0 = end_0_phi_fu_5844_p32)) and (tmp_37_fu_13557_p1 = ap_const_lv4_6)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and not((ap_const_lv1_0 = end_0_phi_fu_5844_p32)) and (tmp_37_fu_13557_p1 = ap_const_lv4_5)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and not((ap_const_lv1_0 = end_0_phi_fu_5844_p32)) and (tmp_37_fu_13557_p1 = ap_const_lv4_4)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and not((ap_const_lv1_0 = end_0_phi_fu_5844_p32)) and (tmp_37_fu_13557_p1 = ap_const_lv4_3)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and not((ap_const_lv1_0 = end_0_phi_fu_5844_p32)) and (tmp_37_fu_13557_p1 = ap_const_lv4_2)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and not((ap_const_lv1_0 = end_0_phi_fu_5844_p32)) and (tmp_37_fu_13557_p1 = ap_const_lv4_1)))) then
end_string_0_5_reg_7649 <= end_string_0_4_reg_5812;
end if;
end if;
end process;
-- end_string_0_6_reg_11469 assign process. --
end_string_0_6_reg_11469_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ST_st30_fsm_29 = ap_CS_fsm) and not((ap_const_lv1_0 = end_0_reg_5841)))) then
end_string_0_6_reg_11469 <= end_string_0_5_reg_7649;
elsif ((((ap_ST_st22_fsm_21 = ap_CS_fsm) and not((tmp_37_reg_14631 = ap_const_lv4_E)) and not((tmp_37_reg_14631 = ap_const_lv4_D)) and not((tmp_37_reg_14631 = ap_const_lv4_C)) and not((tmp_37_reg_14631 = ap_const_lv4_B)) and not((tmp_37_reg_14631 = ap_const_lv4_A)) and not((tmp_37_reg_14631 = ap_const_lv4_9)) and not((tmp_37_reg_14631 = ap_const_lv4_8)) and not((tmp_37_reg_14631 = ap_const_lv4_7)) and not((tmp_37_reg_14631 = ap_const_lv4_6)) and not((tmp_37_reg_14631 = ap_const_lv4_5)) and not((tmp_37_reg_14631 = ap_const_lv4_4)) and not((tmp_37_reg_14631 = ap_const_lv4_3)) and not((tmp_37_reg_14631 = ap_const_lv4_2)) and not((tmp_37_reg_14631 = ap_const_lv4_1)) and not((tmp_37_reg_14631 = ap_const_lv4_0))) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_E)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_D)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_C)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_B)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_A)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_9)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_8)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_7)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_6)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_5)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_4)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_3)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_2)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_1)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_0)))) then
end_string_0_6_reg_11469 <= end_string_0_4_reg_5812;
end if;
end if;
end process;
-- end_string_0_reg_6828 assign process. --
end_string_0_reg_6828_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_sig_bdd_1793) then
if (not((ap_const_lv1_0 = tmp_7_reg_14542))) then
end_string_0_reg_6828 <= ap_const_lv1_1;
elsif ((ap_const_lv1_0 = tmp_7_reg_14542)) then
end_string_0_reg_6828 <= tmp_12_fu_13561_p2;
end if;
end if;
end if;
end process;
-- end_string_10_2_reg_1442 assign process. --
end_string_10_2_reg_1442_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ST_st2_fsm_1 = ap_CS_fsm) and not((ap_const_lv1_0 = exitcond3_fu_12991_p2)))) then
end_string_10_2_reg_1442 <= end_string_10_fu_192;
elsif (((ap_ST_st44_fsm_43 = ap_CS_fsm) and not((ap_const_lv1_0 = exitcond_fu_13718_p2)) and not((ap_const_lv1_0 = all_end_phi_fu_12651_p36)))) then
end_string_10_2_reg_1442 <= end_string_10_4_reg_5662;
end if;
end if;
end process;
-- end_string_10_3_reg_4490 assign process. --
end_string_10_3_reg_4490_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ST_st44_fsm_43 = ap_CS_fsm) and not((ap_const_lv1_0 = exitcond_fu_13718_p2)) and (ap_const_lv1_0 = all_end_phi_fu_12651_p36))) then
end_string_10_3_reg_4490 <= end_string_10_4_reg_5662;
elsif (((ap_ST_st8_fsm_7 = ap_CS_fsm) and not((exitcond2_fu_13247_p2 = ap_const_lv1_0)))) then
end_string_10_3_reg_4490 <= end_string_10_2_reg_1442;
end if;
end if;
end process;
-- end_string_10_4_reg_5662 assign process. --
end_string_10_4_reg_5662_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ST_st43_fsm_42 = ap_CS_fsm) or ((ap_ST_st32_fsm_31 = ap_CS_fsm) and ((not((ap_const_lv1_0 = end_load_3_phi_phi_fu_11584_p32)) and (ap_const_lv1_0 = brmerge_demorgan_reg_14680)) or (not((ap_const_lv1_0 = end_load_3_phi_phi_fu_11584_p32)) and not((ap_const_lv1_0 = tmp1_fu_13626_p2))))))) then
end_string_10_4_reg_5662 <= end_string_10_6_reg_10879;
elsif ((ap_ST_st18_fsm_17 = ap_CS_fsm)) then
end_string_10_4_reg_5662 <= end_string_10_3_reg_4490;
end if;
end if;
end process;
-- end_string_10_5_reg_7109 assign process. --
end_string_10_5_reg_7109_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and not((ap_const_lv1_0 = end_0_phi_fu_5844_p32)) and (tmp_37_fu_13557_p1 = ap_const_lv4_A))) then
end_string_10_5_reg_7109 <= end_string_0_phi_fu_6831_p4;
elsif ((((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and not((ap_const_lv1_0 = end_0_phi_fu_5844_p32))) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and not((ap_const_lv1_0 = end_0_phi_fu_5844_p32)) and (tmp_37_fu_13557_p1 = ap_const_lv4_D)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and not((ap_const_lv1_0 = end_0_phi_fu_5844_p32)) and (tmp_37_fu_13557_p1 = ap_const_lv4_C)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and not((ap_const_lv1_0 = end_0_phi_fu_5844_p32)) and (tmp_37_fu_13557_p1 = ap_const_lv4_B)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and not((ap_const_lv1_0 = end_0_phi_fu_5844_p32)) and (tmp_37_fu_13557_p1 = ap_const_lv4_9)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and not((ap_const_lv1_0 = end_0_phi_fu_5844_p32)) and (tmp_37_fu_13557_p1 = ap_const_lv4_8)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and not((ap_const_lv1_0 = end_0_phi_fu_5844_p32)) and (tmp_37_fu_13557_p1 = ap_const_lv4_7)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and not((ap_const_lv1_0 = end_0_phi_fu_5844_p32)) and (tmp_37_fu_13557_p1 = ap_const_lv4_6)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and not((ap_const_lv1_0 = end_0_phi_fu_5844_p32)) and (tmp_37_fu_13557_p1 = ap_const_lv4_5)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and not((ap_const_lv1_0 = end_0_phi_fu_5844_p32)) and (tmp_37_fu_13557_p1 = ap_const_lv4_4)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and not((ap_const_lv1_0 = end_0_phi_fu_5844_p32)) and (tmp_37_fu_13557_p1 = ap_const_lv4_3)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and not((ap_const_lv1_0 = end_0_phi_fu_5844_p32)) and (tmp_37_fu_13557_p1 = ap_const_lv4_2)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and not((ap_const_lv1_0 = end_0_phi_fu_5844_p32)) and (tmp_37_fu_13557_p1 = ap_const_lv4_1)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and not((ap_const_lv1_0 = end_0_phi_fu_5844_p32)) and (tmp_37_fu_13557_p1 = ap_const_lv4_0)))) then
end_string_10_5_reg_7109 <= end_string_10_4_reg_5662;
end if;
end if;
end process;
-- end_string_10_6_reg_10879 assign process. --
end_string_10_6_reg_10879_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ST_st30_fsm_29 = ap_CS_fsm) and not((ap_const_lv1_0 = end_0_reg_5841)))) then
end_string_10_6_reg_10879 <= end_string_10_5_reg_7109;
elsif ((((ap_ST_st22_fsm_21 = ap_CS_fsm) and not((tmp_37_reg_14631 = ap_const_lv4_E)) and not((tmp_37_reg_14631 = ap_const_lv4_D)) and not((tmp_37_reg_14631 = ap_const_lv4_C)) and not((tmp_37_reg_14631 = ap_const_lv4_B)) and not((tmp_37_reg_14631 = ap_const_lv4_A)) and not((tmp_37_reg_14631 = ap_const_lv4_9)) and not((tmp_37_reg_14631 = ap_const_lv4_8)) and not((tmp_37_reg_14631 = ap_const_lv4_7)) and not((tmp_37_reg_14631 = ap_const_lv4_6)) and not((tmp_37_reg_14631 = ap_const_lv4_5)) and not((tmp_37_reg_14631 = ap_const_lv4_4)) and not((tmp_37_reg_14631 = ap_const_lv4_3)) and not((tmp_37_reg_14631 = ap_const_lv4_2)) and not((tmp_37_reg_14631 = ap_const_lv4_1)) and not((tmp_37_reg_14631 = ap_const_lv4_0))) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_E)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_D)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_C)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_B)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_A)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_9)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_8)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_7)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_6)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_5)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_4)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_3)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_2)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_1)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_0)))) then
end_string_10_6_reg_10879 <= end_string_10_4_reg_5662;
end if;
end if;
end process;
-- end_string_11_2_reg_1432 assign process. --
end_string_11_2_reg_1432_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ST_st2_fsm_1 = ap_CS_fsm) and not((ap_const_lv1_0 = exitcond3_fu_12991_p2)))) then
end_string_11_2_reg_1432 <= end_string_11_fu_196;
elsif (((ap_ST_st44_fsm_43 = ap_CS_fsm) and not((ap_const_lv1_0 = exitcond_fu_13718_p2)) and not((ap_const_lv1_0 = all_end_phi_fu_12651_p36)))) then
end_string_11_2_reg_1432 <= end_string_11_4_reg_5647;
end if;
end if;
end process;
-- end_string_11_3_reg_4479 assign process. --
end_string_11_3_reg_4479_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ST_st44_fsm_43 = ap_CS_fsm) and not((ap_const_lv1_0 = exitcond_fu_13718_p2)) and (ap_const_lv1_0 = all_end_phi_fu_12651_p36))) then
end_string_11_3_reg_4479 <= end_string_11_4_reg_5647;
elsif (((ap_ST_st8_fsm_7 = ap_CS_fsm) and not((exitcond2_fu_13247_p2 = ap_const_lv1_0)))) then
end_string_11_3_reg_4479 <= end_string_11_2_reg_1432;
end if;
end if;
end process;
-- end_string_11_4_reg_5647 assign process. --
end_string_11_4_reg_5647_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ST_st43_fsm_42 = ap_CS_fsm) or ((ap_ST_st32_fsm_31 = ap_CS_fsm) and ((not((ap_const_lv1_0 = end_load_3_phi_phi_fu_11584_p32)) and (ap_const_lv1_0 = brmerge_demorgan_reg_14680)) or (not((ap_const_lv1_0 = end_load_3_phi_phi_fu_11584_p32)) and not((ap_const_lv1_0 = tmp1_fu_13626_p2))))))) then
end_string_11_4_reg_5647 <= end_string_11_6_reg_10820;
elsif ((ap_ST_st18_fsm_17 = ap_CS_fsm)) then
end_string_11_4_reg_5647 <= end_string_11_3_reg_4479;
end if;
end if;
end process;
-- end_string_11_5_reg_7055 assign process. --
end_string_11_5_reg_7055_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and not((ap_const_lv1_0 = end_0_phi_fu_5844_p32)) and (tmp_37_fu_13557_p1 = ap_const_lv4_B))) then
end_string_11_5_reg_7055 <= end_string_0_phi_fu_6831_p4;
elsif ((((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and not((ap_const_lv1_0 = end_0_phi_fu_5844_p32))) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and not((ap_const_lv1_0 = end_0_phi_fu_5844_p32)) and (tmp_37_fu_13557_p1 = ap_const_lv4_D)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and not((ap_const_lv1_0 = end_0_phi_fu_5844_p32)) and (tmp_37_fu_13557_p1 = ap_const_lv4_C)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and not((ap_const_lv1_0 = end_0_phi_fu_5844_p32)) and (tmp_37_fu_13557_p1 = ap_const_lv4_A)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and not((ap_const_lv1_0 = end_0_phi_fu_5844_p32)) and (tmp_37_fu_13557_p1 = ap_const_lv4_9)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and not((ap_const_lv1_0 = end_0_phi_fu_5844_p32)) and (tmp_37_fu_13557_p1 = ap_const_lv4_8)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and not((ap_const_lv1_0 = end_0_phi_fu_5844_p32)) and (tmp_37_fu_13557_p1 = ap_const_lv4_7)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and not((ap_const_lv1_0 = end_0_phi_fu_5844_p32)) and (tmp_37_fu_13557_p1 = ap_const_lv4_6)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and not((ap_const_lv1_0 = end_0_phi_fu_5844_p32)) and (tmp_37_fu_13557_p1 = ap_const_lv4_5)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and not((ap_const_lv1_0 = end_0_phi_fu_5844_p32)) and (tmp_37_fu_13557_p1 = ap_const_lv4_4)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and not((ap_const_lv1_0 = end_0_phi_fu_5844_p32)) and (tmp_37_fu_13557_p1 = ap_const_lv4_3)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and not((ap_const_lv1_0 = end_0_phi_fu_5844_p32)) and (tmp_37_fu_13557_p1 = ap_const_lv4_2)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and not((ap_const_lv1_0 = end_0_phi_fu_5844_p32)) and (tmp_37_fu_13557_p1 = ap_const_lv4_1)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and not((ap_const_lv1_0 = end_0_phi_fu_5844_p32)) and (tmp_37_fu_13557_p1 = ap_const_lv4_0)))) then
end_string_11_5_reg_7055 <= end_string_11_4_reg_5647;
end if;
end if;
end process;
-- end_string_11_6_reg_10820 assign process. --
end_string_11_6_reg_10820_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ST_st30_fsm_29 = ap_CS_fsm) and not((ap_const_lv1_0 = end_0_reg_5841)))) then
end_string_11_6_reg_10820 <= end_string_11_5_reg_7055;
elsif ((((ap_ST_st22_fsm_21 = ap_CS_fsm) and not((tmp_37_reg_14631 = ap_const_lv4_E)) and not((tmp_37_reg_14631 = ap_const_lv4_D)) and not((tmp_37_reg_14631 = ap_const_lv4_C)) and not((tmp_37_reg_14631 = ap_const_lv4_B)) and not((tmp_37_reg_14631 = ap_const_lv4_A)) and not((tmp_37_reg_14631 = ap_const_lv4_9)) and not((tmp_37_reg_14631 = ap_const_lv4_8)) and not((tmp_37_reg_14631 = ap_const_lv4_7)) and not((tmp_37_reg_14631 = ap_const_lv4_6)) and not((tmp_37_reg_14631 = ap_const_lv4_5)) and not((tmp_37_reg_14631 = ap_const_lv4_4)) and not((tmp_37_reg_14631 = ap_const_lv4_3)) and not((tmp_37_reg_14631 = ap_const_lv4_2)) and not((tmp_37_reg_14631 = ap_const_lv4_1)) and not((tmp_37_reg_14631 = ap_const_lv4_0))) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_E)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_D)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_C)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_B)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_A)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_9)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_8)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_7)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_6)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_5)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_4)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_3)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_2)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_1)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_0)))) then
end_string_11_6_reg_10820 <= end_string_11_4_reg_5647;
end if;
end if;
end process;
-- end_string_12_2_reg_1422 assign process. --
end_string_12_2_reg_1422_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ST_st2_fsm_1 = ap_CS_fsm) and not((ap_const_lv1_0 = exitcond3_fu_12991_p2)))) then
end_string_12_2_reg_1422 <= end_string_12_fu_200;
elsif (((ap_ST_st44_fsm_43 = ap_CS_fsm) and not((ap_const_lv1_0 = exitcond_fu_13718_p2)) and not((ap_const_lv1_0 = all_end_phi_fu_12651_p36)))) then
end_string_12_2_reg_1422 <= end_string_12_4_reg_5632;
end if;
end if;
end process;
-- end_string_12_3_reg_4468 assign process. --
end_string_12_3_reg_4468_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ST_st44_fsm_43 = ap_CS_fsm) and not((ap_const_lv1_0 = exitcond_fu_13718_p2)) and (ap_const_lv1_0 = all_end_phi_fu_12651_p36))) then
end_string_12_3_reg_4468 <= end_string_12_4_reg_5632;
elsif (((ap_ST_st8_fsm_7 = ap_CS_fsm) and not((exitcond2_fu_13247_p2 = ap_const_lv1_0)))) then
end_string_12_3_reg_4468 <= end_string_12_2_reg_1422;
end if;
end if;
end process;
-- end_string_12_4_reg_5632 assign process. --
end_string_12_4_reg_5632_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ST_st43_fsm_42 = ap_CS_fsm) or ((ap_ST_st32_fsm_31 = ap_CS_fsm) and ((not((ap_const_lv1_0 = end_load_3_phi_phi_fu_11584_p32)) and (ap_const_lv1_0 = brmerge_demorgan_reg_14680)) or (not((ap_const_lv1_0 = end_load_3_phi_phi_fu_11584_p32)) and not((ap_const_lv1_0 = tmp1_fu_13626_p2))))))) then
end_string_12_4_reg_5632 <= end_string_12_6_reg_10761;
elsif ((ap_ST_st18_fsm_17 = ap_CS_fsm)) then
end_string_12_4_reg_5632 <= end_string_12_3_reg_4468;
end if;
end if;
end process;
-- end_string_12_5_reg_7001 assign process. --
end_string_12_5_reg_7001_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and not((ap_const_lv1_0 = end_0_phi_fu_5844_p32)) and (tmp_37_fu_13557_p1 = ap_const_lv4_C))) then
end_string_12_5_reg_7001 <= end_string_0_phi_fu_6831_p4;
elsif ((((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and not((ap_const_lv1_0 = end_0_phi_fu_5844_p32))) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and not((ap_const_lv1_0 = end_0_phi_fu_5844_p32)) and (tmp_37_fu_13557_p1 = ap_const_lv4_D)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and not((ap_const_lv1_0 = end_0_phi_fu_5844_p32)) and (tmp_37_fu_13557_p1 = ap_const_lv4_B)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and not((ap_const_lv1_0 = end_0_phi_fu_5844_p32)) and (tmp_37_fu_13557_p1 = ap_const_lv4_A)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and not((ap_const_lv1_0 = end_0_phi_fu_5844_p32)) and (tmp_37_fu_13557_p1 = ap_const_lv4_9)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and not((ap_const_lv1_0 = end_0_phi_fu_5844_p32)) and (tmp_37_fu_13557_p1 = ap_const_lv4_8)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and not((ap_const_lv1_0 = end_0_phi_fu_5844_p32)) and (tmp_37_fu_13557_p1 = ap_const_lv4_7)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and not((ap_const_lv1_0 = end_0_phi_fu_5844_p32)) and (tmp_37_fu_13557_p1 = ap_const_lv4_6)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and not((ap_const_lv1_0 = end_0_phi_fu_5844_p32)) and (tmp_37_fu_13557_p1 = ap_const_lv4_5)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and not((ap_const_lv1_0 = end_0_phi_fu_5844_p32)) and (tmp_37_fu_13557_p1 = ap_const_lv4_4)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and not((ap_const_lv1_0 = end_0_phi_fu_5844_p32)) and (tmp_37_fu_13557_p1 = ap_const_lv4_3)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and not((ap_const_lv1_0 = end_0_phi_fu_5844_p32)) and (tmp_37_fu_13557_p1 = ap_const_lv4_2)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and not((ap_const_lv1_0 = end_0_phi_fu_5844_p32)) and (tmp_37_fu_13557_p1 = ap_const_lv4_1)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and not((ap_const_lv1_0 = end_0_phi_fu_5844_p32)) and (tmp_37_fu_13557_p1 = ap_const_lv4_0)))) then
end_string_12_5_reg_7001 <= end_string_12_4_reg_5632;
end if;
end if;
end process;
-- end_string_12_6_reg_10761 assign process. --
end_string_12_6_reg_10761_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ST_st30_fsm_29 = ap_CS_fsm) and not((ap_const_lv1_0 = end_0_reg_5841)))) then
end_string_12_6_reg_10761 <= end_string_12_5_reg_7001;
elsif ((((ap_ST_st22_fsm_21 = ap_CS_fsm) and not((tmp_37_reg_14631 = ap_const_lv4_E)) and not((tmp_37_reg_14631 = ap_const_lv4_D)) and not((tmp_37_reg_14631 = ap_const_lv4_C)) and not((tmp_37_reg_14631 = ap_const_lv4_B)) and not((tmp_37_reg_14631 = ap_const_lv4_A)) and not((tmp_37_reg_14631 = ap_const_lv4_9)) and not((tmp_37_reg_14631 = ap_const_lv4_8)) and not((tmp_37_reg_14631 = ap_const_lv4_7)) and not((tmp_37_reg_14631 = ap_const_lv4_6)) and not((tmp_37_reg_14631 = ap_const_lv4_5)) and not((tmp_37_reg_14631 = ap_const_lv4_4)) and not((tmp_37_reg_14631 = ap_const_lv4_3)) and not((tmp_37_reg_14631 = ap_const_lv4_2)) and not((tmp_37_reg_14631 = ap_const_lv4_1)) and not((tmp_37_reg_14631 = ap_const_lv4_0))) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_E)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_D)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_C)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_B)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_A)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_9)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_8)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_7)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_6)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_5)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_4)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_3)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_2)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_1)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_0)))) then
end_string_12_6_reg_10761 <= end_string_12_4_reg_5632;
end if;
end if;
end process;
-- end_string_13_2_reg_1412 assign process. --
end_string_13_2_reg_1412_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ST_st2_fsm_1 = ap_CS_fsm) and not((ap_const_lv1_0 = exitcond3_fu_12991_p2)))) then
end_string_13_2_reg_1412 <= end_string_13_fu_204;
elsif (((ap_ST_st44_fsm_43 = ap_CS_fsm) and not((ap_const_lv1_0 = exitcond_fu_13718_p2)) and not((ap_const_lv1_0 = all_end_phi_fu_12651_p36)))) then
end_string_13_2_reg_1412 <= end_string_13_4_reg_5617;
end if;
end if;
end process;
-- end_string_13_3_reg_4457 assign process. --
end_string_13_3_reg_4457_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ST_st44_fsm_43 = ap_CS_fsm) and not((ap_const_lv1_0 = exitcond_fu_13718_p2)) and (ap_const_lv1_0 = all_end_phi_fu_12651_p36))) then
end_string_13_3_reg_4457 <= end_string_13_4_reg_5617;
elsif (((ap_ST_st8_fsm_7 = ap_CS_fsm) and not((exitcond2_fu_13247_p2 = ap_const_lv1_0)))) then
end_string_13_3_reg_4457 <= end_string_13_2_reg_1412;
end if;
end if;
end process;
-- end_string_13_4_reg_5617 assign process. --
end_string_13_4_reg_5617_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ST_st43_fsm_42 = ap_CS_fsm) or ((ap_ST_st32_fsm_31 = ap_CS_fsm) and ((not((ap_const_lv1_0 = end_load_3_phi_phi_fu_11584_p32)) and (ap_const_lv1_0 = brmerge_demorgan_reg_14680)) or (not((ap_const_lv1_0 = end_load_3_phi_phi_fu_11584_p32)) and not((ap_const_lv1_0 = tmp1_fu_13626_p2))))))) then
end_string_13_4_reg_5617 <= end_string_13_6_reg_10702;
elsif ((ap_ST_st18_fsm_17 = ap_CS_fsm)) then
end_string_13_4_reg_5617 <= end_string_13_3_reg_4457;
end if;
end if;
end process;
-- end_string_13_5_reg_6947 assign process. --
end_string_13_5_reg_6947_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and not((ap_const_lv1_0 = end_0_phi_fu_5844_p32)) and (tmp_37_fu_13557_p1 = ap_const_lv4_D))) then
end_string_13_5_reg_6947 <= end_string_0_phi_fu_6831_p4;
elsif ((((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and not((ap_const_lv1_0 = end_0_phi_fu_5844_p32))) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and not((ap_const_lv1_0 = end_0_phi_fu_5844_p32)) and (tmp_37_fu_13557_p1 = ap_const_lv4_C)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and not((ap_const_lv1_0 = end_0_phi_fu_5844_p32)) and (tmp_37_fu_13557_p1 = ap_const_lv4_B)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and not((ap_const_lv1_0 = end_0_phi_fu_5844_p32)) and (tmp_37_fu_13557_p1 = ap_const_lv4_A)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and not((ap_const_lv1_0 = end_0_phi_fu_5844_p32)) and (tmp_37_fu_13557_p1 = ap_const_lv4_9)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and not((ap_const_lv1_0 = end_0_phi_fu_5844_p32)) and (tmp_37_fu_13557_p1 = ap_const_lv4_8)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and not((ap_const_lv1_0 = end_0_phi_fu_5844_p32)) and (tmp_37_fu_13557_p1 = ap_const_lv4_7)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and not((ap_const_lv1_0 = end_0_phi_fu_5844_p32)) and (tmp_37_fu_13557_p1 = ap_const_lv4_6)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and not((ap_const_lv1_0 = end_0_phi_fu_5844_p32)) and (tmp_37_fu_13557_p1 = ap_const_lv4_5)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and not((ap_const_lv1_0 = end_0_phi_fu_5844_p32)) and (tmp_37_fu_13557_p1 = ap_const_lv4_4)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and not((ap_const_lv1_0 = end_0_phi_fu_5844_p32)) and (tmp_37_fu_13557_p1 = ap_const_lv4_3)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and not((ap_const_lv1_0 = end_0_phi_fu_5844_p32)) and (tmp_37_fu_13557_p1 = ap_const_lv4_2)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and not((ap_const_lv1_0 = end_0_phi_fu_5844_p32)) and (tmp_37_fu_13557_p1 = ap_const_lv4_1)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and not((ap_const_lv1_0 = end_0_phi_fu_5844_p32)) and (tmp_37_fu_13557_p1 = ap_const_lv4_0)))) then
end_string_13_5_reg_6947 <= end_string_13_4_reg_5617;
end if;
end if;
end process;
-- end_string_13_6_reg_10702 assign process. --
end_string_13_6_reg_10702_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ST_st30_fsm_29 = ap_CS_fsm) and not((ap_const_lv1_0 = end_0_reg_5841)))) then
end_string_13_6_reg_10702 <= end_string_13_5_reg_6947;
elsif ((((ap_ST_st22_fsm_21 = ap_CS_fsm) and not((tmp_37_reg_14631 = ap_const_lv4_E)) and not((tmp_37_reg_14631 = ap_const_lv4_D)) and not((tmp_37_reg_14631 = ap_const_lv4_C)) and not((tmp_37_reg_14631 = ap_const_lv4_B)) and not((tmp_37_reg_14631 = ap_const_lv4_A)) and not((tmp_37_reg_14631 = ap_const_lv4_9)) and not((tmp_37_reg_14631 = ap_const_lv4_8)) and not((tmp_37_reg_14631 = ap_const_lv4_7)) and not((tmp_37_reg_14631 = ap_const_lv4_6)) and not((tmp_37_reg_14631 = ap_const_lv4_5)) and not((tmp_37_reg_14631 = ap_const_lv4_4)) and not((tmp_37_reg_14631 = ap_const_lv4_3)) and not((tmp_37_reg_14631 = ap_const_lv4_2)) and not((tmp_37_reg_14631 = ap_const_lv4_1)) and not((tmp_37_reg_14631 = ap_const_lv4_0))) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_E)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_D)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_C)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_B)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_A)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_9)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_8)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_7)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_6)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_5)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_4)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_3)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_2)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_1)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_0)))) then
end_string_13_6_reg_10702 <= end_string_13_4_reg_5617;
end if;
end if;
end process;
-- end_string_14_2_reg_1402 assign process. --
end_string_14_2_reg_1402_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ST_st2_fsm_1 = ap_CS_fsm) and not((ap_const_lv1_0 = exitcond3_fu_12991_p2)))) then
end_string_14_2_reg_1402 <= end_string_14_fu_208;
elsif (((ap_ST_st44_fsm_43 = ap_CS_fsm) and not((ap_const_lv1_0 = exitcond_fu_13718_p2)) and not((ap_const_lv1_0 = all_end_phi_fu_12651_p36)))) then
end_string_14_2_reg_1402 <= end_string_14_4_reg_5602;
end if;
end if;
end process;
-- end_string_14_3_reg_4446 assign process. --
end_string_14_3_reg_4446_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ST_st44_fsm_43 = ap_CS_fsm) and not((ap_const_lv1_0 = exitcond_fu_13718_p2)) and (ap_const_lv1_0 = all_end_phi_fu_12651_p36))) then
end_string_14_3_reg_4446 <= end_string_14_4_reg_5602;
elsif (((ap_ST_st8_fsm_7 = ap_CS_fsm) and not((exitcond2_fu_13247_p2 = ap_const_lv1_0)))) then
end_string_14_3_reg_4446 <= end_string_14_2_reg_1402;
end if;
end if;
end process;
-- end_string_14_4_reg_5602 assign process. --
end_string_14_4_reg_5602_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ST_st43_fsm_42 = ap_CS_fsm) or ((ap_ST_st32_fsm_31 = ap_CS_fsm) and ((not((ap_const_lv1_0 = end_load_3_phi_phi_fu_11584_p32)) and (ap_const_lv1_0 = brmerge_demorgan_reg_14680)) or (not((ap_const_lv1_0 = end_load_3_phi_phi_fu_11584_p32)) and not((ap_const_lv1_0 = tmp1_fu_13626_p2))))))) then
end_string_14_4_reg_5602 <= end_string_14_6_reg_10643;
elsif ((ap_ST_st18_fsm_17 = ap_CS_fsm)) then
end_string_14_4_reg_5602 <= end_string_14_3_reg_4446;
end if;
end if;
end process;
-- end_string_14_5_reg_6893 assign process. --
end_string_14_5_reg_6893_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and not((ap_const_lv1_0 = end_0_phi_fu_5844_p32)) and (tmp_37_fu_13557_p1 = ap_const_lv4_E))) then
end_string_14_5_reg_6893 <= end_string_0_phi_fu_6831_p4;
elsif ((((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and not((ap_const_lv1_0 = end_0_phi_fu_5844_p32))) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and not((ap_const_lv1_0 = end_0_phi_fu_5844_p32)) and (tmp_37_fu_13557_p1 = ap_const_lv4_C)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and not((ap_const_lv1_0 = end_0_phi_fu_5844_p32)) and (tmp_37_fu_13557_p1 = ap_const_lv4_B)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and not((ap_const_lv1_0 = end_0_phi_fu_5844_p32)) and (tmp_37_fu_13557_p1 = ap_const_lv4_A)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and not((ap_const_lv1_0 = end_0_phi_fu_5844_p32)) and (tmp_37_fu_13557_p1 = ap_const_lv4_9)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and not((ap_const_lv1_0 = end_0_phi_fu_5844_p32)) and (tmp_37_fu_13557_p1 = ap_const_lv4_8)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and not((ap_const_lv1_0 = end_0_phi_fu_5844_p32)) and (tmp_37_fu_13557_p1 = ap_const_lv4_7)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and not((ap_const_lv1_0 = end_0_phi_fu_5844_p32)) and (tmp_37_fu_13557_p1 = ap_const_lv4_6)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and not((ap_const_lv1_0 = end_0_phi_fu_5844_p32)) and (tmp_37_fu_13557_p1 = ap_const_lv4_5)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and not((ap_const_lv1_0 = end_0_phi_fu_5844_p32)) and (tmp_37_fu_13557_p1 = ap_const_lv4_4)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and not((ap_const_lv1_0 = end_0_phi_fu_5844_p32)) and (tmp_37_fu_13557_p1 = ap_const_lv4_3)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and not((ap_const_lv1_0 = end_0_phi_fu_5844_p32)) and (tmp_37_fu_13557_p1 = ap_const_lv4_2)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and not((ap_const_lv1_0 = end_0_phi_fu_5844_p32)) and (tmp_37_fu_13557_p1 = ap_const_lv4_1)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and not((ap_const_lv1_0 = end_0_phi_fu_5844_p32)) and (tmp_37_fu_13557_p1 = ap_const_lv4_0)))) then
end_string_14_5_reg_6893 <= end_string_14_4_reg_5602;
end if;
end if;
end process;
-- end_string_14_6_reg_10643 assign process. --
end_string_14_6_reg_10643_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ST_st30_fsm_29 = ap_CS_fsm) and not((ap_const_lv1_0 = end_0_reg_5841)))) then
end_string_14_6_reg_10643 <= end_string_14_5_reg_6893;
elsif ((((ap_ST_st22_fsm_21 = ap_CS_fsm) and not((tmp_37_reg_14631 = ap_const_lv4_E)) and not((tmp_37_reg_14631 = ap_const_lv4_D)) and not((tmp_37_reg_14631 = ap_const_lv4_C)) and not((tmp_37_reg_14631 = ap_const_lv4_B)) and not((tmp_37_reg_14631 = ap_const_lv4_A)) and not((tmp_37_reg_14631 = ap_const_lv4_9)) and not((tmp_37_reg_14631 = ap_const_lv4_8)) and not((tmp_37_reg_14631 = ap_const_lv4_7)) and not((tmp_37_reg_14631 = ap_const_lv4_6)) and not((tmp_37_reg_14631 = ap_const_lv4_5)) and not((tmp_37_reg_14631 = ap_const_lv4_4)) and not((tmp_37_reg_14631 = ap_const_lv4_3)) and not((tmp_37_reg_14631 = ap_const_lv4_2)) and not((tmp_37_reg_14631 = ap_const_lv4_1)) and not((tmp_37_reg_14631 = ap_const_lv4_0))) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_E)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_D)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_C)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_B)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_A)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_9)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_8)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_7)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_6)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_5)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_4)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_3)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_2)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_1)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_0)))) then
end_string_14_6_reg_10643 <= end_string_14_4_reg_5602;
end if;
end if;
end process;
-- end_string_15_2_reg_1392 assign process. --
end_string_15_2_reg_1392_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ST_st2_fsm_1 = ap_CS_fsm) and not((ap_const_lv1_0 = exitcond3_fu_12991_p2)))) then
end_string_15_2_reg_1392 <= end_string_s_fu_212;
elsif (((ap_ST_st44_fsm_43 = ap_CS_fsm) and not((ap_const_lv1_0 = exitcond_fu_13718_p2)) and not((ap_const_lv1_0 = all_end_phi_fu_12651_p36)))) then
end_string_15_2_reg_1392 <= end_string_15_4_reg_5587;
end if;
end if;
end process;
-- end_string_15_3_reg_4435 assign process. --
end_string_15_3_reg_4435_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ST_st44_fsm_43 = ap_CS_fsm) and not((ap_const_lv1_0 = exitcond_fu_13718_p2)) and (ap_const_lv1_0 = all_end_phi_fu_12651_p36))) then
end_string_15_3_reg_4435 <= end_string_15_4_reg_5587;
elsif (((ap_ST_st8_fsm_7 = ap_CS_fsm) and not((exitcond2_fu_13247_p2 = ap_const_lv1_0)))) then
end_string_15_3_reg_4435 <= end_string_15_2_reg_1392;
end if;
end if;
end process;
-- end_string_15_4_reg_5587 assign process. --
end_string_15_4_reg_5587_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ST_st43_fsm_42 = ap_CS_fsm) or ((ap_ST_st32_fsm_31 = ap_CS_fsm) and ((not((ap_const_lv1_0 = end_load_3_phi_phi_fu_11584_p32)) and (ap_const_lv1_0 = brmerge_demorgan_reg_14680)) or (not((ap_const_lv1_0 = end_load_3_phi_phi_fu_11584_p32)) and not((ap_const_lv1_0 = tmp1_fu_13626_p2))))))) then
end_string_15_4_reg_5587 <= end_string_15_6_reg_10584;
elsif ((ap_ST_st18_fsm_17 = ap_CS_fsm)) then
end_string_15_4_reg_5587 <= end_string_15_3_reg_4435;
end if;
end if;
end process;
-- end_string_15_5_reg_6839 assign process. --
end_string_15_5_reg_6839_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and not((ap_const_lv1_0 = end_0_phi_fu_5844_p32)) and (tmp_37_fu_13557_p1 = ap_const_lv4_E)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and not((ap_const_lv1_0 = end_0_phi_fu_5844_p32)) and (tmp_37_fu_13557_p1 = ap_const_lv4_D)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and not((ap_const_lv1_0 = end_0_phi_fu_5844_p32)) and (tmp_37_fu_13557_p1 = ap_const_lv4_C)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and not((ap_const_lv1_0 = end_0_phi_fu_5844_p32)) and (tmp_37_fu_13557_p1 = ap_const_lv4_B)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and not((ap_const_lv1_0 = end_0_phi_fu_5844_p32)) and (tmp_37_fu_13557_p1 = ap_const_lv4_A)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and not((ap_const_lv1_0 = end_0_phi_fu_5844_p32)) and (tmp_37_fu_13557_p1 = ap_const_lv4_9)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and not((ap_const_lv1_0 = end_0_phi_fu_5844_p32)) and (tmp_37_fu_13557_p1 = ap_const_lv4_8)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and not((ap_const_lv1_0 = end_0_phi_fu_5844_p32)) and (tmp_37_fu_13557_p1 = ap_const_lv4_7)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and not((ap_const_lv1_0 = end_0_phi_fu_5844_p32)) and (tmp_37_fu_13557_p1 = ap_const_lv4_6)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and not((ap_const_lv1_0 = end_0_phi_fu_5844_p32)) and (tmp_37_fu_13557_p1 = ap_const_lv4_5)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and not((ap_const_lv1_0 = end_0_phi_fu_5844_p32)) and (tmp_37_fu_13557_p1 = ap_const_lv4_4)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and not((ap_const_lv1_0 = end_0_phi_fu_5844_p32)) and (tmp_37_fu_13557_p1 = ap_const_lv4_3)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and not((ap_const_lv1_0 = end_0_phi_fu_5844_p32)) and (tmp_37_fu_13557_p1 = ap_const_lv4_2)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and not((ap_const_lv1_0 = end_0_phi_fu_5844_p32)) and (tmp_37_fu_13557_p1 = ap_const_lv4_1)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and not((ap_const_lv1_0 = end_0_phi_fu_5844_p32)) and (tmp_37_fu_13557_p1 = ap_const_lv4_0)))) then
end_string_15_5_reg_6839 <= end_string_15_4_reg_5587;
elsif (((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and not((ap_const_lv1_0 = end_0_phi_fu_5844_p32)))) then
end_string_15_5_reg_6839 <= end_string_0_phi_fu_6831_p4;
end if;
end if;
end process;
-- end_string_15_6_reg_10584 assign process. --
end_string_15_6_reg_10584_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ST_st30_fsm_29 = ap_CS_fsm) and not((ap_const_lv1_0 = end_0_reg_5841)))) then
end_string_15_6_reg_10584 <= end_string_15_5_reg_6839;
elsif ((((ap_ST_st22_fsm_21 = ap_CS_fsm) and not((tmp_37_reg_14631 = ap_const_lv4_E)) and not((tmp_37_reg_14631 = ap_const_lv4_D)) and not((tmp_37_reg_14631 = ap_const_lv4_C)) and not((tmp_37_reg_14631 = ap_const_lv4_B)) and not((tmp_37_reg_14631 = ap_const_lv4_A)) and not((tmp_37_reg_14631 = ap_const_lv4_9)) and not((tmp_37_reg_14631 = ap_const_lv4_8)) and not((tmp_37_reg_14631 = ap_const_lv4_7)) and not((tmp_37_reg_14631 = ap_const_lv4_6)) and not((tmp_37_reg_14631 = ap_const_lv4_5)) and not((tmp_37_reg_14631 = ap_const_lv4_4)) and not((tmp_37_reg_14631 = ap_const_lv4_3)) and not((tmp_37_reg_14631 = ap_const_lv4_2)) and not((tmp_37_reg_14631 = ap_const_lv4_1)) and not((tmp_37_reg_14631 = ap_const_lv4_0))) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_E)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_D)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_C)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_B)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_A)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_9)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_8)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_7)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_6)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_5)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_4)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_3)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_2)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_1)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_0)))) then
end_string_15_6_reg_10584 <= end_string_15_4_reg_5587;
end if;
end if;
end process;
-- end_string_1_2_reg_1532 assign process. --
end_string_1_2_reg_1532_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ST_st2_fsm_1 = ap_CS_fsm) and not((ap_const_lv1_0 = exitcond3_fu_12991_p2)))) then
end_string_1_2_reg_1532 <= end_string_1_fu_156;
elsif (((ap_ST_st44_fsm_43 = ap_CS_fsm) and not((ap_const_lv1_0 = exitcond_fu_13718_p2)) and not((ap_const_lv1_0 = all_end_phi_fu_12651_p36)))) then
end_string_1_2_reg_1532 <= end_string_1_4_reg_5797;
end if;
end if;
end process;
-- end_string_1_3_reg_4589 assign process. --
end_string_1_3_reg_4589_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ST_st44_fsm_43 = ap_CS_fsm) and not((ap_const_lv1_0 = exitcond_fu_13718_p2)) and (ap_const_lv1_0 = all_end_phi_fu_12651_p36))) then
end_string_1_3_reg_4589 <= end_string_1_4_reg_5797;
elsif (((ap_ST_st8_fsm_7 = ap_CS_fsm) and not((exitcond2_fu_13247_p2 = ap_const_lv1_0)))) then
end_string_1_3_reg_4589 <= end_string_1_2_reg_1532;
end if;
end if;
end process;
-- end_string_1_4_reg_5797 assign process. --
end_string_1_4_reg_5797_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ST_st43_fsm_42 = ap_CS_fsm) or ((ap_ST_st32_fsm_31 = ap_CS_fsm) and ((not((ap_const_lv1_0 = end_load_3_phi_phi_fu_11584_p32)) and (ap_const_lv1_0 = brmerge_demorgan_reg_14680)) or (not((ap_const_lv1_0 = end_load_3_phi_phi_fu_11584_p32)) and not((ap_const_lv1_0 = tmp1_fu_13626_p2))))))) then
end_string_1_4_reg_5797 <= end_string_1_6_reg_11410;
elsif ((ap_ST_st18_fsm_17 = ap_CS_fsm)) then
end_string_1_4_reg_5797 <= end_string_1_3_reg_4589;
end if;
end if;
end process;
-- end_string_1_5_reg_7595 assign process. --
end_string_1_5_reg_7595_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and not((ap_const_lv1_0 = end_0_phi_fu_5844_p32)) and (tmp_37_fu_13557_p1 = ap_const_lv4_1))) then
end_string_1_5_reg_7595 <= end_string_0_phi_fu_6831_p4;
elsif ((((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and not((ap_const_lv1_0 = end_0_phi_fu_5844_p32))) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and not((ap_const_lv1_0 = end_0_phi_fu_5844_p32)) and (tmp_37_fu_13557_p1 = ap_const_lv4_D)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and not((ap_const_lv1_0 = end_0_phi_fu_5844_p32)) and (tmp_37_fu_13557_p1 = ap_const_lv4_C)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and not((ap_const_lv1_0 = end_0_phi_fu_5844_p32)) and (tmp_37_fu_13557_p1 = ap_const_lv4_B)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and not((ap_const_lv1_0 = end_0_phi_fu_5844_p32)) and (tmp_37_fu_13557_p1 = ap_const_lv4_A)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and not((ap_const_lv1_0 = end_0_phi_fu_5844_p32)) and (tmp_37_fu_13557_p1 = ap_const_lv4_9)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and not((ap_const_lv1_0 = end_0_phi_fu_5844_p32)) and (tmp_37_fu_13557_p1 = ap_const_lv4_8)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and not((ap_const_lv1_0 = end_0_phi_fu_5844_p32)) and (tmp_37_fu_13557_p1 = ap_const_lv4_7)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and not((ap_const_lv1_0 = end_0_phi_fu_5844_p32)) and (tmp_37_fu_13557_p1 = ap_const_lv4_6)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and not((ap_const_lv1_0 = end_0_phi_fu_5844_p32)) and (tmp_37_fu_13557_p1 = ap_const_lv4_5)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and not((ap_const_lv1_0 = end_0_phi_fu_5844_p32)) and (tmp_37_fu_13557_p1 = ap_const_lv4_4)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and not((ap_const_lv1_0 = end_0_phi_fu_5844_p32)) and (tmp_37_fu_13557_p1 = ap_const_lv4_3)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and not((ap_const_lv1_0 = end_0_phi_fu_5844_p32)) and (tmp_37_fu_13557_p1 = ap_const_lv4_2)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and not((ap_const_lv1_0 = end_0_phi_fu_5844_p32)) and (tmp_37_fu_13557_p1 = ap_const_lv4_0)))) then
end_string_1_5_reg_7595 <= end_string_1_4_reg_5797;
end if;
end if;
end process;
-- end_string_1_6_reg_11410 assign process. --
end_string_1_6_reg_11410_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ST_st30_fsm_29 = ap_CS_fsm) and not((ap_const_lv1_0 = end_0_reg_5841)))) then
end_string_1_6_reg_11410 <= end_string_1_5_reg_7595;
elsif ((((ap_ST_st22_fsm_21 = ap_CS_fsm) and not((tmp_37_reg_14631 = ap_const_lv4_E)) and not((tmp_37_reg_14631 = ap_const_lv4_D)) and not((tmp_37_reg_14631 = ap_const_lv4_C)) and not((tmp_37_reg_14631 = ap_const_lv4_B)) and not((tmp_37_reg_14631 = ap_const_lv4_A)) and not((tmp_37_reg_14631 = ap_const_lv4_9)) and not((tmp_37_reg_14631 = ap_const_lv4_8)) and not((tmp_37_reg_14631 = ap_const_lv4_7)) and not((tmp_37_reg_14631 = ap_const_lv4_6)) and not((tmp_37_reg_14631 = ap_const_lv4_5)) and not((tmp_37_reg_14631 = ap_const_lv4_4)) and not((tmp_37_reg_14631 = ap_const_lv4_3)) and not((tmp_37_reg_14631 = ap_const_lv4_2)) and not((tmp_37_reg_14631 = ap_const_lv4_1)) and not((tmp_37_reg_14631 = ap_const_lv4_0))) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_E)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_D)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_C)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_B)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_A)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_9)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_8)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_7)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_6)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_5)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_4)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_3)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_2)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_1)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_0)))) then
end_string_1_6_reg_11410 <= end_string_1_4_reg_5797;
end if;
end if;
end process;
-- end_string_2_2_reg_1522 assign process. --
end_string_2_2_reg_1522_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ST_st2_fsm_1 = ap_CS_fsm) and not((ap_const_lv1_0 = exitcond3_fu_12991_p2)))) then
end_string_2_2_reg_1522 <= end_string_2_fu_160;
elsif (((ap_ST_st44_fsm_43 = ap_CS_fsm) and not((ap_const_lv1_0 = exitcond_fu_13718_p2)) and not((ap_const_lv1_0 = all_end_phi_fu_12651_p36)))) then
end_string_2_2_reg_1522 <= end_string_2_4_reg_5782;
end if;
end if;
end process;
-- end_string_2_3_reg_4578 assign process. --
end_string_2_3_reg_4578_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ST_st44_fsm_43 = ap_CS_fsm) and not((ap_const_lv1_0 = exitcond_fu_13718_p2)) and (ap_const_lv1_0 = all_end_phi_fu_12651_p36))) then
end_string_2_3_reg_4578 <= end_string_2_4_reg_5782;
elsif (((ap_ST_st8_fsm_7 = ap_CS_fsm) and not((exitcond2_fu_13247_p2 = ap_const_lv1_0)))) then
end_string_2_3_reg_4578 <= end_string_2_2_reg_1522;
end if;
end if;
end process;
-- end_string_2_4_reg_5782 assign process. --
end_string_2_4_reg_5782_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ST_st43_fsm_42 = ap_CS_fsm) or ((ap_ST_st32_fsm_31 = ap_CS_fsm) and ((not((ap_const_lv1_0 = end_load_3_phi_phi_fu_11584_p32)) and (ap_const_lv1_0 = brmerge_demorgan_reg_14680)) or (not((ap_const_lv1_0 = end_load_3_phi_phi_fu_11584_p32)) and not((ap_const_lv1_0 = tmp1_fu_13626_p2))))))) then
end_string_2_4_reg_5782 <= end_string_2_6_reg_11351;
elsif ((ap_ST_st18_fsm_17 = ap_CS_fsm)) then
end_string_2_4_reg_5782 <= end_string_2_3_reg_4578;
end if;
end if;
end process;
-- end_string_2_5_reg_7541 assign process. --
end_string_2_5_reg_7541_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and not((ap_const_lv1_0 = end_0_phi_fu_5844_p32)) and (tmp_37_fu_13557_p1 = ap_const_lv4_2))) then
end_string_2_5_reg_7541 <= end_string_0_phi_fu_6831_p4;
elsif ((((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and not((ap_const_lv1_0 = end_0_phi_fu_5844_p32))) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and not((ap_const_lv1_0 = end_0_phi_fu_5844_p32)) and (tmp_37_fu_13557_p1 = ap_const_lv4_D)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and not((ap_const_lv1_0 = end_0_phi_fu_5844_p32)) and (tmp_37_fu_13557_p1 = ap_const_lv4_C)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and not((ap_const_lv1_0 = end_0_phi_fu_5844_p32)) and (tmp_37_fu_13557_p1 = ap_const_lv4_B)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and not((ap_const_lv1_0 = end_0_phi_fu_5844_p32)) and (tmp_37_fu_13557_p1 = ap_const_lv4_A)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and not((ap_const_lv1_0 = end_0_phi_fu_5844_p32)) and (tmp_37_fu_13557_p1 = ap_const_lv4_9)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and not((ap_const_lv1_0 = end_0_phi_fu_5844_p32)) and (tmp_37_fu_13557_p1 = ap_const_lv4_8)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and not((ap_const_lv1_0 = end_0_phi_fu_5844_p32)) and (tmp_37_fu_13557_p1 = ap_const_lv4_7)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and not((ap_const_lv1_0 = end_0_phi_fu_5844_p32)) and (tmp_37_fu_13557_p1 = ap_const_lv4_6)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and not((ap_const_lv1_0 = end_0_phi_fu_5844_p32)) and (tmp_37_fu_13557_p1 = ap_const_lv4_5)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and not((ap_const_lv1_0 = end_0_phi_fu_5844_p32)) and (tmp_37_fu_13557_p1 = ap_const_lv4_4)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and not((ap_const_lv1_0 = end_0_phi_fu_5844_p32)) and (tmp_37_fu_13557_p1 = ap_const_lv4_3)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and not((ap_const_lv1_0 = end_0_phi_fu_5844_p32)) and (tmp_37_fu_13557_p1 = ap_const_lv4_1)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and not((ap_const_lv1_0 = end_0_phi_fu_5844_p32)) and (tmp_37_fu_13557_p1 = ap_const_lv4_0)))) then
end_string_2_5_reg_7541 <= end_string_2_4_reg_5782;
end if;
end if;
end process;
-- end_string_2_6_reg_11351 assign process. --
end_string_2_6_reg_11351_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ST_st30_fsm_29 = ap_CS_fsm) and not((ap_const_lv1_0 = end_0_reg_5841)))) then
end_string_2_6_reg_11351 <= end_string_2_5_reg_7541;
elsif ((((ap_ST_st22_fsm_21 = ap_CS_fsm) and not((tmp_37_reg_14631 = ap_const_lv4_E)) and not((tmp_37_reg_14631 = ap_const_lv4_D)) and not((tmp_37_reg_14631 = ap_const_lv4_C)) and not((tmp_37_reg_14631 = ap_const_lv4_B)) and not((tmp_37_reg_14631 = ap_const_lv4_A)) and not((tmp_37_reg_14631 = ap_const_lv4_9)) and not((tmp_37_reg_14631 = ap_const_lv4_8)) and not((tmp_37_reg_14631 = ap_const_lv4_7)) and not((tmp_37_reg_14631 = ap_const_lv4_6)) and not((tmp_37_reg_14631 = ap_const_lv4_5)) and not((tmp_37_reg_14631 = ap_const_lv4_4)) and not((tmp_37_reg_14631 = ap_const_lv4_3)) and not((tmp_37_reg_14631 = ap_const_lv4_2)) and not((tmp_37_reg_14631 = ap_const_lv4_1)) and not((tmp_37_reg_14631 = ap_const_lv4_0))) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_E)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_D)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_C)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_B)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_A)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_9)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_8)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_7)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_6)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_5)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_4)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_3)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_2)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_1)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_0)))) then
end_string_2_6_reg_11351 <= end_string_2_4_reg_5782;
end if;
end if;
end process;
-- end_string_3_2_reg_1512 assign process. --
end_string_3_2_reg_1512_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ST_st2_fsm_1 = ap_CS_fsm) and not((ap_const_lv1_0 = exitcond3_fu_12991_p2)))) then
end_string_3_2_reg_1512 <= end_string_3_fu_164;
elsif (((ap_ST_st44_fsm_43 = ap_CS_fsm) and not((ap_const_lv1_0 = exitcond_fu_13718_p2)) and not((ap_const_lv1_0 = all_end_phi_fu_12651_p36)))) then
end_string_3_2_reg_1512 <= end_string_3_4_reg_5767;
end if;
end if;
end process;
-- end_string_3_3_reg_4567 assign process. --
end_string_3_3_reg_4567_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ST_st44_fsm_43 = ap_CS_fsm) and not((ap_const_lv1_0 = exitcond_fu_13718_p2)) and (ap_const_lv1_0 = all_end_phi_fu_12651_p36))) then
end_string_3_3_reg_4567 <= end_string_3_4_reg_5767;
elsif (((ap_ST_st8_fsm_7 = ap_CS_fsm) and not((exitcond2_fu_13247_p2 = ap_const_lv1_0)))) then
end_string_3_3_reg_4567 <= end_string_3_2_reg_1512;
end if;
end if;
end process;
-- end_string_3_4_reg_5767 assign process. --
end_string_3_4_reg_5767_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ST_st43_fsm_42 = ap_CS_fsm) or ((ap_ST_st32_fsm_31 = ap_CS_fsm) and ((not((ap_const_lv1_0 = end_load_3_phi_phi_fu_11584_p32)) and (ap_const_lv1_0 = brmerge_demorgan_reg_14680)) or (not((ap_const_lv1_0 = end_load_3_phi_phi_fu_11584_p32)) and not((ap_const_lv1_0 = tmp1_fu_13626_p2))))))) then
end_string_3_4_reg_5767 <= end_string_3_6_reg_11292;
elsif ((ap_ST_st18_fsm_17 = ap_CS_fsm)) then
end_string_3_4_reg_5767 <= end_string_3_3_reg_4567;
end if;
end if;
end process;
-- end_string_3_5_reg_7487 assign process. --
end_string_3_5_reg_7487_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and not((ap_const_lv1_0 = end_0_phi_fu_5844_p32)) and (tmp_37_fu_13557_p1 = ap_const_lv4_3))) then
end_string_3_5_reg_7487 <= end_string_0_phi_fu_6831_p4;
elsif ((((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and not((ap_const_lv1_0 = end_0_phi_fu_5844_p32))) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and not((ap_const_lv1_0 = end_0_phi_fu_5844_p32)) and (tmp_37_fu_13557_p1 = ap_const_lv4_D)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and not((ap_const_lv1_0 = end_0_phi_fu_5844_p32)) and (tmp_37_fu_13557_p1 = ap_const_lv4_C)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and not((ap_const_lv1_0 = end_0_phi_fu_5844_p32)) and (tmp_37_fu_13557_p1 = ap_const_lv4_B)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and not((ap_const_lv1_0 = end_0_phi_fu_5844_p32)) and (tmp_37_fu_13557_p1 = ap_const_lv4_A)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and not((ap_const_lv1_0 = end_0_phi_fu_5844_p32)) and (tmp_37_fu_13557_p1 = ap_const_lv4_9)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and not((ap_const_lv1_0 = end_0_phi_fu_5844_p32)) and (tmp_37_fu_13557_p1 = ap_const_lv4_8)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and not((ap_const_lv1_0 = end_0_phi_fu_5844_p32)) and (tmp_37_fu_13557_p1 = ap_const_lv4_7)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and not((ap_const_lv1_0 = end_0_phi_fu_5844_p32)) and (tmp_37_fu_13557_p1 = ap_const_lv4_6)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and not((ap_const_lv1_0 = end_0_phi_fu_5844_p32)) and (tmp_37_fu_13557_p1 = ap_const_lv4_5)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and not((ap_const_lv1_0 = end_0_phi_fu_5844_p32)) and (tmp_37_fu_13557_p1 = ap_const_lv4_4)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and not((ap_const_lv1_0 = end_0_phi_fu_5844_p32)) and (tmp_37_fu_13557_p1 = ap_const_lv4_2)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and not((ap_const_lv1_0 = end_0_phi_fu_5844_p32)) and (tmp_37_fu_13557_p1 = ap_const_lv4_1)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and not((ap_const_lv1_0 = end_0_phi_fu_5844_p32)) and (tmp_37_fu_13557_p1 = ap_const_lv4_0)))) then
end_string_3_5_reg_7487 <= end_string_3_4_reg_5767;
end if;
end if;
end process;
-- end_string_3_6_reg_11292 assign process. --
end_string_3_6_reg_11292_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ST_st30_fsm_29 = ap_CS_fsm) and not((ap_const_lv1_0 = end_0_reg_5841)))) then
end_string_3_6_reg_11292 <= end_string_3_5_reg_7487;
elsif ((((ap_ST_st22_fsm_21 = ap_CS_fsm) and not((tmp_37_reg_14631 = ap_const_lv4_E)) and not((tmp_37_reg_14631 = ap_const_lv4_D)) and not((tmp_37_reg_14631 = ap_const_lv4_C)) and not((tmp_37_reg_14631 = ap_const_lv4_B)) and not((tmp_37_reg_14631 = ap_const_lv4_A)) and not((tmp_37_reg_14631 = ap_const_lv4_9)) and not((tmp_37_reg_14631 = ap_const_lv4_8)) and not((tmp_37_reg_14631 = ap_const_lv4_7)) and not((tmp_37_reg_14631 = ap_const_lv4_6)) and not((tmp_37_reg_14631 = ap_const_lv4_5)) and not((tmp_37_reg_14631 = ap_const_lv4_4)) and not((tmp_37_reg_14631 = ap_const_lv4_3)) and not((tmp_37_reg_14631 = ap_const_lv4_2)) and not((tmp_37_reg_14631 = ap_const_lv4_1)) and not((tmp_37_reg_14631 = ap_const_lv4_0))) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_E)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_D)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_C)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_B)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_A)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_9)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_8)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_7)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_6)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_5)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_4)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_3)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_2)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_1)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_0)))) then
end_string_3_6_reg_11292 <= end_string_3_4_reg_5767;
end if;
end if;
end process;
-- end_string_4_2_reg_1502 assign process. --
end_string_4_2_reg_1502_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ST_st2_fsm_1 = ap_CS_fsm) and not((ap_const_lv1_0 = exitcond3_fu_12991_p2)))) then
end_string_4_2_reg_1502 <= end_string_4_fu_168;
elsif (((ap_ST_st44_fsm_43 = ap_CS_fsm) and not((ap_const_lv1_0 = exitcond_fu_13718_p2)) and not((ap_const_lv1_0 = all_end_phi_fu_12651_p36)))) then
end_string_4_2_reg_1502 <= end_string_4_4_reg_5752;
end if;
end if;
end process;
-- end_string_4_3_reg_4556 assign process. --
end_string_4_3_reg_4556_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ST_st44_fsm_43 = ap_CS_fsm) and not((ap_const_lv1_0 = exitcond_fu_13718_p2)) and (ap_const_lv1_0 = all_end_phi_fu_12651_p36))) then
end_string_4_3_reg_4556 <= end_string_4_4_reg_5752;
elsif (((ap_ST_st8_fsm_7 = ap_CS_fsm) and not((exitcond2_fu_13247_p2 = ap_const_lv1_0)))) then
end_string_4_3_reg_4556 <= end_string_4_2_reg_1502;
end if;
end if;
end process;
-- end_string_4_4_reg_5752 assign process. --
end_string_4_4_reg_5752_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ST_st43_fsm_42 = ap_CS_fsm) or ((ap_ST_st32_fsm_31 = ap_CS_fsm) and ((not((ap_const_lv1_0 = end_load_3_phi_phi_fu_11584_p32)) and (ap_const_lv1_0 = brmerge_demorgan_reg_14680)) or (not((ap_const_lv1_0 = end_load_3_phi_phi_fu_11584_p32)) and not((ap_const_lv1_0 = tmp1_fu_13626_p2))))))) then
end_string_4_4_reg_5752 <= end_string_4_6_reg_11233;
elsif ((ap_ST_st18_fsm_17 = ap_CS_fsm)) then
end_string_4_4_reg_5752 <= end_string_4_3_reg_4556;
end if;
end if;
end process;
-- end_string_4_5_reg_7433 assign process. --
end_string_4_5_reg_7433_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and not((ap_const_lv1_0 = end_0_phi_fu_5844_p32)) and (tmp_37_fu_13557_p1 = ap_const_lv4_4))) then
end_string_4_5_reg_7433 <= end_string_0_phi_fu_6831_p4;
elsif ((((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and not((ap_const_lv1_0 = end_0_phi_fu_5844_p32))) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and not((ap_const_lv1_0 = end_0_phi_fu_5844_p32)) and (tmp_37_fu_13557_p1 = ap_const_lv4_D)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and not((ap_const_lv1_0 = end_0_phi_fu_5844_p32)) and (tmp_37_fu_13557_p1 = ap_const_lv4_C)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and not((ap_const_lv1_0 = end_0_phi_fu_5844_p32)) and (tmp_37_fu_13557_p1 = ap_const_lv4_B)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and not((ap_const_lv1_0 = end_0_phi_fu_5844_p32)) and (tmp_37_fu_13557_p1 = ap_const_lv4_A)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and not((ap_const_lv1_0 = end_0_phi_fu_5844_p32)) and (tmp_37_fu_13557_p1 = ap_const_lv4_9)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and not((ap_const_lv1_0 = end_0_phi_fu_5844_p32)) and (tmp_37_fu_13557_p1 = ap_const_lv4_8)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and not((ap_const_lv1_0 = end_0_phi_fu_5844_p32)) and (tmp_37_fu_13557_p1 = ap_const_lv4_7)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and not((ap_const_lv1_0 = end_0_phi_fu_5844_p32)) and (tmp_37_fu_13557_p1 = ap_const_lv4_6)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and not((ap_const_lv1_0 = end_0_phi_fu_5844_p32)) and (tmp_37_fu_13557_p1 = ap_const_lv4_5)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and not((ap_const_lv1_0 = end_0_phi_fu_5844_p32)) and (tmp_37_fu_13557_p1 = ap_const_lv4_3)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and not((ap_const_lv1_0 = end_0_phi_fu_5844_p32)) and (tmp_37_fu_13557_p1 = ap_const_lv4_2)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and not((ap_const_lv1_0 = end_0_phi_fu_5844_p32)) and (tmp_37_fu_13557_p1 = ap_const_lv4_1)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and not((ap_const_lv1_0 = end_0_phi_fu_5844_p32)) and (tmp_37_fu_13557_p1 = ap_const_lv4_0)))) then
end_string_4_5_reg_7433 <= end_string_4_4_reg_5752;
end if;
end if;
end process;
-- end_string_4_6_reg_11233 assign process. --
end_string_4_6_reg_11233_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ST_st30_fsm_29 = ap_CS_fsm) and not((ap_const_lv1_0 = end_0_reg_5841)))) then
end_string_4_6_reg_11233 <= end_string_4_5_reg_7433;
elsif ((((ap_ST_st22_fsm_21 = ap_CS_fsm) and not((tmp_37_reg_14631 = ap_const_lv4_E)) and not((tmp_37_reg_14631 = ap_const_lv4_D)) and not((tmp_37_reg_14631 = ap_const_lv4_C)) and not((tmp_37_reg_14631 = ap_const_lv4_B)) and not((tmp_37_reg_14631 = ap_const_lv4_A)) and not((tmp_37_reg_14631 = ap_const_lv4_9)) and not((tmp_37_reg_14631 = ap_const_lv4_8)) and not((tmp_37_reg_14631 = ap_const_lv4_7)) and not((tmp_37_reg_14631 = ap_const_lv4_6)) and not((tmp_37_reg_14631 = ap_const_lv4_5)) and not((tmp_37_reg_14631 = ap_const_lv4_4)) and not((tmp_37_reg_14631 = ap_const_lv4_3)) and not((tmp_37_reg_14631 = ap_const_lv4_2)) and not((tmp_37_reg_14631 = ap_const_lv4_1)) and not((tmp_37_reg_14631 = ap_const_lv4_0))) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_E)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_D)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_C)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_B)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_A)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_9)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_8)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_7)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_6)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_5)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_4)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_3)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_2)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_1)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_0)))) then
end_string_4_6_reg_11233 <= end_string_4_4_reg_5752;
end if;
end if;
end process;
-- end_string_5_2_reg_1492 assign process. --
end_string_5_2_reg_1492_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ST_st2_fsm_1 = ap_CS_fsm) and not((ap_const_lv1_0 = exitcond3_fu_12991_p2)))) then
end_string_5_2_reg_1492 <= end_string_5_fu_172;
elsif (((ap_ST_st44_fsm_43 = ap_CS_fsm) and not((ap_const_lv1_0 = exitcond_fu_13718_p2)) and not((ap_const_lv1_0 = all_end_phi_fu_12651_p36)))) then
end_string_5_2_reg_1492 <= end_string_5_4_reg_5737;
end if;
end if;
end process;
-- end_string_5_3_reg_4545 assign process. --
end_string_5_3_reg_4545_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ST_st44_fsm_43 = ap_CS_fsm) and not((ap_const_lv1_0 = exitcond_fu_13718_p2)) and (ap_const_lv1_0 = all_end_phi_fu_12651_p36))) then
end_string_5_3_reg_4545 <= end_string_5_4_reg_5737;
elsif (((ap_ST_st8_fsm_7 = ap_CS_fsm) and not((exitcond2_fu_13247_p2 = ap_const_lv1_0)))) then
end_string_5_3_reg_4545 <= end_string_5_2_reg_1492;
end if;
end if;
end process;
-- end_string_5_4_reg_5737 assign process. --
end_string_5_4_reg_5737_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ST_st43_fsm_42 = ap_CS_fsm) or ((ap_ST_st32_fsm_31 = ap_CS_fsm) and ((not((ap_const_lv1_0 = end_load_3_phi_phi_fu_11584_p32)) and (ap_const_lv1_0 = brmerge_demorgan_reg_14680)) or (not((ap_const_lv1_0 = end_load_3_phi_phi_fu_11584_p32)) and not((ap_const_lv1_0 = tmp1_fu_13626_p2))))))) then
end_string_5_4_reg_5737 <= end_string_5_6_reg_11174;
elsif ((ap_ST_st18_fsm_17 = ap_CS_fsm)) then
end_string_5_4_reg_5737 <= end_string_5_3_reg_4545;
end if;
end if;
end process;
-- end_string_5_5_reg_7379 assign process. --
end_string_5_5_reg_7379_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and not((ap_const_lv1_0 = end_0_phi_fu_5844_p32)) and (tmp_37_fu_13557_p1 = ap_const_lv4_5))) then
end_string_5_5_reg_7379 <= end_string_0_phi_fu_6831_p4;
elsif ((((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and not((ap_const_lv1_0 = end_0_phi_fu_5844_p32))) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and not((ap_const_lv1_0 = end_0_phi_fu_5844_p32)) and (tmp_37_fu_13557_p1 = ap_const_lv4_D)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and not((ap_const_lv1_0 = end_0_phi_fu_5844_p32)) and (tmp_37_fu_13557_p1 = ap_const_lv4_C)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and not((ap_const_lv1_0 = end_0_phi_fu_5844_p32)) and (tmp_37_fu_13557_p1 = ap_const_lv4_B)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and not((ap_const_lv1_0 = end_0_phi_fu_5844_p32)) and (tmp_37_fu_13557_p1 = ap_const_lv4_A)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and not((ap_const_lv1_0 = end_0_phi_fu_5844_p32)) and (tmp_37_fu_13557_p1 = ap_const_lv4_9)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and not((ap_const_lv1_0 = end_0_phi_fu_5844_p32)) and (tmp_37_fu_13557_p1 = ap_const_lv4_8)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and not((ap_const_lv1_0 = end_0_phi_fu_5844_p32)) and (tmp_37_fu_13557_p1 = ap_const_lv4_7)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and not((ap_const_lv1_0 = end_0_phi_fu_5844_p32)) and (tmp_37_fu_13557_p1 = ap_const_lv4_6)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and not((ap_const_lv1_0 = end_0_phi_fu_5844_p32)) and (tmp_37_fu_13557_p1 = ap_const_lv4_4)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and not((ap_const_lv1_0 = end_0_phi_fu_5844_p32)) and (tmp_37_fu_13557_p1 = ap_const_lv4_3)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and not((ap_const_lv1_0 = end_0_phi_fu_5844_p32)) and (tmp_37_fu_13557_p1 = ap_const_lv4_2)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and not((ap_const_lv1_0 = end_0_phi_fu_5844_p32)) and (tmp_37_fu_13557_p1 = ap_const_lv4_1)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and not((ap_const_lv1_0 = end_0_phi_fu_5844_p32)) and (tmp_37_fu_13557_p1 = ap_const_lv4_0)))) then
end_string_5_5_reg_7379 <= end_string_5_4_reg_5737;
end if;
end if;
end process;
-- end_string_5_6_reg_11174 assign process. --
end_string_5_6_reg_11174_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ST_st30_fsm_29 = ap_CS_fsm) and not((ap_const_lv1_0 = end_0_reg_5841)))) then
end_string_5_6_reg_11174 <= end_string_5_5_reg_7379;
elsif ((((ap_ST_st22_fsm_21 = ap_CS_fsm) and not((tmp_37_reg_14631 = ap_const_lv4_E)) and not((tmp_37_reg_14631 = ap_const_lv4_D)) and not((tmp_37_reg_14631 = ap_const_lv4_C)) and not((tmp_37_reg_14631 = ap_const_lv4_B)) and not((tmp_37_reg_14631 = ap_const_lv4_A)) and not((tmp_37_reg_14631 = ap_const_lv4_9)) and not((tmp_37_reg_14631 = ap_const_lv4_8)) and not((tmp_37_reg_14631 = ap_const_lv4_7)) and not((tmp_37_reg_14631 = ap_const_lv4_6)) and not((tmp_37_reg_14631 = ap_const_lv4_5)) and not((tmp_37_reg_14631 = ap_const_lv4_4)) and not((tmp_37_reg_14631 = ap_const_lv4_3)) and not((tmp_37_reg_14631 = ap_const_lv4_2)) and not((tmp_37_reg_14631 = ap_const_lv4_1)) and not((tmp_37_reg_14631 = ap_const_lv4_0))) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_E)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_D)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_C)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_B)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_A)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_9)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_8)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_7)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_6)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_5)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_4)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_3)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_2)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_1)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_0)))) then
end_string_5_6_reg_11174 <= end_string_5_4_reg_5737;
end if;
end if;
end process;
-- end_string_6_2_reg_1482 assign process. --
end_string_6_2_reg_1482_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ST_st2_fsm_1 = ap_CS_fsm) and not((ap_const_lv1_0 = exitcond3_fu_12991_p2)))) then
end_string_6_2_reg_1482 <= end_string_6_fu_176;
elsif (((ap_ST_st44_fsm_43 = ap_CS_fsm) and not((ap_const_lv1_0 = exitcond_fu_13718_p2)) and not((ap_const_lv1_0 = all_end_phi_fu_12651_p36)))) then
end_string_6_2_reg_1482 <= end_string_6_4_reg_5722;
end if;
end if;
end process;
-- end_string_6_3_reg_4534 assign process. --
end_string_6_3_reg_4534_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ST_st44_fsm_43 = ap_CS_fsm) and not((ap_const_lv1_0 = exitcond_fu_13718_p2)) and (ap_const_lv1_0 = all_end_phi_fu_12651_p36))) then
end_string_6_3_reg_4534 <= end_string_6_4_reg_5722;
elsif (((ap_ST_st8_fsm_7 = ap_CS_fsm) and not((exitcond2_fu_13247_p2 = ap_const_lv1_0)))) then
end_string_6_3_reg_4534 <= end_string_6_2_reg_1482;
end if;
end if;
end process;
-- end_string_6_4_reg_5722 assign process. --
end_string_6_4_reg_5722_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ST_st43_fsm_42 = ap_CS_fsm) or ((ap_ST_st32_fsm_31 = ap_CS_fsm) and ((not((ap_const_lv1_0 = end_load_3_phi_phi_fu_11584_p32)) and (ap_const_lv1_0 = brmerge_demorgan_reg_14680)) or (not((ap_const_lv1_0 = end_load_3_phi_phi_fu_11584_p32)) and not((ap_const_lv1_0 = tmp1_fu_13626_p2))))))) then
end_string_6_4_reg_5722 <= end_string_6_6_reg_11115;
elsif ((ap_ST_st18_fsm_17 = ap_CS_fsm)) then
end_string_6_4_reg_5722 <= end_string_6_3_reg_4534;
end if;
end if;
end process;
-- end_string_6_5_reg_7325 assign process. --
end_string_6_5_reg_7325_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and not((ap_const_lv1_0 = end_0_phi_fu_5844_p32)) and (tmp_37_fu_13557_p1 = ap_const_lv4_6))) then
end_string_6_5_reg_7325 <= end_string_0_phi_fu_6831_p4;
elsif ((((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and not((ap_const_lv1_0 = end_0_phi_fu_5844_p32))) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and not((ap_const_lv1_0 = end_0_phi_fu_5844_p32)) and (tmp_37_fu_13557_p1 = ap_const_lv4_D)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and not((ap_const_lv1_0 = end_0_phi_fu_5844_p32)) and (tmp_37_fu_13557_p1 = ap_const_lv4_C)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and not((ap_const_lv1_0 = end_0_phi_fu_5844_p32)) and (tmp_37_fu_13557_p1 = ap_const_lv4_B)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and not((ap_const_lv1_0 = end_0_phi_fu_5844_p32)) and (tmp_37_fu_13557_p1 = ap_const_lv4_A)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and not((ap_const_lv1_0 = end_0_phi_fu_5844_p32)) and (tmp_37_fu_13557_p1 = ap_const_lv4_9)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and not((ap_const_lv1_0 = end_0_phi_fu_5844_p32)) and (tmp_37_fu_13557_p1 = ap_const_lv4_8)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and not((ap_const_lv1_0 = end_0_phi_fu_5844_p32)) and (tmp_37_fu_13557_p1 = ap_const_lv4_7)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and not((ap_const_lv1_0 = end_0_phi_fu_5844_p32)) and (tmp_37_fu_13557_p1 = ap_const_lv4_5)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and not((ap_const_lv1_0 = end_0_phi_fu_5844_p32)) and (tmp_37_fu_13557_p1 = ap_const_lv4_4)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and not((ap_const_lv1_0 = end_0_phi_fu_5844_p32)) and (tmp_37_fu_13557_p1 = ap_const_lv4_3)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and not((ap_const_lv1_0 = end_0_phi_fu_5844_p32)) and (tmp_37_fu_13557_p1 = ap_const_lv4_2)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and not((ap_const_lv1_0 = end_0_phi_fu_5844_p32)) and (tmp_37_fu_13557_p1 = ap_const_lv4_1)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and not((ap_const_lv1_0 = end_0_phi_fu_5844_p32)) and (tmp_37_fu_13557_p1 = ap_const_lv4_0)))) then
end_string_6_5_reg_7325 <= end_string_6_4_reg_5722;
end if;
end if;
end process;
-- end_string_6_6_reg_11115 assign process. --
end_string_6_6_reg_11115_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ST_st30_fsm_29 = ap_CS_fsm) and not((ap_const_lv1_0 = end_0_reg_5841)))) then
end_string_6_6_reg_11115 <= end_string_6_5_reg_7325;
elsif ((((ap_ST_st22_fsm_21 = ap_CS_fsm) and not((tmp_37_reg_14631 = ap_const_lv4_E)) and not((tmp_37_reg_14631 = ap_const_lv4_D)) and not((tmp_37_reg_14631 = ap_const_lv4_C)) and not((tmp_37_reg_14631 = ap_const_lv4_B)) and not((tmp_37_reg_14631 = ap_const_lv4_A)) and not((tmp_37_reg_14631 = ap_const_lv4_9)) and not((tmp_37_reg_14631 = ap_const_lv4_8)) and not((tmp_37_reg_14631 = ap_const_lv4_7)) and not((tmp_37_reg_14631 = ap_const_lv4_6)) and not((tmp_37_reg_14631 = ap_const_lv4_5)) and not((tmp_37_reg_14631 = ap_const_lv4_4)) and not((tmp_37_reg_14631 = ap_const_lv4_3)) and not((tmp_37_reg_14631 = ap_const_lv4_2)) and not((tmp_37_reg_14631 = ap_const_lv4_1)) and not((tmp_37_reg_14631 = ap_const_lv4_0))) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_E)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_D)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_C)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_B)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_A)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_9)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_8)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_7)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_6)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_5)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_4)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_3)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_2)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_1)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_0)))) then
end_string_6_6_reg_11115 <= end_string_6_4_reg_5722;
end if;
end if;
end process;
-- end_string_7_2_reg_1472 assign process. --
end_string_7_2_reg_1472_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ST_st2_fsm_1 = ap_CS_fsm) and not((ap_const_lv1_0 = exitcond3_fu_12991_p2)))) then
end_string_7_2_reg_1472 <= end_string_7_fu_180;
elsif (((ap_ST_st44_fsm_43 = ap_CS_fsm) and not((ap_const_lv1_0 = exitcond_fu_13718_p2)) and not((ap_const_lv1_0 = all_end_phi_fu_12651_p36)))) then
end_string_7_2_reg_1472 <= end_string_7_4_reg_5707;
end if;
end if;
end process;
-- end_string_7_3_reg_4523 assign process. --
end_string_7_3_reg_4523_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ST_st44_fsm_43 = ap_CS_fsm) and not((ap_const_lv1_0 = exitcond_fu_13718_p2)) and (ap_const_lv1_0 = all_end_phi_fu_12651_p36))) then
end_string_7_3_reg_4523 <= end_string_7_4_reg_5707;
elsif (((ap_ST_st8_fsm_7 = ap_CS_fsm) and not((exitcond2_fu_13247_p2 = ap_const_lv1_0)))) then
end_string_7_3_reg_4523 <= end_string_7_2_reg_1472;
end if;
end if;
end process;
-- end_string_7_4_reg_5707 assign process. --
end_string_7_4_reg_5707_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ST_st43_fsm_42 = ap_CS_fsm) or ((ap_ST_st32_fsm_31 = ap_CS_fsm) and ((not((ap_const_lv1_0 = end_load_3_phi_phi_fu_11584_p32)) and (ap_const_lv1_0 = brmerge_demorgan_reg_14680)) or (not((ap_const_lv1_0 = end_load_3_phi_phi_fu_11584_p32)) and not((ap_const_lv1_0 = tmp1_fu_13626_p2))))))) then
end_string_7_4_reg_5707 <= end_string_7_6_reg_11056;
elsif ((ap_ST_st18_fsm_17 = ap_CS_fsm)) then
end_string_7_4_reg_5707 <= end_string_7_3_reg_4523;
end if;
end if;
end process;
-- end_string_7_5_reg_7271 assign process. --
end_string_7_5_reg_7271_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and not((ap_const_lv1_0 = end_0_phi_fu_5844_p32)) and (tmp_37_fu_13557_p1 = ap_const_lv4_7))) then
end_string_7_5_reg_7271 <= end_string_0_phi_fu_6831_p4;
elsif ((((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and not((ap_const_lv1_0 = end_0_phi_fu_5844_p32))) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and not((ap_const_lv1_0 = end_0_phi_fu_5844_p32)) and (tmp_37_fu_13557_p1 = ap_const_lv4_D)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and not((ap_const_lv1_0 = end_0_phi_fu_5844_p32)) and (tmp_37_fu_13557_p1 = ap_const_lv4_C)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and not((ap_const_lv1_0 = end_0_phi_fu_5844_p32)) and (tmp_37_fu_13557_p1 = ap_const_lv4_B)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and not((ap_const_lv1_0 = end_0_phi_fu_5844_p32)) and (tmp_37_fu_13557_p1 = ap_const_lv4_A)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and not((ap_const_lv1_0 = end_0_phi_fu_5844_p32)) and (tmp_37_fu_13557_p1 = ap_const_lv4_9)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and not((ap_const_lv1_0 = end_0_phi_fu_5844_p32)) and (tmp_37_fu_13557_p1 = ap_const_lv4_8)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and not((ap_const_lv1_0 = end_0_phi_fu_5844_p32)) and (tmp_37_fu_13557_p1 = ap_const_lv4_6)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and not((ap_const_lv1_0 = end_0_phi_fu_5844_p32)) and (tmp_37_fu_13557_p1 = ap_const_lv4_5)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and not((ap_const_lv1_0 = end_0_phi_fu_5844_p32)) and (tmp_37_fu_13557_p1 = ap_const_lv4_4)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and not((ap_const_lv1_0 = end_0_phi_fu_5844_p32)) and (tmp_37_fu_13557_p1 = ap_const_lv4_3)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and not((ap_const_lv1_0 = end_0_phi_fu_5844_p32)) and (tmp_37_fu_13557_p1 = ap_const_lv4_2)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and not((ap_const_lv1_0 = end_0_phi_fu_5844_p32)) and (tmp_37_fu_13557_p1 = ap_const_lv4_1)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and not((ap_const_lv1_0 = end_0_phi_fu_5844_p32)) and (tmp_37_fu_13557_p1 = ap_const_lv4_0)))) then
end_string_7_5_reg_7271 <= end_string_7_4_reg_5707;
end if;
end if;
end process;
-- end_string_7_6_reg_11056 assign process. --
end_string_7_6_reg_11056_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ST_st30_fsm_29 = ap_CS_fsm) and not((ap_const_lv1_0 = end_0_reg_5841)))) then
end_string_7_6_reg_11056 <= end_string_7_5_reg_7271;
elsif ((((ap_ST_st22_fsm_21 = ap_CS_fsm) and not((tmp_37_reg_14631 = ap_const_lv4_E)) and not((tmp_37_reg_14631 = ap_const_lv4_D)) and not((tmp_37_reg_14631 = ap_const_lv4_C)) and not((tmp_37_reg_14631 = ap_const_lv4_B)) and not((tmp_37_reg_14631 = ap_const_lv4_A)) and not((tmp_37_reg_14631 = ap_const_lv4_9)) and not((tmp_37_reg_14631 = ap_const_lv4_8)) and not((tmp_37_reg_14631 = ap_const_lv4_7)) and not((tmp_37_reg_14631 = ap_const_lv4_6)) and not((tmp_37_reg_14631 = ap_const_lv4_5)) and not((tmp_37_reg_14631 = ap_const_lv4_4)) and not((tmp_37_reg_14631 = ap_const_lv4_3)) and not((tmp_37_reg_14631 = ap_const_lv4_2)) and not((tmp_37_reg_14631 = ap_const_lv4_1)) and not((tmp_37_reg_14631 = ap_const_lv4_0))) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_E)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_D)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_C)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_B)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_A)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_9)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_8)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_7)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_6)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_5)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_4)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_3)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_2)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_1)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_0)))) then
end_string_7_6_reg_11056 <= end_string_7_4_reg_5707;
end if;
end if;
end process;
-- end_string_8_2_reg_1462 assign process. --
end_string_8_2_reg_1462_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ST_st2_fsm_1 = ap_CS_fsm) and not((ap_const_lv1_0 = exitcond3_fu_12991_p2)))) then
end_string_8_2_reg_1462 <= end_string_8_fu_184;
elsif (((ap_ST_st44_fsm_43 = ap_CS_fsm) and not((ap_const_lv1_0 = exitcond_fu_13718_p2)) and not((ap_const_lv1_0 = all_end_phi_fu_12651_p36)))) then
end_string_8_2_reg_1462 <= end_string_8_4_reg_5692;
end if;
end if;
end process;
-- end_string_8_3_reg_4512 assign process. --
end_string_8_3_reg_4512_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ST_st44_fsm_43 = ap_CS_fsm) and not((ap_const_lv1_0 = exitcond_fu_13718_p2)) and (ap_const_lv1_0 = all_end_phi_fu_12651_p36))) then
end_string_8_3_reg_4512 <= end_string_8_4_reg_5692;
elsif (((ap_ST_st8_fsm_7 = ap_CS_fsm) and not((exitcond2_fu_13247_p2 = ap_const_lv1_0)))) then
end_string_8_3_reg_4512 <= end_string_8_2_reg_1462;
end if;
end if;
end process;
-- end_string_8_4_reg_5692 assign process. --
end_string_8_4_reg_5692_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ST_st43_fsm_42 = ap_CS_fsm) or ((ap_ST_st32_fsm_31 = ap_CS_fsm) and ((not((ap_const_lv1_0 = end_load_3_phi_phi_fu_11584_p32)) and (ap_const_lv1_0 = brmerge_demorgan_reg_14680)) or (not((ap_const_lv1_0 = end_load_3_phi_phi_fu_11584_p32)) and not((ap_const_lv1_0 = tmp1_fu_13626_p2))))))) then
end_string_8_4_reg_5692 <= end_string_8_6_reg_10997;
elsif ((ap_ST_st18_fsm_17 = ap_CS_fsm)) then
end_string_8_4_reg_5692 <= end_string_8_3_reg_4512;
end if;
end if;
end process;
-- end_string_8_5_reg_7217 assign process. --
end_string_8_5_reg_7217_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and not((ap_const_lv1_0 = end_0_phi_fu_5844_p32)) and (tmp_37_fu_13557_p1 = ap_const_lv4_8))) then
end_string_8_5_reg_7217 <= end_string_0_phi_fu_6831_p4;
elsif ((((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and not((ap_const_lv1_0 = end_0_phi_fu_5844_p32))) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and not((ap_const_lv1_0 = end_0_phi_fu_5844_p32)) and (tmp_37_fu_13557_p1 = ap_const_lv4_D)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and not((ap_const_lv1_0 = end_0_phi_fu_5844_p32)) and (tmp_37_fu_13557_p1 = ap_const_lv4_C)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and not((ap_const_lv1_0 = end_0_phi_fu_5844_p32)) and (tmp_37_fu_13557_p1 = ap_const_lv4_B)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and not((ap_const_lv1_0 = end_0_phi_fu_5844_p32)) and (tmp_37_fu_13557_p1 = ap_const_lv4_A)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and not((ap_const_lv1_0 = end_0_phi_fu_5844_p32)) and (tmp_37_fu_13557_p1 = ap_const_lv4_9)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and not((ap_const_lv1_0 = end_0_phi_fu_5844_p32)) and (tmp_37_fu_13557_p1 = ap_const_lv4_7)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and not((ap_const_lv1_0 = end_0_phi_fu_5844_p32)) and (tmp_37_fu_13557_p1 = ap_const_lv4_6)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and not((ap_const_lv1_0 = end_0_phi_fu_5844_p32)) and (tmp_37_fu_13557_p1 = ap_const_lv4_5)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and not((ap_const_lv1_0 = end_0_phi_fu_5844_p32)) and (tmp_37_fu_13557_p1 = ap_const_lv4_4)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and not((ap_const_lv1_0 = end_0_phi_fu_5844_p32)) and (tmp_37_fu_13557_p1 = ap_const_lv4_3)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and not((ap_const_lv1_0 = end_0_phi_fu_5844_p32)) and (tmp_37_fu_13557_p1 = ap_const_lv4_2)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and not((ap_const_lv1_0 = end_0_phi_fu_5844_p32)) and (tmp_37_fu_13557_p1 = ap_const_lv4_1)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and not((ap_const_lv1_0 = end_0_phi_fu_5844_p32)) and (tmp_37_fu_13557_p1 = ap_const_lv4_0)))) then
end_string_8_5_reg_7217 <= end_string_8_4_reg_5692;
end if;
end if;
end process;
-- end_string_8_6_reg_10997 assign process. --
end_string_8_6_reg_10997_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ST_st30_fsm_29 = ap_CS_fsm) and not((ap_const_lv1_0 = end_0_reg_5841)))) then
end_string_8_6_reg_10997 <= end_string_8_5_reg_7217;
elsif ((((ap_ST_st22_fsm_21 = ap_CS_fsm) and not((tmp_37_reg_14631 = ap_const_lv4_E)) and not((tmp_37_reg_14631 = ap_const_lv4_D)) and not((tmp_37_reg_14631 = ap_const_lv4_C)) and not((tmp_37_reg_14631 = ap_const_lv4_B)) and not((tmp_37_reg_14631 = ap_const_lv4_A)) and not((tmp_37_reg_14631 = ap_const_lv4_9)) and not((tmp_37_reg_14631 = ap_const_lv4_8)) and not((tmp_37_reg_14631 = ap_const_lv4_7)) and not((tmp_37_reg_14631 = ap_const_lv4_6)) and not((tmp_37_reg_14631 = ap_const_lv4_5)) and not((tmp_37_reg_14631 = ap_const_lv4_4)) and not((tmp_37_reg_14631 = ap_const_lv4_3)) and not((tmp_37_reg_14631 = ap_const_lv4_2)) and not((tmp_37_reg_14631 = ap_const_lv4_1)) and not((tmp_37_reg_14631 = ap_const_lv4_0))) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_E)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_D)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_C)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_B)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_A)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_9)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_8)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_7)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_6)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_5)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_4)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_3)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_2)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_1)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_0)))) then
end_string_8_6_reg_10997 <= end_string_8_4_reg_5692;
end if;
end if;
end process;
-- end_string_9_2_reg_1452 assign process. --
end_string_9_2_reg_1452_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ST_st2_fsm_1 = ap_CS_fsm) and not((ap_const_lv1_0 = exitcond3_fu_12991_p2)))) then
end_string_9_2_reg_1452 <= end_string_9_fu_188;
elsif (((ap_ST_st44_fsm_43 = ap_CS_fsm) and not((ap_const_lv1_0 = exitcond_fu_13718_p2)) and not((ap_const_lv1_0 = all_end_phi_fu_12651_p36)))) then
end_string_9_2_reg_1452 <= end_string_9_4_reg_5677;
end if;
end if;
end process;
-- end_string_9_3_reg_4501 assign process. --
end_string_9_3_reg_4501_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ST_st44_fsm_43 = ap_CS_fsm) and not((ap_const_lv1_0 = exitcond_fu_13718_p2)) and (ap_const_lv1_0 = all_end_phi_fu_12651_p36))) then
end_string_9_3_reg_4501 <= end_string_9_4_reg_5677;
elsif (((ap_ST_st8_fsm_7 = ap_CS_fsm) and not((exitcond2_fu_13247_p2 = ap_const_lv1_0)))) then
end_string_9_3_reg_4501 <= end_string_9_2_reg_1452;
end if;
end if;
end process;
-- end_string_9_4_reg_5677 assign process. --
end_string_9_4_reg_5677_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ST_st43_fsm_42 = ap_CS_fsm) or ((ap_ST_st32_fsm_31 = ap_CS_fsm) and ((not((ap_const_lv1_0 = end_load_3_phi_phi_fu_11584_p32)) and (ap_const_lv1_0 = brmerge_demorgan_reg_14680)) or (not((ap_const_lv1_0 = end_load_3_phi_phi_fu_11584_p32)) and not((ap_const_lv1_0 = tmp1_fu_13626_p2))))))) then
end_string_9_4_reg_5677 <= end_string_9_6_reg_10938;
elsif ((ap_ST_st18_fsm_17 = ap_CS_fsm)) then
end_string_9_4_reg_5677 <= end_string_9_3_reg_4501;
end if;
end if;
end process;
-- end_string_9_5_reg_7163 assign process. --
end_string_9_5_reg_7163_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and not((ap_const_lv1_0 = end_0_phi_fu_5844_p32)) and (tmp_37_fu_13557_p1 = ap_const_lv4_9))) then
end_string_9_5_reg_7163 <= end_string_0_phi_fu_6831_p4;
elsif ((((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and not((ap_const_lv1_0 = end_0_phi_fu_5844_p32))) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and not((ap_const_lv1_0 = end_0_phi_fu_5844_p32)) and (tmp_37_fu_13557_p1 = ap_const_lv4_D)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and not((ap_const_lv1_0 = end_0_phi_fu_5844_p32)) and (tmp_37_fu_13557_p1 = ap_const_lv4_C)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and not((ap_const_lv1_0 = end_0_phi_fu_5844_p32)) and (tmp_37_fu_13557_p1 = ap_const_lv4_B)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and not((ap_const_lv1_0 = end_0_phi_fu_5844_p32)) and (tmp_37_fu_13557_p1 = ap_const_lv4_A)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and not((ap_const_lv1_0 = end_0_phi_fu_5844_p32)) and (tmp_37_fu_13557_p1 = ap_const_lv4_8)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and not((ap_const_lv1_0 = end_0_phi_fu_5844_p32)) and (tmp_37_fu_13557_p1 = ap_const_lv4_7)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and not((ap_const_lv1_0 = end_0_phi_fu_5844_p32)) and (tmp_37_fu_13557_p1 = ap_const_lv4_6)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and not((ap_const_lv1_0 = end_0_phi_fu_5844_p32)) and (tmp_37_fu_13557_p1 = ap_const_lv4_5)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and not((ap_const_lv1_0 = end_0_phi_fu_5844_p32)) and (tmp_37_fu_13557_p1 = ap_const_lv4_4)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and not((ap_const_lv1_0 = end_0_phi_fu_5844_p32)) and (tmp_37_fu_13557_p1 = ap_const_lv4_3)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and not((ap_const_lv1_0 = end_0_phi_fu_5844_p32)) and (tmp_37_fu_13557_p1 = ap_const_lv4_2)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and not((ap_const_lv1_0 = end_0_phi_fu_5844_p32)) and (tmp_37_fu_13557_p1 = ap_const_lv4_1)) or ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and not((ap_const_lv1_0 = end_0_phi_fu_5844_p32)) and (tmp_37_fu_13557_p1 = ap_const_lv4_0)))) then
end_string_9_5_reg_7163 <= end_string_9_4_reg_5677;
end if;
end if;
end process;
-- end_string_9_6_reg_10938 assign process. --
end_string_9_6_reg_10938_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ST_st30_fsm_29 = ap_CS_fsm) and not((ap_const_lv1_0 = end_0_reg_5841)))) then
end_string_9_6_reg_10938 <= end_string_9_5_reg_7163;
elsif ((((ap_ST_st22_fsm_21 = ap_CS_fsm) and not((tmp_37_reg_14631 = ap_const_lv4_E)) and not((tmp_37_reg_14631 = ap_const_lv4_D)) and not((tmp_37_reg_14631 = ap_const_lv4_C)) and not((tmp_37_reg_14631 = ap_const_lv4_B)) and not((tmp_37_reg_14631 = ap_const_lv4_A)) and not((tmp_37_reg_14631 = ap_const_lv4_9)) and not((tmp_37_reg_14631 = ap_const_lv4_8)) and not((tmp_37_reg_14631 = ap_const_lv4_7)) and not((tmp_37_reg_14631 = ap_const_lv4_6)) and not((tmp_37_reg_14631 = ap_const_lv4_5)) and not((tmp_37_reg_14631 = ap_const_lv4_4)) and not((tmp_37_reg_14631 = ap_const_lv4_3)) and not((tmp_37_reg_14631 = ap_const_lv4_2)) and not((tmp_37_reg_14631 = ap_const_lv4_1)) and not((tmp_37_reg_14631 = ap_const_lv4_0))) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_E)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_D)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_C)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_B)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_A)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_9)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_8)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_7)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_6)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_5)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_4)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_3)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_2)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_1)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_0)))) then
end_string_9_6_reg_10938 <= end_string_9_4_reg_5677;
end if;
end if;
end process;
-- i_reg_1552 assign process. --
i_reg_1552_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ST_st2_fsm_1 = ap_CS_fsm) and not((ap_const_lv1_0 = exitcond3_fu_12991_p2)))) then
i_reg_1552 <= length_r;
elsif (((ap_ST_st44_fsm_43 = ap_CS_fsm) and not((ap_const_lv1_0 = exitcond_fu_13718_p2)) and not((ap_const_lv1_0 = all_end_phi_fu_12651_p36)))) then
i_reg_1552 <= i_1_reg_14270;
end if;
end if;
end process;
-- j_0_bucket_index_reg_3706 assign process. --
j_0_bucket_index_reg_3706_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ST_st12_fsm_11 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_11_fu_13276_p2)) and not((ap_const_lv1_0 = tmp_27_1_fu_13292_p2)))) then
j_0_bucket_index_reg_3706 <= ap_const_lv2_2;
elsif ((ap_ST_st13_fsm_12 = ap_CS_fsm)) then
j_0_bucket_index_reg_3706 <= r_1_0_i_lcssa3_cast_fu_13298_p1;
end if;
end if;
end process;
-- j_0_end_reg_3717 assign process. --
j_0_end_reg_3717_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ST_st12_fsm_11 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_11_fu_13276_p2)) and not((ap_const_lv1_0 = tmp_27_1_fu_13292_p2)))) then
j_0_end_reg_3717 <= ap_const_lv1_1;
elsif ((ap_ST_st13_fsm_12 = ap_CS_fsm)) then
j_0_end_reg_3717 <= ap_const_lv1_0;
end if;
end if;
end process;
-- j_bit_addr12_phi_reg_8637 assign process. --
j_bit_addr12_phi_reg_8637_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_ST_st20_fsm_19 = ap_CS_fsm)) then
if ((tmp_37_reg_14631 = ap_const_lv4_0)) then
j_bit_addr12_phi_reg_8637 <= j_15_bit_load_reg_14279;
elsif ((tmp_37_reg_14631 = ap_const_lv4_E)) then
j_bit_addr12_phi_reg_8637 <= j_15_bit_14_load_reg_14349;
elsif ((tmp_37_reg_14631 = ap_const_lv4_D)) then
j_bit_addr12_phi_reg_8637 <= j_15_bit_13_load_reg_14344;
elsif ((tmp_37_reg_14631 = ap_const_lv4_C)) then
j_bit_addr12_phi_reg_8637 <= j_15_bit_12_load_reg_14339;
elsif ((tmp_37_reg_14631 = ap_const_lv4_B)) then
j_bit_addr12_phi_reg_8637 <= j_15_bit_11_load_reg_14334;
elsif ((tmp_37_reg_14631 = ap_const_lv4_A)) then
j_bit_addr12_phi_reg_8637 <= j_15_bit_10_load_reg_14329;
elsif ((tmp_37_reg_14631 = ap_const_lv4_9)) then
j_bit_addr12_phi_reg_8637 <= j_15_bit_9_load_reg_14324;
elsif ((tmp_37_reg_14631 = ap_const_lv4_8)) then
j_bit_addr12_phi_reg_8637 <= j_15_bit_8_load_reg_14319;
elsif ((tmp_37_reg_14631 = ap_const_lv4_7)) then
j_bit_addr12_phi_reg_8637 <= j_15_bit_7_load_reg_14314;
elsif ((tmp_37_reg_14631 = ap_const_lv4_6)) then
j_bit_addr12_phi_reg_8637 <= j_15_bit_6_load_reg_14309;
elsif ((tmp_37_reg_14631 = ap_const_lv4_5)) then
j_bit_addr12_phi_reg_8637 <= j_15_bit_5_load_reg_14304;
elsif ((tmp_37_reg_14631 = ap_const_lv4_4)) then
j_bit_addr12_phi_reg_8637 <= j_15_bit_4_load_reg_14299;
elsif ((tmp_37_reg_14631 = ap_const_lv4_3)) then
j_bit_addr12_phi_reg_8637 <= j_15_bit_3_load_reg_14294;
elsif ((tmp_37_reg_14631 = ap_const_lv4_2)) then
j_bit_addr12_phi_reg_8637 <= j_15_bit_2_load_reg_14289;
elsif ((tmp_37_reg_14631 = ap_const_lv4_1)) then
j_bit_addr12_phi_reg_8637 <= j_15_bit_1_load_reg_14284;
elsif ((ap_true = ap_true)) then
j_bit_addr12_phi_reg_8637 <= j_15_bit_15_load_reg_14354;
end if;
end if;
end if;
end process;
-- j_bucket_index_addr13_phi_reg_8675 assign process. --
j_bucket_index_addr13_phi_reg_8675_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_ST_st21_fsm_20 = ap_CS_fsm)) then
if ((tmp_37_reg_14631 = ap_const_lv4_0)) then
j_bucket_index_addr13_phi_reg_8675(0) <= j_bucket_index_0_load_reg_14359(0);
j_bucket_index_addr13_phi_reg_8675(1) <= j_bucket_index_0_load_reg_14359(1);
elsif ((tmp_37_reg_14631 = ap_const_lv4_E)) then
j_bucket_index_addr13_phi_reg_8675(0) <= j_bucket_index_14_load_reg_14429(0);
j_bucket_index_addr13_phi_reg_8675(1) <= j_bucket_index_14_load_reg_14429(1);
elsif ((tmp_37_reg_14631 = ap_const_lv4_D)) then
j_bucket_index_addr13_phi_reg_8675(0) <= j_bucket_index_13_load_reg_14424(0);
j_bucket_index_addr13_phi_reg_8675(1) <= j_bucket_index_13_load_reg_14424(1);
elsif ((tmp_37_reg_14631 = ap_const_lv4_C)) then
j_bucket_index_addr13_phi_reg_8675(0) <= j_bucket_index_12_load_reg_14419(0);
j_bucket_index_addr13_phi_reg_8675(1) <= j_bucket_index_12_load_reg_14419(1);
elsif ((tmp_37_reg_14631 = ap_const_lv4_B)) then
j_bucket_index_addr13_phi_reg_8675(0) <= j_bucket_index_11_load_reg_14414(0);
j_bucket_index_addr13_phi_reg_8675(1) <= j_bucket_index_11_load_reg_14414(1);
elsif ((tmp_37_reg_14631 = ap_const_lv4_A)) then
j_bucket_index_addr13_phi_reg_8675(0) <= j_bucket_index_10_load_reg_14409(0);
j_bucket_index_addr13_phi_reg_8675(1) <= j_bucket_index_10_load_reg_14409(1);
elsif ((tmp_37_reg_14631 = ap_const_lv4_9)) then
j_bucket_index_addr13_phi_reg_8675(0) <= j_bucket_index_9_load_reg_14404(0);
j_bucket_index_addr13_phi_reg_8675(1) <= j_bucket_index_9_load_reg_14404(1);
elsif ((tmp_37_reg_14631 = ap_const_lv4_8)) then
j_bucket_index_addr13_phi_reg_8675(0) <= j_bucket_index_8_load_reg_14399(0);
j_bucket_index_addr13_phi_reg_8675(1) <= j_bucket_index_8_load_reg_14399(1);
elsif ((tmp_37_reg_14631 = ap_const_lv4_7)) then
j_bucket_index_addr13_phi_reg_8675(0) <= j_bucket_index_7_load_reg_14394(0);
j_bucket_index_addr13_phi_reg_8675(1) <= j_bucket_index_7_load_reg_14394(1);
elsif ((tmp_37_reg_14631 = ap_const_lv4_6)) then
j_bucket_index_addr13_phi_reg_8675(0) <= j_bucket_index_6_load_reg_14389(0);
j_bucket_index_addr13_phi_reg_8675(1) <= j_bucket_index_6_load_reg_14389(1);
elsif ((tmp_37_reg_14631 = ap_const_lv4_5)) then
j_bucket_index_addr13_phi_reg_8675(0) <= j_bucket_index_5_load_reg_14384(0);
j_bucket_index_addr13_phi_reg_8675(1) <= j_bucket_index_5_load_reg_14384(1);
elsif ((tmp_37_reg_14631 = ap_const_lv4_4)) then
j_bucket_index_addr13_phi_reg_8675(0) <= j_bucket_index_4_load_reg_14379(0);
j_bucket_index_addr13_phi_reg_8675(1) <= j_bucket_index_4_load_reg_14379(1);
elsif ((tmp_37_reg_14631 = ap_const_lv4_3)) then
j_bucket_index_addr13_phi_reg_8675(0) <= j_bucket_index_3_load_reg_14374(0);
j_bucket_index_addr13_phi_reg_8675(1) <= j_bucket_index_3_load_reg_14374(1);
elsif ((tmp_37_reg_14631 = ap_const_lv4_2)) then
j_bucket_index_addr13_phi_reg_8675(0) <= j_bucket_index_2_load_reg_14369(0);
j_bucket_index_addr13_phi_reg_8675(1) <= j_bucket_index_2_load_reg_14369(1);
elsif ((tmp_37_reg_14631 = ap_const_lv4_1)) then
j_bucket_index_addr13_phi_reg_8675(0) <= j_bucket_index_1_load_reg_14364(0);
j_bucket_index_addr13_phi_reg_8675(1) <= j_bucket_index_1_load_reg_14364(1);
elsif ((ap_true = ap_true)) then
j_bucket_index_addr13_phi_reg_8675(0) <= j_bucket_index_15_load_reg_14434(0);
j_bucket_index_addr13_phi_reg_8675(1) <= j_bucket_index_15_load_reg_14434(1);
end if;
end if;
end if;
end process;
-- k_1_reg_1913 assign process. --
k_1_reg_1913_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_ST_st17_fsm_16 = ap_CS_fsm)) then
k_1_reg_1913 <= k_5_reg_14522;
elsif (((ap_ST_st7_fsm_6 = ap_CS_fsm) and (ap_const_lv1_0 = tmp_6_fu_13097_p2))) then
k_1_reg_1913 <= ap_const_lv5_0;
end if;
end if;
end process;
-- k_2_reg_5827 assign process. --
k_2_reg_5827_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ST_st43_fsm_42 = ap_CS_fsm) or ((ap_ST_st32_fsm_31 = ap_CS_fsm) and ((not((ap_const_lv1_0 = end_load_3_phi_phi_fu_11584_p32)) and (ap_const_lv1_0 = brmerge_demorgan_reg_14680)) or (not((ap_const_lv1_0 = end_load_3_phi_phi_fu_11584_p32)) and not((ap_const_lv1_0 = tmp1_fu_13626_p2))))))) then
k_2_reg_5827 <= k_7_reg_14615;
elsif ((ap_ST_st18_fsm_17 = ap_CS_fsm)) then
k_2_reg_5827 <= ap_const_lv5_0;
end if;
end if;
end process;
-- k_3_reg_12604 assign process. --
k_3_reg_12604_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ST_st19_fsm_18 = ap_CS_fsm) and (ap_const_lv1_0 = tmp_9_fu_13539_p2))) then
k_3_reg_12604 <= ap_const_lv5_0;
elsif ((((ap_ST_st47_fsm_46 = ap_CS_fsm) and not((tmp_38_reg_14781 = ap_const_lv4_E)) and not((tmp_38_reg_14781 = ap_const_lv4_D)) and not((tmp_38_reg_14781 = ap_const_lv4_C)) and not((tmp_38_reg_14781 = ap_const_lv4_B)) and not((tmp_38_reg_14781 = ap_const_lv4_A)) and not((tmp_38_reg_14781 = ap_const_lv4_9)) and not((tmp_38_reg_14781 = ap_const_lv4_8)) and not((tmp_38_reg_14781 = ap_const_lv4_7)) and not((tmp_38_reg_14781 = ap_const_lv4_6)) and not((tmp_38_reg_14781 = ap_const_lv4_5)) and not((tmp_38_reg_14781 = ap_const_lv4_4)) and not((tmp_38_reg_14781 = ap_const_lv4_3)) and not((tmp_38_reg_14781 = ap_const_lv4_2)) and not((tmp_38_reg_14781 = ap_const_lv4_1)) and not((tmp_38_reg_14781 = ap_const_lv4_0)) and (ap_const_lv1_0 = any_end_reg_12691)) or ((ap_ST_st47_fsm_46 = ap_CS_fsm) and (tmp_38_reg_14781 = ap_const_lv4_E) and (ap_const_lv1_0 = any_end_reg_12691)) or ((ap_ST_st47_fsm_46 = ap_CS_fsm) and (tmp_38_reg_14781 = ap_const_lv4_D) and (ap_const_lv1_0 = any_end_reg_12691)) or ((ap_ST_st47_fsm_46 = ap_CS_fsm) and (tmp_38_reg_14781 = ap_const_lv4_C) and (ap_const_lv1_0 = any_end_reg_12691)) or ((ap_ST_st47_fsm_46 = ap_CS_fsm) and (tmp_38_reg_14781 = ap_const_lv4_B) and (ap_const_lv1_0 = any_end_reg_12691)) or ((ap_ST_st47_fsm_46 = ap_CS_fsm) and (tmp_38_reg_14781 = ap_const_lv4_A) and (ap_const_lv1_0 = any_end_reg_12691)) or ((ap_ST_st47_fsm_46 = ap_CS_fsm) and (tmp_38_reg_14781 = ap_const_lv4_9) and (ap_const_lv1_0 = any_end_reg_12691)) or ((ap_ST_st47_fsm_46 = ap_CS_fsm) and (tmp_38_reg_14781 = ap_const_lv4_8) and (ap_const_lv1_0 = any_end_reg_12691)) or ((ap_ST_st47_fsm_46 = ap_CS_fsm) and (tmp_38_reg_14781 = ap_const_lv4_7) and (ap_const_lv1_0 = any_end_reg_12691)) or ((ap_ST_st47_fsm_46 = ap_CS_fsm) and (tmp_38_reg_14781 = ap_const_lv4_6) and (ap_const_lv1_0 = any_end_reg_12691)) or ((ap_ST_st47_fsm_46 = ap_CS_fsm) and (tmp_38_reg_14781 = ap_const_lv4_5) and (ap_const_lv1_0 = any_end_reg_12691)) or ((ap_ST_st47_fsm_46 = ap_CS_fsm) and (tmp_38_reg_14781 = ap_const_lv4_4) and (ap_const_lv1_0 = any_end_reg_12691)) or ((ap_ST_st47_fsm_46 = ap_CS_fsm) and (tmp_38_reg_14781 = ap_const_lv4_3) and (ap_const_lv1_0 = any_end_reg_12691)) or ((ap_ST_st47_fsm_46 = ap_CS_fsm) and (tmp_38_reg_14781 = ap_const_lv4_2) and (ap_const_lv1_0 = any_end_reg_12691)) or ((ap_ST_st47_fsm_46 = ap_CS_fsm) and (tmp_38_reg_14781 = ap_const_lv4_1) and (ap_const_lv1_0 = any_end_reg_12691)) or ((ap_ST_st47_fsm_46 = ap_CS_fsm) and (tmp_38_reg_14781 = ap_const_lv4_0) and (ap_const_lv1_0 = any_end_reg_12691)) or ((ap_ST_st47_fsm_46 = ap_CS_fsm) and not((ap_const_lv1_0 = any_end_reg_12691))))) then
k_3_reg_12604 <= k_6_reg_14754;
end if;
end if;
end process;
-- k_reg_612 assign process. --
k_reg_612_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_ST_st6_fsm_5 = ap_CS_fsm)) then
k_reg_612 <= k_4_reg_13968;
elsif (((ap_ST_st1_fsm_0 = ap_CS_fsm) and not((ap_start = ap_const_logic_0)))) then
k_reg_612 <= ap_const_lv5_0;
end if;
end if;
end process;
-- offset_reg_11634 assign process. --
offset_reg_11634_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_ST_st32_fsm_31 = ap_CS_fsm)) then
if (ap_sig_bdd_2617) then
offset_reg_11634 <= sym_offset_0_4_reg_5571;
elsif (ap_sig_bdd_2613) then
offset_reg_11634 <= sym_offset_14_4_reg_5347;
elsif (ap_sig_bdd_2609) then
offset_reg_11634 <= sym_offset_13_4_reg_5363;
elsif (ap_sig_bdd_2605) then
offset_reg_11634 <= sym_offset_12_4_reg_5379;
elsif (ap_sig_bdd_2601) then
offset_reg_11634 <= sym_offset_11_4_reg_5395;
elsif (ap_sig_bdd_2597) then
offset_reg_11634 <= sym_offset_10_4_reg_5411;
elsif (ap_sig_bdd_2593) then
offset_reg_11634 <= sym_offset_9_4_reg_5427;
elsif (ap_sig_bdd_2589) then
offset_reg_11634 <= sym_offset_8_4_reg_5443;
elsif (ap_sig_bdd_2585) then
offset_reg_11634 <= sym_offset_7_4_reg_5459;
elsif (ap_sig_bdd_2581) then
offset_reg_11634 <= sym_offset_6_4_reg_5475;
elsif (ap_sig_bdd_2577) then
offset_reg_11634 <= sym_offset_5_4_reg_5491;
elsif (ap_sig_bdd_2573) then
offset_reg_11634 <= sym_offset_4_4_reg_5507;
elsif (ap_sig_bdd_2569) then
offset_reg_11634 <= sym_offset_3_4_reg_5523;
elsif (ap_sig_bdd_2565) then
offset_reg_11634 <= sym_offset_2_4_reg_5539;
elsif (ap_sig_bdd_2561) then
offset_reg_11634 <= sym_offset_1_4_reg_5555;
elsif (ap_sig_bdd_2557) then
offset_reg_11634 <= sym_offset_15_4_reg_5331;
end if;
end if;
end if;
end process;
-- p_0_reg_12882 assign process. --
p_0_reg_12882_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ST_st7_fsm_6 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_6_fu_13097_p2)))) then
p_0_reg_12882 <= ap_const_lv1_0;
elsif (((ap_ST_st32_fsm_31 = ap_CS_fsm) and (ap_const_lv1_0 = tmp1_fu_13626_p2) and not((ap_const_lv1_0 = brmerge_demorgan_reg_14680)))) then
p_0_reg_12882 <= ap_const_lv1_1;
end if;
end if;
end process;
-- r_1_0_i_lcssa3_reg_3693 assign process. --
r_1_0_i_lcssa3_reg_3693_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_ST_st12_fsm_11 = ap_CS_fsm)) then
if (ap_sig_bdd_1202) then
r_1_0_i_lcssa3_reg_3693 <= ap_const_lv1_1;
elsif ((ap_const_lv1_0 = tmp_11_fu_13276_p2)) then
r_1_0_i_lcssa3_reg_3693 <= ap_const_lv1_0;
end if;
end if;
end if;
end process;
-- state_0_1_reg_3896 assign process. --
state_0_1_reg_3896_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ST_st44_fsm_43 = ap_CS_fsm) and not((ap_const_lv1_0 = exitcond_fu_13718_p2)) and (ap_const_lv1_0 = all_end_phi_fu_12651_p36))) then
state_0_1_reg_3896 <= state_0_2_reg_4836;
elsif (((ap_ST_st8_fsm_7 = ap_CS_fsm) and not((exitcond2_fu_13247_p2 = ap_const_lv1_0)))) then
state_0_1_reg_3896 <= state_0_s_reg_804;
end if;
end if;
end process;
-- state_0_2_reg_4836 assign process. --
state_0_2_reg_4836_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ST_st43_fsm_42 = ap_CS_fsm) or ((ap_ST_st32_fsm_31 = ap_CS_fsm) and ((not((ap_const_lv1_0 = end_load_3_phi_phi_fu_11584_p32)) and (ap_const_lv1_0 = brmerge_demorgan_reg_14680)) or (not((ap_const_lv1_0 = end_load_3_phi_phi_fu_11584_p32)) and not((ap_const_lv1_0 = tmp1_fu_13626_p2))))))) then
state_0_2_reg_4836 <= state_0_4_reg_9582;
elsif ((ap_ST_st18_fsm_17 = ap_CS_fsm)) then
state_0_2_reg_4836 <= state_0_1_reg_3896;
end if;
end if;
end process;
-- state_0_4_reg_9582 assign process. --
state_0_4_reg_9582_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_0))) then
state_0_4_reg_9582 <= state_0_fu_13574_p2;
elsif ((((ap_ST_st22_fsm_21 = ap_CS_fsm) and not((tmp_37_reg_14631 = ap_const_lv4_E)) and not((tmp_37_reg_14631 = ap_const_lv4_D)) and not((tmp_37_reg_14631 = ap_const_lv4_C)) and not((tmp_37_reg_14631 = ap_const_lv4_B)) and not((tmp_37_reg_14631 = ap_const_lv4_A)) and not((tmp_37_reg_14631 = ap_const_lv4_9)) and not((tmp_37_reg_14631 = ap_const_lv4_8)) and not((tmp_37_reg_14631 = ap_const_lv4_7)) and not((tmp_37_reg_14631 = ap_const_lv4_6)) and not((tmp_37_reg_14631 = ap_const_lv4_5)) and not((tmp_37_reg_14631 = ap_const_lv4_4)) and not((tmp_37_reg_14631 = ap_const_lv4_3)) and not((tmp_37_reg_14631 = ap_const_lv4_2)) and not((tmp_37_reg_14631 = ap_const_lv4_1)) and not((tmp_37_reg_14631 = ap_const_lv4_0))) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_E)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_D)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_C)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_B)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_A)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_9)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_8)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_7)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_6)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_5)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_4)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_3)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_2)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_1)) or ((ap_ST_st30_fsm_29 = ap_CS_fsm) and not((ap_const_lv1_0 = end_0_reg_5841))))) then
state_0_4_reg_9582 <= state_0_2_reg_4836;
end if;
end if;
end process;
-- state_10_1_reg_3786 assign process. --
state_10_1_reg_3786_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ST_st44_fsm_43 = ap_CS_fsm) and not((ap_const_lv1_0 = exitcond_fu_13718_p2)) and (ap_const_lv1_0 = all_end_phi_fu_12651_p36))) then
state_10_1_reg_3786 <= state_10_2_reg_4686;
elsif (((ap_ST_st8_fsm_7 = ap_CS_fsm) and not((exitcond2_fu_13247_p2 = ap_const_lv1_0)))) then
state_10_1_reg_3786 <= state_10_s_reg_684;
end if;
end if;
end process;
-- state_10_2_reg_4686 assign process. --
state_10_2_reg_4686_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ST_st43_fsm_42 = ap_CS_fsm) or ((ap_ST_st32_fsm_31 = ap_CS_fsm) and ((not((ap_const_lv1_0 = end_load_3_phi_phi_fu_11584_p32)) and (ap_const_lv1_0 = brmerge_demorgan_reg_14680)) or (not((ap_const_lv1_0 = end_load_3_phi_phi_fu_11584_p32)) and not((ap_const_lv1_0 = tmp1_fu_13626_p2))))))) then
state_10_2_reg_4686 <= state_10_4_reg_9002;
elsif ((ap_ST_st18_fsm_17 = ap_CS_fsm)) then
state_10_2_reg_4686 <= state_10_1_reg_3786;
end if;
end if;
end process;
-- state_10_4_reg_9002 assign process. --
state_10_4_reg_9002_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_A))) then
state_10_4_reg_9002 <= state_0_fu_13574_p2;
elsif ((((ap_ST_st22_fsm_21 = ap_CS_fsm) and not((tmp_37_reg_14631 = ap_const_lv4_E)) and not((tmp_37_reg_14631 = ap_const_lv4_D)) and not((tmp_37_reg_14631 = ap_const_lv4_C)) and not((tmp_37_reg_14631 = ap_const_lv4_B)) and not((tmp_37_reg_14631 = ap_const_lv4_A)) and not((tmp_37_reg_14631 = ap_const_lv4_9)) and not((tmp_37_reg_14631 = ap_const_lv4_8)) and not((tmp_37_reg_14631 = ap_const_lv4_7)) and not((tmp_37_reg_14631 = ap_const_lv4_6)) and not((tmp_37_reg_14631 = ap_const_lv4_5)) and not((tmp_37_reg_14631 = ap_const_lv4_4)) and not((tmp_37_reg_14631 = ap_const_lv4_3)) and not((tmp_37_reg_14631 = ap_const_lv4_2)) and not((tmp_37_reg_14631 = ap_const_lv4_1)) and not((tmp_37_reg_14631 = ap_const_lv4_0))) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_E)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_D)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_C)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_B)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_9)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_8)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_7)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_6)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_5)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_4)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_3)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_2)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_1)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_0)) or ((ap_ST_st30_fsm_29 = ap_CS_fsm) and not((ap_const_lv1_0 = end_0_reg_5841))))) then
state_10_4_reg_9002 <= state_10_2_reg_4686;
end if;
end if;
end process;
-- state_11_1_reg_3775 assign process. --
state_11_1_reg_3775_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ST_st44_fsm_43 = ap_CS_fsm) and not((ap_const_lv1_0 = exitcond_fu_13718_p2)) and (ap_const_lv1_0 = all_end_phi_fu_12651_p36))) then
state_11_1_reg_3775 <= state_11_2_reg_4671;
elsif (((ap_ST_st8_fsm_7 = ap_CS_fsm) and not((exitcond2_fu_13247_p2 = ap_const_lv1_0)))) then
state_11_1_reg_3775 <= state_11_s_reg_672;
end if;
end if;
end process;
-- state_11_2_reg_4671 assign process. --
state_11_2_reg_4671_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ST_st43_fsm_42 = ap_CS_fsm) or ((ap_ST_st32_fsm_31 = ap_CS_fsm) and ((not((ap_const_lv1_0 = end_load_3_phi_phi_fu_11584_p32)) and (ap_const_lv1_0 = brmerge_demorgan_reg_14680)) or (not((ap_const_lv1_0 = end_load_3_phi_phi_fu_11584_p32)) and not((ap_const_lv1_0 = tmp1_fu_13626_p2))))))) then
state_11_2_reg_4671 <= state_11_4_reg_8944;
elsif ((ap_ST_st18_fsm_17 = ap_CS_fsm)) then
state_11_2_reg_4671 <= state_11_1_reg_3775;
end if;
end if;
end process;
-- state_11_4_reg_8944 assign process. --
state_11_4_reg_8944_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_B))) then
state_11_4_reg_8944 <= state_0_fu_13574_p2;
elsif ((((ap_ST_st22_fsm_21 = ap_CS_fsm) and not((tmp_37_reg_14631 = ap_const_lv4_E)) and not((tmp_37_reg_14631 = ap_const_lv4_D)) and not((tmp_37_reg_14631 = ap_const_lv4_C)) and not((tmp_37_reg_14631 = ap_const_lv4_B)) and not((tmp_37_reg_14631 = ap_const_lv4_A)) and not((tmp_37_reg_14631 = ap_const_lv4_9)) and not((tmp_37_reg_14631 = ap_const_lv4_8)) and not((tmp_37_reg_14631 = ap_const_lv4_7)) and not((tmp_37_reg_14631 = ap_const_lv4_6)) and not((tmp_37_reg_14631 = ap_const_lv4_5)) and not((tmp_37_reg_14631 = ap_const_lv4_4)) and not((tmp_37_reg_14631 = ap_const_lv4_3)) and not((tmp_37_reg_14631 = ap_const_lv4_2)) and not((tmp_37_reg_14631 = ap_const_lv4_1)) and not((tmp_37_reg_14631 = ap_const_lv4_0))) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_E)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_D)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_C)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_A)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_9)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_8)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_7)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_6)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_5)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_4)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_3)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_2)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_1)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_0)) or ((ap_ST_st30_fsm_29 = ap_CS_fsm) and not((ap_const_lv1_0 = end_0_reg_5841))))) then
state_11_4_reg_8944 <= state_11_2_reg_4671;
end if;
end if;
end process;
-- state_12_1_reg_3764 assign process. --
state_12_1_reg_3764_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ST_st44_fsm_43 = ap_CS_fsm) and not((ap_const_lv1_0 = exitcond_fu_13718_p2)) and (ap_const_lv1_0 = all_end_phi_fu_12651_p36))) then
state_12_1_reg_3764 <= state_12_2_reg_4656;
elsif (((ap_ST_st8_fsm_7 = ap_CS_fsm) and not((exitcond2_fu_13247_p2 = ap_const_lv1_0)))) then
state_12_1_reg_3764 <= state_12_s_reg_660;
end if;
end if;
end process;
-- state_12_2_reg_4656 assign process. --
state_12_2_reg_4656_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ST_st43_fsm_42 = ap_CS_fsm) or ((ap_ST_st32_fsm_31 = ap_CS_fsm) and ((not((ap_const_lv1_0 = end_load_3_phi_phi_fu_11584_p32)) and (ap_const_lv1_0 = brmerge_demorgan_reg_14680)) or (not((ap_const_lv1_0 = end_load_3_phi_phi_fu_11584_p32)) and not((ap_const_lv1_0 = tmp1_fu_13626_p2))))))) then
state_12_2_reg_4656 <= state_12_4_reg_8886;
elsif ((ap_ST_st18_fsm_17 = ap_CS_fsm)) then
state_12_2_reg_4656 <= state_12_1_reg_3764;
end if;
end if;
end process;
-- state_12_4_reg_8886 assign process. --
state_12_4_reg_8886_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_C))) then
state_12_4_reg_8886 <= state_0_fu_13574_p2;
elsif ((((ap_ST_st22_fsm_21 = ap_CS_fsm) and not((tmp_37_reg_14631 = ap_const_lv4_E)) and not((tmp_37_reg_14631 = ap_const_lv4_D)) and not((tmp_37_reg_14631 = ap_const_lv4_C)) and not((tmp_37_reg_14631 = ap_const_lv4_B)) and not((tmp_37_reg_14631 = ap_const_lv4_A)) and not((tmp_37_reg_14631 = ap_const_lv4_9)) and not((tmp_37_reg_14631 = ap_const_lv4_8)) and not((tmp_37_reg_14631 = ap_const_lv4_7)) and not((tmp_37_reg_14631 = ap_const_lv4_6)) and not((tmp_37_reg_14631 = ap_const_lv4_5)) and not((tmp_37_reg_14631 = ap_const_lv4_4)) and not((tmp_37_reg_14631 = ap_const_lv4_3)) and not((tmp_37_reg_14631 = ap_const_lv4_2)) and not((tmp_37_reg_14631 = ap_const_lv4_1)) and not((tmp_37_reg_14631 = ap_const_lv4_0))) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_E)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_D)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_B)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_A)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_9)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_8)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_7)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_6)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_5)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_4)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_3)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_2)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_1)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_0)) or ((ap_ST_st30_fsm_29 = ap_CS_fsm) and not((ap_const_lv1_0 = end_0_reg_5841))))) then
state_12_4_reg_8886 <= state_12_2_reg_4656;
end if;
end if;
end process;
-- state_13_1_reg_3753 assign process. --
state_13_1_reg_3753_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ST_st44_fsm_43 = ap_CS_fsm) and not((ap_const_lv1_0 = exitcond_fu_13718_p2)) and (ap_const_lv1_0 = all_end_phi_fu_12651_p36))) then
state_13_1_reg_3753 <= state_13_2_reg_4641;
elsif (((ap_ST_st8_fsm_7 = ap_CS_fsm) and not((exitcond2_fu_13247_p2 = ap_const_lv1_0)))) then
state_13_1_reg_3753 <= state_13_s_reg_648;
end if;
end if;
end process;
-- state_13_2_reg_4641 assign process. --
state_13_2_reg_4641_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ST_st43_fsm_42 = ap_CS_fsm) or ((ap_ST_st32_fsm_31 = ap_CS_fsm) and ((not((ap_const_lv1_0 = end_load_3_phi_phi_fu_11584_p32)) and (ap_const_lv1_0 = brmerge_demorgan_reg_14680)) or (not((ap_const_lv1_0 = end_load_3_phi_phi_fu_11584_p32)) and not((ap_const_lv1_0 = tmp1_fu_13626_p2))))))) then
state_13_2_reg_4641 <= state_13_4_reg_8828;
elsif ((ap_ST_st18_fsm_17 = ap_CS_fsm)) then
state_13_2_reg_4641 <= state_13_1_reg_3753;
end if;
end if;
end process;
-- state_13_4_reg_8828 assign process. --
state_13_4_reg_8828_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_D))) then
state_13_4_reg_8828 <= state_0_fu_13574_p2;
elsif ((((ap_ST_st22_fsm_21 = ap_CS_fsm) and not((tmp_37_reg_14631 = ap_const_lv4_E)) and not((tmp_37_reg_14631 = ap_const_lv4_D)) and not((tmp_37_reg_14631 = ap_const_lv4_C)) and not((tmp_37_reg_14631 = ap_const_lv4_B)) and not((tmp_37_reg_14631 = ap_const_lv4_A)) and not((tmp_37_reg_14631 = ap_const_lv4_9)) and not((tmp_37_reg_14631 = ap_const_lv4_8)) and not((tmp_37_reg_14631 = ap_const_lv4_7)) and not((tmp_37_reg_14631 = ap_const_lv4_6)) and not((tmp_37_reg_14631 = ap_const_lv4_5)) and not((tmp_37_reg_14631 = ap_const_lv4_4)) and not((tmp_37_reg_14631 = ap_const_lv4_3)) and not((tmp_37_reg_14631 = ap_const_lv4_2)) and not((tmp_37_reg_14631 = ap_const_lv4_1)) and not((tmp_37_reg_14631 = ap_const_lv4_0))) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_E)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_C)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_B)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_A)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_9)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_8)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_7)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_6)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_5)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_4)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_3)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_2)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_1)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_0)) or ((ap_ST_st30_fsm_29 = ap_CS_fsm) and not((ap_const_lv1_0 = end_0_reg_5841))))) then
state_13_4_reg_8828 <= state_13_2_reg_4641;
end if;
end if;
end process;
-- state_14_1_reg_3742 assign process. --
state_14_1_reg_3742_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ST_st44_fsm_43 = ap_CS_fsm) and not((ap_const_lv1_0 = exitcond_fu_13718_p2)) and (ap_const_lv1_0 = all_end_phi_fu_12651_p36))) then
state_14_1_reg_3742 <= state_14_2_reg_4626;
elsif (((ap_ST_st8_fsm_7 = ap_CS_fsm) and not((exitcond2_fu_13247_p2 = ap_const_lv1_0)))) then
state_14_1_reg_3742 <= state_14_s_reg_636;
end if;
end if;
end process;
-- state_14_2_reg_4626 assign process. --
state_14_2_reg_4626_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ST_st43_fsm_42 = ap_CS_fsm) or ((ap_ST_st32_fsm_31 = ap_CS_fsm) and ((not((ap_const_lv1_0 = end_load_3_phi_phi_fu_11584_p32)) and (ap_const_lv1_0 = brmerge_demorgan_reg_14680)) or (not((ap_const_lv1_0 = end_load_3_phi_phi_fu_11584_p32)) and not((ap_const_lv1_0 = tmp1_fu_13626_p2))))))) then
state_14_2_reg_4626 <= state_14_4_reg_8770;
elsif ((ap_ST_st18_fsm_17 = ap_CS_fsm)) then
state_14_2_reg_4626 <= state_14_1_reg_3742;
end if;
end if;
end process;
-- state_14_4_reg_8770 assign process. --
state_14_4_reg_8770_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_E))) then
state_14_4_reg_8770 <= state_0_fu_13574_p2;
elsif ((((ap_ST_st22_fsm_21 = ap_CS_fsm) and not((tmp_37_reg_14631 = ap_const_lv4_E)) and not((tmp_37_reg_14631 = ap_const_lv4_D)) and not((tmp_37_reg_14631 = ap_const_lv4_C)) and not((tmp_37_reg_14631 = ap_const_lv4_B)) and not((tmp_37_reg_14631 = ap_const_lv4_A)) and not((tmp_37_reg_14631 = ap_const_lv4_9)) and not((tmp_37_reg_14631 = ap_const_lv4_8)) and not((tmp_37_reg_14631 = ap_const_lv4_7)) and not((tmp_37_reg_14631 = ap_const_lv4_6)) and not((tmp_37_reg_14631 = ap_const_lv4_5)) and not((tmp_37_reg_14631 = ap_const_lv4_4)) and not((tmp_37_reg_14631 = ap_const_lv4_3)) and not((tmp_37_reg_14631 = ap_const_lv4_2)) and not((tmp_37_reg_14631 = ap_const_lv4_1)) and not((tmp_37_reg_14631 = ap_const_lv4_0))) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_D)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_C)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_B)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_A)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_9)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_8)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_7)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_6)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_5)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_4)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_3)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_2)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_1)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_0)) or ((ap_ST_st30_fsm_29 = ap_CS_fsm) and not((ap_const_lv1_0 = end_0_reg_5841))))) then
state_14_4_reg_8770 <= state_14_2_reg_4626;
end if;
end if;
end process;
-- state_15_1_reg_3731 assign process. --
state_15_1_reg_3731_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ST_st44_fsm_43 = ap_CS_fsm) and not((ap_const_lv1_0 = exitcond_fu_13718_p2)) and (ap_const_lv1_0 = all_end_phi_fu_12651_p36))) then
state_15_1_reg_3731 <= state_15_2_reg_4611;
elsif (((ap_ST_st8_fsm_7 = ap_CS_fsm) and not((exitcond2_fu_13247_p2 = ap_const_lv1_0)))) then
state_15_1_reg_3731 <= state_15_s_reg_624;
end if;
end if;
end process;
-- state_15_2_reg_4611 assign process. --
state_15_2_reg_4611_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ST_st43_fsm_42 = ap_CS_fsm) or ((ap_ST_st32_fsm_31 = ap_CS_fsm) and ((not((ap_const_lv1_0 = end_load_3_phi_phi_fu_11584_p32)) and (ap_const_lv1_0 = brmerge_demorgan_reg_14680)) or (not((ap_const_lv1_0 = end_load_3_phi_phi_fu_11584_p32)) and not((ap_const_lv1_0 = tmp1_fu_13626_p2))))))) then
state_15_2_reg_4611 <= state_15_4_reg_8712;
elsif ((ap_ST_st18_fsm_17 = ap_CS_fsm)) then
state_15_2_reg_4611 <= state_15_1_reg_3731;
end if;
end if;
end process;
-- state_15_4_reg_8712 assign process. --
state_15_4_reg_8712_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_E)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_D)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_C)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_B)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_A)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_9)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_8)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_7)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_6)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_5)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_4)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_3)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_2)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_1)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_0)) or ((ap_ST_st30_fsm_29 = ap_CS_fsm) and not((ap_const_lv1_0 = end_0_reg_5841))))) then
state_15_4_reg_8712 <= state_15_2_reg_4611;
elsif (((ap_ST_st22_fsm_21 = ap_CS_fsm) and not((tmp_37_reg_14631 = ap_const_lv4_E)) and not((tmp_37_reg_14631 = ap_const_lv4_D)) and not((tmp_37_reg_14631 = ap_const_lv4_C)) and not((tmp_37_reg_14631 = ap_const_lv4_B)) and not((tmp_37_reg_14631 = ap_const_lv4_A)) and not((tmp_37_reg_14631 = ap_const_lv4_9)) and not((tmp_37_reg_14631 = ap_const_lv4_8)) and not((tmp_37_reg_14631 = ap_const_lv4_7)) and not((tmp_37_reg_14631 = ap_const_lv4_6)) and not((tmp_37_reg_14631 = ap_const_lv4_5)) and not((tmp_37_reg_14631 = ap_const_lv4_4)) and not((tmp_37_reg_14631 = ap_const_lv4_3)) and not((tmp_37_reg_14631 = ap_const_lv4_2)) and not((tmp_37_reg_14631 = ap_const_lv4_1)) and not((tmp_37_reg_14631 = ap_const_lv4_0)))) then
state_15_4_reg_8712 <= state_0_fu_13574_p2;
end if;
end if;
end process;
-- state_1_1_reg_3885 assign process. --
state_1_1_reg_3885_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ST_st44_fsm_43 = ap_CS_fsm) and not((ap_const_lv1_0 = exitcond_fu_13718_p2)) and (ap_const_lv1_0 = all_end_phi_fu_12651_p36))) then
state_1_1_reg_3885 <= state_1_2_reg_4821;
elsif (((ap_ST_st8_fsm_7 = ap_CS_fsm) and not((exitcond2_fu_13247_p2 = ap_const_lv1_0)))) then
state_1_1_reg_3885 <= state_1_s_reg_792;
end if;
end if;
end process;
-- state_1_2_reg_4821 assign process. --
state_1_2_reg_4821_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ST_st43_fsm_42 = ap_CS_fsm) or ((ap_ST_st32_fsm_31 = ap_CS_fsm) and ((not((ap_const_lv1_0 = end_load_3_phi_phi_fu_11584_p32)) and (ap_const_lv1_0 = brmerge_demorgan_reg_14680)) or (not((ap_const_lv1_0 = end_load_3_phi_phi_fu_11584_p32)) and not((ap_const_lv1_0 = tmp1_fu_13626_p2))))))) then
state_1_2_reg_4821 <= state_1_4_reg_9524;
elsif ((ap_ST_st18_fsm_17 = ap_CS_fsm)) then
state_1_2_reg_4821 <= state_1_1_reg_3885;
end if;
end if;
end process;
-- state_1_4_reg_9524 assign process. --
state_1_4_reg_9524_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_1))) then
state_1_4_reg_9524 <= state_0_fu_13574_p2;
elsif ((((ap_ST_st22_fsm_21 = ap_CS_fsm) and not((tmp_37_reg_14631 = ap_const_lv4_E)) and not((tmp_37_reg_14631 = ap_const_lv4_D)) and not((tmp_37_reg_14631 = ap_const_lv4_C)) and not((tmp_37_reg_14631 = ap_const_lv4_B)) and not((tmp_37_reg_14631 = ap_const_lv4_A)) and not((tmp_37_reg_14631 = ap_const_lv4_9)) and not((tmp_37_reg_14631 = ap_const_lv4_8)) and not((tmp_37_reg_14631 = ap_const_lv4_7)) and not((tmp_37_reg_14631 = ap_const_lv4_6)) and not((tmp_37_reg_14631 = ap_const_lv4_5)) and not((tmp_37_reg_14631 = ap_const_lv4_4)) and not((tmp_37_reg_14631 = ap_const_lv4_3)) and not((tmp_37_reg_14631 = ap_const_lv4_2)) and not((tmp_37_reg_14631 = ap_const_lv4_1)) and not((tmp_37_reg_14631 = ap_const_lv4_0))) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_E)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_D)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_C)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_B)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_A)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_9)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_8)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_7)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_6)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_5)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_4)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_3)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_2)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_0)) or ((ap_ST_st30_fsm_29 = ap_CS_fsm) and not((ap_const_lv1_0 = end_0_reg_5841))))) then
state_1_4_reg_9524 <= state_1_2_reg_4821;
end if;
end if;
end process;
-- state_2_1_reg_3874 assign process. --
state_2_1_reg_3874_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ST_st44_fsm_43 = ap_CS_fsm) and not((ap_const_lv1_0 = exitcond_fu_13718_p2)) and (ap_const_lv1_0 = all_end_phi_fu_12651_p36))) then
state_2_1_reg_3874 <= state_2_2_reg_4806;
elsif (((ap_ST_st8_fsm_7 = ap_CS_fsm) and not((exitcond2_fu_13247_p2 = ap_const_lv1_0)))) then
state_2_1_reg_3874 <= state_2_s_reg_780;
end if;
end if;
end process;
-- state_2_2_reg_4806 assign process. --
state_2_2_reg_4806_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ST_st43_fsm_42 = ap_CS_fsm) or ((ap_ST_st32_fsm_31 = ap_CS_fsm) and ((not((ap_const_lv1_0 = end_load_3_phi_phi_fu_11584_p32)) and (ap_const_lv1_0 = brmerge_demorgan_reg_14680)) or (not((ap_const_lv1_0 = end_load_3_phi_phi_fu_11584_p32)) and not((ap_const_lv1_0 = tmp1_fu_13626_p2))))))) then
state_2_2_reg_4806 <= state_2_4_reg_9466;
elsif ((ap_ST_st18_fsm_17 = ap_CS_fsm)) then
state_2_2_reg_4806 <= state_2_1_reg_3874;
end if;
end if;
end process;
-- state_2_4_reg_9466 assign process. --
state_2_4_reg_9466_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_2))) then
state_2_4_reg_9466 <= state_0_fu_13574_p2;
elsif ((((ap_ST_st22_fsm_21 = ap_CS_fsm) and not((tmp_37_reg_14631 = ap_const_lv4_E)) and not((tmp_37_reg_14631 = ap_const_lv4_D)) and not((tmp_37_reg_14631 = ap_const_lv4_C)) and not((tmp_37_reg_14631 = ap_const_lv4_B)) and not((tmp_37_reg_14631 = ap_const_lv4_A)) and not((tmp_37_reg_14631 = ap_const_lv4_9)) and not((tmp_37_reg_14631 = ap_const_lv4_8)) and not((tmp_37_reg_14631 = ap_const_lv4_7)) and not((tmp_37_reg_14631 = ap_const_lv4_6)) and not((tmp_37_reg_14631 = ap_const_lv4_5)) and not((tmp_37_reg_14631 = ap_const_lv4_4)) and not((tmp_37_reg_14631 = ap_const_lv4_3)) and not((tmp_37_reg_14631 = ap_const_lv4_2)) and not((tmp_37_reg_14631 = ap_const_lv4_1)) and not((tmp_37_reg_14631 = ap_const_lv4_0))) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_E)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_D)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_C)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_B)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_A)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_9)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_8)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_7)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_6)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_5)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_4)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_3)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_1)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_0)) or ((ap_ST_st30_fsm_29 = ap_CS_fsm) and not((ap_const_lv1_0 = end_0_reg_5841))))) then
state_2_4_reg_9466 <= state_2_2_reg_4806;
end if;
end if;
end process;
-- state_3_1_reg_3863 assign process. --
state_3_1_reg_3863_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ST_st44_fsm_43 = ap_CS_fsm) and not((ap_const_lv1_0 = exitcond_fu_13718_p2)) and (ap_const_lv1_0 = all_end_phi_fu_12651_p36))) then
state_3_1_reg_3863 <= state_3_2_reg_4791;
elsif (((ap_ST_st8_fsm_7 = ap_CS_fsm) and not((exitcond2_fu_13247_p2 = ap_const_lv1_0)))) then
state_3_1_reg_3863 <= state_3_s_reg_768;
end if;
end if;
end process;
-- state_3_2_reg_4791 assign process. --
state_3_2_reg_4791_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ST_st43_fsm_42 = ap_CS_fsm) or ((ap_ST_st32_fsm_31 = ap_CS_fsm) and ((not((ap_const_lv1_0 = end_load_3_phi_phi_fu_11584_p32)) and (ap_const_lv1_0 = brmerge_demorgan_reg_14680)) or (not((ap_const_lv1_0 = end_load_3_phi_phi_fu_11584_p32)) and not((ap_const_lv1_0 = tmp1_fu_13626_p2))))))) then
state_3_2_reg_4791 <= state_3_4_reg_9408;
elsif ((ap_ST_st18_fsm_17 = ap_CS_fsm)) then
state_3_2_reg_4791 <= state_3_1_reg_3863;
end if;
end if;
end process;
-- state_3_4_reg_9408 assign process. --
state_3_4_reg_9408_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_3))) then
state_3_4_reg_9408 <= state_0_fu_13574_p2;
elsif ((((ap_ST_st22_fsm_21 = ap_CS_fsm) and not((tmp_37_reg_14631 = ap_const_lv4_E)) and not((tmp_37_reg_14631 = ap_const_lv4_D)) and not((tmp_37_reg_14631 = ap_const_lv4_C)) and not((tmp_37_reg_14631 = ap_const_lv4_B)) and not((tmp_37_reg_14631 = ap_const_lv4_A)) and not((tmp_37_reg_14631 = ap_const_lv4_9)) and not((tmp_37_reg_14631 = ap_const_lv4_8)) and not((tmp_37_reg_14631 = ap_const_lv4_7)) and not((tmp_37_reg_14631 = ap_const_lv4_6)) and not((tmp_37_reg_14631 = ap_const_lv4_5)) and not((tmp_37_reg_14631 = ap_const_lv4_4)) and not((tmp_37_reg_14631 = ap_const_lv4_3)) and not((tmp_37_reg_14631 = ap_const_lv4_2)) and not((tmp_37_reg_14631 = ap_const_lv4_1)) and not((tmp_37_reg_14631 = ap_const_lv4_0))) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_E)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_D)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_C)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_B)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_A)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_9)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_8)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_7)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_6)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_5)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_4)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_2)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_1)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_0)) or ((ap_ST_st30_fsm_29 = ap_CS_fsm) and not((ap_const_lv1_0 = end_0_reg_5841))))) then
state_3_4_reg_9408 <= state_3_2_reg_4791;
end if;
end if;
end process;
-- state_4_1_reg_3852 assign process. --
state_4_1_reg_3852_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ST_st44_fsm_43 = ap_CS_fsm) and not((ap_const_lv1_0 = exitcond_fu_13718_p2)) and (ap_const_lv1_0 = all_end_phi_fu_12651_p36))) then
state_4_1_reg_3852 <= state_4_2_reg_4776;
elsif (((ap_ST_st8_fsm_7 = ap_CS_fsm) and not((exitcond2_fu_13247_p2 = ap_const_lv1_0)))) then
state_4_1_reg_3852 <= state_4_s_reg_756;
end if;
end if;
end process;
-- state_4_2_reg_4776 assign process. --
state_4_2_reg_4776_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ST_st43_fsm_42 = ap_CS_fsm) or ((ap_ST_st32_fsm_31 = ap_CS_fsm) and ((not((ap_const_lv1_0 = end_load_3_phi_phi_fu_11584_p32)) and (ap_const_lv1_0 = brmerge_demorgan_reg_14680)) or (not((ap_const_lv1_0 = end_load_3_phi_phi_fu_11584_p32)) and not((ap_const_lv1_0 = tmp1_fu_13626_p2))))))) then
state_4_2_reg_4776 <= state_4_4_reg_9350;
elsif ((ap_ST_st18_fsm_17 = ap_CS_fsm)) then
state_4_2_reg_4776 <= state_4_1_reg_3852;
end if;
end if;
end process;
-- state_4_4_reg_9350 assign process. --
state_4_4_reg_9350_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_4))) then
state_4_4_reg_9350 <= state_0_fu_13574_p2;
elsif ((((ap_ST_st22_fsm_21 = ap_CS_fsm) and not((tmp_37_reg_14631 = ap_const_lv4_E)) and not((tmp_37_reg_14631 = ap_const_lv4_D)) and not((tmp_37_reg_14631 = ap_const_lv4_C)) and not((tmp_37_reg_14631 = ap_const_lv4_B)) and not((tmp_37_reg_14631 = ap_const_lv4_A)) and not((tmp_37_reg_14631 = ap_const_lv4_9)) and not((tmp_37_reg_14631 = ap_const_lv4_8)) and not((tmp_37_reg_14631 = ap_const_lv4_7)) and not((tmp_37_reg_14631 = ap_const_lv4_6)) and not((tmp_37_reg_14631 = ap_const_lv4_5)) and not((tmp_37_reg_14631 = ap_const_lv4_4)) and not((tmp_37_reg_14631 = ap_const_lv4_3)) and not((tmp_37_reg_14631 = ap_const_lv4_2)) and not((tmp_37_reg_14631 = ap_const_lv4_1)) and not((tmp_37_reg_14631 = ap_const_lv4_0))) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_E)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_D)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_C)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_B)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_A)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_9)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_8)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_7)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_6)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_5)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_3)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_2)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_1)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_0)) or ((ap_ST_st30_fsm_29 = ap_CS_fsm) and not((ap_const_lv1_0 = end_0_reg_5841))))) then
state_4_4_reg_9350 <= state_4_2_reg_4776;
end if;
end if;
end process;
-- state_5_1_reg_3841 assign process. --
state_5_1_reg_3841_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ST_st44_fsm_43 = ap_CS_fsm) and not((ap_const_lv1_0 = exitcond_fu_13718_p2)) and (ap_const_lv1_0 = all_end_phi_fu_12651_p36))) then
state_5_1_reg_3841 <= state_5_2_reg_4761;
elsif (((ap_ST_st8_fsm_7 = ap_CS_fsm) and not((exitcond2_fu_13247_p2 = ap_const_lv1_0)))) then
state_5_1_reg_3841 <= state_5_s_reg_744;
end if;
end if;
end process;
-- state_5_2_reg_4761 assign process. --
state_5_2_reg_4761_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ST_st43_fsm_42 = ap_CS_fsm) or ((ap_ST_st32_fsm_31 = ap_CS_fsm) and ((not((ap_const_lv1_0 = end_load_3_phi_phi_fu_11584_p32)) and (ap_const_lv1_0 = brmerge_demorgan_reg_14680)) or (not((ap_const_lv1_0 = end_load_3_phi_phi_fu_11584_p32)) and not((ap_const_lv1_0 = tmp1_fu_13626_p2))))))) then
state_5_2_reg_4761 <= state_5_4_reg_9292;
elsif ((ap_ST_st18_fsm_17 = ap_CS_fsm)) then
state_5_2_reg_4761 <= state_5_1_reg_3841;
end if;
end if;
end process;
-- state_5_4_reg_9292 assign process. --
state_5_4_reg_9292_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_5))) then
state_5_4_reg_9292 <= state_0_fu_13574_p2;
elsif ((((ap_ST_st22_fsm_21 = ap_CS_fsm) and not((tmp_37_reg_14631 = ap_const_lv4_E)) and not((tmp_37_reg_14631 = ap_const_lv4_D)) and not((tmp_37_reg_14631 = ap_const_lv4_C)) and not((tmp_37_reg_14631 = ap_const_lv4_B)) and not((tmp_37_reg_14631 = ap_const_lv4_A)) and not((tmp_37_reg_14631 = ap_const_lv4_9)) and not((tmp_37_reg_14631 = ap_const_lv4_8)) and not((tmp_37_reg_14631 = ap_const_lv4_7)) and not((tmp_37_reg_14631 = ap_const_lv4_6)) and not((tmp_37_reg_14631 = ap_const_lv4_5)) and not((tmp_37_reg_14631 = ap_const_lv4_4)) and not((tmp_37_reg_14631 = ap_const_lv4_3)) and not((tmp_37_reg_14631 = ap_const_lv4_2)) and not((tmp_37_reg_14631 = ap_const_lv4_1)) and not((tmp_37_reg_14631 = ap_const_lv4_0))) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_E)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_D)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_C)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_B)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_A)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_9)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_8)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_7)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_6)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_4)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_3)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_2)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_1)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_0)) or ((ap_ST_st30_fsm_29 = ap_CS_fsm) and not((ap_const_lv1_0 = end_0_reg_5841))))) then
state_5_4_reg_9292 <= state_5_2_reg_4761;
end if;
end if;
end process;
-- state_6_1_reg_3830 assign process. --
state_6_1_reg_3830_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ST_st44_fsm_43 = ap_CS_fsm) and not((ap_const_lv1_0 = exitcond_fu_13718_p2)) and (ap_const_lv1_0 = all_end_phi_fu_12651_p36))) then
state_6_1_reg_3830 <= state_6_2_reg_4746;
elsif (((ap_ST_st8_fsm_7 = ap_CS_fsm) and not((exitcond2_fu_13247_p2 = ap_const_lv1_0)))) then
state_6_1_reg_3830 <= state_6_s_reg_732;
end if;
end if;
end process;
-- state_6_2_reg_4746 assign process. --
state_6_2_reg_4746_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ST_st43_fsm_42 = ap_CS_fsm) or ((ap_ST_st32_fsm_31 = ap_CS_fsm) and ((not((ap_const_lv1_0 = end_load_3_phi_phi_fu_11584_p32)) and (ap_const_lv1_0 = brmerge_demorgan_reg_14680)) or (not((ap_const_lv1_0 = end_load_3_phi_phi_fu_11584_p32)) and not((ap_const_lv1_0 = tmp1_fu_13626_p2))))))) then
state_6_2_reg_4746 <= state_6_4_reg_9234;
elsif ((ap_ST_st18_fsm_17 = ap_CS_fsm)) then
state_6_2_reg_4746 <= state_6_1_reg_3830;
end if;
end if;
end process;
-- state_6_4_reg_9234 assign process. --
state_6_4_reg_9234_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_6))) then
state_6_4_reg_9234 <= state_0_fu_13574_p2;
elsif ((((ap_ST_st22_fsm_21 = ap_CS_fsm) and not((tmp_37_reg_14631 = ap_const_lv4_E)) and not((tmp_37_reg_14631 = ap_const_lv4_D)) and not((tmp_37_reg_14631 = ap_const_lv4_C)) and not((tmp_37_reg_14631 = ap_const_lv4_B)) and not((tmp_37_reg_14631 = ap_const_lv4_A)) and not((tmp_37_reg_14631 = ap_const_lv4_9)) and not((tmp_37_reg_14631 = ap_const_lv4_8)) and not((tmp_37_reg_14631 = ap_const_lv4_7)) and not((tmp_37_reg_14631 = ap_const_lv4_6)) and not((tmp_37_reg_14631 = ap_const_lv4_5)) and not((tmp_37_reg_14631 = ap_const_lv4_4)) and not((tmp_37_reg_14631 = ap_const_lv4_3)) and not((tmp_37_reg_14631 = ap_const_lv4_2)) and not((tmp_37_reg_14631 = ap_const_lv4_1)) and not((tmp_37_reg_14631 = ap_const_lv4_0))) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_E)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_D)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_C)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_B)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_A)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_9)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_8)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_7)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_5)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_4)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_3)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_2)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_1)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_0)) or ((ap_ST_st30_fsm_29 = ap_CS_fsm) and not((ap_const_lv1_0 = end_0_reg_5841))))) then
state_6_4_reg_9234 <= state_6_2_reg_4746;
end if;
end if;
end process;
-- state_7_1_reg_3819 assign process. --
state_7_1_reg_3819_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ST_st44_fsm_43 = ap_CS_fsm) and not((ap_const_lv1_0 = exitcond_fu_13718_p2)) and (ap_const_lv1_0 = all_end_phi_fu_12651_p36))) then
state_7_1_reg_3819 <= state_7_2_reg_4731;
elsif (((ap_ST_st8_fsm_7 = ap_CS_fsm) and not((exitcond2_fu_13247_p2 = ap_const_lv1_0)))) then
state_7_1_reg_3819 <= state_7_s_reg_720;
end if;
end if;
end process;
-- state_7_2_reg_4731 assign process. --
state_7_2_reg_4731_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ST_st43_fsm_42 = ap_CS_fsm) or ((ap_ST_st32_fsm_31 = ap_CS_fsm) and ((not((ap_const_lv1_0 = end_load_3_phi_phi_fu_11584_p32)) and (ap_const_lv1_0 = brmerge_demorgan_reg_14680)) or (not((ap_const_lv1_0 = end_load_3_phi_phi_fu_11584_p32)) and not((ap_const_lv1_0 = tmp1_fu_13626_p2))))))) then
state_7_2_reg_4731 <= state_7_4_reg_9176;
elsif ((ap_ST_st18_fsm_17 = ap_CS_fsm)) then
state_7_2_reg_4731 <= state_7_1_reg_3819;
end if;
end if;
end process;
-- state_7_4_reg_9176 assign process. --
state_7_4_reg_9176_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_7))) then
state_7_4_reg_9176 <= state_0_fu_13574_p2;
elsif ((((ap_ST_st22_fsm_21 = ap_CS_fsm) and not((tmp_37_reg_14631 = ap_const_lv4_E)) and not((tmp_37_reg_14631 = ap_const_lv4_D)) and not((tmp_37_reg_14631 = ap_const_lv4_C)) and not((tmp_37_reg_14631 = ap_const_lv4_B)) and not((tmp_37_reg_14631 = ap_const_lv4_A)) and not((tmp_37_reg_14631 = ap_const_lv4_9)) and not((tmp_37_reg_14631 = ap_const_lv4_8)) and not((tmp_37_reg_14631 = ap_const_lv4_7)) and not((tmp_37_reg_14631 = ap_const_lv4_6)) and not((tmp_37_reg_14631 = ap_const_lv4_5)) and not((tmp_37_reg_14631 = ap_const_lv4_4)) and not((tmp_37_reg_14631 = ap_const_lv4_3)) and not((tmp_37_reg_14631 = ap_const_lv4_2)) and not((tmp_37_reg_14631 = ap_const_lv4_1)) and not((tmp_37_reg_14631 = ap_const_lv4_0))) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_E)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_D)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_C)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_B)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_A)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_9)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_8)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_6)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_5)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_4)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_3)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_2)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_1)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_0)) or ((ap_ST_st30_fsm_29 = ap_CS_fsm) and not((ap_const_lv1_0 = end_0_reg_5841))))) then
state_7_4_reg_9176 <= state_7_2_reg_4731;
end if;
end if;
end process;
-- state_8_1_reg_3808 assign process. --
state_8_1_reg_3808_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ST_st44_fsm_43 = ap_CS_fsm) and not((ap_const_lv1_0 = exitcond_fu_13718_p2)) and (ap_const_lv1_0 = all_end_phi_fu_12651_p36))) then
state_8_1_reg_3808 <= state_8_2_reg_4716;
elsif (((ap_ST_st8_fsm_7 = ap_CS_fsm) and not((exitcond2_fu_13247_p2 = ap_const_lv1_0)))) then
state_8_1_reg_3808 <= state_8_s_reg_708;
end if;
end if;
end process;
-- state_8_2_reg_4716 assign process. --
state_8_2_reg_4716_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ST_st43_fsm_42 = ap_CS_fsm) or ((ap_ST_st32_fsm_31 = ap_CS_fsm) and ((not((ap_const_lv1_0 = end_load_3_phi_phi_fu_11584_p32)) and (ap_const_lv1_0 = brmerge_demorgan_reg_14680)) or (not((ap_const_lv1_0 = end_load_3_phi_phi_fu_11584_p32)) and not((ap_const_lv1_0 = tmp1_fu_13626_p2))))))) then
state_8_2_reg_4716 <= state_8_4_reg_9118;
elsif ((ap_ST_st18_fsm_17 = ap_CS_fsm)) then
state_8_2_reg_4716 <= state_8_1_reg_3808;
end if;
end if;
end process;
-- state_8_4_reg_9118 assign process. --
state_8_4_reg_9118_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_8))) then
state_8_4_reg_9118 <= state_0_fu_13574_p2;
elsif ((((ap_ST_st22_fsm_21 = ap_CS_fsm) and not((tmp_37_reg_14631 = ap_const_lv4_E)) and not((tmp_37_reg_14631 = ap_const_lv4_D)) and not((tmp_37_reg_14631 = ap_const_lv4_C)) and not((tmp_37_reg_14631 = ap_const_lv4_B)) and not((tmp_37_reg_14631 = ap_const_lv4_A)) and not((tmp_37_reg_14631 = ap_const_lv4_9)) and not((tmp_37_reg_14631 = ap_const_lv4_8)) and not((tmp_37_reg_14631 = ap_const_lv4_7)) and not((tmp_37_reg_14631 = ap_const_lv4_6)) and not((tmp_37_reg_14631 = ap_const_lv4_5)) and not((tmp_37_reg_14631 = ap_const_lv4_4)) and not((tmp_37_reg_14631 = ap_const_lv4_3)) and not((tmp_37_reg_14631 = ap_const_lv4_2)) and not((tmp_37_reg_14631 = ap_const_lv4_1)) and not((tmp_37_reg_14631 = ap_const_lv4_0))) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_E)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_D)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_C)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_B)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_A)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_9)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_7)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_6)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_5)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_4)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_3)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_2)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_1)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_0)) or ((ap_ST_st30_fsm_29 = ap_CS_fsm) and not((ap_const_lv1_0 = end_0_reg_5841))))) then
state_8_4_reg_9118 <= state_8_2_reg_4716;
end if;
end if;
end process;
-- state_9_1_reg_3797 assign process. --
state_9_1_reg_3797_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ST_st44_fsm_43 = ap_CS_fsm) and not((ap_const_lv1_0 = exitcond_fu_13718_p2)) and (ap_const_lv1_0 = all_end_phi_fu_12651_p36))) then
state_9_1_reg_3797 <= state_9_2_reg_4701;
elsif (((ap_ST_st8_fsm_7 = ap_CS_fsm) and not((exitcond2_fu_13247_p2 = ap_const_lv1_0)))) then
state_9_1_reg_3797 <= state_9_s_reg_696;
end if;
end if;
end process;
-- state_9_2_reg_4701 assign process. --
state_9_2_reg_4701_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ST_st43_fsm_42 = ap_CS_fsm) or ((ap_ST_st32_fsm_31 = ap_CS_fsm) and ((not((ap_const_lv1_0 = end_load_3_phi_phi_fu_11584_p32)) and (ap_const_lv1_0 = brmerge_demorgan_reg_14680)) or (not((ap_const_lv1_0 = end_load_3_phi_phi_fu_11584_p32)) and not((ap_const_lv1_0 = tmp1_fu_13626_p2))))))) then
state_9_2_reg_4701 <= state_9_4_reg_9060;
elsif ((ap_ST_st18_fsm_17 = ap_CS_fsm)) then
state_9_2_reg_4701 <= state_9_1_reg_3797;
end if;
end if;
end process;
-- state_9_4_reg_9060 assign process. --
state_9_4_reg_9060_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_9))) then
state_9_4_reg_9060 <= state_0_fu_13574_p2;
elsif ((((ap_ST_st22_fsm_21 = ap_CS_fsm) and not((tmp_37_reg_14631 = ap_const_lv4_E)) and not((tmp_37_reg_14631 = ap_const_lv4_D)) and not((tmp_37_reg_14631 = ap_const_lv4_C)) and not((tmp_37_reg_14631 = ap_const_lv4_B)) and not((tmp_37_reg_14631 = ap_const_lv4_A)) and not((tmp_37_reg_14631 = ap_const_lv4_9)) and not((tmp_37_reg_14631 = ap_const_lv4_8)) and not((tmp_37_reg_14631 = ap_const_lv4_7)) and not((tmp_37_reg_14631 = ap_const_lv4_6)) and not((tmp_37_reg_14631 = ap_const_lv4_5)) and not((tmp_37_reg_14631 = ap_const_lv4_4)) and not((tmp_37_reg_14631 = ap_const_lv4_3)) and not((tmp_37_reg_14631 = ap_const_lv4_2)) and not((tmp_37_reg_14631 = ap_const_lv4_1)) and not((tmp_37_reg_14631 = ap_const_lv4_0))) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_E)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_D)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_C)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_B)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_A)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_8)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_7)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_6)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_5)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_4)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_3)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_2)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_1)) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_0)) or ((ap_ST_st30_fsm_29 = ap_CS_fsm) and not((ap_const_lv1_0 = end_0_reg_5841))))) then
state_9_4_reg_9060 <= state_9_2_reg_4701;
end if;
end if;
end process;
-- state_assign_in_reg_12551 assign process. --
state_assign_in_reg_12551_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_sig_bdd_369) then
if ((tmp_37_reg_14631 = ap_const_lv4_0)) then
state_assign_in_reg_12551 <= state_0_4_reg_9582;
elsif ((tmp_37_reg_14631 = ap_const_lv4_E)) then
state_assign_in_reg_12551 <= state_14_4_reg_8770;
elsif ((tmp_37_reg_14631 = ap_const_lv4_D)) then
state_assign_in_reg_12551 <= state_13_4_reg_8828;
elsif ((tmp_37_reg_14631 = ap_const_lv4_C)) then
state_assign_in_reg_12551 <= state_12_4_reg_8886;
elsif ((tmp_37_reg_14631 = ap_const_lv4_B)) then
state_assign_in_reg_12551 <= state_11_4_reg_8944;
elsif ((tmp_37_reg_14631 = ap_const_lv4_A)) then
state_assign_in_reg_12551 <= state_10_4_reg_9002;
elsif ((tmp_37_reg_14631 = ap_const_lv4_9)) then
state_assign_in_reg_12551 <= state_9_4_reg_9060;
elsif ((tmp_37_reg_14631 = ap_const_lv4_8)) then
state_assign_in_reg_12551 <= state_8_4_reg_9118;
elsif ((tmp_37_reg_14631 = ap_const_lv4_7)) then
state_assign_in_reg_12551 <= state_7_4_reg_9176;
elsif ((tmp_37_reg_14631 = ap_const_lv4_6)) then
state_assign_in_reg_12551 <= state_6_4_reg_9234;
elsif ((tmp_37_reg_14631 = ap_const_lv4_5)) then
state_assign_in_reg_12551 <= state_5_4_reg_9292;
elsif ((tmp_37_reg_14631 = ap_const_lv4_4)) then
state_assign_in_reg_12551 <= state_4_4_reg_9350;
elsif ((tmp_37_reg_14631 = ap_const_lv4_3)) then
state_assign_in_reg_12551 <= state_3_4_reg_9408;
elsif ((tmp_37_reg_14631 = ap_const_lv4_2)) then
state_assign_in_reg_12551 <= state_2_4_reg_9466;
elsif ((tmp_37_reg_14631 = ap_const_lv4_1)) then
state_assign_in_reg_12551 <= state_1_4_reg_9524;
elsif ((ap_true = ap_true)) then
state_assign_in_reg_12551 <= state_15_4_reg_8712;
end if;
end if;
end if;
end process;
-- sym_offset_0_1_reg_1902 assign process. --
sym_offset_0_1_reg_1902_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_ST_st17_fsm_16 = ap_CS_fsm)) then
sym_offset_0_1_reg_1902 <= sym_offset_0_2_reg_2734;
elsif (((ap_ST_st7_fsm_6 = ap_CS_fsm) and (ap_const_lv1_0 = tmp_6_fu_13097_p2))) then
sym_offset_0_1_reg_1902 <= sym_offset_reg_1380;
end if;
end if;
end process;
-- sym_offset_0_2_reg_2734 assign process. --
sym_offset_0_2_reg_2734_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ST_st9_fsm_8 = ap_CS_fsm) and (tmp_36_reg_14538 = ap_const_lv4_0))) then
sym_offset_0_2_reg_2734 <= start_indices_q0;
elsif (((ap_ST_st9_fsm_8 = ap_CS_fsm) or ((ap_ST_st9_fsm_8 = ap_CS_fsm) and (tmp_36_reg_14538 = ap_const_lv4_E)) or ((ap_ST_st9_fsm_8 = ap_CS_fsm) and (tmp_36_reg_14538 = ap_const_lv4_D)) or ((ap_ST_st9_fsm_8 = ap_CS_fsm) and (tmp_36_reg_14538 = ap_const_lv4_C)) or ((ap_ST_st9_fsm_8 = ap_CS_fsm) and (tmp_36_reg_14538 = ap_const_lv4_B)) or ((ap_ST_st9_fsm_8 = ap_CS_fsm) and (tmp_36_reg_14538 = ap_const_lv4_A)) or ((ap_ST_st9_fsm_8 = ap_CS_fsm) and (tmp_36_reg_14538 = ap_const_lv4_9)) or ((ap_ST_st9_fsm_8 = ap_CS_fsm) and (tmp_36_reg_14538 = ap_const_lv4_8)) or ((ap_ST_st9_fsm_8 = ap_CS_fsm) and (tmp_36_reg_14538 = ap_const_lv4_7)) or ((ap_ST_st9_fsm_8 = ap_CS_fsm) and (tmp_36_reg_14538 = ap_const_lv4_6)) or ((ap_ST_st9_fsm_8 = ap_CS_fsm) and (tmp_36_reg_14538 = ap_const_lv4_5)) or ((ap_ST_st9_fsm_8 = ap_CS_fsm) and (tmp_36_reg_14538 = ap_const_lv4_4)) or ((ap_ST_st9_fsm_8 = ap_CS_fsm) and (tmp_36_reg_14538 = ap_const_lv4_3)) or ((ap_ST_st9_fsm_8 = ap_CS_fsm) and (tmp_36_reg_14538 = ap_const_lv4_2)) or ((ap_ST_st9_fsm_8 = ap_CS_fsm) and (tmp_36_reg_14538 = ap_const_lv4_1)))) then
sym_offset_0_2_reg_2734 <= sym_offset_0_1_reg_1902;
end if;
end if;
end process;
-- sym_offset_0_3_reg_4424 assign process. --
sym_offset_0_3_reg_4424_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ST_st44_fsm_43 = ap_CS_fsm) and not((ap_const_lv1_0 = exitcond_fu_13718_p2)) and (ap_const_lv1_0 = all_end_phi_fu_12651_p36))) then
sym_offset_0_3_reg_4424 <= sym_offset_0_4_reg_5571;
elsif (((ap_ST_st8_fsm_7 = ap_CS_fsm) and not((exitcond2_fu_13247_p2 = ap_const_lv1_0)))) then
sym_offset_0_3_reg_4424 <= sym_offset_0_1_reg_1902;
end if;
end if;
end process;
-- sym_offset_0_4_reg_5571 assign process. --
sym_offset_0_4_reg_5571_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_ST_st43_fsm_42 = ap_CS_fsm)) then
sym_offset_0_4_reg_5571 <= sym_offset_0_5_reg_12497;
elsif (((ap_ST_st32_fsm_31 = ap_CS_fsm) and ((not((ap_const_lv1_0 = end_load_3_phi_phi_fu_11584_p32)) and (ap_const_lv1_0 = brmerge_demorgan_reg_14680)) or (not((ap_const_lv1_0 = end_load_3_phi_phi_fu_11584_p32)) and not((ap_const_lv1_0 = tmp1_fu_13626_p2)))))) then
sym_offset_0_4_reg_5571 <= sym_offset_0_4_reg_5571;
elsif ((ap_ST_st18_fsm_17 = ap_CS_fsm)) then
sym_offset_0_4_reg_5571 <= sym_offset_0_3_reg_4424;
end if;
end if;
end process;
-- sym_offset_0_5_reg_12497 assign process. --
sym_offset_0_5_reg_12497_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ST_st33_fsm_32 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_0))) then
sym_offset_0_5_reg_12497 <= sym_offset_0_1_25_fu_13631_p2;
elsif (((ap_ST_st33_fsm_32 = ap_CS_fsm) or ((ap_ST_st33_fsm_32 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_E)) or ((ap_ST_st33_fsm_32 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_D)) or ((ap_ST_st33_fsm_32 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_C)) or ((ap_ST_st33_fsm_32 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_B)) or ((ap_ST_st33_fsm_32 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_A)) or ((ap_ST_st33_fsm_32 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_9)) or ((ap_ST_st33_fsm_32 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_8)) or ((ap_ST_st33_fsm_32 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_7)) or ((ap_ST_st33_fsm_32 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_6)) or ((ap_ST_st33_fsm_32 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_5)) or ((ap_ST_st33_fsm_32 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_4)) or ((ap_ST_st33_fsm_32 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_3)) or ((ap_ST_st33_fsm_32 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_2)) or ((ap_ST_st33_fsm_32 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_1)))) then
sym_offset_0_5_reg_12497 <= sym_offset_0_4_reg_5571;
end if;
end if;
end process;
-- sym_offset_10_1_reg_1792 assign process. --
sym_offset_10_1_reg_1792_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_ST_st17_fsm_16 = ap_CS_fsm)) then
sym_offset_10_1_reg_1792 <= sym_offset_10_2_reg_2194;
elsif (((ap_ST_st7_fsm_6 = ap_CS_fsm) and (ap_const_lv1_0 = tmp_6_fu_13097_p2))) then
sym_offset_10_1_reg_1792 <= sym_offset_10_reg_1260;
end if;
end if;
end process;
-- sym_offset_10_2_reg_2194 assign process. --
sym_offset_10_2_reg_2194_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ST_st9_fsm_8 = ap_CS_fsm) and (tmp_36_reg_14538 = ap_const_lv4_A))) then
sym_offset_10_2_reg_2194 <= start_indices_q0;
elsif (((ap_ST_st9_fsm_8 = ap_CS_fsm) or ((ap_ST_st9_fsm_8 = ap_CS_fsm) and (tmp_36_reg_14538 = ap_const_lv4_E)) or ((ap_ST_st9_fsm_8 = ap_CS_fsm) and (tmp_36_reg_14538 = ap_const_lv4_D)) or ((ap_ST_st9_fsm_8 = ap_CS_fsm) and (tmp_36_reg_14538 = ap_const_lv4_C)) or ((ap_ST_st9_fsm_8 = ap_CS_fsm) and (tmp_36_reg_14538 = ap_const_lv4_B)) or ((ap_ST_st9_fsm_8 = ap_CS_fsm) and (tmp_36_reg_14538 = ap_const_lv4_9)) or ((ap_ST_st9_fsm_8 = ap_CS_fsm) and (tmp_36_reg_14538 = ap_const_lv4_8)) or ((ap_ST_st9_fsm_8 = ap_CS_fsm) and (tmp_36_reg_14538 = ap_const_lv4_7)) or ((ap_ST_st9_fsm_8 = ap_CS_fsm) and (tmp_36_reg_14538 = ap_const_lv4_6)) or ((ap_ST_st9_fsm_8 = ap_CS_fsm) and (tmp_36_reg_14538 = ap_const_lv4_5)) or ((ap_ST_st9_fsm_8 = ap_CS_fsm) and (tmp_36_reg_14538 = ap_const_lv4_4)) or ((ap_ST_st9_fsm_8 = ap_CS_fsm) and (tmp_36_reg_14538 = ap_const_lv4_3)) or ((ap_ST_st9_fsm_8 = ap_CS_fsm) and (tmp_36_reg_14538 = ap_const_lv4_2)) or ((ap_ST_st9_fsm_8 = ap_CS_fsm) and (tmp_36_reg_14538 = ap_const_lv4_1)) or ((ap_ST_st9_fsm_8 = ap_CS_fsm) and (tmp_36_reg_14538 = ap_const_lv4_0)))) then
sym_offset_10_2_reg_2194 <= sym_offset_10_1_reg_1792;
end if;
end if;
end process;
-- sym_offset_10_3_reg_4314 assign process. --
sym_offset_10_3_reg_4314_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ST_st44_fsm_43 = ap_CS_fsm) and not((ap_const_lv1_0 = exitcond_fu_13718_p2)) and (ap_const_lv1_0 = all_end_phi_fu_12651_p36))) then
sym_offset_10_3_reg_4314 <= sym_offset_10_4_reg_5411;
elsif (((ap_ST_st8_fsm_7 = ap_CS_fsm) and not((exitcond2_fu_13247_p2 = ap_const_lv1_0)))) then
sym_offset_10_3_reg_4314 <= sym_offset_10_1_reg_1792;
end if;
end if;
end process;
-- sym_offset_10_4_reg_5411 assign process. --
sym_offset_10_4_reg_5411_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_ST_st43_fsm_42 = ap_CS_fsm)) then
sym_offset_10_4_reg_5411 <= sym_offset_10_5_reg_11957;
elsif (((ap_ST_st32_fsm_31 = ap_CS_fsm) and ((not((ap_const_lv1_0 = end_load_3_phi_phi_fu_11584_p32)) and (ap_const_lv1_0 = brmerge_demorgan_reg_14680)) or (not((ap_const_lv1_0 = end_load_3_phi_phi_fu_11584_p32)) and not((ap_const_lv1_0 = tmp1_fu_13626_p2)))))) then
sym_offset_10_4_reg_5411 <= sym_offset_10_4_reg_5411;
elsif ((ap_ST_st18_fsm_17 = ap_CS_fsm)) then
sym_offset_10_4_reg_5411 <= sym_offset_10_3_reg_4314;
end if;
end if;
end process;
-- sym_offset_10_5_reg_11957 assign process. --
sym_offset_10_5_reg_11957_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ST_st33_fsm_32 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_A))) then
sym_offset_10_5_reg_11957 <= sym_offset_0_1_25_fu_13631_p2;
elsif (((ap_ST_st33_fsm_32 = ap_CS_fsm) or ((ap_ST_st33_fsm_32 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_E)) or ((ap_ST_st33_fsm_32 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_D)) or ((ap_ST_st33_fsm_32 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_C)) or ((ap_ST_st33_fsm_32 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_B)) or ((ap_ST_st33_fsm_32 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_9)) or ((ap_ST_st33_fsm_32 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_8)) or ((ap_ST_st33_fsm_32 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_7)) or ((ap_ST_st33_fsm_32 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_6)) or ((ap_ST_st33_fsm_32 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_5)) or ((ap_ST_st33_fsm_32 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_4)) or ((ap_ST_st33_fsm_32 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_3)) or ((ap_ST_st33_fsm_32 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_2)) or ((ap_ST_st33_fsm_32 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_1)) or ((ap_ST_st33_fsm_32 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_0)))) then
sym_offset_10_5_reg_11957 <= sym_offset_10_4_reg_5411;
end if;
end if;
end process;
-- sym_offset_11_1_reg_1781 assign process. --
sym_offset_11_1_reg_1781_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_ST_st17_fsm_16 = ap_CS_fsm)) then
sym_offset_11_1_reg_1781 <= sym_offset_11_2_reg_2140;
elsif (((ap_ST_st7_fsm_6 = ap_CS_fsm) and (ap_const_lv1_0 = tmp_6_fu_13097_p2))) then
sym_offset_11_1_reg_1781 <= sym_offset_11_reg_1248;
end if;
end if;
end process;
-- sym_offset_11_2_reg_2140 assign process. --
sym_offset_11_2_reg_2140_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ST_st9_fsm_8 = ap_CS_fsm) and (tmp_36_reg_14538 = ap_const_lv4_B))) then
sym_offset_11_2_reg_2140 <= start_indices_q0;
elsif (((ap_ST_st9_fsm_8 = ap_CS_fsm) or ((ap_ST_st9_fsm_8 = ap_CS_fsm) and (tmp_36_reg_14538 = ap_const_lv4_E)) or ((ap_ST_st9_fsm_8 = ap_CS_fsm) and (tmp_36_reg_14538 = ap_const_lv4_D)) or ((ap_ST_st9_fsm_8 = ap_CS_fsm) and (tmp_36_reg_14538 = ap_const_lv4_C)) or ((ap_ST_st9_fsm_8 = ap_CS_fsm) and (tmp_36_reg_14538 = ap_const_lv4_A)) or ((ap_ST_st9_fsm_8 = ap_CS_fsm) and (tmp_36_reg_14538 = ap_const_lv4_9)) or ((ap_ST_st9_fsm_8 = ap_CS_fsm) and (tmp_36_reg_14538 = ap_const_lv4_8)) or ((ap_ST_st9_fsm_8 = ap_CS_fsm) and (tmp_36_reg_14538 = ap_const_lv4_7)) or ((ap_ST_st9_fsm_8 = ap_CS_fsm) and (tmp_36_reg_14538 = ap_const_lv4_6)) or ((ap_ST_st9_fsm_8 = ap_CS_fsm) and (tmp_36_reg_14538 = ap_const_lv4_5)) or ((ap_ST_st9_fsm_8 = ap_CS_fsm) and (tmp_36_reg_14538 = ap_const_lv4_4)) or ((ap_ST_st9_fsm_8 = ap_CS_fsm) and (tmp_36_reg_14538 = ap_const_lv4_3)) or ((ap_ST_st9_fsm_8 = ap_CS_fsm) and (tmp_36_reg_14538 = ap_const_lv4_2)) or ((ap_ST_st9_fsm_8 = ap_CS_fsm) and (tmp_36_reg_14538 = ap_const_lv4_1)) or ((ap_ST_st9_fsm_8 = ap_CS_fsm) and (tmp_36_reg_14538 = ap_const_lv4_0)))) then
sym_offset_11_2_reg_2140 <= sym_offset_11_1_reg_1781;
end if;
end if;
end process;
-- sym_offset_11_3_reg_4303 assign process. --
sym_offset_11_3_reg_4303_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ST_st44_fsm_43 = ap_CS_fsm) and not((ap_const_lv1_0 = exitcond_fu_13718_p2)) and (ap_const_lv1_0 = all_end_phi_fu_12651_p36))) then
sym_offset_11_3_reg_4303 <= sym_offset_11_4_reg_5395;
elsif (((ap_ST_st8_fsm_7 = ap_CS_fsm) and not((exitcond2_fu_13247_p2 = ap_const_lv1_0)))) then
sym_offset_11_3_reg_4303 <= sym_offset_11_1_reg_1781;
end if;
end if;
end process;
-- sym_offset_11_4_reg_5395 assign process. --
sym_offset_11_4_reg_5395_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_ST_st43_fsm_42 = ap_CS_fsm)) then
sym_offset_11_4_reg_5395 <= sym_offset_11_5_reg_11903;
elsif (((ap_ST_st32_fsm_31 = ap_CS_fsm) and ((not((ap_const_lv1_0 = end_load_3_phi_phi_fu_11584_p32)) and (ap_const_lv1_0 = brmerge_demorgan_reg_14680)) or (not((ap_const_lv1_0 = end_load_3_phi_phi_fu_11584_p32)) and not((ap_const_lv1_0 = tmp1_fu_13626_p2)))))) then
sym_offset_11_4_reg_5395 <= sym_offset_11_4_reg_5395;
elsif ((ap_ST_st18_fsm_17 = ap_CS_fsm)) then
sym_offset_11_4_reg_5395 <= sym_offset_11_3_reg_4303;
end if;
end if;
end process;
-- sym_offset_11_5_reg_11903 assign process. --
sym_offset_11_5_reg_11903_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ST_st33_fsm_32 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_B))) then
sym_offset_11_5_reg_11903 <= sym_offset_0_1_25_fu_13631_p2;
elsif (((ap_ST_st33_fsm_32 = ap_CS_fsm) or ((ap_ST_st33_fsm_32 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_E)) or ((ap_ST_st33_fsm_32 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_D)) or ((ap_ST_st33_fsm_32 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_C)) or ((ap_ST_st33_fsm_32 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_A)) or ((ap_ST_st33_fsm_32 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_9)) or ((ap_ST_st33_fsm_32 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_8)) or ((ap_ST_st33_fsm_32 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_7)) or ((ap_ST_st33_fsm_32 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_6)) or ((ap_ST_st33_fsm_32 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_5)) or ((ap_ST_st33_fsm_32 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_4)) or ((ap_ST_st33_fsm_32 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_3)) or ((ap_ST_st33_fsm_32 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_2)) or ((ap_ST_st33_fsm_32 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_1)) or ((ap_ST_st33_fsm_32 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_0)))) then
sym_offset_11_5_reg_11903 <= sym_offset_11_4_reg_5395;
end if;
end if;
end process;
-- sym_offset_12_1_reg_1770 assign process. --
sym_offset_12_1_reg_1770_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_ST_st17_fsm_16 = ap_CS_fsm)) then
sym_offset_12_1_reg_1770 <= sym_offset_12_2_reg_2086;
elsif (((ap_ST_st7_fsm_6 = ap_CS_fsm) and (ap_const_lv1_0 = tmp_6_fu_13097_p2))) then
sym_offset_12_1_reg_1770 <= sym_offset_12_reg_1236;
end if;
end if;
end process;
-- sym_offset_12_2_reg_2086 assign process. --
sym_offset_12_2_reg_2086_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ST_st9_fsm_8 = ap_CS_fsm) and (tmp_36_reg_14538 = ap_const_lv4_C))) then
sym_offset_12_2_reg_2086 <= start_indices_q0;
elsif (((ap_ST_st9_fsm_8 = ap_CS_fsm) or ((ap_ST_st9_fsm_8 = ap_CS_fsm) and (tmp_36_reg_14538 = ap_const_lv4_E)) or ((ap_ST_st9_fsm_8 = ap_CS_fsm) and (tmp_36_reg_14538 = ap_const_lv4_D)) or ((ap_ST_st9_fsm_8 = ap_CS_fsm) and (tmp_36_reg_14538 = ap_const_lv4_B)) or ((ap_ST_st9_fsm_8 = ap_CS_fsm) and (tmp_36_reg_14538 = ap_const_lv4_A)) or ((ap_ST_st9_fsm_8 = ap_CS_fsm) and (tmp_36_reg_14538 = ap_const_lv4_9)) or ((ap_ST_st9_fsm_8 = ap_CS_fsm) and (tmp_36_reg_14538 = ap_const_lv4_8)) or ((ap_ST_st9_fsm_8 = ap_CS_fsm) and (tmp_36_reg_14538 = ap_const_lv4_7)) or ((ap_ST_st9_fsm_8 = ap_CS_fsm) and (tmp_36_reg_14538 = ap_const_lv4_6)) or ((ap_ST_st9_fsm_8 = ap_CS_fsm) and (tmp_36_reg_14538 = ap_const_lv4_5)) or ((ap_ST_st9_fsm_8 = ap_CS_fsm) and (tmp_36_reg_14538 = ap_const_lv4_4)) or ((ap_ST_st9_fsm_8 = ap_CS_fsm) and (tmp_36_reg_14538 = ap_const_lv4_3)) or ((ap_ST_st9_fsm_8 = ap_CS_fsm) and (tmp_36_reg_14538 = ap_const_lv4_2)) or ((ap_ST_st9_fsm_8 = ap_CS_fsm) and (tmp_36_reg_14538 = ap_const_lv4_1)) or ((ap_ST_st9_fsm_8 = ap_CS_fsm) and (tmp_36_reg_14538 = ap_const_lv4_0)))) then
sym_offset_12_2_reg_2086 <= sym_offset_12_1_reg_1770;
end if;
end if;
end process;
-- sym_offset_12_3_reg_4292 assign process. --
sym_offset_12_3_reg_4292_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ST_st44_fsm_43 = ap_CS_fsm) and not((ap_const_lv1_0 = exitcond_fu_13718_p2)) and (ap_const_lv1_0 = all_end_phi_fu_12651_p36))) then
sym_offset_12_3_reg_4292 <= sym_offset_12_4_reg_5379;
elsif (((ap_ST_st8_fsm_7 = ap_CS_fsm) and not((exitcond2_fu_13247_p2 = ap_const_lv1_0)))) then
sym_offset_12_3_reg_4292 <= sym_offset_12_1_reg_1770;
end if;
end if;
end process;
-- sym_offset_12_4_reg_5379 assign process. --
sym_offset_12_4_reg_5379_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_ST_st43_fsm_42 = ap_CS_fsm)) then
sym_offset_12_4_reg_5379 <= sym_offset_12_5_reg_11849;
elsif (((ap_ST_st32_fsm_31 = ap_CS_fsm) and ((not((ap_const_lv1_0 = end_load_3_phi_phi_fu_11584_p32)) and (ap_const_lv1_0 = brmerge_demorgan_reg_14680)) or (not((ap_const_lv1_0 = end_load_3_phi_phi_fu_11584_p32)) and not((ap_const_lv1_0 = tmp1_fu_13626_p2)))))) then
sym_offset_12_4_reg_5379 <= sym_offset_12_4_reg_5379;
elsif ((ap_ST_st18_fsm_17 = ap_CS_fsm)) then
sym_offset_12_4_reg_5379 <= sym_offset_12_3_reg_4292;
end if;
end if;
end process;
-- sym_offset_12_5_reg_11849 assign process. --
sym_offset_12_5_reg_11849_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ST_st33_fsm_32 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_C))) then
sym_offset_12_5_reg_11849 <= sym_offset_0_1_25_fu_13631_p2;
elsif (((ap_ST_st33_fsm_32 = ap_CS_fsm) or ((ap_ST_st33_fsm_32 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_E)) or ((ap_ST_st33_fsm_32 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_D)) or ((ap_ST_st33_fsm_32 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_B)) or ((ap_ST_st33_fsm_32 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_A)) or ((ap_ST_st33_fsm_32 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_9)) or ((ap_ST_st33_fsm_32 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_8)) or ((ap_ST_st33_fsm_32 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_7)) or ((ap_ST_st33_fsm_32 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_6)) or ((ap_ST_st33_fsm_32 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_5)) or ((ap_ST_st33_fsm_32 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_4)) or ((ap_ST_st33_fsm_32 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_3)) or ((ap_ST_st33_fsm_32 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_2)) or ((ap_ST_st33_fsm_32 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_1)) or ((ap_ST_st33_fsm_32 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_0)))) then
sym_offset_12_5_reg_11849 <= sym_offset_12_4_reg_5379;
end if;
end if;
end process;
-- sym_offset_13_1_reg_1759 assign process. --
sym_offset_13_1_reg_1759_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_ST_st17_fsm_16 = ap_CS_fsm)) then
sym_offset_13_1_reg_1759 <= sym_offset_13_2_reg_2032;
elsif (((ap_ST_st7_fsm_6 = ap_CS_fsm) and (ap_const_lv1_0 = tmp_6_fu_13097_p2))) then
sym_offset_13_1_reg_1759 <= sym_offset_13_reg_1224;
end if;
end if;
end process;
-- sym_offset_13_2_reg_2032 assign process. --
sym_offset_13_2_reg_2032_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ST_st9_fsm_8 = ap_CS_fsm) and (tmp_36_reg_14538 = ap_const_lv4_D))) then
sym_offset_13_2_reg_2032 <= start_indices_q0;
elsif (((ap_ST_st9_fsm_8 = ap_CS_fsm) or ((ap_ST_st9_fsm_8 = ap_CS_fsm) and (tmp_36_reg_14538 = ap_const_lv4_E)) or ((ap_ST_st9_fsm_8 = ap_CS_fsm) and (tmp_36_reg_14538 = ap_const_lv4_C)) or ((ap_ST_st9_fsm_8 = ap_CS_fsm) and (tmp_36_reg_14538 = ap_const_lv4_B)) or ((ap_ST_st9_fsm_8 = ap_CS_fsm) and (tmp_36_reg_14538 = ap_const_lv4_A)) or ((ap_ST_st9_fsm_8 = ap_CS_fsm) and (tmp_36_reg_14538 = ap_const_lv4_9)) or ((ap_ST_st9_fsm_8 = ap_CS_fsm) and (tmp_36_reg_14538 = ap_const_lv4_8)) or ((ap_ST_st9_fsm_8 = ap_CS_fsm) and (tmp_36_reg_14538 = ap_const_lv4_7)) or ((ap_ST_st9_fsm_8 = ap_CS_fsm) and (tmp_36_reg_14538 = ap_const_lv4_6)) or ((ap_ST_st9_fsm_8 = ap_CS_fsm) and (tmp_36_reg_14538 = ap_const_lv4_5)) or ((ap_ST_st9_fsm_8 = ap_CS_fsm) and (tmp_36_reg_14538 = ap_const_lv4_4)) or ((ap_ST_st9_fsm_8 = ap_CS_fsm) and (tmp_36_reg_14538 = ap_const_lv4_3)) or ((ap_ST_st9_fsm_8 = ap_CS_fsm) and (tmp_36_reg_14538 = ap_const_lv4_2)) or ((ap_ST_st9_fsm_8 = ap_CS_fsm) and (tmp_36_reg_14538 = ap_const_lv4_1)) or ((ap_ST_st9_fsm_8 = ap_CS_fsm) and (tmp_36_reg_14538 = ap_const_lv4_0)))) then
sym_offset_13_2_reg_2032 <= sym_offset_13_1_reg_1759;
end if;
end if;
end process;
-- sym_offset_13_3_reg_4281 assign process. --
sym_offset_13_3_reg_4281_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ST_st44_fsm_43 = ap_CS_fsm) and not((ap_const_lv1_0 = exitcond_fu_13718_p2)) and (ap_const_lv1_0 = all_end_phi_fu_12651_p36))) then
sym_offset_13_3_reg_4281 <= sym_offset_13_4_reg_5363;
elsif (((ap_ST_st8_fsm_7 = ap_CS_fsm) and not((exitcond2_fu_13247_p2 = ap_const_lv1_0)))) then
sym_offset_13_3_reg_4281 <= sym_offset_13_1_reg_1759;
end if;
end if;
end process;
-- sym_offset_13_4_reg_5363 assign process. --
sym_offset_13_4_reg_5363_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_ST_st43_fsm_42 = ap_CS_fsm)) then
sym_offset_13_4_reg_5363 <= sym_offset_13_5_reg_11795;
elsif (((ap_ST_st32_fsm_31 = ap_CS_fsm) and ((not((ap_const_lv1_0 = end_load_3_phi_phi_fu_11584_p32)) and (ap_const_lv1_0 = brmerge_demorgan_reg_14680)) or (not((ap_const_lv1_0 = end_load_3_phi_phi_fu_11584_p32)) and not((ap_const_lv1_0 = tmp1_fu_13626_p2)))))) then
sym_offset_13_4_reg_5363 <= sym_offset_13_4_reg_5363;
elsif ((ap_ST_st18_fsm_17 = ap_CS_fsm)) then
sym_offset_13_4_reg_5363 <= sym_offset_13_3_reg_4281;
end if;
end if;
end process;
-- sym_offset_13_5_reg_11795 assign process. --
sym_offset_13_5_reg_11795_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ST_st33_fsm_32 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_D))) then
sym_offset_13_5_reg_11795 <= sym_offset_0_1_25_fu_13631_p2;
elsif (((ap_ST_st33_fsm_32 = ap_CS_fsm) or ((ap_ST_st33_fsm_32 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_E)) or ((ap_ST_st33_fsm_32 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_C)) or ((ap_ST_st33_fsm_32 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_B)) or ((ap_ST_st33_fsm_32 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_A)) or ((ap_ST_st33_fsm_32 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_9)) or ((ap_ST_st33_fsm_32 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_8)) or ((ap_ST_st33_fsm_32 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_7)) or ((ap_ST_st33_fsm_32 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_6)) or ((ap_ST_st33_fsm_32 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_5)) or ((ap_ST_st33_fsm_32 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_4)) or ((ap_ST_st33_fsm_32 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_3)) or ((ap_ST_st33_fsm_32 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_2)) or ((ap_ST_st33_fsm_32 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_1)) or ((ap_ST_st33_fsm_32 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_0)))) then
sym_offset_13_5_reg_11795 <= sym_offset_13_4_reg_5363;
end if;
end if;
end process;
-- sym_offset_14_1_reg_1748 assign process. --
sym_offset_14_1_reg_1748_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_ST_st17_fsm_16 = ap_CS_fsm)) then
sym_offset_14_1_reg_1748 <= sym_offset_14_2_reg_1978;
elsif (((ap_ST_st7_fsm_6 = ap_CS_fsm) and (ap_const_lv1_0 = tmp_6_fu_13097_p2))) then
sym_offset_14_1_reg_1748 <= sym_offset_14_reg_1212;
end if;
end if;
end process;
-- sym_offset_14_2_reg_1978 assign process. --
sym_offset_14_2_reg_1978_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ST_st9_fsm_8 = ap_CS_fsm) and (tmp_36_reg_14538 = ap_const_lv4_E))) then
sym_offset_14_2_reg_1978 <= start_indices_q0;
elsif (((ap_ST_st9_fsm_8 = ap_CS_fsm) or ((ap_ST_st9_fsm_8 = ap_CS_fsm) and (tmp_36_reg_14538 = ap_const_lv4_D)) or ((ap_ST_st9_fsm_8 = ap_CS_fsm) and (tmp_36_reg_14538 = ap_const_lv4_C)) or ((ap_ST_st9_fsm_8 = ap_CS_fsm) and (tmp_36_reg_14538 = ap_const_lv4_B)) or ((ap_ST_st9_fsm_8 = ap_CS_fsm) and (tmp_36_reg_14538 = ap_const_lv4_A)) or ((ap_ST_st9_fsm_8 = ap_CS_fsm) and (tmp_36_reg_14538 = ap_const_lv4_9)) or ((ap_ST_st9_fsm_8 = ap_CS_fsm) and (tmp_36_reg_14538 = ap_const_lv4_8)) or ((ap_ST_st9_fsm_8 = ap_CS_fsm) and (tmp_36_reg_14538 = ap_const_lv4_7)) or ((ap_ST_st9_fsm_8 = ap_CS_fsm) and (tmp_36_reg_14538 = ap_const_lv4_6)) or ((ap_ST_st9_fsm_8 = ap_CS_fsm) and (tmp_36_reg_14538 = ap_const_lv4_5)) or ((ap_ST_st9_fsm_8 = ap_CS_fsm) and (tmp_36_reg_14538 = ap_const_lv4_4)) or ((ap_ST_st9_fsm_8 = ap_CS_fsm) and (tmp_36_reg_14538 = ap_const_lv4_3)) or ((ap_ST_st9_fsm_8 = ap_CS_fsm) and (tmp_36_reg_14538 = ap_const_lv4_2)) or ((ap_ST_st9_fsm_8 = ap_CS_fsm) and (tmp_36_reg_14538 = ap_const_lv4_1)) or ((ap_ST_st9_fsm_8 = ap_CS_fsm) and (tmp_36_reg_14538 = ap_const_lv4_0)))) then
sym_offset_14_2_reg_1978 <= sym_offset_14_1_reg_1748;
end if;
end if;
end process;
-- sym_offset_14_3_reg_4270 assign process. --
sym_offset_14_3_reg_4270_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ST_st44_fsm_43 = ap_CS_fsm) and not((ap_const_lv1_0 = exitcond_fu_13718_p2)) and (ap_const_lv1_0 = all_end_phi_fu_12651_p36))) then
sym_offset_14_3_reg_4270 <= sym_offset_14_4_reg_5347;
elsif (((ap_ST_st8_fsm_7 = ap_CS_fsm) and not((exitcond2_fu_13247_p2 = ap_const_lv1_0)))) then
sym_offset_14_3_reg_4270 <= sym_offset_14_1_reg_1748;
end if;
end if;
end process;
-- sym_offset_14_4_reg_5347 assign process. --
sym_offset_14_4_reg_5347_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_ST_st43_fsm_42 = ap_CS_fsm)) then
sym_offset_14_4_reg_5347 <= sym_offset_14_5_reg_11741;
elsif (((ap_ST_st32_fsm_31 = ap_CS_fsm) and ((not((ap_const_lv1_0 = end_load_3_phi_phi_fu_11584_p32)) and (ap_const_lv1_0 = brmerge_demorgan_reg_14680)) or (not((ap_const_lv1_0 = end_load_3_phi_phi_fu_11584_p32)) and not((ap_const_lv1_0 = tmp1_fu_13626_p2)))))) then
sym_offset_14_4_reg_5347 <= sym_offset_14_4_reg_5347;
elsif ((ap_ST_st18_fsm_17 = ap_CS_fsm)) then
sym_offset_14_4_reg_5347 <= sym_offset_14_3_reg_4270;
end if;
end if;
end process;
-- sym_offset_14_5_reg_11741 assign process. --
sym_offset_14_5_reg_11741_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ST_st33_fsm_32 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_E))) then
sym_offset_14_5_reg_11741 <= sym_offset_0_1_25_fu_13631_p2;
elsif (((ap_ST_st33_fsm_32 = ap_CS_fsm) or ((ap_ST_st33_fsm_32 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_D)) or ((ap_ST_st33_fsm_32 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_C)) or ((ap_ST_st33_fsm_32 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_B)) or ((ap_ST_st33_fsm_32 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_A)) or ((ap_ST_st33_fsm_32 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_9)) or ((ap_ST_st33_fsm_32 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_8)) or ((ap_ST_st33_fsm_32 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_7)) or ((ap_ST_st33_fsm_32 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_6)) or ((ap_ST_st33_fsm_32 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_5)) or ((ap_ST_st33_fsm_32 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_4)) or ((ap_ST_st33_fsm_32 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_3)) or ((ap_ST_st33_fsm_32 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_2)) or ((ap_ST_st33_fsm_32 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_1)) or ((ap_ST_st33_fsm_32 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_0)))) then
sym_offset_14_5_reg_11741 <= sym_offset_14_4_reg_5347;
end if;
end if;
end process;
-- sym_offset_15_1_reg_1737 assign process. --
sym_offset_15_1_reg_1737_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_ST_st17_fsm_16 = ap_CS_fsm)) then
sym_offset_15_1_reg_1737 <= sym_offset_15_2_reg_1924;
elsif (((ap_ST_st7_fsm_6 = ap_CS_fsm) and (ap_const_lv1_0 = tmp_6_fu_13097_p2))) then
sym_offset_15_1_reg_1737 <= sym_offset_s_reg_1200;
end if;
end if;
end process;
-- sym_offset_15_2_reg_1924 assign process. --
sym_offset_15_2_reg_1924_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((((ap_ST_st9_fsm_8 = ap_CS_fsm) and (tmp_36_reg_14538 = ap_const_lv4_E)) or ((ap_ST_st9_fsm_8 = ap_CS_fsm) and (tmp_36_reg_14538 = ap_const_lv4_D)) or ((ap_ST_st9_fsm_8 = ap_CS_fsm) and (tmp_36_reg_14538 = ap_const_lv4_C)) or ((ap_ST_st9_fsm_8 = ap_CS_fsm) and (tmp_36_reg_14538 = ap_const_lv4_B)) or ((ap_ST_st9_fsm_8 = ap_CS_fsm) and (tmp_36_reg_14538 = ap_const_lv4_A)) or ((ap_ST_st9_fsm_8 = ap_CS_fsm) and (tmp_36_reg_14538 = ap_const_lv4_9)) or ((ap_ST_st9_fsm_8 = ap_CS_fsm) and (tmp_36_reg_14538 = ap_const_lv4_8)) or ((ap_ST_st9_fsm_8 = ap_CS_fsm) and (tmp_36_reg_14538 = ap_const_lv4_7)) or ((ap_ST_st9_fsm_8 = ap_CS_fsm) and (tmp_36_reg_14538 = ap_const_lv4_6)) or ((ap_ST_st9_fsm_8 = ap_CS_fsm) and (tmp_36_reg_14538 = ap_const_lv4_5)) or ((ap_ST_st9_fsm_8 = ap_CS_fsm) and (tmp_36_reg_14538 = ap_const_lv4_4)) or ((ap_ST_st9_fsm_8 = ap_CS_fsm) and (tmp_36_reg_14538 = ap_const_lv4_3)) or ((ap_ST_st9_fsm_8 = ap_CS_fsm) and (tmp_36_reg_14538 = ap_const_lv4_2)) or ((ap_ST_st9_fsm_8 = ap_CS_fsm) and (tmp_36_reg_14538 = ap_const_lv4_1)) or ((ap_ST_st9_fsm_8 = ap_CS_fsm) and (tmp_36_reg_14538 = ap_const_lv4_0)))) then
sym_offset_15_2_reg_1924 <= sym_offset_15_1_reg_1737;
elsif ((ap_ST_st9_fsm_8 = ap_CS_fsm)) then
sym_offset_15_2_reg_1924 <= start_indices_q0;
end if;
end if;
end process;
-- sym_offset_15_3_reg_4259 assign process. --
sym_offset_15_3_reg_4259_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ST_st44_fsm_43 = ap_CS_fsm) and not((ap_const_lv1_0 = exitcond_fu_13718_p2)) and (ap_const_lv1_0 = all_end_phi_fu_12651_p36))) then
sym_offset_15_3_reg_4259 <= sym_offset_15_4_reg_5331;
elsif (((ap_ST_st8_fsm_7 = ap_CS_fsm) and not((exitcond2_fu_13247_p2 = ap_const_lv1_0)))) then
sym_offset_15_3_reg_4259 <= sym_offset_15_1_reg_1737;
end if;
end if;
end process;
-- sym_offset_15_4_reg_5331 assign process. --
sym_offset_15_4_reg_5331_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_ST_st43_fsm_42 = ap_CS_fsm)) then
sym_offset_15_4_reg_5331 <= sym_offset_15_5_reg_11687;
elsif (((ap_ST_st32_fsm_31 = ap_CS_fsm) and ((not((ap_const_lv1_0 = end_load_3_phi_phi_fu_11584_p32)) and (ap_const_lv1_0 = brmerge_demorgan_reg_14680)) or (not((ap_const_lv1_0 = end_load_3_phi_phi_fu_11584_p32)) and not((ap_const_lv1_0 = tmp1_fu_13626_p2)))))) then
sym_offset_15_4_reg_5331 <= sym_offset_15_4_reg_5331;
elsif ((ap_ST_st18_fsm_17 = ap_CS_fsm)) then
sym_offset_15_4_reg_5331 <= sym_offset_15_3_reg_4259;
end if;
end if;
end process;
-- sym_offset_15_5_reg_11687 assign process. --
sym_offset_15_5_reg_11687_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((((ap_ST_st33_fsm_32 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_E)) or ((ap_ST_st33_fsm_32 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_D)) or ((ap_ST_st33_fsm_32 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_C)) or ((ap_ST_st33_fsm_32 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_B)) or ((ap_ST_st33_fsm_32 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_A)) or ((ap_ST_st33_fsm_32 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_9)) or ((ap_ST_st33_fsm_32 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_8)) or ((ap_ST_st33_fsm_32 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_7)) or ((ap_ST_st33_fsm_32 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_6)) or ((ap_ST_st33_fsm_32 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_5)) or ((ap_ST_st33_fsm_32 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_4)) or ((ap_ST_st33_fsm_32 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_3)) or ((ap_ST_st33_fsm_32 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_2)) or ((ap_ST_st33_fsm_32 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_1)) or ((ap_ST_st33_fsm_32 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_0)))) then
sym_offset_15_5_reg_11687 <= sym_offset_15_4_reg_5331;
elsif ((ap_ST_st33_fsm_32 = ap_CS_fsm)) then
sym_offset_15_5_reg_11687 <= sym_offset_0_1_25_fu_13631_p2;
end if;
end if;
end process;
-- sym_offset_1_1_reg_1891 assign process. --
sym_offset_1_1_reg_1891_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_ST_st17_fsm_16 = ap_CS_fsm)) then
sym_offset_1_1_reg_1891 <= sym_offset_1_2_reg_2680;
elsif (((ap_ST_st7_fsm_6 = ap_CS_fsm) and (ap_const_lv1_0 = tmp_6_fu_13097_p2))) then
sym_offset_1_1_reg_1891 <= sym_offset_1_reg_1368;
end if;
end if;
end process;
-- sym_offset_1_2_reg_2680 assign process. --
sym_offset_1_2_reg_2680_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ST_st9_fsm_8 = ap_CS_fsm) and (tmp_36_reg_14538 = ap_const_lv4_1))) then
sym_offset_1_2_reg_2680 <= start_indices_q0;
elsif (((ap_ST_st9_fsm_8 = ap_CS_fsm) or ((ap_ST_st9_fsm_8 = ap_CS_fsm) and (tmp_36_reg_14538 = ap_const_lv4_E)) or ((ap_ST_st9_fsm_8 = ap_CS_fsm) and (tmp_36_reg_14538 = ap_const_lv4_D)) or ((ap_ST_st9_fsm_8 = ap_CS_fsm) and (tmp_36_reg_14538 = ap_const_lv4_C)) or ((ap_ST_st9_fsm_8 = ap_CS_fsm) and (tmp_36_reg_14538 = ap_const_lv4_B)) or ((ap_ST_st9_fsm_8 = ap_CS_fsm) and (tmp_36_reg_14538 = ap_const_lv4_A)) or ((ap_ST_st9_fsm_8 = ap_CS_fsm) and (tmp_36_reg_14538 = ap_const_lv4_9)) or ((ap_ST_st9_fsm_8 = ap_CS_fsm) and (tmp_36_reg_14538 = ap_const_lv4_8)) or ((ap_ST_st9_fsm_8 = ap_CS_fsm) and (tmp_36_reg_14538 = ap_const_lv4_7)) or ((ap_ST_st9_fsm_8 = ap_CS_fsm) and (tmp_36_reg_14538 = ap_const_lv4_6)) or ((ap_ST_st9_fsm_8 = ap_CS_fsm) and (tmp_36_reg_14538 = ap_const_lv4_5)) or ((ap_ST_st9_fsm_8 = ap_CS_fsm) and (tmp_36_reg_14538 = ap_const_lv4_4)) or ((ap_ST_st9_fsm_8 = ap_CS_fsm) and (tmp_36_reg_14538 = ap_const_lv4_3)) or ((ap_ST_st9_fsm_8 = ap_CS_fsm) and (tmp_36_reg_14538 = ap_const_lv4_2)) or ((ap_ST_st9_fsm_8 = ap_CS_fsm) and (tmp_36_reg_14538 = ap_const_lv4_0)))) then
sym_offset_1_2_reg_2680 <= sym_offset_1_1_reg_1891;
end if;
end if;
end process;
-- sym_offset_1_3_reg_4413 assign process. --
sym_offset_1_3_reg_4413_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ST_st44_fsm_43 = ap_CS_fsm) and not((ap_const_lv1_0 = exitcond_fu_13718_p2)) and (ap_const_lv1_0 = all_end_phi_fu_12651_p36))) then
sym_offset_1_3_reg_4413 <= sym_offset_1_4_reg_5555;
elsif (((ap_ST_st8_fsm_7 = ap_CS_fsm) and not((exitcond2_fu_13247_p2 = ap_const_lv1_0)))) then
sym_offset_1_3_reg_4413 <= sym_offset_1_1_reg_1891;
end if;
end if;
end process;
-- sym_offset_1_4_reg_5555 assign process. --
sym_offset_1_4_reg_5555_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_ST_st43_fsm_42 = ap_CS_fsm)) then
sym_offset_1_4_reg_5555 <= sym_offset_1_5_reg_12443;
elsif (((ap_ST_st32_fsm_31 = ap_CS_fsm) and ((not((ap_const_lv1_0 = end_load_3_phi_phi_fu_11584_p32)) and (ap_const_lv1_0 = brmerge_demorgan_reg_14680)) or (not((ap_const_lv1_0 = end_load_3_phi_phi_fu_11584_p32)) and not((ap_const_lv1_0 = tmp1_fu_13626_p2)))))) then
sym_offset_1_4_reg_5555 <= sym_offset_1_4_reg_5555;
elsif ((ap_ST_st18_fsm_17 = ap_CS_fsm)) then
sym_offset_1_4_reg_5555 <= sym_offset_1_3_reg_4413;
end if;
end if;
end process;
-- sym_offset_1_5_reg_12443 assign process. --
sym_offset_1_5_reg_12443_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ST_st33_fsm_32 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_1))) then
sym_offset_1_5_reg_12443 <= sym_offset_0_1_25_fu_13631_p2;
elsif (((ap_ST_st33_fsm_32 = ap_CS_fsm) or ((ap_ST_st33_fsm_32 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_E)) or ((ap_ST_st33_fsm_32 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_D)) or ((ap_ST_st33_fsm_32 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_C)) or ((ap_ST_st33_fsm_32 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_B)) or ((ap_ST_st33_fsm_32 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_A)) or ((ap_ST_st33_fsm_32 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_9)) or ((ap_ST_st33_fsm_32 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_8)) or ((ap_ST_st33_fsm_32 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_7)) or ((ap_ST_st33_fsm_32 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_6)) or ((ap_ST_st33_fsm_32 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_5)) or ((ap_ST_st33_fsm_32 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_4)) or ((ap_ST_st33_fsm_32 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_3)) or ((ap_ST_st33_fsm_32 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_2)) or ((ap_ST_st33_fsm_32 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_0)))) then
sym_offset_1_5_reg_12443 <= sym_offset_1_4_reg_5555;
end if;
end if;
end process;
-- sym_offset_2_1_reg_1880 assign process. --
sym_offset_2_1_reg_1880_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_ST_st17_fsm_16 = ap_CS_fsm)) then
sym_offset_2_1_reg_1880 <= sym_offset_2_2_reg_2626;
elsif (((ap_ST_st7_fsm_6 = ap_CS_fsm) and (ap_const_lv1_0 = tmp_6_fu_13097_p2))) then
sym_offset_2_1_reg_1880 <= sym_offset_2_reg_1356;
end if;
end if;
end process;
-- sym_offset_2_2_reg_2626 assign process. --
sym_offset_2_2_reg_2626_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ST_st9_fsm_8 = ap_CS_fsm) and (tmp_36_reg_14538 = ap_const_lv4_2))) then
sym_offset_2_2_reg_2626 <= start_indices_q0;
elsif (((ap_ST_st9_fsm_8 = ap_CS_fsm) or ((ap_ST_st9_fsm_8 = ap_CS_fsm) and (tmp_36_reg_14538 = ap_const_lv4_E)) or ((ap_ST_st9_fsm_8 = ap_CS_fsm) and (tmp_36_reg_14538 = ap_const_lv4_D)) or ((ap_ST_st9_fsm_8 = ap_CS_fsm) and (tmp_36_reg_14538 = ap_const_lv4_C)) or ((ap_ST_st9_fsm_8 = ap_CS_fsm) and (tmp_36_reg_14538 = ap_const_lv4_B)) or ((ap_ST_st9_fsm_8 = ap_CS_fsm) and (tmp_36_reg_14538 = ap_const_lv4_A)) or ((ap_ST_st9_fsm_8 = ap_CS_fsm) and (tmp_36_reg_14538 = ap_const_lv4_9)) or ((ap_ST_st9_fsm_8 = ap_CS_fsm) and (tmp_36_reg_14538 = ap_const_lv4_8)) or ((ap_ST_st9_fsm_8 = ap_CS_fsm) and (tmp_36_reg_14538 = ap_const_lv4_7)) or ((ap_ST_st9_fsm_8 = ap_CS_fsm) and (tmp_36_reg_14538 = ap_const_lv4_6)) or ((ap_ST_st9_fsm_8 = ap_CS_fsm) and (tmp_36_reg_14538 = ap_const_lv4_5)) or ((ap_ST_st9_fsm_8 = ap_CS_fsm) and (tmp_36_reg_14538 = ap_const_lv4_4)) or ((ap_ST_st9_fsm_8 = ap_CS_fsm) and (tmp_36_reg_14538 = ap_const_lv4_3)) or ((ap_ST_st9_fsm_8 = ap_CS_fsm) and (tmp_36_reg_14538 = ap_const_lv4_1)) or ((ap_ST_st9_fsm_8 = ap_CS_fsm) and (tmp_36_reg_14538 = ap_const_lv4_0)))) then
sym_offset_2_2_reg_2626 <= sym_offset_2_1_reg_1880;
end if;
end if;
end process;
-- sym_offset_2_3_reg_4402 assign process. --
sym_offset_2_3_reg_4402_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ST_st44_fsm_43 = ap_CS_fsm) and not((ap_const_lv1_0 = exitcond_fu_13718_p2)) and (ap_const_lv1_0 = all_end_phi_fu_12651_p36))) then
sym_offset_2_3_reg_4402 <= sym_offset_2_4_reg_5539;
elsif (((ap_ST_st8_fsm_7 = ap_CS_fsm) and not((exitcond2_fu_13247_p2 = ap_const_lv1_0)))) then
sym_offset_2_3_reg_4402 <= sym_offset_2_1_reg_1880;
end if;
end if;
end process;
-- sym_offset_2_4_reg_5539 assign process. --
sym_offset_2_4_reg_5539_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_ST_st43_fsm_42 = ap_CS_fsm)) then
sym_offset_2_4_reg_5539 <= sym_offset_2_5_reg_12389;
elsif (((ap_ST_st32_fsm_31 = ap_CS_fsm) and ((not((ap_const_lv1_0 = end_load_3_phi_phi_fu_11584_p32)) and (ap_const_lv1_0 = brmerge_demorgan_reg_14680)) or (not((ap_const_lv1_0 = end_load_3_phi_phi_fu_11584_p32)) and not((ap_const_lv1_0 = tmp1_fu_13626_p2)))))) then
sym_offset_2_4_reg_5539 <= sym_offset_2_4_reg_5539;
elsif ((ap_ST_st18_fsm_17 = ap_CS_fsm)) then
sym_offset_2_4_reg_5539 <= sym_offset_2_3_reg_4402;
end if;
end if;
end process;
-- sym_offset_2_5_reg_12389 assign process. --
sym_offset_2_5_reg_12389_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ST_st33_fsm_32 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_2))) then
sym_offset_2_5_reg_12389 <= sym_offset_0_1_25_fu_13631_p2;
elsif (((ap_ST_st33_fsm_32 = ap_CS_fsm) or ((ap_ST_st33_fsm_32 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_E)) or ((ap_ST_st33_fsm_32 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_D)) or ((ap_ST_st33_fsm_32 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_C)) or ((ap_ST_st33_fsm_32 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_B)) or ((ap_ST_st33_fsm_32 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_A)) or ((ap_ST_st33_fsm_32 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_9)) or ((ap_ST_st33_fsm_32 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_8)) or ((ap_ST_st33_fsm_32 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_7)) or ((ap_ST_st33_fsm_32 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_6)) or ((ap_ST_st33_fsm_32 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_5)) or ((ap_ST_st33_fsm_32 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_4)) or ((ap_ST_st33_fsm_32 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_3)) or ((ap_ST_st33_fsm_32 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_1)) or ((ap_ST_st33_fsm_32 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_0)))) then
sym_offset_2_5_reg_12389 <= sym_offset_2_4_reg_5539;
end if;
end if;
end process;
-- sym_offset_3_1_reg_1869 assign process. --
sym_offset_3_1_reg_1869_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_ST_st17_fsm_16 = ap_CS_fsm)) then
sym_offset_3_1_reg_1869 <= sym_offset_3_2_reg_2572;
elsif (((ap_ST_st7_fsm_6 = ap_CS_fsm) and (ap_const_lv1_0 = tmp_6_fu_13097_p2))) then
sym_offset_3_1_reg_1869 <= sym_offset_3_reg_1344;
end if;
end if;
end process;
-- sym_offset_3_2_reg_2572 assign process. --
sym_offset_3_2_reg_2572_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ST_st9_fsm_8 = ap_CS_fsm) and (tmp_36_reg_14538 = ap_const_lv4_3))) then
sym_offset_3_2_reg_2572 <= start_indices_q0;
elsif (((ap_ST_st9_fsm_8 = ap_CS_fsm) or ((ap_ST_st9_fsm_8 = ap_CS_fsm) and (tmp_36_reg_14538 = ap_const_lv4_E)) or ((ap_ST_st9_fsm_8 = ap_CS_fsm) and (tmp_36_reg_14538 = ap_const_lv4_D)) or ((ap_ST_st9_fsm_8 = ap_CS_fsm) and (tmp_36_reg_14538 = ap_const_lv4_C)) or ((ap_ST_st9_fsm_8 = ap_CS_fsm) and (tmp_36_reg_14538 = ap_const_lv4_B)) or ((ap_ST_st9_fsm_8 = ap_CS_fsm) and (tmp_36_reg_14538 = ap_const_lv4_A)) or ((ap_ST_st9_fsm_8 = ap_CS_fsm) and (tmp_36_reg_14538 = ap_const_lv4_9)) or ((ap_ST_st9_fsm_8 = ap_CS_fsm) and (tmp_36_reg_14538 = ap_const_lv4_8)) or ((ap_ST_st9_fsm_8 = ap_CS_fsm) and (tmp_36_reg_14538 = ap_const_lv4_7)) or ((ap_ST_st9_fsm_8 = ap_CS_fsm) and (tmp_36_reg_14538 = ap_const_lv4_6)) or ((ap_ST_st9_fsm_8 = ap_CS_fsm) and (tmp_36_reg_14538 = ap_const_lv4_5)) or ((ap_ST_st9_fsm_8 = ap_CS_fsm) and (tmp_36_reg_14538 = ap_const_lv4_4)) or ((ap_ST_st9_fsm_8 = ap_CS_fsm) and (tmp_36_reg_14538 = ap_const_lv4_2)) or ((ap_ST_st9_fsm_8 = ap_CS_fsm) and (tmp_36_reg_14538 = ap_const_lv4_1)) or ((ap_ST_st9_fsm_8 = ap_CS_fsm) and (tmp_36_reg_14538 = ap_const_lv4_0)))) then
sym_offset_3_2_reg_2572 <= sym_offset_3_1_reg_1869;
end if;
end if;
end process;
-- sym_offset_3_3_reg_4391 assign process. --
sym_offset_3_3_reg_4391_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ST_st44_fsm_43 = ap_CS_fsm) and not((ap_const_lv1_0 = exitcond_fu_13718_p2)) and (ap_const_lv1_0 = all_end_phi_fu_12651_p36))) then
sym_offset_3_3_reg_4391 <= sym_offset_3_4_reg_5523;
elsif (((ap_ST_st8_fsm_7 = ap_CS_fsm) and not((exitcond2_fu_13247_p2 = ap_const_lv1_0)))) then
sym_offset_3_3_reg_4391 <= sym_offset_3_1_reg_1869;
end if;
end if;
end process;
-- sym_offset_3_4_reg_5523 assign process. --
sym_offset_3_4_reg_5523_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_ST_st43_fsm_42 = ap_CS_fsm)) then
sym_offset_3_4_reg_5523 <= sym_offset_3_5_reg_12335;
elsif (((ap_ST_st32_fsm_31 = ap_CS_fsm) and ((not((ap_const_lv1_0 = end_load_3_phi_phi_fu_11584_p32)) and (ap_const_lv1_0 = brmerge_demorgan_reg_14680)) or (not((ap_const_lv1_0 = end_load_3_phi_phi_fu_11584_p32)) and not((ap_const_lv1_0 = tmp1_fu_13626_p2)))))) then
sym_offset_3_4_reg_5523 <= sym_offset_3_4_reg_5523;
elsif ((ap_ST_st18_fsm_17 = ap_CS_fsm)) then
sym_offset_3_4_reg_5523 <= sym_offset_3_3_reg_4391;
end if;
end if;
end process;
-- sym_offset_3_5_reg_12335 assign process. --
sym_offset_3_5_reg_12335_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ST_st33_fsm_32 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_3))) then
sym_offset_3_5_reg_12335 <= sym_offset_0_1_25_fu_13631_p2;
elsif (((ap_ST_st33_fsm_32 = ap_CS_fsm) or ((ap_ST_st33_fsm_32 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_E)) or ((ap_ST_st33_fsm_32 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_D)) or ((ap_ST_st33_fsm_32 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_C)) or ((ap_ST_st33_fsm_32 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_B)) or ((ap_ST_st33_fsm_32 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_A)) or ((ap_ST_st33_fsm_32 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_9)) or ((ap_ST_st33_fsm_32 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_8)) or ((ap_ST_st33_fsm_32 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_7)) or ((ap_ST_st33_fsm_32 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_6)) or ((ap_ST_st33_fsm_32 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_5)) or ((ap_ST_st33_fsm_32 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_4)) or ((ap_ST_st33_fsm_32 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_2)) or ((ap_ST_st33_fsm_32 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_1)) or ((ap_ST_st33_fsm_32 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_0)))) then
sym_offset_3_5_reg_12335 <= sym_offset_3_4_reg_5523;
end if;
end if;
end process;
-- sym_offset_4_1_reg_1858 assign process. --
sym_offset_4_1_reg_1858_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_ST_st17_fsm_16 = ap_CS_fsm)) then
sym_offset_4_1_reg_1858 <= sym_offset_4_2_reg_2518;
elsif (((ap_ST_st7_fsm_6 = ap_CS_fsm) and (ap_const_lv1_0 = tmp_6_fu_13097_p2))) then
sym_offset_4_1_reg_1858 <= sym_offset_4_reg_1332;
end if;
end if;
end process;
-- sym_offset_4_2_reg_2518 assign process. --
sym_offset_4_2_reg_2518_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ST_st9_fsm_8 = ap_CS_fsm) and (tmp_36_reg_14538 = ap_const_lv4_4))) then
sym_offset_4_2_reg_2518 <= start_indices_q0;
elsif (((ap_ST_st9_fsm_8 = ap_CS_fsm) or ((ap_ST_st9_fsm_8 = ap_CS_fsm) and (tmp_36_reg_14538 = ap_const_lv4_E)) or ((ap_ST_st9_fsm_8 = ap_CS_fsm) and (tmp_36_reg_14538 = ap_const_lv4_D)) or ((ap_ST_st9_fsm_8 = ap_CS_fsm) and (tmp_36_reg_14538 = ap_const_lv4_C)) or ((ap_ST_st9_fsm_8 = ap_CS_fsm) and (tmp_36_reg_14538 = ap_const_lv4_B)) or ((ap_ST_st9_fsm_8 = ap_CS_fsm) and (tmp_36_reg_14538 = ap_const_lv4_A)) or ((ap_ST_st9_fsm_8 = ap_CS_fsm) and (tmp_36_reg_14538 = ap_const_lv4_9)) or ((ap_ST_st9_fsm_8 = ap_CS_fsm) and (tmp_36_reg_14538 = ap_const_lv4_8)) or ((ap_ST_st9_fsm_8 = ap_CS_fsm) and (tmp_36_reg_14538 = ap_const_lv4_7)) or ((ap_ST_st9_fsm_8 = ap_CS_fsm) and (tmp_36_reg_14538 = ap_const_lv4_6)) or ((ap_ST_st9_fsm_8 = ap_CS_fsm) and (tmp_36_reg_14538 = ap_const_lv4_5)) or ((ap_ST_st9_fsm_8 = ap_CS_fsm) and (tmp_36_reg_14538 = ap_const_lv4_3)) or ((ap_ST_st9_fsm_8 = ap_CS_fsm) and (tmp_36_reg_14538 = ap_const_lv4_2)) or ((ap_ST_st9_fsm_8 = ap_CS_fsm) and (tmp_36_reg_14538 = ap_const_lv4_1)) or ((ap_ST_st9_fsm_8 = ap_CS_fsm) and (tmp_36_reg_14538 = ap_const_lv4_0)))) then
sym_offset_4_2_reg_2518 <= sym_offset_4_1_reg_1858;
end if;
end if;
end process;
-- sym_offset_4_3_reg_4380 assign process. --
sym_offset_4_3_reg_4380_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ST_st44_fsm_43 = ap_CS_fsm) and not((ap_const_lv1_0 = exitcond_fu_13718_p2)) and (ap_const_lv1_0 = all_end_phi_fu_12651_p36))) then
sym_offset_4_3_reg_4380 <= sym_offset_4_4_reg_5507;
elsif (((ap_ST_st8_fsm_7 = ap_CS_fsm) and not((exitcond2_fu_13247_p2 = ap_const_lv1_0)))) then
sym_offset_4_3_reg_4380 <= sym_offset_4_1_reg_1858;
end if;
end if;
end process;
-- sym_offset_4_4_reg_5507 assign process. --
sym_offset_4_4_reg_5507_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_ST_st43_fsm_42 = ap_CS_fsm)) then
sym_offset_4_4_reg_5507 <= sym_offset_4_5_reg_12281;
elsif (((ap_ST_st32_fsm_31 = ap_CS_fsm) and ((not((ap_const_lv1_0 = end_load_3_phi_phi_fu_11584_p32)) and (ap_const_lv1_0 = brmerge_demorgan_reg_14680)) or (not((ap_const_lv1_0 = end_load_3_phi_phi_fu_11584_p32)) and not((ap_const_lv1_0 = tmp1_fu_13626_p2)))))) then
sym_offset_4_4_reg_5507 <= sym_offset_4_4_reg_5507;
elsif ((ap_ST_st18_fsm_17 = ap_CS_fsm)) then
sym_offset_4_4_reg_5507 <= sym_offset_4_3_reg_4380;
end if;
end if;
end process;
-- sym_offset_4_5_reg_12281 assign process. --
sym_offset_4_5_reg_12281_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ST_st33_fsm_32 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_4))) then
sym_offset_4_5_reg_12281 <= sym_offset_0_1_25_fu_13631_p2;
elsif (((ap_ST_st33_fsm_32 = ap_CS_fsm) or ((ap_ST_st33_fsm_32 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_E)) or ((ap_ST_st33_fsm_32 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_D)) or ((ap_ST_st33_fsm_32 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_C)) or ((ap_ST_st33_fsm_32 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_B)) or ((ap_ST_st33_fsm_32 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_A)) or ((ap_ST_st33_fsm_32 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_9)) or ((ap_ST_st33_fsm_32 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_8)) or ((ap_ST_st33_fsm_32 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_7)) or ((ap_ST_st33_fsm_32 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_6)) or ((ap_ST_st33_fsm_32 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_5)) or ((ap_ST_st33_fsm_32 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_3)) or ((ap_ST_st33_fsm_32 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_2)) or ((ap_ST_st33_fsm_32 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_1)) or ((ap_ST_st33_fsm_32 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_0)))) then
sym_offset_4_5_reg_12281 <= sym_offset_4_4_reg_5507;
end if;
end if;
end process;
-- sym_offset_5_1_reg_1847 assign process. --
sym_offset_5_1_reg_1847_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_ST_st17_fsm_16 = ap_CS_fsm)) then
sym_offset_5_1_reg_1847 <= sym_offset_5_2_reg_2464;
elsif (((ap_ST_st7_fsm_6 = ap_CS_fsm) and (ap_const_lv1_0 = tmp_6_fu_13097_p2))) then
sym_offset_5_1_reg_1847 <= sym_offset_5_reg_1320;
end if;
end if;
end process;
-- sym_offset_5_2_reg_2464 assign process. --
sym_offset_5_2_reg_2464_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ST_st9_fsm_8 = ap_CS_fsm) and (tmp_36_reg_14538 = ap_const_lv4_5))) then
sym_offset_5_2_reg_2464 <= start_indices_q0;
elsif (((ap_ST_st9_fsm_8 = ap_CS_fsm) or ((ap_ST_st9_fsm_8 = ap_CS_fsm) and (tmp_36_reg_14538 = ap_const_lv4_E)) or ((ap_ST_st9_fsm_8 = ap_CS_fsm) and (tmp_36_reg_14538 = ap_const_lv4_D)) or ((ap_ST_st9_fsm_8 = ap_CS_fsm) and (tmp_36_reg_14538 = ap_const_lv4_C)) or ((ap_ST_st9_fsm_8 = ap_CS_fsm) and (tmp_36_reg_14538 = ap_const_lv4_B)) or ((ap_ST_st9_fsm_8 = ap_CS_fsm) and (tmp_36_reg_14538 = ap_const_lv4_A)) or ((ap_ST_st9_fsm_8 = ap_CS_fsm) and (tmp_36_reg_14538 = ap_const_lv4_9)) or ((ap_ST_st9_fsm_8 = ap_CS_fsm) and (tmp_36_reg_14538 = ap_const_lv4_8)) or ((ap_ST_st9_fsm_8 = ap_CS_fsm) and (tmp_36_reg_14538 = ap_const_lv4_7)) or ((ap_ST_st9_fsm_8 = ap_CS_fsm) and (tmp_36_reg_14538 = ap_const_lv4_6)) or ((ap_ST_st9_fsm_8 = ap_CS_fsm) and (tmp_36_reg_14538 = ap_const_lv4_4)) or ((ap_ST_st9_fsm_8 = ap_CS_fsm) and (tmp_36_reg_14538 = ap_const_lv4_3)) or ((ap_ST_st9_fsm_8 = ap_CS_fsm) and (tmp_36_reg_14538 = ap_const_lv4_2)) or ((ap_ST_st9_fsm_8 = ap_CS_fsm) and (tmp_36_reg_14538 = ap_const_lv4_1)) or ((ap_ST_st9_fsm_8 = ap_CS_fsm) and (tmp_36_reg_14538 = ap_const_lv4_0)))) then
sym_offset_5_2_reg_2464 <= sym_offset_5_1_reg_1847;
end if;
end if;
end process;
-- sym_offset_5_3_reg_4369 assign process. --
sym_offset_5_3_reg_4369_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ST_st44_fsm_43 = ap_CS_fsm) and not((ap_const_lv1_0 = exitcond_fu_13718_p2)) and (ap_const_lv1_0 = all_end_phi_fu_12651_p36))) then
sym_offset_5_3_reg_4369 <= sym_offset_5_4_reg_5491;
elsif (((ap_ST_st8_fsm_7 = ap_CS_fsm) and not((exitcond2_fu_13247_p2 = ap_const_lv1_0)))) then
sym_offset_5_3_reg_4369 <= sym_offset_5_1_reg_1847;
end if;
end if;
end process;
-- sym_offset_5_4_reg_5491 assign process. --
sym_offset_5_4_reg_5491_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_ST_st43_fsm_42 = ap_CS_fsm)) then
sym_offset_5_4_reg_5491 <= sym_offset_5_5_reg_12227;
elsif (((ap_ST_st32_fsm_31 = ap_CS_fsm) and ((not((ap_const_lv1_0 = end_load_3_phi_phi_fu_11584_p32)) and (ap_const_lv1_0 = brmerge_demorgan_reg_14680)) or (not((ap_const_lv1_0 = end_load_3_phi_phi_fu_11584_p32)) and not((ap_const_lv1_0 = tmp1_fu_13626_p2)))))) then
sym_offset_5_4_reg_5491 <= sym_offset_5_4_reg_5491;
elsif ((ap_ST_st18_fsm_17 = ap_CS_fsm)) then
sym_offset_5_4_reg_5491 <= sym_offset_5_3_reg_4369;
end if;
end if;
end process;
-- sym_offset_5_5_reg_12227 assign process. --
sym_offset_5_5_reg_12227_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ST_st33_fsm_32 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_5))) then
sym_offset_5_5_reg_12227 <= sym_offset_0_1_25_fu_13631_p2;
elsif (((ap_ST_st33_fsm_32 = ap_CS_fsm) or ((ap_ST_st33_fsm_32 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_E)) or ((ap_ST_st33_fsm_32 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_D)) or ((ap_ST_st33_fsm_32 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_C)) or ((ap_ST_st33_fsm_32 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_B)) or ((ap_ST_st33_fsm_32 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_A)) or ((ap_ST_st33_fsm_32 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_9)) or ((ap_ST_st33_fsm_32 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_8)) or ((ap_ST_st33_fsm_32 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_7)) or ((ap_ST_st33_fsm_32 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_6)) or ((ap_ST_st33_fsm_32 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_4)) or ((ap_ST_st33_fsm_32 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_3)) or ((ap_ST_st33_fsm_32 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_2)) or ((ap_ST_st33_fsm_32 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_1)) or ((ap_ST_st33_fsm_32 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_0)))) then
sym_offset_5_5_reg_12227 <= sym_offset_5_4_reg_5491;
end if;
end if;
end process;
-- sym_offset_6_1_reg_1836 assign process. --
sym_offset_6_1_reg_1836_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_ST_st17_fsm_16 = ap_CS_fsm)) then
sym_offset_6_1_reg_1836 <= sym_offset_6_2_reg_2410;
elsif (((ap_ST_st7_fsm_6 = ap_CS_fsm) and (ap_const_lv1_0 = tmp_6_fu_13097_p2))) then
sym_offset_6_1_reg_1836 <= sym_offset_6_reg_1308;
end if;
end if;
end process;
-- sym_offset_6_2_reg_2410 assign process. --
sym_offset_6_2_reg_2410_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ST_st9_fsm_8 = ap_CS_fsm) and (tmp_36_reg_14538 = ap_const_lv4_6))) then
sym_offset_6_2_reg_2410 <= start_indices_q0;
elsif (((ap_ST_st9_fsm_8 = ap_CS_fsm) or ((ap_ST_st9_fsm_8 = ap_CS_fsm) and (tmp_36_reg_14538 = ap_const_lv4_E)) or ((ap_ST_st9_fsm_8 = ap_CS_fsm) and (tmp_36_reg_14538 = ap_const_lv4_D)) or ((ap_ST_st9_fsm_8 = ap_CS_fsm) and (tmp_36_reg_14538 = ap_const_lv4_C)) or ((ap_ST_st9_fsm_8 = ap_CS_fsm) and (tmp_36_reg_14538 = ap_const_lv4_B)) or ((ap_ST_st9_fsm_8 = ap_CS_fsm) and (tmp_36_reg_14538 = ap_const_lv4_A)) or ((ap_ST_st9_fsm_8 = ap_CS_fsm) and (tmp_36_reg_14538 = ap_const_lv4_9)) or ((ap_ST_st9_fsm_8 = ap_CS_fsm) and (tmp_36_reg_14538 = ap_const_lv4_8)) or ((ap_ST_st9_fsm_8 = ap_CS_fsm) and (tmp_36_reg_14538 = ap_const_lv4_7)) or ((ap_ST_st9_fsm_8 = ap_CS_fsm) and (tmp_36_reg_14538 = ap_const_lv4_5)) or ((ap_ST_st9_fsm_8 = ap_CS_fsm) and (tmp_36_reg_14538 = ap_const_lv4_4)) or ((ap_ST_st9_fsm_8 = ap_CS_fsm) and (tmp_36_reg_14538 = ap_const_lv4_3)) or ((ap_ST_st9_fsm_8 = ap_CS_fsm) and (tmp_36_reg_14538 = ap_const_lv4_2)) or ((ap_ST_st9_fsm_8 = ap_CS_fsm) and (tmp_36_reg_14538 = ap_const_lv4_1)) or ((ap_ST_st9_fsm_8 = ap_CS_fsm) and (tmp_36_reg_14538 = ap_const_lv4_0)))) then
sym_offset_6_2_reg_2410 <= sym_offset_6_1_reg_1836;
end if;
end if;
end process;
-- sym_offset_6_3_reg_4358 assign process. --
sym_offset_6_3_reg_4358_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ST_st44_fsm_43 = ap_CS_fsm) and not((ap_const_lv1_0 = exitcond_fu_13718_p2)) and (ap_const_lv1_0 = all_end_phi_fu_12651_p36))) then
sym_offset_6_3_reg_4358 <= sym_offset_6_4_reg_5475;
elsif (((ap_ST_st8_fsm_7 = ap_CS_fsm) and not((exitcond2_fu_13247_p2 = ap_const_lv1_0)))) then
sym_offset_6_3_reg_4358 <= sym_offset_6_1_reg_1836;
end if;
end if;
end process;
-- sym_offset_6_4_reg_5475 assign process. --
sym_offset_6_4_reg_5475_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_ST_st43_fsm_42 = ap_CS_fsm)) then
sym_offset_6_4_reg_5475 <= sym_offset_6_5_reg_12173;
elsif (((ap_ST_st32_fsm_31 = ap_CS_fsm) and ((not((ap_const_lv1_0 = end_load_3_phi_phi_fu_11584_p32)) and (ap_const_lv1_0 = brmerge_demorgan_reg_14680)) or (not((ap_const_lv1_0 = end_load_3_phi_phi_fu_11584_p32)) and not((ap_const_lv1_0 = tmp1_fu_13626_p2)))))) then
sym_offset_6_4_reg_5475 <= sym_offset_6_4_reg_5475;
elsif ((ap_ST_st18_fsm_17 = ap_CS_fsm)) then
sym_offset_6_4_reg_5475 <= sym_offset_6_3_reg_4358;
end if;
end if;
end process;
-- sym_offset_6_5_reg_12173 assign process. --
sym_offset_6_5_reg_12173_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ST_st33_fsm_32 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_6))) then
sym_offset_6_5_reg_12173 <= sym_offset_0_1_25_fu_13631_p2;
elsif (((ap_ST_st33_fsm_32 = ap_CS_fsm) or ((ap_ST_st33_fsm_32 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_E)) or ((ap_ST_st33_fsm_32 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_D)) or ((ap_ST_st33_fsm_32 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_C)) or ((ap_ST_st33_fsm_32 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_B)) or ((ap_ST_st33_fsm_32 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_A)) or ((ap_ST_st33_fsm_32 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_9)) or ((ap_ST_st33_fsm_32 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_8)) or ((ap_ST_st33_fsm_32 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_7)) or ((ap_ST_st33_fsm_32 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_5)) or ((ap_ST_st33_fsm_32 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_4)) or ((ap_ST_st33_fsm_32 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_3)) or ((ap_ST_st33_fsm_32 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_2)) or ((ap_ST_st33_fsm_32 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_1)) or ((ap_ST_st33_fsm_32 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_0)))) then
sym_offset_6_5_reg_12173 <= sym_offset_6_4_reg_5475;
end if;
end if;
end process;
-- sym_offset_7_1_reg_1825 assign process. --
sym_offset_7_1_reg_1825_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_ST_st17_fsm_16 = ap_CS_fsm)) then
sym_offset_7_1_reg_1825 <= sym_offset_7_2_reg_2356;
elsif (((ap_ST_st7_fsm_6 = ap_CS_fsm) and (ap_const_lv1_0 = tmp_6_fu_13097_p2))) then
sym_offset_7_1_reg_1825 <= sym_offset_7_reg_1296;
end if;
end if;
end process;
-- sym_offset_7_2_reg_2356 assign process. --
sym_offset_7_2_reg_2356_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ST_st9_fsm_8 = ap_CS_fsm) and (tmp_36_reg_14538 = ap_const_lv4_7))) then
sym_offset_7_2_reg_2356 <= start_indices_q0;
elsif (((ap_ST_st9_fsm_8 = ap_CS_fsm) or ((ap_ST_st9_fsm_8 = ap_CS_fsm) and (tmp_36_reg_14538 = ap_const_lv4_E)) or ((ap_ST_st9_fsm_8 = ap_CS_fsm) and (tmp_36_reg_14538 = ap_const_lv4_D)) or ((ap_ST_st9_fsm_8 = ap_CS_fsm) and (tmp_36_reg_14538 = ap_const_lv4_C)) or ((ap_ST_st9_fsm_8 = ap_CS_fsm) and (tmp_36_reg_14538 = ap_const_lv4_B)) or ((ap_ST_st9_fsm_8 = ap_CS_fsm) and (tmp_36_reg_14538 = ap_const_lv4_A)) or ((ap_ST_st9_fsm_8 = ap_CS_fsm) and (tmp_36_reg_14538 = ap_const_lv4_9)) or ((ap_ST_st9_fsm_8 = ap_CS_fsm) and (tmp_36_reg_14538 = ap_const_lv4_8)) or ((ap_ST_st9_fsm_8 = ap_CS_fsm) and (tmp_36_reg_14538 = ap_const_lv4_6)) or ((ap_ST_st9_fsm_8 = ap_CS_fsm) and (tmp_36_reg_14538 = ap_const_lv4_5)) or ((ap_ST_st9_fsm_8 = ap_CS_fsm) and (tmp_36_reg_14538 = ap_const_lv4_4)) or ((ap_ST_st9_fsm_8 = ap_CS_fsm) and (tmp_36_reg_14538 = ap_const_lv4_3)) or ((ap_ST_st9_fsm_8 = ap_CS_fsm) and (tmp_36_reg_14538 = ap_const_lv4_2)) or ((ap_ST_st9_fsm_8 = ap_CS_fsm) and (tmp_36_reg_14538 = ap_const_lv4_1)) or ((ap_ST_st9_fsm_8 = ap_CS_fsm) and (tmp_36_reg_14538 = ap_const_lv4_0)))) then
sym_offset_7_2_reg_2356 <= sym_offset_7_1_reg_1825;
end if;
end if;
end process;
-- sym_offset_7_3_reg_4347 assign process. --
sym_offset_7_3_reg_4347_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ST_st44_fsm_43 = ap_CS_fsm) and not((ap_const_lv1_0 = exitcond_fu_13718_p2)) and (ap_const_lv1_0 = all_end_phi_fu_12651_p36))) then
sym_offset_7_3_reg_4347 <= sym_offset_7_4_reg_5459;
elsif (((ap_ST_st8_fsm_7 = ap_CS_fsm) and not((exitcond2_fu_13247_p2 = ap_const_lv1_0)))) then
sym_offset_7_3_reg_4347 <= sym_offset_7_1_reg_1825;
end if;
end if;
end process;
-- sym_offset_7_4_reg_5459 assign process. --
sym_offset_7_4_reg_5459_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_ST_st43_fsm_42 = ap_CS_fsm)) then
sym_offset_7_4_reg_5459 <= sym_offset_7_5_reg_12119;
elsif (((ap_ST_st32_fsm_31 = ap_CS_fsm) and ((not((ap_const_lv1_0 = end_load_3_phi_phi_fu_11584_p32)) and (ap_const_lv1_0 = brmerge_demorgan_reg_14680)) or (not((ap_const_lv1_0 = end_load_3_phi_phi_fu_11584_p32)) and not((ap_const_lv1_0 = tmp1_fu_13626_p2)))))) then
sym_offset_7_4_reg_5459 <= sym_offset_7_4_reg_5459;
elsif ((ap_ST_st18_fsm_17 = ap_CS_fsm)) then
sym_offset_7_4_reg_5459 <= sym_offset_7_3_reg_4347;
end if;
end if;
end process;
-- sym_offset_7_5_reg_12119 assign process. --
sym_offset_7_5_reg_12119_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ST_st33_fsm_32 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_7))) then
sym_offset_7_5_reg_12119 <= sym_offset_0_1_25_fu_13631_p2;
elsif (((ap_ST_st33_fsm_32 = ap_CS_fsm) or ((ap_ST_st33_fsm_32 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_E)) or ((ap_ST_st33_fsm_32 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_D)) or ((ap_ST_st33_fsm_32 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_C)) or ((ap_ST_st33_fsm_32 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_B)) or ((ap_ST_st33_fsm_32 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_A)) or ((ap_ST_st33_fsm_32 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_9)) or ((ap_ST_st33_fsm_32 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_8)) or ((ap_ST_st33_fsm_32 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_6)) or ((ap_ST_st33_fsm_32 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_5)) or ((ap_ST_st33_fsm_32 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_4)) or ((ap_ST_st33_fsm_32 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_3)) or ((ap_ST_st33_fsm_32 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_2)) or ((ap_ST_st33_fsm_32 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_1)) or ((ap_ST_st33_fsm_32 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_0)))) then
sym_offset_7_5_reg_12119 <= sym_offset_7_4_reg_5459;
end if;
end if;
end process;
-- sym_offset_8_1_reg_1814 assign process. --
sym_offset_8_1_reg_1814_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_ST_st17_fsm_16 = ap_CS_fsm)) then
sym_offset_8_1_reg_1814 <= sym_offset_8_2_reg_2302;
elsif (((ap_ST_st7_fsm_6 = ap_CS_fsm) and (ap_const_lv1_0 = tmp_6_fu_13097_p2))) then
sym_offset_8_1_reg_1814 <= sym_offset_8_reg_1284;
end if;
end if;
end process;
-- sym_offset_8_2_reg_2302 assign process. --
sym_offset_8_2_reg_2302_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ST_st9_fsm_8 = ap_CS_fsm) and (tmp_36_reg_14538 = ap_const_lv4_8))) then
sym_offset_8_2_reg_2302 <= start_indices_q0;
elsif (((ap_ST_st9_fsm_8 = ap_CS_fsm) or ((ap_ST_st9_fsm_8 = ap_CS_fsm) and (tmp_36_reg_14538 = ap_const_lv4_E)) or ((ap_ST_st9_fsm_8 = ap_CS_fsm) and (tmp_36_reg_14538 = ap_const_lv4_D)) or ((ap_ST_st9_fsm_8 = ap_CS_fsm) and (tmp_36_reg_14538 = ap_const_lv4_C)) or ((ap_ST_st9_fsm_8 = ap_CS_fsm) and (tmp_36_reg_14538 = ap_const_lv4_B)) or ((ap_ST_st9_fsm_8 = ap_CS_fsm) and (tmp_36_reg_14538 = ap_const_lv4_A)) or ((ap_ST_st9_fsm_8 = ap_CS_fsm) and (tmp_36_reg_14538 = ap_const_lv4_9)) or ((ap_ST_st9_fsm_8 = ap_CS_fsm) and (tmp_36_reg_14538 = ap_const_lv4_7)) or ((ap_ST_st9_fsm_8 = ap_CS_fsm) and (tmp_36_reg_14538 = ap_const_lv4_6)) or ((ap_ST_st9_fsm_8 = ap_CS_fsm) and (tmp_36_reg_14538 = ap_const_lv4_5)) or ((ap_ST_st9_fsm_8 = ap_CS_fsm) and (tmp_36_reg_14538 = ap_const_lv4_4)) or ((ap_ST_st9_fsm_8 = ap_CS_fsm) and (tmp_36_reg_14538 = ap_const_lv4_3)) or ((ap_ST_st9_fsm_8 = ap_CS_fsm) and (tmp_36_reg_14538 = ap_const_lv4_2)) or ((ap_ST_st9_fsm_8 = ap_CS_fsm) and (tmp_36_reg_14538 = ap_const_lv4_1)) or ((ap_ST_st9_fsm_8 = ap_CS_fsm) and (tmp_36_reg_14538 = ap_const_lv4_0)))) then
sym_offset_8_2_reg_2302 <= sym_offset_8_1_reg_1814;
end if;
end if;
end process;
-- sym_offset_8_3_reg_4336 assign process. --
sym_offset_8_3_reg_4336_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ST_st44_fsm_43 = ap_CS_fsm) and not((ap_const_lv1_0 = exitcond_fu_13718_p2)) and (ap_const_lv1_0 = all_end_phi_fu_12651_p36))) then
sym_offset_8_3_reg_4336 <= sym_offset_8_4_reg_5443;
elsif (((ap_ST_st8_fsm_7 = ap_CS_fsm) and not((exitcond2_fu_13247_p2 = ap_const_lv1_0)))) then
sym_offset_8_3_reg_4336 <= sym_offset_8_1_reg_1814;
end if;
end if;
end process;
-- sym_offset_8_4_reg_5443 assign process. --
sym_offset_8_4_reg_5443_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_ST_st43_fsm_42 = ap_CS_fsm)) then
sym_offset_8_4_reg_5443 <= sym_offset_8_5_reg_12065;
elsif (((ap_ST_st32_fsm_31 = ap_CS_fsm) and ((not((ap_const_lv1_0 = end_load_3_phi_phi_fu_11584_p32)) and (ap_const_lv1_0 = brmerge_demorgan_reg_14680)) or (not((ap_const_lv1_0 = end_load_3_phi_phi_fu_11584_p32)) and not((ap_const_lv1_0 = tmp1_fu_13626_p2)))))) then
sym_offset_8_4_reg_5443 <= sym_offset_8_4_reg_5443;
elsif ((ap_ST_st18_fsm_17 = ap_CS_fsm)) then
sym_offset_8_4_reg_5443 <= sym_offset_8_3_reg_4336;
end if;
end if;
end process;
-- sym_offset_8_5_reg_12065 assign process. --
sym_offset_8_5_reg_12065_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ST_st33_fsm_32 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_8))) then
sym_offset_8_5_reg_12065 <= sym_offset_0_1_25_fu_13631_p2;
elsif (((ap_ST_st33_fsm_32 = ap_CS_fsm) or ((ap_ST_st33_fsm_32 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_E)) or ((ap_ST_st33_fsm_32 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_D)) or ((ap_ST_st33_fsm_32 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_C)) or ((ap_ST_st33_fsm_32 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_B)) or ((ap_ST_st33_fsm_32 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_A)) or ((ap_ST_st33_fsm_32 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_9)) or ((ap_ST_st33_fsm_32 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_7)) or ((ap_ST_st33_fsm_32 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_6)) or ((ap_ST_st33_fsm_32 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_5)) or ((ap_ST_st33_fsm_32 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_4)) or ((ap_ST_st33_fsm_32 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_3)) or ((ap_ST_st33_fsm_32 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_2)) or ((ap_ST_st33_fsm_32 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_1)) or ((ap_ST_st33_fsm_32 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_0)))) then
sym_offset_8_5_reg_12065 <= sym_offset_8_4_reg_5443;
end if;
end if;
end process;
-- sym_offset_9_1_reg_1803 assign process. --
sym_offset_9_1_reg_1803_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_ST_st17_fsm_16 = ap_CS_fsm)) then
sym_offset_9_1_reg_1803 <= sym_offset_9_2_reg_2248;
elsif (((ap_ST_st7_fsm_6 = ap_CS_fsm) and (ap_const_lv1_0 = tmp_6_fu_13097_p2))) then
sym_offset_9_1_reg_1803 <= sym_offset_9_reg_1272;
end if;
end if;
end process;
-- sym_offset_9_2_reg_2248 assign process. --
sym_offset_9_2_reg_2248_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ST_st9_fsm_8 = ap_CS_fsm) and (tmp_36_reg_14538 = ap_const_lv4_9))) then
sym_offset_9_2_reg_2248 <= start_indices_q0;
elsif (((ap_ST_st9_fsm_8 = ap_CS_fsm) or ((ap_ST_st9_fsm_8 = ap_CS_fsm) and (tmp_36_reg_14538 = ap_const_lv4_E)) or ((ap_ST_st9_fsm_8 = ap_CS_fsm) and (tmp_36_reg_14538 = ap_const_lv4_D)) or ((ap_ST_st9_fsm_8 = ap_CS_fsm) and (tmp_36_reg_14538 = ap_const_lv4_C)) or ((ap_ST_st9_fsm_8 = ap_CS_fsm) and (tmp_36_reg_14538 = ap_const_lv4_B)) or ((ap_ST_st9_fsm_8 = ap_CS_fsm) and (tmp_36_reg_14538 = ap_const_lv4_A)) or ((ap_ST_st9_fsm_8 = ap_CS_fsm) and (tmp_36_reg_14538 = ap_const_lv4_8)) or ((ap_ST_st9_fsm_8 = ap_CS_fsm) and (tmp_36_reg_14538 = ap_const_lv4_7)) or ((ap_ST_st9_fsm_8 = ap_CS_fsm) and (tmp_36_reg_14538 = ap_const_lv4_6)) or ((ap_ST_st9_fsm_8 = ap_CS_fsm) and (tmp_36_reg_14538 = ap_const_lv4_5)) or ((ap_ST_st9_fsm_8 = ap_CS_fsm) and (tmp_36_reg_14538 = ap_const_lv4_4)) or ((ap_ST_st9_fsm_8 = ap_CS_fsm) and (tmp_36_reg_14538 = ap_const_lv4_3)) or ((ap_ST_st9_fsm_8 = ap_CS_fsm) and (tmp_36_reg_14538 = ap_const_lv4_2)) or ((ap_ST_st9_fsm_8 = ap_CS_fsm) and (tmp_36_reg_14538 = ap_const_lv4_1)) or ((ap_ST_st9_fsm_8 = ap_CS_fsm) and (tmp_36_reg_14538 = ap_const_lv4_0)))) then
sym_offset_9_2_reg_2248 <= sym_offset_9_1_reg_1803;
end if;
end if;
end process;
-- sym_offset_9_3_reg_4325 assign process. --
sym_offset_9_3_reg_4325_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ST_st44_fsm_43 = ap_CS_fsm) and not((ap_const_lv1_0 = exitcond_fu_13718_p2)) and (ap_const_lv1_0 = all_end_phi_fu_12651_p36))) then
sym_offset_9_3_reg_4325 <= sym_offset_9_4_reg_5427;
elsif (((ap_ST_st8_fsm_7 = ap_CS_fsm) and not((exitcond2_fu_13247_p2 = ap_const_lv1_0)))) then
sym_offset_9_3_reg_4325 <= sym_offset_9_1_reg_1803;
end if;
end if;
end process;
-- sym_offset_9_4_reg_5427 assign process. --
sym_offset_9_4_reg_5427_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_ST_st43_fsm_42 = ap_CS_fsm)) then
sym_offset_9_4_reg_5427 <= sym_offset_9_5_reg_12011;
elsif (((ap_ST_st32_fsm_31 = ap_CS_fsm) and ((not((ap_const_lv1_0 = end_load_3_phi_phi_fu_11584_p32)) and (ap_const_lv1_0 = brmerge_demorgan_reg_14680)) or (not((ap_const_lv1_0 = end_load_3_phi_phi_fu_11584_p32)) and not((ap_const_lv1_0 = tmp1_fu_13626_p2)))))) then
sym_offset_9_4_reg_5427 <= sym_offset_9_4_reg_5427;
elsif ((ap_ST_st18_fsm_17 = ap_CS_fsm)) then
sym_offset_9_4_reg_5427 <= sym_offset_9_3_reg_4325;
end if;
end if;
end process;
-- sym_offset_9_5_reg_12011 assign process. --
sym_offset_9_5_reg_12011_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ST_st33_fsm_32 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_9))) then
sym_offset_9_5_reg_12011 <= sym_offset_0_1_25_fu_13631_p2;
elsif (((ap_ST_st33_fsm_32 = ap_CS_fsm) or ((ap_ST_st33_fsm_32 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_E)) or ((ap_ST_st33_fsm_32 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_D)) or ((ap_ST_st33_fsm_32 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_C)) or ((ap_ST_st33_fsm_32 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_B)) or ((ap_ST_st33_fsm_32 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_A)) or ((ap_ST_st33_fsm_32 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_8)) or ((ap_ST_st33_fsm_32 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_7)) or ((ap_ST_st33_fsm_32 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_6)) or ((ap_ST_st33_fsm_32 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_5)) or ((ap_ST_st33_fsm_32 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_4)) or ((ap_ST_st33_fsm_32 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_3)) or ((ap_ST_st33_fsm_32 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_2)) or ((ap_ST_st33_fsm_32 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_1)) or ((ap_ST_st33_fsm_32 = ap_CS_fsm) and (tmp_37_reg_14631 = ap_const_lv4_0)))) then
sym_offset_9_5_reg_12011 <= sym_offset_9_4_reg_5427;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ST_st44_fsm_43 = ap_CS_fsm) and not((ap_const_lv1_0 = exitcond_fu_13718_p2)) and not((ap_const_lv1_0 = all_end_phi_fu_12651_p36)))) then
any_state_10_reg_1068 <= any_state_10_4_reg_5166;
any_state_11_reg_1056 <= any_state_11_4_reg_5151;
any_state_12_reg_1044 <= any_state_12_4_reg_5136;
any_state_13_reg_1032 <= any_state_13_4_reg_5121;
any_state_14_reg_1020 <= any_state_14_4_reg_5106;
any_state_1_reg_1176 <= any_state_1_4_reg_5301;
any_state_2_reg_1164 <= any_state_2_4_reg_5286;
any_state_3_reg_1152 <= any_state_3_4_reg_5271;
any_state_4_reg_1140 <= any_state_4_4_reg_5256;
any_state_5_reg_1128 <= any_state_5_4_reg_5241;
any_state_6_reg_1116 <= any_state_6_4_reg_5226;
any_state_7_reg_1104 <= any_state_7_4_reg_5211;
any_state_8_reg_1092 <= any_state_8_4_reg_5196;
any_state_9_reg_1080 <= any_state_9_4_reg_5181;
any_state_reg_1188 <= any_state_0_4_reg_5316;
any_state_s_reg_1008 <= any_state_15_4_reg_5091;
end_0_s_reg_996 <= end_0_2_reg_5076;
end_10_s_reg_876 <= end_10_2_reg_4926;
end_11_s_reg_864 <= end_11_2_reg_4911;
end_12_s_reg_852 <= end_12_2_reg_4896;
end_13_s_reg_840 <= end_13_2_reg_4881;
end_14_s_reg_828 <= end_14_2_reg_4866;
end_15_s_reg_816 <= end_15_2_reg_4851;
end_1_s_reg_984 <= end_1_2_reg_5061;
end_2_s_reg_972 <= end_2_2_reg_5046;
end_3_s_reg_960 <= end_3_2_reg_5031;
end_4_s_reg_948 <= end_4_2_reg_5016;
end_5_s_reg_936 <= end_5_2_reg_5001;
end_6_s_reg_924 <= end_6_2_reg_4986;
end_7_s_reg_912 <= end_7_2_reg_4971;
end_8_s_reg_900 <= end_8_2_reg_4956;
end_9_s_reg_888 <= end_9_2_reg_4941;
state_0_s_reg_804 <= state_0_2_reg_4836;
state_10_s_reg_684 <= state_10_2_reg_4686;
state_11_s_reg_672 <= state_11_2_reg_4671;
state_12_s_reg_660 <= state_12_2_reg_4656;
state_13_s_reg_648 <= state_13_2_reg_4641;
state_14_s_reg_636 <= state_14_2_reg_4626;
state_15_s_reg_624 <= state_15_2_reg_4611;
state_1_s_reg_792 <= state_1_2_reg_4821;
state_2_s_reg_780 <= state_2_2_reg_4806;
state_3_s_reg_768 <= state_3_2_reg_4791;
state_4_s_reg_756 <= state_4_2_reg_4776;
state_5_s_reg_744 <= state_5_2_reg_4761;
state_6_s_reg_732 <= state_6_2_reg_4746;
state_7_s_reg_720 <= state_7_2_reg_4731;
state_8_s_reg_708 <= state_8_2_reg_4716;
state_9_s_reg_696 <= state_9_2_reg_4701;
sym_offset_10_reg_1260 <= sym_offset_10_4_reg_5411;
sym_offset_11_reg_1248 <= sym_offset_11_4_reg_5395;
sym_offset_12_reg_1236 <= sym_offset_12_4_reg_5379;
sym_offset_13_reg_1224 <= sym_offset_13_4_reg_5363;
sym_offset_14_reg_1212 <= sym_offset_14_4_reg_5347;
sym_offset_1_reg_1368 <= sym_offset_1_4_reg_5555;
sym_offset_2_reg_1356 <= sym_offset_2_4_reg_5539;
sym_offset_3_reg_1344 <= sym_offset_3_4_reg_5523;
sym_offset_4_reg_1332 <= sym_offset_4_4_reg_5507;
sym_offset_5_reg_1320 <= sym_offset_5_4_reg_5491;
sym_offset_6_reg_1308 <= sym_offset_6_4_reg_5475;
sym_offset_7_reg_1296 <= sym_offset_7_4_reg_5459;
sym_offset_8_reg_1284 <= sym_offset_8_4_reg_5443;
sym_offset_9_reg_1272 <= sym_offset_9_4_reg_5427;
sym_offset_reg_1380 <= sym_offset_0_4_reg_5571;
sym_offset_s_reg_1200 <= sym_offset_15_4_reg_5331;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_ST_st30_fsm_29 = ap_CS_fsm)) then
brmerge_demorgan_reg_14680 <= brmerge_demorgan_fu_13621_p2;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and not((ap_const_lv1_0 = end_0_phi_fu_5844_p32)) and (ap_const_lv1_0 = end_string_0_phi_fu_6831_p4))) then
current_buckets_addr_1_reg_14640 <= tmp_5_fu_13550_p1(4 - 1 downto 0);
next_buckets_addr_3_reg_14635 <= tmp_5_fu_13550_p1(4 - 1 downto 0);
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_ST_st7_fsm_6 = ap_CS_fsm)) then
i_1_reg_14270 <= i_1_fu_13091_p2;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_ST_st14_fsm_13 = ap_CS_fsm)) then
j_0_bucket_index_cast_reg_14592(0) <= j_0_bucket_index_cast_fu_13311_p1(0);
j_0_bucket_index_cast_reg_14592(1) <= j_0_bucket_index_cast_fu_13311_p1(1);
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ST_st14_fsm_13 = ap_CS_fsm) and (tmp_36_reg_14538 = ap_const_lv4_A))) then
j_15_bit_10_fu_272 <= j_15_bit_17_fu_228;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_ST_st8_fsm_7 = ap_CS_fsm)) then
j_15_bit_10_load_reg_14329 <= j_15_bit_10_fu_272;
j_15_bit_11_load_reg_14334 <= j_15_bit_11_fu_276;
j_15_bit_12_load_reg_14339 <= j_15_bit_12_fu_280;
j_15_bit_13_load_reg_14344 <= j_15_bit_13_fu_284;
j_15_bit_14_load_reg_14349 <= j_15_bit_14_fu_288;
j_15_bit_15_load_reg_14354 <= j_15_bit_15_fu_292;
j_15_bit_1_load_reg_14284 <= j_15_bit_1_fu_236;
j_15_bit_2_load_reg_14289 <= j_15_bit_2_fu_240;
j_15_bit_3_load_reg_14294 <= j_15_bit_3_fu_244;
j_15_bit_4_load_reg_14299 <= j_15_bit_4_fu_248;
j_15_bit_5_load_reg_14304 <= j_15_bit_5_fu_252;
j_15_bit_6_load_reg_14309 <= j_15_bit_6_fu_256;
j_15_bit_7_load_reg_14314 <= j_15_bit_7_fu_260;
j_15_bit_8_load_reg_14319 <= j_15_bit_8_fu_264;
j_15_bit_9_load_reg_14324 <= j_15_bit_9_fu_268;
j_15_bit_load_reg_14279 <= j_15_bit_fu_232;
j_15_end_10_load_reg_14489 <= j_15_end_10_fu_400;
j_15_end_11_load_reg_14494 <= j_15_end_11_fu_404;
j_15_end_12_load_reg_14499 <= j_15_end_12_fu_408;
j_15_end_13_load_reg_14504 <= j_15_end_13_fu_412;
j_15_end_14_load_reg_14509 <= j_15_end_14_fu_416;
j_15_end_15_load_reg_14514 <= j_15_end_15_fu_420;
j_15_end_1_load_reg_14444 <= j_15_end_1_fu_364;
j_15_end_2_load_reg_14449 <= j_15_end_2_fu_368;
j_15_end_3_load_reg_14454 <= j_15_end_3_fu_372;
j_15_end_4_load_reg_14459 <= j_15_end_4_fu_376;
j_15_end_5_load_reg_14464 <= j_15_end_5_fu_380;
j_15_end_6_load_reg_14469 <= j_15_end_6_fu_384;
j_15_end_7_load_reg_14474 <= j_15_end_7_fu_388;
j_15_end_8_load_reg_14479 <= j_15_end_8_fu_392;
j_15_end_9_load_reg_14484 <= j_15_end_9_fu_396;
j_15_end_load_reg_14439 <= j_15_end_fu_360;
j_bucket_index_0_load_reg_14359(0) <= j_bucket_index_0_s_fu_296(0);
j_bucket_index_0_load_reg_14359(1) <= j_bucket_index_0_s_fu_296(1);
j_bucket_index_10_load_reg_14409(0) <= j_bucket_index_10_s_fu_336(0);
j_bucket_index_10_load_reg_14409(1) <= j_bucket_index_10_s_fu_336(1);
j_bucket_index_11_load_reg_14414(0) <= j_bucket_index_11_s_fu_340(0);
j_bucket_index_11_load_reg_14414(1) <= j_bucket_index_11_s_fu_340(1);
j_bucket_index_12_load_reg_14419(0) <= j_bucket_index_12_s_fu_344(0);
j_bucket_index_12_load_reg_14419(1) <= j_bucket_index_12_s_fu_344(1);
j_bucket_index_13_load_reg_14424(0) <= j_bucket_index_13_s_fu_348(0);
j_bucket_index_13_load_reg_14424(1) <= j_bucket_index_13_s_fu_348(1);
j_bucket_index_14_load_reg_14429(0) <= j_bucket_index_14_s_fu_352(0);
j_bucket_index_14_load_reg_14429(1) <= j_bucket_index_14_s_fu_352(1);
j_bucket_index_15_load_reg_14434(0) <= j_bucket_index_15_s_fu_356(0);
j_bucket_index_15_load_reg_14434(1) <= j_bucket_index_15_s_fu_356(1);
j_bucket_index_1_load_reg_14364(0) <= j_bucket_index_1_s_fu_300(0);
j_bucket_index_1_load_reg_14364(1) <= j_bucket_index_1_s_fu_300(1);
j_bucket_index_2_load_reg_14369(0) <= j_bucket_index_2_s_fu_304(0);
j_bucket_index_2_load_reg_14369(1) <= j_bucket_index_2_s_fu_304(1);
j_bucket_index_3_load_reg_14374(0) <= j_bucket_index_3_s_fu_308(0);
j_bucket_index_3_load_reg_14374(1) <= j_bucket_index_3_s_fu_308(1);
j_bucket_index_4_load_reg_14379(0) <= j_bucket_index_4_s_fu_312(0);
j_bucket_index_4_load_reg_14379(1) <= j_bucket_index_4_s_fu_312(1);
j_bucket_index_5_load_reg_14384(0) <= j_bucket_index_5_s_fu_316(0);
j_bucket_index_5_load_reg_14384(1) <= j_bucket_index_5_s_fu_316(1);
j_bucket_index_6_load_reg_14389(0) <= j_bucket_index_6_s_fu_320(0);
j_bucket_index_6_load_reg_14389(1) <= j_bucket_index_6_s_fu_320(1);
j_bucket_index_7_load_reg_14394(0) <= j_bucket_index_7_s_fu_324(0);
j_bucket_index_7_load_reg_14394(1) <= j_bucket_index_7_s_fu_324(1);
j_bucket_index_8_load_reg_14399(0) <= j_bucket_index_8_s_fu_328(0);
j_bucket_index_8_load_reg_14399(1) <= j_bucket_index_8_s_fu_328(1);
j_bucket_index_9_load_reg_14404(0) <= j_bucket_index_9_s_fu_332(0);
j_bucket_index_9_load_reg_14404(1) <= j_bucket_index_9_s_fu_332(1);
k_5_reg_14522 <= k_5_fu_13252_p2;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ST_st14_fsm_13 = ap_CS_fsm) and (tmp_36_reg_14538 = ap_const_lv4_B))) then
j_15_bit_11_fu_276 <= j_15_bit_17_fu_228;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ST_st14_fsm_13 = ap_CS_fsm) and (tmp_36_reg_14538 = ap_const_lv4_C))) then
j_15_bit_12_fu_280 <= j_15_bit_17_fu_228;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ST_st14_fsm_13 = ap_CS_fsm) and (tmp_36_reg_14538 = ap_const_lv4_D))) then
j_15_bit_13_fu_284 <= j_15_bit_17_fu_228;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ST_st14_fsm_13 = ap_CS_fsm) and (tmp_36_reg_14538 = ap_const_lv4_E))) then
j_15_bit_14_fu_288 <= j_15_bit_17_fu_228;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ST_st14_fsm_13 = ap_CS_fsm) and not((tmp_36_reg_14538 = ap_const_lv4_E)) and not((tmp_36_reg_14538 = ap_const_lv4_D)) and not((tmp_36_reg_14538 = ap_const_lv4_C)) and not((tmp_36_reg_14538 = ap_const_lv4_B)) and not((tmp_36_reg_14538 = ap_const_lv4_A)) and not((tmp_36_reg_14538 = ap_const_lv4_9)) and not((tmp_36_reg_14538 = ap_const_lv4_8)) and not((tmp_36_reg_14538 = ap_const_lv4_7)) and not((tmp_36_reg_14538 = ap_const_lv4_6)) and not((tmp_36_reg_14538 = ap_const_lv4_5)) and not((tmp_36_reg_14538 = ap_const_lv4_4)) and not((tmp_36_reg_14538 = ap_const_lv4_3)) and not((tmp_36_reg_14538 = ap_const_lv4_2)) and not((tmp_36_reg_14538 = ap_const_lv4_1)) and not((tmp_36_reg_14538 = ap_const_lv4_0)))) then
j_15_bit_15_fu_292 <= j_15_bit_17_fu_228;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_ST_st13_fsm_12 = ap_CS_fsm)) then
j_15_bit_17_fu_228 <= j_15_bit_16_fu_13302_p1;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ST_st14_fsm_13 = ap_CS_fsm) and (tmp_36_reg_14538 = ap_const_lv4_1))) then
j_15_bit_1_fu_236 <= j_15_bit_17_fu_228;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ST_st14_fsm_13 = ap_CS_fsm) and (tmp_36_reg_14538 = ap_const_lv4_2))) then
j_15_bit_2_fu_240 <= j_15_bit_17_fu_228;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ST_st14_fsm_13 = ap_CS_fsm) and (tmp_36_reg_14538 = ap_const_lv4_3))) then
j_15_bit_3_fu_244 <= j_15_bit_17_fu_228;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ST_st14_fsm_13 = ap_CS_fsm) and (tmp_36_reg_14538 = ap_const_lv4_4))) then
j_15_bit_4_fu_248 <= j_15_bit_17_fu_228;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ST_st14_fsm_13 = ap_CS_fsm) and (tmp_36_reg_14538 = ap_const_lv4_5))) then
j_15_bit_5_fu_252 <= j_15_bit_17_fu_228;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ST_st14_fsm_13 = ap_CS_fsm) and (tmp_36_reg_14538 = ap_const_lv4_6))) then
j_15_bit_6_fu_256 <= j_15_bit_17_fu_228;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ST_st14_fsm_13 = ap_CS_fsm) and (tmp_36_reg_14538 = ap_const_lv4_7))) then
j_15_bit_7_fu_260 <= j_15_bit_17_fu_228;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ST_st14_fsm_13 = ap_CS_fsm) and (tmp_36_reg_14538 = ap_const_lv4_8))) then
j_15_bit_8_fu_264 <= j_15_bit_17_fu_228;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ST_st14_fsm_13 = ap_CS_fsm) and (tmp_36_reg_14538 = ap_const_lv4_9))) then
j_15_bit_9_fu_268 <= j_15_bit_17_fu_228;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ST_st14_fsm_13 = ap_CS_fsm) and (tmp_36_reg_14538 = ap_const_lv4_0))) then
j_15_bit_fu_232 <= j_15_bit_17_fu_228;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((tmp_36_reg_14538 = ap_const_lv4_A) and (ap_ST_st16_fsm_15 = ap_CS_fsm))) then
j_15_end_10_fu_400 <= j_0_end_reg_3717;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((tmp_36_reg_14538 = ap_const_lv4_B) and (ap_ST_st16_fsm_15 = ap_CS_fsm))) then
j_15_end_11_fu_404 <= j_0_end_reg_3717;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((tmp_36_reg_14538 = ap_const_lv4_C) and (ap_ST_st16_fsm_15 = ap_CS_fsm))) then
j_15_end_12_fu_408 <= j_0_end_reg_3717;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((tmp_36_reg_14538 = ap_const_lv4_D) and (ap_ST_st16_fsm_15 = ap_CS_fsm))) then
j_15_end_13_fu_412 <= j_0_end_reg_3717;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((tmp_36_reg_14538 = ap_const_lv4_E) and (ap_ST_st16_fsm_15 = ap_CS_fsm))) then
j_15_end_14_fu_416 <= j_0_end_reg_3717;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((not((tmp_36_reg_14538 = ap_const_lv4_E)) and not((tmp_36_reg_14538 = ap_const_lv4_D)) and not((tmp_36_reg_14538 = ap_const_lv4_C)) and not((tmp_36_reg_14538 = ap_const_lv4_B)) and not((tmp_36_reg_14538 = ap_const_lv4_A)) and not((tmp_36_reg_14538 = ap_const_lv4_9)) and not((tmp_36_reg_14538 = ap_const_lv4_8)) and not((tmp_36_reg_14538 = ap_const_lv4_7)) and not((tmp_36_reg_14538 = ap_const_lv4_6)) and not((tmp_36_reg_14538 = ap_const_lv4_5)) and not((tmp_36_reg_14538 = ap_const_lv4_4)) and not((tmp_36_reg_14538 = ap_const_lv4_3)) and not((tmp_36_reg_14538 = ap_const_lv4_2)) and not((tmp_36_reg_14538 = ap_const_lv4_1)) and not((tmp_36_reg_14538 = ap_const_lv4_0)) and (ap_ST_st16_fsm_15 = ap_CS_fsm))) then
j_15_end_15_fu_420 <= j_0_end_reg_3717;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((tmp_36_reg_14538 = ap_const_lv4_1) and (ap_ST_st16_fsm_15 = ap_CS_fsm))) then
j_15_end_1_fu_364 <= j_0_end_reg_3717;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((tmp_36_reg_14538 = ap_const_lv4_2) and (ap_ST_st16_fsm_15 = ap_CS_fsm))) then
j_15_end_2_fu_368 <= j_0_end_reg_3717;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((tmp_36_reg_14538 = ap_const_lv4_3) and (ap_ST_st16_fsm_15 = ap_CS_fsm))) then
j_15_end_3_fu_372 <= j_0_end_reg_3717;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((tmp_36_reg_14538 = ap_const_lv4_4) and (ap_ST_st16_fsm_15 = ap_CS_fsm))) then
j_15_end_4_fu_376 <= j_0_end_reg_3717;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((tmp_36_reg_14538 = ap_const_lv4_5) and (ap_ST_st16_fsm_15 = ap_CS_fsm))) then
j_15_end_5_fu_380 <= j_0_end_reg_3717;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((tmp_36_reg_14538 = ap_const_lv4_6) and (ap_ST_st16_fsm_15 = ap_CS_fsm))) then
j_15_end_6_fu_384 <= j_0_end_reg_3717;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((tmp_36_reg_14538 = ap_const_lv4_7) and (ap_ST_st16_fsm_15 = ap_CS_fsm))) then
j_15_end_7_fu_388 <= j_0_end_reg_3717;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((tmp_36_reg_14538 = ap_const_lv4_8) and (ap_ST_st16_fsm_15 = ap_CS_fsm))) then
j_15_end_8_fu_392 <= j_0_end_reg_3717;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((tmp_36_reg_14538 = ap_const_lv4_9) and (ap_ST_st16_fsm_15 = ap_CS_fsm))) then
j_15_end_9_fu_396 <= j_0_end_reg_3717;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((tmp_36_reg_14538 = ap_const_lv4_0) and (ap_ST_st16_fsm_15 = ap_CS_fsm))) then
j_15_end_fu_360 <= j_0_end_reg_3717;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((tmp_36_reg_14538 = ap_const_lv4_0) and (ap_ST_st15_fsm_14 = ap_CS_fsm))) then
j_bucket_index_0_s_fu_296(0) <= j_0_bucket_index_cast_reg_14592(0);
j_bucket_index_0_s_fu_296(1) <= j_0_bucket_index_cast_reg_14592(1);
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((tmp_36_reg_14538 = ap_const_lv4_A) and (ap_ST_st15_fsm_14 = ap_CS_fsm))) then
j_bucket_index_10_s_fu_336(0) <= j_0_bucket_index_cast_reg_14592(0);
j_bucket_index_10_s_fu_336(1) <= j_0_bucket_index_cast_reg_14592(1);
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((tmp_36_reg_14538 = ap_const_lv4_B) and (ap_ST_st15_fsm_14 = ap_CS_fsm))) then
j_bucket_index_11_s_fu_340(0) <= j_0_bucket_index_cast_reg_14592(0);
j_bucket_index_11_s_fu_340(1) <= j_0_bucket_index_cast_reg_14592(1);
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((tmp_36_reg_14538 = ap_const_lv4_C) and (ap_ST_st15_fsm_14 = ap_CS_fsm))) then
j_bucket_index_12_s_fu_344(0) <= j_0_bucket_index_cast_reg_14592(0);
j_bucket_index_12_s_fu_344(1) <= j_0_bucket_index_cast_reg_14592(1);
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((tmp_36_reg_14538 = ap_const_lv4_D) and (ap_ST_st15_fsm_14 = ap_CS_fsm))) then
j_bucket_index_13_s_fu_348(0) <= j_0_bucket_index_cast_reg_14592(0);
j_bucket_index_13_s_fu_348(1) <= j_0_bucket_index_cast_reg_14592(1);
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((tmp_36_reg_14538 = ap_const_lv4_E) and (ap_ST_st15_fsm_14 = ap_CS_fsm))) then
j_bucket_index_14_s_fu_352(0) <= j_0_bucket_index_cast_reg_14592(0);
j_bucket_index_14_s_fu_352(1) <= j_0_bucket_index_cast_reg_14592(1);
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((not((tmp_36_reg_14538 = ap_const_lv4_E)) and not((tmp_36_reg_14538 = ap_const_lv4_D)) and not((tmp_36_reg_14538 = ap_const_lv4_C)) and not((tmp_36_reg_14538 = ap_const_lv4_B)) and not((tmp_36_reg_14538 = ap_const_lv4_A)) and not((tmp_36_reg_14538 = ap_const_lv4_9)) and not((tmp_36_reg_14538 = ap_const_lv4_8)) and not((tmp_36_reg_14538 = ap_const_lv4_7)) and not((tmp_36_reg_14538 = ap_const_lv4_6)) and not((tmp_36_reg_14538 = ap_const_lv4_5)) and not((tmp_36_reg_14538 = ap_const_lv4_4)) and not((tmp_36_reg_14538 = ap_const_lv4_3)) and not((tmp_36_reg_14538 = ap_const_lv4_2)) and not((tmp_36_reg_14538 = ap_const_lv4_1)) and not((tmp_36_reg_14538 = ap_const_lv4_0)) and (ap_ST_st15_fsm_14 = ap_CS_fsm))) then
j_bucket_index_15_s_fu_356(0) <= j_0_bucket_index_cast_reg_14592(0);
j_bucket_index_15_s_fu_356(1) <= j_0_bucket_index_cast_reg_14592(1);
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((tmp_36_reg_14538 = ap_const_lv4_1) and (ap_ST_st15_fsm_14 = ap_CS_fsm))) then
j_bucket_index_1_s_fu_300(0) <= j_0_bucket_index_cast_reg_14592(0);
j_bucket_index_1_s_fu_300(1) <= j_0_bucket_index_cast_reg_14592(1);
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((tmp_36_reg_14538 = ap_const_lv4_2) and (ap_ST_st15_fsm_14 = ap_CS_fsm))) then
j_bucket_index_2_s_fu_304(0) <= j_0_bucket_index_cast_reg_14592(0);
j_bucket_index_2_s_fu_304(1) <= j_0_bucket_index_cast_reg_14592(1);
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((tmp_36_reg_14538 = ap_const_lv4_3) and (ap_ST_st15_fsm_14 = ap_CS_fsm))) then
j_bucket_index_3_s_fu_308(0) <= j_0_bucket_index_cast_reg_14592(0);
j_bucket_index_3_s_fu_308(1) <= j_0_bucket_index_cast_reg_14592(1);
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((tmp_36_reg_14538 = ap_const_lv4_4) and (ap_ST_st15_fsm_14 = ap_CS_fsm))) then
j_bucket_index_4_s_fu_312(0) <= j_0_bucket_index_cast_reg_14592(0);
j_bucket_index_4_s_fu_312(1) <= j_0_bucket_index_cast_reg_14592(1);
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((tmp_36_reg_14538 = ap_const_lv4_5) and (ap_ST_st15_fsm_14 = ap_CS_fsm))) then
j_bucket_index_5_s_fu_316(0) <= j_0_bucket_index_cast_reg_14592(0);
j_bucket_index_5_s_fu_316(1) <= j_0_bucket_index_cast_reg_14592(1);
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((tmp_36_reg_14538 = ap_const_lv4_6) and (ap_ST_st15_fsm_14 = ap_CS_fsm))) then
j_bucket_index_6_s_fu_320(0) <= j_0_bucket_index_cast_reg_14592(0);
j_bucket_index_6_s_fu_320(1) <= j_0_bucket_index_cast_reg_14592(1);
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((tmp_36_reg_14538 = ap_const_lv4_7) and (ap_ST_st15_fsm_14 = ap_CS_fsm))) then
j_bucket_index_7_s_fu_324(0) <= j_0_bucket_index_cast_reg_14592(0);
j_bucket_index_7_s_fu_324(1) <= j_0_bucket_index_cast_reg_14592(1);
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((tmp_36_reg_14538 = ap_const_lv4_8) and (ap_ST_st15_fsm_14 = ap_CS_fsm))) then
j_bucket_index_8_s_fu_328(0) <= j_0_bucket_index_cast_reg_14592(0);
j_bucket_index_8_s_fu_328(1) <= j_0_bucket_index_cast_reg_14592(1);
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((tmp_36_reg_14538 = ap_const_lv4_9) and (ap_ST_st15_fsm_14 = ap_CS_fsm))) then
j_bucket_index_9_s_fu_332(0) <= j_0_bucket_index_cast_reg_14592(0);
j_bucket_index_9_s_fu_332(1) <= j_0_bucket_index_cast_reg_14592(1);
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_ST_st2_fsm_1 = ap_CS_fsm)) then
k_4_reg_13968 <= k_4_fu_12996_p2;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_ST_st44_fsm_43 = ap_CS_fsm)) then
k_6_reg_14754 <= k_6_fu_13723_p2;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_ST_st19_fsm_18 = ap_CS_fsm)) then
k_7_reg_14615 <= k_7_fu_13544_p2;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ST_st45_fsm_44 = ap_CS_fsm) and (ap_const_lv1_0 = end_load_phi_phi_fu_12756_p32))) then
next_buckets_addr_2_reg_14790 <= tmp_10_reg_14775(4 - 1 downto 0);
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_ST_st28_fsm_27 = ap_CS_fsm)) then
next_buckets_addr_4_reg_14670 <= tmp_5_reg_14621(4 - 1 downto 0);
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((not((nfa_forward_buckets_rsp_empty_n = ap_const_logic_0)) and (ap_ST_st42_fsm_41 = ap_CS_fsm))) then
nfa_forward_buckets_addr_1_read_reg_14746 <= nfa_forward_buckets_datain;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ST_st39_fsm_38 = ap_CS_fsm) and not((nfa_forward_buckets_rsp_empty_n = ap_const_logic_0)))) then
nfa_forward_buckets_addr_read_reg_14735 <= nfa_forward_buckets_datain;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_ST_st29_fsm_28 = ap_CS_fsm)) then
not_s_reg_14675 <= not_s_fu_13615_p2;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ST_st35_fsm_34 = ap_CS_fsm) and not((sample_rsp_empty_n = ap_const_logic_0)))) then
sample_addr_read_reg_14718 <= sample_datain;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ST_st44_fsm_43 = ap_CS_fsm) and (ap_const_lv1_0 = exitcond_fu_13718_p2))) then
tmp_10_reg_14775(0) <= tmp_10_fu_13729_p1(0);
tmp_10_reg_14775(1) <= tmp_10_fu_13729_p1(1);
tmp_10_reg_14775(2) <= tmp_10_fu_13729_p1(2);
tmp_10_reg_14775(3) <= tmp_10_fu_13729_p1(3);
tmp_10_reg_14775(4) <= tmp_10_fu_13729_p1(4);
tmp_38_reg_14781 <= tmp_38_fu_13733_p1;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ST_st8_fsm_7 = ap_CS_fsm) and (exitcond2_fu_13247_p2 = ap_const_lv1_0))) then
tmp_36_reg_14538 <= tmp_36_fu_13263_p1;
tmp_8_reg_14527(0) <= tmp_8_fu_13258_p1(0);
tmp_8_reg_14527(1) <= tmp_8_fu_13258_p1(1);
tmp_8_reg_14527(2) <= tmp_8_fu_13258_p1(2);
tmp_8_reg_14527(3) <= tmp_8_fu_13258_p1(3);
tmp_8_reg_14527(4) <= tmp_8_fu_13258_p1(4);
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)))) then
tmp_37_reg_14631 <= tmp_37_fu_13557_p1;
tmp_5_reg_14621(0) <= tmp_5_fu_13550_p1(0);
tmp_5_reg_14621(1) <= tmp_5_fu_13550_p1(1);
tmp_5_reg_14621(2) <= tmp_5_fu_13550_p1(2);
tmp_5_reg_14621(3) <= tmp_5_fu_13550_p1(3);
tmp_5_reg_14621(4) <= tmp_5_fu_13550_p1(4);
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ST_st8_fsm_7 = ap_CS_fsm) and not((exitcond2_fu_13247_p2 = ap_const_lv1_0)))) then
tmp_7_reg_14542 <= tmp_7_fu_13267_p2;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_ST_st36_fsm_35 = ap_CS_fsm)) then
tmp_8_i1_reg_14723 <= tmp_8_i1_fu_13669_p2;
end if;
end if;
end process;
j_bucket_index_0_load_reg_14359(7 downto 2) <= "000000";
j_bucket_index_1_load_reg_14364(7 downto 2) <= "000000";
j_bucket_index_2_load_reg_14369(7 downto 2) <= "000000";
j_bucket_index_3_load_reg_14374(7 downto 2) <= "000000";
j_bucket_index_4_load_reg_14379(7 downto 2) <= "000000";
j_bucket_index_5_load_reg_14384(7 downto 2) <= "000000";
j_bucket_index_6_load_reg_14389(7 downto 2) <= "000000";
j_bucket_index_7_load_reg_14394(7 downto 2) <= "000000";
j_bucket_index_8_load_reg_14399(7 downto 2) <= "000000";
j_bucket_index_9_load_reg_14404(7 downto 2) <= "000000";
j_bucket_index_10_load_reg_14409(7 downto 2) <= "000000";
j_bucket_index_11_load_reg_14414(7 downto 2) <= "000000";
j_bucket_index_12_load_reg_14419(7 downto 2) <= "000000";
j_bucket_index_13_load_reg_14424(7 downto 2) <= "000000";
j_bucket_index_14_load_reg_14429(7 downto 2) <= "000000";
j_bucket_index_15_load_reg_14434(7 downto 2) <= "000000";
tmp_8_reg_14527(63 downto 5) <= "00000000000000000000000000000000000000000000000000000000000";
j_0_bucket_index_cast_reg_14592(7 downto 2) <= "000000";
tmp_5_reg_14621(63 downto 5) <= "00000000000000000000000000000000000000000000000000000000000";
tmp_10_reg_14775(63 downto 5) <= "00000000000000000000000000000000000000000000000000000000000";
j_bucket_index_addr13_phi_reg_8675(7 downto 2) <= "000000";
j_bucket_index_0_s_fu_296(7 downto 2) <= "000000";
j_bucket_index_1_s_fu_300(7 downto 2) <= "000000";
j_bucket_index_2_s_fu_304(7 downto 2) <= "000000";
j_bucket_index_3_s_fu_308(7 downto 2) <= "000000";
j_bucket_index_4_s_fu_312(7 downto 2) <= "000000";
j_bucket_index_5_s_fu_316(7 downto 2) <= "000000";
j_bucket_index_6_s_fu_320(7 downto 2) <= "000000";
j_bucket_index_7_s_fu_324(7 downto 2) <= "000000";
j_bucket_index_8_s_fu_328(7 downto 2) <= "000000";
j_bucket_index_9_s_fu_332(7 downto 2) <= "000000";
j_bucket_index_10_s_fu_336(7 downto 2) <= "000000";
j_bucket_index_11_s_fu_340(7 downto 2) <= "000000";
j_bucket_index_12_s_fu_344(7 downto 2) <= "000000";
j_bucket_index_13_s_fu_348(7 downto 2) <= "000000";
j_bucket_index_14_s_fu_352(7 downto 2) <= "000000";
j_bucket_index_15_s_fu_356(7 downto 2) <= "000000";
-- the next state (ap_NS_fsm) of the state machine. --
ap_NS_fsm_assign_proc : process (ap_start , ap_CS_fsm , nfa_forward_buckets_rsp_empty_n , sample_rsp_empty_n , exitcond2_fu_13247_p2 , tmp_11_fu_13276_p2 , tmp_9_fu_13539_p2 , end_0_phi_fu_5844_p32 , end_string_0_phi_fu_6831_p4 , brmerge_demorgan_fu_13621_p2 , brmerge_demorgan_reg_14680 , exitcond_fu_13718_p2 , all_end_phi_fu_12651_p36 , exitcond3_fu_12991_p2 , tmp_6_fu_13097_p2 , tmp_27_1_fu_13292_p2 , end_load_3_phi_phi_fu_11584_p32 , tmp1_fu_13626_p2 , any_state_load_1_phi_phi_fu_7706_p32)
begin
case ap_CS_fsm is
when ap_ST_st1_fsm_0 =>
if (not((ap_start = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st2_fsm_1;
else
ap_NS_fsm <= ap_ST_st1_fsm_0;
end if;
when ap_ST_st2_fsm_1 =>
if (not((ap_const_lv1_0 = exitcond3_fu_12991_p2))) then
ap_NS_fsm <= ap_ST_st7_fsm_6;
else
ap_NS_fsm <= ap_ST_st3_fsm_2;
end if;
when ap_ST_st3_fsm_2 =>
ap_NS_fsm <= ap_ST_st4_fsm_3;
when ap_ST_st4_fsm_3 =>
ap_NS_fsm <= ap_ST_st5_fsm_4;
when ap_ST_st5_fsm_4 =>
ap_NS_fsm <= ap_ST_st6_fsm_5;
when ap_ST_st6_fsm_5 =>
ap_NS_fsm <= ap_ST_st2_fsm_1;
when ap_ST_st7_fsm_6 =>
if ((ap_const_lv1_0 = tmp_6_fu_13097_p2)) then
ap_NS_fsm <= ap_ST_st8_fsm_7;
else
ap_NS_fsm <= ap_ST_st48_fsm_47;
end if;
when ap_ST_st8_fsm_7 =>
if (not((exitcond2_fu_13247_p2 = ap_const_lv1_0))) then
ap_NS_fsm <= ap_ST_st18_fsm_17;
else
ap_NS_fsm <= ap_ST_st9_fsm_8;
end if;
when ap_ST_st9_fsm_8 =>
ap_NS_fsm <= ap_ST_st10_fsm_9;
when ap_ST_st10_fsm_9 =>
ap_NS_fsm <= ap_ST_st11_fsm_10;
when ap_ST_st11_fsm_10 =>
ap_NS_fsm <= ap_ST_st12_fsm_11;
when ap_ST_st12_fsm_11 =>
if ((not((ap_const_lv1_0 = tmp_11_fu_13276_p2)) and not((ap_const_lv1_0 = tmp_27_1_fu_13292_p2)))) then
ap_NS_fsm <= ap_ST_st14_fsm_13;
else
ap_NS_fsm <= ap_ST_st13_fsm_12;
end if;
when ap_ST_st13_fsm_12 =>
ap_NS_fsm <= ap_ST_st14_fsm_13;
when ap_ST_st14_fsm_13 =>
ap_NS_fsm <= ap_ST_st15_fsm_14;
when ap_ST_st15_fsm_14 =>
ap_NS_fsm <= ap_ST_st16_fsm_15;
when ap_ST_st16_fsm_15 =>
ap_NS_fsm <= ap_ST_st17_fsm_16;
when ap_ST_st17_fsm_16 =>
ap_NS_fsm <= ap_ST_st8_fsm_7;
when ap_ST_st18_fsm_17 =>
ap_NS_fsm <= ap_ST_st19_fsm_18;
when ap_ST_st19_fsm_18 =>
if ((not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and not((ap_const_lv1_0 = end_0_phi_fu_5844_p32)) and not((ap_const_lv1_0 = end_string_0_phi_fu_6831_p4)) and (ap_const_lv1_0 = any_state_load_1_phi_phi_fu_7706_p32))) then
ap_NS_fsm <= ap_ST_st30_fsm_29;
elsif ((not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and not((ap_const_lv1_0 = end_0_phi_fu_5844_p32)) and not((ap_const_lv1_0 = end_string_0_phi_fu_6831_p4)) and not((ap_const_lv1_0 = any_state_load_1_phi_phi_fu_7706_p32)))) then
ap_NS_fsm <= ap_ST_st24_fsm_23;
elsif ((not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and not((ap_const_lv1_0 = end_0_phi_fu_5844_p32)) and (ap_const_lv1_0 = end_string_0_phi_fu_6831_p4))) then
ap_NS_fsm <= ap_ST_st23_fsm_22;
elsif ((not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and (ap_const_lv1_0 = end_0_phi_fu_5844_p32))) then
ap_NS_fsm <= ap_ST_st20_fsm_19;
else
ap_NS_fsm <= ap_ST_st44_fsm_43;
end if;
when ap_ST_st20_fsm_19 =>
ap_NS_fsm <= ap_ST_st21_fsm_20;
when ap_ST_st21_fsm_20 =>
ap_NS_fsm <= ap_ST_st22_fsm_21;
when ap_ST_st22_fsm_21 =>
ap_NS_fsm <= ap_ST_st30_fsm_29;
when ap_ST_st23_fsm_22 =>
ap_NS_fsm <= ap_ST_st30_fsm_29;
when ap_ST_st24_fsm_23 =>
ap_NS_fsm <= ap_ST_st25_fsm_24;
when ap_ST_st25_fsm_24 =>
ap_NS_fsm <= ap_ST_st26_fsm_25;
when ap_ST_st26_fsm_25 =>
ap_NS_fsm <= ap_ST_st27_fsm_26;
when ap_ST_st27_fsm_26 =>
ap_NS_fsm <= ap_ST_st28_fsm_27;
when ap_ST_st28_fsm_27 =>
ap_NS_fsm <= ap_ST_st29_fsm_28;
when ap_ST_st29_fsm_28 =>
ap_NS_fsm <= ap_ST_st30_fsm_29;
when ap_ST_st30_fsm_29 =>
if ((ap_const_lv1_0 = brmerge_demorgan_fu_13621_p2)) then
ap_NS_fsm <= ap_ST_st32_fsm_31;
else
ap_NS_fsm <= ap_ST_st31_fsm_30;
end if;
when ap_ST_st31_fsm_30 =>
ap_NS_fsm <= ap_ST_st32_fsm_31;
when ap_ST_st32_fsm_31 =>
if ((((ap_const_lv1_0 = end_load_3_phi_phi_fu_11584_p32) and (ap_const_lv1_0 = brmerge_demorgan_reg_14680)) or ((ap_const_lv1_0 = end_load_3_phi_phi_fu_11584_p32) and not((ap_const_lv1_0 = tmp1_fu_13626_p2))))) then
ap_NS_fsm <= ap_ST_st33_fsm_32;
elsif (((not((ap_const_lv1_0 = end_load_3_phi_phi_fu_11584_p32)) and (ap_const_lv1_0 = brmerge_demorgan_reg_14680)) or (not((ap_const_lv1_0 = end_load_3_phi_phi_fu_11584_p32)) and not((ap_const_lv1_0 = tmp1_fu_13626_p2))))) then
ap_NS_fsm <= ap_ST_st19_fsm_18;
else
ap_NS_fsm <= ap_ST_st48_fsm_47;
end if;
when ap_ST_st33_fsm_32 =>
ap_NS_fsm <= ap_ST_st34_fsm_33;
when ap_ST_st34_fsm_33 =>
ap_NS_fsm <= ap_ST_st35_fsm_34;
when ap_ST_st35_fsm_34 =>
if (not((sample_rsp_empty_n = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st36_fsm_35;
else
ap_NS_fsm <= ap_ST_st35_fsm_34;
end if;
when ap_ST_st36_fsm_35 =>
ap_NS_fsm <= ap_ST_st37_fsm_36;
when ap_ST_st37_fsm_36 =>
ap_NS_fsm <= ap_ST_st38_fsm_37;
when ap_ST_st38_fsm_37 =>
ap_NS_fsm <= ap_ST_st39_fsm_38;
when ap_ST_st39_fsm_38 =>
if (not((nfa_forward_buckets_rsp_empty_n = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st40_fsm_39;
else
ap_NS_fsm <= ap_ST_st39_fsm_38;
end if;
when ap_ST_st40_fsm_39 =>
ap_NS_fsm <= ap_ST_st41_fsm_40;
when ap_ST_st41_fsm_40 =>
ap_NS_fsm <= ap_ST_st42_fsm_41;
when ap_ST_st42_fsm_41 =>
if (not((nfa_forward_buckets_rsp_empty_n = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st43_fsm_42;
else
ap_NS_fsm <= ap_ST_st42_fsm_41;
end if;
when ap_ST_st43_fsm_42 =>
ap_NS_fsm <= ap_ST_st19_fsm_18;
when ap_ST_st44_fsm_43 =>
if ((not((ap_const_lv1_0 = exitcond_fu_13718_p2)) and not((ap_const_lv1_0 = all_end_phi_fu_12651_p36)))) then
ap_NS_fsm <= ap_ST_st7_fsm_6;
elsif ((not((ap_const_lv1_0 = exitcond_fu_13718_p2)) and (ap_const_lv1_0 = all_end_phi_fu_12651_p36))) then
ap_NS_fsm <= ap_ST_st18_fsm_17;
else
ap_NS_fsm <= ap_ST_st45_fsm_44;
end if;
when ap_ST_st45_fsm_44 =>
ap_NS_fsm <= ap_ST_st46_fsm_45;
when ap_ST_st46_fsm_45 =>
ap_NS_fsm <= ap_ST_st47_fsm_46;
when ap_ST_st47_fsm_46 =>
ap_NS_fsm <= ap_ST_st44_fsm_43;
when ap_ST_st48_fsm_47 =>
ap_NS_fsm <= ap_ST_st1_fsm_0;
when others =>
ap_NS_fsm <= "XXXXXX";
end case;
end process;
all_end_phi_fu_12651_p36 <= all_end_reg_12647;
-- any_state_load_1_phi_phi_fu_7706_p32 assign process. --
any_state_load_1_phi_phi_fu_7706_p32_assign_proc : process(tmp_37_fu_13557_p1, any_state_15_4_reg_5091, any_state_14_4_reg_5106, any_state_13_4_reg_5121, any_state_12_4_reg_5136, any_state_11_4_reg_5151, any_state_10_4_reg_5166, any_state_9_4_reg_5181, any_state_8_4_reg_5196, any_state_7_4_reg_5211, any_state_6_4_reg_5226, any_state_5_4_reg_5241, any_state_4_4_reg_5256, any_state_3_4_reg_5271, any_state_2_4_reg_5286, any_state_1_4_reg_5301, any_state_0_4_reg_5316, ap_sig_bdd_1962)
begin
if (ap_sig_bdd_1962) then
if ((tmp_37_fu_13557_p1 = ap_const_lv4_0)) then
any_state_load_1_phi_phi_fu_7706_p32 <= any_state_0_4_reg_5316;
elsif ((tmp_37_fu_13557_p1 = ap_const_lv4_E)) then
any_state_load_1_phi_phi_fu_7706_p32 <= any_state_14_4_reg_5106;
elsif ((tmp_37_fu_13557_p1 = ap_const_lv4_D)) then
any_state_load_1_phi_phi_fu_7706_p32 <= any_state_13_4_reg_5121;
elsif ((tmp_37_fu_13557_p1 = ap_const_lv4_C)) then
any_state_load_1_phi_phi_fu_7706_p32 <= any_state_12_4_reg_5136;
elsif ((tmp_37_fu_13557_p1 = ap_const_lv4_B)) then
any_state_load_1_phi_phi_fu_7706_p32 <= any_state_11_4_reg_5151;
elsif ((tmp_37_fu_13557_p1 = ap_const_lv4_A)) then
any_state_load_1_phi_phi_fu_7706_p32 <= any_state_10_4_reg_5166;
elsif ((tmp_37_fu_13557_p1 = ap_const_lv4_9)) then
any_state_load_1_phi_phi_fu_7706_p32 <= any_state_9_4_reg_5181;
elsif ((tmp_37_fu_13557_p1 = ap_const_lv4_8)) then
any_state_load_1_phi_phi_fu_7706_p32 <= any_state_8_4_reg_5196;
elsif ((tmp_37_fu_13557_p1 = ap_const_lv4_7)) then
any_state_load_1_phi_phi_fu_7706_p32 <= any_state_7_4_reg_5211;
elsif ((tmp_37_fu_13557_p1 = ap_const_lv4_6)) then
any_state_load_1_phi_phi_fu_7706_p32 <= any_state_6_4_reg_5226;
elsif ((tmp_37_fu_13557_p1 = ap_const_lv4_5)) then
any_state_load_1_phi_phi_fu_7706_p32 <= any_state_5_4_reg_5241;
elsif ((tmp_37_fu_13557_p1 = ap_const_lv4_4)) then
any_state_load_1_phi_phi_fu_7706_p32 <= any_state_4_4_reg_5256;
elsif ((tmp_37_fu_13557_p1 = ap_const_lv4_3)) then
any_state_load_1_phi_phi_fu_7706_p32 <= any_state_3_4_reg_5271;
elsif ((tmp_37_fu_13557_p1 = ap_const_lv4_2)) then
any_state_load_1_phi_phi_fu_7706_p32 <= any_state_2_4_reg_5286;
elsif ((tmp_37_fu_13557_p1 = ap_const_lv4_1)) then
any_state_load_1_phi_phi_fu_7706_p32 <= any_state_1_4_reg_5301;
elsif ((ap_true = ap_true)) then
any_state_load_1_phi_phi_fu_7706_p32 <= any_state_15_4_reg_5091;
else
any_state_load_1_phi_phi_fu_7706_p32 <= "X";
end if;
else
any_state_load_1_phi_phi_fu_7706_p32 <= "X";
end if;
end process;
-- any_state_load_phi_phi_fu_6778_p32 assign process. --
any_state_load_phi_phi_fu_6778_p32_assign_proc : process(tmp_37_fu_13557_p1, any_state_15_4_reg_5091, any_state_14_4_reg_5106, any_state_13_4_reg_5121, any_state_12_4_reg_5136, any_state_11_4_reg_5151, any_state_10_4_reg_5166, any_state_9_4_reg_5181, any_state_8_4_reg_5196, any_state_7_4_reg_5211, any_state_6_4_reg_5226, any_state_5_4_reg_5241, any_state_4_4_reg_5256, any_state_3_4_reg_5271, any_state_2_4_reg_5286, any_state_1_4_reg_5301, any_state_0_4_reg_5316, ap_sig_bdd_1739)
begin
if (ap_sig_bdd_1739) then
if ((tmp_37_fu_13557_p1 = ap_const_lv4_0)) then
any_state_load_phi_phi_fu_6778_p32 <= any_state_0_4_reg_5316;
elsif ((tmp_37_fu_13557_p1 = ap_const_lv4_E)) then
any_state_load_phi_phi_fu_6778_p32 <= any_state_14_4_reg_5106;
elsif ((tmp_37_fu_13557_p1 = ap_const_lv4_D)) then
any_state_load_phi_phi_fu_6778_p32 <= any_state_13_4_reg_5121;
elsif ((tmp_37_fu_13557_p1 = ap_const_lv4_C)) then
any_state_load_phi_phi_fu_6778_p32 <= any_state_12_4_reg_5136;
elsif ((tmp_37_fu_13557_p1 = ap_const_lv4_B)) then
any_state_load_phi_phi_fu_6778_p32 <= any_state_11_4_reg_5151;
elsif ((tmp_37_fu_13557_p1 = ap_const_lv4_A)) then
any_state_load_phi_phi_fu_6778_p32 <= any_state_10_4_reg_5166;
elsif ((tmp_37_fu_13557_p1 = ap_const_lv4_9)) then
any_state_load_phi_phi_fu_6778_p32 <= any_state_9_4_reg_5181;
elsif ((tmp_37_fu_13557_p1 = ap_const_lv4_8)) then
any_state_load_phi_phi_fu_6778_p32 <= any_state_8_4_reg_5196;
elsif ((tmp_37_fu_13557_p1 = ap_const_lv4_7)) then
any_state_load_phi_phi_fu_6778_p32 <= any_state_7_4_reg_5211;
elsif ((tmp_37_fu_13557_p1 = ap_const_lv4_6)) then
any_state_load_phi_phi_fu_6778_p32 <= any_state_6_4_reg_5226;
elsif ((tmp_37_fu_13557_p1 = ap_const_lv4_5)) then
any_state_load_phi_phi_fu_6778_p32 <= any_state_5_4_reg_5241;
elsif ((tmp_37_fu_13557_p1 = ap_const_lv4_4)) then
any_state_load_phi_phi_fu_6778_p32 <= any_state_4_4_reg_5256;
elsif ((tmp_37_fu_13557_p1 = ap_const_lv4_3)) then
any_state_load_phi_phi_fu_6778_p32 <= any_state_3_4_reg_5271;
elsif ((tmp_37_fu_13557_p1 = ap_const_lv4_2)) then
any_state_load_phi_phi_fu_6778_p32 <= any_state_2_4_reg_5286;
elsif ((tmp_37_fu_13557_p1 = ap_const_lv4_1)) then
any_state_load_phi_phi_fu_6778_p32 <= any_state_1_4_reg_5301;
elsif ((ap_true = ap_true)) then
any_state_load_phi_phi_fu_6778_p32 <= any_state_15_4_reg_5091;
else
any_state_load_phi_phi_fu_6778_p32 <= "X";
end if;
else
any_state_load_phi_phi_fu_6778_p32 <= "X";
end if;
end process;
-- ap_done assign process. --
ap_done_assign_proc : process(ap_start, ap_CS_fsm)
begin
if (((not((ap_const_logic_1 = ap_start)) and (ap_ST_st1_fsm_0 = ap_CS_fsm)) or (ap_ST_st48_fsm_47 = ap_CS_fsm))) then
ap_done <= ap_const_logic_1;
else
ap_done <= ap_const_logic_0;
end if;
end process;
-- ap_idle assign process. --
ap_idle_assign_proc : process(ap_start, ap_CS_fsm)
begin
if ((not((ap_const_logic_1 = ap_start)) and (ap_ST_st1_fsm_0 = ap_CS_fsm))) then
ap_idle <= ap_const_logic_1;
else
ap_idle <= ap_const_logic_0;
end if;
end process;
-- ap_ready assign process. --
ap_ready_assign_proc : process(ap_CS_fsm)
begin
if ((ap_ST_st48_fsm_47 = ap_CS_fsm)) then
ap_ready <= ap_const_logic_1;
else
ap_ready <= ap_const_logic_0;
end if;
end process;
-- ap_return assign process. --
ap_return_assign_proc : process(ap_CS_fsm, p_0_reg_12882, ap_return_preg)
begin
if ((ap_ST_st48_fsm_47 = ap_CS_fsm)) then
ap_return <= p_0_reg_12882;
else
ap_return <= ap_return_preg;
end if;
end process;
-- ap_sig_bdd_1202 assign process. --
ap_sig_bdd_1202_assign_proc : process(tmp_11_fu_13276_p2, tmp_27_1_fu_13292_p2)
begin
ap_sig_bdd_1202 <= (not((ap_const_lv1_0 = tmp_11_fu_13276_p2)) and (ap_const_lv1_0 = tmp_27_1_fu_13292_p2));
end process;
-- ap_sig_bdd_1739 assign process. --
ap_sig_bdd_1739_assign_proc : process(ap_CS_fsm, tmp_7_reg_14542, tmp_9_fu_13539_p2, end_0_phi_fu_5844_p32)
begin
ap_sig_bdd_1739 <= ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and not((ap_const_lv1_0 = end_0_phi_fu_5844_p32)) and (ap_const_lv1_0 = tmp_7_reg_14542));
end process;
-- ap_sig_bdd_1793 assign process. --
ap_sig_bdd_1793_assign_proc : process(ap_CS_fsm, tmp_9_fu_13539_p2, end_0_phi_fu_5844_p32)
begin
ap_sig_bdd_1793 <= ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and not((ap_const_lv1_0 = end_0_phi_fu_5844_p32)));
end process;
-- ap_sig_bdd_1962 assign process. --
ap_sig_bdd_1962_assign_proc : process(ap_CS_fsm, tmp_9_fu_13539_p2, end_0_phi_fu_5844_p32, end_string_0_phi_fu_6831_p4)
begin
ap_sig_bdd_1962 <= ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and not((ap_const_lv1_0 = end_0_phi_fu_5844_p32)) and not((ap_const_lv1_0 = end_string_0_phi_fu_6831_p4)));
end process;
-- ap_sig_bdd_2491 assign process. --
ap_sig_bdd_2491_assign_proc : process(brmerge_demorgan_reg_14680, tmp1_fu_13626_p2)
begin
ap_sig_bdd_2491 <= ((ap_const_lv1_0 = brmerge_demorgan_reg_14680) or not((ap_const_lv1_0 = tmp1_fu_13626_p2)));
end process;
-- ap_sig_bdd_2495 assign process. --
ap_sig_bdd_2495_assign_proc : process(tmp_37_reg_14631, brmerge_demorgan_reg_14680, tmp1_fu_13626_p2)
begin
ap_sig_bdd_2495 <= (((ap_const_lv1_0 = brmerge_demorgan_reg_14680) and (tmp_37_reg_14631 = ap_const_lv4_1)) or (not((ap_const_lv1_0 = tmp1_fu_13626_p2)) and (tmp_37_reg_14631 = ap_const_lv4_1)));
end process;
-- ap_sig_bdd_2499 assign process. --
ap_sig_bdd_2499_assign_proc : process(tmp_37_reg_14631, brmerge_demorgan_reg_14680, tmp1_fu_13626_p2)
begin
ap_sig_bdd_2499 <= (((ap_const_lv1_0 = brmerge_demorgan_reg_14680) and (tmp_37_reg_14631 = ap_const_lv4_2)) or (not((ap_const_lv1_0 = tmp1_fu_13626_p2)) and (tmp_37_reg_14631 = ap_const_lv4_2)));
end process;
-- ap_sig_bdd_2503 assign process. --
ap_sig_bdd_2503_assign_proc : process(tmp_37_reg_14631, brmerge_demorgan_reg_14680, tmp1_fu_13626_p2)
begin
ap_sig_bdd_2503 <= (((ap_const_lv1_0 = brmerge_demorgan_reg_14680) and (tmp_37_reg_14631 = ap_const_lv4_3)) or (not((ap_const_lv1_0 = tmp1_fu_13626_p2)) and (tmp_37_reg_14631 = ap_const_lv4_3)));
end process;
-- ap_sig_bdd_2507 assign process. --
ap_sig_bdd_2507_assign_proc : process(tmp_37_reg_14631, brmerge_demorgan_reg_14680, tmp1_fu_13626_p2)
begin
ap_sig_bdd_2507 <= (((ap_const_lv1_0 = brmerge_demorgan_reg_14680) and (tmp_37_reg_14631 = ap_const_lv4_4)) or (not((ap_const_lv1_0 = tmp1_fu_13626_p2)) and (tmp_37_reg_14631 = ap_const_lv4_4)));
end process;
-- ap_sig_bdd_2511 assign process. --
ap_sig_bdd_2511_assign_proc : process(tmp_37_reg_14631, brmerge_demorgan_reg_14680, tmp1_fu_13626_p2)
begin
ap_sig_bdd_2511 <= (((ap_const_lv1_0 = brmerge_demorgan_reg_14680) and (tmp_37_reg_14631 = ap_const_lv4_5)) or (not((ap_const_lv1_0 = tmp1_fu_13626_p2)) and (tmp_37_reg_14631 = ap_const_lv4_5)));
end process;
-- ap_sig_bdd_2515 assign process. --
ap_sig_bdd_2515_assign_proc : process(tmp_37_reg_14631, brmerge_demorgan_reg_14680, tmp1_fu_13626_p2)
begin
ap_sig_bdd_2515 <= (((ap_const_lv1_0 = brmerge_demorgan_reg_14680) and (tmp_37_reg_14631 = ap_const_lv4_6)) or (not((ap_const_lv1_0 = tmp1_fu_13626_p2)) and (tmp_37_reg_14631 = ap_const_lv4_6)));
end process;
-- ap_sig_bdd_2519 assign process. --
ap_sig_bdd_2519_assign_proc : process(tmp_37_reg_14631, brmerge_demorgan_reg_14680, tmp1_fu_13626_p2)
begin
ap_sig_bdd_2519 <= (((ap_const_lv1_0 = brmerge_demorgan_reg_14680) and (tmp_37_reg_14631 = ap_const_lv4_7)) or (not((ap_const_lv1_0 = tmp1_fu_13626_p2)) and (tmp_37_reg_14631 = ap_const_lv4_7)));
end process;
-- ap_sig_bdd_2523 assign process. --
ap_sig_bdd_2523_assign_proc : process(tmp_37_reg_14631, brmerge_demorgan_reg_14680, tmp1_fu_13626_p2)
begin
ap_sig_bdd_2523 <= (((ap_const_lv1_0 = brmerge_demorgan_reg_14680) and (tmp_37_reg_14631 = ap_const_lv4_8)) or (not((ap_const_lv1_0 = tmp1_fu_13626_p2)) and (tmp_37_reg_14631 = ap_const_lv4_8)));
end process;
-- ap_sig_bdd_2527 assign process. --
ap_sig_bdd_2527_assign_proc : process(tmp_37_reg_14631, brmerge_demorgan_reg_14680, tmp1_fu_13626_p2)
begin
ap_sig_bdd_2527 <= (((ap_const_lv1_0 = brmerge_demorgan_reg_14680) and (tmp_37_reg_14631 = ap_const_lv4_9)) or (not((ap_const_lv1_0 = tmp1_fu_13626_p2)) and (tmp_37_reg_14631 = ap_const_lv4_9)));
end process;
-- ap_sig_bdd_2531 assign process. --
ap_sig_bdd_2531_assign_proc : process(tmp_37_reg_14631, brmerge_demorgan_reg_14680, tmp1_fu_13626_p2)
begin
ap_sig_bdd_2531 <= (((ap_const_lv1_0 = brmerge_demorgan_reg_14680) and (tmp_37_reg_14631 = ap_const_lv4_A)) or (not((ap_const_lv1_0 = tmp1_fu_13626_p2)) and (tmp_37_reg_14631 = ap_const_lv4_A)));
end process;
-- ap_sig_bdd_2535 assign process. --
ap_sig_bdd_2535_assign_proc : process(tmp_37_reg_14631, brmerge_demorgan_reg_14680, tmp1_fu_13626_p2)
begin
ap_sig_bdd_2535 <= (((ap_const_lv1_0 = brmerge_demorgan_reg_14680) and (tmp_37_reg_14631 = ap_const_lv4_B)) or (not((ap_const_lv1_0 = tmp1_fu_13626_p2)) and (tmp_37_reg_14631 = ap_const_lv4_B)));
end process;
-- ap_sig_bdd_2539 assign process. --
ap_sig_bdd_2539_assign_proc : process(tmp_37_reg_14631, brmerge_demorgan_reg_14680, tmp1_fu_13626_p2)
begin
ap_sig_bdd_2539 <= (((ap_const_lv1_0 = brmerge_demorgan_reg_14680) and (tmp_37_reg_14631 = ap_const_lv4_C)) or (not((ap_const_lv1_0 = tmp1_fu_13626_p2)) and (tmp_37_reg_14631 = ap_const_lv4_C)));
end process;
-- ap_sig_bdd_2543 assign process. --
ap_sig_bdd_2543_assign_proc : process(tmp_37_reg_14631, brmerge_demorgan_reg_14680, tmp1_fu_13626_p2)
begin
ap_sig_bdd_2543 <= (((ap_const_lv1_0 = brmerge_demorgan_reg_14680) and (tmp_37_reg_14631 = ap_const_lv4_D)) or (not((ap_const_lv1_0 = tmp1_fu_13626_p2)) and (tmp_37_reg_14631 = ap_const_lv4_D)));
end process;
-- ap_sig_bdd_2547 assign process. --
ap_sig_bdd_2547_assign_proc : process(tmp_37_reg_14631, brmerge_demorgan_reg_14680, tmp1_fu_13626_p2)
begin
ap_sig_bdd_2547 <= (((ap_const_lv1_0 = brmerge_demorgan_reg_14680) and (tmp_37_reg_14631 = ap_const_lv4_E)) or (not((ap_const_lv1_0 = tmp1_fu_13626_p2)) and (tmp_37_reg_14631 = ap_const_lv4_E)));
end process;
-- ap_sig_bdd_2551 assign process. --
ap_sig_bdd_2551_assign_proc : process(tmp_37_reg_14631, brmerge_demorgan_reg_14680, tmp1_fu_13626_p2)
begin
ap_sig_bdd_2551 <= (((ap_const_lv1_0 = brmerge_demorgan_reg_14680) and (tmp_37_reg_14631 = ap_const_lv4_0)) or (not((ap_const_lv1_0 = tmp1_fu_13626_p2)) and (tmp_37_reg_14631 = ap_const_lv4_0)));
end process;
-- ap_sig_bdd_2557 assign process. --
ap_sig_bdd_2557_assign_proc : process(brmerge_demorgan_reg_14680, end_load_3_phi_phi_fu_11584_p32, tmp1_fu_13626_p2)
begin
ap_sig_bdd_2557 <= (((ap_const_lv1_0 = end_load_3_phi_phi_fu_11584_p32) and (ap_const_lv1_0 = brmerge_demorgan_reg_14680)) or ((ap_const_lv1_0 = end_load_3_phi_phi_fu_11584_p32) and not((ap_const_lv1_0 = tmp1_fu_13626_p2))));
end process;
-- ap_sig_bdd_2561 assign process. --
ap_sig_bdd_2561_assign_proc : process(tmp_37_reg_14631, brmerge_demorgan_reg_14680, end_load_3_phi_phi_fu_11584_p32, tmp1_fu_13626_p2)
begin
ap_sig_bdd_2561 <= (((ap_const_lv1_0 = end_load_3_phi_phi_fu_11584_p32) and (ap_const_lv1_0 = brmerge_demorgan_reg_14680) and (tmp_37_reg_14631 = ap_const_lv4_1)) or ((ap_const_lv1_0 = end_load_3_phi_phi_fu_11584_p32) and not((ap_const_lv1_0 = tmp1_fu_13626_p2)) and (tmp_37_reg_14631 = ap_const_lv4_1)));
end process;
-- ap_sig_bdd_2565 assign process. --
ap_sig_bdd_2565_assign_proc : process(tmp_37_reg_14631, brmerge_demorgan_reg_14680, end_load_3_phi_phi_fu_11584_p32, tmp1_fu_13626_p2)
begin
ap_sig_bdd_2565 <= (((ap_const_lv1_0 = end_load_3_phi_phi_fu_11584_p32) and (ap_const_lv1_0 = brmerge_demorgan_reg_14680) and (tmp_37_reg_14631 = ap_const_lv4_2)) or ((ap_const_lv1_0 = end_load_3_phi_phi_fu_11584_p32) and not((ap_const_lv1_0 = tmp1_fu_13626_p2)) and (tmp_37_reg_14631 = ap_const_lv4_2)));
end process;
-- ap_sig_bdd_2569 assign process. --
ap_sig_bdd_2569_assign_proc : process(tmp_37_reg_14631, brmerge_demorgan_reg_14680, end_load_3_phi_phi_fu_11584_p32, tmp1_fu_13626_p2)
begin
ap_sig_bdd_2569 <= (((ap_const_lv1_0 = end_load_3_phi_phi_fu_11584_p32) and (ap_const_lv1_0 = brmerge_demorgan_reg_14680) and (tmp_37_reg_14631 = ap_const_lv4_3)) or ((ap_const_lv1_0 = end_load_3_phi_phi_fu_11584_p32) and not((ap_const_lv1_0 = tmp1_fu_13626_p2)) and (tmp_37_reg_14631 = ap_const_lv4_3)));
end process;
-- ap_sig_bdd_2573 assign process. --
ap_sig_bdd_2573_assign_proc : process(tmp_37_reg_14631, brmerge_demorgan_reg_14680, end_load_3_phi_phi_fu_11584_p32, tmp1_fu_13626_p2)
begin
ap_sig_bdd_2573 <= (((ap_const_lv1_0 = end_load_3_phi_phi_fu_11584_p32) and (ap_const_lv1_0 = brmerge_demorgan_reg_14680) and (tmp_37_reg_14631 = ap_const_lv4_4)) or ((ap_const_lv1_0 = end_load_3_phi_phi_fu_11584_p32) and not((ap_const_lv1_0 = tmp1_fu_13626_p2)) and (tmp_37_reg_14631 = ap_const_lv4_4)));
end process;
-- ap_sig_bdd_2577 assign process. --
ap_sig_bdd_2577_assign_proc : process(tmp_37_reg_14631, brmerge_demorgan_reg_14680, end_load_3_phi_phi_fu_11584_p32, tmp1_fu_13626_p2)
begin
ap_sig_bdd_2577 <= (((ap_const_lv1_0 = end_load_3_phi_phi_fu_11584_p32) and (ap_const_lv1_0 = brmerge_demorgan_reg_14680) and (tmp_37_reg_14631 = ap_const_lv4_5)) or ((ap_const_lv1_0 = end_load_3_phi_phi_fu_11584_p32) and not((ap_const_lv1_0 = tmp1_fu_13626_p2)) and (tmp_37_reg_14631 = ap_const_lv4_5)));
end process;
-- ap_sig_bdd_2581 assign process. --
ap_sig_bdd_2581_assign_proc : process(tmp_37_reg_14631, brmerge_demorgan_reg_14680, end_load_3_phi_phi_fu_11584_p32, tmp1_fu_13626_p2)
begin
ap_sig_bdd_2581 <= (((ap_const_lv1_0 = end_load_3_phi_phi_fu_11584_p32) and (ap_const_lv1_0 = brmerge_demorgan_reg_14680) and (tmp_37_reg_14631 = ap_const_lv4_6)) or ((ap_const_lv1_0 = end_load_3_phi_phi_fu_11584_p32) and not((ap_const_lv1_0 = tmp1_fu_13626_p2)) and (tmp_37_reg_14631 = ap_const_lv4_6)));
end process;
-- ap_sig_bdd_2585 assign process. --
ap_sig_bdd_2585_assign_proc : process(tmp_37_reg_14631, brmerge_demorgan_reg_14680, end_load_3_phi_phi_fu_11584_p32, tmp1_fu_13626_p2)
begin
ap_sig_bdd_2585 <= (((ap_const_lv1_0 = end_load_3_phi_phi_fu_11584_p32) and (ap_const_lv1_0 = brmerge_demorgan_reg_14680) and (tmp_37_reg_14631 = ap_const_lv4_7)) or ((ap_const_lv1_0 = end_load_3_phi_phi_fu_11584_p32) and not((ap_const_lv1_0 = tmp1_fu_13626_p2)) and (tmp_37_reg_14631 = ap_const_lv4_7)));
end process;
-- ap_sig_bdd_2589 assign process. --
ap_sig_bdd_2589_assign_proc : process(tmp_37_reg_14631, brmerge_demorgan_reg_14680, end_load_3_phi_phi_fu_11584_p32, tmp1_fu_13626_p2)
begin
ap_sig_bdd_2589 <= (((ap_const_lv1_0 = end_load_3_phi_phi_fu_11584_p32) and (ap_const_lv1_0 = brmerge_demorgan_reg_14680) and (tmp_37_reg_14631 = ap_const_lv4_8)) or ((ap_const_lv1_0 = end_load_3_phi_phi_fu_11584_p32) and not((ap_const_lv1_0 = tmp1_fu_13626_p2)) and (tmp_37_reg_14631 = ap_const_lv4_8)));
end process;
-- ap_sig_bdd_2593 assign process. --
ap_sig_bdd_2593_assign_proc : process(tmp_37_reg_14631, brmerge_demorgan_reg_14680, end_load_3_phi_phi_fu_11584_p32, tmp1_fu_13626_p2)
begin
ap_sig_bdd_2593 <= (((ap_const_lv1_0 = end_load_3_phi_phi_fu_11584_p32) and (ap_const_lv1_0 = brmerge_demorgan_reg_14680) and (tmp_37_reg_14631 = ap_const_lv4_9)) or ((ap_const_lv1_0 = end_load_3_phi_phi_fu_11584_p32) and not((ap_const_lv1_0 = tmp1_fu_13626_p2)) and (tmp_37_reg_14631 = ap_const_lv4_9)));
end process;
-- ap_sig_bdd_2597 assign process. --
ap_sig_bdd_2597_assign_proc : process(tmp_37_reg_14631, brmerge_demorgan_reg_14680, end_load_3_phi_phi_fu_11584_p32, tmp1_fu_13626_p2)
begin
ap_sig_bdd_2597 <= (((ap_const_lv1_0 = end_load_3_phi_phi_fu_11584_p32) and (ap_const_lv1_0 = brmerge_demorgan_reg_14680) and (tmp_37_reg_14631 = ap_const_lv4_A)) or ((ap_const_lv1_0 = end_load_3_phi_phi_fu_11584_p32) and not((ap_const_lv1_0 = tmp1_fu_13626_p2)) and (tmp_37_reg_14631 = ap_const_lv4_A)));
end process;
-- ap_sig_bdd_2601 assign process. --
ap_sig_bdd_2601_assign_proc : process(tmp_37_reg_14631, brmerge_demorgan_reg_14680, end_load_3_phi_phi_fu_11584_p32, tmp1_fu_13626_p2)
begin
ap_sig_bdd_2601 <= (((ap_const_lv1_0 = end_load_3_phi_phi_fu_11584_p32) and (ap_const_lv1_0 = brmerge_demorgan_reg_14680) and (tmp_37_reg_14631 = ap_const_lv4_B)) or ((ap_const_lv1_0 = end_load_3_phi_phi_fu_11584_p32) and not((ap_const_lv1_0 = tmp1_fu_13626_p2)) and (tmp_37_reg_14631 = ap_const_lv4_B)));
end process;
-- ap_sig_bdd_2605 assign process. --
ap_sig_bdd_2605_assign_proc : process(tmp_37_reg_14631, brmerge_demorgan_reg_14680, end_load_3_phi_phi_fu_11584_p32, tmp1_fu_13626_p2)
begin
ap_sig_bdd_2605 <= (((ap_const_lv1_0 = end_load_3_phi_phi_fu_11584_p32) and (ap_const_lv1_0 = brmerge_demorgan_reg_14680) and (tmp_37_reg_14631 = ap_const_lv4_C)) or ((ap_const_lv1_0 = end_load_3_phi_phi_fu_11584_p32) and not((ap_const_lv1_0 = tmp1_fu_13626_p2)) and (tmp_37_reg_14631 = ap_const_lv4_C)));
end process;
-- ap_sig_bdd_2609 assign process. --
ap_sig_bdd_2609_assign_proc : process(tmp_37_reg_14631, brmerge_demorgan_reg_14680, end_load_3_phi_phi_fu_11584_p32, tmp1_fu_13626_p2)
begin
ap_sig_bdd_2609 <= (((ap_const_lv1_0 = end_load_3_phi_phi_fu_11584_p32) and (ap_const_lv1_0 = brmerge_demorgan_reg_14680) and (tmp_37_reg_14631 = ap_const_lv4_D)) or ((ap_const_lv1_0 = end_load_3_phi_phi_fu_11584_p32) and not((ap_const_lv1_0 = tmp1_fu_13626_p2)) and (tmp_37_reg_14631 = ap_const_lv4_D)));
end process;
-- ap_sig_bdd_2613 assign process. --
ap_sig_bdd_2613_assign_proc : process(tmp_37_reg_14631, brmerge_demorgan_reg_14680, end_load_3_phi_phi_fu_11584_p32, tmp1_fu_13626_p2)
begin
ap_sig_bdd_2613 <= (((ap_const_lv1_0 = end_load_3_phi_phi_fu_11584_p32) and (ap_const_lv1_0 = brmerge_demorgan_reg_14680) and (tmp_37_reg_14631 = ap_const_lv4_E)) or ((ap_const_lv1_0 = end_load_3_phi_phi_fu_11584_p32) and not((ap_const_lv1_0 = tmp1_fu_13626_p2)) and (tmp_37_reg_14631 = ap_const_lv4_E)));
end process;
-- ap_sig_bdd_2617 assign process. --
ap_sig_bdd_2617_assign_proc : process(tmp_37_reg_14631, brmerge_demorgan_reg_14680, end_load_3_phi_phi_fu_11584_p32, tmp1_fu_13626_p2)
begin
ap_sig_bdd_2617 <= (((ap_const_lv1_0 = end_load_3_phi_phi_fu_11584_p32) and (ap_const_lv1_0 = brmerge_demorgan_reg_14680) and (tmp_37_reg_14631 = ap_const_lv4_0)) or ((ap_const_lv1_0 = end_load_3_phi_phi_fu_11584_p32) and not((ap_const_lv1_0 = tmp1_fu_13626_p2)) and (tmp_37_reg_14631 = ap_const_lv4_0)));
end process;
-- ap_sig_bdd_2953 assign process. --
ap_sig_bdd_2953_assign_proc : process(tmp_38_reg_14781, all_end_reg_12647)
begin
ap_sig_bdd_2953 <= ((tmp_38_reg_14781 = ap_const_lv4_1) and not((ap_const_lv1_0 = all_end_reg_12647)));
end process;
-- ap_sig_bdd_2955 assign process. --
ap_sig_bdd_2955_assign_proc : process(tmp_38_reg_14781, all_end_reg_12647)
begin
ap_sig_bdd_2955 <= ((tmp_38_reg_14781 = ap_const_lv4_2) and not((ap_const_lv1_0 = all_end_reg_12647)));
end process;
-- ap_sig_bdd_2957 assign process. --
ap_sig_bdd_2957_assign_proc : process(tmp_38_reg_14781, all_end_reg_12647)
begin
ap_sig_bdd_2957 <= ((tmp_38_reg_14781 = ap_const_lv4_3) and not((ap_const_lv1_0 = all_end_reg_12647)));
end process;
-- ap_sig_bdd_2959 assign process. --
ap_sig_bdd_2959_assign_proc : process(tmp_38_reg_14781, all_end_reg_12647)
begin
ap_sig_bdd_2959 <= ((tmp_38_reg_14781 = ap_const_lv4_4) and not((ap_const_lv1_0 = all_end_reg_12647)));
end process;
-- ap_sig_bdd_2961 assign process. --
ap_sig_bdd_2961_assign_proc : process(tmp_38_reg_14781, all_end_reg_12647)
begin
ap_sig_bdd_2961 <= ((tmp_38_reg_14781 = ap_const_lv4_5) and not((ap_const_lv1_0 = all_end_reg_12647)));
end process;
-- ap_sig_bdd_2963 assign process. --
ap_sig_bdd_2963_assign_proc : process(tmp_38_reg_14781, all_end_reg_12647)
begin
ap_sig_bdd_2963 <= ((tmp_38_reg_14781 = ap_const_lv4_6) and not((ap_const_lv1_0 = all_end_reg_12647)));
end process;
-- ap_sig_bdd_2965 assign process. --
ap_sig_bdd_2965_assign_proc : process(tmp_38_reg_14781, all_end_reg_12647)
begin
ap_sig_bdd_2965 <= ((tmp_38_reg_14781 = ap_const_lv4_7) and not((ap_const_lv1_0 = all_end_reg_12647)));
end process;
-- ap_sig_bdd_2967 assign process. --
ap_sig_bdd_2967_assign_proc : process(tmp_38_reg_14781, all_end_reg_12647)
begin
ap_sig_bdd_2967 <= ((tmp_38_reg_14781 = ap_const_lv4_8) and not((ap_const_lv1_0 = all_end_reg_12647)));
end process;
-- ap_sig_bdd_2969 assign process. --
ap_sig_bdd_2969_assign_proc : process(tmp_38_reg_14781, all_end_reg_12647)
begin
ap_sig_bdd_2969 <= ((tmp_38_reg_14781 = ap_const_lv4_9) and not((ap_const_lv1_0 = all_end_reg_12647)));
end process;
-- ap_sig_bdd_2971 assign process. --
ap_sig_bdd_2971_assign_proc : process(tmp_38_reg_14781, all_end_reg_12647)
begin
ap_sig_bdd_2971 <= ((tmp_38_reg_14781 = ap_const_lv4_A) and not((ap_const_lv1_0 = all_end_reg_12647)));
end process;
-- ap_sig_bdd_2973 assign process. --
ap_sig_bdd_2973_assign_proc : process(tmp_38_reg_14781, all_end_reg_12647)
begin
ap_sig_bdd_2973 <= ((tmp_38_reg_14781 = ap_const_lv4_B) and not((ap_const_lv1_0 = all_end_reg_12647)));
end process;
-- ap_sig_bdd_2975 assign process. --
ap_sig_bdd_2975_assign_proc : process(tmp_38_reg_14781, all_end_reg_12647)
begin
ap_sig_bdd_2975 <= ((tmp_38_reg_14781 = ap_const_lv4_C) and not((ap_const_lv1_0 = all_end_reg_12647)));
end process;
-- ap_sig_bdd_2977 assign process. --
ap_sig_bdd_2977_assign_proc : process(tmp_38_reg_14781, all_end_reg_12647)
begin
ap_sig_bdd_2977 <= ((tmp_38_reg_14781 = ap_const_lv4_D) and not((ap_const_lv1_0 = all_end_reg_12647)));
end process;
-- ap_sig_bdd_2979 assign process. --
ap_sig_bdd_2979_assign_proc : process(tmp_38_reg_14781, all_end_reg_12647)
begin
ap_sig_bdd_2979 <= ((tmp_38_reg_14781 = ap_const_lv4_E) and not((ap_const_lv1_0 = all_end_reg_12647)));
end process;
-- ap_sig_bdd_2981 assign process. --
ap_sig_bdd_2981_assign_proc : process(tmp_38_reg_14781, all_end_reg_12647)
begin
ap_sig_bdd_2981 <= (not((tmp_38_reg_14781 = ap_const_lv4_E)) and not((tmp_38_reg_14781 = ap_const_lv4_D)) and not((tmp_38_reg_14781 = ap_const_lv4_C)) and not((tmp_38_reg_14781 = ap_const_lv4_B)) and not((tmp_38_reg_14781 = ap_const_lv4_A)) and not((tmp_38_reg_14781 = ap_const_lv4_9)) and not((tmp_38_reg_14781 = ap_const_lv4_8)) and not((tmp_38_reg_14781 = ap_const_lv4_7)) and not((tmp_38_reg_14781 = ap_const_lv4_6)) and not((tmp_38_reg_14781 = ap_const_lv4_5)) and not((tmp_38_reg_14781 = ap_const_lv4_4)) and not((tmp_38_reg_14781 = ap_const_lv4_3)) and not((tmp_38_reg_14781 = ap_const_lv4_2)) and not((tmp_38_reg_14781 = ap_const_lv4_1)) and not((tmp_38_reg_14781 = ap_const_lv4_0)) and not((ap_const_lv1_0 = all_end_reg_12647)));
end process;
-- ap_sig_bdd_2983 assign process. --
ap_sig_bdd_2983_assign_proc : process(tmp_38_reg_14781, all_end_reg_12647)
begin
ap_sig_bdd_2983 <= ((tmp_38_reg_14781 = ap_const_lv4_0) and not((ap_const_lv1_0 = all_end_reg_12647)));
end process;
-- ap_sig_bdd_327 assign process. --
ap_sig_bdd_327_assign_proc : process(ap_CS_fsm, tmp_9_fu_13539_p2)
begin
ap_sig_bdd_327 <= ((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)));
end process;
-- ap_sig_bdd_369 assign process. --
ap_sig_bdd_369_assign_proc : process(ap_CS_fsm, sample_rsp_empty_n)
begin
ap_sig_bdd_369 <= ((ap_ST_st35_fsm_34 = ap_CS_fsm) and not((sample_rsp_empty_n = ap_const_logic_0)));
end process;
-- ap_sig_bdd_395 assign process. --
ap_sig_bdd_395_assign_proc : process(ap_CS_fsm, exitcond_fu_13718_p2)
begin
ap_sig_bdd_395 <= ((ap_ST_st44_fsm_43 = ap_CS_fsm) and (ap_const_lv1_0 = exitcond_fu_13718_p2));
end process;
brmerge_demorgan_fu_13621_p2 <= (end_string_load_phi_phi_fu_11531_p32 and stop_on_first);
-- current_buckets_address0 assign process. --
current_buckets_address0_assign_proc : process(ap_CS_fsm, tmp_8_reg_14527, tmp_5_fu_13550_p1, current_buckets_addr_1_reg_14640, grp_nfa_get_initials_1_fu_12896_initials_buckets_address0)
begin
if ((ap_ST_st23_fsm_22 = ap_CS_fsm)) then
current_buckets_address0 <= current_buckets_addr_1_reg_14640;
elsif ((ap_ST_st19_fsm_18 = ap_CS_fsm)) then
current_buckets_address0 <= tmp_5_fu_13550_p1(4 - 1 downto 0);
elsif ((ap_ST_st11_fsm_10 = ap_CS_fsm)) then
current_buckets_address0 <= tmp_8_reg_14527(4 - 1 downto 0);
elsif (((ap_ST_st6_fsm_5 = ap_CS_fsm) or (ap_ST_st3_fsm_2 = ap_CS_fsm) or (ap_ST_st4_fsm_3 = ap_CS_fsm) or (ap_ST_st5_fsm_4 = ap_CS_fsm))) then
current_buckets_address0 <= grp_nfa_get_initials_1_fu_12896_initials_buckets_address0;
else
current_buckets_address0 <= "XXXX";
end if;
end process;
-- current_buckets_ce0 assign process. --
current_buckets_ce0_assign_proc : process(ap_CS_fsm, grp_nfa_get_initials_1_fu_12896_initials_buckets_ce0)
begin
if (((ap_ST_st11_fsm_10 = ap_CS_fsm) or (ap_ST_st19_fsm_18 = ap_CS_fsm) or (ap_ST_st23_fsm_22 = ap_CS_fsm))) then
current_buckets_ce0 <= ap_const_logic_1;
elsif (((ap_ST_st6_fsm_5 = ap_CS_fsm) or (ap_ST_st3_fsm_2 = ap_CS_fsm) or (ap_ST_st4_fsm_3 = ap_CS_fsm) or (ap_ST_st5_fsm_4 = ap_CS_fsm))) then
current_buckets_ce0 <= grp_nfa_get_initials_1_fu_12896_initials_buckets_ce0;
else
current_buckets_ce0 <= ap_const_logic_0;
end if;
end process;
-- current_buckets_d0 assign process. --
current_buckets_d0_assign_proc : process(ap_CS_fsm, next_buckets_q0, grp_nfa_get_initials_1_fu_12896_initials_buckets_d0)
begin
if ((ap_ST_st23_fsm_22 = ap_CS_fsm)) then
current_buckets_d0 <= next_buckets_q0;
elsif (((ap_ST_st6_fsm_5 = ap_CS_fsm) or (ap_ST_st3_fsm_2 = ap_CS_fsm) or (ap_ST_st4_fsm_3 = ap_CS_fsm) or (ap_ST_st5_fsm_4 = ap_CS_fsm))) then
current_buckets_d0 <= grp_nfa_get_initials_1_fu_12896_initials_buckets_d0;
else
current_buckets_d0 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
-- current_buckets_we0 assign process. --
current_buckets_we0_assign_proc : process(ap_CS_fsm, grp_nfa_get_initials_1_fu_12896_initials_buckets_we0)
begin
if (((ap_ST_st23_fsm_22 = ap_CS_fsm))) then
current_buckets_we0 <= ap_const_logic_1;
elsif (((ap_ST_st6_fsm_5 = ap_CS_fsm) or (ap_ST_st3_fsm_2 = ap_CS_fsm) or (ap_ST_st4_fsm_3 = ap_CS_fsm) or (ap_ST_st5_fsm_4 = ap_CS_fsm))) then
current_buckets_we0 <= grp_nfa_get_initials_1_fu_12896_initials_buckets_we0;
else
current_buckets_we0 <= ap_const_logic_0;
end if;
end process;
-- end_0_phi_fu_5844_p32 assign process. --
end_0_phi_fu_5844_p32_assign_proc : process(j_15_end_load_reg_14439, j_15_end_1_load_reg_14444, j_15_end_2_load_reg_14449, j_15_end_3_load_reg_14454, j_15_end_4_load_reg_14459, j_15_end_5_load_reg_14464, j_15_end_6_load_reg_14469, j_15_end_7_load_reg_14474, j_15_end_8_load_reg_14479, j_15_end_9_load_reg_14484, j_15_end_10_load_reg_14489, j_15_end_11_load_reg_14494, j_15_end_12_load_reg_14499, j_15_end_13_load_reg_14504, j_15_end_14_load_reg_14509, j_15_end_15_load_reg_14514, tmp_37_fu_13557_p1, ap_sig_bdd_327)
begin
if (ap_sig_bdd_327) then
if ((tmp_37_fu_13557_p1 = ap_const_lv4_0)) then
end_0_phi_fu_5844_p32 <= j_15_end_load_reg_14439;
elsif ((tmp_37_fu_13557_p1 = ap_const_lv4_E)) then
end_0_phi_fu_5844_p32 <= j_15_end_14_load_reg_14509;
elsif ((tmp_37_fu_13557_p1 = ap_const_lv4_D)) then
end_0_phi_fu_5844_p32 <= j_15_end_13_load_reg_14504;
elsif ((tmp_37_fu_13557_p1 = ap_const_lv4_C)) then
end_0_phi_fu_5844_p32 <= j_15_end_12_load_reg_14499;
elsif ((tmp_37_fu_13557_p1 = ap_const_lv4_B)) then
end_0_phi_fu_5844_p32 <= j_15_end_11_load_reg_14494;
elsif ((tmp_37_fu_13557_p1 = ap_const_lv4_A)) then
end_0_phi_fu_5844_p32 <= j_15_end_10_load_reg_14489;
elsif ((tmp_37_fu_13557_p1 = ap_const_lv4_9)) then
end_0_phi_fu_5844_p32 <= j_15_end_9_load_reg_14484;
elsif ((tmp_37_fu_13557_p1 = ap_const_lv4_8)) then
end_0_phi_fu_5844_p32 <= j_15_end_8_load_reg_14479;
elsif ((tmp_37_fu_13557_p1 = ap_const_lv4_7)) then
end_0_phi_fu_5844_p32 <= j_15_end_7_load_reg_14474;
elsif ((tmp_37_fu_13557_p1 = ap_const_lv4_6)) then
end_0_phi_fu_5844_p32 <= j_15_end_6_load_reg_14469;
elsif ((tmp_37_fu_13557_p1 = ap_const_lv4_5)) then
end_0_phi_fu_5844_p32 <= j_15_end_5_load_reg_14464;
elsif ((tmp_37_fu_13557_p1 = ap_const_lv4_4)) then
end_0_phi_fu_5844_p32 <= j_15_end_4_load_reg_14459;
elsif ((tmp_37_fu_13557_p1 = ap_const_lv4_3)) then
end_0_phi_fu_5844_p32 <= j_15_end_3_load_reg_14454;
elsif ((tmp_37_fu_13557_p1 = ap_const_lv4_2)) then
end_0_phi_fu_5844_p32 <= j_15_end_2_load_reg_14449;
elsif ((tmp_37_fu_13557_p1 = ap_const_lv4_1)) then
end_0_phi_fu_5844_p32 <= j_15_end_1_load_reg_14444;
elsif ((ap_true = ap_true)) then
end_0_phi_fu_5844_p32 <= j_15_end_15_load_reg_14514;
else
end_0_phi_fu_5844_p32 <= "X";
end if;
else
end_0_phi_fu_5844_p32 <= "X";
end if;
end process;
-- end_load_3_phi_phi_fu_11584_p32 assign process. --
end_load_3_phi_phi_fu_11584_p32_assign_proc : process(ap_CS_fsm, end_15_3_reg_5879, end_14_3_reg_5935, end_13_3_reg_5991, end_12_3_reg_6047, end_11_3_reg_6103, end_10_3_reg_6159, end_9_3_reg_6215, end_8_3_reg_6271, end_7_3_reg_6327, end_6_3_reg_6383, end_5_3_reg_6439, end_4_3_reg_6495, end_3_3_reg_6551, end_2_3_reg_6607, end_1_3_reg_6663, end_0_3_reg_6719, ap_sig_bdd_2491, ap_sig_bdd_2495, ap_sig_bdd_2499, ap_sig_bdd_2503, ap_sig_bdd_2507, ap_sig_bdd_2511, ap_sig_bdd_2515, ap_sig_bdd_2519, ap_sig_bdd_2523, ap_sig_bdd_2527, ap_sig_bdd_2531, ap_sig_bdd_2535, ap_sig_bdd_2539, ap_sig_bdd_2543, ap_sig_bdd_2547, ap_sig_bdd_2551)
begin
if ((ap_ST_st32_fsm_31 = ap_CS_fsm)) then
if (ap_sig_bdd_2551) then
end_load_3_phi_phi_fu_11584_p32 <= end_0_3_reg_6719;
elsif (ap_sig_bdd_2547) then
end_load_3_phi_phi_fu_11584_p32 <= end_14_3_reg_5935;
elsif (ap_sig_bdd_2543) then
end_load_3_phi_phi_fu_11584_p32 <= end_13_3_reg_5991;
elsif (ap_sig_bdd_2539) then
end_load_3_phi_phi_fu_11584_p32 <= end_12_3_reg_6047;
elsif (ap_sig_bdd_2535) then
end_load_3_phi_phi_fu_11584_p32 <= end_11_3_reg_6103;
elsif (ap_sig_bdd_2531) then
end_load_3_phi_phi_fu_11584_p32 <= end_10_3_reg_6159;
elsif (ap_sig_bdd_2527) then
end_load_3_phi_phi_fu_11584_p32 <= end_9_3_reg_6215;
elsif (ap_sig_bdd_2523) then
end_load_3_phi_phi_fu_11584_p32 <= end_8_3_reg_6271;
elsif (ap_sig_bdd_2519) then
end_load_3_phi_phi_fu_11584_p32 <= end_7_3_reg_6327;
elsif (ap_sig_bdd_2515) then
end_load_3_phi_phi_fu_11584_p32 <= end_6_3_reg_6383;
elsif (ap_sig_bdd_2511) then
end_load_3_phi_phi_fu_11584_p32 <= end_5_3_reg_6439;
elsif (ap_sig_bdd_2507) then
end_load_3_phi_phi_fu_11584_p32 <= end_4_3_reg_6495;
elsif (ap_sig_bdd_2503) then
end_load_3_phi_phi_fu_11584_p32 <= end_3_3_reg_6551;
elsif (ap_sig_bdd_2499) then
end_load_3_phi_phi_fu_11584_p32 <= end_2_3_reg_6607;
elsif (ap_sig_bdd_2495) then
end_load_3_phi_phi_fu_11584_p32 <= end_1_3_reg_6663;
elsif (ap_sig_bdd_2491) then
end_load_3_phi_phi_fu_11584_p32 <= end_15_3_reg_5879;
else
end_load_3_phi_phi_fu_11584_p32 <= "X";
end if;
else
end_load_3_phi_phi_fu_11584_p32 <= "X";
end if;
end process;
end_load_phi_phi_fu_12756_p32 <= end_load_phi_reg_12753;
-- end_string_0_6_phi_fu_11474_p34 assign process. --
end_string_0_6_phi_fu_11474_p34_assign_proc : process(ap_CS_fsm, end_string_0_6_reg_11469, end_0_reg_5841, end_string_0_5_reg_7649)
begin
if (((ap_ST_st30_fsm_29 = ap_CS_fsm) and not((ap_const_lv1_0 = end_0_reg_5841)))) then
end_string_0_6_phi_fu_11474_p34 <= end_string_0_5_reg_7649;
else
end_string_0_6_phi_fu_11474_p34 <= end_string_0_6_reg_11469;
end if;
end process;
-- end_string_0_phi_fu_6831_p4 assign process. --
end_string_0_phi_fu_6831_p4_assign_proc : process(tmp_7_reg_14542, tmp_12_fu_13561_p2, ap_sig_bdd_1793)
begin
if (ap_sig_bdd_1793) then
if (not((ap_const_lv1_0 = tmp_7_reg_14542))) then
end_string_0_phi_fu_6831_p4 <= ap_const_lv1_1;
elsif ((ap_const_lv1_0 = tmp_7_reg_14542)) then
end_string_0_phi_fu_6831_p4 <= tmp_12_fu_13561_p2;
else
end_string_0_phi_fu_6831_p4 <= "X";
end if;
else
end_string_0_phi_fu_6831_p4 <= "X";
end if;
end process;
-- end_string_10_6_phi_fu_10884_p34 assign process. --
end_string_10_6_phi_fu_10884_p34_assign_proc : process(ap_CS_fsm, end_string_10_6_reg_10879, end_0_reg_5841, end_string_10_5_reg_7109)
begin
if (((ap_ST_st30_fsm_29 = ap_CS_fsm) and not((ap_const_lv1_0 = end_0_reg_5841)))) then
end_string_10_6_phi_fu_10884_p34 <= end_string_10_5_reg_7109;
else
end_string_10_6_phi_fu_10884_p34 <= end_string_10_6_reg_10879;
end if;
end process;
end_string_10_fu_192 <= ap_const_lv1_0;
-- end_string_11_6_phi_fu_10825_p34 assign process. --
end_string_11_6_phi_fu_10825_p34_assign_proc : process(ap_CS_fsm, end_string_11_6_reg_10820, end_0_reg_5841, end_string_11_5_reg_7055)
begin
if (((ap_ST_st30_fsm_29 = ap_CS_fsm) and not((ap_const_lv1_0 = end_0_reg_5841)))) then
end_string_11_6_phi_fu_10825_p34 <= end_string_11_5_reg_7055;
else
end_string_11_6_phi_fu_10825_p34 <= end_string_11_6_reg_10820;
end if;
end process;
end_string_11_fu_196 <= ap_const_lv1_0;
-- end_string_12_6_phi_fu_10766_p34 assign process. --
end_string_12_6_phi_fu_10766_p34_assign_proc : process(ap_CS_fsm, end_string_12_6_reg_10761, end_0_reg_5841, end_string_12_5_reg_7001)
begin
if (((ap_ST_st30_fsm_29 = ap_CS_fsm) and not((ap_const_lv1_0 = end_0_reg_5841)))) then
end_string_12_6_phi_fu_10766_p34 <= end_string_12_5_reg_7001;
else
end_string_12_6_phi_fu_10766_p34 <= end_string_12_6_reg_10761;
end if;
end process;
end_string_12_fu_200 <= ap_const_lv1_0;
-- end_string_13_6_phi_fu_10707_p34 assign process. --
end_string_13_6_phi_fu_10707_p34_assign_proc : process(ap_CS_fsm, end_string_13_6_reg_10702, end_0_reg_5841, end_string_13_5_reg_6947)
begin
if (((ap_ST_st30_fsm_29 = ap_CS_fsm) and not((ap_const_lv1_0 = end_0_reg_5841)))) then
end_string_13_6_phi_fu_10707_p34 <= end_string_13_5_reg_6947;
else
end_string_13_6_phi_fu_10707_p34 <= end_string_13_6_reg_10702;
end if;
end process;
end_string_13_fu_204 <= ap_const_lv1_0;
-- end_string_14_6_phi_fu_10648_p34 assign process. --
end_string_14_6_phi_fu_10648_p34_assign_proc : process(ap_CS_fsm, end_string_14_6_reg_10643, end_0_reg_5841, end_string_14_5_reg_6893)
begin
if (((ap_ST_st30_fsm_29 = ap_CS_fsm) and not((ap_const_lv1_0 = end_0_reg_5841)))) then
end_string_14_6_phi_fu_10648_p34 <= end_string_14_5_reg_6893;
else
end_string_14_6_phi_fu_10648_p34 <= end_string_14_6_reg_10643;
end if;
end process;
end_string_14_fu_208 <= ap_const_lv1_0;
-- end_string_15_6_phi_fu_10589_p34 assign process. --
end_string_15_6_phi_fu_10589_p34_assign_proc : process(ap_CS_fsm, end_string_15_6_reg_10584, end_0_reg_5841, end_string_15_5_reg_6839)
begin
if (((ap_ST_st30_fsm_29 = ap_CS_fsm) and not((ap_const_lv1_0 = end_0_reg_5841)))) then
end_string_15_6_phi_fu_10589_p34 <= end_string_15_5_reg_6839;
else
end_string_15_6_phi_fu_10589_p34 <= end_string_15_6_reg_10584;
end if;
end process;
-- end_string_1_6_phi_fu_11415_p34 assign process. --
end_string_1_6_phi_fu_11415_p34_assign_proc : process(ap_CS_fsm, end_string_1_6_reg_11410, end_0_reg_5841, end_string_1_5_reg_7595)
begin
if (((ap_ST_st30_fsm_29 = ap_CS_fsm) and not((ap_const_lv1_0 = end_0_reg_5841)))) then
end_string_1_6_phi_fu_11415_p34 <= end_string_1_5_reg_7595;
else
end_string_1_6_phi_fu_11415_p34 <= end_string_1_6_reg_11410;
end if;
end process;
end_string_1_fu_156 <= ap_const_lv1_0;
-- end_string_2_6_phi_fu_11356_p34 assign process. --
end_string_2_6_phi_fu_11356_p34_assign_proc : process(ap_CS_fsm, end_string_2_6_reg_11351, end_0_reg_5841, end_string_2_5_reg_7541)
begin
if (((ap_ST_st30_fsm_29 = ap_CS_fsm) and not((ap_const_lv1_0 = end_0_reg_5841)))) then
end_string_2_6_phi_fu_11356_p34 <= end_string_2_5_reg_7541;
else
end_string_2_6_phi_fu_11356_p34 <= end_string_2_6_reg_11351;
end if;
end process;
end_string_2_fu_160 <= ap_const_lv1_0;
-- end_string_3_6_phi_fu_11297_p34 assign process. --
end_string_3_6_phi_fu_11297_p34_assign_proc : process(ap_CS_fsm, end_string_3_6_reg_11292, end_0_reg_5841, end_string_3_5_reg_7487)
begin
if (((ap_ST_st30_fsm_29 = ap_CS_fsm) and not((ap_const_lv1_0 = end_0_reg_5841)))) then
end_string_3_6_phi_fu_11297_p34 <= end_string_3_5_reg_7487;
else
end_string_3_6_phi_fu_11297_p34 <= end_string_3_6_reg_11292;
end if;
end process;
end_string_3_fu_164 <= ap_const_lv1_0;
-- end_string_4_6_phi_fu_11238_p34 assign process. --
end_string_4_6_phi_fu_11238_p34_assign_proc : process(ap_CS_fsm, end_string_4_6_reg_11233, end_0_reg_5841, end_string_4_5_reg_7433)
begin
if (((ap_ST_st30_fsm_29 = ap_CS_fsm) and not((ap_const_lv1_0 = end_0_reg_5841)))) then
end_string_4_6_phi_fu_11238_p34 <= end_string_4_5_reg_7433;
else
end_string_4_6_phi_fu_11238_p34 <= end_string_4_6_reg_11233;
end if;
end process;
end_string_4_fu_168 <= ap_const_lv1_0;
-- end_string_5_6_phi_fu_11179_p34 assign process. --
end_string_5_6_phi_fu_11179_p34_assign_proc : process(ap_CS_fsm, end_string_5_6_reg_11174, end_0_reg_5841, end_string_5_5_reg_7379)
begin
if (((ap_ST_st30_fsm_29 = ap_CS_fsm) and not((ap_const_lv1_0 = end_0_reg_5841)))) then
end_string_5_6_phi_fu_11179_p34 <= end_string_5_5_reg_7379;
else
end_string_5_6_phi_fu_11179_p34 <= end_string_5_6_reg_11174;
end if;
end process;
end_string_5_fu_172 <= ap_const_lv1_0;
-- end_string_6_6_phi_fu_11120_p34 assign process. --
end_string_6_6_phi_fu_11120_p34_assign_proc : process(ap_CS_fsm, end_string_6_6_reg_11115, end_0_reg_5841, end_string_6_5_reg_7325)
begin
if (((ap_ST_st30_fsm_29 = ap_CS_fsm) and not((ap_const_lv1_0 = end_0_reg_5841)))) then
end_string_6_6_phi_fu_11120_p34 <= end_string_6_5_reg_7325;
else
end_string_6_6_phi_fu_11120_p34 <= end_string_6_6_reg_11115;
end if;
end process;
end_string_6_fu_176 <= ap_const_lv1_0;
-- end_string_7_6_phi_fu_11061_p34 assign process. --
end_string_7_6_phi_fu_11061_p34_assign_proc : process(ap_CS_fsm, end_string_7_6_reg_11056, end_0_reg_5841, end_string_7_5_reg_7271)
begin
if (((ap_ST_st30_fsm_29 = ap_CS_fsm) and not((ap_const_lv1_0 = end_0_reg_5841)))) then
end_string_7_6_phi_fu_11061_p34 <= end_string_7_5_reg_7271;
else
end_string_7_6_phi_fu_11061_p34 <= end_string_7_6_reg_11056;
end if;
end process;
end_string_7_fu_180 <= ap_const_lv1_0;
-- end_string_8_6_phi_fu_11002_p34 assign process. --
end_string_8_6_phi_fu_11002_p34_assign_proc : process(ap_CS_fsm, end_string_8_6_reg_10997, end_0_reg_5841, end_string_8_5_reg_7217)
begin
if (((ap_ST_st30_fsm_29 = ap_CS_fsm) and not((ap_const_lv1_0 = end_0_reg_5841)))) then
end_string_8_6_phi_fu_11002_p34 <= end_string_8_5_reg_7217;
else
end_string_8_6_phi_fu_11002_p34 <= end_string_8_6_reg_10997;
end if;
end process;
end_string_8_fu_184 <= ap_const_lv1_0;
-- end_string_9_6_phi_fu_10943_p34 assign process. --
end_string_9_6_phi_fu_10943_p34_assign_proc : process(ap_CS_fsm, end_string_9_6_reg_10938, end_0_reg_5841, end_string_9_5_reg_7163)
begin
if (((ap_ST_st30_fsm_29 = ap_CS_fsm) and not((ap_const_lv1_0 = end_0_reg_5841)))) then
end_string_9_6_phi_fu_10943_p34 <= end_string_9_5_reg_7163;
else
end_string_9_6_phi_fu_10943_p34 <= end_string_9_6_reg_10938;
end if;
end process;
end_string_9_fu_188 <= ap_const_lv1_0;
end_string_fu_152 <= ap_const_lv1_0;
-- end_string_load_phi_phi_fu_11531_p32 assign process. --
end_string_load_phi_phi_fu_11531_p32_assign_proc : process(ap_CS_fsm, tmp_37_reg_14631, end_string_15_6_phi_fu_10589_p34, end_string_14_6_phi_fu_10648_p34, end_string_13_6_phi_fu_10707_p34, end_string_12_6_phi_fu_10766_p34, end_string_11_6_phi_fu_10825_p34, end_string_10_6_phi_fu_10884_p34, end_string_9_6_phi_fu_10943_p34, end_string_8_6_phi_fu_11002_p34, end_string_7_6_phi_fu_11061_p34, end_string_6_6_phi_fu_11120_p34, end_string_5_6_phi_fu_11179_p34, end_string_4_6_phi_fu_11238_p34, end_string_3_6_phi_fu_11297_p34, end_string_2_6_phi_fu_11356_p34, end_string_1_6_phi_fu_11415_p34, end_string_0_6_phi_fu_11474_p34)
begin
if ((ap_ST_st30_fsm_29 = ap_CS_fsm)) then
if ((tmp_37_reg_14631 = ap_const_lv4_0)) then
end_string_load_phi_phi_fu_11531_p32 <= end_string_0_6_phi_fu_11474_p34;
elsif ((tmp_37_reg_14631 = ap_const_lv4_E)) then
end_string_load_phi_phi_fu_11531_p32 <= end_string_14_6_phi_fu_10648_p34;
elsif ((tmp_37_reg_14631 = ap_const_lv4_D)) then
end_string_load_phi_phi_fu_11531_p32 <= end_string_13_6_phi_fu_10707_p34;
elsif ((tmp_37_reg_14631 = ap_const_lv4_C)) then
end_string_load_phi_phi_fu_11531_p32 <= end_string_12_6_phi_fu_10766_p34;
elsif ((tmp_37_reg_14631 = ap_const_lv4_B)) then
end_string_load_phi_phi_fu_11531_p32 <= end_string_11_6_phi_fu_10825_p34;
elsif ((tmp_37_reg_14631 = ap_const_lv4_A)) then
end_string_load_phi_phi_fu_11531_p32 <= end_string_10_6_phi_fu_10884_p34;
elsif ((tmp_37_reg_14631 = ap_const_lv4_9)) then
end_string_load_phi_phi_fu_11531_p32 <= end_string_9_6_phi_fu_10943_p34;
elsif ((tmp_37_reg_14631 = ap_const_lv4_8)) then
end_string_load_phi_phi_fu_11531_p32 <= end_string_8_6_phi_fu_11002_p34;
elsif ((tmp_37_reg_14631 = ap_const_lv4_7)) then
end_string_load_phi_phi_fu_11531_p32 <= end_string_7_6_phi_fu_11061_p34;
elsif ((tmp_37_reg_14631 = ap_const_lv4_6)) then
end_string_load_phi_phi_fu_11531_p32 <= end_string_6_6_phi_fu_11120_p34;
elsif ((tmp_37_reg_14631 = ap_const_lv4_5)) then
end_string_load_phi_phi_fu_11531_p32 <= end_string_5_6_phi_fu_11179_p34;
elsif ((tmp_37_reg_14631 = ap_const_lv4_4)) then
end_string_load_phi_phi_fu_11531_p32 <= end_string_4_6_phi_fu_11238_p34;
elsif ((tmp_37_reg_14631 = ap_const_lv4_3)) then
end_string_load_phi_phi_fu_11531_p32 <= end_string_3_6_phi_fu_11297_p34;
elsif ((tmp_37_reg_14631 = ap_const_lv4_2)) then
end_string_load_phi_phi_fu_11531_p32 <= end_string_2_6_phi_fu_11356_p34;
elsif ((tmp_37_reg_14631 = ap_const_lv4_1)) then
end_string_load_phi_phi_fu_11531_p32 <= end_string_1_6_phi_fu_11415_p34;
elsif ((ap_true = ap_true)) then
end_string_load_phi_phi_fu_11531_p32 <= end_string_15_6_phi_fu_10589_p34;
else
end_string_load_phi_phi_fu_11531_p32 <= "X";
end if;
else
end_string_load_phi_phi_fu_11531_p32 <= "X";
end if;
end process;
end_string_s_fu_212 <= ap_const_lv1_0;
exitcond2_fu_13247_p2 <= "1" when (k_1_reg_1913 = units) else "0";
exitcond3_fu_12991_p2 <= "1" when (k_reg_612 = units) else "0";
exitcond_fu_13718_p2 <= "1" when (k_3_reg_12604 = units) else "0";
grp_fu_12923_p4 <= next_buckets_q0(63 downto 32);
grp_fu_12933_p4 <= tmp_buckets_q0(63 downto 32);
grp_nfa_get_finals_1_fu_12905_ap_ce <= ap_const_logic_1;
grp_nfa_get_finals_1_fu_12905_ap_start <= grp_nfa_get_finals_1_fu_12905_ap_start_ap_start_reg;
grp_nfa_get_finals_1_fu_12905_nfa_finals_buckets_datain <= nfa_finals_buckets_datain;
grp_nfa_get_finals_1_fu_12905_nfa_finals_buckets_req_full_n <= nfa_finals_buckets_req_full_n;
grp_nfa_get_finals_1_fu_12905_nfa_finals_buckets_rsp_empty_n <= nfa_finals_buckets_rsp_empty_n;
grp_nfa_get_finals_1_fu_12905_tmp_28 <= k_2_reg_5827;
grp_nfa_get_initials_1_fu_12896_ap_ce <= ap_const_logic_1;
grp_nfa_get_initials_1_fu_12896_ap_start <= grp_nfa_get_initials_1_fu_12896_ap_start_ap_start_reg;
grp_nfa_get_initials_1_fu_12896_nfa_initials_buckets_datain <= nfa_initials_buckets_datain;
grp_nfa_get_initials_1_fu_12896_nfa_initials_buckets_req_full_n <= nfa_initials_buckets_req_full_n;
grp_nfa_get_initials_1_fu_12896_nfa_initials_buckets_rsp_empty_n <= nfa_initials_buckets_rsp_empty_n;
grp_nfa_get_initials_1_fu_12896_tmp_s <= k_reg_612;
i_1_fu_13091_p2 <= std_logic_vector(unsigned(i_reg_1552) + unsigned(ap_const_lv16_FFFF));
j_0_bucket_index_cast_fu_13311_p1 <= std_logic_vector(resize(unsigned(j_0_bucket_index_reg_3706),8));
r_bit_p_bsf32_hw_fu_12914_ap_return_temp <= signed(r_bit_p_bsf32_hw_fu_12914_ap_return);
j_15_bit_16_fu_13302_p1 <= std_logic_vector(resize(r_bit_p_bsf32_hw_fu_12914_ap_return_temp,8));
k_4_fu_12996_p2 <= std_logic_vector(unsigned(k_reg_612) + unsigned(ap_const_lv5_1));
k_5_fu_13252_p2 <= std_logic_vector(unsigned(k_1_reg_1913) + unsigned(ap_const_lv5_1));
k_6_fu_13723_p2 <= std_logic_vector(unsigned(k_3_reg_12604) + unsigned(ap_const_lv5_1));
k_7_fu_13544_p2 <= std_logic_vector(unsigned(k_2_reg_5827) + unsigned(ap_const_lv5_1));
-- next_buckets_address0 assign process. --
next_buckets_address0_assign_proc : process(ap_CS_fsm, tmp_8_reg_14527, tmp_5_fu_13550_p1, tmp_5_reg_14621, next_buckets_addr_3_reg_14635, next_buckets_addr_4_reg_14670, tmp_10_reg_14775, next_buckets_addr_2_reg_14790, tmp_s_fu_13002_p1)
begin
if ((ap_ST_st46_fsm_45 = ap_CS_fsm)) then
next_buckets_address0 <= next_buckets_addr_2_reg_14790;
elsif ((ap_ST_st29_fsm_28 = ap_CS_fsm)) then
next_buckets_address0 <= next_buckets_addr_4_reg_14670;
elsif ((ap_ST_st23_fsm_22 = ap_CS_fsm)) then
next_buckets_address0 <= next_buckets_addr_3_reg_14635;
elsif ((ap_ST_st11_fsm_10 = ap_CS_fsm)) then
next_buckets_address0 <= tmp_8_reg_14527(4 - 1 downto 0);
elsif ((ap_ST_st2_fsm_1 = ap_CS_fsm)) then
next_buckets_address0 <= tmp_s_fu_13002_p1(4 - 1 downto 0);
elsif ((ap_ST_st45_fsm_44 = ap_CS_fsm)) then
next_buckets_address0 <= tmp_10_reg_14775(4 - 1 downto 0);
elsif ((ap_ST_st28_fsm_27 = ap_CS_fsm)) then
next_buckets_address0 <= tmp_5_reg_14621(4 - 1 downto 0);
elsif ((ap_ST_st19_fsm_18 = ap_CS_fsm)) then
next_buckets_address0 <= tmp_5_fu_13550_p1(4 - 1 downto 0);
else
next_buckets_address0 <= "XXXX";
end if;
end process;
-- next_buckets_ce0 assign process. --
next_buckets_ce0_assign_proc : process(ap_CS_fsm)
begin
if (((ap_ST_st2_fsm_1 = ap_CS_fsm) or (ap_ST_st11_fsm_10 = ap_CS_fsm) or (ap_ST_st19_fsm_18 = ap_CS_fsm) or (ap_ST_st28_fsm_27 = ap_CS_fsm) or (ap_ST_st29_fsm_28 = ap_CS_fsm) or (ap_ST_st45_fsm_44 = ap_CS_fsm) or (ap_ST_st46_fsm_45 = ap_CS_fsm) or (ap_ST_st23_fsm_22 = ap_CS_fsm))) then
next_buckets_ce0 <= ap_const_logic_1;
else
next_buckets_ce0 <= ap_const_logic_0;
end if;
end process;
-- next_buckets_d0 assign process. --
next_buckets_d0_assign_proc : process(ap_CS_fsm, current_buckets_q0, tmp_49_i_fu_13600_p3, tmp_68_i_fu_13757_p3)
begin
if ((ap_ST_st46_fsm_45 = ap_CS_fsm)) then
next_buckets_d0 <= tmp_68_i_fu_13757_p3;
elsif ((ap_ST_st29_fsm_28 = ap_CS_fsm)) then
next_buckets_d0 <= tmp_49_i_fu_13600_p3;
elsif ((ap_ST_st23_fsm_22 = ap_CS_fsm)) then
next_buckets_d0 <= current_buckets_q0;
elsif (((ap_ST_st2_fsm_1 = ap_CS_fsm) or (ap_ST_st11_fsm_10 = ap_CS_fsm))) then
next_buckets_d0 <= ap_const_lv64_0;
else
next_buckets_d0 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
-- next_buckets_we0 assign process. --
next_buckets_we0_assign_proc : process(ap_CS_fsm, exitcond3_fu_12991_p2, end_load_phi_reg_12753)
begin
if (((ap_ST_st11_fsm_10 = ap_CS_fsm) or (ap_ST_st29_fsm_28 = ap_CS_fsm) or ((ap_ST_st2_fsm_1 = ap_CS_fsm) and (ap_const_lv1_0 = exitcond3_fu_12991_p2)) or (ap_ST_st23_fsm_22 = ap_CS_fsm) or ((ap_ST_st46_fsm_45 = ap_CS_fsm) and (ap_const_lv1_0 = end_load_phi_reg_12753)))) then
next_buckets_we0 <= ap_const_logic_1;
else
next_buckets_we0 <= ap_const_logic_0;
end if;
end process;
nfa_finals_buckets_address <= grp_nfa_get_finals_1_fu_12905_nfa_finals_buckets_address;
nfa_finals_buckets_dataout <= grp_nfa_get_finals_1_fu_12905_nfa_finals_buckets_dataout;
nfa_finals_buckets_req_din <= grp_nfa_get_finals_1_fu_12905_nfa_finals_buckets_req_din;
nfa_finals_buckets_req_write <= grp_nfa_get_finals_1_fu_12905_nfa_finals_buckets_req_write;
nfa_finals_buckets_rsp_read <= grp_nfa_get_finals_1_fu_12905_nfa_finals_buckets_rsp_read;
nfa_finals_buckets_size <= grp_nfa_get_finals_1_fu_12905_nfa_finals_buckets_size;
-- nfa_forward_buckets_address assign process. --
nfa_forward_buckets_address_assign_proc : process(ap_CS_fsm, tmp_82_i_cast_fu_13682_p1, tmp_83_i_cast_fu_13700_p1)
begin
if ((ap_ST_st40_fsm_39 = ap_CS_fsm)) then
nfa_forward_buckets_address <= tmp_83_i_cast_fu_13700_p1(32 - 1 downto 0);
elsif ((ap_ST_st37_fsm_36 = ap_CS_fsm)) then
nfa_forward_buckets_address <= tmp_82_i_cast_fu_13682_p1(32 - 1 downto 0);
else
nfa_forward_buckets_address <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
nfa_forward_buckets_dataout <= ap_const_lv32_0;
nfa_forward_buckets_req_din <= ap_const_logic_0;
-- nfa_forward_buckets_req_write assign process. --
nfa_forward_buckets_req_write_assign_proc : process(ap_CS_fsm)
begin
if (((ap_ST_st37_fsm_36 = ap_CS_fsm) or (ap_ST_st40_fsm_39 = ap_CS_fsm))) then
nfa_forward_buckets_req_write <= ap_const_logic_1;
else
nfa_forward_buckets_req_write <= ap_const_logic_0;
end if;
end process;
-- nfa_forward_buckets_rsp_read assign process. --
nfa_forward_buckets_rsp_read_assign_proc : process(ap_CS_fsm, nfa_forward_buckets_rsp_empty_n)
begin
if ((((ap_ST_st39_fsm_38 = ap_CS_fsm) and not((nfa_forward_buckets_rsp_empty_n = ap_const_logic_0))) or (not((nfa_forward_buckets_rsp_empty_n = ap_const_logic_0)) and (ap_ST_st42_fsm_41 = ap_CS_fsm)))) then
nfa_forward_buckets_rsp_read <= ap_const_logic_1;
else
nfa_forward_buckets_rsp_read <= ap_const_logic_0;
end if;
end process;
nfa_forward_buckets_size <= ap_const_lv32_1;
nfa_initials_buckets_address <= grp_nfa_get_initials_1_fu_12896_nfa_initials_buckets_address;
nfa_initials_buckets_dataout <= grp_nfa_get_initials_1_fu_12896_nfa_initials_buckets_dataout;
nfa_initials_buckets_req_din <= grp_nfa_get_initials_1_fu_12896_nfa_initials_buckets_req_din;
nfa_initials_buckets_req_write <= grp_nfa_get_initials_1_fu_12896_nfa_initials_buckets_req_write;
nfa_initials_buckets_rsp_read <= grp_nfa_get_initials_1_fu_12896_nfa_initials_buckets_rsp_read;
nfa_initials_buckets_size <= grp_nfa_get_initials_1_fu_12896_nfa_initials_buckets_size;
not_s_fu_13615_p2 <= "0" when (tmp_1_fu_13609_p2 = ap_const_lv32_0) else "1";
r_1_0_i_lcssa3_cast_fu_13298_p1 <= std_logic_vector(resize(unsigned(r_1_0_i_lcssa3_reg_3693),2));
r_bit_p_bsf32_hw_fu_12914_bus_r <= bus_assign_reg_3684;
result_addr_gep_fu_575_p3 <= tmp_5_reg_14621(4 - 1 downto 0);
-- result_address0 assign process. --
result_address0_assign_proc : process(ap_CS_fsm, tmp_5_fu_13550_p1, tmp_5_reg_14621, result_addr_gep_fu_575_p3)
begin
if ((ap_ST_st30_fsm_29 = ap_CS_fsm)) then
result_address0 <= result_addr_gep_fu_575_p3;
elsif ((ap_ST_st19_fsm_18 = ap_CS_fsm)) then
result_address0 <= tmp_5_fu_13550_p1(4 - 1 downto 0);
elsif ((ap_ST_st31_fsm_30 = ap_CS_fsm)) then
result_address0 <= tmp_5_reg_14621(4 - 1 downto 0);
else
result_address0 <= "XXXX";
end if;
end process;
-- result_ce0 assign process. --
result_ce0_assign_proc : process(ap_CS_fsm)
begin
if (((ap_ST_st19_fsm_18 = ap_CS_fsm) or (ap_ST_st30_fsm_29 = ap_CS_fsm) or (ap_ST_st31_fsm_30 = ap_CS_fsm))) then
result_ce0 <= ap_const_logic_1;
else
result_ce0 <= ap_const_logic_0;
end if;
end process;
-- result_d0 assign process. --
result_d0_assign_proc : process(ap_CS_fsm, not_s_reg_14675)
begin
if ((ap_ST_st30_fsm_29 = ap_CS_fsm)) then
result_d0 <= not_s_reg_14675;
elsif ((ap_ST_st19_fsm_18 = ap_CS_fsm)) then
result_d0 <= ap_const_lv1_0;
else
result_d0 <= "X";
end if;
end process;
-- result_we0 assign process. --
result_we0_assign_proc : process(ap_CS_fsm, tmp_9_fu_13539_p2, end_0_phi_fu_5844_p32, end_string_0_phi_fu_6831_p4, end_0_reg_5841, end_string_0_reg_6828, any_state_load_1_phi_phi_fu_7706_p32, any_state_load_1_phi_reg_7703)
begin
if ((((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((ap_const_lv1_0 = tmp_9_fu_13539_p2)) and not((ap_const_lv1_0 = end_0_phi_fu_5844_p32)) and not((ap_const_lv1_0 = end_string_0_phi_fu_6831_p4)) and (ap_const_lv1_0 = any_state_load_1_phi_phi_fu_7706_p32)) or ((ap_ST_st30_fsm_29 = ap_CS_fsm) and not((ap_const_lv1_0 = end_0_reg_5841)) and not((ap_const_lv1_0 = end_string_0_reg_6828)) and not((ap_const_lv1_0 = any_state_load_1_phi_reg_7703))))) then
result_we0 <= ap_const_logic_1;
else
result_we0 <= ap_const_logic_0;
end if;
end process;
sample_address <= tmp_15_fu_13637_p1(32 - 1 downto 0);
sample_dataout <= ap_const_lv8_0;
sample_req_din <= ap_const_logic_0;
-- sample_req_write assign process. --
sample_req_write_assign_proc : process(ap_CS_fsm)
begin
if ((ap_ST_st33_fsm_32 = ap_CS_fsm)) then
sample_req_write <= ap_const_logic_1;
else
sample_req_write <= ap_const_logic_0;
end if;
end process;
-- sample_rsp_read assign process. --
sample_rsp_read_assign_proc : process(ap_CS_fsm, sample_rsp_empty_n)
begin
if (((ap_ST_st35_fsm_34 = ap_CS_fsm) and not((sample_rsp_empty_n = ap_const_logic_0)))) then
sample_rsp_read <= ap_const_logic_1;
else
sample_rsp_read <= ap_const_logic_0;
end if;
end process;
sample_size <= ap_const_lv32_1;
start_indices_address0 <= tmp_8_fu_13258_p1(4 - 1 downto 0);
-- start_indices_ce0 assign process. --
start_indices_ce0_assign_proc : process(ap_CS_fsm)
begin
if ((ap_ST_st8_fsm_7 = ap_CS_fsm)) then
start_indices_ce0 <= ap_const_logic_1;
else
start_indices_ce0 <= ap_const_logic_0;
end if;
end process;
state_0_fu_13574_p2 <= std_logic_vector(unsigned(tmp_42_fu_13568_p2) + unsigned(j_bit_addr12_phi_reg_8637));
sym_offset_0_1_25_fu_13631_p2 <= std_logic_vector(unsigned(offset_reg_11634) + unsigned(ap_const_lv32_1));
tmp1_fu_13626_p2 <= (result_q0 xor accept);
tmp_10_fu_13729_p1 <= std_logic_vector(resize(unsigned(k_3_reg_12604),64));
tmp_11_fu_13276_p2 <= "1" when (tmp_39_fu_13272_p1 = ap_const_lv32_0) else "0";
tmp_12_fu_13561_p2 <= (any_state_load_phi_phi_fu_6778_p32 xor ap_const_lv1_1);
tmp_13_fu_13282_p4 <= current_buckets_q0(63 downto 32);
tmp_15_fu_13637_p1 <= std_logic_vector(resize(unsigned(offset_reg_11634),64));
tmp_1_fu_13609_p2 <= (tmp_8_i_fu_13588_p2 or tmp_8_1_i_fu_13594_p2);
tmp_27_1_fu_13292_p2 <= "1" when (tmp_13_fu_13282_p4 = ap_const_lv32_0) else "0";
tmp_35_fu_13007_p1 <= k_reg_612(4 - 1 downto 0);
tmp_36_fu_13263_p1 <= k_1_reg_1913(4 - 1 downto 0);
tmp_37_fu_13557_p1 <= k_2_reg_5827(4 - 1 downto 0);
tmp_38_fu_13733_p1 <= k_3_reg_12604(4 - 1 downto 0);
tmp_39_fu_13272_p1 <= current_buckets_q0(32 - 1 downto 0);
tmp_40_fu_13737_p1 <= tmp_buckets_q0(32 - 1 downto 0);
tmp_41_fu_13741_p1 <= next_buckets_q0(32 - 1 downto 0);
tmp_42_fu_13568_p2 <= std_logic_vector(shift_left(unsigned(j_bucket_index_addr13_phi_reg_8675),to_integer(unsigned('0' & ap_const_lv8_5(8-1 downto 0)))));
tmp_43_fu_13580_p1 <= tmp_buckets_q0(32 - 1 downto 0);
tmp_44_fu_13584_p1 <= next_buckets_q0(32 - 1 downto 0);
tmp_45_fu_13648_p1 <= state_assign_in_reg_12551(6 - 1 downto 0);
tmp_49_i_fu_13600_p3 <= (tmp_8_1_i_fu_13594_p2 & tmp_8_i_fu_13588_p2);
tmp_57_i_fu_13745_p2 <= (tmp_41_fu_13741_p1 or tmp_40_fu_13737_p1);
tmp_5_fu_13550_p1 <= std_logic_vector(resize(unsigned(k_2_reg_5827),64));
tmp_68_i_fu_13757_p3 <= (tmp_6_1_i_fu_13751_p2 & tmp_57_i_fu_13745_p2);
tmp_6_1_i_fu_13751_p2 <= (grp_fu_12923_p4 or grp_fu_12933_p4);
tmp_6_fu_13097_p2 <= "1" when (i_reg_1552 = ap_const_lv16_0) else "0";
tmp_6_i_fu_13660_p0 <= tmp_6_i_fu_13660_p00(8 - 1 downto 0);
tmp_6_i_fu_13660_p00 <= std_logic_vector(resize(unsigned(nfa_symbols),14));
tmp_6_i_fu_13660_p1 <= tmp_6_i_fu_13660_p10(6 - 1 downto 0);
tmp_6_i_fu_13660_p10 <= std_logic_vector(resize(unsigned(tmp_45_fu_13648_p1),14));
tmp_6_i_fu_13660_p2 <= std_logic_vector(resize(unsigned(tmp_6_i_fu_13660_p0) * unsigned(tmp_6_i_fu_13660_p1), 14));
tmp_7_fu_13267_p2 <= "1" when (i_1_reg_14270 = ap_const_lv16_0) else "0";
tmp_7_i_cast_fu_13666_p1 <= std_logic_vector(resize(unsigned(sample_addr_read_reg_14718),14));
tmp_82_i_cast_fu_13682_p1 <= std_logic_vector(resize(unsigned(tmp_82_i_fu_13675_p3),64));
tmp_82_i_fu_13675_p3 <= (tmp_8_i1_reg_14723 & ap_const_lv1_0);
tmp_83_i_cast_fu_13700_p1 <= std_logic_vector(resize(unsigned(tmp_83_i_fu_13693_p3),64));
tmp_83_i_fu_13693_p3 <= (tmp_8_i1_reg_14723 & ap_const_lv1_1);
tmp_84_i_fu_13711_p3 <= (nfa_forward_buckets_addr_1_read_reg_14746 & nfa_forward_buckets_addr_read_reg_14735);
tmp_8_1_i_fu_13594_p2 <= (grp_fu_12923_p4 and grp_fu_12933_p4);
tmp_8_fu_13258_p1 <= std_logic_vector(resize(unsigned(k_1_reg_1913),64));
tmp_8_i1_fu_13669_p2 <= std_logic_vector(unsigned(tmp_6_i_fu_13660_p2) + unsigned(tmp_7_i_cast_fu_13666_p1));
tmp_8_i_fu_13588_p2 <= (tmp_44_fu_13584_p1 and tmp_43_fu_13580_p1);
tmp_9_fu_13539_p2 <= "1" when (unsigned(k_2_reg_5827) < unsigned(units)) else "0";
tmp_buckets_addr_1_gep_fu_547_p3 <= tmp_5_reg_14621(4 - 1 downto 0);
tmp_buckets_addr_3_gep_fu_591_p3 <= tmp_5_reg_14621(4 - 1 downto 0);
-- tmp_buckets_address0 assign process. --
tmp_buckets_address0_assign_proc : process(ap_CS_fsm, tmp_5_reg_14621, tmp_10_reg_14775, grp_nfa_get_finals_1_fu_12905_finals_buckets_address0, tmp_buckets_addr_1_gep_fu_547_p3, tmp_buckets_addr_3_gep_fu_591_p3)
begin
if ((ap_ST_st43_fsm_42 = ap_CS_fsm)) then
tmp_buckets_address0 <= tmp_buckets_addr_3_gep_fu_591_p3;
elsif ((ap_ST_st23_fsm_22 = ap_CS_fsm)) then
tmp_buckets_address0 <= tmp_buckets_addr_1_gep_fu_547_p3;
elsif ((ap_ST_st45_fsm_44 = ap_CS_fsm)) then
tmp_buckets_address0 <= tmp_10_reg_14775(4 - 1 downto 0);
elsif ((ap_ST_st28_fsm_27 = ap_CS_fsm)) then
tmp_buckets_address0 <= tmp_5_reg_14621(4 - 1 downto 0);
elsif (((ap_ST_st24_fsm_23 = ap_CS_fsm) or (ap_ST_st25_fsm_24 = ap_CS_fsm) or (ap_ST_st26_fsm_25 = ap_CS_fsm) or (ap_ST_st27_fsm_26 = ap_CS_fsm))) then
tmp_buckets_address0 <= grp_nfa_get_finals_1_fu_12905_finals_buckets_address0;
else
tmp_buckets_address0 <= "XXXX";
end if;
end process;
-- tmp_buckets_ce0 assign process. --
tmp_buckets_ce0_assign_proc : process(ap_CS_fsm, grp_nfa_get_finals_1_fu_12905_finals_buckets_ce0)
begin
if (((ap_ST_st28_fsm_27 = ap_CS_fsm) or (ap_ST_st45_fsm_44 = ap_CS_fsm) or (ap_ST_st43_fsm_42 = ap_CS_fsm) or (ap_ST_st23_fsm_22 = ap_CS_fsm))) then
tmp_buckets_ce0 <= ap_const_logic_1;
elsif (((ap_ST_st24_fsm_23 = ap_CS_fsm) or (ap_ST_st25_fsm_24 = ap_CS_fsm) or (ap_ST_st26_fsm_25 = ap_CS_fsm) or (ap_ST_st27_fsm_26 = ap_CS_fsm))) then
tmp_buckets_ce0 <= grp_nfa_get_finals_1_fu_12905_finals_buckets_ce0;
else
tmp_buckets_ce0 <= ap_const_logic_0;
end if;
end process;
-- tmp_buckets_d0 assign process. --
tmp_buckets_d0_assign_proc : process(ap_CS_fsm, next_buckets_q0, grp_nfa_get_finals_1_fu_12905_finals_buckets_d0, tmp_84_i_fu_13711_p3)
begin
if ((ap_ST_st43_fsm_42 = ap_CS_fsm)) then
tmp_buckets_d0 <= tmp_84_i_fu_13711_p3;
elsif ((ap_ST_st23_fsm_22 = ap_CS_fsm)) then
tmp_buckets_d0 <= next_buckets_q0;
elsif (((ap_ST_st24_fsm_23 = ap_CS_fsm) or (ap_ST_st25_fsm_24 = ap_CS_fsm) or (ap_ST_st26_fsm_25 = ap_CS_fsm) or (ap_ST_st27_fsm_26 = ap_CS_fsm))) then
tmp_buckets_d0 <= grp_nfa_get_finals_1_fu_12905_finals_buckets_d0;
else
tmp_buckets_d0 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
-- tmp_buckets_we0 assign process. --
tmp_buckets_we0_assign_proc : process(ap_CS_fsm, grp_nfa_get_finals_1_fu_12905_finals_buckets_we0)
begin
if (((ap_ST_st43_fsm_42 = ap_CS_fsm) or (ap_ST_st23_fsm_22 = ap_CS_fsm))) then
tmp_buckets_we0 <= ap_const_logic_1;
elsif (((ap_ST_st24_fsm_23 = ap_CS_fsm) or (ap_ST_st25_fsm_24 = ap_CS_fsm) or (ap_ST_st26_fsm_25 = ap_CS_fsm) or (ap_ST_st27_fsm_26 = ap_CS_fsm))) then
tmp_buckets_we0 <= grp_nfa_get_finals_1_fu_12905_finals_buckets_we0;
else
tmp_buckets_we0 <= ap_const_logic_0;
end if;
end process;
tmp_s_fu_13002_p1 <= std_logic_vector(resize(unsigned(k_reg_612),64));
end behav;
| lgpl-3.0 | b5ed5a07d2d4ee292aed6f8d94302cc2 | 0.597735 | 2.351393 | false | false | false | false |
jairov4/accel-oil | solution_kintex7/sim/vhdl/bitset_next.vhd | 1 | 17,562 | -- ==============================================================
-- RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2013.4
-- Copyright (C) 2013 Xilinx Inc. All rights reserved.
--
-- ===========================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity bitset_next is
port (
ap_clk : IN STD_LOGIC;
ap_rst : IN STD_LOGIC;
p_read : IN STD_LOGIC_VECTOR (31 downto 0);
r_bit : IN STD_LOGIC_VECTOR (7 downto 0);
r_bucket_index : IN STD_LOGIC_VECTOR (7 downto 0);
r_bucket : IN STD_LOGIC_VECTOR (31 downto 0);
ap_return_0 : OUT STD_LOGIC_VECTOR (7 downto 0);
ap_return_1 : OUT STD_LOGIC_VECTOR (7 downto 0);
ap_return_2 : OUT STD_LOGIC_VECTOR (31 downto 0);
ap_return_3 : OUT STD_LOGIC_VECTOR (0 downto 0);
ap_ce : IN STD_LOGIC );
end;
architecture behav of bitset_next is
constant ap_const_logic_1 : STD_LOGIC := '1';
constant ap_const_logic_0 : STD_LOGIC := '0';
constant ap_const_lv1_0 : STD_LOGIC_VECTOR (0 downto 0) := "0";
constant ap_const_lv32_0 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000000";
constant ap_const_lv1_1 : STD_LOGIC_VECTOR (0 downto 0) := "1";
constant ap_const_lv2_1 : STD_LOGIC_VECTOR (1 downto 0) := "01";
constant ap_const_lv2_2 : STD_LOGIC_VECTOR (1 downto 0) := "10";
constant ap_const_lv32_FFFFFFFF : STD_LOGIC_VECTOR (31 downto 0) := "11111111111111111111111111111111";
constant ap_const_lv2_0 : STD_LOGIC_VECTOR (1 downto 0) := "00";
constant ap_const_lv32_1 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000001";
constant ap_const_lv8_1 : STD_LOGIC_VECTOR (7 downto 0) := "00000001";
constant ap_true : BOOLEAN := true;
signal r_bucket_read_reg_190 : STD_LOGIC_VECTOR (31 downto 0);
signal r_bit_read_reg_195 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_ppstg_r_bit_read_reg_195_pp0_it1 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_ppstg_r_bit_read_reg_195_pp0_it2 : STD_LOGIC_VECTOR (7 downto 0);
signal p_read_1_reg_201 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_p_read_1_reg_201_pp0_it1 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_p_read_1_reg_201_pp0_it2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_fu_123_p1 : STD_LOGIC_VECTOR (1 downto 0);
signal tmp_reg_209 : STD_LOGIC_VECTOR (1 downto 0);
signal ap_reg_ppstg_tmp_reg_209_pp0_it1 : STD_LOGIC_VECTOR (1 downto 0);
signal ap_reg_ppstg_tmp_reg_209_pp0_it2 : STD_LOGIC_VECTOR (1 downto 0);
signal tmp_1_fu_127_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_1_reg_215 : STD_LOGIC_VECTOR (31 downto 0);
signal bus_assign_fu_133_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal bus_assign_reg_220 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_bus_assign_reg_220_pp0_it2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_3_fu_137_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_3_reg_227 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_26_1_fu_142_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_26_1_reg_231 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_28_1_fu_147_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_28_1_reg_235 : STD_LOGIC_VECTOR (0 downto 0);
signal grp_p_bsf32_hw_fu_118_bus_r : STD_LOGIC_VECTOR (31 downto 0);
signal grp_p_bsf32_hw_fu_118_ap_return : STD_LOGIC_VECTOR (4 downto 0);
signal grp_p_bsf32_hw_fu_118_ap_ce : STD_LOGIC;
signal ap_reg_phiprechg_agg_result_bucket_write_assign_reg_54pp0_it3 : STD_LOGIC_VECTOR (31 downto 0);
signal agg_result_bucket_write_assign_phi_fu_58_p8 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_phiprechg_agg_result_bucket_write_assign_reg_54pp0_it2 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_phiprechg_agg_result_end_write_assign_reg_69pp0_it3 : STD_LOGIC_VECTOR (0 downto 0);
signal agg_result_end_write_assign_phi_fu_73_p8 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_phiprechg_agg_result_end_write_assign_reg_69pp0_it2 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_phiprechg_agg_result_bucket_index_write_assign_reg_87pp0_it3 : STD_LOGIC_VECTOR (1 downto 0);
signal agg_result_bucket_index_write_assign_phi_fu_91_p8 : STD_LOGIC_VECTOR (1 downto 0);
signal ap_reg_phiprechg_agg_result_bucket_index_write_assign_reg_87pp0_it2 : STD_LOGIC_VECTOR (1 downto 0);
signal agg_result_bit_write_assign_trunc3_ext_fu_157_p1 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_phiprechg_agg_result_bit_write_assign_reg_104pp0_it3 : STD_LOGIC_VECTOR (7 downto 0);
signal agg_result_bit_write_assign_phi_fu_107_p8 : STD_LOGIC_VECTOR (7 downto 0);
signal agg_result_bit_write_assign_trunc_ext_fu_152_p1 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_phiprechg_agg_result_bit_write_assign_reg_104pp0_it2 : STD_LOGIC_VECTOR (7 downto 0);
signal agg_result_bucket_index_write_assign_cast_fu_162_p1 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_sig_bdd_90 : BOOLEAN;
component p_bsf32_hw IS
port (
ap_clk : IN STD_LOGIC;
ap_rst : IN STD_LOGIC;
bus_r : IN STD_LOGIC_VECTOR (31 downto 0);
ap_return : OUT STD_LOGIC_VECTOR (4 downto 0);
ap_ce : IN STD_LOGIC );
end component;
begin
grp_p_bsf32_hw_fu_118 : component p_bsf32_hw
port map (
ap_clk => ap_clk,
ap_rst => ap_rst,
bus_r => grp_p_bsf32_hw_fu_118_bus_r,
ap_return => grp_p_bsf32_hw_fu_118_ap_return,
ap_ce => grp_p_bsf32_hw_fu_118_ap_ce);
-- ap_reg_phiprechg_agg_result_bit_write_assign_reg_104pp0_it3 assign process. --
ap_reg_phiprechg_agg_result_bit_write_assign_reg_104pp0_it3_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_ce)) then
if (ap_sig_bdd_90) then
ap_reg_phiprechg_agg_result_bit_write_assign_reg_104pp0_it3 <= ap_reg_ppstg_r_bit_read_reg_195_pp0_it1;
elsif ((ap_true = ap_true)) then
ap_reg_phiprechg_agg_result_bit_write_assign_reg_104pp0_it3 <= ap_reg_phiprechg_agg_result_bit_write_assign_reg_104pp0_it2;
end if;
end if;
end if;
end process;
-- ap_reg_phiprechg_agg_result_bucket_index_write_assign_reg_87pp0_it3 assign process. --
ap_reg_phiprechg_agg_result_bucket_index_write_assign_reg_87pp0_it3_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_ce)) then
if (ap_sig_bdd_90) then
ap_reg_phiprechg_agg_result_bucket_index_write_assign_reg_87pp0_it3 <= ap_const_lv2_2;
elsif ((ap_true = ap_true)) then
ap_reg_phiprechg_agg_result_bucket_index_write_assign_reg_87pp0_it3 <= ap_reg_phiprechg_agg_result_bucket_index_write_assign_reg_87pp0_it2;
end if;
end if;
end if;
end process;
-- ap_reg_phiprechg_agg_result_bucket_write_assign_reg_54pp0_it3 assign process. --
ap_reg_phiprechg_agg_result_bucket_write_assign_reg_54pp0_it3_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_ce)) then
if (ap_sig_bdd_90) then
ap_reg_phiprechg_agg_result_bucket_write_assign_reg_54pp0_it3(0) <= '0';
elsif ((ap_true = ap_true)) then
ap_reg_phiprechg_agg_result_bucket_write_assign_reg_54pp0_it3(0) <= ap_reg_phiprechg_agg_result_bucket_write_assign_reg_54pp0_it2(0);
end if;
end if;
end if;
end process;
-- ap_reg_phiprechg_agg_result_end_write_assign_reg_69pp0_it3 assign process. --
ap_reg_phiprechg_agg_result_end_write_assign_reg_69pp0_it3_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_ce)) then
ap_reg_ppstg_bus_assign_reg_220_pp0_it2 <= bus_assign_reg_220;
ap_reg_ppstg_p_read_1_reg_201_pp0_it1 <= p_read_1_reg_201;
ap_reg_ppstg_p_read_1_reg_201_pp0_it2 <= ap_reg_ppstg_p_read_1_reg_201_pp0_it1;
ap_reg_ppstg_r_bit_read_reg_195_pp0_it1 <= r_bit_read_reg_195;
ap_reg_ppstg_r_bit_read_reg_195_pp0_it2 <= ap_reg_ppstg_r_bit_read_reg_195_pp0_it1;
ap_reg_ppstg_tmp_reg_209_pp0_it1 <= tmp_reg_209;
ap_reg_ppstg_tmp_reg_209_pp0_it2 <= ap_reg_ppstg_tmp_reg_209_pp0_it1;
bus_assign_reg_220 <= bus_assign_fu_133_p2;
p_read_1_reg_201 <= p_read;
r_bit_read_reg_195 <= r_bit;
r_bucket_read_reg_190 <= r_bucket;
tmp_1_reg_215 <= tmp_1_fu_127_p2;
tmp_3_reg_227 <= tmp_3_fu_137_p2;
tmp_reg_209 <= tmp_fu_123_p1;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_ce) and not((tmp_3_fu_137_p2 = ap_const_lv1_0)))) then
tmp_26_1_reg_231 <= tmp_26_1_fu_142_p2;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_ce) and not((tmp_3_fu_137_p2 = ap_const_lv1_0)) and not((tmp_26_1_fu_142_p2 = ap_const_lv1_0)))) then
tmp_28_1_reg_235 <= tmp_28_1_fu_147_p2;
end if;
end if;
end process;
ap_reg_phiprechg_agg_result_bucket_write_assign_reg_54pp0_it3(31 downto 1) <= "0000000000000000000000000000000";
ap_reg_phiprechg_agg_result_end_write_assign_reg_69pp0_it3(0) <= '1';
-- agg_result_bit_write_assign_phi_fu_107_p8 assign process. --
agg_result_bit_write_assign_phi_fu_107_p8_assign_proc : process(ap_reg_ppstg_r_bit_read_reg_195_pp0_it2, tmp_3_reg_227, tmp_26_1_reg_231, tmp_28_1_reg_235, agg_result_bit_write_assign_trunc3_ext_fu_157_p1, ap_reg_phiprechg_agg_result_bit_write_assign_reg_104pp0_it3, agg_result_bit_write_assign_trunc_ext_fu_152_p1)
begin
if ((not((tmp_3_reg_227 = ap_const_lv1_0)) and not((tmp_26_1_reg_231 = ap_const_lv1_0)) and not((ap_const_lv1_0 = tmp_28_1_reg_235)))) then
agg_result_bit_write_assign_phi_fu_107_p8 <= ap_reg_ppstg_r_bit_read_reg_195_pp0_it2;
elsif ((tmp_3_reg_227 = ap_const_lv1_0)) then
agg_result_bit_write_assign_phi_fu_107_p8 <= agg_result_bit_write_assign_trunc_ext_fu_152_p1;
elsif ((not((tmp_3_reg_227 = ap_const_lv1_0)) and not((tmp_26_1_reg_231 = ap_const_lv1_0)) and (ap_const_lv1_0 = tmp_28_1_reg_235))) then
agg_result_bit_write_assign_phi_fu_107_p8 <= agg_result_bit_write_assign_trunc3_ext_fu_157_p1;
else
agg_result_bit_write_assign_phi_fu_107_p8 <= ap_reg_phiprechg_agg_result_bit_write_assign_reg_104pp0_it3;
end if;
end process;
agg_result_bit_write_assign_trunc3_ext_fu_157_p1 <= std_logic_vector(resize(unsigned(grp_p_bsf32_hw_fu_118_ap_return),8));
agg_result_bit_write_assign_trunc_ext_fu_152_p1 <= std_logic_vector(resize(unsigned(grp_p_bsf32_hw_fu_118_ap_return),8));
agg_result_bucket_index_write_assign_cast_fu_162_p1 <= std_logic_vector(resize(unsigned(agg_result_bucket_index_write_assign_phi_fu_91_p8),8));
-- agg_result_bucket_index_write_assign_phi_fu_91_p8 assign process. --
agg_result_bucket_index_write_assign_phi_fu_91_p8_assign_proc : process(ap_reg_ppstg_tmp_reg_209_pp0_it2, tmp_3_reg_227, tmp_26_1_reg_231, tmp_28_1_reg_235, ap_reg_phiprechg_agg_result_bucket_index_write_assign_reg_87pp0_it3)
begin
if ((not((tmp_3_reg_227 = ap_const_lv1_0)) and not((tmp_26_1_reg_231 = ap_const_lv1_0)) and not((ap_const_lv1_0 = tmp_28_1_reg_235)))) then
agg_result_bucket_index_write_assign_phi_fu_91_p8 <= ap_const_lv2_2;
elsif ((tmp_3_reg_227 = ap_const_lv1_0)) then
agg_result_bucket_index_write_assign_phi_fu_91_p8 <= ap_reg_ppstg_tmp_reg_209_pp0_it2;
elsif ((not((tmp_3_reg_227 = ap_const_lv1_0)) and not((tmp_26_1_reg_231 = ap_const_lv1_0)) and (ap_const_lv1_0 = tmp_28_1_reg_235))) then
agg_result_bucket_index_write_assign_phi_fu_91_p8 <= ap_const_lv2_1;
else
agg_result_bucket_index_write_assign_phi_fu_91_p8 <= ap_reg_phiprechg_agg_result_bucket_index_write_assign_reg_87pp0_it3;
end if;
end process;
-- agg_result_bucket_write_assign_phi_fu_58_p8 assign process. --
agg_result_bucket_write_assign_phi_fu_58_p8_assign_proc : process(ap_reg_ppstg_p_read_1_reg_201_pp0_it2, ap_reg_ppstg_bus_assign_reg_220_pp0_it2, tmp_3_reg_227, tmp_26_1_reg_231, tmp_28_1_reg_235, ap_reg_phiprechg_agg_result_bucket_write_assign_reg_54pp0_it3)
begin
if ((tmp_3_reg_227 = ap_const_lv1_0)) then
agg_result_bucket_write_assign_phi_fu_58_p8 <= ap_reg_ppstg_bus_assign_reg_220_pp0_it2;
elsif (((not((tmp_3_reg_227 = ap_const_lv1_0)) and not((tmp_26_1_reg_231 = ap_const_lv1_0)) and (ap_const_lv1_0 = tmp_28_1_reg_235)) or (not((tmp_3_reg_227 = ap_const_lv1_0)) and not((tmp_26_1_reg_231 = ap_const_lv1_0)) and not((ap_const_lv1_0 = tmp_28_1_reg_235))))) then
agg_result_bucket_write_assign_phi_fu_58_p8 <= ap_reg_ppstg_p_read_1_reg_201_pp0_it2;
else
agg_result_bucket_write_assign_phi_fu_58_p8 <= ap_reg_phiprechg_agg_result_bucket_write_assign_reg_54pp0_it3;
end if;
end process;
-- agg_result_end_write_assign_phi_fu_73_p8 assign process. --
agg_result_end_write_assign_phi_fu_73_p8_assign_proc : process(tmp_3_reg_227, tmp_26_1_reg_231, tmp_28_1_reg_235, ap_reg_phiprechg_agg_result_end_write_assign_reg_69pp0_it3)
begin
if ((not((tmp_3_reg_227 = ap_const_lv1_0)) and not((tmp_26_1_reg_231 = ap_const_lv1_0)) and not((ap_const_lv1_0 = tmp_28_1_reg_235)))) then
agg_result_end_write_assign_phi_fu_73_p8 <= ap_const_lv1_1;
elsif (((tmp_3_reg_227 = ap_const_lv1_0) or (not((tmp_3_reg_227 = ap_const_lv1_0)) and not((tmp_26_1_reg_231 = ap_const_lv1_0)) and (ap_const_lv1_0 = tmp_28_1_reg_235)))) then
agg_result_end_write_assign_phi_fu_73_p8 <= ap_const_lv1_0;
else
agg_result_end_write_assign_phi_fu_73_p8 <= ap_reg_phiprechg_agg_result_end_write_assign_reg_69pp0_it3;
end if;
end process;
ap_reg_phiprechg_agg_result_bit_write_assign_reg_104pp0_it2 <= ap_const_lv8_1;
ap_reg_phiprechg_agg_result_bucket_index_write_assign_reg_87pp0_it2 <= ap_const_lv2_1;
ap_reg_phiprechg_agg_result_bucket_write_assign_reg_54pp0_it2 <= ap_const_lv32_1;
ap_reg_phiprechg_agg_result_end_write_assign_reg_69pp0_it2 <= ap_const_lv1_1;
ap_return_0 <= agg_result_bit_write_assign_phi_fu_107_p8;
ap_return_1 <= agg_result_bucket_index_write_assign_cast_fu_162_p1;
ap_return_2 <= agg_result_bucket_write_assign_phi_fu_58_p8;
ap_return_3 <= agg_result_end_write_assign_phi_fu_73_p8;
-- ap_sig_bdd_90 assign process. --
ap_sig_bdd_90_assign_proc : process(tmp_3_fu_137_p2, tmp_26_1_fu_142_p2)
begin
ap_sig_bdd_90 <= (not((tmp_3_fu_137_p2 = ap_const_lv1_0)) and (tmp_26_1_fu_142_p2 = ap_const_lv1_0));
end process;
bus_assign_fu_133_p2 <= (tmp_1_reg_215 and r_bucket_read_reg_190);
-- grp_p_bsf32_hw_fu_118_ap_ce assign process. --
grp_p_bsf32_hw_fu_118_ap_ce_assign_proc : process(ap_ce, tmp_3_fu_137_p2, tmp_3_reg_227, tmp_26_1_fu_142_p2, tmp_26_1_reg_231, tmp_28_1_fu_147_p2, tmp_28_1_reg_235)
begin
if (((ap_const_logic_1 = ap_ce) and ((tmp_3_fu_137_p2 = ap_const_lv1_0) or (tmp_3_reg_227 = ap_const_lv1_0) or (not((tmp_3_fu_137_p2 = ap_const_lv1_0)) and not((tmp_26_1_fu_142_p2 = ap_const_lv1_0)) and (ap_const_lv1_0 = tmp_28_1_fu_147_p2)) or (not((tmp_3_reg_227 = ap_const_lv1_0)) and not((tmp_26_1_reg_231 = ap_const_lv1_0)) and (ap_const_lv1_0 = tmp_28_1_reg_235))))) then
grp_p_bsf32_hw_fu_118_ap_ce <= ap_const_logic_1;
else
grp_p_bsf32_hw_fu_118_ap_ce <= ap_const_logic_0;
end if;
end process;
-- grp_p_bsf32_hw_fu_118_bus_r assign process. --
grp_p_bsf32_hw_fu_118_bus_r_assign_proc : process(ap_reg_ppstg_p_read_1_reg_201_pp0_it1, bus_assign_reg_220, tmp_3_fu_137_p2, tmp_26_1_fu_142_p2, tmp_28_1_fu_147_p2)
begin
if ((not((tmp_3_fu_137_p2 = ap_const_lv1_0)) and not((tmp_26_1_fu_142_p2 = ap_const_lv1_0)) and (ap_const_lv1_0 = tmp_28_1_fu_147_p2))) then
grp_p_bsf32_hw_fu_118_bus_r <= ap_reg_ppstg_p_read_1_reg_201_pp0_it1;
elsif ((tmp_3_fu_137_p2 = ap_const_lv1_0)) then
grp_p_bsf32_hw_fu_118_bus_r <= bus_assign_reg_220;
else
grp_p_bsf32_hw_fu_118_bus_r <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
tmp_1_fu_127_p2 <= std_logic_vector(unsigned(r_bucket) + unsigned(ap_const_lv32_FFFFFFFF));
tmp_26_1_fu_142_p2 <= "1" when (ap_reg_ppstg_tmp_reg_209_pp0_it1 = ap_const_lv2_0) else "0";
tmp_28_1_fu_147_p2 <= "1" when (ap_reg_ppstg_p_read_1_reg_201_pp0_it1 = ap_const_lv32_0) else "0";
tmp_3_fu_137_p2 <= "1" when (bus_assign_reg_220 = ap_const_lv32_0) else "0";
tmp_fu_123_p1 <= r_bucket_index(2 - 1 downto 0);
end behav;
| lgpl-3.0 | 0507a8fb88d84f88263132d021bab7b0 | 0.627036 | 2.602935 | false | false | false | false |
jairov4/accel-oil | impl/impl_test_single/simulation/behavioral/nfa_accept_samples_generic_hw_top_v1_01_a/nfa_get_initials/_primary.vhd | 1 | 2,777 | library verilog;
use verilog.vl_types.all;
entity nfa_get_initials is
generic(
ap_const_logic_1: vl_logic := Hi1;
ap_const_logic_0: vl_logic := Hi0;
ap_ST_pp0_stg0_fsm_0: vl_logic_vector(0 to 1) := (Hi1, Hi0);
ap_ST_pp0_stg1_fsm_1: vl_logic_vector(0 to 1) := (Hi0, Hi0);
ap_ST_pp0_stg2_fsm_2: vl_logic_vector(0 to 1) := (Hi0, Hi1);
ap_ST_pp0_stg3_fsm_3: vl_logic_vector(0 to 1) := (Hi1, Hi1);
ap_const_lv64_1 : vl_logic_vector(0 to 63) := (Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi1);
ap_const_lv32_0 : integer := 0;
ap_const_lv32_1 : integer := 1;
ap_true : vl_logic := Hi1
);
port(
ap_clk : in vl_logic;
ap_rst : in vl_logic;
ap_start : in vl_logic;
ap_done : out vl_logic;
ap_idle : out vl_logic;
ap_ready : out vl_logic;
ap_ce : in vl_logic;
nfa_initials_buckets_req_din: out vl_logic;
nfa_initials_buckets_req_full_n: in vl_logic;
nfa_initials_buckets_req_write: out vl_logic;
nfa_initials_buckets_rsp_empty_n: in vl_logic;
nfa_initials_buckets_rsp_read: out vl_logic;
nfa_initials_buckets_address: out vl_logic_vector(31 downto 0);
nfa_initials_buckets_datain: in vl_logic_vector(31 downto 0);
nfa_initials_buckets_dataout: out vl_logic_vector(31 downto 0);
nfa_initials_buckets_size: out vl_logic_vector(31 downto 0);
ap_return_0 : out vl_logic_vector(31 downto 0);
ap_return_1 : out vl_logic_vector(31 downto 0)
);
attribute mti_svvh_generic_type : integer;
attribute mti_svvh_generic_type of ap_const_logic_1 : constant is 1;
attribute mti_svvh_generic_type of ap_const_logic_0 : constant is 1;
attribute mti_svvh_generic_type of ap_ST_pp0_stg0_fsm_0 : constant is 1;
attribute mti_svvh_generic_type of ap_ST_pp0_stg1_fsm_1 : constant is 1;
attribute mti_svvh_generic_type of ap_ST_pp0_stg2_fsm_2 : constant is 1;
attribute mti_svvh_generic_type of ap_ST_pp0_stg3_fsm_3 : constant is 1;
attribute mti_svvh_generic_type of ap_const_lv64_1 : constant is 1;
attribute mti_svvh_generic_type of ap_const_lv32_0 : constant is 1;
attribute mti_svvh_generic_type of ap_const_lv32_1 : constant is 1;
attribute mti_svvh_generic_type of ap_true : constant is 1;
end nfa_get_initials;
| lgpl-3.0 | 6f45f6916d137c6be58065793859b7cc | 0.600288 | 2.667627 | false | false | false | false |
grwlf/vsim | vhdl_ct/ct00216.vhd | 1 | 5,570 | -- NEED RESULT: ENT00216: Wait statement longest static prefix check passed
-- NEED RESULT: ENT00216: Wait statement longest static prefix check passed
-- NEED RESULT: ENT00216: Wait statement longest static prefix check passed
-- NEED RESULT: ENT00216: Wait statement longest static prefix check passed
-- NEED RESULT: P1: Wait longest static prefix test completed passed
-------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
-------------------------------------------------------------------------------
--
-- TEST NAME:
--
-- CT00216
--
-- AUTHOR:
--
-- G. Tominovich
--
-- TEST OBJECTIVES:
--
-- 8.1 (5)
--
-- DESIGN UNIT ORDERING:
--
-- ENT00216(ARCH00216)
-- ENT00216_Test_Bench(ARCH00216_Test_Bench)
--
-- REVISION HISTORY:
--
-- 10-JUL-1987 - initial revision
--
-- NOTES:
--
-- self-checking
-- automatically generated
--
use WORK.STANDARD_TYPES.all ;
entity ENT00216 is
generic (G : integer) ;
--
constant CG : integer := G+1;
attribute attr : integer ;
attribute attr of CG : constant is CG+1;
--
end ENT00216 ;
--
--
architecture ARCH00216 of ENT00216 is
signal s_st_arr1_vector : st_arr1_vector
:= c_st_arr1_vector_1 ;
--
subtype chk_sig_type is integer range -1 to 100 ;
signal chk_st_arr1_vector : chk_sig_type := -1 ;
--
procedure Proc1 (
signal s_st_arr1_vector : inout st_arr1_vector
; variable counter : inout integer
; variable correct : inout boolean
; variable savtime : inout time
; signal chk_st_arr1_vector : out chk_sig_type
)
is
begin
case counter is
when 0
=>
s_st_arr1_vector(1)(1) <= transport
c_st_arr1_vector_2(1)(1) ;
s_st_arr1_vector(2)(2) <= transport
c_st_arr1_vector_2(2)(2) after 10 ns ;
wait until s_st_arr1_vector(2)(2) =
c_st_arr1_vector_2(2)(2) ;
Test_Report (
"ENT00216",
"Wait statement longest static prefix check",
((savtime + 10 ns) = Std.Standard.Now) and
(s_st_arr1_vector(2)(2) =
c_st_arr1_vector_2(2)(2) )) ;
--
when 1
=>
s_st_arr1_vector(1)(1) <= transport
c_st_arr1_vector_1(1)(1) ;
s_st_arr1_vector(G)(G) <= transport
c_st_arr1_vector_2(G)(G) after 10 ns ;
wait until s_st_arr1_vector(G)(G) =
c_st_arr1_vector_2(G)(G) ;
Test_Report (
"ENT00216",
"Wait statement longest static prefix check",
((savtime + 10 ns) = Std.Standard.Now) and
(s_st_arr1_vector(G)(G) =
c_st_arr1_vector_2(G)(G) )) ;
--
when 2
=>
s_st_arr1_vector(1)(1) <= transport
c_st_arr1_vector_2(1)(1) ;
s_st_arr1_vector(CG)(CG) <= transport
c_st_arr1_vector_2(CG)(CG) after 10 ns ;
wait until s_st_arr1_vector(CG)(CG) =
c_st_arr1_vector_2(CG)(CG) ;
Test_Report (
"ENT00216",
"Wait statement longest static prefix check",
((savtime + 10 ns) = Std.Standard.Now) and
(s_st_arr1_vector(CG)(CG) =
c_st_arr1_vector_2(CG)(CG) )) ;
--
when 3
=>
s_st_arr1_vector(1)(1) <= transport
c_st_arr1_vector_1(1)(1) ;
s_st_arr1_vector(CG'Attr)(CG'Attr) <= transport
c_st_arr1_vector_2(CG'Attr)(CG'Attr) after 10 ns ;
wait until s_st_arr1_vector(CG'Attr)(CG'Attr) =
c_st_arr1_vector_2(CG'Attr)(CG'Attr) ;
Test_Report (
"ENT00216",
"Wait statement longest static prefix check",
((savtime + 10 ns) = Std.Standard.Now) and
(s_st_arr1_vector(CG'Attr)(CG'Attr) =
c_st_arr1_vector_2(CG'Attr)(CG'Attr) )) ;
--
when others
=> wait ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_st_arr1_vector <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
end Proc1 ;
--
begin
P1 :
process
variable counter : integer := 0 ;
variable correct : boolean ;
variable savtime : time := 0 ns ;
begin
Proc1 (
s_st_arr1_vector
, counter
, correct
, savtime
, chk_st_arr1_vector
) ;
end process P1 ;
--
PGEN_CHKP_1 :
process ( chk_st_arr1_vector )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P1" ,
"Wait longest static prefix test completed",
chk_st_arr1_vector = 3 ) ;
end if ;
end process PGEN_CHKP_1 ;
--
--
end ARCH00216 ;
--
--
use WORK.STANDARD_TYPES.all ;
entity ENT00216_Test_Bench is
end ENT00216_Test_Bench ;
--
--
architecture ARCH00216_Test_Bench of ENT00216_Test_Bench is
begin
L1:
block
component UUT
generic (G : integer) ;
end component ;
--
for CIS1 : UUT use entity WORK.ENT00216 ( ARCH00216 ) ;
begin
CIS1 : UUT
generic map (lowb+2)
;
end block L1 ;
end ARCH00216_Test_Bench ;
| gpl-3.0 | c93e7896744b471d9faa184b4909c880 | 0.495512 | 3.455335 | false | true | false | false |
jairov4/accel-oil | solution_virtex5_plb/impl/pcores/nfa_accept_samples_generic_hw_top_v1_01_a/synhdl/vhdl/nfa_forward_buckets_if_ap_fifo.vhd | 3 | 2,829 | -- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2014.1
-- Copyright (C) 2014 Xilinx Inc. All rights reserved.
--
-- ==============================================================
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
entity nfa_forward_buckets_if_ap_fifo is
generic (
DATA_WIDTH : integer := 32;
ADDR_WIDTH : integer := 16;
DEPTH : integer := 1);
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
if_empty_n : OUT STD_LOGIC;
if_read_ce : IN STD_LOGIC;
if_read : IN STD_LOGIC;
if_dout : OUT STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0);
if_full_n : OUT STD_LOGIC;
if_write_ce : IN STD_LOGIC;
if_write : IN STD_LOGIC;
if_din : IN STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0));
end entity;
architecture rtl of nfa_forward_buckets_if_ap_fifo is
type memtype is array (0 to DEPTH - 1) of STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0);
signal mStorage : memtype := (others => (others => '0'));
signal mInPtr : UNSIGNED(ADDR_WIDTH - 1 downto 0) := (others => '0');
signal mOutPtr : UNSIGNED(ADDR_WIDTH - 1 downto 0) := (others => '0');
signal internal_empty_n, internal_full_n : STD_LOGIC;
signal mFlag_nEF_hint : STD_LOGIC := '0'; -- 0: empty hint, 1: full hint
begin
if_dout <= mStorage(CONV_INTEGER(mOutPtr));
if_empty_n <= internal_empty_n;
if_full_n <= internal_full_n;
internal_empty_n <= '0' when mInPtr = mOutPtr and mFlag_nEF_hint = '0' else '1';
internal_full_n <= '0' when mInptr = mOutPtr and mFlag_nEF_hint = '1' else '1';
process (clk, reset)
begin
if reset = '1' then
mInPtr <= (others => '0');
mOutPtr <= (others => '0');
mFlag_nEF_hint <= '0'; -- empty hint
elsif clk'event and clk = '1' then
if if_read_ce = '1' and if_read = '1' and internal_empty_n = '1' then
if (mOutPtr = DEPTH -1) then
mOutPtr <= (others => '0');
mFlag_nEF_hint <= not mFlag_nEF_hint;
else
mOutPtr <= mOutPtr + 1;
end if;
end if;
if if_write_ce = '1' and if_write = '1' and internal_full_n = '1' then
mStorage(CONV_INTEGER(mInPtr)) <= if_din;
if (mInPtr = DEPTH -1) then
mInPtr <= (others => '0');
mFlag_nEF_hint <= not mFlag_nEF_hint;
else
mInPtr <= mInPtr + 1;
end if;
end if;
end if;
end process;
end architecture;
| lgpl-3.0 | 7aa4f5f76767b3f38d26ddd02e4d5bb7 | 0.497349 | 3.659767 | false | false | false | false |
jairov4/accel-oil | solution_virtex5_plb/impl/pcores/nfa_accept_samples_generic_hw_top_v1_01_a/synhdl/vhdl/nfa_finals_buckets_if_plb_master_if.vhd | 2 | 37,001 | -- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2014.1
-- Copyright (C) 2014 Xilinx Inc. All rights reserved.
--
-- ==============================================================
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity nfa_finals_buckets_if_ap_fifo_uw is
generic (
DATA_WIDTH : integer := 32;
ADDR_WIDTH : integer := 4;
DEPTH : integer := 16);
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
if_empty_n : OUT STD_LOGIC;
if_read : IN STD_LOGIC;
if_dout : OUT STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0);
if_full_n : OUT STD_LOGIC;
if_write : IN STD_LOGIC;
if_din : IN STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0);
use_word: OUT STD_LOGIC_VECTOR(ADDR_WIDTH -1 downto 0));
end entity;
architecture rtl of nfa_finals_buckets_if_ap_fifo_uw is
type memtype is array (0 to DEPTH - 1) of STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0);
signal mStorage : memtype;
signal mInPtr, mNextInPtr, mOutPtr : UNSIGNED(ADDR_WIDTH - 1 downto 0);
signal internal_empty_n, internal_full_n : STD_LOGIC;
signal internal_use_word : STD_LOGIC_VECTOR(ADDR_WIDTH -1 downto 0);
begin
mNextInPtr <= mInPtr + 1;
if_dout <= mStorage(CONV_INTEGER(mOutPtr));
if_empty_n <= internal_empty_n;
if_full_n <= internal_full_n;
use_word <= internal_use_word;
process (clk, reset)
begin
if reset = '1' then
mInPtr <= (others => '0');
mOutPtr <= (others => '0');
internal_use_word <= (others => '0');
else
if clk'event and clk = '1' then
if if_read = '1' and internal_empty_n = '1' then
mOutPtr <= mOutPtr + 1;
end if;
if if_write = '1' and internal_full_n = '1' then
mStorage(CONV_INTEGER(mInPtr)) <= if_din;
mInPtr <= mNextInPtr;
end if;
if (if_read = '1' and if_write = '0') then
internal_use_word <= internal_use_word - '1';
elsif (if_read = '0' and if_write = '1') then
internal_use_word <= internal_use_word + '1';
end if;
end if;
end if;
end process;
process (mInPtr, mOutPtr, mNextInPtr)
begin
if mInPtr = mOutPtr then
internal_empty_n <= '0';
else
internal_empty_n <= '1';
end if;
if mNextInPtr = mOutPtr then
internal_full_n <= '0';
else
internal_full_n <= '1';
end if;
end process;
end architecture;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity nfa_finals_buckets_if_plb_master_if is
generic
(
C_PLB_AWIDTH : integer := 32;
C_PLB_DWIDTH : integer := 64;
PLB_ADDR_SHIFT : integer := 3
);
port
(
-- ADD USER PORTS BELOW THIS LINE ------------------
--USER ports added here
-- ADD USER PORTS ABOVE THIS LINE ------------------
-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol ports, do not add to or delete
PLB_Clk : in std_logic;
PLB_Rst : in std_logic;
M_abort : out std_logic;
M_ABus : out std_logic_vector(0 to C_PLB_AWIDTH-1);
M_BE : out std_logic_vector(0 to C_PLB_DWIDTH/8-1);
M_busLock : out std_logic;
M_lockErr : out std_logic;
M_MSize : out std_logic_vector(0 to 1);
M_priority : out std_logic_vector(0 to 1);
M_rdBurst : out std_logic;
M_request : out std_logic;
M_RNW : out std_logic;
M_size : out std_logic_vector(0 to 3);
M_type : out std_logic_vector(0 to 2);
M_wrBurst : out std_logic;
M_wrDBus : out std_logic_vector(0 to C_PLB_DWIDTH-1);
PLB_MBusy : in std_logic;
PLB_MWrBTerm : in std_logic;
PLB_MWrDAck : in std_logic;
PLB_MAddrAck : in std_logic;
PLB_MRdBTerm : in std_logic;
PLB_MRdDAck : in std_logic;
PLB_MRdDBus : in std_logic_vector(0 to (C_PLB_DWIDTH-1));
PLB_MRdWdAddr : in std_logic_vector(0 to 3);
PLB_MRearbitrate : in std_logic;
PLB_MSSize : in std_logic_vector(0 to 1);
-- signals from user logic
BUS_RdData : out std_logic_vector(C_PLB_DWIDTH-1 downto 0); -- Bus read return data to user_logic
BUS_WrData : in std_logic_vector(C_PLB_DWIDTH-1 downto 0); -- Bus write data
BUS_address : in std_logic_vector(31 downto 0); -- physical address
BUS_size : in std_logic_vector(31 downto 0); -- burst size of word
BUS_req_nRW : in std_logic; -- req type 0: Read, 1: write
BUS_req_BE : in std_logic_vector(C_PLB_DWIDTH/8-1 downto 0); -- Bus write data byte enable
BUS_req_full_n : out std_logic; -- req Fifo full
BUS_req_push : in std_logic; -- req Fifo push (new request in)
BUS_rsp_nRW : out std_logic; -- return data FIFO rsp type
BUS_rsp_empty_n: out std_logic; -- return data FIFO empty
BUS_rsp_pop : in std_logic -- return data FIFO pop
);
attribute SIGIS : string;
attribute SIGIS of PLB_Clk : signal is "Clk";
attribute SIGIS of PLB_Rst : signal is "Rst";
end entity;
------------------------------------------------------------------------------
-- Architecture section
------------------------------------------------------------------------------
architecture IMP of nfa_finals_buckets_if_plb_master_if is
component nfa_finals_buckets_if_ap_fifo is
generic (
DATA_WIDTH : integer := 32;
ADDR_WIDTH : integer := 4;
DEPTH : integer := 16);
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
if_empty_n : OUT STD_LOGIC;
if_read : IN STD_LOGIC;
if_dout : OUT STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0);
if_full_n : OUT STD_LOGIC;
if_write : IN STD_LOGIC;
if_din : IN STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0));
end component;
component nfa_finals_buckets_if_ap_fifo_uw is
generic (
DATA_WIDTH : integer := 32;
ADDR_WIDTH : integer := 4;
DEPTH : integer := 16);
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
if_empty_n : OUT STD_LOGIC;
if_read : IN STD_LOGIC;
if_dout : OUT STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0);
if_full_n : OUT STD_LOGIC;
if_write : IN STD_LOGIC;
if_din : IN STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0);
use_word: OUT STD_LOGIC_VECTOR(ADDR_WIDTH -1 downto 0));
end component;
constant PLB_DW : integer := C_PLB_DWIDTH;
constant PLB_BYTE_COUNT : integer := PLB_DW/8;
constant REQ_FIFO_WIDTH : integer := 1 + PLB_BYTE_COUNT + 32 + 32; --nRW + BE + 32 bits phy addr + size
constant FIFO_ADDR_WIDTH : integer := 5;
constant FIFO_DEPTH : integer := 32;
-- request FIFO
signal req_fifo_empty_n : STD_LOGIC;
signal req_fifo_pop : STD_LOGIC;
signal req_fifo_dout : STD_LOGIC_VECTOR(REQ_FIFO_WIDTH - 1 downto 0);
signal req_fifo_full_n : STD_LOGIC;
signal req_fifo_push : STD_LOGIC;
signal req_fifo_din : STD_LOGIC_VECTOR(REQ_FIFO_WIDTH - 1 downto 0);
-- burst write counter (only push burst data in and ignore all burst write request except the first one)
signal req_burst_write: STD_LOGIC; -- whether last request is a burst write
signal req_burst_write_counter: STD_LOGIC_VECTOR(31 downto 0);
-- write data FIFO (for bus write data)
signal wd_fifo_empty_n : STD_LOGIC;
signal wd_fifo_pop : STD_LOGIC;
signal wd_fifo_dout : STD_LOGIC_VECTOR(PLB_DW - 1 downto 0);
signal wd_fifo_dout_mirror : STD_LOGIC_VECTOR(PLB_DW - 1 downto 0);
signal wd_fifo_full_n : STD_LOGIC;
signal wd_fifo_push : STD_LOGIC;
signal wd_fifo_din : STD_LOGIC_VECTOR(PLB_DW - 1 downto 0);
signal wd_fifo_use_word: STD_LOGIC_VECTOR(FIFO_ADDR_WIDTH -1 downto 0);
-- read data FIFO (for bus read returned data)
signal rd_fifo_empty_n : STD_LOGIC;
signal rd_fifo_pop : STD_LOGIC;
signal rd_fifo_dout : STD_LOGIC_VECTOR(PLB_DW - 1 downto 0);
signal rd_fifo_full_n : STD_LOGIC;
signal rd_fifo_push : STD_LOGIC;
signal rd_fifo_din : STD_LOGIC_VECTOR(PLB_DW - 1 downto 0);
signal rd_fifo_use_word: STD_LOGIC_VECTOR(FIFO_ADDR_WIDTH -1 downto 0);
signal req_address : std_logic_vector(0 to C_PLB_AWIDTH -1);-- bus request word address
signal req_fifo_dout_req_size : std_logic_vector(31 downto 0); -- req_size -1
signal req_size : std_logic_vector(0 to 27); -- burst size of 16 word block
signal request, req_nRW: std_logic;
signal req_BE : std_logic_vector(PLB_BYTE_COUNT-1 downto 0);
signal pending_rd_req_burst_mode: std_logic;
signal pending_rd_req_burst_size: std_logic_vector(3 downto 0);
signal pending_wr_req_burst_mode: std_logic;
signal pending_wr_req_burst_size: std_logic_vector(3 downto 0);
signal pending_read, pending_write: std_logic;
signal burst_mode, burst_last : std_logic;
signal burst_size : std_logic_vector(3 downto 0); -- maximum burst 16 words
--signals for write data mirror
signal conv_mode_comb : std_logic_vector(1 downto 0); -- 00: NO conv, 01: 128/32, 10: 64/32, 11: 128/64
signal conv_counter_comb: std_logic_vector(1 downto 0);
signal wr_data_phase : std_logic;
signal dataConv_last: std_logic;
signal dp_dataConv_last: std_logic;
signal dp_dataConv_word_addr: std_logic_vector(1 downto 0);
signal dp_dataConv_wd_conv_mode : std_logic_vector(1 downto 0); -- 00:NO conv, 01:128/32, 10:64/32, 11:128/64
signal dp_dataConv_wd_burst_counter: std_logic_vector(1 downto 0);
signal dp_dataConv_wd_BE: std_logic_vector(PLB_BYTE_COUNT-1 downto 0);
signal dp_PLB_MSSize : std_logic_vector(1 downto 0);
--signals for read data mirror
signal PLB_MRdDAck_reg : std_logic;
signal dp_dataConv_rd_conv_mode : std_logic_vector(1 downto 0);-- 00: NO conv, 01: 128/32, 10: 64/32, 11: 128/64
signal dp_dataConv_rd_burst_counter, dp_dataConv_rd_burst_counter_reg: std_logic_vector(1 downto 0);
signal PLB_MRdDBus_reverse : std_logic_vector(PLB_DW-1 downto 0);
-- signals with dp_ prefix stand for data phase signals
-- signals with req_ prefix stand for request phase signals
begin
-- interface to user logic
BUS_RdData <= rd_fifo_dout;
BUS_req_full_n <= req_fifo_full_n and wd_fifo_full_n;
BUS_rsp_nRW <= '0';
BUS_rsp_empty_n <= rd_fifo_empty_n;
-- interface to PLB
M_abort <= '0';
M_busLock <= '0';
M_lockErr <= '0';
M_MSize <= "01"; -- 00:32b dev, 01:64b, 10:128b, 11:256b
M_size <= "0000" when (burst_mode = '0' or burst_size = "0000") else "1011"; -- single rw or 64 bits burst
M_type <= "000"; -- memory trans
M_priority <= "00";
M_RNW <= not req_nRW;
M_rdBurst <= '1' when pending_rd_req_burst_mode = '1' and
(pending_rd_req_burst_size /= "0000" or dp_dataConv_rd_burst_counter /="00") else '0';
process (PLB_MSSize)
begin
M_wrBurst <= '0';
if (pending_wr_req_burst_mode = '1' and
(pending_wr_req_burst_size /= "0000" or dp_dataConv_wd_burst_counter /="00")) then
M_wrBurst <= '1';
elsif (request = '1' and req_nRW = '1' and pending_write = '0' and
burst_mode = '1' and burst_size /="0000" and wd_fifo_use_word > burst_size) then
M_wrBurst <= '1';
end if;
end process;
-- write data mirror section
process (PLB_MSSize)
begin
if (C_PLB_DWIDTH = 64 and PLB_MSSize = "00") then
conv_mode_comb <= "10"; -- conv 64:32
conv_counter_comb <= "01";
elsif (C_PLB_DWIDTH = 128 and PLB_MSSize = "01") then
conv_mode_comb <= "11"; -- conv 128:64
conv_counter_comb <= "01";
elsif (C_PLB_DWIDTH = 128 and PLB_MSSize = "00") then
conv_mode_comb <= "01"; -- conv 128:32
conv_counter_comb <= "11";
else
conv_mode_comb <= "00"; -- do not need conv
conv_counter_comb <= "00";
end if;
end process;
process (burst_mode, burst_size, conv_mode_comb, req_address, req_BE)
begin
dataConv_last <= '0';
if (burst_mode = '0' or burst_size = "0000") then
if (conv_mode_comb = "00") then -- no conv
dataConv_last <= '1';
elsif (conv_mode_comb = "10") then -- 64:32 conv
if (req_address(29)='1' or req_BE(PLB_BYTE_COUNT-1 downto PLB_BYTE_COUNT/2)=CONV_STD_LOGIC_VECTOR(0,PLB_BYTE_COUNT/2)) then
dataConv_last <= '1';
end if;
elsif (conv_mode_comb = "11") then -- 128:64 conv
if (req_address(28)='1' or req_BE(PLB_BYTE_COUNT-1 downto PLB_BYTE_COUNT/2)=CONV_STD_LOGIC_VECTOR(0,PLB_BYTE_COUNT/2)) then
dataConv_last <= '1';
end if;
elsif (conv_mode_comb = "01") then -- 128:32 conv
if (req_address(28 to 29) = "00" and req_BE(PLB_BYTE_COUNT-1 downto PLB_BYTE_COUNT/4)=CONV_STD_LOGIC_VECTOR(0,PLB_BYTE_COUNT*3/4)) then
dataConv_last <= '1';
elsif (req_address(28 to 29) = "01" and req_BE(PLB_BYTE_COUNT-1 downto PLB_BYTE_COUNT/2)=CONV_STD_LOGIC_VECTOR(0,PLB_BYTE_COUNT/2)) then
dataConv_last <= '1';
elsif (req_address(28 to 29) = "10" and req_BE(PLB_BYTE_COUNT-1 downto PLB_BYTE_COUNT*3/4)=CONV_STD_LOGIC_VECTOR(0,PLB_BYTE_COUNT/4)) then
dataConv_last <= '1';
elsif (req_address(28 to 29) = "11") then
dataConv_last <= '1';
end if;
end if;
end if;
end process;
process (PLB_Clk, PLB_Rst)
begin
if (PLB_Rst = '1') then
dp_dataConv_word_addr <= (others => '0');
dp_dataConv_wd_conv_mode <= (others =>'0');
dp_dataConv_wd_burst_counter <= (others => '0');
dp_dataConv_wd_BE <= (others => '0');
dp_dataConv_last <= '0';
wr_data_phase <= '0';
elsif (PLB_Clk'event and PLB_Clk = '1') then
if (PLB_MAddrAck = '1' and req_nRW = '1') then
dp_dataConv_wd_BE <= req_BE;
dp_dataConv_last <= dataConv_last;
end if;
if (PLB_MAddrAck = '1' and req_nRW = '1' and
(PLB_MWrDAck = '0' or (burst_mode = '1' and burst_size /= "0000"))) then
wr_data_phase <= '1';
end if;
if (PLB_MWrDAck = '1' and wr_data_phase = '1') then
if ((pending_wr_req_burst_size = "0000" and dp_dataConv_wd_burst_counter = "00") or
(pending_wr_req_burst_mode = '0')) then
wr_data_phase <= '0';
end if;
end if;
if (PLB_MAddrAck = '1' and req_nRW = '1' and dp_dataConv_wd_conv_mode = "00") then
if (PLB_MWrDAck = '0') then
-- only AddrAck asserted
dp_dataConv_wd_conv_mode <= conv_mode_comb;
dp_dataConv_word_addr <= req_address(28 to 29);
dp_dataConv_wd_burst_counter <= conv_counter_comb;
else
-- Xilinx PLB v4.6 support assert addrAck & wrDAck at the same cycle
if (dataConv_last = '0') then
dp_dataConv_wd_conv_mode <= conv_mode_comb;
end if;
if (PLB_MSSize = "00") then -- 32 bits slave
dp_dataConv_word_addr <= req_address(28 to 29) +1;
elsif (PLB_MSSize = "01") then -- 64 bits slave
dp_dataConv_word_addr <= req_address(28 to 29) +2;
end if;
if (conv_mode_comb /= "00") then -- need conv
dp_dataConv_wd_burst_counter <= conv_counter_comb -1;
end if;
end if;
end if;
if (wr_data_phase = '1' and PLB_MWrDAck = '1' and
((pending_wr_req_burst_mode = '1' and pending_wr_req_burst_size = "0000" and dp_dataConv_wd_burst_counter = "00") or
(pending_wr_req_burst_mode = '0' and dp_dataConv_last = '1'))) then
dp_dataConv_wd_conv_mode <= "00";
end if;
if (PLB_MWrDAck = '1' and wr_data_phase = '1') then
if (dp_PLB_MSSize = "01") then -- 64 bits slave
dp_dataConv_word_addr <= dp_dataConv_word_addr +2;
else
dp_dataConv_word_addr <= dp_dataConv_word_addr +1;
end if;
if ((pending_wr_req_burst_mode = '1' and pending_wr_req_burst_size /= "0000") or
dp_dataConv_wd_burst_counter /= "00") then
if (dp_dataConv_wd_burst_counter = "00") then
if (dp_dataConv_wd_conv_mode = "01") then -- 128/32
dp_dataConv_wd_burst_counter <= "11";
elsif (dp_dataConv_wd_conv_mode(1) = '1') then -- 64/32 or 128/64
dp_dataConv_wd_burst_counter <= "01";
end if;
else
dp_dataConv_wd_burst_counter <= dp_dataConv_wd_burst_counter -1;
end if;
end if;
end if;
end if;
end process;
process(PLB_MWrDAck, wr_data_phase, dp_dataConv_wd_burst_counter, burst_mode, conv_counter_comb, conv_mode_comb, req_BE)
begin
wd_fifo_pop <= '0';
if (PLB_MWrDAck = '1') then
if (wr_data_phase = '1') then
if ((pending_wr_req_burst_mode = '1' and dp_dataConv_wd_burst_counter = "00") or
(dp_dataConv_wd_conv_mode /= "00" and dp_dataConv_last = '1') or
dp_dataConv_wd_conv_mode = "00" )then
wd_fifo_pop <= '1';
end if;
else
-- got addrAck and wrDAck at the same cycle
if (burst_mode = '1' and burst_size /= "0000" and conv_counter_comb = "00") then
wd_fifo_pop <= '1';
elsif ((burst_mode = '0' or burst_size = "0000") and dataConv_last = '1') then
wd_fifo_pop <= '1';
end if;
end if;
end if;
end process;
process(wd_fifo_dout, wr_data_phase, req_address, dp_dataConv_wd_conv_mode, dp_dataConv_word_addr)
begin
wd_fifo_dout_mirror <= wd_fifo_dout;
if (wr_data_phase = '0') then -- we do not know slave bus width, perform default convert
if (C_PLB_DWIDTH = 32) then
wd_fifo_dout_mirror <= wd_fifo_dout;
elsif (C_PLB_DWIDTH = 64) then
if (req_address(29) = '0') then
wd_fifo_dout_mirror <= wd_fifo_dout;
else
wd_fifo_dout_mirror(PLB_DW/2-1 downto 0) <= wd_fifo_dout(PLB_DW-1 downto PLB_DW/2);
wd_fifo_dout_mirror(PLB_DW-1 downto PLB_DW/2) <= wd_fifo_dout(PLB_DW-1 downto PLB_DW/2);
end if;
elsif (C_PLB_DWIDTH = 128) then
case req_address(28 to 29) is
when "00" =>
wd_fifo_dout_mirror <= wd_fifo_dout;
when "01" =>
wd_fifo_dout_mirror(C_PLB_DWIDTH/4-1 downto 0) <= wd_fifo_dout(C_PLB_DWIDTH/2-1 downto C_PLB_DWIDTH/4);
wd_fifo_dout_mirror(C_PLB_DWIDTH-1 downto C_PLB_DWIDTH/4) <= wd_fifo_dout(C_PLB_DWIDTH-1 downto C_PLB_DWIDTH/4);
when "10" =>
wd_fifo_dout_mirror(C_PLB_DWIDTH/2-1 downto 0) <= wd_fifo_dout(C_PLB_DWIDTH-1 downto C_PLB_DWIDTH/2);
wd_fifo_dout_mirror(C_PLB_DWIDTH-1 downto C_PLB_DWIDTH/2) <= wd_fifo_dout(C_PLB_DWIDTH-1 downto C_PLB_DWIDTH/2);
when "11" =>
wd_fifo_dout_mirror(C_PLB_DWIDTH/4-1 downto 0) <= wd_fifo_dout(C_PLB_DWIDTH-1 downto C_PLB_DWIDTH*3/4);
wd_fifo_dout_mirror(C_PLB_DWIDTH/2-1 downto C_PLB_DWIDTH/4) <= wd_fifo_dout(C_PLB_DWIDTH-1 downto C_PLB_DWIDTH*3/4);
wd_fifo_dout_mirror(C_PLB_DWIDTH*3/4-1 downto C_PLB_DWIDTH/2) <= wd_fifo_dout(C_PLB_DWIDTH-1 downto C_PLB_DWIDTH*3/4);
wd_fifo_dout_mirror(C_PLB_DWIDTH-1 downto C_PLB_DWIDTH*3/4) <= wd_fifo_dout(C_PLB_DWIDTH-1 downto C_PLB_DWIDTH*3/4);
when others => null;
end case;
end if;
else -- in data phase
wd_fifo_dout_mirror <= wd_fifo_dout;
if ((dp_dataConv_wd_conv_mode = "10" and dp_dataConv_word_addr(0) = '1') or
(dp_dataConv_wd_conv_mode = "11" and dp_dataConv_word_addr(1) = '1')) then -- conv 64:32 or 128:64
wd_fifo_dout_mirror(C_PLB_DWIDTH/2-1 downto 0) <= wd_fifo_dout(C_PLB_DWIDTH-1 downto C_PLB_DWIDTH/2);
wd_fifo_dout_mirror(C_PLB_DWIDTH-1 downto C_PLB_DWIDTH/2) <= wd_fifo_dout(C_PLB_DWIDTH-1 downto C_PLB_DWIDTH/2);
elsif (dp_dataConv_wd_conv_mode = "01") then -- conv 128:32
case dp_dataConv_word_addr is
when "00" =>
wd_fifo_dout_mirror <= wd_fifo_dout;
when "01" =>
wd_fifo_dout_mirror(C_PLB_DWIDTH/4-1 downto 0) <= wd_fifo_dout(C_PLB_DWIDTH/2-1 downto C_PLB_DWIDTH/4);
when "10" =>
wd_fifo_dout_mirror(C_PLB_DWIDTH/4-1 downto 0) <= wd_fifo_dout(C_PLB_DWIDTH*3/4-1 downto C_PLB_DWIDTH/2);
when "11" =>
wd_fifo_dout_mirror(C_PLB_DWIDTH/4-1 downto 0) <= wd_fifo_dout(C_PLB_DWIDTH-1 downto C_PLB_DWIDTH*3/4);
when others => null;
end case;
end if;
end if;
end process;
process(wd_fifo_dout_mirror)
variable i: integer;
begin
for i in 0 to C_PLB_DWIDTH-1 loop
M_wrDBus(i) <= wd_fifo_dout_mirror(i);
end loop;
end process;
process (request, req_nRW, pending_read, burst_mode, rd_fifo_full_n, rd_fifo_use_word,
pending_write, wd_fifo_empty_n, wd_fifo_use_word, burst_size)
begin
M_request <= '0';
if (request = '1') then
if (req_nRW = '0' and pending_read = '0') then -- read request
if ((burst_mode = '0' or burst_size = "0000") and rd_fifo_full_n = '1') then
M_request <= '1';
elsif (rd_fifo_use_word(4) = '0') then -- 16 words slots available
M_request <= '1';
end if;
elsif (req_nRW = '1' and pending_write = '0') then -- write request
if ((burst_mode = '0' or burst_size = "0000") and wd_fifo_empty_n = '1') then
M_request <= '1';
elsif (wd_fifo_use_word > burst_size) then
M_request <= '1';
end if;
end if;
end if;
end process;
M_ABus(0 to C_PLB_AWIDTH - 1) <= req_address;
process(req_nRW, burst_mode, burst_size, req_BE)
variable i:integer;
begin
M_BE <= (others => '0');
if (burst_mode = '1') then
if (burst_size = "0000") then
M_BE <= (others => '1'); -- first single,then burst 16
else
M_BE(0 to 3) <= burst_size; -- fixed length burst
end if;
elsif (req_nRW = '0') then
M_BE <= (others => '1');
else
for i in 0 to PLB_BYTE_COUNT-1 loop
M_BE(i) <= req_BE(i);
end loop;
end if;
end process;
-- user req FIFO, for both read request and write request
U_req_nfa_finals_buckets_if_fifo: component nfa_finals_buckets_if_ap_fifo
generic map(
DATA_WIDTH => REQ_FIFO_WIDTH,
ADDR_WIDTH => FIFO_ADDR_WIDTH,
DEPTH => FIFO_DEPTH)
port map(
clk => PLB_Clk,
reset => PLB_Rst,
if_empty_n => req_fifo_empty_n,
if_read => req_fifo_pop,
if_dout => req_fifo_dout,
if_full_n => req_fifo_full_n,
if_write => req_fifo_push,
if_din => req_fifo_din
);
req_fifo_push <= BUS_req_push and not req_burst_write;
req_fifo_din <= BUS_req_nRW & BUS_req_BE & BUS_address & BUS_size;
req_fifo_dout_req_size <= req_fifo_dout(31 downto 0) -1;
process (PLB_Clk, PLB_Rst)
begin
if (PLB_Rst = '1') then
req_burst_write <= '0';
req_burst_write_counter <= (others => '0');
elsif (PLB_Clk'event and PLB_Clk = '1') then
if (req_fifo_push = '1' and BUS_req_nRW = '1' and BUS_size(31 downto 1) /= "0000000000000000000000000000000") then
req_burst_write <= '1';
req_burst_write_counter <= BUS_size - 1;
end if;
if (BUS_req_push = '1' and BUS_req_nRW = '1' and req_burst_write = '1') then
req_burst_write_counter <= req_burst_write_counter -1;
end if;
if (BUS_req_push = '1' and BUS_req_nRW = '1' and req_burst_write_counter = X"00000001") then-- last burst write data
req_burst_write <= '0';
end if;
end if;
end process;
process (PLB_Clk, PLB_Rst)
begin
if (PLB_Rst = '1') then
request <= '0';
req_size <= (others => '0');
req_nRW <= '0';
req_address(0 to C_PLB_AWIDTH - 1) <= (others => '0');
burst_mode <= '0';
burst_size <= (others => '0');
req_fifo_pop <= '0';
elsif (PLB_Clk'event and PLB_Clk = '1') then
req_fifo_pop <= '0';
if ((request = '0' and req_fifo_empty_n = '1') or PLB_MAddrAck = '1') then
if (PLB_MAddrAck = '1' and (burst_mode = '0' or burst_size ="0000") and dataConv_last = '0') then
request <= '1';
if (conv_mode_comb(1) = '1') then -- 2:1 conv
req_BE(PLB_BYTE_COUNT/2-1 downto 0) <= (others => '0');
else -- 128:32
if (req_address(28 to 29) = "00") then
req_BE(PLB_BYTE_COUNT/4-1 downto 0) <= (others => '0');
elsif (req_address(28 to 29) = "01") then
req_BE(PLB_BYTE_COUNT/2-1 downto PLB_BYTE_COUNT/4) <= (others => '0');
elsif (req_address(28 to 29) = "10") then
req_BE(PLB_BYTE_COUNT*3/4-1 downto PLB_BYTE_COUNT/2) <= (others => '0');
end if;
end if;
if (PLB_MSSize = "00") then -- 32 bits slave
req_address <= req_address + 4;
elsif (PLB_MSSize = "01") then -- 64 slave
req_address <= req_address + 8;
end if;-- 128 bits slave does not need conversion cycle
elsif (PLB_MAddrAck = '1' and burst_mode = '1' and burst_last = '0') then
request <= '1'; -- req next burst section, this will be pending until previous burst finished
req_size(0 to 27) <= req_size(0 to 27) - 1;
req_address(0 to C_PLB_AWIDTH - PLB_ADDR_SHIFT - 1) <= req_address(0 to C_PLB_AWIDTH -PLB_ADDR_SHIFT -1) + burst_size +1;
req_address(C_PLB_AWIDTH-PLB_ADDR_SHIFT to C_PLB_AWIDTH-1) <= (others => '0');
-- low bits of addr must be reset for possible data_conv modifications of 10 lines above
burst_mode <= '1';
burst_size <= "1111"; -- burst 16 words
else
if (req_fifo_empty_n = '1') then
req_fifo_pop <= '1';
end if;
request <= req_fifo_empty_n; -- fetch next user_req, may be a vaild req or a null req
req_size(0 to 27) <= req_fifo_dout_req_size(31 downto 4); --remaining burst transfer except current one
req_nRW <= req_fifo_dout(REQ_FIFO_WIDTH-1);
req_BE <= req_fifo_dout(REQ_FIFO_WIDTH-2 downto 64);
req_address <= req_fifo_dout(63 downto 32);
if (req_fifo_dout(REQ_FIFO_WIDTH-1) = '0') then -- read request
req_address(C_PLB_AWIDTH-PLB_ADDR_SHIFT to C_PLB_AWIDTH-1) <= (others => '0');
end if;
-- long burst request will be split to 1stReq: 1-16 words, all next req: 16 words
if (req_fifo_dout_req_size /= X"00000000") then -- more than 1 word, burst
burst_mode <= req_fifo_empty_n; -- fetched req may be null req
-- req of burst 17 will be single + burst 16, please check burst_size also
else
burst_mode <= '0';
end if;
burst_size(3 downto 0) <= req_fifo_dout_req_size(3 downto 0);-- 0:single, 1-15: burst 2-16words
end if;
end if;
end if;
end process;
process (PLB_Clk, PLB_Rst)
begin
if (PLB_Rst = '1') then
pending_read <= '0';
pending_write <= '0';
dp_PLB_MSSize <= (others => '0');
elsif (PLB_Clk'event and PLB_Clk = '1') then
if (PLB_MRdDAck = '1' and
((pending_rd_req_burst_mode = '1' and pending_rd_req_burst_size = "0000" and dp_dataConv_rd_burst_counter = "00") or
(pending_rd_req_burst_mode = '0'))) then
pending_read <= '0';
elsif (PLB_MAddrAck = '1' and req_nRW='0') then
pending_read <= '1';
end if;
if (PLB_MWrDAck = '1' and wr_data_phase = '1' and
((pending_wr_req_burst_mode = '1' and pending_wr_req_burst_size = "0000" and dp_dataConv_wd_burst_counter = "00") or
pending_wr_req_burst_mode = '0')) then
pending_write <= '0';
elsif (PLB_MAddrAck = '1' and req_nRW='1' and
(PLB_MWrDAck = '0' or burst_size /= "0000")) then
pending_write <= '1';
end if;
if (PLB_MAddrAck = '1') then
dp_PLB_MSSize <= PLB_MSSize;
end if;
end if;
end process;
process(req_size)
begin
if (req_size(0 to 27) = "000000000000000000000000000") then
burst_last <= '1'; -- one request is ok
else
burst_last <= '0';
end if;
end process;
-- user write data FIFO, for data of bus write request
U_wd_nfa_finals_buckets_if_fifo: component nfa_finals_buckets_if_ap_fifo_uw
generic map(
DATA_WIDTH => PLB_DW,
ADDR_WIDTH => FIFO_ADDR_WIDTH,
DEPTH => FIFO_DEPTH)
port map(
clk => PLB_Clk,
reset => PLB_Rst,
if_empty_n => wd_fifo_empty_n,
if_read => wd_fifo_pop,
if_dout => wd_fifo_dout,
if_full_n => wd_fifo_full_n,
if_write => wd_fifo_push,
if_din => wd_fifo_din,
use_word => wd_fifo_use_word
);
wd_fifo_push <= BUS_req_push and BUS_req_nRW;
wd_fifo_din <= BUS_WrData;
-- returned bus read data fifo
U_rd_nfa_finals_buckets_if_fifo: component nfa_finals_buckets_if_ap_fifo_uw
generic map(
DATA_WIDTH => PLB_DW,
ADDR_WIDTH => FIFO_ADDR_WIDTH,
DEPTH => FIFO_DEPTH)
port map(
clk => PLB_Clk,
reset => PLB_Rst,
if_empty_n => rd_fifo_empty_n,
if_read => rd_fifo_pop,
if_dout => rd_fifo_dout,
if_full_n => rd_fifo_full_n,
if_write => rd_fifo_push,
if_din => rd_fifo_din,
use_word => rd_fifo_use_word
);
process (PLB_Clk, PLB_Rst)
begin
if (PLB_Rst = '1') then
dp_dataConv_rd_conv_mode <= (others =>'0');
dp_dataConv_rd_burst_counter <= (others => '0');
dp_dataConv_rd_burst_counter_reg <= (others => '0');
PLB_MRdDAck_reg <= '0';
elsif (PLB_Clk'event and PLB_Clk = '1') then
if (PLB_MAddrAck = '1' and req_nRW = '0' and dp_dataConv_rd_conv_mode = "00") then
dp_dataConv_rd_conv_mode <= conv_mode_comb;
dp_dataConv_rd_burst_counter <= conv_counter_comb;
end if;
if (PLB_MRdDAck = '1' and
((pending_rd_req_burst_mode = '1' and (pending_rd_req_burst_size = "0000" and dp_dataConv_rd_burst_counter = "00")) or
(pending_rd_req_burst_mode = '0' and dp_dataConv_rd_burst_counter = "00")))then
dp_dataConv_rd_conv_mode <= "00";
end if;
if (PLB_MRdDAck = '1' and
((pending_rd_req_burst_mode = '1' and (pending_rd_req_burst_size /= "0000" or dp_dataConv_rd_burst_counter /= "00")) or
(pending_rd_req_burst_mode = '0' and dp_dataConv_rd_burst_counter /= "00")))then
if (dp_dataConv_rd_burst_counter = "00") then
if (dp_dataConv_rd_conv_mode = "01") then -- 128/32
dp_dataConv_rd_burst_counter <= "11";
elsif (dp_dataConv_rd_conv_mode(1) = '1') then -- 64/32 or 128/64
dp_dataConv_rd_burst_counter <= "01";
end if;
else
dp_dataConv_rd_burst_counter <= dp_dataConv_rd_burst_counter -1;
end if;
end if;
dp_dataConv_rd_burst_counter_reg <= dp_dataConv_rd_burst_counter;
PLB_MRdDAck_reg <= PLB_MRdDAck;
end if;
end process;
rd_fifo_push <= '1' when PLB_MRdDAck_reg = '1' and dp_dataConv_rd_burst_counter_reg = "00" else '0';
process(PLB_MRdDBus)
variable i: integer;
begin
-- change to little endian
for i in 0 to C_PLB_DWIDTH-1 loop
PLB_MRdDBus_reverse(i) <= PLB_MRdDBus(i);
end loop;
end process;
process(PLB_Clk, PLB_Rst)
begin
if (PLB_Rst = '1') then
rd_fifo_din <= (others => '0');
elsif (PLB_Clk'event and PLB_Clk = '1') then
if (PLB_MRdDAck = '1') then
case dp_dataConv_rd_conv_mode is
when "00" => rd_fifo_din <= PLB_MRdDBus_reverse;
when "10" | "11" =>
if (dp_dataConv_rd_burst_counter = "00") then
rd_fifo_din(PLB_DW-1 downto PLB_DW/2) <= PLB_MRdDBus_reverse(PLB_DW/2-1 downto 0);
else
rd_fifo_din(PLB_DW/2-1 downto 0) <= PLB_MRdDBus_reverse(PLB_DW/2-1 downto 0);
end if;
when "01" =>
case dp_dataConv_rd_burst_counter is
when "00" =>
rd_fifo_din(PLB_DW-1 downto PLB_DW*3/4) <= PLB_MRdDBus_reverse(PLB_DW/4-1 downto 0);
when "01" =>
rd_fifo_din(PLB_DW*3/4-1 downto PLB_DW/2) <= PLB_MRdDBus_reverse(PLB_DW/4-1 downto 0);
when "10" =>
rd_fifo_din(PLB_DW/2-1 downto PLB_DW/4) <= PLB_MRdDBus_reverse(PLB_DW/4-1 downto 0);
when "11" =>
rd_fifo_din(PLB_DW/4-1 downto 0) <= PLB_MRdDBus_reverse(PLB_DW/4-1 downto 0);
when others => null;
end case;
when others => null;
end case;
end if;
end if;
end process;
rd_fifo_pop <= BUS_rsp_pop;
pending_read_req_p: process (PLB_Clk, PLB_Rst)
begin
if (PLB_Rst = '1') then
pending_rd_req_burst_mode <= '0';
pending_rd_req_burst_size <= (others => '0');
elsif (PLB_Clk'event and PLB_Clk = '1') then
if (PLB_MAddrAck = '1' and req_nRW = '0') then
if (burst_mode = '1' and burst_size /= "0000") then
pending_rd_req_burst_mode <= burst_mode;
end if;
pending_rd_req_burst_size <= burst_size;
elsif (PLB_MRdDAck = '1' and pending_rd_req_burst_mode = '1') then
if (dp_dataConv_rd_burst_counter = "00") then
pending_rd_req_burst_size <= pending_rd_req_burst_size - 1;
if (pending_rd_req_burst_size = "0000") then
pending_rd_req_burst_mode <= '0';
end if;
end if;
end if;
end if;
end process;
pending_write_req_p: process (PLB_Clk, PLB_Rst)
begin
if (PLB_Rst = '1') then
pending_wr_req_burst_mode <= '0';
pending_wr_req_burst_size <= (others => '0');
elsif (PLB_Clk'event and PLB_Clk = '1') then
if (PLB_MAddrAck = '1' and req_nRW = '1') then
if (burst_mode = '1' and burst_size /= "0000") then
pending_wr_req_burst_mode <= '1';
end if;
pending_wr_req_burst_size <= burst_size;
if (PLB_MWrDAck = '1') then
if (conv_counter_comb = "00") then
pending_wr_req_burst_size <= burst_size -1;
else
pending_wr_req_burst_size <= burst_size;
end if;
end if;
elsif (PLB_MWrDAck = '1' and pending_wr_req_burst_mode = '1') then
if (dp_dataConv_wd_burst_counter = "00") then
pending_wr_req_burst_size <= pending_wr_req_burst_size - 1;
if (pending_wr_req_burst_size = "0000") then
pending_wr_req_burst_mode <= '0';
end if;
end if;
end if;
end if;
end process;
end IMP;
| lgpl-3.0 | 3e90e7b8fee36a1e75a39f77efea483f | 0.53485 | 3.307204 | false | false | false | false |
grwlf/vsim | vhdl_ct/pro000023.vhd | 1 | 20,060 | -- Prosoft VHDL tests.
--
-- Copyright (C) 2011 Prosoft.
--
-- Author: Zefirov, Karavaev.
--
-- This is a set of simplest tests for isolated tests of VHDL features.
--
-- Nothing more than standard package should be required.
--
-- Categories: entity, architecture, process, type, subtype, case, enumerations, array, for-loop, Attributes-of-the-array-type-or-objects-of-the-array-type
use work.std_logic_1164_for_tst.all;
entity ENT00023_Test_Bench is
end ENT00023_Test_Bench;
architecture ARCH00023_Test_Bench of ENT00023_Test_Bench is
subtype byte is bit_vector(1 to 8);
type IntArray is array (natural range <>) of integer;
type std_array is array (0 to 3) of std_logic;
signal I_sa : std_array := "1010";
type enum is (a_v, b_v, c_v, d_v, e_v, f_v);
type BooleanVector is array (integer range <>) of boolean;
type StateType is (init, assign, analize, waiting);
signal state : StateType := init;
begin
process (state)
variable vv1 : IntArray(7 downto 0) := (others => 7);
variable bv : bit_vector(9 downto 2);
variable vv3, vv4, vv5, vv6, vv7, vv8, vv9, vv10, vv11 : IntArray(7 downto 0);
variable vv2 : IntArray(107 downto 100);
subtype IntArray8 is IntArray(1 to 8);
variable int : IntArray(1 to 35) := (others => 0);
variable r_1, r_2, r_3, r_4 : real;
variable bool : BooleanVector(1 to 12) := (others => false);
type EnumArray is array (integer range <>) of enum;
variable ea : EnumArray(1 to 4);
subtype EnumArray4 is EnumArray(2 to 5);
begin
case state is
when init =>
vv2 := (107 => 10, 100 => 0, others => 3);
bv := x"A0";
state <= assign;
when assign =>
state <= analize;
-- bit_vector
int(5) := bv'low;
int(6) := bv'high;
int(7) := bv'left;
int(8) := bv'right;
int(17) := bv'length;
bool(2) := not bv'ascending;
int(27) := byte'low;
int(28) := byte'high;
int(29) := byte'left;
int(30) := byte'right;
int(31) := byte'length;
bool(6) := byte'ascending;
-- boolean vector
int(9) := bool'low;
int(10) := bool'high;
int(11) := bool'left;
int(12) := bool'right;
int(18) := bool'length;
bool(1) := bool'ascending;
-- IntArray
int(1) := vv2'low;
int(2) := vv2'high;
int(3) := vv2'left;
int(4) := vv2'right;
int(19) := vv2'length;
bool(3) := not vv2'ascending;
bool(4) := IntArray8'ascending;
int(20) := IntArray8'length;
int(32) := IntArray8'low;
int(33) := IntArray8'high;
int(34) := IntArray8'left;
int(35) := IntArray8'right;
-- EnumArray
int(13) := ea'Low;
int(14) := ea'High;
int(15) := ea'Left;
int(16) := ea'Right;
int(21) := ea'length;
bool(5) := ea'Ascending;
int(22) := EnumArray4'Low;
int(23) := EnumArray4'High;
int(24) := EnumArray4'Left;
int(25) := EnumArray4'Right;
int(26) := EnumArray4'Length;
bool(7) := EnumArray4'Ascending;
-- range
l1: for i in I_sa'range loop
vv1(i) := i;
end loop l1;
l2: for i in IntArray8'range loop
vv3(i-1) := i-1;
end loop l2;
l3: for i in bv'range loop
vv4(i-2) := i-2;
end loop l3;
l4: for i in std_array'range loop
vv5(i) := i;
vv5(i+4) := i+4;
end loop l4;
l5: for i in EnumArray4'range loop
vv6(i-2) := i-2;
vv6(i-2+4) := i-2+4;
end loop l5;
-- reverse_range
l6: for i in I_sa'reverse_range loop
vv7(i) := i;
vv7(i+4) := i+4;
end loop l6;
l7: for i in IntArray8'reverse_range loop
vv8(i-1) := i-1;
end loop l7;
l8: for i in bv'reverse_range loop
vv9(i-2) := i-2;
end loop l8;
l9: for i in std_array'reverse_range loop
vv10(i) := i;
vv10(i+4) := i+4;
end loop l9;
l10: for i in EnumArray4'reverse_range loop
vv11(i-2) := i-2;
vv11(i-2+4) := i-2+4;
end loop l10;
when analize =>
state <= waiting;
-- bit_vector
assert int(5) /= 2
report "Attribute A'Low(0) worked with the object of the type Bit_Vector correctly"
severity NOTE;
assert int(5) = 2
report "Attribute A'Low(0) does not work with the object of the type Bit_Vector"
severity NOTE;
assert int(6) /= 9
report "Attribute A'High(0) worked with the object of the type Bit_Vector correctly"
severity NOTE;
assert int(6) = 9
report "Attribute A'High(0) does not work with the object of the type Bit_Vector"
severity NOTE;
assert int(7) /= 9
report "Attribute A'Left(0) worked with the object of the type Bit_Vector correctly"
severity NOTE;
assert int(7) = 9
report "Attribute A'Left(0) does not work with the object of the type Bit_Vector"
severity NOTE;
assert int(8) /= 2
report "Attribute A'Right(0) worked with the object of the type Bit_Vector correctly"
severity NOTE;
assert int(8) = 2
report "Attribute A'Right(0) does not work with the object of the type Bit_Vector"
severity NOTE;
assert int(17) /= 8
report "Attribute A'Length(0) worked with the object of the type Bit_Vector correctly"
severity NOTE;
assert int(17) = 8
report "Attribute A'Length(0) does not work with the object of the type Bit_Vector"
severity NOTE;
assert not bool(2)
report "Attribute A'Ascending(0) worked with the object of the type Bit_Vector correctly"
severity NOTE;
assert bool(2)
report "Attribute A'Ascending(0) does not work with the object of the type Bit_Vector"
severity NOTE;
assert int(27) /= 1
report "Attribute A'Low(0) worked with the boarded subtype of the type Bit_Vector correctly"
severity NOTE;
assert int(27) = 1
report "Attribute A'Low(0) does not work with the boarded subtype of the type Bit_Vector"
severity NOTE;
assert int(28) /= 8
report "Attribute A'High(0) worked with the boarded subtype of the type Bit_Vector correctly"
severity NOTE;
assert int(28) = 8
report "Attribute A'High(0) does not work with the boarded subtype of the type Bit_Vector"
severity NOTE;
assert int(29) /= 1
report "Attribute A'Left(0) worked with the boarded subtype of the type Bit_Vector correctly"
severity NOTE;
assert int(29) = 1
report "Attribute A'Left(0) does not work with the boarded subtype of the type Bit_Vector"
severity NOTE;
assert int(30) /= 8
report "Attribute A'Right(0) worked with the boarded subtype of the type Bit_Vector correctly"
severity NOTE;
assert int(30) = 8
report "Attribute A'Right(0) does not work with the boarded subtype of the type Bit_Vector"
severity NOTE;
assert int(31) /= 8
report "Attribute A'Length(0) worked with the boarded subtype of the type Bit_Vector correctly"
severity NOTE;
assert int(31) = 8
report "Attribute A'Length(0) does not work with the boarded subtype of the type Bit_Vector"
severity NOTE;
assert not bool(6)
report "Attribute A'Ascending(0) worked with the boarded subtype of the type Bit_Vector correctly"
severity NOTE;
assert bool(6)
report "Attribute A'Ascending(0) does not work with the boarded subtype of the type Bit_Vector"
severity NOTE;
-- boolean vector
assert int(9) /= 1
report "Attribute A'Low(0) worked with the object of the boarded type Boolean Array correctly"
severity NOTE;
assert int(9) = 1
report "Attribute A'Low(0) does not work with the object of the boarded type Boolean Array"
severity NOTE;
assert int(10) /= 16#C#
report "Attribute A'High(0) worked with the object of the boarded type Boolean Array correctly"
severity NOTE;
assert int(10) = 16#C#
report "Attribute A'High(0) does not work with the object of the boarded type Boolean Array"
severity NOTE;
assert int(11) /= 1
report "Attribute A'Left(0) worked with the object of the boarded type Boolean Array correctly"
severity NOTE;
assert int(11) = 1
report "Attribute A'Left(0) does not work with the object of the boarded type Boolean Array"
severity NOTE;
assert int(12) /= 16#C#
report "Attribute A'Right(0) worked with the object of the boarded type Boolean Array correctly"
severity NOTE;
assert int(12) = 16#C#
report "Attribute A'Right(0) does not work with the object of the boarded type Boolean Array"
severity NOTE;
assert int(18) /= 16#C#
report "Attribute A'Length(0) worked with the object of the boarded type Boolean Array correctly"
severity NOTE;
assert int(18) = 16#C#
report "Attribute A'Length(0) does not work with the object of the boarded type Boolean Array"
severity NOTE;
assert not bool(1)
report "Attribute A'Ascending(0) worked with the object of the boarded type Boolean Array correctly"
severity NOTE;
assert bool(1)
report "Attribute A'Ascending(0) does not work with the object of the boarded type Boolean Array"
severity NOTE;
-- IntArray
assert int(1) /= 100
report "Attribute A'Low(0) worked with the object of the boarded type Integer Array correctly"
severity NOTE;
assert int(1) = 100
report "Attribute A'Low(0) does not work with the object of the boarded type Integer Array"
severity NOTE;
assert int(2) /= 107
report "Attribute A'High(0) worked with the object of the boarded type Integer Array correctly"
severity NOTE;
assert int(2) = 107
report "Attribute A'High(0) does not work with the object of the boarded type Integer Array"
severity NOTE;
assert int(3) /= 107
report "Attribute A'Left(0) worked with the object of the boarded type Integer Array correctly"
severity NOTE;
assert int(3) = 107
report "Attribute A'Left(0) does not work with the object of the boarded type Integer Array"
severity NOTE;
assert int(4) /= 100
report "Attribute A'Right(0) worked with the object of the boarded type Integer Array correctly"
severity NOTE;
assert int(4) = 100
report "Attribute A'Right(0) does not work with the object of the boarded type Integer Array"
severity NOTE;
assert int(19) /= 8
report "Attribute A'Length(0) worked with the object of the boarded type Integer Array correctly"
severity NOTE;
assert int(19) = 8
report "Attribute A'Length(0) does not work with the object of the boarded type Integer Array"
severity NOTE;
assert not bool(3)
report "Attribute A'Ascending(0) worked with the object of the boarded type Integer Array correctly"
severity NOTE;
assert bool(3)
report "Attribute A'Ascending(0) does not work with the object of the type boarded type Integer Array"
severity NOTE;
assert int(32) /= 1
report "Attribute A'Low(0) worked with the boarded subtype Integer Array correctly"
severity NOTE;
assert int(32) = 1
report "Attribute A'Low(0) does not work with the boarded subtype Integer Array"
severity NOTE;
assert int(33) /= 8
report "Attribute A'High(0) worked with the boarded subtype Integer Array correctly"
severity NOTE;
assert int(33) = 8
report "Attribute A'High(0) does not work with the boarded subtype Integer Array"
severity NOTE;
assert int(34) /= 1
report "Attribute A'Left(0) worked with the boarded subtype Integer Array correctly"
severity NOTE;
assert int(34) = 1
report "Attribute A'Left(0) does not work with the boarded subtype Integer Array"
severity NOTE;
assert int(35) /= 8
report "Attribute A'Right(0) worked with the boarded subtype Integer Array correctly"
severity NOTE;
assert int(35) = 8
report "Attribute A'Right(0) does not work with the boarded subtype Integer Array"
severity NOTE;
assert int(20) /= 8
report "Attribute A'Length(0) worked with the boarded subtype Integer Array correctly"
severity NOTE;
assert int(20) = 8
report "Attribute A'Length(0) does not work with the boarded subtype Integer Array"
severity NOTE;
assert not bool(4)
report "Attribute A'Ascending(0) worked with the boarded subtype Integer Array correctly"
severity NOTE;
assert bool(4)
report "Attribute A'Ascending(0) does not work with the type boarded subtype Integer Array"
severity NOTE;
-- EnumArray
assert int(13) /= 1
report "Attribute A'Low(0) worked with the object of the boarded type Enum Array correctly"
severity NOTE;
assert int(13) = 1
report "Attribute A'Low(0) does not work with the object of the boarded type Enum Array"
severity NOTE;
assert int(14) /= 4
report "Attribute A'High(0) worked with the object of the boarded type Enum Array correctly"
severity NOTE;
assert int(14) = 4
report "Attribute A'High(0) does not work with the object of the boarded type Enum Array"
severity NOTE;
assert int(15) /= 1
report "Attribute A'Left(0) worked with the object of the boarded type Enum Array correctly"
severity NOTE;
assert int(15) = 1
report "Attribute A'Left(0) does not work with the object of the boarded type Enum Array"
severity NOTE;
assert int(16) /= 4
report "Attribute A'Right(0) worked with the object of the boarded type Enum Array correctly"
severity NOTE;
assert int(16) = 4
report "Attribute A'Right(0) does not work with the object of the boarded type Enum Array"
severity NOTE;
assert int(21) /= 4
report "Attribute A'Length(0) worked with the object of the boarded type Enum Array correctly"
severity NOTE;
assert int(21) = 4
report "Attribute A'Length(0) does not work with the object of the boarded type Enum Array"
severity NOTE;
assert not bool(5)
report "Attribute A'Ascending(0) worked with the object of the boarded type Enum Array correctly"
severity NOTE;
assert bool(5)
report "Attribute A'Ascending(0) does not work with the object of the type boarded type Enum Array"
severity NOTE;
assert int(22) /= 2
report "Attribute A'Low(0) worked with the boarded type Enum Array correctly"
severity NOTE;
assert int(22) = 2
report "Attribute A'Low(0) does not work with the boarded type Enum Array"
severity NOTE;
assert int(23) /= 5
report "Attribute A'High(0) worked with the boarded type Enum Array correctly"
severity NOTE;
assert int(23) = 5
report "Attribute A'High(0) does not work with the boarded type Enum Array"
severity NOTE;
assert int(24) /= 2
report "Attribute A'Left(0) worked with the boarded type Enum Array correctly"
severity NOTE;
assert int(24) = 2
report "Attribute A'Left(0) does not work with the boarded type Enum Array"
severity NOTE;
assert int(25) /= 5
report "Attribute A'Right(0) worked with the boarded type Enum Array correctly"
severity NOTE;
assert int(25) = 5
report "Attribute A'Right(0) does not work with the boarded type Enum Array"
severity NOTE;
assert int(26) /= 4
report "Attribute A'Length(0) worked with the boarded type Enum Array correctly"
severity NOTE;
assert int(26) = 4
report "Attribute A'Length(0) does not work with the boarded type Enum Array"
severity NOTE;
assert not bool(7)
report "Attribute A'Ascending(0) worked with the boarded type Enum Array correctly"
severity NOTE;
assert bool(7)
report "Attribute A'Ascending(0) does not work with the type boarded type Enum Array"
severity NOTE;
-- Range
-- obj of std_logic array
assert vv1 /= 7 & 7 & 7 & 7 & 3 & 2 & 1 & 0
report "Attribute A'Range(0) worked with the object of the boarded type Std_logic Array correctly"
severity NOTE;
assert vv1 = 7 & 7 & 7 & 7 & 3 & 2 & 1 & 0
report "Attribute A'Range(0) does not work with the object of the boarded type Std_logic Array"
severity NOTE;
-- Boarded Integer Array
assert vv3 /= 7 & 6 & 5 & 4 & 3 & 2 & 1 & 0
report "Attribute A'Range(0) worked with the boarded subtype Integer Array correctly"
severity NOTE;
assert vv3 = 7 & 6 & 5 & 4 & 3 & 2 & 1 & 0
report "Attribute A'Range(0) does not work with the boarded subtype Integer Array"
severity NOTE;
-- obj of boarded bit_vector
assert vv4 /= 7 & 6 & 5 & 4 & 3 & 2 & 1 & 0
report "Attribute A'Range(0) worked with the object of the bit_vector correctly"
severity NOTE;
assert vv4 = 7 & 6 & 5 & 4 & 3 & 2 & 1 & 0
report "Attribute A'Range(0) does not work with the object of the bit_vector"
severity NOTE;
-- boarded std_logic array
assert vv5 /= 7 & 6 & 5 & 4 & 3 & 2 & 1 & 0
report "Attribute A'Range(0) worked with the boarded type Std_logic Array correctly"
severity NOTE;
assert vv5 = 7 & 6 & 5 & 4 & 3 & 2 & 1 & 0
report "Attribute A'Range(0) does not work with the boarded type Std_logic Array"
severity NOTE;
-- boarded enum array
assert vv6 /= 7 & 6 & 5 & 4 & 3 & 2 & 1 & 0
report "Attribute A'Range(0) worked with the boarded subtype Enumeration Array correctly"
severity NOTE;
assert vv6 = 7 & 6 & 5 & 4 & 3 & 2 & 1 & 0
report "Attribute A'Range(0) does not work with the boarded subtype Enumeration Array"
severity NOTE;
-- Reverse_Range
-- obj of std_logic array
assert vv7 /= 7 & 6 & 5 & 4 & 3 & 2 & 1 & 0
report "Attribute A'Reverse_range(0) worked with the object of the boarded type Std_logic Array correctly"
severity NOTE;
assert vv7 = 7 & 6 & 5 & 4 & 3 & 2 & 1 & 0
report "Attribute A'Reverse_range(0) does not work with the object of the boarded type Std_logic Array"
severity NOTE;
-- Boarded Integer Array
assert vv8 /= 7 & 6 & 5 & 4 & 3 & 2 & 1 & 0
report "Attribute A'Reverse_range(0) worked with the boarded subtype Integer Array correctly"
severity NOTE;
assert vv8 = 7 & 6 & 5 & 4 & 3 & 2 & 1 & 0
report "Attribute A'Reverse_range(0) does not work with the boarded subtype Integer Array"
severity NOTE;
-- obj of boarded bit_vector
assert vv9 /= 7 & 6 & 5 & 4 & 3 & 2 & 1 & 0
report "Attribute A'Reverse_range(0) worked with the object of the bit_vector correctly"
severity NOTE;
assert vv9 = 7 & 6 & 5 & 4 & 3 & 2 & 1 & 0
report "Attribute A'Reverse_range(0) does not work with the object of the bit_vector"
severity NOTE;
-- boarded std_logic array
assert vv10 /= 7 & 6 & 5 & 4 & 3 & 2 & 1 & 0
report "Attribute A'Reverse_range(0) worked with the boarded type Std_logic Array correctly"
severity NOTE;
assert vv10 = 7 & 6 & 5 & 4 & 3 & 2 & 1 & 0
report "Attribute A'Reverse_range(0) does not work with the boarded type Std_logic Array"
severity NOTE;
-- boarded enum array
assert vv11 /= 7 & 6 & 5 & 4 & 3 & 2 & 1 & 0
report "Attribute A'Reverse_range(0) worked with the boarded subtype Enumeration Array correctly"
severity NOTE;
assert vv11 = 7 & 6 & 5 & 4 & 3 & 2 & 1 & 0
report "Attribute A'Reverse_range(0) does not work with the boarded subtype Enumeration Array"
severity NOTE;
when waiting =>
null;
end case;
end process;
end ARCH00023_Test_Bench ; | gpl-3.0 | 9ddba3ea85b2ee450ff5a4de4ec260f0 | 0.629063 | 3.434343 | false | false | false | false |
jairov4/accel-oil | impl/impl_test_pcie/simulation/behavioral/elaborate/lmb_bram_elaborate_v1_00_a/hdl/vhdl/lmb_bram_elaborate.vhd | 1 | 4,504 | -------------------------------------------------------------------------------
-- lmb_bram_elaborate.vhd
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity lmb_bram_elaborate is
generic (
C_MEMSIZE : integer;
C_PORT_DWIDTH : integer;
C_PORT_AWIDTH : integer;
C_NUM_WE : integer;
C_FAMILY : string
);
port (
BRAM_Rst_A : in std_logic;
BRAM_Clk_A : in std_logic;
BRAM_EN_A : in std_logic;
BRAM_WEN_A : in std_logic_vector(0 to C_NUM_WE-1);
BRAM_Addr_A : in std_logic_vector(0 to C_PORT_AWIDTH-1);
BRAM_Din_A : out std_logic_vector(0 to C_PORT_DWIDTH-1);
BRAM_Dout_A : in std_logic_vector(0 to C_PORT_DWIDTH-1);
BRAM_Rst_B : in std_logic;
BRAM_Clk_B : in std_logic;
BRAM_EN_B : in std_logic;
BRAM_WEN_B : in std_logic_vector(0 to C_NUM_WE-1);
BRAM_Addr_B : in std_logic_vector(0 to C_PORT_AWIDTH-1);
BRAM_Din_B : out std_logic_vector(0 to C_PORT_DWIDTH-1);
BRAM_Dout_B : in std_logic_vector(0 to C_PORT_DWIDTH-1)
);
end lmb_bram_elaborate;
architecture STRUCTURE of lmb_bram_elaborate is
component RAMB36 is
generic (
WRITE_MODE_A : string;
WRITE_MODE_B : string;
INIT_FILE : string;
READ_WIDTH_A : integer;
READ_WIDTH_B : integer;
WRITE_WIDTH_A : integer;
WRITE_WIDTH_B : integer;
RAM_EXTENSION_A : string;
RAM_EXTENSION_B : string
);
port (
ADDRA : in std_logic_vector(15 downto 0);
CASCADEINLATA : in std_logic;
CASCADEINREGA : in std_logic;
CASCADEOUTLATA : out std_logic;
CASCADEOUTREGA : out std_logic;
CLKA : in std_logic;
DIA : in std_logic_vector(31 downto 0);
DIPA : in std_logic_vector(3 downto 0);
DOA : out std_logic_vector(31 downto 0);
DOPA : out std_logic_vector(3 downto 0);
ENA : in std_logic;
REGCEA : in std_logic;
SSRA : in std_logic;
WEA : in std_logic_vector(3 downto 0);
ADDRB : in std_logic_vector(15 downto 0);
CASCADEINLATB : in std_logic;
CASCADEINREGB : in std_logic;
CASCADEOUTLATB : out std_logic;
CASCADEOUTREGB : out std_logic;
CLKB : in std_logic;
DIB : in std_logic_vector(31 downto 0);
DIPB : in std_logic_vector(3 downto 0);
DOB : out std_logic_vector(31 downto 0);
DOPB : out std_logic_vector(3 downto 0);
ENB : in std_logic;
REGCEB : in std_logic;
SSRB : in std_logic;
WEB : in std_logic_vector(3 downto 0)
);
end component;
-- Internal signals
signal net_gnd0 : std_logic;
signal net_gnd4 : std_logic_vector(3 downto 0);
signal pgassign1 : std_logic_vector(0 to 0);
signal pgassign2 : std_logic_vector(0 to 4);
signal pgassign3 : std_logic_vector(15 downto 0);
signal pgassign4 : std_logic_vector(15 downto 0);
begin
-- Internal assignments
pgassign1(0 to 0) <= B"1";
pgassign2(0 to 4) <= B"00000";
pgassign3(15 downto 15) <= B"1";
pgassign3(14 downto 5) <= BRAM_Addr_A(20 to 29);
pgassign3(4 downto 0) <= B"00000";
pgassign4(15 downto 15) <= B"1";
pgassign4(14 downto 5) <= BRAM_Addr_B(20 to 29);
pgassign4(4 downto 0) <= B"00000";
net_gnd0 <= '0';
net_gnd4(3 downto 0) <= B"0000";
ramb36_0 : RAMB36
generic map (
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
INIT_FILE => "lmb_bram_combined_0.mem",
READ_WIDTH_A => 36,
READ_WIDTH_B => 36,
WRITE_WIDTH_A => 36,
WRITE_WIDTH_B => 36,
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE"
)
port map (
ADDRA => pgassign3,
CASCADEINLATA => net_gnd0,
CASCADEINREGA => net_gnd0,
CASCADEOUTLATA => open,
CASCADEOUTREGA => open,
CLKA => BRAM_Clk_A,
DIA => BRAM_Dout_A(0 to 31),
DIPA => net_gnd4,
DOA => BRAM_Din_A(0 to 31),
DOPA => open,
ENA => BRAM_EN_A,
REGCEA => net_gnd0,
SSRA => BRAM_Rst_A,
WEA => BRAM_WEN_A(0 to 3),
ADDRB => pgassign4,
CASCADEINLATB => net_gnd0,
CASCADEINREGB => net_gnd0,
CASCADEOUTLATB => open,
CASCADEOUTREGB => open,
CLKB => BRAM_Clk_B,
DIB => BRAM_Dout_B(0 to 31),
DIPB => net_gnd4,
DOB => BRAM_Din_B(0 to 31),
DOPB => open,
ENB => BRAM_EN_B,
REGCEB => net_gnd0,
SSRB => BRAM_Rst_B,
WEB => BRAM_WEN_B(0 to 3)
);
end architecture STRUCTURE;
| lgpl-3.0 | 3a9e871bbb89a589498042b0a37ffde7 | 0.573268 | 3.273256 | false | false | false | false |
wsoltys/AtomFpga | src/AVR8/Memory/XPM4Kx16.vhd | 1 | 8,512 | --************************************************************************************************
-- 4Kx16(8 KB) PM RAM for AVR Core(Xilinx)
-- Version 0.1
-- Designed by Ruslan Lepetenok modified by Jack Gassett for use with Spartan 3E
-- Modified 11.06.2009
--************************************************************************************************
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
-- For Synplicity Synplify
--library virtexe;
--use virtexe.components.all;
-- Aldec
library unisim;
use unisim.vcomponents.all;
entity XPM4Kx16 is port(
cp2 : in std_logic;
ce : in std_logic;
address : in std_logic_vector(11 downto 0);
din : in std_logic_vector(15 downto 0);
dout : out std_logic_vector(15 downto 0);
we : in std_logic
);
end XPM4Kx16;
architecture RTL of XPM4Kx16 is
type RAMBlDOut_Type is array(2**(address'length-10)-1 downto 0) of std_logic_vector(dout'range);
signal RAMBlDOut : RAMBlDOut_Type;
signal WEB : std_logic_vector(2**(address'length-10)-1 downto 0);
signal gnd : std_logic;
signal DIP : STD_LOGIC_VECTOR(1 downto 0) := "11";
signal SSR : STD_LOGIC := '0'; -- Don't use the output resets.
begin
gnd <= '0';
WEB_Dcd:for i in WEB'range generate
WEB(i) <= '1' when (we='1' and address(address'high downto 10)=i) else '0';
end generate ;
RAM_Inst:for i in 0 to 2**(address'length-10)-1 generate
RAM_Word:component RAMB16_S18
generic map (
INIT => X"00000", -- Value of output RAM registers at startup
SRVAL => X"00000", -- Ouput value upon SSR assertion
WRITE_MODE => "WRITE_FIRST", -- WRITE_FIRST, READ_FIRST or NO_CHANGE
-- The following INIT_xx declarations specify the intial contents of the RAM
-- Address 0 to 255
INIT_00 => X"007E940C007E940C007E940C007E940C007E940C007E940C007E940C005B940C",
INIT_01 => X"007E940C007E940C007E940C007E940C007E940C007E940C007E940C007E940C",
INIT_02 => X"007E940C007E940C007E940C007E940C007E940C007E940C007E940C009D940C",
INIT_03 => X"0404040404040030003600000000003200350038000000000031003700000000",
INIT_04 => X"0804020120100804020180402010080402010303030303030202020202020404",
INIT_05 => X"BFDEE0DFEFCFBE1F241100000000000000000604030000010200070000002010",
INIT_06 => X"07B136A2F3C89631920D95D8C004BF0B9503EF0FE0F3E2ECE0B0E6A0E010BFCD",
INIT_07 => X"0000940C0194940C018D940EF7E107B136AB921DC001E0B0E6A2E010BE1BF7C9",
INIT_08 => X"0151940EE0600060918000F5940EE090E080E070E0610151940EE06100609180",
INIT_09 => X"B60F920F921F95080129940EE06100609180950800F5940EE090E080E070E061",
INIT_0A => X"006791300066912093BF93AF939F938F937F936F935F934F933F932F2411920F",
INIT_0B => X"376D5F6A2F671DB11DA196022F822F932FA42FB5006A91700069915000689140",
INIT_0C => X"93A00067939000669380006A93601DB11DA196032F822F932FA42FB5576DF040",
INIT_0D => X"006293801DB11DA19601006591B0006491A00063919000629180006993B00068",
INIT_0E => X"912F913F914F915F916F917F918F919F91AF91BF006593B0006493A000639390",
INIT_0F => X"914094F8B78F2F192F082EF72EE6931F930F92FF92EF9518901F900FBE0F900F",
INIT_10 => X"006891A0006791900066918094F8B72FBF8F0069917000689160006791500066",
INIT_11 => X"90EF90FF910F911FF760071B070A06F916E80BB70BA60B951B84BF2F006991B0",
INIT_12 => X"2FE84F9F57822F932F82E0302F289508BF876081B787BF836084B78394789508",
INIT_13 => X"5AE01FFF0FEEE0F02FE8F0A923882D8095C82FF32FE24F3F58262D9095C82FF9",
INIT_14 => X"938C2B89918C9508938C23899590918CF42923662DB095C896312DA095C84FFF",
INIT_15 => X"2FE84F9F57822F952F842D2095C82FF92FE84F9F558E2F952F84E0502F489508",
INIT_16 => X"B58FF4193023F0512322F10923332D3095C82FF52FE44F5F58462D9095C82FF9",
INIT_17 => X"96312DA095C84FFF59E81FFF0FEEE0F02FE3BD8F7D8FB58FF4193024C004778F",
INIT_18 => X"940E0121940E9508938C2B89918C9508938C23899590918CF42923662DB095C8",
INIT_19 => X"000000000000000000000000000000000000000DCFFF94F8CFFD0080940E0097",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
-- Address 768 to 1023
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000",
-- The next set of INITP_xx are for the parity bits
-- Address 0 to 255
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
-- Address 256 to 511
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
-- Address 512 to 767
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
-- Address 768 to 1023
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000")
port map(
DO => RAMBlDOut(i)(15 downto 0),
ADDR => address(9 downto 0),
DI => din(15 downto 0),
DIP => DIP,
EN => ce,
SSR => SSR,
CLK => cp2,
WE => WEB(i)
);
end generate;
-- Output data mux
dout <= RAMBlDOut(CONV_INTEGER(address(address'high downto 10)));
end RTL;
| apache-2.0 | 388661086512a616646ef876b50d7dc5 | 0.760926 | 3.953553 | false | false | false | false |
jairov4/accel-oil | impl/impl_test_single/simulation/behavioral/elaborate/clock_generator_0_v4_03_a/hdl/vhdl/clock_generator.vhd | 1 | 37,697 | ------------------------------------------------------------------------------
-- C:/Users/JairoAndres/Documents/Vivado/oil_plainc_hls/impl/impl_test_single/simulation/behavioral/elaborate/clock_generator_0_v4_03_a/hdl/vhdl/clock_generator.vhd
------------------------------------------------------------------------------
-- ClkGen Wrapper HDL file generated by ClkGen's TCL generator
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.all;
library Unisim;
use Unisim.vcomponents.all;
library clock_generator_v4_03_a;
use clock_generator_v4_03_a.all;
entity clock_generator is
generic (
C_FAMILY : string := "virtex5" ;
C_DEVICE : string := "5vlx50t";
C_PACKAGE : string := "ff1136";
C_SPEEDGRADE : string := "-2";
C_CLK_GEN : string := "PASSED"
);
port (
-- clock generation
CLKIN : in std_logic;
CLKOUT0 : out std_logic;
CLKOUT1 : out std_logic;
CLKOUT2 : out std_logic;
CLKOUT3 : out std_logic;
CLKOUT4 : out std_logic;
CLKOUT5 : out std_logic;
CLKOUT6 : out std_logic;
CLKOUT7 : out std_logic;
CLKOUT8 : out std_logic;
CLKOUT9 : out std_logic;
CLKOUT10 : out std_logic;
CLKOUT11 : out std_logic;
CLKOUT12 : out std_logic;
CLKOUT13 : out std_logic;
CLKOUT14 : out std_logic;
CLKOUT15 : out std_logic;
-- external feedback
CLKFBIN : in std_logic;
CLKFBOUT : out std_logic;
-- variable phase shift
PSCLK : in std_logic;
PSEN : in std_logic;
PSINCDEC : in std_logic;
PSDONE : out std_logic;
-- reset
RST : in std_logic;
LOCKED : out std_logic
);
end clock_generator;
architecture STRUCTURE of clock_generator is
----------------------------------------------------------------------------
-- Components ( copy from entity, exact the same in low level parameters )
----------------------------------------------------------------------------
component pll_module is
generic (
C_BANDWIDTH : string := "OPTIMIZED";
C_CLKFBOUT_MULT : integer := 1;
C_CLKFBOUT_PHASE : real := 0.0;
C_CLKIN1_PERIOD : real := 0.000;
-- C_CLKIN2_PERIOD : real := 0.000;
C_CLKOUT0_DIVIDE : integer := 1;
C_CLKOUT0_DUTY_CYCLE : real := 0.5;
C_CLKOUT0_PHASE : real := 0.0;
C_CLKOUT1_DIVIDE : integer := 1;
C_CLKOUT1_DUTY_CYCLE : real := 0.5;
C_CLKOUT1_PHASE : real := 0.0;
C_CLKOUT2_DIVIDE : integer := 1;
C_CLKOUT2_DUTY_CYCLE : real := 0.5;
C_CLKOUT2_PHASE : real := 0.0;
C_CLKOUT3_DIVIDE : integer := 1;
C_CLKOUT3_DUTY_CYCLE : real := 0.5;
C_CLKOUT3_PHASE : real := 0.0;
C_CLKOUT4_DIVIDE : integer := 1;
C_CLKOUT4_DUTY_CYCLE : real := 0.5;
C_CLKOUT4_PHASE : real := 0.0;
C_CLKOUT5_DIVIDE : integer := 1;
C_CLKOUT5_DUTY_CYCLE : real := 0.5;
C_CLKOUT5_PHASE : real := 0.0;
C_COMPENSATION : string := "SYSTEM_SYNCHRONOUS";
C_DIVCLK_DIVIDE : integer := 1;
-- C_EN_REL : boolean := false;
-- C_PLL_PMCD_MODE : boolean := false;
C_REF_JITTER : real := 0.100;
C_RESET_ON_LOSS_OF_LOCK : boolean := false;
C_RST_DEASSERT_CLK : string := "CLKIN1";
C_CLKOUT0_DESKEW_ADJUST : string := "NONE";
C_CLKOUT1_DESKEW_ADJUST : string := "NONE";
C_CLKOUT2_DESKEW_ADJUST : string := "NONE";
C_CLKOUT3_DESKEW_ADJUST : string := "NONE";
C_CLKOUT4_DESKEW_ADJUST : string := "NONE";
C_CLKOUT5_DESKEW_ADJUST : string := "NONE";
C_CLKFBOUT_DESKEW_ADJUST : string := "NONE";
C_CLKIN1_BUF : boolean := false;
-- C_CLKIN2_BUF : boolean := false;
C_CLKFBOUT_BUF : boolean := false;
C_CLKOUT0_BUF : boolean := false;
C_CLKOUT1_BUF : boolean := false;
C_CLKOUT2_BUF : boolean := false;
C_CLKOUT3_BUF : boolean := false;
C_CLKOUT4_BUF : boolean := false;
C_CLKOUT5_BUF : boolean := false;
C_EXT_RESET_HIGH : integer := 1;
C_FAMILY : string := "spartan6"
);
port (
CLKFBDCM : out std_logic;
CLKFBOUT : out std_logic;
CLKOUT0 : out std_logic;
CLKOUT1 : out std_logic;
CLKOUT2 : out std_logic;
CLKOUT3 : out std_logic;
CLKOUT4 : out std_logic;
CLKOUT5 : out std_logic;
CLKOUTDCM0 : out std_logic;
CLKOUTDCM1 : out std_logic;
CLKOUTDCM2 : out std_logic;
CLKOUTDCM3 : out std_logic;
CLKOUTDCM4 : out std_logic;
CLKOUTDCM5 : out std_logic;
-- DO : out std_logic_vector (15 downto 0);
-- DRDY : out std_logic;
LOCKED : out std_logic;
CLKFBIN : in std_logic;
CLKIN1 : in std_logic;
-- CLKIN2 : in std_logic;
-- CLKINSEL : in std_logic;
-- DADDR : in std_logic_vector (4 downto 0);
-- DCLK : in std_logic;
-- DEN : in std_logic;
-- DI : in std_logic_vector (15 downto 0);
-- DWE : in std_logic;
-- REL : in std_logic;
RST : in std_logic
);
end component;
----------------------------------------------------------------------------
-- Functions
----------------------------------------------------------------------------
-- Note : The string functions are put here to remove dependency to other pcore level libraries
function UpperCase_Char(char : character) return character is
begin
-- If char is not an upper case letter then return char
if char < 'a' or char > 'z' then
return char;
end if;
-- Otherwise map char to its corresponding lower case character and
-- return that
case char is
when 'a' => return 'A'; when 'b' => return 'B'; when 'c' => return 'C'; when 'd' => return 'D';
when 'e' => return 'E'; when 'f' => return 'F'; when 'g' => return 'G'; when 'h' => return 'H';
when 'i' => return 'I'; when 'j' => return 'J'; when 'k' => return 'K'; when 'l' => return 'L';
when 'm' => return 'M'; when 'n' => return 'N'; when 'o' => return 'O'; when 'p' => return 'P';
when 'q' => return 'Q'; when 'r' => return 'R'; when 's' => return 'S'; when 't' => return 'T';
when 'u' => return 'U'; when 'v' => return 'V'; when 'w' => return 'W'; when 'x' => return 'X';
when 'y' => return 'Y'; when 'z' => return 'Z';
when others => return char;
end case;
end UpperCase_Char;
function UpperCase_String (s : string) return string is
variable res : string(s'range);
begin -- function LoweerCase_String
for I in s'range loop
res(I) := UpperCase_Char(s(I));
end loop; -- I
return res;
end function UpperCase_String;
-- Returns true if case insensitive string comparison determines that
-- str1 and str2 are equal
function equalString( str1, str2 : string ) return boolean is
constant len1 : integer := str1'length;
constant len2 : integer := str2'length;
variable equal : boolean := true;
begin
if not (len1 = len2) then
equal := false;
else
for i in str1'range loop
if not (UpperCase_Char(str1(i)) = UpperCase_Char(str2(i))) then
equal := false;
end if;
end loop;
end if;
return equal;
end equalString;
----------------------------------------------------------------------------
-- Signals
----------------------------------------------------------------------------
-- signals: gnd
signal net_gnd0 : std_logic;
signal net_gnd1 : std_logic_vector(0 to 0);
signal net_gnd16 : std_logic_vector(0 to 15);
-- signals: vdd
signal net_vdd0 : std_logic;
-- signals : PLL0 wrapper
signal SIG_PLL0_CLKFBDCM : std_logic;
signal SIG_PLL0_CLKFBOUT : std_logic;
signal SIG_PLL0_CLKOUT0 : std_logic;
signal SIG_PLL0_CLKOUT1 : std_logic;
signal SIG_PLL0_CLKOUT2 : std_logic;
signal SIG_PLL0_CLKOUT3 : std_logic;
signal SIG_PLL0_CLKOUT4 : std_logic;
signal SIG_PLL0_CLKOUT5 : std_logic;
signal SIG_PLL0_CLKOUTDCM0 : std_logic;
signal SIG_PLL0_CLKOUTDCM1 : std_logic;
signal SIG_PLL0_CLKOUTDCM2 : std_logic;
signal SIG_PLL0_CLKOUTDCM3 : std_logic;
signal SIG_PLL0_CLKOUTDCM4 : std_logic;
signal SIG_PLL0_CLKOUTDCM5 : std_logic;
signal SIG_PLL0_LOCKED : std_logic;
signal SIG_PLL0_CLKFBIN : std_logic;
signal SIG_PLL0_CLKIN1 : std_logic;
signal SIG_PLL0_RST : std_logic;
signal SIG_PLL0_CLKFBOUT_BUF : std_logic;
signal SIG_PLL0_CLKOUT0_BUF : std_logic;
signal SIG_PLL0_CLKOUT1_BUF : std_logic;
signal SIG_PLL0_CLKOUT2_BUF : std_logic;
signal SIG_PLL0_CLKOUT3_BUF : std_logic;
signal SIG_PLL0_CLKOUT4_BUF : std_logic;
signal SIG_PLL0_CLKOUT5_BUF : std_logic;
begin
----------------------------------------------------------------------------
-- GND and VCC signals
----------------------------------------------------------------------------
net_gnd0 <= '0';
net_gnd1(0 to 0) <= B"0";
net_gnd16(0 to 15) <= B"0000000000000000";
net_vdd0 <= '1';
----------------------------------------------------------------------------
-- DCM wrappers
----------------------------------------------------------------------------
----------------------------------------------------------------------------
-- PLL wrappers
----------------------------------------------------------------------------
-- PLL0 wrapper
PLL0_INST : pll_module
generic map (
C_BANDWIDTH => "OPTIMIZED",
C_CLKFBOUT_MULT => 12,
C_CLKFBOUT_PHASE => 0.0,
C_CLKIN1_PERIOD => 10.000000,
C_CLKOUT0_DIVIDE => 24,
C_CLKOUT0_DUTY_CYCLE => 0.5,
C_CLKOUT0_PHASE => 0.0000,
C_CLKOUT1_DIVIDE => 1,
C_CLKOUT1_DUTY_CYCLE => 0.5,
C_CLKOUT1_PHASE => 0.0,
C_CLKOUT2_DIVIDE => 1,
C_CLKOUT2_DUTY_CYCLE => 0.5,
C_CLKOUT2_PHASE => 0.0,
C_CLKOUT3_DIVIDE => 1,
C_CLKOUT3_DUTY_CYCLE => 0.5,
C_CLKOUT3_PHASE => 0.0,
C_CLKOUT4_DIVIDE => 1,
C_CLKOUT4_DUTY_CYCLE => 0.5,
C_CLKOUT4_PHASE => 0.0,
C_CLKOUT5_DIVIDE => 1,
C_CLKOUT5_DUTY_CYCLE => 0.5,
C_CLKOUT5_PHASE => 0.0,
C_COMPENSATION => "SYSTEM_SYNCHRONOUS",
C_DIVCLK_DIVIDE => 1,
C_REF_JITTER => 0.100,
C_RESET_ON_LOSS_OF_LOCK => false,
C_RST_DEASSERT_CLK => "CLKIN1",
C_CLKOUT0_DESKEW_ADJUST => "NONE",
C_CLKOUT1_DESKEW_ADJUST => "NONE",
C_CLKOUT2_DESKEW_ADJUST => "NONE",
C_CLKOUT3_DESKEW_ADJUST => "NONE",
C_CLKOUT4_DESKEW_ADJUST => "NONE",
C_CLKOUT5_DESKEW_ADJUST => "NONE",
C_CLKFBOUT_DESKEW_ADJUST => "NONE",
C_CLKIN1_BUF => false,
C_CLKFBOUT_BUF => false,
C_CLKOUT0_BUF => false,
C_CLKOUT1_BUF => false,
C_CLKOUT2_BUF => false,
C_CLKOUT3_BUF => false,
C_CLKOUT4_BUF => false,
C_CLKOUT5_BUF => false,
C_EXT_RESET_HIGH => 0,
C_FAMILY => "virtex5"
)
port map (
CLKFBDCM => SIG_PLL0_CLKFBDCM,
CLKFBOUT => SIG_PLL0_CLKFBOUT,
CLKOUT0 => SIG_PLL0_CLKOUT0,
CLKOUT1 => SIG_PLL0_CLKOUT1,
CLKOUT2 => SIG_PLL0_CLKOUT2,
CLKOUT3 => SIG_PLL0_CLKOUT3,
CLKOUT4 => SIG_PLL0_CLKOUT4,
CLKOUT5 => SIG_PLL0_CLKOUT5,
CLKOUTDCM0 => SIG_PLL0_CLKOUTDCM0,
CLKOUTDCM1 => SIG_PLL0_CLKOUTDCM1,
CLKOUTDCM2 => SIG_PLL0_CLKOUTDCM2,
CLKOUTDCM3 => SIG_PLL0_CLKOUTDCM3,
CLKOUTDCM4 => SIG_PLL0_CLKOUTDCM4,
CLKOUTDCM5 => SIG_PLL0_CLKOUTDCM5,
-- DO
-- DRDY
LOCKED => SIG_PLL0_LOCKED,
CLKFBIN => SIG_PLL0_CLKFBIN,
CLKIN1 => SIG_PLL0_CLKIN1,
-- CLKIN2
-- CLKINSEL
-- DADDR
-- DCLK
-- DEN
-- DI
-- DWE
-- REL
RST => SIG_PLL0_RST
);
-- wrapper of clkout : CLKOUT0
PLL0_CLKOUT0_BUFG_INST : BUFG
port map (
I => SIG_PLL0_CLKOUT0,
O => SIG_PLL0_CLKOUT0_BUF
);
-- wrapper of clkout : CLKOUT1
SIG_PLL0_CLKOUT1_BUF <= SIG_PLL0_CLKOUT1;
-- wrapper of clkout : CLKOUT2
SIG_PLL0_CLKOUT2_BUF <= SIG_PLL0_CLKOUT2;
-- wrapper of clkout : CLKOUT3
SIG_PLL0_CLKOUT3_BUF <= SIG_PLL0_CLKOUT3;
-- wrapper of clkout : CLKOUT4
SIG_PLL0_CLKOUT4_BUF <= SIG_PLL0_CLKOUT4;
-- wrapper of clkout : CLKOUT5
SIG_PLL0_CLKOUT5_BUF <= SIG_PLL0_CLKOUT5;
-- wrapper of clkout : CLKFBOUT
PLL0_CLKFBOUT_BUFG_INST : BUFG
port map (
I => SIG_PLL0_CLKFBOUT,
O => SIG_PLL0_CLKFBOUT_BUF
);
----------------------------------------------------------------------------
-- MMCM wrappers
----------------------------------------------------------------------------
----------------------------------------------------------------------------
-- PLLE wrappers
----------------------------------------------------------------------------
----------------------------------------------------------------------------
-- DCMs CLKIN, CLKFB and RST signal connection
----------------------------------------------------------------------------
----------------------------------------------------------------------------
-- PLLs CLKIN1, CLKFBIN and RST signal connection
----------------------------------------------------------------------------
-- PLL0 CLKIN1
SIG_PLL0_CLKIN1 <= CLKIN;
-- PLL0 CLKFBIN
SIG_PLL0_CLKFBIN <= SIG_PLL0_CLKFBOUT;
-- PLL0 RST
SIG_PLL0_RST <= RST;
----------------------------------------------------------------------------
-- MMCMs CLKIN1, CLKFBIN, RST and Variable_Phase_Control signal connection
----------------------------------------------------------------------------
----------------------------------------------------------------------------
-- PLLEs CLKIN1, CLKFBIN, RST and Variable_Phase_Control signal connection
----------------------------------------------------------------------------
----------------------------------------------------------------------------
-- CLKGEN CLKOUT, CLKFBOUT and LOCKED signal connection
----------------------------------------------------------------------------
-- CLKGEN CLKOUT
CLKOUT0 <= SIG_PLL0_CLKOUT0_BUF;
CLKOUT1 <= '0';
CLKOUT2 <= '0';
CLKOUT3 <= '0';
CLKOUT4 <= '0';
CLKOUT5 <= '0';
CLKOUT6 <= '0';
CLKOUT7 <= '0';
CLKOUT8 <= '0';
CLKOUT9 <= '0';
CLKOUT10 <= '0';
CLKOUT11 <= '0';
CLKOUT12 <= '0';
CLKOUT13 <= '0';
CLKOUT14 <= '0';
CLKOUT15 <= '0';
-- CLKGEN CLKFBOUT
-- CLKGEN LOCKED
LOCKED <= SIG_PLL0_LOCKED;
end architecture STRUCTURE;
------------------------------------------------------------------------------
-- High level parameters
------------------------------------------------------------------------------
-- C_CLK_GEN = PASSED
-- C_ELABORATE_DIR =
-- C_ELABORATE_RES = NOT_SET
-- C_FAMILY = virtex5
-- C_DEVICE = 5vlx50t
-- C_PACKAGE = ff1136
-- C_SPEEDGRADE = -2
----------------------------------------
-- C_EXTRA_MMCM_FOR_DESKEW =
-- C_MMCMExtra_CLKIN_FREQ =
-- C_MMCMExtra_CLKOUT0 =
-- C_MMCMExtra_CLKOUT1 =
-- C_MMCMExtra_CLKOUT2 =
-- C_MMCMExtra_CLKOUT3 =
-- C_MMCMExtra_CLKOUT4 =
-- C_MMCMExtra_CLKOUT5 =
-- C_MMCMExtra_CLKOUT6 =
-- C_MMCMExtra_CLKOUT7 =
-- C_MMCMExtra_CLKOUT8 =
-- C_MMCMExtra_CLKOUT9 =
-- C_MMCMExtra_CLKOUT10 =
-- C_MMCMExtra_CLKOUT11 =
-- C_MMCMExtra_CLKOUT12 =
-- C_MMCMExtra_CLKOUT13 =
-- C_MMCMExtra_CLKOUT14 =
-- C_MMCMExtra_CLKOUT15 =
-- C_MMCMExtra_CLKFBOUT_MULT =
-- C_MMCMExtra_DIVCLK_DIVIDE =
-- C_MMCMExtra_CLKOUT0_DIVIDE =
-- C_MMCMExtra_CLKOUT1_DIVIDE =
-- C_MMCMExtra_CLKOUT2_DIVIDE =
-- C_MMCMExtra_CLKOUT3_DIVIDE =
-- C_MMCMExtra_CLKOUT4_DIVIDE =
-- C_MMCMExtra_CLKOUT5_DIVIDE =
-- C_MMCMExtra_CLKOUT6_DIVIDE =
-- C_MMCMExtra_CLKOUT0_BUF =
-- C_MMCMExtra_CLKOUT1_BUF =
-- C_MMCMExtra_CLKOUT2_BUF =
-- C_MMCMExtra_CLKOUT3_BUF =
-- C_MMCMExtra_CLKOUT4_BUF =
-- C_MMCMExtra_CLKOUT5_BUF =
-- C_MMCMExtra_CLKOUT6_BUF =
-- C_MMCMExtra_CLKFBOUT_BUF =
-- C_MMCMExtra_CLKOUT0_PHASE =
-- C_MMCMExtra_CLKOUT1_PHASE =
-- C_MMCMExtra_CLKOUT2_PHASE =
-- C_MMCMExtra_CLKOUT3_PHASE =
-- C_MMCMExtra_CLKOUT4_PHASE =
-- C_MMCMExtra_CLKOUT5_PHASE =
-- C_MMCMExtra_CLKOUT6_PHASE =
----------------------------------------
-- C_CLKIN_FREQ = 100000000
-- C_CLKOUT0_FREQ = 50000000
-- C_CLKOUT0_PHASE = 0
-- C_CLKOUT0_GROUP = NONE
-- C_CLKOUT0_BUF = TRUE
-- C_CLKOUT0_VARIABLE_PHASE = FALSE
-- C_CLKOUT1_FREQ = 0
-- C_CLKOUT1_PHASE = 0
-- C_CLKOUT1_GROUP = NONE
-- C_CLKOUT1_BUF = TRUE
-- C_CLKOUT1_VARIABLE_PHASE = FALSE
-- C_CLKOUT2_FREQ = 0
-- C_CLKOUT2_PHASE = 0
-- C_CLKOUT2_GROUP = NONE
-- C_CLKOUT2_BUF = TRUE
-- C_CLKOUT2_VARIABLE_PHASE = FALSE
-- C_CLKOUT3_FREQ = 0
-- C_CLKOUT3_PHASE = 0
-- C_CLKOUT3_GROUP = NONE
-- C_CLKOUT3_BUF = TRUE
-- C_CLKOUT3_VARIABLE_PHASE = FALSE
-- C_CLKOUT4_FREQ = 0
-- C_CLKOUT4_PHASE = 0
-- C_CLKOUT4_GROUP = NONE
-- C_CLKOUT4_BUF = TRUE
-- C_CLKOUT4_VARIABLE_PHASE = FALSE
-- C_CLKOUT5_FREQ = 0
-- C_CLKOUT5_PHASE = 0
-- C_CLKOUT5_GROUP = NONE
-- C_CLKOUT5_BUF = TRUE
-- C_CLKOUT5_VARIABLE_PHASE = FALSE
-- C_CLKOUT6_FREQ = 0
-- C_CLKOUT6_PHASE = 0
-- C_CLKOUT6_GROUP = NONE
-- C_CLKOUT6_BUF = TRUE
-- C_CLKOUT6_VARIABLE_PHASE = FALSE
-- C_CLKOUT7_FREQ = 0
-- C_CLKOUT7_PHASE = 0
-- C_CLKOUT7_GROUP = NONE
-- C_CLKOUT7_BUF = TRUE
-- C_CLKOUT7_VARIABLE_PHASE = FALSE
-- C_CLKOUT8_FREQ = 0
-- C_CLKOUT8_PHASE = 0
-- C_CLKOUT8_GROUP = NONE
-- C_CLKOUT8_BUF = TRUE
-- C_CLKOUT8_VARIABLE_PHASE = FALSE
-- C_CLKOUT9_FREQ = 0
-- C_CLKOUT9_PHASE = 0
-- C_CLKOUT9_GROUP = NONE
-- C_CLKOUT9_BUF = TRUE
-- C_CLKOUT9_VARIABLE_PHASE = FALSE
-- C_CLKOUT10_FREQ = 0
-- C_CLKOUT10_PHASE = 0
-- C_CLKOUT10_GROUP = NONE
-- C_CLKOUT10_BUF = TRUE
-- C_CLKOUT10_VARIABLE_PHASE = FALSE
-- C_CLKOUT11_FREQ = 0
-- C_CLKOUT11_PHASE = 0
-- C_CLKOUT11_GROUP = NONE
-- C_CLKOUT11_BUF = TRUE
-- C_CLKOUT11_VARIABLE_PHASE = FALSE
-- C_CLKOUT12_FREQ = 0
-- C_CLKOUT12_PHASE = 0
-- C_CLKOUT12_GROUP = NONE
-- C_CLKOUT12_BUF = TRUE
-- C_CLKOUT12_VARIABLE_PHASE = FALSE
-- C_CLKOUT13_FREQ = 0
-- C_CLKOUT13_PHASE = 0
-- C_CLKOUT13_GROUP = NONE
-- C_CLKOUT13_BUF = TRUE
-- C_CLKOUT13_VARIABLE_PHASE = FALSE
-- C_CLKOUT14_FREQ = 0
-- C_CLKOUT14_PHASE = 0
-- C_CLKOUT14_GROUP = NONE
-- C_CLKOUT14_BUF = TRUE
-- C_CLKOUT14_VARIABLE_PHASE = FALSE
-- C_CLKOUT15_FREQ = 0
-- C_CLKOUT15_PHASE = 0
-- C_CLKOUT15_GROUP = NONE
-- C_CLKOUT15_BUF = TRUE
-- C_CLKOUT15_VARIABLE_PHASE = FALSE
----------------------------------------
-- C_CLKFBIN_FREQ = 0
-- C_CLKFBIN_DESKEW = NONE
-- C_CLKFBOUT_FREQ = 0
-- C_CLKFBOUT_GROUP = NONE
-- C_CLKFBOUT_BUF = TRUE
----------------------------------------
-- C_PSDONE_GROUP = NONE
------------------------------------------------------------------------------
-- Low level parameters
------------------------------------------------------------------------------
-- C_CLKOUT0_MODULE = PLL0
-- C_CLKOUT0_PORT = CLKOUT0B
-- C_CLKOUT1_MODULE = NONE
-- C_CLKOUT1_PORT = NONE
-- C_CLKOUT2_MODULE = NONE
-- C_CLKOUT2_PORT = NONE
-- C_CLKOUT3_MODULE = NONE
-- C_CLKOUT3_PORT = NONE
-- C_CLKOUT4_MODULE = NONE
-- C_CLKOUT4_PORT = NONE
-- C_CLKOUT5_MODULE = NONE
-- C_CLKOUT5_PORT = NONE
-- C_CLKOUT6_MODULE = NONE
-- C_CLKOUT6_PORT = NONE
-- C_CLKOUT7_MODULE = NONE
-- C_CLKOUT7_PORT = NONE
-- C_CLKOUT8_MODULE = NONE
-- C_CLKOUT8_PORT = NONE
-- C_CLKOUT9_MODULE = NONE
-- C_CLKOUT9_PORT = NONE
-- C_CLKOUT10_MODULE = NONE
-- C_CLKOUT10_PORT = NONE
-- C_CLKOUT11_MODULE = NONE
-- C_CLKOUT11_PORT = NONE
-- C_CLKOUT12_MODULE = NONE
-- C_CLKOUT12_PORT = NONE
-- C_CLKOUT13_MODULE = NONE
-- C_CLKOUT13_PORT = NONE
-- C_CLKOUT14_MODULE = NONE
-- C_CLKOUT14_PORT = NONE
-- C_CLKOUT15_MODULE = NONE
-- C_CLKOUT15_PORT = NONE
----------------------------------------
-- C_CLKFBOUT_MODULE = NONE
-- C_CLKFBOUT_PORT = NONE
-- C_CLKFBOUT_get_clkgen_dcm_default_params = NONE
----------------------------------------
-- C_PSDONE_MODULE = NONE
----------------------------------------
-- C_DCM0_DFS_FREQUENCY_MODE = "LOW"
-- C_DCM0_DLL_FREQUENCY_MODE = "LOW"
-- C_DCM0_DUTY_CYCLE_CORRECTION = true
-- C_DCM0_CLKIN_DIVIDE_BY_2 = false
-- C_DCM0_CLK_FEEDBACK = "1X"
-- C_DCM0_CLKOUT_PHASE_SHIFT = "NONE"
-- C_DCM0_DSS_MODE = "NONE"
-- C_DCM0_STARTUP_WAIT = false
-- C_DCM0_PHASE_SHIFT = 0
-- C_DCM0_CLKFX_MULTIPLY = 4
-- C_DCM0_CLKFX_DIVIDE = 1
-- C_DCM0_CLKDV_DIVIDE = 2.0
-- C_DCM0_CLKIN_PERIOD = 41.6666666
-- C_DCM0_DESKEW_ADJUST = "SYSTEM_SYNCHRONOUS"
-- C_DCM0_CLKIN_BUF = false
-- C_DCM0_CLKFB_BUF = false
-- C_DCM0_CLK0_BUF = false
-- C_DCM0_CLK90_BUF = false
-- C_DCM0_CLK180_BUF = false
-- C_DCM0_CLK270_BUF = false
-- C_DCM0_CLKDV_BUF = false
-- C_DCM0_CLK2X_BUF = false
-- C_DCM0_CLK2X180_BUF = false
-- C_DCM0_CLKFX_BUF = false
-- C_DCM0_CLKFX180_BUF = false
-- C_DCM0_EXT_RESET_HIGH = 1
-- C_DCM0_FAMILY = "virtex5"
-- C_DCM0_CLKIN_MODULE = NONE
-- C_DCM0_CLKIN_PORT = NONE
-- C_DCM0_CLKFB_MODULE = NONE
-- C_DCM0_CLKFB_PORT = NONE
-- C_DCM0_RST_MODULE = NONE
-- C_DCM1_DFS_FREQUENCY_MODE = "LOW"
-- C_DCM1_DLL_FREQUENCY_MODE = "LOW"
-- C_DCM1_DUTY_CYCLE_CORRECTION = true
-- C_DCM1_CLKIN_DIVIDE_BY_2 = false
-- C_DCM1_CLK_FEEDBACK = "1X"
-- C_DCM1_CLKOUT_PHASE_SHIFT = "NONE"
-- C_DCM1_DSS_MODE = "NONE"
-- C_DCM1_STARTUP_WAIT = false
-- C_DCM1_PHASE_SHIFT = 0
-- C_DCM1_CLKFX_MULTIPLY = 4
-- C_DCM1_CLKFX_DIVIDE = 1
-- C_DCM1_CLKDV_DIVIDE = 2.0
-- C_DCM1_CLKIN_PERIOD = 41.6666666
-- C_DCM1_DESKEW_ADJUST = "SYSTEM_SYNCHRONOUS"
-- C_DCM1_CLKIN_BUF = false
-- C_DCM1_CLKFB_BUF = false
-- C_DCM1_CLK0_BUF = false
-- C_DCM1_CLK90_BUF = false
-- C_DCM1_CLK180_BUF = false
-- C_DCM1_CLK270_BUF = false
-- C_DCM1_CLKDV_BUF = false
-- C_DCM1_CLK2X_BUF = false
-- C_DCM1_CLK2X180_BUF = false
-- C_DCM1_CLKFX_BUF = false
-- C_DCM1_CLKFX180_BUF = false
-- C_DCM1_EXT_RESET_HIGH = 1
-- C_DCM1_FAMILY = "virtex5"
-- C_DCM1_CLKIN_MODULE = NONE
-- C_DCM1_CLKIN_PORT = NONE
-- C_DCM1_CLKFB_MODULE = NONE
-- C_DCM1_CLKFB_PORT = NONE
-- C_DCM1_RST_MODULE = NONE
-- C_DCM2_DFS_FREQUENCY_MODE = "LOW"
-- C_DCM2_DLL_FREQUENCY_MODE = "LOW"
-- C_DCM2_DUTY_CYCLE_CORRECTION = true
-- C_DCM2_CLKIN_DIVIDE_BY_2 = false
-- C_DCM2_CLK_FEEDBACK = "1X"
-- C_DCM2_CLKOUT_PHASE_SHIFT = "NONE"
-- C_DCM2_DSS_MODE = "NONE"
-- C_DCM2_STARTUP_WAIT = false
-- C_DCM2_PHASE_SHIFT = 0
-- C_DCM2_CLKFX_MULTIPLY = 4
-- C_DCM2_CLKFX_DIVIDE = 1
-- C_DCM2_CLKDV_DIVIDE = 2.0
-- C_DCM2_CLKIN_PERIOD = 41.6666666
-- C_DCM2_DESKEW_ADJUST = "SYSTEM_SYNCHRONOUS"
-- C_DCM2_CLKIN_BUF = false
-- C_DCM2_CLKFB_BUF = false
-- C_DCM2_CLK0_BUF = false
-- C_DCM2_CLK90_BUF = false
-- C_DCM2_CLK180_BUF = false
-- C_DCM2_CLK270_BUF = false
-- C_DCM2_CLKDV_BUF = false
-- C_DCM2_CLK2X_BUF = false
-- C_DCM2_CLK2X180_BUF = false
-- C_DCM2_CLKFX_BUF = false
-- C_DCM2_CLKFX180_BUF = false
-- C_DCM2_EXT_RESET_HIGH = 1
-- C_DCM2_FAMILY = "virtex5"
-- C_DCM2_CLKIN_MODULE = NONE
-- C_DCM2_CLKIN_PORT = NONE
-- C_DCM2_CLKFB_MODULE = NONE
-- C_DCM2_CLKFB_PORT = NONE
-- C_DCM2_RST_MODULE = NONE
-- C_DCM3_DFS_FREQUENCY_MODE = "LOW"
-- C_DCM3_DLL_FREQUENCY_MODE = "LOW"
-- C_DCM3_DUTY_CYCLE_CORRECTION = true
-- C_DCM3_CLKIN_DIVIDE_BY_2 = false
-- C_DCM3_CLK_FEEDBACK = "1X"
-- C_DCM3_CLKOUT_PHASE_SHIFT = "NONE"
-- C_DCM3_DSS_MODE = "NONE"
-- C_DCM3_STARTUP_WAIT = false
-- C_DCM3_PHASE_SHIFT = 0
-- C_DCM3_CLKFX_MULTIPLY = 4
-- C_DCM3_CLKFX_DIVIDE = 1
-- C_DCM3_CLKDV_DIVIDE = 2.0
-- C_DCM3_CLKIN_PERIOD = 41.6666666
-- C_DCM3_DESKEW_ADJUST = "SYSTEM_SYNCHRONOUS"
-- C_DCM3_CLKIN_BUF = false
-- C_DCM3_CLKFB_BUF = false
-- C_DCM3_CLK0_BUF = false
-- C_DCM3_CLK90_BUF = false
-- C_DCM3_CLK180_BUF = false
-- C_DCM3_CLK270_BUF = false
-- C_DCM3_CLKDV_BUF = false
-- C_DCM3_CLK2X_BUF = false
-- C_DCM3_CLK2X180_BUF = false
-- C_DCM3_CLKFX_BUF = false
-- C_DCM3_CLKFX180_BUF = false
-- C_DCM3_EXT_RESET_HIGH = 1
-- C_DCM3_FAMILY = "virtex5"
-- C_DCM3_CLKIN_MODULE = NONE
-- C_DCM3_CLKIN_PORT = NONE
-- C_DCM3_CLKFB_MODULE = NONE
-- C_DCM3_CLKFB_PORT = NONE
-- C_DCM3_RST_MODULE = NONE
----------------------------------------
-- C_PLL0_BANDWIDTH = "OPTIMIZED"
-- C_PLL0_CLKFBOUT_MULT = 12
-- C_PLL0_CLKFBOUT_PHASE = 0.0
-- C_PLL0_CLKIN1_PERIOD = 10.000000
-- C_PLL0_CLKOUT0_DIVIDE = 24
-- C_PLL0_CLKOUT0_DUTY_CYCLE = 0.5
-- C_PLL0_CLKOUT0_PHASE = 0.0000
-- C_PLL0_CLKOUT1_DIVIDE = 1
-- C_PLL0_CLKOUT1_DUTY_CYCLE = 0.5
-- C_PLL0_CLKOUT1_PHASE = 0.0
-- C_PLL0_CLKOUT2_DIVIDE = 1
-- C_PLL0_CLKOUT2_DUTY_CYCLE = 0.5
-- C_PLL0_CLKOUT2_PHASE = 0.0
-- C_PLL0_CLKOUT3_DIVIDE = 1
-- C_PLL0_CLKOUT3_DUTY_CYCLE = 0.5
-- C_PLL0_CLKOUT3_PHASE = 0.0
-- C_PLL0_CLKOUT4_DIVIDE = 1
-- C_PLL0_CLKOUT4_DUTY_CYCLE = 0.5
-- C_PLL0_CLKOUT4_PHASE = 0.0
-- C_PLL0_CLKOUT5_DIVIDE = 1
-- C_PLL0_CLKOUT5_DUTY_CYCLE = 0.5
-- C_PLL0_CLKOUT5_PHASE = 0.0
-- C_PLL0_COMPENSATION = "SYSTEM_SYNCHRONOUS"
-- C_PLL0_DIVCLK_DIVIDE = 1
-- C_PLL0_REF_JITTER = 0.100
-- C_PLL0_RESET_ON_LOSS_OF_LOCK = false
-- C_PLL0_RST_DEASSERT_CLK = "CLKIN1"
-- C_PLL0_CLKOUT0_DESKEW_ADJUST = "NONE"
-- C_PLL0_CLKOUT1_DESKEW_ADJUST = "NONE"
-- C_PLL0_CLKOUT2_DESKEW_ADJUST = "NONE"
-- C_PLL0_CLKOUT3_DESKEW_ADJUST = "NONE"
-- C_PLL0_CLKOUT4_DESKEW_ADJUST = "NONE"
-- C_PLL0_CLKOUT5_DESKEW_ADJUST = "NONE"
-- C_PLL0_CLKFBOUT_DESKEW_ADJUST = "NONE"
-- C_PLL0_CLKIN1_BUF = false
-- C_PLL0_CLKFBOUT_BUF = TRUE
-- C_PLL0_CLKOUT0_BUF = TRUE
-- C_PLL0_CLKOUT1_BUF = false
-- C_PLL0_CLKOUT2_BUF = false
-- C_PLL0_CLKOUT3_BUF = false
-- C_PLL0_CLKOUT4_BUF = false
-- C_PLL0_CLKOUT5_BUF = false
-- C_PLL0_EXT_RESET_HIGH = 0
-- C_PLL0_FAMILY = "virtex5"
-- C_PLL0_CLKIN1_MODULE = CLKGEN
-- C_PLL0_CLKIN1_PORT = CLKIN
-- C_PLL0_CLKFBIN_MODULE = PLL0
-- C_PLL0_CLKFBIN_PORT = CLKFBOUT
-- C_PLL0_RST_MODULE = CLKGEN
-- C_PLL1_BANDWIDTH = "OPTIMIZED"
-- C_PLL1_CLKFBOUT_MULT = 1
-- C_PLL1_CLKFBOUT_PHASE = 0.0
-- C_PLL1_CLKIN1_PERIOD = 0.000
-- C_PLL1_CLKOUT0_DIVIDE = 1
-- C_PLL1_CLKOUT0_DUTY_CYCLE = 0.5
-- C_PLL1_CLKOUT0_PHASE = 0.0
-- C_PLL1_CLKOUT1_DIVIDE = 1
-- C_PLL1_CLKOUT1_DUTY_CYCLE = 0.5
-- C_PLL1_CLKOUT1_PHASE = 0.0
-- C_PLL1_CLKOUT2_DIVIDE = 1
-- C_PLL1_CLKOUT2_DUTY_CYCLE = 0.5
-- C_PLL1_CLKOUT2_PHASE = 0.0
-- C_PLL1_CLKOUT3_DIVIDE = 1
-- C_PLL1_CLKOUT3_DUTY_CYCLE = 0.5
-- C_PLL1_CLKOUT3_PHASE = 0.0
-- C_PLL1_CLKOUT4_DIVIDE = 1
-- C_PLL1_CLKOUT4_DUTY_CYCLE = 0.5
-- C_PLL1_CLKOUT4_PHASE = 0.0
-- C_PLL1_CLKOUT5_DIVIDE = 1
-- C_PLL1_CLKOUT5_DUTY_CYCLE = 0.5
-- C_PLL1_CLKOUT5_PHASE = 0.0
-- C_PLL1_COMPENSATION = "SYSTEM_SYNCHRONOUS"
-- C_PLL1_DIVCLK_DIVIDE = 1
-- C_PLL1_REF_JITTER = 0.100
-- C_PLL1_RESET_ON_LOSS_OF_LOCK = false
-- C_PLL1_RST_DEASSERT_CLK = "CLKIN1"
-- C_PLL1_CLKOUT0_DESKEW_ADJUST = "NONE"
-- C_PLL1_CLKOUT1_DESKEW_ADJUST = "NONE"
-- C_PLL1_CLKOUT2_DESKEW_ADJUST = "NONE"
-- C_PLL1_CLKOUT3_DESKEW_ADJUST = "NONE"
-- C_PLL1_CLKOUT4_DESKEW_ADJUST = "NONE"
-- C_PLL1_CLKOUT5_DESKEW_ADJUST = "NONE"
-- C_PLL1_CLKFBOUT_DESKEW_ADJUST = "NONE"
-- C_PLL1_CLKIN1_BUF = false
-- C_PLL1_CLKFBOUT_BUF = false
-- C_PLL1_CLKOUT0_BUF = false
-- C_PLL1_CLKOUT1_BUF = false
-- C_PLL1_CLKOUT2_BUF = false
-- C_PLL1_CLKOUT3_BUF = false
-- C_PLL1_CLKOUT4_BUF = false
-- C_PLL1_CLKOUT5_BUF = false
-- C_PLL1_EXT_RESET_HIGH = 1
-- C_PLL1_FAMILY = "virtex5"
-- C_PLL1_CLKIN1_MODULE = NONE
-- C_PLL1_CLKIN1_PORT = NONE
-- C_PLL1_CLKFBIN_MODULE = NONE
-- C_PLL1_CLKFBIN_PORT = NONE
-- C_PLL1_RST_MODULE = NONE
----------------------------------------
-- C_MMCM0_BANDWIDTH = "OPTIMIZED"
-- C_MMCM0_CLKFBOUT_MULT_F = 1.0
-- C_MMCM0_CLKFBOUT_PHASE = 0.0
-- C_MMCM0_CLKFBOUT_USE_FINE_PS = false
-- C_MMCM0_CLKIN1_PERIOD = 0.000
-- C_MMCM0_CLKOUT0_DIVIDE_F = 1.0
-- C_MMCM0_CLKOUT0_DUTY_CYCLE = 0.5
-- C_MMCM0_CLKOUT0_PHASE = 0.0
-- C_MMCM0_CLKOUT1_DIVIDE = 1
-- C_MMCM0_CLKOUT1_DUTY_CYCLE = 0.5
-- C_MMCM0_CLKOUT1_PHASE = 0.0
-- C_MMCM0_CLKOUT2_DIVIDE = 1
-- C_MMCM0_CLKOUT2_DUTY_CYCLE = 0.5
-- C_MMCM0_CLKOUT2_PHASE = 0.0
-- C_MMCM0_CLKOUT3_DIVIDE = 1
-- C_MMCM0_CLKOUT3_DUTY_CYCLE = 0.5
-- C_MMCM0_CLKOUT3_PHASE = 0.0
-- C_MMCM0_CLKOUT4_DIVIDE = 1
-- C_MMCM0_CLKOUT4_DUTY_CYCLE = 0.5
-- C_MMCM0_CLKOUT4_PHASE = 0.0
-- C_MMCM0_CLKOUT4_CASCADE = false
-- C_MMCM0_CLKOUT5_DIVIDE = 1
-- C_MMCM0_CLKOUT5_DUTY_CYCLE = 0.5
-- C_MMCM0_CLKOUT5_PHASE = 0.0
-- C_MMCM0_CLKOUT6_DIVIDE = 1
-- C_MMCM0_CLKOUT6_DUTY_CYCLE = 0.5
-- C_MMCM0_CLKOUT6_PHASE = 0.0
-- C_MMCM0_CLKOUT0_USE_FINE_PS = false
-- C_MMCM0_CLKOUT1_USE_FINE_PS = false
-- C_MMCM0_CLKOUT2_USE_FINE_PS = false
-- C_MMCM0_CLKOUT3_USE_FINE_PS = false
-- C_MMCM0_CLKOUT4_USE_FINE_PS = false
-- C_MMCM0_CLKOUT5_USE_FINE_PS = false
-- C_MMCM0_CLKOUT6_USE_FINE_PS = false
-- C_MMCM0_COMPENSATION = "ZHOLD"
-- C_MMCM0_DIVCLK_DIVIDE = 1
-- C_MMCM0_REF_JITTER1 = 0.010
-- C_MMCM0_CLKIN1_BUF = false
-- C_MMCM0_CLKFBOUT_BUF = false
-- C_MMCM0_CLKOUT0_BUF = false
-- C_MMCM0_CLKOUT1_BUF = false
-- C_MMCM0_CLKOUT2_BUF = false
-- C_MMCM0_CLKOUT3_BUF = false
-- C_MMCM0_CLKOUT4_BUF = false
-- C_MMCM0_CLKOUT5_BUF = false
-- C_MMCM0_CLKOUT6_BUF = false
-- C_MMCM0_CLOCK_HOLD = false
-- C_MMCM0_STARTUP_WAIT = false
-- C_MMCM0_EXT_RESET_HIGH = 1
-- C_MMCM0_FAMILY = "virtex5"
-- C_MMCM0_CLKIN1_MODULE = NONE
-- C_MMCM0_CLKIN1_PORT = NONE
-- C_MMCM0_CLKFBIN_MODULE = NONE
-- C_MMCM0_CLKFBIN_PORT = NONE
-- C_MMCM0_RST_MODULE = NONE
-- C_MMCM1_BANDWIDTH = "OPTIMIZED"
-- C_MMCM1_CLKFBOUT_MULT_F = 1.0
-- C_MMCM1_CLKFBOUT_PHASE = 0.0
-- C_MMCM1_CLKFBOUT_USE_FINE_PS = false
-- C_MMCM1_CLKIN1_PERIOD = 0.000
-- C_MMCM1_CLKOUT0_DIVIDE_F = 1.0
-- C_MMCM1_CLKOUT0_DUTY_CYCLE = 0.5
-- C_MMCM1_CLKOUT0_PHASE = 0.0
-- C_MMCM1_CLKOUT1_DIVIDE = 1
-- C_MMCM1_CLKOUT1_DUTY_CYCLE = 0.5
-- C_MMCM1_CLKOUT1_PHASE = 0.0
-- C_MMCM1_CLKOUT2_DIVIDE = 1
-- C_MMCM1_CLKOUT2_DUTY_CYCLE = 0.5
-- C_MMCM1_CLKOUT2_PHASE = 0.0
-- C_MMCM1_CLKOUT3_DIVIDE = 1
-- C_MMCM1_CLKOUT3_DUTY_CYCLE = 0.5
-- C_MMCM1_CLKOUT3_PHASE = 0.0
-- C_MMCM1_CLKOUT4_DIVIDE = 1
-- C_MMCM1_CLKOUT4_DUTY_CYCLE = 0.5
-- C_MMCM1_CLKOUT4_PHASE = 0.0
-- C_MMCM1_CLKOUT4_CASCADE = false
-- C_MMCM1_CLKOUT5_DIVIDE = 1
-- C_MMCM1_CLKOUT5_DUTY_CYCLE = 0.5
-- C_MMCM1_CLKOUT5_PHASE = 0.0
-- C_MMCM1_CLKOUT6_DIVIDE = 1
-- C_MMCM1_CLKOUT6_DUTY_CYCLE = 0.5
-- C_MMCM1_CLKOUT6_PHASE = 0.0
-- C_MMCM1_CLKOUT0_USE_FINE_PS = false
-- C_MMCM1_CLKOUT1_USE_FINE_PS = false
-- C_MMCM1_CLKOUT2_USE_FINE_PS = false
-- C_MMCM1_CLKOUT3_USE_FINE_PS = false
-- C_MMCM1_CLKOUT4_USE_FINE_PS = false
-- C_MMCM1_CLKOUT5_USE_FINE_PS = false
-- C_MMCM1_CLKOUT6_USE_FINE_PS = false
-- C_MMCM1_COMPENSATION = "ZHOLD"
-- C_MMCM1_DIVCLK_DIVIDE = 1
-- C_MMCM1_REF_JITTER1 = 0.010
-- C_MMCM1_CLKIN1_BUF = false
-- C_MMCM1_CLKFBOUT_BUF = false
-- C_MMCM1_CLKOUT0_BUF = false
-- C_MMCM1_CLKOUT1_BUF = false
-- C_MMCM1_CLKOUT2_BUF = false
-- C_MMCM1_CLKOUT3_BUF = false
-- C_MMCM1_CLKOUT4_BUF = false
-- C_MMCM1_CLKOUT5_BUF = false
-- C_MMCM1_CLKOUT6_BUF = false
-- C_MMCM1_CLOCK_HOLD = false
-- C_MMCM1_STARTUP_WAIT = false
-- C_MMCM1_EXT_RESET_HIGH = 1
-- C_MMCM1_FAMILY = "virtex5"
-- C_MMCM1_CLKIN1_MODULE = NONE
-- C_MMCM1_CLKIN1_PORT = NONE
-- C_MMCM1_CLKFBIN_MODULE = NONE
-- C_MMCM1_CLKFBIN_PORT = NONE
-- C_MMCM1_RST_MODULE = NONE
-- C_MMCM2_BANDWIDTH = "OPTIMIZED"
-- C_MMCM2_CLKFBOUT_MULT_F = 1.0
-- C_MMCM2_CLKFBOUT_PHASE = 0.0
-- C_MMCM2_CLKFBOUT_USE_FINE_PS = false
-- C_MMCM2_CLKIN1_PERIOD = 0.000
-- C_MMCM2_CLKOUT0_DIVIDE_F = 1.0
-- C_MMCM2_CLKOUT0_DUTY_CYCLE = 0.5
-- C_MMCM2_CLKOUT0_PHASE = 0.0
-- C_MMCM2_CLKOUT1_DIVIDE = 1
-- C_MMCM2_CLKOUT1_DUTY_CYCLE = 0.5
-- C_MMCM2_CLKOUT1_PHASE = 0.0
-- C_MMCM2_CLKOUT2_DIVIDE = 1
-- C_MMCM2_CLKOUT2_DUTY_CYCLE = 0.5
-- C_MMCM2_CLKOUT2_PHASE = 0.0
-- C_MMCM2_CLKOUT3_DIVIDE = 1
-- C_MMCM2_CLKOUT3_DUTY_CYCLE = 0.5
-- C_MMCM2_CLKOUT3_PHASE = 0.0
-- C_MMCM2_CLKOUT4_DIVIDE = 1
-- C_MMCM2_CLKOUT4_DUTY_CYCLE = 0.5
-- C_MMCM2_CLKOUT4_PHASE = 0.0
-- C_MMCM2_CLKOUT4_CASCADE = false
-- C_MMCM2_CLKOUT5_DIVIDE = 1
-- C_MMCM2_CLKOUT5_DUTY_CYCLE = 0.5
-- C_MMCM2_CLKOUT5_PHASE = 0.0
-- C_MMCM2_CLKOUT6_DIVIDE = 1
-- C_MMCM2_CLKOUT6_DUTY_CYCLE = 0.5
-- C_MMCM2_CLKOUT6_PHASE = 0.0
-- C_MMCM2_CLKOUT0_USE_FINE_PS = false
-- C_MMCM2_CLKOUT1_USE_FINE_PS = false
-- C_MMCM2_CLKOUT2_USE_FINE_PS = false
-- C_MMCM2_CLKOUT3_USE_FINE_PS = false
-- C_MMCM2_CLKOUT4_USE_FINE_PS = false
-- C_MMCM2_CLKOUT5_USE_FINE_PS = false
-- C_MMCM2_CLKOUT6_USE_FINE_PS = false
-- C_MMCM2_COMPENSATION = "ZHOLD"
-- C_MMCM2_DIVCLK_DIVIDE = 1
-- C_MMCM2_REF_JITTER1 = 0.010
-- C_MMCM2_CLKIN1_BUF = false
-- C_MMCM2_CLKFBOUT_BUF = false
-- C_MMCM2_CLKOUT0_BUF = false
-- C_MMCM2_CLKOUT1_BUF = false
-- C_MMCM2_CLKOUT2_BUF = false
-- C_MMCM2_CLKOUT3_BUF = false
-- C_MMCM2_CLKOUT4_BUF = false
-- C_MMCM2_CLKOUT5_BUF = false
-- C_MMCM2_CLKOUT6_BUF = false
-- C_MMCM2_CLOCK_HOLD = false
-- C_MMCM2_STARTUP_WAIT = false
-- C_MMCM2_EXT_RESET_HIGH = 1
-- C_MMCM2_FAMILY = "virtex5"
-- C_MMCM2_CLKIN1_MODULE = NONE
-- C_MMCM2_CLKIN1_PORT = NONE
-- C_MMCM2_CLKFBIN_MODULE = NONE
-- C_MMCM2_CLKFBIN_PORT = NONE
-- C_MMCM2_RST_MODULE = NONE
-- C_MMCM3_BANDWIDTH = "OPTIMIZED"
-- C_MMCM3_CLKFBOUT_MULT_F = 1.0
-- C_MMCM3_CLKFBOUT_PHASE = 0.0
-- C_MMCM3_CLKFBOUT_USE_FINE_PS = false
-- C_MMCM3_CLKIN1_PERIOD = 0.000
-- C_MMCM3_CLKOUT0_DIVIDE_F = 1.0
-- C_MMCM3_CLKOUT0_DUTY_CYCLE = 0.5
-- C_MMCM3_CLKOUT0_PHASE = 0.0
-- C_MMCM3_CLKOUT1_DIVIDE = 1
-- C_MMCM3_CLKOUT1_DUTY_CYCLE = 0.5
-- C_MMCM3_CLKOUT1_PHASE = 0.0
-- C_MMCM3_CLKOUT2_DIVIDE = 1
-- C_MMCM3_CLKOUT2_DUTY_CYCLE = 0.5
-- C_MMCM3_CLKOUT2_PHASE = 0.0
-- C_MMCM3_CLKOUT3_DIVIDE = 1
-- C_MMCM3_CLKOUT3_DUTY_CYCLE = 0.5
-- C_MMCM3_CLKOUT3_PHASE = 0.0
-- C_MMCM3_CLKOUT4_DIVIDE = 1
-- C_MMCM3_CLKOUT4_DUTY_CYCLE = 0.5
-- C_MMCM3_CLKOUT4_PHASE = 0.0
-- C_MMCM3_CLKOUT4_CASCADE = false
-- C_MMCM3_CLKOUT5_DIVIDE = 1
-- C_MMCM3_CLKOUT5_DUTY_CYCLE = 0.5
-- C_MMCM3_CLKOUT5_PHASE = 0.0
-- C_MMCM3_CLKOUT6_DIVIDE = 1
-- C_MMCM3_CLKOUT6_DUTY_CYCLE = 0.5
-- C_MMCM3_CLKOUT6_PHASE = 0.0
-- C_MMCM3_CLKOUT0_USE_FINE_PS = false
-- C_MMCM3_CLKOUT1_USE_FINE_PS = false
-- C_MMCM3_CLKOUT2_USE_FINE_PS = false
-- C_MMCM3_CLKOUT3_USE_FINE_PS = false
-- C_MMCM3_CLKOUT4_USE_FINE_PS = false
-- C_MMCM3_CLKOUT5_USE_FINE_PS = false
-- C_MMCM3_CLKOUT6_USE_FINE_PS = false
-- C_MMCM3_COMPENSATION = "ZHOLD"
-- C_MMCM3_DIVCLK_DIVIDE = 1
-- C_MMCM3_REF_JITTER1 = 0.010
-- C_MMCM3_CLKIN1_BUF = false
-- C_MMCM3_CLKFBOUT_BUF = false
-- C_MMCM3_CLKOUT0_BUF = false
-- C_MMCM3_CLKOUT1_BUF = false
-- C_MMCM3_CLKOUT2_BUF = false
-- C_MMCM3_CLKOUT3_BUF = false
-- C_MMCM3_CLKOUT4_BUF = false
-- C_MMCM3_CLKOUT5_BUF = false
-- C_MMCM3_CLKOUT6_BUF = false
-- C_MMCM3_CLOCK_HOLD = false
-- C_MMCM3_STARTUP_WAIT = false
-- C_MMCM3_EXT_RESET_HIGH = 1
-- C_MMCM3_FAMILY = "virtex5"
-- C_MMCM3_CLKIN1_MODULE = NONE
-- C_MMCM3_CLKIN1_PORT = NONE
-- C_MMCM3_CLKFBIN_MODULE = NONE
-- C_MMCM3_CLKFBIN_PORT = NONE
-- C_MMCM3_RST_MODULE = NONE
----------------------------------------
-- C_PLLE0_BANDWIDTH = "OPTIMIZED"
-- C_PLLE0_CLKFBOUT_MULT = 1
-- C_PLLE0_CLKFBOUT_PHASE = 0.0
-- C_PLLE0_CLKIN1_PERIOD = 0.000
-- C_PLLE0_CLKOUT0_DIVIDE = 1
-- C_PLLE0_CLKOUT0_DUTY_CYCLE = 0.5
-- C_PLLE0_CLKOUT0_PHASE = 0.0
-- C_PLLE0_CLKOUT1_DIVIDE = 1
-- C_PLLE0_CLKOUT1_DUTY_CYCLE = 0.5
-- C_PLLE0_CLKOUT1_PHASE = 0.0
-- C_PLLE0_CLKOUT2_DIVIDE = 1
-- C_PLLE0_CLKOUT2_DUTY_CYCLE = 0.5
-- C_PLLE0_CLKOUT2_PHASE = 0.0
-- C_PLLE0_CLKOUT3_DIVIDE = 1
-- C_PLLE0_CLKOUT3_DUTY_CYCLE = 0.5
-- C_PLLE0_CLKOUT3_PHASE = 0.0
-- C_PLLE0_CLKOUT4_DIVIDE = 1
-- C_PLLE0_CLKOUT4_DUTY_CYCLE = 0.5
-- C_PLLE0_CLKOUT4_PHASE = 0.0
-- C_PLLE0_CLKOUT5_DIVIDE = 1
-- C_PLLE0_CLKOUT5_DUTY_CYCLE = 0.5
-- C_PLLE0_CLKOUT5_PHASE = 0.0
-- C_PLLE0_COMPENSATION = "ZHOLD"
-- C_PLLE0_DIVCLK_DIVIDE = 1
-- C_PLLE0_REF_JITTER1 = 0.010
-- C_PLLE0_CLKIN1_BUF = false
-- C_PLLE0_CLKFBOUT_BUF = false
-- C_PLLE0_CLKOUT0_BUF = false
-- C_PLLE0_CLKOUT1_BUF = false
-- C_PLLE0_CLKOUT2_BUF = false
-- C_PLLE0_CLKOUT3_BUF = false
-- C_PLLE0_CLKOUT4_BUF = false
-- C_PLLE0_CLKOUT5_BUF = false
-- C_PLLE0_STARTUP_WAIT = "false"
-- C_PLLE0_EXT_RESET_HIGH = 1
-- C_PLLE0_FAMILY = "virtex7"
-- C_PLLE0_CLKIN1_MODULE = NONE
-- C_PLLE0_CLKIN1_PORT = NONE
-- C_PLLE0_CLKFBIN_MODULE = NONE
-- C_PLLE0_CLKFBIN_PORT = NONE
-- C_PLLE0_RST_MODULE = NONE
----------------------------------------
| lgpl-3.0 | 011fbc32ac6c541539e96d118dfd6673 | 0.551954 | 2.94692 | false | false | false | false |
grwlf/vsim | vhdl_ct/ct00093.vhd | 1 | 11,427 | -- NEED RESULT: ARCH00093.P1: Multi transport transactions occurred on signal asg with selected name on LHS passed
-- NEED RESULT: ARCH00093.P2: Multi transport transactions occurred on signal asg with selected name on LHS passed
-- NEED RESULT: ARCH00093.P3: Multi transport transactions occurred on signal asg with selected name on LHS passed
-- NEED RESULT: ARCH00093: One transport transaction occurred on signal asg with selected name on LHS passed
-- NEED RESULT: ARCH00093: Old transactions were removed on signal asg with selected name on LHS passed
-- NEED RESULT: ARCH00093: One transport transaction occurred on signal asg with selected name on LHS passed
-- NEED RESULT: ARCH00093: Old transactions were removed on signal asg with selected name on LHS passed
-- NEED RESULT: ARCH00093: One transport transaction occurred on signal asg with selected name on LHS passed
-- NEED RESULT: ARCH00093: Old transactions were removed on signal asg with selected name on LHS passed
-- NEED RESULT: P3: Transport transactions entirely completed passed
-- NEED RESULT: P2: Transport transactions entirely completed passed
-- NEED RESULT: P1: Transport transactions entirely completed passed
-------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
-------------------------------------------------------------------------------
--
-- TEST NAME:
--
-- CT00093
--
-- AUTHOR:
--
-- G. Tominovich
--
-- TEST OBJECTIVES:
--
-- 8.3 (2)
-- 8.3 (3)
-- 8.3 (5)
-- 8.3.1 (3)
--
-- DESIGN UNIT ORDERING:
--
-- ENT00093(ARCH00093)
-- ENT00093_Test_Bench(ARCH00093_Test_Bench)
--
-- REVISION HISTORY:
--
-- 07-JUL-1987 - initial revision
--
-- NOTES:
--
-- self-checking
-- automatically generated
--
use WORK.STANDARD_TYPES.all ;
entity ENT00093 is
port (
s_st_rec1 : inout st_rec1
; s_st_rec2 : inout st_rec2
; s_st_rec3 : inout st_rec3
) ;
subtype chk_sig_type is integer range -1 to 100 ;
signal chk_st_rec1 : chk_sig_type := -1 ;
signal chk_st_rec2 : chk_sig_type := -1 ;
signal chk_st_rec3 : chk_sig_type := -1 ;
--
end ENT00093 ;
--
architecture ARCH00093 of ENT00093 is
begin
PGEN_CHKP_1 :
process ( chk_st_rec1 )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P1" ,
"Transport transactions entirely completed",
chk_st_rec1 = 4 ) ;
end if ;
end process PGEN_CHKP_1 ;
--
P1 :
process ( s_st_rec1 )
variable correct : boolean ;
variable counter : integer := 0 ;
variable savtime : time ;
--
procedure Proc1 is
begin
case counter is
when 0
=> s_st_rec1.f2 <= transport
c_st_rec1_2.f2 after 10 ns,
c_st_rec1_1.f2 after 20 ns ;
--
when 1
=> correct :=
s_st_rec1.f2 = c_st_rec1_2.f2 and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_rec1.f2 = c_st_rec1_1.f2 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00093.P1" ,
"Multi transport transactions occurred on signal " &
"asg with selected name on LHS",
correct ) ;
s_st_rec1.f2 <= transport
c_st_rec1_2.f2 after 10 ns ,
c_st_rec1_1.f2 after 20 ns ,
c_st_rec1_2.f2 after 30 ns ,
c_st_rec1_1.f2 after 40 ns ;
--
when 3
=> correct :=
s_st_rec1.f2 = c_st_rec1_2.f2 and
(savtime + 10 ns) = Std.Standard.Now ;
s_st_rec1.f2 <= transport c_st_rec1_1.f2 after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_rec1.f2 = c_st_rec1_1.f2 and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00093" ,
"One transport transaction occurred on signal " &
"asg with selected name on LHS",
correct ) ;
test_report ( "ARCH00093" ,
"Old transactions were removed on signal " &
"asg with selected name on LHS",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00093" ,
"Old transactions were removed on signal " &
"asg with selected name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_st_rec1 <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
end Proc1 ;
--
begin
Proc1 ;
end process P1 ;
--
PGEN_CHKP_2 :
process ( chk_st_rec2 )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P2" ,
"Transport transactions entirely completed",
chk_st_rec2 = 4 ) ;
end if ;
end process PGEN_CHKP_2 ;
--
P2 :
process ( s_st_rec2 )
variable correct : boolean ;
variable counter : integer := 0 ;
variable savtime : time ;
--
procedure Proc1 is
begin
case counter is
when 0
=> s_st_rec2.f2 <= transport
c_st_rec2_2.f2 after 10 ns,
c_st_rec2_1.f2 after 20 ns ;
--
when 1
=> correct :=
s_st_rec2.f2 = c_st_rec2_2.f2 and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_rec2.f2 = c_st_rec2_1.f2 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00093.P2" ,
"Multi transport transactions occurred on signal " &
"asg with selected name on LHS",
correct ) ;
s_st_rec2.f2 <= transport
c_st_rec2_2.f2 after 10 ns ,
c_st_rec2_1.f2 after 20 ns ,
c_st_rec2_2.f2 after 30 ns ,
c_st_rec2_1.f2 after 40 ns ;
--
when 3
=> correct :=
s_st_rec2.f2 = c_st_rec2_2.f2 and
(savtime + 10 ns) = Std.Standard.Now ;
s_st_rec2.f2 <= transport c_st_rec2_1.f2 after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_rec2.f2 = c_st_rec2_1.f2 and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00093" ,
"One transport transaction occurred on signal " &
"asg with selected name on LHS",
correct ) ;
test_report ( "ARCH00093" ,
"Old transactions were removed on signal " &
"asg with selected name on LHS",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00093" ,
"Old transactions were removed on signal " &
"asg with selected name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_st_rec2 <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
end Proc1 ;
--
begin
Proc1 ;
end process P2 ;
--
PGEN_CHKP_3 :
process ( chk_st_rec3 )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P3" ,
"Transport transactions entirely completed",
chk_st_rec3 = 4 ) ;
end if ;
end process PGEN_CHKP_3 ;
--
P3 :
process ( s_st_rec3 )
variable correct : boolean ;
variable counter : integer := 0 ;
variable savtime : time ;
--
procedure Proc1 is
begin
case counter is
when 0
=> s_st_rec3.f2 <= transport
c_st_rec3_2.f2 after 10 ns,
c_st_rec3_1.f2 after 20 ns ;
--
when 1
=> correct :=
s_st_rec3.f2 = c_st_rec3_2.f2 and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_rec3.f2 = c_st_rec3_1.f2 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00093.P3" ,
"Multi transport transactions occurred on signal " &
"asg with selected name on LHS",
correct ) ;
s_st_rec3.f2 <= transport
c_st_rec3_2.f2 after 10 ns ,
c_st_rec3_1.f2 after 20 ns ,
c_st_rec3_2.f2 after 30 ns ,
c_st_rec3_1.f2 after 40 ns ;
--
when 3
=> correct :=
s_st_rec3.f2 = c_st_rec3_2.f2 and
(savtime + 10 ns) = Std.Standard.Now ;
s_st_rec3.f2 <= transport c_st_rec3_1.f2 after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_rec3.f2 = c_st_rec3_1.f2 and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00093" ,
"One transport transaction occurred on signal " &
"asg with selected name on LHS",
correct ) ;
test_report ( "ARCH00093" ,
"Old transactions were removed on signal " &
"asg with selected name on LHS",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00093" ,
"Old transactions were removed on signal " &
"asg with selected name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_st_rec3 <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
end Proc1 ;
--
begin
Proc1 ;
end process P3 ;
--
--
end ARCH00093 ;
--
use WORK.STANDARD_TYPES.all ;
entity ENT00093_Test_Bench is
signal s_st_rec1 : st_rec1
:= c_st_rec1_1 ;
signal s_st_rec2 : st_rec2
:= c_st_rec2_1 ;
signal s_st_rec3 : st_rec3
:= c_st_rec3_1 ;
--
end ENT00093_Test_Bench ;
--
architecture ARCH00093_Test_Bench of ENT00093_Test_Bench is
begin
L1:
block
component UUT
port (
s_st_rec1 : inout st_rec1
; s_st_rec2 : inout st_rec2
; s_st_rec3 : inout st_rec3
) ;
end component ;
--
for CIS1 : UUT use entity WORK.ENT00093 ( ARCH00093 ) ;
begin
CIS1 : UUT
port map (
s_st_rec1
, s_st_rec2
, s_st_rec3
) ;
end block L1 ;
end ARCH00093_Test_Bench ;
| gpl-3.0 | 8667b027ef47ece415f658581f0bc6a1 | 0.482016 | 3.797607 | false | true | false | false |
grwlf/vsim | vhdl_ct/ct00338.vhd | 1 | 65,412 | -- NEED RESULT: ARCH00338.P1: Multi transport transactions occurred on concurrent signal asg passed
-- NEED RESULT: ARCH00338.P2: Multi transport transactions occurred on concurrent signal asg passed
-- NEED RESULT: ARCH00338.P3: Multi transport transactions occurred on concurrent signal asg passed
-- NEED RESULT: ARCH00338.P4: Multi transport transactions occurred on concurrent signal asg passed
-- NEED RESULT: ARCH00338.P5: Multi transport transactions occurred on concurrent signal asg passed
-- NEED RESULT: ARCH00338.P6: Multi transport transactions occurred on concurrent signal asg passed
-- NEED RESULT: ARCH00338.P7: Multi transport transactions occurred on concurrent signal asg passed
-- NEED RESULT: ARCH00338.P8: Multi transport transactions occurred on concurrent signal asg passed
-- NEED RESULT: ARCH00338.P9: Multi transport transactions occurred on concurrent signal asg passed
-- NEED RESULT: ARCH00338.P10: Multi transport transactions occurred on concurrent signal asg passed
-- NEED RESULT: ARCH00338.P11: Multi transport transactions occurred on concurrent signal asg passed
-- NEED RESULT: ARCH00338.P12: Multi transport transactions occurred on concurrent signal asg passed
-- NEED RESULT: ARCH00338.P13: Multi transport transactions occurred on concurrent signal asg passed
-- NEED RESULT: ARCH00338.P14: Multi transport transactions occurred on concurrent signal asg passed
-- NEED RESULT: ARCH00338.P15: Multi transport transactions occurred on concurrent signal asg passed
-- NEED RESULT: ARCH00338.P16: Multi transport transactions occurred on concurrent signal asg passed
-- NEED RESULT: ARCH00338.P17: Multi transport transactions occurred on concurrent signal asg passed
-- NEED RESULT: ARCH00338: One transport transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00338: Old transactions were removed on a concurrent signal asg passed
-- NEED RESULT: ARCH00338: One transport transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00338: Old transactions were removed on a concurrent signal asg passed
-- NEED RESULT: ARCH00338: One transport transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00338: Old transactions were removed on a concurrent signal asg passed
-- NEED RESULT: ARCH00338: One transport transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00338: Old transactions were removed on a concurrent signal asg passed
-- NEED RESULT: ARCH00338: One transport transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00338: Old transactions were removed on a concurrent signal asg passed
-- NEED RESULT: ARCH00338: One transport transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00338: Old transactions were removed on a concurrent signal asg passed
-- NEED RESULT: ARCH00338: One transport transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00338: Old transactions were removed on a concurrent signal asg passed
-- NEED RESULT: ARCH00338: One transport transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00338: Old transactions were removed on a concurrent signal asg passed
-- NEED RESULT: ARCH00338: One transport transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00338: Old transactions were removed on a concurrent signal asg passed
-- NEED RESULT: ARCH00338: One transport transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00338: Old transactions were removed on a concurrent signal asg passed
-- NEED RESULT: ARCH00338: One transport transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00338: Old transactions were removed on a concurrent signal asg passed
-- NEED RESULT: ARCH00338: One transport transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00338: Old transactions were removed on a concurrent signal asg passed
-- NEED RESULT: ARCH00338: One transport transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00338: Old transactions were removed on a concurrent signal asg passed
-- NEED RESULT: ARCH00338: One transport transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00338: Old transactions were removed on a concurrent signal asg passed
-- NEED RESULT: ARCH00338: One transport transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00338: Old transactions were removed on a concurrent signal asg passed
-- NEED RESULT: ARCH00338: One transport transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00338: Old transactions were removed on a concurrent signal asg passed
-- NEED RESULT: ARCH00338: One transport transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00338: Old transactions were removed on a concurrent signal asg passed
-- NEED RESULT: P17: Transport transactions completed entirely passed
-- NEED RESULT: P16: Transport transactions completed entirely passed
-- NEED RESULT: P15: Transport transactions completed entirely passed
-- NEED RESULT: P14: Transport transactions completed entirely passed
-- NEED RESULT: P13: Transport transactions completed entirely passed
-- NEED RESULT: P12: Transport transactions completed entirely passed
-- NEED RESULT: P11: Transport transactions completed entirely passed
-- NEED RESULT: P10: Transport transactions completed entirely passed
-- NEED RESULT: P9: Transport transactions completed entirely passed
-- NEED RESULT: P8: Transport transactions completed entirely passed
-- NEED RESULT: P7: Transport transactions completed entirely passed
-- NEED RESULT: P6: Transport transactions completed entirely passed
-- NEED RESULT: P5: Transport transactions completed entirely passed
-- NEED RESULT: P4: Transport transactions completed entirely passed
-- NEED RESULT: P3: Transport transactions completed entirely passed
-- NEED RESULT: P2: Transport transactions completed entirely passed
-- NEED RESULT: P1: Transport transactions completed entirely passed
-------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
-------------------------------------------------------------------------------
--
-- TEST NAME:
--
-- CT00338
--
-- AUTHOR:
--
-- G. Tominovich
--
-- TEST OBJECTIVES:
--
-- 9.5 (2)
-- 9.5.2 (1)
--
-- DESIGN UNIT ORDERING:
--
-- ENT00338(ARCH00338)
-- ENT00338_Test_Bench(ARCH00338_Test_Bench)
--
-- REVISION HISTORY:
--
-- 30-JUL-1987 - initial revision
--
-- NOTES:
--
-- self-checking
-- automatically generated
--
use WORK.STANDARD_TYPES.all ;
entity ENT00338 is
port (
s_boolean : inout boolean
; s_bit : inout bit
; s_severity_level : inout severity_level
; s_character : inout character
; s_st_enum1 : inout st_enum1
; s_integer : inout integer
; s_st_int1 : inout st_int1
; s_time : inout time
; s_st_phys1 : inout st_phys1
; s_real : inout real
; s_st_real1 : inout st_real1
; s_st_rec1 : inout st_rec1
; s_st_rec2 : inout st_rec2
; s_st_rec3 : inout st_rec3
; s_st_arr1 : inout st_arr1
; s_st_arr2 : inout st_arr2
; s_st_arr3 : inout st_arr3
) ;
subtype chk_sig_type is integer range -1 to 100 ;
signal chk_boolean : chk_sig_type := -1 ;
signal chk_bit : chk_sig_type := -1 ;
signal chk_severity_level : chk_sig_type := -1 ;
signal chk_character : chk_sig_type := -1 ;
signal chk_st_enum1 : chk_sig_type := -1 ;
signal chk_integer : chk_sig_type := -1 ;
signal chk_st_int1 : chk_sig_type := -1 ;
signal chk_time : chk_sig_type := -1 ;
signal chk_st_phys1 : chk_sig_type := -1 ;
signal chk_real : chk_sig_type := -1 ;
signal chk_st_real1 : chk_sig_type := -1 ;
signal chk_st_rec1 : chk_sig_type := -1 ;
signal chk_st_rec2 : chk_sig_type := -1 ;
signal chk_st_rec3 : chk_sig_type := -1 ;
signal chk_st_arr1 : chk_sig_type := -1 ;
signal chk_st_arr2 : chk_sig_type := -1 ;
signal chk_st_arr3 : chk_sig_type := -1 ;
--
end ENT00338 ;
--
--
architecture ARCH00338 of ENT00338 is
subtype chk_time_type is Time ;
signal s_boolean_savt : chk_time_type := 0 ns ;
signal s_bit_savt : chk_time_type := 0 ns ;
signal s_severity_level_savt : chk_time_type := 0 ns ;
signal s_character_savt : chk_time_type := 0 ns ;
signal s_st_enum1_savt : chk_time_type := 0 ns ;
signal s_integer_savt : chk_time_type := 0 ns ;
signal s_st_int1_savt : chk_time_type := 0 ns ;
signal s_time_savt : chk_time_type := 0 ns ;
signal s_st_phys1_savt : chk_time_type := 0 ns ;
signal s_real_savt : chk_time_type := 0 ns ;
signal s_st_real1_savt : chk_time_type := 0 ns ;
signal s_st_rec1_savt : chk_time_type := 0 ns ;
signal s_st_rec2_savt : chk_time_type := 0 ns ;
signal s_st_rec3_savt : chk_time_type := 0 ns ;
signal s_st_arr1_savt : chk_time_type := 0 ns ;
signal s_st_arr2_savt : chk_time_type := 0 ns ;
signal s_st_arr3_savt : chk_time_type := 0 ns ;
--
subtype chk_cnt_type is Integer ;
signal s_boolean_cnt : chk_cnt_type := 0 ;
signal s_bit_cnt : chk_cnt_type := 0 ;
signal s_severity_level_cnt : chk_cnt_type := 0 ;
signal s_character_cnt : chk_cnt_type := 0 ;
signal s_st_enum1_cnt : chk_cnt_type := 0 ;
signal s_integer_cnt : chk_cnt_type := 0 ;
signal s_st_int1_cnt : chk_cnt_type := 0 ;
signal s_time_cnt : chk_cnt_type := 0 ;
signal s_st_phys1_cnt : chk_cnt_type := 0 ;
signal s_real_cnt : chk_cnt_type := 0 ;
signal s_st_real1_cnt : chk_cnt_type := 0 ;
signal s_st_rec1_cnt : chk_cnt_type := 0 ;
signal s_st_rec2_cnt : chk_cnt_type := 0 ;
signal s_st_rec3_cnt : chk_cnt_type := 0 ;
signal s_st_arr1_cnt : chk_cnt_type := 0 ;
signal s_st_arr2_cnt : chk_cnt_type := 0 ;
signal s_st_arr3_cnt : chk_cnt_type := 0 ;
--
type select_type is range 1 to 3 ;
signal boolean_select : select_type := 1 ;
signal bit_select : select_type := 1 ;
signal severity_level_select : select_type := 1 ;
signal character_select : select_type := 1 ;
signal st_enum1_select : select_type := 1 ;
signal integer_select : select_type := 1 ;
signal st_int1_select : select_type := 1 ;
signal time_select : select_type := 1 ;
signal st_phys1_select : select_type := 1 ;
signal real_select : select_type := 1 ;
signal st_real1_select : select_type := 1 ;
signal st_rec1_select : select_type := 1 ;
signal st_rec2_select : select_type := 1 ;
signal st_rec3_select : select_type := 1 ;
signal st_arr1_select : select_type := 1 ;
signal st_arr2_select : select_type := 1 ;
signal st_arr3_select : select_type := 1 ;
--
begin
CHG1 :
process ( s_boolean )
variable correct : boolean ;
begin
case s_boolean_cnt is
when 0
=> null ;
-- s_boolean <= transport
-- c_boolean_2 after 10 ns,
-- c_boolean_1 after 20 ns ;
--
when 1
=> correct :=
s_boolean =
c_boolean_2 and
(s_boolean_savt + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_boolean =
c_boolean_1 and
(s_boolean_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00338.P1" ,
"Multi transport transactions occurred on " &
"concurrent signal asg",
correct ) ;
--
boolean_select <= transport 2 ;
-- s_boolean <= transport
-- c_boolean_2 after 10 ns ,
-- c_boolean_1 after 20 ns ,
-- c_boolean_2 after 30 ns ,
-- c_boolean_1 after 40 ns ;
--
when 3
=> correct :=
s_boolean =
c_boolean_2 and
(s_boolean_savt + 10 ns) = Std.Standard.Now ;
boolean_select <= transport 3 ;
-- s_boolean <= transport
-- c_boolean_1 after 5 ns ;
--
when 4
=> correct :=
correct and
s_boolean =
c_boolean_1 and
(s_boolean_savt + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00338" ,
"One transport transaction occurred on a " &
"concurrent signal asg",
correct ) ;
test_report ( "ARCH00338" ,
"Old transactions were removed on a " &
"concurrent signal asg",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00338" ,
"Old transactions were removed on a " &
"concurrent signal asg",
false ) ;
--
end case ;
--
s_boolean_savt <= transport Std.Standard.Now ;
chk_boolean <= transport s_boolean_cnt
after (1 us - Std.Standard.Now) ;
s_boolean_cnt <= transport s_boolean_cnt + 1 ;
--
end process CHG1 ;
--
PGEN_CHKP_1 :
process ( chk_boolean )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P1" ,
"Transport transactions completed entirely",
chk_boolean = 4 ) ;
end if ;
end process PGEN_CHKP_1 ;
--
--
with boolean_select select
s_boolean <= transport
c_boolean_2 after 10 ns,
c_boolean_1 after 20 ns
when 1,
--
c_boolean_2 after 10 ns ,
c_boolean_1 after 20 ns ,
c_boolean_2 after 30 ns ,
c_boolean_1 after 40 ns
when 2,
--
c_boolean_1 after 5 ns when 3 ;
--
CHG2 :
process ( s_bit )
variable correct : boolean ;
begin
case s_bit_cnt is
when 0
=> null ;
-- s_bit <= transport
-- c_bit_2 after 10 ns,
-- c_bit_1 after 20 ns ;
--
when 1
=> correct :=
s_bit =
c_bit_2 and
(s_bit_savt + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_bit =
c_bit_1 and
(s_bit_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00338.P2" ,
"Multi transport transactions occurred on " &
"concurrent signal asg",
correct ) ;
--
bit_select <= transport 2 ;
-- s_bit <= transport
-- c_bit_2 after 10 ns ,
-- c_bit_1 after 20 ns ,
-- c_bit_2 after 30 ns ,
-- c_bit_1 after 40 ns ;
--
when 3
=> correct :=
s_bit =
c_bit_2 and
(s_bit_savt + 10 ns) = Std.Standard.Now ;
bit_select <= transport 3 ;
-- s_bit <= transport
-- c_bit_1 after 5 ns ;
--
when 4
=> correct :=
correct and
s_bit =
c_bit_1 and
(s_bit_savt + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00338" ,
"One transport transaction occurred on a " &
"concurrent signal asg",
correct ) ;
test_report ( "ARCH00338" ,
"Old transactions were removed on a " &
"concurrent signal asg",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00338" ,
"Old transactions were removed on a " &
"concurrent signal asg",
false ) ;
--
end case ;
--
s_bit_savt <= transport Std.Standard.Now ;
chk_bit <= transport s_bit_cnt
after (1 us - Std.Standard.Now) ;
s_bit_cnt <= transport s_bit_cnt + 1 ;
--
end process CHG2 ;
--
PGEN_CHKP_2 :
process ( chk_bit )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P2" ,
"Transport transactions completed entirely",
chk_bit = 4 ) ;
end if ;
end process PGEN_CHKP_2 ;
--
--
with bit_select select
s_bit <= transport
c_bit_2 after 10 ns,
c_bit_1 after 20 ns
when 1,
--
c_bit_2 after 10 ns ,
c_bit_1 after 20 ns ,
c_bit_2 after 30 ns ,
c_bit_1 after 40 ns
when 2,
--
c_bit_1 after 5 ns when 3 ;
--
CHG3 :
process ( s_severity_level )
variable correct : boolean ;
begin
case s_severity_level_cnt is
when 0
=> null ;
-- s_severity_level <= transport
-- c_severity_level_2 after 10 ns,
-- c_severity_level_1 after 20 ns ;
--
when 1
=> correct :=
s_severity_level =
c_severity_level_2 and
(s_severity_level_savt + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_severity_level =
c_severity_level_1 and
(s_severity_level_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00338.P3" ,
"Multi transport transactions occurred on " &
"concurrent signal asg",
correct ) ;
--
severity_level_select <= transport 2 ;
-- s_severity_level <= transport
-- c_severity_level_2 after 10 ns ,
-- c_severity_level_1 after 20 ns ,
-- c_severity_level_2 after 30 ns ,
-- c_severity_level_1 after 40 ns ;
--
when 3
=> correct :=
s_severity_level =
c_severity_level_2 and
(s_severity_level_savt + 10 ns) = Std.Standard.Now ;
severity_level_select <= transport 3 ;
-- s_severity_level <= transport
-- c_severity_level_1 after 5 ns ;
--
when 4
=> correct :=
correct and
s_severity_level =
c_severity_level_1 and
(s_severity_level_savt + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00338" ,
"One transport transaction occurred on a " &
"concurrent signal asg",
correct ) ;
test_report ( "ARCH00338" ,
"Old transactions were removed on a " &
"concurrent signal asg",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00338" ,
"Old transactions were removed on a " &
"concurrent signal asg",
false ) ;
--
end case ;
--
s_severity_level_savt <= transport Std.Standard.Now ;
chk_severity_level <= transport s_severity_level_cnt
after (1 us - Std.Standard.Now) ;
s_severity_level_cnt <= transport s_severity_level_cnt + 1 ;
--
end process CHG3 ;
--
PGEN_CHKP_3 :
process ( chk_severity_level )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P3" ,
"Transport transactions completed entirely",
chk_severity_level = 4 ) ;
end if ;
end process PGEN_CHKP_3 ;
--
--
with severity_level_select select
s_severity_level <= transport
c_severity_level_2 after 10 ns,
c_severity_level_1 after 20 ns
when 1,
--
c_severity_level_2 after 10 ns ,
c_severity_level_1 after 20 ns ,
c_severity_level_2 after 30 ns ,
c_severity_level_1 after 40 ns
when 2,
--
c_severity_level_1 after 5 ns when 3 ;
--
CHG4 :
process ( s_character )
variable correct : boolean ;
begin
case s_character_cnt is
when 0
=> null ;
-- s_character <= transport
-- c_character_2 after 10 ns,
-- c_character_1 after 20 ns ;
--
when 1
=> correct :=
s_character =
c_character_2 and
(s_character_savt + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_character =
c_character_1 and
(s_character_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00338.P4" ,
"Multi transport transactions occurred on " &
"concurrent signal asg",
correct ) ;
--
character_select <= transport 2 ;
-- s_character <= transport
-- c_character_2 after 10 ns ,
-- c_character_1 after 20 ns ,
-- c_character_2 after 30 ns ,
-- c_character_1 after 40 ns ;
--
when 3
=> correct :=
s_character =
c_character_2 and
(s_character_savt + 10 ns) = Std.Standard.Now ;
character_select <= transport 3 ;
-- s_character <= transport
-- c_character_1 after 5 ns ;
--
when 4
=> correct :=
correct and
s_character =
c_character_1 and
(s_character_savt + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00338" ,
"One transport transaction occurred on a " &
"concurrent signal asg",
correct ) ;
test_report ( "ARCH00338" ,
"Old transactions were removed on a " &
"concurrent signal asg",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00338" ,
"Old transactions were removed on a " &
"concurrent signal asg",
false ) ;
--
end case ;
--
s_character_savt <= transport Std.Standard.Now ;
chk_character <= transport s_character_cnt
after (1 us - Std.Standard.Now) ;
s_character_cnt <= transport s_character_cnt + 1 ;
--
end process CHG4 ;
--
PGEN_CHKP_4 :
process ( chk_character )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P4" ,
"Transport transactions completed entirely",
chk_character = 4 ) ;
end if ;
end process PGEN_CHKP_4 ;
--
--
with character_select select
s_character <= transport
c_character_2 after 10 ns,
c_character_1 after 20 ns
when 1,
--
c_character_2 after 10 ns ,
c_character_1 after 20 ns ,
c_character_2 after 30 ns ,
c_character_1 after 40 ns
when 2,
--
c_character_1 after 5 ns when 3 ;
--
CHG5 :
process ( s_st_enum1 )
variable correct : boolean ;
begin
case s_st_enum1_cnt is
when 0
=> null ;
-- s_st_enum1 <= transport
-- c_st_enum1_2 after 10 ns,
-- c_st_enum1_1 after 20 ns ;
--
when 1
=> correct :=
s_st_enum1 =
c_st_enum1_2 and
(s_st_enum1_savt + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_enum1 =
c_st_enum1_1 and
(s_st_enum1_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00338.P5" ,
"Multi transport transactions occurred on " &
"concurrent signal asg",
correct ) ;
--
st_enum1_select <= transport 2 ;
-- s_st_enum1 <= transport
-- c_st_enum1_2 after 10 ns ,
-- c_st_enum1_1 after 20 ns ,
-- c_st_enum1_2 after 30 ns ,
-- c_st_enum1_1 after 40 ns ;
--
when 3
=> correct :=
s_st_enum1 =
c_st_enum1_2 and
(s_st_enum1_savt + 10 ns) = Std.Standard.Now ;
st_enum1_select <= transport 3 ;
-- s_st_enum1 <= transport
-- c_st_enum1_1 after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_enum1 =
c_st_enum1_1 and
(s_st_enum1_savt + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00338" ,
"One transport transaction occurred on a " &
"concurrent signal asg",
correct ) ;
test_report ( "ARCH00338" ,
"Old transactions were removed on a " &
"concurrent signal asg",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00338" ,
"Old transactions were removed on a " &
"concurrent signal asg",
false ) ;
--
end case ;
--
s_st_enum1_savt <= transport Std.Standard.Now ;
chk_st_enum1 <= transport s_st_enum1_cnt
after (1 us - Std.Standard.Now) ;
s_st_enum1_cnt <= transport s_st_enum1_cnt + 1 ;
--
end process CHG5 ;
--
PGEN_CHKP_5 :
process ( chk_st_enum1 )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P5" ,
"Transport transactions completed entirely",
chk_st_enum1 = 4 ) ;
end if ;
end process PGEN_CHKP_5 ;
--
--
with st_enum1_select select
s_st_enum1 <= transport
c_st_enum1_2 after 10 ns,
c_st_enum1_1 after 20 ns
when 1,
--
c_st_enum1_2 after 10 ns ,
c_st_enum1_1 after 20 ns ,
c_st_enum1_2 after 30 ns ,
c_st_enum1_1 after 40 ns
when 2,
--
c_st_enum1_1 after 5 ns when 3 ;
--
CHG6 :
process ( s_integer )
variable correct : boolean ;
begin
case s_integer_cnt is
when 0
=> null ;
-- s_integer <= transport
-- c_integer_2 after 10 ns,
-- c_integer_1 after 20 ns ;
--
when 1
=> correct :=
s_integer =
c_integer_2 and
(s_integer_savt + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_integer =
c_integer_1 and
(s_integer_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00338.P6" ,
"Multi transport transactions occurred on " &
"concurrent signal asg",
correct ) ;
--
integer_select <= transport 2 ;
-- s_integer <= transport
-- c_integer_2 after 10 ns ,
-- c_integer_1 after 20 ns ,
-- c_integer_2 after 30 ns ,
-- c_integer_1 after 40 ns ;
--
when 3
=> correct :=
s_integer =
c_integer_2 and
(s_integer_savt + 10 ns) = Std.Standard.Now ;
integer_select <= transport 3 ;
-- s_integer <= transport
-- c_integer_1 after 5 ns ;
--
when 4
=> correct :=
correct and
s_integer =
c_integer_1 and
(s_integer_savt + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00338" ,
"One transport transaction occurred on a " &
"concurrent signal asg",
correct ) ;
test_report ( "ARCH00338" ,
"Old transactions were removed on a " &
"concurrent signal asg",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00338" ,
"Old transactions were removed on a " &
"concurrent signal asg",
false ) ;
--
end case ;
--
s_integer_savt <= transport Std.Standard.Now ;
chk_integer <= transport s_integer_cnt
after (1 us - Std.Standard.Now) ;
s_integer_cnt <= transport s_integer_cnt + 1 ;
--
end process CHG6 ;
--
PGEN_CHKP_6 :
process ( chk_integer )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P6" ,
"Transport transactions completed entirely",
chk_integer = 4 ) ;
end if ;
end process PGEN_CHKP_6 ;
--
--
with integer_select select
s_integer <= transport
c_integer_2 after 10 ns,
c_integer_1 after 20 ns
when 1,
--
c_integer_2 after 10 ns ,
c_integer_1 after 20 ns ,
c_integer_2 after 30 ns ,
c_integer_1 after 40 ns
when 2,
--
c_integer_1 after 5 ns when 3 ;
--
CHG7 :
process ( s_st_int1 )
variable correct : boolean ;
begin
case s_st_int1_cnt is
when 0
=> null ;
-- s_st_int1 <= transport
-- c_st_int1_2 after 10 ns,
-- c_st_int1_1 after 20 ns ;
--
when 1
=> correct :=
s_st_int1 =
c_st_int1_2 and
(s_st_int1_savt + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_int1 =
c_st_int1_1 and
(s_st_int1_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00338.P7" ,
"Multi transport transactions occurred on " &
"concurrent signal asg",
correct ) ;
--
st_int1_select <= transport 2 ;
-- s_st_int1 <= transport
-- c_st_int1_2 after 10 ns ,
-- c_st_int1_1 after 20 ns ,
-- c_st_int1_2 after 30 ns ,
-- c_st_int1_1 after 40 ns ;
--
when 3
=> correct :=
s_st_int1 =
c_st_int1_2 and
(s_st_int1_savt + 10 ns) = Std.Standard.Now ;
st_int1_select <= transport 3 ;
-- s_st_int1 <= transport
-- c_st_int1_1 after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_int1 =
c_st_int1_1 and
(s_st_int1_savt + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00338" ,
"One transport transaction occurred on a " &
"concurrent signal asg",
correct ) ;
test_report ( "ARCH00338" ,
"Old transactions were removed on a " &
"concurrent signal asg",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00338" ,
"Old transactions were removed on a " &
"concurrent signal asg",
false ) ;
--
end case ;
--
s_st_int1_savt <= transport Std.Standard.Now ;
chk_st_int1 <= transport s_st_int1_cnt
after (1 us - Std.Standard.Now) ;
s_st_int1_cnt <= transport s_st_int1_cnt + 1 ;
--
end process CHG7 ;
--
PGEN_CHKP_7 :
process ( chk_st_int1 )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P7" ,
"Transport transactions completed entirely",
chk_st_int1 = 4 ) ;
end if ;
end process PGEN_CHKP_7 ;
--
--
with st_int1_select select
s_st_int1 <= transport
c_st_int1_2 after 10 ns,
c_st_int1_1 after 20 ns
when 1,
--
c_st_int1_2 after 10 ns ,
c_st_int1_1 after 20 ns ,
c_st_int1_2 after 30 ns ,
c_st_int1_1 after 40 ns
when 2,
--
c_st_int1_1 after 5 ns when 3 ;
--
CHG8 :
process ( s_time )
variable correct : boolean ;
begin
case s_time_cnt is
when 0
=> null ;
-- s_time <= transport
-- c_time_2 after 10 ns,
-- c_time_1 after 20 ns ;
--
when 1
=> correct :=
s_time =
c_time_2 and
(s_time_savt + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_time =
c_time_1 and
(s_time_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00338.P8" ,
"Multi transport transactions occurred on " &
"concurrent signal asg",
correct ) ;
--
time_select <= transport 2 ;
-- s_time <= transport
-- c_time_2 after 10 ns ,
-- c_time_1 after 20 ns ,
-- c_time_2 after 30 ns ,
-- c_time_1 after 40 ns ;
--
when 3
=> correct :=
s_time =
c_time_2 and
(s_time_savt + 10 ns) = Std.Standard.Now ;
time_select <= transport 3 ;
-- s_time <= transport
-- c_time_1 after 5 ns ;
--
when 4
=> correct :=
correct and
s_time =
c_time_1 and
(s_time_savt + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00338" ,
"One transport transaction occurred on a " &
"concurrent signal asg",
correct ) ;
test_report ( "ARCH00338" ,
"Old transactions were removed on a " &
"concurrent signal asg",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00338" ,
"Old transactions were removed on a " &
"concurrent signal asg",
false ) ;
--
end case ;
--
s_time_savt <= transport Std.Standard.Now ;
chk_time <= transport s_time_cnt
after (1 us - Std.Standard.Now) ;
s_time_cnt <= transport s_time_cnt + 1 ;
--
end process CHG8 ;
--
PGEN_CHKP_8 :
process ( chk_time )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P8" ,
"Transport transactions completed entirely",
chk_time = 4 ) ;
end if ;
end process PGEN_CHKP_8 ;
--
--
with time_select select
s_time <= transport
c_time_2 after 10 ns,
c_time_1 after 20 ns
when 1,
--
c_time_2 after 10 ns ,
c_time_1 after 20 ns ,
c_time_2 after 30 ns ,
c_time_1 after 40 ns
when 2,
--
c_time_1 after 5 ns when 3 ;
--
CHG9 :
process ( s_st_phys1 )
variable correct : boolean ;
begin
case s_st_phys1_cnt is
when 0
=> null ;
-- s_st_phys1 <= transport
-- c_st_phys1_2 after 10 ns,
-- c_st_phys1_1 after 20 ns ;
--
when 1
=> correct :=
s_st_phys1 =
c_st_phys1_2 and
(s_st_phys1_savt + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_phys1 =
c_st_phys1_1 and
(s_st_phys1_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00338.P9" ,
"Multi transport transactions occurred on " &
"concurrent signal asg",
correct ) ;
--
st_phys1_select <= transport 2 ;
-- s_st_phys1 <= transport
-- c_st_phys1_2 after 10 ns ,
-- c_st_phys1_1 after 20 ns ,
-- c_st_phys1_2 after 30 ns ,
-- c_st_phys1_1 after 40 ns ;
--
when 3
=> correct :=
s_st_phys1 =
c_st_phys1_2 and
(s_st_phys1_savt + 10 ns) = Std.Standard.Now ;
st_phys1_select <= transport 3 ;
-- s_st_phys1 <= transport
-- c_st_phys1_1 after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_phys1 =
c_st_phys1_1 and
(s_st_phys1_savt + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00338" ,
"One transport transaction occurred on a " &
"concurrent signal asg",
correct ) ;
test_report ( "ARCH00338" ,
"Old transactions were removed on a " &
"concurrent signal asg",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00338" ,
"Old transactions were removed on a " &
"concurrent signal asg",
false ) ;
--
end case ;
--
s_st_phys1_savt <= transport Std.Standard.Now ;
chk_st_phys1 <= transport s_st_phys1_cnt
after (1 us - Std.Standard.Now) ;
s_st_phys1_cnt <= transport s_st_phys1_cnt + 1 ;
--
end process CHG9 ;
--
PGEN_CHKP_9 :
process ( chk_st_phys1 )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P9" ,
"Transport transactions completed entirely",
chk_st_phys1 = 4 ) ;
end if ;
end process PGEN_CHKP_9 ;
--
--
with st_phys1_select select
s_st_phys1 <= transport
c_st_phys1_2 after 10 ns,
c_st_phys1_1 after 20 ns
when 1,
--
c_st_phys1_2 after 10 ns ,
c_st_phys1_1 after 20 ns ,
c_st_phys1_2 after 30 ns ,
c_st_phys1_1 after 40 ns
when 2,
--
c_st_phys1_1 after 5 ns when 3 ;
--
CHG10 :
process ( s_real )
variable correct : boolean ;
begin
case s_real_cnt is
when 0
=> null ;
-- s_real <= transport
-- c_real_2 after 10 ns,
-- c_real_1 after 20 ns ;
--
when 1
=> correct :=
s_real =
c_real_2 and
(s_real_savt + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_real =
c_real_1 and
(s_real_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00338.P10" ,
"Multi transport transactions occurred on " &
"concurrent signal asg",
correct ) ;
--
real_select <= transport 2 ;
-- s_real <= transport
-- c_real_2 after 10 ns ,
-- c_real_1 after 20 ns ,
-- c_real_2 after 30 ns ,
-- c_real_1 after 40 ns ;
--
when 3
=> correct :=
s_real =
c_real_2 and
(s_real_savt + 10 ns) = Std.Standard.Now ;
real_select <= transport 3 ;
-- s_real <= transport
-- c_real_1 after 5 ns ;
--
when 4
=> correct :=
correct and
s_real =
c_real_1 and
(s_real_savt + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00338" ,
"One transport transaction occurred on a " &
"concurrent signal asg",
correct ) ;
test_report ( "ARCH00338" ,
"Old transactions were removed on a " &
"concurrent signal asg",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00338" ,
"Old transactions were removed on a " &
"concurrent signal asg",
false ) ;
--
end case ;
--
s_real_savt <= transport Std.Standard.Now ;
chk_real <= transport s_real_cnt
after (1 us - Std.Standard.Now) ;
s_real_cnt <= transport s_real_cnt + 1 ;
--
end process CHG10 ;
--
PGEN_CHKP_10 :
process ( chk_real )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P10" ,
"Transport transactions completed entirely",
chk_real = 4 ) ;
end if ;
end process PGEN_CHKP_10 ;
--
--
with real_select select
s_real <= transport
c_real_2 after 10 ns,
c_real_1 after 20 ns
when 1,
--
c_real_2 after 10 ns ,
c_real_1 after 20 ns ,
c_real_2 after 30 ns ,
c_real_1 after 40 ns
when 2,
--
c_real_1 after 5 ns when 3 ;
--
CHG11 :
process ( s_st_real1 )
variable correct : boolean ;
begin
case s_st_real1_cnt is
when 0
=> null ;
-- s_st_real1 <= transport
-- c_st_real1_2 after 10 ns,
-- c_st_real1_1 after 20 ns ;
--
when 1
=> correct :=
s_st_real1 =
c_st_real1_2 and
(s_st_real1_savt + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_real1 =
c_st_real1_1 and
(s_st_real1_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00338.P11" ,
"Multi transport transactions occurred on " &
"concurrent signal asg",
correct ) ;
--
st_real1_select <= transport 2 ;
-- s_st_real1 <= transport
-- c_st_real1_2 after 10 ns ,
-- c_st_real1_1 after 20 ns ,
-- c_st_real1_2 after 30 ns ,
-- c_st_real1_1 after 40 ns ;
--
when 3
=> correct :=
s_st_real1 =
c_st_real1_2 and
(s_st_real1_savt + 10 ns) = Std.Standard.Now ;
st_real1_select <= transport 3 ;
-- s_st_real1 <= transport
-- c_st_real1_1 after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_real1 =
c_st_real1_1 and
(s_st_real1_savt + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00338" ,
"One transport transaction occurred on a " &
"concurrent signal asg",
correct ) ;
test_report ( "ARCH00338" ,
"Old transactions were removed on a " &
"concurrent signal asg",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00338" ,
"Old transactions were removed on a " &
"concurrent signal asg",
false ) ;
--
end case ;
--
s_st_real1_savt <= transport Std.Standard.Now ;
chk_st_real1 <= transport s_st_real1_cnt
after (1 us - Std.Standard.Now) ;
s_st_real1_cnt <= transport s_st_real1_cnt + 1 ;
--
end process CHG11 ;
--
PGEN_CHKP_11 :
process ( chk_st_real1 )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P11" ,
"Transport transactions completed entirely",
chk_st_real1 = 4 ) ;
end if ;
end process PGEN_CHKP_11 ;
--
--
with st_real1_select select
s_st_real1 <= transport
c_st_real1_2 after 10 ns,
c_st_real1_1 after 20 ns
when 1,
--
c_st_real1_2 after 10 ns ,
c_st_real1_1 after 20 ns ,
c_st_real1_2 after 30 ns ,
c_st_real1_1 after 40 ns
when 2,
--
c_st_real1_1 after 5 ns when 3 ;
--
CHG12 :
process ( s_st_rec1 )
variable correct : boolean ;
begin
case s_st_rec1_cnt is
when 0
=> null ;
-- s_st_rec1 <= transport
-- c_st_rec1_2 after 10 ns,
-- c_st_rec1_1 after 20 ns ;
--
when 1
=> correct :=
s_st_rec1 =
c_st_rec1_2 and
(s_st_rec1_savt + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_rec1 =
c_st_rec1_1 and
(s_st_rec1_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00338.P12" ,
"Multi transport transactions occurred on " &
"concurrent signal asg",
correct ) ;
--
st_rec1_select <= transport 2 ;
-- s_st_rec1 <= transport
-- c_st_rec1_2 after 10 ns ,
-- c_st_rec1_1 after 20 ns ,
-- c_st_rec1_2 after 30 ns ,
-- c_st_rec1_1 after 40 ns ;
--
when 3
=> correct :=
s_st_rec1 =
c_st_rec1_2 and
(s_st_rec1_savt + 10 ns) = Std.Standard.Now ;
st_rec1_select <= transport 3 ;
-- s_st_rec1 <= transport
-- c_st_rec1_1 after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_rec1 =
c_st_rec1_1 and
(s_st_rec1_savt + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00338" ,
"One transport transaction occurred on a " &
"concurrent signal asg",
correct ) ;
test_report ( "ARCH00338" ,
"Old transactions were removed on a " &
"concurrent signal asg",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00338" ,
"Old transactions were removed on a " &
"concurrent signal asg",
false ) ;
--
end case ;
--
s_st_rec1_savt <= transport Std.Standard.Now ;
chk_st_rec1 <= transport s_st_rec1_cnt
after (1 us - Std.Standard.Now) ;
s_st_rec1_cnt <= transport s_st_rec1_cnt + 1 ;
--
end process CHG12 ;
--
PGEN_CHKP_12 :
process ( chk_st_rec1 )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P12" ,
"Transport transactions completed entirely",
chk_st_rec1 = 4 ) ;
end if ;
end process PGEN_CHKP_12 ;
--
--
with st_rec1_select select
s_st_rec1 <= transport
c_st_rec1_2 after 10 ns,
c_st_rec1_1 after 20 ns
when 1,
--
c_st_rec1_2 after 10 ns ,
c_st_rec1_1 after 20 ns ,
c_st_rec1_2 after 30 ns ,
c_st_rec1_1 after 40 ns
when 2,
--
c_st_rec1_1 after 5 ns when 3 ;
--
CHG13 :
process ( s_st_rec2 )
variable correct : boolean ;
begin
case s_st_rec2_cnt is
when 0
=> null ;
-- s_st_rec2 <= transport
-- c_st_rec2_2 after 10 ns,
-- c_st_rec2_1 after 20 ns ;
--
when 1
=> correct :=
s_st_rec2 =
c_st_rec2_2 and
(s_st_rec2_savt + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_rec2 =
c_st_rec2_1 and
(s_st_rec2_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00338.P13" ,
"Multi transport transactions occurred on " &
"concurrent signal asg",
correct ) ;
--
st_rec2_select <= transport 2 ;
-- s_st_rec2 <= transport
-- c_st_rec2_2 after 10 ns ,
-- c_st_rec2_1 after 20 ns ,
-- c_st_rec2_2 after 30 ns ,
-- c_st_rec2_1 after 40 ns ;
--
when 3
=> correct :=
s_st_rec2 =
c_st_rec2_2 and
(s_st_rec2_savt + 10 ns) = Std.Standard.Now ;
st_rec2_select <= transport 3 ;
-- s_st_rec2 <= transport
-- c_st_rec2_1 after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_rec2 =
c_st_rec2_1 and
(s_st_rec2_savt + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00338" ,
"One transport transaction occurred on a " &
"concurrent signal asg",
correct ) ;
test_report ( "ARCH00338" ,
"Old transactions were removed on a " &
"concurrent signal asg",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00338" ,
"Old transactions were removed on a " &
"concurrent signal asg",
false ) ;
--
end case ;
--
s_st_rec2_savt <= transport Std.Standard.Now ;
chk_st_rec2 <= transport s_st_rec2_cnt
after (1 us - Std.Standard.Now) ;
s_st_rec2_cnt <= transport s_st_rec2_cnt + 1 ;
--
end process CHG13 ;
--
PGEN_CHKP_13 :
process ( chk_st_rec2 )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P13" ,
"Transport transactions completed entirely",
chk_st_rec2 = 4 ) ;
end if ;
end process PGEN_CHKP_13 ;
--
--
with st_rec2_select select
s_st_rec2 <= transport
c_st_rec2_2 after 10 ns,
c_st_rec2_1 after 20 ns
when 1,
--
c_st_rec2_2 after 10 ns ,
c_st_rec2_1 after 20 ns ,
c_st_rec2_2 after 30 ns ,
c_st_rec2_1 after 40 ns
when 2,
--
c_st_rec2_1 after 5 ns when 3 ;
--
CHG14 :
process ( s_st_rec3 )
variable correct : boolean ;
begin
case s_st_rec3_cnt is
when 0
=> null ;
-- s_st_rec3 <= transport
-- c_st_rec3_2 after 10 ns,
-- c_st_rec3_1 after 20 ns ;
--
when 1
=> correct :=
s_st_rec3 =
c_st_rec3_2 and
(s_st_rec3_savt + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_rec3 =
c_st_rec3_1 and
(s_st_rec3_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00338.P14" ,
"Multi transport transactions occurred on " &
"concurrent signal asg",
correct ) ;
--
st_rec3_select <= transport 2 ;
-- s_st_rec3 <= transport
-- c_st_rec3_2 after 10 ns ,
-- c_st_rec3_1 after 20 ns ,
-- c_st_rec3_2 after 30 ns ,
-- c_st_rec3_1 after 40 ns ;
--
when 3
=> correct :=
s_st_rec3 =
c_st_rec3_2 and
(s_st_rec3_savt + 10 ns) = Std.Standard.Now ;
st_rec3_select <= transport 3 ;
-- s_st_rec3 <= transport
-- c_st_rec3_1 after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_rec3 =
c_st_rec3_1 and
(s_st_rec3_savt + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00338" ,
"One transport transaction occurred on a " &
"concurrent signal asg",
correct ) ;
test_report ( "ARCH00338" ,
"Old transactions were removed on a " &
"concurrent signal asg",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00338" ,
"Old transactions were removed on a " &
"concurrent signal asg",
false ) ;
--
end case ;
--
s_st_rec3_savt <= transport Std.Standard.Now ;
chk_st_rec3 <= transport s_st_rec3_cnt
after (1 us - Std.Standard.Now) ;
s_st_rec3_cnt <= transport s_st_rec3_cnt + 1 ;
--
end process CHG14 ;
--
PGEN_CHKP_14 :
process ( chk_st_rec3 )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P14" ,
"Transport transactions completed entirely",
chk_st_rec3 = 4 ) ;
end if ;
end process PGEN_CHKP_14 ;
--
--
with st_rec3_select select
s_st_rec3 <= transport
c_st_rec3_2 after 10 ns,
c_st_rec3_1 after 20 ns
when 1,
--
c_st_rec3_2 after 10 ns ,
c_st_rec3_1 after 20 ns ,
c_st_rec3_2 after 30 ns ,
c_st_rec3_1 after 40 ns
when 2,
--
c_st_rec3_1 after 5 ns when 3 ;
--
CHG15 :
process ( s_st_arr1 )
variable correct : boolean ;
begin
case s_st_arr1_cnt is
when 0
=> null ;
-- s_st_arr1 <= transport
-- c_st_arr1_2 after 10 ns,
-- c_st_arr1_1 after 20 ns ;
--
when 1
=> correct :=
s_st_arr1 =
c_st_arr1_2 and
(s_st_arr1_savt + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_arr1 =
c_st_arr1_1 and
(s_st_arr1_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00338.P15" ,
"Multi transport transactions occurred on " &
"concurrent signal asg",
correct ) ;
--
st_arr1_select <= transport 2 ;
-- s_st_arr1 <= transport
-- c_st_arr1_2 after 10 ns ,
-- c_st_arr1_1 after 20 ns ,
-- c_st_arr1_2 after 30 ns ,
-- c_st_arr1_1 after 40 ns ;
--
when 3
=> correct :=
s_st_arr1 =
c_st_arr1_2 and
(s_st_arr1_savt + 10 ns) = Std.Standard.Now ;
st_arr1_select <= transport 3 ;
-- s_st_arr1 <= transport
-- c_st_arr1_1 after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_arr1 =
c_st_arr1_1 and
(s_st_arr1_savt + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00338" ,
"One transport transaction occurred on a " &
"concurrent signal asg",
correct ) ;
test_report ( "ARCH00338" ,
"Old transactions were removed on a " &
"concurrent signal asg",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00338" ,
"Old transactions were removed on a " &
"concurrent signal asg",
false ) ;
--
end case ;
--
s_st_arr1_savt <= transport Std.Standard.Now ;
chk_st_arr1 <= transport s_st_arr1_cnt
after (1 us - Std.Standard.Now) ;
s_st_arr1_cnt <= transport s_st_arr1_cnt + 1 ;
--
end process CHG15 ;
--
PGEN_CHKP_15 :
process ( chk_st_arr1 )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P15" ,
"Transport transactions completed entirely",
chk_st_arr1 = 4 ) ;
end if ;
end process PGEN_CHKP_15 ;
--
--
with st_arr1_select select
s_st_arr1 <= transport
c_st_arr1_2 after 10 ns,
c_st_arr1_1 after 20 ns
when 1,
--
c_st_arr1_2 after 10 ns ,
c_st_arr1_1 after 20 ns ,
c_st_arr1_2 after 30 ns ,
c_st_arr1_1 after 40 ns
when 2,
--
c_st_arr1_1 after 5 ns when 3 ;
--
CHG16 :
process ( s_st_arr2 )
variable correct : boolean ;
begin
case s_st_arr2_cnt is
when 0
=> null ;
-- s_st_arr2 <= transport
-- c_st_arr2_2 after 10 ns,
-- c_st_arr2_1 after 20 ns ;
--
when 1
=> correct :=
s_st_arr2 =
c_st_arr2_2 and
(s_st_arr2_savt + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_arr2 =
c_st_arr2_1 and
(s_st_arr2_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00338.P16" ,
"Multi transport transactions occurred on " &
"concurrent signal asg",
correct ) ;
--
st_arr2_select <= transport 2 ;
-- s_st_arr2 <= transport
-- c_st_arr2_2 after 10 ns ,
-- c_st_arr2_1 after 20 ns ,
-- c_st_arr2_2 after 30 ns ,
-- c_st_arr2_1 after 40 ns ;
--
when 3
=> correct :=
s_st_arr2 =
c_st_arr2_2 and
(s_st_arr2_savt + 10 ns) = Std.Standard.Now ;
st_arr2_select <= transport 3 ;
-- s_st_arr2 <= transport
-- c_st_arr2_1 after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_arr2 =
c_st_arr2_1 and
(s_st_arr2_savt + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00338" ,
"One transport transaction occurred on a " &
"concurrent signal asg",
correct ) ;
test_report ( "ARCH00338" ,
"Old transactions were removed on a " &
"concurrent signal asg",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00338" ,
"Old transactions were removed on a " &
"concurrent signal asg",
false ) ;
--
end case ;
--
s_st_arr2_savt <= transport Std.Standard.Now ;
chk_st_arr2 <= transport s_st_arr2_cnt
after (1 us - Std.Standard.Now) ;
s_st_arr2_cnt <= transport s_st_arr2_cnt + 1 ;
--
end process CHG16 ;
--
PGEN_CHKP_16 :
process ( chk_st_arr2 )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P16" ,
"Transport transactions completed entirely",
chk_st_arr2 = 4 ) ;
end if ;
end process PGEN_CHKP_16 ;
--
--
with st_arr2_select select
s_st_arr2 <= transport
c_st_arr2_2 after 10 ns,
c_st_arr2_1 after 20 ns
when 1,
--
c_st_arr2_2 after 10 ns ,
c_st_arr2_1 after 20 ns ,
c_st_arr2_2 after 30 ns ,
c_st_arr2_1 after 40 ns
when 2,
--
c_st_arr2_1 after 5 ns when 3 ;
--
CHG17 :
process ( s_st_arr3 )
variable correct : boolean ;
begin
case s_st_arr3_cnt is
when 0
=> null ;
-- s_st_arr3 <= transport
-- c_st_arr3_2 after 10 ns,
-- c_st_arr3_1 after 20 ns ;
--
when 1
=> correct :=
s_st_arr3 =
c_st_arr3_2 and
(s_st_arr3_savt + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_arr3 =
c_st_arr3_1 and
(s_st_arr3_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00338.P17" ,
"Multi transport transactions occurred on " &
"concurrent signal asg",
correct ) ;
--
st_arr3_select <= transport 2 ;
-- s_st_arr3 <= transport
-- c_st_arr3_2 after 10 ns ,
-- c_st_arr3_1 after 20 ns ,
-- c_st_arr3_2 after 30 ns ,
-- c_st_arr3_1 after 40 ns ;
--
when 3
=> correct :=
s_st_arr3 =
c_st_arr3_2 and
(s_st_arr3_savt + 10 ns) = Std.Standard.Now ;
st_arr3_select <= transport 3 ;
-- s_st_arr3 <= transport
-- c_st_arr3_1 after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_arr3 =
c_st_arr3_1 and
(s_st_arr3_savt + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00338" ,
"One transport transaction occurred on a " &
"concurrent signal asg",
correct ) ;
test_report ( "ARCH00338" ,
"Old transactions were removed on a " &
"concurrent signal asg",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00338" ,
"Old transactions were removed on a " &
"concurrent signal asg",
false ) ;
--
end case ;
--
s_st_arr3_savt <= transport Std.Standard.Now ;
chk_st_arr3 <= transport s_st_arr3_cnt
after (1 us - Std.Standard.Now) ;
s_st_arr3_cnt <= transport s_st_arr3_cnt + 1 ;
--
end process CHG17 ;
--
PGEN_CHKP_17 :
process ( chk_st_arr3 )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P17" ,
"Transport transactions completed entirely",
chk_st_arr3 = 4 ) ;
end if ;
end process PGEN_CHKP_17 ;
--
--
with st_arr3_select select
s_st_arr3 <= transport
c_st_arr3_2 after 10 ns,
c_st_arr3_1 after 20 ns
when 1,
--
c_st_arr3_2 after 10 ns ,
c_st_arr3_1 after 20 ns ,
c_st_arr3_2 after 30 ns ,
c_st_arr3_1 after 40 ns
when 2,
--
c_st_arr3_1 after 5 ns when 3 ;
--
end ARCH00338 ;
--
--
use WORK.STANDARD_TYPES.all ;
entity ENT00338_Test_Bench is
signal s_boolean : boolean
:= c_boolean_1 ;
signal s_bit : bit
:= c_bit_1 ;
signal s_severity_level : severity_level
:= c_severity_level_1 ;
signal s_character : character
:= c_character_1 ;
signal s_st_enum1 : st_enum1
:= c_st_enum1_1 ;
signal s_integer : integer
:= c_integer_1 ;
signal s_st_int1 : st_int1
:= c_st_int1_1 ;
signal s_time : time
:= c_time_1 ;
signal s_st_phys1 : st_phys1
:= c_st_phys1_1 ;
signal s_real : real
:= c_real_1 ;
signal s_st_real1 : st_real1
:= c_st_real1_1 ;
signal s_st_rec1 : st_rec1
:= c_st_rec1_1 ;
signal s_st_rec2 : st_rec2
:= c_st_rec2_1 ;
signal s_st_rec3 : st_rec3
:= c_st_rec3_1 ;
signal s_st_arr1 : st_arr1
:= c_st_arr1_1 ;
signal s_st_arr2 : st_arr2
:= c_st_arr2_1 ;
signal s_st_arr3 : st_arr3
:= c_st_arr3_1 ;
--
end ENT00338_Test_Bench ;
--
--
architecture ARCH00338_Test_Bench of ENT00338_Test_Bench is
begin
L1:
block
component UUT
port (
s_boolean : inout boolean
; s_bit : inout bit
; s_severity_level : inout severity_level
; s_character : inout character
; s_st_enum1 : inout st_enum1
; s_integer : inout integer
; s_st_int1 : inout st_int1
; s_time : inout time
; s_st_phys1 : inout st_phys1
; s_real : inout real
; s_st_real1 : inout st_real1
; s_st_rec1 : inout st_rec1
; s_st_rec2 : inout st_rec2
; s_st_rec3 : inout st_rec3
; s_st_arr1 : inout st_arr1
; s_st_arr2 : inout st_arr2
; s_st_arr3 : inout st_arr3
) ;
end component ;
--
for CIS1 : UUT use entity WORK.ENT00338 ( ARCH00338 ) ;
begin
CIS1 : UUT
port map (
s_boolean
, s_bit
, s_severity_level
, s_character
, s_st_enum1
, s_integer
, s_st_int1
, s_time
, s_st_phys1
, s_real
, s_st_real1
, s_st_rec1
, s_st_rec2
, s_st_rec3
, s_st_arr1
, s_st_arr2
, s_st_arr3
)
;
end block L1 ;
end ARCH00338_Test_Bench ;
| gpl-3.0 | 8a180fd51a03fba5b2a00fefc7d12795 | 0.487342 | 3.725906 | false | false | false | false |
TWW12/lzw | ip_repo/axi_compression_1.0/src/bram_1024_0/synth/bram_1024_0.vhd | 4 | 14,457 | -- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:blk_mem_gen:8.3
-- IP Revision: 5
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY blk_mem_gen_v8_3_5;
USE blk_mem_gen_v8_3_5.blk_mem_gen_v8_3_5;
ENTITY bram_1024_0 IS
PORT (
clka : IN STD_LOGIC;
ena : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(19 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(19 DOWNTO 0)
);
END bram_1024_0;
ARCHITECTURE bram_1024_0_arch OF bram_1024_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF bram_1024_0_arch: ARCHITECTURE IS "yes";
COMPONENT blk_mem_gen_v8_3_5 IS
GENERIC (
C_FAMILY : STRING;
C_XDEVICEFAMILY : STRING;
C_ELABORATION_DIR : STRING;
C_INTERFACE_TYPE : INTEGER;
C_AXI_TYPE : INTEGER;
C_AXI_SLAVE_TYPE : INTEGER;
C_USE_BRAM_BLOCK : INTEGER;
C_ENABLE_32BIT_ADDRESS : INTEGER;
C_CTRL_ECC_ALGO : STRING;
C_HAS_AXI_ID : INTEGER;
C_AXI_ID_WIDTH : INTEGER;
C_MEM_TYPE : INTEGER;
C_BYTE_SIZE : INTEGER;
C_ALGORITHM : INTEGER;
C_PRIM_TYPE : INTEGER;
C_LOAD_INIT_FILE : INTEGER;
C_INIT_FILE_NAME : STRING;
C_INIT_FILE : STRING;
C_USE_DEFAULT_DATA : INTEGER;
C_DEFAULT_DATA : STRING;
C_HAS_RSTA : INTEGER;
C_RST_PRIORITY_A : STRING;
C_RSTRAM_A : INTEGER;
C_INITA_VAL : STRING;
C_HAS_ENA : INTEGER;
C_HAS_REGCEA : INTEGER;
C_USE_BYTE_WEA : INTEGER;
C_WEA_WIDTH : INTEGER;
C_WRITE_MODE_A : STRING;
C_WRITE_WIDTH_A : INTEGER;
C_READ_WIDTH_A : INTEGER;
C_WRITE_DEPTH_A : INTEGER;
C_READ_DEPTH_A : INTEGER;
C_ADDRA_WIDTH : INTEGER;
C_HAS_RSTB : INTEGER;
C_RST_PRIORITY_B : STRING;
C_RSTRAM_B : INTEGER;
C_INITB_VAL : STRING;
C_HAS_ENB : INTEGER;
C_HAS_REGCEB : INTEGER;
C_USE_BYTE_WEB : INTEGER;
C_WEB_WIDTH : INTEGER;
C_WRITE_MODE_B : STRING;
C_WRITE_WIDTH_B : INTEGER;
C_READ_WIDTH_B : INTEGER;
C_WRITE_DEPTH_B : INTEGER;
C_READ_DEPTH_B : INTEGER;
C_ADDRB_WIDTH : INTEGER;
C_HAS_MEM_OUTPUT_REGS_A : INTEGER;
C_HAS_MEM_OUTPUT_REGS_B : INTEGER;
C_HAS_MUX_OUTPUT_REGS_A : INTEGER;
C_HAS_MUX_OUTPUT_REGS_B : INTEGER;
C_MUX_PIPELINE_STAGES : INTEGER;
C_HAS_SOFTECC_INPUT_REGS_A : INTEGER;
C_HAS_SOFTECC_OUTPUT_REGS_B : INTEGER;
C_USE_SOFTECC : INTEGER;
C_USE_ECC : INTEGER;
C_EN_ECC_PIPE : INTEGER;
C_HAS_INJECTERR : INTEGER;
C_SIM_COLLISION_CHECK : STRING;
C_COMMON_CLK : INTEGER;
C_DISABLE_WARN_BHV_COLL : INTEGER;
C_EN_SLEEP_PIN : INTEGER;
C_USE_URAM : INTEGER;
C_EN_RDADDRA_CHG : INTEGER;
C_EN_RDADDRB_CHG : INTEGER;
C_EN_DEEPSLEEP_PIN : INTEGER;
C_EN_SHUTDOWN_PIN : INTEGER;
C_EN_SAFETY_CKT : INTEGER;
C_DISABLE_WARN_BHV_RANGE : INTEGER;
C_COUNT_36K_BRAM : STRING;
C_COUNT_18K_BRAM : STRING;
C_EST_POWER_SUMMARY : STRING
);
PORT (
clka : IN STD_LOGIC;
rsta : IN STD_LOGIC;
ena : IN STD_LOGIC;
regcea : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(19 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(19 DOWNTO 0);
clkb : IN STD_LOGIC;
rstb : IN STD_LOGIC;
enb : IN STD_LOGIC;
regceb : IN STD_LOGIC;
web : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addrb : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
dinb : IN STD_LOGIC_VECTOR(19 DOWNTO 0);
doutb : OUT STD_LOGIC_VECTOR(19 DOWNTO 0);
injectsbiterr : IN STD_LOGIC;
injectdbiterr : IN STD_LOGIC;
eccpipece : IN STD_LOGIC;
sbiterr : OUT STD_LOGIC;
dbiterr : OUT STD_LOGIC;
rdaddrecc : OUT STD_LOGIC_VECTOR(9 DOWNTO 0);
sleep : IN STD_LOGIC;
deepsleep : IN STD_LOGIC;
shutdown : IN STD_LOGIC;
rsta_busy : OUT STD_LOGIC;
rstb_busy : OUT STD_LOGIC;
s_aclk : IN STD_LOGIC;
s_aresetn : IN STD_LOGIC;
s_axi_awid : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_awaddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_awlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_awsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_awburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(19 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_wlast : IN STD_LOGIC;
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bid : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_arid : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_araddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_arlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_arsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_arburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rid : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_rdata : OUT STD_LOGIC_VECTOR(19 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rlast : OUT STD_LOGIC;
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
s_axi_injectsbiterr : IN STD_LOGIC;
s_axi_injectdbiterr : IN STD_LOGIC;
s_axi_sbiterr : OUT STD_LOGIC;
s_axi_dbiterr : OUT STD_LOGIC;
s_axi_rdaddrecc : OUT STD_LOGIC_VECTOR(9 DOWNTO 0)
);
END COMPONENT blk_mem_gen_v8_3_5;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF bram_1024_0_arch: ARCHITECTURE IS "blk_mem_gen_v8_3_5,Vivado 2016.4";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF bram_1024_0_arch : ARCHITECTURE IS "bram_1024_0,blk_mem_gen_v8_3_5,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF bram_1024_0_arch: ARCHITECTURE IS "bram_1024_0,blk_mem_gen_v8_3_5,{x_ipProduct=Vivado 2016.4,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=blk_mem_gen,x_ipVersion=8.3,x_ipCoreRevision=5,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,C_FAMILY=zynq,C_XDEVICEFAMILY=zynq,C_ELABORATION_DIR=./,C_INTERFACE_TYPE=0,C_AXI_TYPE=1,C_AXI_SLAVE_TYPE=0,C_USE_BRAM_BLOCK=0,C_ENABLE_32BIT_ADDRESS=0,C_CTRL_ECC_ALGO=NONE,C_HAS_AXI_ID=0,C_AXI_ID_WIDTH=4,C_MEM_TYPE=0,C_BYTE_SIZE=9,C_ALGORITHM=1,C_PRIM_TYPE=1,C_LOAD_INIT_FILE=1,C_INIT_FILE_NAME=bram_1024_0.mi" &
"f,C_INIT_FILE=bram_1024_0.mem,C_USE_DEFAULT_DATA=0,C_DEFAULT_DATA=0,C_HAS_RSTA=0,C_RST_PRIORITY_A=CE,C_RSTRAM_A=0,C_INITA_VAL=0,C_HAS_ENA=1,C_HAS_REGCEA=0,C_USE_BYTE_WEA=0,C_WEA_WIDTH=1,C_WRITE_MODE_A=WRITE_FIRST,C_WRITE_WIDTH_A=20,C_READ_WIDTH_A=20,C_WRITE_DEPTH_A=1024,C_READ_DEPTH_A=1024,C_ADDRA_WIDTH=10,C_HAS_RSTB=0,C_RST_PRIORITY_B=CE,C_RSTRAM_B=0,C_INITB_VAL=0,C_HAS_ENB=0,C_HAS_REGCEB=0,C_USE_BYTE_WEB=0,C_WEB_WIDTH=1,C_WRITE_MODE_B=WRITE_FIRST,C_WRITE_WIDTH_B=20,C_READ_WIDTH_B=20,C_WRITE_DE" &
"PTH_B=1024,C_READ_DEPTH_B=1024,C_ADDRB_WIDTH=10,C_HAS_MEM_OUTPUT_REGS_A=1,C_HAS_MEM_OUTPUT_REGS_B=0,C_HAS_MUX_OUTPUT_REGS_A=0,C_HAS_MUX_OUTPUT_REGS_B=0,C_MUX_PIPELINE_STAGES=0,C_HAS_SOFTECC_INPUT_REGS_A=0,C_HAS_SOFTECC_OUTPUT_REGS_B=0,C_USE_SOFTECC=0,C_USE_ECC=0,C_EN_ECC_PIPE=0,C_HAS_INJECTERR=0,C_SIM_COLLISION_CHECK=ALL,C_COMMON_CLK=0,C_DISABLE_WARN_BHV_COLL=0,C_EN_SLEEP_PIN=0,C_USE_URAM=0,C_EN_RDADDRA_CHG=0,C_EN_RDADDRB_CHG=0,C_EN_DEEPSLEEP_PIN=0,C_EN_SHUTDOWN_PIN=0,C_EN_SAFETY_CKT=0,C_DISABLE" &
"_WARN_BHV_RANGE=0,C_COUNT_36K_BRAM=1,C_COUNT_18K_BRAM=0,C_EST_POWER_SUMMARY=Estimated Power for IP _ 2.74095 mW}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF clka: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA CLK";
ATTRIBUTE X_INTERFACE_INFO OF ena: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA EN";
ATTRIBUTE X_INTERFACE_INFO OF wea: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA WE";
ATTRIBUTE X_INTERFACE_INFO OF addra: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA ADDR";
ATTRIBUTE X_INTERFACE_INFO OF dina: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA DIN";
ATTRIBUTE X_INTERFACE_INFO OF douta: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA DOUT";
BEGIN
U0 : blk_mem_gen_v8_3_5
GENERIC MAP (
C_FAMILY => "zynq",
C_XDEVICEFAMILY => "zynq",
C_ELABORATION_DIR => "./",
C_INTERFACE_TYPE => 0,
C_AXI_TYPE => 1,
C_AXI_SLAVE_TYPE => 0,
C_USE_BRAM_BLOCK => 0,
C_ENABLE_32BIT_ADDRESS => 0,
C_CTRL_ECC_ALGO => "NONE",
C_HAS_AXI_ID => 0,
C_AXI_ID_WIDTH => 4,
C_MEM_TYPE => 0,
C_BYTE_SIZE => 9,
C_ALGORITHM => 1,
C_PRIM_TYPE => 1,
C_LOAD_INIT_FILE => 1,
C_INIT_FILE_NAME => "bram_1024_0.mif",
C_INIT_FILE => "bram_1024_0.mem",
C_USE_DEFAULT_DATA => 0,
C_DEFAULT_DATA => "0",
C_HAS_RSTA => 0,
C_RST_PRIORITY_A => "CE",
C_RSTRAM_A => 0,
C_INITA_VAL => "0",
C_HAS_ENA => 1,
C_HAS_REGCEA => 0,
C_USE_BYTE_WEA => 0,
C_WEA_WIDTH => 1,
C_WRITE_MODE_A => "WRITE_FIRST",
C_WRITE_WIDTH_A => 20,
C_READ_WIDTH_A => 20,
C_WRITE_DEPTH_A => 1024,
C_READ_DEPTH_A => 1024,
C_ADDRA_WIDTH => 10,
C_HAS_RSTB => 0,
C_RST_PRIORITY_B => "CE",
C_RSTRAM_B => 0,
C_INITB_VAL => "0",
C_HAS_ENB => 0,
C_HAS_REGCEB => 0,
C_USE_BYTE_WEB => 0,
C_WEB_WIDTH => 1,
C_WRITE_MODE_B => "WRITE_FIRST",
C_WRITE_WIDTH_B => 20,
C_READ_WIDTH_B => 20,
C_WRITE_DEPTH_B => 1024,
C_READ_DEPTH_B => 1024,
C_ADDRB_WIDTH => 10,
C_HAS_MEM_OUTPUT_REGS_A => 1,
C_HAS_MEM_OUTPUT_REGS_B => 0,
C_HAS_MUX_OUTPUT_REGS_A => 0,
C_HAS_MUX_OUTPUT_REGS_B => 0,
C_MUX_PIPELINE_STAGES => 0,
C_HAS_SOFTECC_INPUT_REGS_A => 0,
C_HAS_SOFTECC_OUTPUT_REGS_B => 0,
C_USE_SOFTECC => 0,
C_USE_ECC => 0,
C_EN_ECC_PIPE => 0,
C_HAS_INJECTERR => 0,
C_SIM_COLLISION_CHECK => "ALL",
C_COMMON_CLK => 0,
C_DISABLE_WARN_BHV_COLL => 0,
C_EN_SLEEP_PIN => 0,
C_USE_URAM => 0,
C_EN_RDADDRA_CHG => 0,
C_EN_RDADDRB_CHG => 0,
C_EN_DEEPSLEEP_PIN => 0,
C_EN_SHUTDOWN_PIN => 0,
C_EN_SAFETY_CKT => 0,
C_DISABLE_WARN_BHV_RANGE => 0,
C_COUNT_36K_BRAM => "1",
C_COUNT_18K_BRAM => "0",
C_EST_POWER_SUMMARY => "Estimated Power for IP : 2.74095 mW"
)
PORT MAP (
clka => clka,
rsta => '0',
ena => ena,
regcea => '0',
wea => wea,
addra => addra,
dina => dina,
douta => douta,
clkb => '0',
rstb => '0',
enb => '0',
regceb => '0',
web => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
addrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
dinb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 20)),
injectsbiterr => '0',
injectdbiterr => '0',
eccpipece => '0',
sleep => '0',
deepsleep => '0',
shutdown => '0',
s_aclk => '0',
s_aresetn => '0',
s_axi_awid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_awaddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_awlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_awsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_awburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_awvalid => '0',
s_axi_wdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 20)),
s_axi_wstrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_wlast => '0',
s_axi_wvalid => '0',
s_axi_bready => '0',
s_axi_arid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_araddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_arlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_arsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_arburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_arvalid => '0',
s_axi_rready => '0',
s_axi_injectsbiterr => '0',
s_axi_injectdbiterr => '0'
);
END bram_1024_0_arch;
| unlicense | 41a2984e595bff2a0323b59c5a65ad23 | 0.625372 | 3.002492 | false | false | false | false |
TWW12/lzw | final_project_sim/lzw/lzw.srcs/sources_1/ip/bram_1024_2/bram_1024_2_sim_netlist.vhdl | 1 | 50,604 | -- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1756540 Mon Jan 23 19:11:23 MST 2017
-- Date : Tue Apr 18 23:18:55 2017
-- Host : DESKTOP-I9J3TQJ running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode funcsim
-- X:/final_project_sim/lzw/lzw.srcs/sources_1/ip/bram_1024_2/bram_1024_2_sim_netlist.vhdl
-- Design : bram_1024_2
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7z020clg484-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity bram_1024_2_blk_mem_gen_prim_wrapper_init is
port (
douta : out STD_LOGIC_VECTOR ( 19 downto 0 );
clka : in STD_LOGIC;
ena : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 9 downto 0 );
dina : in STD_LOGIC_VECTOR ( 19 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of bram_1024_2_blk_mem_gen_prim_wrapper_init : entity is "blk_mem_gen_prim_wrapper_init";
end bram_1024_2_blk_mem_gen_prim_wrapper_init;
architecture STRUCTURE of bram_1024_2_blk_mem_gen_prim_wrapper_init is
signal \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_21\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_22\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_23\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_29\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_30\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_31\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_37\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_38\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_39\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_45\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_46\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_47\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_85\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_86\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_87\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_88\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute CLOCK_DOMAINS : string;
attribute CLOCK_DOMAINS of \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\ : label is "COMMON";
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 1,
DOB_REG => 0,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_00 => X"0000001F0000001B00000017000000130000000F0000000B0000000700000003",
INIT_01 => X"0000011F0000011B00000117000001130000010F0000010B0000010700000103",
INIT_02 => X"0000021F0000021B00000217000002130000020F0000020B0000020700000203",
INIT_03 => X"0000031F0000031B00000317000003130000030F0000030B0000030700000303",
INIT_04 => X"0000041F0000041B00000417000004130000040F0000040B0000040700000403",
INIT_05 => X"0000051F0000051B00000517000005130000050F0000050B0000050700000503",
INIT_06 => X"0000061F0000061B00000617000006130000060F0000060B0000060700000603",
INIT_07 => X"0000071F0000071B00000717000007130000070F0000070B0000070700000703",
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INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_43 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_44 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_45 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_46 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_47 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_48 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_49 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_50 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_51 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_52 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_53 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_54 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_55 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_56 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_57 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_58 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_59 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_60 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_61 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_62 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_63 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_64 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_65 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_66 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_67 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_68 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_69 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_70 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_71 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_72 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_73 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_74 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "PERFORMANCE",
READ_WIDTH_A => 36,
READ_WIDTH_B => 36,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 36,
WRITE_WIDTH_B => 36
)
port map (
ADDRARDADDR(15) => '1',
ADDRARDADDR(14 downto 5) => addra(9 downto 0),
ADDRARDADDR(4 downto 0) => B"11111",
ADDRBWRADDR(15 downto 0) => B"0000000000000000",
CASCADEINA => '0',
CASCADEINB => '0',
CASCADEOUTA => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => clka,
CLKBWRCLK => clka,
DBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\,
DIADI(31 downto 29) => B"000",
DIADI(28 downto 24) => dina(19 downto 15),
DIADI(23 downto 21) => B"000",
DIADI(20 downto 16) => dina(14 downto 10),
DIADI(15 downto 13) => B"000",
DIADI(12 downto 8) => dina(9 downto 5),
DIADI(7 downto 5) => B"000",
DIADI(4 downto 0) => dina(4 downto 0),
DIBDI(31 downto 0) => B"00000000000000000000000000000000",
DIPADIP(3 downto 0) => B"0000",
DIPBDIP(3 downto 0) => B"0000",
DOADO(31) => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_21\,
DOADO(30) => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_22\,
DOADO(29) => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_23\,
DOADO(28 downto 24) => douta(19 downto 15),
DOADO(23) => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_29\,
DOADO(22) => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_30\,
DOADO(21) => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_31\,
DOADO(20 downto 16) => douta(14 downto 10),
DOADO(15) => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_37\,
DOADO(14) => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_38\,
DOADO(13) => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_39\,
DOADO(12 downto 8) => douta(9 downto 5),
DOADO(7) => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_45\,
DOADO(6) => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_46\,
DOADO(5) => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_47\,
DOADO(4 downto 0) => douta(4 downto 0),
DOBDO(31 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\(31 downto 0),
DOPADOP(3) => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_85\,
DOPADOP(2) => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_86\,
DOPADOP(1) => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_87\,
DOPADOP(0) => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_88\,
DOPBDOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\(3 downto 0),
ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => ena,
ENBWREN => '0',
INJECTDBITERR => '0',
INJECTSBITERR => '0',
RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => ena,
REGCEB => '0',
RSTRAMARSTRAM => '0',
RSTRAMB => '0',
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\,
WEA(3) => wea(0),
WEA(2) => wea(0),
WEA(1) => wea(0),
WEA(0) => wea(0),
WEBWE(7 downto 0) => B"00000000"
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity bram_1024_2_blk_mem_gen_prim_width is
port (
douta : out STD_LOGIC_VECTOR ( 19 downto 0 );
clka : in STD_LOGIC;
ena : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 9 downto 0 );
dina : in STD_LOGIC_VECTOR ( 19 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of bram_1024_2_blk_mem_gen_prim_width : entity is "blk_mem_gen_prim_width";
end bram_1024_2_blk_mem_gen_prim_width;
architecture STRUCTURE of bram_1024_2_blk_mem_gen_prim_width is
begin
\prim_init.ram\: entity work.bram_1024_2_blk_mem_gen_prim_wrapper_init
port map (
addra(9 downto 0) => addra(9 downto 0),
clka => clka,
dina(19 downto 0) => dina(19 downto 0),
douta(19 downto 0) => douta(19 downto 0),
ena => ena,
wea(0) => wea(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity bram_1024_2_blk_mem_gen_generic_cstr is
port (
douta : out STD_LOGIC_VECTOR ( 19 downto 0 );
clka : in STD_LOGIC;
ena : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 9 downto 0 );
dina : in STD_LOGIC_VECTOR ( 19 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of bram_1024_2_blk_mem_gen_generic_cstr : entity is "blk_mem_gen_generic_cstr";
end bram_1024_2_blk_mem_gen_generic_cstr;
architecture STRUCTURE of bram_1024_2_blk_mem_gen_generic_cstr is
begin
\ramloop[0].ram.r\: entity work.bram_1024_2_blk_mem_gen_prim_width
port map (
addra(9 downto 0) => addra(9 downto 0),
clka => clka,
dina(19 downto 0) => dina(19 downto 0),
douta(19 downto 0) => douta(19 downto 0),
ena => ena,
wea(0) => wea(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity bram_1024_2_blk_mem_gen_top is
port (
douta : out STD_LOGIC_VECTOR ( 19 downto 0 );
clka : in STD_LOGIC;
ena : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 9 downto 0 );
dina : in STD_LOGIC_VECTOR ( 19 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of bram_1024_2_blk_mem_gen_top : entity is "blk_mem_gen_top";
end bram_1024_2_blk_mem_gen_top;
architecture STRUCTURE of bram_1024_2_blk_mem_gen_top is
begin
\valid.cstr\: entity work.bram_1024_2_blk_mem_gen_generic_cstr
port map (
addra(9 downto 0) => addra(9 downto 0),
clka => clka,
dina(19 downto 0) => dina(19 downto 0),
douta(19 downto 0) => douta(19 downto 0),
ena => ena,
wea(0) => wea(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity bram_1024_2_blk_mem_gen_v8_3_5_synth is
port (
douta : out STD_LOGIC_VECTOR ( 19 downto 0 );
clka : in STD_LOGIC;
ena : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 9 downto 0 );
dina : in STD_LOGIC_VECTOR ( 19 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of bram_1024_2_blk_mem_gen_v8_3_5_synth : entity is "blk_mem_gen_v8_3_5_synth";
end bram_1024_2_blk_mem_gen_v8_3_5_synth;
architecture STRUCTURE of bram_1024_2_blk_mem_gen_v8_3_5_synth is
begin
\gnbram.gnativebmg.native_blk_mem_gen\: entity work.bram_1024_2_blk_mem_gen_top
port map (
addra(9 downto 0) => addra(9 downto 0),
clka => clka,
dina(19 downto 0) => dina(19 downto 0),
douta(19 downto 0) => douta(19 downto 0),
ena => ena,
wea(0) => wea(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity bram_1024_2_blk_mem_gen_v8_3_5 is
port (
clka : in STD_LOGIC;
rsta : in STD_LOGIC;
ena : in STD_LOGIC;
regcea : in STD_LOGIC;
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
addra : in STD_LOGIC_VECTOR ( 9 downto 0 );
dina : in STD_LOGIC_VECTOR ( 19 downto 0 );
douta : out STD_LOGIC_VECTOR ( 19 downto 0 );
clkb : in STD_LOGIC;
rstb : in STD_LOGIC;
enb : in STD_LOGIC;
regceb : in STD_LOGIC;
web : in STD_LOGIC_VECTOR ( 0 to 0 );
addrb : in STD_LOGIC_VECTOR ( 9 downto 0 );
dinb : in STD_LOGIC_VECTOR ( 19 downto 0 );
doutb : out STD_LOGIC_VECTOR ( 19 downto 0 );
injectsbiterr : in STD_LOGIC;
injectdbiterr : in STD_LOGIC;
eccpipece : in STD_LOGIC;
sbiterr : out STD_LOGIC;
dbiterr : out STD_LOGIC;
rdaddrecc : out STD_LOGIC_VECTOR ( 9 downto 0 );
sleep : in STD_LOGIC;
deepsleep : in STD_LOGIC;
shutdown : in STD_LOGIC;
rsta_busy : out STD_LOGIC;
rstb_busy : out STD_LOGIC;
s_aclk : in STD_LOGIC;
s_aresetn : in STD_LOGIC;
s_axi_awid : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_awready : out STD_LOGIC;
s_axi_wdata : in STD_LOGIC_VECTOR ( 19 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_wlast : in STD_LOGIC;
s_axi_wvalid : in STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_bid : out STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_bvalid : out STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_arid : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arvalid : in STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_rid : out STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_rdata : out STD_LOGIC_VECTOR ( 19 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rlast : out STD_LOGIC;
s_axi_rvalid : out STD_LOGIC;
s_axi_rready : in STD_LOGIC;
s_axi_injectsbiterr : in STD_LOGIC;
s_axi_injectdbiterr : in STD_LOGIC;
s_axi_sbiterr : out STD_LOGIC;
s_axi_dbiterr : out STD_LOGIC;
s_axi_rdaddrecc : out STD_LOGIC_VECTOR ( 9 downto 0 )
);
attribute C_ADDRA_WIDTH : integer;
attribute C_ADDRA_WIDTH of bram_1024_2_blk_mem_gen_v8_3_5 : entity is 10;
attribute C_ADDRB_WIDTH : integer;
attribute C_ADDRB_WIDTH of bram_1024_2_blk_mem_gen_v8_3_5 : entity is 10;
attribute C_ALGORITHM : integer;
attribute C_ALGORITHM of bram_1024_2_blk_mem_gen_v8_3_5 : entity is 1;
attribute C_AXI_ID_WIDTH : integer;
attribute C_AXI_ID_WIDTH of bram_1024_2_blk_mem_gen_v8_3_5 : entity is 4;
attribute C_AXI_SLAVE_TYPE : integer;
attribute C_AXI_SLAVE_TYPE of bram_1024_2_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_AXI_TYPE : integer;
attribute C_AXI_TYPE of bram_1024_2_blk_mem_gen_v8_3_5 : entity is 1;
attribute C_BYTE_SIZE : integer;
attribute C_BYTE_SIZE of bram_1024_2_blk_mem_gen_v8_3_5 : entity is 9;
attribute C_COMMON_CLK : integer;
attribute C_COMMON_CLK of bram_1024_2_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_COUNT_18K_BRAM : string;
attribute C_COUNT_18K_BRAM of bram_1024_2_blk_mem_gen_v8_3_5 : entity is "0";
attribute C_COUNT_36K_BRAM : string;
attribute C_COUNT_36K_BRAM of bram_1024_2_blk_mem_gen_v8_3_5 : entity is "1";
attribute C_CTRL_ECC_ALGO : string;
attribute C_CTRL_ECC_ALGO of bram_1024_2_blk_mem_gen_v8_3_5 : entity is "NONE";
attribute C_DEFAULT_DATA : string;
attribute C_DEFAULT_DATA of bram_1024_2_blk_mem_gen_v8_3_5 : entity is "0";
attribute C_DISABLE_WARN_BHV_COLL : integer;
attribute C_DISABLE_WARN_BHV_COLL of bram_1024_2_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_DISABLE_WARN_BHV_RANGE : integer;
attribute C_DISABLE_WARN_BHV_RANGE of bram_1024_2_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_ELABORATION_DIR : string;
attribute C_ELABORATION_DIR of bram_1024_2_blk_mem_gen_v8_3_5 : entity is "./";
attribute C_ENABLE_32BIT_ADDRESS : integer;
attribute C_ENABLE_32BIT_ADDRESS of bram_1024_2_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_EN_DEEPSLEEP_PIN : integer;
attribute C_EN_DEEPSLEEP_PIN of bram_1024_2_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_EN_ECC_PIPE : integer;
attribute C_EN_ECC_PIPE of bram_1024_2_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_EN_RDADDRA_CHG : integer;
attribute C_EN_RDADDRA_CHG of bram_1024_2_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_EN_RDADDRB_CHG : integer;
attribute C_EN_RDADDRB_CHG of bram_1024_2_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_EN_SAFETY_CKT : integer;
attribute C_EN_SAFETY_CKT of bram_1024_2_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_EN_SHUTDOWN_PIN : integer;
attribute C_EN_SHUTDOWN_PIN of bram_1024_2_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_EN_SLEEP_PIN : integer;
attribute C_EN_SLEEP_PIN of bram_1024_2_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_EST_POWER_SUMMARY : string;
attribute C_EST_POWER_SUMMARY of bram_1024_2_blk_mem_gen_v8_3_5 : entity is "Estimated Power for IP : 2.74095 mW";
attribute C_FAMILY : string;
attribute C_FAMILY of bram_1024_2_blk_mem_gen_v8_3_5 : entity is "zynq";
attribute C_HAS_AXI_ID : integer;
attribute C_HAS_AXI_ID of bram_1024_2_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_HAS_ENA : integer;
attribute C_HAS_ENA of bram_1024_2_blk_mem_gen_v8_3_5 : entity is 1;
attribute C_HAS_ENB : integer;
attribute C_HAS_ENB of bram_1024_2_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_HAS_INJECTERR : integer;
attribute C_HAS_INJECTERR of bram_1024_2_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_HAS_MEM_OUTPUT_REGS_A : integer;
attribute C_HAS_MEM_OUTPUT_REGS_A of bram_1024_2_blk_mem_gen_v8_3_5 : entity is 1;
attribute C_HAS_MEM_OUTPUT_REGS_B : integer;
attribute C_HAS_MEM_OUTPUT_REGS_B of bram_1024_2_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_HAS_MUX_OUTPUT_REGS_A : integer;
attribute C_HAS_MUX_OUTPUT_REGS_A of bram_1024_2_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_HAS_MUX_OUTPUT_REGS_B : integer;
attribute C_HAS_MUX_OUTPUT_REGS_B of bram_1024_2_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_HAS_REGCEA : integer;
attribute C_HAS_REGCEA of bram_1024_2_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_HAS_REGCEB : integer;
attribute C_HAS_REGCEB of bram_1024_2_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_HAS_RSTA : integer;
attribute C_HAS_RSTA of bram_1024_2_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_HAS_RSTB : integer;
attribute C_HAS_RSTB of bram_1024_2_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_HAS_SOFTECC_INPUT_REGS_A : integer;
attribute C_HAS_SOFTECC_INPUT_REGS_A of bram_1024_2_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_HAS_SOFTECC_OUTPUT_REGS_B : integer;
attribute C_HAS_SOFTECC_OUTPUT_REGS_B of bram_1024_2_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_INITA_VAL : string;
attribute C_INITA_VAL of bram_1024_2_blk_mem_gen_v8_3_5 : entity is "0";
attribute C_INITB_VAL : string;
attribute C_INITB_VAL of bram_1024_2_blk_mem_gen_v8_3_5 : entity is "0";
attribute C_INIT_FILE : string;
attribute C_INIT_FILE of bram_1024_2_blk_mem_gen_v8_3_5 : entity is "bram_1024_2.mem";
attribute C_INIT_FILE_NAME : string;
attribute C_INIT_FILE_NAME of bram_1024_2_blk_mem_gen_v8_3_5 : entity is "bram_1024_2.mif";
attribute C_INTERFACE_TYPE : integer;
attribute C_INTERFACE_TYPE of bram_1024_2_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_LOAD_INIT_FILE : integer;
attribute C_LOAD_INIT_FILE of bram_1024_2_blk_mem_gen_v8_3_5 : entity is 1;
attribute C_MEM_TYPE : integer;
attribute C_MEM_TYPE of bram_1024_2_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_MUX_PIPELINE_STAGES : integer;
attribute C_MUX_PIPELINE_STAGES of bram_1024_2_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_PRIM_TYPE : integer;
attribute C_PRIM_TYPE of bram_1024_2_blk_mem_gen_v8_3_5 : entity is 1;
attribute C_READ_DEPTH_A : integer;
attribute C_READ_DEPTH_A of bram_1024_2_blk_mem_gen_v8_3_5 : entity is 1024;
attribute C_READ_DEPTH_B : integer;
attribute C_READ_DEPTH_B of bram_1024_2_blk_mem_gen_v8_3_5 : entity is 1024;
attribute C_READ_WIDTH_A : integer;
attribute C_READ_WIDTH_A of bram_1024_2_blk_mem_gen_v8_3_5 : entity is 20;
attribute C_READ_WIDTH_B : integer;
attribute C_READ_WIDTH_B of bram_1024_2_blk_mem_gen_v8_3_5 : entity is 20;
attribute C_RSTRAM_A : integer;
attribute C_RSTRAM_A of bram_1024_2_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_RSTRAM_B : integer;
attribute C_RSTRAM_B of bram_1024_2_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_RST_PRIORITY_A : string;
attribute C_RST_PRIORITY_A of bram_1024_2_blk_mem_gen_v8_3_5 : entity is "CE";
attribute C_RST_PRIORITY_B : string;
attribute C_RST_PRIORITY_B of bram_1024_2_blk_mem_gen_v8_3_5 : entity is "CE";
attribute C_SIM_COLLISION_CHECK : string;
attribute C_SIM_COLLISION_CHECK of bram_1024_2_blk_mem_gen_v8_3_5 : entity is "ALL";
attribute C_USE_BRAM_BLOCK : integer;
attribute C_USE_BRAM_BLOCK of bram_1024_2_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_USE_BYTE_WEA : integer;
attribute C_USE_BYTE_WEA of bram_1024_2_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_USE_BYTE_WEB : integer;
attribute C_USE_BYTE_WEB of bram_1024_2_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_USE_DEFAULT_DATA : integer;
attribute C_USE_DEFAULT_DATA of bram_1024_2_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_USE_ECC : integer;
attribute C_USE_ECC of bram_1024_2_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_USE_SOFTECC : integer;
attribute C_USE_SOFTECC of bram_1024_2_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_USE_URAM : integer;
attribute C_USE_URAM of bram_1024_2_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_WEA_WIDTH : integer;
attribute C_WEA_WIDTH of bram_1024_2_blk_mem_gen_v8_3_5 : entity is 1;
attribute C_WEB_WIDTH : integer;
attribute C_WEB_WIDTH of bram_1024_2_blk_mem_gen_v8_3_5 : entity is 1;
attribute C_WRITE_DEPTH_A : integer;
attribute C_WRITE_DEPTH_A of bram_1024_2_blk_mem_gen_v8_3_5 : entity is 1024;
attribute C_WRITE_DEPTH_B : integer;
attribute C_WRITE_DEPTH_B of bram_1024_2_blk_mem_gen_v8_3_5 : entity is 1024;
attribute C_WRITE_MODE_A : string;
attribute C_WRITE_MODE_A of bram_1024_2_blk_mem_gen_v8_3_5 : entity is "WRITE_FIRST";
attribute C_WRITE_MODE_B : string;
attribute C_WRITE_MODE_B of bram_1024_2_blk_mem_gen_v8_3_5 : entity is "WRITE_FIRST";
attribute C_WRITE_WIDTH_A : integer;
attribute C_WRITE_WIDTH_A of bram_1024_2_blk_mem_gen_v8_3_5 : entity is 20;
attribute C_WRITE_WIDTH_B : integer;
attribute C_WRITE_WIDTH_B of bram_1024_2_blk_mem_gen_v8_3_5 : entity is 20;
attribute C_XDEVICEFAMILY : string;
attribute C_XDEVICEFAMILY of bram_1024_2_blk_mem_gen_v8_3_5 : entity is "zynq";
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of bram_1024_2_blk_mem_gen_v8_3_5 : entity is "blk_mem_gen_v8_3_5";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of bram_1024_2_blk_mem_gen_v8_3_5 : entity is "yes";
end bram_1024_2_blk_mem_gen_v8_3_5;
architecture STRUCTURE of bram_1024_2_blk_mem_gen_v8_3_5 is
signal \<const0>\ : STD_LOGIC;
begin
dbiterr <= \<const0>\;
doutb(19) <= \<const0>\;
doutb(18) <= \<const0>\;
doutb(17) <= \<const0>\;
doutb(16) <= \<const0>\;
doutb(15) <= \<const0>\;
doutb(14) <= \<const0>\;
doutb(13) <= \<const0>\;
doutb(12) <= \<const0>\;
doutb(11) <= \<const0>\;
doutb(10) <= \<const0>\;
doutb(9) <= \<const0>\;
doutb(8) <= \<const0>\;
doutb(7) <= \<const0>\;
doutb(6) <= \<const0>\;
doutb(5) <= \<const0>\;
doutb(4) <= \<const0>\;
doutb(3) <= \<const0>\;
doutb(2) <= \<const0>\;
doutb(1) <= \<const0>\;
doutb(0) <= \<const0>\;
rdaddrecc(9) <= \<const0>\;
rdaddrecc(8) <= \<const0>\;
rdaddrecc(7) <= \<const0>\;
rdaddrecc(6) <= \<const0>\;
rdaddrecc(5) <= \<const0>\;
rdaddrecc(4) <= \<const0>\;
rdaddrecc(3) <= \<const0>\;
rdaddrecc(2) <= \<const0>\;
rdaddrecc(1) <= \<const0>\;
rdaddrecc(0) <= \<const0>\;
rsta_busy <= \<const0>\;
rstb_busy <= \<const0>\;
s_axi_arready <= \<const0>\;
s_axi_awready <= \<const0>\;
s_axi_bid(3) <= \<const0>\;
s_axi_bid(2) <= \<const0>\;
s_axi_bid(1) <= \<const0>\;
s_axi_bid(0) <= \<const0>\;
s_axi_bresp(1) <= \<const0>\;
s_axi_bresp(0) <= \<const0>\;
s_axi_bvalid <= \<const0>\;
s_axi_dbiterr <= \<const0>\;
s_axi_rdaddrecc(9) <= \<const0>\;
s_axi_rdaddrecc(8) <= \<const0>\;
s_axi_rdaddrecc(7) <= \<const0>\;
s_axi_rdaddrecc(6) <= \<const0>\;
s_axi_rdaddrecc(5) <= \<const0>\;
s_axi_rdaddrecc(4) <= \<const0>\;
s_axi_rdaddrecc(3) <= \<const0>\;
s_axi_rdaddrecc(2) <= \<const0>\;
s_axi_rdaddrecc(1) <= \<const0>\;
s_axi_rdaddrecc(0) <= \<const0>\;
s_axi_rdata(19) <= \<const0>\;
s_axi_rdata(18) <= \<const0>\;
s_axi_rdata(17) <= \<const0>\;
s_axi_rdata(16) <= \<const0>\;
s_axi_rdata(15) <= \<const0>\;
s_axi_rdata(14) <= \<const0>\;
s_axi_rdata(13) <= \<const0>\;
s_axi_rdata(12) <= \<const0>\;
s_axi_rdata(11) <= \<const0>\;
s_axi_rdata(10) <= \<const0>\;
s_axi_rdata(9) <= \<const0>\;
s_axi_rdata(8) <= \<const0>\;
s_axi_rdata(7) <= \<const0>\;
s_axi_rdata(6) <= \<const0>\;
s_axi_rdata(5) <= \<const0>\;
s_axi_rdata(4) <= \<const0>\;
s_axi_rdata(3) <= \<const0>\;
s_axi_rdata(2) <= \<const0>\;
s_axi_rdata(1) <= \<const0>\;
s_axi_rdata(0) <= \<const0>\;
s_axi_rid(3) <= \<const0>\;
s_axi_rid(2) <= \<const0>\;
s_axi_rid(1) <= \<const0>\;
s_axi_rid(0) <= \<const0>\;
s_axi_rlast <= \<const0>\;
s_axi_rresp(1) <= \<const0>\;
s_axi_rresp(0) <= \<const0>\;
s_axi_rvalid <= \<const0>\;
s_axi_sbiterr <= \<const0>\;
s_axi_wready <= \<const0>\;
sbiterr <= \<const0>\;
GND: unisim.vcomponents.GND
port map (
G => \<const0>\
);
inst_blk_mem_gen: entity work.bram_1024_2_blk_mem_gen_v8_3_5_synth
port map (
addra(9 downto 0) => addra(9 downto 0),
clka => clka,
dina(19 downto 0) => dina(19 downto 0),
douta(19 downto 0) => douta(19 downto 0),
ena => ena,
wea(0) => wea(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity bram_1024_2 is
port (
clka : in STD_LOGIC;
ena : in STD_LOGIC;
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
addra : in STD_LOGIC_VECTOR ( 9 downto 0 );
dina : in STD_LOGIC_VECTOR ( 19 downto 0 );
douta : out STD_LOGIC_VECTOR ( 19 downto 0 )
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of bram_1024_2 : entity is true;
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of bram_1024_2 : entity is "bram_1024_2,blk_mem_gen_v8_3_5,{}";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of bram_1024_2 : entity is "yes";
attribute x_core_info : string;
attribute x_core_info of bram_1024_2 : entity is "blk_mem_gen_v8_3_5,Vivado 2016.4";
end bram_1024_2;
architecture STRUCTURE of bram_1024_2 is
signal NLW_U0_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_rsta_busy_UNCONNECTED : STD_LOGIC;
signal NLW_U0_rstb_busy_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_arready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_awready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_bvalid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_rlast_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_rvalid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_wready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_doutb_UNCONNECTED : STD_LOGIC_VECTOR ( 19 downto 0 );
signal NLW_U0_rdaddrecc_UNCONNECTED : STD_LOGIC_VECTOR ( 9 downto 0 );
signal NLW_U0_s_axi_bid_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_s_axi_bresp_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_U0_s_axi_rdaddrecc_UNCONNECTED : STD_LOGIC_VECTOR ( 9 downto 0 );
signal NLW_U0_s_axi_rdata_UNCONNECTED : STD_LOGIC_VECTOR ( 19 downto 0 );
signal NLW_U0_s_axi_rid_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_s_axi_rresp_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute C_ADDRA_WIDTH : integer;
attribute C_ADDRA_WIDTH of U0 : label is 10;
attribute C_ADDRB_WIDTH : integer;
attribute C_ADDRB_WIDTH of U0 : label is 10;
attribute C_ALGORITHM : integer;
attribute C_ALGORITHM of U0 : label is 1;
attribute C_AXI_ID_WIDTH : integer;
attribute C_AXI_ID_WIDTH of U0 : label is 4;
attribute C_AXI_SLAVE_TYPE : integer;
attribute C_AXI_SLAVE_TYPE of U0 : label is 0;
attribute C_AXI_TYPE : integer;
attribute C_AXI_TYPE of U0 : label is 1;
attribute C_BYTE_SIZE : integer;
attribute C_BYTE_SIZE of U0 : label is 9;
attribute C_COMMON_CLK : integer;
attribute C_COMMON_CLK of U0 : label is 0;
attribute C_COUNT_18K_BRAM : string;
attribute C_COUNT_18K_BRAM of U0 : label is "0";
attribute C_COUNT_36K_BRAM : string;
attribute C_COUNT_36K_BRAM of U0 : label is "1";
attribute C_CTRL_ECC_ALGO : string;
attribute C_CTRL_ECC_ALGO of U0 : label is "NONE";
attribute C_DEFAULT_DATA : string;
attribute C_DEFAULT_DATA of U0 : label is "0";
attribute C_DISABLE_WARN_BHV_COLL : integer;
attribute C_DISABLE_WARN_BHV_COLL of U0 : label is 0;
attribute C_DISABLE_WARN_BHV_RANGE : integer;
attribute C_DISABLE_WARN_BHV_RANGE of U0 : label is 0;
attribute C_ELABORATION_DIR : string;
attribute C_ELABORATION_DIR of U0 : label is "./";
attribute C_ENABLE_32BIT_ADDRESS : integer;
attribute C_ENABLE_32BIT_ADDRESS of U0 : label is 0;
attribute C_EN_DEEPSLEEP_PIN : integer;
attribute C_EN_DEEPSLEEP_PIN of U0 : label is 0;
attribute C_EN_ECC_PIPE : integer;
attribute C_EN_ECC_PIPE of U0 : label is 0;
attribute C_EN_RDADDRA_CHG : integer;
attribute C_EN_RDADDRA_CHG of U0 : label is 0;
attribute C_EN_RDADDRB_CHG : integer;
attribute C_EN_RDADDRB_CHG of U0 : label is 0;
attribute C_EN_SAFETY_CKT : integer;
attribute C_EN_SAFETY_CKT of U0 : label is 0;
attribute C_EN_SHUTDOWN_PIN : integer;
attribute C_EN_SHUTDOWN_PIN of U0 : label is 0;
attribute C_EN_SLEEP_PIN : integer;
attribute C_EN_SLEEP_PIN of U0 : label is 0;
attribute C_EST_POWER_SUMMARY : string;
attribute C_EST_POWER_SUMMARY of U0 : label is "Estimated Power for IP : 2.74095 mW";
attribute C_FAMILY : string;
attribute C_FAMILY of U0 : label is "zynq";
attribute C_HAS_AXI_ID : integer;
attribute C_HAS_AXI_ID of U0 : label is 0;
attribute C_HAS_ENA : integer;
attribute C_HAS_ENA of U0 : label is 1;
attribute C_HAS_ENB : integer;
attribute C_HAS_ENB of U0 : label is 0;
attribute C_HAS_INJECTERR : integer;
attribute C_HAS_INJECTERR of U0 : label is 0;
attribute C_HAS_MEM_OUTPUT_REGS_A : integer;
attribute C_HAS_MEM_OUTPUT_REGS_A of U0 : label is 1;
attribute C_HAS_MEM_OUTPUT_REGS_B : integer;
attribute C_HAS_MEM_OUTPUT_REGS_B of U0 : label is 0;
attribute C_HAS_MUX_OUTPUT_REGS_A : integer;
attribute C_HAS_MUX_OUTPUT_REGS_A of U0 : label is 0;
attribute C_HAS_MUX_OUTPUT_REGS_B : integer;
attribute C_HAS_MUX_OUTPUT_REGS_B of U0 : label is 0;
attribute C_HAS_REGCEA : integer;
attribute C_HAS_REGCEA of U0 : label is 0;
attribute C_HAS_REGCEB : integer;
attribute C_HAS_REGCEB of U0 : label is 0;
attribute C_HAS_RSTA : integer;
attribute C_HAS_RSTA of U0 : label is 0;
attribute C_HAS_RSTB : integer;
attribute C_HAS_RSTB of U0 : label is 0;
attribute C_HAS_SOFTECC_INPUT_REGS_A : integer;
attribute C_HAS_SOFTECC_INPUT_REGS_A of U0 : label is 0;
attribute C_HAS_SOFTECC_OUTPUT_REGS_B : integer;
attribute C_HAS_SOFTECC_OUTPUT_REGS_B of U0 : label is 0;
attribute C_INITA_VAL : string;
attribute C_INITA_VAL of U0 : label is "0";
attribute C_INITB_VAL : string;
attribute C_INITB_VAL of U0 : label is "0";
attribute C_INIT_FILE : string;
attribute C_INIT_FILE of U0 : label is "bram_1024_2.mem";
attribute C_INIT_FILE_NAME : string;
attribute C_INIT_FILE_NAME of U0 : label is "bram_1024_2.mif";
attribute C_INTERFACE_TYPE : integer;
attribute C_INTERFACE_TYPE of U0 : label is 0;
attribute C_LOAD_INIT_FILE : integer;
attribute C_LOAD_INIT_FILE of U0 : label is 1;
attribute C_MEM_TYPE : integer;
attribute C_MEM_TYPE of U0 : label is 0;
attribute C_MUX_PIPELINE_STAGES : integer;
attribute C_MUX_PIPELINE_STAGES of U0 : label is 0;
attribute C_PRIM_TYPE : integer;
attribute C_PRIM_TYPE of U0 : label is 1;
attribute C_READ_DEPTH_A : integer;
attribute C_READ_DEPTH_A of U0 : label is 1024;
attribute C_READ_DEPTH_B : integer;
attribute C_READ_DEPTH_B of U0 : label is 1024;
attribute C_READ_WIDTH_A : integer;
attribute C_READ_WIDTH_A of U0 : label is 20;
attribute C_READ_WIDTH_B : integer;
attribute C_READ_WIDTH_B of U0 : label is 20;
attribute C_RSTRAM_A : integer;
attribute C_RSTRAM_A of U0 : label is 0;
attribute C_RSTRAM_B : integer;
attribute C_RSTRAM_B of U0 : label is 0;
attribute C_RST_PRIORITY_A : string;
attribute C_RST_PRIORITY_A of U0 : label is "CE";
attribute C_RST_PRIORITY_B : string;
attribute C_RST_PRIORITY_B of U0 : label is "CE";
attribute C_SIM_COLLISION_CHECK : string;
attribute C_SIM_COLLISION_CHECK of U0 : label is "ALL";
attribute C_USE_BRAM_BLOCK : integer;
attribute C_USE_BRAM_BLOCK of U0 : label is 0;
attribute C_USE_BYTE_WEA : integer;
attribute C_USE_BYTE_WEA of U0 : label is 0;
attribute C_USE_BYTE_WEB : integer;
attribute C_USE_BYTE_WEB of U0 : label is 0;
attribute C_USE_DEFAULT_DATA : integer;
attribute C_USE_DEFAULT_DATA of U0 : label is 0;
attribute C_USE_ECC : integer;
attribute C_USE_ECC of U0 : label is 0;
attribute C_USE_SOFTECC : integer;
attribute C_USE_SOFTECC of U0 : label is 0;
attribute C_USE_URAM : integer;
attribute C_USE_URAM of U0 : label is 0;
attribute C_WEA_WIDTH : integer;
attribute C_WEA_WIDTH of U0 : label is 1;
attribute C_WEB_WIDTH : integer;
attribute C_WEB_WIDTH of U0 : label is 1;
attribute C_WRITE_DEPTH_A : integer;
attribute C_WRITE_DEPTH_A of U0 : label is 1024;
attribute C_WRITE_DEPTH_B : integer;
attribute C_WRITE_DEPTH_B of U0 : label is 1024;
attribute C_WRITE_MODE_A : string;
attribute C_WRITE_MODE_A of U0 : label is "WRITE_FIRST";
attribute C_WRITE_MODE_B : string;
attribute C_WRITE_MODE_B of U0 : label is "WRITE_FIRST";
attribute C_WRITE_WIDTH_A : integer;
attribute C_WRITE_WIDTH_A of U0 : label is 20;
attribute C_WRITE_WIDTH_B : integer;
attribute C_WRITE_WIDTH_B of U0 : label is 20;
attribute C_XDEVICEFAMILY : string;
attribute C_XDEVICEFAMILY of U0 : label is "zynq";
attribute downgradeipidentifiedwarnings of U0 : label is "yes";
begin
U0: entity work.bram_1024_2_blk_mem_gen_v8_3_5
port map (
addra(9 downto 0) => addra(9 downto 0),
addrb(9 downto 0) => B"0000000000",
clka => clka,
clkb => '0',
dbiterr => NLW_U0_dbiterr_UNCONNECTED,
deepsleep => '0',
dina(19 downto 0) => dina(19 downto 0),
dinb(19 downto 0) => B"00000000000000000000",
douta(19 downto 0) => douta(19 downto 0),
doutb(19 downto 0) => NLW_U0_doutb_UNCONNECTED(19 downto 0),
eccpipece => '0',
ena => ena,
enb => '0',
injectdbiterr => '0',
injectsbiterr => '0',
rdaddrecc(9 downto 0) => NLW_U0_rdaddrecc_UNCONNECTED(9 downto 0),
regcea => '0',
regceb => '0',
rsta => '0',
rsta_busy => NLW_U0_rsta_busy_UNCONNECTED,
rstb => '0',
rstb_busy => NLW_U0_rstb_busy_UNCONNECTED,
s_aclk => '0',
s_aresetn => '0',
s_axi_araddr(31 downto 0) => B"00000000000000000000000000000000",
s_axi_arburst(1 downto 0) => B"00",
s_axi_arid(3 downto 0) => B"0000",
s_axi_arlen(7 downto 0) => B"00000000",
s_axi_arready => NLW_U0_s_axi_arready_UNCONNECTED,
s_axi_arsize(2 downto 0) => B"000",
s_axi_arvalid => '0',
s_axi_awaddr(31 downto 0) => B"00000000000000000000000000000000",
s_axi_awburst(1 downto 0) => B"00",
s_axi_awid(3 downto 0) => B"0000",
s_axi_awlen(7 downto 0) => B"00000000",
s_axi_awready => NLW_U0_s_axi_awready_UNCONNECTED,
s_axi_awsize(2 downto 0) => B"000",
s_axi_awvalid => '0',
s_axi_bid(3 downto 0) => NLW_U0_s_axi_bid_UNCONNECTED(3 downto 0),
s_axi_bready => '0',
s_axi_bresp(1 downto 0) => NLW_U0_s_axi_bresp_UNCONNECTED(1 downto 0),
s_axi_bvalid => NLW_U0_s_axi_bvalid_UNCONNECTED,
s_axi_dbiterr => NLW_U0_s_axi_dbiterr_UNCONNECTED,
s_axi_injectdbiterr => '0',
s_axi_injectsbiterr => '0',
s_axi_rdaddrecc(9 downto 0) => NLW_U0_s_axi_rdaddrecc_UNCONNECTED(9 downto 0),
s_axi_rdata(19 downto 0) => NLW_U0_s_axi_rdata_UNCONNECTED(19 downto 0),
s_axi_rid(3 downto 0) => NLW_U0_s_axi_rid_UNCONNECTED(3 downto 0),
s_axi_rlast => NLW_U0_s_axi_rlast_UNCONNECTED,
s_axi_rready => '0',
s_axi_rresp(1 downto 0) => NLW_U0_s_axi_rresp_UNCONNECTED(1 downto 0),
s_axi_rvalid => NLW_U0_s_axi_rvalid_UNCONNECTED,
s_axi_sbiterr => NLW_U0_s_axi_sbiterr_UNCONNECTED,
s_axi_wdata(19 downto 0) => B"00000000000000000000",
s_axi_wlast => '0',
s_axi_wready => NLW_U0_s_axi_wready_UNCONNECTED,
s_axi_wstrb(0) => '0',
s_axi_wvalid => '0',
sbiterr => NLW_U0_sbiterr_UNCONNECTED,
shutdown => '0',
sleep => '0',
wea(0) => wea(0),
web(0) => '0'
);
end STRUCTURE;
| unlicense | dcc718b28f3037af1de9e982ec8b6ece | 0.698719 | 3.459393 | false | false | false | false |
jairov4/accel-oil | solution_virtex5_plb/syn/vhdl/nfa_accept_samples_generic_hw_result.vhd | 1 | 3,206 | -- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2014.1
-- Copyright (C) 2014 Xilinx Inc. All rights reserved.
--
-- ==============================================================
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity nfa_accept_samples_generic_hw_result_ram is
generic(
mem_type : string := "distributed";
dwidth : integer := 1;
awidth : integer := 4;
mem_size : integer := 16
);
port (
addr0 : in std_logic_vector(awidth-1 downto 0);
ce0 : in std_logic;
d0 : in std_logic_vector(dwidth-1 downto 0);
we0 : in std_logic;
q0 : out std_logic_vector(dwidth-1 downto 0);
clk : in std_logic
);
end entity;
architecture rtl of nfa_accept_samples_generic_hw_result_ram is
signal addr0_tmp : std_logic_vector(awidth-1 downto 0);
type mem_array is array (0 to mem_size-1) of std_logic_vector (dwidth-1 downto 0);
shared variable ram : mem_array;
attribute syn_ramstyle : string;
attribute syn_ramstyle of ram : variable is "select_ram";
attribute ram_style : string;
attribute ram_style of ram : variable is mem_type;
attribute EQUIVALENT_REGISTER_REMOVAL : string;
begin
memory_access_guard_0: process (addr0)
begin
addr0_tmp <= addr0;
--synthesis translate_off
if (CONV_INTEGER(addr0) > mem_size-1) then
addr0_tmp <= (others => '0');
else
addr0_tmp <= addr0;
end if;
--synthesis translate_on
end process;
p_memory_access_0: process (clk)
begin
if (clk'event and clk = '1') then
if (ce0 = '1') then
if (we0 = '1') then
ram(CONV_INTEGER(addr0_tmp)) := d0;
end if;
q0 <= ram(CONV_INTEGER(addr0_tmp));
end if;
end if;
end process;
end rtl;
Library IEEE;
use IEEE.std_logic_1164.all;
entity nfa_accept_samples_generic_hw_result is
generic (
DataWidth : INTEGER := 1;
AddressRange : INTEGER := 16;
AddressWidth : INTEGER := 4);
port (
reset : IN STD_LOGIC;
clk : IN STD_LOGIC;
address0 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0);
ce0 : IN STD_LOGIC;
we0 : IN STD_LOGIC;
d0 : IN STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0);
q0 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0));
end entity;
architecture arch of nfa_accept_samples_generic_hw_result is
component nfa_accept_samples_generic_hw_result_ram is
port (
clk : IN STD_LOGIC;
addr0 : IN STD_LOGIC_VECTOR;
ce0 : IN STD_LOGIC;
d0 : IN STD_LOGIC_VECTOR;
we0 : IN STD_LOGIC;
q0 : OUT STD_LOGIC_VECTOR);
end component;
begin
nfa_accept_samples_generic_hw_result_ram_U : component nfa_accept_samples_generic_hw_result_ram
port map (
clk => clk,
addr0 => address0,
ce0 => ce0,
d0 => d0,
we0 => we0,
q0 => q0);
end architecture;
| lgpl-3.0 | ed6bc27477fdead22796e822ae788718 | 0.556457 | 3.554324 | false | false | false | false |
grwlf/vsim | vhdl/IEEE/synopsys/std_logic_arith.vhdl | 1 | 70,086 | --------------------------------------------------------------------------
-- --
-- Copyright (c) 1990,1991,1992 by Synopsys, Inc. All rights reserved. --
-- --
-- This source file may be used and distributed without restriction --
-- provided that this copyright statement is not removed from the file --
-- and that any derivative work contains this copyright notice. --
-- --
-- Package name: STD_LOGIC_ARITH --
-- --
-- Purpose: --
-- A set of arithemtic, conversion, and comparison functions --
-- for SIGNED, UNSIGNED, SMALL_INT, INTEGER, --
-- STD_ULOGIC, STD_LOGIC, and STD_LOGIC_VECTOR. --
-- --
--------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
package std_logic_arith is
type UNSIGNED is array (NATURAL range <>) of STD_LOGIC;
type SIGNED is array (NATURAL range <>) of STD_LOGIC;
subtype SMALL_INT is INTEGER range 0 to 1;
function "+"(L: UNSIGNED; R: UNSIGNED) return UNSIGNED;
function "+"(L: SIGNED; R: SIGNED) return SIGNED;
function "+"(L: UNSIGNED; R: SIGNED) return SIGNED;
function "+"(L: SIGNED; R: UNSIGNED) return SIGNED;
function "+"(L: UNSIGNED; R: INTEGER) return UNSIGNED;
function "+"(L: INTEGER; R: UNSIGNED) return UNSIGNED;
function "+"(L: SIGNED; R: INTEGER) return SIGNED;
function "+"(L: INTEGER; R: SIGNED) return SIGNED;
function "+"(L: UNSIGNED; R: STD_ULOGIC) return UNSIGNED;
function "+"(L: STD_ULOGIC; R: UNSIGNED) return UNSIGNED;
function "+"(L: SIGNED; R: STD_ULOGIC) return SIGNED;
function "+"(L: STD_ULOGIC; R: SIGNED) return SIGNED;
function "+"(L: UNSIGNED; R: UNSIGNED) return STD_LOGIC_VECTOR;
function "+"(L: SIGNED; R: SIGNED) return STD_LOGIC_VECTOR;
function "+"(L: UNSIGNED; R: SIGNED) return STD_LOGIC_VECTOR;
function "+"(L: SIGNED; R: UNSIGNED) return STD_LOGIC_VECTOR;
function "+"(L: UNSIGNED; R: INTEGER) return STD_LOGIC_VECTOR;
function "+"(L: INTEGER; R: UNSIGNED) return STD_LOGIC_VECTOR;
function "+"(L: SIGNED; R: INTEGER) return STD_LOGIC_VECTOR;
function "+"(L: INTEGER; R: SIGNED) return STD_LOGIC_VECTOR;
function "+"(L: UNSIGNED; R: STD_ULOGIC) return STD_LOGIC_VECTOR;
function "+"(L: STD_ULOGIC; R: UNSIGNED) return STD_LOGIC_VECTOR;
function "+"(L: SIGNED; R: STD_ULOGIC) return STD_LOGIC_VECTOR;
function "+"(L: STD_ULOGIC; R: SIGNED) return STD_LOGIC_VECTOR;
function "-"(L: UNSIGNED; R: UNSIGNED) return UNSIGNED;
function "-"(L: SIGNED; R: SIGNED) return SIGNED;
function "-"(L: UNSIGNED; R: SIGNED) return SIGNED;
function "-"(L: SIGNED; R: UNSIGNED) return SIGNED;
function "-"(L: UNSIGNED; R: INTEGER) return UNSIGNED;
function "-"(L: INTEGER; R: UNSIGNED) return UNSIGNED;
function "-"(L: SIGNED; R: INTEGER) return SIGNED;
function "-"(L: INTEGER; R: SIGNED) return SIGNED;
function "-"(L: UNSIGNED; R: STD_ULOGIC) return UNSIGNED;
function "-"(L: STD_ULOGIC; R: UNSIGNED) return UNSIGNED;
function "-"(L: SIGNED; R: STD_ULOGIC) return SIGNED;
function "-"(L: STD_ULOGIC; R: SIGNED) return SIGNED;
function "-"(L: UNSIGNED; R: UNSIGNED) return STD_LOGIC_VECTOR;
function "-"(L: SIGNED; R: SIGNED) return STD_LOGIC_VECTOR;
function "-"(L: UNSIGNED; R: SIGNED) return STD_LOGIC_VECTOR;
function "-"(L: SIGNED; R: UNSIGNED) return STD_LOGIC_VECTOR;
function "-"(L: UNSIGNED; R: INTEGER) return STD_LOGIC_VECTOR;
function "-"(L: INTEGER; R: UNSIGNED) return STD_LOGIC_VECTOR;
function "-"(L: SIGNED; R: INTEGER) return STD_LOGIC_VECTOR;
function "-"(L: INTEGER; R: SIGNED) return STD_LOGIC_VECTOR;
function "-"(L: UNSIGNED; R: STD_ULOGIC) return STD_LOGIC_VECTOR;
function "-"(L: STD_ULOGIC; R: UNSIGNED) return STD_LOGIC_VECTOR;
function "-"(L: SIGNED; R: STD_ULOGIC) return STD_LOGIC_VECTOR;
function "-"(L: STD_ULOGIC; R: SIGNED) return STD_LOGIC_VECTOR;
function "+"(L: UNSIGNED) return UNSIGNED;
function "+"(L: SIGNED) return SIGNED;
function "-"(L: SIGNED) return SIGNED;
function "ABS"(L: SIGNED) return SIGNED;
function "+"(L: UNSIGNED) return STD_LOGIC_VECTOR;
function "+"(L: SIGNED) return STD_LOGIC_VECTOR;
function "-"(L: SIGNED) return STD_LOGIC_VECTOR;
function "ABS"(L: SIGNED) return STD_LOGIC_VECTOR;
function "*"(L: UNSIGNED; R: UNSIGNED) return UNSIGNED;
function "*"(L: SIGNED; R: SIGNED) return SIGNED;
function "*"(L: SIGNED; R: UNSIGNED) return SIGNED;
function "*"(L: UNSIGNED; R: SIGNED) return SIGNED;
function "*"(L: UNSIGNED; R: UNSIGNED) return STD_LOGIC_VECTOR;
function "*"(L: SIGNED; R: SIGNED) return STD_LOGIC_VECTOR;
function "*"(L: SIGNED; R: UNSIGNED) return STD_LOGIC_VECTOR;
function "*"(L: UNSIGNED; R: SIGNED) return STD_LOGIC_VECTOR;
function "<"(L: UNSIGNED; R: UNSIGNED) return BOOLEAN;
function "<"(L: SIGNED; R: SIGNED) return BOOLEAN;
function "<"(L: UNSIGNED; R: SIGNED) return BOOLEAN;
function "<"(L: SIGNED; R: UNSIGNED) return BOOLEAN;
function "<"(L: UNSIGNED; R: INTEGER) return BOOLEAN;
function "<"(L: INTEGER; R: UNSIGNED) return BOOLEAN;
function "<"(L: SIGNED; R: INTEGER) return BOOLEAN;
function "<"(L: INTEGER; R: SIGNED) return BOOLEAN;
function "<="(L: UNSIGNED; R: UNSIGNED) return BOOLEAN;
function "<="(L: SIGNED; R: SIGNED) return BOOLEAN;
function "<="(L: UNSIGNED; R: SIGNED) return BOOLEAN;
function "<="(L: SIGNED; R: UNSIGNED) return BOOLEAN;
function "<="(L: UNSIGNED; R: INTEGER) return BOOLEAN;
function "<="(L: INTEGER; R: UNSIGNED) return BOOLEAN;
function "<="(L: SIGNED; R: INTEGER) return BOOLEAN;
function "<="(L: INTEGER; R: SIGNED) return BOOLEAN;
function ">"(L: UNSIGNED; R: UNSIGNED) return BOOLEAN;
function ">"(L: SIGNED; R: SIGNED) return BOOLEAN;
function ">"(L: UNSIGNED; R: SIGNED) return BOOLEAN;
function ">"(L: SIGNED; R: UNSIGNED) return BOOLEAN;
function ">"(L: UNSIGNED; R: INTEGER) return BOOLEAN;
function ">"(L: INTEGER; R: UNSIGNED) return BOOLEAN;
function ">"(L: SIGNED; R: INTEGER) return BOOLEAN;
function ">"(L: INTEGER; R: SIGNED) return BOOLEAN;
function ">="(L: UNSIGNED; R: UNSIGNED) return BOOLEAN;
function ">="(L: SIGNED; R: SIGNED) return BOOLEAN;
function ">="(L: UNSIGNED; R: SIGNED) return BOOLEAN;
function ">="(L: SIGNED; R: UNSIGNED) return BOOLEAN;
function ">="(L: UNSIGNED; R: INTEGER) return BOOLEAN;
function ">="(L: INTEGER; R: UNSIGNED) return BOOLEAN;
function ">="(L: SIGNED; R: INTEGER) return BOOLEAN;
function ">="(L: INTEGER; R: SIGNED) return BOOLEAN;
function "="(L: UNSIGNED; R: UNSIGNED) return BOOLEAN;
function "="(L: SIGNED; R: SIGNED) return BOOLEAN;
function "="(L: UNSIGNED; R: SIGNED) return BOOLEAN;
function "="(L: SIGNED; R: UNSIGNED) return BOOLEAN;
function "="(L: UNSIGNED; R: INTEGER) return BOOLEAN;
function "="(L: INTEGER; R: UNSIGNED) return BOOLEAN;
function "="(L: SIGNED; R: INTEGER) return BOOLEAN;
function "="(L: INTEGER; R: SIGNED) return BOOLEAN;
function "/="(L: UNSIGNED; R: UNSIGNED) return BOOLEAN;
function "/="(L: SIGNED; R: SIGNED) return BOOLEAN;
function "/="(L: UNSIGNED; R: SIGNED) return BOOLEAN;
function "/="(L: SIGNED; R: UNSIGNED) return BOOLEAN;
function "/="(L: UNSIGNED; R: INTEGER) return BOOLEAN;
function "/="(L: INTEGER; R: UNSIGNED) return BOOLEAN;
function "/="(L: SIGNED; R: INTEGER) return BOOLEAN;
function "/="(L: INTEGER; R: SIGNED) return BOOLEAN;
function SHL(ARG: UNSIGNED; COUNT: UNSIGNED) return UNSIGNED;
function SHL(ARG: SIGNED; COUNT: UNSIGNED) return SIGNED;
function SHR(ARG: UNSIGNED; COUNT: UNSIGNED) return UNSIGNED;
function SHR(ARG: SIGNED; COUNT: UNSIGNED) return SIGNED;
function CONV_INTEGER(ARG: INTEGER) return INTEGER;
function CONV_INTEGER(ARG: UNSIGNED) return INTEGER;
function CONV_INTEGER(ARG: SIGNED) return INTEGER;
function CONV_INTEGER(ARG: STD_ULOGIC) return SMALL_INT;
function CONV_UNSIGNED(ARG: INTEGER; SIZE: INTEGER) return UNSIGNED;
function CONV_UNSIGNED(ARG: UNSIGNED; SIZE: INTEGER) return UNSIGNED;
function CONV_UNSIGNED(ARG: SIGNED; SIZE: INTEGER) return UNSIGNED;
function CONV_UNSIGNED(ARG: STD_ULOGIC; SIZE: INTEGER) return UNSIGNED;
function CONV_SIGNED(ARG: INTEGER; SIZE: INTEGER) return SIGNED;
function CONV_SIGNED(ARG: UNSIGNED; SIZE: INTEGER) return SIGNED;
function CONV_SIGNED(ARG: SIGNED; SIZE: INTEGER) return SIGNED;
function CONV_SIGNED(ARG: STD_ULOGIC; SIZE: INTEGER) return SIGNED;
function CONV_STD_LOGIC_VECTOR(ARG: INTEGER; SIZE: INTEGER)
return STD_LOGIC_VECTOR;
function CONV_STD_LOGIC_VECTOR(ARG: UNSIGNED; SIZE: INTEGER)
return STD_LOGIC_VECTOR;
function CONV_STD_LOGIC_VECTOR(ARG: SIGNED; SIZE: INTEGER)
return STD_LOGIC_VECTOR;
function CONV_STD_LOGIC_VECTOR(ARG: STD_ULOGIC; SIZE: INTEGER)
return STD_LOGIC_VECTOR;
-- zero extend STD_LOGIC_VECTOR (ARG) to SIZE,
-- SIZE < 0 is same as SIZE = 0
-- returns STD_LOGIC_VECTOR(SIZE-1 downto 0)
function EXT(ARG: STD_LOGIC_VECTOR; SIZE: INTEGER) return STD_LOGIC_VECTOR;
-- sign extend STD_LOGIC_VECTOR (ARG) to SIZE,
-- SIZE < 0 is same as SIZE = 0
-- return STD_LOGIC_VECTOR(SIZE-1 downto 0)
function SXT(ARG: STD_LOGIC_VECTOR; SIZE: INTEGER) return STD_LOGIC_VECTOR;
end Std_logic_arith;
library IEEE;
use IEEE.std_logic_1164.all;
package body std_logic_arith is
function max(L, R: INTEGER) return INTEGER is
begin
if L > R then
return L;
else
return R;
end if;
end;
function min(L, R: INTEGER) return INTEGER is
begin
if L < R then
return L;
else
return R;
end if;
end;
-- synopsys synthesis_off
type tbl_type is array (STD_ULOGIC) of STD_ULOGIC;
constant tbl_BINARY : tbl_type :=
('X', 'X', '0', '1', 'X', 'X', '0', '1', 'X');
-- synopsys synthesis_on
-- synopsys synthesis_off
type tbl_mvl9_boolean is array (STD_ULOGIC) of boolean;
constant IS_X : tbl_mvl9_boolean :=
(true, true, false, false, true, true, false, false, true);
-- synopsys synthesis_on
function MAKE_BINARY(A : STD_ULOGIC) return STD_ULOGIC is
-- synopsys built_in SYN_FEED_THRU
begin
-- synopsys synthesis_off
if (IS_X(A)) then
assert false
report "There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es)."
severity warning;
return ('X');
end if;
return tbl_BINARY(A);
-- synopsys synthesis_on
end;
function MAKE_BINARY(A : UNSIGNED) return UNSIGNED is
-- synopsys built_in SYN_FEED_THRU
variable one_bit : STD_ULOGIC;
variable result : UNSIGNED (A'range);
begin
-- synopsys synthesis_off
for i in A'range loop
if (IS_X(A(i))) then
assert false
report "There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es)."
severity warning;
result := (others => 'X');
return result;
end if;
result(i) := tbl_BINARY(A(i));
end loop;
return result;
-- synopsys synthesis_on
end;
function MAKE_BINARY(A : UNSIGNED) return SIGNED is
-- synopsys built_in SYN_FEED_THRU
variable one_bit : STD_ULOGIC;
variable result : SIGNED (A'range);
begin
-- synopsys synthesis_off
for i in A'range loop
if (IS_X(A(i))) then
assert false
report "There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es)."
severity warning;
result := (others => 'X');
return result;
end if;
result(i) := tbl_BINARY(A(i));
end loop;
return result;
-- synopsys synthesis_on
end;
function MAKE_BINARY(A : SIGNED) return UNSIGNED is
-- synopsys built_in SYN_FEED_THRU
variable one_bit : STD_ULOGIC;
variable result : UNSIGNED (A'range);
begin
-- synopsys synthesis_off
for i in A'range loop
if (IS_X(A(i))) then
assert false
report "There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es)."
severity warning;
result := (others => 'X');
return result;
end if;
result(i) := tbl_BINARY(A(i));
end loop;
return result;
-- synopsys synthesis_on
end;
function MAKE_BINARY(A : SIGNED) return SIGNED is
-- synopsys built_in SYN_FEED_THRU
variable one_bit : STD_ULOGIC;
variable result : SIGNED (A'range);
begin
-- synopsys synthesis_off
for i in A'range loop
if (IS_X(A(i))) then
assert false
report "There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es)."
severity warning;
result := (others => 'X');
return result;
end if;
result(i) := tbl_BINARY(A(i));
end loop;
return result;
-- synopsys synthesis_on
end;
function MAKE_BINARY(A : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
-- synopsys built_in SYN_FEED_THRU
variable one_bit : STD_ULOGIC;
variable result : STD_LOGIC_VECTOR (A'range);
begin
-- synopsys synthesis_off
for i in A'range loop
if (IS_X(A(i))) then
assert false
report "There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es)."
severity warning;
result := (others => 'X');
return result;
end if;
result(i) := tbl_BINARY(A(i));
end loop;
return result;
-- synopsys synthesis_on
end;
function MAKE_BINARY(A : UNSIGNED) return STD_LOGIC_VECTOR is
-- synopsys built_in SYN_FEED_THRU
variable one_bit : STD_ULOGIC;
variable result : STD_LOGIC_VECTOR (A'range);
begin
-- synopsys synthesis_off
for i in A'range loop
if (IS_X(A(i))) then
assert false
report "There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es)."
severity warning;
result := (others => 'X');
return result;
end if;
result(i) := tbl_BINARY(A(i));
end loop;
return result;
-- synopsys synthesis_on
end;
function MAKE_BINARY(A : SIGNED) return STD_LOGIC_VECTOR is
-- synopsys built_in SYN_FEED_THRU
variable one_bit : STD_ULOGIC;
variable result : STD_LOGIC_VECTOR (A'range);
begin
-- synopsys synthesis_off
for i in A'range loop
if (IS_X(A(i))) then
assert false
report "There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es)."
severity warning;
result := (others => 'X');
return result;
end if;
result(i) := tbl_BINARY(A(i));
end loop;
return result;
-- synopsys synthesis_on
end;
-- Type propagation function which returns a signed type with the
-- size of the left arg.
function LEFT_SIGNED_ARG(A,B: SIGNED) return SIGNED is
variable Z: SIGNED (A'left downto 0);
-- pragma return_port_name Z
begin
return(Z);
end;
-- Type propagation function which returns an unsigned type with the
-- size of the left arg.
function LEFT_UNSIGNED_ARG(A,B: UNSIGNED) return UNSIGNED is
variable Z: UNSIGNED (A'left downto 0);
-- pragma return_port_name Z
begin
return(Z);
end;
-- Type propagation function which returns a signed type with the
-- size of the result of a signed multiplication
function MULT_SIGNED_ARG(A,B: SIGNED) return SIGNED is
variable Z: SIGNED ((A'length+B'length-1) downto 0);
-- pragma return_port_name Z
begin
return(Z);
end;
-- Type propagation function which returns an unsigned type with the
-- size of the result of a unsigned multiplication
function MULT_UNSIGNED_ARG(A,B: UNSIGNED) return UNSIGNED is
variable Z: UNSIGNED ((A'length+B'length-1) downto 0);
-- pragma return_port_name Z
begin
return(Z);
end;
function mult(A,B: SIGNED) return SIGNED is
variable BA: SIGNED((A'length+B'length-1) downto 0);
variable PA: SIGNED((A'length+B'length-1) downto 0);
variable AA: SIGNED(A'length downto 0);
variable neg: STD_ULOGIC;
constant one : UNSIGNED(1 downto 0) := "01";
-- pragma map_to_operator MULT_TC_OP
-- pragma type_function MULT_SIGNED_ARG
-- pragma return_port_name Z
begin
if (A(A'left) = 'X' or B(B'left) = 'X') then
PA := (others => 'X');
return(PA);
end if;
PA := (others => '0');
neg := B(B'left) xor A(A'left);
BA := CONV_SIGNED(('0' & ABS(B)),(A'length+B'length));
AA := '0' & ABS(A);
for i in 0 to A'length-1 loop
if AA(i) = '1' then
PA := PA+BA;
end if;
BA := SHL(BA,one);
end loop;
if (neg= '1') then
return(-PA);
else
return(PA);
end if;
end;
function mult(A,B: UNSIGNED) return UNSIGNED is
variable BA: UNSIGNED((A'length+B'length-1) downto 0);
variable PA: UNSIGNED((A'length+B'length-1) downto 0);
constant one : UNSIGNED(1 downto 0) := "01";
-- pragma map_to_operator MULT_UNS_OP
-- pragma type_function MULT_UNSIGNED_ARG
-- pragma return_port_name Z
begin
if (A(A'left) = 'X' or B(B'left) = 'X') then
PA := (others => 'X');
return(PA);
end if;
PA := (others => '0');
BA := CONV_UNSIGNED(B,(A'length+B'length));
for i in 0 to A'length-1 loop
if A(i) = '1' then
PA := PA+BA;
end if;
BA := SHL(BA,one);
end loop;
return(PA);
end;
-- subtract two signed numbers of the same length
-- both arrays must have range (msb downto 0)
function minus(A, B: SIGNED) return SIGNED is
variable carry: STD_ULOGIC;
variable BV: STD_ULOGIC_VECTOR (A'left downto 0);
variable sum: SIGNED (A'left downto 0);
-- pragma map_to_operator SUB_TC_OP
-- pragma type_function LEFT_SIGNED_ARG
-- pragma return_port_name Z
begin
if (A(A'left) = 'X' or B(B'left) = 'X') then
sum := (others => 'X');
return(sum);
end if;
carry := '1';
BV := not STD_ULOGIC_VECTOR(B);
for i in 0 to A'left loop
sum(i) := A(i) xor BV(i) xor carry;
carry := (A(i) and BV(i)) or
(A(i) and carry) or
(carry and BV(i));
end loop;
return sum;
end;
-- add two signed numbers of the same length
-- both arrays must have range (msb downto 0)
function plus(A, B: SIGNED) return SIGNED is
variable carry: STD_ULOGIC;
variable BV, sum: SIGNED (A'left downto 0);
-- pragma map_to_operator ADD_TC_OP
-- pragma type_function LEFT_SIGNED_ARG
-- pragma return_port_name Z
begin
if (A(A'left) = 'X' or B(B'left) = 'X') then
sum := (others => 'X');
return(sum);
end if;
carry := '0';
BV := B;
for i in 0 to A'left loop
sum(i) := A(i) xor BV(i) xor carry;
carry := (A(i) and BV(i)) or
(A(i) and carry) or
(carry and BV(i));
end loop;
return sum;
end;
-- subtract two unsigned numbers of the same length
-- both arrays must have range (msb downto 0)
function unsigned_minus(A, B: UNSIGNED) return UNSIGNED is
variable carry: STD_ULOGIC;
variable BV: STD_ULOGIC_VECTOR (A'left downto 0);
variable sum: UNSIGNED (A'left downto 0);
-- pragma map_to_operator SUB_UNS_OP
-- pragma type_function LEFT_UNSIGNED_ARG
-- pragma return_port_name Z
begin
if (A(A'left) = 'X' or B(B'left) = 'X') then
sum := (others => 'X');
return(sum);
end if;
carry := '1';
BV := not STD_ULOGIC_VECTOR(B);
for i in 0 to A'left loop
sum(i) := A(i) xor BV(i) xor carry;
carry := (A(i) and BV(i)) or
(A(i) and carry) or
(carry and BV(i));
end loop;
return sum;
end;
-- add two unsigned numbers of the same length
-- both arrays must have range (msb downto 0)
function unsigned_plus(A, B: UNSIGNED) return UNSIGNED is
variable carry: STD_ULOGIC;
variable BV, sum: UNSIGNED (A'left downto 0);
-- pragma map_to_operator ADD_UNS_OP
-- pragma type_function LEFT_UNSIGNED_ARG
-- pragma return_port_name Z
begin
if (A(A'left) = 'X' or B(B'left) = 'X') then
sum := (others => 'X');
return(sum);
end if;
carry := '0';
BV := B;
for i in 0 to A'left loop
sum(i) := A(i) xor BV(i) xor carry;
carry := (A(i) and BV(i)) or
(A(i) and carry) or
(carry and BV(i));
end loop;
return sum;
end;
function "*"(L: SIGNED; R: SIGNED) return SIGNED is
-- pragma label_applies_to mult
-- synopsys subpgm_id 296
begin
return mult(CONV_SIGNED(L, L'length),
CONV_SIGNED(R, R'length)); -- pragma label mult
end;
function "*"(L: UNSIGNED; R: UNSIGNED) return UNSIGNED is
-- pragma label_applies_to mult
-- synopsys subpgm_id 295
begin
return mult(CONV_UNSIGNED(L, L'length),
CONV_UNSIGNED(R, R'length)); -- pragma label mult
end;
function "*"(L: UNSIGNED; R: SIGNED) return SIGNED is
-- pragma label_applies_to mult
-- synopsys subpgm_id 297
begin
return mult(CONV_SIGNED(L, L'length+1),
CONV_SIGNED(R, R'length)); -- pragma label mult
end;
function "*"(L: SIGNED; R: UNSIGNED) return SIGNED is
-- pragma label_applies_to mult
-- synopsys subpgm_id 298
begin
return mult(CONV_SIGNED(L, L'length),
CONV_SIGNED(R, R'length+1)); -- pragma label mult
end;
function "*"(L: SIGNED; R: SIGNED) return STD_LOGIC_VECTOR is
-- pragma label_applies_to mult
-- synopsys subpgm_id 301
begin
return STD_LOGIC_VECTOR (
mult(-- pragma label mult
CONV_SIGNED(L, L'length), CONV_SIGNED(R, R'length)));
end;
function "*"(L: UNSIGNED; R: UNSIGNED) return STD_LOGIC_VECTOR is
-- pragma label_applies_to mult
-- synopsys subpgm_id 300
begin
return STD_LOGIC_VECTOR (
mult(-- pragma label mult
CONV_UNSIGNED(L, L'length), CONV_UNSIGNED(R, R'length)));
end;
function "*"(L: UNSIGNED; R: SIGNED) return STD_LOGIC_VECTOR is
-- pragma label_applies_to mult
-- synopsys subpgm_id 302
begin
return STD_LOGIC_VECTOR (
mult(-- pragma label mult
CONV_SIGNED(L, L'length+1), CONV_SIGNED(R, R'length)));
end;
function "*"(L: SIGNED; R: UNSIGNED) return STD_LOGIC_VECTOR is
-- pragma label_applies_to mult
-- synopsys subpgm_id 303
begin
return STD_LOGIC_VECTOR (
mult(-- pragma label mult
CONV_SIGNED(L, L'length), CONV_SIGNED(R, R'length+1)));
end;
function "+"(L: UNSIGNED; R: UNSIGNED) return UNSIGNED is
-- pragma label_applies_to plus
-- synopsys subpgm_id 236
constant length: INTEGER := max(L'length, R'length);
begin
return unsigned_plus(CONV_UNSIGNED(L, length),
CONV_UNSIGNED(R, length)); -- pragma label plus
end;
function "+"(L: SIGNED; R: SIGNED) return SIGNED is
-- pragma label_applies_to plus
-- synopsys subpgm_id 237
constant length: INTEGER := max(L'length, R'length);
begin
return plus(CONV_SIGNED(L, length),
CONV_SIGNED(R, length)); -- pragma label plus
end;
function "+"(L: UNSIGNED; R: SIGNED) return SIGNED is
-- pragma label_applies_to plus
-- synopsys subpgm_id 238
constant length: INTEGER := max(L'length + 1, R'length);
begin
return plus(CONV_SIGNED(L, length),
CONV_SIGNED(R, length)); -- pragma label plus
end;
function "+"(L: SIGNED; R: UNSIGNED) return SIGNED is
-- pragma label_applies_to plus
-- synopsys subpgm_id 239
constant length: INTEGER := max(L'length, R'length + 1);
begin
return plus(CONV_SIGNED(L, length),
CONV_SIGNED(R, length)); -- pragma label plus
end;
function "+"(L: UNSIGNED; R: INTEGER) return UNSIGNED is
-- pragma label_applies_to plus
-- synopsys subpgm_id 240
constant length: INTEGER := L'length + 1;
begin
return CONV_UNSIGNED(
plus( -- pragma label plus
CONV_SIGNED(L, length), CONV_SIGNED(R, length)), length-1);
end;
function "+"(L: INTEGER; R: UNSIGNED) return UNSIGNED is
-- pragma label_applies_to plus
-- synopsys subpgm_id 241
constant length: INTEGER := R'length + 1;
begin
return CONV_UNSIGNED(
plus( -- pragma label plus
CONV_SIGNED(L, length), CONV_SIGNED(R, length)), length-1);
end;
function "+"(L: SIGNED; R: INTEGER) return SIGNED is
-- pragma label_applies_to plus
-- synopsys subpgm_id 242
constant length: INTEGER := L'length;
begin
return plus(CONV_SIGNED(L, length),
CONV_SIGNED(R, length)); -- pragma label plus
end;
function "+"(L: INTEGER; R: SIGNED) return SIGNED is
-- pragma label_applies_to plus
-- synopsys subpgm_id 243
constant length: INTEGER := R'length;
begin
return plus(CONV_SIGNED(L, length),
CONV_SIGNED(R, length)); -- pragma label plus
end;
function "+"(L: UNSIGNED; R: STD_ULOGIC) return UNSIGNED is
-- pragma label_applies_to plus
-- synopsys subpgm_id 244
constant length: INTEGER := L'length;
begin
return unsigned_plus(CONV_UNSIGNED(L, length),
CONV_UNSIGNED(R, length)) ; -- pragma label plus
end;
function "+"(L: STD_ULOGIC; R: UNSIGNED) return UNSIGNED is
-- pragma label_applies_to plus
-- synopsys subpgm_id 245
constant length: INTEGER := R'length;
begin
return unsigned_plus(CONV_UNSIGNED(L, length),
CONV_UNSIGNED(R, length)); -- pragma label plus
end;
function "+"(L: SIGNED; R: STD_ULOGIC) return SIGNED is
-- pragma label_applies_to plus
-- synopsys subpgm_id 246
constant length: INTEGER := L'length;
begin
return plus(CONV_SIGNED(L, length),
CONV_SIGNED(R, length)); -- pragma label plus
end;
function "+"(L: STD_ULOGIC; R: SIGNED) return SIGNED is
-- pragma label_applies_to plus
-- synopsys subpgm_id 247
constant length: INTEGER := R'length;
begin
return plus(CONV_SIGNED(L, length),
CONV_SIGNED(R, length)); -- pragma label plus
end;
function "+"(L: UNSIGNED; R: UNSIGNED) return STD_LOGIC_VECTOR is
-- pragma label_applies_to plus
-- synopsys subpgm_id 260
constant length: INTEGER := max(L'length, R'length);
begin
return STD_LOGIC_VECTOR (
unsigned_plus(-- pragma label plus
CONV_UNSIGNED(L, length), CONV_UNSIGNED(R, length)));
end;
function "+"(L: SIGNED; R: SIGNED) return STD_LOGIC_VECTOR is
-- pragma label_applies_to plus
-- synopsys subpgm_id 261
constant length: INTEGER := max(L'length, R'length);
begin
return STD_LOGIC_VECTOR (
plus(-- pragma label plus
CONV_SIGNED(L, length), CONV_SIGNED(R, length)));
end;
function "+"(L: UNSIGNED; R: SIGNED) return STD_LOGIC_VECTOR is
-- pragma label_applies_to plus
-- synopsys subpgm_id 262
constant length: INTEGER := max(L'length + 1, R'length);
begin
return STD_LOGIC_VECTOR (
plus(-- pragma label plus
CONV_SIGNED(L, length), CONV_SIGNED(R, length)));
end;
function "+"(L: SIGNED; R: UNSIGNED) return STD_LOGIC_VECTOR is
-- pragma label_applies_to plus
-- synopsys subpgm_id 263
constant length: INTEGER := max(L'length, R'length + 1);
begin
return STD_LOGIC_VECTOR (
plus(-- pragma label plus
CONV_SIGNED(L, length), CONV_SIGNED(R, length)));
end;
function "+"(L: UNSIGNED; R: INTEGER) return STD_LOGIC_VECTOR is
-- pragma label_applies_to plus
-- synopsys subpgm_id 264
constant length: INTEGER := L'length + 1;
begin
return STD_LOGIC_VECTOR (CONV_UNSIGNED(
plus( -- pragma label plus
CONV_SIGNED(L, length), CONV_SIGNED(R, length)), length-1));
end;
function "+"(L: INTEGER; R: UNSIGNED) return STD_LOGIC_VECTOR is
-- pragma label_applies_to plus
-- synopsys subpgm_id 265
constant length: INTEGER := R'length + 1;
begin
return STD_LOGIC_VECTOR (CONV_UNSIGNED(
plus( -- pragma label plus
CONV_SIGNED(L, length), CONV_SIGNED(R, length)), length-1));
end;
function "+"(L: SIGNED; R: INTEGER) return STD_LOGIC_VECTOR is
-- pragma label_applies_to plus
-- synopsys subpgm_id 266
constant length: INTEGER := L'length;
begin
return STD_LOGIC_VECTOR (
plus(-- pragma label plus
CONV_SIGNED(L, length), CONV_SIGNED(R, length)));
end;
function "+"(L: INTEGER; R: SIGNED) return STD_LOGIC_VECTOR is
-- pragma label_applies_to plus
-- synopsys subpgm_id 267
constant length: INTEGER := R'length;
begin
return STD_LOGIC_VECTOR (
plus(-- pragma label plus
CONV_SIGNED(L, length), CONV_SIGNED(R, length)));
end;
function "+"(L: UNSIGNED; R: STD_ULOGIC) return STD_LOGIC_VECTOR is
-- pragma label_applies_to plus
-- synopsys subpgm_id 268
constant length: INTEGER := L'length;
begin
return STD_LOGIC_VECTOR (
unsigned_plus(-- pragma label plus
CONV_UNSIGNED(L, length), CONV_UNSIGNED(R, length))) ;
end;
function "+"(L: STD_ULOGIC; R: UNSIGNED) return STD_LOGIC_VECTOR is
-- pragma label_applies_to plus
-- synopsys subpgm_id 269
constant length: INTEGER := R'length;
begin
return STD_LOGIC_VECTOR (
unsigned_plus(-- pragma label plus
CONV_UNSIGNED(L, length), CONV_UNSIGNED(R, length)));
end;
function "+"(L: SIGNED; R: STD_ULOGIC) return STD_LOGIC_VECTOR is
-- pragma label_applies_to plus
-- synopsys subpgm_id 270
constant length: INTEGER := L'length;
begin
return STD_LOGIC_VECTOR (
plus(-- pragma label plus
CONV_SIGNED(L, length), CONV_SIGNED(R, length)));
end;
function "+"(L: STD_ULOGIC; R: SIGNED) return STD_LOGIC_VECTOR is
-- pragma label_applies_to plus
-- synopsys subpgm_id 271
constant length: INTEGER := R'length;
begin
return STD_LOGIC_VECTOR (
plus(-- pragma label plus
CONV_SIGNED(L, length), CONV_SIGNED(R, length)));
end;
function "-"(L: UNSIGNED; R: UNSIGNED) return UNSIGNED is
-- pragma label_applies_to minus
-- synopsys subpgm_id 248
constant length: INTEGER := max(L'length, R'length);
begin
return unsigned_minus(CONV_UNSIGNED(L, length),
CONV_UNSIGNED(R, length)); -- pragma label minus
end;
function "-"(L: SIGNED; R: SIGNED) return SIGNED is
-- pragma label_applies_to minus
-- synopsys subpgm_id 249
constant length: INTEGER := max(L'length, R'length);
begin
return minus(CONV_SIGNED(L, length),
CONV_SIGNED(R, length)); -- pragma label minus
end;
function "-"(L: UNSIGNED; R: SIGNED) return SIGNED is
-- pragma label_applies_to minus
-- synopsys subpgm_id 250
constant length: INTEGER := max(L'length + 1, R'length);
begin
return minus(CONV_SIGNED(L, length),
CONV_SIGNED(R, length)); -- pragma label minus
end;
function "-"(L: SIGNED; R: UNSIGNED) return SIGNED is
-- pragma label_applies_to minus
-- synopsys subpgm_id 251
constant length: INTEGER := max(L'length, R'length + 1);
begin
return minus(CONV_SIGNED(L, length),
CONV_SIGNED(R, length)); -- pragma label minus
end;
function "-"(L: UNSIGNED; R: INTEGER) return UNSIGNED is
-- pragma label_applies_to minus
-- synopsys subpgm_id 252
constant length: INTEGER := L'length + 1;
begin
return CONV_UNSIGNED(
minus( -- pragma label minus
CONV_SIGNED(L, length), CONV_SIGNED(R, length)), length-1);
end;
function "-"(L: INTEGER; R: UNSIGNED) return UNSIGNED is
-- pragma label_applies_to minus
-- synopsys subpgm_id 253
constant length: INTEGER := R'length + 1;
begin
return CONV_UNSIGNED(
minus( -- pragma label minus
CONV_SIGNED(L, length), CONV_SIGNED(R, length)), length-1);
end;
function "-"(L: SIGNED; R: INTEGER) return SIGNED is
-- pragma label_applies_to minus
-- synopsys subpgm_id 254
constant length: INTEGER := L'length;
begin
return minus(CONV_SIGNED(L, length),
CONV_SIGNED(R, length)); -- pragma label minus
end;
function "-"(L: INTEGER; R: SIGNED) return SIGNED is
-- pragma label_applies_to minus
-- synopsys subpgm_id 255
constant length: INTEGER := R'length;
begin
return minus(CONV_SIGNED(L, length),
CONV_SIGNED(R, length)); -- pragma label minus
end;
function "-"(L: UNSIGNED; R: STD_ULOGIC) return UNSIGNED is
-- pragma label_applies_to minus
-- synopsys subpgm_id 256
constant length: INTEGER := L'length + 1;
begin
return CONV_UNSIGNED(
minus( -- pragma label minus
CONV_SIGNED(L, length), CONV_SIGNED(R, length)), length-1);
end;
function "-"(L: STD_ULOGIC; R: UNSIGNED) return UNSIGNED is
-- pragma label_applies_to minus
-- synopsys subpgm_id 257
constant length: INTEGER := R'length + 1;
begin
return CONV_UNSIGNED(
minus( -- pragma label minus
CONV_SIGNED(L, length), CONV_SIGNED(R, length)), length-1);
end;
function "-"(L: SIGNED; R: STD_ULOGIC) return SIGNED is
-- pragma label_applies_to minus
-- synopsys subpgm_id 258
constant length: INTEGER := L'length;
begin
return minus(CONV_SIGNED(L, length),
CONV_SIGNED(R, length)); -- pragma label minus
end;
function "-"(L: STD_ULOGIC; R: SIGNED) return SIGNED is
-- pragma label_applies_to minus
-- synopsys subpgm_id 259
constant length: INTEGER := R'length;
begin
return minus(CONV_SIGNED(L, length),
CONV_SIGNED(R, length)); -- pragma label minus
end;
function "-"(L: UNSIGNED; R: UNSIGNED) return STD_LOGIC_VECTOR is
-- pragma label_applies_to minus
-- synopsys subpgm_id 272
constant length: INTEGER := max(L'length, R'length);
begin
return STD_LOGIC_VECTOR (
unsigned_minus(-- pragma label minus
CONV_UNSIGNED(L, length), CONV_UNSIGNED(R, length)));
end;
function "-"(L: SIGNED; R: SIGNED) return STD_LOGIC_VECTOR is
-- pragma label_applies_to minus
-- synopsys subpgm_id 273
constant length: INTEGER := max(L'length, R'length);
begin
return STD_LOGIC_VECTOR (
minus(-- pragma label minus
CONV_SIGNED(L, length), CONV_SIGNED(R, length)));
end;
function "-"(L: UNSIGNED; R: SIGNED) return STD_LOGIC_VECTOR is
-- pragma label_applies_to minus
-- synopsys subpgm_id 274
constant length: INTEGER := max(L'length + 1, R'length);
begin
return STD_LOGIC_VECTOR (
minus(-- pragma label minus
CONV_SIGNED(L, length), CONV_SIGNED(R, length)));
end;
function "-"(L: SIGNED; R: UNSIGNED) return STD_LOGIC_VECTOR is
-- pragma label_applies_to minus
-- synopsys subpgm_id 275
constant length: INTEGER := max(L'length, R'length + 1);
begin
return STD_LOGIC_VECTOR (
minus(-- pragma label minus
CONV_SIGNED(L, length), CONV_SIGNED(R, length)));
end;
function "-"(L: UNSIGNED; R: INTEGER) return STD_LOGIC_VECTOR is
-- pragma label_applies_to minus
-- synopsys subpgm_id 276
constant length: INTEGER := L'length + 1;
begin
return STD_LOGIC_VECTOR (CONV_UNSIGNED(
minus( -- pragma label minus
CONV_SIGNED(L, length), CONV_SIGNED(R, length)), length-1));
end;
function "-"(L: INTEGER; R: UNSIGNED) return STD_LOGIC_VECTOR is
-- pragma label_applies_to minus
-- synopsys subpgm_id 277
constant length: INTEGER := R'length + 1;
begin
return STD_LOGIC_VECTOR (CONV_UNSIGNED(
minus( -- pragma label minus
CONV_SIGNED(L, length), CONV_SIGNED(R, length)), length-1));
end;
function "-"(L: SIGNED; R: INTEGER) return STD_LOGIC_VECTOR is
-- pragma label_applies_to minus
-- synopsys subpgm_id 278
constant length: INTEGER := L'length;
begin
return STD_LOGIC_VECTOR (
minus(-- pragma label minus
CONV_SIGNED(L, length), CONV_SIGNED(R, length)));
end;
function "-"(L: INTEGER; R: SIGNED) return STD_LOGIC_VECTOR is
-- pragma label_applies_to minus
-- synopsys subpgm_id 279
constant length: INTEGER := R'length;
begin
return STD_LOGIC_VECTOR (
minus(-- pragma label minus
CONV_SIGNED(L, length), CONV_SIGNED(R, length)));
end;
function "-"(L: UNSIGNED; R: STD_ULOGIC) return STD_LOGIC_VECTOR is
-- pragma label_applies_to minus
-- synopsys subpgm_id 280
constant length: INTEGER := L'length + 1;
begin
return STD_LOGIC_VECTOR (CONV_UNSIGNED(
minus( -- pragma label minus
CONV_SIGNED(L, length), CONV_SIGNED(R, length)), length-1));
end;
function "-"(L: STD_ULOGIC; R: UNSIGNED) return STD_LOGIC_VECTOR is
-- pragma label_applies_to minus
-- synopsys subpgm_id 281
constant length: INTEGER := R'length + 1;
begin
return STD_LOGIC_VECTOR (CONV_UNSIGNED(
minus( -- pragma label minus
CONV_SIGNED(L, length), CONV_SIGNED(R, length)), length-1));
end;
function "-"(L: SIGNED; R: STD_ULOGIC) return STD_LOGIC_VECTOR is
-- pragma label_applies_to minus
-- synopsys subpgm_id 282
constant length: INTEGER := L'length;
begin
return STD_LOGIC_VECTOR (
minus(-- pragma label minus
CONV_SIGNED(L, length), CONV_SIGNED(R, length)));
end;
function "-"(L: STD_ULOGIC; R: SIGNED) return STD_LOGIC_VECTOR is
-- pragma label_applies_to minus
-- synopsys subpgm_id 283
constant length: INTEGER := R'length;
begin
return STD_LOGIC_VECTOR (
minus(-- pragma label minus
CONV_SIGNED(L, length), CONV_SIGNED(R, length)));
end;
function "+"(L: UNSIGNED) return UNSIGNED is
-- synopsys subpgm_id 284
begin
return L;
end;
function "+"(L: SIGNED) return SIGNED is
-- synopsys subpgm_id 285
begin
return L;
end;
function "-"(L: SIGNED) return SIGNED is
-- pragma label_applies_to minus
-- synopsys subpgm_id 286
begin
return 0 - L; -- pragma label minus
end;
function "ABS"(L: SIGNED) return SIGNED is
-- synopsys subpgm_id 287
begin
if (L(L'left) = '0' or L(L'left) = 'L') then
return L;
else
return 0 - L;
end if;
end;
function "+"(L: UNSIGNED) return STD_LOGIC_VECTOR is
-- synopsys subpgm_id 289
begin
return STD_LOGIC_VECTOR (L);
end;
function "+"(L: SIGNED) return STD_LOGIC_VECTOR is
-- synopsys subpgm_id 290
begin
return STD_LOGIC_VECTOR (L);
end;
function "-"(L: SIGNED) return STD_LOGIC_VECTOR is
-- pragma label_applies_to minus
-- synopsys subpgm_id 292
variable tmp: SIGNED(L'length-1 downto 0);
begin
tmp := 0 - L; -- pragma label minus
return STD_LOGIC_VECTOR (tmp);
end;
function "ABS"(L: SIGNED) return STD_LOGIC_VECTOR is
-- synopsys subpgm_id 294
variable tmp: SIGNED(L'length-1 downto 0);
begin
if (L(L'left) = '0' or L(L'left) = 'L') then
return STD_LOGIC_VECTOR (L);
else
tmp := 0 - L;
return STD_LOGIC_VECTOR (tmp);
end if;
end;
-- Type propagation function which returns the type BOOLEAN
function UNSIGNED_RETURN_BOOLEAN(A,B: UNSIGNED) return BOOLEAN is
variable Z: BOOLEAN;
-- pragma return_port_name Z
begin
return(Z);
end;
-- Type propagation function which returns the type BOOLEAN
function SIGNED_RETURN_BOOLEAN(A,B: SIGNED) return BOOLEAN is
variable Z: BOOLEAN;
-- pragma return_port_name Z
begin
return(Z);
end;
-- compare two signed numbers of the same length
-- both arrays must have range (msb downto 0)
function is_less(A, B: SIGNED) return BOOLEAN is
constant sign: INTEGER := A'left;
variable a_is_0, b_is_1, result : boolean;
-- pragma map_to_operator LT_TC_OP
-- pragma type_function SIGNED_RETURN_BOOLEAN
-- pragma return_port_name Z
begin
if A(sign) /= B(sign) then
result := A(sign) = '1';
else
result := FALSE;
for i in 0 to sign-1 loop
a_is_0 := A(i) = '0';
b_is_1 := B(i) = '1';
result := (a_is_0 and b_is_1) or
(a_is_0 and result) or
(b_is_1 and result);
end loop;
end if;
return result;
end;
-- compare two signed numbers of the same length
-- both arrays must have range (msb downto 0)
function is_less_or_equal(A, B: SIGNED) return BOOLEAN is
constant sign: INTEGER := A'left;
variable a_is_0, b_is_1, result : boolean;
-- pragma map_to_operator LEQ_TC_OP
-- pragma type_function SIGNED_RETURN_BOOLEAN
-- pragma return_port_name Z
begin
if A(sign) /= B(sign) then
result := A(sign) = '1';
else
result := TRUE;
for i in 0 to sign-1 loop
a_is_0 := A(i) = '0';
b_is_1 := B(i) = '1';
result := (a_is_0 and b_is_1) or
(a_is_0 and result) or
(b_is_1 and result);
end loop;
end if;
return result;
end;
-- compare two unsigned numbers of the same length
-- both arrays must have range (msb downto 0)
function unsigned_is_less(A, B: UNSIGNED) return BOOLEAN is
constant sign: INTEGER := A'left;
variable a_is_0, b_is_1, result : boolean;
-- pragma map_to_operator LT_UNS_OP
-- pragma type_function UNSIGNED_RETURN_BOOLEAN
-- pragma return_port_name Z
begin
result := FALSE;
for i in 0 to sign loop
a_is_0 := A(i) = '0';
b_is_1 := B(i) = '1';
result := (a_is_0 and b_is_1) or
(a_is_0 and result) or
(b_is_1 and result);
end loop;
return result;
end;
-- compare two unsigned numbers of the same length
-- both arrays must have range (msb downto 0)
function unsigned_is_less_or_equal(A, B: UNSIGNED) return BOOLEAN is
constant sign: INTEGER := A'left;
variable a_is_0, b_is_1, result : boolean;
-- pragma map_to_operator LEQ_UNS_OP
-- pragma type_function UNSIGNED_RETURN_BOOLEAN
-- pragma return_port_name Z
begin
result := TRUE;
for i in 0 to sign loop
a_is_0 := A(i) = '0';
b_is_1 := B(i) = '1';
result := (a_is_0 and b_is_1) or
(a_is_0 and result) or
(b_is_1 and result);
end loop;
return result;
end;
function "<"(L: UNSIGNED; R: UNSIGNED) return BOOLEAN is
-- pragma label_applies_to lt
-- synopsys subpgm_id 305
constant length: INTEGER := max(L'length, R'length);
begin
return unsigned_is_less(CONV_UNSIGNED(L, length),
CONV_UNSIGNED(R, length)); -- pragma label lt
end;
function "<"(L: SIGNED; R: SIGNED) return BOOLEAN is
-- pragma label_applies_to lt
-- synopsys subpgm_id 306
constant length: INTEGER := max(L'length, R'length);
begin
return is_less(CONV_SIGNED(L, length),
CONV_SIGNED(R, length)); -- pragma label lt
end;
function "<"(L: UNSIGNED; R: SIGNED) return BOOLEAN is
-- pragma label_applies_to lt
-- synopsys subpgm_id 307
constant length: INTEGER := max(L'length + 1, R'length);
begin
return is_less(CONV_SIGNED(L, length),
CONV_SIGNED(R, length)); -- pragma label lt
end;
function "<"(L: SIGNED; R: UNSIGNED) return BOOLEAN is
-- pragma label_applies_to lt
-- synopsys subpgm_id 308
constant length: INTEGER := max(L'length, R'length + 1);
begin
return is_less(CONV_SIGNED(L, length),
CONV_SIGNED(R, length)); -- pragma label lt
end;
function "<"(L: UNSIGNED; R: INTEGER) return BOOLEAN is
-- pragma label_applies_to lt
-- synopsys subpgm_id 309
constant length: INTEGER := L'length + 1;
begin
return is_less(CONV_SIGNED(L, length),
CONV_SIGNED(R, length)); -- pragma label lt
end;
function "<"(L: INTEGER; R: UNSIGNED) return BOOLEAN is
-- pragma label_applies_to lt
-- synopsys subpgm_id 310
constant length: INTEGER := R'length + 1;
begin
return is_less(CONV_SIGNED(L, length),
CONV_SIGNED(R, length)); -- pragma label lt
end;
function "<"(L: SIGNED; R: INTEGER) return BOOLEAN is
-- pragma label_applies_to lt
-- synopsys subpgm_id 311
constant length: INTEGER := L'length;
begin
return is_less(CONV_SIGNED(L, length),
CONV_SIGNED(R, length)); -- pragma label lt
end;
function "<"(L: INTEGER; R: SIGNED) return BOOLEAN is
-- pragma label_applies_to lt
-- synopsys subpgm_id 312
constant length: INTEGER := R'length;
begin
return is_less(CONV_SIGNED(L, length),
CONV_SIGNED(R, length)); -- pragma label lt
end;
function "<="(L: UNSIGNED; R: UNSIGNED) return BOOLEAN is
-- pragma label_applies_to leq
-- synopsys subpgm_id 314
constant length: INTEGER := max(L'length, R'length);
begin
return unsigned_is_less_or_equal(CONV_UNSIGNED(L, length),
CONV_UNSIGNED(R, length)); -- pragma label leq
end;
function "<="(L: SIGNED; R: SIGNED) return BOOLEAN is
-- pragma label_applies_to leq
-- synopsys subpgm_id 315
constant length: INTEGER := max(L'length, R'length);
begin
return is_less_or_equal(CONV_SIGNED(L, length),
CONV_SIGNED(R, length)); -- pragma label leq
end;
function "<="(L: UNSIGNED; R: SIGNED) return BOOLEAN is
-- pragma label_applies_to leq
-- synopsys subpgm_id 316
constant length: INTEGER := max(L'length + 1, R'length);
begin
return is_less_or_equal(CONV_SIGNED(L, length),
CONV_SIGNED(R, length)); -- pragma label leq
end;
function "<="(L: SIGNED; R: UNSIGNED) return BOOLEAN is
-- pragma label_applies_to leq
-- synopsys subpgm_id 317
constant length: INTEGER := max(L'length, R'length + 1);
begin
return is_less_or_equal(CONV_SIGNED(L, length),
CONV_SIGNED(R, length)); -- pragma label leq
end;
function "<="(L: UNSIGNED; R: INTEGER) return BOOLEAN is
-- pragma label_applies_to leq
-- synopsys subpgm_id 318
constant length: INTEGER := L'length + 1;
begin
return is_less_or_equal(CONV_SIGNED(L, length),
CONV_SIGNED(R, length)); -- pragma label leq
end;
function "<="(L: INTEGER; R: UNSIGNED) return BOOLEAN is
-- pragma label_applies_to leq
-- synopsys subpgm_id 319
constant length: INTEGER := R'length + 1;
begin
return is_less_or_equal(CONV_SIGNED(L, length),
CONV_SIGNED(R, length)); -- pragma label leq
end;
function "<="(L: SIGNED; R: INTEGER) return BOOLEAN is
-- pragma label_applies_to leq
-- synopsys subpgm_id 320
constant length: INTEGER := L'length;
begin
return is_less_or_equal(CONV_SIGNED(L, length),
CONV_SIGNED(R, length)); -- pragma label leq
end;
function "<="(L: INTEGER; R: SIGNED) return BOOLEAN is
-- pragma label_applies_to leq
-- synopsys subpgm_id 321
constant length: INTEGER := R'length;
begin
return is_less_or_equal(CONV_SIGNED(L, length),
CONV_SIGNED(R, length)); -- pragma label leq
end;
function ">"(L: UNSIGNED; R: UNSIGNED) return BOOLEAN is
-- pragma label_applies_to gt
-- synopsys subpgm_id 323
constant length: INTEGER := max(L'length, R'length);
begin
return unsigned_is_less(CONV_UNSIGNED(R, length),
CONV_UNSIGNED(L, length)); -- pragma label gt
end;
function ">"(L: SIGNED; R: SIGNED) return BOOLEAN is
-- pragma label_applies_to gt
-- synopsys subpgm_id 324
constant length: INTEGER := max(L'length, R'length);
begin
return is_less(CONV_SIGNED(R, length),
CONV_SIGNED(L, length)); -- pragma label gt
end;
function ">"(L: UNSIGNED; R: SIGNED) return BOOLEAN is
-- pragma label_applies_to gt
-- synopsys subpgm_id 325
constant length: INTEGER := max(L'length + 1, R'length);
begin
return is_less(CONV_SIGNED(R, length),
CONV_SIGNED(L, length)); -- pragma label gt
end;
function ">"(L: SIGNED; R: UNSIGNED) return BOOLEAN is
-- pragma label_applies_to gt
-- synopsys subpgm_id 326
constant length: INTEGER := max(L'length, R'length + 1);
begin
return is_less(CONV_SIGNED(R, length),
CONV_SIGNED(L, length)); -- pragma label gt
end;
function ">"(L: UNSIGNED; R: INTEGER) return BOOLEAN is
-- pragma label_applies_to gt
-- synopsys subpgm_id 327
constant length: INTEGER := L'length + 1;
begin
return is_less(CONV_SIGNED(R, length),
CONV_SIGNED(L, length)); -- pragma label gt
end;
function ">"(L: INTEGER; R: UNSIGNED) return BOOLEAN is
-- pragma label_applies_to gt
-- synopsys subpgm_id 328
constant length: INTEGER := R'length + 1;
begin
return is_less(CONV_SIGNED(R, length),
CONV_SIGNED(L, length)); -- pragma label gt
end;
function ">"(L: SIGNED; R: INTEGER) return BOOLEAN is
-- pragma label_applies_to gt
-- synopsys subpgm_id 329
constant length: INTEGER := L'length;
begin
return is_less(CONV_SIGNED(R, length),
CONV_SIGNED(L, length)); -- pragma label gt
end;
function ">"(L: INTEGER; R: SIGNED) return BOOLEAN is
-- pragma label_applies_to gt
-- synopsys subpgm_id 330
constant length: INTEGER := R'length;
begin
return is_less(CONV_SIGNED(R, length),
CONV_SIGNED(L, length)); -- pragma label gt
end;
function ">="(L: UNSIGNED; R: UNSIGNED) return BOOLEAN is
-- pragma label_applies_to geq
-- synopsys subpgm_id 332
constant length: INTEGER := max(L'length, R'length);
begin
return unsigned_is_less_or_equal(CONV_UNSIGNED(R, length),
CONV_UNSIGNED(L, length)); -- pragma label geq
end;
function ">="(L: SIGNED; R: SIGNED) return BOOLEAN is
-- pragma label_applies_to geq
-- synopsys subpgm_id 333
constant length: INTEGER := max(L'length, R'length);
begin
return is_less_or_equal(CONV_SIGNED(R, length),
CONV_SIGNED(L, length)); -- pragma label geq
end;
function ">="(L: UNSIGNED; R: SIGNED) return BOOLEAN is
-- pragma label_applies_to geq
-- synopsys subpgm_id 334
constant length: INTEGER := max(L'length + 1, R'length);
begin
return is_less_or_equal(CONV_SIGNED(R, length),
CONV_SIGNED(L, length)); -- pragma label geq
end;
function ">="(L: SIGNED; R: UNSIGNED) return BOOLEAN is
-- pragma label_applies_to geq
-- synopsys subpgm_id 335
constant length: INTEGER := max(L'length, R'length + 1);
begin
return is_less_or_equal(CONV_SIGNED(R, length),
CONV_SIGNED(L, length)); -- pragma label geq
end;
function ">="(L: UNSIGNED; R: INTEGER) return BOOLEAN is
-- pragma label_applies_to geq
-- synopsys subpgm_id 336
constant length: INTEGER := L'length + 1;
begin
return is_less_or_equal(CONV_SIGNED(R, length),
CONV_SIGNED(L, length)); -- pragma label geq
end;
function ">="(L: INTEGER; R: UNSIGNED) return BOOLEAN is
-- pragma label_applies_to geq
-- synopsys subpgm_id 337
constant length: INTEGER := R'length + 1;
begin
return is_less_or_equal(CONV_SIGNED(R, length),
CONV_SIGNED(L, length)); -- pragma label geq
end;
function ">="(L: SIGNED; R: INTEGER) return BOOLEAN is
-- pragma label_applies_to geq
-- synopsys subpgm_id 338
constant length: INTEGER := L'length;
begin
return is_less_or_equal(CONV_SIGNED(R, length),
CONV_SIGNED(L, length)); -- pragma label geq
end;
function ">="(L: INTEGER; R: SIGNED) return BOOLEAN is
-- pragma label_applies_to geq
-- synopsys subpgm_id 339
constant length: INTEGER := R'length;
begin
return is_less_or_equal(CONV_SIGNED(R, length),
CONV_SIGNED(L, length)); -- pragma label geq
end;
-- for internal use only. Assumes SIGNED arguments of equal length.
function bitwise_eql(L: STD_ULOGIC_VECTOR; R: STD_ULOGIC_VECTOR)
return BOOLEAN is
-- pragma built_in SYN_EQL
begin
for i in L'range loop
if L(i) /= R(i) then
return FALSE;
end if;
end loop;
return TRUE;
end;
-- for internal use only. Assumes SIGNED arguments of equal length.
function bitwise_neq(L: STD_ULOGIC_VECTOR; R: STD_ULOGIC_VECTOR)
return BOOLEAN is
-- pragma built_in SYN_NEQ
begin
for i in L'range loop
if L(i) /= R(i) then
return TRUE;
end if;
end loop;
return FALSE;
end;
function "="(L: UNSIGNED; R: UNSIGNED) return BOOLEAN is
-- synopsys subpgm_id 341
constant length: INTEGER := max(L'length, R'length);
begin
return bitwise_eql( STD_ULOGIC_VECTOR( CONV_UNSIGNED(L, length) ),
STD_ULOGIC_VECTOR( CONV_UNSIGNED(R, length) ) );
end;
function "="(L: SIGNED; R: SIGNED) return BOOLEAN is
-- synopsys subpgm_id 342
constant length: INTEGER := max(L'length, R'length);
begin
return bitwise_eql( STD_ULOGIC_VECTOR( CONV_SIGNED(L, length) ),
STD_ULOGIC_VECTOR( CONV_SIGNED(R, length) ) );
end;
function "="(L: UNSIGNED; R: SIGNED) return BOOLEAN is
-- synopsys subpgm_id 343
constant length: INTEGER := max(L'length + 1, R'length);
begin
return bitwise_eql( STD_ULOGIC_VECTOR( CONV_SIGNED(L, length) ),
STD_ULOGIC_VECTOR( CONV_SIGNED(R, length) ) );
end;
function "="(L: SIGNED; R: UNSIGNED) return BOOLEAN is
-- synopsys subpgm_id 344
constant length: INTEGER := max(L'length, R'length + 1);
begin
return bitwise_eql( STD_ULOGIC_VECTOR( CONV_SIGNED(L, length) ),
STD_ULOGIC_VECTOR( CONV_SIGNED(R, length) ) );
end;
function "="(L: UNSIGNED; R: INTEGER) return BOOLEAN is
-- synopsys subpgm_id 345
constant length: INTEGER := L'length + 1;
begin
return bitwise_eql( STD_ULOGIC_VECTOR( CONV_SIGNED(L, length) ),
STD_ULOGIC_VECTOR( CONV_SIGNED(R, length) ) );
end;
function "="(L: INTEGER; R: UNSIGNED) return BOOLEAN is
-- synopsys subpgm_id 346
constant length: INTEGER := R'length + 1;
begin
return bitwise_eql( STD_ULOGIC_VECTOR( CONV_SIGNED(L, length) ),
STD_ULOGIC_VECTOR( CONV_SIGNED(R, length) ) );
end;
function "="(L: SIGNED; R: INTEGER) return BOOLEAN is
-- synopsys subpgm_id 347
constant length: INTEGER := L'length;
begin
return bitwise_eql( STD_ULOGIC_VECTOR( CONV_SIGNED(L, length) ),
STD_ULOGIC_VECTOR( CONV_SIGNED(R, length) ) );
end;
function "="(L: INTEGER; R: SIGNED) return BOOLEAN is
-- synopsys subpgm_id 348
constant length: INTEGER := R'length;
begin
return bitwise_eql( STD_ULOGIC_VECTOR( CONV_SIGNED(L, length) ),
STD_ULOGIC_VECTOR( CONV_SIGNED(R, length) ) );
end;
function "/="(L: UNSIGNED; R: UNSIGNED) return BOOLEAN is
-- synopsys subpgm_id 350
constant length: INTEGER := max(L'length, R'length);
begin
return bitwise_neq( STD_ULOGIC_VECTOR( CONV_UNSIGNED(L, length) ),
STD_ULOGIC_VECTOR( CONV_UNSIGNED(R, length) ) );
end;
function "/="(L: SIGNED; R: SIGNED) return BOOLEAN is
-- synopsys subpgm_id 351
constant length: INTEGER := max(L'length, R'length);
begin
return bitwise_neq( STD_ULOGIC_VECTOR( CONV_SIGNED(L, length) ),
STD_ULOGIC_VECTOR( CONV_SIGNED(R, length) ) );
end;
function "/="(L: UNSIGNED; R: SIGNED) return BOOLEAN is
-- synopsys subpgm_id 352
constant length: INTEGER := max(L'length + 1, R'length);
begin
return bitwise_neq( STD_ULOGIC_VECTOR( CONV_SIGNED(L, length) ),
STD_ULOGIC_VECTOR( CONV_SIGNED(R, length) ) );
end;
function "/="(L: SIGNED; R: UNSIGNED) return BOOLEAN is
-- synopsys subpgm_id 353
constant length: INTEGER := max(L'length, R'length + 1);
begin
return bitwise_neq( STD_ULOGIC_VECTOR( CONV_SIGNED(L, length) ),
STD_ULOGIC_VECTOR( CONV_SIGNED(R, length) ) );
end;
function "/="(L: UNSIGNED; R: INTEGER) return BOOLEAN is
-- synopsys subpgm_id 354
constant length: INTEGER := L'length + 1;
begin
return bitwise_neq( STD_ULOGIC_VECTOR( CONV_SIGNED(L, length) ),
STD_ULOGIC_VECTOR( CONV_SIGNED(R, length) ) );
end;
function "/="(L: INTEGER; R: UNSIGNED) return BOOLEAN is
-- synopsys subpgm_id 355
constant length: INTEGER := R'length + 1;
begin
return bitwise_neq( STD_ULOGIC_VECTOR( CONV_SIGNED(L, length) ),
STD_ULOGIC_VECTOR( CONV_SIGNED(R, length) ) );
end;
function "/="(L: SIGNED; R: INTEGER) return BOOLEAN is
-- synopsys subpgm_id 356
constant length: INTEGER := L'length;
begin
return bitwise_neq( STD_ULOGIC_VECTOR( CONV_SIGNED(L, length) ),
STD_ULOGIC_VECTOR( CONV_SIGNED(R, length) ) );
end;
function "/="(L: INTEGER; R: SIGNED) return BOOLEAN is
-- synopsys subpgm_id 357
constant length: INTEGER := R'length;
begin
return bitwise_neq( STD_ULOGIC_VECTOR( CONV_SIGNED(L, length) ),
STD_ULOGIC_VECTOR( CONV_SIGNED(R, length) ) );
end;
function SHL(ARG: UNSIGNED; COUNT: UNSIGNED) return UNSIGNED is
-- synopsys subpgm_id 358
constant control_msb: INTEGER := COUNT'length - 1;
variable control: UNSIGNED (control_msb downto 0);
constant result_msb: INTEGER := ARG'length-1;
subtype rtype is UNSIGNED (result_msb downto 0);
variable result, temp: rtype;
begin
control := MAKE_BINARY(COUNT);
-- synopsys synthesis_off
if (control(0) = 'X') then
result := rtype'(others => 'X');
return result;
end if;
-- synopsys synthesis_on
result := ARG;
for i in 0 to control_msb loop
if control(i) = '1' then
temp := rtype'(others => '0');
if 2**i <= result_msb then
temp(result_msb downto 2**i) :=
result(result_msb - 2**i downto 0);
end if;
result := temp;
end if;
end loop;
return result;
end;
function SHL(ARG: SIGNED; COUNT: UNSIGNED) return SIGNED is
-- synopsys subpgm_id 359
constant control_msb: INTEGER := COUNT'length - 1;
variable control: UNSIGNED (control_msb downto 0);
constant result_msb: INTEGER := ARG'length-1;
subtype rtype is SIGNED (result_msb downto 0);
variable result, temp: rtype;
begin
control := MAKE_BINARY(COUNT);
-- synopsys synthesis_off
if (control(0) = 'X') then
result := rtype'(others => 'X');
return result;
end if;
-- synopsys synthesis_on
result := ARG;
for i in 0 to control_msb loop
if control(i) = '1' then
temp := rtype'(others => '0');
if 2**i <= result_msb then
temp(result_msb downto 2**i) :=
result(result_msb - 2**i downto 0);
end if;
result := temp;
end if;
end loop;
return result;
end;
function SHR(ARG: UNSIGNED; COUNT: UNSIGNED) return UNSIGNED is
-- synopsys subpgm_id 360
constant control_msb: INTEGER := COUNT'length - 1;
variable control: UNSIGNED (control_msb downto 0);
constant result_msb: INTEGER := ARG'length-1;
subtype rtype is UNSIGNED (result_msb downto 0);
variable result, temp: rtype;
begin
control := MAKE_BINARY(COUNT);
-- synopsys synthesis_off
if (control(0) = 'X') then
result := rtype'(others => 'X');
return result;
end if;
-- synopsys synthesis_on
result := ARG;
for i in 0 to control_msb loop
if control(i) = '1' then
temp := rtype'(others => '0');
if 2**i <= result_msb then
temp(result_msb - 2**i downto 0) :=
result(result_msb downto 2**i);
end if;
result := temp;
end if;
end loop;
return result;
end;
function SHR(ARG: SIGNED; COUNT: UNSIGNED) return SIGNED is
-- synopsys subpgm_id 361
constant control_msb: INTEGER := COUNT'length - 1;
variable control: UNSIGNED (control_msb downto 0);
constant result_msb: INTEGER := ARG'length-1;
subtype rtype is SIGNED (result_msb downto 0);
variable result, temp: rtype;
variable sign_bit: STD_ULOGIC;
begin
control := MAKE_BINARY(COUNT);
-- synopsys synthesis_off
if (control(0) = 'X') then
result := rtype'(others => 'X');
return result;
end if;
-- synopsys synthesis_on
result := ARG;
sign_bit := ARG(ARG'left);
for i in 0 to control_msb loop
if control(i) = '1' then
temp := rtype'(others => sign_bit);
if 2**i <= result_msb then
temp(result_msb - 2**i downto 0) :=
result(result_msb downto 2**i);
end if;
result := temp;
end if;
end loop;
return result;
end;
function CONV_INTEGER(ARG: INTEGER) return INTEGER is
-- synopsys subpgm_id 365
begin
return ARG;
end;
function CONV_INTEGER(ARG: UNSIGNED) return INTEGER is
variable result: INTEGER;
variable tmp: STD_ULOGIC;
-- synopsys built_in SYN_UNSIGNED_TO_INTEGER
-- synopsys subpgm_id 366
begin
-- synopsys synthesis_off
assert ARG'length <= 31
report "ARG is too large in CONV_INTEGER"
severity FAILURE;
result := 0;
for i in ARG'range loop
result := result * 2;
tmp := tbl_BINARY(ARG(i));
if tmp = '1' then
result := result + 1;
elsif tmp = 'X' then
assert false
report "CONV_INTEGER: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, and it has been converted to 0."
severity WARNING;
end if;
end loop;
return result;
-- synopsys synthesis_on
end;
function CONV_INTEGER(ARG: SIGNED) return INTEGER is
variable result: INTEGER;
variable tmp: STD_ULOGIC;
-- synopsys built_in SYN_SIGNED_TO_INTEGER
-- synopsys subpgm_id 367
begin
-- synopsys synthesis_off
assert ARG'length <= 32
report "ARG is too large in CONV_INTEGER"
severity FAILURE;
result := 0;
for i in ARG'range loop
if i /= ARG'left then
result := result * 2;
tmp := tbl_BINARY(ARG(i));
if tmp = '1' then
result := result + 1;
elsif tmp = 'X' then
assert false
report "CONV_INTEGER: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, and it has been converted to 0."
severity WARNING;
end if;
end if;
end loop;
tmp := MAKE_BINARY(ARG(ARG'left));
if tmp = '1' then
if ARG'length = 32 then
result := (result - 2**30) - 2**30;
else
result := result - (2 ** (ARG'length-1));
end if;
end if;
return result;
-- synopsys synthesis_on
end;
function CONV_INTEGER(ARG: STD_ULOGIC) return SMALL_INT is
variable tmp: STD_ULOGIC;
-- synopsys built_in SYN_FEED_THRU
-- synopsys subpgm_id 370
begin
-- synopsys synthesis_off
tmp := tbl_BINARY(ARG);
if tmp = '1' then
return 1;
elsif tmp = 'X' then
assert false
report "CONV_INTEGER: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, and it has been converted to 0."
severity WARNING;
return 0;
else
return 0;
end if;
-- synopsys synthesis_on
end;
-- convert an integer to a unsigned STD_ULOGIC_VECTOR
function CONV_UNSIGNED(ARG: INTEGER; SIZE: INTEGER) return UNSIGNED is
variable result: UNSIGNED(SIZE-1 downto 0);
variable temp: integer;
-- synopsys built_in SYN_INTEGER_TO_UNSIGNED
-- synopsys subpgm_id 371
begin
-- synopsys synthesis_off
temp := ARG;
for i in 0 to SIZE-1 loop
if (temp mod 2) = 1 then
result(i) := '1';
else
result(i) := '0';
end if;
if temp > 0 then
temp := temp / 2;
else
temp := (temp - 1) / 2; -- simulate ASR
end if;
end loop;
return result;
-- synopsys synthesis_on
end;
function CONV_UNSIGNED(ARG: UNSIGNED; SIZE: INTEGER) return UNSIGNED is
constant msb: INTEGER := min(ARG'length, SIZE) - 1;
subtype rtype is UNSIGNED (SIZE-1 downto 0);
variable new_bounds: UNSIGNED (ARG'length-1 downto 0);
variable result: rtype;
-- synopsys built_in SYN_ZERO_EXTEND
-- synopsys subpgm_id 372
begin
-- synopsys synthesis_off
new_bounds := MAKE_BINARY(ARG);
if (new_bounds(0) = 'X') then
result := rtype'(others => 'X');
return result;
end if;
result := rtype'(others => '0');
result(msb downto 0) := new_bounds(msb downto 0);
return result;
-- synopsys synthesis_on
end;
function CONV_UNSIGNED(ARG: SIGNED; SIZE: INTEGER) return UNSIGNED is
constant msb: INTEGER := min(ARG'length, SIZE) - 1;
subtype rtype is UNSIGNED (SIZE-1 downto 0);
variable new_bounds: UNSIGNED (ARG'length-1 downto 0);
variable result: rtype;
-- synopsys built_in SYN_SIGN_EXTEND
-- synopsys subpgm_id 373
begin
-- synopsys synthesis_off
new_bounds := MAKE_BINARY(ARG);
if (new_bounds(0) = 'X') then
result := rtype'(others => 'X');
return result;
end if;
result := rtype'(others => new_bounds(new_bounds'left));
result(msb downto 0) := new_bounds(msb downto 0);
return result;
-- synopsys synthesis_on
end;
function CONV_UNSIGNED(ARG: STD_ULOGIC; SIZE: INTEGER) return UNSIGNED is
subtype rtype is UNSIGNED (SIZE-1 downto 0);
variable result: rtype;
-- synopsys built_in SYN_ZERO_EXTEND
-- synopsys subpgm_id 375
begin
-- synopsys synthesis_off
result := rtype'(others => '0');
result(0) := MAKE_BINARY(ARG);
if (result(0) = 'X') then
result := rtype'(others => 'X');
end if;
return result;
-- synopsys synthesis_on
end;
-- convert an integer to a 2's complement STD_ULOGIC_VECTOR
function CONV_SIGNED(ARG: INTEGER; SIZE: INTEGER) return SIGNED is
variable result: SIGNED (SIZE-1 downto 0);
variable temp: integer;
-- synopsys built_in SYN_INTEGER_TO_SIGNED
-- synopsys subpgm_id 376
begin
-- synopsys synthesis_off
temp := ARG;
for i in 0 to SIZE-1 loop
if (temp mod 2) = 1 then
result(i) := '1';
else
result(i) := '0';
end if;
if temp > 0 then
temp := temp / 2;
elsif (temp > integer'low) then
temp := (temp - 1) / 2; -- simulate ASR
else
temp := temp / 2; -- simulate ASR
end if;
end loop;
return result;
-- synopsys synthesis_on
end;
function CONV_SIGNED(ARG: UNSIGNED; SIZE: INTEGER) return SIGNED is
constant msb: INTEGER := min(ARG'length, SIZE) - 1;
subtype rtype is SIGNED (SIZE-1 downto 0);
variable new_bounds : SIGNED (ARG'length-1 downto 0);
variable result: rtype;
-- synopsys built_in SYN_ZERO_EXTEND
-- synopsys subpgm_id 377
begin
-- synopsys synthesis_off
new_bounds := MAKE_BINARY(ARG);
if (new_bounds(0) = 'X') then
result := rtype'(others => 'X');
return result;
end if;
result := rtype'(others => '0');
result(msb downto 0) := new_bounds(msb downto 0);
return result;
-- synopsys synthesis_on
end;
function CONV_SIGNED(ARG: SIGNED; SIZE: INTEGER) return SIGNED is
constant msb: INTEGER := min(ARG'length, SIZE) - 1;
subtype rtype is SIGNED (SIZE-1 downto 0);
variable new_bounds : SIGNED (ARG'length-1 downto 0);
variable result: rtype;
-- synopsys built_in SYN_SIGN_EXTEND
-- synopsys subpgm_id 378
begin
-- synopsys synthesis_off
new_bounds := MAKE_BINARY(ARG);
if (new_bounds(0) = 'X') then
result := rtype'(others => 'X');
return result;
end if;
result := rtype'(others => new_bounds(new_bounds'left));
result(msb downto 0) := new_bounds(msb downto 0);
return result;
-- synopsys synthesis_on
end;
function CONV_SIGNED(ARG: STD_ULOGIC; SIZE: INTEGER) return SIGNED is
subtype rtype is SIGNED (SIZE-1 downto 0);
variable result: rtype;
-- synopsys built_in SYN_ZERO_EXTEND
-- synopsys subpgm_id 380
begin
-- synopsys synthesis_off
result := rtype'(others => '0');
result(0) := MAKE_BINARY(ARG);
if (result(0) = 'X') then
result := rtype'(others => 'X');
end if;
return result;
-- synopsys synthesis_on
end;
-- convert an integer to an STD_LOGIC_VECTOR
function CONV_STD_LOGIC_VECTOR(ARG: INTEGER; SIZE: INTEGER) return STD_LOGIC_VECTOR is
variable result: STD_LOGIC_VECTOR (SIZE-1 downto 0);
variable temp: integer;
-- synopsys built_in SYN_INTEGER_TO_SIGNED
-- synopsys subpgm_id 381
begin
-- synopsys synthesis_off
temp := ARG;
for i in 0 to SIZE-1 loop
if (temp mod 2) = 1 then
result(i) := '1';
else
result(i) := '0';
end if;
if temp > 0 then
temp := temp / 2;
elsif (temp > integer'low) then
temp := (temp - 1) / 2; -- simulate ASR
else
temp := temp / 2; -- simulate ASR
end if;
end loop;
return result;
-- synopsys synthesis_on
end;
function CONV_STD_LOGIC_VECTOR(ARG: UNSIGNED; SIZE: INTEGER) return STD_LOGIC_VECTOR is
constant msb: INTEGER := min(ARG'length, SIZE) - 1;
subtype rtype is STD_LOGIC_VECTOR (SIZE-1 downto 0);
variable new_bounds : STD_LOGIC_VECTOR (ARG'length-1 downto 0);
variable result: rtype;
-- synopsys built_in SYN_ZERO_EXTEND
-- synopsys subpgm_id 382
begin
-- synopsys synthesis_off
new_bounds := MAKE_BINARY(ARG);
if (new_bounds(0) = 'X') then
result := rtype'(others => 'X');
return result;
end if;
result := rtype'(others => '0');
result(msb downto 0) := new_bounds(msb downto 0);
return result;
-- synopsys synthesis_on
end;
function CONV_STD_LOGIC_VECTOR(ARG: SIGNED; SIZE: INTEGER) return STD_LOGIC_VECTOR is
constant msb: INTEGER := min(ARG'length, SIZE) - 1;
subtype rtype is STD_LOGIC_VECTOR (SIZE-1 downto 0);
variable new_bounds : STD_LOGIC_VECTOR (ARG'length-1 downto 0);
variable result: rtype;
-- synopsys built_in SYN_SIGN_EXTEND
-- synopsys subpgm_id 383
begin
-- synopsys synthesis_off
new_bounds := MAKE_BINARY(ARG);
if (new_bounds(0) = 'X') then
result := rtype'(others => 'X');
return result;
end if;
result := rtype'(others => new_bounds(new_bounds'left));
result(msb downto 0) := new_bounds(msb downto 0);
return result;
-- synopsys synthesis_on
end;
function CONV_STD_LOGIC_VECTOR(ARG: STD_ULOGIC; SIZE: INTEGER) return STD_LOGIC_VECTOR is
subtype rtype is STD_LOGIC_VECTOR (SIZE-1 downto 0);
variable result: rtype;
-- synopsys built_in SYN_ZERO_EXTEND
-- synopsys subpgm_id 384
begin
-- synopsys synthesis_off
result := rtype'(others => '0');
result(0) := MAKE_BINARY(ARG);
if (result(0) = 'X') then
result := rtype'(others => 'X');
end if;
return result;
-- synopsys synthesis_on
end;
function EXT(ARG: STD_LOGIC_VECTOR; SIZE: INTEGER)
return STD_LOGIC_VECTOR is
constant msb: INTEGER := min(ARG'length, SIZE) - 1;
subtype rtype is STD_LOGIC_VECTOR (SIZE-1 downto 0);
variable new_bounds: STD_LOGIC_VECTOR (ARG'length-1 downto 0);
variable result: rtype;
-- synopsys built_in SYN_ZERO_EXTEND
-- synopsys subpgm_id 385
begin
-- synopsys synthesis_off
new_bounds := MAKE_BINARY(ARG);
if (new_bounds(0) = 'X') then
result := rtype'(others => 'X');
return result;
end if;
result := rtype'(others => '0');
result(msb downto 0) := new_bounds(msb downto 0);
return result;
-- synopsys synthesis_on
end;
function SXT(ARG: STD_LOGIC_VECTOR; SIZE: INTEGER) return STD_LOGIC_VECTOR is
constant msb: INTEGER := min(ARG'length, SIZE) - 1;
subtype rtype is STD_LOGIC_VECTOR (SIZE-1 downto 0);
variable new_bounds : STD_LOGIC_VECTOR (ARG'length-1 downto 0);
variable result: rtype;
-- synopsys built_in SYN_SIGN_EXTEND
-- synopsys subpgm_id 386
begin
-- synopsys synthesis_off
new_bounds := MAKE_BINARY(ARG);
if (new_bounds(0) = 'X') then
result := rtype'(others => 'X');
return result;
end if;
result := rtype'(others => new_bounds(new_bounds'left));
result(msb downto 0) := new_bounds(msb downto 0);
return result;
-- synopsys synthesis_on
end;
end std_logic_arith;
| gpl-3.0 | 062e81dde13362dd529e7689b4d21c45 | 0.640128 | 3.436936 | false | false | false | false |
grwlf/vsim | vhdl_ct/ct00282.vhd | 1 | 2,778 | -------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
-------------------------------------------------------------------------------
--
-- TEST NAME:
--
-- CT00282
--
-- AUTHOR:
--
-- A. Wilmot
--
-- TEST OBJECTIVES:
--
-- 7.1 (1)
--
-- DESIGN UNIT ORDERING:
--
-- ENT00282(ARCH00282)
-- ENT00282_Test_Bench(ARCH00282_Test_Bench)
--
-- REVISION HISTORY:
--
-- 21-JUL-1987 - initial revision
--
-- NOTES:
--
-- self-checking
-- automatically generated
--
use WORK.STANDARD_TYPES.all ;
entity ENT00282 is
generic ( g1 : boolean ) ;
port ( locally_static_correct : out boolean := true ;
dynamic_correct : out boolean := true ) ;
end ENT00282 ;
architecture ARCH00282 of ENT00282 is
constant answer : boolean := true ;
constant c1 : boolean := true ;
constant c2 : boolean := false ;
signal s1, s2 : boolean := true ;
begin
s2 <= false ;
gen1: if answer = ( c1 and (not c2) and g1 and
(c2 or (not g1) or c1) and
(c1 xor c2 xor g1 xor c1 ) ) generate
process ( s2 )
variable bool : boolean ;
begin
if not s2 then
bool := true ;
dynamic_correct <= s1 and (not s2) and g1 and
(s2 or (not g1) or s1) and
(s1 xor s2 xor g1 xor s1 ) ;
case bool is
when ( answer = ( c1 and (not c2) and true and
(c2 or (not true) or c1) and
(c1 xor c2 xor true xor c1 ) ) ) =>
locally_static_correct <= true ;
when others =>
locally_static_correct <= false ;
end case ;
end if ;
end process ;
end generate ;
end ARCH00282 ;
use WORK.STANDARD_TYPES.all ;
entity ENT00282_Test_Bench is
end ENT00282_Test_Bench ;
architecture ARCH00282_Test_Bench of ENT00282_Test_Bench is
begin
L1:
block
signal locally_static_correct, dynamic_correct : boolean := false ;
constant c1 : boolean := true ;
component UUT
generic ( g1 : boolean ) ;
port ( locally_static_correct : out boolean := false ;
dynamic_correct : out boolean := false ) ;
end component ;
for CIS1 : UUT use entity WORK.ENT00282 ( ARCH00282 ) ;
begin
CIS1 : UUT
generic map ( c1 )
port map ( locally_static_correct ,
dynamic_correct ) ;
process ( locally_static_correct, dynamic_correct )
begin
if locally_static_correct and dynamic_correct then
test_report ( "ARCH00282" ,
"And's, or's, xor's in succession" ,
true ) ;
end if ;
end process ;
end block L1 ;
end ARCH00282_Test_Bench ;
| gpl-3.0 | 3ebd6cbbb644bb18c88d0c08597065ef | 0.530598 | 3.694149 | false | true | false | false |
TWW12/lzw | ip_repo/axi_compression_1.0/src/lzw.vhd | 4 | 7,433 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity lzw is
generic (num_blocks : integer := 4);
Port (
clk : in std_logic;
rst : in std_logic;
--Input character from FIFO
char_in : in std_logic_vector(7 downto 0);
--Input character valid? (tie to NOT fifo_empty)
input_valid : in std_logic;
--How many characters is the input file
file_size : in std_logic_vector(15 downto 0);
--FIFO read acknowledgement
input_rd : out std_logic;
--Output data
prefix_out : out std_logic_vector(11 downto 0);
--Output data is valid, tie to output FIFO wr_en
output_valid : out std_logic;
--Done processing current file
done : out std_logic);
end lzw;
architecture Behavioral of lzw is
type state_type is (S_RST,S_WAIT,S_READ_FIRST_CHAR,S_READ,S_SEARCH);
signal state : state_type;
signal current_char : std_logic_vector(7 downto 0);
signal current_prefix : std_logic_vector(11 downto 0);
signal output_last_prefix : std_logic;
signal start_search : std_logic;
signal search_entry : std_logic_vector(19 downto 0);
signal dict_wr : std_logic;
signal wr_entry : std_logic_vector(19 downto 0);
signal match_prefix : std_logic_vector(11 downto 0);
signal entry_found : std_logic;
signal search_completed : std_logic;
signal dictionary_full : std_logic;
signal eof : std_logic;
signal bytes_read : std_logic_vector(15 downto 0);
begin
prefix_out <= current_prefix;
GEN_DICT1: if num_blocks = 1 generate
U_DICTIONARY : entity work.dictionary_block
port map (
clk => clk,
rst => rst,
start_search => start_search,
search_entry => search_entry,
wr_en => dict_wr,
wr_entry => wr_entry,
prefix => match_prefix,
entry_found => entry_found,
search_completed => search_completed,
dictionary_full => dictionary_full);
end generate GEN_DICT1;
GEN_DICT2: if num_blocks = 2 generate
U_DICTIONARY : entity work.dictionary_2
port map (
clk => clk,
rst => rst,
start_search => start_search,
search_entry => search_entry,
wr_en => dict_wr,
wr_entry => wr_entry,
prefix => match_prefix,
entry_found => entry_found,
search_completed => search_completed,
dictionary_full => dictionary_full);
end generate GEN_DICT2;
GEN_DICT4: if num_blocks = 4 generate
U_DICTIONARY : entity work.dictionary_4
port map (
clk => clk,
rst => rst,
start_search => start_search,
search_entry => search_entry,
wr_en => dict_wr,
wr_entry => wr_entry,
prefix => match_prefix,
entry_found => entry_found,
search_completed => search_completed,
dictionary_full => dictionary_full);
end generate GEN_DICT4;
search_entry(7 downto 0) <= current_char;
search_entry(19 downto 8) <= current_prefix;
wr_entry <= search_entry;
--State machine and synchronous outputs
process(clk,rst)
begin
if rst = '1' then
state <= S_RST;
current_char <= x"00";
current_prefix <= x"000";
start_search <= '0';
input_rd <= '0';
bytes_read <= (bytes_read'range => '0');
done <= '0';
elsif rising_edge(clk) then
--default values
input_rd <= '0';
start_search <= '0';
case state is
when S_RST =>
state <= S_READ_FIRST_CHAR;
when S_READ_FIRST_CHAR =>
if input_valid = '1' then
current_prefix(7 downto 0) <= char_in;
input_rd <= '1';
state <= S_WAIT;
bytes_read <= x"0001";
done <= '0';
end if;
when S_WAIT =>
input_rd <= '0';
state <= S_READ;
--read in another character
when S_READ =>
if input_valid = '1' then
current_char <= char_in;
start_search <= '1';
input_rd <= '1';
state <= S_SEARCH;
bytes_read <= std_logic_vector(unsigned(bytes_read)+to_unsigned(1,16));
end if;
when S_SEARCH =>
if search_completed = '1' then
state <= S_READ;
--if its found, save the prefix, read another char and look for another string
if entry_found = '1' then
current_prefix <= match_prefix;
--otherwise we'll be writing to the dictionary (look at asynchronous outputs below)
--and clearing out our saved values
else
current_char <= x"00";
current_prefix(11 downto 8) <= x"0";
current_prefix(7 downto 0) <= current_char;
end if;
if eof = '1' then
state <= S_READ_FIRST_CHAR;
done <= '1';
end if;
end if;
end case;
end if;
end process;
--when we force the controller to output the last prefix value
--we need to delay it by one cycle or else the wrong value is marked as valid
process(clk,rst)
begin
if rst = '1' then
output_last_prefix <= '0';
elsif rising_edge(clk) then
if state = S_SEARCH and search_completed = '1' and
entry_found = '1' and eof = '1' then
output_last_prefix <= '1';
else
output_last_prefix <= '0';
end if;
end if;
end process;
--Asynchronous outputs
process(state,search_completed,entry_found,dictionary_full,bytes_read,file_size)
begin
output_valid <= output_last_prefix;
dict_wr <= '0';
--if we finished a search and no entry was found, write new entry to the dictionary
--and output the current values
if state = S_SEARCH and search_completed = '1' and entry_found = '0' then
output_valid <= '1';
dict_wr <= not dictionary_full;
end if;
if bytes_read = file_size then
eof <= '1';
else
eof <= '0';
end if;
end process;
end Behavioral;
| unlicense | 39dc536b3dce91c9d81bf102de459a94 | 0.465223 | 4.524041 | false | false | false | false |
wsoltys/AtomFpga | src/AtomGodilVideo/src/MC6847/mc6847t1_ntsc.vhd | 1 | 55,854 | -- generated with romgen v3.0.1r4 by MikeJ truhy and eD
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
library UNISIM;
use UNISIM.Vcomponents.all;
entity mc6847t1_ntsc is
port (
CLK : in std_logic;
ADDR : in std_logic_vector(10 downto 0);
DATA : out std_logic_vector(7 downto 0)
);
end;
architecture RTL of mc6847t1_ntsc is
signal rom_addr : std_logic_vector(11 downto 0);
begin
p_addr : process(ADDR)
begin
rom_addr <= (others => '0');
rom_addr(10 downto 0) <= ADDR;
end process;
p_rom : process
begin
wait until rising_edge(CLK);
DATA <= (others => '0');
case rom_addr is
when x"000" => DATA <= x"00";
when x"001" => DATA <= x"00";
when x"002" => DATA <= x"38";
when x"003" => DATA <= x"44";
when x"004" => DATA <= x"04";
when x"005" => DATA <= x"34";
when x"006" => DATA <= x"4C";
when x"007" => DATA <= x"4C";
when x"008" => DATA <= x"38";
when x"009" => DATA <= x"00";
when x"00A" => DATA <= x"00";
when x"00B" => DATA <= x"00";
when x"00C" => DATA <= x"00";
when x"00D" => DATA <= x"00";
when x"00E" => DATA <= x"00";
when x"00F" => DATA <= x"00";
when x"010" => DATA <= x"00";
when x"011" => DATA <= x"00";
when x"012" => DATA <= x"10";
when x"013" => DATA <= x"28";
when x"014" => DATA <= x"44";
when x"015" => DATA <= x"44";
when x"016" => DATA <= x"7C";
when x"017" => DATA <= x"44";
when x"018" => DATA <= x"44";
when x"019" => DATA <= x"00";
when x"01A" => DATA <= x"00";
when x"01B" => DATA <= x"00";
when x"01C" => DATA <= x"00";
when x"01D" => DATA <= x"00";
when x"01E" => DATA <= x"00";
when x"01F" => DATA <= x"00";
when x"020" => DATA <= x"00";
when x"021" => DATA <= x"00";
when x"022" => DATA <= x"78";
when x"023" => DATA <= x"24";
when x"024" => DATA <= x"24";
when x"025" => DATA <= x"38";
when x"026" => DATA <= x"24";
when x"027" => DATA <= x"24";
when x"028" => DATA <= x"78";
when x"029" => DATA <= x"00";
when x"02A" => DATA <= x"00";
when x"02B" => DATA <= x"00";
when x"02C" => DATA <= x"00";
when x"02D" => DATA <= x"00";
when x"02E" => DATA <= x"00";
when x"02F" => DATA <= x"00";
when x"030" => DATA <= x"00";
when x"031" => DATA <= x"00";
when x"032" => DATA <= x"38";
when x"033" => DATA <= x"44";
when x"034" => DATA <= x"40";
when x"035" => DATA <= x"40";
when x"036" => DATA <= x"40";
when x"037" => DATA <= x"44";
when x"038" => DATA <= x"38";
when x"039" => DATA <= x"00";
when x"03A" => DATA <= x"00";
when x"03B" => DATA <= x"00";
when x"03C" => DATA <= x"00";
when x"03D" => DATA <= x"00";
when x"03E" => DATA <= x"00";
when x"03F" => DATA <= x"00";
when x"040" => DATA <= x"00";
when x"041" => DATA <= x"00";
when x"042" => DATA <= x"78";
when x"043" => DATA <= x"24";
when x"044" => DATA <= x"24";
when x"045" => DATA <= x"24";
when x"046" => DATA <= x"24";
when x"047" => DATA <= x"24";
when x"048" => DATA <= x"78";
when x"049" => DATA <= x"00";
when x"04A" => DATA <= x"00";
when x"04B" => DATA <= x"00";
when x"04C" => DATA <= x"00";
when x"04D" => DATA <= x"00";
when x"04E" => DATA <= x"00";
when x"04F" => DATA <= x"00";
when x"050" => DATA <= x"00";
when x"051" => DATA <= x"00";
when x"052" => DATA <= x"7C";
when x"053" => DATA <= x"40";
when x"054" => DATA <= x"40";
when x"055" => DATA <= x"70";
when x"056" => DATA <= x"40";
when x"057" => DATA <= x"40";
when x"058" => DATA <= x"7C";
when x"059" => DATA <= x"00";
when x"05A" => DATA <= x"00";
when x"05B" => DATA <= x"00";
when x"05C" => DATA <= x"00";
when x"05D" => DATA <= x"00";
when x"05E" => DATA <= x"00";
when x"05F" => DATA <= x"00";
when x"060" => DATA <= x"00";
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when x"4A9" => DATA <= x"38";
when x"4AA" => DATA <= x"00";
when x"4AB" => DATA <= x"00";
when x"4AC" => DATA <= x"00";
when x"4AD" => DATA <= x"00";
when x"4AE" => DATA <= x"00";
when x"4AF" => DATA <= x"00";
when x"4B0" => DATA <= x"00";
when x"4B1" => DATA <= x"00";
when x"4B2" => DATA <= x"40";
when x"4B3" => DATA <= x"40";
when x"4B4" => DATA <= x"48";
when x"4B5" => DATA <= x"50";
when x"4B6" => DATA <= x"60";
when x"4B7" => DATA <= x"50";
when x"4B8" => DATA <= x"48";
when x"4B9" => DATA <= x"00";
when x"4BA" => DATA <= x"00";
when x"4BB" => DATA <= x"00";
when x"4BC" => DATA <= x"00";
when x"4BD" => DATA <= x"00";
when x"4BE" => DATA <= x"00";
when x"4BF" => DATA <= x"00";
when x"4C0" => DATA <= x"00";
when x"4C1" => DATA <= x"00";
when x"4C2" => DATA <= x"30";
when x"4C3" => DATA <= x"10";
when x"4C4" => DATA <= x"10";
when x"4C5" => DATA <= x"10";
when x"4C6" => DATA <= x"10";
when x"4C7" => DATA <= x"10";
when x"4C8" => DATA <= x"38";
when x"4C9" => DATA <= x"00";
when x"4CA" => DATA <= x"00";
when x"4CB" => DATA <= x"00";
when x"4CC" => DATA <= x"00";
when x"4CD" => DATA <= x"00";
when x"4CE" => DATA <= x"00";
when x"4CF" => DATA <= x"00";
when x"4D0" => DATA <= x"00";
when x"4D1" => DATA <= x"00";
when x"4D2" => DATA <= x"00";
when x"4D3" => DATA <= x"00";
when x"4D4" => DATA <= x"78";
when x"4D5" => DATA <= x"54";
when x"4D6" => DATA <= x"54";
when x"4D7" => DATA <= x"54";
when x"4D8" => DATA <= x"54";
when x"4D9" => DATA <= x"00";
when x"4DA" => DATA <= x"00";
when x"4DB" => DATA <= x"00";
when x"4DC" => DATA <= x"00";
when x"4DD" => DATA <= x"00";
when x"4DE" => DATA <= x"00";
when x"4DF" => DATA <= x"00";
when x"4E0" => DATA <= x"00";
when x"4E1" => DATA <= x"00";
when x"4E2" => DATA <= x"00";
when x"4E3" => DATA <= x"00";
when x"4E4" => DATA <= x"58";
when x"4E5" => DATA <= x"64";
when x"4E6" => DATA <= x"44";
when x"4E7" => DATA <= x"44";
when x"4E8" => DATA <= x"44";
when x"4E9" => DATA <= x"00";
when x"4EA" => DATA <= x"00";
when x"4EB" => DATA <= x"00";
when x"4EC" => DATA <= x"00";
when x"4ED" => DATA <= x"00";
when x"4EE" => DATA <= x"00";
when x"4EF" => DATA <= x"00";
when x"4F0" => DATA <= x"00";
when x"4F1" => DATA <= x"00";
when x"4F2" => DATA <= x"00";
when x"4F3" => DATA <= x"00";
when x"4F4" => DATA <= x"38";
when x"4F5" => DATA <= x"44";
when x"4F6" => DATA <= x"44";
when x"4F7" => DATA <= x"44";
when x"4F8" => DATA <= x"38";
when x"4F9" => DATA <= x"00";
when x"4FA" => DATA <= x"00";
when x"4FB" => DATA <= x"00";
when x"4FC" => DATA <= x"00";
when x"4FD" => DATA <= x"00";
when x"4FE" => DATA <= x"00";
when x"4FF" => DATA <= x"00";
when x"500" => DATA <= x"00";
when x"501" => DATA <= x"00";
when x"502" => DATA <= x"00";
when x"503" => DATA <= x"00";
when x"504" => DATA <= x"78";
when x"505" => DATA <= x"44";
when x"506" => DATA <= x"44";
when x"507" => DATA <= x"44";
when x"508" => DATA <= x"78";
when x"509" => DATA <= x"40";
when x"50A" => DATA <= x"40";
when x"50B" => DATA <= x"00";
when x"50C" => DATA <= x"00";
when x"50D" => DATA <= x"00";
when x"50E" => DATA <= x"00";
when x"50F" => DATA <= x"00";
when x"510" => DATA <= x"00";
when x"511" => DATA <= x"00";
when x"512" => DATA <= x"00";
when x"513" => DATA <= x"00";
when x"514" => DATA <= x"3C";
when x"515" => DATA <= x"44";
when x"516" => DATA <= x"44";
when x"517" => DATA <= x"44";
when x"518" => DATA <= x"3C";
when x"519" => DATA <= x"04";
when x"51A" => DATA <= x"04";
when x"51B" => DATA <= x"00";
when x"51C" => DATA <= x"00";
when x"51D" => DATA <= x"00";
when x"51E" => DATA <= x"00";
when x"51F" => DATA <= x"00";
when x"520" => DATA <= x"00";
when x"521" => DATA <= x"00";
when x"522" => DATA <= x"00";
when x"523" => DATA <= x"00";
when x"524" => DATA <= x"58";
when x"525" => DATA <= x"64";
when x"526" => DATA <= x"40";
when x"527" => DATA <= x"40";
when x"528" => DATA <= x"40";
when x"529" => DATA <= x"00";
when x"52A" => DATA <= x"00";
when x"52B" => DATA <= x"00";
when x"52C" => DATA <= x"00";
when x"52D" => DATA <= x"00";
when x"52E" => DATA <= x"00";
when x"52F" => DATA <= x"00";
when x"530" => DATA <= x"00";
when x"531" => DATA <= x"00";
when x"532" => DATA <= x"00";
when x"533" => DATA <= x"00";
when x"534" => DATA <= x"3C";
when x"535" => DATA <= x"40";
when x"536" => DATA <= x"38";
when x"537" => DATA <= x"04";
when x"538" => DATA <= x"78";
when x"539" => DATA <= x"00";
when x"53A" => DATA <= x"00";
when x"53B" => DATA <= x"00";
when x"53C" => DATA <= x"00";
when x"53D" => DATA <= x"00";
when x"53E" => DATA <= x"00";
when x"53F" => DATA <= x"00";
when x"540" => DATA <= x"00";
when x"541" => DATA <= x"00";
when x"542" => DATA <= x"20";
when x"543" => DATA <= x"20";
when x"544" => DATA <= x"70";
when x"545" => DATA <= x"20";
when x"546" => DATA <= x"20";
when x"547" => DATA <= x"24";
when x"548" => DATA <= x"18";
when x"549" => DATA <= x"00";
when x"54A" => DATA <= x"00";
when x"54B" => DATA <= x"00";
when x"54C" => DATA <= x"00";
when x"54D" => DATA <= x"00";
when x"54E" => DATA <= x"00";
when x"54F" => DATA <= x"00";
when x"550" => DATA <= x"00";
when x"551" => DATA <= x"00";
when x"552" => DATA <= x"00";
when x"553" => DATA <= x"00";
when x"554" => DATA <= x"44";
when x"555" => DATA <= x"44";
when x"556" => DATA <= x"44";
when x"557" => DATA <= x"4C";
when x"558" => DATA <= x"34";
when x"559" => DATA <= x"00";
when x"55A" => DATA <= x"00";
when x"55B" => DATA <= x"00";
when x"55C" => DATA <= x"00";
when x"55D" => DATA <= x"00";
when x"55E" => DATA <= x"00";
when x"55F" => DATA <= x"00";
when x"560" => DATA <= x"00";
when x"561" => DATA <= x"00";
when x"562" => DATA <= x"00";
when x"563" => DATA <= x"00";
when x"564" => DATA <= x"44";
when x"565" => DATA <= x"44";
when x"566" => DATA <= x"44";
when x"567" => DATA <= x"28";
when x"568" => DATA <= x"10";
when x"569" => DATA <= x"00";
when x"56A" => DATA <= x"00";
when x"56B" => DATA <= x"00";
when x"56C" => DATA <= x"00";
when x"56D" => DATA <= x"00";
when x"56E" => DATA <= x"00";
when x"56F" => DATA <= x"00";
when x"570" => DATA <= x"00";
when x"571" => DATA <= x"00";
when x"572" => DATA <= x"00";
when x"573" => DATA <= x"00";
when x"574" => DATA <= x"44";
when x"575" => DATA <= x"54";
when x"576" => DATA <= x"54";
when x"577" => DATA <= x"28";
when x"578" => DATA <= x"28";
when x"579" => DATA <= x"00";
when x"57A" => DATA <= x"00";
when x"57B" => DATA <= x"00";
when x"57C" => DATA <= x"00";
when x"57D" => DATA <= x"00";
when x"57E" => DATA <= x"00";
when x"57F" => DATA <= x"00";
when x"580" => DATA <= x"00";
when x"581" => DATA <= x"00";
when x"582" => DATA <= x"00";
when x"583" => DATA <= x"00";
when x"584" => DATA <= x"44";
when x"585" => DATA <= x"28";
when x"586" => DATA <= x"10";
when x"587" => DATA <= x"28";
when x"588" => DATA <= x"44";
when x"589" => DATA <= x"00";
when x"58A" => DATA <= x"00";
when x"58B" => DATA <= x"00";
when x"58C" => DATA <= x"00";
when x"58D" => DATA <= x"00";
when x"58E" => DATA <= x"00";
when x"58F" => DATA <= x"00";
when x"590" => DATA <= x"00";
when x"591" => DATA <= x"00";
when x"592" => DATA <= x"00";
when x"593" => DATA <= x"00";
when x"594" => DATA <= x"44";
when x"595" => DATA <= x"44";
when x"596" => DATA <= x"44";
when x"597" => DATA <= x"3C";
when x"598" => DATA <= x"04";
when x"599" => DATA <= x"38";
when x"59A" => DATA <= x"00";
when x"59B" => DATA <= x"00";
when x"59C" => DATA <= x"00";
when x"59D" => DATA <= x"00";
when x"59E" => DATA <= x"00";
when x"59F" => DATA <= x"00";
when x"5A0" => DATA <= x"00";
when x"5A1" => DATA <= x"00";
when x"5A2" => DATA <= x"00";
when x"5A3" => DATA <= x"00";
when x"5A4" => DATA <= x"7C";
when x"5A5" => DATA <= x"08";
when x"5A6" => DATA <= x"10";
when x"5A7" => DATA <= x"20";
when x"5A8" => DATA <= x"7C";
when x"5A9" => DATA <= x"00";
when x"5AA" => DATA <= x"00";
when x"5AB" => DATA <= x"00";
when x"5AC" => DATA <= x"00";
when x"5AD" => DATA <= x"00";
when x"5AE" => DATA <= x"00";
when x"5AF" => DATA <= x"00";
when x"5B0" => DATA <= x"00";
when x"5B1" => DATA <= x"00";
when x"5B2" => DATA <= x"08";
when x"5B3" => DATA <= x"10";
when x"5B4" => DATA <= x"10";
when x"5B5" => DATA <= x"20";
when x"5B6" => DATA <= x"10";
when x"5B7" => DATA <= x"10";
when x"5B8" => DATA <= x"08";
when x"5B9" => DATA <= x"00";
when x"5BA" => DATA <= x"00";
when x"5BB" => DATA <= x"00";
when x"5BC" => DATA <= x"00";
when x"5BD" => DATA <= x"00";
when x"5BE" => DATA <= x"00";
when x"5BF" => DATA <= x"00";
when x"5C0" => DATA <= x"00";
when x"5C1" => DATA <= x"00";
when x"5C2" => DATA <= x"10";
when x"5C3" => DATA <= x"10";
when x"5C4" => DATA <= x"10";
when x"5C5" => DATA <= x"00";
when x"5C6" => DATA <= x"10";
when x"5C7" => DATA <= x"10";
when x"5C8" => DATA <= x"10";
when x"5C9" => DATA <= x"00";
when x"5CA" => DATA <= x"00";
when x"5CB" => DATA <= x"00";
when x"5CC" => DATA <= x"00";
when x"5CD" => DATA <= x"00";
when x"5CE" => DATA <= x"00";
when x"5CF" => DATA <= x"00";
when x"5D0" => DATA <= x"00";
when x"5D1" => DATA <= x"00";
when x"5D2" => DATA <= x"20";
when x"5D3" => DATA <= x"10";
when x"5D4" => DATA <= x"10";
when x"5D5" => DATA <= x"08";
when x"5D6" => DATA <= x"10";
when x"5D7" => DATA <= x"10";
when x"5D8" => DATA <= x"20";
when x"5D9" => DATA <= x"00";
when x"5DA" => DATA <= x"00";
when x"5DB" => DATA <= x"00";
when x"5DC" => DATA <= x"00";
when x"5DD" => DATA <= x"00";
when x"5DE" => DATA <= x"00";
when x"5DF" => DATA <= x"00";
when x"5E0" => DATA <= x"00";
when x"5E1" => DATA <= x"00";
when x"5E2" => DATA <= x"20";
when x"5E3" => DATA <= x"54";
when x"5E4" => DATA <= x"08";
when x"5E5" => DATA <= x"00";
when x"5E6" => DATA <= x"00";
when x"5E7" => DATA <= x"00";
when x"5E8" => DATA <= x"00";
when x"5E9" => DATA <= x"00";
when x"5EA" => DATA <= x"00";
when x"5EB" => DATA <= x"00";
when x"5EC" => DATA <= x"00";
when x"5ED" => DATA <= x"00";
when x"5EE" => DATA <= x"00";
when x"5EF" => DATA <= x"00";
when x"5F0" => DATA <= x"00";
when x"5F1" => DATA <= x"00";
when x"5F2" => DATA <= x"00";
when x"5F3" => DATA <= x"00";
when x"5F4" => DATA <= x"00";
when x"5F5" => DATA <= x"00";
when x"5F6" => DATA <= x"00";
when x"5F7" => DATA <= x"00";
when x"5F8" => DATA <= x"7C";
when others => DATA <= (others => '0');
end case;
end process;
end RTL;
| apache-2.0 | 9aa18d71ffac094585309c58e3983d06 | 0.41954 | 2.601854 | false | false | false | false |
jairov4/accel-oil | impl/impl_test_pcie/simulation/behavioral/elaborate/clock_generator_0_v4_03_a/hdl/vhdl/clock_generator.vhd | 1 | 45,054 | ------------------------------------------------------------------------------
-- C:/Users/JairoAndres/Documents/Vivado/oil_plainc_hls/impl/impl_test_pcie/simulation/behavioral/elaborate/clock_generator_0_v4_03_a/hdl/vhdl/clock_generator.vhd
------------------------------------------------------------------------------
-- ClkGen Wrapper HDL file generated by ClkGen's TCL generator
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.all;
library Unisim;
use Unisim.vcomponents.all;
library clock_generator_v4_03_a;
use clock_generator_v4_03_a.all;
entity clock_generator is
generic (
C_FAMILY : string := "virtex5" ;
C_DEVICE : string := "5vlx50t";
C_PACKAGE : string := "ff1136";
C_SPEEDGRADE : string := "-1";
C_CLK_GEN : string := "PASSED"
);
port (
-- clock generation
CLKIN : in std_logic;
CLKOUT0 : out std_logic;
CLKOUT1 : out std_logic;
CLKOUT2 : out std_logic;
CLKOUT3 : out std_logic;
CLKOUT4 : out std_logic;
CLKOUT5 : out std_logic;
CLKOUT6 : out std_logic;
CLKOUT7 : out std_logic;
CLKOUT8 : out std_logic;
CLKOUT9 : out std_logic;
CLKOUT10 : out std_logic;
CLKOUT11 : out std_logic;
CLKOUT12 : out std_logic;
CLKOUT13 : out std_logic;
CLKOUT14 : out std_logic;
CLKOUT15 : out std_logic;
-- external feedback
CLKFBIN : in std_logic;
CLKFBOUT : out std_logic;
-- variable phase shift
PSCLK : in std_logic;
PSEN : in std_logic;
PSINCDEC : in std_logic;
PSDONE : out std_logic;
-- reset
RST : in std_logic;
LOCKED : out std_logic
);
end clock_generator;
architecture STRUCTURE of clock_generator is
----------------------------------------------------------------------------
-- Components ( copy from entity, exact the same in low level parameters )
----------------------------------------------------------------------------
component dcm_module is
generic (
C_DFS_FREQUENCY_MODE : string := "LOW";
C_DLL_FREQUENCY_MODE : string := "LOW";
C_DUTY_CYCLE_CORRECTION : boolean := true;
C_CLKIN_DIVIDE_BY_2 : boolean := false;
C_CLK_FEEDBACK : string := "1X";
C_CLKOUT_PHASE_SHIFT : string := "NONE";
C_DSS_MODE : string := "NONE";
C_STARTUP_WAIT : boolean := false;
C_PHASE_SHIFT : integer := 0;
C_CLKFX_MULTIPLY : integer := 4;
C_CLKFX_DIVIDE : integer := 1;
C_CLKDV_DIVIDE : real := 2.0;
C_CLKIN_PERIOD : real := 41.6666666;
C_DESKEW_ADJUST : string := "SYSTEM_SYNCHRONOUS";
C_CLKIN_BUF : boolean := false;
C_CLKFB_BUF : boolean := false;
C_CLK0_BUF : boolean := false;
C_CLK90_BUF : boolean := false;
C_CLK180_BUF : boolean := false;
C_CLK270_BUF : boolean := false;
C_CLKDV_BUF : boolean := false;
C_CLK2X_BUF : boolean := false;
C_CLK2X180_BUF : boolean := false;
C_CLKFX_BUF : boolean := false;
C_CLKFX180_BUF : boolean := false;
C_EXT_RESET_HIGH : integer := 1;
C_FAMILY : string := "spartan6"
);
port (
RST : in std_logic;
CLKIN : in std_logic;
CLKFB : in std_logic;
PSEN : in std_logic;
PSINCDEC : in std_logic;
PSCLK : in std_logic;
DSSEN : in std_logic;
CLK0 : out std_logic;
CLK90 : out std_logic;
CLK180 : out std_logic;
CLK270 : out std_logic;
CLKDV : out std_logic;
CLK2X : out std_logic;
CLK2X180 : out std_logic;
CLKFX : out std_logic;
CLKFX180 : out std_logic;
STATUS : out std_logic_vector(7 downto 0);
LOCKED : out std_logic;
PSDONE : out std_logic
);
end component;
----------------------------------------------------------------------------
-- Components ( copy from entity, exact the same in low level parameters )
----------------------------------------------------------------------------
component pll_module is
generic (
C_BANDWIDTH : string := "OPTIMIZED";
C_CLKFBOUT_MULT : integer := 1;
C_CLKFBOUT_PHASE : real := 0.0;
C_CLKIN1_PERIOD : real := 0.000;
-- C_CLKIN2_PERIOD : real := 0.000;
C_CLKOUT0_DIVIDE : integer := 1;
C_CLKOUT0_DUTY_CYCLE : real := 0.5;
C_CLKOUT0_PHASE : real := 0.0;
C_CLKOUT1_DIVIDE : integer := 1;
C_CLKOUT1_DUTY_CYCLE : real := 0.5;
C_CLKOUT1_PHASE : real := 0.0;
C_CLKOUT2_DIVIDE : integer := 1;
C_CLKOUT2_DUTY_CYCLE : real := 0.5;
C_CLKOUT2_PHASE : real := 0.0;
C_CLKOUT3_DIVIDE : integer := 1;
C_CLKOUT3_DUTY_CYCLE : real := 0.5;
C_CLKOUT3_PHASE : real := 0.0;
C_CLKOUT4_DIVIDE : integer := 1;
C_CLKOUT4_DUTY_CYCLE : real := 0.5;
C_CLKOUT4_PHASE : real := 0.0;
C_CLKOUT5_DIVIDE : integer := 1;
C_CLKOUT5_DUTY_CYCLE : real := 0.5;
C_CLKOUT5_PHASE : real := 0.0;
C_COMPENSATION : string := "SYSTEM_SYNCHRONOUS";
C_DIVCLK_DIVIDE : integer := 1;
-- C_EN_REL : boolean := false;
-- C_PLL_PMCD_MODE : boolean := false;
C_REF_JITTER : real := 0.100;
C_RESET_ON_LOSS_OF_LOCK : boolean := false;
C_RST_DEASSERT_CLK : string := "CLKIN1";
C_CLKOUT0_DESKEW_ADJUST : string := "NONE";
C_CLKOUT1_DESKEW_ADJUST : string := "NONE";
C_CLKOUT2_DESKEW_ADJUST : string := "NONE";
C_CLKOUT3_DESKEW_ADJUST : string := "NONE";
C_CLKOUT4_DESKEW_ADJUST : string := "NONE";
C_CLKOUT5_DESKEW_ADJUST : string := "NONE";
C_CLKFBOUT_DESKEW_ADJUST : string := "NONE";
C_CLKIN1_BUF : boolean := false;
-- C_CLKIN2_BUF : boolean := false;
C_CLKFBOUT_BUF : boolean := false;
C_CLKOUT0_BUF : boolean := false;
C_CLKOUT1_BUF : boolean := false;
C_CLKOUT2_BUF : boolean := false;
C_CLKOUT3_BUF : boolean := false;
C_CLKOUT4_BUF : boolean := false;
C_CLKOUT5_BUF : boolean := false;
C_EXT_RESET_HIGH : integer := 1;
C_FAMILY : string := "spartan6"
);
port (
CLKFBDCM : out std_logic;
CLKFBOUT : out std_logic;
CLKOUT0 : out std_logic;
CLKOUT1 : out std_logic;
CLKOUT2 : out std_logic;
CLKOUT3 : out std_logic;
CLKOUT4 : out std_logic;
CLKOUT5 : out std_logic;
CLKOUTDCM0 : out std_logic;
CLKOUTDCM1 : out std_logic;
CLKOUTDCM2 : out std_logic;
CLKOUTDCM3 : out std_logic;
CLKOUTDCM4 : out std_logic;
CLKOUTDCM5 : out std_logic;
-- DO : out std_logic_vector (15 downto 0);
-- DRDY : out std_logic;
LOCKED : out std_logic;
CLKFBIN : in std_logic;
CLKIN1 : in std_logic;
-- CLKIN2 : in std_logic;
-- CLKINSEL : in std_logic;
-- DADDR : in std_logic_vector (4 downto 0);
-- DCLK : in std_logic;
-- DEN : in std_logic;
-- DI : in std_logic_vector (15 downto 0);
-- DWE : in std_logic;
-- REL : in std_logic;
RST : in std_logic
);
end component;
----------------------------------------------------------------------------
-- Functions
----------------------------------------------------------------------------
-- Note : The string functions are put here to remove dependency to other pcore level libraries
function UpperCase_Char(char : character) return character is
begin
-- If char is not an upper case letter then return char
if char < 'a' or char > 'z' then
return char;
end if;
-- Otherwise map char to its corresponding lower case character and
-- return that
case char is
when 'a' => return 'A'; when 'b' => return 'B'; when 'c' => return 'C'; when 'd' => return 'D';
when 'e' => return 'E'; when 'f' => return 'F'; when 'g' => return 'G'; when 'h' => return 'H';
when 'i' => return 'I'; when 'j' => return 'J'; when 'k' => return 'K'; when 'l' => return 'L';
when 'm' => return 'M'; when 'n' => return 'N'; when 'o' => return 'O'; when 'p' => return 'P';
when 'q' => return 'Q'; when 'r' => return 'R'; when 's' => return 'S'; when 't' => return 'T';
when 'u' => return 'U'; when 'v' => return 'V'; when 'w' => return 'W'; when 'x' => return 'X';
when 'y' => return 'Y'; when 'z' => return 'Z';
when others => return char;
end case;
end UpperCase_Char;
function UpperCase_String (s : string) return string is
variable res : string(s'range);
begin -- function LoweerCase_String
for I in s'range loop
res(I) := UpperCase_Char(s(I));
end loop; -- I
return res;
end function UpperCase_String;
-- Returns true if case insensitive string comparison determines that
-- str1 and str2 are equal
function equalString( str1, str2 : string ) return boolean is
constant len1 : integer := str1'length;
constant len2 : integer := str2'length;
variable equal : boolean := true;
begin
if not (len1 = len2) then
equal := false;
else
for i in str1'range loop
if not (UpperCase_Char(str1(i)) = UpperCase_Char(str2(i))) then
equal := false;
end if;
end loop;
end if;
return equal;
end equalString;
----------------------------------------------------------------------------
-- Signals
----------------------------------------------------------------------------
-- signals: gnd
signal net_gnd0 : std_logic;
signal net_gnd1 : std_logic_vector(0 to 0);
signal net_gnd16 : std_logic_vector(0 to 15);
-- signals: vdd
signal net_vdd0 : std_logic;
-- signals : DCM0 wrapper
signal SIG_DCM0_RST : std_logic;
signal SIG_DCM0_CLKIN : std_logic;
signal SIG_DCM0_CLKFB : std_logic;
signal SIG_DCM0_PSEN : std_logic;
signal SIG_DCM0_PSINCDEC : std_logic;
signal SIG_DCM0_PSCLK : std_logic;
signal SIG_DCM0_DSSEN : std_logic;
signal SIG_DCM0_CLK0 : std_logic;
signal SIG_DCM0_CLK90 : std_logic;
signal SIG_DCM0_CLK180 : std_logic;
signal SIG_DCM0_CLK270 : std_logic;
signal SIG_DCM0_CLKDV : std_logic;
signal SIG_DCM0_CLKDV180 : std_logic;
signal SIG_DCM0_CLK2X : std_logic;
signal SIG_DCM0_CLK2X180 : std_logic;
signal SIG_DCM0_CLKFX : std_logic;
signal SIG_DCM0_CLKFX180 : std_logic;
signal SIG_DCM0_STATUS : std_logic;
signal SIG_DCM0_LOCKED : std_logic;
signal SIG_DCM0_PSDONE : std_logic;
signal SIG_DCM0_CLK0_BUF : std_logic;
signal SIG_DCM0_CLK90_BUF : std_logic;
signal SIG_DCM0_CLK180_BUF : std_logic;
signal SIG_DCM0_CLK270_BUF : std_logic;
signal SIG_DCM0_CLKDV_BUF : std_logic;
signal SIG_DCM0_CLKDV180_BUF : std_logic;
signal SIG_DCM0_CLK2X_BUF : std_logic;
signal SIG_DCM0_CLK2X180_BUF : std_logic;
signal SIG_DCM0_CLKFX_BUF : std_logic;
signal SIG_DCM0_CLKFX180_BUF : std_logic;
-- signals : PLL0 wrapper
signal SIG_PLL0_CLKFBDCM : std_logic;
signal SIG_PLL0_CLKFBOUT : std_logic;
signal SIG_PLL0_CLKOUT0 : std_logic;
signal SIG_PLL0_CLKOUT1 : std_logic;
signal SIG_PLL0_CLKOUT2 : std_logic;
signal SIG_PLL0_CLKOUT3 : std_logic;
signal SIG_PLL0_CLKOUT4 : std_logic;
signal SIG_PLL0_CLKOUT5 : std_logic;
signal SIG_PLL0_CLKOUTDCM0 : std_logic;
signal SIG_PLL0_CLKOUTDCM1 : std_logic;
signal SIG_PLL0_CLKOUTDCM2 : std_logic;
signal SIG_PLL0_CLKOUTDCM3 : std_logic;
signal SIG_PLL0_CLKOUTDCM4 : std_logic;
signal SIG_PLL0_CLKOUTDCM5 : std_logic;
signal SIG_PLL0_LOCKED : std_logic;
signal SIG_PLL0_CLKFBIN : std_logic;
signal SIG_PLL0_CLKIN1 : std_logic;
signal SIG_PLL0_RST : std_logic;
signal SIG_PLL0_CLKFBOUT_BUF : std_logic;
signal SIG_PLL0_CLKOUT0_BUF : std_logic;
signal SIG_PLL0_CLKOUT1_BUF : std_logic;
signal SIG_PLL0_CLKOUT2_BUF : std_logic;
signal SIG_PLL0_CLKOUT3_BUF : std_logic;
signal SIG_PLL0_CLKOUT4_BUF : std_logic;
signal SIG_PLL0_CLKOUT5_BUF : std_logic;
begin
----------------------------------------------------------------------------
-- GND and VCC signals
----------------------------------------------------------------------------
net_gnd0 <= '0';
net_gnd1(0 to 0) <= B"0";
net_gnd16(0 to 15) <= B"0000000000000000";
net_vdd0 <= '1';
----------------------------------------------------------------------------
-- DCM wrappers
----------------------------------------------------------------------------
-- DCM0 wrapper
DCM0_INST : dcm_module
generic map (
C_DFS_FREQUENCY_MODE => "LOW",
C_DLL_FREQUENCY_MODE => "HIGH",
C_DUTY_CYCLE_CORRECTION => true,
C_CLKIN_DIVIDE_BY_2 => false,
C_CLK_FEEDBACK => "1X",
C_CLKOUT_PHASE_SHIFT => "NONE",
C_DSS_MODE => "NONE",
C_STARTUP_WAIT => false,
C_PHASE_SHIFT => 0,
C_CLKFX_MULTIPLY => 4,
C_CLKFX_DIVIDE => 1,
C_CLKDV_DIVIDE => 2.0,
C_CLKIN_PERIOD => 8.000000,
C_DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS",
C_CLKIN_BUF => false,
C_CLKFB_BUF => false,
C_CLK0_BUF => false,
C_CLK90_BUF => false,
C_CLK180_BUF => false,
C_CLK270_BUF => false,
C_CLKDV_BUF => false,
C_CLK2X_BUF => false,
C_CLK2X180_BUF => false,
C_CLKFX_BUF => false,
C_CLKFX180_BUF => false,
C_EXT_RESET_HIGH => 0,
C_FAMILY => "virtex5"
)
port map (
RST => SIG_DCM0_RST,
CLKIN => SIG_DCM0_CLKIN,
CLKFB => SIG_DCM0_CLKFB,
PSEN => SIG_DCM0_PSEN,
PSINCDEC => SIG_DCM0_PSINCDEC,
PSCLK => SIG_DCM0_PSCLK,
DSSEN => net_gnd0,
CLK0 => SIG_DCM0_CLK0,
CLK90 => SIG_DCM0_CLK90,
CLK180 => open,
CLK270 => SIG_DCM0_CLK270,
CLKDV => SIG_DCM0_CLKDV,
CLK2X => SIG_DCM0_CLK2X,
CLK2X180 => open,
CLKFX => SIG_DCM0_CLKFX,
CLKFX180 => open,
STATUS => open,
LOCKED => SIG_DCM0_LOCKED,
PSDONE => SIG_DCM0_PSDONE
);
-- wrapper of clkout : CLK0 and clkinv : CLK180
DCM0_CLK0_BUFG_INST : BUFG
port map (
I => SIG_DCM0_CLK0,
O => SIG_DCM0_CLK0_BUF
);
SIG_DCM0_CLK180 <= NOT SIG_DCM0_CLK0;
SIG_DCM0_CLK180_BUF <= NOT SIG_DCM0_CLK0_BUF;
-- wrapper of clkout : CLK2X and clkinv : CLK2X180
SIG_DCM0_CLK2X_BUF <= SIG_DCM0_CLK2X;
SIG_DCM0_CLK2X180 <= NOT SIG_DCM0_CLK2X;
SIG_DCM0_CLK2X180_BUF <= NOT SIG_DCM0_CLK2X_BUF;
-- wrapper of clkout : CLKDV and clkinv : CLKDV180
SIG_DCM0_CLKDV_BUF <= SIG_DCM0_CLKDV;
SIG_DCM0_CLKDV180 <= NOT SIG_DCM0_CLKDV;
SIG_DCM0_CLKDV180_BUF <= NOT SIG_DCM0_CLKDV_BUF;
-- wrapper of clkout : CLKFX and clkinv : CLKFX180
SIG_DCM0_CLKFX_BUF <= SIG_DCM0_CLKFX;
SIG_DCM0_CLKFX180 <= NOT SIG_DCM0_CLKFX;
SIG_DCM0_CLKFX180_BUF <= NOT SIG_DCM0_CLKFX_BUF;
DCM0_CLK90_BUFG_INST : BUFG
port map (
I => SIG_DCM0_CLK90,
O => SIG_DCM0_CLK90_BUF
);
DCM0_CLK270_BUFG_INST : BUFG
port map (
I => SIG_DCM0_CLK270,
O => SIG_DCM0_CLK270_BUF
);
----------------------------------------------------------------------------
-- PLL wrappers
----------------------------------------------------------------------------
-- PLL0 wrapper
PLL0_INST : pll_module
generic map (
C_BANDWIDTH => "OPTIMIZED",
C_CLKFBOUT_MULT => 10,
C_CLKFBOUT_PHASE => 0.0,
C_CLKIN1_PERIOD => 10.000000,
C_CLKOUT0_DIVIDE => 8,
C_CLKOUT0_DUTY_CYCLE => 0.5,
C_CLKOUT0_PHASE => 90.0000,
C_CLKOUT1_DIVIDE => 8,
C_CLKOUT1_DUTY_CYCLE => 0.5,
C_CLKOUT1_PHASE => 0.0000,
C_CLKOUT2_DIVIDE => 5,
C_CLKOUT2_DUTY_CYCLE => 0.5,
C_CLKOUT2_PHASE => 0.0000,
C_CLKOUT3_DIVIDE => 16,
C_CLKOUT3_DUTY_CYCLE => 0.5,
C_CLKOUT3_PHASE => 0.0000,
C_CLKOUT4_DIVIDE => 1,
C_CLKOUT4_DUTY_CYCLE => 0.5,
C_CLKOUT4_PHASE => 0.0,
C_CLKOUT5_DIVIDE => 1,
C_CLKOUT5_DUTY_CYCLE => 0.5,
C_CLKOUT5_PHASE => 0.0,
C_COMPENSATION => "SYSTEM_SYNCHRONOUS",
C_DIVCLK_DIVIDE => 1,
C_REF_JITTER => 0.100,
C_RESET_ON_LOSS_OF_LOCK => false,
C_RST_DEASSERT_CLK => "CLKIN1",
C_CLKOUT0_DESKEW_ADJUST => "NONE",
C_CLKOUT1_DESKEW_ADJUST => "NONE",
C_CLKOUT2_DESKEW_ADJUST => "NONE",
C_CLKOUT3_DESKEW_ADJUST => "NONE",
C_CLKOUT4_DESKEW_ADJUST => "NONE",
C_CLKOUT5_DESKEW_ADJUST => "NONE",
C_CLKFBOUT_DESKEW_ADJUST => "NONE",
C_CLKIN1_BUF => false,
C_CLKFBOUT_BUF => false,
C_CLKOUT0_BUF => false,
C_CLKOUT1_BUF => false,
C_CLKOUT2_BUF => false,
C_CLKOUT3_BUF => false,
C_CLKOUT4_BUF => false,
C_CLKOUT5_BUF => false,
C_EXT_RESET_HIGH => 0,
C_FAMILY => "virtex5"
)
port map (
CLKFBDCM => SIG_PLL0_CLKFBDCM,
CLKFBOUT => SIG_PLL0_CLKFBOUT,
CLKOUT0 => SIG_PLL0_CLKOUT0,
CLKOUT1 => SIG_PLL0_CLKOUT1,
CLKOUT2 => SIG_PLL0_CLKOUT2,
CLKOUT3 => SIG_PLL0_CLKOUT3,
CLKOUT4 => SIG_PLL0_CLKOUT4,
CLKOUT5 => SIG_PLL0_CLKOUT5,
CLKOUTDCM0 => SIG_PLL0_CLKOUTDCM0,
CLKOUTDCM1 => SIG_PLL0_CLKOUTDCM1,
CLKOUTDCM2 => SIG_PLL0_CLKOUTDCM2,
CLKOUTDCM3 => SIG_PLL0_CLKOUTDCM3,
CLKOUTDCM4 => SIG_PLL0_CLKOUTDCM4,
CLKOUTDCM5 => SIG_PLL0_CLKOUTDCM5,
-- DO
-- DRDY
LOCKED => SIG_PLL0_LOCKED,
CLKFBIN => SIG_PLL0_CLKFBIN,
CLKIN1 => SIG_PLL0_CLKIN1,
-- CLKIN2
-- CLKINSEL
-- DADDR
-- DCLK
-- DEN
-- DI
-- DWE
-- REL
RST => SIG_PLL0_RST
);
-- wrapper of clkout : CLKOUT0
PLL0_CLKOUT0_BUFG_INST : BUFG
port map (
I => SIG_PLL0_CLKOUT0,
O => SIG_PLL0_CLKOUT0_BUF
);
-- wrapper of clkout : CLKOUT1
PLL0_CLKOUT1_BUFG_INST : BUFG
port map (
I => SIG_PLL0_CLKOUT1,
O => SIG_PLL0_CLKOUT1_BUF
);
-- wrapper of clkout : CLKOUT2
PLL0_CLKOUT2_BUFG_INST : BUFG
port map (
I => SIG_PLL0_CLKOUT2,
O => SIG_PLL0_CLKOUT2_BUF
);
-- wrapper of clkout : CLKOUT3
PLL0_CLKOUT3_BUFG_INST : BUFG
port map (
I => SIG_PLL0_CLKOUT3,
O => SIG_PLL0_CLKOUT3_BUF
);
-- wrapper of clkout : CLKOUT4
SIG_PLL0_CLKOUT4_BUF <= SIG_PLL0_CLKOUT4;
-- wrapper of clkout : CLKOUT5
SIG_PLL0_CLKOUT5_BUF <= SIG_PLL0_CLKOUT5;
-- wrapper of clkout : CLKFBOUT
PLL0_CLKFBOUT_BUFG_INST : BUFG
port map (
I => SIG_PLL0_CLKFBOUT,
O => SIG_PLL0_CLKFBOUT_BUF
);
----------------------------------------------------------------------------
-- MMCM wrappers
----------------------------------------------------------------------------
----------------------------------------------------------------------------
-- PLLE wrappers
----------------------------------------------------------------------------
----------------------------------------------------------------------------
-- DCMs CLKIN, CLKFB and RST signal connection
----------------------------------------------------------------------------
-- DCM0 CLKIN
SIG_DCM0_CLKIN <= SIG_PLL0_CLKOUT1_BUF;
-- DCM0 CLKFB
SIG_DCM0_CLKFB <= CLKFBIN;
-- DCM0 RST
SIG_DCM0_RST <= SIG_PLL0_LOCKED;
----------------------------------------------------------------------------
-- PLLs CLKIN1, CLKFBIN and RST signal connection
----------------------------------------------------------------------------
-- PLL0 CLKIN1
SIG_PLL0_CLKIN1 <= CLKIN;
-- PLL0 CLKFBIN
SIG_PLL0_CLKFBIN <= SIG_PLL0_CLKFBOUT;
-- PLL0 RST
SIG_PLL0_RST <= RST;
----------------------------------------------------------------------------
-- MMCMs CLKIN1, CLKFBIN, RST and Variable_Phase_Control signal connection
----------------------------------------------------------------------------
----------------------------------------------------------------------------
-- PLLEs CLKIN1, CLKFBIN, RST and Variable_Phase_Control signal connection
----------------------------------------------------------------------------
----------------------------------------------------------------------------
-- CLKGEN CLKOUT, CLKFBOUT and LOCKED signal connection
----------------------------------------------------------------------------
-- CLKGEN CLKOUT
CLKOUT0 <= SIG_PLL0_CLKOUT0_BUF;
CLKOUT1 <= SIG_PLL0_CLKOUT1_BUF;
CLKOUT2 <= SIG_PLL0_CLKOUT2_BUF;
CLKOUT3 <= SIG_PLL0_CLKOUT3_BUF;
CLKOUT4 <= '0';
CLKOUT5 <= '0';
CLKOUT6 <= '0';
CLKOUT7 <= '0';
CLKOUT8 <= '0';
CLKOUT9 <= '0';
CLKOUT10 <= '0';
CLKOUT11 <= '0';
CLKOUT12 <= '0';
CLKOUT13 <= '0';
CLKOUT14 <= '0';
CLKOUT15 <= '0';
-- CLKGEN CLKFBOUT
CLKFBOUT <= SIG_DCM0_CLK0_BUF;
-- CLKGEN LOCKED
LOCKED <= SIG_DCM0_LOCKED and SIG_PLL0_LOCKED;
end architecture STRUCTURE;
------------------------------------------------------------------------------
-- High level parameters
------------------------------------------------------------------------------
-- C_CLK_GEN = PASSED
-- C_ELABORATE_DIR =
-- C_ELABORATE_RES = NOT_SET
-- C_FAMILY = virtex5
-- C_DEVICE = 5vlx50t
-- C_PACKAGE = ff1136
-- C_SPEEDGRADE = -1
----------------------------------------
-- C_EXTRA_MMCM_FOR_DESKEW =
-- C_MMCMExtra_CLKIN_FREQ =
-- C_MMCMExtra_CLKOUT0 =
-- C_MMCMExtra_CLKOUT1 =
-- C_MMCMExtra_CLKOUT2 =
-- C_MMCMExtra_CLKOUT3 =
-- C_MMCMExtra_CLKOUT4 =
-- C_MMCMExtra_CLKOUT5 =
-- C_MMCMExtra_CLKOUT6 =
-- C_MMCMExtra_CLKOUT7 =
-- C_MMCMExtra_CLKOUT8 =
-- C_MMCMExtra_CLKOUT9 =
-- C_MMCMExtra_CLKOUT10 =
-- C_MMCMExtra_CLKOUT11 =
-- C_MMCMExtra_CLKOUT12 =
-- C_MMCMExtra_CLKOUT13 =
-- C_MMCMExtra_CLKOUT14 =
-- C_MMCMExtra_CLKOUT15 =
-- C_MMCMExtra_CLKFBOUT_MULT =
-- C_MMCMExtra_DIVCLK_DIVIDE =
-- C_MMCMExtra_CLKOUT0_DIVIDE =
-- C_MMCMExtra_CLKOUT1_DIVIDE =
-- C_MMCMExtra_CLKOUT2_DIVIDE =
-- C_MMCMExtra_CLKOUT3_DIVIDE =
-- C_MMCMExtra_CLKOUT4_DIVIDE =
-- C_MMCMExtra_CLKOUT5_DIVIDE =
-- C_MMCMExtra_CLKOUT6_DIVIDE =
-- C_MMCMExtra_CLKOUT0_BUF =
-- C_MMCMExtra_CLKOUT1_BUF =
-- C_MMCMExtra_CLKOUT2_BUF =
-- C_MMCMExtra_CLKOUT3_BUF =
-- C_MMCMExtra_CLKOUT4_BUF =
-- C_MMCMExtra_CLKOUT5_BUF =
-- C_MMCMExtra_CLKOUT6_BUF =
-- C_MMCMExtra_CLKFBOUT_BUF =
-- C_MMCMExtra_CLKOUT0_PHASE =
-- C_MMCMExtra_CLKOUT1_PHASE =
-- C_MMCMExtra_CLKOUT2_PHASE =
-- C_MMCMExtra_CLKOUT3_PHASE =
-- C_MMCMExtra_CLKOUT4_PHASE =
-- C_MMCMExtra_CLKOUT5_PHASE =
-- C_MMCMExtra_CLKOUT6_PHASE =
----------------------------------------
-- C_CLKIN_FREQ = 100000000
-- C_CLKOUT0_FREQ = 125000000
-- C_CLKOUT0_PHASE = 90
-- C_CLKOUT0_GROUP = PLL0
-- C_CLKOUT0_BUF = TRUE
-- C_CLKOUT0_VARIABLE_PHASE = FALSE
-- C_CLKOUT1_FREQ = 125000000
-- C_CLKOUT1_PHASE = 0
-- C_CLKOUT1_GROUP = PLL0
-- C_CLKOUT1_BUF = TRUE
-- C_CLKOUT1_VARIABLE_PHASE = FALSE
-- C_CLKOUT2_FREQ = 200000000
-- C_CLKOUT2_PHASE = 0
-- C_CLKOUT2_GROUP = NONE
-- C_CLKOUT2_BUF = TRUE
-- C_CLKOUT2_VARIABLE_PHASE = FALSE
-- C_CLKOUT3_FREQ = 62500000
-- C_CLKOUT3_PHASE = 0
-- C_CLKOUT3_GROUP = PLL0
-- C_CLKOUT3_BUF = TRUE
-- C_CLKOUT3_VARIABLE_PHASE = FALSE
-- C_CLKOUT4_FREQ = 0
-- C_CLKOUT4_PHASE = 0
-- C_CLKOUT4_GROUP = NONE
-- C_CLKOUT4_BUF = TRUE
-- C_CLKOUT4_VARIABLE_PHASE = FALSE
-- C_CLKOUT5_FREQ = 0
-- C_CLKOUT5_PHASE = 0
-- C_CLKOUT5_GROUP = NONE
-- C_CLKOUT5_BUF = TRUE
-- C_CLKOUT5_VARIABLE_PHASE = FALSE
-- C_CLKOUT6_FREQ = 0
-- C_CLKOUT6_PHASE = 0
-- C_CLKOUT6_GROUP = NONE
-- C_CLKOUT6_BUF = TRUE
-- C_CLKOUT6_VARIABLE_PHASE = FALSE
-- C_CLKOUT7_FREQ = 0
-- C_CLKOUT7_PHASE = 0
-- C_CLKOUT7_GROUP = NONE
-- C_CLKOUT7_BUF = TRUE
-- C_CLKOUT7_VARIABLE_PHASE = FALSE
-- C_CLKOUT8_FREQ = 0
-- C_CLKOUT8_PHASE = 0
-- C_CLKOUT8_GROUP = NONE
-- C_CLKOUT8_BUF = TRUE
-- C_CLKOUT8_VARIABLE_PHASE = FALSE
-- C_CLKOUT9_FREQ = 0
-- C_CLKOUT9_PHASE = 0
-- C_CLKOUT9_GROUP = NONE
-- C_CLKOUT9_BUF = TRUE
-- C_CLKOUT9_VARIABLE_PHASE = FALSE
-- C_CLKOUT10_FREQ = 0
-- C_CLKOUT10_PHASE = 0
-- C_CLKOUT10_GROUP = NONE
-- C_CLKOUT10_BUF = TRUE
-- C_CLKOUT10_VARIABLE_PHASE = FALSE
-- C_CLKOUT11_FREQ = 0
-- C_CLKOUT11_PHASE = 0
-- C_CLKOUT11_GROUP = NONE
-- C_CLKOUT11_BUF = TRUE
-- C_CLKOUT11_VARIABLE_PHASE = FALSE
-- C_CLKOUT12_FREQ = 0
-- C_CLKOUT12_PHASE = 0
-- C_CLKOUT12_GROUP = NONE
-- C_CLKOUT12_BUF = TRUE
-- C_CLKOUT12_VARIABLE_PHASE = FALSE
-- C_CLKOUT13_FREQ = 0
-- C_CLKOUT13_PHASE = 0
-- C_CLKOUT13_GROUP = NONE
-- C_CLKOUT13_BUF = TRUE
-- C_CLKOUT13_VARIABLE_PHASE = FALSE
-- C_CLKOUT14_FREQ = 0
-- C_CLKOUT14_PHASE = 0
-- C_CLKOUT14_GROUP = NONE
-- C_CLKOUT14_BUF = TRUE
-- C_CLKOUT14_VARIABLE_PHASE = FALSE
-- C_CLKOUT15_FREQ = 0
-- C_CLKOUT15_PHASE = 0
-- C_CLKOUT15_GROUP = NONE
-- C_CLKOUT15_BUF = TRUE
-- C_CLKOUT15_VARIABLE_PHASE = FALSE
----------------------------------------
-- C_CLKFBIN_FREQ = 125000000
-- C_CLKFBIN_DESKEW = NONE
-- C_CLKFBOUT_FREQ = 125000000
-- C_CLKFBOUT_GROUP = NONE
-- C_CLKFBOUT_BUF = TRUE
----------------------------------------
-- C_PSDONE_GROUP = NONE
------------------------------------------------------------------------------
-- Low level parameters
------------------------------------------------------------------------------
-- C_CLKOUT0_MODULE = PLL0
-- C_CLKOUT0_PORT = CLKOUT0B
-- C_CLKOUT1_MODULE = PLL0
-- C_CLKOUT1_PORT = CLKOUT1B
-- C_CLKOUT2_MODULE = PLL0
-- C_CLKOUT2_PORT = CLKOUT2B
-- C_CLKOUT3_MODULE = PLL0
-- C_CLKOUT3_PORT = CLKOUT3B
-- C_CLKOUT4_MODULE = NONE
-- C_CLKOUT4_PORT = NONE
-- C_CLKOUT5_MODULE = NONE
-- C_CLKOUT5_PORT = NONE
-- C_CLKOUT6_MODULE = NONE
-- C_CLKOUT6_PORT = NONE
-- C_CLKOUT7_MODULE = NONE
-- C_CLKOUT7_PORT = NONE
-- C_CLKOUT8_MODULE = NONE
-- C_CLKOUT8_PORT = NONE
-- C_CLKOUT9_MODULE = NONE
-- C_CLKOUT9_PORT = NONE
-- C_CLKOUT10_MODULE = NONE
-- C_CLKOUT10_PORT = NONE
-- C_CLKOUT11_MODULE = NONE
-- C_CLKOUT11_PORT = NONE
-- C_CLKOUT12_MODULE = NONE
-- C_CLKOUT12_PORT = NONE
-- C_CLKOUT13_MODULE = NONE
-- C_CLKOUT13_PORT = NONE
-- C_CLKOUT14_MODULE = NONE
-- C_CLKOUT14_PORT = NONE
-- C_CLKOUT15_MODULE = NONE
-- C_CLKOUT15_PORT = NONE
----------------------------------------
-- C_CLKFBOUT_MODULE = DCM0
-- C_CLKFBOUT_PORT = CLK0B
-- C_CLKFBOUT_get_clkgen_dcm_default_params = NONE
----------------------------------------
-- C_PSDONE_MODULE = NONE
----------------------------------------
-- C_DCM0_DFS_FREQUENCY_MODE = "LOW"
-- C_DCM0_DLL_FREQUENCY_MODE = "HIGH"
-- C_DCM0_DUTY_CYCLE_CORRECTION = true
-- C_DCM0_CLKIN_DIVIDE_BY_2 = false
-- C_DCM0_CLK_FEEDBACK = "1X"
-- C_DCM0_CLKOUT_PHASE_SHIFT = "NONE"
-- C_DCM0_DSS_MODE = "NONE"
-- C_DCM0_STARTUP_WAIT = false
-- C_DCM0_PHASE_SHIFT = 0
-- C_DCM0_CLKFX_MULTIPLY = 4
-- C_DCM0_CLKFX_DIVIDE = 1
-- C_DCM0_CLKDV_DIVIDE = 2.0
-- C_DCM0_CLKIN_PERIOD = 8.000000
-- C_DCM0_DESKEW_ADJUST = "SYSTEM_SYNCHRONOUS"
-- C_DCM0_CLKIN_BUF = false
-- C_DCM0_CLKFB_BUF = false
-- C_DCM0_CLK0_BUF = TRUE
-- C_DCM0_CLK90_BUF = false
-- C_DCM0_CLK180_BUF = false
-- C_DCM0_CLK270_BUF = false
-- C_DCM0_CLKDV_BUF = false
-- C_DCM0_CLK2X_BUF = false
-- C_DCM0_CLK2X180_BUF = false
-- C_DCM0_CLKFX_BUF = false
-- C_DCM0_CLKFX180_BUF = false
-- C_DCM0_EXT_RESET_HIGH = 0
-- C_DCM0_FAMILY = "virtex5"
-- C_DCM0_CLKIN_MODULE = PLL0
-- C_DCM0_CLKIN_PORT = CLKOUT1B
-- C_DCM0_CLKFB_MODULE = CLKGEN
-- C_DCM0_CLKFB_PORT = CLKFBIN
-- C_DCM0_RST_MODULE = PLL0
-- C_DCM1_DFS_FREQUENCY_MODE = "LOW"
-- C_DCM1_DLL_FREQUENCY_MODE = "LOW"
-- C_DCM1_DUTY_CYCLE_CORRECTION = true
-- C_DCM1_CLKIN_DIVIDE_BY_2 = false
-- C_DCM1_CLK_FEEDBACK = "1X"
-- C_DCM1_CLKOUT_PHASE_SHIFT = "NONE"
-- C_DCM1_DSS_MODE = "NONE"
-- C_DCM1_STARTUP_WAIT = false
-- C_DCM1_PHASE_SHIFT = 0
-- C_DCM1_CLKFX_MULTIPLY = 4
-- C_DCM1_CLKFX_DIVIDE = 1
-- C_DCM1_CLKDV_DIVIDE = 2.0
-- C_DCM1_CLKIN_PERIOD = 41.6666666
-- C_DCM1_DESKEW_ADJUST = "SYSTEM_SYNCHRONOUS"
-- C_DCM1_CLKIN_BUF = false
-- C_DCM1_CLKFB_BUF = false
-- C_DCM1_CLK0_BUF = false
-- C_DCM1_CLK90_BUF = false
-- C_DCM1_CLK180_BUF = false
-- C_DCM1_CLK270_BUF = false
-- C_DCM1_CLKDV_BUF = false
-- C_DCM1_CLK2X_BUF = false
-- C_DCM1_CLK2X180_BUF = false
-- C_DCM1_CLKFX_BUF = false
-- C_DCM1_CLKFX180_BUF = false
-- C_DCM1_EXT_RESET_HIGH = 1
-- C_DCM1_FAMILY = "virtex5"
-- C_DCM1_CLKIN_MODULE = NONE
-- C_DCM1_CLKIN_PORT = NONE
-- C_DCM1_CLKFB_MODULE = NONE
-- C_DCM1_CLKFB_PORT = NONE
-- C_DCM1_RST_MODULE = NONE
-- C_DCM2_DFS_FREQUENCY_MODE = "LOW"
-- C_DCM2_DLL_FREQUENCY_MODE = "LOW"
-- C_DCM2_DUTY_CYCLE_CORRECTION = true
-- C_DCM2_CLKIN_DIVIDE_BY_2 = false
-- C_DCM2_CLK_FEEDBACK = "1X"
-- C_DCM2_CLKOUT_PHASE_SHIFT = "NONE"
-- C_DCM2_DSS_MODE = "NONE"
-- C_DCM2_STARTUP_WAIT = false
-- C_DCM2_PHASE_SHIFT = 0
-- C_DCM2_CLKFX_MULTIPLY = 4
-- C_DCM2_CLKFX_DIVIDE = 1
-- C_DCM2_CLKDV_DIVIDE = 2.0
-- C_DCM2_CLKIN_PERIOD = 41.6666666
-- C_DCM2_DESKEW_ADJUST = "SYSTEM_SYNCHRONOUS"
-- C_DCM2_CLKIN_BUF = false
-- C_DCM2_CLKFB_BUF = false
-- C_DCM2_CLK0_BUF = false
-- C_DCM2_CLK90_BUF = false
-- C_DCM2_CLK180_BUF = false
-- C_DCM2_CLK270_BUF = false
-- C_DCM2_CLKDV_BUF = false
-- C_DCM2_CLK2X_BUF = false
-- C_DCM2_CLK2X180_BUF = false
-- C_DCM2_CLKFX_BUF = false
-- C_DCM2_CLKFX180_BUF = false
-- C_DCM2_EXT_RESET_HIGH = 1
-- C_DCM2_FAMILY = "virtex5"
-- C_DCM2_CLKIN_MODULE = NONE
-- C_DCM2_CLKIN_PORT = NONE
-- C_DCM2_CLKFB_MODULE = NONE
-- C_DCM2_CLKFB_PORT = NONE
-- C_DCM2_RST_MODULE = NONE
-- C_DCM3_DFS_FREQUENCY_MODE = "LOW"
-- C_DCM3_DLL_FREQUENCY_MODE = "LOW"
-- C_DCM3_DUTY_CYCLE_CORRECTION = true
-- C_DCM3_CLKIN_DIVIDE_BY_2 = false
-- C_DCM3_CLK_FEEDBACK = "1X"
-- C_DCM3_CLKOUT_PHASE_SHIFT = "NONE"
-- C_DCM3_DSS_MODE = "NONE"
-- C_DCM3_STARTUP_WAIT = false
-- C_DCM3_PHASE_SHIFT = 0
-- C_DCM3_CLKFX_MULTIPLY = 4
-- C_DCM3_CLKFX_DIVIDE = 1
-- C_DCM3_CLKDV_DIVIDE = 2.0
-- C_DCM3_CLKIN_PERIOD = 41.6666666
-- C_DCM3_DESKEW_ADJUST = "SYSTEM_SYNCHRONOUS"
-- C_DCM3_CLKIN_BUF = false
-- C_DCM3_CLKFB_BUF = false
-- C_DCM3_CLK0_BUF = false
-- C_DCM3_CLK90_BUF = false
-- C_DCM3_CLK180_BUF = false
-- C_DCM3_CLK270_BUF = false
-- C_DCM3_CLKDV_BUF = false
-- C_DCM3_CLK2X_BUF = false
-- C_DCM3_CLK2X180_BUF = false
-- C_DCM3_CLKFX_BUF = false
-- C_DCM3_CLKFX180_BUF = false
-- C_DCM3_EXT_RESET_HIGH = 1
-- C_DCM3_FAMILY = "virtex5"
-- C_DCM3_CLKIN_MODULE = NONE
-- C_DCM3_CLKIN_PORT = NONE
-- C_DCM3_CLKFB_MODULE = NONE
-- C_DCM3_CLKFB_PORT = NONE
-- C_DCM3_RST_MODULE = NONE
----------------------------------------
-- C_PLL0_BANDWIDTH = "OPTIMIZED"
-- C_PLL0_CLKFBOUT_MULT = 10
-- C_PLL0_CLKFBOUT_PHASE = 0.0
-- C_PLL0_CLKIN1_PERIOD = 10.000000
-- C_PLL0_CLKOUT0_DIVIDE = 8
-- C_PLL0_CLKOUT0_DUTY_CYCLE = 0.5
-- C_PLL0_CLKOUT0_PHASE = 90.0000
-- C_PLL0_CLKOUT1_DIVIDE = 8
-- C_PLL0_CLKOUT1_DUTY_CYCLE = 0.5
-- C_PLL0_CLKOUT1_PHASE = 0.0000
-- C_PLL0_CLKOUT2_DIVIDE = 5
-- C_PLL0_CLKOUT2_DUTY_CYCLE = 0.5
-- C_PLL0_CLKOUT2_PHASE = 0.0000
-- C_PLL0_CLKOUT3_DIVIDE = 16
-- C_PLL0_CLKOUT3_DUTY_CYCLE = 0.5
-- C_PLL0_CLKOUT3_PHASE = 0.0000
-- C_PLL0_CLKOUT4_DIVIDE = 1
-- C_PLL0_CLKOUT4_DUTY_CYCLE = 0.5
-- C_PLL0_CLKOUT4_PHASE = 0.0
-- C_PLL0_CLKOUT5_DIVIDE = 1
-- C_PLL0_CLKOUT5_DUTY_CYCLE = 0.5
-- C_PLL0_CLKOUT5_PHASE = 0.0
-- C_PLL0_COMPENSATION = "SYSTEM_SYNCHRONOUS"
-- C_PLL0_DIVCLK_DIVIDE = 1
-- C_PLL0_REF_JITTER = 0.100
-- C_PLL0_RESET_ON_LOSS_OF_LOCK = false
-- C_PLL0_RST_DEASSERT_CLK = "CLKIN1"
-- C_PLL0_CLKOUT0_DESKEW_ADJUST = "NONE"
-- C_PLL0_CLKOUT1_DESKEW_ADJUST = "NONE"
-- C_PLL0_CLKOUT2_DESKEW_ADJUST = "NONE"
-- C_PLL0_CLKOUT3_DESKEW_ADJUST = "NONE"
-- C_PLL0_CLKOUT4_DESKEW_ADJUST = "NONE"
-- C_PLL0_CLKOUT5_DESKEW_ADJUST = "NONE"
-- C_PLL0_CLKFBOUT_DESKEW_ADJUST = "NONE"
-- C_PLL0_CLKIN1_BUF = false
-- C_PLL0_CLKFBOUT_BUF = TRUE
-- C_PLL0_CLKOUT0_BUF = TRUE
-- C_PLL0_CLKOUT1_BUF = TRUE
-- C_PLL0_CLKOUT2_BUF = TRUE
-- C_PLL0_CLKOUT3_BUF = TRUE
-- C_PLL0_CLKOUT4_BUF = false
-- C_PLL0_CLKOUT5_BUF = false
-- C_PLL0_EXT_RESET_HIGH = 0
-- C_PLL0_FAMILY = "virtex5"
-- C_PLL0_CLKIN1_MODULE = CLKGEN
-- C_PLL0_CLKIN1_PORT = CLKIN
-- C_PLL0_CLKFBIN_MODULE = PLL0
-- C_PLL0_CLKFBIN_PORT = CLKFBOUT
-- C_PLL0_RST_MODULE = CLKGEN
-- C_PLL1_BANDWIDTH = "OPTIMIZED"
-- C_PLL1_CLKFBOUT_MULT = 1
-- C_PLL1_CLKFBOUT_PHASE = 0.0
-- C_PLL1_CLKIN1_PERIOD = 0.000
-- C_PLL1_CLKOUT0_DIVIDE = 1
-- C_PLL1_CLKOUT0_DUTY_CYCLE = 0.5
-- C_PLL1_CLKOUT0_PHASE = 0.0
-- C_PLL1_CLKOUT1_DIVIDE = 1
-- C_PLL1_CLKOUT1_DUTY_CYCLE = 0.5
-- C_PLL1_CLKOUT1_PHASE = 0.0
-- C_PLL1_CLKOUT2_DIVIDE = 1
-- C_PLL1_CLKOUT2_DUTY_CYCLE = 0.5
-- C_PLL1_CLKOUT2_PHASE = 0.0
-- C_PLL1_CLKOUT3_DIVIDE = 1
-- C_PLL1_CLKOUT3_DUTY_CYCLE = 0.5
-- C_PLL1_CLKOUT3_PHASE = 0.0
-- C_PLL1_CLKOUT4_DIVIDE = 1
-- C_PLL1_CLKOUT4_DUTY_CYCLE = 0.5
-- C_PLL1_CLKOUT4_PHASE = 0.0
-- C_PLL1_CLKOUT5_DIVIDE = 1
-- C_PLL1_CLKOUT5_DUTY_CYCLE = 0.5
-- C_PLL1_CLKOUT5_PHASE = 0.0
-- C_PLL1_COMPENSATION = "SYSTEM_SYNCHRONOUS"
-- C_PLL1_DIVCLK_DIVIDE = 1
-- C_PLL1_REF_JITTER = 0.100
-- C_PLL1_RESET_ON_LOSS_OF_LOCK = false
-- C_PLL1_RST_DEASSERT_CLK = "CLKIN1"
-- C_PLL1_CLKOUT0_DESKEW_ADJUST = "NONE"
-- C_PLL1_CLKOUT1_DESKEW_ADJUST = "NONE"
-- C_PLL1_CLKOUT2_DESKEW_ADJUST = "NONE"
-- C_PLL1_CLKOUT3_DESKEW_ADJUST = "NONE"
-- C_PLL1_CLKOUT4_DESKEW_ADJUST = "NONE"
-- C_PLL1_CLKOUT5_DESKEW_ADJUST = "NONE"
-- C_PLL1_CLKFBOUT_DESKEW_ADJUST = "NONE"
-- C_PLL1_CLKIN1_BUF = false
-- C_PLL1_CLKFBOUT_BUF = false
-- C_PLL1_CLKOUT0_BUF = false
-- C_PLL1_CLKOUT1_BUF = false
-- C_PLL1_CLKOUT2_BUF = false
-- C_PLL1_CLKOUT3_BUF = false
-- C_PLL1_CLKOUT4_BUF = false
-- C_PLL1_CLKOUT5_BUF = false
-- C_PLL1_EXT_RESET_HIGH = 1
-- C_PLL1_FAMILY = "virtex5"
-- C_PLL1_CLKIN1_MODULE = NONE
-- C_PLL1_CLKIN1_PORT = NONE
-- C_PLL1_CLKFBIN_MODULE = NONE
-- C_PLL1_CLKFBIN_PORT = NONE
-- C_PLL1_RST_MODULE = NONE
----------------------------------------
-- C_MMCM0_BANDWIDTH = "OPTIMIZED"
-- C_MMCM0_CLKFBOUT_MULT_F = 1.0
-- C_MMCM0_CLKFBOUT_PHASE = 0.0
-- C_MMCM0_CLKFBOUT_USE_FINE_PS = false
-- C_MMCM0_CLKIN1_PERIOD = 0.000
-- C_MMCM0_CLKOUT0_DIVIDE_F = 1.0
-- C_MMCM0_CLKOUT0_DUTY_CYCLE = 0.5
-- C_MMCM0_CLKOUT0_PHASE = 0.0
-- C_MMCM0_CLKOUT1_DIVIDE = 1
-- C_MMCM0_CLKOUT1_DUTY_CYCLE = 0.5
-- C_MMCM0_CLKOUT1_PHASE = 0.0
-- C_MMCM0_CLKOUT2_DIVIDE = 1
-- C_MMCM0_CLKOUT2_DUTY_CYCLE = 0.5
-- C_MMCM0_CLKOUT2_PHASE = 0.0
-- C_MMCM0_CLKOUT3_DIVIDE = 1
-- C_MMCM0_CLKOUT3_DUTY_CYCLE = 0.5
-- C_MMCM0_CLKOUT3_PHASE = 0.0
-- C_MMCM0_CLKOUT4_DIVIDE = 1
-- C_MMCM0_CLKOUT4_DUTY_CYCLE = 0.5
-- C_MMCM0_CLKOUT4_PHASE = 0.0
-- C_MMCM0_CLKOUT4_CASCADE = false
-- C_MMCM0_CLKOUT5_DIVIDE = 1
-- C_MMCM0_CLKOUT5_DUTY_CYCLE = 0.5
-- C_MMCM0_CLKOUT5_PHASE = 0.0
-- C_MMCM0_CLKOUT6_DIVIDE = 1
-- C_MMCM0_CLKOUT6_DUTY_CYCLE = 0.5
-- C_MMCM0_CLKOUT6_PHASE = 0.0
-- C_MMCM0_CLKOUT0_USE_FINE_PS = false
-- C_MMCM0_CLKOUT1_USE_FINE_PS = false
-- C_MMCM0_CLKOUT2_USE_FINE_PS = false
-- C_MMCM0_CLKOUT3_USE_FINE_PS = false
-- C_MMCM0_CLKOUT4_USE_FINE_PS = false
-- C_MMCM0_CLKOUT5_USE_FINE_PS = false
-- C_MMCM0_CLKOUT6_USE_FINE_PS = false
-- C_MMCM0_COMPENSATION = "ZHOLD"
-- C_MMCM0_DIVCLK_DIVIDE = 1
-- C_MMCM0_REF_JITTER1 = 0.010
-- C_MMCM0_CLKIN1_BUF = false
-- C_MMCM0_CLKFBOUT_BUF = false
-- C_MMCM0_CLKOUT0_BUF = false
-- C_MMCM0_CLKOUT1_BUF = false
-- C_MMCM0_CLKOUT2_BUF = false
-- C_MMCM0_CLKOUT3_BUF = false
-- C_MMCM0_CLKOUT4_BUF = false
-- C_MMCM0_CLKOUT5_BUF = false
-- C_MMCM0_CLKOUT6_BUF = false
-- C_MMCM0_CLOCK_HOLD = false
-- C_MMCM0_STARTUP_WAIT = false
-- C_MMCM0_EXT_RESET_HIGH = 1
-- C_MMCM0_FAMILY = "virtex5"
-- C_MMCM0_CLKIN1_MODULE = NONE
-- C_MMCM0_CLKIN1_PORT = NONE
-- C_MMCM0_CLKFBIN_MODULE = NONE
-- C_MMCM0_CLKFBIN_PORT = NONE
-- C_MMCM0_RST_MODULE = NONE
-- C_MMCM1_BANDWIDTH = "OPTIMIZED"
-- C_MMCM1_CLKFBOUT_MULT_F = 1.0
-- C_MMCM1_CLKFBOUT_PHASE = 0.0
-- C_MMCM1_CLKFBOUT_USE_FINE_PS = false
-- C_MMCM1_CLKIN1_PERIOD = 0.000
-- C_MMCM1_CLKOUT0_DIVIDE_F = 1.0
-- C_MMCM1_CLKOUT0_DUTY_CYCLE = 0.5
-- C_MMCM1_CLKOUT0_PHASE = 0.0
-- C_MMCM1_CLKOUT1_DIVIDE = 1
-- C_MMCM1_CLKOUT1_DUTY_CYCLE = 0.5
-- C_MMCM1_CLKOUT1_PHASE = 0.0
-- C_MMCM1_CLKOUT2_DIVIDE = 1
-- C_MMCM1_CLKOUT2_DUTY_CYCLE = 0.5
-- C_MMCM1_CLKOUT2_PHASE = 0.0
-- C_MMCM1_CLKOUT3_DIVIDE = 1
-- C_MMCM1_CLKOUT3_DUTY_CYCLE = 0.5
-- C_MMCM1_CLKOUT3_PHASE = 0.0
-- C_MMCM1_CLKOUT4_DIVIDE = 1
-- C_MMCM1_CLKOUT4_DUTY_CYCLE = 0.5
-- C_MMCM1_CLKOUT4_PHASE = 0.0
-- C_MMCM1_CLKOUT4_CASCADE = false
-- C_MMCM1_CLKOUT5_DIVIDE = 1
-- C_MMCM1_CLKOUT5_DUTY_CYCLE = 0.5
-- C_MMCM1_CLKOUT5_PHASE = 0.0
-- C_MMCM1_CLKOUT6_DIVIDE = 1
-- C_MMCM1_CLKOUT6_DUTY_CYCLE = 0.5
-- C_MMCM1_CLKOUT6_PHASE = 0.0
-- C_MMCM1_CLKOUT0_USE_FINE_PS = false
-- C_MMCM1_CLKOUT1_USE_FINE_PS = false
-- C_MMCM1_CLKOUT2_USE_FINE_PS = false
-- C_MMCM1_CLKOUT3_USE_FINE_PS = false
-- C_MMCM1_CLKOUT4_USE_FINE_PS = false
-- C_MMCM1_CLKOUT5_USE_FINE_PS = false
-- C_MMCM1_CLKOUT6_USE_FINE_PS = false
-- C_MMCM1_COMPENSATION = "ZHOLD"
-- C_MMCM1_DIVCLK_DIVIDE = 1
-- C_MMCM1_REF_JITTER1 = 0.010
-- C_MMCM1_CLKIN1_BUF = false
-- C_MMCM1_CLKFBOUT_BUF = false
-- C_MMCM1_CLKOUT0_BUF = false
-- C_MMCM1_CLKOUT1_BUF = false
-- C_MMCM1_CLKOUT2_BUF = false
-- C_MMCM1_CLKOUT3_BUF = false
-- C_MMCM1_CLKOUT4_BUF = false
-- C_MMCM1_CLKOUT5_BUF = false
-- C_MMCM1_CLKOUT6_BUF = false
-- C_MMCM1_CLOCK_HOLD = false
-- C_MMCM1_STARTUP_WAIT = false
-- C_MMCM1_EXT_RESET_HIGH = 1
-- C_MMCM1_FAMILY = "virtex5"
-- C_MMCM1_CLKIN1_MODULE = NONE
-- C_MMCM1_CLKIN1_PORT = NONE
-- C_MMCM1_CLKFBIN_MODULE = NONE
-- C_MMCM1_CLKFBIN_PORT = NONE
-- C_MMCM1_RST_MODULE = NONE
-- C_MMCM2_BANDWIDTH = "OPTIMIZED"
-- C_MMCM2_CLKFBOUT_MULT_F = 1.0
-- C_MMCM2_CLKFBOUT_PHASE = 0.0
-- C_MMCM2_CLKFBOUT_USE_FINE_PS = false
-- C_MMCM2_CLKIN1_PERIOD = 0.000
-- C_MMCM2_CLKOUT0_DIVIDE_F = 1.0
-- C_MMCM2_CLKOUT0_DUTY_CYCLE = 0.5
-- C_MMCM2_CLKOUT0_PHASE = 0.0
-- C_MMCM2_CLKOUT1_DIVIDE = 1
-- C_MMCM2_CLKOUT1_DUTY_CYCLE = 0.5
-- C_MMCM2_CLKOUT1_PHASE = 0.0
-- C_MMCM2_CLKOUT2_DIVIDE = 1
-- C_MMCM2_CLKOUT2_DUTY_CYCLE = 0.5
-- C_MMCM2_CLKOUT2_PHASE = 0.0
-- C_MMCM2_CLKOUT3_DIVIDE = 1
-- C_MMCM2_CLKOUT3_DUTY_CYCLE = 0.5
-- C_MMCM2_CLKOUT3_PHASE = 0.0
-- C_MMCM2_CLKOUT4_DIVIDE = 1
-- C_MMCM2_CLKOUT4_DUTY_CYCLE = 0.5
-- C_MMCM2_CLKOUT4_PHASE = 0.0
-- C_MMCM2_CLKOUT4_CASCADE = false
-- C_MMCM2_CLKOUT5_DIVIDE = 1
-- C_MMCM2_CLKOUT5_DUTY_CYCLE = 0.5
-- C_MMCM2_CLKOUT5_PHASE = 0.0
-- C_MMCM2_CLKOUT6_DIVIDE = 1
-- C_MMCM2_CLKOUT6_DUTY_CYCLE = 0.5
-- C_MMCM2_CLKOUT6_PHASE = 0.0
-- C_MMCM2_CLKOUT0_USE_FINE_PS = false
-- C_MMCM2_CLKOUT1_USE_FINE_PS = false
-- C_MMCM2_CLKOUT2_USE_FINE_PS = false
-- C_MMCM2_CLKOUT3_USE_FINE_PS = false
-- C_MMCM2_CLKOUT4_USE_FINE_PS = false
-- C_MMCM2_CLKOUT5_USE_FINE_PS = false
-- C_MMCM2_CLKOUT6_USE_FINE_PS = false
-- C_MMCM2_COMPENSATION = "ZHOLD"
-- C_MMCM2_DIVCLK_DIVIDE = 1
-- C_MMCM2_REF_JITTER1 = 0.010
-- C_MMCM2_CLKIN1_BUF = false
-- C_MMCM2_CLKFBOUT_BUF = false
-- C_MMCM2_CLKOUT0_BUF = false
-- C_MMCM2_CLKOUT1_BUF = false
-- C_MMCM2_CLKOUT2_BUF = false
-- C_MMCM2_CLKOUT3_BUF = false
-- C_MMCM2_CLKOUT4_BUF = false
-- C_MMCM2_CLKOUT5_BUF = false
-- C_MMCM2_CLKOUT6_BUF = false
-- C_MMCM2_CLOCK_HOLD = false
-- C_MMCM2_STARTUP_WAIT = false
-- C_MMCM2_EXT_RESET_HIGH = 1
-- C_MMCM2_FAMILY = "virtex5"
-- C_MMCM2_CLKIN1_MODULE = NONE
-- C_MMCM2_CLKIN1_PORT = NONE
-- C_MMCM2_CLKFBIN_MODULE = NONE
-- C_MMCM2_CLKFBIN_PORT = NONE
-- C_MMCM2_RST_MODULE = NONE
-- C_MMCM3_BANDWIDTH = "OPTIMIZED"
-- C_MMCM3_CLKFBOUT_MULT_F = 1.0
-- C_MMCM3_CLKFBOUT_PHASE = 0.0
-- C_MMCM3_CLKFBOUT_USE_FINE_PS = false
-- C_MMCM3_CLKIN1_PERIOD = 0.000
-- C_MMCM3_CLKOUT0_DIVIDE_F = 1.0
-- C_MMCM3_CLKOUT0_DUTY_CYCLE = 0.5
-- C_MMCM3_CLKOUT0_PHASE = 0.0
-- C_MMCM3_CLKOUT1_DIVIDE = 1
-- C_MMCM3_CLKOUT1_DUTY_CYCLE = 0.5
-- C_MMCM3_CLKOUT1_PHASE = 0.0
-- C_MMCM3_CLKOUT2_DIVIDE = 1
-- C_MMCM3_CLKOUT2_DUTY_CYCLE = 0.5
-- C_MMCM3_CLKOUT2_PHASE = 0.0
-- C_MMCM3_CLKOUT3_DIVIDE = 1
-- C_MMCM3_CLKOUT3_DUTY_CYCLE = 0.5
-- C_MMCM3_CLKOUT3_PHASE = 0.0
-- C_MMCM3_CLKOUT4_DIVIDE = 1
-- C_MMCM3_CLKOUT4_DUTY_CYCLE = 0.5
-- C_MMCM3_CLKOUT4_PHASE = 0.0
-- C_MMCM3_CLKOUT4_CASCADE = false
-- C_MMCM3_CLKOUT5_DIVIDE = 1
-- C_MMCM3_CLKOUT5_DUTY_CYCLE = 0.5
-- C_MMCM3_CLKOUT5_PHASE = 0.0
-- C_MMCM3_CLKOUT6_DIVIDE = 1
-- C_MMCM3_CLKOUT6_DUTY_CYCLE = 0.5
-- C_MMCM3_CLKOUT6_PHASE = 0.0
-- C_MMCM3_CLKOUT0_USE_FINE_PS = false
-- C_MMCM3_CLKOUT1_USE_FINE_PS = false
-- C_MMCM3_CLKOUT2_USE_FINE_PS = false
-- C_MMCM3_CLKOUT3_USE_FINE_PS = false
-- C_MMCM3_CLKOUT4_USE_FINE_PS = false
-- C_MMCM3_CLKOUT5_USE_FINE_PS = false
-- C_MMCM3_CLKOUT6_USE_FINE_PS = false
-- C_MMCM3_COMPENSATION = "ZHOLD"
-- C_MMCM3_DIVCLK_DIVIDE = 1
-- C_MMCM3_REF_JITTER1 = 0.010
-- C_MMCM3_CLKIN1_BUF = false
-- C_MMCM3_CLKFBOUT_BUF = false
-- C_MMCM3_CLKOUT0_BUF = false
-- C_MMCM3_CLKOUT1_BUF = false
-- C_MMCM3_CLKOUT2_BUF = false
-- C_MMCM3_CLKOUT3_BUF = false
-- C_MMCM3_CLKOUT4_BUF = false
-- C_MMCM3_CLKOUT5_BUF = false
-- C_MMCM3_CLKOUT6_BUF = false
-- C_MMCM3_CLOCK_HOLD = false
-- C_MMCM3_STARTUP_WAIT = false
-- C_MMCM3_EXT_RESET_HIGH = 1
-- C_MMCM3_FAMILY = "virtex5"
-- C_MMCM3_CLKIN1_MODULE = NONE
-- C_MMCM3_CLKIN1_PORT = NONE
-- C_MMCM3_CLKFBIN_MODULE = NONE
-- C_MMCM3_CLKFBIN_PORT = NONE
-- C_MMCM3_RST_MODULE = NONE
----------------------------------------
-- C_PLLE0_BANDWIDTH = "OPTIMIZED"
-- C_PLLE0_CLKFBOUT_MULT = 1
-- C_PLLE0_CLKFBOUT_PHASE = 0.0
-- C_PLLE0_CLKIN1_PERIOD = 0.000
-- C_PLLE0_CLKOUT0_DIVIDE = 1
-- C_PLLE0_CLKOUT0_DUTY_CYCLE = 0.5
-- C_PLLE0_CLKOUT0_PHASE = 0.0
-- C_PLLE0_CLKOUT1_DIVIDE = 1
-- C_PLLE0_CLKOUT1_DUTY_CYCLE = 0.5
-- C_PLLE0_CLKOUT1_PHASE = 0.0
-- C_PLLE0_CLKOUT2_DIVIDE = 1
-- C_PLLE0_CLKOUT2_DUTY_CYCLE = 0.5
-- C_PLLE0_CLKOUT2_PHASE = 0.0
-- C_PLLE0_CLKOUT3_DIVIDE = 1
-- C_PLLE0_CLKOUT3_DUTY_CYCLE = 0.5
-- C_PLLE0_CLKOUT3_PHASE = 0.0
-- C_PLLE0_CLKOUT4_DIVIDE = 1
-- C_PLLE0_CLKOUT4_DUTY_CYCLE = 0.5
-- C_PLLE0_CLKOUT4_PHASE = 0.0
-- C_PLLE0_CLKOUT5_DIVIDE = 1
-- C_PLLE0_CLKOUT5_DUTY_CYCLE = 0.5
-- C_PLLE0_CLKOUT5_PHASE = 0.0
-- C_PLLE0_COMPENSATION = "ZHOLD"
-- C_PLLE0_DIVCLK_DIVIDE = 1
-- C_PLLE0_REF_JITTER1 = 0.010
-- C_PLLE0_CLKIN1_BUF = false
-- C_PLLE0_CLKFBOUT_BUF = false
-- C_PLLE0_CLKOUT0_BUF = false
-- C_PLLE0_CLKOUT1_BUF = false
-- C_PLLE0_CLKOUT2_BUF = false
-- C_PLLE0_CLKOUT3_BUF = false
-- C_PLLE0_CLKOUT4_BUF = false
-- C_PLLE0_CLKOUT5_BUF = false
-- C_PLLE0_STARTUP_WAIT = "false"
-- C_PLLE0_EXT_RESET_HIGH = 1
-- C_PLLE0_FAMILY = "virtex7"
-- C_PLLE0_CLKIN1_MODULE = NONE
-- C_PLLE0_CLKIN1_PORT = NONE
-- C_PLLE0_CLKFBIN_MODULE = NONE
-- C_PLLE0_CLKFBIN_PORT = NONE
-- C_PLLE0_RST_MODULE = NONE
----------------------------------------
| lgpl-3.0 | da4154dfb7a6d46f267672e4ca07d660 | 0.54357 | 3.007811 | false | false | false | false |
grwlf/vsim | vhdl_ct/ct00556.vhd | 1 | 4,728 | -- NEED RESULT: ARCH00556: Variable declarations - scalar static subtypes passed
-------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
-------------------------------------------------------------------------------
--
-- TEST NAME:
--
-- CT00556
--
-- AUTHOR:
--
-- A. Wilmot
--
-- TEST OBJECTIVES:
--
-- 4.3.1.3 (7)
-- 4.3.1.3 (8)
--
-- DESIGN UNIT ORDERING:
--
-- E00000(ARCH00556)
-- ENT00556_Test_Bench(ARCH00556_Test_Bench)
--
-- REVISION HISTORY:
--
-- 19-AUG-1987 - initial revision
--
-- NOTES:
--
-- self-checking
-- automatically generated
--
use WORK.STANDARD_TYPES.all ;
architecture ARCH00556 of E00000 is
begin
process
variable correct : boolean := true ;
variable va_boolean_1 : boolean
:= c_boolean_1 ;
variable va_bit_1 : bit
:= c_bit_1 ;
variable va_severity_level_1 : severity_level
:= c_severity_level_1 ;
variable va_character_1 : character
:= c_character_1 ;
variable va_t_enum1_1 : t_enum1
:= c_t_enum1_1 ;
variable va_st_enum1_1 : st_enum1
:= c_st_enum1_1 ;
variable va_integer_1 : integer
:= c_integer_1 ;
variable va_t_int1_1 : t_int1
:= c_t_int1_1 ;
variable va_st_int1_1 : st_int1
:= c_st_int1_1 ;
variable va_time_1 : time
:= c_time_1 ;
variable va_t_phys1_1 : t_phys1
:= c_t_phys1_1 ;
variable va_st_phys1_1 : st_phys1
:= c_st_phys1_1 ;
variable va_real_1 : real
:= c_real_1 ;
variable va_t_real1_1 : t_real1
:= c_t_real1_1 ;
variable va_st_real1_1 : st_real1
:= c_st_real1_1 ;
begin
correct := correct and va_boolean_1 = c_boolean_1 ;
correct := correct and va_bit_1 = c_bit_1 ;
correct := correct and va_severity_level_1 = c_severity_level_1 ;
correct := correct and va_character_1 = c_character_1 ;
correct := correct and va_t_enum1_1 = c_t_enum1_1 ;
correct := correct and va_st_enum1_1 = c_st_enum1_1 ;
correct := correct and va_integer_1 = c_integer_1 ;
correct := correct and va_t_int1_1 = c_t_int1_1 ;
correct := correct and va_st_int1_1 = c_st_int1_1 ;
correct := correct and va_time_1 = c_time_1 ;
correct := correct and va_t_phys1_1 = c_t_phys1_1 ;
correct := correct and va_st_phys1_1 = c_st_phys1_1 ;
correct := correct and va_real_1 = c_real_1 ;
correct := correct and va_t_real1_1 = c_t_real1_1 ;
correct := correct and va_st_real1_1 = c_st_real1_1 ;
va_boolean_1 := c_boolean_2 ;
va_bit_1 := c_bit_2 ;
va_severity_level_1 := c_severity_level_2 ;
va_character_1 := c_character_2 ;
va_t_enum1_1 := c_t_enum1_2 ;
va_st_enum1_1 := c_st_enum1_2 ;
va_integer_1 := c_integer_2 ;
va_t_int1_1 := c_t_int1_2 ;
va_st_int1_1 := c_st_int1_2 ;
va_time_1 := c_time_2 ;
va_t_phys1_1 := c_t_phys1_2 ;
va_st_phys1_1 := c_st_phys1_2 ;
va_real_1 := c_real_2 ;
va_t_real1_1 := c_t_real1_2 ;
va_st_real1_1 := c_st_real1_2 ;
correct := correct and va_boolean_1 = c_boolean_2 ;
correct := correct and va_bit_1 = c_bit_2 ;
correct := correct and va_severity_level_1 = c_severity_level_2 ;
correct := correct and va_character_1 = c_character_2 ;
correct := correct and va_t_enum1_1 = c_t_enum1_2 ;
correct := correct and va_st_enum1_1 = c_st_enum1_2 ;
correct := correct and va_integer_1 = c_integer_2 ;
correct := correct and va_t_int1_1 = c_t_int1_2 ;
correct := correct and va_st_int1_1 = c_st_int1_2 ;
correct := correct and va_time_1 = c_time_2 ;
correct := correct and va_t_phys1_1 = c_t_phys1_2 ;
correct := correct and va_st_phys1_1 = c_st_phys1_2 ;
correct := correct and va_real_1 = c_real_2 ;
correct := correct and va_t_real1_1 = c_t_real1_2 ;
correct := correct and va_st_real1_1 = c_st_real1_2 ;
test_report ( "ARCH00556" ,
"Variable declarations - scalar static subtypes" ,
correct) ;
wait ;
end process ;
end ARCH00556 ;
--
entity ENT00556_Test_Bench is
end ENT00556_Test_Bench ;
--
architecture ARCH00556_Test_Bench of ENT00556_Test_Bench is
begin
L1:
block
component UUT
end component ;
for CIS1 : UUT use entity WORK.E00000 ( ARCH00556 ) ;
begin
CIS1 : UUT ;
end block L1 ;
end ARCH00556_Test_Bench ;
| gpl-3.0 | bfdda1ef1a39c721459f0d5b503674ed | 0.532149 | 2.955 | false | true | false | false |
wsoltys/AtomFpga | src/AtomGodilVideo/src/TopRoland.vhd | 1 | 12,707 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 14:42:09 02/09/2013
-- Design Name:
-- Module Name: Top - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.all;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
use IEEE.NUMERIC_STD.all;
use IEEE.STD_LOGIC_UNSIGNED.all;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity TopRoland is
port (
-- Standard 6847 signals
--
-- expept DA which is now input only
-- except nRP which re-purposed as a nWR
DD : inout std_logic_vector (7 downto 0);
DA : in std_logic_vector (12 downto 0);
nMS : in std_logic;
CSS : in std_logic;
nFS : out std_logic;
nWR : in std_logic; -- Was nRP
AG : in std_logic;
GM : in std_logic_vector (2 downto 0);
-- 5 bit VGA Output
R : out std_logic_vector (0 downto 0);
G : out std_logic_vector (1 downto 0);
B : out std_logic_vector (0 downto 0);
HSYNC : out std_logic;
VSYNC : out std_logic;
-- 1 bit AUDIO Output
AUDIO : out std_logic;
-- Other GODIL specific pins
clock49 : in std_logic;
nRST : in std_logic;
nBXXX : in std_logic;
-- Jumpers
-- Enabled SID Audio
SIDEN : in std_logic;
-- Moves SID from 9FE0 to BDC0
nSIDD : in std_logic;
-- Active low version of the SID Select Signal for disabling the external bus buffers
-- nSIDSEL : out std_logic;
-- PS/2 Mouse
PS2_CLK : inout std_logic;
PS2_DATA : inout std_logic;
-- UART
uart_TxD : out std_logic;
uart_RxD : in std_logic
);
end TopRoland;
architecture BEHAVIORAL of TopRoland is
-- clock32 is the main clock
signal clock32 : std_logic;
-- clock25 is a full speed VGA clock
signal clock25 : std_logic;
-- clock15 is just used between two DCMs
signal clock15 : std_logic;
-- Reset signal (active high)
signal reset : std_logic;
-- Reset signal to 6847 (active high), not currently used
signal reset_vid : std_logic;
-- pipelined versions of the address/data/write signals
signal nWR1 : std_logic;
signal nWR2 : std_logic;
signal nMS1 : std_logic;
signal nMS2 : std_logic;
signal nWRMS1 : std_logic;
signal nWRMS2 : std_logic;
signal nBXXX1 : std_logic;
signal nBXXX2 : std_logic;
signal DA1 : std_logic_vector (12 downto 0);
signal DA2 : std_logic_vector (12 downto 0);
signal DD1 : std_logic_vector (7 downto 0);
signal DD2 : std_logic_vector (7 downto 0);
signal DD3 : std_logic_vector (7 downto 0);
signal ram_we : std_logic;
signal addr : std_logic_vector (12 downto 0);
signal din : std_logic_vector (7 downto 0);
-- Dout back to the Atom, that is either VRAM or SID
signal dout : std_logic_vector (7 downto 0);
-- SID sigmals
signal sid_cs : std_logic;
signal sid_we : std_logic;
signal sid_audio : std_logic;
-- UART sigmals
signal uart_cs : std_logic;
signal uart_we : std_logic;
-- Atom extension register signals
signal reg_cs : std_logic;
signal reg_we : std_logic;
signal final_red : std_logic;
signal final_green1 : std_logic;
signal final_green0 : std_logic;
signal final_blue : std_logic;
signal final_vsync : std_logic;
signal final_hsync : std_logic;
signal final_char_a : std_logic_vector (10 downto 0);
component DCM0
port(
CLKIN_IN : in std_logic;
CLK0_OUT : out std_logic;
CLK0_OUT1 : out std_logic;
CLK2X_OUT : out std_logic
);
end component;
component DCMSID0
port(
CLKIN_IN : in std_logic;
CLK0_OUT : out std_logic;
CLK0_OUT1 : out std_logic;
CLK2X_OUT : out std_logic
);
end component;
component DCMSID1
port(
CLKIN_IN : in std_logic;
CLK0_OUT : out std_logic;
CLK0_OUT1 : out std_logic;
CLK2X_OUT : out std_logic
);
end component;
component AtomGodilVideo
generic (
CImplGraphicsExt : boolean;
CImplSoftChar : boolean;
CImplSID : boolean;
CImplVGA80x40 : boolean;
CImplHWScrolling : boolean;
CImplMouse : boolean;
CImplUart : boolean;
MainClockSpeed : integer;
DefaultBaud : integer
);
port (
-- clock_vga is a full speed VGA clock (25MHz ish)
clock_vga : in std_logic;
-- clock_main is the main clock
clock_main : in std_logic;
-- A fixed 32MHz clock for the SID
clock_sid_32MHz : in std_logic;
-- As fast a clock as possible for the SID DAC
clock_sid_dac : in std_logic;
-- Reset signal (active high)
reset : in std_logic;
-- Reset signal to 6847 (active high), not currently used
reset_vid : in std_logic;
-- Main Address / Data Bus
din : in std_logic_vector (7 downto 0);
dout : out std_logic_vector (7 downto 0);
addr : in std_logic_vector (12 downto 0);
-- 6847 Control Signals
CSS : in std_logic;
AG : in std_logic;
GM : in std_logic_vector (2 downto 0);
nFS : out std_logic;
-- RAM signals
ram_we : in std_logic;
-- SID signals
reg_cs : in std_logic;
reg_we : in std_logic;
-- SID signals
sid_cs : in std_logic;
sid_we : in std_logic;
sid_audio : out std_logic;
-- PS/2 Mouse
PS2_CLK : inout std_logic;
PS2_DATA : inout std_logic;
-- UART signals
uart_cs : in std_logic;
uart_we : in std_logic;
uart_RxD : in std_logic;
uart_TxD : out std_logic;
uart_escape : out std_logic;
uart_break : out std_logic;
-- VGA Signals
final_red : out std_logic;
final_green1 : out std_logic;
final_green0 : out std_logic;
final_blue : out std_logic;
final_vsync : out std_logic;
final_hsync : out std_logic
);
end component;
begin
reset <= not nRST;
reset_vid <= '0';
-- Currently set at 49.152 * 8 / 31 = 12.684MHz
-- half VGA should be 25.175 / 2 = 12. 5875
-- we could get closer with to cascaded multipliers
Inst_DCM0 : DCM0
port map (
CLKIN_IN => clock49,
CLK0_OUT => clock25,
CLK0_OUT1 => open,
CLK2X_OUT => open
);
Inst_DCMSID0 : DCMSID0
port map (
CLKIN_IN => clock49,
CLK0_OUT => clock15,
CLK0_OUT1 => open,
CLK2X_OUT => open
);
Inst_DCMSID1 : DCMSID1
port map (
CLKIN_IN => clock15,
CLK0_OUT => clock32,
CLK0_OUT1 => open,
CLK2X_OUT => open
);
Inst_AtomGodilVideo : AtomGodilVideo
generic map (
CImplGraphicsExt => true,
CImplSoftChar => true,
CImplSID => true,
CImplVGA80x40 => true,
CImplHWScrolling => true,
CImplMouse => true,
CImplUart => true,
MainClockSpeed => 32000000,
DefaultBaud => 115200
)
port map (
clock_vga => clock25,
clock_main => clock32,
clock_sid_32Mhz => clock32,
clock_sid_dac => clock49,
reset => reset,
reset_vid => reset_vid,
din => din,
dout => dout,
addr => addr,
CSS => CSS,
AG => AG,
GM => GM,
nFS => nFS,
ram_we => ram_we,
reg_cs => reg_cs,
reg_we => reg_we,
sid_cs => sid_cs,
sid_we => sid_we,
sid_audio => sid_audio,
PS2_CLK => PS2_CLK,
PS2_DATA => PS2_DATA,
uart_cs => uart_cs,
uart_we => uart_we,
uart_RxD => uart_RxD,
uart_TxD => uart_TxD,
uart_escape => open,
uart_break => open,
final_red => final_red,
final_green1 => final_green1,
final_green0 => final_green0,
final_blue => final_blue,
final_vsync => final_vsync,
final_hsync => final_hsync
);
-- Pipelined version of address/data/write signals
process (clock32)
begin
if rising_edge(clock32) then
nBXXX2 <= nBXXX1;
nBXXX1 <= nBXXX;
nMS2 <= nMS1;
nMS1 <= nMS;
nWRMS2 <= nWRMS1;
nWRMS1 <= nWR or nMS;
nWR2 <= nWR1;
nWR1 <= nWR;
DD3 <= DD2;
DD2 <= DD1;
DD1 <= DD;
DA2 <= DA1;
DA1 <= DA;
end if;
end process;
-- Signals driving the VRAM
-- Write just before the rising edge of nWR
ram_we <= '1' when (nWRMS1 = '1' and nWRMS2 = '0' and nBXXX2 = '1') else '0';
din <= DD3;
addr <= DA2;
-- Signals driving the internal registers
-- When nSIDD=0 the registers are mapped to BDE0-BDFF
-- When nSIDD=1 the registers are mapped to 9FE0-9FFF
reg_cs <= '1' when (nSIDD = '1' and nMS2 = '0' and DA2(12 downto 5) = "11111111") or
(nSIDD = '0' and nBXXX2 = '0' and DA2(11 downto 5) = "1101111")
else '0';
reg_we <= '1' when (nSIDD = '1' and nWRMS1 = '1' and nWRMS2 = '0') or
(nSIDD = '0' and nWR1 = '1' and nWR2 = '0')
else '0';
-- Signals driving the SID
-- When nSIDD=0 the SID is mapped to BDC0-BDDF
-- When nSIDD=1 the SID is mapped to 9FC0-9FDF
sid_cs <= '1' when (nSIDD = '1' and nMS2 = '0' and DA2(12 downto 5) = "11111110") or
(nSIDD = '0' and nBXXX2 = '0' and DA2(11 downto 5) = "1101110")
else '0';
sid_we <= '1' when (nSIDD = '1' and nWRMS1 = '1' and nWRMS2 = '0') or
(nSIDD = '0' and nWR1 = '1' and nWR2 = '0')
else '0';
-- Signals driving the UART
-- When nSIDD=0 the UART is mapped to BDB0-BDBF
-- When nSIDD=1 the UART is mapped to 9FB0-9FBF
uart_cs <= '1' when (nSIDD = '1' and nMS2 = '0' and DA2(12 downto 4) = "111111011") or
(nSIDD = '0' and nBXXX2 = '0' and DA2(11 downto 4) = "11011011")
else '0';
uart_we <= '1' when (nSIDD = '1' and nWRMS1 = '1' and nWRMS2 = '0') or
(nSIDD = '0' and nWR1 = '1' and nWR2 = '0')
else '0';
AUDIO <= sid_audio when SIDEN = '1' else '0';
-- Output the SID Select Signal so it can be used to disable the bus buffers
-- TODO: this looks incorrect
-- nSIDSEL <= not sid_cs;
-- Tri-state data back to the Atom
DD <= dout when (nMS = '0' and nWR = '1') else (others => 'Z');
-- 1/2/1 Bit RGB Video to GODIL Test Connector
R(0) <= final_red;
G(1) <= final_green1;
G(0) <= final_green0;
B(0) <= final_blue;
VSYNC <= final_vsync;
HSYNC <= final_hsync;
end BEHAVIORAL;
| apache-2.0 | d35b02d51a53b38bce9c77ceeb155d3b | 0.484772 | 3.747272 | false | false | false | false |
KaskMartin/Digiloogika_ALU | ALU_FPGA/PORTER.vhdl | 1 | 1,459 | LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
use ieee.std_logic_arith.all;
-- Helper component to map My IO to FPGA IO-s
entity PORTER is
Port (
JA_P: in std_logic_vector(7 downto 0); --JA port input
JB_P: in std_logic_vector(7 downto 0); --JB port input
JC_P: in std_logic_vector(7 downto 0); --JC port input
-- JD_P: in std_logic_vector(7 downto 0); --JD port input
LED_P: out std_logic_vector(7 downto 0); --LEDs
a : out STD_LOGIC_VECTOR (3 downto 0); --4 bit input
b : out STD_LOGIC_VECTOR (3 downto 0); -- 4 bit input
op : out STD_LOGIC_VECTOR (1 downto 0);
o : in STD_LOGIC_VECTOR (3 downto 0));
end PORTER;
architecture design of PORTER is
signal JA_P_sign, JB_P_sign, JC_P_sign, LED_P_sign: signed(7 downto 0);
signal a_sign, b_sign, o_sign: signed(3 downto 0);
signal op_sign: signed(1 downto 0);
begin
JA_P_sign <= signed(JA_P);
JB_P_sign <= signed(JB_P);
JC_P_sign <= signed(JC_P);
-- JD_P_sign <= signed(JD_P);
o_sign <= signed(o);
--Last 4 bits of JA will be my A-in -signal
a_sign <= JA_P_sign(3 downto 0);
--Last 4 bits of JB will be my B-in -signal
b_sign <= JB_P_sign(3 downto 0);
--Last 4 bits of JC will be my op-in -signal
op_sign <= JC_P_sign(1 downto 0);
--Last 4 LED lights will be controlled by o-out -signal
LED_P_sign <= ("0000" & o_sign);
a <= std_logic_vector(a_sign);
b <= std_logic_vector(b_sign);
op <= std_logic_vector(op_sign);
LED_P <= std_logic_vector(LED_P_sign);
end design; | mit | 323797940431495edae1925a1ba2404a | 0.651131 | 2.591474 | false | false | false | false |
wsoltys/AtomFpga | src/AtomGodilVideo/src/SID/sid_6581.vhd | 1 | 14,159 | -------------------------------------------------------------------------------
--
-- SID 6581
--
-- A fully functional SID chip implementation in VHDL
--
-------------------------------------------------------------------------------
-- to do: - filter
-- - smaller implementation, use multiplexed channels
--
--
-- "The Filter was a classic multi-mode (state variable) VCF design. There was
-- no way to create a variable transconductance amplifier in our NMOS process,
-- so I simply used FETs as voltage-controlled resistors to control the cutoff
-- frequency. An 11-bit D/A converter generates the control voltage for the
-- FETs (it's actually a 12-bit D/A, but the LSB had no audible affect so I
-- disconnected it!)."
-- "Filter resonance was controlled by a 4-bit weighted resistor ladder. Each
-- bit would turn on one of the weighted resistors and allow a portion of the
-- output to feed back to the input. The state-variable design provided
-- simultaneous low-pass, band-pass and high-pass outputs. Analog switches
-- selected which combination of outputs were sent to the final amplifier (a
-- notch filter was created by enabling both the high and low-pass outputs
-- simultaneously)."
-- "The filter is the worst part of SID because I could not create high-gain
-- op-amps in NMOS, which were essential to a resonant filter. In addition,
-- the resistance of the FETs varied considerably with processing, so different
-- lots of SID chips had different cutoff frequency characteristics. I knew it
-- wouldn't work very well, but it was better than nothing and I didn't have
-- time to make it better."
--
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
use IEEE.numeric_std.all;
-------------------------------------------------------------------------------
entity sid6581 is
port (
clk_1MHz : in std_logic; -- main SID clock signal
clk32 : in std_logic; -- main clock signal
clk_DAC : in std_logic; -- DAC clock signal, must be as high as possible for the best results
reset : in std_logic; -- high active signal (reset when reset = '1')
cs : in std_logic; -- "chip select", when this signal is '1' this model can be accessed
we : in std_logic; -- when '1' this model can be written to, otherwise access is considered as read
addr : in std_logic_vector(4 downto 0); -- address lines
di : in std_logic_vector(7 downto 0); -- data in (to chip)
do : out std_logic_vector(7 downto 0); -- data out (from chip)
pot_x : in std_logic; -- paddle input-X
pot_y : in std_logic; -- paddle input-Y
audio_out : out std_logic; -- this line holds the audio-signal in PWM format
audio_data : out std_logic_vector(17 downto 0)
);
end sid6581;
architecture Behavioral of sid6581 is
signal Voice_1_Freq_lo : std_logic_vector(7 downto 0) := (others => '0');
signal Voice_1_Freq_hi : std_logic_vector(7 downto 0) := (others => '0');
signal Voice_1_Pw_lo : std_logic_vector(7 downto 0) := (others => '0');
signal Voice_1_Pw_hi : std_logic_vector(3 downto 0) := (others => '0');
signal Voice_1_Control : std_logic_vector(7 downto 0) := (others => '0');
signal Voice_1_Att_dec : std_logic_vector(7 downto 0) := (others => '0');
signal Voice_1_Sus_Rel : std_logic_vector(7 downto 0) := (others => '0');
signal Voice_1_Osc : std_logic_vector(7 downto 0) := (others => '0');
signal Voice_1_Env : std_logic_vector(7 downto 0) := (others => '0');
signal Voice_2_Freq_lo : std_logic_vector(7 downto 0) := (others => '0');
signal Voice_2_Freq_hi : std_logic_vector(7 downto 0) := (others => '0');
signal Voice_2_Pw_lo : std_logic_vector(7 downto 0) := (others => '0');
signal Voice_2_Pw_hi : std_logic_vector(3 downto 0) := (others => '0');
signal Voice_2_Control : std_logic_vector(7 downto 0) := (others => '0');
signal Voice_2_Att_dec : std_logic_vector(7 downto 0) := (others => '0');
signal Voice_2_Sus_Rel : std_logic_vector(7 downto 0) := (others => '0');
signal Voice_2_Osc : std_logic_vector(7 downto 0) := (others => '0');
signal Voice_2_Env : std_logic_vector(7 downto 0) := (others => '0');
signal Voice_3_Freq_lo : std_logic_vector(7 downto 0) := (others => '0');
signal Voice_3_Freq_hi : std_logic_vector(7 downto 0) := (others => '0');
signal Voice_3_Pw_lo : std_logic_vector(7 downto 0) := (others => '0');
signal Voice_3_Pw_hi : std_logic_vector(3 downto 0) := (others => '0');
signal Voice_3_Control : std_logic_vector(7 downto 0) := (others => '0');
signal Voice_3_Att_dec : std_logic_vector(7 downto 0) := (others => '0');
signal Voice_3_Sus_Rel : std_logic_vector(7 downto 0) := (others => '0');
signal Filter_Fc_lo : std_logic_vector(7 downto 0) := (others => '0');
signal Filter_Fc_hi : std_logic_vector(7 downto 0) := (others => '0');
signal Filter_Res_Filt : std_logic_vector(7 downto 0) := (others => '0');
signal Filter_Mode_Vol : std_logic_vector(7 downto 0) := (others => '0');
signal Misc_PotX : std_logic_vector(7 downto 0) := (others => '0');
signal Misc_PotY : std_logic_vector(7 downto 0) := (others => '0');
signal Misc_Osc3_Random : std_logic_vector(7 downto 0) := (others => '0');
signal Misc_Env3 : std_logic_vector(7 downto 0) := (others => '0');
signal do_buf : std_logic_vector(7 downto 0) := (others => '0');
signal voice_1 : std_logic_vector(11 downto 0) := (others => '0');
signal voice_2 : std_logic_vector(11 downto 0) := (others => '0');
signal voice_3 : std_logic_vector(11 downto 0) := (others => '0');
signal voice_mixed : std_logic_vector(13 downto 0) := (others => '0');
signal voice_volume : std_logic_vector(35 downto 0) := (others => '0');
signal divide_0 : std_logic_vector(31 downto 0) := (others => '0');
signal voice_1_PA_MSB : std_logic := '0';
signal voice_2_PA_MSB : std_logic := '0';
signal voice_3_PA_MSB : std_logic := '0';
signal voice1_signed : signed(12 downto 0);
signal voice2_signed : signed(12 downto 0);
signal voice3_signed : signed(12 downto 0);
constant ext_in_signed : signed(12 downto 0) := to_signed(0,13);
signal filtered_audio : signed(18 downto 0);
signal tick_q1, tick_q2 : std_logic;
signal input_valid : std_logic;
signal unsigned_audio : std_logic_vector(17 downto 0);
signal unsigned_filt : std_logic_vector(18 downto 0);
signal ff1 : std_logic;
-------------------------------------------------------------------------------
begin
digital_to_analog: entity work.pwm_sddac
port map(
clk_i => clk_DAC,
reset => reset,
dac_i => unsigned_audio(17 downto 8),
dac_o => audio_out
);
paddle_x: entity work.pwm_sdadc
port map (
clk => clk_1MHz,
reset => reset,
ADC_out => Misc_PotX,
ADC_in => pot_x
);
paddle_y: entity work.pwm_sdadc
port map (
clk => clk_1MHz,
reset => reset,
ADC_out => Misc_PotY,
ADC_in => pot_y
);
sid_voice_1: entity work.sid_voice
port map(
clk_1MHz => clk_1MHz,
reset => reset,
Freq_lo => Voice_1_Freq_lo,
Freq_hi => Voice_1_Freq_hi,
Pw_lo => Voice_1_Pw_lo,
Pw_hi => Voice_1_Pw_hi,
Control => Voice_1_Control,
Att_dec => Voice_1_Att_dec,
Sus_Rel => Voice_1_Sus_Rel,
PA_MSB_in => voice_3_PA_MSB,
PA_MSB_out => voice_1_PA_MSB,
Osc => Voice_1_Osc,
Env => Voice_1_Env,
voice => voice_1
);
sid_voice_2: entity work.sid_voice
port map(
clk_1MHz => clk_1MHz,
reset => reset,
Freq_lo => Voice_2_Freq_lo,
Freq_hi => Voice_2_Freq_hi,
Pw_lo => Voice_2_Pw_lo,
Pw_hi => Voice_2_Pw_hi,
Control => Voice_2_Control,
Att_dec => Voice_2_Att_dec,
Sus_Rel => Voice_2_Sus_Rel,
PA_MSB_in => voice_1_PA_MSB,
PA_MSB_out => voice_2_PA_MSB,
Osc => Voice_2_Osc,
Env => Voice_2_Env,
voice => voice_2
);
sid_voice_3: entity work.sid_voice
port map(
clk_1MHz => clk_1MHz,
reset => reset,
Freq_lo => Voice_3_Freq_lo,
Freq_hi => Voice_3_Freq_hi,
Pw_lo => Voice_3_Pw_lo,
Pw_hi => Voice_3_Pw_hi,
Control => Voice_3_Control,
Att_dec => Voice_3_Att_dec,
Sus_Rel => Voice_3_Sus_Rel,
PA_MSB_in => voice_2_PA_MSB,
PA_MSB_out => voice_3_PA_MSB,
Osc => Misc_Osc3_Random,
Env => Misc_Env3,
voice => voice_3
);
-------------------------------------------------------------------------------------
do <= do_buf;
-- SID filters
process (clk_1MHz,reset)
begin
if reset='1' then
ff1<='0';
else
if rising_edge(clk_1MHz) then
ff1<=not ff1;
end if;
end if;
end process;
process(clk32)
begin
if rising_edge(clk32) then
tick_q1 <= ff1;
tick_q2 <= tick_q1;
end if;
end process;
input_valid <= '1' when tick_q1 /=tick_q2 else '0';
voice1_signed <= signed("0" & voice_1) - 2048;
voice2_signed <= signed("0" & voice_2) - 2048;
voice3_signed <= signed("0" & voice_3) - 2048;
filters: entity work.sid_filters
port map (
clk => clk32,
rst => reset,
-- SID registers.
Fc_lo => Filter_Fc_lo,
Fc_hi => Filter_Fc_hi,
Res_Filt => Filter_Res_Filt,
Mode_Vol => Filter_Mode_Vol,
-- Voices - resampled to 13 bit
voice1 => voice1_signed,
voice2 => voice2_signed,
voice3 => voice3_signed,
--
input_valid => input_valid,
ext_in => ext_in_signed,
sound => filtered_audio,
valid => open
);
unsigned_filt <= std_logic_vector(filtered_audio + "1000000000000000000");
unsigned_audio <= unsigned_filt(18 downto 1);
audio_data <= unsigned_audio;
-- Register decoding
register_decoder:process(clk32)
begin
if rising_edge(clk32) then
if (reset = '1') then
--------------------------------------- Voice-1
Voice_1_Freq_lo <= (others => '0');
Voice_1_Freq_hi <= (others => '0');
Voice_1_Pw_lo <= (others => '0');
Voice_1_Pw_hi <= (others => '0');
Voice_1_Control <= (others => '0');
Voice_1_Att_dec <= (others => '0');
Voice_1_Sus_Rel <= (others => '0');
--------------------------------------- Voice-2
Voice_2_Freq_lo <= (others => '0');
Voice_2_Freq_hi <= (others => '0');
Voice_2_Pw_lo <= (others => '0');
Voice_2_Pw_hi <= (others => '0');
Voice_2_Control <= (others => '0');
Voice_2_Att_dec <= (others => '0');
Voice_2_Sus_Rel <= (others => '0');
--------------------------------------- Voice-3
Voice_3_Freq_lo <= (others => '0');
Voice_3_Freq_hi <= (others => '0');
Voice_3_Pw_lo <= (others => '0');
Voice_3_Pw_hi <= (others => '0');
Voice_3_Control <= (others => '0');
Voice_3_Att_dec <= (others => '0');
Voice_3_Sus_Rel <= (others => '0');
--------------------------------------- Filter & volume
Filter_Fc_lo <= (others => '0');
Filter_Fc_hi <= (others => '0');
Filter_Res_Filt <= (others => '0');
Filter_Mode_Vol <= (others => '0');
else
Voice_1_Freq_lo <= Voice_1_Freq_lo;
Voice_1_Freq_hi <= Voice_1_Freq_hi;
Voice_1_Pw_lo <= Voice_1_Pw_lo;
Voice_1_Pw_hi <= Voice_1_Pw_hi;
Voice_1_Control <= Voice_1_Control;
Voice_1_Att_dec <= Voice_1_Att_dec;
Voice_1_Sus_Rel <= Voice_1_Sus_Rel;
Voice_2_Freq_lo <= Voice_2_Freq_lo;
Voice_2_Freq_hi <= Voice_2_Freq_hi;
Voice_2_Pw_lo <= Voice_2_Pw_lo;
Voice_2_Pw_hi <= Voice_2_Pw_hi;
Voice_2_Control <= Voice_2_Control;
Voice_2_Att_dec <= Voice_2_Att_dec;
Voice_2_Sus_Rel <= Voice_2_Sus_Rel;
Voice_3_Freq_lo <= Voice_3_Freq_lo;
Voice_3_Freq_hi <= Voice_3_Freq_hi;
Voice_3_Pw_lo <= Voice_3_Pw_lo;
Voice_3_Pw_hi <= Voice_3_Pw_hi;
Voice_3_Control <= Voice_3_Control;
Voice_3_Att_dec <= Voice_3_Att_dec;
Voice_3_Sus_Rel <= Voice_3_Sus_Rel;
Filter_Fc_lo <= Filter_Fc_lo;
Filter_Fc_hi <= Filter_Fc_hi;
Filter_Res_Filt <= Filter_Res_Filt;
Filter_Mode_Vol <= Filter_Mode_Vol;
do_buf <= (others => '0');
if (cs='1') then
if (we='1') then -- Write to SID-register
------------------------
case addr is
-------------------------------------- Voice-1
when "00000" => Voice_1_Freq_lo <= di;
when "00001" => Voice_1_Freq_hi <= di;
when "00010" => Voice_1_Pw_lo <= di;
when "00011" => Voice_1_Pw_hi <= di(3 downto 0);
when "00100" => Voice_1_Control <= di;
when "00101" => Voice_1_Att_dec <= di;
when "00110" => Voice_1_Sus_Rel <= di;
--------------------------------------- Voice-2
when "00111" => Voice_2_Freq_lo <= di;
when "01000" => Voice_2_Freq_hi <= di;
when "01001" => Voice_2_Pw_lo <= di;
when "01010" => Voice_2_Pw_hi <= di(3 downto 0);
when "01011" => Voice_2_Control <= di;
when "01100" => Voice_2_Att_dec <= di;
when "01101" => Voice_2_Sus_Rel <= di;
--------------------------------------- Voice-3
when "01110" => Voice_3_Freq_lo <= di;
when "01111" => Voice_3_Freq_hi <= di;
when "10000" => Voice_3_Pw_lo <= di;
when "10001" => Voice_3_Pw_hi <= di(3 downto 0);
when "10010" => Voice_3_Control <= di;
when "10011" => Voice_3_Att_dec <= di;
when "10100" => Voice_3_Sus_Rel <= di;
--------------------------------------- Filter & volume
when "10101" => Filter_Fc_lo <= di;
when "10110" => Filter_Fc_hi <= di;
when "10111" => Filter_Res_Filt <= di;
when "11000" => Filter_Mode_Vol <= di;
--------------------------------------
when others => null;
end case;
else -- Read from SID-register
-------------------------
--case CONV_INTEGER(addr) is
case addr is
-------------------------------------- Misc
when "11001" => do_buf <= Misc_PotX;
when "11010" => do_buf <= Misc_PotY;
when "11011" => do_buf <= Misc_Osc3_Random;
when "11100" => do_buf <= Misc_Env3;
--------------------------------------
-- when others => null;
when others => do_buf <= (others => '0');
end case;
end if;
end if;
end if;
end if;
end process;
end Behavioral;
| apache-2.0 | 3280eea0d39ceaaef732469c60cadaaa | 0.553358 | 2.719224 | false | false | false | false |
grwlf/vsim | vhdl_ct/ct00232.vhd | 1 | 9,535 | -- NEED RESULT: ENT00232.P00232: Associated composite out ports with static subtypes passed
-- NEED RESULT: ENT00232: Associated composite out ports with static subtypes passed
-- NEED RESULT: ENT00232.P00232: Associated composite out ports with static subtypes passed
-------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
-------------------------------------------------------------------------------
--
-- TEST NAME:
--
-- CT00232
--
-- AUTHOR:
--
-- A. Wilmot
--
-- TEST OBJECTIVES:
--
-- 1.1.1.2 (4)
-- 1.1.1.2 (7)
--
-- DESIGN UNIT ORDERING:
--
-- ENT00232(ARCH00232)
-- ENT00232_Test_Bench(ARCH00232_Test_Bench)
--
-- REVISION HISTORY:
--
-- 25-JUN-1987 - initial revision
--
-- NOTES:
--
-- self-checking
-- automatically generated
--
use WORK.STANDARD_TYPES.all ;
entity ENT00232 is
port (
toggle : out switch := down;
i_bit_vector_1, i_bit_vector_2 : out bit_vector
:= c_st_bit_vector_1
;
i_string_1, i_string_2 : out string
:= c_st_string_1
;
i_t_rec1_1, i_t_rec1_2 : out t_rec1
:= c_st_rec1_1
;
i_st_rec1_1, i_st_rec1_2 : out st_rec1
:= c_st_rec1_1
;
i_t_rec2_1, i_t_rec2_2 : out t_rec2
:= c_st_rec2_1
;
i_st_rec2_1, i_st_rec2_2 : out st_rec2
:= c_st_rec2_1
;
i_t_rec3_1, i_t_rec3_2 : out t_rec3
:= c_st_rec3_1
;
i_st_rec3_1, i_st_rec3_2 : out st_rec3
:= c_st_rec3_1
;
i_t_arr1_1, i_t_arr1_2 : out t_arr1
:= c_st_arr1_1
;
i_st_arr1_1, i_st_arr1_2 : out st_arr1
:= c_st_arr1_1
;
i_t_arr2_1, i_t_arr2_2 : out t_arr2
:= c_st_arr2_1
;
i_st_arr2_1, i_st_arr2_2 : out st_arr2
:= c_st_arr2_1
;
i_t_arr3_1, i_t_arr3_2 : out t_arr3
:= c_st_arr3_1
;
i_st_arr3_1, i_st_arr3_2 : out st_arr3
:= c_st_arr3_1
) ;
begin
end ENT00232 ;
--
architecture ARCH00232 of ENT00232 is
begin
process
variable correct : boolean := true ;
begin
test_report ( "ENT00232" ,
"Associated composite out ports with static subtypes" ,
correct) ;
--
toggle <= up ;
i_bit_vector_1 <= c_st_bit_vector_2 ;
i_bit_vector_2 <= c_st_bit_vector_2 ;
i_string_1 <= c_st_string_2 ;
i_string_2 <= c_st_string_2 ;
i_t_rec1_1 <= c_st_rec1_2 ;
i_t_rec1_2 <= c_st_rec1_2 ;
i_st_rec1_1 <= c_st_rec1_2 ;
i_st_rec1_2 <= c_st_rec1_2 ;
i_t_rec2_1 <= c_st_rec2_2 ;
i_t_rec2_2 <= c_st_rec2_2 ;
i_st_rec2_1 <= c_st_rec2_2 ;
i_st_rec2_2 <= c_st_rec2_2 ;
i_t_rec3_1 <= c_st_rec3_2 ;
i_t_rec3_2 <= c_st_rec3_2 ;
i_st_rec3_1 <= c_st_rec3_2 ;
i_st_rec3_2 <= c_st_rec3_2 ;
i_t_arr1_1 <= c_st_arr1_2 ;
i_t_arr1_2 <= c_st_arr1_2 ;
i_st_arr1_1 <= c_st_arr1_2 ;
i_st_arr1_2 <= c_st_arr1_2 ;
i_t_arr2_1 <= c_st_arr2_2 ;
i_t_arr2_2 <= c_st_arr2_2 ;
i_st_arr2_1 <= c_st_arr2_2 ;
i_st_arr2_2 <= c_st_arr2_2 ;
i_t_arr3_1 <= c_st_arr3_2 ;
i_t_arr3_2 <= c_st_arr3_2 ;
i_st_arr3_1 <= c_st_arr3_2 ;
i_st_arr3_2 <= c_st_arr3_2 ;
wait ;
end process ;
end ARCH00232 ;
--
use WORK.STANDARD_TYPES.all ;
entity ENT00232_Test_Bench is
end ENT00232_Test_Bench ;
--
architecture ARCH00232_Test_Bench of ENT00232_Test_Bench is
begin
L1:
block
signal i_bit_vector_1, i_bit_vector_2 : st_bit_vector
:= c_st_bit_vector_1 ;
signal i_string_1, i_string_2 : st_string
:= c_st_string_1 ;
signal i_t_rec1_1, i_t_rec1_2 : st_rec1
:= c_st_rec1_1 ;
signal i_st_rec1_1, i_st_rec1_2 : st_rec1
:= c_st_rec1_1 ;
signal i_t_rec2_1, i_t_rec2_2 : st_rec2
:= c_st_rec2_1 ;
signal i_st_rec2_1, i_st_rec2_2 : st_rec2
:= c_st_rec2_1 ;
signal i_t_rec3_1, i_t_rec3_2 : st_rec3
:= c_st_rec3_1 ;
signal i_st_rec3_1, i_st_rec3_2 : st_rec3
:= c_st_rec3_1 ;
signal i_t_arr1_1, i_t_arr1_2 : st_arr1
:= c_st_arr1_1 ;
signal i_st_arr1_1, i_st_arr1_2 : st_arr1
:= c_st_arr1_1 ;
signal i_t_arr2_1, i_t_arr2_2 : st_arr2
:= c_st_arr2_1 ;
signal i_st_arr2_1, i_st_arr2_2 : st_arr2
:= c_st_arr2_1 ;
signal i_t_arr3_1, i_t_arr3_2 : st_arr3
:= c_st_arr3_1 ;
signal i_st_arr3_1, i_st_arr3_2 : st_arr3
:= c_st_arr3_1 ;
--
component UUT
port (
toggle : out switch ;
i_bit_vector_1, i_bit_vector_2 : out bit_vector
:= c_st_bit_vector_1
;
i_string_1, i_string_2 : out string
:= c_st_string_1
;
i_t_rec1_1, i_t_rec1_2 : out t_rec1
:= c_st_rec1_1
;
i_st_rec1_1, i_st_rec1_2 : out st_rec1
:= c_st_rec1_1
;
i_t_rec2_1, i_t_rec2_2 : out t_rec2
:= c_st_rec2_1
;
i_st_rec2_1, i_st_rec2_2 : out st_rec2
:= c_st_rec2_1
;
i_t_rec3_1, i_t_rec3_2 : out t_rec3
:= c_st_rec3_1
;
i_st_rec3_1, i_st_rec3_2 : out st_rec3
:= c_st_rec3_1
;
i_t_arr1_1, i_t_arr1_2 : out t_arr1
:= c_st_arr1_1
;
i_st_arr1_1, i_st_arr1_2 : out st_arr1
:= c_st_arr1_1
;
i_t_arr2_1, i_t_arr2_2 : out t_arr2
:= c_st_arr2_1
;
i_st_arr2_1, i_st_arr2_2 : out st_arr2
:= c_st_arr2_1
;
i_t_arr3_1, i_t_arr3_2 : out t_arr3
:= c_st_arr3_1
;
i_st_arr3_1, i_st_arr3_2 : out st_arr3
:= c_st_arr3_1
) ;
end component ;
--
for CIS1 : UUT use entity WORK.ENT00232 ( ARCH00232 ) ;
--
begin
CIS1 : UUT
port map (
toggle ,
i_bit_vector_1, i_bit_vector_2,
i_string_1, i_string_2,
i_t_rec1_1, i_t_rec1_2,
i_st_rec1_1, i_st_rec1_2,
i_t_rec2_1, i_t_rec2_2,
i_st_rec2_1, i_st_rec2_2,
i_t_rec3_1, i_t_rec3_2,
i_st_rec3_1, i_st_rec3_2,
i_t_arr1_1, i_t_arr1_2,
i_st_arr1_1, i_st_arr1_2,
i_t_arr2_1, i_t_arr2_2,
i_st_arr2_1, i_st_arr2_2,
i_t_arr3_1, i_t_arr3_2,
i_st_arr3_1, i_st_arr3_2
) ;
P00232 :
process ( toggle )
variable correct : boolean := true ;
begin
if toggle = up then
correct := correct and i_bit_vector_1 = c_st_bit_vector_2
and i_bit_vector_2 = c_st_bit_vector_2 ;
correct := correct and i_string_1 = c_st_string_2
and i_string_2 = c_st_string_2 ;
correct := correct and i_t_rec1_1 = c_st_rec1_2
and i_t_rec1_2 = c_st_rec1_2 ;
correct := correct and i_st_rec1_1 = c_st_rec1_2
and i_st_rec1_2 = c_st_rec1_2 ;
correct := correct and i_t_rec2_1 = c_st_rec2_2
and i_t_rec2_2 = c_st_rec2_2 ;
correct := correct and i_st_rec2_1 = c_st_rec2_2
and i_st_rec2_2 = c_st_rec2_2 ;
correct := correct and i_t_rec3_1 = c_st_rec3_2
and i_t_rec3_2 = c_st_rec3_2 ;
correct := correct and i_st_rec3_1 = c_st_rec3_2
and i_st_rec3_2 = c_st_rec3_2 ;
correct := correct and i_t_arr1_1 = c_st_arr1_2
and i_t_arr1_2 = c_st_arr1_2 ;
correct := correct and i_st_arr1_1 = c_st_arr1_2
and i_st_arr1_2 = c_st_arr1_2 ;
correct := correct and i_t_arr2_1 = c_st_arr2_2
and i_t_arr2_2 = c_st_arr2_2 ;
correct := correct and i_st_arr2_1 = c_st_arr2_2
and i_st_arr2_2 = c_st_arr2_2 ;
correct := correct and i_t_arr3_1 = c_st_arr3_2
and i_t_arr3_2 = c_st_arr3_2 ;
correct := correct and i_st_arr3_1 = c_st_arr3_2
and i_st_arr3_2 = c_st_arr3_2 ;
end if ;
--
test_report ( "ENT00232.P00232" ,
"Associated composite out ports with static subtypes",
correct) ;
end process P00232 ;
end block L1 ;
end ARCH00232_Test_Bench ;
| gpl-3.0 | 9826cd77accf9b278fb332884ce19ecc | 0.419297 | 2.800294 | false | false | false | false |
grwlf/vsim | vhdl_ct/ct00485.vhd | 1 | 3,024 | -- NEED RESULT: ARCH00485: Function parameters of globally static size passed
-------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
-------------------------------------------------------------------------------
--
-- TEST NAME:
--
-- CT00485
--
-- AUTHOR:
--
-- D. Hyman
--
-- TEST OBJECTIVES:
--
-- 2.1.1 (8)
-- 2.1.1 (10)
--
-- DESIGN UNIT ORDERING:
--
-- GENERIC_STANDARD_TYPES(ARCH00485)
-- ENT00485_Test_Bench(ARCH00485_Test_Bench)
--
-- REVISION HISTORY:
--
-- 7-AUG-1987 - initial revision
--
-- NOTES:
--
-- self-checking
--
--
use WORK.STANDARD_TYPES.test_report ;
architecture ARCH00485 of GENERIC_STANDARD_TYPES is
begin
P :
process
-- this will test 2.1.1 (8)
-- (the various types are in GENERIC_STANDARD_TYPES)
function f_2 ( t_en : t_enum1 ;
st_en : st_enum1 ;
t_in : t_int1 ;
st_in : st_int1 ;
t_ph : t_phys1 ;
st_ph : st_phys1 ;
t_re : t_real1 ;
st_re : st_real1 ) return integer is
variable n : integer := 0 ;
begin
if t_en = en2 then
n := n + 1 ;
end if ;
if st_en = en3 then
n := n + 1 ;
end if ;
if t_in = 10 then
n := n + 1 ;
end if ;
if st_in = 12 then
n := n + 1 ;
end if ;
if t_ph = phys1_3 then
n := n + 1 ;
end if ;
if st_ph = phys1_4 then
n := n + 1 ;
end if ;
if t_re = 10.0 then
n := n + 1 ;
end if ;
if st_re = 12.0 then
n := n + 1 ;
end if ;
return n ;
end f_2 ;
-- this will test 2.1.1 (10)
-- (the various types are in GENERIC_STANDARD_TYPES)
function f_3 ( t_ar : t_arr1 ;
st_ar : st_arr1 ;
t_r1 : t_rec1 ;
t_r3 : t_rec3 ) return integer is
variable n : integer := 0 ;
begin
if t_ar(2) = c_st_int1_1 then
n := n + 1 ;
end if ;
if st_ar(2) = c_st_int1_2 then
n := n + 1 ;
end if ;
if t_r1.f2 = c_time_1 then
n := n + 1 ;
end if ;
if t_r3.f1 = c_boolean_1 then
n := n + 1 ;
end if ;
return n ;
end f_3 ;
begin
test_report ( "ARCH00485" ,
"Function parameters of globally static size" ,
(f_2(en2, en3, 10, 12, phys1_3, phys1_4, 10.0, 12.0) = 8) and
(f_3(c_st_arr1_1, c_st_arr1_2, c_t_rec1_1, c_t_rec3_1) = 4)
) ;
wait ;
end process P ;
end ARCH00485 ;
entity ENT00485_Test_Bench is
end ENT00485_Test_Bench ;
architecture ARCH00485_Test_Bench of ENT00485_Test_Bench is
begin
L1:
block
component UUT
end component ;
for CIS1 : UUT use entity WORK.GENERIC_STANDARD_TYPES ( ARCH00485 ) ;
begin
CIS1 : UUT ;
end block L1 ;
end ARCH00485_Test_Bench ;
| gpl-3.0 | cc9e36fd3cc6e4e60420ad1138185556 | 0.458333 | 3.07943 | false | true | false | false |
grwlf/vsim | vhdl_ct/ct00626.vhd | 1 | 6,148 | -- NEED RESULT: ARCH00626: Concurrent proc call 1 passed
-- NEED RESULT: ARCH00626.P1: Multi transport transactions occurred on concurrent signal asg passed
-- NEED RESULT: ARCH00626: Concurrent proc call 2 passed
-- NEED RESULT: ARCH00626: One transport transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00626: Old transactions were removed on a concurrent signal asg passed
-- NEED RESULT: P1: Transport transactions completed entirely passed
-------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
-------------------------------------------------------------------------------
--
-- TEST NAME:
--
-- CT00626
--
-- AUTHOR:
--
-- G. Tominovich
--
-- TEST OBJECTIVES:
--
-- 9.3 (3)
--
-- DESIGN UNIT ORDERING:
--
-- ENT00626(ARCH00626)
-- ENT00626_Test_Bench(ARCH00626_Test_Bench)
--
-- REVISION HISTORY:
--
-- 24-AUG-1987 - initial revision
--
-- NOTES:
--
-- self-checking
-- automatically generated
--
use WORK.STANDARD_TYPES.all ;
entity ENT00626 is
port (
s_st_rec3 : inout st_rec3
) ;
subtype chk_sig_type is integer range -1 to 100 ;
signal chk_st_rec3 : chk_sig_type := -1 ;
--
end ENT00626 ;
--
--
architecture ARCH00626 of ENT00626 is
subtype chk_time_type is Time ;
signal s_st_rec3_savt : chk_time_type := 0 ns ;
--
subtype chk_cnt_type is Integer ;
signal s_st_rec3_cnt : chk_cnt_type := 0 ;
--
type select_type is range 1 to 3 ;
signal st_rec3_select : select_type := 1 ;
--
procedure P1
(signal s_st_rec3 : in st_rec3 ;
signal select_sig : out Select_Type ;
signal savtime : out Chk_Time_Type ;
signal chk_sig : out Chk_Sig_Type ;
signal count : out Integer)
is
variable correct : boolean ;
begin
case s_st_rec3_cnt is
when 0
=> null ;
-- s_st_rec3.f3(lowb,true) <= transport
-- c_st_rec3_2.f3(lowb,true) after 10 ns,
-- c_st_rec3_1.f3(lowb,true) after 20 ns ;
--
when 1
=> correct :=
s_st_rec3.f3(lowb,true) =
c_st_rec3_2.f3(lowb,true) and
(s_st_rec3_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00626" ,
"Concurrent proc call 1",
correct ) ;
--
when 2
=> correct :=
s_st_rec3.f3(lowb,true) =
c_st_rec3_1.f3(lowb,true) and
(s_st_rec3_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00626.P1" ,
"Multi transport transactions occurred on " &
"concurrent signal asg",
correct ) ;
--
select_sig <= transport 2 ;
-- s_st_rec3.f3(lowb,true) <= transport
-- c_st_rec3_2.f3(lowb,true) after 10 ns ,
-- c_st_rec3_1.f3(lowb,true) after 20 ns ,
-- c_st_rec3_2.f3(lowb,true) after 30 ns ,
-- c_st_rec3_1.f3(lowb,true) after 40 ns ;
--
when 3
=> correct :=
s_st_rec3.f3(lowb,true) =
c_st_rec3_2.f3(lowb,true) and
(s_st_rec3_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00626" ,
"Concurrent proc call 2",
correct ) ;
select_sig <= transport 3 ;
-- s_st_rec3.f3(lowb,true) <= transport
-- c_st_rec3_1.f3(lowb,true) after 5 ns ;
--
when 4
=> correct :=
s_st_rec3.f3(lowb,true) =
c_st_rec3_1.f3(lowb,true) and
(s_st_rec3_savt + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00626" ,
"One transport transaction occurred on a " &
"concurrent signal asg",
correct ) ;
test_report ( "ARCH00626" ,
"Old transactions were removed on a " &
"concurrent signal asg",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00626" ,
"Old transactions were removed on a " &
"concurrent signal asg",
false ) ;
--
end case ;
--
savtime <= transport Std.Standard.Now ;
chk_sig <= transport s_st_rec3_cnt
after (1 us - Std.Standard.Now) ;
count <= transport s_st_rec3_cnt + 1 ;
--
end ;
--
begin
CHG1 :
P1(
s_st_rec3 ,
st_rec3_select ,
s_st_rec3_savt ,
chk_st_rec3 ,
s_st_rec3_cnt ) ;
--
PGEN_CHKP_1 :
process ( chk_st_rec3 )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P1" ,
"Transport transactions completed entirely",
chk_st_rec3 = 4 ) ;
end if ;
end process PGEN_CHKP_1 ;
--
--
with st_rec3_select select
s_st_rec3.f3(lowb,true) <= transport
c_st_rec3_2.f3(lowb,true) after 10 ns,
c_st_rec3_1.f3(lowb,true) after 20 ns
when 1,
--
c_st_rec3_2.f3(lowb,true) after 10 ns ,
c_st_rec3_1.f3(lowb,true) after 20 ns ,
c_st_rec3_2.f3(lowb,true) after 30 ns ,
c_st_rec3_1.f3(lowb,true) after 40 ns
when 2,
--
c_st_rec3_1.f3(lowb,true) after 5 ns when 3 ;
--
end ARCH00626 ;
--
--
use WORK.STANDARD_TYPES.all ;
entity ENT00626_Test_Bench is
signal s_st_rec3 : st_rec3
:= c_st_rec3_1 ;
--
end ENT00626_Test_Bench ;
--
--
architecture ARCH00626_Test_Bench of ENT00626_Test_Bench is
begin
L1:
block
component UUT
port (
s_st_rec3 : inout st_rec3
) ;
end component ;
--
for CIS1 : UUT use entity WORK.ENT00626 ( ARCH00626 ) ;
begin
CIS1 : UUT
port map (
s_st_rec3
)
;
end block L1 ;
end ARCH00626_Test_Bench ;
| gpl-3.0 | 69011894eafbc0a1d873f073540474e3 | 0.500163 | 3.237493 | false | true | false | false |
jairov4/accel-oil | solution_virtex5_plb/impl/vhdl/p_bsf32_hw.vhd | 3 | 35,901 | -- ==============================================================
-- RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2014.1
-- Copyright (C) 2014 Xilinx Inc. All rights reserved.
--
-- ===========================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity p_bsf32_hw is
port (
bus_r : IN STD_LOGIC_VECTOR (31 downto 0);
ap_return : OUT STD_LOGIC_VECTOR (4 downto 0) );
end;
architecture behav of p_bsf32_hw is
constant ap_const_lv5_0 : STD_LOGIC_VECTOR (4 downto 0) := "00000";
constant ap_true : BOOLEAN := true;
constant ap_const_lv1_0 : STD_LOGIC_VECTOR (0 downto 0) := "0";
constant ap_const_lv5_1 : STD_LOGIC_VECTOR (4 downto 0) := "00001";
constant ap_const_lv5_2 : STD_LOGIC_VECTOR (4 downto 0) := "00010";
constant ap_const_lv5_3 : STD_LOGIC_VECTOR (4 downto 0) := "00011";
constant ap_const_lv5_4 : STD_LOGIC_VECTOR (4 downto 0) := "00100";
constant ap_const_lv5_5 : STD_LOGIC_VECTOR (4 downto 0) := "00101";
constant ap_const_lv5_6 : STD_LOGIC_VECTOR (4 downto 0) := "00110";
constant ap_const_lv5_7 : STD_LOGIC_VECTOR (4 downto 0) := "00111";
constant ap_const_lv5_8 : STD_LOGIC_VECTOR (4 downto 0) := "01000";
constant ap_const_lv5_9 : STD_LOGIC_VECTOR (4 downto 0) := "01001";
constant ap_const_lv5_A : STD_LOGIC_VECTOR (4 downto 0) := "01010";
constant ap_const_lv5_B : STD_LOGIC_VECTOR (4 downto 0) := "01011";
constant ap_const_lv5_C : STD_LOGIC_VECTOR (4 downto 0) := "01100";
constant ap_const_lv5_D : STD_LOGIC_VECTOR (4 downto 0) := "01101";
constant ap_const_lv5_E : STD_LOGIC_VECTOR (4 downto 0) := "01110";
constant ap_const_lv5_F : STD_LOGIC_VECTOR (4 downto 0) := "01111";
constant ap_const_lv5_10 : STD_LOGIC_VECTOR (4 downto 0) := "10000";
constant ap_const_lv5_11 : STD_LOGIC_VECTOR (4 downto 0) := "10001";
constant ap_const_lv5_12 : STD_LOGIC_VECTOR (4 downto 0) := "10010";
constant ap_const_lv5_13 : STD_LOGIC_VECTOR (4 downto 0) := "10011";
constant ap_const_lv5_14 : STD_LOGIC_VECTOR (4 downto 0) := "10100";
constant ap_const_lv5_15 : STD_LOGIC_VECTOR (4 downto 0) := "10101";
constant ap_const_lv5_16 : STD_LOGIC_VECTOR (4 downto 0) := "10110";
constant ap_const_lv5_17 : STD_LOGIC_VECTOR (4 downto 0) := "10111";
constant ap_const_lv5_18 : STD_LOGIC_VECTOR (4 downto 0) := "11000";
constant ap_const_lv5_19 : STD_LOGIC_VECTOR (4 downto 0) := "11001";
constant ap_const_lv5_1A : STD_LOGIC_VECTOR (4 downto 0) := "11010";
constant ap_const_lv5_1B : STD_LOGIC_VECTOR (4 downto 0) := "11011";
constant ap_const_lv5_1C : STD_LOGIC_VECTOR (4 downto 0) := "11100";
constant ap_const_lv5_1D : STD_LOGIC_VECTOR (4 downto 0) := "11101";
constant ap_const_lv5_1E : STD_LOGIC_VECTOR (4 downto 0) := "11110";
constant ap_const_lv5_1F : STD_LOGIC_VECTOR (4 downto 0) := "11111";
constant ap_const_lv32_1 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000001";
constant ap_const_lv32_2 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000010";
constant ap_const_lv32_3 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000011";
constant ap_const_lv32_4 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000100";
constant ap_const_lv32_5 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000101";
constant ap_const_lv32_6 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000110";
constant ap_const_lv32_7 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000111";
constant ap_const_lv32_8 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001000";
constant ap_const_lv32_9 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001001";
constant ap_const_lv32_A : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001010";
constant ap_const_lv32_B : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001011";
constant ap_const_lv32_C : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001100";
constant ap_const_lv32_D : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001101";
constant ap_const_lv32_E : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001110";
constant ap_const_lv32_F : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001111";
constant ap_const_lv32_10 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000010000";
constant ap_const_lv32_11 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000010001";
constant ap_const_lv32_12 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000010010";
constant ap_const_lv32_13 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000010011";
constant ap_const_lv32_14 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000010100";
constant ap_const_lv32_15 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000010101";
constant ap_const_lv32_16 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000010110";
constant ap_const_lv32_17 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000010111";
constant ap_const_lv32_18 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000011000";
constant ap_const_lv32_19 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000011001";
constant ap_const_lv32_1A : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000011010";
constant ap_const_lv32_1B : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000011011";
constant ap_const_lv32_1C : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000011100";
constant ap_const_lv32_1D : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000011101";
constant ap_const_lv32_1E : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000011110";
constant ap_const_logic_1 : STD_LOGIC := '1';
constant ap_const_logic_0 : STD_LOGIC := '0';
signal p_s_phi_fu_139_p62 : STD_LOGIC_VECTOR (4 downto 0);
signal tmp_fu_246_p1 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_10_fu_250_p3 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_11_fu_258_p3 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_12_fu_266_p3 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_13_fu_274_p3 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_14_fu_282_p3 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_15_fu_290_p3 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_16_fu_298_p3 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_17_fu_306_p3 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_18_fu_314_p3 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_19_fu_322_p3 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_20_fu_330_p3 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_21_fu_338_p3 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_22_fu_346_p3 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_23_fu_354_p3 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_24_fu_362_p3 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_25_fu_370_p3 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_26_fu_378_p3 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_27_fu_386_p3 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_28_fu_394_p3 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_29_fu_402_p3 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_30_fu_410_p3 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_31_fu_418_p3 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_32_fu_426_p3 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_33_fu_434_p3 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_34_fu_442_p3 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_35_fu_450_p3 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_36_fu_458_p3 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_37_fu_466_p3 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_38_fu_474_p3 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_39_fu_482_p3 : STD_LOGIC_VECTOR (0 downto 0);
signal merge_phi_fu_237_p4 : STD_LOGIC_VECTOR (4 downto 0);
begin
ap_return <= merge_phi_fu_237_p4;
-- merge_phi_fu_237_p4 assign process. --
merge_phi_fu_237_p4_assign_proc : process(p_s_phi_fu_139_p62, tmp_fu_246_p1, tmp_10_fu_250_p3, tmp_11_fu_258_p3, tmp_12_fu_266_p3, tmp_13_fu_274_p3, tmp_14_fu_282_p3, tmp_15_fu_290_p3, tmp_16_fu_298_p3, tmp_17_fu_306_p3, tmp_18_fu_314_p3, tmp_19_fu_322_p3, tmp_20_fu_330_p3, tmp_21_fu_338_p3, tmp_22_fu_346_p3, tmp_23_fu_354_p3, tmp_24_fu_362_p3, tmp_25_fu_370_p3, tmp_26_fu_378_p3, tmp_27_fu_386_p3, tmp_28_fu_394_p3, tmp_29_fu_402_p3, tmp_30_fu_410_p3, tmp_31_fu_418_p3, tmp_32_fu_426_p3, tmp_33_fu_434_p3, tmp_34_fu_442_p3, tmp_35_fu_450_p3, tmp_36_fu_458_p3, tmp_37_fu_466_p3, tmp_38_fu_474_p3, tmp_39_fu_482_p3)
begin
if ((not((tmp_fu_246_p1 = ap_const_lv1_0)) or not((ap_const_lv1_0 = tmp_10_fu_250_p3)) or not((ap_const_lv1_0 = tmp_11_fu_258_p3)) or not((ap_const_lv1_0 = tmp_12_fu_266_p3)) or not((ap_const_lv1_0 = tmp_13_fu_274_p3)) or not((ap_const_lv1_0 = tmp_14_fu_282_p3)) or not((ap_const_lv1_0 = tmp_15_fu_290_p3)) or not((ap_const_lv1_0 = tmp_16_fu_298_p3)) or not((ap_const_lv1_0 = tmp_17_fu_306_p3)) or not((ap_const_lv1_0 = tmp_18_fu_314_p3)) or not((ap_const_lv1_0 = tmp_19_fu_322_p3)) or not((ap_const_lv1_0 = tmp_20_fu_330_p3)) or not((ap_const_lv1_0 = tmp_21_fu_338_p3)) or not((ap_const_lv1_0 = tmp_22_fu_346_p3)) or not((ap_const_lv1_0 = tmp_23_fu_354_p3)) or not((ap_const_lv1_0 = tmp_24_fu_362_p3)) or not((ap_const_lv1_0 = tmp_25_fu_370_p3)) or not((ap_const_lv1_0 = tmp_26_fu_378_p3)) or not((ap_const_lv1_0 = tmp_27_fu_386_p3)) or not((ap_const_lv1_0 = tmp_28_fu_394_p3)) or not((ap_const_lv1_0 = tmp_29_fu_402_p3)) or not((ap_const_lv1_0 = tmp_30_fu_410_p3)) or not((ap_const_lv1_0 = tmp_31_fu_418_p3)) or not((ap_const_lv1_0 = tmp_32_fu_426_p3)) or not((ap_const_lv1_0 = tmp_33_fu_434_p3)) or not((ap_const_lv1_0 = tmp_34_fu_442_p3)) or not((ap_const_lv1_0 = tmp_35_fu_450_p3)) or not((ap_const_lv1_0 = tmp_36_fu_458_p3)) or not((ap_const_lv1_0 = tmp_37_fu_466_p3)) or not((ap_const_lv1_0 = tmp_38_fu_474_p3)) or not((ap_const_lv1_0 = tmp_39_fu_482_p3)))) then
merge_phi_fu_237_p4 <= p_s_phi_fu_139_p62;
elsif (((tmp_fu_246_p1 = ap_const_lv1_0) and (ap_const_lv1_0 = tmp_10_fu_250_p3) and (ap_const_lv1_0 = tmp_11_fu_258_p3) and (ap_const_lv1_0 = tmp_12_fu_266_p3) and (ap_const_lv1_0 = tmp_13_fu_274_p3) and (ap_const_lv1_0 = tmp_14_fu_282_p3) and (ap_const_lv1_0 = tmp_15_fu_290_p3) and (ap_const_lv1_0 = tmp_16_fu_298_p3) and (ap_const_lv1_0 = tmp_17_fu_306_p3) and (ap_const_lv1_0 = tmp_18_fu_314_p3) and (ap_const_lv1_0 = tmp_19_fu_322_p3) and (ap_const_lv1_0 = tmp_20_fu_330_p3) and (ap_const_lv1_0 = tmp_21_fu_338_p3) and (ap_const_lv1_0 = tmp_22_fu_346_p3) and (ap_const_lv1_0 = tmp_23_fu_354_p3) and (ap_const_lv1_0 = tmp_24_fu_362_p3) and (ap_const_lv1_0 = tmp_25_fu_370_p3) and (ap_const_lv1_0 = tmp_26_fu_378_p3) and (ap_const_lv1_0 = tmp_27_fu_386_p3) and (ap_const_lv1_0 = tmp_28_fu_394_p3) and (ap_const_lv1_0 = tmp_29_fu_402_p3) and (ap_const_lv1_0 = tmp_30_fu_410_p3) and (ap_const_lv1_0 = tmp_31_fu_418_p3) and (ap_const_lv1_0 = tmp_32_fu_426_p3) and (ap_const_lv1_0 = tmp_33_fu_434_p3) and (ap_const_lv1_0 = tmp_34_fu_442_p3) and (ap_const_lv1_0 = tmp_35_fu_450_p3) and (ap_const_lv1_0 = tmp_36_fu_458_p3) and (ap_const_lv1_0 = tmp_37_fu_466_p3) and (ap_const_lv1_0 = tmp_38_fu_474_p3) and (ap_const_lv1_0 = tmp_39_fu_482_p3))) then
merge_phi_fu_237_p4 <= ap_const_lv5_1F;
else
merge_phi_fu_237_p4 <= "XXXXX";
end if;
end process;
-- p_s_phi_fu_139_p62 assign process. --
p_s_phi_fu_139_p62_assign_proc : process(tmp_fu_246_p1, tmp_10_fu_250_p3, tmp_11_fu_258_p3, tmp_12_fu_266_p3, tmp_13_fu_274_p3, tmp_14_fu_282_p3, tmp_15_fu_290_p3, tmp_16_fu_298_p3, tmp_17_fu_306_p3, tmp_18_fu_314_p3, tmp_19_fu_322_p3, tmp_20_fu_330_p3, tmp_21_fu_338_p3, tmp_22_fu_346_p3, tmp_23_fu_354_p3, tmp_24_fu_362_p3, tmp_25_fu_370_p3, tmp_26_fu_378_p3, tmp_27_fu_386_p3, tmp_28_fu_394_p3, tmp_29_fu_402_p3, tmp_30_fu_410_p3, tmp_31_fu_418_p3, tmp_32_fu_426_p3, tmp_33_fu_434_p3, tmp_34_fu_442_p3, tmp_35_fu_450_p3, tmp_36_fu_458_p3, tmp_37_fu_466_p3, tmp_38_fu_474_p3, tmp_39_fu_482_p3)
begin
if (((tmp_fu_246_p1 = ap_const_lv1_0) and (ap_const_lv1_0 = tmp_10_fu_250_p3) and (ap_const_lv1_0 = tmp_11_fu_258_p3) and (ap_const_lv1_0 = tmp_12_fu_266_p3) and (ap_const_lv1_0 = tmp_13_fu_274_p3) and (ap_const_lv1_0 = tmp_14_fu_282_p3) and (ap_const_lv1_0 = tmp_15_fu_290_p3) and (ap_const_lv1_0 = tmp_16_fu_298_p3) and (ap_const_lv1_0 = tmp_17_fu_306_p3) and (ap_const_lv1_0 = tmp_18_fu_314_p3) and (ap_const_lv1_0 = tmp_19_fu_322_p3) and (ap_const_lv1_0 = tmp_20_fu_330_p3) and (ap_const_lv1_0 = tmp_21_fu_338_p3) and (ap_const_lv1_0 = tmp_22_fu_346_p3) and (ap_const_lv1_0 = tmp_23_fu_354_p3) and (ap_const_lv1_0 = tmp_24_fu_362_p3) and (ap_const_lv1_0 = tmp_25_fu_370_p3) and (ap_const_lv1_0 = tmp_26_fu_378_p3) and (ap_const_lv1_0 = tmp_27_fu_386_p3) and (ap_const_lv1_0 = tmp_28_fu_394_p3) and (ap_const_lv1_0 = tmp_29_fu_402_p3) and (ap_const_lv1_0 = tmp_30_fu_410_p3) and (ap_const_lv1_0 = tmp_31_fu_418_p3) and (ap_const_lv1_0 = tmp_32_fu_426_p3) and (ap_const_lv1_0 = tmp_33_fu_434_p3) and (ap_const_lv1_0 = tmp_34_fu_442_p3) and (ap_const_lv1_0 = tmp_35_fu_450_p3) and (ap_const_lv1_0 = tmp_36_fu_458_p3) and (ap_const_lv1_0 = tmp_37_fu_466_p3) and (ap_const_lv1_0 = tmp_38_fu_474_p3) and not((ap_const_lv1_0 = tmp_39_fu_482_p3)))) then
p_s_phi_fu_139_p62 <= ap_const_lv5_1E;
elsif (((tmp_fu_246_p1 = ap_const_lv1_0) and (ap_const_lv1_0 = tmp_10_fu_250_p3) and (ap_const_lv1_0 = tmp_11_fu_258_p3) and (ap_const_lv1_0 = tmp_12_fu_266_p3) and (ap_const_lv1_0 = tmp_13_fu_274_p3) and (ap_const_lv1_0 = tmp_14_fu_282_p3) and (ap_const_lv1_0 = tmp_15_fu_290_p3) and (ap_const_lv1_0 = tmp_16_fu_298_p3) and (ap_const_lv1_0 = tmp_17_fu_306_p3) and (ap_const_lv1_0 = tmp_18_fu_314_p3) and (ap_const_lv1_0 = tmp_19_fu_322_p3) and (ap_const_lv1_0 = tmp_20_fu_330_p3) and (ap_const_lv1_0 = tmp_21_fu_338_p3) and (ap_const_lv1_0 = tmp_22_fu_346_p3) and (ap_const_lv1_0 = tmp_23_fu_354_p3) and (ap_const_lv1_0 = tmp_24_fu_362_p3) and (ap_const_lv1_0 = tmp_25_fu_370_p3) and (ap_const_lv1_0 = tmp_26_fu_378_p3) and (ap_const_lv1_0 = tmp_27_fu_386_p3) and (ap_const_lv1_0 = tmp_28_fu_394_p3) and (ap_const_lv1_0 = tmp_29_fu_402_p3) and (ap_const_lv1_0 = tmp_30_fu_410_p3) and (ap_const_lv1_0 = tmp_31_fu_418_p3) and (ap_const_lv1_0 = tmp_32_fu_426_p3) and (ap_const_lv1_0 = tmp_33_fu_434_p3) and (ap_const_lv1_0 = tmp_34_fu_442_p3) and (ap_const_lv1_0 = tmp_35_fu_450_p3) and (ap_const_lv1_0 = tmp_36_fu_458_p3) and (ap_const_lv1_0 = tmp_37_fu_466_p3) and not((ap_const_lv1_0 = tmp_38_fu_474_p3)))) then
p_s_phi_fu_139_p62 <= ap_const_lv5_1D;
elsif (((tmp_fu_246_p1 = ap_const_lv1_0) and (ap_const_lv1_0 = tmp_10_fu_250_p3) and (ap_const_lv1_0 = tmp_11_fu_258_p3) and (ap_const_lv1_0 = tmp_12_fu_266_p3) and (ap_const_lv1_0 = tmp_13_fu_274_p3) and (ap_const_lv1_0 = tmp_14_fu_282_p3) and (ap_const_lv1_0 = tmp_15_fu_290_p3) and (ap_const_lv1_0 = tmp_16_fu_298_p3) and (ap_const_lv1_0 = tmp_17_fu_306_p3) and (ap_const_lv1_0 = tmp_18_fu_314_p3) and (ap_const_lv1_0 = tmp_19_fu_322_p3) and (ap_const_lv1_0 = tmp_20_fu_330_p3) and (ap_const_lv1_0 = tmp_21_fu_338_p3) and (ap_const_lv1_0 = tmp_22_fu_346_p3) and (ap_const_lv1_0 = tmp_23_fu_354_p3) and (ap_const_lv1_0 = tmp_24_fu_362_p3) and (ap_const_lv1_0 = tmp_25_fu_370_p3) and (ap_const_lv1_0 = tmp_26_fu_378_p3) and (ap_const_lv1_0 = tmp_27_fu_386_p3) and (ap_const_lv1_0 = tmp_28_fu_394_p3) and (ap_const_lv1_0 = tmp_29_fu_402_p3) and (ap_const_lv1_0 = tmp_30_fu_410_p3) and (ap_const_lv1_0 = tmp_31_fu_418_p3) and (ap_const_lv1_0 = tmp_32_fu_426_p3) and (ap_const_lv1_0 = tmp_33_fu_434_p3) and (ap_const_lv1_0 = tmp_34_fu_442_p3) and (ap_const_lv1_0 = tmp_35_fu_450_p3) and (ap_const_lv1_0 = tmp_36_fu_458_p3) and not((ap_const_lv1_0 = tmp_37_fu_466_p3)))) then
p_s_phi_fu_139_p62 <= ap_const_lv5_1C;
elsif (((tmp_fu_246_p1 = ap_const_lv1_0) and (ap_const_lv1_0 = tmp_10_fu_250_p3) and (ap_const_lv1_0 = tmp_11_fu_258_p3) and (ap_const_lv1_0 = tmp_12_fu_266_p3) and (ap_const_lv1_0 = tmp_13_fu_274_p3) and (ap_const_lv1_0 = tmp_14_fu_282_p3) and (ap_const_lv1_0 = tmp_15_fu_290_p3) and (ap_const_lv1_0 = tmp_16_fu_298_p3) and (ap_const_lv1_0 = tmp_17_fu_306_p3) and (ap_const_lv1_0 = tmp_18_fu_314_p3) and (ap_const_lv1_0 = tmp_19_fu_322_p3) and (ap_const_lv1_0 = tmp_20_fu_330_p3) and (ap_const_lv1_0 = tmp_21_fu_338_p3) and (ap_const_lv1_0 = tmp_22_fu_346_p3) and (ap_const_lv1_0 = tmp_23_fu_354_p3) and (ap_const_lv1_0 = tmp_24_fu_362_p3) and (ap_const_lv1_0 = tmp_25_fu_370_p3) and (ap_const_lv1_0 = tmp_26_fu_378_p3) and (ap_const_lv1_0 = tmp_27_fu_386_p3) and (ap_const_lv1_0 = tmp_28_fu_394_p3) and (ap_const_lv1_0 = tmp_29_fu_402_p3) and (ap_const_lv1_0 = tmp_30_fu_410_p3) and (ap_const_lv1_0 = tmp_31_fu_418_p3) and (ap_const_lv1_0 = tmp_32_fu_426_p3) and (ap_const_lv1_0 = tmp_33_fu_434_p3) and (ap_const_lv1_0 = tmp_34_fu_442_p3) and (ap_const_lv1_0 = tmp_35_fu_450_p3) and not((ap_const_lv1_0 = tmp_36_fu_458_p3)))) then
p_s_phi_fu_139_p62 <= ap_const_lv5_1B;
elsif (((tmp_fu_246_p1 = ap_const_lv1_0) and (ap_const_lv1_0 = tmp_10_fu_250_p3) and (ap_const_lv1_0 = tmp_11_fu_258_p3) and (ap_const_lv1_0 = tmp_12_fu_266_p3) and (ap_const_lv1_0 = tmp_13_fu_274_p3) and (ap_const_lv1_0 = tmp_14_fu_282_p3) and (ap_const_lv1_0 = tmp_15_fu_290_p3) and (ap_const_lv1_0 = tmp_16_fu_298_p3) and (ap_const_lv1_0 = tmp_17_fu_306_p3) and (ap_const_lv1_0 = tmp_18_fu_314_p3) and (ap_const_lv1_0 = tmp_19_fu_322_p3) and (ap_const_lv1_0 = tmp_20_fu_330_p3) and (ap_const_lv1_0 = tmp_21_fu_338_p3) and (ap_const_lv1_0 = tmp_22_fu_346_p3) and (ap_const_lv1_0 = tmp_23_fu_354_p3) and (ap_const_lv1_0 = tmp_24_fu_362_p3) and (ap_const_lv1_0 = tmp_25_fu_370_p3) and (ap_const_lv1_0 = tmp_26_fu_378_p3) and (ap_const_lv1_0 = tmp_27_fu_386_p3) and (ap_const_lv1_0 = tmp_28_fu_394_p3) and (ap_const_lv1_0 = tmp_29_fu_402_p3) and (ap_const_lv1_0 = tmp_30_fu_410_p3) and (ap_const_lv1_0 = tmp_31_fu_418_p3) and (ap_const_lv1_0 = tmp_32_fu_426_p3) and (ap_const_lv1_0 = tmp_33_fu_434_p3) and (ap_const_lv1_0 = tmp_34_fu_442_p3) and not((ap_const_lv1_0 = tmp_35_fu_450_p3)))) then
p_s_phi_fu_139_p62 <= ap_const_lv5_1A;
elsif (((tmp_fu_246_p1 = ap_const_lv1_0) and (ap_const_lv1_0 = tmp_10_fu_250_p3) and (ap_const_lv1_0 = tmp_11_fu_258_p3) and (ap_const_lv1_0 = tmp_12_fu_266_p3) and (ap_const_lv1_0 = tmp_13_fu_274_p3) and (ap_const_lv1_0 = tmp_14_fu_282_p3) and (ap_const_lv1_0 = tmp_15_fu_290_p3) and (ap_const_lv1_0 = tmp_16_fu_298_p3) and (ap_const_lv1_0 = tmp_17_fu_306_p3) and (ap_const_lv1_0 = tmp_18_fu_314_p3) and (ap_const_lv1_0 = tmp_19_fu_322_p3) and (ap_const_lv1_0 = tmp_20_fu_330_p3) and (ap_const_lv1_0 = tmp_21_fu_338_p3) and (ap_const_lv1_0 = tmp_22_fu_346_p3) and (ap_const_lv1_0 = tmp_23_fu_354_p3) and (ap_const_lv1_0 = tmp_24_fu_362_p3) and (ap_const_lv1_0 = tmp_25_fu_370_p3) and (ap_const_lv1_0 = tmp_26_fu_378_p3) and (ap_const_lv1_0 = tmp_27_fu_386_p3) and (ap_const_lv1_0 = tmp_28_fu_394_p3) and (ap_const_lv1_0 = tmp_29_fu_402_p3) and (ap_const_lv1_0 = tmp_30_fu_410_p3) and (ap_const_lv1_0 = tmp_31_fu_418_p3) and (ap_const_lv1_0 = tmp_32_fu_426_p3) and (ap_const_lv1_0 = tmp_33_fu_434_p3) and not((ap_const_lv1_0 = tmp_34_fu_442_p3)))) then
p_s_phi_fu_139_p62 <= ap_const_lv5_19;
elsif (((tmp_fu_246_p1 = ap_const_lv1_0) and (ap_const_lv1_0 = tmp_10_fu_250_p3) and (ap_const_lv1_0 = tmp_11_fu_258_p3) and (ap_const_lv1_0 = tmp_12_fu_266_p3) and (ap_const_lv1_0 = tmp_13_fu_274_p3) and (ap_const_lv1_0 = tmp_14_fu_282_p3) and (ap_const_lv1_0 = tmp_15_fu_290_p3) and (ap_const_lv1_0 = tmp_16_fu_298_p3) and (ap_const_lv1_0 = tmp_17_fu_306_p3) and (ap_const_lv1_0 = tmp_18_fu_314_p3) and (ap_const_lv1_0 = tmp_19_fu_322_p3) and (ap_const_lv1_0 = tmp_20_fu_330_p3) and (ap_const_lv1_0 = tmp_21_fu_338_p3) and (ap_const_lv1_0 = tmp_22_fu_346_p3) and (ap_const_lv1_0 = tmp_23_fu_354_p3) and (ap_const_lv1_0 = tmp_24_fu_362_p3) and (ap_const_lv1_0 = tmp_25_fu_370_p3) and (ap_const_lv1_0 = tmp_26_fu_378_p3) and (ap_const_lv1_0 = tmp_27_fu_386_p3) and (ap_const_lv1_0 = tmp_28_fu_394_p3) and (ap_const_lv1_0 = tmp_29_fu_402_p3) and (ap_const_lv1_0 = tmp_30_fu_410_p3) and (ap_const_lv1_0 = tmp_31_fu_418_p3) and (ap_const_lv1_0 = tmp_32_fu_426_p3) and not((ap_const_lv1_0 = tmp_33_fu_434_p3)))) then
p_s_phi_fu_139_p62 <= ap_const_lv5_18;
elsif (((tmp_fu_246_p1 = ap_const_lv1_0) and (ap_const_lv1_0 = tmp_10_fu_250_p3) and (ap_const_lv1_0 = tmp_11_fu_258_p3) and (ap_const_lv1_0 = tmp_12_fu_266_p3) and (ap_const_lv1_0 = tmp_13_fu_274_p3) and (ap_const_lv1_0 = tmp_14_fu_282_p3) and (ap_const_lv1_0 = tmp_15_fu_290_p3) and (ap_const_lv1_0 = tmp_16_fu_298_p3) and (ap_const_lv1_0 = tmp_17_fu_306_p3) and (ap_const_lv1_0 = tmp_18_fu_314_p3) and (ap_const_lv1_0 = tmp_19_fu_322_p3) and (ap_const_lv1_0 = tmp_20_fu_330_p3) and (ap_const_lv1_0 = tmp_21_fu_338_p3) and (ap_const_lv1_0 = tmp_22_fu_346_p3) and (ap_const_lv1_0 = tmp_23_fu_354_p3) and (ap_const_lv1_0 = tmp_24_fu_362_p3) and (ap_const_lv1_0 = tmp_25_fu_370_p3) and (ap_const_lv1_0 = tmp_26_fu_378_p3) and (ap_const_lv1_0 = tmp_27_fu_386_p3) and (ap_const_lv1_0 = tmp_28_fu_394_p3) and (ap_const_lv1_0 = tmp_29_fu_402_p3) and (ap_const_lv1_0 = tmp_30_fu_410_p3) and (ap_const_lv1_0 = tmp_31_fu_418_p3) and not((ap_const_lv1_0 = tmp_32_fu_426_p3)))) then
p_s_phi_fu_139_p62 <= ap_const_lv5_17;
elsif (((tmp_fu_246_p1 = ap_const_lv1_0) and (ap_const_lv1_0 = tmp_10_fu_250_p3) and (ap_const_lv1_0 = tmp_11_fu_258_p3) and (ap_const_lv1_0 = tmp_12_fu_266_p3) and (ap_const_lv1_0 = tmp_13_fu_274_p3) and (ap_const_lv1_0 = tmp_14_fu_282_p3) and (ap_const_lv1_0 = tmp_15_fu_290_p3) and (ap_const_lv1_0 = tmp_16_fu_298_p3) and (ap_const_lv1_0 = tmp_17_fu_306_p3) and (ap_const_lv1_0 = tmp_18_fu_314_p3) and (ap_const_lv1_0 = tmp_19_fu_322_p3) and (ap_const_lv1_0 = tmp_20_fu_330_p3) and (ap_const_lv1_0 = tmp_21_fu_338_p3) and (ap_const_lv1_0 = tmp_22_fu_346_p3) and (ap_const_lv1_0 = tmp_23_fu_354_p3) and (ap_const_lv1_0 = tmp_24_fu_362_p3) and (ap_const_lv1_0 = tmp_25_fu_370_p3) and (ap_const_lv1_0 = tmp_26_fu_378_p3) and (ap_const_lv1_0 = tmp_27_fu_386_p3) and (ap_const_lv1_0 = tmp_28_fu_394_p3) and (ap_const_lv1_0 = tmp_29_fu_402_p3) and (ap_const_lv1_0 = tmp_30_fu_410_p3) and not((ap_const_lv1_0 = tmp_31_fu_418_p3)))) then
p_s_phi_fu_139_p62 <= ap_const_lv5_16;
elsif (((tmp_fu_246_p1 = ap_const_lv1_0) and (ap_const_lv1_0 = tmp_10_fu_250_p3) and (ap_const_lv1_0 = tmp_11_fu_258_p3) and (ap_const_lv1_0 = tmp_12_fu_266_p3) and (ap_const_lv1_0 = tmp_13_fu_274_p3) and (ap_const_lv1_0 = tmp_14_fu_282_p3) and (ap_const_lv1_0 = tmp_15_fu_290_p3) and (ap_const_lv1_0 = tmp_16_fu_298_p3) and (ap_const_lv1_0 = tmp_17_fu_306_p3) and (ap_const_lv1_0 = tmp_18_fu_314_p3) and (ap_const_lv1_0 = tmp_19_fu_322_p3) and (ap_const_lv1_0 = tmp_20_fu_330_p3) and (ap_const_lv1_0 = tmp_21_fu_338_p3) and (ap_const_lv1_0 = tmp_22_fu_346_p3) and (ap_const_lv1_0 = tmp_23_fu_354_p3) and (ap_const_lv1_0 = tmp_24_fu_362_p3) and (ap_const_lv1_0 = tmp_25_fu_370_p3) and (ap_const_lv1_0 = tmp_26_fu_378_p3) and (ap_const_lv1_0 = tmp_27_fu_386_p3) and (ap_const_lv1_0 = tmp_28_fu_394_p3) and (ap_const_lv1_0 = tmp_29_fu_402_p3) and not((ap_const_lv1_0 = tmp_30_fu_410_p3)))) then
p_s_phi_fu_139_p62 <= ap_const_lv5_15;
elsif (((tmp_fu_246_p1 = ap_const_lv1_0) and (ap_const_lv1_0 = tmp_10_fu_250_p3) and (ap_const_lv1_0 = tmp_11_fu_258_p3) and (ap_const_lv1_0 = tmp_12_fu_266_p3) and (ap_const_lv1_0 = tmp_13_fu_274_p3) and (ap_const_lv1_0 = tmp_14_fu_282_p3) and (ap_const_lv1_0 = tmp_15_fu_290_p3) and (ap_const_lv1_0 = tmp_16_fu_298_p3) and (ap_const_lv1_0 = tmp_17_fu_306_p3) and (ap_const_lv1_0 = tmp_18_fu_314_p3) and (ap_const_lv1_0 = tmp_19_fu_322_p3) and (ap_const_lv1_0 = tmp_20_fu_330_p3) and (ap_const_lv1_0 = tmp_21_fu_338_p3) and (ap_const_lv1_0 = tmp_22_fu_346_p3) and (ap_const_lv1_0 = tmp_23_fu_354_p3) and (ap_const_lv1_0 = tmp_24_fu_362_p3) and (ap_const_lv1_0 = tmp_25_fu_370_p3) and (ap_const_lv1_0 = tmp_26_fu_378_p3) and (ap_const_lv1_0 = tmp_27_fu_386_p3) and (ap_const_lv1_0 = tmp_28_fu_394_p3) and not((ap_const_lv1_0 = tmp_29_fu_402_p3)))) then
p_s_phi_fu_139_p62 <= ap_const_lv5_14;
elsif (((tmp_fu_246_p1 = ap_const_lv1_0) and (ap_const_lv1_0 = tmp_10_fu_250_p3) and (ap_const_lv1_0 = tmp_11_fu_258_p3) and (ap_const_lv1_0 = tmp_12_fu_266_p3) and (ap_const_lv1_0 = tmp_13_fu_274_p3) and (ap_const_lv1_0 = tmp_14_fu_282_p3) and (ap_const_lv1_0 = tmp_15_fu_290_p3) and (ap_const_lv1_0 = tmp_16_fu_298_p3) and (ap_const_lv1_0 = tmp_17_fu_306_p3) and (ap_const_lv1_0 = tmp_18_fu_314_p3) and (ap_const_lv1_0 = tmp_19_fu_322_p3) and (ap_const_lv1_0 = tmp_20_fu_330_p3) and (ap_const_lv1_0 = tmp_21_fu_338_p3) and (ap_const_lv1_0 = tmp_22_fu_346_p3) and (ap_const_lv1_0 = tmp_23_fu_354_p3) and (ap_const_lv1_0 = tmp_24_fu_362_p3) and (ap_const_lv1_0 = tmp_25_fu_370_p3) and (ap_const_lv1_0 = tmp_26_fu_378_p3) and (ap_const_lv1_0 = tmp_27_fu_386_p3) and not((ap_const_lv1_0 = tmp_28_fu_394_p3)))) then
p_s_phi_fu_139_p62 <= ap_const_lv5_13;
elsif (((tmp_fu_246_p1 = ap_const_lv1_0) and (ap_const_lv1_0 = tmp_10_fu_250_p3) and (ap_const_lv1_0 = tmp_11_fu_258_p3) and (ap_const_lv1_0 = tmp_12_fu_266_p3) and (ap_const_lv1_0 = tmp_13_fu_274_p3) and (ap_const_lv1_0 = tmp_14_fu_282_p3) and (ap_const_lv1_0 = tmp_15_fu_290_p3) and (ap_const_lv1_0 = tmp_16_fu_298_p3) and (ap_const_lv1_0 = tmp_17_fu_306_p3) and (ap_const_lv1_0 = tmp_18_fu_314_p3) and (ap_const_lv1_0 = tmp_19_fu_322_p3) and (ap_const_lv1_0 = tmp_20_fu_330_p3) and (ap_const_lv1_0 = tmp_21_fu_338_p3) and (ap_const_lv1_0 = tmp_22_fu_346_p3) and (ap_const_lv1_0 = tmp_23_fu_354_p3) and (ap_const_lv1_0 = tmp_24_fu_362_p3) and (ap_const_lv1_0 = tmp_25_fu_370_p3) and (ap_const_lv1_0 = tmp_26_fu_378_p3) and not((ap_const_lv1_0 = tmp_27_fu_386_p3)))) then
p_s_phi_fu_139_p62 <= ap_const_lv5_12;
elsif (((tmp_fu_246_p1 = ap_const_lv1_0) and (ap_const_lv1_0 = tmp_10_fu_250_p3) and (ap_const_lv1_0 = tmp_11_fu_258_p3) and (ap_const_lv1_0 = tmp_12_fu_266_p3) and (ap_const_lv1_0 = tmp_13_fu_274_p3) and (ap_const_lv1_0 = tmp_14_fu_282_p3) and (ap_const_lv1_0 = tmp_15_fu_290_p3) and (ap_const_lv1_0 = tmp_16_fu_298_p3) and (ap_const_lv1_0 = tmp_17_fu_306_p3) and (ap_const_lv1_0 = tmp_18_fu_314_p3) and (ap_const_lv1_0 = tmp_19_fu_322_p3) and (ap_const_lv1_0 = tmp_20_fu_330_p3) and (ap_const_lv1_0 = tmp_21_fu_338_p3) and (ap_const_lv1_0 = tmp_22_fu_346_p3) and (ap_const_lv1_0 = tmp_23_fu_354_p3) and (ap_const_lv1_0 = tmp_24_fu_362_p3) and (ap_const_lv1_0 = tmp_25_fu_370_p3) and not((ap_const_lv1_0 = tmp_26_fu_378_p3)))) then
p_s_phi_fu_139_p62 <= ap_const_lv5_11;
elsif (((tmp_fu_246_p1 = ap_const_lv1_0) and (ap_const_lv1_0 = tmp_10_fu_250_p3) and (ap_const_lv1_0 = tmp_11_fu_258_p3) and (ap_const_lv1_0 = tmp_12_fu_266_p3) and (ap_const_lv1_0 = tmp_13_fu_274_p3) and (ap_const_lv1_0 = tmp_14_fu_282_p3) and (ap_const_lv1_0 = tmp_15_fu_290_p3) and (ap_const_lv1_0 = tmp_16_fu_298_p3) and (ap_const_lv1_0 = tmp_17_fu_306_p3) and (ap_const_lv1_0 = tmp_18_fu_314_p3) and (ap_const_lv1_0 = tmp_19_fu_322_p3) and (ap_const_lv1_0 = tmp_20_fu_330_p3) and (ap_const_lv1_0 = tmp_21_fu_338_p3) and (ap_const_lv1_0 = tmp_22_fu_346_p3) and (ap_const_lv1_0 = tmp_23_fu_354_p3) and (ap_const_lv1_0 = tmp_24_fu_362_p3) and not((ap_const_lv1_0 = tmp_25_fu_370_p3)))) then
p_s_phi_fu_139_p62 <= ap_const_lv5_10;
elsif (((tmp_fu_246_p1 = ap_const_lv1_0) and (ap_const_lv1_0 = tmp_10_fu_250_p3) and (ap_const_lv1_0 = tmp_11_fu_258_p3) and (ap_const_lv1_0 = tmp_12_fu_266_p3) and (ap_const_lv1_0 = tmp_13_fu_274_p3) and (ap_const_lv1_0 = tmp_14_fu_282_p3) and (ap_const_lv1_0 = tmp_15_fu_290_p3) and (ap_const_lv1_0 = tmp_16_fu_298_p3) and (ap_const_lv1_0 = tmp_17_fu_306_p3) and (ap_const_lv1_0 = tmp_18_fu_314_p3) and (ap_const_lv1_0 = tmp_19_fu_322_p3) and (ap_const_lv1_0 = tmp_20_fu_330_p3) and (ap_const_lv1_0 = tmp_21_fu_338_p3) and (ap_const_lv1_0 = tmp_22_fu_346_p3) and (ap_const_lv1_0 = tmp_23_fu_354_p3) and not((ap_const_lv1_0 = tmp_24_fu_362_p3)))) then
p_s_phi_fu_139_p62 <= ap_const_lv5_F;
elsif (((tmp_fu_246_p1 = ap_const_lv1_0) and (ap_const_lv1_0 = tmp_10_fu_250_p3) and (ap_const_lv1_0 = tmp_11_fu_258_p3) and (ap_const_lv1_0 = tmp_12_fu_266_p3) and (ap_const_lv1_0 = tmp_13_fu_274_p3) and (ap_const_lv1_0 = tmp_14_fu_282_p3) and (ap_const_lv1_0 = tmp_15_fu_290_p3) and (ap_const_lv1_0 = tmp_16_fu_298_p3) and (ap_const_lv1_0 = tmp_17_fu_306_p3) and (ap_const_lv1_0 = tmp_18_fu_314_p3) and (ap_const_lv1_0 = tmp_19_fu_322_p3) and (ap_const_lv1_0 = tmp_20_fu_330_p3) and (ap_const_lv1_0 = tmp_21_fu_338_p3) and (ap_const_lv1_0 = tmp_22_fu_346_p3) and not((ap_const_lv1_0 = tmp_23_fu_354_p3)))) then
p_s_phi_fu_139_p62 <= ap_const_lv5_E;
elsif (((tmp_fu_246_p1 = ap_const_lv1_0) and (ap_const_lv1_0 = tmp_10_fu_250_p3) and (ap_const_lv1_0 = tmp_11_fu_258_p3) and (ap_const_lv1_0 = tmp_12_fu_266_p3) and (ap_const_lv1_0 = tmp_13_fu_274_p3) and (ap_const_lv1_0 = tmp_14_fu_282_p3) and (ap_const_lv1_0 = tmp_15_fu_290_p3) and (ap_const_lv1_0 = tmp_16_fu_298_p3) and (ap_const_lv1_0 = tmp_17_fu_306_p3) and (ap_const_lv1_0 = tmp_18_fu_314_p3) and (ap_const_lv1_0 = tmp_19_fu_322_p3) and (ap_const_lv1_0 = tmp_20_fu_330_p3) and (ap_const_lv1_0 = tmp_21_fu_338_p3) and not((ap_const_lv1_0 = tmp_22_fu_346_p3)))) then
p_s_phi_fu_139_p62 <= ap_const_lv5_D;
elsif (((tmp_fu_246_p1 = ap_const_lv1_0) and (ap_const_lv1_0 = tmp_10_fu_250_p3) and (ap_const_lv1_0 = tmp_11_fu_258_p3) and (ap_const_lv1_0 = tmp_12_fu_266_p3) and (ap_const_lv1_0 = tmp_13_fu_274_p3) and (ap_const_lv1_0 = tmp_14_fu_282_p3) and (ap_const_lv1_0 = tmp_15_fu_290_p3) and (ap_const_lv1_0 = tmp_16_fu_298_p3) and (ap_const_lv1_0 = tmp_17_fu_306_p3) and (ap_const_lv1_0 = tmp_18_fu_314_p3) and (ap_const_lv1_0 = tmp_19_fu_322_p3) and (ap_const_lv1_0 = tmp_20_fu_330_p3) and not((ap_const_lv1_0 = tmp_21_fu_338_p3)))) then
p_s_phi_fu_139_p62 <= ap_const_lv5_C;
elsif (((tmp_fu_246_p1 = ap_const_lv1_0) and (ap_const_lv1_0 = tmp_10_fu_250_p3) and (ap_const_lv1_0 = tmp_11_fu_258_p3) and (ap_const_lv1_0 = tmp_12_fu_266_p3) and (ap_const_lv1_0 = tmp_13_fu_274_p3) and (ap_const_lv1_0 = tmp_14_fu_282_p3) and (ap_const_lv1_0 = tmp_15_fu_290_p3) and (ap_const_lv1_0 = tmp_16_fu_298_p3) and (ap_const_lv1_0 = tmp_17_fu_306_p3) and (ap_const_lv1_0 = tmp_18_fu_314_p3) and (ap_const_lv1_0 = tmp_19_fu_322_p3) and not((ap_const_lv1_0 = tmp_20_fu_330_p3)))) then
p_s_phi_fu_139_p62 <= ap_const_lv5_B;
elsif (((tmp_fu_246_p1 = ap_const_lv1_0) and (ap_const_lv1_0 = tmp_10_fu_250_p3) and (ap_const_lv1_0 = tmp_11_fu_258_p3) and (ap_const_lv1_0 = tmp_12_fu_266_p3) and (ap_const_lv1_0 = tmp_13_fu_274_p3) and (ap_const_lv1_0 = tmp_14_fu_282_p3) and (ap_const_lv1_0 = tmp_15_fu_290_p3) and (ap_const_lv1_0 = tmp_16_fu_298_p3) and (ap_const_lv1_0 = tmp_17_fu_306_p3) and (ap_const_lv1_0 = tmp_18_fu_314_p3) and not((ap_const_lv1_0 = tmp_19_fu_322_p3)))) then
p_s_phi_fu_139_p62 <= ap_const_lv5_A;
elsif (((tmp_fu_246_p1 = ap_const_lv1_0) and (ap_const_lv1_0 = tmp_10_fu_250_p3) and (ap_const_lv1_0 = tmp_11_fu_258_p3) and (ap_const_lv1_0 = tmp_12_fu_266_p3) and (ap_const_lv1_0 = tmp_13_fu_274_p3) and (ap_const_lv1_0 = tmp_14_fu_282_p3) and (ap_const_lv1_0 = tmp_15_fu_290_p3) and (ap_const_lv1_0 = tmp_16_fu_298_p3) and (ap_const_lv1_0 = tmp_17_fu_306_p3) and not((ap_const_lv1_0 = tmp_18_fu_314_p3)))) then
p_s_phi_fu_139_p62 <= ap_const_lv5_9;
elsif (((tmp_fu_246_p1 = ap_const_lv1_0) and (ap_const_lv1_0 = tmp_10_fu_250_p3) and (ap_const_lv1_0 = tmp_11_fu_258_p3) and (ap_const_lv1_0 = tmp_12_fu_266_p3) and (ap_const_lv1_0 = tmp_13_fu_274_p3) and (ap_const_lv1_0 = tmp_14_fu_282_p3) and (ap_const_lv1_0 = tmp_15_fu_290_p3) and (ap_const_lv1_0 = tmp_16_fu_298_p3) and not((ap_const_lv1_0 = tmp_17_fu_306_p3)))) then
p_s_phi_fu_139_p62 <= ap_const_lv5_8;
elsif (((tmp_fu_246_p1 = ap_const_lv1_0) and (ap_const_lv1_0 = tmp_10_fu_250_p3) and (ap_const_lv1_0 = tmp_11_fu_258_p3) and (ap_const_lv1_0 = tmp_12_fu_266_p3) and (ap_const_lv1_0 = tmp_13_fu_274_p3) and (ap_const_lv1_0 = tmp_14_fu_282_p3) and (ap_const_lv1_0 = tmp_15_fu_290_p3) and not((ap_const_lv1_0 = tmp_16_fu_298_p3)))) then
p_s_phi_fu_139_p62 <= ap_const_lv5_7;
elsif (((tmp_fu_246_p1 = ap_const_lv1_0) and (ap_const_lv1_0 = tmp_10_fu_250_p3) and (ap_const_lv1_0 = tmp_11_fu_258_p3) and (ap_const_lv1_0 = tmp_12_fu_266_p3) and (ap_const_lv1_0 = tmp_13_fu_274_p3) and (ap_const_lv1_0 = tmp_14_fu_282_p3) and not((ap_const_lv1_0 = tmp_15_fu_290_p3)))) then
p_s_phi_fu_139_p62 <= ap_const_lv5_6;
elsif (((tmp_fu_246_p1 = ap_const_lv1_0) and (ap_const_lv1_0 = tmp_10_fu_250_p3) and (ap_const_lv1_0 = tmp_11_fu_258_p3) and (ap_const_lv1_0 = tmp_12_fu_266_p3) and (ap_const_lv1_0 = tmp_13_fu_274_p3) and not((ap_const_lv1_0 = tmp_14_fu_282_p3)))) then
p_s_phi_fu_139_p62 <= ap_const_lv5_5;
elsif (((tmp_fu_246_p1 = ap_const_lv1_0) and (ap_const_lv1_0 = tmp_10_fu_250_p3) and (ap_const_lv1_0 = tmp_11_fu_258_p3) and (ap_const_lv1_0 = tmp_12_fu_266_p3) and not((ap_const_lv1_0 = tmp_13_fu_274_p3)))) then
p_s_phi_fu_139_p62 <= ap_const_lv5_4;
elsif (((tmp_fu_246_p1 = ap_const_lv1_0) and (ap_const_lv1_0 = tmp_10_fu_250_p3) and (ap_const_lv1_0 = tmp_11_fu_258_p3) and not((ap_const_lv1_0 = tmp_12_fu_266_p3)))) then
p_s_phi_fu_139_p62 <= ap_const_lv5_3;
elsif (((tmp_fu_246_p1 = ap_const_lv1_0) and (ap_const_lv1_0 = tmp_10_fu_250_p3) and not((ap_const_lv1_0 = tmp_11_fu_258_p3)))) then
p_s_phi_fu_139_p62 <= ap_const_lv5_2;
elsif (((tmp_fu_246_p1 = ap_const_lv1_0) and not((ap_const_lv1_0 = tmp_10_fu_250_p3)))) then
p_s_phi_fu_139_p62 <= ap_const_lv5_1;
elsif (not((tmp_fu_246_p1 = ap_const_lv1_0))) then
p_s_phi_fu_139_p62 <= ap_const_lv5_0;
else
p_s_phi_fu_139_p62 <= "XXXXX";
end if;
end process;
tmp_10_fu_250_p3 <= bus_r(1 downto 1);
tmp_11_fu_258_p3 <= bus_r(2 downto 2);
tmp_12_fu_266_p3 <= bus_r(3 downto 3);
tmp_13_fu_274_p3 <= bus_r(4 downto 4);
tmp_14_fu_282_p3 <= bus_r(5 downto 5);
tmp_15_fu_290_p3 <= bus_r(6 downto 6);
tmp_16_fu_298_p3 <= bus_r(7 downto 7);
tmp_17_fu_306_p3 <= bus_r(8 downto 8);
tmp_18_fu_314_p3 <= bus_r(9 downto 9);
tmp_19_fu_322_p3 <= bus_r(10 downto 10);
tmp_20_fu_330_p3 <= bus_r(11 downto 11);
tmp_21_fu_338_p3 <= bus_r(12 downto 12);
tmp_22_fu_346_p3 <= bus_r(13 downto 13);
tmp_23_fu_354_p3 <= bus_r(14 downto 14);
tmp_24_fu_362_p3 <= bus_r(15 downto 15);
tmp_25_fu_370_p3 <= bus_r(16 downto 16);
tmp_26_fu_378_p3 <= bus_r(17 downto 17);
tmp_27_fu_386_p3 <= bus_r(18 downto 18);
tmp_28_fu_394_p3 <= bus_r(19 downto 19);
tmp_29_fu_402_p3 <= bus_r(20 downto 20);
tmp_30_fu_410_p3 <= bus_r(21 downto 21);
tmp_31_fu_418_p3 <= bus_r(22 downto 22);
tmp_32_fu_426_p3 <= bus_r(23 downto 23);
tmp_33_fu_434_p3 <= bus_r(24 downto 24);
tmp_34_fu_442_p3 <= bus_r(25 downto 25);
tmp_35_fu_450_p3 <= bus_r(26 downto 26);
tmp_36_fu_458_p3 <= bus_r(27 downto 27);
tmp_37_fu_466_p3 <= bus_r(28 downto 28);
tmp_38_fu_474_p3 <= bus_r(29 downto 29);
tmp_39_fu_482_p3 <= bus_r(30 downto 30);
tmp_fu_246_p1 <= bus_r(1 - 1 downto 0);
end behav;
| lgpl-3.0 | 1e12d4b5163c54c3045fdf0c1d54dc3e | 0.636751 | 2.099965 | false | false | false | false |
grwlf/vsim | vhdl_ct/ct00569.vhd | 1 | 8,785 | -- NEED RESULT: ARCH00569: Attribute declarations - composite generic subtypes with static initial values passed
-- NEED RESULT: ARCH00569: Attribute declarations - scalar generic subtypes with generic initial values passed
-------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
-------------------------------------------------------------------------------
--
-- TEST NAME:
--
-- CT00569
--
-- AUTHOR:
--
-- A. Wilmot
--
-- TEST OBJECTIVES:
--
-- 4.4 (1)
-- 4.4 (7)
--
-- DESIGN UNIT ORDERING:
--
-- GENERIC_STANDARD_TYPES(ARCH00569)
-- ENT00569_Test_Bench(ARCH00569_Test_Bench)
--
-- REVISION HISTORY:
--
-- 19-AUG-1987 - initial revision
--
-- NOTES:
--
-- self-checking
-- automatically generated
--
use WORK.STANDARD_TYPES.all ;
architecture ARCH00569 of GENERIC_STANDARD_TYPES is
begin
B1 :
block
generic (
i_bit_vector_1, i_bit_vector_2 : bit_vector
:= c_st_bit_vector_1 ;
i_string_1, i_string_2 : string
:= c_st_string_1 ;
i_t_rec1_1, i_t_rec1_2 : t_rec1
:= c_st_rec1_1 ;
i_st_rec1_1, i_st_rec1_2 : st_rec1
:= c_st_rec1_1 ;
i_t_rec2_1, i_t_rec2_2 : t_rec2
:= c_st_rec2_1 ;
i_st_rec2_1, i_st_rec2_2 : st_rec2
:= c_st_rec2_1 ;
i_t_rec3_1, i_t_rec3_2 : t_rec3
:= c_st_rec3_1 ;
i_st_rec3_1, i_st_rec3_2 : st_rec3
:= c_st_rec3_1 ;
i_t_arr1_1, i_t_arr1_2 : t_arr1
:= c_st_arr1_1 ;
i_st_arr1_1, i_st_arr1_2 : st_arr1
:= c_st_arr1_1 ;
i_t_arr2_1, i_t_arr2_2 : t_arr2
:= c_st_arr2_1 ;
i_st_arr2_1, i_st_arr2_2 : st_arr2
:= c_st_arr2_1 ;
i_t_arr3_1, i_t_arr3_2 : t_arr3
:= c_st_arr3_1 ;
i_st_arr3_1, i_st_arr3_2 : st_arr3
:= c_st_arr3_1
) ;
generic map (
open, open,
open, open,
open, open,
open, open,
open, open,
open, open,
open, open,
open, open,
open, open,
open, open,
open, open,
open, open,
open, open,
open, open
) ;
attribute at_bit_vector_1 : bit_vector ;
attribute at_string_1 : string ;
attribute at_t_rec1_1 : t_rec1 ;
attribute at_st_rec1_1 : st_rec1 ;
attribute at_t_rec2_1 : t_rec2 ;
attribute at_st_rec2_1 : st_rec2 ;
attribute at_t_rec3_1 : t_rec3 ;
attribute at_st_rec3_1 : st_rec3 ;
attribute at_t_arr1_1 : t_arr1 ;
attribute at_st_arr1_1 : st_arr1 ;
attribute at_t_arr2_1 : t_arr2 ;
attribute at_st_arr2_1 : st_arr2 ;
attribute at_t_arr3_1 : t_arr3 ;
attribute at_st_arr3_1 : st_arr3 ;
begin
process
variable correct : boolean := true ;
procedure p1 ;
attribute at_bit_vector_1 of p1 : procedure is
c_st_bit_vector_1 ;
attribute at_string_1 of p1 : procedure is
c_st_string_1 ;
attribute at_t_rec1_1 of p1 : procedure is
c_st_rec1_1 ;
attribute at_st_rec1_1 of p1 : procedure is
c_st_rec1_1 ;
attribute at_t_rec2_1 of p1 : procedure is
c_st_rec2_1 ;
attribute at_st_rec2_1 of p1 : procedure is
c_st_rec2_1 ;
attribute at_t_rec3_1 of p1 : procedure is
c_st_rec3_1 ;
attribute at_st_rec3_1 of p1 : procedure is
c_st_rec3_1 ;
attribute at_t_arr1_1 of p1 : procedure is
c_st_arr1_1 ;
attribute at_st_arr1_1 of p1 : procedure is
c_st_arr1_1 ;
attribute at_t_arr2_1 of p1 : procedure is
c_st_arr2_1 ;
attribute at_st_arr2_1 of p1 : procedure is
c_st_arr2_1 ;
attribute at_t_arr3_1 of p1 : procedure is
c_st_arr3_1 ;
attribute at_st_arr3_1 of p1 : procedure is
c_st_arr3_1 ;
procedure p1 is
begin
correct := correct and p1'at_bit_vector_1
= c_st_bit_vector_1 ;
correct := correct and p1'at_string_1
= c_st_string_1 ;
correct := correct and p1'at_t_rec1_1
= c_st_rec1_1 ;
correct := correct and p1'at_st_rec1_1
= c_st_rec1_1 ;
correct := correct and p1'at_t_rec2_1
= c_st_rec2_1 ;
correct := correct and p1'at_st_rec2_1
= c_st_rec2_1 ;
correct := correct and p1'at_t_rec3_1
= c_st_rec3_1 ;
correct := correct and p1'at_st_rec3_1
= c_st_rec3_1 ;
correct := correct and p1'at_t_arr1_1
= c_st_arr1_1 ;
correct := correct and p1'at_st_arr1_1
= c_st_arr1_1 ;
correct := correct and p1'at_t_arr2_1
= c_st_arr2_1 ;
correct := correct and p1'at_st_arr2_1
= c_st_arr2_1 ;
correct := correct and p1'at_t_arr3_1
= c_st_arr3_1 ;
correct := correct and p1'at_st_arr3_1
= c_st_arr3_1 ;
test_report ( "ARCH00569" ,
"Attribute declarations - composite generic subtypes"
& " with static initial values" ,
correct) ;
end p1 ;
begin
p1 ;
wait ;
end process ;
process
variable correct : boolean := true ;
procedure p1 ;
attribute at_bit_vector_1 of p1 : procedure is
i_bit_vector_1 ;
attribute at_string_1 of p1 : procedure is
i_string_1 ;
attribute at_t_rec1_1 of p1 : procedure is
i_t_rec1_1 ;
attribute at_st_rec1_1 of p1 : procedure is
i_st_rec1_1 ;
attribute at_t_rec2_1 of p1 : procedure is
i_t_rec2_1 ;
attribute at_st_rec2_1 of p1 : procedure is
i_st_rec2_1 ;
attribute at_t_rec3_1 of p1 : procedure is
i_t_rec3_1 ;
attribute at_st_rec3_1 of p1 : procedure is
i_st_rec3_1 ;
attribute at_t_arr1_1 of p1 : procedure is
i_t_arr1_1 ;
attribute at_st_arr1_1 of p1 : procedure is
i_st_arr1_1 ;
attribute at_t_arr2_1 of p1 : procedure is
i_t_arr2_1 ;
attribute at_st_arr2_1 of p1 : procedure is
i_st_arr2_1 ;
attribute at_t_arr3_1 of p1 : procedure is
i_t_arr3_1 ;
attribute at_st_arr3_1 of p1 : procedure is
i_st_arr3_1 ;
procedure p1 is
begin
correct := correct and p1'at_bit_vector_1
= c_st_bit_vector_1 ;
correct := correct and p1'at_string_1
= c_st_string_1 ;
correct := correct and p1'at_t_rec1_1
= c_st_rec1_1 ;
correct := correct and p1'at_st_rec1_1
= c_st_rec1_1 ;
correct := correct and p1'at_t_rec2_1
= c_st_rec2_1 ;
correct := correct and p1'at_st_rec2_1
= c_st_rec2_1 ;
correct := correct and p1'at_t_rec3_1
= c_st_rec3_1 ;
correct := correct and p1'at_st_rec3_1
= c_st_rec3_1 ;
correct := correct and p1'at_t_arr1_1
= c_st_arr1_1 ;
correct := correct and p1'at_st_arr1_1
= c_st_arr1_1 ;
correct := correct and p1'at_t_arr2_1
= c_st_arr2_1 ;
correct := correct and p1'at_st_arr2_1
= c_st_arr2_1 ;
correct := correct and p1'at_t_arr3_1
= c_st_arr3_1 ;
correct := correct and p1'at_st_arr3_1
= c_st_arr3_1 ;
test_report ( "ARCH00569" ,
"Attribute declarations - scalar generic subtypes"
& " with generic initial values" ,
correct) ;
end p1 ;
begin
p1 ;
wait ;
end process ;
end block B1 ;
end ARCH00569 ;
--
entity ENT00569_Test_Bench is
end ENT00569_Test_Bench ;
--
architecture ARCH00569_Test_Bench of ENT00569_Test_Bench is
begin
L1:
block
component UUT
end component ;
for CIS1 : UUT use entity WORK.GENERIC_STANDARD_TYPES ( ARCH00569 ) ;
begin
CIS1 : UUT ;
end block L1 ;
end ARCH00569_Test_Bench ;
| gpl-3.0 | e406a54b19be5f0644b146a2b44968dd | 0.475242 | 3.168049 | false | false | false | false |
grwlf/vsim | vhdl_ct/ct00393.vhd | 1 | 19,377 | -- NEED RESULT: ARCH00393.P1: Multi inertial transactions occurred on concurrent signal asg passed
-- NEED RESULT: ARCH00393.P2: Multi inertial transactions occurred on concurrent signal asg passed
-- NEED RESULT: ARCH00393.P3: Multi inertial transactions occurred on concurrent signal asg passed
-- NEED RESULT: ARCH00393: One inertial transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00393: One inertial transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00393: One inertial transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00393: Old transactions were removed on a concurrent signal asg passed
-- NEED RESULT: ARCH00393: Old transactions were removed on a concurrent signal asg passed
-- NEED RESULT: ARCH00393: Old transactions were removed on a concurrent signal asg passed
-- NEED RESULT: ARCH00393: One inertial transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00393: One inertial transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00393: One inertial transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00393: Inertial semantics check on a concurrent signal asg passed
-- NEED RESULT: ARCH00393: Inertial semantics check on a concurrent signal asg passed
-- NEED RESULT: ARCH00393: Inertial semantics check on a concurrent signal asg passed
-- NEED RESULT: P3: Inertial transactions completed entirely passed
-- NEED RESULT: P2: Inertial transactions completed entirely passed
-- NEED RESULT: P1: Inertial transactions completed entirely passed
-------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
-------------------------------------------------------------------------------
--
-- TEST NAME:
--
-- CT00393
--
-- AUTHOR:
--
-- G. Tominovich
--
-- TEST OBJECTIVES:
--
-- 9.5 (3)
-- 9.5.2 (1)
--
-- DESIGN UNIT ORDERING:
--
-- ENT00393(ARCH00393)
-- ENT00393_Test_Bench(ARCH00393_Test_Bench)
--
-- REVISION HISTORY:
--
-- 30-JUL-1987 - initial revision
--
-- NOTES:
--
-- self-checking
-- automatically generated
--
use WORK.STANDARD_TYPES.all ;
entity ENT00393 is
end ENT00393 ;
--
--
architecture ARCH00393 of ENT00393 is
subtype chk_sig_type is integer range -1 to 100 ;
signal chk_st_rec1 : chk_sig_type := -1 ;
signal chk_st_rec2 : chk_sig_type := -1 ;
signal chk_st_rec3 : chk_sig_type := -1 ;
--
subtype chk_time_type is Time ;
signal s_st_rec1_savt : chk_time_type := 0 ns ;
signal s_st_rec2_savt : chk_time_type := 0 ns ;
signal s_st_rec3_savt : chk_time_type := 0 ns ;
--
subtype chk_cnt_type is Integer ;
signal s_st_rec1_cnt : chk_cnt_type := 0 ;
signal s_st_rec2_cnt : chk_cnt_type := 0 ;
signal s_st_rec3_cnt : chk_cnt_type := 0 ;
--
type select_type is range 1 to 6 ;
signal st_rec1_select : select_type := 1 ;
signal st_rec2_select : select_type := 1 ;
signal st_rec3_select : select_type := 1 ;
--
signal s_st_rec1 : st_rec1
:= c_st_rec1_1 ;
signal s_st_rec2 : st_rec2
:= c_st_rec2_1 ;
signal s_st_rec3 : st_rec3
:= c_st_rec3_1 ;
--
begin
CHG1 :
process
variable correct : boolean ;
begin
case s_st_rec1_cnt is
when 0
=> null ;
-- s_st_rec1.f2 <=
-- c_st_rec1_2.f2 after 10 ns,
-- c_st_rec1_1.f2 after 20 ns ;
--
when 1
=> correct :=
s_st_rec1.f2 =
c_st_rec1_2.f2 and
(s_st_rec1_savt + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_rec1.f2 =
c_st_rec1_1.f2 and
(s_st_rec1_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00393.P1" ,
"Multi inertial transactions occurred on " &
"concurrent signal asg",
correct ) ;
--
st_rec1_select <= transport 2 ;
-- s_st_rec1.f2 <=
-- c_st_rec1_2.f2 after 10 ns ,
-- c_st_rec1_1.f2 after 20 ns ,
-- c_st_rec1_2.f2 after 30 ns ,
-- c_st_rec1_1.f2 after 40 ns ;
--
when 3
=> correct :=
s_st_rec1.f2 =
c_st_rec1_2.f2 and
(s_st_rec1_savt + 10 ns) = Std.Standard.Now ;
st_rec1_select <= transport 3 ;
-- s_st_rec1.f2 <=
-- c_st_rec1_1.f2 after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_rec1.f2 =
c_st_rec1_1.f2 and
(s_st_rec1_savt + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00393" ,
"One inertial transaction occurred on a " &
"concurrent signal asg",
correct ) ;
st_rec1_select <= transport 4 ;
-- s_st_rec1.f2 <=
-- c_st_rec1_1.f2 after 100 ns ;
--
when 5
=> correct :=
correct and
s_st_rec1.f2 =
c_st_rec1_1.f2 and
(s_st_rec1_savt + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00393" ,
"Old transactions were removed on a " &
"concurrent signal asg",
correct ) ;
st_rec1_select <= transport 5 ;
-- s_st_rec1.f2 <=
-- c_st_rec1_2.f2 after 10 ns ,
-- c_st_rec1_1.f2 after 20 ns ,
-- c_st_rec1_2.f2 after 30 ns ,
-- c_st_rec1_1.f2 after 40 ns ;
--
when 6
=> correct :=
correct and
s_st_rec1.f2 =
c_st_rec1_2.f2 and
(s_st_rec1_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00393" ,
"One inertial transaction occurred on a " &
"concurrent signal asg",
correct ) ;
st_rec1_select <= transport 6 ;
-- Last transaction above is marked
-- s_st_rec1.f2 <=
-- c_st_rec1_1.f2 after 40 ns ;
--
when 7
=> correct :=
correct and
s_st_rec1.f2 =
c_st_rec1_1.f2 and
(s_st_rec1_savt + 30 ns) = Std.Standard.Now ;
--
when 8
=> correct :=
correct and
s_st_rec1.f2 =
c_st_rec1_1.f2 and
(s_st_rec1_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00393" ,
"Inertial semantics check on a concurrent " &
"signal asg",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00393" ,
"Inertial semantics check on a concurrent " &
"signal asg",
false ) ;
--
end case ;
--
s_st_rec1_savt <= transport Std.Standard.Now ;
chk_st_rec1 <= transport s_st_rec1_cnt
after (1 us - Std.Standard.Now) ;
s_st_rec1_cnt <= transport s_st_rec1_cnt + 1 ;
wait until (not s_st_rec1.f2'Quiet) and
(s_st_rec1_savt /= Std.Standard.Now) ;
--
end process CHG1 ;
--
PGEN_CHKP_1 :
process ( chk_st_rec1 )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P1" ,
"Inertial transactions completed entirely",
chk_st_rec1 = 8 ) ;
end if ;
end process PGEN_CHKP_1 ;
--
--
with st_rec1_select select
s_st_rec1.f2 <=
c_st_rec1_2.f2 after 10 ns,
c_st_rec1_1.f2 after 20 ns
when 1,
--
c_st_rec1_2.f2 after 10 ns ,
c_st_rec1_1.f2 after 20 ns ,
c_st_rec1_2.f2 after 30 ns ,
c_st_rec1_1.f2 after 40 ns
when 2,
--
c_st_rec1_1.f2 after 5 ns
when 3,
--
c_st_rec1_1.f2 after 100 ns
when 4,
--
c_st_rec1_2.f2 after 10 ns ,
c_st_rec1_1.f2 after 20 ns ,
c_st_rec1_2.f2 after 30 ns ,
c_st_rec1_1.f2 after 40 ns
when 5,
--
-- Last transaction above is marked
c_st_rec1_1.f2 after 40 ns when 6 ;
--
CHG2 :
process
variable correct : boolean ;
begin
case s_st_rec2_cnt is
when 0
=> null ;
-- s_st_rec2.f2 <=
-- c_st_rec2_2.f2 after 10 ns,
-- c_st_rec2_1.f2 after 20 ns ;
--
when 1
=> correct :=
s_st_rec2.f2 =
c_st_rec2_2.f2 and
(s_st_rec2_savt + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_rec2.f2 =
c_st_rec2_1.f2 and
(s_st_rec2_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00393.P2" ,
"Multi inertial transactions occurred on " &
"concurrent signal asg",
correct ) ;
--
st_rec2_select <= transport 2 ;
-- s_st_rec2.f2 <=
-- c_st_rec2_2.f2 after 10 ns ,
-- c_st_rec2_1.f2 after 20 ns ,
-- c_st_rec2_2.f2 after 30 ns ,
-- c_st_rec2_1.f2 after 40 ns ;
--
when 3
=> correct :=
s_st_rec2.f2 =
c_st_rec2_2.f2 and
(s_st_rec2_savt + 10 ns) = Std.Standard.Now ;
st_rec2_select <= transport 3 ;
-- s_st_rec2.f2 <=
-- c_st_rec2_1.f2 after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_rec2.f2 =
c_st_rec2_1.f2 and
(s_st_rec2_savt + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00393" ,
"One inertial transaction occurred on a " &
"concurrent signal asg",
correct ) ;
st_rec2_select <= transport 4 ;
-- s_st_rec2.f2 <=
-- c_st_rec2_1.f2 after 100 ns ;
--
when 5
=> correct :=
correct and
s_st_rec2.f2 =
c_st_rec2_1.f2 and
(s_st_rec2_savt + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00393" ,
"Old transactions were removed on a " &
"concurrent signal asg",
correct ) ;
st_rec2_select <= transport 5 ;
-- s_st_rec2.f2 <=
-- c_st_rec2_2.f2 after 10 ns ,
-- c_st_rec2_1.f2 after 20 ns ,
-- c_st_rec2_2.f2 after 30 ns ,
-- c_st_rec2_1.f2 after 40 ns ;
--
when 6
=> correct :=
correct and
s_st_rec2.f2 =
c_st_rec2_2.f2 and
(s_st_rec2_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00393" ,
"One inertial transaction occurred on a " &
"concurrent signal asg",
correct ) ;
st_rec2_select <= transport 6 ;
-- Last transaction above is marked
-- s_st_rec2.f2 <=
-- c_st_rec2_1.f2 after 40 ns ;
--
when 7
=> correct :=
correct and
s_st_rec2.f2 =
c_st_rec2_1.f2 and
(s_st_rec2_savt + 30 ns) = Std.Standard.Now ;
--
when 8
=> correct :=
correct and
s_st_rec2.f2 =
c_st_rec2_1.f2 and
(s_st_rec2_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00393" ,
"Inertial semantics check on a concurrent " &
"signal asg",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00393" ,
"Inertial semantics check on a concurrent " &
"signal asg",
false ) ;
--
end case ;
--
s_st_rec2_savt <= transport Std.Standard.Now ;
chk_st_rec2 <= transport s_st_rec2_cnt
after (1 us - Std.Standard.Now) ;
s_st_rec2_cnt <= transport s_st_rec2_cnt + 1 ;
wait until (not s_st_rec2.f2'Quiet) and
(s_st_rec2_savt /= Std.Standard.Now) ;
--
end process CHG2 ;
--
PGEN_CHKP_2 :
process ( chk_st_rec2 )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P2" ,
"Inertial transactions completed entirely",
chk_st_rec2 = 8 ) ;
end if ;
end process PGEN_CHKP_2 ;
--
--
with st_rec2_select select
s_st_rec2.f2 <=
c_st_rec2_2.f2 after 10 ns,
c_st_rec2_1.f2 after 20 ns
when 1,
--
c_st_rec2_2.f2 after 10 ns ,
c_st_rec2_1.f2 after 20 ns ,
c_st_rec2_2.f2 after 30 ns ,
c_st_rec2_1.f2 after 40 ns
when 2,
--
c_st_rec2_1.f2 after 5 ns
when 3,
--
c_st_rec2_1.f2 after 100 ns
when 4,
--
c_st_rec2_2.f2 after 10 ns ,
c_st_rec2_1.f2 after 20 ns ,
c_st_rec2_2.f2 after 30 ns ,
c_st_rec2_1.f2 after 40 ns
when 5,
--
-- Last transaction above is marked
c_st_rec2_1.f2 after 40 ns when 6 ;
--
CHG3 :
process
variable correct : boolean ;
begin
case s_st_rec3_cnt is
when 0
=> null ;
-- s_st_rec3.f2 <=
-- c_st_rec3_2.f2 after 10 ns,
-- c_st_rec3_1.f2 after 20 ns ;
--
when 1
=> correct :=
s_st_rec3.f2 =
c_st_rec3_2.f2 and
(s_st_rec3_savt + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_rec3.f2 =
c_st_rec3_1.f2 and
(s_st_rec3_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00393.P3" ,
"Multi inertial transactions occurred on " &
"concurrent signal asg",
correct ) ;
--
st_rec3_select <= transport 2 ;
-- s_st_rec3.f2 <=
-- c_st_rec3_2.f2 after 10 ns ,
-- c_st_rec3_1.f2 after 20 ns ,
-- c_st_rec3_2.f2 after 30 ns ,
-- c_st_rec3_1.f2 after 40 ns ;
--
when 3
=> correct :=
s_st_rec3.f2 =
c_st_rec3_2.f2 and
(s_st_rec3_savt + 10 ns) = Std.Standard.Now ;
st_rec3_select <= transport 3 ;
-- s_st_rec3.f2 <=
-- c_st_rec3_1.f2 after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_rec3.f2 =
c_st_rec3_1.f2 and
(s_st_rec3_savt + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00393" ,
"One inertial transaction occurred on a " &
"concurrent signal asg",
correct ) ;
st_rec3_select <= transport 4 ;
-- s_st_rec3.f2 <=
-- c_st_rec3_1.f2 after 100 ns ;
--
when 5
=> correct :=
correct and
s_st_rec3.f2 =
c_st_rec3_1.f2 and
(s_st_rec3_savt + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00393" ,
"Old transactions were removed on a " &
"concurrent signal asg",
correct ) ;
st_rec3_select <= transport 5 ;
-- s_st_rec3.f2 <=
-- c_st_rec3_2.f2 after 10 ns ,
-- c_st_rec3_1.f2 after 20 ns ,
-- c_st_rec3_2.f2 after 30 ns ,
-- c_st_rec3_1.f2 after 40 ns ;
--
when 6
=> correct :=
correct and
s_st_rec3.f2 =
c_st_rec3_2.f2 and
(s_st_rec3_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00393" ,
"One inertial transaction occurred on a " &
"concurrent signal asg",
correct ) ;
st_rec3_select <= transport 6 ;
-- Last transaction above is marked
-- s_st_rec3.f2 <=
-- c_st_rec3_1.f2 after 40 ns ;
--
when 7
=> correct :=
correct and
s_st_rec3.f2 =
c_st_rec3_1.f2 and
(s_st_rec3_savt + 30 ns) = Std.Standard.Now ;
--
when 8
=> correct :=
correct and
s_st_rec3.f2 =
c_st_rec3_1.f2 and
(s_st_rec3_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00393" ,
"Inertial semantics check on a concurrent " &
"signal asg",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00393" ,
"Inertial semantics check on a concurrent " &
"signal asg",
false ) ;
--
end case ;
--
s_st_rec3_savt <= transport Std.Standard.Now ;
chk_st_rec3 <= transport s_st_rec3_cnt
after (1 us - Std.Standard.Now) ;
s_st_rec3_cnt <= transport s_st_rec3_cnt + 1 ;
wait until (not s_st_rec3.f2'Quiet) and
(s_st_rec3_savt /= Std.Standard.Now) ;
--
end process CHG3 ;
--
PGEN_CHKP_3 :
process ( chk_st_rec3 )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P3" ,
"Inertial transactions completed entirely",
chk_st_rec3 = 8 ) ;
end if ;
end process PGEN_CHKP_3 ;
--
--
with st_rec3_select select
s_st_rec3.f2 <=
c_st_rec3_2.f2 after 10 ns,
c_st_rec3_1.f2 after 20 ns
when 1,
--
c_st_rec3_2.f2 after 10 ns ,
c_st_rec3_1.f2 after 20 ns ,
c_st_rec3_2.f2 after 30 ns ,
c_st_rec3_1.f2 after 40 ns
when 2,
--
c_st_rec3_1.f2 after 5 ns
when 3,
--
c_st_rec3_1.f2 after 100 ns
when 4,
--
c_st_rec3_2.f2 after 10 ns ,
c_st_rec3_1.f2 after 20 ns ,
c_st_rec3_2.f2 after 30 ns ,
c_st_rec3_1.f2 after 40 ns
when 5,
--
-- Last transaction above is marked
c_st_rec3_1.f2 after 40 ns when 6 ;
--
end ARCH00393 ;
--
--
use WORK.STANDARD_TYPES.all ;
entity ENT00393_Test_Bench is
end ENT00393_Test_Bench ;
--
--
architecture ARCH00393_Test_Bench of ENT00393_Test_Bench is
begin
L1:
block
component UUT
end component ;
--
for CIS1 : UUT use entity WORK.ENT00393 ( ARCH00393 ) ;
begin
CIS1 : UUT
;
end block L1 ;
end ARCH00393_Test_Bench ;
| gpl-3.0 | ae98a73fcd39201178cbb1171f7c2fc1 | 0.468803 | 3.376961 | false | true | false | false |
jairov4/accel-oil | solution_kintex7/sim/vhdl/nfa_accept_samples_generic_hw_mul_16ns_8ns_24_4.vhd | 1 | 2,906 | -- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2013.4
-- Copyright (C) 2013 Xilinx Inc. All rights reserved.
--
-- ==============================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity nfa_accept_samples_generic_hw_mul_16ns_8ns_24_4_MAC4S_0 is
port (
clk: in std_logic;
ce: in std_logic;
a: in std_logic_vector(16 - 1 downto 0);
b: in std_logic_vector(8 - 1 downto 0);
p: out std_logic_vector(24 - 1 downto 0));
end entity;
architecture behav of nfa_accept_samples_generic_hw_mul_16ns_8ns_24_4_MAC4S_0 is
signal tmp_product : std_logic_vector(24 - 1 downto 0);
signal a_i : std_logic_vector(16 - 1 downto 0);
signal b_i : std_logic_vector(8 - 1 downto 0);
signal p_tmp : std_logic_vector(24 - 1 downto 0);
signal a_reg : std_logic_vector(16 - 1 downto 0);
signal b_reg : std_logic_vector(8 - 1 downto 0);
attribute keep : string;
attribute keep of a_i : signal is "true";
attribute keep of b_i : signal is "true";
signal buff0 : std_logic_vector(24 - 1 downto 0);
signal buff1 : std_logic_vector(24 - 1 downto 0);
begin
a_i <= a;
b_i <= b;
p <= p_tmp;
p_tmp <= buff1;
tmp_product <= std_logic_vector(resize(unsigned(a_reg) * unsigned(b_reg), 24));
process(clk)
begin
if (clk'event and clk = '1') then
if (ce = '1') then
a_reg <= a_i;
b_reg <= b_i;
buff0 <= tmp_product;
buff1 <= buff0;
end if;
end if;
end process;
end architecture;
Library IEEE;
use IEEE.std_logic_1164.all;
entity nfa_accept_samples_generic_hw_mul_16ns_8ns_24_4 is
generic (
ID : INTEGER;
NUM_STAGE : INTEGER;
din0_WIDTH : INTEGER;
din1_WIDTH : INTEGER;
dout_WIDTH : INTEGER);
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
ce : IN STD_LOGIC;
din0 : IN STD_LOGIC_VECTOR(din0_WIDTH - 1 DOWNTO 0);
din1 : IN STD_LOGIC_VECTOR(din1_WIDTH - 1 DOWNTO 0);
dout : OUT STD_LOGIC_VECTOR(dout_WIDTH - 1 DOWNTO 0));
end entity;
architecture arch of nfa_accept_samples_generic_hw_mul_16ns_8ns_24_4 is
component nfa_accept_samples_generic_hw_mul_16ns_8ns_24_4_MAC4S_0 is
port (
clk : IN STD_LOGIC;
ce : IN STD_LOGIC;
a : IN STD_LOGIC_VECTOR;
b : IN STD_LOGIC_VECTOR;
p : OUT STD_LOGIC_VECTOR);
end component;
begin
nfa_accept_samples_generic_hw_mul_16ns_8ns_24_4_MAC4S_0_U : component nfa_accept_samples_generic_hw_mul_16ns_8ns_24_4_MAC4S_0
port map (
clk => clk,
ce => ce,
a => din0,
b => din1,
p => dout);
end architecture;
| lgpl-3.0 | 7d445a2d64b9b55046494be41e4b1ffa | 0.560564 | 3.193407 | false | false | false | false |
MrDoomBringer/DSD-Labs | Lab 6/alu.vhd | 1 | 7,804 | LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
USE ieee.std_logic_signed.ALL;
ENTITY quad_bit_alu IS
port(
a: IN SIGNED (3 DOWNTO 0); -- Arith input A
b: IN SIGNED (3 DOWNTO 0); -- Arith input B
s: IN UNSIGNED (2 DOWNTO 0); -- Arith Op Select
HEX0 : OUT STD_LOGIC_VECTOR (6 DOWNTO 0);
HEX1 : OUT STD_LOGIC_VECTOR (6 DOWNTO 0);
HEX2 : OUT STD_LOGIC_VECTOR (6 DOWNTO 0)
);
END quad_bit_alu;
ARCHITECTURE alu OF quad_bit_alu IS
-- Hex display constants
CONSTANT hex_blk : STD_LOGIC_VECTOR (6 DOWNTO 0) := "1111111";
CONSTANT hex_neg : STD_LOGIC_VECTOR (6 DOWNTO 0) := "0111111";
CONSTANT hex_zer : STD_LOGIC_VECTOR (6 DOWNTO 0) := "1000000";
CONSTANT hex_one : STD_LOGIC_VECTOR (6 DOWNTO 0) := "1111001";
CONSTANT hex_two : STD_LOGIC_VECTOR (6 DOWNTO 0) := "0100100";
CONSTANT hex_thr : STD_LOGIC_VECTOR (6 DOWNTO 0) := "0110000";
CONSTANT hex_fou : STD_LOGIC_VECTOR (6 DOWNTO 0) := "0011001";
CONSTANT hex_fiv : STD_LOGIC_VECTOR (6 DOWNTO 0) := "0010010";
CONSTANT hex_six : STD_LOGIC_VECTOR (6 DOWNTO 0) := "0000010";
CONSTANT hex_sev : STD_LOGIC_VECTOR (6 DOWNTO 0) := "1111000";
CONSTANT hex_eig : STD_LOGIC_VECTOR (6 DOWNTO 0) := "0000000";
CONSTANT hex_nin : STD_LOGIC_VECTOR (6 DOWNTO 0) := "0011000";
CONSTANT hex_0xa : STD_LOGIC_VECTOR (6 DOWNTO 0) := "0001000";
CONSTANT hex_0xb : STD_LOGIC_VECTOR (6 DOWNTO 0) := "0000011";
CONSTANT hex_0xc : STD_LOGIC_VECTOR (6 DOWNTO 0) := "1000110";
CONSTANT hex_0xd : STD_LOGIC_VECTOR (6 DOWNTO 0) := "0100001";
CONSTANT hex_0xe : STD_LOGIC_VECTOR (6 DOWNTO 0) := "0000110";
CONSTANT hex_0xf : STD_LOGIC_VECTOR (6 DOWNTO 0) := "0001110";
-- HEX buffers for hex displays
SIGNAL HEX0_buff_hex : STD_LOGIC_VECTOR (6 DOWNTO 0);
SIGNAL HEX1_buff_hex : STD_LOGIC_VECTOR (6 DOWNTO 0);
SIGNAL HEX2_buff_hex : STD_LOGIC_VECTOR (6 DOWNTO 0);
-- DEC buffers for hex displays
SIGNAL HEX0_buff_dec : STD_LOGIC_VECTOR (6 DOWNTO 0);
SIGNAL HEX1_buff_dec : STD_LOGIC_VECTOR (6 DOWNTO 0);
SIGNAL HEX2_buff_dec : STD_LOGIC_VECTOR (6 DOWNTO 0);
-- Padded variables
SIGNAL a_pad: SIGNED (7 DOWNTO 0);
SIGNAL b_pad: SIGNED (7 DOWNTO 0);
-- Temp buffer for result value
SIGNAL r_buff: STD_LOGIC_VECTOR (7 DOWNTO 0);
BEGIN
-- Pad A
pad_a: PROCESS(a)
VARIABLE sign : std_logic;
BEGIN
sign:= a(3);
IF (sign = '0') THEN
a_pad <= ("0000" & a);
ELSIF (sign = '1') THEN
a_pad <= ("1111" & a);
ELSE
a_pad <= "00000000";
END IF;
END PROCESS pad_a;
-- Pad B
pad_b: PROCESS(b)
VARIABLE sign : std_logic;
BEGIN
sign:= b(3);
IF (sign = '0') THEN
b_pad <= ("0000" & b);
ELSIF (sign = '1') THEN
b_pad <= ("1111" & b);
ELSE
b_pad <= "00000000";
END IF;
END PROCESS pad_b;
-- Main ALU process
op_select: PROCESS(s, a_pad, b_pad, a, b)
BEGIN
CASE s IS
WHEN "000" => r_buff <= STD_LOGIC_VECTOR(a_pad AND b_pad);
WHEN "001" => r_buff <= STD_LOGIC_VECTOR(a_pad OR b_pad);
WHEN "010" => r_buff <= STD_LOGIC_VECTOR(a_pad XOR b_pad);
WHEN "011" => r_buff <= STD_LOGIC_VECTOR(NOT a_pad);
WHEN "100" => r_buff <= STD_LOGIC_VECTOR(a_pad + b_pad);
WHEN "101" => r_buff <= STD_LOGIC_VECTOR(a_pad - b_pad);
WHEN "110" => r_buff <= STD_LOGIC_VECTOR(a * b);
WHEN "111" => r_buff <= STD_LOGIC_VECTOR(NOT(a_pad) + "00000001");
WHEN OTHERS => r_buff <= "00000000";
END CASE;
END PROCESS op_select;
-- Generate a hex display
display_hex : PROCESS (r_buff)
ALIAS high_bit : STD_LOGIC_VECTOR (3 DOWNTO 0) IS r_buff (7 DOWNTO 4);
ALIAS low_bit : STD_LOGIC_VECTOR (3 DOWNTO 0) IS r_buff (3 DOWNTO 0);
BEGIN
CASE high_bit IS
WHEN "0000" => HEX1_buff_hex <= hex_zer;
WHEN "0001" => HEX1_buff_hex <= hex_one;
WHEN "0010" => HEX1_buff_hex <= hex_two;
WHEN "0011" => HEX1_buff_hex <= hex_thr;
WHEN "0100" => HEX1_buff_hex <= hex_fou;
WHEN "0101" => HEX1_buff_hex <= hex_fiv;
WHEN "0110" => HEX1_buff_hex <= hex_six;
WHEN "0111" => HEX1_buff_hex <= hex_sev;
WHEN "1000" => HEX1_buff_hex <= hex_eig;
WHEN "1001" => HEX1_buff_hex <= hex_nin;
WHEN "1010" => HEX1_buff_hex <= hex_0xa;
WHEN "1011" => HEX1_buff_hex <= hex_0xb;
WHEN "1100" => HEX1_buff_hex <= hex_0xc;
WHEN "1101" => HEX1_buff_hex <= hex_0xd;
WHEN "1110" => HEX1_buff_hex <= hex_0xe;
WHEN "1111" => HEX1_buff_hex <= hex_0xf;
WHEN OTHERS => HEX1_buff_hex <= hex_blk;
END CASE;
CASE low_bit IS
WHEN "0000" => HEX2_buff_hex <= hex_zer;
WHEN "0001" => HEX2_buff_hex <= hex_one;
WHEN "0010" => HEX2_buff_hex <= hex_two;
WHEN "0011" => HEX2_buff_hex <= hex_thr;
WHEN "0100" => HEX2_buff_hex <= hex_fou;
WHEN "0101" => HEX2_buff_hex <= hex_fiv;
WHEN "0110" => HEX2_buff_hex <= hex_six;
WHEN "0111" => HEX2_buff_hex <= hex_sev;
WHEN "1000" => HEX2_buff_hex <= hex_eig;
WHEN "1001" => HEX2_buff_hex <= hex_nin;
WHEN "1010" => HEX2_buff_hex <= hex_0xa;
WHEN "1011" => HEX2_buff_hex <= hex_0xb;
WHEN "1100" => HEX2_buff_hex <= hex_0xc;
WHEN "1101" => HEX2_buff_hex <= hex_0xd;
WHEN "1110" => HEX2_buff_hex <= hex_0xe;
WHEN "1111" => HEX2_buff_hex <= hex_0xf;
WHEN OTHERS => HEX2_buff_hex <= hex_blk;
END CASE;
END PROCESS display_hex;
-- Generate a decimal display
display_dec: PROCESS (r_buff)
ALIAS sign_bit : STD_LOGIC IS r_buff (7);
VARIABLE r_lower: STD_LOGIC_VECTOR (7 DOWNTO 0);
VARIABLE r_buff_int : STD_LOGIC_VECTOR (7 DOWNTO 0);
BEGIN
-- Select value to work off of
IF (sign_bit='1') THEN
HEX0_buff_dec <= hex_neg;
r_buff_int := (NOT(r_buff) + "00000001");
ELSIF (sign_bit='0') THEN
HEX0_buff_dec <= hex_blk;
r_buff_int := r_buff;
ELSE
HEX0_buff_dec <= hex_blk;
r_buff_int := "00000000";
END IF;
-- Display higher digit
IF (r_buff_int >= "00001010" AND r_buff_int < "00010100") THEN -- Within 10-19
HEX1_buff_dec <= hex_one;
r_lower := r_buff_int - "00001010";
ELSIF (r_buff_int >= "00010100" AND r_buff_int < "00011110") THEN -- Within 20-29
HEX1_buff_dec <= hex_two;
r_lower := r_buff_int - "00010100";
ELSIF (r_buff_int >= "00011110" AND r_buff_int < "00101000") THEN -- Within 30-39
HEX1_buff_dec <= hex_thr;
r_lower := r_buff_int - "00011110";
ELSIF (r_buff_int >= "00101000" AND r_buff_int < "00110010") THEN -- Within 40-49
HEX1_buff_dec <= hex_fou;
r_lower := r_buff_int - "00101000";
ELSIF (r_buff_int >= "00110010" AND r_buff_int < "00111100") THEN -- Within 50-59
HEX1_buff_dec <= hex_fiv;
r_lower := r_buff_int - "00110010";
ELSIF (r_buff_int >= "00111100" AND r_buff_int < "01000110") THEN -- Within 60-69
HEX1_buff_dec <= hex_six;
r_lower := r_buff_int - "00111100";
ELSE -- We can't have any higher values from our ALU, everything else must be zero.
HEX1_buff_dec <= hex_zer;
r_lower := r_buff_int;
END IF;
-- Display lower digit
CASE r_lower IS
WHEN "00000000" => HEX2_buff_dec <= hex_zer;
WHEN "00000001" => HEX2_buff_dec <= hex_one;
WHEN "00000010" => HEX2_buff_dec <= hex_two;
WHEN "00000011" => HEX2_buff_dec <= hex_thr;
WHEN "00000100" => HEX2_buff_dec <= hex_fou;
WHEN "00000101" => HEX2_buff_dec <= hex_fiv;
WHEN "00000110" => HEX2_buff_dec <= hex_six;
WHEN "00000111" => HEX2_buff_dec <= hex_sev;
WHEN "00001000" => HEX2_buff_dec <= hex_eig;
WHEN "00001001" => HEX2_buff_dec <= hex_nin;
WHEN OTHERS => HEX2_buff_dec <= hex_zer;
END CASE;
END PROCESS display_dec;
-- Select display type for output
select_display : PROCESS (s, HEX0_buff_hex, HEX1_buff_hex, HEX2_buff_hex, HEX0_buff_dec, HEX1_buff_dec, HEX2_buff_dec)
BEGIN
IF (s <= "011") THEN
HEX0 <= hex_blk;
HEX1 <= HEX1_buff_hex;
HEX2 <= HEX2_buff_hex;
ELSE
HEX0 <= HEX0_buff_dec;
HEX1 <= HEX1_buff_dec;
HEX2 <= HEX2_buff_dec;
END IF;
END PROCESS select_display;
END alu; | mit | 40b0866eb7a613f48ab044b7e3d671fb | 0.617119 | 2.631153 | false | false | false | false |
grwlf/vsim | vhdl_ct/ct00252.vhd | 1 | 4,751 | -- NEED RESULT: ENT00252: Open scalar buffer ports with static subtypes passed
-------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
-------------------------------------------------------------------------------
--
-- TEST NAME:
--
-- CT00252
--
-- AUTHOR:
--
-- A. Wilmot
--
-- TEST OBJECTIVES:
--
-- 1.1.1.2 (3)
--
-- DESIGN UNIT ORDERING:
--
-- ENT00252(ARCH00252)
-- ENT00252_Test_Bench(ARCH00252_Test_Bench)
--
-- REVISION HISTORY:
--
-- 25-JUN-1987 - initial revision
--
-- NOTES:
--
-- self-checking
-- automatically generated
--
use WORK.STANDARD_TYPES.all ;
entity ENT00252 is
port (
toggle : buffer switch ;
i_boolean_1, i_boolean_2 : buffer boolean
:= c_boolean_1
;
i_bit_1, i_bit_2 : buffer bit
:= c_bit_1
;
i_severity_level_1, i_severity_level_2 : buffer severity_level
:= c_severity_level_1
;
i_character_1, i_character_2 : buffer character
:= c_character_1
;
i_t_enum1_1, i_t_enum1_2 : buffer t_enum1
:= c_t_enum1_1
;
i_st_enum1_1, i_st_enum1_2 : buffer st_enum1
:= c_st_enum1_1
;
i_integer_1, i_integer_2 : buffer integer
:= c_integer_1
;
i_t_int1_1, i_t_int1_2 : buffer t_int1
:= c_t_int1_1
;
i_st_int1_1, i_st_int1_2 : buffer st_int1
:= c_st_int1_1
;
i_time_1, i_time_2 : buffer time
:= c_time_1
;
i_t_phys1_1, i_t_phys1_2 : buffer t_phys1
:= c_t_phys1_1
;
i_st_phys1_1, i_st_phys1_2 : buffer st_phys1
:= c_st_phys1_1
;
i_real_1, i_real_2 : buffer real
:= c_real_1
;
i_t_real1_1, i_t_real1_2 : buffer t_real1
:= c_t_real1_1
;
i_st_real1_1, i_st_real1_2 : buffer st_real1
:= c_st_real1_1
) ;
begin
end ENT00252 ;
--
architecture ARCH00252 of ENT00252 is
begin
process
variable correct : boolean := true ;
begin
--
toggle <= up ;
i_boolean_1 <= c_boolean_2 ;
i_boolean_2 <= c_boolean_2 ;
i_bit_1 <= c_bit_2 ;
i_bit_2 <= c_bit_2 ;
i_severity_level_1 <= c_severity_level_2 ;
i_severity_level_2 <= c_severity_level_2 ;
i_character_1 <= c_character_2 ;
i_character_2 <= c_character_2 ;
i_t_enum1_1 <= c_t_enum1_2 ;
i_t_enum1_2 <= c_t_enum1_2 ;
i_st_enum1_1 <= c_st_enum1_2 ;
i_st_enum1_2 <= c_st_enum1_2 ;
i_integer_1 <= c_integer_2 ;
i_integer_2 <= c_integer_2 ;
i_t_int1_1 <= c_t_int1_2 ;
i_t_int1_2 <= c_t_int1_2 ;
i_st_int1_1 <= c_st_int1_2 ;
i_st_int1_2 <= c_st_int1_2 ;
i_time_1 <= c_time_2 ;
i_time_2 <= c_time_2 ;
i_t_phys1_1 <= c_t_phys1_2 ;
i_t_phys1_2 <= c_t_phys1_2 ;
i_st_phys1_1 <= c_st_phys1_2 ;
i_st_phys1_2 <= c_st_phys1_2 ;
i_real_1 <= c_real_2 ;
i_real_2 <= c_real_2 ;
i_t_real1_1 <= c_t_real1_2 ;
i_t_real1_2 <= c_t_real1_2 ;
i_st_real1_1 <= c_st_real1_2 ;
i_st_real1_2 <= c_st_real1_2 ;
test_report ( "ENT00252" ,
"Open scalar buffer ports with static subtypes" ,
correct) ;
wait ;
end process ;
end ARCH00252 ;
--
use WORK.STANDARD_TYPES.all ;
entity ENT00252_Test_Bench is
end ENT00252_Test_Bench ;
--
architecture ARCH00252_Test_Bench of ENT00252_Test_Bench is
begin
L1:
block
--
signal toggle : switch ;
--
component UUT
end component ;
--
for CIS1 : UUT use entity WORK.ENT00252 ( ARCH00252 )
port map (
toggle ,
open, open,
open, open,
open, open,
open, open,
open, open,
open, open,
open, open,
open, open,
open, open,
open, open,
open, open,
open, open,
open, open,
open, open,
open, open
) ;
--
begin
CIS1 : UUT ;
end block L1 ;
end ARCH00252_Test_Bench ;
| gpl-3.0 | 6f2ad3665bdc1bac9de0cb7bb2060298 | 0.425595 | 3.156811 | false | true | false | false |
grwlf/vsim | vhdl_ct/ct00337.vhd | 1 | 63,653 | -- NEED RESULT: ARCH00337.P1: Multi transport transactions occurred on concurrent signal asg passed
-- NEED RESULT: ARCH00337.P2: Multi transport transactions occurred on concurrent signal asg passed
-- NEED RESULT: ARCH00337.P3: Multi transport transactions occurred on concurrent signal asg passed
-- NEED RESULT: ARCH00337.P4: Multi transport transactions occurred on concurrent signal asg passed
-- NEED RESULT: ARCH00337.P5: Multi transport transactions occurred on concurrent signal asg passed
-- NEED RESULT: ARCH00337.P6: Multi transport transactions occurred on concurrent signal asg passed
-- NEED RESULT: ARCH00337.P7: Multi transport transactions occurred on concurrent signal asg passed
-- NEED RESULT: ARCH00337.P8: Multi transport transactions occurred on concurrent signal asg passed
-- NEED RESULT: ARCH00337.P9: Multi transport transactions occurred on concurrent signal asg passed
-- NEED RESULT: ARCH00337.P10: Multi transport transactions occurred on concurrent signal asg passed
-- NEED RESULT: ARCH00337.P11: Multi transport transactions occurred on concurrent signal asg passed
-- NEED RESULT: ARCH00337.P12: Multi transport transactions occurred on concurrent signal asg passed
-- NEED RESULT: ARCH00337.P13: Multi transport transactions occurred on concurrent signal asg passed
-- NEED RESULT: ARCH00337.P14: Multi transport transactions occurred on concurrent signal asg passed
-- NEED RESULT: ARCH00337.P15: Multi transport transactions occurred on concurrent signal asg passed
-- NEED RESULT: ARCH00337.P16: Multi transport transactions occurred on concurrent signal asg passed
-- NEED RESULT: ARCH00337.P17: Multi transport transactions occurred on concurrent signal asg passed
-- NEED RESULT: ARCH00337: One transport transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00337: Old transactions were removed on a concurrent signal asg passed
-- NEED RESULT: ARCH00337: One transport transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00337: Old transactions were removed on a concurrent signal asg passed
-- NEED RESULT: ARCH00337: One transport transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00337: Old transactions were removed on a concurrent signal asg passed
-- NEED RESULT: ARCH00337: One transport transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00337: Old transactions were removed on a concurrent signal asg passed
-- NEED RESULT: ARCH00337: One transport transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00337: Old transactions were removed on a concurrent signal asg passed
-- NEED RESULT: ARCH00337: One transport transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00337: Old transactions were removed on a concurrent signal asg passed
-- NEED RESULT: ARCH00337: One transport transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00337: Old transactions were removed on a concurrent signal asg passed
-- NEED RESULT: ARCH00337: One transport transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00337: Old transactions were removed on a concurrent signal asg passed
-- NEED RESULT: ARCH00337: One transport transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00337: Old transactions were removed on a concurrent signal asg passed
-- NEED RESULT: ARCH00337: One transport transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00337: Old transactions were removed on a concurrent signal asg passed
-- NEED RESULT: ARCH00337: One transport transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00337: Old transactions were removed on a concurrent signal asg passed
-- NEED RESULT: ARCH00337: One transport transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00337: Old transactions were removed on a concurrent signal asg passed
-- NEED RESULT: ARCH00337: One transport transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00337: Old transactions were removed on a concurrent signal asg passed
-- NEED RESULT: ARCH00337: One transport transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00337: Old transactions were removed on a concurrent signal asg passed
-- NEED RESULT: ARCH00337: One transport transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00337: Old transactions were removed on a concurrent signal asg passed
-- NEED RESULT: ARCH00337: One transport transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00337: Old transactions were removed on a concurrent signal asg passed
-- NEED RESULT: ARCH00337: One transport transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00337: Old transactions were removed on a concurrent signal asg passed
-- NEED RESULT: P17: Transport transactions completed entirely passed
-- NEED RESULT: P16: Transport transactions completed entirely passed
-- NEED RESULT: P15: Transport transactions completed entirely passed
-- NEED RESULT: P14: Transport transactions completed entirely passed
-- NEED RESULT: P13: Transport transactions completed entirely passed
-- NEED RESULT: P12: Transport transactions completed entirely passed
-- NEED RESULT: P11: Transport transactions completed entirely passed
-- NEED RESULT: P10: Transport transactions completed entirely passed
-- NEED RESULT: P9: Transport transactions completed entirely passed
-- NEED RESULT: P8: Transport transactions completed entirely passed
-- NEED RESULT: P7: Transport transactions completed entirely passed
-- NEED RESULT: P6: Transport transactions completed entirely passed
-- NEED RESULT: P5: Transport transactions completed entirely passed
-- NEED RESULT: P4: Transport transactions completed entirely passed
-- NEED RESULT: P3: Transport transactions completed entirely passed
-- NEED RESULT: P2: Transport transactions completed entirely passed
-- NEED RESULT: P1: Transport transactions completed entirely passed
-------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
-------------------------------------------------------------------------------
--
-- TEST NAME:
--
-- CT00337
--
-- AUTHOR:
--
-- G. Tominovich
--
-- TEST OBJECTIVES:
--
-- 9.5 (2)
-- 9.5.1 (1)
-- 9.5.1 (2)
--
-- DESIGN UNIT ORDERING:
--
-- ENT00337(ARCH00337)
-- ENT00337_Test_Bench(ARCH00337_Test_Bench)
--
-- REVISION HISTORY:
--
-- 30-JUL-1987 - initial revision
--
-- NOTES:
--
-- self-checking
-- automatically generated
--
use WORK.STANDARD_TYPES.all ;
entity ENT00337 is
end ENT00337 ;
--
--
architecture ARCH00337 of ENT00337 is
subtype chk_sig_type is integer range -1 to 100 ;
signal chk_boolean : chk_sig_type := -1 ;
signal chk_bit : chk_sig_type := -1 ;
signal chk_severity_level : chk_sig_type := -1 ;
signal chk_character : chk_sig_type := -1 ;
signal chk_st_enum1 : chk_sig_type := -1 ;
signal chk_integer : chk_sig_type := -1 ;
signal chk_st_int1 : chk_sig_type := -1 ;
signal chk_time : chk_sig_type := -1 ;
signal chk_st_phys1 : chk_sig_type := -1 ;
signal chk_real : chk_sig_type := -1 ;
signal chk_st_real1 : chk_sig_type := -1 ;
signal chk_st_rec1 : chk_sig_type := -1 ;
signal chk_st_rec2 : chk_sig_type := -1 ;
signal chk_st_rec3 : chk_sig_type := -1 ;
signal chk_st_arr1 : chk_sig_type := -1 ;
signal chk_st_arr2 : chk_sig_type := -1 ;
signal chk_st_arr3 : chk_sig_type := -1 ;
--
subtype chk_time_type is Time ;
signal s_boolean_savt : chk_time_type := 0 ns ;
signal s_bit_savt : chk_time_type := 0 ns ;
signal s_severity_level_savt : chk_time_type := 0 ns ;
signal s_character_savt : chk_time_type := 0 ns ;
signal s_st_enum1_savt : chk_time_type := 0 ns ;
signal s_integer_savt : chk_time_type := 0 ns ;
signal s_st_int1_savt : chk_time_type := 0 ns ;
signal s_time_savt : chk_time_type := 0 ns ;
signal s_st_phys1_savt : chk_time_type := 0 ns ;
signal s_real_savt : chk_time_type := 0 ns ;
signal s_st_real1_savt : chk_time_type := 0 ns ;
signal s_st_rec1_savt : chk_time_type := 0 ns ;
signal s_st_rec2_savt : chk_time_type := 0 ns ;
signal s_st_rec3_savt : chk_time_type := 0 ns ;
signal s_st_arr1_savt : chk_time_type := 0 ns ;
signal s_st_arr2_savt : chk_time_type := 0 ns ;
signal s_st_arr3_savt : chk_time_type := 0 ns ;
--
subtype chk_cnt_type is Integer ;
signal s_boolean_cnt : chk_cnt_type := 0 ;
signal s_bit_cnt : chk_cnt_type := 0 ;
signal s_severity_level_cnt : chk_cnt_type := 0 ;
signal s_character_cnt : chk_cnt_type := 0 ;
signal s_st_enum1_cnt : chk_cnt_type := 0 ;
signal s_integer_cnt : chk_cnt_type := 0 ;
signal s_st_int1_cnt : chk_cnt_type := 0 ;
signal s_time_cnt : chk_cnt_type := 0 ;
signal s_st_phys1_cnt : chk_cnt_type := 0 ;
signal s_real_cnt : chk_cnt_type := 0 ;
signal s_st_real1_cnt : chk_cnt_type := 0 ;
signal s_st_rec1_cnt : chk_cnt_type := 0 ;
signal s_st_rec2_cnt : chk_cnt_type := 0 ;
signal s_st_rec3_cnt : chk_cnt_type := 0 ;
signal s_st_arr1_cnt : chk_cnt_type := 0 ;
signal s_st_arr2_cnt : chk_cnt_type := 0 ;
signal s_st_arr3_cnt : chk_cnt_type := 0 ;
--
type select_type is range 1 to 3 ;
signal boolean_select : select_type := 1 ;
signal bit_select : select_type := 1 ;
signal severity_level_select : select_type := 1 ;
signal character_select : select_type := 1 ;
signal st_enum1_select : select_type := 1 ;
signal integer_select : select_type := 1 ;
signal st_int1_select : select_type := 1 ;
signal time_select : select_type := 1 ;
signal st_phys1_select : select_type := 1 ;
signal real_select : select_type := 1 ;
signal st_real1_select : select_type := 1 ;
signal st_rec1_select : select_type := 1 ;
signal st_rec2_select : select_type := 1 ;
signal st_rec3_select : select_type := 1 ;
signal st_arr1_select : select_type := 1 ;
signal st_arr2_select : select_type := 1 ;
signal st_arr3_select : select_type := 1 ;
--
signal s_boolean : boolean
:= c_boolean_1 ;
signal s_bit : bit
:= c_bit_1 ;
signal s_severity_level : severity_level
:= c_severity_level_1 ;
signal s_character : character
:= c_character_1 ;
signal s_st_enum1 : st_enum1
:= c_st_enum1_1 ;
signal s_integer : integer
:= c_integer_1 ;
signal s_st_int1 : st_int1
:= c_st_int1_1 ;
signal s_time : time
:= c_time_1 ;
signal s_st_phys1 : st_phys1
:= c_st_phys1_1 ;
signal s_real : real
:= c_real_1 ;
signal s_st_real1 : st_real1
:= c_st_real1_1 ;
signal s_st_rec1 : st_rec1
:= c_st_rec1_1 ;
signal s_st_rec2 : st_rec2
:= c_st_rec2_1 ;
signal s_st_rec3 : st_rec3
:= c_st_rec3_1 ;
signal s_st_arr1 : st_arr1
:= c_st_arr1_1 ;
signal s_st_arr2 : st_arr2
:= c_st_arr2_1 ;
signal s_st_arr3 : st_arr3
:= c_st_arr3_1 ;
--
begin
CHG1 :
process ( s_boolean )
variable correct : boolean ;
begin
case s_boolean_cnt is
when 0
=> null ;
-- s_boolean <= transport
-- c_boolean_2 after 10 ns,
-- c_boolean_1 after 20 ns ;
--
when 1
=> correct :=
s_boolean =
c_boolean_2 and
(s_boolean_savt + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_boolean =
c_boolean_1 and
(s_boolean_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00337.P1" ,
"Multi transport transactions occurred on " &
"concurrent signal asg",
correct ) ;
--
boolean_select <= transport 2 ;
-- s_boolean <= transport
-- c_boolean_2 after 10 ns ,
-- c_boolean_1 after 20 ns ,
-- c_boolean_2 after 30 ns ,
-- c_boolean_1 after 40 ns ;
--
when 3
=> correct :=
s_boolean =
c_boolean_2 and
(s_boolean_savt + 10 ns) = Std.Standard.Now ;
boolean_select <= transport 3 ;
-- s_boolean <= transport
-- c_boolean_1 after 5 ns ;
--
when 4
=> correct :=
correct and
s_boolean =
c_boolean_1 and
(s_boolean_savt + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00337" ,
"One transport transaction occurred on a " &
"concurrent signal asg",
correct ) ;
test_report ( "ARCH00337" ,
"Old transactions were removed on a " &
"concurrent signal asg",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00337" ,
"Old transactions were removed on a " &
"concurrent signal asg",
false ) ;
--
end case ;
--
s_boolean_savt <= transport Std.Standard.Now ;
chk_boolean <= transport s_boolean_cnt
after (1 us - Std.Standard.Now) ;
s_boolean_cnt <= transport s_boolean_cnt + 1 ;
--
end process CHG1 ;
--
PGEN_CHKP_1 :
process ( chk_boolean )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P1" ,
"Transport transactions completed entirely",
chk_boolean = 4 ) ;
end if ;
end process PGEN_CHKP_1 ;
--
--
s_boolean <= transport
c_boolean_2 after 10 ns,
c_boolean_1 after 20 ns
when boolean_select = 1 else
--
c_boolean_2 after 10 ns ,
c_boolean_1 after 20 ns ,
c_boolean_2 after 30 ns ,
c_boolean_1 after 40 ns
when boolean_select = 2 else
--
c_boolean_1 after 5 ns ;
--
CHG2 :
process ( s_bit )
variable correct : boolean ;
begin
case s_bit_cnt is
when 0
=> null ;
-- s_bit <= transport
-- c_bit_2 after 10 ns,
-- c_bit_1 after 20 ns ;
--
when 1
=> correct :=
s_bit =
c_bit_2 and
(s_bit_savt + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_bit =
c_bit_1 and
(s_bit_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00337.P2" ,
"Multi transport transactions occurred on " &
"concurrent signal asg",
correct ) ;
--
bit_select <= transport 2 ;
-- s_bit <= transport
-- c_bit_2 after 10 ns ,
-- c_bit_1 after 20 ns ,
-- c_bit_2 after 30 ns ,
-- c_bit_1 after 40 ns ;
--
when 3
=> correct :=
s_bit =
c_bit_2 and
(s_bit_savt + 10 ns) = Std.Standard.Now ;
bit_select <= transport 3 ;
-- s_bit <= transport
-- c_bit_1 after 5 ns ;
--
when 4
=> correct :=
correct and
s_bit =
c_bit_1 and
(s_bit_savt + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00337" ,
"One transport transaction occurred on a " &
"concurrent signal asg",
correct ) ;
test_report ( "ARCH00337" ,
"Old transactions were removed on a " &
"concurrent signal asg",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00337" ,
"Old transactions were removed on a " &
"concurrent signal asg",
false ) ;
--
end case ;
--
s_bit_savt <= transport Std.Standard.Now ;
chk_bit <= transport s_bit_cnt
after (1 us - Std.Standard.Now) ;
s_bit_cnt <= transport s_bit_cnt + 1 ;
--
end process CHG2 ;
--
PGEN_CHKP_2 :
process ( chk_bit )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P2" ,
"Transport transactions completed entirely",
chk_bit = 4 ) ;
end if ;
end process PGEN_CHKP_2 ;
--
--
s_bit <= transport
c_bit_2 after 10 ns,
c_bit_1 after 20 ns
when bit_select = 1 else
--
c_bit_2 after 10 ns ,
c_bit_1 after 20 ns ,
c_bit_2 after 30 ns ,
c_bit_1 after 40 ns
when bit_select = 2 else
--
c_bit_1 after 5 ns ;
--
CHG3 :
process ( s_severity_level )
variable correct : boolean ;
begin
case s_severity_level_cnt is
when 0
=> null ;
-- s_severity_level <= transport
-- c_severity_level_2 after 10 ns,
-- c_severity_level_1 after 20 ns ;
--
when 1
=> correct :=
s_severity_level =
c_severity_level_2 and
(s_severity_level_savt + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_severity_level =
c_severity_level_1 and
(s_severity_level_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00337.P3" ,
"Multi transport transactions occurred on " &
"concurrent signal asg",
correct ) ;
--
severity_level_select <= transport 2 ;
-- s_severity_level <= transport
-- c_severity_level_2 after 10 ns ,
-- c_severity_level_1 after 20 ns ,
-- c_severity_level_2 after 30 ns ,
-- c_severity_level_1 after 40 ns ;
--
when 3
=> correct :=
s_severity_level =
c_severity_level_2 and
(s_severity_level_savt + 10 ns) = Std.Standard.Now ;
severity_level_select <= transport 3 ;
-- s_severity_level <= transport
-- c_severity_level_1 after 5 ns ;
--
when 4
=> correct :=
correct and
s_severity_level =
c_severity_level_1 and
(s_severity_level_savt + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00337" ,
"One transport transaction occurred on a " &
"concurrent signal asg",
correct ) ;
test_report ( "ARCH00337" ,
"Old transactions were removed on a " &
"concurrent signal asg",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00337" ,
"Old transactions were removed on a " &
"concurrent signal asg",
false ) ;
--
end case ;
--
s_severity_level_savt <= transport Std.Standard.Now ;
chk_severity_level <= transport s_severity_level_cnt
after (1 us - Std.Standard.Now) ;
s_severity_level_cnt <= transport s_severity_level_cnt + 1 ;
--
end process CHG3 ;
--
PGEN_CHKP_3 :
process ( chk_severity_level )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P3" ,
"Transport transactions completed entirely",
chk_severity_level = 4 ) ;
end if ;
end process PGEN_CHKP_3 ;
--
--
s_severity_level <= transport
c_severity_level_2 after 10 ns,
c_severity_level_1 after 20 ns
when severity_level_select = 1 else
--
c_severity_level_2 after 10 ns ,
c_severity_level_1 after 20 ns ,
c_severity_level_2 after 30 ns ,
c_severity_level_1 after 40 ns
when severity_level_select = 2 else
--
c_severity_level_1 after 5 ns ;
--
CHG4 :
process ( s_character )
variable correct : boolean ;
begin
case s_character_cnt is
when 0
=> null ;
-- s_character <= transport
-- c_character_2 after 10 ns,
-- c_character_1 after 20 ns ;
--
when 1
=> correct :=
s_character =
c_character_2 and
(s_character_savt + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_character =
c_character_1 and
(s_character_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00337.P4" ,
"Multi transport transactions occurred on " &
"concurrent signal asg",
correct ) ;
--
character_select <= transport 2 ;
-- s_character <= transport
-- c_character_2 after 10 ns ,
-- c_character_1 after 20 ns ,
-- c_character_2 after 30 ns ,
-- c_character_1 after 40 ns ;
--
when 3
=> correct :=
s_character =
c_character_2 and
(s_character_savt + 10 ns) = Std.Standard.Now ;
character_select <= transport 3 ;
-- s_character <= transport
-- c_character_1 after 5 ns ;
--
when 4
=> correct :=
correct and
s_character =
c_character_1 and
(s_character_savt + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00337" ,
"One transport transaction occurred on a " &
"concurrent signal asg",
correct ) ;
test_report ( "ARCH00337" ,
"Old transactions were removed on a " &
"concurrent signal asg",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00337" ,
"Old transactions were removed on a " &
"concurrent signal asg",
false ) ;
--
end case ;
--
s_character_savt <= transport Std.Standard.Now ;
chk_character <= transport s_character_cnt
after (1 us - Std.Standard.Now) ;
s_character_cnt <= transport s_character_cnt + 1 ;
--
end process CHG4 ;
--
PGEN_CHKP_4 :
process ( chk_character )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P4" ,
"Transport transactions completed entirely",
chk_character = 4 ) ;
end if ;
end process PGEN_CHKP_4 ;
--
--
s_character <= transport
c_character_2 after 10 ns,
c_character_1 after 20 ns
when character_select = 1 else
--
c_character_2 after 10 ns ,
c_character_1 after 20 ns ,
c_character_2 after 30 ns ,
c_character_1 after 40 ns
when character_select = 2 else
--
c_character_1 after 5 ns ;
--
CHG5 :
process ( s_st_enum1 )
variable correct : boolean ;
begin
case s_st_enum1_cnt is
when 0
=> null ;
-- s_st_enum1 <= transport
-- c_st_enum1_2 after 10 ns,
-- c_st_enum1_1 after 20 ns ;
--
when 1
=> correct :=
s_st_enum1 =
c_st_enum1_2 and
(s_st_enum1_savt + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_enum1 =
c_st_enum1_1 and
(s_st_enum1_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00337.P5" ,
"Multi transport transactions occurred on " &
"concurrent signal asg",
correct ) ;
--
st_enum1_select <= transport 2 ;
-- s_st_enum1 <= transport
-- c_st_enum1_2 after 10 ns ,
-- c_st_enum1_1 after 20 ns ,
-- c_st_enum1_2 after 30 ns ,
-- c_st_enum1_1 after 40 ns ;
--
when 3
=> correct :=
s_st_enum1 =
c_st_enum1_2 and
(s_st_enum1_savt + 10 ns) = Std.Standard.Now ;
st_enum1_select <= transport 3 ;
-- s_st_enum1 <= transport
-- c_st_enum1_1 after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_enum1 =
c_st_enum1_1 and
(s_st_enum1_savt + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00337" ,
"One transport transaction occurred on a " &
"concurrent signal asg",
correct ) ;
test_report ( "ARCH00337" ,
"Old transactions were removed on a " &
"concurrent signal asg",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00337" ,
"Old transactions were removed on a " &
"concurrent signal asg",
false ) ;
--
end case ;
--
s_st_enum1_savt <= transport Std.Standard.Now ;
chk_st_enum1 <= transport s_st_enum1_cnt
after (1 us - Std.Standard.Now) ;
s_st_enum1_cnt <= transport s_st_enum1_cnt + 1 ;
--
end process CHG5 ;
--
PGEN_CHKP_5 :
process ( chk_st_enum1 )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P5" ,
"Transport transactions completed entirely",
chk_st_enum1 = 4 ) ;
end if ;
end process PGEN_CHKP_5 ;
--
--
s_st_enum1 <= transport
c_st_enum1_2 after 10 ns,
c_st_enum1_1 after 20 ns
when st_enum1_select = 1 else
--
c_st_enum1_2 after 10 ns ,
c_st_enum1_1 after 20 ns ,
c_st_enum1_2 after 30 ns ,
c_st_enum1_1 after 40 ns
when st_enum1_select = 2 else
--
c_st_enum1_1 after 5 ns ;
--
CHG6 :
process ( s_integer )
variable correct : boolean ;
begin
case s_integer_cnt is
when 0
=> null ;
-- s_integer <= transport
-- c_integer_2 after 10 ns,
-- c_integer_1 after 20 ns ;
--
when 1
=> correct :=
s_integer =
c_integer_2 and
(s_integer_savt + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_integer =
c_integer_1 and
(s_integer_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00337.P6" ,
"Multi transport transactions occurred on " &
"concurrent signal asg",
correct ) ;
--
integer_select <= transport 2 ;
-- s_integer <= transport
-- c_integer_2 after 10 ns ,
-- c_integer_1 after 20 ns ,
-- c_integer_2 after 30 ns ,
-- c_integer_1 after 40 ns ;
--
when 3
=> correct :=
s_integer =
c_integer_2 and
(s_integer_savt + 10 ns) = Std.Standard.Now ;
integer_select <= transport 3 ;
-- s_integer <= transport
-- c_integer_1 after 5 ns ;
--
when 4
=> correct :=
correct and
s_integer =
c_integer_1 and
(s_integer_savt + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00337" ,
"One transport transaction occurred on a " &
"concurrent signal asg",
correct ) ;
test_report ( "ARCH00337" ,
"Old transactions were removed on a " &
"concurrent signal asg",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00337" ,
"Old transactions were removed on a " &
"concurrent signal asg",
false ) ;
--
end case ;
--
s_integer_savt <= transport Std.Standard.Now ;
chk_integer <= transport s_integer_cnt
after (1 us - Std.Standard.Now) ;
s_integer_cnt <= transport s_integer_cnt + 1 ;
--
end process CHG6 ;
--
PGEN_CHKP_6 :
process ( chk_integer )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P6" ,
"Transport transactions completed entirely",
chk_integer = 4 ) ;
end if ;
end process PGEN_CHKP_6 ;
--
--
s_integer <= transport
c_integer_2 after 10 ns,
c_integer_1 after 20 ns
when integer_select = 1 else
--
c_integer_2 after 10 ns ,
c_integer_1 after 20 ns ,
c_integer_2 after 30 ns ,
c_integer_1 after 40 ns
when integer_select = 2 else
--
c_integer_1 after 5 ns ;
--
CHG7 :
process ( s_st_int1 )
variable correct : boolean ;
begin
case s_st_int1_cnt is
when 0
=> null ;
-- s_st_int1 <= transport
-- c_st_int1_2 after 10 ns,
-- c_st_int1_1 after 20 ns ;
--
when 1
=> correct :=
s_st_int1 =
c_st_int1_2 and
(s_st_int1_savt + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_int1 =
c_st_int1_1 and
(s_st_int1_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00337.P7" ,
"Multi transport transactions occurred on " &
"concurrent signal asg",
correct ) ;
--
st_int1_select <= transport 2 ;
-- s_st_int1 <= transport
-- c_st_int1_2 after 10 ns ,
-- c_st_int1_1 after 20 ns ,
-- c_st_int1_2 after 30 ns ,
-- c_st_int1_1 after 40 ns ;
--
when 3
=> correct :=
s_st_int1 =
c_st_int1_2 and
(s_st_int1_savt + 10 ns) = Std.Standard.Now ;
st_int1_select <= transport 3 ;
-- s_st_int1 <= transport
-- c_st_int1_1 after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_int1 =
c_st_int1_1 and
(s_st_int1_savt + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00337" ,
"One transport transaction occurred on a " &
"concurrent signal asg",
correct ) ;
test_report ( "ARCH00337" ,
"Old transactions were removed on a " &
"concurrent signal asg",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00337" ,
"Old transactions were removed on a " &
"concurrent signal asg",
false ) ;
--
end case ;
--
s_st_int1_savt <= transport Std.Standard.Now ;
chk_st_int1 <= transport s_st_int1_cnt
after (1 us - Std.Standard.Now) ;
s_st_int1_cnt <= transport s_st_int1_cnt + 1 ;
--
end process CHG7 ;
--
PGEN_CHKP_7 :
process ( chk_st_int1 )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P7" ,
"Transport transactions completed entirely",
chk_st_int1 = 4 ) ;
end if ;
end process PGEN_CHKP_7 ;
--
--
s_st_int1 <= transport
c_st_int1_2 after 10 ns,
c_st_int1_1 after 20 ns
when st_int1_select = 1 else
--
c_st_int1_2 after 10 ns ,
c_st_int1_1 after 20 ns ,
c_st_int1_2 after 30 ns ,
c_st_int1_1 after 40 ns
when st_int1_select = 2 else
--
c_st_int1_1 after 5 ns ;
--
CHG8 :
process ( s_time )
variable correct : boolean ;
begin
case s_time_cnt is
when 0
=> null ;
-- s_time <= transport
-- c_time_2 after 10 ns,
-- c_time_1 after 20 ns ;
--
when 1
=> correct :=
s_time =
c_time_2 and
(s_time_savt + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_time =
c_time_1 and
(s_time_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00337.P8" ,
"Multi transport transactions occurred on " &
"concurrent signal asg",
correct ) ;
--
time_select <= transport 2 ;
-- s_time <= transport
-- c_time_2 after 10 ns ,
-- c_time_1 after 20 ns ,
-- c_time_2 after 30 ns ,
-- c_time_1 after 40 ns ;
--
when 3
=> correct :=
s_time =
c_time_2 and
(s_time_savt + 10 ns) = Std.Standard.Now ;
time_select <= transport 3 ;
-- s_time <= transport
-- c_time_1 after 5 ns ;
--
when 4
=> correct :=
correct and
s_time =
c_time_1 and
(s_time_savt + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00337" ,
"One transport transaction occurred on a " &
"concurrent signal asg",
correct ) ;
test_report ( "ARCH00337" ,
"Old transactions were removed on a " &
"concurrent signal asg",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00337" ,
"Old transactions were removed on a " &
"concurrent signal asg",
false ) ;
--
end case ;
--
s_time_savt <= transport Std.Standard.Now ;
chk_time <= transport s_time_cnt
after (1 us - Std.Standard.Now) ;
s_time_cnt <= transport s_time_cnt + 1 ;
--
end process CHG8 ;
--
PGEN_CHKP_8 :
process ( chk_time )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P8" ,
"Transport transactions completed entirely",
chk_time = 4 ) ;
end if ;
end process PGEN_CHKP_8 ;
--
--
s_time <= transport
c_time_2 after 10 ns,
c_time_1 after 20 ns
when time_select = 1 else
--
c_time_2 after 10 ns ,
c_time_1 after 20 ns ,
c_time_2 after 30 ns ,
c_time_1 after 40 ns
when time_select = 2 else
--
c_time_1 after 5 ns ;
--
CHG9 :
process ( s_st_phys1 )
variable correct : boolean ;
begin
case s_st_phys1_cnt is
when 0
=> null ;
-- s_st_phys1 <= transport
-- c_st_phys1_2 after 10 ns,
-- c_st_phys1_1 after 20 ns ;
--
when 1
=> correct :=
s_st_phys1 =
c_st_phys1_2 and
(s_st_phys1_savt + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_phys1 =
c_st_phys1_1 and
(s_st_phys1_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00337.P9" ,
"Multi transport transactions occurred on " &
"concurrent signal asg",
correct ) ;
--
st_phys1_select <= transport 2 ;
-- s_st_phys1 <= transport
-- c_st_phys1_2 after 10 ns ,
-- c_st_phys1_1 after 20 ns ,
-- c_st_phys1_2 after 30 ns ,
-- c_st_phys1_1 after 40 ns ;
--
when 3
=> correct :=
s_st_phys1 =
c_st_phys1_2 and
(s_st_phys1_savt + 10 ns) = Std.Standard.Now ;
st_phys1_select <= transport 3 ;
-- s_st_phys1 <= transport
-- c_st_phys1_1 after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_phys1 =
c_st_phys1_1 and
(s_st_phys1_savt + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00337" ,
"One transport transaction occurred on a " &
"concurrent signal asg",
correct ) ;
test_report ( "ARCH00337" ,
"Old transactions were removed on a " &
"concurrent signal asg",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00337" ,
"Old transactions were removed on a " &
"concurrent signal asg",
false ) ;
--
end case ;
--
s_st_phys1_savt <= transport Std.Standard.Now ;
chk_st_phys1 <= transport s_st_phys1_cnt
after (1 us - Std.Standard.Now) ;
s_st_phys1_cnt <= transport s_st_phys1_cnt + 1 ;
--
end process CHG9 ;
--
PGEN_CHKP_9 :
process ( chk_st_phys1 )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P9" ,
"Transport transactions completed entirely",
chk_st_phys1 = 4 ) ;
end if ;
end process PGEN_CHKP_9 ;
--
--
s_st_phys1 <= transport
c_st_phys1_2 after 10 ns,
c_st_phys1_1 after 20 ns
when st_phys1_select = 1 else
--
c_st_phys1_2 after 10 ns ,
c_st_phys1_1 after 20 ns ,
c_st_phys1_2 after 30 ns ,
c_st_phys1_1 after 40 ns
when st_phys1_select = 2 else
--
c_st_phys1_1 after 5 ns ;
--
CHG10 :
process ( s_real )
variable correct : boolean ;
begin
case s_real_cnt is
when 0
=> null ;
-- s_real <= transport
-- c_real_2 after 10 ns,
-- c_real_1 after 20 ns ;
--
when 1
=> correct :=
s_real =
c_real_2 and
(s_real_savt + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_real =
c_real_1 and
(s_real_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00337.P10" ,
"Multi transport transactions occurred on " &
"concurrent signal asg",
correct ) ;
--
real_select <= transport 2 ;
-- s_real <= transport
-- c_real_2 after 10 ns ,
-- c_real_1 after 20 ns ,
-- c_real_2 after 30 ns ,
-- c_real_1 after 40 ns ;
--
when 3
=> correct :=
s_real =
c_real_2 and
(s_real_savt + 10 ns) = Std.Standard.Now ;
real_select <= transport 3 ;
-- s_real <= transport
-- c_real_1 after 5 ns ;
--
when 4
=> correct :=
correct and
s_real =
c_real_1 and
(s_real_savt + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00337" ,
"One transport transaction occurred on a " &
"concurrent signal asg",
correct ) ;
test_report ( "ARCH00337" ,
"Old transactions were removed on a " &
"concurrent signal asg",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00337" ,
"Old transactions were removed on a " &
"concurrent signal asg",
false ) ;
--
end case ;
--
s_real_savt <= transport Std.Standard.Now ;
chk_real <= transport s_real_cnt
after (1 us - Std.Standard.Now) ;
s_real_cnt <= transport s_real_cnt + 1 ;
--
end process CHG10 ;
--
PGEN_CHKP_10 :
process ( chk_real )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P10" ,
"Transport transactions completed entirely",
chk_real = 4 ) ;
end if ;
end process PGEN_CHKP_10 ;
--
--
s_real <= transport
c_real_2 after 10 ns,
c_real_1 after 20 ns
when real_select = 1 else
--
c_real_2 after 10 ns ,
c_real_1 after 20 ns ,
c_real_2 after 30 ns ,
c_real_1 after 40 ns
when real_select = 2 else
--
c_real_1 after 5 ns ;
--
CHG11 :
process ( s_st_real1 )
variable correct : boolean ;
begin
case s_st_real1_cnt is
when 0
=> null ;
-- s_st_real1 <= transport
-- c_st_real1_2 after 10 ns,
-- c_st_real1_1 after 20 ns ;
--
when 1
=> correct :=
s_st_real1 =
c_st_real1_2 and
(s_st_real1_savt + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_real1 =
c_st_real1_1 and
(s_st_real1_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00337.P11" ,
"Multi transport transactions occurred on " &
"concurrent signal asg",
correct ) ;
--
st_real1_select <= transport 2 ;
-- s_st_real1 <= transport
-- c_st_real1_2 after 10 ns ,
-- c_st_real1_1 after 20 ns ,
-- c_st_real1_2 after 30 ns ,
-- c_st_real1_1 after 40 ns ;
--
when 3
=> correct :=
s_st_real1 =
c_st_real1_2 and
(s_st_real1_savt + 10 ns) = Std.Standard.Now ;
st_real1_select <= transport 3 ;
-- s_st_real1 <= transport
-- c_st_real1_1 after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_real1 =
c_st_real1_1 and
(s_st_real1_savt + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00337" ,
"One transport transaction occurred on a " &
"concurrent signal asg",
correct ) ;
test_report ( "ARCH00337" ,
"Old transactions were removed on a " &
"concurrent signal asg",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00337" ,
"Old transactions were removed on a " &
"concurrent signal asg",
false ) ;
--
end case ;
--
s_st_real1_savt <= transport Std.Standard.Now ;
chk_st_real1 <= transport s_st_real1_cnt
after (1 us - Std.Standard.Now) ;
s_st_real1_cnt <= transport s_st_real1_cnt + 1 ;
--
end process CHG11 ;
--
PGEN_CHKP_11 :
process ( chk_st_real1 )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P11" ,
"Transport transactions completed entirely",
chk_st_real1 = 4 ) ;
end if ;
end process PGEN_CHKP_11 ;
--
--
s_st_real1 <= transport
c_st_real1_2 after 10 ns,
c_st_real1_1 after 20 ns
when st_real1_select = 1 else
--
c_st_real1_2 after 10 ns ,
c_st_real1_1 after 20 ns ,
c_st_real1_2 after 30 ns ,
c_st_real1_1 after 40 ns
when st_real1_select = 2 else
--
c_st_real1_1 after 5 ns ;
--
CHG12 :
process ( s_st_rec1 )
variable correct : boolean ;
begin
case s_st_rec1_cnt is
when 0
=> null ;
-- s_st_rec1 <= transport
-- c_st_rec1_2 after 10 ns,
-- c_st_rec1_1 after 20 ns ;
--
when 1
=> correct :=
s_st_rec1 =
c_st_rec1_2 and
(s_st_rec1_savt + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_rec1 =
c_st_rec1_1 and
(s_st_rec1_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00337.P12" ,
"Multi transport transactions occurred on " &
"concurrent signal asg",
correct ) ;
--
st_rec1_select <= transport 2 ;
-- s_st_rec1 <= transport
-- c_st_rec1_2 after 10 ns ,
-- c_st_rec1_1 after 20 ns ,
-- c_st_rec1_2 after 30 ns ,
-- c_st_rec1_1 after 40 ns ;
--
when 3
=> correct :=
s_st_rec1 =
c_st_rec1_2 and
(s_st_rec1_savt + 10 ns) = Std.Standard.Now ;
st_rec1_select <= transport 3 ;
-- s_st_rec1 <= transport
-- c_st_rec1_1 after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_rec1 =
c_st_rec1_1 and
(s_st_rec1_savt + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00337" ,
"One transport transaction occurred on a " &
"concurrent signal asg",
correct ) ;
test_report ( "ARCH00337" ,
"Old transactions were removed on a " &
"concurrent signal asg",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00337" ,
"Old transactions were removed on a " &
"concurrent signal asg",
false ) ;
--
end case ;
--
s_st_rec1_savt <= transport Std.Standard.Now ;
chk_st_rec1 <= transport s_st_rec1_cnt
after (1 us - Std.Standard.Now) ;
s_st_rec1_cnt <= transport s_st_rec1_cnt + 1 ;
--
end process CHG12 ;
--
PGEN_CHKP_12 :
process ( chk_st_rec1 )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P12" ,
"Transport transactions completed entirely",
chk_st_rec1 = 4 ) ;
end if ;
end process PGEN_CHKP_12 ;
--
--
s_st_rec1 <= transport
c_st_rec1_2 after 10 ns,
c_st_rec1_1 after 20 ns
when st_rec1_select = 1 else
--
c_st_rec1_2 after 10 ns ,
c_st_rec1_1 after 20 ns ,
c_st_rec1_2 after 30 ns ,
c_st_rec1_1 after 40 ns
when st_rec1_select = 2 else
--
c_st_rec1_1 after 5 ns ;
--
CHG13 :
process ( s_st_rec2 )
variable correct : boolean ;
begin
case s_st_rec2_cnt is
when 0
=> null ;
-- s_st_rec2 <= transport
-- c_st_rec2_2 after 10 ns,
-- c_st_rec2_1 after 20 ns ;
--
when 1
=> correct :=
s_st_rec2 =
c_st_rec2_2 and
(s_st_rec2_savt + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_rec2 =
c_st_rec2_1 and
(s_st_rec2_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00337.P13" ,
"Multi transport transactions occurred on " &
"concurrent signal asg",
correct ) ;
--
st_rec2_select <= transport 2 ;
-- s_st_rec2 <= transport
-- c_st_rec2_2 after 10 ns ,
-- c_st_rec2_1 after 20 ns ,
-- c_st_rec2_2 after 30 ns ,
-- c_st_rec2_1 after 40 ns ;
--
when 3
=> correct :=
s_st_rec2 =
c_st_rec2_2 and
(s_st_rec2_savt + 10 ns) = Std.Standard.Now ;
st_rec2_select <= transport 3 ;
-- s_st_rec2 <= transport
-- c_st_rec2_1 after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_rec2 =
c_st_rec2_1 and
(s_st_rec2_savt + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00337" ,
"One transport transaction occurred on a " &
"concurrent signal asg",
correct ) ;
test_report ( "ARCH00337" ,
"Old transactions were removed on a " &
"concurrent signal asg",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00337" ,
"Old transactions were removed on a " &
"concurrent signal asg",
false ) ;
--
end case ;
--
s_st_rec2_savt <= transport Std.Standard.Now ;
chk_st_rec2 <= transport s_st_rec2_cnt
after (1 us - Std.Standard.Now) ;
s_st_rec2_cnt <= transport s_st_rec2_cnt + 1 ;
--
end process CHG13 ;
--
PGEN_CHKP_13 :
process ( chk_st_rec2 )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P13" ,
"Transport transactions completed entirely",
chk_st_rec2 = 4 ) ;
end if ;
end process PGEN_CHKP_13 ;
--
--
s_st_rec2 <= transport
c_st_rec2_2 after 10 ns,
c_st_rec2_1 after 20 ns
when st_rec2_select = 1 else
--
c_st_rec2_2 after 10 ns ,
c_st_rec2_1 after 20 ns ,
c_st_rec2_2 after 30 ns ,
c_st_rec2_1 after 40 ns
when st_rec2_select = 2 else
--
c_st_rec2_1 after 5 ns ;
--
CHG14 :
process ( s_st_rec3 )
variable correct : boolean ;
begin
case s_st_rec3_cnt is
when 0
=> null ;
-- s_st_rec3 <= transport
-- c_st_rec3_2 after 10 ns,
-- c_st_rec3_1 after 20 ns ;
--
when 1
=> correct :=
s_st_rec3 =
c_st_rec3_2 and
(s_st_rec3_savt + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_rec3 =
c_st_rec3_1 and
(s_st_rec3_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00337.P14" ,
"Multi transport transactions occurred on " &
"concurrent signal asg",
correct ) ;
--
st_rec3_select <= transport 2 ;
-- s_st_rec3 <= transport
-- c_st_rec3_2 after 10 ns ,
-- c_st_rec3_1 after 20 ns ,
-- c_st_rec3_2 after 30 ns ,
-- c_st_rec3_1 after 40 ns ;
--
when 3
=> correct :=
s_st_rec3 =
c_st_rec3_2 and
(s_st_rec3_savt + 10 ns) = Std.Standard.Now ;
st_rec3_select <= transport 3 ;
-- s_st_rec3 <= transport
-- c_st_rec3_1 after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_rec3 =
c_st_rec3_1 and
(s_st_rec3_savt + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00337" ,
"One transport transaction occurred on a " &
"concurrent signal asg",
correct ) ;
test_report ( "ARCH00337" ,
"Old transactions were removed on a " &
"concurrent signal asg",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00337" ,
"Old transactions were removed on a " &
"concurrent signal asg",
false ) ;
--
end case ;
--
s_st_rec3_savt <= transport Std.Standard.Now ;
chk_st_rec3 <= transport s_st_rec3_cnt
after (1 us - Std.Standard.Now) ;
s_st_rec3_cnt <= transport s_st_rec3_cnt + 1 ;
--
end process CHG14 ;
--
PGEN_CHKP_14 :
process ( chk_st_rec3 )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P14" ,
"Transport transactions completed entirely",
chk_st_rec3 = 4 ) ;
end if ;
end process PGEN_CHKP_14 ;
--
--
s_st_rec3 <= transport
c_st_rec3_2 after 10 ns,
c_st_rec3_1 after 20 ns
when st_rec3_select = 1 else
--
c_st_rec3_2 after 10 ns ,
c_st_rec3_1 after 20 ns ,
c_st_rec3_2 after 30 ns ,
c_st_rec3_1 after 40 ns
when st_rec3_select = 2 else
--
c_st_rec3_1 after 5 ns ;
--
CHG15 :
process ( s_st_arr1 )
variable correct : boolean ;
begin
case s_st_arr1_cnt is
when 0
=> null ;
-- s_st_arr1 <= transport
-- c_st_arr1_2 after 10 ns,
-- c_st_arr1_1 after 20 ns ;
--
when 1
=> correct :=
s_st_arr1 =
c_st_arr1_2 and
(s_st_arr1_savt + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_arr1 =
c_st_arr1_1 and
(s_st_arr1_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00337.P15" ,
"Multi transport transactions occurred on " &
"concurrent signal asg",
correct ) ;
--
st_arr1_select <= transport 2 ;
-- s_st_arr1 <= transport
-- c_st_arr1_2 after 10 ns ,
-- c_st_arr1_1 after 20 ns ,
-- c_st_arr1_2 after 30 ns ,
-- c_st_arr1_1 after 40 ns ;
--
when 3
=> correct :=
s_st_arr1 =
c_st_arr1_2 and
(s_st_arr1_savt + 10 ns) = Std.Standard.Now ;
st_arr1_select <= transport 3 ;
-- s_st_arr1 <= transport
-- c_st_arr1_1 after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_arr1 =
c_st_arr1_1 and
(s_st_arr1_savt + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00337" ,
"One transport transaction occurred on a " &
"concurrent signal asg",
correct ) ;
test_report ( "ARCH00337" ,
"Old transactions were removed on a " &
"concurrent signal asg",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00337" ,
"Old transactions were removed on a " &
"concurrent signal asg",
false ) ;
--
end case ;
--
s_st_arr1_savt <= transport Std.Standard.Now ;
chk_st_arr1 <= transport s_st_arr1_cnt
after (1 us - Std.Standard.Now) ;
s_st_arr1_cnt <= transport s_st_arr1_cnt + 1 ;
--
end process CHG15 ;
--
PGEN_CHKP_15 :
process ( chk_st_arr1 )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P15" ,
"Transport transactions completed entirely",
chk_st_arr1 = 4 ) ;
end if ;
end process PGEN_CHKP_15 ;
--
--
s_st_arr1 <= transport
c_st_arr1_2 after 10 ns,
c_st_arr1_1 after 20 ns
when st_arr1_select = 1 else
--
c_st_arr1_2 after 10 ns ,
c_st_arr1_1 after 20 ns ,
c_st_arr1_2 after 30 ns ,
c_st_arr1_1 after 40 ns
when st_arr1_select = 2 else
--
c_st_arr1_1 after 5 ns ;
--
CHG16 :
process ( s_st_arr2 )
variable correct : boolean ;
begin
case s_st_arr2_cnt is
when 0
=> null ;
-- s_st_arr2 <= transport
-- c_st_arr2_2 after 10 ns,
-- c_st_arr2_1 after 20 ns ;
--
when 1
=> correct :=
s_st_arr2 =
c_st_arr2_2 and
(s_st_arr2_savt + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_arr2 =
c_st_arr2_1 and
(s_st_arr2_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00337.P16" ,
"Multi transport transactions occurred on " &
"concurrent signal asg",
correct ) ;
--
st_arr2_select <= transport 2 ;
-- s_st_arr2 <= transport
-- c_st_arr2_2 after 10 ns ,
-- c_st_arr2_1 after 20 ns ,
-- c_st_arr2_2 after 30 ns ,
-- c_st_arr2_1 after 40 ns ;
--
when 3
=> correct :=
s_st_arr2 =
c_st_arr2_2 and
(s_st_arr2_savt + 10 ns) = Std.Standard.Now ;
st_arr2_select <= transport 3 ;
-- s_st_arr2 <= transport
-- c_st_arr2_1 after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_arr2 =
c_st_arr2_1 and
(s_st_arr2_savt + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00337" ,
"One transport transaction occurred on a " &
"concurrent signal asg",
correct ) ;
test_report ( "ARCH00337" ,
"Old transactions were removed on a " &
"concurrent signal asg",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00337" ,
"Old transactions were removed on a " &
"concurrent signal asg",
false ) ;
--
end case ;
--
s_st_arr2_savt <= transport Std.Standard.Now ;
chk_st_arr2 <= transport s_st_arr2_cnt
after (1 us - Std.Standard.Now) ;
s_st_arr2_cnt <= transport s_st_arr2_cnt + 1 ;
--
end process CHG16 ;
--
PGEN_CHKP_16 :
process ( chk_st_arr2 )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P16" ,
"Transport transactions completed entirely",
chk_st_arr2 = 4 ) ;
end if ;
end process PGEN_CHKP_16 ;
--
--
s_st_arr2 <= transport
c_st_arr2_2 after 10 ns,
c_st_arr2_1 after 20 ns
when st_arr2_select = 1 else
--
c_st_arr2_2 after 10 ns ,
c_st_arr2_1 after 20 ns ,
c_st_arr2_2 after 30 ns ,
c_st_arr2_1 after 40 ns
when st_arr2_select = 2 else
--
c_st_arr2_1 after 5 ns ;
--
CHG17 :
process ( s_st_arr3 )
variable correct : boolean ;
begin
case s_st_arr3_cnt is
when 0
=> null ;
-- s_st_arr3 <= transport
-- c_st_arr3_2 after 10 ns,
-- c_st_arr3_1 after 20 ns ;
--
when 1
=> correct :=
s_st_arr3 =
c_st_arr3_2 and
(s_st_arr3_savt + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_arr3 =
c_st_arr3_1 and
(s_st_arr3_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00337.P17" ,
"Multi transport transactions occurred on " &
"concurrent signal asg",
correct ) ;
--
st_arr3_select <= transport 2 ;
-- s_st_arr3 <= transport
-- c_st_arr3_2 after 10 ns ,
-- c_st_arr3_1 after 20 ns ,
-- c_st_arr3_2 after 30 ns ,
-- c_st_arr3_1 after 40 ns ;
--
when 3
=> correct :=
s_st_arr3 =
c_st_arr3_2 and
(s_st_arr3_savt + 10 ns) = Std.Standard.Now ;
st_arr3_select <= transport 3 ;
-- s_st_arr3 <= transport
-- c_st_arr3_1 after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_arr3 =
c_st_arr3_1 and
(s_st_arr3_savt + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00337" ,
"One transport transaction occurred on a " &
"concurrent signal asg",
correct ) ;
test_report ( "ARCH00337" ,
"Old transactions were removed on a " &
"concurrent signal asg",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00337" ,
"Old transactions were removed on a " &
"concurrent signal asg",
false ) ;
--
end case ;
--
s_st_arr3_savt <= transport Std.Standard.Now ;
chk_st_arr3 <= transport s_st_arr3_cnt
after (1 us - Std.Standard.Now) ;
s_st_arr3_cnt <= transport s_st_arr3_cnt + 1 ;
--
end process CHG17 ;
--
PGEN_CHKP_17 :
process ( chk_st_arr3 )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P17" ,
"Transport transactions completed entirely",
chk_st_arr3 = 4 ) ;
end if ;
end process PGEN_CHKP_17 ;
--
--
s_st_arr3 <= transport
c_st_arr3_2 after 10 ns,
c_st_arr3_1 after 20 ns
when st_arr3_select = 1 else
--
c_st_arr3_2 after 10 ns ,
c_st_arr3_1 after 20 ns ,
c_st_arr3_2 after 30 ns ,
c_st_arr3_1 after 40 ns
when st_arr3_select = 2 else
--
c_st_arr3_1 after 5 ns ;
--
end ARCH00337 ;
--
--
use WORK.STANDARD_TYPES.all ;
entity ENT00337_Test_Bench is
end ENT00337_Test_Bench ;
--
--
architecture ARCH00337_Test_Bench of ENT00337_Test_Bench is
begin
L1:
block
component UUT
end component ;
--
for CIS1 : UUT use entity WORK.ENT00337 ( ARCH00337 ) ;
begin
CIS1 : UUT
;
end block L1 ;
end ARCH00337_Test_Bench ;
| gpl-3.0 | fdc11d0202eb6b749a99dcfb14952065 | 0.489985 | 3.733095 | false | false | false | false |
TWW12/lzw | final_project/lzw_compression/lzw_compression.srcs/sources_1/bd/design_1/ip/design_1_axi_compression_0_0/synth/design_1_axi_compression_0_0.vhd | 1 | 8,855 | -- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
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-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:user:axi_compression:1.0
-- IP Revision: 29
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY design_1_axi_compression_0_0 IS
PORT (
s00_axi_awaddr : IN STD_LOGIC_VECTOR(5 DOWNTO 0);
s00_axi_awprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s00_axi_awvalid : IN STD_LOGIC;
s00_axi_awready : OUT STD_LOGIC;
s00_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s00_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s00_axi_wvalid : IN STD_LOGIC;
s00_axi_wready : OUT STD_LOGIC;
s00_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s00_axi_bvalid : OUT STD_LOGIC;
s00_axi_bready : IN STD_LOGIC;
s00_axi_araddr : IN STD_LOGIC_VECTOR(5 DOWNTO 0);
s00_axi_arprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s00_axi_arvalid : IN STD_LOGIC;
s00_axi_arready : OUT STD_LOGIC;
s00_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s00_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s00_axi_rvalid : OUT STD_LOGIC;
s00_axi_rready : IN STD_LOGIC;
s00_axi_aclk : IN STD_LOGIC;
s00_axi_aresetn : IN STD_LOGIC
);
END design_1_axi_compression_0_0;
ARCHITECTURE design_1_axi_compression_0_0_arch OF design_1_axi_compression_0_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF design_1_axi_compression_0_0_arch: ARCHITECTURE IS "yes";
COMPONENT axi_compression_v1_0 IS
GENERIC (
C_S00_AXI_DATA_WIDTH : INTEGER; -- Width of S_AXI data bus
C_S00_AXI_ADDR_WIDTH : INTEGER -- Width of S_AXI address bus
);
PORT (
s00_axi_awaddr : IN STD_LOGIC_VECTOR(5 DOWNTO 0);
s00_axi_awprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s00_axi_awvalid : IN STD_LOGIC;
s00_axi_awready : OUT STD_LOGIC;
s00_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s00_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s00_axi_wvalid : IN STD_LOGIC;
s00_axi_wready : OUT STD_LOGIC;
s00_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s00_axi_bvalid : OUT STD_LOGIC;
s00_axi_bready : IN STD_LOGIC;
s00_axi_araddr : IN STD_LOGIC_VECTOR(5 DOWNTO 0);
s00_axi_arprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s00_axi_arvalid : IN STD_LOGIC;
s00_axi_arready : OUT STD_LOGIC;
s00_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s00_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s00_axi_rvalid : OUT STD_LOGIC;
s00_axi_rready : IN STD_LOGIC;
s00_axi_aclk : IN STD_LOGIC;
s00_axi_aresetn : IN STD_LOGIC
);
END COMPONENT axi_compression_v1_0;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF design_1_axi_compression_0_0_arch: ARCHITECTURE IS "axi_compression_v1_0,Vivado 2016.4";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF design_1_axi_compression_0_0_arch : ARCHITECTURE IS "design_1_axi_compression_0_0,axi_compression_v1_0,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF design_1_axi_compression_0_0_arch: ARCHITECTURE IS "design_1_axi_compression_0_0,axi_compression_v1_0,{x_ipProduct=Vivado 2016.4,x_ipVendor=xilinx.com,x_ipLibrary=user,x_ipName=axi_compression,x_ipVersion=1.0,x_ipCoreRevision=29,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,C_S00_AXI_DATA_WIDTH=32,C_S00_AXI_ADDR_WIDTH=6}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_awaddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI AWADDR";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_awprot: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI AWPROT";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_awvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI AWVALID";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_awready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI AWREADY";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_wdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI WDATA";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_wstrb: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI WSTRB";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_wvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI WVALID";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_wready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI WREADY";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_bresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI BRESP";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_bvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI BVALID";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_bready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI BREADY";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_araddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI ARADDR";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_arprot: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI ARPROT";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_arvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI ARVALID";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_arready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI ARREADY";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_rdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI RDATA";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_rresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI RRESP";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_rvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI RVALID";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_rready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI RREADY";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 S00_AXI_CLK CLK";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 S00_AXI_RST RST";
BEGIN
U0 : axi_compression_v1_0
GENERIC MAP (
C_S00_AXI_DATA_WIDTH => 32,
C_S00_AXI_ADDR_WIDTH => 6
)
PORT MAP (
s00_axi_awaddr => s00_axi_awaddr,
s00_axi_awprot => s00_axi_awprot,
s00_axi_awvalid => s00_axi_awvalid,
s00_axi_awready => s00_axi_awready,
s00_axi_wdata => s00_axi_wdata,
s00_axi_wstrb => s00_axi_wstrb,
s00_axi_wvalid => s00_axi_wvalid,
s00_axi_wready => s00_axi_wready,
s00_axi_bresp => s00_axi_bresp,
s00_axi_bvalid => s00_axi_bvalid,
s00_axi_bready => s00_axi_bready,
s00_axi_araddr => s00_axi_araddr,
s00_axi_arprot => s00_axi_arprot,
s00_axi_arvalid => s00_axi_arvalid,
s00_axi_arready => s00_axi_arready,
s00_axi_rdata => s00_axi_rdata,
s00_axi_rresp => s00_axi_rresp,
s00_axi_rvalid => s00_axi_rvalid,
s00_axi_rready => s00_axi_rready,
s00_axi_aclk => s00_axi_aclk,
s00_axi_aresetn => s00_axi_aresetn
);
END design_1_axi_compression_0_0_arch;
| unlicense | 765c5b9cdd03483c664907ad13c75069 | 0.714399 | 3.209496 | false | false | false | false |
jairov4/accel-oil | impl/impl_test_pcie/hdl/system_ac1_mb_bridge_wrapper.vhd | 1 | 11,046 | -------------------------------------------------------------------------------
-- system_ac1_mb_bridge_wrapper.vhd
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
library plbv46_plbv46_bridge_v1_04_a;
use plbv46_plbv46_bridge_v1_04_a.all;
entity system_ac1_mb_bridge_wrapper is
port (
SPLB_Clk : in std_logic;
SPLB_Rst : in std_logic;
IP2INTC_Irpt : out std_logic;
PLB_ABus : in std_logic_vector(0 to 31);
PLB_UABus : in std_logic_vector(0 to 31);
PLB_PAValid : in std_logic;
PLB_SAValid : in std_logic;
PLB_rdPrim : in std_logic;
PLB_wrPrim : in std_logic;
PLB_masterID : in std_logic_vector(0 to 3);
PLB_abort : in std_logic;
PLB_busLock : in std_logic;
PLB_RNW : in std_logic;
PLB_BE : in std_logic_vector(0 to 7);
PLB_MSize : in std_logic_vector(0 to 1);
PLB_size : in std_logic_vector(0 to 3);
PLB_type : in std_logic_vector(0 to 2);
PLB_lockErr : in std_logic;
PLB_wrDBus : in std_logic_vector(0 to 63);
PLB_wrBurst : in std_logic;
PLB_rdBurst : in std_logic;
PLB_wrPendReq : in std_logic;
PLB_rdPendReq : in std_logic;
PLB_wrPendPri : in std_logic_vector(0 to 1);
PLB_rdPendPri : in std_logic_vector(0 to 1);
PLB_reqPri : in std_logic_vector(0 to 1);
PLB_TAttribute : in std_logic_vector(0 to 15);
Sl_addrAck : out std_logic;
Sl_SSize : out std_logic_vector(0 to 1);
Sl_wait : out std_logic;
Sl_rearbitrate : out std_logic;
Sl_wrDAck : out std_logic;
Sl_wrComp : out std_logic;
Sl_wrBTerm : out std_logic;
Sl_rdDBus : out std_logic_vector(0 to 63);
Sl_rdWdAddr : out std_logic_vector(0 to 3);
Sl_rdDAck : out std_logic;
Sl_rdComp : out std_logic;
Sl_rdBTerm : out std_logic;
Sl_MBusy : out std_logic_vector(0 to 14);
Sl_MWrErr : out std_logic_vector(0 to 14);
Sl_MRdErr : out std_logic_vector(0 to 14);
Sl_MIRQ : out std_logic_vector(0 to 14);
MPLB_Clk : in std_logic;
MPLB_Rst : in std_logic;
M_request : out std_logic;
M_priority : out std_logic_vector(0 to 1);
M_busLock : out std_logic;
M_RNW : out std_logic;
M_BE : out std_logic_vector(0 to 7);
M_MSize : out std_logic_vector(0 to 1);
M_size : out std_logic_vector(0 to 3);
M_type : out std_logic_vector(0 to 2);
M_ABus : out std_logic_vector(0 to 31);
M_wrBurst : out std_logic;
M_rdBurst : out std_logic;
M_wrDBus : out std_logic_vector(0 to 63);
PLB_MAddrAck : in std_logic;
PLB_MSSize : in std_logic_vector(0 to 1);
PLB_MRearbitrate : in std_logic;
PLB_MTimeout : in std_logic;
PLB_MRdErr : in std_logic;
PLB_MWrErr : in std_logic;
PLB_MRdDBus : in std_logic_vector(0 to 63);
PLB_MRdDAck : in std_logic;
PLB_MRdBTerm : in std_logic;
PLB_MWrDAck : in std_logic;
PLB_MWrBTerm : in std_logic;
M_TAttribute : out std_logic_vector(0 to 15);
M_lockErr : out std_logic;
M_abort : out std_logic;
M_UABus : out std_logic_vector(0 to 31);
PLB_MBusy : in std_logic;
PLB_MIRQ : in std_logic;
PLB_MRdWdAddr : in std_logic_vector(0 to 3)
);
attribute x_core_info : STRING;
attribute x_core_info of system_ac1_mb_bridge_wrapper : entity is "plbv46_plbv46_bridge_v1_04_a";
end system_ac1_mb_bridge_wrapper;
architecture STRUCTURE of system_ac1_mb_bridge_wrapper is
component plbv46_plbv46_bridge is
generic (
C_NUM_ADDR_RNG : INTEGER;
C_BRIDGE_BASEADDR : std_logic_vector;
C_BRIDGE_HIGHADDR : std_logic_vector;
C_RNG0_BASEADDR : std_logic_vector;
C_RNG0_HIGHADDR : std_logic_vector;
C_RNG1_BASEADDR : std_logic_vector;
C_RNG1_HIGHADDR : std_logic_vector;
C_RNG2_BASEADDR : std_logic_vector;
C_RNG2_HIGHADDR : std_logic_vector;
C_RNG3_BASEADDR : std_logic_vector;
C_RNG3_HIGHADDR : std_logic_vector;
C_SPLB_P2P : INTEGER;
C_SPLB_MID_WIDTH : INTEGER;
C_SPLB_NUM_MASTERS : INTEGER;
C_SPLB_SMALLEST_MASTER : INTEGER;
C_SPLB_BIGGEST_MASTER : INTEGER;
C_SPLB_AWIDTH : INTEGER;
C_SPLB_DWIDTH : INTEGER;
C_MPLB_AWIDTH : INTEGER;
C_MPLB_DWIDTH : INTEGER;
C_SPLB_NATIVE_DWIDTH : INTEGER;
C_MPLB_NATIVE_DWIDTH : INTEGER;
C_MPLB_SMALLEST_SLAVE : INTEGER;
C_BUS_CLOCK_RATIO : INTEGER;
C_PREFETCH_TIMEOUT : INTEGER;
C_FAMILY : STRING
);
port (
SPLB_Clk : in std_logic;
SPLB_Rst : in std_logic;
IP2INTC_Irpt : out std_logic;
PLB_ABus : in std_logic_vector(0 to C_SPLB_AWIDTH-1);
PLB_UABus : in std_logic_vector(0 to C_SPLB_AWIDTH-1);
PLB_PAValid : in std_logic;
PLB_SAValid : in std_logic;
PLB_rdPrim : in std_logic;
PLB_wrPrim : in std_logic;
PLB_masterID : in std_logic_vector(0 to (C_SPLB_MID_WIDTH-1));
PLB_abort : in std_logic;
PLB_busLock : in std_logic;
PLB_RNW : in std_logic;
PLB_BE : in std_logic_vector(0 to ((C_SPLB_DWIDTH/8)-1));
PLB_MSize : in std_logic_vector(0 to 1);
PLB_size : in std_logic_vector(0 to 3);
PLB_type : in std_logic_vector(0 to 2);
PLB_lockErr : in std_logic;
PLB_wrDBus : in std_logic_vector(0 to (C_SPLB_DWIDTH-1));
PLB_wrBurst : in std_logic;
PLB_rdBurst : in std_logic;
PLB_wrPendReq : in std_logic;
PLB_rdPendReq : in std_logic;
PLB_wrPendPri : in std_logic_vector(0 to 1);
PLB_rdPendPri : in std_logic_vector(0 to 1);
PLB_reqPri : in std_logic_vector(0 to 1);
PLB_TAttribute : in std_logic_vector(0 to 15);
Sl_addrAck : out std_logic;
Sl_SSize : out std_logic_vector(0 to 1);
Sl_wait : out std_logic;
Sl_rearbitrate : out std_logic;
Sl_wrDAck : out std_logic;
Sl_wrComp : out std_logic;
Sl_wrBTerm : out std_logic;
Sl_rdDBus : out std_logic_vector(0 to (C_SPLB_DWIDTH-1));
Sl_rdWdAddr : out std_logic_vector(0 to 3);
Sl_rdDAck : out std_logic;
Sl_rdComp : out std_logic;
Sl_rdBTerm : out std_logic;
Sl_MBusy : out std_logic_vector(0 to (C_SPLB_NUM_MASTERS-1));
Sl_MWrErr : out std_logic_vector(0 to (C_SPLB_NUM_MASTERS-1));
Sl_MRdErr : out std_logic_vector(0 to (C_SPLB_NUM_MASTERS-1));
Sl_MIRQ : out std_logic_vector(0 to (C_SPLB_NUM_MASTERS-1));
MPLB_Clk : in std_logic;
MPLB_Rst : in std_logic;
M_request : out std_logic;
M_priority : out std_logic_vector(0 to 1);
M_busLock : out std_logic;
M_RNW : out std_logic;
M_BE : out std_logic_vector(0 to ((C_MPLB_DWIDTH/8)-1));
M_MSize : out std_logic_vector(0 to 1);
M_size : out std_logic_vector(0 to 3);
M_type : out std_logic_vector(0 to 2);
M_ABus : out std_logic_vector(0 to C_MPLB_AWIDTH-1);
M_wrBurst : out std_logic;
M_rdBurst : out std_logic;
M_wrDBus : out std_logic_vector(0 to (C_MPLB_DWIDTH-1));
PLB_MAddrAck : in std_logic;
PLB_MSSize : in std_logic_vector(0 to 1);
PLB_MRearbitrate : in std_logic;
PLB_MTimeout : in std_logic;
PLB_MRdErr : in std_logic;
PLB_MWrErr : in std_logic;
PLB_MRdDBus : in std_logic_vector(0 to (C_MPLB_DWIDTH-1));
PLB_MRdDAck : in std_logic;
PLB_MRdBTerm : in std_logic;
PLB_MWrDAck : in std_logic;
PLB_MWrBTerm : in std_logic;
M_TAttribute : out std_logic_vector(0 to 15);
M_lockErr : out std_logic;
M_abort : out std_logic;
M_UABus : out std_logic_vector(0 to C_MPLB_AWIDTH-1);
PLB_MBusy : in std_logic;
PLB_MIRQ : in std_logic;
PLB_MRdWdAddr : in std_logic_vector(0 to 3)
);
end component;
begin
ac1_mb_bridge : plbv46_plbv46_bridge
generic map (
C_NUM_ADDR_RNG => 1,
C_BRIDGE_BASEADDR => X"00000000",
C_BRIDGE_HIGHADDR => X"FFFFFFFF",
C_RNG0_BASEADDR => X"00000000",
C_RNG0_HIGHADDR => X"FFFFFFFF",
C_RNG1_BASEADDR => X"ffffffff",
C_RNG1_HIGHADDR => X"00000000",
C_RNG2_BASEADDR => X"ffffffff",
C_RNG2_HIGHADDR => X"00000000",
C_RNG3_BASEADDR => X"ffffffff",
C_RNG3_HIGHADDR => X"00000000",
C_SPLB_P2P => 0,
C_SPLB_MID_WIDTH => 4,
C_SPLB_NUM_MASTERS => 15,
C_SPLB_SMALLEST_MASTER => 64,
C_SPLB_BIGGEST_MASTER => 32,
C_SPLB_AWIDTH => 32,
C_SPLB_DWIDTH => 64,
C_MPLB_AWIDTH => 32,
C_MPLB_DWIDTH => 64,
C_SPLB_NATIVE_DWIDTH => 32,
C_MPLB_NATIVE_DWIDTH => 32,
C_MPLB_SMALLEST_SLAVE => 32,
C_BUS_CLOCK_RATIO => 1,
C_PREFETCH_TIMEOUT => 10,
C_FAMILY => "virtex5"
)
port map (
SPLB_Clk => SPLB_Clk,
SPLB_Rst => SPLB_Rst,
IP2INTC_Irpt => IP2INTC_Irpt,
PLB_ABus => PLB_ABus,
PLB_UABus => PLB_UABus,
PLB_PAValid => PLB_PAValid,
PLB_SAValid => PLB_SAValid,
PLB_rdPrim => PLB_rdPrim,
PLB_wrPrim => PLB_wrPrim,
PLB_masterID => PLB_masterID,
PLB_abort => PLB_abort,
PLB_busLock => PLB_busLock,
PLB_RNW => PLB_RNW,
PLB_BE => PLB_BE,
PLB_MSize => PLB_MSize,
PLB_size => PLB_size,
PLB_type => PLB_type,
PLB_lockErr => PLB_lockErr,
PLB_wrDBus => PLB_wrDBus,
PLB_wrBurst => PLB_wrBurst,
PLB_rdBurst => PLB_rdBurst,
PLB_wrPendReq => PLB_wrPendReq,
PLB_rdPendReq => PLB_rdPendReq,
PLB_wrPendPri => PLB_wrPendPri,
PLB_rdPendPri => PLB_rdPendPri,
PLB_reqPri => PLB_reqPri,
PLB_TAttribute => PLB_TAttribute,
Sl_addrAck => Sl_addrAck,
Sl_SSize => Sl_SSize,
Sl_wait => Sl_wait,
Sl_rearbitrate => Sl_rearbitrate,
Sl_wrDAck => Sl_wrDAck,
Sl_wrComp => Sl_wrComp,
Sl_wrBTerm => Sl_wrBTerm,
Sl_rdDBus => Sl_rdDBus,
Sl_rdWdAddr => Sl_rdWdAddr,
Sl_rdDAck => Sl_rdDAck,
Sl_rdComp => Sl_rdComp,
Sl_rdBTerm => Sl_rdBTerm,
Sl_MBusy => Sl_MBusy,
Sl_MWrErr => Sl_MWrErr,
Sl_MRdErr => Sl_MRdErr,
Sl_MIRQ => Sl_MIRQ,
MPLB_Clk => MPLB_Clk,
MPLB_Rst => MPLB_Rst,
M_request => M_request,
M_priority => M_priority,
M_busLock => M_busLock,
M_RNW => M_RNW,
M_BE => M_BE,
M_MSize => M_MSize,
M_size => M_size,
M_type => M_type,
M_ABus => M_ABus,
M_wrBurst => M_wrBurst,
M_rdBurst => M_rdBurst,
M_wrDBus => M_wrDBus,
PLB_MAddrAck => PLB_MAddrAck,
PLB_MSSize => PLB_MSSize,
PLB_MRearbitrate => PLB_MRearbitrate,
PLB_MTimeout => PLB_MTimeout,
PLB_MRdErr => PLB_MRdErr,
PLB_MWrErr => PLB_MWrErr,
PLB_MRdDBus => PLB_MRdDBus,
PLB_MRdDAck => PLB_MRdDAck,
PLB_MRdBTerm => PLB_MRdBTerm,
PLB_MWrDAck => PLB_MWrDAck,
PLB_MWrBTerm => PLB_MWrBTerm,
M_TAttribute => M_TAttribute,
M_lockErr => M_lockErr,
M_abort => M_abort,
M_UABus => M_UABus,
PLB_MBusy => PLB_MBusy,
PLB_MIRQ => PLB_MIRQ,
PLB_MRdWdAddr => PLB_MRdWdAddr
);
end architecture STRUCTURE;
| lgpl-3.0 | b0fa3e469be3280cd61a5fa2255b7468 | 0.591707 | 3.16142 | false | false | false | false |
jairov4/accel-oil | solution_spartan6/syn/vhdl/nfa_accept_samples_generic_hw_mul_16ns_8ns_24_4.vhd | 4 | 2,906 | -- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2013.4
-- Copyright (C) 2013 Xilinx Inc. All rights reserved.
--
-- ==============================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity nfa_accept_samples_generic_hw_mul_16ns_8ns_24_4_MulnS_0 is
port (
clk: in std_logic;
ce: in std_logic;
a: in std_logic_vector(16 - 1 downto 0);
b: in std_logic_vector(8 - 1 downto 0);
p: out std_logic_vector(24 - 1 downto 0));
end entity;
architecture behav of nfa_accept_samples_generic_hw_mul_16ns_8ns_24_4_MulnS_0 is
signal tmp_product : std_logic_vector(24 - 1 downto 0);
signal a_i : std_logic_vector(16 - 1 downto 0);
signal b_i : std_logic_vector(8 - 1 downto 0);
signal p_tmp : std_logic_vector(24 - 1 downto 0);
signal a_reg : std_logic_vector(16 - 1 downto 0);
signal b_reg : std_logic_vector(8 - 1 downto 0);
attribute keep : string;
attribute keep of a_i : signal is "true";
attribute keep of b_i : signal is "true";
signal buff0 : std_logic_vector(24 - 1 downto 0);
signal buff1 : std_logic_vector(24 - 1 downto 0);
begin
a_i <= a;
b_i <= b;
p <= p_tmp;
p_tmp <= buff1;
tmp_product <= std_logic_vector(resize(unsigned(a_reg) * unsigned(b_reg), 24));
process(clk)
begin
if (clk'event and clk = '1') then
if (ce = '1') then
a_reg <= a_i;
b_reg <= b_i;
buff0 <= tmp_product;
buff1 <= buff0;
end if;
end if;
end process;
end architecture;
Library IEEE;
use IEEE.std_logic_1164.all;
entity nfa_accept_samples_generic_hw_mul_16ns_8ns_24_4 is
generic (
ID : INTEGER;
NUM_STAGE : INTEGER;
din0_WIDTH : INTEGER;
din1_WIDTH : INTEGER;
dout_WIDTH : INTEGER);
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
ce : IN STD_LOGIC;
din0 : IN STD_LOGIC_VECTOR(din0_WIDTH - 1 DOWNTO 0);
din1 : IN STD_LOGIC_VECTOR(din1_WIDTH - 1 DOWNTO 0);
dout : OUT STD_LOGIC_VECTOR(dout_WIDTH - 1 DOWNTO 0));
end entity;
architecture arch of nfa_accept_samples_generic_hw_mul_16ns_8ns_24_4 is
component nfa_accept_samples_generic_hw_mul_16ns_8ns_24_4_MulnS_0 is
port (
clk : IN STD_LOGIC;
ce : IN STD_LOGIC;
a : IN STD_LOGIC_VECTOR;
b : IN STD_LOGIC_VECTOR;
p : OUT STD_LOGIC_VECTOR);
end component;
begin
nfa_accept_samples_generic_hw_mul_16ns_8ns_24_4_MulnS_0_U : component nfa_accept_samples_generic_hw_mul_16ns_8ns_24_4_MulnS_0
port map (
clk => clk,
ce => ce,
a => din0,
b => din1,
p => dout);
end architecture;
| lgpl-3.0 | 9fcb1890cc294f0995d91bc56af45b8f | 0.560564 | 3.228889 | false | false | false | false |
grwlf/vsim | vhdl_ct/ct00347.vhd | 1 | 2,635 | -------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
-------------------------------------------------------------------------------
--
-- TEST NAME:
--
-- CT00347
--
-- AUTHOR:
--
-- D. Hyman
--
-- TEST OBJECTIVES:
--
-- 6.5 (1)
-- 6.5 (2)
-- 6.5 (4)
-- 6.5 (5)
-- 6.5 (6)
-- 6.5 (7)
-- 6.5 (8)
--
-- DESIGN UNIT ORDERING:
--
-- ENT00347(ARCH00347)
-- ENT00347_Test_Bench(ARCH00347_Test_Bench)
--
-- REVISION HISTORY:
--
-- 30-JUL-1987 - initial revision
--
-- NOTES:
--
-- self-checking
--
use WORK.STANDARD_TYPES.all ;
entity ENT00347 is
generic ( g : integer := 5 ) ;
begin
end ENT00347 ;
architecture ARCH00347 of ENT00347 is
signal s : st_integer_vector := c_st_integer_vector_1 ;
begin
P :
process ( s )
variable a : st_integer_vector := c_st_integer_vector_2 ;
variable b : st_integer_vector := c_st_integer_vector_1 ;
variable i1,i2,i3,i4,i5,j : integer := 3 ;
variable n : integer := 0 ;
begin
if n = 0 then
s (2 to 4) <= a (2 to 4) after 1 ns; -- this tests 6.5 (1)
n := 1 ;
else
b (2 to 4) := a (2 to 4) ; -- this tests 6.5 (2)
i1 := bf_integer( a(4 to 2)) ; -- this tests 6.5 (4)
i2 := bf_integer( a(1 downto 2)) ; -- this tests 6.5 (5)
i3 := bf_integer( a(2 to 4)) ; -- this tests 6.5 (6)
i4 := bf_integer( a(2 to g)) ; -- this tests 6.5 (7)
i5 := bf_integer( a(2 to j)) ; -- this tests 6.5 (8)
test_report ( "ARCH00347" ,
"Slice names" ,
(i1 = integer'left)
and (i2 = integer'left)
and (i3 = 3 * c_integer_2)
and (i4 = 4 * c_integer_2)
and (i5 = 2 * c_integer_2)
and (b(1) = c_integer_1)
and (b(2) = c_integer_2)
and (b(3) = c_integer_2)
and (b(4) = c_integer_2)
and (b(5) = c_integer_1)
and (s(1) = c_integer_1)
and (s(2) = c_integer_2)
and (s(3) = c_integer_2)
and (s(4) = c_integer_2)
and (s(5) = c_integer_1)
) ;
end if ;
end process P ;
end ARCH00347 ;
entity ENT00347_Test_Bench is
end ENT00347_Test_Bench ;
architecture ARCH00347_Test_Bench of ENT00347_Test_Bench is
begin
L1:
block
component UUT
end component ;
for CIS1 : UUT use entity WORK.ENT00347 ( ARCH00347 ) ;
begin
CIS1 : UUT ;
end block L1 ;
end ARCH00347_Test_Bench ;
| gpl-3.0 | 91f6a3f79a146092a73fee5524efd96f | 0.462998 | 2.970688 | false | true | false | false |
wsoltys/AtomFpga | src/AtomGodilVideo/src/Top.vhd | 1 | 13,281 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 14:42:09 02/09/2013
-- Design Name:
-- Module Name: Top - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.all;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
use IEEE.NUMERIC_STD.all;
use IEEE.STD_LOGIC_UNSIGNED.all;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity Top is
port (
-- Standard 6847 signals
--
-- expept DA which is now input only
-- except nRP which re-purposed as a nWR
CLK : in std_logic;
DD : inout std_logic_vector (7 downto 0);
DA : in std_logic_vector (12 downto 0);
CHB : out std_logic;
OA : out std_logic;
OB : out std_logic;
nMS : in std_logic;
CSS : in std_logic;
nHS : out std_logic;
nFS : out std_logic;
nWR : in std_logic; -- Was nRP
AG : in std_logic;
AS : in std_logic;
INV : in std_logic;
INTEXT : in std_logic;
GM : in std_logic_vector (2 downto 0);
Y : out std_logic;
-- 5 bit VGA Output
R : out std_logic_vector (0 downto 0);
G : out std_logic_vector (1 downto 0);
B : out std_logic_vector (0 downto 0);
HSYNC : out std_logic;
VSYNC : out std_logic;
-- 1 bit AUDIO Output
AUDIO : out std_logic;
-- Other GODIL specific pins
clock49 : in std_logic;
nRST : in std_logic;
nBXXX : in std_logic;
-- Jumpers
-- Enables VGA Signals on PL4
nPL4 : in std_logic;
-- Moves SID from 9FE0 to BDC0
nSIDD : in std_logic;
-- Active low version of the SID Select Signal for disabling the external bus buffers
-- nSIDSEL : out std_logic;
-- PS/2 Mouse
PS2_CLK : inout std_logic;
PS2_DATA : inout std_logic;
-- UART
uart_TxD : out std_logic;
uart_RxD : in std_logic
);
end Top;
architecture BEHAVIORAL of Top is
-- clock32 is the main clock
signal clock32 : std_logic;
-- clock25 is a full speed VGA clock
signal clock25 : std_logic;
-- clock15 is just used between two DCMs
signal clock15 : std_logic;
-- Reset signal (active high)
signal reset : std_logic;
-- Reset signal to 6847 (active high), not currently used
signal reset_vid : std_logic;
-- pipelined versions of the address/data/write signals
signal nWR1 : std_logic;
signal nWR2 : std_logic;
signal nMS1 : std_logic;
signal nMS2 : std_logic;
signal nWRMS1 : std_logic;
signal nWRMS2 : std_logic;
signal nBXXX1 : std_logic;
signal nBXXX2 : std_logic;
signal DA1 : std_logic_vector (12 downto 0);
signal DA2 : std_logic_vector (12 downto 0);
signal DD1 : std_logic_vector (7 downto 0);
signal DD2 : std_logic_vector (7 downto 0);
signal DD3 : std_logic_vector (7 downto 0);
signal ram_we : std_logic;
signal addr : std_logic_vector (12 downto 0);
signal din : std_logic_vector (7 downto 0);
-- Dout back to the Atom, that is either VRAM or SID
signal dout : std_logic_vector (7 downto 0);
-- SID sigmals
signal sid_cs : std_logic;
signal sid_we : std_logic;
signal sid_audio : std_logic;
-- UART sigmals
signal uart_cs : std_logic;
signal uart_we : std_logic;
-- Atom extension register signals
signal reg_cs : std_logic;
signal reg_we : std_logic;
signal final_red : std_logic;
signal final_green1 : std_logic;
signal final_green0 : std_logic;
signal final_blue : std_logic;
signal final_vsync : std_logic;
signal final_hsync : std_logic;
signal final_char_a : std_logic_vector (10 downto 0);
component DCM0
port(
CLKIN_IN : in std_logic;
CLK0_OUT : out std_logic;
CLK0_OUT1 : out std_logic;
CLK2X_OUT : out std_logic
);
end component;
component DCMSID0
port(
CLKIN_IN : in std_logic;
CLK0_OUT : out std_logic;
CLK0_OUT1 : out std_logic;
CLK2X_OUT : out std_logic
);
end component;
component DCMSID1
port(
CLKIN_IN : in std_logic;
CLK0_OUT : out std_logic;
CLK0_OUT1 : out std_logic;
CLK2X_OUT : out std_logic
);
end component;
component AtomGodilVideo
generic (
CImplGraphicsExt : boolean;
CImplSoftChar : boolean;
CImplSID : boolean;
CImplVGA80x40 : boolean;
CImplHWScrolling : boolean;
CImplMouse : boolean;
CImplUart : boolean;
MainClockSpeed : integer;
DefaultBaud : integer
);
port (
-- clock_vga is a full speed VGA clock (25MHz ish)
clock_vga : in std_logic;
-- clock_main is the main clock
clock_main : in std_logic;
-- A fixed 32MHz clock for the SID
clock_sid_32MHz : in std_logic;
-- As fast a clock as possible for the SID DAC
clock_sid_dac : in std_logic;
-- Reset signal (active high)
reset : in std_logic;
-- Reset signal to 6847 (active high), not currently used
reset_vid : in std_logic;
-- Main Address / Data Bus
din : in std_logic_vector (7 downto 0);
dout : out std_logic_vector (7 downto 0);
addr : in std_logic_vector (12 downto 0);
-- 6847 Control Signals
CSS : in std_logic;
AG : in std_logic;
GM : in std_logic_vector (2 downto 0);
nFS : out std_logic;
-- RAM signals
ram_we : in std_logic;
-- SID signals
reg_cs : in std_logic;
reg_we : in std_logic;
-- SID signals
sid_cs : in std_logic;
sid_we : in std_logic;
sid_audio : out std_logic;
-- PS/2 Mouse
PS2_CLK : inout std_logic;
PS2_DATA : inout std_logic;
-- UART signals
uart_cs : in std_logic;
uart_we : in std_logic;
uart_RxD : in std_logic;
uart_TxD : out std_logic;
uart_escape : out std_logic;
uart_break : out std_logic;
-- VGA Signals
final_red : out std_logic;
final_green1 : out std_logic;
final_green0 : out std_logic;
final_blue : out std_logic;
final_vsync : out std_logic;
final_hsync : out std_logic
);
end component;
begin
reset <= not nRST;
reset_vid <= '0';
-- Currently set at 49.152 * 8 / 31 = 12.684MHz
-- half VGA should be 25.175 / 2 = 12. 5875
-- we could get closer with to cascaded multipliers
Inst_DCM0 : DCM0
port map (
CLKIN_IN => clock49,
CLK0_OUT => clock25,
CLK0_OUT1 => open,
CLK2X_OUT => open
);
Inst_DCMSID0 : DCMSID0
port map (
CLKIN_IN => clock49,
CLK0_OUT => clock15,
CLK0_OUT1 => open,
CLK2X_OUT => open
);
Inst_DCMSID1 : DCMSID1
port map (
CLKIN_IN => clock15,
CLK0_OUT => clock32,
CLK0_OUT1 => open,
CLK2X_OUT => open
);
Inst_AtomGodilVideo : AtomGodilVideo
generic map (
CImplGraphicsExt => true,
CImplSoftChar => true,
CImplSID => true,
CImplVGA80x40 => true,
CImplHWScrolling => true,
CImplMouse => true,
CImplUart => true,
MainClockSpeed => 32000000,
DefaultBaud => 115200
)
port map (
clock_vga => clock25,
clock_main => clock32,
clock_sid_32Mhz => clock32,
clock_sid_dac => clock49,
reset => reset,
reset_vid => reset_vid,
din => din,
dout => dout,
addr => addr,
CSS => CSS,
AG => AG,
GM => GM,
nFS => nFS,
ram_we => ram_we,
reg_cs => reg_cs,
reg_we => reg_we,
sid_cs => sid_cs,
sid_we => sid_we,
sid_audio => sid_audio,
PS2_CLK => PS2_CLK,
PS2_DATA => PS2_DATA,
uart_cs => uart_cs,
uart_we => uart_we,
uart_RxD => uart_RxD,
uart_TxD => uart_TxD,
uart_escape => open,
uart_break => open,
final_red => final_red,
final_green1 => final_green1,
final_green0 => final_green0,
final_blue => final_blue,
final_vsync => final_vsync,
final_hsync => final_hsync
);
-- Pipelined version of address/data/write signals
process (clock32)
begin
if rising_edge(clock32) then
nBXXX2 <= nBXXX1;
nBXXX1 <= nBXXX;
nMS2 <= nMS1;
nMS1 <= nMS;
nWRMS2 <= nWRMS1;
nWRMS1 <= nWR or nMS;
nWR2 <= nWR1;
nWR1 <= nWR;
DD3 <= DD2;
DD2 <= DD1;
DD1 <= DD;
DA2 <= DA1;
DA1 <= DA;
end if;
end process;
-- Signals driving the VRAM
-- Write just before the rising edge of nWR
ram_we <= '1' when (nWRMS1 = '1' and nWRMS2 = '0' and nBXXX2 = '1') else '0';
din <= DD3;
addr <= DA2;
-- Signals driving the internal registers
-- When nSIDD=0 the registers are mapped to BDE0-BDFF
-- When nSIDD=1 the registers are mapped to 9FE0-9FFF
reg_cs <= '1' when (nSIDD = '1' and nMS2 = '0' and DA2(12 downto 5) = "11111111") or
(nSIDD = '0' and nBXXX2 = '0' and DA2(11 downto 5) = "1101111")
else '0';
reg_we <= '1' when (nSIDD = '1' and nWRMS1 = '1' and nWRMS2 = '0') or
(nSIDD = '0' and nWR1 = '1' and nWR2 = '0')
else '0';
-- Signals driving the SID
-- When nSIDD=0 the SID is mapped to BDC0-BDDF
-- When nSIDD=1 the SID is mapped to 9FC0-9FDF
sid_cs <= '1' when (nSIDD = '1' and nMS2 = '0' and DA2(12 downto 5) = "11111110") or
(nSIDD = '0' and nBXXX2 = '0' and DA2(11 downto 5) = "1101110")
else '0';
sid_we <= '1' when (nSIDD = '1' and nWRMS1 = '1' and nWRMS2 = '0') or
(nSIDD = '0' and nWR1 = '1' and nWR2 = '0')
else '0';
-- Signals driving the UART
-- When nSIDD=0 the UART is mapped to BDB0-BDBF
-- When nSIDD=1 the UART is mapped to 9FB0-9FBF
uart_cs <= '1' when (nSIDD = '1' and nMS2 = '0' and DA2(12 downto 4) = "111111011") or
(nSIDD = '0' and nBXXX2 = '0' and DA2(11 downto 4) = "11011011")
else '0';
uart_we <= '1' when (nSIDD = '1' and nWRMS1 = '1' and nWRMS2 = '0') or
(nSIDD = '0' and nWR1 = '1' and nWR2 = '0')
else '0';
AUDIO <= sid_audio;
-- Output the SID Select Signal so it can be used to disable the bus buffers
-- TODO: this looks incorrect
-- nSIDSEL <= not sid_cs;
-- Tri-state data back to the Atom
DD <= dout when (nMS = '0' and nWR = '1') else (others => 'Z');
-- 1/1/1 Bit RGB Video to PL4 Connectors
OA <= final_red when nPL4 = '0' else '0';
CHB <= final_green1 when nPL4 = '0' else '0';
OB <= final_blue when nPL4 = '0' else '0';
nHS <= final_hsync when nPL4 = '0' else '0';
Y <= final_vsync when nPL4 = '0' else '0';
-- 1/2/1 Bit RGB Video to GODIL Test Connector
R(0) <= final_red;
G(1) <= final_green1;
G(0) <= final_green0;
B(0) <= final_blue;
VSYNC <= final_vsync;
HSYNC <= final_hsync;
end BEHAVIORAL;
| apache-2.0 | d9fa56a9855cbf4eff51c108e79fbab9 | 0.48272 | 3.705636 | false | false | false | false |
grwlf/vsim | vhdl_ct/ct00050.vhd | 1 | 3,127 | -- NEED RESULT: ARCH00050.P1: If statement with no else or elsif passed
-- NEED RESULT: ARCH00050.P2: If statement with no else passed
-- NEED RESULT: ARCH00050.P3: If statement with else passed
-- NEED RESULT: ARCH00050.P4: If statement with else passed
-------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
-------------------------------------------------------------------------------
--
-- TEST NAME:
--
-- CT00050
--
-- AUTHOR:
--
-- G. Tominovich
--
-- TEST OBJECTIVES:
--
-- 8.6 (1)
--
-- DESIGN UNIT ORDERING:
--
-- E00000(ARCH00050)
-- ENT00050_Test_Bench(ARCH00050_Test_Bench)
--
-- REVISION HISTORY:
--
-- 01-JUL-1987 - initial revision
--
-- NOTES:
--
-- self-checking
-- automatically generated
--
use WORK.STANDARD_TYPES.all ;
architecture ARCH00050 of E00000 is
signal Dummy : Boolean := false ;
--
begin
P1_1 :
process ( Dummy )
variable v_integer : integer :=
c_integer_1 ;
--
variable correct : boolean := false;
begin
if v_integer = c_integer_1 then
correct := true ;
end if ;
test_report ( "ARCH00050.P1",
"If statement with no else or elsif",
correct) ;
end process P1_1 ;
--
P2_1 :
process ( Dummy )
variable v_integer : integer :=
c_integer_1 ;
--
variable correct : boolean := false;
begin
if v_integer = c_integer_1 then
correct := true ;
elsif v_integer /= c_integer_1 then
correct := false ;
end if ;
test_report ( "ARCH00050.P2",
"If statement with no else",
correct) ;
end process P2_1 ;
--
P3_1 :
process ( Dummy )
variable v_integer : integer :=
c_integer_1 ;
--
variable correct : boolean := false;
begin
if false then
correct := false ;
elsif v_integer /= c_integer_1 then
correct := false ;
else
correct := true ;
end if ;
test_report ( "ARCH00050.P3",
"If statement with else",
correct) ;
end process P3_1 ;
--
P4_1 :
process ( Dummy )
variable v_integer : integer :=
c_integer_1 ;
--
variable correct : boolean := false;
begin
if v_integer /= c_integer_1 then
correct := false ;
else
correct := true ;
end if ;
test_report ( "ARCH00050.P4",
"If statement with else",
correct) ;
end process P4_1 ;
--
--
--
end ARCH00050 ;
--
entity ENT00050_Test_Bench is
end ENT00050_Test_Bench ;
--
architecture ARCH00050_Test_Bench of ENT00050_Test_Bench is
begin
L1:
block
component UUT
end component ;
for CIS1 : UUT use entity WORK.E00000 ( ARCH00050 ) ;
begin
CIS1 : UUT ;
end block L1 ;
end ARCH00050_Test_Bench ;
| gpl-3.0 | 2468c3153f4a451997ae23ed8c8b7e83 | 0.50016 | 3.772014 | false | true | false | false |
grwlf/vsim | vhdl_ct/ct00251.vhd | 1 | 4,697 | -- NEED RESULT: ENT00251: Open scalar out ports with static subtypes passed
-------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
-------------------------------------------------------------------------------
--
-- TEST NAME:
--
-- CT00251
--
-- AUTHOR:
--
-- A. Wilmot
--
-- TEST OBJECTIVES:
--
-- 1.1.1.2 (3)
--
-- DESIGN UNIT ORDERING:
--
-- ENT00251(ARCH00251)
-- ENT00251_Test_Bench(ARCH00251_Test_Bench)
--
-- REVISION HISTORY:
--
-- 25-JUN-1987 - initial revision
--
-- NOTES:
--
-- self-checking
-- automatically generated
--
use WORK.STANDARD_TYPES.all ;
entity ENT00251 is
port (
toggle : out switch ;
i_boolean_1, i_boolean_2 : out boolean
:= c_boolean_1
;
i_bit_1, i_bit_2 : out bit
:= c_bit_1
;
i_severity_level_1, i_severity_level_2 : out severity_level
:= c_severity_level_1
;
i_character_1, i_character_2 : out character
:= c_character_1
;
i_t_enum1_1, i_t_enum1_2 : out t_enum1
:= c_t_enum1_1
;
i_st_enum1_1, i_st_enum1_2 : out st_enum1
:= c_st_enum1_1
;
i_integer_1, i_integer_2 : out integer
:= c_integer_1
;
i_t_int1_1, i_t_int1_2 : out t_int1
:= c_t_int1_1
;
i_st_int1_1, i_st_int1_2 : out st_int1
:= c_st_int1_1
;
i_time_1, i_time_2 : out time
:= c_time_1
;
i_t_phys1_1, i_t_phys1_2 : out t_phys1
:= c_t_phys1_1
;
i_st_phys1_1, i_st_phys1_2 : out st_phys1
:= c_st_phys1_1
;
i_real_1, i_real_2 : out real
:= c_real_1
;
i_t_real1_1, i_t_real1_2 : out t_real1
:= c_t_real1_1
;
i_st_real1_1, i_st_real1_2 : out st_real1
:= c_st_real1_1
) ;
begin
end ENT00251 ;
--
architecture ARCH00251 of ENT00251 is
begin
process
variable correct : boolean := true ;
begin
--
toggle <= up ;
i_boolean_1 <= c_boolean_2 ;
i_boolean_2 <= c_boolean_2 ;
i_bit_1 <= c_bit_2 ;
i_bit_2 <= c_bit_2 ;
i_severity_level_1 <= c_severity_level_2 ;
i_severity_level_2 <= c_severity_level_2 ;
i_character_1 <= c_character_2 ;
i_character_2 <= c_character_2 ;
i_t_enum1_1 <= c_t_enum1_2 ;
i_t_enum1_2 <= c_t_enum1_2 ;
i_st_enum1_1 <= c_st_enum1_2 ;
i_st_enum1_2 <= c_st_enum1_2 ;
i_integer_1 <= c_integer_2 ;
i_integer_2 <= c_integer_2 ;
i_t_int1_1 <= c_t_int1_2 ;
i_t_int1_2 <= c_t_int1_2 ;
i_st_int1_1 <= c_st_int1_2 ;
i_st_int1_2 <= c_st_int1_2 ;
i_time_1 <= c_time_2 ;
i_time_2 <= c_time_2 ;
i_t_phys1_1 <= c_t_phys1_2 ;
i_t_phys1_2 <= c_t_phys1_2 ;
i_st_phys1_1 <= c_st_phys1_2 ;
i_st_phys1_2 <= c_st_phys1_2 ;
i_real_1 <= c_real_2 ;
i_real_2 <= c_real_2 ;
i_t_real1_1 <= c_t_real1_2 ;
i_t_real1_2 <= c_t_real1_2 ;
i_st_real1_1 <= c_st_real1_2 ;
i_st_real1_2 <= c_st_real1_2 ;
test_report ( "ENT00251" ,
"Open scalar out ports with static subtypes" ,
correct) ;
wait ;
end process ;
end ARCH00251 ;
--
use WORK.STANDARD_TYPES.all ;
entity ENT00251_Test_Bench is
end ENT00251_Test_Bench ;
--
architecture ARCH00251_Test_Bench of ENT00251_Test_Bench is
begin
L1:
block
--
signal toggle : switch ;
--
component UUT
end component ;
--
for CIS1 : UUT use entity WORK.ENT00251 ( ARCH00251 )
port map (
toggle ,
open, open,
open, open,
open, open,
open, open,
open, open,
open, open,
open, open,
open, open,
open, open,
open, open,
open, open,
open, open,
open, open,
open, open,
open, open
) ;
--
begin
CIS1 : UUT ;
end block L1 ;
end ARCH00251_Test_Bench ;
| gpl-3.0 | 395b70014e5e561c78e0212fa824c89d | 0.418991 | 3.160834 | false | true | false | false |
jairov4/accel-oil | solution_kintex7/sim/vhdl/AESL_autobus_nfa_initials_buckets.vhd | 1 | 28,977 | library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
use IEEE.numeric_std.all;
use ieee.std_logic_textio.all;
use std.textio.all;
library work;
use work.all;
entity AESL_autobus_nfa_initials_buckets is
generic (
constant TV_IN : STRING (1 to 81) := "../tv/cdatafile/c.nfa_accept_samples_generic_hw.autotvin_nfa_initials_buckets.dat";
constant TV_OUT : STRING (1 to 86) := "../tv/rtldatafile/rtl.nfa_accept_samples_generic_hw.autotvout_nfa_initials_buckets.dat";
constant DATA_WIDTH : INTEGER := 32;
constant ADDR_WIDTH : INTEGER := 32;
constant DEPTH : INTEGER := 2;
constant FIFO_DEPTH : INTEGER := 32;
constant FIFO_DEPTH_ADDR_WIDTH : INTEGER := 32
);
port (
clk : IN STD_LOGIC;
rst : IN STD_LOGIC;
bus_req_RW : IN STD_LOGIC;
bus_req_full_n : OUT STD_LOGIC;
bus_req_RW_en : IN STD_LOGIC;
bus_rsp_empty_n : OUT STD_LOGIC;
bus_rsp_read : IN STD_LOGIC;
bus_address : IN STD_LOGIC_VECTOR (ADDR_WIDTH - 1 downto 0);
bus_din : IN STD_LOGIC_VECTOR (DATA_WIDTH - 1 downto 0);
bus_dout : OUT STD_LOGIC_VECTOR (DATA_WIDTH - 1 downto 0);
bus_size : IN STD_LOGIC_VECTOR ( 31 downto 0);
ready : IN STD_LOGIC;
done : IN STD_LOGIC
);
end AESL_autobus_nfa_initials_buckets;
architecture behav of AESL_autobus_nfa_initials_buckets is
-- Inner signals
signal FIFO_req_ptr_r : STD_LOGIC_VECTOR (FIFO_DEPTH_ADDR_WIDTH - 1 downto 0) := (others => '0');
signal FIFO_req_ptr_w : STD_LOGIC_VECTOR (FIFO_DEPTH_ADDR_WIDTH - 1 downto 0) := (others => '0');
signal FIFO_req_flag : STD_LOGIC := '0'; -- 0: empty hint, 1: full hint
signal FIFO_req_empty : STD_LOGIC := '0';
signal FIFO_req_full : STD_LOGIC := '0';
signal FIFO_req_read : STD_LOGIC := '0';
signal FIFO_req_burst_flag:STD_LOGIC := '0';
signal FIFO_rsp_ptr_r : STD_LOGIC_VECTOR (ADDR_WIDTH - 1 downto 0) := (others => '0');
signal FIFO_rsp_ptr_w : STD_LOGIC_VECTOR (ADDR_WIDTH - 1 downto 0) := (others => '0');
signal FIFO_rsp_flag : STD_LOGIC := '0';
signal FIFO_rsp_empty : STD_LOGIC;
signal FIFO_rsp_full : STD_LOGIC;
signal FIFO_rsp_write : STD_LOGIC;
signal FIFO_req_temp_state : STD_LOGIC_VECTOR(1 downto 0) := "00";
type arr_fifo_req_RW is array(0 to FIFO_DEPTH - 1) of STD_LOGIC;
type arr_fifo_req_addr is array(0 to FIFO_DEPTH - 1) of STD_LOGIC_VECTOR(ADDR_WIDTH - 1 downto 0);
type arr_fifo_req_din is array(0 to FIFO_DEPTH - 1) of STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0);
type arr_fifo_req_size is array(0 to FIFO_DEPTH - 1) of STD_LOGIC_VECTOR(31 downto 0);
type arr_mem is array(0 to DEPTH - 1) of STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0);
shared variable FIFO_req_RW : arr_fifo_req_RW;
shared variable FIFO_req_address: arr_fifo_req_addr;
shared variable FIFO_req_din : arr_fifo_req_din;
shared variable FIFO_req_size : arr_fifo_req_size;
shared variable mem : arr_mem := (others => (others => '0'));
shared variable FIFO_rsp_mem : arr_mem := (others => (others => '0'));
procedure esl_read_token (file textfile: TEXT; textline: inout LINE; token: out STRING; token_len: out INTEGER) is
variable whitespace : CHARACTER;
variable i : INTEGER;
variable ok: BOOLEAN;
variable buff: STRING(1 to token'length);
begin
ok := false;
i := 1;
loop_main: while not endfile(textfile) loop
if textline = null or textline'length = 0 then
readline(textfile, textline);
end if;
loop_remove_whitespace: while textline'length > 0 loop
if textline(textline'left) = ' ' or
textline(textline'left) = HT or
textline(textline'left) = CR or
textline(textline'left) = LF then
read(textline, whitespace);
else
exit loop_remove_whitespace;
end if;
end loop;
loop_aesl_read_token: while textline'length > 0 and i <= buff'length loop
if textline(textline'left) = ' ' or
textline(textline'left) = HT or
textline(textline'left) = CR or
textline(textline'left) = LF then
exit loop_aesl_read_token;
else
read(textline, buff(i));
i := i + 1;
end if;
ok := true;
end loop;
if ok = true then
exit loop_main;
end if;
end loop;
buff(i) := ' ';
token := buff;
token_len:= i-1;
end procedure esl_read_token;
procedure esl_read_token (file textfile: TEXT;
textline: inout LINE;
token: out STRING) is
variable i : INTEGER;
begin
esl_read_token (textfile, textline, token, i);
end procedure esl_read_token;
function esl_add(v1, v2 : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
variable res : unsigned(v1'length-1 downto 0);
begin
res := unsigned(v1) + unsigned(v2);
return std_logic_vector(res);
end function;
function esl_sub(v1, v2 : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
variable res : unsigned(v1'length-1 downto 0);
begin
res := unsigned(v1) - unsigned(v2);
return std_logic_vector(res);
end function;
function esl_str2lv_hex (RHS : STRING; data_width : INTEGER) return STD_LOGIC_VECTOR is
variable ret : STD_LOGIC_VECTOR(data_width - 1 downto 0);
variable idx : integer := 3;
begin
ret := (others => '0');
if(RHS(1) /= '0' and (RHS(2) /= 'x' or RHS(2) /= 'X')) then
report "Error! The format of hex number is not initialed by 0x";
end if;
while true loop
if (data_width > 4) then
case RHS(idx) is
when '0' => ret := ret(data_width - 5 downto 0) & "0000";
when '1' => ret := ret(data_width - 5 downto 0) & "0001";
when '2' => ret := ret(data_width - 5 downto 0) & "0010";
when '3' => ret := ret(data_width - 5 downto 0) & "0011";
when '4' => ret := ret(data_width - 5 downto 0) & "0100";
when '5' => ret := ret(data_width - 5 downto 0) & "0101";
when '6' => ret := ret(data_width - 5 downto 0) & "0110";
when '7' => ret := ret(data_width - 5 downto 0) & "0111";
when '8' => ret := ret(data_width - 5 downto 0) & "1000";
when '9' => ret := ret(data_width - 5 downto 0) & "1001";
when 'a' | 'A' => ret := ret(data_width - 5 downto 0) & "1010";
when 'b' | 'B' => ret := ret(data_width - 5 downto 0) & "1011";
when 'c' | 'C' => ret := ret(data_width - 5 downto 0) & "1100";
when 'd' | 'D' => ret := ret(data_width - 5 downto 0) & "1101";
when 'e' | 'E' => ret := ret(data_width - 5 downto 0) & "1110";
when 'f' | 'F' => ret := ret(data_width - 5 downto 0) & "1111";
when ' ' => return ret;
when others => report "Wrong hex char " & RHS(idx); return ret;
end case;
elsif (data_width = 4) then
case RHS(idx) is
when '0' => ret := "0000";
when '1' => ret := "0001";
when '2' => ret := "0010";
when '3' => ret := "0011";
when '4' => ret := "0100";
when '5' => ret := "0101";
when '6' => ret := "0110";
when '7' => ret := "0111";
when '8' => ret := "1000";
when '9' => ret := "1001";
when 'a' | 'A' => ret := "1010";
when 'b' | 'B' => ret := "1011";
when 'c' | 'C' => ret := "1100";
when 'd' | 'D' => ret := "1101";
when 'e' | 'E' => ret := "1110";
when 'f' | 'F' => ret := "1111";
when ' ' => return ret;
when others => report "Wrong hex char " & RHS(idx); return ret;
end case;
elsif (data_width = 3) then
case RHS(idx) is
when '0' => ret := "000";
when '1' => ret := "001";
when '2' => ret := "010";
when '3' => ret := "011";
when '4' => ret := "100";
when '5' => ret := "101";
when '6' => ret := "110";
when '7' => ret := "111";
when ' ' => return ret;
when others => report "Wrong hex char " & RHS(idx); return ret;
end case;
elsif (data_width = 2) then
case RHS(idx) is
when '0' => ret := "00";
when '1' => ret := "01";
when '2' => ret := "10";
when '3' => ret := "11";
when ' ' => return ret;
when others => report "Wrong hex char " & RHS(idx); return ret;
end case;
elsif (data_width = 1) then
case RHS(idx) is
when '0' => ret := "0";
when '1' => ret := "1";
when ' ' => return ret;
when others => report "Wrong hex char " & RHS(idx); return ret;
end case;
else
report string'("Wrong data_width.");
return ret;
end if;
idx := idx + 1;
end loop;
return ret;
end function;
function esl_conv_string_hex (lv : STD_LOGIC_VECTOR) return STRING is
constant str_len : integer := (lv'length + 3)/4;
variable ret : STRING (1 to str_len);
variable i, tmp: INTEGER;
variable normal_lv : STD_LOGIC_VECTOR(lv'length - 1 downto 0);
variable tmp_lv : STD_LOGIC_VECTOR(3 downto 0);
begin
normal_lv := lv;
for i in 1 to str_len loop
if(i = 1) then
if((lv'length mod 4) = 3) then
tmp_lv(2 downto 0) := normal_lv(lv'length - 1 downto lv'length - 3);
case tmp_lv(2 downto 0) is
when "000" => ret(i) := '0';
when "001" => ret(i) := '1';
when "010" => ret(i) := '2';
when "011" => ret(i) := '3';
when "100" => ret(i) := '4';
when "101" => ret(i) := '5';
when "110" => ret(i) := '6';
when "111" => ret(i) := '7';
when others => ret(i) := '0';
end case;
elsif((lv'length mod 4) = 2) then
tmp_lv(1 downto 0) := normal_lv(lv'length - 1 downto lv'length - 2);
case tmp_lv(1 downto 0) is
when "00" => ret(i) := '0';
when "01" => ret(i) := '1';
when "10" => ret(i) := '2';
when "11" => ret(i) := '3';
when others => ret(i) := '0';
end case;
elsif((lv'length mod 4) = 1) then
tmp_lv(0 downto 0) := normal_lv(lv'length - 1 downto lv'length - 1);
case tmp_lv(0 downto 0) is
when "0" => ret(i) := '0';
when "1" => ret(i) := '1';
when others=> ret(i) := '0';
end case;
elsif((lv'length mod 4) = 0) then
tmp_lv(3 downto 0) := normal_lv(lv'length - 1 downto lv'length - 4);
case tmp_lv(3 downto 0) is
when "0000" => ret(i) := '0';
when "0001" => ret(i) := '1';
when "0010" => ret(i) := '2';
when "0011" => ret(i) := '3';
when "0100" => ret(i) := '4';
when "0101" => ret(i) := '5';
when "0110" => ret(i) := '6';
when "0111" => ret(i) := '7';
when "1000" => ret(i) := '8';
when "1001" => ret(i) := '9';
when "1010" => ret(i) := 'a';
when "1011" => ret(i) := 'b';
when "1100" => ret(i) := 'c';
when "1101" => ret(i) := 'd';
when "1110" => ret(i) := 'e';
when "1111" => ret(i) := 'f';
when others => ret(i) := '0';
end case;
end if;
else
tmp_lv(3 downto 0) := normal_lv((str_len - i) * 4 + 3 downto (str_len - i) * 4);
case tmp_lv(3 downto 0) is
when "0000" => ret(i) := '0';
when "0001" => ret(i) := '1';
when "0010" => ret(i) := '2';
when "0011" => ret(i) := '3';
when "0100" => ret(i) := '4';
when "0101" => ret(i) := '5';
when "0110" => ret(i) := '6';
when "0111" => ret(i) := '7';
when "1000" => ret(i) := '8';
when "1001" => ret(i) := '9';
when "1010" => ret(i) := 'a';
when "1011" => ret(i) := 'b';
when "1100" => ret(i) := 'c';
when "1101" => ret(i) := 'd';
when "1110" => ret(i) := 'e';
when "1111" => ret(i) := 'f';
when others => ret(i) := '0';
end case;
end if;
end loop;
return ret;
end function;
begin
-------------- Assignment for output port -------------------
assign_proc : process
begin
wait until (clk'event and clk = '1');
wait for 0.4 ns;
bus_dout <= FIFO_rsp_mem(CONV_INTEGER(FIFO_rsp_ptr_r));
end process;
bus_rsp_proc : process(FIFO_rsp_empty)
begin
bus_rsp_empty_n <= not FIFO_rsp_empty;
end process;
bus_req_full_n_proc : process(FIFO_req_full)
begin
bus_req_full_n <= not FIFO_req_full;
end process;
FIFO_req_empty_full_proc : process(FIFO_req_ptr_r, FIFO_req_ptr_w, FIFO_req_flag)
begin
if(FIFO_req_ptr_r = FIFO_req_ptr_w) then
if(FIFO_req_flag = '1') then
FIFO_req_full <= '1';
FIFO_req_empty <= '0';
else
FIFO_req_full <= '0';
FIFO_req_empty <= '1';
end if;
else
FIFO_req_full <= '0';
FIFO_req_empty <= '0';
end if;
end process;
FIFO_rsp_empty_full_proc : process(FIFO_rsp_ptr_r, FIFO_rsp_ptr_w, FIFO_rsp_flag)
begin
if(FIFO_rsp_ptr_r = FIFO_rsp_ptr_w) then
if(FIFO_rsp_flag = '1') then
FIFO_rsp_full <= '1';
FIFO_rsp_empty <= '0';
else
FIFO_rsp_full <= '0';
FIFO_rsp_empty <= '1';
end if;
else
FIFO_rsp_full <= '0';
FIFO_rsp_empty <= '0';
end if;
end process;
-- Push RTL's req into FIFO_req
FIFO_req_write_proc : process(clk, rst)
begin
if(rst = '1') then
FIFO_req_ptr_w <= (others => '0');
elsif (clk'event and clk = '1') then
if(bus_req_RW_en = '1' and FIFO_req_full = '0') then
FIFO_req_RW(CONV_INTEGER(FIFO_req_ptr_w)) := bus_req_RW;
FIFO_req_address(CONV_INTEGER(FIFO_req_ptr_w)) := bus_address;
FIFO_req_din(CONV_INTEGER(FIFO_req_ptr_w)) := bus_din;
FIFO_req_size(CONV_INTEGER(FIFO_req_ptr_w)) := bus_size;
if(CONV_INTEGER(FIFO_req_ptr_w) /= FIFO_DEPTH - 1) then
FIFO_req_ptr_w <= esl_add(FIFO_req_ptr_w,"1");
else
FIFO_req_ptr_w <= (others => '0');
end if;
end if;
end if;
end process;
FIFO_req_read_proc : process(clk, rst)
variable FIFO_req_RW_temp : STD_LOGIC;
variable FIFO_req_address_temp : STD_LOGIC_VECTOR(ADDR_WIDTH - 1 downto 0);
variable FIFO_req_din_temp : STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0);
variable FIFO_req_size_temp : STD_LOGIC_VECTOR(31 downto 0);
constant IDLE_STATE : STD_LOGIC_VECTOR(1 downto 0) := "00";
constant READ_BURST_STATE : STD_LOGIC_VECTOR(1 downto 0) := "01";
constant WRITE_BURST_STATE : STD_LOGIC_VECTOR(1 downto 0) := "10";
begin
if(rst = '1') then
FIFO_req_temp_state <= IDLE_STATE;
FIFO_req_read <= '0';
FIFO_rsp_write <= '0';
elsif (clk'event and clk = '1') then
case FIFO_req_temp_state is
when IDLE_STATE =>
if(FIFO_req_empty = '0' and FIFO_rsp_full = '0') then
FIFO_req_read <= '1';
if(CONV_INTEGER(FIFO_req_ptr_r) /= FIFO_DEPTH - 1) then
FIFO_req_ptr_r <= esl_add(FIFO_req_ptr_r, "1");
else
FIFO_req_ptr_r <= (others => '0');
end if;
FIFO_req_RW_temp:= FIFO_req_RW(CONV_INTEGER(FIFO_req_ptr_r));
FIFO_req_address_temp := FIFO_req_address(CONV_INTEGER(FIFO_req_ptr_r));
FIFO_req_din_temp := FIFO_req_din(CONV_INTEGER(FIFO_req_ptr_r));
FIFO_req_size_temp := FIFO_req_size(CONV_INTEGER(FIFO_req_ptr_r));
-- Read request
if(FIFO_req_RW_temp = '0') then
FIFO_rsp_write <= '1'; -- Indicate the output is valid
FIFO_rsp_mem(CONV_INTEGER(FIFO_rsp_ptr_w)) := mem(CONV_INTEGER(FIFO_req_address_temp));
if(FIFO_rsp_ptr_w /= DEPTH - 1) then
FIFO_rsp_ptr_w <= esl_add(FIFO_rsp_ptr_w,"1");
else
FIFO_rsp_ptr_w <= (others => '0');
end if;
if(CONV_INTEGER(FIFO_req_size_temp) /= 0 and CONV_INTEGER(FIFO_req_size_temp) /= 1) then -- Read burst request
FIFO_req_temp_state <= READ_BURST_STATE; -- To deal with the rest data
end if;
else
FIFO_rsp_write <= '0'; -- Indicate the output is not valid
if(CONV_INTEGER(FIFO_req_size_temp) = 0 or CONV_INTEGER(FIFO_req_size_temp) = 1) then -- Write single request
mem(CONV_INTEGER(FIFO_req_address_temp)) := FIFO_req_din_temp;
else -- Write burst request
mem(CONV_INTEGER(FIFO_req_address_temp)) := FIFO_req_din_temp; -- Input the first data
FIFO_req_temp_state <= WRITE_BURST_STATE; -- To deal with the rest data
end if;
end if;
else -- There is no request in the FIFO_req
FIFO_req_read <= '0';
FIFO_rsp_write <= '0';
end if;
when READ_BURST_STATE =>
FIFO_req_read <= '0'; -- Stop reading the next request
FIFO_req_size_temp := esl_sub(FIFO_req_size_temp, "1");
if(CONV_INTEGER(FIFO_req_address_temp) /= DEPTH - 1) then
FIFO_req_address_temp := esl_add(FIFO_req_address_temp, "1");
else
report "Burst read out of size!";
end if;
FIFO_rsp_mem(CONV_INTEGER(FIFO_rsp_ptr_w)) := mem(CONV_INTEGER(FIFO_req_address_temp));
if(CONV_INTEGER(FIFO_rsp_ptr_w) /= DEPTH - 1) then
FIFO_rsp_ptr_w <= esl_add(FIFO_rsp_ptr_w, "1");
else
FIFO_rsp_ptr_w <= (others => '0');
end if;
if(CONV_INTEGER(FIFO_req_size_temp) = 1) then -- The last one is done
FIFO_req_temp_state <= IDLE_STATE;
end if;
when WRITE_BURST_STATE =>
if(FIFO_req_empty = '0') then
FIFO_req_read <= '1'; -- Keep reading the next data(The data is storaged in FIFO_req but it is not a request)
if(CONV_INTEGER(FIFO_req_ptr_r) /= FIFO_DEPTH - 1) then
FIFO_req_ptr_r <= esl_add(FIFO_req_ptr_r, "1");
else
FIFO_req_ptr_r <= (others => '0');
end if;
FIFO_req_size_temp := esl_sub(FIFO_req_size_temp, "1");
if(CONV_INTEGER(FIFO_req_address_temp) /= DEPTH - 1) then
FIFO_req_address_temp := esl_add(FIFO_req_address_temp, "1");
else
report "Burst write out of size!";
end if;
mem(CONV_INTEGER(FIFO_req_address_temp)) := FIFO_req_din(CONV_INTEGER(FIFO_req_ptr_r));
if(CONV_INTEGER(FIFO_req_size_temp) = 1) then -- The last one is done
FIFO_req_temp_state <= IDLE_STATE;
end if;
end if;
when OTHERS =>
FIFO_req_temp_state <= IDLE_STATE;
end case;
end if;
end process;
-- Generate "FIFO_req_flag"
FIFO_req_flag_proc : process
begin
wait until clk'event and clk = '1';
if(rst = '1') then
FIFO_req_flag <= '0';
else
if((bus_req_RW_en = '1' and FIFO_req_full /= '1') and CONV_INTEGER(FIFO_req_ptr_w) = FIFO_DEPTH - 1) then
FIFO_req_flag <= '1';
end if;
wait for 0.4 ns;
if((FIFO_req_read = '1' and FIFO_req_empty /= '1') and CONV_INTEGER(FIFO_req_ptr_r) = 0) then
FIFO_req_flag <= '0';
end if;
end if;
end process;
-- Generate "FIFO_rsp_flag"
FIFO_rsp_flag_proc : process
begin
wait until clk'event and clk = '1';
if(rst = '1') then
FIFO_rsp_flag <= '0';
else
if((bus_rsp_read = '1' and FIFO_rsp_empty /= '1') and CONV_INTEGER(FIFO_rsp_ptr_r) = DEPTH - 1) then
FIFO_rsp_flag <= '0';
end if;
wait for 0.4 ns;
if((FIFO_rsp_write = '1' and FIFO_rsp_full /= '1') and CONV_INTEGER(FIFO_rsp_ptr_w) = 0) then
FIFO_rsp_flag <= '1';
end if;
end if;
end process;
-- Pop data from FIFO_rsp
FIFO_rsp_ptr_r_proc : process(clk, rst)
begin
if(rst = '1') then
FIFO_rsp_ptr_r <= (others => '0');
elsif (clk'event and clk = '1') then
if(bus_rsp_read = '1' and FIFO_rsp_empty /= '1') then
if(CONV_INTEGER(FIFO_rsp_ptr_r) /= DEPTH - 1) then
FIFO_rsp_ptr_r <= esl_add(FIFO_rsp_ptr_r, "1");
else
FIFO_rsp_ptr_r <= (others => '0');
end if;
end if;
end if;
end process;
----------------------------Read file-------------------
-- Read data from file
read_file_proc : process
file fp : TEXT;
variable fstatus : FILE_OPEN_STATUS;
variable token_line : LINE;
variable token : STRING(1 to 128 );
variable token_len : INTEGER;
variable token_int : INTEGER;
variable idx : INTEGER;
--variable mem_var : arr2D;
begin
file_open(fstatus, fp, TV_IN, READ_MODE);
if(fstatus /= OPEN_OK) then
assert false report "Open file " & TV_IN & " failed!!!" severity failure;
end if;
esl_read_token(fp, token_line, token);
if(token(1 to 13) /= "[[[runtime]]]") then
report "The token is " & token;
assert false report "Illegal format of [[[runtime]]] part in " & TV_IN severity failure;
end if;
esl_read_token(fp, token_line, token);
while(token(1 to 14) /= "[[[/runtime]]]") loop
if(token(1 to 15) /= "[[transaction]]") then
report "The token is " & token;
assert false report "Illegal format of [[transaction]] part in " & TV_IN severity failure;
end if;
esl_read_token(fp, token_line, token); -- Skip transaction number
-- Start to read data for every transaction round
wait until clk'event and clk = '1';
wait for 0.2 ns;
while(ready /= '1') loop
wait until clk'event and clk = '1';
wait for 0.2 ns;
end loop;
for i in 0 to DEPTH - 1 loop
esl_read_token(fp, token_line, token);
mem(i) := esl_str2lv_hex(token, DATA_WIDTH);
end loop;
esl_read_token(fp, token_line, token);
if(token(1 to 16) /= "[[/transaction]]") then
report "The token is " & token;
assert false report "Illegal format of [[/transaction]] part in " & TV_IN severity failure;
end if;
esl_read_token(fp, token_line, token);
end loop;
file_close(fp);
wait;
end process;
----------------------------Write file-------------------
-- Write data to file
write_file_proc : process
file fp : TEXT;
variable fstatus : FILE_OPEN_STATUS;
variable token_line : LINE;
variable token : STRING(1 to 128 );
variable transaction_idx : INTEGER;
begin
wait until (rst = '0');
transaction_idx := 0;
while(true) loop
wait until clk'event and clk = '1';
while(done /= '1') loop
wait until clk'event and clk = '1';
end loop;
wait for 0.1 ns;
file_open(fstatus, fp, TV_OUT, APPEND_MODE);
if(fstatus /= OPEN_OK) then
assert false report "Open file " & TV_OUT & " failed!!!" severity failure;
end if;
write(token_line, "[[transaction]] " & integer'image(transaction_idx));
writeline(fp, token_line);
for i in 0 to DEPTH - 1 loop
write(token_line, "0x" & esl_conv_string_hex(mem(i)));
writeline(fp, token_line);
end loop;
write(token_line, string'("[[/transaction]]"));
writeline(fp, token_line);
transaction_idx := transaction_idx + 1;
file_close(fp);
end loop;
wait;
end process;
end behav;
| lgpl-3.0 | 806f53c5da911f595d8b666372fd76d2 | 0.431825 | 3.795285 | false | false | false | false |
jairov4/accel-oil | solution_spartan6/syn/vhdl/nfa_accept_samples_generic_hw_add_6ns_6ns_6_2.vhd | 3 | 7,081 | -- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2013.4
-- Copyright (C) 2013 Xilinx Inc. All rights reserved.
--
-- ==============================================================
library IEEE;
use IEEE.std_logic_1164.all;
use ieee.std_logic_arith.all;
entity nfa_accept_samples_generic_hw_add_6ns_6ns_6_2_AddSubnS_3 is
port (
clk: in std_logic;
reset: in std_logic;
ce: in std_logic;
a: in std_logic_vector(5 downto 0);
b: in std_logic_vector(5 downto 0);
s: out std_logic_vector(5 downto 0));
end entity;
architecture behav of nfa_accept_samples_generic_hw_add_6ns_6ns_6_2_AddSubnS_3 is
component nfa_accept_samples_generic_hw_add_6ns_6ns_6_2_AddSubnS_3_fadder is
port (
faa : IN STD_LOGIC_VECTOR (3-1 downto 0);
fab : IN STD_LOGIC_VECTOR (3-1 downto 0);
facin : IN STD_LOGIC_VECTOR (0 downto 0);
fas : OUT STD_LOGIC_VECTOR (3-1 downto 0);
facout : OUT STD_LOGIC_VECTOR (0 downto 0));
end component;
component nfa_accept_samples_generic_hw_add_6ns_6ns_6_2_AddSubnS_3_fadder_f is
port (
faa : IN STD_LOGIC_VECTOR (3-1 downto 0);
fab : IN STD_LOGIC_VECTOR (3-1 downto 0);
facin : IN STD_LOGIC_VECTOR (0 downto 0);
fas : OUT STD_LOGIC_VECTOR (3-1 downto 0);
facout : OUT STD_LOGIC_VECTOR (0 downto 0));
end component;
-- ---- register and wire type variables list here ----
-- wire for the primary inputs
signal a_reg : std_logic_vector(5 downto 0);
signal b_reg : std_logic_vector(5 downto 0);
-- wires for each small adder
signal a0_cb : std_logic_vector(2 downto 0);
signal b0_cb : std_logic_vector(2 downto 0);
signal a1_cb : std_logic_vector(5 downto 3);
signal b1_cb : std_logic_vector(5 downto 3);
-- registers for input register array
type ramtypei0 is array (0 downto 0) of std_logic_vector(2 downto 0);
signal a1_cb_regi1 : ramtypei0;
signal b1_cb_regi1 : ramtypei0;
-- wires for each full adder sum
signal fas : std_logic_vector(5 downto 0);
-- wires and register for carry out bit
signal faccout_ini : std_logic_vector (0 downto 0);
signal faccout0_co0 : std_logic_vector (0 downto 0);
signal faccout1_co1 : std_logic_vector (0 downto 0);
signal faccout0_co0_reg : std_logic_vector (0 downto 0);
-- registers for output register array
type ramtypeo0 is array (0 downto 0) of std_logic_vector(2 downto 0);
signal s0_ca_rego0 : ramtypeo0;
-- wire for the temporary output
signal s_tmp : std_logic_vector(5 downto 0);
-- ---- RTL code for assignment statements/always blocks/module instantiations here ----
begin
a_reg <= a;
b_reg <= b;
-- small adder input assigments
a0_cb <= a_reg(2 downto 0);
b0_cb <= b_reg(2 downto 0);
a1_cb <= a_reg(5 downto 3);
b1_cb <= b_reg(5 downto 3);
-- input register array
process (clk)
begin
if (clk'event and clk='1') then
if (ce='1') then
a1_cb_regi1 (0) <= a1_cb;
b1_cb_regi1 (0) <= b1_cb;
end if;
end if;
end process;
-- carry out bit processing
process (clk)
begin
if (clk'event and clk='1') then
if (ce='1') then
faccout0_co0_reg <= faccout0_co0;
end if;
end if;
end process;
-- small adder generation
u0 : nfa_accept_samples_generic_hw_add_6ns_6ns_6_2_AddSubnS_3_fadder
port map
(faa => a0_cb,
fab => b0_cb,
facin => faccout_ini,
fas => fas(2 downto 0),
facout => faccout0_co0);
u1 : nfa_accept_samples_generic_hw_add_6ns_6ns_6_2_AddSubnS_3_fadder_f
port map
(faa => a1_cb_regi1(0),
fab => b1_cb_regi1(0),
facin => faccout0_co0_reg,
fas => fas(5 downto 3),
facout => faccout1_co1);
faccout_ini <= "0";
-- output register array
process (clk)
begin
if (clk'event and clk='1') then
if (ce='1') then
s0_ca_rego0 (0) <= fas(2 downto 0);
end if;
end if;
end process;
-- get the s_tmp, assign it to the primary output
s_tmp(2 downto 0) <= s0_ca_rego0(0);
s_tmp(5 downto 3) <= fas(5 downto 3);
s <= s_tmp;
end architecture;
-- short adder
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity nfa_accept_samples_generic_hw_add_6ns_6ns_6_2_AddSubnS_3_fadder is
generic(N : natural :=3);
port (
faa : IN STD_LOGIC_VECTOR (N-1 downto 0);
fab : IN STD_LOGIC_VECTOR (N-1 downto 0);
facin : IN STD_LOGIC_VECTOR (0 downto 0);
fas : OUT STD_LOGIC_VECTOR (N-1 downto 0);
facout : OUT STD_LOGIC_VECTOR (0 downto 0));
end;
architecture behav of nfa_accept_samples_generic_hw_add_6ns_6ns_6_2_AddSubnS_3_fadder is
signal tmp : STD_LOGIC_VECTOR (N downto 0);
begin
tmp <= std_logic_vector(unsigned(std_logic_vector(unsigned(std_logic_vector(resize(unsigned(faa),N+1))) + unsigned(fab))) + unsigned(facin));
fas <= tmp(N-1 downto 0 );
facout <= tmp(N downto N);
end behav;
-- the final stage short adder
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity nfa_accept_samples_generic_hw_add_6ns_6ns_6_2_AddSubnS_3_fadder_f is
generic(N : natural :=3);
port (
faa : IN STD_LOGIC_VECTOR (N-1 downto 0);
fab : IN STD_LOGIC_VECTOR (N-1 downto 0);
facin : IN STD_LOGIC_VECTOR (0 downto 0);
fas : OUT STD_LOGIC_VECTOR (N-1 downto 0);
facout : OUT STD_LOGIC_VECTOR (0 downto 0));
end;
architecture behav of nfa_accept_samples_generic_hw_add_6ns_6ns_6_2_AddSubnS_3_fadder_f is
signal tmp : STD_LOGIC_VECTOR (N downto 0);
begin
tmp <= std_logic_vector(unsigned(std_logic_vector(unsigned(std_logic_vector(resize(unsigned(faa),N+1))) + unsigned(fab))) + unsigned(facin));
fas <= tmp(N-1 downto 0 );
facout <= tmp(N downto N);
end behav;
Library IEEE;
use IEEE.std_logic_1164.all;
entity nfa_accept_samples_generic_hw_add_6ns_6ns_6_2 is
generic (
ID : INTEGER;
NUM_STAGE : INTEGER;
din0_WIDTH : INTEGER;
din1_WIDTH : INTEGER;
dout_WIDTH : INTEGER);
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
ce : IN STD_LOGIC;
din0 : IN STD_LOGIC_VECTOR(din0_WIDTH - 1 DOWNTO 0);
din1 : IN STD_LOGIC_VECTOR(din1_WIDTH - 1 DOWNTO 0);
dout : OUT STD_LOGIC_VECTOR(dout_WIDTH - 1 DOWNTO 0));
end entity;
architecture arch of nfa_accept_samples_generic_hw_add_6ns_6ns_6_2 is
component nfa_accept_samples_generic_hw_add_6ns_6ns_6_2_AddSubnS_3 is
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
ce : IN STD_LOGIC;
a : IN STD_LOGIC_VECTOR;
b : IN STD_LOGIC_VECTOR;
s : OUT STD_LOGIC_VECTOR);
end component;
begin
nfa_accept_samples_generic_hw_add_6ns_6ns_6_2_AddSubnS_3_U : component nfa_accept_samples_generic_hw_add_6ns_6ns_6_2_AddSubnS_3
port map (
clk => clk,
reset => reset,
ce => ce,
a => din0,
b => din1,
s => dout);
end architecture;
| lgpl-3.0 | 19d503c8e435fe918f7b05aa1666291f | 0.615873 | 3.001696 | false | false | false | false |
grwlf/vsim | vhdl/letprocess1.vhd | 1 | 418 | entity test is
end entity test;
architecture test_arch of test is
-- constant size : integer := 10;
signal clk : integer := 0;
signal s1 : integer := 0;
begin
main: process
constant xzz : integer := 10;
variable aone : integer := 1;
begin
report "simple letprocess";
s1 <= clk + aone;
assert false report "end of simulation" severity failure;
end process;
end architecture test_arch;
| gpl-3.0 | b098d12188c88cb3478dbeb375a685ee | 0.667464 | 3.542373 | false | true | false | false |
jairov4/accel-oil | impl/impl_test_single/hdl/system.vhd | 1 | 142,011 | -------------------------------------------------------------------------------
-- system.vhd
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system is
port (
fpga_0_clk_1_sys_clk_pin : in std_logic;
fpga_0_rst_1_sys_rst_pin : in std_logic
);
end system;
architecture STRUCTURE of system is
component system_microblaze_0_wrapper is
port (
CLK : in std_logic;
RESET : in std_logic;
MB_RESET : in std_logic;
INTERRUPT : in std_logic;
INTERRUPT_ADDRESS : in std_logic_vector(0 to 31);
INTERRUPT_ACK : out std_logic_vector(0 to 1);
EXT_BRK : in std_logic;
EXT_NM_BRK : in std_logic;
DBG_STOP : in std_logic;
MB_Halted : out std_logic;
MB_Error : out std_logic;
WAKEUP : in std_logic_vector(0 to 1);
SLEEP : out std_logic;
DBG_WAKEUP : out std_logic;
LOCKSTEP_MASTER_OUT : out std_logic_vector(0 to 4095);
LOCKSTEP_SLAVE_IN : in std_logic_vector(0 to 4095);
LOCKSTEP_OUT : out std_logic_vector(0 to 4095);
INSTR : in std_logic_vector(0 to 31);
IREADY : in std_logic;
IWAIT : in std_logic;
ICE : in std_logic;
IUE : in std_logic;
INSTR_ADDR : out std_logic_vector(0 to 31);
IFETCH : out std_logic;
I_AS : out std_logic;
IPLB_M_ABort : out std_logic;
IPLB_M_ABus : out std_logic_vector(0 to 31);
IPLB_M_UABus : out std_logic_vector(0 to 31);
IPLB_M_BE : out std_logic_vector(0 to 7);
IPLB_M_busLock : out std_logic;
IPLB_M_lockErr : out std_logic;
IPLB_M_MSize : out std_logic_vector(0 to 1);
IPLB_M_priority : out std_logic_vector(0 to 1);
IPLB_M_rdBurst : out std_logic;
IPLB_M_request : out std_logic;
IPLB_M_RNW : out std_logic;
IPLB_M_size : out std_logic_vector(0 to 3);
IPLB_M_TAttribute : out std_logic_vector(0 to 15);
IPLB_M_type : out std_logic_vector(0 to 2);
IPLB_M_wrBurst : out std_logic;
IPLB_M_wrDBus : out std_logic_vector(0 to 63);
IPLB_MBusy : in std_logic;
IPLB_MRdErr : in std_logic;
IPLB_MWrErr : in std_logic;
IPLB_MIRQ : in std_logic;
IPLB_MWrBTerm : in std_logic;
IPLB_MWrDAck : in std_logic;
IPLB_MAddrAck : in std_logic;
IPLB_MRdBTerm : in std_logic;
IPLB_MRdDAck : in std_logic;
IPLB_MRdDBus : in std_logic_vector(0 to 63);
IPLB_MRdWdAddr : in std_logic_vector(0 to 3);
IPLB_MRearbitrate : in std_logic;
IPLB_MSSize : in std_logic_vector(0 to 1);
IPLB_MTimeout : in std_logic;
DATA_READ : in std_logic_vector(0 to 31);
DREADY : in std_logic;
DWAIT : in std_logic;
DCE : in std_logic;
DUE : in std_logic;
DATA_WRITE : out std_logic_vector(0 to 31);
DATA_ADDR : out std_logic_vector(0 to 31);
D_AS : out std_logic;
READ_STROBE : out std_logic;
WRITE_STROBE : out std_logic;
BYTE_ENABLE : out std_logic_vector(0 to 3);
DPLB_M_ABort : out std_logic;
DPLB_M_ABus : out std_logic_vector(0 to 31);
DPLB_M_UABus : out std_logic_vector(0 to 31);
DPLB_M_BE : out std_logic_vector(0 to 7);
DPLB_M_busLock : out std_logic;
DPLB_M_lockErr : out std_logic;
DPLB_M_MSize : out std_logic_vector(0 to 1);
DPLB_M_priority : out std_logic_vector(0 to 1);
DPLB_M_rdBurst : out std_logic;
DPLB_M_request : out std_logic;
DPLB_M_RNW : out std_logic;
DPLB_M_size : out std_logic_vector(0 to 3);
DPLB_M_TAttribute : out std_logic_vector(0 to 15);
DPLB_M_type : out std_logic_vector(0 to 2);
DPLB_M_wrBurst : out std_logic;
DPLB_M_wrDBus : out std_logic_vector(0 to 63);
DPLB_MBusy : in std_logic;
DPLB_MRdErr : in std_logic;
DPLB_MWrErr : in std_logic;
DPLB_MIRQ : in std_logic;
DPLB_MWrBTerm : in std_logic;
DPLB_MWrDAck : in std_logic;
DPLB_MAddrAck : in std_logic;
DPLB_MRdBTerm : in std_logic;
DPLB_MRdDAck : in std_logic;
DPLB_MRdDBus : in std_logic_vector(0 to 63);
DPLB_MRdWdAddr : in std_logic_vector(0 to 3);
DPLB_MRearbitrate : in std_logic;
DPLB_MSSize : in std_logic_vector(0 to 1);
DPLB_MTimeout : in std_logic;
M_AXI_IP_AWID : out std_logic_vector(0 downto 0);
M_AXI_IP_AWADDR : out std_logic_vector(31 downto 0);
M_AXI_IP_AWLEN : out std_logic_vector(7 downto 0);
M_AXI_IP_AWSIZE : out std_logic_vector(2 downto 0);
M_AXI_IP_AWBURST : out std_logic_vector(1 downto 0);
M_AXI_IP_AWLOCK : out std_logic;
M_AXI_IP_AWCACHE : out std_logic_vector(3 downto 0);
M_AXI_IP_AWPROT : out std_logic_vector(2 downto 0);
M_AXI_IP_AWQOS : out std_logic_vector(3 downto 0);
M_AXI_IP_AWVALID : out std_logic;
M_AXI_IP_AWREADY : in std_logic;
M_AXI_IP_WDATA : out std_logic_vector(31 downto 0);
M_AXI_IP_WSTRB : out std_logic_vector(3 downto 0);
M_AXI_IP_WLAST : out std_logic;
M_AXI_IP_WVALID : out std_logic;
M_AXI_IP_WREADY : in std_logic;
M_AXI_IP_BID : in std_logic_vector(0 downto 0);
M_AXI_IP_BRESP : in std_logic_vector(1 downto 0);
M_AXI_IP_BVALID : in std_logic;
M_AXI_IP_BREADY : out std_logic;
M_AXI_IP_ARID : out std_logic_vector(0 downto 0);
M_AXI_IP_ARADDR : out std_logic_vector(31 downto 0);
M_AXI_IP_ARLEN : out std_logic_vector(7 downto 0);
M_AXI_IP_ARSIZE : out std_logic_vector(2 downto 0);
M_AXI_IP_ARBURST : out std_logic_vector(1 downto 0);
M_AXI_IP_ARLOCK : out std_logic;
M_AXI_IP_ARCACHE : out std_logic_vector(3 downto 0);
M_AXI_IP_ARPROT : out std_logic_vector(2 downto 0);
M_AXI_IP_ARQOS : out std_logic_vector(3 downto 0);
M_AXI_IP_ARVALID : out std_logic;
M_AXI_IP_ARREADY : in std_logic;
M_AXI_IP_RID : in std_logic_vector(0 downto 0);
M_AXI_IP_RDATA : in std_logic_vector(31 downto 0);
M_AXI_IP_RRESP : in std_logic_vector(1 downto 0);
M_AXI_IP_RLAST : in std_logic;
M_AXI_IP_RVALID : in std_logic;
M_AXI_IP_RREADY : out std_logic;
M_AXI_DP_AWID : out std_logic_vector(0 downto 0);
M_AXI_DP_AWADDR : out std_logic_vector(31 downto 0);
M_AXI_DP_AWLEN : out std_logic_vector(7 downto 0);
M_AXI_DP_AWSIZE : out std_logic_vector(2 downto 0);
M_AXI_DP_AWBURST : out std_logic_vector(1 downto 0);
M_AXI_DP_AWLOCK : out std_logic;
M_AXI_DP_AWCACHE : out std_logic_vector(3 downto 0);
M_AXI_DP_AWPROT : out std_logic_vector(2 downto 0);
M_AXI_DP_AWQOS : out std_logic_vector(3 downto 0);
M_AXI_DP_AWVALID : out std_logic;
M_AXI_DP_AWREADY : in std_logic;
M_AXI_DP_WDATA : out std_logic_vector(31 downto 0);
M_AXI_DP_WSTRB : out std_logic_vector(3 downto 0);
M_AXI_DP_WLAST : out std_logic;
M_AXI_DP_WVALID : out std_logic;
M_AXI_DP_WREADY : in std_logic;
M_AXI_DP_BID : in std_logic_vector(0 downto 0);
M_AXI_DP_BRESP : in std_logic_vector(1 downto 0);
M_AXI_DP_BVALID : in std_logic;
M_AXI_DP_BREADY : out std_logic;
M_AXI_DP_ARID : out std_logic_vector(0 downto 0);
M_AXI_DP_ARADDR : out std_logic_vector(31 downto 0);
M_AXI_DP_ARLEN : out std_logic_vector(7 downto 0);
M_AXI_DP_ARSIZE : out std_logic_vector(2 downto 0);
M_AXI_DP_ARBURST : out std_logic_vector(1 downto 0);
M_AXI_DP_ARLOCK : out std_logic;
M_AXI_DP_ARCACHE : out std_logic_vector(3 downto 0);
M_AXI_DP_ARPROT : out std_logic_vector(2 downto 0);
M_AXI_DP_ARQOS : out std_logic_vector(3 downto 0);
M_AXI_DP_ARVALID : out std_logic;
M_AXI_DP_ARREADY : in std_logic;
M_AXI_DP_RID : in std_logic_vector(0 downto 0);
M_AXI_DP_RDATA : in std_logic_vector(31 downto 0);
M_AXI_DP_RRESP : in std_logic_vector(1 downto 0);
M_AXI_DP_RLAST : in std_logic;
M_AXI_DP_RVALID : in std_logic;
M_AXI_DP_RREADY : out std_logic;
M_AXI_IC_AWID : out std_logic_vector(0 downto 0);
M_AXI_IC_AWADDR : out std_logic_vector(31 downto 0);
M_AXI_IC_AWLEN : out std_logic_vector(7 downto 0);
M_AXI_IC_AWSIZE : out std_logic_vector(2 downto 0);
M_AXI_IC_AWBURST : out std_logic_vector(1 downto 0);
M_AXI_IC_AWLOCK : out std_logic;
M_AXI_IC_AWCACHE : out std_logic_vector(3 downto 0);
M_AXI_IC_AWPROT : out std_logic_vector(2 downto 0);
M_AXI_IC_AWQOS : out std_logic_vector(3 downto 0);
M_AXI_IC_AWVALID : out std_logic;
M_AXI_IC_AWREADY : in std_logic;
M_AXI_IC_AWUSER : out std_logic_vector(4 downto 0);
M_AXI_IC_AWDOMAIN : out std_logic_vector(1 downto 0);
M_AXI_IC_AWSNOOP : out std_logic_vector(2 downto 0);
M_AXI_IC_AWBAR : out std_logic_vector(1 downto 0);
M_AXI_IC_WDATA : out std_logic_vector(31 downto 0);
M_AXI_IC_WSTRB : out std_logic_vector(3 downto 0);
M_AXI_IC_WLAST : out std_logic;
M_AXI_IC_WVALID : out std_logic;
M_AXI_IC_WREADY : in std_logic;
M_AXI_IC_WUSER : out std_logic_vector(0 downto 0);
M_AXI_IC_BID : in std_logic_vector(0 downto 0);
M_AXI_IC_BRESP : in std_logic_vector(1 downto 0);
M_AXI_IC_BVALID : in std_logic;
M_AXI_IC_BREADY : out std_logic;
M_AXI_IC_BUSER : in std_logic_vector(0 downto 0);
M_AXI_IC_WACK : out std_logic;
M_AXI_IC_ARID : out std_logic_vector(0 downto 0);
M_AXI_IC_ARADDR : out std_logic_vector(31 downto 0);
M_AXI_IC_ARLEN : out std_logic_vector(7 downto 0);
M_AXI_IC_ARSIZE : out std_logic_vector(2 downto 0);
M_AXI_IC_ARBURST : out std_logic_vector(1 downto 0);
M_AXI_IC_ARLOCK : out std_logic;
M_AXI_IC_ARCACHE : out std_logic_vector(3 downto 0);
M_AXI_IC_ARPROT : out std_logic_vector(2 downto 0);
M_AXI_IC_ARQOS : out std_logic_vector(3 downto 0);
M_AXI_IC_ARVALID : out std_logic;
M_AXI_IC_ARREADY : in std_logic;
M_AXI_IC_ARUSER : out std_logic_vector(4 downto 0);
M_AXI_IC_ARDOMAIN : out std_logic_vector(1 downto 0);
M_AXI_IC_ARSNOOP : out std_logic_vector(3 downto 0);
M_AXI_IC_ARBAR : out std_logic_vector(1 downto 0);
M_AXI_IC_RID : in std_logic_vector(0 downto 0);
M_AXI_IC_RDATA : in std_logic_vector(31 downto 0);
M_AXI_IC_RRESP : in std_logic_vector(1 downto 0);
M_AXI_IC_RLAST : in std_logic;
M_AXI_IC_RVALID : in std_logic;
M_AXI_IC_RREADY : out std_logic;
M_AXI_IC_RUSER : in std_logic_vector(0 downto 0);
M_AXI_IC_RACK : out std_logic;
M_AXI_IC_ACVALID : in std_logic;
M_AXI_IC_ACADDR : in std_logic_vector(31 downto 0);
M_AXI_IC_ACSNOOP : in std_logic_vector(3 downto 0);
M_AXI_IC_ACPROT : in std_logic_vector(2 downto 0);
M_AXI_IC_ACREADY : out std_logic;
M_AXI_IC_CRREADY : in std_logic;
M_AXI_IC_CRVALID : out std_logic;
M_AXI_IC_CRRESP : out std_logic_vector(4 downto 0);
M_AXI_IC_CDVALID : out std_logic;
M_AXI_IC_CDREADY : in std_logic;
M_AXI_IC_CDDATA : out std_logic_vector(31 downto 0);
M_AXI_IC_CDLAST : out std_logic;
M_AXI_DC_AWID : out std_logic_vector(0 downto 0);
M_AXI_DC_AWADDR : out std_logic_vector(31 downto 0);
M_AXI_DC_AWLEN : out std_logic_vector(7 downto 0);
M_AXI_DC_AWSIZE : out std_logic_vector(2 downto 0);
M_AXI_DC_AWBURST : out std_logic_vector(1 downto 0);
M_AXI_DC_AWLOCK : out std_logic;
M_AXI_DC_AWCACHE : out std_logic_vector(3 downto 0);
M_AXI_DC_AWPROT : out std_logic_vector(2 downto 0);
M_AXI_DC_AWQOS : out std_logic_vector(3 downto 0);
M_AXI_DC_AWVALID : out std_logic;
M_AXI_DC_AWREADY : in std_logic;
M_AXI_DC_AWUSER : out std_logic_vector(4 downto 0);
M_AXI_DC_AWDOMAIN : out std_logic_vector(1 downto 0);
M_AXI_DC_AWSNOOP : out std_logic_vector(2 downto 0);
M_AXI_DC_AWBAR : out std_logic_vector(1 downto 0);
M_AXI_DC_WDATA : out std_logic_vector(31 downto 0);
M_AXI_DC_WSTRB : out std_logic_vector(3 downto 0);
M_AXI_DC_WLAST : out std_logic;
M_AXI_DC_WVALID : out std_logic;
M_AXI_DC_WREADY : in std_logic;
M_AXI_DC_WUSER : out std_logic_vector(0 downto 0);
M_AXI_DC_BID : in std_logic_vector(0 downto 0);
M_AXI_DC_BRESP : in std_logic_vector(1 downto 0);
M_AXI_DC_BVALID : in std_logic;
M_AXI_DC_BREADY : out std_logic;
M_AXI_DC_BUSER : in std_logic_vector(0 downto 0);
M_AXI_DC_WACK : out std_logic;
M_AXI_DC_ARID : out std_logic_vector(0 downto 0);
M_AXI_DC_ARADDR : out std_logic_vector(31 downto 0);
M_AXI_DC_ARLEN : out std_logic_vector(7 downto 0);
M_AXI_DC_ARSIZE : out std_logic_vector(2 downto 0);
M_AXI_DC_ARBURST : out std_logic_vector(1 downto 0);
M_AXI_DC_ARLOCK : out std_logic;
M_AXI_DC_ARCACHE : out std_logic_vector(3 downto 0);
M_AXI_DC_ARPROT : out std_logic_vector(2 downto 0);
M_AXI_DC_ARQOS : out std_logic_vector(3 downto 0);
M_AXI_DC_ARVALID : out std_logic;
M_AXI_DC_ARREADY : in std_logic;
M_AXI_DC_ARUSER : out std_logic_vector(4 downto 0);
M_AXI_DC_ARDOMAIN : out std_logic_vector(1 downto 0);
M_AXI_DC_ARSNOOP : out std_logic_vector(3 downto 0);
M_AXI_DC_ARBAR : out std_logic_vector(1 downto 0);
M_AXI_DC_RID : in std_logic_vector(0 downto 0);
M_AXI_DC_RDATA : in std_logic_vector(31 downto 0);
M_AXI_DC_RRESP : in std_logic_vector(1 downto 0);
M_AXI_DC_RLAST : in std_logic;
M_AXI_DC_RVALID : in std_logic;
M_AXI_DC_RREADY : out std_logic;
M_AXI_DC_RUSER : in std_logic_vector(0 downto 0);
M_AXI_DC_RACK : out std_logic;
M_AXI_DC_ACVALID : in std_logic;
M_AXI_DC_ACADDR : in std_logic_vector(31 downto 0);
M_AXI_DC_ACSNOOP : in std_logic_vector(3 downto 0);
M_AXI_DC_ACPROT : in std_logic_vector(2 downto 0);
M_AXI_DC_ACREADY : out std_logic;
M_AXI_DC_CRREADY : in std_logic;
M_AXI_DC_CRVALID : out std_logic;
M_AXI_DC_CRRESP : out std_logic_vector(4 downto 0);
M_AXI_DC_CDVALID : out std_logic;
M_AXI_DC_CDREADY : in std_logic;
M_AXI_DC_CDDATA : out std_logic_vector(31 downto 0);
M_AXI_DC_CDLAST : out std_logic;
DBG_CLK : in std_logic;
DBG_TDI : in std_logic;
DBG_TDO : out std_logic;
DBG_REG_EN : in std_logic_vector(0 to 7);
DBG_SHIFT : in std_logic;
DBG_CAPTURE : in std_logic;
DBG_UPDATE : in std_logic;
DEBUG_RST : in std_logic;
Trace_Instruction : out std_logic_vector(0 to 31);
Trace_Valid_Instr : out std_logic;
Trace_PC : out std_logic_vector(0 to 31);
Trace_Reg_Write : out std_logic;
Trace_Reg_Addr : out std_logic_vector(0 to 4);
Trace_MSR_Reg : out std_logic_vector(0 to 14);
Trace_PID_Reg : out std_logic_vector(0 to 7);
Trace_New_Reg_Value : out std_logic_vector(0 to 31);
Trace_Exception_Taken : out std_logic;
Trace_Exception_Kind : out std_logic_vector(0 to 4);
Trace_Jump_Taken : out std_logic;
Trace_Delay_Slot : out std_logic;
Trace_Data_Address : out std_logic_vector(0 to 31);
Trace_Data_Access : out std_logic;
Trace_Data_Read : out std_logic;
Trace_Data_Write : out std_logic;
Trace_Data_Write_Value : out std_logic_vector(0 to 31);
Trace_Data_Byte_Enable : out std_logic_vector(0 to 3);
Trace_DCache_Req : out std_logic;
Trace_DCache_Hit : out std_logic;
Trace_DCache_Rdy : out std_logic;
Trace_DCache_Read : out std_logic;
Trace_ICache_Req : out std_logic;
Trace_ICache_Hit : out std_logic;
Trace_ICache_Rdy : out std_logic;
Trace_OF_PipeRun : out std_logic;
Trace_EX_PipeRun : out std_logic;
Trace_MEM_PipeRun : out std_logic;
Trace_MB_Halted : out std_logic;
Trace_Jump_Hit : out std_logic;
FSL0_S_CLK : out std_logic;
FSL0_S_READ : out std_logic;
FSL0_S_DATA : in std_logic_vector(0 to 31);
FSL0_S_CONTROL : in std_logic;
FSL0_S_EXISTS : in std_logic;
FSL0_M_CLK : out std_logic;
FSL0_M_WRITE : out std_logic;
FSL0_M_DATA : out std_logic_vector(0 to 31);
FSL0_M_CONTROL : out std_logic;
FSL0_M_FULL : in std_logic;
FSL1_S_CLK : out std_logic;
FSL1_S_READ : out std_logic;
FSL1_S_DATA : in std_logic_vector(0 to 31);
FSL1_S_CONTROL : in std_logic;
FSL1_S_EXISTS : in std_logic;
FSL1_M_CLK : out std_logic;
FSL1_M_WRITE : out std_logic;
FSL1_M_DATA : out std_logic_vector(0 to 31);
FSL1_M_CONTROL : out std_logic;
FSL1_M_FULL : in std_logic;
FSL2_S_CLK : out std_logic;
FSL2_S_READ : out std_logic;
FSL2_S_DATA : in std_logic_vector(0 to 31);
FSL2_S_CONTROL : in std_logic;
FSL2_S_EXISTS : in std_logic;
FSL2_M_CLK : out std_logic;
FSL2_M_WRITE : out std_logic;
FSL2_M_DATA : out std_logic_vector(0 to 31);
FSL2_M_CONTROL : out std_logic;
FSL2_M_FULL : in std_logic;
FSL3_S_CLK : out std_logic;
FSL3_S_READ : out std_logic;
FSL3_S_DATA : in std_logic_vector(0 to 31);
FSL3_S_CONTROL : in std_logic;
FSL3_S_EXISTS : in std_logic;
FSL3_M_CLK : out std_logic;
FSL3_M_WRITE : out std_logic;
FSL3_M_DATA : out std_logic_vector(0 to 31);
FSL3_M_CONTROL : out std_logic;
FSL3_M_FULL : in std_logic;
FSL4_S_CLK : out std_logic;
FSL4_S_READ : out std_logic;
FSL4_S_DATA : in std_logic_vector(0 to 31);
FSL4_S_CONTROL : in std_logic;
FSL4_S_EXISTS : in std_logic;
FSL4_M_CLK : out std_logic;
FSL4_M_WRITE : out std_logic;
FSL4_M_DATA : out std_logic_vector(0 to 31);
FSL4_M_CONTROL : out std_logic;
FSL4_M_FULL : in std_logic;
FSL5_S_CLK : out std_logic;
FSL5_S_READ : out std_logic;
FSL5_S_DATA : in std_logic_vector(0 to 31);
FSL5_S_CONTROL : in std_logic;
FSL5_S_EXISTS : in std_logic;
FSL5_M_CLK : out std_logic;
FSL5_M_WRITE : out std_logic;
FSL5_M_DATA : out std_logic_vector(0 to 31);
FSL5_M_CONTROL : out std_logic;
FSL5_M_FULL : in std_logic;
FSL6_S_CLK : out std_logic;
FSL6_S_READ : out std_logic;
FSL6_S_DATA : in std_logic_vector(0 to 31);
FSL6_S_CONTROL : in std_logic;
FSL6_S_EXISTS : in std_logic;
FSL6_M_CLK : out std_logic;
FSL6_M_WRITE : out std_logic;
FSL6_M_DATA : out std_logic_vector(0 to 31);
FSL6_M_CONTROL : out std_logic;
FSL6_M_FULL : in std_logic;
FSL7_S_CLK : out std_logic;
FSL7_S_READ : out std_logic;
FSL7_S_DATA : in std_logic_vector(0 to 31);
FSL7_S_CONTROL : in std_logic;
FSL7_S_EXISTS : in std_logic;
FSL7_M_CLK : out std_logic;
FSL7_M_WRITE : out std_logic;
FSL7_M_DATA : out std_logic_vector(0 to 31);
FSL7_M_CONTROL : out std_logic;
FSL7_M_FULL : in std_logic;
FSL8_S_CLK : out std_logic;
FSL8_S_READ : out std_logic;
FSL8_S_DATA : in std_logic_vector(0 to 31);
FSL8_S_CONTROL : in std_logic;
FSL8_S_EXISTS : in std_logic;
FSL8_M_CLK : out std_logic;
FSL8_M_WRITE : out std_logic;
FSL8_M_DATA : out std_logic_vector(0 to 31);
FSL8_M_CONTROL : out std_logic;
FSL8_M_FULL : in std_logic;
FSL9_S_CLK : out std_logic;
FSL9_S_READ : out std_logic;
FSL9_S_DATA : in std_logic_vector(0 to 31);
FSL9_S_CONTROL : in std_logic;
FSL9_S_EXISTS : in std_logic;
FSL9_M_CLK : out std_logic;
FSL9_M_WRITE : out std_logic;
FSL9_M_DATA : out std_logic_vector(0 to 31);
FSL9_M_CONTROL : out std_logic;
FSL9_M_FULL : in std_logic;
FSL10_S_CLK : out std_logic;
FSL10_S_READ : out std_logic;
FSL10_S_DATA : in std_logic_vector(0 to 31);
FSL10_S_CONTROL : in std_logic;
FSL10_S_EXISTS : in std_logic;
FSL10_M_CLK : out std_logic;
FSL10_M_WRITE : out std_logic;
FSL10_M_DATA : out std_logic_vector(0 to 31);
FSL10_M_CONTROL : out std_logic;
FSL10_M_FULL : in std_logic;
FSL11_S_CLK : out std_logic;
FSL11_S_READ : out std_logic;
FSL11_S_DATA : in std_logic_vector(0 to 31);
FSL11_S_CONTROL : in std_logic;
FSL11_S_EXISTS : in std_logic;
FSL11_M_CLK : out std_logic;
FSL11_M_WRITE : out std_logic;
FSL11_M_DATA : out std_logic_vector(0 to 31);
FSL11_M_CONTROL : out std_logic;
FSL11_M_FULL : in std_logic;
FSL12_S_CLK : out std_logic;
FSL12_S_READ : out std_logic;
FSL12_S_DATA : in std_logic_vector(0 to 31);
FSL12_S_CONTROL : in std_logic;
FSL12_S_EXISTS : in std_logic;
FSL12_M_CLK : out std_logic;
FSL12_M_WRITE : out std_logic;
FSL12_M_DATA : out std_logic_vector(0 to 31);
FSL12_M_CONTROL : out std_logic;
FSL12_M_FULL : in std_logic;
FSL13_S_CLK : out std_logic;
FSL13_S_READ : out std_logic;
FSL13_S_DATA : in std_logic_vector(0 to 31);
FSL13_S_CONTROL : in std_logic;
FSL13_S_EXISTS : in std_logic;
FSL13_M_CLK : out std_logic;
FSL13_M_WRITE : out std_logic;
FSL13_M_DATA : out std_logic_vector(0 to 31);
FSL13_M_CONTROL : out std_logic;
FSL13_M_FULL : in std_logic;
FSL14_S_CLK : out std_logic;
FSL14_S_READ : out std_logic;
FSL14_S_DATA : in std_logic_vector(0 to 31);
FSL14_S_CONTROL : in std_logic;
FSL14_S_EXISTS : in std_logic;
FSL14_M_CLK : out std_logic;
FSL14_M_WRITE : out std_logic;
FSL14_M_DATA : out std_logic_vector(0 to 31);
FSL14_M_CONTROL : out std_logic;
FSL14_M_FULL : in std_logic;
FSL15_S_CLK : out std_logic;
FSL15_S_READ : out std_logic;
FSL15_S_DATA : in std_logic_vector(0 to 31);
FSL15_S_CONTROL : in std_logic;
FSL15_S_EXISTS : in std_logic;
FSL15_M_CLK : out std_logic;
FSL15_M_WRITE : out std_logic;
FSL15_M_DATA : out std_logic_vector(0 to 31);
FSL15_M_CONTROL : out std_logic;
FSL15_M_FULL : in std_logic;
M0_AXIS_TLAST : out std_logic;
M0_AXIS_TDATA : out std_logic_vector(31 downto 0);
M0_AXIS_TVALID : out std_logic;
M0_AXIS_TREADY : in std_logic;
S0_AXIS_TLAST : in std_logic;
S0_AXIS_TDATA : in std_logic_vector(31 downto 0);
S0_AXIS_TVALID : in std_logic;
S0_AXIS_TREADY : out std_logic;
M1_AXIS_TLAST : out std_logic;
M1_AXIS_TDATA : out std_logic_vector(31 downto 0);
M1_AXIS_TVALID : out std_logic;
M1_AXIS_TREADY : in std_logic;
S1_AXIS_TLAST : in std_logic;
S1_AXIS_TDATA : in std_logic_vector(31 downto 0);
S1_AXIS_TVALID : in std_logic;
S1_AXIS_TREADY : out std_logic;
M2_AXIS_TLAST : out std_logic;
M2_AXIS_TDATA : out std_logic_vector(31 downto 0);
M2_AXIS_TVALID : out std_logic;
M2_AXIS_TREADY : in std_logic;
S2_AXIS_TLAST : in std_logic;
S2_AXIS_TDATA : in std_logic_vector(31 downto 0);
S2_AXIS_TVALID : in std_logic;
S2_AXIS_TREADY : out std_logic;
M3_AXIS_TLAST : out std_logic;
M3_AXIS_TDATA : out std_logic_vector(31 downto 0);
M3_AXIS_TVALID : out std_logic;
M3_AXIS_TREADY : in std_logic;
S3_AXIS_TLAST : in std_logic;
S3_AXIS_TDATA : in std_logic_vector(31 downto 0);
S3_AXIS_TVALID : in std_logic;
S3_AXIS_TREADY : out std_logic;
M4_AXIS_TLAST : out std_logic;
M4_AXIS_TDATA : out std_logic_vector(31 downto 0);
M4_AXIS_TVALID : out std_logic;
M4_AXIS_TREADY : in std_logic;
S4_AXIS_TLAST : in std_logic;
S4_AXIS_TDATA : in std_logic_vector(31 downto 0);
S4_AXIS_TVALID : in std_logic;
S4_AXIS_TREADY : out std_logic;
M5_AXIS_TLAST : out std_logic;
M5_AXIS_TDATA : out std_logic_vector(31 downto 0);
M5_AXIS_TVALID : out std_logic;
M5_AXIS_TREADY : in std_logic;
S5_AXIS_TLAST : in std_logic;
S5_AXIS_TDATA : in std_logic_vector(31 downto 0);
S5_AXIS_TVALID : in std_logic;
S5_AXIS_TREADY : out std_logic;
M6_AXIS_TLAST : out std_logic;
M6_AXIS_TDATA : out std_logic_vector(31 downto 0);
M6_AXIS_TVALID : out std_logic;
M6_AXIS_TREADY : in std_logic;
S6_AXIS_TLAST : in std_logic;
S6_AXIS_TDATA : in std_logic_vector(31 downto 0);
S6_AXIS_TVALID : in std_logic;
S6_AXIS_TREADY : out std_logic;
M7_AXIS_TLAST : out std_logic;
M7_AXIS_TDATA : out std_logic_vector(31 downto 0);
M7_AXIS_TVALID : out std_logic;
M7_AXIS_TREADY : in std_logic;
S7_AXIS_TLAST : in std_logic;
S7_AXIS_TDATA : in std_logic_vector(31 downto 0);
S7_AXIS_TVALID : in std_logic;
S7_AXIS_TREADY : out std_logic;
M8_AXIS_TLAST : out std_logic;
M8_AXIS_TDATA : out std_logic_vector(31 downto 0);
M8_AXIS_TVALID : out std_logic;
M8_AXIS_TREADY : in std_logic;
S8_AXIS_TLAST : in std_logic;
S8_AXIS_TDATA : in std_logic_vector(31 downto 0);
S8_AXIS_TVALID : in std_logic;
S8_AXIS_TREADY : out std_logic;
M9_AXIS_TLAST : out std_logic;
M9_AXIS_TDATA : out std_logic_vector(31 downto 0);
M9_AXIS_TVALID : out std_logic;
M9_AXIS_TREADY : in std_logic;
S9_AXIS_TLAST : in std_logic;
S9_AXIS_TDATA : in std_logic_vector(31 downto 0);
S9_AXIS_TVALID : in std_logic;
S9_AXIS_TREADY : out std_logic;
M10_AXIS_TLAST : out std_logic;
M10_AXIS_TDATA : out std_logic_vector(31 downto 0);
M10_AXIS_TVALID : out std_logic;
M10_AXIS_TREADY : in std_logic;
S10_AXIS_TLAST : in std_logic;
S10_AXIS_TDATA : in std_logic_vector(31 downto 0);
S10_AXIS_TVALID : in std_logic;
S10_AXIS_TREADY : out std_logic;
M11_AXIS_TLAST : out std_logic;
M11_AXIS_TDATA : out std_logic_vector(31 downto 0);
M11_AXIS_TVALID : out std_logic;
M11_AXIS_TREADY : in std_logic;
S11_AXIS_TLAST : in std_logic;
S11_AXIS_TDATA : in std_logic_vector(31 downto 0);
S11_AXIS_TVALID : in std_logic;
S11_AXIS_TREADY : out std_logic;
M12_AXIS_TLAST : out std_logic;
M12_AXIS_TDATA : out std_logic_vector(31 downto 0);
M12_AXIS_TVALID : out std_logic;
M12_AXIS_TREADY : in std_logic;
S12_AXIS_TLAST : in std_logic;
S12_AXIS_TDATA : in std_logic_vector(31 downto 0);
S12_AXIS_TVALID : in std_logic;
S12_AXIS_TREADY : out std_logic;
M13_AXIS_TLAST : out std_logic;
M13_AXIS_TDATA : out std_logic_vector(31 downto 0);
M13_AXIS_TVALID : out std_logic;
M13_AXIS_TREADY : in std_logic;
S13_AXIS_TLAST : in std_logic;
S13_AXIS_TDATA : in std_logic_vector(31 downto 0);
S13_AXIS_TVALID : in std_logic;
S13_AXIS_TREADY : out std_logic;
M14_AXIS_TLAST : out std_logic;
M14_AXIS_TDATA : out std_logic_vector(31 downto 0);
M14_AXIS_TVALID : out std_logic;
M14_AXIS_TREADY : in std_logic;
S14_AXIS_TLAST : in std_logic;
S14_AXIS_TDATA : in std_logic_vector(31 downto 0);
S14_AXIS_TVALID : in std_logic;
S14_AXIS_TREADY : out std_logic;
M15_AXIS_TLAST : out std_logic;
M15_AXIS_TDATA : out std_logic_vector(31 downto 0);
M15_AXIS_TVALID : out std_logic;
M15_AXIS_TREADY : in std_logic;
S15_AXIS_TLAST : in std_logic;
S15_AXIS_TDATA : in std_logic_vector(31 downto 0);
S15_AXIS_TVALID : in std_logic;
S15_AXIS_TREADY : out std_logic;
ICACHE_FSL_IN_CLK : out std_logic;
ICACHE_FSL_IN_READ : out std_logic;
ICACHE_FSL_IN_DATA : in std_logic_vector(0 to 31);
ICACHE_FSL_IN_CONTROL : in std_logic;
ICACHE_FSL_IN_EXISTS : in std_logic;
ICACHE_FSL_OUT_CLK : out std_logic;
ICACHE_FSL_OUT_WRITE : out std_logic;
ICACHE_FSL_OUT_DATA : out std_logic_vector(0 to 31);
ICACHE_FSL_OUT_CONTROL : out std_logic;
ICACHE_FSL_OUT_FULL : in std_logic;
DCACHE_FSL_IN_CLK : out std_logic;
DCACHE_FSL_IN_READ : out std_logic;
DCACHE_FSL_IN_DATA : in std_logic_vector(0 to 31);
DCACHE_FSL_IN_CONTROL : in std_logic;
DCACHE_FSL_IN_EXISTS : in std_logic;
DCACHE_FSL_OUT_CLK : out std_logic;
DCACHE_FSL_OUT_WRITE : out std_logic;
DCACHE_FSL_OUT_DATA : out std_logic_vector(0 to 31);
DCACHE_FSL_OUT_CONTROL : out std_logic;
DCACHE_FSL_OUT_FULL : in std_logic
);
end component;
component system_mb_plb_wrapper is
port (
PLB_Clk : in std_logic;
SYS_Rst : in std_logic;
PLB_Rst : out std_logic;
SPLB_Rst : out std_logic_vector(0 to 1);
MPLB_Rst : out std_logic_vector(0 to 6);
PLB_dcrAck : out std_logic;
PLB_dcrDBus : out std_logic_vector(0 to 31);
DCR_ABus : in std_logic_vector(0 to 9);
DCR_DBus : in std_logic_vector(0 to 31);
DCR_Read : in std_logic;
DCR_Write : in std_logic;
M_ABus : in std_logic_vector(0 to 223);
M_UABus : in std_logic_vector(0 to 223);
M_BE : in std_logic_vector(0 to 55);
M_RNW : in std_logic_vector(0 to 6);
M_abort : in std_logic_vector(0 to 6);
M_busLock : in std_logic_vector(0 to 6);
M_TAttribute : in std_logic_vector(0 to 111);
M_lockErr : in std_logic_vector(0 to 6);
M_MSize : in std_logic_vector(0 to 13);
M_priority : in std_logic_vector(0 to 13);
M_rdBurst : in std_logic_vector(0 to 6);
M_request : in std_logic_vector(0 to 6);
M_size : in std_logic_vector(0 to 27);
M_type : in std_logic_vector(0 to 20);
M_wrBurst : in std_logic_vector(0 to 6);
M_wrDBus : in std_logic_vector(0 to 447);
Sl_addrAck : in std_logic_vector(0 to 1);
Sl_MRdErr : in std_logic_vector(0 to 13);
Sl_MWrErr : in std_logic_vector(0 to 13);
Sl_MBusy : in std_logic_vector(0 to 13);
Sl_rdBTerm : in std_logic_vector(0 to 1);
Sl_rdComp : in std_logic_vector(0 to 1);
Sl_rdDAck : in std_logic_vector(0 to 1);
Sl_rdDBus : in std_logic_vector(0 to 127);
Sl_rdWdAddr : in std_logic_vector(0 to 7);
Sl_rearbitrate : in std_logic_vector(0 to 1);
Sl_SSize : in std_logic_vector(0 to 3);
Sl_wait : in std_logic_vector(0 to 1);
Sl_wrBTerm : in std_logic_vector(0 to 1);
Sl_wrComp : in std_logic_vector(0 to 1);
Sl_wrDAck : in std_logic_vector(0 to 1);
Sl_MIRQ : in std_logic_vector(0 to 13);
PLB_MIRQ : out std_logic_vector(0 to 6);
PLB_ABus : out std_logic_vector(0 to 31);
PLB_UABus : out std_logic_vector(0 to 31);
PLB_BE : out std_logic_vector(0 to 7);
PLB_MAddrAck : out std_logic_vector(0 to 6);
PLB_MTimeout : out std_logic_vector(0 to 6);
PLB_MBusy : out std_logic_vector(0 to 6);
PLB_MRdErr : out std_logic_vector(0 to 6);
PLB_MWrErr : out std_logic_vector(0 to 6);
PLB_MRdBTerm : out std_logic_vector(0 to 6);
PLB_MRdDAck : out std_logic_vector(0 to 6);
PLB_MRdDBus : out std_logic_vector(0 to 447);
PLB_MRdWdAddr : out std_logic_vector(0 to 27);
PLB_MRearbitrate : out std_logic_vector(0 to 6);
PLB_MWrBTerm : out std_logic_vector(0 to 6);
PLB_MWrDAck : out std_logic_vector(0 to 6);
PLB_MSSize : out std_logic_vector(0 to 13);
PLB_PAValid : out std_logic;
PLB_RNW : out std_logic;
PLB_SAValid : out std_logic;
PLB_abort : out std_logic;
PLB_busLock : out std_logic;
PLB_TAttribute : out std_logic_vector(0 to 15);
PLB_lockErr : out std_logic;
PLB_masterID : out std_logic_vector(0 to 2);
PLB_MSize : out std_logic_vector(0 to 1);
PLB_rdPendPri : out std_logic_vector(0 to 1);
PLB_wrPendPri : out std_logic_vector(0 to 1);
PLB_rdPendReq : out std_logic;
PLB_wrPendReq : out std_logic;
PLB_rdBurst : out std_logic;
PLB_rdPrim : out std_logic_vector(0 to 1);
PLB_reqPri : out std_logic_vector(0 to 1);
PLB_size : out std_logic_vector(0 to 3);
PLB_type : out std_logic_vector(0 to 2);
PLB_wrBurst : out std_logic;
PLB_wrDBus : out std_logic_vector(0 to 63);
PLB_wrPrim : out std_logic_vector(0 to 1);
PLB_SaddrAck : out std_logic;
PLB_SMRdErr : out std_logic_vector(0 to 6);
PLB_SMWrErr : out std_logic_vector(0 to 6);
PLB_SMBusy : out std_logic_vector(0 to 6);
PLB_SrdBTerm : out std_logic;
PLB_SrdComp : out std_logic;
PLB_SrdDAck : out std_logic;
PLB_SrdDBus : out std_logic_vector(0 to 63);
PLB_SrdWdAddr : out std_logic_vector(0 to 3);
PLB_Srearbitrate : out std_logic;
PLB_Sssize : out std_logic_vector(0 to 1);
PLB_Swait : out std_logic;
PLB_SwrBTerm : out std_logic;
PLB_SwrComp : out std_logic;
PLB_SwrDAck : out std_logic;
Bus_Error_Det : out std_logic
);
end component;
component system_ilmb_wrapper is
port (
LMB_Clk : in std_logic;
SYS_Rst : in std_logic;
LMB_Rst : out std_logic;
M_ABus : in std_logic_vector(0 to 31);
M_ReadStrobe : in std_logic;
M_WriteStrobe : in std_logic;
M_AddrStrobe : in std_logic;
M_DBus : in std_logic_vector(0 to 31);
M_BE : in std_logic_vector(0 to 3);
Sl_DBus : in std_logic_vector(0 to 31);
Sl_Ready : in std_logic_vector(0 to 0);
Sl_Wait : in std_logic_vector(0 to 0);
Sl_UE : in std_logic_vector(0 to 0);
Sl_CE : in std_logic_vector(0 to 0);
LMB_ABus : out std_logic_vector(0 to 31);
LMB_ReadStrobe : out std_logic;
LMB_WriteStrobe : out std_logic;
LMB_AddrStrobe : out std_logic;
LMB_ReadDBus : out std_logic_vector(0 to 31);
LMB_WriteDBus : out std_logic_vector(0 to 31);
LMB_Ready : out std_logic;
LMB_Wait : out std_logic;
LMB_UE : out std_logic;
LMB_CE : out std_logic;
LMB_BE : out std_logic_vector(0 to 3)
);
end component;
component system_dlmb_wrapper is
port (
LMB_Clk : in std_logic;
SYS_Rst : in std_logic;
LMB_Rst : out std_logic;
M_ABus : in std_logic_vector(0 to 31);
M_ReadStrobe : in std_logic;
M_WriteStrobe : in std_logic;
M_AddrStrobe : in std_logic;
M_DBus : in std_logic_vector(0 to 31);
M_BE : in std_logic_vector(0 to 3);
Sl_DBus : in std_logic_vector(0 to 31);
Sl_Ready : in std_logic_vector(0 to 0);
Sl_Wait : in std_logic_vector(0 to 0);
Sl_UE : in std_logic_vector(0 to 0);
Sl_CE : in std_logic_vector(0 to 0);
LMB_ABus : out std_logic_vector(0 to 31);
LMB_ReadStrobe : out std_logic;
LMB_WriteStrobe : out std_logic;
LMB_AddrStrobe : out std_logic;
LMB_ReadDBus : out std_logic_vector(0 to 31);
LMB_WriteDBus : out std_logic_vector(0 to 31);
LMB_Ready : out std_logic;
LMB_Wait : out std_logic;
LMB_UE : out std_logic;
LMB_CE : out std_logic;
LMB_BE : out std_logic_vector(0 to 3)
);
end component;
component system_dlmb_cntlr_wrapper is
port (
LMB_Clk : in std_logic;
LMB_Rst : in std_logic;
LMB_ABus : in std_logic_vector(0 to 31);
LMB_WriteDBus : in std_logic_vector(0 to 31);
LMB_AddrStrobe : in std_logic;
LMB_ReadStrobe : in std_logic;
LMB_WriteStrobe : in std_logic;
LMB_BE : in std_logic_vector(0 to 3);
Sl_DBus : out std_logic_vector(0 to 31);
Sl_Ready : out std_logic;
Sl_Wait : out std_logic;
Sl_UE : out std_logic;
Sl_CE : out std_logic;
LMB1_ABus : in std_logic_vector(0 to 31);
LMB1_WriteDBus : in std_logic_vector(0 to 31);
LMB1_AddrStrobe : in std_logic;
LMB1_ReadStrobe : in std_logic;
LMB1_WriteStrobe : in std_logic;
LMB1_BE : in std_logic_vector(0 to 3);
Sl1_DBus : out std_logic_vector(0 to 31);
Sl1_Ready : out std_logic;
Sl1_Wait : out std_logic;
Sl1_UE : out std_logic;
Sl1_CE : out std_logic;
LMB2_ABus : in std_logic_vector(0 to 31);
LMB2_WriteDBus : in std_logic_vector(0 to 31);
LMB2_AddrStrobe : in std_logic;
LMB2_ReadStrobe : in std_logic;
LMB2_WriteStrobe : in std_logic;
LMB2_BE : in std_logic_vector(0 to 3);
Sl2_DBus : out std_logic_vector(0 to 31);
Sl2_Ready : out std_logic;
Sl2_Wait : out std_logic;
Sl2_UE : out std_logic;
Sl2_CE : out std_logic;
LMB3_ABus : in std_logic_vector(0 to 31);
LMB3_WriteDBus : in std_logic_vector(0 to 31);
LMB3_AddrStrobe : in std_logic;
LMB3_ReadStrobe : in std_logic;
LMB3_WriteStrobe : in std_logic;
LMB3_BE : in std_logic_vector(0 to 3);
Sl3_DBus : out std_logic_vector(0 to 31);
Sl3_Ready : out std_logic;
Sl3_Wait : out std_logic;
Sl3_UE : out std_logic;
Sl3_CE : out std_logic;
BRAM_Rst_A : out std_logic;
BRAM_Clk_A : out std_logic;
BRAM_EN_A : out std_logic;
BRAM_WEN_A : out std_logic_vector(0 to 3);
BRAM_Addr_A : out std_logic_vector(0 to 31);
BRAM_Din_A : in std_logic_vector(0 to 31);
BRAM_Dout_A : out std_logic_vector(0 to 31);
Interrupt : out std_logic;
UE : out std_logic;
CE : out std_logic;
SPLB_CTRL_PLB_ABus : in std_logic_vector(0 to 31);
SPLB_CTRL_PLB_PAValid : in std_logic;
SPLB_CTRL_PLB_masterID : in std_logic_vector(0 to 0);
SPLB_CTRL_PLB_RNW : in std_logic;
SPLB_CTRL_PLB_BE : in std_logic_vector(0 to 3);
SPLB_CTRL_PLB_size : in std_logic_vector(0 to 3);
SPLB_CTRL_PLB_type : in std_logic_vector(0 to 2);
SPLB_CTRL_PLB_wrDBus : in std_logic_vector(0 to 31);
SPLB_CTRL_Sl_addrAck : out std_logic;
SPLB_CTRL_Sl_SSize : out std_logic_vector(0 to 1);
SPLB_CTRL_Sl_wait : out std_logic;
SPLB_CTRL_Sl_rearbitrate : out std_logic;
SPLB_CTRL_Sl_wrDAck : out std_logic;
SPLB_CTRL_Sl_wrComp : out std_logic;
SPLB_CTRL_Sl_rdDBus : out std_logic_vector(0 to 31);
SPLB_CTRL_Sl_rdDAck : out std_logic;
SPLB_CTRL_Sl_rdComp : out std_logic;
SPLB_CTRL_Sl_MBusy : out std_logic_vector(0 to 0);
SPLB_CTRL_Sl_MWrErr : out std_logic_vector(0 to 0);
SPLB_CTRL_Sl_MRdErr : out std_logic_vector(0 to 0);
SPLB_CTRL_PLB_UABus : in std_logic_vector(0 to 31);
SPLB_CTRL_PLB_SAValid : in std_logic;
SPLB_CTRL_PLB_rdPrim : in std_logic;
SPLB_CTRL_PLB_wrPrim : in std_logic;
SPLB_CTRL_PLB_abort : in std_logic;
SPLB_CTRL_PLB_busLock : in std_logic;
SPLB_CTRL_PLB_MSize : in std_logic_vector(0 to 1);
SPLB_CTRL_PLB_lockErr : in std_logic;
SPLB_CTRL_PLB_wrBurst : in std_logic;
SPLB_CTRL_PLB_rdBurst : in std_logic;
SPLB_CTRL_PLB_wrPendReq : in std_logic;
SPLB_CTRL_PLB_rdPendReq : in std_logic;
SPLB_CTRL_PLB_wrPendPri : in std_logic_vector(0 to 1);
SPLB_CTRL_PLB_rdPendPri : in std_logic_vector(0 to 1);
SPLB_CTRL_PLB_reqPri : in std_logic_vector(0 to 1);
SPLB_CTRL_PLB_TAttribute : in std_logic_vector(0 to 15);
SPLB_CTRL_Sl_wrBTerm : out std_logic;
SPLB_CTRL_Sl_rdWdAddr : out std_logic_vector(0 to 3);
SPLB_CTRL_Sl_rdBTerm : out std_logic;
SPLB_CTRL_Sl_MIRQ : out std_logic_vector(0 to 0);
S_AXI_CTRL_ACLK : in std_logic;
S_AXI_CTRL_ARESETN : in std_logic;
S_AXI_CTRL_AWADDR : in std_logic_vector(31 downto 0);
S_AXI_CTRL_AWVALID : in std_logic;
S_AXI_CTRL_AWREADY : out std_logic;
S_AXI_CTRL_WDATA : in std_logic_vector(31 downto 0);
S_AXI_CTRL_WSTRB : in std_logic_vector(3 downto 0);
S_AXI_CTRL_WVALID : in std_logic;
S_AXI_CTRL_WREADY : out std_logic;
S_AXI_CTRL_BRESP : out std_logic_vector(1 downto 0);
S_AXI_CTRL_BVALID : out std_logic;
S_AXI_CTRL_BREADY : in std_logic;
S_AXI_CTRL_ARADDR : in std_logic_vector(31 downto 0);
S_AXI_CTRL_ARVALID : in std_logic;
S_AXI_CTRL_ARREADY : out std_logic;
S_AXI_CTRL_RDATA : out std_logic_vector(31 downto 0);
S_AXI_CTRL_RRESP : out std_logic_vector(1 downto 0);
S_AXI_CTRL_RVALID : out std_logic;
S_AXI_CTRL_RREADY : in std_logic
);
end component;
component system_ilmb_cntlr_wrapper is
port (
LMB_Clk : in std_logic;
LMB_Rst : in std_logic;
LMB_ABus : in std_logic_vector(0 to 31);
LMB_WriteDBus : in std_logic_vector(0 to 31);
LMB_AddrStrobe : in std_logic;
LMB_ReadStrobe : in std_logic;
LMB_WriteStrobe : in std_logic;
LMB_BE : in std_logic_vector(0 to 3);
Sl_DBus : out std_logic_vector(0 to 31);
Sl_Ready : out std_logic;
Sl_Wait : out std_logic;
Sl_UE : out std_logic;
Sl_CE : out std_logic;
LMB1_ABus : in std_logic_vector(0 to 31);
LMB1_WriteDBus : in std_logic_vector(0 to 31);
LMB1_AddrStrobe : in std_logic;
LMB1_ReadStrobe : in std_logic;
LMB1_WriteStrobe : in std_logic;
LMB1_BE : in std_logic_vector(0 to 3);
Sl1_DBus : out std_logic_vector(0 to 31);
Sl1_Ready : out std_logic;
Sl1_Wait : out std_logic;
Sl1_UE : out std_logic;
Sl1_CE : out std_logic;
LMB2_ABus : in std_logic_vector(0 to 31);
LMB2_WriteDBus : in std_logic_vector(0 to 31);
LMB2_AddrStrobe : in std_logic;
LMB2_ReadStrobe : in std_logic;
LMB2_WriteStrobe : in std_logic;
LMB2_BE : in std_logic_vector(0 to 3);
Sl2_DBus : out std_logic_vector(0 to 31);
Sl2_Ready : out std_logic;
Sl2_Wait : out std_logic;
Sl2_UE : out std_logic;
Sl2_CE : out std_logic;
LMB3_ABus : in std_logic_vector(0 to 31);
LMB3_WriteDBus : in std_logic_vector(0 to 31);
LMB3_AddrStrobe : in std_logic;
LMB3_ReadStrobe : in std_logic;
LMB3_WriteStrobe : in std_logic;
LMB3_BE : in std_logic_vector(0 to 3);
Sl3_DBus : out std_logic_vector(0 to 31);
Sl3_Ready : out std_logic;
Sl3_Wait : out std_logic;
Sl3_UE : out std_logic;
Sl3_CE : out std_logic;
BRAM_Rst_A : out std_logic;
BRAM_Clk_A : out std_logic;
BRAM_EN_A : out std_logic;
BRAM_WEN_A : out std_logic_vector(0 to 3);
BRAM_Addr_A : out std_logic_vector(0 to 31);
BRAM_Din_A : in std_logic_vector(0 to 31);
BRAM_Dout_A : out std_logic_vector(0 to 31);
Interrupt : out std_logic;
UE : out std_logic;
CE : out std_logic;
SPLB_CTRL_PLB_ABus : in std_logic_vector(0 to 31);
SPLB_CTRL_PLB_PAValid : in std_logic;
SPLB_CTRL_PLB_masterID : in std_logic_vector(0 to 0);
SPLB_CTRL_PLB_RNW : in std_logic;
SPLB_CTRL_PLB_BE : in std_logic_vector(0 to 3);
SPLB_CTRL_PLB_size : in std_logic_vector(0 to 3);
SPLB_CTRL_PLB_type : in std_logic_vector(0 to 2);
SPLB_CTRL_PLB_wrDBus : in std_logic_vector(0 to 31);
SPLB_CTRL_Sl_addrAck : out std_logic;
SPLB_CTRL_Sl_SSize : out std_logic_vector(0 to 1);
SPLB_CTRL_Sl_wait : out std_logic;
SPLB_CTRL_Sl_rearbitrate : out std_logic;
SPLB_CTRL_Sl_wrDAck : out std_logic;
SPLB_CTRL_Sl_wrComp : out std_logic;
SPLB_CTRL_Sl_rdDBus : out std_logic_vector(0 to 31);
SPLB_CTRL_Sl_rdDAck : out std_logic;
SPLB_CTRL_Sl_rdComp : out std_logic;
SPLB_CTRL_Sl_MBusy : out std_logic_vector(0 to 0);
SPLB_CTRL_Sl_MWrErr : out std_logic_vector(0 to 0);
SPLB_CTRL_Sl_MRdErr : out std_logic_vector(0 to 0);
SPLB_CTRL_PLB_UABus : in std_logic_vector(0 to 31);
SPLB_CTRL_PLB_SAValid : in std_logic;
SPLB_CTRL_PLB_rdPrim : in std_logic;
SPLB_CTRL_PLB_wrPrim : in std_logic;
SPLB_CTRL_PLB_abort : in std_logic;
SPLB_CTRL_PLB_busLock : in std_logic;
SPLB_CTRL_PLB_MSize : in std_logic_vector(0 to 1);
SPLB_CTRL_PLB_lockErr : in std_logic;
SPLB_CTRL_PLB_wrBurst : in std_logic;
SPLB_CTRL_PLB_rdBurst : in std_logic;
SPLB_CTRL_PLB_wrPendReq : in std_logic;
SPLB_CTRL_PLB_rdPendReq : in std_logic;
SPLB_CTRL_PLB_wrPendPri : in std_logic_vector(0 to 1);
SPLB_CTRL_PLB_rdPendPri : in std_logic_vector(0 to 1);
SPLB_CTRL_PLB_reqPri : in std_logic_vector(0 to 1);
SPLB_CTRL_PLB_TAttribute : in std_logic_vector(0 to 15);
SPLB_CTRL_Sl_wrBTerm : out std_logic;
SPLB_CTRL_Sl_rdWdAddr : out std_logic_vector(0 to 3);
SPLB_CTRL_Sl_rdBTerm : out std_logic;
SPLB_CTRL_Sl_MIRQ : out std_logic_vector(0 to 0);
S_AXI_CTRL_ACLK : in std_logic;
S_AXI_CTRL_ARESETN : in std_logic;
S_AXI_CTRL_AWADDR : in std_logic_vector(31 downto 0);
S_AXI_CTRL_AWVALID : in std_logic;
S_AXI_CTRL_AWREADY : out std_logic;
S_AXI_CTRL_WDATA : in std_logic_vector(31 downto 0);
S_AXI_CTRL_WSTRB : in std_logic_vector(3 downto 0);
S_AXI_CTRL_WVALID : in std_logic;
S_AXI_CTRL_WREADY : out std_logic;
S_AXI_CTRL_BRESP : out std_logic_vector(1 downto 0);
S_AXI_CTRL_BVALID : out std_logic;
S_AXI_CTRL_BREADY : in std_logic;
S_AXI_CTRL_ARADDR : in std_logic_vector(31 downto 0);
S_AXI_CTRL_ARVALID : in std_logic;
S_AXI_CTRL_ARREADY : out std_logic;
S_AXI_CTRL_RDATA : out std_logic_vector(31 downto 0);
S_AXI_CTRL_RRESP : out std_logic_vector(1 downto 0);
S_AXI_CTRL_RVALID : out std_logic;
S_AXI_CTRL_RREADY : in std_logic
);
end component;
component system_lmb_bram_wrapper is
port (
BRAM_Rst_A : in std_logic;
BRAM_Clk_A : in std_logic;
BRAM_EN_A : in std_logic;
BRAM_WEN_A : in std_logic_vector(0 to 3);
BRAM_Addr_A : in std_logic_vector(0 to 31);
BRAM_Din_A : out std_logic_vector(0 to 31);
BRAM_Dout_A : in std_logic_vector(0 to 31);
BRAM_Rst_B : in std_logic;
BRAM_Clk_B : in std_logic;
BRAM_EN_B : in std_logic;
BRAM_WEN_B : in std_logic_vector(0 to 3);
BRAM_Addr_B : in std_logic_vector(0 to 31);
BRAM_Din_B : out std_logic_vector(0 to 31);
BRAM_Dout_B : in std_logic_vector(0 to 31)
);
end component;
component system_clock_generator_0_wrapper is
port (
CLKIN : in std_logic;
CLKOUT0 : out std_logic;
CLKOUT1 : out std_logic;
CLKOUT2 : out std_logic;
CLKOUT3 : out std_logic;
CLKOUT4 : out std_logic;
CLKOUT5 : out std_logic;
CLKOUT6 : out std_logic;
CLKOUT7 : out std_logic;
CLKOUT8 : out std_logic;
CLKOUT9 : out std_logic;
CLKOUT10 : out std_logic;
CLKOUT11 : out std_logic;
CLKOUT12 : out std_logic;
CLKOUT13 : out std_logic;
CLKOUT14 : out std_logic;
CLKOUT15 : out std_logic;
CLKFBIN : in std_logic;
CLKFBOUT : out std_logic;
PSCLK : in std_logic;
PSEN : in std_logic;
PSINCDEC : in std_logic;
PSDONE : out std_logic;
RST : in std_logic;
LOCKED : out std_logic
);
end component;
component system_mdm_0_wrapper is
port (
Interrupt : out std_logic;
Debug_SYS_Rst : out std_logic;
Ext_BRK : out std_logic;
Ext_NM_BRK : out std_logic;
S_AXI_ACLK : in std_logic;
S_AXI_ARESETN : in std_logic;
S_AXI_AWADDR : in std_logic_vector(31 downto 0);
S_AXI_AWVALID : in std_logic;
S_AXI_AWREADY : out std_logic;
S_AXI_WDATA : in std_logic_vector(31 downto 0);
S_AXI_WSTRB : in std_logic_vector(3 downto 0);
S_AXI_WVALID : in std_logic;
S_AXI_WREADY : out std_logic;
S_AXI_BRESP : out std_logic_vector(1 downto 0);
S_AXI_BVALID : out std_logic;
S_AXI_BREADY : in std_logic;
S_AXI_ARADDR : in std_logic_vector(31 downto 0);
S_AXI_ARVALID : in std_logic;
S_AXI_ARREADY : out std_logic;
S_AXI_RDATA : out std_logic_vector(31 downto 0);
S_AXI_RRESP : out std_logic_vector(1 downto 0);
S_AXI_RVALID : out std_logic;
S_AXI_RREADY : in std_logic;
SPLB_Clk : in std_logic;
SPLB_Rst : in std_logic;
PLB_ABus : in std_logic_vector(0 to 31);
PLB_UABus : in std_logic_vector(0 to 31);
PLB_PAValid : in std_logic;
PLB_SAValid : in std_logic;
PLB_rdPrim : in std_logic;
PLB_wrPrim : in std_logic;
PLB_masterID : in std_logic_vector(0 to 2);
PLB_abort : in std_logic;
PLB_busLock : in std_logic;
PLB_RNW : in std_logic;
PLB_BE : in std_logic_vector(0 to 7);
PLB_MSize : in std_logic_vector(0 to 1);
PLB_size : in std_logic_vector(0 to 3);
PLB_type : in std_logic_vector(0 to 2);
PLB_lockErr : in std_logic;
PLB_wrDBus : in std_logic_vector(0 to 63);
PLB_wrBurst : in std_logic;
PLB_rdBurst : in std_logic;
PLB_wrPendReq : in std_logic;
PLB_rdPendReq : in std_logic;
PLB_wrPendPri : in std_logic_vector(0 to 1);
PLB_rdPendPri : in std_logic_vector(0 to 1);
PLB_reqPri : in std_logic_vector(0 to 1);
PLB_TAttribute : in std_logic_vector(0 to 15);
Sl_addrAck : out std_logic;
Sl_SSize : out std_logic_vector(0 to 1);
Sl_wait : out std_logic;
Sl_rearbitrate : out std_logic;
Sl_wrDAck : out std_logic;
Sl_wrComp : out std_logic;
Sl_wrBTerm : out std_logic;
Sl_rdDBus : out std_logic_vector(0 to 63);
Sl_rdWdAddr : out std_logic_vector(0 to 3);
Sl_rdDAck : out std_logic;
Sl_rdComp : out std_logic;
Sl_rdBTerm : out std_logic;
Sl_MBusy : out std_logic_vector(0 to 6);
Sl_MWrErr : out std_logic_vector(0 to 6);
Sl_MRdErr : out std_logic_vector(0 to 6);
Sl_MIRQ : out std_logic_vector(0 to 6);
Dbg_Clk_0 : out std_logic;
Dbg_TDI_0 : out std_logic;
Dbg_TDO_0 : in std_logic;
Dbg_Reg_En_0 : out std_logic_vector(0 to 7);
Dbg_Capture_0 : out std_logic;
Dbg_Shift_0 : out std_logic;
Dbg_Update_0 : out std_logic;
Dbg_Rst_0 : out std_logic;
Dbg_Clk_1 : out std_logic;
Dbg_TDI_1 : out std_logic;
Dbg_TDO_1 : in std_logic;
Dbg_Reg_En_1 : out std_logic_vector(0 to 7);
Dbg_Capture_1 : out std_logic;
Dbg_Shift_1 : out std_logic;
Dbg_Update_1 : out std_logic;
Dbg_Rst_1 : out std_logic;
Dbg_Clk_2 : out std_logic;
Dbg_TDI_2 : out std_logic;
Dbg_TDO_2 : in std_logic;
Dbg_Reg_En_2 : out std_logic_vector(0 to 7);
Dbg_Capture_2 : out std_logic;
Dbg_Shift_2 : out std_logic;
Dbg_Update_2 : out std_logic;
Dbg_Rst_2 : out std_logic;
Dbg_Clk_3 : out std_logic;
Dbg_TDI_3 : out std_logic;
Dbg_TDO_3 : in std_logic;
Dbg_Reg_En_3 : out std_logic_vector(0 to 7);
Dbg_Capture_3 : out std_logic;
Dbg_Shift_3 : out std_logic;
Dbg_Update_3 : out std_logic;
Dbg_Rst_3 : out std_logic;
Dbg_Clk_4 : out std_logic;
Dbg_TDI_4 : out std_logic;
Dbg_TDO_4 : in std_logic;
Dbg_Reg_En_4 : out std_logic_vector(0 to 7);
Dbg_Capture_4 : out std_logic;
Dbg_Shift_4 : out std_logic;
Dbg_Update_4 : out std_logic;
Dbg_Rst_4 : out std_logic;
Dbg_Clk_5 : out std_logic;
Dbg_TDI_5 : out std_logic;
Dbg_TDO_5 : in std_logic;
Dbg_Reg_En_5 : out std_logic_vector(0 to 7);
Dbg_Capture_5 : out std_logic;
Dbg_Shift_5 : out std_logic;
Dbg_Update_5 : out std_logic;
Dbg_Rst_5 : out std_logic;
Dbg_Clk_6 : out std_logic;
Dbg_TDI_6 : out std_logic;
Dbg_TDO_6 : in std_logic;
Dbg_Reg_En_6 : out std_logic_vector(0 to 7);
Dbg_Capture_6 : out std_logic;
Dbg_Shift_6 : out std_logic;
Dbg_Update_6 : out std_logic;
Dbg_Rst_6 : out std_logic;
Dbg_Clk_7 : out std_logic;
Dbg_TDI_7 : out std_logic;
Dbg_TDO_7 : in std_logic;
Dbg_Reg_En_7 : out std_logic_vector(0 to 7);
Dbg_Capture_7 : out std_logic;
Dbg_Shift_7 : out std_logic;
Dbg_Update_7 : out std_logic;
Dbg_Rst_7 : out std_logic;
Dbg_Clk_8 : out std_logic;
Dbg_TDI_8 : out std_logic;
Dbg_TDO_8 : in std_logic;
Dbg_Reg_En_8 : out std_logic_vector(0 to 7);
Dbg_Capture_8 : out std_logic;
Dbg_Shift_8 : out std_logic;
Dbg_Update_8 : out std_logic;
Dbg_Rst_8 : out std_logic;
Dbg_Clk_9 : out std_logic;
Dbg_TDI_9 : out std_logic;
Dbg_TDO_9 : in std_logic;
Dbg_Reg_En_9 : out std_logic_vector(0 to 7);
Dbg_Capture_9 : out std_logic;
Dbg_Shift_9 : out std_logic;
Dbg_Update_9 : out std_logic;
Dbg_Rst_9 : out std_logic;
Dbg_Clk_10 : out std_logic;
Dbg_TDI_10 : out std_logic;
Dbg_TDO_10 : in std_logic;
Dbg_Reg_En_10 : out std_logic_vector(0 to 7);
Dbg_Capture_10 : out std_logic;
Dbg_Shift_10 : out std_logic;
Dbg_Update_10 : out std_logic;
Dbg_Rst_10 : out std_logic;
Dbg_Clk_11 : out std_logic;
Dbg_TDI_11 : out std_logic;
Dbg_TDO_11 : in std_logic;
Dbg_Reg_En_11 : out std_logic_vector(0 to 7);
Dbg_Capture_11 : out std_logic;
Dbg_Shift_11 : out std_logic;
Dbg_Update_11 : out std_logic;
Dbg_Rst_11 : out std_logic;
Dbg_Clk_12 : out std_logic;
Dbg_TDI_12 : out std_logic;
Dbg_TDO_12 : in std_logic;
Dbg_Reg_En_12 : out std_logic_vector(0 to 7);
Dbg_Capture_12 : out std_logic;
Dbg_Shift_12 : out std_logic;
Dbg_Update_12 : out std_logic;
Dbg_Rst_12 : out std_logic;
Dbg_Clk_13 : out std_logic;
Dbg_TDI_13 : out std_logic;
Dbg_TDO_13 : in std_logic;
Dbg_Reg_En_13 : out std_logic_vector(0 to 7);
Dbg_Capture_13 : out std_logic;
Dbg_Shift_13 : out std_logic;
Dbg_Update_13 : out std_logic;
Dbg_Rst_13 : out std_logic;
Dbg_Clk_14 : out std_logic;
Dbg_TDI_14 : out std_logic;
Dbg_TDO_14 : in std_logic;
Dbg_Reg_En_14 : out std_logic_vector(0 to 7);
Dbg_Capture_14 : out std_logic;
Dbg_Shift_14 : out std_logic;
Dbg_Update_14 : out std_logic;
Dbg_Rst_14 : out std_logic;
Dbg_Clk_15 : out std_logic;
Dbg_TDI_15 : out std_logic;
Dbg_TDO_15 : in std_logic;
Dbg_Reg_En_15 : out std_logic_vector(0 to 7);
Dbg_Capture_15 : out std_logic;
Dbg_Shift_15 : out std_logic;
Dbg_Update_15 : out std_logic;
Dbg_Rst_15 : out std_logic;
Dbg_Clk_16 : out std_logic;
Dbg_TDI_16 : out std_logic;
Dbg_TDO_16 : in std_logic;
Dbg_Reg_En_16 : out std_logic_vector(0 to 7);
Dbg_Capture_16 : out std_logic;
Dbg_Shift_16 : out std_logic;
Dbg_Update_16 : out std_logic;
Dbg_Rst_16 : out std_logic;
Dbg_Clk_17 : out std_logic;
Dbg_TDI_17 : out std_logic;
Dbg_TDO_17 : in std_logic;
Dbg_Reg_En_17 : out std_logic_vector(0 to 7);
Dbg_Capture_17 : out std_logic;
Dbg_Shift_17 : out std_logic;
Dbg_Update_17 : out std_logic;
Dbg_Rst_17 : out std_logic;
Dbg_Clk_18 : out std_logic;
Dbg_TDI_18 : out std_logic;
Dbg_TDO_18 : in std_logic;
Dbg_Reg_En_18 : out std_logic_vector(0 to 7);
Dbg_Capture_18 : out std_logic;
Dbg_Shift_18 : out std_logic;
Dbg_Update_18 : out std_logic;
Dbg_Rst_18 : out std_logic;
Dbg_Clk_19 : out std_logic;
Dbg_TDI_19 : out std_logic;
Dbg_TDO_19 : in std_logic;
Dbg_Reg_En_19 : out std_logic_vector(0 to 7);
Dbg_Capture_19 : out std_logic;
Dbg_Shift_19 : out std_logic;
Dbg_Update_19 : out std_logic;
Dbg_Rst_19 : out std_logic;
Dbg_Clk_20 : out std_logic;
Dbg_TDI_20 : out std_logic;
Dbg_TDO_20 : in std_logic;
Dbg_Reg_En_20 : out std_logic_vector(0 to 7);
Dbg_Capture_20 : out std_logic;
Dbg_Shift_20 : out std_logic;
Dbg_Update_20 : out std_logic;
Dbg_Rst_20 : out std_logic;
Dbg_Clk_21 : out std_logic;
Dbg_TDI_21 : out std_logic;
Dbg_TDO_21 : in std_logic;
Dbg_Reg_En_21 : out std_logic_vector(0 to 7);
Dbg_Capture_21 : out std_logic;
Dbg_Shift_21 : out std_logic;
Dbg_Update_21 : out std_logic;
Dbg_Rst_21 : out std_logic;
Dbg_Clk_22 : out std_logic;
Dbg_TDI_22 : out std_logic;
Dbg_TDO_22 : in std_logic;
Dbg_Reg_En_22 : out std_logic_vector(0 to 7);
Dbg_Capture_22 : out std_logic;
Dbg_Shift_22 : out std_logic;
Dbg_Update_22 : out std_logic;
Dbg_Rst_22 : out std_logic;
Dbg_Clk_23 : out std_logic;
Dbg_TDI_23 : out std_logic;
Dbg_TDO_23 : in std_logic;
Dbg_Reg_En_23 : out std_logic_vector(0 to 7);
Dbg_Capture_23 : out std_logic;
Dbg_Shift_23 : out std_logic;
Dbg_Update_23 : out std_logic;
Dbg_Rst_23 : out std_logic;
Dbg_Clk_24 : out std_logic;
Dbg_TDI_24 : out std_logic;
Dbg_TDO_24 : in std_logic;
Dbg_Reg_En_24 : out std_logic_vector(0 to 7);
Dbg_Capture_24 : out std_logic;
Dbg_Shift_24 : out std_logic;
Dbg_Update_24 : out std_logic;
Dbg_Rst_24 : out std_logic;
Dbg_Clk_25 : out std_logic;
Dbg_TDI_25 : out std_logic;
Dbg_TDO_25 : in std_logic;
Dbg_Reg_En_25 : out std_logic_vector(0 to 7);
Dbg_Capture_25 : out std_logic;
Dbg_Shift_25 : out std_logic;
Dbg_Update_25 : out std_logic;
Dbg_Rst_25 : out std_logic;
Dbg_Clk_26 : out std_logic;
Dbg_TDI_26 : out std_logic;
Dbg_TDO_26 : in std_logic;
Dbg_Reg_En_26 : out std_logic_vector(0 to 7);
Dbg_Capture_26 : out std_logic;
Dbg_Shift_26 : out std_logic;
Dbg_Update_26 : out std_logic;
Dbg_Rst_26 : out std_logic;
Dbg_Clk_27 : out std_logic;
Dbg_TDI_27 : out std_logic;
Dbg_TDO_27 : in std_logic;
Dbg_Reg_En_27 : out std_logic_vector(0 to 7);
Dbg_Capture_27 : out std_logic;
Dbg_Shift_27 : out std_logic;
Dbg_Update_27 : out std_logic;
Dbg_Rst_27 : out std_logic;
Dbg_Clk_28 : out std_logic;
Dbg_TDI_28 : out std_logic;
Dbg_TDO_28 : in std_logic;
Dbg_Reg_En_28 : out std_logic_vector(0 to 7);
Dbg_Capture_28 : out std_logic;
Dbg_Shift_28 : out std_logic;
Dbg_Update_28 : out std_logic;
Dbg_Rst_28 : out std_logic;
Dbg_Clk_29 : out std_logic;
Dbg_TDI_29 : out std_logic;
Dbg_TDO_29 : in std_logic;
Dbg_Reg_En_29 : out std_logic_vector(0 to 7);
Dbg_Capture_29 : out std_logic;
Dbg_Shift_29 : out std_logic;
Dbg_Update_29 : out std_logic;
Dbg_Rst_29 : out std_logic;
Dbg_Clk_30 : out std_logic;
Dbg_TDI_30 : out std_logic;
Dbg_TDO_30 : in std_logic;
Dbg_Reg_En_30 : out std_logic_vector(0 to 7);
Dbg_Capture_30 : out std_logic;
Dbg_Shift_30 : out std_logic;
Dbg_Update_30 : out std_logic;
Dbg_Rst_30 : out std_logic;
Dbg_Clk_31 : out std_logic;
Dbg_TDI_31 : out std_logic;
Dbg_TDO_31 : in std_logic;
Dbg_Reg_En_31 : out std_logic_vector(0 to 7);
Dbg_Capture_31 : out std_logic;
Dbg_Shift_31 : out std_logic;
Dbg_Update_31 : out std_logic;
Dbg_Rst_31 : out std_logic;
bscan_tdi : out std_logic;
bscan_reset : out std_logic;
bscan_shift : out std_logic;
bscan_update : out std_logic;
bscan_capture : out std_logic;
bscan_sel1 : out std_logic;
bscan_drck1 : out std_logic;
bscan_tdo1 : in std_logic;
bscan_ext_tdi : in std_logic;
bscan_ext_reset : in std_logic;
bscan_ext_shift : in std_logic;
bscan_ext_update : in std_logic;
bscan_ext_capture : in std_logic;
bscan_ext_sel : in std_logic;
bscan_ext_drck : in std_logic;
bscan_ext_tdo : out std_logic;
Ext_JTAG_DRCK : out std_logic;
Ext_JTAG_RESET : out std_logic;
Ext_JTAG_SEL : out std_logic;
Ext_JTAG_CAPTURE : out std_logic;
Ext_JTAG_SHIFT : out std_logic;
Ext_JTAG_UPDATE : out std_logic;
Ext_JTAG_TDI : out std_logic;
Ext_JTAG_TDO : in std_logic
);
end component;
component system_proc_sys_reset_0_wrapper is
port (
Slowest_sync_clk : in std_logic;
Ext_Reset_In : in std_logic;
Aux_Reset_In : in std_logic;
MB_Debug_Sys_Rst : in std_logic;
Core_Reset_Req_0 : in std_logic;
Chip_Reset_Req_0 : in std_logic;
System_Reset_Req_0 : in std_logic;
Core_Reset_Req_1 : in std_logic;
Chip_Reset_Req_1 : in std_logic;
System_Reset_Req_1 : in std_logic;
Dcm_locked : in std_logic;
RstcPPCresetcore_0 : out std_logic;
RstcPPCresetchip_0 : out std_logic;
RstcPPCresetsys_0 : out std_logic;
RstcPPCresetcore_1 : out std_logic;
RstcPPCresetchip_1 : out std_logic;
RstcPPCresetsys_1 : out std_logic;
MB_Reset : out std_logic;
Bus_Struct_Reset : out std_logic_vector(0 to 0);
Peripheral_Reset : out std_logic_vector(0 to 0);
Interconnect_aresetn : out std_logic_vector(0 to 0);
Peripheral_aresetn : out std_logic_vector(0 to 0)
);
end component;
component system_nfa_accept_samples_generic_hw_top_0_wrapper is
port (
aclk : in std_logic;
aresetn : in std_logic;
indices_MPLB_Clk : in std_logic;
indices_MPLB_Rst : in std_logic;
indices_M_request : out std_logic;
indices_M_priority : out std_logic_vector(0 to 1);
indices_M_busLock : out std_logic;
indices_M_RNW : out std_logic;
indices_M_BE : out std_logic_vector(0 to 7);
indices_M_MSize : out std_logic_vector(0 to 1);
indices_M_size : out std_logic_vector(0 to 3);
indices_M_type : out std_logic_vector(0 to 2);
indices_M_TAttribute : out std_logic_vector(0 to 15);
indices_M_lockErr : out std_logic;
indices_M_abort : out std_logic;
indices_M_UABus : out std_logic_vector(0 to 31);
indices_M_ABus : out std_logic_vector(0 to 31);
indices_M_wrDBus : out std_logic_vector(0 to 63);
indices_M_wrBurst : out std_logic;
indices_M_rdBurst : out std_logic;
indices_PLB_MAddrAck : in std_logic;
indices_PLB_MSSize : in std_logic_vector(0 to 1);
indices_PLB_MRearbitrate : in std_logic;
indices_PLB_MTimeout : in std_logic;
indices_PLB_MBusy : in std_logic;
indices_PLB_MRdErr : in std_logic;
indices_PLB_MWrErr : in std_logic;
indices_PLB_MIRQ : in std_logic;
indices_PLB_MRdDBus : in std_logic_vector(0 to 63);
indices_PLB_MRdWdAddr : in std_logic_vector(0 to 3);
indices_PLB_MRdDAck : in std_logic;
indices_PLB_MRdBTerm : in std_logic;
indices_PLB_MWrDAck : in std_logic;
indices_PLB_MWrBTerm : in std_logic;
nfa_finals_buckets_MPLB_Clk : in std_logic;
nfa_finals_buckets_MPLB_Rst : in std_logic;
nfa_finals_buckets_M_request : out std_logic;
nfa_finals_buckets_M_priority : out std_logic_vector(0 to 1);
nfa_finals_buckets_M_busLock : out std_logic;
nfa_finals_buckets_M_RNW : out std_logic;
nfa_finals_buckets_M_BE : out std_logic_vector(0 to 7);
nfa_finals_buckets_M_MSize : out std_logic_vector(0 to 1);
nfa_finals_buckets_M_size : out std_logic_vector(0 to 3);
nfa_finals_buckets_M_type : out std_logic_vector(0 to 2);
nfa_finals_buckets_M_TAttribute : out std_logic_vector(0 to 15);
nfa_finals_buckets_M_lockErr : out std_logic;
nfa_finals_buckets_M_abort : out std_logic;
nfa_finals_buckets_M_UABus : out std_logic_vector(0 to 31);
nfa_finals_buckets_M_ABus : out std_logic_vector(0 to 31);
nfa_finals_buckets_M_wrDBus : out std_logic_vector(0 to 63);
nfa_finals_buckets_M_wrBurst : out std_logic;
nfa_finals_buckets_M_rdBurst : out std_logic;
nfa_finals_buckets_PLB_MAddrAck : in std_logic;
nfa_finals_buckets_PLB_MSSize : in std_logic_vector(0 to 1);
nfa_finals_buckets_PLB_MRearbitrate : in std_logic;
nfa_finals_buckets_PLB_MTimeout : in std_logic;
nfa_finals_buckets_PLB_MBusy : in std_logic;
nfa_finals_buckets_PLB_MRdErr : in std_logic;
nfa_finals_buckets_PLB_MWrErr : in std_logic;
nfa_finals_buckets_PLB_MIRQ : in std_logic;
nfa_finals_buckets_PLB_MRdDBus : in std_logic_vector(0 to 63);
nfa_finals_buckets_PLB_MRdWdAddr : in std_logic_vector(0 to 3);
nfa_finals_buckets_PLB_MRdDAck : in std_logic;
nfa_finals_buckets_PLB_MRdBTerm : in std_logic;
nfa_finals_buckets_PLB_MWrDAck : in std_logic;
nfa_finals_buckets_PLB_MWrBTerm : in std_logic;
nfa_forward_buckets_MPLB_Clk : in std_logic;
nfa_forward_buckets_MPLB_Rst : in std_logic;
nfa_forward_buckets_M_request : out std_logic;
nfa_forward_buckets_M_priority : out std_logic_vector(0 to 1);
nfa_forward_buckets_M_busLock : out std_logic;
nfa_forward_buckets_M_RNW : out std_logic;
nfa_forward_buckets_M_BE : out std_logic_vector(0 to 7);
nfa_forward_buckets_M_MSize : out std_logic_vector(0 to 1);
nfa_forward_buckets_M_size : out std_logic_vector(0 to 3);
nfa_forward_buckets_M_type : out std_logic_vector(0 to 2);
nfa_forward_buckets_M_TAttribute : out std_logic_vector(0 to 15);
nfa_forward_buckets_M_lockErr : out std_logic;
nfa_forward_buckets_M_abort : out std_logic;
nfa_forward_buckets_M_UABus : out std_logic_vector(0 to 31);
nfa_forward_buckets_M_ABus : out std_logic_vector(0 to 31);
nfa_forward_buckets_M_wrDBus : out std_logic_vector(0 to 63);
nfa_forward_buckets_M_wrBurst : out std_logic;
nfa_forward_buckets_M_rdBurst : out std_logic;
nfa_forward_buckets_PLB_MAddrAck : in std_logic;
nfa_forward_buckets_PLB_MSSize : in std_logic_vector(0 to 1);
nfa_forward_buckets_PLB_MRearbitrate : in std_logic;
nfa_forward_buckets_PLB_MTimeout : in std_logic;
nfa_forward_buckets_PLB_MBusy : in std_logic;
nfa_forward_buckets_PLB_MRdErr : in std_logic;
nfa_forward_buckets_PLB_MWrErr : in std_logic;
nfa_forward_buckets_PLB_MIRQ : in std_logic;
nfa_forward_buckets_PLB_MRdDBus : in std_logic_vector(0 to 63);
nfa_forward_buckets_PLB_MRdWdAddr : in std_logic_vector(0 to 3);
nfa_forward_buckets_PLB_MRdDAck : in std_logic;
nfa_forward_buckets_PLB_MRdBTerm : in std_logic;
nfa_forward_buckets_PLB_MWrDAck : in std_logic;
nfa_forward_buckets_PLB_MWrBTerm : in std_logic;
nfa_initials_buckets_MPLB_Clk : in std_logic;
nfa_initials_buckets_MPLB_Rst : in std_logic;
nfa_initials_buckets_M_request : out std_logic;
nfa_initials_buckets_M_priority : out std_logic_vector(0 to 1);
nfa_initials_buckets_M_busLock : out std_logic;
nfa_initials_buckets_M_RNW : out std_logic;
nfa_initials_buckets_M_BE : out std_logic_vector(0 to 7);
nfa_initials_buckets_M_MSize : out std_logic_vector(0 to 1);
nfa_initials_buckets_M_size : out std_logic_vector(0 to 3);
nfa_initials_buckets_M_type : out std_logic_vector(0 to 2);
nfa_initials_buckets_M_TAttribute : out std_logic_vector(0 to 15);
nfa_initials_buckets_M_lockErr : out std_logic;
nfa_initials_buckets_M_abort : out std_logic;
nfa_initials_buckets_M_UABus : out std_logic_vector(0 to 31);
nfa_initials_buckets_M_ABus : out std_logic_vector(0 to 31);
nfa_initials_buckets_M_wrDBus : out std_logic_vector(0 to 63);
nfa_initials_buckets_M_wrBurst : out std_logic;
nfa_initials_buckets_M_rdBurst : out std_logic;
nfa_initials_buckets_PLB_MAddrAck : in std_logic;
nfa_initials_buckets_PLB_MSSize : in std_logic_vector(0 to 1);
nfa_initials_buckets_PLB_MRearbitrate : in std_logic;
nfa_initials_buckets_PLB_MTimeout : in std_logic;
nfa_initials_buckets_PLB_MBusy : in std_logic;
nfa_initials_buckets_PLB_MRdErr : in std_logic;
nfa_initials_buckets_PLB_MWrErr : in std_logic;
nfa_initials_buckets_PLB_MIRQ : in std_logic;
nfa_initials_buckets_PLB_MRdDBus : in std_logic_vector(0 to 63);
nfa_initials_buckets_PLB_MRdWdAddr : in std_logic_vector(0 to 3);
nfa_initials_buckets_PLB_MRdDAck : in std_logic;
nfa_initials_buckets_PLB_MRdBTerm : in std_logic;
nfa_initials_buckets_PLB_MWrDAck : in std_logic;
nfa_initials_buckets_PLB_MWrBTerm : in std_logic;
sample_buffer_MPLB_Clk : in std_logic;
sample_buffer_MPLB_Rst : in std_logic;
sample_buffer_M_request : out std_logic;
sample_buffer_M_priority : out std_logic_vector(0 to 1);
sample_buffer_M_busLock : out std_logic;
sample_buffer_M_RNW : out std_logic;
sample_buffer_M_BE : out std_logic_vector(0 to 7);
sample_buffer_M_MSize : out std_logic_vector(0 to 1);
sample_buffer_M_size : out std_logic_vector(0 to 3);
sample_buffer_M_type : out std_logic_vector(0 to 2);
sample_buffer_M_TAttribute : out std_logic_vector(0 to 15);
sample_buffer_M_lockErr : out std_logic;
sample_buffer_M_abort : out std_logic;
sample_buffer_M_UABus : out std_logic_vector(0 to 31);
sample_buffer_M_ABus : out std_logic_vector(0 to 31);
sample_buffer_M_wrDBus : out std_logic_vector(0 to 63);
sample_buffer_M_wrBurst : out std_logic;
sample_buffer_M_rdBurst : out std_logic;
sample_buffer_PLB_MAddrAck : in std_logic;
sample_buffer_PLB_MSSize : in std_logic_vector(0 to 1);
sample_buffer_PLB_MRearbitrate : in std_logic;
sample_buffer_PLB_MTimeout : in std_logic;
sample_buffer_PLB_MBusy : in std_logic;
sample_buffer_PLB_MRdErr : in std_logic;
sample_buffer_PLB_MWrErr : in std_logic;
sample_buffer_PLB_MIRQ : in std_logic;
sample_buffer_PLB_MRdDBus : in std_logic_vector(0 to 63);
sample_buffer_PLB_MRdWdAddr : in std_logic_vector(0 to 3);
sample_buffer_PLB_MRdDAck : in std_logic;
sample_buffer_PLB_MRdBTerm : in std_logic;
sample_buffer_PLB_MWrDAck : in std_logic;
sample_buffer_PLB_MWrBTerm : in std_logic;
splb_slv0_SPLB_Clk : in std_logic;
splb_slv0_SPLB_Rst : in std_logic;
splb_slv0_PLB_ABus : in std_logic_vector(0 to 31);
splb_slv0_PLB_UABus : in std_logic_vector(0 to 31);
splb_slv0_PLB_PAValid : in std_logic;
splb_slv0_PLB_SAValid : in std_logic;
splb_slv0_PLB_rdPrim : in std_logic;
splb_slv0_PLB_wrPrim : in std_logic;
splb_slv0_PLB_masterID : in std_logic_vector(0 to 2);
splb_slv0_PLB_abort : in std_logic;
splb_slv0_PLB_busLock : in std_logic;
splb_slv0_PLB_RNW : in std_logic;
splb_slv0_PLB_BE : in std_logic_vector(0 to 7);
splb_slv0_PLB_MSize : in std_logic_vector(0 to 1);
splb_slv0_PLB_size : in std_logic_vector(0 to 3);
splb_slv0_PLB_type : in std_logic_vector(0 to 2);
splb_slv0_PLB_lockErr : in std_logic;
splb_slv0_PLB_wrDBus : in std_logic_vector(0 to 63);
splb_slv0_PLB_wrBurst : in std_logic;
splb_slv0_PLB_rdBurst : in std_logic;
splb_slv0_PLB_wrPendReq : in std_logic;
splb_slv0_PLB_rdPendReq : in std_logic;
splb_slv0_PLB_wrPendPri : in std_logic_vector(0 to 1);
splb_slv0_PLB_rdPendPri : in std_logic_vector(0 to 1);
splb_slv0_PLB_reqPri : in std_logic_vector(0 to 1);
splb_slv0_PLB_TAttribute : in std_logic_vector(0 to 15);
splb_slv0_Sl_addrAck : out std_logic;
splb_slv0_Sl_SSize : out std_logic_vector(0 to 1);
splb_slv0_Sl_wait : out std_logic;
splb_slv0_Sl_rearbitrate : out std_logic;
splb_slv0_Sl_wrDAck : out std_logic;
splb_slv0_Sl_wrComp : out std_logic;
splb_slv0_Sl_wrBTerm : out std_logic;
splb_slv0_Sl_rdDBus : out std_logic_vector(0 to 63);
splb_slv0_Sl_rdWdAddr : out std_logic_vector(0 to 3);
splb_slv0_Sl_rdDAck : out std_logic;
splb_slv0_Sl_rdComp : out std_logic;
splb_slv0_Sl_rdBTerm : out std_logic;
splb_slv0_Sl_MBusy : out std_logic_vector(0 to 6);
splb_slv0_Sl_MWrErr : out std_logic_vector(0 to 6);
splb_slv0_Sl_MRdErr : out std_logic_vector(0 to 6);
splb_slv0_Sl_MIRQ : out std_logic_vector(0 to 6)
);
end component;
-- Internal signals
signal CLK_S : std_logic;
signal Dcm_all_locked : std_logic;
signal Debug_SYS_Rst : std_logic;
signal Ext_BRK : std_logic;
signal Ext_NM_BRK : std_logic;
signal clk_50_0000MHz : std_logic;
signal dlmb_LMB_ABus : std_logic_vector(0 to 31);
signal dlmb_LMB_AddrStrobe : std_logic;
signal dlmb_LMB_BE : std_logic_vector(0 to 3);
signal dlmb_LMB_CE : std_logic;
signal dlmb_LMB_ReadDBus : std_logic_vector(0 to 31);
signal dlmb_LMB_ReadStrobe : std_logic;
signal dlmb_LMB_Ready : std_logic;
signal dlmb_LMB_Rst : std_logic;
signal dlmb_LMB_UE : std_logic;
signal dlmb_LMB_Wait : std_logic;
signal dlmb_LMB_WriteDBus : std_logic_vector(0 to 31);
signal dlmb_LMB_WriteStrobe : std_logic;
signal dlmb_M_ABus : std_logic_vector(0 to 31);
signal dlmb_M_AddrStrobe : std_logic;
signal dlmb_M_BE : std_logic_vector(0 to 3);
signal dlmb_M_DBus : std_logic_vector(0 to 31);
signal dlmb_M_ReadStrobe : std_logic;
signal dlmb_M_WriteStrobe : std_logic;
signal dlmb_Sl_CE : std_logic_vector(0 to 0);
signal dlmb_Sl_DBus : std_logic_vector(0 to 31);
signal dlmb_Sl_Ready : std_logic_vector(0 to 0);
signal dlmb_Sl_UE : std_logic_vector(0 to 0);
signal dlmb_Sl_Wait : std_logic_vector(0 to 0);
signal dlmb_port_BRAM_Addr : std_logic_vector(0 to 31);
signal dlmb_port_BRAM_Clk : std_logic;
signal dlmb_port_BRAM_Din : std_logic_vector(0 to 31);
signal dlmb_port_BRAM_Dout : std_logic_vector(0 to 31);
signal dlmb_port_BRAM_EN : std_logic;
signal dlmb_port_BRAM_Rst : std_logic;
signal dlmb_port_BRAM_WEN : std_logic_vector(0 to 3);
signal ilmb_LMB_ABus : std_logic_vector(0 to 31);
signal ilmb_LMB_AddrStrobe : std_logic;
signal ilmb_LMB_BE : std_logic_vector(0 to 3);
signal ilmb_LMB_CE : std_logic;
signal ilmb_LMB_ReadDBus : std_logic_vector(0 to 31);
signal ilmb_LMB_ReadStrobe : std_logic;
signal ilmb_LMB_Ready : std_logic;
signal ilmb_LMB_Rst : std_logic;
signal ilmb_LMB_UE : std_logic;
signal ilmb_LMB_Wait : std_logic;
signal ilmb_LMB_WriteDBus : std_logic_vector(0 to 31);
signal ilmb_LMB_WriteStrobe : std_logic;
signal ilmb_M_ABus : std_logic_vector(0 to 31);
signal ilmb_M_AddrStrobe : std_logic;
signal ilmb_M_ReadStrobe : std_logic;
signal ilmb_Sl_CE : std_logic_vector(0 to 0);
signal ilmb_Sl_DBus : std_logic_vector(0 to 31);
signal ilmb_Sl_Ready : std_logic_vector(0 to 0);
signal ilmb_Sl_UE : std_logic_vector(0 to 0);
signal ilmb_Sl_Wait : std_logic_vector(0 to 0);
signal ilmb_port_BRAM_Addr : std_logic_vector(0 to 31);
signal ilmb_port_BRAM_Clk : std_logic;
signal ilmb_port_BRAM_Din : std_logic_vector(0 to 31);
signal ilmb_port_BRAM_Dout : std_logic_vector(0 to 31);
signal ilmb_port_BRAM_EN : std_logic;
signal ilmb_port_BRAM_Rst : std_logic;
signal ilmb_port_BRAM_WEN : std_logic_vector(0 to 3);
signal mb_plb_MPLB_Rst : std_logic_vector(0 to 6);
signal mb_plb_M_ABort : std_logic_vector(0 to 6);
signal mb_plb_M_ABus : std_logic_vector(0 to 223);
signal mb_plb_M_BE : std_logic_vector(0 to 55);
signal mb_plb_M_MSize : std_logic_vector(0 to 13);
signal mb_plb_M_RNW : std_logic_vector(0 to 6);
signal mb_plb_M_TAttribute : std_logic_vector(0 to 111);
signal mb_plb_M_UABus : std_logic_vector(0 to 223);
signal mb_plb_M_busLock : std_logic_vector(0 to 6);
signal mb_plb_M_lockErr : std_logic_vector(0 to 6);
signal mb_plb_M_priority : std_logic_vector(0 to 13);
signal mb_plb_M_rdBurst : std_logic_vector(0 to 6);
signal mb_plb_M_request : std_logic_vector(0 to 6);
signal mb_plb_M_size : std_logic_vector(0 to 27);
signal mb_plb_M_type : std_logic_vector(0 to 20);
signal mb_plb_M_wrBurst : std_logic_vector(0 to 6);
signal mb_plb_M_wrDBus : std_logic_vector(0 to 447);
signal mb_plb_PLB_ABus : std_logic_vector(0 to 31);
signal mb_plb_PLB_BE : std_logic_vector(0 to 7);
signal mb_plb_PLB_MAddrAck : std_logic_vector(0 to 6);
signal mb_plb_PLB_MBusy : std_logic_vector(0 to 6);
signal mb_plb_PLB_MIRQ : std_logic_vector(0 to 6);
signal mb_plb_PLB_MRdBTerm : std_logic_vector(0 to 6);
signal mb_plb_PLB_MRdDAck : std_logic_vector(0 to 6);
signal mb_plb_PLB_MRdDBus : std_logic_vector(0 to 447);
signal mb_plb_PLB_MRdErr : std_logic_vector(0 to 6);
signal mb_plb_PLB_MRdWdAddr : std_logic_vector(0 to 27);
signal mb_plb_PLB_MRearbitrate : std_logic_vector(0 to 6);
signal mb_plb_PLB_MSSize : std_logic_vector(0 to 13);
signal mb_plb_PLB_MSize : std_logic_vector(0 to 1);
signal mb_plb_PLB_MTimeout : std_logic_vector(0 to 6);
signal mb_plb_PLB_MWrBTerm : std_logic_vector(0 to 6);
signal mb_plb_PLB_MWrDAck : std_logic_vector(0 to 6);
signal mb_plb_PLB_MWrErr : std_logic_vector(0 to 6);
signal mb_plb_PLB_PAValid : std_logic;
signal mb_plb_PLB_RNW : std_logic;
signal mb_plb_PLB_SAValid : std_logic;
signal mb_plb_PLB_TAttribute : std_logic_vector(0 to 15);
signal mb_plb_PLB_UABus : std_logic_vector(0 to 31);
signal mb_plb_PLB_abort : std_logic;
signal mb_plb_PLB_busLock : std_logic;
signal mb_plb_PLB_lockErr : std_logic;
signal mb_plb_PLB_masterID : std_logic_vector(0 to 2);
signal mb_plb_PLB_rdBurst : std_logic;
signal mb_plb_PLB_rdPendPri : std_logic_vector(0 to 1);
signal mb_plb_PLB_rdPendReq : std_logic;
signal mb_plb_PLB_rdPrim : std_logic_vector(0 to 1);
signal mb_plb_PLB_reqPri : std_logic_vector(0 to 1);
signal mb_plb_PLB_size : std_logic_vector(0 to 3);
signal mb_plb_PLB_type : std_logic_vector(0 to 2);
signal mb_plb_PLB_wrBurst : std_logic;
signal mb_plb_PLB_wrDBus : std_logic_vector(0 to 63);
signal mb_plb_PLB_wrPendPri : std_logic_vector(0 to 1);
signal mb_plb_PLB_wrPendReq : std_logic;
signal mb_plb_PLB_wrPrim : std_logic_vector(0 to 1);
signal mb_plb_SPLB_Rst : std_logic_vector(0 to 1);
signal mb_plb_Sl_MBusy : std_logic_vector(0 to 13);
signal mb_plb_Sl_MIRQ : std_logic_vector(0 to 13);
signal mb_plb_Sl_MRdErr : std_logic_vector(0 to 13);
signal mb_plb_Sl_MWrErr : std_logic_vector(0 to 13);
signal mb_plb_Sl_SSize : std_logic_vector(0 to 3);
signal mb_plb_Sl_addrAck : std_logic_vector(0 to 1);
signal mb_plb_Sl_rdBTerm : std_logic_vector(0 to 1);
signal mb_plb_Sl_rdComp : std_logic_vector(0 to 1);
signal mb_plb_Sl_rdDAck : std_logic_vector(0 to 1);
signal mb_plb_Sl_rdDBus : std_logic_vector(0 to 127);
signal mb_plb_Sl_rdWdAddr : std_logic_vector(0 to 7);
signal mb_plb_Sl_rearbitrate : std_logic_vector(0 to 1);
signal mb_plb_Sl_wait : std_logic_vector(0 to 1);
signal mb_plb_Sl_wrBTerm : std_logic_vector(0 to 1);
signal mb_plb_Sl_wrComp : std_logic_vector(0 to 1);
signal mb_plb_Sl_wrDAck : std_logic_vector(0 to 1);
signal mb_reset : std_logic;
signal microblaze_0_mdm_bus_Dbg_Capture : std_logic;
signal microblaze_0_mdm_bus_Dbg_Clk : std_logic;
signal microblaze_0_mdm_bus_Dbg_Reg_En : std_logic_vector(0 to 7);
signal microblaze_0_mdm_bus_Dbg_Shift : std_logic;
signal microblaze_0_mdm_bus_Dbg_TDI : std_logic;
signal microblaze_0_mdm_bus_Dbg_TDO : std_logic;
signal microblaze_0_mdm_bus_Dbg_Update : std_logic;
signal microblaze_0_mdm_bus_Debug_Rst : std_logic;
signal net_gnd0 : std_logic;
signal net_gnd1 : std_logic_vector(0 downto 0);
signal net_gnd2 : std_logic_vector(0 to 1);
signal net_gnd3 : std_logic_vector(2 downto 0);
signal net_gnd4 : std_logic_vector(0 to 3);
signal net_gnd10 : std_logic_vector(0 to 9);
signal net_gnd16 : std_logic_vector(0 to 15);
signal net_gnd32 : std_logic_vector(0 to 31);
signal net_gnd4096 : std_logic_vector(0 to 4095);
signal net_vcc0 : std_logic;
signal sys_bus_reset : std_logic_vector(0 to 0);
signal sys_periph_reset : std_logic_vector(0 to 0);
signal sys_rst_s : std_logic;
attribute BOX_TYPE : STRING;
attribute BOX_TYPE of system_microblaze_0_wrapper : component is "user_black_box";
attribute BOX_TYPE of system_mb_plb_wrapper : component is "user_black_box";
attribute BOX_TYPE of system_ilmb_wrapper : component is "user_black_box";
attribute BOX_TYPE of system_dlmb_wrapper : component is "user_black_box";
attribute BOX_TYPE of system_dlmb_cntlr_wrapper : component is "user_black_box";
attribute BOX_TYPE of system_ilmb_cntlr_wrapper : component is "user_black_box";
attribute BOX_TYPE of system_lmb_bram_wrapper : component is "user_black_box";
attribute BOX_TYPE of system_clock_generator_0_wrapper : component is "user_black_box";
attribute BOX_TYPE of system_mdm_0_wrapper : component is "user_black_box";
attribute BOX_TYPE of system_proc_sys_reset_0_wrapper : component is "user_black_box";
attribute BOX_TYPE of system_nfa_accept_samples_generic_hw_top_0_wrapper : component is "user_black_box";
begin
-- Internal assignments
CLK_S <= fpga_0_clk_1_sys_clk_pin;
sys_rst_s <= fpga_0_rst_1_sys_rst_pin;
net_gnd0 <= '0';
net_gnd1(0 downto 0) <= B"0";
net_gnd10(0 to 9) <= B"0000000000";
net_gnd16(0 to 15) <= B"0000000000000000";
net_gnd2(0 to 1) <= B"00";
net_gnd3(2 downto 0) <= B"000";
net_gnd32(0 to 31) <= B"00000000000000000000000000000000";
net_gnd4(0 to 3) <= B"0000";
net_gnd4096(0 to 4095) <= X"0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
net_vcc0 <= '1';
microblaze_0 : system_microblaze_0_wrapper
port map (
CLK => clk_50_0000MHz,
RESET => dlmb_LMB_Rst,
MB_RESET => mb_reset,
INTERRUPT => net_gnd0,
INTERRUPT_ADDRESS => net_gnd32,
INTERRUPT_ACK => open,
EXT_BRK => Ext_BRK,
EXT_NM_BRK => Ext_NM_BRK,
DBG_STOP => net_gnd0,
MB_Halted => open,
MB_Error => open,
WAKEUP => net_gnd2,
SLEEP => open,
DBG_WAKEUP => open,
LOCKSTEP_MASTER_OUT => open,
LOCKSTEP_SLAVE_IN => net_gnd4096,
LOCKSTEP_OUT => open,
INSTR => ilmb_LMB_ReadDBus,
IREADY => ilmb_LMB_Ready,
IWAIT => ilmb_LMB_Wait,
ICE => ilmb_LMB_CE,
IUE => ilmb_LMB_UE,
INSTR_ADDR => ilmb_M_ABus,
IFETCH => ilmb_M_ReadStrobe,
I_AS => ilmb_M_AddrStrobe,
IPLB_M_ABort => mb_plb_M_ABort(1),
IPLB_M_ABus => mb_plb_M_ABus(32 to 63),
IPLB_M_UABus => mb_plb_M_UABus(32 to 63),
IPLB_M_BE => mb_plb_M_BE(8 to 15),
IPLB_M_busLock => mb_plb_M_busLock(1),
IPLB_M_lockErr => mb_plb_M_lockErr(1),
IPLB_M_MSize => mb_plb_M_MSize(2 to 3),
IPLB_M_priority => mb_plb_M_priority(2 to 3),
IPLB_M_rdBurst => mb_plb_M_rdBurst(1),
IPLB_M_request => mb_plb_M_request(1),
IPLB_M_RNW => mb_plb_M_RNW(1),
IPLB_M_size => mb_plb_M_size(4 to 7),
IPLB_M_TAttribute => mb_plb_M_TAttribute(16 to 31),
IPLB_M_type => mb_plb_M_type(3 to 5),
IPLB_M_wrBurst => mb_plb_M_wrBurst(1),
IPLB_M_wrDBus => mb_plb_M_wrDBus(64 to 127),
IPLB_MBusy => mb_plb_PLB_MBusy(1),
IPLB_MRdErr => mb_plb_PLB_MRdErr(1),
IPLB_MWrErr => mb_plb_PLB_MWrErr(1),
IPLB_MIRQ => mb_plb_PLB_MIRQ(1),
IPLB_MWrBTerm => mb_plb_PLB_MWrBTerm(1),
IPLB_MWrDAck => mb_plb_PLB_MWrDAck(1),
IPLB_MAddrAck => mb_plb_PLB_MAddrAck(1),
IPLB_MRdBTerm => mb_plb_PLB_MRdBTerm(1),
IPLB_MRdDAck => mb_plb_PLB_MRdDAck(1),
IPLB_MRdDBus => mb_plb_PLB_MRdDBus(64 to 127),
IPLB_MRdWdAddr => mb_plb_PLB_MRdWdAddr(4 to 7),
IPLB_MRearbitrate => mb_plb_PLB_MRearbitrate(1),
IPLB_MSSize => mb_plb_PLB_MSSize(2 to 3),
IPLB_MTimeout => mb_plb_PLB_MTimeout(1),
DATA_READ => dlmb_LMB_ReadDBus,
DREADY => dlmb_LMB_Ready,
DWAIT => dlmb_LMB_Wait,
DCE => dlmb_LMB_CE,
DUE => dlmb_LMB_UE,
DATA_WRITE => dlmb_M_DBus,
DATA_ADDR => dlmb_M_ABus,
D_AS => dlmb_M_AddrStrobe,
READ_STROBE => dlmb_M_ReadStrobe,
WRITE_STROBE => dlmb_M_WriteStrobe,
BYTE_ENABLE => dlmb_M_BE,
DPLB_M_ABort => mb_plb_M_ABort(0),
DPLB_M_ABus => mb_plb_M_ABus(0 to 31),
DPLB_M_UABus => mb_plb_M_UABus(0 to 31),
DPLB_M_BE => mb_plb_M_BE(0 to 7),
DPLB_M_busLock => mb_plb_M_busLock(0),
DPLB_M_lockErr => mb_plb_M_lockErr(0),
DPLB_M_MSize => mb_plb_M_MSize(0 to 1),
DPLB_M_priority => mb_plb_M_priority(0 to 1),
DPLB_M_rdBurst => mb_plb_M_rdBurst(0),
DPLB_M_request => mb_plb_M_request(0),
DPLB_M_RNW => mb_plb_M_RNW(0),
DPLB_M_size => mb_plb_M_size(0 to 3),
DPLB_M_TAttribute => mb_plb_M_TAttribute(0 to 15),
DPLB_M_type => mb_plb_M_type(0 to 2),
DPLB_M_wrBurst => mb_plb_M_wrBurst(0),
DPLB_M_wrDBus => mb_plb_M_wrDBus(0 to 63),
DPLB_MBusy => mb_plb_PLB_MBusy(0),
DPLB_MRdErr => mb_plb_PLB_MRdErr(0),
DPLB_MWrErr => mb_plb_PLB_MWrErr(0),
DPLB_MIRQ => mb_plb_PLB_MIRQ(0),
DPLB_MWrBTerm => mb_plb_PLB_MWrBTerm(0),
DPLB_MWrDAck => mb_plb_PLB_MWrDAck(0),
DPLB_MAddrAck => mb_plb_PLB_MAddrAck(0),
DPLB_MRdBTerm => mb_plb_PLB_MRdBTerm(0),
DPLB_MRdDAck => mb_plb_PLB_MRdDAck(0),
DPLB_MRdDBus => mb_plb_PLB_MRdDBus(0 to 63),
DPLB_MRdWdAddr => mb_plb_PLB_MRdWdAddr(0 to 3),
DPLB_MRearbitrate => mb_plb_PLB_MRearbitrate(0),
DPLB_MSSize => mb_plb_PLB_MSSize(0 to 1),
DPLB_MTimeout => mb_plb_PLB_MTimeout(0),
M_AXI_IP_AWID => open,
M_AXI_IP_AWADDR => open,
M_AXI_IP_AWLEN => open,
M_AXI_IP_AWSIZE => open,
M_AXI_IP_AWBURST => open,
M_AXI_IP_AWLOCK => open,
M_AXI_IP_AWCACHE => open,
M_AXI_IP_AWPROT => open,
M_AXI_IP_AWQOS => open,
M_AXI_IP_AWVALID => open,
M_AXI_IP_AWREADY => net_gnd0,
M_AXI_IP_WDATA => open,
M_AXI_IP_WSTRB => open,
M_AXI_IP_WLAST => open,
M_AXI_IP_WVALID => open,
M_AXI_IP_WREADY => net_gnd0,
M_AXI_IP_BID => net_gnd1(0 downto 0),
M_AXI_IP_BRESP => net_gnd2(0 to 1),
M_AXI_IP_BVALID => net_gnd0,
M_AXI_IP_BREADY => open,
M_AXI_IP_ARID => open,
M_AXI_IP_ARADDR => open,
M_AXI_IP_ARLEN => open,
M_AXI_IP_ARSIZE => open,
M_AXI_IP_ARBURST => open,
M_AXI_IP_ARLOCK => open,
M_AXI_IP_ARCACHE => open,
M_AXI_IP_ARPROT => open,
M_AXI_IP_ARQOS => open,
M_AXI_IP_ARVALID => open,
M_AXI_IP_ARREADY => net_gnd0,
M_AXI_IP_RID => net_gnd1(0 downto 0),
M_AXI_IP_RDATA => net_gnd32(0 to 31),
M_AXI_IP_RRESP => net_gnd2(0 to 1),
M_AXI_IP_RLAST => net_gnd0,
M_AXI_IP_RVALID => net_gnd0,
M_AXI_IP_RREADY => open,
M_AXI_DP_AWID => open,
M_AXI_DP_AWADDR => open,
M_AXI_DP_AWLEN => open,
M_AXI_DP_AWSIZE => open,
M_AXI_DP_AWBURST => open,
M_AXI_DP_AWLOCK => open,
M_AXI_DP_AWCACHE => open,
M_AXI_DP_AWPROT => open,
M_AXI_DP_AWQOS => open,
M_AXI_DP_AWVALID => open,
M_AXI_DP_AWREADY => net_gnd0,
M_AXI_DP_WDATA => open,
M_AXI_DP_WSTRB => open,
M_AXI_DP_WLAST => open,
M_AXI_DP_WVALID => open,
M_AXI_DP_WREADY => net_gnd0,
M_AXI_DP_BID => net_gnd1(0 downto 0),
M_AXI_DP_BRESP => net_gnd2(0 to 1),
M_AXI_DP_BVALID => net_gnd0,
M_AXI_DP_BREADY => open,
M_AXI_DP_ARID => open,
M_AXI_DP_ARADDR => open,
M_AXI_DP_ARLEN => open,
M_AXI_DP_ARSIZE => open,
M_AXI_DP_ARBURST => open,
M_AXI_DP_ARLOCK => open,
M_AXI_DP_ARCACHE => open,
M_AXI_DP_ARPROT => open,
M_AXI_DP_ARQOS => open,
M_AXI_DP_ARVALID => open,
M_AXI_DP_ARREADY => net_gnd0,
M_AXI_DP_RID => net_gnd1(0 downto 0),
M_AXI_DP_RDATA => net_gnd32(0 to 31),
M_AXI_DP_RRESP => net_gnd2(0 to 1),
M_AXI_DP_RLAST => net_gnd0,
M_AXI_DP_RVALID => net_gnd0,
M_AXI_DP_RREADY => open,
M_AXI_IC_AWID => open,
M_AXI_IC_AWADDR => open,
M_AXI_IC_AWLEN => open,
M_AXI_IC_AWSIZE => open,
M_AXI_IC_AWBURST => open,
M_AXI_IC_AWLOCK => open,
M_AXI_IC_AWCACHE => open,
M_AXI_IC_AWPROT => open,
M_AXI_IC_AWQOS => open,
M_AXI_IC_AWVALID => open,
M_AXI_IC_AWREADY => net_gnd0,
M_AXI_IC_AWUSER => open,
M_AXI_IC_AWDOMAIN => open,
M_AXI_IC_AWSNOOP => open,
M_AXI_IC_AWBAR => open,
M_AXI_IC_WDATA => open,
M_AXI_IC_WSTRB => open,
M_AXI_IC_WLAST => open,
M_AXI_IC_WVALID => open,
M_AXI_IC_WREADY => net_gnd0,
M_AXI_IC_WUSER => open,
M_AXI_IC_BID => net_gnd1(0 downto 0),
M_AXI_IC_BRESP => net_gnd2(0 to 1),
M_AXI_IC_BVALID => net_gnd0,
M_AXI_IC_BREADY => open,
M_AXI_IC_BUSER => net_gnd1(0 downto 0),
M_AXI_IC_WACK => open,
M_AXI_IC_ARID => open,
M_AXI_IC_ARADDR => open,
M_AXI_IC_ARLEN => open,
M_AXI_IC_ARSIZE => open,
M_AXI_IC_ARBURST => open,
M_AXI_IC_ARLOCK => open,
M_AXI_IC_ARCACHE => open,
M_AXI_IC_ARPROT => open,
M_AXI_IC_ARQOS => open,
M_AXI_IC_ARVALID => open,
M_AXI_IC_ARREADY => net_gnd0,
M_AXI_IC_ARUSER => open,
M_AXI_IC_ARDOMAIN => open,
M_AXI_IC_ARSNOOP => open,
M_AXI_IC_ARBAR => open,
M_AXI_IC_RID => net_gnd1(0 downto 0),
M_AXI_IC_RDATA => net_gnd32(0 to 31),
M_AXI_IC_RRESP => net_gnd2(0 to 1),
M_AXI_IC_RLAST => net_gnd0,
M_AXI_IC_RVALID => net_gnd0,
M_AXI_IC_RREADY => open,
M_AXI_IC_RUSER => net_gnd1(0 downto 0),
M_AXI_IC_RACK => open,
M_AXI_IC_ACVALID => net_gnd0,
M_AXI_IC_ACADDR => net_gnd32(0 to 31),
M_AXI_IC_ACSNOOP => net_gnd4(0 to 3),
M_AXI_IC_ACPROT => net_gnd3,
M_AXI_IC_ACREADY => open,
M_AXI_IC_CRREADY => net_gnd0,
M_AXI_IC_CRVALID => open,
M_AXI_IC_CRRESP => open,
M_AXI_IC_CDVALID => open,
M_AXI_IC_CDREADY => net_gnd0,
M_AXI_IC_CDDATA => open,
M_AXI_IC_CDLAST => open,
M_AXI_DC_AWID => open,
M_AXI_DC_AWADDR => open,
M_AXI_DC_AWLEN => open,
M_AXI_DC_AWSIZE => open,
M_AXI_DC_AWBURST => open,
M_AXI_DC_AWLOCK => open,
M_AXI_DC_AWCACHE => open,
M_AXI_DC_AWPROT => open,
M_AXI_DC_AWQOS => open,
M_AXI_DC_AWVALID => open,
M_AXI_DC_AWREADY => net_gnd0,
M_AXI_DC_AWUSER => open,
M_AXI_DC_AWDOMAIN => open,
M_AXI_DC_AWSNOOP => open,
M_AXI_DC_AWBAR => open,
M_AXI_DC_WDATA => open,
M_AXI_DC_WSTRB => open,
M_AXI_DC_WLAST => open,
M_AXI_DC_WVALID => open,
M_AXI_DC_WREADY => net_gnd0,
M_AXI_DC_WUSER => open,
M_AXI_DC_BID => net_gnd1(0 downto 0),
M_AXI_DC_BRESP => net_gnd2(0 to 1),
M_AXI_DC_BVALID => net_gnd0,
M_AXI_DC_BREADY => open,
M_AXI_DC_BUSER => net_gnd1(0 downto 0),
M_AXI_DC_WACK => open,
M_AXI_DC_ARID => open,
M_AXI_DC_ARADDR => open,
M_AXI_DC_ARLEN => open,
M_AXI_DC_ARSIZE => open,
M_AXI_DC_ARBURST => open,
M_AXI_DC_ARLOCK => open,
M_AXI_DC_ARCACHE => open,
M_AXI_DC_ARPROT => open,
M_AXI_DC_ARQOS => open,
M_AXI_DC_ARVALID => open,
M_AXI_DC_ARREADY => net_gnd0,
M_AXI_DC_ARUSER => open,
M_AXI_DC_ARDOMAIN => open,
M_AXI_DC_ARSNOOP => open,
M_AXI_DC_ARBAR => open,
M_AXI_DC_RID => net_gnd1(0 downto 0),
M_AXI_DC_RDATA => net_gnd32(0 to 31),
M_AXI_DC_RRESP => net_gnd2(0 to 1),
M_AXI_DC_RLAST => net_gnd0,
M_AXI_DC_RVALID => net_gnd0,
M_AXI_DC_RREADY => open,
M_AXI_DC_RUSER => net_gnd1(0 downto 0),
M_AXI_DC_RACK => open,
M_AXI_DC_ACVALID => net_gnd0,
M_AXI_DC_ACADDR => net_gnd32(0 to 31),
M_AXI_DC_ACSNOOP => net_gnd4(0 to 3),
M_AXI_DC_ACPROT => net_gnd3,
M_AXI_DC_ACREADY => open,
M_AXI_DC_CRREADY => net_gnd0,
M_AXI_DC_CRVALID => open,
M_AXI_DC_CRRESP => open,
M_AXI_DC_CDVALID => open,
M_AXI_DC_CDREADY => net_gnd0,
M_AXI_DC_CDDATA => open,
M_AXI_DC_CDLAST => open,
DBG_CLK => microblaze_0_mdm_bus_Dbg_Clk,
DBG_TDI => microblaze_0_mdm_bus_Dbg_TDI,
DBG_TDO => microblaze_0_mdm_bus_Dbg_TDO,
DBG_REG_EN => microblaze_0_mdm_bus_Dbg_Reg_En,
DBG_SHIFT => microblaze_0_mdm_bus_Dbg_Shift,
DBG_CAPTURE => microblaze_0_mdm_bus_Dbg_Capture,
DBG_UPDATE => microblaze_0_mdm_bus_Dbg_Update,
DEBUG_RST => microblaze_0_mdm_bus_Debug_Rst,
Trace_Instruction => open,
Trace_Valid_Instr => open,
Trace_PC => open,
Trace_Reg_Write => open,
Trace_Reg_Addr => open,
Trace_MSR_Reg => open,
Trace_PID_Reg => open,
Trace_New_Reg_Value => open,
Trace_Exception_Taken => open,
Trace_Exception_Kind => open,
Trace_Jump_Taken => open,
Trace_Delay_Slot => open,
Trace_Data_Address => open,
Trace_Data_Access => open,
Trace_Data_Read => open,
Trace_Data_Write => open,
Trace_Data_Write_Value => open,
Trace_Data_Byte_Enable => open,
Trace_DCache_Req => open,
Trace_DCache_Hit => open,
Trace_DCache_Rdy => open,
Trace_DCache_Read => open,
Trace_ICache_Req => open,
Trace_ICache_Hit => open,
Trace_ICache_Rdy => open,
Trace_OF_PipeRun => open,
Trace_EX_PipeRun => open,
Trace_MEM_PipeRun => open,
Trace_MB_Halted => open,
Trace_Jump_Hit => open,
FSL0_S_CLK => open,
FSL0_S_READ => open,
FSL0_S_DATA => net_gnd32,
FSL0_S_CONTROL => net_gnd0,
FSL0_S_EXISTS => net_gnd0,
FSL0_M_CLK => open,
FSL0_M_WRITE => open,
FSL0_M_DATA => open,
FSL0_M_CONTROL => open,
FSL0_M_FULL => net_gnd0,
FSL1_S_CLK => open,
FSL1_S_READ => open,
FSL1_S_DATA => net_gnd32,
FSL1_S_CONTROL => net_gnd0,
FSL1_S_EXISTS => net_gnd0,
FSL1_M_CLK => open,
FSL1_M_WRITE => open,
FSL1_M_DATA => open,
FSL1_M_CONTROL => open,
FSL1_M_FULL => net_gnd0,
FSL2_S_CLK => open,
FSL2_S_READ => open,
FSL2_S_DATA => net_gnd32,
FSL2_S_CONTROL => net_gnd0,
FSL2_S_EXISTS => net_gnd0,
FSL2_M_CLK => open,
FSL2_M_WRITE => open,
FSL2_M_DATA => open,
FSL2_M_CONTROL => open,
FSL2_M_FULL => net_gnd0,
FSL3_S_CLK => open,
FSL3_S_READ => open,
FSL3_S_DATA => net_gnd32,
FSL3_S_CONTROL => net_gnd0,
FSL3_S_EXISTS => net_gnd0,
FSL3_M_CLK => open,
FSL3_M_WRITE => open,
FSL3_M_DATA => open,
FSL3_M_CONTROL => open,
FSL3_M_FULL => net_gnd0,
FSL4_S_CLK => open,
FSL4_S_READ => open,
FSL4_S_DATA => net_gnd32,
FSL4_S_CONTROL => net_gnd0,
FSL4_S_EXISTS => net_gnd0,
FSL4_M_CLK => open,
FSL4_M_WRITE => open,
FSL4_M_DATA => open,
FSL4_M_CONTROL => open,
FSL4_M_FULL => net_gnd0,
FSL5_S_CLK => open,
FSL5_S_READ => open,
FSL5_S_DATA => net_gnd32,
FSL5_S_CONTROL => net_gnd0,
FSL5_S_EXISTS => net_gnd0,
FSL5_M_CLK => open,
FSL5_M_WRITE => open,
FSL5_M_DATA => open,
FSL5_M_CONTROL => open,
FSL5_M_FULL => net_gnd0,
FSL6_S_CLK => open,
FSL6_S_READ => open,
FSL6_S_DATA => net_gnd32,
FSL6_S_CONTROL => net_gnd0,
FSL6_S_EXISTS => net_gnd0,
FSL6_M_CLK => open,
FSL6_M_WRITE => open,
FSL6_M_DATA => open,
FSL6_M_CONTROL => open,
FSL6_M_FULL => net_gnd0,
FSL7_S_CLK => open,
FSL7_S_READ => open,
FSL7_S_DATA => net_gnd32,
FSL7_S_CONTROL => net_gnd0,
FSL7_S_EXISTS => net_gnd0,
FSL7_M_CLK => open,
FSL7_M_WRITE => open,
FSL7_M_DATA => open,
FSL7_M_CONTROL => open,
FSL7_M_FULL => net_gnd0,
FSL8_S_CLK => open,
FSL8_S_READ => open,
FSL8_S_DATA => net_gnd32,
FSL8_S_CONTROL => net_gnd0,
FSL8_S_EXISTS => net_gnd0,
FSL8_M_CLK => open,
FSL8_M_WRITE => open,
FSL8_M_DATA => open,
FSL8_M_CONTROL => open,
FSL8_M_FULL => net_gnd0,
FSL9_S_CLK => open,
FSL9_S_READ => open,
FSL9_S_DATA => net_gnd32,
FSL9_S_CONTROL => net_gnd0,
FSL9_S_EXISTS => net_gnd0,
FSL9_M_CLK => open,
FSL9_M_WRITE => open,
FSL9_M_DATA => open,
FSL9_M_CONTROL => open,
FSL9_M_FULL => net_gnd0,
FSL10_S_CLK => open,
FSL10_S_READ => open,
FSL10_S_DATA => net_gnd32,
FSL10_S_CONTROL => net_gnd0,
FSL10_S_EXISTS => net_gnd0,
FSL10_M_CLK => open,
FSL10_M_WRITE => open,
FSL10_M_DATA => open,
FSL10_M_CONTROL => open,
FSL10_M_FULL => net_gnd0,
FSL11_S_CLK => open,
FSL11_S_READ => open,
FSL11_S_DATA => net_gnd32,
FSL11_S_CONTROL => net_gnd0,
FSL11_S_EXISTS => net_gnd0,
FSL11_M_CLK => open,
FSL11_M_WRITE => open,
FSL11_M_DATA => open,
FSL11_M_CONTROL => open,
FSL11_M_FULL => net_gnd0,
FSL12_S_CLK => open,
FSL12_S_READ => open,
FSL12_S_DATA => net_gnd32,
FSL12_S_CONTROL => net_gnd0,
FSL12_S_EXISTS => net_gnd0,
FSL12_M_CLK => open,
FSL12_M_WRITE => open,
FSL12_M_DATA => open,
FSL12_M_CONTROL => open,
FSL12_M_FULL => net_gnd0,
FSL13_S_CLK => open,
FSL13_S_READ => open,
FSL13_S_DATA => net_gnd32,
FSL13_S_CONTROL => net_gnd0,
FSL13_S_EXISTS => net_gnd0,
FSL13_M_CLK => open,
FSL13_M_WRITE => open,
FSL13_M_DATA => open,
FSL13_M_CONTROL => open,
FSL13_M_FULL => net_gnd0,
FSL14_S_CLK => open,
FSL14_S_READ => open,
FSL14_S_DATA => net_gnd32,
FSL14_S_CONTROL => net_gnd0,
FSL14_S_EXISTS => net_gnd0,
FSL14_M_CLK => open,
FSL14_M_WRITE => open,
FSL14_M_DATA => open,
FSL14_M_CONTROL => open,
FSL14_M_FULL => net_gnd0,
FSL15_S_CLK => open,
FSL15_S_READ => open,
FSL15_S_DATA => net_gnd32,
FSL15_S_CONTROL => net_gnd0,
FSL15_S_EXISTS => net_gnd0,
FSL15_M_CLK => open,
FSL15_M_WRITE => open,
FSL15_M_DATA => open,
FSL15_M_CONTROL => open,
FSL15_M_FULL => net_gnd0,
M0_AXIS_TLAST => open,
M0_AXIS_TDATA => open,
M0_AXIS_TVALID => open,
M0_AXIS_TREADY => net_gnd0,
S0_AXIS_TLAST => net_gnd0,
S0_AXIS_TDATA => net_gnd32(0 to 31),
S0_AXIS_TVALID => net_gnd0,
S0_AXIS_TREADY => open,
M1_AXIS_TLAST => open,
M1_AXIS_TDATA => open,
M1_AXIS_TVALID => open,
M1_AXIS_TREADY => net_gnd0,
S1_AXIS_TLAST => net_gnd0,
S1_AXIS_TDATA => net_gnd32(0 to 31),
S1_AXIS_TVALID => net_gnd0,
S1_AXIS_TREADY => open,
M2_AXIS_TLAST => open,
M2_AXIS_TDATA => open,
M2_AXIS_TVALID => open,
M2_AXIS_TREADY => net_gnd0,
S2_AXIS_TLAST => net_gnd0,
S2_AXIS_TDATA => net_gnd32(0 to 31),
S2_AXIS_TVALID => net_gnd0,
S2_AXIS_TREADY => open,
M3_AXIS_TLAST => open,
M3_AXIS_TDATA => open,
M3_AXIS_TVALID => open,
M3_AXIS_TREADY => net_gnd0,
S3_AXIS_TLAST => net_gnd0,
S3_AXIS_TDATA => net_gnd32(0 to 31),
S3_AXIS_TVALID => net_gnd0,
S3_AXIS_TREADY => open,
M4_AXIS_TLAST => open,
M4_AXIS_TDATA => open,
M4_AXIS_TVALID => open,
M4_AXIS_TREADY => net_gnd0,
S4_AXIS_TLAST => net_gnd0,
S4_AXIS_TDATA => net_gnd32(0 to 31),
S4_AXIS_TVALID => net_gnd0,
S4_AXIS_TREADY => open,
M5_AXIS_TLAST => open,
M5_AXIS_TDATA => open,
M5_AXIS_TVALID => open,
M5_AXIS_TREADY => net_gnd0,
S5_AXIS_TLAST => net_gnd0,
S5_AXIS_TDATA => net_gnd32(0 to 31),
S5_AXIS_TVALID => net_gnd0,
S5_AXIS_TREADY => open,
M6_AXIS_TLAST => open,
M6_AXIS_TDATA => open,
M6_AXIS_TVALID => open,
M6_AXIS_TREADY => net_gnd0,
S6_AXIS_TLAST => net_gnd0,
S6_AXIS_TDATA => net_gnd32(0 to 31),
S6_AXIS_TVALID => net_gnd0,
S6_AXIS_TREADY => open,
M7_AXIS_TLAST => open,
M7_AXIS_TDATA => open,
M7_AXIS_TVALID => open,
M7_AXIS_TREADY => net_gnd0,
S7_AXIS_TLAST => net_gnd0,
S7_AXIS_TDATA => net_gnd32(0 to 31),
S7_AXIS_TVALID => net_gnd0,
S7_AXIS_TREADY => open,
M8_AXIS_TLAST => open,
M8_AXIS_TDATA => open,
M8_AXIS_TVALID => open,
M8_AXIS_TREADY => net_gnd0,
S8_AXIS_TLAST => net_gnd0,
S8_AXIS_TDATA => net_gnd32(0 to 31),
S8_AXIS_TVALID => net_gnd0,
S8_AXIS_TREADY => open,
M9_AXIS_TLAST => open,
M9_AXIS_TDATA => open,
M9_AXIS_TVALID => open,
M9_AXIS_TREADY => net_gnd0,
S9_AXIS_TLAST => net_gnd0,
S9_AXIS_TDATA => net_gnd32(0 to 31),
S9_AXIS_TVALID => net_gnd0,
S9_AXIS_TREADY => open,
M10_AXIS_TLAST => open,
M10_AXIS_TDATA => open,
M10_AXIS_TVALID => open,
M10_AXIS_TREADY => net_gnd0,
S10_AXIS_TLAST => net_gnd0,
S10_AXIS_TDATA => net_gnd32(0 to 31),
S10_AXIS_TVALID => net_gnd0,
S10_AXIS_TREADY => open,
M11_AXIS_TLAST => open,
M11_AXIS_TDATA => open,
M11_AXIS_TVALID => open,
M11_AXIS_TREADY => net_gnd0,
S11_AXIS_TLAST => net_gnd0,
S11_AXIS_TDATA => net_gnd32(0 to 31),
S11_AXIS_TVALID => net_gnd0,
S11_AXIS_TREADY => open,
M12_AXIS_TLAST => open,
M12_AXIS_TDATA => open,
M12_AXIS_TVALID => open,
M12_AXIS_TREADY => net_gnd0,
S12_AXIS_TLAST => net_gnd0,
S12_AXIS_TDATA => net_gnd32(0 to 31),
S12_AXIS_TVALID => net_gnd0,
S12_AXIS_TREADY => open,
M13_AXIS_TLAST => open,
M13_AXIS_TDATA => open,
M13_AXIS_TVALID => open,
M13_AXIS_TREADY => net_gnd0,
S13_AXIS_TLAST => net_gnd0,
S13_AXIS_TDATA => net_gnd32(0 to 31),
S13_AXIS_TVALID => net_gnd0,
S13_AXIS_TREADY => open,
M14_AXIS_TLAST => open,
M14_AXIS_TDATA => open,
M14_AXIS_TVALID => open,
M14_AXIS_TREADY => net_gnd0,
S14_AXIS_TLAST => net_gnd0,
S14_AXIS_TDATA => net_gnd32(0 to 31),
S14_AXIS_TVALID => net_gnd0,
S14_AXIS_TREADY => open,
M15_AXIS_TLAST => open,
M15_AXIS_TDATA => open,
M15_AXIS_TVALID => open,
M15_AXIS_TREADY => net_gnd0,
S15_AXIS_TLAST => net_gnd0,
S15_AXIS_TDATA => net_gnd32(0 to 31),
S15_AXIS_TVALID => net_gnd0,
S15_AXIS_TREADY => open,
ICACHE_FSL_IN_CLK => open,
ICACHE_FSL_IN_READ => open,
ICACHE_FSL_IN_DATA => net_gnd32,
ICACHE_FSL_IN_CONTROL => net_gnd0,
ICACHE_FSL_IN_EXISTS => net_gnd0,
ICACHE_FSL_OUT_CLK => open,
ICACHE_FSL_OUT_WRITE => open,
ICACHE_FSL_OUT_DATA => open,
ICACHE_FSL_OUT_CONTROL => open,
ICACHE_FSL_OUT_FULL => net_gnd0,
DCACHE_FSL_IN_CLK => open,
DCACHE_FSL_IN_READ => open,
DCACHE_FSL_IN_DATA => net_gnd32,
DCACHE_FSL_IN_CONTROL => net_gnd0,
DCACHE_FSL_IN_EXISTS => net_gnd0,
DCACHE_FSL_OUT_CLK => open,
DCACHE_FSL_OUT_WRITE => open,
DCACHE_FSL_OUT_DATA => open,
DCACHE_FSL_OUT_CONTROL => open,
DCACHE_FSL_OUT_FULL => net_gnd0
);
mb_plb : system_mb_plb_wrapper
port map (
PLB_Clk => clk_50_0000MHz,
SYS_Rst => sys_bus_reset(0),
PLB_Rst => open,
SPLB_Rst => mb_plb_SPLB_Rst,
MPLB_Rst => mb_plb_MPLB_Rst,
PLB_dcrAck => open,
PLB_dcrDBus => open,
DCR_ABus => net_gnd10,
DCR_DBus => net_gnd32,
DCR_Read => net_gnd0,
DCR_Write => net_gnd0,
M_ABus => mb_plb_M_ABus,
M_UABus => mb_plb_M_UABus,
M_BE => mb_plb_M_BE,
M_RNW => mb_plb_M_RNW,
M_abort => mb_plb_M_ABort,
M_busLock => mb_plb_M_busLock,
M_TAttribute => mb_plb_M_TAttribute,
M_lockErr => mb_plb_M_lockErr,
M_MSize => mb_plb_M_MSize,
M_priority => mb_plb_M_priority,
M_rdBurst => mb_plb_M_rdBurst,
M_request => mb_plb_M_request,
M_size => mb_plb_M_size,
M_type => mb_plb_M_type,
M_wrBurst => mb_plb_M_wrBurst,
M_wrDBus => mb_plb_M_wrDBus,
Sl_addrAck => mb_plb_Sl_addrAck,
Sl_MRdErr => mb_plb_Sl_MRdErr,
Sl_MWrErr => mb_plb_Sl_MWrErr,
Sl_MBusy => mb_plb_Sl_MBusy,
Sl_rdBTerm => mb_plb_Sl_rdBTerm,
Sl_rdComp => mb_plb_Sl_rdComp,
Sl_rdDAck => mb_plb_Sl_rdDAck,
Sl_rdDBus => mb_plb_Sl_rdDBus,
Sl_rdWdAddr => mb_plb_Sl_rdWdAddr,
Sl_rearbitrate => mb_plb_Sl_rearbitrate,
Sl_SSize => mb_plb_Sl_SSize,
Sl_wait => mb_plb_Sl_wait,
Sl_wrBTerm => mb_plb_Sl_wrBTerm,
Sl_wrComp => mb_plb_Sl_wrComp,
Sl_wrDAck => mb_plb_Sl_wrDAck,
Sl_MIRQ => mb_plb_Sl_MIRQ,
PLB_MIRQ => mb_plb_PLB_MIRQ,
PLB_ABus => mb_plb_PLB_ABus,
PLB_UABus => mb_plb_PLB_UABus,
PLB_BE => mb_plb_PLB_BE,
PLB_MAddrAck => mb_plb_PLB_MAddrAck,
PLB_MTimeout => mb_plb_PLB_MTimeout,
PLB_MBusy => mb_plb_PLB_MBusy,
PLB_MRdErr => mb_plb_PLB_MRdErr,
PLB_MWrErr => mb_plb_PLB_MWrErr,
PLB_MRdBTerm => mb_plb_PLB_MRdBTerm,
PLB_MRdDAck => mb_plb_PLB_MRdDAck,
PLB_MRdDBus => mb_plb_PLB_MRdDBus,
PLB_MRdWdAddr => mb_plb_PLB_MRdWdAddr,
PLB_MRearbitrate => mb_plb_PLB_MRearbitrate,
PLB_MWrBTerm => mb_plb_PLB_MWrBTerm,
PLB_MWrDAck => mb_plb_PLB_MWrDAck,
PLB_MSSize => mb_plb_PLB_MSSize,
PLB_PAValid => mb_plb_PLB_PAValid,
PLB_RNW => mb_plb_PLB_RNW,
PLB_SAValid => mb_plb_PLB_SAValid,
PLB_abort => mb_plb_PLB_abort,
PLB_busLock => mb_plb_PLB_busLock,
PLB_TAttribute => mb_plb_PLB_TAttribute,
PLB_lockErr => mb_plb_PLB_lockErr,
PLB_masterID => mb_plb_PLB_masterID,
PLB_MSize => mb_plb_PLB_MSize,
PLB_rdPendPri => mb_plb_PLB_rdPendPri,
PLB_wrPendPri => mb_plb_PLB_wrPendPri,
PLB_rdPendReq => mb_plb_PLB_rdPendReq,
PLB_wrPendReq => mb_plb_PLB_wrPendReq,
PLB_rdBurst => mb_plb_PLB_rdBurst,
PLB_rdPrim => mb_plb_PLB_rdPrim,
PLB_reqPri => mb_plb_PLB_reqPri,
PLB_size => mb_plb_PLB_size,
PLB_type => mb_plb_PLB_type,
PLB_wrBurst => mb_plb_PLB_wrBurst,
PLB_wrDBus => mb_plb_PLB_wrDBus,
PLB_wrPrim => mb_plb_PLB_wrPrim,
PLB_SaddrAck => open,
PLB_SMRdErr => open,
PLB_SMWrErr => open,
PLB_SMBusy => open,
PLB_SrdBTerm => open,
PLB_SrdComp => open,
PLB_SrdDAck => open,
PLB_SrdDBus => open,
PLB_SrdWdAddr => open,
PLB_Srearbitrate => open,
PLB_Sssize => open,
PLB_Swait => open,
PLB_SwrBTerm => open,
PLB_SwrComp => open,
PLB_SwrDAck => open,
Bus_Error_Det => open
);
ilmb : system_ilmb_wrapper
port map (
LMB_Clk => clk_50_0000MHz,
SYS_Rst => sys_bus_reset(0),
LMB_Rst => ilmb_LMB_Rst,
M_ABus => ilmb_M_ABus,
M_ReadStrobe => ilmb_M_ReadStrobe,
M_WriteStrobe => net_gnd0,
M_AddrStrobe => ilmb_M_AddrStrobe,
M_DBus => net_gnd32,
M_BE => net_gnd4,
Sl_DBus => ilmb_Sl_DBus,
Sl_Ready => ilmb_Sl_Ready(0 to 0),
Sl_Wait => ilmb_Sl_Wait(0 to 0),
Sl_UE => ilmb_Sl_UE(0 to 0),
Sl_CE => ilmb_Sl_CE(0 to 0),
LMB_ABus => ilmb_LMB_ABus,
LMB_ReadStrobe => ilmb_LMB_ReadStrobe,
LMB_WriteStrobe => ilmb_LMB_WriteStrobe,
LMB_AddrStrobe => ilmb_LMB_AddrStrobe,
LMB_ReadDBus => ilmb_LMB_ReadDBus,
LMB_WriteDBus => ilmb_LMB_WriteDBus,
LMB_Ready => ilmb_LMB_Ready,
LMB_Wait => ilmb_LMB_Wait,
LMB_UE => ilmb_LMB_UE,
LMB_CE => ilmb_LMB_CE,
LMB_BE => ilmb_LMB_BE
);
dlmb : system_dlmb_wrapper
port map (
LMB_Clk => clk_50_0000MHz,
SYS_Rst => sys_bus_reset(0),
LMB_Rst => dlmb_LMB_Rst,
M_ABus => dlmb_M_ABus,
M_ReadStrobe => dlmb_M_ReadStrobe,
M_WriteStrobe => dlmb_M_WriteStrobe,
M_AddrStrobe => dlmb_M_AddrStrobe,
M_DBus => dlmb_M_DBus,
M_BE => dlmb_M_BE,
Sl_DBus => dlmb_Sl_DBus,
Sl_Ready => dlmb_Sl_Ready(0 to 0),
Sl_Wait => dlmb_Sl_Wait(0 to 0),
Sl_UE => dlmb_Sl_UE(0 to 0),
Sl_CE => dlmb_Sl_CE(0 to 0),
LMB_ABus => dlmb_LMB_ABus,
LMB_ReadStrobe => dlmb_LMB_ReadStrobe,
LMB_WriteStrobe => dlmb_LMB_WriteStrobe,
LMB_AddrStrobe => dlmb_LMB_AddrStrobe,
LMB_ReadDBus => dlmb_LMB_ReadDBus,
LMB_WriteDBus => dlmb_LMB_WriteDBus,
LMB_Ready => dlmb_LMB_Ready,
LMB_Wait => dlmb_LMB_Wait,
LMB_UE => dlmb_LMB_UE,
LMB_CE => dlmb_LMB_CE,
LMB_BE => dlmb_LMB_BE
);
dlmb_cntlr : system_dlmb_cntlr_wrapper
port map (
LMB_Clk => clk_50_0000MHz,
LMB_Rst => dlmb_LMB_Rst,
LMB_ABus => dlmb_LMB_ABus,
LMB_WriteDBus => dlmb_LMB_WriteDBus,
LMB_AddrStrobe => dlmb_LMB_AddrStrobe,
LMB_ReadStrobe => dlmb_LMB_ReadStrobe,
LMB_WriteStrobe => dlmb_LMB_WriteStrobe,
LMB_BE => dlmb_LMB_BE,
Sl_DBus => dlmb_Sl_DBus,
Sl_Ready => dlmb_Sl_Ready(0),
Sl_Wait => dlmb_Sl_Wait(0),
Sl_UE => dlmb_Sl_UE(0),
Sl_CE => dlmb_Sl_CE(0),
LMB1_ABus => net_gnd32,
LMB1_WriteDBus => net_gnd32,
LMB1_AddrStrobe => net_gnd0,
LMB1_ReadStrobe => net_gnd0,
LMB1_WriteStrobe => net_gnd0,
LMB1_BE => net_gnd4,
Sl1_DBus => open,
Sl1_Ready => open,
Sl1_Wait => open,
Sl1_UE => open,
Sl1_CE => open,
LMB2_ABus => net_gnd32,
LMB2_WriteDBus => net_gnd32,
LMB2_AddrStrobe => net_gnd0,
LMB2_ReadStrobe => net_gnd0,
LMB2_WriteStrobe => net_gnd0,
LMB2_BE => net_gnd4,
Sl2_DBus => open,
Sl2_Ready => open,
Sl2_Wait => open,
Sl2_UE => open,
Sl2_CE => open,
LMB3_ABus => net_gnd32,
LMB3_WriteDBus => net_gnd32,
LMB3_AddrStrobe => net_gnd0,
LMB3_ReadStrobe => net_gnd0,
LMB3_WriteStrobe => net_gnd0,
LMB3_BE => net_gnd4,
Sl3_DBus => open,
Sl3_Ready => open,
Sl3_Wait => open,
Sl3_UE => open,
Sl3_CE => open,
BRAM_Rst_A => dlmb_port_BRAM_Rst,
BRAM_Clk_A => dlmb_port_BRAM_Clk,
BRAM_EN_A => dlmb_port_BRAM_EN,
BRAM_WEN_A => dlmb_port_BRAM_WEN,
BRAM_Addr_A => dlmb_port_BRAM_Addr,
BRAM_Din_A => dlmb_port_BRAM_Din,
BRAM_Dout_A => dlmb_port_BRAM_Dout,
Interrupt => open,
UE => open,
CE => open,
SPLB_CTRL_PLB_ABus => net_gnd32,
SPLB_CTRL_PLB_PAValid => net_gnd0,
SPLB_CTRL_PLB_masterID => net_gnd1(0 downto 0),
SPLB_CTRL_PLB_RNW => net_gnd0,
SPLB_CTRL_PLB_BE => net_gnd4,
SPLB_CTRL_PLB_size => net_gnd4,
SPLB_CTRL_PLB_type => net_gnd3(2 downto 0),
SPLB_CTRL_PLB_wrDBus => net_gnd32,
SPLB_CTRL_Sl_addrAck => open,
SPLB_CTRL_Sl_SSize => open,
SPLB_CTRL_Sl_wait => open,
SPLB_CTRL_Sl_rearbitrate => open,
SPLB_CTRL_Sl_wrDAck => open,
SPLB_CTRL_Sl_wrComp => open,
SPLB_CTRL_Sl_rdDBus => open,
SPLB_CTRL_Sl_rdDAck => open,
SPLB_CTRL_Sl_rdComp => open,
SPLB_CTRL_Sl_MBusy => open,
SPLB_CTRL_Sl_MWrErr => open,
SPLB_CTRL_Sl_MRdErr => open,
SPLB_CTRL_PLB_UABus => net_gnd32,
SPLB_CTRL_PLB_SAValid => net_gnd0,
SPLB_CTRL_PLB_rdPrim => net_gnd0,
SPLB_CTRL_PLB_wrPrim => net_gnd0,
SPLB_CTRL_PLB_abort => net_gnd0,
SPLB_CTRL_PLB_busLock => net_gnd0,
SPLB_CTRL_PLB_MSize => net_gnd2,
SPLB_CTRL_PLB_lockErr => net_gnd0,
SPLB_CTRL_PLB_wrBurst => net_gnd0,
SPLB_CTRL_PLB_rdBurst => net_gnd0,
SPLB_CTRL_PLB_wrPendReq => net_gnd0,
SPLB_CTRL_PLB_rdPendReq => net_gnd0,
SPLB_CTRL_PLB_wrPendPri => net_gnd2,
SPLB_CTRL_PLB_rdPendPri => net_gnd2,
SPLB_CTRL_PLB_reqPri => net_gnd2,
SPLB_CTRL_PLB_TAttribute => net_gnd16,
SPLB_CTRL_Sl_wrBTerm => open,
SPLB_CTRL_Sl_rdWdAddr => open,
SPLB_CTRL_Sl_rdBTerm => open,
SPLB_CTRL_Sl_MIRQ => open,
S_AXI_CTRL_ACLK => net_vcc0,
S_AXI_CTRL_ARESETN => net_gnd0,
S_AXI_CTRL_AWADDR => net_gnd32(0 to 31),
S_AXI_CTRL_AWVALID => net_gnd0,
S_AXI_CTRL_AWREADY => open,
S_AXI_CTRL_WDATA => net_gnd32(0 to 31),
S_AXI_CTRL_WSTRB => net_gnd4(0 to 3),
S_AXI_CTRL_WVALID => net_gnd0,
S_AXI_CTRL_WREADY => open,
S_AXI_CTRL_BRESP => open,
S_AXI_CTRL_BVALID => open,
S_AXI_CTRL_BREADY => net_gnd0,
S_AXI_CTRL_ARADDR => net_gnd32(0 to 31),
S_AXI_CTRL_ARVALID => net_gnd0,
S_AXI_CTRL_ARREADY => open,
S_AXI_CTRL_RDATA => open,
S_AXI_CTRL_RRESP => open,
S_AXI_CTRL_RVALID => open,
S_AXI_CTRL_RREADY => net_gnd0
);
ilmb_cntlr : system_ilmb_cntlr_wrapper
port map (
LMB_Clk => clk_50_0000MHz,
LMB_Rst => ilmb_LMB_Rst,
LMB_ABus => ilmb_LMB_ABus,
LMB_WriteDBus => ilmb_LMB_WriteDBus,
LMB_AddrStrobe => ilmb_LMB_AddrStrobe,
LMB_ReadStrobe => ilmb_LMB_ReadStrobe,
LMB_WriteStrobe => ilmb_LMB_WriteStrobe,
LMB_BE => ilmb_LMB_BE,
Sl_DBus => ilmb_Sl_DBus,
Sl_Ready => ilmb_Sl_Ready(0),
Sl_Wait => ilmb_Sl_Wait(0),
Sl_UE => ilmb_Sl_UE(0),
Sl_CE => ilmb_Sl_CE(0),
LMB1_ABus => net_gnd32,
LMB1_WriteDBus => net_gnd32,
LMB1_AddrStrobe => net_gnd0,
LMB1_ReadStrobe => net_gnd0,
LMB1_WriteStrobe => net_gnd0,
LMB1_BE => net_gnd4,
Sl1_DBus => open,
Sl1_Ready => open,
Sl1_Wait => open,
Sl1_UE => open,
Sl1_CE => open,
LMB2_ABus => net_gnd32,
LMB2_WriteDBus => net_gnd32,
LMB2_AddrStrobe => net_gnd0,
LMB2_ReadStrobe => net_gnd0,
LMB2_WriteStrobe => net_gnd0,
LMB2_BE => net_gnd4,
Sl2_DBus => open,
Sl2_Ready => open,
Sl2_Wait => open,
Sl2_UE => open,
Sl2_CE => open,
LMB3_ABus => net_gnd32,
LMB3_WriteDBus => net_gnd32,
LMB3_AddrStrobe => net_gnd0,
LMB3_ReadStrobe => net_gnd0,
LMB3_WriteStrobe => net_gnd0,
LMB3_BE => net_gnd4,
Sl3_DBus => open,
Sl3_Ready => open,
Sl3_Wait => open,
Sl3_UE => open,
Sl3_CE => open,
BRAM_Rst_A => ilmb_port_BRAM_Rst,
BRAM_Clk_A => ilmb_port_BRAM_Clk,
BRAM_EN_A => ilmb_port_BRAM_EN,
BRAM_WEN_A => ilmb_port_BRAM_WEN,
BRAM_Addr_A => ilmb_port_BRAM_Addr,
BRAM_Din_A => ilmb_port_BRAM_Din,
BRAM_Dout_A => ilmb_port_BRAM_Dout,
Interrupt => open,
UE => open,
CE => open,
SPLB_CTRL_PLB_ABus => net_gnd32,
SPLB_CTRL_PLB_PAValid => net_gnd0,
SPLB_CTRL_PLB_masterID => net_gnd1(0 downto 0),
SPLB_CTRL_PLB_RNW => net_gnd0,
SPLB_CTRL_PLB_BE => net_gnd4,
SPLB_CTRL_PLB_size => net_gnd4,
SPLB_CTRL_PLB_type => net_gnd3(2 downto 0),
SPLB_CTRL_PLB_wrDBus => net_gnd32,
SPLB_CTRL_Sl_addrAck => open,
SPLB_CTRL_Sl_SSize => open,
SPLB_CTRL_Sl_wait => open,
SPLB_CTRL_Sl_rearbitrate => open,
SPLB_CTRL_Sl_wrDAck => open,
SPLB_CTRL_Sl_wrComp => open,
SPLB_CTRL_Sl_rdDBus => open,
SPLB_CTRL_Sl_rdDAck => open,
SPLB_CTRL_Sl_rdComp => open,
SPLB_CTRL_Sl_MBusy => open,
SPLB_CTRL_Sl_MWrErr => open,
SPLB_CTRL_Sl_MRdErr => open,
SPLB_CTRL_PLB_UABus => net_gnd32,
SPLB_CTRL_PLB_SAValid => net_gnd0,
SPLB_CTRL_PLB_rdPrim => net_gnd0,
SPLB_CTRL_PLB_wrPrim => net_gnd0,
SPLB_CTRL_PLB_abort => net_gnd0,
SPLB_CTRL_PLB_busLock => net_gnd0,
SPLB_CTRL_PLB_MSize => net_gnd2,
SPLB_CTRL_PLB_lockErr => net_gnd0,
SPLB_CTRL_PLB_wrBurst => net_gnd0,
SPLB_CTRL_PLB_rdBurst => net_gnd0,
SPLB_CTRL_PLB_wrPendReq => net_gnd0,
SPLB_CTRL_PLB_rdPendReq => net_gnd0,
SPLB_CTRL_PLB_wrPendPri => net_gnd2,
SPLB_CTRL_PLB_rdPendPri => net_gnd2,
SPLB_CTRL_PLB_reqPri => net_gnd2,
SPLB_CTRL_PLB_TAttribute => net_gnd16,
SPLB_CTRL_Sl_wrBTerm => open,
SPLB_CTRL_Sl_rdWdAddr => open,
SPLB_CTRL_Sl_rdBTerm => open,
SPLB_CTRL_Sl_MIRQ => open,
S_AXI_CTRL_ACLK => net_vcc0,
S_AXI_CTRL_ARESETN => net_gnd0,
S_AXI_CTRL_AWADDR => net_gnd32(0 to 31),
S_AXI_CTRL_AWVALID => net_gnd0,
S_AXI_CTRL_AWREADY => open,
S_AXI_CTRL_WDATA => net_gnd32(0 to 31),
S_AXI_CTRL_WSTRB => net_gnd4(0 to 3),
S_AXI_CTRL_WVALID => net_gnd0,
S_AXI_CTRL_WREADY => open,
S_AXI_CTRL_BRESP => open,
S_AXI_CTRL_BVALID => open,
S_AXI_CTRL_BREADY => net_gnd0,
S_AXI_CTRL_ARADDR => net_gnd32(0 to 31),
S_AXI_CTRL_ARVALID => net_gnd0,
S_AXI_CTRL_ARREADY => open,
S_AXI_CTRL_RDATA => open,
S_AXI_CTRL_RRESP => open,
S_AXI_CTRL_RVALID => open,
S_AXI_CTRL_RREADY => net_gnd0
);
lmb_bram : system_lmb_bram_wrapper
port map (
BRAM_Rst_A => ilmb_port_BRAM_Rst,
BRAM_Clk_A => ilmb_port_BRAM_Clk,
BRAM_EN_A => ilmb_port_BRAM_EN,
BRAM_WEN_A => ilmb_port_BRAM_WEN,
BRAM_Addr_A => ilmb_port_BRAM_Addr,
BRAM_Din_A => ilmb_port_BRAM_Din,
BRAM_Dout_A => ilmb_port_BRAM_Dout,
BRAM_Rst_B => dlmb_port_BRAM_Rst,
BRAM_Clk_B => dlmb_port_BRAM_Clk,
BRAM_EN_B => dlmb_port_BRAM_EN,
BRAM_WEN_B => dlmb_port_BRAM_WEN,
BRAM_Addr_B => dlmb_port_BRAM_Addr,
BRAM_Din_B => dlmb_port_BRAM_Din,
BRAM_Dout_B => dlmb_port_BRAM_Dout
);
clock_generator_0 : system_clock_generator_0_wrapper
port map (
CLKIN => CLK_S,
CLKOUT0 => clk_50_0000MHz,
CLKOUT1 => open,
CLKOUT2 => open,
CLKOUT3 => open,
CLKOUT4 => open,
CLKOUT5 => open,
CLKOUT6 => open,
CLKOUT7 => open,
CLKOUT8 => open,
CLKOUT9 => open,
CLKOUT10 => open,
CLKOUT11 => open,
CLKOUT12 => open,
CLKOUT13 => open,
CLKOUT14 => open,
CLKOUT15 => open,
CLKFBIN => net_gnd0,
CLKFBOUT => open,
PSCLK => net_gnd0,
PSEN => net_gnd0,
PSINCDEC => net_gnd0,
PSDONE => open,
RST => sys_rst_s,
LOCKED => Dcm_all_locked
);
mdm_0 : system_mdm_0_wrapper
port map (
Interrupt => open,
Debug_SYS_Rst => Debug_SYS_Rst,
Ext_BRK => Ext_BRK,
Ext_NM_BRK => Ext_NM_BRK,
S_AXI_ACLK => net_gnd0,
S_AXI_ARESETN => net_gnd0,
S_AXI_AWADDR => net_gnd32(0 to 31),
S_AXI_AWVALID => net_gnd0,
S_AXI_AWREADY => open,
S_AXI_WDATA => net_gnd32(0 to 31),
S_AXI_WSTRB => net_gnd4(0 to 3),
S_AXI_WVALID => net_gnd0,
S_AXI_WREADY => open,
S_AXI_BRESP => open,
S_AXI_BVALID => open,
S_AXI_BREADY => net_gnd0,
S_AXI_ARADDR => net_gnd32(0 to 31),
S_AXI_ARVALID => net_gnd0,
S_AXI_ARREADY => open,
S_AXI_RDATA => open,
S_AXI_RRESP => open,
S_AXI_RVALID => open,
S_AXI_RREADY => net_gnd0,
SPLB_Clk => clk_50_0000MHz,
SPLB_Rst => mb_plb_SPLB_Rst(0),
PLB_ABus => mb_plb_PLB_ABus,
PLB_UABus => mb_plb_PLB_UABus,
PLB_PAValid => mb_plb_PLB_PAValid,
PLB_SAValid => mb_plb_PLB_SAValid,
PLB_rdPrim => mb_plb_PLB_rdPrim(0),
PLB_wrPrim => mb_plb_PLB_wrPrim(0),
PLB_masterID => mb_plb_PLB_masterID,
PLB_abort => mb_plb_PLB_abort,
PLB_busLock => mb_plb_PLB_busLock,
PLB_RNW => mb_plb_PLB_RNW,
PLB_BE => mb_plb_PLB_BE,
PLB_MSize => mb_plb_PLB_MSize,
PLB_size => mb_plb_PLB_size,
PLB_type => mb_plb_PLB_type,
PLB_lockErr => mb_plb_PLB_lockErr,
PLB_wrDBus => mb_plb_PLB_wrDBus,
PLB_wrBurst => mb_plb_PLB_wrBurst,
PLB_rdBurst => mb_plb_PLB_rdBurst,
PLB_wrPendReq => mb_plb_PLB_wrPendReq,
PLB_rdPendReq => mb_plb_PLB_rdPendReq,
PLB_wrPendPri => mb_plb_PLB_wrPendPri,
PLB_rdPendPri => mb_plb_PLB_rdPendPri,
PLB_reqPri => mb_plb_PLB_reqPri,
PLB_TAttribute => mb_plb_PLB_TAttribute,
Sl_addrAck => mb_plb_Sl_addrAck(0),
Sl_SSize => mb_plb_Sl_SSize(0 to 1),
Sl_wait => mb_plb_Sl_wait(0),
Sl_rearbitrate => mb_plb_Sl_rearbitrate(0),
Sl_wrDAck => mb_plb_Sl_wrDAck(0),
Sl_wrComp => mb_plb_Sl_wrComp(0),
Sl_wrBTerm => mb_plb_Sl_wrBTerm(0),
Sl_rdDBus => mb_plb_Sl_rdDBus(0 to 63),
Sl_rdWdAddr => mb_plb_Sl_rdWdAddr(0 to 3),
Sl_rdDAck => mb_plb_Sl_rdDAck(0),
Sl_rdComp => mb_plb_Sl_rdComp(0),
Sl_rdBTerm => mb_plb_Sl_rdBTerm(0),
Sl_MBusy => mb_plb_Sl_MBusy(0 to 6),
Sl_MWrErr => mb_plb_Sl_MWrErr(0 to 6),
Sl_MRdErr => mb_plb_Sl_MRdErr(0 to 6),
Sl_MIRQ => mb_plb_Sl_MIRQ(0 to 6),
Dbg_Clk_0 => microblaze_0_mdm_bus_Dbg_Clk,
Dbg_TDI_0 => microblaze_0_mdm_bus_Dbg_TDI,
Dbg_TDO_0 => microblaze_0_mdm_bus_Dbg_TDO,
Dbg_Reg_En_0 => microblaze_0_mdm_bus_Dbg_Reg_En,
Dbg_Capture_0 => microblaze_0_mdm_bus_Dbg_Capture,
Dbg_Shift_0 => microblaze_0_mdm_bus_Dbg_Shift,
Dbg_Update_0 => microblaze_0_mdm_bus_Dbg_Update,
Dbg_Rst_0 => microblaze_0_mdm_bus_Debug_Rst,
Dbg_Clk_1 => open,
Dbg_TDI_1 => open,
Dbg_TDO_1 => net_gnd0,
Dbg_Reg_En_1 => open,
Dbg_Capture_1 => open,
Dbg_Shift_1 => open,
Dbg_Update_1 => open,
Dbg_Rst_1 => open,
Dbg_Clk_2 => open,
Dbg_TDI_2 => open,
Dbg_TDO_2 => net_gnd0,
Dbg_Reg_En_2 => open,
Dbg_Capture_2 => open,
Dbg_Shift_2 => open,
Dbg_Update_2 => open,
Dbg_Rst_2 => open,
Dbg_Clk_3 => open,
Dbg_TDI_3 => open,
Dbg_TDO_3 => net_gnd0,
Dbg_Reg_En_3 => open,
Dbg_Capture_3 => open,
Dbg_Shift_3 => open,
Dbg_Update_3 => open,
Dbg_Rst_3 => open,
Dbg_Clk_4 => open,
Dbg_TDI_4 => open,
Dbg_TDO_4 => net_gnd0,
Dbg_Reg_En_4 => open,
Dbg_Capture_4 => open,
Dbg_Shift_4 => open,
Dbg_Update_4 => open,
Dbg_Rst_4 => open,
Dbg_Clk_5 => open,
Dbg_TDI_5 => open,
Dbg_TDO_5 => net_gnd0,
Dbg_Reg_En_5 => open,
Dbg_Capture_5 => open,
Dbg_Shift_5 => open,
Dbg_Update_5 => open,
Dbg_Rst_5 => open,
Dbg_Clk_6 => open,
Dbg_TDI_6 => open,
Dbg_TDO_6 => net_gnd0,
Dbg_Reg_En_6 => open,
Dbg_Capture_6 => open,
Dbg_Shift_6 => open,
Dbg_Update_6 => open,
Dbg_Rst_6 => open,
Dbg_Clk_7 => open,
Dbg_TDI_7 => open,
Dbg_TDO_7 => net_gnd0,
Dbg_Reg_En_7 => open,
Dbg_Capture_7 => open,
Dbg_Shift_7 => open,
Dbg_Update_7 => open,
Dbg_Rst_7 => open,
Dbg_Clk_8 => open,
Dbg_TDI_8 => open,
Dbg_TDO_8 => net_gnd0,
Dbg_Reg_En_8 => open,
Dbg_Capture_8 => open,
Dbg_Shift_8 => open,
Dbg_Update_8 => open,
Dbg_Rst_8 => open,
Dbg_Clk_9 => open,
Dbg_TDI_9 => open,
Dbg_TDO_9 => net_gnd0,
Dbg_Reg_En_9 => open,
Dbg_Capture_9 => open,
Dbg_Shift_9 => open,
Dbg_Update_9 => open,
Dbg_Rst_9 => open,
Dbg_Clk_10 => open,
Dbg_TDI_10 => open,
Dbg_TDO_10 => net_gnd0,
Dbg_Reg_En_10 => open,
Dbg_Capture_10 => open,
Dbg_Shift_10 => open,
Dbg_Update_10 => open,
Dbg_Rst_10 => open,
Dbg_Clk_11 => open,
Dbg_TDI_11 => open,
Dbg_TDO_11 => net_gnd0,
Dbg_Reg_En_11 => open,
Dbg_Capture_11 => open,
Dbg_Shift_11 => open,
Dbg_Update_11 => open,
Dbg_Rst_11 => open,
Dbg_Clk_12 => open,
Dbg_TDI_12 => open,
Dbg_TDO_12 => net_gnd0,
Dbg_Reg_En_12 => open,
Dbg_Capture_12 => open,
Dbg_Shift_12 => open,
Dbg_Update_12 => open,
Dbg_Rst_12 => open,
Dbg_Clk_13 => open,
Dbg_TDI_13 => open,
Dbg_TDO_13 => net_gnd0,
Dbg_Reg_En_13 => open,
Dbg_Capture_13 => open,
Dbg_Shift_13 => open,
Dbg_Update_13 => open,
Dbg_Rst_13 => open,
Dbg_Clk_14 => open,
Dbg_TDI_14 => open,
Dbg_TDO_14 => net_gnd0,
Dbg_Reg_En_14 => open,
Dbg_Capture_14 => open,
Dbg_Shift_14 => open,
Dbg_Update_14 => open,
Dbg_Rst_14 => open,
Dbg_Clk_15 => open,
Dbg_TDI_15 => open,
Dbg_TDO_15 => net_gnd0,
Dbg_Reg_En_15 => open,
Dbg_Capture_15 => open,
Dbg_Shift_15 => open,
Dbg_Update_15 => open,
Dbg_Rst_15 => open,
Dbg_Clk_16 => open,
Dbg_TDI_16 => open,
Dbg_TDO_16 => net_gnd0,
Dbg_Reg_En_16 => open,
Dbg_Capture_16 => open,
Dbg_Shift_16 => open,
Dbg_Update_16 => open,
Dbg_Rst_16 => open,
Dbg_Clk_17 => open,
Dbg_TDI_17 => open,
Dbg_TDO_17 => net_gnd0,
Dbg_Reg_En_17 => open,
Dbg_Capture_17 => open,
Dbg_Shift_17 => open,
Dbg_Update_17 => open,
Dbg_Rst_17 => open,
Dbg_Clk_18 => open,
Dbg_TDI_18 => open,
Dbg_TDO_18 => net_gnd0,
Dbg_Reg_En_18 => open,
Dbg_Capture_18 => open,
Dbg_Shift_18 => open,
Dbg_Update_18 => open,
Dbg_Rst_18 => open,
Dbg_Clk_19 => open,
Dbg_TDI_19 => open,
Dbg_TDO_19 => net_gnd0,
Dbg_Reg_En_19 => open,
Dbg_Capture_19 => open,
Dbg_Shift_19 => open,
Dbg_Update_19 => open,
Dbg_Rst_19 => open,
Dbg_Clk_20 => open,
Dbg_TDI_20 => open,
Dbg_TDO_20 => net_gnd0,
Dbg_Reg_En_20 => open,
Dbg_Capture_20 => open,
Dbg_Shift_20 => open,
Dbg_Update_20 => open,
Dbg_Rst_20 => open,
Dbg_Clk_21 => open,
Dbg_TDI_21 => open,
Dbg_TDO_21 => net_gnd0,
Dbg_Reg_En_21 => open,
Dbg_Capture_21 => open,
Dbg_Shift_21 => open,
Dbg_Update_21 => open,
Dbg_Rst_21 => open,
Dbg_Clk_22 => open,
Dbg_TDI_22 => open,
Dbg_TDO_22 => net_gnd0,
Dbg_Reg_En_22 => open,
Dbg_Capture_22 => open,
Dbg_Shift_22 => open,
Dbg_Update_22 => open,
Dbg_Rst_22 => open,
Dbg_Clk_23 => open,
Dbg_TDI_23 => open,
Dbg_TDO_23 => net_gnd0,
Dbg_Reg_En_23 => open,
Dbg_Capture_23 => open,
Dbg_Shift_23 => open,
Dbg_Update_23 => open,
Dbg_Rst_23 => open,
Dbg_Clk_24 => open,
Dbg_TDI_24 => open,
Dbg_TDO_24 => net_gnd0,
Dbg_Reg_En_24 => open,
Dbg_Capture_24 => open,
Dbg_Shift_24 => open,
Dbg_Update_24 => open,
Dbg_Rst_24 => open,
Dbg_Clk_25 => open,
Dbg_TDI_25 => open,
Dbg_TDO_25 => net_gnd0,
Dbg_Reg_En_25 => open,
Dbg_Capture_25 => open,
Dbg_Shift_25 => open,
Dbg_Update_25 => open,
Dbg_Rst_25 => open,
Dbg_Clk_26 => open,
Dbg_TDI_26 => open,
Dbg_TDO_26 => net_gnd0,
Dbg_Reg_En_26 => open,
Dbg_Capture_26 => open,
Dbg_Shift_26 => open,
Dbg_Update_26 => open,
Dbg_Rst_26 => open,
Dbg_Clk_27 => open,
Dbg_TDI_27 => open,
Dbg_TDO_27 => net_gnd0,
Dbg_Reg_En_27 => open,
Dbg_Capture_27 => open,
Dbg_Shift_27 => open,
Dbg_Update_27 => open,
Dbg_Rst_27 => open,
Dbg_Clk_28 => open,
Dbg_TDI_28 => open,
Dbg_TDO_28 => net_gnd0,
Dbg_Reg_En_28 => open,
Dbg_Capture_28 => open,
Dbg_Shift_28 => open,
Dbg_Update_28 => open,
Dbg_Rst_28 => open,
Dbg_Clk_29 => open,
Dbg_TDI_29 => open,
Dbg_TDO_29 => net_gnd0,
Dbg_Reg_En_29 => open,
Dbg_Capture_29 => open,
Dbg_Shift_29 => open,
Dbg_Update_29 => open,
Dbg_Rst_29 => open,
Dbg_Clk_30 => open,
Dbg_TDI_30 => open,
Dbg_TDO_30 => net_gnd0,
Dbg_Reg_En_30 => open,
Dbg_Capture_30 => open,
Dbg_Shift_30 => open,
Dbg_Update_30 => open,
Dbg_Rst_30 => open,
Dbg_Clk_31 => open,
Dbg_TDI_31 => open,
Dbg_TDO_31 => net_gnd0,
Dbg_Reg_En_31 => open,
Dbg_Capture_31 => open,
Dbg_Shift_31 => open,
Dbg_Update_31 => open,
Dbg_Rst_31 => open,
bscan_tdi => open,
bscan_reset => open,
bscan_shift => open,
bscan_update => open,
bscan_capture => open,
bscan_sel1 => open,
bscan_drck1 => open,
bscan_tdo1 => net_gnd0,
bscan_ext_tdi => net_gnd0,
bscan_ext_reset => net_gnd0,
bscan_ext_shift => net_gnd0,
bscan_ext_update => net_gnd0,
bscan_ext_capture => net_gnd0,
bscan_ext_sel => net_gnd0,
bscan_ext_drck => net_gnd0,
bscan_ext_tdo => open,
Ext_JTAG_DRCK => open,
Ext_JTAG_RESET => open,
Ext_JTAG_SEL => open,
Ext_JTAG_CAPTURE => open,
Ext_JTAG_SHIFT => open,
Ext_JTAG_UPDATE => open,
Ext_JTAG_TDI => open,
Ext_JTAG_TDO => net_gnd0
);
proc_sys_reset_0 : system_proc_sys_reset_0_wrapper
port map (
Slowest_sync_clk => clk_50_0000MHz,
Ext_Reset_In => sys_rst_s,
Aux_Reset_In => net_gnd0,
MB_Debug_Sys_Rst => Debug_SYS_Rst,
Core_Reset_Req_0 => net_gnd0,
Chip_Reset_Req_0 => net_gnd0,
System_Reset_Req_0 => net_gnd0,
Core_Reset_Req_1 => net_gnd0,
Chip_Reset_Req_1 => net_gnd0,
System_Reset_Req_1 => net_gnd0,
Dcm_locked => Dcm_all_locked,
RstcPPCresetcore_0 => open,
RstcPPCresetchip_0 => open,
RstcPPCresetsys_0 => open,
RstcPPCresetcore_1 => open,
RstcPPCresetchip_1 => open,
RstcPPCresetsys_1 => open,
MB_Reset => mb_reset,
Bus_Struct_Reset => sys_bus_reset(0 to 0),
Peripheral_Reset => sys_periph_reset(0 to 0),
Interconnect_aresetn => open,
Peripheral_aresetn => open
);
nfa_accept_samples_generic_hw_top_0 : system_nfa_accept_samples_generic_hw_top_0_wrapper
port map (
aclk => clk_50_0000MHz,
aresetn => sys_periph_reset(0),
indices_MPLB_Clk => clk_50_0000MHz,
indices_MPLB_Rst => mb_plb_MPLB_Rst(2),
indices_M_request => mb_plb_M_request(2),
indices_M_priority => mb_plb_M_priority(4 to 5),
indices_M_busLock => mb_plb_M_busLock(2),
indices_M_RNW => mb_plb_M_RNW(2),
indices_M_BE => mb_plb_M_BE(16 to 23),
indices_M_MSize => mb_plb_M_MSize(4 to 5),
indices_M_size => mb_plb_M_size(8 to 11),
indices_M_type => mb_plb_M_type(6 to 8),
indices_M_TAttribute => mb_plb_M_TAttribute(32 to 47),
indices_M_lockErr => mb_plb_M_lockErr(2),
indices_M_abort => mb_plb_M_ABort(2),
indices_M_UABus => mb_plb_M_UABus(64 to 95),
indices_M_ABus => mb_plb_M_ABus(64 to 95),
indices_M_wrDBus => mb_plb_M_wrDBus(128 to 191),
indices_M_wrBurst => mb_plb_M_wrBurst(2),
indices_M_rdBurst => mb_plb_M_rdBurst(2),
indices_PLB_MAddrAck => mb_plb_PLB_MAddrAck(2),
indices_PLB_MSSize => mb_plb_PLB_MSSize(4 to 5),
indices_PLB_MRearbitrate => mb_plb_PLB_MRearbitrate(2),
indices_PLB_MTimeout => mb_plb_PLB_MTimeout(2),
indices_PLB_MBusy => mb_plb_PLB_MBusy(2),
indices_PLB_MRdErr => mb_plb_PLB_MRdErr(2),
indices_PLB_MWrErr => mb_plb_PLB_MWrErr(2),
indices_PLB_MIRQ => mb_plb_PLB_MIRQ(2),
indices_PLB_MRdDBus => mb_plb_PLB_MRdDBus(128 to 191),
indices_PLB_MRdWdAddr => mb_plb_PLB_MRdWdAddr(8 to 11),
indices_PLB_MRdDAck => mb_plb_PLB_MRdDAck(2),
indices_PLB_MRdBTerm => mb_plb_PLB_MRdBTerm(2),
indices_PLB_MWrDAck => mb_plb_PLB_MWrDAck(2),
indices_PLB_MWrBTerm => mb_plb_PLB_MWrBTerm(2),
nfa_finals_buckets_MPLB_Clk => clk_50_0000MHz,
nfa_finals_buckets_MPLB_Rst => mb_plb_MPLB_Rst(3),
nfa_finals_buckets_M_request => mb_plb_M_request(3),
nfa_finals_buckets_M_priority => mb_plb_M_priority(6 to 7),
nfa_finals_buckets_M_busLock => mb_plb_M_busLock(3),
nfa_finals_buckets_M_RNW => mb_plb_M_RNW(3),
nfa_finals_buckets_M_BE => mb_plb_M_BE(24 to 31),
nfa_finals_buckets_M_MSize => mb_plb_M_MSize(6 to 7),
nfa_finals_buckets_M_size => mb_plb_M_size(12 to 15),
nfa_finals_buckets_M_type => mb_plb_M_type(9 to 11),
nfa_finals_buckets_M_TAttribute => mb_plb_M_TAttribute(48 to 63),
nfa_finals_buckets_M_lockErr => mb_plb_M_lockErr(3),
nfa_finals_buckets_M_abort => mb_plb_M_ABort(3),
nfa_finals_buckets_M_UABus => mb_plb_M_UABus(96 to 127),
nfa_finals_buckets_M_ABus => mb_plb_M_ABus(96 to 127),
nfa_finals_buckets_M_wrDBus => mb_plb_M_wrDBus(192 to 255),
nfa_finals_buckets_M_wrBurst => mb_plb_M_wrBurst(3),
nfa_finals_buckets_M_rdBurst => mb_plb_M_rdBurst(3),
nfa_finals_buckets_PLB_MAddrAck => mb_plb_PLB_MAddrAck(3),
nfa_finals_buckets_PLB_MSSize => mb_plb_PLB_MSSize(6 to 7),
nfa_finals_buckets_PLB_MRearbitrate => mb_plb_PLB_MRearbitrate(3),
nfa_finals_buckets_PLB_MTimeout => mb_plb_PLB_MTimeout(3),
nfa_finals_buckets_PLB_MBusy => mb_plb_PLB_MBusy(3),
nfa_finals_buckets_PLB_MRdErr => mb_plb_PLB_MRdErr(3),
nfa_finals_buckets_PLB_MWrErr => mb_plb_PLB_MWrErr(3),
nfa_finals_buckets_PLB_MIRQ => mb_plb_PLB_MIRQ(3),
nfa_finals_buckets_PLB_MRdDBus => mb_plb_PLB_MRdDBus(192 to 255),
nfa_finals_buckets_PLB_MRdWdAddr => mb_plb_PLB_MRdWdAddr(12 to 15),
nfa_finals_buckets_PLB_MRdDAck => mb_plb_PLB_MRdDAck(3),
nfa_finals_buckets_PLB_MRdBTerm => mb_plb_PLB_MRdBTerm(3),
nfa_finals_buckets_PLB_MWrDAck => mb_plb_PLB_MWrDAck(3),
nfa_finals_buckets_PLB_MWrBTerm => mb_plb_PLB_MWrBTerm(3),
nfa_forward_buckets_MPLB_Clk => clk_50_0000MHz,
nfa_forward_buckets_MPLB_Rst => mb_plb_MPLB_Rst(4),
nfa_forward_buckets_M_request => mb_plb_M_request(4),
nfa_forward_buckets_M_priority => mb_plb_M_priority(8 to 9),
nfa_forward_buckets_M_busLock => mb_plb_M_busLock(4),
nfa_forward_buckets_M_RNW => mb_plb_M_RNW(4),
nfa_forward_buckets_M_BE => mb_plb_M_BE(32 to 39),
nfa_forward_buckets_M_MSize => mb_plb_M_MSize(8 to 9),
nfa_forward_buckets_M_size => mb_plb_M_size(16 to 19),
nfa_forward_buckets_M_type => mb_plb_M_type(12 to 14),
nfa_forward_buckets_M_TAttribute => mb_plb_M_TAttribute(64 to 79),
nfa_forward_buckets_M_lockErr => mb_plb_M_lockErr(4),
nfa_forward_buckets_M_abort => mb_plb_M_ABort(4),
nfa_forward_buckets_M_UABus => mb_plb_M_UABus(128 to 159),
nfa_forward_buckets_M_ABus => mb_plb_M_ABus(128 to 159),
nfa_forward_buckets_M_wrDBus => mb_plb_M_wrDBus(256 to 319),
nfa_forward_buckets_M_wrBurst => mb_plb_M_wrBurst(4),
nfa_forward_buckets_M_rdBurst => mb_plb_M_rdBurst(4),
nfa_forward_buckets_PLB_MAddrAck => mb_plb_PLB_MAddrAck(4),
nfa_forward_buckets_PLB_MSSize => mb_plb_PLB_MSSize(8 to 9),
nfa_forward_buckets_PLB_MRearbitrate => mb_plb_PLB_MRearbitrate(4),
nfa_forward_buckets_PLB_MTimeout => mb_plb_PLB_MTimeout(4),
nfa_forward_buckets_PLB_MBusy => mb_plb_PLB_MBusy(4),
nfa_forward_buckets_PLB_MRdErr => mb_plb_PLB_MRdErr(4),
nfa_forward_buckets_PLB_MWrErr => mb_plb_PLB_MWrErr(4),
nfa_forward_buckets_PLB_MIRQ => mb_plb_PLB_MIRQ(4),
nfa_forward_buckets_PLB_MRdDBus => mb_plb_PLB_MRdDBus(256 to 319),
nfa_forward_buckets_PLB_MRdWdAddr => mb_plb_PLB_MRdWdAddr(16 to 19),
nfa_forward_buckets_PLB_MRdDAck => mb_plb_PLB_MRdDAck(4),
nfa_forward_buckets_PLB_MRdBTerm => mb_plb_PLB_MRdBTerm(4),
nfa_forward_buckets_PLB_MWrDAck => mb_plb_PLB_MWrDAck(4),
nfa_forward_buckets_PLB_MWrBTerm => mb_plb_PLB_MWrBTerm(4),
nfa_initials_buckets_MPLB_Clk => clk_50_0000MHz,
nfa_initials_buckets_MPLB_Rst => mb_plb_MPLB_Rst(5),
nfa_initials_buckets_M_request => mb_plb_M_request(5),
nfa_initials_buckets_M_priority => mb_plb_M_priority(10 to 11),
nfa_initials_buckets_M_busLock => mb_plb_M_busLock(5),
nfa_initials_buckets_M_RNW => mb_plb_M_RNW(5),
nfa_initials_buckets_M_BE => mb_plb_M_BE(40 to 47),
nfa_initials_buckets_M_MSize => mb_plb_M_MSize(10 to 11),
nfa_initials_buckets_M_size => mb_plb_M_size(20 to 23),
nfa_initials_buckets_M_type => mb_plb_M_type(15 to 17),
nfa_initials_buckets_M_TAttribute => mb_plb_M_TAttribute(80 to 95),
nfa_initials_buckets_M_lockErr => mb_plb_M_lockErr(5),
nfa_initials_buckets_M_abort => mb_plb_M_ABort(5),
nfa_initials_buckets_M_UABus => mb_plb_M_UABus(160 to 191),
nfa_initials_buckets_M_ABus => mb_plb_M_ABus(160 to 191),
nfa_initials_buckets_M_wrDBus => mb_plb_M_wrDBus(320 to 383),
nfa_initials_buckets_M_wrBurst => mb_plb_M_wrBurst(5),
nfa_initials_buckets_M_rdBurst => mb_plb_M_rdBurst(5),
nfa_initials_buckets_PLB_MAddrAck => mb_plb_PLB_MAddrAck(5),
nfa_initials_buckets_PLB_MSSize => mb_plb_PLB_MSSize(10 to 11),
nfa_initials_buckets_PLB_MRearbitrate => mb_plb_PLB_MRearbitrate(5),
nfa_initials_buckets_PLB_MTimeout => mb_plb_PLB_MTimeout(5),
nfa_initials_buckets_PLB_MBusy => mb_plb_PLB_MBusy(5),
nfa_initials_buckets_PLB_MRdErr => mb_plb_PLB_MRdErr(5),
nfa_initials_buckets_PLB_MWrErr => mb_plb_PLB_MWrErr(5),
nfa_initials_buckets_PLB_MIRQ => mb_plb_PLB_MIRQ(5),
nfa_initials_buckets_PLB_MRdDBus => mb_plb_PLB_MRdDBus(320 to 383),
nfa_initials_buckets_PLB_MRdWdAddr => mb_plb_PLB_MRdWdAddr(20 to 23),
nfa_initials_buckets_PLB_MRdDAck => mb_plb_PLB_MRdDAck(5),
nfa_initials_buckets_PLB_MRdBTerm => mb_plb_PLB_MRdBTerm(5),
nfa_initials_buckets_PLB_MWrDAck => mb_plb_PLB_MWrDAck(5),
nfa_initials_buckets_PLB_MWrBTerm => mb_plb_PLB_MWrBTerm(5),
sample_buffer_MPLB_Clk => clk_50_0000MHz,
sample_buffer_MPLB_Rst => mb_plb_MPLB_Rst(6),
sample_buffer_M_request => mb_plb_M_request(6),
sample_buffer_M_priority => mb_plb_M_priority(12 to 13),
sample_buffer_M_busLock => mb_plb_M_busLock(6),
sample_buffer_M_RNW => mb_plb_M_RNW(6),
sample_buffer_M_BE => mb_plb_M_BE(48 to 55),
sample_buffer_M_MSize => mb_plb_M_MSize(12 to 13),
sample_buffer_M_size => mb_plb_M_size(24 to 27),
sample_buffer_M_type => mb_plb_M_type(18 to 20),
sample_buffer_M_TAttribute => mb_plb_M_TAttribute(96 to 111),
sample_buffer_M_lockErr => mb_plb_M_lockErr(6),
sample_buffer_M_abort => mb_plb_M_ABort(6),
sample_buffer_M_UABus => mb_plb_M_UABus(192 to 223),
sample_buffer_M_ABus => mb_plb_M_ABus(192 to 223),
sample_buffer_M_wrDBus => mb_plb_M_wrDBus(384 to 447),
sample_buffer_M_wrBurst => mb_plb_M_wrBurst(6),
sample_buffer_M_rdBurst => mb_plb_M_rdBurst(6),
sample_buffer_PLB_MAddrAck => mb_plb_PLB_MAddrAck(6),
sample_buffer_PLB_MSSize => mb_plb_PLB_MSSize(12 to 13),
sample_buffer_PLB_MRearbitrate => mb_plb_PLB_MRearbitrate(6),
sample_buffer_PLB_MTimeout => mb_plb_PLB_MTimeout(6),
sample_buffer_PLB_MBusy => mb_plb_PLB_MBusy(6),
sample_buffer_PLB_MRdErr => mb_plb_PLB_MRdErr(6),
sample_buffer_PLB_MWrErr => mb_plb_PLB_MWrErr(6),
sample_buffer_PLB_MIRQ => mb_plb_PLB_MIRQ(6),
sample_buffer_PLB_MRdDBus => mb_plb_PLB_MRdDBus(384 to 447),
sample_buffer_PLB_MRdWdAddr => mb_plb_PLB_MRdWdAddr(24 to 27),
sample_buffer_PLB_MRdDAck => mb_plb_PLB_MRdDAck(6),
sample_buffer_PLB_MRdBTerm => mb_plb_PLB_MRdBTerm(6),
sample_buffer_PLB_MWrDAck => mb_plb_PLB_MWrDAck(6),
sample_buffer_PLB_MWrBTerm => mb_plb_PLB_MWrBTerm(6),
splb_slv0_SPLB_Clk => clk_50_0000MHz,
splb_slv0_SPLB_Rst => mb_plb_SPLB_Rst(1),
splb_slv0_PLB_ABus => mb_plb_PLB_ABus,
splb_slv0_PLB_UABus => mb_plb_PLB_UABus,
splb_slv0_PLB_PAValid => mb_plb_PLB_PAValid,
splb_slv0_PLB_SAValid => mb_plb_PLB_SAValid,
splb_slv0_PLB_rdPrim => mb_plb_PLB_rdPrim(1),
splb_slv0_PLB_wrPrim => mb_plb_PLB_wrPrim(1),
splb_slv0_PLB_masterID => mb_plb_PLB_masterID,
splb_slv0_PLB_abort => mb_plb_PLB_abort,
splb_slv0_PLB_busLock => mb_plb_PLB_busLock,
splb_slv0_PLB_RNW => mb_plb_PLB_RNW,
splb_slv0_PLB_BE => mb_plb_PLB_BE,
splb_slv0_PLB_MSize => mb_plb_PLB_MSize,
splb_slv0_PLB_size => mb_plb_PLB_size,
splb_slv0_PLB_type => mb_plb_PLB_type,
splb_slv0_PLB_lockErr => mb_plb_PLB_lockErr,
splb_slv0_PLB_wrDBus => mb_plb_PLB_wrDBus,
splb_slv0_PLB_wrBurst => mb_plb_PLB_wrBurst,
splb_slv0_PLB_rdBurst => mb_plb_PLB_rdBurst,
splb_slv0_PLB_wrPendReq => mb_plb_PLB_wrPendReq,
splb_slv0_PLB_rdPendReq => mb_plb_PLB_rdPendReq,
splb_slv0_PLB_wrPendPri => mb_plb_PLB_wrPendPri,
splb_slv0_PLB_rdPendPri => mb_plb_PLB_rdPendPri,
splb_slv0_PLB_reqPri => mb_plb_PLB_reqPri,
splb_slv0_PLB_TAttribute => mb_plb_PLB_TAttribute,
splb_slv0_Sl_addrAck => mb_plb_Sl_addrAck(1),
splb_slv0_Sl_SSize => mb_plb_Sl_SSize(2 to 3),
splb_slv0_Sl_wait => mb_plb_Sl_wait(1),
splb_slv0_Sl_rearbitrate => mb_plb_Sl_rearbitrate(1),
splb_slv0_Sl_wrDAck => mb_plb_Sl_wrDAck(1),
splb_slv0_Sl_wrComp => mb_plb_Sl_wrComp(1),
splb_slv0_Sl_wrBTerm => mb_plb_Sl_wrBTerm(1),
splb_slv0_Sl_rdDBus => mb_plb_Sl_rdDBus(64 to 127),
splb_slv0_Sl_rdWdAddr => mb_plb_Sl_rdWdAddr(4 to 7),
splb_slv0_Sl_rdDAck => mb_plb_Sl_rdDAck(1),
splb_slv0_Sl_rdComp => mb_plb_Sl_rdComp(1),
splb_slv0_Sl_rdBTerm => mb_plb_Sl_rdBTerm(1),
splb_slv0_Sl_MBusy => mb_plb_Sl_MBusy(7 to 13),
splb_slv0_Sl_MWrErr => mb_plb_Sl_MWrErr(7 to 13),
splb_slv0_Sl_MRdErr => mb_plb_Sl_MRdErr(7 to 13),
splb_slv0_Sl_MIRQ => mb_plb_Sl_MIRQ(7 to 13)
);
end architecture STRUCTURE;
| lgpl-3.0 | 5b96c6c95210041ff37c0bdf2cbc5a00 | 0.599052 | 2.916336 | false | false | false | false |
dcliche/mdsynth | rtl/src/clock_div.vhd | 1 | 3,190 | --===========================================================================
--
-- clock_div.vhd - Clock divider for System09
--
--===========================================================================
--
-- File name : clock_div.vhd
--
-- Entity name : clock_div
--
-- Purpose : Generates Clocks for System09
-- For BurchED B3-Spartan2+ and B5-X300
-- Divides the input clock which is normally 50MHz
-- Generates a 1/1 (50.0 MHz) SYS clock
-- Generates a 1/2 (25.0 MHz) VGA clock
-- Generates a 1/4 (12.5 MHz) CPU clock
--
-- Dependencies : ieee.Std_Logic_1164
-- ieee.std_logic_unsigned
-- ieee.std_logic_arith
-- ieee.numeric_std
--
-- Uses : IBUFG
-- BUFG
--
-- Author : John E. Kent
-- [email protected]
--
-- Copyright (C) 2003 - 2010 John Kent
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
--===========================================================================
--
-- Revision History:
--
--===========================================================================
--
-- Rev: Date: Author: Description:
--
-- 0.1 2008-09-07 John Kent Initial version
-- 0.2 2010-09-14 John Kent Updated header
--
--
library ieee;
use ieee.std_logic_1164.all;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use ieee.numeric_std.all;
--library unisim;
-- use unisim.vcomponents.all;
entity clock_div is
port(
clk_in : in std_Logic; -- System Clock input
sys_clk : out std_logic; -- System Clock Out (1/1)
vga_clk : out std_logic; -- VGA Pixel Clock Out (1/2)
cpu_clk : out std_logic -- CPU Clock Out (1/4)
);
end entity;
architecture RTL of clock_div is
signal div_count : std_logic_vector(1 downto 0);
component BUFG
port (
i: in std_logic;
o: out std_logic
);
end component;
--
-- Start instantiation
--
begin
--
-- 50 MHz SYS clock output
--
sys_clk_buffer : BUFG
port map(
i => clk_in,
o => sys_clk
);
--
-- 25 MHz VGA clock output
--
vga_clk_buffer : BUFG
port map(
i => div_count(0),
o => vga_clk
);
--
-- 12.5MHz CPU clock
--
cpu_clk_buffer : BUFG
port map(
i => div_count(1),
o => cpu_clk
);
--
-- Clock divider
--
clock_div : process( clk_in )
begin
if rising_edge( clk_in ) then
div_count <= div_count + "01";
end if;
end process;
end architecture;
| gpl-3.0 | 502add91b42eaa6f7c407064466630ba | 0.533229 | 3.633257 | false | false | false | false |
takeshineshiro/fpga_fibre_scan | HUCB2P0_150701/frontend/hilbert_filter.vhd | 1 | 7,378 |
-- optimized version of a 10 tap FIR hilbert filter
-- The impulse response is h={-0.1066 0 -0.1781 0 -0.5347 0 0.5347 0 0.1781 0 0.1066}
--
-- This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License
-- as published by the Free Software Foundation; either version 3 of the License, or (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied
-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License along with this program;
-- if not, see <http://www.gnu.org/licenses/>.
-- Package Definition
library ieee;
use ieee.std_logic_1164.all;
use IEEE.STD_LOGIC_arith.all;
package hilbert_filter_pkg is
component hilbert_filter
generic(
input_data_width : integer;
output_data_width : integer;
internal_data_width : integer
);
port(
clk : in std_logic;
clk_enable : in std_logic;
reset : in std_logic;
filter_in : in std_logic_vector(15 downto 0); -- sfix16_en15
filter_out : out std_logic_vector(15 downto 0) -- sfix16_en10
);
end component;
end hilbert_filter_pkg;
package body hilbert_filter_pkg is
end hilbert_filter_pkg;
-- Entity Definition
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.resize_tools_pkg.all;
entity hilbert_filter is
generic(
input_data_width : integer := 16;
output_data_width : integer := 16;
internal_data_width : integer := 16
);
port(
clk : in std_logic;
clk_enable : in std_logic;
reset : in std_logic;
filter_in : in std_logic_vector(15 downto 0); -- sfix16_en15
filter_out : out std_logic_vector(15 downto 0) -- sfix16_en10
);
end hilbert_filter;
architecture hilbert_filter_arch of hilbert_filter is
constant no_of_coefficients : integer := 3;
constant h0_real : real := -32.0/256.0; -- -0.106635588611691;
constant h2_real : real := -54.0/256.0;-- -0.178063554399423;
constant h4_real : real := -163.0/256.0;-- -0.534697271169593;
--constant h0_int : std_logic_vector(internal_data_width-1 downto 0) := std_logic_vector(to_signed(integer(h0_real * 2.0**(internal_data_width-1)),internal_data_width));
--constant h2_int : std_logic_vector(internal_data_width-1 downto 0) := std_logic_vector(to_signed(integer(h2_real * 2.0**(internal_data_width-1)),internal_data_width));
--constant h4_int : std_logic_vector(internal_data_width-1 downto 0) := std_logic_vector(to_signed(integer(h4_real * 2.0**(internal_data_width-1)),internal_data_width));
--************************************************************************
constant h0_int : std_logic_vector(internal_data_width-1 downto 0) := std_logic_vector(to_signed(integer(h0_real * 2.0**(internal_data_width-1)),internal_data_width));
constant h2_int : std_logic_vector(internal_data_width-1 downto 0) := std_logic_vector(to_signed(integer(h2_real * 2.0**(internal_data_width-1)),internal_data_width));
constant h4_int : std_logic_vector(internal_data_width-1 downto 0) := std_logic_vector(to_signed(integer(h4_real * 2.0**(internal_data_width-1)),internal_data_width));
--************************************************************************
type xmh_type is array(0 to no_of_coefficients-1) of std_logic_vector(internal_data_width-1 downto 0);
--*****************************************************************
--test signal
type test_type is array(0 to no_of_coefficients-1) of std_logic_vector(31 downto 0);
signal test_data : test_type;
---------------------------------------------------------------------------------------------------------
signal xmh : xmh_type; --x mult with coeff. h
signal xmhd : xmh_type; --xmh delayed one clock
signal xmhd0inv : std_logic_vector(internal_data_width-1 downto 0);
signal xmhd0invd : std_logic_vector(internal_data_width-1 downto 0);
signal xmhd0invdd : std_logic_vector(internal_data_width-1 downto 0);
type tmp_type is array(0 to no_of_coefficients) of std_logic_vector(internal_data_width-1 downto 0);
signal t : tmp_type; --temporary signal ater each addition
signal td : tmp_type; --t delayed one clock
signal tdd : tmp_type; --t delayed two clocks
signal y : std_logic_vector(internal_data_width-1 downto 0);
begin
--shift left remove the flag
--
-- xmh(0) <= std_logic_vector(shift_left(signed(resize_to_msb_trunc(filter_in,internal_data_width/2)) * signed(resize_to_msb_round(h0_int,internal_data_width/2)),1));
-- xmh(1) <= std_logic_vector(shift_left(signed(resize_to_msb_trunc(filter_in,internal_data_width/2)) * signed(resize_to_msb_round(h2_int,internal_data_width/2)),1));
-- xmh(2) <= std_logic_vector(shift_left(signed(resize_to_msb_trunc(filter_in,internal_data_width/2)) * signed(resize_to_msb_round(h4_int,internal_data_width/2)),1));
--*****************************************************************************************************
test_data(0) <= std_logic_vector(shift_left(signed(filter_in) * signed(h0_int),1));
test_data(1) <= std_logic_vector(shift_left(signed(filter_in) * signed(h2_int),1));
test_data(2) <= std_logic_vector(shift_left(signed(filter_in) * signed(h4_int),1));
-- test_data(0) <= std_logic_vector(signed(filter_in) * signed(h0_int));
-- test_data(1) <= std_logic_vector(signed(filter_in) * signed(h2_int));
-- test_data(2) <= std_logic_vector(signed(filter_in) * signed(h4_int));
xmh(0) <= test_data(0)(31 downto 16);
xmh(1) <= test_data(1)(31 downto 16);
xmh(2) <= test_data(2)(31 downto 16);
--**************************************************************************************************************************************************************
xmhd0inv <= std_logic_vector(to_signed(-1 * to_integer(signed(xmhd(0))),internal_data_width));
t(0) <= std_logic_vector(signed(xmhd0invdd) - signed(xmhd(1)));
t(1) <= std_logic_vector(signed(tdd(0)) - signed(xmhd(2)));
t(2) <= std_logic_vector(signed(tdd(1)) + signed(xmhd(2)));
t(3) <= std_logic_vector(signed(tdd(2)) + signed(xmhd(1)));
y <= std_logic_vector(signed(tdd(3)) + signed(xmhd(0)));
process (clk, reset)
begin
if reset = '1' then
for i in 0 to no_of_coefficients-1 loop
xmhd(i) <= (others => '0');
end loop;
for i in 0 to no_of_coefficients loop
td(i) <= (others => '0');
tdd(i) <= (others => '0');
end loop;
xmhd0invd <= (others => '0');
xmhd0invdd <= (others => '0');
filter_out <= (others => '0');
elsif clk'event and clk = '1' then
if clk_enable = '1' then
for i in 0 to no_of_coefficients-1 loop
xmhd(i) <= xmh(i);
end loop;
for i in 0 to no_of_coefficients loop
td(i) <= t(i);
tdd(i) <= td(i);
end loop;
xmhd0invd <= xmhd0inv; --delay one clock
xmhd0invdd <= xmhd0invd; --delay two clock
filter_out <= resize_to_msb_trunc(y,output_data_width);
end if;
end if;
end process;
end hilbert_filter_arch;
| apache-2.0 | 4f87cee433ed456b678efa561e48a363 | 0.59962 | 3.251653 | false | true | false | false |
grwlf/vsim | vhdl_ct/ct00299.vhd | 1 | 7,198 | -------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
-------------------------------------------------------------------------------
--
-- TEST NAME:
--
-- CT00299
--
-- AUTHOR:
--
-- A. Wilmot
--
-- TEST OBJECTIVES:
--
-- 7.2.1 (6)
-- 7.2.1 (7)
--
-- DESIGN UNIT ORDERING:
--
-- E00000(ARCH00299)
-- ENT00299_Test_Bench(ARCH00299_Test_Bench)
--
-- REVISION HISTORY:
--
-- 27-JUL-1987 - initial revision
--
-- NOTES:
--
-- self-checking
-- this test depends upon constraint checking; if no constraint errors
-- are raised; then the test has passed
--
use WORK.STANDARD_TYPES.all ;
architecture ARCH00299 of E00000 is
begin
P00299 :
process
constant boolean0 : boolean := false ;
constant boolean1 : boolean := true ;
variable bool, bool0 : boolean := true ;
constant i : integer := 3 ;
begin
bool0 := true ;
case bool0 is
when (((i /= 3) and ((boolean'val(i) = true) and (boolean'val(i) = true))) = false
and (((i /= 3) and (boolean'val(i) = true)) and (boolean'val(i) = true)) = false
and ((i = 3) and ((i /= 3) and (boolean'val(i) = true))) = false
and (((i = 3) and (i /= 3)) and (boolean'val(i) = true)) = false
and ((i = 3) and ((i = 3) and (i /= 3))) = false
and (((i = 3) and (i = 3)) and (i /= 3)) = false
and ((i = 3) and ((i = 3) and (i = 3))) = true
and (((i = 3) and (i = 3)) and (i = 3)) = true ) =>
bool := bool and true ;
when false =>
bool := false ;
end case ;
bool0 := true ;
case bool0 is
when (((i > 3) or ((i > 3) or (i > 3))) = false
and (((i > 3) or (i > 3)) or (i > 3)) = false
and ((i > 3) or ((i > 3) or (i <= 3))) = true
and (((i > 3) or (i > 3)) or (i <= 3)) = true
and ((i > 3) or ((i <= 3) or (boolean'val(i) = true))) = true
and (((i > 3) or (i <= 3)) or (boolean'val(i) = true)) = true
and ((i <= 3) or ((boolean'val(i) = true) or (boolean'val(i) = true))) = true
and (((i <= 3) or (boolean'val(i) = true)) or (boolean'val(i) = true)) = true ) =>
bool := bool and true ;
when false =>
bool := false ;
end case ;
bool0 := true ;
case bool0 is
when (((i < 3) or ((i < 3) and (boolean'val(i) = true))) = false
and (((i < 3) or (i < 3)) and (boolean'val(i) = true)) = false
and ((i < 3) or ((i >= 3) and (i < 3))) = false
and (((i < 3) or (i >= 3)) and (i < 3)) = false
and ((i < 3) or ((i >= 3) and (i >= 3))) = true
and (((i < 3) or (i >= 3)) and (i >= 3)) = true
and ((i >= 3) or ((boolean'val(i) = true) and (boolean'val(i) = true))) = true
and (((i >= 3) or (boolean'val(i) = true)) and (i < 3)) = false
and (((i >= 3) or (boolean'val(i) = true)) and (i >= 3)) = true ) =>
bool := bool and true ;
when false =>
bool := false ;
end case ;
bool0 := true ;
case bool0 is
when (((i /= 3) and ((boolean'val(i) = true) or (boolean'val(i) = true))) = false
and (((i /= 3) and (boolean'val(i) = true)) or (i /= 3)) = false
and (((i /= 3) and (boolean'val(i) = true)) or (i = 3)) = true
and ((i = 3) and ((i /= 3) or (i /= 3))) = false
and (((i = 3) and (i /= 3)) or (i /= 3)) = false
and ((i = 3) and ((i /= 3) or (i = 3))) = true
and (((i = 3) and (i /= 3)) or (i = 3)) = true
and ((i = 3) and ((i = 3) or (boolean'val(i) = true))) = true
and (((i = 3) and (i = 3)) or (boolean'val(i) = true)) = true ) =>
bool := bool and true ;
when false =>
bool := false ;
end case ;
--
bool0 := true ;
case bool0 is
when (((i /= 3) nand ((boolean'val(i) = true) nand (boolean'val(i) = true))) = true
and (((i /= 3) nand (boolean'val(i) = true)) nand (i /= 3)) = true
and ((i = 3) nand ((i /= 3) nand (boolean'val(i) = true))) = false
and (((i = 3) nand (i /= 3)) nand (i /= 3)) = true
and ((i = 3) nand ((i = 3) nand (i /= 3))) = false
and (((i = 3) nand (i = 3)) nand (i /= 3)) = true
and ((i = 3) nand ((i = 3) nand (i = 3))) = true
and (((i = 3) nand (i = 3)) nand (i = 3)) = true ) =>
bool := bool and true ;
when false =>
bool := false ;
end case ;
bool0 := true ;
case bool0 is
when (((i /= 3) nor ((i /= 3) nor (i /= 3))) = false
and (((i /= 3) nor (i /= 3)) nor (i /= 3)) = false
and ((i /= 3) nor ((i /= 3) nor (i = 3))) = true
and (((i /= 3) nor (i /= 3)) nor (i = 3)) = false
and ((i /= 3) nor ((i = 3) nor (boolean'val(i) = true))) = true
and (((i /= 3) nor (i = 3)) nor (i /= 3)) = true
and ((i = 3) nor ((boolean'val(i) = true) nor (boolean'val(i) = true))) = false
and (((i = 3) nor (boolean'val(i) = true)) nor (i /= 3)) = true) =>
bool := bool and true ;
when false =>
bool := false ;
end case ;
bool0 := true ;
case bool0 is
when (((i /= 3) nor ((i /= 3) nand (boolean'val(i) = true))) = false
and (((i /= 3) nor (i /= 3)) nand (i = 3)) = false
and ((i /= 3) nor ((i = 3) nand (i /= 3))) = false
and (((i /= 3) nor (i = 3)) nand (i /= 3)) = true
and ((i /= 3) nor ((i = 3) nand (i = 3))) = true
and (((i /= 3) nor (i = 3)) nand (i = 3)) = true
and ((i = 3) nor ((boolean'val(i) = true) nand (boolean'val(i) = true))) = false
and (((i = 3) nor (boolean'val(i) = true)) nand (i /= 3)) = true
and (((i = 3) nor (boolean'val(i) = true)) nand (i = 3)) = true ) =>
bool := bool and true ;
when false =>
bool := false ;
end case ;
bool0 := true ;
case bool0 is
when (((i /= 3) nand ((boolean'val(i) = true) nor (boolean'val(i) = true))) = true
and (((i /= 3) nand (boolean'val(i) = true)) nor (i /= 3)) = false
and (((i /= 3) nand (boolean'val(i) = true)) nor (i = 3)) = false
and ((i = 3) nand ((i /= 3) nor (i /= 3))) = false
and (((i = 3) nand (i /= 3)) nor (i /= 3)) = false
and ((i = 3) nand ((i /= 3) nor (i = 3))) = true
and (((i = 3) nand (i /= 3)) nor (i = 3)) = false
and ((i = 3) nand ((i = 3) nor (boolean'val(i) = true))) = true
and (((i = 3) nand (i /= 3)) nor (boolean'val(i) = true)) = false ) =>
bool := bool and true ;
when false =>
bool := false ;
end case ;
test_report ( "ARCH00299" ,
"Locally static boolean short circuiting" ,
bool ) ;
wait ;
end process P00299 ;
end ARCH00299 ;
entity ENT00299_Test_Bench is
end ENT00299_Test_Bench ;
architecture ARCH00299_Test_Bench of ENT00299_Test_Bench is
begin
L1:
block
component UUT
end component ;
for CIS1 : UUT use entity WORK.E00000 ( ARCH00299 ) ;
begin
CIS1 : UUT ;
end block L1 ;
end ARCH00299_Test_Bench ;
| gpl-3.0 | 465ad1b309487c3fa3aea9c4c7fe2777 | 0.439011 | 3.102586 | false | true | false | false |
grwlf/vsim | vhdl_ct/ct00440.vhd | 1 | 4,709 | -------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
-------------------------------------------------------------------------------
--
-- TEST NAME:
--
-- CT00440
--
-- AUTHOR:
--
-- A. Wilmot
--
-- TEST OBJECTIVES:
--
-- 7.2.4 (1)
-- 7.2.4 (4)
-- 7.2.4 (11)
-- 7.2.4 (12)
-- 7.2.4 (13)
--
-- DESIGN UNIT ORDERING:
--
-- ENT00440(ARCH00440)
-- ENT00440_Test_Bench(ARCH00440_Test_Bench)
--
-- REVISION HISTORY:
--
-- 29-JUL-1987 - initial revision
--
-- NOTES:
--
-- self-checking
--
use WORK.ARITHMETIC.ALL ;
entity ENT00440 is
generic (
i_int_1 : integer := c_int_1 ;
i_int_2 : integer := c_int_2 ;
i_t_int_1 : t_int := c_t_int_1 ;
i_t_int_2 : t_int := c_t_int_2 ;
i_st_int_1 : st_int := c_st_int_1 ;
i_st_int_2 : st_int := c_st_int_2
) ;
port ( locally_static_correct : out boolean ;
globally_static_correct : out boolean ;
dynamic_correct : out boolean ) ;
end ENT00440 ;
architecture ARCH00440 of ENT00440 is
constant c2_int_1 : integer :=
(-10) rem i_int_1 + i_int_1 rem i_int_2 + i_int_1 rem (i_int_1 - 1)
- i_int_2 rem (c_int_2 + 1) ;
constant c2_t_int_1 : t_int :=
(1) rem i_t_int_1 + (i_t_int_1) rem i_t_int_2 + (-i_t_int_1) rem 2 -
c_t_int_2 rem (i_t_int_2 - 1) ;
constant c2_st_int_1 : st_int :=
(-0) rem i_st_int_2 + i_t_int_1 rem (i_st_int_1) +
(i_st_int_1 rem i_t_int_2) - (c_st_int_2) rem i_t_int_2 ;
begin
process
variable bool : boolean := true ;
variable cons_correct, gen_correct, dyn_correct : boolean := true ;
--
variable v_int_1, v2_int_1 : integer := i_int_1 ;
variable v_int_2, v2_int_2 : integer := i_int_2 ;
variable v_t_int_1, v2_t_int_1 : t_int := i_t_int_1 ;
variable v_t_int_2, v2_t_int_2 : t_int := i_t_int_2 ;
variable v_st_int_1, v2_st_int_1 : st_int := i_st_int_1 ;
variable v_st_int_2, v2_st_int_2 : st_int := i_st_int_2 ;
--
begin
-- static expression
case bool is
when (
(-10) rem c_int_1 + c_int_1 rem c_int_2 + c_int_1 rem (c_int_1 - 1)
- c_int_2 rem (c_int_2 + 1) = 5 and
(1) rem c_t_int_1 + (c_t_int_1) rem c_t_int_2 + (-c_t_int_1) rem 2 -
c_t_int_2 rem (c_t_int_2 - 1) = 6 and
(-0) rem c_st_int_2 + c_t_int_1 rem (c_st_int_1) +
(c_st_int_1 rem c_t_int_2) - (c_st_int_2) rem c_t_int_2 = 3
) =>
null ;
when others =>
cons_correct := false ;
end case ;
-- generic expression
gen_correct := c2_int_1 = 5 and
c2_t_int_1 = 6 and
c2_st_int_1 = 3 ;
-- dynamic expression
v2_int_1 :=
(-10) rem v_int_1 + v_int_1 rem v_int_2 + v_int_1 rem (v_int_1 - 1)
- v_int_2 rem (i_int_2 + 1) ;
v2_t_int_1 :=
(1) rem v_t_int_1 + (v_t_int_1) rem v_t_int_2 + (-v_t_int_1) rem 2 -
i_t_int_2 rem (v_t_int_2 - 1) ;
v2_st_int_1 :=
(-0) rem v_st_int_2 + v_t_int_1 rem (v_st_int_1) +
(v_st_int_1 rem v_t_int_2) - (c_st_int_2) rem v_t_int_2 ;
dyn_correct := v2_int_1 = 5 and
v2_t_int_1 = 6 and
v2_st_int_1 = 3 ;
locally_static_correct <= cons_correct ;
globally_static_correct <= gen_correct ;
dynamic_correct <= dyn_correct ;
wait ;
end process ;
end ARCH00440 ;
use WORK.STANDARD_TYPES.all ;
entity ENT00440_Test_Bench is
end ENT00440_Test_Bench ;
architecture ARCH00440_Test_Bench of ENT00440_Test_Bench is
begin
L1:
block
signal locally_static_correct, globally_static_correct,
dynamic_correct : boolean := false ;
component UUT
port ( locally_static_correct : out boolean := false ;
globally_static_correct : out boolean := false ;
dynamic_correct : out boolean := false ) ;
end component ;
for CIS1 : UUT use entity WORK.ENT00440 ( ARCH00440 ) ;
begin
CIS1 : UUT
port map ( locally_static_correct,
globally_static_correct,
dynamic_correct ) ;
process ( locally_static_correct, globally_static_correct,
dynamic_correct )
begin
if locally_static_correct and globally_static_correct and
dynamic_correct then
test_report ( "ARCH00440" ,
"rem predefined for integer types" ,
true ) ;
end if ;
end process ;
end block L1 ;
end ARCH00440_Test_Bench ;
| gpl-3.0 | 7446eee5177ce0edaa13ccd8944a0d7c | 0.498407 | 2.871341 | false | true | false | false |
grwlf/vsim | vhdl_ct/ct00310.vhd | 1 | 41,883 | -------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
-------------------------------------------------------------------------------
--
-- TEST NAME:
--
-- CT00310
--
-- AUTHOR:
--
-- A. Wilmot
--
-- TEST OBJECTIVES:
--
-- 7.2.2 (1)
-- 7.2.2 (2)
-- 7.2.2 (6)
-- 7.2.2 (9)
-- 7.2.2 (10)
-- 7.2.2 (11)
--
-- DESIGN UNIT ORDERING:
--
-- ENT00310(ARCH00310)
-- GENERIC_STANDARD_TYPES(ARCH00310_1)
-- ENT00310_Test_Bench(ARCH00310_Test_Bench)
--
-- REVISION HISTORY:
--
-- 21-JUL-1987 - initial revision
--
-- NOTES:
--
-- self-checking
-- automatically generated
--
use WORK.STANDARD_TYPES.all ;
entity ENT00310 is
generic (
i_boolean_1 : boolean
:= c_boolean_1 ;
i_boolean_2 : boolean
:= c_boolean_2 ;
i_bit_1 : bit
:= c_bit_1 ;
i_bit_2 : bit
:= c_bit_2 ;
i_severity_level_1 : severity_level
:= c_severity_level_1 ;
i_severity_level_2 : severity_level
:= c_severity_level_2 ;
i_character_1 : character
:= c_character_1 ;
i_character_2 : character
:= c_character_2 ;
i_t_enum1_1 : t_enum1
:= c_t_enum1_1 ;
i_t_enum1_2 : t_enum1
:= c_t_enum1_2 ;
i_st_enum1_1 : st_enum1
:= c_st_enum1_1 ;
i_st_enum1_2 : st_enum1
:= c_st_enum1_2 ;
i_integer_1 : integer
:= c_integer_1 ;
i_integer_2 : integer
:= c_integer_2 ;
i_t_int1_1 : t_int1
:= c_t_int1_1 ;
i_t_int1_2 : t_int1
:= c_t_int1_2 ;
i_st_int1_1 : st_int1
:= c_st_int1_1 ;
i_st_int1_2 : st_int1
:= c_st_int1_2 ;
i_time_1 : time
:= c_time_1 ;
i_time_2 : time
:= c_time_2 ;
i_t_phys1_1 : t_phys1
:= c_t_phys1_1 ;
i_t_phys1_2 : t_phys1
:= c_t_phys1_2 ;
i_st_phys1_1 : st_phys1
:= c_st_phys1_1 ;
i_st_phys1_2 : st_phys1
:= c_st_phys1_2 ;
i_real_1 : real
:= c_real_1 ;
i_real_2 : real
:= c_real_2 ;
i_t_real1_1 : t_real1
:= c_t_real1_1 ;
i_t_real1_2 : t_real1
:= c_t_real1_2 ;
i_st_real1_1 : st_real1
:= c_st_real1_1 ;
i_st_real1_2 : st_real1
:= c_st_real1_2 ;
i_st_bit_vector_1 : st_bit_vector
:= c_st_bit_vector_1 ;
i_st_bit_vector_2 : st_bit_vector
:= c_st_bit_vector_2 ;
i_st_string_1 : st_string
:= c_st_string_1 ;
i_st_string_2 : st_string
:= c_st_string_2 ;
i_t_rec1_1 : t_rec1
:= c_t_rec1_1 ;
i_t_rec1_2 : t_rec1
:= c_t_rec1_2 ;
i_st_rec1_1 : st_rec1
:= c_st_rec1_1 ;
i_st_rec1_2 : st_rec1
:= c_st_rec1_2 ;
i_t_rec2_1 : t_rec2
:= c_t_rec2_1 ;
i_t_rec2_2 : t_rec2
:= c_t_rec2_2 ;
i_st_rec2_1 : st_rec2
:= c_st_rec2_1 ;
i_st_rec2_2 : st_rec2
:= c_st_rec2_2 ;
i_t_rec3_1 : t_rec3
:= c_t_rec3_1 ;
i_t_rec3_2 : t_rec3
:= c_t_rec3_2 ;
i_st_rec3_1 : st_rec3
:= c_st_rec3_1 ;
i_st_rec3_2 : st_rec3
:= c_st_rec3_2 ;
i_st_arr1_1 : st_arr1
:= c_st_arr1_1 ;
i_st_arr1_2 : st_arr1
:= c_st_arr1_2 ;
i_st_arr2_1 : st_arr2
:= c_st_arr2_1 ;
i_st_arr2_2 : st_arr2
:= c_st_arr2_2 ;
i_st_arr3_1 : st_arr3 := c_st_arr3_1 ;
i_st_arr3_2 : st_arr3 := c_st_arr3_2
) ;
port ( locally_static_correct : out boolean ;
globally_static_correct : out boolean ;
dynamic_correct : out boolean ) ;
end ENT00310 ;
architecture ARCH00310 of ENT00310 is
begin
process
variable bool : boolean := true ;
variable cons_correct, gen_correct, dyn_correct : boolean := true ;
variable v_boolean_1 : boolean
:= c_boolean_1 ;
variable v_boolean_2 : boolean
:= c_boolean_2 ;
variable v_bit_1 : bit
:= c_bit_1 ;
variable v_bit_2 : bit
:= c_bit_2 ;
variable v_severity_level_1 : severity_level
:= c_severity_level_1 ;
variable v_severity_level_2 : severity_level
:= c_severity_level_2 ;
variable v_character_1 : character
:= c_character_1 ;
variable v_character_2 : character
:= c_character_2 ;
variable v_t_enum1_1 : t_enum1
:= c_t_enum1_1 ;
variable v_t_enum1_2 : t_enum1
:= c_t_enum1_2 ;
variable v_st_enum1_1 : st_enum1
:= c_st_enum1_1 ;
variable v_st_enum1_2 : st_enum1
:= c_st_enum1_2 ;
variable v_integer_1 : integer
:= c_integer_1 ;
variable v_integer_2 : integer
:= c_integer_2 ;
variable v_t_int1_1 : t_int1
:= c_t_int1_1 ;
variable v_t_int1_2 : t_int1
:= c_t_int1_2 ;
variable v_st_int1_1 : st_int1
:= c_st_int1_1 ;
variable v_st_int1_2 : st_int1
:= c_st_int1_2 ;
variable v_time_1 : time
:= c_time_1 ;
variable v_time_2 : time
:= c_time_2 ;
variable v_t_phys1_1 : t_phys1
:= c_t_phys1_1 ;
variable v_t_phys1_2 : t_phys1
:= c_t_phys1_2 ;
variable v_st_phys1_1 : st_phys1
:= c_st_phys1_1 ;
variable v_st_phys1_2 : st_phys1
:= c_st_phys1_2 ;
variable v_real_1 : real
:= c_real_1 ;
variable v_real_2 : real
:= c_real_2 ;
variable v_t_real1_1 : t_real1
:= c_t_real1_1 ;
variable v_t_real1_2 : t_real1
:= c_t_real1_2 ;
variable v_st_real1_1 : st_real1
:= c_st_real1_1 ;
variable v_st_real1_2 : st_real1
:= c_st_real1_2 ;
variable v_st_bit_vector_1 : st_bit_vector
:= c_st_bit_vector_1 ;
variable v_st_bit_vector_2 : st_bit_vector
:= c_st_bit_vector_2 ;
variable v_st_string_1 : st_string
:= c_st_string_1 ;
variable v_st_string_2 : st_string
:= c_st_string_2 ;
variable v_t_rec1_1 : t_rec1
:= c_t_rec1_1 ;
variable v_t_rec1_2 : t_rec1
:= c_t_rec1_2 ;
variable v_st_rec1_1 : st_rec1
:= c_st_rec1_1 ;
variable v_st_rec1_2 : st_rec1
:= c_st_rec1_2 ;
variable v_t_rec2_1 : t_rec2
:= c_t_rec2_1 ;
variable v_t_rec2_2 : t_rec2
:= c_t_rec2_2 ;
variable v_st_rec2_1 : st_rec2
:= c_st_rec2_1 ;
variable v_st_rec2_2 : st_rec2
:= c_st_rec2_2 ;
variable v_t_rec3_1 : t_rec3
:= c_t_rec3_1 ;
variable v_t_rec3_2 : t_rec3
:= c_t_rec3_2 ;
variable v_st_rec3_1 : st_rec3
:= c_st_rec3_1 ;
variable v_st_rec3_2 : st_rec3
:= c_st_rec3_2 ;
variable v_st_arr1_1 : st_arr1
:= c_st_arr1_1 ;
variable v_st_arr1_2 : st_arr1
:= c_st_arr1_2 ;
variable v_st_arr2_1 : st_arr2
:= c_st_arr2_1 ;
variable v_st_arr2_2 : st_arr2
:= c_st_arr2_2 ;
variable v_st_arr3_1 : st_arr3
:= c_st_arr3_1 ;
variable v_st_arr3_2 : st_arr3
:= c_st_arr3_2 ;
constant c2_boolean_1 : boolean :=
i_boolean_1 = c_boolean_1 and
i_boolean_1 /= i_boolean_2 and
not (i_boolean_1 = i_boolean_2)
;
constant c2_bit_1 : boolean :=
i_bit_1 = c_bit_1 and
i_bit_1 /= i_bit_2 and
not (i_bit_1 = i_bit_2)
;
constant c2_severity_level_1 : boolean :=
i_severity_level_1 = c_severity_level_1 and
i_severity_level_1 /= i_severity_level_2 and
not (i_severity_level_1 = i_severity_level_2)
;
constant c2_character_1 : boolean :=
i_character_1 = c_character_1 and
i_character_1 /= i_character_2 and
not (i_character_1 = i_character_2)
;
constant c2_t_enum1_1 : boolean :=
i_t_enum1_1 = c_t_enum1_1 and
i_t_enum1_1 /= i_t_enum1_2 and
not (i_t_enum1_1 = i_t_enum1_2)
;
constant c2_st_enum1_1 : boolean :=
i_st_enum1_1 = c_st_enum1_1 and
i_st_enum1_1 /= i_st_enum1_2 and
not (i_st_enum1_1 = i_st_enum1_2)
;
constant c2_integer_1 : boolean :=
i_integer_1 = c_integer_1 and
i_integer_1 /= i_integer_2 and
not (i_integer_1 = i_integer_2)
;
constant c2_t_int1_1 : boolean :=
i_t_int1_1 = c_t_int1_1 and
i_t_int1_1 /= i_t_int1_2 and
not (i_t_int1_1 = i_t_int1_2)
;
constant c2_st_int1_1 : boolean :=
i_st_int1_1 = c_st_int1_1 and
i_st_int1_1 /= i_st_int1_2 and
not (i_st_int1_1 = i_st_int1_2)
;
constant c2_time_1 : boolean :=
i_time_1 = c_time_1 and
i_time_1 /= i_time_2 and
not (i_time_1 = i_time_2)
;
constant c2_t_phys1_1 : boolean :=
i_t_phys1_1 = c_t_phys1_1 and
i_t_phys1_1 /= i_t_phys1_2 and
not (i_t_phys1_1 = i_t_phys1_2)
;
constant c2_st_phys1_1 : boolean :=
i_st_phys1_1 = c_st_phys1_1 and
i_st_phys1_1 /= i_st_phys1_2 and
not (i_st_phys1_1 = i_st_phys1_2)
;
constant c2_real_1 : boolean :=
i_real_1 = c_real_1 and
i_real_1 /= i_real_2 and
not (i_real_1 = i_real_2)
;
constant c2_t_real1_1 : boolean :=
i_t_real1_1 = c_t_real1_1 and
i_t_real1_1 /= i_t_real1_2 and
not (i_t_real1_1 = i_t_real1_2)
;
constant c2_st_real1_1 : boolean :=
i_st_real1_1 = c_st_real1_1 and
i_st_real1_1 /= i_st_real1_2 and
not (i_st_real1_1 = i_st_real1_2)
;
constant c2_st_bit_vector_1 : boolean :=
i_st_bit_vector_1 = c_st_bit_vector_1 and
i_st_bit_vector_1 /= i_st_bit_vector_2 and
not (i_st_bit_vector_1 = i_st_bit_vector_2)
;
constant c2_st_string_1 : boolean :=
i_st_string_1 = c_st_string_1 and
i_st_string_1 /= i_st_string_2 and
not (i_st_string_1 = i_st_string_2)
;
constant c2_t_rec1_1 : boolean :=
i_t_rec1_1 = c_t_rec1_1 and
i_t_rec1_1 /= i_t_rec1_2 and
not (i_t_rec1_1 = i_t_rec1_2)
;
constant c2_st_rec1_1 : boolean :=
i_st_rec1_1 = c_st_rec1_1 and
i_st_rec1_1 /= i_st_rec1_2 and
not (i_st_rec1_1 = i_st_rec1_2)
;
constant c2_t_rec2_1 : boolean :=
i_t_rec2_1 = c_t_rec2_1 and
i_t_rec2_1 /= i_t_rec2_2 and
not (i_t_rec2_1 = i_t_rec2_2)
;
constant c2_st_rec2_1 : boolean :=
i_st_rec2_1 = c_st_rec2_1 and
i_st_rec2_1 /= i_st_rec2_2 and
not (i_st_rec2_1 = i_st_rec2_2)
;
constant c2_t_rec3_1 : boolean :=
i_t_rec3_1 = c_t_rec3_1 and
i_t_rec3_1 /= i_t_rec3_2 and
not (i_t_rec3_1 = i_t_rec3_2)
;
constant c2_st_rec3_1 : boolean :=
i_st_rec3_1 = c_st_rec3_1 and
i_st_rec3_1 /= i_st_rec3_2 and
not (i_st_rec3_1 = i_st_rec3_2)
;
constant c2_st_arr1_1 : boolean :=
i_st_arr1_1 = c_st_arr1_1 and
i_st_arr1_1 /= i_st_arr1_2 and
not (i_st_arr1_1 = i_st_arr1_2)
;
constant c2_st_arr2_1 : boolean :=
i_st_arr2_1 = c_st_arr2_1 and
i_st_arr2_1 /= i_st_arr2_2 and
not (i_st_arr2_1 = i_st_arr2_2)
;
constant c2_st_arr3_1 : boolean :=
i_st_arr3_1 = c_st_arr3_1 and
i_st_arr3_1 /= i_st_arr3_2 and
not (i_st_arr3_1 = i_st_arr3_2)
;
begin
gen_correct := gen_correct and c2_boolean_1 = true ;
gen_correct := gen_correct and c2_bit_1 = true ;
gen_correct := gen_correct and c2_severity_level_1 = true ;
gen_correct := gen_correct and c2_character_1 = true ;
gen_correct := gen_correct and c2_t_enum1_1 = true ;
gen_correct := gen_correct and c2_st_enum1_1 = true ;
gen_correct := gen_correct and c2_integer_1 = true ;
gen_correct := gen_correct and c2_t_int1_1 = true ;
gen_correct := gen_correct and c2_st_int1_1 = true ;
gen_correct := gen_correct and c2_time_1 = true ;
gen_correct := gen_correct and c2_t_phys1_1 = true ;
gen_correct := gen_correct and c2_st_phys1_1 = true ;
gen_correct := gen_correct and c2_real_1 = true ;
gen_correct := gen_correct and c2_t_real1_1 = true ;
gen_correct := gen_correct and c2_st_real1_1 = true ;
gen_correct := gen_correct and c2_st_bit_vector_1 = true ;
gen_correct := gen_correct and c2_st_string_1 = true ;
gen_correct := gen_correct and c2_t_rec1_1 = true ;
gen_correct := gen_correct and c2_st_rec1_1 = true ;
gen_correct := gen_correct and c2_t_rec2_1 = true ;
gen_correct := gen_correct and c2_st_rec2_1 = true ;
gen_correct := gen_correct and c2_t_rec3_1 = true ;
gen_correct := gen_correct and c2_st_rec3_1 = true ;
gen_correct := gen_correct and c2_st_arr1_1 = true ;
gen_correct := gen_correct and c2_st_arr2_1 = true ;
gen_correct := gen_correct and c2_st_arr3_1 = true ;
dyn_correct := dyn_correct and
v_boolean_1 = c_boolean_1 and
v_boolean_1 /= v_boolean_2 and
not (v_boolean_1 = v_boolean_2)
;
dyn_correct := dyn_correct and
v_bit_1 = c_bit_1 and
v_bit_1 /= v_bit_2 and
not (v_bit_1 = v_bit_2)
;
dyn_correct := dyn_correct and
v_severity_level_1 = c_severity_level_1 and
v_severity_level_1 /= v_severity_level_2 and
not (v_severity_level_1 = v_severity_level_2)
;
dyn_correct := dyn_correct and
v_character_1 = c_character_1 and
v_character_1 /= v_character_2 and
not (v_character_1 = v_character_2)
;
dyn_correct := dyn_correct and
v_t_enum1_1 = c_t_enum1_1 and
v_t_enum1_1 /= v_t_enum1_2 and
not (v_t_enum1_1 = v_t_enum1_2)
;
dyn_correct := dyn_correct and
v_st_enum1_1 = c_st_enum1_1 and
v_st_enum1_1 /= v_st_enum1_2 and
not (v_st_enum1_1 = v_st_enum1_2)
;
dyn_correct := dyn_correct and
v_integer_1 = c_integer_1 and
v_integer_1 /= v_integer_2 and
not (v_integer_1 = v_integer_2)
;
dyn_correct := dyn_correct and
v_t_int1_1 = c_t_int1_1 and
v_t_int1_1 /= v_t_int1_2 and
not (v_t_int1_1 = v_t_int1_2)
;
dyn_correct := dyn_correct and
v_st_int1_1 = c_st_int1_1 and
v_st_int1_1 /= v_st_int1_2 and
not (v_st_int1_1 = v_st_int1_2)
;
dyn_correct := dyn_correct and
v_time_1 = c_time_1 and
v_time_1 /= v_time_2 and
not (v_time_1 = v_time_2)
;
dyn_correct := dyn_correct and
v_t_phys1_1 = c_t_phys1_1 and
v_t_phys1_1 /= v_t_phys1_2 and
not (v_t_phys1_1 = v_t_phys1_2)
;
dyn_correct := dyn_correct and
v_st_phys1_1 = c_st_phys1_1 and
v_st_phys1_1 /= v_st_phys1_2 and
not (v_st_phys1_1 = v_st_phys1_2)
;
dyn_correct := dyn_correct and
v_real_1 = c_real_1 and
v_real_1 /= v_real_2 and
not (v_real_1 = v_real_2)
;
dyn_correct := dyn_correct and
v_t_real1_1 = c_t_real1_1 and
v_t_real1_1 /= v_t_real1_2 and
not (v_t_real1_1 = v_t_real1_2)
;
dyn_correct := dyn_correct and
v_st_real1_1 = c_st_real1_1 and
v_st_real1_1 /= v_st_real1_2 and
not (v_st_real1_1 = v_st_real1_2)
;
dyn_correct := dyn_correct and
v_st_bit_vector_1 = c_st_bit_vector_1 and
v_st_bit_vector_1 /= v_st_bit_vector_2 and
not (v_st_bit_vector_1 = v_st_bit_vector_2)
;
dyn_correct := dyn_correct and
v_st_string_1 = c_st_string_1 and
v_st_string_1 /= v_st_string_2 and
not (v_st_string_1 = v_st_string_2)
;
dyn_correct := dyn_correct and
v_t_rec1_1 = c_t_rec1_1 and
v_t_rec1_1 /= v_t_rec1_2 and
not (v_t_rec1_1 = v_t_rec1_2)
;
dyn_correct := dyn_correct and
v_st_rec1_1 = c_st_rec1_1 and
v_st_rec1_1 /= v_st_rec1_2 and
not (v_st_rec1_1 = v_st_rec1_2)
;
dyn_correct := dyn_correct and
v_t_rec2_1 = c_t_rec2_1 and
v_t_rec2_1 /= v_t_rec2_2 and
not (v_t_rec2_1 = v_t_rec2_2)
;
dyn_correct := dyn_correct and
v_st_rec2_1 = c_st_rec2_1 and
v_st_rec2_1 /= v_st_rec2_2 and
not (v_st_rec2_1 = v_st_rec2_2)
;
dyn_correct := dyn_correct and
v_t_rec3_1 = c_t_rec3_1 and
v_t_rec3_1 /= v_t_rec3_2 and
not (v_t_rec3_1 = v_t_rec3_2)
;
dyn_correct := dyn_correct and
v_st_rec3_1 = c_st_rec3_1 and
v_st_rec3_1 /= v_st_rec3_2 and
not (v_st_rec3_1 = v_st_rec3_2)
;
dyn_correct := dyn_correct and
v_st_arr1_1 = c_st_arr1_1 and
v_st_arr1_1 /= v_st_arr1_2 and
not (v_st_arr1_1 = v_st_arr1_2)
;
dyn_correct := dyn_correct and
v_st_arr2_1 = c_st_arr2_1 and
v_st_arr2_1 /= v_st_arr2_2 and
not (v_st_arr2_1 = v_st_arr2_2)
;
dyn_correct := dyn_correct and
v_st_arr3_1 = c_st_arr3_1 and
v_st_arr3_1 /= v_st_arr3_2 and
not (v_st_arr3_1 = v_st_arr3_2)
;
locally_static_correct <= cons_correct ;
globally_static_correct <= gen_correct ;
dynamic_correct <= dyn_correct ;
wait;
end process ;
end ARCH00310 ;
architecture ARCH00310_1 of GENERIC_STANDARD_TYPES is
begin
B : block
generic (
i_boolean_1 : boolean
:= c_boolean_1 ;
i_boolean_2 : boolean
:= c_boolean_2 ;
i_bit_1 : bit
:= c_bit_1 ;
i_bit_2 : bit
:= c_bit_2 ;
i_severity_level_1 : severity_level
:= c_severity_level_1 ;
i_severity_level_2 : severity_level
:= c_severity_level_2 ;
i_character_1 : character
:= c_character_1 ;
i_character_2 : character
:= c_character_2 ;
i_t_enum1_1 : t_enum1
:= c_t_enum1_1 ;
i_t_enum1_2 : t_enum1
:= c_t_enum1_2 ;
i_st_enum1_1 : st_enum1
:= c_st_enum1_1 ;
i_st_enum1_2 : st_enum1
:= c_st_enum1_2 ;
i_integer_1 : integer
:= c_integer_1 ;
i_integer_2 : integer
:= c_integer_2 ;
i_t_int1_1 : t_int1
:= c_t_int1_1 ;
i_t_int1_2 : t_int1
:= c_t_int1_2 ;
i_st_int1_1 : st_int1
:= c_st_int1_1 ;
i_st_int1_2 : st_int1
:= c_st_int1_2 ;
i_time_1 : time
:= c_time_1 ;
i_time_2 : time
:= c_time_2 ;
i_t_phys1_1 : t_phys1
:= c_t_phys1_1 ;
i_t_phys1_2 : t_phys1
:= c_t_phys1_2 ;
i_st_phys1_1 : st_phys1
:= c_st_phys1_1 ;
i_st_phys1_2 : st_phys1
:= c_st_phys1_2 ;
i_real_1 : real
:= c_real_1 ;
i_real_2 : real
:= c_real_2 ;
i_t_real1_1 : t_real1
:= c_t_real1_1 ;
i_t_real1_2 : t_real1
:= c_t_real1_2 ;
i_st_real1_1 : st_real1
:= c_st_real1_1 ;
i_st_real1_2 : st_real1
:= c_st_real1_2 ;
i_st_bit_vector_1 : st_bit_vector
:= c_st_bit_vector_1 ;
i_st_bit_vector_2 : st_bit_vector
:= c_st_bit_vector_2 ;
i_st_string_1 : st_string
:= c_st_string_1 ;
i_st_string_2 : st_string
:= c_st_string_2 ;
i_t_rec1_1 : t_rec1
:= c_t_rec1_1 ;
i_t_rec1_2 : t_rec1
:= c_t_rec1_2 ;
i_st_rec1_1 : st_rec1
:= c_st_rec1_1 ;
i_st_rec1_2 : st_rec1
:= c_st_rec1_2 ;
i_t_rec2_1 : t_rec2
:= c_t_rec2_1 ;
i_t_rec2_2 : t_rec2
:= c_t_rec2_2 ;
i_st_rec2_1 : st_rec2
:= c_st_rec2_1 ;
i_st_rec2_2 : st_rec2
:= c_st_rec2_2 ;
i_t_rec3_1 : t_rec3
:= c_t_rec3_1 ;
i_t_rec3_2 : t_rec3
:= c_t_rec3_2 ;
i_st_rec3_1 : st_rec3
:= c_st_rec3_1 ;
i_st_rec3_2 : st_rec3
:= c_st_rec3_2 ;
i_st_arr1_1 : st_arr1
:= c_st_arr1_1 ;
i_st_arr1_2 : st_arr1
:= c_st_arr1_2 ;
i_st_arr2_1 : st_arr2
:= c_st_arr2_1 ;
i_st_arr2_2 : st_arr2
:= c_st_arr2_2 ;
i_st_arr3_1 : st_arr3 := c_st_arr3_1 ;
i_st_arr3_2 : st_arr3 := c_st_arr3_2
) ;
begin
process
variable bool : boolean := true ;
variable gen_correct, dyn_correct : boolean := true ;
variable v_boolean_1 : boolean
:= c_boolean_1 ;
variable v_boolean_2 : boolean
:= c_boolean_2 ;
variable v_bit_1 : bit
:= c_bit_1 ;
variable v_bit_2 : bit
:= c_bit_2 ;
variable v_severity_level_1 : severity_level
:= c_severity_level_1 ;
variable v_severity_level_2 : severity_level
:= c_severity_level_2 ;
variable v_character_1 : character
:= c_character_1 ;
variable v_character_2 : character
:= c_character_2 ;
variable v_t_enum1_1 : t_enum1
:= c_t_enum1_1 ;
variable v_t_enum1_2 : t_enum1
:= c_t_enum1_2 ;
variable v_st_enum1_1 : st_enum1
:= c_st_enum1_1 ;
variable v_st_enum1_2 : st_enum1
:= c_st_enum1_2 ;
variable v_integer_1 : integer
:= c_integer_1 ;
variable v_integer_2 : integer
:= c_integer_2 ;
variable v_t_int1_1 : t_int1
:= c_t_int1_1 ;
variable v_t_int1_2 : t_int1
:= c_t_int1_2 ;
variable v_st_int1_1 : st_int1
:= c_st_int1_1 ;
variable v_st_int1_2 : st_int1
:= c_st_int1_2 ;
variable v_time_1 : time
:= c_time_1 ;
variable v_time_2 : time
:= c_time_2 ;
variable v_t_phys1_1 : t_phys1
:= c_t_phys1_1 ;
variable v_t_phys1_2 : t_phys1
:= c_t_phys1_2 ;
variable v_st_phys1_1 : st_phys1
:= c_st_phys1_1 ;
variable v_st_phys1_2 : st_phys1
:= c_st_phys1_2 ;
variable v_real_1 : real
:= c_real_1 ;
variable v_real_2 : real
:= c_real_2 ;
variable v_t_real1_1 : t_real1
:= c_t_real1_1 ;
variable v_t_real1_2 : t_real1
:= c_t_real1_2 ;
variable v_st_real1_1 : st_real1
:= c_st_real1_1 ;
variable v_st_real1_2 : st_real1
:= c_st_real1_2 ;
variable v_st_bit_vector_1 : st_bit_vector
:= c_st_bit_vector_1 ;
variable v_st_bit_vector_2 : st_bit_vector
:= c_st_bit_vector_2 ;
variable v_st_string_1 : st_string
:= c_st_string_1 ;
variable v_st_string_2 : st_string
:= c_st_string_2 ;
variable v_t_rec1_1 : t_rec1
:= c_t_rec1_1 ;
variable v_t_rec1_2 : t_rec1
:= c_t_rec1_2 ;
variable v_st_rec1_1 : st_rec1
:= c_st_rec1_1 ;
variable v_st_rec1_2 : st_rec1
:= c_st_rec1_2 ;
variable v_t_rec2_1 : t_rec2
:= c_t_rec2_1 ;
variable v_t_rec2_2 : t_rec2
:= c_t_rec2_2 ;
variable v_st_rec2_1 : st_rec2
:= c_st_rec2_1 ;
variable v_st_rec2_2 : st_rec2
:= c_st_rec2_2 ;
variable v_t_rec3_1 : t_rec3
:= c_t_rec3_1 ;
variable v_t_rec3_2 : t_rec3
:= c_t_rec3_2 ;
variable v_st_rec3_1 : st_rec3
:= c_st_rec3_1 ;
variable v_st_rec3_2 : st_rec3
:= c_st_rec3_2 ;
variable v_st_arr1_1 : st_arr1
:= c_st_arr1_1 ;
variable v_st_arr1_2 : st_arr1
:= c_st_arr1_2 ;
variable v_st_arr2_1 : st_arr2
:= c_st_arr2_1 ;
variable v_st_arr2_2 : st_arr2
:= c_st_arr2_2 ;
variable v_st_arr3_1 : st_arr3
:= c_st_arr3_1 ;
variable v_st_arr3_2 : st_arr3
:= c_st_arr3_2 ;
constant c2_boolean_1 : boolean :=
i_boolean_1 = c_boolean_1 and
i_boolean_1 /= i_boolean_2 and
not (i_boolean_1 = i_boolean_2)
;
constant c2_bit_1 : boolean :=
i_bit_1 = c_bit_1 and
i_bit_1 /= i_bit_2 and
not (i_bit_1 = i_bit_2)
;
constant c2_severity_level_1 : boolean :=
i_severity_level_1 = c_severity_level_1 and
i_severity_level_1 /= i_severity_level_2 and
not (i_severity_level_1 = i_severity_level_2)
;
constant c2_character_1 : boolean :=
i_character_1 = c_character_1 and
i_character_1 /= i_character_2 and
not (i_character_1 = i_character_2)
;
constant c2_t_enum1_1 : boolean :=
i_t_enum1_1 = c_t_enum1_1 and
i_t_enum1_1 /= i_t_enum1_2 and
not (i_t_enum1_1 = i_t_enum1_2)
;
constant c2_st_enum1_1 : boolean :=
i_st_enum1_1 = c_st_enum1_1 and
i_st_enum1_1 /= i_st_enum1_2 and
not (i_st_enum1_1 = i_st_enum1_2)
;
constant c2_integer_1 : boolean :=
i_integer_1 = c_integer_1 and
i_integer_1 /= i_integer_2 and
not (i_integer_1 = i_integer_2)
;
constant c2_t_int1_1 : boolean :=
i_t_int1_1 = c_t_int1_1 and
i_t_int1_1 /= i_t_int1_2 and
not (i_t_int1_1 = i_t_int1_2)
;
constant c2_st_int1_1 : boolean :=
i_st_int1_1 = c_st_int1_1 and
i_st_int1_1 /= i_st_int1_2 and
not (i_st_int1_1 = i_st_int1_2)
;
constant c2_time_1 : boolean :=
i_time_1 = c_time_1 and
i_time_1 /= i_time_2 and
not (i_time_1 = i_time_2)
;
constant c2_t_phys1_1 : boolean :=
i_t_phys1_1 = c_t_phys1_1 and
i_t_phys1_1 /= i_t_phys1_2 and
not (i_t_phys1_1 = i_t_phys1_2)
;
constant c2_st_phys1_1 : boolean :=
i_st_phys1_1 = c_st_phys1_1 and
i_st_phys1_1 /= i_st_phys1_2 and
not (i_st_phys1_1 = i_st_phys1_2)
;
constant c2_real_1 : boolean :=
i_real_1 = c_real_1 and
i_real_1 /= i_real_2 and
not (i_real_1 = i_real_2)
;
constant c2_t_real1_1 : boolean :=
i_t_real1_1 = c_t_real1_1 and
i_t_real1_1 /= i_t_real1_2 and
not (i_t_real1_1 = i_t_real1_2)
;
constant c2_st_real1_1 : boolean :=
i_st_real1_1 = c_st_real1_1 and
i_st_real1_1 /= i_st_real1_2 and
not (i_st_real1_1 = i_st_real1_2)
;
constant c2_st_bit_vector_1 : boolean :=
i_st_bit_vector_1 = c_st_bit_vector_1 and
i_st_bit_vector_1 /= i_st_bit_vector_2 and
not (i_st_bit_vector_1 = i_st_bit_vector_2)
;
constant c2_st_string_1 : boolean :=
i_st_string_1 = c_st_string_1 and
i_st_string_1 /= i_st_string_2 and
not (i_st_string_1 = i_st_string_2)
;
constant c2_t_rec1_1 : boolean :=
i_t_rec1_1 = c_t_rec1_1 and
i_t_rec1_1 /= i_t_rec1_2 and
not (i_t_rec1_1 = i_t_rec1_2)
;
constant c2_st_rec1_1 : boolean :=
i_st_rec1_1 = c_st_rec1_1 and
i_st_rec1_1 /= i_st_rec1_2 and
not (i_st_rec1_1 = i_st_rec1_2)
;
constant c2_t_rec2_1 : boolean :=
i_t_rec2_1 = c_t_rec2_1 and
i_t_rec2_1 /= i_t_rec2_2 and
not (i_t_rec2_1 = i_t_rec2_2)
;
constant c2_st_rec2_1 : boolean :=
i_st_rec2_1 = c_st_rec2_1 and
i_st_rec2_1 /= i_st_rec2_2 and
not (i_st_rec2_1 = i_st_rec2_2)
;
constant c2_t_rec3_1 : boolean :=
i_t_rec3_1 = c_t_rec3_1 and
i_t_rec3_1 /= i_t_rec3_2 and
not (i_t_rec3_1 = i_t_rec3_2)
;
constant c2_st_rec3_1 : boolean :=
i_st_rec3_1 = c_st_rec3_1 and
i_st_rec3_1 /= i_st_rec3_2 and
not (i_st_rec3_1 = i_st_rec3_2)
;
constant c2_st_arr1_1 : boolean :=
i_st_arr1_1 = c_st_arr1_1 and
i_st_arr1_1 /= i_st_arr1_2 and
not (i_st_arr1_1 = i_st_arr1_2)
;
constant c2_st_arr2_1 : boolean :=
i_st_arr2_1 = c_st_arr2_1 and
i_st_arr2_1 /= i_st_arr2_2 and
not (i_st_arr2_1 = i_st_arr2_2)
;
constant c2_st_arr3_1 : boolean :=
i_st_arr3_1 = c_st_arr3_1 and
i_st_arr3_1 /= i_st_arr3_2 and
not (i_st_arr3_1 = i_st_arr3_2)
;
begin
dyn_correct := dyn_correct and
v_boolean_1 = c_boolean_1 and
v_boolean_1 /= v_boolean_2 and
not (v_boolean_1 = v_boolean_2)
;
dyn_correct := dyn_correct and
v_bit_1 = c_bit_1 and
v_bit_1 /= v_bit_2 and
not (v_bit_1 = v_bit_2)
;
dyn_correct := dyn_correct and
v_severity_level_1 = c_severity_level_1 and
v_severity_level_1 /= v_severity_level_2 and
not (v_severity_level_1 = v_severity_level_2)
;
dyn_correct := dyn_correct and
v_character_1 = c_character_1 and
v_character_1 /= v_character_2 and
not (v_character_1 = v_character_2)
;
dyn_correct := dyn_correct and
v_t_enum1_1 = c_t_enum1_1 and
v_t_enum1_1 /= v_t_enum1_2 and
not (v_t_enum1_1 = v_t_enum1_2)
;
dyn_correct := dyn_correct and
v_st_enum1_1 = c_st_enum1_1 and
v_st_enum1_1 /= v_st_enum1_2 and
not (v_st_enum1_1 = v_st_enum1_2)
;
dyn_correct := dyn_correct and
v_integer_1 = c_integer_1 and
v_integer_1 /= v_integer_2 and
not (v_integer_1 = v_integer_2)
;
dyn_correct := dyn_correct and
v_t_int1_1 = c_t_int1_1 and
v_t_int1_1 /= v_t_int1_2 and
not (v_t_int1_1 = v_t_int1_2)
;
dyn_correct := dyn_correct and
v_st_int1_1 = c_st_int1_1 and
v_st_int1_1 /= v_st_int1_2 and
not (v_st_int1_1 = v_st_int1_2)
;
dyn_correct := dyn_correct and
v_time_1 = c_time_1 and
v_time_1 /= v_time_2 and
not (v_time_1 = v_time_2)
;
dyn_correct := dyn_correct and
v_t_phys1_1 = c_t_phys1_1 and
v_t_phys1_1 /= v_t_phys1_2 and
not (v_t_phys1_1 = v_t_phys1_2)
;
dyn_correct := dyn_correct and
v_st_phys1_1 = c_st_phys1_1 and
v_st_phys1_1 /= v_st_phys1_2 and
not (v_st_phys1_1 = v_st_phys1_2)
;
dyn_correct := dyn_correct and
v_real_1 = c_real_1 and
v_real_1 /= v_real_2 and
not (v_real_1 = v_real_2)
;
dyn_correct := dyn_correct and
v_t_real1_1 = c_t_real1_1 and
v_t_real1_1 /= v_t_real1_2 and
not (v_t_real1_1 = v_t_real1_2)
;
dyn_correct := dyn_correct and
v_st_real1_1 = c_st_real1_1 and
v_st_real1_1 /= v_st_real1_2 and
not (v_st_real1_1 = v_st_real1_2)
;
dyn_correct := dyn_correct and
v_st_bit_vector_1 = c_st_bit_vector_1 and
v_st_bit_vector_1 /= v_st_bit_vector_2 and
not (v_st_bit_vector_1 = v_st_bit_vector_2)
;
dyn_correct := dyn_correct and
v_st_string_1 = c_st_string_1 and
v_st_string_1 /= v_st_string_2 and
not (v_st_string_1 = v_st_string_2)
;
dyn_correct := dyn_correct and
v_t_rec1_1 = c_t_rec1_1 and
v_t_rec1_1 /= v_t_rec1_2 and
not (v_t_rec1_1 = v_t_rec1_2)
;
dyn_correct := dyn_correct and
v_st_rec1_1 = c_st_rec1_1 and
v_st_rec1_1 /= v_st_rec1_2 and
not (v_st_rec1_1 = v_st_rec1_2)
;
dyn_correct := dyn_correct and
v_t_rec2_1 = c_t_rec2_1 and
v_t_rec2_1 /= v_t_rec2_2 and
not (v_t_rec2_1 = v_t_rec2_2)
;
dyn_correct := dyn_correct and
v_st_rec2_1 = c_st_rec2_1 and
v_st_rec2_1 /= v_st_rec2_2 and
not (v_st_rec2_1 = v_st_rec2_2)
;
dyn_correct := dyn_correct and
v_t_rec3_1 = c_t_rec3_1 and
v_t_rec3_1 /= v_t_rec3_2 and
not (v_t_rec3_1 = v_t_rec3_2)
;
dyn_correct := dyn_correct and
v_st_rec3_1 = c_st_rec3_1 and
v_st_rec3_1 /= v_st_rec3_2 and
not (v_st_rec3_1 = v_st_rec3_2)
;
dyn_correct := dyn_correct and
v_st_arr1_1 = c_st_arr1_1 and
v_st_arr1_1 /= v_st_arr1_2 and
not (v_st_arr1_1 = v_st_arr1_2)
;
dyn_correct := dyn_correct and
v_st_arr2_1 = c_st_arr2_1 and
v_st_arr2_1 /= v_st_arr2_2 and
not (v_st_arr2_1 = v_st_arr2_2)
;
dyn_correct := dyn_correct and
v_st_arr3_1 = c_st_arr3_1 and
v_st_arr3_1 /= v_st_arr3_2 and
not (v_st_arr3_1 = v_st_arr3_2)
;
if gen_correct and dyn_correct then
work.standard_types.test_report ( "ARCH&(TEST_NUM)" ,
"Relational operators are correctly predefined"
& " for generically sized types" ,
true ) ;
else
work.standard_types.test_report ( "ARCH&(TEST_NUM)" ,
"Relational operators are correctly predefined"
& " for generically sized types" ,
false ) ;
end if ;
wait;
end process ;
end block ;
end ARCH00310_1 ;
use WORK.STANDARD_TYPES.all ;
entity ENT00310_Test_Bench is
end ENT00310_Test_Bench ;
architecture ARCH00310_Test_Bench of ENT00310_Test_Bench is
begin
L1:
block
signal locally_static_correct, globally_static_correct,
dynamic_correct : boolean := false ;
component UUT
end component ;
component UUT_1
port ( locally_static_correct, globally_static_correct,
dynamic_correct : out boolean ) ;
end component ;
for CIS2 : UUT_1 use entity WORK.ENT00310 ( ARCH00310 ) ;
for CIS1 : UUT use entity
WORK.GENERIC_STANDARD_TYPES ( ARCH00310_1 ) ;
begin
CIS2 : UUT_1
port map ( locally_static_correct,
globally_static_correct,
dynamic_correct ) ;
CIS1 : UUT ;
process ( locally_static_correct, globally_static_correct,
dynamic_correct )
begin
if locally_static_correct and globally_static_correct and
dynamic_correct then
test_report ( "ARCH&(TEST_NUM)" ,
"Relational operators are correctly predefined"
& " for types" ,
true ) ;
end if ;
end process ;
end block L1 ;
end ARCH00310_Test_Bench ;
| gpl-3.0 | d5cbf7f0410441f1ecd4793b470286dc | 0.409116 | 3.155979 | false | false | false | false |
grwlf/vsim | vhdl_ct/ct00284.vhd | 1 | 8,465 | -- NEED RESULT: ARCH00284: Predefined enumeration types failed
-------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
-------------------------------------------------------------------------------
--
-- TEST NAME:
--
-- CT00284
--
-- AUTHOR:
--
-- D. Hyman
--
-- TEST OBJECTIVES:
--
-- 3.1.1.1 (1)
-- 3.1.1.1 (2)
-- 3.1.1.1 (3)
-- 3.1.1.1 (4)
--
-- DESIGN UNIT ORDERING:
--
-- E00000(ARCH00284)
-- ENT00284_Test_Bench(ARCH00284_Test_Bench)
--
-- REVISION HISTORY:
--
-- 21-JUL-1987 - initial revision
--
-- NOTES:
--
-- self-checking
--
use WORK.STANDARD_TYPES.all ;
architecture ARCH00284 of E00000 is
begin
P :
process
begin
test_report ( "ARCH00284" ,
"Predefined enumeration types" ,
(character'pos(NUL) = 0) and
(character'pos(SOH) = 1) and
(character'pos(STX) = 2) and
(character'pos(ETX) = 3) and
(character'pos(EOT) = 4) and
(character'pos(ENQ) = 5) and
(character'pos(ACK) = 6) and
(character'pos(BEL) = 7) and
(character'pos(BS ) = 8) and
(character'pos(HT ) = 9) and
(character'pos(LF ) = 10) and
(character'pos(VT ) = 11) and
(character'pos(FF ) = 12) and
(character'pos(CR ) = 13) and
(character'pos(SO ) = 14) and
(character'pos(SI ) = 15) and
(character'pos(DLE) = 16) and
(character'pos(DC1) = 17) and
(character'pos(DC2) = 18) and
(character'pos(DC3) = 19) and
(character'pos(DC4) = 20) and
(character'pos(NAK) = 21) and
(character'pos(SYN) = 22) and
(character'pos(ETB) = 23) and
(character'pos(CAN) = 24) and
(character'pos(EM ) = 25) and
(character'pos(SUB) = 26) and
(character'pos(ESC) = 27) and
(character'pos(FSP) = 28) and
(character'pos(GSP) = 29) and
(character'pos(RSP) = 30) and
(character'pos(USP) = 31) and
(character'pos(' ') = 32) and
(character'pos('!') = 33) and
(character'pos('"') = 34) and
(character'pos('#') = 35) and
(character'pos('$') = 36) and
(character'pos('%') = 37) and
(character'pos('&') = 38) and
(character'pos(''') = 39) and
(character'pos('(') = 40) and
(character'pos(')') = 41) and
(character'pos('*') = 42) and
(character'pos('+') = 43) and
(character'pos(',') = 44) and
(character'pos('-') = 45) and
(character'pos('.') = 46) and
(character'pos('/') = 47) and
(character'pos('0') = 48) and
(character'pos('1') = 49) and
(character'pos('2') = 50) and
(character'pos('3') = 51) and
(character'pos('4') = 52) and
(character'pos('5') = 53) and
(character'pos('6') = 54) and
(character'pos('7') = 55) and
(character'pos('8') = 56) and
(character'pos('9') = 57) and
(character'pos(':') = 58) and
(character'pos(';') = 59) and
(character'pos('<') = 60) and
(character'pos('=') = 61) and
(character'pos('>') = 62) and
(character'pos('?') = 63) and
(character'pos('@') = 64) and
(character'pos('A') = 65) and
(character'pos('B') = 66) and
(character'pos('C') = 67) and
(character'pos('D') = 68) and
(character'pos('E') = 69) and
(character'pos('F') = 70) and
(character'pos('G') = 71) and
(character'pos('H') = 72) and
(character'pos('I') = 73) and
(character'pos('J') = 74) and
(character'pos('K') = 75) and
(character'pos('L') = 76) and
(character'pos('M') = 77) and
(character'pos('N') = 78) and
(character'pos('O') = 79) and
(character'pos('P') = 80) and
(character'pos('Q') = 81) and
(character'pos('R') = 82) and
(character'pos('S') = 83) and
(character'pos('T') = 84) and
(character'pos('U') = 85) and
(character'pos('V') = 86) and
(character'pos('W') = 87) and
(character'pos('X') = 88) and
(character'pos('Y') = 89) and
(character'pos('Z') = 90) and
(character'pos('[') = 91) and
(character'pos('\') = 92) and
(character'pos(']') = 93) and
(character'pos('^') = 94) and
(character'pos('_') = 95) and
(character'pos('`') = 96) and
(character'pos('a') = 97) and
(character'pos('b') = 98) and
(character'pos('c') = 99) and
(character'pos('d') = 100) and
(character'pos('e') = 101) and
(character'pos('f') = 102) and
(character'pos('g') = 103) and
(character'pos('h') = 104) and
(character'pos('i') = 105) and
(character'pos('j') = 106) and
(character'pos('k') = 107) and
(character'pos('l') = 108) and
(character'pos('m') = 109) and
(character'pos('n') = 110) and
(character'pos('o') = 111) and
(character'pos('p') = 112) and
(character'pos('q') = 113) and
(character'pos('r') = 114) and
(character'pos('s') = 115) and
(character'pos('t') = 116) and
(character'pos('u') = 117) and
(character'pos('v') = 118) and
(character'pos('w') = 119) and
(character'pos('x') = 120) and
(character'pos('y') = 121) and
(character'pos('z') = 122) and
(character'pos('{') = 123) and
(character'pos('|') = 124) and
(character'pos('}') = 125) and
(character'pos('~') = 126) and
(character'pos(DEL) = 127) and
(character'pos(character'right) = 127) and
(bit'pos('0') = 0) and
(bit'pos('1') = 1) and
(bit'pos(bit'right) = 1) and
(boolean'pos(false) = 0) and
(boolean'pos(true) = 1) and
(boolean'pos(boolean'right) = 1) and
(severity_level'pos(NOTE) = 0) and
(severity_level'pos(WARNING) = 1) and
(severity_level'pos(ERROR) = 2) and
(severity_level'pos(FAILURE) = 3) and
(severity_level'pos(severity_level'right) = 3)
) ;
wait ;
end process P ;
end ARCH00284 ;
entity ENT00284_Test_Bench is
end ENT00284_Test_Bench ;
architecture ARCH00284_Test_Bench of ENT00284_Test_Bench is
begin
L1:
block
component UUT
end component ;
for CIS1 : UUT use entity WORK.E00000 ( ARCH00284 ) ;
begin
CIS1 : UUT ;
end block L1 ;
end ARCH00284_Test_Bench ;
| gpl-3.0 | d8498ba72ae21ac66eb704ca8a74f6ae | 0.385115 | 3.854736 | false | false | false | false |
grwlf/vsim | vhdl_ct/ct00424.vhd | 1 | 2,476 | -- NEED RESULT: ARCH00424: Identifiers passed
--
-- TEST NAME:
--
-- CT00424
--
-- AUTHOR:
--
-- D. Hyman
--
-- TEST OBJECTIVES:
--
-- 13.3 (1)
-- 13.3 (2)
-- 13.3 (3)
--
-- DESIGN UNIT ORDERING:
--
-- E00000(ARCH00424)
-- ENT00424_Test_Bench(ARCH00424_Test_Bench)
--
-- REVISION HISTORY:
--
-- 3-AUG-1987 - initial revision
--
-- NOTES:
--
-- self-checking
--
--
use WORK.STANDARD_TYPES.all ;
architecture ARCH00424 of E00000 is
begin
P :
PROCESS
-- these declarations verify that letter case is insignificant (13.3 (1))
TYpe XyZ is ( A1, A2, A3, A4, A5, A6, A7 ) ;
suBtyPe XYZ_subtype is xYz range a3 to a6 ;
cONStant xyz_C1 : XYZ_SUBTYpe := A4 ;
Constant Xyz_C2 : xyZ_SUBType := A6 ;
constaNT Xyz_C3 : XyZ_sUBType := xyz_Subtype'RighT ;
-- these declarations chack that input lines and identifiers can be
-- 132 chars long, and that all chars in a name are significant
-- (13.3 (2) and 13.3 (3))
variABle
X1234567890123456789012345678901234567890123456789012345678901234567890123456789012345678901234567890123456789012345678901234567890a
: inTeger := 25 ;
VAriABle
X1234567890123456789012345678901234567890123456789012345678901234567890123456789012345678901234567890123456789012345678901234567890b
: InTeger := 25 ;
begin
X1234567890123456789012345678901234567890123456789012345678901234567890123456789012345678901234567890123456789012345678901234567890A
:=
X1234567890123456789012345678901234567890123456789012345678901234567890123456789012345678901234567890123456789012345678901234567890B
+ 2 ;
Test_REPort ( "ARCH00424" ,
"Identifiers" ,
(xYz_C1 /= Xyz_c2) and
(XyZ_C2 = XYZ_C3) and
(
x1234567890123456789012345678901234567890123456789012345678901234567890123456789012345678901234567890123456789012345678901234567890A
= 25 + 2)
) ;
wait ;
end process P ;
end ARCH00424 ;
entitY ENT00424_Test_Bench iS
enD ENT00424_Test_Bench ;
ARCHitecture ARCH00424_Test_Bench of ENT00424_Test_Bench is
begiN
L1:
blOCk
cOMPonent UUT
end component ;
foR cis1 : uut USe Entity WORK.e00000 ( aRCH00424 ) ;
beGin
CIS1 : UUT ;
end block L1 ;
end aRCH00424_Test_Bench ;
| gpl-3.0 | 89f0d91796a61c8e13a6552e402ac24e | 0.642973 | 3.695522 | false | true | false | false |
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